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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND3B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__NAND3B_BEHAVIORAL_PP_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__nand3b (
Y ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y , B, not0_out, C );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND3B_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XOR3_2_V
`define SKY130_FD_SC_HD__XOR3_2_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog wrapper for xor3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__xor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__xor3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__xor3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__XOR3_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EDFXTP_1_V
`define SKY130_FD_SC_MS__EDFXTP_1_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Verilog wrapper for edfxtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__edfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__edfxtp_1 (
Q ,
CLK ,
D ,
DE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__edfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__edfxtp_1 (
Q ,
CLK,
D ,
DE
);
output Q ;
input CLK;
input D ;
input DE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__edfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__EDFXTP_1_V
|
// Generator : SpinalHDL v1.1.5 git head : 0310b2489a097f2b9de5535e02192d9ddd2764ae
// Date : 20/07/2018, 19:12:38
// Component : Murax
`define UartStopType_binary_sequancial_type [0:0]
`define UartStopType_binary_sequancial_ONE 1'b0
`define UartStopType_binary_sequancial_TWO 1'b1
`define AluBitwiseCtrlEnum_binary_sequancial_type [1:0]
`define AluBitwiseCtrlEnum_binary_sequancial_XOR_1 2'b00
`define AluBitwiseCtrlEnum_binary_sequancial_OR_1 2'b01
`define AluBitwiseCtrlEnum_binary_sequancial_AND_1 2'b10
`define AluBitwiseCtrlEnum_binary_sequancial_SRC1 2'b11
`define JtagState_binary_sequancial_type [3:0]
`define JtagState_binary_sequancial_RESET 4'b0000
`define JtagState_binary_sequancial_IDLE 4'b0001
`define JtagState_binary_sequancial_IR_SELECT 4'b0010
`define JtagState_binary_sequancial_IR_CAPTURE 4'b0011
`define JtagState_binary_sequancial_IR_SHIFT 4'b0100
`define JtagState_binary_sequancial_IR_EXIT1 4'b0101
`define JtagState_binary_sequancial_IR_PAUSE 4'b0110
`define JtagState_binary_sequancial_IR_EXIT2 4'b0111
`define JtagState_binary_sequancial_IR_UPDATE 4'b1000
`define JtagState_binary_sequancial_DR_SELECT 4'b1001
`define JtagState_binary_sequancial_DR_CAPTURE 4'b1010
`define JtagState_binary_sequancial_DR_SHIFT 4'b1011
`define JtagState_binary_sequancial_DR_EXIT1 4'b1100
`define JtagState_binary_sequancial_DR_PAUSE 4'b1101
`define JtagState_binary_sequancial_DR_EXIT2 4'b1110
`define JtagState_binary_sequancial_DR_UPDATE 4'b1111
`define Src1CtrlEnum_binary_sequancial_type [1:0]
`define Src1CtrlEnum_binary_sequancial_RS 2'b00
`define Src1CtrlEnum_binary_sequancial_IMU 2'b01
`define Src1CtrlEnum_binary_sequancial_FOUR 2'b10
`define UartCtrlTxState_binary_sequancial_type [2:0]
`define UartCtrlTxState_binary_sequancial_IDLE 3'b000
`define UartCtrlTxState_binary_sequancial_START 3'b001
`define UartCtrlTxState_binary_sequancial_DATA 3'b010
`define UartCtrlTxState_binary_sequancial_PARITY 3'b011
`define UartCtrlTxState_binary_sequancial_STOP 3'b100
`define Src2CtrlEnum_binary_sequancial_type [1:0]
`define Src2CtrlEnum_binary_sequancial_RS 2'b00
`define Src2CtrlEnum_binary_sequancial_IMI 2'b01
`define Src2CtrlEnum_binary_sequancial_IMS 2'b10
`define Src2CtrlEnum_binary_sequancial_PC 2'b11
`define ShiftCtrlEnum_binary_sequancial_type [1:0]
`define ShiftCtrlEnum_binary_sequancial_DISABLE_1 2'b00
`define ShiftCtrlEnum_binary_sequancial_SLL_1 2'b01
`define ShiftCtrlEnum_binary_sequancial_SRL_1 2'b10
`define ShiftCtrlEnum_binary_sequancial_SRA_1 2'b11
`define UartParityType_binary_sequancial_type [1:0]
`define UartParityType_binary_sequancial_NONE 2'b00
`define UartParityType_binary_sequancial_EVEN 2'b01
`define UartParityType_binary_sequancial_ODD 2'b10
`define BranchCtrlEnum_binary_sequancial_type [1:0]
`define BranchCtrlEnum_binary_sequancial_INC 2'b00
`define BranchCtrlEnum_binary_sequancial_B 2'b01
`define BranchCtrlEnum_binary_sequancial_JAL 2'b10
`define BranchCtrlEnum_binary_sequancial_JALR 2'b11
`define AluCtrlEnum_binary_sequancial_type [1:0]
`define AluCtrlEnum_binary_sequancial_ADD_SUB 2'b00
`define AluCtrlEnum_binary_sequancial_SLT_SLTU 2'b01
`define AluCtrlEnum_binary_sequancial_BITWISE 2'b10
`define UartCtrlRxState_binary_sequancial_type [2:0]
`define UartCtrlRxState_binary_sequancial_IDLE 3'b000
`define UartCtrlRxState_binary_sequancial_START 3'b001
`define UartCtrlRxState_binary_sequancial_DATA 3'b010
`define UartCtrlRxState_binary_sequancial_PARITY 3'b011
`define UartCtrlRxState_binary_sequancial_STOP 3'b100
`define EnvCtrlEnum_binary_sequancial_type [1:0]
`define EnvCtrlEnum_binary_sequancial_NONE 2'b00
`define EnvCtrlEnum_binary_sequancial_EBREAK 2'b01
`define EnvCtrlEnum_binary_sequancial_MRET 2'b10
module BufferCC (
input io_initial,
input io_dataIn,
output io_dataOut,
input io_mainClk,
input resetCtrl_systemReset);
reg buffers_0;
reg buffers_1;
assign io_dataOut = buffers_1;
always @ (posedge io_mainClk or posedge resetCtrl_systemReset) begin
if (resetCtrl_systemReset) begin
buffers_0 <= io_initial;
buffers_1 <= io_initial;
end else begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
end
endmodule
module BufferCC_1 (
input io_dataIn,
output io_dataOut,
input io_mainClk,
input resetCtrl_mainClkReset);
reg buffers_0;
reg buffers_1;
assign io_dataOut = buffers_1;
always @ (posedge io_mainClk) begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
endmodule
module UartCtrlTx (
input [2:0] io_configFrame_dataLength,
input `UartStopType_binary_sequancial_type io_configFrame_stop,
input `UartParityType_binary_sequancial_type io_configFrame_parity,
input io_samplingTick,
input io_write_valid,
output reg io_write_ready,
input [7:0] io_write_payload,
output io_txd,
input io_mainClk,
input resetCtrl_systemReset);
wire _zz_2;
wire [0:0] _zz_3;
wire [2:0] _zz_4;
wire [0:0] _zz_5;
wire [2:0] _zz_6;
reg clockDivider_counter_willIncrement;
wire clockDivider_counter_willClear;
reg [2:0] clockDivider_counter_valueNext;
reg [2:0] clockDivider_counter_value;
wire clockDivider_counter_willOverflowIfInc;
wire clockDivider_tick;
reg [2:0] tickCounter_value;
reg `UartCtrlTxState_binary_sequancial_type stateMachine_state;
reg stateMachine_parity;
reg stateMachine_txd;
reg _zz_1;
assign _zz_2 = (tickCounter_value == io_configFrame_dataLength);
assign _zz_3 = clockDivider_counter_willIncrement;
assign _zz_4 = {2'd0, _zz_3};
assign _zz_5 = ((io_configFrame_stop == `UartStopType_binary_sequancial_ONE) ? (1'b0) : (1'b1));
assign _zz_6 = {2'd0, _zz_5};
always @ (*) begin
clockDivider_counter_willIncrement = 1'b0;
if(io_samplingTick)begin
clockDivider_counter_willIncrement = 1'b1;
end
end
assign clockDivider_counter_willClear = 1'b0;
assign clockDivider_counter_willOverflowIfInc = (clockDivider_counter_value == (3'b100));
assign clockDivider_tick = (clockDivider_counter_willOverflowIfInc && clockDivider_counter_willIncrement);
always @ (*) begin
if(clockDivider_tick)begin
clockDivider_counter_valueNext = (3'b000);
end else begin
clockDivider_counter_valueNext = (clockDivider_counter_value + _zz_4);
end
if(clockDivider_counter_willClear)begin
clockDivider_counter_valueNext = (3'b000);
end
end
always @ (*) begin
stateMachine_txd = 1'b1;
io_write_ready = 1'b0;
case(stateMachine_state)
`UartCtrlTxState_binary_sequancial_IDLE : begin
end
`UartCtrlTxState_binary_sequancial_START : begin
stateMachine_txd = 1'b0;
end
`UartCtrlTxState_binary_sequancial_DATA : begin
stateMachine_txd = io_write_payload[tickCounter_value];
if(clockDivider_tick)begin
if(_zz_2)begin
io_write_ready = 1'b1;
end
end
end
`UartCtrlTxState_binary_sequancial_PARITY : begin
stateMachine_txd = stateMachine_parity;
end
default : begin
end
endcase
end
assign io_txd = _zz_1;
always @ (posedge io_mainClk or posedge resetCtrl_systemReset) begin
if (resetCtrl_systemReset) begin
clockDivider_counter_value <= (3'b000);
stateMachine_state <= `UartCtrlTxState_binary_sequancial_IDLE;
_zz_1 <= 1'b1;
end else begin
clockDivider_counter_value <= clockDivider_counter_valueNext;
case(stateMachine_state)
`UartCtrlTxState_binary_sequancial_IDLE : begin
if((io_write_valid && clockDivider_tick))begin
stateMachine_state <= `UartCtrlTxState_binary_sequancial_START;
end
end
`UartCtrlTxState_binary_sequancial_START : begin
if(clockDivider_tick)begin
stateMachine_state <= `UartCtrlTxState_binary_sequancial_DATA;
end
end
`UartCtrlTxState_binary_sequancial_DATA : begin
if(clockDivider_tick)begin
if(_zz_2)begin
if((io_configFrame_parity == `UartParityType_binary_sequancial_NONE))begin
stateMachine_state <= `UartCtrlTxState_binary_sequancial_STOP;
end else begin
stateMachine_state <= `UartCtrlTxState_binary_sequancial_PARITY;
end
end
end
end
`UartCtrlTxState_binary_sequancial_PARITY : begin
if(clockDivider_tick)begin
stateMachine_state <= `UartCtrlTxState_binary_sequancial_STOP;
end
end
default : begin
if(clockDivider_tick)begin
if((tickCounter_value == _zz_6))begin
stateMachine_state <= (io_write_valid ? `UartCtrlTxState_binary_sequancial_START : `UartCtrlTxState_binary_sequancial_IDLE);
end
end
end
endcase
_zz_1 <= stateMachine_txd;
end
end
always @ (posedge io_mainClk) begin
if(clockDivider_tick)begin
tickCounter_value <= (tickCounter_value + (3'b001));
end
if(clockDivider_tick)begin
stateMachine_parity <= (stateMachine_parity ^ stateMachine_txd);
end
case(stateMachine_state)
`UartCtrlTxState_binary_sequancial_IDLE : begin
end
`UartCtrlTxState_binary_sequancial_START : begin
if(clockDivider_tick)begin
stateMachine_parity <= (io_configFrame_parity == `UartParityType_binary_sequancial_ODD);
tickCounter_value <= (3'b000);
end
end
`UartCtrlTxState_binary_sequancial_DATA : begin
if(clockDivider_tick)begin
if(_zz_2)begin
tickCounter_value <= (3'b000);
end
end
end
`UartCtrlTxState_binary_sequancial_PARITY : begin
if(clockDivider_tick)begin
tickCounter_value <= (3'b000);
end
end
default : begin
end
endcase
end
endmodule
module UartCtrlRx (
input [2:0] io_configFrame_dataLength,
input `UartStopType_binary_sequancial_type io_configFrame_stop,
input `UartParityType_binary_sequancial_type io_configFrame_parity,
input io_samplingTick,
output io_read_valid,
output [7:0] io_read_payload,
input io_rxd,
input io_mainClk,
input resetCtrl_systemReset);
wire _zz_2;
wire _zz_3;
wire _zz_4;
wire _zz_5;
wire _zz_6;
wire [0:0] _zz_7;
wire [2:0] _zz_8;
wire sampler_syncroniser;
wire _zz_1;
wire sampler_samples_0;
reg sampler_samples_1;
reg sampler_samples_2;
reg sampler_value;
reg sampler_tick;
reg [2:0] bitTimer_counter;
reg bitTimer_tick;
reg [2:0] bitCounter_value;
reg `UartCtrlRxState_binary_sequancial_type stateMachine_state;
reg stateMachine_parity;
reg [7:0] stateMachine_shifter;
reg stateMachine_validReg;
assign _zz_4 = (sampler_tick && (! sampler_value));
assign _zz_5 = (bitCounter_value == io_configFrame_dataLength);
assign _zz_6 = (bitTimer_counter == (3'b000));
assign _zz_7 = ((io_configFrame_stop == `UartStopType_binary_sequancial_ONE) ? (1'b0) : (1'b1));
assign _zz_8 = {2'd0, _zz_7};
BufferCC bufferCC_3 (
.io_initial(_zz_2),
.io_dataIn(io_rxd),
.io_dataOut(_zz_3),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
assign _zz_2 = 1'b0;
assign sampler_syncroniser = _zz_3;
assign _zz_1 = 1'b1;
assign sampler_samples_0 = sampler_syncroniser;
always @ (*) begin
bitTimer_tick = 1'b0;
if(sampler_tick)begin
if(_zz_6)begin
bitTimer_tick = 1'b1;
end
end
end
assign io_read_valid = stateMachine_validReg;
assign io_read_payload = stateMachine_shifter;
always @ (posedge io_mainClk or posedge resetCtrl_systemReset) begin
if (resetCtrl_systemReset) begin
sampler_samples_1 <= _zz_1;
sampler_samples_2 <= _zz_1;
sampler_value <= 1'b1;
sampler_tick <= 1'b0;
stateMachine_state <= `UartCtrlRxState_binary_sequancial_IDLE;
stateMachine_validReg <= 1'b0;
end else begin
if(io_samplingTick)begin
sampler_samples_1 <= sampler_samples_0;
end
if(io_samplingTick)begin
sampler_samples_2 <= sampler_samples_1;
end
sampler_value <= (((1'b0 || ((1'b1 && sampler_samples_0) && sampler_samples_1)) || ((1'b1 && sampler_samples_0) && sampler_samples_2)) || ((1'b1 && sampler_samples_1) && sampler_samples_2));
sampler_tick <= io_samplingTick;
stateMachine_validReg <= 1'b0;
case(stateMachine_state)
`UartCtrlRxState_binary_sequancial_IDLE : begin
if(_zz_4)begin
stateMachine_state <= `UartCtrlRxState_binary_sequancial_START;
end
end
`UartCtrlRxState_binary_sequancial_START : begin
if(bitTimer_tick)begin
stateMachine_state <= `UartCtrlRxState_binary_sequancial_DATA;
if((sampler_value == 1'b1))begin
stateMachine_state <= `UartCtrlRxState_binary_sequancial_IDLE;
end
end
end
`UartCtrlRxState_binary_sequancial_DATA : begin
if(bitTimer_tick)begin
if(_zz_5)begin
if((io_configFrame_parity == `UartParityType_binary_sequancial_NONE))begin
stateMachine_state <= `UartCtrlRxState_binary_sequancial_STOP;
stateMachine_validReg <= 1'b1;
end else begin
stateMachine_state <= `UartCtrlRxState_binary_sequancial_PARITY;
end
end
end
end
`UartCtrlRxState_binary_sequancial_PARITY : begin
if(bitTimer_tick)begin
if((stateMachine_parity == sampler_value))begin
stateMachine_state <= `UartCtrlRxState_binary_sequancial_STOP;
stateMachine_validReg <= 1'b1;
end else begin
stateMachine_state <= `UartCtrlRxState_binary_sequancial_IDLE;
end
end
end
default : begin
if(bitTimer_tick)begin
if((! sampler_value))begin
stateMachine_state <= `UartCtrlRxState_binary_sequancial_IDLE;
end else begin
if((bitCounter_value == _zz_8))begin
stateMachine_state <= `UartCtrlRxState_binary_sequancial_IDLE;
end
end
end
end
endcase
end
end
always @ (posedge io_mainClk) begin
if(sampler_tick)begin
bitTimer_counter <= (bitTimer_counter - (3'b001));
if(_zz_6)begin
bitTimer_counter <= (3'b100);
end
end
if(bitTimer_tick)begin
bitCounter_value <= (bitCounter_value + (3'b001));
end
if(bitTimer_tick)begin
stateMachine_parity <= (stateMachine_parity ^ sampler_value);
end
case(stateMachine_state)
`UartCtrlRxState_binary_sequancial_IDLE : begin
if(_zz_4)begin
bitTimer_counter <= (3'b001);
end
end
`UartCtrlRxState_binary_sequancial_START : begin
if(bitTimer_tick)begin
bitCounter_value <= (3'b000);
stateMachine_parity <= (io_configFrame_parity == `UartParityType_binary_sequancial_ODD);
end
end
`UartCtrlRxState_binary_sequancial_DATA : begin
if(bitTimer_tick)begin
stateMachine_shifter[bitCounter_value] <= sampler_value;
if(_zz_5)begin
bitCounter_value <= (3'b000);
end
end
end
`UartCtrlRxState_binary_sequancial_PARITY : begin
if(bitTimer_tick)begin
bitCounter_value <= (3'b000);
end
end
default : begin
end
endcase
end
endmodule
module FlowCCByToggle (
input io_input_valid,
input io_input_payload_last,
input [0:0] io_input_payload_fragment,
output io_output_valid,
output io_output_payload_last,
output [0:0] io_output_payload_fragment,
input io_jtag_tck,
input io_mainClk,
input resetCtrl_mainClkReset);
wire _zz_4;
wire outHitSignal;
reg inputArea_target = 1;
reg inputArea_data_last;
reg [0:0] inputArea_data_fragment;
wire outputArea_target;
reg outputArea_hit;
wire outputArea_flow_valid;
wire outputArea_flow_payload_last;
wire [0:0] outputArea_flow_payload_fragment;
reg _zz_1;
reg _zz_2;
reg [0:0] _zz_3;
BufferCC_1 bufferCC_3 (
.io_dataIn(inputArea_target),
.io_dataOut(_zz_4),
.io_mainClk(io_mainClk),
.resetCtrl_mainClkReset(resetCtrl_mainClkReset)
);
assign outputArea_target = _zz_4;
assign outputArea_flow_valid = (outputArea_target != outputArea_hit);
assign outputArea_flow_payload_last = inputArea_data_last;
assign outputArea_flow_payload_fragment = inputArea_data_fragment;
assign io_output_valid = _zz_1;
assign io_output_payload_last = _zz_2;
assign io_output_payload_fragment = _zz_3;
always @ (posedge io_jtag_tck) begin
if(io_input_valid)begin
inputArea_target <= (! inputArea_target);
inputArea_data_last <= io_input_payload_last;
inputArea_data_fragment <= io_input_payload_fragment;
end
end
always @ (posedge io_mainClk) begin
outputArea_hit <= outputArea_target;
_zz_2 <= outputArea_flow_payload_last;
_zz_3 <= outputArea_flow_payload_fragment;
end
always @ (posedge io_mainClk or posedge resetCtrl_mainClkReset) begin
if (resetCtrl_mainClkReset) begin
_zz_1 <= 1'b0;
end else begin
_zz_1 <= outputArea_flow_valid;
end
end
endmodule
module UartCtrl (
input [2:0] io_config_frame_dataLength,
input `UartStopType_binary_sequancial_type io_config_frame_stop,
input `UartParityType_binary_sequancial_type io_config_frame_parity,
input [19:0] io_config_clockDivider,
input io_write_valid,
output io_write_ready,
input [7:0] io_write_payload,
output io_read_valid,
output [7:0] io_read_payload,
output io_uart_txd,
input io_uart_rxd,
input io_mainClk,
input resetCtrl_systemReset);
wire _zz_1;
wire _zz_2;
wire _zz_3;
wire [7:0] _zz_4;
reg [19:0] clockDivider_counter;
wire clockDivider_tick;
UartCtrlTx tx (
.io_configFrame_dataLength(io_config_frame_dataLength),
.io_configFrame_stop(io_config_frame_stop),
.io_configFrame_parity(io_config_frame_parity),
.io_samplingTick(clockDivider_tick),
.io_write_valid(io_write_valid),
.io_write_ready(_zz_1),
.io_write_payload(io_write_payload),
.io_txd(_zz_2),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
UartCtrlRx rx (
.io_configFrame_dataLength(io_config_frame_dataLength),
.io_configFrame_stop(io_config_frame_stop),
.io_configFrame_parity(io_config_frame_parity),
.io_samplingTick(clockDivider_tick),
.io_read_valid(_zz_3),
.io_read_payload(_zz_4),
.io_rxd(io_uart_rxd),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
assign clockDivider_tick = (clockDivider_counter == (20'b00000000000000000000));
assign io_write_ready = _zz_1;
assign io_read_valid = _zz_3;
assign io_read_payload = _zz_4;
assign io_uart_txd = _zz_2;
always @ (posedge io_mainClk or posedge resetCtrl_systemReset) begin
if (resetCtrl_systemReset) begin
clockDivider_counter <= (20'b00000000000000000000);
end else begin
clockDivider_counter <= (clockDivider_counter - (20'b00000000000000000001));
if(clockDivider_tick)begin
clockDivider_counter <= io_config_clockDivider;
end
end
end
endmodule
module StreamFifo (
input io_push_valid,
output io_push_ready,
input [7:0] io_push_payload,
output io_pop_valid,
input io_pop_ready,
output [7:0] io_pop_payload,
input io_flush,
output [4:0] io_occupancy,
output [4:0] io_availability,
input io_mainClk,
input resetCtrl_systemReset);
reg [7:0] _zz_4;
wire _zz_5;
wire _zz_6;
wire [0:0] _zz_7;
wire [3:0] _zz_8;
wire [0:0] _zz_9;
wire [3:0] _zz_10;
wire [3:0] _zz_11;
reg _zz_1;
reg pushPtr_willIncrement;
reg pushPtr_willClear;
reg [3:0] pushPtr_valueNext;
reg [3:0] pushPtr_value;
wire pushPtr_willOverflowIfInc;
wire pushPtr_willOverflow;
reg popPtr_willIncrement;
reg popPtr_willClear;
reg [3:0] popPtr_valueNext;
reg [3:0] popPtr_value;
wire popPtr_willOverflowIfInc;
wire popPtr_willOverflow;
wire ptrMatch;
reg risingOccupancy;
wire pushing;
wire popping;
wire empty;
wire full;
reg _zz_2;
wire _zz_3;
wire [3:0] ptrDif;
reg [7:0] ram [0:15];
assign io_push_ready = _zz_5;
assign io_pop_valid = _zz_6;
assign _zz_7 = pushPtr_willIncrement;
assign _zz_8 = {3'd0, _zz_7};
assign _zz_9 = popPtr_willIncrement;
assign _zz_10 = {3'd0, _zz_9};
assign _zz_11 = (popPtr_value - pushPtr_value);
always @ (posedge io_mainClk) begin
if(_zz_1) begin
ram[pushPtr_value] <= io_push_payload;
end
end
always @ (posedge io_mainClk) begin
if(_zz_3) begin
_zz_4 <= ram[popPtr_valueNext];
end
end
always @ (*) begin
_zz_1 = 1'b0;
pushPtr_willIncrement = 1'b0;
if(pushing)begin
_zz_1 = 1'b1;
pushPtr_willIncrement = 1'b1;
end
end
always @ (*) begin
pushPtr_willClear = 1'b0;
popPtr_willClear = 1'b0;
if(io_flush)begin
pushPtr_willClear = 1'b1;
popPtr_willClear = 1'b1;
end
end
assign pushPtr_willOverflowIfInc = (pushPtr_value == (4'b1111));
assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement);
always @ (*) begin
pushPtr_valueNext = (pushPtr_value + _zz_8);
if(pushPtr_willClear)begin
pushPtr_valueNext = (4'b0000);
end
end
always @ (*) begin
popPtr_willIncrement = 1'b0;
if(popping)begin
popPtr_willIncrement = 1'b1;
end
end
assign popPtr_willOverflowIfInc = (popPtr_value == (4'b1111));
assign popPtr_willOverflow = (popPtr_willOverflowIfInc && popPtr_willIncrement);
always @ (*) begin
popPtr_valueNext = (popPtr_value + _zz_10);
if(popPtr_willClear)begin
popPtr_valueNext = (4'b0000);
end
end
assign ptrMatch = (pushPtr_value == popPtr_value);
assign pushing = (io_push_valid && _zz_5);
assign popping = (_zz_6 && io_pop_ready);
assign empty = (ptrMatch && (! risingOccupancy));
assign full = (ptrMatch && risingOccupancy);
assign _zz_5 = (! full);
assign _zz_6 = ((! empty) && (! (_zz_2 && (! full))));
assign _zz_3 = 1'b1;
assign io_pop_payload = _zz_4;
assign ptrDif = (pushPtr_value - popPtr_value);
assign io_occupancy = {(risingOccupancy && ptrMatch),ptrDif};
assign io_availability = {((! risingOccupancy) && ptrMatch),_zz_11};
always @ (posedge io_mainClk or posedge resetCtrl_systemReset) begin
if (resetCtrl_systemReset) begin
pushPtr_value <= (4'b0000);
popPtr_value <= (4'b0000);
risingOccupancy <= 1'b0;
_zz_2 <= 1'b0;
end else begin
pushPtr_value <= pushPtr_valueNext;
popPtr_value <= popPtr_valueNext;
_zz_2 <= (popPtr_valueNext == pushPtr_value);
if((pushing != popping))begin
risingOccupancy <= pushing;
end
if(io_flush)begin
risingOccupancy <= 1'b0;
end
end
end
endmodule
//StreamFifo_1 remplaced by StreamFifo
module Prescaler (
input io_clear,
input [15:0] io_limit,
output io_overflow,
input io_mainClk,
input resetCtrl_systemReset);
wire _zz_1;
reg [15:0] counter;
assign io_overflow = _zz_1;
assign _zz_1 = (counter == io_limit);
always @ (posedge io_mainClk) begin
counter <= (counter + (16'b0000000000000001));
if((io_clear || _zz_1))begin
counter <= (16'b0000000000000000);
end
end
endmodule
module Timer (
input io_tick,
input io_clear,
input [15:0] io_limit,
output io_full,
output [15:0] io_value,
input io_mainClk,
input resetCtrl_systemReset);
wire [0:0] _zz_1;
wire [15:0] _zz_2;
reg [15:0] counter;
wire limitHit;
reg inhibitFull;
assign _zz_1 = (! limitHit);
assign _zz_2 = {15'd0, _zz_1};
assign limitHit = (counter == io_limit);
assign io_full = ((limitHit && io_tick) && (! inhibitFull));
assign io_value = counter;
always @ (posedge io_mainClk or posedge resetCtrl_systemReset) begin
if (resetCtrl_systemReset) begin
inhibitFull <= 1'b0;
end else begin
if(io_tick)begin
inhibitFull <= limitHit;
end
if(io_clear)begin
inhibitFull <= 1'b0;
end
end
end
always @ (posedge io_mainClk) begin
if(io_tick)begin
counter <= (counter + _zz_2);
end
if(io_clear)begin
counter <= (16'b0000000000000000);
end
end
endmodule
//Timer_1 remplaced by Timer
module InterruptCtrl (
input [1:0] io_inputs,
input [1:0] io_clears,
input [1:0] io_masks,
output [1:0] io_pendings,
input io_mainClk,
input resetCtrl_systemReset);
reg [1:0] pendings;
assign io_pendings = (pendings & io_masks);
always @ (posedge io_mainClk or posedge resetCtrl_systemReset) begin
if (resetCtrl_systemReset) begin
pendings <= (2'b00);
end else begin
pendings <= ((pendings & (~ io_clears)) | io_inputs);
end
end
endmodule
module BufferCC_2 (
input io_dataIn,
output io_dataOut,
input io_mainClk);
reg buffers_0;
reg buffers_1;
assign io_dataOut = buffers_1;
always @ (posedge io_mainClk) begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
endmodule
module MuraxMasterArbiter (
input io_iBus_cmd_valid,
output reg io_iBus_cmd_ready,
input [31:0] io_iBus_cmd_payload_pc,
output io_iBus_rsp_ready,
output io_iBus_rsp_error,
output [31:0] io_iBus_rsp_inst,
input io_dBus_cmd_valid,
output reg io_dBus_cmd_ready,
input io_dBus_cmd_payload_wr,
input [31:0] io_dBus_cmd_payload_address,
input [31:0] io_dBus_cmd_payload_data,
input [1:0] io_dBus_cmd_payload_size,
output io_dBus_rsp_ready,
output io_dBus_rsp_error,
output [31:0] io_dBus_rsp_data,
output io_masterBus_cmd_valid,
input io_masterBus_cmd_ready,
output io_masterBus_cmd_payload_wr,
output [31:0] io_masterBus_cmd_payload_address,
output [31:0] io_masterBus_cmd_payload_data,
output [3:0] io_masterBus_cmd_payload_mask,
input io_masterBus_rsp_valid,
input [31:0] io_masterBus_rsp_payload_data,
input io_mainClk,
input resetCtrl_systemReset);
reg _zz_2;
wire _zz_3;
reg [3:0] _zz_1;
reg rspPending;
reg rspTarget;
assign io_masterBus_cmd_valid = _zz_2;
assign io_masterBus_cmd_payload_wr = _zz_3;
always @ (*) begin
_zz_2 = (io_iBus_cmd_valid || io_dBus_cmd_valid);
io_iBus_cmd_ready = (io_masterBus_cmd_ready && (! io_dBus_cmd_valid));
io_dBus_cmd_ready = io_masterBus_cmd_ready;
if((rspPending && (! io_masterBus_rsp_valid)))begin
io_iBus_cmd_ready = 1'b0;
io_dBus_cmd_ready = 1'b0;
_zz_2 = 1'b0;
end
end
assign _zz_3 = (io_dBus_cmd_valid && io_dBus_cmd_payload_wr);
assign io_masterBus_cmd_payload_address = (io_dBus_cmd_valid ? io_dBus_cmd_payload_address : io_iBus_cmd_payload_pc);
assign io_masterBus_cmd_payload_data = io_dBus_cmd_payload_data;
always @ (*) begin
case(io_dBus_cmd_payload_size)
2'b00 : begin
_zz_1 = (4'b0001);
end
2'b01 : begin
_zz_1 = (4'b0011);
end
default : begin
_zz_1 = (4'b1111);
end
endcase
end
assign io_masterBus_cmd_payload_mask = (_zz_1 <<< io_dBus_cmd_payload_address[1 : 0]);
assign io_iBus_rsp_ready = (io_masterBus_rsp_valid && (! rspTarget));
assign io_iBus_rsp_inst = io_masterBus_rsp_payload_data;
assign io_iBus_rsp_error = 1'b0;
assign io_dBus_rsp_ready = (io_masterBus_rsp_valid && rspTarget);
assign io_dBus_rsp_data = io_masterBus_rsp_payload_data;
assign io_dBus_rsp_error = 1'b0;
always @ (posedge io_mainClk or posedge resetCtrl_systemReset) begin
if (resetCtrl_systemReset) begin
rspPending <= 1'b0;
rspTarget <= 1'b0;
end else begin
if(io_masterBus_rsp_valid)begin
rspPending <= 1'b0;
end
if(((_zz_2 && io_masterBus_cmd_ready) && (! _zz_3)))begin
rspTarget <= io_dBus_cmd_valid;
rspPending <= 1'b1;
end
end
end
endmodule
module VexRiscv (
input timerInterrupt,
input externalInterrupt,
input debug_bus_cmd_valid,
output debug_bus_cmd_ready,
input debug_bus_cmd_payload_wr,
input [7:0] debug_bus_cmd_payload_address,
input [31:0] debug_bus_cmd_payload_data,
output reg [31:0] debug_bus_rsp_data,
output debug_resetOut,
output iBus_cmd_valid,
input iBus_cmd_ready,
output [31:0] iBus_cmd_payload_pc,
input iBus_rsp_ready,
input iBus_rsp_error,
input [31:0] iBus_rsp_inst,
output dBus_cmd_valid,
input dBus_cmd_ready,
output dBus_cmd_payload_wr,
output [31:0] dBus_cmd_payload_address,
output [31:0] dBus_cmd_payload_data,
output [1:0] dBus_cmd_payload_size,
input dBus_rsp_ready,
input dBus_rsp_error,
input [31:0] dBus_rsp_data,
input io_mainClk,
input resetCtrl_systemReset,
input resetCtrl_mainClkReset);
reg [31:0] _zz_133;
reg [31:0] _zz_134;
wire _zz_135;
wire [1:0] _zz_136;
wire [31:0] _zz_137;
reg _zz_138;
reg [31:0] _zz_139;
wire _zz_140;
wire _zz_141;
wire _zz_142;
wire [0:0] _zz_143;
wire _zz_144;
wire _zz_145;
wire [1:0] _zz_146;
wire _zz_147;
wire [1:0] _zz_148;
wire [1:0] _zz_149;
wire [2:0] _zz_150;
wire [3:0] _zz_151;
wire [4:0] _zz_152;
wire [31:0] _zz_153;
wire [0:0] _zz_154;
wire [0:0] _zz_155;
wire [0:0] _zz_156;
wire [0:0] _zz_157;
wire [0:0] _zz_158;
wire [0:0] _zz_159;
wire [0:0] _zz_160;
wire [0:0] _zz_161;
wire [0:0] _zz_162;
wire [0:0] _zz_163;
wire [0:0] _zz_164;
wire [11:0] _zz_165;
wire [11:0] _zz_166;
wire [31:0] _zz_167;
wire [31:0] _zz_168;
wire [31:0] _zz_169;
wire [31:0] _zz_170;
wire [1:0] _zz_171;
wire [31:0] _zz_172;
wire [1:0] _zz_173;
wire [1:0] _zz_174;
wire [31:0] _zz_175;
wire [32:0] _zz_176;
wire [19:0] _zz_177;
wire [11:0] _zz_178;
wire [11:0] _zz_179;
wire [0:0] _zz_180;
wire [0:0] _zz_181;
wire [0:0] _zz_182;
wire [0:0] _zz_183;
wire [0:0] _zz_184;
wire [0:0] _zz_185;
wire [0:0] _zz_186;
wire [31:0] _zz_187;
wire [31:0] _zz_188;
wire [0:0] _zz_189;
wire [0:0] _zz_190;
wire [0:0] _zz_191;
wire [0:0] _zz_192;
wire _zz_193;
wire [0:0] _zz_194;
wire [17:0] _zz_195;
wire [0:0] _zz_196;
wire [2:0] _zz_197;
wire [0:0] _zz_198;
wire [1:0] _zz_199;
wire [2:0] _zz_200;
wire [2:0] _zz_201;
wire _zz_202;
wire [0:0] _zz_203;
wire [13:0] _zz_204;
wire [31:0] _zz_205;
wire [31:0] _zz_206;
wire _zz_207;
wire _zz_208;
wire [31:0] _zz_209;
wire [31:0] _zz_210;
wire _zz_211;
wire [0:0] _zz_212;
wire [0:0] _zz_213;
wire [0:0] _zz_214;
wire [1:0] _zz_215;
wire [0:0] _zz_216;
wire [0:0] _zz_217;
wire _zz_218;
wire [0:0] _zz_219;
wire [10:0] _zz_220;
wire [31:0] _zz_221;
wire [31:0] _zz_222;
wire [31:0] _zz_223;
wire [31:0] _zz_224;
wire [31:0] _zz_225;
wire [31:0] _zz_226;
wire [31:0] _zz_227;
wire [31:0] _zz_228;
wire [31:0] _zz_229;
wire _zz_230;
wire _zz_231;
wire _zz_232;
wire [0:0] _zz_233;
wire [0:0] _zz_234;
wire _zz_235;
wire [0:0] _zz_236;
wire [8:0] _zz_237;
wire [31:0] _zz_238;
wire [31:0] _zz_239;
wire [0:0] _zz_240;
wire [0:0] _zz_241;
wire [1:0] _zz_242;
wire [1:0] _zz_243;
wire _zz_244;
wire [0:0] _zz_245;
wire [5:0] _zz_246;
wire [31:0] _zz_247;
wire [31:0] _zz_248;
wire [31:0] _zz_249;
wire [31:0] _zz_250;
wire [31:0] _zz_251;
wire [31:0] _zz_252;
wire _zz_253;
wire [0:0] _zz_254;
wire [0:0] _zz_255;
wire _zz_256;
wire [0:0] _zz_257;
wire [2:0] _zz_258;
wire [31:0] _zz_259;
wire [31:0] _zz_260;
wire [31:0] _zz_261;
wire [0:0] _zz_262;
wire [0:0] _zz_263;
wire [1:0] _zz_264;
wire [1:0] _zz_265;
wire [3:0] _zz_266;
wire [3:0] _zz_267;
wire [31:0] _zz_268;
wire [31:0] _zz_269;
wire [31:0] _zz_270;
wire [31:0] _zz_271;
wire [31:0] _zz_272;
wire _zz_273;
wire [1:0] memory_MEMORY_ADDRESS_LOW;
wire [1:0] execute_MEMORY_ADDRESS_LOW;
wire [31:0] memory_FORMAL_PC_NEXT;
wire [31:0] execute_FORMAL_PC_NEXT;
wire [31:0] decode_FORMAL_PC_NEXT;
wire [31:0] fetch_FORMAL_PC_NEXT;
wire [31:0] prefetch_FORMAL_PC_NEXT;
wire [31:0] fetch_INSTRUCTION;
wire `ShiftCtrlEnum_binary_sequancial_type decode_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequancial_type _zz_1;
wire `ShiftCtrlEnum_binary_sequancial_type _zz_2;
wire `ShiftCtrlEnum_binary_sequancial_type _zz_3;
wire `BranchCtrlEnum_binary_sequancial_type decode_BRANCH_CTRL;
wire `BranchCtrlEnum_binary_sequancial_type _zz_4;
wire `BranchCtrlEnum_binary_sequancial_type _zz_5;
wire `BranchCtrlEnum_binary_sequancial_type _zz_6;
wire [31:0] memory_MEMORY_READ_DATA;
wire [31:0] decode_RS1;
wire execute_BRANCH_DO;
wire `AluCtrlEnum_binary_sequancial_type decode_ALU_CTRL;
wire `AluCtrlEnum_binary_sequancial_type _zz_7;
wire `AluCtrlEnum_binary_sequancial_type _zz_8;
wire `AluCtrlEnum_binary_sequancial_type _zz_9;
wire decode_SRC_LESS_UNSIGNED;
wire [31:0] execute_BRANCH_CALC;
wire [31:0] decode_SRC1;
wire `EnvCtrlEnum_binary_sequancial_type execute_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequancial_type _zz_10;
wire `EnvCtrlEnum_binary_sequancial_type _zz_11;
wire `EnvCtrlEnum_binary_sequancial_type _zz_12;
wire `EnvCtrlEnum_binary_sequancial_type decode_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequancial_type _zz_13;
wire `EnvCtrlEnum_binary_sequancial_type _zz_14;
wire `EnvCtrlEnum_binary_sequancial_type _zz_15;
wire decode_MEMORY_ENABLE;
wire [31:0] decode_SRC2;
wire [31:0] decode_RS2;
wire `AluBitwiseCtrlEnum_binary_sequancial_type decode_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequancial_type _zz_16;
wire `AluBitwiseCtrlEnum_binary_sequancial_type _zz_17;
wire `AluBitwiseCtrlEnum_binary_sequancial_type _zz_18;
wire decode_CSR_READ_OPCODE;
wire [31:0] writeBack_REGFILE_WRITE_DATA;
wire [31:0] execute_REGFILE_WRITE_DATA;
wire execute_BYPASSABLE_MEMORY_STAGE;
wire decode_BYPASSABLE_MEMORY_STAGE;
wire decode_SRC_USE_SUB_LESS;
wire decode_BYPASSABLE_EXECUTE_STAGE;
wire decode_CSR_WRITE_OPCODE;
wire [31:0] memory_PC;
wire [31:0] fetch_PC;
wire decode_IS_EBREAK;
wire execute_IS_EBREAK;
wire [31:0] memory_BRANCH_CALC;
wire memory_BRANCH_DO;
wire [31:0] _zz_19;
wire [31:0] execute_PC;
wire [31:0] execute_RS1;
wire `BranchCtrlEnum_binary_sequancial_type execute_BRANCH_CTRL;
wire `BranchCtrlEnum_binary_sequancial_type _zz_20;
wire _zz_21;
wire decode_RS2_USE;
wire decode_RS1_USE;
wire execute_REGFILE_WRITE_VALID;
wire execute_BYPASSABLE_EXECUTE_STAGE;
wire memory_REGFILE_WRITE_VALID;
wire memory_BYPASSABLE_MEMORY_STAGE;
wire writeBack_REGFILE_WRITE_VALID;
wire `ShiftCtrlEnum_binary_sequancial_type execute_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequancial_type _zz_22;
wire _zz_23;
wire [31:0] _zz_24;
wire [31:0] _zz_25;
wire execute_SRC_LESS_UNSIGNED;
wire execute_SRC_USE_SUB_LESS;
wire [31:0] _zz_26;
wire [31:0] _zz_27;
wire `Src2CtrlEnum_binary_sequancial_type decode_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequancial_type _zz_28;
wire [31:0] _zz_29;
wire [31:0] _zz_30;
wire `Src1CtrlEnum_binary_sequancial_type decode_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequancial_type _zz_31;
wire [31:0] _zz_32;
wire [31:0] execute_SRC_ADD_SUB;
wire execute_SRC_LESS;
wire `AluCtrlEnum_binary_sequancial_type execute_ALU_CTRL;
wire `AluCtrlEnum_binary_sequancial_type _zz_33;
wire [31:0] _zz_34;
wire [31:0] execute_SRC2;
wire `AluBitwiseCtrlEnum_binary_sequancial_type execute_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequancial_type _zz_35;
wire [31:0] _zz_36;
wire _zz_37;
reg _zz_38;
wire [31:0] _zz_39;
wire [31:0] _zz_40;
wire [31:0] decode_INSTRUCTION_ANTICIPATED;
reg decode_REGFILE_WRITE_VALID;
wire `AluBitwiseCtrlEnum_binary_sequancial_type _zz_41;
wire _zz_42;
wire `EnvCtrlEnum_binary_sequancial_type _zz_43;
wire _zz_44;
wire `Src2CtrlEnum_binary_sequancial_type _zz_45;
wire _zz_46;
wire `AluCtrlEnum_binary_sequancial_type _zz_47;
wire _zz_48;
wire _zz_49;
wire `ShiftCtrlEnum_binary_sequancial_type _zz_50;
wire _zz_51;
wire `BranchCtrlEnum_binary_sequancial_type _zz_52;
wire `Src1CtrlEnum_binary_sequancial_type _zz_53;
wire _zz_54;
wire _zz_55;
wire _zz_56;
wire _zz_57;
reg [31:0] _zz_58;
wire execute_CSR_READ_OPCODE;
wire execute_CSR_WRITE_OPCODE;
wire [31:0] memory_REGFILE_WRITE_DATA;
wire [31:0] execute_SRC1;
wire execute_IS_CSR;
wire decode_IS_CSR;
wire _zz_59;
wire _zz_60;
wire `EnvCtrlEnum_binary_sequancial_type memory_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequancial_type _zz_61;
wire [31:0] prefetch_PC_CALC_WITHOUT_JUMP;
reg [31:0] _zz_62;
wire writeBack_MEMORY_ENABLE;
wire [1:0] writeBack_MEMORY_ADDRESS_LOW;
wire [31:0] writeBack_MEMORY_READ_DATA;
wire [31:0] memory_INSTRUCTION;
wire memory_MEMORY_ENABLE;
wire [31:0] _zz_63;
wire [1:0] _zz_64;
wire [31:0] execute_RS2;
wire [31:0] execute_SRC_ADD;
wire [31:0] execute_INSTRUCTION;
wire execute_ALIGNEMENT_FAULT;
wire execute_MEMORY_ENABLE;
wire _zz_65;
wire [31:0] _zz_66;
wire [31:0] _zz_67;
reg [31:0] _zz_68;
wire [31:0] _zz_69;
reg [31:0] _zz_70;
wire [31:0] prefetch_PC;
wire [31:0] _zz_71;
wire [31:0] _zz_72;
wire [31:0] _zz_73;
wire [31:0] writeBack_PC /* verilator public */ ;
wire [31:0] writeBack_INSTRUCTION /* verilator public */ ;
wire [31:0] decode_PC /* verilator public */ ;
wire [31:0] decode_INSTRUCTION /* verilator public */ ;
reg prefetch_arbitration_haltItself;
reg prefetch_arbitration_haltByOther;
reg prefetch_arbitration_removeIt;
wire prefetch_arbitration_flushAll;
wire prefetch_arbitration_redoIt;
reg prefetch_arbitration_isValid;
wire prefetch_arbitration_isStuck;
wire prefetch_arbitration_isStuckByOthers;
wire prefetch_arbitration_isFlushed;
wire prefetch_arbitration_isMoving;
wire prefetch_arbitration_isFiring;
reg fetch_arbitration_haltItself;
wire fetch_arbitration_haltByOther;
reg fetch_arbitration_removeIt;
wire fetch_arbitration_flushAll;
wire fetch_arbitration_redoIt;
reg fetch_arbitration_isValid;
wire fetch_arbitration_isStuck;
wire fetch_arbitration_isStuckByOthers;
wire fetch_arbitration_isFlushed;
wire fetch_arbitration_isMoving;
wire fetch_arbitration_isFiring;
reg decode_arbitration_haltItself /* verilator public */ ;
wire decode_arbitration_haltByOther;
reg decode_arbitration_removeIt;
reg decode_arbitration_flushAll /* verilator public */ ;
wire decode_arbitration_redoIt;
reg decode_arbitration_isValid /* verilator public */ ;
wire decode_arbitration_isStuck;
wire decode_arbitration_isStuckByOthers;
wire decode_arbitration_isFlushed;
wire decode_arbitration_isMoving;
wire decode_arbitration_isFiring;
reg execute_arbitration_haltItself;
wire execute_arbitration_haltByOther;
reg execute_arbitration_removeIt;
reg execute_arbitration_flushAll;
wire execute_arbitration_redoIt;
reg execute_arbitration_isValid;
wire execute_arbitration_isStuck;
wire execute_arbitration_isStuckByOthers;
wire execute_arbitration_isFlushed;
wire execute_arbitration_isMoving;
wire execute_arbitration_isFiring;
reg memory_arbitration_haltItself;
wire memory_arbitration_haltByOther;
reg memory_arbitration_removeIt;
wire memory_arbitration_flushAll;
wire memory_arbitration_redoIt;
reg memory_arbitration_isValid;
wire memory_arbitration_isStuck;
wire memory_arbitration_isStuckByOthers;
wire memory_arbitration_isFlushed;
wire memory_arbitration_isMoving;
wire memory_arbitration_isFiring;
wire writeBack_arbitration_haltItself;
wire writeBack_arbitration_haltByOther;
reg writeBack_arbitration_removeIt;
wire writeBack_arbitration_flushAll;
wire writeBack_arbitration_redoIt;
reg writeBack_arbitration_isValid /* verilator public */ ;
wire writeBack_arbitration_isStuck;
wire writeBack_arbitration_isStuckByOthers;
wire writeBack_arbitration_isFlushed;
wire writeBack_arbitration_isMoving;
wire writeBack_arbitration_isFiring /* verilator public */ ;
reg _zz_74;
reg [31:0] _zz_75;
wire contextSwitching;
reg [1:0] _zz_76;
reg _zz_77;
wire _zz_78;
reg [31:0] prefetch_PcManagerSimplePlugin_pcReg /* verilator public */ ;
(* syn_keep , keep *) wire [31:0] prefetch_PcManagerSimplePlugin_pcPlus4 /* synthesis syn_keep = 1 */ ;
wire prefetch_PcManagerSimplePlugin_jump_pcLoad_valid;
wire [31:0] prefetch_PcManagerSimplePlugin_jump_pcLoad_payload;
wire [1:0] _zz_79;
wire _zz_80;
reg prefetch_IBusSimplePlugin_pendingCmd;
reg _zz_81;
reg [31:0] _zz_82;
reg [31:0] _zz_83;
reg [3:0] _zz_84;
wire [3:0] execute_DBusSimplePlugin_formalMask;
reg [31:0] writeBack_DBusSimplePlugin_rspShifted;
wire _zz_85;
reg [31:0] _zz_86;
wire _zz_87;
reg [31:0] _zz_88;
reg [31:0] writeBack_DBusSimplePlugin_rspFormated;
wire [1:0] CsrPlugin_misa_base;
wire [25:0] CsrPlugin_misa_extensions;
wire [31:0] CsrPlugin_mtvec;
reg [31:0] CsrPlugin_mepc;
reg CsrPlugin_mstatus_MIE;
reg CsrPlugin_mstatus_MPIE;
reg [1:0] CsrPlugin_mstatus_MPP;
reg CsrPlugin_mip_MEIP;
reg CsrPlugin_mip_MTIP;
reg CsrPlugin_mip_MSIP;
reg CsrPlugin_mie_MEIE;
reg CsrPlugin_mie_MTIE;
reg CsrPlugin_mie_MSIE;
reg CsrPlugin_mcause_interrupt;
reg [3:0] CsrPlugin_mcause_exceptionCode;
reg [31:0] CsrPlugin_mbadaddr;
reg [63:0] CsrPlugin_mcycle = 64'b0000010001001101000000101000010001000111110101110010011001010011;
reg [63:0] CsrPlugin_minstret = 64'b1110011011100100100100010001110100010111101010011111010100011101;
reg CsrPlugin_pipelineLiberator_enable;
wire CsrPlugin_pipelineLiberator_done;
wire CsrPlugin_interruptRequest;
wire CsrPlugin_interrupt;
wire CsrPlugin_exception;
wire CsrPlugin_writeBackWasWfi;
reg [31:0] _zz_89;
reg _zz_90;
reg execute_CsrPlugin_illegalAccess;
wire [31:0] execute_CsrPlugin_writeSrc;
reg [31:0] execute_CsrPlugin_readData;
reg execute_CsrPlugin_readDataRegValid;
reg [31:0] execute_CsrPlugin_writeData;
wire execute_CsrPlugin_writeInstruction;
wire execute_CsrPlugin_readInstruction;
wire execute_CsrPlugin_writeEnable;
wire execute_CsrPlugin_readEnable;
wire [11:0] execute_CsrPlugin_csrAddress;
wire [23:0] _zz_91;
wire _zz_92;
wire _zz_93;
wire _zz_94;
wire _zz_95;
wire _zz_96;
wire _zz_97;
wire `Src1CtrlEnum_binary_sequancial_type _zz_98;
wire `BranchCtrlEnum_binary_sequancial_type _zz_99;
wire `ShiftCtrlEnum_binary_sequancial_type _zz_100;
wire `AluCtrlEnum_binary_sequancial_type _zz_101;
wire `Src2CtrlEnum_binary_sequancial_type _zz_102;
wire `EnvCtrlEnum_binary_sequancial_type _zz_103;
wire `AluBitwiseCtrlEnum_binary_sequancial_type _zz_104;
wire [4:0] decode_RegFilePlugin_regFileReadAddress1;
wire [4:0] decode_RegFilePlugin_regFileReadAddress2;
wire [31:0] decode_RegFilePlugin_rs1Data;
wire _zz_105;
wire [31:0] decode_RegFilePlugin_rs2Data;
wire _zz_106;
reg writeBack_RegFilePlugin_regFileWrite_valid /* verilator public */ ;
wire [4:0] writeBack_RegFilePlugin_regFileWrite_payload_address /* verilator public */ ;
wire [31:0] writeBack_RegFilePlugin_regFileWrite_payload_data /* verilator public */ ;
reg _zz_107;
reg [31:0] execute_IntAluPlugin_bitwise;
reg [31:0] _zz_108;
reg [31:0] _zz_109;
wire _zz_110;
reg [19:0] _zz_111;
wire _zz_112;
reg [19:0] _zz_113;
reg [31:0] _zz_114;
wire [31:0] execute_SrcPlugin_addSub;
wire execute_SrcPlugin_less;
reg execute_LightShifterPlugin_isActive;
wire execute_LightShifterPlugin_isShift;
reg [4:0] execute_LightShifterPlugin_amplitudeReg;
wire [4:0] execute_LightShifterPlugin_amplitude;
wire [31:0] execute_LightShifterPlugin_shiftInput;
wire execute_LightShifterPlugin_done;
reg [31:0] _zz_115;
reg _zz_116;
reg _zz_117;
reg _zz_118;
reg [4:0] _zz_119;
wire execute_BranchPlugin_eq;
wire [2:0] _zz_120;
reg _zz_121;
reg _zz_122;
wire [31:0] execute_BranchPlugin_branch_src1;
wire _zz_123;
reg [10:0] _zz_124;
wire _zz_125;
reg [19:0] _zz_126;
wire _zz_127;
reg [18:0] _zz_128;
reg [31:0] _zz_129;
wire [31:0] execute_BranchPlugin_branch_src2;
wire [31:0] execute_BranchPlugin_branchAdder;
reg DebugPlugin_insertDecodeInstruction;
reg DebugPlugin_firstCycle;
reg DebugPlugin_secondCycle;
reg DebugPlugin_resetIt;
reg DebugPlugin_haltIt;
reg DebugPlugin_stepIt;
reg DebugPlugin_isPipActive;
reg _zz_130;
wire DebugPlugin_isPipBusy;
reg DebugPlugin_haltedByBreak;
reg [31:0] DebugPlugin_busReadDataReg;
reg _zz_131;
reg _zz_132;
reg decode_to_execute_IS_EBREAK;
reg [31:0] prefetch_to_fetch_PC;
reg [31:0] fetch_to_decode_PC;
reg [31:0] decode_to_execute_PC;
reg [31:0] execute_to_memory_PC;
reg [31:0] memory_to_writeBack_PC;
reg decode_to_execute_CSR_WRITE_OPCODE;
reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
reg decode_to_execute_SRC_USE_SUB_LESS;
reg decode_to_execute_BYPASSABLE_MEMORY_STAGE;
reg execute_to_memory_BYPASSABLE_MEMORY_STAGE;
reg [31:0] execute_to_memory_REGFILE_WRITE_DATA;
reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA;
reg decode_to_execute_CSR_READ_OPCODE;
reg `AluBitwiseCtrlEnum_binary_sequancial_type decode_to_execute_ALU_BITWISE_CTRL;
reg [31:0] decode_to_execute_RS2;
reg [31:0] decode_to_execute_SRC2;
reg decode_to_execute_MEMORY_ENABLE;
reg execute_to_memory_MEMORY_ENABLE;
reg memory_to_writeBack_MEMORY_ENABLE;
reg `EnvCtrlEnum_binary_sequancial_type decode_to_execute_ENV_CTRL;
reg `EnvCtrlEnum_binary_sequancial_type execute_to_memory_ENV_CTRL;
reg [31:0] decode_to_execute_SRC1;
reg [31:0] execute_to_memory_BRANCH_CALC;
reg decode_to_execute_SRC_LESS_UNSIGNED;
reg `AluCtrlEnum_binary_sequancial_type decode_to_execute_ALU_CTRL;
reg execute_to_memory_BRANCH_DO;
reg [31:0] decode_to_execute_RS1;
reg decode_to_execute_IS_CSR;
reg [31:0] memory_to_writeBack_MEMORY_READ_DATA;
reg `BranchCtrlEnum_binary_sequancial_type decode_to_execute_BRANCH_CTRL;
reg decode_to_execute_REGFILE_WRITE_VALID;
reg execute_to_memory_REGFILE_WRITE_VALID;
reg memory_to_writeBack_REGFILE_WRITE_VALID;
reg `ShiftCtrlEnum_binary_sequancial_type decode_to_execute_SHIFT_CTRL;
reg [31:0] fetch_to_decode_INSTRUCTION;
reg [31:0] decode_to_execute_INSTRUCTION;
reg [31:0] execute_to_memory_INSTRUCTION;
reg [31:0] memory_to_writeBack_INSTRUCTION;
reg [31:0] prefetch_to_fetch_FORMAL_PC_NEXT;
reg [31:0] fetch_to_decode_FORMAL_PC_NEXT;
reg [31:0] decode_to_execute_FORMAL_PC_NEXT;
reg [31:0] execute_to_memory_FORMAL_PC_NEXT;
reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW;
reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW;
reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ;
assign iBus_cmd_valid = _zz_135;
assign dBus_cmd_payload_size = _zz_136;
assign dBus_cmd_payload_address = _zz_137;
assign debug_bus_cmd_ready = _zz_138;
assign _zz_140 = (execute_arbitration_isFiring && execute_IS_EBREAK);
assign _zz_141 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != (5'b00000)));
assign _zz_142 = (! execute_arbitration_isStuckByOthers);
assign _zz_143 = debug_bus_cmd_payload_address[2 : 2];
assign _zz_144 = (memory_ENV_CTRL == `EnvCtrlEnum_binary_sequancial_MRET);
assign _zz_145 = (CsrPlugin_exception || (CsrPlugin_interrupt && CsrPlugin_pipelineLiberator_done));
assign _zz_146 = writeBack_INSTRUCTION[13 : 12];
assign _zz_147 = execute_INSTRUCTION[13];
assign _zz_148 = (_zz_79 & (~ _zz_149));
assign _zz_149 = (_zz_79 - (2'b01));
assign _zz_150 = ((CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE) ? (3'b011) : (3'b111));
assign _zz_151 = {1'd0, _zz_150};
assign _zz_152 = execute_INSTRUCTION[19 : 15];
assign _zz_153 = {27'd0, _zz_152};
assign _zz_154 = _zz_91[0 : 0];
assign _zz_155 = _zz_91[1 : 1];
assign _zz_156 = _zz_91[2 : 2];
assign _zz_157 = _zz_91[3 : 3];
assign _zz_158 = _zz_91[8 : 8];
assign _zz_159 = _zz_91[11 : 11];
assign _zz_160 = _zz_91[12 : 12];
assign _zz_161 = _zz_91[15 : 15];
assign _zz_162 = _zz_91[18 : 18];
assign _zz_163 = _zz_91[21 : 21];
assign _zz_164 = execute_SRC_LESS;
assign _zz_165 = decode_INSTRUCTION[31 : 20];
assign _zz_166 = {decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]};
assign _zz_167 = ($signed(_zz_168) + $signed(_zz_172));
assign _zz_168 = ($signed(_zz_169) + $signed(_zz_170));
assign _zz_169 = execute_SRC1;
assign _zz_170 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2);
assign _zz_171 = (execute_SRC_USE_SUB_LESS ? _zz_173 : _zz_174);
assign _zz_172 = {{30{_zz_171[1]}}, _zz_171};
assign _zz_173 = (2'b01);
assign _zz_174 = (2'b00);
assign _zz_175 = (_zz_176 >>> 1);
assign _zz_176 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequancial_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput};
assign _zz_177 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
assign _zz_178 = execute_INSTRUCTION[31 : 20];
assign _zz_179 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
assign _zz_180 = execute_CsrPlugin_writeData[7 : 7];
assign _zz_181 = execute_CsrPlugin_writeData[3 : 3];
assign _zz_182 = execute_CsrPlugin_writeData[3 : 3];
assign _zz_183 = execute_CsrPlugin_writeData[11 : 11];
assign _zz_184 = execute_CsrPlugin_writeData[7 : 7];
assign _zz_185 = execute_CsrPlugin_writeData[3 : 3];
assign _zz_186 = _zz_80;
assign _zz_187 = (decode_INSTRUCTION & (32'b00000000000000000001000000000000));
assign _zz_188 = (32'b00000000000000000001000000000000);
assign _zz_189 = ((decode_INSTRUCTION & (32'b00000000000000000011000000000000)) == (32'b00000000000000000001000000000000));
assign _zz_190 = ((decode_INSTRUCTION & (32'b00000000000000000011000000000000)) == (32'b00000000000000000010000000000000));
assign _zz_191 = ((decode_INSTRUCTION & (32'b00000000000100000011000001010000)) == (32'b00000000000000000000000001010000));
assign _zz_192 = (1'b0);
assign _zz_193 = 1'b0;
assign _zz_194 = ({_zz_97,{_zz_196,_zz_197}} != (5'b00000));
assign _zz_195 = {({_zz_198,_zz_199} != (3'b000)),{(_zz_200 != _zz_201),{_zz_202,{_zz_203,_zz_204}}}};
assign _zz_196 = _zz_96;
assign _zz_197 = {(_zz_205 == _zz_206),{_zz_207,_zz_208}};
assign _zz_198 = _zz_97;
assign _zz_199 = {_zz_95,(_zz_209 == _zz_210)};
assign _zz_200 = {_zz_97,{_zz_96,_zz_95}};
assign _zz_201 = (3'b000);
assign _zz_202 = ({_zz_211,{_zz_212,_zz_213}} != (3'b000));
assign _zz_203 = ({_zz_214,_zz_215} != (3'b000));
assign _zz_204 = {(_zz_216 != _zz_217),{_zz_218,{_zz_219,_zz_220}}};
assign _zz_205 = (decode_INSTRUCTION & (32'b00000000000000000001000000010000));
assign _zz_206 = (32'b00000000000000000001000000010000);
assign _zz_207 = ((decode_INSTRUCTION & _zz_221) == (32'b00000000000000000010000000010000));
assign _zz_208 = ((decode_INSTRUCTION & _zz_222) == (32'b00000000000000000000000000010000));
assign _zz_209 = (decode_INSTRUCTION & (32'b00000000000000000000000001110000));
assign _zz_210 = (32'b00000000000000000000000000100000);
assign _zz_211 = ((decode_INSTRUCTION & _zz_223) == (32'b01000000000000000000000000110000));
assign _zz_212 = (_zz_224 == _zz_225);
assign _zz_213 = (_zz_226 == _zz_227);
assign _zz_214 = (_zz_228 == _zz_229);
assign _zz_215 = {_zz_230,_zz_231};
assign _zz_216 = _zz_92;
assign _zz_217 = (1'b0);
assign _zz_218 = (_zz_232 != (1'b0));
assign _zz_219 = (_zz_233 != _zz_234);
assign _zz_220 = {_zz_235,{_zz_236,_zz_237}};
assign _zz_221 = (32'b00000000000000000010000000010000);
assign _zz_222 = (32'b00000000000000000000000001010000);
assign _zz_223 = (32'b01000000000000000000000000110000);
assign _zz_224 = (decode_INSTRUCTION & (32'b00000000000000000010000000010100));
assign _zz_225 = (32'b00000000000000000010000000010000);
assign _zz_226 = (decode_INSTRUCTION & (32'b00000000000000000000000001010100));
assign _zz_227 = (32'b00000000000000000000000001000000);
assign _zz_228 = (decode_INSTRUCTION & (32'b00000000000000000100000000000100));
assign _zz_229 = (32'b00000000000000000100000000000000);
assign _zz_230 = ((decode_INSTRUCTION & (32'b00000000000000000000000001100100)) == (32'b00000000000000000000000000100100));
assign _zz_231 = ((decode_INSTRUCTION & (32'b00000000000000000011000000000100)) == (32'b00000000000000000001000000000000));
assign _zz_232 = ((decode_INSTRUCTION & (32'b00100000000000000011000001010000)) == (32'b00000000000000000000000001010000));
assign _zz_233 = _zz_94;
assign _zz_234 = (1'b0);
assign _zz_235 = ((_zz_238 == _zz_239) != (1'b0));
assign _zz_236 = ({_zz_240,_zz_241} != (2'b00));
assign _zz_237 = {(_zz_242 != _zz_243),{_zz_244,{_zz_245,_zz_246}}};
assign _zz_238 = (decode_INSTRUCTION & (32'b00000000000000000111000001010100));
assign _zz_239 = (32'b00000000000000000101000000010000);
assign _zz_240 = ((decode_INSTRUCTION & _zz_247) == (32'b01000000000000000001000000010000));
assign _zz_241 = ((decode_INSTRUCTION & _zz_248) == (32'b00000000000000000001000000010000));
assign _zz_242 = {(_zz_249 == _zz_250),(_zz_251 == _zz_252)};
assign _zz_243 = (2'b00);
assign _zz_244 = (_zz_93 != (1'b0));
assign _zz_245 = (_zz_253 != (1'b0));
assign _zz_246 = {(_zz_254 != _zz_255),{_zz_256,{_zz_257,_zz_258}}};
assign _zz_247 = (32'b01000000000000000011000001010100);
assign _zz_248 = (32'b00000000000000000111000001010100);
assign _zz_249 = (decode_INSTRUCTION & (32'b00000000000000000010000000010000));
assign _zz_250 = (32'b00000000000000000010000000000000);
assign _zz_251 = (decode_INSTRUCTION & (32'b00000000000000000101000000000000));
assign _zz_252 = (32'b00000000000000000001000000000000);
assign _zz_253 = ((decode_INSTRUCTION & (32'b00000000000000000000000001011000)) == (32'b00000000000000000000000001000000));
assign _zz_254 = _zz_93;
assign _zz_255 = (1'b0);
assign _zz_256 = (((decode_INSTRUCTION & _zz_259) == (32'b00000000000000000000000000000100)) != (1'b0));
assign _zz_257 = ((_zz_260 == _zz_261) != (1'b0));
assign _zz_258 = {({_zz_262,_zz_263} != (2'b00)),{(_zz_264 != _zz_265),(_zz_266 != _zz_267)}};
assign _zz_259 = (32'b00000000000000000000000001000100);
assign _zz_260 = (decode_INSTRUCTION & (32'b00000000000000000000000001010000));
assign _zz_261 = (32'b00000000000000000000000000000000);
assign _zz_262 = ((decode_INSTRUCTION & (32'b00000000000000000000000000110100)) == (32'b00000000000000000000000000100000));
assign _zz_263 = ((decode_INSTRUCTION & (32'b00000000000000000000000001100100)) == (32'b00000000000000000000000000100000));
assign _zz_264 = {((decode_INSTRUCTION & _zz_268) == (32'b00000000000000000001000001010000)),((decode_INSTRUCTION & _zz_269) == (32'b00000000000000000010000001010000))};
assign _zz_265 = (2'b00);
assign _zz_266 = {((decode_INSTRUCTION & _zz_270) == (32'b00000000000000000000000000000000)),{(_zz_271 == _zz_272),{_zz_92,_zz_273}}};
assign _zz_267 = (4'b0000);
assign _zz_268 = (32'b00000000000000000001000001010000);
assign _zz_269 = (32'b00000000000000000010000001010000);
assign _zz_270 = (32'b00000000000000000000000001000100);
assign _zz_271 = (decode_INSTRUCTION & (32'b00000000000000000000000000011000));
assign _zz_272 = (32'b00000000000000000000000000000000);
assign _zz_273 = ((decode_INSTRUCTION & (32'b00000000000000000101000000000100)) == (32'b00000000000000000001000000000000));
always @ (posedge io_mainClk) begin
if(_zz_38) begin
RegFilePlugin_regFile[writeBack_RegFilePlugin_regFileWrite_payload_address] <= writeBack_RegFilePlugin_regFileWrite_payload_data;
end
end
always @ (posedge io_mainClk) begin
if(_zz_105) begin
_zz_133 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1];
end
end
always @ (posedge io_mainClk) begin
if(_zz_106) begin
_zz_134 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2];
end
end
always @(*) begin
case(_zz_186)
1'b0 : begin
_zz_139 = memory_BRANCH_CALC;
end
default : begin
_zz_139 = _zz_75;
end
endcase
end
assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW;
assign execute_MEMORY_ADDRESS_LOW = _zz_64;
assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT;
assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT;
assign decode_FORMAL_PC_NEXT = fetch_to_decode_FORMAL_PC_NEXT;
assign fetch_FORMAL_PC_NEXT = prefetch_to_fetch_FORMAL_PC_NEXT;
assign prefetch_FORMAL_PC_NEXT = _zz_71;
assign fetch_INSTRUCTION = _zz_68;
assign decode_SHIFT_CTRL = _zz_1;
assign _zz_2 = _zz_3;
assign decode_BRANCH_CTRL = _zz_4;
assign _zz_5 = _zz_6;
assign memory_MEMORY_READ_DATA = _zz_63;
assign decode_RS1 = _zz_40;
assign execute_BRANCH_DO = _zz_21;
assign decode_ALU_CTRL = _zz_7;
assign _zz_8 = _zz_9;
assign decode_SRC_LESS_UNSIGNED = _zz_51;
assign execute_BRANCH_CALC = _zz_19;
assign decode_SRC1 = _zz_32;
assign execute_ENV_CTRL = _zz_10;
assign _zz_11 = _zz_12;
assign decode_ENV_CTRL = _zz_13;
assign _zz_14 = _zz_15;
assign decode_MEMORY_ENABLE = _zz_54;
assign decode_SRC2 = _zz_29;
assign decode_RS2 = _zz_39;
assign decode_ALU_BITWISE_CTRL = _zz_16;
assign _zz_17 = _zz_18;
assign decode_CSR_READ_OPCODE = _zz_59;
assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA;
assign execute_REGFILE_WRITE_DATA = _zz_34;
assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE;
assign decode_BYPASSABLE_MEMORY_STAGE = _zz_42;
assign decode_SRC_USE_SUB_LESS = _zz_46;
assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_49;
assign decode_CSR_WRITE_OPCODE = _zz_60;
assign memory_PC = execute_to_memory_PC;
assign fetch_PC = prefetch_to_fetch_PC;
assign decode_IS_EBREAK = _zz_48;
assign execute_IS_EBREAK = decode_to_execute_IS_EBREAK;
assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC;
assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO;
assign execute_PC = decode_to_execute_PC;
assign execute_RS1 = decode_to_execute_RS1;
assign execute_BRANCH_CTRL = _zz_20;
assign decode_RS2_USE = _zz_55;
assign decode_RS1_USE = _zz_57;
assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID;
assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID;
assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE;
assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID;
assign execute_SHIFT_CTRL = _zz_22;
assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED;
assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS;
assign _zz_26 = decode_PC;
assign _zz_27 = decode_RS2;
assign decode_SRC2_CTRL = _zz_28;
assign _zz_30 = decode_RS1;
assign decode_SRC1_CTRL = _zz_31;
assign execute_SRC_ADD_SUB = _zz_25;
assign execute_SRC_LESS = _zz_23;
assign execute_ALU_CTRL = _zz_33;
assign execute_SRC2 = decode_to_execute_SRC2;
assign execute_ALU_BITWISE_CTRL = _zz_35;
assign _zz_36 = writeBack_INSTRUCTION;
assign _zz_37 = writeBack_REGFILE_WRITE_VALID;
always @ (*) begin
_zz_38 = 1'b0;
if(writeBack_RegFilePlugin_regFileWrite_valid)begin
_zz_38 = 1'b1;
end
end
assign decode_INSTRUCTION_ANTICIPATED = _zz_67;
always @ (*) begin
decode_REGFILE_WRITE_VALID = _zz_44;
if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin
decode_REGFILE_WRITE_VALID = 1'b0;
end
end
always @ (*) begin
_zz_58 = execute_REGFILE_WRITE_DATA;
execute_arbitration_haltItself = 1'b0;
if((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_ALIGNEMENT_FAULT)))begin
execute_arbitration_haltItself = 1'b1;
end
if((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_readDataRegValid)))begin
execute_arbitration_haltItself = 1'b1;
end
if((execute_arbitration_isValid && execute_IS_CSR))begin
_zz_58 = execute_CsrPlugin_readData;
end
if(_zz_141)begin
_zz_58 = _zz_115;
if(_zz_142)begin
if(! execute_LightShifterPlugin_done) begin
execute_arbitration_haltItself = 1'b1;
end
end
end
end
assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE;
assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE;
assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA;
assign execute_SRC1 = decode_to_execute_SRC1;
assign execute_IS_CSR = decode_to_execute_IS_CSR;
assign decode_IS_CSR = _zz_56;
assign memory_ENV_CTRL = _zz_61;
assign prefetch_PC_CALC_WITHOUT_JUMP = _zz_73;
always @ (*) begin
_zz_62 = writeBack_REGFILE_WRITE_DATA;
if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin
_zz_62 = writeBack_DBusSimplePlugin_rspFormated;
end
end
assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE;
assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW;
assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA;
assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION;
assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE;
assign execute_RS2 = decode_to_execute_RS2;
assign execute_SRC_ADD = _zz_24;
assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION;
assign execute_ALIGNEMENT_FAULT = _zz_65;
assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE;
assign _zz_66 = fetch_INSTRUCTION;
assign _zz_69 = prefetch_PC;
always @ (*) begin
_zz_70 = execute_FORMAL_PC_NEXT;
if(_zz_74)begin
_zz_70 = _zz_75;
end
end
assign prefetch_PC = _zz_72;
assign writeBack_PC = memory_to_writeBack_PC;
assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION;
assign decode_PC = fetch_to_decode_PC;
assign decode_INSTRUCTION = fetch_to_decode_INSTRUCTION;
always @ (*) begin
prefetch_arbitration_haltItself = 1'b0;
if(((! iBus_cmd_ready) || (prefetch_IBusSimplePlugin_pendingCmd && (! iBus_rsp_ready))))begin
prefetch_arbitration_haltItself = 1'b1;
end
end
always @ (*) begin
prefetch_arbitration_haltByOther = 1'b0;
decode_arbitration_flushAll = 1'b0;
if(CsrPlugin_pipelineLiberator_enable)begin
prefetch_arbitration_haltByOther = 1'b1;
end
if(_zz_140)begin
prefetch_arbitration_haltByOther = 1'b1;
decode_arbitration_flushAll = 1'b1;
end
if(DebugPlugin_haltIt)begin
prefetch_arbitration_haltByOther = 1'b1;
end
end
always @ (*) begin
prefetch_arbitration_removeIt = 1'b0;
if(prefetch_arbitration_isFlushed)begin
prefetch_arbitration_removeIt = 1'b1;
end
end
assign prefetch_arbitration_flushAll = 1'b0;
assign prefetch_arbitration_redoIt = 1'b0;
always @ (*) begin
fetch_arbitration_haltItself = 1'b0;
if(((fetch_arbitration_isValid && (! iBus_rsp_ready)) && (! _zz_81)))begin
fetch_arbitration_haltItself = 1'b1;
end
end
assign fetch_arbitration_haltByOther = 1'b0;
always @ (*) begin
fetch_arbitration_removeIt = 1'b0;
if(fetch_arbitration_isFlushed)begin
fetch_arbitration_removeIt = 1'b1;
end
end
assign fetch_arbitration_flushAll = 1'b0;
assign fetch_arbitration_redoIt = 1'b0;
always @ (*) begin
decode_arbitration_haltItself = 1'b0;
if(((decode_arbitration_isValid && decode_IS_CSR) && (execute_arbitration_isValid || memory_arbitration_isValid)))begin
decode_arbitration_haltItself = 1'b1;
end
if((decode_arbitration_isValid && (_zz_116 || _zz_117)))begin
decode_arbitration_haltItself = 1'b1;
end
DebugPlugin_insertDecodeInstruction = 1'b0;
_zz_138 = 1'b1;
if(debug_bus_cmd_valid)begin
case(_zz_143)
1'b0 : begin
end
default : begin
if(debug_bus_cmd_payload_wr)begin
DebugPlugin_insertDecodeInstruction = 1'b1;
if(DebugPlugin_secondCycle)begin
decode_arbitration_haltItself = 1'b1;
end
_zz_138 = (! ((DebugPlugin_firstCycle || DebugPlugin_secondCycle) || decode_arbitration_isValid));
end
end
endcase
end
end
assign decode_arbitration_haltByOther = 1'b0;
always @ (*) begin
decode_arbitration_removeIt = 1'b0;
if(decode_arbitration_isFlushed)begin
decode_arbitration_removeIt = 1'b1;
end
end
assign decode_arbitration_redoIt = 1'b0;
assign execute_arbitration_haltByOther = 1'b0;
always @ (*) begin
execute_arbitration_removeIt = 1'b0;
if(execute_arbitration_isFlushed)begin
execute_arbitration_removeIt = 1'b1;
end
end
always @ (*) begin
execute_arbitration_flushAll = 1'b0;
if(_zz_144)begin
if(memory_arbitration_isFiring)begin
execute_arbitration_flushAll = 1'b1;
end
end
if(_zz_78)begin
execute_arbitration_flushAll = 1'b1;
end
end
assign execute_arbitration_redoIt = 1'b0;
always @ (*) begin
memory_arbitration_haltItself = 1'b0;
_zz_74 = 1'b0;
_zz_75 = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_INSTRUCTION[5])) && (! dBus_rsp_ready)))begin
memory_arbitration_haltItself = 1'b1;
end
if(_zz_145)begin
_zz_74 = 1'b1;
_zz_75 = CsrPlugin_mtvec;
end
if(_zz_144)begin
memory_arbitration_haltItself = writeBack_arbitration_isValid;
if(memory_arbitration_isFiring)begin
_zz_74 = 1'b1;
_zz_75 = CsrPlugin_mepc;
end
end
end
assign memory_arbitration_haltByOther = 1'b0;
always @ (*) begin
memory_arbitration_removeIt = 1'b0;
if(memory_arbitration_isFlushed)begin
memory_arbitration_removeIt = 1'b1;
end
end
assign memory_arbitration_flushAll = 1'b0;
assign memory_arbitration_redoIt = 1'b0;
assign writeBack_arbitration_haltItself = 1'b0;
assign writeBack_arbitration_haltByOther = 1'b0;
always @ (*) begin
writeBack_arbitration_removeIt = 1'b0;
if(writeBack_arbitration_isFlushed)begin
writeBack_arbitration_removeIt = 1'b1;
end
end
assign writeBack_arbitration_flushAll = 1'b0;
assign writeBack_arbitration_redoIt = 1'b0;
always @ (*) begin
_zz_77 = 1'b1;
if((DebugPlugin_haltIt || DebugPlugin_stepIt))begin
_zz_77 = 1'b0;
end
end
assign prefetch_PcManagerSimplePlugin_pcPlus4 = (prefetch_PcManagerSimplePlugin_pcReg + (32'b00000000000000000000000000000100));
assign prefetch_PcManagerSimplePlugin_jump_pcLoad_valid = (_zz_74 || _zz_78);
assign _zz_79 = {_zz_74,_zz_78};
assign _zz_80 = _zz_148[1];
assign prefetch_PcManagerSimplePlugin_jump_pcLoad_payload = _zz_139;
assign _zz_73 = prefetch_PcManagerSimplePlugin_pcReg;
assign _zz_72 = prefetch_PcManagerSimplePlugin_pcReg;
assign _zz_71 = (prefetch_PC + (32'b00000000000000000000000000000100));
assign _zz_135 = (((prefetch_arbitration_isValid && (! prefetch_arbitration_removeIt)) && (! prefetch_arbitration_isStuckByOthers)) && (! (prefetch_IBusSimplePlugin_pendingCmd && (! iBus_rsp_ready))));
assign iBus_cmd_payload_pc = _zz_69;
always @ (*) begin
_zz_68 = iBus_rsp_inst;
if(_zz_81)begin
_zz_68 = _zz_82;
end
end
assign _zz_67 = (decode_arbitration_isStuck ? decode_INSTRUCTION : _zz_66);
assign _zz_65 = 1'b0;
assign dBus_cmd_valid = ((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_removeIt)) && (! execute_ALIGNEMENT_FAULT));
assign dBus_cmd_payload_wr = execute_INSTRUCTION[5];
assign _zz_137 = execute_SRC_ADD;
assign _zz_136 = execute_INSTRUCTION[13 : 12];
always @ (*) begin
case(_zz_136)
2'b00 : begin
_zz_83 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]};
end
2'b01 : begin
_zz_83 = {execute_RS2[15 : 0],execute_RS2[15 : 0]};
end
default : begin
_zz_83 = execute_RS2[31 : 0];
end
endcase
end
assign dBus_cmd_payload_data = _zz_83;
assign _zz_64 = _zz_137[1 : 0];
always @ (*) begin
case(_zz_136)
2'b00 : begin
_zz_84 = (4'b0001);
end
2'b01 : begin
_zz_84 = (4'b0011);
end
default : begin
_zz_84 = (4'b1111);
end
endcase
end
assign execute_DBusSimplePlugin_formalMask = (_zz_84 <<< _zz_137[1 : 0]);
assign _zz_63 = dBus_rsp_data;
always @ (*) begin
writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA;
case(writeBack_MEMORY_ADDRESS_LOW)
2'b01 : begin
writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[15 : 8];
end
2'b10 : begin
writeBack_DBusSimplePlugin_rspShifted[15 : 0] = writeBack_MEMORY_READ_DATA[31 : 16];
end
2'b11 : begin
writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[31 : 24];
end
default : begin
end
endcase
end
assign _zz_85 = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14]));
always @ (*) begin
_zz_86[31] = _zz_85;
_zz_86[30] = _zz_85;
_zz_86[29] = _zz_85;
_zz_86[28] = _zz_85;
_zz_86[27] = _zz_85;
_zz_86[26] = _zz_85;
_zz_86[25] = _zz_85;
_zz_86[24] = _zz_85;
_zz_86[23] = _zz_85;
_zz_86[22] = _zz_85;
_zz_86[21] = _zz_85;
_zz_86[20] = _zz_85;
_zz_86[19] = _zz_85;
_zz_86[18] = _zz_85;
_zz_86[17] = _zz_85;
_zz_86[16] = _zz_85;
_zz_86[15] = _zz_85;
_zz_86[14] = _zz_85;
_zz_86[13] = _zz_85;
_zz_86[12] = _zz_85;
_zz_86[11] = _zz_85;
_zz_86[10] = _zz_85;
_zz_86[9] = _zz_85;
_zz_86[8] = _zz_85;
_zz_86[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0];
end
assign _zz_87 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14]));
always @ (*) begin
_zz_88[31] = _zz_87;
_zz_88[30] = _zz_87;
_zz_88[29] = _zz_87;
_zz_88[28] = _zz_87;
_zz_88[27] = _zz_87;
_zz_88[26] = _zz_87;
_zz_88[25] = _zz_87;
_zz_88[24] = _zz_87;
_zz_88[23] = _zz_87;
_zz_88[22] = _zz_87;
_zz_88[21] = _zz_87;
_zz_88[20] = _zz_87;
_zz_88[19] = _zz_87;
_zz_88[18] = _zz_87;
_zz_88[17] = _zz_87;
_zz_88[16] = _zz_87;
_zz_88[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0];
end
always @ (*) begin
case(_zz_146)
2'b00 : begin
writeBack_DBusSimplePlugin_rspFormated = _zz_86;
end
2'b01 : begin
writeBack_DBusSimplePlugin_rspFormated = _zz_88;
end
default : begin
writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted;
end
endcase
end
assign CsrPlugin_misa_base = (2'b01);
assign CsrPlugin_misa_extensions = (26'b00000000000000000001000010);
assign CsrPlugin_mtvec = (32'b10000000000000000000000000100000);
always @ (*) begin
CsrPlugin_pipelineLiberator_enable = 1'b0;
if(CsrPlugin_interrupt)begin
CsrPlugin_pipelineLiberator_enable = 1'b1;
end
end
assign CsrPlugin_pipelineLiberator_done = (! ((((fetch_arbitration_isValid || decode_arbitration_isValid) || execute_arbitration_isValid) || memory_arbitration_isValid) || writeBack_arbitration_isValid));
assign CsrPlugin_interruptRequest = ((((CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE) || (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE)) || (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE)) && CsrPlugin_mstatus_MIE);
assign CsrPlugin_interrupt = (CsrPlugin_interruptRequest && _zz_77);
assign CsrPlugin_exception = 1'b0;
assign CsrPlugin_writeBackWasWfi = 1'b0;
always @ (*) begin
case(CsrPlugin_exception)
1'b1 : begin
_zz_89 = writeBack_PC;
end
default : begin
_zz_89 = (CsrPlugin_writeBackWasWfi ? writeBack_PC : prefetch_PC_CALC_WITHOUT_JUMP);
end
endcase
end
assign contextSwitching = _zz_74;
assign _zz_60 = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000)))));
assign _zz_59 = (decode_INSTRUCTION[13 : 7] != (7'b0100000));
always @ (*) begin
execute_CsrPlugin_illegalAccess = (execute_arbitration_isValid && execute_IS_CSR);
execute_CsrPlugin_readData = (32'b00000000000000000000000000000000);
case(execute_CsrPlugin_csrAddress)
12'b001100000000 : begin
execute_CsrPlugin_illegalAccess = 1'b0;
execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP;
execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE;
execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE;
end
12'b001101000100 : begin
execute_CsrPlugin_illegalAccess = 1'b0;
execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP;
execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP;
execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP;
end
12'b001100000100 : begin
execute_CsrPlugin_illegalAccess = 1'b0;
execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE;
execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE;
execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE;
end
12'b001101000010 : begin
if(execute_CSR_READ_OPCODE)begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt;
execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode;
end
default : begin
end
endcase
if((_zz_76 < execute_CsrPlugin_csrAddress[9 : 8]))begin
execute_CsrPlugin_illegalAccess = 1'b1;
end
end
assign execute_CsrPlugin_writeSrc = (execute_INSTRUCTION[14] ? _zz_153 : execute_SRC1);
always @ (*) begin
case(_zz_147)
1'b0 : begin
execute_CsrPlugin_writeData = execute_CsrPlugin_writeSrc;
end
default : begin
execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (memory_REGFILE_WRITE_DATA & (~ execute_CsrPlugin_writeSrc)) : (memory_REGFILE_WRITE_DATA | execute_CsrPlugin_writeSrc));
end
endcase
end
assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE);
assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE);
assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && execute_CsrPlugin_readDataRegValid);
assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_readDataRegValid));
assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20];
assign _zz_92 = ((decode_INSTRUCTION & (32'b00000000000000000110000000000100)) == (32'b00000000000000000010000000000000));
assign _zz_93 = ((decode_INSTRUCTION & (32'b00000000000000000000000000010100)) == (32'b00000000000000000000000000000100));
assign _zz_94 = ((decode_INSTRUCTION & (32'b00000000000000000000000000010000)) == (32'b00000000000000000000000000010000));
assign _zz_95 = ((decode_INSTRUCTION & (32'b00000000000000000000000001010000)) == (32'b00000000000000000000000001010000));
assign _zz_96 = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000000000));
assign _zz_97 = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100));
assign _zz_91 = {({(_zz_187 == _zz_188),_zz_97} != (2'b00)),{({_zz_97,{_zz_189,_zz_190}} != (3'b000)),{(_zz_94 != (1'b0)),{(_zz_191 != _zz_192),{_zz_193,{_zz_194,_zz_195}}}}}};
assign _zz_57 = _zz_154[0];
assign _zz_56 = _zz_155[0];
assign _zz_55 = _zz_156[0];
assign _zz_54 = _zz_157[0];
assign _zz_98 = _zz_91[5 : 4];
assign _zz_53 = _zz_98;
assign _zz_99 = _zz_91[7 : 6];
assign _zz_52 = _zz_99;
assign _zz_51 = _zz_158[0];
assign _zz_100 = _zz_91[10 : 9];
assign _zz_50 = _zz_100;
assign _zz_49 = _zz_159[0];
assign _zz_48 = _zz_160[0];
assign _zz_101 = _zz_91[14 : 13];
assign _zz_47 = _zz_101;
assign _zz_46 = _zz_161[0];
assign _zz_102 = _zz_91[17 : 16];
assign _zz_45 = _zz_102;
assign _zz_44 = _zz_162[0];
assign _zz_103 = _zz_91[20 : 19];
assign _zz_43 = _zz_103;
assign _zz_42 = _zz_163[0];
assign _zz_104 = _zz_91[23 : 22];
assign _zz_41 = _zz_104;
assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15];
assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20];
assign _zz_105 = 1'b1;
assign decode_RegFilePlugin_rs1Data = _zz_133;
assign _zz_106 = 1'b1;
assign decode_RegFilePlugin_rs2Data = _zz_134;
assign _zz_40 = decode_RegFilePlugin_rs1Data;
assign _zz_39 = decode_RegFilePlugin_rs2Data;
always @ (*) begin
writeBack_RegFilePlugin_regFileWrite_valid = (_zz_37 && writeBack_arbitration_isFiring);
if(_zz_107)begin
writeBack_RegFilePlugin_regFileWrite_valid = 1'b1;
end
end
assign writeBack_RegFilePlugin_regFileWrite_payload_address = _zz_36[11 : 7];
assign writeBack_RegFilePlugin_regFileWrite_payload_data = _zz_62;
always @ (*) begin
case(execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequancial_AND_1 : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2);
end
`AluBitwiseCtrlEnum_binary_sequancial_OR_1 : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2);
end
`AluBitwiseCtrlEnum_binary_sequancial_XOR_1 : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2);
end
default : begin
execute_IntAluPlugin_bitwise = execute_SRC1;
end
endcase
end
always @ (*) begin
case(execute_ALU_CTRL)
`AluCtrlEnum_binary_sequancial_BITWISE : begin
_zz_108 = execute_IntAluPlugin_bitwise;
end
`AluCtrlEnum_binary_sequancial_SLT_SLTU : begin
_zz_108 = {31'd0, _zz_164};
end
default : begin
_zz_108 = execute_SRC_ADD_SUB;
end
endcase
end
assign _zz_34 = _zz_108;
always @ (*) begin
case(decode_SRC1_CTRL)
`Src1CtrlEnum_binary_sequancial_RS : begin
_zz_109 = _zz_30;
end
`Src1CtrlEnum_binary_sequancial_FOUR : begin
_zz_109 = (32'b00000000000000000000000000000100);
end
default : begin
_zz_109 = {decode_INSTRUCTION[31 : 12],(12'b000000000000)};
end
endcase
end
assign _zz_32 = _zz_109;
assign _zz_110 = _zz_165[11];
always @ (*) begin
_zz_111[19] = _zz_110;
_zz_111[18] = _zz_110;
_zz_111[17] = _zz_110;
_zz_111[16] = _zz_110;
_zz_111[15] = _zz_110;
_zz_111[14] = _zz_110;
_zz_111[13] = _zz_110;
_zz_111[12] = _zz_110;
_zz_111[11] = _zz_110;
_zz_111[10] = _zz_110;
_zz_111[9] = _zz_110;
_zz_111[8] = _zz_110;
_zz_111[7] = _zz_110;
_zz_111[6] = _zz_110;
_zz_111[5] = _zz_110;
_zz_111[4] = _zz_110;
_zz_111[3] = _zz_110;
_zz_111[2] = _zz_110;
_zz_111[1] = _zz_110;
_zz_111[0] = _zz_110;
end
assign _zz_112 = _zz_166[11];
always @ (*) begin
_zz_113[19] = _zz_112;
_zz_113[18] = _zz_112;
_zz_113[17] = _zz_112;
_zz_113[16] = _zz_112;
_zz_113[15] = _zz_112;
_zz_113[14] = _zz_112;
_zz_113[13] = _zz_112;
_zz_113[12] = _zz_112;
_zz_113[11] = _zz_112;
_zz_113[10] = _zz_112;
_zz_113[9] = _zz_112;
_zz_113[8] = _zz_112;
_zz_113[7] = _zz_112;
_zz_113[6] = _zz_112;
_zz_113[5] = _zz_112;
_zz_113[4] = _zz_112;
_zz_113[3] = _zz_112;
_zz_113[2] = _zz_112;
_zz_113[1] = _zz_112;
_zz_113[0] = _zz_112;
end
always @ (*) begin
case(decode_SRC2_CTRL)
`Src2CtrlEnum_binary_sequancial_RS : begin
_zz_114 = _zz_27;
end
`Src2CtrlEnum_binary_sequancial_IMI : begin
_zz_114 = {_zz_111,decode_INSTRUCTION[31 : 20]};
end
`Src2CtrlEnum_binary_sequancial_IMS : begin
_zz_114 = {_zz_113,{decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}};
end
default : begin
_zz_114 = _zz_26;
end
endcase
end
assign _zz_29 = _zz_114;
assign execute_SrcPlugin_addSub = _zz_167;
assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31]));
assign _zz_25 = execute_SrcPlugin_addSub;
assign _zz_24 = execute_SrcPlugin_addSub;
assign _zz_23 = execute_SrcPlugin_less;
assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_binary_sequancial_DISABLE_1);
assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]);
assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? memory_REGFILE_WRITE_DATA : execute_SRC1);
assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == (4'b0000));
always @ (*) begin
case(execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequancial_SLL_1 : begin
_zz_115 = (execute_LightShifterPlugin_shiftInput <<< 1);
end
default : begin
_zz_115 = _zz_175;
end
endcase
end
always @ (*) begin
_zz_116 = 1'b0;
_zz_117 = 1'b0;
if(_zz_118)begin
if((_zz_119 == decode_INSTRUCTION[19 : 15]))begin
_zz_116 = 1'b1;
end
if((_zz_119 == decode_INSTRUCTION[24 : 20]))begin
_zz_117 = 1'b1;
end
end
if((writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID))begin
if((1'b1 || (! 1'b1)))begin
if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin
_zz_116 = 1'b1;
end
if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin
_zz_117 = 1'b1;
end
end
end
if((memory_arbitration_isValid && memory_REGFILE_WRITE_VALID))begin
if((1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)))begin
if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin
_zz_116 = 1'b1;
end
if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin
_zz_117 = 1'b1;
end
end
end
if((execute_arbitration_isValid && execute_REGFILE_WRITE_VALID))begin
if((1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)))begin
if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin
_zz_116 = 1'b1;
end
if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin
_zz_117 = 1'b1;
end
end
end
if((! decode_RS1_USE))begin
_zz_116 = 1'b0;
end
if((! decode_RS2_USE))begin
_zz_117 = 1'b0;
end
end
assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2);
assign _zz_120 = execute_INSTRUCTION[14 : 12];
always @ (*) begin
if((_zz_120 == (3'b000))) begin
_zz_121 = execute_BranchPlugin_eq;
end else if((_zz_120 == (3'b001))) begin
_zz_121 = (! execute_BranchPlugin_eq);
end else if((((_zz_120 & (3'b101)) == (3'b101)))) begin
_zz_121 = (! execute_SRC_LESS);
end else begin
_zz_121 = execute_SRC_LESS;
end
end
always @ (*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequancial_INC : begin
_zz_122 = 1'b0;
end
`BranchCtrlEnum_binary_sequancial_JAL : begin
_zz_122 = 1'b1;
end
`BranchCtrlEnum_binary_sequancial_JALR : begin
_zz_122 = 1'b1;
end
default : begin
_zz_122 = _zz_121;
end
endcase
end
assign _zz_21 = _zz_122;
assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequancial_JALR) ? execute_RS1 : execute_PC);
assign _zz_123 = _zz_177[19];
always @ (*) begin
_zz_124[10] = _zz_123;
_zz_124[9] = _zz_123;
_zz_124[8] = _zz_123;
_zz_124[7] = _zz_123;
_zz_124[6] = _zz_123;
_zz_124[5] = _zz_123;
_zz_124[4] = _zz_123;
_zz_124[3] = _zz_123;
_zz_124[2] = _zz_123;
_zz_124[1] = _zz_123;
_zz_124[0] = _zz_123;
end
assign _zz_125 = _zz_178[11];
always @ (*) begin
_zz_126[19] = _zz_125;
_zz_126[18] = _zz_125;
_zz_126[17] = _zz_125;
_zz_126[16] = _zz_125;
_zz_126[15] = _zz_125;
_zz_126[14] = _zz_125;
_zz_126[13] = _zz_125;
_zz_126[12] = _zz_125;
_zz_126[11] = _zz_125;
_zz_126[10] = _zz_125;
_zz_126[9] = _zz_125;
_zz_126[8] = _zz_125;
_zz_126[7] = _zz_125;
_zz_126[6] = _zz_125;
_zz_126[5] = _zz_125;
_zz_126[4] = _zz_125;
_zz_126[3] = _zz_125;
_zz_126[2] = _zz_125;
_zz_126[1] = _zz_125;
_zz_126[0] = _zz_125;
end
assign _zz_127 = _zz_179[11];
always @ (*) begin
_zz_128[18] = _zz_127;
_zz_128[17] = _zz_127;
_zz_128[16] = _zz_127;
_zz_128[15] = _zz_127;
_zz_128[14] = _zz_127;
_zz_128[13] = _zz_127;
_zz_128[12] = _zz_127;
_zz_128[11] = _zz_127;
_zz_128[10] = _zz_127;
_zz_128[9] = _zz_127;
_zz_128[8] = _zz_127;
_zz_128[7] = _zz_127;
_zz_128[6] = _zz_127;
_zz_128[5] = _zz_127;
_zz_128[4] = _zz_127;
_zz_128[3] = _zz_127;
_zz_128[2] = _zz_127;
_zz_128[1] = _zz_127;
_zz_128[0] = _zz_127;
end
always @ (*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequancial_JAL : begin
_zz_129 = {{_zz_124,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0};
end
`BranchCtrlEnum_binary_sequancial_JALR : begin
_zz_129 = {_zz_126,execute_INSTRUCTION[31 : 20]};
end
default : begin
_zz_129 = {{_zz_128,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0};
end
endcase
end
assign execute_BranchPlugin_branch_src2 = _zz_129;
assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2);
assign _zz_19 = {execute_BranchPlugin_branchAdder[31 : 1],((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequancial_JALR) ? 1'b0 : execute_BranchPlugin_branchAdder[0])};
assign _zz_78 = (memory_arbitration_isFiring && memory_BRANCH_DO);
assign DebugPlugin_isPipBusy = (DebugPlugin_isPipActive || _zz_130);
always @ (*) begin
debug_bus_rsp_data = DebugPlugin_busReadDataReg;
if((! _zz_131))begin
debug_bus_rsp_data[0] = DebugPlugin_resetIt;
debug_bus_rsp_data[1] = DebugPlugin_haltIt;
debug_bus_rsp_data[2] = DebugPlugin_isPipBusy;
debug_bus_rsp_data[3] = DebugPlugin_haltedByBreak;
debug_bus_rsp_data[4] = DebugPlugin_stepIt;
end
end
assign debug_resetOut = _zz_132;
assign _zz_18 = decode_ALU_BITWISE_CTRL;
assign _zz_16 = _zz_41;
assign _zz_35 = decode_to_execute_ALU_BITWISE_CTRL;
assign _zz_15 = decode_ENV_CTRL;
assign _zz_12 = execute_ENV_CTRL;
assign _zz_13 = _zz_43;
assign _zz_10 = decode_to_execute_ENV_CTRL;
assign _zz_61 = execute_to_memory_ENV_CTRL;
assign _zz_31 = _zz_53;
assign _zz_9 = decode_ALU_CTRL;
assign _zz_7 = _zz_47;
assign _zz_33 = decode_to_execute_ALU_CTRL;
assign _zz_28 = _zz_45;
assign _zz_6 = decode_BRANCH_CTRL;
assign _zz_4 = _zz_52;
assign _zz_20 = decode_to_execute_BRANCH_CTRL;
assign _zz_3 = decode_SHIFT_CTRL;
assign _zz_1 = _zz_50;
assign _zz_22 = decode_to_execute_SHIFT_CTRL;
assign prefetch_arbitration_isFlushed = (((((prefetch_arbitration_flushAll || fetch_arbitration_flushAll) || decode_arbitration_flushAll) || execute_arbitration_flushAll) || memory_arbitration_flushAll) || writeBack_arbitration_flushAll);
assign fetch_arbitration_isFlushed = ((((fetch_arbitration_flushAll || decode_arbitration_flushAll) || execute_arbitration_flushAll) || memory_arbitration_flushAll) || writeBack_arbitration_flushAll);
assign decode_arbitration_isFlushed = (((decode_arbitration_flushAll || execute_arbitration_flushAll) || memory_arbitration_flushAll) || writeBack_arbitration_flushAll);
assign execute_arbitration_isFlushed = ((execute_arbitration_flushAll || memory_arbitration_flushAll) || writeBack_arbitration_flushAll);
assign memory_arbitration_isFlushed = (memory_arbitration_flushAll || writeBack_arbitration_flushAll);
assign writeBack_arbitration_isFlushed = writeBack_arbitration_flushAll;
assign prefetch_arbitration_isStuckByOthers = (prefetch_arbitration_haltByOther || (((((1'b0 || fetch_arbitration_haltItself) || decode_arbitration_haltItself) || execute_arbitration_haltItself) || memory_arbitration_haltItself) || writeBack_arbitration_haltItself));
assign prefetch_arbitration_isStuck = (prefetch_arbitration_haltItself || prefetch_arbitration_isStuckByOthers);
assign prefetch_arbitration_isMoving = ((! prefetch_arbitration_isStuck) && (! prefetch_arbitration_removeIt));
assign prefetch_arbitration_isFiring = ((prefetch_arbitration_isValid && (! prefetch_arbitration_isStuck)) && (! prefetch_arbitration_removeIt));
assign fetch_arbitration_isStuckByOthers = (fetch_arbitration_haltByOther || ((((1'b0 || decode_arbitration_haltItself) || execute_arbitration_haltItself) || memory_arbitration_haltItself) || writeBack_arbitration_haltItself));
assign fetch_arbitration_isStuck = (fetch_arbitration_haltItself || fetch_arbitration_isStuckByOthers);
assign fetch_arbitration_isMoving = ((! fetch_arbitration_isStuck) && (! fetch_arbitration_removeIt));
assign fetch_arbitration_isFiring = ((fetch_arbitration_isValid && (! fetch_arbitration_isStuck)) && (! fetch_arbitration_removeIt));
assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_haltItself) || memory_arbitration_haltItself) || writeBack_arbitration_haltItself));
assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers);
assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt));
assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt));
assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_haltItself) || writeBack_arbitration_haltItself));
assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers);
assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt));
assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt));
assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_haltItself));
assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers);
assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt));
assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt));
assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0);
assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers);
assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt));
assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt));
always @ (posedge io_mainClk or posedge resetCtrl_systemReset) begin
if (resetCtrl_systemReset) begin
prefetch_arbitration_isValid <= 1'b0;
fetch_arbitration_isValid <= 1'b0;
decode_arbitration_isValid <= 1'b0;
execute_arbitration_isValid <= 1'b0;
memory_arbitration_isValid <= 1'b0;
writeBack_arbitration_isValid <= 1'b0;
_zz_76 <= (2'b11);
prefetch_PcManagerSimplePlugin_pcReg <= (32'b10000000000000000000000000000000);
prefetch_IBusSimplePlugin_pendingCmd <= 1'b0;
_zz_81 <= 1'b0;
CsrPlugin_mstatus_MIE <= 1'b0;
CsrPlugin_mstatus_MPIE <= 1'b0;
CsrPlugin_mstatus_MPP <= (2'b11);
CsrPlugin_mip_MEIP <= 1'b0;
CsrPlugin_mip_MTIP <= 1'b0;
CsrPlugin_mip_MSIP <= 1'b0;
CsrPlugin_mie_MEIE <= 1'b0;
CsrPlugin_mie_MTIE <= 1'b0;
CsrPlugin_mie_MSIE <= 1'b0;
_zz_107 <= 1'b1;
execute_LightShifterPlugin_isActive <= 1'b0;
_zz_118 <= 1'b0;
memory_to_writeBack_REGFILE_WRITE_DATA <= (32'b00000000000000000000000000000000);
memory_to_writeBack_INSTRUCTION <= (32'b00000000000000000000000000000000);
end else begin
prefetch_arbitration_isValid <= 1'b1;
if(prefetch_arbitration_isFiring)begin
prefetch_PcManagerSimplePlugin_pcReg <= prefetch_PcManagerSimplePlugin_pcPlus4;
end
if(prefetch_PcManagerSimplePlugin_jump_pcLoad_valid)begin
prefetch_PcManagerSimplePlugin_pcReg <= prefetch_PcManagerSimplePlugin_jump_pcLoad_payload;
end
if(iBus_rsp_ready)begin
prefetch_IBusSimplePlugin_pendingCmd <= 1'b0;
end
if((_zz_135 && iBus_cmd_ready))begin
prefetch_IBusSimplePlugin_pendingCmd <= 1'b1;
end
if(iBus_rsp_ready)begin
_zz_81 <= 1'b1;
end
if((! fetch_arbitration_isStuck))begin
_zz_81 <= 1'b0;
end
CsrPlugin_mip_MEIP <= externalInterrupt;
CsrPlugin_mip_MTIP <= timerInterrupt;
if(_zz_145)begin
CsrPlugin_mstatus_MIE <= 1'b0;
CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE;
CsrPlugin_mstatus_MPP <= _zz_76;
end
if(_zz_144)begin
if(memory_arbitration_isFiring)begin
CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE;
_zz_76 <= CsrPlugin_mstatus_MPP;
end
end
_zz_107 <= 1'b0;
if(_zz_141)begin
if(_zz_142)begin
execute_LightShifterPlugin_isActive <= 1'b1;
if(execute_LightShifterPlugin_done)begin
execute_LightShifterPlugin_isActive <= 1'b0;
end
end
end
if(execute_arbitration_removeIt)begin
execute_LightShifterPlugin_isActive <= 1'b0;
end
_zz_118 <= (_zz_37 && writeBack_arbitration_isFiring);
if(debug_bus_cmd_valid)begin
case(_zz_143)
1'b0 : begin
end
default : begin
if(debug_bus_cmd_payload_wr)begin
if(DebugPlugin_firstCycle)begin
decode_arbitration_isValid <= 1'b1;
end
end
end
endcase
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_REGFILE_WRITE_DATA <= memory_REGFILE_WRITE_DATA;
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION;
end
if(((! fetch_arbitration_isStuck) || fetch_arbitration_removeIt))begin
fetch_arbitration_isValid <= 1'b0;
end
if(((! prefetch_arbitration_isStuck) && (! prefetch_arbitration_removeIt)))begin
fetch_arbitration_isValid <= prefetch_arbitration_isValid;
end
if(((! decode_arbitration_isStuck) || decode_arbitration_removeIt))begin
decode_arbitration_isValid <= 1'b0;
end
if(((! fetch_arbitration_isStuck) && (! fetch_arbitration_removeIt)))begin
decode_arbitration_isValid <= fetch_arbitration_isValid;
end
if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin
execute_arbitration_isValid <= 1'b0;
end
if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin
execute_arbitration_isValid <= decode_arbitration_isValid;
end
if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin
memory_arbitration_isValid <= 1'b0;
end
if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin
memory_arbitration_isValid <= execute_arbitration_isValid;
end
if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin
writeBack_arbitration_isValid <= 1'b0;
end
if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin
writeBack_arbitration_isValid <= memory_arbitration_isValid;
end
case(execute_CsrPlugin_csrAddress)
12'b001100000000 : begin
if(execute_CsrPlugin_writeEnable)begin
CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11];
CsrPlugin_mstatus_MPIE <= _zz_180[0];
CsrPlugin_mstatus_MIE <= _zz_181[0];
end
end
12'b001101000100 : begin
if(execute_CsrPlugin_writeEnable)begin
CsrPlugin_mip_MSIP <= _zz_182[0];
end
end
12'b001100000100 : begin
if(execute_CsrPlugin_writeEnable)begin
CsrPlugin_mie_MEIE <= _zz_183[0];
CsrPlugin_mie_MTIE <= _zz_184[0];
CsrPlugin_mie_MSIE <= _zz_185[0];
end
end
12'b001101000010 : begin
end
default : begin
end
endcase
end
end
always @ (posedge io_mainClk) begin
if((! _zz_81))begin
_zz_82 <= iBus_rsp_inst;
end
if (!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin
$display("ERROR DBusSimplePlugin doesn't allow memory stage stall when read happend");
end
if (!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_INSTRUCTION[5])) && writeBack_arbitration_isStuck))) begin
$display("ERROR DBusSimplePlugin doesn't allow memory stage stall when read happend");
end
CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001));
if(writeBack_arbitration_isFiring)begin
CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001));
end
if(_zz_145)begin
CsrPlugin_mepc <= _zz_89;
CsrPlugin_mcause_interrupt <= CsrPlugin_interrupt;
CsrPlugin_mcause_exceptionCode <= ((CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE) ? (4'b1011) : _zz_151);
end
_zz_90 <= CsrPlugin_exception;
if(_zz_90)begin
CsrPlugin_mbadaddr <= (32'b00000000000000000000000000000000);
CsrPlugin_mcause_exceptionCode <= (4'b0000);
end
if(execute_arbitration_isValid)begin
execute_CsrPlugin_readDataRegValid <= 1'b1;
end
if((! execute_arbitration_isStuck))begin
execute_CsrPlugin_readDataRegValid <= 1'b0;
end
if(_zz_141)begin
if(_zz_142)begin
execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - (5'b00001));
end
end
_zz_119 <= _zz_36[11 : 7];
if((! execute_arbitration_isStuck))begin
decode_to_execute_IS_EBREAK <= decode_IS_EBREAK;
end
if((! fetch_arbitration_isStuck))begin
prefetch_to_fetch_PC <= _zz_69;
end
if((! decode_arbitration_isStuck))begin
fetch_to_decode_PC <= fetch_PC;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_PC <= _zz_26;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_PC <= execute_PC;
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_PC <= memory_PC;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_REGFILE_WRITE_DATA <= _zz_58;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_ALU_BITWISE_CTRL <= _zz_17;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_RS2 <= _zz_27;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_SRC2 <= decode_SRC2;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE;
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_ENV_CTRL <= _zz_14;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_ENV_CTRL <= _zz_11;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_SRC1 <= decode_SRC1;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_ALU_CTRL <= _zz_8;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_BRANCH_DO <= execute_BRANCH_DO;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_RS1 <= _zz_30;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_IS_CSR <= decode_IS_CSR;
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_BRANCH_CTRL <= _zz_5;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID;
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_SHIFT_CTRL <= _zz_2;
end
if((! decode_arbitration_isStuck))begin
fetch_to_decode_INSTRUCTION <= _zz_66;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_INSTRUCTION <= decode_INSTRUCTION;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_INSTRUCTION <= execute_INSTRUCTION;
end
if((! fetch_arbitration_isStuck))begin
prefetch_to_fetch_FORMAL_PC_NEXT <= prefetch_FORMAL_PC_NEXT;
end
if((! decode_arbitration_isStuck))begin
fetch_to_decode_FORMAL_PC_NEXT <= fetch_FORMAL_PC_NEXT;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_FORMAL_PC_NEXT <= decode_FORMAL_PC_NEXT;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_FORMAL_PC_NEXT <= _zz_70;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW;
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW;
end
if(DebugPlugin_insertDecodeInstruction)begin
fetch_to_decode_INSTRUCTION <= debug_bus_cmd_payload_data;
end
end
always @ (posedge io_mainClk) begin
DebugPlugin_firstCycle <= 1'b0;
if(_zz_138)begin
DebugPlugin_firstCycle <= 1'b1;
end
DebugPlugin_secondCycle <= DebugPlugin_firstCycle;
DebugPlugin_isPipActive <= ((((fetch_arbitration_isValid || decode_arbitration_isValid) || execute_arbitration_isValid) || memory_arbitration_isValid) || writeBack_arbitration_isValid);
_zz_130 <= DebugPlugin_isPipActive;
if(writeBack_arbitration_isValid)begin
DebugPlugin_busReadDataReg <= _zz_62;
end
_zz_131 <= debug_bus_cmd_payload_address[2];
_zz_132 <= DebugPlugin_resetIt;
end
always @ (posedge io_mainClk or posedge resetCtrl_mainClkReset) begin
if (resetCtrl_mainClkReset) begin
DebugPlugin_resetIt <= 1'b0;
DebugPlugin_haltIt <= 1'b0;
DebugPlugin_stepIt <= 1'b0;
DebugPlugin_haltedByBreak <= 1'b0;
end else begin
if(debug_bus_cmd_valid)begin
case(_zz_143)
1'b0 : begin
if(debug_bus_cmd_payload_wr)begin
DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4];
if(debug_bus_cmd_payload_data[16])begin
DebugPlugin_resetIt <= 1'b1;
end
if(debug_bus_cmd_payload_data[24])begin
DebugPlugin_resetIt <= 1'b0;
end
if(debug_bus_cmd_payload_data[17])begin
DebugPlugin_haltIt <= 1'b1;
end
if(debug_bus_cmd_payload_data[25])begin
DebugPlugin_haltIt <= 1'b0;
end
if(debug_bus_cmd_payload_data[25])begin
DebugPlugin_haltedByBreak <= 1'b0;
end
end
end
default : begin
end
endcase
end
if(_zz_140)begin
DebugPlugin_haltIt <= 1'b1;
DebugPlugin_haltedByBreak <= 1'b1;
end
if((DebugPlugin_stepIt && prefetch_arbitration_isFiring))begin
DebugPlugin_haltIt <= 1'b1;
end
if((DebugPlugin_stepIt && ({writeBack_arbitration_redoIt,{memory_arbitration_redoIt,{execute_arbitration_redoIt,{decode_arbitration_redoIt,{fetch_arbitration_redoIt,prefetch_arbitration_redoIt}}}}} != (6'b000000))))begin
DebugPlugin_haltIt <= 1'b0;
end
end
end
endmodule
module JtagBridge (
input io_jtag_tms,
input io_jtag_tdi,
output reg io_jtag_tdo,
input io_jtag_tck,
output io_remote_cmd_valid,
input io_remote_cmd_ready,
output io_remote_cmd_payload_last,
output [0:0] io_remote_cmd_payload_fragment,
input io_remote_rsp_valid,
output io_remote_rsp_ready,
input io_remote_rsp_payload_error,
input [31:0] io_remote_rsp_payload_data,
input io_mainClk,
input resetCtrl_mainClkReset);
wire _zz_2;
wire _zz_3;
wire _zz_4;
wire _zz_5;
wire [0:0] _zz_6;
wire _zz_7;
wire _zz_8;
wire [3:0] _zz_9;
wire [3:0] _zz_10;
wire [3:0] _zz_11;
wire system_cmd_valid;
wire system_cmd_payload_last;
wire [0:0] system_cmd_payload_fragment;
reg system_rsp_valid;
reg system_rsp_payload_error;
reg [31:0] system_rsp_payload_data;
wire `JtagState_binary_sequancial_type jtag_tap_fsm_stateNext;
reg `JtagState_binary_sequancial_type jtag_tap_fsm_state = `JtagState_binary_sequancial_IR_UPDATE;
reg `JtagState_binary_sequancial_type _zz_1;
reg [3:0] jtag_tap_instruction;
reg [3:0] jtag_tap_instructionShift;
reg jtag_tap_bypass;
wire [0:0] jtag_idcodeArea_instructionId;
wire jtag_idcodeArea_instructionHit;
reg [31:0] jtag_idcodeArea_shifter;
wire [1:0] jtag_writeArea_instructionId;
wire jtag_writeArea_instructionHit;
reg jtag_writeArea_source_valid;
wire jtag_writeArea_source_payload_last;
wire [0:0] jtag_writeArea_source_payload_fragment;
wire [1:0] jtag_readArea_instructionId;
wire jtag_readArea_instructionHit;
reg [33:0] jtag_readArea_shifter;
assign io_remote_cmd_valid = _zz_2;
assign io_remote_rsp_ready = _zz_3;
assign _zz_7 = (jtag_tap_fsm_state == `JtagState_binary_sequancial_DR_SHIFT);
assign _zz_8 = (jtag_tap_fsm_state == `JtagState_binary_sequancial_DR_SHIFT);
assign _zz_9 = {3'd0, jtag_idcodeArea_instructionId};
assign _zz_10 = {2'd0, jtag_writeArea_instructionId};
assign _zz_11 = {2'd0, jtag_readArea_instructionId};
FlowCCByToggle flowCCByToggle_1 (
.io_input_valid(jtag_writeArea_source_valid),
.io_input_payload_last(jtag_writeArea_source_payload_last),
.io_input_payload_fragment(jtag_writeArea_source_payload_fragment),
.io_output_valid(_zz_4),
.io_output_payload_last(_zz_5),
.io_output_payload_fragment(_zz_6),
.io_jtag_tck(io_jtag_tck),
.io_mainClk(io_mainClk),
.resetCtrl_mainClkReset(resetCtrl_mainClkReset)
);
assign _zz_2 = system_cmd_valid;
assign io_remote_cmd_payload_last = system_cmd_payload_last;
assign io_remote_cmd_payload_fragment = system_cmd_payload_fragment;
assign _zz_3 = 1'b1;
always @ (*) begin
case(jtag_tap_fsm_state)
`JtagState_binary_sequancial_IDLE : begin
_zz_1 = (io_jtag_tms ? `JtagState_binary_sequancial_DR_SELECT : `JtagState_binary_sequancial_IDLE);
end
`JtagState_binary_sequancial_IR_SELECT : begin
_zz_1 = (io_jtag_tms ? `JtagState_binary_sequancial_RESET : `JtagState_binary_sequancial_IR_CAPTURE);
end
`JtagState_binary_sequancial_IR_CAPTURE : begin
_zz_1 = (io_jtag_tms ? `JtagState_binary_sequancial_IR_EXIT1 : `JtagState_binary_sequancial_IR_SHIFT);
end
`JtagState_binary_sequancial_IR_SHIFT : begin
_zz_1 = (io_jtag_tms ? `JtagState_binary_sequancial_IR_EXIT1 : `JtagState_binary_sequancial_IR_SHIFT);
end
`JtagState_binary_sequancial_IR_EXIT1 : begin
_zz_1 = (io_jtag_tms ? `JtagState_binary_sequancial_IR_UPDATE : `JtagState_binary_sequancial_IR_PAUSE);
end
`JtagState_binary_sequancial_IR_PAUSE : begin
_zz_1 = (io_jtag_tms ? `JtagState_binary_sequancial_IR_EXIT2 : `JtagState_binary_sequancial_IR_PAUSE);
end
`JtagState_binary_sequancial_IR_EXIT2 : begin
_zz_1 = (io_jtag_tms ? `JtagState_binary_sequancial_IR_UPDATE : `JtagState_binary_sequancial_IR_SHIFT);
end
`JtagState_binary_sequancial_IR_UPDATE : begin
_zz_1 = (io_jtag_tms ? `JtagState_binary_sequancial_DR_SELECT : `JtagState_binary_sequancial_IDLE);
end
`JtagState_binary_sequancial_DR_SELECT : begin
_zz_1 = (io_jtag_tms ? `JtagState_binary_sequancial_IR_SELECT : `JtagState_binary_sequancial_DR_CAPTURE);
end
`JtagState_binary_sequancial_DR_CAPTURE : begin
_zz_1 = (io_jtag_tms ? `JtagState_binary_sequancial_DR_EXIT1 : `JtagState_binary_sequancial_DR_SHIFT);
end
`JtagState_binary_sequancial_DR_SHIFT : begin
_zz_1 = (io_jtag_tms ? `JtagState_binary_sequancial_DR_EXIT1 : `JtagState_binary_sequancial_DR_SHIFT);
end
`JtagState_binary_sequancial_DR_EXIT1 : begin
_zz_1 = (io_jtag_tms ? `JtagState_binary_sequancial_DR_UPDATE : `JtagState_binary_sequancial_DR_PAUSE);
end
`JtagState_binary_sequancial_DR_PAUSE : begin
_zz_1 = (io_jtag_tms ? `JtagState_binary_sequancial_DR_EXIT2 : `JtagState_binary_sequancial_DR_PAUSE);
end
`JtagState_binary_sequancial_DR_EXIT2 : begin
_zz_1 = (io_jtag_tms ? `JtagState_binary_sequancial_DR_UPDATE : `JtagState_binary_sequancial_DR_SHIFT);
end
`JtagState_binary_sequancial_DR_UPDATE : begin
_zz_1 = (io_jtag_tms ? `JtagState_binary_sequancial_DR_SELECT : `JtagState_binary_sequancial_IDLE);
end
default : begin
_zz_1 = (io_jtag_tms ? `JtagState_binary_sequancial_RESET : `JtagState_binary_sequancial_IDLE);
end
endcase
end
assign jtag_tap_fsm_stateNext = _zz_1;
always @ (*) begin
io_jtag_tdo = jtag_tap_bypass;
case(jtag_tap_fsm_state)
`JtagState_binary_sequancial_IR_CAPTURE : begin
end
`JtagState_binary_sequancial_IR_SHIFT : begin
io_jtag_tdo = jtag_tap_instructionShift[0];
end
`JtagState_binary_sequancial_IR_UPDATE : begin
end
`JtagState_binary_sequancial_DR_SHIFT : begin
end
default : begin
end
endcase
if(jtag_idcodeArea_instructionHit)begin
if(_zz_8)begin
io_jtag_tdo = jtag_idcodeArea_shifter[0];
end
end
if(jtag_readArea_instructionHit)begin
if(_zz_7)begin
io_jtag_tdo = jtag_readArea_shifter[0];
end
end
end
assign jtag_idcodeArea_instructionId = (1'b1);
assign jtag_idcodeArea_instructionHit = (jtag_tap_instruction == _zz_9);
assign jtag_writeArea_instructionId = (2'b10);
assign jtag_writeArea_instructionHit = (jtag_tap_instruction == _zz_10);
always @ (*) begin
jtag_writeArea_source_valid = 1'b0;
if(jtag_writeArea_instructionHit)begin
if((jtag_tap_fsm_state == `JtagState_binary_sequancial_DR_SHIFT))begin
jtag_writeArea_source_valid = 1'b1;
end
end
end
assign jtag_writeArea_source_payload_last = io_jtag_tms;
assign jtag_writeArea_source_payload_fragment[0] = io_jtag_tdi;
assign system_cmd_valid = _zz_4;
assign system_cmd_payload_last = _zz_5;
assign system_cmd_payload_fragment = _zz_6;
assign jtag_readArea_instructionId = (2'b11);
assign jtag_readArea_instructionHit = (jtag_tap_instruction == _zz_11);
always @ (posedge io_mainClk) begin
if(_zz_2)begin
system_rsp_valid <= 1'b0;
end
if((io_remote_rsp_valid && _zz_3))begin
system_rsp_valid <= 1'b1;
system_rsp_payload_error <= io_remote_rsp_payload_error;
system_rsp_payload_data <= io_remote_rsp_payload_data;
end
end
always @ (posedge io_jtag_tck) begin
jtag_tap_fsm_state <= jtag_tap_fsm_stateNext;
case(jtag_tap_fsm_state)
`JtagState_binary_sequancial_IR_CAPTURE : begin
jtag_tap_instructionShift <= jtag_tap_instruction;
end
`JtagState_binary_sequancial_IR_SHIFT : begin
jtag_tap_instructionShift <= ({io_jtag_tdi,jtag_tap_instructionShift} >>> 1);
end
`JtagState_binary_sequancial_IR_UPDATE : begin
jtag_tap_instruction <= jtag_tap_instructionShift;
end
`JtagState_binary_sequancial_DR_SHIFT : begin
jtag_tap_bypass <= io_jtag_tdi;
end
default : begin
end
endcase
if(jtag_idcodeArea_instructionHit)begin
if(_zz_8)begin
jtag_idcodeArea_shifter <= ({io_jtag_tdi,jtag_idcodeArea_shifter} >>> 1);
end
end
if((jtag_tap_fsm_state == `JtagState_binary_sequancial_RESET))begin
jtag_idcodeArea_shifter <= (32'b00010000000000000001111111111111);
jtag_tap_instruction <= {3'd0, jtag_idcodeArea_instructionId};
end
if(jtag_readArea_instructionHit)begin
if((jtag_tap_fsm_state == `JtagState_binary_sequancial_DR_CAPTURE))begin
jtag_readArea_shifter <= {{system_rsp_payload_data,system_rsp_payload_error},system_rsp_valid};
end
if(_zz_7)begin
jtag_readArea_shifter <= ({io_jtag_tdi,jtag_readArea_shifter} >>> 1);
end
end
end
endmodule
module SystemDebugger (
input io_remote_cmd_valid,
output io_remote_cmd_ready,
input io_remote_cmd_payload_last,
input [0:0] io_remote_cmd_payload_fragment,
output io_remote_rsp_valid,
input io_remote_rsp_ready,
output io_remote_rsp_payload_error,
output [31:0] io_remote_rsp_payload_data,
output io_mem_cmd_valid,
input io_mem_cmd_ready,
output [31:0] io_mem_cmd_payload_address,
output [31:0] io_mem_cmd_payload_data,
output io_mem_cmd_payload_wr,
output [1:0] io_mem_cmd_payload_size,
input io_mem_rsp_valid,
input [31:0] io_mem_rsp_payload,
input io_mainClk,
input resetCtrl_mainClkReset);
wire _zz_2;
wire _zz_3;
wire [0:0] _zz_4;
reg [66:0] dispatcher_dataShifter;
reg dispatcher_dataLoaded;
reg [7:0] dispatcher_headerShifter;
wire [7:0] dispatcher_header;
reg dispatcher_headerLoaded;
reg [2:0] dispatcher_counter;
wire [66:0] _zz_1;
assign io_mem_cmd_valid = _zz_2;
assign _zz_3 = (dispatcher_headerLoaded == 1'b0);
assign _zz_4 = _zz_1[64 : 64];
assign dispatcher_header = dispatcher_headerShifter[7 : 0];
assign io_remote_cmd_ready = (! dispatcher_dataLoaded);
assign _zz_1 = dispatcher_dataShifter[66 : 0];
assign io_mem_cmd_payload_address = _zz_1[31 : 0];
assign io_mem_cmd_payload_data = _zz_1[63 : 32];
assign io_mem_cmd_payload_wr = _zz_4[0];
assign io_mem_cmd_payload_size = _zz_1[66 : 65];
assign _zz_2 = (dispatcher_dataLoaded && (dispatcher_header == (8'b00000000)));
assign io_remote_rsp_valid = io_mem_rsp_valid;
assign io_remote_rsp_payload_error = 1'b0;
assign io_remote_rsp_payload_data = io_mem_rsp_payload;
always @ (posedge io_mainClk or posedge resetCtrl_mainClkReset) begin
if (resetCtrl_mainClkReset) begin
dispatcher_dataLoaded <= 1'b0;
dispatcher_headerLoaded <= 1'b0;
dispatcher_counter <= (3'b000);
end else begin
if(io_remote_cmd_valid)begin
if(_zz_3)begin
dispatcher_counter <= (dispatcher_counter + (3'b001));
if((dispatcher_counter == (3'b111)))begin
dispatcher_headerLoaded <= 1'b1;
end
end
if(io_remote_cmd_payload_last)begin
dispatcher_headerLoaded <= 1'b1;
dispatcher_dataLoaded <= 1'b1;
dispatcher_counter <= (3'b000);
end
end
if((_zz_2 && io_mem_cmd_ready))begin
dispatcher_headerLoaded <= 1'b0;
dispatcher_dataLoaded <= 1'b0;
end
end
end
always @ (posedge io_mainClk) begin
if(io_remote_cmd_valid)begin
if(_zz_3)begin
dispatcher_headerShifter <= ({io_remote_cmd_payload_fragment,dispatcher_headerShifter} >>> 1);
end else begin
dispatcher_dataShifter <= ({io_remote_cmd_payload_fragment,dispatcher_dataShifter} >>> 1);
end
end
end
endmodule
module MuraxSimpleBusRam (
input io_bus_cmd_valid,
output io_bus_cmd_ready,
input io_bus_cmd_payload_wr,
input [31:0] io_bus_cmd_payload_address,
input [31:0] io_bus_cmd_payload_data,
input [3:0] io_bus_cmd_payload_mask,
output io_bus_rsp_valid,
output [31:0] io_bus_rsp_payload_data,
input io_mainClk,
input resetCtrl_systemReset);
reg [31:0] _zz_4;
wire _zz_5;
wire [9:0] _zz_6;
reg _zz_1;
wire [29:0] _zz_2;
wire [31:0] _zz_3;
reg [7:0] ram_symbol0 [0:1023];
reg [7:0] ram_symbol1 [0:1023];
reg [7:0] ram_symbol2 [0:1023];
reg [7:0] ram_symbol3 [0:1023];
reg [7:0] _zz_7;
reg [7:0] _zz_8;
reg [7:0] _zz_9;
reg [7:0] _zz_10;
assign io_bus_cmd_ready = _zz_5;
assign _zz_6 = _zz_2[9:0];
initial begin
$readmemb("Murax.v_toplevel_system_ram_ram_symbol0.bin",ram_symbol0);
$readmemb("Murax.v_toplevel_system_ram_ram_symbol1.bin",ram_symbol1);
$readmemb("Murax.v_toplevel_system_ram_ram_symbol2.bin",ram_symbol2);
$readmemb("Murax.v_toplevel_system_ram_ram_symbol3.bin",ram_symbol3);
end
always @ (*) begin
_zz_4 = {_zz_10, _zz_9, _zz_8, _zz_7};
end
always @ (posedge io_mainClk) begin
if(io_bus_cmd_payload_mask[0] && io_bus_cmd_valid && io_bus_cmd_payload_wr ) begin
ram_symbol0[_zz_6] <= _zz_3[7 : 0];
end
if(io_bus_cmd_payload_mask[1] && io_bus_cmd_valid && io_bus_cmd_payload_wr ) begin
ram_symbol1[_zz_6] <= _zz_3[15 : 8];
end
if(io_bus_cmd_payload_mask[2] && io_bus_cmd_valid && io_bus_cmd_payload_wr ) begin
ram_symbol2[_zz_6] <= _zz_3[23 : 16];
end
if(io_bus_cmd_payload_mask[3] && io_bus_cmd_valid && io_bus_cmd_payload_wr ) begin
ram_symbol3[_zz_6] <= _zz_3[31 : 24];
end
if(io_bus_cmd_valid) begin
_zz_7 <= ram_symbol0[_zz_6];
_zz_8 <= ram_symbol1[_zz_6];
_zz_9 <= ram_symbol2[_zz_6];
_zz_10 <= ram_symbol3[_zz_6];
end
end
assign io_bus_rsp_valid = _zz_1;
assign _zz_2 = (io_bus_cmd_payload_address >>> 2);
assign _zz_3 = io_bus_cmd_payload_data;
assign io_bus_rsp_payload_data = _zz_4;
assign _zz_5 = 1'b1;
always @ (posedge io_mainClk or posedge resetCtrl_systemReset) begin
if (resetCtrl_systemReset) begin
_zz_1 <= 1'b0;
end else begin
_zz_1 <= ((io_bus_cmd_valid && _zz_5) && (! io_bus_cmd_payload_wr));
end
end
endmodule
module MuraxSimpleBusToApbBridge (
input io_simpleBus_cmd_valid,
output io_simpleBus_cmd_ready,
input io_simpleBus_cmd_payload_wr,
input [31:0] io_simpleBus_cmd_payload_address,
input [31:0] io_simpleBus_cmd_payload_data,
input [3:0] io_simpleBus_cmd_payload_mask,
output io_simpleBus_rsp_valid,
output [31:0] io_simpleBus_rsp_payload_data,
output [19:0] io_apb_PADDR,
output [0:0] io_apb_PSEL,
output io_apb_PENABLE,
input io_apb_PREADY,
output io_apb_PWRITE,
output [31:0] io_apb_PWDATA,
input [31:0] io_apb_PRDATA,
input io_apb_PSLVERROR,
input io_mainClk,
input resetCtrl_systemReset);
wire _zz_10;
wire _zz_11;
wire simpleBusStage_cmd_valid;
reg simpleBusStage_cmd_ready;
wire simpleBusStage_cmd_payload_wr;
wire [31:0] simpleBusStage_cmd_payload_address;
wire [31:0] simpleBusStage_cmd_payload_data;
wire [3:0] simpleBusStage_cmd_payload_mask;
reg simpleBusStage_rsp_valid;
wire [31:0] simpleBusStage_rsp_payload_data;
wire _zz_1;
reg _zz_2;
reg _zz_3;
reg _zz_4;
reg [31:0] _zz_5;
reg [31:0] _zz_6;
reg [3:0] _zz_7;
reg _zz_8;
reg [31:0] _zz_9;
reg state;
assign _zz_10 = (! _zz_2);
assign _zz_11 = (! state);
assign io_simpleBus_cmd_ready = _zz_3;
assign simpleBusStage_cmd_valid = _zz_2;
assign _zz_1 = simpleBusStage_cmd_ready;
assign simpleBusStage_cmd_payload_wr = _zz_4;
assign simpleBusStage_cmd_payload_address = _zz_5;
assign simpleBusStage_cmd_payload_data = _zz_6;
assign simpleBusStage_cmd_payload_mask = _zz_7;
assign io_simpleBus_rsp_valid = _zz_8;
assign io_simpleBus_rsp_payload_data = _zz_9;
always @ (*) begin
simpleBusStage_cmd_ready = 1'b0;
simpleBusStage_rsp_valid = 1'b0;
if(! _zz_11) begin
if(io_apb_PREADY)begin
simpleBusStage_rsp_valid = (! simpleBusStage_cmd_payload_wr);
simpleBusStage_cmd_ready = 1'b1;
end
end
end
assign io_apb_PSEL[0] = simpleBusStage_cmd_valid;
assign io_apb_PENABLE = state;
assign io_apb_PWRITE = simpleBusStage_cmd_payload_wr;
assign io_apb_PADDR = simpleBusStage_cmd_payload_address[19:0];
assign io_apb_PWDATA = simpleBusStage_cmd_payload_data;
assign simpleBusStage_rsp_payload_data = io_apb_PRDATA;
always @ (posedge io_mainClk or posedge resetCtrl_systemReset) begin
if (resetCtrl_systemReset) begin
_zz_2 <= 1'b0;
_zz_3 <= 1'b1;
_zz_8 <= 1'b0;
state <= 1'b0;
end else begin
if(_zz_10)begin
_zz_2 <= io_simpleBus_cmd_valid;
_zz_3 <= (! io_simpleBus_cmd_valid);
end else begin
_zz_2 <= (! _zz_1);
_zz_3 <= _zz_1;
end
_zz_8 <= simpleBusStage_rsp_valid;
if(_zz_11)begin
state <= simpleBusStage_cmd_valid;
end else begin
if(io_apb_PREADY)begin
state <= 1'b0;
end
end
end
end
always @ (posedge io_mainClk) begin
if(_zz_10)begin
_zz_4 <= io_simpleBus_cmd_payload_wr;
_zz_5 <= io_simpleBus_cmd_payload_address;
_zz_6 <= io_simpleBus_cmd_payload_data;
_zz_7 <= io_simpleBus_cmd_payload_mask;
end
_zz_9 <= simpleBusStage_rsp_payload_data;
end
endmodule
module Apb3Gpio (
input [3:0] io_apb_PADDR,
input [0:0] io_apb_PSEL,
input io_apb_PENABLE,
output io_apb_PREADY,
input io_apb_PWRITE,
input [31:0] io_apb_PWDATA,
output reg [31:0] io_apb_PRDATA,
output io_apb_PSLVERROR,
input [31:0] io_gpio_read,
output [31:0] io_gpio_write,
output [31:0] io_gpio_writeEnable,
input io_mainClk,
input resetCtrl_systemReset);
wire _zz_3;
wire ctrl_askWrite;
wire ctrl_askRead;
wire ctrl_doWrite;
wire ctrl_doRead;
reg [31:0] _zz_1;
reg [31:0] _zz_2;
assign io_apb_PREADY = _zz_3;
assign _zz_3 = 1'b1;
always @ (*) begin
io_apb_PRDATA = (32'b00000000000000000000000000000000);
case(io_apb_PADDR)
4'b0000 : begin
io_apb_PRDATA[31 : 0] = io_gpio_read;
end
4'b0100 : begin
io_apb_PRDATA[31 : 0] = _zz_1;
end
4'b1000 : begin
io_apb_PRDATA[31 : 0] = _zz_2;
end
default : begin
end
endcase
end
assign io_apb_PSLVERROR = 1'b0;
assign ctrl_askWrite = ((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PWRITE);
assign ctrl_askRead = ((io_apb_PSEL[0] && io_apb_PENABLE) && (! io_apb_PWRITE));
assign ctrl_doWrite = (((io_apb_PSEL[0] && io_apb_PENABLE) && _zz_3) && io_apb_PWRITE);
assign ctrl_doRead = (((io_apb_PSEL[0] && io_apb_PENABLE) && _zz_3) && (! io_apb_PWRITE));
assign io_gpio_write = _zz_1;
assign io_gpio_writeEnable = _zz_2;
always @ (posedge io_mainClk or posedge resetCtrl_systemReset) begin
if (resetCtrl_systemReset) begin
_zz_2 <= (32'b00000000000000000000000000000000);
end else begin
case(io_apb_PADDR)
4'b0000 : begin
end
4'b0100 : begin
end
4'b1000 : begin
if(ctrl_doWrite)begin
_zz_2 <= io_apb_PWDATA[31 : 0];
end
end
default : begin
end
endcase
end
end
always @ (posedge io_mainClk) begin
case(io_apb_PADDR)
4'b0000 : begin
end
4'b0100 : begin
if(ctrl_doWrite)begin
_zz_1 <= io_apb_PWDATA[31 : 0];
end
end
4'b1000 : begin
end
default : begin
end
endcase
end
endmodule
module Apb3UartCtrl (
input [3:0] io_apb_PADDR,
input [0:0] io_apb_PSEL,
input io_apb_PENABLE,
output io_apb_PREADY,
input io_apb_PWRITE,
input [31:0] io_apb_PWDATA,
output reg [31:0] io_apb_PRDATA,
output io_uart_txd,
input io_uart_rxd,
output io_interrupt,
input io_mainClk,
input resetCtrl_systemReset);
wire _zz_3;
reg _zz_4;
wire _zz_5;
wire _zz_6;
wire _zz_7;
wire _zz_8;
wire [7:0] _zz_9;
wire _zz_10;
wire _zz_11;
wire _zz_12;
wire [7:0] _zz_13;
wire [4:0] _zz_14;
wire [4:0] _zz_15;
wire _zz_16;
wire _zz_17;
wire [7:0] _zz_18;
wire [4:0] _zz_19;
wire [4:0] _zz_20;
wire [0:0] _zz_21;
wire [0:0] _zz_22;
wire [4:0] _zz_23;
wire busCtrl_askWrite;
wire busCtrl_askRead;
wire busCtrl_doWrite;
wire busCtrl_doRead;
wire [2:0] bridge_uartConfigReg_frame_dataLength;
wire `UartStopType_binary_sequancial_type bridge_uartConfigReg_frame_stop;
wire `UartParityType_binary_sequancial_type bridge_uartConfigReg_frame_parity;
reg [19:0] bridge_uartConfigReg_clockDivider;
reg _zz_1;
wire bridge_write_streamUnbuffered_valid;
wire bridge_write_streamUnbuffered_ready;
wire [7:0] bridge_write_streamUnbuffered_payload;
reg bridge_interruptCtrl_writeIntEnable;
reg bridge_interruptCtrl_readIntEnable;
wire bridge_interruptCtrl_readInt;
wire bridge_interruptCtrl_writeInt;
wire bridge_interruptCtrl_interrupt;
wire [7:0] _zz_2;
function [19:0] zz_bridge_uartConfigReg_clockDivider(input dummy);
begin
zz_bridge_uartConfigReg_clockDivider = (20'b00000000000000000000);
zz_bridge_uartConfigReg_clockDivider = (20'b00000000000000010011);
end
endfunction
wire [19:0] _zz_24;
assign io_apb_PREADY = _zz_6;
assign _zz_21 = io_apb_PWDATA[0 : 0];
assign _zz_22 = io_apb_PWDATA[1 : 1];
assign _zz_23 = ((5'b10000) - _zz_14);
UartCtrl uartCtrl_1 (
.io_config_frame_dataLength(bridge_uartConfigReg_frame_dataLength),
.io_config_frame_stop(bridge_uartConfigReg_frame_stop),
.io_config_frame_parity(bridge_uartConfigReg_frame_parity),
.io_config_clockDivider(bridge_uartConfigReg_clockDivider),
.io_write_valid(_zz_12),
.io_write_ready(_zz_7),
.io_write_payload(_zz_13),
.io_read_valid(_zz_8),
.io_read_payload(_zz_9),
.io_uart_txd(_zz_10),
.io_uart_rxd(io_uart_rxd),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
StreamFifo streamFifo_2 (
.io_push_valid(bridge_write_streamUnbuffered_valid),
.io_push_ready(_zz_11),
.io_push_payload(bridge_write_streamUnbuffered_payload),
.io_pop_valid(_zz_12),
.io_pop_ready(_zz_7),
.io_pop_payload(_zz_13),
.io_flush(_zz_3),
.io_occupancy(_zz_14),
.io_availability(_zz_15),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
StreamFifo streamFifo_3 (
.io_push_valid(_zz_8),
.io_push_ready(_zz_16),
.io_push_payload(_zz_9),
.io_pop_valid(_zz_17),
.io_pop_ready(_zz_4),
.io_pop_payload(_zz_18),
.io_flush(_zz_5),
.io_occupancy(_zz_19),
.io_availability(_zz_20),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
assign io_uart_txd = _zz_10;
assign _zz_6 = 1'b1;
always @ (*) begin
io_apb_PRDATA = (32'b00000000000000000000000000000000);
_zz_1 = 1'b0;
_zz_4 = 1'b0;
case(io_apb_PADDR)
4'b0000 : begin
if(busCtrl_doWrite)begin
_zz_1 = 1'b1;
end
if(busCtrl_doRead)begin
_zz_4 = 1'b1;
end
io_apb_PRDATA[16 : 16] = _zz_17;
io_apb_PRDATA[7 : 0] = _zz_18;
end
4'b0100 : begin
io_apb_PRDATA[20 : 16] = _zz_23;
io_apb_PRDATA[28 : 24] = _zz_19;
io_apb_PRDATA[0 : 0] = bridge_interruptCtrl_writeIntEnable;
io_apb_PRDATA[1 : 1] = bridge_interruptCtrl_readIntEnable;
io_apb_PRDATA[8 : 8] = bridge_interruptCtrl_writeInt;
io_apb_PRDATA[9 : 9] = bridge_interruptCtrl_readInt;
end
default : begin
end
endcase
end
assign busCtrl_askWrite = ((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PWRITE);
assign busCtrl_askRead = ((io_apb_PSEL[0] && io_apb_PENABLE) && (! io_apb_PWRITE));
assign busCtrl_doWrite = (((io_apb_PSEL[0] && io_apb_PENABLE) && _zz_6) && io_apb_PWRITE);
assign busCtrl_doRead = (((io_apb_PSEL[0] && io_apb_PENABLE) && _zz_6) && (! io_apb_PWRITE));
assign _zz_24 = zz_bridge_uartConfigReg_clockDivider(1'b0);
always @ (*) bridge_uartConfigReg_clockDivider = _zz_24;
assign bridge_uartConfigReg_frame_dataLength = (3'b111);
assign bridge_uartConfigReg_frame_parity = `UartParityType_binary_sequancial_NONE;
assign bridge_uartConfigReg_frame_stop = `UartStopType_binary_sequancial_ONE;
assign bridge_write_streamUnbuffered_valid = _zz_1;
assign bridge_write_streamUnbuffered_payload = _zz_2;
assign bridge_write_streamUnbuffered_ready = _zz_11;
assign bridge_interruptCtrl_readInt = (bridge_interruptCtrl_readIntEnable && _zz_17);
assign bridge_interruptCtrl_writeInt = (bridge_interruptCtrl_writeIntEnable && (! _zz_12));
assign bridge_interruptCtrl_interrupt = (bridge_interruptCtrl_readInt || bridge_interruptCtrl_writeInt);
assign io_interrupt = bridge_interruptCtrl_interrupt;
assign _zz_2 = io_apb_PWDATA[7 : 0];
assign _zz_3 = 1'b0;
assign _zz_5 = 1'b0;
always @ (posedge io_mainClk or posedge resetCtrl_systemReset) begin
if (resetCtrl_systemReset) begin
bridge_interruptCtrl_writeIntEnable <= 1'b0;
bridge_interruptCtrl_readIntEnable <= 1'b0;
end else begin
case(io_apb_PADDR)
4'b0000 : begin
end
4'b0100 : begin
if(busCtrl_doWrite)begin
bridge_interruptCtrl_writeIntEnable <= _zz_21[0];
bridge_interruptCtrl_readIntEnable <= _zz_22[0];
end
end
default : begin
end
endcase
end
end
endmodule
module MuraxApb3Timer (
input [7:0] io_apb_PADDR,
input [0:0] io_apb_PSEL,
input io_apb_PENABLE,
output io_apb_PREADY,
input io_apb_PWRITE,
input [31:0] io_apb_PWDATA,
output reg [31:0] io_apb_PRDATA,
output io_apb_PSLVERROR,
output io_interrupt,
input io_mainClk,
input resetCtrl_systemReset);
wire _zz_10;
wire _zz_11;
wire _zz_12;
wire _zz_13;
reg [1:0] _zz_14;
reg [1:0] _zz_15;
wire _zz_16;
wire _zz_17;
wire _zz_18;
wire [15:0] _zz_19;
wire _zz_20;
wire [15:0] _zz_21;
wire [1:0] _zz_22;
wire busCtrl_askWrite;
wire busCtrl_askRead;
wire busCtrl_doWrite;
wire busCtrl_doRead;
reg [15:0] _zz_1;
reg _zz_2;
reg [1:0] timerABridge_ticksEnable;
reg [0:0] timerABridge_clearsEnable;
reg timerABridge_busClearing;
reg [15:0] _zz_3;
reg _zz_4;
reg _zz_5;
reg [1:0] timerBBridge_ticksEnable;
reg [0:0] timerBBridge_clearsEnable;
reg timerBBridge_busClearing;
reg [15:0] _zz_6;
reg _zz_7;
reg _zz_8;
reg [1:0] _zz_9;
assign io_apb_PREADY = _zz_16;
Prescaler prescaler_1 (
.io_clear(_zz_2),
.io_limit(_zz_1),
.io_overflow(_zz_17),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
Timer timerA (
.io_tick(_zz_10),
.io_clear(_zz_11),
.io_limit(_zz_3),
.io_full(_zz_18),
.io_value(_zz_19),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
Timer timerB (
.io_tick(_zz_12),
.io_clear(_zz_13),
.io_limit(_zz_6),
.io_full(_zz_20),
.io_value(_zz_21),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
InterruptCtrl interruptCtrl_1 (
.io_inputs(_zz_14),
.io_clears(_zz_15),
.io_masks(_zz_9),
.io_pendings(_zz_22),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
assign _zz_16 = 1'b1;
always @ (*) begin
io_apb_PRDATA = (32'b00000000000000000000000000000000);
_zz_2 = 1'b0;
_zz_4 = 1'b0;
_zz_5 = 1'b0;
_zz_7 = 1'b0;
_zz_8 = 1'b0;
_zz_15 = (2'b00);
case(io_apb_PADDR)
8'b00000000 : begin
if(busCtrl_doWrite)begin
_zz_2 = 1'b1;
end
io_apb_PRDATA[15 : 0] = _zz_1;
end
8'b01000000 : begin
io_apb_PRDATA[1 : 0] = timerABridge_ticksEnable;
io_apb_PRDATA[16 : 16] = timerABridge_clearsEnable;
end
8'b01000100 : begin
if(busCtrl_doWrite)begin
_zz_4 = 1'b1;
end
io_apb_PRDATA[15 : 0] = _zz_3;
end
8'b01001000 : begin
if(busCtrl_doWrite)begin
_zz_5 = 1'b1;
end
io_apb_PRDATA[15 : 0] = _zz_19;
end
8'b01010000 : begin
io_apb_PRDATA[1 : 0] = timerBBridge_ticksEnable;
io_apb_PRDATA[16 : 16] = timerBBridge_clearsEnable;
end
8'b01010100 : begin
if(busCtrl_doWrite)begin
_zz_7 = 1'b1;
end
io_apb_PRDATA[15 : 0] = _zz_6;
end
8'b01011000 : begin
if(busCtrl_doWrite)begin
_zz_8 = 1'b1;
end
io_apb_PRDATA[15 : 0] = _zz_21;
end
8'b00010000 : begin
if(busCtrl_doWrite)begin
_zz_15 = io_apb_PWDATA[1 : 0];
end
io_apb_PRDATA[1 : 0] = _zz_22;
end
8'b00010100 : begin
io_apb_PRDATA[1 : 0] = _zz_9;
end
default : begin
end
endcase
end
assign io_apb_PSLVERROR = 1'b0;
assign busCtrl_askWrite = ((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PWRITE);
assign busCtrl_askRead = ((io_apb_PSEL[0] && io_apb_PENABLE) && (! io_apb_PWRITE));
assign busCtrl_doWrite = (((io_apb_PSEL[0] && io_apb_PENABLE) && _zz_16) && io_apb_PWRITE);
assign busCtrl_doRead = (((io_apb_PSEL[0] && io_apb_PENABLE) && _zz_16) && (! io_apb_PWRITE));
always @ (*) begin
timerABridge_busClearing = 1'b0;
if(_zz_4)begin
timerABridge_busClearing = 1'b1;
end
if(_zz_5)begin
timerABridge_busClearing = 1'b1;
end
end
assign _zz_11 = (((timerABridge_clearsEnable & _zz_18) != (1'b0)) || timerABridge_busClearing);
assign _zz_10 = ((timerABridge_ticksEnable & {_zz_17,1'b1}) != (2'b00));
always @ (*) begin
timerBBridge_busClearing = 1'b0;
if(_zz_7)begin
timerBBridge_busClearing = 1'b1;
end
if(_zz_8)begin
timerBBridge_busClearing = 1'b1;
end
end
assign _zz_13 = (((timerBBridge_clearsEnable & _zz_20) != (1'b0)) || timerBBridge_busClearing);
assign _zz_12 = ((timerBBridge_ticksEnable & {_zz_17,1'b1}) != (2'b00));
always @ (*) begin
_zz_14[0] = _zz_18;
_zz_14[1] = _zz_20;
end
assign io_interrupt = (_zz_22 != (2'b00));
always @ (posedge io_mainClk or posedge resetCtrl_systemReset) begin
if (resetCtrl_systemReset) begin
timerABridge_ticksEnable <= (2'b00);
timerABridge_clearsEnable <= (1'b0);
timerBBridge_ticksEnable <= (2'b00);
timerBBridge_clearsEnable <= (1'b0);
_zz_9 <= (2'b00);
end else begin
case(io_apb_PADDR)
8'b00000000 : begin
end
8'b01000000 : begin
if(busCtrl_doWrite)begin
timerABridge_ticksEnable <= io_apb_PWDATA[1 : 0];
timerABridge_clearsEnable <= io_apb_PWDATA[16 : 16];
end
end
8'b01000100 : begin
end
8'b01001000 : begin
end
8'b01010000 : begin
if(busCtrl_doWrite)begin
timerBBridge_ticksEnable <= io_apb_PWDATA[1 : 0];
timerBBridge_clearsEnable <= io_apb_PWDATA[16 : 16];
end
end
8'b01010100 : begin
end
8'b01011000 : begin
end
8'b00010000 : begin
end
8'b00010100 : begin
if(busCtrl_doWrite)begin
_zz_9 <= io_apb_PWDATA[1 : 0];
end
end
default : begin
end
endcase
end
end
always @ (posedge io_mainClk) begin
case(io_apb_PADDR)
8'b00000000 : begin
if(busCtrl_doWrite)begin
_zz_1 <= io_apb_PWDATA[15 : 0];
end
end
8'b01000000 : begin
end
8'b01000100 : begin
if(busCtrl_doWrite)begin
_zz_3 <= io_apb_PWDATA[15 : 0];
end
end
8'b01001000 : begin
end
8'b01010000 : begin
end
8'b01010100 : begin
if(busCtrl_doWrite)begin
_zz_6 <= io_apb_PWDATA[15 : 0];
end
end
8'b01011000 : begin
end
8'b00010000 : begin
end
8'b00010100 : begin
end
default : begin
end
endcase
end
endmodule
module Apb3Decoder (
input [19:0] io_input_PADDR,
input [0:0] io_input_PSEL,
input io_input_PENABLE,
output io_input_PREADY,
input io_input_PWRITE,
input [31:0] io_input_PWDATA,
output [31:0] io_input_PRDATA,
output io_input_PSLVERROR,
output [19:0] io_output_PADDR,
output reg [2:0] io_output_PSEL,
output io_output_PENABLE,
input io_output_PREADY,
output io_output_PWRITE,
output [31:0] io_output_PWDATA,
input [31:0] io_output_PRDATA,
input io_output_PSLVERROR);
wire [19:0] _zz_1;
wire [19:0] _zz_2;
wire [19:0] _zz_3;
assign _zz_1 = (20'b11111111000000000000);
assign _zz_2 = (20'b11111111000000000000);
assign _zz_3 = (20'b11111111000000000000);
assign io_output_PADDR = io_input_PADDR;
assign io_output_PENABLE = io_input_PENABLE;
assign io_output_PWRITE = io_input_PWRITE;
assign io_output_PWDATA = io_input_PWDATA;
always @ (*) begin
io_output_PSEL[0] = (((io_input_PADDR & _zz_1) == (20'b00000000000000000000)) && io_input_PSEL[0]);
io_output_PSEL[1] = (((io_input_PADDR & _zz_2) == (20'b00010000000000000000)) && io_input_PSEL[0]);
io_output_PSEL[2] = (((io_input_PADDR & _zz_3) == (20'b00100000000000000000)) && io_input_PSEL[0]);
end
assign io_input_PREADY = io_output_PREADY;
assign io_input_PRDATA = io_output_PRDATA;
assign io_input_PSLVERROR = io_output_PSLVERROR;
endmodule
module Apb3Router (
input [19:0] io_input_PADDR,
input [2:0] io_input_PSEL,
input io_input_PENABLE,
output io_input_PREADY,
input io_input_PWRITE,
input [31:0] io_input_PWDATA,
output [31:0] io_input_PRDATA,
output io_input_PSLVERROR,
output [19:0] io_outputs_0_PADDR,
output [0:0] io_outputs_0_PSEL,
output io_outputs_0_PENABLE,
input io_outputs_0_PREADY,
output io_outputs_0_PWRITE,
output [31:0] io_outputs_0_PWDATA,
input [31:0] io_outputs_0_PRDATA,
input io_outputs_0_PSLVERROR,
output [19:0] io_outputs_1_PADDR,
output [0:0] io_outputs_1_PSEL,
output io_outputs_1_PENABLE,
input io_outputs_1_PREADY,
output io_outputs_1_PWRITE,
output [31:0] io_outputs_1_PWDATA,
input [31:0] io_outputs_1_PRDATA,
input io_outputs_1_PSLVERROR,
output [19:0] io_outputs_2_PADDR,
output [0:0] io_outputs_2_PSEL,
output io_outputs_2_PENABLE,
input io_outputs_2_PREADY,
output io_outputs_2_PWRITE,
output [31:0] io_outputs_2_PWDATA,
input [31:0] io_outputs_2_PRDATA,
input io_outputs_2_PSLVERROR,
input io_mainClk,
input resetCtrl_systemReset);
reg _zz_3;
reg [31:0] _zz_4;
reg _zz_5;
wire _zz_1;
wire _zz_2;
reg [1:0] selIndex;
always @(*) begin
case(selIndex)
2'b00 : begin
_zz_3 = io_outputs_0_PREADY;
_zz_4 = io_outputs_0_PRDATA;
_zz_5 = io_outputs_0_PSLVERROR;
end
2'b01 : begin
_zz_3 = io_outputs_1_PREADY;
_zz_4 = io_outputs_1_PRDATA;
_zz_5 = io_outputs_1_PSLVERROR;
end
default : begin
_zz_3 = io_outputs_2_PREADY;
_zz_4 = io_outputs_2_PRDATA;
_zz_5 = io_outputs_2_PSLVERROR;
end
endcase
end
assign io_outputs_0_PADDR = io_input_PADDR;
assign io_outputs_0_PENABLE = io_input_PENABLE;
assign io_outputs_0_PSEL[0] = io_input_PSEL[0];
assign io_outputs_0_PWRITE = io_input_PWRITE;
assign io_outputs_0_PWDATA = io_input_PWDATA;
assign io_outputs_1_PADDR = io_input_PADDR;
assign io_outputs_1_PENABLE = io_input_PENABLE;
assign io_outputs_1_PSEL[0] = io_input_PSEL[1];
assign io_outputs_1_PWRITE = io_input_PWRITE;
assign io_outputs_1_PWDATA = io_input_PWDATA;
assign io_outputs_2_PADDR = io_input_PADDR;
assign io_outputs_2_PENABLE = io_input_PENABLE;
assign io_outputs_2_PSEL[0] = io_input_PSEL[2];
assign io_outputs_2_PWRITE = io_input_PWRITE;
assign io_outputs_2_PWDATA = io_input_PWDATA;
assign _zz_1 = io_input_PSEL[1];
assign _zz_2 = io_input_PSEL[2];
assign io_input_PREADY = _zz_3;
assign io_input_PRDATA = _zz_4;
assign io_input_PSLVERROR = _zz_5;
always @ (posedge io_mainClk) begin
selIndex <= {_zz_2,_zz_1};
end
endmodule
module Murax (
input io_asyncReset,
input io_mainClk,
input io_jtag_tms,
input io_jtag_tdi,
output io_jtag_tdo,
input io_jtag_tck,
input [31:0] io_gpioA_read,
output [31:0] io_gpioA_write,
output [31:0] io_gpioA_writeEnable,
output io_uart_txd,
input io_uart_rxd);
wire [7:0] _zz_11;
reg _zz_12;
reg _zz_13;
wire [3:0] _zz_14;
wire [3:0] _zz_15;
wire [7:0] _zz_16;
wire _zz_17;
reg [31:0] _zz_18;
wire _zz_19;
wire _zz_20;
wire _zz_21;
wire _zz_22;
wire [31:0] _zz_23;
wire _zz_24;
wire _zz_25;
wire _zz_26;
wire [31:0] _zz_27;
wire _zz_28;
wire _zz_29;
wire [31:0] _zz_30;
wire [31:0] _zz_31;
wire [3:0] _zz_32;
wire _zz_33;
wire [31:0] _zz_34;
wire _zz_35;
wire _zz_36;
wire [31:0] _zz_37;
wire _zz_38;
wire _zz_39;
wire [31:0] _zz_40;
wire [31:0] _zz_41;
wire [1:0] _zz_42;
wire _zz_43;
wire _zz_44;
wire _zz_45;
wire [0:0] _zz_46;
wire _zz_47;
wire _zz_48;
wire _zz_49;
wire _zz_50;
wire [31:0] _zz_51;
wire _zz_52;
wire [31:0] _zz_53;
wire [31:0] _zz_54;
wire _zz_55;
wire [1:0] _zz_56;
wire _zz_57;
wire _zz_58;
wire [31:0] _zz_59;
wire _zz_60;
wire _zz_61;
wire [31:0] _zz_62;
wire [19:0] _zz_63;
wire [0:0] _zz_64;
wire _zz_65;
wire _zz_66;
wire [31:0] _zz_67;
wire _zz_68;
wire [31:0] _zz_69;
wire _zz_70;
wire [31:0] _zz_71;
wire [31:0] _zz_72;
wire _zz_73;
wire [31:0] _zz_74;
wire _zz_75;
wire _zz_76;
wire _zz_77;
wire [31:0] _zz_78;
wire _zz_79;
wire _zz_80;
wire _zz_81;
wire [31:0] _zz_82;
wire _zz_83;
wire [19:0] _zz_84;
wire [2:0] _zz_85;
wire _zz_86;
wire _zz_87;
wire [31:0] _zz_88;
wire _zz_89;
wire [31:0] _zz_90;
wire _zz_91;
wire [19:0] _zz_92;
wire [0:0] _zz_93;
wire _zz_94;
wire _zz_95;
wire [31:0] _zz_96;
wire [19:0] _zz_97;
wire [0:0] _zz_98;
wire _zz_99;
wire _zz_100;
wire [31:0] _zz_101;
wire [19:0] _zz_102;
wire [0:0] _zz_103;
wire _zz_104;
wire _zz_105;
wire [31:0] _zz_106;
wire _zz_107;
wire _zz_108;
wire [31:0] _zz_109;
wire [31:0] _zz_110;
reg resetCtrl_mainClkResetUnbuffered;
reg [5:0] resetCtrl_systemClkResetCounter = (6'b000000);
wire [5:0] _zz_1;
reg resetCtrl_mainClkReset;
reg resetCtrl_systemReset;
reg system_timerInterrupt;
reg system_externalInterrupt;
wire _zz_2;
reg _zz_3;
reg _zz_4;
reg _zz_5;
reg [31:0] _zz_6;
reg [31:0] _zz_7;
reg [1:0] _zz_8;
reg _zz_9;
reg _zz_10;
wire system_mainBusDecoder_logic_masterPipelined_cmd_valid;
reg system_mainBusDecoder_logic_masterPipelined_cmd_ready;
wire system_mainBusDecoder_logic_masterPipelined_cmd_payload_wr;
wire [31:0] system_mainBusDecoder_logic_masterPipelined_cmd_payload_address;
wire [31:0] system_mainBusDecoder_logic_masterPipelined_cmd_payload_data;
wire [3:0] system_mainBusDecoder_logic_masterPipelined_cmd_payload_mask;
wire system_mainBusDecoder_logic_masterPipelined_rsp_valid;
wire [31:0] system_mainBusDecoder_logic_masterPipelined_rsp_payload_data;
wire system_mainBusDecoder_logic_hits_0;
wire system_mainBusDecoder_logic_hits_1;
wire system_mainBusDecoder_logic_noHit;
reg system_mainBusDecoder_logic_rspPending;
reg system_mainBusDecoder_logic_rspNoHit;
reg [0:0] system_mainBusDecoder_logic_rspSourceId;
assign _zz_107 = (! _zz_3);
assign _zz_108 = (resetCtrl_systemClkResetCounter != _zz_1);
assign _zz_109 = (32'b11111111111111111111000000000000);
assign _zz_110 = (32'b11111111111100000000000000000000);
BufferCC_2 bufferCC_3 (
.io_dataIn(io_asyncReset),
.io_dataOut(_zz_19),
.io_mainClk(io_mainClk)
);
MuraxMasterArbiter system_mainBusArbiter (
.io_iBus_cmd_valid(_zz_36),
.io_iBus_cmd_ready(_zz_20),
.io_iBus_cmd_payload_pc(_zz_37),
.io_iBus_rsp_ready(_zz_21),
.io_iBus_rsp_error(_zz_22),
.io_iBus_rsp_inst(_zz_23),
.io_dBus_cmd_valid(_zz_3),
.io_dBus_cmd_ready(_zz_24),
.io_dBus_cmd_payload_wr(_zz_5),
.io_dBus_cmd_payload_address(_zz_6),
.io_dBus_cmd_payload_data(_zz_7),
.io_dBus_cmd_payload_size(_zz_8),
.io_dBus_rsp_ready(_zz_25),
.io_dBus_rsp_error(_zz_26),
.io_dBus_rsp_data(_zz_27),
.io_masterBus_cmd_valid(_zz_28),
.io_masterBus_cmd_ready(system_mainBusDecoder_logic_masterPipelined_cmd_ready),
.io_masterBus_cmd_payload_wr(_zz_29),
.io_masterBus_cmd_payload_address(_zz_30),
.io_masterBus_cmd_payload_data(_zz_31),
.io_masterBus_cmd_payload_mask(_zz_32),
.io_masterBus_rsp_valid(system_mainBusDecoder_logic_masterPipelined_rsp_valid),
.io_masterBus_rsp_payload_data(system_mainBusDecoder_logic_masterPipelined_rsp_payload_data),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
VexRiscv system_cpu (
.timerInterrupt(system_timerInterrupt),
.externalInterrupt(system_externalInterrupt),
.debug_bus_cmd_valid(_zz_52),
.debug_bus_cmd_ready(_zz_33),
.debug_bus_cmd_payload_wr(_zz_55),
.debug_bus_cmd_payload_address(_zz_11),
.debug_bus_cmd_payload_data(_zz_54),
.debug_bus_rsp_data(_zz_34),
.debug_resetOut(_zz_35),
.iBus_cmd_valid(_zz_36),
.iBus_cmd_ready(_zz_20),
.iBus_cmd_payload_pc(_zz_37),
.iBus_rsp_ready(_zz_21),
.iBus_rsp_error(_zz_22),
.iBus_rsp_inst(_zz_23),
.dBus_cmd_valid(_zz_38),
.dBus_cmd_ready(_zz_4),
.dBus_cmd_payload_wr(_zz_39),
.dBus_cmd_payload_address(_zz_40),
.dBus_cmd_payload_data(_zz_41),
.dBus_cmd_payload_size(_zz_42),
.dBus_rsp_ready(_zz_25),
.dBus_rsp_error(_zz_26),
.dBus_rsp_data(_zz_27),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset),
.resetCtrl_mainClkReset(resetCtrl_mainClkReset)
);
JtagBridge jtagBridge_1 (
.io_jtag_tms(io_jtag_tms),
.io_jtag_tdi(io_jtag_tdi),
.io_jtag_tdo(_zz_43),
.io_jtag_tck(io_jtag_tck),
.io_remote_cmd_valid(_zz_44),
.io_remote_cmd_ready(_zz_48),
.io_remote_cmd_payload_last(_zz_45),
.io_remote_cmd_payload_fragment(_zz_46),
.io_remote_rsp_valid(_zz_49),
.io_remote_rsp_ready(_zz_47),
.io_remote_rsp_payload_error(_zz_50),
.io_remote_rsp_payload_data(_zz_51),
.io_mainClk(io_mainClk),
.resetCtrl_mainClkReset(resetCtrl_mainClkReset)
);
SystemDebugger systemDebugger_1 (
.io_remote_cmd_valid(_zz_44),
.io_remote_cmd_ready(_zz_48),
.io_remote_cmd_payload_last(_zz_45),
.io_remote_cmd_payload_fragment(_zz_46),
.io_remote_rsp_valid(_zz_49),
.io_remote_rsp_ready(_zz_47),
.io_remote_rsp_payload_error(_zz_50),
.io_remote_rsp_payload_data(_zz_51),
.io_mem_cmd_valid(_zz_52),
.io_mem_cmd_ready(_zz_33),
.io_mem_cmd_payload_address(_zz_53),
.io_mem_cmd_payload_data(_zz_54),
.io_mem_cmd_payload_wr(_zz_55),
.io_mem_cmd_payload_size(_zz_56),
.io_mem_rsp_valid(_zz_10),
.io_mem_rsp_payload(_zz_34),
.io_mainClk(io_mainClk),
.resetCtrl_mainClkReset(resetCtrl_mainClkReset)
);
MuraxSimpleBusRam system_ram (
.io_bus_cmd_valid(_zz_12),
.io_bus_cmd_ready(_zz_57),
.io_bus_cmd_payload_wr(system_mainBusDecoder_logic_masterPipelined_cmd_payload_wr),
.io_bus_cmd_payload_address(system_mainBusDecoder_logic_masterPipelined_cmd_payload_address),
.io_bus_cmd_payload_data(system_mainBusDecoder_logic_masterPipelined_cmd_payload_data),
.io_bus_cmd_payload_mask(system_mainBusDecoder_logic_masterPipelined_cmd_payload_mask),
.io_bus_rsp_valid(_zz_58),
.io_bus_rsp_payload_data(_zz_59),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
MuraxSimpleBusToApbBridge system_apbBridge (
.io_simpleBus_cmd_valid(_zz_13),
.io_simpleBus_cmd_ready(_zz_60),
.io_simpleBus_cmd_payload_wr(system_mainBusDecoder_logic_masterPipelined_cmd_payload_wr),
.io_simpleBus_cmd_payload_address(system_mainBusDecoder_logic_masterPipelined_cmd_payload_address),
.io_simpleBus_cmd_payload_data(system_mainBusDecoder_logic_masterPipelined_cmd_payload_data),
.io_simpleBus_cmd_payload_mask(system_mainBusDecoder_logic_masterPipelined_cmd_payload_mask),
.io_simpleBus_rsp_valid(_zz_61),
.io_simpleBus_rsp_payload_data(_zz_62),
.io_apb_PADDR(_zz_63),
.io_apb_PSEL(_zz_64),
.io_apb_PENABLE(_zz_65),
.io_apb_PREADY(_zz_81),
.io_apb_PWRITE(_zz_66),
.io_apb_PWDATA(_zz_67),
.io_apb_PRDATA(_zz_82),
.io_apb_PSLVERROR(_zz_83),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
Apb3Gpio system_gpioACtrl (
.io_apb_PADDR(_zz_14),
.io_apb_PSEL(_zz_93),
.io_apb_PENABLE(_zz_94),
.io_apb_PREADY(_zz_68),
.io_apb_PWRITE(_zz_95),
.io_apb_PWDATA(_zz_96),
.io_apb_PRDATA(_zz_69),
.io_apb_PSLVERROR(_zz_70),
.io_gpio_read(io_gpioA_read),
.io_gpio_write(_zz_71),
.io_gpio_writeEnable(_zz_72),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
Apb3UartCtrl system_uartCtrl (
.io_apb_PADDR(_zz_15),
.io_apb_PSEL(_zz_98),
.io_apb_PENABLE(_zz_99),
.io_apb_PREADY(_zz_73),
.io_apb_PWRITE(_zz_100),
.io_apb_PWDATA(_zz_101),
.io_apb_PRDATA(_zz_74),
.io_uart_txd(_zz_75),
.io_uart_rxd(io_uart_rxd),
.io_interrupt(_zz_76),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
MuraxApb3Timer system_timer (
.io_apb_PADDR(_zz_16),
.io_apb_PSEL(_zz_103),
.io_apb_PENABLE(_zz_104),
.io_apb_PREADY(_zz_77),
.io_apb_PWRITE(_zz_105),
.io_apb_PWDATA(_zz_106),
.io_apb_PRDATA(_zz_78),
.io_apb_PSLVERROR(_zz_79),
.io_interrupt(_zz_80),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
Apb3Decoder io_apb_decoder (
.io_input_PADDR(_zz_63),
.io_input_PSEL(_zz_64),
.io_input_PENABLE(_zz_65),
.io_input_PREADY(_zz_81),
.io_input_PWRITE(_zz_66),
.io_input_PWDATA(_zz_67),
.io_input_PRDATA(_zz_82),
.io_input_PSLVERROR(_zz_83),
.io_output_PADDR(_zz_84),
.io_output_PSEL(_zz_85),
.io_output_PENABLE(_zz_86),
.io_output_PREADY(_zz_89),
.io_output_PWRITE(_zz_87),
.io_output_PWDATA(_zz_88),
.io_output_PRDATA(_zz_90),
.io_output_PSLVERROR(_zz_91)
);
Apb3Router apb3Router_1 (
.io_input_PADDR(_zz_84),
.io_input_PSEL(_zz_85),
.io_input_PENABLE(_zz_86),
.io_input_PREADY(_zz_89),
.io_input_PWRITE(_zz_87),
.io_input_PWDATA(_zz_88),
.io_input_PRDATA(_zz_90),
.io_input_PSLVERROR(_zz_91),
.io_outputs_0_PADDR(_zz_92),
.io_outputs_0_PSEL(_zz_93),
.io_outputs_0_PENABLE(_zz_94),
.io_outputs_0_PREADY(_zz_68),
.io_outputs_0_PWRITE(_zz_95),
.io_outputs_0_PWDATA(_zz_96),
.io_outputs_0_PRDATA(_zz_69),
.io_outputs_0_PSLVERROR(_zz_70),
.io_outputs_1_PADDR(_zz_97),
.io_outputs_1_PSEL(_zz_98),
.io_outputs_1_PENABLE(_zz_99),
.io_outputs_1_PREADY(_zz_73),
.io_outputs_1_PWRITE(_zz_100),
.io_outputs_1_PWDATA(_zz_101),
.io_outputs_1_PRDATA(_zz_74),
.io_outputs_1_PSLVERROR(_zz_17),
.io_outputs_2_PADDR(_zz_102),
.io_outputs_2_PSEL(_zz_103),
.io_outputs_2_PENABLE(_zz_104),
.io_outputs_2_PREADY(_zz_77),
.io_outputs_2_PWRITE(_zz_105),
.io_outputs_2_PWDATA(_zz_106),
.io_outputs_2_PRDATA(_zz_78),
.io_outputs_2_PSLVERROR(_zz_79),
.io_mainClk(io_mainClk),
.resetCtrl_systemReset(resetCtrl_systemReset)
);
always @(*) begin
case(system_mainBusDecoder_logic_rspSourceId)
1'b0 : begin
_zz_18 = _zz_59;
end
default : begin
_zz_18 = _zz_62;
end
endcase
end
always @ (*) begin
resetCtrl_mainClkResetUnbuffered = 1'b0;
if(_zz_108)begin
resetCtrl_mainClkResetUnbuffered = 1'b1;
end
end
assign _zz_1[5 : 0] = (6'b111111);
always @ (*) begin
system_timerInterrupt = 1'b0;
if(_zz_80)begin
system_timerInterrupt = 1'b1;
end
end
always @ (*) begin
system_externalInterrupt = 1'b0;
if(_zz_76)begin
system_externalInterrupt = 1'b1;
end
end
assign _zz_2 = _zz_24;
assign _zz_11 = _zz_53[7:0];
assign io_jtag_tdo = _zz_43;
assign io_gpioA_write = _zz_71;
assign io_gpioA_writeEnable = _zz_72;
assign io_uart_txd = _zz_75;
assign _zz_14 = _zz_92[3:0];
assign _zz_15 = _zz_97[3:0];
assign _zz_17 = 1'b0;
assign _zz_16 = _zz_102[7:0];
assign system_mainBusDecoder_logic_masterPipelined_cmd_valid = _zz_28;
assign system_mainBusDecoder_logic_masterPipelined_cmd_payload_wr = _zz_29;
assign system_mainBusDecoder_logic_masterPipelined_cmd_payload_address = _zz_30;
assign system_mainBusDecoder_logic_masterPipelined_cmd_payload_data = _zz_31;
assign system_mainBusDecoder_logic_masterPipelined_cmd_payload_mask = _zz_32;
assign system_mainBusDecoder_logic_hits_0 = ((system_mainBusDecoder_logic_masterPipelined_cmd_payload_address & _zz_109) == (32'b10000000000000000000000000000000));
always @ (*) begin
_zz_12 = (system_mainBusDecoder_logic_masterPipelined_cmd_valid && system_mainBusDecoder_logic_hits_0);
_zz_13 = (system_mainBusDecoder_logic_masterPipelined_cmd_valid && system_mainBusDecoder_logic_hits_1);
system_mainBusDecoder_logic_masterPipelined_cmd_ready = (((system_mainBusDecoder_logic_hits_0 && _zz_57) || (system_mainBusDecoder_logic_hits_1 && _zz_60)) || system_mainBusDecoder_logic_noHit);
if((system_mainBusDecoder_logic_rspPending && (! system_mainBusDecoder_logic_masterPipelined_rsp_valid)))begin
system_mainBusDecoder_logic_masterPipelined_cmd_ready = 1'b0;
_zz_12 = 1'b0;
_zz_13 = 1'b0;
end
end
assign system_mainBusDecoder_logic_hits_1 = ((system_mainBusDecoder_logic_masterPipelined_cmd_payload_address & _zz_110) == (32'b11110000000000000000000000000000));
assign system_mainBusDecoder_logic_noHit = (! (system_mainBusDecoder_logic_hits_0 || system_mainBusDecoder_logic_hits_1));
assign system_mainBusDecoder_logic_masterPipelined_rsp_valid = ((_zz_58 || _zz_61) || (system_mainBusDecoder_logic_rspPending && system_mainBusDecoder_logic_rspNoHit));
assign system_mainBusDecoder_logic_masterPipelined_rsp_payload_data = _zz_18;
always @ (posedge io_mainClk) begin
if(_zz_108)begin
resetCtrl_systemClkResetCounter <= (resetCtrl_systemClkResetCounter + (6'b000001));
end
if(_zz_19)begin
resetCtrl_systemClkResetCounter <= (6'b000000);
end
end
always @ (posedge io_mainClk) begin
resetCtrl_mainClkReset <= resetCtrl_mainClkResetUnbuffered;
resetCtrl_systemReset <= resetCtrl_mainClkResetUnbuffered;
if(_zz_9)begin
resetCtrl_systemReset <= 1'b1;
end
end
always @ (posedge io_mainClk or posedge resetCtrl_systemReset) begin
if (resetCtrl_systemReset) begin
_zz_3 <= 1'b0;
_zz_4 <= 1'b1;
system_mainBusDecoder_logic_rspPending <= 1'b0;
system_mainBusDecoder_logic_rspNoHit <= 1'b0;
end else begin
if(_zz_107)begin
_zz_3 <= _zz_38;
_zz_4 <= (! _zz_38);
end else begin
_zz_3 <= (! _zz_2);
_zz_4 <= _zz_2;
end
if(system_mainBusDecoder_logic_masterPipelined_rsp_valid)begin
system_mainBusDecoder_logic_rspPending <= 1'b0;
end
if(((system_mainBusDecoder_logic_masterPipelined_cmd_valid && system_mainBusDecoder_logic_masterPipelined_cmd_ready) && (! system_mainBusDecoder_logic_masterPipelined_cmd_payload_wr)))begin
system_mainBusDecoder_logic_rspPending <= 1'b1;
end
system_mainBusDecoder_logic_rspNoHit <= 1'b0;
if(system_mainBusDecoder_logic_noHit)begin
system_mainBusDecoder_logic_rspNoHit <= 1'b1;
end
end
end
always @ (posedge io_mainClk) begin
if(_zz_107)begin
_zz_5 <= _zz_39;
_zz_6 <= _zz_40;
_zz_7 <= _zz_41;
_zz_8 <= _zz_42;
end
if((system_mainBusDecoder_logic_masterPipelined_cmd_valid && system_mainBusDecoder_logic_masterPipelined_cmd_ready))begin
system_mainBusDecoder_logic_rspSourceId <= system_mainBusDecoder_logic_hits_1;
end
end
always @ (posedge io_mainClk) begin
_zz_9 <= _zz_35;
end
always @ (posedge io_mainClk or posedge resetCtrl_mainClkReset) begin
if (resetCtrl_mainClkReset) begin
_zz_10 <= 1'b0;
end else begin
_zz_10 <= (_zz_52 && _zz_33);
end
end
endmodule
|
module AluTest;
reg [7:0] a = 0;
reg [7:0] b = 0;
reg [3:0] control = 0;
wire [7:0] out;
wire overflow;
reg clk;
reg reset;
ArithmeticLogicUnit alu(a, b, control, clk, reset, out, overflow);
`include "Framework.v"
always #10 clk = ~clk;
initial begin
clk = 0;
reset = 1;
#20 reset = 0;
a = 5;
b = 7;
control = 0;
#10 display_test(12, out);
// Substraction
a = 5;
b = 7;
control = 1;
#10 display_test(-2, $signed(out));
// Shifting test
a = 5;
b = 1;
control = 2;
#10 display_test(10, out);
// Bitwise OR test
a = 'b01010101;
b = 'b10101010;
control = 3;
#10 display_test('b11111111, out);
// Bitwise AND test
a = 'b01010101;
b = 'b10101010;
control = 4;
#10 display_test(0, out);
// Bitwise XOR test
a = 'b01010101;
b = 'b10101011;
control = 5;
#10 display_test('b11111110, out);
// Bitwise ROR test
a = 'b01010101;
b = 1;
control = 6;
#10 display_test('b10101010, out);
// EQUALS test
a = 'b01010101;
b = 'b01010101;
control = 7;
#10 display_test(1, overflow);
// IS_GREATER test
a = 5;
b = 1;
control = 8;
#10 display_test(1, overflow);
// IS_SMALLER test
a = 5;
b = 1;
control = 9;
#10 display_test(0, overflow);
$finish;
end
endmodule
|
module microfono
(
input reset,
output ledres,
input clk,
output mclk,
output reg micLRSel,
input micData,
output ampPWM,
output ampSD,
input rd,wr,
output empty,
output full,
output reg done
//output [7:0] dout,
);
wire [320:0] dout;
wire [320:0] dout1;
wire mclk1;
wire mclk2;
assign mclk3=mclk2;
assign mclk2=mclk1;
assign mclk=mclk1;
reg [320:0] sregt1;
reg [320:0] sregt;
fifo fi(.reset(reset),.din(sregt1),.dout(dout),.clock(done),.rd(rd),.wr(wr),.empty(empty),.full(full));
pwm pw(.ampSD(ampSD), .reset(reset),.mclk(mclk2),.ampPWM(ampPWM),.clk(clk),.dout(dout1));
div_freq df(.clk(clk), .reset(reset),.clkout(mclk1),.led(ledres));
reg [320:0] count;
assign dout1=dout;
initial micLRSel <= 0;
initial count <= 0;
initial sregt <= 0;
initial sregt1 <= 0;
always @(posedge mclk)
begin
if (reset)
begin
sregt<=0;
end
else
begin
if(count<=320)
begin
sregt<= {sregt[320:0],micData};
count<=count+1;
done<=0;
end
else
begin
count<=0;
done<=1;
sregt1<=sregt;
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EINVN_BEHAVIORAL_V
`define SKY130_FD_SC_MS__EINVN_BEHAVIORAL_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__einvn (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
notif0 notif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__EINVN_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFXTP_1_V
`define SKY130_FD_SC_MS__SDFXTP_1_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog wrapper for sdfxtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__sdfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdfxtp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdfxtp_1 (
Q ,
CLK,
D ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFXTP_1_V
|
/*
** -----------------------------------------------------------------------------**
** macros353.v
**
** I/O pads related circuitry
**
** Copyright (C) 2002 Elphel, Inc
**
** -----------------------------------------------------------------------------**
** This file is part of X353
** X353 is free software - hardware description language (HDL) code.
**
** This program is free software: you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation, either version 3 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program. If not, see <http://www.gnu.org/licenses/>.
** -----------------------------------------------------------------------------**
**
*/
// just make more convenient A[3:0] instead of 4 one-bit inputs
// TODO: Replace direct instances of SRL16 to imporve portability
module MSRL16 (Q, A, CLK, D);
output Q;
input [3:0] A;
input CLK, D;
`ifdef SIMULATION
SRL16_MOD #(.INVERT(1'b0)) i_q (.Q(Q), .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .CLK(CLK), .D(D));
`else
SRL16 i_q (.Q(Q), .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .CLK(CLK), .D(D));
`endif
endmodule
module MSRL16_1 (Q, A, CLK, D);
output Q;
input [3:0] A;
input CLK, D;
`ifdef SIMULATION
SRL16_MOD #(.INVERT(1'b1)) i_q (.Q(Q), .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .CLK(CLK), .D(D));
`else
SRL16_1 i_q (.Q(Q), .A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .CLK(CLK), .D(D));
`endif
endmodule
module myRAM_WxD_D(D,WE,clk,AW,AR,QW,QR);
parameter DATA_WIDTH=16;
parameter DATA_DEPTH=4;
parameter DATA_2DEPTH=(1<<DATA_DEPTH)-1;
input [DATA_WIDTH-1:0] D;
input WE,clk;
input [DATA_DEPTH-1:0] AW;
input [DATA_DEPTH-1:0] AR;
output [DATA_WIDTH-1:0] QW;
output [DATA_WIDTH-1:0] QR;
reg [DATA_WIDTH-1:0] ram [0:DATA_2DEPTH];
always @ (posedge clk) if (WE) ram[AW] <= D;
assign QW= ram[AW];
assign QR= ram[AR];
endmodule
module myRAM_WxD_D_1(D,WE,clk,AW,AR,QW,QR);
parameter DATA_WIDTH=16;
parameter DATA_DEPTH=4;
parameter DATA_2DEPTH=(1<<DATA_DEPTH)-1;
input [DATA_WIDTH-1:0] D;
input WE,clk;
input [DATA_DEPTH-1:0] AW;
input [DATA_DEPTH-1:0] AR;
output [DATA_WIDTH-1:0] QW;
output [DATA_WIDTH-1:0] QR;
reg [DATA_WIDTH-1:0] ram [0:DATA_2DEPTH];
always @ (negedge clk) if (WE) ram[AW] <= D;
assign QW= ram[AW];
assign QR= ram[AR];
endmodule
// Modifying Xilinx SLR16_x to better simulate real hardware
module SRL16_MOD #(
parameter INIT = 16'h0000,
parameter INVERT = 0 // *_1 - invert
) (
output Q,
input A0,
input A1,
input A2,
input A3,
input CLK,
input D);
reg [15:0] data;
wire clk_;
wire [3:0] a = {A3, A2, A1, A0};
assign Q = (|data) ? ((&data) ? 1'b1 : data[a]) : 1'b0 ;
// assign Q = (data == 16'h0) ? 1'b0 :
// ((data == 16'hffff) ? 1'b1 : data[a]);
assign clk_ = INVERT? (~CLK) : CLK;
initial
begin
assign data = INIT;
while (clk_ === 1'b1 || clk_ === 1'bX)
#10;
deassign data;
end
always @(posedge clk_)
begin
{data[15:0]} <= #100 {data[14:0], D};
end
endmodule
|
// UC Berkeley CS251
// Spring 2018
// Arya Reais-Parsi ([email protected])
`include "Opcode.vh"
`include "const.vh"
module datapath(
input clk, reset,
//input [0:0] hazard_controls,
input stall,
// Stage 1 controls and output to controller.
input wire [1:0] s1_pc_sel,
input wire s3_csr_we,
input wire s1_fwd_s3_rs1,
input wire s1_fwd_s3_rs2,
output wire [4:0] s1_rs1,
output wire [4:0] s1_rs2,
output wire [4:0] s1_rd,
output wire [6:0] s1_opcode,
output wire [2:0] s1_func,
// Stage 2 controls and output to controller.
input wire [1:0] s2_alu_a_sel,
input wire [2:0] s2_alu_b_sel,
input wire [1:0] s2_adder_a_sel,
input wire s2_adder_b_sel,
input wire s2_pc_out_sel,
input wire [1:0] s2_dmem_we,
input wire s2_dmem_re,
input wire s2_fwd_s3_rs1,
input wire s2_fwd_s3_rs2,
output wire [4:0] s2_rs1,
output wire [4:0] s2_rs2,
output wire [4:0] s2_rd,
output wire [6:0] s2_opcode,
output wire [2:0] s2_func,
// Stage 3 controls and output to controller.
input wire [2:0] s3_rdata_sel,
input wire [1:0] s3_reg_wdata_sel,
input wire s3_reg_we,
input wire s3_csr_new_data_sel,
output wire [4:0] s3_rs1,
output wire [4:0] s3_rs2,
output wire [4:0] s3_rd,
output wire [6:0] s3_opcode,
output wire [2:0] s3_func,
output wire s3_branch,
// Memory system connections
output [31:0] dcache_addr,
output [31:0] icache_addr,
output reg [3:0] dcache_we,
output dcache_re,
output reg [31:0] dcache_din,
input [31:0] dcache_dout,
input [31:0] icache_dout,
output wire [31:0] csr_tohost
);
//-------------------------------------------------------------------
// Control status registers (CSR)
//-------------------------------------------------------------------
reg [`CPU_DATA_BITS-1:0] csr_tohost_reg;
assign csr_tohost = csr_tohost_reg;
//-------------------------------------------------------------------
// Stage 1
//-------------------------------------------------------------------
wire [4:0] rf_raddr0;
wire [4:0] rf_raddr1;
wire [4:0] rf_waddr;
wire [`CPU_DATA_BITS-1:0] rf_rdata0;
wire [`CPU_DATA_BITS-1:0] rf_rdata1;
reg [`CPU_DATA_BITS-1:0] rf_wdata;
// Latch the last s3_result in case we need to forward it.
reg [`CPU_DATA_BITS-1:0] s2_s3_result_reg;
RegisterFile #(
.LOG2_NUM_REGISTERS(5),
.NUM_REGISTERS(32)
) integer_register_file (
.clk(clk),
.reset(reset),
.waddr(rf_waddr),
.wdata(rf_wdata),
.write_enable(s3_reg_we),
.raddr0(rf_raddr0),
.rdata0(rf_rdata0),
.raddr1(rf_raddr1),
.rdata1(rf_rdata1)
);
wire [`CPU_ADDR_BITS-1:0] s1_pc;
wire [`CPU_ADDR_BITS-1:0] override_pc;
//wire [4:0] s1_rs1, [4:0] s1_rs2, [4:0] s1_rd;
wire [11:0] s1_imm_i;
wire [19:0] s1_imm_uj;
wire [11:0] s1_imm_bs;
wire s1_add_rshift_type;
reg [`CPU_ADDR_BITS-1:0] s3_pc_reg;
assign rf_raddr0 = s1_rs1;
assign rf_raddr1 = s1_rs2;
FetchDecodeStage fetch_decode_stage (
.clk(clk),
.reset(reset),
.s1_pc(s1_pc),
.s1_imem_addr(icache_addr),
.s3_pc(s3_pc_reg),
.override_pc(0), // TODO(aryap): Not sure if this is necessary or where to connect it.
.s1_pc_sel(s1_pc_sel),
.s1_inst(icache_dout),
.s1_rs1(s1_rs1),
.s1_rs2(s1_rs2),
.s1_rd(s1_rd),
.s1_imm_i(s1_imm_i),
.s1_imm_uj(s1_imm_uj),
.s1_imm_bs(s1_imm_bs),
.s1_opcode(s1_opcode),
.s1_func(s1_func),
.s1_add_rshift_type(s1_add_rshift_type)
);
// TODO(aryap): CSR can be written immediately in the first stage, since the
// data is available from the register file. But this violates precise
// exceptions, if we care about that. The alternative is to propagate the
// rs1 and csr values through the pipeline stages, which is what we do. But
// if we can get away with it, it will improve performance to do it early.
// Maybe.
//-------------------------------------------------------------------
// Stage 2
//-------------------------------------------------------------------
// S1/S2 pipeline registers.
//
// The naming convention is to follow the stage receiving the latched
// values.
reg [`CPU_DATA_BITS-1:0] s2_csr_data_reg;
reg [`CPU_DATA_BITS-1:0] s2_rs1_data_reg;
reg [`CPU_DATA_BITS-1:0] s2_rs2_data_reg;
reg [11:0] s2_imm_i_reg;
reg [19:0] s2_imm_uj_reg;
reg [11:0] s2_imm_bs_reg;
reg [`CPU_ADDR_BITS-1:0] s2_pc_reg;
reg [6:0] s2_opcode_reg;
reg [2:0] s2_func_reg;
reg s2_add_rshift_type_reg;
reg [4:0] s2_rs1_reg;
reg [4:0] s2_rs2_reg;
reg [4:0] s2_rd_reg;
reg [1:0] s2_byte_sel_reg;
reg s2_s1_fwd_s3_rs1_reg;
reg s2_s1_fwd_s3_rs2_reg;
// Forwarding registers.
reg [`CPU_DATA_BITS-1:0] s3_alu_result_reg;
assign s2_opcode = s2_opcode_reg;
assign dcache_re = s2_dmem_re;
assign s2_rs1 = s2_rs1_reg;
assign s2_rs2 = s2_rs2_reg;
assign s2_rd = s2_rd_reg;
always @(posedge clk) begin
if (!stall) begin
// Because we only implement one CSR, we will add custom logic here to
// connect it instead of another register file. But since it is memory, we
// don't include in the FetchDecodeStage directly. TODO(aryap): Maybe.
s2_csr_data_reg <=
s1_imm_i == 12'h51E && s1_rd != 0 ? csr_tohost_reg : 0;
s2_rs1_data_reg <= rf_rdata0;
s2_rs2_data_reg <= rf_rdata1;
s2_imm_i_reg <= s1_imm_i;
s2_imm_uj_reg <= s1_imm_uj;
s2_imm_bs_reg <= s1_imm_bs;
s2_pc_reg <= s1_pc;
s2_opcode_reg <= s1_opcode;
s2_func_reg <= s1_func;
s2_add_rshift_type_reg <= s1_add_rshift_type;
s2_rs1_reg <= s1_rs1;
s2_rs2_reg <= s1_rs2;
s2_rd_reg <= s1_rd;
s2_s1_fwd_s3_rs1_reg <= s1_fwd_s3_rs1;
s2_s1_fwd_s3_rs2_reg <= s1_fwd_s3_rs2;
// Store the last S3 result for forwarding to the instruction currently
// in S1 (when it gets to S2).
s2_s3_result_reg <= rf_wdata;
end
end
wire [`CPU_DATA_BITS-1:0] s2_imm_i_out;
wire s2_branch;
wire [`CPU_DATA_BITS-1:0] s2_alu_out;
wire [`CPU_ADDR_BITS-1:0] s2_pc_out;
wire [`CPU_DATA_BITS-1:0] s2_rs1_data_eff;
wire [`CPU_DATA_BITS-1:0] s2_rs2_data_eff;
wire [`CPU_DATA_BITS-1:0] s2_rs2_data_out;
// TODO(aryap): Put all of the DMEM signal handling in the Execute stage.
assign s2_rs1_data_eff = s2_fwd_s3_rs1 ? rf_wdata :
s2_s1_fwd_s3_rs1_reg ? s2_s3_result_reg : s2_rs1_data_reg;
assign s2_rs2_data_eff = s2_fwd_s3_rs2 ? rf_wdata :
s2_s1_fwd_s3_rs2_reg ? s2_s3_result_reg : s2_rs2_data_reg;
assign dcache_addr = s2_alu_out;
assign s2_func = s2_func_reg;
// Figure out dmem_we byte mask if dmem writes are enabled.
always @(*) begin
s2_byte_sel_reg = s2_alu_out[1:0];
dcache_din = s2_rs2_data_out;
case (s2_dmem_we)
`S2_DMEM_WE_BYTE: begin
dcache_we = 4'b1 << s2_byte_sel_reg;
dcache_din = s2_rs2_data_out[7:0] << (s2_byte_sel_reg * 8);
end
`S2_DMEM_WE_HALF_WORD: begin
dcache_we = 4'b11 << s2_byte_sel_reg;
dcache_din = s2_rs2_data_out[15:0] << (s2_byte_sel_reg * 8);
end
`S2_DMEM_WE_WORD: begin
dcache_we = 4'b1111;
end
default: begin
dcache_we = 0; // `S2_DMEM_WE_OFF
end
endcase
end
ExecuteStage execute_stage (
.clk(clk),
.reset(reset),
.s2_rs1_data(s2_rs1_data_eff),
.s2_rs2_data(s2_rs2_data_eff),
.s2_imm_i(s2_imm_i_reg),
.s2_imm_uj(s2_imm_uj_reg),
.s2_imm_bs(s2_imm_bs_reg),
.s2_pc(s2_pc_reg),
.s2_opcode(s2_opcode_reg),
.s2_func(s2_func_reg),
.s2_add_rshift_type(s2_add_rshift_type_reg),
.s2_imm_i_out(s2_imm_i_out),
.s2_alu_out(s2_alu_out),
.s2_pc_out(s2_pc_out),
.s2_rs2_data_out(s2_rs2_data_out),
.s2_branch(s2_branch),
// Control signals.
.s2_alu_a_sel(s2_alu_a_sel),
.s2_alu_b_sel(s2_alu_b_sel),
.s2_adder_a_sel(s2_adder_a_sel),
.s2_adder_b_sel(s2_adder_b_sel),
.s2_pc_out_sel(s2_pc_out_sel)
);
//-------------------------------------------------------------------
// Stage 3
//-------------------------------------------------------------------
// S2/S3 pipeline registers.
reg [6:0] s3_opcode_reg;
reg [2:0] s3_func_reg;
reg s3_branch_reg;
reg [`CPU_DATA_BITS-1:0] s3_rs1_data_reg;
reg [`CPU_DATA_BITS-1:0] s3_imm_i_reg;
// NOTE(aryap): This is instead of a general-purpose second write port for
// registers or any bypassing.
reg [`CPU_DATA_BITS-1:0] s3_csr_data_reg;
reg [4:0] s3_rs1_reg;
reg [4:0] s3_rs2_reg;
reg [4:0] s3_rd_reg;
reg [1:0] s3_byte_sel_reg;
assign s3_opcode = s3_opcode_reg;
assign s3_func = s3_func_reg;
assign s3_branch = s3_branch_reg;
assign s3_rs1 = s3_rs1_reg;
assign s3_rs2 = s3_rs2_reg;
assign s3_rd = s3_rd_reg;
always @(posedge clk) begin
if (!stall) begin
s3_opcode_reg <= s2_opcode;
s3_func_reg <= s2_func;
s3_branch_reg <= s2_branch;
s3_alu_result_reg <= s2_alu_out;
s3_rs1_data_reg <= s2_rs1_data_eff;
s3_pc_reg <= s2_pc_out;
s3_rd_reg <= s2_rd_reg;
s3_imm_i_reg <= s2_imm_i_out;
s3_csr_data_reg <= s2_csr_data_reg;
s3_rs1_reg <= s2_rs1_reg;
s3_rs2_reg <= s2_rs2_reg;
s3_byte_sel_reg <= s2_alu_out[1:0];
end
end
wire [`CPU_DATA_BITS-1:0] s3_rdata_out;
WriteBackStage write_back_stage (
.clk(clk),
.reset(reset),
.byte_select(s3_byte_sel_reg),
.s3_rdata_sel(s3_rdata_sel),
.s3_rdata(dcache_dout),
.s3_rdata_out(s3_rdata_out)
);
assign rf_waddr = s3_rd_reg;
always @(*) begin
case (s3_reg_wdata_sel)
`S3_REG_WDATA_SEL_S3_RS1: rf_wdata = s3_rs1_data_reg;
`S3_REG_WDATA_SEL_S3_RESULT: rf_wdata = s3_alu_result_reg;
`S3_REG_WDATA_SEL_S3_RDATA_OUT: rf_wdata = s3_rdata_out;
`S3_REG_WDATA_SEL_S3_CSR_DATA: rf_wdata = s3_csr_data_reg;
default: rf_wdata = s3_alu_result_reg;
endcase
end
// TODO(aryap): Move this with the other immediate generation in
// ExecuteStage?
parameter NUM_IMM_RS1_0_BITS = `CPU_DATA_BITS - 5;
wire [`CPU_DATA_BITS-1:0] s3_imm_rs1 =
{{NUM_IMM_RS1_0_BITS{1'b0}}, s3_rs1_reg};
always @(posedge clk) begin
if (!stall)
if (s3_csr_we)
case (s3_csr_new_data_sel)
`S3_CSR_NEW_DATA_SEL_IMM_RS1: csr_tohost_reg <= s3_imm_rs1;
// `S3_CSR_NEW_DATA_SEL_RS1_DATA
default: csr_tohost_reg <= s3_rs1_data_reg;
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRTP_OV2_PP_SYMBOL_V
`define SKY130_FD_SC_LP__SDFRTP_OV2_PP_SYMBOL_V
/**
* sdfrtp_ov2: ????.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfrtp_ov2 (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRTP_OV2_PP_SYMBOL_V
|
`include "riscv_functions.vh"
module riscv_ex_pipe (
input clk,
input rstn,
//ID to EX inputs
input id_ex_rdy,
output id_ex_ack,
input [31:0] id_ex_op1,
input [31:0] id_ex_op2,
input [`EX_FUNCT_W-1:0] id_ex_funct,
//ID to MEM inputs
input [31:0] id_ex_mem_st_data,
input [`ST_FUNCT_W-1:0] id_ex_mem_st_funct,
input [`LD_FUNCT_W-1:0] id_ex_mem_ld_funct,
//Data bif
output [31:0] data_bif_addr,
output data_bif_rnw,
output data_bif_rdy,
input data_bif_ack,
input [31:0] data_bif_rdata,
output [31:0] data_bif_wdata,
output [3:0] data_bif_wmask,
//RF output
output mem_rf_rdy,
output [31:0] mem_rf_data
);
wire clk;
wire rstn;
wire id_ex_rdy;
wire id_ex_ack;
wire [31:0] id_ex_op1;
wire [31:0] id_ex_op2;
wire [`EX_FUNCT_W-1:0] id_ex_funct;
wire [31:0] id_ex_mem_st_data;
wire [`ST_FUNCT_W-1:0] id_ex_mem_st_funct;
wire [`LD_FUNCT_W-1:0] id_ex_mem_ld_funct;
wire ex_mem_rdy;
wire ex_mem_ack;
wire ex_mem_alu_op;
wire [31:0] ex_mem_st_data;
wire [`LD_FUNCT_W-1:0] ex_mem_ld_funct;
wire [`ST_FUNCT_W-1:0] ex_mem_st_funct;
wire [31:0] ex_mem_data;
wire [31:0] data_bif_addr;
wire data_bif_rnw;
wire data_bif_rdy;
wire data_bif_ack;
wire [31:0] data_bif_rdata;
wire [31:0] data_bif_wdata;
wire [3:0] data_bif_wmask;
wire mem_rf_rdy;
wire [31:0] mem_rf_data;
riscv_ex i_riscv_ex (
.clk (clk),
.rstn (rstn),
.id_ex_rdy (id_ex_rdy),
.id_ex_ack (id_ex_ack),
.id_ex_op1 (id_ex_op1),
.id_ex_op2 (id_ex_op2),
.id_ex_funct (id_ex_funct),
.id_ex_mem_st_data (id_ex_mem_st_data),
.id_ex_mem_st_funct (id_ex_mem_st_funct),
.id_ex_mem_ld_funct (id_ex_mem_ld_funct),
.ex_mem_rdy (ex_mem_rdy),
.ex_mem_ack (ex_mem_ack),
.ex_mem_alu_op (ex_mem_alu_op),
.ex_mem_st_data (ex_mem_st_data),
.ex_mem_ld_funct (ex_mem_ld_funct),
.ex_mem_st_funct (ex_mem_st_funct),
.ex_mem_data (ex_mem_data)
);
riscv_mem i_riscv_mem (
.clk (clk),
.rstn (rstn),
.ex_mem_rdy (ex_mem_rdy),
.ex_mem_ack (ex_mem_ack),
.ex_mem_alu_op (ex_mem_alu_op),
.ex_mem_st_data (ex_mem_st_data),
.ex_mem_ld_funct (ex_mem_ld_funct),
.ex_mem_st_funct (ex_mem_st_funct),
.ex_mem_data (ex_mem_data),
.data_bif_addr (data_bif_addr),
.data_bif_rnw (data_bif_rnw),
.data_bif_rdy (data_bif_rdy),
.data_bif_ack (data_bif_ack),
.data_bif_rdata (data_bif_rdata),
.data_bif_wdata (data_bif_wdata),
.data_bif_wmask (data_bif_wmask),
.mem_rf_rdy (mem_rf_rdy),
.mem_rf_data (mem_rf_data)
);
endmodule
|
module node_noc(clk, rst, data_in, data_in_ready, fifo_in_ready, data_out, data_out_ready);
parameter IDLE = 4'b0000;
parameter IDLE1 = 4'b1111;
parameter KEYWORD = 4'b0001;
parameter TEXTFILE = 4'b0010;
parameter TEXTFILE_1 = 4'b0011;
parameter PAIR_NUM = 10;
input clk;
input rst;
input [31:0] data_in;
input data_in_ready;
input fifo_in_ready; // mapper can write to router when fifo_in_ready==1
output reg [31:0] data_out;
output reg data_out_ready;
reg [31:0] text_in;
wire [31:0] keyword_in;
reg [31:0] keyword_in_reg;
wire [31:0] pair;
wire pair_out;
reg pair_out_reg;
reg [127:0] pair_reg [PAIR_NUM-1:0]; // Store at most 10 pairs now.
reg [4:0] i; // Index the pair_reg
reg [4:0] pair_reg_index;
reg [4:0] pair_reg_index_1;
reg [2:0] pair_reg_counter;
reg [2:0] pair_reg_counter_1;
reg [3:0] current_state;
reg [3:0] next_state;
reg [2:0] key_counter; // Counter keyword reception for 4 cycles.
reg key_en;
reg text_en;
reg [127:0] mem [128:0];
reg [31:0] pt_in;
reg [31:0] pt_out;
reg data_wr;
reg [2:0] data_wr_counter;
always@(posedge clk or negedge rst)
if(!rst) begin
data_out <= 0;
data_out_ready <= 0;
pair_reg_index_1 <= 0;
pair_reg_counter_1 <= 0;
end
else if(pair_reg_index_1<pair_reg_index && fifo_in_ready==1) begin
data_out_ready <= 1;
case(pair_reg_counter_1)
0: begin
data_out <= pair_reg[pair_reg_index_1][31:0];
pair_reg_counter_1 <= 1;
end
1: begin
data_out <= pair_reg[pair_reg_index_1][63:32];
pair_reg_counter_1 <= 2;
end
2: begin
data_out <= pair_reg[pair_reg_index_1][95:64];
pair_reg_counter_1 <= 3;
end
3: begin
data_out <= pair_reg[pair_reg_index_1][127:96];
pair_reg_index_1 <= pair_reg_index_1 + 1;
pair_reg_counter_1 <= 0;
end
default: begin
end
endcase
end
else begin
data_out_ready <= 0;
data_out <= 0;
end
always@(posedge clk or negedge rst)
if(!rst)
pair_out_reg <= 0;
else
pair_out_reg <= pair_out;
always@(posedge clk or negedge rst)
if(!rst) begin
for(i=0; i<PAIR_NUM; i=i+1)
pair_reg[i] <= 0;
pair_reg_counter <= 0;
pair_reg_index <= 0;
end
else if(pair_out_reg == 1) begin
case(pair_reg_counter)
0: begin
pair_reg[pair_reg_index][31:0] <= pair;
pair_reg_counter <= 1;
end
1: begin
pair_reg[pair_reg_index][63:32] <= pair;
pair_reg_counter <= 2;
end
2: begin
pair_reg[pair_reg_index][95:64] <= pair;
pair_reg_counter <= 3;
end
3: begin
pair_reg[pair_reg_index][127:96] <= pair;
pair_reg_counter <= 0;
pair_reg_index <= pair_reg_index + 1;
end
default: begin
pair_reg[pair_reg_index] <= pair_reg[pair_reg_index];
end
endcase
//pair_reg_index <= pair_reg_index + 1;
end
else
pair_reg[pair_reg_index] <= pair_reg[pair_reg_index];
/*always@(posedge clk or negedge rst)
if(!rst) begin
data_out <= 0;
data_out_ready <= 0;
end
else if(fifo_in_ready==1) begin
data_out <= 0;
data_out_ready <= 0;
end
else begin
end */
assign keyword_in = (key_en == 1'b1)?keyword_in_reg:32'bz;
always@(posedge clk or negedge rst)
if(!rst)
current_state <= IDLE;
else
current_state <= next_state;
always@*
case(current_state)
IDLE: begin
if(data_in_ready == 1'b1) next_state = IDLE1;
else next_state = IDLE;
end
IDLE1: begin
next_state = KEYWORD;
end
KEYWORD: begin
if(key_counter == 3) next_state = TEXTFILE;
else next_state = KEYWORD;
end
TEXTFILE: begin
if( pt_out==pt_in && pt_in!=0 ) next_state = TEXTFILE_1;
else next_state = TEXTFILE;
end
TEXTFILE_1: begin
end
default: begin
next_state = IDLE;
end
endcase
always@(posedge clk)
case(current_state)
IDLE: begin
key_counter <= 0;
key_en <= 0;
text_en <= 0;
pt_in <= 0;
pt_out <= 0;
data_wr_counter <= 0;
end
IDLE1: begin
end
KEYWORD: begin
key_counter <= key_counter + 1'd1;
key_en <= 1;
keyword_in_reg <= data_in[31:0];
end
TEXTFILE: begin
key_en <= 0;
text_en <= 1;
if(data_in_ready == 1)
mem[pt_in] <= data_in;
else begin
end
if(data_in_ready==1 && pt_in < 1024) begin
pt_in <= pt_in + 1;
end
else if(pt_in < 1024) begin
pt_in <= pt_in;
end
else begin
pt_in <= 0;
end
if(data_wr_counter == 6) begin
data_wr_counter <=0;
end
else if(data_wr_counter == 1) begin
data_wr <= 1'b1;
data_wr_counter <= data_wr_counter + 1;
text_in <= mem[pt_out];
pt_out <= pt_out + 1;
end
else if(data_wr_counter == 2) begin
data_wr <= 1'b0;
data_wr_counter <= data_wr_counter + 1;
end
else
data_wr_counter <= data_wr_counter + 1;
end
default: begin
end
endcase
node node0(
.clk(clk),
.rst(rst),
.textfile(text_in),
.keyword(keyword_in),
.key_en(key_en),
.data_wr(data_wr));
//.write_free(),
//.pair(pair),
//.pair_out(pair_out),
//.pair_out(pair_out));
endmodule
|
module ledDriver /*#( parameter NUM_LEDS = 60 )*/(input clk, input reset, output reg led, input data, input lastBit, input start, output finish, output read);
//Generate the pulse width modulated output signal
//Running at 20MHz, a High pulse of 8 cycles and 17 low cycles produces a 0,
//16 cycles of high and 9 low a 1.
//Are we doing stuff right now?
reg running = 0;
//Are we waiting for RES?
reg resCounting = 0;
/*
function integer clog2;
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction
parameter LOG_BITS = clog2(NUM_LEDS*24);
reg[LOG_BITS-1:0] bitCnt = 0; */
reg read = 0;
//Count repeatedly counts from 0 to 24.
reg[4:0] count = 0;
always @(posedge clk or posedge reset) begin
if (reset || ~running) begin
count<=0;
end else begin
if (count!=24) begin
count <= count + 1;
end else begin
count <=0;
end
end
end
/*
wire lastBit;
assign lastBit = (bitCnt==(NUM_LEDS*24-1));*/
reg firstbit = 0;
always @(posedge clk or posedge reset) begin
if (reset) begin
running <= 0;
firstbit <= 1;
read <= 0;
end else begin
if (~running & start) begin
running <= 1;
//data <= inData;
//bitCnt<= 0;
firstbit <= 1;
end else if (running) begin
firstbit<=0;
if (lastBit && count==24) begin
running <= 0;
resCounting <= 1;
read <= 0;
end else if (count==0 && ~firstbit) begin
//data <= data << 1;
read <= 1;
//bitCnt <= bitCnt +1;
end else read <= 0;
end else if (resCounting && finish) begin
resCounting <= 0;
end
end
end
/*//The bit being currently output
wire current;
//Is always the highest bit in the shift reg
assign current = data[(NUM_LEDS*24)-1]; */
//Pulse out the data
always @(posedge clk or posedge reset) begin
if (reset || ~running) begin
led <= 0;
end else begin
if (count==0) begin
led <= 1;
end else if ( (count==8 && ~data) || (count==16 && data)) begin
led<=0;
end
end
end
//Counter for res contition
reg [10:0] resCounter=0;
always @(posedge clk or posedge reset) begin
if (reset || ~resCounting) begin
resCounter=0;
end else begin
resCounter <= resCounter+1;
end
end
assign finish = resCounter==11'h7FF;
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR4B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__OR4B_BEHAVIORAL_PP_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__or4b (
VPWR,
VGND,
X ,
A ,
B ,
C ,
D_N
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
input B ;
input C ;
input D_N ;
// Local signals
wire DN not0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
not not0 (not0_out , D_N );
or or0 (or0_out_X , not0_out, C, B, A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR4B_BEHAVIORAL_PP_V |
// ============================================================================
// Copyright (c) 2010
// ============================================================================
//
// Permission:
//
//
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods.
// ============================================================================
//
// ReConfigurable Computing Group
//
// web: http://www.ecs.umass.edu/ece/tessier/rcg/
//
//
// ============================================================================
// Major Functions/Design Description:
//
//
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |RCG |05/10/2011 |
// ============================================================================
//include "NF_2.1_defines.v"
//include "reg_defines_reference_router.v"
module unencoded_cam_lut_sm_lpm
#(parameter CMP_WIDTH = 32,
parameter DATA_WIDTH = 3,
parameter LUT_DEPTH = 16,
parameter LUT_DEPTH_BITS = log2(LUT_DEPTH),
parameter DEFAULT_DATA = 0, // DATA to return on a miss
parameter RESET_DATA = {DATA_WIDTH{1'b0}}, // value of data on reset
parameter RESET_CMP_DATA = {CMP_WIDTH{1'b0}}, // value of compare datae on reset
parameter RESET_CMP_DMASK = {CMP_WIDTH{1'b0}} // value compare of data mask on reset
)
(// --- Interface for lookups
input lookup_req,
input [CMP_WIDTH-1:0] lookup_cmp_data,
input [CMP_WIDTH-1:0] lookup_cmp_dmask,
output reg lookup_ack,
output reg lookup_hit,
output [DATA_WIDTH-1:0] lookup_data,
// --- Interface to registers
// --- Read port
input [LUT_DEPTH_BITS-1:0] rd_addr, // address in table to read
input rd_req, // request a read
output [DATA_WIDTH-1:0] rd_data, // data found for the entry
output [CMP_WIDTH-1:0] rd_cmp_data, // matching data for the entry
output [CMP_WIDTH-1:0] rd_cmp_dmask, // don't cares entry
output reg rd_ack, // pulses high
// --- Write port
input [LUT_DEPTH_BITS-1:0] wr_addr,
input wr_req,
input [DATA_WIDTH-1:0] wr_data, // data found for the entry
input [CMP_WIDTH-1:0] wr_cmp_data, // matching data for the entry
input [CMP_WIDTH-1:0] wr_cmp_dmask, // don't cares for the entry
output reg wr_ack,
// --- CAM interface
input cam_busy,
input cam_match,
input [LUT_DEPTH-1:0] cam_match_addr,
output [CMP_WIDTH-1:0] cam_cmp_din,
output reg [CMP_WIDTH-1:0] cam_din,
output reg cam_we,
output reg [LUT_DEPTH_BITS-1:0] cam_wr_addr,
output [CMP_WIDTH-1:0] cam_cmp_data_mask,
output reg [CMP_WIDTH-1:0] cam_data_mask,
// --- Misc
input reset,
input clk
);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
//-------------------- Internal Parameters ------------------------
localparam RESET = 0;
localparam READY = 1;
//---------------------- Wires and regs----------------------------
reg [LUT_DEPTH_BITS-1:0] lut_rd_addr;
reg [DATA_WIDTH+2*CMP_WIDTH-1:0] lut_rd_data;
reg [DATA_WIDTH-1:0] lut_wr_data;
reg [DATA_WIDTH+2*CMP_WIDTH-1:0] lut[LUT_DEPTH-1:0];
reg lookup_latched;
reg cam_match_found;
reg cam_lookup_done;
reg rd_req_latched;
reg cam_match_encoded;
reg cam_match_found_d1;
reg [LUT_DEPTH-1:0] cam_match_unencoded_addr;
reg [LUT_DEPTH_BITS-1:0] cam_match_encoded_addr;
reg lookup_latched_first_time;
// synthesis attribute PRIORITY_EXTRACT of cam_match_encoded_addr is force;
integer i;
/* used to track the addresses for resetting the CAM and the LUT */
reg [LUT_DEPTH_BITS:0] reset_count;
reg state;
//reg lookup_latched_first_time;
//------------------------- Logic --------------------------------
assign cam_cmp_din = lookup_cmp_data;
assign cam_cmp_data_mask = lookup_cmp_dmask;
assign lookup_data = (lookup_hit & lookup_ack) ? lut_rd_data[DATA_WIDTH-1:0] : DEFAULT_DATA;
assign rd_data = lut_rd_data[DATA_WIDTH-1:0];
assign rd_cmp_data = lut_rd_data[DATA_WIDTH+CMP_WIDTH-1:DATA_WIDTH];
assign rd_cmp_dmask = lut_rd_data[DATA_WIDTH+2*CMP_WIDTH-1:DATA_WIDTH+CMP_WIDTH];
/* encode the match address */
always @(*) begin
cam_match_encoded_addr = LUT_DEPTH[LUT_DEPTH_BITS-1:0] - 1'b1;
for (i = LUT_DEPTH-2; i >= 0; i = i-1) begin
if (cam_match_unencoded_addr[i]) begin
cam_match_encoded_addr = i[LUT_DEPTH_BITS-1:0];
end
end
end
always @(posedge clk) begin
if(reset) begin
lookup_latched <= 0;
cam_match_found <= 0;
cam_lookup_done <= 0;
rd_req_latched <= 0;
lookup_ack <= 0;
lookup_hit <= 0;
cam_we <= 0;
cam_wr_addr <= 0;
cam_din <= 0;
cam_data_mask <= 0;
wr_ack <= 0;
state <= RESET;
reset_count <= 0;
end // if (reset)
else begin
if (state == RESET && !cam_busy) begin
if(1) begin // if(reset_count == LUT_DEPTH) begin
state <= READY;
cam_we <= 1'b0;
end
else begin
reset_count <= reset_count + 1'b1;
cam_we <= 1'b1;
cam_wr_addr <= reset_count[LUT_DEPTH_BITS-1:0];
cam_din <= RESET_CMP_DATA;
cam_data_mask <= RESET_CMP_DMASK;
lut_wr_data <= RESET_DATA;
end
end
else if (state == READY) begin
/* first pipeline stage -- do CAM lookup */
lookup_latched_first_time <= lookup_req;
lookup_latched <= lookup_latched_first_time;
/* second pipeline stage -- CAM result/LUT input*/
cam_match_found <= lookup_latched & cam_match;
cam_lookup_done <= lookup_latched;
cam_match_unencoded_addr <= cam_match_addr;
/* third pipeline stage -- encode the CAM output */
cam_match_encoded <= cam_lookup_done;
cam_match_found_d1 <= cam_match_found;
lut_rd_addr <= (!cam_match_found && rd_req) ? rd_addr : cam_match_encoded_addr;
rd_req_latched <= (!cam_match_found && rd_req);
/* fourth pipeline stage -- read LUT */
lookup_ack <= cam_match_encoded;
lookup_hit <= cam_match_found_d1;
lut_rd_data <= lut[lut_rd_addr];
rd_ack <= rd_req_latched;
/* Handle writes */
if(wr_req & !cam_busy & !lookup_latched & !cam_match_found & !cam_match_found_d1) begin
cam_we <= 1;
cam_wr_addr <= wr_addr;
cam_din <= wr_cmp_data ;
cam_data_mask <= ~wr_cmp_dmask;
wr_ack <= 1;
lut_wr_data <= wr_data;
end
else begin
cam_we <= 0;
wr_ack <= 0;
end // else: !if(wr_req & !cam_busy & !lookup_latched & !cam_match_found & !cam_match_found_d1)
end // else: !if(state == RESET)
end // else: !if(reset)
// separate this out to allow implementation as BRAM
if(cam_we) begin
lut[cam_wr_addr] <= {cam_data_mask, cam_din, lut_wr_data};
end
end // always @ (posedge clk)
endmodule // cam_lut_sm
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O211AI_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__O211AI_PP_SYMBOL_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o211ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input C1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O211AI_PP_SYMBOL_V
|
(** * Logic: Logic in Coq *)
Require Export MoreCoq.
(** Coq's built-in logic is very small: the only primitives are
[Inductive] definitions, universal quantification ([forall]), and
implication ([->]), while all the other familiar logical
connectives -- conjunction, disjunction, negation, existential
quantification, even equality -- can be encoded using just these.
This chapter explains the encodings and shows how the tactics
we've seen can be used to carry out standard forms of logical
reasoning involving these connectives. *)
(* ########################################################### *)
(** * Propositions *)
(** In previous chapters, we have seen many examples of factual
claims (_propositions_) and ways of presenting evidence of their
truth (_proofs_). In particular, we have worked extensively with
_equality propositions_ of the form [e1 = e2], with
implications ([P -> Q]), and with quantified propositions
([forall x, P]).
*)
(** In Coq, the type of things that can (potentially)
be proven is [Prop]. *)
(** Here is an example of a provable proposition: *)
Check (3 = 3).
(* ===> Prop *)
(** Here is an example of an unprovable proposition: *)
Check (forall (n:nat), n = 2).
(* ===> Prop *)
(** Recall that [Check] asks Coq to tell us the type of the indicated
expression. *)
(* ########################################################### *)
(** * Proofs and Evidence *)
(** In Coq, propositions have the same status as other types, such as
[nat]. Just as the natural numbers [0], [1], [2], etc. inhabit
the type [nat], a Coq proposition [P] is inhabited by its
_proofs_. We will refer to such inhabitants as _proof term_ or
_proof object_ or _evidence_ for the truth of [P].
In Coq, when we state and then prove a lemma such as:
Lemma silly : 0 * 3 = 0.
Proof. reflexivity. Qed.
the tactics we use within the [Proof]...[Qed] keywords tell Coq
how to construct a proof term that inhabits the proposition. In
this case, the proposition [0 * 3 = 0] is justified by a
combination of the _definition_ of [mult], which says that [0 * 3]
_simplifies_ to just [0], and the _reflexive_ principle of
equality, which says that [0 = 0].
*)
(** *** *)
Lemma silly : 0 * 3 = 0.
Proof. reflexivity. Qed.
(** We can see which proof term Coq constructs for a given Lemma by
using the [Print] directive: *)
Print silly.
(* ===> silly = eq_refl : 0 * 3 = 0 *)
(** Here, the [eq_refl] proof term witnesses the equality. (More on equality later!)*)
(** ** Implications _are_ functions *)
(** Just as we can implement natural number multiplication as a
function:
[
mult : nat -> nat -> nat
]
The _proof term_ for an implication [P -> Q] is a _function_ that takes evidence for [P] as input and produces evidence for [Q] as its output.
*)
Lemma silly_implication : (1 + 1) = 2 -> 0 * 3 = 0.
Proof. intros H. reflexivity. Qed.
(** We can see that the proof term for the above lemma is indeed a
function: *)
Print silly_implication.
(* ===> silly_implication = fun _ : 1 + 1 = 2 => eq_refl
: 1 + 1 = 2 -> 0 * 3 = 0 *)
(** ** Defining Propositions *)
(** Just as we can create user-defined inductive types (like the
lists, binary representations of natural numbers, etc., that we
seen before), we can also create _user-defined_ propositions.
Question: How do you define the meaning of a proposition?
*)
(** *** *)
(** The meaning of a proposition is given by _rules_ and _definitions_
that say how to construct _evidence_ for the truth of the
proposition from other evidence.
- Typically, rules are defined _inductively_, just like any other datatype.
- Sometimes a proposition is declared to be true without substantiating evidence. Such propositions are called _axioms_.
In this, and subsequence chapters, we'll see more about how these
proof terms work in more detail.
*)
(* ########################################################### *)
(** * Conjunction (Logical "and") *)
(** The logical conjunction of propositions [P] and [Q] can be
represented using an [Inductive] definition with one
constructor. *)
Inductive and (P Q : Prop) : Prop :=
conj : P -> Q -> (and P Q).
(** The intuition behind this definition is simple: to
construct evidence for [and P Q], we must provide evidence
for [P] and evidence for [Q]. More precisely:
- [conj p q] can be taken as evidence for [and P Q] if [p]
is evidence for [P] and [q] is evidence for [Q]; and
- this is the _only_ way to give evidence for [and P Q] --
that is, if someone gives us evidence for [and P Q], we
know it must have the form [conj p q], where [p] is
evidence for [P] and [q] is evidence for [Q].
Since we'll be using conjunction a lot, let's introduce a more
familiar-looking infix notation for it. *)
Notation "P /\ Q" := (and P Q) : type_scope.
(** (The [type_scope] annotation tells Coq that this notation
will be appearing in propositions, not values.) *)
(** Consider the "type" of the constructor [conj]: *)
Check conj.
(* ===> forall P Q : Prop, P -> Q -> P /\ Q *)
(** Notice that it takes 4 inputs -- namely the propositions [P]
and [Q] and evidence for [P] and [Q] -- and returns as output the
evidence of [P /\ Q]. *)
(** ** "Introducing" Conjuctions *)
(** Besides the elegance of building everything up from a tiny
foundation, what's nice about defining conjunction this way is
that we can prove statements involving conjunction using the
tactics that we already know. For example, if the goal statement
is a conjuction, we can prove it by applying the single
constructor [conj], which (as can be seen from the type of [conj])
solves the current goal and leaves the two parts of the
conjunction as subgoals to be proved separately. *)
Theorem and_example :
(0 = 0) /\ (4 = mult 2 2).
Proof.
apply conj.
Case "left". reflexivity.
Case "right". reflexivity. Qed.
(** Just for convenience, we can use the tactic [split] as a shorthand for
[apply conj]. *)
Theorem and_example' :
(0 = 0) /\ (4 = mult 2 2).
Proof.
split.
Case "left". reflexivity.
Case "right". reflexivity. Qed.
(** ** "Eliminating" conjunctions *)
(** Conversely, the [inversion] tactic can be used to take a
conjunction hypothesis in the context, calculate what evidence
must have been used to build it, and add variables representing
this evidence to the proof context. *)
Theorem proj1 : forall P Q : Prop,
P /\ Q -> P.
Proof.
intros P Q H.
inversion H as [HP HQ].
apply HP. Qed.
(** **** Exercise: 1 star, optional (proj2) *)
Theorem proj2 : forall P Q : Prop,
P /\ Q -> Q.
Proof.
intros.
inversion H.
apply H1. Qed.
(** [] *)
Theorem and_commut : forall P Q : Prop,
P /\ Q -> Q /\ P.
Proof.
(* WORKED IN CLASS *)
intros P Q H.
inversion H as [HP HQ].
split.
Case "left". apply HQ.
Case "right". apply HP. Qed.
(** **** Exercise: 2 stars (and_assoc) *)
(** In the following proof, notice how the _nested pattern_ in the
[inversion] breaks the hypothesis [H : P /\ (Q /\ R)] down into
[HP: P], [HQ : Q], and [HR : R]. Finish the proof from there: *)
Theorem and_assoc : forall P Q R : Prop,
P /\ (Q /\ R) -> (P /\ Q) /\ R.
Proof.
intros P Q R H.
inversion H as [HP [HQ HR]].
split.
split. apply HP. apply HQ. apply HR. Qed.
(** [] *)
(* ###################################################### *)
(** * Iff *)
(** The handy "if and only if" connective is just the conjunction of
two implications. *)
Definition iff (P Q : Prop) := (P -> Q) /\ (Q -> P).
Notation "P <-> Q" := (iff P Q)
(at level 95, no associativity)
: type_scope.
Theorem iff_implies : forall P Q : Prop,
(P <-> Q) -> P -> Q.
Proof.
intros P Q H.
inversion H as [HAB HBA]. apply HAB. Qed.
Theorem iff_sym : forall P Q : Prop,
(P <-> Q) -> (Q <-> P).
Proof.
(* WORKED IN CLASS *)
intros P Q H.
inversion H as [HAB HBA].
split.
Case "->". apply HBA.
Case "<-". apply HAB. Qed.
(** **** Exercise: 1 star, optional (iff_properties) *)
(** Using the above proof that [<->] is symmetric ([iff_sym]) as
a guide, prove that it is also reflexive and transitive. *)
Theorem iff_refl : forall P : Prop,
P <-> P.
Proof.
intros. split; intros; apply H. Qed.
Theorem iff_trans : forall P Q R : Prop,
(P <-> Q) -> (Q <-> R) -> (P <-> R).
Proof.
intros. split. intros.
inversion H as [HP HQ].
inversion H0 as [H0Q H0R].
apply H0Q. apply HP. apply H1.
inversion H as [HP HQ].
inversion H0 as [H0Q H0R].
intros. apply HQ. apply H0R. apply H1. Qed.
(** Hint: If you have an iff hypothesis in the context, you can use
[inversion] to break it into two separate implications. (Think
about why this works.) *)
(** [] *)
(** Some of Coq's tactics treat [iff] statements specially, thus
avoiding the need for some low-level manipulation when reasoning
with them. In particular, [rewrite] can be used with [iff]
statements, not just equalities. *)
(* ############################################################ *)
(** * Disjunction (Logical "or") *)
(** ** Implementing Disjunction *)
(** Disjunction ("logical or") can also be defined as an
inductive proposition. *)
Inductive or (P Q : Prop) : Prop :=
| or_introl : P -> or P Q
| or_intror : Q -> or P Q.
Notation "P \/ Q" := (or P Q) : type_scope.
(** Consider the "type" of the constructor [or_introl]: *)
Check or_introl.
(* ===> forall P Q : Prop, P -> P \/ Q *)
(** It takes 3 inputs, namely the propositions [P], [Q] and
evidence of [P], and returns, as output, the evidence of [P \/ Q].
Next, look at the type of [or_intror]: *)
Check or_intror.
(* ===> forall P Q : Prop, Q -> P \/ Q *)
(** It is like [or_introl] but it requires evidence of [Q]
instead of evidence of [P]. *)
(** Intuitively, there are two ways of giving evidence for [P \/ Q]:
- give evidence for [P] (and say that it is [P] you are giving
evidence for -- this is the function of the [or_introl]
constructor), or
- give evidence for [Q], tagged with the [or_intror]
constructor. *)
(** *** *)
(** Since [P \/ Q] has two constructors, doing [inversion] on a
hypothesis of type [P \/ Q] yields two subgoals. *)
Theorem or_commut : forall P Q : Prop,
P \/ Q -> Q \/ P.
Proof.
intros P Q H.
inversion H as [HP | HQ].
Case "left". apply or_intror. apply HP.
Case "right". apply or_introl. apply HQ. Qed.
(** From here on, we'll use the shorthand tactics [left] and [right]
in place of [apply or_introl] and [apply or_intror]. *)
Theorem or_commut' : forall P Q : Prop,
P \/ Q -> Q \/ P.
Proof.
intros P Q H.
inversion H as [HP | HQ].
Case "left". right. apply HP.
Case "right". left. apply HQ. Qed.
Theorem or_distributes_over_and_1 : forall P Q R : Prop,
P \/ (Q /\ R) -> (P \/ Q) /\ (P \/ R).
Proof.
intros P Q R. intros H. inversion H as [HP | [HQ HR]].
Case "left". split.
SCase "left". left. apply HP.
SCase "right". left. apply HP.
Case "right". split.
SCase "left". right. apply HQ.
SCase "right". right. apply HR. Qed.
Theorem or_distributes_over_and_2 : forall P Q R : Prop,
(P \/ Q) /\ (P \/ R) -> P \/ (Q /\ R).
Proof.
intros.
inversion H as [HPQ HPR].
inversion HPQ as [HP | HQ].
Case "left". left. apply HP.
Case "right". inversion HPR as [HP' | HR].
SCase "left". left. apply HP'.
SCase "right". right.
split.
SSCase "left". apply HQ.
SSCase "right". apply HR.
Qed.
Definition truth (P Q R : Prop) (ip : (P \/ Q) /\ (P \/ R)) : P \/ (Q /\ R) :=
match ip with
| conj pq pr => match pq with
| or_introl p => or_introl P (Q /\ R) p
| or_intror q => match pr with
| or_introl p => or_introl P (Q /\ R) p
| or_intror r => or_intror P (Q /\ R) (conj Q R q r)
end
end
end.
(** **** Exercise: 2 stars (or_distributes_over_and_2) *)
Theorem or_distributes_over_and_2_alt : forall P Q R : Prop,
(P \/ Q) /\ (P \/ R) -> P \/ (Q /\ R).
Proof.
intros. apply truth in H. assumption.
Qed.
(** [] *)
(** **** Exercise: 1 star, optional (or_distributes_over_and) *)
Theorem or_distributes_over_and : forall P Q R : Prop,
P \/ (Q /\ R) <-> (P \/ Q) /\ (P \/ R).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################### *)
(** ** Relating [/\] and [\/] with [andb] and [orb] (advanced) *)
(** We've already seen several places where analogous structures
can be found in Coq's computational ([Type]) and logical ([Prop])
worlds. Here is one more: the boolean operators [andb] and [orb]
are clearly analogs of the logical connectives [/\] and [\/].
This analogy can be made more precise by the following theorems,
which show how to translate knowledge about [andb] and [orb]'s
behaviors on certain inputs into propositional facts about those
inputs. *)
Theorem andb_prop : forall b c,
andb b c = true -> b = true /\ c = true.
Proof.
(* WORKED IN CLASS *)
intros b c H.
destruct b.
Case "b = true". destruct c.
SCase "c = true". apply conj. reflexivity. reflexivity.
SCase "c = false". inversion H.
Case "b = false". inversion H. Qed.
Theorem andb_true_intro : forall b c,
b = true /\ c = true -> andb b c = true.
Proof.
(* WORKED IN CLASS *)
intros b c H.
inversion H.
rewrite H0. rewrite H1. reflexivity. Qed.
(** **** Exercise: 2 stars, optional (bool_prop) *)
Theorem andb_false : forall b c,
andb b c = false -> b = false \/ c = false.
Proof.
(* FILL IN HERE *) Admitted.
Theorem orb_prop : forall b c,
orb b c = true -> b = true \/ c = true.
Proof.
(* FILL IN HERE *) Admitted.
Theorem orb_false_elim : forall b c,
orb b c = false -> b = false /\ c = false.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################### *)
(** * Falsehood *)
(** Logical falsehood can be represented in Coq as an inductively
defined proposition with no constructors. *)
Inductive False : Prop := .
(** Intuition: [False] is a proposition for which there is no way
to give evidence. *)
(** Since [False] has no constructors, inverting an assumption
of type [False] always yields zero subgoals, allowing us to
immediately prove any goal. *)
Theorem False_implies_nonsense :
False -> 2 + 2 = 5.
Proof.
intros contra.
inversion contra. Qed.
(** How does this work? The [inversion] tactic breaks [contra] into
each of its possible cases, and yields a subgoal for each case.
As [contra] is evidence for [False], it has _no_ possible cases,
hence, there are no possible subgoals and the proof is done. *)
(** *** *)
(** Conversely, the only way to prove [False] is if there is already
something nonsensical or contradictory in the context: *)
Theorem nonsense_implies_False :
2 + 2 = 5 -> False.
Proof.
intros contra.
inversion contra. Qed.
(** Actually, since the proof of [False_implies_nonsense]
doesn't actually have anything to do with the specific nonsensical
thing being proved; it can easily be generalized to work for an
arbitrary [P]: *)
Theorem ex_falso_quodlibet : forall (P:Prop),
False -> P.
Proof.
(* WORKED IN CLASS *)
intros P contra.
inversion contra. Qed.
(** The Latin _ex falso quodlibet_ means, literally, "from
falsehood follows whatever you please." This theorem is also
known as the _principle of explosion_. *)
(* #################################################### *)
(** ** Truth *)
(** Since we have defined falsehood in Coq, one might wonder whether
it is possible to define truth in the same way. We can. *)
(** **** Exercise: 2 stars, advanced (True) *)
(** Define [True] as another inductively defined proposition. (The
intution is that [True] should be a proposition for which it is
trivial to give evidence.) *)
(* FILL IN HERE *)
(** [] *)
(** However, unlike [False], which we'll use extensively, [True] is
used fairly rarely. By itself, it is trivial (and therefore
uninteresting) to prove as a goal, and it carries no useful
information as a hypothesis. But it can be useful when defining
complex [Prop]s using conditionals, or as a parameter to
higher-order [Prop]s. *)
(* #################################################### *)
(** * Negation *)
(** The logical complement of a proposition [P] is written [not
P] or, for shorthand, [~P]: *)
Definition not (P:Prop) := P -> False.
(** The intuition is that, if [P] is not true, then anything at
all (even [False]) follows from assuming [P]. *)
Notation "~ x" := (not x) : type_scope.
Check not.
(* ===> Prop -> Prop *)
(** It takes a little practice to get used to working with
negation in Coq. Even though you can see perfectly well why
something is true, it can be a little hard at first to get things
into the right configuration so that Coq can see it! Here are
proofs of a few familiar facts about negation to get you warmed
up. *)
Theorem not_False :
~ False.
Proof.
unfold not. intros H. inversion H. Qed.
(** *** *)
Theorem contradiction_implies_anything : forall P Q : Prop,
(P /\ ~P) -> Q.
Proof.
(* WORKED IN CLASS *)
intros P Q H. inversion H as [HP HNA]. unfold not in HNA.
apply HNA in HP. inversion HP. Qed.
Theorem double_neg : forall P : Prop,
P -> ~~P.
Proof.
(* WORKED IN CLASS *)
intros P H. unfold not. intros G. apply G. apply H. Qed.
(** **** Exercise: 2 stars, advanced (double_neg_inf) *)
(** Write an informal proof of [double_neg]:
_Theorem_: [P] implies [~~P], for any proposition [P].
_Proof_:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 2 stars (contrapositive) *)
Theorem contrapositive : forall P Q : Prop,
(P -> Q) -> (~Q -> ~P).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star (not_both_true_and_false) *)
Theorem not_both_true_and_false : forall P : Prop,
~ (P /\ ~P).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star, advanced (informal_not_PNP) *)
(** Write an informal proof (in English) of the proposition [forall P
: Prop, ~(P /\ ~P)]. *)
(* FILL IN HERE *)
(** [] *)
(** *** Constructive logic *)
(** Note that some theorems that are true in classical logic are _not_
provable in Coq's (constructive) logic. E.g., let's look at how
this proof gets stuck... *)
Theorem classic_double_neg : forall P : Prop,
~~P -> P.
Proof.
(* WORKED IN CLASS *)
intros P H. unfold not in H.
(* But now what? There is no way to "invent" evidence for [~P]
from evidence for [P]. *)
Abort.
(** **** Exercise: 5 stars, advanced, optional (classical_axioms) *)
(** For those who like a challenge, here is an exercise
taken from the Coq'Art book (p. 123). The following five
statements are often considered as characterizations of
classical logic (as opposed to constructive logic, which is
what is "built in" to Coq). We can't prove them in Coq, but
we can consistently add any one of them as an unproven axiom
if we wish to work in classical logic. Prove that these five
propositions are equivalent. *)
Definition peirce := forall P Q: Prop,
((P->Q)->P)->P.
Definition classic := forall P:Prop,
~~P -> P.
Definition excluded_middle := forall P:Prop,
P \/ ~P.
Definition de_morgan_not_and_not := forall P Q:Prop,
~(~P /\ ~Q) -> P\/Q.
Definition implies_to_or := forall P Q:Prop,
(P->Q) -> (~P\/Q).
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars (excluded_middle_irrefutable) *)
(** This theorem implies that it is always safe to add a decidability
axiom (i.e. an instance of excluded middle) for any _particular_ Prop [P].
Why? Because we cannot prove the negation of such an axiom; if we could,
we would have both [~ (P \/ ~P)] and [~ ~ (P \/ ~P)], a contradiction. *)
Theorem excluded_middle_irrefutable: forall (P:Prop), ~ ~ (P \/ ~ P).
Proof.
(* FILL IN HERE *) Admitted.
(* ########################################################## *)
(** ** Inequality *)
(** Saying [x <> y] is just the same as saying [~(x = y)]. *)
Notation "x <> y" := (~ (x = y)) : type_scope.
(** Since inequality involves a negation, it again requires
a little practice to be able to work with it fluently. Here
is one very useful trick. If you are trying to prove a goal
that is nonsensical (e.g., the goal state is [false = true]),
apply the lemma [ex_falso_quodlibet] to change the goal to
[False]. This makes it easier to use assumptions of the form
[~P] that are available in the context -- in particular,
assumptions of the form [x<>y]. *)
Theorem not_false_then_true : forall b : bool,
b <> false -> b = true.
Proof.
intros b H. destruct b.
Case "b = true". reflexivity.
Case "b = false".
unfold not in H.
apply ex_falso_quodlibet.
apply H. reflexivity. Qed.
(** *** *)
(** *** *)
(** *** *)
(** *** *)
(** *** *)
(** **** Exercise: 2 stars (false_beq_nat) *)
Theorem false_beq_nat : forall n m : nat,
n <> m ->
beq_nat n m = false.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional (beq_nat_false) *)
Theorem beq_nat_false : forall n m,
beq_nat n m = false -> n <> m.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* $Date: 2014-06-05 07:22:21 -0400 (Thu, 05 Jun 2014) $ *)
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module vgafb_pixelfeed #(
parameter fml_depth = 26
) (
input sys_clk,
/* We must take into account both resets :
* VGA reset should not interrupt a pending FML request
* but system reset should.
*/
input sys_rst,
input vga_rst,
input [17:0] nbursts,
input [fml_depth-1:0] baseaddress,
output baseaddress_ack,
output reg [fml_depth-1:0] fml_adr,
output reg fml_stb,
input fml_ack,
input [63:0] fml_di,
output reg dcb_stb,
output [fml_depth-1:0] dcb_adr,
input [63:0] dcb_dat,
input dcb_hit,
output pixel_valid,
output [15:0] pixel,
input pixel_ack
);
/* FIFO that stores the 64-bit bursts and slices it in 16-bit words */
reg fifo_source_cache;
reg fifo_stb;
wire fifo_valid;
vgafb_fifo64to16 fifo64to16(
.sys_clk(sys_clk),
.vga_rst(vga_rst),
.stb(fifo_stb),
.di(fifo_source_cache ? dcb_dat : fml_di),
.do_valid(fifo_valid),
.do(pixel),
.next(pixel_ack)
);
assign pixel_valid = fifo_valid;
/* BURST COUNTER */
reg sof;
wire counter_en;
reg [17:0] bcounter;
always @(posedge sys_clk) begin
if(vga_rst) begin
bcounter <= 18'd1;
sof <= 1'b1;
end else begin
if(counter_en) begin
if(bcounter == nbursts) begin
bcounter <= 18'd1;
sof <= 1'b1;
end else begin
bcounter <= bcounter + 18'd1;
sof <= 1'b0;
end
end
end
end
/* FML ADDRESS GENERATOR */
wire next_address;
assign baseaddress_ack = sof & next_address;
always @(posedge sys_clk) begin
if(sys_rst) begin
fml_adr <= {fml_depth{1'b0}};
end else begin
if(next_address) begin
if(sof)
fml_adr <= baseaddress;
else
fml_adr <= fml_adr + {{fml_depth-6{1'b0}}, 6'd32};
end
end
end
/* DCB ADDRESS GENERATOR */
reg [1:0] dcb_index;
always @(posedge sys_clk) begin
if(dcb_stb)
dcb_index <= dcb_index + 2'd1;
else
dcb_index <= 2'd0;
end
assign dcb_adr = {fml_adr[fml_depth-1:5], dcb_index, 3'b000};
/* CONTROLLER */
reg [3:0] state;
reg [3:0] next_state;
parameter IDLE = 4'd0;
parameter TRYCACHE = 4'd1;
parameter CACHE1 = 4'd2;
parameter CACHE2 = 4'd3;
parameter CACHE3 = 4'd4;
parameter CACHE4 = 4'd5;
parameter FML1 = 4'd6;
parameter FML2 = 4'd7;
parameter FML3 = 4'd8;
parameter FML4 = 4'd9;
always @(posedge sys_clk) begin
if(sys_rst)
state <= IDLE;
else
state <= next_state;
end
/*
* Do not put spurious data into the FIFO if the VGA reset
* is asserted and released during the FML access. Getting
* the FIFO out of sync would result in distorted pictures
* we really want to avoid.
*/
reg ignore;
reg ignore_clear;
always @(posedge sys_clk) begin
if(vga_rst)
ignore <= 1'b1;
else if(ignore_clear)
ignore <= 1'b0;
end
reg next_burst;
assign counter_en = next_burst;
assign next_address = next_burst;
always @(*) begin
next_state = state;
fifo_stb = 1'b0;
next_burst = 1'b0;
fml_stb = 1'b0;
ignore_clear = 1'b0;
dcb_stb = 1'b0;
fifo_source_cache = 1'b0;
case(state)
IDLE: begin
if(~fifo_valid & ~vga_rst) begin
/* We're in need of pixels ! */
next_burst = 1'b1;
ignore_clear = 1'b1;
next_state = TRYCACHE;
end
end
/* Try to fetch from L2 first */
TRYCACHE: begin
dcb_stb = 1'b1;
next_state = CACHE1;
end
CACHE1: begin
fifo_source_cache = 1'b1;
if(dcb_hit) begin
dcb_stb = 1'b1;
if(~ignore) fifo_stb = 1'b1;
next_state = CACHE2;
end else
next_state = FML1; /* Not in L2 cache, fetch from DRAM */
end
/* No need to check for cache hits anymore:
* - we fetched from the beginning of a line
* - we fetch exactly a line
* - we do not release dcb_stb so the cache controller locks the line
* Therefore, next 3 fetchs always are cache hits.
*/
CACHE2: begin
dcb_stb = 1'b1;
fifo_source_cache = 1'b1;
if(~ignore) fifo_stb = 1'b1;
next_state = CACHE3;
end
CACHE3: begin
dcb_stb = 1'b1;
fifo_source_cache = 1'b1;
if(~ignore) fifo_stb = 1'b1;
next_state = CACHE4;
end
CACHE4: begin
fifo_source_cache = 1'b1;
if(~ignore) fifo_stb = 1'b1;
next_state = IDLE;
end
FML1: begin
fml_stb = 1'b1;
if(fml_ack) begin
if(~ignore) fifo_stb = 1'b1;
next_state = FML2;
end
end
FML2: begin
if(~ignore) fifo_stb = 1'b1;
next_state = FML3;
end
FML3: begin
if(~ignore) fifo_stb = 1'b1;
next_state = FML4;
end
FML4: begin
if(~ignore) fifo_stb = 1'b1;
next_state = IDLE;
end
endcase
end
endmodule
|
/*
* SBN machine with hardwired FSM control
* (c) Volker Strumpen
*
* modified to halt execution
* if result address is C all fff's
* i.e. ff for fwidth=8
* by Martin Polak
*/
module sbn (clk, state, PC, a, b);
parameter fwidth = 8; // field width of sbn operand
parameter dwidth = 32;
input clk;
output [2:0] state;
output [fwidth-1:0] PC;
output [dwidth-1:0] a, b;
parameter iwidth = 4 * fwidth;
reg [iwidth-1:0] imem[0:((1<<fwidth)-1)];
reg [dwidth-1:0] dmem[0:((1<<fwidth)-1)];
reg [dwidth-1:0] X, Y;
reg [fwidth-1:0] PC;
reg [iwidth-1:0] IR;
wire [iwidth-1:0] insn;
wire [dwidth-1:0] data, asubb;
wire [fwidth-1:0] addr, PCp1, A, B, C, D;
wire altb, stp;
reg [1:0] da;
reg [2:0] state, nextstate;
parameter S0 = 3'b000;
parameter S1 = 3'b001;
parameter S2 = 3'b010;
parameter S3 = 3'b011;
parameter S4 = 3'b100;
parameter S5 = 3'b101;
parameter S6 = 3'b111;
// datapath
assign insn = imem[PC];
assign data = dmem[addr];
assign a = X; // for monitoring
assign b = Y; // for monitoring
assign asubb = X - Y;
assign altb = asubb[dwidth-1];
assign PCp1 = PC + 1;
assign A = IR[(4*fwidth-1):(3*fwidth)];
assign B = IR[(3*fwidth-1):(2*fwidth)];
assign C = IR[(2*fwidth-1):fwidth];
assign D = IR[fwidth-1:0];
assign stp = (C == ~{fwidth{1'b0}}) ? 1 : 0;
assign addr = (da == 2'b00) ? A : ((da == 2'b01) ? B : C);
always @ (posedge clk)
case (state) // action at end of state cycle
S0: begin
IR <= insn;
da <= 2'b00;
end
S1: begin
X <= data;
da <= 2'b01;
end
S2: begin
Y <= data;
da <= 2'b10;
end
S3: dmem[addr] <= asubb;
S4: PC <= D;
S5: PC <= PCp1;
S6: begin
// $display("program caused halt with value %d\n",asubb);
$finish;
end
endcase
// state register
always @ (posedge clk)
state <= nextstate;
// next state logic
always @ (state or altb or stp)
case (state)
S0: nextstate = S1;
S1: nextstate = S2;
S2: if (stp ) nextstate = S6;
else nextstate = S3;
S3: if (altb) nextstate = S4;
else nextstate = S5;
default: nextstate = S0;
endcase
initial begin
$readmemh(%PROG%, imem);
$readmemh(%DATA%, dmem);
PC = 0;
state = 0;
$monitor($time,, ",%b,%d,%d,%d,%d,%d,%d,%d,%h,%d,%d,%d",
clk, PC, X, Y, A, B, C, D, insn, addr, asubb, PCp1);
end // initial begin
endmodule
module top;
parameter fwidth = 8; // field width of sbn operand
parameter dwidth = 32;
parameter maximum = 5000;
parameter maxmone = maximum - 1;
parameter step = 10;
reg clk;
wire [2:0] state;
wire [fwidth-1:0] pc;
wire [dwidth-1:0] a, b;
sbn #(fwidth,dwidth) mach1 (clk, state, pc, a, b);
initial begin
$display("=== start ===");
clk = 0;
#maxmone $display("=== end ===");
#1 $finish;
end
always
#step clk = ~clk;
endmodule
|
module konamiacceptor (
clk,
reset_,
up_,
down_,
left_,
right_,
segment_,
digit_enable_
);
input clk;
input reset_;
input up_;
input down_;
input left_;
input right_;
output [6:0] segment_;
output [3:0] digit_enable_;
// Konami code acceptor states
parameter START = 4'd0; // Initial state; waiting for first input
parameter UP_1 = 4'd1; // User pressed (and released) d-pad up
parameter UP_2 = 4'd2;
parameter DOWN_1 = 4'd3;
parameter DOWN_2 = 4'd4;
parameter LEFT_1 = 4'd5;
parameter RIGHT_1 = 4'd6;
parameter LEFT_2 = 4'd7;
parameter ACCEPT = 4'd9; // Input sequence accepted; user gets 40 lives
parameter REJECT = 4'd10; // Input sequence rejected; user gets 3 lives
reg [3:0] state; // FSM state value (one of the above values)
reg [24:0] timeout_ctr; // If no input for a while, then we REJECT
reg [1:0] down_shift; // Down key shift register to capture key-press events
reg [1:0] up_shift;
reg [1:0] left_shift;
reg [1:0] right_shift;
wire down_debounced; // Debounced d-pad down
wire up_debounced; // Debounced d-pad up
wire left_debounced; // Debounced d-pad left
wire right_debounced; // Debounced d-pad right
wire [6:0] digit_0; // 7-segment digit values
wire [6:0] digit_1;
wire [6:0] digit_2;
wire [6:0] digit_3;
assign timeout = &timeout_ctr; // Same as timeout_ctr == 8'hff_ffff
// Key-up event when key was down (1) now is up (0)
assign down_released = down_shift == 2'b10;
assign up_released = up_shift == 2'b10;
assign left_released = left_shift == 2'b10;
assign right_released = right_shift == 2'b10;
// Debouncers for d-pad inputs (prevents microscopic changes to key values
// from causing errors--see notes)
debouncer down_debouncer(
.clk(clk),
.reset_(reset_),
.raw(~down_),
.debounced(down_debounced)
);
debouncer up_debouncer(
.clk(clk),
.reset_(reset_),
.raw(~up_),
.debounced(up_debounced)
);
debouncer left_debouncer(
.clk(clk),
.reset_(reset_),
.raw(~left_),
.debounced(left_debounced)
);
debouncer right_debouncer(
.clk(clk),
.reset_(reset_),
.raw(~right_),
.debounced(right_debounced)
);
// Digit coder converts state to a 7-segment displayed value
konamicoder coder (
.digit_0(digit_3),
.digit_1(digit_2),
.digit_2(digit_1),
.digit_3(digit_0),
.state(state)
);
// Drives the seven segment display with digit values (see notes)
displaydriver display (
.clk(clk),
.reset_(reset_),
.digit_0(digit_0),
.digit_1(digit_1),
.digit_2(digit_2),
.digit_3(digit_3),
.segment_(segment_),
.digit_enable_(digit_enable_)
);
// Timeout counter generation; REJECT on timout
always@ (posedge clk or negedge reset_)
if (!reset_)
timeout_ctr <= 25'd0;
else if (up_released || down_released || left_released || right_released)
timeout_ctr <= 25'd0;
else
timeout_ctr <= timeout_ctr + 25'd1;
// Down key shift register (for key press event generation)
always@ (posedge clk or negedge reset_)
if (!reset_)
down_shift <= 2'd0;
else
down_shift <= {down_shift[0], down_debounced};
// Up key shift register (for key press event generation)
always@ (posedge clk or negedge reset_)
if (!reset_)
up_shift <= 2'd0;
else
up_shift <= {up_shift[0], up_debounced};
// Left key shift register (for key press event generation)
always@ (posedge clk or negedge reset_)
if (!reset_)
left_shift <= 2'd0;
else
left_shift <= {left_shift[0], left_debounced};
// Right key shift register (for key press event generation)
always@ (posedge clk or negedge reset_)
if (!reset_)
right_shift <= 2'd0;
else
right_shift <= {right_shift[0], right_debounced};
// State transition register
always@ (posedge clk or negedge reset_)
if (!reset_)
state <= START;
// Initial state; wait for user to press UP
else if (state == START && up_released)
state <= UP_1;
// Up pressed once; wait for user to press up again
else if (state == UP_1 && up_released)
state <= UP_2;
else if (state == UP_1 && (timeout || down_released || left_released || right_released))
state <= REJECT;
// Up pressed twice; wait for user to press down
else if (state == UP_2 && down_released)
state <= DOWN_1;
else if (state == UP_2 && (timeout || up_released || left_released || right_released))
state <= REJECT;
// Down pressed once; wait for user to press down again
else if (state == DOWN_1 && down_released)
state <= DOWN_2;
else if (state == DOWN_1 && (timeout || up_released || left_released || right_released))
state <= REJECT;
// Down pressed twice; wait for user to press left
else if (state == DOWN_2 && left_released)
state <= LEFT_1;
else if (state == DOWN_2 && (timeout || up_released || down_released || right_released))
state <= REJECT;
// Left pressed once; wait for user to press right
else if (state == LEFT_1 && right_released)
state <= RIGHT_1;
else if (state == LEFT_1 && (timeout || left_released || up_released || down_released))
state <= REJECT;
// Right pressed once; wait for user to press left
else if (state == RIGHT_1 && left_released)
state <= LEFT_2;
else if (state == RIGHT_1 && (timeout || up_released || down_released || right_released))
state <= REJECT;
// Left pressed again; wait for user to press right again
else if (state == LEFT_2 && right_released)
state <= ACCEPT;
else if (state == LEFT_2 && (timeout || up_released || down_released || left_released))
state <= REJECT;
// In the ACCEPT or REJECT state; wait for user to press any direction, then return to start
else if ((state == ACCEPT || state == REJECT) && (up_released || down_released || left_released || right_released))
state <= START;
endmodule
|
// system_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.0 145
`timescale 1 ps / 1 ps
module system_mm_interconnect_0 (
input wire pll_0_outclk0_clk, // pll_0_outclk0.clk
input wire nios2_gen2_0_reset_reset_bridge_in_reset_reset, // nios2_gen2_0_reset_reset_bridge_in_reset.reset
input wire [26:0] nios2_gen2_0_data_master_address, // nios2_gen2_0_data_master.address
output wire nios2_gen2_0_data_master_waitrequest, // .waitrequest
input wire [3:0] nios2_gen2_0_data_master_byteenable, // .byteenable
input wire nios2_gen2_0_data_master_read, // .read
output wire [31:0] nios2_gen2_0_data_master_readdata, // .readdata
output wire nios2_gen2_0_data_master_readdatavalid, // .readdatavalid
input wire nios2_gen2_0_data_master_write, // .write
input wire [31:0] nios2_gen2_0_data_master_writedata, // .writedata
input wire nios2_gen2_0_data_master_debugaccess, // .debugaccess
input wire [16:0] nios2_gen2_0_instruction_master_address, // nios2_gen2_0_instruction_master.address
output wire nios2_gen2_0_instruction_master_waitrequest, // .waitrequest
input wire nios2_gen2_0_instruction_master_read, // .read
output wire [31:0] nios2_gen2_0_instruction_master_readdata, // .readdata
output wire nios2_gen2_0_instruction_master_readdatavalid, // .readdatavalid
output wire [0:0] jtag_uart_0_avalon_jtag_slave_address, // jtag_uart_0_avalon_jtag_slave.address
output wire jtag_uart_0_avalon_jtag_slave_write, // .write
output wire jtag_uart_0_avalon_jtag_slave_read, // .read
input wire [31:0] jtag_uart_0_avalon_jtag_slave_readdata, // .readdata
output wire [31:0] jtag_uart_0_avalon_jtag_slave_writedata, // .writedata
input wire jtag_uart_0_avalon_jtag_slave_waitrequest, // .waitrequest
output wire jtag_uart_0_avalon_jtag_slave_chipselect, // .chipselect
output wire [24:0] new_sdram_controller_0_s1_address, // new_sdram_controller_0_s1.address
output wire new_sdram_controller_0_s1_write, // .write
output wire new_sdram_controller_0_s1_read, // .read
input wire [15:0] new_sdram_controller_0_s1_readdata, // .readdata
output wire [15:0] new_sdram_controller_0_s1_writedata, // .writedata
output wire [1:0] new_sdram_controller_0_s1_byteenable, // .byteenable
input wire new_sdram_controller_0_s1_readdatavalid, // .readdatavalid
input wire new_sdram_controller_0_s1_waitrequest, // .waitrequest
output wire new_sdram_controller_0_s1_chipselect, // .chipselect
output wire [8:0] nios2_gen2_0_debug_mem_slave_address, // nios2_gen2_0_debug_mem_slave.address
output wire nios2_gen2_0_debug_mem_slave_write, // .write
output wire nios2_gen2_0_debug_mem_slave_read, // .read
input wire [31:0] nios2_gen2_0_debug_mem_slave_readdata, // .readdata
output wire [31:0] nios2_gen2_0_debug_mem_slave_writedata, // .writedata
output wire [3:0] nios2_gen2_0_debug_mem_slave_byteenable, // .byteenable
input wire nios2_gen2_0_debug_mem_slave_waitrequest, // .waitrequest
output wire nios2_gen2_0_debug_mem_slave_debugaccess, // .debugaccess
output wire [13:0] onchip_memory2_0_s1_address, // onchip_memory2_0_s1.address
output wire onchip_memory2_0_s1_write, // .write
input wire [31:0] onchip_memory2_0_s1_readdata, // .readdata
output wire [31:0] onchip_memory2_0_s1_writedata, // .writedata
output wire [3:0] onchip_memory2_0_s1_byteenable, // .byteenable
output wire onchip_memory2_0_s1_chipselect, // .chipselect
output wire onchip_memory2_0_s1_clken // .clken
);
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_waitrequest; // nios2_gen2_0_data_master_agent:av_waitrequest -> nios2_gen2_0_data_master_translator:uav_waitrequest
wire [31:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdata; // nios2_gen2_0_data_master_agent:av_readdata -> nios2_gen2_0_data_master_translator:uav_readdata
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_debugaccess; // nios2_gen2_0_data_master_translator:uav_debugaccess -> nios2_gen2_0_data_master_agent:av_debugaccess
wire [26:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_address; // nios2_gen2_0_data_master_translator:uav_address -> nios2_gen2_0_data_master_agent:av_address
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_read; // nios2_gen2_0_data_master_translator:uav_read -> nios2_gen2_0_data_master_agent:av_read
wire [3:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_byteenable; // nios2_gen2_0_data_master_translator:uav_byteenable -> nios2_gen2_0_data_master_agent:av_byteenable
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdatavalid; // nios2_gen2_0_data_master_agent:av_readdatavalid -> nios2_gen2_0_data_master_translator:uav_readdatavalid
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_lock; // nios2_gen2_0_data_master_translator:uav_lock -> nios2_gen2_0_data_master_agent:av_lock
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_write; // nios2_gen2_0_data_master_translator:uav_write -> nios2_gen2_0_data_master_agent:av_write
wire [31:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_writedata; // nios2_gen2_0_data_master_translator:uav_writedata -> nios2_gen2_0_data_master_agent:av_writedata
wire [2:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_burstcount; // nios2_gen2_0_data_master_translator:uav_burstcount -> nios2_gen2_0_data_master_agent:av_burstcount
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_waitrequest; // nios2_gen2_0_instruction_master_agent:av_waitrequest -> nios2_gen2_0_instruction_master_translator:uav_waitrequest
wire [31:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdata; // nios2_gen2_0_instruction_master_agent:av_readdata -> nios2_gen2_0_instruction_master_translator:uav_readdata
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_debugaccess; // nios2_gen2_0_instruction_master_translator:uav_debugaccess -> nios2_gen2_0_instruction_master_agent:av_debugaccess
wire [26:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_address; // nios2_gen2_0_instruction_master_translator:uav_address -> nios2_gen2_0_instruction_master_agent:av_address
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_read; // nios2_gen2_0_instruction_master_translator:uav_read -> nios2_gen2_0_instruction_master_agent:av_read
wire [3:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_byteenable; // nios2_gen2_0_instruction_master_translator:uav_byteenable -> nios2_gen2_0_instruction_master_agent:av_byteenable
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdatavalid; // nios2_gen2_0_instruction_master_agent:av_readdatavalid -> nios2_gen2_0_instruction_master_translator:uav_readdatavalid
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_lock; // nios2_gen2_0_instruction_master_translator:uav_lock -> nios2_gen2_0_instruction_master_agent:av_lock
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_write; // nios2_gen2_0_instruction_master_translator:uav_write -> nios2_gen2_0_instruction_master_agent:av_write
wire [31:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_writedata; // nios2_gen2_0_instruction_master_translator:uav_writedata -> nios2_gen2_0_instruction_master_agent:av_writedata
wire [2:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_burstcount; // nios2_gen2_0_instruction_master_translator:uav_burstcount -> nios2_gen2_0_instruction_master_agent:av_burstcount
wire [31:0] jtag_uart_0_avalon_jtag_slave_agent_m0_readdata; // jtag_uart_0_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_0_avalon_jtag_slave_agent:m0_readdata
wire jtag_uart_0_avalon_jtag_slave_agent_m0_waitrequest; // jtag_uart_0_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_0_avalon_jtag_slave_agent:m0_waitrequest
wire jtag_uart_0_avalon_jtag_slave_agent_m0_debugaccess; // jtag_uart_0_avalon_jtag_slave_agent:m0_debugaccess -> jtag_uart_0_avalon_jtag_slave_translator:uav_debugaccess
wire [26:0] jtag_uart_0_avalon_jtag_slave_agent_m0_address; // jtag_uart_0_avalon_jtag_slave_agent:m0_address -> jtag_uart_0_avalon_jtag_slave_translator:uav_address
wire [3:0] jtag_uart_0_avalon_jtag_slave_agent_m0_byteenable; // jtag_uart_0_avalon_jtag_slave_agent:m0_byteenable -> jtag_uart_0_avalon_jtag_slave_translator:uav_byteenable
wire jtag_uart_0_avalon_jtag_slave_agent_m0_read; // jtag_uart_0_avalon_jtag_slave_agent:m0_read -> jtag_uart_0_avalon_jtag_slave_translator:uav_read
wire jtag_uart_0_avalon_jtag_slave_agent_m0_readdatavalid; // jtag_uart_0_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_0_avalon_jtag_slave_agent:m0_readdatavalid
wire jtag_uart_0_avalon_jtag_slave_agent_m0_lock; // jtag_uart_0_avalon_jtag_slave_agent:m0_lock -> jtag_uart_0_avalon_jtag_slave_translator:uav_lock
wire [31:0] jtag_uart_0_avalon_jtag_slave_agent_m0_writedata; // jtag_uart_0_avalon_jtag_slave_agent:m0_writedata -> jtag_uart_0_avalon_jtag_slave_translator:uav_writedata
wire jtag_uart_0_avalon_jtag_slave_agent_m0_write; // jtag_uart_0_avalon_jtag_slave_agent:m0_write -> jtag_uart_0_avalon_jtag_slave_translator:uav_write
wire [2:0] jtag_uart_0_avalon_jtag_slave_agent_m0_burstcount; // jtag_uart_0_avalon_jtag_slave_agent:m0_burstcount -> jtag_uart_0_avalon_jtag_slave_translator:uav_burstcount
wire jtag_uart_0_avalon_jtag_slave_agent_rf_source_valid; // jtag_uart_0_avalon_jtag_slave_agent:rf_source_valid -> jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:in_valid
wire [101:0] jtag_uart_0_avalon_jtag_slave_agent_rf_source_data; // jtag_uart_0_avalon_jtag_slave_agent:rf_source_data -> jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:in_data
wire jtag_uart_0_avalon_jtag_slave_agent_rf_source_ready; // jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:in_ready -> jtag_uart_0_avalon_jtag_slave_agent:rf_source_ready
wire jtag_uart_0_avalon_jtag_slave_agent_rf_source_startofpacket; // jtag_uart_0_avalon_jtag_slave_agent:rf_source_startofpacket -> jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:in_startofpacket
wire jtag_uart_0_avalon_jtag_slave_agent_rf_source_endofpacket; // jtag_uart_0_avalon_jtag_slave_agent:rf_source_endofpacket -> jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:in_endofpacket
wire jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_valid; // jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:out_valid -> jtag_uart_0_avalon_jtag_slave_agent:rf_sink_valid
wire [101:0] jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_data; // jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:out_data -> jtag_uart_0_avalon_jtag_slave_agent:rf_sink_data
wire jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_ready; // jtag_uart_0_avalon_jtag_slave_agent:rf_sink_ready -> jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:out_ready
wire jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket; // jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:out_startofpacket -> jtag_uart_0_avalon_jtag_slave_agent:rf_sink_startofpacket
wire jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket; // jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:out_endofpacket -> jtag_uart_0_avalon_jtag_slave_agent:rf_sink_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> jtag_uart_0_avalon_jtag_slave_agent:cp_valid
wire [100:0] cmd_mux_src_data; // cmd_mux:src_data -> jtag_uart_0_avalon_jtag_slave_agent:cp_data
wire cmd_mux_src_ready; // jtag_uart_0_avalon_jtag_slave_agent:cp_ready -> cmd_mux:src_ready
wire [3:0] cmd_mux_src_channel; // cmd_mux:src_channel -> jtag_uart_0_avalon_jtag_slave_agent:cp_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> jtag_uart_0_avalon_jtag_slave_agent:cp_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> jtag_uart_0_avalon_jtag_slave_agent:cp_endofpacket
wire [31:0] nios2_gen2_0_debug_mem_slave_agent_m0_readdata; // nios2_gen2_0_debug_mem_slave_translator:uav_readdata -> nios2_gen2_0_debug_mem_slave_agent:m0_readdata
wire nios2_gen2_0_debug_mem_slave_agent_m0_waitrequest; // nios2_gen2_0_debug_mem_slave_translator:uav_waitrequest -> nios2_gen2_0_debug_mem_slave_agent:m0_waitrequest
wire nios2_gen2_0_debug_mem_slave_agent_m0_debugaccess; // nios2_gen2_0_debug_mem_slave_agent:m0_debugaccess -> nios2_gen2_0_debug_mem_slave_translator:uav_debugaccess
wire [26:0] nios2_gen2_0_debug_mem_slave_agent_m0_address; // nios2_gen2_0_debug_mem_slave_agent:m0_address -> nios2_gen2_0_debug_mem_slave_translator:uav_address
wire [3:0] nios2_gen2_0_debug_mem_slave_agent_m0_byteenable; // nios2_gen2_0_debug_mem_slave_agent:m0_byteenable -> nios2_gen2_0_debug_mem_slave_translator:uav_byteenable
wire nios2_gen2_0_debug_mem_slave_agent_m0_read; // nios2_gen2_0_debug_mem_slave_agent:m0_read -> nios2_gen2_0_debug_mem_slave_translator:uav_read
wire nios2_gen2_0_debug_mem_slave_agent_m0_readdatavalid; // nios2_gen2_0_debug_mem_slave_translator:uav_readdatavalid -> nios2_gen2_0_debug_mem_slave_agent:m0_readdatavalid
wire nios2_gen2_0_debug_mem_slave_agent_m0_lock; // nios2_gen2_0_debug_mem_slave_agent:m0_lock -> nios2_gen2_0_debug_mem_slave_translator:uav_lock
wire [31:0] nios2_gen2_0_debug_mem_slave_agent_m0_writedata; // nios2_gen2_0_debug_mem_slave_agent:m0_writedata -> nios2_gen2_0_debug_mem_slave_translator:uav_writedata
wire nios2_gen2_0_debug_mem_slave_agent_m0_write; // nios2_gen2_0_debug_mem_slave_agent:m0_write -> nios2_gen2_0_debug_mem_slave_translator:uav_write
wire [2:0] nios2_gen2_0_debug_mem_slave_agent_m0_burstcount; // nios2_gen2_0_debug_mem_slave_agent:m0_burstcount -> nios2_gen2_0_debug_mem_slave_translator:uav_burstcount
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_valid; // nios2_gen2_0_debug_mem_slave_agent:rf_source_valid -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_valid
wire [101:0] nios2_gen2_0_debug_mem_slave_agent_rf_source_data; // nios2_gen2_0_debug_mem_slave_agent:rf_source_data -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_data
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_ready; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_ready -> nios2_gen2_0_debug_mem_slave_agent:rf_source_ready
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_startofpacket; // nios2_gen2_0_debug_mem_slave_agent:rf_source_startofpacket -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_startofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_endofpacket; // nios2_gen2_0_debug_mem_slave_agent:rf_source_endofpacket -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_endofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_valid; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_valid -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_valid
wire [101:0] nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_data; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_data -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_data
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_ready; // nios2_gen2_0_debug_mem_slave_agent:rf_sink_ready -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_ready
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_startofpacket -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_startofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_endofpacket -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> nios2_gen2_0_debug_mem_slave_agent:cp_valid
wire [100:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> nios2_gen2_0_debug_mem_slave_agent:cp_data
wire cmd_mux_001_src_ready; // nios2_gen2_0_debug_mem_slave_agent:cp_ready -> cmd_mux_001:src_ready
wire [3:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> nios2_gen2_0_debug_mem_slave_agent:cp_channel
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> nios2_gen2_0_debug_mem_slave_agent:cp_startofpacket
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> nios2_gen2_0_debug_mem_slave_agent:cp_endofpacket
wire [31:0] onchip_memory2_0_s1_agent_m0_readdata; // onchip_memory2_0_s1_translator:uav_readdata -> onchip_memory2_0_s1_agent:m0_readdata
wire onchip_memory2_0_s1_agent_m0_waitrequest; // onchip_memory2_0_s1_translator:uav_waitrequest -> onchip_memory2_0_s1_agent:m0_waitrequest
wire onchip_memory2_0_s1_agent_m0_debugaccess; // onchip_memory2_0_s1_agent:m0_debugaccess -> onchip_memory2_0_s1_translator:uav_debugaccess
wire [26:0] onchip_memory2_0_s1_agent_m0_address; // onchip_memory2_0_s1_agent:m0_address -> onchip_memory2_0_s1_translator:uav_address
wire [3:0] onchip_memory2_0_s1_agent_m0_byteenable; // onchip_memory2_0_s1_agent:m0_byteenable -> onchip_memory2_0_s1_translator:uav_byteenable
wire onchip_memory2_0_s1_agent_m0_read; // onchip_memory2_0_s1_agent:m0_read -> onchip_memory2_0_s1_translator:uav_read
wire onchip_memory2_0_s1_agent_m0_readdatavalid; // onchip_memory2_0_s1_translator:uav_readdatavalid -> onchip_memory2_0_s1_agent:m0_readdatavalid
wire onchip_memory2_0_s1_agent_m0_lock; // onchip_memory2_0_s1_agent:m0_lock -> onchip_memory2_0_s1_translator:uav_lock
wire [31:0] onchip_memory2_0_s1_agent_m0_writedata; // onchip_memory2_0_s1_agent:m0_writedata -> onchip_memory2_0_s1_translator:uav_writedata
wire onchip_memory2_0_s1_agent_m0_write; // onchip_memory2_0_s1_agent:m0_write -> onchip_memory2_0_s1_translator:uav_write
wire [2:0] onchip_memory2_0_s1_agent_m0_burstcount; // onchip_memory2_0_s1_agent:m0_burstcount -> onchip_memory2_0_s1_translator:uav_burstcount
wire onchip_memory2_0_s1_agent_rf_source_valid; // onchip_memory2_0_s1_agent:rf_source_valid -> onchip_memory2_0_s1_agent_rsp_fifo:in_valid
wire [101:0] onchip_memory2_0_s1_agent_rf_source_data; // onchip_memory2_0_s1_agent:rf_source_data -> onchip_memory2_0_s1_agent_rsp_fifo:in_data
wire onchip_memory2_0_s1_agent_rf_source_ready; // onchip_memory2_0_s1_agent_rsp_fifo:in_ready -> onchip_memory2_0_s1_agent:rf_source_ready
wire onchip_memory2_0_s1_agent_rf_source_startofpacket; // onchip_memory2_0_s1_agent:rf_source_startofpacket -> onchip_memory2_0_s1_agent_rsp_fifo:in_startofpacket
wire onchip_memory2_0_s1_agent_rf_source_endofpacket; // onchip_memory2_0_s1_agent:rf_source_endofpacket -> onchip_memory2_0_s1_agent_rsp_fifo:in_endofpacket
wire onchip_memory2_0_s1_agent_rsp_fifo_out_valid; // onchip_memory2_0_s1_agent_rsp_fifo:out_valid -> onchip_memory2_0_s1_agent:rf_sink_valid
wire [101:0] onchip_memory2_0_s1_agent_rsp_fifo_out_data; // onchip_memory2_0_s1_agent_rsp_fifo:out_data -> onchip_memory2_0_s1_agent:rf_sink_data
wire onchip_memory2_0_s1_agent_rsp_fifo_out_ready; // onchip_memory2_0_s1_agent:rf_sink_ready -> onchip_memory2_0_s1_agent_rsp_fifo:out_ready
wire onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket; // onchip_memory2_0_s1_agent_rsp_fifo:out_startofpacket -> onchip_memory2_0_s1_agent:rf_sink_startofpacket
wire onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket; // onchip_memory2_0_s1_agent_rsp_fifo:out_endofpacket -> onchip_memory2_0_s1_agent:rf_sink_endofpacket
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> onchip_memory2_0_s1_agent:cp_valid
wire [100:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> onchip_memory2_0_s1_agent:cp_data
wire cmd_mux_002_src_ready; // onchip_memory2_0_s1_agent:cp_ready -> cmd_mux_002:src_ready
wire [3:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> onchip_memory2_0_s1_agent:cp_channel
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> onchip_memory2_0_s1_agent:cp_startofpacket
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> onchip_memory2_0_s1_agent:cp_endofpacket
wire [15:0] new_sdram_controller_0_s1_agent_m0_readdata; // new_sdram_controller_0_s1_translator:uav_readdata -> new_sdram_controller_0_s1_agent:m0_readdata
wire new_sdram_controller_0_s1_agent_m0_waitrequest; // new_sdram_controller_0_s1_translator:uav_waitrequest -> new_sdram_controller_0_s1_agent:m0_waitrequest
wire new_sdram_controller_0_s1_agent_m0_debugaccess; // new_sdram_controller_0_s1_agent:m0_debugaccess -> new_sdram_controller_0_s1_translator:uav_debugaccess
wire [26:0] new_sdram_controller_0_s1_agent_m0_address; // new_sdram_controller_0_s1_agent:m0_address -> new_sdram_controller_0_s1_translator:uav_address
wire [1:0] new_sdram_controller_0_s1_agent_m0_byteenable; // new_sdram_controller_0_s1_agent:m0_byteenable -> new_sdram_controller_0_s1_translator:uav_byteenable
wire new_sdram_controller_0_s1_agent_m0_read; // new_sdram_controller_0_s1_agent:m0_read -> new_sdram_controller_0_s1_translator:uav_read
wire new_sdram_controller_0_s1_agent_m0_readdatavalid; // new_sdram_controller_0_s1_translator:uav_readdatavalid -> new_sdram_controller_0_s1_agent:m0_readdatavalid
wire new_sdram_controller_0_s1_agent_m0_lock; // new_sdram_controller_0_s1_agent:m0_lock -> new_sdram_controller_0_s1_translator:uav_lock
wire [15:0] new_sdram_controller_0_s1_agent_m0_writedata; // new_sdram_controller_0_s1_agent:m0_writedata -> new_sdram_controller_0_s1_translator:uav_writedata
wire new_sdram_controller_0_s1_agent_m0_write; // new_sdram_controller_0_s1_agent:m0_write -> new_sdram_controller_0_s1_translator:uav_write
wire [1:0] new_sdram_controller_0_s1_agent_m0_burstcount; // new_sdram_controller_0_s1_agent:m0_burstcount -> new_sdram_controller_0_s1_translator:uav_burstcount
wire new_sdram_controller_0_s1_agent_rf_source_valid; // new_sdram_controller_0_s1_agent:rf_source_valid -> new_sdram_controller_0_s1_agent_rsp_fifo:in_valid
wire [83:0] new_sdram_controller_0_s1_agent_rf_source_data; // new_sdram_controller_0_s1_agent:rf_source_data -> new_sdram_controller_0_s1_agent_rsp_fifo:in_data
wire new_sdram_controller_0_s1_agent_rf_source_ready; // new_sdram_controller_0_s1_agent_rsp_fifo:in_ready -> new_sdram_controller_0_s1_agent:rf_source_ready
wire new_sdram_controller_0_s1_agent_rf_source_startofpacket; // new_sdram_controller_0_s1_agent:rf_source_startofpacket -> new_sdram_controller_0_s1_agent_rsp_fifo:in_startofpacket
wire new_sdram_controller_0_s1_agent_rf_source_endofpacket; // new_sdram_controller_0_s1_agent:rf_source_endofpacket -> new_sdram_controller_0_s1_agent_rsp_fifo:in_endofpacket
wire new_sdram_controller_0_s1_agent_rsp_fifo_out_valid; // new_sdram_controller_0_s1_agent_rsp_fifo:out_valid -> new_sdram_controller_0_s1_agent:rf_sink_valid
wire [83:0] new_sdram_controller_0_s1_agent_rsp_fifo_out_data; // new_sdram_controller_0_s1_agent_rsp_fifo:out_data -> new_sdram_controller_0_s1_agent:rf_sink_data
wire new_sdram_controller_0_s1_agent_rsp_fifo_out_ready; // new_sdram_controller_0_s1_agent:rf_sink_ready -> new_sdram_controller_0_s1_agent_rsp_fifo:out_ready
wire new_sdram_controller_0_s1_agent_rsp_fifo_out_startofpacket; // new_sdram_controller_0_s1_agent_rsp_fifo:out_startofpacket -> new_sdram_controller_0_s1_agent:rf_sink_startofpacket
wire new_sdram_controller_0_s1_agent_rsp_fifo_out_endofpacket; // new_sdram_controller_0_s1_agent_rsp_fifo:out_endofpacket -> new_sdram_controller_0_s1_agent:rf_sink_endofpacket
wire new_sdram_controller_0_s1_agent_rdata_fifo_src_valid; // new_sdram_controller_0_s1_agent:rdata_fifo_src_valid -> new_sdram_controller_0_s1_agent_rdata_fifo:in_valid
wire [17:0] new_sdram_controller_0_s1_agent_rdata_fifo_src_data; // new_sdram_controller_0_s1_agent:rdata_fifo_src_data -> new_sdram_controller_0_s1_agent_rdata_fifo:in_data
wire new_sdram_controller_0_s1_agent_rdata_fifo_src_ready; // new_sdram_controller_0_s1_agent_rdata_fifo:in_ready -> new_sdram_controller_0_s1_agent:rdata_fifo_src_ready
wire nios2_gen2_0_data_master_agent_cp_valid; // nios2_gen2_0_data_master_agent:cp_valid -> router:sink_valid
wire [100:0] nios2_gen2_0_data_master_agent_cp_data; // nios2_gen2_0_data_master_agent:cp_data -> router:sink_data
wire nios2_gen2_0_data_master_agent_cp_ready; // router:sink_ready -> nios2_gen2_0_data_master_agent:cp_ready
wire nios2_gen2_0_data_master_agent_cp_startofpacket; // nios2_gen2_0_data_master_agent:cp_startofpacket -> router:sink_startofpacket
wire nios2_gen2_0_data_master_agent_cp_endofpacket; // nios2_gen2_0_data_master_agent:cp_endofpacket -> router:sink_endofpacket
wire nios2_gen2_0_instruction_master_agent_cp_valid; // nios2_gen2_0_instruction_master_agent:cp_valid -> router_001:sink_valid
wire [100:0] nios2_gen2_0_instruction_master_agent_cp_data; // nios2_gen2_0_instruction_master_agent:cp_data -> router_001:sink_data
wire nios2_gen2_0_instruction_master_agent_cp_ready; // router_001:sink_ready -> nios2_gen2_0_instruction_master_agent:cp_ready
wire nios2_gen2_0_instruction_master_agent_cp_startofpacket; // nios2_gen2_0_instruction_master_agent:cp_startofpacket -> router_001:sink_startofpacket
wire nios2_gen2_0_instruction_master_agent_cp_endofpacket; // nios2_gen2_0_instruction_master_agent:cp_endofpacket -> router_001:sink_endofpacket
wire jtag_uart_0_avalon_jtag_slave_agent_rp_valid; // jtag_uart_0_avalon_jtag_slave_agent:rp_valid -> router_002:sink_valid
wire [100:0] jtag_uart_0_avalon_jtag_slave_agent_rp_data; // jtag_uart_0_avalon_jtag_slave_agent:rp_data -> router_002:sink_data
wire jtag_uart_0_avalon_jtag_slave_agent_rp_ready; // router_002:sink_ready -> jtag_uart_0_avalon_jtag_slave_agent:rp_ready
wire jtag_uart_0_avalon_jtag_slave_agent_rp_startofpacket; // jtag_uart_0_avalon_jtag_slave_agent:rp_startofpacket -> router_002:sink_startofpacket
wire jtag_uart_0_avalon_jtag_slave_agent_rp_endofpacket; // jtag_uart_0_avalon_jtag_slave_agent:rp_endofpacket -> router_002:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> rsp_demux:sink_valid
wire [100:0] router_002_src_data; // router_002:src_data -> rsp_demux:sink_data
wire router_002_src_ready; // rsp_demux:sink_ready -> router_002:src_ready
wire [3:0] router_002_src_channel; // router_002:src_channel -> rsp_demux:sink_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rp_valid; // nios2_gen2_0_debug_mem_slave_agent:rp_valid -> router_003:sink_valid
wire [100:0] nios2_gen2_0_debug_mem_slave_agent_rp_data; // nios2_gen2_0_debug_mem_slave_agent:rp_data -> router_003:sink_data
wire nios2_gen2_0_debug_mem_slave_agent_rp_ready; // router_003:sink_ready -> nios2_gen2_0_debug_mem_slave_agent:rp_ready
wire nios2_gen2_0_debug_mem_slave_agent_rp_startofpacket; // nios2_gen2_0_debug_mem_slave_agent:rp_startofpacket -> router_003:sink_startofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rp_endofpacket; // nios2_gen2_0_debug_mem_slave_agent:rp_endofpacket -> router_003:sink_endofpacket
wire router_003_src_valid; // router_003:src_valid -> rsp_demux_001:sink_valid
wire [100:0] router_003_src_data; // router_003:src_data -> rsp_demux_001:sink_data
wire router_003_src_ready; // rsp_demux_001:sink_ready -> router_003:src_ready
wire [3:0] router_003_src_channel; // router_003:src_channel -> rsp_demux_001:sink_channel
wire router_003_src_startofpacket; // router_003:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire router_003_src_endofpacket; // router_003:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire onchip_memory2_0_s1_agent_rp_valid; // onchip_memory2_0_s1_agent:rp_valid -> router_004:sink_valid
wire [100:0] onchip_memory2_0_s1_agent_rp_data; // onchip_memory2_0_s1_agent:rp_data -> router_004:sink_data
wire onchip_memory2_0_s1_agent_rp_ready; // router_004:sink_ready -> onchip_memory2_0_s1_agent:rp_ready
wire onchip_memory2_0_s1_agent_rp_startofpacket; // onchip_memory2_0_s1_agent:rp_startofpacket -> router_004:sink_startofpacket
wire onchip_memory2_0_s1_agent_rp_endofpacket; // onchip_memory2_0_s1_agent:rp_endofpacket -> router_004:sink_endofpacket
wire router_004_src_valid; // router_004:src_valid -> rsp_demux_002:sink_valid
wire [100:0] router_004_src_data; // router_004:src_data -> rsp_demux_002:sink_data
wire router_004_src_ready; // rsp_demux_002:sink_ready -> router_004:src_ready
wire [3:0] router_004_src_channel; // router_004:src_channel -> rsp_demux_002:sink_channel
wire router_004_src_startofpacket; // router_004:src_startofpacket -> rsp_demux_002:sink_startofpacket
wire router_004_src_endofpacket; // router_004:src_endofpacket -> rsp_demux_002:sink_endofpacket
wire new_sdram_controller_0_s1_agent_rp_valid; // new_sdram_controller_0_s1_agent:rp_valid -> router_005:sink_valid
wire [82:0] new_sdram_controller_0_s1_agent_rp_data; // new_sdram_controller_0_s1_agent:rp_data -> router_005:sink_data
wire new_sdram_controller_0_s1_agent_rp_ready; // router_005:sink_ready -> new_sdram_controller_0_s1_agent:rp_ready
wire new_sdram_controller_0_s1_agent_rp_startofpacket; // new_sdram_controller_0_s1_agent:rp_startofpacket -> router_005:sink_startofpacket
wire new_sdram_controller_0_s1_agent_rp_endofpacket; // new_sdram_controller_0_s1_agent:rp_endofpacket -> router_005:sink_endofpacket
wire router_src_valid; // router:src_valid -> nios2_gen2_0_data_master_limiter:cmd_sink_valid
wire [100:0] router_src_data; // router:src_data -> nios2_gen2_0_data_master_limiter:cmd_sink_data
wire router_src_ready; // nios2_gen2_0_data_master_limiter:cmd_sink_ready -> router:src_ready
wire [3:0] router_src_channel; // router:src_channel -> nios2_gen2_0_data_master_limiter:cmd_sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> nios2_gen2_0_data_master_limiter:cmd_sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> nios2_gen2_0_data_master_limiter:cmd_sink_endofpacket
wire [100:0] nios2_gen2_0_data_master_limiter_cmd_src_data; // nios2_gen2_0_data_master_limiter:cmd_src_data -> cmd_demux:sink_data
wire nios2_gen2_0_data_master_limiter_cmd_src_ready; // cmd_demux:sink_ready -> nios2_gen2_0_data_master_limiter:cmd_src_ready
wire [3:0] nios2_gen2_0_data_master_limiter_cmd_src_channel; // nios2_gen2_0_data_master_limiter:cmd_src_channel -> cmd_demux:sink_channel
wire nios2_gen2_0_data_master_limiter_cmd_src_startofpacket; // nios2_gen2_0_data_master_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
wire nios2_gen2_0_data_master_limiter_cmd_src_endofpacket; // nios2_gen2_0_data_master_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> nios2_gen2_0_data_master_limiter:rsp_sink_valid
wire [100:0] rsp_mux_src_data; // rsp_mux:src_data -> nios2_gen2_0_data_master_limiter:rsp_sink_data
wire rsp_mux_src_ready; // nios2_gen2_0_data_master_limiter:rsp_sink_ready -> rsp_mux:src_ready
wire [3:0] rsp_mux_src_channel; // rsp_mux:src_channel -> nios2_gen2_0_data_master_limiter:rsp_sink_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> nios2_gen2_0_data_master_limiter:rsp_sink_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> nios2_gen2_0_data_master_limiter:rsp_sink_endofpacket
wire nios2_gen2_0_data_master_limiter_rsp_src_valid; // nios2_gen2_0_data_master_limiter:rsp_src_valid -> nios2_gen2_0_data_master_agent:rp_valid
wire [100:0] nios2_gen2_0_data_master_limiter_rsp_src_data; // nios2_gen2_0_data_master_limiter:rsp_src_data -> nios2_gen2_0_data_master_agent:rp_data
wire nios2_gen2_0_data_master_limiter_rsp_src_ready; // nios2_gen2_0_data_master_agent:rp_ready -> nios2_gen2_0_data_master_limiter:rsp_src_ready
wire [3:0] nios2_gen2_0_data_master_limiter_rsp_src_channel; // nios2_gen2_0_data_master_limiter:rsp_src_channel -> nios2_gen2_0_data_master_agent:rp_channel
wire nios2_gen2_0_data_master_limiter_rsp_src_startofpacket; // nios2_gen2_0_data_master_limiter:rsp_src_startofpacket -> nios2_gen2_0_data_master_agent:rp_startofpacket
wire nios2_gen2_0_data_master_limiter_rsp_src_endofpacket; // nios2_gen2_0_data_master_limiter:rsp_src_endofpacket -> nios2_gen2_0_data_master_agent:rp_endofpacket
wire router_001_src_valid; // router_001:src_valid -> nios2_gen2_0_instruction_master_limiter:cmd_sink_valid
wire [100:0] router_001_src_data; // router_001:src_data -> nios2_gen2_0_instruction_master_limiter:cmd_sink_data
wire router_001_src_ready; // nios2_gen2_0_instruction_master_limiter:cmd_sink_ready -> router_001:src_ready
wire [3:0] router_001_src_channel; // router_001:src_channel -> nios2_gen2_0_instruction_master_limiter:cmd_sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> nios2_gen2_0_instruction_master_limiter:cmd_sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> nios2_gen2_0_instruction_master_limiter:cmd_sink_endofpacket
wire [100:0] nios2_gen2_0_instruction_master_limiter_cmd_src_data; // nios2_gen2_0_instruction_master_limiter:cmd_src_data -> cmd_demux_001:sink_data
wire nios2_gen2_0_instruction_master_limiter_cmd_src_ready; // cmd_demux_001:sink_ready -> nios2_gen2_0_instruction_master_limiter:cmd_src_ready
wire [3:0] nios2_gen2_0_instruction_master_limiter_cmd_src_channel; // nios2_gen2_0_instruction_master_limiter:cmd_src_channel -> cmd_demux_001:sink_channel
wire nios2_gen2_0_instruction_master_limiter_cmd_src_startofpacket; // nios2_gen2_0_instruction_master_limiter:cmd_src_startofpacket -> cmd_demux_001:sink_startofpacket
wire nios2_gen2_0_instruction_master_limiter_cmd_src_endofpacket; // nios2_gen2_0_instruction_master_limiter:cmd_src_endofpacket -> cmd_demux_001:sink_endofpacket
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> nios2_gen2_0_instruction_master_limiter:rsp_sink_valid
wire [100:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> nios2_gen2_0_instruction_master_limiter:rsp_sink_data
wire rsp_mux_001_src_ready; // nios2_gen2_0_instruction_master_limiter:rsp_sink_ready -> rsp_mux_001:src_ready
wire [3:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> nios2_gen2_0_instruction_master_limiter:rsp_sink_channel
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> nios2_gen2_0_instruction_master_limiter:rsp_sink_startofpacket
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> nios2_gen2_0_instruction_master_limiter:rsp_sink_endofpacket
wire nios2_gen2_0_instruction_master_limiter_rsp_src_valid; // nios2_gen2_0_instruction_master_limiter:rsp_src_valid -> nios2_gen2_0_instruction_master_agent:rp_valid
wire [100:0] nios2_gen2_0_instruction_master_limiter_rsp_src_data; // nios2_gen2_0_instruction_master_limiter:rsp_src_data -> nios2_gen2_0_instruction_master_agent:rp_data
wire nios2_gen2_0_instruction_master_limiter_rsp_src_ready; // nios2_gen2_0_instruction_master_agent:rp_ready -> nios2_gen2_0_instruction_master_limiter:rsp_src_ready
wire [3:0] nios2_gen2_0_instruction_master_limiter_rsp_src_channel; // nios2_gen2_0_instruction_master_limiter:rsp_src_channel -> nios2_gen2_0_instruction_master_agent:rp_channel
wire nios2_gen2_0_instruction_master_limiter_rsp_src_startofpacket; // nios2_gen2_0_instruction_master_limiter:rsp_src_startofpacket -> nios2_gen2_0_instruction_master_agent:rp_startofpacket
wire nios2_gen2_0_instruction_master_limiter_rsp_src_endofpacket; // nios2_gen2_0_instruction_master_limiter:rsp_src_endofpacket -> nios2_gen2_0_instruction_master_agent:rp_endofpacket
wire new_sdram_controller_0_s1_burst_adapter_source0_valid; // new_sdram_controller_0_s1_burst_adapter:source0_valid -> new_sdram_controller_0_s1_agent:cp_valid
wire [82:0] new_sdram_controller_0_s1_burst_adapter_source0_data; // new_sdram_controller_0_s1_burst_adapter:source0_data -> new_sdram_controller_0_s1_agent:cp_data
wire new_sdram_controller_0_s1_burst_adapter_source0_ready; // new_sdram_controller_0_s1_agent:cp_ready -> new_sdram_controller_0_s1_burst_adapter:source0_ready
wire [3:0] new_sdram_controller_0_s1_burst_adapter_source0_channel; // new_sdram_controller_0_s1_burst_adapter:source0_channel -> new_sdram_controller_0_s1_agent:cp_channel
wire new_sdram_controller_0_s1_burst_adapter_source0_startofpacket; // new_sdram_controller_0_s1_burst_adapter:source0_startofpacket -> new_sdram_controller_0_s1_agent:cp_startofpacket
wire new_sdram_controller_0_s1_burst_adapter_source0_endofpacket; // new_sdram_controller_0_s1_burst_adapter:source0_endofpacket -> new_sdram_controller_0_s1_agent:cp_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [100:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [3:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
wire [100:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data
wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
wire [3:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire cmd_demux_src2_valid; // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
wire [100:0] cmd_demux_src2_data; // cmd_demux:src2_data -> cmd_mux_002:sink0_data
wire cmd_demux_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
wire [3:0] cmd_demux_src2_channel; // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_src2_startofpacket; // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire cmd_demux_src2_endofpacket; // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_src3_valid; // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
wire [100:0] cmd_demux_src3_data; // cmd_demux:src3_data -> cmd_mux_003:sink0_data
wire cmd_demux_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
wire [3:0] cmd_demux_src3_channel; // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_src3_startofpacket; // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire cmd_demux_src3_endofpacket; // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux_001:sink1_valid
wire [100:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux_001:sink1_data
wire cmd_demux_001_src0_ready; // cmd_mux_001:sink1_ready -> cmd_demux_001:src0_ready
wire [3:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux_001:sink1_channel
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux_001:sink1_startofpacket
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux_001:sink1_endofpacket
wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> cmd_mux_002:sink1_valid
wire [100:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> cmd_mux_002:sink1_data
wire cmd_demux_001_src1_ready; // cmd_mux_002:sink1_ready -> cmd_demux_001:src1_ready
wire [3:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> cmd_mux_002:sink1_channel
wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> cmd_mux_002:sink1_startofpacket
wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> cmd_mux_002:sink1_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [100:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [3:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
wire [100:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data
wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
wire [3:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
wire rsp_demux_001_src1_valid; // rsp_demux_001:src1_valid -> rsp_mux_001:sink0_valid
wire [100:0] rsp_demux_001_src1_data; // rsp_demux_001:src1_data -> rsp_mux_001:sink0_data
wire rsp_demux_001_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux_001:src1_ready
wire [3:0] rsp_demux_001_src1_channel; // rsp_demux_001:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_001_src1_startofpacket; // rsp_demux_001:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire rsp_demux_001_src1_endofpacket; // rsp_demux_001:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
wire [100:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux:sink2_data
wire rsp_demux_002_src0_ready; // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
wire [3:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
wire rsp_demux_002_src1_valid; // rsp_demux_002:src1_valid -> rsp_mux_001:sink1_valid
wire [100:0] rsp_demux_002_src1_data; // rsp_demux_002:src1_data -> rsp_mux_001:sink1_data
wire rsp_demux_002_src1_ready; // rsp_mux_001:sink1_ready -> rsp_demux_002:src1_ready
wire [3:0] rsp_demux_002_src1_channel; // rsp_demux_002:src1_channel -> rsp_mux_001:sink1_channel
wire rsp_demux_002_src1_startofpacket; // rsp_demux_002:src1_startofpacket -> rsp_mux_001:sink1_startofpacket
wire rsp_demux_002_src1_endofpacket; // rsp_demux_002:src1_endofpacket -> rsp_mux_001:sink1_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
wire [100:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux:sink3_data
wire rsp_demux_003_src0_ready; // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
wire [3:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
wire router_005_src_valid; // router_005:src_valid -> new_sdram_controller_0_s1_rsp_width_adapter:in_valid
wire [82:0] router_005_src_data; // router_005:src_data -> new_sdram_controller_0_s1_rsp_width_adapter:in_data
wire router_005_src_ready; // new_sdram_controller_0_s1_rsp_width_adapter:in_ready -> router_005:src_ready
wire [3:0] router_005_src_channel; // router_005:src_channel -> new_sdram_controller_0_s1_rsp_width_adapter:in_channel
wire router_005_src_startofpacket; // router_005:src_startofpacket -> new_sdram_controller_0_s1_rsp_width_adapter:in_startofpacket
wire router_005_src_endofpacket; // router_005:src_endofpacket -> new_sdram_controller_0_s1_rsp_width_adapter:in_endofpacket
wire new_sdram_controller_0_s1_rsp_width_adapter_src_valid; // new_sdram_controller_0_s1_rsp_width_adapter:out_valid -> rsp_demux_003:sink_valid
wire [100:0] new_sdram_controller_0_s1_rsp_width_adapter_src_data; // new_sdram_controller_0_s1_rsp_width_adapter:out_data -> rsp_demux_003:sink_data
wire new_sdram_controller_0_s1_rsp_width_adapter_src_ready; // rsp_demux_003:sink_ready -> new_sdram_controller_0_s1_rsp_width_adapter:out_ready
wire [3:0] new_sdram_controller_0_s1_rsp_width_adapter_src_channel; // new_sdram_controller_0_s1_rsp_width_adapter:out_channel -> rsp_demux_003:sink_channel
wire new_sdram_controller_0_s1_rsp_width_adapter_src_startofpacket; // new_sdram_controller_0_s1_rsp_width_adapter:out_startofpacket -> rsp_demux_003:sink_startofpacket
wire new_sdram_controller_0_s1_rsp_width_adapter_src_endofpacket; // new_sdram_controller_0_s1_rsp_width_adapter:out_endofpacket -> rsp_demux_003:sink_endofpacket
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> new_sdram_controller_0_s1_cmd_width_adapter:in_valid
wire [100:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> new_sdram_controller_0_s1_cmd_width_adapter:in_data
wire cmd_mux_003_src_ready; // new_sdram_controller_0_s1_cmd_width_adapter:in_ready -> cmd_mux_003:src_ready
wire [3:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> new_sdram_controller_0_s1_cmd_width_adapter:in_channel
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> new_sdram_controller_0_s1_cmd_width_adapter:in_startofpacket
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> new_sdram_controller_0_s1_cmd_width_adapter:in_endofpacket
wire new_sdram_controller_0_s1_cmd_width_adapter_src_valid; // new_sdram_controller_0_s1_cmd_width_adapter:out_valid -> new_sdram_controller_0_s1_burst_adapter:sink0_valid
wire [82:0] new_sdram_controller_0_s1_cmd_width_adapter_src_data; // new_sdram_controller_0_s1_cmd_width_adapter:out_data -> new_sdram_controller_0_s1_burst_adapter:sink0_data
wire new_sdram_controller_0_s1_cmd_width_adapter_src_ready; // new_sdram_controller_0_s1_burst_adapter:sink0_ready -> new_sdram_controller_0_s1_cmd_width_adapter:out_ready
wire [3:0] new_sdram_controller_0_s1_cmd_width_adapter_src_channel; // new_sdram_controller_0_s1_cmd_width_adapter:out_channel -> new_sdram_controller_0_s1_burst_adapter:sink0_channel
wire new_sdram_controller_0_s1_cmd_width_adapter_src_startofpacket; // new_sdram_controller_0_s1_cmd_width_adapter:out_startofpacket -> new_sdram_controller_0_s1_burst_adapter:sink0_startofpacket
wire new_sdram_controller_0_s1_cmd_width_adapter_src_endofpacket; // new_sdram_controller_0_s1_cmd_width_adapter:out_endofpacket -> new_sdram_controller_0_s1_burst_adapter:sink0_endofpacket
wire [3:0] nios2_gen2_0_data_master_limiter_cmd_valid_data; // nios2_gen2_0_data_master_limiter:cmd_src_valid -> cmd_demux:sink_valid
wire [3:0] nios2_gen2_0_instruction_master_limiter_cmd_valid_data; // nios2_gen2_0_instruction_master_limiter:cmd_src_valid -> cmd_demux_001:sink_valid
wire jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_valid; // jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
wire [33:0] jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_data; // jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
wire jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter:in_0_ready -> jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_src_ready
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_out_0_ready; // jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_sink_error
wire nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_valid; // nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_001:in_0_valid
wire [33:0] nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_data; // nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_001:in_0_data
wire nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter_001:in_0_ready -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_src_ready
wire avalon_st_adapter_001_out_0_valid; // avalon_st_adapter_001:out_0_valid -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_001_out_0_data; // avalon_st_adapter_001:out_0_data -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_001_out_0_ready; // nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
wire [0:0] avalon_st_adapter_001_out_0_error; // avalon_st_adapter_001:out_0_error -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_error
wire onchip_memory2_0_s1_agent_rdata_fifo_src_valid; // onchip_memory2_0_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_002:in_0_valid
wire [33:0] onchip_memory2_0_s1_agent_rdata_fifo_src_data; // onchip_memory2_0_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_002:in_0_data
wire onchip_memory2_0_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_002:in_0_ready -> onchip_memory2_0_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_002_out_0_valid; // avalon_st_adapter_002:out_0_valid -> onchip_memory2_0_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_002_out_0_data; // avalon_st_adapter_002:out_0_data -> onchip_memory2_0_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_002_out_0_ready; // onchip_memory2_0_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_002:out_0_ready
wire [0:0] avalon_st_adapter_002_out_0_error; // avalon_st_adapter_002:out_0_error -> onchip_memory2_0_s1_agent:rdata_fifo_sink_error
wire new_sdram_controller_0_s1_agent_rdata_fifo_out_valid; // new_sdram_controller_0_s1_agent_rdata_fifo:out_valid -> avalon_st_adapter_003:in_0_valid
wire [17:0] new_sdram_controller_0_s1_agent_rdata_fifo_out_data; // new_sdram_controller_0_s1_agent_rdata_fifo:out_data -> avalon_st_adapter_003:in_0_data
wire new_sdram_controller_0_s1_agent_rdata_fifo_out_ready; // avalon_st_adapter_003:in_0_ready -> new_sdram_controller_0_s1_agent_rdata_fifo:out_ready
wire avalon_st_adapter_003_out_0_valid; // avalon_st_adapter_003:out_0_valid -> new_sdram_controller_0_s1_agent:rdata_fifo_sink_valid
wire [17:0] avalon_st_adapter_003_out_0_data; // avalon_st_adapter_003:out_0_data -> new_sdram_controller_0_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_003_out_0_ready; // new_sdram_controller_0_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_003:out_0_ready
wire [0:0] avalon_st_adapter_003_out_0_error; // avalon_st_adapter_003:out_0_error -> new_sdram_controller_0_s1_agent:rdata_fifo_sink_error
altera_merlin_master_translator #(
.AV_ADDRESS_W (27),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) nios2_gen2_0_data_master_translator (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_gen2_0_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios2_gen2_0_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios2_gen2_0_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios2_gen2_0_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios2_gen2_0_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_gen2_0_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios2_gen2_0_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios2_gen2_0_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios2_gen2_0_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios2_gen2_0_data_master_waitrequest), // .waitrequest
.av_byteenable (nios2_gen2_0_data_master_byteenable), // .byteenable
.av_read (nios2_gen2_0_data_master_read), // .read
.av_readdata (nios2_gen2_0_data_master_readdata), // .readdata
.av_readdatavalid (nios2_gen2_0_data_master_readdatavalid), // .readdatavalid
.av_write (nios2_gen2_0_data_master_write), // .write
.av_writedata (nios2_gen2_0_data_master_writedata), // .writedata
.av_debugaccess (nios2_gen2_0_data_master_debugaccess), // .debugaccess
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (17),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) nios2_gen2_0_instruction_master_translator (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios2_gen2_0_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios2_gen2_0_instruction_master_waitrequest), // .waitrequest
.av_read (nios2_gen2_0_instruction_master_read), // .read
.av_readdata (nios2_gen2_0_instruction_master_readdata), // .readdata
.av_readdatavalid (nios2_gen2_0_instruction_master_readdatavalid), // .readdatavalid
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) jtag_uart_0_avalon_jtag_slave_translator (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (jtag_uart_0_avalon_jtag_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (jtag_uart_0_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
.uav_read (jtag_uart_0_avalon_jtag_slave_agent_m0_read), // .read
.uav_write (jtag_uart_0_avalon_jtag_slave_agent_m0_write), // .write
.uav_waitrequest (jtag_uart_0_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (jtag_uart_0_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (jtag_uart_0_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (jtag_uart_0_avalon_jtag_slave_agent_m0_readdata), // .readdata
.uav_writedata (jtag_uart_0_avalon_jtag_slave_agent_m0_writedata), // .writedata
.uav_lock (jtag_uart_0_avalon_jtag_slave_agent_m0_lock), // .lock
.uav_debugaccess (jtag_uart_0_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
.av_address (jtag_uart_0_avalon_jtag_slave_address), // avalon_anti_slave_0.address
.av_write (jtag_uart_0_avalon_jtag_slave_write), // .write
.av_read (jtag_uart_0_avalon_jtag_slave_read), // .read
.av_readdata (jtag_uart_0_avalon_jtag_slave_readdata), // .readdata
.av_writedata (jtag_uart_0_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (jtag_uart_0_avalon_jtag_slave_waitrequest), // .waitrequest
.av_chipselect (jtag_uart_0_avalon_jtag_slave_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) nios2_gen2_0_debug_mem_slave_translator (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_gen2_0_debug_mem_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (nios2_gen2_0_debug_mem_slave_agent_m0_burstcount), // .burstcount
.uav_read (nios2_gen2_0_debug_mem_slave_agent_m0_read), // .read
.uav_write (nios2_gen2_0_debug_mem_slave_agent_m0_write), // .write
.uav_waitrequest (nios2_gen2_0_debug_mem_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_gen2_0_debug_mem_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_gen2_0_debug_mem_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (nios2_gen2_0_debug_mem_slave_agent_m0_readdata), // .readdata
.uav_writedata (nios2_gen2_0_debug_mem_slave_agent_m0_writedata), // .writedata
.uav_lock (nios2_gen2_0_debug_mem_slave_agent_m0_lock), // .lock
.uav_debugaccess (nios2_gen2_0_debug_mem_slave_agent_m0_debugaccess), // .debugaccess
.av_address (nios2_gen2_0_debug_mem_slave_address), // avalon_anti_slave_0.address
.av_write (nios2_gen2_0_debug_mem_slave_write), // .write
.av_read (nios2_gen2_0_debug_mem_slave_read), // .read
.av_readdata (nios2_gen2_0_debug_mem_slave_readdata), // .readdata
.av_writedata (nios2_gen2_0_debug_mem_slave_writedata), // .writedata
.av_byteenable (nios2_gen2_0_debug_mem_slave_byteenable), // .byteenable
.av_waitrequest (nios2_gen2_0_debug_mem_slave_waitrequest), // .waitrequest
.av_debugaccess (nios2_gen2_0_debug_mem_slave_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (14),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) onchip_memory2_0_s1_translator (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (onchip_memory2_0_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (onchip_memory2_0_s1_agent_m0_burstcount), // .burstcount
.uav_read (onchip_memory2_0_s1_agent_m0_read), // .read
.uav_write (onchip_memory2_0_s1_agent_m0_write), // .write
.uav_waitrequest (onchip_memory2_0_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (onchip_memory2_0_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (onchip_memory2_0_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (onchip_memory2_0_s1_agent_m0_readdata), // .readdata
.uav_writedata (onchip_memory2_0_s1_agent_m0_writedata), // .writedata
.uav_lock (onchip_memory2_0_s1_agent_m0_lock), // .lock
.uav_debugaccess (onchip_memory2_0_s1_agent_m0_debugaccess), // .debugaccess
.av_address (onchip_memory2_0_s1_address), // avalon_anti_slave_0.address
.av_write (onchip_memory2_0_s1_write), // .write
.av_readdata (onchip_memory2_0_s1_readdata), // .readdata
.av_writedata (onchip_memory2_0_s1_writedata), // .writedata
.av_byteenable (onchip_memory2_0_s1_byteenable), // .byteenable
.av_chipselect (onchip_memory2_0_s1_chipselect), // .chipselect
.av_clken (onchip_memory2_0_s1_clken), // .clken
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (25),
.AV_DATA_W (16),
.UAV_DATA_W (16),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (2),
.UAV_BYTEENABLE_W (2),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (2),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (2),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) new_sdram_controller_0_s1_translator (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (new_sdram_controller_0_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (new_sdram_controller_0_s1_agent_m0_burstcount), // .burstcount
.uav_read (new_sdram_controller_0_s1_agent_m0_read), // .read
.uav_write (new_sdram_controller_0_s1_agent_m0_write), // .write
.uav_waitrequest (new_sdram_controller_0_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (new_sdram_controller_0_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (new_sdram_controller_0_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (new_sdram_controller_0_s1_agent_m0_readdata), // .readdata
.uav_writedata (new_sdram_controller_0_s1_agent_m0_writedata), // .writedata
.uav_lock (new_sdram_controller_0_s1_agent_m0_lock), // .lock
.uav_debugaccess (new_sdram_controller_0_s1_agent_m0_debugaccess), // .debugaccess
.av_address (new_sdram_controller_0_s1_address), // avalon_anti_slave_0.address
.av_write (new_sdram_controller_0_s1_write), // .write
.av_read (new_sdram_controller_0_s1_read), // .read
.av_readdata (new_sdram_controller_0_s1_readdata), // .readdata
.av_writedata (new_sdram_controller_0_s1_writedata), // .writedata
.av_byteenable (new_sdram_controller_0_s1_byteenable), // .byteenable
.av_readdatavalid (new_sdram_controller_0_s1_readdatavalid), // .readdatavalid
.av_waitrequest (new_sdram_controller_0_s1_waitrequest), // .waitrequest
.av_chipselect (new_sdram_controller_0_s1_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (100),
.PKT_ORI_BURST_SIZE_L (98),
.PKT_RESPONSE_STATUS_H (97),
.PKT_RESPONSE_STATUS_L (96),
.PKT_QOS_H (83),
.PKT_QOS_L (83),
.PKT_DATA_SIDEBAND_H (81),
.PKT_DATA_SIDEBAND_L (81),
.PKT_ADDR_SIDEBAND_H (80),
.PKT_ADDR_SIDEBAND_L (80),
.PKT_BURST_TYPE_H (79),
.PKT_BURST_TYPE_L (78),
.PKT_CACHE_H (95),
.PKT_CACHE_L (92),
.PKT_THREAD_ID_H (88),
.PKT_THREAD_ID_L (88),
.PKT_BURST_SIZE_H (77),
.PKT_BURST_SIZE_L (75),
.PKT_TRANS_EXCLUSIVE (68),
.PKT_TRANS_LOCK (67),
.PKT_BEGIN_BURST (82),
.PKT_PROTECTION_H (91),
.PKT_PROTECTION_L (89),
.PKT_BURSTWRAP_H (74),
.PKT_BURSTWRAP_L (72),
.PKT_BYTE_CNT_H (71),
.PKT_BYTE_CNT_L (69),
.PKT_ADDR_H (62),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (63),
.PKT_TRANS_POSTED (64),
.PKT_TRANS_WRITE (65),
.PKT_TRANS_READ (66),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (85),
.PKT_SRC_ID_L (84),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (86),
.ST_DATA_W (101),
.ST_CHANNEL_W (4),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_gen2_0_data_master_agent (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (nios2_gen2_0_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios2_gen2_0_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios2_gen2_0_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios2_gen2_0_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios2_gen2_0_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios2_gen2_0_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios2_gen2_0_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios2_gen2_0_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios2_gen2_0_data_master_agent_cp_valid), // cp.valid
.cp_data (nios2_gen2_0_data_master_agent_cp_data), // .data
.cp_startofpacket (nios2_gen2_0_data_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios2_gen2_0_data_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios2_gen2_0_data_master_agent_cp_ready), // .ready
.rp_valid (nios2_gen2_0_data_master_limiter_rsp_src_valid), // rp.valid
.rp_data (nios2_gen2_0_data_master_limiter_rsp_src_data), // .data
.rp_channel (nios2_gen2_0_data_master_limiter_rsp_src_channel), // .channel
.rp_startofpacket (nios2_gen2_0_data_master_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (nios2_gen2_0_data_master_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (nios2_gen2_0_data_master_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (100),
.PKT_ORI_BURST_SIZE_L (98),
.PKT_RESPONSE_STATUS_H (97),
.PKT_RESPONSE_STATUS_L (96),
.PKT_QOS_H (83),
.PKT_QOS_L (83),
.PKT_DATA_SIDEBAND_H (81),
.PKT_DATA_SIDEBAND_L (81),
.PKT_ADDR_SIDEBAND_H (80),
.PKT_ADDR_SIDEBAND_L (80),
.PKT_BURST_TYPE_H (79),
.PKT_BURST_TYPE_L (78),
.PKT_CACHE_H (95),
.PKT_CACHE_L (92),
.PKT_THREAD_ID_H (88),
.PKT_THREAD_ID_L (88),
.PKT_BURST_SIZE_H (77),
.PKT_BURST_SIZE_L (75),
.PKT_TRANS_EXCLUSIVE (68),
.PKT_TRANS_LOCK (67),
.PKT_BEGIN_BURST (82),
.PKT_PROTECTION_H (91),
.PKT_PROTECTION_L (89),
.PKT_BURSTWRAP_H (74),
.PKT_BURSTWRAP_L (72),
.PKT_BYTE_CNT_H (71),
.PKT_BYTE_CNT_L (69),
.PKT_ADDR_H (62),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (63),
.PKT_TRANS_POSTED (64),
.PKT_TRANS_WRITE (65),
.PKT_TRANS_READ (66),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (85),
.PKT_SRC_ID_L (84),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (86),
.ST_DATA_W (101),
.ST_CHANNEL_W (4),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (3),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_gen2_0_instruction_master_agent (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios2_gen2_0_instruction_master_agent_cp_valid), // cp.valid
.cp_data (nios2_gen2_0_instruction_master_agent_cp_data), // .data
.cp_startofpacket (nios2_gen2_0_instruction_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios2_gen2_0_instruction_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios2_gen2_0_instruction_master_agent_cp_ready), // .ready
.rp_valid (nios2_gen2_0_instruction_master_limiter_rsp_src_valid), // rp.valid
.rp_data (nios2_gen2_0_instruction_master_limiter_rsp_src_data), // .data
.rp_channel (nios2_gen2_0_instruction_master_limiter_rsp_src_channel), // .channel
.rp_startofpacket (nios2_gen2_0_instruction_master_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (nios2_gen2_0_instruction_master_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (nios2_gen2_0_instruction_master_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (100),
.PKT_ORI_BURST_SIZE_L (98),
.PKT_RESPONSE_STATUS_H (97),
.PKT_RESPONSE_STATUS_L (96),
.PKT_BURST_SIZE_H (77),
.PKT_BURST_SIZE_L (75),
.PKT_TRANS_LOCK (67),
.PKT_BEGIN_BURST (82),
.PKT_PROTECTION_H (91),
.PKT_PROTECTION_L (89),
.PKT_BURSTWRAP_H (74),
.PKT_BURSTWRAP_L (72),
.PKT_BYTE_CNT_H (71),
.PKT_BYTE_CNT_L (69),
.PKT_ADDR_H (62),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (63),
.PKT_TRANS_POSTED (64),
.PKT_TRANS_WRITE (65),
.PKT_TRANS_READ (66),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (85),
.PKT_SRC_ID_L (84),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (86),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (4),
.ST_DATA_W (101),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) jtag_uart_0_avalon_jtag_slave_agent (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (jtag_uart_0_avalon_jtag_slave_agent_m0_address), // m0.address
.m0_burstcount (jtag_uart_0_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (jtag_uart_0_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (jtag_uart_0_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (jtag_uart_0_avalon_jtag_slave_agent_m0_lock), // .lock
.m0_readdata (jtag_uart_0_avalon_jtag_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (jtag_uart_0_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (jtag_uart_0_avalon_jtag_slave_agent_m0_read), // .read
.m0_waitrequest (jtag_uart_0_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (jtag_uart_0_avalon_jtag_slave_agent_m0_writedata), // .writedata
.m0_write (jtag_uart_0_avalon_jtag_slave_agent_m0_write), // .write
.rp_endofpacket (jtag_uart_0_avalon_jtag_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (jtag_uart_0_avalon_jtag_slave_agent_rp_ready), // .ready
.rp_valid (jtag_uart_0_avalon_jtag_slave_agent_rp_valid), // .valid
.rp_data (jtag_uart_0_avalon_jtag_slave_agent_rp_data), // .data
.rp_startofpacket (jtag_uart_0_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (jtag_uart_0_avalon_jtag_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (jtag_uart_0_avalon_jtag_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (jtag_uart_0_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (jtag_uart_0_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (jtag_uart_0_avalon_jtag_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
.rdata_fifo_src_ready (jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (102),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (jtag_uart_0_avalon_jtag_slave_agent_rf_source_data), // in.data
.in_valid (jtag_uart_0_avalon_jtag_slave_agent_rf_source_valid), // .valid
.in_ready (jtag_uart_0_avalon_jtag_slave_agent_rf_source_ready), // .ready
.in_startofpacket (jtag_uart_0_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (jtag_uart_0_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (100),
.PKT_ORI_BURST_SIZE_L (98),
.PKT_RESPONSE_STATUS_H (97),
.PKT_RESPONSE_STATUS_L (96),
.PKT_BURST_SIZE_H (77),
.PKT_BURST_SIZE_L (75),
.PKT_TRANS_LOCK (67),
.PKT_BEGIN_BURST (82),
.PKT_PROTECTION_H (91),
.PKT_PROTECTION_L (89),
.PKT_BURSTWRAP_H (74),
.PKT_BURSTWRAP_L (72),
.PKT_BYTE_CNT_H (71),
.PKT_BYTE_CNT_L (69),
.PKT_ADDR_H (62),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (63),
.PKT_TRANS_POSTED (64),
.PKT_TRANS_WRITE (65),
.PKT_TRANS_READ (66),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (85),
.PKT_SRC_ID_L (84),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (86),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (4),
.ST_DATA_W (101),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) nios2_gen2_0_debug_mem_slave_agent (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (nios2_gen2_0_debug_mem_slave_agent_m0_address), // m0.address
.m0_burstcount (nios2_gen2_0_debug_mem_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (nios2_gen2_0_debug_mem_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (nios2_gen2_0_debug_mem_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (nios2_gen2_0_debug_mem_slave_agent_m0_lock), // .lock
.m0_readdata (nios2_gen2_0_debug_mem_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (nios2_gen2_0_debug_mem_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (nios2_gen2_0_debug_mem_slave_agent_m0_read), // .read
.m0_waitrequest (nios2_gen2_0_debug_mem_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (nios2_gen2_0_debug_mem_slave_agent_m0_writedata), // .writedata
.m0_write (nios2_gen2_0_debug_mem_slave_agent_m0_write), // .write
.rp_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (nios2_gen2_0_debug_mem_slave_agent_rp_ready), // .ready
.rp_valid (nios2_gen2_0_debug_mem_slave_agent_rp_valid), // .valid
.rp_data (nios2_gen2_0_debug_mem_slave_agent_rp_data), // .data
.rp_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_001_src_ready), // cp.ready
.cp_valid (cmd_mux_001_src_valid), // .valid
.cp_data (cmd_mux_001_src_data), // .data
.cp_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_001_src_channel), // .channel
.rf_sink_ready (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (nios2_gen2_0_debug_mem_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (nios2_gen2_0_debug_mem_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (nios2_gen2_0_debug_mem_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_001_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_001_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_001_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_001_out_0_error), // .error
.rdata_fifo_src_ready (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (102),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) nios2_gen2_0_debug_mem_slave_agent_rsp_fifo (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (nios2_gen2_0_debug_mem_slave_agent_rf_source_data), // in.data
.in_valid (nios2_gen2_0_debug_mem_slave_agent_rf_source_valid), // .valid
.in_ready (nios2_gen2_0_debug_mem_slave_agent_rf_source_ready), // .ready
.in_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (100),
.PKT_ORI_BURST_SIZE_L (98),
.PKT_RESPONSE_STATUS_H (97),
.PKT_RESPONSE_STATUS_L (96),
.PKT_BURST_SIZE_H (77),
.PKT_BURST_SIZE_L (75),
.PKT_TRANS_LOCK (67),
.PKT_BEGIN_BURST (82),
.PKT_PROTECTION_H (91),
.PKT_PROTECTION_L (89),
.PKT_BURSTWRAP_H (74),
.PKT_BURSTWRAP_L (72),
.PKT_BYTE_CNT_H (71),
.PKT_BYTE_CNT_L (69),
.PKT_ADDR_H (62),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (63),
.PKT_TRANS_POSTED (64),
.PKT_TRANS_WRITE (65),
.PKT_TRANS_READ (66),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (85),
.PKT_SRC_ID_L (84),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (86),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (4),
.ST_DATA_W (101),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) onchip_memory2_0_s1_agent (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (onchip_memory2_0_s1_agent_m0_address), // m0.address
.m0_burstcount (onchip_memory2_0_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (onchip_memory2_0_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (onchip_memory2_0_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (onchip_memory2_0_s1_agent_m0_lock), // .lock
.m0_readdata (onchip_memory2_0_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (onchip_memory2_0_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (onchip_memory2_0_s1_agent_m0_read), // .read
.m0_waitrequest (onchip_memory2_0_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (onchip_memory2_0_s1_agent_m0_writedata), // .writedata
.m0_write (onchip_memory2_0_s1_agent_m0_write), // .write
.rp_endofpacket (onchip_memory2_0_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (onchip_memory2_0_s1_agent_rp_ready), // .ready
.rp_valid (onchip_memory2_0_s1_agent_rp_valid), // .valid
.rp_data (onchip_memory2_0_s1_agent_rp_data), // .data
.rp_startofpacket (onchip_memory2_0_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_002_src_ready), // cp.ready
.cp_valid (cmd_mux_002_src_valid), // .valid
.cp_data (cmd_mux_002_src_data), // .data
.cp_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_002_src_channel), // .channel
.rf_sink_ready (onchip_memory2_0_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (onchip_memory2_0_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (onchip_memory2_0_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (onchip_memory2_0_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (onchip_memory2_0_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (onchip_memory2_0_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (onchip_memory2_0_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (onchip_memory2_0_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_002_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_002_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_002_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_002_out_0_error), // .error
.rdata_fifo_src_ready (onchip_memory2_0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (onchip_memory2_0_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (onchip_memory2_0_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (102),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) onchip_memory2_0_s1_agent_rsp_fifo (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (onchip_memory2_0_s1_agent_rf_source_data), // in.data
.in_valid (onchip_memory2_0_s1_agent_rf_source_valid), // .valid
.in_ready (onchip_memory2_0_s1_agent_rf_source_ready), // .ready
.in_startofpacket (onchip_memory2_0_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (onchip_memory2_0_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (onchip_memory2_0_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (onchip_memory2_0_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (onchip_memory2_0_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (82),
.PKT_ORI_BURST_SIZE_L (80),
.PKT_RESPONSE_STATUS_H (79),
.PKT_RESPONSE_STATUS_L (78),
.PKT_BURST_SIZE_H (59),
.PKT_BURST_SIZE_L (57),
.PKT_TRANS_LOCK (49),
.PKT_BEGIN_BURST (64),
.PKT_PROTECTION_H (73),
.PKT_PROTECTION_L (71),
.PKT_BURSTWRAP_H (56),
.PKT_BURSTWRAP_L (54),
.PKT_BYTE_CNT_H (53),
.PKT_BYTE_CNT_L (51),
.PKT_ADDR_H (44),
.PKT_ADDR_L (18),
.PKT_TRANS_COMPRESSED_READ (45),
.PKT_TRANS_POSTED (46),
.PKT_TRANS_WRITE (47),
.PKT_TRANS_READ (48),
.PKT_DATA_H (15),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_SRC_ID_H (67),
.PKT_SRC_ID_L (66),
.PKT_DEST_ID_H (69),
.PKT_DEST_ID_L (68),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (4),
.ST_DATA_W (83),
.AVS_BURSTCOUNT_W (2),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) new_sdram_controller_0_s1_agent (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (new_sdram_controller_0_s1_agent_m0_address), // m0.address
.m0_burstcount (new_sdram_controller_0_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (new_sdram_controller_0_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (new_sdram_controller_0_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (new_sdram_controller_0_s1_agent_m0_lock), // .lock
.m0_readdata (new_sdram_controller_0_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (new_sdram_controller_0_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (new_sdram_controller_0_s1_agent_m0_read), // .read
.m0_waitrequest (new_sdram_controller_0_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (new_sdram_controller_0_s1_agent_m0_writedata), // .writedata
.m0_write (new_sdram_controller_0_s1_agent_m0_write), // .write
.rp_endofpacket (new_sdram_controller_0_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (new_sdram_controller_0_s1_agent_rp_ready), // .ready
.rp_valid (new_sdram_controller_0_s1_agent_rp_valid), // .valid
.rp_data (new_sdram_controller_0_s1_agent_rp_data), // .data
.rp_startofpacket (new_sdram_controller_0_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (new_sdram_controller_0_s1_burst_adapter_source0_ready), // cp.ready
.cp_valid (new_sdram_controller_0_s1_burst_adapter_source0_valid), // .valid
.cp_data (new_sdram_controller_0_s1_burst_adapter_source0_data), // .data
.cp_startofpacket (new_sdram_controller_0_s1_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (new_sdram_controller_0_s1_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (new_sdram_controller_0_s1_burst_adapter_source0_channel), // .channel
.rf_sink_ready (new_sdram_controller_0_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (new_sdram_controller_0_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (new_sdram_controller_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (new_sdram_controller_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (new_sdram_controller_0_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (new_sdram_controller_0_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (new_sdram_controller_0_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (new_sdram_controller_0_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (new_sdram_controller_0_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (new_sdram_controller_0_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_003_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_003_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_003_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_003_out_0_error), // .error
.rdata_fifo_src_ready (new_sdram_controller_0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (new_sdram_controller_0_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (new_sdram_controller_0_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (84),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) new_sdram_controller_0_s1_agent_rsp_fifo (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (new_sdram_controller_0_s1_agent_rf_source_data), // in.data
.in_valid (new_sdram_controller_0_s1_agent_rf_source_valid), // .valid
.in_ready (new_sdram_controller_0_s1_agent_rf_source_ready), // .ready
.in_startofpacket (new_sdram_controller_0_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (new_sdram_controller_0_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (new_sdram_controller_0_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (new_sdram_controller_0_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (new_sdram_controller_0_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (new_sdram_controller_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (new_sdram_controller_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (18),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (3),
.USE_MEMORY_BLOCKS (1),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) new_sdram_controller_0_s1_agent_rdata_fifo (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (new_sdram_controller_0_s1_agent_rdata_fifo_src_data), // in.data
.in_valid (new_sdram_controller_0_s1_agent_rdata_fifo_src_valid), // .valid
.in_ready (new_sdram_controller_0_s1_agent_rdata_fifo_src_ready), // .ready
.out_data (new_sdram_controller_0_s1_agent_rdata_fifo_out_data), // out.data
.out_valid (new_sdram_controller_0_s1_agent_rdata_fifo_out_valid), // .valid
.out_ready (new_sdram_controller_0_s1_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
system_mm_interconnect_0_router router (
.sink_ready (nios2_gen2_0_data_master_agent_cp_ready), // sink.ready
.sink_valid (nios2_gen2_0_data_master_agent_cp_valid), // .valid
.sink_data (nios2_gen2_0_data_master_agent_cp_data), // .data
.sink_startofpacket (nios2_gen2_0_data_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_gen2_0_data_master_agent_cp_endofpacket), // .endofpacket
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
system_mm_interconnect_0_router_001 router_001 (
.sink_ready (nios2_gen2_0_instruction_master_agent_cp_ready), // sink.ready
.sink_valid (nios2_gen2_0_instruction_master_agent_cp_valid), // .valid
.sink_data (nios2_gen2_0_instruction_master_agent_cp_data), // .data
.sink_startofpacket (nios2_gen2_0_instruction_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_gen2_0_instruction_master_agent_cp_endofpacket), // .endofpacket
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
system_mm_interconnect_0_router_002 router_002 (
.sink_ready (jtag_uart_0_avalon_jtag_slave_agent_rp_ready), // sink.ready
.sink_valid (jtag_uart_0_avalon_jtag_slave_agent_rp_valid), // .valid
.sink_data (jtag_uart_0_avalon_jtag_slave_agent_rp_data), // .data
.sink_startofpacket (jtag_uart_0_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (jtag_uart_0_avalon_jtag_slave_agent_rp_endofpacket), // .endofpacket
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
system_mm_interconnect_0_router_003 router_003 (
.sink_ready (nios2_gen2_0_debug_mem_slave_agent_rp_ready), // sink.ready
.sink_valid (nios2_gen2_0_debug_mem_slave_agent_rp_valid), // .valid
.sink_data (nios2_gen2_0_debug_mem_slave_agent_rp_data), // .data
.sink_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_endofpacket), // .endofpacket
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
system_mm_interconnect_0_router_003 router_004 (
.sink_ready (onchip_memory2_0_s1_agent_rp_ready), // sink.ready
.sink_valid (onchip_memory2_0_s1_agent_rp_valid), // .valid
.sink_data (onchip_memory2_0_s1_agent_rp_data), // .data
.sink_startofpacket (onchip_memory2_0_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (onchip_memory2_0_s1_agent_rp_endofpacket), // .endofpacket
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
system_mm_interconnect_0_router_005 router_005 (
.sink_ready (new_sdram_controller_0_s1_agent_rp_ready), // sink.ready
.sink_valid (new_sdram_controller_0_s1_agent_rp_valid), // .valid
.sink_data (new_sdram_controller_0_s1_agent_rp_data), // .data
.sink_startofpacket (new_sdram_controller_0_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (new_sdram_controller_0_s1_agent_rp_endofpacket), // .endofpacket
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (86),
.PKT_SRC_ID_H (85),
.PKT_SRC_ID_L (84),
.PKT_BYTE_CNT_H (71),
.PKT_BYTE_CNT_L (69),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_TRANS_POSTED (64),
.PKT_TRANS_WRITE (65),
.MAX_OUTSTANDING_RESPONSES (9),
.PIPELINED (0),
.ST_DATA_W (101),
.ST_CHANNEL_W (4),
.VALID_WIDTH (4),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.SUPPORTS_POSTED_WRITES (1),
.SUPPORTS_NONPOSTED_WRITES (0),
.REORDER (0)
) nios2_gen2_0_data_master_limiter (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_src_valid), // .valid
.cmd_sink_data (router_src_data), // .data
.cmd_sink_channel (router_src_channel), // .channel
.cmd_sink_startofpacket (router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_src_endofpacket), // .endofpacket
.cmd_src_ready (nios2_gen2_0_data_master_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (nios2_gen2_0_data_master_limiter_cmd_src_data), // .data
.cmd_src_channel (nios2_gen2_0_data_master_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (nios2_gen2_0_data_master_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (nios2_gen2_0_data_master_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_src_valid), // .valid
.rsp_sink_channel (rsp_mux_src_channel), // .channel
.rsp_sink_data (rsp_mux_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rsp_src_ready (nios2_gen2_0_data_master_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (nios2_gen2_0_data_master_limiter_rsp_src_valid), // .valid
.rsp_src_data (nios2_gen2_0_data_master_limiter_rsp_src_data), // .data
.rsp_src_channel (nios2_gen2_0_data_master_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (nios2_gen2_0_data_master_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (nios2_gen2_0_data_master_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (nios2_gen2_0_data_master_limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (86),
.PKT_SRC_ID_H (85),
.PKT_SRC_ID_L (84),
.PKT_BYTE_CNT_H (71),
.PKT_BYTE_CNT_L (69),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_TRANS_POSTED (64),
.PKT_TRANS_WRITE (65),
.MAX_OUTSTANDING_RESPONSES (1),
.PIPELINED (0),
.ST_DATA_W (101),
.ST_CHANNEL_W (4),
.VALID_WIDTH (4),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.SUPPORTS_POSTED_WRITES (1),
.SUPPORTS_NONPOSTED_WRITES (0),
.REORDER (0)
) nios2_gen2_0_instruction_master_limiter (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_001_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_001_src_valid), // .valid
.cmd_sink_data (router_001_src_data), // .data
.cmd_sink_channel (router_001_src_channel), // .channel
.cmd_sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.cmd_src_ready (nios2_gen2_0_instruction_master_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (nios2_gen2_0_instruction_master_limiter_cmd_src_data), // .data
.cmd_src_channel (nios2_gen2_0_instruction_master_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (nios2_gen2_0_instruction_master_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (nios2_gen2_0_instruction_master_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_001_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_001_src_valid), // .valid
.rsp_sink_channel (rsp_mux_001_src_channel), // .channel
.rsp_sink_data (rsp_mux_001_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rsp_src_ready (nios2_gen2_0_instruction_master_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (nios2_gen2_0_instruction_master_limiter_rsp_src_valid), // .valid
.rsp_src_data (nios2_gen2_0_instruction_master_limiter_rsp_src_data), // .data
.rsp_src_channel (nios2_gen2_0_instruction_master_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (nios2_gen2_0_instruction_master_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (nios2_gen2_0_instruction_master_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (nios2_gen2_0_instruction_master_limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (44),
.PKT_ADDR_L (18),
.PKT_BEGIN_BURST (64),
.PKT_BYTE_CNT_H (53),
.PKT_BYTE_CNT_L (51),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_BURST_SIZE_H (59),
.PKT_BURST_SIZE_L (57),
.PKT_BURST_TYPE_H (61),
.PKT_BURST_TYPE_L (60),
.PKT_BURSTWRAP_H (56),
.PKT_BURSTWRAP_L (54),
.PKT_TRANS_COMPRESSED_READ (45),
.PKT_TRANS_WRITE (47),
.PKT_TRANS_READ (48),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (83),
.ST_CHANNEL_W (4),
.OUT_BYTE_CNT_H (52),
.OUT_BURSTWRAP_H (56),
.COMPRESSED_READ_SUPPORT (0),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (7),
.BURSTWRAP_CONST_VALUE (7),
.ADAPTER_VERSION ("13.1")
) new_sdram_controller_0_s1_burst_adapter (
.clk (pll_0_outclk0_clk), // cr0.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (new_sdram_controller_0_s1_cmd_width_adapter_src_valid), // sink0.valid
.sink0_data (new_sdram_controller_0_s1_cmd_width_adapter_src_data), // .data
.sink0_channel (new_sdram_controller_0_s1_cmd_width_adapter_src_channel), // .channel
.sink0_startofpacket (new_sdram_controller_0_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.sink0_endofpacket (new_sdram_controller_0_s1_cmd_width_adapter_src_endofpacket), // .endofpacket
.sink0_ready (new_sdram_controller_0_s1_cmd_width_adapter_src_ready), // .ready
.source0_valid (new_sdram_controller_0_s1_burst_adapter_source0_valid), // source0.valid
.source0_data (new_sdram_controller_0_s1_burst_adapter_source0_data), // .data
.source0_channel (new_sdram_controller_0_s1_burst_adapter_source0_channel), // .channel
.source0_startofpacket (new_sdram_controller_0_s1_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (new_sdram_controller_0_s1_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (new_sdram_controller_0_s1_burst_adapter_source0_ready) // .ready
);
system_mm_interconnect_0_cmd_demux cmd_demux (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (nios2_gen2_0_data_master_limiter_cmd_src_ready), // sink.ready
.sink_channel (nios2_gen2_0_data_master_limiter_cmd_src_channel), // .channel
.sink_data (nios2_gen2_0_data_master_limiter_cmd_src_data), // .data
.sink_startofpacket (nios2_gen2_0_data_master_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (nios2_gen2_0_data_master_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (nios2_gen2_0_data_master_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_src2_ready), // src2.ready
.src2_valid (cmd_demux_src2_valid), // .valid
.src2_data (cmd_demux_src2_data), // .data
.src2_channel (cmd_demux_src2_channel), // .channel
.src2_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_src3_ready), // src3.ready
.src3_valid (cmd_demux_src3_valid), // .valid
.src3_data (cmd_demux_src3_data), // .data
.src3_channel (cmd_demux_src3_channel), // .channel
.src3_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_src3_endofpacket) // .endofpacket
);
system_mm_interconnect_0_cmd_demux_001 cmd_demux_001 (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (nios2_gen2_0_instruction_master_limiter_cmd_src_ready), // sink.ready
.sink_channel (nios2_gen2_0_instruction_master_limiter_cmd_src_channel), // .channel
.sink_data (nios2_gen2_0_instruction_master_limiter_cmd_src_data), // .data
.sink_startofpacket (nios2_gen2_0_instruction_master_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (nios2_gen2_0_instruction_master_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (nios2_gen2_0_instruction_master_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_demux_001_src1_valid), // .valid
.src1_data (cmd_demux_001_src1_data), // .data
.src1_channel (cmd_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_001_src1_endofpacket) // .endofpacket
);
system_mm_interconnect_0_cmd_mux cmd_mux (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
system_mm_interconnect_0_cmd_mux_001 cmd_mux_001 (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_src1_valid), // .valid
.sink0_channel (cmd_demux_src1_channel), // .channel
.sink0_data (cmd_demux_src1_data), // .data
.sink0_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
system_mm_interconnect_0_cmd_mux_001 cmd_mux_002 (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_src2_valid), // .valid
.sink0_channel (cmd_demux_src2_channel), // .channel
.sink0_data (cmd_demux_src2_data), // .data
.sink0_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src1_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src1_valid), // .valid
.sink1_channel (cmd_demux_001_src1_channel), // .channel
.sink1_data (cmd_demux_001_src1_data), // .data
.sink1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src1_endofpacket) // .endofpacket
);
system_mm_interconnect_0_cmd_mux cmd_mux_003 (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_src3_valid), // .valid
.sink0_channel (cmd_demux_src3_channel), // .channel
.sink0_data (cmd_demux_src3_data), // .data
.sink0_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src3_endofpacket) // .endofpacket
);
system_mm_interconnect_0_rsp_demux rsp_demux (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
system_mm_interconnect_0_rsp_demux_001 rsp_demux_001 (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_003_src_ready), // sink.ready
.sink_channel (router_003_src_channel), // .channel
.sink_data (router_003_src_data), // .data
.sink_startofpacket (router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (router_003_src_endofpacket), // .endofpacket
.sink_valid (router_003_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_demux_001_src1_valid), // .valid
.src1_data (rsp_demux_001_src1_data), // .data
.src1_channel (rsp_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_001_src1_endofpacket) // .endofpacket
);
system_mm_interconnect_0_rsp_demux_001 rsp_demux_002 (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_004_src_ready), // sink.ready
.sink_channel (router_004_src_channel), // .channel
.sink_data (router_004_src_data), // .data
.sink_startofpacket (router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (router_004_src_endofpacket), // .endofpacket
.sink_valid (router_004_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_002_src1_ready), // src1.ready
.src1_valid (rsp_demux_002_src1_valid), // .valid
.src1_data (rsp_demux_002_src1_data), // .data
.src1_channel (rsp_demux_002_src1_channel), // .channel
.src1_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_002_src1_endofpacket) // .endofpacket
);
system_mm_interconnect_0_rsp_demux rsp_demux_003 (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (new_sdram_controller_0_s1_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (new_sdram_controller_0_s1_rsp_width_adapter_src_channel), // .channel
.sink_data (new_sdram_controller_0_s1_rsp_width_adapter_src_data), // .data
.sink_startofpacket (new_sdram_controller_0_s1_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (new_sdram_controller_0_s1_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (new_sdram_controller_0_s1_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket) // .endofpacket
);
system_mm_interconnect_0_rsp_mux rsp_mux (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket) // .endofpacket
);
system_mm_interconnect_0_rsp_mux_001 rsp_mux_001 (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_001_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_001_src1_valid), // .valid
.sink0_channel (rsp_demux_001_src1_channel), // .channel
.sink0_data (rsp_demux_001_src1_data), // .data
.sink0_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_001_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_002_src1_ready), // sink1.ready
.sink1_valid (rsp_demux_002_src1_valid), // .valid
.sink1_channel (rsp_demux_002_src1_channel), // .channel
.sink1_data (rsp_demux_002_src1_data), // .data
.sink1_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_002_src1_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (44),
.IN_PKT_ADDR_L (18),
.IN_PKT_DATA_H (15),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (17),
.IN_PKT_BYTEEN_L (16),
.IN_PKT_BYTE_CNT_H (53),
.IN_PKT_BYTE_CNT_L (51),
.IN_PKT_TRANS_COMPRESSED_READ (45),
.IN_PKT_TRANS_WRITE (47),
.IN_PKT_BURSTWRAP_H (56),
.IN_PKT_BURSTWRAP_L (54),
.IN_PKT_BURST_SIZE_H (59),
.IN_PKT_BURST_SIZE_L (57),
.IN_PKT_RESPONSE_STATUS_H (79),
.IN_PKT_RESPONSE_STATUS_L (78),
.IN_PKT_TRANS_EXCLUSIVE (50),
.IN_PKT_BURST_TYPE_H (61),
.IN_PKT_BURST_TYPE_L (60),
.IN_PKT_ORI_BURST_SIZE_L (80),
.IN_PKT_ORI_BURST_SIZE_H (82),
.IN_ST_DATA_W (83),
.OUT_PKT_ADDR_H (62),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (71),
.OUT_PKT_BYTE_CNT_L (69),
.OUT_PKT_TRANS_COMPRESSED_READ (63),
.OUT_PKT_BURST_SIZE_H (77),
.OUT_PKT_BURST_SIZE_L (75),
.OUT_PKT_RESPONSE_STATUS_H (97),
.OUT_PKT_RESPONSE_STATUS_L (96),
.OUT_PKT_TRANS_EXCLUSIVE (68),
.OUT_PKT_BURST_TYPE_H (79),
.OUT_PKT_BURST_TYPE_L (78),
.OUT_PKT_ORI_BURST_SIZE_L (98),
.OUT_PKT_ORI_BURST_SIZE_H (100),
.OUT_ST_DATA_W (101),
.ST_CHANNEL_W (4),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) new_sdram_controller_0_s1_rsp_width_adapter (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_005_src_valid), // sink.valid
.in_channel (router_005_src_channel), // .channel
.in_startofpacket (router_005_src_startofpacket), // .startofpacket
.in_endofpacket (router_005_src_endofpacket), // .endofpacket
.in_ready (router_005_src_ready), // .ready
.in_data (router_005_src_data), // .data
.out_endofpacket (new_sdram_controller_0_s1_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (new_sdram_controller_0_s1_rsp_width_adapter_src_data), // .data
.out_channel (new_sdram_controller_0_s1_rsp_width_adapter_src_channel), // .channel
.out_valid (new_sdram_controller_0_s1_rsp_width_adapter_src_valid), // .valid
.out_ready (new_sdram_controller_0_s1_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (new_sdram_controller_0_s1_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (62),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (71),
.IN_PKT_BYTE_CNT_L (69),
.IN_PKT_TRANS_COMPRESSED_READ (63),
.IN_PKT_TRANS_WRITE (65),
.IN_PKT_BURSTWRAP_H (74),
.IN_PKT_BURSTWRAP_L (72),
.IN_PKT_BURST_SIZE_H (77),
.IN_PKT_BURST_SIZE_L (75),
.IN_PKT_RESPONSE_STATUS_H (97),
.IN_PKT_RESPONSE_STATUS_L (96),
.IN_PKT_TRANS_EXCLUSIVE (68),
.IN_PKT_BURST_TYPE_H (79),
.IN_PKT_BURST_TYPE_L (78),
.IN_PKT_ORI_BURST_SIZE_L (98),
.IN_PKT_ORI_BURST_SIZE_H (100),
.IN_ST_DATA_W (101),
.OUT_PKT_ADDR_H (44),
.OUT_PKT_ADDR_L (18),
.OUT_PKT_DATA_H (15),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (17),
.OUT_PKT_BYTEEN_L (16),
.OUT_PKT_BYTE_CNT_H (53),
.OUT_PKT_BYTE_CNT_L (51),
.OUT_PKT_TRANS_COMPRESSED_READ (45),
.OUT_PKT_BURST_SIZE_H (59),
.OUT_PKT_BURST_SIZE_L (57),
.OUT_PKT_RESPONSE_STATUS_H (79),
.OUT_PKT_RESPONSE_STATUS_L (78),
.OUT_PKT_TRANS_EXCLUSIVE (50),
.OUT_PKT_BURST_TYPE_H (61),
.OUT_PKT_BURST_TYPE_L (60),
.OUT_PKT_ORI_BURST_SIZE_L (80),
.OUT_PKT_ORI_BURST_SIZE_H (82),
.OUT_ST_DATA_W (83),
.ST_CHANNEL_W (4),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) new_sdram_controller_0_s1_cmd_width_adapter (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_003_src_valid), // sink.valid
.in_channel (cmd_mux_003_src_channel), // .channel
.in_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_003_src_ready), // .ready
.in_data (cmd_mux_003_src_data), // .data
.out_endofpacket (new_sdram_controller_0_s1_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (new_sdram_controller_0_s1_cmd_width_adapter_src_data), // .data
.out_channel (new_sdram_controller_0_s1_cmd_width_adapter_src_channel), // .channel
.out_valid (new_sdram_controller_0_s1_cmd_width_adapter_src_valid), // .valid
.out_ready (new_sdram_controller_0_s1_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (new_sdram_controller_0_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
system_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (pll_0_outclk0_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_out_0_error) // .error
);
system_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_001 (
.in_clk_0_clk (pll_0_outclk0_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_001_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_001_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_001_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_001_out_0_error) // .error
);
system_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_002 (
.in_clk_0_clk (pll_0_outclk0_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (onchip_memory2_0_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (onchip_memory2_0_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (onchip_memory2_0_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_002_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_002_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_002_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_002_out_0_error) // .error
);
system_mm_interconnect_0_avalon_st_adapter_003 #(
.inBitsPerSymbol (18),
.inUsePackets (0),
.inDataWidth (18),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (18),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_003 (
.in_clk_0_clk (pll_0_outclk0_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (new_sdram_controller_0_s1_agent_rdata_fifo_out_data), // in_0.data
.in_0_valid (new_sdram_controller_0_s1_agent_rdata_fifo_out_valid), // .valid
.in_0_ready (new_sdram_controller_0_s1_agent_rdata_fifo_out_ready), // .ready
.out_0_data (avalon_st_adapter_003_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_003_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_003_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_003_out_0_error) // .error
);
endmodule
|
`include "defines.v"
module serialcontrol(
input wire clk25,
input wire rst,
//Input
//Control from MMU
input wire[2:0] ramOp_i,
input wire mode_i, /* 0: data; 1: control */
input wire[7:0] storeData_i,
//Output
//Data to MMU
output wire[31:0] ramData_o,
//Interrupt
output wire serialInt_o,
//Physical circuit
input wire RxD,
output wire TxD
);
reg[7:0] buffer[0:15];
reg[3:0] readPos;
reg[3:0] recvPos;
wire data_ready;
wire[7:0] data_receive;
wire write_busy;
reg[7:0] ramData;
wire[3:0] nextRecvPos = (recvPos == 15) ? 0 : recvPos + 1;
wire[3:0] nextReadPos = (readPos == 15) ? 0 : readPos + 1;
wire bufferEmpty = (recvPos == readPos);
wire serialRead = (ramOp_i == `MEM_LW_OP && mode_i == 0);
wire serialWrite = (ramOp_i == `MEM_SW_OP && mode_i == 0);
wire[7:0] controlData = {6'h0, ~bufferEmpty, ~write_busy};
assign ramData_o = {24'h0, mode_i ? controlData : ramData};
assign serialInt_o = data_ready | !bufferEmpty;
//Simulation
always @(posedge clk25) begin
if (serialWrite) begin
$write("%c", storeData_i);
end
end
//Receive buffer
always @(posedge clk25) begin
if (rst == `Enable) begin
buffer[0] <= `ZeroByte;
buffer[1] <= `ZeroByte;
buffer[2] <= `ZeroByte;
buffer[3] <= `ZeroByte;
buffer[4] <= `ZeroByte;
buffer[5] <= `ZeroByte;
buffer[6] <= `ZeroByte;
buffer[7] <= `ZeroByte;
buffer[8] <= `ZeroByte;
buffer[9] <= `ZeroByte;
buffer[10] <= `ZeroByte;
buffer[11] <= `ZeroByte;
buffer[12] <= `ZeroByte;
buffer[13] <= `ZeroByte;
buffer[14] <= `ZeroByte;
buffer[15] <= `ZeroByte;
end else if (data_ready == `Enable) begin
buffer[recvPos] <= data_receive;
end
end
//Receive pointer
always @(posedge clk25) begin
if (rst == `Enable) begin
recvPos <= 0;
end else if (data_ready == `Enable) begin
recvPos <= nextRecvPos;
end
end
//Read pointer
always @(posedge clk25) begin
if (rst == `Enable) begin
readPos <= 0;
end else if (serialRead && !bufferEmpty) begin
readPos <= nextReadPos;
end
end
//Data output
always @(*) begin
//Data
ramData = `ZeroByte;
if (serialRead) begin
if (!bufferEmpty) begin
ramData = buffer[readPos];
end else if (data_ready) begin //Bypass
ramData = data_receive;
end
end
end
localparam clkFrequency = 12500000; //Clock frequency: 25MHz
// localparam clkFrequency = 6250000;
localparam baudRate = 115200; //Baud Rate: 115.2KHz
//Transmitter
async_transmitter #(.ClkFrequency(clkFrequency), .Baud(baudRate)) transmitter(
.clk(clk25),
.TxD_start(serialWrite && !write_busy),
.TxD_data(storeData_i),
.TxD(TxD),
.TxD_busy(write_busy)
);
//Receiver
async_receiver #(.ClkFrequency(clkFrequency), .Baud(baudRate)) receiver(
.clk(clk25),
.RxD(RxD),
.RxD_data_ready(data_ready),
.RxD_data(data_receive)
);
endmodule
|
`timescale 1ns / 1ps
`define FLASH 2'b00
`define READ 2'b01
`define WRITE 2'b10
`define INVALID 2'b11
`define NOP 4'b0000
`define MISS 1'b0
`define HIT 1'b1
`define CACHE_ENABLE 1'b0
`define CACHE_DISABLE 1'b1
`define HALT 1'b1
`define START 1'b0
`define BUS_REQUESTED 1'b1
`define BUS_NOT_REQUESTED 1'b0
`define BUS_GRANTED 1'b1
`define BUS_NOT_GRANTED 1'b0
`define FIFO_FULL 1'b1
`define FIFO_NOT_FULL 1'b0
`define FIFO_EMPTY 1'b1
`define FIFO_NOT_EMPTY 1'b0
`define LOG2(width) (width<=2)?1:\
(width<=4)?2:\
(width<=8)?3:\
(width<=16)?4:\
(width<=32)?5:\
(width<=64)?6:\
(width<=128)?7:\
(width<=256)?8:\
-1
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:54:07 04/08/2015
// Design Name:
// Module Name: inst_decoder
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module processor(
alu_out, alu_carry_output, alu_zero_flag_output, addr_out, bus_request_out, status_out,
vector_in, bus_grant_in, reset_in, fetching, data_in, clk
);
// parameters for the module
parameter CONTROL_WIDTH = 4; // width of the alu control
parameter ADDR_WIDTH = 4; // width of tag/adress for cache access
parameter DATA_WIDTH = 8; // width of data coming from cache
parameter ENTRIES_WIDTH = 4; // # of entries in cache
parameter OPCODE_WIDTH = 2; // width of the opcode
parameter BUFFER_SPACE = 2; // index of the instruction
parameter FIFO_ENTRIES = 2;
parameter EXTRA_BIT_FOR_FIFO = 1;
parameter INSTR_LINE_WIDTH = CONTROL_WIDTH+ADDR_WIDTH+ADDR_WIDTH; // length of the input vector DECODER
parameter CACHE_LINE_WIDTH = OPCODE_WIDTH+ADDR_WIDTH+DATA_WIDTH; // length of the input vector CACHE
parameter ALU_VECTOR_WIDTH = CONTROL_WIDTH+DATA_WIDTH+DATA_WIDTH; // length of the input vector ALU
parameter FIFO_VECTOR_WIDTH = OPCODE_WIDTH+ADDR_WIDTH+EXTRA_BIT_FOR_FIFO; // length of the input vector FIFO
parameter WAIT_FOR_ONE_CYCLE = 0;
parameter ADDRESS_FOR_REQUEST = 1;
parameter L2_FIRST_ACCESS = 2;
parameter L2_FINAL_ACCESS = 3;
parameter CACHE_SWAP_WAIT = 4;
parameter BUS_REQUEST_WAIT = 5;
parameter WAIT_FOR_SECOND_CYCLE = 6;
// outputs of the module
output [DATA_WIDTH-1:0]alu_out; // address out for the L2 access
output alu_carry_output; // carry from ALU
output alu_zero_flag_output; // zero flag ALU
output reg [ADDR_WIDTH-1:0]addr_out; // address out for the L2 access
output reg bus_request_out; // bus request signal
output status_out; // status for the testbench feedback
// inputs of the module
input [INSTR_LINE_WIDTH-1:0]vector_in; // input vector
input bus_grant_in; // bus grant signal
input reset_in; // input reset
input fetching; // input reset
input [DATA_WIDTH-1:0]data_in; // data coming in from L2 cache
input clk; // input clk
// local module variables
//reg [BUFFER_SPACE-1:0]buffer_index; // tag bits for the module obtained from the input vector
//reg [CONTROL_WIDTH-1:0]control_in[BUFFER_SPACE-1:0]; // tag bits for the module obtained from the input vector
//reg [ADDR_WIDTH-1:0]data_addr1[BUFFER_SPACE-1:0]; // 1st data address to be fetched from cache
//reg [ADDR_WIDTH-1:0]data_addr2[BUFFER_SPACE-1:0]; // 2nd data address to be fetched from cache
// local module variables
reg [BUFFER_SPACE-1:0]buffer_index; // tag bits for the module obtained from the input vector
reg [CONTROL_WIDTH-1:0]control_in; // tag bits for the module obtained from the input vector
reg [ADDR_WIDTH-1:0]data_addr1; // 1st data address to be fetched from cache
reg [ADDR_WIDTH-1:0]data_addr2; // 2nd data address to be fetched from cache
// ALU variables
reg [ALU_VECTOR_WIDTH-1:0]ALU_vector_in; // ALU input vector
reg [DATA_WIDTH-1:0]data_alu1[BUFFER_SPACE-1:0];// 1st data fetched from cache to ALU
reg [DATA_WIDTH-1:0]data_alu2[BUFFER_SPACE-1:0];// 2nd data fetched from cache to ALU
// control enable for the cache
reg L1_enable; // L1 enable
// variables for the cache module
wire [DATA_WIDTH-1:0]data_out; // final output of the block
wire hit_miss_out; // outputs the hit/miss of the block
// temporary variables used somewhere
reg [CACHE_LINE_WIDTH-1:0]L1_vector_in; // L1 input vector used in the state machine
reg [DATA_WIDTH-1:0]temp_data_in; // temp data vector for L1 cache
// state machine variables
reg [3:0]state; // current state of the SM
reg [3:0]next_state; // next state for the SM
// fifo variables
wire [ADDR_WIDTH-1:0]instr_fifo_data_out;
wire instr_fifo_empty_flag;
wire instr_fifo_full_flag;
reg [FIFO_VECTOR_WIDTH-1:0]instr_fifo_vector_in;
wire [ADDR_WIDTH-1:0]addr1_fifo_data_out;
wire addr1_fifo_empty_flag;
wire addr1_fifo_full_flag;
reg [FIFO_VECTOR_WIDTH-1:0]addr1_fifo_vector_in;
wire [ADDR_WIDTH-1:0]addr2_fifo_data_out;
wire addr2_fifo_empty_flag;
wire addr2_fifo_full_flag;
reg [FIFO_VECTOR_WIDTH-1:0]addr2_fifo_vector_in;
reg [ADDR_WIDTH-1:0]instr_fifo_flag;
reg [ADDR_WIDTH-1:0]addr2_fifo_flag;
reg [ADDR_WIDTH-1:0]addr1_fifo_flag;
reg extra_bit_flag;
cache #(ADDR_WIDTH,DATA_WIDTH,ENTRIES_WIDTH) L1 (
.data_out(data_out), .hit_miss_out(hit_miss_out), .vector_in(L1_vector_in),
.enable(L1_enable), .reset(reset_in), .clk(clk)
);
alu #(CONTROL_WIDTH,DATA_WIDTH) alu (
.final_output(alu_out), .carry_output(alu_carry_output), .zero_flag(alu_zero_flag_output),
.opcode_inputs(ALU_vector_in), .reset_in(reset_in), .clk(clk)
);
fifo #(ADDR_WIDTH, FIFO_ENTRIES) instr_fifo (
.data_out(instr_fifo_data_out), .empty_flag(instr_fifo_empty_flag), .full_flag(status_out),
.vector_in(instr_fifo_vector_in), .reset(reset_in), .clk(clk)
);
fifo #(ADDR_WIDTH, FIFO_ENTRIES) addr1_fifo (
.data_out(addr1_fifo_data_out), .empty_flag(addr1_fifo_empty_flag), .full_flag(addr1_fifo_full_flag),
.vector_in(addr1_fifo_vector_in), .reset(reset_in), .clk(clk)
);
fifo #(ADDR_WIDTH, FIFO_ENTRIES) addr2_fifo (
.data_out(addr2_fifo_data_out), .empty_flag(addr2_fifo_empty_flag), .full_flag(addr2_fifo_full_flag),
.vector_in(addr2_fifo_vector_in), .reset(reset_in), .clk(clk)
);
always @(posedge clk)
begin
if (reset_in)
begin
state = WAIT_FOR_ONE_CYCLE;
L1_vector_in = {`INVALID,4'b0,8'b0};
L1_enable = `CACHE_DISABLE;
temp_data_in = {DATA_WIDTH{1'b0}};
// alu_out = {DATA_WIDTH-1{1'b0}};
buffer_index = {BUFFER_SPACE{1'b0}};
bus_request_out = `BUS_NOT_REQUESTED;
// status_out = `START;
ALU_vector_in = {`NOP,data_alu1[0],data_alu2[0]};
instr_fifo_flag = 4'b0;
addr1_fifo_flag = 4'b0;
addr2_fifo_flag = 4'b0;
extra_bit_flag = 1'b0;
control_in = 4'b0;
data_addr1 = 4'b0;
data_addr2 = 4'b0;
end else
begin
if(fetching) begin
if(instr_fifo_empty_flag == `FIFO_EMPTY && status_out != `HALT)
// if(status_out == `START)
begin
control_in = vector_in[INSTR_LINE_WIDTH-1:INSTR_LINE_WIDTH-CONTROL_WIDTH];
instr_fifo_vector_in = {`WRITE,control_in,extra_bit_flag};
// $display("control_in:%d ",control_in);
end
// else
// status_out = `HALT;
if(addr1_fifo_empty_flag == `FIFO_EMPTY && addr2_fifo_empty_flag == `FIFO_EMPTY && status_out != `HALT)
// if(status_out == `START)
begin
data_addr1 = vector_in[INSTR_LINE_WIDTH-CONTROL_WIDTH-1:INSTR_LINE_WIDTH-CONTROL_WIDTH-ADDR_WIDTH];
addr1_fifo_vector_in = {`WRITE,data_addr1,extra_bit_flag};
data_addr2 = vector_in[INSTR_LINE_WIDTH-CONTROL_WIDTH-ADDR_WIDTH-1:INSTR_LINE_WIDTH-CONTROL_WIDTH-ADDR_WIDTH-ADDR_WIDTH];
addr2_fifo_vector_in = {`WRITE,data_addr2,extra_bit_flag};
// $display("data_addr1:%d, data_addr2:%d ",data_addr1,data_addr2);
// @(posedge clk);
// status_out = `HALT;
// addr1_fifo_vector_in = {2'b00,data_addr2};
// addr2_fifo_vector_in = {2'b00,data_addr2};
end
end
// else
// status_out = `HALT;
/*
control_in[buffer_index] = vector_in[INSTR_LINE_WIDTH-1:INSTR_LINE_WIDTH-CONTROL_WIDTH];
if(buffer_index < BUFFER_SPACE - 2)
begin
data_addr1[buffer_index] = vector_in[INSTR_LINE_WIDTH-CONTROL_WIDTH-1:INSTR_LINE_WIDTH-CONTROL_WIDTH-ADDR_WIDTH];
data_addr2[buffer_index] = vector_in[INSTR_LINE_WIDTH-CONTROL_WIDTH-ADDR_WIDTH-1:INSTR_LINE_WIDTH-CONTROL_WIDTH-ADDR_WIDTH-ADDR_WIDTH];
end
$display("buffer_index:%d, control: %d,data_addr1: %d,data_addr2: %d",buffer_index, control_in[buffer_index], data_addr1[buffer_index], data_addr2[buffer_index]);
buffer_index = buffer_index + 1;
*/
case(state)
/*
L1_CACHE_ACCESS:
begin
$display("L1_CACHE_ACCESS");
L1_enable = `CACHE_ENABLE;
L1_vector_in = {`READ,data_addr1[0],temp_data_in};
status_out = `HALT;
next_state = L1_ACCESS_CHECK;
end
L1_ACCESS_CHECK:
begin
@(posedge clk);
$display("data_out:%d, hit_miss_out:%d",data_out,hit_miss_out);
if(hit_miss_out == `MISS)
begin
L1_enable = `CACHE_DISABLE;
status_out = `HALT;
bus_request_out = `BUS_REQUESTED;
next_state = BUS_REQUEST_WAIT;
end
end
*/
WAIT_FOR_ONE_CYCLE:
begin
next_state = WAIT_FOR_SECOND_CYCLE;
end
WAIT_FOR_SECOND_CYCLE:
begin
next_state = ADDRESS_FOR_REQUEST;
end
ADDRESS_FOR_REQUEST:
begin
// $display("GETTING THE ADDRESS");
// bus being requested
bus_request_out = `BUS_REQUESTED;
// address for the L2 request being read out from the fifo
addr1_fifo_vector_in = {`READ,addr1_fifo_flag,extra_bit_flag};
addr1_fifo_flag = addr1_fifo_flag + 4'b1;
// feedback for the testbench
// status_out = `HALT;
next_state = BUS_REQUEST_WAIT;
end
BUS_REQUEST_WAIT:
begin
// $display("WAITING FOR BUS");
if(bus_grant_in == `BUS_GRANTED)
begin
// address for the L2 request from arrived from the fifo
addr_out = addr1_fifo_data_out;
// $display("addr_out:%d", addr_out);
// address for the L2 request being read out from the fifo
addr2_fifo_vector_in = {`READ,addr2_fifo_flag,extra_bit_flag};
addr2_fifo_flag = addr2_fifo_flag + 4'b1;
// instruction being read out from the fifo for the alu operation
instr_fifo_vector_in = {`READ,instr_fifo_flag,extra_bit_flag};
instr_fifo_flag = instr_fifo_flag + 4'b1;
next_state = L2_FIRST_ACCESS;
// $display("BUS GRANTED");
end
end
L2_FIRST_ACCESS:
begin
// $display("L2_FIRST_ACCESS");
// data should have arrived in the clock cycle
data_alu1[0] = data_in;
// send the second access address
addr_out = addr2_fifo_data_out;
next_state = L2_FINAL_ACCESS;
// $display("data_alu1[0]:%d, addr_out:%d", data_alu1[0],addr_out);
end
L2_FINAL_ACCESS:
begin
// $display("L2_FINAL_ACCESS");
// get the second data
data_alu1[1] = data_in;
// also start new decoding
// status_out = `START;
// start the alu process
ALU_vector_in = {instr_fifo_data_out,data_alu1[0],data_alu1[1]};
// start the buffer_index from 0
// buffer_index = {BUFFER_SPACE-1{1'b0}};
// bus request removed
bus_request_out = `BUS_NOT_REQUESTED;
// go back to the start for the l1 cache access
next_state = WAIT_FOR_ONE_CYCLE;
// $display("data_alu1[1]:%d, control_in:%d", data_alu1[1],instr_fifo_data_out);
end
default: $display("WRONG PLACE DUDE");
endcase
state = next_state;
extra_bit_flag = extra_bit_flag + 1'b1;
end
end
endmodule
|
`include "../../../rtl/verilog/gfx/gfx_blender.v"
`include "../../../rtl/verilog/gfx/gfx_color.v"
module blender_bench();
reg clk_i;
reg rst_i;
reg blending_enable_i;
reg [31:2] target_base_i;
reg [15:0] target_size_x_i;
reg [15:0] target_size_y_i;
reg [1:0] color_depth_i;
// from fragment
reg [15:0] x_counter_i;
reg [15:0] y_counter_i;
reg signed [15:0] z_i;
reg [7:0] global_alpha_i;
reg [7:0] alpha_i;
reg [31:0] pixel_color_i;
reg write_i;
reg ack_i;
// Wbm
reg target_ack_i;
wire [31:2] target_addr_o;
reg [31:0] target_data_i;
wire [3:0] target_sel_o;
wire target_request_o;
reg wbm_busy_i;
//to render
wire [15:0] pixel_x_o;
wire [15:0] pixel_y_o;
wire [31:0] pixel_color_o;
wire write_o;
wire ack_o;
initial begin
$dumpfile("blender.vcd");
$dumpvars(0,blender_bench);
// init values
clk_i = 0;
rst_i = 1;
write_i = 0;
blending_enable_i = 0;
alpha_i = 8'h80;
global_alpha_i = 8'hff;
x_counter_i = 0;
y_counter_i = 0;
z_i = 10;
wbm_busy_i = 0;
color_depth_i = 2'b01; // 16 bit
target_base_i = 32'h01f00000;
target_size_x_i = 12;
target_size_y_i = 10;
pixel_color_i = 32'h00001234;
target_data_i = 32'h00000000;
ack_i = 0;
//timing
#4 rst_i = 0;
#4 write_i = 1;
#2 write_i = 0;
#10 pixel_color_i = 32'h00005678;
#10 pixel_color_i = 32'h00009abc;
#10 pixel_color_i = 32'h0000f800;
// end sim
#100 $finish;
end
always @(posedge clk_i)
begin
ack_i <= #1 write_o;
target_ack_i <= #1 target_request_o;
end
always begin
#1 clk_i = ~clk_i;
end
gfx_blender blender(
.clk_i (clk_i),
.rst_i (rst_i),
.blending_enable_i(blending_enable_i),
.target_base_i (target_base_i),
.target_size_x_i (target_size_x_i),
.target_size_y_i (target_size_y_i),
.color_depth_i (color_depth_i),
.x_counter_i (x_counter_i),
.y_counter_i (y_counter_i),
.z_i (z_i),
.alpha_i (alpha_i),
.global_alpha_i (global_alpha_i),
.pixel_color_i (pixel_color_i),
.write_i (write_i),
.ack_i (ack_i),
.target_ack_i (target_ack_i),
.target_addr_o (target_addr_o),
.target_data_i (target_data_i),
.target_sel_o (target_sel_o),
.target_request_o (target_request_o),
.wbm_busy_i (wbm_busy_i),
.pixel_x_o (pixel_x_o),
.pixel_y_o (pixel_y_o),
.pixel_color_o (pixel_color_o),
.write_o (write_o),
.ack_o (ack_o)
);
endmodule
|
/*
* Titor - Butterfly Unit - Does multiple bit manipulations for the titor processor
* Copyright (C) 2012 Sean Ryan Moore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`ifdef INC_BUTTERFLY_UNIT
`else
`define INC_BUTTERFLY_UNIT
`timescale 1 ns / 100 ps
// The top level which carries out these operations
module Butterfly_Unit (
result,
operand,
amount,
shift_type,
opcode
);
`include "definition/Definition.v"
output reg [WORD-1:0] result;
input [WORD-1:0] operand;
input [WORD-1:0] amount;
input [WORD-1:0] shift_type;
input [WORD-1:0] opcode;
wire [((WORD/2)*LOGWORD)-1:0] control_rotate;
wire [((WORD/2)*LOGWORD)-1:0] control_swap;
wire [(WORD/2)-1:0] control_const [LOGWORD-1:0]; // control for 1 bit strings
wire [(WORD/2)-1:0] control_exp [LOGWORD-1:0]; // control for exponential strings
wire [(WORD/2)-1:0] control_array [LOGWORD-1:0]; // control for full array
wire [((WORD/2)*LOGWORD)-1:0] control_bfly; // control input to inverse butterfly
wire [WORD-1:0] emit;
wire [WORD-1:0] mask;
wire [WORD-1:0] rotor;
genvar i;
genvar j;
generate
for(i=0; i<LOGWORD; i=i+1) begin : GEN_CONTROL
assign control_const[i] = control_swap[(i+1)*(WORD/2)-1:(i*(WORD/2))];
assign control_exp[i] = (shift_type==TYPE_CONST) ? {(1<<i){control_const[i][0]}} : control_rotate[((i+1)*(WORD/2))-1:(i*(WORD/2))];
assign control_array[i] = {((WORD/2)/(1<<i)){control_exp[i][(1<<i)-1:0]}} ;
assign control_bfly[((i+1)*WORD/2)-1:((i+0)*WORD/2)] = control_array[i];
end
endgenerate
InvButterfly datapath (
.outword(rotor),
.inword(operand),
.control(control_bfly)
);
RotateControl controlpath (
.emit(emit),
.control(control_rotate),
.rotate(amount)
);
generate
for(i=0; i<LOGWORD; i=i+1) begin : GEN_SWAP
assign control_swap[i*(WORD/2)] = amount[i];
end
endgenerate
assign mask = (&amount[WORD-1:LOGWORD]) || (&(~amount[WORD-1:LOGWORD])) ? emit : {WORD{1'b1}};
// either the sign extends or the number is too large
// if the number is too large the mask gets saturated
always @(*) begin
case(shift_type)
TYPE_CONST: result <= rotor;
TYPE_EXP:
case(opcode)
SHIFT_LOGICAL: result <= rotor & ~mask;
SHIFT_ANTILOGICAL: result <= rotor | mask;
SHIFT_ARITHMETIC: result <= amount[WORD-1] ?
(rotor & (~mask)) | ({WORD{operand[ 0]}} & mask) : // shift left
(rotor & (~mask)) | ({WORD{operand[WORD-1]}} & mask) ; // shift right
SHIFT_CIRCULAR: result <= rotor;
default: result <= rotor;
endcase
default: result <= rotor;
endcase
end
endmodule
// The heart of the datapath which performs the bit manipulations indicated by control lines
module InvButterfly (
outword,
inword,
control
);
`include "definition/Definition.v"
output [WORD-1:0] outword;
input [WORD-1:0] inword;
input [((WORD/2)*LOGWORD)-1:0] control;
Lepid #(.stage(LOGWORD-1), .child(0)) root (
.outword(outword),
.inword(inword),
.control(control)
);
endmodule
// Recursively contructed datapath which goes into InvButterfly
module Lepid (
outword,
inword,
control
);
`include "definition/Definition.v"
parameter stage = 0; // stage is which in the sequence of Lepid modules this one is
parameter child = 0; // which part of the branch is this child
localparam PART = 1<<stage; // short for partner/partition offset
localparam OFFS = child*PART; // the offset between partnered muxes
output reg [2*PART-1:0] outword;
input [2*PART-1:0] inword;
input [(LOGWORD*WORD/2)-1:0] control; // total control array
wire [WORD/2-1:0] control_a; // level extracted control bits
wire [PART-1:0] minget; // output from maxchild
wire [PART-1:0] maxget; // output from minchild
assign control_a = control[((stage+1)*(WORD/2))-1:(stage*(WORD/2))]; // extract a piece of the control array
genvar i;
generate
if(stage==0) begin
assign maxget = inword[1];
assign minget = inword[0];
end
else begin
Lepid #(.stage(stage-1), .child(2*child+0)) minchild(
.outword(minget),
.inword(inword[PART-1:0]),
.control(control)
);
Lepid #(.stage(stage-1), .child(2*child+1)) maxchild(
.outword(maxget),
.inword(inword[2*PART-1:PART]),
.control(control)
);
end
for(i=0; i<PART; i=i+1) begin : GEN_OUTWORD
always @(*) begin
outword[i+0 ] <= control_a[i+OFFS] ? maxget[i] : minget[i];
outword[i+PART] <= control_a[i+OFFS] ? minget[i] : maxget[i];
end
end
endgenerate
endmodule
// Generates the control bits necessary to perform a rotate
module RotateControl (
emit,
control,
rotate
);
`include "definition/Definition.v"
output wire [WORD-1:0] emit;
output wire [((WORD/2)*LOGWORD)-1:0] control;
input [WORD-1:0] rotate;
wire [WORD-1:0] control_a [LOGWORD-1:0];
wire [WORD-1:0] feedword [LOGWORD+1:0];
assign feedword[0] = 0;
genvar i;
generate
for(i=0; i<LOGWORD; i=i+1) begin : GEN_CONTROL
assign control[((i+1)*(WORD/2))-1:(i*(WORD/2))] = control_a[i]; // serialize the control array
end
endgenerate
generate
for(i=0; i<LOGWORD; i=i+1) begin : GEN_ROTATELINE
RotateLine #(.stage(i)) unitLine (
.cb(control_a[i]),
.feedout(feedword[i+1]),
.feedin(feedword[i]),
.rotate(rotate)
);
end
endgenerate
RotateLine #(.stage(LOGWORD)) unitLine (
.cb(emit),
.feedout(feedword[LOGWORD+1]),
.feedin(feedword[LOGWORD]),
.rotate(rotate)
);
endmodule
// Generates the control bits for a rotation stage by stage
module RotateLine (
cb,
feedout,
feedin,
rotate
);
`include "definition/Definition.v"
parameter stage = 0; // stage is which in the sequence of Lepid modules this one is
localparam HSTRING = 1<<((stage==0)?1:stage-1); // the width of the string in this stage
localparam SSTRING = stage==0 ? 1 : HSTRING; // compiler-safe half string width
output reg [WORD-1:0] cb;
output reg [WORD-1:0] feedout;
input [WORD-1:0] feedin;
input [WORD-1:0] rotate;
reg [WORD-1:0] thermo;
reg [WORD-1:0] piezo;
always @(*) begin
cb <= feedout[(1<<stage)-1:0] ^ thermo[(1<<stage)-1:0] ;
thermo <= {WORD{rotate[stage]}};
end
generate
if(stage == 0) begin
initial begin
piezo <= 0;
feedout <= 0;
end
end else begin
always @(*) begin
piezo <= {WORD{rotate[stage-1]}};
feedout <= { feedin[SSTRING-1:0] | piezo[SSTRING-1:0] , feedin[SSTRING-1:0] & piezo[SSTRING-1:0] };
end
end
endgenerate
endmodule
`endif
|
`timescale 1ns / 1ps
module eth_if #(
parameter MY_MAC = 48'h00_AA_BB_CC_DD_EE,
parameter MY_IP = {8'd10, 8'd5, 8'd5, 8'd5},
parameter DEST_MAC = 48'h30_85_A9_13_05_32,
parameter DEST_IP = {8'd10, 8'd5, 8'd5, 8'd1}
) (
input wire rst,
input wire clk_200,
input wire GTX_CLK,
output wire ETH_RESET,
output wire [7:0] GMII_TXD,
output wire GMII_TX_EN,
output wire GMII_TX_ER,
output wire GMII_TX_CLK,
input wire [7:0] GMII_RXD,
input wire GMII_RX_DV,
input wire GMII_RX_ER,
input wire GMII_RX_CLK,
input wire MII_TX_CLK,
input wire GMII_COL,
input wire GMII_CRS,
output wire udp_rx_clk,
output wire [7:0] udp_rx,
output wire udp_rx_dv,
input wire [15: 0] udp_tx_pending_data,
output wire udp_tx_clk,
input wire [7:0] udp_tx,
output wire udp_tx_rden
);
(* KEEP_HIERARCHY="TRUE" *)
wire tx_clk;
wire rx_clk;
assign ETH_RESET = 1'b1; // active lo
assign udp_rx_clk = rx_clk;
assign udp_tx_clk = tx_clk;
wire [7:0] emac0_rx_data;
wire emac0_rx_data_valid;
wire emac0_rx_data_goodframe;
wire emac0_rx_data_badframe;
wire [7:0] emac0_tx_data;
wire emac0_tx_data_valid;
wire emac0_tx_data_ack;
wire gmii_rx_clk_delay;
ethmac_block emac_block_inst (
// EMAC0 Clocking
// TX Clock output from EMAC
.TX_CLK_OUT (),
// EMAC0 TX Clock input from BUFG
.TX_CLK_0 (tx_clk),
// Client Receiver Interface - EMAC0
.EMAC0CLIENTRXD (emac0_rx_data),
.EMAC0CLIENTRXDVLD (emac0_rx_data_valid),
.EMAC0CLIENTRXGOODFRAME (emac0_rx_data_goodframe),
.EMAC0CLIENTRXBADFRAME (emac0_rx_data_badframe),
.EMAC0CLIENTRXFRAMEDROP (),
.EMAC0CLIENTRXSTATS (),
.EMAC0CLIENTRXSTATSVLD (),
.EMAC0CLIENTRXSTATSBYTEVLD (),
// Client Transmitter Interface - EMAC0
.CLIENTEMAC0TXD (emac0_tx_data),
.CLIENTEMAC0TXDVLD (emac0_tx_data_valid),
.EMAC0CLIENTTXACK (emac0_tx_data_ack),
.CLIENTEMAC0TXFIRSTBYTE (1'b0),
.CLIENTEMAC0TXUNDERRUN (1'b0),
.EMAC0CLIENTTXCOLLISION (),
.EMAC0CLIENTTXRETRANSMIT (),
.CLIENTEMAC0TXIFGDELAY (8'h00),
.EMAC0CLIENTTXSTATS (),
.EMAC0CLIENTTXSTATSVLD (),
.EMAC0CLIENTTXSTATSBYTEVLD (),
// MAC Control Interface - EMAC0
.CLIENTEMAC0PAUSEREQ (0),
.CLIENTEMAC0PAUSEVAL (0),
// Clock Signal - EMAC0
.GTX_CLK_0(1'b0),
// GMII Interface - EMAC0
.GMII_TXD_0 (GMII_TXD),
.GMII_TX_EN_0 (GMII_TX_EN),
.GMII_TX_ER_0 (GMII_TX_ER),
.GMII_TX_CLK_0 (GMII_TX_CLK),
.GMII_RXD_0 (GMII_RXD),
.GMII_RX_DV_0 (GMII_RX_DV),
.GMII_RX_ER_0 (GMII_RX_ER),
.GMII_RX_CLK_0 (rx_clk),
.RESET(rst)
);
IDELAYCTRL dlyctrl0 (
.RDY(),
.REFCLK(clk_200),
.RST(rst)
);
BUFG bufg_tx (.I(gtx_clk_i), .O(tx_clk));
IBUF gtx_clk0_ibuf (.I(GTX_CLK), .O(gtx_clk_i));
BUFG bufg_rx (.I(gmii_rx_clk_delay), .O(rx_clk));
IODELAY gmii_rxc0_delay (
.IDATAIN(GMII_RX_CLK),
.ODATAIN(1'b0),
.DATAOUT(gmii_rx_clk_delay),
.DATAIN(1'b0),
.C(1'b0),
.T(1'b0),
.CE(1'b0),
.INC(1'b0),
.RST(1'b0)
);
defparam gmii_rxc0_delay.IDELAY_TYPE = "FIXED";
defparam gmii_rxc0_delay.IDELAY_VALUE = 0;
defparam gmii_rxc0_delay.DELAY_SRC = "I";
defparam gmii_rxc0_delay.SIGNAL_PATTERN = "CLOCK";
ip_minimal #(
.MY_MAC(MY_MAC),
.MY_IP(MY_IP),
.DEST_MAC(DEST_MAC),
.DEST_IP(DEST_IP)
) ipcore (
.eth_tx_clk(tx_clk),
.eth_tx_data(emac0_tx_data),
.eth_tx_data_en(emac0_tx_data_valid),
.eth_tx_ack(emac0_tx_data_ack),
.eth_rx_clk(rx_clk),
.eth_rx_data(emac0_rx_data),
.eth_rx_data_valid(emac0_rx_data_valid),
.eth_rx_frame_good(emac0_rx_data_goodframe),
.eth_rx_frame_bad(emac0_rx_data_badframe),
.udp_rx(udp_rx),
.udp_rx_dv(udp_rx_dv),
.udp_tx_pending_data(udp_tx_pending_data),
.udp_tx(udp_tx),
.udp_tx_rden(udp_tx_rden)
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_ifu_invctl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
///////////////////////////////////////////////////////////////////////
/*
// Module Name: sparc_ifu_invctl
// Description:
// Control logic for handling invalidations to the icache
//
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "iop.h"
`include "ifu.h"
module sparc_ifu_invctl(/*AUTOARG*/
// Outputs
so, inv_ifc_inv_pending, ifq_icv_wrindex_bf, ifq_icv_wren_bf,
ifq_ict_dec_wrway_bf, ifq_fcl_invreq_bf, ifq_erb_asiway_f,
// Inputs
rclk, se, si, const_cpuid, mbist_icache_write,
lsu_ifu_ld_icache_index, lsu_ifu_ld_pcxpkt_vld,
lsu_ifu_ld_pcxpkt_tid, ifc_inv_ifqadv_i2, ifc_inv_asireq_i2,
ifq_icd_index_bf, ifd_inv_ifqop_i2, ifd_inv_wrway_i2
);
input rclk,
se,
si;
input [2:0] const_cpuid;
input mbist_icache_write;
input [`IC_IDX_HI:5] lsu_ifu_ld_icache_index;
input lsu_ifu_ld_pcxpkt_vld;
input [1:0] lsu_ifu_ld_pcxpkt_tid;
input ifc_inv_ifqadv_i2;
input ifc_inv_asireq_i2;
input [`IC_IDX_HI:5] ifq_icd_index_bf;
input [`CPX_WIDTH-1:0] ifd_inv_ifqop_i2;
input [1:0] ifd_inv_wrway_i2;
output so;
output inv_ifc_inv_pending;
output [`IC_IDX_HI:5] ifq_icv_wrindex_bf;
output [15:0] ifq_icv_wren_bf;
output [3:0] ifq_ict_dec_wrway_bf;
output ifq_fcl_invreq_bf;
output [1:0] ifq_erb_asiway_f;
//----------------------------------------------------------------------
// Local Signals
//----------------------------------------------------------------------
wire [3:0] cpu_sel,
invcpu21_sel_i2;
wire invcpu0_sel_i2;
wire [1:0] inv_vec0,
inv_vec1;
wire [1:0] inv_way0_p1_i2,
inv_way0_p0_i2,
inv_way1_p1_i2,
inv_way1_p0_i2,
invwd0_way_i2,
invwd1_way_i2,
inv0_way_i2,
inv1_way_i2;
wire [1:0] asi_way_f;
wire word0_inv_i2,
word1_inv_i2;
wire ldinv_i2,
ldpkt_i2,
evpkt_i2,
stpkt_i2,
strmack_i2,
imissrtn_i2;
wire invreq_i2,
invalidate_i2,
invalidate_f;
wire invall_i2,
invpa5_i2;
wire [1:0] cpxthrid_i2;
wire [3:0] dcpxthr_i2;
wire [1:0] ldinv_way_i2;
wire [1:0] w0_way_i2,
w1_way_i2,
w0_way_f,
w1_way_f;
wire pick_wr;
wire icv_wrreq_i2;
wire [3:0] wrt_en_wd_i2,
wrt_en_wd_bf,
wrt_en_wd_f;
wire [3:0] w0_dec_way_i2,
w1_dec_way_i2;
wire [3:0] dec_wrway;
wire icvidx_sel_wr_i2,
icvidx_sel_ld_i2,
icvidx_sel_inv_i2;
wire [15:0] wren_i2;
wire [`IC_IDX_HI:6] inv_addr_i2;
wire [`IC_IDX_HI:5] icaddr_i2;
wire missaddr5_i2;
wire missaddr6_i2;
wire [3:0] ldthr,
ldidx_sel_new;
wire [`IC_IDX_HI:5] ldinv_addr_i2,
ldindex0,
ldindex1,
ldindex2,
ldindex3,
ldindex0_nxt,
ldindex1_nxt,
ldindex2_nxt,
ldindex3_nxt;
wire clk;
//
// Code Begins Here
//
assign clk = rclk;
//----------------------------------------------------------------------
// Extract Invalidate Packet For This Core
//----------------------------------------------------------------------
// mux the invalidate vector down to get this processors inv vector
// First ecode cpu id
assign cpu_sel[0] = ~const_cpuid[2] & ~const_cpuid[1];
assign cpu_sel[1] = ~const_cpuid[2] & const_cpuid[1];
assign cpu_sel[2] = const_cpuid[2] & ~const_cpuid[1];
assign cpu_sel[3] = const_cpuid[2] & const_cpuid[1];
// 4:1 follwed by 2:1 to get 8:1, to get invalidate way selects
assign invcpu21_sel_i2 = cpu_sel;
assign invcpu0_sel_i2 = const_cpuid[0];
// First do word 0 for even processors
mux4ds #(1) v0p0_mux(.dout (inv_vec0[0]),
.in0 (ifd_inv_ifqop_i2[1]),
.in1 (ifd_inv_ifqop_i2[9]),
.in2 (ifd_inv_ifqop_i2[17]),
.in3 (ifd_inv_ifqop_i2[25]),
.sel0 (invcpu21_sel_i2[0]),
.sel1 (invcpu21_sel_i2[1]),
.sel2 (invcpu21_sel_i2[2]),
.sel3 (invcpu21_sel_i2[3]));
mux4ds #(2) w0p0_mux(.dout (inv_way0_p0_i2[1:0]),
.in0 (ifd_inv_ifqop_i2[3:2]),
.in1 (ifd_inv_ifqop_i2[11:10]),
.in2 (ifd_inv_ifqop_i2[19:18]),
.in3 (ifd_inv_ifqop_i2[27:26]),
.sel0 (invcpu21_sel_i2[0]),
.sel1 (invcpu21_sel_i2[1]),
.sel2 (invcpu21_sel_i2[2]),
.sel3 (invcpu21_sel_i2[3]));
// word 0 for odd processors
mux4ds #(1) v0p1_mux(.dout (inv_vec0[1]),
.in0 (ifd_inv_ifqop_i2[5]),
.in1 (ifd_inv_ifqop_i2[13]),
.in2 (ifd_inv_ifqop_i2[21]),
.in3 (ifd_inv_ifqop_i2[29]),
.sel0 (invcpu21_sel_i2[0]),
.sel1 (invcpu21_sel_i2[1]),
.sel2 (invcpu21_sel_i2[2]),
.sel3 (invcpu21_sel_i2[3]));
mux4ds #(2) w0p1_mux(.dout (inv_way0_p1_i2[1:0]),
.in0 (ifd_inv_ifqop_i2[7:6]),
.in1 (ifd_inv_ifqop_i2[15:14]),
.in2 (ifd_inv_ifqop_i2[23:22]),
.in3 (ifd_inv_ifqop_i2[31:30]),
.sel0 (invcpu21_sel_i2[0]),
.sel1 (invcpu21_sel_i2[1]),
.sel2 (invcpu21_sel_i2[2]),
.sel3 (invcpu21_sel_i2[3]));
// Word 1
// word 1 for even processors
mux4ds #(1) v1p0_mux(.dout (inv_vec1[0]),
.in0 (ifd_inv_ifqop_i2[57]),
.in1 (ifd_inv_ifqop_i2[65]),
.in2 (ifd_inv_ifqop_i2[73]),
.in3 (ifd_inv_ifqop_i2[81]),
.sel0 (invcpu21_sel_i2[0]),
.sel1 (invcpu21_sel_i2[1]),
.sel2 (invcpu21_sel_i2[2]),
.sel3 (invcpu21_sel_i2[3]));
mux4ds #(2) w1p0_mux(.dout (inv_way1_p0_i2[1:0]),
.in0 (ifd_inv_ifqop_i2[59:58]),
.in1 (ifd_inv_ifqop_i2[67:66]),
.in2 (ifd_inv_ifqop_i2[75:74]),
.in3 (ifd_inv_ifqop_i2[83:82]),
.sel0 (invcpu21_sel_i2[0]),
.sel1 (invcpu21_sel_i2[1]),
.sel2 (invcpu21_sel_i2[2]),
.sel3 (invcpu21_sel_i2[3]));
// word 1 for odd processors
mux4ds #(1) inv_v1p1_mux(.dout (inv_vec1[1]),
.in0 (ifd_inv_ifqop_i2[61]),
.in1 (ifd_inv_ifqop_i2[69]),
.in2 (ifd_inv_ifqop_i2[77]),
.in3 (ifd_inv_ifqop_i2[85]),
.sel0 (invcpu21_sel_i2[0]),
.sel1 (invcpu21_sel_i2[1]),
.sel2 (invcpu21_sel_i2[2]),
.sel3 (invcpu21_sel_i2[3]));
mux4ds #(2) w1p1_mux(.dout (inv_way1_p1_i2[1:0]),
.in0 (ifd_inv_ifqop_i2[63:62]),
.in1 (ifd_inv_ifqop_i2[71:70]),
.in2 (ifd_inv_ifqop_i2[79:78]),
.in3 (ifd_inv_ifqop_i2[87:86]),
.sel0 (invcpu21_sel_i2[0]),
.sel1 (invcpu21_sel_i2[1]),
.sel2 (invcpu21_sel_i2[2]),
.sel3 (invcpu21_sel_i2[3]));
// Mux odd and even values down to a single value for word0 and word1
// dp_mux2es #(1) v0_mux (.dout (word0_inv_i2),
// .in0 (inv_vec0[0]),
// .in1 (inv_vec0[1]),
// .sel (invcpu0_sel_i2));
assign word0_inv_i2 = invcpu0_sel_i2 ? inv_vec0[1] : inv_vec0[0];
// dp_mux2es #(2) w0_mux (.dout (invwd0_way_i2[1:0]),
// .in0 (inv_way0_p0_i2[1:0]),
// .in1 (inv_way0_p1_i2[1:0]),
// .sel (invcpu0_sel_i2));
assign invwd0_way_i2 = invcpu0_sel_i2 ? inv_way0_p1_i2[1:0] :
inv_way0_p0_i2[1:0];
// word1
// dp_mux2es #(1) v1_mux (.dout (word1_inv_i2),
// .in0 (inv_vec1[0]),
// .in1 (inv_vec1[1]),
// .sel (invcpu0_sel_i2));
assign word1_inv_i2 = invcpu0_sel_i2 ? inv_vec1[1] : inv_vec1[0];
// dp_mux2es #(2) w1_mux (.dout (invwd1_way_i2[1:0]),
// .in0 (inv_way1_p0_i2[1:0]),
// .in1 (inv_way1_p1_i2[1:0]),
// .sel (invcpu0_sel_i2));
assign invwd1_way_i2 = invcpu0_sel_i2 ? inv_way1_p1_i2[1:0] :
inv_way1_p0_i2[1:0];
//-----------------------------
// Decode CPX Packet
//-----------------------------
// load
assign ldpkt_i2 = ({ifd_inv_ifqop_i2[`CPX_VLD],
ifd_inv_ifqop_i2[`CPX_REQFIELD]} == `CPX_LDPKT) ?
1'b1 : 1'b0;
assign ldinv_i2 = ldpkt_i2 & ifd_inv_ifqop_i2[`CPX_WYVLD];
assign ldinv_way_i2= ifd_inv_ifqop_i2[`CPX_WY_HI:`CPX_WY_LO];
// ifill
assign imissrtn_i2 = ({ifd_inv_ifqop_i2[`CPX_VLD],
ifd_inv_ifqop_i2[`CPX_REQFIELD]} == `CPX_IFILLPKT) ?
1'b1 : 1'b0;
// store ack
assign stpkt_i2 = ({ifd_inv_ifqop_i2[`CPX_VLD],
ifd_inv_ifqop_i2[`CPX_REQFIELD]} == `CPX_STRPKT) ?
1'b1 : 1'b0;
assign strmack_i2 = ({ifd_inv_ifqop_i2[`CPX_VLD],
ifd_inv_ifqop_i2[`CPX_REQFIELD]} == `CPX_STRMACK) ?
1'b1 : 1'b0;
assign invall_i2 = stpkt_i2 & ifd_inv_ifqop_i2[`CPX_IINV] &
ifc_inv_ifqadv_i2;
assign invpa5_i2 = ifd_inv_ifqop_i2[`CPX_INVPA5];
// evict
assign evpkt_i2 = ({ifd_inv_ifqop_i2[`CPX_VLD],
ifd_inv_ifqop_i2[`CPX_REQFIELD]} == `CPX_EVPKT) ?
1'b1 : 1'b0;
// get thread id and decode
assign cpxthrid_i2 = ifd_inv_ifqop_i2[`CPX_THRFIELD];
assign dcpxthr_i2[0] = ~cpxthrid_i2[1] & ~cpxthrid_i2[0];
assign dcpxthr_i2[1] = ~cpxthrid_i2[1] & cpxthrid_i2[0];
assign dcpxthr_i2[2] = cpxthrid_i2[1] & ~cpxthrid_i2[0];
assign dcpxthr_i2[3] = cpxthrid_i2[1] & cpxthrid_i2[0];
//-----------------------------------------------
// Generate Write Way and Write Enables
//-----------------------------------------------
// decode way for tags
assign dec_wrway[0] = ~ifd_inv_wrway_i2[1] & ~ifd_inv_wrway_i2[0];
assign dec_wrway[1] = ~ifd_inv_wrway_i2[1] & ifd_inv_wrway_i2[0];
assign dec_wrway[2] = ifd_inv_wrway_i2[1] & ~ifd_inv_wrway_i2[0];
assign dec_wrway[3] = ifd_inv_wrway_i2[1] & ifd_inv_wrway_i2[0];
assign ifq_ict_dec_wrway_bf = dec_wrway;
// way for asi
dff_s #(2) asiwayf_reg(.din (ifd_inv_wrway_i2),
.q (asi_way_f),
.clk (clk), .se(se), .si(), .so());
assign ifq_erb_asiway_f = asi_way_f;
// Select which index/way to invalidate
assign icv_wrreq_i2 = imissrtn_i2 | ifc_inv_asireq_i2 | mbist_icache_write;
assign inv0_way_i2 = ~ifc_inv_ifqadv_i2 ? w0_way_f :
ldinv_i2 ? ldinv_way_i2 :
invwd0_way_i2;
assign inv1_way_i2 = ~ifc_inv_ifqadv_i2 ? w1_way_f :
ldinv_i2 ? ldinv_way_i2 :
invwd1_way_i2;
assign pick_wr = (imissrtn_i2 | ifc_inv_asireq_i2) & ifc_inv_ifqadv_i2 |
mbist_icache_write;
assign w0_way_i2 = pick_wr ? ifd_inv_wrway_i2 :
inv0_way_i2;
assign w1_way_i2 = pick_wr ? ifd_inv_wrway_i2 :
inv1_way_i2;
dff_s #(4) wrway_reg(.din ({w0_way_i2, w1_way_i2}),
.q ({w0_way_f, w1_way_f}),
.clk (clk), .se(se), .si(), .so());
// determine the way in the ICV we are writing to
// mux3ds #(2) w0_waymux(.dout (w0_way_i2),
// .in0 (ifd_inv_wrway_i2[1:0]),
// .in1 (invwd0_way_i2[1:0]),
// .in2 (ldinv_way_i2[1:0]),
// .sel0 (icvidx_sel_wr_i2),
// .sel1 (icvidx_sel_inv_i2),
// .sel2 (icvidx_sel_ld_i2));
// mux3ds #(2) w1_waymux(.dout (w1_way_i2),
// .in0 (ifd_inv_wrway_i2[1:0]),
// .in1 (invwd1_way_i2[1:0]),
// .in2 (ldinv_way_i2[1:0]),
// .sel0 (icvidx_sel_wr_i2),
// .sel1 (icvidx_sel_inv_i2),
// .sel2 (icvidx_sel_ld_i2));
// decode write way
assign w0_dec_way_i2[0] = ~w0_way_i2[1] & ~w0_way_i2[0];
assign w0_dec_way_i2[1] = ~w0_way_i2[1] & w0_way_i2[0];
assign w0_dec_way_i2[2] = w0_way_i2[1] & ~w0_way_i2[0];
assign w0_dec_way_i2[3] = w0_way_i2[1] & w0_way_i2[0];
assign w1_dec_way_i2[0] = ~w1_way_i2[1] & ~w1_way_i2[0];
assign w1_dec_way_i2[1] = ~w1_way_i2[1] & w1_way_i2[0];
assign w1_dec_way_i2[2] = w1_way_i2[1] & ~w1_way_i2[0];
assign w1_dec_way_i2[3] = w1_way_i2[1] & w1_way_i2[0];
// determine if valid bit write to top 32B, bot 32B or both
assign wrt_en_wd_i2[0] = word0_inv_i2 & (stpkt_i2 | evpkt_i2 |strmack_i2) &
~inv_addr_i2[6] |
ldinv_i2 & ~ldinv_addr_i2[5] & ~ldinv_addr_i2[6] |
icv_wrreq_i2 & ~missaddr5_i2 & ~missaddr6_i2;
assign wrt_en_wd_i2[1] = word1_inv_i2 & (stpkt_i2 | evpkt_i2 |strmack_i2) &
~inv_addr_i2[6] |
ldinv_i2 & ldinv_addr_i2[5] & ~ldinv_addr_i2[6] |
icv_wrreq_i2 & missaddr5_i2 & ~missaddr6_i2;
assign wrt_en_wd_i2[2] = word0_inv_i2 & (stpkt_i2 | evpkt_i2 |strmack_i2) &
inv_addr_i2[6] |
ldinv_i2 & ~ldinv_addr_i2[5] & ldinv_addr_i2[6] |
icv_wrreq_i2 & ~missaddr5_i2 & missaddr6_i2;
assign wrt_en_wd_i2[3] = word1_inv_i2 & (stpkt_i2 | evpkt_i2 |strmack_i2) &
inv_addr_i2[6] |
ldinv_i2 & ldinv_addr_i2[5] & ldinv_addr_i2[6] |
icv_wrreq_i2 & missaddr5_i2 & missaddr6_i2;
assign wrt_en_wd_bf = ifc_inv_ifqadv_i2 ? wrt_en_wd_i2 :
wrt_en_wd_f;
dff_s #(4) wrten_reg(.din (wrt_en_wd_bf),
.q (wrt_en_wd_f),
.clk (clk), .se(se), .si(), .so());
// Final Write Enable to ICV
assign wren_i2[3:0] = (w0_dec_way_i2 & {4{wrt_en_wd_bf[0]}}) |
{4{invall_i2 & ~invpa5_i2 & ~inv_addr_i2[6]}};
assign wren_i2[7:4] = (w1_dec_way_i2 & {4{wrt_en_wd_bf[1]}}) |
{4{invall_i2 & invpa5_i2 & ~inv_addr_i2[6]}};
assign wren_i2[11:8] = (w0_dec_way_i2 & {4{wrt_en_wd_bf[2]}}) |
{4{invall_i2 & ~invpa5_i2 & inv_addr_i2[6]}};
assign wren_i2[15:12] = (w1_dec_way_i2 & {4{wrt_en_wd_bf[3]}}) |
{4{invall_i2 & invpa5_i2 & inv_addr_i2[6]}};
assign ifq_icv_wren_bf = wren_i2;
// advance the wr way for the ICV array
// mux2ds #(8) wren_mux(.dout (next_wren_i2),
// .in0 (wren_f),
// .in1 (wren_i2),
// .sel0 (~ifc_ifd_ifqadv_i2),
// .sel1 (ifc_ifd_ifqadv_i2));
// assign wren_bf = ifc_inv_ifqadv_i2 ? wren_i2 : wren_f;
// dff #(8) icv_weff(.din (wren_bf),
// .q (wren_f),
// .clk (clk),
// .se (se), .si(), .so());
// assign ifq_icv_wren_bf[7:0] = wren_bf[7:0] & {8{~icvaddr6_i2}};
// assign ifq_icv_wren_bf[15:8] = wren_bf[7:0] & {8{icvaddr6_i2}};
//--------------------------
// Invalidates
//--------------------------
assign invalidate_i2 = (stpkt_i2 | evpkt_i2 | strmack_i2) &
(word0_inv_i2 |
word1_inv_i2 |
ifd_inv_ifqop_i2[`CPX_IINV]) | // all ways
ldinv_i2;
mux2ds #(1) invf_mux(.dout (invreq_i2),
.in0 (invalidate_f),
.in1 (invalidate_i2),
.sel0 (~ifc_inv_ifqadv_i2),
.sel1 (ifc_inv_ifqadv_i2));
dff_s #(1) invf_ff(.din (invreq_i2),
.q (invalidate_f),
.clk (clk),
.se (se), .si(), .so());
// auto invalidate is done during bist
// no need to qualify bist_write with ifqadv_i2 since bist is done
// before anything else.
assign ifq_fcl_invreq_bf = invreq_i2 | mbist_icache_write;
// don't really need to OR with invalidate_f, since this will be
// gone in a cycle
// assign inv_ifc_inv_pending = invalidate_i2 | invalidate_f;
assign inv_ifc_inv_pending = invalidate_i2;
//---------------------------------
// Get the ifill/invalidation index
//---------------------------------
// ifill index
assign icaddr_i2[`IC_IDX_HI:5] = ifq_icd_index_bf[`IC_IDX_HI:5];
assign missaddr5_i2 = ifq_icd_index_bf[5];
assign missaddr6_i2 = ifq_icd_index_bf[6];
// evict invalidate index
// assign inv_addr_i2 = ifqop_i2[117:112];
assign inv_addr_i2 = ifd_inv_ifqop_i2[`CPX_INV_IDX_HI:`CPX_INV_IDX_LO];
// index for invalidates caused by a load
// store dcache index when a load req is made
assign ldthr[0] = ~lsu_ifu_ld_pcxpkt_tid[1] & ~lsu_ifu_ld_pcxpkt_tid[0];
assign ldthr[1] = ~lsu_ifu_ld_pcxpkt_tid[1] & lsu_ifu_ld_pcxpkt_tid[0];
assign ldthr[2] = lsu_ifu_ld_pcxpkt_tid[1] & ~lsu_ifu_ld_pcxpkt_tid[0];
assign ldthr[3] = lsu_ifu_ld_pcxpkt_tid[1] & lsu_ifu_ld_pcxpkt_tid[0];
assign ldidx_sel_new = ldthr & {4{lsu_ifu_ld_pcxpkt_vld}};
// dp_mux2es #(`IC_IDX_SZ) t0_ldidx_mux(.dout (ldindex0_nxt),
// .in0 (ldindex0),
// .in1 (lsu_ifu_ld_icache_index),
// .sel (ldidx_sel_new[0]));
assign ldindex0_nxt = ldidx_sel_new[0] ? lsu_ifu_ld_icache_index :
ldindex0;
// dp_mux2es #(`IC_IDX_SZ) t1_ldidx_mux(.dout (ldindex1_nxt),
// .in0 (ldindex1),
// .in1 (lsu_ifu_ld_icache_index),
// .sel (ldidx_sel_new[1]));
assign ldindex1_nxt = ldidx_sel_new[1] ? lsu_ifu_ld_icache_index :
ldindex1;
// dp_mux2es #(`IC_IDX_SZ) t2_ldidx_mux(.dout (ldindex2_nxt),
// .in0 (ldindex2),
// .in1 (lsu_ifu_ld_icache_index),
// .sel (ldidx_sel_new[2]));
assign ldindex2_nxt = ldidx_sel_new[2] ? lsu_ifu_ld_icache_index :
ldindex2;
// dp_mux2es #(`IC_IDX_SZ) t3_ldidx_mux(.dout (ldindex3_nxt),
// .in0 (ldindex3),
// .in1 (lsu_ifu_ld_icache_index),
// .sel (ldidx_sel_new[3]));
assign ldindex3_nxt = ldidx_sel_new[3] ? lsu_ifu_ld_icache_index :
ldindex3;
dff_s #(`IC_IDX_SZ) ldix0_reg(.din (ldindex0_nxt),
.q (ldindex0),
.clk (clk), .se(se), .si(), .so());
dff_s #(`IC_IDX_SZ) ldix1_reg(.din (ldindex1_nxt),
.q (ldindex1),
.clk (clk), .se(se), .si(), .so());
dff_s #(`IC_IDX_SZ) ldix2_reg(.din (ldindex2_nxt),
.q (ldindex2),
.clk (clk), .se(se), .si(), .so());
dff_s #(`IC_IDX_SZ) ldix3_reg(.din (ldindex3_nxt),
.q (ldindex3),
.clk (clk), .se(se), .si(), .so());
// Pick dcache index corresponding to current thread
mux4ds #(`IC_IDX_SZ) ldinv_mux(.dout (ldinv_addr_i2),
.in0 (ldindex0),
.in1 (ldindex1),
.in2 (ldindex2),
.in3 (ldindex3),
.sel0 (dcpxthr_i2[0]),
.sel1 (dcpxthr_i2[1]),
.sel2 (dcpxthr_i2[2]),
.sel3 (dcpxthr_i2[3]));
// Final Mux for Index
assign icvidx_sel_wr_i2 = imissrtn_i2 | ifc_inv_asireq_i2 |
mbist_icache_write | ~ifc_inv_ifqadv_i2;
assign icvidx_sel_ld_i2 = ldinv_i2 & ifc_inv_ifqadv_i2;
assign icvidx_sel_inv_i2 = ~imissrtn_i2 & ~ldinv_i2 &
~ifc_inv_asireq_i2 & ifc_inv_ifqadv_i2 &
~mbist_icache_write;
mux3ds #(`IC_IDX_SZ) icv_idx_mux(
.dout (ifq_icv_wrindex_bf[`IC_IDX_HI:5]),
.in0 (icaddr_i2[`IC_IDX_HI:5]),
.in1 ({inv_addr_i2[`IC_IDX_HI:6], 1'b0}),
.in2 (ldinv_addr_i2[`IC_IDX_HI:5]),
.sel0 (icvidx_sel_wr_i2),
.sel1 (icvidx_sel_inv_i2),
.sel2 (icvidx_sel_ld_i2));
sink #(`CPX_WIDTH) s0(.in (ifd_inv_ifqop_i2));
endmodule // sparc_ifu_invctl
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: BMSTU
// Engineer: Oleg Odintsov
//
// Create Date: 15:09:47 01/19/2012
// Design Name:
// Module Name: ag_main
// Project Name: Agat Hardware Project
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module RAM2kx8(input CLK, input[10:0] AB, input CS, input READ, output[7:0] DO, input[7:0] DI);
reg[7:0] mem[0:2047];
reg[7:0] R;
assign DO = CS? R: 8'bZ;
initial begin
`include "monitor7.v"
// mem['h7FA] = 8'h58;
// mem['h7FB] = 8'hF9;
mem['h7FC] = 8'h00;
mem['h7FD] = 8'h18;
end
always @(posedge CLK) if (CS) if (READ) R <= mem[AB]; else mem[AB] <= DI;
endmodule
module RAM4kx8(input CLK, input[11:0] AB, input CS, input READ, output[7:0] DO, input[7:0] DI);
reg[7:0] mem[0:4095];
reg[7:0] R;
assign DO = CS? R: 8'bZ;
always @(posedge CLK) if (CS) if (READ) R <= mem[AB]; else mem[AB] <= DI;
endmodule
module RAM8kx8(input CLK, input[12:0] AB, input CS, input READ, output[7:0] DO, input[7:0] DI);
reg[7:0] mem[0:8191];
reg[7:0] R;
assign DO = CS? R: 8'bZ;
always @(posedge CLK) if (CS) if (READ) R <= mem[AB]; else mem[AB] <= DI;
endmodule
module RAM32kx8(input CLK, input[14:0] AB, input CS, input READ, output[7:0] DO, input[7:0] DI);
reg[7:0] mem[0:32767];
reg[7:0] R;
integer i;
assign DO = CS? R: 8'bZ;
initial begin
for(i = 0; i<32768; i = i + 1) mem[i] <= 0;
end
always @(posedge CLK) if (CS) if (READ) R <= mem[AB]; else mem[AB] <= DI;
endmodule
module ag_main(
input clk50,
input[3:0] btns,
output[7:0] leds,
output[3:0] controls,
output[4:0] vga_bus,
input[1:0] ps2_bus_in,
output clk_cpu
);
// assign leds = 0;
// assign controls = 0;
// assign vga_bus = 0;
wire clk1, clk10;
clk_div#5 cd5(clk50, clk10);
clk_div#10 cd10(clk10, clk1);
wire clk_vram;
wire[13:0] AB2;
wire[15:0] DI2;
wire [15:0] AB; // address bus
wire [7:0] DI; // data in, read bus
wire [7:0] DO; // data out, write bus
wire read;
wire rom_cs, ram_cs, xram_cs;
wire phi_1, phi_2;
RAM32Kx8x16 base_ram(phi_2, AB[14:0], ram_cs, read, DI, DO,
clk_vram, AB2, 1, DI2);
RAM2kx8 rom1(phi_2, AB[10:0], rom_cs, read, DI, DO);
// RAM8kx8 xram(phi_2, AB[12:0], xram_cs, read, DI, DO);
wire [3:0] AB_HH = AB[15:12];
wire [3:0] AB_HL = AB[11:8];
wire [3:0] AB_LH = AB[7:4];
wire [3:0] AB_LL = AB[3:0];
wire [7:0] AB_H = AB[15:8];
wire [7:0] AB_L = AB[7:0];
wire AB_CXXX = (AB_HH == 4'hC);
wire AB_FXXX = (AB_HH == 4'hF);
wire AB_C0XX = AB_CXXX && !AB_HL;
wire AB_C00X = AB_C0XX && (AB_LH == 4'h0);
wire AB_C01X = AB_C0XX && (AB_LH == 4'h1);
wire AB_C02X = AB_C0XX && (AB_LH == 4'h2);
wire AB_C03X = AB_C0XX && (AB_LH == 4'h3);
wire AB_C04X = AB_C0XX && (AB_LH == 4'h4);
wire AB_C05X = AB_C0XX && (AB_LH == 4'h5);
wire AB_C7XX = AB_CXXX && (AB_HL == 4'h7);
reg timer_ints = 0;
assign rom_cs = AB_FXXX && AB[11]; // F800-FFFF
assign ram_cs = !AB[15];
assign xram_cs = (AB_HH[3:1] == 3'b100);
reg reset_auto = 1;
wire reset;
wire WE = ~read; // write enable
supply0 IRQ; // interrupt request
wire NMI; // non-maskable interrupt request
supply1 RDY; // Ready signal. Pauses CPU when RDY=0
supply1 SO; // Set Overflow, not used.
wire SYNC;
assign NMI = timer_ints & vga_bus[0];
reg[7:0] vmode = 0;
wire[7:0] key_reg;
reg[7:0] b_reg;
reg[3:0] lb;
wire key_rus;
reg key_clear = 0;
wire key_rst, key_pause;
reg beep_reg = 0, tape_out_reg = 0;
assign reset = 0;//btns[0];
assign leds = AB[11:4];
assign controls = {1'b0, beep_reg ^ tape_out_reg, tape_out_reg, beep_reg};
ag_video video(clk50, vmode, clk_vram, AB2, DI2, vga_bus);
wire[1:0] ps2_bus;
signal_filter sf1(clk1, ps2_bus_in[0], ps2_bus[0]);
signal_filter sf2(clk1, ps2_bus_in[1], ps2_bus[1]);
ag_keyb keyb(phi_2, ps2_bus, key_reg, key_clear, key_rus, key_rst, key_pause);
assign DI = (AB_C00X && !WE)?b_reg?b_reg:key_reg:8'bZ;
wire reset_all = reset | reset_auto | key_rst;
always @(posedge phi_2) begin
key_clear <= AB_C01X;
if (AB_C01X) b_reg <= 0;
else if (AB_C04X) timer_ints <= 1;
else if (AB_C05X || reset_all) timer_ints <= 0;
if (btns[2] & ~lb[2]) b_reg <= 8'h8D;
else if (btns[0] & ~lb[0]) b_reg <= 8'h9A;
else if (btns[1] & ~lb[1]) b_reg <= 8'hA0;
else if (btns[3] & ~lb[3]) b_reg <= 8'h99;
lb <= btns;
if (AB_C02X) tape_out_reg <= ~tape_out_reg;
if (AB_C03X) beep_reg <= ~beep_reg;
if (AB_C7XX) vmode <= AB_L;
end
always @(posedge vga_bus[0]) begin
reset_auto <= 0;
end
ag6502_ext_clock clk(clk50, clk1, phi_1, phi_2);
ag6502 cpu(clk1, phi_1, phi_2, AB, read, DI, DO,
RDY & ~key_pause, ~reset_all, ~IRQ, ~NMI, SO, SYNC);
assign clk_cpu = clk1;
endmodule
module ag_test(
input clk10
);
wire clk1, clkx;
my_clk_div#10 c10(clk10, clk1);
my_clk_div#100 c100(clk1, clkx);
wire[13:0] AB2 = 0;
wire[15:0] DI2;
wire [15:0] AB; // address bus
wire [7:0] DI; // data in, read bus
wire [7:0] DO; // data out, write bus
wire read;
wire rom_cs, ram_cs;
wire phi_1, phi_2;
wire clk_vram = 0;
// RAM32Kx8x16 base_ram(phi_2, AB[14:0], ram_cs, read, DI, DO,
// clk_vram, AB2, 1, DI2);
RAM32kx8 base_ram(phi_2, AB[14:0], ram_cs, read, DI, DO);
RAM2kx8 rom1(phi_2, AB[10:0], rom_cs, read, DI, DO);
wire [3:0] AB_HH = AB[15:12];
wire [3:0] AB_HL = AB[11:8];
wire [3:0] AB_LH = AB[7:4];
wire [3:0] AB_LL = AB[3:0];
wire [7:0] AB_H = AB[15:8];
wire [7:0] AB_L = AB[7:0];
wire AB_CXXX = (AB_HH == 4'hC);
wire AB_FXXX = (AB_HH == 4'hF);
wire AB_C0XX = AB_CXXX && !AB_HL;
wire AB_C00X = AB_C0XX && (AB_LH == 4'h0);
wire AB_C01X = AB_C0XX && (AB_LH == 4'h1);
wire AB_C02X = AB_C0XX && (AB_LH == 4'h2);
wire AB_C03X = AB_C0XX && (AB_LH == 4'h3);
wire AB_C04X = AB_C0XX && (AB_LH == 4'h4);
wire AB_C05X = AB_C0XX && (AB_LH == 4'h5);
wire AB_C7XX = AB_CXXX && (AB_HL == 4'h7);
reg timer_ints = 1;
assign rom_cs = AB_FXXX && AB[11]; // F800-FFFF
assign ram_cs = !AB[15];
assign xram_cs = (AB_HH[3:1] == 3'b100);
reg reset_auto = 1;
wire reset;
wire WE = ~read; // write enable
supply0 IRQ; // interrupt request
wire NMI; // non-maskable interrupt request
supply1 RDY; // Ready signal. Pauses CPU when RDY=0
supply1 SO; // Set Overflow, not used.
wire SYNC;
assign NMI = clkx;
reg[7:0] vmode = 0;
wire[7:0] key_reg;
reg[7:0] b_reg;
reg lb;
wire key_rus = 0;
reg key_clear = 0;
wire key_rst = 0, key_pause = 0;
reg beep_reg = 0, tape_out_reg = 0;
assign reset = 0;//btns[0];
assign DI = (AB_C00X && !WE)?b_reg?b_reg:key_reg:8'bZ;
always @(negedge clkx) begin
reset_auto <= 0;
end
ag6502_ext_clock#(2,1) clk(clk10, clk1, phi_1, phi_2);
ag6502 cpu(clk1, phi_1, phi_2, AB, read, DI, DO,
RDY & ~key_pause, ~(reset | reset_auto | key_rst), ~IRQ, ~NMI, SO, SYNC);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DECAP_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__DECAP_PP_SYMBOL_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__decap (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DECAP_PP_SYMBOL_V
|
module RAMB16_S2_S2(
input WEA,
input ENA,
input SSRA,
input CLKA,
input [12:0] ADDRA,
input [1:0] DIA,
// input DIPA,
// output [3:0] DOPA,
output [1:0] DOA,
input WEB,
input ENB,
input SSRB,
input CLKB,
input [12:0] ADDRB,
input [1:0] DIB,
// input DIPB,
// output [3:0] DOPB,
output [1:0] DOB);
parameter WRITE_MODE_A = "write_first";
parameter WRITE_MODE_B = "write_first";
parameter INIT_00=256'd0;
parameter INIT_01=256'd0;
parameter INIT_02=256'd0;
parameter INIT_03=256'd0;
parameter INIT_04=256'd0;
parameter INIT_05=256'd0;
parameter INIT_06=256'd0;
parameter INIT_07=256'd0;
parameter INIT_08=256'd0;
parameter INIT_09=256'd0;
parameter INIT_0A=256'd0;
parameter INIT_0B=256'd0;
parameter INIT_0C=256'd0;
parameter INIT_0D=256'd0;
parameter INIT_0E=256'd0;
parameter INIT_0F=256'd0;
parameter INIT_10=256'd0;
parameter INIT_11=256'd0;
parameter INIT_12=256'd0;
parameter INIT_13=256'd0;
parameter INIT_14=256'd0;
parameter INIT_15=256'd0;
parameter INIT_16=256'd0;
parameter INIT_17=256'd0;
parameter INIT_18=256'd0;
parameter INIT_19=256'd0;
parameter INIT_1A=256'd0;
parameter INIT_1B=256'd0;
parameter INIT_1C=256'd0;
parameter INIT_1D=256'd0;
parameter INIT_1E=256'd0;
parameter INIT_1F=256'd0;
parameter INIT_20=256'd0;
parameter INIT_21=256'd0;
parameter INIT_22=256'd0;
parameter INIT_23=256'd0;
parameter INIT_24=256'd0;
parameter INIT_25=256'd0;
parameter INIT_26=256'd0;
parameter INIT_27=256'd0;
parameter INIT_28=256'd0;
parameter INIT_29=256'd0;
parameter INIT_2A=256'd0;
parameter INIT_2B=256'd0;
parameter INIT_2C=256'd0;
parameter INIT_2D=256'd0;
parameter INIT_2E=256'd0;
parameter INIT_2F=256'd0;
parameter INIT_30=256'd0;
parameter INIT_31=256'd0;
parameter INIT_32=256'd0;
parameter INIT_33=256'd0;
parameter INIT_34=256'd0;
parameter INIT_35=256'd0;
parameter INIT_36=256'd0;
parameter INIT_37=256'd0;
parameter INIT_38=256'd0;
parameter INIT_39=256'd0;
parameter INIT_3A=256'd0;
parameter INIT_3B=256'd0;
parameter INIT_3C=256'd0;
parameter INIT_3D=256'd0;
parameter INIT_3E=256'd0;
parameter INIT_3F=256'd0;
RAMB16_RIGEL #(.WRITE_MODE_A(WRITE_MODE_A),.WRITE_MODE_B(WRITE_MODE_B),.BITS(2),.INIT_00(INIT_00),.INIT_01(INIT_01),.INIT_02(INIT_02),.INIT_03(INIT_03),.INIT_04(INIT_04),.INIT_05(INIT_05),.INIT_06(INIT_06),.INIT_07(INIT_07),.INIT_08(INIT_08),.INIT_09(INIT_09),.INIT_0A(INIT_0A),.INIT_0B(INIT_0B),.INIT_0C(INIT_0C),.INIT_0D(INIT_0D),.INIT_0E(INIT_0E),.INIT_0F(INIT_0F),.INIT_10(INIT_10),.INIT_11(INIT_11),.INIT_12(INIT_12),.INIT_13(INIT_13),.INIT_14(INIT_14),.INIT_15(INIT_15),.INIT_16(INIT_16),.INIT_17(INIT_17),.INIT_18(INIT_18),.INIT_19(INIT_19),.INIT_1A(INIT_1A),.INIT_1B(INIT_1B),.INIT_1C(INIT_1C),.INIT_1D(INIT_1D),.INIT_1E(INIT_1E),.INIT_1F(INIT_1F),.INIT_20(INIT_20),.INIT_21(INIT_21),.INIT_22(INIT_22),.INIT_23(INIT_23),.INIT_24(INIT_24),.INIT_25(INIT_25),.INIT_26(INIT_26),.INIT_27(INIT_27),.INIT_28(INIT_28),.INIT_29(INIT_29),.INIT_2A(INIT_2A),.INIT_2B(INIT_2B),.INIT_2C(INIT_2C),.INIT_2D(INIT_2D),.INIT_2E(INIT_2E),.INIT_2F(INIT_2F),.INIT_30(INIT_30),.INIT_31(INIT_31),.INIT_32(INIT_32),.INIT_33(INIT_33),.INIT_34(INIT_34),.INIT_35(INIT_35),.INIT_36(INIT_36),.INIT_37(INIT_37),.INIT_38(INIT_38),.INIT_39(INIT_39),.INIT_3A(INIT_3A),.INIT_3B(INIT_3B),.INIT_3C(INIT_3C),.INIT_3D(INIT_3D),.INIT_3E(INIT_3E),.INIT_3F(INIT_3F)) inner_ram(.WEA(WEA),.ENA(ENA),.SSRA(SSRA),.CLKA(CLKA),.ADDRA(ADDRA),.DIA(DIA),.DIPA(1'b0),.DOA(DOA),.WEB(WEB),.ENB(ENB),.SSRB(SSRB),.CLKB(CLKB),.ADDRB(ADDRB),.DIB(DIB),.DIPB(1'b0),.DOB(DOB));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFXTP_BEHAVIORAL_V
`define SKY130_FD_SC_LP__DFXTP_BEHAVIORAL_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_lp__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dfxtp (
Q ,
CLK,
D
);
// Module ports
output Q ;
input CLK;
input D ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire CLK_delayed;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_lp__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFXTP_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRBN_BEHAVIORAL_V
`define SKY130_FD_SC_MS__DLRBN_BEHAVIORAL_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_ms__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dlrbn (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N
);
// Module ports
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire RESET ;
wire intgate ;
reg notifier ;
wire D_delayed ;
wire GATE_N_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intgate, GATE_N_delayed );
sky130_fd_sc_ms__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, intgate, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRBN_BEHAVIORAL_V |
`default_nettype none
`timescale 1ns / 1ps
// The receiver core provides a ITU V.4-compatible bit-serial interface.
// The receiver is broadly broken up into three parts: the Wishbone B4
// slave interface, the transmitter, and the receiver.
//
// This module defines the V.4-compatible receiver.
//
// Note that if both eedd_i and eedc_i are low, the receiver never
// sees any edges to transition with, and therefore can be used to
// disable the receiver.
//
// eedd_i eedc_i Results
// 0 0 Disable receiver.
// 0 1 Receiver clocks on RXC input only. [1]
// 1 0 Receiver clocks on RXD input only. [2]
// 1 1 Receiver clocks on any edge it can find. [1, 2]
//
// Note 1: Only the rising edge of RXC is recognized.
// Note 2: Both rising AND falling edges of RXD are recognized.
module receiver(
input clk_i,
input reset_i,
// These inputs correspond to fields found in the register
// set of the receiver. Register set not included.
input [5:0] bits_i,
input [BRW:0] baud_i,
input eedd_i, // Enable Edge Detect on Data
input eedc_i, // Enable Edge Detect on Clock
// Inputs from external hardware
input rxd_i,
input rxc_i,
// Outputs to receiver FIFO.
output [SRW:0] dat_o,
output idle_o,
// Test outputs.
output sample_to
);
parameter SHIFT_REG_WIDTH = 16;
parameter BAUD_RATE_WIDTH = 32;
parameter SRW = SHIFT_REG_WIDTH - 1;
parameter BRW = BAUD_RATE_WIDTH - 1;
reg [SRW:0] shiftRegister;
reg [BRW:0] sampleCtr;
reg [5:0] bitsLeft;
reg d0, d1, c0, c1;
wire edgeDetected = (eedd_i & (d0 ^ d1)) | (eedc_i & (~c1 & c0));
wire sampleBit = ~idle_o && (sampleCtr == 0);
wire [SRW:0] shiftRegister_rev;
genvar i;
generate
for(i = 0; i <= SRW; i = i + 1) begin
assign shiftRegister_rev[i] = shiftRegister[SRW-i];
end
endgenerate
assign idle_o = (bitsLeft == 0);
assign dat_o = shiftRegister;
always @(posedge clk_i) begin
shiftRegister <= shiftRegister;
bitsLeft <= bitsLeft;
sampleCtr <= sampleCtr;
d1 <= d0;
d0 <= rxd_i;
c1 <= c0;
c0 <= rxc_i;
if(reset_i) begin
shiftRegister <= ~(0);
bitsLeft <= 0;
sampleCtr <= baud_i;
d0 <= 1;
d1 <= 1;
end
else begin
if(edgeDetected) begin
if(idle_o) begin
bitsLeft <= bits_i;
end
sampleCtr <= {1'b0, baud_i[BRW:1]};
end
else if(sampleBit) begin
sampleCtr <= baud_i;
bitsLeft <= bitsLeft - 1;
shiftRegister <= {d0, shiftRegister[SRW:1]};
end
else if(idle_o) begin
sampleCtr <= baud_i;
end
else begin
sampleCtr <= sampleCtr - 1;
end
end
end
assign sample_to = sampleBit;
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_a
//
// Generated
// by: wig
// on: Tue Jul 4 08:39:13 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_a.v,v 1.3 2007/03/05 13:33:58 wig Exp $
// $Date: 2007/03/05 13:33:58 $
// $Log: ent_a.v,v $
// Revision 1.3 2007/03/05 13:33:58 wig
// Updated testcase output (only comments)!
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_a
//
// No user `defines in this module
module ent_a
//
// Generated Module inst_a
//
(
p_mix_sig_01_go,
p_mix_sig_03_go,
p_mix_sig_04_gi,
p_mix_sig_05_2_1_go,
p_mix_sig_06_gi,
p_mix_sig_i_ae_gi,
p_mix_sig_o_ae_go,
port_i_a, // Input Port
port_o_a, // Output Port
sig_07, // Conflicting definition, IN false!
sig_08, // VHDL intermediate needed (port name)
sig_13, // Create internal signal name
sig_i_a2, // Input Port
sig_o_a2 // Output Port
);
// Generated Module Inputs:
input p_mix_sig_04_gi;
input [3:0] p_mix_sig_06_gi;
input [6:0] p_mix_sig_i_ae_gi;
input port_i_a;
input [5:0] sig_07;
input sig_i_a2;
// Generated Module Outputs:
output p_mix_sig_01_go;
output p_mix_sig_03_go;
output [1:0] p_mix_sig_05_2_1_go;
output [7:0] p_mix_sig_o_ae_go;
output port_o_a;
output [8:2] sig_08;
output [4:0] sig_13;
output sig_o_a2;
// Generated Wires:
wire p_mix_sig_01_go;
wire p_mix_sig_03_go;
wire p_mix_sig_04_gi;
wire [1:0] p_mix_sig_05_2_1_go;
wire [3:0] p_mix_sig_06_gi;
wire [6:0] p_mix_sig_i_ae_gi;
wire [7:0] p_mix_sig_o_ae_go;
wire port_i_a;
wire port_o_a;
wire [5:0] sig_07;
wire [8:2] sig_08;
wire [4:0] sig_13;
wire sig_i_a2;
wire sig_o_a2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire sig_01; // __W_PORT_SIGNAL_MAP_REQ
wire [4:0] sig_02;
wire sig_03; // __W_PORT_SIGNAL_MAP_REQ
wire sig_04; // __W_PORT_SIGNAL_MAP_REQ
wire [3:0] sig_05; // __W_PORT_SIGNAL_MAP_REQ
wire [3:0] sig_06; // __W_PORT_SIGNAL_MAP_REQ
wire [6:0] sig_14;
wire [6:0] sig_i_ae; // __W_PORT_SIGNAL_MAP_REQ
wire [7:0] sig_o_ae; // __W_PORT_SIGNAL_MAP_REQ
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
assign p_mix_sig_01_go = sig_01; // __I_O_BIT_PORT
assign p_mix_sig_03_go = sig_03; // __I_O_BIT_PORT
assign sig_04 = p_mix_sig_04_gi; // __I_I_BIT_PORT
assign p_mix_sig_05_2_1_go[1:0] = sig_05[2:1]; // __I_O_SLICE_PORT
assign sig_06 = p_mix_sig_06_gi; // __I_I_BUS_PORT
assign sig_i_ae = p_mix_sig_i_ae_gi; // __I_I_BUS_PORT
assign p_mix_sig_o_ae_go = sig_o_ae; // __I_O_BUS_PORT
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_aa
ent_aa inst_aa (
.port_aa_1(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.port_aa_2(sig_02[0]), // Use internally test2, no port generated
.port_aa_3(sig_03), // Interhierachy link, will create p_mix_sig_3_go
.port_aa_4(sig_04), // Interhierachy link, will create p_mix_sig_4_gi
.port_aa_5(sig_05), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_aa_6(sig_06), // Conflicting definition (X2)
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08), // VHDL intermediate needed (port name)
.sig_13(sig_13), // Create internal signal name
.sig_14(sig_14) // Multiline comment 1
// Multiline comment 2
// Multiline comment 3
);
// End of Generated Instance Port Map for inst_aa
// Generated Instance Port Map for inst_ab
ent_ab inst_ab (
.port_ab_1(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.port_ab_2(sig_02[1]), // Use internally test2, no port generated
.sig_13(sig_13), // Create internal signal name
.sig_14(sig_14) // Multiline comment 1
// Multiline comment 2
// Multiline comment 3
);
// End of Generated Instance Port Map for inst_ab
// Generated Instance Port Map for inst_ac
ent_ac inst_ac (
.port_ac_2(sig_02[3]) // Use internally test2, no port generated
);
// End of Generated Instance Port Map for inst_ac
// Generated Instance Port Map for inst_ad
ent_ad inst_ad (
.port_ad_2(sig_02[4]) // Use internally test2, no port generated
);
// End of Generated Instance Port Map for inst_ad
// Generated Instance Port Map for inst_ae
ent_ae inst_ae (
.port_ae_2[1:0](sig_02[1:0]), // Use internally test2, no port generated// __E_CANNOT_COMBINE_SPLICES
.port_ae_2[4:3](sig_02[4:3]), // Use internally test2, no port generated// __E_CANNOT_COMBINE_SPLICES
.port_ae_5(sig_05), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_ae_6(sig_06), // Conflicting definition (X2)
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08), // VHDL intermediate needed (port name)
.sig_i_ae(sig_i_ae), // Input Bus
.sig_o_ae(sig_o_ae) // Output Bus
);
// End of Generated Instance Port Map for inst_ae
endmodule
//
// End of Generated Module rtl of ent_a
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the communication channel
/**
* Import the modules that will be tested for in this testbench
*
* Include statements for design modules/files need to be commented
* out when I use the Make environment - similar to that in
* Assignment/Homework 3.
*
* Else, the Make/Cadence environment will not be able to locate
* the files that need to be included.
*
* The Make/Cadence environment will automatically search all
* files in the design/ and include/ directories of the working
* directory for this project that uses the Make/Cadence
* environment for the design modules
*
* If the ".f" files are used to run NC-Verilog to compile and
* simulate the Verilog testbench modules, use this include
* statement
*/
/*
`include "syntheziedviterbi.v"
`include "viterbi_decoder.sdf"
`include "cencoder.v"
`include "noisegen.v"
`include "xor2.v"
`include "pipe.v"
`include "pipe2.v"
*/
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
// ============================================================
module tb_syn_communication_channel();
/**
* Description of module to model a communication channel
*
* This includes 3 stages in the communications channel
* @stage 1: Data from the transmitter (TX) is encoded.
* @stage 2: Data is "transmitted" across the communication
* channel, and gets corrupted with noise.
* Noise in the communication channel is modeled
* by pseudo-random noise that corrupts some of
* the data bits
* @stage 3: Data is received at the receiver (RX), and is
* subsequently decoded.
*/
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the communication channel
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// ============================================================
// Declare "wire" signals: outputs from the DUT
// Outputs from the communication channel
wire d; // Output data signal
wire [1:0] c; // Encoded data
wire [1:0] cx; // Corrupted encoded data
wire b; // Original data
// -----------------------------------------------------------
// Encoded data output from the convolutional encoder
wire [1:0] r_c;
//wire [255:0] rf;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// ------------------------------------------------------------
// Inputs to the communication channel
//reg [255:0] r; // Original data: 256 stream of bits
reg r[0:255]; // Original data: 256 stream of bits
reg rr;
/**
* Randomly generated number to determine if data bit should
* be corrupted
*/
reg [7:0] e;
reg clock; // Clock input to all flip-flops
// ------------------------------------------------------------
/**
* Inputs to and outputs from the 1st stage of the communication
* channel
*/
// Original data input & input to the convolutional encoder
reg r_b;
// Encoded data output from the convolutional encoder
// reg [1:0] r_c;
/**
* Propagated randomly generated number to determine if data
* bit should be corrupted - propagated value from the input
* to the communications channel
*/
reg [7:0] r_e;
// ------------------------------------------------------------
/**
* Inputs to and outputs from the 2nd stage of the communication
* channel
*/
// Propagated values of the encoded data; also, input to XOR gate
reg [1:0] rr_c;
/**
* Further propagated randomly generated number to determine
* if data bit should be corrupted - propagated value from the
* input to the communications channel
*/
reg [7:0] r_e1;
/**
* Randomly generated error that determines the corruption of
* the data bits
*
* Random number will corrupt the encoded data bits based on
* the XOR operator - invert the bits of the encoded data if
* they are different from the random error bits
*
* Also, input to XOR gate to generated corrupted encoded bits
*/
wire [1:0] r_e2;
/**
* Corrupted encoded data bits - model corruption of data during
* transmission of the data in the communications channel
*/
wire [1:0] r_cx;
// Propagated original data input
reg r_b1;
/** ########################################################
#
# IMPORTANT!!!: MODIFY THE error_level HERE!!!
#
########################################################
***
*
* Error level that will be used to generate noise that will
* be used to corrupt encoded data bits
*
* Randomly generated error bits will be compared with this
* error level
*/
reg [7:0] error_level;
// ------------------------------------------------------------
// Inputs to the 3rd stage of the communication channel
// Further propagated values of the encoded data
reg [1:0] rr_c1;
// Propagated values of the corrupted encoded data
reg [1:0] r_cx1;
// Propagated original data input
reg r_b2;
// Reset signal for the flip-flops and registers
reg rset;
// ============================================================
// Counter for loop to enumerate all the values of r
integer count;
// ============================================================
// Defining constants: parameter [name_of_constant] = value;
parameter size_of_input = 9'd256;
// ============================================================
// Declare and instantiate modules for the communication channel
/**
* Instantiate an instance of Viterbi decoder so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "v_d"
*/
viterbi_decoder v_d (
// instance_name(signal name),
// Signal name can be the same as the instance name
d,r_cx1,clock,rset);
// ------------------------------------------------------------
/**
* Instantiate an instance of the convolutional encoder so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "enc"
*/
conv_encoder enc (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_c,r_b,clock,rset);
// ------------------------------------------------------------
/**
* Instantiate an instance of the noise generator so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "ng"
*/
noise_generator ng (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_e1,r_e2,error_level);
// ------------------------------------------------------------
/**
* Instantiate an instance of the 2-bit 2-input XOR gate so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "xor22"
*/
xor2_2bit xor22 (
// instance_name(signal name),
// Signal name can be the same as the instance name
rr_c,r_e2,r_cx);
// ------------------------------------------------------------
/**
* Instantiate an instance of the pipe
* so that inputs can be passed to the Device Under Test (DUT)
* Given instance name is "pipe_c"
*/
pipeline_buffer_2bit pipe_c (
// instance_name(signal name),
// Signal name can be the same as the instance name
rr_c1,c,clock,rset);
// ------------------------------------------------------------
/**
* Instantiate an instance of the pipe
* so that inputs can be passed to the Device Under Test (DUT)
* Given instance name is "pipe_cx"
*/
pipeline_buffer_2bit pipe_cx (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_cx1,cx,clock,rset);
// ------------------------------------------------------------
/**
* Instantiate an instance of the pipe
* so that inputs can be passed to the Device Under Test (DUT)
* Given instance name is "pipe_b"
*/
pipeline_buffer pipe_b (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_b2,b,clock,rset);
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#5 clock = 0;
#5 clock = 1;
// Period = 10 clock cycles
end
// ============================================================
// Create the register (flip-flop) for the initial/1st stage
always@(posedge clock)
begin
if(rset)
begin
r_b<=0;
r_e<=0;
end
else
begin
r_e<=e;
r_b<=rr;
end
end
// ------------------------------------------------------------
// Create the register (flip-flop) for the 2nd stage
always@(posedge clock)
begin
if(rset)
begin
rr_c<=0;
r_e1<=0;
r_b1<=0;
end
else
begin
rr_c<=r_c;
r_e1<=r_e;
r_b1<=r_b;
end
end
// ------------------------------------------------------------
// Create the register (flip-flop) for the 3rd stage
always@(posedge clock)
begin
if(rset)
begin
rr_c1<=0;
r_cx1<=0;
r_b2<=0;
end
else
begin
rr_c1<=rr_c;
r_cx1<=r_cx;
r_b2<=r_b1;
end
end
// ------------------------------------------------------------
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
// @t=0,
error_level=8'd5;
rset=1;
// @t=20,
#20
rset=0;
/**
* Read the input data for r from an input file named
* "testfile.bit"
*/
$readmemb("testfile.bit",r);
/// $readmemb("testfile.bit",rf);
/**
* IMPORTANT NOTE:
* Start to process inputs from the input file after
* 30 clock cycles
*/
for(count=0;count<size_of_input;count=count+1)
begin
#10
$display("Next");
e=$random;
rr=r[count];
if(rr_c != r_cx)
begin
$display($time,"rr_c NOT EQUAL to r_cx");
end
if(count==150)
begin
rset=1;
end
else if(count==151)
begin
rset=0;
end
end
// Problem with d and error_level
#20;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2015(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module util_dacfifo (
// DMA interface
dma_clk,
dma_rst,
dma_valid,
dma_data,
dma_ready,
dma_xfer_req,
dma_xfer_last,
// DAC interface
dac_clk,
dac_valid,
dac_data
);
// depth of the FIFO
parameter ADDR_WIDTH = 6;
parameter DATA_WIDTH = 128;
// local parameters
// port definitions
// DMA interface
input dma_clk;
input dma_rst;
input dma_valid;
input [(DATA_WIDTH-1):0] dma_data;
output dma_ready;
input dma_xfer_req;
input dma_xfer_last;
// DAC interface
input dac_clk;
input dac_valid;
output [(DATA_WIDTH-1):0] dac_data;
// internal registers
reg [(ADDR_WIDTH-1):0] dma_waddr = 'b0;
reg [(ADDR_WIDTH-1):0] dma_lastaddr = 'b0;
reg [(ADDR_WIDTH-1):0] dma_lastaddr_d = 'b0;
reg [(ADDR_WIDTH-1):0] dma_lastaddr_2d = 'b0;
reg dma_xfer_req_ff = 1'b0;
reg dma_ready = 1'b0;
reg [(ADDR_WIDTH-1):0] dac_raddr = 'b0;
reg [(DATA_WIDTH-1):0] dac_data = 'b0;
// internal wires
wire dma_wren;
wire [(DATA_WIDTH-1):0] dac_data_s;
// write interface
always @(posedge dma_clk) begin
if(dma_rst == 1'b1) begin
dma_ready <= 1'b0;
dma_xfer_req_ff <= 1'b0;
end else begin
dma_ready <= 1'b1; // Fifo is always ready
dma_xfer_req_ff <= dma_xfer_req;
end
end
always @(posedge dma_clk) begin
if(dma_rst == 1'b1) begin
dma_waddr <= 'b0;
dma_lastaddr <= 'b0;
end else begin
if (dma_valid && dma_xfer_req) begin
dma_waddr <= dma_waddr + 1;
end
if (dma_xfer_last) begin
dma_lastaddr <= dma_waddr;
dma_waddr <= 'b0;
end
end
end
assign dma_wren = dma_valid & dma_xfer_req;
// read interface
// sync lastaddr to dac clock domain
always @(posedge dac_clk) begin
dma_lastaddr_d <= dma_lastaddr;
dma_lastaddr_2d <= dma_lastaddr_d;
end
// generate dac read address
always @(posedge dac_clk) begin
if(dac_valid == 1'b1) begin
if (dma_lastaddr_2d == 'h0) begin
dac_raddr <= dac_raddr + 1;
end else begin
dac_raddr <= (dac_raddr < dma_lastaddr_2d) ? (dac_raddr + 1) : 'b0;
end
end
dac_data <= dac_data_s;
end
// memory instantiation
ad_mem #(
.ADDR_WIDTH (ADDR_WIDTH),
.DATA_WIDTH (DATA_WIDTH))
i_mem_fifo (
.clka (dma_clk),
.wea (dma_wren),
.addra (dma_waddr),
.dina (dma_data),
.clkb (dac_clk),
.addrb (dac_raddr),
.doutb (dac_data_s));
endmodule
|
// File: DEMUX1_4_B.v
// Generated by MyHDL 0.10
// Date: Sun Sep 23 18:24:25 2018
`timescale 1ns/10ps
module DEMUX1_4_B (
x,
s0,
s1,
y0,
y1,
y2,
y3
);
// 1:4 DEMUX written via behaviorial
//
// Inputs:
// x(bool): input feed
// s0(bool): channel select 0
// s1(bool): channel select 1
//
// Outputs:
// y0(bool): ouput channel 0
// y1(bool): ouput channel 1
// y2(bool): ouput channel 2
// y3(bool): ouput channel 3
input x;
input s0;
input s1;
output y0;
reg y0;
output y1;
reg y1;
output y2;
reg y2;
output y3;
reg y3;
always @(x, s1, s0) begin: DEMUX1_4_B_LOGIC
if (((s0 == 0) && (s1 == 0))) begin
y0 = x;
y1 = 0;
y2 = 0;
y3 = 0;
end
else if (((s0 == 1) && (s1 == 0))) begin
y0 = 0;
y1 = x;
y2 = 0;
y3 = 0;
end
else if (((s0 == 0) && (s1 == 1))) begin
y0 = 0;
y1 = 0;
y2 = x;
y3 = 0;
end
else begin
y0 = 0;
y1 = 0;
y2 = 0;
y3 = x;
end
end
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2018 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file sa1_iram.v when simulating
// the core, sa1_iram. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module sa1_iram(
clka,
wea,
addra,
dina,
douta,
clkb,
web,
addrb,
dinb,
doutb
);
input clka;
input [0 : 0] wea;
input [10 : 0] addra;
input [7 : 0] dina;
output [7 : 0] douta;
input clkb;
input [0 : 0] web;
input [10 : 0] addrb;
input [7 : 0] dinb;
output [7 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(11),
.C_ADDRB_WIDTH(11),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(2048),
.C_READ_DEPTH_B(2048),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(2048),
.C_WRITE_DEPTH_B(2048),
.C_WRITE_MODE_A("READ_FIRST"),
.C_WRITE_MODE_B("READ_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.RSTB(),
.ENB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2015/09/22 10:47:40
// Design Name:
// Module Name: test_filter
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module test_filter(
vid_pData_I,
vid_pHSync_I,
vid_pVSync_I,
vid_pVDE_I,
PixelClk_I,
vid_pData_O,
vid_pHSync_O,
vid_pVSync_O,
vid_pVDE_O,
PixelClk_O
);
input [23:0] vid_pData_I;
input vid_pHSync_I;
input vid_pVSync_I;
input vid_pVDE_I;
input PixelClk_I;
output [23:0] vid_pData_O;
output vid_pHSync_O;
output vid_pVSync_O;
output vid_pVDE_O;
output PixelClk_O;
assign vid_pData_O[23:16] = vid_pData_I[7:0];
assign vid_pData_O[15:8] = vid_pData_I[23:16];
assign vid_pData_O[7:0] = vid_pData_I[15:8];
assign vid_pVSync_O = vid_pVSync_I;
assign vid_pHSync_O = vid_pHSync_I;
assign vid_pVDE_O = vid_pVDE_I;
assign PixelClk_O = PixelClk_I;
endmodule
|
`timescale 1ns / 1ps
module top_ASCCI(
input clk,
input [76:0] string,
input new_string,
input [7:0]dir,
output [15:0]datoram,
output [6:0] efect,
output run_efect
//abilita y desa el bus de direcion de ram de cada modulo
);
wire [3:0]col;
wire top_col;
wire [3:0]n_ascci;
wire top_ascci;
wire add_ascci;
wire reset_ascci;
wire add_col;
wire reset_col;
wire add_dirram;
wire reset_dirram;
wire leer_rom;
wire leer_ram;
wire [6:0]ascci;
wire [10:0]dir_rom;
wire wram;
wire [15:0]datorom;
wire [10:0]dir_in;
wire [7:0] d_ram;
wire [7:0] dir_ram;
wire done;
select_dir seldir(.clk(clk),.d_ram(d_ram),.dir_ram(dir_ram),.dir(dir),.leer_ram(leer_ram) );
comp_col comcol(.col(col),.top_col(top_col));
compn_ascci camasc (.n_ascci(n_ascci),.top_ascci(top_ascci));
cont_ascci aonasc (.n_ascci(n_ascci),.clk(clk),.add_ascci(add_ascci),.reset_ascci(reset_ascci));
cont_col aoncol(.clk(clk),.add_col(add_col),.reset_col(reset_col),.col(col));
cont_ram conra (.clk(clk),.add_dirram(add_dirram),.reset_dirram(reset_dirram),.dir_ram(dir_ram));
control_ascci contrascc (.clk(clk),.top_ascci(top_ascci),.top_col(top_col),.add_dirram(add_dirram),.reset_dirram(reset_dirram),.add_col(add_col),.reset_col(reset_col),.add_ascci(add_ascci),.reset_ascci(reset_ascci),.leer_rom(leer_rom),.leer_ram(leer_ram),.new_string(new_string),.init(init),.done(done),.run_efect(run_efect));
dir_ascci dirasc (.dir_in(dir_in),.clk(clk),.dir_rom(dir_rom),.col(col),.done(done));
m_plexor mplex(.string(string),.n_ascci(n_ascci),.ascci(ascci),.efect(efect) );
ram ra (.clk(clk),.direccionram(d_ram),.wram(leer_ram),.datorom(datorom),.datoram(datoram));
rom ro (.clk(clk),.leer_rom(leer_rom),.dir_rom(dir_rom),.dato_rom(datorom));
top_multiplicador mult(.clk(clk),.init(init),.A(ascci),.pp(dir_in), .done(done));
endmodule
|
//////////////////////////////////////////////////////////////////////
/// ////
/// ORPSoC testbench for Altera de1 board ////
/// ////
/// Franck Jullien, [email protected] ////
/// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "timescale.v"
module orpsoc_tb;
reg clk = 0;
reg rst_n = 0;
////////////////////////////////////////////////////////////////////////
//
// Generate clock (100MHz) and external reset
//
////////////////////////////////////////////////////////////////////////
always
#5 clk <= ~clk;
initial begin
#100 rst_n <= 0;
#200 rst_n <= 1;
end
////////////////////////////////////////////////////////////////////////
//
// Add --vcd and --timeout options to the simulation
//
////////////////////////////////////////////////////////////////////////
vlog_tb_utils vlog_tb_utils0();
////////////////////////////////////////////////////////////////////////
//
// JTAG VPI interface
//
////////////////////////////////////////////////////////////////////////
reg enable_jtag_vpi;
initial enable_jtag_vpi = $test$plusargs("enable_jtag_vpi");
jtag_vpi jtag_vpi0
(
.tms (tms),
.tck (tck),
.tdi (tdi),
.tdo (tdo),
.enable (enable_jtag_vpi),
.init_done (orpsoc_tb.dut.wb_rst));
////////////////////////////////////////////////////////////////////////
//
// SDRAM
//
////////////////////////////////////////////////////////////////////////
wire [11:0] sdram_addr;
wire [1:0] sdram_ba;
wire sdram_cas;
wire sdram_cke;
wire sdram_clk;
wire sdram_cs_n;
wire [15:0] sdram_dq;
wire [1:0] sdram_dqm;
wire sdram_ras;
wire sdram_we;
wire uart_tx;
mt48lc16m16a2_wrapper
#(.ADDR_BITS (12),
.COL_BITS (8),
.MEM_SIZES (1048576))
sdram_wrapper0
(.clk_i (sdram_clk),
.rst_n_i (rst_n),
.dq_io (sdram_dq),
.addr_i (sdram_addr),
.ba_i (sdram_ba),
.cas_i (sdram_cas),
.cke_i (sdram_cke),
.cs_n_i (sdram_cs_n),
.dqm_i (sdram_dqm),
.ras_i (sdram_ras),
.we_i (sdram_we));
////////////////////////////////////////////////////////////////////////
//
// DUT
//
////////////////////////////////////////////////////////////////////////
orpsoc_top dut
(
.sys_clk_pad_i (clk),
.rst_n_pad_i (rst_n),
.led_r_pad_o (),
.gpio0_io (),
.tms_pad_i (tms),
.tck_pad_i (tck),
.tdi_pad_i (tdi),
.tdo_pad_o (tdo),
.sdram_ba_pad_o (sdram_ba),
.sdram_a_pad_o (sdram_addr),
.sdram_cs_n_pad_o (sdram_cs_n),
.sdram_ras_pad_o (sdram_ras),
.sdram_cas_pad_o (sdram_cas),
.sdram_we_pad_o (sdram_we),
.sdram_dq_pad_io (sdram_dq),
.sdram_dqm_pad_o (sdram_dqm),
.sdram_cke_pad_o (sdram_cke),
.sdram_clk_pad_o (sdram_clk),
.uart0_srx_pad_i (),
.uart0_stx_pad_o (uart_tx)
);
`ifdef OR1200_CPU
or1200_monitor i_monitor();
`else
mor1kx_monitor #(.LOG_DIR(".")) i_monitor();
`endif
////////////////////////////////////////////////////////////////////////
//
// UART decoder
//
////////////////////////////////////////////////////////////////////////
//FIXME: Get correct baud rate from parameter
uart_decoder
#(.uart_baudrate_period_ns(8680 / 2))
uart_decoder0
(
.clk(clk),
.uart_tx(uart_tx)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:44:38 02/19/2017
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module top(
input wire clk, reset,
input wire sensorA,
input wire sensorB,
output wire sensorAdb,
output wire sensorBdb,
output wire [3:0] enable, // enable 1-out-of-4 asserted low
output wire [7:0] sseg // led segments
);
wire [3:0] counter;
// Debounce sensorA
debouncer dbA (
.clk (clk),
.reset (reset),
.sw (sensorA),
.db (sensorAdb)
);
// Debounce sensorA
debouncer dbB (
.clk (clk),
.reset (reset),
.sw (sensorB),
.db (sensorBdb)
);
//instantiation of car_detector
car_detector count1(
.clk (clk),
.res (reset),
.sensorA (sensorAdb),
.sensorB (sensorBdb),
.car_count (counter)
);
//instantiation of sevenSegValue controller
sevenSegValue brd1(
.d_in (counter),
.an (enable),
.sseg (sseg)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__TAP_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__TAP_PP_BLACKBOX_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__tap (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__TAP_PP_BLACKBOX_V
|
module Rintaro (
input wire fastClk,
input wire clk1,
input wire clk2,
input wire rst,
input wire[1:0] dig,
input wire[2:0] switch,
output wire[3:0] tubeDig,
output wire[7:0] tubeSeg,
output wire[10:0] lcdPins,
inout wire ps2CLK,
inout wire ps2DATA,
output wire irqOut,
input wire ir,
output wire err,
output wire stateOut,
output wire[1:0] cpuClkMode
);
wire[31:0] addr, intAddr;
wire[15:0] read;
wire[15:0] write;
reg[15:0] intData;
wire we;
wire re;
wire ready;
wire irq;
assign irqOut = irq;
wire turnOffIRQ;
wire[31:0] PC;
wire[15:0] A, B, C, FP, SP, BPH, BPL;
wire[5:0] state;
wire[15:0] page;
wire[3:0] F;
wire[31:0] bp0Addr, bp1Addr, bp2Addr, bp3Addr, bpAddr, keyboardAddr, irAddr;
wire bp0En, bp1En, bp2En, bp3En, keyboardEn, irEn;
wire[1:0] inMask, outMask;
wire[15:0] lcdIn;
RAM ram (
.rst (rst),
.clk (clk1),
.addrIn (addr),
.write (write),
.we (we),
.read (read),
.re (re),
.inMask (inMask),
.outMask (outMask),
.ready (ready),
.lcdPins (lcdPins),
.page (page),
.switch (switch),
.bp0Addr (bp0Addr),
.bp1Addr (bp1Addr),
.bp2Addr (bp2Addr),
.bp3Addr (bp3Addr),
.bpAddr (bpAddr),
.keyboardAddr (keyboardAddr),
.irAddr (irAddr),
.bp0En (bp0En),
.bp1En (bp1En),
.bp2En (bp2En),
.bp3En (bp3En),
.keyboardEn (keyboardEn),
.irEn (irEn),
.lcdIn (lcdIn)
);
rcpu cpu(
.clk (clk2),
.rst (rst),
.memAddr (addr),
.memReadIn (read),
.memWrite (write),
.memWE (we),
.memRE (re),
.memReady (ready),
.irq (irq),
.turnOffIRQ (turnOffIRQ),
.intAddr (intAddr),
.intData (intData),
.page (page),
.inMask (inMask),
.outMask (outMask),
.PC (PC),
.FP (FP),
.SP (SP),
.A (A),
.B (B),
.C (C),
.state (state),
.F (F)
);
wire[3:0] irData;
wire irPressed;
InterruptController intCtrl (
.rst (rst),
.clk (clk1),
.fastClk (fastClk),
.irq (irq),
.turnOffIRQ (turnOffIRQ),
.intAddr (intAddr),
.intData (intData),
.ps2CLK (ps2CLK),
.ps2DATA (ps2DATA),
.addr (addr),
.re (re),
.we (we),
.irData (irData),
.irPressed (irPressed),
.bp0Addr (bp0Addr),
.bp1Addr (bp1Addr),
.bp2Addr (bp2Addr),
.bp3Addr (bp3Addr),
.bpAddr (bpAddr),
.keyboardAddr (keyboardAddr),
.irAddr (irAddr),
.bp0En (bp0En),
.bp1En (bp1En),
.bp2En (bp2En),
.bp3En (bp3En),
.keyboardEn (keyboardEn),
.irEn (irEn)
);
reg[15:0] value;
reg[3:0] auxs;
wire[3:0] mode;
wire showName;
DebugIR irModule (fastClk, rst, ir, mode, showName, err, stateOut, cpuClkMode, irData, irPressed);
always @ (*) begin
if (showName) begin
case (mode)
4'h0: begin value = 16'h1C00; auxs = 4'b1011; end // PC__
4'h1: begin value = 16'hA000; auxs = 4'b0111; end // A___
4'h2: begin value = 16'hB000; auxs = 4'b0111; end // B___
4'h3: begin value = 16'hC000; auxs = 4'b0111; end // C___
4'h4: begin value = 16'h52A2; auxs = 4'b0101; end // 5tAt // Stat
4'h5: begin value = 16'h3044; auxs = 4'b1111; end // r_vv // r/w
4'h6: begin value = 16'hADD5; auxs = 4'b0001; end // AddH
4'h7: begin value = 16'hADD6; auxs = 4'b0001; end // AddL
4'h8: begin value = 16'hDA2A; auxs = 4'b0010; end // dAtA
4'h9: begin value = 16'h5100; auxs = 4'b0111; end // 5P__ // SP
4'hA: begin value = 16'hF100; auxs = 4'b0111; end // FP__
4'hB: begin value = 16'h8B12; auxs = 4'b0001; end // 8B1t
4'hC: begin value = 16'h6CD0; auxs = 4'b1001; end // LCD_
4'hD: begin value = 16'hF000; auxs = 4'b0111; end // F___
default: begin value = 16'h0000; auxs = 4'b1111; end // ____
endcase
end else begin
auxs = 4'b0000;
case (mode)
4'd0: value = PC[15:0];
4'd1: value = A;
4'd2: value = B;
4'd3: value = C;
4'd4: value = {3'b000, irq, 3'b000, keyboardEn, 2'b00, state};
4'd5: begin
if (re) begin
value = 16'h3EAD;
auxs = 4'b1000;
end else if (we) begin
value = 16'h4432;
auxs = 4'b1111;
end else begin
value = 16'h0000;
auxs = 4'b1111;
end
end
4'd6: value = addr[31:16];
4'd7: value = addr[15:0];
4'd8: value = re? read : we? write : read;
4'd9: value = SP;
4'd10: value = FP;
4'd11: value = {3'b000, inMask[1], 3'b000, inMask[0], 3'b000, outMask[1], 3'b000, outMask[0]};
4'd12: value = lcdIn;
4'd13: value = {3'b000, F[3], 3'b000, F[2], 3'b000, F[1], 3'b000, F[0]};
default: value = 16'h0000;
endcase
end
end
TubeController tube (
.dig (dig),
.dig4 (value[15:12]),
.dig3 (value[11:8]),
.dig2 (value[7:4]),
.dig1 (value[3:0]),
.dots (4'b0000),
.auxs (auxs),
.tubeDig (tubeDig),
.tubeSeg (tubeSeg)
);
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 09:39:14 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_auto_pc_0_stub.v
// Design : zynq_design_1_auto_pc_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awregion, s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb,
s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready,
s_axi_arid, s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock,
s_axi_arcache, s_axi_arprot, s_axi_arregion, s_axi_arqos, s_axi_arvalid, s_axi_arready,
s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr,
m_axi_awprot, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid,
m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot,
m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awregion[3:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_awaddr;
output [2:0]m_axi_awprot;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0]m_axi_araddr;
output [2:0]m_axi_arprot;
output m_axi_arvalid;
input m_axi_arready;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
module sendConst(input clk, input reset,
output io_in_ready,
input io_in_valid,
input [31:0] io_in_bits,
input [4:0] io_in_tag,
input io_out_ready,
output io_out_valid,
output[31:0] io_out_bits,
output[4:0] io_out_tag,
input io_pcIn_valid,
input io_pcIn_bits_request,
input [15:0] io_pcIn_bits_moduleId,
input [7:0] io_pcIn_bits_portId,
input [15:0] io_pcIn_bits_pcValue,
input [3:0] io_pcIn_bits_pcType,
output io_pcOut_valid,
output io_pcOut_bits_request,
output[15:0] io_pcOut_bits_moduleId,
output[7:0] io_pcOut_bits_portId,
output[15:0] io_pcOut_bits_pcValue,
output[3:0] io_pcOut_bits_pcType);
reg[0:0] R0;
wire T1;
wire T2;
wire T3;
wire T4;
wire T5;
wire T6;
wire T7;
reg[3:0] R8;
wire T9;
wire[3:0] T10;
wire T11;
reg[7:0] R12;
wire T13;
wire[7:0] T14;
wire T15;
reg[15:0] R16;
wire T17;
wire[15:0] T18;
wire[15:0] T19;
wire[15:0] T20;
reg[15:0] R21;
wire T22;
wire T23;
wire T24;
wire T25;
wire T26;
wire T27;
wire[7:0] T28;
wire[7:0] T29;
wire T30;
wire T31;
wire[1:0] T32;
wire rThreadEncoder_io_chosen;
wire T33;
reg[0:0] subStateTh_0;
wire T34;
wire T35;
wire T36;
wire vThreadEncoder_io_chosen;
wire T37;
wire AllOffloadsValid_0;
wire T38;
wire T39;
wire T40;
reg[7:0] State_0;
wire T41;
wire T42;
wire T43;
wire[7:0] T44;
wire[7:0] T45;
wire[7:0] T46;
wire T47;
wire T48;
wire[1:0] T49;
wire T50;
wire T51;
wire T52;
wire T53;
wire T54;
wire T55;
wire T56;
wire T57;
wire T58;
wire T59;
wire[1:0] T60;
wire sThreadEncoder_io_chosen;
wire T61;
wire T62;
wire T63;
wire T64;
wire T65;
wire T66;
wire[7:0] T67;
wire[7:0] T68;
wire[7:0] T69;
wire[7:0] T70;
wire[7:0] T71;
wire[7:0] T72;
reg[7:0] EmitReturnState_0;
wire T73;
wire[7:0] T74;
wire[7:0] T75;
wire T76;
wire T77;
wire T78;
wire T79;
wire T80;
wire T81;
wire T82;
wire[3:0] T83;
wire T84;
wire[15:0] T85;
wire[15:0] T86;
wire[15:0] T87;
reg[15:0] R88;
wire T89;
wire T90;
wire T91;
wire T92;
wire T93;
wire T94;
wire T95;
wire[3:0] T96;
wire T97;
wire[15:0] T98;
wire[15:0] T99;
wire[15:0] T100;
wire T101;
wire[15:0] T102;
reg[15:0] R103;
wire T104;
wire[15:0] T105;
wire T106;
reg[0:0] R107;
wire T108;
wire T109;
wire T110;
wire[31:0] T111;
wire[31:0] T112;
reg[31:0] outputReg_0;
wire[31:0] T113;
assign io_pcOut_valid = R0;
assign T1 = T3 || T2;
assign T2 = ! T3;
assign T3 = T4 && io_pcIn_bits_request;
assign T4 = io_pcIn_valid && T5;
assign T5 = io_pcIn_bits_moduleId == 16'h5/* 5*/;
assign T6 = T2 ? io_pcIn_valid : T7;
assign T7 = T3 ? 1'h1/* 1*/ : R0;
assign io_pcOut_bits_pcType = R8;
assign T9 = T3 || T2;
assign T10 = T11 ? io_pcIn_bits_pcType : R8;
assign T11 = T3 || T2;
assign io_pcOut_bits_portId = R12;
assign T13 = T3 || T2;
assign T14 = T15 ? io_pcIn_bits_portId : R12;
assign T15 = T3 || T2;
assign io_pcOut_bits_pcValue = R16;
assign T17 = T3 || T2;
assign T18 = T2 ? io_pcIn_bits_pcValue : T19;
assign T19 = T3 ? T20 : R16;
assign T20 = T101 ? R88 : R21;
assign T22 = T81 || T23;
assign T23 = T80 && T24;
assign T24 = io_out_valid && T25;
assign T25 = ! io_out_ready;
assign io_out_valid = T26;
assign T26 = T79 && T27;
assign T27 = T28 == 8'hff/* 255*/;
assign T28 = State_0 & T29;
assign T29 = {4'h8/* 8*/{T30}};
assign T30 = T31;
assign T31 = T32[1'h0/* 0*/:1'h0/* 0*/];
assign T32 = 1'h1/* 1*/ << rThreadEncoder_io_chosen;
assign T33 = subStateTh_0 == 1'h0/* 0*/;
assign T34 = T39 ? 1'h1/* 1*/ : T35;
assign T35 = T36 ? 1'h0/* 0*/ : subStateTh_0;
assign T36 = 1'h0/* 0*/ == vThreadEncoder_io_chosen;
assign T37 = T38 && AllOffloadsValid_0;
assign AllOffloadsValid_0 = 1'h1/* 1*/;
assign T38 = subStateTh_0 == 1'h1/* 1*/;
assign T39 = T76 && T40;
assign T40 = State_0 != 8'hff/* 255*/;
assign T41 = T51 || T42;
assign T42 = T50 && T43;
assign T43 = T45 == T44;
assign T44 = {7'h0/* 0*/, 1'h1/* 1*/};
assign T45 = State_0 & T46;
assign T46 = {4'h8/* 8*/{T47}};
assign T47 = T48;
assign T48 = T49[1'h0/* 0*/:1'h0/* 0*/];
assign T49 = 1'h1/* 1*/ << vThreadEncoder_io_chosen;
assign T50 = vThreadEncoder_io_chosen != 1'h1/* 1*/;
assign T51 = T57 || T52;
assign T52 = T53 && T30;
assign T53 = T54 && io_out_ready;
assign T54 = T56 && T55;
assign T55 = T28 == 8'hff/* 255*/;
assign T56 = rThreadEncoder_io_chosen != 1'h1/* 1*/;
assign T57 = T64 && T58;
assign T58 = T59;
assign T59 = T60[1'h0/* 0*/:1'h0/* 0*/];
assign T60 = 1'h1/* 1*/ << sThreadEncoder_io_chosen;
assign T61 = T63 && T62;
assign T62 = State_0 == 8'h0/* 0*/;
assign T63 = subStateTh_0 == 1'h0/* 0*/;
assign T64 = T66 && io_in_valid;
assign io_in_ready = T65;
assign T65 = sThreadEncoder_io_chosen != 1'h1/* 1*/;
assign T66 = sThreadEncoder_io_chosen != 1'h1/* 1*/;
assign T67 = T42 ? T75 : T68;
assign T68 = T52 ? T71 : T69;
assign T69 = T57 ? T70 : State_0;
assign T70 = {7'h0/* 0*/, 1'h1/* 1*/};
assign T71 = EmitReturnState_0 & T72;
assign T72 = {4'h8/* 8*/{T30}};
assign T73 = T42 && T47;
assign T74 = T73 ? 8'h0/* 0*/ : EmitReturnState_0;
assign T75 = {7'h0/* 0*/, 1'h1/* 1*/};
assign T76 = T78 && T77;
assign T77 = State_0 != 8'h0/* 0*/;
assign T78 = 1'h0/* 0*/ == rThreadEncoder_io_chosen;
assign T79 = rThreadEncoder_io_chosen != 1'h1/* 1*/;
assign T80 = ! T81;
assign T81 = T84 && T82;
assign T82 = io_pcIn_bits_pcType == T83;
assign T83 = {2'h0/* 0*/, 2'h2/* 2*/};
assign T84 = io_pcIn_valid && io_pcIn_bits_request;
assign T85 = T23 ? T87 : T86;
assign T86 = T81 ? 16'h0/* 0*/ : R21;
assign T87 = R21 + 16'h1/* 1*/;
assign T89 = T94 || T90;
assign T90 = T93 && T91;
assign T91 = io_in_valid && T92;
assign T92 = ! io_in_ready;
assign T93 = ! T94;
assign T94 = T97 && T95;
assign T95 = io_pcIn_bits_pcType == T96;
assign T96 = {2'h0/* 0*/, 2'h2/* 2*/};
assign T97 = io_pcIn_valid && io_pcIn_bits_request;
assign T98 = T90 ? T100 : T99;
assign T99 = T94 ? 16'h0/* 0*/ : R88;
assign T100 = R88 + 16'h1/* 1*/;
assign T101 = T102 == 16'h1/* 1*/;
assign T102 = {8'h0/* 0*/, io_pcIn_bits_portId};
assign io_pcOut_bits_moduleId = R103;
assign T104 = T3 || T2;
assign T105 = T106 ? io_pcIn_bits_moduleId : R103;
assign T106 = T3 || T2;
assign io_pcOut_bits_request = R107;
assign T108 = T3 || T2;
assign T109 = T2 ? io_pcIn_bits_request : T110;
assign T110 = T3 ? 1'h0/* 0*/ : R107;
assign io_out_bits = T111;
assign T111 = outputReg_0 & T112;
assign T112 = {6'h20/* 32*/{T30}};
assign T113 = T73 ? 32'h2/* 2*/ : outputReg_0;
RREncode_6 rThreadEncoder(
.io_valid_0( T33 ),
.io_chosen( rThreadEncoder_io_chosen ),
.io_ready( ));
RREncode_7 vThreadEncoder(
.io_valid_0( T37 ),
.io_chosen( vThreadEncoder_io_chosen ),
.io_ready( ));
RREncode_8 sThreadEncoder(
.io_valid_0( T61 ),
.io_chosen( sThreadEncoder_io_chosen ),
.io_ready( ));
always @(posedge clk) begin
if(reset) begin
R0 <= 1'h0/* 0*/;
end else if(T1) begin
R0 <= T6;
end
if(reset) begin
R8 <= 4'h0/* 0*/;
end else if(T9) begin
R8 <= T10;
end
if(reset) begin
R12 <= 8'h0/* 0*/;
end else if(T13) begin
R12 <= T14;
end
if(reset) begin
R16 <= 16'h0/* 0*/;
end else if(T17) begin
R16 <= T18;
end
if(reset) begin
R21 <= 16'h0/* 0*/;
end else if(T22) begin
R21 <= T85;
end
subStateTh_0 <= reset ? 1'h0/* 0*/ : T34;
if(reset) begin
State_0 <= 8'h0/* 0*/;
end else if(T41) begin
State_0 <= T67;
end
if(reset) begin
EmitReturnState_0 <= 8'h0/* 0*/;
end else if(T73) begin
EmitReturnState_0 <= T74;
end
if(reset) begin
R88 <= 16'h0/* 0*/;
end else if(T89) begin
R88 <= T98;
end
if(reset) begin
R103 <= 16'h0/* 0*/;
end else if(T104) begin
R103 <= T105;
end
if(reset) begin
R107 <= 1'h1/* 1*/;
end else if(T108) begin
R107 <= T109;
end
if(T73) begin
outputReg_0 <= T113;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFRBP_FUNCTIONAL_V
`define SKY130_FD_SC_MS__SDFRBP_FUNCTIONAL_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_pr/sky130_fd_sc_ms__udp_dff_pr.v"
`celldefine
module sky130_fd_sc_ms__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_ms__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFRBP_FUNCTIONAL_V |
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_handshake (clock, reset, enable, req, ack, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter min_ack_cycle = 0;
parameter max_ack_cycle = 0;
parameter req_drop = 0;
parameter deassert_count = 0;
parameter max_ack_length = 0;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input req;
input ack;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_HANDSHAKE";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/assert_handshake_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_handshake_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_handshake_psl_logic.v"
`else
`endmodule // ovl_handshake
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O211A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__O211A_BEHAVIORAL_PP_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__o211a (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , or0_out, B1, C1 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O211A_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKINV_BEHAVIORAL_V
`define SKY130_FD_SC_LP__CLKINV_BEHAVIORAL_V
/**
* clkinv: Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__clkinv (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKINV_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A311O_TB_V
`define SKY130_FD_SC_MS__A311O_TB_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a311o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ms__a311o dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A311O_TB_V
|
// Generated by FIR Compiler 9.0 [Altera, IP Toolbench 1.3.0 Build 132]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2015 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
module matchfilter (
clk,
reset_n,
ast_sink_data,
ast_sink_valid,
ast_source_ready,
ast_sink_error,
ast_source_data,
ast_sink_ready,
ast_source_valid,
ast_source_error);
input clk;
input reset_n;
input [14:0] ast_sink_data;
input ast_sink_valid;
input ast_source_ready;
input [1:0] ast_sink_error;
output [29:0] ast_source_data;
output ast_sink_ready;
output ast_source_valid;
output [1:0] ast_source_error;
endmodule
|
/*
Copyright (c) 2014-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA top-level module
*/
module fpga (
/*
* Clock: 100MHz
* Reset: Push button, active low
*/
input wire clk,
input wire reset_n,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire [7:0] led,
/*
* I2C
*/
inout wire i2c_scl,
inout wire i2c_sda,
/*
* Ethernet: 1000BASE-T RGMII
*/
input wire phy_rx_clk,
input wire [3:0] phy_rxd,
input wire phy_rx_ctl,
output wire phy_tx_clk,
output wire [3:0] phy_txd,
output wire phy_tx_ctl,
output wire phy_reset_n,
input wire phy_int_n,
input wire phy_pme_n,
/*
* UART: 115200 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd
);
// Clock and reset
wire clk_ibufg;
wire clk_bufg;
wire clk_mmcm_out;
// Internal 125 MHz clock
wire clk_int;
wire rst_int;
wire mmcm_rst = ~reset_n;
wire mmcm_locked;
wire mmcm_clkfb;
IBUFG
clk_ibufg_inst(
.I(clk),
.O(clk_ibufg)
);
wire clk90_mmcm_out;
wire clk90_int;
wire clk_200_mmcm_out;
wire clk_200_int;
// MMCM instance
// 100 MHz in, 125 MHz out
// PFD range: 10 MHz to 550 MHz
// VCO range: 600 MHz to 1200 MHz
// M = 10, D = 1 sets Fvco = 1000 MHz (in range)
// Divide by 8 to get output frequency of 125 MHz
// Need two 125 MHz outputs with 90 degree offset
// Also need 200 MHz out for IODELAY
// 1000 / 5 = 200 MHz
MMCME2_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(8),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(8),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(90),
.CLKOUT2_DIVIDE(5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(10),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(10.0),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_ibufg),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(clk90_mmcm_out),
.CLKOUT1B(),
.CLKOUT2(clk_200_mmcm_out),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_bufg_inst (
.I(clk_mmcm_out),
.O(clk_int)
);
BUFG
clk90_bufg_inst (
.I(clk90_mmcm_out),
.O(clk90_int)
);
BUFG
clk_200_bufg_inst (
.I(clk_200_mmcm_out),
.O(clk_200_int)
);
sync_reset #(
.N(4)
)
sync_reset_inst (
.clk(clk_int),
.rst(~mmcm_locked),
.out(rst_int)
);
// GPIO
wire btnu_int;
wire btnl_int;
wire btnd_int;
wire btnr_int;
wire btnc_int;
wire [7:0] sw_int;
debounce_switch #(
.WIDTH(13),
.N(4),
.RATE(125000)
)
debounce_switch_inst (
.clk(clk_int),
.rst(rst_int),
.in({btnu,
btnl,
btnd,
btnr,
btnc,
sw}),
.out({btnu_int,
btnl_int,
btnd_int,
btnr_int,
btnc_int,
sw_int})
);
sync_signal #(
.WIDTH(1),
.N(2)
)
sync_signal_inst (
.clk(clk_int),
.in({uart_rxd}),
.out({uart_rxd_int})
);
assign i2c_scl_i = i2c_scl;
assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
assign i2c_sda_i = i2c_sda;
assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
// IODELAY elements for RGMII interface to PHY
wire [3:0] phy_rxd_delay;
wire phy_rx_ctl_delay;
IDELAYCTRL
idelayctrl_inst
(
.REFCLK(clk_200_int),
.RST(rst_int),
.RDY()
);
IDELAYE2 #(
.IDELAY_TYPE("FIXED")
)
phy_rxd_idelay_0
(
.IDATAIN(phy_rxd[0]),
.DATAOUT(phy_rxd_delay[0]),
.DATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(5'd0),
.CNTVALUEOUT(),
.LD(1'b0),
.LDPIPEEN(1'b0),
.REGRST(1'b0)
);
IDELAYE2 #(
.IDELAY_TYPE("FIXED")
)
phy_rxd_idelay_1
(
.IDATAIN(phy_rxd[1]),
.DATAOUT(phy_rxd_delay[1]),
.DATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(5'd0),
.CNTVALUEOUT(),
.LD(1'b0),
.LDPIPEEN(1'b0),
.REGRST(1'b0)
);
IDELAYE2 #(
.IDELAY_TYPE("FIXED")
)
phy_rxd_idelay_2
(
.IDATAIN(phy_rxd[2]),
.DATAOUT(phy_rxd_delay[2]),
.DATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(5'd0),
.CNTVALUEOUT(),
.LD(1'b0),
.LDPIPEEN(1'b0),
.REGRST(1'b0)
);
IDELAYE2 #(
.IDELAY_TYPE("FIXED")
)
phy_rxd_idelay_3
(
.IDATAIN(phy_rxd[3]),
.DATAOUT(phy_rxd_delay[3]),
.DATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(5'd0),
.CNTVALUEOUT(),
.LD(1'b0),
.LDPIPEEN(1'b0),
.REGRST(1'b0)
);
IDELAYE2 #(
.IDELAY_TYPE("FIXED")
)
phy_rx_ctl_idelay
(
.IDATAIN(phy_rx_ctl),
.DATAOUT(phy_rx_ctl_delay),
.DATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(5'd0),
.CNTVALUEOUT(),
.LD(1'b0),
.LDPIPEEN(1'b0),
.REGRST(1'b0)
);
fpga_core
core_inst (
/*
* Clock: 125MHz
* Synchronous reset
*/
.clk(clk_int),
.clk90(clk90_int),
.rst(rst_int),
/*
* GPIO
*/
.btnu(btnu_int),
.btnl(btnl_int),
.btnd(btnd_int),
.btnr(btnr_int),
.btnc(btnc_int),
.sw(sw_int),
.led(led),
/*
* I2C
*/
.i2c_scl_i(i2c_scl_i),
.i2c_scl_o(i2c_scl_o),
.i2c_scl_t(i2c_scl_t),
.i2c_sda_i(i2c_sda_i),
.i2c_sda_o(i2c_sda_o),
.i2c_sda_t(i2c_sda_t),
/*
* Ethernet: 1000BASE-T RGMII
*/
.phy_rx_clk(phy_rx_clk),
.phy_rxd(phy_rxd_delay),
.phy_rx_ctl(phy_rx_ctl_delay),
.phy_tx_clk(phy_tx_clk),
.phy_txd(phy_txd),
.phy_tx_ctl(phy_tx_ctl),
.phy_reset_n(phy_reset_n),
.phy_int_n(phy_int_n),
.phy_pme_n(phy_pme_n),
/*
* UART: 115200 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd)
);
endmodule
|
// -*- Mode: Verilog -*-
// Filename : cpu_wrapper.v
// Description : Wrapper around WishBone based CPUs
// Author : Philip Tracton
// Created On : Sun Jul 24 20:57:15 2016
// Last Modified By: Philip Tracton
// Last Modified On: Sun Jul 24 20:57:15 2016
// Update Count : 0
// Status : Unknown, Use with caution!
//`include "wb_soc_includes.vh"
module wishbone_cpu (/*AUTOARG*/
// Outputs
iwbm_adr_o, iwbm_stb_o, iwbm_cyc_o, iwbm_sel_o, iwbm_we_o,
iwbm_cti_o, iwbm_bte_o, iwbm_dat_o, dwbm_adr_o, dwbm_stb_o,
dwbm_cyc_o, dwbm_sel_o, dwbm_we_o, dwbm_cti_o, dwbm_bte_o,
dwbm_dat_o, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o,
dbg_ack_o,
// Inputs
clk_i, rst_i, interrupts, iwbm_err_i, iwbm_ack_i, iwbm_dat_i,
iwbm_rty_i, dwbm_err_i, dwbm_ack_i, dwbm_dat_i, dwbm_rty_i,
dbg_stall_i, dbg_ewt_i, dbg_stb_i, dbg_we_i, dbg_sel_i, dbg_cti_i,
dbg_bte_i, dbg_lock_i, dbg_cyc_i, dbg_adr_i, dbg_dat_i
) ;
parameter NUMBER_OF_INTERRUPTS = 32;
parameter ADDRESS_WIDTH = 32;
parameter DATA_WIDTH = 32;
//
// System Interface
//
input wire clk_i;
input wire rst_i;
input wire [NUMBER_OF_INTERRUPTS-1:0] interrupts;
//
// Instruction Bus
//
output wire [ADDRESS_WIDTH-1:0] iwbm_adr_o;
output wire iwbm_stb_o;
output wire iwbm_cyc_o;
output wire [3:0] iwbm_sel_o;
output wire iwbm_we_o;
output wire [2:0] iwbm_cti_o;
output wire [1:0] iwbm_bte_o;
output wire [DATA_WIDTH-1:0] iwbm_dat_o;
input wire iwbm_err_i;
input wire iwbm_ack_i;
input wire [DATA_WIDTH-1:0] iwbm_dat_i;
input wire iwbm_rty_i;
//
// Data Bus
//
output wire [ADDRESS_WIDTH-1:0] dwbm_adr_o;
output wire dwbm_stb_o;
output wire dwbm_cyc_o;
output wire [3:0] dwbm_sel_o;
output wire dwbm_we_o;
output wire [2:0] dwbm_cti_o;
output wire [1:0] dwbm_bte_o;
output wire [DATA_WIDTH-1:0] dwbm_dat_o;
input wire dwbm_err_i;
input wire dwbm_ack_i;
input wire [DATA_WIDTH-1:0] dwbm_dat_i;
input wire dwbm_rty_i;
//
// Debug interface
//
input wire dbg_stall_i; // External Stall Input
input wire dbg_ewt_i; // External Watchpoint Trigger Input
output wire [3:0] dbg_lss_o; // External Load/Store Unit Status
output wire [1:0] dbg_is_o; // External Insn Fetch Status
output wire [10:0] dbg_wp_o; // Watchpoints Outputs
output wire dbg_bp_o; // Breakpoint Output
input wire dbg_stb_i; // External Address/Data Strobe
input wire dbg_we_i; // External Write Enable
input wire dbg_sel_i; //Debug select
input wire [2:0] dbg_cti_i;//
input wire dbg_bte_i;//
input wire dbg_lock_i;
input wire dbg_cyc_i;
input wire [ADDRESS_WIDTH-1:0] dbg_adr_i; // External Address Input
input wire [DATA_WIDTH-1:0] dbg_dat_i; // External Data Input
output wire [DATA_WIDTH-1:0] dbg_dat_o; // External Data Output
output wire dbg_ack_o; // External Data Acknowledge (not WB compatible)
`ifdef WISHBONE_CPU_LM32
`include "lm32_config.v"
assign dbg_cti_i = 3'b000;
initial begin
$display("INSTANTIATE LM32 CPU");
end
lm32_top cpu(
// ----- Inputs -------
.clk_i(clk_i),
.rst_i(rst_i),
`ifdef CFG_DEBUG_ENABLED
`ifdef CFG_ALTERNATE_EBA
.at_debug(),
`endif
`endif
// From external devices
`ifdef CFG_INTERRUPTS_ENABLED
.interrupt(interrupts),
`endif
// From user logic
`ifdef CFG_USER_ENABLED
.user_result(),
.user_complete(),
`endif
`ifdef CFG_IWB_ENABLED
// Instruction Wishbone master
.I_DAT_I(iwbm_dat_i),
.I_ACK_I(iwbm_ack_i),
.I_ERR_I(iwbm_err_i),
.I_RTY_I(iwbm_rty_i),
`endif
// Data Wishbone master
.D_DAT_I(dwbm_dat_i),
.D_ACK_I(dwbm_ack_i),
.D_ERR_I(dwbm_err_i),
.D_RTY_I(dwbm_rty_i),
// ----- Outputs -------
`ifdef CFG_USER_ENABLED
.user_valid(),
.user_opcode(),
.user_operand_0(),
.user_operand_1(),
`endif
`ifdef CFG_IWB_ENABLED
// Instruction Wishbone master
.I_DAT_O(iwbm_dat_o),
.I_ADR_O(iwbm_adr_o),
.I_CYC_O(iwbm_cyc_o),
.I_SEL_O(iwbm_sel_o),
.I_STB_O(iwbm_stb_o),
.I_WE_O(iwbm_we_o),
.I_CTI_O(iwbm_cti_o),
.I_LOCK_O(),
.I_BTE_O(iwbm_bte_o),
`endif
// Data Wishbone master
.D_DAT_O(dwbm_dat_o),
.D_ADR_O(dwbm_adr_o),
.D_CYC_O(dwbm_cyc_o),
.D_SEL_O(dwbm_sel_o),
.D_STB_O(dwbm_stb_o),
.D_WE_O(dwbm_we_o),
.D_CTI_O(dwbm_cti_o),
.D_LOCK_O(),
.D_BTE_O(dwbm_bte_o)
);
`elsif WISHBONE_CPU_MOR1KX
initial begin
$display("INSTANTIATE MOR1K CPU");
end
mor1kx cpu(
.clk(clk_i),
.rst(rst_i),
// Wishbone interface
.iwbm_adr_o(iwbm_adr_o),
.iwbm_stb_o(iwbm_stb_o),
.iwbm_cyc_o(iwbm_cyc_o),
.iwbm_sel_o(iwbm_sel_o),
.iwbm_we_o(iwbm_we_o),
.iwbm_cti_o(iwbm_cti_o),
.iwbm_bte_o(iwbm_bte_o),
.iwbm_dat_o(iwbm_dat_o),
.iwbm_err_i(iwbm_err_i),
.iwbm_ack_i(iwbm_ack_i),
.iwbm_dat_i(iwbm_dat_i),
.iwbm_rty_i(iwbm_rty_i),
.dwbm_adr_o(dwbm_adr_o),
.dwbm_stb_o(dwbm_stb_o),
.dwbm_cyc_o(dwbm_cyc_o),
.dwbm_sel_o(dwbm_sel_o),
.dwbm_we_o(dwbm_we_o),
.dwbm_cti_o(dwbm_cti_o),
.dwbm_bte_o(dwbm_bte_o),
.dwbm_dat_o(dwbm_dat_o),
.dwbm_err_i(dwbm_err_i),
.dwbm_ack_i(dwbm_ack_i),
.dwbm_dat_i(dwbm_dat_i),
.dwbm_rty_i(dwbm_rty_i),
.irq_i(interrupts),
// Debug interface
.du_addr_i('b0),
.du_stb_i('b0),
.du_dat_i('b0),
.du_we_i('b0),
.du_dat_o(),
.du_ack_o(),
// Stall control from debug interface
.du_stall_i('b0),
.du_stall_o(),
.traceport_exec_valid_o(),
.traceport_exec_pc_o(),
.traceport_exec_insn_o(),
.traceport_exec_wbdata_o(),
.traceport_exec_wbreg_o(),
.traceport_exec_wben_o(),
// The multicore core identifier
.multicore_coreid_i('b0),
// The number of cores
.multicore_numcores_i('b0),
.snoop_adr_i('b0),
.snoop_en_i('b0)
);
`elsif WISHBONE_CPU_OR1200
`include "or1200_defines.v"
initial begin
$display("INSTANTIATE OR1200 CPU");
end
or1200_top cpu(
// System
.clk_i(clk_i),
.rst_i(rst_i),
.pic_ints_i(interrupts),
.clmode_i(2'b00), //WB=RISC
// Instruction WISHBONE INTERFACE
.iwb_clk_i(clk_i),
.iwb_rst_i(rst_i),
.iwb_ack_i(iwbm_ack_i),
.iwb_err_i(iwbm_err_i),
.iwb_rty_i(iwbm_rty_i),
.iwb_dat_i(iwbm_dat_i),
.iwb_cyc_o(iwbm_cyc_o),
.iwb_adr_o(iwbm_adr_o),
.iwb_stb_o(iwbm_stb_o),
.iwb_we_o(iwbm_we_o),
.iwb_sel_o(iwbm_sel_o),
.iwb_dat_o(iwbm_dat_o),
`ifdef OR1200_WB_CAB
.iwb_cab_o(),
`endif
`ifdef OR1200_WB_B3
.iwb_cti_o(iwbm_cti_o),
.iwb_bte_o(iwbm_bte_o),
`endif
// Data WISHBONE INTERFACE
.dwb_clk_i(clk_i),
.dwb_rst_i(rst_i),
.dwb_ack_i(dwbm_ack_i),
.dwb_err_i(dwbm_err_i),
.dwb_rty_i(dwbm_rty_i),
.dwb_dat_i(dwbm_dat_i),
.dwb_cyc_o(dwbm_cyc_o),
.dwb_adr_o(dwbm_adr_o),
.dwb_stb_o(dwbm_stb_o),
.dwb_we_o(dwbm_we_o),
.dwb_sel_o(dwbm_sel_o),
.dwb_dat_o(dwbm_dat_o),
`ifdef OR1200_WB_CAB
.dwb_cab_o(),
`endif
`ifdef OR1200_WB_B3
.dwb_cti_o(dwbm_cti_o),
.dwb_bte_o(dwbm_bte_o),
`endif
// External Debug Interface
.dbg_stall_i(dbg_stall_i),
.dbg_ewt_i(dbg_ewt_i),
.dbg_lss_o(dbg_lss_o),
.dbg_is_o(dbg_is_o),
.dbg_wp_o(dbg_wp_o),
.dbg_bp_o(dbg_bp_o),
.dbg_stb_i(dbg_stb_i),
.dbg_we_i(dbg_we_i),
.dbg_adr_i(dbg_adr_i),
.dbg_dat_i(dbg_dat_i),
.dbg_dat_o(dbg_adr_o),
.dbg_ack_o(dbg_ack_o),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i('b0),
.mbist_so_o(),
.mbist_ctrl_i('b0),
`endif
// Power Management
.pm_cpustall_i('b0),
.pm_clksd_o(),
.pm_dc_gate_o(),
.pm_ic_gate_o(),
.pm_dmmu_gate_o(),
.pm_immu_gate_o(),
.pm_tt_gate_o(),
.pm_cpu_gate_o(),
.pm_wakeup_o(),
.pm_lvolt_o()
,.sig_tick()
);
`elsif WISHBONE_CPU_RISCV
initial begin
$display("INSTANTIATE RISCV CPU");
end
wire [ADDRESS_WIDTH-1:0] rv_wbm_adr_o;
wire rv_wbm_stb_o;
wire rv_wbm_cyc_o;
wire [3:0] rv_wbm_sel_o;
wire rv_wbm_we_o;
wire [2:0] rv_wbm_cti_o;
wire [1:0] rv_wbm_bte_o;
wire [DATA_WIDTH-1:0] rv_wbm_dat_o;
wire rv_wbm_err_i;
wire rv_wbm_ack_i;
wire [DATA_WIDTH-1:0] rv_wbm_dat_i;
wire rv_wbm_rty_i;
wire [31:0] end_of_interrupt;
wire mem_instr;
//
// picorv32 has a single WB interface. Our design has 2. The mem_instr signal indicates if we are fetching
// an instruction (iwbm) or data (dwbm).
//
assign iwbm_adr_o = ( mem_instr) ? rv_wbm_adr_o : 32'b0;
assign dwbm_adr_o = (!mem_instr) ? rv_wbm_adr_o : 32'b0;
assign iwbm_dat_o = ( mem_instr) ? rv_wbm_dat_o : 32'b0;
assign dwbm_dat_o = (!mem_instr) ? rv_wbm_dat_o : 32'b0;
assign iwbm_stb_o = ( mem_instr) ? rv_wbm_stb_o : 1'b0;
assign dwbm_stb_o = (!mem_instr) ? rv_wbm_stb_o : 1'b0;
assign iwbm_cyc_o = ( mem_instr) ? rv_wbm_cyc_o : 1'b0;
assign dwbm_cyc_o = (!mem_instr) ? rv_wbm_cyc_o : 1'b0;
assign iwbm_sel_o = ( mem_instr) ? rv_wbm_sel_o : 1'b0;
assign dwbm_sel_o = (!mem_instr) ? rv_wbm_sel_o : 4'b0;
assign iwbm_cti_o = 3'b0;
assign dwbm_cti_o = 3'b0;
assign iwbm_bte_o = 2'b0;
assign dwbm_bte_o = 2'b0;
assign rv_wbm_dat_i = ( mem_instr) ? iwbm_dat_i : dwbm_dat_i;
assign rv_wbm_err_i = ( mem_instr) ? iwbm_err_i : dwbm_err_i;
assign rv_wbm_ack_i = ( mem_instr) ? iwbm_ack_i : dwbm_ack_i;
assign rv_wbm_rty_i = ( mem_instr) ? iwbm_rty_i : dwbm_rty_i;
picorv32_wb cpu(
.trap(),
// Wishbone interfaces
.wb_rst_i(rst_i),
.wb_clk_i(clk_i),
.wbm_adr_o(rv_wbm_adr_o),
.wbm_dat_o(rv_wbm_dat_o),
.wbm_dat_i(rv_wbm_dat_i),
.wbm_we_o (rv_wbm_we_o ),
.wbm_sel_o(rv_wbm_sel_o),
.wbm_stb_o(rv_wbm_stb_o),
.wbm_ack_i(rv_wbm_ack_i),
.wbm_cyc_o(rv_wbm_cyc_o),
// Pico Co-Processor Interface (PCPI)
.pcpi_valid(),
.pcpi_insn(),
.pcpi_rs1(),
.pcpi_rs2(),
.pcpi_wr(1'b0),
.pcpi_rd(32'b0),
.pcpi_wait(1'b0),
.pcpi_ready(1'b0),
// IRQ interface
.irq(interrupts),
.eoi(end_of_interrupt),
// Trace Interface
.trace_valid(),
.trace_data(),
.mem_instr(mem_instr)
);
`elsif WISHBONE_CPU_ZIP
//
// ZIP has a single WB interface, this design assumes 2
//
wire z_inst_or_data;
wire [29:0] zwbm_adr_o;
wire [DATA_WIDTH-1:0] zwbm_dat_o;
wire zwbm_cyc_o;
wire [3:0] zwbm_sel_o;
wire zwbm_we_o;
wire zwbm_stb_o;
wire zwbm_err_i;
wire zwbm_ack_i;
wire [DATA_WIDTH-1:0] zwbm_dat_i;
wire zwbm_rty_i;
`define ZWBM_INSTR_ADDR_START 32'h00000000
`define ZWBM_INSTR_ADDR_END 32'h00001000
//Determine if this is a instruction or data access
/* -----\/----- EXCLUDED -----\/-----
assign z_inst_or_data = ((zwbm_adr_o >= `ZWBM_INSTR_ADDR_START) && (zwbm_adr_o <`ZWBM_INSTR_ADDR_END));
assign iwbm_adr_o = (z_inst_or_data) ? {2'b00, zwbm_adr_o} : 32'h0;
assign iwbm_dat_o = (z_inst_or_data) ? zwbm_dat_o : 32'h0;
assign iwbm_stb_o = (z_inst_or_data) ? zwbm_stb_o : 0;
assign iwbm_cyc_o = (z_inst_or_data) ? zwbm_cyc_o : 0;
assign iwbm_sel_o = (z_inst_or_data) ? zwbm_sel_o : 0;
assign iwbm_we_o = (z_inst_or_data) ? zwbm_we_o : 0;
assign zwbm_err_i = (z_inst_or_data) ? iwbm_err_i : dwbm_err_i;
assign zwbm_ack_i = (z_inst_or_data) ? iwbm_ack_i : dwbm_ack_i;
assign zwbm_rty_i = (z_inst_or_data) ? iwbm_rty_i : dwbm_rty_i;
assign zwbm_dat_i = (z_inst_or_data) ? iwbm_dat_i : dwbm_dat_i;
assign dwbm_adr_o = (!z_inst_or_data) ? {2'b00,zwbm_adr_o} : 32'h0;
assign dwbm_dat_o = (!z_inst_or_data) ? zwbm_dat_o : 32'h0;
assign dwbm_stb_o = (!z_inst_or_data) ? zwbm_stb_o : 0;
assign dwbm_cyc_o = (!z_inst_or_data) ? zwbm_cyc_o : 0;
assign dwbm_sel_o = (!z_inst_or_data) ? zwbm_sel_o : 0;
assign dwbm_we_o = (!z_inst_or_data) ? zwbm_we_o : 0;
assign dwbm_bte_o = 2'b0;
assign dwbm_cti_o = 3'b0;
-----/\----- EXCLUDED -----/\----- */
assign iwbm_adr_o[31:30] = 2'b00;
assign iwbm_bte_o = 2'b0;
assign iwbm_cti_o = 3'b0;
assign dwbm_adr_o = 32'h0;
assign dwbm_dat_o = 32'h0;
assign dwbm_stb_o = 0;
assign dwbm_cyc_o = 0;
assign dwbm_sel_o = 0;
assign dwbm_we_o = 0;
assign dwbm_bte_o = 2'b0;
assign dwbm_cti_o = 3'b0;
wire lcl_cyc;
wire lcl_stb;
zipcpu #(.RESET_ADDRESS(`ZWBM_INSTR_ADDR_START))
cpu(
.i_clk(clk_i),
.i_rst(rst_i),
.i_interrupt(),
// Debug interface
.i_halt(1'b0),
.i_clear_pf_cache(1'b0),
.i_dbg_reg(5'b0),
.i_dbg_we(1'b0),
.i_dbg_data(32'b0),
.o_dbg_stall(),
.o_dbg_reg(),
.o_dbg_cc(),
.o_break(),
// CPU interface to the wishbone bus
.o_wb_gbl_cyc(iwbm_cyc_o),
.o_wb_gbl_stb(iwbm_stb_o),
.o_wb_lcl_cyc(lcl_cyc),
.o_wb_lcl_stb(lcl_stb),
.o_wb_we(iwbm_we_o),
.o_wb_addr(iwbm_adr_o[29:0]),
.o_wb_data(iwbm_dat_o),
.o_wb_sel(iwbm_sel_o),
.i_wb_ack(iwbm_ack_i),
.i_wb_stall(iwbm_rty_i),
.i_wb_data(iwbm_dat_i),
.i_wb_err(iwbm_err_i),
// Accounting/CPU usage interface
.o_op_stall(),
.o_pf_stall(),
.o_i_count()
`ifdef DEBUG_SCOPE
, o_debug()
`endif
);
`endif // !`elsif WISHBONE_CPU_RISCV
endmodule // wishbone_cpu
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module pulse_gen
#(
parameter BASEADDR = 16'h0000,
parameter HIGHADDR = 16'h0000,
parameter ABUSWIDTH = 16
)(
input wire BUS_CLK,
input wire BUS_RST,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
input wire PULSE_CLK,
input wire EXT_START,
output wire PULSE
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
bus_to_ip #( .BASEADDR(BASEADDR), .HIGHADDR(HIGHADDR), .ABUSWIDTH(ABUSWIDTH) ) i_bus_to_ip
(
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
pulse_gen_core #(.ABUSWIDTH(ABUSWIDTH) ) i_pulse_gen_core
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.BUS_DATA_OUT(IP_DATA_OUT),
.PULSE_CLK(PULSE_CLK),
.EXT_START(EXT_START),
.PULSE(PULSE)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND2B_TB_V
`define SKY130_FD_SC_LP__NAND2B_TB_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand2b.v"
module top();
// Inputs are registered
reg A_N;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A_N = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A_N = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A_N = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A_N = 1'bx;
end
sky130_fd_sc_lp__nand2b dut (.A_N(A_N), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND2B_TB_V
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_nios2_qsys_0_jtag_debug_module_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
nios_system_nios2_qsys_0_jtag_debug_module_tck the_nios_system_nios2_qsys_0_jtag_debug_module_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
nios_system_nios2_qsys_0_jtag_debug_module_sysclk the_nios_system_nios2_qsys_0_jtag_debug_module_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic nios_system_nios2_qsys_0_jtag_debug_module_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam nios_system_nios2_qsys_0_jtag_debug_module_phy.sld_auto_instance_index = "YES",
// nios_system_nios2_qsys_0_jtag_debug_module_phy.sld_instance_index = 0,
// nios_system_nios2_qsys_0_jtag_debug_module_phy.sld_ir_width = 2,
// nios_system_nios2_qsys_0_jtag_debug_module_phy.sld_mfg_id = 70,
// nios_system_nios2_qsys_0_jtag_debug_module_phy.sld_sim_action = "",
// nios_system_nios2_qsys_0_jtag_debug_module_phy.sld_sim_n_scan = 0,
// nios_system_nios2_qsys_0_jtag_debug_module_phy.sld_sim_total_length = 0,
// nios_system_nios2_qsys_0_jtag_debug_module_phy.sld_type_id = 34,
// nios_system_nios2_qsys_0_jtag_debug_module_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
`timescale 1ns/1ps
`default_nettype none
`ifndef VCDFILE
`define VCDFILE "testbench_error_output_logic_tb.vcd"
`endif
module test;
`include "../../../../library/tbassert.v"
localparam ADDR_WIDTH = 10;
localparam DATA_WIDTH = 1;
reg [0:0] rst = 1'b0;
reg [0:0] clk = 1'b0;
reg [0:0] loop_complete = 1'b0;
reg [0:0] error_detected = 1'b0;
reg [7:0] error_state = 8'b0;
reg [ADDR_WIDTH-1:0] error_address = {ADDR_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] expected_data = {DATA_WIDTH{1'b0}};
// Output to UART
reg [0:0] tx_data_accepted = 1'b0;
wire [0:0] tx_data_ready;
wire [7:0] tx_data;
// clock generation
always #1 clk=~clk;
wire [15:0] sw;
wire [15:0] led;
wire tx;
wire rx;
assign sw[0] = rst;
assign sw[1] = loop_complete;
assign sw[2] = error_detected;
assign sw[4:3] = error_state[1:0];
assign sw[14:5] = error_address;
assign sw[15] = expected_data;
assign rx = tx_data_accepted;
assign tx_data = led[7:0];
assign tx_data_ready = led[8];
top unt(
.clk(clk),
.rx(rx),
.tx(tx),
.sw(sw),
.led(led)
);
initial begin
$dumpfile(`VCDFILE);
$dumpvars;
#1.1 // 1
tbassert(clk, "Clock!");
tbassert(!tx_data_ready, "No data");
#1 // 2
tbassert(!clk, "Clock!");
tbassert(!tx_data_ready, "No data");
rst = 1;
#1 // 3
tbassert(clk, "Clock!");
tbassert(!tx_data_ready, "No data");
#1 // 4
tbassert(!clk, "Clock!");
tbassert(!tx_data_ready, "No data");
rst = 0;
#1 // 5
tbassert(clk, "Clock!");
tbassert(!tx_data_ready, "No data");
#1 // 6 : Test simple output
tbassert(!clk, "Clock!");
tbassert(!tx_data_ready, "No data");
loop_complete = 1;
#2 // 8
loop_complete = 0;
#3 // 11
tbassert(clk, "Clock!");
tbassert(tx_data_ready, "Data!");
tbassert(tx_data == "L", "Check data value!");
#1 // 12
tbassert(!clk, "Clock!");
loop_complete = 0;
tx_data_accepted = 1;
#1 // 13
tbassert(clk, "Clock!");
tbassert(!tx_data_ready, "No data");
#1 // 14
tbassert(!clk, "Clock!");
#1 // 15
tbassert(clk, "Clock!");
tbassert(tx_data_ready, "Data!");
tbassert(tx_data == 8'b0, "Check data value!");
#4 // 19
tbassert(clk, "Clock!");
tbassert(tx_data_ready, "Data!");
tbassert(tx_data == 8'b0, "Check data value!");
#4 // 23
tbassert(clk, "Clock!");
tbassert(tx_data_ready, "Data!");
tbassert(tx_data == 8'b0, "Check data value!");
#4 // 27
tbassert(clk, "Clock!");
tbassert(tx_data_ready, "Data!");
tbassert(tx_data == 8'h0D, "Check data value!");
#4 // 31
tbassert(clk, "Clock!");
tbassert(tx_data_ready, "Data!");
tbassert(tx_data == 8'h0A, "Check data value!");
#3 // 34 : Check no extra data
tbassert(!clk, "Clock!");
tbassert(!tx_data_ready, "No data");
#1 // 35
tbassert(clk, "Clock!");
tbassert(!tx_data_ready, "No data");
#1 // 36
tbassert(!clk, "Clock!");
tbassert(!tx_data_ready, "No data");
#1 // 37
tbassert(clk, "Clock!");
tbassert(!tx_data_ready, "No data");
#1 // 38
tbassert(!clk, "Clock!");
error_detected = 1;
error_state = 8'b10;
error_address = 10'h3EF;
expected_data = 1;
#2 // 39
error_detected = 0;
#3 // 39
tbassert(clk, "Clock!");
tbassert(tx_data_ready, "Data!");
tbassert(tx_data == "E", "Check data value!");
#4 // 43
tbassert(clk, "Clock!");
tbassert(tx_data_ready, "Data!");
tbassert(tx_data == 8'b10, "Check error state!");
#4 // 47
tbassert(clk, "Clock!");
tbassert(tx_data_ready, "Data!");
tbassert(tx_data == 8'hEF, "Check addr[0] state!");
#4 // 51
tbassert(clk, "Clock!");
tbassert(tx_data_ready, "Data!");
tbassert(tx_data == 8'h03, "Check addr[1] state!");
#4 // 55
tbassert(clk, "Clock!");
tbassert(tx_data_ready, "Data!");
tbassert(tx_data == 8'b1, "Check expected data[0] state!");
#4 // 59
tbassert(clk, "Clock!");
tbassert(tx_data_ready, "Data!");
tbassert(tx_data == 8'b0, "Check actual data[0] state!");
#4 // 63
tbassert(clk, "Clock!");
tbassert(tx_data_ready, "Data!");
tbassert(tx_data == 8'h0D, "Check data value!");
#4 // 67
tbassert(clk, "Clock!");
tbassert(tx_data_ready, "Data!");
tbassert(tx_data == 8'h0A, "Check data value!");
#3 // 70 : Check no extra data
tbassert(!clk, "Clock!");
tbassert(!tx_data_ready, "No data");
#1 // 71
tbassert(clk, "Clock!");
tbassert(!tx_data_ready, "No data");
#1 // 72
tbassert(!clk, "Clock!");
tbassert(!tx_data_ready, "No data");
#1 // 73
tbassert(clk, "Clock!");
tbassert(!tx_data_ready, "No data");
#1 $finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21BO_BLACKBOX_V
`define SKY130_FD_SC_HD__A21BO_BLACKBOX_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a21bo (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21BO_BLACKBOX_V
|
// sram_0.v
// This file was auto-generated as part of a SOPC Builder generate operation.
// If you edit it your changes will probably be lost.
`timescale 1 ps / 1 ps
module sram_0 (
input wire iCLK, // clk.clk
inout wire [15:0] SRAM_DQ, // avalon_slave_0_export.export
output wire [17:0] SRAM_ADDR, // .export
output wire SRAM_UB_N, // .export
output wire SRAM_LB_N, // .export
output wire SRAM_WE_N, // .export
output wire SRAM_CE_N, // .export
output wire SRAM_OE_N, // .export
input wire [15:0] iDATA, // avalon_slave_0.writedata
output wire [15:0] oDATA, // .readdata
input wire [17:0] iADDR, // .address
input wire iWE_N, // .write_n
input wire iOE_N, // .read_n
input wire iCE_N, // .chipselect_n
input wire [1:0] iBE_N, // .byteenable_n
input wire iRST_N // reset_n.reset_n
);
SRAM_16Bit_512K sram_0 (
.iCLK (iCLK), // clk.clk
.SRAM_DQ (SRAM_DQ), // avalon_slave_0_export.export
.SRAM_ADDR (SRAM_ADDR), // .export
.SRAM_UB_N (SRAM_UB_N), // .export
.SRAM_LB_N (SRAM_LB_N), // .export
.SRAM_WE_N (SRAM_WE_N), // .export
.SRAM_CE_N (SRAM_CE_N), // .export
.SRAM_OE_N (SRAM_OE_N), // .export
.iDATA (iDATA), // avalon_slave_0.writedata
.oDATA (oDATA), // .readdata
.iADDR (iADDR), // .address
.iWE_N (iWE_N), // .write_n
.iOE_N (iOE_N), // .read_n
.iCE_N (iCE_N), // .chipselect_n
.iBE_N (iBE_N), // .byteenable_n
.iRST_N (iRST_N) // reset_n.reset_n
);
endmodule
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Open_Loop_Control.v
// Created: 2014-09-08 14:12:04
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Open_Loop_Control
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control
// Hierarchy Level: 3
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Open_Loop_Control
(
CLK_IN,
reset,
enb_1_2000_0,
reset_1,
command_value,
param_open_loop_bias,
param_open_loop_scalar,
phase_voltages_0,
phase_voltages_1,
phase_voltages_2,
electrical_position
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input reset_1;
input signed [17:0] command_value; // sfix18_En8
input signed [17:0] param_open_loop_bias; // sfix18_En14
input signed [17:0] param_open_loop_scalar; // sfix18_En16
output signed [17:0] phase_voltages_0; // sfix18_En13
output signed [17:0] phase_voltages_1; // sfix18_En13
output signed [17:0] phase_voltages_2; // sfix18_En13
output signed [17:0] electrical_position; // sfix18_En14
wire signed [17:0] direct_voltage; // sfix18_En12
wire signed [17:0] volts_dt; // sfix18_En12
wire signed [17:0] Generate_Position_And_Voltage_Ramp_out2; // sfix18_En14
wire signed [17:0] sin_coefficient; // sfix18_En16
wire signed [17:0] cos_coefficient; // sfix18_En16
wire signed [17:0] Transform_dq_to_ABC_out1_0; // sfix18_En13
wire signed [17:0] Transform_dq_to_ABC_out1_1; // sfix18_En13
wire signed [17:0] Transform_dq_to_ABC_out1_2; // sfix18_En13
// <S15>/Zero
assign direct_voltage = 18'sb000000000000000000;
// <S15>/Generate_Position_And_Voltage_Ramp
controllerHdl_Generate_Position_And_Voltage_Ramp u_Generate_Position_And_Voltage_Ramp (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.Reset_1(reset_1),
.target_velocity(command_value), // sfix18_En8
.param_open_loop_bias(param_open_loop_bias), // sfix18_En14
.param_open_loop_scalar(param_open_loop_scalar), // sfix18_En16
.Q_Voltage(volts_dt), // sfix18_En12
.Position(Generate_Position_And_Voltage_Ramp_out2) // sfix18_En14
);
// <S15>/Sin_Cos
controllerHdl_Sin_Cos u_Sin_Cos (.x(Generate_Position_And_Voltage_Ramp_out2), // sfix18_En14
.sin(sin_coefficient), // sfix18_En16
.cos(cos_coefficient) // sfix18_En16
);
// <S15>/Transform_dq_to_ABC
controllerHdl_Transform_dq_to_ABC u_Transform_dq_to_ABC (.d(direct_voltage), // sfix18_En12
.q(volts_dt), // sfix18_En12
.sin(sin_coefficient), // sfix18_En16
.cos(cos_coefficient), // sfix18_En16
.ABC_0(Transform_dq_to_ABC_out1_0), // sfix18_En13
.ABC_1(Transform_dq_to_ABC_out1_1), // sfix18_En13
.ABC_2(Transform_dq_to_ABC_out1_2) // sfix18_En13
);
assign phase_voltages_0 = Transform_dq_to_ABC_out1_0;
assign phase_voltages_1 = Transform_dq_to_ABC_out1_1;
assign phase_voltages_2 = Transform_dq_to_ABC_out1_2;
assign electrical_position = Generate_Position_And_Voltage_Ramp_out2;
endmodule // controllerHdl_Open_Loop_Control
|
//--------------------------------------------------------------------------------
// prescaler.vhd
//
// Copyright (C) 2006 Michael Poppitz
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details: http://www.sump.org/projects/analyzer/
//
// Shared prescaler for transmitter and receiver timings.
// Used to control the transfer speed.
//
//--------------------------------------------------------------------------------
`timescale 1ns/100ps
module prescaler #(
parameter [31:0] SCALE = 28
)(
input wire clock;
input wire reset;
input wire [1:0] div;
output reg scaled;
);
always @ (*)
scaled = 1'b1;
/*
reg [31:0] counter, next_counter;
reg next_scaled;
always @(posedge clock, posedge reset)
if (reset) begin
counter <= 0;
scaled <= 1'b0;
end else begin
counter <= next_counter;
scaled <= next_scaled;
end
always
begin
next_scaled = 1'b0;
case (div)
2'b00 : next_scaled = (counter == (SCALE-1)); // 115200 baud
2'b01 : next_scaled = (counter == (2*SCALE-1)); // 57600 baud
2'b10 : next_scaled = (counter == (3*SCALE-1)); // 38400 baud
2'b11 : next_scaled = (counter == (6*SCALE-1)); // 19200 baud
endcase
next_counter = counter + 1'b1;
if (next_scaled) next_counter = 0;
end
*/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFRTP_TB_V
`define SKY130_FD_SC_HS__SDFRTP_TB_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sdfrtp.v"
module top();
// Inputs are registered
reg RESET_B;
reg D;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 RESET_B = 1'b1;
#180 SCD = 1'b1;
#200 SCE = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 RESET_B = 1'b0;
#300 SCD = 1'b0;
#320 SCE = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 SCE = 1'b1;
#440 SCD = 1'b1;
#460 RESET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 SCE = 1'bx;
#560 SCD = 1'bx;
#580 RESET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__sdfrtp dut (.RESET_B(RESET_B), .D(D), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFRTP_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EBUFN_1_V
`define SKY130_FD_SC_LS__EBUFN_1_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog wrapper for ebufn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__ebufn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__ebufn_1 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__ebufn_1 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__EBUFN_1_V
|
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29755 $
// $Date: 2012-10-22 13:58:12 +0000 (Mon, 22 Oct 2012) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
`ifdef BSV_RESET_FIFO_HEAD
`define BSV_ARESET_EDGE_HEAD `BSV_ARESET_EDGE_META
`else
`define BSV_ARESET_EDGE_HEAD
`endif
`ifdef BSV_RESET_FIFO_ARRAY
`define BSV_ARESET_EDGE_ARRAY `BSV_ARESET_EDGE_META
`else
`define BSV_ARESET_EDGE_ARRAY
`endif
// Sized "loopy" fifo. Model has output register which improves timing
module SizedFIFOL(CLK, RST, D_IN, ENQ, FULL_N, D_OUT, DEQ, EMPTY_N, CLR);
parameter p1width = 1; // data width
parameter p2depth = 3;
parameter p3cntr_width = 1; // log(p2depth-1)
// The -1 is allowed since this model has a fast output register
localparam p2depth2 = (p2depth >= 2) ? (p2depth -2) : 0 ;
input CLK;
input RST;
input CLR;
input [p1width - 1 : 0] D_IN;
input ENQ;
input DEQ;
output FULL_N;
output EMPTY_N;
output [p1width - 1 : 0] D_OUT;
reg not_ring_full;
reg ring_empty;
reg [p3cntr_width-1 : 0] head;
wire [p3cntr_width-1 : 0] next_head;
reg [p3cntr_width-1 : 0] tail;
wire [p3cntr_width-1 : 0] next_tail;
// if the depth is too small, don't create an ill-sized array;
// instead, make a 1-sized array and let the initial block report an error
reg [p1width - 1 : 0] arr[0: p2depth2];
reg [p1width - 1 : 0] D_OUT;
reg hasodata;
wire [p3cntr_width-1:0] depthLess2 = p2depth2[p3cntr_width-1:0] ;
wire [p3cntr_width-1 : 0] incr_tail;
wire [p3cntr_width-1 : 0] incr_head;
assign incr_tail = tail + 1'b1 ;
assign incr_head = head + 1'b1 ;
assign next_head = (head == depthLess2 ) ? {p3cntr_width{1'b0}} : incr_head ;
assign next_tail = (tail == depthLess2 ) ? {p3cntr_width{1'b0}} : incr_tail ;
assign EMPTY_N = hasodata;
assign FULL_N = not_ring_full || DEQ;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin : initial_block
integer i;
D_OUT = {((p1width + 1)/2){2'b10}} ;
ring_empty = 1'b1;
not_ring_full = 1'b1;
hasodata = 1'b0;
head = {p3cntr_width {1'b0}} ;
tail = {p3cntr_width {1'b0}} ;
for (i = 0; i <= p2depth2; i = i + 1)
begin
arr[i] = D_OUT ;
end
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
always @(posedge CLK `BSV_ARESET_EDGE_META)
begin
if (RST == `BSV_RESET_VALUE)
begin
head <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
tail <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b1;
not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (RST == `BSV_RESET_VALUE)
else
begin
casez ({CLR, DEQ, ENQ, hasodata, ring_empty})
// Clear operation
5'b1????: begin
head <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
tail <= `BSV_ASSIGNMENT_DELAY {p3cntr_width {1'b0}} ;
ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b1;
not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
// -----------------------
// DEQ && ENQ case -- change head and tail if added to ring
5'b011?0: begin
tail <= `BSV_ASSIGNMENT_DELAY next_tail;
head <= `BSV_ASSIGNMENT_DELAY next_head;
end
// -----------------------
// DEQ only and NO data is in ring
5'b010?1: begin
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
// DEQ only and data is in ring (move the head pointer)
5'b010?0: begin
head <= `BSV_ASSIGNMENT_DELAY next_head;
not_ring_full <= `BSV_ASSIGNMENT_DELAY 1'b1;
ring_empty <= `BSV_ASSIGNMENT_DELAY next_head == tail ;
end
// -----------------------
// ENQ only when empty
5'b0010?: begin
hasodata <= `BSV_ASSIGNMENT_DELAY 1'b1;
end
// ENQ only when not empty
5'b0011?: begin
if ( not_ring_full ) // Drop this test to save redundant test
// but be warnned that with test fifo overflow causes loss of new data
// while without test fifo drops all but head entry! (pointer overflow)
begin
tail <= `BSV_ASSIGNMENT_DELAY next_tail;
ring_empty <= `BSV_ASSIGNMENT_DELAY 1'b0;
not_ring_full <= `BSV_ASSIGNMENT_DELAY ! (next_tail == head) ;
end
end
endcase
end // else: !if(RST == `BSV_RESET_VALUE)
end // always @ (posedge CLK)
// Update the fast data out register
always @(posedge CLK `BSV_ARESET_EDGE_HEAD)
begin
`ifdef BSV_RESET_FIFO_HEAD
if (RST == `BSV_RESET_VALUE)
begin
D_OUT <= `BSV_ASSIGNMENT_DELAY {p1width {1'b0}} ;
end // if (RST == `BSV_RESET_VALUE)
else
`endif
begin
casez ({CLR, DEQ, ENQ, hasodata, ring_empty})
// DEQ && ENQ cases
5'b011?0: begin D_OUT <= `BSV_ASSIGNMENT_DELAY arr[head]; end
5'b011?1: begin D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; end
// DEQ only and data is in ring
5'b010?0: begin D_OUT <= `BSV_ASSIGNMENT_DELAY arr[head]; end
// ENQ only when empty
5'b0010?: begin D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN; end
endcase
end // else: !if(RST == `BSV_RESET_VALUE)
end // always @ (posedge CLK)
// Update the memory array reset is OFF
always @(posedge CLK `BSV_ARESET_EDGE_ARRAY)
begin: array
`ifdef BSV_RESET_FIFO_ARRAY
if (RST == `BSV_RESET_VALUE)
begin: rst_array
integer i;
for (i = 0; i <= p2depth2 && p2depth > 2; i = i + 1)
begin
arr[i] <= `BSV_ASSIGNMENT_DELAY {p1width {1'b0}} ;
end
end // if (RST == `BSV_RESET_VALUE)
else
`endif
begin
if (!CLR && ENQ && ((DEQ && !ring_empty) || (!DEQ && hasodata && not_ring_full)))
begin
arr[tail] <= `BSV_ASSIGNMENT_DELAY D_IN;
end
end // else: !if(RST == `BSV_RESET_VALUE)
end // always @ (posedge CLK)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if (RST == ! `BSV_RESET_VALUE)
begin
if ( ! EMPTY_N && DEQ )
begin
deqerror = 1 ;
$display( "Warning: SizedFIFOL: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! FULL_N && ENQ )
begin
enqerror = 1 ;
$display( "Warning: SizedFIFOL: %m -- Enqueuing to a full fifo" ) ;
end
end
end // block: error_checks
// synopsys translate_on
// synopsys translate_off
// Some assertions about parameter values
initial
begin : parameter_assertions
integer ok ;
ok = 1 ;
if ( p2depth <= 1)
begin
ok = 0;
$display ( "Warning SizedFIFOL: %m -- depth parameter increased from %0d to 2", p2depth);
end
if ( p3cntr_width <= 0 )
begin
ok = 0;
$display ( "ERROR SizedFIFOL: %m -- width parameter must be greater than 0" ) ;
end
if ( ok == 0 ) $finish ;
end // initial begin
// synopsys translate_on
endmodule
|
/*
* Copyright (c) 2014 CERN
* @author Maciej Suminski <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// Test for VPI functions handling dynamic arrays
module main();
initial
begin
int int_darray[];
real real_darray[];
bit [63:0] bit_darray[];
string string_darray[];
int_darray = new[4];
int_darray = '{1, 2, 3, 4};
$display_array(int_darray);
$increase_array_vals(int_darray);
real_darray = new[2];
real_darray = '{2.2, 2.3};
$increase_array_vals(real_darray);
$display_array(real_darray);
bit_darray = new[4];
bit_darray = '{64'hdeadbeefcafebabe, 64'h0badc0dec0dec0de,
64'h0123456789abcdef, 64'hfedcba9876543210};
$increase_array_vals(bit_darray);
$display_array(bit_darray);
string_darray = new[4];
string_darray = '{"test string", "another one", "yet one more", "the last one"};
$increase_array_vals(string_darray);
$display_array(string_darray);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDLCLKP_BLACKBOX_V
`define SKY130_FD_SC_HD__SDLCLKP_BLACKBOX_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sdlclkp (
GCLK,
SCE ,
GATE,
CLK
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDLCLKP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRTP_2_V
`define SKY130_FD_SC_LP__DLRTP_2_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog wrapper for dlrtp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrtp_2 (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrtp_2 (
Q ,
RESET_B,
D ,
GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRTP_2_V
|
//
// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
//
// On Mon Feb 3 15:04:58 EST 2014
//
//
// Ports:
// Name I/O size props
// wciS0_SResp O 2 reg
// wciS0_SData O 32 reg
// wciS0_SThreadBusy O 1
// wciS0_SFlag O 2
// wsiS0_SThreadBusy O 1
// wsiS0_SReset_n O 1
// wsiM0_MCmd O 3
// wsiM0_MReqLast O 1
// wsiM0_MBurstPrecise O 1
// wsiM0_MBurstLength O 12
// wsiM0_MData O 64 reg
// wsiM0_MByteEn O 8 reg
// wsiM0_MReqInfo O 8
// wsiM0_MReset_n O 1
// wciS0_Clk I 1 clock
// wciS0_MReset_n I 1 reset
// wciS0_MCmd I 3
// wciS0_MAddrSpace I 1
// wciS0_MByteEn I 4
// wciS0_MAddr I 32
// wciS0_MData I 32
// wciS0_MFlag I 2 unused
// wsiS0_MCmd I 3
// wsiS0_MBurstLength I 12
// wsiS0_MData I 64
// wsiS0_MByteEn I 8
// wsiS0_MReqInfo I 8
// wsiS0_MReqLast I 1
// wsiS0_MBurstPrecise I 1
// wsiS0_MReset_n I 1 reg
// wsiM0_SThreadBusy I 1 reg
// wsiM0_SReset_n I 1 reg
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkBiasWorker8B(wciS0_Clk,
wciS0_MReset_n,
wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData,
wciS0_SResp,
wciS0_SData,
wciS0_SThreadBusy,
wciS0_SFlag,
wciS0_MFlag,
wsiS0_MCmd,
wsiS0_MReqLast,
wsiS0_MBurstPrecise,
wsiS0_MBurstLength,
wsiS0_MData,
wsiS0_MByteEn,
wsiS0_MReqInfo,
wsiS0_SThreadBusy,
wsiS0_SReset_n,
wsiS0_MReset_n,
wsiM0_MCmd,
wsiM0_MReqLast,
wsiM0_MBurstPrecise,
wsiM0_MBurstLength,
wsiM0_MData,
wsiM0_MByteEn,
wsiM0_MReqInfo,
wsiM0_SThreadBusy,
wsiM0_MReset_n,
wsiM0_SReset_n);
parameter [0 : 0] hasDebugLogic = 1'b0;
input wciS0_Clk;
input wciS0_MReset_n;
// action method wciS0_mCmd
input [2 : 0] wciS0_MCmd;
// action method wciS0_mAddrSpace
input wciS0_MAddrSpace;
// action method wciS0_mByteEn
input [3 : 0] wciS0_MByteEn;
// action method wciS0_mAddr
input [31 : 0] wciS0_MAddr;
// action method wciS0_mData
input [31 : 0] wciS0_MData;
// value method wciS0_sResp
output [1 : 0] wciS0_SResp;
// value method wciS0_sData
output [31 : 0] wciS0_SData;
// value method wciS0_sThreadBusy
output wciS0_SThreadBusy;
// value method wciS0_sFlag
output [1 : 0] wciS0_SFlag;
// action method wciS0_mFlag
input [1 : 0] wciS0_MFlag;
// action method wsiS0_mCmd
input [2 : 0] wsiS0_MCmd;
// action method wsiS0_mReqLast
input wsiS0_MReqLast;
// action method wsiS0_mBurstPrecise
input wsiS0_MBurstPrecise;
// action method wsiS0_mBurstLength
input [11 : 0] wsiS0_MBurstLength;
// action method wsiS0_mData
input [63 : 0] wsiS0_MData;
// action method wsiS0_mByteEn
input [7 : 0] wsiS0_MByteEn;
// action method wsiS0_mReqInfo
input [7 : 0] wsiS0_MReqInfo;
// action method wsiS0_mDataInfo
// value method wsiS0_sThreadBusy
output wsiS0_SThreadBusy;
// value method wsiS0_sReset_n
output wsiS0_SReset_n;
// action method wsiS0_mReset_n
input wsiS0_MReset_n;
// value method wsiM0_mCmd
output [2 : 0] wsiM0_MCmd;
// value method wsiM0_mReqLast
output wsiM0_MReqLast;
// value method wsiM0_mBurstPrecise
output wsiM0_MBurstPrecise;
// value method wsiM0_mBurstLength
output [11 : 0] wsiM0_MBurstLength;
// value method wsiM0_mData
output [63 : 0] wsiM0_MData;
// value method wsiM0_mByteEn
output [7 : 0] wsiM0_MByteEn;
// value method wsiM0_mReqInfo
output [7 : 0] wsiM0_MReqInfo;
// value method wsiM0_mDataInfo
// action method wsiM0_sThreadBusy
input wsiM0_SThreadBusy;
// value method wsiM0_mReset_n
output wsiM0_MReset_n;
// action method wsiM0_sReset_n
input wsiM0_SReset_n;
// signals for module outputs
wire [63 : 0] wsiM0_MData;
wire [31 : 0] wciS0_SData;
wire [11 : 0] wsiM0_MBurstLength;
wire [7 : 0] wsiM0_MByteEn, wsiM0_MReqInfo;
wire [2 : 0] wsiM0_MCmd;
wire [1 : 0] wciS0_SFlag, wciS0_SResp;
wire wciS0_SThreadBusy,
wsiM0_MBurstPrecise,
wsiM0_MReqLast,
wsiM0_MReset_n,
wsiS0_SReset_n,
wsiS0_SThreadBusy;
// inlined wires
wire [96 : 0] wsiM_reqFifo_x_wire_wget, wsiS_wsiReq_wget;
wire [95 : 0] wsiM_extStatusW_wget, wsiS_extStatusW_wget;
wire [71 : 0] wci_wslv_wciReq_wget;
wire [63 : 0] wsi_Es_mData_w_wget;
wire [33 : 0] wci_wslv_respF_x_wire_wget;
wire [31 : 0] wci_wci_Es_mAddr_w_wget, wci_wci_Es_mData_w_wget;
wire [11 : 0] wsi_Es_mBurstLength_w_wget;
wire [7 : 0] wsi_Es_mByteEn_w_wget, wsi_Es_mReqInfo_w_wget;
wire [3 : 0] wci_wci_Es_mByteEn_w_wget;
wire [2 : 0] wci_wci_Es_mCmd_w_wget,
wci_wslv_wEdge_wget,
wsi_Es_mCmd_w_wget;
wire wci_wci_Es_mAddrSpace_w_wget,
wci_wci_Es_mAddrSpace_w_whas,
wci_wci_Es_mAddr_w_whas,
wci_wci_Es_mByteEn_w_whas,
wci_wci_Es_mCmd_w_whas,
wci_wci_Es_mData_w_whas,
wci_wslv_ctlAckReg_1_wget,
wci_wslv_ctlAckReg_1_whas,
wci_wslv_reqF_r_clr_whas,
wci_wslv_reqF_r_deq_whas,
wci_wslv_reqF_r_enq_whas,
wci_wslv_respF_dequeueing_whas,
wci_wslv_respF_enqueueing_whas,
wci_wslv_respF_x_wire_whas,
wci_wslv_sFlagReg_1_wget,
wci_wslv_sFlagReg_1_whas,
wci_wslv_sThreadBusy_pw_whas,
wci_wslv_wEdge_whas,
wci_wslv_wciReq_whas,
wci_wslv_wci_cfrd_pw_whas,
wci_wslv_wci_cfwr_pw_whas,
wci_wslv_wci_ctrl_pw_whas,
wsiM_operateD_1_wget,
wsiM_operateD_1_whas,
wsiM_peerIsReady_1_wget,
wsiM_peerIsReady_1_whas,
wsiM_reqFifo_dequeueing_whas,
wsiM_reqFifo_enqueueing_whas,
wsiM_reqFifo_x_wire_whas,
wsiM_sThreadBusy_pw_whas,
wsiS_operateD_1_wget,
wsiS_operateD_1_whas,
wsiS_peerIsReady_1_wget,
wsiS_peerIsReady_1_whas,
wsiS_reqFifo_doResetClr_whas,
wsiS_reqFifo_doResetDeq_whas,
wsiS_reqFifo_doResetEnq_whas,
wsiS_reqFifo_r_clr_whas,
wsiS_reqFifo_r_deq_whas,
wsiS_reqFifo_r_enq_whas,
wsiS_sThreadBusy_dw_wget,
wsiS_sThreadBusy_dw_whas,
wsiS_wsiReq_whas,
wsi_Es_mBurstLength_w_whas,
wsi_Es_mBurstPrecise_w_whas,
wsi_Es_mByteEn_w_whas,
wsi_Es_mCmd_w_whas,
wsi_Es_mDataInfo_w_whas,
wsi_Es_mData_w_whas,
wsi_Es_mReqInfo_w_whas,
wsi_Es_mReqLast_w_whas;
// register biasValue
reg [31 : 0] biasValue;
wire [31 : 0] biasValue_D_IN;
wire biasValue_EN;
// register controlReg
reg [31 : 0] controlReg;
wire [31 : 0] controlReg_D_IN;
wire controlReg_EN;
// register wci_wslv_cEdge
reg [2 : 0] wci_wslv_cEdge;
wire [2 : 0] wci_wslv_cEdge_D_IN;
wire wci_wslv_cEdge_EN;
// register wci_wslv_cState
reg [2 : 0] wci_wslv_cState;
wire [2 : 0] wci_wslv_cState_D_IN;
wire wci_wslv_cState_EN;
// register wci_wslv_ctlAckReg
reg wci_wslv_ctlAckReg;
wire wci_wslv_ctlAckReg_D_IN, wci_wslv_ctlAckReg_EN;
// register wci_wslv_ctlOpActive
reg wci_wslv_ctlOpActive;
wire wci_wslv_ctlOpActive_D_IN, wci_wslv_ctlOpActive_EN;
// register wci_wslv_illegalEdge
reg wci_wslv_illegalEdge;
wire wci_wslv_illegalEdge_D_IN, wci_wslv_illegalEdge_EN;
// register wci_wslv_isReset_isInReset
reg wci_wslv_isReset_isInReset;
wire wci_wslv_isReset_isInReset_D_IN, wci_wslv_isReset_isInReset_EN;
// register wci_wslv_nState
reg [2 : 0] wci_wslv_nState;
reg [2 : 0] wci_wslv_nState_D_IN;
wire wci_wslv_nState_EN;
// register wci_wslv_reqF_countReg
reg [1 : 0] wci_wslv_reqF_countReg;
wire [1 : 0] wci_wslv_reqF_countReg_D_IN;
wire wci_wslv_reqF_countReg_EN;
// register wci_wslv_respF_cntr_r
reg [1 : 0] wci_wslv_respF_cntr_r;
wire [1 : 0] wci_wslv_respF_cntr_r_D_IN;
wire wci_wslv_respF_cntr_r_EN;
// register wci_wslv_respF_q_0
reg [33 : 0] wci_wslv_respF_q_0;
reg [33 : 0] wci_wslv_respF_q_0_D_IN;
wire wci_wslv_respF_q_0_EN;
// register wci_wslv_respF_q_1
reg [33 : 0] wci_wslv_respF_q_1;
reg [33 : 0] wci_wslv_respF_q_1_D_IN;
wire wci_wslv_respF_q_1_EN;
// register wci_wslv_sFlagReg
reg wci_wslv_sFlagReg;
wire wci_wslv_sFlagReg_D_IN, wci_wslv_sFlagReg_EN;
// register wci_wslv_sThreadBusy_d
reg wci_wslv_sThreadBusy_d;
wire wci_wslv_sThreadBusy_d_D_IN, wci_wslv_sThreadBusy_d_EN;
// register wsiM_burstKind
reg [1 : 0] wsiM_burstKind;
wire [1 : 0] wsiM_burstKind_D_IN;
wire wsiM_burstKind_EN;
// register wsiM_errorSticky
reg wsiM_errorSticky;
wire wsiM_errorSticky_D_IN, wsiM_errorSticky_EN;
// register wsiM_iMesgCount
reg [31 : 0] wsiM_iMesgCount;
wire [31 : 0] wsiM_iMesgCount_D_IN;
wire wsiM_iMesgCount_EN;
// register wsiM_isReset_isInReset
reg wsiM_isReset_isInReset;
wire wsiM_isReset_isInReset_D_IN, wsiM_isReset_isInReset_EN;
// register wsiM_operateD
reg wsiM_operateD;
wire wsiM_operateD_D_IN, wsiM_operateD_EN;
// register wsiM_pMesgCount
reg [31 : 0] wsiM_pMesgCount;
wire [31 : 0] wsiM_pMesgCount_D_IN;
wire wsiM_pMesgCount_EN;
// register wsiM_peerIsReady
reg wsiM_peerIsReady;
wire wsiM_peerIsReady_D_IN, wsiM_peerIsReady_EN;
// register wsiM_reqFifo_cntr_r
reg [1 : 0] wsiM_reqFifo_cntr_r;
wire [1 : 0] wsiM_reqFifo_cntr_r_D_IN;
wire wsiM_reqFifo_cntr_r_EN;
// register wsiM_reqFifo_q_0
reg [96 : 0] wsiM_reqFifo_q_0;
reg [96 : 0] wsiM_reqFifo_q_0_D_IN;
wire wsiM_reqFifo_q_0_EN;
// register wsiM_reqFifo_q_1
reg [96 : 0] wsiM_reqFifo_q_1;
reg [96 : 0] wsiM_reqFifo_q_1_D_IN;
wire wsiM_reqFifo_q_1_EN;
// register wsiM_sThreadBusy_d
reg wsiM_sThreadBusy_d;
wire wsiM_sThreadBusy_d_D_IN, wsiM_sThreadBusy_d_EN;
// register wsiM_statusR
reg [7 : 0] wsiM_statusR;
wire [7 : 0] wsiM_statusR_D_IN;
wire wsiM_statusR_EN;
// register wsiM_tBusyCount
reg [31 : 0] wsiM_tBusyCount;
wire [31 : 0] wsiM_tBusyCount_D_IN;
wire wsiM_tBusyCount_EN;
// register wsiM_trafficSticky
reg wsiM_trafficSticky;
wire wsiM_trafficSticky_D_IN, wsiM_trafficSticky_EN;
// register wsiS_burstKind
reg [1 : 0] wsiS_burstKind;
wire [1 : 0] wsiS_burstKind_D_IN;
wire wsiS_burstKind_EN;
// register wsiS_errorSticky
reg wsiS_errorSticky;
wire wsiS_errorSticky_D_IN, wsiS_errorSticky_EN;
// register wsiS_iMesgCount
reg [31 : 0] wsiS_iMesgCount;
wire [31 : 0] wsiS_iMesgCount_D_IN;
wire wsiS_iMesgCount_EN;
// register wsiS_isReset_isInReset
reg wsiS_isReset_isInReset;
wire wsiS_isReset_isInReset_D_IN, wsiS_isReset_isInReset_EN;
// register wsiS_mesgWordLength
reg [11 : 0] wsiS_mesgWordLength;
wire [11 : 0] wsiS_mesgWordLength_D_IN;
wire wsiS_mesgWordLength_EN;
// register wsiS_operateD
reg wsiS_operateD;
wire wsiS_operateD_D_IN, wsiS_operateD_EN;
// register wsiS_pMesgCount
reg [31 : 0] wsiS_pMesgCount;
wire [31 : 0] wsiS_pMesgCount_D_IN;
wire wsiS_pMesgCount_EN;
// register wsiS_peerIsReady
reg wsiS_peerIsReady;
wire wsiS_peerIsReady_D_IN, wsiS_peerIsReady_EN;
// register wsiS_reqFifo_countReg
reg [1 : 0] wsiS_reqFifo_countReg;
wire [1 : 0] wsiS_reqFifo_countReg_D_IN;
wire wsiS_reqFifo_countReg_EN;
// register wsiS_reqFifo_levelsValid
reg wsiS_reqFifo_levelsValid;
wire wsiS_reqFifo_levelsValid_D_IN, wsiS_reqFifo_levelsValid_EN;
// register wsiS_statusR
reg [7 : 0] wsiS_statusR;
wire [7 : 0] wsiS_statusR_D_IN;
wire wsiS_statusR_EN;
// register wsiS_tBusyCount
reg [31 : 0] wsiS_tBusyCount;
wire [31 : 0] wsiS_tBusyCount_D_IN;
wire wsiS_tBusyCount_EN;
// register wsiS_trafficSticky
reg wsiS_trafficSticky;
wire wsiS_trafficSticky_D_IN, wsiS_trafficSticky_EN;
// register wsiS_wordCount
reg [11 : 0] wsiS_wordCount;
wire [11 : 0] wsiS_wordCount_D_IN;
wire wsiS_wordCount_EN;
// ports of submodule wci_wslv_reqF
wire [71 : 0] wci_wslv_reqF_D_IN, wci_wslv_reqF_D_OUT;
wire wci_wslv_reqF_CLR,
wci_wslv_reqF_DEQ,
wci_wslv_reqF_EMPTY_N,
wci_wslv_reqF_ENQ;
// ports of submodule wsiS_reqFifo
wire [96 : 0] wsiS_reqFifo_D_IN, wsiS_reqFifo_D_OUT;
wire wsiS_reqFifo_CLR,
wsiS_reqFifo_DEQ,
wsiS_reqFifo_EMPTY_N,
wsiS_reqFifo_ENQ,
wsiS_reqFifo_FULL_N;
// rule scheduling signals
wire WILL_FIRE_RL_wci_cfrd,
WILL_FIRE_RL_wci_cfwr,
WILL_FIRE_RL_wci_ctrl_IsO,
WILL_FIRE_RL_wci_ctrl_OrE,
WILL_FIRE_RL_wci_wslv_ctl_op_complete,
WILL_FIRE_RL_wci_wslv_ctl_op_start,
WILL_FIRE_RL_wci_wslv_respF_both,
WILL_FIRE_RL_wci_wslv_respF_decCtr,
WILL_FIRE_RL_wci_wslv_respF_incCtr,
WILL_FIRE_RL_wsiM_reqFifo_both,
WILL_FIRE_RL_wsiM_reqFifo_decCtr,
WILL_FIRE_RL_wsiM_reqFifo_deq,
WILL_FIRE_RL_wsiM_reqFifo_incCtr,
WILL_FIRE_RL_wsiS_reqFifo_enq,
WILL_FIRE_RL_wsiS_reqFifo_reset;
// inputs to muxes for submodule ports
reg [33 : 0] MUX_wci_wslv_respF_q_0_write_1__VAL_2;
wire [96 : 0] MUX_wsiM_reqFifo_q_0_write_1__VAL_1,
MUX_wsiM_reqFifo_q_0_write_1__VAL_2,
MUX_wsiM_reqFifo_q_1_write_1__VAL_1;
wire [33 : 0] MUX_wci_wslv_respF_q_0_write_1__VAL_1,
MUX_wci_wslv_respF_q_1_write_1__VAL_1,
MUX_wci_wslv_respF_x_wire_wset_1__VAL_1,
MUX_wci_wslv_respF_x_wire_wset_1__VAL_2;
wire [1 : 0] MUX_wci_wslv_respF_cntr_r_write_1__VAL_2,
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1,
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2;
wire MUX_biasValue_write_1__SEL_1,
MUX_biasValue_write_1__SEL_2,
MUX_controlReg_write_1__SEL_1,
MUX_wci_wslv_illegalEdge_write_1__SEL_1,
MUX_wci_wslv_illegalEdge_write_1__VAL_1,
MUX_wci_wslv_respF_q_0_write_1__SEL_1,
MUX_wci_wslv_respF_q_0_write_1__SEL_2,
MUX_wci_wslv_respF_q_1_write_1__SEL_1,
MUX_wci_wslv_respF_q_1_write_1__SEL_2,
MUX_wsiM_reqFifo_q_0_write_1__SEL_1,
MUX_wsiM_reqFifo_q_0_write_1__SEL_2,
MUX_wsiM_reqFifo_q_1_write_1__SEL_1,
MUX_wsiM_reqFifo_q_1_write_1__SEL_2,
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3;
// remaining internal signals
reg [63 : 0] v__h10832, v__h10987, v__h3574, v__h3749, v__h3893;
reg [31 : 0] _theResult____h10971;
wire [63 : 0] x_data__h10099;
wire [31 : 0] rdat__h11061,
rdat__h11161,
rdat__h11175,
rdat__h11183,
rdat__h11189,
rdat__h11203,
rdat__h11211;
wire [15 : 0] x__h11065;
wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27;
wire _dfoo1, _dfoo3, _dfoo5, _dfoo7;
// value method wciS0_sResp
assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ;
// value method wciS0_sData
assign wciS0_SData = wci_wslv_respF_q_0[31:0] ;
// value method wciS0_sThreadBusy
assign wciS0_SThreadBusy =
wci_wslv_reqF_countReg > 2'd1 || wci_wslv_isReset_isInReset ;
// value method wciS0_sFlag
assign wciS0_SFlag = { 1'd1, wci_wslv_sFlagReg } ;
// value method wsiS0_sThreadBusy
assign wsiS0_SThreadBusy =
!wsiS_sThreadBusy_dw_whas || wsiS_sThreadBusy_dw_wget ;
// value method wsiS0_sReset_n
assign wsiS0_SReset_n = !wsiS_isReset_isInReset && wsiS_operateD ;
// value method wsiM0_mCmd
assign wsiM0_MCmd = wsiM_sThreadBusy_d ? 3'd0 : wsiM_reqFifo_q_0[96:94] ;
// value method wsiM0_mReqLast
assign wsiM0_MReqLast = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[93] ;
// value method wsiM0_mBurstPrecise
assign wsiM0_MBurstPrecise = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[92] ;
// value method wsiM0_mBurstLength
assign wsiM0_MBurstLength =
wsiM_sThreadBusy_d ? 12'd0 : wsiM_reqFifo_q_0[91:80] ;
// value method wsiM0_mData
assign wsiM0_MData = wsiM_reqFifo_q_0[79:16] ;
// value method wsiM0_mByteEn
assign wsiM0_MByteEn = wsiM_reqFifo_q_0[15:8] ;
// value method wsiM0_mReqInfo
assign wsiM0_MReqInfo = wsiM_sThreadBusy_d ? 8'd0 : wsiM_reqFifo_q_0[7:0] ;
// value method wsiM0_mReset_n
assign wsiM0_MReset_n = !wsiM_isReset_isInReset && wsiM_operateD ;
// submodule wci_wslv_reqF
SizedFIFO #(.p1width(32'd72),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wci_wslv_reqF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wci_wslv_reqF_D_IN),
.ENQ(wci_wslv_reqF_ENQ),
.DEQ(wci_wslv_reqF_DEQ),
.CLR(wci_wslv_reqF_CLR),
.D_OUT(wci_wslv_reqF_D_OUT),
.FULL_N(),
.EMPTY_N(wci_wslv_reqF_EMPTY_N));
// submodule wsiS_reqFifo
SizedFIFO #(.p1width(32'd97),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wsiS_reqFifo(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wsiS_reqFifo_D_IN),
.ENQ(wsiS_reqFifo_ENQ),
.DEQ(wsiS_reqFifo_DEQ),
.CLR(wsiS_reqFifo_CLR),
.D_OUT(wsiS_reqFifo_D_OUT),
.FULL_N(wsiS_reqFifo_FULL_N),
.EMPTY_N(wsiS_reqFifo_EMPTY_N));
// rule RL_wci_wslv_ctl_op_start
assign WILL_FIRE_RL_wci_wslv_ctl_op_start =
wci_wslv_reqF_EMPTY_N && wci_wslv_wci_ctrl_pw_whas &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wci_ctrl_IsO
assign WILL_FIRE_RL_wci_ctrl_IsO =
wci_wslv_wci_ctrl_pw_whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd1 &&
wci_wslv_reqF_D_OUT[36:34] == 3'd1 ;
// rule RL_wci_ctrl_OrE
assign WILL_FIRE_RL_wci_ctrl_OrE =
wci_wslv_wci_ctrl_pw_whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd2 &&
wci_wslv_reqF_D_OUT[36:34] == 3'd3 ;
// rule RL_wci_cfwr
assign WILL_FIRE_RL_wci_cfwr =
wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF_EMPTY_N &&
wci_wslv_wci_cfwr_pw_whas &&
!WILL_FIRE_RL_wci_wslv_ctl_op_start &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wci_wslv_ctl_op_complete
assign WILL_FIRE_RL_wci_wslv_ctl_op_complete =
wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_ctlOpActive &&
wci_wslv_ctlAckReg ;
// rule RL_wci_cfrd
assign WILL_FIRE_RL_wci_cfrd =
wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF_EMPTY_N &&
wci_wslv_wci_cfrd_pw_whas &&
!WILL_FIRE_RL_wci_wslv_ctl_op_start &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wci_wslv_respF_incCtr
assign WILL_FIRE_RL_wci_wslv_respF_incCtr =
wci_wslv_respF_x_wire_whas && wci_wslv_respF_enqueueing_whas &&
!(wci_wslv_respF_cntr_r != 2'd0) ;
// rule RL_wci_wslv_respF_decCtr
assign WILL_FIRE_RL_wci_wslv_respF_decCtr =
wci_wslv_respF_cntr_r != 2'd0 &&
!wci_wslv_respF_enqueueing_whas ;
// rule RL_wci_wslv_respF_both
assign WILL_FIRE_RL_wci_wslv_respF_both =
wci_wslv_respF_x_wire_whas && wci_wslv_respF_cntr_r != 2'd0 &&
wci_wslv_respF_enqueueing_whas ;
// rule RL_wsiM_reqFifo_deq
assign WILL_FIRE_RL_wsiM_reqFifo_deq =
wsiM_reqFifo_cntr_r != 2'd0 && !wsiM_sThreadBusy_d ;
// rule RL_wsiM_reqFifo_incCtr
assign WILL_FIRE_RL_wsiM_reqFifo_incCtr =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 &&
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 &&
!WILL_FIRE_RL_wsiM_reqFifo_deq ;
// rule RL_wsiM_reqFifo_decCtr
assign WILL_FIRE_RL_wsiM_reqFifo_decCtr =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
!MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
// rule RL_wsiM_reqFifo_both
assign WILL_FIRE_RL_wsiM_reqFifo_both =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 &&
WILL_FIRE_RL_wsiM_reqFifo_deq &&
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
// rule RL_wsiS_reqFifo_enq
assign WILL_FIRE_RL_wsiS_reqFifo_enq =
wsiS_reqFifo_FULL_N && wsiS_operateD && wsiS_peerIsReady &&
wsiS_wsiReq_wget[96:94] == 3'd1 ;
// rule RL_wsiS_reqFifo_reset
assign WILL_FIRE_RL_wsiS_reqFifo_reset =
WILL_FIRE_RL_wsiS_reqFifo_enq ||
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
// inputs to muxes for submodule ports
assign MUX_biasValue_write_1__SEL_1 =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h0 ;
assign MUX_biasValue_write_1__SEL_2 =
wci_wslv_wci_ctrl_pw_whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd0 &&
wci_wslv_reqF_D_OUT[36:34] == 3'd0 ;
assign MUX_controlReg_write_1__SEL_1 =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h04 ;
assign MUX_wci_wslv_illegalEdge_write_1__SEL_1 =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF_D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 &&
wci_wslv_cState != 3'd3 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd2 && wci_wslv_cState != 3'd2 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd3 && wci_wslv_cState != 3'd3 &&
wci_wslv_cState != 3'd2 &&
wci_wslv_cState != 3'd1 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd4 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd5 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd6 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd7) ;
assign MUX_wci_wslv_respF_q_0_write_1__SEL_1 =
WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 ;
assign MUX_wci_wslv_respF_q_0_write_1__SEL_2 =
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_cntr_r == 2'd0 ;
assign MUX_wci_wslv_respF_q_1_write_1__SEL_1 =
WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 ;
assign MUX_wci_wslv_respF_q_1_write_1__SEL_2 =
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_cntr_r == 2'd1 ;
assign MUX_wsiM_reqFifo_q_0_write_1__SEL_1 =
WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo7 ;
assign MUX_wsiM_reqFifo_q_0_write_1__SEL_2 =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd0 ;
assign MUX_wsiM_reqFifo_q_1_write_1__SEL_1 =
WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo5 ;
assign MUX_wsiM_reqFifo_q_1_write_1__SEL_2 =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd1 ;
assign MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 =
wsiM_reqFifo_cntr_r != 2'd2 && wsiS_reqFifo_EMPTY_N &&
wci_wslv_cState == 3'd2 ;
assign MUX_wci_wslv_illegalEdge_write_1__VAL_1 =
wci_wslv_reqF_D_OUT[36:34] != 3'd4 &&
wci_wslv_reqF_D_OUT[36:34] != 3'd5 &&
wci_wslv_reqF_D_OUT[36:34] != 3'd6 ;
assign MUX_wci_wslv_respF_cntr_r_write_1__VAL_2 =
wci_wslv_respF_cntr_r + 2'd1 ;
assign MUX_wci_wslv_respF_q_0_write_1__VAL_1 =
(wci_wslv_respF_cntr_r == 2'd1) ?
MUX_wci_wslv_respF_q_0_write_1__VAL_2 :
wci_wslv_respF_q_1 ;
always@(WILL_FIRE_RL_wci_wslv_ctl_op_complete or
MUX_wci_wslv_respF_x_wire_wset_1__VAL_1 or
WILL_FIRE_RL_wci_cfrd or
MUX_wci_wslv_respF_x_wire_wset_1__VAL_2 or WILL_FIRE_RL_wci_cfwr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_wslv_ctl_op_complete:
MUX_wci_wslv_respF_q_0_write_1__VAL_2 =
MUX_wci_wslv_respF_x_wire_wset_1__VAL_1;
WILL_FIRE_RL_wci_cfrd:
MUX_wci_wslv_respF_q_0_write_1__VAL_2 =
MUX_wci_wslv_respF_x_wire_wset_1__VAL_2;
WILL_FIRE_RL_wci_cfwr:
MUX_wci_wslv_respF_q_0_write_1__VAL_2 = 34'h1C0DE4201;
default: MUX_wci_wslv_respF_q_0_write_1__VAL_2 =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign MUX_wci_wslv_respF_q_1_write_1__VAL_1 =
(wci_wslv_respF_cntr_r == 2'd2) ?
MUX_wci_wslv_respF_q_0_write_1__VAL_2 :
34'h0AAAAAAAA ;
assign MUX_wci_wslv_respF_x_wire_wset_1__VAL_1 =
wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ;
assign MUX_wci_wslv_respF_x_wire_wset_1__VAL_2 =
{ 2'd1, _theResult____h10971 } ;
assign MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 = wsiM_reqFifo_cntr_r - 2'd1 ;
assign MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2 = wsiM_reqFifo_cntr_r + 2'd1 ;
assign MUX_wsiM_reqFifo_q_0_write_1__VAL_1 =
(wsiM_reqFifo_cntr_r == 2'd1) ?
MUX_wsiM_reqFifo_q_0_write_1__VAL_2 :
wsiM_reqFifo_q_1 ;
assign MUX_wsiM_reqFifo_q_0_write_1__VAL_2 =
{ wsiS_reqFifo_D_OUT[96:80],
x_data__h10099,
wsiS_reqFifo_D_OUT[15:0] } ;
assign MUX_wsiM_reqFifo_q_1_write_1__VAL_1 =
(wsiM_reqFifo_cntr_r == 2'd2) ?
MUX_wsiM_reqFifo_q_0_write_1__VAL_2 :
97'h00000AAAAAAAAAAAAAAAAAA00 ;
// inlined wires
assign wci_wslv_wciReq_wget =
{ wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData } ;
assign wci_wslv_wciReq_whas = 1'd1 ;
assign wci_wslv_respF_x_wire_wget = MUX_wci_wslv_respF_q_0_write_1__VAL_2 ;
assign wci_wslv_respF_x_wire_whas =
WILL_FIRE_RL_wci_wslv_ctl_op_complete || WILL_FIRE_RL_wci_cfrd ||
WILL_FIRE_RL_wci_cfwr ;
assign wci_wslv_wEdge_wget = wci_wslv_reqF_D_OUT[36:34] ;
assign wci_wslv_wEdge_whas = WILL_FIRE_RL_wci_wslv_ctl_op_start ;
assign wci_wslv_sFlagReg_1_wget = 1'b0 ;
assign wci_wslv_sFlagReg_1_whas = 1'b0 ;
assign wci_wslv_ctlAckReg_1_wget = 1'd1 ;
assign wci_wslv_ctlAckReg_1_whas =
WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO ||
MUX_biasValue_write_1__SEL_2 ;
assign wci_wci_Es_mCmd_w_wget = wciS0_MCmd ;
assign wci_wci_Es_mCmd_w_whas = 1'd1 ;
assign wci_wci_Es_mAddrSpace_w_wget = wciS0_MAddrSpace ;
assign wci_wci_Es_mAddrSpace_w_whas = 1'd1 ;
assign wci_wci_Es_mByteEn_w_wget = wciS0_MByteEn ;
assign wci_wci_Es_mByteEn_w_whas = 1'd1 ;
assign wci_wci_Es_mAddr_w_wget = wciS0_MAddr ;
assign wci_wci_Es_mAddr_w_whas = 1'd1 ;
assign wci_wci_Es_mData_w_wget = wciS0_MData ;
assign wci_wci_Es_mData_w_whas = 1'd1 ;
assign wsiS_wsiReq_wget =
{ wsiS0_MCmd,
wsiS0_MReqLast,
wsiS0_MBurstPrecise,
wsiS0_MBurstLength,
wsiS0_MData,
wsiS0_MByteEn,
wsiS0_MReqInfo } ;
assign wsiS_wsiReq_whas = 1'd1 ;
assign wsiS_operateD_1_wget = 1'd1 ;
assign wsiS_operateD_1_whas = wci_wslv_cState == 3'd2 ;
assign wsiS_peerIsReady_1_wget = 1'd1 ;
assign wsiS_peerIsReady_1_whas = wsiS0_MReset_n ;
assign wsiS_sThreadBusy_dw_wget = wsiS_reqFifo_countReg > 2'd1 ;
assign wsiS_sThreadBusy_dw_whas =
wsiS_reqFifo_levelsValid && wsiS_operateD && wsiS_peerIsReady ;
assign wsiM_reqFifo_x_wire_wget = MUX_wsiM_reqFifo_q_0_write_1__VAL_2 ;
assign wsiM_reqFifo_x_wire_whas =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
assign wsiM_operateD_1_wget = 1'd1 ;
assign wsiM_operateD_1_whas = wci_wslv_cState == 3'd2 ;
assign wsiM_peerIsReady_1_wget = 1'd1 ;
assign wsiM_peerIsReady_1_whas = wsiM0_SReset_n ;
assign wsi_Es_mCmd_w_wget = wsiS0_MCmd ;
assign wsi_Es_mCmd_w_whas = 1'd1 ;
assign wsi_Es_mBurstLength_w_wget = wsiS0_MBurstLength ;
assign wsi_Es_mBurstLength_w_whas = 1'd1 ;
assign wsi_Es_mData_w_wget = wsiS0_MData ;
assign wsi_Es_mData_w_whas = 1'd1 ;
assign wsi_Es_mByteEn_w_wget = wsiS0_MByteEn ;
assign wsi_Es_mByteEn_w_whas = 1'd1 ;
assign wsi_Es_mReqInfo_w_wget = wsiS0_MReqInfo ;
assign wsi_Es_mReqInfo_w_whas = 1'd1 ;
assign wci_wslv_reqF_r_enq_whas = wci_wslv_wciReq_wget[71:69] != 3'd0 ;
assign wci_wslv_reqF_r_deq_whas =
WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_wslv_ctl_op_start ;
assign wci_wslv_reqF_r_clr_whas = 1'b0 ;
assign wci_wslv_respF_enqueueing_whas =
WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
assign wci_wslv_respF_dequeueing_whas = wci_wslv_respF_cntr_r != 2'd0 ;
assign wci_wslv_sThreadBusy_pw_whas = 1'b0 ;
assign wci_wslv_wci_cfwr_pw_whas =
wci_wslv_reqF_EMPTY_N && wci_wslv_reqF_D_OUT[68] &&
wci_wslv_reqF_D_OUT[71:69] == 3'd1 ;
assign wci_wslv_wci_cfrd_pw_whas =
wci_wslv_reqF_EMPTY_N && wci_wslv_reqF_D_OUT[68] &&
wci_wslv_reqF_D_OUT[71:69] == 3'd2 ;
assign wci_wslv_wci_ctrl_pw_whas =
wci_wslv_reqF_EMPTY_N && !wci_wslv_reqF_D_OUT[68] &&
wci_wslv_reqF_D_OUT[71:69] == 3'd2 ;
assign wsiS_reqFifo_r_enq_whas = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo_r_deq_whas =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
assign wsiS_reqFifo_r_clr_whas = 1'b0 ;
assign wsiS_reqFifo_doResetEnq_whas = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo_doResetDeq_whas =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
assign wsiS_reqFifo_doResetClr_whas = 1'b0 ;
assign wsiM_reqFifo_enqueueing_whas =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
assign wsiM_reqFifo_dequeueing_whas = WILL_FIRE_RL_wsiM_reqFifo_deq ;
assign wsiM_sThreadBusy_pw_whas = wsiM0_SThreadBusy ;
assign wsi_Es_mReqLast_w_whas = wsiS0_MReqLast ;
assign wsi_Es_mBurstPrecise_w_whas = wsiS0_MBurstPrecise ;
assign wsi_Es_mDataInfo_w_whas = 1'd1 ;
assign wsiS_extStatusW_wget =
{ wsiS_pMesgCount, wsiS_iMesgCount, wsiS_tBusyCount } ;
assign wsiM_extStatusW_wget =
{ wsiM_pMesgCount, wsiM_iMesgCount, wsiM_tBusyCount } ;
// register biasValue
assign biasValue_D_IN =
MUX_biasValue_write_1__SEL_1 ?
wci_wslv_reqF_D_OUT[31:0] :
32'd0 ;
assign biasValue_EN =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h0 ||
MUX_biasValue_write_1__SEL_2 ;
// register controlReg
assign controlReg_D_IN =
MUX_controlReg_write_1__SEL_1 ?
wci_wslv_reqF_D_OUT[31:0] :
32'd0 ;
assign controlReg_EN =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h04 ||
MUX_biasValue_write_1__SEL_2 ;
// register wci_wslv_cEdge
assign wci_wslv_cEdge_D_IN = wci_wslv_reqF_D_OUT[36:34] ;
assign wci_wslv_cEdge_EN = WILL_FIRE_RL_wci_wslv_ctl_op_start ;
// register wci_wslv_cState
assign wci_wslv_cState_D_IN = wci_wslv_nState ;
assign wci_wslv_cState_EN =
WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge ;
// register wci_wslv_ctlAckReg
assign wci_wslv_ctlAckReg_D_IN = wci_wslv_ctlAckReg_1_whas ;
assign wci_wslv_ctlAckReg_EN = 1'd1 ;
// register wci_wslv_ctlOpActive
assign wci_wslv_ctlOpActive_D_IN = !WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
assign wci_wslv_ctlOpActive_EN =
WILL_FIRE_RL_wci_wslv_ctl_op_complete ||
WILL_FIRE_RL_wci_wslv_ctl_op_start ;
// register wci_wslv_illegalEdge
assign wci_wslv_illegalEdge_D_IN =
MUX_wci_wslv_illegalEdge_write_1__SEL_1 &&
MUX_wci_wslv_illegalEdge_write_1__VAL_1 ;
assign wci_wslv_illegalEdge_EN =
MUX_wci_wslv_illegalEdge_write_1__SEL_1 ||
WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ;
// register wci_wslv_isReset_isInReset
assign wci_wslv_isReset_isInReset_D_IN = 1'd0 ;
assign wci_wslv_isReset_isInReset_EN = wci_wslv_isReset_isInReset ;
// register wci_wslv_nState
always@(wci_wslv_reqF_D_OUT)
begin
case (wci_wslv_reqF_D_OUT[36:34])
3'd0: wci_wslv_nState_D_IN = 3'd1;
3'd1: wci_wslv_nState_D_IN = 3'd2;
3'd2: wci_wslv_nState_D_IN = 3'd3;
default: wci_wslv_nState_D_IN = 3'd0;
endcase
end
assign wci_wslv_nState_EN =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF_D_OUT[36:34] == 3'd0 && wci_wslv_cState == 3'd0 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd1 &&
(wci_wslv_cState == 3'd1 || wci_wslv_cState == 3'd3) ||
wci_wslv_reqF_D_OUT[36:34] == 3'd2 && wci_wslv_cState == 3'd2 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd3 &&
(wci_wslv_cState == 3'd3 || wci_wslv_cState == 3'd2 ||
wci_wslv_cState == 3'd1)) ;
// register wci_wslv_reqF_countReg
assign wci_wslv_reqF_countReg_D_IN =
(wci_wslv_wciReq_wget[71:69] != 3'd0) ?
wci_wslv_reqF_countReg + 2'd1 :
wci_wslv_reqF_countReg - 2'd1 ;
assign wci_wslv_reqF_countReg_EN =
(wci_wslv_wciReq_wget[71:69] != 3'd0) !=
wci_wslv_reqF_r_deq_whas ;
// register wci_wslv_respF_cntr_r
assign wci_wslv_respF_cntr_r_D_IN =
WILL_FIRE_RL_wci_wslv_respF_decCtr ?
wci_wslv_respF_cntr_r_8_MINUS_1___d27 :
MUX_wci_wslv_respF_cntr_r_write_1__VAL_2 ;
assign wci_wslv_respF_cntr_r_EN =
WILL_FIRE_RL_wci_wslv_respF_decCtr ||
WILL_FIRE_RL_wci_wslv_respF_incCtr ;
// register wci_wslv_respF_q_0
always@(MUX_wci_wslv_respF_q_0_write_1__SEL_1 or
MUX_wci_wslv_respF_q_0_write_1__VAL_1 or
MUX_wci_wslv_respF_q_0_write_1__SEL_2 or
MUX_wci_wslv_respF_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wci_wslv_respF_decCtr or wci_wslv_respF_q_1)
begin
case (1'b1) // synopsys parallel_case
MUX_wci_wslv_respF_q_0_write_1__SEL_1:
wci_wslv_respF_q_0_D_IN = MUX_wci_wslv_respF_q_0_write_1__VAL_1;
MUX_wci_wslv_respF_q_0_write_1__SEL_2:
wci_wslv_respF_q_0_D_IN = MUX_wci_wslv_respF_q_0_write_1__VAL_2;
WILL_FIRE_RL_wci_wslv_respF_decCtr:
wci_wslv_respF_q_0_D_IN = wci_wslv_respF_q_1;
default: wci_wslv_respF_q_0_D_IN =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_wslv_respF_q_0_EN =
WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 ||
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_cntr_r == 2'd0 ||
WILL_FIRE_RL_wci_wslv_respF_decCtr ;
// register wci_wslv_respF_q_1
always@(MUX_wci_wslv_respF_q_1_write_1__SEL_1 or
MUX_wci_wslv_respF_q_1_write_1__VAL_1 or
MUX_wci_wslv_respF_q_1_write_1__SEL_2 or
MUX_wci_wslv_respF_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wci_wslv_respF_decCtr)
begin
case (1'b1) // synopsys parallel_case
MUX_wci_wslv_respF_q_1_write_1__SEL_1:
wci_wslv_respF_q_1_D_IN = MUX_wci_wslv_respF_q_1_write_1__VAL_1;
MUX_wci_wslv_respF_q_1_write_1__SEL_2:
wci_wslv_respF_q_1_D_IN = MUX_wci_wslv_respF_q_0_write_1__VAL_2;
WILL_FIRE_RL_wci_wslv_respF_decCtr:
wci_wslv_respF_q_1_D_IN = 34'h0AAAAAAAA;
default: wci_wslv_respF_q_1_D_IN =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_wslv_respF_q_1_EN =
WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 ||
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_cntr_r == 2'd1 ||
WILL_FIRE_RL_wci_wslv_respF_decCtr ;
// register wci_wslv_sFlagReg
assign wci_wslv_sFlagReg_D_IN = 1'b0 ;
assign wci_wslv_sFlagReg_EN = 1'd1 ;
// register wci_wslv_sThreadBusy_d
assign wci_wslv_sThreadBusy_d_D_IN = 1'b0 ;
assign wci_wslv_sThreadBusy_d_EN = 1'd1 ;
// register wsiM_burstKind
assign wsiM_burstKind_D_IN =
(wsiM_burstKind == 2'd0) ?
(wsiM_reqFifo_q_0[92] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsiM_burstKind_EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[96:94] == 3'd1 &&
(wsiM_burstKind == 2'd0 ||
(wsiM_burstKind == 2'd1 || wsiM_burstKind == 2'd2) &&
wsiM_reqFifo_q_0[93]) ;
// register wsiM_errorSticky
assign wsiM_errorSticky_D_IN = 1'b0 ;
assign wsiM_errorSticky_EN = 1'b0 ;
// register wsiM_iMesgCount
assign wsiM_iMesgCount_D_IN = wsiM_iMesgCount + 32'd1 ;
assign wsiM_iMesgCount_EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[96:94] == 3'd1 &&
wsiM_burstKind == 2'd2 &&
wsiM_reqFifo_q_0[93] ;
// register wsiM_isReset_isInReset
assign wsiM_isReset_isInReset_D_IN = 1'd0 ;
assign wsiM_isReset_isInReset_EN = wsiM_isReset_isInReset ;
// register wsiM_operateD
assign wsiM_operateD_D_IN = wci_wslv_cState == 3'd2 ;
assign wsiM_operateD_EN = 1'd1 ;
// register wsiM_pMesgCount
assign wsiM_pMesgCount_D_IN = wsiM_pMesgCount + 32'd1 ;
assign wsiM_pMesgCount_EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[96:94] == 3'd1 &&
wsiM_burstKind == 2'd1 &&
wsiM_reqFifo_q_0[93] ;
// register wsiM_peerIsReady
assign wsiM_peerIsReady_D_IN = wsiM0_SReset_n ;
assign wsiM_peerIsReady_EN = 1'd1 ;
// register wsiM_reqFifo_cntr_r
assign wsiM_reqFifo_cntr_r_D_IN =
WILL_FIRE_RL_wsiM_reqFifo_decCtr ?
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 :
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2 ;
assign wsiM_reqFifo_cntr_r_EN =
WILL_FIRE_RL_wsiM_reqFifo_decCtr ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr ;
// register wsiM_reqFifo_q_0
always@(MUX_wsiM_reqFifo_q_0_write_1__SEL_1 or
MUX_wsiM_reqFifo_q_0_write_1__VAL_1 or
MUX_wsiM_reqFifo_q_0_write_1__SEL_2 or
MUX_wsiM_reqFifo_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1)
begin
case (1'b1) // synopsys parallel_case
MUX_wsiM_reqFifo_q_0_write_1__SEL_1:
wsiM_reqFifo_q_0_D_IN = MUX_wsiM_reqFifo_q_0_write_1__VAL_1;
MUX_wsiM_reqFifo_q_0_write_1__SEL_2:
wsiM_reqFifo_q_0_D_IN = MUX_wsiM_reqFifo_q_0_write_1__VAL_2;
WILL_FIRE_RL_wsiM_reqFifo_decCtr:
wsiM_reqFifo_q_0_D_IN = wsiM_reqFifo_q_1;
default: wsiM_reqFifo_q_0_D_IN =
97'h0AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsiM_reqFifo_q_0_EN =
WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo7 ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr &&
wsiM_reqFifo_cntr_r == 2'd0 ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_reqFifo_q_1
always@(MUX_wsiM_reqFifo_q_1_write_1__SEL_1 or
MUX_wsiM_reqFifo_q_1_write_1__VAL_1 or
MUX_wsiM_reqFifo_q_1_write_1__SEL_2 or
MUX_wsiM_reqFifo_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wsiM_reqFifo_decCtr)
begin
case (1'b1) // synopsys parallel_case
MUX_wsiM_reqFifo_q_1_write_1__SEL_1:
wsiM_reqFifo_q_1_D_IN = MUX_wsiM_reqFifo_q_1_write_1__VAL_1;
MUX_wsiM_reqFifo_q_1_write_1__SEL_2:
wsiM_reqFifo_q_1_D_IN = MUX_wsiM_reqFifo_q_0_write_1__VAL_2;
WILL_FIRE_RL_wsiM_reqFifo_decCtr:
wsiM_reqFifo_q_1_D_IN = 97'h00000AAAAAAAAAAAAAAAAAA00;
default: wsiM_reqFifo_q_1_D_IN =
97'h0AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsiM_reqFifo_q_1_EN =
WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo5 ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr &&
wsiM_reqFifo_cntr_r == 2'd1 ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_sThreadBusy_d
assign wsiM_sThreadBusy_d_D_IN = wsiM0_SThreadBusy ;
assign wsiM_sThreadBusy_d_EN = 1'd1 ;
// register wsiM_statusR
assign wsiM_statusR_D_IN =
{ wsiM_isReset_isInReset,
!wsiM_peerIsReady,
!wsiM_operateD,
wsiM_errorSticky,
wsiM_burstKind != 2'd0,
wsiM_sThreadBusy_d,
1'd0,
wsiM_trafficSticky } ;
assign wsiM_statusR_EN = 1'd1 ;
// register wsiM_tBusyCount
assign wsiM_tBusyCount_D_IN = wsiM_tBusyCount + 32'd1 ;
assign wsiM_tBusyCount_EN =
wsiM_operateD && wsiM_peerIsReady && wsiM_sThreadBusy_d ;
// register wsiM_trafficSticky
assign wsiM_trafficSticky_D_IN = 1'd1 ;
assign wsiM_trafficSticky_EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[96:94] == 3'd1 ;
// register wsiS_burstKind
assign wsiS_burstKind_D_IN =
(wsiS_burstKind == 2'd0) ?
(wsiS_wsiReq_wget[92] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsiS_burstKind_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq &&
(wsiS_burstKind == 2'd0 ||
(wsiS_burstKind == 2'd1 || wsiS_burstKind == 2'd2) &&
wsiS_wsiReq_wget[93]) ;
// register wsiS_errorSticky
assign wsiS_errorSticky_D_IN = 1'b0 ;
assign wsiS_errorSticky_EN = 1'b0 ;
// register wsiS_iMesgCount
assign wsiS_iMesgCount_D_IN = wsiS_iMesgCount + 32'd1 ;
assign wsiS_iMesgCount_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd2 &&
wsiS_wsiReq_wget[93] ;
// register wsiS_isReset_isInReset
assign wsiS_isReset_isInReset_D_IN = 1'd0 ;
assign wsiS_isReset_isInReset_EN = wsiS_isReset_isInReset ;
// register wsiS_mesgWordLength
assign wsiS_mesgWordLength_D_IN = wsiS_wordCount ;
assign wsiS_mesgWordLength_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_wsiReq_wget[93] ;
// register wsiS_operateD
assign wsiS_operateD_D_IN = wci_wslv_cState == 3'd2 ;
assign wsiS_operateD_EN = 1'd1 ;
// register wsiS_pMesgCount
assign wsiS_pMesgCount_D_IN = wsiS_pMesgCount + 32'd1 ;
assign wsiS_pMesgCount_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd1 &&
wsiS_wsiReq_wget[93] ;
// register wsiS_peerIsReady
assign wsiS_peerIsReady_D_IN = wsiS0_MReset_n ;
assign wsiS_peerIsReady_EN = 1'd1 ;
// register wsiS_reqFifo_countReg
assign wsiS_reqFifo_countReg_D_IN =
WILL_FIRE_RL_wsiS_reqFifo_enq ?
wsiS_reqFifo_countReg + 2'd1 :
wsiS_reqFifo_countReg - 2'd1 ;
assign wsiS_reqFifo_countReg_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq !=
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
// register wsiS_reqFifo_levelsValid
assign wsiS_reqFifo_levelsValid_D_IN = WILL_FIRE_RL_wsiS_reqFifo_reset ;
assign wsiS_reqFifo_levelsValid_EN =
wsiM_reqFifo_cntr_r != 2'd2 && wsiS_reqFifo_EMPTY_N &&
wci_wslv_cState == 3'd2 ||
WILL_FIRE_RL_wsiS_reqFifo_enq ||
WILL_FIRE_RL_wsiS_reqFifo_reset ;
// register wsiS_statusR
assign wsiS_statusR_D_IN =
{ wsiS_isReset_isInReset,
!wsiS_peerIsReady,
!wsiS_operateD,
wsiS_errorSticky,
wsiS_burstKind != 2'd0,
!wsiS_sThreadBusy_dw_whas || wsiS_sThreadBusy_dw_wget,
1'd0,
wsiS_trafficSticky } ;
assign wsiS_statusR_EN = 1'd1 ;
// register wsiS_tBusyCount
assign wsiS_tBusyCount_D_IN = wsiS_tBusyCount + 32'd1 ;
assign wsiS_tBusyCount_EN =
wsiS_operateD && wsiS_peerIsReady &&
(!wsiS_sThreadBusy_dw_whas || wsiS_sThreadBusy_dw_wget) ;
// register wsiS_trafficSticky
assign wsiS_trafficSticky_D_IN = 1'd1 ;
assign wsiS_trafficSticky_EN = WILL_FIRE_RL_wsiS_reqFifo_enq ;
// register wsiS_wordCount
assign wsiS_wordCount_D_IN =
wsiS_wsiReq_wget[93] ? 12'd1 : wsiS_wordCount + 12'd1 ;
assign wsiS_wordCount_EN = WILL_FIRE_RL_wsiS_reqFifo_enq ;
// submodule wci_wslv_reqF
assign wci_wslv_reqF_D_IN = wci_wslv_wciReq_wget ;
assign wci_wslv_reqF_ENQ = wci_wslv_wciReq_wget[71:69] != 3'd0 ;
assign wci_wslv_reqF_DEQ = wci_wslv_reqF_r_deq_whas ;
assign wci_wslv_reqF_CLR = 1'b0 ;
// submodule wsiS_reqFifo
assign wsiS_reqFifo_D_IN = wsiS_wsiReq_wget ;
assign wsiS_reqFifo_ENQ = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo_DEQ = MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
assign wsiS_reqFifo_CLR = 1'b0 ;
// remaining internal signals
assign _dfoo1 =
wci_wslv_respF_cntr_r != 2'd2 ||
wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd1 ;
assign _dfoo3 =
wci_wslv_respF_cntr_r != 2'd1 ||
wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd0 ;
assign _dfoo5 =
wsiM_reqFifo_cntr_r != 2'd2 ||
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 == 2'd1 ;
assign _dfoo7 =
wsiM_reqFifo_cntr_r != 2'd1 ||
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 == 2'd0 ;
assign rdat__h11061 = hasDebugLogic ? { 16'd0, x__h11065 } : 32'd0 ;
assign rdat__h11161 = hasDebugLogic ? wsiS_extStatusW_wget[95:64] : 32'd0 ;
assign rdat__h11175 = hasDebugLogic ? wsiS_extStatusW_wget[63:32] : 32'd0 ;
assign rdat__h11183 = hasDebugLogic ? wsiS_extStatusW_wget[31:0] : 32'd0 ;
assign rdat__h11189 = hasDebugLogic ? wsiM_extStatusW_wget[95:64] : 32'd0 ;
assign rdat__h11203 = hasDebugLogic ? wsiM_extStatusW_wget[63:32] : 32'd0 ;
assign rdat__h11211 = hasDebugLogic ? wsiM_extStatusW_wget[31:0] : 32'd0 ;
assign wci_wslv_respF_cntr_r_8_MINUS_1___d27 =
wci_wslv_respF_cntr_r - 2'd1 ;
assign x__h11065 = { wsiS_statusR, wsiM_statusR } ;
assign x_data__h10099 =
{ wsiS_reqFifo_D_OUT[79:48] + biasValue,
wsiS_reqFifo_D_OUT[47:16] + biasValue } ;
always@(wci_wslv_reqF_D_OUT or
biasValue or
controlReg or
rdat__h11061 or
rdat__h11161 or
rdat__h11175 or
rdat__h11183 or rdat__h11189 or rdat__h11203 or rdat__h11211)
begin
case (wci_wslv_reqF_D_OUT[39:32])
8'h0: _theResult____h10971 = biasValue;
8'h04: _theResult____h10971 = controlReg;
8'h20: _theResult____h10971 = rdat__h11061;
8'h24: _theResult____h10971 = rdat__h11161;
8'h28: _theResult____h10971 = rdat__h11175;
8'h2C: _theResult____h10971 = rdat__h11183;
8'h30: _theResult____h10971 = rdat__h11189;
8'h34: _theResult____h10971 = rdat__h11203;
8'h38: _theResult____h10971 = rdat__h11211;
default: _theResult____h10971 = 32'd0;
endcase
end
// handling of inlined registers
always@(posedge wciS0_Clk)
begin
if (wciS0_MReset_n == `BSV_RESET_VALUE)
begin
wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2;
wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_wslv_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY
97'h00000AAAAAAAAAAAAAAAAAA00;
wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY
97'h00000AAAAAAAAAAAAAAAAAA00;
wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY 12'd1;
end
else
begin
if (wci_wslv_cEdge_EN)
wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY wci_wslv_cEdge_D_IN;
if (wci_wslv_cState_EN)
wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY wci_wslv_cState_D_IN;
if (wci_wslv_ctlAckReg_EN)
wci_wslv_ctlAckReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_ctlAckReg_D_IN;
if (wci_wslv_ctlOpActive_EN)
wci_wslv_ctlOpActive <= `BSV_ASSIGNMENT_DELAY
wci_wslv_ctlOpActive_D_IN;
if (wci_wslv_illegalEdge_EN)
wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY
wci_wslv_illegalEdge_D_IN;
if (wci_wslv_nState_EN)
wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY wci_wslv_nState_D_IN;
if (wci_wslv_reqF_countReg_EN)
wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY
wci_wslv_reqF_countReg_D_IN;
if (wci_wslv_respF_cntr_r_EN)
wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY
wci_wslv_respF_cntr_r_D_IN;
if (wci_wslv_respF_q_0_EN)
wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_0_D_IN;
if (wci_wslv_respF_q_1_EN)
wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_1_D_IN;
if (wci_wslv_sFlagReg_EN)
wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_sFlagReg_D_IN;
if (wci_wslv_sThreadBusy_d_EN)
wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY
wci_wslv_sThreadBusy_d_D_IN;
if (wsiM_burstKind_EN)
wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY wsiM_burstKind_D_IN;
if (wsiM_errorSticky_EN)
wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiM_errorSticky_D_IN;
if (wsiM_iMesgCount_EN)
wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_iMesgCount_D_IN;
if (wsiM_operateD_EN)
wsiM_operateD <= `BSV_ASSIGNMENT_DELAY wsiM_operateD_D_IN;
if (wsiM_pMesgCount_EN)
wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_pMesgCount_D_IN;
if (wsiM_peerIsReady_EN)
wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiM_peerIsReady_D_IN;
if (wsiM_reqFifo_cntr_r_EN)
wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY
wsiM_reqFifo_cntr_r_D_IN;
if (wsiM_reqFifo_q_0_EN)
wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_0_D_IN;
if (wsiM_reqFifo_q_1_EN)
wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_1_D_IN;
if (wsiM_sThreadBusy_d_EN)
wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wsiM_sThreadBusy_d_D_IN;
if (wsiM_tBusyCount_EN)
wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiM_tBusyCount_D_IN;
if (wsiM_trafficSticky_EN)
wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiM_trafficSticky_D_IN;
if (wsiS_burstKind_EN)
wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY wsiS_burstKind_D_IN;
if (wsiS_errorSticky_EN)
wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiS_errorSticky_D_IN;
if (wsiS_iMesgCount_EN)
wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_iMesgCount_D_IN;
if (wsiS_operateD_EN)
wsiS_operateD <= `BSV_ASSIGNMENT_DELAY wsiS_operateD_D_IN;
if (wsiS_pMesgCount_EN)
wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_pMesgCount_D_IN;
if (wsiS_peerIsReady_EN)
wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiS_peerIsReady_D_IN;
if (wsiS_reqFifo_countReg_EN)
wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY
wsiS_reqFifo_countReg_D_IN;
if (wsiS_reqFifo_levelsValid_EN)
wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY
wsiS_reqFifo_levelsValid_D_IN;
if (wsiS_tBusyCount_EN)
wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiS_tBusyCount_D_IN;
if (wsiS_trafficSticky_EN)
wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiS_trafficSticky_D_IN;
if (wsiS_wordCount_EN)
wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY wsiS_wordCount_D_IN;
end
if (biasValue_EN) biasValue <= `BSV_ASSIGNMENT_DELAY biasValue_D_IN;
if (controlReg_EN) controlReg <= `BSV_ASSIGNMENT_DELAY controlReg_D_IN;
if (wsiM_statusR_EN)
wsiM_statusR <= `BSV_ASSIGNMENT_DELAY wsiM_statusR_D_IN;
if (wsiS_mesgWordLength_EN)
wsiS_mesgWordLength <= `BSV_ASSIGNMENT_DELAY wsiS_mesgWordLength_D_IN;
if (wsiS_statusR_EN)
wsiS_statusR <= `BSV_ASSIGNMENT_DELAY wsiS_statusR_D_IN;
end
always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n)
if (wciS0_MReset_n == `BSV_RESET_VALUE)
begin
wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (wci_wslv_isReset_isInReset_EN)
wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wci_wslv_isReset_isInReset_D_IN;
if (wsiM_isReset_isInReset_EN)
wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wsiM_isReset_isInReset_D_IN;
if (wsiS_isReset_isInReset_EN)
wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wsiS_isReset_isInReset_D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
biasValue = 32'hAAAAAAAA;
controlReg = 32'hAAAAAAAA;
wci_wslv_cEdge = 3'h2;
wci_wslv_cState = 3'h2;
wci_wslv_ctlAckReg = 1'h0;
wci_wslv_ctlOpActive = 1'h0;
wci_wslv_illegalEdge = 1'h0;
wci_wslv_isReset_isInReset = 1'h0;
wci_wslv_nState = 3'h2;
wci_wslv_reqF_countReg = 2'h2;
wci_wslv_respF_cntr_r = 2'h2;
wci_wslv_respF_q_0 = 34'h2AAAAAAAA;
wci_wslv_respF_q_1 = 34'h2AAAAAAAA;
wci_wslv_sFlagReg = 1'h0;
wci_wslv_sThreadBusy_d = 1'h0;
wsiM_burstKind = 2'h2;
wsiM_errorSticky = 1'h0;
wsiM_iMesgCount = 32'hAAAAAAAA;
wsiM_isReset_isInReset = 1'h0;
wsiM_operateD = 1'h0;
wsiM_pMesgCount = 32'hAAAAAAAA;
wsiM_peerIsReady = 1'h0;
wsiM_reqFifo_cntr_r = 2'h2;
wsiM_reqFifo_q_0 = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA;
wsiM_reqFifo_q_1 = 97'h0AAAAAAAAAAAAAAAAAAAAAAAA;
wsiM_sThreadBusy_d = 1'h0;
wsiM_statusR = 8'hAA;
wsiM_tBusyCount = 32'hAAAAAAAA;
wsiM_trafficSticky = 1'h0;
wsiS_burstKind = 2'h2;
wsiS_errorSticky = 1'h0;
wsiS_iMesgCount = 32'hAAAAAAAA;
wsiS_isReset_isInReset = 1'h0;
wsiS_mesgWordLength = 12'hAAA;
wsiS_operateD = 1'h0;
wsiS_pMesgCount = 32'hAAAAAAAA;
wsiS_peerIsReady = 1'h0;
wsiS_reqFifo_countReg = 2'h2;
wsiS_reqFifo_levelsValid = 1'h0;
wsiS_statusR = 8'hAA;
wsiS_tBusyCount = 32'hAAAAAAAA;
wsiS_trafficSticky = 1'h0;
wsiS_wordCount = 12'hAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge wciS0_Clk)
begin
#0;
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_start)
begin
v__h3574 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_start)
$display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x",
v__h3574,
wci_wslv_reqF_D_OUT[36:34],
wci_wslv_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (MUX_biasValue_write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (MUX_biasValue_write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 62: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr)
begin
v__h10832 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr)
$display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x",
v__h10832,
wci_wslv_reqF_D_OUT[63:32],
wci_wslv_reqF_D_OUT[67:64],
wci_wslv_reqF_D_OUT[31:0]);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge)
begin
v__h3893 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x",
v__h3893,
wci_wslv_cEdge,
wci_wslv_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge)
begin
v__h3749 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x",
v__h3749,
wci_wslv_cEdge,
wci_wslv_cState,
wci_wslv_nState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd)
begin
v__h10987 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd)
$display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x",
v__h10987,
wci_wslv_reqF_D_OUT[63:32],
wci_wslv_reqF_D_OUT[67:64],
_theResult____h10971);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && MUX_biasValue_write_1__SEL_2)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && MUX_biasValue_write_1__SEL_2)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
end
// synopsys translate_on
endmodule // mkBiasWorker8B
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:56:46 05/18/2016
// Design Name: R_CPU
// Module Name: Y:/TEOCOA/EXPR8/TESTRCPU.v
// Project Name: EXPR8
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: R_CPU
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TESTRCPU;
// Inputs
reg clk;
reg rst;
// Outputs
wire [31:0] ALU_F;
wire FR_ZF;
wire FR_OF;
wire [4:0] rs;
wire [4:0] rt;
wire [4:0] rd;
wire [5:0] OP;
wire [5:0] func;
wire [31:0] ALU_A;
wire [31:0] ALU_B;
// Instantiate the Unit Under Test (UUT)
R_CPU uut (
.clk(clk),
.rst(rst),
.ALU_F(ALU_F),
.FR_ZF(FR_ZF),
.FR_OF(FR_OF),
.rs(rs),
.rt(rt),
.rd(rd),
.OP(OP),
.func(func),
.ALU_A(ALU_A),
.ALU_B(ALU_B)
);
always #25 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
#100;
// Wait 100 ns for global reset to finish
rst = 1;
clk = 0;
#100;
rst = 0;
end
endmodule
|
// track loads on each port and in each router. Also, when a port is disabled, use to track the potential deflection.
// After RC
`include "globalVariable.v"
module loadTrack (reset, clk, valid, productiveVector, pgEnable, portStatus, routerLoad, portLoad);
input clk, reset,pgEnable;
input [3:0] valid;
input [3:0] productiveVector;
input [4*`PORT_STAT_SIZE-1:0] portStatus; // [S, N, W, E]
output [`PG_ROUTER_LOAD_SIZE-1:0] routerLoad;
output [4*`PG_PORT_LOAD_SIZE-1:0] portLoad; // [S, N, W, E]
wire [`PORT_STAT_SIZE-1:0] wPortStatus [3:0];
genvar i;
generate
for (i=0; i<4; i= i+1) begin : split_bus
assign wPortStatus[i] = portStatus[i*`PORT_STAT_SIZE+:`PORT_STAT_SIZE];
end
endgenerate
reg [`PG_PORT_LOAD_SIZE-1:0] portUtilization [3:0];
reg [2:0] j;
always @ (posedge clk or negedge reset) begin
if (~reset) begin
for (j=0;j<4;j=j+1)
portUtilization[j] <= 0;
end
else begin
if (~pgEnable) begin
for (j=0;j<4;j=j+1)
if ((valid[j] && (wPortStatus[j] == `ACTIVE))| (productiveVector[j] && (wPortStatus[j] == `INACTIVE)))
portUtilization[j] <= portUtilization[j] + 1;
end
else
for (j=0;j<4;j=j+1)
portUtilization[j] <= 0;
end
end
assign routerLoad = portUtilization[3]+portUtilization[2]+portUtilization[1]+portUtilization[0];
assign portLoad = {portUtilization[3],portUtilization[2],portUtilization[1],portUtilization[0]};
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__LSBUFISO1P_TB_V
`define SKY130_FD_SC_LP__LSBUFISO1P_TB_V
/**
* lsbufiso1p: ????.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__lsbufiso1p.v"
module top();
// Inputs are registered
reg A;
reg SLEEP;
reg DESTPWR;
reg VPWR;
reg VGND;
reg DESTVPB;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
DESTPWR = 1'bX;
DESTVPB = 1'bX;
SLEEP = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 DESTPWR = 1'b0;
#60 DESTVPB = 1'b0;
#80 SLEEP = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 DESTPWR = 1'b1;
#220 DESTVPB = 1'b1;
#240 SLEEP = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 DESTPWR = 1'b0;
#380 DESTVPB = 1'b0;
#400 SLEEP = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SLEEP = 1'b1;
#600 DESTVPB = 1'b1;
#620 DESTPWR = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SLEEP = 1'bx;
#760 DESTVPB = 1'bx;
#780 DESTPWR = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_lp__lsbufiso1p dut (.A(A), .SLEEP(SLEEP), .DESTPWR(DESTPWR), .VPWR(VPWR), .VGND(VGND), .DESTVPB(DESTVPB), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__LSBUFISO1P_TB_V
|
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7_bfm:2.0
// IP Revision: 1
`timescale 1ns/1ps
module design_1_processing_system7_0_0 (
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
SDIO0_WP,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
IRQ_F2P,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input SDIO0_WP;
output [1 : 0] USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11 : 0] M_AXI_GP0_ARID;
output [11 : 0] M_AXI_GP0_AWID;
output [11 : 0] M_AXI_GP0_WID;
output [1 : 0] M_AXI_GP0_ARBURST;
output [1 : 0] M_AXI_GP0_ARLOCK;
output [2 : 0] M_AXI_GP0_ARSIZE;
output [1 : 0] M_AXI_GP0_AWBURST;
output [1 : 0] M_AXI_GP0_AWLOCK;
output [2 : 0] M_AXI_GP0_AWSIZE;
output [2 : 0] M_AXI_GP0_ARPROT;
output [2 : 0] M_AXI_GP0_AWPROT;
output [31 : 0] M_AXI_GP0_ARADDR;
output [31 : 0] M_AXI_GP0_AWADDR;
output [31 : 0] M_AXI_GP0_WDATA;
output [3 : 0] M_AXI_GP0_ARCACHE;
output [3 : 0] M_AXI_GP0_ARLEN;
output [3 : 0] M_AXI_GP0_ARQOS;
output [3 : 0] M_AXI_GP0_AWCACHE;
output [3 : 0] M_AXI_GP0_AWLEN;
output [3 : 0] M_AXI_GP0_AWQOS;
output [3 : 0] M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11 : 0] M_AXI_GP0_BID;
input [11 : 0] M_AXI_GP0_RID;
input [1 : 0] M_AXI_GP0_BRESP;
input [1 : 0] M_AXI_GP0_RRESP;
input [31 : 0] M_AXI_GP0_RDATA;
input [1 : 0] IRQ_F2P;
output FCLK_CLK0;
output FCLK_RESET0_N;
input [53 : 0] MIO;
input DDR_CAS_n;
input DDR_CKE;
input DDR_Clk_n;
input DDR_Clk;
input DDR_CS_n;
input DDR_DRSTB;
input DDR_ODT;
input DDR_RAS_n;
input DDR_WEB;
input [2 : 0] DDR_BankAddr;
input [14 : 0] DDR_Addr;
input DDR_VRN;
input DDR_VRP;
input [3 : 0] DDR_DM;
input [31 : 0] DDR_DQ;
input [3 : 0] DDR_DQS_n;
input [3 : 0] DDR_DQS;
input PS_SRSTB;
input PS_CLK;
input PS_PORB;
processing_system7_bfm_v2_0_processing_system7_bfm #(
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_ACP(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_GP1(0),
.C_USE_S_AXI_HP0(0),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_HIGH_OCM_EN(0),
.C_FCLK_CLK0_FREQ(100),
.C_FCLK_CLK1_FREQ(175),
.C_FCLK_CLK2_FREQ(12),
.C_FCLK_CLK3_FREQ(100),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP0_THREAD_ID_WIDTH (12),
.C_M_AXI_GP1_THREAD_ID_WIDTH (12)
) inst (
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(),
.S_AXI_HP0_AWREADY(),
.S_AXI_HP0_BVALID(),
.S_AXI_HP0_RLAST(),
.S_AXI_HP0_RVALID(),
.S_AXI_HP0_WREADY(),
.S_AXI_HP0_BRESP(),
.S_AXI_HP0_RRESP(),
.S_AXI_HP0_BID(),
.S_AXI_HP0_RID(),
.S_AXI_HP0_RDATA(),
.S_AXI_HP0_ACLK(1'B0),
.S_AXI_HP0_ARVALID(1'B0),
.S_AXI_HP0_AWVALID(1'B0),
.S_AXI_HP0_BREADY(1'B0),
.S_AXI_HP0_RREADY(1'B0),
.S_AXI_HP0_WLAST(1'B0),
.S_AXI_HP0_WVALID(1'B0),
.S_AXI_HP0_ARBURST(2'B0),
.S_AXI_HP0_ARLOCK(2'B0),
.S_AXI_HP0_ARSIZE(3'B0),
.S_AXI_HP0_AWBURST(2'B0),
.S_AXI_HP0_AWLOCK(2'B0),
.S_AXI_HP0_AWSIZE(3'B0),
.S_AXI_HP0_ARPROT(3'B0),
.S_AXI_HP0_AWPROT(3'B0),
.S_AXI_HP0_ARADDR(32'B0),
.S_AXI_HP0_AWADDR(32'B0),
.S_AXI_HP0_ARCACHE(4'B0),
.S_AXI_HP0_ARLEN(4'B0),
.S_AXI_HP0_ARQOS(4'B0),
.S_AXI_HP0_AWCACHE(4'B0),
.S_AXI_HP0_AWLEN(4'B0),
.S_AXI_HP0_AWQOS(4'B0),
.S_AXI_HP0_ARID(6'B0),
.S_AXI_HP0_AWID(6'B0),
.S_AXI_HP0_WID(6'B0),
.S_AXI_HP0_WDATA(64'B0),
.S_AXI_HP0_WSTRB(8'B0),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.IRQ_F2P(IRQ_F2P),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND3B_LP_V
`define SKY130_FD_SC_LP__AND3B_LP_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog wrapper for and3b with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and3b_lp (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and3b_lp (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND3B_LP_V
|
module top();
reg consumer_iclk;
reg producer_iclk;
wire cr;
wire [3:0] cd;
wire [3:0] pd;
reg clk;
always@(posedge clk)
begin
#10 assign consumer_iclk = ~consumer_iclk;
#5 assign producer_iclk = ~producer_iclk;
end
always
#1 assign clk = ~clk;
initial
begin
/*
consumer_iclk = 0;
producer_iclk = 0;
cr =0;
cd=0;
pd=0;
*/
#5000 $finish;
end
producer p1(
pd
);
fifo f1(
cd,
pd,
cr
);
consumer c1(
cr,
cd
);
endmodule
//------------------------------
//PRODUCER IS PRODUCING DATA
module producer (/*producer_iclk,*/producer_data);
//input producer_iclk;
output producer_data;
reg producer_iclk;
reg [3:0] producer_data;
//assign producer_data = 0;
reg [3:0] i = 4'b0000;
always @(producer_iclk)
begin
producer_data = producer_data + 1;
end
initial
begin
producer_data = 0;
producer_iclk = 0;
//$monitor("time=%t data produced = %b clk=%b",$time,producer_data,producer_iclk);
//#100 $finish;
end
//internal 5 unit clk
always
begin
#5 producer_iclk = ~(producer_iclk);
end
endmodule
//-------------------------------
module fifo(consumer_data,producer_data, consumer_req);
input consumer_req;
input producer_data;
output consumer_data;
reg [3:0] consumer_data;
reg [3:0] producer_data;
reg consumer_req;
int i;
int j;
int last;
int start;
int diff;
int last_s;
int start_s;
reg [3:0] queue [9:0];
initial
begin
assign last_s = last % 10;
assign start_s = start % 10;
assign diff = last - start;
//$monitor("producer data = %b %d",producer_data,producer_data);
//producer_data = 0;
#30for(j=0;j<10;j++)
begin
//$display("queue[%d] =%d at time =%t",j,queue[j],$time);
end
end
//add_data thingy
always @ (producer_data)
if((diff < 10))
begin
begin
queue[last_s] = producer_data;
//$display("add queue[%d] is %d",last_s,queue[last_s]);
#0 last = last +1;
end
end else begin
$finish;
end
//pop data thingy
always @(consumer_req)
begin
if(consumer_req == 1)
begin
if(diff != 0)
begin
// $display("pop queue[%d] = %d",start_s,queue[start_s]);
consumer_data = queue[start_s];
//$display("consumer data = %d",consumer_data);
#0 start = start +1;
end
/*
queue[start] = consumer_data;
#0 start = start + 1;
$display("start = %d at time = %t",start,$time);
$display("consumer data = %d",consumer_data);
*/
end
end
endmodule
//------------------------
module consumer(/*consumer_iclk,*/consumer_req,consumer_data);
//input consumer_iclk;
input consumer_data;
output consumer_req;
reg consumer_iclk;
reg [3:0] consumer_data;
reg consumer_req;
// consumer_req = 0;
always @(consumer_iclk)
begin
consumer_req = 1;
#1 consumer_req = 0;
end
initial
begin
//consumer_data = 0;
consumer_req=0;
consumer_iclk =1;
$monitor("data consumed : %d at time = %t", consumer_data,$time);
//#20 $finish;
end
//internal clk
always
begin
#10 consumer_iclk = ~consumer_iclk;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O22A_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__O22A_PP_BLACKBOX_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o22a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O22A_PP_BLACKBOX_V
|
(** * Basics: Functional Programming in Coq *)
(*
[Admitted] is Coq's "escape hatch" that says accept this definition
without proof. We use it to mark the 'holes' in the development
that should be completed as part of your homework exercises. In
practice, [Admitted] is useful when you're incrementally developing
large proofs. *)
Definition admit {T: Type} : T. Admitted.
(* ###################################################################### *)
(** * Introduction *)
(** The functional programming style brings programming closer to
simple, everyday mathematics: If a procedure or method has no side
effects, then pretty much all you need to understand about it is
how it maps inputs to outputs -- that is, you can think of it as
just a concrete method for computing a mathematical function.
This is one sense of the word "functional" in "functional
programming." The direct connection between programs and simple
mathematical objects supports both formal proofs of correctness
and sound informal reasoning about program behavior.
The other sense in which functional programming is "functional" is
that it emphasizes the use of functions (or methods) as
_first-class_ values -- i.e., values that can be passed as
arguments to other functions, returned as results, stored in data
structures, etc. The recognition that functions can be treated as
data in this way enables a host of useful and powerful idioms.
Other common features of functional languages include _algebraic
data types_ and _pattern matching_, which make it easy to construct
and manipulate rich data structures, and sophisticated
_polymorphic type systems_ that support abstraction and code
reuse. Coq shares all of these features.
The first half of this chapter introduces the most essential
elements of Coq's functional programming language. The second
half introduces some basic _tactics_ that can be used to prove
simple properties of Coq programs.
*)
(* ###################################################################### *)
(** * Enumerated Types *)
(** One unusual aspect of Coq is that its set of built-in
features is _extremely_ small. For example, instead of providing
the usual palette of atomic data types (booleans, integers,
strings, etc.), Coq offers an extremely powerful mechanism for
defining new data types from scratch -- so powerful that all these
familiar types arise as instances.
Naturally, the Coq distribution comes with an extensive standard
library providing definitions of booleans, numbers, and many
common data structures like lists and hash tables. But there is
nothing magic or primitive about these library definitions: they
are ordinary user code. To illustrate this, we will explicitly
recapitulate all the definitions we need in this course, rather
than just getting them implicitly from the library.
To see how this mechanism works, let's start with a very simple
example. *)
(* ###################################################################### *)
(** ** Days of the Week *)
(** The following declaration tells Coq that we are defining
a new set of data values -- a _type_. *)
Inductive day : Type :=
| monday : day
| tuesday : day
| wednesday : day
| thursday : day
| friday : day
| saturday : day
| sunday : day.
(** The type is called [day], and its members are [monday],
[tuesday], etc. The second and following lines of the definition
can be read "[monday] is a [day], [tuesday] is a [day], etc."
Having defined [day], we can write functions that operate on
days. *)
Definition next_weekday (d:day) : day :=
match d with
| monday => tuesday
| tuesday => wednesday
| wednesday => thursday
| thursday => friday
| friday => monday
| saturday => monday
| sunday => monday
end.
(** One thing to note is that the argument and return types of
this function are explicitly declared. Like most functional
programming languages, Coq can often figure out these types for
itself when they are not given explicitly -- i.e., it performs
some _type inference_ -- but we'll always include them to make
reading easier. *)
(** Having defined a function, we should check that it works on
some examples. There are actually three different ways to do this
in Coq.
First, we can use the command [Eval compute] to evaluate a
compound expression involving [next_weekday]. *)
Eval compute in (next_weekday friday).
(* ==> monday : day *)
Eval compute in (next_weekday (next_weekday saturday)).
(* ==> tuesday : day *)
(** If you have a computer handy, this would be an excellent
moment to fire up the Coq interpreter under your favorite IDE --
either CoqIde or Proof General -- and try this for yourself. Load
this file ([Basics.v]) from the book's accompanying Coq sources,
find the above example, submit it to Coq, and observe the
result. *)
(** The keyword [compute] tells Coq precisely how to
evaluate the expression we give it. For the moment, [compute] is
the only one we'll need; later on we'll see some alternatives that
are sometimes useful. *)
(** Second, we can record what we _expect_ the result to be in
the form of a Coq example: *)
Example test_next_weekday:
(next_weekday (next_weekday saturday)) = tuesday.
(** This declaration does two things: it makes an
assertion (that the second weekday after [saturday] is [tuesday]),
and it gives the assertion a name that can be used to refer to it
later. *)
(** Having made the assertion, we can also ask Coq to verify it,
like this: *)
Proof. simpl. reflexivity. Qed.
(** The details are not important for now (we'll come back to
them in a bit), but essentially this can be read as "The assertion
we've just made can be proved by observing that both sides of the
equality evaluate to the same thing, after some simplification." *)
(** Third, we can ask Coq to _extract_, from our [Definition], a
program in some other, more conventional, programming
language (OCaml, Scheme, or Haskell) with a high-performance
compiler. This facility is very interesting, since it gives us a
way to construct _fully certified_ programs in mainstream
languages. Indeed, this is one of the main uses for which Coq was
developed. We'll come back to this topic in later chapters. More
information can also be found in the Coq'Art book by Bertot and
Casteran, as well as the Coq reference manual. *)
(* ###################################################################### *)
(** ** Booleans *)
(** In a similar way, we can define the standard type [bool] of
booleans, with members [true] and [false]. *)
Inductive bool : Type :=
| true : bool
| false : bool.
(** Although we are rolling our own booleans here for the sake
of building up everything from scratch, Coq does, of course,
provide a default implementation of the booleans in its standard
library, together with a multitude of useful functions and
lemmas. (Take a look at [Coq.Init.Datatypes] in the Coq library
documentation if you're interested.) Whenever possible, we'll
name our own definitions and theorems so that they exactly
coincide with the ones in the standard library. *)
(** Functions over booleans can be defined in the same way as
above: *)
Definition negb (b:bool) : bool :=
match b with
| true => false
| false => true
end.
Definition andb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => b2
| false => false
end.
Definition orb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => true
| false => b2
end.
(** The last two illustrate the syntax for multi-argument
function definitions. *)
(** The following four "unit tests" constitute a complete
specification -- a truth table -- for the [orb] function: *)
Example test_orb1: (orb true false) = true.
Proof. reflexivity. Qed.
Example test_orb2: (orb false false) = false.
Proof. reflexivity. Qed.
Example test_orb3: (orb false true) = true.
Proof. reflexivity. Qed.
Example test_orb4: (orb true true) = true.
Proof. reflexivity. Qed.
(** (Note that we've dropped the [simpl] in the proofs. It's not
actually needed because [reflexivity] automatically performs
simplification.) *)
(** _A note on notation_: In .v files, we use square brackets to
delimit fragments of Coq code within comments; this convention,
also used by the [coqdoc] documentation tool, keeps them visually
separate from the surrounding text. In the html version of the
files, these pieces of text appear in a [different font]. *)
(** The values [Admitted] and [admit] can be used to fill
a hole in an incomplete definition or proof. We'll use them in the
following exercises. In general, your job in the exercises is
to replace [admit] or [Admitted] with real definitions or proofs. *)
(** **** Exercise: 1 star (nandb) *)
(** Complete the definition of the following function, then make
sure that the [Example] assertions below can each be verified by
Coq. *)
(** This function should return [true] if either or both of
its inputs are [false]. *)
Definition nandb (b1:bool) (b2:bool) : bool := negb (andb b1 b2).
(** Remove "[Admitted.]" and fill in each proof with
"[Proof. reflexivity. Qed.]" *)
Example test_nandb1: (nandb true false) = true.
Proof. reflexivity. Qed.
Example test_nandb2: (nandb false false) = true.
Proof. reflexivity. Qed.
Example test_nandb3: (nandb false true) = true.
Proof. reflexivity. Qed.
Example test_nandb4: (nandb true true) = false.
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 1 star (andb3) *)
(** Do the same for the [andb3] function below. This function should
return [true] when all of its inputs are [true], and [false]
otherwise. *)
Definition andb3 (b1:bool) (b2:bool) (b3:bool) : bool :=
andb (andb b1 b2) b3.
Example test_andb31: (andb3 true true true) = true.
Proof. reflexivity. Qed.
Example test_andb32: (andb3 false true true) = false.
Proof. reflexivity. Qed.
Example test_andb33: (andb3 true false true) = false.
Proof. reflexivity. Qed.
Example test_andb34: (andb3 true true false) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** ** Function Types *)
(** The [Check] command causes Coq to print the type of an
expression. For example, the type of [negb true] is [bool]. *)
Check true.
(* ===> true : bool *)
Check (negb true).
(* ===> negb true : bool *)
(** Functions like [negb] itself are also data values, just like
[true] and [false]. Their types are called _function types_, and
they are written with arrows. *)
Check negb.
(* ===> negb : bool -> bool *)
(** The type of [negb], written [bool -> bool] and pronounced
"[bool] arrow [bool]," can be read, "Given an input of type
[bool], this function produces an output of type [bool]."
Similarly, the type of [andb], written [bool -> bool -> bool], can
be read, "Given two inputs, both of type [bool], this function
produces an output of type [bool]." *)
(* ###################################################################### *)
(** ** Numbers *)
(** _Technical digression_: Coq provides a fairly sophisticated
_module system_, to aid in organizing large developments. In this
course we won't need most of its features, but one is useful: If
we enclose a collection of declarations between [Module X] and
[End X] markers, then, in the remainder of the file after the
[End], these definitions will be referred to by names like [X.foo]
instead of just [foo]. Here, we use this feature to introduce the
definition of the type [nat] in an inner module so that it does
not shadow the one from the standard library. *)
Module Playground1.
(** The types we have defined so far are examples of "enumerated
types": their definitions explicitly enumerate a finite set of
elements. A more interesting way of defining a type is to give a
collection of "inductive rules" describing its elements. For
example, we can define the natural numbers as follows: *)
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
(** The clauses of this definition can be read:
- [O] is a natural number (note that this is the letter "[O]," not
the numeral "[0]").
- [S] is a "constructor" that takes a natural number and yields
another one -- that is, if [n] is a natural number, then [S n]
is too.
Let's look at this in a little more detail.
Every inductively defined set ([day], [nat], [bool], etc.) is
actually a set of _expressions_. The definition of [nat] says how
expressions in the set [nat] can be constructed:
- the expression [O] belongs to the set [nat];
- if [n] is an expression belonging to the set [nat], then [S n]
is also an expression belonging to the set [nat]; and
- expressions formed in these two ways are the only ones belonging
to the set [nat].
The same rules apply for our definitions of [day] and [bool]. The
annotations we used for their constructors are analogous to the
one for the [O] constructor, and indicate that each of those
constructors doesn't take any arguments. *)
(** These three conditions are the precise force of the
[Inductive] declaration. They imply that the expression [O], the
expression [S O], the expression [S (S O)], the expression
[S (S (S O))], and so on all belong to the set [nat], while other
expressions like [true], [andb true false], and [S (S false)] do
not.
We can write simple functions that pattern match on natural
numbers just as we did above -- for example, the predecessor
function: *)
Definition pred (n : nat) : nat :=
match n with
| O => O
| S n' => n'
end.
(** The second branch can be read: "if [n] has the form [S n']
for some [n'], then return [n']." *)
End Playground1.
Definition minustwo (n : nat) : nat :=
match n with
| O => O
| S O => O
| S (S n') => n'
end.
(** Because natural numbers are such a pervasive form of data,
Coq provides a tiny bit of built-in magic for parsing and printing
them: ordinary arabic numerals can be used as an alternative to
the "unary" notation defined by the constructors [S] and [O]. Coq
prints numbers in arabic form by default: *)
Check (S (S (S (S O)))).
Eval compute in (minustwo 4).
(** The constructor [S] has the type [nat -> nat], just like the
functions [minustwo] and [pred]: *)
Check S.
Check pred.
Check minustwo.
(** These are all things that can be applied to a number to yield a
number. However, there is a fundamental difference: functions
like [pred] and [minustwo] come with _computation rules_ -- e.g.,
the definition of [pred] says that [pred 2] can be simplified to
[1] -- while the definition of [S] has no such behavior attached.
Although it is like a function in the sense that it can be applied
to an argument, it does not _do_ anything at all! *)
(** For most function definitions over numbers, pure pattern
matching is not enough: we also need recursion. For example, to
check that a number [n] is even, we may need to recursively check
whether [n-2] is even. To write such functions, we use the
keyword [Fixpoint]. *)
Fixpoint evenb (n:nat) : bool :=
match n with
| O => true
| S O => false
| S (S n') => evenb n'
end.
(** We can define [oddb] by a similar [Fixpoint] declaration, but here
is a simpler definition that will be a bit easier to work with: *)
Definition oddb (n:nat) : bool := negb (evenb n).
Example test_oddb1: (oddb (S O)) = true.
Proof. reflexivity. Qed.
Example test_oddb2: (oddb (S (S (S (S O))))) = false.
Proof. reflexivity. Qed.
(** Naturally, we can also define multi-argument functions by
recursion. (Once again, we use a module to avoid polluting the
namespace.) *)
Module Playground2.
Fixpoint plus (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus n' m)
end.
(** Adding three to two now gives us five, as we'd expect. *)
Eval compute in (plus (S (S (S O))) (S (S O))).
(** The simplification that Coq performs to reach this conclusion can
be visualized as follows: *)
(* [plus (S (S (S O))) (S (S O))]
==> [S (plus (S (S O)) (S (S O)))] by the second clause of the [match]
==> [S (S (plus (S O) (S (S O))))] by the second clause of the [match]
==> [S (S (S (plus O (S (S O)))))] by the second clause of the [match]
==> [S (S (S (S (S O))))] by the first clause of the [match]
*)
(** As a notational convenience, if two or more arguments have
the same type, they can be written together. In the following
definition, [(n m : nat)] means just the same as if we had written
[(n : nat) (m : nat)]. *)
Fixpoint mult (n m : nat) : nat :=
match n with
| O => O
| S n' => plus m (mult n' m)
end.
Example test_mult1: (mult 3 3) = 9.
Proof. reflexivity. Qed.
(** You can match two expressions at once by putting a comma
between them: *)
Fixpoint minus (n m:nat) : nat :=
match n, m with
| O , _ => O
| S _ , O => n
| S n', S m' => minus n' m'
end.
(** The _ in the first line is a _wildcard pattern_. Writing _ in a
pattern is the same as writing some variable that doesn't get used
on the right-hand side. This avoids the need to invent a bogus
variable name. *)
End Playground2.
Fixpoint exp (base power : nat) : nat :=
match power with
| O => S O
| S p => mult base (exp base p)
end.
(** **** Exercise: 1 star (factorial) *)
(** Recall the standard factorial function:
<<
factorial(0) = 1
factorial(n) = n * factorial(n-1) (if n>0)
>>
Translate this into Coq. *)
Fixpoint factorial (n:nat) : nat :=
match n with
| O => 1
| S n' => n * factorial n'
end.
Example test_factorial1: (factorial 3) = 6.
Proof. reflexivity. Qed.
Example test_factorial2: (factorial 5) = (mult 10 12).
Proof. reflexivity. Qed.
(** [] *)
(** We can make numerical expressions a little easier to read and
write by introducing "notations" for addition, multiplication, and
subtraction. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x - y" := (minus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
Check ((0 + 1) + 1).
(** (The [level], [associativity], and [nat_scope] annotations
control how these notations are treated by Coq's parser. The
details are not important, but interested readers can refer to the
"More on Notation" subsection in the "Advanced Material" section at
the end of this chapter.) *)
(** Note that these do not change the definitions we've already
made: they are simply instructions to the Coq parser to accept [x
+ y] in place of [plus x y] and, conversely, to the Coq
pretty-printer to display [plus x y] as [x + y]. *)
(** When we say that Coq comes with nothing built-in, we really
mean it: even equality testing for numbers is a user-defined
operation! *)
(** The [beq_nat] function tests [nat]ural numbers for [eq]uality,
yielding a [b]oolean. Note the use of nested [match]es (we could
also have used a simultaneous match, as we did in [minus].) *)
Fixpoint beq_nat (n m : nat) : bool :=
match n with
| O => match m with
| O => true
| S m' => false
end
| S n' => match m with
| O => false
| S m' => beq_nat n' m'
end
end.
(** Similarly, the [ble_nat] function tests [nat]ural numbers for
[l]ess-or-[e]qual, yielding a [b]oolean. *)
Fixpoint ble_nat (n m : nat) : bool :=
match n with
| O => true
| S n' =>
match m with
| O => false
| S m' => ble_nat n' m'
end
end.
Example test_ble_nat1: (ble_nat 2 2) = true.
Proof. reflexivity. Qed.
Example test_ble_nat2: (ble_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_ble_nat3: (ble_nat 4 2) = false.
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (blt_nat) *)
(** The [blt_nat] function tests [nat]ural numbers for [l]ess-[t]han,
yielding a [b]oolean. Instead of making up a new [Fixpoint] for
this one, define it in terms of a previously defined function. *)
Definition blt_nat (n m : nat) : bool := andb (ble_nat n m) (negb (beq_nat n m)).
Example test_blt_nat1: (blt_nat 2 2) = false.
Proof. reflexivity. Qed.
Example test_blt_nat2: (blt_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_blt_nat3: (blt_nat 4 2) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Simplification *)
(** Now that we've defined a few datatypes and functions, let's
turn to the question of how to state and prove properties of their
behavior. Actually, in a sense, we've already started doing this:
each [Example] in the previous sections makes a precise claim
about the behavior of some function on some particular inputs.
The proofs of these claims were always the same: use [reflexivity]
to check that both sides of the [=] simplify to identical values.
(By the way, it will be useful later to know that
[reflexivity] actually does somewhat more simplification than [simpl]
does -- for example, it tries "unfolding" defined terms, replacing them with
their right-hand sides. The reason for this difference is that,
when reflexivity succeeds, the whole goal is finished and we don't
need to look at whatever expanded expressions [reflexivity] has
found; by contrast, [simpl] is used in situations where we may
have to read and understand the new goal, so we would not want it
blindly expanding definitions.)
The same sort of "proof by simplification" can be used to prove
more interesting properties as well. For example, the fact that
[0] is a "neutral element" for [+] on the left can be proved
just by observing that [0 + n] reduces to [n] no matter what
[n] is, a fact that can be read directly off the definition of [plus].*)
Theorem plus_O_n : forall n : nat, 0 + n = n.
Proof.
intros n. reflexivity. Qed.
(** (_Note_: You may notice that the above statement looks
different in the original source file and the final html output. In Coq
files, we write the [forall] universal quantifier using the
"_forall_" reserved identifier. This gets printed as an
upside-down "A", the familiar symbol used in logic.) *)
(** The form of this theorem and proof are almost exactly the
same as the examples above; there are just a few differences.
First, we've used the keyword [Theorem] instead of
[Example]. Indeed, the difference is purely a matter of
style; the keywords [Example] and [Theorem] (and a few others,
including [Lemma], [Fact], and [Remark]) mean exactly the same
thing to Coq.
Secondly, we've added the quantifier [forall n:nat], so that our
theorem talks about _all_ natural numbers [n]. In order to prove
theorems of this form, we need to to be able to reason by
_assuming_ the existence of an arbitrary natural number [n]. This
is achieved in the proof by [intros n], which moves the quantifier
from the goal to a "context" of current assumptions. In effect, we
start the proof by saying "OK, suppose [n] is some arbitrary number."
The keywords [intros], [simpl], and [reflexivity] are examples of
_tactics_. A tactic is a command that is used between [Proof] and
[Qed] to tell Coq how it should check the correctness of some
claim we are making. We will see several more tactics in the rest
of this lecture, and yet more in future lectures. *)
(** We could try to prove a similar theorem about [plus] *)
Theorem plus_n_O : forall n, n + 0 = n.
(** However, unlike the previous proof, [simpl] doesn't do anything in
this case *)
Proof.
simpl. (* Doesn't do anything! *)
Abort.
(** (Can you explain why this happens? Step through both proofs with
Coq and notice how the goal and context change.) *)
Theorem plus_1_l : forall n:nat, 1 + n = S n.
Proof.
intros n. reflexivity. Qed.
Theorem mult_0_l : forall n:nat, 0 * n = 0.
Proof.
intros n. reflexivity. Qed.
(** The [_l] suffix in the names of these theorems is
pronounced "on the left." *)
(* ###################################################################### *)
(** * Proof by Rewriting *)
(** Here is a slightly more interesting theorem: *)
Theorem plus_id_example : forall n m:nat,
n = m ->
n + n = m + m.
(** Instead of making a completely universal claim about all numbers
[n] and [m], this theorem talks about a more specialized property
that only holds when [n = m]. The arrow symbol is pronounced
"implies."
As before, we need to be able to reason by assuming the existence
of some numbers [n] and [m]. We also need to assume the hypothesis
[n = m]. The [intros] tactic will serve to move all three of these
from the goal into assumptions in the current context.
Since [n] and [m] are arbitrary numbers, we can't just use
simplification to prove this theorem. Instead, we prove it by
observing that, if we are assuming [n = m], then we can replace
[n] with [m] in the goal statement and obtain an equality with the
same expression on both sides. The tactic that tells Coq to
perform this replacement is called [rewrite]. *)
Proof.
intros n m. (* move both quantifiers into the context *)
intros H. (* move the hypothesis into the context *)
rewrite -> H. (* Rewrite the goal using the hypothesis *)
reflexivity. Qed.
(** The first line of the proof moves the universally quantified
variables [n] and [m] into the context. The second moves the
hypothesis [n = m] into the context and gives it the (arbitrary)
name [H]. The third tells Coq to rewrite the current goal ([n + n
= m + m]) by replacing the left side of the equality hypothesis
[H] with the right side.
(The arrow symbol in the [rewrite] has nothing to do with
implication: it tells Coq to apply the rewrite from left to right.
To rewrite from right to left, you can use [rewrite <-]. Try
making this change in the above proof and see what difference it
makes in Coq's behavior.) *)
(** **** Exercise: 1 star (plus_id_exercise) *)
(** Remove "[Admitted.]" and fill in the proof. *)
Theorem plus_id_exercise : forall n m o : nat,
n = m -> m = o -> n + m = m + o.
Proof.
intros n m o H1 H2.
rewrite H1. rewrite H2. reflexivity.
Qed.
(** [] *)
(** As we've seen in earlier examples, the [Admitted] command
tells Coq that we want to skip trying to prove this theorem and
just accept it as a given. This can be useful for developing
longer proofs, since we can state subsidiary facts that we believe
will be useful for making some larger argument, use [Admitted] to
accept them on faith for the moment, and continue thinking about
the larger argument until we are sure it makes sense; then we can
go back and fill in the proofs we skipped. Be careful, though:
every time you say [Admitted] (or [admit]) you are leaving a door
open for total nonsense to enter Coq's nice, rigorous, formally
checked world! *)
(** We can also use the [rewrite] tactic with a previously proved
theorem instead of a hypothesis from the context. *)
Theorem mult_0_plus : forall n m : nat,
(0 + n) * m = n * m.
Proof.
intros n m.
rewrite -> plus_O_n.
reflexivity. Qed.
(** **** Exercise: 2 stars (mult_S_1) *)
Theorem mult_S_1 : forall n m : nat,
m = S n ->
m * (1 + n) = m * m.
Proof.
intros n m H.
rewrite plus_1_l. rewrite H. reflexivity.
Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Case Analysis *)
(** Of course, not everything can be proved by simple
calculation: In general, unknown, hypothetical values (arbitrary
numbers, booleans, lists, etc.) can block the calculation.
For example, if we try to prove the following fact using the
[simpl] tactic as above, we get stuck. *)
Theorem plus_1_neq_0_firsttry : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n.
simpl. (* does nothing! *)
Abort.
(** The reason for this is that the definitions of both
[beq_nat] and [+] begin by performing a [match] on their first
argument. But here, the first argument to [+] is the unknown
number [n] and the argument to [beq_nat] is the compound
expression [n + 1]; neither can be simplified.
What we need is to be able to consider the possible forms of [n]
separately. If [n] is [O], then we can calculate the final result
of [beq_nat (n + 1) 0] and check that it is, indeed, [false].
And if [n = S n'] for some [n'], then, although we don't know
exactly what number [n + 1] yields, we can calculate that, at
least, it will begin with one [S], and this is enough to calculate
that, again, [beq_nat (n + 1) 0] will yield [false].
The tactic that tells Coq to consider, separately, the cases where
[n = O] and where [n = S n'] is called [destruct]. *)
Theorem plus_1_neq_0 : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n. destruct n as [| n'].
reflexivity.
reflexivity. Qed.
(** The [destruct] generates _two_ subgoals, which we must then
prove, separately, in order to get Coq to accept the theorem as
proved. (No special command is needed for moving from one subgoal
to the other. When the first subgoal has been proved, it just
disappears and we are left with the other "in focus.") In this
proof, each of the subgoals is easily proved by a single use of
[reflexivity].
The annotation "[as [| n']]" is called an _intro pattern_. It
tells Coq what variable names to introduce in each subgoal. In
general, what goes between the square brackets is a _list_ of
lists of names, separated by [|]. Here, the first component is
empty, since the [O] constructor is nullary (it doesn't carry any
data). The second component gives a single name, [n'], since [S]
is a unary constructor.
The [destruct] tactic can be used with any inductively defined
datatype. For example, we use it here to prove that boolean
negation is involutive -- i.e., that negation is its own
inverse. *)
Theorem negb_involutive : forall b : bool,
negb (negb b) = b.
Proof.
intros b. destruct b.
reflexivity.
reflexivity. Qed.
(** Note that the [destruct] here has no [as] clause because
none of the subcases of the [destruct] need to bind any variables,
so there is no need to specify any names. (We could also have
written [as [|]], or [as []].) In fact, we can omit the [as]
clause from _any_ [destruct] and Coq will fill in variable names
automatically. Although this is convenient, it is arguably bad
style, since Coq often makes confusing choices of names when left
to its own devices. *)
(** **** Exercise: 1 star (zero_nbeq_plus_1) *)
Theorem zero_nbeq_plus_1 : forall n : nat,
beq_nat 0 (n + 1) = false.
Proof.
intro n. destruct n.
reflexivity.
reflexivity.
Qed.
(** [] *)
(* ###################################################################### *)
(** * More Exercises *)
(** **** Exercise: 2 stars (boolean_functions) *)
(** Use the tactics you have learned so far to prove the following
theorem about boolean functions. *)
Theorem identity_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = x) ->
forall (b : bool), f (f b) = b.
Proof.
intros f H b.
rewrite H. rewrite H. reflexivity.
Qed.
(** Now state and prove a theorem [negation_fn_applied_twice] similar
to the previous one but where the second hypothesis says that the
function [f] has the property that [f x = negb x].*)
Theorem negation_fn_applied_twice :
forall f : bool -> bool,
(forall x : bool, f x = negb x) ->
forall b : bool, f (f b) = b.
Proof.
intros f H b.
rewrite H. rewrite H. rewrite negb_involutive. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars (andb_eq_orb) *)
(** Prove the following theorem. (You may want to first prove a
subsidiary lemma or two. Alternatively, remember that you do
not have to introduce all hypotheses at the same time.) *)
Theorem andb_eq_orb :
forall (b c : bool),
(andb b c = orb b c) ->
b = c.
Proof.
intros b c H.
destruct b; destruct c; simpl in *; congruence.
Qed.
(** [] *)
(** **** Exercise: 3 stars (binary) *)
(** Consider a different, more efficient representation of natural
numbers using a binary rather than unary system. That is, instead
of saying that each natural number is either zero or the successor
of a natural number, we can say that each binary number is either
- zero,
- twice a binary number, or
- one more than twice a binary number.
(a) First, write an inductive definition of the type [bin]
corresponding to this description of binary numbers.
(Hint: Recall that the definition of [nat] from class,
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
says nothing about what [O] and [S] "mean." It just says "[O] is
in the set called [nat], and if [n] is in the set then so is [S
n]." The interpretation of [O] as zero and [S] as successor/plus
one comes from the way that we _use_ [nat] values, by writing
functions to do things with them, proving things about them, and
so on. Your definition of [bin] should be correspondingly simple;
it is the functions you will write next that will give it
mathematical meaning.)
(b) Next, write an increment function [incr] for binary numbers,
and a function [bin_to_nat] to convert binary numbers to unary numbers.
(c) Write five unit tests [test_bin_incr1], [test_bin_incr2], etc.
for your increment and binary-to-unary functions. Notice that
incrementing a binary number and then converting it to unary
should yield the same result as first converting it to unary and
then incrementing.
*)
Inductive bin :=
| bZ : bin
| bO : bin -> bin
| bI : bin -> bin.
Fixpoint incr (b : bin) :=
match b with
| bZ => bI bZ
| bO b' => bI b'
| bI b' => bO (incr b')
end.
Fixpoint bin_to_nat (b : bin) : nat :=
match b with
| bZ => 0
| bO b' => 2 * bin_to_nat b'
| bI b' => 1 + 2 * bin_to_nat b'
end.
Example test_bin_incr1 : bin_to_nat (incr bZ) = S (bin_to_nat bZ).
Proof. reflexivity. Qed.
Example test_bin_incr2 : bin_to_nat (incr (bO bZ)) = S (bin_to_nat (bO bZ)).
Proof. reflexivity. Qed.
Example test_bin_incr3 : bin_to_nat (incr (bI bZ)) = S (bin_to_nat (bI bZ)).
Proof. reflexivity. Qed.
Example test_bin_incr4 : bin_to_nat (incr (bO (bI bZ))) = S (bin_to_nat (bO (bI bZ))).
Proof. reflexivity. Qed.
Example test_bin_incr5 : bin_to_nat (incr (bI (bO bZ))) = S (bin_to_nat (bI (bO bZ))).
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * More on Notation (Advanced) *)
(** In general, sections marked Advanced are not needed to follow the
rest of the book, except possibly other Advanced sections. On a
first reading, you might want to skim these sections so that you
know what's there for future reference. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
(** For each notation-symbol in Coq we can specify its _precedence level_
and its _associativity_. The precedence level n can be specified by the
keywords [at level n] and it is helpful to disambiguate
expressions containing different symbols. The associativity is helpful
to disambiguate expressions containing more occurrences of the same
symbol. For example, the parameters specified above for [+] and [*]
say that the expression [1+2*3*4] is a shorthand for the expression
[(1+((2*3)*4))]. Coq uses precedence levels from 0 to 100, and
_left_, _right_, or _no_ associativity.
Each notation-symbol in Coq is also active in a _notation scope_.
Coq tries to guess what scope you mean, so when you write [S(O*O)]
it guesses [nat_scope], but when you write the cartesian
product (tuple) type [bool*bool] it guesses [type_scope].
Occasionally you have to help it out with percent-notation by
writing [(x*y)%nat], and sometimes in Coq's feedback to you it
will use [%nat] to indicate what scope a notation is in.
Notation scopes also apply to numeral notation (3,4,5, etc.), so you
may sometimes see [0%nat] which means [O], or [0%Z] which means the
Integer zero.
*)
(** * [Fixpoint] and Structural Recursion (Advanced) *)
Fixpoint plus' (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus' n' m)
end.
(** When Coq checks this definition, it notes that [plus'] is
"decreasing on 1st argument." What this means is that we are
performing a _structural recursion_ over the argument [n] -- i.e.,
that we make recursive calls only on strictly smaller values of
[n]. This implies that all calls to [plus'] will eventually
terminate. Coq demands that some argument of _every_ [Fixpoint]
definition is "decreasing".
This requirement is a fundamental feature of Coq's design: In
particular, it guarantees that every function that can be defined
in Coq will terminate on all inputs. However, because Coq's
"decreasing analysis" is not very sophisticated, it is sometimes
necessary to write functions in slightly unnatural ways. *)
(** **** Exercise: 2 stars, optional (decreasing) *)
(** To get a concrete sense of this, find a way to write a sensible
[Fixpoint] definition (of a simple function on numbers, say) that
_does_ terminate on all inputs, but that Coq will reject because
of this restriction. *)
(* Fixpoint sad_coq (n : nat) : nat :=
match n with
| O => sad_coq (S n)
| S _ => O
end. *)
(** [] *)
(** $Date: 2014-12-31 15:31:47 -0500 (Wed, 31 Dec 2014) $ *)
(** $Done: 2016-03-10 13:14:38 -0500 (Thu, 10 Mar 2016) $ *)
|
/**
* ------------------------------------------------------------
* Copyright (c) SILAB , Physics Institute of Bonn University
* ------------------------------------------------------------
*/
`timescale 1ps / 1ps
`include "utils/bus_to_ip.v"
`include "i2c/i2c.v"
`include "i2c/i2c_core.v"
`include "utils/cdc_pulse_sync.v"
`include "utils/clock_divider.v"
`include "utils/ODDR_sim.v"
`include "utils/IDDR_sim.v"
module i2c_slave_model (
input wire SCL,
inout wire SDA
);
parameter ADDRESS = 7'b1001001;
reg START;
//initial START = 1;
always@(negedge SDA or negedge SCL)
if(~SCL)
START <= 0;
else
START <= 1;
reg [7:0] REC_ADDRESS;
localparam STATE_IDLE = 0, STATE_START = 1, STATE_ADDR = 2, STATE_AACK = 4, STATE_DATA_W = 5, STATE_DATA_R = 6, STATE_DACK_W = 7, STATE_DACK_R = 8, STATE_DACK_LAST = 9, STATE_STOP = 10;
reg [3:0] state, next_state;
reg [2:0] bit_count;
reg [15:0] byte_count;
initial state = STATE_IDLE;
always @ (posedge SCL or posedge START) begin
if (START)
state <= STATE_ADDR;
else
state <= next_state;
end
//rec stop
always @ (*) begin
next_state = state;
case(state)
STATE_IDLE:
next_state = state;
STATE_ADDR:
if(bit_count==7)
next_state = STATE_AACK;
STATE_AACK:
if(REC_ADDRESS[7:1] == ADDRESS) begin
if(REC_ADDRESS[0])
next_state = STATE_DATA_R;
else
next_state = STATE_DATA_W;
end
else
next_state = STATE_IDLE;
STATE_DATA_R:
if(bit_count==7)
next_state = STATE_DACK_R;
STATE_DATA_W:
if(bit_count==7)
next_state = STATE_DACK_W;
STATE_DACK_W:
next_state = STATE_DATA_W;
STATE_DACK_R:
if(SDA==0)
next_state = STATE_DATA_R;
else
next_state = STATE_IDLE;
endcase
end
always @ (posedge SCL or posedge START) begin
if(START)
bit_count <= 0;
else if (state == STATE_AACK | state == STATE_DACK_R | state == STATE_DACK_W )
bit_count <= 0;
else
bit_count <= bit_count + 1;
end
always @ (posedge SCL or posedge START) begin
if (START)
byte_count <= 0;
else if(next_state == STATE_DACK_W | next_state == STATE_DACK_R)
byte_count <= byte_count + 1;
end
always @ (posedge SCL)
if(state == STATE_ADDR)
REC_ADDRESS[7-bit_count] = SDA;
reg [7:0] BYTE_DATA_IN;
always @ (posedge SCL)
if(state == STATE_DATA_W)
BYTE_DATA_IN[7-bit_count] = SDA;
reg [7:0] mem_addr;
always @ (posedge SCL) begin
if(byte_count == 0 & next_state == STATE_DACK_W )
mem_addr <= BYTE_DATA_IN;
else if(next_state == STATE_DACK_R | next_state == STATE_DACK_W)
mem_addr <= mem_addr + 1;
end
reg [7:0] mem [255:0];
wire MEM_WE;
assign MEM_WE = next_state == STATE_DACK_W & byte_count != 0;
always @ (posedge SCL or posedge START)
if(MEM_WE) begin
mem[mem_addr] <= BYTE_DATA_IN;
end
wire [7:0] BYTE_DATA_OUT;
assign BYTE_DATA_OUT = mem[mem_addr];
wire SDA_PRE;
assign SDA_PRE = ((state == STATE_AACK & REC_ADDRESS[7:1] == ADDRESS) | state == STATE_DACK_W) ? 1'b0 : state == STATE_DATA_R ? BYTE_DATA_OUT[7-bit_count] : 1;
reg SDAR;
initial SDAR = 1;
always @ (negedge SCL)
SDAR <= SDA_PRE;
assign SDA = SDAR ? 1'bz : 1'b0;
endmodule
module tb (
input wire BUS_CLK,
input wire BUS_RST,
input wire [31:0] BUS_ADD,
inout wire [31:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
output wire BUS_BYTE_ACCESS
);
// MODULE ADREESSES //
localparam I2C_BASEADDR = 32'h1000;
localparam I2C_HIGHADDR = 32'h2000-1;
localparam ABUSWIDTH = 32;
assign BUS_BYTE_ACCESS = BUS_ADD < 32'h8000_0000 ? 1'b1 : 1'b0;
wire I2C_CLK;
clock_divider #(
.DIVISOR(4)
) i_clock_divisor_spi (
.CLK(BUS_CLK),
.RESET(1'b0),
.CE(),
.CLOCK(I2C_CLK)
);
wire SDA, SCL;
pullup isda (SDA);
pullup iscl (SCL);
i2c
#(
.BASEADDR(I2C_BASEADDR),
.HIGHADDR(I2C_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.MEM_BYTES(32)
) i_i2c
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.I2C_CLK(I2C_CLK),
.I2C_SDA(SDA),
.I2C_SCL(SCL)
);
i2c_slave_model ii2c_slave_model (.SDA(SDA), .SCL(SCL));
initial begin
$dumpfile("i2c.vcd");
$dumpvars(0);
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XNOR2_FUNCTIONAL_V
`define SKY130_FD_SC_HD__XNOR2_FUNCTIONAL_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__xnor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Local signals
wire xnor0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y, A, B );
buf buf0 (Y , xnor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__XNOR2_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR2B_PP_SYMBOL_V
`define SKY130_FD_SC_LP__NOR2B_PP_SYMBOL_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nor2b (
//# {{data|Data Signals}}
input A ,
input B_N ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR2B_PP_SYMBOL_V
|
// BF2HW
// Copyright (C) 2017 Christian Fibich
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3 of the License, or
// (at your option) any later version.
//
// IP for the bambu_putchar() function. Writes a single character
//
module bambu_putchar (input clock, input reset, input start_port, output reg done_port, input [7:0] c, output reg [7:0] TX_DATA, output reg TX_ENABLE, input TX_READY);
reg fifo_read;
wire [7:0] fifo_out;
wire fifo_empty;
reg [7:0] fifo_in;
reg fifo_write;
wire fifo_full;
sync_fifo #(.width(8))
the_fifo (.clk(clock), .reset(reset), .wr_enable(fifo_write), .rd_enable(fifo_read),
.empty(fifo_empty), .full(fifo_full), .rd_data(fifo_out), .wr_data(fifo_in),
.count());
reg [1:0] fifo_state;
reg [2:0] tx_state;
reg TX_READY_reg;
wire TX_READY_posedge;
localparam FIFO_STATE_IDLE = 2'b01,
FIFO_STATE_WRITE = 2'b10;
localparam TX_STATE_IDLE = 3'b001,
TX_STATE_TX_BYTE = 3'b010,
TX_STATE_WAIT_TX_READY = 3'b100;
always @(posedge clock or posedge reset)
begin
if (reset) begin
fifo_write <= 1'b0;
done_port <= 1'b0;
fifo_state <= FIFO_STATE_IDLE;
end else begin
done_port <= 1'b0;
fifo_write <= 1'b0;
if (fifo_state == FIFO_STATE_IDLE) begin
if (start_port) begin
fifo_in <= c;
fifo_state <= FIFO_STATE_WRITE;
end
end else begin
if (fifo_full == 1'b0) begin
fifo_write <= 1'b1;
fifo_state <= FIFO_STATE_IDLE;
done_port <= 1'b1;
end
end
end
end
assign TX_READY_posedge = TX_READY & ~TX_READY_reg;
always @(posedge clock or posedge reset)
begin
if (reset) begin
tx_state <= TX_STATE_IDLE;
TX_DATA <= 8'b0;
TX_ENABLE <= 1'b0;
fifo_read <= 1'b0;
TX_READY_reg <= 1'b0;
end else begin
fifo_read <= 1'b0;
TX_ENABLE <= 1'b0;
TX_READY_reg <= TX_READY;
case(tx_state)
TX_STATE_IDLE : begin
if (fifo_empty == 1'b0 && TX_READY == 1'b1) begin
fifo_read <= 1'b1;
tx_state <= TX_STATE_TX_BYTE;
end
end
TX_STATE_TX_BYTE : begin
TX_DATA <= fifo_out;
TX_ENABLE <= 1'b1;
tx_state <= TX_STATE_WAIT_TX_READY;
end
TX_STATE_WAIT_TX_READY : begin
if (TX_READY_posedge == 1'b1)
tx_state <= TX_STATE_IDLE;
end
endcase
end
end
endmodule
|
`timescale 1ns / 1ps
module Print(CLK, TYPE, DIS, AN, display);
input CLK, TYPE, DIS;
output reg [3:0] AN; // λѡ¶Ë(4λ)
output reg [7:0] display; // ¶ÎÑ¡¶Ë(8λ)
reg [31:0] counter; // ¼ÆÊýÆ÷, ÓÃÓÚÊÊÅäÏÔʾ¼ä¸ôʱ¼ä
reg [31:0] move_counter; // ¼ÆÊýÆ÷, ÓÃÓÚÊÊÅä¹ö¶¯¼ä¸ôʱ¼ä
parameter [31:0] MAX_COUNTER = 5_0000; // ÏÔʾ¼ä¸ô
parameter [31:0] MAX_MOVE_COUNTER = 1_0000_0000; // ¹ö¶¯¼ä¸ô
parameter [31:0] ID = 32'H16340040; // ѧºÅ
reg [15:0] num; // ÐèÒªÏÔʾµÄλÊý
reg [4:0] tmp; // ÕýÔÚÏÔʾµÄÊý×Ö
initial begin
AN = 4'B0111;
display = 8'B0000_0000;
counter = 0;
move_counter = MAX_MOVE_COUNTER + 1;
num = ID[15:0];
end
always@(AN) begin
case(AN)
4'B0111: tmp = num[15:12];
4'B1011: tmp = num[11:8];
4'B1101: tmp = num[7:4];
4'B1110: tmp = num[3:0];
endcase
case(tmp)
4'H0: display = 8'B0000_0011;
4'H1: display = 8'B1001_1111;
4'H2: display = 8'B0010_0101;
4'H3: display = 8'B0000_1101;
4'H4: display = 8'B1001_1001;
4'H5: display = 8'B0100_1001;
4'H6: display = 8'B0100_0001;
4'H7: display = 8'B0001_1111;
4'H8: display = 8'B0000_0001;
4'H9: display = 8'B0000_1001;
4'Hf: display = 8'B1111_1111; // blank
endcase
end
always@(posedge CLK) begin
counter = counter + 1;
if(counter == MAX_COUNTER) begin
AN = (AN >> 1) + 4'B1000;
counter = 0;
end
if(AN == 4'B1111) begin
AN = 4'B0111;
end
if(TYPE == 1) begin
if(move_counter == MAX_MOVE_COUNTER + 1) begin
// Èç¹ûmove_counter == MAX_MOVE_COUNTER + 1
// Ôò˵Ã÷TYPE¸Õ¸Õ´Ó0->1, Ïȸ´Î»numΪǰËÄλ
num = ID[31:16];
move_counter = 0;
end
move_counter = move_counter + 1;
if(move_counter == MAX_MOVE_COUNTER) begin
// ¹ö¶¯ÐèÒªÏÔʾµÄѧºÅ
case(num)
ID[31:16]: num = ID[27:12];
ID[27:12]: num = ID[23:8];
ID[23:8]: num = ID[19:4];
ID[19:4]: num = ID[15:0];
ID[15:0]: num = {ID[11:0], 4'Hf};
{ID[11:0], 4'Hf}: num = {ID[7:0], 8'Hff};
{ID[7:0], 8'Hff}: num = {ID[3:0], 12'Hfff};
{ID[3:0], 12'Hfff}: num = 16'Hffff;
16'Hffff: num = {12'Hfff, ID[31:28]};
{12'Hfff, ID[31:28]}: num = {8'Hff, ID[31:24]};
{8'Hff, ID[31:24]}: num = {4'Hf, ID[31:20]};
{4'Hf, ID[31:20]}: num = ID[31:16];
endcase
move_counter = 0;
end
end else begin
case(DIS)
0: num = ID[15:0];
1: num = ID[31:16];
endcase
move_counter = MAX_MOVE_COUNTER + 1;
end
end
endmodule |
//----------------------------------------------------------------------------
// Title : Testbench for BPM Swap Wishbone Slave
//----------------------------------------------------------------------------
// Author : Jose Alvim Berkenbrock
// Company : CNPEM LNLS-DIG
// Platform : FPGA-generic
//-----------------------------------------------------------------------------
// Description: This desing put together a wishbone master and slave block for
// control of swap channels in RF Front-End Board.
//-----------------------------------------------------------------------------
// Copyright (c) 2013 CNPEM
// Licensed under GNU Lesser General Public License (LGPL) v3.0
//-----------------------------------------------------------------------------
// Revisions :
// Date Version Author Description
// 2013-04-14 1.0 jose.berkenbrock Created
//-----------------------------------------------------------------------------
// Common definitions
`include "defines.v"
// Simulation timescale
`include "timescale.v"
// Wishbone Master
`include "wishbone_test_master.v"
// bpm swap Register definitions
`include "regs/xbpm_swap_regs.vh"
module wb_bpm_swap_tb;
WB_TEST_MASTER WB();
reg [`ADC_DATA_WIDTH-1:0] cha_i, chb_i, chc_i, chd_i;
wire [`ADC_DATA_WIDTH-1:0] cha_o, chb_o, chc_o, chd_o;
wire [7:0] ctrl1_o, ctrl2_o ;
wire clk = WB.wb_clk;
wire rst = WB.wb_rst;
wb_bpm_swap dut(
.rst_n_i (WB.wb_rst),
.clk_sys_i (WB.wb_clk),
.wb_adr_i (WB.wb_addr),
.wb_dat_i (WB.wb_data_o),
.wb_dat_o (WB.wb_data_i),
.wb_cyc_i (WB.wb_cyc),
.wb_sel_i (WB.wb_bwsel),
.wb_stb_i (WB.wb_stb),
.wb_we_i (WB.wb_we),
.wb_ack_o (WB.wb_ack),
.cha_i (cha_i),
.chb_i (chb_i),
.chc_i (chc_i),
.chd_i (chd_i),
.cha_o (cha_o),
.chb_o (chb_o),
.chc_o (chc_o),
.chd_o (chd_o),
.ctrl1_o (ctrl1_o),
.ctrl2_o (ctrl2_o)
);
reg [31:0] ans, ans2, ans3, ans4;
initial begin
// Initial values for ADC data signals
if (`debug) begin
cha_i <= 16'h0001;
chc_i <= 16'h0002;
end else begin
cha_i <= 16'h00ff;
chc_i <= 16'hf00f;
end
chb_i <= 16'hff00;
chd_i <= 16'h0ff0;
if (`debug) begin $display("Debug mode running");
$display("-----------------------------------");
$display("Config. on Debug mode: ");
$display("ch A = 1 and ch C = 2");
$display("AA Gain = 3, CC Gain = 5, AC Gain = 7 and CA Gain = 11");
$display("Swap Freq = 13 KHz, Delay1 = 2 and Delay2 = 8");
$display("-----------------------------------");
$display("Otherwise, all of them are loaded as unitary value");
$display("-----------------------------------");
end else begin $display("Normal running"); end
wait (WB.ready)
@(posedge clk);
$display("-----------------------------------");
$display("@%0d: Inicialization Begin", $time);
$display("-----------------------------------");
////////////////////////
// Set delay values between cross and uncross actions
#1 $display("Set delay 2");
if (`debug) begin WB.write32(`ADDR_BPM_SWAP_CTRL +(4),(16'h0008 << `BPM_SWAP_DLY_2_OFFSET));
//WB.read32(`ADDR_BPM_SWAP_CTRL <<4, ans);
//WB.write32(`ADDR_BPM_SWAP_CTRL <<4,(~`BPM_SWAP_DLY_2&ans)|(16'h0008 << `BPM_SWAP_DLY_2_OFFSET));
end else begin WB.write32(`ADDR_BPM_SWAP_CTRL +(4),(16'h0001 << `BPM_SWAP_DLY_2_OFFSET)); end
#1 $display("Set delay 1");
//WB.write32(`ADDR_BPM_SWAP_CTRL <<4,(16'h0002 << `BPM_SWAP_DLY_1_OFFSET));
WB.read32(`ADDR_BPM_SWAP_CTRL +(4), ans);
if (`debug) begin WB.write32(`ADDR_BPM_SWAP_CTRL +(4),(~`BPM_SWAP_DLY_1&ans)|(16'h0002 << `BPM_SWAP_DLY_1_OFFSET));
end else begin WB.write32(`ADDR_BPM_SWAP_CTRL +(4),(~`BPM_SWAP_DLY_1&ans)|(16'h0001 << `BPM_SWAP_DLY_1_OFFSET)); end
////////////////////////
// Set swap frequency
#1 $display("Set swap frequency");
if (`debug) begin WB.write32(`ADDR_BPM_SWAP_CTRL,(16'h1e0a << `BPM_SWAP_CTRL_SWAP_DIV_F_OFFSET));
//WB.read32(`ADDR_BPM_SWAP_CTRL, ans);
//WB.write32(`ADDR_BPM_SWAP_CTRL,(~`BPM_SWAP_CTRL_SWAP_DIV_F&ans)|(16'h00ff << `BPM_SWAP_CTRL_SWAP_DIV_F_OFFSET));
end else begin WB.write32(`ADDR_BPM_SWAP_CTRL,(16'h0001 << `BPM_SWAP_CTRL_SWAP_DIV_F_OFFSET)); end
////////////////////////
// Set gain channels compensation
#1 $display("Set constant AA");
if (`debug) begin WB.write32(`ADDR_BPM_SWAP_CTRL+(8),(10'h003 << `BPM_SWAP_A_A_OFFSET));
//WB.read32(`ADDR_BPM_SWAP_CTRL<<8, ans);
//WB.write32(`ADDR_BPM_SWAP_CTRL<<8,(~`BPM_SWAP_A_A&ans)|(10'h001 << `BPM_SWAP_A_A_OFFSET));
end else begin WB.write32(`ADDR_BPM_SWAP_CTRL+(8),(10'h001 << `BPM_SWAP_A_A_OFFSET)); end
#1 $display("Set constant BB");
WB.write32(`ADDR_BPM_SWAP_CTRL+'hc,(10'h001 << `BPM_SWAP_B_B_OFFSET));
//WB.read32(`ADDR_BPM_SWAP_CTRL<<'hc, ans);
//WB.write32(`ADDR_BPM_SWAP_CTRL<<'hc,(~`BPM_SWAP_B_B&ans)|(10'h001 << `BPM_SWAP_B_B_OFFSET));
#1 $display("Set constant CC");
if (`debug) begin WB.write32(`ADDR_BPM_SWAP_CTRL+'h10,(10'h005 << `BPM_SWAP_C_C_OFFSET));
//WB.read32(`ADDR_BPM_SWAP_CTRL<<'h10, ans);
//WB.write32(`ADDR_BPM_SWAP_CTRL<<'h10,(~`BPM_SWAP_C_C&ans)|(10'h001 << `BPM_SWAP_C_C_OFFSET));
end else begin WB.write32(`ADDR_BPM_SWAP_CTRL+'h10,(10'h001 << `BPM_SWAP_C_C_OFFSET)); end
#1 $display("Set constant DD");
WB.write32(`ADDR_BPM_SWAP_CTRL+'h14,(10'h001 << `BPM_SWAP_D_D_OFFSET));
//WB.read32(`ADDR_BPM_SWAP_CTRL<<'h14, ans);
//WB.write32(`ADDR_BPM_SWAP_CTRL<<'h14,(~`BPM_SWAP_D_D&ans)|(10'h001 << `BPM_SWAP_D_D_OFFSET));
#1 $display("Set constant AC");
//WB.write32(`ADDR_BPM_SWAP_CTRL+'h8,(10'h001 << `BPM_SWAP_A_C_OFFSET));
WB.read32(`ADDR_BPM_SWAP_CTRL+'h8, ans);
if (`debug) begin WB.write32(`ADDR_BPM_SWAP_CTRL+'h8,(~`BPM_SWAP_A_C&ans)|(10'h007 << `BPM_SWAP_A_C_OFFSET));
end else begin WB.write32(`ADDR_BPM_SWAP_CTRL+'h8,(~`BPM_SWAP_A_C&ans)|(10'h001 << `BPM_SWAP_A_C_OFFSET)); end
#1 $display("Set constant BD");
//WB.write32(`ADDR_BPM_SWAP_CTRL+'hc,(10'h001 << `BPM_SWAP_B_D_OFFSET));
WB.read32(`ADDR_BPM_SWAP_CTRL+'hc, ans);
WB.write32(`ADDR_BPM_SWAP_CTRL+'hc,(~`BPM_SWAP_B_D&ans)|(10'h001 << `BPM_SWAP_B_D_OFFSET));
#1 $display("Set constant CA");
//WB.write32(`ADDR_BPM_SWAP_CTRL+'h10,(10'h001 << `BPM_SWAP_C_A_OFFSET));
WB.read32(`ADDR_BPM_SWAP_CTRL+'h10, ans);
if (`debug) begin WB.write32(`ADDR_BPM_SWAP_CTRL+'h10,(~`BPM_SWAP_C_A&ans)|(10'h00b << `BPM_SWAP_C_A_OFFSET));
end else begin WB.write32(`ADDR_BPM_SWAP_CTRL+'h10,(~`BPM_SWAP_C_A&ans)|(10'h001 << `BPM_SWAP_C_A_OFFSET)); end
#1 $display("Set constant DB");
//WB.write32(`ADDR_BPM_SWAP_CTRL+'h14,(10'h001 << `BPM_SWAP_D_B_OFFSET));
WB.read32(`ADDR_BPM_SWAP_CTRL+'h14, ans);
WB.write32(`ADDR_BPM_SWAP_CTRL+'h14,(~`BPM_SWAP_D_B&ans)|(10'h001 << `BPM_SWAP_D_B_OFFSET));
////////////////////////
// Set operation mode of channel pairs
#1 $display("Set mode1 to direct");
WB.read32(`ADDR_BPM_SWAP_CTRL, ans);
//WB.write32(`ADDR_BPM_SWAP_CTRL, (ans&32'hfff9) | 32'h0004); //works, but complicated
//WB.write32(`ADDR_BPM_SWAP_CTRL, (~`BPM_SWAP_CTRL_MODE1&ans)|32'h0004); //works, with mask
WB.write32(`ADDR_BPM_SWAP_CTRL,((~`BPM_SWAP_CTRL_MODE1)&ans)|(2'b01 << `BPM_SWAP_CTRL_MODE1_OFFSET));
//WB.write32(`ADDR_BPM_SWAP_CTRL,(2'b10 << `BPM_SWAP_CTRL_MODE1_OFFSET));
#1 $display("Set mode2 to inverted");
WB.read32(`ADDR_BPM_SWAP_CTRL, ans);
//WB.write32(`ADDR_BPM_SWAP_CTRL, ((ans&32'hffe7) | 32'h0008));
WB.write32(`ADDR_BPM_SWAP_CTRL,(~`BPM_SWAP_CTRL_MODE2&ans)|(2'b10 << `BPM_SWAP_CTRL_MODE2_OFFSET));
//WB.write32(`ADDR_BPM_SWAP_CTRL,(2'b11 << `BPM_SWAP_CTRL_MODE2_OFFSET));
$display("-------------------------------------");
$display("@%0d: Inicialization Done!", $time);
$display("-------------------------------------");
////////////////////////
// reading registers
#1; // wait
WB.read32(`ADDR_BPM_SWAP_CTRL, ans);
$display("Mode1 Response %b (%x) and mode2 is %b", ans[2:1], ans[2:1], ans[4:3]);
$display("\t&");
$display("Swap Div Freq Response %b (%x)", ans[23:8], ans[23:8]);
#1; // wait
WB.read32(`ADDR_BPM_SWAP_CTRL+'h8, ans);
$display("Gain AC Response %b (%x)", ans[9:0], ans[9:0]);
#1; // wait
WB.read32(`ADDR_BPM_SWAP_CTRL+'h4, ans);
$display("Delay1 @%.3f ut and Delay2 @%.3f ut", ans[15:0], ans[31:16]);
////////////////////////
// change mode 1 value
#1000 WB.read32(`ADDR_BPM_SWAP_CTRL, ans);
$display("-------------------------------------------------");
$display("Set mode1 to swapping @%.3f KHz", 1000000/(`WB_CLOCK_PERIOD*(ans[23:8]+2)));
$display("-------------------------------------------------");
WB.write32(`ADDR_BPM_SWAP_CTRL,((~`BPM_SWAP_CTRL_MODE1)&ans)|(2'b11 << `BPM_SWAP_CTRL_MODE1_OFFSET));
#1 $display("That's it");
$display("---------------------------------------------");
#1 $finish;
end
endmodule
|
module CPU(
input clkR,
output [15:0] ADDRBUS,
output reg [1:0] CTRLBUS,//00 - none //01 - read // 10 - write // 11 - ?
inout [15:0] DATABUS,
output vga, output hsync, output vsync
);
wire clk;
CPUclk clk3(.CLK_IN1(clkR), .CLK_OUT1(clk));
reg reset = 0;
//<bus>
reg [15:0] toWrite;
assign DATABUS = (CTRLBUS == 2'b10) ? toWrite : 16'bz;
assign ADDRBUS = bx;
//</bus>
//<GPU>
reg [15:0] gpuline;
GPU g1(clk, gpuline, 1'b1, vga, hsync, vsync);
//</GPU>
//<reg>
reg [15:0] ax = 0;
reg [15:0] bx = 0;
reg [15:0] cx = 0;
reg [15:0] dx = 0;
reg [15:0] sp = 0;//stackpointer
reg [15:0] bp = 0;//basepointer
reg [15:0] pc = 0;//programcounter
//</reg>
//<flg>
reg cf = 0;//carry
reg zf = 0;//zero
reg of = 0;//overflow
//</flg>
//<stack>
reg [15:0] stack[63:0];
//</stack>
//<RAM>
reg [11:0] ADDR1 = 0;
reg [11:0] ADDR2;
reg [11:0] ADDR3;
reg [11:0] ADDR4;
reg [11:0] ADDW1;
reg [15:0] DATA;
reg WREN = 0;
wire [15:0] DATA1;
wire [15:0] DATA2;
wire [15:0] DATA3;
wire [15:0] DATA4;
reg RAMState = 0;
RAM r(ADDR1, ADDR2, ADDR3, ADDR4, ADDW1, DATA, WREN, DATA1, DATA2, DATA3, DATA4, clk);
//</RAM>
//<op>
parameter oNOP = 16'h0;
//trans
parameter oSCF = 16'h1;
parameter oCFF = 16'h2;
parameter oCOF = 16'h3;
parameter oCZF = 16'h4;
parameter oCBP = 16'h2D;
parameter oCPC = 16'h2E;
parameter oMOV1 = 16'h5;
parameter oMOV2 = 16'h6;
parameter oMOV3 = 16'h7;
parameter oMOV4 = 16'h8;
parameter oMOV5 = 16'h2A;
parameter oMOV6 = 16'h2B;
parameter oLEA1 = 16'h27;
parameter oLEA2 = 16'h2C;
parameter oLEA3 = 16'h2F;
parameter oLEA4 = 16'h30;
parameter oPOP = 16'h9;
parameter oOUT = 16'hA;
parameter oIN = 16'h28;
parameter oXCH = 16'h29;
parameter oPUSH = 16'hB;
//arithm
parameter oADD = 16'hC;
parameter oADC = 16'hD;
parameter oSUB = 16'hE;
parameter oSUC = 16'hF;
parameter oMUL8 = 16'h10;
parameter oDIV8 = 16'h12;
parameter oCMP = 16'h14;
//logic
parameter oAND = 16'h15;
parameter oNEG = 16'h16;
parameter oNOT = 16'h17;
parameter oOR = 16'h18;
parameter oSHL = 16'h19;
parameter oSHR = 16'h1A;
parameter oXOR = 16'h1B;
parameter oTEST = 16'h1C;
//jumps
parameter oINT = 16'h1D;
parameter oCALL = 16'h1E;
parameter oRET = 16'h1F;
parameter oJMP1 = 16'h20;
parameter oJMP2 = 16'h31;
parameter oJMP3 = 16'h32;
parameter oJMP4 = 16'h33;
parameter oJC = 16'h21;
parameter oJNC = 16'h22;
parameter oJZ = 16'h23;
parameter oJNZ = 16'h24;
parameter oJO = 16'h25;
parameter oJNO = 16'h26;
//<alu params>
parameter xADD = 8'h1;
parameter xADC = 8'h2;
parameter xSUB = 8'h3;
parameter xSUC = 8'h4;
parameter xMUL8 = 8'h5;
parameter xDIV8 = 8'h7;
parameter xCMP = 8'h9;
//</alu params>
//</op>
//<ALU>
reg [15:0] ain;
reg [15:0] bin;
reg [7:0] op;
wire c_flag;
wire z_flag;
wire o_flag;
wire [15:0] acc;
wire [15:0] c;
dALU alu0 (
.clk (clk),
.a(ain),
.b(bin),
.op(op),
.cf(cf),
.c_flag(c_flag),
.z_flag(z_flag),
.o_flag(o_flag),
.acc(acc),
.c(c)
);
//</ALU>
//<control>
reg [15:0] opcode = 0;
reg [15:0] par1 = 0;
reg [15:0] par2 = 0;
reg alustate = 0;
reg [8:0] clkint = 0;
//</control>
always @(posedge clk) begin : Main_FSM
CTRLBUS <= 0; //totally fucking unsafe
WREN = 0;
gpuline = 16'h0;
opcode = DATA1;
par1 = DATA2;
par2 = DATA3;
case (opcode)
oNOP: begin pc = pc + 1; end
oSCF: begin
cf <= par1;
pc = pc + 2;
end
oCFF: begin
dx <= cf;
pc = pc + 1;
end
oCOF: begin
dx <= of;
pc = pc + 1;
end
oCZF: begin
dx <= zf;
pc = pc + 1;
end
oCBP: begin
dx <= bp;
pc = pc + 1;
end
oCPC: begin
dx <= pc;
pc = pc + 1;
end
oMOV1: begin //[adr],xx [adr]<=xx //relative address
ADDW1 = par1+bp;
case (par2[1:0]) //00-ax 01-bx 10-cx 11-dx
2'b00: DATA = ax;
2'b01: DATA = bx;
2'b10: DATA = cx;
2'b11: DATA = dx;
endcase
WREN = 1;
pc = pc + 3;
end
oMOV2: begin //xx,[adr] xx<=[adr] //relative address
case (RAMState)
1'b0: begin
ADDR4 = par2+bp;
RAMState <= 1;
end
1'b1: begin
case (par1[1:0]) //00-ax 01-bx 10-cx 11-dx
2'b00: ax <= DATA4;
2'b01: bx <= DATA4;
2'b10: cx <= DATA4;
2'b11: dx <= DATA4;
endcase
pc = pc + 3;
RAMState <= 0;
end
endcase
end
oMOV5: begin //<adr>,xx <adr><=xx //absolute address
ADDW1 = par1;
case (par2[1:0]) //00-ax 01-bx 10-cx 11-dx
2'b00: DATA = ax;
2'b01: DATA = bx;
2'b10: DATA = cx;
2'b11: DATA = dx;
endcase
WREN = 1;
pc = pc + 3;
end
oMOV6: begin //xx,<adr> xx<=<adr> //absolute address
case (RAMState)
1'b0: begin
ADDR4 = par2;
RAMState <= 1;
end
1'b1: begin
case (par1[1:0]) //00-ax 01-bx 10-cx 11-dx
2'b00: ax <= DATA4;
2'b01: bx <= DATA4;
2'b10: cx <= DATA4;
2'b11: dx <= DATA4;
endcase
pc = pc + 3;
RAMState <= 0;
end
endcase
end
oMOV3: begin //xx,yx xx<=yx
case (par1[3:0])//00-ax 01-bx 10-cx 11-dx
4'b0001: ax <= bx;
4'b0010: ax <= cx;
4'b0011: ax <= dx;
4'b0100: bx <= ax;
4'b0110: bx <= cx;
4'b0111: bx <= dx;
4'b1000: cx <= ax;
4'b1001: cx <= bx;
4'b1011: cx <= dx;
4'b1100: dx <= ax;
4'b1101: dx <= bx;
4'b1110: dx <= cx;
endcase
pc = pc + 2;
end
oMOV4: begin //xx,(int) xx<=(int)
case (par1[1:0])//00-ax 01-bx 10-cx 11-dx
2'b00: ax <= par2;
2'b01: bx <= par2;
2'b10: cx <= par2;
2'b11: dx <= par2;
endcase
pc = pc + 3;
end
oLEA1: begin //xx,[yy] xx<=[yx]
case (RAMState)
1'b0: begin
case (par1[1:0])
2'b00: ADDR4 = ax+bp;
2'b01: ADDR4 = bx+bp;
2'b10: ADDR4 = cx+bp;
2'b11: ADDR4 = dx+bp;
endcase
RAMState <= 1;
end
1'b1: begin
case (par1[3:2])//00-ax 01-bx 10-cx 11-dx
2'b00: ax <= DATA4;
2'b01: bx <= DATA4;
2'b10: cx <= DATA4;
2'b11: dx <= DATA4;
endcase
pc = pc + 2;
RAMState <= 0;
end
endcase
end
oLEA2: begin //[xx],yy [xx]<=yy
case (par1[3:0])//00-ax 01-bx 10-cx 11-dx//@TODO: two-step
4'b0001: begin ADDW1 = ax+bp; DATA = bx; end
4'b0010: begin ADDW1 = ax+bp; DATA = cx; end
4'b0011: begin ADDW1 = ax+bp; DATA = dx; end
4'b0100: begin ADDW1 = bx+bp; DATA = ax; end
4'b0110: begin ADDW1 = bx+bp; DATA = cx; end
4'b0111: begin ADDW1 = bx+bp; DATA = dx; end
4'b1000: begin ADDW1 = cx+bp; DATA = ax; end
4'b1001: begin ADDW1 = cx+bp; DATA = bx; end
4'b1011: begin ADDW1 = cx+bp; DATA = dx; end
4'b1100: begin ADDW1 = dx+bp; DATA = ax; end
4'b1101: begin ADDW1 = dx+bp; DATA = bx; end
4'b1110: begin ADDW1 = dx+bp; DATA = cx; end
endcase
WREN = 1;
pc = pc + 2;
end
oLEA3: begin //xx,<yy> xx<=<yx>
case (RAMState)
1'b0: begin
case (par1[1:0])
2'b00: ADDR4 = ax;
2'b01: ADDR4 = bx;
2'b10: ADDR4 = cx;
2'b11: ADDR4 = dx;
endcase
RAMState <= 1;
end
1'b1: begin
case (par1[3:2])//00-ax 01-bx 10-cx 11-dx
2'b00: ax <= DATA4;
2'b01: bx <= DATA4;
2'b10: cx <= DATA4;
2'b11: dx <= DATA4;
endcase
pc = pc + 2;
RAMState <= 0;
end
endcase
end
oLEA4: begin //<xx>,yy <xx><=yy
case (par1[3:0])//00-ax 01-bx 10-cx 11-dx //ABS //@TODO: two-step
4'b0001: begin ADDW1 = ax; DATA = bx; end
4'b0010: begin ADDW1 = ax; DATA = cx; end
4'b0011: begin ADDW1 = ax; DATA = dx; end
4'b0100: begin ADDW1 = bx; DATA = ax; end
4'b0110: begin ADDW1 = bx; DATA = cx; end
4'b0111: begin ADDW1 = bx; DATA = dx; end
4'b1000: begin ADDW1 = cx; DATA = ax; end
4'b1001: begin ADDW1 = cx; DATA = bx; end
4'b1011: begin ADDW1 = cx; DATA = dx; end
4'b1100: begin ADDW1 = dx; DATA = ax; end
4'b1101: begin ADDW1 = dx; DATA = bx; end
4'b1110: begin ADDW1 = dx; DATA = cx; end
endcase
WREN = 1;
pc = pc + 2;
end
oPOP: begin
case (par1[1:0])//00-ax 01-bx 10-cx 11-dx
2'b00: ax <= stack[sp-1];
2'b01: bx <= stack[sp-1];
2'b10: cx <= stack[sp-1];
2'b11: dx <= stack[sp-1];
endcase
sp <= sp - 1;
pc = pc + 2;
end
oOUT: begin
toWrite <= dx;
CTRLBUS <= 2'b10;
pc = pc + 1;
$display("Address: %b, Data: %b", bx, dx);
end
oIN: begin
case (RAMState)
1'b0: begin
CTRLBUS <= 2'b01;
RAMState <= 1;
end
1'b1: begin
CTRLBUS <= 2'b00;
dx <= DATABUS;
pc = pc + 1;
RAMState <= 0;
end
endcase
end
oXCH: begin
case (par1[3:0])//00-ax 01-bx 10-cx 11-dx
4'b0001: begin ax <= bx; bx <= ax; end
4'b0010: begin ax <= cx; cx <= ax; end
4'b0011: begin ax <= dx; dx <= ax; end
4'b0100: begin bx <= ax; ax <= bx; end
4'b0110: begin bx <= cx; cx <= bx; end
4'b0111: begin bx <= dx; dx <= bx; end
4'b1000: begin cx <= ax; ax <= cx; end
4'b1001: begin cx <= bx; bx <= cx; end
4'b1011: begin cx <= dx; dx <= cx; end
4'b1100: begin dx <= ax; ax <= dx; end
4'b1101: begin dx <= bx; bx <= dx; end
4'b1110: begin dx <= cx; cx <= dx; end
endcase
pc = pc + 2;
end
oPUSH: begin
case (par1[1:0])//00-ax 01-bx 10-cx 11-dx
2'b00: stack[sp] <= ax;
2'b01: stack[sp] <= bx;
2'b10: stack[sp] <= cx;
2'b11: stack[sp] <= dx;
endcase
sp <= sp + 1;
pc = pc + 2;
end
oADD: begin
case (alustate) //0- not initiated 1-waiting
1'b0: begin
case (par1[3:2])//00-ax 01-bx 10-cx 11-dx
2'b00: ain = ax;
2'b01: ain = bx;
2'b10: ain = cx;
2'b11: ain = dx;
endcase
case (par1[1:0])//00-ax 01-bx 10-cx 11-dx
2'b00: bin = ax;
2'b01: bin = bx;
2'b10: bin = cx;
2'b11: bin = dx;
endcase
op = xADD;
alustate <= 1;
end
1'b1: begin
case (par1[3:2])//00-ax 01-bx 10-cx 11-dx
2'b00: ax <= acc;
2'b01: bx <= acc;
2'b10: cx <= acc;
2'b11: dx <= acc;
endcase
pc = pc + 2;
cf <= c_flag;
zf <= z_flag;
of <= o_flag;
alustate <= 0;
end
endcase
end
oADC: begin
case (alustate) //0- not initiated 1-waiting
1'b0: begin
case (par1[3:2])//00-ax 01-bx 10-cx 11-dx
2'b00: ain = ax;
2'b01: ain = bx;
2'b10: ain = cx;
2'b11: ain = dx;
endcase
case (par1[1:0])//00-ax 01-bx 10-cx 11-dx
2'b00: bin = ax;
2'b01: bin = bx;
2'b10: bin = cx;
2'b11: bin = dx;
endcase
op = xADC;
alustate <= 1;
end
1'b1: begin
case (par1[3:2])//00-ax 01-bx 10-cx 11-dx
2'b00: ax <= acc;
2'b01: bx <= acc;
2'b10: cx <= acc;
2'b11: dx <= acc;
endcase
pc = pc + 2;
cf <= c_flag;
zf <= z_flag;
of <= o_flag;
alustate <= 0;
end
endcase
end
oSUB: begin
case (alustate) //0- not initiated 1-waiting
1'b0: begin
case (par1[3:2])//00-ax 01-bx 10-cx 11-dx
2'b00: ain = ax;
2'b01: ain = bx;
2'b10: ain = cx;
2'b11: ain = dx;
endcase
case (par1[1:0])//00-ax 01-bx 10-cx 11-dx
2'b00: bin = ax;
2'b01: bin = bx;
2'b10: bin = cx;
2'b11: bin = dx;
endcase
op = xSUB;
alustate <= 1;
end
1'b1: begin
case (par1[3:2])//00-ax 01-bx 10-cx 11-dx
2'b00: ax <= acc;
2'b01: bx <= acc;
2'b10: cx <= acc;
2'b11: dx <= acc;
endcase
pc = pc + 2;
cf <= c_flag;
zf <= z_flag;
of <= o_flag;
alustate <= 0;
end
endcase
end
oSUC: begin
case (alustate) //0- not initiated 1-waiting
1'b0: begin
case (par1[3:2])//00-ax 01-bx 10-cx 11-dx
2'b00: ain = ax;
2'b01: ain = bx;
2'b10: ain = cx;
2'b11: ain = dx;
endcase
case (par1[1:0])//00-ax 01-bx 10-cx 11-dx
2'b00: bin = ax;
2'b01: bin = bx;
2'b10: bin = cx;
2'b11: bin = dx;
endcase
op = xSUC;
alustate <= 1;
end
1'b1: begin
case (par1[3:2])//00-ax 01-bx 10-cx 11-dx
2'b00: ax <= acc;
2'b01: bx <= acc;
2'b10: cx <= acc;
2'b11: dx <= acc;
endcase
pc = pc + 2;
cf <= c_flag;
zf <= z_flag;
of <= o_flag;
alustate <= 0;
end
endcase
end
oMUL8: begin
case (alustate) //0- not initiated 1-waiting
1'b0: begin
case (par1[3:2])//00-ax 01-bx 10-cx 11-dx
2'b00: ain = ax;
2'b01: ain = bx;
2'b10: ain = cx;
2'b11: ain = dx;
endcase
case (par1[1:0])//00-ax 01-bx 10-cx 11-dx
2'b00: bin = ax;
2'b01: bin = bx;
2'b10: bin = cx;
2'b11: bin = dx;
endcase
op = xMUL8;
alustate <= 1;
end
1'b1: begin
case (par1[3:2])//00-ax 01-bx 10-cx 11-dx
2'b00: ax <= acc;
2'b01: bx <= acc;
2'b10: cx <= acc;
2'b11: dx <= acc;
endcase
pc = pc + 2;
zf <= z_flag;
alustate <= 0;
end
endcase
end
oDIV8: begin
case (alustate) //0- not initiated 1-waiting
1'b0: begin
case (par1[3:2])//00-ax 01-bx 10-cx 11-dx
2'b00: ain = ax;
2'b01: ain = bx;
2'b10: ain = cx;
2'b11: ain = dx;
endcase
case (par1[1:0])//00-ax 01-bx 10-cx 11-dx
2'b00: bin = ax;
2'b01: bin = bx;
2'b10: bin = cx;
2'b11: bin = dx;
endcase
op = xDIV8;
alustate <= 1;
end
1'b1: begin
case (par1[3:2])//00-ax 01-bx 10-cx 11-dx
2'b00: ax <= acc;
2'b01: bx <= acc;
2'b10: cx <= acc;
2'b11: dx <= acc;
endcase
pc = pc + 2;
zf <= z_flag;
alustate <= 0;
end
endcase
end
oCMP: begin
case (alustate) //0- not initiated 1-waiting
1'b0: begin
case (par1[3:2])//00-ax 01-bx 10-cx 11-dx
2'b00: ain = ax;
2'b01: ain = bx;
2'b10: ain = cx;
2'b11: ain = dx;
endcase
case (par1[1:0])//00-ax 01-bx 10-cx 11-dx
2'b00: bin = ax;
2'b01: bin = bx;
2'b10: bin = cx;
2'b11: bin = dx;
endcase
op = xCMP;
alustate <= 1;
end
1'b1: begin
pc = pc + 2;
cf <= c_flag;
zf <= z_flag;
of <= o_flag;
alustate <= 0;
end
endcase
end
oAND: begin //xx,yx xx <= xx&&yx
case (par1[3:0])//00-ax 01-bx 10-cx 11-dx
4'b0001: ax <= (ax & bx);
4'b0010: ax <= (ax & cx);
4'b0011: ax <= (ax & dx);
4'b0100: bx <= (bx & ax);
4'b0110: bx <= (bx & cx);
4'b0111: bx <= (bx & dx);
4'b1000: cx <= (cx & ax);
4'b1001: cx <= (cx & bx);
4'b1011: cx <= (cx & dx);
4'b1100: dx <= (dx & ax);
4'b1101: dx <= (dx & bx);
4'b1110: dx <= (dx & cx);
endcase
pc = pc + 2;
end
oNEG: begin //xx xx <= ~xx
case (par1[1:0])//00-ax 01-bx 10-cx 11-dx
2'b00: ax <= ~ax;
2'b01: bx <= ~bx;
2'b10: cx <= ~cx;
2'b11: dx <= ~dx;
endcase
pc = pc + 2;
end
oNOT: begin //xx xx <= !xx
case (par1[1:0])//00-ax 01-bx 10-cx 11-dx
2'b00: ax <= !ax;
2'b01: bx <= !bx;
2'b10: cx <= !cx;
2'b11: dx <= !dx;
endcase
pc = pc + 2;
end
oOR: begin //xx,yx xx <= xx||yx
case (par1[3:0])//00-ax 01-bx 10-cx 11-dx
4'b0001: ax <= (ax | bx);
4'b0010: ax <= (ax | cx);
4'b0011: ax <= (ax | dx);
4'b0100: bx <= (bx | ax);
4'b0110: bx <= (bx | cx);
4'b0111: bx <= (bx | dx);
4'b1000: cx <= (cx | ax);
4'b1001: cx <= (cx | bx);
4'b1011: cx <= (cx | dx);
4'b1100: dx <= (dx | ax);
4'b1101: dx <= (dx | bx);
4'b1110: dx <= (dx | cx);
endcase
pc = pc + 2;
end
oSHL: begin //xx xx <= xx << 1
case (par1[1:0])//00-ax 01-bx 10-cx 11-dx
2'b00: ax <= ax << 1;
2'b01: bx <= bx << 1;
2'b10: cx <= cx << 1;
2'b11: dx <= dx << 1;
endcase
pc = pc + 2;
end
oSHR: begin //xx xx <= xx >> 1
case (par1[1:0])//00-ax 01-bx 10-cx 11-dx
2'b00: ax <= ax >> 1;
2'b01: bx <= bx >> 1;
2'b10: cx <= cx >> 1;
2'b11: dx <= dx >> 1;
endcase
pc = pc + 2;
end
oXOR: begin //xx,yx xx <= xx^yx
case (par1[3:0])//00-ax 01-bx 10-cx 11-dx
4'b0001: ax <= (ax ^ bx);
4'b0010: ax <= (ax ^ cx);
4'b0011: ax <= (ax ^ dx);
4'b0100: bx <= (bx ^ ax);
4'b0110: bx <= (bx ^ cx);
4'b0111: bx <= (bx ^ dx);
4'b1000: cx <= (cx ^ ax);
4'b1001: cx <= (cx ^ bx);
4'b1011: cx <= (cx ^ dx);
4'b1100: dx <= (dx ^ ax);
4'b1101: dx <= (dx ^ bx);
4'b1110: dx <= (dx ^ cx);
endcase
pc = pc + 2;
end
oTEST: begin //xx,yx xx ?= yx
case (par1[3:0])//00-ax 01-bx 10-cx 11-dx
4'b0001: zf <= (ax == bx);
4'b0010: zf <= (ax == cx);
4'b0011: zf <= (ax == dx);
4'b0100: zf <= (ax == bx);
4'b0110: zf <= (cx == bx);
4'b0111: zf <= (dx == bx);
4'b1000: zf <= (ax == cx);
4'b1001: zf <= (cx == bx);
4'b1011: zf <= (cx == dx);
4'b1100: zf <= (ax == dx);
4'b1101: zf <= (dx == bx);
4'b1110: zf <= (dx == cx);
endcase
pc = pc + 2;
end
oINT: begin//absolute address
stack[sp] <= bp;
stack[sp+1] <= pc;
sp <= sp + 2;
bp <= par1;
pc = par1;
end
oCALL: begin//relative address
stack[sp] <= bp;
stack[sp+1] <= pc;
sp <= sp + 2;
pc = par1 + bp;
bp <= par1;
end
oRET: begin
pc = stack[sp-1];
bp <= stack[sp-2];
sp <= sp - 2;
end
oJMP1: begin
pc = par1 + bp;
end
oJMP2: begin
pc = par1;
end
oJMP3: begin
case (par1[1:0])//00-ax 01-bx 10-cx 11-dx
2'b00: pc = ax + bp;
2'b01: pc = bx + bp;
2'b10: pc = cx + bp;
2'b11: pc = dx + bp;
endcase
end
oJMP4: begin
case (par1[1:0])//00-ax 01-bx 10-cx 11-dx
2'b00: pc = ax;
2'b01: pc = bx;
2'b10: pc = cx;
2'b11: pc = dx;
endcase
end
oJC: begin
if (cf) pc = par1 + bp;
else pc = pc + 2;
end
oJNC: begin
if (!cf) pc = par1 + bp;
else pc = pc + 2;
end
oJZ: begin
if (zf) pc = par1 + bp;
else pc = pc + 2;
end
oJNZ: begin
if (!zf) pc = par1 + bp;
else pc = pc + 2;
end
oJO: begin
if (of) pc = par1 + bp;
else pc = pc + 2;
end
oJNO: begin
if (!of) pc = par1 + bp;
else pc = pc + 2;
end
16'hBF: begin //putchar from mem
if (!alustate) begin
gpuline = opcode;
ADDR4 = par2+bp;
alustate <= 1;
end
else begin
pc = pc + 2;
//gpuline <= ram[par1 + bp];
gpuline = DATA4;
alustate <= 0;
end
end
default: begin//unrecognized cmd//maybe gpu
if (!alustate) begin
gpuline = opcode;
alustate <= 1;
end
else begin
pc = pc + 2;
gpuline = par1;
alustate <= 0;
end
end
endcase
if(clkint > 1000 && !alustate && !RAMState) begin
clkint <= 0;
//GENERATE INTERRUPT
stack[sp] <= bp;
stack[sp+1] <= pc;
sp <= sp + 2;
bp <= 100;
pc = 100; //HARDCODED CLK INTERRUPT ADDRESS
end else begin
clkint <= clkint + 1;
end
ADDR1 = pc;
ADDR2 = pc + 1;
ADDR3 = pc + 2;
end
endmodule |
`ifdef cyclonev
`define LCELL cyclonev_lcell_comb
`define MAC cyclonev_mac
`define MLAB cyclonev_mlab_cell
`endif
`ifdef cyclone10gx
`define LCELL cyclone10gx_lcell_comb
`define MAC cyclone10gx_mac
`define MLAB cyclone10gx_mlab_cell
`endif
module __MISTRAL_VCC(output Q);
MISTRAL_ALUT2 #(.LUT(4'b1111)) _TECHMAP_REPLACE_ (.A(1'b1), .B(1'b1), .Q(Q));
endmodule
module __MISTRAL_GND(output Q);
MISTRAL_ALUT2 #(.LUT(4'b0000)) _TECHMAP_REPLACE_ (.A(1'b1), .B(1'b1), .Q(Q));
endmodule
module MISTRAL_FF(input DATAIN, CLK, ACLR, ENA, SCLR, SLOAD, SDATA, output reg Q);
dffeas #(.power_up("low"), .is_wysiwyg("true")) _TECHMAP_REPLACE_ (.d(DATAIN), .clk(CLK), .clrn(ACLR), .ena(ENA), .sclr(SCLR), .sload(SLOAD), .asdata(SDATA), .q(Q));
endmodule
module MISTRAL_ALUT6(input A, B, C, D, E, F, output Q);
parameter [63:0] LUT = 64'h0000_0000_0000_0000;
`LCELL #(.lut_mask(LUT)) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .datae(E), .dataf(F), .combout(Q));
endmodule
module MISTRAL_ALUT5(input A, B, C, D, E, output Q);
parameter [31:0] LUT = 32'h0000_0000;
`LCELL #(.lut_mask({2{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .datae(E), .combout(Q));
endmodule
module MISTRAL_ALUT4(input A, B, C, D, output Q);
parameter [15:0] LUT = 16'h0000;
`LCELL #(.lut_mask({4{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .combout(Q));
endmodule
module MISTRAL_ALUT3(input A, B, C, output Q);
parameter [7:0] LUT = 8'h00;
`LCELL #(.lut_mask({8{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .combout(Q));
endmodule
module MISTRAL_ALUT2(input A, B, output Q);
parameter [3:0] LUT = 4'h0;
`LCELL #(.lut_mask({16{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .combout(Q));
endmodule
module MISTRAL_NOT(input A, output Q);
NOT _TECHMAP_REPLACE_ (.IN(A), .OUT(Q));
endmodule
module MISTRAL_ALUT_ARITH(input A, B, C, D0, D1, CI, output SO, CO);
parameter LUT0 = 16'h0000;
parameter LUT1 = 16'h0000;
`LCELL #(.lut_mask({16'h0, LUT1, 16'h0, LUT0})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D0), .dataf(D1), .cin(CI), .sumout(SO), .cout(CO));
endmodule
module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1ADDR, output B1DATA);
parameter _TECHMAP_CELLNAME_ = "";
// Here we get to an unfortunate situation. The cell has a mem_init0 parameter,
// which takes in a hexadecimal string that could be used to initialise RAM.
// In the vendor simulation models, this appears to work fine, but Quartus,
// either intentionally or not, forgets about this parameter and initialises the
// RAM to zero.
//
// Because of this, RAM initialisation is presently disabled, but the source
// used to generate mem_init0 is kept (commented out) in case this gets fixed
// or an undocumented way to get Quartus to initialise from mem_init0 is found.
`MLAB #(
.logical_ram_name(_TECHMAP_CELLNAME_),
.logical_ram_depth(32),
.logical_ram_width(1),
.mixed_port_feed_through_mode("Dont Care"),
.first_bit_number(0),
.first_address(0),
.last_address(31),
.address_width(5),
.data_width(1),
.byte_enable_mask_width(1),
.port_b_data_out_clock("NONE"),
// .mem_init0($sformatf("%08x", INIT))
) _TECHMAP_REPLACE_ (
.portaaddr(A1ADDR),
.portadatain(A1DATA),
.portbaddr(B1ADDR),
.portbdataout(B1DATA),
.ena0(A1EN),
.clk0(CLK1)
);
endmodule
module MISTRAL_M10K(A1ADDR, A1DATA, A1EN, CLK1, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 10;
parameter CFG_DBITS = 10;
parameter _TECHMAP_CELLNAME_ = "";
input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
input [CFG_DBITS-1:0] A1DATA;
input CLK1, A1EN, B1EN;
output [CFG_DBITS-1:0] B1DATA;
// Much like the MLAB, the M10K has mem_init[01234] parameters which would let
// you initialise the RAM cell via hex literals. If they were implemented.
cyclonev_ram_block #(
.operation_mode("dual_port"),
.logical_ram_name(_TECHMAP_CELLNAME_),
.port_a_address_width(CFG_ABITS),
.port_a_data_width(CFG_DBITS),
.port_a_logical_ram_depth(2**CFG_ABITS),
.port_a_logical_ram_width(CFG_DBITS),
.port_a_first_address(0),
.port_a_last_address(2**CFG_ABITS - 1),
.port_a_first_bit_number(0),
.port_b_address_width(CFG_ABITS),
.port_b_data_width(CFG_DBITS),
.port_b_logical_ram_depth(2**CFG_ABITS),
.port_b_logical_ram_width(CFG_DBITS),
.port_b_first_address(0),
.port_b_last_address(2**CFG_ABITS - 1),
.port_b_first_bit_number(0),
.port_b_address_clock("clock0"),
.port_b_read_enable_clock("clock0")
) _TECHMAP_REPLACE_ (
.portaaddr(A1ADDR),
.portadatain(A1DATA),
.portawe(A1EN),
.portbaddr(B1ADDR),
.portbdataout(B1DATA),
.portbre(B1EN),
.clk0(CLK1)
);
endmodule
module MISTRAL_MUL27X27(input [26:0] A, B, output [53:0] Y);
parameter A_SIGNED = 1;
parameter B_SIGNED = 1;
`MAC #(
.ax_width(27),
.signed_max(A_SIGNED ? "true" : "false"),
.ay_scan_in_width(27),
.signed_may(B_SIGNED ? "true" : "false"),
.result_a_width(54),
.operation_mode("M27x27")
) _TECHMAP_REPLACE_ (
.ax(A),
.ay(B),
.resulta(Y)
);
endmodule
module MISTRAL_MUL18X18(input [17:0] A, B, output [35:0] Y);
parameter A_SIGNED = 1;
parameter B_SIGNED = 1;
`MAC #(
.ax_width(18),
.signed_max(A_SIGNED ? "true" : "false"),
.ay_scan_in_width(18),
.signed_may(B_SIGNED ? "true" : "false"),
.result_a_width(36),
.operation_mode("M18x18_FULL")
) _TECHMAP_REPLACE_ (
.ax(A),
.ay(B),
.resulta(Y)
);
endmodule
module MISTRAL_MUL9X9(input [8:0] A, B, output [17:0] Y);
parameter A_SIGNED = 1;
parameter B_SIGNED = 1;
`MAC #(
.ax_width(9),
.signed_max(A_SIGNED ? "true" : "false"),
.ay_scan_in_width(9),
.signed_may(B_SIGNED ? "true" : "false"),
.result_a_width(18),
.operation_mode("M9x9")
) _TECHMAP_REPLACE_ (
.ax(A),
.ay(B),
.resulta(Y)
);
endmodule
|
/*
* regm - register memory
*
* A 32-bit register memory. Two registers can be read at once. The
* variables `read1` and `read2` specifiy which registers to read. The
* output is placed in `data1` and `data2`.
*
* If `regwrite` is high, the value in `wrdata` will be written to the
* register in `wrreg`.
*
* The register at address $zero is treated special, it ignores
* assignment and the value read is always zero.
*
* If the register being read is the same as that being written, the
* value being written will be available immediately without a one
* cycle delay.
*
*/
`ifndef _regm
`define _regm
`ifndef DEBUG_CPU_REG
`define DEBUG_CPU_REG 0
`endif
module regm(
input wire clk,
input wire [4:0] read1, read2,
output wire [31:0] data1, data2,
input wire regwrite,
input wire [4:0] wrreg,
input wire [31:0] wrdata);
reg [31:0] mem [0:31]; // 32-bit memory with 32 entries
reg [31:0] _data1, _data2;
initial begin
if (`DEBUG_CPU_REG) begin
$display(" $v0, $v1, $t0, $t1, $t2, $t3, $t4, $t5, $t6, $t7");
$monitor("%x, %x, %x, %x, %x, %x, %x, %x, %x, %x",
mem[2][31:0], /* $v0 */
mem[3][31:0], /* $v1 */
mem[8][31:0], /* $t0 */
mem[9][31:0], /* $t1 */
mem[10][31:0], /* $t2 */
mem[11][31:0], /* $t3 */
mem[12][31:0], /* $t4 */
mem[13][31:0], /* $t5 */
mem[14][31:0], /* $t6 */
mem[15][31:0], /* $t7 */
);
end
end
always @(*) begin
if (read1 == 5'd0)
_data1 = 32'd0;
else if ((read1 == wrreg) && regwrite)
_data1 = wrdata;
else
_data1 = mem[read1][31:0];
end
always @(*) begin
if (read2 == 5'd0)
_data2 = 32'd0;
else if ((read2 == wrreg) && regwrite)
_data2 = wrdata;
else
_data2 = mem[read2][31:0];
end
assign data1 = _data1;
assign data2 = _data2;
always @(posedge clk) begin
if (regwrite && wrreg != 5'd0) begin
// write a non $zero register
mem[wrreg] <= wrdata;
end
end
endmodule
`endif
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:11:34 06/01/2015
// Design Name:
// Module Name: mixColumns
// Project Name:
// Target Devices:
// Tool versions:
// Description: MixColumn applied to a single column
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mixColumns(
output [31:0] mixOut, // Data Out
input [31:0] mixIn, // Data In
input clk, // Clock
input inv // Inverse, If 1 do inverse mix columns step.
);
wire [31:0] mixOutInv;
wire [31:0] mixOutNorm;
wire [7:0] s [0:3]; // Input Column
wire [7:0] c [0:3]; // Output Column
wire [7:0] cinv [0:3]; // Inverse Output Column
// Inputs multiplied by 02 and 03.
reg [7:0] s0_2;
reg [7:0] s0_3;
reg [7:0] s1_2;
reg [7:0] s1_3;
reg [7:0] s2_2;
reg [7:0] s2_3;
reg [7:0] s3_2;
reg [7:0] s3_3;
reg [7:0] s0_1;
reg [7:0] s1_1;
reg [7:0] s2_1;
reg [7:0] s3_1;
wire [7:0] s0_9;
wire [7:0] s0_B;
wire [7:0] s0_D;
wire [7:0] s0_E;
wire [7:0] s1_9;
wire [7:0] s1_B;
wire [7:0] s1_D;
wire [7:0] s1_E;
wire [7:0] s2_9;
wire [7:0] s2_B;
wire [7:0] s2_D;
wire [7:0] s2_E;
wire [7:0] s3_9;
wire [7:0] s3_B;
wire [7:0] s3_D;
wire [7:0] s3_E;
// Bind input to bytes,
assign {s[0], s[1], s[2], s[3]} = mixIn;
// Mix Columns multipliers.
// 02 03 01 01
// 01 02 03 01
// 01 01 02 03
// 03 01 01 02
// Bind sx_1, sx_2 and sx_3
// This is to make encyrption and decryption run with the same clock steps.
always @(posedge clk) begin
s0_2 = (s[0] & 8'h80) ? ((s[0] << 1) ^ 8'h1B) : (s[0] << 1);
s1_2 = (s[1] & 8'h80) ? ((s[1] << 1) ^ 8'h1B) : (s[1] << 1);
s2_2 = (s[2] & 8'h80) ? ((s[2] << 1) ^ 8'h1B) : (s[2] << 1);
s3_2 = (s[3] & 8'h80) ? ((s[3] << 1) ^ 8'h1B) : (s[3] << 1);
s0_3 = s0_2 ^ s[0];
s1_3 = s1_2 ^ s[1];
s2_3 = s2_2 ^ s[2];
s3_3 = s3_2 ^ s[3];
s0_1 = s[0];
s1_1 = s[1];
s2_1 = s[2];
s3_1 = s[3];
end
// Do the xor.
assign c[0] = s0_2 ^ s1_3 ^ s2_1 ^ s3_1;
assign c[1] = s0_1 ^ s1_2 ^ s2_3 ^ s3_1;
assign c[2] = s0_1 ^ s1_1 ^ s2_2 ^ s3_3;
assign c[3] = s0_3 ^ s1_1 ^ s2_1 ^ s3_2;
// Inverse Mix Columns Multipliers
// 0E 0B 0D 09
// 09 0E 0B 0D
// 0D 09 0E 0B
// 0B 0D 09 0E
// S0
mixcolumns9b mix1(.dout({s0_9,s0_B}), .add(s[0]), .clock(clk), .en(1'b1) );
mixcolumnsde mix2(.dout({s0_D,s0_E}), .add(s[0]), .clock(clk), .en(1'b1) );
// S1
mixcolumns9b mix3(.dout({s1_9,s1_B}), .add(s[1]), .clock(clk), .en(1'b1) );
mixcolumnsde mix4(.dout({s1_D,s1_E}), .add(s[1]), .clock(clk), .en(1'b1) );
// S2
mixcolumns9b mix5(.dout({s2_9,s2_B}), .add(s[2]), .clock(clk), .en(1'b1) );
mixcolumnsde mix6(.dout({s2_D,s2_E}), .add(s[2]), .clock(clk), .en(1'b1) );
// S3
mixcolumns9b mix7(.dout({s3_9,s3_B}), .add(s[3]), .clock(clk), .en(1'b1) );
mixcolumnsde mix8(.dout({s3_D,s3_E}), .add(s[3]), .clock(clk), .en(1'b1) );
assign cinv[0] = s0_E ^ s1_B ^ s2_D ^ s3_9;
assign cinv[1] = s0_9 ^ s1_E ^ s2_B ^ s3_D;
assign cinv[2] = s0_D ^ s1_9 ^ s2_E ^ s3_B;
assign cinv[3] = s0_B ^ s1_D ^ s2_9 ^ s3_E;
// Assign output
assign mixOutNorm = {c[0], c[1], c[2], c[3]};
assign mixOutInv = {cinv[0], cinv[1], cinv[2], cinv[3]};
assign mixOut = (inv)?(mixOutInv):(mixOutNorm);
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_a_e
//
// Generated
// by: wig
// on: Mon Mar 22 12:42:23 2004
// cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../io.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_a_e.v,v 1.1 2004/04/06 11:05:03 wig Exp $
// $Date: 2004/04/06 11:05:03 $
// $Log: inst_a_e.v,v $
// Revision 1.1 2004/04/06 11:05:03 wig
// Adding result/io
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
//
// Generator: mix_0.pl Revision: 1.26 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_a_e
//
// No `defines in this module
module inst_a_e
//
// Generated module inst_a
//
(
p_mix_sig_in_01_gi,
p_mix_sig_in_03_gi,
p_mix_sig_io_05_gc,
p_mix_sig_io_06_gc,
p_mix_sig_out_02_go,
p_mix_sig_out_04_go
);
// Generated Module Inputs:
input p_mix_sig_in_01_gi;
input [7:0] p_mix_sig_in_03_gi;
// Generated Module In/Outputs:
inout [5:0] p_mix_sig_io_05_gc;
inout [6:0] p_mix_sig_io_06_gc;
// Generated Module Outputs:
output p_mix_sig_out_02_go;
output [7:0] p_mix_sig_out_04_go;
// Generated Wires:
wire p_mix_sig_in_01_gi;
wire [7:0] p_mix_sig_in_03_gi;
wire [5:0] p_mix_sig_io_05_gc;
wire [6:0] p_mix_sig_io_06_gc;
wire p_mix_sig_out_02_go;
wire [7:0] p_mix_sig_out_04_go;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire sig_in_01; // __W_PORT_SIGNAL_MAP_REQ
wire [7:0] sig_in_03; // __W_PORT_SIGNAL_MAP_REQ
wire [5:0] sig_io_05; // __W_PORT_SIGNAL_MAP_REQ
wire [6:0] sig_io_06; // __W_PORT_SIGNAL_MAP_REQ
wire sig_out_02; // __W_PORT_SIGNAL_MAP_REQ
wire [7:0] sig_out_04; // __W_PORT_SIGNAL_MAP_REQ
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
assign sig_in_01 = p_mix_sig_in_01_gi; // __I_I_BIT_PORT
assign sig_in_03 = p_mix_sig_in_03_gi; // __I_I_BUS_PORT
assign sig_io_05 = p_mix_sig_io_05_gc; // __I_I_BUS_PORT
assign sig_io_06 = p_mix_sig_io_06_gc; // __I_I_BUS_PORT
assign p_mix_sig_out_02_go = sig_out_02; // __I_O_BIT_PORT
assign p_mix_sig_out_04_go = sig_out_04; // __I_O_BUS_PORT
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for inst_aa
inst_aa_e inst_aa(
.sig_in_01_p(sig_in_01),
.sig_in_03_p(sig_in_03),
.sig_io_out_05_p(sig_io_05),
.sig_io_out_06_p(sig_io_06),
.sig_out_02_p(sig_out_02),
.sig_out_04_p(sig_out_04)
);
// End of Generated Instance Port Map for inst_aa
// Generated Instance Port Map for inst_ab
inst_ab_e inst_ab(
);
// End of Generated Instance Port Map for inst_ab
// Generated Instance Port Map for inst_ac
inst_ac_e inst_ac(
);
// End of Generated Instance Port Map for inst_ac
endmodule
//
// End of Generated Module rtl of inst_a_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND2B_2_V
`define SKY130_FD_SC_LP__NAND2B_2_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog wrapper for nand2b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand2b_2 (
Y ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand2b base (
.Y(Y),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand2b_2 (
Y ,
A_N,
B
);
output Y ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand2b base (
.Y(Y),
.A_N(A_N),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND2B_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND3B_FUNCTIONAL_V
`define SKY130_FD_SC_HD__AND3B_FUNCTIONAL_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__and3b (
X ,
A_N,
B ,
C
);
// Module ports
output X ;
input A_N;
input B ;
input C ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X, C, not0_out, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND3B_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O211A_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__O211A_PP_BLACKBOX_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o211a (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O211A_PP_BLACKBOX_V
|
//
// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_hart0_server_reset_request_put O 1 reg
// hart0_server_reset_response_get O 1 reg
// RDY_hart0_server_reset_response_get O 1 reg
// imem_master_awvalid O 1 reg
// imem_master_awid O 4 reg
// imem_master_awaddr O 64 reg
// imem_master_awlen O 8 reg
// imem_master_awsize O 3 reg
// imem_master_awburst O 2 reg
// imem_master_awlock O 1 reg
// imem_master_awcache O 4 reg
// imem_master_awprot O 3 reg
// imem_master_awqos O 4 reg
// imem_master_awregion O 4 reg
// imem_master_wvalid O 1 reg
// imem_master_wdata O 64 reg
// imem_master_wstrb O 8 reg
// imem_master_wlast O 1 reg
// imem_master_bready O 1 reg
// imem_master_arvalid O 1 reg
// imem_master_arid O 4 reg
// imem_master_araddr O 64 reg
// imem_master_arlen O 8 reg
// imem_master_arsize O 3 reg
// imem_master_arburst O 2 reg
// imem_master_arlock O 1 reg
// imem_master_arcache O 4 reg
// imem_master_arprot O 3 reg
// imem_master_arqos O 4 reg
// imem_master_arregion O 4 reg
// imem_master_rready O 1 reg
// dmem_master_awvalid O 1 reg
// dmem_master_awid O 4 reg
// dmem_master_awaddr O 64 reg
// dmem_master_awlen O 8 reg
// dmem_master_awsize O 3 reg
// dmem_master_awburst O 2 reg
// dmem_master_awlock O 1 reg
// dmem_master_awcache O 4 reg
// dmem_master_awprot O 3 reg
// dmem_master_awqos O 4 reg
// dmem_master_awregion O 4 reg
// dmem_master_wvalid O 1 reg
// dmem_master_wdata O 64 reg
// dmem_master_wstrb O 8 reg
// dmem_master_wlast O 1 reg
// dmem_master_bready O 1 reg
// dmem_master_arvalid O 1 reg
// dmem_master_arid O 4 reg
// dmem_master_araddr O 64 reg
// dmem_master_arlen O 8 reg
// dmem_master_arsize O 3 reg
// dmem_master_arburst O 2 reg
// dmem_master_arlock O 1 reg
// dmem_master_arcache O 4 reg
// dmem_master_arprot O 3 reg
// dmem_master_arqos O 4 reg
// dmem_master_arregion O 4 reg
// dmem_master_rready O 1 reg
// RDY_set_verbosity O 1 const
// CLK I 1 clock
// RST_N I 1 reset
// hart0_server_reset_request_put I 1 reg
// imem_master_awready I 1
// imem_master_wready I 1
// imem_master_bvalid I 1
// imem_master_bid I 4 reg
// imem_master_bresp I 2 reg
// imem_master_arready I 1
// imem_master_rvalid I 1
// imem_master_rid I 4 reg
// imem_master_rdata I 64 reg
// imem_master_rresp I 2 reg
// imem_master_rlast I 1 reg
// dmem_master_awready I 1
// dmem_master_wready I 1
// dmem_master_bvalid I 1
// dmem_master_bid I 4 reg
// dmem_master_bresp I 2 reg
// dmem_master_arready I 1
// dmem_master_rvalid I 1
// dmem_master_rid I 4 reg
// dmem_master_rdata I 64 reg
// dmem_master_rresp I 2 reg
// dmem_master_rlast I 1 reg
// m_external_interrupt_req_set_not_clear I 1 reg
// s_external_interrupt_req_set_not_clear I 1 reg
// software_interrupt_req_set_not_clear I 1 reg
// timer_interrupt_req_set_not_clear I 1 reg
// nmi_req_set_not_clear I 1
// set_verbosity_verbosity I 4 reg
// set_verbosity_logdelay I 64 reg
// EN_hart0_server_reset_request_put I 1
// EN_set_verbosity I 1
// EN_hart0_server_reset_response_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkCPU(CLK,
RST_N,
hart0_server_reset_request_put,
EN_hart0_server_reset_request_put,
RDY_hart0_server_reset_request_put,
EN_hart0_server_reset_response_get,
hart0_server_reset_response_get,
RDY_hart0_server_reset_response_get,
imem_master_awvalid,
imem_master_awid,
imem_master_awaddr,
imem_master_awlen,
imem_master_awsize,
imem_master_awburst,
imem_master_awlock,
imem_master_awcache,
imem_master_awprot,
imem_master_awqos,
imem_master_awregion,
imem_master_awready,
imem_master_wvalid,
imem_master_wdata,
imem_master_wstrb,
imem_master_wlast,
imem_master_wready,
imem_master_bvalid,
imem_master_bid,
imem_master_bresp,
imem_master_bready,
imem_master_arvalid,
imem_master_arid,
imem_master_araddr,
imem_master_arlen,
imem_master_arsize,
imem_master_arburst,
imem_master_arlock,
imem_master_arcache,
imem_master_arprot,
imem_master_arqos,
imem_master_arregion,
imem_master_arready,
imem_master_rvalid,
imem_master_rid,
imem_master_rdata,
imem_master_rresp,
imem_master_rlast,
imem_master_rready,
dmem_master_awvalid,
dmem_master_awid,
dmem_master_awaddr,
dmem_master_awlen,
dmem_master_awsize,
dmem_master_awburst,
dmem_master_awlock,
dmem_master_awcache,
dmem_master_awprot,
dmem_master_awqos,
dmem_master_awregion,
dmem_master_awready,
dmem_master_wvalid,
dmem_master_wdata,
dmem_master_wstrb,
dmem_master_wlast,
dmem_master_wready,
dmem_master_bvalid,
dmem_master_bid,
dmem_master_bresp,
dmem_master_bready,
dmem_master_arvalid,
dmem_master_arid,
dmem_master_araddr,
dmem_master_arlen,
dmem_master_arsize,
dmem_master_arburst,
dmem_master_arlock,
dmem_master_arcache,
dmem_master_arprot,
dmem_master_arqos,
dmem_master_arregion,
dmem_master_arready,
dmem_master_rvalid,
dmem_master_rid,
dmem_master_rdata,
dmem_master_rresp,
dmem_master_rlast,
dmem_master_rready,
m_external_interrupt_req_set_not_clear,
s_external_interrupt_req_set_not_clear,
software_interrupt_req_set_not_clear,
timer_interrupt_req_set_not_clear,
nmi_req_set_not_clear,
set_verbosity_verbosity,
set_verbosity_logdelay,
EN_set_verbosity,
RDY_set_verbosity);
input CLK;
input RST_N;
// action method hart0_server_reset_request_put
input hart0_server_reset_request_put;
input EN_hart0_server_reset_request_put;
output RDY_hart0_server_reset_request_put;
// actionvalue method hart0_server_reset_response_get
input EN_hart0_server_reset_response_get;
output hart0_server_reset_response_get;
output RDY_hart0_server_reset_response_get;
// value method imem_master_m_awvalid
output imem_master_awvalid;
// value method imem_master_m_awid
output [3 : 0] imem_master_awid;
// value method imem_master_m_awaddr
output [63 : 0] imem_master_awaddr;
// value method imem_master_m_awlen
output [7 : 0] imem_master_awlen;
// value method imem_master_m_awsize
output [2 : 0] imem_master_awsize;
// value method imem_master_m_awburst
output [1 : 0] imem_master_awburst;
// value method imem_master_m_awlock
output imem_master_awlock;
// value method imem_master_m_awcache
output [3 : 0] imem_master_awcache;
// value method imem_master_m_awprot
output [2 : 0] imem_master_awprot;
// value method imem_master_m_awqos
output [3 : 0] imem_master_awqos;
// value method imem_master_m_awregion
output [3 : 0] imem_master_awregion;
// value method imem_master_m_awuser
// action method imem_master_m_awready
input imem_master_awready;
// value method imem_master_m_wvalid
output imem_master_wvalid;
// value method imem_master_m_wdata
output [63 : 0] imem_master_wdata;
// value method imem_master_m_wstrb
output [7 : 0] imem_master_wstrb;
// value method imem_master_m_wlast
output imem_master_wlast;
// value method imem_master_m_wuser
// action method imem_master_m_wready
input imem_master_wready;
// action method imem_master_m_bvalid
input imem_master_bvalid;
input [3 : 0] imem_master_bid;
input [1 : 0] imem_master_bresp;
// value method imem_master_m_bready
output imem_master_bready;
// value method imem_master_m_arvalid
output imem_master_arvalid;
// value method imem_master_m_arid
output [3 : 0] imem_master_arid;
// value method imem_master_m_araddr
output [63 : 0] imem_master_araddr;
// value method imem_master_m_arlen
output [7 : 0] imem_master_arlen;
// value method imem_master_m_arsize
output [2 : 0] imem_master_arsize;
// value method imem_master_m_arburst
output [1 : 0] imem_master_arburst;
// value method imem_master_m_arlock
output imem_master_arlock;
// value method imem_master_m_arcache
output [3 : 0] imem_master_arcache;
// value method imem_master_m_arprot
output [2 : 0] imem_master_arprot;
// value method imem_master_m_arqos
output [3 : 0] imem_master_arqos;
// value method imem_master_m_arregion
output [3 : 0] imem_master_arregion;
// value method imem_master_m_aruser
// action method imem_master_m_arready
input imem_master_arready;
// action method imem_master_m_rvalid
input imem_master_rvalid;
input [3 : 0] imem_master_rid;
input [63 : 0] imem_master_rdata;
input [1 : 0] imem_master_rresp;
input imem_master_rlast;
// value method imem_master_m_rready
output imem_master_rready;
// value method dmem_master_m_awvalid
output dmem_master_awvalid;
// value method dmem_master_m_awid
output [3 : 0] dmem_master_awid;
// value method dmem_master_m_awaddr
output [63 : 0] dmem_master_awaddr;
// value method dmem_master_m_awlen
output [7 : 0] dmem_master_awlen;
// value method dmem_master_m_awsize
output [2 : 0] dmem_master_awsize;
// value method dmem_master_m_awburst
output [1 : 0] dmem_master_awburst;
// value method dmem_master_m_awlock
output dmem_master_awlock;
// value method dmem_master_m_awcache
output [3 : 0] dmem_master_awcache;
// value method dmem_master_m_awprot
output [2 : 0] dmem_master_awprot;
// value method dmem_master_m_awqos
output [3 : 0] dmem_master_awqos;
// value method dmem_master_m_awregion
output [3 : 0] dmem_master_awregion;
// value method dmem_master_m_awuser
// action method dmem_master_m_awready
input dmem_master_awready;
// value method dmem_master_m_wvalid
output dmem_master_wvalid;
// value method dmem_master_m_wdata
output [63 : 0] dmem_master_wdata;
// value method dmem_master_m_wstrb
output [7 : 0] dmem_master_wstrb;
// value method dmem_master_m_wlast
output dmem_master_wlast;
// value method dmem_master_m_wuser
// action method dmem_master_m_wready
input dmem_master_wready;
// action method dmem_master_m_bvalid
input dmem_master_bvalid;
input [3 : 0] dmem_master_bid;
input [1 : 0] dmem_master_bresp;
// value method dmem_master_m_bready
output dmem_master_bready;
// value method dmem_master_m_arvalid
output dmem_master_arvalid;
// value method dmem_master_m_arid
output [3 : 0] dmem_master_arid;
// value method dmem_master_m_araddr
output [63 : 0] dmem_master_araddr;
// value method dmem_master_m_arlen
output [7 : 0] dmem_master_arlen;
// value method dmem_master_m_arsize
output [2 : 0] dmem_master_arsize;
// value method dmem_master_m_arburst
output [1 : 0] dmem_master_arburst;
// value method dmem_master_m_arlock
output dmem_master_arlock;
// value method dmem_master_m_arcache
output [3 : 0] dmem_master_arcache;
// value method dmem_master_m_arprot
output [2 : 0] dmem_master_arprot;
// value method dmem_master_m_arqos
output [3 : 0] dmem_master_arqos;
// value method dmem_master_m_arregion
output [3 : 0] dmem_master_arregion;
// value method dmem_master_m_aruser
// action method dmem_master_m_arready
input dmem_master_arready;
// action method dmem_master_m_rvalid
input dmem_master_rvalid;
input [3 : 0] dmem_master_rid;
input [63 : 0] dmem_master_rdata;
input [1 : 0] dmem_master_rresp;
input dmem_master_rlast;
// value method dmem_master_m_rready
output dmem_master_rready;
// action method m_external_interrupt_req
input m_external_interrupt_req_set_not_clear;
// action method s_external_interrupt_req
input s_external_interrupt_req_set_not_clear;
// action method software_interrupt_req
input software_interrupt_req_set_not_clear;
// action method timer_interrupt_req
input timer_interrupt_req_set_not_clear;
// action method nmi_req
input nmi_req_set_not_clear;
// action method set_verbosity
input [3 : 0] set_verbosity_verbosity;
input [63 : 0] set_verbosity_logdelay;
input EN_set_verbosity;
output RDY_set_verbosity;
// signals for module outputs
wire [63 : 0] dmem_master_araddr,
dmem_master_awaddr,
dmem_master_wdata,
imem_master_araddr,
imem_master_awaddr,
imem_master_wdata;
wire [7 : 0] dmem_master_arlen,
dmem_master_awlen,
dmem_master_wstrb,
imem_master_arlen,
imem_master_awlen,
imem_master_wstrb;
wire [3 : 0] dmem_master_arcache,
dmem_master_arid,
dmem_master_arqos,
dmem_master_arregion,
dmem_master_awcache,
dmem_master_awid,
dmem_master_awqos,
dmem_master_awregion,
imem_master_arcache,
imem_master_arid,
imem_master_arqos,
imem_master_arregion,
imem_master_awcache,
imem_master_awid,
imem_master_awqos,
imem_master_awregion;
wire [2 : 0] dmem_master_arprot,
dmem_master_arsize,
dmem_master_awprot,
dmem_master_awsize,
imem_master_arprot,
imem_master_arsize,
imem_master_awprot,
imem_master_awsize;
wire [1 : 0] dmem_master_arburst,
dmem_master_awburst,
imem_master_arburst,
imem_master_awburst;
wire RDY_hart0_server_reset_request_put,
RDY_hart0_server_reset_response_get,
RDY_set_verbosity,
dmem_master_arlock,
dmem_master_arvalid,
dmem_master_awlock,
dmem_master_awvalid,
dmem_master_bready,
dmem_master_rready,
dmem_master_wlast,
dmem_master_wvalid,
hart0_server_reset_response_get,
imem_master_arlock,
imem_master_arvalid,
imem_master_awlock,
imem_master_awvalid,
imem_master_bready,
imem_master_rready,
imem_master_wlast,
imem_master_wvalid;
// register cfg_logdelay
reg [63 : 0] cfg_logdelay;
wire [63 : 0] cfg_logdelay$D_IN;
wire cfg_logdelay$EN;
// register cfg_verbosity
reg [3 : 0] cfg_verbosity;
wire [3 : 0] cfg_verbosity$D_IN;
wire cfg_verbosity$EN;
// register imem_rg_cache_addr
reg [63 : 0] imem_rg_cache_addr;
wire [63 : 0] imem_rg_cache_addr$D_IN;
wire imem_rg_cache_addr$EN;
// register imem_rg_cache_b16
reg [15 : 0] imem_rg_cache_b16;
wire [15 : 0] imem_rg_cache_b16$D_IN;
wire imem_rg_cache_b16$EN;
// register imem_rg_f3
reg [2 : 0] imem_rg_f3;
wire [2 : 0] imem_rg_f3$D_IN;
wire imem_rg_f3$EN;
// register imem_rg_mstatus_MXR
reg imem_rg_mstatus_MXR;
wire imem_rg_mstatus_MXR$D_IN, imem_rg_mstatus_MXR$EN;
// register imem_rg_pc
reg [63 : 0] imem_rg_pc;
reg [63 : 0] imem_rg_pc$D_IN;
wire imem_rg_pc$EN;
// register imem_rg_priv
reg [1 : 0] imem_rg_priv;
wire [1 : 0] imem_rg_priv$D_IN;
wire imem_rg_priv$EN;
// register imem_rg_satp
reg [63 : 0] imem_rg_satp;
wire [63 : 0] imem_rg_satp$D_IN;
wire imem_rg_satp$EN;
// register imem_rg_sstatus_SUM
reg imem_rg_sstatus_SUM;
wire imem_rg_sstatus_SUM$D_IN, imem_rg_sstatus_SUM$EN;
// register imem_rg_tval
reg [63 : 0] imem_rg_tval;
reg [63 : 0] imem_rg_tval$D_IN;
wire imem_rg_tval$EN;
// register rg_csr_pc
reg [63 : 0] rg_csr_pc;
wire [63 : 0] rg_csr_pc$D_IN;
wire rg_csr_pc$EN;
// register rg_csr_val1
reg [63 : 0] rg_csr_val1;
wire [63 : 0] rg_csr_val1$D_IN;
wire rg_csr_val1$EN;
// register rg_cur_priv
reg [1 : 0] rg_cur_priv;
reg [1 : 0] rg_cur_priv$D_IN;
wire rg_cur_priv$EN;
// register rg_epoch
reg [1 : 0] rg_epoch;
reg [1 : 0] rg_epoch$D_IN;
wire rg_epoch$EN;
// register rg_mstatus_MXR
reg rg_mstatus_MXR;
wire rg_mstatus_MXR$D_IN, rg_mstatus_MXR$EN;
// register rg_next_pc
reg [63 : 0] rg_next_pc;
reg [63 : 0] rg_next_pc$D_IN;
wire rg_next_pc$EN;
// register rg_run_on_reset
reg rg_run_on_reset;
wire rg_run_on_reset$D_IN, rg_run_on_reset$EN;
// register rg_sstatus_SUM
reg rg_sstatus_SUM;
wire rg_sstatus_SUM$D_IN, rg_sstatus_SUM$EN;
// register rg_start_CPI_cycles
reg [63 : 0] rg_start_CPI_cycles;
wire [63 : 0] rg_start_CPI_cycles$D_IN;
wire rg_start_CPI_cycles$EN;
// register rg_start_CPI_instrs
reg [63 : 0] rg_start_CPI_instrs;
wire [63 : 0] rg_start_CPI_instrs$D_IN;
wire rg_start_CPI_instrs$EN;
// register rg_state
reg [3 : 0] rg_state;
reg [3 : 0] rg_state$D_IN;
wire rg_state$EN;
// register rg_trap_info
reg [131 : 0] rg_trap_info;
reg [131 : 0] rg_trap_info$D_IN;
wire rg_trap_info$EN;
// register rg_trap_instr
reg [31 : 0] rg_trap_instr;
wire [31 : 0] rg_trap_instr$D_IN;
wire rg_trap_instr$EN;
// register rg_trap_interrupt
reg rg_trap_interrupt;
wire rg_trap_interrupt$D_IN, rg_trap_interrupt$EN;
// register stage1_rg_full
reg stage1_rg_full;
reg stage1_rg_full$D_IN;
wire stage1_rg_full$EN;
// register stage1_rg_stage_input
reg [401 : 0] stage1_rg_stage_input;
wire [401 : 0] stage1_rg_stage_input$D_IN;
wire stage1_rg_stage_input$EN;
// register stage2_rg_full
reg stage2_rg_full;
reg stage2_rg_full$D_IN;
wire stage2_rg_full$EN;
// register stage2_rg_resetting
reg stage2_rg_resetting;
wire stage2_rg_resetting$D_IN, stage2_rg_resetting$EN;
// register stage2_rg_stage2
reg [297 : 0] stage2_rg_stage2;
wire [297 : 0] stage2_rg_stage2$D_IN;
wire stage2_rg_stage2$EN;
// register stage3_rg_full
reg stage3_rg_full;
reg stage3_rg_full$D_IN;
wire stage3_rg_full$EN;
// register stage3_rg_stage3
reg [167 : 0] stage3_rg_stage3;
wire [167 : 0] stage3_rg_stage3$D_IN;
wire stage3_rg_stage3$EN;
// register stageD_rg_data
reg [233 : 0] stageD_rg_data;
wire [233 : 0] stageD_rg_data$D_IN;
wire stageD_rg_data$EN;
// register stageD_rg_full
reg stageD_rg_full;
reg stageD_rg_full$D_IN;
wire stageD_rg_full$EN;
// register stageF_rg_epoch
reg [1 : 0] stageF_rg_epoch;
reg [1 : 0] stageF_rg_epoch$D_IN;
wire stageF_rg_epoch$EN;
// register stageF_rg_full
reg stageF_rg_full;
reg stageF_rg_full$D_IN;
wire stageF_rg_full$EN;
// register stageF_rg_priv
reg [1 : 0] stageF_rg_priv;
wire [1 : 0] stageF_rg_priv$D_IN;
wire stageF_rg_priv$EN;
// ports of submodule csr_regfile
reg [1 : 0] csr_regfile$csr_ret_actions_from_priv;
wire [193 : 0] csr_regfile$csr_trap_actions;
wire [129 : 0] csr_regfile$csr_ret_actions;
wire [64 : 0] csr_regfile$read_csr;
wire [63 : 0] csr_regfile$csr_trap_actions_pc,
csr_regfile$csr_trap_actions_xtval,
csr_regfile$mav_csr_write_word,
csr_regfile$read_csr_mcycle,
csr_regfile$read_csr_minstret,
csr_regfile$read_mstatus,
csr_regfile$read_satp;
wire [27 : 0] csr_regfile$read_misa;
wire [11 : 0] csr_regfile$access_permitted_1_csr_addr,
csr_regfile$access_permitted_2_csr_addr,
csr_regfile$csr_counter_read_fault_csr_addr,
csr_regfile$mav_csr_write_csr_addr,
csr_regfile$mav_read_csr_csr_addr,
csr_regfile$read_csr_csr_addr,
csr_regfile$read_csr_port2_csr_addr;
wire [4 : 0] csr_regfile$interrupt_pending;
wire [3 : 0] csr_regfile$csr_trap_actions_exc_code;
wire [1 : 0] csr_regfile$access_permitted_1_priv,
csr_regfile$access_permitted_2_priv,
csr_regfile$csr_counter_read_fault_priv,
csr_regfile$csr_trap_actions_from_priv,
csr_regfile$interrupt_pending_cur_priv;
wire csr_regfile$EN_csr_minstret_incr,
csr_regfile$EN_csr_ret_actions,
csr_regfile$EN_csr_trap_actions,
csr_regfile$EN_debug,
csr_regfile$EN_mav_csr_write,
csr_regfile$EN_mav_read_csr,
csr_regfile$EN_server_reset_request_put,
csr_regfile$EN_server_reset_response_get,
csr_regfile$RDY_server_reset_request_put,
csr_regfile$RDY_server_reset_response_get,
csr_regfile$access_permitted_1,
csr_regfile$access_permitted_1_read_not_write,
csr_regfile$access_permitted_2,
csr_regfile$access_permitted_2_read_not_write,
csr_regfile$csr_trap_actions_interrupt,
csr_regfile$csr_trap_actions_nmi,
csr_regfile$m_external_interrupt_req_set_not_clear,
csr_regfile$nmi_pending,
csr_regfile$nmi_req_set_not_clear,
csr_regfile$s_external_interrupt_req_set_not_clear,
csr_regfile$software_interrupt_req_set_not_clear,
csr_regfile$timer_interrupt_req_set_not_clear,
csr_regfile$wfi_resume;
// ports of submodule f_reset_reqs
wire f_reset_reqs$CLR,
f_reset_reqs$DEQ,
f_reset_reqs$D_IN,
f_reset_reqs$D_OUT,
f_reset_reqs$EMPTY_N,
f_reset_reqs$ENQ,
f_reset_reqs$FULL_N;
// ports of submodule f_reset_rsps
wire f_reset_rsps$CLR,
f_reset_rsps$DEQ,
f_reset_rsps$D_IN,
f_reset_rsps$D_OUT,
f_reset_rsps$EMPTY_N,
f_reset_rsps$ENQ,
f_reset_rsps$FULL_N;
// ports of submodule gpr_regfile
wire [63 : 0] gpr_regfile$read_rs1,
gpr_regfile$read_rs2,
gpr_regfile$write_rd_rd_val;
wire [4 : 0] gpr_regfile$read_rs1_port2_rs1,
gpr_regfile$read_rs1_rs1,
gpr_regfile$read_rs2_rs2,
gpr_regfile$write_rd_rd;
wire gpr_regfile$EN_server_reset_request_put,
gpr_regfile$EN_server_reset_response_get,
gpr_regfile$EN_write_rd,
gpr_regfile$RDY_server_reset_request_put,
gpr_regfile$RDY_server_reset_response_get;
// ports of submodule near_mem
reg [63 : 0] near_mem$imem_req_addr;
reg [1 : 0] near_mem$dmem_req_op;
wire [63 : 0] near_mem$dmem_master_araddr,
near_mem$dmem_master_awaddr,
near_mem$dmem_master_rdata,
near_mem$dmem_master_wdata,
near_mem$dmem_req_addr,
near_mem$dmem_req_satp,
near_mem$dmem_req_store_value,
near_mem$dmem_word64,
near_mem$imem_master_araddr,
near_mem$imem_master_awaddr,
near_mem$imem_master_rdata,
near_mem$imem_master_wdata,
near_mem$imem_pc,
near_mem$imem_req_satp;
wire [31 : 0] near_mem$imem_instr;
wire [7 : 0] near_mem$dmem_master_arlen,
near_mem$dmem_master_awlen,
near_mem$dmem_master_wstrb,
near_mem$imem_master_arlen,
near_mem$imem_master_awlen,
near_mem$imem_master_wstrb,
near_mem$server_fence_request_put;
wire [6 : 0] near_mem$dmem_req_amo_funct7;
wire [3 : 0] near_mem$dmem_exc_code,
near_mem$dmem_master_arcache,
near_mem$dmem_master_arid,
near_mem$dmem_master_arqos,
near_mem$dmem_master_arregion,
near_mem$dmem_master_awcache,
near_mem$dmem_master_awid,
near_mem$dmem_master_awqos,
near_mem$dmem_master_awregion,
near_mem$dmem_master_bid,
near_mem$dmem_master_rid,
near_mem$imem_exc_code,
near_mem$imem_master_arcache,
near_mem$imem_master_arid,
near_mem$imem_master_arqos,
near_mem$imem_master_arregion,
near_mem$imem_master_awcache,
near_mem$imem_master_awid,
near_mem$imem_master_awqos,
near_mem$imem_master_awregion,
near_mem$imem_master_bid,
near_mem$imem_master_rid;
wire [2 : 0] near_mem$dmem_master_arprot,
near_mem$dmem_master_arsize,
near_mem$dmem_master_awprot,
near_mem$dmem_master_awsize,
near_mem$dmem_req_f3,
near_mem$imem_master_arprot,
near_mem$imem_master_arsize,
near_mem$imem_master_awprot,
near_mem$imem_master_awsize,
near_mem$imem_req_f3;
wire [1 : 0] near_mem$dmem_master_arburst,
near_mem$dmem_master_awburst,
near_mem$dmem_master_bresp,
near_mem$dmem_master_rresp,
near_mem$dmem_req_priv,
near_mem$imem_master_arburst,
near_mem$imem_master_awburst,
near_mem$imem_master_bresp,
near_mem$imem_master_rresp,
near_mem$imem_req_priv;
wire near_mem$EN_dmem_req,
near_mem$EN_imem_req,
near_mem$EN_server_fence_i_request_put,
near_mem$EN_server_fence_i_response_get,
near_mem$EN_server_fence_request_put,
near_mem$EN_server_fence_response_get,
near_mem$EN_server_reset_request_put,
near_mem$EN_server_reset_response_get,
near_mem$EN_sfence_vma,
near_mem$RDY_server_fence_i_request_put,
near_mem$RDY_server_fence_i_response_get,
near_mem$RDY_server_fence_request_put,
near_mem$RDY_server_fence_response_get,
near_mem$RDY_server_reset_request_put,
near_mem$RDY_server_reset_response_get,
near_mem$dmem_exc,
near_mem$dmem_master_arlock,
near_mem$dmem_master_arready,
near_mem$dmem_master_arvalid,
near_mem$dmem_master_awlock,
near_mem$dmem_master_awready,
near_mem$dmem_master_awvalid,
near_mem$dmem_master_bready,
near_mem$dmem_master_bvalid,
near_mem$dmem_master_rlast,
near_mem$dmem_master_rready,
near_mem$dmem_master_rvalid,
near_mem$dmem_master_wlast,
near_mem$dmem_master_wready,
near_mem$dmem_master_wvalid,
near_mem$dmem_req_mstatus_MXR,
near_mem$dmem_req_sstatus_SUM,
near_mem$dmem_valid,
near_mem$imem_exc,
near_mem$imem_is_i32_not_i16,
near_mem$imem_master_arlock,
near_mem$imem_master_arready,
near_mem$imem_master_arvalid,
near_mem$imem_master_awlock,
near_mem$imem_master_awready,
near_mem$imem_master_awvalid,
near_mem$imem_master_bready,
near_mem$imem_master_bvalid,
near_mem$imem_master_rlast,
near_mem$imem_master_rready,
near_mem$imem_master_rvalid,
near_mem$imem_master_wlast,
near_mem$imem_master_wready,
near_mem$imem_master_wvalid,
near_mem$imem_req_mstatus_MXR,
near_mem$imem_req_sstatus_SUM,
near_mem$imem_valid;
// ports of submodule soc_map
wire [63 : 0] soc_map$m_is_IO_addr_addr,
soc_map$m_is_mem_addr_addr,
soc_map$m_is_near_mem_IO_addr_addr,
soc_map$m_pc_reset_value;
// ports of submodule stage1_f_reset_reqs
wire stage1_f_reset_reqs$CLR,
stage1_f_reset_reqs$DEQ,
stage1_f_reset_reqs$EMPTY_N,
stage1_f_reset_reqs$ENQ,
stage1_f_reset_reqs$FULL_N;
// ports of submodule stage1_f_reset_rsps
wire stage1_f_reset_rsps$CLR,
stage1_f_reset_rsps$DEQ,
stage1_f_reset_rsps$EMPTY_N,
stage1_f_reset_rsps$ENQ,
stage1_f_reset_rsps$FULL_N;
// ports of submodule stage2_f_reset_reqs
wire stage2_f_reset_reqs$CLR,
stage2_f_reset_reqs$DEQ,
stage2_f_reset_reqs$EMPTY_N,
stage2_f_reset_reqs$ENQ,
stage2_f_reset_reqs$FULL_N;
// ports of submodule stage2_f_reset_rsps
wire stage2_f_reset_rsps$CLR,
stage2_f_reset_rsps$DEQ,
stage2_f_reset_rsps$EMPTY_N,
stage2_f_reset_rsps$ENQ,
stage2_f_reset_rsps$FULL_N;
// ports of submodule stage2_mbox
wire [63 : 0] stage2_mbox$req_v1, stage2_mbox$req_v2, stage2_mbox$word;
wire [3 : 0] stage2_mbox$set_verbosity_verbosity;
wire [2 : 0] stage2_mbox$req_f3;
wire stage2_mbox$EN_req,
stage2_mbox$EN_req_reset,
stage2_mbox$EN_rsp_reset,
stage2_mbox$EN_set_verbosity,
stage2_mbox$req_is_OP_not_OP_32,
stage2_mbox$valid;
// ports of submodule stage3_f_reset_reqs
wire stage3_f_reset_reqs$CLR,
stage3_f_reset_reqs$DEQ,
stage3_f_reset_reqs$EMPTY_N,
stage3_f_reset_reqs$ENQ,
stage3_f_reset_reqs$FULL_N;
// ports of submodule stage3_f_reset_rsps
wire stage3_f_reset_rsps$CLR,
stage3_f_reset_rsps$DEQ,
stage3_f_reset_rsps$EMPTY_N,
stage3_f_reset_rsps$ENQ,
stage3_f_reset_rsps$FULL_N;
// ports of submodule stageD_f_reset_reqs
wire stageD_f_reset_reqs$CLR,
stageD_f_reset_reqs$DEQ,
stageD_f_reset_reqs$EMPTY_N,
stageD_f_reset_reqs$ENQ,
stageD_f_reset_reqs$FULL_N;
// ports of submodule stageD_f_reset_rsps
wire stageD_f_reset_rsps$CLR,
stageD_f_reset_rsps$DEQ,
stageD_f_reset_rsps$EMPTY_N,
stageD_f_reset_rsps$ENQ,
stageD_f_reset_rsps$FULL_N;
// ports of submodule stageF_branch_predictor
reg [63 : 0] stageF_branch_predictor$predict_req_pc;
wire [194 : 0] stageF_branch_predictor$bp_train_cf_info;
wire [63 : 0] stageF_branch_predictor$bp_train_pc,
stageF_branch_predictor$predict_rsp;
wire [31 : 0] stageF_branch_predictor$bp_train_instr,
stageF_branch_predictor$predict_rsp_instr;
wire stageF_branch_predictor$EN_bp_train,
stageF_branch_predictor$EN_predict_req,
stageF_branch_predictor$EN_reset,
stageF_branch_predictor$RDY_predict_req,
stageF_branch_predictor$bp_train_is_i32_not_i16,
stageF_branch_predictor$predict_rsp_is_i32_not_i16;
// ports of submodule stageF_f_reset_reqs
wire stageF_f_reset_reqs$CLR,
stageF_f_reset_reqs$DEQ,
stageF_f_reset_reqs$EMPTY_N,
stageF_f_reset_reqs$ENQ,
stageF_f_reset_reqs$FULL_N;
// ports of submodule stageF_f_reset_rsps
wire stageF_f_reset_rsps$CLR,
stageF_f_reset_rsps$DEQ,
stageF_f_reset_rsps$EMPTY_N,
stageF_f_reset_rsps$ENQ,
stageF_f_reset_rsps$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_imem_rl_assert_fail,
CAN_FIRE_RL_imem_rl_fetch_next_32b,
CAN_FIRE_RL_rl_WFI_resume,
CAN_FIRE_RL_rl_finish_FENCE,
CAN_FIRE_RL_rl_finish_FENCE_I,
CAN_FIRE_RL_rl_finish_SFENCE_VMA,
CAN_FIRE_RL_rl_pipe,
CAN_FIRE_RL_rl_reset_complete,
CAN_FIRE_RL_rl_reset_from_WFI,
CAN_FIRE_RL_rl_reset_start,
CAN_FIRE_RL_rl_show_pipe,
CAN_FIRE_RL_rl_stage1_CSRR_S_or_C,
CAN_FIRE_RL_rl_stage1_CSRR_S_or_C_2,
CAN_FIRE_RL_rl_stage1_CSRR_W,
CAN_FIRE_RL_rl_stage1_CSRR_W_2,
CAN_FIRE_RL_rl_stage1_FENCE,
CAN_FIRE_RL_rl_stage1_FENCE_I,
CAN_FIRE_RL_rl_stage1_SFENCE_VMA,
CAN_FIRE_RL_rl_stage1_WFI,
CAN_FIRE_RL_rl_stage1_interrupt,
CAN_FIRE_RL_rl_stage1_restart_after_csrrx,
CAN_FIRE_RL_rl_stage1_trap,
CAN_FIRE_RL_rl_stage1_xRET,
CAN_FIRE_RL_rl_stage2_nonpipe,
CAN_FIRE_RL_rl_trap,
CAN_FIRE_RL_rl_trap_fetch,
CAN_FIRE_RL_stage1_rl_reset,
CAN_FIRE_RL_stage2_rl_reset_begin,
CAN_FIRE_RL_stage2_rl_reset_end,
CAN_FIRE_RL_stage3_rl_reset,
CAN_FIRE_RL_stageD_rl_reset,
CAN_FIRE_RL_stageF_rl_reset,
CAN_FIRE_dmem_master_m_arready,
CAN_FIRE_dmem_master_m_awready,
CAN_FIRE_dmem_master_m_bvalid,
CAN_FIRE_dmem_master_m_rvalid,
CAN_FIRE_dmem_master_m_wready,
CAN_FIRE_hart0_server_reset_request_put,
CAN_FIRE_hart0_server_reset_response_get,
CAN_FIRE_imem_master_m_arready,
CAN_FIRE_imem_master_m_awready,
CAN_FIRE_imem_master_m_bvalid,
CAN_FIRE_imem_master_m_rvalid,
CAN_FIRE_imem_master_m_wready,
CAN_FIRE_m_external_interrupt_req,
CAN_FIRE_nmi_req,
CAN_FIRE_s_external_interrupt_req,
CAN_FIRE_set_verbosity,
CAN_FIRE_software_interrupt_req,
CAN_FIRE_timer_interrupt_req,
WILL_FIRE_RL_imem_rl_assert_fail,
WILL_FIRE_RL_imem_rl_fetch_next_32b,
WILL_FIRE_RL_rl_WFI_resume,
WILL_FIRE_RL_rl_finish_FENCE,
WILL_FIRE_RL_rl_finish_FENCE_I,
WILL_FIRE_RL_rl_finish_SFENCE_VMA,
WILL_FIRE_RL_rl_pipe,
WILL_FIRE_RL_rl_reset_complete,
WILL_FIRE_RL_rl_reset_from_WFI,
WILL_FIRE_RL_rl_reset_start,
WILL_FIRE_RL_rl_show_pipe,
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C,
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2,
WILL_FIRE_RL_rl_stage1_CSRR_W,
WILL_FIRE_RL_rl_stage1_CSRR_W_2,
WILL_FIRE_RL_rl_stage1_FENCE,
WILL_FIRE_RL_rl_stage1_FENCE_I,
WILL_FIRE_RL_rl_stage1_SFENCE_VMA,
WILL_FIRE_RL_rl_stage1_WFI,
WILL_FIRE_RL_rl_stage1_interrupt,
WILL_FIRE_RL_rl_stage1_restart_after_csrrx,
WILL_FIRE_RL_rl_stage1_trap,
WILL_FIRE_RL_rl_stage1_xRET,
WILL_FIRE_RL_rl_stage2_nonpipe,
WILL_FIRE_RL_rl_trap,
WILL_FIRE_RL_rl_trap_fetch,
WILL_FIRE_RL_stage1_rl_reset,
WILL_FIRE_RL_stage2_rl_reset_begin,
WILL_FIRE_RL_stage2_rl_reset_end,
WILL_FIRE_RL_stage3_rl_reset,
WILL_FIRE_RL_stageD_rl_reset,
WILL_FIRE_RL_stageF_rl_reset,
WILL_FIRE_dmem_master_m_arready,
WILL_FIRE_dmem_master_m_awready,
WILL_FIRE_dmem_master_m_bvalid,
WILL_FIRE_dmem_master_m_rvalid,
WILL_FIRE_dmem_master_m_wready,
WILL_FIRE_hart0_server_reset_request_put,
WILL_FIRE_hart0_server_reset_response_get,
WILL_FIRE_imem_master_m_arready,
WILL_FIRE_imem_master_m_awready,
WILL_FIRE_imem_master_m_bvalid,
WILL_FIRE_imem_master_m_rvalid,
WILL_FIRE_imem_master_m_wready,
WILL_FIRE_m_external_interrupt_req,
WILL_FIRE_nmi_req,
WILL_FIRE_s_external_interrupt_req,
WILL_FIRE_set_verbosity,
WILL_FIRE_software_interrupt_req,
WILL_FIRE_timer_interrupt_req;
// inputs to muxes for submodule ports
reg [63 : 0] MUX_csr_regfile$mav_csr_write_2__VAL_2;
wire [131 : 0] MUX_rg_trap_info$write_1__VAL_1,
MUX_rg_trap_info$write_1__VAL_2,
MUX_rg_trap_info$write_1__VAL_3,
MUX_rg_trap_info$write_1__VAL_4;
wire [63 : 0] MUX_imem_rg_tval$write_1__VAL_4,
MUX_near_mem$imem_req_2__VAL_1,
MUX_near_mem$imem_req_2__VAL_2,
MUX_near_mem$imem_req_2__VAL_4;
wire [31 : 0] MUX_rg_trap_instr$write_1__VAL_1;
wire [3 : 0] MUX_rg_state$write_1__VAL_2,
MUX_rg_state$write_1__VAL_3,
MUX_rg_state$write_1__VAL_4;
wire MUX_csr_regfile$mav_csr_write_1__SEL_1,
MUX_gpr_regfile$write_rd_1__SEL_3,
MUX_imem_rg_cache_addr$write_1__SEL_3,
MUX_imem_rg_f3$write_1__SEL_1,
MUX_rg_next_pc$write_1__SEL_1,
MUX_rg_next_pc$write_1__SEL_2,
MUX_rg_state$write_1__SEL_1,
MUX_rg_state$write_1__SEL_10,
MUX_rg_state$write_1__SEL_11,
MUX_rg_state$write_1__SEL_12,
MUX_rg_state$write_1__SEL_13,
MUX_rg_state$write_1__SEL_2,
MUX_rg_state$write_1__SEL_5,
MUX_rg_state$write_1__SEL_7,
MUX_rg_state$write_1__SEL_8,
MUX_rg_state$write_1__SEL_9,
MUX_rg_trap_info$write_1__SEL_1,
MUX_rg_trap_instr$write_1__SEL_1,
MUX_rg_trap_interrupt$write_1__SEL_1,
MUX_stage1_rg_full$write_1__VAL_2,
MUX_stage2_rg_full$write_1__VAL_2,
MUX_stageD_rg_full$write_1__VAL_2,
MUX_stageF_rg_full$write_1__VAL_2;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h2136;
reg [31 : 0] v__h2130;
// synopsys translate_on
// remaining internal signals
reg [63 : 0] CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q23,
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d824,
_theResult_____1_fst__h8786,
alu_outputs___1_val1__h8068,
rs1_val__h23899,
x_out_bypass_rd_val__h7420,
x_out_cf_info_taken_PC__h9708,
x_out_data_to_stage2_addr__h7708,
x_out_data_to_stage2_val1__h7709,
x_out_data_to_stage3_rd_val__h7081;
reg [4 : 0] x_out_bypass_rd__h7419, x_out_data_to_stage3_rd__h7080;
reg [3 : 0] CASE_rg_cur_priv_0b0_8_0b1_9_11__q3,
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q16,
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q17,
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q18,
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q20,
CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_1_ETC__q19,
CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_C_ETC__q4,
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d538,
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d541,
alu_outputs_exc_code__h8364;
reg [2 : 0] CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q24,
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q25;
reg [1 : 0] CASE_stage2_rg_stage2_BITS_199_TO_197_0_2_1_IF_ETC__q5,
CASE_stage2_rg_stage2_BITS_199_TO_197_0_2_1_IF_ETC__q6,
IF_NOT_stage1_rg_full_03_87_OR_NOT_stage1_rg_s_ETC___d626;
reg CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q12,
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q13,
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q14,
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q15,
IF_stage1_rg_stage_input_04_BITS_112_TO_110_33_ETC___d279,
IF_stage1_rg_stage_input_04_BITS_112_TO_110_33_ETC___d405,
IF_stage2_rg_stage2_01_BITS_199_TO_197_02_EQ_1_ETC___d145,
IF_stage2_rg_stage2_01_BITS_199_TO_197_02_EQ_1_ETC___d154;
wire [127 : 0] csr_regfile_read_csr_mcycle__0_MINUS_rg_start__ETC___d1774;
wire [63 : 0] IF_csr_regfile_read_csr_rg_trap_instr_771_BITS_ETC___d1826,
IF_stage1_rg_stage_input_04_BITS_139_TO_135_07_ETC___d655,
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d825,
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d826,
SEXT_stage1_rg_stage_input_04_BITS_87_TO_76_02___d654,
_theResult_____1_fst__h8779,
_theResult_____1_fst__h8814,
_theResult____h22748,
_theResult___fst__h8884,
_theResult___fst__h8891,
_theResult___fst__h8951,
_theResult___snd__h10041,
addr_of_b32___1__h18620,
addr_of_b32___1__h21691,
addr_of_b32___1__h30871,
addr_of_b32__h18508,
addr_of_b32__h21579,
addr_of_b32__h30759,
alu_outputs___1_addr__h7863,
alu_outputs___1_addr__h8135,
alu_outputs___1_val1__h7990,
alu_outputs___1_val1__h8026,
alu_outputs___1_val1__h8047,
alu_outputs___1_val1__h8324,
alu_outputs___1_val1__h8344,
alu_outputs_cf_info_fallthru_PC__h9699,
alu_outputs_cf_info_taken_PC__h9700,
branch_target__h7840,
cpi__h22750,
cpifrac__h22751,
data_to_stage2_addr__h7698,
delta_CPI_cycles__h22746,
delta_CPI_instrs___1__h22783,
delta_CPI_instrs__h22747,
fall_through_pc__h7648,
next_pc___1__h9323,
next_pc__h7649,
next_pc__h7869,
next_pc__h7896,
next_pc__h9320,
rd_val___1__h10070,
rd_val___1__h10101,
rd_val___1__h10154,
rd_val___1__h10183,
rd_val___1__h10235,
rd_val___1__h10283,
rd_val___1__h10289,
rd_val___1__h10334,
rd_val___1__h8767,
rd_val___1__h8775,
rd_val___1__h8782,
rd_val___1__h8789,
rd_val___1__h8796,
rd_val___1__h8803,
rd_val__h10011,
rd_val__h7550,
rd_val__h7624,
rd_val__h8075,
rd_val__h8089,
rd_val__h9938,
rd_val__h9989,
rs1_val__h23220,
rs1_val_bypassed__h4837,
rs2_val_bypassed__h4843,
trap_info_tval__h9527,
val__h7552,
val__h7626,
value__h9576,
x__h22749,
x_out_cf_info_fallthru_PC__h9707,
x_out_data_to_stage2_val2__h7710,
x_out_next_pc__h7665,
y__h24168;
wire [31 : 0] IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem__ETC___d1319,
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1165,
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1166,
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1168,
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1170,
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1172,
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1174,
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1175,
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1176,
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1178,
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1179,
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1180,
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1182,
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1184,
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1185,
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1187,
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1188,
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1189,
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1190,
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1191,
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1192,
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1193,
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1194,
IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg_p_ETC___d1320,
IF_stage1_rg_stage_input_04_BITS_139_TO_135_07_ETC__q22,
_theResult____h5108,
d_instr__h16678,
instr___1__h10647,
instr__h10816,
instr__h10961,
instr__h11153,
instr__h11348,
instr__h11577,
instr__h12030,
instr__h12146,
instr__h12211,
instr__h12528,
instr__h12866,
instr__h13050,
instr__h13179,
instr__h13406,
instr__h13661,
instr__h13833,
instr__h14002,
instr__h14191,
instr__h14380,
instr__h14497,
instr__h14675,
instr__h14794,
instr__h14889,
instr__h15025,
instr__h15161,
instr__h15297,
instr__h15435,
instr__h15573,
instr__h15731,
instr__h15827,
instr__h15980,
instr__h16179,
instr__h16330,
instr_out___1__h16680,
instr_out___1__h16702,
rs1_val_bypassed837_BITS_31_TO_0_MINUS_rs2_val_ETC__q11,
rs1_val_bypassed837_BITS_31_TO_0_PLUS_rs2_val__ETC__q10,
rs1_val_bypassed837_BITS_31_TO_0_SRL_rs2_val_b_ETC__q9,
rs1_val_bypassed837_BITS_31_TO_0__q8,
tmp__h10182,
v32__h8073,
x__h10104,
x__h10157,
x__h10292,
x__h10337,
x_out_data_to_stage1_instr__h10611;
wire [20 : 0] SEXT_stageD_rg_data_21_BIT_76_38_CONCAT_stageD_ETC___d991,
decoded_instr_imm21_UJ__h20273,
stage1_rg_stage_input_BITS_30_TO_10__q2;
wire [19 : 0] imm20__h12918;
wire [12 : 0] SEXT_stageD_rg_data_21_BIT_76_38_CONCAT_stageD_ETC___d1016,
decoded_instr_imm13_SB__h20271,
stage1_rg_stage_input_BITS_63_TO_51__q1;
wire [11 : 0] decoded_instr_imm12_S__h20270,
imm12__h10817,
imm12__h11154,
imm12__h12790,
imm12__h13459,
imm12__h13674,
imm12__h13870,
imm12__h14207,
imm12__h15828,
imm12__h16180,
offset__h11524,
stage1_rg_stage_input_BITS_75_TO_64__q7,
stage1_rg_stage_input_BITS_87_TO_76__q21;
wire [9 : 0] decoded_instr_funct10__h20268,
nzimm10__h13457,
nzimm10__h13672;
wire [8 : 0] offset__h12155, offset__h15742;
wire [7 : 0] offset__h10689, offset__h16114;
wire [6 : 0] offset__h11096;
wire [5 : 0] imm6__h12788, shamt__h7977;
wire [4 : 0] data_to_stage2_rd__h7697,
offset_BITS_4_TO_0___h11085,
offset_BITS_4_TO_0___h11516,
offset_BITS_4_TO_0___h16455,
rd__h11156,
rs1__h11155,
x_out_data_to_stage2_rd__h7707;
wire [3 : 0] IF_NOT_stage1_rg_stage_input_04_BITS_112_TO_11_ETC___d490,
IF_rg_cur_priv_1_EQ_0b11_06_AND_stage1_rg_stag_ETC___d520,
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544,
alu_outputs___1_exc_code__h8320,
cur_verbosity__h3317,
x_exc_code__h31121,
x_out_trap_info_exc_code__h9532;
wire [2 : 0] IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d690;
wire [1 : 0] IF_NOT_near_mem_dmem_valid__22_41_OR_NOT_near__ETC___d187,
IF_near_mem_dmem_valid__22_THEN_IF_near_mem_dm_ETC___d125,
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131,
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d191,
IF_stage2_rg_stage2_01_BITS_199_TO_197_02_EQ_3_ETC___d128,
new_epoch__h18044,
sxl__h6149,
uxl__h6150;
wire IF_IF_stage1_rg_stage_input_04_BITS_151_TO_145_ETC___d911,
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1529,
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1532,
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1643,
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1684,
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1691,
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1703,
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1727,
IF_NOT_stage1_rg_full_03_87_OR_NOT_stage1_rg_s_ETC___d1561,
IF_NOT_stage1_rg_full_03_87_OR_NOT_stage1_rg_s_ETC___d1591,
IF_stage1_rg_stage_input_04_BITS_139_TO_135_07_ETC___d268,
IF_stage1_rg_stage_input_04_BITS_139_TO_135_07_ETC___d270,
IF_stage1_rg_stage_input_04_BITS_139_TO_135_07_ETC___d272,
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d399,
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d410,
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d478,
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d480,
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d1514,
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d208,
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d210,
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d483,
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49,
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d1522,
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1521,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1525,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1534,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1536,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1542,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1564,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1581,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1588,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1617,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1640,
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1746,
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1302,
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1316,
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1345,
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1347,
NOT_rg_next_pc_837_BITS_1_TO_0_838_EQ_0b0_839__ETC___d1846,
NOT_soc_map_m_pc_reset_value__492_BITS_1_TO_0__ETC___d1505,
NOT_stage1_rg_full_03_87_OR_stage1_rg_stage_in_ETC___d1557,
NOT_stage1_rg_full_03_87_OR_stage1_rg_stage_in_ETC___d1559,
NOT_stage1_rg_stage_input_04_BITS_112_TO_110_3_ETC___d315,
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d1894,
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d1898,
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d417,
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d617,
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d629,
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d633,
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d639,
NOT_stageF_branch_predictor_predict_rsp_NOT_im_ETC___d1712,
csr_regfile_RDY_server_reset_request_put__447__ETC___d1459,
csr_regfile_RDY_server_reset_response_get__466_ETC___d1487,
csr_regfile_interrupt_pending_rg_cur_priv_1_50_ETC___d1694,
csr_regfile_interrupt_pending_rg_cur_priv_1_50_ETC___d1698,
csr_regfile_interrupt_pending_rg_cur_priv_1_50_ETC___d1701,
csr_regfile_interrupt_pending_rg_cur_priv_1_50_ETC___d1736,
csr_regfile_read_misa__9_BIT_2_26_AND_stageD_r_ETC___d1001,
csr_regfile_read_misa__9_BIT_2_26_AND_stageD_r_ETC___d1007,
f_reset_rsps_i_notFull__472_AND_NOT_rg_run_on__ETC___d1481,
imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1334,
imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1338,
imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1341,
imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d1477,
imem_rg_pc_BITS_63_TO_2_0_EQ_imem_rg_cache_add_ETC___d1294,
imem_rg_pc_BITS_63_TO_2_0_EQ_near_mem_imem_pc__ETC___d13,
near_mem_imem_pc__1_EQ_imem_rg_pc_PLUS_2_296___d1297,
near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d1443,
rg_cur_priv_1_EQ_0b11_06_OR_rg_cur_priv_1_EQ_0_ETC___d518,
rg_state_0_EQ_12_7_AND_csr_regfile_wfi_resume__ETC___d1885,
rg_state_0_EQ_3_544_AND_NOT_csr_regfile_interr_ETC___d1750,
rg_state_0_EQ_3_544_AND_NOT_csr_regfile_interr_ETC___d1861,
rg_state_0_EQ_3_544_AND_NOT_csr_regfile_interr_ETC___d1870,
rg_state_0_EQ_3_544_AND_stage3_rg_full_1_OR_NO_ETC___d1554,
rg_state_0_EQ_5_889_AND_NOT_stageF_rg_full_324_ETC___d1890,
rg_state_0_EQ_8_834_AND_NOT_stageF_rg_full_324_ETC___d1835,
rg_trap_info_760_BITS_131_TO_68_761_EQ_csr_reg_ETC___d1770,
stage1_rg_full_03_AND_NOT_stage1_rg_stage_inpu_ETC___d486,
stage1_rg_stage_input_04_BITS_112_TO_110_33_EQ_ETC___d437,
stage1_rg_stage_input_04_BITS_151_TO_145_31_EQ_ETC___d430,
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d1517,
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206,
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d224,
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d861,
stage3_rg_full_1_OR_NOT_IF_stage2_rg_full_00_T_ETC___d1552,
stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1356,
stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1362,
stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1366,
stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1370,
stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1374,
stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1378,
stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1382,
stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1386,
stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1390,
stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1394,
stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1398,
stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1402,
stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1406,
stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1410,
stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1414;
// action method hart0_server_reset_request_put
assign RDY_hart0_server_reset_request_put = f_reset_reqs$FULL_N ;
assign CAN_FIRE_hart0_server_reset_request_put = f_reset_reqs$FULL_N ;
assign WILL_FIRE_hart0_server_reset_request_put =
EN_hart0_server_reset_request_put ;
// actionvalue method hart0_server_reset_response_get
assign hart0_server_reset_response_get = f_reset_rsps$D_OUT ;
assign RDY_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_hart0_server_reset_response_get =
EN_hart0_server_reset_response_get ;
// value method imem_master_m_awvalid
assign imem_master_awvalid = near_mem$imem_master_awvalid ;
// value method imem_master_m_awid
assign imem_master_awid = near_mem$imem_master_awid ;
// value method imem_master_m_awaddr
assign imem_master_awaddr = near_mem$imem_master_awaddr ;
// value method imem_master_m_awlen
assign imem_master_awlen = near_mem$imem_master_awlen ;
// value method imem_master_m_awsize
assign imem_master_awsize = near_mem$imem_master_awsize ;
// value method imem_master_m_awburst
assign imem_master_awburst = near_mem$imem_master_awburst ;
// value method imem_master_m_awlock
assign imem_master_awlock = near_mem$imem_master_awlock ;
// value method imem_master_m_awcache
assign imem_master_awcache = near_mem$imem_master_awcache ;
// value method imem_master_m_awprot
assign imem_master_awprot = near_mem$imem_master_awprot ;
// value method imem_master_m_awqos
assign imem_master_awqos = near_mem$imem_master_awqos ;
// value method imem_master_m_awregion
assign imem_master_awregion = near_mem$imem_master_awregion ;
// action method imem_master_m_awready
assign CAN_FIRE_imem_master_m_awready = 1'd1 ;
assign WILL_FIRE_imem_master_m_awready = 1'd1 ;
// value method imem_master_m_wvalid
assign imem_master_wvalid = near_mem$imem_master_wvalid ;
// value method imem_master_m_wdata
assign imem_master_wdata = near_mem$imem_master_wdata ;
// value method imem_master_m_wstrb
assign imem_master_wstrb = near_mem$imem_master_wstrb ;
// value method imem_master_m_wlast
assign imem_master_wlast = near_mem$imem_master_wlast ;
// action method imem_master_m_wready
assign CAN_FIRE_imem_master_m_wready = 1'd1 ;
assign WILL_FIRE_imem_master_m_wready = 1'd1 ;
// action method imem_master_m_bvalid
assign CAN_FIRE_imem_master_m_bvalid = 1'd1 ;
assign WILL_FIRE_imem_master_m_bvalid = 1'd1 ;
// value method imem_master_m_bready
assign imem_master_bready = near_mem$imem_master_bready ;
// value method imem_master_m_arvalid
assign imem_master_arvalid = near_mem$imem_master_arvalid ;
// value method imem_master_m_arid
assign imem_master_arid = near_mem$imem_master_arid ;
// value method imem_master_m_araddr
assign imem_master_araddr = near_mem$imem_master_araddr ;
// value method imem_master_m_arlen
assign imem_master_arlen = near_mem$imem_master_arlen ;
// value method imem_master_m_arsize
assign imem_master_arsize = near_mem$imem_master_arsize ;
// value method imem_master_m_arburst
assign imem_master_arburst = near_mem$imem_master_arburst ;
// value method imem_master_m_arlock
assign imem_master_arlock = near_mem$imem_master_arlock ;
// value method imem_master_m_arcache
assign imem_master_arcache = near_mem$imem_master_arcache ;
// value method imem_master_m_arprot
assign imem_master_arprot = near_mem$imem_master_arprot ;
// value method imem_master_m_arqos
assign imem_master_arqos = near_mem$imem_master_arqos ;
// value method imem_master_m_arregion
assign imem_master_arregion = near_mem$imem_master_arregion ;
// action method imem_master_m_arready
assign CAN_FIRE_imem_master_m_arready = 1'd1 ;
assign WILL_FIRE_imem_master_m_arready = 1'd1 ;
// action method imem_master_m_rvalid
assign CAN_FIRE_imem_master_m_rvalid = 1'd1 ;
assign WILL_FIRE_imem_master_m_rvalid = 1'd1 ;
// value method imem_master_m_rready
assign imem_master_rready = near_mem$imem_master_rready ;
// value method dmem_master_m_awvalid
assign dmem_master_awvalid = near_mem$dmem_master_awvalid ;
// value method dmem_master_m_awid
assign dmem_master_awid = near_mem$dmem_master_awid ;
// value method dmem_master_m_awaddr
assign dmem_master_awaddr = near_mem$dmem_master_awaddr ;
// value method dmem_master_m_awlen
assign dmem_master_awlen = near_mem$dmem_master_awlen ;
// value method dmem_master_m_awsize
assign dmem_master_awsize = near_mem$dmem_master_awsize ;
// value method dmem_master_m_awburst
assign dmem_master_awburst = near_mem$dmem_master_awburst ;
// value method dmem_master_m_awlock
assign dmem_master_awlock = near_mem$dmem_master_awlock ;
// value method dmem_master_m_awcache
assign dmem_master_awcache = near_mem$dmem_master_awcache ;
// value method dmem_master_m_awprot
assign dmem_master_awprot = near_mem$dmem_master_awprot ;
// value method dmem_master_m_awqos
assign dmem_master_awqos = near_mem$dmem_master_awqos ;
// value method dmem_master_m_awregion
assign dmem_master_awregion = near_mem$dmem_master_awregion ;
// action method dmem_master_m_awready
assign CAN_FIRE_dmem_master_m_awready = 1'd1 ;
assign WILL_FIRE_dmem_master_m_awready = 1'd1 ;
// value method dmem_master_m_wvalid
assign dmem_master_wvalid = near_mem$dmem_master_wvalid ;
// value method dmem_master_m_wdata
assign dmem_master_wdata = near_mem$dmem_master_wdata ;
// value method dmem_master_m_wstrb
assign dmem_master_wstrb = near_mem$dmem_master_wstrb ;
// value method dmem_master_m_wlast
assign dmem_master_wlast = near_mem$dmem_master_wlast ;
// action method dmem_master_m_wready
assign CAN_FIRE_dmem_master_m_wready = 1'd1 ;
assign WILL_FIRE_dmem_master_m_wready = 1'd1 ;
// action method dmem_master_m_bvalid
assign CAN_FIRE_dmem_master_m_bvalid = 1'd1 ;
assign WILL_FIRE_dmem_master_m_bvalid = 1'd1 ;
// value method dmem_master_m_bready
assign dmem_master_bready = near_mem$dmem_master_bready ;
// value method dmem_master_m_arvalid
assign dmem_master_arvalid = near_mem$dmem_master_arvalid ;
// value method dmem_master_m_arid
assign dmem_master_arid = near_mem$dmem_master_arid ;
// value method dmem_master_m_araddr
assign dmem_master_araddr = near_mem$dmem_master_araddr ;
// value method dmem_master_m_arlen
assign dmem_master_arlen = near_mem$dmem_master_arlen ;
// value method dmem_master_m_arsize
assign dmem_master_arsize = near_mem$dmem_master_arsize ;
// value method dmem_master_m_arburst
assign dmem_master_arburst = near_mem$dmem_master_arburst ;
// value method dmem_master_m_arlock
assign dmem_master_arlock = near_mem$dmem_master_arlock ;
// value method dmem_master_m_arcache
assign dmem_master_arcache = near_mem$dmem_master_arcache ;
// value method dmem_master_m_arprot
assign dmem_master_arprot = near_mem$dmem_master_arprot ;
// value method dmem_master_m_arqos
assign dmem_master_arqos = near_mem$dmem_master_arqos ;
// value method dmem_master_m_arregion
assign dmem_master_arregion = near_mem$dmem_master_arregion ;
// action method dmem_master_m_arready
assign CAN_FIRE_dmem_master_m_arready = 1'd1 ;
assign WILL_FIRE_dmem_master_m_arready = 1'd1 ;
// action method dmem_master_m_rvalid
assign CAN_FIRE_dmem_master_m_rvalid = 1'd1 ;
assign WILL_FIRE_dmem_master_m_rvalid = 1'd1 ;
// value method dmem_master_m_rready
assign dmem_master_rready = near_mem$dmem_master_rready ;
// action method m_external_interrupt_req
assign CAN_FIRE_m_external_interrupt_req = 1'd1 ;
assign WILL_FIRE_m_external_interrupt_req = 1'd1 ;
// action method s_external_interrupt_req
assign CAN_FIRE_s_external_interrupt_req = 1'd1 ;
assign WILL_FIRE_s_external_interrupt_req = 1'd1 ;
// action method software_interrupt_req
assign CAN_FIRE_software_interrupt_req = 1'd1 ;
assign WILL_FIRE_software_interrupt_req = 1'd1 ;
// action method timer_interrupt_req
assign CAN_FIRE_timer_interrupt_req = 1'd1 ;
assign WILL_FIRE_timer_interrupt_req = 1'd1 ;
// action method nmi_req
assign CAN_FIRE_nmi_req = 1'd1 ;
assign WILL_FIRE_nmi_req = 1'd1 ;
// action method set_verbosity
assign RDY_set_verbosity = 1'd1 ;
assign CAN_FIRE_set_verbosity = 1'd1 ;
assign WILL_FIRE_set_verbosity = EN_set_verbosity ;
// submodule csr_regfile
mkCSR_RegFile csr_regfile(.CLK(CLK),
.RST_N(RST_N),
.access_permitted_1_csr_addr(csr_regfile$access_permitted_1_csr_addr),
.access_permitted_1_priv(csr_regfile$access_permitted_1_priv),
.access_permitted_1_read_not_write(csr_regfile$access_permitted_1_read_not_write),
.access_permitted_2_csr_addr(csr_regfile$access_permitted_2_csr_addr),
.access_permitted_2_priv(csr_regfile$access_permitted_2_priv),
.access_permitted_2_read_not_write(csr_regfile$access_permitted_2_read_not_write),
.csr_counter_read_fault_csr_addr(csr_regfile$csr_counter_read_fault_csr_addr),
.csr_counter_read_fault_priv(csr_regfile$csr_counter_read_fault_priv),
.csr_ret_actions_from_priv(csr_regfile$csr_ret_actions_from_priv),
.csr_trap_actions_exc_code(csr_regfile$csr_trap_actions_exc_code),
.csr_trap_actions_from_priv(csr_regfile$csr_trap_actions_from_priv),
.csr_trap_actions_interrupt(csr_regfile$csr_trap_actions_interrupt),
.csr_trap_actions_nmi(csr_regfile$csr_trap_actions_nmi),
.csr_trap_actions_pc(csr_regfile$csr_trap_actions_pc),
.csr_trap_actions_xtval(csr_regfile$csr_trap_actions_xtval),
.interrupt_pending_cur_priv(csr_regfile$interrupt_pending_cur_priv),
.m_external_interrupt_req_set_not_clear(csr_regfile$m_external_interrupt_req_set_not_clear),
.mav_csr_write_csr_addr(csr_regfile$mav_csr_write_csr_addr),
.mav_csr_write_word(csr_regfile$mav_csr_write_word),
.mav_read_csr_csr_addr(csr_regfile$mav_read_csr_csr_addr),
.nmi_req_set_not_clear(csr_regfile$nmi_req_set_not_clear),
.read_csr_csr_addr(csr_regfile$read_csr_csr_addr),
.read_csr_port2_csr_addr(csr_regfile$read_csr_port2_csr_addr),
.s_external_interrupt_req_set_not_clear(csr_regfile$s_external_interrupt_req_set_not_clear),
.software_interrupt_req_set_not_clear(csr_regfile$software_interrupt_req_set_not_clear),
.timer_interrupt_req_set_not_clear(csr_regfile$timer_interrupt_req_set_not_clear),
.EN_server_reset_request_put(csr_regfile$EN_server_reset_request_put),
.EN_server_reset_response_get(csr_regfile$EN_server_reset_response_get),
.EN_mav_read_csr(csr_regfile$EN_mav_read_csr),
.EN_mav_csr_write(csr_regfile$EN_mav_csr_write),
.EN_csr_trap_actions(csr_regfile$EN_csr_trap_actions),
.EN_csr_ret_actions(csr_regfile$EN_csr_ret_actions),
.EN_csr_minstret_incr(csr_regfile$EN_csr_minstret_incr),
.EN_debug(csr_regfile$EN_debug),
.RDY_server_reset_request_put(csr_regfile$RDY_server_reset_request_put),
.RDY_server_reset_response_get(csr_regfile$RDY_server_reset_response_get),
.read_csr(csr_regfile$read_csr),
.read_csr_port2(),
.mav_read_csr(),
.mav_csr_write(),
.read_misa(csr_regfile$read_misa),
.read_mstatus(csr_regfile$read_mstatus),
.read_ustatus(),
.read_satp(csr_regfile$read_satp),
.csr_trap_actions(csr_regfile$csr_trap_actions),
.RDY_csr_trap_actions(),
.csr_ret_actions(csr_regfile$csr_ret_actions),
.RDY_csr_ret_actions(),
.read_csr_minstret(csr_regfile$read_csr_minstret),
.read_csr_mcycle(csr_regfile$read_csr_mcycle),
.read_csr_mtime(),
.access_permitted_1(csr_regfile$access_permitted_1),
.access_permitted_2(csr_regfile$access_permitted_2),
.csr_counter_read_fault(),
.csr_mip_read(),
.interrupt_pending(csr_regfile$interrupt_pending),
.wfi_resume(csr_regfile$wfi_resume),
.nmi_pending(csr_regfile$nmi_pending),
.RDY_debug());
// submodule f_reset_reqs
FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_reset_reqs$D_IN),
.ENQ(f_reset_reqs$ENQ),
.DEQ(f_reset_reqs$DEQ),
.CLR(f_reset_reqs$CLR),
.D_OUT(f_reset_reqs$D_OUT),
.FULL_N(f_reset_reqs$FULL_N),
.EMPTY_N(f_reset_reqs$EMPTY_N));
// submodule f_reset_rsps
FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(f_reset_rsps$D_IN),
.ENQ(f_reset_rsps$ENQ),
.DEQ(f_reset_rsps$DEQ),
.CLR(f_reset_rsps$CLR),
.D_OUT(f_reset_rsps$D_OUT),
.FULL_N(f_reset_rsps$FULL_N),
.EMPTY_N(f_reset_rsps$EMPTY_N));
// submodule gpr_regfile
mkGPR_RegFile gpr_regfile(.CLK(CLK),
.RST_N(RST_N),
.read_rs1_port2_rs1(gpr_regfile$read_rs1_port2_rs1),
.read_rs1_rs1(gpr_regfile$read_rs1_rs1),
.read_rs2_rs2(gpr_regfile$read_rs2_rs2),
.write_rd_rd(gpr_regfile$write_rd_rd),
.write_rd_rd_val(gpr_regfile$write_rd_rd_val),
.EN_server_reset_request_put(gpr_regfile$EN_server_reset_request_put),
.EN_server_reset_response_get(gpr_regfile$EN_server_reset_response_get),
.EN_write_rd(gpr_regfile$EN_write_rd),
.RDY_server_reset_request_put(gpr_regfile$RDY_server_reset_request_put),
.RDY_server_reset_response_get(gpr_regfile$RDY_server_reset_response_get),
.read_rs1(gpr_regfile$read_rs1),
.read_rs1_port2(),
.read_rs2(gpr_regfile$read_rs2));
// submodule near_mem
mkNear_Mem near_mem(.CLK(CLK),
.RST_N(RST_N),
.dmem_master_arready(near_mem$dmem_master_arready),
.dmem_master_awready(near_mem$dmem_master_awready),
.dmem_master_bid(near_mem$dmem_master_bid),
.dmem_master_bresp(near_mem$dmem_master_bresp),
.dmem_master_bvalid(near_mem$dmem_master_bvalid),
.dmem_master_rdata(near_mem$dmem_master_rdata),
.dmem_master_rid(near_mem$dmem_master_rid),
.dmem_master_rlast(near_mem$dmem_master_rlast),
.dmem_master_rresp(near_mem$dmem_master_rresp),
.dmem_master_rvalid(near_mem$dmem_master_rvalid),
.dmem_master_wready(near_mem$dmem_master_wready),
.dmem_req_addr(near_mem$dmem_req_addr),
.dmem_req_amo_funct7(near_mem$dmem_req_amo_funct7),
.dmem_req_f3(near_mem$dmem_req_f3),
.dmem_req_mstatus_MXR(near_mem$dmem_req_mstatus_MXR),
.dmem_req_op(near_mem$dmem_req_op),
.dmem_req_priv(near_mem$dmem_req_priv),
.dmem_req_satp(near_mem$dmem_req_satp),
.dmem_req_sstatus_SUM(near_mem$dmem_req_sstatus_SUM),
.dmem_req_store_value(near_mem$dmem_req_store_value),
.imem_master_arready(near_mem$imem_master_arready),
.imem_master_awready(near_mem$imem_master_awready),
.imem_master_bid(near_mem$imem_master_bid),
.imem_master_bresp(near_mem$imem_master_bresp),
.imem_master_bvalid(near_mem$imem_master_bvalid),
.imem_master_rdata(near_mem$imem_master_rdata),
.imem_master_rid(near_mem$imem_master_rid),
.imem_master_rlast(near_mem$imem_master_rlast),
.imem_master_rresp(near_mem$imem_master_rresp),
.imem_master_rvalid(near_mem$imem_master_rvalid),
.imem_master_wready(near_mem$imem_master_wready),
.imem_req_addr(near_mem$imem_req_addr),
.imem_req_f3(near_mem$imem_req_f3),
.imem_req_mstatus_MXR(near_mem$imem_req_mstatus_MXR),
.imem_req_priv(near_mem$imem_req_priv),
.imem_req_satp(near_mem$imem_req_satp),
.imem_req_sstatus_SUM(near_mem$imem_req_sstatus_SUM),
.server_fence_request_put(near_mem$server_fence_request_put),
.EN_server_reset_request_put(near_mem$EN_server_reset_request_put),
.EN_server_reset_response_get(near_mem$EN_server_reset_response_get),
.EN_imem_req(near_mem$EN_imem_req),
.EN_dmem_req(near_mem$EN_dmem_req),
.EN_server_fence_i_request_put(near_mem$EN_server_fence_i_request_put),
.EN_server_fence_i_response_get(near_mem$EN_server_fence_i_response_get),
.EN_server_fence_request_put(near_mem$EN_server_fence_request_put),
.EN_server_fence_response_get(near_mem$EN_server_fence_response_get),
.EN_sfence_vma(near_mem$EN_sfence_vma),
.RDY_server_reset_request_put(near_mem$RDY_server_reset_request_put),
.RDY_server_reset_response_get(near_mem$RDY_server_reset_response_get),
.imem_valid(near_mem$imem_valid),
.imem_is_i32_not_i16(near_mem$imem_is_i32_not_i16),
.imem_pc(near_mem$imem_pc),
.imem_instr(near_mem$imem_instr),
.imem_exc(near_mem$imem_exc),
.imem_exc_code(near_mem$imem_exc_code),
.imem_tval(),
.imem_master_awvalid(near_mem$imem_master_awvalid),
.imem_master_awid(near_mem$imem_master_awid),
.imem_master_awaddr(near_mem$imem_master_awaddr),
.imem_master_awlen(near_mem$imem_master_awlen),
.imem_master_awsize(near_mem$imem_master_awsize),
.imem_master_awburst(near_mem$imem_master_awburst),
.imem_master_awlock(near_mem$imem_master_awlock),
.imem_master_awcache(near_mem$imem_master_awcache),
.imem_master_awprot(near_mem$imem_master_awprot),
.imem_master_awqos(near_mem$imem_master_awqos),
.imem_master_awregion(near_mem$imem_master_awregion),
.imem_master_wvalid(near_mem$imem_master_wvalid),
.imem_master_wdata(near_mem$imem_master_wdata),
.imem_master_wstrb(near_mem$imem_master_wstrb),
.imem_master_wlast(near_mem$imem_master_wlast),
.imem_master_bready(near_mem$imem_master_bready),
.imem_master_arvalid(near_mem$imem_master_arvalid),
.imem_master_arid(near_mem$imem_master_arid),
.imem_master_araddr(near_mem$imem_master_araddr),
.imem_master_arlen(near_mem$imem_master_arlen),
.imem_master_arsize(near_mem$imem_master_arsize),
.imem_master_arburst(near_mem$imem_master_arburst),
.imem_master_arlock(near_mem$imem_master_arlock),
.imem_master_arcache(near_mem$imem_master_arcache),
.imem_master_arprot(near_mem$imem_master_arprot),
.imem_master_arqos(near_mem$imem_master_arqos),
.imem_master_arregion(near_mem$imem_master_arregion),
.imem_master_rready(near_mem$imem_master_rready),
.dmem_valid(near_mem$dmem_valid),
.dmem_word64(near_mem$dmem_word64),
.dmem_st_amo_val(),
.dmem_exc(near_mem$dmem_exc),
.dmem_exc_code(near_mem$dmem_exc_code),
.dmem_master_awvalid(near_mem$dmem_master_awvalid),
.dmem_master_awid(near_mem$dmem_master_awid),
.dmem_master_awaddr(near_mem$dmem_master_awaddr),
.dmem_master_awlen(near_mem$dmem_master_awlen),
.dmem_master_awsize(near_mem$dmem_master_awsize),
.dmem_master_awburst(near_mem$dmem_master_awburst),
.dmem_master_awlock(near_mem$dmem_master_awlock),
.dmem_master_awcache(near_mem$dmem_master_awcache),
.dmem_master_awprot(near_mem$dmem_master_awprot),
.dmem_master_awqos(near_mem$dmem_master_awqos),
.dmem_master_awregion(near_mem$dmem_master_awregion),
.dmem_master_wvalid(near_mem$dmem_master_wvalid),
.dmem_master_wdata(near_mem$dmem_master_wdata),
.dmem_master_wstrb(near_mem$dmem_master_wstrb),
.dmem_master_wlast(near_mem$dmem_master_wlast),
.dmem_master_bready(near_mem$dmem_master_bready),
.dmem_master_arvalid(near_mem$dmem_master_arvalid),
.dmem_master_arid(near_mem$dmem_master_arid),
.dmem_master_araddr(near_mem$dmem_master_araddr),
.dmem_master_arlen(near_mem$dmem_master_arlen),
.dmem_master_arsize(near_mem$dmem_master_arsize),
.dmem_master_arburst(near_mem$dmem_master_arburst),
.dmem_master_arlock(near_mem$dmem_master_arlock),
.dmem_master_arcache(near_mem$dmem_master_arcache),
.dmem_master_arprot(near_mem$dmem_master_arprot),
.dmem_master_arqos(near_mem$dmem_master_arqos),
.dmem_master_arregion(near_mem$dmem_master_arregion),
.dmem_master_rready(near_mem$dmem_master_rready),
.RDY_server_fence_i_request_put(near_mem$RDY_server_fence_i_request_put),
.RDY_server_fence_i_response_get(near_mem$RDY_server_fence_i_response_get),
.RDY_server_fence_request_put(near_mem$RDY_server_fence_request_put),
.RDY_server_fence_response_get(near_mem$RDY_server_fence_response_get),
.RDY_sfence_vma());
// submodule soc_map
mkSoC_Map soc_map(.CLK(CLK),
.RST_N(RST_N),
.m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
.m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
.m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
.m_near_mem_io_addr_base(),
.m_near_mem_io_addr_size(),
.m_near_mem_io_addr_lim(),
.m_plic_addr_base(),
.m_plic_addr_size(),
.m_plic_addr_lim(),
.m_uart0_addr_base(),
.m_uart0_addr_size(),
.m_uart0_addr_lim(),
.m_boot_rom_addr_base(),
.m_boot_rom_addr_size(),
.m_boot_rom_addr_lim(),
.m_mem0_controller_addr_base(),
.m_mem0_controller_addr_size(),
.m_mem0_controller_addr_lim(),
.m_tcm_addr_base(),
.m_tcm_addr_size(),
.m_tcm_addr_lim(),
.m_is_mem_addr(),
.m_is_IO_addr(),
.m_is_near_mem_IO_addr(),
.m_pc_reset_value(soc_map$m_pc_reset_value),
.m_mtvec_reset_value(),
.m_nmivec_reset_value());
// submodule stage1_f_reset_reqs
FIFO20 #(.guarded(32'd1)) stage1_f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.ENQ(stage1_f_reset_reqs$ENQ),
.DEQ(stage1_f_reset_reqs$DEQ),
.CLR(stage1_f_reset_reqs$CLR),
.FULL_N(stage1_f_reset_reqs$FULL_N),
.EMPTY_N(stage1_f_reset_reqs$EMPTY_N));
// submodule stage1_f_reset_rsps
FIFO20 #(.guarded(32'd1)) stage1_f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(stage1_f_reset_rsps$ENQ),
.DEQ(stage1_f_reset_rsps$DEQ),
.CLR(stage1_f_reset_rsps$CLR),
.FULL_N(stage1_f_reset_rsps$FULL_N),
.EMPTY_N(stage1_f_reset_rsps$EMPTY_N));
// submodule stage2_f_reset_reqs
FIFO20 #(.guarded(32'd1)) stage2_f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.ENQ(stage2_f_reset_reqs$ENQ),
.DEQ(stage2_f_reset_reqs$DEQ),
.CLR(stage2_f_reset_reqs$CLR),
.FULL_N(stage2_f_reset_reqs$FULL_N),
.EMPTY_N(stage2_f_reset_reqs$EMPTY_N));
// submodule stage2_f_reset_rsps
FIFO20 #(.guarded(32'd1)) stage2_f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(stage2_f_reset_rsps$ENQ),
.DEQ(stage2_f_reset_rsps$DEQ),
.CLR(stage2_f_reset_rsps$CLR),
.FULL_N(stage2_f_reset_rsps$FULL_N),
.EMPTY_N(stage2_f_reset_rsps$EMPTY_N));
// submodule stage2_mbox
mkRISCV_MBox stage2_mbox(.CLK(CLK),
.RST_N(RST_N),
.req_f3(stage2_mbox$req_f3),
.req_is_OP_not_OP_32(stage2_mbox$req_is_OP_not_OP_32),
.req_v1(stage2_mbox$req_v1),
.req_v2(stage2_mbox$req_v2),
.set_verbosity_verbosity(stage2_mbox$set_verbosity_verbosity),
.EN_set_verbosity(stage2_mbox$EN_set_verbosity),
.EN_req_reset(stage2_mbox$EN_req_reset),
.EN_rsp_reset(stage2_mbox$EN_rsp_reset),
.EN_req(stage2_mbox$EN_req),
.RDY_set_verbosity(),
.RDY_req_reset(),
.RDY_rsp_reset(),
.valid(stage2_mbox$valid),
.word(stage2_mbox$word));
// submodule stage3_f_reset_reqs
FIFO20 #(.guarded(32'd1)) stage3_f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.ENQ(stage3_f_reset_reqs$ENQ),
.DEQ(stage3_f_reset_reqs$DEQ),
.CLR(stage3_f_reset_reqs$CLR),
.FULL_N(stage3_f_reset_reqs$FULL_N),
.EMPTY_N(stage3_f_reset_reqs$EMPTY_N));
// submodule stage3_f_reset_rsps
FIFO20 #(.guarded(32'd1)) stage3_f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(stage3_f_reset_rsps$ENQ),
.DEQ(stage3_f_reset_rsps$DEQ),
.CLR(stage3_f_reset_rsps$CLR),
.FULL_N(stage3_f_reset_rsps$FULL_N),
.EMPTY_N(stage3_f_reset_rsps$EMPTY_N));
// submodule stageD_f_reset_reqs
FIFO20 #(.guarded(32'd1)) stageD_f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.ENQ(stageD_f_reset_reqs$ENQ),
.DEQ(stageD_f_reset_reqs$DEQ),
.CLR(stageD_f_reset_reqs$CLR),
.FULL_N(stageD_f_reset_reqs$FULL_N),
.EMPTY_N(stageD_f_reset_reqs$EMPTY_N));
// submodule stageD_f_reset_rsps
FIFO20 #(.guarded(32'd1)) stageD_f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(stageD_f_reset_rsps$ENQ),
.DEQ(stageD_f_reset_rsps$DEQ),
.CLR(stageD_f_reset_rsps$CLR),
.FULL_N(stageD_f_reset_rsps$FULL_N),
.EMPTY_N(stageD_f_reset_rsps$EMPTY_N));
// submodule stageF_branch_predictor
mkBranch_Predictor stageF_branch_predictor(.CLK(CLK),
.RST_N(RST_N),
.bp_train_cf_info(stageF_branch_predictor$bp_train_cf_info),
.bp_train_instr(stageF_branch_predictor$bp_train_instr),
.bp_train_is_i32_not_i16(stageF_branch_predictor$bp_train_is_i32_not_i16),
.bp_train_pc(stageF_branch_predictor$bp_train_pc),
.predict_req_pc(stageF_branch_predictor$predict_req_pc),
.predict_rsp_instr(stageF_branch_predictor$predict_rsp_instr),
.predict_rsp_is_i32_not_i16(stageF_branch_predictor$predict_rsp_is_i32_not_i16),
.EN_reset(stageF_branch_predictor$EN_reset),
.EN_predict_req(stageF_branch_predictor$EN_predict_req),
.EN_bp_train(stageF_branch_predictor$EN_bp_train),
.RDY_reset(),
.RDY_predict_req(stageF_branch_predictor$RDY_predict_req),
.predict_rsp(stageF_branch_predictor$predict_rsp),
.RDY_bp_train());
// submodule stageF_f_reset_reqs
FIFO20 #(.guarded(32'd1)) stageF_f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.ENQ(stageF_f_reset_reqs$ENQ),
.DEQ(stageF_f_reset_reqs$DEQ),
.CLR(stageF_f_reset_reqs$CLR),
.FULL_N(stageF_f_reset_reqs$FULL_N),
.EMPTY_N(stageF_f_reset_reqs$EMPTY_N));
// submodule stageF_f_reset_rsps
FIFO20 #(.guarded(32'd1)) stageF_f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(stageF_f_reset_rsps$ENQ),
.DEQ(stageF_f_reset_rsps$DEQ),
.CLR(stageF_f_reset_rsps$CLR),
.FULL_N(stageF_f_reset_rsps$FULL_N),
.EMPTY_N(stageF_f_reset_rsps$EMPTY_N));
// rule RL_rl_show_pipe
assign CAN_FIRE_RL_rl_show_pipe =
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49 &&
rg_state != 4'd0 &&
rg_state != 4'd1 &&
rg_state != 4'd12 ;
assign WILL_FIRE_RL_rl_show_pipe = CAN_FIRE_RL_rl_show_pipe ;
// rule RL_rl_stage2_nonpipe
assign CAN_FIRE_RL_rl_stage2_nonpipe =
rg_state == 4'd3 && !stage3_rg_full &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 ==
2'd3 ;
assign WILL_FIRE_RL_rl_stage2_nonpipe = CAN_FIRE_RL_rl_stage2_nonpipe ;
// rule RL_rl_stage1_trap
assign CAN_FIRE_RL_rl_stage1_trap =
rg_state_0_EQ_3_544_AND_NOT_csr_regfile_interr_ETC___d1750 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 ==
4'd12 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1347) ;
assign WILL_FIRE_RL_rl_stage1_trap = CAN_FIRE_RL_rl_stage1_trap ;
// rule RL_rl_trap
assign CAN_FIRE_RL_rl_trap =
rg_state == 4'd4 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1347) ;
assign WILL_FIRE_RL_rl_trap = CAN_FIRE_RL_rl_trap ;
// rule RL_rl_stage1_CSRR_W
assign CAN_FIRE_RL_rl_stage1_CSRR_W = MUX_rg_state$write_1__SEL_10 ;
assign WILL_FIRE_RL_rl_stage1_CSRR_W = MUX_rg_state$write_1__SEL_10 ;
// rule RL_rl_stage1_CSRR_W_2
assign CAN_FIRE_RL_rl_stage1_CSRR_W_2 = rg_state == 4'd6 ;
assign WILL_FIRE_RL_rl_stage1_CSRR_W_2 = rg_state == 4'd6 ;
// rule RL_rl_stage1_CSRR_S_or_C
assign CAN_FIRE_RL_rl_stage1_CSRR_S_or_C = MUX_rg_state$write_1__SEL_11 ;
assign WILL_FIRE_RL_rl_stage1_CSRR_S_or_C = MUX_rg_state$write_1__SEL_11 ;
// rule RL_rl_stage1_CSRR_S_or_C_2
assign CAN_FIRE_RL_rl_stage1_CSRR_S_or_C_2 = rg_state == 4'd7 ;
assign WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 = rg_state == 4'd7 ;
// rule RL_rl_stage1_restart_after_csrrx
assign CAN_FIRE_RL_rl_stage1_restart_after_csrrx =
imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d1477 &&
stageF_branch_predictor$RDY_predict_req &&
rg_state_0_EQ_8_834_AND_NOT_stageF_rg_full_324_ETC___d1835 ;
assign WILL_FIRE_RL_rl_stage1_restart_after_csrrx =
CAN_FIRE_RL_rl_stage1_restart_after_csrrx ;
// rule RL_rl_stage1_xRET
assign CAN_FIRE_RL_rl_stage1_xRET =
rg_state_0_EQ_3_544_AND_NOT_csr_regfile_interr_ETC___d1750 &&
(IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 ==
4'd8 ||
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 ==
4'd9 ||
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 ==
4'd10) &&
(!stageF_rg_full ||
near_mem$imem_valid &&
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1347) ;
assign WILL_FIRE_RL_rl_stage1_xRET = CAN_FIRE_RL_rl_stage1_xRET ;
// rule RL_rl_stage1_FENCE_I
assign CAN_FIRE_RL_rl_stage1_FENCE_I = MUX_rg_state$write_1__SEL_12 ;
assign WILL_FIRE_RL_rl_stage1_FENCE_I = MUX_rg_state$write_1__SEL_12 ;
// rule RL_rl_finish_FENCE_I
assign CAN_FIRE_RL_rl_finish_FENCE_I =
imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d1477 &&
stageF_branch_predictor$RDY_predict_req &&
near_mem$RDY_server_fence_i_response_get &&
rg_state == 4'd9 ;
assign WILL_FIRE_RL_rl_finish_FENCE_I = CAN_FIRE_RL_rl_finish_FENCE_I ;
// rule RL_rl_stage1_FENCE
assign CAN_FIRE_RL_rl_stage1_FENCE = MUX_rg_state$write_1__SEL_13 ;
assign WILL_FIRE_RL_rl_stage1_FENCE = MUX_rg_state$write_1__SEL_13 ;
// rule RL_rl_finish_FENCE
assign CAN_FIRE_RL_rl_finish_FENCE =
imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d1477 &&
stageF_branch_predictor$RDY_predict_req &&
near_mem$RDY_server_fence_response_get &&
rg_state == 4'd10 ;
assign WILL_FIRE_RL_rl_finish_FENCE = CAN_FIRE_RL_rl_finish_FENCE ;
// rule RL_rl_stage1_SFENCE_VMA
assign CAN_FIRE_RL_rl_stage1_SFENCE_VMA =
rg_state_0_EQ_3_544_AND_NOT_csr_regfile_interr_ETC___d1750 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 ==
4'd7 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1347) ;
assign WILL_FIRE_RL_rl_stage1_SFENCE_VMA =
CAN_FIRE_RL_rl_stage1_SFENCE_VMA ;
// rule RL_rl_finish_SFENCE_VMA
assign CAN_FIRE_RL_rl_finish_SFENCE_VMA =
imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d1477 &&
stageF_branch_predictor$RDY_predict_req &&
rg_state == 4'd11 ;
assign WILL_FIRE_RL_rl_finish_SFENCE_VMA =
CAN_FIRE_RL_rl_finish_SFENCE_VMA ;
// rule RL_rl_stage1_WFI
assign CAN_FIRE_RL_rl_stage1_WFI =
rg_state_0_EQ_3_544_AND_NOT_csr_regfile_interr_ETC___d1750 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 ==
4'd11 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1347) ;
assign WILL_FIRE_RL_rl_stage1_WFI = CAN_FIRE_RL_rl_stage1_WFI ;
// rule RL_rl_WFI_resume
assign CAN_FIRE_RL_rl_WFI_resume =
imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d1477 &&
stageF_branch_predictor$RDY_predict_req &&
rg_state_0_EQ_12_7_AND_csr_regfile_wfi_resume__ETC___d1885 ;
assign WILL_FIRE_RL_rl_WFI_resume = CAN_FIRE_RL_rl_WFI_resume ;
// rule RL_rl_reset_from_WFI
assign CAN_FIRE_RL_rl_reset_from_WFI =
rg_state == 4'd12 && f_reset_reqs$EMPTY_N ;
assign WILL_FIRE_RL_rl_reset_from_WFI = MUX_rg_state$write_1__SEL_5 ;
// rule RL_rl_trap_fetch
assign CAN_FIRE_RL_rl_trap_fetch =
imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d1477 &&
stageF_branch_predictor$RDY_predict_req &&
rg_state_0_EQ_5_889_AND_NOT_stageF_rg_full_324_ETC___d1890 ;
assign WILL_FIRE_RL_rl_trap_fetch = CAN_FIRE_RL_rl_trap_fetch ;
// rule RL_rl_stage1_interrupt
assign CAN_FIRE_RL_rl_stage1_interrupt =
(csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) &&
rg_state == 4'd3 &&
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d1898 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1347) ;
assign WILL_FIRE_RL_rl_stage1_interrupt = CAN_FIRE_RL_rl_stage1_interrupt ;
// rule RL_imem_rl_assert_fail
assign CAN_FIRE_RL_imem_rl_assert_fail = !near_mem$imem_is_i32_not_i16 ;
assign WILL_FIRE_RL_imem_rl_assert_fail = CAN_FIRE_RL_imem_rl_assert_fail ;
// rule RL_rl_reset_complete
assign CAN_FIRE_RL_rl_reset_complete =
gpr_regfile$RDY_server_reset_response_get &&
near_mem$RDY_server_reset_response_get &&
csr_regfile_RDY_server_reset_response_get__466_ETC___d1487 &&
rg_state == 4'd1 ;
assign WILL_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_2 ;
// rule RL_rl_pipe
assign CAN_FIRE_RL_rl_pipe =
(IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1532 ||
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1542) &&
rg_state_0_EQ_3_544_AND_stage3_rg_full_1_OR_NO_ETC___d1554 &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1564 ;
assign WILL_FIRE_RL_rl_pipe =
CAN_FIRE_RL_rl_pipe && !WILL_FIRE_RL_imem_rl_fetch_next_32b ;
// rule RL_rl_reset_start
assign CAN_FIRE_RL_rl_reset_start =
gpr_regfile$RDY_server_reset_request_put &&
near_mem$RDY_server_reset_request_put &&
csr_regfile_RDY_server_reset_request_put__447__ETC___d1459 &&
rg_state == 4'd0 ;
assign WILL_FIRE_RL_rl_reset_start = CAN_FIRE_RL_rl_reset_start ;
// rule RL_imem_rl_fetch_next_32b
assign CAN_FIRE_RL_imem_rl_fetch_next_32b =
near_mem$imem_valid && imem_rg_pc[1:0] != 2'b0 &&
imem_rg_pc_BITS_63_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 &&
near_mem$imem_instr[17:16] == 2'b11 ;
assign WILL_FIRE_RL_imem_rl_fetch_next_32b =
CAN_FIRE_RL_imem_rl_fetch_next_32b ;
// rule RL_stage3_rl_reset
assign CAN_FIRE_RL_stage3_rl_reset =
stage3_f_reset_reqs$EMPTY_N && stage3_f_reset_rsps$FULL_N ;
assign WILL_FIRE_RL_stage3_rl_reset = CAN_FIRE_RL_stage3_rl_reset ;
// rule RL_stage2_rl_reset_end
assign CAN_FIRE_RL_stage2_rl_reset_end =
stage2_f_reset_rsps$FULL_N && stage2_rg_resetting ;
assign WILL_FIRE_RL_stage2_rl_reset_end = CAN_FIRE_RL_stage2_rl_reset_end ;
// rule RL_stage2_rl_reset_begin
assign CAN_FIRE_RL_stage2_rl_reset_begin = stage2_f_reset_reqs$EMPTY_N ;
assign WILL_FIRE_RL_stage2_rl_reset_begin = stage2_f_reset_reqs$EMPTY_N ;
// rule RL_stage1_rl_reset
assign CAN_FIRE_RL_stage1_rl_reset =
stage1_f_reset_reqs$EMPTY_N && stage1_f_reset_rsps$FULL_N ;
assign WILL_FIRE_RL_stage1_rl_reset = CAN_FIRE_RL_stage1_rl_reset ;
// rule RL_stageD_rl_reset
assign CAN_FIRE_RL_stageD_rl_reset =
stageD_f_reset_reqs$EMPTY_N && stageD_f_reset_rsps$FULL_N ;
assign WILL_FIRE_RL_stageD_rl_reset = CAN_FIRE_RL_stageD_rl_reset ;
// rule RL_stageF_rl_reset
assign CAN_FIRE_RL_stageF_rl_reset =
stageF_f_reset_reqs$EMPTY_N && stageF_f_reset_rsps$FULL_N ;
assign WILL_FIRE_RL_stageF_rl_reset = CAN_FIRE_RL_stageF_rl_reset ;
// inputs to muxes for submodule ports
assign MUX_csr_regfile$mav_csr_write_1__SEL_1 =
WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
csr_regfile$access_permitted_1 ;
assign MUX_gpr_regfile$write_rd_1__SEL_3 =
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
csr_regfile$access_permitted_2 ;
assign MUX_imem_rg_cache_addr$write_1__SEL_3 =
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1703 ;
assign MUX_imem_rg_f3$write_1__SEL_1 =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ;
assign MUX_rg_next_pc$write_1__SEL_1 =
WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1640 ;
assign MUX_rg_next_pc$write_1__SEL_2 =
WILL_FIRE_RL_rl_stage1_WFI || WILL_FIRE_RL_rl_stage1_FENCE ||
WILL_FIRE_RL_rl_stage1_FENCE_I ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_stage1_SFENCE_VMA ;
assign MUX_rg_state$write_1__SEL_1 =
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1691 ;
assign MUX_rg_state$write_1__SEL_2 =
CAN_FIRE_RL_rl_reset_complete &&
!WILL_FIRE_RL_imem_rl_fetch_next_32b ;
assign MUX_rg_state$write_1__SEL_5 =
CAN_FIRE_RL_rl_reset_from_WFI && !WILL_FIRE_RL_rl_WFI_resume ;
assign MUX_rg_state$write_1__SEL_7 =
WILL_FIRE_RL_rl_trap_fetch || WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
assign MUX_rg_state$write_1__SEL_8 =
WILL_FIRE_RL_rl_stage1_interrupt ||
WILL_FIRE_RL_rl_stage1_trap ||
WILL_FIRE_RL_rl_stage2_nonpipe ;
assign MUX_rg_state$write_1__SEL_9 =
WILL_FIRE_RL_rl_stage1_xRET || WILL_FIRE_RL_rl_trap ;
assign MUX_rg_state$write_1__SEL_10 =
rg_state_0_EQ_3_544_AND_NOT_csr_regfile_interr_ETC___d1750 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 ==
4'd3 ;
assign MUX_rg_state$write_1__SEL_11 =
rg_state_0_EQ_3_544_AND_NOT_csr_regfile_interr_ETC___d1750 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 ==
4'd4 ;
assign MUX_rg_state$write_1__SEL_12 =
near_mem$RDY_server_fence_i_request_put &&
rg_state_0_EQ_3_544_AND_NOT_csr_regfile_interr_ETC___d1861 ;
assign MUX_rg_state$write_1__SEL_13 =
near_mem$RDY_server_fence_request_put &&
rg_state_0_EQ_3_544_AND_NOT_csr_regfile_interr_ETC___d1870 ;
assign MUX_rg_trap_info$write_1__SEL_1 =
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ;
assign MUX_rg_trap_instr$write_1__SEL_1 =
WILL_FIRE_RL_rl_stage1_interrupt ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_stage1_trap ;
assign MUX_rg_trap_interrupt$write_1__SEL_1 =
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_stage1_trap ||
WILL_FIRE_RL_rl_stage2_nonpipe ;
always@(rg_trap_instr or
csr_regfile$read_csr or
y__h24168 or
IF_csr_regfile_read_csr_rg_trap_instr_771_BITS_ETC___d1826)
begin
case (rg_trap_instr[14:12])
3'b010, 3'b110:
MUX_csr_regfile$mav_csr_write_2__VAL_2 =
IF_csr_regfile_read_csr_rg_trap_instr_771_BITS_ETC___d1826;
default: MUX_csr_regfile$mav_csr_write_2__VAL_2 =
csr_regfile$read_csr[63:0] & y__h24168;
endcase
end
assign MUX_imem_rg_tval$write_1__VAL_4 = near_mem$imem_pc + 64'd4 ;
assign MUX_near_mem$imem_req_2__VAL_1 =
NOT_soc_map_m_pc_reset_value__492_BITS_1_TO_0__ETC___d1505 ?
addr_of_b32___1__h18620 :
addr_of_b32__h18508 ;
assign MUX_near_mem$imem_req_2__VAL_2 =
NOT_stageF_branch_predictor_predict_rsp_NOT_im_ETC___d1712 ?
addr_of_b32___1__h21691 :
addr_of_b32__h21579 ;
assign MUX_near_mem$imem_req_2__VAL_4 =
NOT_rg_next_pc_837_BITS_1_TO_0_838_EQ_0b0_839__ETC___d1846 ?
addr_of_b32___1__h30871 :
addr_of_b32__h30759 ;
assign MUX_rg_state$write_1__VAL_2 = rg_run_on_reset ? 4'd3 : 4'd2 ;
assign MUX_rg_state$write_1__VAL_3 =
csr_regfile$access_permitted_1 ? 4'd8 : 4'd4 ;
assign MUX_rg_state$write_1__VAL_4 =
csr_regfile$access_permitted_2 ? 4'd8 : 4'd4 ;
assign MUX_rg_trap_info$write_1__VAL_1 =
{ stage1_rg_stage_input[401:338], 4'd2, value__h9576 } ;
assign MUX_rg_trap_info$write_1__VAL_2 =
{ stage2_rg_stage2[295:232],
near_mem$dmem_exc_code,
stage2_rg_stage2[191:128] } ;
assign MUX_rg_trap_info$write_1__VAL_3 =
{ stage1_rg_stage_input[401:338],
stage1_rg_stage_input[332] ?
stage1_rg_stage_input[331:264] :
{ alu_outputs_exc_code__h8364, trap_info_tval__h9527 } } ;
assign MUX_rg_trap_info$write_1__VAL_4 =
{ stage1_rg_stage_input[401:338], x_exc_code__h31121, 64'd0 } ;
assign MUX_rg_trap_instr$write_1__VAL_1 = stage1_rg_stage_input[263:232] ;
assign MUX_stage1_rg_full$write_1__VAL_2 =
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1643 &&
stageD_rg_full ||
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1727 ;
assign MUX_stage2_rg_full$write_1__VAL_2 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1525 ?
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 !=
4'd0 &&
IF_NOT_stage1_rg_full_03_87_OR_NOT_stage1_rg_s_ETC___d1591 :
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 !=
2'd2 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 !=
2'd0 ;
assign MUX_stageD_rg_full$write_1__VAL_2 =
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1684 ||
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1529 &&
stageD_rg_full ;
assign MUX_stageF_rg_full$write_1__VAL_2 =
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1684 ?
csr_regfile_interrupt_pending_rg_cur_priv_1_50_ETC___d1736 :
(IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1529 &&
stageD_rg_full ||
!near_mem$imem_valid ||
imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1341) &&
stageF_rg_full ;
// register cfg_logdelay
assign cfg_logdelay$D_IN = set_verbosity_logdelay ;
assign cfg_logdelay$EN = EN_set_verbosity ;
// register cfg_verbosity
assign cfg_verbosity$D_IN = set_verbosity_verbosity ;
assign cfg_verbosity$EN = EN_set_verbosity ;
// register imem_rg_cache_addr
assign imem_rg_cache_addr$D_IN = near_mem$imem_pc ;
assign imem_rg_cache_addr$EN =
MUX_rg_state$write_1__SEL_7 && near_mem$imem_valid ||
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
near_mem$imem_valid ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1703 ||
WILL_FIRE_RL_imem_rl_fetch_next_32b ;
// register imem_rg_cache_b16
assign imem_rg_cache_b16$D_IN = near_mem$imem_instr[31:16] ;
assign imem_rg_cache_b16$EN =
MUX_rg_state$write_1__SEL_7 && near_mem$imem_valid ||
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
near_mem$imem_valid ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1703 ||
WILL_FIRE_RL_imem_rl_fetch_next_32b ;
// register imem_rg_f3
assign imem_rg_f3$D_IN = 3'b010 ;
assign imem_rg_f3$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1703 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register imem_rg_mstatus_MXR
assign imem_rg_mstatus_MXR$D_IN = csr_regfile$read_mstatus[19] ;
assign imem_rg_mstatus_MXR$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1703 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register imem_rg_pc
always@(MUX_imem_rg_f3$write_1__SEL_1 or
soc_map$m_pc_reset_value or
MUX_imem_rg_cache_addr$write_1__SEL_3 or
stageF_branch_predictor$predict_rsp or
MUX_rg_state$write_1__SEL_7 or rg_next_pc)
begin
case (1'b1) // synopsys parallel_case
MUX_imem_rg_f3$write_1__SEL_1:
imem_rg_pc$D_IN = soc_map$m_pc_reset_value;
MUX_imem_rg_cache_addr$write_1__SEL_3:
imem_rg_pc$D_IN = stageF_branch_predictor$predict_rsp;
MUX_rg_state$write_1__SEL_7: imem_rg_pc$D_IN = rg_next_pc;
default: imem_rg_pc$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign imem_rg_pc$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1703 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register imem_rg_priv
assign imem_rg_priv$D_IN = rg_cur_priv ;
assign imem_rg_priv$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1703 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register imem_rg_satp
assign imem_rg_satp$D_IN = csr_regfile$read_satp ;
assign imem_rg_satp$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1703 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register imem_rg_sstatus_SUM
assign imem_rg_sstatus_SUM$D_IN = 1'd0 ;
assign imem_rg_sstatus_SUM$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1703 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register imem_rg_tval
always@(MUX_imem_rg_f3$write_1__SEL_1 or
soc_map$m_pc_reset_value or
MUX_imem_rg_cache_addr$write_1__SEL_3 or
stageF_branch_predictor$predict_rsp or
MUX_rg_state$write_1__SEL_7 or
rg_next_pc or
WILL_FIRE_RL_imem_rl_fetch_next_32b or
MUX_imem_rg_tval$write_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_imem_rg_f3$write_1__SEL_1:
imem_rg_tval$D_IN = soc_map$m_pc_reset_value;
MUX_imem_rg_cache_addr$write_1__SEL_3:
imem_rg_tval$D_IN = stageF_branch_predictor$predict_rsp;
MUX_rg_state$write_1__SEL_7: imem_rg_tval$D_IN = rg_next_pc;
WILL_FIRE_RL_imem_rl_fetch_next_32b:
imem_rg_tval$D_IN = MUX_imem_rg_tval$write_1__VAL_4;
default: imem_rg_tval$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign imem_rg_tval$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1703 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_imem_rl_fetch_next_32b ;
// register rg_csr_pc
assign rg_csr_pc$D_IN = stage1_rg_stage_input[401:338] ;
assign rg_csr_pc$EN = MUX_rg_trap_info$write_1__SEL_1 ;
// register rg_csr_val1
assign rg_csr_val1$D_IN = x_out_data_to_stage2_val1__h7709 ;
assign rg_csr_val1$EN = MUX_rg_trap_info$write_1__SEL_1 ;
// register rg_cur_priv
always@(WILL_FIRE_RL_rl_trap or
csr_regfile$csr_trap_actions or
WILL_FIRE_RL_rl_stage1_xRET or
csr_regfile$csr_ret_actions or WILL_FIRE_RL_rl_reset_start)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_rl_trap:
rg_cur_priv$D_IN = csr_regfile$csr_trap_actions[1:0];
WILL_FIRE_RL_rl_stage1_xRET:
rg_cur_priv$D_IN = csr_regfile$csr_ret_actions[65:64];
WILL_FIRE_RL_rl_reset_start: rg_cur_priv$D_IN = 2'b11;
default: rg_cur_priv$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign rg_cur_priv$EN =
WILL_FIRE_RL_rl_trap || WILL_FIRE_RL_rl_stage1_xRET ||
WILL_FIRE_RL_rl_reset_start ;
// register rg_epoch
always@(MUX_imem_rg_f3$write_1__SEL_1 or
new_epoch__h18044 or
MUX_rg_state$write_1__SEL_7 or WILL_FIRE_RL_rl_reset_start)
begin
case (1'b1) // synopsys parallel_case
MUX_imem_rg_f3$write_1__SEL_1: rg_epoch$D_IN = new_epoch__h18044;
MUX_rg_state$write_1__SEL_7: rg_epoch$D_IN = new_epoch__h18044;
WILL_FIRE_RL_rl_reset_start: rg_epoch$D_IN = 2'd0;
default: rg_epoch$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign rg_epoch$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_rl_reset_start ;
// register rg_mstatus_MXR
assign rg_mstatus_MXR$D_IN = csr_regfile$read_mstatus[19] ;
assign rg_mstatus_MXR$EN = MUX_rg_state$write_1__SEL_9 ;
// register rg_next_pc
always@(MUX_rg_next_pc$write_1__SEL_1 or
x_out_next_pc__h7665 or
MUX_rg_next_pc$write_1__SEL_2 or
WILL_FIRE_RL_rl_trap or
csr_regfile$csr_trap_actions or
WILL_FIRE_RL_rl_stage1_xRET or csr_regfile$csr_ret_actions)
begin
case (1'b1) // synopsys parallel_case
MUX_rg_next_pc$write_1__SEL_1: rg_next_pc$D_IN = x_out_next_pc__h7665;
MUX_rg_next_pc$write_1__SEL_2: rg_next_pc$D_IN = x_out_next_pc__h7665;
WILL_FIRE_RL_rl_trap:
rg_next_pc$D_IN = csr_regfile$csr_trap_actions[193:130];
WILL_FIRE_RL_rl_stage1_xRET:
rg_next_pc$D_IN = csr_regfile$csr_ret_actions[129:66];
default: rg_next_pc$D_IN =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign rg_next_pc$EN =
WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1640 ||
WILL_FIRE_RL_rl_stage1_WFI ||
WILL_FIRE_RL_rl_stage1_FENCE ||
WILL_FIRE_RL_rl_stage1_FENCE_I ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_stage1_SFENCE_VMA ||
WILL_FIRE_RL_rl_trap ||
WILL_FIRE_RL_rl_stage1_xRET ;
// register rg_run_on_reset
assign rg_run_on_reset$D_IN = f_reset_reqs$D_OUT ;
assign rg_run_on_reset$EN = CAN_FIRE_RL_rl_reset_start ;
// register rg_sstatus_SUM
assign rg_sstatus_SUM$D_IN = 1'd0 ;
assign rg_sstatus_SUM$EN = MUX_rg_state$write_1__SEL_9 ;
// register rg_start_CPI_cycles
assign rg_start_CPI_cycles$D_IN = csr_regfile$read_csr_mcycle ;
assign rg_start_CPI_cycles$EN = MUX_imem_rg_f3$write_1__SEL_1 ;
// register rg_start_CPI_instrs
assign rg_start_CPI_instrs$D_IN = csr_regfile$read_csr_minstret ;
assign rg_start_CPI_instrs$EN = MUX_imem_rg_f3$write_1__SEL_1 ;
// register rg_state
always@(WILL_FIRE_RL_rl_reset_complete or
MUX_rg_state$write_1__VAL_2 or
WILL_FIRE_RL_rl_stage1_CSRR_W_2 or
MUX_rg_state$write_1__VAL_3 or
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 or
MUX_rg_state$write_1__VAL_4 or
WILL_FIRE_RL_rl_reset_from_WFI or
WILL_FIRE_RL_rl_reset_start or
MUX_rg_state$write_1__SEL_7 or
MUX_rg_state$write_1__SEL_8 or
MUX_rg_state$write_1__SEL_1 or
MUX_rg_state$write_1__SEL_9 or
WILL_FIRE_RL_rl_stage1_CSRR_W or
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C or
WILL_FIRE_RL_rl_stage1_FENCE_I or
WILL_FIRE_RL_rl_stage1_FENCE or
WILL_FIRE_RL_rl_stage1_SFENCE_VMA or WILL_FIRE_RL_rl_stage1_WFI)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_rl_reset_complete:
rg_state$D_IN = MUX_rg_state$write_1__VAL_2;
WILL_FIRE_RL_rl_stage1_CSRR_W_2:
rg_state$D_IN = MUX_rg_state$write_1__VAL_3;
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2:
rg_state$D_IN = MUX_rg_state$write_1__VAL_4;
WILL_FIRE_RL_rl_reset_from_WFI: rg_state$D_IN = 4'd0;
WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 4'd1;
MUX_rg_state$write_1__SEL_7: rg_state$D_IN = 4'd3;
MUX_rg_state$write_1__SEL_8: rg_state$D_IN = 4'd4;
MUX_rg_state$write_1__SEL_1 || MUX_rg_state$write_1__SEL_9:
rg_state$D_IN = 4'd5;
WILL_FIRE_RL_rl_stage1_CSRR_W: rg_state$D_IN = 4'd6;
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C: rg_state$D_IN = 4'd7;
WILL_FIRE_RL_rl_stage1_FENCE_I: rg_state$D_IN = 4'd9;
WILL_FIRE_RL_rl_stage1_FENCE: rg_state$D_IN = 4'd10;
WILL_FIRE_RL_rl_stage1_SFENCE_VMA: rg_state$D_IN = 4'd11;
WILL_FIRE_RL_rl_stage1_WFI: rg_state$D_IN = 4'd12;
default: rg_state$D_IN = 4'b1010 /* unspecified value */ ;
endcase
end
assign rg_state$EN =
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1691 ||
WILL_FIRE_RL_rl_reset_complete ||
WILL_FIRE_RL_rl_stage1_CSRR_W_2 ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 ||
WILL_FIRE_RL_rl_reset_from_WFI ||
WILL_FIRE_RL_rl_reset_start ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_rl_stage1_interrupt ||
WILL_FIRE_RL_rl_stage1_trap ||
WILL_FIRE_RL_rl_stage2_nonpipe ||
WILL_FIRE_RL_rl_stage1_xRET ||
WILL_FIRE_RL_rl_trap ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_FENCE_I ||
WILL_FIRE_RL_rl_stage1_FENCE ||
WILL_FIRE_RL_rl_stage1_SFENCE_VMA ||
WILL_FIRE_RL_rl_stage1_WFI ;
// register rg_trap_info
always@(MUX_rg_trap_info$write_1__SEL_1 or
MUX_rg_trap_info$write_1__VAL_1 or
WILL_FIRE_RL_rl_stage2_nonpipe or
MUX_rg_trap_info$write_1__VAL_2 or
WILL_FIRE_RL_rl_stage1_trap or
MUX_rg_trap_info$write_1__VAL_3 or
WILL_FIRE_RL_rl_stage1_interrupt or MUX_rg_trap_info$write_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_rg_trap_info$write_1__SEL_1:
rg_trap_info$D_IN = MUX_rg_trap_info$write_1__VAL_1;
WILL_FIRE_RL_rl_stage2_nonpipe:
rg_trap_info$D_IN = MUX_rg_trap_info$write_1__VAL_2;
WILL_FIRE_RL_rl_stage1_trap:
rg_trap_info$D_IN = MUX_rg_trap_info$write_1__VAL_3;
WILL_FIRE_RL_rl_stage1_interrupt:
rg_trap_info$D_IN = MUX_rg_trap_info$write_1__VAL_4;
default: rg_trap_info$D_IN =
132'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign rg_trap_info$EN =
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_stage2_nonpipe ||
WILL_FIRE_RL_rl_stage1_trap ||
WILL_FIRE_RL_rl_stage1_interrupt ;
// register rg_trap_instr
assign rg_trap_instr$D_IN =
MUX_rg_trap_instr$write_1__SEL_1 ?
stage1_rg_stage_input[263:232] :
stage2_rg_stage2[231:200] ;
assign rg_trap_instr$EN =
WILL_FIRE_RL_rl_stage1_interrupt ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_stage1_trap ||
WILL_FIRE_RL_rl_stage2_nonpipe ;
// register rg_trap_interrupt
assign rg_trap_interrupt$D_IN = !MUX_rg_trap_interrupt$write_1__SEL_1 ;
assign rg_trap_interrupt$EN =
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
WILL_FIRE_RL_rl_stage1_CSRR_W ||
WILL_FIRE_RL_rl_stage1_trap ||
WILL_FIRE_RL_rl_stage2_nonpipe ||
WILL_FIRE_RL_rl_stage1_interrupt ;
// register stage1_rg_full
always@(WILL_FIRE_RL_stage1_rl_reset or
WILL_FIRE_RL_rl_pipe or
MUX_stage1_rg_full$write_1__VAL_2 or
MUX_imem_rg_f3$write_1__SEL_1 or
WILL_FIRE_RL_rl_stage1_WFI or
WILL_FIRE_RL_rl_finish_SFENCE_VMA or
WILL_FIRE_RL_rl_finish_FENCE or
WILL_FIRE_RL_rl_finish_FENCE_I or
WILL_FIRE_RL_rl_stage1_xRET or
WILL_FIRE_RL_rl_stage1_restart_after_csrrx or WILL_FIRE_RL_rl_trap)
case (1'b1)
WILL_FIRE_RL_stage1_rl_reset: stage1_rg_full$D_IN = 1'd0;
WILL_FIRE_RL_rl_pipe:
stage1_rg_full$D_IN = MUX_stage1_rg_full$write_1__VAL_2;
MUX_imem_rg_f3$write_1__SEL_1 || WILL_FIRE_RL_rl_stage1_WFI ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_xRET ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_rl_trap:
stage1_rg_full$D_IN = 1'd0;
default: stage1_rg_full$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign stage1_rg_full$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe ||
WILL_FIRE_RL_rl_stage1_WFI ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_xRET ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_rl_trap ||
WILL_FIRE_RL_stage1_rl_reset ;
// register stage1_rg_stage_input
assign stage1_rg_stage_input$D_IN =
{ stageD_rg_data[233:170],
stageD_rg_data[167:166],
stageD_rg_data[169:168],
stageD_rg_data[165:96],
_theResult____h5108,
stageD_rg_data[79:0],
_theResult____h5108[6:0],
_theResult____h5108[11:7],
_theResult____h5108[19:15],
_theResult____h5108[24:20],
_theResult____h5108[31:27],
_theResult____h5108[31:20],
_theResult____h5108[14:12],
_theResult____h5108[31:27],
_theResult____h5108[31:25],
decoded_instr_funct10__h20268,
_theResult____h5108[31:20],
decoded_instr_imm12_S__h20270,
decoded_instr_imm13_SB__h20271,
_theResult____h5108[31:12],
decoded_instr_imm21_UJ__h20273,
_theResult____h5108[27:20],
_theResult____h5108[26:25] } ;
assign stage1_rg_stage_input$EN =
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1643 &&
stageD_rg_full ;
// register stage2_rg_full
always@(stage2_f_reset_reqs$EMPTY_N or
WILL_FIRE_RL_rl_pipe or
MUX_stage2_rg_full$write_1__VAL_2 or
MUX_imem_rg_f3$write_1__SEL_1 or WILL_FIRE_RL_rl_trap)
case (1'b1)
stage2_f_reset_reqs$EMPTY_N: stage2_rg_full$D_IN = 1'd0;
WILL_FIRE_RL_rl_pipe:
stage2_rg_full$D_IN = MUX_stage2_rg_full$write_1__VAL_2;
MUX_imem_rg_f3$write_1__SEL_1 || WILL_FIRE_RL_rl_trap:
stage2_rg_full$D_IN = 1'd0;
default: stage2_rg_full$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign stage2_rg_full$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe ||
WILL_FIRE_RL_rl_trap ||
stage2_f_reset_reqs$EMPTY_N ;
// register stage2_rg_resetting
assign stage2_rg_resetting$D_IN = stage2_f_reset_reqs$EMPTY_N ;
assign stage2_rg_resetting$EN =
WILL_FIRE_RL_stage2_rl_reset_end || stage2_f_reset_reqs$EMPTY_N ;
// register stage2_rg_stage2
assign stage2_rg_stage2$D_IN =
{ rg_cur_priv,
stage1_rg_stage_input[401:338],
stage1_rg_stage_input[263:232],
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d690,
x_out_data_to_stage2_rd__h7707,
x_out_data_to_stage2_addr__h7708,
x_out_data_to_stage2_val1__h7709,
x_out_data_to_stage2_val2__h7710 } ;
assign stage2_rg_stage2$EN =
WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1588 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 !=
4'd0 &&
IF_NOT_stage1_rg_full_03_87_OR_NOT_stage1_rg_s_ETC___d1591 ;
// register stage3_rg_full
always@(WILL_FIRE_RL_stage3_rl_reset or
WILL_FIRE_RL_rl_pipe or
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 or
MUX_imem_rg_f3$write_1__SEL_1)
case (1'b1)
WILL_FIRE_RL_stage3_rl_reset: stage3_rg_full$D_IN = 1'd0;
WILL_FIRE_RL_rl_pipe:
stage3_rg_full$D_IN =
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd2;
MUX_imem_rg_f3$write_1__SEL_1: stage3_rg_full$D_IN = 1'd0;
default: stage3_rg_full$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign stage3_rg_full$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe ||
WILL_FIRE_RL_stage3_rl_reset ;
// register stage3_rg_stage3
assign stage3_rg_stage3$D_IN =
{ stage2_rg_stage2[295:200],
stage2_rg_stage2[297:296],
stage2_rg_stage2[199:197] == 3'd0 ||
IF_stage2_rg_stage2_01_BITS_199_TO_197_02_EQ_1_ETC___d154,
x_out_data_to_stage3_rd__h7080,
x_out_data_to_stage3_rd_val__h7081 } ;
assign stage3_rg_stage3$EN =
WILL_FIRE_RL_rl_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 ==
2'd2 ;
// register stageD_rg_data
assign stageD_rg_data$D_IN =
{ imem_rg_pc,
stageF_rg_epoch,
stageF_rg_priv,
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1345,
near_mem$imem_exc,
near_mem$imem_exc_code,
imem_rg_tval,
d_instr__h16678,
stageF_branch_predictor$predict_rsp } ;
assign stageD_rg_data$EN =
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1684 ;
// register stageD_rg_full
always@(WILL_FIRE_RL_stageD_rl_reset or
WILL_FIRE_RL_rl_pipe or
MUX_stageD_rg_full$write_1__VAL_2 or
MUX_imem_rg_f3$write_1__SEL_1 or
WILL_FIRE_RL_rl_trap_fetch or
WILL_FIRE_RL_rl_WFI_resume or
WILL_FIRE_RL_rl_stage1_WFI or
WILL_FIRE_RL_rl_finish_SFENCE_VMA or
WILL_FIRE_RL_rl_finish_FENCE or
WILL_FIRE_RL_rl_finish_FENCE_I or
WILL_FIRE_RL_rl_stage1_xRET or
WILL_FIRE_RL_rl_stage1_restart_after_csrrx or WILL_FIRE_RL_rl_trap)
case (1'b1)
WILL_FIRE_RL_stageD_rl_reset: stageD_rg_full$D_IN = 1'd0;
WILL_FIRE_RL_rl_pipe:
stageD_rg_full$D_IN = MUX_stageD_rg_full$write_1__VAL_2;
MUX_imem_rg_f3$write_1__SEL_1 || WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_stage1_WFI ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_xRET ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_rl_trap:
stageD_rg_full$D_IN = 1'd0;
default: stageD_rg_full$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign stageD_rg_full$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_stage1_WFI ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_xRET ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_rl_trap ||
WILL_FIRE_RL_stageD_rl_reset ;
// register stageF_rg_epoch
always@(WILL_FIRE_RL_stageF_rl_reset or
MUX_imem_rg_cache_addr$write_1__SEL_3 or
stageF_rg_epoch or
MUX_imem_rg_f3$write_1__SEL_1 or
new_epoch__h18044 or
WILL_FIRE_RL_rl_trap_fetch or
WILL_FIRE_RL_rl_WFI_resume or
WILL_FIRE_RL_rl_finish_SFENCE_VMA or
WILL_FIRE_RL_rl_finish_FENCE or
WILL_FIRE_RL_rl_finish_FENCE_I or
WILL_FIRE_RL_rl_stage1_restart_after_csrrx)
case (1'b1)
WILL_FIRE_RL_stageF_rl_reset: stageF_rg_epoch$D_IN = 2'd0;
MUX_imem_rg_cache_addr$write_1__SEL_3:
stageF_rg_epoch$D_IN = stageF_rg_epoch;
MUX_imem_rg_f3$write_1__SEL_1: stageF_rg_epoch$D_IN = new_epoch__h18044;
WILL_FIRE_RL_rl_trap_fetch: stageF_rg_epoch$D_IN = new_epoch__h18044;
WILL_FIRE_RL_rl_WFI_resume: stageF_rg_epoch$D_IN = new_epoch__h18044;
WILL_FIRE_RL_rl_finish_SFENCE_VMA:
stageF_rg_epoch$D_IN = new_epoch__h18044;
WILL_FIRE_RL_rl_finish_FENCE: stageF_rg_epoch$D_IN = new_epoch__h18044;
WILL_FIRE_RL_rl_finish_FENCE_I: stageF_rg_epoch$D_IN = new_epoch__h18044;
WILL_FIRE_RL_rl_stage1_restart_after_csrrx:
stageF_rg_epoch$D_IN = new_epoch__h18044;
default: stageF_rg_epoch$D_IN = 2'b10 /* unspecified value */ ;
endcase
assign stageF_rg_epoch$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1703 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
WILL_FIRE_RL_stageF_rl_reset ;
// register stageF_rg_full
always@(WILL_FIRE_RL_stageF_rl_reset or
WILL_FIRE_RL_rl_pipe or
MUX_stageF_rg_full$write_1__VAL_2 or
MUX_imem_rg_f3$write_1__SEL_1 or
WILL_FIRE_RL_rl_trap_fetch or
WILL_FIRE_RL_rl_WFI_resume or
WILL_FIRE_RL_rl_finish_SFENCE_VMA or
WILL_FIRE_RL_rl_finish_FENCE or
WILL_FIRE_RL_rl_finish_FENCE_I or
WILL_FIRE_RL_rl_stage1_restart_after_csrrx)
case (1'b1)
WILL_FIRE_RL_stageF_rl_reset: stageF_rg_full$D_IN = 1'd0;
WILL_FIRE_RL_rl_pipe:
stageF_rg_full$D_IN = MUX_stageF_rg_full$write_1__VAL_2;
MUX_imem_rg_f3$write_1__SEL_1 || WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx:
stageF_rg_full$D_IN = 1'd1;
default: stageF_rg_full$D_IN = 1'b0 /* unspecified value */ ;
endcase
assign stageF_rg_full$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe ||
WILL_FIRE_RL_stageF_rl_reset ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// register stageF_rg_priv
assign stageF_rg_priv$D_IN = rg_cur_priv ;
assign stageF_rg_priv$EN =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1703 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
// submodule csr_regfile
assign csr_regfile$access_permitted_1_csr_addr = rg_trap_instr[31:20] ;
assign csr_regfile$access_permitted_1_priv = rg_cur_priv ;
assign csr_regfile$access_permitted_1_read_not_write = 1'd0 ;
assign csr_regfile$access_permitted_2_csr_addr = rg_trap_instr[31:20] ;
assign csr_regfile$access_permitted_2_priv = rg_cur_priv ;
assign csr_regfile$access_permitted_2_read_not_write =
rs1_val__h23899 == 64'd0 ;
assign csr_regfile$csr_counter_read_fault_csr_addr = 12'h0 ;
assign csr_regfile$csr_counter_read_fault_priv = 2'h0 ;
always@(IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544)
begin
case (IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544)
4'd8: csr_regfile$csr_ret_actions_from_priv = 2'b11;
4'd9: csr_regfile$csr_ret_actions_from_priv = 2'b01;
default: csr_regfile$csr_ret_actions_from_priv = 2'b0;
endcase
end
assign csr_regfile$csr_trap_actions_exc_code = rg_trap_info[67:64] ;
assign csr_regfile$csr_trap_actions_from_priv = rg_cur_priv ;
assign csr_regfile$csr_trap_actions_interrupt =
rg_trap_interrupt && !csr_regfile$nmi_pending ;
assign csr_regfile$csr_trap_actions_nmi =
rg_trap_interrupt && csr_regfile$nmi_pending ;
assign csr_regfile$csr_trap_actions_pc = rg_trap_info[131:68] ;
assign csr_regfile$csr_trap_actions_xtval = rg_trap_info[63:0] ;
assign csr_regfile$interrupt_pending_cur_priv = rg_cur_priv ;
assign csr_regfile$m_external_interrupt_req_set_not_clear =
m_external_interrupt_req_set_not_clear ;
assign csr_regfile$mav_csr_write_csr_addr = rg_trap_instr[31:20] ;
assign csr_regfile$mav_csr_write_word =
MUX_csr_regfile$mav_csr_write_1__SEL_1 ?
rs1_val__h23220 :
MUX_csr_regfile$mav_csr_write_2__VAL_2 ;
assign csr_regfile$mav_read_csr_csr_addr = 12'h0 ;
assign csr_regfile$nmi_req_set_not_clear = nmi_req_set_not_clear ;
assign csr_regfile$read_csr_csr_addr = rg_trap_instr[31:20] ;
assign csr_regfile$read_csr_port2_csr_addr = 12'h0 ;
assign csr_regfile$s_external_interrupt_req_set_not_clear =
s_external_interrupt_req_set_not_clear ;
assign csr_regfile$software_interrupt_req_set_not_clear =
software_interrupt_req_set_not_clear ;
assign csr_regfile$timer_interrupt_req_set_not_clear =
timer_interrupt_req_set_not_clear ;
assign csr_regfile$EN_server_reset_request_put =
CAN_FIRE_RL_rl_reset_start ;
assign csr_regfile$EN_server_reset_response_get =
MUX_rg_state$write_1__SEL_2 ;
assign csr_regfile$EN_mav_read_csr = 1'b0 ;
assign csr_regfile$EN_mav_csr_write =
WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
csr_regfile$access_permitted_1 ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
csr_regfile$access_permitted_2 &&
rg_trap_instr[19:15] != 5'd0 ;
assign csr_regfile$EN_csr_trap_actions = CAN_FIRE_RL_rl_trap ;
assign csr_regfile$EN_csr_ret_actions = CAN_FIRE_RL_rl_stage1_xRET ;
assign csr_regfile$EN_csr_minstret_incr =
WILL_FIRE_RL_rl_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 ==
2'd2 ||
WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
csr_regfile$access_permitted_1 ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
csr_regfile$access_permitted_2 ||
WILL_FIRE_RL_rl_stage1_WFI ||
WILL_FIRE_RL_rl_stage1_FENCE ||
WILL_FIRE_RL_rl_stage1_FENCE_I ||
WILL_FIRE_RL_rl_stage1_xRET ||
WILL_FIRE_RL_rl_stage1_SFENCE_VMA ;
assign csr_regfile$EN_debug = 1'b0 ;
// submodule f_reset_reqs
assign f_reset_reqs$D_IN = hart0_server_reset_request_put ;
assign f_reset_reqs$ENQ = EN_hart0_server_reset_request_put ;
assign f_reset_reqs$DEQ =
gpr_regfile$RDY_server_reset_request_put &&
near_mem$RDY_server_reset_request_put &&
csr_regfile_RDY_server_reset_request_put__447__ETC___d1459 &&
rg_state == 4'd0 ;
assign f_reset_reqs$CLR = 1'b0 ;
// submodule f_reset_rsps
assign f_reset_rsps$D_IN = rg_run_on_reset ;
assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_2 ;
assign f_reset_rsps$DEQ = EN_hart0_server_reset_response_get ;
assign f_reset_rsps$CLR = 1'b0 ;
// submodule gpr_regfile
assign gpr_regfile$read_rs1_port2_rs1 = 5'h0 ;
assign gpr_regfile$read_rs1_rs1 = stage1_rg_stage_input[139:135] ;
assign gpr_regfile$read_rs2_rs2 = stage1_rg_stage_input[134:130] ;
assign gpr_regfile$write_rd_rd =
(MUX_csr_regfile$mav_csr_write_1__SEL_1 ||
MUX_gpr_regfile$write_rd_1__SEL_3) ?
rg_trap_instr[11:7] :
stage3_rg_stage3[68:64] ;
assign gpr_regfile$write_rd_rd_val =
(MUX_csr_regfile$mav_csr_write_1__SEL_1 ||
MUX_gpr_regfile$write_rd_1__SEL_3) ?
csr_regfile$read_csr[63:0] :
stage3_rg_stage3[63:0] ;
assign gpr_regfile$EN_server_reset_request_put =
CAN_FIRE_RL_rl_reset_start ;
assign gpr_regfile$EN_server_reset_response_get =
MUX_rg_state$write_1__SEL_2 ;
assign gpr_regfile$EN_write_rd =
WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[69] ||
WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
csr_regfile$access_permitted_1 ||
WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
csr_regfile$access_permitted_2 ;
// submodule near_mem
assign near_mem$dmem_master_arready = dmem_master_arready ;
assign near_mem$dmem_master_awready = dmem_master_awready ;
assign near_mem$dmem_master_bid = dmem_master_bid ;
assign near_mem$dmem_master_bresp = dmem_master_bresp ;
assign near_mem$dmem_master_bvalid = dmem_master_bvalid ;
assign near_mem$dmem_master_rdata = dmem_master_rdata ;
assign near_mem$dmem_master_rid = dmem_master_rid ;
assign near_mem$dmem_master_rlast = dmem_master_rlast ;
assign near_mem$dmem_master_rresp = dmem_master_rresp ;
assign near_mem$dmem_master_rvalid = dmem_master_rvalid ;
assign near_mem$dmem_master_wready = dmem_master_wready ;
assign near_mem$dmem_req_addr = x_out_data_to_stage2_addr__h7708 ;
assign near_mem$dmem_req_amo_funct7 =
x_out_data_to_stage2_val1__h7709[6:0] ;
assign near_mem$dmem_req_f3 = MUX_rg_trap_instr$write_1__VAL_1[14:12] ;
assign near_mem$dmem_req_mstatus_MXR = csr_regfile$read_mstatus[19] ;
always@(IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d690)
begin
case (IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d690)
3'd1: near_mem$dmem_req_op = 2'd0;
3'd2: near_mem$dmem_req_op = 2'd1;
default: near_mem$dmem_req_op = 2'd2;
endcase
end
assign near_mem$dmem_req_priv =
csr_regfile$read_mstatus[17] ?
csr_regfile$read_mstatus[12:11] :
rg_cur_priv ;
assign near_mem$dmem_req_satp = csr_regfile$read_satp ;
assign near_mem$dmem_req_sstatus_SUM = 1'd0 ;
assign near_mem$dmem_req_store_value = x_out_data_to_stage2_val2__h7710 ;
assign near_mem$imem_master_arready = imem_master_arready ;
assign near_mem$imem_master_awready = imem_master_awready ;
assign near_mem$imem_master_bid = imem_master_bid ;
assign near_mem$imem_master_bresp = imem_master_bresp ;
assign near_mem$imem_master_bvalid = imem_master_bvalid ;
assign near_mem$imem_master_rdata = imem_master_rdata ;
assign near_mem$imem_master_rid = imem_master_rid ;
assign near_mem$imem_master_rlast = imem_master_rlast ;
assign near_mem$imem_master_rresp = imem_master_rresp ;
assign near_mem$imem_master_rvalid = imem_master_rvalid ;
assign near_mem$imem_master_wready = imem_master_wready ;
always@(MUX_imem_rg_f3$write_1__SEL_1 or
MUX_near_mem$imem_req_2__VAL_1 or
MUX_imem_rg_cache_addr$write_1__SEL_3 or
MUX_near_mem$imem_req_2__VAL_2 or
WILL_FIRE_RL_imem_rl_fetch_next_32b or
MUX_imem_rg_tval$write_1__VAL_4 or
MUX_rg_state$write_1__SEL_7 or MUX_near_mem$imem_req_2__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_imem_rg_f3$write_1__SEL_1:
near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_1;
MUX_imem_rg_cache_addr$write_1__SEL_3:
near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_2;
WILL_FIRE_RL_imem_rl_fetch_next_32b:
near_mem$imem_req_addr = MUX_imem_rg_tval$write_1__VAL_4;
MUX_rg_state$write_1__SEL_7:
near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_4;
default: near_mem$imem_req_addr =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign near_mem$imem_req_f3 =
WILL_FIRE_RL_imem_rl_fetch_next_32b ? imem_rg_f3 : 3'b010 ;
assign near_mem$imem_req_mstatus_MXR =
(MUX_imem_rg_f3$write_1__SEL_1 ||
MUX_imem_rg_cache_addr$write_1__SEL_3 ||
MUX_rg_state$write_1__SEL_7) ?
csr_regfile$read_mstatus[19] :
imem_rg_mstatus_MXR ;
assign near_mem$imem_req_priv =
(MUX_imem_rg_f3$write_1__SEL_1 ||
MUX_imem_rg_cache_addr$write_1__SEL_3 ||
MUX_rg_state$write_1__SEL_7) ?
rg_cur_priv :
imem_rg_priv ;
assign near_mem$imem_req_satp =
WILL_FIRE_RL_imem_rl_fetch_next_32b ?
imem_rg_satp :
csr_regfile$read_satp ;
assign near_mem$imem_req_sstatus_SUM =
WILL_FIRE_RL_imem_rl_fetch_next_32b && imem_rg_sstatus_SUM ;
assign near_mem$server_fence_request_put =
8'b10101010 /* unspecified value */ ;
assign near_mem$EN_server_reset_request_put = CAN_FIRE_RL_rl_reset_start ;
assign near_mem$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_2 ;
assign near_mem$EN_imem_req =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1703 ||
WILL_FIRE_RL_imem_rl_fetch_next_32b ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
assign near_mem$EN_dmem_req =
WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1588 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 !=
4'd0 &&
IF_NOT_stage1_rg_full_03_87_OR_NOT_stage1_rg_s_ETC___d1591 &&
(IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d690 ==
3'd1 ||
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d690 ==
3'd2 ||
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d690 ==
3'd4) ;
assign near_mem$EN_server_fence_i_request_put =
MUX_rg_state$write_1__SEL_12 ;
assign near_mem$EN_server_fence_i_response_get =
CAN_FIRE_RL_rl_finish_FENCE_I ;
assign near_mem$EN_server_fence_request_put = MUX_rg_state$write_1__SEL_13 ;
assign near_mem$EN_server_fence_response_get = CAN_FIRE_RL_rl_finish_FENCE ;
assign near_mem$EN_sfence_vma = CAN_FIRE_RL_rl_stage1_SFENCE_VMA ;
// submodule soc_map
assign soc_map$m_is_IO_addr_addr = 64'h0 ;
assign soc_map$m_is_mem_addr_addr = 64'h0 ;
assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;
// submodule stage1_f_reset_reqs
assign stage1_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ;
assign stage1_f_reset_reqs$DEQ = CAN_FIRE_RL_stage1_rl_reset ;
assign stage1_f_reset_reqs$CLR = 1'b0 ;
// submodule stage1_f_reset_rsps
assign stage1_f_reset_rsps$ENQ = CAN_FIRE_RL_stage1_rl_reset ;
assign stage1_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_2 ;
assign stage1_f_reset_rsps$CLR = 1'b0 ;
// submodule stage2_f_reset_reqs
assign stage2_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ;
assign stage2_f_reset_reqs$DEQ = stage2_f_reset_reqs$EMPTY_N ;
assign stage2_f_reset_reqs$CLR = 1'b0 ;
// submodule stage2_f_reset_rsps
assign stage2_f_reset_rsps$ENQ = CAN_FIRE_RL_stage2_rl_reset_end ;
assign stage2_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_2 ;
assign stage2_f_reset_rsps$CLR = 1'b0 ;
// submodule stage2_mbox
assign stage2_mbox$req_f3 = MUX_rg_trap_instr$write_1__VAL_1[14:12] ;
assign stage2_mbox$req_is_OP_not_OP_32 =
!MUX_rg_trap_instr$write_1__VAL_1[3] ;
assign stage2_mbox$req_v1 = x_out_data_to_stage2_val1__h7709 ;
assign stage2_mbox$req_v2 = x_out_data_to_stage2_val2__h7710 ;
assign stage2_mbox$set_verbosity_verbosity = 4'h0 ;
assign stage2_mbox$EN_set_verbosity = 1'b0 ;
assign stage2_mbox$EN_req_reset = 1'b0 ;
assign stage2_mbox$EN_rsp_reset = 1'b0 ;
assign stage2_mbox$EN_req =
WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1588 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 !=
4'd0 &&
IF_NOT_stage1_rg_full_03_87_OR_NOT_stage1_rg_s_ETC___d1591 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d690 ==
3'd3 ;
// submodule stage3_f_reset_reqs
assign stage3_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ;
assign stage3_f_reset_reqs$DEQ = CAN_FIRE_RL_stage3_rl_reset ;
assign stage3_f_reset_reqs$CLR = 1'b0 ;
// submodule stage3_f_reset_rsps
assign stage3_f_reset_rsps$ENQ = CAN_FIRE_RL_stage3_rl_reset ;
assign stage3_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_2 ;
assign stage3_f_reset_rsps$CLR = 1'b0 ;
// submodule stageD_f_reset_reqs
assign stageD_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ;
assign stageD_f_reset_reqs$DEQ = CAN_FIRE_RL_stageD_rl_reset ;
assign stageD_f_reset_reqs$CLR = 1'b0 ;
// submodule stageD_f_reset_rsps
assign stageD_f_reset_rsps$ENQ = CAN_FIRE_RL_stageD_rl_reset ;
assign stageD_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_2 ;
assign stageD_f_reset_rsps$CLR = 1'b0 ;
// submodule stageF_branch_predictor
assign stageF_branch_predictor$bp_train_cf_info =
(stage1_rg_full &&
(!stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ||
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d1522) &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 !=
4'd0) ?
{ IF_NOT_stage1_rg_full_03_87_OR_NOT_stage1_rg_s_ETC___d626,
stage1_rg_stage_input[401:338],
stage1_rg_stage_input[151:145] != 7'b1100011 ||
IF_stage1_rg_stage_input_04_BITS_112_TO_110_33_ETC___d279,
alu_outputs_cf_info_fallthru_PC__h9699,
alu_outputs_cf_info_taken_PC__h9700 } :
195'h6AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
assign stageF_branch_predictor$bp_train_instr = d_instr__h16678 ;
assign stageF_branch_predictor$bp_train_is_i32_not_i16 =
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1345 ;
assign stageF_branch_predictor$bp_train_pc = imem_rg_pc ;
always@(MUX_imem_rg_f3$write_1__SEL_1 or
soc_map$m_pc_reset_value or
MUX_imem_rg_cache_addr$write_1__SEL_3 or
stageF_branch_predictor$predict_rsp or
MUX_rg_state$write_1__SEL_7 or rg_next_pc)
begin
case (1'b1) // synopsys parallel_case
MUX_imem_rg_f3$write_1__SEL_1:
stageF_branch_predictor$predict_req_pc = soc_map$m_pc_reset_value;
MUX_imem_rg_cache_addr$write_1__SEL_3:
stageF_branch_predictor$predict_req_pc =
stageF_branch_predictor$predict_rsp;
MUX_rg_state$write_1__SEL_7:
stageF_branch_predictor$predict_req_pc = rg_next_pc;
default: stageF_branch_predictor$predict_req_pc =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign stageF_branch_predictor$predict_rsp_instr = d_instr__h16678 ;
assign stageF_branch_predictor$predict_rsp_is_i32_not_i16 =
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1345 ;
assign stageF_branch_predictor$EN_reset = 1'b0 ;
assign stageF_branch_predictor$EN_predict_req =
WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1703 ||
WILL_FIRE_RL_rl_trap_fetch ||
WILL_FIRE_RL_rl_WFI_resume ||
WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
WILL_FIRE_RL_rl_finish_FENCE ||
WILL_FIRE_RL_rl_finish_FENCE_I ||
WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
assign stageF_branch_predictor$EN_bp_train =
WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1684 ;
// submodule stageF_f_reset_reqs
assign stageF_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ;
assign stageF_f_reset_reqs$DEQ = CAN_FIRE_RL_stageF_rl_reset ;
assign stageF_f_reset_reqs$CLR = 1'b0 ;
// submodule stageF_f_reset_rsps
assign stageF_f_reset_rsps$ENQ = CAN_FIRE_RL_stageF_rl_reset ;
assign stageF_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_2 ;
assign stageF_f_reset_rsps$CLR = 1'b0 ;
// remaining internal signals
assign IF_IF_stage1_rg_stage_input_04_BITS_151_TO_145_ETC___d911 =
next_pc__h7649 == stage1_rg_stage_input[215:152] ;
assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1529 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1525 ?
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 !=
4'd0 &&
!IF_IF_stage1_rg_stage_input_04_BITS_151_TO_145_ETC___d911 &&
stageF_rg_full &&
(!near_mem$imem_valid ||
imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1341) :
stage1_rg_full ;
assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1532 =
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1529 &&
stageD_rg_full ||
!stageF_rg_full ||
!near_mem$imem_valid ||
imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1341 ;
assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1643 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1525 ?
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 ==
4'd0 ||
IF_IF_stage1_rg_stage_input_04_BITS_151_TO_145_ETC___d911 ||
!stageF_rg_full ||
near_mem$imem_valid &&
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1347 :
!stage1_rg_full ;
assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1684 =
(IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1643 ||
!stageD_rg_full) &&
stageF_rg_full &&
near_mem$imem_valid &&
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1347 ;
assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1691 =
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1684 &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1536 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 !=
4'd0 &&
!IF_IF_stage1_rg_stage_input_04_BITS_151_TO_145_ETC___d911 ;
assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1703 =
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1684 &&
(csr_regfile_interrupt_pending_rg_cur_priv_1_50_ETC___d1698 ||
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 ==
4'd0 ||
IF_IF_stage1_rg_stage_input_04_BITS_151_TO_145_ETC___d911) ;
assign IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1727 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1525 ?
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 !=
4'd0 &&
IF_NOT_stage1_rg_full_03_87_OR_NOT_stage1_rg_s_ETC___d1561 :
stage1_rg_full ;
assign IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem__ETC___d1319 =
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1316 ?
{ 16'b0,
imem_rg_pc_BITS_63_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 ?
near_mem$imem_instr[31:16] :
imem_rg_cache_b16 } :
near_mem$imem_instr ;
assign IF_NOT_near_mem_dmem_valid__22_41_OR_NOT_near__ETC___d187 =
(!near_mem$dmem_valid || !near_mem$dmem_exc) ?
((stage2_rg_stage2[196:192] == 5'd0) ? 2'd0 : 2'd1) :
2'd0 ;
assign IF_NOT_stage1_rg_full_03_87_OR_NOT_stage1_rg_s_ETC___d1561 =
!IF_IF_stage1_rg_stage_input_04_BITS_151_TO_145_ETC___d911 &&
stageF_rg_full &&
(!near_mem$imem_valid ||
imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1341) ;
assign IF_NOT_stage1_rg_full_03_87_OR_NOT_stage1_rg_s_ETC___d1591 =
IF_IF_stage1_rg_stage_input_04_BITS_151_TO_145_ETC___d911 ||
!stageF_rg_full ||
near_mem$imem_valid &&
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1347 ;
assign IF_NOT_stage1_rg_stage_input_04_BITS_112_TO_11_ETC___d490 =
NOT_stage1_rg_stage_input_04_BITS_112_TO_110_3_ETC___d315 ?
4'd12 :
4'd1 ;
assign IF_csr_regfile_read_csr_rg_trap_instr_771_BITS_ETC___d1826 =
csr_regfile$read_csr[63:0] | rs1_val__h23899 ;
assign IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1165 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b0 &&
stageD_rg_data[79:77] == 3'b011) ?
instr__h16179 :
((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b0 &&
stageD_rg_data[79:77] == 3'b111) ?
instr__h16330 :
32'h0) ;
assign IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1166 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[79:77] == 3'b111) ?
instr__h15980 :
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1165 ;
assign IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1168 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[79:76] == 4'b1001 &&
stageD_rg_data[75:71] == 5'd0 &&
stageD_rg_data[70:66] == 5'd0) ?
instr__h15731 :
((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[75:71] != 5'd0 &&
stageD_rg_data[79:77] == 3'b011) ?
instr__h15827 :
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1166) ;
assign IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1170 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:74] == 6'b100111 &&
stageD_rg_data[70:69] == 2'b01) ?
instr__h15435 :
((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:74] == 6'b100111 &&
stageD_rg_data[70:69] == 2'b0) ?
instr__h15573 :
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1168) ;
assign IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1172 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:74] == 6'b100011 &&
stageD_rg_data[70:69] == 2'b01) ?
instr__h15161 :
((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:74] == 6'b100011 &&
stageD_rg_data[70:69] == 2'b0) ?
instr__h15297 :
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1170) ;
assign IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1174 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:74] == 6'b100011 &&
stageD_rg_data[70:69] == 2'b11) ?
instr__h14889 :
((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:74] == 6'b100011 &&
stageD_rg_data[70:69] == 2'b10) ?
instr__h15025 :
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1172) ;
assign IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1175 =
(csr_regfile_read_misa__9_BIT_2_26_AND_stageD_r_ETC___d1007 &&
stageD_rg_data[70:66] != 5'd0) ?
instr__h14794 :
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1174 ;
assign IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1176 =
(csr_regfile_read_misa__9_BIT_2_26_AND_stageD_r_ETC___d1001 &&
stageD_rg_data[70:66] != 5'd0) ?
instr__h14675 :
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1175 ;
assign IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1178 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b100 &&
stageD_rg_data[75:74] == 2'b01 &&
imm6__h12788 != 6'd0) ?
instr__h14380 :
((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b100 &&
stageD_rg_data[75:74] == 2'b10) ?
instr__h14497 :
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1176) ;
assign IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1179 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b100 &&
stageD_rg_data[75:74] == 2'b0 &&
imm6__h12788 != 6'd0) ?
instr__h14191 :
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1178 ;
assign IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1180 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[79:77] == 3'b0 &&
stageD_rg_data[75:71] != 5'd0 &&
imm6__h12788 != 6'd0) ?
instr__h14002 :
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1179 ;
assign IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1182 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b011 &&
stageD_rg_data[75:71] == 5'd2 &&
nzimm10__h13457 != 10'd0) ?
instr__h13661 :
((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b0 &&
stageD_rg_data[79:77] == 3'b0 &&
nzimm10__h13672 != 10'd0) ?
instr__h13833 :
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1180) ;
assign IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1184 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b0 &&
stageD_rg_data[75:71] != 5'd0 &&
imm6__h12788 != 6'd0 ||
csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b0 &&
stageD_rg_data[75:71] == 5'd0 &&
imm6__h12788 == 6'd0) ?
instr__h13179 :
((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b001 &&
stageD_rg_data[75:71] != 5'd0) ?
instr__h13406 :
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1182) ;
assign IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1185 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b011 &&
stageD_rg_data[75:71] != 5'd0 &&
stageD_rg_data[75:71] != 5'd2 &&
imm6__h12788 != 6'd0) ?
instr__h13050 :
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1184 ;
assign IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1187 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b111) ?
instr__h12528 :
((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b010 &&
stageD_rg_data[75:71] != 5'd0) ?
instr__h12866 :
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1185) ;
assign IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1188 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b110) ?
instr__h12211 :
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1187 ;
assign IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1189 =
(csr_regfile_read_misa__9_BIT_2_26_AND_stageD_r_ETC___d1007 &&
stageD_rg_data[70:66] == 5'd0) ?
instr__h12146 :
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1188 ;
assign IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1190 =
(csr_regfile_read_misa__9_BIT_2_26_AND_stageD_r_ETC___d1001 &&
stageD_rg_data[70:66] == 5'd0) ?
instr__h12030 :
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1189 ;
assign IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1191 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
stageD_rg_data[79:77] == 3'b101) ?
instr__h11577 :
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1190 ;
assign IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1192 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b0 &&
stageD_rg_data[79:77] == 3'b110) ?
instr__h11348 :
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1191 ;
assign IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1193 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b0 &&
stageD_rg_data[79:77] == 3'b010) ?
instr__h11153 :
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1192 ;
assign IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1194 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[79:77] == 3'b110) ?
instr__h10961 :
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1193 ;
assign IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg_p_ETC___d1320 =
(imem_rg_pc[1:0] == 2'b0 &&
imem_rg_pc_BITS_63_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 &&
near_mem$imem_instr[1:0] != 2'b11) ?
instr_out___1__h16702 :
IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem__ETC___d1319 ;
assign IF_near_mem_dmem_valid__22_THEN_IF_near_mem_dm_ETC___d125 =
near_mem$dmem_valid ? (near_mem$dmem_exc ? 2'd3 : 2'd2) : 2'd1 ;
assign IF_rg_cur_priv_1_EQ_0b11_06_AND_stage1_rg_stag_ETC___d520 =
(rg_cur_priv == 2'b11 &&
stage1_rg_stage_input[87:76] == 12'b001100000010) ?
4'd8 :
(rg_cur_priv_1_EQ_0b11_06_OR_rg_cur_priv_1_EQ_0_ETC___d518 ?
4'd11 :
4'd12) ;
assign IF_stage1_rg_stage_input_04_BITS_139_TO_135_07_ETC___d268 =
rs1_val_bypassed__h4837 == rs2_val_bypassed__h4843 ;
assign IF_stage1_rg_stage_input_04_BITS_139_TO_135_07_ETC___d270 =
(rs1_val_bypassed__h4837 ^ 64'h8000000000000000) <
(rs2_val_bypassed__h4843 ^ 64'h8000000000000000) ;
assign IF_stage1_rg_stage_input_04_BITS_139_TO_135_07_ETC___d272 =
rs1_val_bypassed__h4837 < rs2_val_bypassed__h4843 ;
assign IF_stage1_rg_stage_input_04_BITS_139_TO_135_07_ETC___d655 =
rs1_val_bypassed__h4837 +
SEXT_stage1_rg_stage_input_04_BITS_87_TO_76_02___d654 ;
assign IF_stage1_rg_stage_input_04_BITS_139_TO_135_07_ETC__q22 =
IF_stage1_rg_stage_input_04_BITS_139_TO_135_07_ETC___d655[31:0] ;
assign IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d399 =
(stage1_rg_stage_input[151:145] == 7'b1100011) ?
stage1_rg_stage_input[112:110] != 3'b0 &&
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b100 &&
stage1_rg_stage_input[112:110] != 3'b101 &&
stage1_rg_stage_input[112:110] != 3'b110 &&
stage1_rg_stage_input[112:110] != 3'b111 ||
IF_stage1_rg_stage_input_04_BITS_112_TO_110_33_ETC___d279 :
(stage1_rg_stage_input[151:145] != 7'b0110011 ||
stage1_rg_stage_input[104:98] != 7'b0000001) &&
(stage1_rg_stage_input[151:145] != 7'b0111011 ||
stage1_rg_stage_input[104:98] != 7'b0000001) &&
(stage1_rg_stage_input[151:145] != 7'b0010011 &&
stage1_rg_stage_input[151:145] != 7'b0110011 ||
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b101) &&
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q13 ;
assign IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d410 =
(stage1_rg_stage_input[151:145] == 7'b1100011) ?
stage1_rg_stage_input[112:110] != 3'b0 &&
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b100 &&
stage1_rg_stage_input[112:110] != 3'b101 &&
stage1_rg_stage_input[112:110] != 3'b110 &&
stage1_rg_stage_input[112:110] != 3'b111 ||
IF_stage1_rg_stage_input_04_BITS_112_TO_110_33_ETC___d405 :
stage1_rg_stage_input[151:145] != 7'b1101111 &&
stage1_rg_stage_input[151:145] != 7'b1100111 ;
assign IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d478 =
(stage1_rg_stage_input[151:145] == 7'b1100011) ?
(stage1_rg_stage_input[112:110] == 3'b0 ||
stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b100 ||
stage1_rg_stage_input[112:110] == 3'b101 ||
stage1_rg_stage_input[112:110] == 3'b110 ||
stage1_rg_stage_input[112:110] == 3'b111) &&
IF_stage1_rg_stage_input_04_BITS_112_TO_110_33_ETC___d405 :
stage1_rg_stage_input[151:145] != 7'b1101111 &&
stage1_rg_stage_input[151:145] != 7'b1100111 &&
(stage1_rg_stage_input_04_BITS_151_TO_145_31_EQ_ETC___d430 ||
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q15) ;
assign IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d480 =
(stage1_rg_stage_input[151:145] == 7'b1100011) ?
(stage1_rg_stage_input[112:110] == 3'b0 ||
stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b100 ||
stage1_rg_stage_input[112:110] == 3'b101 ||
stage1_rg_stage_input[112:110] == 3'b110 ||
stage1_rg_stage_input[112:110] == 3'b111) &&
IF_stage1_rg_stage_input_04_BITS_112_TO_110_33_ETC___d279 :
stage1_rg_stage_input[151:145] == 7'b1101111 ||
stage1_rg_stage_input[151:145] == 7'b1100111 ;
assign IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d825 =
((stage1_rg_stage_input[151:145] == 7'b0010011 ||
stage1_rg_stage_input[151:145] == 7'b0110011) &&
(stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b101)) ?
alu_outputs___1_val1__h7990 :
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d824 ;
assign IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d826 =
((stage1_rg_stage_input[151:145] == 7'b0110011 ||
stage1_rg_stage_input[151:145] == 7'b0111011) &&
stage1_rg_stage_input[104:98] == 7'b0000001) ?
rs1_val_bypassed__h4837 :
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d825 ;
assign IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 =
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ?
(stage1_rg_stage_input[332] ?
4'd12 :
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d541) :
4'd0 ;
assign IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d690 =
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ?
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q25 :
3'd0 ;
assign IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 =
stage2_rg_full ?
CASE_stage2_rg_stage2_BITS_199_TO_197_0_2_1_IF_ETC__q5 :
2'd0 ;
assign IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d1514 =
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d191 ==
2'd1 &&
(IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d208 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d210) ||
stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d399 &&
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d410 ;
assign IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d191 =
stage2_rg_full ?
CASE_stage2_rg_stage2_BITS_199_TO_197_0_2_1_IF_ETC__q6 :
2'd0 ;
assign IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d208 =
x_out_bypass_rd__h7419 == stage1_rg_stage_input[139:135] ;
assign IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d210 =
x_out_bypass_rd__h7419 == stage1_rg_stage_input[134:130] ;
assign IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d483 =
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d191 ==
2'd1 &&
(IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d208 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d210) ||
!stage1_rg_stage_input[332] &&
(IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d478 ||
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d480) ;
assign IF_stage2_rg_stage2_01_BITS_199_TO_197_02_EQ_3_ETC___d128 =
stage2_mbox$valid ? 2'd2 : 2'd1 ;
assign NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49 =
cur_verbosity__h3317 > 4'd1 ;
assign NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d1522 =
(IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d191 !=
2'd1 ||
!IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d208 &&
!IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d210) &&
!stage1_rg_stage_input[332] &&
(IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d478 ||
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d480) ;
assign NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413 =
(IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d191 !=
2'd1 ||
!IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d208 &&
!IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d210) &&
(stage1_rg_stage_input[332] ||
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d399 &&
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d410) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1521 =
(!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d1517) &&
(IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 ==
2'd2 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 ==
2'd0) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1525 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1521 &&
stage1_rg_full &&
(!stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ||
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d1522) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1534 =
!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d1514 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d483 ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1536 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1534 &&
(IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 ==
2'd2 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 ==
2'd0) &&
stage1_rg_full &&
(!stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ||
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d1522) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1542 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1536 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 !=
4'd0 &&
!IF_IF_stage1_rg_stage_input_04_BITS_151_TO_145_ETC___d911 ||
(imem_rg_pc[1:0] == 2'b0 ||
!imem_rg_pc_BITS_63_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 ||
near_mem$imem_instr[17:16] != 2'b11) &&
stageF_branch_predictor$RDY_predict_req ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1564 =
!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
NOT_stage1_rg_full_03_87_OR_stage1_rg_stage_in_ETC___d1557 ||
NOT_stage1_rg_full_03_87_OR_stage1_rg_stage_in_ETC___d1559 ||
IF_NOT_stage1_rg_full_03_87_OR_NOT_stage1_rg_s_ETC___d1561 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 !=
2'd0 ||
stage3_rg_full ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1581 =
(!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
!stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d483) &&
(IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 ==
2'd2 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 ==
2'd0) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1588 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1534 &&
(IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 ==
2'd2 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 ==
2'd0) &&
stage1_rg_full &&
(!stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ||
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d1522) ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1617 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1588 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 !=
4'd0 &&
IF_NOT_stage1_rg_full_03_87_OR_NOT_stage1_rg_s_ETC___d1591 &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49 ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1640 =
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1588 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 !=
4'd0 &&
IF_NOT_stage1_rg_full_03_87_OR_NOT_stage1_rg_s_ETC___d1591 &&
!IF_IF_stage1_rg_stage_input_04_BITS_151_TO_145_ETC___d911 ;
assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1746 =
!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
!stage1_rg_stage_input[332] &&
(IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d478 ||
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d480) ;
assign NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1302 =
imem_rg_pc[1:0] != 2'b0 &&
imem_rg_pc_BITS_63_TO_2_0_EQ_imem_rg_cache_add_ETC___d1294 &&
near_mem_imem_pc__1_EQ_imem_rg_pc_PLUS_2_296___d1297 &&
imem_rg_cache_b16[1:0] == 2'b11 ;
assign NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1316 =
imem_rg_pc[1:0] != 2'b0 &&
(imem_rg_pc_BITS_63_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 &&
near_mem$imem_instr[17:16] != 2'b11 ||
imem_rg_pc_BITS_63_TO_2_0_EQ_imem_rg_cache_add_ETC___d1294 &&
imem_rg_cache_b16[1:0] != 2'b11) ;
assign NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1345 =
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1302 ||
imem_rg_pc[1:0] == 2'b0 &&
imem_rg_pc_BITS_63_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 &&
near_mem$imem_instr[1:0] == 2'b11 ;
assign NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1347 =
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1345 ||
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1316 ||
imem_rg_pc[1:0] == 2'b0 &&
imem_rg_pc_BITS_63_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 &&
near_mem$imem_instr[1:0] != 2'b11 ;
assign NOT_rg_next_pc_837_BITS_1_TO_0_838_EQ_0b0_839__ETC___d1846 =
rg_next_pc[1:0] != 2'b0 && near_mem$imem_valid &&
addr_of_b32__h30759 == near_mem$imem_pc &&
near_mem$imem_instr[17:16] == 2'b11 ;
assign NOT_soc_map_m_pc_reset_value__492_BITS_1_TO_0__ETC___d1505 =
soc_map$m_pc_reset_value[1:0] != 2'b0 && near_mem$imem_valid &&
addr_of_b32__h18508 == near_mem$imem_pc &&
near_mem$imem_instr[17:16] == 2'b11 ;
assign NOT_stage1_rg_full_03_87_OR_stage1_rg_stage_in_ETC___d1557 =
(!stage1_rg_full ||
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d1514 ||
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 ==
4'd0) &&
(!stage1_rg_full ||
!stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d483) ;
assign NOT_stage1_rg_full_03_87_OR_stage1_rg_stage_in_ETC___d1559 =
(!stage1_rg_full ||
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d1514) &&
(!stage1_rg_full ||
!stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d483) ;
assign NOT_stage1_rg_stage_input_04_BITS_112_TO_110_3_ETC___d315 =
(stage1_rg_stage_input[112:110] != 3'b0 ||
stage1_rg_stage_input[151:145] == 7'b0110011 &&
stage1_rg_stage_input[262]) &&
(stage1_rg_stage_input[112:110] != 3'b0 ||
stage1_rg_stage_input[151:145] != 7'b0110011 ||
!stage1_rg_stage_input[262]) &&
stage1_rg_stage_input[112:110] != 3'b010 &&
stage1_rg_stage_input[112:110] != 3'b011 &&
stage1_rg_stage_input[112:110] != 3'b100 &&
stage1_rg_stage_input[112:110] != 3'b110 &&
stage1_rg_stage_input[112:110] != 3'b111 ;
assign NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d1894 =
(!stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ||
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d1522) &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 !=
4'd0 ||
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413 ;
assign NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d1898 =
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d1894 &&
stage1_rg_full &&
(!stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ||
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d1522 ||
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413) &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 ==
2'd0 &&
!stage3_rg_full ;
assign NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d417 =
!stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d191 !=
2'd1 ||
!IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d208 &&
!IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d210 ;
assign NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d617 =
(!stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d483) &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 !=
4'd0 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 !=
4'd1 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 !=
4'd2 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 !=
4'd3 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 !=
4'd4 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 !=
4'd5 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 !=
4'd6 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 !=
4'd7 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 !=
4'd8 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 !=
4'd9 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 !=
4'd10 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 !=
4'd11 ;
assign NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d629 =
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d417 &&
(!stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d483) &&
IF_NOT_stage1_rg_full_03_87_OR_NOT_stage1_rg_s_ETC___d626 ==
2'd3 ;
assign NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d633 =
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d417 &&
(!stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d483) &&
IF_NOT_stage1_rg_full_03_87_OR_NOT_stage1_rg_s_ETC___d626 ==
2'd0 ;
assign NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d639 =
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d417 &&
(!stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d483) &&
IF_NOT_stage1_rg_full_03_87_OR_NOT_stage1_rg_s_ETC___d626 !=
2'd3 &&
IF_NOT_stage1_rg_full_03_87_OR_NOT_stage1_rg_s_ETC___d626 !=
2'd0 ;
assign NOT_stageF_branch_predictor_predict_rsp_NOT_im_ETC___d1712 =
stageF_branch_predictor$predict_rsp[1:0] != 2'b0 &&
near_mem$imem_valid &&
addr_of_b32__h21579 == near_mem$imem_pc &&
near_mem$imem_instr[17:16] == 2'b11 ;
assign SEXT_stage1_rg_stage_input_04_BITS_87_TO_76_02___d654 =
{ {52{stage1_rg_stage_input_BITS_87_TO_76__q21[11]}},
stage1_rg_stage_input_BITS_87_TO_76__q21 } ;
assign SEXT_stageD_rg_data_21_BIT_76_38_CONCAT_stageD_ETC___d1016 =
{ {4{offset__h12155[8]}}, offset__h12155 } ;
assign SEXT_stageD_rg_data_21_BIT_76_38_CONCAT_stageD_ETC___d991 =
{ {9{offset__h11524[11]}}, offset__h11524 } ;
assign _theResult_____1_fst__h8779 =
(stage1_rg_stage_input[112:110] == 3'b0 &&
stage1_rg_stage_input[151:145] == 7'b0110011 &&
stage1_rg_stage_input[262]) ?
rd_val___1__h8775 :
_theResult_____1_fst__h8786 ;
assign _theResult_____1_fst__h8814 =
rs1_val_bypassed__h4837 & _theResult___snd__h10041 ;
assign _theResult____h22748 =
(delta_CPI_instrs__h22747 == 64'd0) ?
delta_CPI_instrs___1__h22783 :
delta_CPI_instrs__h22747 ;
assign _theResult____h5108 = x_out_data_to_stage1_instr__h10611 ;
assign _theResult___fst__h8884 =
(stage1_rg_stage_input[112:110] == 3'b001 &&
!stage1_rg_stage_input[257]) ?
rd_val___1__h10101 :
_theResult___fst__h8891 ;
assign _theResult___fst__h8891 =
stage1_rg_stage_input[262] ?
rd_val___1__h10183 :
rd_val___1__h10154 ;
assign _theResult___fst__h8951 =
{ {32{rs1_val_bypassed837_BITS_31_TO_0_SRL_rs2_val_b_ETC__q9[31]}},
rs1_val_bypassed837_BITS_31_TO_0_SRL_rs2_val_b_ETC__q9 } ;
assign _theResult___snd__h10041 =
(stage1_rg_stage_input[151:145] == 7'b0010011) ?
SEXT_stage1_rg_stage_input_04_BITS_87_TO_76_02___d654 :
rs2_val_bypassed__h4843 ;
assign addr_of_b32___1__h18620 = addr_of_b32__h18508 + 64'd4 ;
assign addr_of_b32___1__h21691 = addr_of_b32__h21579 + 64'd4 ;
assign addr_of_b32___1__h30871 = addr_of_b32__h30759 + 64'd4 ;
assign addr_of_b32__h18508 = { soc_map$m_pc_reset_value[63:2], 2'd0 } ;
assign addr_of_b32__h21579 =
{ stageF_branch_predictor$predict_rsp[63:2], 2'd0 } ;
assign addr_of_b32__h30759 = { rg_next_pc[63:2], 2'd0 } ;
assign alu_outputs___1_addr__h7863 =
IF_stage1_rg_stage_input_04_BITS_112_TO_110_33_ETC___d279 ?
branch_target__h7840 :
x_out_cf_info_fallthru_PC__h9707 ;
assign alu_outputs___1_addr__h8135 =
rs1_val_bypassed__h4837 +
{ {52{stage1_rg_stage_input_BITS_75_TO_64__q7[11]}},
stage1_rg_stage_input_BITS_75_TO_64__q7 } ;
assign alu_outputs___1_exc_code__h8320 =
(stage1_rg_stage_input[112:110] == 3'b0) ?
((stage1_rg_stage_input[144:140] == 5'd0 &&
stage1_rg_stage_input[139:135] == 5'd0) ?
CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_C_ETC__q4 :
4'd2) :
4'd2 ;
assign alu_outputs___1_val1__h7990 =
(stage1_rg_stage_input[112:110] == 3'b001) ?
rd_val__h9938 :
(stage1_rg_stage_input[262] ? rd_val__h10011 : rd_val__h9989) ;
assign alu_outputs___1_val1__h8026 =
(stage1_rg_stage_input[112:110] == 3'b0 &&
(stage1_rg_stage_input[151:145] != 7'b0110011 ||
!stage1_rg_stage_input[262])) ?
rd_val___1__h8767 :
_theResult_____1_fst__h8779 ;
assign alu_outputs___1_val1__h8047 =
(stage1_rg_stage_input[112:110] == 3'b0) ?
rd_val___1__h10070 :
_theResult___fst__h8884 ;
assign alu_outputs___1_val1__h8324 =
stage1_rg_stage_input[112] ?
{ 59'd0, stage1_rg_stage_input[139:135] } :
rs1_val_bypassed__h4837 ;
assign alu_outputs___1_val1__h8344 =
{ 57'd0, stage1_rg_stage_input[104:98] } ;
assign alu_outputs_cf_info_fallthru_PC__h9699 =
x_out_cf_info_fallthru_PC__h9707 ;
assign alu_outputs_cf_info_taken_PC__h9700 = x_out_cf_info_taken_PC__h9708 ;
assign branch_target__h7840 =
stage1_rg_stage_input[401:338] +
{ {51{stage1_rg_stage_input_BITS_63_TO_51__q1[12]}},
stage1_rg_stage_input_BITS_63_TO_51__q1 } ;
assign cpi__h22750 = x__h22749 / 64'd10 ;
assign cpifrac__h22751 = x__h22749 % 64'd10 ;
assign csr_regfile_RDY_server_reset_request_put__447__ETC___d1459 =
csr_regfile$RDY_server_reset_request_put &&
f_reset_reqs$EMPTY_N &&
stageF_f_reset_reqs$FULL_N &&
stageD_f_reset_reqs$FULL_N &&
stage1_f_reset_reqs$FULL_N &&
stage2_f_reset_reqs$FULL_N &&
stage3_f_reset_reqs$FULL_N ;
assign csr_regfile_RDY_server_reset_response_get__466_ETC___d1487 =
csr_regfile$RDY_server_reset_response_get &&
stageF_f_reset_rsps$EMPTY_N &&
stageD_f_reset_rsps$EMPTY_N &&
stage1_f_reset_rsps$EMPTY_N &&
stage2_f_reset_rsps$EMPTY_N &&
stage3_f_reset_rsps$EMPTY_N &&
f_reset_rsps_i_notFull__472_AND_NOT_rg_run_on__ETC___d1481 ;
assign csr_regfile_interrupt_pending_rg_cur_priv_1_50_ETC___d1694 =
(csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) &&
(!stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ||
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d1522 ||
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413) ;
assign csr_regfile_interrupt_pending_rg_cur_priv_1_50_ETC___d1698 =
csr_regfile_interrupt_pending_rg_cur_priv_1_50_ETC___d1694 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 !=
2'd2 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 !=
2'd0 ||
!stage1_rg_full ||
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d1514 ;
assign csr_regfile_interrupt_pending_rg_cur_priv_1_50_ETC___d1701 =
(csr_regfile_interrupt_pending_rg_cur_priv_1_50_ETC___d1698 ||
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 ==
4'd0 ||
IF_IF_stage1_rg_stage_input_04_BITS_151_TO_145_ETC___d911) &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49 ;
assign csr_regfile_interrupt_pending_rg_cur_priv_1_50_ETC___d1736 =
csr_regfile_interrupt_pending_rg_cur_priv_1_50_ETC___d1698 ||
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 ==
4'd0 ||
IF_IF_stage1_rg_stage_input_04_BITS_151_TO_145_ETC___d911 ||
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1529 &&
stageD_rg_full ;
assign csr_regfile_read_csr_mcycle__0_MINUS_rg_start__ETC___d1774 =
delta_CPI_cycles__h22746 * 64'd10 ;
assign csr_regfile_read_misa__9_BIT_2_26_AND_stageD_r_ETC___d1001 =
csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[79:76] == 4'b1000 &&
stageD_rg_data[75:71] != 5'd0 ;
assign csr_regfile_read_misa__9_BIT_2_26_AND_stageD_r_ETC___d1007 =
csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[79:76] == 4'b1001 &&
stageD_rg_data[75:71] != 5'd0 ;
assign cur_verbosity__h3317 =
(csr_regfile$read_csr_minstret < cfg_logdelay) ?
4'd0 :
cfg_verbosity ;
assign d_instr__h16678 =
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1302 ?
instr_out___1__h16680 :
IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg_p_ETC___d1320 ;
assign data_to_stage2_addr__h7698 = x_out_data_to_stage2_addr__h7708 ;
assign data_to_stage2_rd__h7697 =
(stage1_rg_stage_input[151:145] == 7'b1100011) ?
5'd0 :
stage1_rg_stage_input[144:140] ;
assign decoded_instr_funct10__h20268 =
{ _theResult____h5108[31:25], _theResult____h5108[14:12] } ;
assign decoded_instr_imm12_S__h20270 =
{ _theResult____h5108[31:25], _theResult____h5108[11:7] } ;
assign decoded_instr_imm13_SB__h20271 =
{ _theResult____h5108[31],
_theResult____h5108[7],
_theResult____h5108[30:25],
_theResult____h5108[11:8],
1'b0 } ;
assign decoded_instr_imm21_UJ__h20273 =
{ _theResult____h5108[31],
_theResult____h5108[19:12],
_theResult____h5108[20],
_theResult____h5108[30:21],
1'b0 } ;
assign delta_CPI_cycles__h22746 =
csr_regfile$read_csr_mcycle - rg_start_CPI_cycles ;
assign delta_CPI_instrs___1__h22783 = delta_CPI_instrs__h22747 + 64'd1 ;
assign delta_CPI_instrs__h22747 =
csr_regfile$read_csr_minstret - rg_start_CPI_instrs ;
assign f_reset_rsps_i_notFull__472_AND_NOT_rg_run_on__ETC___d1481 =
f_reset_rsps$FULL_N &&
(!rg_run_on_reset ||
imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d1477 &&
stageF_branch_predictor$RDY_predict_req) ;
assign fall_through_pc__h7648 =
stage1_rg_stage_input[401:338] +
(stage1_rg_stage_input[333] ? 64'd4 : 64'd2) ;
assign imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1334 =
(imem_rg_pc[1:0] == 2'b0 ||
!imem_rg_pc_BITS_63_TO_2_0_EQ_imem_rg_cache_add_ETC___d1294 ||
!near_mem_imem_pc__1_EQ_imem_rg_pc_PLUS_2_296___d1297 ||
imem_rg_cache_b16[1:0] != 2'b11) &&
(imem_rg_pc[1:0] != 2'b0 ||
!imem_rg_pc_BITS_63_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 ||
near_mem$imem_instr[1:0] != 2'b11) ;
assign imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1338 =
imem_rg_pc[1:0] == 2'b0 ||
(!imem_rg_pc_BITS_63_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 ||
near_mem$imem_instr[17:16] == 2'b11) &&
(!imem_rg_pc_BITS_63_TO_2_0_EQ_imem_rg_cache_add_ETC___d1294 ||
imem_rg_cache_b16[1:0] == 2'b11) ;
assign imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1341 =
imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1334 &&
imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1338 &&
(imem_rg_pc[1:0] != 2'b0 ||
!imem_rg_pc_BITS_63_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 ||
near_mem$imem_instr[1:0] == 2'b11) ;
assign imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d1477 =
imem_rg_pc[1:0] == 2'b0 || !near_mem$imem_valid ||
!imem_rg_pc_BITS_63_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 ||
near_mem$imem_instr[17:16] != 2'b11 ;
assign imem_rg_pc_BITS_63_TO_2_0_EQ_imem_rg_cache_add_ETC___d1294 =
imem_rg_pc[63:2] == imem_rg_cache_addr[63:2] ;
assign imem_rg_pc_BITS_63_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 =
imem_rg_pc[63:2] == near_mem$imem_pc[63:2] ;
assign imm12__h10817 = { 4'd0, offset__h10689 } ;
assign imm12__h11154 = { 5'd0, offset__h11096 } ;
assign imm12__h12790 = { {6{imm6__h12788[5]}}, imm6__h12788 } ;
assign imm12__h13459 = { {2{nzimm10__h13457[9]}}, nzimm10__h13457 } ;
assign imm12__h13674 = { 2'd0, nzimm10__h13672 } ;
assign imm12__h13870 = { 6'b0, imm6__h12788 } ;
assign imm12__h14207 = { 6'b010000, imm6__h12788 } ;
assign imm12__h15828 = { 3'd0, offset__h15742 } ;
assign imm12__h16180 = { 4'd0, offset__h16114 } ;
assign imm20__h12918 = { {14{imm6__h12788[5]}}, imm6__h12788 } ;
assign imm6__h12788 = { stageD_rg_data[76], stageD_rg_data[70:66] } ;
assign instr___1__h10647 =
(csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
stageD_rg_data[75:71] != 5'd0 &&
stageD_rg_data[79:77] == 3'b010) ?
instr__h10816 :
IF_csr_regfile_read_misa__9_BIT_2_26_AND_stage_ETC___d1194 ;
assign instr__h10816 =
{ imm12__h10817, 8'd18, stageD_rg_data[75:71], 7'b0000011 } ;
assign instr__h10961 =
{ 4'd0,
stageD_rg_data[72:71],
stageD_rg_data[76],
stageD_rg_data[70:66],
8'd18,
offset_BITS_4_TO_0___h11085,
7'b0100011 } ;
assign instr__h11153 =
{ imm12__h11154, rs1__h11155, 3'b010, rd__h11156, 7'b0000011 } ;
assign instr__h11348 =
{ 5'd0,
stageD_rg_data[69],
stageD_rg_data[76],
rd__h11156,
rs1__h11155,
3'b010,
offset_BITS_4_TO_0___h11516,
7'b0100011 } ;
assign instr__h11577 =
{ SEXT_stageD_rg_data_21_BIT_76_38_CONCAT_stageD_ETC___d991[20],
SEXT_stageD_rg_data_21_BIT_76_38_CONCAT_stageD_ETC___d991[10:1],
SEXT_stageD_rg_data_21_BIT_76_38_CONCAT_stageD_ETC___d991[11],
SEXT_stageD_rg_data_21_BIT_76_38_CONCAT_stageD_ETC___d991[19:12],
12'd111 } ;
assign instr__h12030 = { 12'd0, stageD_rg_data[75:71], 15'd103 } ;
assign instr__h12146 = { 12'd0, stageD_rg_data[75:71], 15'd231 } ;
assign instr__h12211 =
{ SEXT_stageD_rg_data_21_BIT_76_38_CONCAT_stageD_ETC___d1016[12],
SEXT_stageD_rg_data_21_BIT_76_38_CONCAT_stageD_ETC___d1016[10:5],
5'd0,
rs1__h11155,
3'b0,
SEXT_stageD_rg_data_21_BIT_76_38_CONCAT_stageD_ETC___d1016[4:1],
SEXT_stageD_rg_data_21_BIT_76_38_CONCAT_stageD_ETC___d1016[11],
7'b1100011 } ;
assign instr__h12528 =
{ SEXT_stageD_rg_data_21_BIT_76_38_CONCAT_stageD_ETC___d1016[12],
SEXT_stageD_rg_data_21_BIT_76_38_CONCAT_stageD_ETC___d1016[10:5],
5'd0,
rs1__h11155,
3'b001,
SEXT_stageD_rg_data_21_BIT_76_38_CONCAT_stageD_ETC___d1016[4:1],
SEXT_stageD_rg_data_21_BIT_76_38_CONCAT_stageD_ETC___d1016[11],
7'b1100011 } ;
assign instr__h12866 =
{ imm12__h12790, 8'd0, stageD_rg_data[75:71], 7'b0010011 } ;
assign instr__h13050 =
{ imm20__h12918, stageD_rg_data[75:71], 7'b0110111 } ;
assign instr__h13179 =
{ imm12__h12790,
stageD_rg_data[75:71],
3'b0,
stageD_rg_data[75:71],
7'b0010011 } ;
assign instr__h13406 =
{ imm12__h12790,
stageD_rg_data[75:71],
3'b0,
stageD_rg_data[75:71],
7'b0011011 } ;
assign instr__h13661 =
{ imm12__h13459,
stageD_rg_data[75:71],
3'b0,
stageD_rg_data[75:71],
7'b0010011 } ;
assign instr__h13833 = { imm12__h13674, 8'd16, rd__h11156, 7'b0010011 } ;
assign instr__h14002 =
{ imm12__h13870,
stageD_rg_data[75:71],
3'b001,
stageD_rg_data[75:71],
7'b0010011 } ;
assign instr__h14191 =
{ imm12__h13870, rs1__h11155, 3'b101, rs1__h11155, 7'b0010011 } ;
assign instr__h14380 =
{ imm12__h14207, rs1__h11155, 3'b101, rs1__h11155, 7'b0010011 } ;
assign instr__h14497 =
{ imm12__h12790, rs1__h11155, 3'b111, rs1__h11155, 7'b0010011 } ;
assign instr__h14675 =
{ 7'b0,
stageD_rg_data[70:66],
8'd0,
stageD_rg_data[75:71],
7'b0110011 } ;
assign instr__h14794 =
{ 7'b0,
stageD_rg_data[70:66],
stageD_rg_data[75:71],
3'b0,
stageD_rg_data[75:71],
7'b0110011 } ;
assign instr__h14889 =
{ 7'b0,
rd__h11156,
rs1__h11155,
3'b111,
rs1__h11155,
7'b0110011 } ;
assign instr__h15025 =
{ 7'b0,
rd__h11156,
rs1__h11155,
3'b110,
rs1__h11155,
7'b0110011 } ;
assign instr__h15161 =
{ 7'b0,
rd__h11156,
rs1__h11155,
3'b100,
rs1__h11155,
7'b0110011 } ;
assign instr__h15297 =
{ 7'b0100000,
rd__h11156,
rs1__h11155,
3'b0,
rs1__h11155,
7'b0110011 } ;
assign instr__h15435 =
{ 7'b0,
rd__h11156,
rs1__h11155,
3'b0,
rs1__h11155,
7'b0111011 } ;
assign instr__h15573 =
{ 7'b0100000,
rd__h11156,
rs1__h11155,
3'b0,
rs1__h11155,
7'b0111011 } ;
assign instr__h15731 =
{ 12'b000000000001,
stageD_rg_data[75:71],
3'b0,
stageD_rg_data[75:71],
7'b1110011 } ;
assign instr__h15827 =
{ imm12__h15828, 8'd19, stageD_rg_data[75:71], 7'b0000011 } ;
assign instr__h15980 =
{ 3'd0,
stageD_rg_data[73:71],
stageD_rg_data[76],
stageD_rg_data[70:66],
8'd19,
offset_BITS_4_TO_0___h16455,
7'b0100011 } ;
assign instr__h16179 =
{ imm12__h16180, rs1__h11155, 3'b011, rd__h11156, 7'b0000011 } ;
assign instr__h16330 =
{ 4'd0,
stageD_rg_data[70:69],
stageD_rg_data[76],
rd__h11156,
rs1__h11155,
3'b011,
offset_BITS_4_TO_0___h16455,
7'b0100011 } ;
assign instr_out___1__h16680 =
{ near_mem$imem_instr[15:0], imem_rg_cache_b16 } ;
assign instr_out___1__h16702 = { 16'b0, near_mem$imem_instr[15:0] } ;
assign near_mem_imem_pc__1_EQ_imem_rg_pc_PLUS_2_296___d1297 =
near_mem$imem_pc == imem_rg_pc + 64'd2 ;
assign near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d1443 =
near_mem$imem_valid &&
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1347 &&
near_mem$imem_exc &&
near_mem$imem_exc_code != 4'd0 &&
near_mem$imem_exc_code != 4'd1 &&
near_mem$imem_exc_code != 4'd2 &&
near_mem$imem_exc_code != 4'd3 &&
near_mem$imem_exc_code != 4'd4 &&
near_mem$imem_exc_code != 4'd5 &&
near_mem$imem_exc_code != 4'd6 &&
near_mem$imem_exc_code != 4'd7 &&
near_mem$imem_exc_code != 4'd8 &&
near_mem$imem_exc_code != 4'd9 &&
near_mem$imem_exc_code != 4'd11 &&
near_mem$imem_exc_code != 4'd12 &&
near_mem$imem_exc_code != 4'd13 &&
near_mem$imem_exc_code != 4'd15 ;
assign new_epoch__h18044 = rg_epoch + 2'd1 ;
assign next_pc___1__h9323 = stage1_rg_stage_input[401:338] + 64'd2 ;
assign next_pc__h7649 = x_out_next_pc__h7665 ;
assign next_pc__h7869 =
stage1_rg_stage_input[401:338] +
{ {43{stage1_rg_stage_input_BITS_30_TO_10__q2[20]}},
stage1_rg_stage_input_BITS_30_TO_10__q2 } ;
assign next_pc__h7896 =
{ IF_stage1_rg_stage_input_04_BITS_139_TO_135_07_ETC___d655[63:1],
1'd0 } ;
assign next_pc__h9320 = stage1_rg_stage_input[401:338] + 64'd4 ;
assign nzimm10__h13457 =
{ stageD_rg_data[76],
stageD_rg_data[68:67],
stageD_rg_data[69],
stageD_rg_data[66],
stageD_rg_data[70],
4'b0 } ;
assign nzimm10__h13672 =
{ stageD_rg_data[74:71],
stageD_rg_data[76:75],
stageD_rg_data[69],
stageD_rg_data[70],
2'b0 } ;
assign offset_BITS_4_TO_0___h11085 = { stageD_rg_data[75:73], 2'b0 } ;
assign offset_BITS_4_TO_0___h11516 =
{ stageD_rg_data[75:74], stageD_rg_data[70], 2'b0 } ;
assign offset_BITS_4_TO_0___h16455 = { stageD_rg_data[75:74], 3'b0 } ;
assign offset__h10689 =
{ stageD_rg_data[67:66],
stageD_rg_data[76],
stageD_rg_data[70:68],
2'b0 } ;
assign offset__h11096 =
{ stageD_rg_data[69],
stageD_rg_data[76:74],
stageD_rg_data[70],
2'b0 } ;
assign offset__h11524 =
{ stageD_rg_data[76],
stageD_rg_data[72],
stageD_rg_data[74:73],
stageD_rg_data[70],
stageD_rg_data[71],
stageD_rg_data[66],
stageD_rg_data[75],
stageD_rg_data[69:67],
1'b0 } ;
assign offset__h12155 =
{ stageD_rg_data[76],
stageD_rg_data[70:69],
stageD_rg_data[66],
stageD_rg_data[75:74],
stageD_rg_data[68:67],
1'b0 } ;
assign offset__h15742 =
{ stageD_rg_data[68:66],
stageD_rg_data[76],
stageD_rg_data[70:69],
3'b0 } ;
assign offset__h16114 =
{ stageD_rg_data[70:69], stageD_rg_data[76:74], 3'b0 } ;
assign rd__h11156 = { 2'b01, stageD_rg_data[68:66] } ;
assign rd_val___1__h10070 =
{ {32{IF_stage1_rg_stage_input_04_BITS_139_TO_135_07_ETC__q22[31]}},
IF_stage1_rg_stage_input_04_BITS_139_TO_135_07_ETC__q22 } ;
assign rd_val___1__h10101 = { {32{x__h10104[31]}}, x__h10104 } ;
assign rd_val___1__h10154 = { {32{x__h10157[31]}}, x__h10157 } ;
assign rd_val___1__h10183 = { {32{tmp__h10182[31]}}, tmp__h10182 } ;
assign rd_val___1__h10235 =
{ {32{rs1_val_bypassed837_BITS_31_TO_0_PLUS_rs2_val__ETC__q10[31]}},
rs1_val_bypassed837_BITS_31_TO_0_PLUS_rs2_val__ETC__q10 } ;
assign rd_val___1__h10283 =
{ {32{rs1_val_bypassed837_BITS_31_TO_0_MINUS_rs2_val_ETC__q11[31]}},
rs1_val_bypassed837_BITS_31_TO_0_MINUS_rs2_val_ETC__q11 } ;
assign rd_val___1__h10289 = { {32{x__h10292[31]}}, x__h10292 } ;
assign rd_val___1__h10334 = { {32{x__h10337[31]}}, x__h10337 } ;
assign rd_val___1__h8767 =
rs1_val_bypassed__h4837 + _theResult___snd__h10041 ;
assign rd_val___1__h8775 =
rs1_val_bypassed__h4837 - _theResult___snd__h10041 ;
assign rd_val___1__h8782 =
((rs1_val_bypassed__h4837 ^ 64'h8000000000000000) <
(_theResult___snd__h10041 ^ 64'h8000000000000000)) ?
64'd1 :
64'd0 ;
assign rd_val___1__h8789 =
(rs1_val_bypassed__h4837 < _theResult___snd__h10041) ?
64'd1 :
64'd0 ;
assign rd_val___1__h8796 =
rs1_val_bypassed__h4837 ^ _theResult___snd__h10041 ;
assign rd_val___1__h8803 =
rs1_val_bypassed__h4837 | _theResult___snd__h10041 ;
assign rd_val__h10011 =
rs1_val_bypassed__h4837 >> shamt__h7977 |
~(64'hFFFFFFFFFFFFFFFF >> shamt__h7977) &
{64{rs1_val_bypassed__h4837[63]}} ;
assign rd_val__h7550 =
(stage3_rg_full && stage3_rg_stage3[69] &&
stage3_rg_stage3[68:64] == stage1_rg_stage_input[139:135]) ?
stage3_rg_stage3[63:0] :
gpr_regfile$read_rs1 ;
assign rd_val__h7624 =
(stage3_rg_full && stage3_rg_stage3[69] &&
stage3_rg_stage3[68:64] == stage1_rg_stage_input[134:130]) ?
stage3_rg_stage3[63:0] :
gpr_regfile$read_rs2 ;
assign rd_val__h8075 = { {32{v32__h8073[31]}}, v32__h8073 } ;
assign rd_val__h8089 = stage1_rg_stage_input[401:338] + rd_val__h8075 ;
assign rd_val__h9938 = rs1_val_bypassed__h4837 << shamt__h7977 ;
assign rd_val__h9989 = rs1_val_bypassed__h4837 >> shamt__h7977 ;
assign rg_cur_priv_1_EQ_0b11_06_OR_rg_cur_priv_1_EQ_0_ETC___d518 =
(rg_cur_priv == 2'b11 ||
rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[21] ||
rg_cur_priv == 2'b0 && csr_regfile$read_misa[13]) &&
stage1_rg_stage_input[87:76] == 12'b000100000101 ;
assign rg_state_0_EQ_12_7_AND_csr_regfile_wfi_resume__ETC___d1885 =
rg_state == 4'd12 && csr_regfile$wfi_resume &&
(!stageF_rg_full ||
near_mem$imem_valid &&
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1347) ;
assign rg_state_0_EQ_3_544_AND_NOT_csr_regfile_interr_ETC___d1750 =
rg_state == 4'd3 &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1746 &&
!stage3_rg_full &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 ==
2'd0 &&
stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413 ;
assign rg_state_0_EQ_3_544_AND_NOT_csr_regfile_interr_ETC___d1861 =
rg_state_0_EQ_3_544_AND_NOT_csr_regfile_interr_ETC___d1750 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 ==
4'd6 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1347) ;
assign rg_state_0_EQ_3_544_AND_NOT_csr_regfile_interr_ETC___d1870 =
rg_state_0_EQ_3_544_AND_NOT_csr_regfile_interr_ETC___d1750 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 ==
4'd5 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1347) ;
assign rg_state_0_EQ_3_544_AND_stage3_rg_full_1_OR_NO_ETC___d1554 =
rg_state == 4'd3 &&
(stage3_rg_full ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 !=
2'd0 ||
stage1_rg_full ||
stageD_rg_full ||
stageF_rg_full) &&
(stage3_rg_full ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 !=
2'd3) &&
stage3_rg_full_1_OR_NOT_IF_stage2_rg_full_00_T_ETC___d1552 ;
assign rg_state_0_EQ_5_889_AND_NOT_stageF_rg_full_324_ETC___d1890 =
rg_state == 4'd5 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1347) ;
assign rg_state_0_EQ_8_834_AND_NOT_stageF_rg_full_324_ETC___d1835 =
rg_state == 4'd8 &&
(!stageF_rg_full ||
near_mem$imem_valid &&
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1347) ;
assign rg_trap_info_760_BITS_131_TO_68_761_EQ_csr_reg_ETC___d1770 =
rg_trap_info[131:68] == csr_regfile$csr_trap_actions[193:130] ;
assign rs1__h11155 = { 2'b01, stageD_rg_data[73:71] } ;
assign rs1_val__h23220 =
(rg_trap_instr[14:12] == 3'b001) ?
rg_csr_val1 :
{ 59'd0, rg_trap_instr[19:15] } ;
assign rs1_val_bypassed837_BITS_31_TO_0_MINUS_rs2_val_ETC__q11 =
rs1_val_bypassed__h4837[31:0] - rs2_val_bypassed__h4843[31:0] ;
assign rs1_val_bypassed837_BITS_31_TO_0_PLUS_rs2_val__ETC__q10 =
rs1_val_bypassed__h4837[31:0] + rs2_val_bypassed__h4843[31:0] ;
assign rs1_val_bypassed837_BITS_31_TO_0_SRL_rs2_val_b_ETC__q9 =
rs1_val_bypassed__h4837[31:0] >> rs2_val_bypassed__h4843[4:0] |
~(32'hFFFFFFFF >> rs2_val_bypassed__h4843[4:0]) &
{32{rs1_val_bypassed837_BITS_31_TO_0__q8[31]}} ;
assign rs1_val_bypassed837_BITS_31_TO_0__q8 =
rs1_val_bypassed__h4837[31:0] ;
assign rs1_val_bypassed__h4837 =
(stage1_rg_stage_input[139:135] == 5'd0) ? 64'd0 : val__h7552 ;
assign rs2_val_bypassed__h4843 =
(stage1_rg_stage_input[134:130] == 5'd0) ? 64'd0 : val__h7626 ;
assign shamt__h7977 =
(stage1_rg_stage_input[151:145] == 7'b0010011) ?
stage1_rg_stage_input[81:76] :
rs2_val_bypassed__h4843[5:0] ;
assign stage1_rg_full_03_AND_NOT_stage1_rg_stage_inpu_ETC___d486 =
stage1_rg_full &&
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d417 &&
(!stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d483) ;
assign stage1_rg_stage_input_04_BITS_112_TO_110_33_EQ_ETC___d437 =
stage1_rg_stage_input[112:110] == 3'b0 &&
(stage1_rg_stage_input[151:145] != 7'b0110011 ||
!stage1_rg_stage_input[262]) ||
stage1_rg_stage_input[112:110] == 3'b0 &&
stage1_rg_stage_input[151:145] == 7'b0110011 &&
stage1_rg_stage_input[262] ||
stage1_rg_stage_input[112:110] == 3'b010 ||
stage1_rg_stage_input[112:110] == 3'b011 ||
stage1_rg_stage_input[112:110] == 3'b100 ||
stage1_rg_stage_input[112:110] == 3'b110 ||
stage1_rg_stage_input[112:110] == 3'b111 ;
assign stage1_rg_stage_input_04_BITS_151_TO_145_31_EQ_ETC___d430 =
stage1_rg_stage_input[151:145] == 7'b0110011 &&
stage1_rg_stage_input[104:98] == 7'b0000001 ||
stage1_rg_stage_input[151:145] == 7'b0111011 &&
stage1_rg_stage_input[104:98] == 7'b0000001 ||
(stage1_rg_stage_input[151:145] == 7'b0010011 ||
stage1_rg_stage_input[151:145] == 7'b0110011) &&
(stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b101) ;
assign stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d1517 =
(stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d1514 ||
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 ==
4'd0) &&
(!stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d483) ;
assign stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 =
stage1_rg_stage_input[335:334] == rg_epoch ;
assign stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d224 =
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d191 ==
2'd1 &&
(IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d208 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d210) ;
assign stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d861 =
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 !=
4'd0 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 !=
4'd1 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 !=
4'd2 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 !=
4'd3 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 !=
4'd4 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 !=
4'd5 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 !=
4'd6 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 !=
4'd7 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 !=
4'd8 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 !=
4'd9 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 !=
4'd10 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 !=
4'd11 ;
assign stage1_rg_stage_input_BITS_30_TO_10__q2 =
stage1_rg_stage_input[30:10] ;
assign stage1_rg_stage_input_BITS_63_TO_51__q1 =
stage1_rg_stage_input[63:51] ;
assign stage1_rg_stage_input_BITS_75_TO_64__q7 =
stage1_rg_stage_input[75:64] ;
assign stage1_rg_stage_input_BITS_87_TO_76__q21 =
stage1_rg_stage_input[87:76] ;
assign stage3_rg_full_1_OR_NOT_IF_stage2_rg_full_00_T_ETC___d1552 =
stage3_rg_full ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 !=
2'd0 ||
!stage1_rg_full ||
!stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d483 ;
assign stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1356 =
stageF_rg_full && near_mem$imem_valid &&
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1347 &&
!near_mem$imem_exc ;
assign stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1362 =
stageF_rg_full && near_mem$imem_valid &&
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1347 &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd0 ;
assign stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1366 =
stageF_rg_full && near_mem$imem_valid &&
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1347 &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd1 ;
assign stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1370 =
stageF_rg_full && near_mem$imem_valid &&
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1347 &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd2 ;
assign stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1374 =
stageF_rg_full && near_mem$imem_valid &&
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1347 &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd3 ;
assign stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1378 =
stageF_rg_full && near_mem$imem_valid &&
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1347 &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd4 ;
assign stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1382 =
stageF_rg_full && near_mem$imem_valid &&
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1347 &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd5 ;
assign stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1386 =
stageF_rg_full && near_mem$imem_valid &&
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1347 &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd6 ;
assign stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1390 =
stageF_rg_full && near_mem$imem_valid &&
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1347 &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd7 ;
assign stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1394 =
stageF_rg_full && near_mem$imem_valid &&
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1347 &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd8 ;
assign stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1398 =
stageF_rg_full && near_mem$imem_valid &&
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1347 &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd9 ;
assign stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1402 =
stageF_rg_full && near_mem$imem_valid &&
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1347 &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd11 ;
assign stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1406 =
stageF_rg_full && near_mem$imem_valid &&
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1347 &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd12 ;
assign stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1410 =
stageF_rg_full && near_mem$imem_valid &&
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1347 &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd13 ;
assign stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1414 =
stageF_rg_full && near_mem$imem_valid &&
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1347 &&
near_mem$imem_exc &&
near_mem$imem_exc_code == 4'd15 ;
assign sxl__h6149 =
(csr_regfile$read_misa[27:26] == 2'd2) ?
csr_regfile$read_mstatus[35:34] :
2'd0 ;
assign tmp__h10182 =
rs1_val_bypassed__h4837[31:0] >> stage1_rg_stage_input[80:76] |
~(32'hFFFFFFFF >> stage1_rg_stage_input[80:76]) &
{32{rs1_val_bypassed837_BITS_31_TO_0__q8[31]}} ;
assign trap_info_tval__h9527 =
(stage1_rg_stage_input[151:145] != 7'b1101111 &&
stage1_rg_stage_input[151:145] != 7'b1100111 &&
(stage1_rg_stage_input[151:145] != 7'b1110011 ||
stage1_rg_stage_input[112:110] != 3'b0 ||
stage1_rg_stage_input[144:140] != 5'd0 ||
stage1_rg_stage_input[139:135] != 5'd0 ||
stage1_rg_stage_input[87:76] != 12'b0 &&
stage1_rg_stage_input[87:76] != 12'b000000000001)) ?
(stage1_rg_stage_input[333] ?
{ 32'd0, stage1_rg_stage_input[263:232] } :
{ 48'd0, stage1_rg_stage_input[231:216] }) :
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q23 ;
assign uxl__h6150 =
(csr_regfile$read_misa[27:26] == 2'd2) ?
csr_regfile$read_mstatus[33:32] :
2'd0 ;
assign v32__h8073 = { stage1_rg_stage_input[50:31], 12'h0 } ;
assign val__h7552 =
(IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d191 ==
2'd2 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d208) ?
x_out_bypass_rd_val__h7420 :
rd_val__h7550 ;
assign val__h7626 =
(IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d191 ==
2'd2 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d210) ?
x_out_bypass_rd_val__h7420 :
rd_val__h7624 ;
assign value__h9576 =
stage1_rg_stage_input[332] ?
stage1_rg_stage_input[327:264] :
trap_info_tval__h9527 ;
assign x__h10104 =
rs1_val_bypassed__h4837[31:0] << stage1_rg_stage_input[80:76] ;
assign x__h10157 =
rs1_val_bypassed__h4837[31:0] >> stage1_rg_stage_input[80:76] ;
assign x__h10292 =
rs1_val_bypassed__h4837[31:0] << rs2_val_bypassed__h4843[4:0] ;
assign x__h10337 =
rs1_val_bypassed__h4837[31:0] >> rs2_val_bypassed__h4843[4:0] ;
assign x__h22749 =
csr_regfile_read_csr_mcycle__0_MINUS_rg_start__ETC___d1774[63:0] /
_theResult____h22748 ;
assign x_exc_code__h31121 =
(csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending) ?
csr_regfile$interrupt_pending[3:0] :
4'd0 ;
assign x_out_cf_info_fallthru_PC__h9707 =
stage1_rg_stage_input[333] ?
next_pc__h9320 :
next_pc___1__h9323 ;
assign x_out_data_to_stage1_instr__h10611 =
stageD_rg_data[165] ? stageD_rg_data[95:64] : instr___1__h10647 ;
assign x_out_data_to_stage2_rd__h7707 =
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ?
data_to_stage2_rd__h7697 :
5'd0 ;
assign x_out_data_to_stage2_val2__h7710 =
(stage1_rg_stage_input[151:145] == 7'b1100011) ?
branch_target__h7840 :
rs2_val_bypassed__h4843 ;
assign x_out_next_pc__h7665 =
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d480 ?
data_to_stage2_addr__h7698 :
fall_through_pc__h7648 ;
assign x_out_trap_info_exc_code__h9532 =
stage1_rg_stage_input[332] ?
stage1_rg_stage_input[331:328] :
alu_outputs_exc_code__h8364 ;
assign y__h24168 = ~rs1_val__h23899 ;
always@(stage2_rg_stage2)
begin
case (stage2_rg_stage2[199:197])
3'd0, 3'd1, 3'd4:
x_out_data_to_stage3_rd__h7080 = stage2_rg_stage2[196:192];
3'd2: x_out_data_to_stage3_rd__h7080 = 5'd0;
default: x_out_data_to_stage3_rd__h7080 = stage2_rg_stage2[196:192];
endcase
end
always@(stage2_rg_stage2 or stage2_mbox$word or near_mem$dmem_word64)
begin
case (stage2_rg_stage2[199:197])
3'd0, 3'd2:
x_out_data_to_stage3_rd_val__h7081 = stage2_rg_stage2[127:64];
3'd1, 3'd4: x_out_data_to_stage3_rd_val__h7081 = near_mem$dmem_word64;
default: x_out_data_to_stage3_rd_val__h7081 = stage2_mbox$word;
endcase
end
always@(stage2_rg_stage2)
begin
case (stage2_rg_stage2[199:197])
3'd0, 3'd1, 3'd4: x_out_bypass_rd__h7419 = stage2_rg_stage2[196:192];
default: x_out_bypass_rd__h7419 = stage2_rg_stage2[196:192];
endcase
end
always@(stage2_rg_stage2 or stage2_mbox$word)
begin
case (stage2_rg_stage2[199:197])
3'd0, 3'd1, 3'd4: x_out_bypass_rd_val__h7420 = stage2_rg_stage2[127:64];
default: x_out_bypass_rd_val__h7420 = stage2_mbox$word;
endcase
end
always@(rg_trap_instr or rg_csr_val1)
begin
case (rg_trap_instr[14:12])
3'b010, 3'b011: rs1_val__h23899 = rg_csr_val1;
default: rs1_val__h23899 = { 59'd0, rg_trap_instr[19:15] };
endcase
end
always@(rg_cur_priv)
begin
case (rg_cur_priv)
2'b0: CASE_rg_cur_priv_0b0_8_0b1_9_11__q3 = 4'd8;
2'b01: CASE_rg_cur_priv_0b0_8_0b1_9_11__q3 = 4'd9;
default: CASE_rg_cur_priv_0b0_8_0b1_9_11__q3 = 4'd11;
endcase
end
always@(stage1_rg_stage_input or CASE_rg_cur_priv_0b0_8_0b1_9_11__q3)
begin
case (stage1_rg_stage_input[87:76])
12'b0:
CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_C_ETC__q4 =
CASE_rg_cur_priv_0b0_8_0b1_9_11__q3;
12'b000000000001:
CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_C_ETC__q4 = 4'd3;
default: CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_C_ETC__q4 = 4'd2;
endcase
end
always@(stage1_rg_stage_input or alu_outputs___1_exc_code__h8320)
begin
case (stage1_rg_stage_input[151:145])
7'b0000011,
7'b0001111,
7'b0010011,
7'b0010111,
7'b0011011,
7'b0100011,
7'b0110011,
7'b0110111,
7'b0111011,
7'b1100011:
alu_outputs_exc_code__h8364 = 4'd2;
7'b1100111, 7'b1101111: alu_outputs_exc_code__h8364 = 4'd0;
7'b1110011:
alu_outputs_exc_code__h8364 = alu_outputs___1_exc_code__h8320;
default: alu_outputs_exc_code__h8364 = 4'd2;
endcase
end
always@(stage2_rg_stage2 or
IF_stage2_rg_stage2_01_BITS_199_TO_197_02_EQ_3_ETC___d128 or
IF_near_mem_dmem_valid__22_THEN_IF_near_mem_dm_ETC___d125)
begin
case (stage2_rg_stage2[199:197])
3'd0: CASE_stage2_rg_stage2_BITS_199_TO_197_0_2_1_IF_ETC__q5 = 2'd2;
3'd1, 3'd2, 3'd4:
CASE_stage2_rg_stage2_BITS_199_TO_197_0_2_1_IF_ETC__q5 =
IF_near_mem_dmem_valid__22_THEN_IF_near_mem_dm_ETC___d125;
default: CASE_stage2_rg_stage2_BITS_199_TO_197_0_2_1_IF_ETC__q5 =
IF_stage2_rg_stage2_01_BITS_199_TO_197_02_EQ_3_ETC___d128;
endcase
end
always@(stage2_rg_stage2 or
stage2_mbox$valid or near_mem$dmem_valid or near_mem$dmem_exc)
begin
case (stage2_rg_stage2[199:197])
3'd1, 3'd2, 3'd4:
IF_stage2_rg_stage2_01_BITS_199_TO_197_02_EQ_1_ETC___d145 =
!near_mem$dmem_valid || near_mem$dmem_exc;
default: IF_stage2_rg_stage2_01_BITS_199_TO_197_02_EQ_1_ETC___d145 =
!stage2_mbox$valid;
endcase
end
always@(stage2_rg_stage2 or
stage2_mbox$valid or near_mem$dmem_valid or near_mem$dmem_exc)
begin
case (stage2_rg_stage2[199:197])
3'd1, 3'd2, 3'd4:
IF_stage2_rg_stage2_01_BITS_199_TO_197_02_EQ_1_ETC___d154 =
near_mem$dmem_valid && !near_mem$dmem_exc;
default: IF_stage2_rg_stage2_01_BITS_199_TO_197_02_EQ_1_ETC___d154 =
stage2_mbox$valid;
endcase
end
always@(stage2_rg_stage2 or
IF_stage2_rg_stage2_01_BITS_199_TO_197_02_EQ_3_ETC___d128 or
IF_NOT_near_mem_dmem_valid__22_41_OR_NOT_near__ETC___d187)
begin
case (stage2_rg_stage2[199:197])
3'd0: CASE_stage2_rg_stage2_BITS_199_TO_197_0_2_1_IF_ETC__q6 = 2'd2;
3'd1, 3'd4:
CASE_stage2_rg_stage2_BITS_199_TO_197_0_2_1_IF_ETC__q6 =
IF_NOT_near_mem_dmem_valid__22_41_OR_NOT_near__ETC___d187;
3'd2: CASE_stage2_rg_stage2_BITS_199_TO_197_0_2_1_IF_ETC__q6 = 2'd0;
default: CASE_stage2_rg_stage2_BITS_199_TO_197_0_2_1_IF_ETC__q6 =
IF_stage2_rg_stage2_01_BITS_199_TO_197_02_EQ_3_ETC___d128;
endcase
end
always@(stage1_rg_stage_input or
_theResult___fst__h8951 or
rd_val___1__h10235 or
rd_val___1__h10289 or rd_val___1__h10334 or rd_val___1__h10283)
begin
case (stage1_rg_stage_input[97:88])
10'b0: alu_outputs___1_val1__h8068 = rd_val___1__h10235;
10'b0000000001: alu_outputs___1_val1__h8068 = rd_val___1__h10289;
10'b0000000101: alu_outputs___1_val1__h8068 = rd_val___1__h10334;
10'b0100000000: alu_outputs___1_val1__h8068 = rd_val___1__h10283;
default: alu_outputs___1_val1__h8068 = _theResult___fst__h8951;
endcase
end
always@(stage1_rg_stage_input or
IF_stage1_rg_stage_input_04_BITS_139_TO_135_07_ETC___d272 or
IF_stage1_rg_stage_input_04_BITS_139_TO_135_07_ETC___d268 or
IF_stage1_rg_stage_input_04_BITS_139_TO_135_07_ETC___d270)
begin
case (stage1_rg_stage_input[112:110])
3'b0:
IF_stage1_rg_stage_input_04_BITS_112_TO_110_33_ETC___d405 =
!IF_stage1_rg_stage_input_04_BITS_139_TO_135_07_ETC___d268;
3'b001:
IF_stage1_rg_stage_input_04_BITS_112_TO_110_33_ETC___d405 =
IF_stage1_rg_stage_input_04_BITS_139_TO_135_07_ETC___d268;
3'b100:
IF_stage1_rg_stage_input_04_BITS_112_TO_110_33_ETC___d405 =
!IF_stage1_rg_stage_input_04_BITS_139_TO_135_07_ETC___d270;
3'b101:
IF_stage1_rg_stage_input_04_BITS_112_TO_110_33_ETC___d405 =
IF_stage1_rg_stage_input_04_BITS_139_TO_135_07_ETC___d270;
3'b110:
IF_stage1_rg_stage_input_04_BITS_112_TO_110_33_ETC___d405 =
!IF_stage1_rg_stage_input_04_BITS_139_TO_135_07_ETC___d272;
default: IF_stage1_rg_stage_input_04_BITS_112_TO_110_33_ETC___d405 =
stage1_rg_stage_input[112:110] != 3'b111 ||
IF_stage1_rg_stage_input_04_BITS_139_TO_135_07_ETC___d272;
endcase
end
always@(stage1_rg_stage_input or
IF_stage1_rg_stage_input_04_BITS_139_TO_135_07_ETC___d272 or
IF_stage1_rg_stage_input_04_BITS_139_TO_135_07_ETC___d268 or
IF_stage1_rg_stage_input_04_BITS_139_TO_135_07_ETC___d270)
begin
case (stage1_rg_stage_input[112:110])
3'b0:
IF_stage1_rg_stage_input_04_BITS_112_TO_110_33_ETC___d279 =
IF_stage1_rg_stage_input_04_BITS_139_TO_135_07_ETC___d268;
3'b001:
IF_stage1_rg_stage_input_04_BITS_112_TO_110_33_ETC___d279 =
!IF_stage1_rg_stage_input_04_BITS_139_TO_135_07_ETC___d268;
3'b100:
IF_stage1_rg_stage_input_04_BITS_112_TO_110_33_ETC___d279 =
IF_stage1_rg_stage_input_04_BITS_139_TO_135_07_ETC___d270;
3'b101:
IF_stage1_rg_stage_input_04_BITS_112_TO_110_33_ETC___d279 =
!IF_stage1_rg_stage_input_04_BITS_139_TO_135_07_ETC___d270;
3'b110:
IF_stage1_rg_stage_input_04_BITS_112_TO_110_33_ETC___d279 =
IF_stage1_rg_stage_input_04_BITS_139_TO_135_07_ETC___d272;
default: IF_stage1_rg_stage_input_04_BITS_112_TO_110_33_ETC___d279 =
stage1_rg_stage_input[112:110] == 3'b111 &&
!IF_stage1_rg_stage_input_04_BITS_139_TO_135_07_ETC___d272;
endcase
end
always@(stage1_rg_stage_input)
begin
case (stage1_rg_stage_input[151:145])
7'b0000011:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q12 =
stage1_rg_stage_input[112:110] != 3'b0 &&
stage1_rg_stage_input[112:110] != 3'b100 &&
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b101 &&
stage1_rg_stage_input[112:110] != 3'b010 &&
stage1_rg_stage_input[112:110] != 3'b110 &&
stage1_rg_stage_input[112:110] != 3'b011;
7'b0100011:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q12 =
stage1_rg_stage_input[112:110] != 3'b0 &&
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b010 &&
stage1_rg_stage_input[112:110] != 3'b011;
default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q12 =
stage1_rg_stage_input[151:145] != 7'b0101111 ||
stage1_rg_stage_input[109:105] != 5'b00010 &&
stage1_rg_stage_input[109:105] != 5'b00011 &&
stage1_rg_stage_input[109:105] != 5'b0 &&
stage1_rg_stage_input[109:105] != 5'b00001 &&
stage1_rg_stage_input[109:105] != 5'b01100 &&
stage1_rg_stage_input[109:105] != 5'b01000 &&
stage1_rg_stage_input[109:105] != 5'b00100 &&
stage1_rg_stage_input[109:105] != 5'b10000 &&
stage1_rg_stage_input[109:105] != 5'b11000 &&
stage1_rg_stage_input[109:105] != 5'b10100 &&
stage1_rg_stage_input[109:105] != 5'b11100 ||
stage1_rg_stage_input[112:110] != 3'b010 &&
stage1_rg_stage_input[112:110] != 3'b011;
endcase
end
always@(stage1_rg_stage_input or
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q12 or
NOT_stage1_rg_stage_input_04_BITS_112_TO_110_3_ETC___d315)
begin
case (stage1_rg_stage_input[151:145])
7'b0010011, 7'b0110011:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q13 =
NOT_stage1_rg_stage_input_04_BITS_112_TO_110_3_ETC___d315;
7'b0011011:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q13 =
stage1_rg_stage_input[112:110] != 3'b0 &&
(stage1_rg_stage_input[112:110] != 3'b001 ||
stage1_rg_stage_input[257]) &&
(stage1_rg_stage_input[112:110] != 3'b101 ||
stage1_rg_stage_input[257]);
7'b0111011:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q13 =
stage1_rg_stage_input[97:88] != 10'b0 &&
stage1_rg_stage_input[97:88] != 10'b0100000000 &&
stage1_rg_stage_input[97:88] != 10'b0000000001 &&
stage1_rg_stage_input[97:88] != 10'b0000000101 &&
stage1_rg_stage_input[97:88] != 10'b0100000101;
default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q13 =
stage1_rg_stage_input[151:145] != 7'b0110111 &&
stage1_rg_stage_input[151:145] != 7'b0010111 &&
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q12;
endcase
end
always@(stage1_rg_stage_input)
begin
case (stage1_rg_stage_input[151:145])
7'b0000011:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q14 =
stage1_rg_stage_input[112:110] == 3'b0 ||
stage1_rg_stage_input[112:110] == 3'b100 ||
stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b101 ||
stage1_rg_stage_input[112:110] == 3'b010 ||
stage1_rg_stage_input[112:110] == 3'b110 ||
stage1_rg_stage_input[112:110] == 3'b011;
7'b0100011:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q14 =
stage1_rg_stage_input[112:110] == 3'b0 ||
stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b010 ||
stage1_rg_stage_input[112:110] == 3'b011;
default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q14 =
stage1_rg_stage_input[151:145] == 7'b0101111 &&
(stage1_rg_stage_input[109:105] == 5'b00010 ||
stage1_rg_stage_input[109:105] == 5'b00011 ||
stage1_rg_stage_input[109:105] == 5'b0 ||
stage1_rg_stage_input[109:105] == 5'b00001 ||
stage1_rg_stage_input[109:105] == 5'b01100 ||
stage1_rg_stage_input[109:105] == 5'b01000 ||
stage1_rg_stage_input[109:105] == 5'b00100 ||
stage1_rg_stage_input[109:105] == 5'b10000 ||
stage1_rg_stage_input[109:105] == 5'b11000 ||
stage1_rg_stage_input[109:105] == 5'b10100 ||
stage1_rg_stage_input[109:105] == 5'b11100) &&
(stage1_rg_stage_input[112:110] == 3'b010 ||
stage1_rg_stage_input[112:110] == 3'b011);
endcase
end
always@(stage1_rg_stage_input or
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q14 or
stage1_rg_stage_input_04_BITS_112_TO_110_33_EQ_ETC___d437)
begin
case (stage1_rg_stage_input[151:145])
7'b0010011, 7'b0110011:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q15 =
stage1_rg_stage_input_04_BITS_112_TO_110_33_EQ_ETC___d437;
7'b0011011:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q15 =
stage1_rg_stage_input[112:110] == 3'b0 ||
(stage1_rg_stage_input[112:110] == 3'b001 ||
stage1_rg_stage_input[112:110] == 3'b101) &&
!stage1_rg_stage_input[257];
7'b0111011:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q15 =
stage1_rg_stage_input[97:88] == 10'b0 ||
stage1_rg_stage_input[97:88] == 10'b0100000000 ||
stage1_rg_stage_input[97:88] == 10'b0000000001 ||
stage1_rg_stage_input[97:88] == 10'b0000000101 ||
stage1_rg_stage_input[97:88] == 10'b0100000101;
default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q15 =
stage1_rg_stage_input[151:145] == 7'b0110111 ||
stage1_rg_stage_input[151:145] == 7'b0010111 ||
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q14;
endcase
end
always@(stage1_rg_stage_input)
begin
case (stage1_rg_stage_input[112:110])
3'b0, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101, 3'b110:
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q16 = 4'd1;
3'd7: CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q16 = 4'd12;
endcase
end
always@(stage1_rg_stage_input)
begin
case (stage1_rg_stage_input[112:110])
3'b0: CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q17 = 4'd5;
3'b001: CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q17 = 4'd6;
default: CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q17 =
4'd12;
endcase
end
always@(stage1_rg_stage_input)
begin
case (stage1_rg_stage_input[112:110])
3'b0, 3'b001, 3'b010, 3'b011:
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q18 = 4'd1;
default: CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q18 =
4'd12;
endcase
end
always@(stage1_rg_stage_input or
IF_rg_cur_priv_1_EQ_0b11_06_AND_stage1_rg_stag_ETC___d520)
begin
case (stage1_rg_stage_input[87:76])
12'b0, 12'b000000000001:
CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_1_ETC__q19 = 4'd12;
default: CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_1_ETC__q19 =
IF_rg_cur_priv_1_EQ_0b11_06_AND_stage1_rg_stag_ETC___d520;
endcase
end
always@(stage1_rg_stage_input or
CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_1_ETC__q19)
begin
case (stage1_rg_stage_input[112:110])
3'b0:
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q20 =
(stage1_rg_stage_input[144:140] == 5'd0 &&
stage1_rg_stage_input[139:135] == 5'd0) ?
CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_1_ETC__q19 :
4'd12;
3'b001, 3'b101:
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q20 = 4'd3;
3'b010, 3'b011, 3'b110, 3'b111:
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q20 = 4'd4;
3'd4: CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q20 = 4'd12;
endcase
end
always@(stage1_rg_stage_input or
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q16 or
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q17 or
IF_NOT_stage1_rg_stage_input_04_BITS_112_TO_11_ETC___d490 or
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q18 or
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q20)
begin
case (stage1_rg_stage_input[151:145])
7'b0000011:
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d538 =
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q16;
7'b0001111:
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d538 =
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q17;
7'b0010011, 7'b0110011:
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d538 =
IF_NOT_stage1_rg_stage_input_04_BITS_112_TO_11_ETC___d490;
7'b0010111, 7'b0110111:
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d538 = 4'd1;
7'b0011011:
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d538 =
(stage1_rg_stage_input[112:110] != 3'b0 &&
(stage1_rg_stage_input[112:110] != 3'b001 ||
stage1_rg_stage_input[257]) &&
(stage1_rg_stage_input[112:110] != 3'b101 ||
stage1_rg_stage_input[257])) ?
4'd12 :
4'd1;
7'b0100011:
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d538 =
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q18;
7'b0101111:
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d538 =
((stage1_rg_stage_input[109:105] == 5'b00010 ||
stage1_rg_stage_input[109:105] == 5'b00011 ||
stage1_rg_stage_input[109:105] == 5'b0 ||
stage1_rg_stage_input[109:105] == 5'b00001 ||
stage1_rg_stage_input[109:105] == 5'b01100 ||
stage1_rg_stage_input[109:105] == 5'b01000 ||
stage1_rg_stage_input[109:105] == 5'b00100 ||
stage1_rg_stage_input[109:105] == 5'b10000 ||
stage1_rg_stage_input[109:105] == 5'b11000 ||
stage1_rg_stage_input[109:105] == 5'b10100 ||
stage1_rg_stage_input[109:105] == 5'b11100) &&
(stage1_rg_stage_input[112:110] == 3'b010 ||
stage1_rg_stage_input[112:110] == 3'b011)) ?
4'd1 :
4'd12;
7'b0111011:
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d538 =
(stage1_rg_stage_input[97:88] != 10'b0 &&
stage1_rg_stage_input[97:88] != 10'b0100000000 &&
stage1_rg_stage_input[97:88] != 10'b0000000001 &&
stage1_rg_stage_input[97:88] != 10'b0000000101 &&
stage1_rg_stage_input[97:88] != 10'b0100000101) ?
4'd12 :
4'd1;
7'b1110011:
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d538 =
CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q20;
default: IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d538 =
4'd12;
endcase
end
always@(stage1_rg_stage_input or
stage1_rg_stage_input_04_BITS_151_TO_145_31_EQ_ETC___d430 or
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d538 or
IF_stage1_rg_stage_input_04_BITS_112_TO_110_33_ETC___d279)
begin
case (stage1_rg_stage_input[151:145])
7'b1100011:
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d541 =
(stage1_rg_stage_input[112:110] != 3'b0 &&
stage1_rg_stage_input[112:110] != 3'b001 &&
stage1_rg_stage_input[112:110] != 3'b100 &&
stage1_rg_stage_input[112:110] != 3'b101 &&
stage1_rg_stage_input[112:110] != 3'b110 &&
stage1_rg_stage_input[112:110] != 3'b111) ?
4'd12 :
(IF_stage1_rg_stage_input_04_BITS_112_TO_110_33_ETC___d279 ?
4'd2 :
4'd1);
7'b1100111, 7'b1101111:
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d541 = 4'd2;
default: IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d541 =
stage1_rg_stage_input_04_BITS_151_TO_145_31_EQ_ETC___d430 ?
4'd1 :
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d538;
endcase
end
always@(stage1_rg_stage_input)
begin
case (stage1_rg_stage_input[151:145])
7'b1100011:
IF_NOT_stage1_rg_full_03_87_OR_NOT_stage1_rg_s_ETC___d626 = 2'd0;
7'b1100111:
IF_NOT_stage1_rg_full_03_87_OR_NOT_stage1_rg_s_ETC___d626 = 2'd2;
7'b1101111:
IF_NOT_stage1_rg_full_03_87_OR_NOT_stage1_rg_s_ETC___d626 = 2'd1;
default: IF_NOT_stage1_rg_full_03_87_OR_NOT_stage1_rg_s_ETC___d626 =
2'd3;
endcase
end
always@(stage1_rg_stage_input or
_theResult_____1_fst__h8814 or
rd_val___1__h8782 or
rd_val___1__h8789 or rd_val___1__h8796 or rd_val___1__h8803)
begin
case (stage1_rg_stage_input[112:110])
3'b010: _theResult_____1_fst__h8786 = rd_val___1__h8782;
3'b011: _theResult_____1_fst__h8786 = rd_val___1__h8789;
3'b100: _theResult_____1_fst__h8786 = rd_val___1__h8796;
3'b110: _theResult_____1_fst__h8786 = rd_val___1__h8803;
default: _theResult_____1_fst__h8786 = _theResult_____1_fst__h8814;
endcase
end
always@(stage1_rg_stage_input or
rs1_val_bypassed__h4837 or
IF_stage1_rg_stage_input_04_BITS_139_TO_135_07_ETC___d655 or
alu_outputs___1_addr__h8135 or
alu_outputs___1_addr__h7863 or next_pc__h7896 or next_pc__h7869)
begin
case (stage1_rg_stage_input[151:145])
7'b0000011:
x_out_data_to_stage2_addr__h7708 =
IF_stage1_rg_stage_input_04_BITS_139_TO_135_07_ETC___d655;
7'b0100011:
x_out_data_to_stage2_addr__h7708 = alu_outputs___1_addr__h8135;
7'b1100011:
x_out_data_to_stage2_addr__h7708 = alu_outputs___1_addr__h7863;
7'b1100111: x_out_data_to_stage2_addr__h7708 = next_pc__h7896;
7'b1101111: x_out_data_to_stage2_addr__h7708 = next_pc__h7869;
default: x_out_data_to_stage2_addr__h7708 = rs1_val_bypassed__h4837;
endcase
end
always@(stage1_rg_stage_input or
next_pc__h7896 or branch_target__h7840 or next_pc__h7869)
begin
case (stage1_rg_stage_input[151:145])
7'b1100011: x_out_cf_info_taken_PC__h9708 = branch_target__h7840;
7'b1101111: x_out_cf_info_taken_PC__h9708 = next_pc__h7869;
default: x_out_cf_info_taken_PC__h9708 = next_pc__h7896;
endcase
end
always@(stage1_rg_stage_input or data_to_stage2_addr__h7698)
begin
case (stage1_rg_stage_input[151:145])
7'b1100111, 7'b1101111:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q23 =
data_to_stage2_addr__h7698;
default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q23 =
(stage1_rg_stage_input[151:145] == 7'b1110011 &&
stage1_rg_stage_input[112:110] == 3'b0 &&
stage1_rg_stage_input[144:140] == 5'd0 &&
stage1_rg_stage_input[139:135] == 5'd0 &&
stage1_rg_stage_input[87:76] == 12'b000000000001) ?
stage1_rg_stage_input[401:338] :
64'd0;
endcase
end
always@(stage1_rg_stage_input)
begin
case (stage1_rg_stage_input[151:145])
7'b0000011:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q24 = 3'd1;
7'b0010011, 7'b0010111, 7'b0011011, 7'b0110011, 7'b0110111, 7'b0111011:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q24 = 3'd0;
7'b0100011:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q24 = 3'd2;
default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q24 = 3'd4;
endcase
end
always@(stage1_rg_stage_input or
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q24)
begin
case (stage1_rg_stage_input[151:145])
7'b1100011, 7'b1100111, 7'b1101111:
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q25 = 3'd0;
default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q25 =
((stage1_rg_stage_input[151:145] == 7'b0110011 ||
stage1_rg_stage_input[151:145] == 7'b0111011) &&
stage1_rg_stage_input[104:98] == 7'b0000001) ?
3'd3 :
CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q24;
endcase
end
always@(stage1_rg_stage_input or
alu_outputs___1_val1__h8344 or
alu_outputs___1_val1__h8026 or
rd_val__h8089 or
alu_outputs___1_val1__h8047 or
rd_val__h8075 or
alu_outputs___1_val1__h8068 or alu_outputs___1_val1__h8324)
begin
case (stage1_rg_stage_input[151:145])
7'b0010011, 7'b0110011:
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d824 =
alu_outputs___1_val1__h8026;
7'b0010111:
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d824 =
rd_val__h8089;
7'b0011011:
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d824 =
alu_outputs___1_val1__h8047;
7'b0110111:
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d824 =
rd_val__h8075;
7'b0111011:
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d824 =
alu_outputs___1_val1__h8068;
7'b1110011:
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d824 =
alu_outputs___1_val1__h8324;
default: IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d824 =
alu_outputs___1_val1__h8344;
endcase
end
always@(stage1_rg_stage_input or
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d826 or
x_out_cf_info_fallthru_PC__h9707)
begin
case (stage1_rg_stage_input[151:145])
7'b1100111, 7'b1101111:
x_out_data_to_stage2_val1__h7709 = x_out_cf_info_fallthru_PC__h9707;
default: x_out_data_to_stage2_val1__h7709 =
IF_stage1_rg_stage_input_04_BITS_151_TO_145_31_ETC___d826;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
cfg_logdelay <= `BSV_ASSIGNMENT_DELAY 64'd0;
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
imem_rg_cache_addr <= `BSV_ASSIGNMENT_DELAY 64'hFFFFFFFFFFFFFFFF;
rg_cur_priv <= `BSV_ASSIGNMENT_DELAY 2'b11;
rg_run_on_reset <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_state <= `BSV_ASSIGNMENT_DELAY 4'd0;
stage1_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
stage2_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
stage2_rg_resetting <= `BSV_ASSIGNMENT_DELAY 1'd0;
stage3_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
stageD_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
stageF_rg_epoch <= `BSV_ASSIGNMENT_DELAY 2'd0;
stageF_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (cfg_logdelay$EN)
cfg_logdelay <= `BSV_ASSIGNMENT_DELAY cfg_logdelay$D_IN;
if (cfg_verbosity$EN)
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN;
if (imem_rg_cache_addr$EN)
imem_rg_cache_addr <= `BSV_ASSIGNMENT_DELAY imem_rg_cache_addr$D_IN;
if (rg_cur_priv$EN)
rg_cur_priv <= `BSV_ASSIGNMENT_DELAY rg_cur_priv$D_IN;
if (rg_run_on_reset$EN)
rg_run_on_reset <= `BSV_ASSIGNMENT_DELAY rg_run_on_reset$D_IN;
if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
if (stage1_rg_full$EN)
stage1_rg_full <= `BSV_ASSIGNMENT_DELAY stage1_rg_full$D_IN;
if (stage2_rg_full$EN)
stage2_rg_full <= `BSV_ASSIGNMENT_DELAY stage2_rg_full$D_IN;
if (stage2_rg_resetting$EN)
stage2_rg_resetting <= `BSV_ASSIGNMENT_DELAY
stage2_rg_resetting$D_IN;
if (stage3_rg_full$EN)
stage3_rg_full <= `BSV_ASSIGNMENT_DELAY stage3_rg_full$D_IN;
if (stageD_rg_full$EN)
stageD_rg_full <= `BSV_ASSIGNMENT_DELAY stageD_rg_full$D_IN;
if (stageF_rg_epoch$EN)
stageF_rg_epoch <= `BSV_ASSIGNMENT_DELAY stageF_rg_epoch$D_IN;
if (stageF_rg_full$EN)
stageF_rg_full <= `BSV_ASSIGNMENT_DELAY stageF_rg_full$D_IN;
end
if (imem_rg_cache_b16$EN)
imem_rg_cache_b16 <= `BSV_ASSIGNMENT_DELAY imem_rg_cache_b16$D_IN;
if (imem_rg_f3$EN) imem_rg_f3 <= `BSV_ASSIGNMENT_DELAY imem_rg_f3$D_IN;
if (imem_rg_mstatus_MXR$EN)
imem_rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY imem_rg_mstatus_MXR$D_IN;
if (imem_rg_pc$EN) imem_rg_pc <= `BSV_ASSIGNMENT_DELAY imem_rg_pc$D_IN;
if (imem_rg_priv$EN)
imem_rg_priv <= `BSV_ASSIGNMENT_DELAY imem_rg_priv$D_IN;
if (imem_rg_satp$EN)
imem_rg_satp <= `BSV_ASSIGNMENT_DELAY imem_rg_satp$D_IN;
if (imem_rg_sstatus_SUM$EN)
imem_rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY imem_rg_sstatus_SUM$D_IN;
if (imem_rg_tval$EN)
imem_rg_tval <= `BSV_ASSIGNMENT_DELAY imem_rg_tval$D_IN;
if (rg_csr_pc$EN) rg_csr_pc <= `BSV_ASSIGNMENT_DELAY rg_csr_pc$D_IN;
if (rg_csr_val1$EN) rg_csr_val1 <= `BSV_ASSIGNMENT_DELAY rg_csr_val1$D_IN;
if (rg_epoch$EN) rg_epoch <= `BSV_ASSIGNMENT_DELAY rg_epoch$D_IN;
if (rg_mstatus_MXR$EN)
rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY rg_mstatus_MXR$D_IN;
if (rg_next_pc$EN) rg_next_pc <= `BSV_ASSIGNMENT_DELAY rg_next_pc$D_IN;
if (rg_sstatus_SUM$EN)
rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY rg_sstatus_SUM$D_IN;
if (rg_start_CPI_cycles$EN)
rg_start_CPI_cycles <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_cycles$D_IN;
if (rg_start_CPI_instrs$EN)
rg_start_CPI_instrs <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_instrs$D_IN;
if (rg_trap_info$EN)
rg_trap_info <= `BSV_ASSIGNMENT_DELAY rg_trap_info$D_IN;
if (rg_trap_instr$EN)
rg_trap_instr <= `BSV_ASSIGNMENT_DELAY rg_trap_instr$D_IN;
if (rg_trap_interrupt$EN)
rg_trap_interrupt <= `BSV_ASSIGNMENT_DELAY rg_trap_interrupt$D_IN;
if (stage1_rg_stage_input$EN)
stage1_rg_stage_input <= `BSV_ASSIGNMENT_DELAY
stage1_rg_stage_input$D_IN;
if (stage2_rg_stage2$EN)
stage2_rg_stage2 <= `BSV_ASSIGNMENT_DELAY stage2_rg_stage2$D_IN;
if (stage3_rg_stage3$EN)
stage3_rg_stage3 <= `BSV_ASSIGNMENT_DELAY stage3_rg_stage3$D_IN;
if (stageD_rg_data$EN)
stageD_rg_data <= `BSV_ASSIGNMENT_DELAY stageD_rg_data$D_IN;
if (stageF_rg_priv$EN)
stageF_rg_priv <= `BSV_ASSIGNMENT_DELAY stageF_rg_priv$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
cfg_logdelay = 64'hAAAAAAAAAAAAAAAA;
cfg_verbosity = 4'hA;
imem_rg_cache_addr = 64'hAAAAAAAAAAAAAAAA;
imem_rg_cache_b16 = 16'hAAAA;
imem_rg_f3 = 3'h2;
imem_rg_mstatus_MXR = 1'h0;
imem_rg_pc = 64'hAAAAAAAAAAAAAAAA;
imem_rg_priv = 2'h2;
imem_rg_satp = 64'hAAAAAAAAAAAAAAAA;
imem_rg_sstatus_SUM = 1'h0;
imem_rg_tval = 64'hAAAAAAAAAAAAAAAA;
rg_csr_pc = 64'hAAAAAAAAAAAAAAAA;
rg_csr_val1 = 64'hAAAAAAAAAAAAAAAA;
rg_cur_priv = 2'h2;
rg_epoch = 2'h2;
rg_mstatus_MXR = 1'h0;
rg_next_pc = 64'hAAAAAAAAAAAAAAAA;
rg_run_on_reset = 1'h0;
rg_sstatus_SUM = 1'h0;
rg_start_CPI_cycles = 64'hAAAAAAAAAAAAAAAA;
rg_start_CPI_instrs = 64'hAAAAAAAAAAAAAAAA;
rg_state = 4'hA;
rg_trap_info = 132'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
rg_trap_instr = 32'hAAAAAAAA;
rg_trap_interrupt = 1'h0;
stage1_rg_full = 1'h0;
stage1_rg_stage_input =
402'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
stage2_rg_full = 1'h0;
stage2_rg_resetting = 1'h0;
stage2_rg_stage2 =
298'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
stage3_rg_full = 1'h0;
stage3_rg_stage3 = 168'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
stageD_rg_data =
234'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
stageD_rg_full = 1'h0;
stageF_rg_epoch = 2'h2;
stageF_rg_full = 1'h0;
stageF_rg_priv = 2'h2;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$display("================================================================");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$display("%0d: Pipeline State: minstret:%0d cur_priv:%0d mstatus:%0x epoch:%0d",
csr_regfile$read_csr_mcycle,
csr_regfile$read_csr_minstret,
rg_cur_priv,
csr_regfile$read_mstatus,
rg_epoch);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write("MStatus{",
"sd:%0d",
csr_regfile$read_mstatus[14:13] == 2'h3 ||
csr_regfile$read_mstatus[16:15] == 2'h3);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && csr_regfile$read_misa[27:26] == 2'd2)
$write(" sxl:%0d uxl:%0d", sxl__h6149, uxl__h6150);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && csr_regfile$read_misa[27:26] != 2'd2)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" tsr:%0d", csr_regfile$read_mstatus[22]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" tw:%0d", csr_regfile$read_mstatus[21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" tvm:%0d", csr_regfile$read_mstatus[20]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" mxr:%0d", csr_regfile$read_mstatus[19]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" sum:%0d", csr_regfile$read_mstatus[18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" mprv:%0d", csr_regfile$read_mstatus[17]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" xs:%0d", csr_regfile$read_mstatus[16:15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" fs:%0d", csr_regfile$read_mstatus[14:13]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" mpp:%0d", csr_regfile$read_mstatus[12:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" spp:%0d", csr_regfile$read_mstatus[8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" pies:%0d_%0d%0d",
csr_regfile$read_mstatus[7],
csr_regfile$read_mstatus[5],
csr_regfile$read_mstatus[4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$write(" ies:%0d_%0d%0d",
csr_regfile$read_mstatus[3],
csr_regfile$read_mstatus[1],
csr_regfile$read_mstatus[0]);
if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" Stage3: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("Output_Stage3");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_full) $write(" PIPE");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage3_rg_full) $write(" EMPTY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" Bypass to Stage1: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("Bypass {");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
(!stage3_rg_full || !stage3_rg_stage3[69]))
$write("Rd -");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_full && stage3_rg_stage3[69])
$write("Rd %0d ",
stage3_rg_stage3[68:64],
"rd_val:%h",
stage3_rg_stage3[63:0]);
if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$display(" Stage2: pc 0x%08h instr 0x%08h priv %0d",
stage2_rg_stage2[295:232],
stage2_rg_stage2[231:200],
stage2_rg_stage2[297:296]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd0)
$write("Output_Stage2", " EMPTY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd1)
$write("Output_Stage2", " BUSY: pc:%0h", stage2_rg_stage2[295:232]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd3)
$write("Output_Stage2", " NONPIPE: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd0 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd1 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd3)
$write("Output_Stage2", " PIPE: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd1)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd3)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd0 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd1 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd3)
$write("data_to_Stage3 {pc:%h instr:%h priv:%0d\n",
stage2_rg_stage2[295:232],
stage2_rg_stage2[231:200],
stage2_rg_stage2[297:296]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd1)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd3)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd0 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd1 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd3)
$write(" rd_valid:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd1)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd3)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd0 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd1 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd3 &&
stage2_rg_stage2[199:197] != 3'd0 &&
IF_stage2_rg_stage2_01_BITS_199_TO_197_02_EQ_1_ETC___d145)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd0 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd1 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd3 &&
(stage2_rg_stage2[199:197] == 3'd0 ||
IF_stage2_rg_stage2_01_BITS_199_TO_197_02_EQ_1_ETC___d154))
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd1)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd3)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd0 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd1 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd3)
$write(" grd:%0d rd_val:%h\n",
x_out_data_to_stage3_rd__h7080,
x_out_data_to_stage3_rd_val__h7081);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd1)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd3)
$write("Trap_Info { ", "epc: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd0 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd1 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd3)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd1)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd3)
$write("'h%h", stage2_rg_stage2[295:232]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd0 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd1 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd3)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd1)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd3)
$write(", ", "exc_code: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd0 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd1 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd3)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd1)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd3)
$write("'h%h", near_mem$dmem_exc_code);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd0 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd1 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd3)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd1)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd3)
$write(", ", "tval: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd0 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd1 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd3)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd1)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd3)
$write("'h%h", stage2_rg_stage2[191:128], " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd0 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd1 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd3)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd1)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd3)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd0 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd1 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd3)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd1)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd3)
$write("Trap_Info { ", "epc: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd0 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd1 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd3)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd1)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd3)
$write("'h%h", stage2_rg_stage2[295:232]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd0 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd1 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd3)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd1)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd3)
$write(", ", "exc_code: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd0 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd1 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd3)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd1)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd3)
$write("'h%h", near_mem$dmem_exc_code);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd0 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd1 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd3)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd1)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd3)
$write(", ", "tval: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd0 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd1 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd3)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd1)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd3)
$write("'h%h", stage2_rg_stage2[191:128], " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd0 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd1 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 != 2'd3)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" Bypass to Stage1: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("Bypass {");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d191 == 2'd0)
$write("Rd -");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d191 != 2'd0)
$write("Rd %0d ", x_out_bypass_rd__h7419);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d191 == 2'd0)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d191 == 2'd1)
$write("-");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d191 != 2'd0 &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d191 != 2'd1)
$write("rd_val:%h", x_out_bypass_rd_val__h7420);
if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$display(" Stage1: pc 0x%08h instr 0x%08h priv %0d",
stage1_rg_stage_input[401:338],
stage1_rg_stage_input[263:232],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d224)
$write("Output_Stage1",
" BUSY pc:%h",
stage1_rg_stage_input[401:338]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413)
$write("Output_Stage1",
" NONPIPE: pc:%h",
stage1_rg_stage_input[401:338]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_03_AND_NOT_stage1_rg_stage_inpu_ETC___d486)
$write("Output_Stage1");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full)
$write("Output_Stage1", " EMPTY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d224)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_03_AND_NOT_stage1_rg_stage_inpu_ETC___d486)
$write(" PIPE: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d224)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d417 &&
(!stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d483) &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 == 4'd0)
$write("CONTROL_DISCARD");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d417 &&
(!stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d483) &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 == 4'd1)
$write("CONTROL_STRAIGHT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d417 &&
(!stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d483) &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 == 4'd2)
$write("CONTROL_BRANCH");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d417 &&
(!stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d483) &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 == 4'd3)
$write("CONTROL_CSRR_W");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d417 &&
(!stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d483) &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 == 4'd4)
$write("CONTROL_CSRR_S_or_C");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d417 &&
(!stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d483) &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 == 4'd5)
$write("CONTROL_FENCE");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d417 &&
(!stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d483) &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 == 4'd6)
$write("CONTROL_FENCE_I");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d417 &&
(!stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d483) &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 == 4'd7)
$write("CONTROL_SFENCE_VMA");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d417 &&
(!stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d483) &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 == 4'd8)
$write("CONTROL_MRET");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d417 &&
(!stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d483) &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 == 4'd9)
$write("CONTROL_SRET");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d417 &&
(!stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d483) &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 == 4'd10)
$write("CONTROL_URET");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d417 &&
(!stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d483) &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 == 4'd11)
$write("CONTROL_WFI");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d417 &&
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d617)
$write("CONTROL_TRAP");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d224)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_03_AND_NOT_stage1_rg_stage_inpu_ETC___d486)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d224)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d629)
$write("{", "CF_None");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d633)
$write("{", "BR ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d639)
$write("{");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d224)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d629)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d633)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d417 &&
(!stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d483) &&
IF_NOT_stage1_rg_full_03_87_OR_NOT_stage1_rg_s_ETC___d626 == 2'd1)
$write("JAL [%h->%h/%h]",
stage1_rg_stage_input[401:338],
x_out_cf_info_taken_PC__h9708,
x_out_cf_info_fallthru_PC__h9707);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d417 &&
(!stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d483) &&
IF_NOT_stage1_rg_full_03_87_OR_NOT_stage1_rg_s_ETC___d626 == 2'd2)
$write("JALR [%h->%h/%h]",
stage1_rg_stage_input[401:338],
x_out_cf_info_taken_PC__h9708,
x_out_cf_info_fallthru_PC__h9707);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d224)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d629)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d633)
if (stage1_rg_stage_input[151:145] != 7'b1100011 ||
IF_stage1_rg_stage_input_04_BITS_112_TO_110_33_ETC___d279)
$write("taken ");
else
$write("fallthru ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d639)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d224)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d629)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d633)
$write("[%h->%h %h]",
stage1_rg_stage_input[401:338],
x_out_cf_info_fallthru_PC__h9707,
x_out_cf_info_taken_PC__h9708);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d639)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d224)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_03_AND_NOT_stage1_rg_stage_inpu_ETC___d486)
$write("}");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d224)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_03_AND_NOT_stage1_rg_stage_inpu_ETC___d486)
$write("data_to_Stage 2 {pc:%h instr:%h priv:%0d\n",
stage1_rg_stage_input[401:338],
stage1_rg_stage_input[263:232],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d224)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_03_AND_NOT_stage1_rg_stage_inpu_ETC___d486)
$write(" op_stage2:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d224)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d417 &&
(!stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d483) &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d690 == 3'd0)
$write("OP_Stage2_ALU");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d417 &&
(!stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d483) &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d690 == 3'd1)
$write("OP_Stage2_LD");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d417 &&
(!stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d483) &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d690 == 3'd2)
$write("OP_Stage2_ST");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d417 &&
(!stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d483) &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d690 == 3'd3)
$write("OP_Stage2_M");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d417 &&
(!stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ||
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d483) &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d690 != 3'd0 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d690 != 3'd1 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d690 != 3'd2 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d690 != 3'd3)
$write("OP_Stage2_AMO");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d224)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_03_AND_NOT_stage1_rg_stage_inpu_ETC___d486)
$write(" rd:%0d\n", x_out_data_to_stage2_rd__h7707);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d224)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_03_AND_NOT_stage1_rg_stage_inpu_ETC___d486)
$write(" addr:%h val1:%h val2:%h}",
x_out_data_to_stage2_addr__h7708,
x_out_data_to_stage2_val1__h7709,
x_out_data_to_stage2_val2__h7710);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d224)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_03_AND_NOT_stage1_rg_stage_inpu_ETC___d486)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d224)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 == 4'd0)
$write("CONTROL_DISCARD");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 == 4'd1)
$write("CONTROL_STRAIGHT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 == 4'd2)
$write("CONTROL_BRANCH");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 == 4'd3)
$write("CONTROL_CSRR_W");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 == 4'd4)
$write("CONTROL_CSRR_S_or_C");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 == 4'd5)
$write("CONTROL_FENCE");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 == 4'd6)
$write("CONTROL_FENCE_I");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 == 4'd7)
$write("CONTROL_SFENCE_VMA");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 == 4'd8)
$write("CONTROL_MRET");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 == 4'd9)
$write("CONTROL_SRET");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 == 4'd10)
$write("CONTROL_URET");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 == 4'd11)
$write("CONTROL_WFI");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d861)
$write("CONTROL_TRAP");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_03_AND_NOT_stage1_rg_stage_inpu_ETC___d486)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d224)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_03_AND_NOT_stage1_rg_stage_inpu_ETC___d486)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d224)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413)
$write("Trap_Info { ", "epc: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_03_AND_NOT_stage1_rg_stage_inpu_ETC___d486)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d224)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413)
$write("'h%h", stage1_rg_stage_input[401:338]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_03_AND_NOT_stage1_rg_stage_inpu_ETC___d486)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d224)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413)
$write(", ", "exc_code: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_03_AND_NOT_stage1_rg_stage_inpu_ETC___d486)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d224)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413)
$write("'h%h", x_out_trap_info_exc_code__h9532);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_03_AND_NOT_stage1_rg_stage_inpu_ETC___d486)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d224)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413)
$write(", ", "tval: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_03_AND_NOT_stage1_rg_stage_inpu_ETC___d486)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d224)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 &&
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d413)
$write("'h%h", value__h9576, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stage1_rg_full_03_AND_NOT_stage1_rg_stage_inpu_ETC___d486)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d224)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d417 &&
!IF_IF_stage1_rg_stage_input_04_BITS_151_TO_145_ETC___d911)
$write("\n redirect next_pc:%h", x_out_next_pc__h7665);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
NOT_stage1_rg_stage_input_04_BITS_335_TO_334_0_ETC___d417 &&
IF_IF_stage1_rg_stage_input_04_BITS_151_TO_145_ETC___d911)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$display(" StageD: pc 0x%08h instr 0x%08h priv %0d epoch %0d",
stageD_rg_data[233:170],
x_out_data_to_stage1_instr__h10611,
stageD_rg_data[167:166],
stageD_rg_data[169:168]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("Output_StageD");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full) $write(" PIPE: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write(" EMPTY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && stageD_rg_data[164])
$write("data_to_Stage1 {pc:%0h priv:%0d epoch:%0d",
stageD_rg_data[233:170],
stageD_rg_data[167:166],
stageD_rg_data[169:168]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && !stageD_rg_data[164])
$write("data_to_Stage1 {pc:%0h priv:%0d epoch:%0d",
stageD_rg_data[233:170],
stageD_rg_data[167:166],
stageD_rg_data[169:168]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && stageD_rg_data[164])
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
!stageD_rg_data[164] &&
stageD_rg_data[165])
$write(" instr_C:%0h", stageD_rg_data[79:64]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
!stageD_rg_data[164] &&
!stageD_rg_data[165])
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && stageD_rg_data[164])
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && !stageD_rg_data[164])
$write(" instr:%0h pred_pc:%0h",
x_out_data_to_stage1_instr__h10611,
stageD_rg_data[63:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && stageD_rg_data[164])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && !stageD_rg_data[164])
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd0)
$write("INSTRUCTION_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd1)
$write("INSTRUCTION_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd2)
$write("ILLEGAL_INSTRUCTION");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd3)
$write("BREAKPOINT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd4)
$write("LOAD_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd5)
$write("LOAD_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd6)
$write("STORE_AMO_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd7)
$write("STORE_AMO_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd8)
$write("ECALL_FROM_U");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd9)
$write("ECALL_FROM_S");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd11)
$write("ECALL_FROM_M");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd12)
$write("INSTRUCTION_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd13)
$write("LOAD_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] == 4'd15)
$write("STORE_AMO_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
stageD_rg_data[164] &&
stageD_rg_data[163:160] != 4'd0 &&
stageD_rg_data[163:160] != 4'd1 &&
stageD_rg_data[163:160] != 4'd2 &&
stageD_rg_data[163:160] != 4'd3 &&
stageD_rg_data[163:160] != 4'd4 &&
stageD_rg_data[163:160] != 4'd5 &&
stageD_rg_data[163:160] != 4'd6 &&
stageD_rg_data[163:160] != 4'd7 &&
stageD_rg_data[163:160] != 4'd8 &&
stageD_rg_data[163:160] != 4'd9 &&
stageD_rg_data[163:160] != 4'd11 &&
stageD_rg_data[163:160] != 4'd12 &&
stageD_rg_data[163:160] != 4'd13 &&
stageD_rg_data[163:160] != 4'd15)
$write("unknown trap Exc_Code %d", stageD_rg_data[163:160]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && !stageD_rg_data[164])
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && stageD_rg_data[164])
$write(" tval %0h", stageD_rg_data[159:96]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && !stageD_rg_data[164])
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full) $write("}");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe)
$display(" StageF: pc 0x%08h instr 0x%08h priv %0d epoch %0d",
imem_rg_pc,
d_instr__h16678,
stageF_rg_priv,
stageF_rg_epoch);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("Output_StageF");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
(!near_mem$imem_valid ||
imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1341))
$write(" BUSY: pc:%h", imem_rg_pc);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1347)
$write(" PIPE: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageF_rg_full) $write(" EMPTY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
(!near_mem$imem_valid ||
imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1341))
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1347)
$write("data_to_StageD {pc:%h priv:%0d epoch:%0d",
imem_rg_pc,
stageF_rg_priv,
stageF_rg_epoch);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageF_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
(!near_mem$imem_valid ||
imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1341))
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1347 &&
near_mem$imem_exc)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1356)
$write(" instr:%h pred_pc:%h",
d_instr__h16678,
stageF_branch_predictor$predict_rsp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageF_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
(!near_mem$imem_valid ||
imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1341))
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1362)
$write("INSTRUCTION_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1366)
$write("INSTRUCTION_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1370)
$write("ILLEGAL_INSTRUCTION");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1374)
$write("BREAKPOINT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1378)
$write("LOAD_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1382)
$write("LOAD_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1386)
$write("STORE_AMO_ADDR_MISALIGNED");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1390)
$write("STORE_AMO_ACCESS_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1394)
$write("ECALL_FROM_U");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1398)
$write("ECALL_FROM_S");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1402)
$write("ECALL_FROM_M");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1406)
$write("INSTRUCTION_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1410)
$write("LOAD_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1414)
$write("STORE_AMO_PAGE_FAULT");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d1443)
$write("unknown trap Exc_Code %d", near_mem$imem_exc_code);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe &&
stageF_rg_full_324_AND_near_mem_imem_valid_AND_ETC___d1356)
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageF_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
(!near_mem$imem_valid ||
imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1341))
$write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
near_mem$imem_valid &&
NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1347)
$write("}");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe && !stageF_rg_full) $write("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_show_pipe) $display("----------------");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage2_nonpipe &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display("%0d: %m.rl_stage2_nonpipe", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_trap &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display("%0d: %m.rl_stage1_trap", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap &&
rg_trap_info_760_BITS_131_TO_68_761_EQ_csr_reg_ETC___d1770)
$display("%0d: %m.rl_stage1_trap: Tight infinite trap loop: pc 0x%0x instr 0x%08x",
csr_regfile$read_csr_mcycle,
csr_regfile$csr_trap_actions[193:130],
rg_trap_instr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap &&
rg_trap_info_760_BITS_131_TO_68_761_EQ_csr_reg_ETC___d1770)
$display("CPI: %0d.%0d = (%0d/%0d) since last 'continue'",
cpi__h22750,
cpifrac__h22751,
delta_CPI_cycles__h22746,
_theResult____h22748);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap &&
rg_trap_info_760_BITS_131_TO_68_761_EQ_csr_reg_ETC___d1770)
$finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap && cur_verbosity__h3317 == 4'd1)
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
rg_trap_info[131:68],
rg_trap_instr,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap && cur_verbosity__h3317 != 4'd0)
$display(" mcause:0x%0h epc 0x%0h tval:0x%0h next_pc 0x%0h, new_priv %0d new_mstatus 0x%0h",
csr_regfile$csr_trap_actions[65:2],
rg_trap_info[131:68],
rg_trap_info[63:0],
csr_regfile$csr_trap_actions[193:130],
csr_regfile$csr_trap_actions[1:0],
csr_regfile$csr_trap_actions[129:66]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_W &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display("%0d: %m.rl_stage1_CSRR_W", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display("%0d: %m.rl_stage1_CSRR_W_2", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_W_2 && csr_regfile$access_permitted_1 &&
cur_verbosity__h3317 == 4'd1)
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
rg_csr_pc,
rg_trap_instr,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_W_2 && csr_regfile$access_permitted_1 &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display(" S1: write CSRRW/CSRRWI Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d",
rg_trap_instr[19:15],
rs1_val__h23220,
rg_trap_instr[31:20],
csr_regfile$read_csr[63:0],
rg_trap_instr[11:7]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
!csr_regfile$access_permitted_1 &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display(" Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d",
rg_trap_instr[19:15],
rs1_val__h23220,
rg_trap_instr[31:20],
rg_trap_instr[11:7]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display("%0d: %m.rl_stage1_CSRR_S_or_C",
csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display("%0d: %m.rl_stage1_CSRR_S_or_C_2",
csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
csr_regfile$access_permitted_2 &&
cur_verbosity__h3317 == 4'd1)
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
rg_csr_pc,
rg_trap_instr,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
csr_regfile$access_permitted_2 &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display(" S1: write CSRR_S_or_C: Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d",
rg_trap_instr[19:15],
rs1_val__h23899,
rg_trap_instr[31:20],
csr_regfile$read_csr[63:0],
rg_trap_instr[11:7]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
!csr_regfile$access_permitted_2 &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display(" Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d",
rg_trap_instr[19:15],
rs1_val__h23899,
rg_trap_instr[31:20],
rg_trap_instr[11:7]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display("%0d: %m.rl_stage1_restart_after_csrrx",
csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$write(" %m.enq: pc:0x%0h epoch:%0d priv:%0d",
rg_next_pc,
new_epoch__h18044,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
1'd0,
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display(" fa_stageF_redirect: minstret:%0d new_pc:%0x cur_priv:%0d, epoch %0d->%0d",
csr_regfile$read_csr_mcycle,
csr_regfile$read_csr_minstret,
rg_next_pc,
rg_cur_priv,
rg_epoch,
new_epoch__h18044);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_xRET &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display("%0d: %m.rl_stage1_xRET", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h3317 == 4'd1)
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
stage1_rg_stage_input[401:338],
stage1_rg_stage_input[263:232],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h3317 != 4'd0)
$display(" xRET: next_pc:0x%0h new mstatus:0x%0h new priv:%0d",
csr_regfile$csr_ret_actions[129:66],
csr_regfile$csr_ret_actions[63:0],
csr_regfile$csr_ret_actions[65:64]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_FENCE_I &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display("%0d: %m.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_FENCE_I && cur_verbosity__h3317 == 4'd1)
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
stage1_rg_stage_input[401:338],
stage1_rg_stage_input[263:232],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_FENCE_I &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display("%0d: %m.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE_I &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display("%0d: %m.rl_finish_FENCE_I", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE_I &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$write(" %m.enq: pc:0x%0h epoch:%0d priv:%0d",
rg_next_pc,
new_epoch__h18044,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE_I &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
1'd0,
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE_I &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE_I &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display(" fa_stageF_redirect: minstret:%0d new_pc:%0x cur_priv:%0d, epoch %0d->%0d",
csr_regfile$read_csr_mcycle,
csr_regfile$read_csr_minstret,
rg_next_pc,
rg_cur_priv,
rg_epoch,
new_epoch__h18044);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE_I &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display(" CPU.rl_finish_FENCE_I");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_FENCE &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display("%0d: %m.rl_stage1_FENCE", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_FENCE && cur_verbosity__h3317 == 4'd1)
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
stage1_rg_stage_input[401:338],
stage1_rg_stage_input[263:232],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_FENCE &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display("%0d: %m.rl_stage1_FENCE", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display("%0d: %m.rl_finish_FENCE", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$write(" %m.enq: pc:0x%0h epoch:%0d priv:%0d",
rg_next_pc,
new_epoch__h18044,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
1'd0,
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display(" fa_stageF_redirect: minstret:%0d new_pc:%0x cur_priv:%0d, epoch %0d->%0d",
csr_regfile$read_csr_mcycle,
csr_regfile$read_csr_minstret,
rg_next_pc,
rg_cur_priv,
rg_epoch,
new_epoch__h18044);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_FENCE &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display(" CPU.rl_finish_FENCE");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display("%0d: %m.rl_stage1_SFENCE_VMA", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA && cur_verbosity__h3317 == 4'd1)
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
stage1_rg_stage_input[401:338],
stage1_rg_stage_input[263:232],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display("%0d: %m.rl_stage1_SFENCE_VMA", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display("%0d: %m.rl_finish_SFENCE_VMA", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$write(" %m.enq: pc:0x%0h epoch:%0d priv:%0d",
rg_next_pc,
new_epoch__h18044,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
1'd0,
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display(" fa_stageF_redirect: minstret:%0d new_pc:%0x cur_priv:%0d, epoch %0d->%0d",
csr_regfile$read_csr_mcycle,
csr_regfile$read_csr_minstret,
rg_next_pc,
rg_cur_priv,
rg_epoch,
new_epoch__h18044);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display(" CPU.rl_finish_SFENCE_VMA");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_WFI &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display("%0d: %m.rl_stage1_WFI", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_WFI && cur_verbosity__h3317 == 4'd1)
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
stage1_rg_stage_input[401:338],
stage1_rg_stage_input[263:232],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_WFI &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display(" CPU.rl_stage1_WFI");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_WFI_resume &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display("%0d: %m.rl_WFI_resume", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_WFI_resume &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$write(" %m.enq: pc:0x%0h epoch:%0d priv:%0d",
rg_next_pc,
new_epoch__h18044,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_WFI_resume &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
1'd0,
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_WFI_resume &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_WFI_resume &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display(" fa_stageF_redirect: minstret:%0d new_pc:%0x cur_priv:%0d, epoch %0d->%0d",
csr_regfile$read_csr_mcycle,
csr_regfile$read_csr_minstret,
rg_next_pc,
rg_cur_priv,
rg_epoch,
new_epoch__h18044);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_from_WFI &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display("%0d: %m.rl_reset_from_WFI", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap_fetch &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$write(" %m.enq: pc:0x%0h epoch:%0d priv:%0d",
rg_next_pc,
new_epoch__h18044,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap_fetch &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
1'd0,
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap_fetch &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_trap_fetch &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display(" fa_stageF_redirect: minstret:%0d new_pc:%0x cur_priv:%0d, epoch %0d->%0d",
csr_regfile$read_csr_mcycle,
csr_regfile$read_csr_minstret,
rg_next_pc,
rg_cur_priv,
rg_epoch,
new_epoch__h18044);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_stage1_interrupt &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display("%0d: %m.rl_stage1_interrupt", csr_regfile$read_csr_mcycle);
if (WILL_FIRE_RL_imem_rl_assert_fail)
begin
v__h2136 = $stime;
#0;
end
v__h2130 = v__h2136 / 32'd10;
if (WILL_FIRE_RL_imem_rl_assert_fail)
$display("%0d: ERROR: CPU_Fetch_C: imem32.is_i32_not_i16 is False",
v__h2130);
if (WILL_FIRE_RL_imem_rl_assert_fail) $finish(32'd1);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset)
$display("%0d: %m.rl_reset_complete: restart at PC = 0x%0h",
csr_regfile$read_csr_mcycle,
soc_map$m_pc_reset_value);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$write(" %m.enq: pc:0x%0h epoch:%0d priv:%0d",
soc_map$m_pc_reset_value,
new_epoch__h18044,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
1'd0,
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display(" fa_stageF_redirect: minstret:%0d new_pc:%0x cur_priv:%0d, epoch %0d->%0d",
csr_regfile$read_csr_mcycle,
csr_regfile$read_csr_minstret,
soc_map$m_pc_reset_value,
rg_cur_priv,
rg_epoch,
new_epoch__h18044);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete && !rg_run_on_reset)
$display("%0d: %m.rl_reset_complete: entering DEBUG_MODE",
csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display("%0d: %m.rl_pipe", csr_regfile$read_csr_mcycle);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[69] &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display(" S3.fa_deq: write GRd 0x%0h, rd_val 0x%0h",
stage3_rg_stage3[68:64],
stage3_rg_stage3[63:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd2 &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$write(" S3.enq: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd2 &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$write("data_to_Stage3 {pc:%h instr:%h priv:%0d\n",
stage2_rg_stage2[295:232],
stage2_rg_stage2[231:200],
stage2_rg_stage2[297:296]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd2 &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$write(" rd_valid:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd2 &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49 &&
stage2_rg_stage2[199:197] != 3'd0 &&
IF_stage2_rg_stage2_01_BITS_199_TO_197_02_EQ_1_ETC___d145)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd2 &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49 &&
(stage2_rg_stage2[199:197] == 3'd0 ||
IF_stage2_rg_stage2_01_BITS_199_TO_197_02_EQ_1_ETC___d154))
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd2 &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$write(" grd:%0d rd_val:%h\n",
x_out_data_to_stage3_rd__h7080,
x_out_data_to_stage3_rd_val__h7081);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd2 &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_stage2_rg_full_00_THEN_IF_stage2_rg_stage2__ETC___d131 == 2'd2 &&
cur_verbosity__h3317 == 4'd1)
$display("instret:%0d PC:0x%0h instr:0x%0h priv:%0d",
csr_regfile$read_csr_minstret,
stage2_rg_stage2[295:232],
stage2_rg_stage2[231:200],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1581 &&
stage1_rg_full &&
(!stage1_rg_stage_input_04_BITS_335_TO_334_05_EQ_ETC___d206 ||
NOT_IF_stage2_rg_full_00_THEN_IF_stage2_rg_sta_ETC___d1522) &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 == 4'd0 &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display(" rl_pipe: Discarding stage1 due to redirection");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1617)
$write(" CPU_Stage2.enq (Data_Stage1_to_Stage2) ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1617)
$write("data_to_Stage 2 {pc:%h instr:%h priv:%0d\n",
stage1_rg_stage_input[401:338],
stage1_rg_stage_input[263:232],
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1617)
$write(" op_stage2:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1588 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 != 4'd0 &&
IF_NOT_stage1_rg_full_03_87_OR_NOT_stage1_rg_s_ETC___d1591 &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d690 == 3'd0)
$write("OP_Stage2_ALU");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1588 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 != 4'd0 &&
IF_NOT_stage1_rg_full_03_87_OR_NOT_stage1_rg_s_ETC___d1591 &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d690 == 3'd1)
$write("OP_Stage2_LD");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1588 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 != 4'd0 &&
IF_NOT_stage1_rg_full_03_87_OR_NOT_stage1_rg_s_ETC___d1591 &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d690 == 3'd2)
$write("OP_Stage2_ST");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1588 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 != 4'd0 &&
IF_NOT_stage1_rg_full_03_87_OR_NOT_stage1_rg_s_ETC___d1591 &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d690 == 3'd3)
$write("OP_Stage2_M");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1588 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d544 != 4'd0 &&
IF_NOT_stage1_rg_full_03_87_OR_NOT_stage1_rg_s_ETC___d1591 &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d690 != 3'd0 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d690 != 3'd1 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d690 != 3'd2 &&
IF_stage1_rg_stage_input_04_BITS_335_TO_334_05_ETC___d690 != 3'd3)
$write("OP_Stage2_AMO");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1617)
$write(" rd:%0d\n", x_out_data_to_stage2_rd__h7707);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1617)
$write(" addr:%h val1:%h val2:%h}",
x_out_data_to_stage2_addr__h7708,
x_out_data_to_stage2_val1__h7709,
x_out_data_to_stage2_val2__h7710);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d1617)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1643 &&
stageD_rg_full &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display(" CPU_Stage1.enq: 0x%08h", stageD_rg_data[233:170]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1684 &&
NOT_IF_csr_regfile_read_csr_minstret__3_ULT_cf_ETC___d49)
$display(" CPU_StageD.enq (Data_StageF_to_StageD)");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1684 &&
csr_regfile_interrupt_pending_rg_cur_priv_1_50_ETC___d1701)
$write(" %m.enq: pc:0x%0h epoch:%0d priv:%0d",
stageF_branch_predictor$predict_rsp,
stageF_rg_epoch,
rg_cur_priv);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1684 &&
csr_regfile_interrupt_pending_rg_cur_priv_1_50_ETC___d1701)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
1'd0,
csr_regfile$read_mstatus[19],
csr_regfile$read_satp);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_pipe &&
IF_NOT_csr_regfile_interrupt_pending_rg_cur_pr_ETC___d1684 &&
csr_regfile_interrupt_pending_rg_cur_priv_1_50_ETC___d1701)
$display("");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_start)
$display("================================================================");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_start)
$write("CPU: Bluespec RISC-V Flute v3.0");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_start) $display(" (RV64)");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_start)
$display("Copyright (c) 2016-2020 Bluespec, Inc. All Rights Reserved.");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_start)
$display("================================================================");
end
// synopsys translate_on
endmodule // mkCPU
|
// Copyright (c) 2014 Takashi Toyoshima <[email protected]>.
// All rights reserved. Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
module UARTSpartan3StarterKit(
// Clock Sources
CLK50MHZ,
SOCKET,
// Fast, Asynchronous SRAM
SRAM_A,
SRAM_WE_X,
SRAM_OE_X,
SRAM_IO_A,
SRAM_CE_A_X,
SRAM_LB_A_X,
SRAM_UB_A_X,
SRAM_IO_B,
SRAM_CE_B_X,
SRAM_LB_B_X,
SRAM_UB_B_X,
// Four-Digit, Saven-Segment LED Display
LED_AN,
LED_A,
LED_B,
LED_C,
LED_D,
LED_E,
LED_F,
LED_G,
LED_DP,
// Switch
SW,
// Button
BTN,
// LED
LD,
// VGA Port
VGA_R,
VGA_G,
VGA_B,
VGA_HS,
VGA_VS,
// PS2
PS2C,
PS2D,
// RS-232 Serial Port
RXD,
TXD,
RXDA,
TXDA,
// Platform Flash (XCF02S Serial PROM)
DIN,
INIT_B,
RCLK);
input CLK50MHZ;
input SOCKET;
output [17:0] SRAM_A;
output SRAM_WE_X;
output SRAM_OE_X;
inout [15:0] SRAM_IO_A;
output SRAM_CE_A_X;
output SRAM_LB_A_X;
output SRAM_UB_A_X;
inout [15:0] SRAM_IO_B;
output SRAM_CE_B_X;
output SRAM_LB_B_X;
output SRAM_UB_B_X;
output [ 3:0] LED_AN;
output LED_A;
output LED_B;
output LED_C;
output LED_D;
output LED_E;
output LED_F;
output LED_G;
output LED_DP;
input [ 7:0] SW;
input [ 3:0] BTN;
output [ 7:0] LD;
output VGA_R;
output VGA_G;
output VGA_B;
output VGA_HS;
output VGA_VS;
input PS2C;
input PS2D;
input RXD;
output TXD;
input RXDA;
output TXDA;
input DIN;
output INIT_B;
output RCLK;
wire clk;
wire rst_x;
wire w_clk49khz;
wire w_tx_error;
wire w_rx_error;
wire [ 7:0] w_data;
reg [ 9:0] r_clock;
reg r_clk463khz;
reg [ 5:0] r_clk463khz_count;
assign SRAM_A = 18'h00000;
assign SRAM_WE_X = 1'b0;
assign SRAM_OE_X = 1'b1;
assign SRAM_IO_A = 16'hffff;
assign SRAM_CE_A_X = 1'b1;
assign SRAM_LB_A_X = 1'b1;
assign SRAM_UB_A_X = 1'b1;
assign SRAM_IO_B = 16'hffff;
assign SRAM_CE_B_X = 1'b1;
assign SRAM_LB_B_X = 1'b1;
assign SRAM_UB_B_X = 1'b1;
assign LD = SW | { 1'b0, BTN, PS2D, PS2C, SOCKET };
assign VGA_R = 1'b0;
assign VGA_G = 1'b0;
assign VGA_B = 1'b0;
assign VGA_HS = 1'b1;
assign VGA_VS = 1'b1;
assign TXDA = RXDA;
assign INIT_B = DIN;
assign RCLK = DIN;
assign clk = CLK50MHZ;
assign rst_x = !BTN[3];
assign w_clk49khz = r_clock[9];
always @ (posedge clk or negedge rst_x) begin
if (!rst_x) begin
r_clock <= 10'h000;
end else begin
r_clock <= r_clock + 10'h001;
end
end
always @ (posedge clk or negedge rst_x) begin
if (!rst_x) begin
r_clk463khz <= 1'b0;
r_clk463khz_count <= 6'h00;
end else begin
if (r_clk463khz_count != 6'h35) begin
r_clk463khz_count <= r_clk463khz_count + 6'h01;
end else begin
r_clk463khz_count <= 6'h00;
r_clk463khz <= !r_clk463khz;
end
end
end
FourDigitSevenSegmentLED led(
.clk (w_clk49khz ),
.rst_x (rst_x ),
.i_data3 (4'b0000 ),
.i_data2 (4'b0000 ),
.i_data1 (w_data[7:4]),
.i_data0 (w_data[3:0]),
.i_dp3 (!w_tx_error),
.i_dp2 (!w_rx_error),
.i_dp1 (1'b1 ),
.i_dp0 (1'b1 ),
.o_a (LED_A ),
.o_b (LED_B ),
.o_c (LED_C ),
.o_d (LED_D ),
.o_e (LED_E ),
.o_f (LED_F ),
.o_g (LED_G ),
.o_dp (LED_DP ),
.o_select (LED_AN ));
// 115200Hz UART
UARTSample uart(
.clk4x (r_clk463khz),
.rst_x (rst_x ),
.i_rx (RXD ),
.o_tx (TXD ),
.o_data (w_data ),
.o_tx_error(w_tx_error ),
.o_rx_error(w_rx_error ));
endmodule // UARTSpartan3StarterKit
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO1P_BLACKBOX_V
`define SKY130_FD_SC_LP__INPUTISO1P_BLACKBOX_V
/**
* inputiso1p: Input isolation, noninverted sleep.
*
* X = (A & !SLEEP)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__inputiso1p (
X ,
A ,
SLEEP
);
output X ;
input A ;
input SLEEP;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO1P_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2111A_BLACKBOX_V
`define SKY130_FD_SC_HS__O2111A_BLACKBOX_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o2111a (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2111A_BLACKBOX_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:57:07 03/28/2014
// Design Name: alu
// Module Name: D:/XilinxProject/CPU/alu_tester.v
// Project Name: CPU
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: alu
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module alu_tester;
// Inputs
reg [31:0] a;
reg [31:0] b;
reg [3:0] aluc;
// Outputs
wire zero;
wire [31:0] result;
// Instantiate the Unit Under Test (UUT)
alu uut (
.a(a),
.b(b),
.aluc(aluc),
.zero(zero),
.result(result)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
aluc = 0;
// Wait 100 ns for global reset to finish
#100;
a = 127;
b = 128;
aluc = 3;
#100;
a = 128;
b = 128;
aluc = 3;
#100;
a = 1;
b = 1;
aluc = 8;
// Add stimulus here
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2BB2A_SYMBOL_V
`define SKY130_FD_SC_LP__O2BB2A_SYMBOL_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o2bb2a (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2BB2A_SYMBOL_V
|
`timescale 1ns / 1ns
/******************************************************************************
* (C) Copyright 2016 AGH UST All Rights Reserved
*
* MODULE: clk_divider
* DEVICE: general
* PROJECT: stopwatch
*
* ABSTRACT: The clock divider module. Assuming 100MHz input clock
*
* HISTORY:
* 1 Jan 2016, RS - initial version
* 7 Jan 2016, HG - dodano parametr FREQ pozwalajacy
na ustalenie pozadanej czestotliwosci
*
*******************************************************************************/
module clk_divider
# ( parameter
FREQ = 100 // clock freqency
)
(
input wire clk100MHz, // input clock 100 MHz
input wire rst, // async reset active high
output reg clk_div // output clock
);
// when the counter should restart from zero
localparam LOOP_COUNTER_AT = 1_000_000 / 2 / (FREQ/100) ;
reg [clog2(LOOP_COUNTER_AT)-1:0] count;
always @( posedge(clk100MHz), posedge(rst) )
begin
if(rst)
begin : counter_reset
count <= #1 0;
clk_div <= #1 1'b0;
end
else
begin : counter_operate
if (count == (LOOP_COUNTER_AT - 1))
begin : counter_loop
count <= #1 0;
clk_div <= #1 ~clk_div;
end
else
begin : counter_increment
count <= #1 count + 1;
clk_div <= #1 clk_div;
end
end
end
// function to calculate number of bits necessary to store the number
// (ceiling of base 2 logarithm)
function integer clog2(input integer number);
begin
clog2 = 0;
while (number)
begin
clog2 = clog2 + 1;
number = number >> 1;
end
end
endfunction
endmodule
|
/**
* The ps2 protocol is here http://www.computer-engineering.org/ps2protocol/
*/
module ps2controller (
input reset,
input i_clock,
input i_data,
output scan_ready,
output [7:0] scan_code
);
reg [7:0] r_scan_code;
reg [3:0] counter;
reg ready;
assign scan_code = r_scan_code;
assign scan_ready = ready;
// Read the ps2 data.
always @(negedge i_clock or posedge reset) begin
if (reset) begin
r_scan_code = 8'b0;
counter = 4'd0;
end else begin
if (counter == 4'd0) begin
// 1 start bit. This is always 0.
ready = 1'b0;
r_scan_code = 8'b0;
counter = counter + 4'd1;
end else if (counter == 4'd9) begin
// 1 parity bit (odd parity).
if (!i_data == ^r_scan_code) begin
ready = 1'b1;
end
counter = counter + 4'd1;
end else if (counter == 4'd10) begin
// 1 stop bit. This is always 1.
counter = 4'd0;
end else begin
// 8 data bits, least significant bit first.
r_scan_code[counter] = i_data;
counter = counter + 4'd1;
ready = 1'b0;
end
end
end
endmodule
|
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