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// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 22233 $
// $Date: 2010-10-09 13:26:19 +0000 (Sat, 09 Oct 2010) $
`ifdef BSV_NO_MAIN_V
`else
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_TIMESCALE
`timescale `BSV_TIMESCALE
`endif
module main();
reg CLK;
// reg CLK_GATE;
reg RST_N;
reg [31:0] cycle;
reg do_vcd;
reg do_fsdb;
reg do_fst;
reg do_cycles;
`TOP top(.CLK(CLK), /* .CLK_GATE(CLK_GATE), */ .RST_N(RST_N));
// For Sce-Mi linkage, insert code here
`ifdef BSV_SCEMI_LINK
`include `BSV_SCEMI_LINK
`endif
`ifdef BSV_DUMP_LEVEL
`else
`define BSV_DUMP_LEVEL 0
`endif
`ifdef BSV_DUMP_TOP
`else
`define BSV_DUMP_TOP main
`endif
initial begin
// CLK_GATE = 1'b1;
// CLK = 1'b0; // This line will cause a neg edge of clk at t=0!
// RST_N = 1'b0; // This needs #0, to allow always blocks to wait
cycle = 0;
do_vcd = $test$plusargs("bscvcd") ;
do_fst = $test$plusargs("bscfst") ;
do_fsdb = $test$plusargs("bscfsdb") ;
do_cycles = $test$plusargs("bsccycle") ;
`ifdef BSC_FSDB
if (do_fsdb) begin
$fsdbDumpfile("dump.fsdb");
$fsdbDumpvars(`BSV_DUMP_LEVEL, `BSV_DUMP_TOP);
end
`else
// if (do_fst && ! do_vcd) begin
// $dumpfile("|vcd2fst -F -f dump.fst -");
// $dumpvars(`BSV_DUMP_LEVEL, `BSV_DUMP_TOP);
// end
if (do_vcd) begin
$dumpfile("dump.vcd");
$dumpvars(`BSV_DUMP_LEVEL, `BSV_DUMP_TOP);
end
`endif
#0
RST_N = 1'b0;
#1;
CLK = 1'b1;
// $display("reset");
#1;
RST_N = 1'b1;
// $display("reset done");
// #200010;
// $finish;
end
`ifndef NO_CLOCK // for cosim
always
begin
#1
if (do_cycles)
$display("cycle %0d", cycle) ;
cycle = cycle + 1 ;
#4;
CLK = 1'b0 ;
#5;
CLK = 1'b1 ;
end // always begin
`endif // `ifndef NO_CLOCK
endmodule
`endif
|
`timescale 1ns/1ps
`define CLOG2(x) \
(x <= 2) ? 1 : \
(x <= 4) ? 2 : \
(x <= 8) ? 3 : \
(x <= 16) ? 4 : \
(x <= 32) ? 5 : \
(x <= 64) ? 6 : \
(x <= 128) ? 7 : \
(x <= 256) ? 8 : \
(x <= 512) ? 9 : \
(x <= 1024) ? 10 : \
(x <= 2048) ? 11 : \
(x <= 4096) ? 12 : \
-1
module tb_cocotb #(
parameter DATA_WIDTH = 32, //This is the output bus
parameter ADDR_WIDTH = 32,
parameter MAX_PACKET_SIZE = 4096,
parameter MAX_PACKET_WIDTH = `CLOG2(MAX_PACKET_SIZE),
parameter INTERRUPT_WIDTH = 32
)(
//Virtual Host Interface Signals
input clk,
input rst,
input [31:0] test_id,
input CMD_EN,
output CMD_ERROR,
output CMD_ACK,
input [ADDR_WIDTH - 1:0] CMD_ADR,
input CMD_ADR_FIXED,
input CMD_ADR_WRAP,
input CMD_WR_RD, //1 = wRITE, 0 = rEAD
input [MAX_PACKET_WIDTH - 1: 0]CMD_COUNT,
output [31:0] CMD_STATUS,
output CMD_INTERRUPT,
//Data FIFOs
//write side
input WR_CLK,
output [1:0] WR_RDY,
input [1:0] WR_ACT,
output [23:0] WR_SIZE,
input WR_STB,
input [DATA_WIDTH - 1: 0] WR_DATA,
output WR_STARVED,
//read side
input RD_CLK,
input RD_STB,
output RD_RDY,
input RD_ACT,
output [23:0] RD_SIZE,
output [DATA_WIDTH - 1: 0] RD_DATA,
//NOT IMPLEMENTED YET
/*
input [2:0] i_cmd_txrx_width, //0 = 8-bit, 1 = 16-bit, 16-bit, 2 = 32-bit...
input [3:0] i_cmd_aw_id, //Add an ide to the write/command paths
input [3:0] i_cmd_w_id,
input [3:0] i_cmd_ar_id,
output [3:0] o_cmd_r_id,
output [3:0] o_cmd_b_id,
*/
//***************** AXI Bus ************************************************
//bus write addr path
output [3:0] AXIS_AWID, //Write ID
output [ADDR_WIDTH - 1:0] AXIS_AWADDR, //Write Addr Path Address
output [7:0] AXIS_AWLEN, //Write Addr Path Burst Length
output [2:0] AXIS_AWSIZE, //Write Addr Path Burst Size (Byte with (00 = 8 bits wide, 01 = 16 bits wide)
output [1:0] AXIS_AWBURST, //Write Addr Path Burst Type
// 0 = Fixed
// 1 = Incrementing
// 2 = wrap
output [1:0] AXIS_AWLOCK, //Write Addr Path Lock (atomic) information
// 0 = Normal
// 1 = Exclusive
// 2 = Locked
output [3:0] AXIS_AWCACHE, //Write Addr Path Cache Type
output [2:0] AXIS_AWPROT, //Write Addr Path Protection Type
output AXIS_AWVALID, //Write Addr Path Address Valid
input AXIS_AWREADY, //Write Addr Path Slave Ready
// 1 = Slave Ready
// 0 = Slave Not Ready
//bus write data
output [3:0] AXIS_WID, //Write ID
output [DATA_WIDTH - 1: 0] AXIS_WDATA, //Write Data (this size is set with the DATA_WIDTH Parameter
//Valid values are: 8, 16, 32, 64, 128, 256, 512, 1024
output [(DATA_WIDTH >> 3) - 1:0] AXIS_WSTRB, //Write Strobe (a 1 in the write is associated with the byte to write)
output AXIS_WLAST, //Write Last transfer in a write burst
output AXIS_WVALID, //Data through this bus is valid
input AXIS_WREADY, //Slave is ready for data
//Write Response Channel
input [3:0] AXIS_BID, //Response ID (this must match awid)
input [1:0] AXIS_BRESP, //Write Response
// 0 = OKAY
// 1 = EXOKAY
// 2 = SLVERR
// 3 = DECERR
input AXIS_BVALID, //Write Response is:
// 1 = Available
// 0 = Not Available
output AXIS_BREADY, //WBM Ready
//bus read addr path
output [3:0] AXIS_ARID, //Read ID
output [ADDR_WIDTH - 1:0] AXIS_ARADDR, //Read Addr Path Address
output [7:0] AXIS_ARLEN, //Read Addr Path Burst Length
output [2:0] AXIS_ARSIZE, //Read Addr Path Burst Size (Byte with (00 = 8 bits wide, 01 = 16 bits wide)
output [1:0] AXIS_ARBURST, //Read Addr Path Burst Type
output [1:0] AXIS_ARLOCK, //Read Addr Path Lock (atomic) information
output [3:0] AXIS_ARCACHE, //Read Addr Path Cache Type
output [2:0] AXIS_ARPROT, //Read Addr Path Protection Type
output AXIS_ARVALID, //Read Addr Path Address Valid
input AXIS_ARREADY, //Read Addr Path Slave Ready
// 1 = Slave Ready
// 0 = Slave Not Ready
//bus read data
input [3:0] AXIS_RID, //Write ID
input [DATA_WIDTH - 1: 0] AXIS_RDATA, //Write Data (this size is set with the DATA_WIDTH Parameter
//Valid values are: 8, 16, 32, 64, 128, 256, 512, 1024
input [1:0] AXIS_RRESP,
input [(DATA_WIDTH >> 3) - 1:0] AXIS_RSTRB, //Write Strobe (a 1 in the write is associated with the byte to write)
input AXIS_RLAST, //Write Last transfer in a write burst
input AXIS_RVALID, //Data through this bus is valid
output AXIS_RREADY, //WBM is ready for data
// 1 = WBM Ready
// 0 = Slave Ready
input [INTERRUPT_WIDTH - 1:0] i_interrupts
);
//Local Parameters
localparam INVERT_AXI_RESET = 0;
localparam FIFO_DEPTH = 8; //256
localparam ENABLE_NACK = 0; //Enable timeout
localparam DEFAULT_TIMEOUT = 32'd100000000; //1 Second at 100MHz
//Registers/Wires
reg r_rst;
wire [INTERRUPT_WIDTH - 1:0] w_interrupts;
//Submodules
axi_master #(
.INVERT_AXI_RESET (INVERT_AXI_RESET ),
.MAX_PACKET_SIZE (MAX_PACKET_SIZE ),
.ADDR_WIDTH (ADDR_WIDTH ),
.DATA_WIDTH (DATA_WIDTH ),
.INTERRUPT_WIDTH (INTERRUPT_WIDTH ),
.ENABLE_NACK (ENABLE_NACK ),
.DEFAULT_TIMEOUT (DEFAULT_TIMEOUT )
) am (
.clk (clk ),
.rst (r_rst ),
//************* User Facing Side *******************************************
.i_cmd_en (CMD_EN ),
.o_cmd_error (CMD_ERROR ),
.o_cmd_ack (CMD_ACK ),
.o_cmd_status (CMD_STATUS ),
.o_cmd_interrupt (CMD_INTERRUPT ),
.i_cmd_addr (CMD_ADR ),
.i_cmd_adr_fixed_en (CMD_ADR_FIXED ),
.i_cmd_adr_wrap_en (CMD_ADR_WRAP ),
.i_cmd_wr_rd (CMD_WR_RD ),
.i_cmd_data_count (CMD_COUNT ),
//Data FIFOs
.i_ingress_clk (WR_CLK ),
.o_ingress_rdy (WR_RDY ),
.i_ingress_act (WR_ACT ),
.i_ingress_stb (WR_STB ),
.i_ingress_data (WR_DATA ),
.o_ingress_size (WR_SIZE ),
.i_egress_clk (RD_CLK ),
.o_egress_rdy (RD_RDY ),
.i_egress_act (RD_ACT ),
.i_egress_stb (RD_STB ),
.o_egress_data (RD_DATA ),
.o_egress_size (RD_SIZE ),
//***************** AXI Bus ************************************************
//bus write addr path
.o_awid (AXIS_AWID ),
.o_awaddr (AXIS_AWADDR ),
.o_awlen (AXIS_AWLEN ),
.o_awsize (AXIS_AWSIZE ),
.o_awburst (AXIS_AWBURST ),
.o_awlock (AXIS_AWLOCK ),
.o_awcache (AXIS_AWCACHE ),
.o_awprot (AXIS_AWPROT ),
.o_awvalid (AXIS_AWVALID ),
.i_awready (AXIS_AWREADY ),
//bus write data
.o_wid (AXIS_WID ),
.o_wdata (AXIS_WDATA ),
.o_wstrobe (AXIS_WSTRB ),
.o_wlast (AXIS_WLAST ),
.o_wvalid (AXIS_WVALID ),
.i_wready (AXIS_WREADY ),
//Write Response Channel
.i_bid (AXIS_BID ),
.i_bresp (AXIS_BRESP ),
.i_bvalid (AXIS_BVALID ),
.o_bready (AXIS_BREADY ),
//bus read addr path
.o_arid (AXIS_ARID ),
.o_araddr (AXIS_ARADDR ),
.o_arlen (AXIS_ARLEN ),
.o_arsize (AXIS_ARSIZE ),
.o_arburst (AXIS_ARBURST ),
.o_arlock (AXIS_ARLOCK ),
.o_arcache (AXIS_ARCACHE ),
.o_arprot (AXIS_ARPROT ),
.o_arvalid (AXIS_ARVALID ),
.i_arready (AXIS_ARREADY ),
//bus read data
.i_rid (AXIS_RID ),
.i_rdata (AXIS_RDATA ),
.i_rresp (AXIS_RRESP ),
.i_rstrobe (AXIS_RSTRB ),
.i_rlast (AXIS_RLAST ),
.i_rvalid (AXIS_RVALID ),
.o_rready (AXIS_RREADY ),
//nterrupts
.i_interrupts (i_interrupts )
);
//There is a timing thing in COCOTB when stiumlating a signal, sometimes it can be corrupted if not registered
always @ (*) r_rst = rst;
//Submodules
//Asynchronous Logic
//Synchronous Logic
//Simulation Control
initial begin
$dumpfile ("design.vcd");
$dumpvars(0, tb_cocotb);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__ISOBUFSRC_TB_V
`define SKY130_FD_SC_HDLL__ISOBUFSRC_TB_V
/**
* isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__isobufsrc.v"
module top();
// Inputs are registered
reg SLEEP;
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
SLEEP = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 SLEEP = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 SLEEP = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 SLEEP = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 SLEEP = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 SLEEP = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hdll__isobufsrc dut (.SLEEP(SLEEP), .A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__ISOBUFSRC_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFSTP_FUNCTIONAL_V
`define SKY130_FD_SC_MS__SDFSTP_FUNCTIONAL_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps/sky130_fd_sc_ms__udp_dff_ps.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_ms__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_ms__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFSTP_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFBBP_BLACKBOX_V
`define SKY130_FD_SC_MS__DFBBP_BLACKBOX_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dfbbp (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFBBP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A22OI_SYMBOL_V
`define SKY130_FD_SC_HS__A22OI_SYMBOL_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a22oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A22OI_SYMBOL_V
|
(** * IndPrinciples: Induction Principles *)
(** With the Curry-Howard correspondence and its realization in Coq in
mind, we can now take a deeper look at induction principles. *)
Require Export ProofObjects.
(* ################################################################# *)
(** * Basics *)
(** Every time we declare a new [Inductive] datatype, Coq
automatically generates an _induction principle_ for this type.
This induction principle is a theorem like any other: If [t] is
defined inductively, the corresponding induction principle is
called [t_ind]. Here is the one for natural numbers: *)
Check nat_ind.
(* ===> nat_ind :
forall P : nat -> Prop,
P 0 ->
(forall n : nat, P n -> P (S n)) ->
forall n : nat, P n *)
(** The [induction] tactic is a straightforward wrapper that, at its
core, simply performs [apply t_ind]. To see this more clearly,
let's experiment with directly using [apply nat_ind], instead of
the [induction] tactic, to carry out some proofs. Here, for
example, is an alternate proof of a theorem that we saw in the
[Basics] chapter. *)
Theorem mult_0_r' : forall n:nat,
n * 0 = 0.
Proof.
apply nat_ind.
- (* n = O *) reflexivity.
- (* n = S n' *) simpl. intros n' IHn'. rewrite -> IHn'.
reflexivity. Qed.
(** This proof is basically the same as the earlier one, but a
few minor differences are worth noting.
First, in the induction step of the proof (the ["S"] case), we
have to do a little bookkeeping manually (the [intros]) that
[induction] does automatically.
Second, we do not introduce [n] into the context before applying
[nat_ind] -- the conclusion of [nat_ind] is a quantified formula,
and [apply] needs this conclusion to exactly match the shape of
the goal state, including the quantifier. By contrast, the
[induction] tactic works either with a variable in the context or
a quantified variable in the goal.
These conveniences make [induction] nicer to use in practice than
applying induction principles like [nat_ind] directly. But it is
important to realize that, modulo these bits of bookkeeping,
applying [nat_ind] is what we are really doing. *)
(** **** Exercise: 2 stars, optional (plus_one_r') *)
(** Complete this proof without using the [induction] tactic. *)
Theorem plus_one_r' : forall n:nat,
n + 1 = S n.
Proof.
apply nat_ind.
- reflexivity.
- intros. simpl. rewrite -> H. reflexivity.
Qed.
(** [] *)
(** Coq generates induction principles for every datatype defined with
[Inductive], including those that aren't recursive. Although of
course we don't need induction to prove properties of
non-recursive datatypes, the idea of an induction principle still
makes sense for them: it gives a way to prove that a property
holds for all values of the type.
These generated principles follow a similar pattern. If we define
a type [t] with constructors [c1] ... [cn], Coq generates a
theorem with this shape:
t_ind : forall P : t -> Prop,
... case for c1 ... ->
... case for c2 ... -> ...
... case for cn ... ->
forall n : t, P n
The specific shape of each case depends on the arguments to the
corresponding constructor. Before trying to write down a general
rule, let's look at some more examples. First, an example where
the constructors take no arguments: *)
Inductive yesno : Type :=
| yes : yesno
| no : yesno.
Check yesno_ind.
(* ===> yesno_ind : forall P : yesno -> Prop,
P yes ->
P no ->
forall y : yesno, P y *)
(** **** Exercise: 1 star, optional (rgb) *)
(** Write out the induction principle that Coq will generate for the
following datatype. Write down your answer on paper or type it
into a comment, and then compare it with what Coq prints. *)
Inductive rgb : Type :=
| red : rgb
| green : rgb
| blue : rgb.
(* rgb_ind : forall P : rgb -> Prop,
P red -> P green -> P blue ->
forall y : rgb, P y *)
Check rgb_ind.
(** [] *)
(** Here's another example, this time with one of the constructors
taking some arguments. *)
Inductive natlist : Type :=
| nnil : natlist
| ncons : nat -> natlist -> natlist.
Check natlist_ind.
(* ===> (modulo a little variable renaming)
natlist_ind :
forall P : natlist -> Prop,
P nnil ->
(forall (n : nat) (l : natlist),
P l -> P (ncons n l)) ->
forall n : natlist, P n *)
(** **** Exercise: 1 star, optional (natlist1) *)
(** Suppose we had written the above definition a little
differently: *)
Inductive natlist1 : Type :=
| nnil1 : natlist1
| nsnoc1 : natlist1 -> nat -> natlist1.
(** Now what will the induction principle look like? *)
(** natlist1_ind : forall P : natlist1 -> Prop,
P nnil1 -> (forall l : natlist1, P l -> forall n : nat, P (nsnoc1 l n)) ->
forall r : natlist1, P r *)
Check natlist1_ind.
(** From these examples, we can extract this general rule:
- The type declaration gives several constructors; each
corresponds to one clause of the induction principle.
- Each constructor [c] takes argument types [a1] ... [an].
- Each [ai] can be either [t] (the datatype we are defining) or
some other type [s].
- The corresponding case of the induction principle says:
- "For all values [x1]...[xn] of types [a1]...[an], if [P]
holds for each of the inductive arguments (each [xi] of type
[t]), then [P] holds for [c x1 ... xn]".
*)
(** **** Exercise: 1 star, optional (byntree_ind) *)
(** Write out the induction principle that Coq will generate for the
following datatype. (Again, write down your answer on paper or
type it into a comment, and then compare it with what Coq
prints.) *)
Inductive byntree : Type :=
| bempty : byntree
| bleaf : yesno -> byntree
| nbranch : yesno -> byntree -> byntree -> byntree.
(** [] *)
(** **** Exercise: 1 star, optional (ex_set) *)
(** Here is an induction principle for an inductively defined
set.
ExSet_ind :
forall P : ExSet -> Prop,
(forall b : bool, P (con1 b)) ->
(forall (n : nat) (e : ExSet), P e -> P (con2 n e)) ->
forall e : ExSet, P e
Give an [Inductive] definition of [ExSet]: *)
Inductive ExSet : Type :=
(* FILL IN HERE *)
.
(** [] *)
(* ################################################################# *)
(** * Polymorphism *)
(** Next, what about polymorphic datatypes?
The inductive definition of polymorphic lists
Inductive list (X:Type) : Type :=
| nil : list X
| cons : X -> list X -> list X.
is very similar to that of [natlist]. The main difference is
that, here, the whole definition is _parameterized_ on a set [X]:
that is, we are defining a _family_ of inductive types [list X],
one for each [X]. (Note that, wherever [list] appears in the body
of the declaration, it is always applied to the parameter [X].)
The induction principle is likewise parameterized on [X]:
list_ind :
forall (X : Type) (P : list X -> Prop),
P [] ->
(forall (x : X) (l : list X), P l -> P (x :: l)) ->
forall l : list X, P l
Note that the _whole_ induction principle is parameterized on
[X]. That is, [list_ind] can be thought of as a polymorphic
function that, when applied to a type [X], gives us back an
induction principle specialized to the type [list X]. *)
(** **** Exercise: 1 star, optional (tree) *)
(** Write out the induction principle that Coq will generate for
the following datatype. Compare your answer with what Coq
prints. *)
Inductive tree (X:Type) : Type :=
| leaf : X -> tree X
| node : tree X -> tree X -> tree X.
Check tree_ind.
(** [] *)
(** **** Exercise: 1 star, optional (mytype) *)
(** Find an inductive definition that gives rise to the
following induction principle:
mytype_ind :
forall (X : Type) (P : mytype X -> Prop),
(forall x : X, P (constr1 X x)) ->
(forall n : nat, P (constr2 X n)) ->
(forall m : mytype X, P m ->
forall n : nat, P (constr3 X m n)) ->
forall m : mytype X, P m
*)
(** [] *)
(** **** Exercise: 1 star, optional (foo) *)
(** Find an inductive definition that gives rise to the
following induction principle:
foo_ind :
forall (X Y : Type) (P : foo X Y -> Prop),
(forall x : X, P (bar X Y x)) ->
(forall y : Y, P (baz X Y y)) ->
(forall f1 : nat -> foo X Y,
(forall n : nat, P (f1 n)) -> P (quux X Y f1)) ->
forall f2 : foo X Y, P f2
*)
(** [] *)
(** **** Exercise: 1 star, optional (foo') *)
(** Consider the following inductive definition: *)
Inductive foo' (X:Type) : Type :=
| C1 : list X -> foo' X -> foo' X
| C2 : foo' X.
(** What induction principle will Coq generate for [foo']? Fill
in the blanks, then check your answer with Coq.)
foo'_ind :
forall (X : Type) (P : foo' X -> Prop),
(forall (l : list X) (f : foo' X),
_______________________ ->
_______________________ ) ->
___________________________________________ ->
forall f : foo' X, ________________________
*)
(** [] *)
(* ################################################################# *)
(** * Induction Hypotheses *)
(** Where does the phrase "induction hypothesis" fit into this story?
The induction principle for numbers
forall P : nat -> Prop,
P 0 ->
(forall n : nat, P n -> P (S n)) ->
forall n : nat, P n
is a generic statement that holds for all propositions
[P] (or rather, strictly speaking, for all families of
propositions [P] indexed by a number [n]). Each time we
use this principle, we are choosing [P] to be a particular
expression of type [nat->Prop].
We can make proofs by induction more explicit by giving
this expression a name. For example, instead of stating
the theorem [mult_0_r] as "[forall n, n * 0 = 0]," we can
write it as "[forall n, P_m0r n]", where [P_m0r] is defined
as... *)
Definition P_m0r (n:nat) : Prop :=
n * 0 = 0.
(** ... or equivalently: *)
Definition P_m0r' : nat->Prop :=
fun n => n * 0 = 0.
(** Now it is easier to see where [P_m0r] appears in the proof. *)
Theorem mult_0_r'' : forall n:nat,
P_m0r n.
Proof.
apply nat_ind.
- (* n = O *) reflexivity.
- (* n = S n' *)
(* Note the proof state at this point! *)
intros n IHn.
unfold P_m0r in IHn. unfold P_m0r. simpl. apply IHn. Qed.
(** This extra naming step isn't something that we do in
normal proofs, but it is useful to do it explicitly for an example
or two, because it allows us to see exactly what the induction
hypothesis is. If we prove [forall n, P_m0r n] by induction on
[n] (using either [induction] or [apply nat_ind]), we see that the
first subgoal requires us to prove [P_m0r 0] ("[P] holds for
zero"), while the second subgoal requires us to prove [forall n',
P_m0r n' -> P_m0r n' (S n')] (that is "[P] holds of [S n'] if it
holds of [n']" or, more elegantly, "[P] is preserved by [S]").
The _induction hypothesis_ is the premise of this latter
implication -- the assumption that [P] holds of [n'], which we are
allowed to use in proving that [P] holds for [S n']. *)
(* ################################################################# *)
(** * More on the [induction] Tactic *)
(** The [induction] tactic actually does even more low-level
bookkeeping for us than we discussed above.
Recall the informal statement of the induction principle for
natural numbers:
- If [P n] is some proposition involving a natural number n, and
we want to show that P holds for _all_ numbers n, we can
reason like this:
- show that [P O] holds
- show that, if [P n'] holds, then so does [P (S n')]
- conclude that [P n] holds for all n.
So, when we begin a proof with [intros n] and then [induction n],
we are first telling Coq to consider a _particular_ [n] (by
introducing it into the context) and then telling it to prove
something about _all_ numbers (by using induction).
What Coq actually does in this situation, internally, is to
"re-generalize" the variable we perform induction on. For
example, in our original proof that [plus] is associative... *)
Theorem plus_assoc' : forall n m p : nat,
n + (m + p) = (n + m) + p.
Proof.
(* ...we first introduce all 3 variables into the context,
which amounts to saying "Consider an arbitrary [n], [m], and
[p]..." *)
intros n m p.
(* ...We now use the [induction] tactic to prove [P n] (that
is, [n + (m + p) = (n + m) + p]) for _all_ [n],
and hence also for the particular [n] that is in the context
at the moment. *)
induction n as [| n'].
- (* n = O *) reflexivity.
- (* n = S n' *)
(* In the second subgoal generated by [induction] -- the
"inductive step" -- we must prove that [P n'] implies
[P (S n')] for all [n']. The [induction] tactic
automatically introduces [n'] and [P n'] into the context
for us, leaving just [P (S n')] as the goal. *)
simpl. rewrite -> IHn'. reflexivity. Qed.
(** It also works to apply [induction] to a variable that is
quantified in the goal. *)
Theorem plus_comm' : forall n m : nat,
n + m = m + n.
Proof.
induction n as [| n'].
- (* n = O *) intros m. rewrite <- plus_n_O. reflexivity.
- (* n = S n' *) intros m. simpl. rewrite -> IHn'.
rewrite <- plus_n_Sm. reflexivity. Qed.
(** Note that [induction n] leaves [m] still bound in the goal --
i.e., what we are proving inductively is a statement beginning
with [forall m].
If we do [induction] on a variable that is quantified in the goal
_after_ some other quantifiers, the [induction] tactic will
automatically introduce the variables bound by these quantifiers
into the context. *)
Theorem plus_comm'' : forall n m : nat,
n + m = m + n.
Proof.
(* Let's do induction on [m] this time, instead of [n]... *)
induction m as [| m'].
- (* m = O *) simpl. rewrite <- plus_n_O. reflexivity.
- (* m = S m' *) simpl. rewrite <- IHm'.
rewrite <- plus_n_Sm. reflexivity. Qed.
(** **** Exercise: 1 star, optional (plus_explicit_prop) *)
(** Rewrite both [plus_assoc'] and [plus_comm'] and their proofs in
the same style as [mult_0_r''] above -- that is, for each theorem,
give an explicit [Definition] of the proposition being proved by
induction, and state the theorem and proof in terms of this
defined proposition. *)
(* FILL IN HERE *)
(** [] *)
(* ################################################################# *)
(** * Induction Principles in [Prop] *)
(** Earlier, we looked in detail at the induction principles that Coq
generates for inductively defined _sets_. The induction
principles for inductively defined _propositions_ like [ev] are a
tiny bit more complicated. As with all induction principles, we
want to use the induction principle on [ev] to prove things by
inductively considering the possible shapes that something in [ev]
can have. Intuitively speaking, however, what we want to prove
are not statements about _evidence_ but statements about
_numbers_: accordingly, we want an induction principle that lets
us prove properties of numbers by induction on evidence.
For example, from what we've said so far, you might expect the
inductive definition of [ev]...
Inductive ev : nat -> Prop :=
| ev_0 : ev 0
| ev_SS : forall n : nat, ev n -> ev (S (S n)).
...to give rise to an induction principle that looks like this...
ev_ind_max : forall P : (forall n : nat, ev n -> Prop),
P O ev_0 ->
(forall (m : nat) (E : ev m),
P m E ->
P (S (S m)) (ev_SS m E)) ->
forall (n : nat) (E : gorgeous n),
P n E
... because:
- Since [ev] is indexed by a number [n] (every [ev] object [E] is
a piece of evidence that some particular number [n] is even),
the proposition [P] is parameterized by both [n] and [E] --
that is, the induction principle can be used to prove
assertions involving both an even number and the evidence that
it is even.
- Since there are two ways of giving evidence of evenness ([ev]
has two constructors), applying the induction principle
generates two subgoals:
- We must prove that [P] holds for [O] and [ev_0].
- We must prove that, whenever [n] is an even number and [E]
is an evidence of its evenness, if [P] holds of [n] and
[E], then it also holds of [S (S n)] and [ev_SS n E].
- If these subgoals can be proved, then the induction principle
tells us that [P] is true for _all_ even numbers [n] and
evidence [E] of their evenness.
This is more flexibility than we normally need or want: it is
giving us a way to prove logical assertions where the assertion
involves properties of some piece of _evidence_ of evenness, while
all we really care about is proving properties of _numbers_ that
are even -- we are interested in assertions about numbers, not
about evidence. It would therefore be more convenient to have an
induction principle for proving propositions [P] that are
parameterized just by [n] and whose conclusion establishes [P] for
all even numbers [n]:
forall P : nat -> Prop,
... ->
forall n : nat,
even n -> P n
For this reason, Coq actually generates the following simplified
induction principle for [ev]: *)
Check ev_ind.
(* ===> ev_ind
: forall P : nat -> Prop,
P 0 ->
(forall n : nat, ev n -> P n -> P (S (S n))) ->
forall n : nat,
ev n -> P n *)
(** In particular, Coq has dropped the evidence term [E] as a
parameter of the the proposition [P]. *)
(** In English, [ev_ind] says:
- Suppose, [P] is a property of natural numbers (that is, [P n] is
a [Prop] for every [n]). To show that [P n] holds whenever [n]
is even, it suffices to show:
- [P] holds for [0],
- for any [n], if [n] is even and [P] holds for [n], then [P]
holds for [S (S n)]. *)
(** As expected, we can apply [ev_ind] directly instead of using
[induction]. *)
Theorem ev_ev' : forall n, ev n -> ev' n.
Proof.
apply ev_ind.
- (* ev_0 *)
apply ev'_0.
- (* ev_SS *)
intros m Hm IH.
apply (ev'_sum 2 m).
+ apply ev'_2.
+ apply IH.
Qed.
(** The precise form of an [Inductive] definition can affect the
induction principle Coq generates.
For example, in chapter [IndProp], we defined [<=] as: *)
(* Inductive le : nat -> nat -> Prop :=
| le_n : forall n, le n n
| le_S : forall n m, (le n m) -> (le n (S m)). *)
(** This definition can be streamlined a little by observing that the
left-hand argument [n] is the same everywhere in the definition,
so we can actually make it a "general parameter" to the whole
definition, rather than an argument to each constructor. *)
Inductive le (n:nat) : nat -> Prop :=
| le_n : le n n
| le_S : forall m, (le n m) -> (le n (S m)).
Notation "m <= n" := (le m n).
(** The second one is better, even though it looks less symmetric.
Why? Because it gives us a simpler induction principle. *)
Check le_ind.
(* ===> forall (n : nat) (P : nat -> Prop),
P n ->
(forall m : nat, n <= m -> P m -> P (S m)) ->
forall n0 : nat, n <= n0 -> P n0 *)
(* ################################################################# *)
(** * Formal vs. Informal Proofs by Induction *)
(** Question: What is the relation between a formal proof of a
proposition [P] and an informal proof of the same proposition [P]?
Answer: The latter should _teach_ the reader how to produce the
former.
Question: How much detail is needed??
Unfortunately, there is no single right answer; rather, there is a
range of choices.
At one end of the spectrum, we can essentially give the reader the
whole formal proof (i.e., the "informal" proof will amount to just
transcribing the formal one into words). This may give the reader
the ability to reproduce the formal one for themselves, but it
probably doesn't _teach_ them anything much.
At the other end of the spectrum, we can say "The theorem is true
and you can figure out why for yourself if you think about it hard
enough." This is also not a good teaching strategy, because often
writing the proof requires one or more significant insights into
the thing we're proving, and most readers will give up before they
rediscover all the same insights as we did.
In the middle is the golden mean -- a proof that includes all of
the essential insights (saving the reader the hard work that we
went through to find the proof in the first place) plus high-level
suggestions for the more routine parts to save the reader from
spending too much time reconstructing these (e.g., what the IH says
and what must be shown in each case of an inductive proof), but not
so much detail that the main ideas are obscured.
Since we've spent much of this chapter looking "under the hood" at
formal proofs by induction, now is a good moment to talk a little
about _informal_ proofs by induction.
In the real world of mathematical communication, written proofs
range from extremely longwinded and pedantic to extremely brief and
telegraphic. Although the ideal is somewhere in between, while one
is getting used to the style it is better to start out at the
pedantic end. Also, during the learning phase, it is probably
helpful to have a clear standard to compare against. With this in
mind, we offer two templates -- one for proofs by induction over
_data_ (i.e., where the thing we're doing induction on lives in
[Type]) and one for proofs by induction over _evidence_ (i.e.,
where the inductively defined thing lives in [Prop]). *)
(* ================================================================= *)
(** ** Induction Over an Inductively Defined Set *)
(** _Template_:
- _Theorem_: <Universally quantified proposition of the form
"For all [n:S], [P(n)]," where [S] is some inductively defined
set.>
_Proof_: By induction on [n].
<one case for each constructor [c] of [S]...>
- Suppose [n = c a1 ... ak], where <...and here we state
the IH for each of the [a]'s that has type [S], if any>.
We must show <...and here we restate [P(c a1 ... ak)]>.
<go on and prove [P(n)] to finish the case...>
- <other cases similarly...> []
_Example_:
- _Theorem_: For all sets [X], lists [l : list X], and numbers
[n], if [length l = n] then [index (S n) l = None].
_Proof_: By induction on [l].
- Suppose [l = []]. We must show, for all numbers [n],
that, if [length [] = n], then [index (S n) [] =
None].
This follows immediately from the definition of [index].
- Suppose [l = x :: l'] for some [x] and [l'], where
[length l' = n'] implies [index (S n') l' = None], for
any number [n']. We must show, for all [n], that, if
[length (x::l') = n] then [index (S n) (x::l') =
None].
Let [n] be a number with [length l = n]. Since
length l = length (x::l') = S (length l'),
it suffices to show that
index (S (length l')) l' = None.
But this follows directly from the induction hypothesis,
picking [n'] to be [length l']. [] *)
(* ================================================================= *)
(** ** Induction Over an Inductively Defined Proposition *)
(** Since inductively defined proof objects are often called
"derivation trees," this form of proof is also known as _induction
on derivations_.
_Template_:
- _Theorem_: <Proposition of the form "[Q -> P]," where [Q] is
some inductively defined proposition (more generally,
"For all [x] [y] [z], [Q x y z -> P x y z]")>
_Proof_: By induction on a derivation of [Q]. <Or, more
generally, "Suppose we are given [x], [y], and [z]. We
show that [Q x y z] implies [P x y z], by induction on a
derivation of [Q x y z]"...>
<one case for each constructor [c] of [Q]...>
- Suppose the final rule used to show [Q] is [c]. Then
<...and here we state the types of all of the [a]'s
together with any equalities that follow from the
definition of the constructor and the IH for each of
the [a]'s that has type [Q], if there are any>. We must
show <...and here we restate [P]>.
<go on and prove [P] to finish the case...>
- <other cases similarly...> []
_Example_
- _Theorem_: The [<=] relation is transitive -- i.e., for all
numbers [n], [m], and [o], if [n <= m] and [m <= o], then
[n <= o].
_Proof_: By induction on a derivation of [m <= o].
- Suppose the final rule used to show [m <= o] is
[le_n]. Then [m = o] and we must show that [n <= m],
which is immediate by hypothesis.
- Suppose the final rule used to show [m <= o] is
[le_S]. Then [o = S o'] for some [o'] with [m <= o'].
We must show that [n <= S o'].
By induction hypothesis, [n <= o'].
But then, by [le_S], [n <= S o']. [] *)
(** $Date: 2016-05-26 16:17:19 -0400 (Thu, 26 May 2016) $ *)
|
////////////////////////////////////////////////////////////////////////////////
// //
// Copyright 2006, 2007 Dennis van Weeren //
// //
// This file is part of Minimig //
// //
// Minimig is free software; you can redistribute it and/or modify //
// it under the terms of the GNU General Public License as published by //
// the Free Software Foundation; either version 3 of the License, or //
// (at your option) any later version. //
// //
// Minimig is distributed in the hope that it will be useful, //
// but WITHOUT ANY WARRANTY; without even the implied warranty of //
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the //
// GNU General Public License for more details. //
// //
// You should have received a copy of the GNU General Public License //
// along with this program. If not, see <http://www.gnu.org/licenses/>. //
// //
////////////////////////////////////////////////////////////////////////////////
// //
// This is Amber //
// Amber is a scandoubler to allow connection to a VGA monitor. //
// In addition, it can overlay an OSD (on-screen-display) menu. //
// Amber also has a pass-through mode in which //
// the video output can be connected to an RGB SCART input. //
// The meaning of _hsync_out and _vsync_out is then: //
// _vsync_out is fixed high (for use as RGB enable on SCART input). //
// _hsync_out is composite sync output. //
// //
////////////////////////////////////////////////////////////////////////////////
// //
// Changelog //
// DW: //
// 2006-01-10 - first serious version //
// 2006-01-11 - done lot's of work, Amber is now finished //
// 2006-12-29 - added support for OSD overlay //
// //
// JB: //
// 2008-02-26 - synchronous 28 MHz version //
// 2008-02-28 - horizontal and vertical interpolation //
// 2008-02-02 - hfilter/vfilter inputs added, unused inputs removed //
// 2008-12-12 - useless scanline effect implemented //
// 2008-12-27 - clean-up //
// 2009-05-24 - clean-up & renaming //
// 2009-08-31 - scanlines synthesis option //
// 2010-05-30 - htotal changed //
// //
// RK: //
// 2013-03-03 - cleanup //
// //
////////////////////////////////////////////////////////////////////////////////
module amber
(
input wire clk, // 28MHz clock
// config
input wire dblscan, // enable VGA output (enable scandoubler)
input wire varbeamen, // variable beam enabled
input wire [ 2-1:0] lr_filter, // interpolation filter settings for low resolution
input wire [ 2-1:0] hr_filter, // interpolation filter settings for high resolution
input wire [ 2-1:0] scanline, // scanline effect enable
input wire [ 2-1:0] dither, // dither enable (00 = off, 01 = temporal, 10 = random, 11 = temporal + random)
// control
input wire [ 9-1:0] htotal, // video line length
input wire hires, // display is in hires mode (from bplcon0)
// osd
input wire osd_blank, // OSD overlay enable (blank normal video)
input wire osd_pixel, // OSD pixel(video) data
// input
input wire [ 8-1:0] red_in, // red componenent video in
input wire [ 8-1:0] green_in, // green component video in
input wire [ 8-1:0] blue_in, // blue component video in
input wire _hsync_in, // horizontal synchronisation in
input wire _vsync_in, // vertical synchronisation in
input wire _csync_in, // composite synchronization in
// output
output reg [ 8-1:0] red_out=0, // red componenent video out
output reg [ 8-1:0] green_out=0, // green component video out
output reg [ 8-1:0] blue_out=0, // blue component video out
output reg _hsync_out=0, // horizontal synchronisation out
output reg _vsync_out=0 // vertical synchronisation out
);
//// params ////
localparam [ 8-1:0] OSD_R = 8'b11110000;
localparam [ 8-1:0] OSD_G = 8'b11110000;
localparam [ 8-1:0] OSD_B = 8'b11110000;
//// control ////
reg _hsync_in_del=0; // delayed horizontal synchronisation input
reg hss=0; // horizontal sync start
reg _vsync_in_del=0; // delayed vertical synchronisation input
reg vss=0; // vertical sync start
// horizontal sync start (falling edge detection)
always @ (posedge clk) begin
_hsync_in_del <= #1 _hsync_in;
hss <= #1 ~_hsync_in & _hsync_in_del;
_vsync_in_del <= #1 _vsync_in;
vss <= #1 ~_vsync_in & _vsync_in_del;
end
//// horizontal interpolation ////
reg hi_en=0; // horizontal interpolation enable
reg [ 8-1:0] r_in_d=0; // pixel data delayed by 70ns for horizontal interpolation
reg [ 8-1:0] g_in_d=0; // pixel data delayed by 70ns for horizontal interpolation
reg [ 8-1:0] b_in_d=0; // pixel data delayed by 70ns for horizontal interpolation
wire [ 9-1:0] hi_r; // horizontal interpolation output
wire [ 9-1:0] hi_g; // horizontal interpolation output
wire [ 9-1:0] hi_b; // horizontal interpolation output
reg [ 11-1:0] sd_lbuf_wr=0; // line buffer write pointer
// horizontal interpolation enable
always @ (posedge clk) begin
`ifdef MINIMIG_VIDEO_FILTER
if (hss) hi_en <= #1 hires ? hr_filter[0] : lr_filter[0];
`else
hi_en <= #1 1'b0;
`endif
end
// pixel data delayed by one hires pixel for horizontal interpolation
always @ (posedge clk) begin
if (sd_lbuf_wr[0]) begin // sampled at 14MHz (hires clock rate)
r_in_d <= red_in;
g_in_d <= green_in;
b_in_d <= blue_in;
end
end
// interpolate & mux
assign hi_r = hi_en ? ({1'b0, red_in} + {1'b0, r_in_d}) : {red_in[7:0] , 1'b0};
assign hi_g = hi_en ? ({1'b0, green_in} + {1'b0, g_in_d}) : {green_in[7:0], 1'b0};
assign hi_b = hi_en ? ({1'b0, blue_in} + {1'b0, b_in_d}) : {blue_in[7:0] , 1'b0};
//// scandoubler ////
reg [ 30-1:0] sd_lbuf [0:1024-1]; // line buffer for scan doubling (there are 908/910 hires pixels in every line)
reg [ 30-1:0] sd_lbuf_o=0; // line buffer output register
reg [ 30-1:0] sd_lbuf_o_d=0; // compensantion for one clock delay of the second line buffer
reg [ 11-1:0] sd_lbuf_rd=0; // line buffer read pointer
// scandoubler line buffer write pointer
always @ (posedge clk) begin
if (hss || !dblscan)
sd_lbuf_wr <= #1 11'd0;
else
sd_lbuf_wr <= #1 sd_lbuf_wr + 11'd1;
end
// scandoubler line buffer read pointer
always @ (posedge clk) begin
if (hss || !dblscan || (sd_lbuf_rd == {htotal[8:1],2'b11})) // reset at horizontal sync start and end of scandoubled line
sd_lbuf_rd <= #1 11'd0;
else
sd_lbuf_rd <= #1 sd_lbuf_rd + 11'd1;
end
// scandoubler line buffer write/read
always @ (posedge clk) begin
if (dblscan) begin
// write
sd_lbuf[sd_lbuf_wr[10:1]] <= #1 {_hsync_in, osd_blank, osd_pixel, hi_r, hi_g, hi_b};
// read
sd_lbuf_o <= #1 sd_lbuf[sd_lbuf_rd[9:0]];
// delayed data
sd_lbuf_o_d <= #1 sd_lbuf_o;
end
end
//// vertical interpolation ////
reg vi_en=0; // vertical interpolation enable
reg [ 30-1:0] vi_lbuf [0:1024-1]; // vertical interpolation line buffer
reg [ 30-1:0] vi_lbuf_o=0; // vertical interpolation line buffer output register
wire [ 10-1:0] vi_r_tmp; // vertical interpolation temp data
wire [ 10-1:0] vi_g_tmp; // vertical interpolation temp data
wire [ 10-1:0] vi_b_tmp; // vertical interpolation temp data
wire [ 8-1:0] vi_r; // vertical interpolation outputs
wire [ 8-1:0] vi_g; // vertical interpolation outputs
wire [ 8-1:0] vi_b; // vertical interpolation outputs
//vertical interpolation enable
always @ (posedge clk) begin
`ifdef MINIMIG_VIDEO_FILTER
if (hss) vi_en <= #1 hires ? hr_filter[1] : lr_filter[1];
`else
vi_en <= #1 1'b0;
`endif
end
// vertical interpolation line buffer write/read
always @ (posedge clk) begin
// write
vi_lbuf[sd_lbuf_rd[9:0]] <= #1 sd_lbuf_o;
// read
vi_lbuf_o <= #1 vi_lbuf[sd_lbuf_rd[9:0]];
end
// interpolate & mux
assign vi_r_tmp = vi_en ? ({1'b0, sd_lbuf_o_d[26:18]} + {1'b0, vi_lbuf_o[26:18]}) : {sd_lbuf_o_d[26:18], 1'b0};
assign vi_g_tmp = vi_en ? ({1'b0, sd_lbuf_o_d[17:09]} + {1'b0, vi_lbuf_o[17:09]}) : {sd_lbuf_o_d[17:09], 1'b0};
assign vi_b_tmp = vi_en ? ({1'b0, sd_lbuf_o_d[ 8: 0]} + {1'b0, vi_lbuf_o[ 8: 0]}) : {sd_lbuf_o_d[ 8: 0], 1'b0};
// cut unneeded bits
assign vi_r = vi_r_tmp[8+2-1:2];
assign vi_g = vi_g_tmp[8+2-1:2];
assign vi_b = vi_b_tmp[8+2-1:2];
//// dither ////
reg [24-1:0] seed=0;
reg [24-1:0] randval=0;
reg [24-1:0] seed_old=0;
wire [26-1:0] hpf_sum;
reg f_cnt=0;
reg h_cnt=0;
reg v_cnt=0;
wire [ 8-1:0] r_dither_err;
wire [ 8-1:0] g_dither_err;
wire [ 8-1:0] b_dither_err;
reg [ 8-1:0] r_err=0;
reg [ 8-1:0] g_err=0;
reg [ 8-1:0] b_err=0;
wire [ 8-1:0] r_dither_tsp;
wire [ 8-1:0] g_dither_tsp;
wire [ 8-1:0] b_dither_tsp;
wire [ 8-1:0] r_dither_rnd;
wire [ 8-1:0] g_dither_rnd;
wire [ 8-1:0] b_dither_rnd;
wire [ 8-1:0] dither_r;
wire [ 8-1:0] dither_g;
wire [ 8-1:0] dither_b;
// pseudo random number generator
always @ (posedge clk) begin
if (vss) begin
seed <= #1 24'h654321;
seed_old <= #1 24'd0;
randval <= #1 24'd0;
end else if (|dither) begin
seed <= #1 {seed[22:0], ~(seed[23] ^ seed[22] ^ seed[21] ^ seed[16])};
seed_old <= #1 seed;
randval <= #1 hpf_sum[25:2];
end
end
assign hpf_sum = {2'b00,randval} + {2'b00, seed} - {2'b00, seed_old};
// horizontal / vertical / frame marker
always @ (posedge clk) begin
if (vss) begin
f_cnt <= #1 ~f_cnt;
v_cnt <= #1 1'b0;
h_cnt <= #1 1'b0;
end else if (|dither) begin
if (sd_lbuf_rd == {htotal[8:1],2'b11}) v_cnt <= #1 ~v_cnt;
h_cnt <= #1 ~h_cnt;
end
end
// dither add previous error / 2
assign r_dither_err = &vi_r[7:2] ? vi_r[7:0] : vi_r[7:0] + {6'b000000, r_err[1:0]};
assign g_dither_err = &vi_g[7:2] ? vi_g[7:0] : vi_g[7:0] + {6'b000000, g_err[1:0]};
assign b_dither_err = &vi_b[7:2] ? vi_b[7:0] : vi_b[7:0] + {6'b000000, b_err[1:0]};
// temporal/spatial dithering
assign r_dither_tsp = &r_dither_err[7:2] ? r_dither_err[7:0] : r_dither_err[7:0] + {6'b000000, (dither[0] & (f_cnt ^ v_cnt ^ h_cnt) & r_dither_err[1]), 1'b0};
assign g_dither_tsp = &g_dither_err[7:2] ? g_dither_err[7:0] : g_dither_err[7:0] + {6'b000000, (dither[0] & (f_cnt ^ v_cnt ^ h_cnt) & g_dither_err[1]), 1'b0};
assign b_dither_tsp = &b_dither_err[7:2] ? b_dither_err[7:0] : b_dither_err[7:0] + {6'b000000, (dither[0] & (f_cnt ^ v_cnt ^ h_cnt) & b_dither_err[1]), 1'b0};
// random dithering
assign r_dither_rnd = &r_dither_tsp[7:2] ? r_dither_tsp[7:0] : r_dither_tsp[7:0] + {7'b0000000, dither[1] & randval[0]};
assign g_dither_rnd = &g_dither_tsp[7:2] ? g_dither_tsp[7:0] : g_dither_tsp[7:0] + {7'b0000000, dither[1] & randval[0]};
assign b_dither_rnd = &b_dither_tsp[7:2] ? b_dither_tsp[7:0] : b_dither_tsp[7:0] + {7'b0000000, dither[1] & randval[0]};
// dither error
always @ (posedge clk) begin
if (vss) begin
r_err <= #1 8'd0;
g_err <= #1 8'd0;
b_err <= #1 8'd0;
end else if (|dither) begin
r_err <= #1 {6'b000000, r_dither_rnd[1:0]};
g_err <= #1 {6'b000000, g_dither_rnd[1:0]};
b_err <= #1 {6'b000000, b_dither_rnd[1:0]};
end
end
assign dither_r = r_dither_rnd;
assign dither_g = g_dither_rnd;
assign dither_b = b_dither_rnd;
//// scanlines ////
reg sl_en=0; // scanline enable
reg [ 8-1:0] sl_r=0; // scanline data output
reg [ 8-1:0] sl_g=0; // scanline data output
reg [ 8-1:0] sl_b=0; // scanline data output
reg [ 8-1:0] ns_r;
reg [ 8-1:0] ns_g;
reg [ 8-1:0] ns_b;
reg ns_csync;
reg ns_osd_blank;
reg ns_osd_pixel;
// scanline enable
always @ (posedge clk) begin
if (hss) // reset at horizontal sync start
sl_en <= #1 1'b0;
else if (sd_lbuf_rd == {htotal[8:1],2'b11}) // set at end of scandoubled line
sl_en <= #1 1'b1;
end
// scanlines for scandoubled lines
always @ (posedge clk) begin
sl_r <= #1 ((sl_en && scanline[1]) ? 8'h00 : ((sl_en && scanline[0]) ? {1'b0, dither_r[7:1]} : dither_r));
sl_g <= #1 ((sl_en && scanline[1]) ? 8'h00 : ((sl_en && scanline[0]) ? {1'b0, dither_g[7:1]} : dither_g));
sl_b <= #1 ((sl_en && scanline[1]) ? 8'h00 : ((sl_en && scanline[0]) ? {1'b0, dither_b[7:1]} : dither_b));
end
// scanlines for non-scandoubled lines
always @ (posedge clk) begin
ns_r <= #1 ((!dblscan && f_cnt && scanline[1]) ? 8'h00 : ((!dblscan && f_cnt && scanline[0]) ? {1'b0, red_in[7:1]} : red_in));
ns_g <= #1 ((!dblscan && f_cnt && scanline[1]) ? 8'h00 : ((!dblscan && f_cnt && scanline[0]) ? {1'b0, green_in[7:1]} : green_in));
ns_b <= #1 ((!dblscan && f_cnt && scanline[1]) ? 8'h00 : ((!dblscan && f_cnt && scanline[0]) ? {1'b0, blue_in[7:1]} : blue_in));
ns_csync <= #1 _csync_in;
ns_osd_blank <= #1 osd_blank;
ns_osd_pixel <= #1 osd_pixel;
end
//// bypass mux ////
wire bm_hsync;
wire bm_vsync;
wire [ 8-1:0] bm_r;
wire [ 8-1:0] bm_g;
wire [ 8-1:0] bm_b;
wire bm_osd_blank;
wire bm_osd_pixel;
assign bm_hsync = dblscan ? sd_lbuf_o_d[29] : varbeamen ? _hsync_in : ns_csync;
assign bm_vsync = dblscan ? _vsync_in : varbeamen ? _vsync_in : 1'b1;
assign bm_r = dblscan ? sl_r : varbeamen ? red_in : ns_r;
assign bm_g = dblscan ? sl_g : varbeamen ? green_in : ns_g;
assign bm_b = dblscan ? sl_b : varbeamen ? blue_in : ns_b;
assign bm_osd_blank = dblscan ? sd_lbuf_o_d[28] : varbeamen ? osd_blank : ns_osd_blank;
assign bm_osd_pixel = dblscan ? sd_lbuf_o_d[27] : varbeamen ? osd_pixel : ns_osd_pixel;
//// osd ////
wire [ 8-1:0] osd_r;
wire [ 8-1:0] osd_g;
wire [ 8-1:0] osd_b;
assign osd_r = (bm_osd_blank ? (bm_osd_pixel ? OSD_R : {2'b00, bm_r[7:2]}) : bm_r);
assign osd_g = (bm_osd_blank ? (bm_osd_pixel ? OSD_G : {2'b00, bm_g[7:2]}) : bm_g);
assign osd_b = (bm_osd_blank ? (bm_osd_pixel ? OSD_B : {2'b10, bm_b[7:2]}) : bm_b);
//// output registers ////
always @ (posedge clk) begin
_hsync_out <= #1 bm_hsync;
_vsync_out <= #1 bm_vsync;
red_out <= #1 osd_r;
green_out <= #1 osd_g;
blue_out <= #1 osd_b;
end
endmodule
|
`timescale 1 ps / 1 ps
module pcie_mem_alloc
#(parameter REVISION=1)
(
input ACLK,
input Axi_resetn,
input [31:0] stats0_data,
input [31:0] stats1_data,
input [31:0] stats2_data,
input [31:0] stats3_data,
//signals from and to pcie_bridge
//address write
input [31: 0] pcie_axi_AWADDR,
input pcie_axi_AWVALID,
output pcie_axi_AWREADY,
//data write
input [31: 0] pcie_axi_WDATA,
input [3: 0] pcie_axi_WSTRB,
input pcie_axi_WVALID,
output pcie_axi_WREADY,
//write response (handhake)
output [1:0] pcie_axi_BRESP,
output pcie_axi_BVALID,
input pcie_axi_BREADY,
//address read
input [31: 0] pcie_axi_ARADDR,
input pcie_axi_ARVALID,
output pcie_axi_ARREADY,
//data read
output [31: 0] pcie_axi_RDATA,
output [1:0] pcie_axi_RRESP,
output pcie_axi_RVALID,
input pcie_axi_RREADY,
input pcieClk,
input pcie_user_lnk_up,
//signals from and to mcd_pipeline
input [31:0] memcached2memAllocation_data, // Address reclamation
input memcached2memAllocation_valid,
output memcached2memAllocation_ready,
output[31:0] memAllocation2memcached_dram_data, // Address assignment for DRAM
output memAllocation2memcached_dram_valid,
input memAllocation2memcached_dram_ready,
output[31:0] memAllocation2memcached_flash_data, // Address assignment for SSD
output memAllocation2memcached_flash_valid,
input memAllocation2memcached_flash_ready,
input flushReq,
output flushAck,
input flushDone
);
wire [31:0] free1_pcie;
wire free1_wr_pcie;
wire free1_full_pcie;
wire [31:0] free2_pcie;
wire free2_wr_pcie;
wire free2_full_pcie;
wire [31:0] free3_pcie;
wire free3_wr_pcie;
wire free3_full_pcie;
wire [31:0] free4_pcie;
wire free4_wr_pcie;
wire free4_full_pcie;
wire [31:0] del1_pcie;
wire del1_rd_pcie;
wire del1_ety_pcie;
//asynchronous fifos to get the memory management signals out/in
//free1 from pcie to memcached
wire free1_fifo_ety;
assign memAllocation2memcached_dram_valid=~free1_fifo_ety;
wire pipereset;
assign pipereset=~Axi_resetn|flushReq;
memMgmt_async_fifo free1_fifo (
.rst(pipereset), // input wire rst
.wr_clk(pcieClk), // input wire wr_clk
.rd_clk(ACLK), // input wire rd_clk
.din(free1_pcie), // input wire [31 : 0] din
.wr_en(free1_wr_pcie), // input wire wr_en
.rd_en(memAllocation2memcached_dram_ready), // input wire rd_en
.dout(memAllocation2memcached_dram_data), // output wire [31 : 0] dout
.full(free1_full_pcie), // output wire full
.empty(free1_fifo_ety) // output wire empty
);
//free2 from pcie to memcached
wire free2_fifo_ety;
assign memAllocation2memcached_flash_valid=~free2_fifo_ety;
memMgmt_async_fifo free2_fifo (
.rst(pipereset), // input wire rst
.wr_clk(pcieClk), // input wire wr_clk
.rd_clk(ACLK), // input wire rd_clk
.din(free2_pcie), // input wire [31 : 0] din
.wr_en(free2_wr_pcie), // input wire wr_en
.rd_en(memAllocation2memcached_flash_ready), // input wire rd_en
.dout(memAllocation2memcached_flash_data), // output wire [31 : 0] dout
.full(free2_full_pcie), // output wire full
.empty(free2_fifo_ety) // output wire empty
);
//free3 and free4 unconnected so far!
//del_fifo: from memcached to pcie
wire del1_fifo_full;
assign memcached2memAllocation_ready=~del1_fifo_full;
memMgmt_async_fifo del_fifo (
.rst(pipereset), // input wire rst
.wr_clk(ACLK), // input wire wr_clk
.rd_clk(pcieClk), // input wire rd_clk
.din(memcached2memAllocation_data), // input wire [31 : 0] din
.wr_en(memcached2memAllocation_valid), // input wire wr_en
.rd_en(del1_rd_pcie), // input wire rd_en
.dout(del1_pcie), // output wire [31 : 0] dout
.full(del1_fifo_full), // output wire full
.empty(del1_ety_pcie) // output wire empty
);
//CDC for flush protocol
wire P_flushack,P_flushreq,P_flushdone; //pcie clock domain
wire A_flushack, A_flushackn, A_flushreq, A_flushdone; //memcached axi clock domain
localparam STATS_WIDTH=32;
wire [STATS_WIDTH-1:0] P_stats0,P_stats1,P_stats2,P_stats3;
//CDC registers for memcached -> pcie. ASYNC_REG attribute not strictly necessary
(* ASYNC_REG="TRUE"*) reg flushreqR, flushreqR2;
(* ASYNC_REG="TRUE"*) reg flushdoneR,flushdoneR2;
(* ASYNC_REG="TRUE"*) reg [STATS_WIDTH-1:0] stats0R,stats0R2;
(* ASYNC_REG="TRUE"*) reg [STATS_WIDTH-1:0] stats1R,stats1R2;
(* ASYNC_REG="TRUE"*) reg [STATS_WIDTH-1:0] stats2R,stats2R2;
(* ASYNC_REG="TRUE"*) reg [STATS_WIDTH-1:0] stats3R,stats3R2;
assign A_flushreq=flushReq;
assign A_flushdone=flushDone;
assign flushAck=A_flushack;
assign A_flushack=~A_flushackn;
//flushack has to be crossed using a fifo because it is a one cycle high signal
singleSignalCDC flushAckCrosser (
.wr_clk(pcieClk), // input wire wr_clk
.rd_clk(ACLK), // input wire rd_clk
.din(1'b0), // input wire [0 : 0] din
.wr_en(P_flushack), // input wire wr_en
.rd_en(1'b1), // input wire rd_en
.dout(), // output wire [0 : 0] dout
.full(), // output wire full
.empty(A_flushackn) // output wire empty
);
always @(posedge pcieClk) begin //(posedge ACLK) begin
flushreqR<=A_flushreq;
flushreqR2<=flushreqR;
flushdoneR<=A_flushdone;
flushdoneR2<=flushdoneR;
end
assign P_flushreq = flushreqR2;
assign P_flushdone = flushdoneR2;
//CDC for stats
always@(posedge pcieClk) begin
//vectors shouldnt be crossed like this, but it's only stats, occasional errors acceptable.
stats0R <=stats0_data;
stats0R2<=stats0R;
stats1R <=stats1_data;
stats1R2<=stats1R;
stats2R <=stats2_data;
stats2R2<=stats2R;
stats3R <=stats3_data;
stats3R2<=stats3R;
end
assign P_stats0=stats0R2;
assign P_stats1=stats1R2;
assign P_stats2=stats2R2;
assign P_stats3=stats3R2;
/* mylittleila axiSide (
.clk(ACLK), // input wire clk
.probe0(A_flushreq), // input wire [0 : 0] probe0
.probe1(A_flushack), // input wire [0 : 0] probe1
.probe2(A_flushdone) // input wire [0 : 0] probe2
);
mylittleila pcieside (
.clk(pcieClk), // input wire clk
.probe0(P_flushreq), // input wire [0 : 0] probe0
.probe1(P_flushack), // input wire [0 : 0] probe1
.probe2(P_flushdone) // input wire [0 : 0] probe2
);*/
stats_to_axi #(.REVISION(REVISION)) stats_to_axi_i
(.ACLK(pcieClk),
.ARESETN(pcie_user_lnk_up),
.ARADDR(pcie_axi_ARADDR),
.ARREADY(pcie_axi_ARREADY),
.ARVALID(pcie_axi_ARVALID),
.AWADDR(pcie_axi_AWADDR),
.AWREADY(pcie_axi_AWREADY),
.AWVALID(pcie_axi_AWVALID),
.RDATA(pcie_axi_RDATA),
.RREADY(pcie_axi_RREADY),
.RRESP(pcie_axi_RRESP),
.RVALID(pcie_axi_RVALID),
.WDATA(pcie_axi_WDATA),
.WREADY(pcie_axi_WREADY),
.WSTRB(pcie_axi_WSTRB),
.WVALID(pcie_axi_WVALID),
.BREADY(pcie_axi_BREADY),
.BRESP(pcie_axi_BRESP),
.BVALID(pcie_axi_BVALID),
//the stats
.stats0_in(stats0_data),
.stats1_in(stats1_data),
.stats2_in(stats2_data),
.stats3_in(stats3_data),
//memory management s
.free1(free1_pcie),
.free1_wr(free1_wr_pcie),
.free1_full(free1_full_pcie),
.free2(free2_pcie),
.free2_wr(free2_wr_pcie),
.free2_full(free2_full_pcie),
.free3(free3_pcie),
.free3_wr(free3_wr_pcie),
.free3_full(free3_full_pcie),
.icap(),
.icap_wr(),
.icap_full(),
.del1(del1_pcie),
.del1_rd(del1_rd_pcie),
.del1_ety(del1_ety_pcie),
.flushreq(P_flushreq),
.flushack(P_flushack),
.flushdone(P_flushdone),
.SC_reset()//software controlled reset, one cycle high. TODO: transform into multicycle high, CDC, expose to top
);
endmodule
|
/*
Instruction Word
15: 0, First Word
31:16, Second Word
*/
module DecOp(
clk,
istrWord,
regCurSr,
idRegD,
idRegS,
idRegT,
idImm,
idStepPc,
idUopPc,
idUopWord
);
input clk; //clock
input[31:0] istrWord; //source instruction word
input[31:0] regCurSr; //current SR
output[6:0] idRegD;
output[6:0] idRegS;
output[6:0] idRegT;
output[31:0] idImm;
output[3:0] idStepPc;
output[11:0] idUopPc;
output[31:0] idUopWord;
reg[11:0] uopPcIdx[256];
reg[31:0] uopPgm[4096];
reg[7:0] uopUseIdx;
reg srIsDq;
initial begin
$readmemh("uopidx.txt", uopPcIdx);
$readmemh("uoppgm.txt", uopPgm);
end
reg opIs32p;
reg op2Is32p;
reg[6:0] tIdRegD;
reg[6:0] tIdRegS;
reg[6:0] tIdRegT;
reg[31:0] tIdImm;
reg[3:0] tIdStepPc;
assign idStepPc = tIdStepPc;
reg[15:0] tInstWord1;
reg[15:0] tInstWord2;
reg[7:0] tInstPfxOp;
reg opIs8Ep;
always @ (clk)
begin
opIs32p =
((istrWord[15:12]==0) && (istrWord[3:1]==0)) ||
((istrWord[15:12]==3) && ((istrWord[3:0]==1) || (istrWord[3:0]==9))) ||
((istrWord[15:12]==15) && (istrWord[3:0]==15)) ||
((istrWord[15:12]==8)&& ((istrWord[3:0]==10) ||
(istrWord[3:0]==12) || (istrWord[3:0]==14))) ;
if(istrWord[15:8]==8'h8E)
begin
tInstWord1=istrWord[31:16];
tInstPfxOp=istrWord[ 7: 0];
opIs8Ep=1;
end
else
begin
tInstWord1=istrWord[15:0];
tInstPfxOp=0;
opIs8Ep=0;
end
if(opIs32p)
tInstWord2=istrWord[47:32];
else
tInstWord2=istrWord[31:16];
op2Is32p =
((tInstWord2[15:12]==0) && (tInstWord2[3:1]==0)) ||
((tInstWord2[15:12]==3) && ((tInstWord2[3:0]==1) ||
(tInstWord2[3:0]==9))) ||
((tInstWord2[15:12]==15) && (tInstWord2[3:0]==15)) ||
((tInstWord2[15:12]==8)&& ((tInstWord2[3:0]==10) ||
(tInstWord2[3:0]==12) || (tInstWord2[3:0]==14))) ;
uopUseIdx=0;
tIdRegD[6:0]=0;
tIdRegS[6:0]=0;
tIdRegT[6:0]=0;
tIdImm[31:0]=32'h0;
tIdStepPc[1:0]=opIs32p ? 2'h2 : 2'h1;
tIdStepPc[3:2]=op2Is32p ? 2'h2 : 2'h1;
// if(istrWord==0)
// tIdStepPc[1:0] = 1;
idUopPc[11:0]=12'h0;
idUopWord[31:0]=32'h0;
// idUopWord[23]=1;
idUopWord[23]=0;
idUopWord[31:24]=UOP_FWOP;
srIsDq = regCurSr[12];
case(tInstWord1[15:12])
4'h0:
begin
// tIdRegD[3:0]=istrWord[7:4];
// tIdRegS[3:0]=istrWord[7:4];
// tIdRegT[3:0]=istrWord[3:0];
case(tInstWord1[3:0])
4'h2:
begin
tIdRegS=REG_CC0;
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[ 7:4];
tIdRegT=REG_ZZR;
idUopWord[31:24]=UOP_MOVI;
end
4'h8:
begin
idUopWord[31:24]=UOP_FWOP;
idUopWord[23:16]=8'b0010_0001;
idUopWord[15: 0]=tInstWord1[15: 0];
end
4'h9:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[11:8];
tIdRegT[3:0]=tInstWord1[11:8];
idUopWord[31:24]=UOP_FWOP;
idUopWord[23:16]=8'b0010_0001;
idUopWord[15: 0]=tInstWord1[15: 0];
end
4'hA:
begin
tIdRegS=REG_CS0;
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[ 7:4];
tIdRegT=REG_ZZR;
idUopWord[31:24]=UOP_MOVI;
end
4'hB:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[11:8];
tIdRegT[3:0]=tInstWord1[11:8];
idUopWord[31:24]=UOP_FWOP;
idUopWord[23:16]=8'b0010_0001;
idUopWord[15: 0]=tInstWord1[15: 0];
end
4'hC:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[ 7:4];
tIdRegT=REG_R0;
idUopWord[31:24]=UOP_MOVLDB;
end
4'hD:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[ 7:4];
tIdRegT=REG_R0;
idUopWord[31:24]=UOP_MOVLDW;
end
4'hE:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[ 7:4];
tIdRegT=REG_R0;
idUopWord[31:24]=UOP_MOVLDI;
end
default:
begin
end
endcase
end
4'h1:
begin
tIdRegD[3:0]=tInstWord1[ 7:4];
tIdRegS[3:0]=tInstWord1[11:8];
tIdRegT=REG_ZZR;
tIdImm[3:0]=tInstWord1[3:0];
idUopWord[31:24]=UOP_MOVSTI;
end
4'h2:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[11:8];
tIdRegT[3:0]=tInstWord1[ 7:4];
case(istrWord[3:0])
4'h0: idUopWord[31:24]=UOP_MOVSTB;
4'h1: idUopWord[31:24]=UOP_MOVSTW;
4'h2: idUopWord[31:24]=UOP_MOVSTI;
4'h8: idUopWord[31:24]=UOP_TESTI;
4'h9: idUopWord[31:24]=UOP_ANDI;
4'hA: idUopWord[31:24]=UOP_XORI;
4'hB: idUopWord[31:24]=UOP_ORI;
default:
begin
end
endcase
end
4'h3:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[11:8];
tIdRegT[3:0]=tInstWord1[ 7:4];
case(istrWord[3:0])
4'h0: idUopWord[31:24]=UOP_CMPEQI;
// 4'h1: idUopWord[31:24]=
4'h2: idUopWord[31:24]=UOP_CMPHSI;
4'h3: idUopWord[31:24]=UOP_CMPGEI;
// 4'h4: idUopWord[31:24]=
// 4'h5: idUopWord[31:24]=
4'h6: idUopWord[31:24]=UOP_CMPHII;
4'h7: idUopWord[31:24]=UOP_CMPGTI;
4'h8: idUopWord[31:24]=UOP_SUBI;
// 4'h9: idUopWord[31:24]=
4'hA: idUopWord[31:24]=UOP_SUBCI;
4'hB: idUopWord[31:24]=UOP_SUBVI;
4'hC: idUopWord[31:24]=UOP_ADDI;
// 4'hD: idUopWord[31:24]=
4'hE: idUopWord[31:24]=UOP_ADDCI;
4'hF: idUopWord[31:24]=UOP_ADDVI;
default:
begin
end
endcase
end
4'h4:
begin
// tIdRegD[3:0]=tInstWord1[11:8];
// tIdRegS[3:0]=tInstWord1[11:8];
// tIdRegT[3:0]=tInstWord1[ 7:4];
case(istrWord[3:0])
4'hA:
begin
tIdRegD=REG_CS0;
tIdRegD[3:0]=tInstWord1[ 7:4];
tIdRegS[3:0]=tInstWord1[11:8];
tIdRegT=REG_ZZR;
idUopWord[31:24]=UOP_MOVI;
end
4'hE:
begin
tIdRegD=REG_CC0;
tIdRegD[3:0]=tInstWord1[ 7:4];
tIdRegS[3:0]=tInstWord1[11:8];
tIdRegT=REG_ZZR;
idUopWord[31:24]=UOP_MOVI;
end
default:
begin
end
endcase
end
4'h5:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[ 7:4];
tIdRegT=REG_ZZR;
tIdImm[3:0]=tInstWord1[3:0];
idUopWord[31:24]=UOP_MOVLDI;
end
4'h6:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[11:8];
tIdRegT[3:0]=tInstWord1[ 7:4];
case(istrWord[3:0])
4'h0: idUopWord[31:24]=UOP_MOVLDB;
4'h1: idUopWord[31:24]=UOP_MOVLDW;
4'h2: idUopWord[31:24]=UOP_MOVLDI;
4'h3:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[ 7:4];
tIdRegT[3:0]=REG_ZZR;
idUopWord[31:24]=UOP_MOVI;
end
4'h7:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[ 7:4];
tIdRegT[3:0]=REG_IMM;
tIdImm[31:0]=32'hFFFF_FFFF;
idUopWord[31:24]=UOP_XOR;
end
4'hA:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=REG_ZZR;
tIdRegT[3:0]=tInstWord1[ 7:4];
idUopWord[31:24]=UOP_SUBI;
end
4'hB:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=REG_ZZR;
tIdRegT[3:0]=tInstWord1[ 7:4];
idUopWord[31:24]=UOP_SUBCI;
end
4'hC:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[ 7:4];
tIdRegT[3:0]=REG_IMM;
tIdImm[31:0]=32'h0000_00FF;
idUopWord[31:24]=UOP_AND;
end
4'hD:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[ 7:4];
tIdRegT[3:0]=REG_IMM;
tIdImm[31:0]=32'h0000_FFFF;
idUopWord[31:24]=UOP_AND;
end
// 4'h4: idUopWord[31:24]=
// 4'h5: idUopWord[31:24]=
// 4'h6: idUopWord[31:24]=
// 4'h7: idUopWord[31:24]=
// 4'h8: idUopWord[31:24]=
// 4'hC: idUopWord[31:24]=UOP_ADDI;
// 4'hE: idUopWord[31:24]=UOP_ADDCI;
// 4'hF: idUopWord[31:24]=
default:
begin
end
endcase
end
4'h7:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS[3:0]=tInstWord1[11:8];
tIdRegT[6:0]=REG_IMM;
// tIdImm[31:8]=tInstWord1[7] ? 24'hFFFFFF : 24'h000000 ;
// tIdImm[ 7:0]=tInstWord1[7:0];
idUopWord[31:24]=UOP_ADDI;
if(opIs8Ep)
begin
tIdImm[31:16]=tInstPfxOp[7] ? 16'hFFFF : 16'h0000 ;
tIdImm[15:8]=tInstPfxOp[7:0];
tIdImm[ 7:0]=tInstWord1[7:0];
end
else
begin
tIdImm[31:8]=tInstWord1[7] ? 24'hFFFFFF : 24'h000000 ;
tIdImm[7:0]=tInstWord1[7:0];
end
end
4'h8:
begin
case(istrWord[11:8])
4'h9: //BT
begin
tIdRegD=REG_ZZR;
tIdRegS=REG_ZZR;
tIdRegT=REG_IMM;
idUopWord[31:24]=UOP_BRTF;
idUopWord[16]=1; //T/F (T)
idUopWord[17]=1; //No DS (DS=False)
if(opIs8Ep)
begin
tIdImm[31:16]=tInstPfxOp[7] ? 16'hFFFF : 16'h0000 ;
tIdImm[15:8]=tInstPfxOp[7:0];
tIdImm[ 7:0]=tInstWord1[7:0];
end
else
begin
tIdImm[31:8]=tInstWord1[7] ? 24'hFFFFFF : 24'h000000 ;
tIdImm[7:0]=tInstWord1[7:0];
end
end
4'hB: //BF
begin
tIdRegD=REG_ZZR;
tIdRegS=REG_ZZR;
tIdRegT=REG_IMM;
idUopWord[31:24]=UOP_BRTF;
idUopWord[16]=0; //T/F (F)
idUopWord[17]=1; //No DS (DS=False)
if(opIs8Ep)
begin
tIdImm[31:16]=tInstPfxOp[7] ? 16'hFFFF : 16'h0000 ;
tIdImm[15:8]=tInstPfxOp[7:0];
tIdImm[ 7:0]=tInstWord1[7:0];
end
else
begin
tIdImm[31:8]=tInstWord1[7] ? 24'hFFFFFF : 24'h000000 ;
tIdImm[7:0]=tInstWord1[7:0];
end
end
4'hD: //BTS
begin
tIdRegD=REG_ZZR;
tIdRegS=REG_ZZR;
tIdRegT=REG_IMM;
idUopWord[31:24]=UOP_BRTF;
idUopWord[16]=1; //T/F (T)
idUopWord[17]=0; //No DS (DS=True)
if(opIs8Ep)
begin
tIdImm[31:16]=tInstPfxOp[7] ? 16'hFFFF : 16'h0000 ;
tIdImm[15:8]=tInstPfxOp[7:0];
tIdImm[ 7:0]=tInstWord1[7:0];
end
else
begin
tIdImm[31:8]=tInstWord1[7] ? 24'hFFFFFF : 24'h000000 ;
tIdImm[7:0]=tInstWord1[7:0];
end
end
4'hF: //BFS
begin
tIdRegD=REG_ZZR;
tIdRegS=REG_ZZR;
tIdRegT=REG_IMM;
idUopWord[31:24]=UOP_BRTF;
idUopWord[16]=0; //T/F (F)
idUopWord[17]=0; //No DS (DS=True)
if(opIs8Ep)
begin
tIdImm[31:16]=tInstPfxOp[7] ? 16'hFFFF : 16'h0000 ;
tIdImm[15:8]=tInstPfxOp[7:0];
tIdImm[ 7:0]=tInstWord1[7:0];
end
else
begin
tIdImm[31:8]=tInstWord1[7] ? 24'hFFFFFF : 24'h000000 ;
tIdImm[7:0]=tInstWord1[7:0];
end
end
default:
begin
end
endcase
end
4'h9:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS=REG_PC4A2;
tIdRegT=REG_ZZR;
tIdImm[7:0]=tInstWord1[7:0];
idUopWord[31:24]=UOP_MOVLDW;
end
4'hA:
begin
tIdRegD=REG_ZZR;
tIdRegS=REG_ZZR;
tIdRegT=REG_IMM;
idUopWord[31:24]=UOP_JMP;
if(opIs8Ep)
begin
tIdImm[31:20]=tInstPfxOp[7] ? 12'hFFF : 12'h000 ;
tIdImm[19:12]=tInstPfxOp[7:0];
tIdImm[11: 0]=tInstWord1[11:0];
end
else
begin
tIdImm[31:12]=tInstWord1[7] ? 20'hFFFFF : 20'h00000 ;
tIdImm[11:0]=tInstWord1[11:0];
end
end
4'hB:
begin
tIdRegD=REG_ZZR;
tIdRegS=REG_ZZR;
tIdRegT=REG_IMM;
idUopWord[31:24]=UOP_JSR;
if(opIs8Ep)
begin
tIdImm[31:20]=tInstPfxOp[7] ? 12'hFFF : 12'h000 ;
tIdImm[19:12]=tInstPfxOp[7:0];
tIdImm[11: 0]=tInstWord1[11:0];
end
else
begin
tIdImm[31:12]=tInstWord1[7] ? 20'hFFFFF : 20'h00000 ;
tIdImm[11:0]=tInstWord1[11:0];
end
end
4'hC:
begin
case(tInstWord1[11:8])
default:
begin
end
endcase
end
4'hD:
begin
tIdRegD[3:0]=tInstWord1[11:8];
tIdRegS=REG_PC4A4;
tIdRegT=REG_ZZR;
tIdImm[7:0]=tInstWord1[7:0];
idUopWord[31:24]=UOP_MOVLDI;
end
4'hE:
begin
tIdRegD[3:0]=tInstWord1[11:8];
// tIdRegS=REG_IMM;
tIdRegS=REG_ZZR;
tIdRegT=REG_IMM;
// tIdImm[31:8]=tInstWord1[7] ? 24'hFFFFFF : 24'h000000 ;
// tIdImm[ 7:0]=tInstWord1[7:0];
// idUopWord[31:24]=UOP_MOVI;
idUopWord[31:24]=UOP_ADDI;
if(opIs8Ep)
begin
tIdImm[31:16]=tInstPfxOp[7] ? 16'hFFFF : 16'h0000 ;
tIdImm[15:8]=tInstPfxOp[7:0];
tIdImm[ 7:0]=tInstWord1[7:0];
end
else
begin
tIdImm[31:8]=tInstWord1[7] ? 24'hFFFFFF : 24'h000000 ;
tIdImm[7:0]=tInstWord1[7:0];
end
end
default:
begin
tIdRegD[6:0]=7'h7F;
tIdRegS[6:0]=7'h7F;
tIdRegT[6:0]=7'h7F;
tIdImm[31:0]=32'h0;
idStepPc=2'h1;
end
endcase
if(uopUseIdx!=0)
begin
idUopPc=uopPcIdx[uopUseIdx];
idUopWord=uopPgm[idUopPc];
end
idRegD=tIdRegD ^
((regCurSr[29] && (tIdRegD[6:3]==4'h0)) ? 7'h40 : 7'h00);
idRegS=tIdRegS ^
((regCurSr[29] && (tIdRegS[6:3]==4'h0)) ? 7'h40 : 7'h00);
idRegT=tIdRegT ^
((regCurSr[29] && (tIdRegT[6:3]==4'h0)) ? 7'h40 : 7'h00);
idImm=tIdImm;
// idRegD=tIdRegD;
// idRegS=tIdRegS;
// idRegT=tIdRegT;
end
endmodule |
`timescale 1ns / 1ps
module AM_ctl # (
parameter integer C_IMG_WW = 12,
parameter integer C_IMG_HW = 12,
parameter integer C_STEP_NUMBER_WIDTH = 32,
parameter integer C_SPEED_DATA_WIDTH = 32,
parameter integer C_L2R = 1
) (
input wire clk,
input wire resetn,
output reg exe_done,
input wire req_ecf,
input wire req_abs,
input wire req_dep_img,
input wire [C_IMG_HW-1:0] req_img_dst,
input wire [C_IMG_HW-1:0] req_img_tol,
input wire [C_SPEED_DATA_WIDTH-1:0] req_speed,
input wire signed [C_STEP_NUMBER_WIDTH-1:0] req_step,
input wire img_pulse,
input wire img_l_valid,
input wire img_r_valid,
input wire img_lo_valid,
input wire [C_IMG_HW-1:0] img_lo_y ,
input wire img_ro_valid,
input wire [C_IMG_HW-1:0] img_ro_y ,
input wire img_li_valid,
input wire [C_IMG_HW-1:0] img_li_y ,
input wire img_ri_valid,
input wire [C_IMG_HW-1:0] img_ri_y ,
output wire m_sel ,
input wire m_ntsign ,
input wire m_zpsign ,
input wire m_ptsign ,
input wire m_state ,
input wire signed [C_STEP_NUMBER_WIDTH-1:0] m_position,
output reg m_start ,
output wire m_stop ,
output reg [C_SPEED_DATA_WIDTH-1:0] m_speed ,
output reg signed [C_STEP_NUMBER_WIDTH-1:0] m_step ,
output reg m_abs ,
output wire m_mod_remain,
output wire signed [C_STEP_NUMBER_WIDTH-1:0] m_new_remain,
input wire m_dep_state,
//output reg rd_en,
output reg [C_IMG_HW-1:0] rd_addr,
input wire [C_STEP_NUMBER_WIDTH-1:0] rd_data,
output reg [31:0] test1,
output reg [31:0] test2,
output reg [31:0] test3,
output reg [31:0] test4
);
//////////////////////////////// delay1 ////////////////////////////////////////
//reg img_o_valid_d1;
reg [C_IMG_HW-1:0] img_o_diff_d1 ;
reg img_i_valid_d1;
reg [C_IMG_HW-1:0] img_i_diff_d1 ;
always @ (posedge clk) begin
if (resetn == 1'b0) begin
//img_o_valid_d1 <= 1'b0;
img_i_valid_d1 <= 1'b0;
img_o_diff_d1 <= 0;
img_i_diff_d1 <= 0;
end
else if (img_pulse) begin
//img_o_valid_d1 <= (img_lo_valid & img_ro_valid);
img_i_valid_d1 <= (img_li_valid & img_ri_valid);
if (C_L2R) begin
/// @note check sign
img_o_diff_d1 <= ($signed(img_lo_y) - $signed(img_ro_y));
img_i_diff_d1 <= ($signed(img_li_y) - $signed(img_ri_y));
end
else begin
img_o_diff_d1 <= ($signed(img_ro_y) - $signed(img_lo_y));
img_i_diff_d1 <= ($signed(img_ri_y) - $signed(img_li_y));
end
end
end
reg [1:0] m_self_running_hist;
reg [1:0] m_dep_running_hist;
always @ (posedge clk) begin
if (resetn == 1'b0) begin
m_self_running_hist <= 0;
m_dep_running_hist <= 0;
end
else if (img_pulse) begin
m_self_running_hist <= {m_self_running_hist[0], m_state};
m_dep_running_hist <= {m_dep_running_hist[0], m_dep_state};
end
else begin
if (m_state)
m_self_running_hist[0] <= 1'b1;
if (m_dep_state)
m_dep_running_hist[0] <= 1'b1;
end
end
/// @note cladding must valid
reg pen_d1;
always @ (posedge clk) begin
if (resetn == 1'b0)
pen_d1 <= 0;
else if (pen_d1 == 1'b1)
pen_d1 <= 0;
else if (img_pulse) begin
pen_d1 <= (req_dep_img
&& img_l_valid
&& img_r_valid
&& img_lo_valid
&& img_ro_valid);
end
end
//////////////////////////////// delay2 ////////////////////////////////////////
/// calc eccentric
reg [C_IMG_HW-1:0] img_ecf_d2 ;
reg [C_IMG_HW-1:0] img_i_diff_d2;
always @ (posedge clk) begin
if (resetn == 1'b0) begin
img_ecf_d2 <= 0;
img_i_diff_d2 <= 0;
end
else if (pen_d1) begin
if (req_ecf)
/// @note compensate 1/4
img_ecf_d2 <= ($signed(img_o_diff_d1) - $signed(img_i_diff_d1)) >>> 2;
else
img_ecf_d2 <= 0;
img_i_diff_d2 <= img_i_diff_d1;
end
end
reg img_self_valid;
reg img_real_valid;
always @ (posedge clk) begin
if (resetn == 1'b0) begin
img_self_valid <= 0;
img_real_valid <= 0;
end
else if (pen_d1) begin
img_self_valid <= (m_self_running_hist == 2'b00);
img_real_valid <= (m_dep_running_hist == 2'b00);
end
end
reg pen_d2;
always @ (posedge clk) begin
if (resetn == 1'b0)
pen_d2 <= 0;
else
pen_d2 <= pen_d1;
end
//////////////////////////////// delay3 ////////////////////////////////////////
/// calc eccentric
reg [C_IMG_HW-1:0] img_pos_d3 ;
always @ (posedge clk) begin
if (resetn == 1'b0) begin
img_pos_d3 <= 0;
end
else if (pen_d2) begin
if (req_ecf && img_i_valid_d1) begin
img_pos_d3 <= ($signed(img_i_diff_d2) - $signed(img_ecf_d2));
end
else begin
img_pos_d3 <= img_o_diff_d1;
end
end
end
reg pen_d3;
always @ (posedge clk) begin
if (resetn == 1'b0)
pen_d3 <= 0;
else
pen_d3 <= pen_d2;
end
//////////////////////////////// delay4 ////////////////////////////////////////
reg [C_IMG_HW-1:0] img_dst_d4 ;
always @ (posedge clk) begin
if (resetn == 1'b0) begin
img_dst_d4 <= 0;
end
else if (pen_d3) begin
if ($signed(img_pos_d3) > 0)
img_dst_d4 <= $signed(img_pos_d3) - $signed(req_img_dst);
else
img_dst_d4 <= $signed(img_pos_d3) + $signed(req_img_dst);
end
end
reg pen_d4;
always @ (posedge clk) begin
if (resetn == 1'b0)
pen_d4 <= 0;
else
pen_d4 <= pen_d3;
end
//////////////////////////////// delay5 ////////////////////////////////////////
/// calc eccentric
reg [C_IMG_HW-1:0] img_needback_d5;
reg [C_IMG_HW-1:0] img_dst_d5;
always @ (posedge clk) begin
if (resetn == 1'b0) begin
img_needback_d5 <= 0;
img_dst_d5 <= 0;
end
else if (pen_d4) begin
if ($signed(img_dst_d4) > 0) begin
img_needback_d5 <= 0;
img_dst_d5 <= img_dst_d4;
end
else begin
img_needback_d5 <= 1;
img_dst_d5 <= ~img_dst_d4 + 1;
end
end
end
reg pen_d5;
always @ (posedge clk) begin
if (resetn == 1'b0)
pen_d5 <= 0;
else
pen_d5 <= pen_d4;
end
//////////////////////////////// delay6 ////////////////////////////////////////
reg pos_needback;
reg pos_ok;
always @ (posedge clk) begin
if (resetn == 1'b0) begin
//rd_en <= 1'b0;
pos_ok <= 0;
pos_needback <= 0;
rd_addr <= 0;
end
else if (pen_d5) begin
pos_ok <= (img_dst_d5 < req_img_tol);
pos_needback <= img_needback_d5;
//rd_en <= 1'b1;
rd_addr <= img_dst_d5;
end
else begin
//rd_en <= 1'b0;
end
end
reg pen_d6;
always @ (posedge clk) begin
if (resetn == 1'b0)
pen_d6 <= 0;
else
pen_d6 <= pen_d5;
end
//////////////////////////////// delay7 ////////////////////////////////////////
reg pen_d7;
always @ (posedge clk) begin
if (resetn == 1'b0)
pen_d7 <= 0;
else
pen_d7 <= pen_d6;
end
//////////////////////////////// delay8 ////////////////////////////////////////
wire m_running;
assign m_running = m_state;
reg m_started;
always @ (posedge clk) begin
if (resetn == 1'b0)
m_started <= 1'b0;
else if (m_start)
m_started <= 1'b1;
end
reg m_run_over;
always @ (posedge clk) begin
if (resetn == 1'b0)
m_run_over <= 1'b0;
else if (m_running)
m_run_over <= 1'b1;
end
wire m_stopped;
assign m_stopped = (m_run_over && ~m_running);
always @ (posedge clk) begin
if (resetn == 1'b0) begin
exe_done <= 0;
end
else if (req_dep_img) begin
if (pen_d7)
exe_done <= (pos_ok && img_real_valid);
end
else begin
if (m_stopped)
exe_done <= 1;
end
end
/// start
always @ (posedge clk) begin
if (resetn == 1'b0) begin
m_start <= 1'b0;
end
else if (m_start == 1'b1) begin
m_start <= 1'b0;
end
else if (req_dep_img) begin
if (pen_d7 && img_self_valid && ~pos_ok) begin
m_start <= 1'b1;
m_speed <= req_speed;
m_step <= (pos_needback ? (0-rd_data) : rd_data);
m_abs <= 1'b0;
end
end
else begin
if (m_started == 1'b0) begin
m_start <= 1'b1;
m_speed <= req_speed;
m_step <= req_step;
m_abs <= req_abs;
end
end
end
reg processed;
always @ (posedge clk) begin
if (resetn == 1'b0) begin
test1 <= 0;
test2 <= 0;
test3 <= 0;
test4 <= 0;
processed <= 0;
end
else if (~processed) begin
if (pen_d7 && img_self_valid && ~pos_ok) begin
processed <= 1;
test1 <= req_speed;
test2 <= rd_data;
test3[15:0] <= img_pos_d3;
test3[31:16] <= img_dst_d4;
test4[15:0] <= img_dst_d5;
test4[31:16] <= rd_addr;
end
end
end
assign m_mod_remain = 0;
assign m_new_remain = 0;
assign m_stop = 0;
assign m_sel = resetn;
endmodule
|
Require Import String.
Open Scope list_scope.
Require Import bin_rels.
Require Import eq_rel.
Require Import universe.
Require Import LibTactics.
Require Import tactics.
Require Import Coq.Bool.Bool.
Require Import Coq.Program.Tactics.
Require Import Omega.
Require Import Coq.Program.Basics.
Require Import Coq.Lists.List.
Require Import Coq.Init.Notations.
Require Import UsefulTypes.
Require Import Coq.Classes.DecidableClass.
Require Import Coq.Classes.Morphisms.
Notation LIn := (List.In).
(**
uncomment this and remove the line above if [univ]:=Type
Fixpoint LIn {A : Type} (a:A) (l:list A) : [univ] :=
match l with
| nil => False
| b :: m => (b = a) [+] LIn a m
end.
Definition In := 9.
*)
(* Move *)
Definition listPad {T} (def:T) (l: list T) (n: nat) : list T :=
l++(repeat def (n-length l)).
Lemma listPad_length {T} (def:T) (l: list T) (n: nat):
n <= length (listPad def l n).
Proof using.
setoid_rewrite app_length.
rewrite repeat_length.
omega.
Qed.
Fixpoint ball (l : list bool) : bool :=
match l with
| [] => true
| x :: xs => andb x (ball xs)
end.
Lemma ball_true :
forall l,
ball l = true <=> (forall x, LIn x l -> x = true).
Proof.
induction l; simpl; sp.
rw andb_eq_true.
trw IHl; split; sp.
Qed.
Lemma ball_map_true :
forall A,
forall f : A -> bool,
forall l : list A,
ball (map f l) = true <=> forall x, LIn x l -> f x = true.
Proof.
induction l; simpl; sp.
trw andb_eq_true.
trw IHl; split; sp; subst; sp.
Qed.
Fixpoint remove {A:Type } `{Deq A} (x : A) (l : list A) : list A :=
match l with
| [] => []
| y::tl => if (decide (x = y)) then remove x tl else y::(remove x tl)
end.
Theorem remove_In {A:Type } `{Deq A} : forall (l : list A) (x : A), ~ In x (remove x l).
Proof.
induction l as [|x l]; auto. simpl. intro y.
rewrite decide_decideP.
cases_if; simpl; auto.
firstorder.
Qed.
(** l \ lr -- removes the elements of lr from l *)
Fixpoint diff {T} {eqd:Deq T} (lr:list T) (l:list T) : list T :=
match lr with
| [] => l
| h::t => diff t (remove h l)
end.
Lemma remove_trivial :
forall T x eq,
forall l : list T,
(! LIn x l)
-> @remove T eq x l = l.
Proof.
induction l as [| a l]; simpl; intro H; sp.
rewrite decide_decideP.
cases_if as Heq.
destruct H. left. auto.
f_equal.
rewrite IHl. auto.
introv Hlin. apply H. auto.
Qed.
Lemma diff_nil :
forall T eq, forall l : list T, @diff T eq l [] = [].
Proof.
induction l; simpl; auto.
Qed.
Hint Rewrite diff_nil.
Typeclasses eauto := 2.
Lemma in_remove {T:Type} `{Deq T}:
forall x y, forall l : list T,
LIn x (remove y l) <=> (~ x = y) # LIn x l.
Proof.
induction l; simpl.
split; sp. rewrite decide_decideP.
cases_if; subst; allsimpl; allrw IHl; split; sp; subst; sp.
Qed.
Lemma in_diff :
forall T,
forall l1 l2 : list T,
forall x eq,
LIn x (@diff T eq l1 l2)
<=>
(LIn x l2 # (! LIn x l1)).
Proof.
induction l1; simpl; sp.
split; sp. introv. auto.
trw IHl1; trw in_remove; split; sp; auto.
Qed.
Lemma remove_app {T:Type} `{Deq T}:
forall x,
forall l1 l2 : list T,
remove x (l1 ++ l2) = remove x l1 ++ remove x l2.
Proof.
induction l1; simpl; sp. repeat rewrite decide_decideP.
cases_if; subst; rewrite IHl1; auto.
Qed.
(* Move *)
Lemma deq_refl {T:Type} `{Deq T} : forall (x:T), (decide (x=x)) = true.
Proof.
intros.
rewrite Decidable_complete; auto.
Qed.
Lemma deqP_refl {T:Type} `{Deq T} : forall (x:T), (decideP (x=x)) = left eq_refl.
Proof.
intros. destruct (decideP (x = x)); try discriminate.
- f_equal. apply Eqdep_dec.UIP_dec.
intros. apply decideP; auto.
- sp.
Qed.
Hint Rewrite (fun T d => @deq_refl T d) (fun T d => @deqP_refl T d) : SquiggleEq.
Lemma remove_comm {T:Type} `{Deq T} :
forall l : list T,
forall x y,
remove x (remove y l) = remove y (remove x l).
Proof.
induction l; simpl; sp.
repeat rewrite decide_decideP.
repeat (cases_if; subst; simpl in *; auto; autorewrite with SquiggleEq; try congruence;
repeat rewrite decide_decideP).
Qed.
Lemma diff_remove {T:Type} {eq:Deq T} :
forall l1 l2 : list T,
forall x,
@diff T eq l1 (@remove T eq x l2) = @remove _ eq x (@diff _ eq l1 l2).
Proof.
induction l1; simpl; sp.
repeat (rewrite IHl1).
rewrite remove_comm; auto.
Qed.
Lemma diff_comm :
forall T eq,
forall l1 l2 l3 : list T,
@diff _ eq l1 (@diff _ eq l2 l3) = @diff _ eq l2 (@diff _ eq l1 l3).
Proof.
induction l1; simpl; sp.
rewrite <- diff_remove.
rewrite IHl1; auto.
Qed.
Lemma diff_app_r :
forall T eq,
forall l1 l2 l3 : list T,
@diff _ eq l1 (l2 ++ l3) = @diff _ eq l1 l2 ++ @diff _ eq l1 l3.
Proof.
induction l1; simpl; sp.
rewrite remove_app.
rewrite IHl1; auto.
Qed.
Lemma diff_app_l :
forall T eq,
forall l1 l2 l3 : list T,
@diff _ eq l1 (@diff _ eq l2 l3) = @diff _ eq (l1 ++ l2) l3.
Proof.
induction l1; simpl; sp.
repeat (rewrite diff_remove).
rewrite IHl1; auto.
Qed.
Lemma remove_repeat :
forall T eq x,
forall l : list T,
@remove T eq x l = @remove T eq x (@remove T eq x l).
Proof.
induction l; simpl; sp. repeat rewrite decide_decideP.
repeat cases_if; auto. simpl.
repeat rewrite decide_decideP.
repeat cases_if; simpl; auto.
provefalse; apply H; auto.
rewrite <- IHl; auto.
Qed.
Lemma diff_repeat :
forall T eq,
forall l1 l2 : list T,
@diff _ eq l1 l2 = @diff _ eq l1 (@diff _ eq l1 l2).
Proof.
induction l1; simpl; sp.
repeat (rewrite diff_remove).
rewrite <- remove_repeat.
rewrite <- IHl1; auto.
Qed.
Lemma remove_dup :
forall T eq,
forall l1 l2 : list T,
forall x,
LIn x l1
-> @diff _ eq l1 l2 = @remove T eq x (@diff _ eq l1 l2).
Proof.
induction l1; simpl; sp; subst.
rewrite diff_remove.
rewrite <- remove_repeat; auto.
Qed.
Lemma diff_move :
forall T eq,
forall l1 l2 l3 : list T,
forall x,
@diff _ eq (l1 ++ x :: l2) l3 = @diff _ eq (x :: l1 ++ l2) l3.
Proof.
induction l1; simpl; sp.
rewrite IHl1; simpl.
rewrite remove_comm; auto.
Qed.
Lemma diff_dup :
forall T eq,
forall l1 l2 l3 : list T,
forall x,
LIn x (l1 ++ l2)
-> @diff _ eq (l1 ++ l2) l3 = @diff _ eq (l1 ++ x :: l2) l3.
Proof.
induction l1; simpl; sp; subst.
rewrite diff_remove.
apply remove_dup; auto.
rewrite diff_move; simpl.
rewrite <- remove_repeat; auto.
Qed.
Lemma in_app_iff :
forall A l l' (a:A),
LIn a (l++l') <=> (LIn a l) [+] (LIn a l').
Proof.
induction l as [| a l]; introv; simpl; try (rw IHl); split; sp.
Qed.
Lemma in_map_iff :
forall (A B : Type) (f : A -> B) l b,
LIn b (map f l) <=> {a : A $ LIn a l # b = f a}.
Proof.
induction l; simpl; sp; try (complete (split; sp)).
trw IHl; split; sp; subst; sp.
exists a; sp.
exists a0; sp.
right; exists a0; sp.
Qed.
Lemma diff_dup2 :
forall T eq,
forall l1 l2 l3 : list T,
forall x,
LIn x l1
-> @diff _ eq (l1 ++ l2) l3 = @diff _ eq (l1 ++ x :: l2) l3.
Proof.
intros; apply diff_dup.
apply in_app_iff; left; auto.
Qed.
Definition null {T} (l : list T) := forall x, !LIn x l.
Lemma null_nil : forall T, null ([] : list T).
Proof.
unfold null; sp.
Qed.
Hint Immediate null_nil.
Lemma null_nil_iff : forall T, null ([] : list T) <=> True.
Proof.
split; sp; apply null_nil.
Qed.
Hint Rewrite null_nil_iff.
Hint Resolve decideP : SquiggleEq.
Lemma null_diff :
forall T,
forall eq : Deq T,
forall l1 l2 : list T,
null (@diff _ eq l1 l2) <=> forall x, LIn x l2 -> LIn x l1.
Proof.
induction l1; simpl; sp.
trw IHl1; sp; split; sp.
assert ({a = x} + {a <> x}) by auto with SquiggleEq; sp.
right; apply_hyp.
trw in_remove; sp.
alltrewrite in_remove; sp.
apply_in_hyp p; sp; subst; sp.
Qed.
Lemma null_iff_nil : forall T, forall l : list T, null l <=> l = [].
Proof.
induction l; unfold null; simpl; split; sp.
assert ((a = a) [+] LIn a l) by (left; auto).
apply_in_hyp p; sp.
Qed.
Lemma null_cons :
forall T x,
forall l : list T,
!( null (x :: l)).
Proof.
unfold null; sp.
assert (LIn x (x :: l)) by (simpl; left; auto).
apply_in_hyp p; sp.
Qed.
Hint Immediate null_cons.
Lemma null_app :
forall T,
forall l1 l2 : list T,
null (l1 ++ l2) <=> null l1 # null l2.
Proof.
induction l1; simpl; sp; split; sp;
try (apply null_nil);
try(apply null_cons in H); sp;
try(apply null_cons in H0); sp.
Qed.
Lemma null_map :
forall A B,
forall f : A -> B,
forall l : list A,
null (map f l) <=> null l.
Proof.
induction l; simpl; sp; split; sp;
try (apply null_nil);
apply null_cons in H; sp.
Qed.
Definition nullb {T} (l : list T) := if l then true else false.
Lemma assert_nullb :
forall T,
forall l : list T,
assert (nullb l) <=> null l.
Proof.
destruct l; simpl; split; sp.
apply not_assert in H; sp.
apply null_cons in H; sp.
Qed.
Definition subsetb {T} (eq : Deq T) (l1 l2 : list T) : bool :=
nullb (@diff _ eq l2 l1).
Definition eqsetb {T} (eq : Deq T) (l1 l2 : list T) : bool :=
subsetb eq l1 l2 && subsetb eq l2 l1.
Lemma assert_subsetb :
forall T eq,
forall l1 l2 : list T,
assert (subsetb eq l1 l2)
<=>
forall x, LIn x l1 -> LIn x l2.
Proof.
sp; unfold subsetb.
trw assert_nullb; trw null_diff; split; sp.
Qed.
Lemma assert_eqsetb :
forall T eq,
forall l1 l2 : list T,
assert (eqsetb eq l1 l2)
<=>
forall x, LIn x l1 <=> LIn x l2.
Proof.
sp; unfold eqsetb; trw assert_of_andb;
repeat (trw assert_subsetb); repeat (split; sp);
apply_in_hyp p; auto.
Qed.
Fixpoint beq_list {A} (eq : Deq A) (l1 l2 : list A) : bool :=
match l1, l2 with
| [], [] => true
| [], _ => false
| _, [] => false
| x :: xs, y :: ys => if (decide (x=y)) then beq_list eq xs ys else false
end.
Lemma assert_beq_list :
forall A eq,
forall l1 l2 : list A,
assert (beq_list eq l1 l2) <=> l1 = l2.
Proof.
unfold assert.
induction l1; destruct l2; simpl; repeat rewrite decide_decideP;
split; sp; try (complete (inversion H)).
destruct (decideP (a=a0)); subst; sp.
f_equal. apply IHl1; auto.
inversion H. subst.
autorewrite with SquiggleEq.
rewrite IHl1. refl.
Qed.
Global Instance deq_list {A:Type} `{Deq A} : Deq (list A).
Proof.
intros l1 l2. exists (beq_list _ l1 l2).
apply assert_beq_list.
Defined.
Typeclasses eauto :=6.
Lemma beq_list_refl :
forall A eq,
forall l : list A,
beq_list eq l l = true.
Proof.
induction l; simpl; sp.
autorewrite with SquiggleEq.
auto.
Qed.
Lemma eq_lists :
forall A (l1 l2 : list A) x,
l1 = l2
<=>
(
length l1 = length l2
#
forall n, nth n l1 x = nth n l2 x
).
Proof.
induction l1; sp; destruct l2; sp; split; allsimpl; sp;
try(inversion H);try(inversion H0); subst; sp.
gen_some 0; subst.
assert (l1 = l2) as eq; try (rewrite eq; sp).
apply IHl1 with (x := x); sp.
gen_some (S n); sp.
Qed.
(*
Fixpoint memberb' {A} (eq : Deq A) (x : A) (l : list A) : { LIn x l } + { ! LIn x l} :=
match l return { LIn x l } + { ! LIn x l} with
| [] => right (fun x => x)
| y :: ys =>
match eq y x with
| left e => left (or_introl e)
| right _ =>
match memberb' eq x ys with
| left x => left (or_intror x)
| right y => right y
end
end
end.
*)
Fixpoint memberb {A : Type} (eq : Deq A) (x : A) (l : list A) : bool :=
match l with
| [] => false
| y :: ys => if decide (y=x) then true else memberb eq x ys
end.
Theorem assert_memberb :
forall {T:Type} {eq : Deq T} (a:T) (l: list T),
assert (memberb eq a l) <=> LIn a l.
Proof with (repeat rewrite decide_decideP).
intros. induction l. simpl.
try (unfold assert; repeat split; intros Hf; auto ; inversion Hf).
simpl ... cases_if. subst. unfold assert; repeat split; auto.
repeat split; intros Hlr. right. apply IHl; auto.
destruct Hlr as [Heq | Hin]; tauto.
Qed.
Lemma memberb_app :
forall A eq x,
forall l1 l2 : list A,
memberb eq x (l1 ++ l2) = memberb eq x l1 || memberb eq x l2.
Proof with (repeat rewrite decide_decideP).
induction l1; simpl; sp ...
destruct (decideP (a = x)); sp.
Qed.
Lemma in_app_deq :
forall A l1 l2 (a : A) (deq : Deq A),
LIn a (l1 ++ l2) -> (LIn a l1 + LIn a l2).
Proof.
introv deq i.
rw <- (@assert_memberb A deq) in i.
rw memberb_app in i.
apply assert_orb in i; sp; allrw (@assert_memberb A deq); sp.
Qed.
Lemma diff_cons_r :
forall A eq x,
forall l1 l2 : list A,
@diff _ eq l1 (x :: l2)
= if memberb eq x l1
then @diff _ eq l1 l2
else x :: @diff _ eq l1 l2.
Proof with (repeat rewrite decide_decideP).
induction l1; simpl; sp...
destruct (decideP (a=x)); subst; auto.
Qed.
Lemma diff_cons_r_ni :
forall A eq x,
forall l1 l2 : list A,
!LIn x l2 -> @diff _ eq (x :: l1) l2 = @diff _ eq l1 l2.
Proof with (repeat rewrite decide_decideP).
induction l1; simpl; sp.
induction l2; allsimpl; allrw not_over_or; sp...
destruct (decideP (x=a)); try subst; sp ;
allrw; sp.
Locate remove_trivial.
rw (remove_trivial A x); sp.
Qed.
Fixpoint maxl (ts : list nat) : nat :=
match ts with
| nil => 0
| n :: ns => max n (maxl ns)
end.
Lemma maxl_prop :
forall nats n,
LIn n nats -> n <= maxl nats.
Proof.
induction nats; simpl; sp; subst.
apply max_prop1.
allapply IHnats.
assert (maxl nats <= max a (maxl nats)) by apply max_prop2.
omega.
Qed.
Fixpoint addl (ts : list nat) : nat :=
match ts with
| nil => 0
| n :: ns => n + (addl ns)
end.
Theorem lin_flat_map :
forall (A B : Type) (f : A -> list B) (l : list A) (y : B),
LIn y (flat_map f l)
<=>
{x : A $ LIn x l # LIn y (f x)}.
Proof.
induction l; simpl; sp.
split; sp.
trw in_app_iff.
trw IHl.
split; sp; subst; sp.
exists a; sp.
exists x; sp.
right; exists x; sp.
Qed.
Theorem flat_map_empty:
forall A B (ll:list A) (f: A -> list B) , flat_map f ll =[]
<=> forall a, LIn a ll -> f a =[].
Proof. sp_iff Case.
Case "->".
intros Hmap a Hin; remember (f a) as fa; destruct fa.
auto. assert ({a: A $ LIn a ll # LIn b (f a)}) as Hass;
try (apply lin_flat_map in Hass;
rewrite Hmap in Hass; inversion Hass).
exists a. (split; auto). rewrite <- Heqfa.
constructor; auto.
Case "<-".
intros Hin.
remember (flat_map f ll) as flat; destruct flat ;auto.
assert ( LIn b (flat_map f ll)) as Hinbf by
(rewrite <- Heqflat; constructor; auto).
apply lin_flat_map in Hinbf. exrepnd.
apply Hin in Hinbf1.
rewrite Hinbf1 in Hinbf0.
inversion Hinbf0.
Qed.
Lemma flat_map_map :
forall A B C ,
forall f : B -> list C,
forall g : A -> B,
forall l : list A,
flat_map f (map g l) = flat_map (compose f g) l.
Proof.
induction l; simpl; sp.
rewrite IHl.
unfold compose; auto.
Qed.
Lemma map_map :
forall A B C ,
forall f : B -> C,
forall g : A -> B,
forall l : list A,
map f (map g l) = map (compose f g) l.
Proof.
induction l; simpl; sp.
rewrite IHl.
unfold compose; auto.
Qed.
Lemma eq_flat_maps :
forall A B,
forall f g : A -> list B,
forall l : list A,
(forall x, LIn x l -> f x = g x)
-> flat_map f l = flat_map g l.
Proof.
induction l; simpl; sp.
assert (f a = g a).
apply H; left; auto.
rewrite H0.
assert (flat_map f l = flat_map g l).
rewrite IHl; auto.
rewrite H1; auto.
Qed.
Lemma eq_maps :
forall A B,
forall f g : A -> B,
forall l : list A,
(forall x, LIn x l -> f x = g x)
-> map f l = map g l.
Proof.
induction l; simpl; sp.
assert (f a = g a).
apply H; left; auto.
rewrite H0.
rewrite IHl; auto.
Qed.
Lemma in_nth :
forall T a (l:list T),
LIn a l
-> {n : nat $ (n < length l) # a = nth n l a}.
Proof.
intros ? ? ?. induction l; intros Hin.
- simpl in Hin. contradiction.
- simpl in Hin. dorn Hin.
+ intros. subst. exists 0. split; auto. simpl. omega.
+ intros. apply IHl in Hin. exrepnd.
simpl.
exists (S n) ;split ; try (simpl; omega).
fold (app [a0] l);sp.
Qed.
(* stronger one above : no need for decidability
Lemma in_nth :
forall T a (l:list T),
Deq T
-> LIn a l
-> {n : nat $ (n < length l) # a = nth n l a}.
Proof.
intros ? ? ? deq. induction l; intros Hin.
- simpl in Hin. contradiction.
- case (deq a a0).
+ intros. subst. exists 0. split; auto. simpl. omega.
+ intros Hneq. simpl in Hin.
destruct Hin as [Heq | Hin].
* symmetry in Heq. apply Hneq in Heq. contradiction.
* apply IHl in Hin. clear Hneq. destruct Hin as [m Hp]. repnd.
exists (S m) ;split ; try (simpl; omega).
fold (app [a0] l).
rewrite app_nth2. simpl. assert (m-0 =m) as Hrew by omega.
rewrite Hrew. auto. simpl. omega.
Qed.
*)
Lemma nth_in :
forall A n (l : list A) d,
n < length l
-> LIn (nth n l d) l.
Proof.
intros A n l d H; revert n H.
induction l; simpl; sp.
destruct n; sp.
allapply S_lt_inj; sp.
Qed.
Fixpoint snoc {X:Type} (l:list X) (v:X) : (list X) :=
match l with
| nil => cons v nil
| cons h t => cons h (snoc t v)
end.
Lemma length_snoc :
forall T,
forall n : T,
forall l : list T,
length (snoc l n) = S (length l).
Proof.
intros; induction l; simpl; sp.
Qed.
Lemma snoc_as_append :
forall T, forall l : list T, forall n,
snoc l n = l ++ [n].
Proof.
intros; induction l; simpl; sp.
rewrite IHl; sp.
Qed.
Lemma snoc_append_r :
forall T, forall l1 l2 : list T, forall v : T,
(snoc l1 v) ++ l2 = l1 ++ (v :: l2).
Proof.
intros; induction l1; simpl; sp.
rewrite IHl1; sp.
Qed.
Lemma snoc_append_l :
forall T, forall l1 l2 : list T, forall v : T,
l2 ++ (snoc l1 v) = snoc (l2 ++ l1) v.
Proof.
intros; induction l2; simpl; sp.
rewrite IHl2; sp.
Qed.
Lemma in_snoc :
forall T,
forall l : list T,
forall x y : T,
LIn x (snoc l y) <=> (LIn x l [+] x = y).
Proof.
induction l; simpl; sp.
split; sp.
trw IHl.
apply sum_assoc.
Qed.
Hint Rewrite in_snoc.
Lemma snoc_cases :
forall T,
forall l : list T,
l = [] [+] {a : T $ {k : list T $ l = snoc k a}}.
Proof.
induction l.
left; auto.
sp; subst.
right; exists a; exists (@nil T); simpl; auto.
right.
exists a0; exists (a :: k); simpl; auto.
Qed.
Lemma snoc_inj :
forall T,
forall l1 l2 : list T,
forall x1 x2 : T,
snoc l1 x1 = snoc l2 x2 -> l1 = l2 # x1 = x2.
Proof.
induction l1; simpl; intros.
destruct l2; simpl in H; inversion H; subst; auto.
inversion H.
destruct l2; simpl in H1; inversion H1.
destruct l2; simpl in H.
inversion H.
destruct l1; simpl in H2; inversion H2.
inversion H.
apply IHl1 in H2. sp; subst; auto.
Qed.
Lemma map_snoc :
forall A B l x,
forall f : A -> B,
map f (snoc l x) = snoc (map f l) (f x).
Proof.
induction l; simpl; sp.
rewrite IHl; sp.
Qed.
Open Scope nat_scope.
Lemma length_app :
forall T,
forall l1 l2 : list T,
length (l1 ++ l2) = length l1 + length l2.
Proof.
induction l1; simpl; sp.
Qed.
Lemma nil_snoc_false :
forall T, forall a : list T, forall b : T, [] = snoc a b -> False.
Proof.
intros.
assert (length ([] : list T) = length (snoc a b)).
rewrite H; auto.
simpl in H0.
rewrite length_snoc in H0.
inversion H0.
Qed.
Definition subset {T} (l1 l2 : list T) :=
forall x, LIn x l1 -> LIn x l2.
Lemma fold_subset :
forall T l1 l2,
(forall x : T, LIn x l1 -> LIn x l2) = subset l1 l2.
Proof. sp. Qed.
Lemma null_diff_subset :
forall T,
forall eq : Deq T,
forall l1 l2 : list T,
null (@diff _ eq l1 l2) <=> subset l2 l1.
Proof.
sp; apply null_diff; unfold subset; split; sp.
Qed.
Lemma subsetb_subset :
forall T eq,
forall l1 l2 : list T,
assert (subsetb eq l1 l2) <=> subset l1 l2.
Proof.
intros.
apply assert_subsetb; unfold subset; split; sp.
Qed.
Lemma subset_refl :
forall T,
forall l : list T,
subset l l.
Proof.
unfold subset; sp.
Qed.
Hint Immediate subset_refl.
Lemma subset_refl_iff :
forall T,
forall l : list T,
subset l l <=> True.
Proof.
unfold subset; sp; split; sp.
Qed.
Hint Rewrite subset_refl_iff.
Lemma subset_nil_l :
forall T, forall s : list T, subset [] s.
Proof.
unfold subset; simpl; sp.
Qed.
Hint Immediate subset_nil_l.
Lemma subset_nil_l_iff :
forall T, forall s : list T, subset [] s <=> True.
Proof.
unfold subset; simpl; sp; split; sp.
Qed.
Hint Rewrite subset_nil_l_iff.
(* same as subset_nil_l *)
Lemma nil_subset :
forall T, forall l : list T, subset [] l.
Proof.
auto.
Qed.
(* same as subset_nil_l_iff *)
Lemma nil_subset_iff :
forall T,
forall l : list T,
subset [] l <=> True.
Proof.
sp; autorewrite with core; sp.
Qed.
Lemma cons_subset :
forall T,
forall x : T,
forall l1 l2 : list T,
subset (x :: l1) l2
<=> LIn x l2 # subset l1 l2.
Proof.
unfold subset; simpl; sp; split; sp; subst; auto.
Qed.
Tactic Notation "trewritec" constr(H) :=
build_and_rewrite H.
Lemma singleton_subset :
forall T,
forall x : T,
forall l : list T,
subset [x] l <=> LIn x l.
Proof.
intros.
remember (cons_subset T x [] l) as Htr.
trewrite Htr.
split; sp.
Qed.
Lemma app_subset :
forall T,
forall l1 l2 l3 : list T,
subset (l1 ++ l2) l3 <=> subset l1 l3 # subset l2 l3.
Proof.
induction l1; simpl; sp; try(split; sp; fail).
trw cons_subset. trw cons_subset.
split; introv Hlin; repnd;
try(trw IHl1); try(trw_h IHl1 Hlin; repnd);
repeat(auto;split;auto).
Qed.
Lemma subset_trans :
forall T,
forall l1 l2 l3 : list T,
subset l1 l2
-> subset l2 l3
-> subset l1 l3.
Proof.
unfold subset; sp.
Qed.
Lemma subset_cons_nil :
forall T x,
forall l : list T,
! subset (x :: l) [].
Proof.
unfold subset; sp.
assert ( LIn x (x :: l)) by (simpl; left; auto).
apply_in_hyp p; allsimpl; sp.
Qed.
Lemma subset_cons1 :
forall T,
forall x : T,
forall l1 l2 : list T,
subset l1 l2
-> subset l1 (x :: l2).
Proof.
unfold subset; simpl; sp.
Qed.
Lemma subset_cons2 :
forall T,
forall x : T,
forall l1 l2 : list T,
subset l1 l2
-> subset (x :: l1) (x :: l2).
Proof.
unfold subset; simpl; sp.
Qed.
Lemma subset_app_r :
forall T,
forall l1 l2 l3 : list T,
subset l1 l2 -> subset l1 (l2 ++ l3).
Proof.
unfold subset; intros.
apply (@in_app_iff T).
left; auto.
Qed.
Lemma subset_app_l :
forall T,
forall l1 l2 l3 : list T,
subset l1 l3 -> subset l1 (l2 ++ l3).
Proof.
unfold subset; intros.
apply in_app_iff.
right; auto.
Qed.
Lemma subset_app :
forall T,
forall l1 l2 l3 : list T,
subset (l1 ++ l2) l3 <=> subset l1 l3 # subset l2 l3.
Proof.
unfold subset; sp; split; sp.
apply_hyp; apply in_app_iff; left; auto.
apply_hyp; apply in_app_iff; right; auto.
allrw in_app_iff; sp.
Qed.
Lemma subset_snoc_r :
forall T x,
forall l1 l2 : list T,
subset l1 l2 -> subset l1 (snoc l2 x).
Proof.
unfold subset; intros.
apply in_snoc.
left; auto.
Qed.
Lemma subset_snoc_l :
forall T x,
forall l1 l2 : list T,
(forall y, LIn y l1 -> y = x)
-> subset l1 (snoc l2 x).
Proof.
unfold subset; sp.
apply in_snoc.
apply_in_hyp p; sp.
Qed.
Lemma null_subset :
forall T,
forall l1 l2 : list T,
subset l1 l2
-> null l2
-> null l1.
Proof.
unfold subset, null; sp.
apply_in_hyp p; sp.
Qed.
Lemma subset_cons_l :
forall T v,
forall vs1 vs2 : list T,
subset (v :: vs1) vs2 <=> LIn v vs2 # subset vs1 vs2.
Proof.
unfold subset; simpl; sp; split; sp; subst; auto.
Qed.
Lemma in_subset :
forall T (s1 s2 : list T) x,
subset s1 s2
-> LIn x s1
-> LIn x s2.
Proof.
intros T s1 s2 x.
unfold subset; sp.
Qed.
Lemma not_in_subset :
forall T (s1 s2 : list T) x,
subset s1 s2
-> LIn x s1
-> ! LIn x s2
-> False.
Proof.
intros T s1 s2 x.
unfold subset; sp.
Qed.
Lemma subset_flat_map :
forall A B,
forall f : A -> list B,
forall l k,
subset (flat_map f l) k
<=>
forall x, LIn x l -> subset (f x) k.
Proof.
induction l; simpl; sp.
trw nil_subset_iff; split; sp.
trw app_subset; split; sp; subst; sp; alltrewrite IHl; sp.
Qed.
Global Instance in_deqq {A:Type} `{Deq A} (x:A) l: Decidable (LIn x l).
Proof.
intros.
exists (memberb _ x l).
apply assert_memberb.
Defined.
(* Require Import Morphisms. *)
Lemma in_deq :
forall A,
forall eq : Deq A,
forall x : A,
forall l,
LIn x l + !LIn x l.
Proof.
induction l; simpl; sp; try (complete (right; sp)).
destruct (decideP (a=x)); subst; sp.
right; sp.
Defined.
Lemma subset_diff :
forall A eq,
forall l1 l2 l3 : list A,
subset (@diff _ eq l1 l2) l3
<=>
subset l2 (l3 ++ l1).
Proof.
unfold subset; sp; split; sp.
apply in_app_iff.
assert (LIn x l1 + !LIn x l1) by (apply in_deq; auto); sp.
left; apply_hyp; apply in_diff; sp.
allrw in_diff; sp.
apply_in_hyp p.
allrw in_app_iff; sp.
Qed.
Definition disjoint {T} (l1 l2 : list T) :=
forall t, LIn t l1 -> !LIn t l2.
Lemma disjoint_nil_r :
forall T,
forall l : list T,
disjoint l [].
Proof.
unfold disjoint; sp.
Qed.
Hint Immediate disjoint_nil_r.
Lemma disjoint_nil_r_iff :
forall T,
forall l : list T,
disjoint l [] <=> True.
Proof.
unfold disjoint; sp; split; sp.
Qed.
Hint Rewrite disjoint_nil_r_iff.
Lemma disjoint_nil_l :
forall T,
forall l : list T,
disjoint [] l.
Proof.
unfold disjoint; sp.
Qed.
Hint Immediate disjoint_nil_l.
Lemma disjoint_nil_l_iff :
forall T,
forall l : list T,
disjoint [] l <=> True.
Proof.
unfold disjoint; sp; split; sp.
Qed.
Hint Rewrite disjoint_nil_l_iff.
Lemma disjoint_sym_impl :
forall T,
forall l1 l2 : list T,
disjoint l1 l2 -> disjoint l2 l1.
Proof.
unfold disjoint; sp.
apply_in_hyp p; sp.
Qed.
Lemma disjoint_sym :
forall T,
forall l1 l2 : list T,
disjoint l1 l2 <=> disjoint l2 l1.
Proof.
sp; split; sp; apply disjoint_sym_impl; auto.
Qed.
Lemma disjoint_cons_r :
forall T x,
forall l1 l2 : list T,
disjoint l1 (x :: l2)
<=> disjoint l1 l2 # !LIn x l1.
Proof.
unfold disjoint; sp; split; sp;
apply_in_hyp p; allsimpl; sp; subst; sp.
Qed.
Lemma disjoint_cons_l :
forall T x,
forall l1 l2 : list T,
disjoint (x :: l1) l2
<=> disjoint l1 l2 # ! LIn x l2.
Proof.
intros; sp.
trw disjoint_sym.
trw disjoint_cons_r.
trw disjoint_sym; split; auto.
Qed.
Lemma disjoint_iff_diff :
forall T eq,
forall l1 l2 : list T,
disjoint l2 l1 <=> @diff _ eq l1 l2 = l2.
Proof.
induction l1; simpl; sp.
trw disjoint_cons_r.
trw IHl1.
sp_iff Case; intros; exrepd.
- Case "->".
rewrite remove_trivial; auto.
- Case "<-".
assert (!LIn a l2)
by (intro i; rw <- H in i;
allrw in_diff; sp;
allrw in_remove; sp).
rewrite remove_trivial in H; auto.
Qed.
Lemma disjoint_snoc_r :
forall T,
forall l1 l2 : list T,
forall x : T,
disjoint l1 (snoc l2 x)
<=> (disjoint l1 l2 # ! LIn x l1).
Proof.
unfold disjoint; sp; split; intros.
- sp; apply_in_hyp p; trw_h in_snoc p; trw_h not_over_or p; sp.
- sp.
allrw in_snoc; sp; subst; sp.
apply_in_hyp p; sp.
Qed.
Lemma disjoint_snoc_l :
forall T,
forall l1 l2 : list T,
forall x : T,
disjoint (snoc l1 x) l2
<=> (disjoint l1 l2 # !LIn x l2).
Proof.
intros; trw disjoint_sym.
trw disjoint_snoc_r; split; sp; trw disjoint_sym; sp.
Qed.
Lemma subset_disjoint :
forall T,
forall l1 l2 l3 : list T,
subset l1 l2
-> disjoint l2 l3
-> disjoint l1 l3.
Proof.
unfold subset, disjoint; intros; auto.
Qed.
Lemma disjoint_singleton_l :
forall A (x : A) s,
disjoint [x] s <=> ! LIn x s.
Proof.
unfold disjoint; simpl; split; intros; auto; sp; subst; sp.
Qed.
Lemma disjoint_singleton_r :
forall A (x : A) s,
disjoint s [x] <=> ! LIn x s.
Proof.
unfold disjoint; split; simpl; sp; subst; sp.
apply_in_hyp p; sp.
Qed.
Lemma disjoint_app_l :
forall A,
forall l1 l2 l3 : list A,
disjoint (l1 ++ l2) l3
<=> (disjoint l1 l3 # disjoint l2 l3).
Proof.
induction l1; simpl; sp; split; sp.
alltrewrite disjoint_cons_l; trw_h IHl1 H; sp.
alltrewrite disjoint_cons_l; trw_h IHl1 H; sp.
alltrewrite disjoint_cons_l; sp.
trw IHl1; sp.
Qed.
Lemma disjoint_app_r :
forall A,
forall l1 l2 l3 : list A,
disjoint l1 (l2 ++ l3)
<=> (disjoint l1 l2 # disjoint l1 l3).
Proof.
intros; trw disjoint_sym.
trw disjoint_app_l.
split; sp; trw disjoint_sym; sp.
Qed.
Lemma disjoint_flat_map_l :
forall A B,
forall f : A -> list B,
forall l1 : list A,
forall l2 : list B,
disjoint (flat_map f l1) l2
<=>
(forall x, LIn x l1 -> disjoint (f x) l2).
Proof.
induction l1; simpl; sp.
split; sp.
trw disjoint_app_l.
trw IHl1.
split; sp; subst; sp.
Qed.
Lemma disjoint_flat_map_r :
forall A B,
forall f : A -> list B,
forall l1 : list A,
forall l2 : list B,
disjoint l2 (flat_map f l1)
<=>
(forall x, LIn x l1 -> disjoint l2 (f x)).
Proof.
sp.
rw disjoint_sym.
rw disjoint_flat_map_l; split; sp;
rw disjoint_sym; sp.
Qed.
Lemma disjoint_remove_l :
forall A eq x,
forall l1 l2 : list A,
disjoint (@remove _ eq x l1) l2 <=> disjoint l1 (@remove _ eq x l2).
Proof.
intros.
unfold disjoint.
setoid_rewrite in_remove.
firstorder.
Qed.
Lemma disjoint_diff_l :
forall A eq,
forall l1 l2 l3 : list A,
disjoint (@diff _ eq l1 l2) l3 <=> disjoint l2 (@diff _ eq l1 l3).
Proof.
induction l1; simpl; sp.
trw IHl1.
rewrite diff_remove.
trw disjoint_remove_l. split; sp.
Qed.
Lemma length0 :
forall T, forall l : list T,
length l = 0 <=> l = [].
Proof.
destruct l; simpl; sp; split; sp; inversion H.
Qed.
Lemma rev_list_indT :
forall (A : Type) (P : list A -> [univ]),
P [] ->
(forall (a : A) (l : list A), P l -> P (snoc l a)) ->
forall l : list A, P l.
Proof.
intros.
assert ({n | length l = n}) as e by (exists (length l); auto); sp.
revert l e.
induction n; intros.
apply length0 in e; subst; sp.
generalize (snoc_cases A l); sp; subst; auto.
apph (apply IHn).
allrewrite length_snoc; allapply S_inj; auto.
Qed.
Lemma rev_list_dest :
forall T,
forall l : list T,
l = [] [+] {u : list T $ {v : T $ l = snoc u v}}.
Proof.
induction l using rev_list_indT.
left; auto.
right; auto.
exists l. exists a; auto.
Qed.
Lemma rev_list_dest2 :
forall {T} (l : list T),
l = [] [+] {u : list T $ {v : T $ l = snoc u v}}.
Proof.
induction l using rev_list_indT.
left; auto.
right; auto.
exists l. exists a; auto.
Qed.
Ltac rev_list_dest l :=
let name := fresh "or" in
generalize (rev_list_dest2 l);
intro name;
destruct name;
try exrepd;
subst.
Lemma rev_list_ind :
forall (A : Type) (P : list A -> Prop),
P [] ->
(forall (a : A) (l : list A), P l -> P (snoc l a)) ->
forall l : list A, P l.
Proof.
intros.
assert ({n : nat $ length l = n}) as p by (exists (length l); auto).
destruct p as [n e].
revert l e.
induction n; intros.
apply length0 in e; subst; sp.
generalize (snoc_cases A l); sp; subst; auto.
apply H0.
apply IHn.
allrewrite length_snoc; allapply S_inj; auto.
Qed.
Lemma combine_in_left : forall T1 T2 (l1: list T1) (l2: list T2),
(length l1=length l2) -> forall u1, ( LIn u1 l1) -> {u2 : T2 $ LIn (u1,u2) (combine l1 l2)}.
Proof. induction l1; intros ? Hlen ? Hin; inverts Hin as Hin; simpl in Hlen;
destruct l2 ; simpl in Hlen; inversion Hlen.
- subst. exists t. simpl. left; auto.
- apply IHl1 with l2 u1 in Hin; auto. parallel u2 Hcom.
simpl. right; auto.
Qed.
Lemma combine_in_left2 : forall T1 T2 (l1: list T1) (l2: list T2),
(length l1 <= length l2) -> forall u1, ( LIn u1 l1) -> {u2 : T2 $ LIn (u1,u2) (combine l1 l2)}.
Proof. induction l1; intros ? Hlen ? Hin. inverts Hin as Hin; simpl in Hlen.
destruct l2 ; simpl in Hlen. omega. inverts Hin as Hin.
- subst. exists t. simpl. left; auto.
- apply IHl1 with l2 u1 in Hin; auto. parallel u2 Hcom.
simpl. right; auto. omega.
Qed.
Lemma cons_as_app :
forall T (a : T) (b : list T),
a :: b = [a] ++ b.
Proof. sp. Qed.
Lemma length1 :
forall T, forall l : list T,
length l = 1 <=> {x : T $ l = [x]}.
Proof.
destruct l; simpl; sp.
split; sp; inversion H.
split; sp; try (inversion H); subst.
destruct l; simpl in H1; inversion H1.
exists t; auto.
invs; sp.
Qed.
Lemma snoc1 :
forall T,
forall a : list T,
forall b x : T,
snoc a b = [x] <=> a = [] # b = x.
Proof.
destruct a; simpl; sp; split; sp; subst; auto.
inversion H; auto.
inversion H; subst; auto.
destruct a; simpl in H2; inversion H2.
inversion H; subst; auto.
destruct a; simpl in H2; inversion H2.
Qed.
Theorem in_single: forall T (a b : T), LIn a [b] -> a=b.
Proof. introv H. invertsn H. auto. inversion H.
Qed.
Lemma in_list2 : forall T (x a b :T),
( LIn x [a,b]) -> (x=a [+] x=b).
Proof. introv H. invertsn H. left; auto.
invertsn H; right; auto.
inverts H.
Qed.
Tactic Notation "dlist2" ident(h) :=
apply in_list2 in h; destruct h.
Lemma in_list2_elim : forall T ( a b :T) (P: T-> Prop),
(forall x, ( LIn x [a,b]) -> P x) -> (P a # P b).
Proof. introv H. split; apply H; simpl; auto.
Qed.
Lemma in_list1 :
forall T (x a :T),
LIn x [a] -> x = a.
Proof.
introv H. invertsn H. auto.
inverts H.
Qed.
Lemma in_list1_elim : forall T (x a b :T) (P: T-> Prop),
(forall x, ( LIn x [a]) -> P x) -> (P a).
Proof. intros. apply H; simpl; auto.
Qed.
Tactic Notation "dlist" ident(l) ident(cs) "as" simple_intropattern(I) :=
destruct l as I;
[ Case_aux cs "nilcase"
| Case_aux cs "conscase"
].
Lemma app_split :
forall T,
forall l1 l2 l3 l4 : list T,
length l1 = length l3
-> l1 ++ l2 = l3 ++ l4
-> l1 = l3 # l2 = l4.
Proof.
induction l1; simpl; sp.
destruct l3; allsimpl; auto.
inversion H.
destruct l3; allsimpl; auto.
inversion H.
destruct l3; allsimpl; auto.
inversion H.
inversion H0; subst.
apply IHl1 in H3; sp; subst; auto.
inversion H0; subst.
destruct l3; allsimpl; auto.
inversion H.
inversion H0; subst.
apply IHl1 in H4; sp; subst; auto.
Qed.
Lemma cons_eq :
forall A a,
forall b c : list A,
b = c -> a :: b = a :: c.
Proof.
sp; subst; sp.
Qed.
Lemma cons_app :
forall T (x : T) l1 l2,
x :: (l1 ++ l2) = (x :: l1) ++ l2.
Proof.
sp.
Qed.
Lemma cons_snoc :
forall T (x y : T) l,
x :: (snoc l y) = snoc (x :: l) y.
Proof.
sp.
Qed.
Lemma cons_inj :
forall A (a c : A) b d,
a :: b = c :: d -> a = c # b = d.
Proof.
sp; inversion H; sp.
Qed.
Lemma in_combine :
forall A B a b,
forall l1 : list A,
forall l2 : list B,
LIn (a,b) (combine l1 l2)
-> LIn a l1 # LIn b l2.
Proof.
induction l1; introv Hlin; simpl; sp; destruct l2; allsimpl; sp;
allapply pair_inj; repnd; subst; sp; apply_in_hyp p; sp.
Qed.
Lemma implies_in_combine :
forall A B (l1 : list A) (l2 : list B) x,
length l1 = length l2
-> LIn x l1
-> {y : B $ LIn (x, y) (combine l1 l2)}.
Proof.
induction l1; simpl; sp; destruct l2; allsimpl; subst; sp;
invertsn H.
exists b; sp.
apply IHl1 with(x:=x) in H; sp.
exists y; sp.
Qed.
Lemma in_repeat : forall T n (u t:T), LIn u (repeat t n) -> u=t.
Proof. induction n; introv H; simpl. inverts H.
simpl in H. destruct H; auto.
Qed.
Lemma combine_app_eq: forall A B (l1:list A) (l21 l22: list B),
length l1 <= length l21 -> combine l1 l21 = combine l1 (l21 ++ l22).
Proof. induction l1;
intros ? ? Hle; simpl; auto.
destruct l21; simpl. inverts Hle.
rewrite <- IHl1; allsimpl; try omega; auto.
Qed.
Lemma combine_nil :
forall A B (l : list A),
combine l (@nil B) = nil.
Proof.
induction l; simpl; auto.
Qed.
Hint Rewrite combine_nil.
Lemma firstn_nil:
forall n T , firstn n nil = @nil T.
Proof.
induction n; intros; simpl; auto.
Qed.
Hint Rewrite firstn_nil.
Lemma app_eq_nil_iff :
forall T (l1 l2 : list T),
l1 ++ l2 = [] <=> (l1 = [] # l2 = []).
Proof.
sp; split; sp; subst; sp; destruct l1; destruct l2; allsimpl; sp.
Qed.
Lemma combine_app_app :
forall A B (l1:list A) (l21 l22: list B),
length l21 <= length l1
-> combine l1 (l21 ++ l22) =
combine l1 l21
++
combine (skipn (length l21) l1) (firstn (length l1-length l21) l22).
Proof.
induction l1; intros ? ? Hle. inverts Hle. trw_h length0 H0. subst.
simpl. auto.
simpl. destruct l21; destruct l22; simpl; auto; try omega.
- fold (app nil l22). rewrite IHl1. rewrite combine_nil. simpl.
assert (length l1 - 0 =length l1) as Hmin by omega. rewrite Hmin. auto.
simpl. omega.
- rewrite app_nil_r. rewrite firstn_nil. rewrite combine_nil. rewrite app_nil_r. auto.
- simpl in Hle. simpl. rewrite IHl1; auto; omega.
Qed.
Lemma in_firstn : forall T n a (l: list T),
n>0 -> LIn a (firstn n l) -> LIn a l.
Proof. induction n; intros ? ? Hgt Hin.
inverts Hin. destruct l. inverts Hin.
simpl in Hin. dorn Hin. left; auto.
right; auto. destruct n. inverts Hin. apply IHn; auto. omega.
Qed.
(* Counter-example: al = [0;1], a = 1, n = 1, t = 0, then ( LIn 1 al) is true
* but LIn (1,0) (combine al (repeat n t)) is LIn (1,0) [(0,0)] is false.
* It is true if length al = n though. *)
Lemma false_in_combine_repeat :
forall A B (al : list A) (t : B) n,
n > 0
-> forall a, LIn a al -> LIn (a,t) (combine al (repeat t n)).
Abort.
Lemma in_combine_repeat :
forall A B (al : list A) (t : B) n,
length al <= n
-> forall a, LIn a al -> LIn (a,t) (combine al (repeat t n)).
Proof.
induction al; simpl; sp; subst; destruct n; try omega;
allapply S_le_inj; simpl; sp.
Qed.
Lemma length_filter :
forall T f (l : list T),
length (filter f l) <= length l.
Proof.
induction l; simpl; sp.
destruct (f a); simpl; omega.
Qed.
Lemma filter_snoc :
forall T f (l : list T) x,
filter f (snoc l x)
= if f x then snoc (filter f l) x else filter f l.
Proof.
induction l; simpl; sp.
destruct (f a); simpl; rewrite IHl; destruct (f x); sp.
Qed.
Theorem eq_list
: forall (A : Type) (x : A) (l1 l2 : list A),
l1 = l2 <=>
length l1 = length l2 # (forall n : nat, nth n l1 x = nth n l2 x).
Proof.
intros. apply eq_lists.
Qed.
Theorem nat_compare_dec: forall m n, (n < m [+] m <= n ).
Proof. induction m. destruct n. right. auto.
right. omega. intros. destruct (IHm n);
destruct (eq_nat_dec n m); subst;
try( left; omega);
try( right; omega).
Qed.
Theorem eq_list2
: forall (A : Type) (x : A) (l1 l2 : list A),
l1 = l2 <=>
length l1 = length l2 # (forall n : nat, n<length l1 -> nth n l1 x = nth n l2 x).
Proof.
intros. split ; introv H.
eapply eq_list in H. repnd. split; auto.
repnd. eapply eq_list; split; eauto.
intros. assert (n < length l1 \/ length l1 <= n ) as Hdic by omega.
destruct Hdic. apply H; auto. repeat (rewrite nth_overflow ); auto.
rewrite <- H0; auto.
Qed.
Lemma singleton_as_snoc :
forall T (x : T),
[x] = snoc [] x.
Proof.
sp.
Qed.
Theorem map_eq_length_eq :
forall A B (f g : A -> B) la1 la2,
map f la1 = map g la2
-> length la1 = length la2.
Proof.
introv Hmap. apply (apply_eq (@length B)) in Hmap.
repeat (rewrite map_length in Hmap); trivial.
Qed.
Theorem nth2 : forall {A:Type} (l:list A) (n:nat) (ev: n < length l) , A .
Proof. induction l; simpl. intros. provefalse.
inversion ev.
intros.
destruct (eq_nat_dec n 0). subst.
exact a.
apply IHl with (n:=(n-1)).
destruct n. destruct n0. reflexivity.
omega.
Qed.
Theorem nth3 : forall {A:Type} (l:list A) (n:nat) (ev: n < length l) , {x:A | nth n l x =x} .
Proof. induction l; simpl. intros. provefalse.
inversion ev.
intros.
destruct n . subst.
exact (exist (eq a) a eq_refl ).
apply IHl with (n:=(n)).
omega.
Qed.
Definition eq_set {A} (l1 l2: list A) := subset l1 l2 # subset l2 l1.
Definition eq_set2 {A} (l1 l2: list A) := forall a , LIn a l1 <=> LIn a l2.
Theorem eq_set_iff_eq_set2 :
forall {A} (l1 l2: list A),
eq_set l1 l2 <=> eq_set2 l1 l2.
Proof.
unfold eq_set, eq_set2, subset.
repeat(split;sp); apply_hyp; auto.
Qed.
Theorem eq_set_refl : forall {A} (l: list A) , eq_set l l.
Proof. split; apply subset_refl.
Qed.
Theorem eq_set_refl2: forall (A : Type) (l1 l2 : list A), (l1=l2) -> eq_set l1 l2.
Proof. intros. rewrite H. apply eq_set_refl.
Qed.
Theorem eq_set_empty :
forall {A} (l1 l2: list A),
eq_set l1 l2
-> l1 = []
-> l2 = [].
Proof.
introv Heqs Heql. apply null_iff_nil. introv v. apply eq_set_iff_eq_set2 in Heqs.
apply Heqs in v. subst. inverts v.
Qed.
Theorem nth2_equiv :
forall (A:Type) (l:list A) (n:nat) (def:A)
(ev: n < length l),
(nth n l def) = nth2 l n ev.
Abort.
Theorem len_flat_map: forall {A B} (f:A->list B) (l: list A),
length (flat_map f l) = addl (map (fun x => length (f x)) l) .
Proof. induction l; auto. simpl. rewrite length_app. f_equal. auto.
Qed.
(** renaming due to some name clash
Lemma rev_list_ind2 :
forall (A : Type) (P : list A -> Prop),
P [] ->
(forall (a : A) (l : list A), P l -> P (snoc l a)) ->
forall l : list A, P l.
Proof.
intros.
assert (texists n, length l = n) by (exists(length l); auto); sp.
revert l H1.
induction n; intros.
destruct l; simpl in H1; auto; inversion H1.
assert (l = [] [+] exists(a : A), exists(k : list A), l = snoc k a) by apply snoc_cases.
sp; subst; auto.
apply H0.
apply IHn.
rewrite length_snoc in H1; inversion H1; auto.
Qed.
*)
Notation no_repeats := NoDup (only parsing).
Theorem last_snoc: forall A (l:list A) (a d:A) ,
nth (length l) (snoc l a) d= a.
Proof.
induction l ; introv . refl.
rewrite snoc_as_append. rewrite app_nth2.
simpl. asserts_rewrite (length l - length l=0); try omega.
auto. omega.
Qed.
Theorem eq_maps2:
forall (A B C: Type) (f : A -> B) (g : C -> B) (la : list A) (lc : list C) defa defc,
length la = length lc
-> (forall n , n < length la -> f (nth n la defa) = g ( nth n lc defc))
-> map f la = map g lc.
Proof. induction la using rev_list_ind; introv Hleq Hp.
invertsn Hleq. symmetry in Hleq. rw length0 in Hleq. subst.
reflexivity. allrewrite snoc_as_append. rewrite map_app.
rewrite length_app in Hleq. allsimpl. rev_list_dest lc. invertsn Hleq.
omega. allrewrite snoc_as_append. rewrite map_app. allsimpl.
rewrite length_app in Hleq. allsimpl.
assert (length la = length u) as Hleq1 by omega.
f_equal. eapply IHla; eauto.
intros. assert (n < length (la++[a])) as Hla. rewrite length_app.
omega. apply Hp in Hla.
rewrite app_nth1 in Hla; auto. rewrite app_nth1 in Hla; auto.
eauto. rewrite <- Hleq1; auto.
instlemma (Hp (length la)) as Hle.
rewrite <- snoc_as_append in Hle.
rewrite <- snoc_as_append in Hle.
rewrite last_snoc in Hle.
rewrite Hleq1 in Hle.
rewrite last_snoc in Hle.
f_equal; auto. apply Hle.
rewrite <- Hleq1.
rewrite length_snoc; omega.
Qed.
(**generalized map where the mapping function takes
evidence of elements being in the list *)
Lemma gmap: forall {A B : Type} (l: list A) (f : forall a, LIn a l -> B),
list B.
Proof. induction l as [| a l maprec]; introv f. exact nil.
pose proof f a as Hb. lapply Hb;[ intro b | left; auto].
assert ( forall a0 : A, LIn a0 (l) -> B) as frec. introv Hin.
eapply f. right. eauto.
pose proof (maprec frec) as brec.
exact (b::brec).
Defined.
Lemma map_gmap_eq : forall {A B : Type} (l: list A)
(f : forall a, LIn a l -> B) (g: A->B),
(forall a (p: LIn a l), f a p = g a)
-> map g l = gmap l f.
Proof. induction l as [| a l Hind]; introv Heq;[reflexivity | ].
simpl. f_equal. rewrite Heq. reflexivity.
apply Hind. intros. rewrite Heq; reflexivity.
Qed.
Fixpoint appl {A: Type} (l: list (list A)) : list A :=
match l with
| [] => []
| h::t => h ++ appl t
end.
Theorem flat_map_as_appl_map:
forall {A B:Type} (f: A->list B) (l : list A),
flat_map f l = appl (map f l).
Proof.
induction l; auto.
simpl. rw IHl; auto.
Qed.
Lemma gmap_length : forall (A B : Type) (l : list A)
(f:(forall a : A, LIn a l -> B)),
length (gmap l f)= length l.
Proof.
induction l; auto.
intros. simpl. f_equal.
rewrite IHl; auto.
Qed.
Lemma map_eq_injective: forall {A B: Type} (f: A->B) (pinj: injective_fun f)
(lvi lvo: list A),
map f lvi = map f lvo -> lvi = lvo.
Proof.
induction lvi as [| vi lvi Hind]; introv Hm; destruct lvo; (try invertsn Hm); auto.
apply pinj in Hm. f_equal; auto.
Qed.
Tactic Notation "cases_if_sum" simple_intropattern(newname) :=
cases_if; clears_last;
let H:= get_last_hyp tt in rename H into newname.
Lemma map_remove_commute: forall {A B : Type} (eqa : Deq A)
(eqb : Deq B) (f: A->B) (r: A) (lvi: list A) (fi : injective_fun f),
map f (@remove _ eqa r lvi)
= @remove _ eqb (f r) (map f lvi).
Proof.
intros. induction lvi; auto.
simpl. symmetry. repeat rewrite decide_decideP. simpl.
cases_if as Ha; cases_if as Hb; subst; sp.
- apply fi in Ha. subst; sp.
- simpl. f_equal; auto.
Qed.
Lemma map_diff_commute: forall {A B : Type} (eqa : Deq A)
(eqb : Deq B) (f: A->B) (lvr lvi: list A) (fi : injective_fun f),
map f (@diff _ eqa lvr lvi)
= @diff _ eqb (map f lvr) (map f lvi).
Proof.
induction lvr as [| ? lvr IHlvr]; intros; try(repeat (rewrite diff_nil)); auto;[].
simpl. rewrite IHlvr; auto. f_equal; auto.
apply map_remove_commute; auto.
Qed.
Lemma memberb_din :
forall (S T : Type)
(deq : Deq S)
(v : S)
(lv : list S)
(ct cf : T),
(if memberb deq v lv then ct else cf)
= (if in_deq _ deq v lv then ct else cf).
Proof.
intros. cases_if as Hb; auto; cases_if_sum Hd ; auto; subst.
apply assert_memberb in Hb. sp.
rw <- (@assert_memberb S deq) in Hd.
rewrite Hd in Hb.
sp.
Qed.
Theorem fst_split_as_map: forall {A B :Type} (sub : list (A * B)),
fst (split sub) = map (fun p=> fst p) sub.
Proof.
intros. induction sub as [| vt sub Hind]; auto.
simpl. destruct vt as [v t].
simpl. destruct (split sub). allsimpl.
f_equal. auto.
Qed.
Theorem snd_split_as_map: forall {A B :Type} (sub : list (A * B)),
snd (split sub) = map (fun p=> snd p) sub.
Proof.
intros. induction sub as [| vt sub Hind]; auto.
simpl. destruct vt as [v t].
simpl. destruct (split sub). allsimpl.
f_equal. auto.
Qed.
Lemma combine_in_right : forall T1 T2 (l2: list T2) (l1: list T1),
(length l2 <= length l1)
-> forall u2, ( LIn u2 l2)
-> {u1 : T1 $ LIn (u1,u2) (combine l1 l2)}.
Proof. induction l2; intros ? Hlen ? Hin. inverts Hin as Hin;
simpl in Hlen.
destruct l1 ; simpl in Hlen. omega. inverts Hin as Hin.
- subst. exists t. simpl. left; auto.
- apply IHl2 with l1 u2 in Hin; auto. parallel u Hcom.
simpl. right; auto. omega.
Qed.
(** nth_error was aleady in the library. *)
Definition select {A:Type} (n:nat) (l:list A): option A :=
nth_error l n.
Lemma nth_select1: forall {A:Type} (n:nat) (l:list A) (def: A),
n < length l -> select n l= Some (nth n l def).
Proof.
induction n as [|n Hind]; introv Hl; destruct l;try (inverts Hl;fail); simpl; auto.
allsimpl. erewrite Hind; eauto. omega.
Qed.
Lemma nth_select2: forall {A:Type} (n:nat) (l:list A) ,
n >= length l <=> select n l= None.
Proof.
induction n as [|n Hind]; destruct l; allsimpl; try (split;sp;omega;fail).
split;intro H.
apply Hind; auto. omega.
apply Hind in H; auto. omega.
Qed.
Lemma first_index {A: Type} (l: list A) (a:A) (deq : Deq A):
{n:nat $ n < length l # nth n l a= a #(forall m, m<n -> nth m l a <>a)}
[+] (! (LIn a l)).
Proof.
induction l as [| h l Hind]; [right;sp;fail|].
destruct (decideP (h=a)); subst; allsimpl;[left ; exists 0; sp; omega | ].
dorn Hind.
+ exrepnd. left. exists (S n0). split; auto; try omega; split; auto.
introv Hlt. destruct m; auto. apply Hind0; omega.
+ right. intro Hc; sp.
Defined.
Lemma split_length_eq: forall {A B :Type} (sub : list (A * B)),
let (la,lb):= split sub in
length la=length lb # length la= length sub.
Proof.
intros. destructr (split sub) as [la lb].
assert(la=fst (la,lb)) as h99 by (simpl;auto).
rewrite h99. rewrite HeqHdeq. rewrite split_length_l. clear h99.
assert(lb=snd (la,lb)) as h99 by (simpl;auto).
rewrite h99. rewrite HeqHdeq. rewrite split_length_r.
sp.
Qed.
Ltac disjoint_reasoning :=
match goal with
| [ |- disjoint _ (_ ++ _) ] => apply disjoint_app_r;split
| [ |- disjoint (_ ++ _) _ ] => apply disjoint_app_l;split
| [ |- disjoint _ (_ :: _) ] => apply disjoint_cons_r;split
| [ |- disjoint (_ :: _) _ ] => apply disjoint_cons_l;split
| [ |- disjoint _ _ ] => (sp;fail || apply disjoint_sym; sp;fail)
(** important to leave it the way it was .. so that repeat progress won't loop*)
| [ H: disjoint _ (_ ++ _) |- _ ] => apply disjoint_app_r in H;sp
| [ H: disjoint (_ ++ _) _ |- _ ] => apply disjoint_app_l in H;sp
| [ H: disjoint _ (_ :: _) |- _ ] => apply disjoint_cons_r in H;sp
| [ H: disjoint (_ :: _) _ |- _ ] => apply disjoint_cons_l in H;sp
| [ H: !(disjoint _ []) |- _ ] => provefalse; apply H; apply disjoint_nil_r
| [ H: !(disjoint [] _) |- _ ] => provefalse; apply H; apply disjoint_nil_l
| [ H: (disjoint _ []) |- _ ] => clear H
| [ H: (disjoint [] _) |- _ ] => clear H
end.
Lemma select_lt : forall {A:Type} (l: list A) (a:A) n,
select n l = Some a -> n < length l.
Proof.
introv Heq.
assert (n<length l \/ n>=length l ) as XX by omega.
dorn XX; auto. apply nth_select2 in XX. rewrite XX in Heq.
inverts Heq.
Qed.
Lemma select_in : forall {A:Type} (l: list A) (a:A) n,
select n l = Some a -> LIn a l.
Proof.
introv Heq. duplicate Heq. apply select_lt in Heq.
pose proof (nth_select1 _ _ a Heq) as XX.
rewrite XX in Heq0. invertsn Heq0.
pose proof (nth_in _ _ l a Heq) as XXX.
auto.
Qed.
Lemma no_repeats_index_unique: forall {T:Type}
(a:T) (n1 n2:nat) (l:list T),
no_repeats l
-> select n1 l = Some a
-> select n2 l = Some a
-> n1 = n2.
Proof.
induction n1 as [| n1 Hind]; introv Hnr H1s H2s; auto; destruct l as [| h l].
inverts H1s.
allsimpl. inverts Hnr. destruct n2; auto.
allsimpl. invertsn H1s.
apply select_in in H2s. sp.
destruct n2; inverts H2s.
allsimpl. destruct n2.
inverts H2s. inverts Hnr. apply select_in in H1s. sp.
f_equal. allsimpl.
apply Hind with (l:=l); eauto.
inverts Hnr; auto.
Qed.
Lemma nth_select3:
forall (A : Type) (n : nat) (l : list A) (a def : A),
n < length l
-> (nth n l def) =a
-> select n l = Some a.
Proof.
introv K1 K2.
pose proof (nth_select1 n l def K1).
congruence.
Qed.
Lemma no_repeats_index_unique2: forall {T:Type} (l:list T)
(a:T) (n1 n2:nat) (def1 def2: T),
no_repeats l
-> n1 < length l
-> n2 < length l
-> (nth n1 l def1 =a)
-> (nth n2 l def2 =a)
-> n1 = n2.
Proof.
introv K1 K2 K3 K4 K5.
apply nth_select3 in K4; auto.
apply nth_select3 in K5; auto.
pose proof (no_repeats_index_unique _ _ _ _ K1 K4 K5). trivial.
Qed.
Lemma length_combine_eq : forall {A B: Type} (la:list A) (lb: list B),
length la =length lb
-> length (combine la lb) = length la.
Proof.
introv XX. rewrite combine_length.
rewrite XX. apply Min.min_idempotent.
Qed.
Lemma nth_in2:
forall (A : Type) (n : nat) (l : list A) (a d : A),
n < length l -> (nth n l d) = a -> LIn a l.
Proof.
introns XX. pose proof (nth_in _ n l d XX) as XY. congruence.
Qed.
Definition not_in_prefix {A: Type} (la : list A) (a:A) (n:nat) :=
(forall m : nat,
m < n -> nth m la a <> a).
Definition lforall {A:Type} (P: A-> [univ]) (l:list A) :=
forall a:A, LIn a l -> P a.
Lemma implies_lforall : forall {A:Type} (P Q: A->[univ]),
(forall (a b :A), P a -> Q a)
-> forall l, lforall P l-> lforall Q l.
Proof.
unfold lforall. sp.
Defined.
Lemma lforall_subset : forall {A:Type} (P: A->[univ]) (la lb : list A),
subset la lb
-> lforall P lb
-> lforall P la.
Proof.
unfold lforall, subset.
firstorder.
Qed.
(* for an application, see alphaeq.change_bvars_alpha_spec_varclass *)
Lemma lforall_flatmap : forall {A B :Type} (P: B->[univ]) (fa fb : A -> list B) (la: list A),
(forall a, LIn a la -> lforall P (fa a) -> lforall P (fb a) )
-> lforall P (flat_map fa la)
-> lforall P (flat_map fb la).
Proof.
unfold lforall, subset.
setoid_rewrite in_flat_map.
intros.
firstorder.
eauto.
Qed.
Lemma lforallApp : forall {A:Type} (lv1 lv2 :list A) P,
lforall P (lv1++lv2)
<-> ((lforall P lv1) # (lforall P lv2)).
Proof using.
unfold lforall.
setoid_rewrite in_app_iff.
firstorder.
Qed.
Lemma combine_eq : forall {A B: Type}
(l1a l2a: list A) (l1b l2b: list B),
combine l1a l1b = combine l2a l2b
-> length l1a = length l1b
-> length l2a = length l2b
-> l1a=l2a # l1b=l2b.
Proof.
induction l1a as [|a1 l1a Hind]; auto; introv Hc He1 He2;
allsimpl; destruct l1b; destruct l2b; destruct l2a;
try(invertsn He1); try(invertsn He2); allsimpl; try(invertsn Hc); auto.
pose proof (Hind _ _ _ Hc He1 He2) as Xr. repnd.
rewrite Xr. rewrite Xr0; split; sp.
Qed.
Definition binrel_list {T}
(def : T)
(R : @bin_rel T)
(tls trs : list T) : [univ] :=
length tls = length trs
# (forall (n : nat),
n < length tls
-> R (nth n tls def) (nth n trs def)).
Lemma length2 :
forall (T : Type) (l : list T),
length l = 2 -> {x, y : T $ l = [x,y]}.
Proof.
introv Hl. destruct l; try(destruct l); try(destruct l); inverts Hl.
eexists; eauto.
Qed.
Lemma length3 :
forall (T : Type) (l : list T),
length l = 3 -> {x, y, z : T $ l = [x,y,z]}.
Proof.
introv Hl. destruct l; try(destruct l); try(destruct l); try(destruct l); inverts Hl.
repeat(eexists); eauto.
Qed.
Lemma length4 :
forall (T : Type) (l : list T),
length l = 4 -> {x, y, z , u : T $ l = [x,y,z,u]}.
Proof.
introv Hl. destruct l; try(destruct l); try(destruct l);
try(destruct l); try(destruct l); inverts Hl.
repeat(eexists); eauto.
Qed.
Definition is_first_index {T:Type} (l: list T) (t:T) (n:nat) :=
n< length l # nth n l t = t # not_in_prefix l t n.
Lemma is_first_index_unique : forall {T:Type} (l: list T) (t:T) (n1 n2 :nat),
is_first_index l t n1
-> is_first_index l t n2
-> n1 = n2.
Proof.
unfold is_first_index, not_in_prefix. introv s1s s3s.
repnd.
assert (n1<n2 \/ n1=n2 \/ n2<n1) as Htri by omega.
(dorn Htri);[|(dorn Htri)]; sp;
try (apply s1s in Htri); sp;
try (apply s3s in Htri); sp.
Qed.
Lemma disjoint_app_lr : forall {A:Type} (l1 l2 r1 r2 : list A),
disjoint (l1 ++ l2) (r1 ++ r2)
<=>
(disjoint l1 r1 # disjoint l1 r2) # disjoint l2 r1 # disjoint l2 r2.
Proof.
introv. rw disjoint_app_l. rw disjoint_app_r.
rw disjoint_app_r. apply t_iff_refl.
Qed.
Definition decide_disjoint {T:Type} {deqt: Deq T} (la lb: list T) : bool :=
ball (List.map (fun x=>negb (memberb _ x lb)) la).
Lemma dec_disjoint :
forall {T:Type} (deqt: Deq T) (la lb: list T),
disjoint la lb + (!disjoint la lb).
Proof.
induction la as [|a la IHla]; sp.
simpl. destruct (IHla lb) as [dd|nd];[|right].
- destruct (in_deq T deqt a lb);[right|left];sp;disjoint_reasoning;sp.
- sp. apply nd. disjoint_reasoning; sp.
Defined.
Lemma decide_disjoint_correct {T:Type} {deqt: Deq T} (la lb: list T) :
isInl (dec_disjoint _ la lb) = decide_disjoint la lb.
Proof using.
induction la as [|a la IHla]; sp.
unfold decide_disjoint. simpl.
setoid_rewrite <- IHla. clear IHla.
destruct (dec_disjoint deqt la lb); sp;[| simpl; rewrite andb_false_r; refl].
unfold negb.
rewrite memberb_din.
simpl.
destruct (in_deq T deqt a lb); refl.
Qed.
Lemma decide_disjoint_ite:
forall (S T : Type) (deq : Deq S) (la lb : list S) (ct cf : T),
(if dec_disjoint deq la lb then ct else cf) =
(if decide_disjoint la lb then ct else cf).
Proof.
intros.
rewrite <- decide_disjoint_correct.
destruct (dec_disjoint deq la lb); refl.
Qed.
Global Instance decideDisjoint {T:Type} {deqt: Deq T} (la lb: list T)
: Decidable (disjoint la lb).
exists (decide_disjoint la lb).
rewrite <- decide_disjoint_correct.
destruct (dec_disjoint deqt la lb); simpl; firstorder.
Defined.
Ltac simpl_list :=
match goal with
| [ H : context[length (map _ _)] |- _] => rewrite map_length in H
| [ |- context[length (map _ _)] ] => rewrite map_length
| [ H : LIn ?x [?h] |- _ ] => apply in_single in H; subst
end.
Lemma bin_rel_list_refl :
forall {T} (R: bin_rel T) (def:T),
refl_rel R -> refl_rel (binrel_list def R).
Proof.
introv HR. intro l. split; sp.
Qed.
Lemma pairInProofsCons :
forall {A:Type} (l: list A) (h:A),
{a: A $ LIn a l}
-> {a: A $ LIn a (h::l)}.
Proof.
introv ph. exrepnd.
exists a.
right. trivial.
Defined.
Lemma pairInProofs: forall {A:Type} (l: list A) , list {a: A $ LIn a l}.
Proof.
induction l as [| a l Hind];[exact []|].
pose proof (map (pairInProofsCons l a) Hind) as Hind'.
exact (exI(a,injL(eq_refl a))::Hind').
Defined.
Theorem in_single_iff: forall T (a b : T), LIn a [b] <=> a=b.
Proof. split.
- introv H. invertsn H. auto. inversion H.
- introv H. constructor. sp.
Qed.
Lemma lin_lift: forall {A B:Type} (a:A) (lv: list A) (f:A->B),
LIn a lv -> LIn (f a) (map f lv).
Proof.
induction lv as [| v lv Hind] ; [sp | ]; introv Hin. simpl.
dorn Hin;subst;spc.
Qed.
Lemma flat_map_app:
forall (A B : Type) (f : A -> list B) (l l' : list A),
flat_map f (l ++ l') = flat_map f l ++ flat_map f l'.
Proof.
induction l as [| a l Hind]; introv;sp.
simpl. rw <- app_assoc.
f_equal. sp.
Qed.
Hint Resolve deq_list.
Ltac get_element_type listtype :=
match listtype with
list ?T => T
end.
Ltac apply_length H :=
match goal with
[ H: (?l = ?r) |- _ ] =>
let T:= (type of l) in
let Tin := get_element_type T in
let Hn := fresh H "len" in
apply_eq (@length Tin) H Hn; try (rw map_length in Hn)
end.
Lemma filter_app :
forall T f (l1 l2 : list T),
filter f (l1 ++ l2) = filter f l1 ++ filter f l2.
Proof.
induction l1; simpl; sp.
rw IHl1.
destruct (f a); sp.
Qed.
Lemma subset_singleton_r :
forall T (l : list T) x,
subset l [x] <=> forall y, LIn y l -> y = x.
Proof.
unfold subset; introv; simpl; split; sp; apply_in_hyp p; sp.
Qed.
Lemma split_eta :
forall A B (l : list (A * B)),
split l = (fst (split l), snd (split l)).
Proof.
induction l; simpl; sp.
rw IHl; simpl; sp.
Qed.
Lemma split_cons :
forall A B a b (l : list (A * B)),
split ((a, b) :: l) = (a :: fst (split l), b :: (snd (split l))).
Proof.
simpl; sp.
rw split_eta; simpl; sp.
Qed.
Lemma simpl_fst :
forall A B (a : A) (b : B), fst (a, b) = a.
Proof. sp. Qed.
Fixpoint gmapd {A B : Type} (l : list A) : (forall a, LIn a l -> B) -> list B :=
match l with
| [] => fun f => []
| x :: xs =>
fun (f : forall a, LIn a (x::xs) -> B) =>
(f x (injL(eq_refl))) :: gmapd xs (fun a i => f a (injR(i)))
end.
Lemma gmap_eq_d :
forall A B (l : list A) (f : forall a : A, LIn a l -> B),
gmap l f = gmapd l f.
Proof.
induction l; simpl; sp.
rw IHl; sp.
Qed.
Lemma eq_gmaps :
forall A B,
forall l : list A,
forall f g : (forall a : A, LIn a l -> B),
(forall a (i : LIn a l), f a i = g a i)
-> gmap l f = gmap l g.
Proof.
induction l; simpl; sp.
generalize (H a (injL(eq_refl))); intro e.
rewrite e.
apply cons_eq; sp.
Qed.
Lemma eq_gmapds :
forall A B,
forall l : list A,
forall f g : (forall a : A, LIn a l -> B),
(forall a (i : LIn a l), f a i = g a i)
-> gmapd l f = gmapd l g.
Proof.
intros.
repeat (rw <- gmap_eq_d).
apply eq_gmaps; sp.
Qed.
Lemma combine_cons :
forall A B (x : A) (y : B) l k,
combine (x :: l) (y :: k) = (x, y) :: combine l k.
Proof. sp. Qed.
Lemma map_cons :
forall A B (x : A) (f : A -> B) l,
map f (x :: l) = (f x) :: map f l.
Proof. sp. Qed.
Lemma Lin_eauto1 : forall {T:Type} (a:T) (l: list T),
LIn a (a::l).
Proof.
intros. simpl. left; sp.
Qed.
Lemma Lin_eauto2 : forall {T:Type} (a b:T) (l: list T),
LIn b l -> LIn b (a::l).
Proof.
intros. simpl. right; sp.
Qed.
Hint Resolve Lin_eauto1 Lin_eauto2 : slow.
Ltac disjoint_lin_contra :=
match goal with
[ H1 : LIn ?t ?lv1 , H2 : LIn ?t ?lv2, H3 : (disjoint ?lv1 ?lv2) |- _ ]
=> apply H3 in H1; sp ; fail
| [ H1 : LIn ?t ?lv1 , H2 : LIn ?t ?lv2, H3 : (disjoint ?lv2 ?lv1) |- _ ]
=> apply H3 in H1; sp ;fail
end.
Lemma in_nth3 :
forall T a def (l:list T),
LIn a l
-> {n : nat $ (n < length l) # a = nth n l def}.
Proof.
introv Hin. apply in_nth in Hin.
exrepnd.
exists n.
dands; sp.
rewrite nth_indep with (d':=a); sp.
Qed.
Lemma le_binrel_list_un : forall {T:Type} (def : T)
(R: @bin_rel T) (Rul Rur: T -> [univ]),
le_bin_rel R (indep_bin_rel Rul Rur)
-> forall (la lb : list T), binrel_list def R la lb
-> (forall x:T , LIn x la -> Rul x) # (forall x:T , LIn x lb -> Rur x).
Proof.
introv Hle Hb. repnud Hle. repnud Hb. unfold indep_bin_rel in Hle.
split;
introv Hin; apply in_nth3 with (def:=def) in Hin; exrepnd;
subst; dimp (Hb n); spc;
apply Hle in hyp; sp.
Qed.
Lemma binrel_list_nil : forall {T : Type } R (def :T ), binrel_list def R nil nil.
Proof.
introv. split;[sp | introv Hlt; simpl in Hlt; omega].
Qed.
Tactic Notation "spcf" :=
try(spc;fail).
Lemma binrel_list_cons : forall {T : Type} R (def a b :T ) ta tb,
(binrel_list def R ta tb # R a b)
<=> (binrel_list def R (a::ta) (b :: tb)).
Proof.
split; introv hyp; unfold binrel_list in hyp; unfold binrel_list.
- repnd.
simpl. dands;spcf;[]. introv Hlt. destruct n; spc.
dimp (hyp0 n); spc; omega.
- allsimpl. repnd. dands ;spcf.
+ introv Hlt. dimp (hyp (S n));sp; omega.
+ dimp (hyp 0); spc; omega.
Qed.
Lemma in_combine_left_eauto :
forall (A B : Type) a b,
forall l1 : list A,
forall l2 : list B,
LIn (a,b) (combine l1 l2)
-> LIn a l1.
Proof.
introv Hin. apply in_combine in Hin; spc.
Qed.
Ltac in_reasoning :=
match goal with
| [ H : context [LIn _ [_]] |- _] => trw_h in_single_iff H
| [ H : LIn _ (_::_) |- _ ] => simpl in H
| [ H : LIn _ (_++_) |- _ ] => apply in_app_iff
| [ H : _ [+] _ |- _] => destruct H as [H | H]
end.
Lemma in_combine_right_eauto :
forall (A B : Type) a b,
forall l1 : list A,
forall l2 : list B,
LIn (a,b) (combine l1 l2)
-> LIn b l2.
Proof.
introv Hin. apply in_combine in Hin; spc.
Qed.
Ltac dLin_hyp :=
repeat
match goal with
| H:forall x : ?T, ?L = x \/ ?R -> ?C
|- _ =>
let Hyp := fresh "Hyp" in
pose proof (H L (or_introl eq_refl)) as Hyp; specialize (fun x y => H x (or_intror y))
| H:forall x y, _ = _ \/ ?R -> ?C
|- _ =>
let Hyp := fresh "Hyp" in
pose proof (H _ _ (or_introl eq_refl)) as Hyp; specialize
(fun x z y => H x z (or_intror y))
| H:forall x : ?T, False -> _ |- _ => clear H
end.
Ltac dlist_len_name ll name :=
repeat match goal with
[ H : length ll = _ |- _ ]=> symmetry in H
|[ H : 0 = length ll |- _ ] => destruct ll; inversion H
|[ H : S _ = length ll |- _ ] =>
let ename:= fresh name in
destruct ll as [| ename ll]; simpl in H; inverts H
|[ H : 0 = length [] |- _ ] => clear H
end.
Ltac dlist_len ll := dlist_len_name ll ll.
Ltac dlists_len :=
repeat match goal with
|[ H : 0 = length ?ll |- _ ] => dlist_len ll
|[ H : S _ = length ?ll |- _ ] => dlist_len ll
end.
Hint Resolve in_combine_left_eauto : slow.
Hint Resolve in_combine_right_eauto : slow.
Ltac destFind := match goal with
[ |- context[find ?s ?v]] =>
let sns := fresh v "s" in
remember (find s v) as sn;
let H := get_last_hyp tt in
let H' := fresh H "l" in
(destruct sn as [sns |];
symmetry in H;
try (pose proof (@find_some _ _ _ _ H) as H');
try (pose proof (@find_none _ _ _ H) as H'))
end.
Lemma no_repeats_as_disjoint : forall {A} (h:A) t,
no_repeats (h::t)
-> disjoint [h] t /\ no_repeats t.
Proof.
intros ? ? ? Hnr.
inverts Hnr.
split; auto.
intros ?. rewrite in_single_iff. intro H.
subst. assumption.
Qed.
Lemma repeat_map_len : forall A B (b:B) (vs: list A) ,
map (fun _ => b) vs = repeat b (Datatypes.length vs).
Proof.
induction vs; auto; simpl; f_equal; auto.
Qed.
Lemma map_eq_repeat_implies : forall A B (b:B) f (vs: list A) n,
map f vs = repeat b n
-> forall v, LIn v vs -> f v = b.
Proof.
induction vs; intros; [simpl in *; tauto|].
applydup (f_equal (@length B)) in H.
rewrite repeat_length in H1.
simpl in *. destruct n;[omega|].
simpl in *. inverts H. in_reasoning; subst; eauto.
Qed.
Lemma list_find_same_compose {A B: Type} (f : A -> bool)
(h : A -> B) (g : B -> bool) :
(forall a, (compose g h) a = f a)
-> forall (s1 def: A) (l1 l2: list A) ,
(map h l1 = map h l2)
-> find f l1 = Some s1
-> exists n, n < length l2 /\ find f l2 = Some (nth n l2 def)
/\ s1 = nth n l1 def /\ f s1 = true /\ f (nth n l2 def) = true.
Proof.
intros Hc ? ? ?.
induction l1 as [|h1 t1]; intros ? Hm Hf;
destruct l2 as [|h2 t2]; inverts Hm as Hm;[inverts Hf|].
specialize (IHt1 _ H2). clear H2.
simpl in *.
apply (f_equal g) in Hm.
setoid_rewrite Hc in Hm.
rewrite <- Hm.
remember (f h1) as fh.
destruct fh.
- inverts Hf. exists 0. split; auto. omega.
- apply_clear IHt1 in Hf. exrepnd. exists (S n).
split; auto. omega.
Qed.
Lemma find_map_same_compose2 {A B: Type} (f : A -> bool)
(h : A -> B) (g : B -> bool) :
(forall a, (compose g h) a = f a)
-> forall (l: list A),
find g (map h l) = option_map h (find f l).
Proof.
intros Hc ?.
induction l; auto;
simpl in *. unfold compose in Hc.
rewrite Hc.
destruct (f a); auto.
Qed.
Lemma find_ext {A: Type} (f g : A -> bool) (l: list A):
(forall a, f a= g a) -> (find f l= find g l).
Proof.
intros Heq. induction l; auto; simpl in *.
rewrite Heq.
cases_if; eauto.
Qed.
Lemma find_map_same_compose {A B: Type} (f : A -> bool)
(h : A -> B) (g : B -> bool) :
(forall a, (compose g h) a = f a)
-> forall (s : A) (l: list A),
find f l = Some s
-> find g (map h l) = Some (h s).
Proof.
intros. erewrite find_map_same_compose2; eauto.
rewrite H0. refl.
Qed.
Lemma combine_map {A B C: Type} (f:A->B) (g: A->C) (la:list A):
combine (map f la) (map g la)
= map (fun x => (f x, g x)) la.
Proof.
induction la; simpl; congruence.
Qed.
Lemma iff_t_iff : forall A B : Prop, A <-> B <-> (A <=> B).
Proof.
firstorder.
Qed.
Lemma eqsetv_prop {A}:
forall (vs1 vs2 : list A),
eq_set vs1 vs2 <=> forall x, LIn x vs1 <=> LIn x vs2.
Proof.
sp.
unfold subset. firstorder.
Qed.
Lemma eqsetv_sym {A} :
forall (s1 s2 : list A), eq_set s1 s2 <=> eq_set s2 s1.
Proof.
introv. unfold eq_set. tauto.
Qed.
Lemma eqsetv_disjoint {A}:
forall (s1 s2 s3 : list A),
eq_set s1 s2
-> disjoint s1 s3
-> disjoint s2 s3.
Proof.
unfold disjoint, subset.
firstorder.
Qed.
Lemma eqsetv_trans {A}: forall (lva lvb lvc : list A),
eq_set lva lvb
-> eq_set lvb lvc
-> eq_set lva lvc.
Proof.
introv He1 He2.
rewrite (eqsetv_prop) in *.
split; intro Hin;
repeat (try(apply He1 in Hin); try(apply He2 in Hin); auto).
Qed.
Lemma eq_vars_sym {A}: forall (lv1 lv2 : list A),
eq_set lv1 lv2 -> eq_set lv2 lv1.
Proof.
introv. rewrite eqsetv_prop. rewrite eqsetv_prop.
intros X x. rw X.
dtiffs2. split; auto.
Qed.
Notation lremove := diff.
Lemma subset_flat_map_r {A B:Type} (f: A-> list B): forall la a,
LIn a la-> subset (f a) (flat_map f la).
Proof.
intros ? ? Hin1 ? Hin2.
apply in_flat_map; eauto.
Qed.
Global Instance subsetRefl {A} : Reflexive (@subset A).
Proof.
eauto.
Qed.
Global Instance subsetTrans {A} : Transitive (@subset A).
Proof.
intros ? ? ? ? ?. eapply subset_trans; eauto.
Qed.
Global Instance equivEqsetv {A}: Equivalence (@eq_set A).
Proof.
constructor; eauto using eqsetv_trans, eq_vars_sym.
constructor; unfold subset; tauto.
Qed.
(* Require Import Morphisms. *)
Global Instance properEqsetvLin {A} : Proper (eq ==> eq_set ==> iff ) (@LIn A).
Proof.
intros ? ? ? ? ? ?. apply iff_t_iff. subst. apply eqsetv_prop; assumption.
Qed.
Global Instance properEqsetvNull {A} : Proper (eq_set ==> iff ) (@null A).
Proof.
intros ? ? H. unfold null. split; intros; [rewrite <- H| rewrite H]; eauto.
Qed.
Global Instance properEqsetvApp {A}: Proper (eq_set ==> eq_set ==> eq_set ) (@app A).
Proof.
intros ? ? H1 ? ? H2. apply eqsetv_prop. setoid_rewrite in_app_iff.
setoid_rewrite H1. setoid_rewrite H2. tauto.
Qed.
Global Instance properEqsetvRemove {A:Type} `{Deq A}: Proper (eq_set ==> eq_set ==> eq_set) (@lremove A _).
Proof.
intros ? ? H1 ? ? H2. apply eqsetv_prop.
setoid_rewrite in_diff.
setoid_rewrite H1. setoid_rewrite H2. tauto.
Qed.
Global Instance properEqsetvSubsetv {A} : Proper (eq_set ==> eq_set ==> iff ) (@subset A).
Proof.
intros ? ? ? ? ? Heq. subst. apply iff_t_iff. unfold subset.
repeat setoid_rewrite Heq. setoid_rewrite H. reflexivity.
Qed.
Global Instance transSubsetv {A}: Transitive (@subset A).
Proof.
intros ? ? ?. apply subset_trans.
Qed.
(* TODO : generalize over P*)
Global Instance properEqsetvlforall {A} P : Proper (eq_set ==> iff ) (@lforall A P).
Proof.
intros ? ? Heq. unfold lforall. setoid_rewrite Heq.
refl.
Qed.
Global Instance proper_memberb {A:Type} `{Deq A} :
Proper (eq ==> eq_set ==>eq) (@memberb A _).
Proof.
intros ? ? ? ? ? ?.
pose proof (@proper_decider2 A _ (@LIn A) eq eq_set in_deqq properEqsetvLin).
simpl in H2.
apply H2; auto.
Qed.
Lemma flat_map_monotone:
forall (A B : Type) (f : A -> list B) (la lb : list A),
subset la lb -> subset (flat_map f la) (flat_map f lb).
Proof.
intros.
rewrite subset_flat_map.
intros ? Hin.
apply subset_flat_map_r.
auto.
Qed.
Lemma map_monotone:
forall (A B : Type) (f : A -> B) (la lb : list A),
subset la lb -> subset (map f la) (map f lb).
Proof.
intros.
unfold subset in *.
setoid_rewrite in_map_iff.
firstorder.
Qed.
Lemma flat_map_fapp:
forall {A B : Type} (f g : A -> list B) (l : list A),
eq_set
(flat_map (fun x => (f x) ++ (g x)) l)
((flat_map f l) ++ (flat_map g l)).
Proof.
intros.
apply eqsetv_prop. repeat setoid_rewrite in_app_iff.
repeat setoid_rewrite in_flat_map.
setoid_rewrite in_app_iff.
firstorder.
Qed.
Global Instance properDisjoint {A} : Proper (eq_set ==> eq_set ==> iff ) (@disjoint A).
Proof.
intros ? ? ? ? ? Heq. subst. apply iff_t_iff. unfold disjoint.
repeat setoid_rewrite Heq. setoid_rewrite H. reflexivity.
Qed.
Lemma subsetvAppLR {A} : forall a b c d,
subset a c
-> subset b d
-> @subset A (a++b) (c++d).
Proof.
intros ? ? ? ? H1s H2s.
apply app_subset.
split; eauto using subset_app_l, subset_app_r.
Qed.
Lemma eqset_flat_maps
: forall (A B : Type) (f g : A -> list B) (l : list A),
(forall x : A, LIn x l -> eq_set (f x) (g x))
-> eq_set (flat_map f l) (flat_map g l).
Proof.
induction l; intros; simpl; [refl|].
rewrite H;[| sp].
simpl in *.
rewrite IHl;[| spc].
refl.
Qed.
Lemma disjoint_sym_eauto
: forall (T : Type) (l1 l2 : list T), disjoint l1 l2 -> disjoint l2 l1.
Proof using.
intros. apply disjoint_sym. assumption.
Qed.
Lemma eqset_app_comm : forall {A} (a b: list A),
eq_set (a++b) (b++a).
Proof using.
intros ? ? ?. rewrite eqsetv_prop. intro. repeat rewrite in_app_iff.
tauto.
Qed.
Global Instance properNil {A}: Proper (eq_set ==> iff) (@eq (list A) nil).
Proof using.
intros ? ? H. rewrite eqsetv_prop in H.
split; intros Hh; subst; simpl in H; firstorder;[destruct y | destruct x]; simpl in *;
try tauto; specialize (H a); try tauto.
Qed.
(* allows rewriting in maps using functional extensionality *)
Global Instance properMapExt {A B}: Proper ((eq ==> eq) ==> eq ==> eq) (@map A B).
Proof.
intros ? ? H1 ? ? H2. subst. apply eq_maps.
auto.
Qed.
(* maps on lists interpreted as bags *)
Global Instance properEquivMap {A B}: Proper ((eq ==> eq) ==> eq_set ==> eq_set) (@map A B).
Proof.
intros f g H1 ? ? H2.
apply eqsetv_prop.
setoid_rewrite in_map_iff.
intros.
setoid_rewrite H2.
firstorder; subst; eexists; split; eauto; try apply H1.
symmetry. apply H1. auto.
Qed.
(* flat_maps on lists interpreted as bags *)
Global Instance properEquivFlatMap {A B}: Proper ((eq ==> eq_set) ==> eq_set ==> eq_set) (@flat_map A B).
Proof.
intros f g H1 ? ? H2.
apply eqsetv_prop.
setoid_rewrite in_flat_map.
intros.
setoid_rewrite H2.
firstorder; subst; eexists; split; eauto; try apply H1.
Qed.
Lemma subsetv_nil_r {A}:
forall vs,
@subset A vs [] <=> vs = [].
Proof.
introv; split; intro k; allrw; sp.
unfold subset in *.
apply null_iff_nil.
unfold null; introv i.
discover; sp.
Qed.
Hint Rewrite @subsetv_nil_r : SquiggleEq.
Lemma disjoint_neq_iff {A} {a b : A} :
disjoint [a] [b]
<-> a <> b.
Proof using.
split; intros; simpl in *;
repeat disjoint_reasoning;
simpl in *;
tauto.
Qed.
Lemma disjoint_neq {A} {a b : A} :
disjoint [a] [b]
-> a <> b.
Proof using.
intros Hd.
intros Hc.
subst.
repeat disjoint_reasoning.
simpl in *.
tauto.
Qed.
Hint Resolve @subset_flat_map_r : subset.
Lemma combine_map_fst2 {A B}: forall la lb,
length la <= length lb
-> la = map fst (@combine A B la lb).
Proof.
induction la; auto;[].
simpl. intros lb Hle.
destruct lb;[ inverts Hle |].
simpl in *. apply le_S_n in Hle.
f_equal; auto.
Qed.
Lemma combine_map_fst {A B}: forall la lb,
length la = length lb
-> la = map fst (@combine A B la lb).
Proof.
intros ? ? Hl.
apply combine_map_fst2. rewrite Hl. reflexivity.
Qed.
Lemma combine_map_snd2 {A B}: forall lb la,
length lb <= length la
-> lb = map snd (@combine A B la lb).
Proof.
induction lb; auto;
simpl; intros la Hle; try rewrite combine_nil; auto.
destruct la;[ inverts Hle |].
simpl in *. apply le_S_n in Hle.
f_equal; auto.
Qed.
Lemma combine_map_snd {A B}: forall la lb,
length la = length lb
-> lb = map snd (@combine A B la lb).
Proof.
intros ? ? Hl.
apply combine_map_snd2. rewrite Hl. reflexivity.
Qed.
Fixpoint seq {T:Type} (next: T->T) (start : T) (len : nat) {struct len} : list T :=
match len with
| 0 => []
| S len0 => start :: seq next (next start) len0
end.
Fixpoint fn {A:Type} (f: A->A) (n:nat) : A -> A :=
match n with
| O => id
| S n' => compose (fn f n') f
end.
Lemma fn_shift2 {A B:Type} (fa: A->A) (fb : B -> B) (ab : A -> B) :
(forall a, ab (fa a) = fb (ab a))
-> forall x start,
fn fb x (ab start) = ab (fn fa x start).
Proof using.
induction x; auto.
simpl. unfold compose. intros.
congruence.
Qed.
Lemma fn_shift {A:Type} (f: A->A) : forall x start,
fn f x (f start) = f (fn f x start).
Proof using.
induction x; auto.
simpl. unfold compose. auto.
Qed.
Lemma seq_spec {A:Type} (f: A->A) :
forall (len:nat) (start:A),
(seq f start len) = map (fun n => (fn f n) start) (List.seq 0 len).
Proof using Type.
induction len; intros ?; auto.
simpl. f_equal. rewrite <- seq_shift.
rewrite map_map. unfold compose. simpl.
eauto.
Qed.
Lemma seq_map {A B:Type} (fa: A->A) (fb : B -> B) (ab : A -> B) :
(forall a, ab (fa a) = fb (ab a))
->
forall (len:nat) (start:A),
(seq fb (ab start) len) = map ab (seq fa start len).
Proof using Type.
intros.
do 2 rewrite seq_spec.
rewrite map_map. unfold compose.
apply eq_maps.
intros ? _.
apply fn_shift2. assumption.
Qed.
Lemma seq_shift {A:Type} (f: A->A) :
forall (len:nat) (start:A),
(seq f (f start) len) = map f (seq f start len).
Proof using Type.
intros.
do 2 rewrite seq_spec.
rewrite map_map. unfold compose.
apply eq_maps.
intros ? _.
apply fn_shift.
Qed.
Lemma seq_length A (f:A->A) n x : length (seq f x n) = n.
Proof using.
intros.
rewrite seq_spec, map_length, seq_length. refl.
Qed.
Require Import Psatz.
Lemma NoDupInjectiveMap {A B : Type} (f:A->B) :
injective_fun f
-> forall l, NoDup l -> NoDup (map f l).
Proof.
intros Hin. induction l; [simpl; constructor |].
intros Hnd. inversion Hnd.
simpl. constructor; auto.
intros Hl.
apply in_map_iff in Hl. subst.
exrepnd.
apply Hin in Hl0.
subst. contradiction.
Qed.
Lemma fn_plusN : forall (n:nat) (m:N), (fn N.succ n) m = ((N.of_nat n) + m)%N.
Proof using Type.
induction n; auto.
intros.
rewrite Nnat.Nat2N.inj_succ. simpl.
unfold compose. simpl.
rewrite IHn.
lia.
Qed.
Lemma in_seq_Nplus : forall len (start n : N),
LIn n (seq N.succ start len) <-> (start <= n /\ n < start + N.of_nat len)%N.
Proof using.
intros.
rewrite seq_spec.
rewrite in_map_iff.
setoid_rewrite fn_plusN.
setoid_rewrite in_seq.
split; intro H.
- exrepnd. lia.
- repnd. exists (N.to_nat (n-start)).
lia.
Qed.
Definition maxlp : (list positive) -> positive -> positive :=
fold_left Pos.max.
Lemma maxlp_le2 : forall lp p1 p2,
(p1 <= p2 -> maxlp lp p1 <= maxlp lp p2)%positive.
Proof using.
induction lp; auto.
intros ? ? Hle. simpl.
apply IHlp.
apply Pos.max_le_compat_r. assumption.
Qed.
(* using MathClasses, this lemma can be stated more generally *)
Lemma maxlp_le : forall x lp p,
(In x (p::lp) -> x <= maxlp lp p)%positive.
Proof.
induction lp; intros ? Hin.
- apply in_single_iff in Hin. subst. reflexivity.
- simpl in *. dorn Hin;[| dorn Hin]; subst; auto.
+ eapply transitivity;[apply IHlp; left; refl | apply maxlp_le2, Pos.le_max_l].
+ eapply transitivity;[apply IHlp; left; refl | apply maxlp_le2, Pos.le_max_r].
Qed.
Lemma select_map {A B}: forall (f: A->B) la n a,
select n la = Some a
-> select n (map f la) = Some (f a).
Proof using.
induction la; simpl;destruct n; introv H; simpl in *; try congruence.
auto.
Qed.
Lemma move_snd_out {A B C}: forall (p: A*B) (f : B->C),
f (snd p) = snd ((fun x => (fst x, f (snd x))) p).
Proof using.
intros. destruct p. refl.
Qed.
Hint Resolve flat_map_monotone map_monotone : subset.
Lemma combineeq {A}: forall la lb,
@length A la = length lb
-> (forall x y, LIn (x,y) (combine la lb) -> x=y)
-> la = lb.
Proof.
induction la; intros ? Hl Hin; simpl in *; dlist_len_name lb b;[refl|].
simpl in *.
dLin_hyp. simpl in *. subst.
f_equal; auto.
Qed.
Lemma list_pair_ext {A B} : forall (la lb : list (A *B)),
map fst la = map fst lb
-> map snd la = map snd lb
-> la = lb.
Proof.
induction la as [| a la Hind]; intros ? H1m H2m; destruct lb as [| b lb]; inverts H1m; auto.
inverts H2m. destruct a. destruct b.
simpl in *. subst.
f_equal. auto.
Qed.
Lemma eqset_repeat {A B} la (lb: list B) :
la <> []
-> eq_set (flat_map (fun _ : A => lb) la) lb.
Proof.
intros ?. apply eqsetv_prop.
intros.
rewrite in_flat_map.
destruct la; [ congruence|]. simpl.
firstorder.
eexists; split; eauto.
Qed.
Lemma repeat_nil {A B} la :
(flat_map (fun _ : A => []) la) = @nil B.
Proof.
induction la; auto.
Qed.
Hint Rewrite @repeat_nil : SquiggleEq.
Ltac rwsimpl He1 :=
repeat progress (autorewrite with list core SquiggleEq in He1; simpl in He1).
Ltac rwsimplAll :=
repeat progress (autorewrite with list core SquiggleEq in *; simpl in *).
Ltac rwsimplC :=
repeat progress (autorewrite with list core SquiggleEq; simpl).
Lemma disjoint_map {A B} (f:A->B) (l1 l2: list A):
disjoint (map f l1) (map f l2)
-> disjoint l1 l2.
Proof using.
intros Hd.
intros ? Hin.
apply (in_map f) in Hin.
apply Hd in Hin.
intros Hc. apply Hin. apply in_map. assumption.
Qed.
Lemma nodup_map {A B} (f:A->B) (l: list A):
NoDup (map f l)
-> NoDup l.
Proof using.
induction l;
intros Hd; [ constructor |].
inverts Hd as Hin Hinb. constructor; auto.
clear Hinb IHl. intros Hc. apply Hin. apply in_map. assumption.
Qed.
(* Move to Coq.Lists.List ? *)
Lemma seq_add : forall n m s,
List.seq s (n+m) = (List.seq s n)++(List.seq (s+n) m).
Proof using.
intros ?. induction n; simpl; intros m s;
[ rewrite <- plus_n_O; reflexivity | ].
f_equal. rewrite IHn. f_equal. simpl.
rewrite plus_n_Sm. reflexivity.
Qed.
(* Move to Coq.Lists.List ? *)
Lemma fold_right_map {A B C: Type}
(f: B -> C -> C) (m: A->B) (s:C) (l: list A) :
fold_right f s (map m l)
= fold_right (fun a c => f (m a) c) s l.
Proof using.
induction l; simpl;congruence.
Qed.
Require Import Coq.Unicode.Utf8.
Lemma fold_left_right_rev:
∀ (A B : Type) (f : A → B → B) (l : list A) (i : B),
fold_right f i l = fold_left (λ (x : B) (y : A), f y x) (rev l) i.
Proof.
intros.
rewrite <- (rev_involutive l) at 1.
apply fold_left_rev_right.
Qed.
(* Move *)
Lemma map_nth2:
forall (A B : Type) (f : A -> B) (l : list A) (d : A) (db: B) (n : nat),
n < length l
-> nth n (map f l) db = f (nth n l d).
Proof using.
intros. rewrite nth_indep with (d':= (f d));[| rewrite map_length; assumption].
apply map_nth.
Qed.
Require Import PArith.
Require Import NArith.
Open Scope N_scope.
Lemma Nseq_add : forall (n m:nat) (s:N),
(seq N.succ s (n+m) = (seq N.succ s n)++(seq N.succ (s+N.of_nat n) m)).
Proof using.
intros ?. induction n; intros m s;
[ rewrite N.add_0_r ; reflexivity | ].
rewrite Nat2N.inj_succ. simpl.
f_equal. rewrite IHn. do 2 f_equal.
lia.
Qed.
(* move to list.v *)
Definition NLength {A:Type} (lv: list A) : N := N.of_nat (length lv).
Lemma NLength_length {A:Type} (lv: list A) :
N.to_nat (NLength lv)
= length lv.
Proof using.
unfold NLength.
lia.
Qed.
Lemma seq_NoDup len start : NoDup (seq N.succ start len).
Proof using.
clear.
revert start; induction len; simpl; constructor; trivial.
rewrite in_seq_Nplus. intros (H,_).
lia.
Qed.
Lemma seq_rev_N : forall l n,
rev (seq N.succ n l) = map (fun x => n + n + N.of_nat l-x-1) (seq N.succ n l).
Proof using.
clear.
induction l; auto.
intro.
replace (S l) with (l + 1)%nat at 1 by omega.
rewrite Nnat.Nat2N.inj_succ.
rewrite Nseq_add. simpl.
rewrite rev_app_distr. simpl.
f_equal;[ lia |].
rewrite IHl.
rewrite seq_shift.
rewrite map_map. unfold compose. simpl.
apply eq_maps. intros ? ?.
lia.
Qed.
Hint Rewrite @NLength_length : list.
Hint Rewrite @NLength_length : SquiggleEq.
Close Scope N_scope.
Lemma flat_map_single {A B:Type} (f: A->B) (l:list A) :
flat_map (fun x => [f x]) l
= map f l.
Proof using.
induction l;auto.
Qed.
Lemma combine_app : forall {A B} (la1 la2 : list A) {lb1 lb2 : list B},
length la1 = length lb1
->
combine (la1 ++ la2) (lb1 ++ lb2)
= (combine la1 lb1) ++ (combine la2 lb2).
Proof using.
induction la1; intros ? ? ? Heq; destruct lb1 as [| b1 lb1]; invertsn Heq;[refl|].
rewrite combine_cons.
do 3 rewrite <- app_comm_cons.
rewrite combine_cons.
f_equal. eauto.
Qed.
(* Move *)
Lemma lforall_rev {A:Type} (P: A -> Prop):
forall l, lforall P l -> lforall P (rev l).
Proof using.
intros ?. unfold lforall. setoid_rewrite <- in_rev.
tauto.
Qed.
(* Move *)
Lemma rev_combine {A B:Type} : forall (la : list A) (lb: list B),
length la = length lb
-> rev (combine la lb) = combine (rev la) (rev lb).
Proof using.
induction la; intros ? Heq; destruct lb as [|b lb]; invertsn Heq; [refl|].
simpl. rewrite combine_app;[| autorewrite with list; assumption].
rewrite IHla by assumption.
refl.
Qed.
(* Move *)
Lemma option_map_id {T:Type}: forall (k:option T),
option_map id k = k.
Proof using.
intros. destruct k; refl.
Qed.
Definition NLmax : (list N) -> N -> N :=
fold_left N.max.
Lemma NLmax_le2 : forall lp p1 p2,
(p1 <= p2 -> NLmax lp p1 <= NLmax lp p2)%N.
Proof using.
induction lp; auto.
intros ? ? Hle. simpl.
apply IHlp. lia.
Qed.
Lemma NLmax_le3 : forall x lp p,
(In x (p::lp) -> x <= NLmax lp p)%N.
Proof.
induction lp; intros ? Hin.
- apply in_single_iff in Hin. subst. reflexivity.
- simpl in *. dorn Hin; [ | dorn Hin]; subst; auto.
+ eapply transitivity;[apply IHlp; left; refl | apply NLmax_le2; lia].
+ eapply transitivity;[apply IHlp; left; refl | apply NLmax_le2; lia].
Qed.
Lemma NLmax_le : forall x lp,
(In x lp -> x <= NLmax lp 0)%N.
Proof.
intros. apply NLmax_le3. sp.
Qed.
(* the 4 items below are exact copies [Z/N] of the 4 above *)
Definition ZLmax : (list Z) -> Z -> Z :=
fold_left Z.max.
Lemma ZLmax_le2 : forall lp p1 p2,
(p1 <= p2 -> ZLmax lp p1 <= ZLmax lp p2)%Z.
Proof using.
induction lp; auto.
intros ? ? Hle. simpl.
apply IHlp. lia.
Qed.
Lemma ZLmax_le3 : forall x lp p,
(In x (p::lp) -> x <= ZLmax lp p)%Z.
Proof.
induction lp; intros ? Hin.
- apply in_single_iff in Hin. subst. reflexivity.
- simpl in *. dorn Hin; [ | dorn Hin]; subst; auto.
+ eapply transitivity;[apply IHlp; left; refl | apply ZLmax_le2; lia].
+ eapply transitivity;[apply IHlp; left; refl | apply ZLmax_le2; lia].
Qed.
Lemma ZLmax_le : forall x lp,
(In x lp -> x <= ZLmax lp 0)%Z.
Proof.
intros. apply ZLmax_le3. sp.
Qed.
Lemma ZLmax_lub : forall lp p ub,
((forall x, In x (p::lp) -> x <= ub) -> ZLmax lp p <= ub)%Z.
Proof.
induction lp; intros ? ? Hin.
- simpl. apply Hin. sp.
- simpl in *. apply IHlp.
intros ? Hinn. apply Hin.
dorn Hinn; auto;[].
pose proof (Zmax_spec p a) as Hz. subst.
firstorder.
Qed.
Lemma ZLmax_lub_lt : forall lp p ub,
((forall x, In x (p::lp) -> x < ub) -> ZLmax lp p < ub)%Z.
Proof.
intros lp p ub.
pose proof (ZLmax_lub lp p (Z.pred ub)) as Hz.
setoid_rewrite <- Z.lt_succ_r in Hz.
setoid_rewrite <- Zsucc_pred in Hz.
exact Hz.
Qed.
Lemma ZLmax_In : forall lp p,
LIn (ZLmax lp p) (p::lp).
Proof.
induction lp; [simpl|]; auto.
simpl ZLmax.
intros.
specialize (IHlp (Z.max p a)).
destruct (Zmax_spec p a) as [Hh| Hh]; repnd;
rewrite Hh; rewrite Hh in IHlp; simpl in *; tauto.
Qed.
Hint Rewrite seq_length: list.
Lemma length_combine_seq {A B:Type} (lnm: list A) (f: B->B) (s:B):
length (combine (seq f s (length lnm)) lnm) = length lnm.
Proof using.
rewrite length_combine_eq; autorewrite with list; refl.
Qed.
Hint Rewrite @length_combine_seq: list.
Lemma opExtractSome (A : Type) (d: A) (op: option A) (x:A):
op = Some x
-> opExtract d op = x.
Proof using.
clear. intros. subst. refl.
Qed.
Fixpoint firstIndex {T:Type} {d: Deq T} (f:T) (l : list T) : option N :=
match l with
| [] => None
| h::tl => if (decide (h=f)) then Some 0%N else option_map N.succ (firstIndex f tl)
end.
Lemma firstIndexNoDup {T:Type} {d: Deq T} (f:T) (l : list T) n:
nth_error l n = Some f
-> NoDup l
-> firstIndex f l = Some (N.of_nat n).
Proof using.
clear.
revert n.
induction l; simpl; intros ? Heq Hnd.
- clear Hnd. destruct n; inverts Heq.
Local Opaque N.of_nat.
- destruct n; simpl in *;
[inverts Heq;rewrite deq_refl; refl| ].
invertsna Hnd Hnd.
specialize (IHl _ Heq Hnd0).
clear Hnd0.
apply nth_error_In in Heq.
rewrite decide_decideP.
cases_if; subst;[contradiction|].
rewrite IHl. simpl.
rewrite Nnat.Nat2N.inj_succ.
refl.
Local Transparent N.of_nat.
Qed.
Lemma firstIndexNoDupN {T:Type} {d: Deq T} (f:T) (l : list T) n:
nth_error l (N.to_nat n) = Some f
-> NoDup l
-> firstIndex f l = Some n.
Proof using.
rewrite <- Nnat.N2Nat.id at 2.
apply firstIndexNoDup.
Qed.
Lemma nth_error_map (A B : Type) (f: A->B) (l : list A) (n : nat):
nth_error (map f l) n = option_map f (nth_error l n).
Proof using.
revert n.
induction l; intros n; destruct n; auto.
simpl. eauto.
Qed.
Lemma seq_nth_select start (nf n:nat):
(n < nf)%nat
-> (nth_error (seq N.succ start nf) n) = Some (start + N.of_nat n)%N.
Proof using.
revert nf n start. clear.
induction nf; intros ? ? Hlt; destruct n; auto; simpl in *;
try omega;[f_equal; lia| ].
simpl. specialize (IHnf n (N.succ start) ltac:(omega)).
rewrite IHnf.
f_equal. lia.
Qed.
Definition injective_fun_conditional {A B : Type} (C : A->Prop) (f : A → B) :=
∀ a1 a2 : A, C a1 -> C a2 ->
f a1 = f a2 → a1 = a2.
Lemma NoDupInjectiveMap2 (A B : Type) (f : A → B) l:
injective_fun_conditional (fun a => In a l) f
→ NoDup l → NoDup (map f l).
Proof.
intros Hin. induction l; [simpl; constructor |].
intros Hnd. inverts Hnd.
simpl. constructor; eauto.
- intros Hl.
apply in_map_iff in Hl. subst.
exrepnd.
apply Hin in Hl0; subst; sp.
- apply IHl; auto. intros ? ? ? ?. apply Hin; right; auto.
Qed.
Definition boolNthTrue (len n:nat) : list bool:=
map (fun m => if decide(n=m) then true else false )(List.seq 0 len).
Fixpoint noDupB {A:Type} {deq : Deq A} (la: list A) : bool :=
match la with
| [] => true
| h::tl => andb (negb (decide (In h tl))) (noDupB tl)
end.
Lemma noDupBCorrect {A:Type} {deq : Deq A} (la: list A) :
noDupB la = true <-> NoDup la.
Proof.
induction la; simpl;[split; intro Hyp; eauto using NoDup_nil,NoDup_cons| ].
unfold negb.
rewrite memberb_din.
destruct (in_deq A deq a la); split; intro Hyp; try inverts Hyp;
repeat rewrite andb_true_l in *;
try congruence; eauto using NoDup_cons.
- apply NoDup_cons; eauto. apply IHla. assumption.
- apply IHla. assumption.
Qed.
Global Instance decideNoDup {A:Type} {deq : Deq A} (la: list A) : Decidable (NoDup la).
exists (noDupB la).
rewrite noDupBCorrect. refl.
Defined.
Lemma NoDupApp {A:Type} (la lb: list A):
NoDup la -> NoDup lb -> disjoint la lb -> NoDup (la++lb).
Proof using.
induction la; auto;[].
intros H1d H2d Hdis.
rewrite <- app_comm_cons.
inverts H1d.
apply disjoint_cons_l in Hdis. repnd.
constructor;[ rewrite in_app_iff; tauto| eauto].
Qed.
(**
Partition a list : those satisfying f go to lhs*)
Fixpoint partition {A:Type} (f: A -> bool) (l: list A): (list A * list A) :=
match l with
| [] => ([],[])
| h::tl => let (l,r) := partition f tl in
if f h then (h::l,r) else (l,h::r)
end.
Definition merge {A :Type} (la lb : list A) :=
flat_map (fun p => [fst p; snd p]) (combine la lb).
Definition numberElems {A:Type }(l: list A) : list (nat*A) :=
combine (List.seq 0 (length l)) l.
(* A fixpoint that maintains a circular counter may be faster than doing the
remainder operation again and again? *)
Definition filter_mod {A:Type }(l: list A) (period rem:N) : (list A)
:=
(let ls := combine (seq N.succ 0 (length l)) l in
let l := filter (fun p => decide ((fst p) mod period = rem)) ls in
(map snd l))%N.
Definition headTail {A:Type} (defhead: A) (la: list A) : (A * list A) :=
match la with
| h::tl => (h,tl)
| _ => (defhead, [])
end.
(* Same as combine, but pads the RHS instead of dropping the xtra items in LHS *)
Fixpoint combineDef2 {A B:Type} (l : list A) (l' : list B) (db:B): list (A*B) :=
match l,l' with
| x::tl, y::tl' => (x,y)::(combineDef2 tl tl' db)
| x::tl, [] => (x,db)::(combineDef2 tl [] db)
| [],_ => []
end.
Lemma combineDef2len {A B:Type} (db:B) (l : list A) (l' : list B) :
length (combineDef2 l l' db) = length l.
Proof using.
revert l'. induction l; auto; destruct l'; simpl; auto.
Qed.
Lemma option_map_map {A B C : Type} (f : A -> B) (g : B -> C) (l : option A):
let map := option_map in
map _ _ g (map _ _ f l) = map _ _ (fun x : A => g (f x)) l.
Proof.
destruct l; refl.
Qed.
Require Import ExtLib.Structures.Monads.
Require Import ExtLib.Data.Monads.OptionMonad.
Lemma fold_option_bind {A B : Type} (f : A -> option B) (o : option A):
@bind option _ _ _ o f =
match o with
| Some a => f a
| None => None
end.
Proof. reflexivity. Qed.
Lemma fold_option_map {A B : Type} (f : A -> B) (o : option A):
option_map f o=
match o with
| Some a => Some (f a)
| None => None
end.
Proof. reflexivity. Qed.
Require Import ExtLibMisc.
Lemma option_map_ext (A B : Type) (f g : A -> B):
(forall a : A, f a = g a) -> forall l : option A, option_map f l = option_map g l.
Proof using.
intros feq ?.
destruct l; simpl; [ fequal; eauto | reflexivity ].
Qed.
Require Import Basics.
Open Scope program_scope.
Lemma opmap_flatten_map {A B C:Type} {fb : A-> option B} {fm: B -> C} la :
option_map (map fm) (flatten (map fb la)) = flatten (map (option_map fm ∘ fb) la).
Proof using.
induction la; auto.
simpl.
rewrite <- IHla. clear IHla.
destruct (map fb la); unfold compose; destruct (fb a); auto;
simpl; auto; destruct (flatten l); simpl; auto; destruct o; auto.
Qed.
Lemma opmap_bind {A B C:Type} {fb : A-> option B} {fm: B -> C} oa :
option_map fm (@bind option _ _ _ oa fb) = (@bind option _ _ _ oa ((option_map fm)∘ fb)).
Proof using.
destruct oa; refl.
Qed.
Lemma matchNoneNone {A B :Type} (oa : option A) (b: B) :
match oa with
| Some _ => b
| None => b
end = b.
Proof using.
destruct oa; refl.
Qed.
(* delete ?
Lemma opmap_flatten_map2 {A B C D:Type} {fb : A-> option B} {fm: B -> C} (fo : list C -> D) la :
option_map (fun lb => fo (map fm lb)) (flatten (map fb la))
=
option_map fo (flatten (map ((option_map fm) ∘ fb) la)).
Proof using.
rewrite <- option_map_map. f_equal.
eapply opmap_flatten_map; eauto.
Qed.
*)
Require Import ExtLib.Data.Option Coq.Classes.RelationClasses.
(** move and replace in Extlib.Datatypes.Option? this is a generalization (heterogenization)*)
Fixpoint Roption {A B:Type} (R: A->B->Prop) (oa: option A) (ob: option B) : Prop :=
match oa,ob with
| Some a, Some b => R a b
| None, None => True
| _, _ => False
end.
Fixpoint Rlist {A B:Type} (R: A->B->Prop) (oa: list A) (ob: list B) : Prop :=
match oa,ob with
| a::oa, b::ob => R a b /\ Rlist R oa ob
| [], [] => True
| _, _ => False
end.
(* Move to Common.ExtlibMisc. *)
Global Instance RoptionRefl T {R: T-> T-> Prop}
{rr: Reflexive R} : Reflexive (Roption R).
Proof using.
intros x. destruct x; simpl; auto.
Qed.
Global Instance RoptionSymm T {R: T-> T-> Prop}
{rr: Symmetric R} : Symmetric (Roption R).
Proof using.
intros x y H. destruct x; destruct y; simpl in *; auto.
Qed.
Global Instance RoptionTrans T {R: T-> T-> Prop}
{rr: Transitive R} : Transitive (Roption R).
Proof using.
intros x y z Ha Hb. destruct x; destruct y; destruct z; simpl in *; eauto.
contradiction.
Qed.
Require Import Morphisms.
Global Instance ProperRoption {A B: Type} {f : A->B} Ra Rb (Hp: Proper (Ra ==> Rb) f) :
Proper (Roption Ra ==> Roption Rb) (option_map f).
Proof using.
intros oa ob. destruct oa; destruct ob; simpl; eauto.
Qed.
(* Move to SquiggleEq.list *)
Lemma RlistNth {A B:Type} (R: A-> B-> Prop) (la : list A) (lb : list B):
Rlist R la lb <->
(Datatypes.length la = Datatypes.length lb /\
(forall (n : nat) a b, n < length la -> R (nth n la a) (nth n lb b))).
Proof using.
revert lb.
induction la; intros lb; split; intros Hyp; destruct lb as [ | b lb]; simpl in *;
dlists_len; try firstorder; try f_equal; try constructor; try firstorder;
rename H0 into Hyps0.
- specialize (IHla lb). rewrite IHla in Hyps0.
apply proj2 in Hyps0.
destruct n; eauto.
apply Hyps0. omega.
- specialize (Hyps0 0). simpl in *. apply Hyps0; eauto. omega.
- apply IHla. dands; auto. intros. specialize (Hyps0 (S n)). simpl in *.
apply Hyps0. omega.
Qed.
Lemma RoptionFlatten {A B:Type} (R : A->B-> Prop) (la: list (option A)) (lb: list (option B)):
Rlist (Roption R) la lb -> Roption (Rlist R) (flatten la) (flatten lb).
Proof using.
revert lb.
induction la; simpl; destruct lb as [ |b lb]; intros Hr; simpl in *; try tauto; repnd.
apply IHla in Hr.
destruct (flatten la);
destruct (flatten lb);simpl in *; try tauto;
destruct a; destruct b; simpl in *; try tauto.
Qed.
Lemma RlistMap {I A B:Type} (fa: I-> A) (fb: I-> B) (R: A-> B-> Prop) li:
Rlist R (map fa li) (map fb li)
<-> (forall i, In i li -> R (fa i) (fb i)).
Proof using.
induction li; simpl; try tauto;[].
firstorder.
subst. assumption.
Qed.
Import MonadNotation.
Lemma isSomeBindRet {A B:Type}: forall (v:option A) (f:A->B),
isSome v
-> isSome (x <- v ;; (ret (f x))).
Proof using.
intros ? ? His.
simpl. destruct v; auto.
Qed.
Lemma isSomeFlatten {A} : forall (lo : list (option A)),
(forall a, In a lo -> isSome a)
-> isSome (flatten lo).
Proof using.
unfold flatten. intros ? Hin.
induction lo; simpl in *; auto.
dLin_hyp.
destruct a; simpl in *; try tauto; auto.
intros.
specialize (IHlo Hin). clear Hin.
match type of IHlo with
isSome ?s => destruct s
end; auto.
Qed.
Lemma combine_eta {A B:Type} : forall (lp: list (A*B)), combine (map fst lp) (map snd lp) = lp.
Proof using.
clear. intros.
rewrite combine_map.
rewrite map_ext with (g:=id);[ apply map_id | ].
intros. destruct a; auto.
Qed.
Lemma flatten_map_Some {A B:Type} (f: A->B) (vs: list A):
(flatten (map (fun x : A => Some (f x)) vs)) = Some (map f vs).
Proof using.
induction vs; auto.
simpl. rewrite IHvs. reflexivity.
Qed.
Lemma opmap_flatten_map2 {A B C D:Type} {fb : A-> option B} {fm: B -> C} (fo : list C -> D) la :
option_map (fun lb => fo (map fm lb)) (flatten (map fb la))
=
option_map fo (flatten (map ((option_map fm) ∘ fb) la)).
Proof using.
rewrite <- option_map_map. f_equal.
eapply opmap_flatten_map; eauto.
Qed.
Definition option_rectp {A:Type} := @option_rect A (fun a => Prop).
Ltac inreasoning := intros; repeat in_reasoning; subst.
Lemma flattenSomeImplies {A:Type} ola (la : list A):
flatten ola = Some la
-> forall a oa, In (oa,a) (combine ola la) -> oa = Some a.
Proof.
revert la.
induction ola; intros ? Hf ? ? Hin; simpl in *; [tauto | ].
simpl in *.
destruct a; invertsn Hf.
destruct la as [ | ha la]; invertsn Hin; try invertsn Hin.
- destruct (flatten ola); invertsn Hf. refl.
- apply IHola with (la:=la); auto.
destruct (flatten ola); invertsn Hf. refl.
Qed.
Lemma flattenSomeImpliesLen {A:Type} ola (la : list A):
flatten ola = Some la
-> length ola = length la.
Proof.
revert la.
induction ola; intros ? Hf; [invertsn Hf; refl | ].
simpl in *.
destruct a; invertsn Hf.
destruct (flatten ola); invertsn Hf.
simpl. f_equal. eauto.
Qed.
Hint Rewrite repeat_length : list.
Lemma lin_combine_map: forall {A B C D :Type}
(fa: A->C) (fb: B->D) (a:A) (b:B) (la: list A) (lb: list B),
LIn (a, b) (combine la lb)
-> LIn (fa a,fb b) (combine (map fa la) (map fb lb)).
Proof using.
induction la; intros ? Hp; sp.
simpl. destruct lb; sp.
simpl. dorn Hp; try invertsn Hp; firstorder.
Qed.
Lemma lin_combine_map_implies : forall {A B C D :Type}
(fa: A->C) (fb: B->D) (c:C) (d:D) (la: list A) (lb: list B),
LIn (c,d) (combine (map fa la) (map fb lb))
-> exists (a:A) (b:B), In (a,b) (combine la lb) /\ c = fa a /\ d = fb b.
Proof using.
induction la; intros ? Hp; firstorder.
destruct lb; invertsn Hp.
- invertsn Hp. eexists. eexists. dands; eauto. firstorder.
- apply IHla in Hp. exrepnd. subst. eexists. eexists. dands; eauto. firstorder.
Qed.
Lemma map_flat_map (A B C : Type) (f : B -> list C) (g : C -> A) (l : list B):
map g (flat_map f l) = flat_map ((map g) ∘ f) l.
Proof using.
induction l; auto.
simpl. rewrite map_app. rewrite IHl. refl.
Qed.
Lemma disjoint_map_if (A B : Type) (f : A -> B) (l1 l2 : list A):
injective_fun f ->
disjoint l1 l2 -> disjoint (map f l1) (map f l2).
Proof using.
intros Hinj. unfold disjoint. unfold injective_fun in Hinj.
intros Hd ? Hin Hinc.
apply in_map_iff in Hin. exrepnd. subst.
apply in_map_iff in Hinc. exrepnd.
apply Hinj in Hinc0. subst. firstorder.
Qed.
Ltac disjoint_reasoning2 :=
match goal with
| [ |- disjoint _ (_ ++ _) ] => apply disjoint_app_r;split
| [ |- disjoint (_ ++ _) _ ] => apply disjoint_app_l;split
| [ |- disjoint _ (_ :: (_ :: _)) ] => apply disjoint_cons_r;split
| [ |- disjoint (_ :: (_ :: _)) _ ] => apply disjoint_cons_l;split
| [ |- disjoint _ (_ :: ?v) ] => notNil v;apply disjoint_cons_r;split
| [ |- disjoint (_ :: ?v) _ ] => notNil v;apply disjoint_cons_l;split
| [ |- disjoint _ _ ] => (sp;fail || apply disjoint_sym; sp;fail)
| [ |- _ <> _] => apply disjoint_neq_iff
| [ |- ! (LIn _ _)] => apply disjoint_singleton_l
(** important to leave it the way it was .. so that repeat progress won't loop*)
| [ H: disjoint _ (_ ++ _) |- _ ] => apply disjoint_app_r in H;sp
| [ H: disjoint (_ ++ _) _ |- _ ] => apply disjoint_app_l in H;sp
| [ H: disjoint _ (_ :: (_ :: _)) |- _ ] => apply disjoint_cons_r in H;sp
| [ H: disjoint (_ :: (_ :: _)) _ |- _ ] => apply disjoint_cons_l in H;sp
| [ H: disjoint _ (_ :: ?v) |- _ ] => notNil v;apply disjoint_cons_r in H;sp
| [ H: disjoint (_ :: ?v) _ |- _ ] => notNil v;apply disjoint_cons_l in H;sp
| [ H: !(disjoint _ []) |- _ ] => provefalse; apply H; apply disjoint_nil_r
| [ H: !(disjoint [] _) |- _ ] => provefalse; apply H; apply disjoint_nil_l
| [ H: (disjoint _ []) |- _ ] => clear H
| [ H: (disjoint [] _) |- _ ] => clear H
| [ H: ! (LIn _ _) |- _] => apply disjoint_singleton_l in H
| [ H: _ <> _ |- _] => apply disjoint_neq_iff in H
end.
Ltac noRepDis1 :=
autorewrite with SquiggleEq;
(repeat match goal with
[H: no_repeats [] |- _] => clear H
|[H: ! (LIn _ _) |- _] => apply disjoint_singleton_l in H
|[|- ! (LIn _ _)] => apply disjoint_singleton_l
|[H: no_repeats (_::_) |- _] =>
let Hnrd := fresh "Hnrd" in
apply no_repeats_as_disjoint in H;
destruct H as [Hnrd H]
end); repeat (progress disjoint_reasoning2);
repeat rewrite in_single_iff in *; subst; try tauto.
Lemma noDupApp {A:Type} (la lb : list A):
NoDup (la++lb)
<-> NoDup la /\ NoDup lb /\ disjoint la lb.
Proof using.
revert lb.
induction la; [simpl; split; intros; dands; autorewrite with list in *; auto; try constructor;
try tauto
|].
intros ?. rewrite <- app_comm_cons.
rewrite NoDup_cons_iff.
rewrite IHla.
split; intros; repnd; dands; auto; noRepDis1.
constructor; noRepDis1.
Qed.
Lemma diffAddCancel {A:Type} {deq: Deq A} (lr lv : list A):
subset lv (lr ++ (lremove lr lv)).
Proof using.
unfold eq_set, subset.
setoid_rewrite in_app_iff.
setoid_rewrite in_diff. firstorder.
destruct (decideP (In x lr)); firstorder.
Qed.
Lemma removeConsCancel {A:Type} {deq: Deq A} (r:A)(lv : list A):
subset lv (r::(remove r lv)).
Proof using.
apply (diffAddCancel [r]).
Qed.
(* need more assumptions. [f] could equate everything not in the list to f (head l).
then LHS would say 0 for such elements. RHS would always be not found for such elements. *)
Lemma mapFirstIndex {A:Type} {deq: Deq A}(f:A->A) x l:
NoDup (map f l)
-> firstIndex (f x) (map f l) = firstIndex x l.
Proof using.
intros Hnd.
induction l; [refl|].
simpl. symmetry. rewrite decide_decideP.
cases_if; subst;[rewrite deq_refl; refl|].
Abort.
Lemma mapNodupFirstIndex {A:Type} {deq: Deq A}(f:A->A) x l:
In x l
-> NoDup (map f l)
-> firstIndex (f x) (map f l) = firstIndex x l.
Proof using.
intros Hin Hnd.
induction l; [refl|]. simpl in *.
simpl. symmetry. rewrite decide_decideP.
cases_if; subst;[rewrite deq_refl; refl|].
dorn Hin;[contradiction|].
invertsn Hnd. specialize (IHl Hin).
apply (in_map f) in Hin.
rewrite decide_decideP.
cases_if;[ congruence |].
f_equal. symmetry. eauto.
Qed.
Lemma eqsetRev {A:Type} (la: list A): eq_set la (rev la).
Proof using.
apply eq_set_iff_eq_set2. unfold eq_set2.
apply in_rev.
Qed.
Lemma noDupRev {A:Type} (la: list A): NoDup la -> NoDup (rev la).
Proof using.
induction la; auto.
intros Hd. simpl. invertsn Hd.
apply NoDupApp; eauto;[constructor; auto; constructor|].
rewrite <- eqsetRev. apply disjoint_singleton_r. assumption.
Qed.
Global Instance properEqsetCons {A : Type}:
Proper (eq ==> eq_set ==> eq_set) (@cons A).
Proof using.
intros ? ? ? ? ? ?. subst.
unfold eq_set, subset in *. simpl in *.
firstorder.
Qed.
Definition singleton {A:Type} (a:A) : list A := [a].
Lemma noDupConsIff {A : Type}:
forall a (lb : list A), NoDup (a::lb) <-> NoDup (singleton a) /\ NoDup lb /\ disjoint [a] lb.
Proof using.
intros. rewrite <- noDupApp. refl.
Qed.
Lemma flat_map_fcons {A B : Type} (f: A->B) (g : A -> list B) (l : list A):
eq_set (flat_map (fun x : A => (f x):: g x) l) (map f l ++ flat_map g l).
Proof using.
rewrite <- flat_map_single.
rewrite <- flat_map_fapp.
refl.
Qed.
Hint Rewrite @noDupApp @noDupConsIff: SquiggleEq.
(* Move to SquiggleEq.list *)
Hint Rewrite app_length repeat_length firstn_length : list.
(* Move to SquiggleEq.list *)
Lemma listPadId {A:Type} d (l: list A) n :
(n <= length l)%nat -> listPad d l n = l.
Proof using.
clear.
intros Hyp.
unfold listPad.
assert (n-length l =0)%nat as Heq by omega.
rewrite Heq. simpl.
autorewrite with list. refl.
Qed.
Lemma listPad_length_eq {T} (def:T) (l: list T) (n: nat):
(length l <= n -> length (listPad def l n) = n)%nat.
Proof using.
setoid_rewrite app_length.
intros.
rewrite repeat_length.
omega.
Qed.
(* Move to SquiggleEq.list
*)
Lemma flattenSomeCons {A:Type} (loa: list (option A)) a:
isSome (flatten (a::loa))
-> isSome (flatten loa).
Proof using.
intros Hs.
simpl in Hs.
destruct a; firstorder.
destruct (flatten loa); firstorder.
Qed.
(* Move to SquiggleEq.list
*)
Lemma flattenLift2 {A B:Type} (f: A-> option B) g l:
(forall b, In b l -> f b = g b)
-> isSome (flatten (map f l))
-> flatten (map f l) = flatten (map g l).
Proof using.
intros Heq Hs.
induction l; try (firstorder; fail).
pose proof Heq as Heqb.
specialize (Heq a). simpl.
pose proof Hs as Hsb.
simpl in Hsb.
destruct (f a);[ | firstorder].
specialize (Heq (ltac:(simpl;auto))).
rewrite <- Heq.
apply flattenSomeCons in Hs.
rewrite IHl;[reflexivity | firstorder| assumption].
Qed.
(* Move to SquiggleEq.Usefultypes
*)
Lemma isSomeIf {A:Type} oa (a: A):
oa = Some a -> isSome oa.
Proof using.
firstorder.
subst. refl.
Qed.
(* Move to SquiggleEq.list
*)
Lemma flattenLift {A B:Type} (f: A-> option B) g l:
(forall b, isSome (f b) -> f b = g b)
-> (forall b, isSome (g b) -> isSome (f b))
-> flatten (map f l) = flatten (map g l).
Proof using.
intros Heq Hn.
induction l;firstorder. simpl in *.
specialize (Heq a).
specialize (Hn a).
destruct (f a).
- unfold isSome in Heq.
specialize (Heq (ltac:(auto))).
rewrite <- Heq. rewrite IHl. refl.
- clear Heq. destruct (g a); firstorder.
Qed.
(* MOVE to SquiggleEq.list *)
Lemma lforallCons {A} (P:A->Prop) a l: lforall P l -> P a -> lforall P (a::l).
Proof using.
intros.
intros ? Hin.
dorn Hin; subst; auto.
Qed.
(* Move to SquiggleEq.list
*)
Lemma flattenSomeIn {A:Type} (loa: list (option A)) a:
isSome (flatten loa)
-> In a loa -> isSome a.
Proof using.
revert a.
induction loa as [ | a loa]; destruct a; intros aa; destruct aa; try (firstorder; fail).
intros Hs Hin. apply False_ind.
apply flattenSomeCons in Hs.
dorn Hin; firstorder.
inversion Hin.
Qed.
Require Import SetoidList.
Lemma eqListA_refl {A} (R : A-> A-> Prop) lbt:
(forall l, In l lbt -> R l l) ->
SetoidList.eqlistA R lbt lbt.
Proof using.
intros.
induction lbt; auto; constructor; firstorder.
Qed.
Lemma eqListA_map {A B} (f g: A->B)
(Ra : A -> A -> Prop) (Rb : B -> B -> Prop) l1 l2
(feq : forall a1 a2, In a1 l1 -> In a2 l2 -> Ra a1 a2 -> Rb (f a1) (g a2)):
SetoidList.eqlistA Ra l1 l2
-> SetoidList.eqlistA Rb (map f l1) (map g l2).
Proof using.
intros Hp.
induction Hp; auto; simpl; firstorder; constructor; eauto.
Qed.
Lemma eqListA_eq {A} l1 l2:
SetoidList.eqlistA (@eq A) l1 l2
-> l1 = l2.
Proof using.
intros Hp.
induction Hp; auto; subst; auto.
Qed.
Ltac in_reasoning2 := unfold lforall;
match goal with
[ |- forall _:_, In _ _ -> _] => intros ? ?;
in_reasoning;subst; auto
end.
Ltac inj0_step :=
match goal with
| [ H : (_, _) = (_, _) |- _ ] => apply pair_inj in H; repd; subst; GC
| [ H : S _ = S _ |- _ ] => apply S_inj in H; repd; subst; GC
| [ H : S _ < S _ |- _ ] => apply S_lt_inj in H; repd; subst; GC
| [ H : snoc _ _ = snoc _ _ |- _ ] => apply snoc_inj in H; repd; subst; GC
end.
Ltac inj0 := repeat inj0_step.
(*
Ltac inj :=
repeat match goal with
[ H : _ |- _ ] =>
(apply pair_inj in H
|| apply S_inj in H
|| apply S_lt_inj in H
|| apply snoc_inj in H);
repd; subst; GC
end; try (complete sp).
*)
Ltac inj := inj0; try (complete auto); try (complete sp).
Ltac cpx :=
repeat match goal with
(* false hypothesis *)
| [ H : [] = snoc _ _ |- _ ] =>
complete (apply nil_snoc_false in H; sp)
| [ H : snoc _ _ = [] |- _ ] =>
complete (symmetry in H; apply nil_snoc_false in H; sp)
(* simplifications *)
| [ H : _ :: _ = _ :: _ |- _ ] => inversion H; subst; GC
| [ H : 0 = length _ |- _ ] =>
symmetry in H; trw_h length0 H; subst
| [ H : length _ = 0 |- _ ] =>
trw_h length0 H; subst
| [ H : 1 = length _ |- _ ] =>
symmetry in H; trw_h length1 H; exrepd; subst
| [ H : length _ = 1 |- _ ] =>
trw_h length1 H; exrepd; subst
| [ H : [_] = snoc _ _ |- _ ] =>
symmetry in H; trw_h snoc1 H; repd; subst
| [ H : snoc _ _ = [_] |- _ ] =>
trw_h snoc1 H; repd; subst
| [ H : context[length (snoc _ _)] |- _ ] =>
rewrite length_snoc in H
end;
inj;
try (complete (allsimpl; sp)).
(* Move to SquiggleEq *)
Lemma in_combine_same {A:Type} (e v: A) pvs: LIn (e, v) (combine pvs pvs)
-> e =v /\ In e pvs.
Proof using.
induction pvs; cpx; simpl.
firstorder; inverts H ;auto.
Qed.
(* Move to SquiggleEq *)
Tactic Notation "forder" ident_list (idl) :=
revert idl; clear; firstorder.
Lemma select_Rl {A:Type} lbt lbtp n (bt:A) R:
select n lbt = Some bt ->
eqlistA R lbt lbtp ->
exists btp, select n lbtp = Some btp /\ R bt btp.
Proof using.
intros Hs Heq. revert dependent n.
induction Heq; intros; destruct n; inverts Hs; simpl.
- eexists; eauto.
- eauto.
Qed.
(* move to SquiggleEq *)
Ltac simpl_combine :=
(
match goal with
| [ H : context[map snd (combine _ _)] |- _] =>rewrite <- combine_map_snd in H; [ |try(simpl_list);spc;idtac "check lengths in combine";fail]
| [ |- context[map snd (combine _ _)] ] =>rewrite <- combine_map_snd ;[ |try(simpl_list);spc;idtac "check lengths in combine";fail]
| [ H : context[map fst (combine _ _)] |- _] =>rewrite <- combine_map_fst in H; [ |try(simpl_list);spc;idtac "check lengths in combine";fail]
| [ |- context[map fst (combine _ _)] ] =>rewrite <- combine_map_fst ;[ |try(simpl_list);spc;idtac "check lengths in combine";fail]
end).
(* Move to SquiggleEq *)
Lemma eq_eqListA {A} l1 l2:
l1 = l2 -> SetoidList.eqlistA (@eq A) l1 l2.
Proof using.
intros. subst. induction l2; auto.
Qed.
Definition listAddNoDup {A} {deqa: Deq A} (la: list A) a :=
if (decide (In a la)) then la else a::la.
Definition flattenL {A} := @flat_map _ _ (@id (list A)).
Definition isSuffixOfL {A:Type} (la lb : list A):Prop :=
exists l, l++la=lb.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_PP_SYMBOL_V
/**
* lsbuflv2hv_isosrchvaon: Level shift buffer, low voltage to high
* voltage, isolated well on input buffer,
* inverting sleep mode input, zero power
* sleep mode.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP_B,
input LVPWR ,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_ISOSRCHVAON_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DIODE_TB_V
`define SKY130_FD_SC_MS__DIODE_TB_V
/**
* diode: Antenna tie-down diode.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__diode.v"
module top();
// Inputs are registered
reg DIODE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
DIODE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 DIODE = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 DIODE = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 DIODE = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 DIODE = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 DIODE = 1'bx;
end
sky130_fd_sc_ms__diode dut (.DIODE(DIODE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DIODE_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLRTP_TB_V
`define SKY130_FD_SC_HVL__DLRTP_TB_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__dlrtp.v"
module top();
// Inputs are registered
reg RESET_B;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 RESET_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 RESET_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 RESET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 RESET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_hvl__dlrtp dut (.RESET_B(RESET_B), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLRTP_TB_V
|
`timescale 1ns / 1ps
/**********************************************************************
* Felix Winterstein, Imperial College London
*
* File: fifo.v
*
* Revision 1.01
* Additional Comments: distributed under a BSD license, see LICENSE.txt
*
**********************************************************************/
module fifo
#(
parameter DATA_WIDTH = 8,
parameter LOG2_DEPTH = 3
)
(
input clk,
input rst_n,
input [DATA_WIDTH-1:0] din,
input wr_en,
input rd_en,
output reg [DATA_WIDTH-1:0] dout,
output full,
output empty,
output reg valid
);
parameter MAX_COUNT = 2**LOG2_DEPTH;
reg [LOG2_DEPTH-1 : 0] rd_ptr;
reg [LOG2_DEPTH-1 : 0] wr_ptr;
reg [DATA_WIDTH-1 : 0] mem[MAX_COUNT-1 : 0]; //memory size: 2**LOG2_DEPTH
reg [LOG2_DEPTH : 0] depth_cnt;
always @(posedge clk) begin
if(~rst_n) begin
wr_ptr <= 'h0;
rd_ptr <= 'h0;
end // end if
else begin
if(wr_en)
wr_ptr <= wr_ptr+1;
if(rd_en)
rd_ptr <= rd_ptr+1;
end //end else
end//end always
assign empty= (depth_cnt=='h0);
assign full = (depth_cnt==MAX_COUNT);
//comment if you want a registered dout
//assign dout = rd_en ? mem[rd_ptr]:'h0;
always @(posedge clk) begin
if (wr_en)
mem[wr_ptr] <= din;
end //end always
//uncomment if you want a registered dout
always @(posedge clk) begin
if (~rst_n) begin
dout <= 'h0;
valid <= 1'b0;
end else begin
if (rd_en)
valid <= 1'b1;
else
valid <= 1'b0;
dout <= mem[rd_ptr];
end
end
always @(posedge clk) begin
if (~rst_n)
depth_cnt <= 'h0;
else begin
case({rd_en,wr_en})
2'b10 : depth_cnt <= depth_cnt-1;
2'b01 : depth_cnt <= depth_cnt+1;
endcase
end //end else
end //end always
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module clips video streams on the DE boards. *
* *
******************************************************************************/
//`define USE_CLIPPER_DROP
module nios_system_video_clipper_0 (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 29; // Frame's data width
parameter EW = 1; // Frame's empty width
parameter WIDTH_IN = 640; // Incoming frame's width in pixels
parameter HEIGHT_IN = 480; // Incoming frame's height in lines
parameter WW_IN = 9; // Incoming frame's width's address width
parameter HW_IN = 8; // Incoming frame's height's address width
parameter DROP_PIXELS_AT_START = 192;
parameter DROP_PIXELS_AT_END = 192;
parameter DROP_LINES_AT_START = 120;
parameter DROP_LINES_AT_END = 120;
parameter WIDTH_OUT = 256; // Final frame's width in pixels
parameter HEIGHT_OUT = 240; // Final frame's height in lines
parameter WW_OUT = 7; // Final frame's width's address width
parameter HW_OUT = 7; // Final frame's height's address width
parameter ADD_PIXELS_AT_START = 0;
parameter ADD_PIXELS_AT_END = 0;
parameter ADD_LINES_AT_START = 0;
parameter ADD_LINES_AT_END = 0;
parameter ADD_DATA = 30'd0; // Data value for added pixels
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [EW: 0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output [DW: 0] stream_out_data;
output stream_out_startofpacket;
output stream_out_endofpacket;
output [EW: 0] stream_out_empty;
output stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [DW: 0] internal_data;
wire internal_startofpacket;
wire internal_endofpacket;
wire [EW: 0] internal_empty;
wire internal_valid;
wire internal_ready;
// Internal Registers
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_video_clipper_drop Clipper_Drop (
// Inputs
.clk (clk),
.reset (reset),
.stream_in_data (stream_in_data),
.stream_in_startofpacket (stream_in_startofpacket),
.stream_in_endofpacket (stream_in_endofpacket),
.stream_in_empty (stream_in_empty),
.stream_in_valid (stream_in_valid),
.stream_out_ready (internal_ready),
// Bidirectional
// Outputs
.stream_in_ready (stream_in_ready),
.stream_out_data (internal_data),
.stream_out_startofpacket (internal_startofpacket),
.stream_out_endofpacket (internal_endofpacket),
.stream_out_empty (internal_empty),
.stream_out_valid (internal_valid)
);
defparam
Clipper_Drop.DW = DW,
Clipper_Drop.EW = EW,
Clipper_Drop.IMAGE_WIDTH = WIDTH_IN,
Clipper_Drop.IMAGE_HEIGHT = HEIGHT_IN,
Clipper_Drop.WW = WW_IN,
Clipper_Drop.HW = HW_IN,
Clipper_Drop.DROP_PIXELS_AT_START = DROP_PIXELS_AT_START,
Clipper_Drop.DROP_PIXELS_AT_END = DROP_PIXELS_AT_END,
Clipper_Drop.DROP_LINES_AT_START = DROP_LINES_AT_START,
Clipper_Drop.DROP_LINES_AT_END = DROP_LINES_AT_END,
Clipper_Drop.ADD_DATA = ADD_DATA;
altera_up_video_clipper_add Clipper_Add (
// Inputs
.clk (clk),
.reset (reset),
.stream_in_data (internal_data),
.stream_in_startofpacket (internal_startofpacket),
.stream_in_endofpacket (internal_endofpacket),
.stream_in_empty (internal_empty),
.stream_in_valid (internal_valid),
.stream_out_ready (stream_out_ready),
// Bidirectional
// Outputs
.stream_in_ready (internal_ready),
.stream_out_data (stream_out_data),
.stream_out_startofpacket (stream_out_startofpacket),
.stream_out_endofpacket (stream_out_endofpacket),
.stream_out_empty (stream_out_empty),
.stream_out_valid (stream_out_valid)
);
defparam
Clipper_Add.DW = DW,
Clipper_Add.EW = EW,
Clipper_Add.IMAGE_WIDTH = WIDTH_OUT,
Clipper_Add.IMAGE_HEIGHT = HEIGHT_OUT,
Clipper_Add.WW = WW_OUT,
Clipper_Add.HW = HW_OUT,
Clipper_Add.ADD_PIXELS_AT_START = ADD_PIXELS_AT_START,
Clipper_Add.ADD_PIXELS_AT_END = ADD_PIXELS_AT_END,
Clipper_Add.ADD_LINES_AT_START = ADD_LINES_AT_START,
Clipper_Add.ADD_LINES_AT_END = ADD_LINES_AT_END,
Clipper_Add.ADD_DATA = ADD_DATA;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
//
// Module: dma_engine_cntr.v
// Project: CPCI (PCI Control FPGA)
// Description: Counters for the DMA engine
//
// Note: read and write are from the perspective of the driver.
// Read means retrieve a packet from the CNET and place in memory.
// Write means send a packet from memory to CNET.
//
// Change history: 12/9/07 - Split from the DMA engine
//
// Issues to address:
//
///////////////////////////////////////////////////////////////////////////////
module dma_engine_cntr (
// PCI Signals
input dma_data_vld, // Indicates data should be captured
// from pci_data during a read or
// that a data transaction has
// occured during a write.
input dma_src_en, // The next piece of data should
// be provided on dma_data
// CPCI register interface signals
input [31:0] dma_rd_addr, // Address when performing reads
input [31:0] dma_wr_addr, // Address when performing writes
output reg [31:0] dma_rd_size,// Packet size when performing reads
input [31:0] dma_wr_size, // Packet size when performing writes
// CNET DMA interface signals
input [31:0] dma_data_frm_cnet, // DMA data to be transfered
// DMA engine signals
output tx_wait_done, // TX wait counter expired
output to_cnet_done, // Finished transfering data to CNET
input retry, // Retry the transaction
input rd_undo, // Undo a read operation
input xfer_is_rd, // Transfer direction
input read_get_len, // Get the length for a read operation
input write_start, // Start a write operation
input read_from_cnet, // Just read a word from the cnet
input wr_data_rdy, // Data is ready to write into the write fifo
input rd_data_rdy, // Data is ready to write into the read fifo
input tx_wait_cnt_ld,// Load the tx wait conter
input ld_dma_addr, // Load the current DMA address
input ld_xfer_cnt, // Load the xfer cntr
output last_word_to_cnet, // Indicates last word going to CNET
output last_word_from_cnet, // Indicates last word coming from CNET
output reg [1:0] non_aligned_bytes, // Number of non-aligned bytes in first word
output reg [3:0] first_word_be, // Byte-Enable for the first word
output reg [3:0] last_word_be, // Byte-Enable for the last word
output reg [8:0] xfer_cnt_start, // Number of words to transfer
output reg [8:0] to_cnet_cnt_start,
output reg [`PCI_ADDR_WIDTH - 1 : 2] dma_addr, // Address to send to host
// Miscelaneous signals
input cnet_reprog, // Indicates that the CNET is
// currently being reprogrammed
input reset,
input clk
);
// ==================================================================
// Local
// ==================================================================
// Transfer counters
reg [8:0] from_cnet_cnt_start;
reg [8:0] to_cnet_cnt;
reg [8:0] from_cnet_cnt;
// Address pointer
reg [`PCI_ADDR_WIDTH - 1 : 2] start_addr;
// Transfer timer
reg [31:0] xfer_timer;
// Retry counter
reg [15:0] retry_cnt;
// Tx Wait counter
reg [8:0] tx_wait_cnt;
// ==================================================================
// Control state machine
// ==================================================================
wire [1:0] addr_word_offset;
assign addr_word_offset = xfer_is_rd ? dma_rd_addr[1:0] : dma_wr_addr[1:0];
always @(posedge clk)
begin
// On either reset or the CNET being reprogrammed, go to the idle state
if (reset || cnet_reprog) begin
xfer_cnt_start <= 'h0;
to_cnet_cnt_start <= 'h0;
from_cnet_cnt_start <= 'h0;
start_addr <= 'h0;
non_aligned_bytes <= 'h0;
first_word_be <= 'h0;
last_word_be <= 'h0;
dma_rd_size <= 'h0;
end
else begin
// Work out how many words to send to the CNET
to_cnet_cnt_start <= dma_wr_size[10:2] + (|(dma_wr_size[1:0]) ? 'h1 : 'h0);
// Capture the length of the transfer
if (read_get_len)
from_cnet_cnt_start <= dma_data_frm_cnet[10:2] + (|(dma_data_frm_cnet[1:0]) ? 'h1 : 'h0);
// Sample the target address
if (xfer_is_rd)
start_addr <= dma_rd_addr[`PCI_ADDR_WIDTH - 1 : 2];
else
start_addr <= dma_wr_addr[`PCI_ADDR_WIDTH - 1 : 2];
// Work out the number of words to transfer
//
// This logic may look weird but we have to take into
// account partial word transfers.
//
// The following table summarises the number of additional
// words to transfer on top of the dma_wr_size[10:2] or
// dma_data_frm_cnet[10:2]:
//
// | Len[1:0] |
// Addr[1:0] | 00 | 01 | 10 | 11 |
// =================================================|
// 00 | +0 | +1 | +1 | +1 |
// 01 | +1 | +1 | +1 | +1 |
// 10 | +1 | +1 | +1 | +2 |
// 11 | +1 | +1 | +2 | +2 |
if (read_get_len)
xfer_cnt_start <= dma_data_frm_cnet[10:2] +
(|{dma_data_frm_cnet[1:0], dma_rd_addr[1:0]}) +
(dma_data_frm_cnet[1] & dma_rd_addr[1] &
(dma_data_frm_cnet[0] | dma_rd_addr[0]));
else if (write_start)
xfer_cnt_start <= dma_wr_size[10:2] +
(|{dma_wr_size[1:0],dma_wr_addr[1:0]}) +
(dma_wr_size[1] & dma_wr_addr[1] &
(dma_wr_size[0] | dma_wr_addr[0]));
// Work out the number of non-aligned bytes to read/write in the
// first word
case (addr_word_offset)
2'b00 : begin
non_aligned_bytes <= 2'b00;
first_word_be <= 4'b0000;
end
2'b01 : begin
non_aligned_bytes <= 2'b11;
first_word_be <= 4'b1000;
end
2'b10 : begin
non_aligned_bytes <= 2'b10;
first_word_be <= 4'b1100;
end
default : begin
non_aligned_bytes <= 2'b01;
first_word_be <= 4'b1110;
end
endcase
if (read_get_len) begin
// Capture the length of the transfer
dma_rd_size <= dma_data_frm_cnet & 'hfff;
// Work out the byte enable for the final word
// Note: BE is active low
case (dma_data_frm_cnet[1:0] + dma_rd_addr[1:0])
2'b01 : last_word_be <= 4'b1000;
2'b10 : last_word_be <= 4'b1100;
2'b11 : last_word_be <= 4'b1110;
default : last_word_be <= 4'b1111;
endcase
end
else if (write_start) begin
// Work out the byte enable for the final word
// Note: BE is active low
case (dma_wr_size[1:0] + dma_wr_addr[1:0])
2'b01 : last_word_be <= 4'b1000;
2'b10 : last_word_be <= 4'b1100;
2'b11 : last_word_be <= 4'b1110;
default : last_word_be <= 4'b1111;
endcase
end
end
end
// ==================================================================
// Tx wait counter
// ==================================================================
always @(posedge clk)
if (reset)
tx_wait_cnt <= 'h0;
else if (tx_wait_cnt_ld)
tx_wait_cnt <= 'd400;
else if (tx_wait_cnt > 0)
tx_wait_cnt <= tx_wait_cnt - 'h1;
assign tx_wait_done = tx_wait_cnt == 'h0;
// ==================================================================
// Address counter
// ==================================================================
always @(posedge clk)
begin
if (reset || cnet_reprog)
dma_addr <= 'h0;
else if (ld_dma_addr)
dma_addr <= start_addr;
else if (dma_data_vld)
dma_addr <= dma_addr + 'h1;
end
// ==================================================================
// CNET tranfser counters
// ==================================================================
always @(posedge clk)
begin
if (reset || cnet_reprog)
to_cnet_cnt <= 'h0;
else if (ld_xfer_cnt)
to_cnet_cnt <= to_cnet_cnt_start;
else if (wr_data_rdy)
to_cnet_cnt <= to_cnet_cnt - 'h1;
end
always @(posedge clk)
begin
if (reset || cnet_reprog)
from_cnet_cnt <= 'h0;
else if (ld_xfer_cnt && read_from_cnet)
from_cnet_cnt <= from_cnet_cnt_start - 'h1;
else if (ld_xfer_cnt && !read_from_cnet)
from_cnet_cnt <= from_cnet_cnt_start;
else if (read_from_cnet)
from_cnet_cnt <= from_cnet_cnt - 'h1;
end
assign to_cnet_done = to_cnet_cnt == 'h0;
// Note: last_word_from_cnet is asserted on 'h2 due to delay in pipeline
assign last_word_to_cnet = to_cnet_cnt == 'h1;
assign last_word_from_cnet = from_cnet_cnt == 'h1;
endmodule // dma_engine_cntr
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_arb_mux
*/
module test_axis_arb_mux_4;
// Parameters
parameter S_COUNT = 4;
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter ARB_TYPE_ROUND_ROBIN = 0;
parameter ARB_LSB_HIGH_PRIORITY = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg [S_COUNT-1:0] s_axis_tvalid = 0;
reg [S_COUNT-1:0] s_axis_tlast = 0;
reg [S_COUNT*ID_WIDTH-1:0] s_axis_tid = 0;
reg [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [S_COUNT*USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire [S_COUNT-1:0] s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_axis_tdata,
s_axis_tkeep,
s_axis_tvalid,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tready
);
$to_myhdl(
s_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tvalid,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser
);
// dump file
$dumpfile("test_axis_arb_mux_4.lxt");
$dumpvars(0, test_axis_arb_mux_4);
end
axis_arb_mux #(
.S_COUNT(S_COUNT),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
UUT (
.clk(clk),
.rst(rst),
// AXI inputs
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser)
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright 2010-2012 by Michael A. Morris, dba M. A. Morris & Associates
//
// All rights reserved. The source code contained herein is publicly released
// under the terms and conditions of the GNU Lesser Public License. No part of
// this source code may be reproduced or transmitted in any form or by any
// means, electronic or mechanical, including photocopying, recording, or any
// information storage and retrieval system in violation of the license under
// which the source code is released.
//
// The souce code contained herein is free; it may be redistributed and/or
// modified in accordance with the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either version 2.1 of
// the GNU Lesser General Public License, or any later version.
//
// The souce code contained herein is freely released WITHOUT ANY WARRANTY;
// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
// PARTICULAR PURPOSE. (Refer to the GNU Lesser General Public License for
// more details.)
//
// A copy of the GNU Lesser General Public License should have been received
// along with the source code contained herein; if not, a copy can be obtained
// by writing to:
//
// Free Software Foundation, Inc.
// 51 Franklin Street, Fifth Floor
// Boston, MA 02110-1301 USA
//
// Further, no use of this source code is permitted in any form or means
// without inclusion of this banner prominently in any derived works.
//
// Michael A. Morris
// Huntsville, AL
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
///////////////////////////////////////////////////////////////////////////////
// Company: M. A. Morris & Associates
// Engineer: Michael A. Morris
//
// Create Date: 12:59:58 10/02/2010
// Design Name: Fast 4-bit Booth Multiplier
// Module Name: Booth_Multiplier_4x.v
// Project Name: Booth_Multiplier
// Target Devices: Spartan-3AN
// Tool versions: Xilinx ISE 10.1 SP3
//
// Description:
//
// This module implements a parameterized multiplier which uses a Modified
// Booth algorithm for its implementation. The implementation is based on the
// algorithm described in "Computer Organization", Hamacher et al, McGraw-
// Hill Book Company, New York, NY, 1978, ISBN: 0-07-025681-0.
//
// Compared to the standard, 1-bit at a time Booth algorithm, this modified
// Booth multiplier algorithm shifts the multiplier 4 bits at a time. Thus,
// this algorithm will compute a 2's complement product four times as fast as
// the base algorithm.
//
// Dependencies:
//
// Revision:
//
// 0.01 10J02 MAM File Created
//
// Additional Comments:
//
// The basic operations follow those of the standard Booth multiplier except
// that the transitions are being tracked across 4 bits plus the guard bit.
// The result is that the operations required are 0, ±1, ±2, ±3, ±4, ±5, ±6,
// ±7, and ±8 times the multiplicand (M). However, it is possible to reduce
// the number of partial products required to implement the multiplication to
// two. That is, ±3, ±5, ±6, and ±7 can be written in terms of combinations of
// ±1, ±2, ±4, and ±8. For example, 3M = (2M + 1M), 5M = (4M + M), 6M = (4M
// + 2M), and 7M = (8M - M). Thus, the following 32 entry table defines the
// operations required for generating the partial products through each pass
// of the algorithm over the multiplier:
//
// Prod[4:0] Operation
// 00000 Prod <= (Prod + 0*M + 0*M) >> 4;
// 00001 Prod <= (Prod + 0*M + 1*M) >> 4;
// 00010 Prod <= (Prod + 0*M + 1*M) >> 4;
// 00011 Prod <= (Prod + 2*M + 0*M) >> 4;
// 00100 Prod <= (Prod + 2*M + 0*M) >> 4;
// 00101 Prod <= (Prod + 2*M + 1*M) >> 4;
// 00110 Prod <= (Prod + 2*M + 1*M) >> 4;
// 00111 Prod <= (Prod + 4*M + 0*M) >> 4;
// 01000 Prod <= (Prod + 4*M + 0*M) >> 4;
// 01001 Prod <= (Prod + 4*M + 1*M) >> 4;
// 01010 Prod <= (Prod + 4*M + 1*M) >> 4;
// 01011 Prod <= (Prod + 4*M + 2*M) >> 4;
// 01100 Prod <= (Prod + 4*M + 2*M) >> 4;
// 01101 Prod <= (Prod + 8*M - 1*M) >> 4;
// 01110 Prod <= (Prod + 8*M - 1*M) >> 4;
// 01111 Prod <= (Prod + 8*M + 0*M) >> 4;
// 10000 Prod <= (Prod - 8*M - 0*M) >> 4;
// 10001 Prod <= (Prod - 8*M + 1*M) >> 4;
// 10010 Prod <= (Prod - 8*M + 1*M) >> 4;
// 10011 Prod <= (Prod - 4*M - 2*M) >> 4;
// 10100 Prod <= (Prod - 4*M - 2*M) >> 4;
// 10101 Prod <= (Prod - 4*M - 1*M) >> 4;
// 10110 Prod <= (Prod - 4*M - 1*M) >> 4;
// 10111 Prod <= (Prod - 4*M - 0*M) >> 4;
// 11000 Prod <= (Prod - 4*M - 0*M) >> 4;
// 11001 Prod <= (Prod - 2*M - 1*M) >> 4;
// 11010 Prod <= (Prod - 2*M - 1*M) >> 4;
// 11011 Prod <= (Prod - 2*M - 0*M) >> 4;
// 11100 Prod <= (Prod - 2*M - 0*M) >> 4;
// 11101 Prod <= (Prod - 0*M - 1*M) >> 4;
// 11110 Prod <= (Prod - 0*M - 1*M) >> 4;
// 11111 Prod <= (Prod - 0*M - 0*M) >> 4;
//
// A better implementation might be to consider implementing two simultaneous
// 4-bit partial products at a time, and combining the partial products after
// they are computed with an appropriate 4-bit shift in the rightmost partial
// product. This approach can be used to trade off complexity for speed. In
// the limit, this approach leads to the implementation of a parallel multi-
// plier. State-of-the-Art parallel multipliers are generally built in this
// manner, but they use arrays of small elements to compute the partial pro-
// ducts in a parallel manner. Typically these partial product generators are
// built around arrays of dual 4-bit inputs and 8-bit output adders with fast
// carry-propagate output carry generators.
//
///////////////////////////////////////////////////////////////////////////////
module Booth_Multiplier_4x #(
parameter N = 16 // Width = N: multiplicand & multiplier
)(
input Rst, // Reset
input Clk, // Clock
input Ld, // Load Registers and Start Multiplier
input [(N - 1):0] M, // Multiplicand
input [(N - 1):0] R, // Multiplier
output reg Valid, // Product Valid
output reg [((2*N) - 1):0] P // Product <= M * R
);
///////////////////////////////////////////////////////////////////////////////
//
// Local Parameters
//
localparam pNumCycles = ((N + 1)/4); // No. of cycles required for product
///////////////////////////////////////////////////////////////////////////////
//
// Declarations
//
reg [4:0] Cntr; // Operation Counter
reg [4:0] Booth; // Booth Recoding Field
reg Guard; // Shift Bit for Booth Recoding
reg [(N + 3):0] A; // Multiplicand w/ guards
reg [(N + 3):0] S; // Adder w/ guards
wire [(N + 3):0] Hi; // Upper Half of Product w/ guards
reg [((2*N) + 3):0] Prod; // Double Length Product w/ guards
///////////////////////////////////////////////////////////////////////////////
//
// Implementation
//
always @(posedge Clk)
begin
if(Rst)
Cntr <= #1 0;
else if(Ld)
Cntr <= #1 pNumCycles;
else if(|Cntr)
Cntr <= #1 (Cntr - 1);
end
// Multiplicand Register
// includes 4 bits to guard sign of multiplicand in the event the most
// negative value is provided as the input.
always @(posedge Clk)
begin
if(Rst)
A <= #1 0;
else if(Ld)
A <= #1 {{4{M[(N - 1)]}}, M};
end
// Compute Upper Partial Product: (N + 4) bits in width
always @(*) Booth <= {Prod[3:0], Guard}; // Booth's Multiplier Recoding fld
assign Hi = Prod[((2*N) + 3):N]; // Upper Half of Product Register
always @(*)
begin
case(Booth)
5'b00000 : S <= Hi; // Prod <= (Prod + 0*M + 0*M) >> 4;
5'b00001 : S <= Hi + A; // Prod <= (Prod + 0*M + 1*M) >> 4;
5'b00010 : S <= Hi + A; // Prod <= (Prod + 0*M + 1*M) >> 4;
5'b00011 : S <= Hi + {A, 1'b0}; // Prod <= (Prod + 2*M + 0*M) >> 4;
5'b00100 : S <= Hi + {A, 1'b0}; // Prod <= (Prod + 2*M + 0*M) >> 4;
5'b00101 : S <= Hi + {A, 1'b0} + A; // Prod <= (Prod + 2*M + 1*M) >> 4;
5'b00110 : S <= Hi + {A, 1'b0} + A; // Prod <= (Prod + 2*M + 1*M) >> 4;
5'b00111 : S <= Hi + {A, 2'b0}; // Prod <= (Prod + 4*M + 0*M) >> 4;
5'b01000 : S <= Hi + {A, 2'b0}; // Prod <= (Prod + 4*M + 0*M) >> 4;
5'b01001 : S <= Hi + {A, 2'b0} + A; // Prod <= (Prod + 4*M + 1*M) >> 4;
5'b01010 : S <= Hi + {A, 2'b0} + A; // Prod <= (Prod + 4*M + 1*M) >> 4;
5'b01011 : S <= Hi + {A, 2'b0} + {A, 1'b0}; // Prod <= (Prod + 4*M + 2*M) >> 4;
5'b01100 : S <= Hi + {A, 2'b0} + {A, 1'b0}; // Prod <= (Prod + 4*M + 2*M) >> 4;
5'b01101 : S <= Hi + {A, 3'b0} - A; // Prod <= (Prod + 8*M - 1*M) >> 4;
5'b01110 : S <= Hi + {A, 3'b0} - A; // Prod <= (Prod + 8*M - 1*M) >> 4;
5'b01111 : S <= Hi + {A, 3'b0}; // Prod <= (Prod + 8*M + 0*M) >> 4;
5'b10000 : S <= Hi - {A, 3'b0}; // Prod <= (Prod - 8*M - 0*M) >> 4;
5'b10001 : S <= Hi - {A, 3'b0} + A; // Prod <= (Prod - 8*M + 1*M) >> 4;
5'b10010 : S <= Hi - {A, 3'b0} + A; // Prod <= (Prod - 8*M + 1*M) >> 4;
5'b10011 : S <= Hi - {A, 2'b0} - {A, 1'b0}; // Prod <= (Prod - 4*M - 2*M) >> 4;
5'b10100 : S <= Hi - {A, 2'b0} - {A, 1'b0}; // Prod <= (Prod - 4*M - 2*M) >> 4;
5'b10101 : S <= Hi - {A, 2'b0} - A; // Prod <= (Prod - 4*M - 1*M) >> 4;
5'b10110 : S <= Hi - {A, 2'b0} - A; // Prod <= (Prod - 4*M - 1*M) >> 4;
5'b10111 : S <= Hi - {A, 2'b0}; // Prod <= (Prod - 4*M - 0*M) >> 4;
5'b11000 : S <= Hi - {A, 2'b0}; // Prod <= (Prod - 4*M - 0*M) >> 4;
5'b11001 : S <= Hi - {A, 1'b0} - A; // Prod <= (Prod - 2*M - 1*M) >> 4;
5'b11010 : S <= Hi - {A, 1'b0} - A; // Prod <= (Prod - 2*M - 1*M) >> 4;
5'b11011 : S <= Hi - {A, 1'b0}; // Prod <= (Prod - 2*M - 0*M) >> 4;
5'b11100 : S <= Hi - {A, 1'b0}; // Prod <= (Prod - 2*M - 0*M) >> 4;
5'b11101 : S <= Hi - A; // Prod <= (Prod - 0*M - 1*M) >> 4;
5'b11110 : S <= Hi - A; // Prod <= (Prod - 0*M - 1*M) >> 4;
5'b11111 : S <= Hi; // Prod <= (Prod - 0*M - 0*M) >> 4;
endcase
end
// Double Length Product Register
// Multiplier, R, is loaded into the least significant half on load, Ld
// Shifted right four places as the product is computed iteratively.
always @(posedge Clk)
begin
if(Rst)
Prod <= #1 0;
else if(Ld)
Prod <= #1 R;
else if(|Cntr) // Shift right four bits
Prod <= #1 {{4{S[(N + 3)]}}, S, Prod[(N - 1):4]};
end
always @(posedge Clk)
begin
if(Rst)
Guard <= #1 0;
else if(Ld)
Guard <= #1 0;
else if(|Cntr)
Guard <= #1 Prod[3];
end
// Assign the product less the four guard bits to the output port
// A 4-bit right shift is required since the output product is stored
// into a synchronous register on the last cycle of the multiply.
always @(posedge Clk)
begin
if(Rst)
P <= #1 0;
else if(Cntr == 1)
P <= #1 {S, Prod[(N - 1):4]};
end
// Count the number of shifts
// This implementation does not use any optimizations to perform multiple
// bit shifts to skip over runs of 1s or 0s.
always @(posedge Clk)
begin
if(Rst)
Valid <= #1 0;
else
Valid <= #1 (Cntr == 1);
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:12:09 08/01/2014
// Design Name:
// Module Name: clk_divider
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module clk_divider( sysclk, slowclk );
input sysclk; // Original Timer Clock in 100MHz
output slowclk; // Slow Clock set to 1MHz, divide by 100 times
reg [6:0] counter; // 'D50 = 6'b110010
reg slowclock;
initial begin
counter = 0;
slowclock = 1;
end
always @ (posedge sysclk) begin
if(counter == 'D50) begin
counter <= 0;
slowclock <= ~slowclock;
end else begin
counter <= counter + 1;
end
end
assign slowclk = slowclock;
endmodule
|
// system_acl_iface_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module system_acl_iface_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
system_acl_iface_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
//
// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
//
// On Mon Feb 3 15:00:16 EST 2014
//
//
// Ports:
// Name I/O size props
// RDY_server_request_put O 1 reg
// server_response_get O 40
// RDY_server_response_get O 1 reg
// client0_request_get O 40
// RDY_client0_request_get O 1 reg
// RDY_client0_response_put O 1 reg
// client1_request_get O 40
// RDY_client1_request_get O 1 reg
// RDY_client1_response_put O 1 reg
// client2_request_get O 40
// RDY_client2_request_get O 1 reg
// RDY_client2_response_put O 1 reg
// et0 I 16
// did I 16
// CLK I 1 clock
// RST_N I 1 reset
// server_request_put I 40
// client0_response_put I 40
// client1_response_put I 40
// client2_response_put I 40
// EN_server_request_put I 1
// EN_client0_response_put I 1
// EN_client1_response_put I 1
// EN_client2_response_put I 1
// EN_server_response_get I 1
// EN_client0_request_get I 1
// EN_client1_request_get I 1
// EN_client2_request_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkQABSMF3(et0,
did,
CLK,
RST_N,
server_request_put,
EN_server_request_put,
RDY_server_request_put,
EN_server_response_get,
server_response_get,
RDY_server_response_get,
EN_client0_request_get,
client0_request_get,
RDY_client0_request_get,
client0_response_put,
EN_client0_response_put,
RDY_client0_response_put,
EN_client1_request_get,
client1_request_get,
RDY_client1_request_get,
client1_response_put,
EN_client1_response_put,
RDY_client1_response_put,
EN_client2_request_get,
client2_request_get,
RDY_client2_request_get,
client2_response_put,
EN_client2_response_put,
RDY_client2_response_put);
input [15 : 0] et0;
input [15 : 0] did;
input CLK;
input RST_N;
// action method server_request_put
input [39 : 0] server_request_put;
input EN_server_request_put;
output RDY_server_request_put;
// actionvalue method server_response_get
input EN_server_response_get;
output [39 : 0] server_response_get;
output RDY_server_response_get;
// actionvalue method client0_request_get
input EN_client0_request_get;
output [39 : 0] client0_request_get;
output RDY_client0_request_get;
// action method client0_response_put
input [39 : 0] client0_response_put;
input EN_client0_response_put;
output RDY_client0_response_put;
// actionvalue method client1_request_get
input EN_client1_request_get;
output [39 : 0] client1_request_get;
output RDY_client1_request_get;
// action method client1_response_put
input [39 : 0] client1_response_put;
input EN_client1_response_put;
output RDY_client1_response_put;
// actionvalue method client2_request_get
input EN_client2_request_get;
output [39 : 0] client2_request_get;
output RDY_client2_request_get;
// action method client2_response_put
input [39 : 0] client2_response_put;
input EN_client2_response_put;
output RDY_client2_response_put;
// signals for module outputs
wire [39 : 0] client0_request_get,
client1_request_get,
client2_request_get,
server_response_get;
wire RDY_client0_request_get,
RDY_client0_response_put,
RDY_client1_request_get,
RDY_client1_response_put,
RDY_client2_request_get,
RDY_client2_response_put,
RDY_server_request_put,
RDY_server_response_get;
// register fork0_decided
reg fork0_decided;
wire fork0_decided_D_IN, fork0_decided_EN;
// register fork0_match0
reg fork0_match0;
wire fork0_match0_D_IN, fork0_match0_EN;
// register fork0_ptr
reg [2 : 0] fork0_ptr;
reg [2 : 0] fork0_ptr_D_IN;
wire fork0_ptr_EN;
// register fork0_sr
reg [119 : 0] fork0_sr;
wire [119 : 0] fork0_sr_D_IN;
wire fork0_sr_EN;
// register fork0_stageSent
reg fork0_stageSent;
wire fork0_stageSent_D_IN, fork0_stageSent_EN;
// register fork0_staged
reg fork0_staged;
wire fork0_staged_D_IN, fork0_staged_EN;
// register fork1_decided
reg fork1_decided;
wire fork1_decided_D_IN, fork1_decided_EN;
// register fork1_match0
reg fork1_match0;
wire fork1_match0_D_IN, fork1_match0_EN;
// register fork1_ptr
reg [2 : 0] fork1_ptr;
reg [2 : 0] fork1_ptr_D_IN;
wire fork1_ptr_EN;
// register fork1_sr
reg [119 : 0] fork1_sr;
wire [119 : 0] fork1_sr_D_IN;
wire fork1_sr_EN;
// register fork1_stageSent
reg fork1_stageSent;
wire fork1_stageSent_D_IN, fork1_stageSent_EN;
// register fork1_staged
reg fork1_staged;
wire fork1_staged_D_IN, fork1_staged_EN;
// register merge0_fi0Active
reg merge0_fi0Active;
wire merge0_fi0Active_D_IN, merge0_fi0Active_EN;
// register merge0_fi0HasPrio
reg merge0_fi0HasPrio;
reg merge0_fi0HasPrio_D_IN;
wire merge0_fi0HasPrio_EN;
// register merge0_fi1Active
reg merge0_fi1Active;
wire merge0_fi1Active_D_IN, merge0_fi1Active_EN;
// register merge1_fi0Active
reg merge1_fi0Active;
wire merge1_fi0Active_D_IN, merge1_fi0Active_EN;
// register merge1_fi0HasPrio
reg merge1_fi0HasPrio;
reg merge1_fi0HasPrio_D_IN;
wire merge1_fi0HasPrio_EN;
// register merge1_fi1Active
reg merge1_fi1Active;
wire merge1_fi1Active_D_IN, merge1_fi1Active_EN;
// ports of submodule fork0_d0F
wire [39 : 0] fork0_d0F_D_IN, fork0_d0F_D_OUT;
wire fork0_d0F_CLR,
fork0_d0F_DEQ,
fork0_d0F_EMPTY_N,
fork0_d0F_ENQ,
fork0_d0F_FULL_N;
// ports of submodule fork0_d1F
wire [39 : 0] fork0_d1F_D_IN, fork0_d1F_D_OUT;
wire fork0_d1F_CLR,
fork0_d1F_DEQ,
fork0_d1F_EMPTY_N,
fork0_d1F_ENQ,
fork0_d1F_FULL_N;
// ports of submodule fork0_srcF
wire [39 : 0] fork0_srcF_D_IN, fork0_srcF_D_OUT;
wire fork0_srcF_CLR,
fork0_srcF_DEQ,
fork0_srcF_EMPTY_N,
fork0_srcF_ENQ,
fork0_srcF_FULL_N;
// ports of submodule fork1_d0F
wire [39 : 0] fork1_d0F_D_IN, fork1_d0F_D_OUT;
wire fork1_d0F_CLR,
fork1_d0F_DEQ,
fork1_d0F_EMPTY_N,
fork1_d0F_ENQ,
fork1_d0F_FULL_N;
// ports of submodule fork1_d1F
wire [39 : 0] fork1_d1F_D_IN, fork1_d1F_D_OUT;
wire fork1_d1F_CLR,
fork1_d1F_DEQ,
fork1_d1F_EMPTY_N,
fork1_d1F_ENQ,
fork1_d1F_FULL_N;
// ports of submodule fork1_srcF
wire [39 : 0] fork1_srcF_D_IN, fork1_srcF_D_OUT;
wire fork1_srcF_CLR,
fork1_srcF_DEQ,
fork1_srcF_EMPTY_N,
fork1_srcF_ENQ,
fork1_srcF_FULL_N;
// ports of submodule merge0_fi0
wire [39 : 0] merge0_fi0_D_IN, merge0_fi0_D_OUT;
wire merge0_fi0_CLR,
merge0_fi0_DEQ,
merge0_fi0_EMPTY_N,
merge0_fi0_ENQ,
merge0_fi0_FULL_N;
// ports of submodule merge0_fi1
wire [39 : 0] merge0_fi1_D_IN, merge0_fi1_D_OUT;
wire merge0_fi1_CLR,
merge0_fi1_DEQ,
merge0_fi1_EMPTY_N,
merge0_fi1_ENQ,
merge0_fi1_FULL_N;
// ports of submodule merge0_fo
reg [39 : 0] merge0_fo_D_IN;
wire [39 : 0] merge0_fo_D_OUT;
wire merge0_fo_CLR,
merge0_fo_DEQ,
merge0_fo_EMPTY_N,
merge0_fo_ENQ,
merge0_fo_FULL_N;
// ports of submodule merge1_fi0
wire [39 : 0] merge1_fi0_D_IN, merge1_fi0_D_OUT;
wire merge1_fi0_CLR,
merge1_fi0_DEQ,
merge1_fi0_EMPTY_N,
merge1_fi0_ENQ,
merge1_fi0_FULL_N;
// ports of submodule merge1_fi1
wire [39 : 0] merge1_fi1_D_IN, merge1_fi1_D_OUT;
wire merge1_fi1_CLR,
merge1_fi1_DEQ,
merge1_fi1_EMPTY_N,
merge1_fi1_ENQ,
merge1_fi1_FULL_N;
// ports of submodule merge1_fo
reg [39 : 0] merge1_fo_D_IN;
wire [39 : 0] merge1_fo_D_OUT;
wire merge1_fo_CLR,
merge1_fo_DEQ,
merge1_fo_EMPTY_N,
merge1_fo_ENQ,
merge1_fo_FULL_N;
// rule scheduling signals
wire WILL_FIRE_RL_fork0_decide,
WILL_FIRE_RL_fork0_egress,
WILL_FIRE_RL_fork0_stage,
WILL_FIRE_RL_fork1_decide,
WILL_FIRE_RL_fork1_egress,
WILL_FIRE_RL_fork1_stage,
WILL_FIRE_RL_merge0_arbitrate,
WILL_FIRE_RL_merge0_fi0_advance,
WILL_FIRE_RL_merge0_fi1_advance,
WILL_FIRE_RL_merge1_arbitrate,
WILL_FIRE_RL_merge1_fi0_advance,
WILL_FIRE_RL_merge1_fi1_advance;
// inputs to muxes for submodule ports
wire [39 : 0] MUX_merge0_fo_enq_1__VAL_1,
MUX_merge0_fo_enq_1__VAL_2,
MUX_merge0_fo_enq_1__VAL_3,
MUX_merge1_fo_enq_1__VAL_1,
MUX_merge1_fo_enq_1__VAL_2,
MUX_merge1_fo_enq_1__VAL_3;
wire [2 : 0] MUX_fork0_ptr_write_1__VAL_1,
MUX_fork0_ptr_write_1__VAL_2,
MUX_fork1_ptr_write_1__VAL_1,
MUX_fork1_ptr_write_1__VAL_2;
wire MUX_fork0_decided_write_1__SEL_1,
MUX_fork0_ptr_write_1__SEL_1,
MUX_fork1_decided_write_1__SEL_1,
MUX_fork1_ptr_write_1__SEL_1,
MUX_merge0_fi0Active_write_1__SEL_1,
MUX_merge0_fi0Active_write_1__VAL_1,
MUX_merge0_fi0Active_write_1__VAL_2,
MUX_merge0_fi1Active_write_1__SEL_1,
MUX_merge0_fi1Active_write_1__VAL_2,
MUX_merge1_fi0Active_write_1__SEL_1,
MUX_merge1_fi0Active_write_1__VAL_1,
MUX_merge1_fi0Active_write_1__VAL_2,
MUX_merge1_fi1Active_write_1__SEL_1,
MUX_merge1_fi1Active_write_1__VAL_2;
// remaining internal signals
reg [7 : 0] SEL_ARR_fork0_sr_94_BITS_17_TO_10_51_fork0_sr__ETC___d553,
SEL_ARR_fork0_sr_94_BITS_27_TO_20_31_fork0_sr__ETC___d533,
SEL_ARR_fork0_sr_94_BITS_37_TO_30_12_fork0_sr__ETC___d514,
SEL_ARR_fork0_sr_94_BITS_7_TO_0_70_fork0_sr_94_ETC___d572,
SEL_ARR_fork1_sr_43_BITS_17_TO_10_00_fork1_sr__ETC___d802,
SEL_ARR_fork1_sr_43_BITS_27_TO_20_80_fork1_sr__ETC___d782,
SEL_ARR_fork1_sr_43_BITS_37_TO_30_61_fork1_sr__ETC___d763,
SEL_ARR_fork1_sr_43_BITS_7_TO_0_19_fork1_sr_43_ETC___d821;
reg [1 : 0] CASE_client0_response_put_BITS_19_TO_18_0_clie_ETC__q91,
CASE_client0_response_put_BITS_29_TO_28_0_clie_ETC__q90,
CASE_client0_response_put_BITS_39_TO_38_0_clie_ETC__q89,
CASE_client0_response_put_BITS_9_TO_8_0_client_ETC__q92,
CASE_client1_response_put_BITS_19_TO_18_0_clie_ETC__q99,
CASE_client1_response_put_BITS_29_TO_28_0_clie_ETC__q98,
CASE_client1_response_put_BITS_39_TO_38_0_clie_ETC__q97,
CASE_client1_response_put_BITS_9_TO_8_0_client_ETC__q100,
CASE_client2_response_put_BITS_19_TO_18_0_clie_ETC__q103,
CASE_client2_response_put_BITS_29_TO_28_0_clie_ETC__q102,
CASE_client2_response_put_BITS_39_TO_38_0_clie_ETC__q101,
CASE_client2_response_put_BITS_9_TO_8_0_client_ETC__q104,
CASE_fork0_d0FD_OUT_BITS_19_TO_18_0_fork0_d0F_ETC__q7,
CASE_fork0_d0FD_OUT_BITS_29_TO_28_0_fork0_d0F_ETC__q6,
CASE_fork0_d0FD_OUT_BITS_39_TO_38_0_fork0_d0F_ETC__q5,
CASE_fork0_d0FD_OUT_BITS_9_TO_8_0_fork0_d0FD_ETC__q8,
CASE_fork0_d1FD_OUT_BITS_19_TO_18_0_fork0_d1F_ETC__q87,
CASE_fork0_d1FD_OUT_BITS_29_TO_28_0_fork0_d1F_ETC__q86,
CASE_fork0_d1FD_OUT_BITS_39_TO_38_0_fork0_d1F_ETC__q85,
CASE_fork0_d1FD_OUT_BITS_9_TO_8_0_fork0_d1FD_ETC__q88,
CASE_fork0_sr_BITS_109_TO_108_0_fork0_sr_BITS__ETC__q66,
CASE_fork0_sr_BITS_119_TO_118_0_fork0_sr_BITS__ETC__q65,
CASE_fork0_sr_BITS_49_TO_48_0_fork0_sr_BITS_49_ETC__q72,
CASE_fork0_sr_BITS_59_TO_58_0_fork0_sr_BITS_59_ETC__q71,
CASE_fork0_sr_BITS_69_TO_68_0_fork0_sr_BITS_69_ETC__q70,
CASE_fork0_sr_BITS_79_TO_78_0_fork0_sr_BITS_79_ETC__q69,
CASE_fork0_sr_BITS_89_TO_88_0_fork0_sr_BITS_89_ETC__q68,
CASE_fork0_sr_BITS_99_TO_98_0_fork0_sr_BITS_99_ETC__q67,
CASE_fork0_srcFD_OUT_BITS_19_TO_18_0_fork0_sr_ETC__q29,
CASE_fork0_srcFD_OUT_BITS_29_TO_28_0_fork0_sr_ETC__q28,
CASE_fork0_srcFD_OUT_BITS_39_TO_38_0_fork0_sr_ETC__q27,
CASE_fork0_srcFD_OUT_BITS_9_TO_8_0_fork0_srcF_ETC__q30,
CASE_fork1_d0FD_OUT_BITS_19_TO_18_0_fork1_d0F_ETC__q3,
CASE_fork1_d0FD_OUT_BITS_29_TO_28_0_fork1_d0F_ETC__q2,
CASE_fork1_d0FD_OUT_BITS_39_TO_38_0_fork1_d0F_ETC__q1,
CASE_fork1_d0FD_OUT_BITS_9_TO_8_0_fork1_d0FD_ETC__q4,
CASE_fork1_d1FD_OUT_BITS_19_TO_18_0_fork1_d1F_ETC__q15,
CASE_fork1_d1FD_OUT_BITS_29_TO_28_0_fork1_d1F_ETC__q14,
CASE_fork1_d1FD_OUT_BITS_39_TO_38_0_fork1_d1F_ETC__q13,
CASE_fork1_d1FD_OUT_BITS_9_TO_8_0_fork1_d1FD_ETC__q16,
CASE_fork1_sr_BITS_109_TO_108_0_fork1_sr_BITS__ETC__q78,
CASE_fork1_sr_BITS_119_TO_118_0_fork1_sr_BITS__ETC__q77,
CASE_fork1_sr_BITS_49_TO_48_0_fork1_sr_BITS_49_ETC__q84,
CASE_fork1_sr_BITS_59_TO_58_0_fork1_sr_BITS_59_ETC__q83,
CASE_fork1_sr_BITS_69_TO_68_0_fork1_sr_BITS_69_ETC__q82,
CASE_fork1_sr_BITS_79_TO_78_0_fork1_sr_BITS_79_ETC__q81,
CASE_fork1_sr_BITS_89_TO_88_0_fork1_sr_BITS_89_ETC__q80,
CASE_fork1_sr_BITS_99_TO_98_0_fork1_sr_BITS_99_ETC__q79,
CASE_fork1_srcFD_OUT_BITS_19_TO_18_0_fork1_sr_ETC__q25,
CASE_fork1_srcFD_OUT_BITS_29_TO_28_0_fork1_sr_ETC__q24,
CASE_fork1_srcFD_OUT_BITS_39_TO_38_0_fork1_sr_ETC__q23,
CASE_fork1_srcFD_OUT_BITS_9_TO_8_0_fork1_srcF_ETC__q26,
CASE_merge0_fi0D_OUT_BITS_19_TO_18_0_merge0_f_ETC__q51,
CASE_merge0_fi0D_OUT_BITS_29_TO_28_0_merge0_f_ETC__q50,
CASE_merge0_fi0D_OUT_BITS_39_TO_38_0_merge0_f_ETC__q49,
CASE_merge0_fi0D_OUT_BITS_9_TO_8_0_merge0_fi0_ETC__q52,
CASE_merge0_fi1D_OUT_BITS_19_TO_18_0_merge0_f_ETC__q55,
CASE_merge0_fi1D_OUT_BITS_29_TO_28_0_merge0_f_ETC__q54,
CASE_merge0_fi1D_OUT_BITS_39_TO_38_0_merge0_f_ETC__q53,
CASE_merge0_fi1D_OUT_BITS_9_TO_8_0_merge0_fi1_ETC__q56,
CASE_merge0_foD_OUT_BITS_19_TO_18_0_merge0_fo_ETC__q11,
CASE_merge0_foD_OUT_BITS_29_TO_28_0_merge0_fo_ETC__q10,
CASE_merge0_foD_OUT_BITS_39_TO_38_0_merge0_fo_ETC__q9,
CASE_merge0_foD_OUT_BITS_9_TO_8_0_merge0_foD_ETC__q12,
CASE_merge1_fi0D_OUT_BITS_19_TO_18_0_merge1_f_ETC__q59,
CASE_merge1_fi0D_OUT_BITS_29_TO_28_0_merge1_f_ETC__q58,
CASE_merge1_fi0D_OUT_BITS_39_TO_38_0_merge1_f_ETC__q57,
CASE_merge1_fi0D_OUT_BITS_9_TO_8_0_merge1_fi0_ETC__q60,
CASE_merge1_fi1D_OUT_BITS_19_TO_18_0_merge1_f_ETC__q63,
CASE_merge1_fi1D_OUT_BITS_29_TO_28_0_merge1_f_ETC__q62,
CASE_merge1_fi1D_OUT_BITS_39_TO_38_0_merge1_f_ETC__q61,
CASE_merge1_fi1D_OUT_BITS_9_TO_8_0_merge1_fi1_ETC__q64,
CASE_merge1_foD_OUT_BITS_19_TO_18_0_merge1_fo_ETC__q95,
CASE_merge1_foD_OUT_BITS_29_TO_28_0_merge1_fo_ETC__q94,
CASE_merge1_foD_OUT_BITS_39_TO_38_0_merge1_fo_ETC__q93,
CASE_merge1_foD_OUT_BITS_9_TO_8_0_merge1_foD_ETC__q96,
CASE_server_request_put_BITS_19_TO_18_0_server_ETC__q75,
CASE_server_request_put_BITS_29_TO_28_0_server_ETC__q74,
CASE_server_request_put_BITS_39_TO_38_0_server_ETC__q73,
CASE_server_request_put_BITS_9_TO_8_0_server_r_ETC__q76;
reg CASE_fork0_ptr_0_fork0_sr_BITS_19_TO_18_EQ_0_1_ETC__q39,
CASE_fork0_ptr_0_fork0_sr_BITS_19_TO_18_EQ_1_1_ETC__q38,
CASE_fork0_ptr_0_fork0_sr_BITS_19_TO_18_EQ_2_1_ETC__q37,
CASE_fork0_ptr_0_fork0_sr_BITS_29_TO_28_EQ_0_1_ETC__q22,
CASE_fork0_ptr_0_fork0_sr_BITS_29_TO_28_EQ_1_1_ETC__q21,
CASE_fork0_ptr_0_fork0_sr_BITS_29_TO_28_EQ_2_1_ETC__q20,
CASE_fork0_ptr_0_fork0_sr_BITS_39_TO_38_EQ_0_1_ETC__q19,
CASE_fork0_ptr_0_fork0_sr_BITS_39_TO_38_EQ_1_1_ETC__q18,
CASE_fork0_ptr_0_fork0_sr_BITS_39_TO_38_EQ_2_1_ETC__q17,
CASE_fork0_ptr_0_fork0_sr_BITS_9_TO_8_EQ_0_1_f_ETC__q42,
CASE_fork0_ptr_0_fork0_sr_BITS_9_TO_8_EQ_1_1_f_ETC__q41,
CASE_fork0_ptr_0_fork0_sr_BITS_9_TO_8_EQ_2_1_f_ETC__q40,
CASE_fork1_ptr_0_fork1_sr_BITS_19_TO_18_EQ_0_1_ETC__q45,
CASE_fork1_ptr_0_fork1_sr_BITS_19_TO_18_EQ_1_1_ETC__q44,
CASE_fork1_ptr_0_fork1_sr_BITS_19_TO_18_EQ_2_1_ETC__q43,
CASE_fork1_ptr_0_fork1_sr_BITS_29_TO_28_EQ_0_1_ETC__q36,
CASE_fork1_ptr_0_fork1_sr_BITS_29_TO_28_EQ_1_1_ETC__q35,
CASE_fork1_ptr_0_fork1_sr_BITS_29_TO_28_EQ_2_1_ETC__q34,
CASE_fork1_ptr_0_fork1_sr_BITS_39_TO_38_EQ_0_1_ETC__q33,
CASE_fork1_ptr_0_fork1_sr_BITS_39_TO_38_EQ_1_1_ETC__q32,
CASE_fork1_ptr_0_fork1_sr_BITS_39_TO_38_EQ_2_1_ETC__q31,
CASE_fork1_ptr_0_fork1_sr_BITS_9_TO_8_EQ_0_1_f_ETC__q48,
CASE_fork1_ptr_0_fork1_sr_BITS_9_TO_8_EQ_1_1_f_ETC__q47,
CASE_fork1_ptr_0_fork1_sr_BITS_9_TO_8_EQ_2_1_f_ETC__q46;
wire [39 : 0] IF_fork0_srcF_first__50_BITS_39_TO_38_51_EQ_0__ETC___d393,
IF_fork1_srcF_first__99_BITS_39_TO_38_00_EQ_0__ETC___d642;
wire [19 : 0] IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d147,
IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d318;
wire [15 : 0] seen__h14989, seen__h24820;
wire [9 : 0] IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d135,
IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d145,
IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d156,
IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d166,
IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d306,
IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d316,
IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d327,
IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d337,
IF_SEL_ARR_fork0_sr_94_BITS_19_TO_18_47_EQ_0_4_ETC___d565,
IF_SEL_ARR_fork0_sr_94_BITS_19_TO_18_47_EQ_1_5_ETC___d564,
IF_SEL_ARR_fork0_sr_94_BITS_19_TO_18_47_EQ_2_5_ETC___d563,
IF_SEL_ARR_fork0_sr_94_BITS_29_TO_28_27_EQ_0_2_ETC___d545,
IF_SEL_ARR_fork0_sr_94_BITS_29_TO_28_27_EQ_1_3_ETC___d544,
IF_SEL_ARR_fork0_sr_94_BITS_29_TO_28_27_EQ_2_3_ETC___d543,
IF_SEL_ARR_fork0_sr_94_BITS_39_TO_38_08_EQ_0_0_ETC___d526,
IF_SEL_ARR_fork0_sr_94_BITS_39_TO_38_08_EQ_1_1_ETC___d525,
IF_SEL_ARR_fork0_sr_94_BITS_39_TO_38_08_EQ_2_2_ETC___d524,
IF_SEL_ARR_fork0_sr_94_BITS_9_TO_8_66_EQ_0_67__ETC___d584,
IF_SEL_ARR_fork0_sr_94_BITS_9_TO_8_66_EQ_1_74__ETC___d583,
IF_SEL_ARR_fork0_sr_94_BITS_9_TO_8_66_EQ_2_78__ETC___d582,
IF_SEL_ARR_fork1_sr_43_BITS_19_TO_18_96_EQ_0_9_ETC___d814,
IF_SEL_ARR_fork1_sr_43_BITS_19_TO_18_96_EQ_1_0_ETC___d813,
IF_SEL_ARR_fork1_sr_43_BITS_19_TO_18_96_EQ_2_0_ETC___d812,
IF_SEL_ARR_fork1_sr_43_BITS_29_TO_28_76_EQ_0_7_ETC___d794,
IF_SEL_ARR_fork1_sr_43_BITS_29_TO_28_76_EQ_1_8_ETC___d793,
IF_SEL_ARR_fork1_sr_43_BITS_29_TO_28_76_EQ_2_8_ETC___d792,
IF_SEL_ARR_fork1_sr_43_BITS_39_TO_38_57_EQ_0_5_ETC___d775,
IF_SEL_ARR_fork1_sr_43_BITS_39_TO_38_57_EQ_1_6_ETC___d774,
IF_SEL_ARR_fork1_sr_43_BITS_39_TO_38_57_EQ_2_6_ETC___d773,
IF_SEL_ARR_fork1_sr_43_BITS_9_TO_8_15_EQ_0_16__ETC___d833,
IF_SEL_ARR_fork1_sr_43_BITS_9_TO_8_15_EQ_1_23__ETC___d832,
IF_SEL_ARR_fork1_sr_43_BITS_9_TO_8_15_EQ_2_27__ETC___d831;
wire [7 : 0] IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d128,
IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d138,
IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d149,
IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d159,
IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d299,
IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d309,
IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d320,
IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d330;
wire [2 : 0] fork0_ptr_90_PLUS_1___d491, fork1_ptr_39_PLUS_1___d740;
wire [1 : 0] IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d133,
IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d143,
IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d154,
IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d164,
IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d304,
IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d314,
IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d325,
IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d335;
wire IF_merge0_fi0HasPrio_06_THEN_NOT_merge0_fi0_i__ETC___d113,
IF_merge0_fi0HasPrio_06_THEN_NOT_merge0_fi0_i__ETC___d115,
IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d127,
IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d137,
IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d148,
IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d158,
IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_i_notE_ETC___d118,
IF_merge1_fi0HasPrio_77_THEN_NOT_merge1_fi0_i__ETC___d284,
IF_merge1_fi0HasPrio_77_THEN_NOT_merge1_fi0_i__ETC___d286,
IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d298,
IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d308,
IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d319,
IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d329,
IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_i_notE_ETC___d289,
NOT_fork0_stageSent_98_99_OR_fork0_srcF_i_notE_ETC___d505,
NOT_fork1_stageSent_47_48_OR_fork1_srcF_i_notE_ETC___d754;
// action method server_request_put
assign RDY_server_request_put = fork0_srcF_FULL_N ;
// actionvalue method server_response_get
assign server_response_get =
{ CASE_merge0_foD_OUT_BITS_39_TO_38_0_merge0_fo_ETC__q9,
merge0_fo_D_OUT[37:30],
CASE_merge0_foD_OUT_BITS_29_TO_28_0_merge0_fo_ETC__q10,
merge0_fo_D_OUT[27:20],
CASE_merge0_foD_OUT_BITS_19_TO_18_0_merge0_fo_ETC__q11,
merge0_fo_D_OUT[17:10],
CASE_merge0_foD_OUT_BITS_9_TO_8_0_merge0_foD_ETC__q12,
merge0_fo_D_OUT[7:0] } ;
assign RDY_server_response_get = merge0_fo_EMPTY_N ;
// actionvalue method client0_request_get
assign client0_request_get =
{ CASE_fork0_d0FD_OUT_BITS_39_TO_38_0_fork0_d0F_ETC__q5,
fork0_d0F_D_OUT[37:30],
CASE_fork0_d0FD_OUT_BITS_29_TO_28_0_fork0_d0F_ETC__q6,
fork0_d0F_D_OUT[27:20],
CASE_fork0_d0FD_OUT_BITS_19_TO_18_0_fork0_d0F_ETC__q7,
fork0_d0F_D_OUT[17:10],
CASE_fork0_d0FD_OUT_BITS_9_TO_8_0_fork0_d0FD_ETC__q8,
fork0_d0F_D_OUT[7:0] } ;
assign RDY_client0_request_get = fork0_d0F_EMPTY_N ;
// action method client0_response_put
assign RDY_client0_response_put = merge0_fi0_FULL_N ;
// actionvalue method client1_request_get
assign client1_request_get =
{ CASE_fork1_d0FD_OUT_BITS_39_TO_38_0_fork1_d0F_ETC__q1,
fork1_d0F_D_OUT[37:30],
CASE_fork1_d0FD_OUT_BITS_29_TO_28_0_fork1_d0F_ETC__q2,
fork1_d0F_D_OUT[27:20],
CASE_fork1_d0FD_OUT_BITS_19_TO_18_0_fork1_d0F_ETC__q3,
fork1_d0F_D_OUT[17:10],
CASE_fork1_d0FD_OUT_BITS_9_TO_8_0_fork1_d0FD_ETC__q4,
fork1_d0F_D_OUT[7:0] } ;
assign RDY_client1_request_get = fork1_d0F_EMPTY_N ;
// action method client1_response_put
assign RDY_client1_response_put = merge1_fi0_FULL_N ;
// actionvalue method client2_request_get
assign client2_request_get =
{ CASE_fork1_d1FD_OUT_BITS_39_TO_38_0_fork1_d1F_ETC__q13,
fork1_d1F_D_OUT[37:30],
CASE_fork1_d1FD_OUT_BITS_29_TO_28_0_fork1_d1F_ETC__q14,
fork1_d1F_D_OUT[27:20],
CASE_fork1_d1FD_OUT_BITS_19_TO_18_0_fork1_d1F_ETC__q15,
fork1_d1F_D_OUT[17:10],
CASE_fork1_d1FD_OUT_BITS_9_TO_8_0_fork1_d1FD_ETC__q16,
fork1_d1F_D_OUT[7:0] } ;
assign RDY_client2_request_get = fork1_d1F_EMPTY_N ;
// action method client2_response_put
assign RDY_client2_response_put = merge1_fi1_FULL_N ;
// submodule fork0_d0F
FIFO2 #(.width(32'd40), .guarded(32'd1)) fork0_d0F(.RST(RST_N),
.CLK(CLK),
.D_IN(fork0_d0F_D_IN),
.ENQ(fork0_d0F_ENQ),
.DEQ(fork0_d0F_DEQ),
.CLR(fork0_d0F_CLR),
.D_OUT(fork0_d0F_D_OUT),
.FULL_N(fork0_d0F_FULL_N),
.EMPTY_N(fork0_d0F_EMPTY_N));
// submodule fork0_d1F
FIFO2 #(.width(32'd40), .guarded(32'd1)) fork0_d1F(.RST(RST_N),
.CLK(CLK),
.D_IN(fork0_d1F_D_IN),
.ENQ(fork0_d1F_ENQ),
.DEQ(fork0_d1F_DEQ),
.CLR(fork0_d1F_CLR),
.D_OUT(fork0_d1F_D_OUT),
.FULL_N(fork0_d1F_FULL_N),
.EMPTY_N(fork0_d1F_EMPTY_N));
// submodule fork0_srcF
FIFO2 #(.width(32'd40), .guarded(32'd1)) fork0_srcF(.RST(RST_N),
.CLK(CLK),
.D_IN(fork0_srcF_D_IN),
.ENQ(fork0_srcF_ENQ),
.DEQ(fork0_srcF_DEQ),
.CLR(fork0_srcF_CLR),
.D_OUT(fork0_srcF_D_OUT),
.FULL_N(fork0_srcF_FULL_N),
.EMPTY_N(fork0_srcF_EMPTY_N));
// submodule fork1_d0F
FIFO2 #(.width(32'd40), .guarded(32'd1)) fork1_d0F(.RST(RST_N),
.CLK(CLK),
.D_IN(fork1_d0F_D_IN),
.ENQ(fork1_d0F_ENQ),
.DEQ(fork1_d0F_DEQ),
.CLR(fork1_d0F_CLR),
.D_OUT(fork1_d0F_D_OUT),
.FULL_N(fork1_d0F_FULL_N),
.EMPTY_N(fork1_d0F_EMPTY_N));
// submodule fork1_d1F
FIFO2 #(.width(32'd40), .guarded(32'd1)) fork1_d1F(.RST(RST_N),
.CLK(CLK),
.D_IN(fork1_d1F_D_IN),
.ENQ(fork1_d1F_ENQ),
.DEQ(fork1_d1F_DEQ),
.CLR(fork1_d1F_CLR),
.D_OUT(fork1_d1F_D_OUT),
.FULL_N(fork1_d1F_FULL_N),
.EMPTY_N(fork1_d1F_EMPTY_N));
// submodule fork1_srcF
FIFO2 #(.width(32'd40), .guarded(32'd1)) fork1_srcF(.RST(RST_N),
.CLK(CLK),
.D_IN(fork1_srcF_D_IN),
.ENQ(fork1_srcF_ENQ),
.DEQ(fork1_srcF_DEQ),
.CLR(fork1_srcF_CLR),
.D_OUT(fork1_srcF_D_OUT),
.FULL_N(fork1_srcF_FULL_N),
.EMPTY_N(fork1_srcF_EMPTY_N));
// submodule merge0_fi0
FIFO2 #(.width(32'd40), .guarded(32'd1)) merge0_fi0(.RST(RST_N),
.CLK(CLK),
.D_IN(merge0_fi0_D_IN),
.ENQ(merge0_fi0_ENQ),
.DEQ(merge0_fi0_DEQ),
.CLR(merge0_fi0_CLR),
.D_OUT(merge0_fi0_D_OUT),
.FULL_N(merge0_fi0_FULL_N),
.EMPTY_N(merge0_fi0_EMPTY_N));
// submodule merge0_fi1
FIFO2 #(.width(32'd40), .guarded(32'd1)) merge0_fi1(.RST(RST_N),
.CLK(CLK),
.D_IN(merge0_fi1_D_IN),
.ENQ(merge0_fi1_ENQ),
.DEQ(merge0_fi1_DEQ),
.CLR(merge0_fi1_CLR),
.D_OUT(merge0_fi1_D_OUT),
.FULL_N(merge0_fi1_FULL_N),
.EMPTY_N(merge0_fi1_EMPTY_N));
// submodule merge0_fo
FIFO2 #(.width(32'd40), .guarded(32'd1)) merge0_fo(.RST(RST_N),
.CLK(CLK),
.D_IN(merge0_fo_D_IN),
.ENQ(merge0_fo_ENQ),
.DEQ(merge0_fo_DEQ),
.CLR(merge0_fo_CLR),
.D_OUT(merge0_fo_D_OUT),
.FULL_N(merge0_fo_FULL_N),
.EMPTY_N(merge0_fo_EMPTY_N));
// submodule merge1_fi0
FIFO2 #(.width(32'd40), .guarded(32'd1)) merge1_fi0(.RST(RST_N),
.CLK(CLK),
.D_IN(merge1_fi0_D_IN),
.ENQ(merge1_fi0_ENQ),
.DEQ(merge1_fi0_DEQ),
.CLR(merge1_fi0_CLR),
.D_OUT(merge1_fi0_D_OUT),
.FULL_N(merge1_fi0_FULL_N),
.EMPTY_N(merge1_fi0_EMPTY_N));
// submodule merge1_fi1
FIFO2 #(.width(32'd40), .guarded(32'd1)) merge1_fi1(.RST(RST_N),
.CLK(CLK),
.D_IN(merge1_fi1_D_IN),
.ENQ(merge1_fi1_ENQ),
.DEQ(merge1_fi1_DEQ),
.CLR(merge1_fi1_CLR),
.D_OUT(merge1_fi1_D_OUT),
.FULL_N(merge1_fi1_FULL_N),
.EMPTY_N(merge1_fi1_EMPTY_N));
// submodule merge1_fo
FIFO2 #(.width(32'd40), .guarded(32'd1)) merge1_fo(.RST(RST_N),
.CLK(CLK),
.D_IN(merge1_fo_D_IN),
.ENQ(merge1_fo_ENQ),
.DEQ(merge1_fo_DEQ),
.CLR(merge1_fo_CLR),
.D_OUT(merge1_fo_D_OUT),
.FULL_N(merge1_fo_FULL_N),
.EMPTY_N(merge1_fo_EMPTY_N));
// rule RL_merge0_fi0_advance
assign WILL_FIRE_RL_merge0_fi0_advance =
merge0_fi0_EMPTY_N && merge0_fo_FULL_N && !merge0_fi1Active &&
!WILL_FIRE_RL_merge0_arbitrate ;
// rule RL_merge0_fi1_advance
assign WILL_FIRE_RL_merge0_fi1_advance =
merge0_fo_FULL_N && merge0_fi1_EMPTY_N && !merge0_fi0Active &&
!WILL_FIRE_RL_merge0_fi0_advance &&
!WILL_FIRE_RL_merge0_arbitrate ;
// rule RL_merge0_arbitrate
assign WILL_FIRE_RL_merge0_arbitrate =
merge0_fo_FULL_N &&
IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_i_notE_ETC___d118 &&
merge0_fi0_EMPTY_N &&
merge0_fi1_EMPTY_N &&
!merge0_fi0Active &&
!merge0_fi1Active ;
// rule RL_merge1_fi0_advance
assign WILL_FIRE_RL_merge1_fi0_advance =
merge1_fi0_EMPTY_N && merge1_fo_FULL_N && !merge1_fi1Active &&
!WILL_FIRE_RL_merge1_arbitrate ;
// rule RL_merge1_fi1_advance
assign WILL_FIRE_RL_merge1_fi1_advance =
merge1_fo_FULL_N && merge1_fi1_EMPTY_N && !merge1_fi0Active &&
!WILL_FIRE_RL_merge1_fi0_advance &&
!WILL_FIRE_RL_merge1_arbitrate ;
// rule RL_merge1_arbitrate
assign WILL_FIRE_RL_merge1_arbitrate =
merge1_fo_FULL_N &&
IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_i_notE_ETC___d289 &&
merge1_fi0_EMPTY_N &&
merge1_fi1_EMPTY_N &&
!merge1_fi0Active &&
!merge1_fi1Active ;
// rule RL_fork0_stage
assign WILL_FIRE_RL_fork0_stage =
fork0_srcF_EMPTY_N && !fork0_staged && !fork0_decided ;
// rule RL_fork0_decide
assign WILL_FIRE_RL_fork0_decide =
fork0_srcF_EMPTY_N && fork0_staged && !fork0_decided ;
// rule RL_fork0_egress
assign WILL_FIRE_RL_fork0_egress =
NOT_fork0_stageSent_98_99_OR_fork0_srcF_i_notE_ETC___d505 &&
fork0_staged &&
fork0_decided ;
// rule RL_fork1_stage
assign WILL_FIRE_RL_fork1_stage =
fork1_srcF_EMPTY_N && !fork1_staged && !fork1_decided ;
// rule RL_fork1_decide
assign WILL_FIRE_RL_fork1_decide =
fork1_srcF_EMPTY_N && fork1_staged && !fork1_decided ;
// rule RL_fork1_egress
assign WILL_FIRE_RL_fork1_egress =
NOT_fork1_stageSent_47_48_OR_fork1_srcF_i_notE_ETC___d754 &&
fork1_staged &&
fork1_decided ;
// inputs to muxes for submodule ports
assign MUX_fork0_decided_write_1__SEL_1 =
WILL_FIRE_RL_fork0_egress && fork0_stageSent &&
(fork0_srcF_D_OUT[9:8] != 2'd0 ||
fork0_srcF_D_OUT[19:18] != 2'd0 ||
fork0_srcF_D_OUT[29:28] != 2'd0 ||
fork0_srcF_D_OUT[39:38] != 2'd0) ;
assign MUX_fork0_ptr_write_1__SEL_1 =
WILL_FIRE_RL_fork0_egress &&
(fork0_srcF_D_OUT[9:8] != 2'd0 ||
fork0_srcF_D_OUT[19:18] != 2'd0 ||
fork0_srcF_D_OUT[29:28] != 2'd0 ||
fork0_srcF_D_OUT[39:38] != 2'd0 ||
!fork0_stageSent) ;
assign MUX_fork1_decided_write_1__SEL_1 =
WILL_FIRE_RL_fork1_egress && fork1_stageSent &&
(fork1_srcF_D_OUT[9:8] != 2'd0 ||
fork1_srcF_D_OUT[19:18] != 2'd0 ||
fork1_srcF_D_OUT[29:28] != 2'd0 ||
fork1_srcF_D_OUT[39:38] != 2'd0) ;
assign MUX_fork1_ptr_write_1__SEL_1 =
WILL_FIRE_RL_fork1_egress &&
(fork1_srcF_D_OUT[9:8] != 2'd0 ||
fork1_srcF_D_OUT[19:18] != 2'd0 ||
fork1_srcF_D_OUT[29:28] != 2'd0 ||
fork1_srcF_D_OUT[39:38] != 2'd0 ||
!fork1_stageSent) ;
assign MUX_merge0_fi0Active_write_1__SEL_1 =
WILL_FIRE_RL_merge0_arbitrate && merge0_fi0HasPrio ;
assign MUX_merge0_fi1Active_write_1__SEL_1 =
WILL_FIRE_RL_merge0_arbitrate && !merge0_fi0HasPrio ;
assign MUX_merge1_fi0Active_write_1__SEL_1 =
WILL_FIRE_RL_merge1_arbitrate && merge1_fi0HasPrio ;
assign MUX_merge1_fi1Active_write_1__SEL_1 =
WILL_FIRE_RL_merge1_arbitrate && !merge1_fi0HasPrio ;
assign MUX_fork0_ptr_write_1__VAL_1 =
fork0_stageSent ? 3'd0 : fork0_ptr_90_PLUS_1___d491 ;
assign MUX_fork0_ptr_write_1__VAL_2 =
(fork0_srcF_D_OUT[9:8] != 2'd0 ||
fork0_srcF_D_OUT[19:18] != 2'd0 ||
fork0_srcF_D_OUT[29:28] != 2'd0 ||
fork0_srcF_D_OUT[39:38] != 2'd0) ?
3'd0 :
fork0_ptr_90_PLUS_1___d491 ;
assign MUX_fork1_ptr_write_1__VAL_1 =
fork1_stageSent ? 3'd0 : fork1_ptr_39_PLUS_1___d740 ;
assign MUX_fork1_ptr_write_1__VAL_2 =
(fork1_srcF_D_OUT[9:8] != 2'd0 ||
fork1_srcF_D_OUT[19:18] != 2'd0 ||
fork1_srcF_D_OUT[29:28] != 2'd0 ||
fork1_srcF_D_OUT[39:38] != 2'd0) ?
3'd0 :
fork1_ptr_39_PLUS_1___d740 ;
assign MUX_merge0_fi0Active_write_1__VAL_1 =
IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d158 &&
IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d148 &&
IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d137 &&
IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d127 ;
assign MUX_merge0_fi0Active_write_1__VAL_2 =
merge0_fi0_D_OUT[9:8] == 2'd0 &&
merge0_fi0_D_OUT[19:18] == 2'd0 &&
merge0_fi0_D_OUT[29:28] == 2'd0 &&
merge0_fi0_D_OUT[39:38] == 2'd0 ;
assign MUX_merge0_fi1Active_write_1__VAL_2 =
merge0_fi1_D_OUT[9:8] == 2'd0 &&
merge0_fi1_D_OUT[19:18] == 2'd0 &&
merge0_fi1_D_OUT[29:28] == 2'd0 &&
merge0_fi1_D_OUT[39:38] == 2'd0 ;
assign MUX_merge0_fo_enq_1__VAL_1 =
{ CASE_merge0_fi0D_OUT_BITS_39_TO_38_0_merge0_f_ETC__q49,
merge0_fi0_D_OUT[37:30],
CASE_merge0_fi0D_OUT_BITS_29_TO_28_0_merge0_f_ETC__q50,
merge0_fi0_D_OUT[27:20],
CASE_merge0_fi0D_OUT_BITS_19_TO_18_0_merge0_f_ETC__q51,
merge0_fi0_D_OUT[17:10],
CASE_merge0_fi0D_OUT_BITS_9_TO_8_0_merge0_fi0_ETC__q52,
merge0_fi0_D_OUT[7:0] } ;
assign MUX_merge0_fo_enq_1__VAL_2 =
{ CASE_merge0_fi1D_OUT_BITS_39_TO_38_0_merge0_f_ETC__q53,
merge0_fi1_D_OUT[37:30],
CASE_merge0_fi1D_OUT_BITS_29_TO_28_0_merge0_f_ETC__q54,
merge0_fi1_D_OUT[27:20],
CASE_merge0_fi1D_OUT_BITS_19_TO_18_0_merge0_f_ETC__q55,
merge0_fi1_D_OUT[17:10],
CASE_merge0_fi1D_OUT_BITS_9_TO_8_0_merge0_fi1_ETC__q56,
merge0_fi1_D_OUT[7:0] } ;
assign MUX_merge0_fo_enq_1__VAL_3 =
{ IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d147,
IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d148 ?
{ 2'd0,
IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d149 } :
IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d156,
IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d158 ?
{ 2'd0,
IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d159 } :
IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d166 } ;
assign MUX_merge1_fi0Active_write_1__VAL_1 =
IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d329 &&
IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d319 &&
IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d308 &&
IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d298 ;
assign MUX_merge1_fi0Active_write_1__VAL_2 =
merge1_fi0_D_OUT[9:8] == 2'd0 &&
merge1_fi0_D_OUT[19:18] == 2'd0 &&
merge1_fi0_D_OUT[29:28] == 2'd0 &&
merge1_fi0_D_OUT[39:38] == 2'd0 ;
assign MUX_merge1_fi1Active_write_1__VAL_2 =
merge1_fi1_D_OUT[9:8] == 2'd0 &&
merge1_fi1_D_OUT[19:18] == 2'd0 &&
merge1_fi1_D_OUT[29:28] == 2'd0 &&
merge1_fi1_D_OUT[39:38] == 2'd0 ;
assign MUX_merge1_fo_enq_1__VAL_1 =
{ CASE_merge1_fi0D_OUT_BITS_39_TO_38_0_merge1_f_ETC__q57,
merge1_fi0_D_OUT[37:30],
CASE_merge1_fi0D_OUT_BITS_29_TO_28_0_merge1_f_ETC__q58,
merge1_fi0_D_OUT[27:20],
CASE_merge1_fi0D_OUT_BITS_19_TO_18_0_merge1_f_ETC__q59,
merge1_fi0_D_OUT[17:10],
CASE_merge1_fi0D_OUT_BITS_9_TO_8_0_merge1_fi0_ETC__q60,
merge1_fi0_D_OUT[7:0] } ;
assign MUX_merge1_fo_enq_1__VAL_2 =
{ CASE_merge1_fi1D_OUT_BITS_39_TO_38_0_merge1_f_ETC__q61,
merge1_fi1_D_OUT[37:30],
CASE_merge1_fi1D_OUT_BITS_29_TO_28_0_merge1_f_ETC__q62,
merge1_fi1_D_OUT[27:20],
CASE_merge1_fi1D_OUT_BITS_19_TO_18_0_merge1_f_ETC__q63,
merge1_fi1_D_OUT[17:10],
CASE_merge1_fi1D_OUT_BITS_9_TO_8_0_merge1_fi1_ETC__q64,
merge1_fi1_D_OUT[7:0] } ;
assign MUX_merge1_fo_enq_1__VAL_3 =
{ IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d318,
IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d319 ?
{ 2'd0,
IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d320 } :
IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d327,
IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d329 ?
{ 2'd0,
IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d330 } :
IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d337 } ;
// register fork0_decided
assign fork0_decided_D_IN = !MUX_fork0_decided_write_1__SEL_1 ;
assign fork0_decided_EN =
WILL_FIRE_RL_fork0_egress && fork0_stageSent &&
(fork0_srcF_D_OUT[9:8] != 2'd0 ||
fork0_srcF_D_OUT[19:18] != 2'd0 ||
fork0_srcF_D_OUT[29:28] != 2'd0 ||
fork0_srcF_D_OUT[39:38] != 2'd0) ||
WILL_FIRE_RL_fork0_decide ;
// register fork0_match0
assign fork0_match0_D_IN = et0 == seen__h14989 ;
assign fork0_match0_EN = WILL_FIRE_RL_fork0_decide ;
// register fork0_ptr
always@(MUX_fork0_ptr_write_1__SEL_1 or
MUX_fork0_ptr_write_1__VAL_1 or
WILL_FIRE_RL_fork0_stage or
MUX_fork0_ptr_write_1__VAL_2 or WILL_FIRE_RL_fork0_decide)
begin
case (1'b1) // synopsys parallel_case
MUX_fork0_ptr_write_1__SEL_1:
fork0_ptr_D_IN = MUX_fork0_ptr_write_1__VAL_1;
WILL_FIRE_RL_fork0_stage: fork0_ptr_D_IN = MUX_fork0_ptr_write_1__VAL_2;
WILL_FIRE_RL_fork0_decide: fork0_ptr_D_IN = 3'd0;
default: fork0_ptr_D_IN = 3'b010 /* unspecified value */ ;
endcase
end
assign fork0_ptr_EN =
WILL_FIRE_RL_fork0_egress &&
(fork0_srcF_D_OUT[9:8] != 2'd0 ||
fork0_srcF_D_OUT[19:18] != 2'd0 ||
fork0_srcF_D_OUT[29:28] != 2'd0 ||
fork0_srcF_D_OUT[39:38] != 2'd0 ||
!fork0_stageSent) ||
WILL_FIRE_RL_fork0_stage ||
WILL_FIRE_RL_fork0_decide ;
// register fork0_sr
assign fork0_sr_D_IN =
{ IF_fork0_srcF_first__50_BITS_39_TO_38_51_EQ_0__ETC___d393,
CASE_fork0_sr_BITS_119_TO_118_0_fork0_sr_BITS__ETC__q65,
fork0_sr[117:110],
CASE_fork0_sr_BITS_109_TO_108_0_fork0_sr_BITS__ETC__q66,
fork0_sr[107:100],
CASE_fork0_sr_BITS_99_TO_98_0_fork0_sr_BITS_99_ETC__q67,
fork0_sr[97:90],
CASE_fork0_sr_BITS_89_TO_88_0_fork0_sr_BITS_89_ETC__q68,
fork0_sr[87:80],
CASE_fork0_sr_BITS_79_TO_78_0_fork0_sr_BITS_79_ETC__q69,
fork0_sr[77:70],
CASE_fork0_sr_BITS_69_TO_68_0_fork0_sr_BITS_69_ETC__q70,
fork0_sr[67:60],
CASE_fork0_sr_BITS_59_TO_58_0_fork0_sr_BITS_59_ETC__q71,
fork0_sr[57:50],
CASE_fork0_sr_BITS_49_TO_48_0_fork0_sr_BITS_49_ETC__q72,
fork0_sr[47:40] } ;
assign fork0_sr_EN = WILL_FIRE_RL_fork0_stage ;
// register fork0_stageSent
assign fork0_stageSent_D_IN = !fork0_stageSent && fork0_ptr == 3'd2 ;
assign fork0_stageSent_EN = MUX_fork0_ptr_write_1__SEL_1 ;
// register fork0_staged
assign fork0_staged_D_IN =
!MUX_fork0_decided_write_1__SEL_1 && fork0_ptr == 3'd2 ;
assign fork0_staged_EN =
WILL_FIRE_RL_fork0_egress && fork0_stageSent &&
(fork0_srcF_D_OUT[9:8] != 2'd0 ||
fork0_srcF_D_OUT[19:18] != 2'd0 ||
fork0_srcF_D_OUT[29:28] != 2'd0 ||
fork0_srcF_D_OUT[39:38] != 2'd0) ||
WILL_FIRE_RL_fork0_stage ;
// register fork1_decided
assign fork1_decided_D_IN = !MUX_fork1_decided_write_1__SEL_1 ;
assign fork1_decided_EN =
WILL_FIRE_RL_fork1_egress && fork1_stageSent &&
(fork1_srcF_D_OUT[9:8] != 2'd0 ||
fork1_srcF_D_OUT[19:18] != 2'd0 ||
fork1_srcF_D_OUT[29:28] != 2'd0 ||
fork1_srcF_D_OUT[39:38] != 2'd0) ||
WILL_FIRE_RL_fork1_decide ;
// register fork1_match0
assign fork1_match0_D_IN = did == seen__h24820 ;
assign fork1_match0_EN = WILL_FIRE_RL_fork1_decide ;
// register fork1_ptr
always@(MUX_fork1_ptr_write_1__SEL_1 or
MUX_fork1_ptr_write_1__VAL_1 or
WILL_FIRE_RL_fork1_stage or
MUX_fork1_ptr_write_1__VAL_2 or WILL_FIRE_RL_fork1_decide)
begin
case (1'b1) // synopsys parallel_case
MUX_fork1_ptr_write_1__SEL_1:
fork1_ptr_D_IN = MUX_fork1_ptr_write_1__VAL_1;
WILL_FIRE_RL_fork1_stage: fork1_ptr_D_IN = MUX_fork1_ptr_write_1__VAL_2;
WILL_FIRE_RL_fork1_decide: fork1_ptr_D_IN = 3'd0;
default: fork1_ptr_D_IN = 3'b010 /* unspecified value */ ;
endcase
end
assign fork1_ptr_EN =
WILL_FIRE_RL_fork1_egress &&
(fork1_srcF_D_OUT[9:8] != 2'd0 ||
fork1_srcF_D_OUT[19:18] != 2'd0 ||
fork1_srcF_D_OUT[29:28] != 2'd0 ||
fork1_srcF_D_OUT[39:38] != 2'd0 ||
!fork1_stageSent) ||
WILL_FIRE_RL_fork1_stage ||
WILL_FIRE_RL_fork1_decide ;
// register fork1_sr
assign fork1_sr_D_IN =
{ IF_fork1_srcF_first__99_BITS_39_TO_38_00_EQ_0__ETC___d642,
CASE_fork1_sr_BITS_119_TO_118_0_fork1_sr_BITS__ETC__q77,
fork1_sr[117:110],
CASE_fork1_sr_BITS_109_TO_108_0_fork1_sr_BITS__ETC__q78,
fork1_sr[107:100],
CASE_fork1_sr_BITS_99_TO_98_0_fork1_sr_BITS_99_ETC__q79,
fork1_sr[97:90],
CASE_fork1_sr_BITS_89_TO_88_0_fork1_sr_BITS_89_ETC__q80,
fork1_sr[87:80],
CASE_fork1_sr_BITS_79_TO_78_0_fork1_sr_BITS_79_ETC__q81,
fork1_sr[77:70],
CASE_fork1_sr_BITS_69_TO_68_0_fork1_sr_BITS_69_ETC__q82,
fork1_sr[67:60],
CASE_fork1_sr_BITS_59_TO_58_0_fork1_sr_BITS_59_ETC__q83,
fork1_sr[57:50],
CASE_fork1_sr_BITS_49_TO_48_0_fork1_sr_BITS_49_ETC__q84,
fork1_sr[47:40] } ;
assign fork1_sr_EN = WILL_FIRE_RL_fork1_stage ;
// register fork1_stageSent
assign fork1_stageSent_D_IN = !fork1_stageSent && fork1_ptr == 3'd2 ;
assign fork1_stageSent_EN = MUX_fork1_ptr_write_1__SEL_1 ;
// register fork1_staged
assign fork1_staged_D_IN =
!MUX_fork1_decided_write_1__SEL_1 && fork1_ptr == 3'd2 ;
assign fork1_staged_EN =
WILL_FIRE_RL_fork1_egress && fork1_stageSent &&
(fork1_srcF_D_OUT[9:8] != 2'd0 ||
fork1_srcF_D_OUT[19:18] != 2'd0 ||
fork1_srcF_D_OUT[29:28] != 2'd0 ||
fork1_srcF_D_OUT[39:38] != 2'd0) ||
WILL_FIRE_RL_fork1_stage ;
// register merge0_fi0Active
assign merge0_fi0Active_D_IN =
MUX_merge0_fi0Active_write_1__SEL_1 ?
MUX_merge0_fi0Active_write_1__VAL_1 :
MUX_merge0_fi0Active_write_1__VAL_2 ;
assign merge0_fi0Active_EN =
WILL_FIRE_RL_merge0_arbitrate && merge0_fi0HasPrio ||
WILL_FIRE_RL_merge0_fi0_advance ;
// register merge0_fi0HasPrio
always@(WILL_FIRE_RL_merge0_arbitrate or
merge0_fi0HasPrio or
WILL_FIRE_RL_merge0_fi0_advance or WILL_FIRE_RL_merge0_fi1_advance)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_merge0_arbitrate:
merge0_fi0HasPrio_D_IN = !merge0_fi0HasPrio;
WILL_FIRE_RL_merge0_fi0_advance: merge0_fi0HasPrio_D_IN = 1'd0;
WILL_FIRE_RL_merge0_fi1_advance: merge0_fi0HasPrio_D_IN = 1'd1;
default: merge0_fi0HasPrio_D_IN = 1'b0 /* unspecified value */ ;
endcase
end
assign merge0_fi0HasPrio_EN =
WILL_FIRE_RL_merge0_arbitrate ||
WILL_FIRE_RL_merge0_fi0_advance ||
WILL_FIRE_RL_merge0_fi1_advance ;
// register merge0_fi1Active
assign merge0_fi1Active_D_IN =
MUX_merge0_fi1Active_write_1__SEL_1 ?
MUX_merge0_fi0Active_write_1__VAL_1 :
MUX_merge0_fi1Active_write_1__VAL_2 ;
assign merge0_fi1Active_EN =
WILL_FIRE_RL_merge0_arbitrate && !merge0_fi0HasPrio ||
WILL_FIRE_RL_merge0_fi1_advance ;
// register merge1_fi0Active
assign merge1_fi0Active_D_IN =
MUX_merge1_fi0Active_write_1__SEL_1 ?
MUX_merge1_fi0Active_write_1__VAL_1 :
MUX_merge1_fi0Active_write_1__VAL_2 ;
assign merge1_fi0Active_EN =
WILL_FIRE_RL_merge1_arbitrate && merge1_fi0HasPrio ||
WILL_FIRE_RL_merge1_fi0_advance ;
// register merge1_fi0HasPrio
always@(WILL_FIRE_RL_merge1_arbitrate or
merge1_fi0HasPrio or
WILL_FIRE_RL_merge1_fi0_advance or WILL_FIRE_RL_merge1_fi1_advance)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_merge1_arbitrate:
merge1_fi0HasPrio_D_IN = !merge1_fi0HasPrio;
WILL_FIRE_RL_merge1_fi0_advance: merge1_fi0HasPrio_D_IN = 1'd0;
WILL_FIRE_RL_merge1_fi1_advance: merge1_fi0HasPrio_D_IN = 1'd1;
default: merge1_fi0HasPrio_D_IN = 1'b0 /* unspecified value */ ;
endcase
end
assign merge1_fi0HasPrio_EN =
WILL_FIRE_RL_merge1_arbitrate ||
WILL_FIRE_RL_merge1_fi0_advance ||
WILL_FIRE_RL_merge1_fi1_advance ;
// register merge1_fi1Active
assign merge1_fi1Active_D_IN =
MUX_merge1_fi1Active_write_1__SEL_1 ?
MUX_merge1_fi0Active_write_1__VAL_1 :
MUX_merge1_fi1Active_write_1__VAL_2 ;
assign merge1_fi1Active_EN =
WILL_FIRE_RL_merge1_arbitrate && !merge1_fi0HasPrio ||
WILL_FIRE_RL_merge1_fi1_advance ;
// submodule fork0_d0F
assign fork0_d0F_D_IN =
fork0_stageSent ?
IF_fork0_srcF_first__50_BITS_39_TO_38_51_EQ_0__ETC___d393 :
{ IF_SEL_ARR_fork0_sr_94_BITS_39_TO_38_08_EQ_0_0_ETC___d526,
IF_SEL_ARR_fork0_sr_94_BITS_29_TO_28_27_EQ_0_2_ETC___d545,
IF_SEL_ARR_fork0_sr_94_BITS_19_TO_18_47_EQ_0_4_ETC___d565,
IF_SEL_ARR_fork0_sr_94_BITS_9_TO_8_66_EQ_0_67__ETC___d584 } ;
assign fork0_d0F_ENQ = WILL_FIRE_RL_fork0_egress && fork0_match0 ;
assign fork0_d0F_DEQ = EN_client0_request_get ;
assign fork0_d0F_CLR = 1'b0 ;
// submodule fork0_d1F
assign fork0_d1F_D_IN = fork0_d0F_D_IN ;
assign fork0_d1F_ENQ = WILL_FIRE_RL_fork0_egress && !fork0_match0 ;
assign fork0_d1F_DEQ = fork0_d1F_EMPTY_N && fork1_srcF_FULL_N ;
assign fork0_d1F_CLR = 1'b0 ;
// submodule fork0_srcF
assign fork0_srcF_D_IN =
{ CASE_server_request_put_BITS_39_TO_38_0_server_ETC__q73,
server_request_put[37:30],
CASE_server_request_put_BITS_29_TO_28_0_server_ETC__q74,
server_request_put[27:20],
CASE_server_request_put_BITS_19_TO_18_0_server_ETC__q75,
server_request_put[17:10],
CASE_server_request_put_BITS_9_TO_8_0_server_r_ETC__q76,
server_request_put[7:0] } ;
assign fork0_srcF_ENQ = EN_server_request_put ;
assign fork0_srcF_DEQ =
WILL_FIRE_RL_fork0_egress && fork0_stageSent ||
WILL_FIRE_RL_fork0_stage ;
assign fork0_srcF_CLR = 1'b0 ;
// submodule fork1_d0F
assign fork1_d0F_D_IN =
fork1_stageSent ?
IF_fork1_srcF_first__99_BITS_39_TO_38_00_EQ_0__ETC___d642 :
{ IF_SEL_ARR_fork1_sr_43_BITS_39_TO_38_57_EQ_0_5_ETC___d775,
IF_SEL_ARR_fork1_sr_43_BITS_29_TO_28_76_EQ_0_7_ETC___d794,
IF_SEL_ARR_fork1_sr_43_BITS_19_TO_18_96_EQ_0_9_ETC___d814,
IF_SEL_ARR_fork1_sr_43_BITS_9_TO_8_15_EQ_0_16__ETC___d833 } ;
assign fork1_d0F_ENQ = WILL_FIRE_RL_fork1_egress && fork1_match0 ;
assign fork1_d0F_DEQ = EN_client1_request_get ;
assign fork1_d0F_CLR = 1'b0 ;
// submodule fork1_d1F
assign fork1_d1F_D_IN = fork1_d0F_D_IN ;
assign fork1_d1F_ENQ = WILL_FIRE_RL_fork1_egress && !fork1_match0 ;
assign fork1_d1F_DEQ = EN_client2_request_get ;
assign fork1_d1F_CLR = 1'b0 ;
// submodule fork1_srcF
assign fork1_srcF_D_IN =
{ CASE_fork0_d1FD_OUT_BITS_39_TO_38_0_fork0_d1F_ETC__q85,
fork0_d1F_D_OUT[37:30],
CASE_fork0_d1FD_OUT_BITS_29_TO_28_0_fork0_d1F_ETC__q86,
fork0_d1F_D_OUT[27:20],
CASE_fork0_d1FD_OUT_BITS_19_TO_18_0_fork0_d1F_ETC__q87,
fork0_d1F_D_OUT[17:10],
CASE_fork0_d1FD_OUT_BITS_9_TO_8_0_fork0_d1FD_ETC__q88,
fork0_d1F_D_OUT[7:0] } ;
assign fork1_srcF_ENQ = fork0_d1F_EMPTY_N && fork1_srcF_FULL_N ;
assign fork1_srcF_DEQ =
WILL_FIRE_RL_fork1_egress && fork1_stageSent ||
WILL_FIRE_RL_fork1_stage ;
assign fork1_srcF_CLR = 1'b0 ;
// submodule merge0_fi0
assign merge0_fi0_D_IN =
{ CASE_client0_response_put_BITS_39_TO_38_0_clie_ETC__q89,
client0_response_put[37:30],
CASE_client0_response_put_BITS_29_TO_28_0_clie_ETC__q90,
client0_response_put[27:20],
CASE_client0_response_put_BITS_19_TO_18_0_clie_ETC__q91,
client0_response_put[17:10],
CASE_client0_response_put_BITS_9_TO_8_0_client_ETC__q92,
client0_response_put[7:0] } ;
assign merge0_fi0_ENQ = EN_client0_response_put ;
assign merge0_fi0_DEQ =
WILL_FIRE_RL_merge0_arbitrate && merge0_fi0HasPrio ||
WILL_FIRE_RL_merge0_fi0_advance ;
assign merge0_fi0_CLR = 1'b0 ;
// submodule merge0_fi1
assign merge0_fi1_D_IN =
{ CASE_merge1_foD_OUT_BITS_39_TO_38_0_merge1_fo_ETC__q93,
merge1_fo_D_OUT[37:30],
CASE_merge1_foD_OUT_BITS_29_TO_28_0_merge1_fo_ETC__q94,
merge1_fo_D_OUT[27:20],
CASE_merge1_foD_OUT_BITS_19_TO_18_0_merge1_fo_ETC__q95,
merge1_fo_D_OUT[17:10],
CASE_merge1_foD_OUT_BITS_9_TO_8_0_merge1_foD_ETC__q96,
merge1_fo_D_OUT[7:0] } ;
assign merge0_fi1_ENQ = merge1_fo_EMPTY_N && merge0_fi1_FULL_N ;
assign merge0_fi1_DEQ =
WILL_FIRE_RL_merge0_arbitrate && !merge0_fi0HasPrio ||
WILL_FIRE_RL_merge0_fi1_advance ;
assign merge0_fi1_CLR = 1'b0 ;
// submodule merge0_fo
always@(WILL_FIRE_RL_merge0_fi0_advance or
MUX_merge0_fo_enq_1__VAL_1 or
WILL_FIRE_RL_merge0_fi1_advance or
MUX_merge0_fo_enq_1__VAL_2 or
WILL_FIRE_RL_merge0_arbitrate or MUX_merge0_fo_enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_merge0_fi0_advance:
merge0_fo_D_IN = MUX_merge0_fo_enq_1__VAL_1;
WILL_FIRE_RL_merge0_fi1_advance:
merge0_fo_D_IN = MUX_merge0_fo_enq_1__VAL_2;
WILL_FIRE_RL_merge0_arbitrate:
merge0_fo_D_IN = MUX_merge0_fo_enq_1__VAL_3;
default: merge0_fo_D_IN = 40'hAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign merge0_fo_ENQ =
WILL_FIRE_RL_merge0_fi0_advance ||
WILL_FIRE_RL_merge0_fi1_advance ||
WILL_FIRE_RL_merge0_arbitrate ;
assign merge0_fo_DEQ = EN_server_response_get ;
assign merge0_fo_CLR = 1'b0 ;
// submodule merge1_fi0
assign merge1_fi0_D_IN =
{ CASE_client1_response_put_BITS_39_TO_38_0_clie_ETC__q97,
client1_response_put[37:30],
CASE_client1_response_put_BITS_29_TO_28_0_clie_ETC__q98,
client1_response_put[27:20],
CASE_client1_response_put_BITS_19_TO_18_0_clie_ETC__q99,
client1_response_put[17:10],
CASE_client1_response_put_BITS_9_TO_8_0_client_ETC__q100,
client1_response_put[7:0] } ;
assign merge1_fi0_ENQ = EN_client1_response_put ;
assign merge1_fi0_DEQ =
WILL_FIRE_RL_merge1_arbitrate && merge1_fi0HasPrio ||
WILL_FIRE_RL_merge1_fi0_advance ;
assign merge1_fi0_CLR = 1'b0 ;
// submodule merge1_fi1
assign merge1_fi1_D_IN =
{ CASE_client2_response_put_BITS_39_TO_38_0_clie_ETC__q101,
client2_response_put[37:30],
CASE_client2_response_put_BITS_29_TO_28_0_clie_ETC__q102,
client2_response_put[27:20],
CASE_client2_response_put_BITS_19_TO_18_0_clie_ETC__q103,
client2_response_put[17:10],
CASE_client2_response_put_BITS_9_TO_8_0_client_ETC__q104,
client2_response_put[7:0] } ;
assign merge1_fi1_ENQ = EN_client2_response_put ;
assign merge1_fi1_DEQ =
WILL_FIRE_RL_merge1_arbitrate && !merge1_fi0HasPrio ||
WILL_FIRE_RL_merge1_fi1_advance ;
assign merge1_fi1_CLR = 1'b0 ;
// submodule merge1_fo
always@(WILL_FIRE_RL_merge1_fi0_advance or
MUX_merge1_fo_enq_1__VAL_1 or
WILL_FIRE_RL_merge1_fi1_advance or
MUX_merge1_fo_enq_1__VAL_2 or
WILL_FIRE_RL_merge1_arbitrate or MUX_merge1_fo_enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_merge1_fi0_advance:
merge1_fo_D_IN = MUX_merge1_fo_enq_1__VAL_1;
WILL_FIRE_RL_merge1_fi1_advance:
merge1_fo_D_IN = MUX_merge1_fo_enq_1__VAL_2;
WILL_FIRE_RL_merge1_arbitrate:
merge1_fo_D_IN = MUX_merge1_fo_enq_1__VAL_3;
default: merge1_fo_D_IN = 40'hAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign merge1_fo_ENQ =
WILL_FIRE_RL_merge1_fi0_advance ||
WILL_FIRE_RL_merge1_fi1_advance ||
WILL_FIRE_RL_merge1_arbitrate ;
assign merge1_fo_DEQ = merge1_fo_EMPTY_N && merge0_fi1_FULL_N ;
assign merge1_fo_CLR = 1'b0 ;
// remaining internal signals
assign IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d133 =
(merge0_fi0HasPrio ?
merge0_fi0_D_OUT[39:38] == 2'd2 :
merge0_fi1_D_OUT[39:38] == 2'd2) ?
2'd2 :
2'd3 ;
assign IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d135 =
(merge0_fi0HasPrio ?
merge0_fi0_D_OUT[39:38] == 2'd1 :
merge0_fi1_D_OUT[39:38] == 2'd1) ?
{ 2'd1,
IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d128 } :
{ IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d133,
IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d128 } ;
assign IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d143 =
(merge0_fi0HasPrio ?
merge0_fi0_D_OUT[29:28] == 2'd2 :
merge0_fi1_D_OUT[29:28] == 2'd2) ?
2'd2 :
2'd3 ;
assign IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d145 =
(merge0_fi0HasPrio ?
merge0_fi0_D_OUT[29:28] == 2'd1 :
merge0_fi1_D_OUT[29:28] == 2'd1) ?
{ 2'd1,
IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d138 } :
{ IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d143,
IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d138 } ;
assign IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d147 =
{ IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d127 ?
{ 2'd0,
IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d128 } :
IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d135,
IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d137 ?
{ 2'd0,
IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d138 } :
IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d145 } ;
assign IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d154 =
(merge0_fi0HasPrio ?
merge0_fi0_D_OUT[19:18] == 2'd2 :
merge0_fi1_D_OUT[19:18] == 2'd2) ?
2'd2 :
2'd3 ;
assign IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d156 =
(merge0_fi0HasPrio ?
merge0_fi0_D_OUT[19:18] == 2'd1 :
merge0_fi1_D_OUT[19:18] == 2'd1) ?
{ 2'd1,
IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d149 } :
{ IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d154,
IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d149 } ;
assign IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d164 =
(merge0_fi0HasPrio ?
merge0_fi0_D_OUT[9:8] == 2'd2 :
merge0_fi1_D_OUT[9:8] == 2'd2) ?
2'd2 :
2'd3 ;
assign IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d166 =
(merge0_fi0HasPrio ?
merge0_fi0_D_OUT[9:8] == 2'd1 :
merge0_fi1_D_OUT[9:8] == 2'd1) ?
{ 2'd1,
IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d159 } :
{ IF_IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_fir_ETC___d164,
IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d159 } ;
assign IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d304 =
(merge1_fi0HasPrio ?
merge1_fi0_D_OUT[39:38] == 2'd2 :
merge1_fi1_D_OUT[39:38] == 2'd2) ?
2'd2 :
2'd3 ;
assign IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d306 =
(merge1_fi0HasPrio ?
merge1_fi0_D_OUT[39:38] == 2'd1 :
merge1_fi1_D_OUT[39:38] == 2'd1) ?
{ 2'd1,
IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d299 } :
{ IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d304,
IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d299 } ;
assign IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d314 =
(merge1_fi0HasPrio ?
merge1_fi0_D_OUT[29:28] == 2'd2 :
merge1_fi1_D_OUT[29:28] == 2'd2) ?
2'd2 :
2'd3 ;
assign IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d316 =
(merge1_fi0HasPrio ?
merge1_fi0_D_OUT[29:28] == 2'd1 :
merge1_fi1_D_OUT[29:28] == 2'd1) ?
{ 2'd1,
IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d309 } :
{ IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d314,
IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d309 } ;
assign IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d318 =
{ IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d298 ?
{ 2'd0,
IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d299 } :
IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d306,
IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d308 ?
{ 2'd0,
IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d309 } :
IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d316 } ;
assign IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d325 =
(merge1_fi0HasPrio ?
merge1_fi0_D_OUT[19:18] == 2'd2 :
merge1_fi1_D_OUT[19:18] == 2'd2) ?
2'd2 :
2'd3 ;
assign IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d327 =
(merge1_fi0HasPrio ?
merge1_fi0_D_OUT[19:18] == 2'd1 :
merge1_fi1_D_OUT[19:18] == 2'd1) ?
{ 2'd1,
IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d320 } :
{ IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d325,
IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d320 } ;
assign IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d335 =
(merge1_fi0HasPrio ?
merge1_fi0_D_OUT[9:8] == 2'd2 :
merge1_fi1_D_OUT[9:8] == 2'd2) ?
2'd2 :
2'd3 ;
assign IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d337 =
(merge1_fi0HasPrio ?
merge1_fi0_D_OUT[9:8] == 2'd1 :
merge1_fi1_D_OUT[9:8] == 2'd1) ?
{ 2'd1,
IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d330 } :
{ IF_IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_fir_ETC___d335,
IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d330 } ;
assign IF_SEL_ARR_fork0_sr_94_BITS_19_TO_18_47_EQ_0_4_ETC___d565 =
CASE_fork0_ptr_0_fork0_sr_BITS_19_TO_18_EQ_0_1_ETC__q39 ?
{ 2'd0,
SEL_ARR_fork0_sr_94_BITS_17_TO_10_51_fork0_sr__ETC___d553 } :
IF_SEL_ARR_fork0_sr_94_BITS_19_TO_18_47_EQ_1_5_ETC___d564 ;
assign IF_SEL_ARR_fork0_sr_94_BITS_19_TO_18_47_EQ_1_5_ETC___d564 =
CASE_fork0_ptr_0_fork0_sr_BITS_19_TO_18_EQ_1_1_ETC__q38 ?
{ 2'd1,
SEL_ARR_fork0_sr_94_BITS_17_TO_10_51_fork0_sr__ETC___d553 } :
IF_SEL_ARR_fork0_sr_94_BITS_19_TO_18_47_EQ_2_5_ETC___d563 ;
assign IF_SEL_ARR_fork0_sr_94_BITS_19_TO_18_47_EQ_2_5_ETC___d563 =
{ CASE_fork0_ptr_0_fork0_sr_BITS_19_TO_18_EQ_2_1_ETC__q37 ?
2'd2 :
2'd3,
SEL_ARR_fork0_sr_94_BITS_17_TO_10_51_fork0_sr__ETC___d553 } ;
assign IF_SEL_ARR_fork0_sr_94_BITS_29_TO_28_27_EQ_0_2_ETC___d545 =
CASE_fork0_ptr_0_fork0_sr_BITS_29_TO_28_EQ_0_1_ETC__q22 ?
{ 2'd0,
SEL_ARR_fork0_sr_94_BITS_27_TO_20_31_fork0_sr__ETC___d533 } :
IF_SEL_ARR_fork0_sr_94_BITS_29_TO_28_27_EQ_1_3_ETC___d544 ;
assign IF_SEL_ARR_fork0_sr_94_BITS_29_TO_28_27_EQ_1_3_ETC___d544 =
CASE_fork0_ptr_0_fork0_sr_BITS_29_TO_28_EQ_1_1_ETC__q21 ?
{ 2'd1,
SEL_ARR_fork0_sr_94_BITS_27_TO_20_31_fork0_sr__ETC___d533 } :
IF_SEL_ARR_fork0_sr_94_BITS_29_TO_28_27_EQ_2_3_ETC___d543 ;
assign IF_SEL_ARR_fork0_sr_94_BITS_29_TO_28_27_EQ_2_3_ETC___d543 =
{ CASE_fork0_ptr_0_fork0_sr_BITS_29_TO_28_EQ_2_1_ETC__q20 ?
2'd2 :
2'd3,
SEL_ARR_fork0_sr_94_BITS_27_TO_20_31_fork0_sr__ETC___d533 } ;
assign IF_SEL_ARR_fork0_sr_94_BITS_39_TO_38_08_EQ_0_0_ETC___d526 =
CASE_fork0_ptr_0_fork0_sr_BITS_39_TO_38_EQ_0_1_ETC__q19 ?
{ 2'd0,
SEL_ARR_fork0_sr_94_BITS_37_TO_30_12_fork0_sr__ETC___d514 } :
IF_SEL_ARR_fork0_sr_94_BITS_39_TO_38_08_EQ_1_1_ETC___d525 ;
assign IF_SEL_ARR_fork0_sr_94_BITS_39_TO_38_08_EQ_1_1_ETC___d525 =
CASE_fork0_ptr_0_fork0_sr_BITS_39_TO_38_EQ_1_1_ETC__q18 ?
{ 2'd1,
SEL_ARR_fork0_sr_94_BITS_37_TO_30_12_fork0_sr__ETC___d514 } :
IF_SEL_ARR_fork0_sr_94_BITS_39_TO_38_08_EQ_2_2_ETC___d524 ;
assign IF_SEL_ARR_fork0_sr_94_BITS_39_TO_38_08_EQ_2_2_ETC___d524 =
{ CASE_fork0_ptr_0_fork0_sr_BITS_39_TO_38_EQ_2_1_ETC__q17 ?
2'd2 :
2'd3,
SEL_ARR_fork0_sr_94_BITS_37_TO_30_12_fork0_sr__ETC___d514 } ;
assign IF_SEL_ARR_fork0_sr_94_BITS_9_TO_8_66_EQ_0_67__ETC___d584 =
CASE_fork0_ptr_0_fork0_sr_BITS_9_TO_8_EQ_0_1_f_ETC__q42 ?
{ 2'd0,
SEL_ARR_fork0_sr_94_BITS_7_TO_0_70_fork0_sr_94_ETC___d572 } :
IF_SEL_ARR_fork0_sr_94_BITS_9_TO_8_66_EQ_1_74__ETC___d583 ;
assign IF_SEL_ARR_fork0_sr_94_BITS_9_TO_8_66_EQ_1_74__ETC___d583 =
CASE_fork0_ptr_0_fork0_sr_BITS_9_TO_8_EQ_1_1_f_ETC__q41 ?
{ 2'd1,
SEL_ARR_fork0_sr_94_BITS_7_TO_0_70_fork0_sr_94_ETC___d572 } :
IF_SEL_ARR_fork0_sr_94_BITS_9_TO_8_66_EQ_2_78__ETC___d582 ;
assign IF_SEL_ARR_fork0_sr_94_BITS_9_TO_8_66_EQ_2_78__ETC___d582 =
{ CASE_fork0_ptr_0_fork0_sr_BITS_9_TO_8_EQ_2_1_f_ETC__q40 ?
2'd2 :
2'd3,
SEL_ARR_fork0_sr_94_BITS_7_TO_0_70_fork0_sr_94_ETC___d572 } ;
assign IF_SEL_ARR_fork1_sr_43_BITS_19_TO_18_96_EQ_0_9_ETC___d814 =
CASE_fork1_ptr_0_fork1_sr_BITS_19_TO_18_EQ_0_1_ETC__q45 ?
{ 2'd0,
SEL_ARR_fork1_sr_43_BITS_17_TO_10_00_fork1_sr__ETC___d802 } :
IF_SEL_ARR_fork1_sr_43_BITS_19_TO_18_96_EQ_1_0_ETC___d813 ;
assign IF_SEL_ARR_fork1_sr_43_BITS_19_TO_18_96_EQ_1_0_ETC___d813 =
CASE_fork1_ptr_0_fork1_sr_BITS_19_TO_18_EQ_1_1_ETC__q44 ?
{ 2'd1,
SEL_ARR_fork1_sr_43_BITS_17_TO_10_00_fork1_sr__ETC___d802 } :
IF_SEL_ARR_fork1_sr_43_BITS_19_TO_18_96_EQ_2_0_ETC___d812 ;
assign IF_SEL_ARR_fork1_sr_43_BITS_19_TO_18_96_EQ_2_0_ETC___d812 =
{ CASE_fork1_ptr_0_fork1_sr_BITS_19_TO_18_EQ_2_1_ETC__q43 ?
2'd2 :
2'd3,
SEL_ARR_fork1_sr_43_BITS_17_TO_10_00_fork1_sr__ETC___d802 } ;
assign IF_SEL_ARR_fork1_sr_43_BITS_29_TO_28_76_EQ_0_7_ETC___d794 =
CASE_fork1_ptr_0_fork1_sr_BITS_29_TO_28_EQ_0_1_ETC__q36 ?
{ 2'd0,
SEL_ARR_fork1_sr_43_BITS_27_TO_20_80_fork1_sr__ETC___d782 } :
IF_SEL_ARR_fork1_sr_43_BITS_29_TO_28_76_EQ_1_8_ETC___d793 ;
assign IF_SEL_ARR_fork1_sr_43_BITS_29_TO_28_76_EQ_1_8_ETC___d793 =
CASE_fork1_ptr_0_fork1_sr_BITS_29_TO_28_EQ_1_1_ETC__q35 ?
{ 2'd1,
SEL_ARR_fork1_sr_43_BITS_27_TO_20_80_fork1_sr__ETC___d782 } :
IF_SEL_ARR_fork1_sr_43_BITS_29_TO_28_76_EQ_2_8_ETC___d792 ;
assign IF_SEL_ARR_fork1_sr_43_BITS_29_TO_28_76_EQ_2_8_ETC___d792 =
{ CASE_fork1_ptr_0_fork1_sr_BITS_29_TO_28_EQ_2_1_ETC__q34 ?
2'd2 :
2'd3,
SEL_ARR_fork1_sr_43_BITS_27_TO_20_80_fork1_sr__ETC___d782 } ;
assign IF_SEL_ARR_fork1_sr_43_BITS_39_TO_38_57_EQ_0_5_ETC___d775 =
CASE_fork1_ptr_0_fork1_sr_BITS_39_TO_38_EQ_0_1_ETC__q33 ?
{ 2'd0,
SEL_ARR_fork1_sr_43_BITS_37_TO_30_61_fork1_sr__ETC___d763 } :
IF_SEL_ARR_fork1_sr_43_BITS_39_TO_38_57_EQ_1_6_ETC___d774 ;
assign IF_SEL_ARR_fork1_sr_43_BITS_39_TO_38_57_EQ_1_6_ETC___d774 =
CASE_fork1_ptr_0_fork1_sr_BITS_39_TO_38_EQ_1_1_ETC__q32 ?
{ 2'd1,
SEL_ARR_fork1_sr_43_BITS_37_TO_30_61_fork1_sr__ETC___d763 } :
IF_SEL_ARR_fork1_sr_43_BITS_39_TO_38_57_EQ_2_6_ETC___d773 ;
assign IF_SEL_ARR_fork1_sr_43_BITS_39_TO_38_57_EQ_2_6_ETC___d773 =
{ CASE_fork1_ptr_0_fork1_sr_BITS_39_TO_38_EQ_2_1_ETC__q31 ?
2'd2 :
2'd3,
SEL_ARR_fork1_sr_43_BITS_37_TO_30_61_fork1_sr__ETC___d763 } ;
assign IF_SEL_ARR_fork1_sr_43_BITS_9_TO_8_15_EQ_0_16__ETC___d833 =
CASE_fork1_ptr_0_fork1_sr_BITS_9_TO_8_EQ_0_1_f_ETC__q48 ?
{ 2'd0,
SEL_ARR_fork1_sr_43_BITS_7_TO_0_19_fork1_sr_43_ETC___d821 } :
IF_SEL_ARR_fork1_sr_43_BITS_9_TO_8_15_EQ_1_23__ETC___d832 ;
assign IF_SEL_ARR_fork1_sr_43_BITS_9_TO_8_15_EQ_1_23__ETC___d832 =
CASE_fork1_ptr_0_fork1_sr_BITS_9_TO_8_EQ_1_1_f_ETC__q47 ?
{ 2'd1,
SEL_ARR_fork1_sr_43_BITS_7_TO_0_19_fork1_sr_43_ETC___d821 } :
IF_SEL_ARR_fork1_sr_43_BITS_9_TO_8_15_EQ_2_27__ETC___d831 ;
assign IF_SEL_ARR_fork1_sr_43_BITS_9_TO_8_15_EQ_2_27__ETC___d831 =
{ CASE_fork1_ptr_0_fork1_sr_BITS_9_TO_8_EQ_2_1_f_ETC__q46 ?
2'd2 :
2'd3,
SEL_ARR_fork1_sr_43_BITS_7_TO_0_19_fork1_sr_43_ETC___d821 } ;
assign IF_fork0_srcF_first__50_BITS_39_TO_38_51_EQ_0__ETC___d393 =
{ CASE_fork0_srcFD_OUT_BITS_39_TO_38_0_fork0_sr_ETC__q27,
fork0_srcF_D_OUT[37:30],
CASE_fork0_srcFD_OUT_BITS_29_TO_28_0_fork0_sr_ETC__q28,
fork0_srcF_D_OUT[27:20],
CASE_fork0_srcFD_OUT_BITS_19_TO_18_0_fork0_sr_ETC__q29,
fork0_srcF_D_OUT[17:10],
CASE_fork0_srcFD_OUT_BITS_9_TO_8_0_fork0_srcF_ETC__q30,
fork0_srcF_D_OUT[7:0] } ;
assign IF_fork1_srcF_first__99_BITS_39_TO_38_00_EQ_0__ETC___d642 =
{ CASE_fork1_srcFD_OUT_BITS_39_TO_38_0_fork1_sr_ETC__q23,
fork1_srcF_D_OUT[37:30],
CASE_fork1_srcFD_OUT_BITS_29_TO_28_0_fork1_sr_ETC__q24,
fork1_srcF_D_OUT[27:20],
CASE_fork1_srcFD_OUT_BITS_19_TO_18_0_fork1_sr_ETC__q25,
fork1_srcF_D_OUT[17:10],
CASE_fork1_srcFD_OUT_BITS_9_TO_8_0_fork1_srcF_ETC__q26,
fork1_srcF_D_OUT[7:0] } ;
assign IF_merge0_fi0HasPrio_06_THEN_NOT_merge0_fi0_i__ETC___d113 =
merge0_fi0HasPrio ?
!merge0_fi0_EMPTY_N || merge0_fi0_D_OUT[9:8] != 2'd0 :
!merge0_fi1_EMPTY_N || merge0_fi1_D_OUT[9:8] != 2'd0 ;
assign IF_merge0_fi0HasPrio_06_THEN_NOT_merge0_fi0_i__ETC___d115 =
IF_merge0_fi0HasPrio_06_THEN_NOT_merge0_fi0_i__ETC___d113 ||
(merge0_fi0HasPrio ? merge0_fi0_EMPTY_N : merge0_fi1_EMPTY_N) ;
assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d127 =
merge0_fi0HasPrio ?
merge0_fi0_D_OUT[39:38] == 2'd0 :
merge0_fi1_D_OUT[39:38] == 2'd0 ;
assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d128 =
merge0_fi0HasPrio ?
merge0_fi0_D_OUT[37:30] :
merge0_fi1_D_OUT[37:30] ;
assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d137 =
merge0_fi0HasPrio ?
merge0_fi0_D_OUT[29:28] == 2'd0 :
merge0_fi1_D_OUT[29:28] == 2'd0 ;
assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d138 =
merge0_fi0HasPrio ?
merge0_fi0_D_OUT[27:20] :
merge0_fi1_D_OUT[27:20] ;
assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d148 =
merge0_fi0HasPrio ?
merge0_fi0_D_OUT[19:18] == 2'd0 :
merge0_fi1_D_OUT[19:18] == 2'd0 ;
assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d149 =
merge0_fi0HasPrio ?
merge0_fi0_D_OUT[17:10] :
merge0_fi1_D_OUT[17:10] ;
assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d158 =
merge0_fi0HasPrio ?
merge0_fi0_D_OUT[9:8] == 2'd0 :
merge0_fi1_D_OUT[9:8] == 2'd0 ;
assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_first__ETC___d159 =
merge0_fi0HasPrio ?
merge0_fi0_D_OUT[7:0] :
merge0_fi1_D_OUT[7:0] ;
assign IF_merge0_fi0HasPrio_06_THEN_merge0_fi0_i_notE_ETC___d118 =
merge0_fi0HasPrio ?
merge0_fi0_EMPTY_N &&
IF_merge0_fi0HasPrio_06_THEN_NOT_merge0_fi0_i__ETC___d115 :
merge0_fi1_EMPTY_N &&
IF_merge0_fi0HasPrio_06_THEN_NOT_merge0_fi0_i__ETC___d115 ;
assign IF_merge1_fi0HasPrio_77_THEN_NOT_merge1_fi0_i__ETC___d284 =
merge1_fi0HasPrio ?
!merge1_fi0_EMPTY_N || merge1_fi0_D_OUT[9:8] != 2'd0 :
!merge1_fi1_EMPTY_N || merge1_fi1_D_OUT[9:8] != 2'd0 ;
assign IF_merge1_fi0HasPrio_77_THEN_NOT_merge1_fi0_i__ETC___d286 =
IF_merge1_fi0HasPrio_77_THEN_NOT_merge1_fi0_i__ETC___d284 ||
(merge1_fi0HasPrio ? merge1_fi0_EMPTY_N : merge1_fi1_EMPTY_N) ;
assign IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d298 =
merge1_fi0HasPrio ?
merge1_fi0_D_OUT[39:38] == 2'd0 :
merge1_fi1_D_OUT[39:38] == 2'd0 ;
assign IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d299 =
merge1_fi0HasPrio ?
merge1_fi0_D_OUT[37:30] :
merge1_fi1_D_OUT[37:30] ;
assign IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d308 =
merge1_fi0HasPrio ?
merge1_fi0_D_OUT[29:28] == 2'd0 :
merge1_fi1_D_OUT[29:28] == 2'd0 ;
assign IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d309 =
merge1_fi0HasPrio ?
merge1_fi0_D_OUT[27:20] :
merge1_fi1_D_OUT[27:20] ;
assign IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d319 =
merge1_fi0HasPrio ?
merge1_fi0_D_OUT[19:18] == 2'd0 :
merge1_fi1_D_OUT[19:18] == 2'd0 ;
assign IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d320 =
merge1_fi0HasPrio ?
merge1_fi0_D_OUT[17:10] :
merge1_fi1_D_OUT[17:10] ;
assign IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d329 =
merge1_fi0HasPrio ?
merge1_fi0_D_OUT[9:8] == 2'd0 :
merge1_fi1_D_OUT[9:8] == 2'd0 ;
assign IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_first__ETC___d330 =
merge1_fi0HasPrio ?
merge1_fi0_D_OUT[7:0] :
merge1_fi1_D_OUT[7:0] ;
assign IF_merge1_fi0HasPrio_77_THEN_merge1_fi0_i_notE_ETC___d289 =
merge1_fi0HasPrio ?
merge1_fi0_EMPTY_N &&
IF_merge1_fi0HasPrio_77_THEN_NOT_merge1_fi0_i__ETC___d286 :
merge1_fi1_EMPTY_N &&
IF_merge1_fi0HasPrio_77_THEN_NOT_merge1_fi0_i__ETC___d286 ;
assign NOT_fork0_stageSent_98_99_OR_fork0_srcF_i_notE_ETC___d505 =
(!fork0_stageSent || fork0_srcF_EMPTY_N) &&
(fork0_match0 ? fork0_d0F_FULL_N : fork0_d1F_FULL_N) ;
assign NOT_fork1_stageSent_47_48_OR_fork1_srcF_i_notE_ETC___d754 =
(!fork1_stageSent || fork1_srcF_EMPTY_N) &&
(fork1_match0 ? fork1_d0F_FULL_N : fork1_d1F_FULL_N) ;
assign fork0_ptr_90_PLUS_1___d491 = fork0_ptr + 3'd1 ;
assign fork1_ptr_39_PLUS_1___d740 = fork1_ptr + 3'd1 ;
assign seen__h14989 = { fork0_srcF_D_OUT[7:0], fork0_srcF_D_OUT[17:10] } ;
assign seen__h24820 = { fork1_srcF_D_OUT[27:20], fork1_srcF_D_OUT[37:30] } ;
always@(fork1_d0F_D_OUT)
begin
case (fork1_d0F_D_OUT[39:38])
2'd0, 2'd1, 2'd2:
CASE_fork1_d0FD_OUT_BITS_39_TO_38_0_fork1_d0F_ETC__q1 =
fork1_d0F_D_OUT[39:38];
2'd3: CASE_fork1_d0FD_OUT_BITS_39_TO_38_0_fork1_d0F_ETC__q1 = 2'd3;
endcase
end
always@(fork1_d0F_D_OUT)
begin
case (fork1_d0F_D_OUT[29:28])
2'd0, 2'd1, 2'd2:
CASE_fork1_d0FD_OUT_BITS_29_TO_28_0_fork1_d0F_ETC__q2 =
fork1_d0F_D_OUT[29:28];
2'd3: CASE_fork1_d0FD_OUT_BITS_29_TO_28_0_fork1_d0F_ETC__q2 = 2'd3;
endcase
end
always@(fork1_d0F_D_OUT)
begin
case (fork1_d0F_D_OUT[19:18])
2'd0, 2'd1, 2'd2:
CASE_fork1_d0FD_OUT_BITS_19_TO_18_0_fork1_d0F_ETC__q3 =
fork1_d0F_D_OUT[19:18];
2'd3: CASE_fork1_d0FD_OUT_BITS_19_TO_18_0_fork1_d0F_ETC__q3 = 2'd3;
endcase
end
always@(fork1_d0F_D_OUT)
begin
case (fork1_d0F_D_OUT[9:8])
2'd0, 2'd1, 2'd2:
CASE_fork1_d0FD_OUT_BITS_9_TO_8_0_fork1_d0FD_ETC__q4 =
fork1_d0F_D_OUT[9:8];
2'd3: CASE_fork1_d0FD_OUT_BITS_9_TO_8_0_fork1_d0FD_ETC__q4 = 2'd3;
endcase
end
always@(fork0_d0F_D_OUT)
begin
case (fork0_d0F_D_OUT[39:38])
2'd0, 2'd1, 2'd2:
CASE_fork0_d0FD_OUT_BITS_39_TO_38_0_fork0_d0F_ETC__q5 =
fork0_d0F_D_OUT[39:38];
2'd3: CASE_fork0_d0FD_OUT_BITS_39_TO_38_0_fork0_d0F_ETC__q5 = 2'd3;
endcase
end
always@(fork0_d0F_D_OUT)
begin
case (fork0_d0F_D_OUT[29:28])
2'd0, 2'd1, 2'd2:
CASE_fork0_d0FD_OUT_BITS_29_TO_28_0_fork0_d0F_ETC__q6 =
fork0_d0F_D_OUT[29:28];
2'd3: CASE_fork0_d0FD_OUT_BITS_29_TO_28_0_fork0_d0F_ETC__q6 = 2'd3;
endcase
end
always@(fork0_d0F_D_OUT)
begin
case (fork0_d0F_D_OUT[19:18])
2'd0, 2'd1, 2'd2:
CASE_fork0_d0FD_OUT_BITS_19_TO_18_0_fork0_d0F_ETC__q7 =
fork0_d0F_D_OUT[19:18];
2'd3: CASE_fork0_d0FD_OUT_BITS_19_TO_18_0_fork0_d0F_ETC__q7 = 2'd3;
endcase
end
always@(fork0_d0F_D_OUT)
begin
case (fork0_d0F_D_OUT[9:8])
2'd0, 2'd1, 2'd2:
CASE_fork0_d0FD_OUT_BITS_9_TO_8_0_fork0_d0FD_ETC__q8 =
fork0_d0F_D_OUT[9:8];
2'd3: CASE_fork0_d0FD_OUT_BITS_9_TO_8_0_fork0_d0FD_ETC__q8 = 2'd3;
endcase
end
always@(merge0_fo_D_OUT)
begin
case (merge0_fo_D_OUT[39:38])
2'd0, 2'd1, 2'd2:
CASE_merge0_foD_OUT_BITS_39_TO_38_0_merge0_fo_ETC__q9 =
merge0_fo_D_OUT[39:38];
2'd3: CASE_merge0_foD_OUT_BITS_39_TO_38_0_merge0_fo_ETC__q9 = 2'd3;
endcase
end
always@(merge0_fo_D_OUT)
begin
case (merge0_fo_D_OUT[29:28])
2'd0, 2'd1, 2'd2:
CASE_merge0_foD_OUT_BITS_29_TO_28_0_merge0_fo_ETC__q10 =
merge0_fo_D_OUT[29:28];
2'd3: CASE_merge0_foD_OUT_BITS_29_TO_28_0_merge0_fo_ETC__q10 = 2'd3;
endcase
end
always@(merge0_fo_D_OUT)
begin
case (merge0_fo_D_OUT[19:18])
2'd0, 2'd1, 2'd2:
CASE_merge0_foD_OUT_BITS_19_TO_18_0_merge0_fo_ETC__q11 =
merge0_fo_D_OUT[19:18];
2'd3: CASE_merge0_foD_OUT_BITS_19_TO_18_0_merge0_fo_ETC__q11 = 2'd3;
endcase
end
always@(merge0_fo_D_OUT)
begin
case (merge0_fo_D_OUT[9:8])
2'd0, 2'd1, 2'd2:
CASE_merge0_foD_OUT_BITS_9_TO_8_0_merge0_foD_ETC__q12 =
merge0_fo_D_OUT[9:8];
2'd3: CASE_merge0_foD_OUT_BITS_9_TO_8_0_merge0_foD_ETC__q12 = 2'd3;
endcase
end
always@(fork1_d1F_D_OUT)
begin
case (fork1_d1F_D_OUT[39:38])
2'd0, 2'd1, 2'd2:
CASE_fork1_d1FD_OUT_BITS_39_TO_38_0_fork1_d1F_ETC__q13 =
fork1_d1F_D_OUT[39:38];
2'd3: CASE_fork1_d1FD_OUT_BITS_39_TO_38_0_fork1_d1F_ETC__q13 = 2'd3;
endcase
end
always@(fork1_d1F_D_OUT)
begin
case (fork1_d1F_D_OUT[29:28])
2'd0, 2'd1, 2'd2:
CASE_fork1_d1FD_OUT_BITS_29_TO_28_0_fork1_d1F_ETC__q14 =
fork1_d1F_D_OUT[29:28];
2'd3: CASE_fork1_d1FD_OUT_BITS_29_TO_28_0_fork1_d1F_ETC__q14 = 2'd3;
endcase
end
always@(fork1_d1F_D_OUT)
begin
case (fork1_d1F_D_OUT[19:18])
2'd0, 2'd1, 2'd2:
CASE_fork1_d1FD_OUT_BITS_19_TO_18_0_fork1_d1F_ETC__q15 =
fork1_d1F_D_OUT[19:18];
2'd3: CASE_fork1_d1FD_OUT_BITS_19_TO_18_0_fork1_d1F_ETC__q15 = 2'd3;
endcase
end
always@(fork1_d1F_D_OUT)
begin
case (fork1_d1F_D_OUT[9:8])
2'd0, 2'd1, 2'd2:
CASE_fork1_d1FD_OUT_BITS_9_TO_8_0_fork1_d1FD_ETC__q16 =
fork1_d1F_D_OUT[9:8];
2'd3: CASE_fork1_d1FD_OUT_BITS_9_TO_8_0_fork1_d1FD_ETC__q16 = 2'd3;
endcase
end
always@(fork0_ptr or fork0_sr)
begin
case (fork0_ptr)
3'd0:
SEL_ARR_fork0_sr_94_BITS_37_TO_30_12_fork0_sr__ETC___d514 =
fork0_sr[37:30];
3'd1:
SEL_ARR_fork0_sr_94_BITS_37_TO_30_12_fork0_sr__ETC___d514 =
fork0_sr[77:70];
3'd2:
SEL_ARR_fork0_sr_94_BITS_37_TO_30_12_fork0_sr__ETC___d514 =
fork0_sr[117:110];
default: SEL_ARR_fork0_sr_94_BITS_37_TO_30_12_fork0_sr__ETC___d514 =
8'b10101010 /* unspecified value */ ;
endcase
end
always@(fork0_ptr or fork0_sr)
begin
case (fork0_ptr)
3'd0:
SEL_ARR_fork0_sr_94_BITS_27_TO_20_31_fork0_sr__ETC___d533 =
fork0_sr[27:20];
3'd1:
SEL_ARR_fork0_sr_94_BITS_27_TO_20_31_fork0_sr__ETC___d533 =
fork0_sr[67:60];
3'd2:
SEL_ARR_fork0_sr_94_BITS_27_TO_20_31_fork0_sr__ETC___d533 =
fork0_sr[107:100];
default: SEL_ARR_fork0_sr_94_BITS_27_TO_20_31_fork0_sr__ETC___d533 =
8'b10101010 /* unspecified value */ ;
endcase
end
always@(fork0_ptr or fork0_sr)
begin
case (fork0_ptr)
3'd0:
CASE_fork0_ptr_0_fork0_sr_BITS_39_TO_38_EQ_2_1_ETC__q17 =
fork0_sr[39:38] == 2'd2;
3'd1:
CASE_fork0_ptr_0_fork0_sr_BITS_39_TO_38_EQ_2_1_ETC__q17 =
fork0_sr[79:78] == 2'd2;
3'd2:
CASE_fork0_ptr_0_fork0_sr_BITS_39_TO_38_EQ_2_1_ETC__q17 =
fork0_sr[119:118] == 2'd2;
default: CASE_fork0_ptr_0_fork0_sr_BITS_39_TO_38_EQ_2_1_ETC__q17 =
1'b0 /* unspecified value */ ;
endcase
end
always@(fork0_ptr or fork0_sr)
begin
case (fork0_ptr)
3'd0:
CASE_fork0_ptr_0_fork0_sr_BITS_39_TO_38_EQ_1_1_ETC__q18 =
fork0_sr[39:38] == 2'd1;
3'd1:
CASE_fork0_ptr_0_fork0_sr_BITS_39_TO_38_EQ_1_1_ETC__q18 =
fork0_sr[79:78] == 2'd1;
3'd2:
CASE_fork0_ptr_0_fork0_sr_BITS_39_TO_38_EQ_1_1_ETC__q18 =
fork0_sr[119:118] == 2'd1;
default: CASE_fork0_ptr_0_fork0_sr_BITS_39_TO_38_EQ_1_1_ETC__q18 =
1'b0 /* unspecified value */ ;
endcase
end
always@(fork0_ptr or fork0_sr)
begin
case (fork0_ptr)
3'd0:
CASE_fork0_ptr_0_fork0_sr_BITS_39_TO_38_EQ_0_1_ETC__q19 =
fork0_sr[39:38] == 2'd0;
3'd1:
CASE_fork0_ptr_0_fork0_sr_BITS_39_TO_38_EQ_0_1_ETC__q19 =
fork0_sr[79:78] == 2'd0;
3'd2:
CASE_fork0_ptr_0_fork0_sr_BITS_39_TO_38_EQ_0_1_ETC__q19 =
fork0_sr[119:118] == 2'd0;
default: CASE_fork0_ptr_0_fork0_sr_BITS_39_TO_38_EQ_0_1_ETC__q19 =
1'b0 /* unspecified value */ ;
endcase
end
always@(fork0_ptr or fork0_sr)
begin
case (fork0_ptr)
3'd0:
SEL_ARR_fork0_sr_94_BITS_17_TO_10_51_fork0_sr__ETC___d553 =
fork0_sr[17:10];
3'd1:
SEL_ARR_fork0_sr_94_BITS_17_TO_10_51_fork0_sr__ETC___d553 =
fork0_sr[57:50];
3'd2:
SEL_ARR_fork0_sr_94_BITS_17_TO_10_51_fork0_sr__ETC___d553 =
fork0_sr[97:90];
default: SEL_ARR_fork0_sr_94_BITS_17_TO_10_51_fork0_sr__ETC___d553 =
8'b10101010 /* unspecified value */ ;
endcase
end
always@(fork0_ptr or fork0_sr)
begin
case (fork0_ptr)
3'd0:
SEL_ARR_fork0_sr_94_BITS_7_TO_0_70_fork0_sr_94_ETC___d572 =
fork0_sr[7:0];
3'd1:
SEL_ARR_fork0_sr_94_BITS_7_TO_0_70_fork0_sr_94_ETC___d572 =
fork0_sr[47:40];
3'd2:
SEL_ARR_fork0_sr_94_BITS_7_TO_0_70_fork0_sr_94_ETC___d572 =
fork0_sr[87:80];
default: SEL_ARR_fork0_sr_94_BITS_7_TO_0_70_fork0_sr_94_ETC___d572 =
8'b10101010 /* unspecified value */ ;
endcase
end
always@(fork0_ptr or fork0_sr)
begin
case (fork0_ptr)
3'd0:
CASE_fork0_ptr_0_fork0_sr_BITS_29_TO_28_EQ_2_1_ETC__q20 =
fork0_sr[29:28] == 2'd2;
3'd1:
CASE_fork0_ptr_0_fork0_sr_BITS_29_TO_28_EQ_2_1_ETC__q20 =
fork0_sr[69:68] == 2'd2;
3'd2:
CASE_fork0_ptr_0_fork0_sr_BITS_29_TO_28_EQ_2_1_ETC__q20 =
fork0_sr[109:108] == 2'd2;
default: CASE_fork0_ptr_0_fork0_sr_BITS_29_TO_28_EQ_2_1_ETC__q20 =
1'b0 /* unspecified value */ ;
endcase
end
always@(fork0_ptr or fork0_sr)
begin
case (fork0_ptr)
3'd0:
CASE_fork0_ptr_0_fork0_sr_BITS_29_TO_28_EQ_1_1_ETC__q21 =
fork0_sr[29:28] == 2'd1;
3'd1:
CASE_fork0_ptr_0_fork0_sr_BITS_29_TO_28_EQ_1_1_ETC__q21 =
fork0_sr[69:68] == 2'd1;
3'd2:
CASE_fork0_ptr_0_fork0_sr_BITS_29_TO_28_EQ_1_1_ETC__q21 =
fork0_sr[109:108] == 2'd1;
default: CASE_fork0_ptr_0_fork0_sr_BITS_29_TO_28_EQ_1_1_ETC__q21 =
1'b0 /* unspecified value */ ;
endcase
end
always@(fork0_ptr or fork0_sr)
begin
case (fork0_ptr)
3'd0:
CASE_fork0_ptr_0_fork0_sr_BITS_29_TO_28_EQ_0_1_ETC__q22 =
fork0_sr[29:28] == 2'd0;
3'd1:
CASE_fork0_ptr_0_fork0_sr_BITS_29_TO_28_EQ_0_1_ETC__q22 =
fork0_sr[69:68] == 2'd0;
3'd2:
CASE_fork0_ptr_0_fork0_sr_BITS_29_TO_28_EQ_0_1_ETC__q22 =
fork0_sr[109:108] == 2'd0;
default: CASE_fork0_ptr_0_fork0_sr_BITS_29_TO_28_EQ_0_1_ETC__q22 =
1'b0 /* unspecified value */ ;
endcase
end
always@(fork1_srcF_D_OUT)
begin
case (fork1_srcF_D_OUT[39:38])
2'd0, 2'd1, 2'd2:
CASE_fork1_srcFD_OUT_BITS_39_TO_38_0_fork1_sr_ETC__q23 =
fork1_srcF_D_OUT[39:38];
2'd3: CASE_fork1_srcFD_OUT_BITS_39_TO_38_0_fork1_sr_ETC__q23 = 2'd3;
endcase
end
always@(fork1_srcF_D_OUT)
begin
case (fork1_srcF_D_OUT[29:28])
2'd0, 2'd1, 2'd2:
CASE_fork1_srcFD_OUT_BITS_29_TO_28_0_fork1_sr_ETC__q24 =
fork1_srcF_D_OUT[29:28];
2'd3: CASE_fork1_srcFD_OUT_BITS_29_TO_28_0_fork1_sr_ETC__q24 = 2'd3;
endcase
end
always@(fork1_srcF_D_OUT)
begin
case (fork1_srcF_D_OUT[19:18])
2'd0, 2'd1, 2'd2:
CASE_fork1_srcFD_OUT_BITS_19_TO_18_0_fork1_sr_ETC__q25 =
fork1_srcF_D_OUT[19:18];
2'd3: CASE_fork1_srcFD_OUT_BITS_19_TO_18_0_fork1_sr_ETC__q25 = 2'd3;
endcase
end
always@(fork1_srcF_D_OUT)
begin
case (fork1_srcF_D_OUT[9:8])
2'd0, 2'd1, 2'd2:
CASE_fork1_srcFD_OUT_BITS_9_TO_8_0_fork1_srcF_ETC__q26 =
fork1_srcF_D_OUT[9:8];
2'd3: CASE_fork1_srcFD_OUT_BITS_9_TO_8_0_fork1_srcF_ETC__q26 = 2'd3;
endcase
end
always@(fork0_srcF_D_OUT)
begin
case (fork0_srcF_D_OUT[39:38])
2'd0, 2'd1, 2'd2:
CASE_fork0_srcFD_OUT_BITS_39_TO_38_0_fork0_sr_ETC__q27 =
fork0_srcF_D_OUT[39:38];
2'd3: CASE_fork0_srcFD_OUT_BITS_39_TO_38_0_fork0_sr_ETC__q27 = 2'd3;
endcase
end
always@(fork0_srcF_D_OUT)
begin
case (fork0_srcF_D_OUT[29:28])
2'd0, 2'd1, 2'd2:
CASE_fork0_srcFD_OUT_BITS_29_TO_28_0_fork0_sr_ETC__q28 =
fork0_srcF_D_OUT[29:28];
2'd3: CASE_fork0_srcFD_OUT_BITS_29_TO_28_0_fork0_sr_ETC__q28 = 2'd3;
endcase
end
always@(fork0_srcF_D_OUT)
begin
case (fork0_srcF_D_OUT[19:18])
2'd0, 2'd1, 2'd2:
CASE_fork0_srcFD_OUT_BITS_19_TO_18_0_fork0_sr_ETC__q29 =
fork0_srcF_D_OUT[19:18];
2'd3: CASE_fork0_srcFD_OUT_BITS_19_TO_18_0_fork0_sr_ETC__q29 = 2'd3;
endcase
end
always@(fork0_srcF_D_OUT)
begin
case (fork0_srcF_D_OUT[9:8])
2'd0, 2'd1, 2'd2:
CASE_fork0_srcFD_OUT_BITS_9_TO_8_0_fork0_srcF_ETC__q30 =
fork0_srcF_D_OUT[9:8];
2'd3: CASE_fork0_srcFD_OUT_BITS_9_TO_8_0_fork0_srcF_ETC__q30 = 2'd3;
endcase
end
always@(fork1_ptr or fork1_sr)
begin
case (fork1_ptr)
3'd0:
SEL_ARR_fork1_sr_43_BITS_27_TO_20_80_fork1_sr__ETC___d782 =
fork1_sr[27:20];
3'd1:
SEL_ARR_fork1_sr_43_BITS_27_TO_20_80_fork1_sr__ETC___d782 =
fork1_sr[67:60];
3'd2:
SEL_ARR_fork1_sr_43_BITS_27_TO_20_80_fork1_sr__ETC___d782 =
fork1_sr[107:100];
default: SEL_ARR_fork1_sr_43_BITS_27_TO_20_80_fork1_sr__ETC___d782 =
8'b10101010 /* unspecified value */ ;
endcase
end
always@(fork1_ptr or fork1_sr)
begin
case (fork1_ptr)
3'd0:
SEL_ARR_fork1_sr_43_BITS_37_TO_30_61_fork1_sr__ETC___d763 =
fork1_sr[37:30];
3'd1:
SEL_ARR_fork1_sr_43_BITS_37_TO_30_61_fork1_sr__ETC___d763 =
fork1_sr[77:70];
3'd2:
SEL_ARR_fork1_sr_43_BITS_37_TO_30_61_fork1_sr__ETC___d763 =
fork1_sr[117:110];
default: SEL_ARR_fork1_sr_43_BITS_37_TO_30_61_fork1_sr__ETC___d763 =
8'b10101010 /* unspecified value */ ;
endcase
end
always@(fork1_ptr or fork1_sr)
begin
case (fork1_ptr)
3'd0:
CASE_fork1_ptr_0_fork1_sr_BITS_39_TO_38_EQ_2_1_ETC__q31 =
fork1_sr[39:38] == 2'd2;
3'd1:
CASE_fork1_ptr_0_fork1_sr_BITS_39_TO_38_EQ_2_1_ETC__q31 =
fork1_sr[79:78] == 2'd2;
3'd2:
CASE_fork1_ptr_0_fork1_sr_BITS_39_TO_38_EQ_2_1_ETC__q31 =
fork1_sr[119:118] == 2'd2;
default: CASE_fork1_ptr_0_fork1_sr_BITS_39_TO_38_EQ_2_1_ETC__q31 =
1'b0 /* unspecified value */ ;
endcase
end
always@(fork1_ptr or fork1_sr)
begin
case (fork1_ptr)
3'd0:
CASE_fork1_ptr_0_fork1_sr_BITS_39_TO_38_EQ_1_1_ETC__q32 =
fork1_sr[39:38] == 2'd1;
3'd1:
CASE_fork1_ptr_0_fork1_sr_BITS_39_TO_38_EQ_1_1_ETC__q32 =
fork1_sr[79:78] == 2'd1;
3'd2:
CASE_fork1_ptr_0_fork1_sr_BITS_39_TO_38_EQ_1_1_ETC__q32 =
fork1_sr[119:118] == 2'd1;
default: CASE_fork1_ptr_0_fork1_sr_BITS_39_TO_38_EQ_1_1_ETC__q32 =
1'b0 /* unspecified value */ ;
endcase
end
always@(fork1_ptr or fork1_sr)
begin
case (fork1_ptr)
3'd0:
CASE_fork1_ptr_0_fork1_sr_BITS_39_TO_38_EQ_0_1_ETC__q33 =
fork1_sr[39:38] == 2'd0;
3'd1:
CASE_fork1_ptr_0_fork1_sr_BITS_39_TO_38_EQ_0_1_ETC__q33 =
fork1_sr[79:78] == 2'd0;
3'd2:
CASE_fork1_ptr_0_fork1_sr_BITS_39_TO_38_EQ_0_1_ETC__q33 =
fork1_sr[119:118] == 2'd0;
default: CASE_fork1_ptr_0_fork1_sr_BITS_39_TO_38_EQ_0_1_ETC__q33 =
1'b0 /* unspecified value */ ;
endcase
end
always@(fork1_ptr or fork1_sr)
begin
case (fork1_ptr)
3'd0:
SEL_ARR_fork1_sr_43_BITS_17_TO_10_00_fork1_sr__ETC___d802 =
fork1_sr[17:10];
3'd1:
SEL_ARR_fork1_sr_43_BITS_17_TO_10_00_fork1_sr__ETC___d802 =
fork1_sr[57:50];
3'd2:
SEL_ARR_fork1_sr_43_BITS_17_TO_10_00_fork1_sr__ETC___d802 =
fork1_sr[97:90];
default: SEL_ARR_fork1_sr_43_BITS_17_TO_10_00_fork1_sr__ETC___d802 =
8'b10101010 /* unspecified value */ ;
endcase
end
always@(fork1_ptr or fork1_sr)
begin
case (fork1_ptr)
3'd0:
SEL_ARR_fork1_sr_43_BITS_7_TO_0_19_fork1_sr_43_ETC___d821 =
fork1_sr[7:0];
3'd1:
SEL_ARR_fork1_sr_43_BITS_7_TO_0_19_fork1_sr_43_ETC___d821 =
fork1_sr[47:40];
3'd2:
SEL_ARR_fork1_sr_43_BITS_7_TO_0_19_fork1_sr_43_ETC___d821 =
fork1_sr[87:80];
default: SEL_ARR_fork1_sr_43_BITS_7_TO_0_19_fork1_sr_43_ETC___d821 =
8'b10101010 /* unspecified value */ ;
endcase
end
always@(fork1_ptr or fork1_sr)
begin
case (fork1_ptr)
3'd0:
CASE_fork1_ptr_0_fork1_sr_BITS_29_TO_28_EQ_2_1_ETC__q34 =
fork1_sr[29:28] == 2'd2;
3'd1:
CASE_fork1_ptr_0_fork1_sr_BITS_29_TO_28_EQ_2_1_ETC__q34 =
fork1_sr[69:68] == 2'd2;
3'd2:
CASE_fork1_ptr_0_fork1_sr_BITS_29_TO_28_EQ_2_1_ETC__q34 =
fork1_sr[109:108] == 2'd2;
default: CASE_fork1_ptr_0_fork1_sr_BITS_29_TO_28_EQ_2_1_ETC__q34 =
1'b0 /* unspecified value */ ;
endcase
end
always@(fork1_ptr or fork1_sr)
begin
case (fork1_ptr)
3'd0:
CASE_fork1_ptr_0_fork1_sr_BITS_29_TO_28_EQ_1_1_ETC__q35 =
fork1_sr[29:28] == 2'd1;
3'd1:
CASE_fork1_ptr_0_fork1_sr_BITS_29_TO_28_EQ_1_1_ETC__q35 =
fork1_sr[69:68] == 2'd1;
3'd2:
CASE_fork1_ptr_0_fork1_sr_BITS_29_TO_28_EQ_1_1_ETC__q35 =
fork1_sr[109:108] == 2'd1;
default: CASE_fork1_ptr_0_fork1_sr_BITS_29_TO_28_EQ_1_1_ETC__q35 =
1'b0 /* unspecified value */ ;
endcase
end
always@(fork1_ptr or fork1_sr)
begin
case (fork1_ptr)
3'd0:
CASE_fork1_ptr_0_fork1_sr_BITS_29_TO_28_EQ_0_1_ETC__q36 =
fork1_sr[29:28] == 2'd0;
3'd1:
CASE_fork1_ptr_0_fork1_sr_BITS_29_TO_28_EQ_0_1_ETC__q36 =
fork1_sr[69:68] == 2'd0;
3'd2:
CASE_fork1_ptr_0_fork1_sr_BITS_29_TO_28_EQ_0_1_ETC__q36 =
fork1_sr[109:108] == 2'd0;
default: CASE_fork1_ptr_0_fork1_sr_BITS_29_TO_28_EQ_0_1_ETC__q36 =
1'b0 /* unspecified value */ ;
endcase
end
always@(fork0_ptr or fork0_sr)
begin
case (fork0_ptr)
3'd0:
CASE_fork0_ptr_0_fork0_sr_BITS_19_TO_18_EQ_2_1_ETC__q37 =
fork0_sr[19:18] == 2'd2;
3'd1:
CASE_fork0_ptr_0_fork0_sr_BITS_19_TO_18_EQ_2_1_ETC__q37 =
fork0_sr[59:58] == 2'd2;
3'd2:
CASE_fork0_ptr_0_fork0_sr_BITS_19_TO_18_EQ_2_1_ETC__q37 =
fork0_sr[99:98] == 2'd2;
default: CASE_fork0_ptr_0_fork0_sr_BITS_19_TO_18_EQ_2_1_ETC__q37 =
1'b0 /* unspecified value */ ;
endcase
end
always@(fork0_ptr or fork0_sr)
begin
case (fork0_ptr)
3'd0:
CASE_fork0_ptr_0_fork0_sr_BITS_19_TO_18_EQ_1_1_ETC__q38 =
fork0_sr[19:18] == 2'd1;
3'd1:
CASE_fork0_ptr_0_fork0_sr_BITS_19_TO_18_EQ_1_1_ETC__q38 =
fork0_sr[59:58] == 2'd1;
3'd2:
CASE_fork0_ptr_0_fork0_sr_BITS_19_TO_18_EQ_1_1_ETC__q38 =
fork0_sr[99:98] == 2'd1;
default: CASE_fork0_ptr_0_fork0_sr_BITS_19_TO_18_EQ_1_1_ETC__q38 =
1'b0 /* unspecified value */ ;
endcase
end
always@(fork0_ptr or fork0_sr)
begin
case (fork0_ptr)
3'd0:
CASE_fork0_ptr_0_fork0_sr_BITS_19_TO_18_EQ_0_1_ETC__q39 =
fork0_sr[19:18] == 2'd0;
3'd1:
CASE_fork0_ptr_0_fork0_sr_BITS_19_TO_18_EQ_0_1_ETC__q39 =
fork0_sr[59:58] == 2'd0;
3'd2:
CASE_fork0_ptr_0_fork0_sr_BITS_19_TO_18_EQ_0_1_ETC__q39 =
fork0_sr[99:98] == 2'd0;
default: CASE_fork0_ptr_0_fork0_sr_BITS_19_TO_18_EQ_0_1_ETC__q39 =
1'b0 /* unspecified value */ ;
endcase
end
always@(fork0_ptr or fork0_sr)
begin
case (fork0_ptr)
3'd0:
CASE_fork0_ptr_0_fork0_sr_BITS_9_TO_8_EQ_2_1_f_ETC__q40 =
fork0_sr[9:8] == 2'd2;
3'd1:
CASE_fork0_ptr_0_fork0_sr_BITS_9_TO_8_EQ_2_1_f_ETC__q40 =
fork0_sr[49:48] == 2'd2;
3'd2:
CASE_fork0_ptr_0_fork0_sr_BITS_9_TO_8_EQ_2_1_f_ETC__q40 =
fork0_sr[89:88] == 2'd2;
default: CASE_fork0_ptr_0_fork0_sr_BITS_9_TO_8_EQ_2_1_f_ETC__q40 =
1'b0 /* unspecified value */ ;
endcase
end
always@(fork0_ptr or fork0_sr)
begin
case (fork0_ptr)
3'd0:
CASE_fork0_ptr_0_fork0_sr_BITS_9_TO_8_EQ_1_1_f_ETC__q41 =
fork0_sr[9:8] == 2'd1;
3'd1:
CASE_fork0_ptr_0_fork0_sr_BITS_9_TO_8_EQ_1_1_f_ETC__q41 =
fork0_sr[49:48] == 2'd1;
3'd2:
CASE_fork0_ptr_0_fork0_sr_BITS_9_TO_8_EQ_1_1_f_ETC__q41 =
fork0_sr[89:88] == 2'd1;
default: CASE_fork0_ptr_0_fork0_sr_BITS_9_TO_8_EQ_1_1_f_ETC__q41 =
1'b0 /* unspecified value */ ;
endcase
end
always@(fork0_ptr or fork0_sr)
begin
case (fork0_ptr)
3'd0:
CASE_fork0_ptr_0_fork0_sr_BITS_9_TO_8_EQ_0_1_f_ETC__q42 =
fork0_sr[9:8] == 2'd0;
3'd1:
CASE_fork0_ptr_0_fork0_sr_BITS_9_TO_8_EQ_0_1_f_ETC__q42 =
fork0_sr[49:48] == 2'd0;
3'd2:
CASE_fork0_ptr_0_fork0_sr_BITS_9_TO_8_EQ_0_1_f_ETC__q42 =
fork0_sr[89:88] == 2'd0;
default: CASE_fork0_ptr_0_fork0_sr_BITS_9_TO_8_EQ_0_1_f_ETC__q42 =
1'b0 /* unspecified value */ ;
endcase
end
always@(fork1_ptr or fork1_sr)
begin
case (fork1_ptr)
3'd0:
CASE_fork1_ptr_0_fork1_sr_BITS_19_TO_18_EQ_2_1_ETC__q43 =
fork1_sr[19:18] == 2'd2;
3'd1:
CASE_fork1_ptr_0_fork1_sr_BITS_19_TO_18_EQ_2_1_ETC__q43 =
fork1_sr[59:58] == 2'd2;
3'd2:
CASE_fork1_ptr_0_fork1_sr_BITS_19_TO_18_EQ_2_1_ETC__q43 =
fork1_sr[99:98] == 2'd2;
default: CASE_fork1_ptr_0_fork1_sr_BITS_19_TO_18_EQ_2_1_ETC__q43 =
1'b0 /* unspecified value */ ;
endcase
end
always@(fork1_ptr or fork1_sr)
begin
case (fork1_ptr)
3'd0:
CASE_fork1_ptr_0_fork1_sr_BITS_19_TO_18_EQ_1_1_ETC__q44 =
fork1_sr[19:18] == 2'd1;
3'd1:
CASE_fork1_ptr_0_fork1_sr_BITS_19_TO_18_EQ_1_1_ETC__q44 =
fork1_sr[59:58] == 2'd1;
3'd2:
CASE_fork1_ptr_0_fork1_sr_BITS_19_TO_18_EQ_1_1_ETC__q44 =
fork1_sr[99:98] == 2'd1;
default: CASE_fork1_ptr_0_fork1_sr_BITS_19_TO_18_EQ_1_1_ETC__q44 =
1'b0 /* unspecified value */ ;
endcase
end
always@(fork1_ptr or fork1_sr)
begin
case (fork1_ptr)
3'd0:
CASE_fork1_ptr_0_fork1_sr_BITS_19_TO_18_EQ_0_1_ETC__q45 =
fork1_sr[19:18] == 2'd0;
3'd1:
CASE_fork1_ptr_0_fork1_sr_BITS_19_TO_18_EQ_0_1_ETC__q45 =
fork1_sr[59:58] == 2'd0;
3'd2:
CASE_fork1_ptr_0_fork1_sr_BITS_19_TO_18_EQ_0_1_ETC__q45 =
fork1_sr[99:98] == 2'd0;
default: CASE_fork1_ptr_0_fork1_sr_BITS_19_TO_18_EQ_0_1_ETC__q45 =
1'b0 /* unspecified value */ ;
endcase
end
always@(fork1_ptr or fork1_sr)
begin
case (fork1_ptr)
3'd0:
CASE_fork1_ptr_0_fork1_sr_BITS_9_TO_8_EQ_2_1_f_ETC__q46 =
fork1_sr[9:8] == 2'd2;
3'd1:
CASE_fork1_ptr_0_fork1_sr_BITS_9_TO_8_EQ_2_1_f_ETC__q46 =
fork1_sr[49:48] == 2'd2;
3'd2:
CASE_fork1_ptr_0_fork1_sr_BITS_9_TO_8_EQ_2_1_f_ETC__q46 =
fork1_sr[89:88] == 2'd2;
default: CASE_fork1_ptr_0_fork1_sr_BITS_9_TO_8_EQ_2_1_f_ETC__q46 =
1'b0 /* unspecified value */ ;
endcase
end
always@(fork1_ptr or fork1_sr)
begin
case (fork1_ptr)
3'd0:
CASE_fork1_ptr_0_fork1_sr_BITS_9_TO_8_EQ_1_1_f_ETC__q47 =
fork1_sr[9:8] == 2'd1;
3'd1:
CASE_fork1_ptr_0_fork1_sr_BITS_9_TO_8_EQ_1_1_f_ETC__q47 =
fork1_sr[49:48] == 2'd1;
3'd2:
CASE_fork1_ptr_0_fork1_sr_BITS_9_TO_8_EQ_1_1_f_ETC__q47 =
fork1_sr[89:88] == 2'd1;
default: CASE_fork1_ptr_0_fork1_sr_BITS_9_TO_8_EQ_1_1_f_ETC__q47 =
1'b0 /* unspecified value */ ;
endcase
end
always@(fork1_ptr or fork1_sr)
begin
case (fork1_ptr)
3'd0:
CASE_fork1_ptr_0_fork1_sr_BITS_9_TO_8_EQ_0_1_f_ETC__q48 =
fork1_sr[9:8] == 2'd0;
3'd1:
CASE_fork1_ptr_0_fork1_sr_BITS_9_TO_8_EQ_0_1_f_ETC__q48 =
fork1_sr[49:48] == 2'd0;
3'd2:
CASE_fork1_ptr_0_fork1_sr_BITS_9_TO_8_EQ_0_1_f_ETC__q48 =
fork1_sr[89:88] == 2'd0;
default: CASE_fork1_ptr_0_fork1_sr_BITS_9_TO_8_EQ_0_1_f_ETC__q48 =
1'b0 /* unspecified value */ ;
endcase
end
always@(merge0_fi0_D_OUT)
begin
case (merge0_fi0_D_OUT[39:38])
2'd0, 2'd1, 2'd2:
CASE_merge0_fi0D_OUT_BITS_39_TO_38_0_merge0_f_ETC__q49 =
merge0_fi0_D_OUT[39:38];
2'd3: CASE_merge0_fi0D_OUT_BITS_39_TO_38_0_merge0_f_ETC__q49 = 2'd3;
endcase
end
always@(merge0_fi0_D_OUT)
begin
case (merge0_fi0_D_OUT[29:28])
2'd0, 2'd1, 2'd2:
CASE_merge0_fi0D_OUT_BITS_29_TO_28_0_merge0_f_ETC__q50 =
merge0_fi0_D_OUT[29:28];
2'd3: CASE_merge0_fi0D_OUT_BITS_29_TO_28_0_merge0_f_ETC__q50 = 2'd3;
endcase
end
always@(merge0_fi0_D_OUT)
begin
case (merge0_fi0_D_OUT[19:18])
2'd0, 2'd1, 2'd2:
CASE_merge0_fi0D_OUT_BITS_19_TO_18_0_merge0_f_ETC__q51 =
merge0_fi0_D_OUT[19:18];
2'd3: CASE_merge0_fi0D_OUT_BITS_19_TO_18_0_merge0_f_ETC__q51 = 2'd3;
endcase
end
always@(merge0_fi0_D_OUT)
begin
case (merge0_fi0_D_OUT[9:8])
2'd0, 2'd1, 2'd2:
CASE_merge0_fi0D_OUT_BITS_9_TO_8_0_merge0_fi0_ETC__q52 =
merge0_fi0_D_OUT[9:8];
2'd3: CASE_merge0_fi0D_OUT_BITS_9_TO_8_0_merge0_fi0_ETC__q52 = 2'd3;
endcase
end
always@(merge0_fi1_D_OUT)
begin
case (merge0_fi1_D_OUT[39:38])
2'd0, 2'd1, 2'd2:
CASE_merge0_fi1D_OUT_BITS_39_TO_38_0_merge0_f_ETC__q53 =
merge0_fi1_D_OUT[39:38];
2'd3: CASE_merge0_fi1D_OUT_BITS_39_TO_38_0_merge0_f_ETC__q53 = 2'd3;
endcase
end
always@(merge0_fi1_D_OUT)
begin
case (merge0_fi1_D_OUT[29:28])
2'd0, 2'd1, 2'd2:
CASE_merge0_fi1D_OUT_BITS_29_TO_28_0_merge0_f_ETC__q54 =
merge0_fi1_D_OUT[29:28];
2'd3: CASE_merge0_fi1D_OUT_BITS_29_TO_28_0_merge0_f_ETC__q54 = 2'd3;
endcase
end
always@(merge0_fi1_D_OUT)
begin
case (merge0_fi1_D_OUT[19:18])
2'd0, 2'd1, 2'd2:
CASE_merge0_fi1D_OUT_BITS_19_TO_18_0_merge0_f_ETC__q55 =
merge0_fi1_D_OUT[19:18];
2'd3: CASE_merge0_fi1D_OUT_BITS_19_TO_18_0_merge0_f_ETC__q55 = 2'd3;
endcase
end
always@(merge0_fi1_D_OUT)
begin
case (merge0_fi1_D_OUT[9:8])
2'd0, 2'd1, 2'd2:
CASE_merge0_fi1D_OUT_BITS_9_TO_8_0_merge0_fi1_ETC__q56 =
merge0_fi1_D_OUT[9:8];
2'd3: CASE_merge0_fi1D_OUT_BITS_9_TO_8_0_merge0_fi1_ETC__q56 = 2'd3;
endcase
end
always@(merge1_fi0_D_OUT)
begin
case (merge1_fi0_D_OUT[39:38])
2'd0, 2'd1, 2'd2:
CASE_merge1_fi0D_OUT_BITS_39_TO_38_0_merge1_f_ETC__q57 =
merge1_fi0_D_OUT[39:38];
2'd3: CASE_merge1_fi0D_OUT_BITS_39_TO_38_0_merge1_f_ETC__q57 = 2'd3;
endcase
end
always@(merge1_fi0_D_OUT)
begin
case (merge1_fi0_D_OUT[29:28])
2'd0, 2'd1, 2'd2:
CASE_merge1_fi0D_OUT_BITS_29_TO_28_0_merge1_f_ETC__q58 =
merge1_fi0_D_OUT[29:28];
2'd3: CASE_merge1_fi0D_OUT_BITS_29_TO_28_0_merge1_f_ETC__q58 = 2'd3;
endcase
end
always@(merge1_fi0_D_OUT)
begin
case (merge1_fi0_D_OUT[19:18])
2'd0, 2'd1, 2'd2:
CASE_merge1_fi0D_OUT_BITS_19_TO_18_0_merge1_f_ETC__q59 =
merge1_fi0_D_OUT[19:18];
2'd3: CASE_merge1_fi0D_OUT_BITS_19_TO_18_0_merge1_f_ETC__q59 = 2'd3;
endcase
end
always@(merge1_fi0_D_OUT)
begin
case (merge1_fi0_D_OUT[9:8])
2'd0, 2'd1, 2'd2:
CASE_merge1_fi0D_OUT_BITS_9_TO_8_0_merge1_fi0_ETC__q60 =
merge1_fi0_D_OUT[9:8];
2'd3: CASE_merge1_fi0D_OUT_BITS_9_TO_8_0_merge1_fi0_ETC__q60 = 2'd3;
endcase
end
always@(merge1_fi1_D_OUT)
begin
case (merge1_fi1_D_OUT[39:38])
2'd0, 2'd1, 2'd2:
CASE_merge1_fi1D_OUT_BITS_39_TO_38_0_merge1_f_ETC__q61 =
merge1_fi1_D_OUT[39:38];
2'd3: CASE_merge1_fi1D_OUT_BITS_39_TO_38_0_merge1_f_ETC__q61 = 2'd3;
endcase
end
always@(merge1_fi1_D_OUT)
begin
case (merge1_fi1_D_OUT[29:28])
2'd0, 2'd1, 2'd2:
CASE_merge1_fi1D_OUT_BITS_29_TO_28_0_merge1_f_ETC__q62 =
merge1_fi1_D_OUT[29:28];
2'd3: CASE_merge1_fi1D_OUT_BITS_29_TO_28_0_merge1_f_ETC__q62 = 2'd3;
endcase
end
always@(merge1_fi1_D_OUT)
begin
case (merge1_fi1_D_OUT[19:18])
2'd0, 2'd1, 2'd2:
CASE_merge1_fi1D_OUT_BITS_19_TO_18_0_merge1_f_ETC__q63 =
merge1_fi1_D_OUT[19:18];
2'd3: CASE_merge1_fi1D_OUT_BITS_19_TO_18_0_merge1_f_ETC__q63 = 2'd3;
endcase
end
always@(merge1_fi1_D_OUT)
begin
case (merge1_fi1_D_OUT[9:8])
2'd0, 2'd1, 2'd2:
CASE_merge1_fi1D_OUT_BITS_9_TO_8_0_merge1_fi1_ETC__q64 =
merge1_fi1_D_OUT[9:8];
2'd3: CASE_merge1_fi1D_OUT_BITS_9_TO_8_0_merge1_fi1_ETC__q64 = 2'd3;
endcase
end
always@(fork0_sr)
begin
case (fork0_sr[119:118])
2'd0, 2'd1, 2'd2:
CASE_fork0_sr_BITS_119_TO_118_0_fork0_sr_BITS__ETC__q65 =
fork0_sr[119:118];
2'd3: CASE_fork0_sr_BITS_119_TO_118_0_fork0_sr_BITS__ETC__q65 = 2'd3;
endcase
end
always@(fork0_sr)
begin
case (fork0_sr[109:108])
2'd0, 2'd1, 2'd2:
CASE_fork0_sr_BITS_109_TO_108_0_fork0_sr_BITS__ETC__q66 =
fork0_sr[109:108];
2'd3: CASE_fork0_sr_BITS_109_TO_108_0_fork0_sr_BITS__ETC__q66 = 2'd3;
endcase
end
always@(fork0_sr)
begin
case (fork0_sr[99:98])
2'd0, 2'd1, 2'd2:
CASE_fork0_sr_BITS_99_TO_98_0_fork0_sr_BITS_99_ETC__q67 =
fork0_sr[99:98];
2'd3: CASE_fork0_sr_BITS_99_TO_98_0_fork0_sr_BITS_99_ETC__q67 = 2'd3;
endcase
end
always@(fork0_sr)
begin
case (fork0_sr[89:88])
2'd0, 2'd1, 2'd2:
CASE_fork0_sr_BITS_89_TO_88_0_fork0_sr_BITS_89_ETC__q68 =
fork0_sr[89:88];
2'd3: CASE_fork0_sr_BITS_89_TO_88_0_fork0_sr_BITS_89_ETC__q68 = 2'd3;
endcase
end
always@(fork0_sr)
begin
case (fork0_sr[79:78])
2'd0, 2'd1, 2'd2:
CASE_fork0_sr_BITS_79_TO_78_0_fork0_sr_BITS_79_ETC__q69 =
fork0_sr[79:78];
2'd3: CASE_fork0_sr_BITS_79_TO_78_0_fork0_sr_BITS_79_ETC__q69 = 2'd3;
endcase
end
always@(fork0_sr)
begin
case (fork0_sr[69:68])
2'd0, 2'd1, 2'd2:
CASE_fork0_sr_BITS_69_TO_68_0_fork0_sr_BITS_69_ETC__q70 =
fork0_sr[69:68];
2'd3: CASE_fork0_sr_BITS_69_TO_68_0_fork0_sr_BITS_69_ETC__q70 = 2'd3;
endcase
end
always@(fork0_sr)
begin
case (fork0_sr[59:58])
2'd0, 2'd1, 2'd2:
CASE_fork0_sr_BITS_59_TO_58_0_fork0_sr_BITS_59_ETC__q71 =
fork0_sr[59:58];
2'd3: CASE_fork0_sr_BITS_59_TO_58_0_fork0_sr_BITS_59_ETC__q71 = 2'd3;
endcase
end
always@(fork0_sr)
begin
case (fork0_sr[49:48])
2'd0, 2'd1, 2'd2:
CASE_fork0_sr_BITS_49_TO_48_0_fork0_sr_BITS_49_ETC__q72 =
fork0_sr[49:48];
2'd3: CASE_fork0_sr_BITS_49_TO_48_0_fork0_sr_BITS_49_ETC__q72 = 2'd3;
endcase
end
always@(server_request_put)
begin
case (server_request_put[39:38])
2'd0, 2'd1, 2'd2:
CASE_server_request_put_BITS_39_TO_38_0_server_ETC__q73 =
server_request_put[39:38];
2'd3: CASE_server_request_put_BITS_39_TO_38_0_server_ETC__q73 = 2'd3;
endcase
end
always@(server_request_put)
begin
case (server_request_put[29:28])
2'd0, 2'd1, 2'd2:
CASE_server_request_put_BITS_29_TO_28_0_server_ETC__q74 =
server_request_put[29:28];
2'd3: CASE_server_request_put_BITS_29_TO_28_0_server_ETC__q74 = 2'd3;
endcase
end
always@(server_request_put)
begin
case (server_request_put[19:18])
2'd0, 2'd1, 2'd2:
CASE_server_request_put_BITS_19_TO_18_0_server_ETC__q75 =
server_request_put[19:18];
2'd3: CASE_server_request_put_BITS_19_TO_18_0_server_ETC__q75 = 2'd3;
endcase
end
always@(server_request_put)
begin
case (server_request_put[9:8])
2'd0, 2'd1, 2'd2:
CASE_server_request_put_BITS_9_TO_8_0_server_r_ETC__q76 =
server_request_put[9:8];
2'd3: CASE_server_request_put_BITS_9_TO_8_0_server_r_ETC__q76 = 2'd3;
endcase
end
always@(fork1_sr)
begin
case (fork1_sr[119:118])
2'd0, 2'd1, 2'd2:
CASE_fork1_sr_BITS_119_TO_118_0_fork1_sr_BITS__ETC__q77 =
fork1_sr[119:118];
2'd3: CASE_fork1_sr_BITS_119_TO_118_0_fork1_sr_BITS__ETC__q77 = 2'd3;
endcase
end
always@(fork1_sr)
begin
case (fork1_sr[109:108])
2'd0, 2'd1, 2'd2:
CASE_fork1_sr_BITS_109_TO_108_0_fork1_sr_BITS__ETC__q78 =
fork1_sr[109:108];
2'd3: CASE_fork1_sr_BITS_109_TO_108_0_fork1_sr_BITS__ETC__q78 = 2'd3;
endcase
end
always@(fork1_sr)
begin
case (fork1_sr[99:98])
2'd0, 2'd1, 2'd2:
CASE_fork1_sr_BITS_99_TO_98_0_fork1_sr_BITS_99_ETC__q79 =
fork1_sr[99:98];
2'd3: CASE_fork1_sr_BITS_99_TO_98_0_fork1_sr_BITS_99_ETC__q79 = 2'd3;
endcase
end
always@(fork1_sr)
begin
case (fork1_sr[89:88])
2'd0, 2'd1, 2'd2:
CASE_fork1_sr_BITS_89_TO_88_0_fork1_sr_BITS_89_ETC__q80 =
fork1_sr[89:88];
2'd3: CASE_fork1_sr_BITS_89_TO_88_0_fork1_sr_BITS_89_ETC__q80 = 2'd3;
endcase
end
always@(fork1_sr)
begin
case (fork1_sr[79:78])
2'd0, 2'd1, 2'd2:
CASE_fork1_sr_BITS_79_TO_78_0_fork1_sr_BITS_79_ETC__q81 =
fork1_sr[79:78];
2'd3: CASE_fork1_sr_BITS_79_TO_78_0_fork1_sr_BITS_79_ETC__q81 = 2'd3;
endcase
end
always@(fork1_sr)
begin
case (fork1_sr[69:68])
2'd0, 2'd1, 2'd2:
CASE_fork1_sr_BITS_69_TO_68_0_fork1_sr_BITS_69_ETC__q82 =
fork1_sr[69:68];
2'd3: CASE_fork1_sr_BITS_69_TO_68_0_fork1_sr_BITS_69_ETC__q82 = 2'd3;
endcase
end
always@(fork1_sr)
begin
case (fork1_sr[59:58])
2'd0, 2'd1, 2'd2:
CASE_fork1_sr_BITS_59_TO_58_0_fork1_sr_BITS_59_ETC__q83 =
fork1_sr[59:58];
2'd3: CASE_fork1_sr_BITS_59_TO_58_0_fork1_sr_BITS_59_ETC__q83 = 2'd3;
endcase
end
always@(fork1_sr)
begin
case (fork1_sr[49:48])
2'd0, 2'd1, 2'd2:
CASE_fork1_sr_BITS_49_TO_48_0_fork1_sr_BITS_49_ETC__q84 =
fork1_sr[49:48];
2'd3: CASE_fork1_sr_BITS_49_TO_48_0_fork1_sr_BITS_49_ETC__q84 = 2'd3;
endcase
end
always@(fork0_d1F_D_OUT)
begin
case (fork0_d1F_D_OUT[39:38])
2'd0, 2'd1, 2'd2:
CASE_fork0_d1FD_OUT_BITS_39_TO_38_0_fork0_d1F_ETC__q85 =
fork0_d1F_D_OUT[39:38];
2'd3: CASE_fork0_d1FD_OUT_BITS_39_TO_38_0_fork0_d1F_ETC__q85 = 2'd3;
endcase
end
always@(fork0_d1F_D_OUT)
begin
case (fork0_d1F_D_OUT[29:28])
2'd0, 2'd1, 2'd2:
CASE_fork0_d1FD_OUT_BITS_29_TO_28_0_fork0_d1F_ETC__q86 =
fork0_d1F_D_OUT[29:28];
2'd3: CASE_fork0_d1FD_OUT_BITS_29_TO_28_0_fork0_d1F_ETC__q86 = 2'd3;
endcase
end
always@(fork0_d1F_D_OUT)
begin
case (fork0_d1F_D_OUT[19:18])
2'd0, 2'd1, 2'd2:
CASE_fork0_d1FD_OUT_BITS_19_TO_18_0_fork0_d1F_ETC__q87 =
fork0_d1F_D_OUT[19:18];
2'd3: CASE_fork0_d1FD_OUT_BITS_19_TO_18_0_fork0_d1F_ETC__q87 = 2'd3;
endcase
end
always@(fork0_d1F_D_OUT)
begin
case (fork0_d1F_D_OUT[9:8])
2'd0, 2'd1, 2'd2:
CASE_fork0_d1FD_OUT_BITS_9_TO_8_0_fork0_d1FD_ETC__q88 =
fork0_d1F_D_OUT[9:8];
2'd3: CASE_fork0_d1FD_OUT_BITS_9_TO_8_0_fork0_d1FD_ETC__q88 = 2'd3;
endcase
end
always@(client0_response_put)
begin
case (client0_response_put[39:38])
2'd0, 2'd1, 2'd2:
CASE_client0_response_put_BITS_39_TO_38_0_clie_ETC__q89 =
client0_response_put[39:38];
2'd3: CASE_client0_response_put_BITS_39_TO_38_0_clie_ETC__q89 = 2'd3;
endcase
end
always@(client0_response_put)
begin
case (client0_response_put[29:28])
2'd0, 2'd1, 2'd2:
CASE_client0_response_put_BITS_29_TO_28_0_clie_ETC__q90 =
client0_response_put[29:28];
2'd3: CASE_client0_response_put_BITS_29_TO_28_0_clie_ETC__q90 = 2'd3;
endcase
end
always@(client0_response_put)
begin
case (client0_response_put[19:18])
2'd0, 2'd1, 2'd2:
CASE_client0_response_put_BITS_19_TO_18_0_clie_ETC__q91 =
client0_response_put[19:18];
2'd3: CASE_client0_response_put_BITS_19_TO_18_0_clie_ETC__q91 = 2'd3;
endcase
end
always@(client0_response_put)
begin
case (client0_response_put[9:8])
2'd0, 2'd1, 2'd2:
CASE_client0_response_put_BITS_9_TO_8_0_client_ETC__q92 =
client0_response_put[9:8];
2'd3: CASE_client0_response_put_BITS_9_TO_8_0_client_ETC__q92 = 2'd3;
endcase
end
always@(merge1_fo_D_OUT)
begin
case (merge1_fo_D_OUT[39:38])
2'd0, 2'd1, 2'd2:
CASE_merge1_foD_OUT_BITS_39_TO_38_0_merge1_fo_ETC__q93 =
merge1_fo_D_OUT[39:38];
2'd3: CASE_merge1_foD_OUT_BITS_39_TO_38_0_merge1_fo_ETC__q93 = 2'd3;
endcase
end
always@(merge1_fo_D_OUT)
begin
case (merge1_fo_D_OUT[29:28])
2'd0, 2'd1, 2'd2:
CASE_merge1_foD_OUT_BITS_29_TO_28_0_merge1_fo_ETC__q94 =
merge1_fo_D_OUT[29:28];
2'd3: CASE_merge1_foD_OUT_BITS_29_TO_28_0_merge1_fo_ETC__q94 = 2'd3;
endcase
end
always@(merge1_fo_D_OUT)
begin
case (merge1_fo_D_OUT[19:18])
2'd0, 2'd1, 2'd2:
CASE_merge1_foD_OUT_BITS_19_TO_18_0_merge1_fo_ETC__q95 =
merge1_fo_D_OUT[19:18];
2'd3: CASE_merge1_foD_OUT_BITS_19_TO_18_0_merge1_fo_ETC__q95 = 2'd3;
endcase
end
always@(merge1_fo_D_OUT)
begin
case (merge1_fo_D_OUT[9:8])
2'd0, 2'd1, 2'd2:
CASE_merge1_foD_OUT_BITS_9_TO_8_0_merge1_foD_ETC__q96 =
merge1_fo_D_OUT[9:8];
2'd3: CASE_merge1_foD_OUT_BITS_9_TO_8_0_merge1_foD_ETC__q96 = 2'd3;
endcase
end
always@(client1_response_put)
begin
case (client1_response_put[39:38])
2'd0, 2'd1, 2'd2:
CASE_client1_response_put_BITS_39_TO_38_0_clie_ETC__q97 =
client1_response_put[39:38];
2'd3: CASE_client1_response_put_BITS_39_TO_38_0_clie_ETC__q97 = 2'd3;
endcase
end
always@(client1_response_put)
begin
case (client1_response_put[29:28])
2'd0, 2'd1, 2'd2:
CASE_client1_response_put_BITS_29_TO_28_0_clie_ETC__q98 =
client1_response_put[29:28];
2'd3: CASE_client1_response_put_BITS_29_TO_28_0_clie_ETC__q98 = 2'd3;
endcase
end
always@(client1_response_put)
begin
case (client1_response_put[19:18])
2'd0, 2'd1, 2'd2:
CASE_client1_response_put_BITS_19_TO_18_0_clie_ETC__q99 =
client1_response_put[19:18];
2'd3: CASE_client1_response_put_BITS_19_TO_18_0_clie_ETC__q99 = 2'd3;
endcase
end
always@(client1_response_put)
begin
case (client1_response_put[9:8])
2'd0, 2'd1, 2'd2:
CASE_client1_response_put_BITS_9_TO_8_0_client_ETC__q100 =
client1_response_put[9:8];
2'd3: CASE_client1_response_put_BITS_9_TO_8_0_client_ETC__q100 = 2'd3;
endcase
end
always@(client2_response_put)
begin
case (client2_response_put[39:38])
2'd0, 2'd1, 2'd2:
CASE_client2_response_put_BITS_39_TO_38_0_clie_ETC__q101 =
client2_response_put[39:38];
2'd3: CASE_client2_response_put_BITS_39_TO_38_0_clie_ETC__q101 = 2'd3;
endcase
end
always@(client2_response_put)
begin
case (client2_response_put[29:28])
2'd0, 2'd1, 2'd2:
CASE_client2_response_put_BITS_29_TO_28_0_clie_ETC__q102 =
client2_response_put[29:28];
2'd3: CASE_client2_response_put_BITS_29_TO_28_0_clie_ETC__q102 = 2'd3;
endcase
end
always@(client2_response_put)
begin
case (client2_response_put[19:18])
2'd0, 2'd1, 2'd2:
CASE_client2_response_put_BITS_19_TO_18_0_clie_ETC__q103 =
client2_response_put[19:18];
2'd3: CASE_client2_response_put_BITS_19_TO_18_0_clie_ETC__q103 = 2'd3;
endcase
end
always@(client2_response_put)
begin
case (client2_response_put[9:8])
2'd0, 2'd1, 2'd2:
CASE_client2_response_put_BITS_9_TO_8_0_client_ETC__q104 =
client2_response_put[9:8];
2'd3: CASE_client2_response_put_BITS_9_TO_8_0_client_ETC__q104 = 2'd3;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
fork0_decided <= `BSV_ASSIGNMENT_DELAY 1'd0;
fork0_match0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
fork0_ptr <= `BSV_ASSIGNMENT_DELAY 3'd0;
fork0_stageSent <= `BSV_ASSIGNMENT_DELAY 1'd0;
fork0_staged <= `BSV_ASSIGNMENT_DELAY 1'd0;
fork1_decided <= `BSV_ASSIGNMENT_DELAY 1'd0;
fork1_match0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
fork1_ptr <= `BSV_ASSIGNMENT_DELAY 3'd0;
fork1_stageSent <= `BSV_ASSIGNMENT_DELAY 1'd0;
fork1_staged <= `BSV_ASSIGNMENT_DELAY 1'd0;
merge0_fi0Active <= `BSV_ASSIGNMENT_DELAY 1'd0;
merge0_fi0HasPrio <= `BSV_ASSIGNMENT_DELAY 1'd1;
merge0_fi1Active <= `BSV_ASSIGNMENT_DELAY 1'd0;
merge1_fi0Active <= `BSV_ASSIGNMENT_DELAY 1'd0;
merge1_fi0HasPrio <= `BSV_ASSIGNMENT_DELAY 1'd1;
merge1_fi1Active <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (fork0_decided_EN)
fork0_decided <= `BSV_ASSIGNMENT_DELAY fork0_decided_D_IN;
if (fork0_match0_EN)
fork0_match0 <= `BSV_ASSIGNMENT_DELAY fork0_match0_D_IN;
if (fork0_ptr_EN) fork0_ptr <= `BSV_ASSIGNMENT_DELAY fork0_ptr_D_IN;
if (fork0_stageSent_EN)
fork0_stageSent <= `BSV_ASSIGNMENT_DELAY fork0_stageSent_D_IN;
if (fork0_staged_EN)
fork0_staged <= `BSV_ASSIGNMENT_DELAY fork0_staged_D_IN;
if (fork1_decided_EN)
fork1_decided <= `BSV_ASSIGNMENT_DELAY fork1_decided_D_IN;
if (fork1_match0_EN)
fork1_match0 <= `BSV_ASSIGNMENT_DELAY fork1_match0_D_IN;
if (fork1_ptr_EN) fork1_ptr <= `BSV_ASSIGNMENT_DELAY fork1_ptr_D_IN;
if (fork1_stageSent_EN)
fork1_stageSent <= `BSV_ASSIGNMENT_DELAY fork1_stageSent_D_IN;
if (fork1_staged_EN)
fork1_staged <= `BSV_ASSIGNMENT_DELAY fork1_staged_D_IN;
if (merge0_fi0Active_EN)
merge0_fi0Active <= `BSV_ASSIGNMENT_DELAY merge0_fi0Active_D_IN;
if (merge0_fi0HasPrio_EN)
merge0_fi0HasPrio <= `BSV_ASSIGNMENT_DELAY merge0_fi0HasPrio_D_IN;
if (merge0_fi1Active_EN)
merge0_fi1Active <= `BSV_ASSIGNMENT_DELAY merge0_fi1Active_D_IN;
if (merge1_fi0Active_EN)
merge1_fi0Active <= `BSV_ASSIGNMENT_DELAY merge1_fi0Active_D_IN;
if (merge1_fi0HasPrio_EN)
merge1_fi0HasPrio <= `BSV_ASSIGNMENT_DELAY merge1_fi0HasPrio_D_IN;
if (merge1_fi1Active_EN)
merge1_fi1Active <= `BSV_ASSIGNMENT_DELAY merge1_fi1Active_D_IN;
end
if (fork0_sr_EN) fork0_sr <= `BSV_ASSIGNMENT_DELAY fork0_sr_D_IN;
if (fork1_sr_EN) fork1_sr <= `BSV_ASSIGNMENT_DELAY fork1_sr_D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
fork0_decided = 1'h0;
fork0_match0 = 1'h0;
fork0_ptr = 3'h2;
fork0_sr = 120'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
fork0_stageSent = 1'h0;
fork0_staged = 1'h0;
fork1_decided = 1'h0;
fork1_match0 = 1'h0;
fork1_ptr = 3'h2;
fork1_sr = 120'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
fork1_stageSent = 1'h0;
fork1_staged = 1'h0;
merge0_fi0Active = 1'h0;
merge0_fi0HasPrio = 1'h0;
merge0_fi1Active = 1'h0;
merge1_fi0Active = 1'h0;
merge1_fi0HasPrio = 1'h0;
merge1_fi1Active = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkQABSMF3
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: bios86.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module bios86 (
address,
clock,
q);
input [10:0] address;
input clock;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({8{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../bios86.mif",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2048,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 11,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../bios86.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../bios86.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL bios86.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL bios86.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bios86.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bios86.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bios86_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bios86_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPVGND_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__TAPVGND_BEHAVIORAL_PP_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection 1
* row down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hs__tapvgnd (
VGND,
VPWR
);
// Module ports
input VGND;
input VPWR;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPVGND_BEHAVIORAL_PP_V |
module OpcodeBufferTest;
`include "Framework.v"
reg reset;
reg clk;
always #10 clk = ~clk;
reg [31:0] addrA;
wire [31:0] addrB;
reg writeEnable = 0;
reg [7:0] dataIn;
reg requestA;
wire requestB;
wire [7:0] outA;
wire [7:0] outB;
wire busyA;
wire busyB;
wire [15:0] displayIn = 0;
wire [31:0] displayAddr;
wire displayWE;
Display dsp(clk, displayIn);
wire [31:0] mmioInB;
wire [31:0] mmioAddrB;
wire mmioWEB;
SimpleMmu mmu(clk, reset, addrA, addrB, writeEnable, dataIn, requestA, requestB, outA, outB, busyA, busyB,
displayIn,displayAddr,displayWE, mmioInB, mmioAddrB, mmioWEB);
reg [31:0] ip;
wire busy;
wire [31:0] opcode;
reg startLoading;
OpcodeBuffer ob(clk, reset, ip, startLoading, outB, busyB, busy, opcode, addrB, requestB);
initial begin
$dumpfile("timing.vcd");
$dumpvars(0,mmu,ob);
reset = 1;
clk = 0;
#20 reset = 0;
ip = 0;
startLoading = 1;
#300 @(negedge busy) $display("Got opcode: %h = %h", ip, opcode);
#10 startLoading = 0;
ip = 4;
startLoading = 1;
#300 @(negedge busy) $display("Got opcode: %h = %h", ip, opcode);
ip = 8;
startLoading = 1;
#300 @(negedge busy) $display("Got opcode: %h = %h", ip, opcode);
$finish;
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: K.39
// \ \ Application: netgen
// / / Filename: FIR_SCALE.v
// /___/ /\ Timestamp: Wed Mar 24 14:52:18 2010
// \ \ / \
// \___\/\___\
//
// Command : -intstyle ise -w -sim -ofmt verilog C:\XilinxProjects\FONT5_9Chan\tmp\_cg\FIR_SCALE.ngc C:\XilinxProjects\FONT5_9Chan\tmp\_cg\FIR_SCALE.v
// Device : 5vlx50tff1136-3
// Input file : C:/XilinxProjects/FONT5_9Chan/tmp/_cg/FIR_SCALE.ngc
// Output file : C:/XilinxProjects/FONT5_9Chan/tmp/_cg/FIR_SCALE.v
// # of Modules : 1
// Design Name : FIR_SCALE
// Xilinx : C:\Xilinx\10.1\ISE
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Development System Reference Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module FIR_SCALE (
clk, a, b, p
);
input clk;
input [41 : 0] a;
input [6 : 0] b;
output [48 : 0] p;
// synthesis translate_off
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bdel_temp<0><0>[0] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bdel_temp<0><0>[1] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bdel_temp<0><0>[2] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bdel_temp<0><0>[3] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bdel_temp<0><0>[4] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bdel_temp<0><0>[5] ;
wire \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bdel_temp<0><0>[10] ;
wire \BU2/N1 ;
wire NLW_VCC_P_UNCONNECTED;
wire NLW_GND_G_UNCONNECTED;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_PATTERNBDETECT_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_PATTERNDETECT_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_OVERFLOW_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_UNDERFLOW_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_CARRYCASCOUT_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_MULTSIGNOUT_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<47>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<46>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<45>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<44>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<43>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<42>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<41>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<40>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<39>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<38>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<37>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<36>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<35>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<34>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<33>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<32>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<31>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<30>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<29>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<28>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<27>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<26>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<25>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<24>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<23>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<22>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<21>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<20>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<19>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<18>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<17>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<29>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<28>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<27>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<26>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<25>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<24>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<23>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<22>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<21>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<20>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<19>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<18>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<17>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<16>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<15>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<14>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<13>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<12>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<11>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<10>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<9>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<8>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<7>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<6>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<5>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<4>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<3>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<2>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<1>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<0>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_PATTERNBDETECT_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_PATTERNDETECT_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_OVERFLOW_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_UNDERFLOW_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_CARRYCASCOUT_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_MULTSIGNOUT_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_P<47>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_P<46>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_P<45>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_P<44>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_P<43>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_BCOUT<17>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_BCOUT<16>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_BCOUT<15>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_BCOUT<14>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_BCOUT<13>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_BCOUT<12>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_BCOUT<11>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_BCOUT<10>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_BCOUT<9>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_BCOUT<8>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_BCOUT<7>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_BCOUT<6>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_BCOUT<5>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_BCOUT<4>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_BCOUT<3>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_BCOUT<2>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_BCOUT<1>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_BCOUT<0>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<29>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<28>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<27>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<26>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<25>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<24>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<23>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<22>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<21>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<20>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<19>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<18>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<17>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<16>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<15>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<14>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<13>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<12>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<11>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<10>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<9>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<8>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<7>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<6>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<5>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<4>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<3>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<2>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<1>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<0>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_CARRYOUT<0>_UNCONNECTED ;
wire [16 : 0] p_2;
wire [16 : 0] \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<0><0> ;
wire [17 : 0] \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> ;
wire [42 : 0] \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> ;
wire [17 : 0] \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bcout<0><0> ;
wire [47 : 0] \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> ;
wire [24 : 0] \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> ;
wire [47 : 0] \BU2/pcasc ;
assign
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [24] = a[41],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [23] = a[40],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [22] = a[39],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [21] = a[38],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [20] = a[37],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [19] = a[36],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [18] = a[35],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [17] = a[34],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [16] = a[33],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [15] = a[32],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [14] = a[31],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [13] = a[30],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [12] = a[29],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [11] = a[28],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [10] = a[27],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [9] = a[26],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [8] = a[25],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [7] = a[24],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [6] = a[23],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [5] = a[22],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [4] = a[21],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [3] = a[20],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [2] = a[19],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [1] = a[18],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [0] = a[17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [16] = a[16],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [15] = a[15],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [14] = a[14],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [13] = a[13],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [12] = a[12],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [11] = a[11],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [10] = a[10],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [9] = a[9],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [8] = a[8],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [7] = a[7],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [6] = a[6],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [5] = a[5],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [4] = a[4],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [3] = a[3],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [2] = a[2],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [1] = a[1],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [0] = a[0],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bdel_temp<0><0>[10] = b[6],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bdel_temp<0><0>[5] = b[5],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bdel_temp<0><0>[4] = b[4],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bdel_temp<0><0>[3] = b[3],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bdel_temp<0><0>[2] = b[2],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bdel_temp<0><0>[1] = b[1],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bdel_temp<0><0>[0] = b[0],
p[48] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [31],
p[47] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [30],
p[46] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [29],
p[45] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [28],
p[44] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [27],
p[43] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [26],
p[42] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [25],
p[41] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [24],
p[40] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [23],
p[39] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [22],
p[38] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [21],
p[37] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [20],
p[36] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [19],
p[35] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [18],
p[34] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [17],
p[33] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [16],
p[32] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [15],
p[31] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [14],
p[30] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [13],
p[29] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [12],
p[28] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [11],
p[27] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [10],
p[26] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [9],
p[25] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [8],
p[24] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [7],
p[23] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [6],
p[22] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [5],
p[21] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [4],
p[20] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [3],
p[19] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [2],
p[18] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [1],
p[17] = \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [0],
p[16] = p_2[16],
p[15] = p_2[15],
p[14] = p_2[14],
p[13] = p_2[13],
p[12] = p_2[12],
p[11] = p_2[11],
p[10] = p_2[10],
p[9] = p_2[9],
p[8] = p_2[8],
p[7] = p_2[7],
p[6] = p_2[6],
p[5] = p_2[5],
p[4] = p_2[4],
p[3] = p_2[3],
p[2] = p_2[2],
p[1] = p_2[1],
p[0] = p_2[0];
VCC VCC_0 (
.P(NLW_VCC_P_UNCONNECTED)
);
GND GND_1 (
.G(NLW_GND_G_UNCONNECTED)
);
DSP48E #(
.ACASCREG ( 1 ),
.ALUMODEREG ( 0 ),
.AREG ( 1 ),
.AUTORESET_PATTERN_DETECT ( "FALSE" ),
.AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ),
.A_INPUT ( "DIRECT" ),
.BCASCREG ( 1 ),
.BREG ( 1 ),
.B_INPUT ( "DIRECT" ),
.CARRYINREG ( 0 ),
.CARRYINSELREG ( 0 ),
.CREG ( 0 ),
.PATTERN ( 48'h000000000000 ),
.MREG ( 1 ),
.MULTCARRYINREG ( 0 ),
.OPMODEREG ( 0 ),
.PREG ( 1 ),
.SEL_MASK ( "MASK" ),
.SEL_PATTERN ( "PATTERN" ),
.SEL_ROUNDING_MASK ( "SEL_MASK" ),
.SIM_MODE ( "SAFE" ),
.USE_MULT ( "MULT_S" ),
.USE_PATTERN_DETECT ( "NO_PATDET" ),
.USE_SIMD ( "ONE48" ),
.MASK ( 48'h000000000000 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E (
.CARRYIN(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]),
.CEA1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]),
.CEA2(\BU2/N1 ),
.CEB1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]),
.CEB2(\BU2/N1 ),
.CEC(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]),
.CECTRL(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]),
.CEP(\BU2/N1 ),
.CEM(\BU2/N1 ),
.CECARRYIN(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]),
.CEMULTCARRYIN(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]),
.CLK(clk),
.RSTA(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]),
.RSTB(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]),
.RSTC(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]),
.RSTCTRL(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]),
.RSTP(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]),
.RSTM(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]),
.RSTALLCARRYIN(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]),
.CEALUMODE(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]),
.RSTALUMODE(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]),
.PATTERNBDETECT
(\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_PATTERNBDETECT_UNCONNECTED ),
.PATTERNDETECT
(\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_PATTERNDETECT_UNCONNECTED ),
.OVERFLOW
(\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_OVERFLOW_UNCONNECTED ),
.UNDERFLOW
(\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_UNDERFLOW_UNCONNECTED ),
.CARRYCASCIN(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]),
.CARRYCASCOUT
(\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_CARRYCASCOUT_UNCONNECTED ),
.MULTSIGNIN(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]),
.MULTSIGNOUT
(\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_MULTSIGNOUT_UNCONNECTED ),
.A({\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [16],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [15],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [14],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [13],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [12],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [11],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [10],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [9],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [8],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [7],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [6],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [5],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [4],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [3],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [2],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [1],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [0]}),
.PCIN({\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]}),
.B({\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bdel_temp<0><0>[10] ,
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bdel_temp<0><0>[10] ,
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bdel_temp<0><0>[10] ,
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bdel_temp<0><0>[10] ,
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bdel_temp<0><0>[10] ,
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bdel_temp<0><0>[10] ,
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bdel_temp<0><0>[10] ,
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bdel_temp<0><0>[10] ,
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bdel_temp<0><0>[10] ,
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bdel_temp<0><0>[10] ,
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bdel_temp<0><0>[10] ,
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bdel_temp<0><0>[10] ,
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bdel_temp<0><0>[5] ,
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bdel_temp<0><0>[4] ,
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bdel_temp<0><0>[3] ,
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bdel_temp<0><0>[2] ,
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bdel_temp<0><0>[1] ,
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bdel_temp<0><0>[0] }),
.C({\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]}),
.CARRYINSEL({\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]}),
.OPMODE({\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17], \BU2/N1 , \BU2/N1 ,
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17], \BU2/N1 ,
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17], \BU2/N1 }),
.BCIN({\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]}),
.ALUMODE({\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]}),
.PCOUT({\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [47],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [46],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [45],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [44],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [43],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [42],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [41],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [40],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [39],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [38],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [37],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [36],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [35],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [34],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [33],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [32],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [31],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [30],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [29],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [28],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [27],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [26],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [25],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [24],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [23],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [22],
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\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [19],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [18],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [16],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [15],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [14],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [13],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [12],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [11],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [10],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [9],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [8],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [7],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [6],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [5],
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\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [0]}),
.P({\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<47>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<46>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<45>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<44>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<43>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<42>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<41>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<40>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<39>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<38>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<37>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<36>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<35>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<34>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<33>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<32>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<31>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<30>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<29>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<28>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<27>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<26>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<25>_UNCONNECTED ,
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\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<23>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<22>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<21>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<20>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<19>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<18>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_P<17>_UNCONNECTED ,
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<0><0> [16],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<0><0> [15],
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\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<0><0> [6],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<0><0> [5],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<0><0> [4],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<0><0> [3],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<0><0> [2],
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\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<0><0> [0]}),
.BCOUT({\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bcout<0><0> [17],
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\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bcout<0><0> [0]}),
.ACIN({\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
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\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]}),
.ACOUT({
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<29>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<28>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<27>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<26>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<25>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<24>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<23>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<22>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<21>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<20>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<19>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<18>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<17>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<16>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<15>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<14>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<13>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<12>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<11>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<10>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<9>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<8>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<7>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<6>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<5>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<4>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<3>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<2>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<1>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_ACOUT<0>_UNCONNECTED }),
.CARRYOUT({
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_CARRYOUT<3>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_CARRYOUT<2>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_CARRYOUT<1>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].iDSP48E_CARRYOUT<0>_UNCONNECTED })
);
DSP48E #(
.ACASCREG ( 2 ),
.ALUMODEREG ( 0 ),
.AREG ( 2 ),
.AUTORESET_PATTERN_DETECT ( "FALSE" ),
.AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ),
.A_INPUT ( "DIRECT" ),
.BCASCREG ( 1 ),
.BREG ( 1 ),
.B_INPUT ( "CASCADE" ),
.CARRYINREG ( 0 ),
.CARRYINSELREG ( 0 ),
.CREG ( 0 ),
.PATTERN ( 48'h000000000000 ),
.MREG ( 1 ),
.MULTCARRYINREG ( 0 ),
.OPMODEREG ( 0 ),
.PREG ( 1 ),
.SEL_MASK ( "MASK" ),
.SEL_PATTERN ( "PATTERN" ),
.SEL_ROUNDING_MASK ( "SEL_MASK" ),
.SIM_MODE ( "SAFE" ),
.USE_MULT ( "MULT_S" ),
.USE_PATTERN_DETECT ( "NO_PATDET" ),
.USE_SIMD ( "ONE48" ),
.MASK ( 48'h000000000000 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E (
.CARRYIN(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]),
.CEA1(\BU2/N1 ),
.CEA2(\BU2/N1 ),
.CEB1(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]),
.CEB2(\BU2/N1 ),
.CEC(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]),
.CECTRL(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]),
.CEP(\BU2/N1 ),
.CEM(\BU2/N1 ),
.CECARRYIN(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]),
.CEMULTCARRYIN(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]),
.CLK(clk),
.RSTA(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]),
.RSTB(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]),
.RSTC(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]),
.RSTCTRL(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]),
.RSTP(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]),
.RSTM(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]),
.RSTALLCARRYIN(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]),
.CEALUMODE(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]),
.RSTALUMODE(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]),
.PATTERNBDETECT
(\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_PATTERNBDETECT_UNCONNECTED ),
.PATTERNDETECT
(\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_PATTERNDETECT_UNCONNECTED ),
.OVERFLOW
(\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_OVERFLOW_UNCONNECTED ),
.UNDERFLOW
(\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_UNDERFLOW_UNCONNECTED ),
.CARRYCASCIN(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]),
.CARRYCASCOUT
(\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_CARRYCASCOUT_UNCONNECTED ),
.MULTSIGNIN(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]),
.MULTSIGNOUT
(\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_MULTSIGNOUT_UNCONNECTED ),
.A({\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [24],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [23],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [22],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [21],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [20],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [19],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [18],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [16],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [15],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [14],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [13],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [12],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [11],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [10],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [9],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [8],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [7],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [6],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [5],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [4],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [3],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [2],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [1],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp0<1><0> [0]}),
.PCIN({\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [47],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [46],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [45],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [44],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [43],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [42],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [41],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [40],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [39],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [38],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [37],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [36],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [35],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [34],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [33],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [32],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [31],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [30],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [29],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [28],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [27],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [26],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [25],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [24],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [23],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [22],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [21],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [20],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [19],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [18],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [16],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [15],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [14],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [13],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [12],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [11],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [10],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [9],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [8],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [7],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [6],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [5],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [4],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [3],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [2],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [1],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pcout<0><0> [0]}),
.B({\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]}),
.C({\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]}),
.CARRYINSEL({\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]}),
.OPMODE({\BU2/N1 , \BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17], \BU2/N1 ,
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17], \BU2/N1 ,
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17], \BU2/N1 }),
.BCIN({\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bcout<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bcout<0><0> [16],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bcout<0><0> [15],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bcout<0><0> [14],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bcout<0><0> [13],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bcout<0><0> [12],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bcout<0><0> [11],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bcout<0><0> [10],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bcout<0><0> [9],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bcout<0><0> [8],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bcout<0><0> [7],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bcout<0><0> [6],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bcout<0><0> [5],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bcout<0><0> [4],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bcout<0><0> [3],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bcout<0><0> [2],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bcout<0><0> [1],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/bcout<0><0> [0]}),
.ALUMODE({\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]}),
.PCOUT({\BU2/pcasc [47], \BU2/pcasc [46], \BU2/pcasc [45], \BU2/pcasc [44], \BU2/pcasc [43], \BU2/pcasc [42], \BU2/pcasc [41], \BU2/pcasc [40],
\BU2/pcasc [39], \BU2/pcasc [38], \BU2/pcasc [37], \BU2/pcasc [36], \BU2/pcasc [35], \BU2/pcasc [34], \BU2/pcasc [33], \BU2/pcasc [32],
\BU2/pcasc [31], \BU2/pcasc [30], \BU2/pcasc [29], \BU2/pcasc [28], \BU2/pcasc [27], \BU2/pcasc [26], \BU2/pcasc [25], \BU2/pcasc [24],
\BU2/pcasc [23], \BU2/pcasc [22], \BU2/pcasc [21], \BU2/pcasc [20], \BU2/pcasc [19], \BU2/pcasc [18], \BU2/pcasc [17], \BU2/pcasc [16],
\BU2/pcasc [15], \BU2/pcasc [14], \BU2/pcasc [13], \BU2/pcasc [12], \BU2/pcasc [11], \BU2/pcasc [10], \BU2/pcasc [9], \BU2/pcasc [8], \BU2/pcasc [7],
\BU2/pcasc [6], \BU2/pcasc [5], \BU2/pcasc [4], \BU2/pcasc [3], \BU2/pcasc [2], \BU2/pcasc [1], \BU2/pcasc [0]}),
.P({\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_P<47>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_P<46>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_P<45>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_P<44>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_P<43>_UNCONNECTED ,
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [42],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [41],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [40],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [39],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [38],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [37],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [36],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [35],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [34],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [33],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [32],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [31],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [30],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [29],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [28],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [27],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [26],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [25],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [24],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [23],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [22],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [21],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [20],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [19],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [18],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [16],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [15],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [14],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [13],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [12],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [11],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [10],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [9],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [8],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [7],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [6],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [5],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [4],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [3],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [2],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [1],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<1><0> [0]}),
.BCOUT({
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_BCOUT<17>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_BCOUT<16>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_BCOUT<15>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_BCOUT<14>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_BCOUT<13>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_BCOUT<12>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_BCOUT<11>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_BCOUT<10>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_BCOUT<9>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_BCOUT<8>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_BCOUT<7>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_BCOUT<6>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_BCOUT<5>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_BCOUT<4>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_BCOUT<3>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_BCOUT<2>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_BCOUT<1>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_BCOUT<0>_UNCONNECTED }),
.ACIN({\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17],
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17]}),
.ACOUT({
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<29>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<28>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<27>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<26>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<25>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<24>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<23>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<22>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<21>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<20>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<19>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<18>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<17>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<16>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<15>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<14>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<13>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<12>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<11>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<10>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<9>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<8>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<7>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<6>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<5>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<4>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<3>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<2>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<1>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_ACOUT<0>_UNCONNECTED }),
.CARRYOUT({
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_CARRYOUT<3>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_CARRYOUT<2>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_CARRYOUT<1>_UNCONNECTED ,
\NLW_BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[1].bppDSP48E[0].iDSP48E_CARRYOUT<0>_UNCONNECTED })
);
VCC \BU2/XST_VCC (
.P(\BU2/N1 )
);
GND \BU2/XST_GND (
.G(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/adel30_temp<0><0> [17])
);
FD #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].need_output_delay.output_delay/dout_i_16 (
.C(clk),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<0><0> [16]),
.Q(p_2[16])
);
FD #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].need_output_delay.output_delay/dout_i_15 (
.C(clk),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<0><0> [15]),
.Q(p_2[15])
);
FD #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].need_output_delay.output_delay/dout_i_14 (
.C(clk),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<0><0> [14]),
.Q(p_2[14])
);
FD #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].need_output_delay.output_delay/dout_i_13 (
.C(clk),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<0><0> [13]),
.Q(p_2[13])
);
FD #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].need_output_delay.output_delay/dout_i_12 (
.C(clk),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<0><0> [12]),
.Q(p_2[12])
);
FD #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].need_output_delay.output_delay/dout_i_11 (
.C(clk),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<0><0> [11]),
.Q(p_2[11])
);
FD #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].need_output_delay.output_delay/dout_i_10 (
.C(clk),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<0><0> [10]),
.Q(p_2[10])
);
FD #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].need_output_delay.output_delay/dout_i_9 (
.C(clk),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<0><0> [9]),
.Q(p_2[9])
);
FD #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].need_output_delay.output_delay/dout_i_8 (
.C(clk),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<0><0> [8]),
.Q(p_2[8])
);
FD #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].need_output_delay.output_delay/dout_i_7 (
.C(clk),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<0><0> [7]),
.Q(p_2[7])
);
FD #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].need_output_delay.output_delay/dout_i_6 (
.C(clk),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<0><0> [6]),
.Q(p_2[6])
);
FD #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].need_output_delay.output_delay/dout_i_5 (
.C(clk),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<0><0> [5]),
.Q(p_2[5])
);
FD #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].need_output_delay.output_delay/dout_i_4 (
.C(clk),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<0><0> [4]),
.Q(p_2[4])
);
FD #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].need_output_delay.output_delay/dout_i_3 (
.C(clk),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<0><0> [3]),
.Q(p_2[3])
);
FD #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].need_output_delay.output_delay/dout_i_2 (
.C(clk),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<0><0> [2]),
.Q(p_2[2])
);
FD #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].need_output_delay.output_delay/dout_i_1 (
.C(clk),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<0><0> [1]),
.Q(p_2[1])
);
FD #(
.INIT ( 1'b0 ))
\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/use_DSP48E.appDSP48E[0].bppDSP48E[0].need_output_delay.output_delay/dout_i_0 (
.C(clk),
.D(\BU2/U0/i_synth.i_synth_model/gEMBEDDED_MULT.gEMB_MULTS_only.gDSP.iDSP/pi<0><0> [0]),
.Q(p_2[0])
);
// synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
wire GSR;
wire GTS;
wire PRLD;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
// synthesis translate_on
|
/******************************************************************************/
/* FPGA Sort for VC707 ArchLab. TOKYO TECH */
/* Version 2014-11-26 */
/******************************************************************************/
`default_nettype none
`include "define.v"
`include "core.v"
/******************************************************************************/
module top_sim;
reg CLK, RST;
wire CLK100M = CLK;
wire d_busy;
wire d_w;
wire [`DRAMW-1:0] d_din;
wire [`DRAMW-1:0] d_dout;
wire d_douten;
wire [1:0] d_req; // DRAM access request (read/write)
wire [31:0] d_initadr; // dram initial address for the access
wire [31:0] d_blocks; // the number of blocks per one access(read/write)
wire initdone;
wire sortdone;
initial begin CLK=0; forever #50 CLK=~CLK; end
initial begin RST=1; #400 RST=0; end
reg [31:0] cnt;
always @(posedge CLK) cnt <= (RST) ? 0 : cnt + 1;
reg [31:0] lcnt;
always @(posedge CLK) lcnt <= (RST) ? 0 : (c.last_phase && c.initdone) ? lcnt + 1 : lcnt;
reg [31:0] cnt0_0, cnt1_0, cnt2_0, cnt3_0, cnt4_0, cnt5_0, cnt6_0, cnt7_0, cnt8_0;
always @(posedge CLK) cnt0_0 <= (RST) ? 0 : (c.phase_a==0 && c.initdone) ? cnt0_0 + 1 : cnt0_0;
always @(posedge CLK) cnt1_0 <= (RST) ? 0 : (c.phase_a==1 && c.initdone) ? cnt1_0 + 1 : cnt1_0;
always @(posedge CLK) cnt2_0 <= (RST) ? 0 : (c.phase_a==2 && c.initdone) ? cnt2_0 + 1 : cnt2_0;
always @(posedge CLK) cnt3_0 <= (RST) ? 0 : (c.phase_a==3 && c.initdone) ? cnt3_0 + 1 : cnt3_0;
always @(posedge CLK) cnt4_0 <= (RST) ? 0 : (c.phase_a==4 && c.initdone) ? cnt4_0 + 1 : cnt4_0;
always @(posedge CLK) cnt5_0 <= (RST) ? 0 : (c.phase_a==5 && c.initdone) ? cnt5_0 + 1 : cnt5_0;
always @(posedge CLK) cnt6_0 <= (RST) ? 0 : (c.phase_a==6 && c.initdone) ? cnt6_0 + 1 : cnt6_0;
always @(posedge CLK) cnt7_0 <= (RST) ? 0 : (c.phase_a==7 && c.initdone) ? cnt7_0 + 1 : cnt7_0;
always @(posedge CLK) cnt8_0 <= (RST) ? 0 : (c.phase_a==8 && c.initdone) ? cnt8_0 + 1 : cnt8_0;
reg [31:0] cnt0_1, cnt1_1, cnt2_1, cnt3_1, cnt4_1, cnt5_1, cnt6_1, cnt7_1, cnt8_1;
always @(posedge CLK) cnt0_1 <= (RST) ? 0 : (c.phase_b==0 && c.initdone) ? cnt0_1 + 1 : cnt0_1;
always @(posedge CLK) cnt1_1 <= (RST) ? 0 : (c.phase_b==1 && c.initdone) ? cnt1_1 + 1 : cnt1_1;
always @(posedge CLK) cnt2_1 <= (RST) ? 0 : (c.phase_b==2 && c.initdone) ? cnt2_1 + 1 : cnt2_1;
always @(posedge CLK) cnt3_1 <= (RST) ? 0 : (c.phase_b==3 && c.initdone) ? cnt3_1 + 1 : cnt3_1;
always @(posedge CLK) cnt4_1 <= (RST) ? 0 : (c.phase_b==4 && c.initdone) ? cnt4_1 + 1 : cnt4_1;
always @(posedge CLK) cnt5_1 <= (RST) ? 0 : (c.phase_b==5 && c.initdone) ? cnt5_1 + 1 : cnt5_1;
always @(posedge CLK) cnt6_1 <= (RST) ? 0 : (c.phase_b==6 && c.initdone) ? cnt6_1 + 1 : cnt6_1;
always @(posedge CLK) cnt7_1 <= (RST) ? 0 : (c.phase_b==7 && c.initdone) ? cnt7_1 + 1 : cnt7_1;
always @(posedge CLK) cnt8_1 <= (RST) ? 0 : (c.phase_b==8 && c.initdone) ? cnt8_1 + 1 : cnt8_1;
generate
if (`INITTYPE=="reverse" || `INITTYPE=="sorted") begin
always @(posedge CLK) begin /// note
if (c.initdone) begin
$write("%d|%d|state(%d)", cnt[19:0], c.last_phase, c.state);
$write("|");
if (c.F01_deq0) $write("%d", c.F01_dot0); else $write(" ");
if (c.F01_deq1) $write("%d", c.F01_dot1); else $write(" ");
if (c.F01_deq2) $write("%d", c.F01_dot2); else $write(" ");
if (c.F01_deq3) $write("%d", c.F01_dot3); else $write(" ");
$write("|");
if (d.app_wdf_wren) $write(" |M%d %d ", d_din[63:32], d_din[31:0]);
$write("\n");
$fflush();
end
end
always @(posedge CLK) begin
if (c.sortdone) begin : simulation_finish
$write("\nIt takes %d cycles\n", cnt);
$write("last(%1d): %d cycles\n", `LAST_PHASE, lcnt);
$write("phase0: %d %d cycles\n", cnt0_0, cnt0_1);
$write("phase1: %d %d cycles\n", cnt1_0, cnt1_1);
$write("phase2: %d %d cycles\n", cnt2_0, cnt2_1);
$write("phase3: %d %d cycles\n", cnt3_0, cnt3_1);
$write("phase4: %d %d cycles\n", cnt4_0, cnt4_1);
$write("phase5: %d %d cycles\n", cnt5_0, cnt5_1);
$write("phase6: %d %d cycles\n", cnt6_0, cnt6_1);
$write("phase7: %d %d cycles\n", cnt7_0, cnt7_1);
$write("phase8: %d %d cycles\n", cnt8_0, cnt8_1);
$write("Sorting finished!\n");
$finish();
end
end
end else if (`INITTYPE == "xorshift") begin
integer fp;
initial begin
fp = $fopen("test.txt", "w");
end
always @(posedge CLK) begin /// note
if (c.last_phase && c.F01_deq0) begin
$write("%08x ", c.F01_dot0);
$fwrite(fp, "%08x ", c.F01_dot0);
$fflush();
end
if (c.sortdone) begin
$fclose(fp);
$finish();
end
end
end
endgenerate
/***** DRAM Controller & DRAM Instantiation *****/
/**********************************************************************************************/
DRAM d(CLK, RST, d_req, d_initadr, d_blocks, d_din, d_w, d_dout, d_douten, d_busy);
wire ERROR;
/***** Core Module Instantiation *****/
/**********************************************************************************************/
CORE c(CLK100M, RST, initdone, sortdone,
d_busy, d_din, d_w, d_dout, d_douten, d_req, d_initadr, d_blocks, ERROR);
endmodule
/**************************************************************************************************/
/**************************************************************************************************/
module DRAM (input wire CLK, //
input wire RST, //
input wire [1:0] D_REQ, // dram request, load or store
input wire [31:0] D_INITADR, // dram request, initial address
input wire [31:0] D_ELEM, // dram request, the number of elements
input wire [`DRAMW-1:0] D_DIN, //
output wire D_W, //
output reg [`DRAMW-1:0] D_DOUT, //
output reg D_DOUTEN, //
output wire D_BUSY); //
/******* DRAM ******************************************************/
localparam M_REQ = 0;
localparam M_WRITE = 1;
localparam M_READ = 2;
///////////////////////////////////////////////////////////////////////////////////
reg [`DDR3_CMD] app_cmd;
reg app_en;
wire [`DRAMW-1:0] app_wdf_data;
reg app_wdf_wren;
wire app_wdf_end = app_wdf_wren;
// outputs of u_dram
wire [`DRAMW-1:0] app_rd_data;
wire app_rd_data_end;
wire app_rd_data_valid=1; // in simulation, always ready !!
wire app_rdy = 1; // in simulation, always ready !!
wire app_wdf_rdy = 1; // in simulation, always ready !!
wire ui_clk = CLK;
reg [1:0] mode;
reg [`DRAMW-1:0] app_wdf_data_buf;
reg [31:0] caddr; // check address
reg [31:0] remain, remain2; //
reg [7:0] req_state; //
///////////////////////////////////////////////////////////////////////////////////
reg [`DRAMW-1:0] mem [`DRAM_SIZE-1:0];
reg [31:0] app_addr;
reg [31:0] dram_addr;
always @(posedge CLK) dram_addr <= app_addr;
always @(posedge CLK) begin /***** DRAM WRITE *****/
if (RST) begin end
else if(app_wdf_wren) mem[dram_addr[27:3]] <= app_wdf_data;
end
assign app_rd_data = mem[app_addr[27:3]];
assign app_wdf_data = D_DIN;
assign D_BUSY = (mode!=M_REQ); // DRAM busy
assign D_W = (mode==M_WRITE && app_rdy && app_wdf_rdy); // store one element
///// READ & WRITE PORT CONTROL (begin) ////////////////////////////////////////////
always @(posedge ui_clk) begin
if (RST) begin
mode <= M_REQ;
{app_addr, app_cmd, app_en, app_wdf_wren} <= 0;
{D_DOUT, D_DOUTEN} <= 0;
{caddr, remain, remain2, req_state} <= 0;
end else begin
case (mode)
///////////////////////////////////////////////////////////////// request
M_REQ: begin
D_DOUTEN <= 0;
if(D_REQ==`DRAM_REQ_WRITE) begin ///// WRITE or STORE request
app_cmd <= `DRAM_CMD_WRITE;
mode <= M_WRITE;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // the number of blocks to be written
end
else if(D_REQ==`DRAM_REQ_READ) begin ///// READ or LOAD request
app_cmd <= `DRAM_CMD_READ;
mode <= M_READ;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // param, the number of blocks to be read
remain2 <= D_ELEM; // param, the number of blocks to be read
end
else begin
app_wdf_wren <= 0;
app_en <= 0;
end
end
//////////////////////////////////////////////////////////////////// read
M_READ: begin
if (app_rdy) begin // read request is accepted.
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain2 <= remain2 - 1;
if(remain2==1) app_en <= 0;
end
D_DOUTEN <= app_rd_data_valid; // dram data_out enable
if (app_rd_data_valid) begin
D_DOUT <= app_rd_data;
caddr <= (caddr==`MEM_LAST_ADDR) ? 0 : caddr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
end
end
end
/////////////////////////////////////////////////////////////////// write
M_WRITE: begin
if (app_rdy && app_wdf_rdy) begin
// app_wdf_data <= D_DIN;
app_wdf_wren <= 1;
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
app_en <= 0;
end
end
else app_wdf_wren <= 0;
end
endcase
end
end
///// READ & WRITE PORT CONTROL (end) //////////////////////////////////////
endmodule
/**************************************************************************************************/
`default_nettype wire
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/13/2016 05:51:29 PM
// Design Name:
// Module Name: Testbench_Barrel_Shifter
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Testbench_Barrel_Shifter ();
parameter PERIOD = 10;
parameter EWR=3;
parameter SWR=8;
//inputs
reg clk;
reg rst;
reg load_i;
reg [EWR-1:0] Shift_Value_i;
reg [SWR-1:0] Shift_Data_i;
reg Left_Right_i;
reg Bit_Shift_i;
///////////////////OUTPUT//////////////////////////7
wire [SWR-1:0] N_mant_o;
DW_rbsh_inst uut(
.Data_i(Shift_Data_i),
.Shift_Value_i(Shift_Value_i),
.inst_SH_TC(Left_Right_i),
.Data_o(N_mant_o)
);
integer Contador_shiftvalue = 0;
always begin
#(8*PERIOD/2) Contador_shiftvalue = Contador_shiftvalue + 1;
Shift_Value_i = Contador_shiftvalue;
Left_Right_i = ~Left_Right_i;
#(8*PERIOD/2);
end
always @ (N_mant_o )
begin
$monitor($time,"REA Salida = %b Entrada = %b Numero de Corrimiento: %d",N_mant_o,Shift_Data_i, Shift_Value_i);
$display($time,"TEO Salida = %b Entrada = %b Numero de Corrimiento: %d",(Shift_Data_i>>Shift_Value_i),Shift_Data_i,Shift_Value_i);
end
initial begin
// Initialize Input
rst = 1;
clk = 0;
load_i = 0;
Shift_Value_i = 0;
Shift_Data_i = $random;
Left_Right_i = 0;
Bit_Shift_i = 0;
#40 rst = 0;
load_i = 1;
end
initial begin
#(PERIOD * 1024);
$finish;
end
initial begin
clk = 1'b0;
#(PERIOD/2);
forever
#(PERIOD/2) clk = ~clk;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/24 22:19:13
// Design Name:
// Module Name: Register_with_synch_reset_set_load_behavior_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Register_with_synch_reset_set_load_behavior_tb(
);
reg [3:0] D;
reg Clk, reset, set, load;
wire [3:0] Q;
Register_with_synch_reset_set_load_behavior DUT (.D(D), .Clk(Clk), .reset(reset), .set(set), .load(load), .Q(Q));
initial begin
#300 $finish;
end
initial begin
D = 4'b0000; Clk = 0; reset = 0; set = 0; load = 0;
#10 Clk = 1;
#10 Clk = 0; D = 4'b0101;
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1;
#10 Clk = 0; load = 1;
#10 Clk = 1;
#10 Clk = 0; D = 4'b1001; load = 0;
#10 Clk = 1;
#10 Clk = 0; // 100ns
#10 Clk = 1;
#10 Clk = 0; load = 1;
#10 Clk = 1;
#10 Clk = 0; load = 0;
#10 Clk = 1;
#5 reset = 1;
#5 Clk = 0;
#10 Clk = 1; set = 1;
#10 Clk = 0;
#10 Clk = 1; set = 0;
#5 load = 1;
#5 Clk = 0; // 200ns
#10 Clk = 1;
#5 load = 0;
#5 Clk = 0;
#10 Clk = 1;
#10 Clk = 0; reset = 0;
#10 Clk = 1; set = 1;
#10 Clk = 0;
#10 Clk = 1; set = 0;
#10 Clk = 0; load = 1;
#10 Clk = 1;
#10 Clk = 0; load = 0;// 300ns
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O211AI_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__O211AI_BEHAVIORAL_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__o211ai (
Y ,
A1,
A2,
B1,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, C1, or0_out, B1);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O211AI_BEHAVIORAL_V |
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: one_new2.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module one_new2 (
address,
clock,
q);
input [9:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../newnums2/one_new2.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../newnums2/one_new2.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL one_new2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL one_new2.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL one_new2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL one_new2.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL one_new2_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL one_new2_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:dist_mem_gen:8.0
// IP Revision: 8
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module CHOPLIFTER_DROM (
a,
spo
);
input wire [14 : 0] a;
output wire [7 : 0] spo;
dist_mem_gen_v8_0 #(
.C_FAMILY("zynq"),
.C_ADDR_WIDTH(15),
.C_DEFAULT_DATA("0"),
.C_DEPTH(32768),
.C_HAS_CLK(0),
.C_HAS_D(0),
.C_HAS_DPO(0),
.C_HAS_DPRA(0),
.C_HAS_I_CE(0),
.C_HAS_QDPO(0),
.C_HAS_QDPO_CE(0),
.C_HAS_QDPO_CLK(0),
.C_HAS_QDPO_RST(0),
.C_HAS_QDPO_SRST(0),
.C_HAS_QSPO(0),
.C_HAS_QSPO_CE(0),
.C_HAS_QSPO_RST(0),
.C_HAS_QSPO_SRST(0),
.C_HAS_SPO(1),
.C_HAS_WE(0),
.C_MEM_INIT_FILE("CHOPLIFTER_DROM.mif"),
.C_ELABORATION_DIR("./"),
.C_MEM_TYPE(0),
.C_PIPELINE_STAGES(0),
.C_QCE_JOINED(0),
.C_QUALIFY_WE(0),
.C_READ_MIF(1),
.C_REG_A_D_INPUTS(0),
.C_REG_DPRA_INPUT(0),
.C_SYNC_ENABLE(1),
.C_WIDTH(8),
.C_PARSER_TYPE(1)
) inst (
.a(a),
.d(8'B0),
.dpra(15'B0),
.clk(1'D0),
.we(1'D0),
.i_ce(1'D1),
.qspo_ce(1'D1),
.qdpo_ce(1'D1),
.qdpo_clk(1'D0),
.qspo_rst(1'D0),
.qdpo_rst(1'D0),
.qspo_srst(1'D0),
.qdpo_srst(1'D0),
.spo(spo),
.dpo(),
.qspo(),
.qdpo()
);
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:20:54 03/06/2016
// Design Name: sumcomp4
// Module Name: C:/XilinxP/Practica1/sumcomp4_test.v
// Project Name: Practica1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: sumcomp4
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module sumcomp4_test;
// Inputs
reg x0;
reg x1;
reg x2;
reg x3;
reg y0;
reg y1;
reg y2;
reg y3;
// Outputs
wire S0;
wire S1;
wire S2;
wire S3;
// Instantiate the Unit Under Test (UUT)
sumcomp4 uut (
.x0(x0),
.x1(x1),
.x2(x2),
.x3(x3),
.y0(y0),
.y1(y1),
.y2(y2),
.y3(y3),
.S0(S0),
.S1(S1),
.S2(S2),
.S3(S3)
);
initial begin
$display("...");
// Initialize Inputs
x0 = 0;
x1 = 0;
x2 = 0;
x3 = 0;
y0 = 0;
y1 = 0;
y2 = 0;
y3 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
x0 = 1; x1 = 1; x2 = 0; x3 = 1; y0 = 1; y1 = 0; y2 = 1; y3 = 0; //1011 + 0101
#50;
$display("x = %b%b%b%b, y = %b%b%b%b, z = %b%b%b%b", x3, x2, x1, x0, y3, y2, y1, y0, S3, S2, S1, S0);
x0 = 0; x1 = 1; x2 = 0; x3 = 1; y0 = 1; y1 = 0; y2 = 1; y3 = 1; //1010 + 1101
#50;
$display("x = %b%b%b%b, y = %b%b%b%b, z = %b%b%b%b", x3, x2, x1, x0, y3, y2, y1, y0, S3, S2, S1, S0);
x0 = 1; x1 = 1; x2 = 1; x3 = 1; y0 = 0; y1 = 1; y2 = 1; y3 = 1; //1111 + 1110
#50;
$display("x = %b%b%b%b, y = %b%b%b%b, z = %b%b%b%b", x3, x2, x1, x0, y3, y2, y1, y0, S3, S2, S1, S0);
x0 = 1; x1 = 1; x2 = 1; x3 = 1; y0 = 1; y1 = 1; y2 = 1; y3 = 1; //1111 + 1111
#50;
$display("x = %b%b%b%b, y = %b%b%b%b, z = %b%b%b%b", x3, x2, x1, x0, y3, y2, y1, y0, S3, S2, S1, S0);
x0 = 0; x1 = 0; x2 = 0; x3 = 1; y0 = 0; y1 = 0; y2 = 1; y3 = 0; //1000 + 0100
#50;
$display("x = %b%b%b%b, y = %b%b%b%b, z = %b%b%b%b", x3, x2, x1, x0, y3, y2, y1, y0, S3, S2, S1, S0);
x0 = 0; x1 = 1; x2 = 0; x3 = 1; y0 = 1; y1 = 0; y2 = 0; y3 = 0; //1010 + 0001
#50;
$display("x = %b%b%b%b, y = %b%b%b%b, z = %b%b%b%b", x3, x2, x1, x0, y3, y2, y1, y0, S3, S2, S1, S0);
x0 = 1; x1 = 1; x2 = 1; x3 = 1; y0 = 0; y1 = 0; y2 = 0; y3 = 0; //1111 + 0000
#50;
$display("x = %b%b%b%b, y = %b%b%b%b, z = %b%b%b%b", x3, x2, x1, x0, y3, y2, y1, y0, S3, S2, S1, S0);
x0 = 0; x1 = 1; x2 = 1; x3 = 0; y0 = 1; y1 = 0; y2 = 0; y3 = 1; //0110 + 1001
#50;
$display("x = %b%b%b%b, y = %b%b%b%b, z = %b%b%b%b", x3, x2, x1, x0, y3, y2, y1, y0, S3, S2, S1, S0);
end
endmodule
|
// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2006 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court 408-826-6000 (other locations)
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
// U.S.A email: [email protected]
// =============================================================================/
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_icache.v
// Title : Instruction cache
// Dependencies : lm32_include.v
//
// Version 3.5
// 1. Bug Fix: Instruction cache flushes issued from Instruction Inline Memory
// cause segmentation fault due to incorrect fetches.
//
// Version 3.1
// 1. Feature: Support for user-selected resource usage when implementing
// cache memory. Additional parameters must be defined when invoking module
// lm32_ram. Instruction cache miss mechanism is dependent on branch
// prediction being performed in D stage of pipeline.
//
// Version 7.0SP2, 3.0
// No change
// =============================================================================
`include "lm32_include.v"
`ifdef CFG_ICACHE_ENABLED
`define LM32_IC_ADDR_OFFSET_RNG addr_offset_msb:addr_offset_lsb
`define LM32_IC_ADDR_SET_RNG addr_set_msb:addr_set_lsb
`define LM32_IC_ADDR_TAG_RNG addr_tag_msb:addr_tag_lsb
`define LM32_IC_ADDR_IDX_RNG addr_set_msb:addr_offset_lsb
`define LM32_IC_TMEM_ADDR_WIDTH addr_set_width
`define LM32_IC_TMEM_ADDR_RNG (`LM32_IC_TMEM_ADDR_WIDTH-1):0
`define LM32_IC_DMEM_ADDR_WIDTH (addr_offset_width+addr_set_width)
`define LM32_IC_DMEM_ADDR_RNG (`LM32_IC_DMEM_ADDR_WIDTH-1):0
`define LM32_IC_TAGS_WIDTH (addr_tag_width+1)
`define LM32_IC_TAGS_RNG (`LM32_IC_TAGS_WIDTH-1):0
`define LM32_IC_TAGS_TAG_RNG (`LM32_IC_TAGS_WIDTH-1):1
`define LM32_IC_TAGS_VALID_RNG 0
`define LM32_IC_STATE_RNG 3:0
`define LM32_IC_STATE_FLUSH_INIT 4'b0001
`define LM32_IC_STATE_FLUSH 4'b0010
`define LM32_IC_STATE_CHECK 4'b0100
`define LM32_IC_STATE_REFILL 4'b1000
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_icache (
// ----- Inputs -----
clk_i,
rst_i,
stall_a,
stall_f,
address_a,
address_f,
read_enable_f,
refill_ready,
refill_data,
iflush,
`ifdef CFG_IROM_ENABLED
select_f,
`endif
valid_d,
branch_predict_taken_d,
// ----- Outputs -----
stall_request,
restart_request,
refill_request,
refill_address,
refilling,
inst
);
/////////////////////////////////////////////////////
// Parameters
/////////////////////////////////////////////////////
parameter associativity = 1; // Associativity of the cache (Number of ways)
parameter sets = 512; // Number of sets
parameter bytes_per_line = 16; // Number of bytes per cache line
parameter base_address = 0; // Base address of cachable memory
parameter limit = 0; // Limit (highest address) of cachable memory
localparam addr_offset_width = clogb2(bytes_per_line)-1-2;
localparam addr_set_width = clogb2(sets)-1;
localparam addr_offset_lsb = 2;
localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
localparam addr_set_lsb = (addr_offset_msb+1);
localparam addr_set_msb = (addr_set_lsb+addr_set_width-1);
localparam addr_tag_lsb = (addr_set_msb+1);
localparam addr_tag_msb = clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-1;
localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1);
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input clk_i; // Clock
input rst_i; // Reset
input stall_a; // Stall instruction in A stage
input stall_f; // Stall instruction in F stage
input valid_d; // Valid instruction in D stage
input branch_predict_taken_d; // Instruction in D stage is a branch and is predicted taken
input [`LM32_PC_RNG] address_a; // Address of instruction in A stage
input [`LM32_PC_RNG] address_f; // Address of instruction in F stage
input read_enable_f; // Indicates if cache access is valid
input refill_ready; // Next word of refill data is ready
input [`LM32_INSTRUCTION_RNG] refill_data; // Data to refill the cache with
input iflush; // Flush the cache
`ifdef CFG_IROM_ENABLED
input select_f; // Instruction in F stage is mapped through instruction cache
`endif
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
output stall_request; // Request to stall the pipeline
wire stall_request;
output restart_request; // Request to restart instruction that caused the cache miss
reg restart_request;
output refill_request; // Request to refill a cache line
wire refill_request;
output [`LM32_PC_RNG] refill_address; // Base address of cache refill
reg [`LM32_PC_RNG] refill_address;
output refilling; // Indicates the instruction cache is currently refilling
reg refilling;
output [`LM32_INSTRUCTION_RNG] inst; // Instruction read from cache
wire [`LM32_INSTRUCTION_RNG] inst;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
wire enable;
wire [0:associativity-1] way_mem_we;
wire [`LM32_INSTRUCTION_RNG] way_data[0:associativity-1];
wire [`LM32_IC_TAGS_TAG_RNG] way_tag[0:associativity-1];
wire [0:associativity-1] way_valid;
wire [0:associativity-1] way_match;
wire miss;
wire [`LM32_IC_TMEM_ADDR_RNG] tmem_read_address;
wire [`LM32_IC_TMEM_ADDR_RNG] tmem_write_address;
wire [`LM32_IC_DMEM_ADDR_RNG] dmem_read_address;
wire [`LM32_IC_DMEM_ADDR_RNG] dmem_write_address;
wire [`LM32_IC_TAGS_RNG] tmem_write_data;
reg [`LM32_IC_STATE_RNG] state;
wire flushing;
wire check;
wire refill;
reg [associativity-1:0] refill_way_select;
reg [`LM32_IC_ADDR_OFFSET_RNG] refill_offset;
wire last_refill;
reg [`LM32_IC_TMEM_ADDR_RNG] flush_set;
genvar i;
/////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////
`include "lm32_functions.v"
/////////////////////////////////////////////////////
// Instantiations
/////////////////////////////////////////////////////
generate
for (i = 0; i < associativity; i = i + 1)
begin : memories
lm32_ram
#(
// ----- Parameters -------
.data_width (32),
.address_width (`LM32_IC_DMEM_ADDR_WIDTH)
// Modified for Milkymist: removed non-portable RAM parameters
)
way_0_data_ram
(
// ----- Inputs -------
.read_clk (clk_i),
.write_clk (clk_i),
.reset (rst_i),
.read_address (dmem_read_address),
.enable_read (enable),
.write_address (dmem_write_address),
.enable_write (`TRUE),
.write_enable (way_mem_we[i]),
.write_data (refill_data),
// ----- Outputs -------
.read_data (way_data[i])
);
lm32_ram
#(
// ----- Parameters -------
.data_width (`LM32_IC_TAGS_WIDTH),
.address_width (`LM32_IC_TMEM_ADDR_WIDTH)
// Modified for Milkymist: removed non-portable RAM parameters
)
way_0_tag_ram
(
// ----- Inputs -------
.read_clk (clk_i),
.write_clk (clk_i),
.reset (rst_i),
.read_address (tmem_read_address),
.enable_read (enable),
.write_address (tmem_write_address),
.enable_write (`TRUE),
.write_enable (way_mem_we[i] | flushing),
.write_data (tmem_write_data),
// ----- Outputs -------
.read_data ({way_tag[i], way_valid[i]})
);
end
endgenerate
/////////////////////////////////////////////////////
// Combinational logic
/////////////////////////////////////////////////////
// Compute which ways in the cache match the address address being read
generate
for (i = 0; i < associativity; i = i + 1)
begin : match
assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_f[`LM32_IC_ADDR_TAG_RNG], `TRUE});
end
endgenerate
// Select data from way that matched the address being read
generate
if (associativity == 1)
begin : inst_1
assign inst = way_match[0] ? way_data[0] : 32'b0;
end
else if (associativity == 2)
begin : inst_2
assign inst = way_match[0] ? way_data[0] : (way_match[1] ? way_data[1] : 32'b0);
end
endgenerate
// Compute address to use to index into the data memories
generate
if (bytes_per_line > 4)
assign dmem_write_address = {refill_address[`LM32_IC_ADDR_SET_RNG], refill_offset};
else
assign dmem_write_address = refill_address[`LM32_IC_ADDR_SET_RNG];
endgenerate
assign dmem_read_address = address_a[`LM32_IC_ADDR_IDX_RNG];
// Compute address to use to index into the tag memories
assign tmem_read_address = address_a[`LM32_IC_ADDR_SET_RNG];
assign tmem_write_address = flushing
? flush_set
: refill_address[`LM32_IC_ADDR_SET_RNG];
// Compute signal to indicate when we are on the last refill accesses
generate
if (bytes_per_line > 4)
assign last_refill = refill_offset == {addr_offset_width{1'b1}};
else
assign last_refill = `TRUE;
endgenerate
// Compute data and tag memory access enable
assign enable = (stall_a == `FALSE);
// Compute data and tag memory write enables
generate
if (associativity == 1)
begin : we_1
assign way_mem_we[0] = (refill_ready == `TRUE);
end
else
begin : we_2
assign way_mem_we[0] = (refill_ready == `TRUE) && (refill_way_select[0] == `TRUE);
assign way_mem_we[1] = (refill_ready == `TRUE) && (refill_way_select[1] == `TRUE);
end
endgenerate
// On the last refill cycle set the valid bit, for all other writes it should be cleared
assign tmem_write_data[`LM32_IC_TAGS_VALID_RNG] = last_refill & !flushing;
assign tmem_write_data[`LM32_IC_TAGS_TAG_RNG] = refill_address[`LM32_IC_ADDR_TAG_RNG];
// Signals that indicate which state we are in
assign flushing = |state[1:0];
assign check = state[2];
assign refill = state[3];
assign miss = (~(|way_match)) && (read_enable_f == `TRUE) && (stall_f == `FALSE) && !(valid_d && branch_predict_taken_d);
assign stall_request = (check == `FALSE);
assign refill_request = (refill == `TRUE);
/////////////////////////////////////////////////////
// Sequential logic
/////////////////////////////////////////////////////
// Record way selected for replacement on a cache miss
generate
if (associativity >= 2)
begin : way_select
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
else
begin
if (miss == `TRUE)
refill_way_select <= {refill_way_select[0], refill_way_select[1]};
end
end
end
endgenerate
// Record whether we are refilling
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
refilling <= `FALSE;
else
refilling <= refill;
end
// Instruction cache control FSM
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
state <= `LM32_IC_STATE_FLUSH_INIT;
flush_set <= {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}};
refill_address <= {`LM32_PC_WIDTH{1'bx}};
restart_request <= `FALSE;
end
else
begin
case (state)
// Flush the cache for the first time after reset
`LM32_IC_STATE_FLUSH_INIT:
begin
if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}})
state <= `LM32_IC_STATE_CHECK;
flush_set <= flush_set - 1'b1;
end
// Flush the cache in response to an write to the ICC CSR
`LM32_IC_STATE_FLUSH:
begin
if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}})
`ifdef CFG_IROM_ENABLED
if (select_f)
state <= `LM32_IC_STATE_REFILL;
else
`endif
state <= `LM32_IC_STATE_CHECK;
flush_set <= flush_set - 1'b1;
end
// Check for cache misses
`LM32_IC_STATE_CHECK:
begin
if (stall_a == `FALSE)
restart_request <= `FALSE;
if (iflush == `TRUE)
begin
refill_address <= address_f;
state <= `LM32_IC_STATE_FLUSH;
end
else if (miss == `TRUE)
begin
refill_address <= address_f;
state <= `LM32_IC_STATE_REFILL;
end
end
// Refill a cache line
`LM32_IC_STATE_REFILL:
begin
if (refill_ready == `TRUE)
begin
if (last_refill == `TRUE)
begin
restart_request <= `TRUE;
state <= `LM32_IC_STATE_CHECK;
end
end
end
endcase
end
end
generate
if (bytes_per_line > 4)
begin
// Refill offset
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
refill_offset <= {addr_offset_width{1'b0}};
else
begin
case (state)
// Check for cache misses
`LM32_IC_STATE_CHECK:
begin
if (iflush == `TRUE)
refill_offset <= {addr_offset_width{1'b0}};
else if (miss == `TRUE)
refill_offset <= {addr_offset_width{1'b0}};
end
// Refill a cache line
`LM32_IC_STATE_REFILL:
begin
if (refill_ready == `TRUE)
refill_offset <= refill_offset + 1'b1;
end
endcase
end
end
end
endgenerate
endmodule
`endif
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_ddr_rptr_c.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_ddr_rptr_c(out21 ,out20 ,out19 ,out18 ,out17 ,out16 ,out15
,out14 ,out13 ,out12 ,out10 ,out9 ,out8 ,out6 ,out5 ,out4 ,out3 ,
out2 ,in21 ,in20 ,in19 ,in18 ,in17 ,in16 ,in15 ,in14 ,in13 ,in12 ,
out1 ,out0 ,in10 ,in22 ,out22 ,in24 ,out24 ,out25 ,vdd18 ,in25 ,in2
,in5 ,in1 ,in4 ,in9 ,out11 ,in3 ,in11 ,in0 ,in6 ,in8 );
output [8:1] out14 ;
output [8:1] out13 ;
output [1:0] out10 ;
output [1:0] out9 ;
output [1:0] out4 ;
output [4:0] out1 ;
output [7:0] out25 ;
input [8:1] in14 ;
input [8:1] in13 ;
input [1:0] in10 ;
input [7:0] in25 ;
input [4:0] in1 ;
input [1:0] in4 ;
input [1:0] in9 ;
output out21 ;
output out20 ;
output out19 ;
output out18 ;
output out17 ;
output out16 ;
output out15 ;
output out12 ;
output out8 ;
output out6 ;
output out5 ;
output out3 ;
output out2 ;
output out0 ;
output out22 ;
output out24 ;
output out11 ;
input in21 ;
input in20 ;
input in19 ;
input in18 ;
input in17 ;
input in16 ;
input in15 ;
input in12 ;
input in22 ;
input in24 ;
input vdd18 ;
input in2 ;
input in5 ;
input in3 ;
input in11 ;
input in0 ;
input in6 ;
input in8 ;
bw_u1_buf_30x I10_1_ (
.z (out9[1] ),
.a (in9[1] ) );
bw_u1_buf_30x I0 (
.z (out2 ),
.a (in2 ) );
bw_u1_buf_30x I1 (
.z (out3 ),
.a (in3 ) );
bw_u1_buf_30x I65_2_ (
.z (out1[2] ),
.a (in1[2] ) );
bw_u1_buf_30x I4 (
.z (out6 ),
.a (in6 ) );
bw_u1_buf_30x I5 (
.z (out5 ),
.a (in5 ) );
bw_u1_buf_30x I34_1_ (
.z (out13[1] ),
.a (in13[1] ) );
bw_u1_buf_30x I6 (
.z (out11 ),
.a (in11 ) );
bw_u1_buf_30x I35_7_ (
.z (out14[7] ),
.a (in14[7] ) );
bw_u1_buf_30x I7 (
.z (out12 ),
.a (in12 ) );
bw_u1_buf_30x I66 (
.z (out0 ),
.a (in0 ) );
bw_u1_buf_30x I65_3_ (
.z (out1[3] ),
.a (in1[3] ) );
bw_u1_buf_30x I34_2_ (
.z (out13[2] ),
.a (in13[2] ) );
bw_u1_buf_30x I35_8_ (
.z (out14[8] ),
.a (in14[8] ) );
bw_u1_buf_30x I65_4_ (
.z (out1[4] ),
.a (in1[4] ) );
bw_u1_buf_30x I34_3_ (
.z (out13[3] ),
.a (in13[3] ) );
bw_u1_buf_30x I35_1_ (
.z (out14[1] ),
.a (in14[1] ) );
bw_u1_buf_30x I9_0_ (
.z (out10[0] ),
.a (in10[0] ) );
bw_u1_buf_30x I11 (
.z (out8 ),
.a (in8 ) );
bw_u1_buf_30x I34_4_ (
.z (out13[4] ),
.a (in13[4] ) );
bw_u1_buf_30x I35_2_ (
.z (out14[2] ),
.a (in14[2] ) );
bw_u1_buf_30x I9_1_ (
.z (out10[1] ),
.a (in10[1] ) );
bw_u1_buf_30x I34_5_ (
.z (out13[5] ),
.a (in13[5] ) );
bw_u1_buf_30x I35_3_ (
.z (out14[3] ),
.a (in14[3] ) );
bw_u1_buf_30x I2_0_ (
.z (out4[0] ),
.a (in4[0] ) );
bw_u1_buf_30x I102 (
.z (out22 ),
.a (in22 ) );
bw_u1_buf_30x I34_6_ (
.z (out13[6] ),
.a (in13[6] ) );
bw_u1_buf_30x I35_4_ (
.z (out14[4] ),
.a (in14[4] ) );
bw_u1_buf_30x I36 (
.z (out15 ),
.a (in15 ) );
bw_u1_buf_30x I37 (
.z (out16 ),
.a (in16 ) );
bw_u1_buf_30x I38 (
.z (out17 ),
.a (in17 ) );
bw_u1_buf_30x I39 (
.z (out19 ),
.a (in19 ) );
bw_u1_buf_30x I110 (
.z (out24 ),
.a (in24 ) );
bw_u1_buf_30x I65_0_ (
.z (out1[0] ),
.a (in1[0] ) );
bw_u1_buf_30x I2_1_ (
.z (out4[1] ),
.a (in4[1] ) );
bw_u1_buf_30x I40 (
.z (out18 ),
.a (in18 ) );
bw_u1_buf_30x I41 (
.z (out20 ),
.a (in20 ) );
bw_u1_buf_30x I42 (
.z (out21 ),
.a (in21 ) );
bw_io_ddr_vref_rptr I115 (
.out ({out25 } ),
.in ({in25 } ),
.vdd18 (vdd18 ) );
bw_u1_buf_30x I34_7_ (
.z (out13[7] ),
.a (in13[7] ) );
bw_u1_buf_30x I35_5_ (
.z (out14[5] ),
.a (in14[5] ) );
bw_u1_buf_30x I10_0_ (
.z (out9[0] ),
.a (in9[0] ) );
bw_u1_buf_30x I65_1_ (
.z (out1[1] ),
.a (in1[1] ) );
bw_u1_buf_30x I34_8_ (
.z (out13[8] ),
.a (in13[8] ) );
bw_u1_buf_30x I35_6_ (
.z (out14[6] ),
.a (in14[6] ) );
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAPVPWRVGND_SYMBOL_V
`define SKY130_FD_SC_HD__TAPVPWRVGND_SYMBOL_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__tapvpwrvgnd ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAPVPWRVGND_SYMBOL_V
|
/*
* Copyright 2018-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module progmem
(
// Closk & reset
input wire clk,
input wire rstn,
// PicoRV32 bus interface
input wire valid,
output wire ready,
input wire [31:0] addr,
output wire [31:0] rdata
);
// ============================================================================
localparam MEM_SIZE_BITS = 10; // In 32-bit words
localparam MEM_SIZE = 1 << MEM_SIZE_BITS;
localparam MEM_ADDR_MASK = 32'h0010_0000;
// ============================================================================
wire [MEM_SIZE_BITS-1:0] mem_addr;
reg [31:0] mem_data;
reg [31:0] mem[0:MEM_SIZE];
initial begin
mem['h0000] <= 32'h00000093;
mem['h0001] <= 32'h00000193;
mem['h0002] <= 32'h00000213;
mem['h0003] <= 32'h00000293;
mem['h0004] <= 32'h00000313;
mem['h0005] <= 32'h00000393;
mem['h0006] <= 32'h00000413;
mem['h0007] <= 32'h00000493;
mem['h0008] <= 32'h00000513;
mem['h0009] <= 32'h00000593;
mem['h000A] <= 32'h00000613;
mem['h000B] <= 32'h00000693;
mem['h000C] <= 32'h00000713;
mem['h000D] <= 32'h00000793;
mem['h000E] <= 32'h00000813;
mem['h000F] <= 32'h00000893;
mem['h0010] <= 32'h00000913;
mem['h0011] <= 32'h00000993;
mem['h0012] <= 32'h00000A13;
mem['h0013] <= 32'h00000A93;
mem['h0014] <= 32'h00000B13;
mem['h0015] <= 32'h00000B93;
mem['h0016] <= 32'h00000C13;
mem['h0017] <= 32'h00000C93;
mem['h0018] <= 32'h00000D13;
mem['h0019] <= 32'h00000D93;
mem['h001A] <= 32'h00000E13;
mem['h001B] <= 32'h00000E93;
mem['h001C] <= 32'h00000F13;
mem['h001D] <= 32'h00000F93;
mem['h001E] <= 32'h03000537;
mem['h001F] <= 32'h00100593;
mem['h0020] <= 32'h00B52023;
mem['h0021] <= 32'h00000513;
mem['h0022] <= 32'h00A52023;
mem['h0023] <= 32'h00450513;
mem['h0024] <= 32'hFE254CE3;
mem['h0025] <= 32'h03000537;
mem['h0026] <= 32'h00300593;
mem['h0027] <= 32'h00B52023;
mem['h0028] <= 32'h00001517;
mem['h0029] <= 32'hB4050513;
mem['h002A] <= 32'h00000593;
mem['h002B] <= 32'h00000613;
mem['h002C] <= 32'h00C5DC63;
mem['h002D] <= 32'h00052683;
mem['h002E] <= 32'h00D5A023;
mem['h002F] <= 32'h00450513;
mem['h0030] <= 32'h00458593;
mem['h0031] <= 32'hFEC5C8E3;
mem['h0032] <= 32'h03000537;
mem['h0033] <= 32'h00700593;
mem['h0034] <= 32'h00B52023;
mem['h0035] <= 32'h00000513;
mem['h0036] <= 32'h00000593;
mem['h0037] <= 32'h00B55863;
mem['h0038] <= 32'h00052023;
mem['h0039] <= 32'h00450513;
mem['h003A] <= 32'hFEB54CE3;
mem['h003B] <= 32'h03000537;
mem['h003C] <= 32'h00F00593;
mem['h003D] <= 32'h00B52023;
mem['h003E] <= 32'h015000EF;
mem['h003F] <= 32'h0000006F;
mem['h0040] <= 32'h020002B7;
mem['h0041] <= 32'h12000313;
mem['h0042] <= 32'h00629023;
mem['h0043] <= 32'h000281A3;
mem['h0044] <= 32'h02060863;
mem['h0045] <= 32'h00800F13;
mem['h0046] <= 32'h0FF67393;
mem['h0047] <= 32'h0073DE93;
mem['h0048] <= 32'h01D28023;
mem['h0049] <= 32'h010EEE93;
mem['h004A] <= 32'h01D28023;
mem['h004B] <= 32'h00139393;
mem['h004C] <= 32'h0FF3F393;
mem['h004D] <= 32'hFFFF0F13;
mem['h004E] <= 32'hFE0F12E3;
mem['h004F] <= 32'h00628023;
mem['h0050] <= 32'h04058663;
mem['h0051] <= 32'h00800F13;
mem['h0052] <= 32'h00054383;
mem['h0053] <= 32'h0073DE93;
mem['h0054] <= 32'h01D28023;
mem['h0055] <= 32'h010EEE93;
mem['h0056] <= 32'h01D28023;
mem['h0057] <= 32'h0002CE83;
mem['h0058] <= 32'h002EFE93;
mem['h0059] <= 32'h001EDE93;
mem['h005A] <= 32'h00139393;
mem['h005B] <= 32'h01D3E3B3;
mem['h005C] <= 32'h0FF3F393;
mem['h005D] <= 32'hFFFF0F13;
mem['h005E] <= 32'hFC0F1AE3;
mem['h005F] <= 32'h00750023;
mem['h0060] <= 32'h00150513;
mem['h0061] <= 32'hFFF58593;
mem['h0062] <= 32'hFB9FF06F;
mem['h0063] <= 32'h08000313;
mem['h0064] <= 32'h006281A3;
mem['h0065] <= 32'h00008067;
mem['h0066] <= 32'hFE010113;
mem['h0067] <= 32'h00112E23;
mem['h0068] <= 32'h00812C23;
mem['h0069] <= 32'h02010413;
mem['h006A] <= 32'h00050793;
mem['h006B] <= 32'hFEF407A3;
mem['h006C] <= 32'hFEF44703;
mem['h006D] <= 32'h00A00793;
mem['h006E] <= 32'h00F71663;
mem['h006F] <= 32'h00D00513;
mem['h0070] <= 32'hFD9FF0EF;
mem['h0071] <= 32'h020007B7;
mem['h0072] <= 32'h00878793;
mem['h0073] <= 32'hFEF44703;
mem['h0074] <= 32'h00E7A023;
mem['h0075] <= 32'h00000013;
mem['h0076] <= 32'h01C12083;
mem['h0077] <= 32'h01812403;
mem['h0078] <= 32'h02010113;
mem['h0079] <= 32'h00008067;
mem['h007A] <= 32'hFE010113;
mem['h007B] <= 32'h00112E23;
mem['h007C] <= 32'h00812C23;
mem['h007D] <= 32'h02010413;
mem['h007E] <= 32'hFEA42623;
mem['h007F] <= 32'h01C0006F;
mem['h0080] <= 32'hFEC42783;
mem['h0081] <= 32'h00178713;
mem['h0082] <= 32'hFEE42623;
mem['h0083] <= 32'h0007C783;
mem['h0084] <= 32'h00078513;
mem['h0085] <= 32'hF85FF0EF;
mem['h0086] <= 32'hFEC42783;
mem['h0087] <= 32'h0007C783;
mem['h0088] <= 32'hFE0790E3;
mem['h0089] <= 32'h00000013;
mem['h008A] <= 32'h01C12083;
mem['h008B] <= 32'h01812403;
mem['h008C] <= 32'h02010113;
mem['h008D] <= 32'h00008067;
mem['h008E] <= 32'hFD010113;
mem['h008F] <= 32'h02112623;
mem['h0090] <= 32'h02812423;
mem['h0091] <= 32'h03010413;
mem['h0092] <= 32'hFCA42E23;
mem['h0093] <= 32'hFCB42C23;
mem['h0094] <= 32'h00700793;
mem['h0095] <= 32'hFEF42623;
mem['h0096] <= 32'h06C0006F;
mem['h0097] <= 32'hFEC42783;
mem['h0098] <= 32'h00279793;
mem['h0099] <= 32'hFDC42703;
mem['h009A] <= 32'h00F757B3;
mem['h009B] <= 32'h00F7F713;
mem['h009C] <= 32'h001017B7;
mem['h009D] <= 32'hA8078793;
mem['h009E] <= 32'h00F707B3;
mem['h009F] <= 32'h0007C783;
mem['h00A0] <= 32'hFEF405A3;
mem['h00A1] <= 32'hFEB44703;
mem['h00A2] <= 32'h03000793;
mem['h00A3] <= 32'h00F71863;
mem['h00A4] <= 32'hFEC42703;
mem['h00A5] <= 32'hFD842783;
mem['h00A6] <= 32'h00F75E63;
mem['h00A7] <= 32'hFEB44783;
mem['h00A8] <= 32'h00078513;
mem['h00A9] <= 32'hEF5FF0EF;
mem['h00AA] <= 32'hFEC42783;
mem['h00AB] <= 32'hFCF42C23;
mem['h00AC] <= 32'h0080006F;
mem['h00AD] <= 32'h00000013;
mem['h00AE] <= 32'hFEC42783;
mem['h00AF] <= 32'hFFF78793;
mem['h00B0] <= 32'hFEF42623;
mem['h00B1] <= 32'hFEC42783;
mem['h00B2] <= 32'hF807DAE3;
mem['h00B3] <= 32'h00000013;
mem['h00B4] <= 32'h02C12083;
mem['h00B5] <= 32'h02812403;
mem['h00B6] <= 32'h03010113;
mem['h00B7] <= 32'h00008067;
mem['h00B8] <= 32'hFE010113;
mem['h00B9] <= 32'h00112E23;
mem['h00BA] <= 32'h00812C23;
mem['h00BB] <= 32'h02010413;
mem['h00BC] <= 32'hFEA42623;
mem['h00BD] <= 32'hFEC42703;
mem['h00BE] <= 32'h06300793;
mem['h00BF] <= 32'h00E7FA63;
mem['h00C0] <= 32'h001017B7;
mem['h00C1] <= 32'hA9478513;
mem['h00C2] <= 32'hEE1FF0EF;
mem['h00C3] <= 32'h28C0006F;
mem['h00C4] <= 32'hFEC42703;
mem['h00C5] <= 32'h05900793;
mem['h00C6] <= 32'h00E7FE63;
mem['h00C7] <= 32'h03900513;
mem['h00C8] <= 32'hE79FF0EF;
mem['h00C9] <= 32'hFEC42783;
mem['h00CA] <= 32'hFA678793;
mem['h00CB] <= 32'hFEF42623;
mem['h00CC] <= 32'h1200006F;
mem['h00CD] <= 32'hFEC42703;
mem['h00CE] <= 32'h04F00793;
mem['h00CF] <= 32'h00E7FE63;
mem['h00D0] <= 32'h03800513;
mem['h00D1] <= 32'hE55FF0EF;
mem['h00D2] <= 32'hFEC42783;
mem['h00D3] <= 32'hFB078793;
mem['h00D4] <= 32'hFEF42623;
mem['h00D5] <= 32'h0FC0006F;
mem['h00D6] <= 32'hFEC42703;
mem['h00D7] <= 32'h04500793;
mem['h00D8] <= 32'h00E7FE63;
mem['h00D9] <= 32'h03700513;
mem['h00DA] <= 32'hE31FF0EF;
mem['h00DB] <= 32'hFEC42783;
mem['h00DC] <= 32'hFBA78793;
mem['h00DD] <= 32'hFEF42623;
mem['h00DE] <= 32'h0D80006F;
mem['h00DF] <= 32'hFEC42703;
mem['h00E0] <= 32'h03B00793;
mem['h00E1] <= 32'h00E7FE63;
mem['h00E2] <= 32'h03600513;
mem['h00E3] <= 32'hE0DFF0EF;
mem['h00E4] <= 32'hFEC42783;
mem['h00E5] <= 32'hFC478793;
mem['h00E6] <= 32'hFEF42623;
mem['h00E7] <= 32'h0B40006F;
mem['h00E8] <= 32'hFEC42703;
mem['h00E9] <= 32'h03100793;
mem['h00EA] <= 32'h00E7FE63;
mem['h00EB] <= 32'h03500513;
mem['h00EC] <= 32'hDE9FF0EF;
mem['h00ED] <= 32'hFEC42783;
mem['h00EE] <= 32'hFCE78793;
mem['h00EF] <= 32'hFEF42623;
mem['h00F0] <= 32'h0900006F;
mem['h00F1] <= 32'hFEC42703;
mem['h00F2] <= 32'h02700793;
mem['h00F3] <= 32'h00E7FE63;
mem['h00F4] <= 32'h03400513;
mem['h00F5] <= 32'hDC5FF0EF;
mem['h00F6] <= 32'hFEC42783;
mem['h00F7] <= 32'hFD878793;
mem['h00F8] <= 32'hFEF42623;
mem['h00F9] <= 32'h06C0006F;
mem['h00FA] <= 32'hFEC42703;
mem['h00FB] <= 32'h01D00793;
mem['h00FC] <= 32'h00E7FE63;
mem['h00FD] <= 32'h03300513;
mem['h00FE] <= 32'hDA1FF0EF;
mem['h00FF] <= 32'hFEC42783;
mem['h0100] <= 32'hFE278793;
mem['h0101] <= 32'hFEF42623;
mem['h0102] <= 32'h0480006F;
mem['h0103] <= 32'hFEC42703;
mem['h0104] <= 32'h01300793;
mem['h0105] <= 32'h00E7FE63;
mem['h0106] <= 32'h03200513;
mem['h0107] <= 32'hD7DFF0EF;
mem['h0108] <= 32'hFEC42783;
mem['h0109] <= 32'hFEC78793;
mem['h010A] <= 32'hFEF42623;
mem['h010B] <= 32'h0240006F;
mem['h010C] <= 32'hFEC42703;
mem['h010D] <= 32'h00900793;
mem['h010E] <= 32'h00E7FC63;
mem['h010F] <= 32'h03100513;
mem['h0110] <= 32'hD59FF0EF;
mem['h0111] <= 32'hFEC42783;
mem['h0112] <= 32'hFF678793;
mem['h0113] <= 32'hFEF42623;
mem['h0114] <= 32'hFEC42703;
mem['h0115] <= 32'h00800793;
mem['h0116] <= 32'h00E7FE63;
mem['h0117] <= 32'h03900513;
mem['h0118] <= 32'hD39FF0EF;
mem['h0119] <= 32'hFEC42783;
mem['h011A] <= 32'hFF778793;
mem['h011B] <= 32'hFEF42623;
mem['h011C] <= 32'h1280006F;
mem['h011D] <= 32'hFEC42703;
mem['h011E] <= 32'h00700793;
mem['h011F] <= 32'h00E7FE63;
mem['h0120] <= 32'h03800513;
mem['h0121] <= 32'hD15FF0EF;
mem['h0122] <= 32'hFEC42783;
mem['h0123] <= 32'hFF878793;
mem['h0124] <= 32'hFEF42623;
mem['h0125] <= 32'h1040006F;
mem['h0126] <= 32'hFEC42703;
mem['h0127] <= 32'h00600793;
mem['h0128] <= 32'h00E7FE63;
mem['h0129] <= 32'h03700513;
mem['h012A] <= 32'hCF1FF0EF;
mem['h012B] <= 32'hFEC42783;
mem['h012C] <= 32'hFF978793;
mem['h012D] <= 32'hFEF42623;
mem['h012E] <= 32'h0E00006F;
mem['h012F] <= 32'hFEC42703;
mem['h0130] <= 32'h00500793;
mem['h0131] <= 32'h00E7FE63;
mem['h0132] <= 32'h03600513;
mem['h0133] <= 32'hCCDFF0EF;
mem['h0134] <= 32'hFEC42783;
mem['h0135] <= 32'hFFA78793;
mem['h0136] <= 32'hFEF42623;
mem['h0137] <= 32'h0BC0006F;
mem['h0138] <= 32'hFEC42703;
mem['h0139] <= 32'h00400793;
mem['h013A] <= 32'h00E7FE63;
mem['h013B] <= 32'h03500513;
mem['h013C] <= 32'hCA9FF0EF;
mem['h013D] <= 32'hFEC42783;
mem['h013E] <= 32'hFFB78793;
mem['h013F] <= 32'hFEF42623;
mem['h0140] <= 32'h0980006F;
mem['h0141] <= 32'hFEC42703;
mem['h0142] <= 32'h00300793;
mem['h0143] <= 32'h00E7FE63;
mem['h0144] <= 32'h03400513;
mem['h0145] <= 32'hC85FF0EF;
mem['h0146] <= 32'hFEC42783;
mem['h0147] <= 32'hFFC78793;
mem['h0148] <= 32'hFEF42623;
mem['h0149] <= 32'h0740006F;
mem['h014A] <= 32'hFEC42703;
mem['h014B] <= 32'h00200793;
mem['h014C] <= 32'h00E7FE63;
mem['h014D] <= 32'h03300513;
mem['h014E] <= 32'hC61FF0EF;
mem['h014F] <= 32'hFEC42783;
mem['h0150] <= 32'hFFD78793;
mem['h0151] <= 32'hFEF42623;
mem['h0152] <= 32'h0500006F;
mem['h0153] <= 32'hFEC42703;
mem['h0154] <= 32'h00100793;
mem['h0155] <= 32'h00E7FE63;
mem['h0156] <= 32'h03200513;
mem['h0157] <= 32'hC3DFF0EF;
mem['h0158] <= 32'hFEC42783;
mem['h0159] <= 32'hFFE78793;
mem['h015A] <= 32'hFEF42623;
mem['h015B] <= 32'h02C0006F;
mem['h015C] <= 32'hFEC42783;
mem['h015D] <= 32'h00078E63;
mem['h015E] <= 32'h03100513;
mem['h015F] <= 32'hC1DFF0EF;
mem['h0160] <= 32'hFEC42783;
mem['h0161] <= 32'hFFF78793;
mem['h0162] <= 32'hFEF42623;
mem['h0163] <= 32'h00C0006F;
mem['h0164] <= 32'h03000513;
mem['h0165] <= 32'hC05FF0EF;
mem['h0166] <= 32'h01C12083;
mem['h0167] <= 32'h01812403;
mem['h0168] <= 32'h02010113;
mem['h0169] <= 32'h00008067;
mem['h016A] <= 32'hFD010113;
mem['h016B] <= 32'h02112623;
mem['h016C] <= 32'h02812423;
mem['h016D] <= 32'h03010413;
mem['h016E] <= 32'hFCA42E23;
mem['h016F] <= 32'hFFF00793;
mem['h0170] <= 32'hFEF42623;
mem['h0171] <= 32'hC00027F3;
mem['h0172] <= 32'hFEF42423;
mem['h0173] <= 32'h030007B7;
mem['h0174] <= 32'hFFF00713;
mem['h0175] <= 32'h00E7A023;
mem['h0176] <= 32'hFDC42783;
mem['h0177] <= 32'h08078A63;
mem['h0178] <= 32'hFDC42503;
mem['h0179] <= 32'hC05FF0EF;
mem['h017A] <= 32'h0880006F;
mem['h017B] <= 32'hC00027F3;
mem['h017C] <= 32'hFEF42223;
mem['h017D] <= 32'hFE442703;
mem['h017E] <= 32'hFE842783;
mem['h017F] <= 32'h40F707B3;
mem['h0180] <= 32'hFEF42023;
mem['h0181] <= 32'hFE042703;
mem['h0182] <= 32'h00B727B7;
mem['h0183] <= 32'hB0078793;
mem['h0184] <= 32'h04E7F863;
mem['h0185] <= 32'hFDC42783;
mem['h0186] <= 32'h00078663;
mem['h0187] <= 32'hFDC42503;
mem['h0188] <= 32'hBC9FF0EF;
mem['h0189] <= 32'hFE442783;
mem['h018A] <= 32'hFEF42423;
mem['h018B] <= 32'h030007B7;
mem['h018C] <= 32'h0007A783;
mem['h018D] <= 32'h00179713;
mem['h018E] <= 32'h030007B7;
mem['h018F] <= 32'h0007A783;
mem['h0190] <= 32'h0017D793;
mem['h0191] <= 32'h0017F793;
mem['h0192] <= 32'h0017B793;
mem['h0193] <= 32'h0FF7F793;
mem['h0194] <= 32'h00078693;
mem['h0195] <= 32'h030007B7;
mem['h0196] <= 32'h00D76733;
mem['h0197] <= 32'h00E7A023;
mem['h0198] <= 32'h020007B7;
mem['h0199] <= 32'h00878793;
mem['h019A] <= 32'h0007A783;
mem['h019B] <= 32'hFEF42623;
mem['h019C] <= 32'hFEC42703;
mem['h019D] <= 32'hFFF00793;
mem['h019E] <= 32'hF6F70AE3;
mem['h019F] <= 32'h030007B7;
mem['h01A0] <= 32'h0007A023;
mem['h01A1] <= 32'hFEC42783;
mem['h01A2] <= 32'h0FF7F793;
mem['h01A3] <= 32'h00078513;
mem['h01A4] <= 32'h02C12083;
mem['h01A5] <= 32'h02812403;
mem['h01A6] <= 32'h03010113;
mem['h01A7] <= 32'h00008067;
mem['h01A8] <= 32'hFF010113;
mem['h01A9] <= 32'h00112623;
mem['h01AA] <= 32'h00812423;
mem['h01AB] <= 32'h01010413;
mem['h01AC] <= 32'h00000513;
mem['h01AD] <= 32'hEF5FF0EF;
mem['h01AE] <= 32'h00050793;
mem['h01AF] <= 32'h00078513;
mem['h01B0] <= 32'h00C12083;
mem['h01B1] <= 32'h00812403;
mem['h01B2] <= 32'h01010113;
mem['h01B3] <= 32'h00008067;
mem['h01B4] <= 32'hEB010113;
mem['h01B5] <= 32'h14112623;
mem['h01B6] <= 32'h14812423;
mem['h01B7] <= 32'h15010413;
mem['h01B8] <= 32'h00050793;
mem['h01B9] <= 32'hEAB42C23;
mem['h01BA] <= 32'hEAF40FA3;
mem['h01BB] <= 32'hEC040793;
mem['h01BC] <= 32'hFCF42A23;
mem['h01BD] <= 32'h12B9B7B7;
mem['h01BE] <= 32'h0A178793;
mem['h01BF] <= 32'hFEF42623;
mem['h01C0] <= 32'hC00027F3;
mem['h01C1] <= 32'hFCF42823;
mem['h01C2] <= 32'hC02027F3;
mem['h01C3] <= 32'hFCF42623;
mem['h01C4] <= 32'hFE042423;
mem['h01C5] <= 32'h1200006F;
mem['h01C6] <= 32'hFE042223;
mem['h01C7] <= 32'h0640006F;
mem['h01C8] <= 32'hFEC42783;
mem['h01C9] <= 32'h00D79793;
mem['h01CA] <= 32'hFEC42703;
mem['h01CB] <= 32'h00F747B3;
mem['h01CC] <= 32'hFEF42623;
mem['h01CD] <= 32'hFEC42783;
mem['h01CE] <= 32'h0117D793;
mem['h01CF] <= 32'hFEC42703;
mem['h01D0] <= 32'h00F747B3;
mem['h01D1] <= 32'hFEF42623;
mem['h01D2] <= 32'hFEC42783;
mem['h01D3] <= 32'h00579793;
mem['h01D4] <= 32'hFEC42703;
mem['h01D5] <= 32'h00F747B3;
mem['h01D6] <= 32'hFEF42623;
mem['h01D7] <= 32'hFEC42783;
mem['h01D8] <= 32'h0FF7F713;
mem['h01D9] <= 32'hFE442783;
mem['h01DA] <= 32'hFF040693;
mem['h01DB] <= 32'h00F687B3;
mem['h01DC] <= 32'hECE78823;
mem['h01DD] <= 32'hFE442783;
mem['h01DE] <= 32'h00178793;
mem['h01DF] <= 32'hFEF42223;
mem['h01E0] <= 32'hFE442703;
mem['h01E1] <= 32'h0FF00793;
mem['h01E2] <= 32'hF8E7DCE3;
mem['h01E3] <= 32'hFE042023;
mem['h01E4] <= 32'hFC042E23;
mem['h01E5] <= 32'h0440006F;
mem['h01E6] <= 32'hFE042783;
mem['h01E7] <= 32'hFF040713;
mem['h01E8] <= 32'h00F707B3;
mem['h01E9] <= 32'hED07C783;
mem['h01EA] <= 32'h02078263;
mem['h01EB] <= 32'hFDC42783;
mem['h01EC] <= 32'h00178713;
mem['h01ED] <= 32'hFCE42E23;
mem['h01EE] <= 32'hFE042703;
mem['h01EF] <= 32'h0FF77713;
mem['h01F0] <= 32'hFF040693;
mem['h01F1] <= 32'h00F687B3;
mem['h01F2] <= 32'hECE78823;
mem['h01F3] <= 32'hFE042783;
mem['h01F4] <= 32'h00178793;
mem['h01F5] <= 32'hFEF42023;
mem['h01F6] <= 32'hFE042703;
mem['h01F7] <= 32'h0FF00793;
mem['h01F8] <= 32'hFAE7DCE3;
mem['h01F9] <= 32'hFC042C23;
mem['h01FA] <= 32'hFC042023;
mem['h01FB] <= 32'h0300006F;
mem['h01FC] <= 32'hFD842783;
mem['h01FD] <= 32'h00279793;
mem['h01FE] <= 32'hFD442703;
mem['h01FF] <= 32'h00F707B3;
mem['h0200] <= 32'h0007A783;
mem['h0201] <= 32'hFEC42703;
mem['h0202] <= 32'h00F747B3;
mem['h0203] <= 32'hFEF42623;
mem['h0204] <= 32'hFD842783;
mem['h0205] <= 32'h00178793;
mem['h0206] <= 32'hFCF42C23;
mem['h0207] <= 32'hFD842703;
mem['h0208] <= 32'h03F00793;
mem['h0209] <= 32'hFCE7D6E3;
mem['h020A] <= 32'hFE842783;
mem['h020B] <= 32'h00178793;
mem['h020C] <= 32'hFEF42423;
mem['h020D] <= 32'hFE842703;
mem['h020E] <= 32'h01300793;
mem['h020F] <= 32'hECE7DEE3;
mem['h0210] <= 32'hC00027F3;
mem['h0211] <= 32'hFCF42423;
mem['h0212] <= 32'hC02027F3;
mem['h0213] <= 32'hFCF42223;
mem['h0214] <= 32'hEBF44783;
mem['h0215] <= 32'h06078E63;
mem['h0216] <= 32'h001017B7;
mem['h0217] <= 32'hA9C78513;
mem['h0218] <= 32'h989FF0EF;
mem['h0219] <= 32'hFC842703;
mem['h021A] <= 32'hFD042783;
mem['h021B] <= 32'h40F707B3;
mem['h021C] <= 32'h00800593;
mem['h021D] <= 32'h00078513;
mem['h021E] <= 32'h9C1FF0EF;
mem['h021F] <= 32'h00A00513;
mem['h0220] <= 32'h919FF0EF;
mem['h0221] <= 32'h001017B7;
mem['h0222] <= 32'hAA878513;
mem['h0223] <= 32'h95DFF0EF;
mem['h0224] <= 32'hFC442703;
mem['h0225] <= 32'hFCC42783;
mem['h0226] <= 32'h40F707B3;
mem['h0227] <= 32'h00800593;
mem['h0228] <= 32'h00078513;
mem['h0229] <= 32'h995FF0EF;
mem['h022A] <= 32'h00A00513;
mem['h022B] <= 32'h8EDFF0EF;
mem['h022C] <= 32'h001017B7;
mem['h022D] <= 32'hAB478513;
mem['h022E] <= 32'h931FF0EF;
mem['h022F] <= 32'h00800593;
mem['h0230] <= 32'hFEC42503;
mem['h0231] <= 32'h975FF0EF;
mem['h0232] <= 32'h00A00513;
mem['h0233] <= 32'h8CDFF0EF;
mem['h0234] <= 32'hEB842783;
mem['h0235] <= 32'h00078C63;
mem['h0236] <= 32'hFC442703;
mem['h0237] <= 32'hFCC42783;
mem['h0238] <= 32'h40F70733;
mem['h0239] <= 32'hEB842783;
mem['h023A] <= 32'h00E7A023;
mem['h023B] <= 32'hFC842703;
mem['h023C] <= 32'hFD042783;
mem['h023D] <= 32'h40F707B3;
mem['h023E] <= 32'h00078513;
mem['h023F] <= 32'h14C12083;
mem['h0240] <= 32'h14812403;
mem['h0241] <= 32'h15010113;
mem['h0242] <= 32'h00008067;
mem['h0243] <= 32'hFE010113;
mem['h0244] <= 32'h00112E23;
mem['h0245] <= 32'h00812C23;
mem['h0246] <= 32'h02010413;
mem['h0247] <= 32'h030007B7;
mem['h0248] <= 32'h01F00713;
mem['h0249] <= 32'h00E7A023;
mem['h024A] <= 32'h020007B7;
mem['h024B] <= 32'h00478793;
mem['h024C] <= 32'h0D900713;
mem['h024D] <= 32'h00E7A023;
mem['h024E] <= 32'h001017B7;
mem['h024F] <= 32'hAC078513;
mem['h0250] <= 32'h8A9FF0EF;
mem['h0251] <= 32'h030007B7;
mem['h0252] <= 32'h03F00713;
mem['h0253] <= 32'h00E7A023;
mem['h0254] <= 32'h030007B7;
mem['h0255] <= 32'h07F00713;
mem['h0256] <= 32'h00E7A023;
mem['h0257] <= 32'h00000013;
mem['h0258] <= 32'h001017B7;
mem['h0259] <= 32'hACC78513;
mem['h025A] <= 32'hC41FF0EF;
mem['h025B] <= 32'h00050793;
mem['h025C] <= 32'h00078713;
mem['h025D] <= 32'h00D00793;
mem['h025E] <= 32'hFEF714E3;
mem['h025F] <= 32'h001017B7;
mem['h0260] <= 32'hAE878513;
mem['h0261] <= 32'h865FF0EF;
mem['h0262] <= 32'h001017B7;
mem['h0263] <= 32'hAEC78513;
mem['h0264] <= 32'h859FF0EF;
mem['h0265] <= 32'h001017B7;
mem['h0266] <= 32'hB1478513;
mem['h0267] <= 32'h84DFF0EF;
mem['h0268] <= 32'h001017B7;
mem['h0269] <= 32'hB3C78513;
mem['h026A] <= 32'h841FF0EF;
mem['h026B] <= 32'h001017B7;
mem['h026C] <= 32'hB6078513;
mem['h026D] <= 32'h835FF0EF;
mem['h026E] <= 32'h001017B7;
mem['h026F] <= 32'hB8878513;
mem['h0270] <= 32'h829FF0EF;
mem['h0271] <= 32'h001017B7;
mem['h0272] <= 32'hAE878513;
mem['h0273] <= 32'h81DFF0EF;
mem['h0274] <= 32'h001017B7;
mem['h0275] <= 32'hAE878513;
mem['h0276] <= 32'h811FF0EF;
mem['h0277] <= 32'h001017B7;
mem['h0278] <= 32'hBB078513;
mem['h0279] <= 32'h805FF0EF;
mem['h027A] <= 32'h001017B7;
mem['h027B] <= 32'hAE878513;
mem['h027C] <= 32'hFF8FF0EF;
mem['h027D] <= 32'h00A00793;
mem['h027E] <= 32'hFEF42623;
mem['h027F] <= 32'h0780006F;
mem['h0280] <= 32'h001017B7;
mem['h0281] <= 32'hBD478513;
mem['h0282] <= 32'hFE0FF0EF;
mem['h0283] <= 32'hC95FF0EF;
mem['h0284] <= 32'h00050793;
mem['h0285] <= 32'hFEF405A3;
mem['h0286] <= 32'hFEB44703;
mem['h0287] <= 32'h02000793;
mem['h0288] <= 32'h00E7FE63;
mem['h0289] <= 32'hFEB44703;
mem['h028A] <= 32'h07E00793;
mem['h028B] <= 32'h00E7E863;
mem['h028C] <= 32'hFEB44783;
mem['h028D] <= 32'h00078513;
mem['h028E] <= 32'hF60FF0EF;
mem['h028F] <= 32'h001017B7;
mem['h0290] <= 32'hAE878513;
mem['h0291] <= 32'hFA4FF0EF;
mem['h0292] <= 32'hFEB44703;
mem['h0293] <= 32'h03900793;
mem['h0294] <= 32'h00F71C63;
mem['h0295] <= 32'h00000593;
mem['h0296] <= 32'h00100513;
mem['h0297] <= 32'hC75FF0EF;
mem['h0298] <= 32'h00000013;
mem['h0299] <= 32'h0180006F;
mem['h029A] <= 32'hFEC42783;
mem['h029B] <= 32'hFFF78793;
mem['h029C] <= 32'hFEF42623;
mem['h029D] <= 32'hFEC42783;
mem['h029E] <= 32'hF8F044E3;
mem['h029F] <= 32'hF49FF06F;
mem['h02A0] <= 32'h33323130;
mem['h02A1] <= 32'h37363534;
mem['h02A2] <= 32'h62613938;
mem['h02A3] <= 32'h66656463;
mem['h02A4] <= 32'h00000000;
mem['h02A5] <= 32'h30313D3E;
mem['h02A6] <= 32'h00000030;
mem['h02A7] <= 32'h6C637943;
mem['h02A8] <= 32'h203A7365;
mem['h02A9] <= 32'h00007830;
mem['h02AA] <= 32'h74736E49;
mem['h02AB] <= 32'h203A736E;
mem['h02AC] <= 32'h00007830;
mem['h02AD] <= 32'h736B6843;
mem['h02AE] <= 32'h203A6D75;
mem['h02AF] <= 32'h00007830;
mem['h02B0] <= 32'h746F6F42;
mem['h02B1] <= 32'h2E676E69;
mem['h02B2] <= 32'h00000A2E;
mem['h02B3] <= 32'h73657250;
mem['h02B4] <= 32'h4E452073;
mem['h02B5] <= 32'h20524554;
mem['h02B6] <= 32'h63206F74;
mem['h02B7] <= 32'h69746E6F;
mem['h02B8] <= 32'h2E65756E;
mem['h02B9] <= 32'h00000A2E;
mem['h02BA] <= 32'h0000000A;
mem['h02BB] <= 32'h5F5F2020;
mem['h02BC] <= 32'h20205F5F;
mem['h02BD] <= 32'h2020205F;
mem['h02BE] <= 32'h20202020;
mem['h02BF] <= 32'h5F202020;
mem['h02C0] <= 32'h205F5F5F;
mem['h02C1] <= 32'h20202020;
mem['h02C2] <= 32'h20202020;
mem['h02C3] <= 32'h5F5F5F5F;
mem['h02C4] <= 32'h0000000A;
mem['h02C5] <= 32'h20207C20;
mem['h02C6] <= 32'h285C205F;
mem['h02C7] <= 32'h5F20295F;
mem['h02C8] <= 32'h5F205F5F;
mem['h02C9] <= 32'h202F5F5F;
mem['h02CA] <= 32'h7C5F5F5F;
mem['h02CB] <= 32'h5F5F2020;
mem['h02CC] <= 32'h2F20205F;
mem['h02CD] <= 32'h5F5F5F20;
mem['h02CE] <= 32'h00000A7C;
mem['h02CF] <= 32'h7C207C20;
mem['h02D0] <= 32'h7C20295F;
mem['h02D1] <= 32'h202F7C20;
mem['h02D2] <= 32'h202F5F5F;
mem['h02D3] <= 32'h5F5C205F;
mem['h02D4] <= 32'h5C205F5F;
mem['h02D5] <= 32'h5F202F20;
mem['h02D6] <= 32'h207C5C20;
mem['h02D7] <= 32'h00000A7C;
mem['h02D8] <= 32'h20207C20;
mem['h02D9] <= 32'h7C2F5F5F;
mem['h02DA] <= 32'h28207C20;
mem['h02DB] <= 32'h28207C5F;
mem['h02DC] <= 32'h7C20295F;
mem['h02DD] <= 32'h20295F5F;
mem['h02DE] <= 32'h5F28207C;
mem['h02DF] <= 32'h207C2029;
mem['h02E0] <= 32'h5F5F5F7C;
mem['h02E1] <= 32'h0000000A;
mem['h02E2] <= 32'h7C5F7C20;
mem['h02E3] <= 32'h7C202020;
mem['h02E4] <= 32'h5F5C7C5F;
mem['h02E5] <= 32'h5F5C5F5F;
mem['h02E6] <= 32'h5F2F5F5F;
mem['h02E7] <= 32'h2F5F5F5F;
mem['h02E8] <= 32'h5F5F5C20;
mem['h02E9] <= 32'h5C202F5F;
mem['h02EA] <= 32'h5F5F5F5F;
mem['h02EB] <= 32'h00000A7C;
mem['h02EC] <= 32'h5B202020;
mem['h02ED] <= 32'h52205D39;
mem['h02EE] <= 32'h73206E75;
mem['h02EF] <= 32'h6C706D69;
mem['h02F0] <= 32'h69747369;
mem['h02F1] <= 32'h65622063;
mem['h02F2] <= 32'h6D68636E;
mem['h02F3] <= 32'h0A6B7261;
mem['h02F4] <= 32'h00000000;
mem['h02F5] <= 32'h6D6D6F43;
mem['h02F6] <= 32'h3E646E61;
mem['h02F7] <= 32'h00000020;
end
always @(posedge clk)
mem_data <= mem[mem_addr];
// ============================================================================
reg o_ready;
always @(posedge clk or negedge rstn)
if (!rstn) o_ready <= 1'd0;
else o_ready <= valid && ((addr & MEM_ADDR_MASK) != 0);
// Output connectins
assign ready = o_ready;
assign rdata = mem_data;
assign mem_addr = addr[MEM_SIZE_BITS+1:2];
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Mon May 26 17:17:23 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode synth_stub
// /home/keith/Documents/VHDL-lib/top/stereo_radio/ip/fir_lp_54kHz/fir_lp_54kHz_stub.v
// Design : fir_lp_54kHz
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fir_compiler_v7_1,Vivado 2014.1" *)
module fir_lp_54kHz(aclk, s_axis_data_tvalid, s_axis_data_tready, s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[31:0],m_axis_data_tvalid,m_axis_data_tdata[95:0]" */;
input aclk;
input s_axis_data_tvalid;
output s_axis_data_tready;
input [31:0]s_axis_data_tdata;
output m_axis_data_tvalid;
output [95:0]m_axis_data_tdata;
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// ********************************************************************************************************************************
// File name: memphy.v
// This file instantiates all the main components of the PHY.
// ********************************************************************************************************************************
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_memphy(
global_reset_n,
soft_reset_n,
reset_request_n,
ctl_reset_n,
pll_locked,
oct_ctl_rs_value,
oct_ctl_rt_value,
afi_addr,
afi_cke,
afi_cs_n,
afi_ba,
afi_cas_n,
afi_odt,
afi_ras_n,
afi_we_n,
afi_rst_n,
afi_mem_clk_disable,
afi_dqs_burst,
afi_wlat,
afi_rlat,
afi_wdata,
afi_wdata_valid,
afi_dm,
afi_rdata,
afi_rdata_en,
afi_rdata_en_full,
afi_rdata_valid,
afi_cal_debug_info,
afi_ctl_refresh_done,
afi_ctl_long_idle,
afi_seq_busy,
afi_cal_success,
afi_cal_fail,
mem_a,
mem_ba,
mem_ck,
mem_ck_n,
mem_cke,
mem_cs_n,
mem_dm,
mem_odt,
mem_ras_n,
mem_cas_n,
mem_we_n,
mem_reset_n,
mem_dq,
mem_dqs,
mem_dqs_n,
pll_afi_clk,
pll_addr_cmd_clk,
pll_mem_clk,
pll_write_clk,
pll_dqs_ena_clk,
seq_clk,
pll_avl_clk,
pll_config_clk,
dll_phy_delayctrl
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver
parameter DEVICE_FAMILY = "";
// On-chip termination
parameter OCT_SERIES_TERM_CONTROL_WIDTH = "";
parameter OCT_PARALLEL_TERM_CONTROL_WIDTH = "";
// PHY-Memory Interface
// Memory device specific parameters, they are set according to the memory spec
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_CK_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_DQS_WIDTH = "";
parameter MEM_CHIP_SELECT_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
// PHY-Controller (AFI) Interface
// The AFI interface widths are derived from the memory interface widths based on full/half rate operations
// The calculations are done on higher level wrapper
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_DEBUG_INFO_WIDTH = "";
parameter CALIB_VFIFO_OFFSET = "";
parameter CALIB_LFIFO_OFFSET = "";
parameter AFI_BANK_WIDTH = "";
parameter AFI_CHIP_SELECT_WIDTH = "";
parameter AFI_CLK_EN_WIDTH = "";
parameter AFI_ODT_WIDTH = "";
parameter AFI_MAX_WRITE_LATENCY_COUNT_WIDTH = "";
parameter AFI_MAX_READ_LATENCY_COUNT_WIDTH = "";
parameter AFI_DATA_MASK_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter AFI_DATA_WIDTH = "";
parameter AFI_DQS_WIDTH = "";
// DLL Interface
// The DLL delay output control is always 6 bits for current existing devices
parameter DLL_DELAY_CTRL_WIDTH = "";
// Read Datapath parameters for timing purposes
parameter NUM_SUBGROUP_PER_READ_DQS = "";
parameter QVLD_EXTRA_FLOP_STAGES = "";
parameter QVLD_WR_ADDRESS_OFFSET = "";
// Read Datapath parameters, the values should not be changed unless the intention is to change the architecture
parameter READ_VALID_TIMEOUT_WIDTH = "";
parameter READ_VALID_FIFO_SIZE = "";
parameter READ_FIFO_SIZE = "";
// Latency calibration parameters
parameter MAX_LATENCY_COUNT_WIDTH = "";
parameter MAX_READ_LATENCY = "";
// Write Datapath
// The sequencer uses this value to control write latency during calibration
parameter MAX_WRITE_LATENCY_COUNT_WIDTH = 4;
parameter NUM_WRITE_PATH_FLOP_STAGES = "";
// Address/Command Datapath
parameter NUM_AC_FR_CYCLE_SHIFTS = "";
// Initialization Sequence
parameter INIT_COUNT_WIDTH = "";
parameter MEM_BURST_LENGTH = "";
parameter MEM_T_WL = "";
parameter MEM_T_RL = "";
parameter MEM_TINIT_CK = "";
parameter MEM_TMRD_CK = "";
parameter RDIMM = "";
parameter MR0_BL = "";
parameter MR0_BT = "";
parameter MR0_CAS_LATENCY = "";
parameter MR0_DLL = "";
parameter MR0_WR = "";
parameter MR0_PD = "";
parameter MR1_DLL = "";
parameter MR1_ODS = "";
parameter MR1_RTT = "";
parameter MR1_AL = "";
parameter MR1_WL = "";
parameter MR1_TDQS = "";
parameter MR1_QOFF = "";
parameter MR2_CWL = "";
parameter MR2_ASR = "";
parameter MR2_SRT = "";
parameter MR2_RTT_WR = "";
parameter MR3_MPR_RF = "";
parameter MR3_MPR = "";
parameter RDIMM_CONFIG = 64'h0;
parameter DELAY_PER_OPA_TAP = "";
parameter DELAY_PER_DCHAIN_TAP = "";
parameter DLL_DELAY_CHAIN_LENGTH = "";
parameter MEM_NUMBER_OF_RANKS = "";
parameter MEM_MIRROR_ADDRESSING = "";
// The sequencer issues back-to-back reads during calibration, NOPs may need to be inserted depending on the burst length
parameter SEQ_BURST_COUNT_WIDTH = "";
// Width of the counter used to determine the number of cycles required
// to calculate if the rddata pattern is all 0 or all 1.
parameter VCALIB_COUNT_WIDTH = "";
parameter ALTDQDQS_INPUT_FREQ = "";
parameter ALTDQDQS_DELAY_CHAIN_BUFFER_MODE = "";
parameter ALTDQDQS_DQS_PHASE_SETTING = "";
parameter ALTDQDQS_DQS_PHASE_SHIFT = "";
parameter ALTDQDQS_DELAYED_CLOCK_PHASE_SETTING = "";
parameter TB_PROTOCOL = "";
parameter TB_MEM_CLK_FREQ = "";
parameter TB_RATE = "";
parameter TB_MEM_DQ_WIDTH = "";
parameter TB_MEM_DQS_WIDTH = "";
parameter TB_PLL_DLL_MASTER = "";
parameter FAST_SIM_MODEL = "";
parameter FAST_SIM_CALIBRATION = "";
// Local parameters
localparam DOUBLE_MEM_DQ_WIDTH = MEM_DQ_WIDTH * 2;
localparam HALF_AFI_DATA_WIDTH = AFI_DATA_WIDTH / 2;
// Width of the calibration status register used to control calibration skipping.
parameter CALIB_REG_WIDTH = "";
// The number of AFI Resets to generate
localparam NUM_AFI_RESET = 4;
// Read valid predication parameters
localparam READ_VALID_FIFO_WRITE_MEM_DEPTH = READ_VALID_FIFO_SIZE / 2; // write operates on half rate clock
localparam READ_VALID_FIFO_READ_MEM_DEPTH = READ_VALID_FIFO_SIZE / 2; // valid-read-prediction operates on half rate clock
localparam READ_VALID_FIFO_PER_DQS_WIDTH = 2; // valid fifo output is a half-rate signal
localparam READ_VALID_FIFO_WIDTH = READ_VALID_FIFO_PER_DQS_WIDTH * MEM_READ_DQS_WIDTH;
localparam READ_VALID_FIFO_WRITE_ADDR_WIDTH = ceil_log2(READ_VALID_FIFO_WRITE_MEM_DEPTH);
localparam READ_VALID_FIFO_READ_ADDR_WIDTH = ceil_log2(READ_VALID_FIFO_READ_MEM_DEPTH);
// Data resynchronization FIFO
localparam READ_FIFO_WRITE_MEM_DEPTH = READ_FIFO_SIZE / 2; // data is written on half rate clock
localparam READ_FIFO_READ_MEM_DEPTH = READ_FIFO_SIZE / 2; // data is read out on half rate clock
localparam READ_FIFO_WRITE_ADDR_WIDTH = ceil_log2(READ_FIFO_WRITE_MEM_DEPTH);
localparam READ_FIFO_READ_ADDR_WIDTH = ceil_log2(READ_FIFO_READ_MEM_DEPTH);
// Sequencer parameters
localparam SEQ_ADDRESS_WIDTH = AFI_ADDRESS_WIDTH;
localparam SEQ_BANK_WIDTH = AFI_BANK_WIDTH;
localparam SEQ_CHIP_SELECT_WIDTH = AFI_CHIP_SELECT_WIDTH;
localparam SEQ_CLK_EN_WIDTH = AFI_CLK_EN_WIDTH;
localparam SEQ_ODT_WIDTH = AFI_ODT_WIDTH;
localparam SEQ_DATA_MASK_WIDTH = AFI_DATA_MASK_WIDTH;
localparam SEQ_CONTROL_WIDTH = AFI_CONTROL_WIDTH;
localparam SEQ_DATA_WIDTH = AFI_DATA_WIDTH;
localparam SEQ_DQS_WIDTH = AFI_DQS_WIDTH;
// END PARAMETER SECTION
// ********************************************************************************************************************************
// ********************************************************************************************************************************
// BEGIN PORT SECTION
// Reset Interface
input global_reset_n; // Resets (active-low) the whole system (all PHY logic + PLL)
input soft_reset_n; // Resets (active-low) PHY logic only, PLL is NOT reset
input pll_locked; // Indicates that PLL is locked
output reset_request_n; // When 1, PLL is out of lock
output ctl_reset_n; // Asynchronously asserted and synchronously de-asserted on afi_clk domain
input [OCT_SERIES_TERM_CONTROL_WIDTH-1:0] oct_ctl_rs_value;
input [OCT_PARALLEL_TERM_CONTROL_WIDTH-1:0] oct_ctl_rt_value;
// PHY-Controller Interface, AFI 2.0
// Control Interface
input [AFI_ADDRESS_WIDTH-1:0] afi_addr; // address
input [AFI_CLK_EN_WIDTH-1:0] afi_cke;
input [AFI_CHIP_SELECT_WIDTH-1:0] afi_cs_n;
input [AFI_BANK_WIDTH-1:0] afi_ba;
input [AFI_CONTROL_WIDTH-1:0] afi_cas_n;
input [AFI_ODT_WIDTH-1:0] afi_odt;
input [AFI_CONTROL_WIDTH-1:0] afi_ras_n;
input [AFI_CONTROL_WIDTH-1:0] afi_we_n;
input [AFI_CONTROL_WIDTH-1:0] afi_rst_n;
input afi_mem_clk_disable;
input [AFI_DQS_WIDTH-1:0] afi_dqs_burst;
output [AFI_MAX_WRITE_LATENCY_COUNT_WIDTH-1:0] afi_wlat;
output [AFI_MAX_READ_LATENCY_COUNT_WIDTH-1:0] afi_rlat;
// Write data interface
input [AFI_DATA_WIDTH-1:0] afi_wdata; // write data
input [AFI_DQS_WIDTH-1:0] afi_wdata_valid; // write data valid, used to maintain write latency required by protocol spec
input [AFI_DATA_MASK_WIDTH-1:0] afi_dm; // write data mask
// Read data interface
output [AFI_DATA_WIDTH-1:0] afi_rdata; // read data
input afi_rdata_en; // read enable, used to maintain the read latency calibrated by PHY
input afi_rdata_en_full; // read enable full burst, used to create DQS enable
output afi_rdata_valid;// read data valid
// Status interface
output afi_cal_success; // calibration success
output [AFI_DEBUG_INFO_WIDTH - 1:0] afi_cal_debug_info;
input [MEM_CHIP_SELECT_WIDTH-1:0] afi_ctl_refresh_done;
input [MEM_CHIP_SELECT_WIDTH-1:0] afi_ctl_long_idle;
output [MEM_CHIP_SELECT_WIDTH-1:0] afi_seq_busy;
output afi_cal_fail; // calibration failure
// PHY-Memory Interface
output [MEM_ADDRESS_WIDTH-1:0] mem_a;
output [MEM_BANK_WIDTH-1:0] mem_ba;
output [MEM_CK_WIDTH-1:0] mem_ck;
output [MEM_CK_WIDTH-1:0] mem_ck_n;
output [MEM_CLK_EN_WIDTH-1:0] mem_cke;
output [MEM_CHIP_SELECT_WIDTH-1:0] mem_cs_n;
output [MEM_DM_WIDTH-1:0] mem_dm;
output [MEM_ODT_WIDTH-1:0] mem_odt;
output [MEM_CONTROL_WIDTH-1:0] mem_ras_n;
output [MEM_CONTROL_WIDTH-1:0] mem_cas_n;
output [MEM_CONTROL_WIDTH-1:0] mem_we_n;
output mem_reset_n;
inout [MEM_DQ_WIDTH-1:0] mem_dq;
inout [MEM_DQS_WIDTH-1:0] mem_dqs;
inout [MEM_DQS_WIDTH-1:0] mem_dqs_n;
// PLL Interface
input pll_afi_clk; // clocks AFI interface logic
input pll_addr_cmd_clk; // clocks address/command DDIO
input pll_mem_clk; // output clock to memory
input pll_write_clk; // clocks write data DDIO
input pll_dqs_ena_clk;
input seq_clk;
input pll_avl_clk;
input pll_config_clk;
// DLL Interface
input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl; // dll output used to control the input DQS phase shift
// END PARAMETER SECTION
// ********************************************************************************************************************************
wire [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address;
wire [AFI_BANK_WIDTH-1:0] phy_ddio_bank;
wire [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
wire [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
wire [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
wire [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
wire [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
wire [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
wire [AFI_CONTROL_WIDTH-1:0] phy_ddio_reset_n;
wire [AFI_DATA_WIDTH-1:0] phy_ddio_dq;
wire [AFI_DQS_WIDTH-1:0] phy_ddio_dqs_en;
wire [AFI_DQS_WIDTH-1:0] phy_ddio_oct_ena;
wire [AFI_DQS_WIDTH-1:0] phy_ddio_wrdata_en;
wire [AFI_DATA_MASK_WIDTH-1:0] phy_ddio_wrdata_mask;
wire [DOUBLE_MEM_DQ_WIDTH-1:0] ddio_phy_dq;
wire [MEM_READ_DQS_WIDTH-1:0] read_capture_clk;
wire [AFI_DATA_WIDTH-1:0] phy_mux_rdata;
wire [AFI_DATA_WIDTH-1:0] phy_mux_read_fifo_q;
wire phy_mux_rdata_valid;
wire [SEQ_ADDRESS_WIDTH-1:0] seq_mux_address;
wire [SEQ_BANK_WIDTH-1:0] seq_mux_bank;
wire [SEQ_CHIP_SELECT_WIDTH-1:0] seq_mux_cs_n;
wire [SEQ_CLK_EN_WIDTH-1:0] seq_mux_cke;
wire [SEQ_ODT_WIDTH-1:0] seq_mux_odt;
wire [SEQ_CONTROL_WIDTH-1:0] seq_mux_ras_n;
wire [SEQ_CONTROL_WIDTH-1:0] seq_mux_cas_n;
wire [SEQ_CONTROL_WIDTH-1:0] seq_mux_we_n;
wire [SEQ_CONTROL_WIDTH-1:0] seq_mux_reset_n;
wire [SEQ_DQS_WIDTH-1:0] seq_mux_dqs_en;
wire [SEQ_DATA_WIDTH-1:0] seq_mux_wdata;
wire [SEQ_DQS_WIDTH-1:0] seq_mux_wdata_valid;
wire [SEQ_DATA_MASK_WIDTH-1:0] seq_mux_dm;
wire seq_mux_rdata_en;
wire [SEQ_DATA_WIDTH-1:0] mux_seq_rdata;
wire [SEQ_DATA_WIDTH-1:0] mux_seq_read_fifo_q;
wire mux_seq_rdata_valid;
wire mux_sel;
wire [AFI_ADDRESS_WIDTH-1:0] mux_phy_address;
wire [AFI_BANK_WIDTH-1:0] mux_phy_bank;
wire [AFI_CHIP_SELECT_WIDTH-1:0] mux_phy_cs_n;
wire [AFI_CLK_EN_WIDTH-1:0] mux_phy_cke;
wire [AFI_ODT_WIDTH-1:0] mux_phy_odt;
wire [AFI_CONTROL_WIDTH-1:0] mux_phy_ras_n;
wire [AFI_CONTROL_WIDTH-1:0] mux_phy_cas_n;
wire [AFI_CONTROL_WIDTH-1:0] mux_phy_we_n;
wire [AFI_CONTROL_WIDTH-1:0] mux_phy_reset_n;
wire [AFI_DQS_WIDTH-1:0] mux_phy_dqs_en;
wire [AFI_DATA_WIDTH-1:0] mux_phy_wdata;
wire [AFI_DQS_WIDTH-1:0] mux_phy_wdata_valid;
wire [AFI_DATA_MASK_WIDTH-1:0] mux_phy_dm;
wire mux_phy_rdata_en;
wire mux_phy_rdata_en_full;
wire [MAX_LATENCY_COUNT_WIDTH-1:0] seq_read_latency_counter;
wire [MEM_READ_DQS_WIDTH-1:0] seq_read_increment_vfifo_fr;
wire [MEM_READ_DQS_WIDTH-1:0] seq_read_increment_vfifo_hr;
wire [MEM_READ_DQS_WIDTH-1:0] seq_read_increment_vfifo_qr;
wire [NUM_AFI_RESET-1:0] reset_n_afi_clk;
wire reset_n_addr_cmd_clk;
wire reset_n_seq_clk;
wire reset_n_resync_clk;
wire [READ_VALID_FIFO_WIDTH-1:0] dqs_enable_ctrl;
wire seq_reset_mem_stable;
wire [MEM_READ_DQS_WIDTH-1:0] seq_read_fifo_reset;
wire [AFI_DQS_WIDTH-1:0] force_oct_off;
wire reset_n_scc_clk;
wire reset_n_avl_clk;
wire csr_soft_reset_req;
wire [MEM_READ_DQS_WIDTH-1:0] dqs_edge_detect;
localparam SKIP_CALIBRATION_STEPS = 7'b1111111;
localparam CALIBRATION_STEPS = SKIP_CALIBRATION_STEPS;
localparam SKIP_MEM_INIT = 1'b1;
localparam SEQ_CALIB_INIT = {CALIBRATION_STEPS, SKIP_MEM_INIT};
reg [CALIB_REG_WIDTH-1:0] seq_calib_init_reg /* synthesis syn_noprune syn_preserve = 1 */;
// Initialization of the sequencer status register. This register
// is preserved in the netlist so that it can be forced during simulation
always @(posedge pll_afi_clk)
`ifndef SYNTH_FOR_SIM
//synthesis translate_off
`endif
seq_calib_init_reg <= SEQ_CALIB_INIT;
`ifndef SYNTH_FOR_SIM
//synthesis translate_on
//synthesis read_comments_as_HDL on
`endif
// seq_calib_init_reg <= {CALIB_REG_WIDTH{1'b0}};
`ifndef SYNTH_FOR_SIM
// synthesis read_comments_as_HDL off
`endif
// ********************************************************************************************************************************
// The reset scheme used in the UNIPHY is asynchronous assert and synchronous de-assert
// The reset block has 2 main functionalities:
// 1. Keep all the PHY logic in reset state until after the PLL is locked
// 2. Synchronize the reset to each clock domain
// ********************************************************************************************************************************
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_reset ureset(
.pll_afi_clk (pll_afi_clk),
.pll_addr_cmd_clk (pll_addr_cmd_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.seq_clk (seq_clk),
.pll_avl_clk (pll_avl_clk),
.scc_clk (pll_config_clk),
.reset_n_scc_clk (reset_n_scc_clk),
.reset_n_avl_clk (reset_n_avl_clk),
.read_capture_clk (read_capture_clk),
.pll_locked (pll_locked),
.global_reset_n (global_reset_n),
.soft_reset_n (soft_reset_n),
.csr_soft_reset_req (csr_soft_reset_req),
.reset_request_n (reset_request_n),
.ctl_reset_n (ctl_reset_n),
.reset_n_afi_clk (reset_n_afi_clk),
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
.reset_n_seq_clk (reset_n_seq_clk),
.reset_n_resync_clk (reset_n_resync_clk)
);
defparam ureset.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam ureset.NUM_AFI_RESET = NUM_AFI_RESET;
wire scc_data;
wire [MEM_READ_DQS_WIDTH - 1:0] scc_dqs_ena;
wire [MEM_READ_DQS_WIDTH - 1:0] scc_dqs_io_ena;
wire [MEM_DQ_WIDTH - 1:0] scc_dq_ena;
wire [MEM_DM_WIDTH - 1:0] scc_dm_ena;
wire scc_upd;
wire [MEM_READ_DQS_WIDTH - 1:0] capture_strobe_tracking;
// ********************************************************************************************************************************
// The sequencer is responsible for intercepting the AFI interface during the initialization and calibration stages
// During initialization stage, the sequencer executes a sequence according to the memory device spec
// There are 2 steps in the calibration stage:
// 1. Calibrates for read data valid in the returned memory clock domain (read valid prediction)
// 2. Calibrates for read data valid in the afi_clk domain (read latency calibration)
// After successful calibration, the sequencer will pass full control back to the AFI interface
// ********************************************************************************************************************************
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_nios_sequencer usequencer(
.pll_config_clk (pll_config_clk),
.pll_avl_clk (pll_avl_clk),
.reset_n_avl_clk (reset_n_avl_clk),
.reset_n_scc_clk (reset_n_scc_clk),
.scc_data (scc_data),
.scc_dqs_ena (scc_dqs_ena),
.scc_dqs_io_ena (scc_dqs_io_ena),
.scc_dq_ena (scc_dq_ena),
.scc_dm_ena (scc_dm_ena),
.scc_upd (scc_upd),
.capture_strobe_tracking (capture_strobe_tracking),
.pll_afi_clk (seq_clk),
.reset_n (reset_n_seq_clk),
.mux_seq_rdata (mux_seq_rdata),
.mux_seq_read_fifo_q (mux_seq_read_fifo_q),
.mux_seq_rdata_valid (mux_seq_rdata_valid),
.seq_mux_address (seq_mux_address),
.seq_mux_bank (seq_mux_bank),
.seq_mux_cs_n (seq_mux_cs_n),
.seq_mux_cke (seq_mux_cke),
.seq_mux_odt (seq_mux_odt),
.seq_mux_ras_n (seq_mux_ras_n),
.seq_mux_cas_n (seq_mux_cas_n),
.seq_mux_we_n (seq_mux_we_n),
.seq_mux_reset_n (seq_mux_reset_n),
.seq_mux_dqs_en (seq_mux_dqs_en),
.seq_mux_wdata (seq_mux_wdata),
.seq_mux_wdata_valid (seq_mux_wdata_valid),
.seq_mux_dm (seq_mux_dm),
.seq_mux_rdata_en (seq_mux_rdata_en),
.mux_sel (mux_sel),
.seq_read_latency_counter (seq_read_latency_counter),
.seq_read_increment_vfifo_fr (seq_read_increment_vfifo_fr),
.seq_read_increment_vfifo_hr (seq_read_increment_vfifo_hr),
.seq_read_increment_vfifo_qr (seq_read_increment_vfifo_qr),
.afi_rlat (afi_rlat),
.afi_wlat (afi_wlat),
.afi_cal_debug_info(afi_cal_debug_info),
.afi_ctl_refresh_done (afi_ctl_refresh_done),
.afi_ctl_long_idle (afi_ctl_long_idle),
.afi_seq_busy (afi_seq_busy),
.afi_cal_success (afi_cal_success),
.afi_cal_fail (afi_cal_fail),
.seq_reset_mem_stable (seq_reset_mem_stable),
.seq_read_fifo_reset (seq_read_fifo_reset),
.seq_calib_init (seq_calib_init_reg)
);
defparam usequencer.MEM_ADDRESS_WIDTH = MEM_ADDRESS_WIDTH;
defparam usequencer.MEM_BANK_WIDTH = MEM_BANK_WIDTH;
defparam usequencer.MEM_CLK_EN_WIDTH = MEM_CLK_EN_WIDTH;
defparam usequencer.MEM_ODT_WIDTH = MEM_ODT_WIDTH;
defparam usequencer.MEM_CHIP_SELECT_WIDTH = MEM_CHIP_SELECT_WIDTH;
defparam usequencer.MEM_CONTROL_WIDTH = MEM_CONTROL_WIDTH;
defparam usequencer.MEM_DM_WIDTH = MEM_DM_WIDTH;
defparam usequencer.MEM_DQ_WIDTH = MEM_DQ_WIDTH;
defparam usequencer.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam usequencer.MEM_WRITE_DQS_WIDTH = MEM_WRITE_DQS_WIDTH;
defparam usequencer.AFI_ADDRESS_WIDTH = SEQ_ADDRESS_WIDTH;
defparam usequencer.AFI_BANK_WIDTH = SEQ_BANK_WIDTH;
defparam usequencer.AFI_CHIP_SELECT_WIDTH = SEQ_CHIP_SELECT_WIDTH;
defparam usequencer.AFI_CLK_EN_WIDTH = SEQ_CLK_EN_WIDTH;
defparam usequencer.AFI_ODT_WIDTH = SEQ_ODT_WIDTH;
defparam usequencer.AFI_DATA_MASK_WIDTH = SEQ_DATA_MASK_WIDTH;
defparam usequencer.AFI_CONTROL_WIDTH = SEQ_CONTROL_WIDTH;
defparam usequencer.AFI_DATA_WIDTH = SEQ_DATA_WIDTH;
defparam usequencer.AFI_DQS_WIDTH = SEQ_DQS_WIDTH;
defparam usequencer.AFI_MAX_WRITE_LATENCY_COUNT_WIDTH = AFI_MAX_WRITE_LATENCY_COUNT_WIDTH;
defparam usequencer.AFI_MAX_READ_LATENCY_COUNT_WIDTH = AFI_MAX_READ_LATENCY_COUNT_WIDTH;
defparam usequencer.AFI_DEBUG_INFO_WIDTH = AFI_DEBUG_INFO_WIDTH;
defparam usequencer.CALIB_VFIFO_OFFSET = CALIB_VFIFO_OFFSET;
defparam usequencer.CALIB_LFIFO_OFFSET = CALIB_LFIFO_OFFSET;
defparam usequencer.MEM_TINIT_CK = MEM_TINIT_CK;
defparam usequencer.MEM_TMRD_CK = MEM_TMRD_CK;
defparam usequencer.RDIMM = RDIMM;
defparam usequencer.MR0_BL = MR0_BL;
defparam usequencer.MR0_BT = MR0_BT;
defparam usequencer.MR0_CAS_LATENCY = MR0_CAS_LATENCY;
defparam usequencer.MR0_DLL = MR0_DLL;
defparam usequencer.MR0_WR = MR0_WR;
defparam usequencer.MR0_PD = MR0_PD;
defparam usequencer.MR1_DLL = MR1_DLL;
defparam usequencer.MR1_ODS = MR1_ODS;
defparam usequencer.MR1_RTT = MR1_RTT;
defparam usequencer.MR1_AL = MR1_AL;
defparam usequencer.MR1_WL = MR1_WL;
defparam usequencer.MR1_TDQS = MR1_TDQS;
defparam usequencer.MR1_QOFF = MR1_QOFF;
defparam usequencer.MR2_CWL = MR2_CWL;
defparam usequencer.MR2_ASR = MR2_ASR;
defparam usequencer.MR2_SRT = MR2_SRT;
defparam usequencer.MR2_RTT_WR = MR2_RTT_WR;
defparam usequencer.MR3_MPR_RF = MR3_MPR_RF;
defparam usequencer.MR3_MPR = MR3_MPR;
defparam usequencer.RDIMM_CONFIG = RDIMM_CONFIG;
defparam usequencer.MEM_BURST_LENGTH = MEM_BURST_LENGTH;
defparam usequencer.MEM_T_WL = MEM_T_WL;
defparam usequencer.MEM_T_RL = MEM_T_RL;
defparam usequencer.READ_VALID_TIMEOUT_WIDTH = READ_VALID_TIMEOUT_WIDTH;
defparam usequencer.MAX_LATENCY_COUNT_WIDTH = MAX_LATENCY_COUNT_WIDTH;
defparam usequencer.MAX_READ_LATENCY = MAX_READ_LATENCY;
defparam usequencer.MAX_WRITE_LATENCY_COUNT_WIDTH = MAX_WRITE_LATENCY_COUNT_WIDTH;
defparam usequencer.INIT_COUNT_WIDTH = INIT_COUNT_WIDTH;
defparam usequencer.SEQ_BURST_COUNT_WIDTH = SEQ_BURST_COUNT_WIDTH;
defparam usequencer.VCALIB_COUNT_WIDTH = VCALIB_COUNT_WIDTH;
defparam usequencer.CALIB_REG_WIDTH = CALIB_REG_WIDTH;
defparam usequencer.READ_VALID_FIFO_SIZE = READ_VALID_FIFO_SIZE;
defparam usequencer.DELAY_PER_OPA_TAP = DELAY_PER_OPA_TAP;
defparam usequencer.DELAY_PER_DCHAIN_TAP = DELAY_PER_DCHAIN_TAP;
defparam usequencer.DLL_DELAY_CHAIN_LENGTH = DLL_DELAY_CHAIN_LENGTH;
defparam usequencer.MEM_NUMBER_OF_RANKS = MEM_NUMBER_OF_RANKS;
defparam usequencer.MEM_MIRROR_ADDRESSING = MEM_MIRROR_ADDRESSING;
// ********************************************************************************************************************************
// This module contains a set of muxes between the sequencer AFI signals and the controller AFI signals
// ********************************************************************************************************************************
reg [AFI_ADDRESS_WIDTH-1:0] afi_addr_r;
reg [AFI_BANK_WIDTH-1:0] afi_ba_r;
reg [AFI_CONTROL_WIDTH-1:0] afi_cas_n_r;
reg [AFI_CLK_EN_WIDTH-1:0] afi_cke_r;
reg [AFI_CHIP_SELECT_WIDTH-1:0] afi_cs_n_r;
reg [AFI_ODT_WIDTH-1:0] afi_odt_r;
reg [AFI_CONTROL_WIDTH-1:0] afi_ras_n_r;
reg [AFI_CONTROL_WIDTH-1:0] afi_we_n_r;
reg [AFI_CONTROL_WIDTH-1:0] afi_rst_n_r;
reg [AFI_ADDRESS_WIDTH-1:0] seq_mux_address_r;
reg [AFI_BANK_WIDTH-1:0] seq_mux_bank_r;
reg [AFI_CHIP_SELECT_WIDTH-1:0] seq_mux_cs_n_r;
reg [AFI_CLK_EN_WIDTH-1:0] seq_mux_cke_r;
reg [AFI_ODT_WIDTH-1:0] seq_mux_odt_r;
reg [AFI_CONTROL_WIDTH-1:0] seq_mux_ras_n_r;
reg [AFI_CONTROL_WIDTH-1:0] seq_mux_cas_n_r;
reg [AFI_CONTROL_WIDTH-1:0] seq_mux_we_n_r;
reg [AFI_CONTROL_WIDTH-1:0] seq_mux_reset_n_r;
always @(posedge pll_addr_cmd_clk)
begin
afi_addr_r <= afi_addr;
afi_ba_r <= afi_ba;
afi_cs_n_r <= afi_cs_n;
afi_cke_r <= afi_cke;
afi_odt_r <= afi_odt;
afi_ras_n_r <= afi_ras_n;
afi_cas_n_r <= afi_cas_n;
afi_we_n_r <= afi_we_n;
afi_rst_n_r <= afi_rst_n;
seq_mux_address_r <= seq_mux_address;
seq_mux_bank_r <= seq_mux_bank;
seq_mux_cs_n_r <= seq_mux_cs_n;
seq_mux_cke_r <= seq_mux_cke;
seq_mux_odt_r <= seq_mux_odt;
seq_mux_ras_n_r <= seq_mux_ras_n;
seq_mux_cas_n_r <= seq_mux_cas_n;
seq_mux_we_n_r <= seq_mux_we_n;
seq_mux_reset_n_r <= seq_mux_reset_n;
end
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_afi_mux uafi_mux(
.mux_sel (mux_sel),
.afi_address (afi_addr_r),
.afi_bank (afi_ba_r),
.afi_cs_n (afi_cs_n_r),
.afi_cke (afi_cke_r),
.afi_odt (afi_odt_r),
.afi_ras_n (afi_ras_n_r),
.afi_cas_n (afi_cas_n_r),
.afi_we_n (afi_we_n_r),
.afi_rst_n (afi_rst_n_r),
.afi_dqs_burst (afi_dqs_burst),
.afi_wdata (afi_wdata),
.afi_wdata_valid (afi_wdata_valid),
.afi_dm (afi_dm),
.afi_rdata_en (afi_rdata_en),
.afi_rdata_en_full (afi_rdata_en_full),
.afi_rdata (afi_rdata),
.afi_rdata_valid (afi_rdata_valid),
.seq_mux_address (seq_mux_address_r),
.seq_mux_bank (seq_mux_bank_r),
.seq_mux_cs_n (seq_mux_cs_n_r),
.seq_mux_cke (seq_mux_cke_r),
.seq_mux_odt (seq_mux_odt_r),
.seq_mux_ras_n (seq_mux_ras_n_r),
.seq_mux_cas_n (seq_mux_cas_n_r),
.seq_mux_we_n (seq_mux_we_n_r),
.seq_mux_reset_n (seq_mux_reset_n_r),
.seq_mux_dqs_en (seq_mux_dqs_en),
.seq_mux_wdata (seq_mux_wdata),
.seq_mux_wdata_valid (seq_mux_wdata_valid),
.seq_mux_dm (seq_mux_dm),
.seq_mux_rdata_en (seq_mux_rdata_en),
.mux_seq_rdata (mux_seq_rdata),
.mux_seq_read_fifo_q (mux_seq_read_fifo_q),
.mux_seq_rdata_valid (mux_seq_rdata_valid),
.mux_phy_address (mux_phy_address),
.mux_phy_bank (mux_phy_bank),
.mux_phy_cs_n (mux_phy_cs_n),
.mux_phy_cke (mux_phy_cke),
.mux_phy_odt (mux_phy_odt),
.mux_phy_ras_n (mux_phy_ras_n),
.mux_phy_cas_n (mux_phy_cas_n),
.mux_phy_we_n (mux_phy_we_n),
.mux_phy_reset_n (mux_phy_reset_n),
.mux_phy_dqs_en (mux_phy_dqs_en),
.mux_phy_wdata (mux_phy_wdata),
.mux_phy_wdata_valid (mux_phy_wdata_valid),
.mux_phy_dm (mux_phy_dm),
.mux_phy_rdata_en (mux_phy_rdata_en),
.mux_phy_rdata_en_full (mux_phy_rdata_en_full),
.phy_mux_rdata (phy_mux_rdata),
.phy_mux_read_fifo_q (phy_mux_read_fifo_q),
.phy_mux_rdata_valid (phy_mux_rdata_valid)
);
defparam uafi_mux.AFI_ADDRESS_WIDTH = AFI_ADDRESS_WIDTH;
defparam uafi_mux.AFI_BANK_WIDTH = AFI_BANK_WIDTH;
defparam uafi_mux.AFI_CHIP_SELECT_WIDTH = AFI_CHIP_SELECT_WIDTH;
defparam uafi_mux.AFI_CLK_EN_WIDTH = AFI_CLK_EN_WIDTH;
defparam uafi_mux.AFI_ODT_WIDTH = AFI_ODT_WIDTH;
defparam uafi_mux.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam uafi_mux.AFI_DQS_WIDTH = AFI_DQS_WIDTH;
defparam uafi_mux.AFI_DATA_MASK_WIDTH = AFI_DATA_MASK_WIDTH;
defparam uafi_mux.AFI_CONTROL_WIDTH = AFI_CONTROL_WIDTH;
defparam uafi_mux.AFI_DATA_WIDTH = AFI_DATA_WIDTH;
// ********************************************************************************************************************************
// The address and command datapath is responsible for adding any flop stages/extra logic that may be required between the AFI
// interface and the output DDIOs.
// ********************************************************************************************************************************
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_addr_cmd_datapath uaddr_cmd_datapath(
.clk (pll_addr_cmd_clk),
.reset_n (reset_n_afi_clk[1]),
.afi_address (mux_phy_address),
.afi_bank (mux_phy_bank),
.afi_cs_n (mux_phy_cs_n),
.afi_cke (mux_phy_cke),
.afi_odt (mux_phy_odt),
.afi_ras_n (mux_phy_ras_n),
.afi_cas_n (mux_phy_cas_n),
.afi_we_n (mux_phy_we_n),
.afi_rst_n (mux_phy_reset_n),
.phy_ddio_address (phy_ddio_address),
.phy_ddio_bank (phy_ddio_bank),
.phy_ddio_cs_n (phy_ddio_cs_n),
.phy_ddio_cke (phy_ddio_cke),
.phy_ddio_we_n (phy_ddio_we_n),
.phy_ddio_ras_n (phy_ddio_ras_n),
.phy_ddio_cas_n (phy_ddio_cas_n),
.phy_ddio_reset_n (phy_ddio_reset_n),
.phy_ddio_odt (phy_ddio_odt)
);
defparam uaddr_cmd_datapath.MEM_ADDRESS_WIDTH = MEM_ADDRESS_WIDTH;
defparam uaddr_cmd_datapath.MEM_BANK_WIDTH = MEM_BANK_WIDTH;
defparam uaddr_cmd_datapath.MEM_CHIP_SELECT_WIDTH = MEM_CHIP_SELECT_WIDTH;
defparam uaddr_cmd_datapath.MEM_CLK_EN_WIDTH = MEM_CLK_EN_WIDTH;
defparam uaddr_cmd_datapath.MEM_ODT_WIDTH = MEM_ODT_WIDTH;
defparam uaddr_cmd_datapath.MEM_DM_WIDTH = MEM_DM_WIDTH;
defparam uaddr_cmd_datapath.MEM_CONTROL_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_datapath.MEM_DQ_WIDTH = MEM_DQ_WIDTH;
defparam uaddr_cmd_datapath.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam uaddr_cmd_datapath.MEM_WRITE_DQS_WIDTH = MEM_WRITE_DQS_WIDTH;
defparam uaddr_cmd_datapath.AFI_ADDRESS_WIDTH = AFI_ADDRESS_WIDTH;
defparam uaddr_cmd_datapath.AFI_BANK_WIDTH = AFI_BANK_WIDTH;
defparam uaddr_cmd_datapath.AFI_CHIP_SELECT_WIDTH = AFI_CHIP_SELECT_WIDTH;
defparam uaddr_cmd_datapath.AFI_CLK_EN_WIDTH = AFI_CLK_EN_WIDTH;
defparam uaddr_cmd_datapath.AFI_ODT_WIDTH = AFI_ODT_WIDTH;
defparam uaddr_cmd_datapath.AFI_DATA_MASK_WIDTH = AFI_DATA_MASK_WIDTH;
defparam uaddr_cmd_datapath.AFI_CONTROL_WIDTH = AFI_CONTROL_WIDTH;
defparam uaddr_cmd_datapath.AFI_DATA_WIDTH = AFI_DATA_WIDTH;
defparam uaddr_cmd_datapath.NUM_AC_FR_CYCLE_SHIFTS = NUM_AC_FR_CYCLE_SHIFTS;
// ********************************************************************************************************************************
// The write datapath is responsible for adding any flop stages/extra logic that may be required between the AFI interface
// and the output DDIOs.
// ********************************************************************************************************************************
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_write_datapath uwrite_datapath(
.pll_afi_clk (pll_afi_clk),
.reset_n (reset_n_afi_clk[2]),
.force_oct_off (force_oct_off),
.phy_ddio_oct_ena (phy_ddio_oct_ena),
.afi_dqs_en (mux_phy_dqs_en),
.afi_wdata (mux_phy_wdata),
.afi_wdata_valid (mux_phy_wdata_valid),
.afi_dm (mux_phy_dm),
.phy_ddio_dq (phy_ddio_dq),
.phy_ddio_dqs_en (phy_ddio_dqs_en),
.phy_ddio_wrdata_en (phy_ddio_wrdata_en),
.phy_ddio_wrdata_mask (phy_ddio_wrdata_mask)
);
defparam uwrite_datapath.MEM_ADDRESS_WIDTH = MEM_ADDRESS_WIDTH;
defparam uwrite_datapath.MEM_DM_WIDTH = MEM_DM_WIDTH;
defparam uwrite_datapath.MEM_CONTROL_WIDTH = MEM_CONTROL_WIDTH;
defparam uwrite_datapath.MEM_DQ_WIDTH = MEM_DQ_WIDTH;
defparam uwrite_datapath.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam uwrite_datapath.MEM_WRITE_DQS_WIDTH = MEM_WRITE_DQS_WIDTH;
defparam uwrite_datapath.AFI_ADDRESS_WIDTH = AFI_ADDRESS_WIDTH;
defparam uwrite_datapath.AFI_DATA_MASK_WIDTH = AFI_DATA_MASK_WIDTH;
defparam uwrite_datapath.AFI_CONTROL_WIDTH = AFI_CONTROL_WIDTH;
defparam uwrite_datapath.AFI_DATA_WIDTH = AFI_DATA_WIDTH;
defparam uwrite_datapath.AFI_DQS_WIDTH = AFI_DQS_WIDTH;
defparam uwrite_datapath.NUM_WRITE_PATH_FLOP_STAGES = NUM_WRITE_PATH_FLOP_STAGES;
// ********************************************************************************************************************************
// The read datapath is responsible for read data resynchronization from the memory clock domain to the AFI clock domain.
// It contains 1 FIFO per DQS group for read valid prediction and 1 FIFO per DQS group for read data synchronization.
// ********************************************************************************************************************************
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_read_datapath uread_datapath(
.reset_n_afi_clk (reset_n_afi_clk[3]),
.reset_n_resync_clk (reset_n_resync_clk),
.seq_read_fifo_reset (seq_read_fifo_reset),
.pll_afi_clk (pll_afi_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.read_capture_clk (read_capture_clk),
.ddio_phy_dq (ddio_phy_dq),
.seq_read_latency_counter (seq_read_latency_counter),
.seq_read_increment_vfifo_fr (seq_read_increment_vfifo_fr),
.seq_read_increment_vfifo_hr (seq_read_increment_vfifo_hr),
.seq_read_increment_vfifo_qr (seq_read_increment_vfifo_qr),
.force_oct_off (force_oct_off),
.dqs_enable_ctrl (dqs_enable_ctrl),
.afi_rdata_en (mux_phy_rdata_en),
.afi_rdata_en_full (mux_phy_rdata_en_full),
.afi_rdata (phy_mux_rdata),
.phy_mux_read_fifo_q (phy_mux_read_fifo_q),
.afi_rdata_valid (phy_mux_rdata_valid),
.seq_calib_init (seq_calib_init_reg),
.dqs_edge_detect (dqs_edge_detect)
);
defparam uread_datapath.DEVICE_FAMILY = DEVICE_FAMILY;
defparam uread_datapath.MEM_ADDRESS_WIDTH = MEM_ADDRESS_WIDTH;
defparam uread_datapath.MEM_DM_WIDTH = MEM_DM_WIDTH;
defparam uread_datapath.MEM_CONTROL_WIDTH = MEM_CONTROL_WIDTH;
defparam uread_datapath.MEM_DQ_WIDTH = MEM_DQ_WIDTH;
defparam uread_datapath.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam uread_datapath.MEM_WRITE_DQS_WIDTH = MEM_WRITE_DQS_WIDTH;
defparam uread_datapath.AFI_ADDRESS_WIDTH = AFI_ADDRESS_WIDTH;
defparam uread_datapath.AFI_DATA_MASK_WIDTH = AFI_DATA_MASK_WIDTH;
defparam uread_datapath.AFI_CONTROL_WIDTH = AFI_CONTROL_WIDTH;
defparam uread_datapath.AFI_DATA_WIDTH = AFI_DATA_WIDTH;
defparam uread_datapath.AFI_DQS_WIDTH = AFI_DQS_WIDTH;
defparam uread_datapath.MAX_LATENCY_COUNT_WIDTH = MAX_LATENCY_COUNT_WIDTH;
defparam uread_datapath.MAX_READ_LATENCY = MAX_READ_LATENCY;
defparam uread_datapath.READ_FIFO_READ_MEM_DEPTH = READ_FIFO_READ_MEM_DEPTH;
defparam uread_datapath.READ_FIFO_READ_ADDR_WIDTH = READ_FIFO_READ_ADDR_WIDTH;
defparam uread_datapath.READ_FIFO_WRITE_MEM_DEPTH = READ_FIFO_WRITE_MEM_DEPTH;
defparam uread_datapath.READ_FIFO_WRITE_ADDR_WIDTH = READ_FIFO_WRITE_ADDR_WIDTH;
defparam uread_datapath.READ_VALID_FIFO_SIZE = READ_VALID_FIFO_SIZE;
defparam uread_datapath.READ_VALID_FIFO_READ_MEM_DEPTH = READ_VALID_FIFO_READ_MEM_DEPTH;
defparam uread_datapath.READ_VALID_FIFO_READ_ADDR_WIDTH = READ_VALID_FIFO_READ_ADDR_WIDTH;
defparam uread_datapath.READ_VALID_FIFO_WRITE_MEM_DEPTH = READ_VALID_FIFO_WRITE_MEM_DEPTH;
defparam uread_datapath.READ_VALID_FIFO_WRITE_ADDR_WIDTH = READ_VALID_FIFO_WRITE_ADDR_WIDTH;
defparam uread_datapath.READ_VALID_FIFO_PER_DQS_WIDTH = READ_VALID_FIFO_PER_DQS_WIDTH;
defparam uread_datapath.NUM_SUBGROUP_PER_READ_DQS = NUM_SUBGROUP_PER_READ_DQS;
defparam uread_datapath.MEM_T_RL = MEM_T_RL;
defparam uread_datapath.CALIB_REG_WIDTH = CALIB_REG_WIDTH;
defparam uread_datapath.QVLD_EXTRA_FLOP_STAGES = QVLD_EXTRA_FLOP_STAGES;
defparam uread_datapath.QVLD_WR_ADDRESS_OFFSET = QVLD_WR_ADDRESS_OFFSET;
defparam uread_datapath.FAST_SIM_MODEL = FAST_SIM_MODEL;
// ********************************************************************************************************************************
// The I/O block is responsible for instantiating all the built-in I/O logic in the FPGA
// ********************************************************************************************************************************
ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_new_io_pads uio_pads (
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
.reset_n_afi_clk (reset_n_afi_clk[1]),
.oct_ctl_rs_value (oct_ctl_rs_value),
.oct_ctl_rt_value (oct_ctl_rt_value),
// Address and Command
.phy_ddio_addr_cmd_clk (pll_addr_cmd_clk),
.phy_ddio_address (phy_ddio_address),
.phy_ddio_bank (phy_ddio_bank),
.phy_ddio_cs_n (phy_ddio_cs_n),
.phy_ddio_cke (phy_ddio_cke),
.phy_ddio_odt (phy_ddio_odt),
.phy_ddio_we_n (phy_ddio_we_n),
.phy_ddio_ras_n (phy_ddio_ras_n),
.phy_ddio_cas_n (phy_ddio_cas_n),
.phy_ddio_reset_n (phy_ddio_reset_n),
.phy_mem_address (mem_a),
.phy_mem_bank (mem_ba),
.phy_mem_cs_n (mem_cs_n),
.phy_mem_cke (mem_cke),
.phy_mem_odt (mem_odt),
.phy_mem_we_n (mem_we_n),
.phy_mem_ras_n (mem_ras_n),
.phy_mem_cas_n (mem_cas_n),
.phy_mem_reset_n (mem_reset_n),
// Write
.pll_afi_clk (pll_afi_clk),
.pll_mem_clk (pll_mem_clk),
.pll_write_clk (pll_write_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.phy_ddio_dq (phy_ddio_dq),
.phy_ddio_dqs_en (phy_ddio_dqs_en),
.phy_ddio_oct_ena (phy_ddio_oct_ena),
.dqs_enable_ctrl (dqs_enable_ctrl),
.phy_ddio_wrdata_en (phy_ddio_wrdata_en),
.phy_ddio_wrdata_mask (phy_ddio_wrdata_mask),
.phy_mem_dq (mem_dq),
.phy_mem_dm (mem_dm),
.phy_mem_ck (mem_ck),
.phy_mem_ck_n (mem_ck_n),
.mem_dqs (mem_dqs),
.mem_dqs_n (mem_dqs_n),
// Read
.dll_phy_delayctrl (dll_phy_delayctrl),
.ddio_phy_dq (ddio_phy_dq),
.read_capture_clk (read_capture_clk)
,
.scc_clk (pll_config_clk),
.scc_data (scc_data),
.scc_dqs_ena (scc_dqs_ena),
.scc_dqs_io_ena (scc_dqs_io_ena),
.scc_dq_ena (scc_dq_ena),
.scc_dm_ena (scc_dm_ena),
.scc_upd (scc_upd),
.capture_strobe_tracking(capture_strobe_tracking)
);
defparam uio_pads.DEVICE_FAMILY = DEVICE_FAMILY;
defparam uio_pads.OCT_SERIES_TERM_CONTROL_WIDTH = OCT_SERIES_TERM_CONTROL_WIDTH;
defparam uio_pads.OCT_PARALLEL_TERM_CONTROL_WIDTH = OCT_PARALLEL_TERM_CONTROL_WIDTH;
defparam uio_pads.MEM_ADDRESS_WIDTH = MEM_ADDRESS_WIDTH;
defparam uio_pads.MEM_BANK_WIDTH = MEM_BANK_WIDTH;
defparam uio_pads.MEM_CHIP_SELECT_WIDTH = MEM_CHIP_SELECT_WIDTH;
defparam uio_pads.MEM_CLK_EN_WIDTH = MEM_CLK_EN_WIDTH;
defparam uio_pads.MEM_CK_WIDTH = MEM_CK_WIDTH;
defparam uio_pads.MEM_ODT_WIDTH = MEM_ODT_WIDTH;
defparam uio_pads.MEM_DQS_WIDTH = MEM_DQS_WIDTH;
defparam uio_pads.MEM_DM_WIDTH = MEM_DM_WIDTH;
defparam uio_pads.MEM_CONTROL_WIDTH = MEM_CONTROL_WIDTH;
defparam uio_pads.MEM_DQ_WIDTH = MEM_DQ_WIDTH;
defparam uio_pads.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam uio_pads.MEM_WRITE_DQS_WIDTH = MEM_WRITE_DQS_WIDTH;
defparam uio_pads.AFI_ADDRESS_WIDTH = AFI_ADDRESS_WIDTH;
defparam uio_pads.AFI_BANK_WIDTH = AFI_BANK_WIDTH;
defparam uio_pads.AFI_CHIP_SELECT_WIDTH = AFI_CHIP_SELECT_WIDTH;
defparam uio_pads.AFI_CLK_EN_WIDTH = AFI_CLK_EN_WIDTH;
defparam uio_pads.AFI_ODT_WIDTH = AFI_ODT_WIDTH;
defparam uio_pads.AFI_DATA_MASK_WIDTH = AFI_DATA_MASK_WIDTH;
defparam uio_pads.AFI_CONTROL_WIDTH = AFI_CONTROL_WIDTH;
defparam uio_pads.AFI_DATA_WIDTH = AFI_DATA_WIDTH;
defparam uio_pads.AFI_DQS_WIDTH = AFI_DQS_WIDTH;
defparam uio_pads.DLL_DELAY_CTRL_WIDTH = DLL_DELAY_CTRL_WIDTH;
defparam uio_pads.DQS_ENABLE_CTRL_WIDTH = READ_VALID_FIFO_WIDTH;
defparam uio_pads.ALTDQDQS_INPUT_FREQ = ALTDQDQS_INPUT_FREQ;
defparam uio_pads.ALTDQDQS_DELAY_CHAIN_BUFFER_MODE = ALTDQDQS_DELAY_CHAIN_BUFFER_MODE;
defparam uio_pads.ALTDQDQS_DQS_PHASE_SETTING = ALTDQDQS_DQS_PHASE_SETTING;
defparam uio_pads.ALTDQDQS_DQS_PHASE_SHIFT = ALTDQDQS_DQS_PHASE_SHIFT;
defparam uio_pads.ALTDQDQS_DELAYED_CLOCK_PHASE_SETTING = ALTDQDQS_DELAYED_CLOCK_PHASE_SETTING;
defparam uio_pads.FAST_SIM_MODEL = FAST_SIM_MODEL;
assign csr_soft_reset_req = 1'b0;
// Calculate the ceiling of log_2 of the input value
function integer ceil_log2;
input integer value;
begin
value = value - 1;
for (ceil_log2 = 0; value > 0; ceil_log2 = ceil_log2 + 1)
value = value >> 1;
end
endfunction
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
//
// This file is part of the N64 RGB/YPbPr DAC project.
//
// Copyright (C) 2015-2021 by Peter Bartmann <[email protected]>
//
// N64 RGB/YPbPr DAC is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//////////////////////////////////////////////////////////////////////////////////
//
// Company: Circuit-Board.de
// Engineer: borti4938
//
// Module Name: register_sync
// Project Name: N64 Advanced RGB/YPbPr DAC Mod
// Target Devices: universial
// Tool versions: Altera Quartus Prime
// Description: generates a reset signal (low-active by default) with duration of
// two clock cycles
//
//////////////////////////////////////////////////////////////////////////////////
module register_sync #(
parameter reg_width = 16,
parameter reg_preset = {reg_width{1'b0}},
parameter resync_stages = 2
) (
clk,
clk_en,
nrst,
reg_i,
reg_o
);
input clk;
input clk_en;
input nrst;
input [reg_width-1:0] reg_i;
output [reg_width-1:0] reg_o;
reg [reg_width-1:0] reg_synced_3 = reg_preset;
reg [reg_width-1:0] reg_synced_2 = reg_preset;
reg [reg_width-1:0] reg_synced_1 = reg_preset;
reg [reg_width-1:0] reg_synced_0 = reg_preset;
always @(posedge clk or negedge nrst)
if (!nrst) begin
reg_synced_2 <= reg_preset;
reg_synced_1 <= reg_preset;
reg_synced_0 <= reg_preset;
end else if (clk_en) begin
reg_synced_2 <= reg_synced_1;
reg_synced_1 <= reg_synced_0;
reg_synced_0 <= reg_i;
end
genvar int_idx;
generate
for (int_idx = 0; int_idx < reg_width; int_idx = int_idx+1) begin : gen_rtl
always @(posedge clk or negedge nrst)
if (!nrst) begin
reg_synced_3[int_idx] <= reg_preset[int_idx];
end else if (clk_en) begin
if (reg_synced_2[int_idx] == reg_synced_1[int_idx])
reg_synced_3[int_idx] <= reg_synced_2[int_idx];
end
end
endgenerate
generate
if (resync_stages == 4)
assign reg_o = reg_synced_3;
else if (resync_stages == 3)
assign reg_o = reg_synced_2;
else if (resync_stages == 1)
assign reg_o = reg_synced_0;
else
assign reg_o = reg_synced_1;
endgenerate
endmodule
|
`include "project_defines.v"
module seeed_tft #(
parameter BUFFER_SIZE = 12
)(
input rst,
input clk,
output [31:0] debug,
input i_soft_tearing,
input [7:0] i_tearing_reg,
input [31:0] i_tearing_value,
input [31:0] i_tearing_count,
input [7:0] i_mem_write_cmd,
input i_tearing_polarity,
//Control Signals
input i_enable,
input i_reset_display,
input i_data_command_mode,
input i_enable_tearing,
input i_cmd_rs,
input i_cmd_write_stb,
input i_cmd_read_stb,
input [7:0] i_cmd_data,
output [7:0] o_cmd_data,
output o_cmd_finished,
input i_backlight_enable,
input i_chip_select,
input [31:0] i_num_pixels,
//FIFO Signals
output [1:0] o_fifo_rdy,
input [1:0] i_fifo_act,
input i_fifo_stb,
output [23:0] o_fifo_size,
input [31:0] i_fifo_data,
//Physical Signals
output o_backlight_enable,
output o_register_data_sel,
output o_write_n,
output o_read_n,
inout [7:0] io_data,
output o_cs_n,
output o_reset_n,
input i_tearing_effect,
output o_display_on
);
//Local Parameters
//Registers/Wires
wire [7:0] w_data_out;
wire [7:0] w_data_in;
wire w_cmd_write;
wire w_cmd_read;
wire [7:0] w_cmd_data;
wire w_cmd_cmd_mode;
wire w_cmd_data_out_en;
wire w_data_dir;
wire w_data_chip_select;
wire w_data_cmd_mode;
wire [7:0] w_data_data;
wire w_data_write;
wire w_data_read;
wire w_data_data_out_en;
//Submodules
seeed_tft_command lcd_commander (
.rst (rst ),
.clk (clk ),
// .debug (debug ),
.i_enable (i_enable ),
.i_cmd_rs (i_cmd_rs ),
.i_cmd_write_stb (i_cmd_write_stb ),
.i_cmd_read_stb (i_cmd_read_stb ),
.i_cmd_data (i_cmd_data ),
.o_cmd_data (o_cmd_data ),
//Control Signals
.o_data_out_en (w_cmd_data_out_en ),
.o_cmd_finished (o_cmd_finished ),
.o_cmd_mode (w_cmd_cmd_mode ),
.o_write (w_cmd_write ),
.o_read (w_cmd_read ),
.o_data_out (w_cmd_data ),
.i_data_in (w_data_in )
);
seeed_tft_data_writer #(
.BUFFER_SIZE (BUFFER_SIZE )
)lcd_data_writer(
.rst (rst ),
.clk (clk ),
.debug (debug ),
.i_soft_tearing (i_soft_tearing ),
.i_tearing_reg (i_tearing_reg ),
.i_tearing_value (i_tearing_value ),
.i_tearing_count (i_tearing_count ),
.i_mem_write_cmd (i_mem_write_cmd ),
.i_tearing_polarity (i_tearing_polarity ),
.i_enable (i_enable ),
.i_enable_tearing (i_enable_tearing ),
.i_num_pixels (i_num_pixels ),
.o_fifo_rdy (o_fifo_rdy ),
.i_fifo_act (i_fifo_act ),
.i_fifo_stb (i_fifo_stb ),
.o_fifo_size (o_fifo_size ),
.i_fifo_data (i_fifo_data ),
.i_tearing_effect (i_tearing_effect ),
.o_chip_select (w_data_chip_select ),
.o_cmd_mode (w_data_cmd_mode ),
.o_data_out (w_data_data ),
.i_data_in (w_data_in ),
.o_write (w_data_write ),
.o_read (w_data_read ),
.o_data_out_en (w_data_data_out_en )
);
//Asynchronous Logic
assign o_backlight_enable = i_backlight_enable;
assign o_display_on = i_enable;
assign o_reset_n = ~i_reset_display;
assign w_data_in = io_data;
//Select control between the Command controller and the Data Controller
assign o_cs_n = (i_data_command_mode) ? ~w_data_chip_select : ~i_chip_select;
assign o_register_data_sel = (i_data_command_mode) ? w_data_cmd_mode : w_cmd_cmd_mode;
assign o_write_n = (i_data_command_mode) ? ~w_data_write : ~w_cmd_write;
assign o_read_n = (i_data_command_mode) ? ~w_data_read : ~w_cmd_read;
assign w_data_dir = (i_data_command_mode) ? w_data_data_out_en : w_cmd_data_out_en;
assign io_data = (w_data_dir) ? (i_data_command_mode) ?
w_data_data : w_cmd_data :
8'hZZ;
//Synchronous Logic
endmodule
|
// -----------------------------------------------------------------------
//
// Copyright 2003 H. Peter Anvin - All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, Inc., 53 Temple Place Ste 330,
// Bostom MA 02111-1307, USA; either version 2 of the License, or
// (at your option) any later version; incorporated herein by reference.
//
// -----------------------------------------------------------------------
// Kindly provided by H. Peter Anvin
`timescale 1ns/10ps
module hexledx (input wire [3:0] value,
input wire blank,
input wire minus,
output reg [6:0] s7);
always @*
if (blank)
s7 = ~7'b0000000;
else if ( minus )
s7 = ~7'b1000000;
else case (value)
4'h0: s7 = ~7'b0111111;
4'h1: s7 = ~7'b0000110;
4'h2: s7 = ~7'b1011011;
4'h3: s7 = ~7'b1001111;
4'h4: s7 = ~7'b1100110;
4'h5: s7 = ~7'b1101101;
4'h6: s7 = ~7'b1111101;
4'h7: s7 = ~7'b0000111;
4'h8: s7 = ~7'b1111111;
4'h9: s7 = ~7'b1101111;
4'hA: s7 = ~7'b1110111;
4'hB: s7 = ~7'b1111100;
4'hC: s7 = ~7'b0111001;
4'hD: s7 = ~7'b1011110;
4'hE: s7 = ~7'b1111001;
4'hF: s7 = ~7'b1110001;
endcase
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tb_pixelfeed();
reg sys_clk;
initial sys_clk = 1'b0;
always #5 sys_clk = ~sys_clk;
reg sys_rst;
reg vga_rst;
wire pixel_valid;
wire fml_stb;
wire [25:0] fml_adr;
initial begin
sys_rst = 1'b1;
vga_rst = 1'b1;
#20 sys_rst = 1'b0;
#20 vga_rst = 1'b0;
end
vgafb_pixelfeed dut(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.vga_rst(vga_rst),
.nbursts(18'd100),
.baseaddress(26'd1024),
.baseaddress_ack(),
.fml_adr(fml_adr),
.fml_stb(fml_stb),
.fml_ack(fml_stb),
.fml_di(64'hcafebabedeadbeef),
.pixel_valid(pixel_valid),
.pixel(),
.pixel_ack(pixel_valid)
);
always @(posedge sys_clk) $display("%x", fml_adr);
initial #600 $finish;
endmodule
|
/*===========================================================================*/
/* Copyright (C) 2001 Authors */
/* */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer. */
/* */
/* This source file is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU Lesser General Public License as published */
/* by the Free Software Foundation; either version 2.1 of the License, or */
/* (at your option) any later version. */
/* */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
/* License for more details. */
/* */
/* You should have received a copy of the GNU Lesser General Public License */
/* along with this source; if not, write to the Free Software Foundation, */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* DHRYSTONE V2.1 */
/*---------------------------------------------------------------------------*/
/* */
/* Author(s): */
/* - Olivier Girard, [email protected] */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 19 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
`define NO_TIMEOUT
time mclk_start_time, mclk_end_time;
real mclk_period, mclk_frequency;
time dhry_start_time, dhry_end_time;
real dhry_per_sec, dhry_mips, dhry_mips_per_mhz;
integer Number_Of_Runs;
initial
begin
$display(" ===============================================");
$display("| START SIMULATION |");
$display(" ===============================================");
// Disable automatic DMA verification
#10;
dma_verif_on = 0;
repeat(5) @(posedge mclk);
stimulus_done = 0;
//---------------------------------------
// Check CPU configuration
//---------------------------------------
if ((`PMEM_SIZE !== 49152) || (`DMEM_SIZE !== 10240))
begin
$display(" ===============================================");
$display("| SIMULATION ERROR |");
$display("| |");
$display("| Core must be configured for: |");
$display("| - 48kB program memory |");
$display("| - 10kB data memory |");
$display(" ===============================================");
$finish;
end
// Disable watchdog
// (only required because RedHat/TI GCC toolchain doesn't disable watchdog properly at startup)
`ifdef WATCHDOG
force dut.watchdog_0.wdtcnt = 16'h0000;
`endif
//---------------------------------------
// Number of benchmark iteration
// (Must match the C-code value)
//---------------------------------------
Number_Of_Runs = 100;
//---------------------------------------
// Measure clock period
//---------------------------------------
repeat(100) @(posedge mclk);
$timeformat(-9, 3, " ns", 10);
@(posedge mclk);
mclk_start_time = $time;
@(posedge mclk);
mclk_end_time = $time;
@(posedge mclk);
mclk_period = mclk_end_time-mclk_start_time;
mclk_frequency = 1000/mclk_period;
$display("\nINFO-VERILOG: openMSP430 System clock frequency %f MHz\n", mclk_frequency);
//---------------------------------------
// Measure Dhrystone run time
//---------------------------------------
// Detect beginning of run
@(posedge p3_dout[0]);
dhry_start_time = $time;
$timeformat(-3, 3, " ms", 10);
$display("\nINFO-VERILOG: Dhrystone loop started at %t ", dhry_start_time);
$display("");
$display("INFO-VERILOG: Be patient... there could be up to 16ms to simulate");
$display("");
// Detect end of run
@(negedge p3_dout[0]);
dhry_end_time = $time;
$timeformat(-3, 3, " ms", 10);
$display("INFO-VERILOG: Dhrystone loop ended at %t ", dhry_end_time);
// Compute results
$timeformat(-9, 3, " ns", 10);
dhry_per_sec = (Number_Of_Runs*1000000000)/(dhry_end_time - dhry_start_time);
dhry_mips = dhry_per_sec / 1757;
dhry_mips_per_mhz = dhry_mips / mclk_frequency;
// Report results
$display("\INFO-VERILOG: Dhrystone per second : %f", dhry_per_sec);
$display("\INFO-VERILOG: DMIPS : %f", dhry_mips);
$display("\INFO-VERILOG: DMIPS/MHz : %f\n", dhry_mips_per_mhz);
//---------------------------------------
// Wait for the end of C-code execution
//---------------------------------------
@(posedge p4_dout[0]);
stimulus_done = 1;
$display(" ===============================================");
$display("| SIMULATION DONE |");
$display("| (stopped through verilog stimulus) |");
$display(" ===============================================");
$finish;
end
// Display stuff from the C-program
always @(p2_dout[0])
begin
$write("%s", p1_dout);
$fflush();
end
// Display some info to show simulation progress
initial
begin
@(posedge p3_dout[0]);
#1000000;
while (p3_dout[0])
begin
$display("INFO-VERILOG: Simulated time %t ", $time);
#1000000;
end
end
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__BUFINV_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__BUFINV_PP_BLACKBOX_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__bufinv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__BUFINV_PP_BLACKBOX_V
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module bus_to_ip
#(
parameter BASEADDR = 0,
parameter HIGHADDR = 0,
parameter ABUSWIDTH = 16,
parameter DBUSWIDTH = 8
)
(
input wire BUS_RD,
input wire BUS_WR,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [DBUSWIDTH-1:0] BUS_DATA,
output wire IP_RD,
output wire IP_WR,
output wire [ABUSWIDTH-1:0] IP_ADD,
output wire [DBUSWIDTH-1:0] IP_DATA_IN,
input wire [DBUSWIDTH-1:0] IP_DATA_OUT
);
wire CS;
/* verilator lint_off UNSIGNED */
assign CS = (BUS_ADD >= BASEADDR && BUS_ADD <= HIGHADDR);
/* verilator lint_on UNSIGNED */
assign IP_ADD = CS ? BUS_ADD - BASEADDR : {ABUSWIDTH{1'b0}};
assign IP_RD = CS ? BUS_RD : 1'b0;
assign IP_WR = CS ? BUS_WR: 1'b0;
assign IP_DATA_IN = BUS_DATA;
assign BUS_DATA = (CS && BUS_WR) ? {DBUSWIDTH{1'bz}} : (CS ? IP_DATA_OUT : {DBUSWIDTH{1'bz}});
endmodule
|
// generated by gen_VerilogEHR.py using VerilogEHR.mako
// Copyright (c) 2019 Massachusetts Institute of Technology
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
module EHR_2 (
CLK,
RST_N,
read_0,
write_0,
EN_write_0,
read_1,
write_1,
EN_write_1
);
parameter DATA_SZ = 1;
parameter RESET_VAL = 0;
input CLK;
input RST_N;
output [DATA_SZ-1:0] read_0;
input [DATA_SZ-1:0] write_0;
input EN_write_0;
output [DATA_SZ-1:0] read_1;
input [DATA_SZ-1:0] write_1;
input EN_write_1;
reg [DATA_SZ-1:0] r;
wire [DATA_SZ-1:0] wire_0;
wire [DATA_SZ-1:0] wire_1;
wire [DATA_SZ-1:0] wire_2;
assign wire_0 = r;
assign wire_1 = EN_write_0 ? write_0 : wire_0;
assign wire_2 = EN_write_1 ? write_1 : wire_1;
assign read_0 = wire_0;
assign read_1 = wire_1;
always @(posedge CLK) begin
if (RST_N == 0) begin
r <= RESET_VAL;
end else begin
r <= wire_2;
end
end
endmodule
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Space_Vector_Modulation.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Space_Vector_Modulation
// Source Path: velocityControlHdl/Space_Vector_Modulation
// Hierarchy Level: 4
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Space_Vector_Modulation
(
Vabc_Raw_0,
Vabc_Raw_1,
Vabc_Raw_2,
phase_voltages_0,
phase_voltages_1,
phase_voltages_2
);
input signed [17:0] Vabc_Raw_0; // sfix18_En13
input signed [17:0] Vabc_Raw_1; // sfix18_En13
input signed [17:0] Vabc_Raw_2; // sfix18_En13
output signed [19:0] phase_voltages_0; // sfix20_En12
output signed [19:0] phase_voltages_1; // sfix20_En12
output signed [19:0] phase_voltages_2; // sfix20_En12
wire signed [17:0] Double_Range_out1_0; // sfix18_En12
wire signed [17:0] Double_Range_out1_1; // sfix18_En12
wire signed [17:0] Double_Range_out1_2; // sfix18_En12
wire signed [17:0] MinMax1_out1; // sfix18_En12
wire signed [17:0] MinMax_out1; // sfix18_En12
wire signed [18:0] Add_add_cast; // sfix19_En12
wire signed [18:0] Add_add_cast_1; // sfix19_En12
wire signed [18:0] Add_out1; // sfix19_En12
wire signed [37:0] Gain_cast; // sfix38_En30
wire signed [18:0] Gain_out1; // sfix19_En12
wire signed [19:0] Add1_sub_cast; // sfix20_En12
wire signed [19:0] Add1_sub_cast_1; // sfix20_En12
wire signed [19:0] Add1_out1; // sfix20_En12
wire signed [19:0] Add2_sub_cast; // sfix20_En12
wire signed [19:0] Add2_sub_cast_1; // sfix20_En12
wire signed [19:0] Add2_out1; // sfix20_En12
wire signed [19:0] Add3_sub_cast; // sfix20_En12
wire signed [19:0] Add3_sub_cast_1; // sfix20_En12
wire signed [19:0] Add3_out1; // sfix20_En12
// <S4>/Double_Range
//
// <S4>/Demux
//
// <S4>/Goto
//
// <S4>/From
//
// <S4>/Goto1
//
// <S4>/From1
//
// <S4>/Goto2
//
// <S4>/From2
//
// <S4>/Demux
//
// <S4>/Goto
//
// <S4>/From6
//
// <S4>/Demux
//
// <S4>/Goto
//
// <S4>/From3
//
// <S4>/Goto1
//
// <S4>/From7
//
// <S4>/Goto1
//
// <S4>/From4
//
// <S4>/Goto2
//
// <S4>/From8
//
// <S4>/Goto2
//
// <S4>/From5
velocityControlHdl_Double_Range u_Double_Range (.In1_0(Vabc_Raw_0), // sfix18_En13
.In1_1(Vabc_Raw_1), // sfix18_En13
.In1_2(Vabc_Raw_2), // sfix18_En13
.Out1_0(Double_Range_out1_0), // sfix18_En12
.Out1_1(Double_Range_out1_1), // sfix18_En12
.Out1_2(Double_Range_out1_2) // sfix18_En12
);
// <S4>/MinMax1
velocityControlHdl_MinMax1 u_MinMax1 (.in0(Double_Range_out1_0), // sfix18_En12
.in1(Double_Range_out1_1), // sfix18_En12
.in2(Double_Range_out1_2), // sfix18_En12
.out0(MinMax1_out1) // sfix18_En12
);
// <S4>/MinMax
velocityControlHdl_MinMax u_MinMax (.in0(Double_Range_out1_0), // sfix18_En12
.in1(Double_Range_out1_1), // sfix18_En12
.in2(Double_Range_out1_2), // sfix18_En12
.out0(MinMax_out1) // sfix18_En12
);
// <S4>/Add
assign Add_add_cast = MinMax1_out1;
assign Add_add_cast_1 = MinMax_out1;
assign Add_out1 = Add_add_cast + Add_add_cast_1;
// <S4>/Gain
assign Gain_cast = {{2{Add_out1[18]}}, {Add_out1, 17'b00000000000000000}};
assign Gain_out1 = Gain_cast[36:18];
// <S4>/Add1
//
// <S4>/Mux
assign Add1_sub_cast = Double_Range_out1_0;
assign Add1_sub_cast_1 = Gain_out1;
assign Add1_out1 = Add1_sub_cast - Add1_sub_cast_1;
assign phase_voltages_0 = Add1_out1;
// <S4>/Add2
assign Add2_sub_cast = Double_Range_out1_1;
assign Add2_sub_cast_1 = Gain_out1;
assign Add2_out1 = Add2_sub_cast - Add2_sub_cast_1;
assign phase_voltages_1 = Add2_out1;
// <S4>/Add3
assign Add3_sub_cast = Double_Range_out1_2;
assign Add3_sub_cast_1 = Gain_out1;
assign Add3_out1 = Add3_sub_cast - Add3_sub_cast_1;
assign phase_voltages_2 = Add3_out1;
endmodule // velocityControlHdl_Space_Vector_Modulation
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: openMSP430.v
//
// *Module Description:
// openMSP430 Top level file
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 175 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2013-01-30 22:21:42 +0100 (Mit, 30. Jän 2013) $
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module openMSP430 (
// OUTPUTs
aclk, // ASIC ONLY: ACLK
aclk_en, // FPGA ONLY: ACLK enable
dbg_freeze, // Freeze peripherals
dbg_i2c_sda_out, // Debug interface: I2C SDA OUT
dbg_uart_txd, // Debug interface: UART TXD
dco_enable, // ASIC ONLY: Fast oscillator enable
dco_wkup, // ASIC ONLY: Fast oscillator wake-up (asynchronous)
dmem_addr, // Data Memory address
dmem_cen, // Data Memory chip enable (low active)
dmem_din, // Data Memory data input
dmem_wen, // Data Memory write enable (low active)
irq_acc, // Interrupt request accepted (one-hot signal)
lfxt_enable, // ASIC ONLY: Low frequency oscillator enable
lfxt_wkup, // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
mclk, // Main system clock
per_addr, // Peripheral address
per_din, // Peripheral data input
per_we, // Peripheral write enable (high active)
per_en, // Peripheral enable (high active)
pmem_addr, // Program Memory address
pmem_cen, // Program Memory chip enable (low active)
pmem_din, // Program Memory data input (optional)
pmem_wen, // Program Memory write enable (low active) (optional)
puc_rst, // Main system reset
smclk, // ASIC ONLY: SMCLK
smclk_en, // FPGA ONLY: SMCLK enable
// INPUTs
cpu_en, // Enable CPU code execution (asynchronous and non-glitchy)
dbg_en, // Debug interface enable (asynchronous and non-glitchy)
dbg_i2c_addr, // Debug interface: I2C Address
dbg_i2c_broadcast, // Debug interface: I2C Broadcast Address (for multicore systems)
dbg_i2c_scl, // Debug interface: I2C SCL
dbg_i2c_sda_in, // Debug interface: I2C SDA IN
dbg_uart_rxd, // Debug interface: UART RXD (asynchronous)
dco_clk, // Fast oscillator (fast clock)
dmem_dout, // Data Memory data output
irq, // Maskable interrupts
lfxt_clk, // Low frequency oscillator (typ 32kHz)
nmi, // Non-maskable interrupt (asynchronous)
per_dout, // Peripheral data output
pmem_dout, // Program Memory data output
reset_n, // Reset Pin (low active, asynchronous and non-glitchy)
scan_enable, // ASIC ONLY: Scan enable (active during scan shifting)
scan_mode, // ASIC ONLY: Scan mode
wkup // ASIC ONLY: System Wake-up (asynchronous and non-glitchy)
);
// PARAMETERs
//============
parameter INST_NR = 8'h00; // Current oMSP instance number (for multicore systems)
parameter TOTAL_NR = 8'h00; // Total number of oMSP instances-1 (for multicore systems)
// OUTPUTs
//============
output aclk; // ASIC ONLY: ACLK
output aclk_en; // FPGA ONLY: ACLK enable
output dbg_freeze; // Freeze peripherals
output dbg_i2c_sda_out; // Debug interface: I2C SDA OUT
output dbg_uart_txd; // Debug interface: UART TXD
output dco_enable; // ASIC ONLY: Fast oscillator enable
output dco_wkup; // ASIC ONLY: Fast oscillator wake-up (asynchronous)
output [`DMEM_MSB:0] dmem_addr; // Data Memory address
output dmem_cen; // Data Memory chip enable (low active)
output [15:0] dmem_din; // Data Memory data input
output [1:0] dmem_wen; // Data Memory write enable (low active)
output [13:0] irq_acc; // Interrupt request accepted (one-hot signal)
output lfxt_enable; // ASIC ONLY: Low frequency oscillator enable
output lfxt_wkup; // ASIC ONLY: Low frequency oscillator wake-up (asynchronous)
output mclk; // Main system clock
output [13:0] per_addr; // Peripheral address
output [15:0] per_din; // Peripheral data input
output [1:0] per_we; // Peripheral write enable (high active)
output per_en; // Peripheral enable (high active)
output [`PMEM_MSB:0] pmem_addr; // Program Memory address
output pmem_cen; // Program Memory chip enable (low active)
output [15:0] pmem_din; // Program Memory data input (optional)
output [1:0] pmem_wen; // Program Memory write enable (low active) (optional)
output puc_rst; // Main system reset
output smclk; // ASIC ONLY: SMCLK
output smclk_en; // FPGA ONLY: SMCLK enable
// INPUTs
//============
input cpu_en; // Enable CPU code execution (asynchronous and non-glitchy)
input dbg_en; // Debug interface enable (asynchronous and non-glitchy)
input [6:0] dbg_i2c_addr; // Debug interface: I2C Address
input [6:0] dbg_i2c_broadcast; // Debug interface: I2C Broadcast Address (for multicore systems)
input dbg_i2c_scl; // Debug interface: I2C SCL
input dbg_i2c_sda_in; // Debug interface: I2C SDA IN
input dbg_uart_rxd; // Debug interface: UART RXD (asynchronous)
input dco_clk; // Fast oscillator (fast clock)
input [15:0] dmem_dout; // Data Memory data output
input [13:0] irq; // Maskable interrupts
input lfxt_clk; // Low frequency oscillator (typ 32kHz)
input nmi; // Non-maskable interrupt (asynchronous and non-glitchy)
input [15:0] per_dout; // Peripheral data output
input [15:0] pmem_dout; // Program Memory data output
input reset_n; // Reset Pin (active low, asynchronous and non-glitchy)
input scan_enable; // ASIC ONLY: Scan enable (active during scan shifting)
input scan_mode; // ASIC ONLY: Scan mode
input wkup; // ASIC ONLY: System Wake-up (asynchronous and non-glitchy)
//=============================================================================
// 1) INTERNAL WIRES/REGISTERS/PARAMETERS DECLARATION
//=============================================================================
wire [7:0] inst_ad;
wire [7:0] inst_as;
wire [11:0] inst_alu;
wire inst_bw;
wire inst_irq_rst;
wire inst_mov;
wire [15:0] inst_dest;
wire [15:0] inst_dext;
wire [15:0] inst_sext;
wire [7:0] inst_so;
wire [15:0] inst_src;
wire [2:0] inst_type;
wire [7:0] inst_jmp;
wire [3:0] e_state;
wire exec_done;
wire decode_noirq;
wire cpu_en_s;
wire cpuoff;
wire oscoff;
wire scg0;
wire scg1;
wire por;
wire gie;
wire mclk_enable;
wire mclk_wkup;
wire [31:0] cpu_id;
wire [7:0] cpu_nr_inst = INST_NR;
wire [7:0] cpu_nr_total = TOTAL_NR;
wire [15:0] eu_mab;
wire [15:0] eu_mdb_in;
wire [15:0] eu_mdb_out;
wire [1:0] eu_mb_wr;
wire eu_mb_en;
wire [15:0] fe_mab;
wire [15:0] fe_mdb_in;
wire fe_mb_en;
wire fe_pmem_wait;
wire pc_sw_wr;
wire [15:0] pc_sw;
wire [15:0] pc;
wire [15:0] pc_nxt;
wire nmi_acc;
wire nmi_pnd;
wire nmi_wkup;
wire wdtie;
wire wdtnmies;
wire wdtifg;
wire wdt_irq;
wire wdt_wkup;
wire wdt_reset;
wire wdtifg_sw_clr;
wire wdtifg_sw_set;
wire dbg_clk;
wire dbg_rst;
wire dbg_en_s;
wire dbg_halt_st;
wire dbg_halt_cmd;
wire dbg_mem_en;
wire dbg_reg_wr;
wire dbg_cpu_reset;
wire [15:0] dbg_mem_addr;
wire [15:0] dbg_mem_dout;
wire [15:0] dbg_mem_din;
wire [15:0] dbg_reg_din;
wire [1:0] dbg_mem_wr;
wire puc_pnd_set;
wire [15:0] per_dout_or;
wire [15:0] per_dout_sfr;
wire [15:0] per_dout_wdog;
wire [15:0] per_dout_mpy;
wire [15:0] per_dout_clk;
//=============================================================================
// 2) GLOBAL CLOCK & RESET MANAGEMENT
//=============================================================================
omsp_clock_module clock_module_0 (
// OUTPUTs
.aclk (aclk), // ACLK
.aclk_en (aclk_en), // ACLK enablex
.cpu_en_s (cpu_en_s), // Enable CPU code execution (synchronous)
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_en_s (dbg_en_s), // Debug interface enable (synchronous)
.dbg_rst (dbg_rst), // Debug unit reset
.dco_enable (dco_enable), // Fast oscillator enable
.dco_wkup (dco_wkup), // Fast oscillator wake-up (asynchronous)
.lfxt_enable (lfxt_enable), // Low frequency oscillator enable
.lfxt_wkup (lfxt_wkup), // Low frequency oscillator wake-up (asynchronous)
.mclk (mclk), // Main system clock
.per_dout (per_dout_clk), // Peripheral data output
.por (por), // Power-on reset
.puc_pnd_set (puc_pnd_set), // PUC pending set for the serial debug interface
.puc_rst (puc_rst), // Main system reset
.smclk (smclk), // SMCLK
.smclk_en (smclk_en), // SMCLK enable
// INPUTs
.cpu_en (cpu_en), // Enable CPU code execution (asynchronous)
.cpuoff (cpuoff), // Turns off the CPU
.dbg_cpu_reset(dbg_cpu_reset), // Reset CPU from debug interface
.dbg_en (dbg_en), // Debug interface enable (asynchronous)
.dco_clk (dco_clk), // Fast oscillator (fast clock)
.lfxt_clk (lfxt_clk), // Low frequency oscillator (typ 32kHz)
.mclk_enable (mclk_enable), // Main System Clock enable
.mclk_wkup (mclk_wkup), // Main System Clock wake-up (asynchronous)
.oscoff (oscoff), // Turns off LFXT1 clock input
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.reset_n (reset_n), // Reset Pin (low active, asynchronous)
.scan_enable (scan_enable), // Scan enable (active during scan shifting)
.scan_mode (scan_mode), // Scan mode
.scg0 (scg0), // System clock generator 1. Turns off the DCO
.scg1 (scg1), // System clock generator 1. Turns off the SMCLK
.wdt_reset (wdt_reset) // Watchdog-timer reset
);
//=============================================================================
// 3) FRONTEND (<=> FETCH & DECODE)
//=============================================================================
omsp_frontend frontend_0 (
// OUTPUTs
.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
.decode_noirq (decode_noirq), // Frontend decode instruction
.e_state (e_state), // Execution state
.exec_done (exec_done), // Execution completed
.inst_ad (inst_ad), // Decoded Inst: destination addressing mode
.inst_as (inst_as), // Decoded Inst: source addressing mode
.inst_alu (inst_alu), // ALU control signals
.inst_bw (inst_bw), // Decoded Inst: byte width
.inst_dest (inst_dest), // Decoded Inst: destination (one hot)
.inst_dext (inst_dext), // Decoded Inst: destination extended instruction word
.inst_irq_rst (inst_irq_rst), // Decoded Inst: Reset interrupt
.inst_jmp (inst_jmp), // Decoded Inst: Conditional jump
.inst_mov (inst_mov), // Decoded Inst: mov instruction
.inst_sext (inst_sext), // Decoded Inst: source extended instruction word
.inst_so (inst_so), // Decoded Inst: Single-operand arithmetic
.inst_src (inst_src), // Decoded Inst: source (one hot)
.inst_type (inst_type), // Decoded Instruction type
.irq_acc (irq_acc), // Interrupt request accepted
.mab (fe_mab), // Frontend Memory address bus
.mb_en (fe_mb_en), // Frontend Memory bus enable
.mclk_enable (mclk_enable), // Main System Clock enable
.mclk_wkup (mclk_wkup), // Main System Clock wake-up (asynchronous)
.nmi_acc (nmi_acc), // Non-Maskable interrupt request accepted
.pc (pc), // Program counter
.pc_nxt (pc_nxt), // Next PC value (for CALL & IRQ)
// INPUTs
.cpu_en_s (cpu_en_s), // Enable CPU code execution (synchronous)
.cpuoff (cpuoff), // Turns off the CPU
.dbg_halt_cmd (dbg_halt_cmd), // Halt CPU command
.dbg_reg_sel (dbg_mem_addr[3:0]), // Debug selected register for rd/wr access
.fe_pmem_wait (fe_pmem_wait), // Frontend wait for Instruction fetch
.gie (gie), // General interrupt enable
.irq (irq), // Maskable interrupts
.mclk (mclk), // Main system clock
.mdb_in (fe_mdb_in), // Frontend Memory data bus input
.nmi_pnd (nmi_pnd), // Non-maskable interrupt pending
.nmi_wkup (nmi_wkup), // NMI Wakeup
.pc_sw (pc_sw), // Program counter software value
.pc_sw_wr (pc_sw_wr), // Program counter software write
.puc_rst (puc_rst), // Main system reset
.scan_enable (scan_enable), // Scan enable (active during scan shifting)
.wdt_irq (wdt_irq), // Watchdog-timer interrupt
.wdt_wkup (wdt_wkup), // Watchdog Wakeup
.wkup (wkup) // System Wake-up (asynchronous)
);
//=============================================================================
// 4) EXECUTION UNIT
//=============================================================================
omsp_execution_unit execution_unit_0 (
// OUTPUTs
.cpuoff (cpuoff), // Turns off the CPU
.dbg_reg_din (dbg_reg_din), // Debug unit CPU register data input
.mab (eu_mab), // Memory address bus
.mb_en (eu_mb_en), // Memory bus enable
.mb_wr (eu_mb_wr), // Memory bus write transfer
.mdb_out (eu_mdb_out), // Memory data bus output
.oscoff (oscoff), // Turns off LFXT1 clock input
.pc_sw (pc_sw), // Program counter software value
.pc_sw_wr (pc_sw_wr), // Program counter software write
.scg0 (scg0), // System clock generator 1. Turns off the DCO
.scg1 (scg1), // System clock generator 1. Turns off the SMCLK
// INPUTs
.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
.dbg_mem_dout (dbg_mem_dout), // Debug unit data output
.dbg_reg_wr (dbg_reg_wr), // Debug unit CPU register write
.e_state (e_state), // Execution state
.exec_done (exec_done), // Execution completed
.gie (gie), // General interrupt enable
.inst_ad (inst_ad), // Decoded Inst: destination addressing mode
.inst_as (inst_as), // Decoded Inst: source addressing mode
.inst_alu (inst_alu), // ALU control signals
.inst_bw (inst_bw), // Decoded Inst: byte width
.inst_dest (inst_dest), // Decoded Inst: destination (one hot)
.inst_dext (inst_dext), // Decoded Inst: destination extended instruction word
.inst_irq_rst (inst_irq_rst), // Decoded Inst: reset interrupt
.inst_jmp (inst_jmp), // Decoded Inst: Conditional jump
.inst_mov (inst_mov), // Decoded Inst: mov instruction
.inst_sext (inst_sext), // Decoded Inst: source extended instruction word
.inst_so (inst_so), // Decoded Inst: Single-operand arithmetic
.inst_src (inst_src), // Decoded Inst: source (one hot)
.inst_type (inst_type), // Decoded Instruction type
.mclk (mclk), // Main system clock
.mdb_in (eu_mdb_in), // Memory data bus input
.pc (pc), // Program counter
.pc_nxt (pc_nxt), // Next PC value (for CALL & IRQ)
.puc_rst (puc_rst), // Main system reset
.scan_enable (scan_enable) // Scan enable (active during scan shifting)
);
//=============================================================================
// 5) MEMORY BACKBONE
//=============================================================================
omsp_mem_backbone mem_backbone_0 (
// OUTPUTs
.dbg_mem_din (dbg_mem_din), // Debug unit Memory data input
.dmem_addr (dmem_addr), // Data Memory address
.dmem_cen (dmem_cen), // Data Memory chip enable (low active)
.dmem_din (dmem_din), // Data Memory data input
.dmem_wen (dmem_wen), // Data Memory write enable (low active)
.eu_mdb_in (eu_mdb_in), // Execution Unit Memory data bus input
.fe_mdb_in (fe_mdb_in), // Frontend Memory data bus input
.fe_pmem_wait (fe_pmem_wait), // Frontend wait for Instruction fetch
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_we (per_we), // Peripheral write enable (high active)
.per_en (per_en), // Peripheral enable (high active)
.pmem_addr (pmem_addr), // Program Memory address
.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
.pmem_din (pmem_din), // Program Memory data input (optional)
.pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)
// INPUTs
.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
.dbg_mem_addr (dbg_mem_addr), // Debug address for rd/wr access
.dbg_mem_dout (dbg_mem_dout), // Debug unit data output
.dbg_mem_en (dbg_mem_en), // Debug unit memory enable
.dbg_mem_wr (dbg_mem_wr), // Debug unit memory write
.dmem_dout (dmem_dout), // Data Memory data output
.eu_mab (eu_mab[15:1]), // Execution Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution Unit Memory bus write transfer
.eu_mdb_out (eu_mdb_out), // Execution Unit Memory data bus output
.fe_mab (fe_mab[15:1]), // Frontend Memory address bus
.fe_mb_en (fe_mb_en), // Frontend Memory bus enable
.mclk (mclk), // Main system clock
.per_dout (per_dout_or), // Peripheral data output
.pmem_dout (pmem_dout), // Program Memory data output
.puc_rst (puc_rst), // Main system reset
.scan_enable (scan_enable) // Scan enable (active during scan shifting)
);
//=============================================================================
// 6) SPECIAL FUNCTION REGISTERS
//=============================================================================
omsp_sfr sfr_0 (
// OUTPUTs
.cpu_id (cpu_id), // CPU ID
.nmi_pnd (nmi_pnd), // NMI Pending
.nmi_wkup (nmi_wkup), // NMI Wakeup
.per_dout (per_dout_sfr), // Peripheral data output
.wdtie (wdtie), // Watchdog-timer interrupt enable
.wdtifg_sw_clr(wdtifg_sw_clr), // Watchdog-timer interrupt flag software clear
.wdtifg_sw_set(wdtifg_sw_set), // Watchdog-timer interrupt flag software set
// INPUTs
.cpu_nr_inst (cpu_nr_inst), // Current oMSP instance number
.cpu_nr_total (cpu_nr_total), // Total number of oMSP instances-1
.mclk (mclk), // Main system clock
.nmi (nmi), // Non-maskable interrupt (asynchronous)
.nmi_acc (nmi_acc), // Non-Maskable interrupt request accepted
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.puc_rst (puc_rst), // Main system reset
.scan_mode (scan_mode), // Scan mode
.wdtifg (wdtifg), // Watchdog-timer interrupt flag
.wdtnmies (wdtnmies) // Watchdog-timer NMI edge selection
);
//=============================================================================
// 7) WATCHDOG TIMER
//=============================================================================
`ifdef WATCHDOG
omsp_watchdog watchdog_0 (
// OUTPUTs
.per_dout (per_dout_wdog), // Peripheral data output
.wdt_irq (wdt_irq), // Watchdog-timer interrupt
.wdt_reset (wdt_reset), // Watchdog-timer reset
.wdt_wkup (wdt_wkup), // Watchdog Wakeup
.wdtifg (wdtifg), // Watchdog-timer interrupt flag
.wdtnmies (wdtnmies), // Watchdog-timer NMI edge selection
// INPUTs
.aclk (aclk), // ACLK
.aclk_en (aclk_en), // ACLK enable
.dbg_freeze (dbg_freeze), // Freeze Watchdog counter
.mclk (mclk), // Main system clock
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.por (por), // Power-on reset
.puc_rst (puc_rst), // Main system reset
.scan_enable (scan_enable), // Scan enable (active during scan shifting)
.scan_mode (scan_mode), // Scan mode
.smclk (smclk), // SMCLK
.smclk_en (smclk_en), // SMCLK enable
.wdtie (wdtie), // Watchdog-timer interrupt enable
.wdtifg_irq_clr (irq_acc[10]), // Clear Watchdog-timer interrupt flag
.wdtifg_sw_clr (wdtifg_sw_clr), // Watchdog-timer interrupt flag software clear
.wdtifg_sw_set (wdtifg_sw_set) // Watchdog-timer interrupt flag software set
);
`else
assign per_dout_wdog = 16'h0000;
assign wdt_irq = 1'b0;
assign wdt_reset = 1'b0;
assign wdt_wkup = 1'b0;
assign wdtifg = 1'b0;
assign wdtnmies = 1'b0;
`endif
//=============================================================================
// 8) HARDWARE MULTIPLIER
//=============================================================================
`ifdef MULTIPLIER
omsp_multiplier multiplier_0 (
// OUTPUTs
.per_dout (per_dout_mpy), // Peripheral data output
// INPUTs
.mclk (mclk), // Main system clock
.per_addr (per_addr), // Peripheral address
.per_din (per_din), // Peripheral data input
.per_en (per_en), // Peripheral enable (high active)
.per_we (per_we), // Peripheral write enable (high active)
.puc_rst (puc_rst), // Main system reset
.scan_enable (scan_enable) // Scan enable (active during scan shifting)
);
`else
assign per_dout_mpy = 16'h0000;
`endif
//=============================================================================
// 9) PERIPHERALS' OUTPUT BUS
//=============================================================================
assign per_dout_or = per_dout |
per_dout_clk |
per_dout_sfr |
per_dout_wdog |
per_dout_mpy;
//=============================================================================
// 10) DEBUG INTERFACE
//=============================================================================
`ifdef DBG_EN
omsp_dbg dbg_0 (
// OUTPUTs
.dbg_cpu_reset (dbg_cpu_reset), // Reset CPU from debug interface
.dbg_freeze (dbg_freeze), // Freeze peripherals
.dbg_halt_cmd (dbg_halt_cmd), // Halt CPU command
.dbg_i2c_sda_out (dbg_i2c_sda_out), // Debug interface: I2C SDA OUT
.dbg_mem_addr (dbg_mem_addr), // Debug address for rd/wr access
.dbg_mem_dout (dbg_mem_dout), // Debug unit data output
.dbg_mem_en (dbg_mem_en), // Debug unit memory enable
.dbg_mem_wr (dbg_mem_wr), // Debug unit memory write
.dbg_reg_wr (dbg_reg_wr), // Debug unit CPU register write
.dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
// INPUTs
.cpu_en_s (cpu_en_s), // Enable CPU code execution (synchronous)
.cpu_id (cpu_id), // CPU ID
.cpu_nr_inst (cpu_nr_inst), // Current oMSP instance number
.cpu_nr_total (cpu_nr_total), // Total number of oMSP instances-1
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_en_s (dbg_en_s), // Debug interface enable (synchronous)
.dbg_halt_st (dbg_halt_st), // Halt/Run status from CPU
.dbg_i2c_addr (dbg_i2c_addr), // Debug interface: I2C Address
.dbg_i2c_broadcast (dbg_i2c_broadcast), // Debug interface: I2C Broadcast Address (for multicore systems)
.dbg_i2c_scl (dbg_i2c_scl), // Debug interface: I2C SCL
.dbg_i2c_sda_in (dbg_i2c_sda_in), // Debug interface: I2C SDA IN
.dbg_mem_din (dbg_mem_din), // Debug unit Memory data input
.dbg_reg_din (dbg_reg_din), // Debug unit CPU register data input
.dbg_rst (dbg_rst), // Debug unit reset
.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD (asynchronous)
.decode_noirq (decode_noirq), // Frontend decode instruction
.eu_mab (eu_mab), // Execution-Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
.fe_mdb_in (fe_mdb_in), // Frontend Memory data bus input
.pc (pc), // Program counter
.puc_pnd_set (puc_pnd_set) // PUC pending set for the serial debug interface
);
`else
assign dbg_cpu_reset = 1'b0;
assign dbg_freeze = ~cpu_en_s;
assign dbg_halt_cmd = 1'b0;
assign dbg_i2c_sda_out = 1'b1;
assign dbg_mem_addr = 16'h0000;
assign dbg_mem_dout = 16'h0000;
assign dbg_mem_en = 1'b0;
assign dbg_mem_wr = 2'b00;
assign dbg_reg_wr = 1'b0;
assign dbg_uart_txd = 1'b1;
`endif
endmodule // openMSP430
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O31A_FUNCTIONAL_V
`define SKY130_FD_SC_LP__O31A_FUNCTIONAL_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__o31a (
X ,
A1,
A2,
A3,
B1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X, or0_out, B1 );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O31A_FUNCTIONAL_V |
module testbench ();
parameter START_ADDR = 32'h80020000;
// test
reg [31:0] test_counter;
// global
reg clk;
// fetch in
reg stall;
reg reset;
// fetch out, mem in, decode in
wire [31:0] addr;
reg rw;
wire [1:0] access_size;
wire enable;
// mem in
reg [31:0] din;
// mem out
wire busy;
// mem out, decode in
wire [31:0] dout;
fetch test_fetch(.clk(clk),
.stall(stall),
.reset(reset),
.pc(addr),
.rw(),
.access_size(access_size),
.enable(enable));
mips_memory2 test_memory(.clk(clk),
.addr(addr),
.din(din),
.dout(dout),
.access_size(access_size),
.rw(rw),
.busy(busy),
.enable(enable));
/*decode test_decode(.clk,
.insn,
.pc,
.instbits,
.op,
.src1,
.src2,
.dst);*/
reg [7:0] mem[0:256];
initial
begin
clk = 1'b1;
test_counter = 0;
stall = 0;
reset = 0;
rw = 1;
din = 32'b0000_0000;
$readmemh("SumArray.x", mem);
end
always @(posedge clk)
begin
if (test_counter <= 2)
begin
test_counter <= test_counter + 1;
reset <= 1;
din <= 'x;
$display("1");
end
else if (test_counter > 2 && test_counter <= 15)
begin
test_counter <= test_counter + 1;
reset <= 0;
din[31:24] = mem[addr - START_ADDR];
din[23:16] = mem[addr + 1 - START_ADDR];
din[15:8] = mem[addr + 2 - START_ADDR];
din[7:0] = mem[addr + 3 - START_ADDR];
$display("2");
end
else
begin
test_counter <= 0;
reset <= 1;
din <= 'x;
rw <= !rw;
$display("3");
end
end
always
#5 clk = !clk;
endmodule
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: pizza.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pizza (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "./sprites/pizza.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./sprites/pizza.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./sprites/pizza.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pizza.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pizza.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pizza.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pizza.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pizza_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pizza_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/********************
* Filename: arbiter.v
* Description: Packets with the same priority and destined for the same output port are scheduled with a round-robin arbiter with the last served as least priority.
Priority direction Local, North, East, South, West
Maintains the priority till it reads the TAIL flit
One-hot encoding for state variable
Output values [5:0]: Output[5:1] -> selection, Output[0] -> idle
*
* $Revision: 26 $
* $Id: arbiter.v 26 2015-11-22 19:24:28Z ranga $
* $Date: 2015-11-22 21:24:28 +0200 (Sun, 22 Nov 2015) $
* $Author: ranga $
*********************/
`include "parameters.v"
`include "state_defines.v"
module arbiter(clk, rst,
Lflit_id, Nflit_id, Eflit_id, Wflit_id, Sflit_id,
Llength, Nlength, Elength, Wlength, Slength,
Lreq, Nreq, Ereq, Wreq, Sreq,
nextstate
);
input clk, rst;
input [2:0] Lflit_id, Nflit_id, Eflit_id, Wflit_id, Sflit_id;
input [11:0] Llength, Nlength, Elength, Wlength, Slength;
input Lreq, Nreq, Ereq, Wreq, Sreq;
output reg [5:0] nextstate;
// Declaring the local variables
reg [5:0] currentstate;
reg Lruntimer, Nruntimer, Eruntimer, Wruntimer, Sruntimer;
wire Ltimesup, Ntimesup, Etimesup, Wtimesup, Stimesup;
// Timer module that runs for the entire packet length
timer Ltimer (clk, rst, Lflit_id, Llength, Lruntimer, Ltimesup);
timer Ntimer (clk, rst, Nflit_id, Nlength, Nruntimer, Ntimesup);
timer Etimer (clk, rst, Eflit_id, Elength, Eruntimer, Etimesup);
timer Wtimer (clk, rst, Wflit_id, Wlength, Wruntimer, Wtimesup);
timer Stimer (clk, rst, Sflit_id, Slength, Sruntimer, Stimesup);
// Arbiter - State Machine
// Current state sequential Logic
always @ (posedge clk) begin
if(rst)
currentstate <= `IDLE;
else
currentstate <= nextstate;
end
// Next state decoder Logic
always @ (Lreq, Nreq, Ereq, Wreq, Sreq, Ltimesup, Ntimesup, Etimesup, Wtimesup, Stimesup, currentstate) begin
{Lruntimer, Nruntimer, Eruntimer, Wruntimer, Sruntimer} = 0;
case(currentstate)
`IDLE:
begin
if(Lreq == 1) begin
nextstate = `GRANT_L;
end
else if(Nreq == 1) begin
nextstate = `GRANT_N;
end
else if(Ereq == 1) begin
nextstate = `GRANT_E;
end
else if(Wreq == 1) begin
nextstate = `GRANT_W;
end
else if (Sreq == 1) begin
nextstate = `GRANT_S;
end
else begin
nextstate = `IDLE;
end
end
`GRANT_L:
begin
if(Lreq == 1 && Ltimesup == 0) begin
Lruntimer = 1;
nextstate = `GRANT_L;
end
else if(Nreq == 1) begin
nextstate = `GRANT_N;
end
else if(Ereq == 1) begin
nextstate = `GRANT_E;
end
else if(Wreq == 1) begin
nextstate = `GRANT_W;
end
else if(Sreq == 1) begin
nextstate = `GRANT_S;
end
else begin
nextstate = `IDLE;
end
end
`GRANT_N:
begin
if(Nreq == 1 && Ntimesup == 0) begin
Nruntimer = 1;
nextstate = `GRANT_N;
end
else if(Ereq == 1) begin
nextstate = `GRANT_E;
end
else if(Wreq == 1) begin
nextstate = `GRANT_W;
end
else if(Sreq == 1) begin
nextstate = `GRANT_S;
end
else if(Lreq == 1) begin
nextstate = `GRANT_L;
end
else begin
nextstate = `IDLE;
end
end
`GRANT_E:
begin
if(Ereq == 1 && Etimesup == 0) begin
Eruntimer = 1;
nextstate = `GRANT_E;
end
else if(Wreq == 1) begin
nextstate = `GRANT_W;
end
else if(Sreq == 1) begin
nextstate = `GRANT_S;
end
else if(Lreq == 1) begin
nextstate = `GRANT_L;
end
else if(Nreq == 1) begin
nextstate = `GRANT_N;
end
else begin
nextstate = `IDLE;
end
end
`GRANT_W:
begin
if(Wreq == 1 && Wtimesup == 0) begin
Wruntimer = 1;
nextstate = `GRANT_W;
end
else if(Sreq == 1) begin
nextstate = `GRANT_S;
end
else if(Lreq == 1) begin
nextstate = `GRANT_L;
end
else if(Nreq == 1) begin
nextstate = `GRANT_N;
end
else if(Ereq == 1) begin
nextstate = `GRANT_E;
end
else begin
nextstate = `IDLE;
end
end
`GRANT_S:
begin
if(Sreq == 1 && Stimesup == 0) begin
Sruntimer = 1;
nextstate = `GRANT_S;
end
else if(Lreq == 1) begin
nextstate = `GRANT_L;
end
else if(Nreq == 1) begin
nextstate = `GRANT_N;
end
else if(Ereq == 1) begin
nextstate = `GRANT_E;
end
else if(Wreq == 1) begin
nextstate = `GRANT_W;
end
else begin
nextstate = `IDLE;
end
end
default:
begin
nextstate = `IDLE;
end
endcase
end
endmodule
module timer (clk, rst, flit_id, length, runtimer, timesup);
input clk, rst;
input [2 : 0] flit_id;
input [11 : 0] length;
input runtimer;
output reg timesup;
//Declaring the local variables
reg [11 : 0] timeoutclockperiods; // stores packet length
reg [11 : 0] count;
// Setting Access time for each request
always @ (posedge clk) begin: timeout
if(rst) begin
count <= 0;
timeoutclockperiods <= 0;
end
else begin
if (flit_id == `HEADER) begin
timeoutclockperiods <= length;
end
if (runtimer == 0) begin
count <= 0;
end
else begin
count <= count + 1;
end
end
end
// Asserting the timesup signal when the access time exceeds timeoutclockperiod
always @ (count, timeoutclockperiods) begin : timeup
if (count == timeoutclockperiods)
timesup = 1;
else
timesup = 0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR4B_SYMBOL_V
`define SKY130_FD_SC_MS__NOR4B_SYMBOL_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nor4b (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D_N,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR4B_SYMBOL_V
|
//
///////////////////////////////////////////////////////////////////////////////////////////
// Copyright © 2010-2013, Xilinx, Inc.
// This file contains confidential and proprietary information of Xilinx, Inc. and is
// protected under U.S. and international copyright and other intellectual property laws.
///////////////////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to
// you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
// MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
// DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
// OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
// (whether in contract or tort, including negligence, or under any other theory
// of liability) for any loss or damage of any kind or nature related to, arising
// under or in connection with these materials, including for any direct, or any
// indirect, special, incidental, or consequential loss or damage (including loss
// of data, profits, goodwill, or any type of loss or damage suffered as a result
// of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-safe, or for use in any
// application requiring fail-safe performance, such as life-support or safety
// devices or systems, Class III medical devices, nuclear facilities, applications
// related to the deployment of airbags, or any other applications that could lead
// to death, personal injury, or severe property or environmental damage
// (individually and collectively, "Critical Applications"). Customer assumes the
// sole risk and liability of any use of Xilinx products in Critical Applications,
// subject only to applicable laws and regulations governing limitations on product
// liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
///////////////////////////////////////////////////////////////////////////////////////////
//
ROM_form.v
Production template for a 2K program for KCPSM6 in a Virtex-6 device using a
RAMB36E1 primitive.
Nick Sawyer (Xilinx Ltd)
Ken Chapman (Xilinx Ltd)
5th August 2011 - First Release
14th March 2013 - Unused address inputs on BRAMs connected High to reflect
descriptions UG363.
This is a verilog template file for the KCPSM6 assembler.
This verilog file is not valid as input directly into a synthesis or a simulation tool.
The assembler will read this template and insert the information required to complete
the definition of program ROM and write it out to a new '.v' file that is ready for
synthesis and simulation.
This template can be modified to define alternative memory definitions. However, you are
responsible for ensuring the template is correct as the assembler does not perform any
checking of the verilog.
The assembler identifies all text enclosed by {} characters, and replaces these
character strings. All templates should include these {} character strings for
the assembler to work correctly.
The next line is used to determine where the template actually starts.
{begin template}
//
///////////////////////////////////////////////////////////////////////////////////////////
// Copyright © 2010-2013, Xilinx, Inc.
// This file contains confidential and proprietary information of Xilinx, Inc. and is
// protected under U.S. and international copyright and other intellectual property laws.
///////////////////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to
// you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
// MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
// DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
// OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
// (whether in contract or tort, including negligence, or under any other theory
// of liability) for any loss or damage of any kind or nature related to, arising
// under or in connection with these materials, including for any direct, or any
// indirect, special, incidental, or consequential loss or damage (including loss
// of data, profits, goodwill, or any type of loss or damage suffered as a result
// of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-safe, or for use in any
// application requiring fail-safe performance, such as life-support or safety
// devices or systems, Class III medical devices, nuclear facilities, applications
// related to the deployment of airbags, or any other applications that could lead
// to death, personal injury, or severe property or environmental damage
// (individually and collectively, "Critical Applications"). Customer assumes the
// sole risk and liability of any use of Xilinx products in Critical Applications,
// subject only to applicable laws and regulations governing limitations on product
// liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
///////////////////////////////////////////////////////////////////////////////////////////
//
//
// Production definition of a 2K program for KCPSM6 in a Virtex-6 device using a
// RAMB36E1 primitive.
//
// Note: The complete 12-bit address bus is connected to KCPSM6 to facilitate future code
// expansion with minimum changes being required to the hardware description.
// Only the lower 11-bits of the address are actually used for the 2K address range
// 000 to 7FF hex.
//
// Program defined by '{psmname}.psm'.
//
// Generated by KCPSM6 Assembler: {timestamp}.
//
// Assembler used ROM_form template: ROM_form_V6_2K_14March13.v
//
//
module {name} (
input [11:0] address,
output [17:0] instruction,
input enable,
input clk);
//
//
wire [15:0] address_a;
wire [35:0] data_in_a;
wire [35:0] data_out_a;
wire [15:0] address_b;
wire [35:0] data_in_b;
wire [35:0] data_out_b;
wire enable_b;
wire clk_b;
wire [7:0] we_b;
//
//
assign address_a = {1'b1, address[10:0], 4'b1111};
assign instruction = {data_out_a[33:32], data_out_a[15:0]};
assign data_in_a = {35'b000000000000000000000000000000000000, address[11]};
//
assign address_b = 16'b1111111111111111;
assign data_in_b = {2'h0, data_out_b[33:32], 16'h0000, data_out_b[15:0]};
assign enable_b = 1'b0;
assign we_b = 8'h00;
assign clk_b = 1'b0;
//
RAMB36E1 # ( .READ_WIDTH_A (18),
.WRITE_WIDTH_A (18),
.DOA_REG (0),
.INIT_A (36'h000000000),
.RSTREG_PRIORITY_A ("REGCE"),
.SRVAL_A (36'h000000000),
.WRITE_MODE_A ("WRITE_FIRST"),
.READ_WIDTH_B (18),
.WRITE_WIDTH_B (18),
.DOB_REG (0),
.INIT_B (36'h000000000),
.RSTREG_PRIORITY_B ("REGCE"),
.SRVAL_B (36'h000000000),
.WRITE_MODE_B ("WRITE_FIRST"),
.INIT_FILE ("NONE"),
.SIM_COLLISION_CHECK ("ALL"),
.RAM_MODE ("TDP"),
.RDADDR_COLLISION_HWCONFIG ("DELAYED_WRITE"),
.EN_ECC_READ ("FALSE"),
.EN_ECC_WRITE ("FALSE"),
.RAM_EXTENSION_A ("NONE"),
.RAM_EXTENSION_B ("NONE"),
.SIM_DEVICE ("VIRTEX6"),
.INIT_00 (256'h{INIT_00}),
.INIT_01 (256'h{INIT_01}),
.INIT_02 (256'h{INIT_02}),
.INIT_03 (256'h{INIT_03}),
.INIT_04 (256'h{INIT_04}),
.INIT_05 (256'h{INIT_05}),
.INIT_06 (256'h{INIT_06}),
.INIT_07 (256'h{INIT_07}),
.INIT_08 (256'h{INIT_08}),
.INIT_09 (256'h{INIT_09}),
.INIT_0A (256'h{INIT_0A}),
.INIT_0B (256'h{INIT_0B}),
.INIT_0C (256'h{INIT_0C}),
.INIT_0D (256'h{INIT_0D}),
.INIT_0E (256'h{INIT_0E}),
.INIT_0F (256'h{INIT_0F}),
.INIT_10 (256'h{INIT_10}),
.INIT_11 (256'h{INIT_11}),
.INIT_12 (256'h{INIT_12}),
.INIT_13 (256'h{INIT_13}),
.INIT_14 (256'h{INIT_14}),
.INIT_15 (256'h{INIT_15}),
.INIT_16 (256'h{INIT_16}),
.INIT_17 (256'h{INIT_17}),
.INIT_18 (256'h{INIT_18}),
.INIT_19 (256'h{INIT_19}),
.INIT_1A (256'h{INIT_1A}),
.INIT_1B (256'h{INIT_1B}),
.INIT_1C (256'h{INIT_1C}),
.INIT_1D (256'h{INIT_1D}),
.INIT_1E (256'h{INIT_1E}),
.INIT_1F (256'h{INIT_1F}),
.INIT_20 (256'h{INIT_20}),
.INIT_21 (256'h{INIT_21}),
.INIT_22 (256'h{INIT_22}),
.INIT_23 (256'h{INIT_23}),
.INIT_24 (256'h{INIT_24}),
.INIT_25 (256'h{INIT_25}),
.INIT_26 (256'h{INIT_26}),
.INIT_27 (256'h{INIT_27}),
.INIT_28 (256'h{INIT_28}),
.INIT_29 (256'h{INIT_29}),
.INIT_2A (256'h{INIT_2A}),
.INIT_2B (256'h{INIT_2B}),
.INIT_2C (256'h{INIT_2C}),
.INIT_2D (256'h{INIT_2D}),
.INIT_2E (256'h{INIT_2E}),
.INIT_2F (256'h{INIT_2F}),
.INIT_30 (256'h{INIT_30}),
.INIT_31 (256'h{INIT_31}),
.INIT_32 (256'h{INIT_32}),
.INIT_33 (256'h{INIT_33}),
.INIT_34 (256'h{INIT_34}),
.INIT_35 (256'h{INIT_35}),
.INIT_36 (256'h{INIT_36}),
.INIT_37 (256'h{INIT_37}),
.INIT_38 (256'h{INIT_38}),
.INIT_39 (256'h{INIT_39}),
.INIT_3A (256'h{INIT_3A}),
.INIT_3B (256'h{INIT_3B}),
.INIT_3C (256'h{INIT_3C}),
.INIT_3D (256'h{INIT_3D}),
.INIT_3E (256'h{INIT_3E}),
.INIT_3F (256'h{INIT_3F}),
.INIT_40 (256'h{INIT_40}),
.INIT_41 (256'h{INIT_41}),
.INIT_42 (256'h{INIT_42}),
.INIT_43 (256'h{INIT_43}),
.INIT_44 (256'h{INIT_44}),
.INIT_45 (256'h{INIT_45}),
.INIT_46 (256'h{INIT_46}),
.INIT_47 (256'h{INIT_47}),
.INIT_48 (256'h{INIT_48}),
.INIT_49 (256'h{INIT_49}),
.INIT_4A (256'h{INIT_4A}),
.INIT_4B (256'h{INIT_4B}),
.INIT_4C (256'h{INIT_4C}),
.INIT_4D (256'h{INIT_4D}),
.INIT_4E (256'h{INIT_4E}),
.INIT_4F (256'h{INIT_4F}),
.INIT_50 (256'h{INIT_50}),
.INIT_51 (256'h{INIT_51}),
.INIT_52 (256'h{INIT_52}),
.INIT_53 (256'h{INIT_53}),
.INIT_54 (256'h{INIT_54}),
.INIT_55 (256'h{INIT_55}),
.INIT_56 (256'h{INIT_56}),
.INIT_57 (256'h{INIT_57}),
.INIT_58 (256'h{INIT_58}),
.INIT_59 (256'h{INIT_59}),
.INIT_5A (256'h{INIT_5A}),
.INIT_5B (256'h{INIT_5B}),
.INIT_5C (256'h{INIT_5C}),
.INIT_5D (256'h{INIT_5D}),
.INIT_5E (256'h{INIT_5E}),
.INIT_5F (256'h{INIT_5F}),
.INIT_60 (256'h{INIT_60}),
.INIT_61 (256'h{INIT_61}),
.INIT_62 (256'h{INIT_62}),
.INIT_63 (256'h{INIT_63}),
.INIT_64 (256'h{INIT_64}),
.INIT_65 (256'h{INIT_65}),
.INIT_66 (256'h{INIT_66}),
.INIT_67 (256'h{INIT_67}),
.INIT_68 (256'h{INIT_68}),
.INIT_69 (256'h{INIT_69}),
.INIT_6A (256'h{INIT_6A}),
.INIT_6B (256'h{INIT_6B}),
.INIT_6C (256'h{INIT_6C}),
.INIT_6D (256'h{INIT_6D}),
.INIT_6E (256'h{INIT_6E}),
.INIT_6F (256'h{INIT_6F}),
.INIT_70 (256'h{INIT_70}),
.INIT_71 (256'h{INIT_71}),
.INIT_72 (256'h{INIT_72}),
.INIT_73 (256'h{INIT_73}),
.INIT_74 (256'h{INIT_74}),
.INIT_75 (256'h{INIT_75}),
.INIT_76 (256'h{INIT_76}),
.INIT_77 (256'h{INIT_77}),
.INIT_78 (256'h{INIT_78}),
.INIT_79 (256'h{INIT_79}),
.INIT_7A (256'h{INIT_7A}),
.INIT_7B (256'h{INIT_7B}),
.INIT_7C (256'h{INIT_7C}),
.INIT_7D (256'h{INIT_7D}),
.INIT_7E (256'h{INIT_7E}),
.INIT_7F (256'h{INIT_7F}),
.INITP_00 (256'h{INITP_00}),
.INITP_01 (256'h{INITP_01}),
.INITP_02 (256'h{INITP_02}),
.INITP_03 (256'h{INITP_03}),
.INITP_04 (256'h{INITP_04}),
.INITP_05 (256'h{INITP_05}),
.INITP_06 (256'h{INITP_06}),
.INITP_07 (256'h{INITP_07}),
.INITP_08 (256'h{INITP_08}),
.INITP_09 (256'h{INITP_09}),
.INITP_0A (256'h{INITP_0A}),
.INITP_0B (256'h{INITP_0B}),
.INITP_0C (256'h{INITP_0C}),
.INITP_0D (256'h{INITP_0D}),
.INITP_0E (256'h{INITP_0E}),
.INITP_0F (256'h{INITP_0F}))
kcpsm6_rom( .ADDRARDADDR (address_a),
.ENARDEN (enable),
.CLKARDCLK (clk),
.DOADO (data_out_a[31:0]),
.DOPADOP (data_out_a[35:32]),
.DIADI (data_in_a[31:0]),
.DIPADIP (data_in_a[35:32]),
.WEA (4'h0),
.REGCEAREGCE (1'b0),
.RSTRAMARSTRAM (1'b0),
.RSTREGARSTREG (1'b0),
.ADDRBWRADDR (address_b),
.ENBWREN (enable_b),
.CLKBWRCLK (clk_b),
.DOBDO (data_out_b[31:0]),
.DOPBDOP (data_out_b[35:32]),
.DIBDI (data_in_b[31:0]),
.DIPBDIP (data_in_b[35:32]),
.WEBWE (we_b),
.REGCEB (1'b0),
.RSTRAMB (1'b0),
.RSTREGB (1'b0),
.CASCADEINA (1'b0),
.CASCADEINB (1'b0),
.CASCADEOUTA (),
.CASCADEOUTB (),
.DBITERR (),
.ECCPARITY (),
.RDADDRECC (),
.SBITERR (),
.INJECTDBITERR (1'b0),
.INJECTSBITERR (1'b0));
//
//
endmodule
//
////////////////////////////////////////////////////////////////////////////////////
//
// END OF FILE {name}.v
//
////////////////////////////////////////////////////////////////////////////////////
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O221AI_4_V
`define SKY130_FD_SC_HS__O221AI_4_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog wrapper for o221ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o221ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o221ai_4 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o221ai_4 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O221AI_4_V
|
`timescale 1ns / 1ps
module display(clk, rst_n, digit, out);
input clk;
input rst_n;
input [15:0]digit;
output [18:0]out;
wire clk, rst_n;
wire [15:0]digit;
reg [18:0]out;
reg [1:0]select;
reg [1:0]select_nxt;
// modify this section
parameter d0=15'b0000_0011_1111_111;
parameter d1=15'b1111_1111_1011_011;
parameter d2=15'b0110_0101_1101_111;
parameter d3=15'b0110_1101_1101_101;
parameter d4=15'b1111_1000_1011_011;
parameter d5=15'b0110_1001_1111_101;
parameter d6=15'b1100_0000_1111_111;
parameter d7=15'b0001_1011_1111_111;
parameter d8=15'b0110_1111_0100_101;
parameter d9=15'b0001_1000_1111_111;
parameter dark=15'b1111_1111_1111_111;
always @*begin
case(digit[(select*4)+:4])
4'd0:out[14:0]=d0;
4'd1:out[14:0]=d1;
4'd2:out[14:0]=d2;
4'd3:out[14:0]=d3;
4'd4:out[14:0]=d4;
4'd5:out[14:0]=d5;
4'd6:out[14:0]=d6;
4'd7:out[14:0]=d7;
4'd8:out[14:0]=d8;
4'd9:out[14:0]=d9;
default:out[14:0]=dark;
endcase
case(select)
2'd0:out[18:15]=4'b1110;
2'd1:out[18:15]=4'b1101;
2'd2:out[18:15]=4'b1011;
2'd3:out[18:15]=4'b0111;
default:out[18:15]=4'b1111;
endcase
select_nxt=select+1;
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
select=2'd0;
end else begin
select=select_nxt;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR4BB_BEHAVIORAL_V
`define SKY130_FD_SC_HS__OR4BB_BEHAVIORAL_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__or4bb (
X ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
// Local signals
wire DN nand0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , D_N, C_N );
or or0 (or0_out_X , B, A, nand0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR4BB_BEHAVIORAL_V |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_3_fast_cfg_init_cntr.v
// Version : 1.3
//--
//-- Description: PCIe Fast Configuration Init Counter
//--
//------------------------------------------------------------------------------
module pcie_7x_v1_3_fast_cfg_init_cntr #(
parameter PATTERN_WIDTH = 8,
parameter INIT_PATTERN = 8'hA5,
parameter TCQ = 1
) (
input clk,
input rst,
output reg [PATTERN_WIDTH-1:0] pattern_o
);
always @(posedge clk) begin
if(rst) begin
pattern_o <= #TCQ {PATTERN_WIDTH{1'b0}};
end else begin
if(pattern_o != INIT_PATTERN) begin
pattern_o <= #TCQ pattern_o + 1;
end
end
end
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps / 1ps
`include "utils/bus_to_ip.v"
`include "gpio/gpio_core.v"
`include "gpio/gpio.v"
`include "pulse_gen/pulse_gen.v"
`include "pulse_gen/pulse_gen_core.v"
`include "utils/clock_multiplier.v"
`include "bram_fifo/bram_fifo_core.v"
`include "bram_fifo/bram_fifo.v"
`include "timestamp/timestamp.v"
`include "timestamp/timestamp_core.v"
`include "utils/cdc_syncfifo.v"
`include "utils/generic_fifo.v"
`include "utils/cdc_pulse_sync.v"
`include "utils/CG_MOD_pos.v"
`include "utils/clock_divider.v"
`include "utils/3_stage_synchronizer.v"
`include "utils/RAMB16_S1_S9_sim.v"
module tb (
input wire BUS_CLK,
input wire BUS_RST,
input wire [31:0] BUS_ADD,
inout wire [31:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
output wire BUS_BYTE_ACCESS
);
// MODULE ADREESSES //
localparam GPIO_BASEADDR = 32'h0000;
localparam GPIO_HIGHADDR = 32'h1000-1;
localparam TIMESTAMP_BASEADDR = 32'h1000; //0x1000
localparam TIMESTAMP_HIGHADDR = 32'h2000-1; //0x300f
localparam PULSE_BASEADDR = 32'h3000;
localparam PULSE_HIGHADDR = PULSE_BASEADDR + 15;
localparam FIFO_BASEADDR = 32'h8000;
localparam FIFO_HIGHADDR = 32'h9000-1;
localparam FIFO_BASEADDR_DATA = 32'h8000_0000;
localparam FIFO_HIGHADDR_DATA = 32'h9000_0000;
localparam ABUSWIDTH = 32;
assign BUS_BYTE_ACCESS = BUS_ADD < 32'h8000_0000 ? 1'b1 : 1'b0;
// MODULES //
reg [63:0] TIMESTAMP;
wire [63:0] TIMESTAMP_OUT;
gpio #(
.BASEADDR(GPIO_BASEADDR),
.HIGHADDR(GPIO_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.IO_WIDTH(64),
.IO_DIRECTION(64'h0)
) i_gpio (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.IO(TIMESTAMP_OUT)
);
wire CLK;
wire PULSE;
pulse_gen #(
.BASEADDR(PULSE_BASEADDR),
.HIGHADDR(PULSE_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) i_pulse_gen (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.PULSE_CLK(CLK),
.EXT_START(1'b0),
.PULSE(PULSE)
);
wire CLK640,CLK320,CLK160,CLK40;
clock_divider #(
.DIVISOR(4)
) i_clock_divisor_spi (
.CLK(BUS_CLK),
.RESET(1'b0),
.CE(),
.CLOCK(CLK)
);
always @(posedge CLK)
TIMESTAMP <= TIMESTAMP + 1;
wire FIFO_READ, FIFO_EMPTY;
wire [31:0] FIFO_DATA;
timestamp #(
.BASEADDR(TIMESTAMP_BASEADDR),
.HIGHADDR(TIMESTAMP_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.IDENTIFIER(4'b0101)
) i_timestamp (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.CLK(CLK),
.DI(PULSE),
.EXT_TIMESTAMP(TIMESTAMP),
.TIMESTAMP_OUT(TIMESTAMP_OUT),
.FIFO_READ(FIFO_READ),
.FIFO_EMPTY(FIFO_EMPTY),
.FIFO_DATA(FIFO_DATA)
);
bram_fifo #(
.BASEADDR(FIFO_BASEADDR),
.HIGHADDR(FIFO_HIGHADDR),
.BASEADDR_DATA(FIFO_BASEADDR_DATA),
.HIGHADDR_DATA(FIFO_HIGHADDR_DATA),
.ABUSWIDTH(ABUSWIDTH)
) i_out_fifo (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.FIFO_READ_NEXT_OUT(FIFO_READ),
.FIFO_EMPTY_IN(FIFO_EMPTY),
.FIFO_DATA(FIFO_DATA),
.FIFO_NOT_EMPTY(),
.FIFO_FULL(),
.FIFO_NEAR_FULL(),
.FIFO_READ_ERROR()
);
initial begin
$dumpfile("timestamp.vcd");
$dumpvars(0);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND3_2_V
`define SKY130_FD_SC_HD__AND3_2_V
/**
* and3: 3-input AND.
*
* Verilog wrapper for and3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__and3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND3_2_V
|
`timescale 1 ns / 1 ps
module axis_pulse_height_analyzer #
(
parameter integer AXIS_TDATA_WIDTH = 16,
parameter AXIS_TDATA_SIGNED = "FALSE",
parameter integer CNTR_WIDTH = 16
)
(
// System signals
input wire aclk,
input wire aresetn,
input wire [CNTR_WIDTH-1:0] cfg_data,
input wire [AXIS_TDATA_WIDTH-1:0] min_data,
input wire [AXIS_TDATA_WIDTH-1:0] max_data,
// Slave side
output wire s_axis_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
// Master side
input wire m_axis_tready,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid
);
reg [AXIS_TDATA_WIDTH-1:0] int_data_reg[1:0], int_data_next[1:0];
reg [AXIS_TDATA_WIDTH-1:0] int_min_reg, int_min_next;
reg [AXIS_TDATA_WIDTH-1:0] int_tdata_reg, int_tdata_next;
reg [CNTR_WIDTH-1:0] int_cntr_reg, int_cntr_next;
reg int_enbl_reg, int_enbl_next;
reg int_rising_reg, int_rising_next;
reg int_tvalid_reg, int_tvalid_next;
wire [AXIS_TDATA_WIDTH-1:0] int_tdata_wire;
wire int_mincut_wire, int_maxcut_wire, int_rising_wire, int_delay_wire;
assign int_delay_wire = int_cntr_reg < cfg_data;
generate
if(AXIS_TDATA_SIGNED == "TRUE")
begin : SIGNED
assign int_rising_wire = $signed(int_data_reg[1]) < $signed(s_axis_tdata);
assign int_tdata_wire = $signed(int_data_reg[0]) - $signed(int_min_reg);
assign int_mincut_wire = $signed(int_tdata_wire) > $signed(min_data);
assign int_maxcut_wire = $signed(int_data_reg[0]) < $signed(max_data);
end
else
begin : UNSIGNED
assign int_rising_wire = int_data_reg[1] < s_axis_tdata;
assign int_tdata_wire = int_data_reg[0] - int_min_reg;
assign int_mincut_wire = int_tdata_wire > min_data;
assign int_maxcut_wire = int_data_reg[0] < max_data;
end
endgenerate
always @(posedge aclk)
begin
if(~aresetn)
begin
int_data_reg[0] <= {(AXIS_TDATA_WIDTH){1'b0}};
int_data_reg[1] <= {(AXIS_TDATA_WIDTH){1'b0}};
int_tdata_reg <= {(AXIS_TDATA_WIDTH){1'b0}};
int_min_reg <= {(AXIS_TDATA_WIDTH){1'b0}};
int_cntr_reg <= {(CNTR_WIDTH){1'b0}};
int_enbl_reg <= 1'b0;
int_rising_reg <= 1'b0;
int_tvalid_reg <= 1'b0;
end
else
begin
int_data_reg[0] <= int_data_next[0];
int_data_reg[1] <= int_data_next[1];
int_tdata_reg <= int_tdata_next;
int_min_reg <= int_min_next;
int_cntr_reg <= int_cntr_next;
int_enbl_reg <= int_enbl_next;
int_rising_reg <= int_rising_next;
int_tvalid_reg <= int_tvalid_next;
end
end
always @*
begin
int_data_next[0] = int_data_reg[0];
int_data_next[1] = int_data_reg[1];
int_tdata_next = int_tdata_reg;
int_min_next = int_min_reg;
int_cntr_next = int_cntr_reg;
int_enbl_next = int_enbl_reg;
int_rising_next = int_rising_reg;
int_tvalid_next = int_tvalid_reg;
if(s_axis_tvalid)
begin
int_data_next[0] = s_axis_tdata;
int_data_next[1] = int_data_reg[0];
int_rising_next = int_rising_wire;
end
if(s_axis_tvalid & int_delay_wire)
begin
int_cntr_next = int_cntr_reg + 1'b1;
end
// minimum after delay
if(s_axis_tvalid & ~int_delay_wire & ~int_rising_reg & int_rising_wire)
begin
int_min_next = int_data_reg[1];
int_enbl_next = 1'b1;
end
// maximum after minimum
if(s_axis_tvalid & int_enbl_reg & int_rising_reg & ~int_rising_wire & int_mincut_wire)
begin
int_tdata_next = int_tdata_wire;
int_tvalid_next = int_maxcut_wire;
int_cntr_next = {(CNTR_WIDTH){1'b0}};
end
if(m_axis_tready & int_tvalid_reg)
begin
int_tvalid_next = 1'b0;
end
end
assign s_axis_tready = 1'b1;
assign m_axis_tdata = int_tdata_reg;
assign m_axis_tvalid = int_tvalid_reg;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND4_4_V
`define SKY130_FD_SC_LS__AND4_4_V
/**
* and4: 4-input AND.
*
* Verilog wrapper for and4 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__and4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and4_4 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and4_4 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__and4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND4_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__A21OI_FUNCTIONAL_PP_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__a21oi (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21OI_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O22A_BLACKBOX_V
`define SKY130_FD_SC_HS__O22A_BLACKBOX_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o22a (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O22A_BLACKBOX_V
|
// file: ClockDivider.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1___108.000______0.000______50.0______221.150____300.991
// CLK_OUT2____15.000______0.000______50.0______303.688____300.991
// CLK_OUT3____30.000______0.000______50.0______270.092____300.991
// CLK_OUT4____90.000______0.000______50.0______226.688____300.991
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
module ClockDivider_clk_wiz
(// Clock in ports
input clkIn,
// Clock out ports
output clk108M,
output clk_cpu,
output clk2cpu,
output clk6cpu
);
// Input buffering
//------------------------------------
IBUF clkin1_ibufg
(.O (clkIn_ClockDivider),
.I (clkIn));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_ClockDivider;
wire clkfbout_buf_ClockDivider;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2b_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (5),
.CLKFBOUT_MULT_F (54.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (10.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (72),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (36),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKOUT3_DIVIDE (12),
.CLKOUT3_PHASE (0.000),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT3_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.0))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_ClockDivider),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk108M_ClockDivider),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clk_cpu_ClockDivider),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clk2cpu_ClockDivider),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clk6cpu_ClockDivider),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_ClockDivider),
.CLKIN1 (clkIn_ClockDivider),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (1'b0));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_ClockDivider),
.I (clkfbout_ClockDivider));
BUFG clkout1_buf
(.O (clk108M),
.I (clk108M_ClockDivider));
BUFG clkout2_buf
(.O (clk_cpu),
.I (clk_cpu_ClockDivider));
BUFG clkout3_buf
(.O (clk2cpu),
.I (clk2cpu_ClockDivider));
BUFG clkout4_buf
(.O (clk6cpu),
.I (clk6cpu_ClockDivider));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFSBP_PP_SYMBOL_V
`define SKY130_FD_SC_LS__DFSBP_PP_SYMBOL_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dfsbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input SET_B,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFSBP_PP_SYMBOL_V
|
/*!
* \file histogram.v
* \brief Software configurable hardware Histogram core
* \author Luca Maggiani
*
* \version 1.0 (Mar13) - first release, it finally works! static 8x8bins
* \version 1.1 (24Apr13) - Adapted to Camera_OneFrame v3.0 Architecture
* \version 3.0 (Jan14) - Major revision, completely rewritten,
* Configurable cell width, height, bins
* Reduced memory footprint by a factor of 2
* Store phase revision (bug during phase switch)
* \version 3.0.1 (14Jan14) - active_cell signal for odd cell width
* \version 3.0.2 (15Jan14) - Store phase revision with count_store_extended
* \version 3.1 (18Feb15) - flow valid interfaces and generic bus size added.
*
* \date Feb 2015
* \pre ram_cell, ram_subcell and ram_module instances
* \param[in] index_fv, index_dv, index_data, inc_fv, inc_dv, inc_data
* \param[out] hist_fv, hist_dv, hist_data
*
* \see ram_cell
* \see ram_subcell
* \see ram_module
*
* \todo input flows synchronisation! (dv_int and fv_int gen)
*/
/*! \f$
\begin{tabular} {|c|c|c|c|}
\hline
\textbf{Offset} & \textbf{Name} & \textbf{R/W} & \textbf{Descriptions of Bits} \\
\hline
0x00 & Status Control & RW & N\_BIN\_EXP\big[5:2\big], MODE\big[1\big], ONOFF\big[0\big]\\
\hline
0x01 & CellControl & RW & cellheight\big[25:16\big], cellwidth\big[9:0\big]\\
\hline
0x02 & ImageControl & RW & cellinrow\big[9:0\big] \\
\hline
0x03 & StoreCycles & RW & storecycles\big[15:0\big]\\
\hline
\end{tabular}
\f$
*/
module histogram(
clk_proc,
reset_n,
index_fv,
index_dv,
index_data,
inc_fv,
inc_dv,
inc_data,
hist_fv,
hist_dv,
hist_data,
addr_rel_i,
wr_i,
datawr_i,
rd_i,
datard_o
);
/* Flows size */
parameter INC_SIZE = 16;
parameter INDEX_SIZE = 8;
parameter HIST_SIZE = 16;
/* Clock param */
parameter CLK_PROC_FREQ = 50000000;
parameter HISTMEM_WORD = 2048;
localparam HISTMEM_ADDR_WIDTH = $clog2(HISTMEM_WORD);
input clk_proc;
input reset_n;
input inc_fv;
input inc_dv;
input [(INC_SIZE-1):0] inc_data;
input index_fv;
input index_dv;
input [(INDEX_SIZE-1):0] index_data;
output hist_fv;
output hist_dv;
output [(HIST_SIZE-1):0] hist_data;
//% \{
//% Avalon-MM interface
//%
input [1:0] addr_rel_i;
input wr_i;
input rd_i;
input [31:0] datawr_i;
output [31:0] datard_o;
//% \}
/*! \{ Status and Control Register */
reg [31:0] scr, scr_new;
/*! \} */
/*! \{ Avalon-MM Parameters */
reg [31:0] cellcontrol, cellcontrol_new;
reg [31:0] imagecontrol, imagecontrol_new;
reg [31:0] storecycles, storecycles_new;
/*! \} */
/*! \{ Internal registers */
reg [31:0] readdata, readdata_new;
/* \} */
/*! \{ Internal wires */
wire [9:0] cellheight;
wire [9:0] cellwidth;
wire [9:0] cellinrow;
wire onoff;
wire mode;
wire [3:0] n_bin_exp;
wire dv_int;
wire fv_int;
wire storecompleted_cellA;
wire storecompleted_cellB;
wire data_valid_cellA;
wire data_valid_cellB;
wire [HIST_SIZE-1:0] data_out_cellA;
wire [HIST_SIZE-1:0] data_out_cellB;
wire data_valid_out_cellA;
wire data_valid_out_cellB;
wire loadcompleted_cellA;
wire loadcompleted_cellB;
/* \} */
/*! \{ Output flow valid fsm */
reg [1:0] hist_fv_fsm, hist_fv_fsm_new;
reg hist_fv_reg;
reg fv_int_reg;
localparam WAIT_A_LOADCOMPL = 2'd0;
localparam WAIT_A_STORECOMPL = 2'd1;
localparam WAIT_B_LOADCOMPL = 2'd2;
localparam WAIT_B_STORECOMPL = 2'd3;
/* \} */
/*! \{ Output flow valid fsm */
reg [1:0] histogram_fsm, histogram_fsm_new;
localparam START_STATE = 2'd0;
localparam WAIT_A_STATE = 2'd1;
localparam WAIT_B_STATE = 2'd2;
/* \} */
/*! \{ Output flow */
reg dv_out_s;
reg [HIST_SIZE-1:0] data_out;
/* \} */
/* ################################### */
/* Input flows synchronisation */
assign dv_int = inc_dv & index_dv & onoff;
assign fv_int = inc_fv & index_fv & onoff;
/* ################################### */
/* Input data management */
always@(posedge clk_proc or negedge reset_n)
if (reset_n == 0)
histogram_fsm <= START_STATE;
else
histogram_fsm <= histogram_fsm_new;
always@(*)
case (histogram_fsm)
START_STATE:
if (onoff == 1'b0)
histogram_fsm_new = START_STATE;
else
histogram_fsm_new = WAIT_A_STATE;
WAIT_A_STATE:
if (onoff == 1'b0)
histogram_fsm_new = START_STATE;
else
if (loadcompleted_cellA)
histogram_fsm_new = WAIT_B_STATE;
else
histogram_fsm_new = WAIT_A_STATE;
WAIT_B_STATE:
if (onoff == 1'b0)
histogram_fsm_new = START_STATE;
else
if (loadcompleted_cellB)
histogram_fsm_new = WAIT_A_STATE;
else
histogram_fsm_new = WAIT_B_STATE;
default:
histogram_fsm_new = START_STATE;
endcase
always@(posedge clk_proc or negedge reset_n)
if (reset_n == 1'b0)
dv_out_s <= 1'b0;
else
dv_out_s <= (data_valid_out_cellA | data_valid_out_cellB);
always@(posedge clk_proc or negedge reset_n)
if (reset_n == 1'b0)
data_out <= 16'd0;
else
if (histogram_fsm == WAIT_A_STATE)
data_out <= data_out_cellB;
else if (histogram_fsm == WAIT_B_STATE)
data_out <= data_out_cellA;
else
data_out <= 16'b0;
//% \brief Data valid to cells
//% \todo Right now it works with a synchronous static exception,
//% I hope to find a cleaner solution (more elegant at least)
//% \{
assign data_valid_cellA = dv_int & ((histogram_fsm == WAIT_A_STATE)| loadcompleted_cellB) &~loadcompleted_cellA;
assign data_valid_cellB = dv_int & ((histogram_fsm == WAIT_B_STATE)| loadcompleted_cellA) &~loadcompleted_cellB;
//% \}
/* ################################### */
/* hist_fv management (output flow) */
always@(posedge clk_proc or negedge reset_n)
if (reset_n == 0)
hist_fv_fsm <= 0;
else
hist_fv_fsm <= hist_fv_fsm_new;
always@(*)
case (hist_fv_fsm)
WAIT_A_LOADCOMPL:
if (onoff == 0)
hist_fv_fsm_new = WAIT_A_LOADCOMPL;
else
if (loadcompleted_cellA)
hist_fv_fsm_new = WAIT_A_STORECOMPL;
else
hist_fv_fsm_new = WAIT_A_LOADCOMPL;
WAIT_A_STORECOMPL:
if (onoff == 0)
hist_fv_fsm_new = WAIT_A_LOADCOMPL;
else
if (storecompleted_cellA)
hist_fv_fsm_new = WAIT_B_LOADCOMPL;
else
hist_fv_fsm_new = WAIT_A_STORECOMPL;
WAIT_B_LOADCOMPL:
if (onoff == 0)
hist_fv_fsm_new = WAIT_A_LOADCOMPL;
else
if (loadcompleted_cellB)
hist_fv_fsm_new = WAIT_B_STORECOMPL;
else
hist_fv_fsm_new = WAIT_B_LOADCOMPL;
WAIT_B_STORECOMPL:
if (onoff == 0)
hist_fv_fsm_new = WAIT_A_LOADCOMPL;
else
if (storecompleted_cellB)
hist_fv_fsm_new = WAIT_A_LOADCOMPL;
else
hist_fv_fsm_new = WAIT_B_STORECOMPL;
default:
hist_fv_fsm_new = WAIT_A_LOADCOMPL;
endcase
always@(posedge clk_proc or negedge reset_n)
if (reset_n == 0)
fv_int_reg <= 0;
else
fv_int_reg <= fv_int;
always@(posedge clk_proc or negedge reset_n)
if (reset_n == 0)
hist_fv_reg <= 0;
else
hist_fv_reg <= fv_int_reg || (hist_fv_fsm == WAIT_A_STORECOMPL) || (hist_fv_fsm == WAIT_B_STORECOMPL);
/* ################### */
//% \brief output flow assignmenent
//% \{
assign hist_fv = hist_fv_reg;
assign hist_dv = dv_out_s;
assign hist_data = data_out;
//% \}
//% \brief ram_cellA instantiation
//% \{
ram_cell
#( .HISTMEM_WORD(HISTMEM_WORD),
.HISTOGRAM_WIDTH(HIST_SIZE)) ram_cellA(
.clk(clk_proc),
.reset_n(reset_n),
.data_in(inc_data),
.dir_max(index_data),
.data_valid_in(data_valid_cellA),
.data_out(data_out_cellA),
.data_valid_out(data_valid_out_cellA),
.cellwidth(cellwidth),
.cellinrow(cellinrow),
.cellheight(cellheight),
.storecycles(storecycles[15:0]),
.onoff(onoff),
.mode(mode),
.n_bin_exp(n_bin_exp),
.newcell_signal(),
.newline_signal(),
.loadcompleted(loadcompleted_cellA),
.storecompleted(storecompleted_cellA),
.count_store_int(),
.address_a_int()
);
//% \}
//% \brief ram_cellA instantiation
//% \{
ram_cell
#( .HISTMEM_WORD(HISTMEM_WORD),
.HISTOGRAM_WIDTH(HIST_SIZE)) ram_cellB(
.clk(clk_proc),
.reset_n(reset_n),
.data_in(inc_data),
.dir_max(index_data),
.data_valid_in(data_valid_cellB),
.data_out(data_out_cellB),
.data_valid_out(data_valid_out_cellB),
.cellwidth(cellwidth),
.cellinrow(cellinrow),
.cellheight(cellheight),
.storecycles(storecycles[15:0]),
.onoff(onoff),
.mode(mode),
.n_bin_exp(n_bin_exp),
.newcell_signal(),
.newline_signal(),
.loadcompleted(loadcompleted_cellB),
.storecompleted(storecompleted_cellB),
.count_store_int(),
.address_a_int()
);
//% \}
/* -------------- Avalon-MM Interface --------------
SCR - R/W
CELLCONTROL - R/W
IMAGECONTROL - R/W
STORECYCLES - R/W
*/
assign cellheight = cellcontrol[25:16];
assign cellwidth = cellcontrol[9:0];
assign cellinrow = imagecontrol[9:0];
assign onoff = scr[0];
assign mode = scr[1];
assign n_bin_exp = scr[5:2];
//%
//% Avalon-MM registers write
//% \code
always @ (*)
if (wr_i)
case(addr_rel_i)
2'd0:
begin
scr_new = datawr_i;
cellcontrol_new = cellcontrol;
imagecontrol_new = imagecontrol;
storecycles_new = storecycles;
end
2'd1:
begin
scr_new = scr;
cellcontrol_new = datawr_i;
imagecontrol_new = imagecontrol;
storecycles_new = storecycles;
end
2'd2:
begin
scr_new = scr;
cellcontrol_new = cellcontrol;
imagecontrol_new = datawr_i;
storecycles_new = storecycles;
end
2'd3:
begin
scr_new = scr;
cellcontrol_new = cellcontrol;
imagecontrol_new = imagecontrol;
storecycles_new = datawr_i;
end
default:
begin
scr_new = scr;
cellcontrol_new = cellcontrol;
imagecontrol_new = imagecontrol;
storecycles_new = storecycles;
end
endcase
else /* write disabled */
begin
scr_new = scr;
cellcontrol_new = cellcontrol;
imagecontrol_new = imagecontrol;
storecycles_new = storecycles;
end
//% \endcode
/*! Read phase
*/
always @ (*)
if (rd_i)
case(addr_rel_i)
2'd0: readdata_new = scr;
2'd1: readdata_new = cellcontrol;
2'd2: readdata_new = imagecontrol;
2'd3: readdata_new = storecycles;
default: readdata_new = 32'd0;
endcase
else
readdata_new = readdata;
/* Internal register update */
always @ (posedge clk_proc or negedge reset_n)
if (reset_n == 1'b0)
begin
scr <= 32'd0;
cellcontrol[31:16] <= 16'd7;
cellcontrol[15:0] <= 16'd7;
imagecontrol <= 32'd39;
storecycles <= 32'd640;
readdata <= 32'd0;
end
else
begin
scr <= scr_new;
cellcontrol <= cellcontrol_new;
imagecontrol <= imagecontrol_new;
storecycles <= storecycles_new;
readdata <= readdata_new;
end
assign datard_o = readdata;
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_arb_wr_4.v
*
* Date : 2012-11
*
* Description : Module that arbitrates between 4 write requests from 4 ports.
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_arb_wr_4(
rstn,
sw_clk,
qos1,
qos2,
qos3,
qos4,
prt_dv1,
prt_dv2,
prt_dv3,
prt_dv4,
prt_data1,
prt_data2,
prt_data3,
prt_data4,
prt_addr1,
prt_addr2,
prt_addr3,
prt_addr4,
prt_bytes1,
prt_bytes2,
prt_bytes3,
prt_bytes4,
prt_ack1,
prt_ack2,
prt_ack3,
prt_ack4,
prt_qos,
prt_req,
prt_data,
prt_addr,
prt_bytes,
prt_ack
);
`include "processing_system7_bfm_v2_0_local_params.v"
input rstn, sw_clk;
input [axi_qos_width-1:0] qos1,qos2,qos3,qos4;
input [max_burst_bits-1:0] prt_data1,prt_data2,prt_data3,prt_data4;
input [addr_width-1:0] prt_addr1,prt_addr2,prt_addr3,prt_addr4;
input [max_burst_bytes_width:0] prt_bytes1,prt_bytes2,prt_bytes3,prt_bytes4;
input prt_dv1, prt_dv2,prt_dv3, prt_dv4, prt_ack;
output reg prt_ack1,prt_ack2,prt_ack3,prt_ack4,prt_req;
output reg [max_burst_bits-1:0] prt_data;
output reg [addr_width-1:0] prt_addr;
output reg [max_burst_bytes_width:0] prt_bytes;
output reg [axi_qos_width-1:0] prt_qos;
parameter wait_req = 3'b000, serv_req1 = 3'b001, serv_req2 = 3'b010, serv_req3 = 3'b011, serv_req4 = 4'b100,wait_ack_low = 3'b101;
reg [2:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
state = wait_req;
prt_req = 1'b0;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
prt_qos = 0;
end else begin
case(state)
wait_req:begin
state = wait_req;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
prt_req = 0;
if(prt_dv1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_dv2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_dv4) begin
prt_req = 1;
prt_qos = qos4;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
serv_req1:begin
state = serv_req1;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
if(prt_ack)begin
prt_ack1 = 1'b1;
//state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv2) begin
state = serv_req2;
prt_qos = qos2;
prt_req = 1;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv3) begin
state = serv_req3;
prt_req = 1;
prt_qos = qos3;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_dv4) begin
prt_req = 1;
prt_qos = qos4;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
state = serv_req4;
end
end
end
serv_req2:begin
state = serv_req2;
prt_ack1 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
if(prt_ack)begin
prt_ack2 = 1'b1;
//state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv3) begin
state = serv_req3;
prt_qos = qos3;
prt_req = 1;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
end else if(prt_dv4) begin
state = serv_req4;
prt_req = 1;
prt_qos = qos4;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_dv1) begin
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end
end
end
serv_req3:begin
state = serv_req3;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack4 = 1'b0;
if(prt_ack)begin
prt_ack3 = 1'b1;
// state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv4) begin
state = serv_req4;
prt_qos = qos4;
prt_req = 1;
prt_data = prt_data4;
prt_addr = prt_addr4;
prt_bytes = prt_bytes4;
end else if(prt_dv1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_dv2) begin
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end
end
end
serv_req4:begin
state = serv_req4;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
if(prt_ack)begin
prt_ack4 = 1'b1;
//state = wait_req;
state = wait_ack_low;
prt_req = 0;
if(prt_dv1) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_data = prt_data1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(prt_dv2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_data = prt_data2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_dv3) begin
prt_req = 1;
prt_qos = qos3;
prt_data = prt_data3;
prt_addr = prt_addr3;
prt_bytes = prt_bytes3;
state = serv_req3;
end
end
end
wait_ack_low:begin
state = wait_ack_low;
prt_ack1 = 1'b0;
prt_ack2 = 1'b0;
prt_ack3 = 1'b0;
prt_ack4 = 1'b0;
if(!prt_ack)
state = wait_req;
end
endcase
end /// if else
end /// always
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE General-Purpose I/O ////
//// ////
//// This file is part of the GPIO project ////
//// http://www.opencores.org/cores/gpio/ ////
//// ////
//// Description ////
//// Implementation of GPIO IP core according to ////
//// GPIO IP core specification document. ////
//// ////
//// To Do: ////
//// Nothing ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.17 2004/05/05 08:21:00 andreje
// Bugfixes when GPIO_RGPIO_ECLK/GPIO_RGPIO_NEC disabled, gpio oe name change and set to active-high according to spec
//
// Revision 1.16 2003/12/17 13:00:52 gorand
// added ECLK and NEC registers, all tests passed.
//
// Revision 1.15 2003/11/10 23:21:22 gorand
// bug fixed. all tests passed.
//
// Revision 1.14 2003/11/06 13:59:07 gorand
// added support for 8-bit access to registers.
//
// Revision 1.13 2002/11/18 22:35:18 lampret
// Bug fix. Interrupts were also asserted when condition was not met.
//
// Revision 1.12 2002/11/11 21:36:28 lampret
// Added ifdef to remove mux from clk_pad_i if mux is not allowed. This also removes RGPIO_CTRL[NEC].
//
// Revision 1.11 2002/03/13 20:56:28 lampret
// Removed zero padding as per Avi Shamli suggestion.
//
// Revision 1.10 2002/03/13 20:47:57 lampret
// Ports changed per Ran Aviram suggestions.
//
// Revision 1.9 2002/03/09 03:43:27 lampret
// Interrupt is asserted only when an input changes (code patch by Jacob Gorban)
//
// Revision 1.8 2002/01/14 19:06:28 lampret
// Changed registered WISHBONE outputs wb_ack_o/wb_err_o to follow WB specification.
//
// Revision 1.7 2001/12/25 17:21:21 lampret
// Fixed two typos.
//
// Revision 1.6 2001/12/25 17:12:35 lampret
// Added RGPIO_INTS.
//
// Revision 1.5 2001/12/12 20:35:53 lampret
// Fixing style.
//
// Revision 1.4 2001/12/12 07:12:58 lampret
// Fixed bug when wb_inta_o is registered (GPIO_WB_REGISTERED_OUTPUTS)
//
// Revision 1.3 2001/11/15 02:24:37 lampret
// Added GPIO_REGISTERED_WB_OUTPUTS, GPIO_REGISTERED_IO_OUTPUTS and GPIO_NO_NEGEDGE_FLOPS.
//
// Revision 1.2 2001/10/31 02:26:51 lampret
// Fixed wb_err_o.
//
// Revision 1.1 2001/09/18 18:49:07 lampret
// Changed top level ptc into gpio_top. Changed defines.v into gpio_defines.v.
//
// Revision 1.1 2001/08/21 21:39:28 lampret
// Changed directory structure, port names and drfines.
//
// Revision 1.2 2001/07/14 20:39:26 lampret
// Better configurability.
//
// Revision 1.1 2001/06/05 07:45:26 lampret
// Added initial RTL and test benches. There are still some issues with these files.
//
//
// synopsys translate_off
//`include "timescale.v"
// synopsys translate_on
`include "gpio_defines.v"
module gpio_top(
// WISHBONE Interface
wb_clk_i, wb_rst_i, wb_cyc_i, wb_adr_i, wb_dat_i, wb_sel_i, wb_we_i, wb_stb_i,
wb_dat_o, wb_ack_o, wb_err_o, wb_inta_o,
`ifdef GPIO_AUX_IMPLEMENT
// Auxiliary inputs interface
aux_i,
`endif // GPIO_AUX_IMPLEMENT
// External GPIO Interface
ext_pad_i, ext_pad_o, ext_padoe_o
`ifdef GPIO_CLKPAD
, clk_pad_i
`endif
);
parameter dw = 32;
parameter aw = `GPIO_ADDRHH+1;
parameter gw = `GPIO_IOS;
//
// WISHBONE Interface
//
input wb_clk_i; // Clock
input wb_rst_i; // Reset
input wb_cyc_i; // cycle valid input
input [aw-1:0] wb_adr_i; // address bus inputs
input [dw-1:0] wb_dat_i; // input data bus
input [3:0] wb_sel_i; // byte select inputs
input wb_we_i; // indicates write transfer
input wb_stb_i; // strobe input
output [dw-1:0] wb_dat_o; // output data bus
output wb_ack_o; // normal termination
output wb_err_o; // termination w/ error
output wb_inta_o; // Interrupt request output
`ifdef GPIO_AUX_IMPLEMENT
// Auxiliary Inputs Interface
input [gw-1:0] aux_i; // Auxiliary inputs
`endif // GPIO_AUX_IMPLEMENT
//
// External GPIO Interface
//
input [gw-1:0] ext_pad_i; // GPIO Inputs
`ifdef GPIO_CLKPAD
input clk_pad_i; // GPIO Eclk
`endif // GPIO_CLKPAD
output [gw-1:0] ext_pad_o; // GPIO Outputs
output [gw-1:0] ext_padoe_o; // GPIO output drivers enables
`ifdef GPIO_IMPLEMENTED
//
// GPIO Input Register (or no register)
//
`ifdef GPIO_RGPIO_IN
reg [gw-1:0] rgpio_in; // RGPIO_IN register
`else
wire [gw-1:0] rgpio_in; // No register
`endif
//
// GPIO Output Register (or no register)
//
`ifdef GPIO_RGPIO_OUT
reg [gw-1:0] rgpio_out; // RGPIO_OUT register
`else
wire [gw-1:0] rgpio_out; // No register
`endif
//
// GPIO Output Driver Enable Register (or no register)
//
`ifdef GPIO_RGPIO_OE
reg [gw-1:0] rgpio_oe; // RGPIO_OE register
`else
wire [gw-1:0] rgpio_oe; // No register
`endif
//
// GPIO Interrupt Enable Register (or no register)
//
`ifdef GPIO_RGPIO_INTE
reg [gw-1:0] rgpio_inte; // RGPIO_INTE register
`else
wire [gw-1:0] rgpio_inte; // No register
`endif
//
// GPIO Positive edge Triggered Register (or no register)
//
`ifdef GPIO_RGPIO_PTRIG
reg [gw-1:0] rgpio_ptrig; // RGPIO_PTRIG register
`else
wire [gw-1:0] rgpio_ptrig; // No register
`endif
//
// GPIO Auxiliary select Register (or no register)
//
`ifdef GPIO_RGPIO_AUX
reg [gw-1:0] rgpio_aux; // RGPIO_AUX register
`else
wire [gw-1:0] rgpio_aux; // No register
`endif
//
// GPIO Control Register (or no register)
//
`ifdef GPIO_RGPIO_CTRL
reg [1:0] rgpio_ctrl; // RGPIO_CTRL register
`else
wire [1:0] rgpio_ctrl; // No register
`endif
//
// GPIO Interrupt Status Register (or no register)
//
`ifdef GPIO_RGPIO_INTS
reg [gw-1:0] rgpio_ints; // RGPIO_INTS register
`else
wire [gw-1:0] rgpio_ints; // No register
`endif
//
// GPIO Enable Clock Register (or no register)
//
`ifdef GPIO_RGPIO_ECLK
reg [gw-1:0] rgpio_eclk; // RGPIO_ECLK register
`else
wire [gw-1:0] rgpio_eclk; // No register
`endif
//
// GPIO Active Negative Edge Register (or no register)
//
`ifdef GPIO_RGPIO_NEC
reg [gw-1:0] rgpio_nec; // RGPIO_NEC register
`else
wire [gw-1:0] rgpio_nec; // No register
`endif
//
// Synchronization flops for input signals
//
`ifdef GPIO_SYNC_IN_WB
reg [gw-1:0] sync ,
ext_pad_s ;
`else
wire [gw-1:0] ext_pad_s ;
`endif
//
// Internal wires & regs
//
wire rgpio_out_sel; // RGPIO_OUT select
wire rgpio_oe_sel; // RGPIO_OE select
wire rgpio_inte_sel; // RGPIO_INTE select
wire rgpio_ptrig_sel;// RGPIO_PTRIG select
wire rgpio_aux_sel; // RGPIO_AUX select
wire rgpio_ctrl_sel; // RGPIO_CTRL select
wire rgpio_ints_sel; // RGPIO_INTS select
wire rgpio_eclk_sel ;
wire rgpio_nec_sel ;
wire full_decoding; // Full address decoding qualification
wire [gw-1:0] in_muxed; // Muxed inputs
wire wb_ack; // WB Acknowledge
wire wb_err; // WB Error
wire wb_inta; // WB Interrupt
reg [dw-1:0] wb_dat; // WB Data out
`ifdef GPIO_REGISTERED_WB_OUTPUTS
reg wb_ack_o; // WB Acknowledge
reg wb_err_o; // WB Error
reg wb_inta_o; // WB Interrupt
reg [dw-1:0] wb_dat_o; // WB Data out
`endif
wire [gw-1:0] out_pad; // GPIO Outputs
`ifdef GPIO_REGISTERED_IO_OUTPUTS
reg [gw-1:0] ext_pad_o; // GPIO Outputs
`endif
`ifdef GPIO_CLKPAD
wire [gw-1:0] extc_in; // Muxed inputs sampled by external clock
wire [gw-1:0] pext_clk; // External clock for posedge flops
reg [gw-1:0] pextc_sampled; // Posedge external clock sampled inputs
`ifdef GPIO_NO_NEGEDGE_FLOPS
`ifdef GPIO_NO_CLKPAD_LOGIC
`else
reg [gw-1:0] nextc_sampled; // Negedge external clock sampled inputs
`endif // GPIO_NO_CLKPAD_LOGIC
`else
reg [gw-1:0] nextc_sampled; // Negedge external clock sampled inputs
`endif
`endif // GPIO_CLKPAD
//
// All WISHBONE transfer terminations are successful except when:
// a) full address decoding is enabled and address doesn't match
// any of the GPIO registers
// b) wb_sel_i evaluation is enabled and one of the wb_sel_i inputs is zero
//
//
// WB Acknowledge
//
assign wb_ack = wb_cyc_i & wb_stb_i & !wb_err_o;
//
// Optional registration of WB Ack
//
`ifdef GPIO_REGISTERED_WB_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
wb_ack_o <= #1 1'b0;
else
wb_ack_o <= #1 wb_ack & ~wb_ack_o & (!wb_err) ;
`else
assign wb_ack_o = wb_ack;
`endif
//
// WB Error
//
`ifdef GPIO_FULL_DECODE
`ifdef GPIO_STRICT_32BIT_ACCESS
assign wb_err = wb_cyc_i & wb_stb_i & (!full_decoding | (wb_sel_i != 4'b1111));
`else
assign wb_err = wb_cyc_i & wb_stb_i & !full_decoding;
`endif
`else
`ifdef GPIO_STRICT_32BIT_ACCESS
assign wb_err = wb_cyc_i & wb_stb_i & (wb_sel_i != 4'b1111);
`else
assign wb_err = 1'b0;
`endif
`endif
//
// Optional registration of WB error
//
`ifdef GPIO_REGISTERED_WB_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
wb_err_o <= #1 1'b0;
else
wb_err_o <= #1 wb_err & ~wb_err_o;
`else
assign wb_err_o = wb_err;
`endif
//
// Full address decoder
//
`ifdef GPIO_FULL_DECODE
assign full_decoding = (wb_adr_i[`GPIO_ADDRHH:`GPIO_ADDRHL] == {`GPIO_ADDRHH-`GPIO_ADDRHL+1{1'b0}}) &
(wb_adr_i[`GPIO_ADDRLH:`GPIO_ADDRLL] == {`GPIO_ADDRLH-`GPIO_ADDRLL+1{1'b0}});
`else
assign full_decoding = 1'b1;
`endif
//
// GPIO registers address decoder
//
`ifdef GPIO_RGPIO_OUT
assign rgpio_out_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OUT) & full_decoding;
`endif
`ifdef GPIO_RGPIO_OE
assign rgpio_oe_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_OE) & full_decoding;
`endif
`ifdef GPIO_RGPIO_INTE
assign rgpio_inte_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTE) & full_decoding;
`endif
`ifdef GPIO_RGPIO_PTRIG
assign rgpio_ptrig_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_PTRIG) & full_decoding;
`endif
`ifdef GPIO_RGPIO_AUX
assign rgpio_aux_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_AUX) & full_decoding;
`endif
`ifdef GPIO_RGPIO_CTRL
assign rgpio_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding;
`endif
`ifdef GPIO_RGPIO_INTS
assign rgpio_ints_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTS) & full_decoding;
`endif
`ifdef GPIO_RGPIO_ECLK
assign rgpio_eclk_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_ECLK) & full_decoding;
`endif
`ifdef GPIO_RGPIO_NEC
assign rgpio_nec_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_NEC) & full_decoding;
`endif
//
// Write to RGPIO_CTRL or update of RGPIO_CTRL[INT] bit
//
`ifdef GPIO_RGPIO_CTRL
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
rgpio_ctrl <= #1 2'b0;
else if (rgpio_ctrl_sel && wb_we_i)
rgpio_ctrl <= #1 wb_dat_i[1:0];
else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] | wb_inta_o;
`else
assign rgpio_ctrl = 2'h01; // RGPIO_CTRL[EN] = 1
`endif
//
// Write to RGPIO_OUT
//
`ifdef GPIO_RGPIO_OUT
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
rgpio_out <= #1 {gw{1'b0}};
else if (rgpio_out_sel && wb_we_i)
begin
`ifdef GPIO_STRICT_32BIT_ACCESS
rgpio_out <= #1 wb_dat_i[gw-1:0];
`endif
`ifdef GPIO_WB_BYTES4
if ( wb_sel_i [3] == 1'b1 )
rgpio_out [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
if ( wb_sel_i [2] == 1'b1 )
rgpio_out [23:16] <= #1 wb_dat_i [23:16] ;
if ( wb_sel_i [1] == 1'b1 )
rgpio_out [15:8] <= #1 wb_dat_i [15:8] ;
if ( wb_sel_i [0] == 1'b1 )
rgpio_out [7:0] <= #1 wb_dat_i [7:0] ;
`endif
`ifdef GPIO_WB_BYTES3
if ( wb_sel_i [2] == 1'b1 )
rgpio_out [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
if ( wb_sel_i [1] == 1'b1 )
rgpio_out [15:8] <= #1 wb_dat_i [15:8] ;
if ( wb_sel_i [0] == 1'b1 )
rgpio_out [7:0] <= #1 wb_dat_i [7:0] ;
`endif
`ifdef GPIO_WB_BYTES2
if ( wb_sel_i [1] == 1'b1 )
rgpio_out [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
if ( wb_sel_i [0] == 1'b1 )
rgpio_out [7:0] <= #1 wb_dat_i [7:0] ;
`endif
`ifdef GPIO_WB_BYTES1
if ( wb_sel_i [0] == 1'b1 )
rgpio_out [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
`endif
end
`else
assign rgpio_out = `GPIO_DEF_RGPIO_OUT; // RGPIO_OUT = 0x0
`endif
//
// Write to RGPIO_OE.
//
`ifdef GPIO_RGPIO_OE
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
rgpio_oe <= #1 {gw{1'b0}};
else if (rgpio_oe_sel && wb_we_i)
begin
`ifdef GPIO_STRICT_32BIT_ACCESS
rgpio_oe <= #1 wb_dat_i[gw-1:0];
`endif
`ifdef GPIO_WB_BYTES4
if ( wb_sel_i [3] == 1'b1 )
rgpio_oe [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
if ( wb_sel_i [2] == 1'b1 )
rgpio_oe [23:16] <= #1 wb_dat_i [23:16] ;
if ( wb_sel_i [1] == 1'b1 )
rgpio_oe [15:8] <= #1 wb_dat_i [15:8] ;
if ( wb_sel_i [0] == 1'b1 )
rgpio_oe [7:0] <= #1 wb_dat_i [7:0] ;
`endif
`ifdef GPIO_WB_BYTES3
if ( wb_sel_i [2] == 1'b1 )
rgpio_oe [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
if ( wb_sel_i [1] == 1'b1 )
rgpio_oe [15:8] <= #1 wb_dat_i [15:8] ;
if ( wb_sel_i [0] == 1'b1 )
rgpio_oe [7:0] <= #1 wb_dat_i [7:0] ;
`endif
`ifdef GPIO_WB_BYTES2
if ( wb_sel_i [1] == 1'b1 )
rgpio_oe [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
if ( wb_sel_i [0] == 1'b1 )
rgpio_oe [7:0] <= #1 wb_dat_i [7:0] ;
`endif
`ifdef GPIO_WB_BYTES1
if ( wb_sel_i [0] == 1'b1 )
rgpio_oe [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
`endif
end
`else
assign rgpio_oe = `GPIO_DEF_RGPIO_OE; // RGPIO_OE = 0x0
`endif
//
// Write to RGPIO_INTE
//
`ifdef GPIO_RGPIO_INTE
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
rgpio_inte <= #1 {gw{1'b0}};
else if (rgpio_inte_sel && wb_we_i)
begin
`ifdef GPIO_STRICT_32BIT_ACCESS
rgpio_inte <= #1 wb_dat_i[gw-1:0];
`endif
`ifdef GPIO_WB_BYTES4
if ( wb_sel_i [3] == 1'b1 )
rgpio_inte [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
if ( wb_sel_i [2] == 1'b1 )
rgpio_inte [23:16] <= #1 wb_dat_i [23:16] ;
if ( wb_sel_i [1] == 1'b1 )
rgpio_inte [15:8] <= #1 wb_dat_i [15:8] ;
if ( wb_sel_i [0] == 1'b1 )
rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ;
`endif
`ifdef GPIO_WB_BYTES3
if ( wb_sel_i [2] == 1'b1 )
rgpio_inte [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
if ( wb_sel_i [1] == 1'b1 )
rgpio_inte [15:8] <= #1 wb_dat_i [15:8] ;
if ( wb_sel_i [0] == 1'b1 )
rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ;
`endif
`ifdef GPIO_WB_BYTES2
if ( wb_sel_i [1] == 1'b1 )
rgpio_inte [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
if ( wb_sel_i [0] == 1'b1 )
rgpio_inte [7:0] <= #1 wb_dat_i [7:0] ;
`endif
`ifdef GPIO_WB_BYTES1
if ( wb_sel_i [0] == 1'b1 )
rgpio_inte [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
`endif
end
`else
assign rgpio_inte = `GPIO_DEF_RGPIO_INTE; // RGPIO_INTE = 0x0
`endif
//
// Write to RGPIO_PTRIG
//
`ifdef GPIO_RGPIO_PTRIG
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
rgpio_ptrig <= #1 {gw{1'b0}};
else if (rgpio_ptrig_sel && wb_we_i)
begin
`ifdef GPIO_STRICT_32BIT_ACCESS
rgpio_ptrig <= #1 wb_dat_i[gw-1:0];
`endif
`ifdef GPIO_WB_BYTES4
if ( wb_sel_i [3] == 1'b1 )
rgpio_ptrig [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
if ( wb_sel_i [2] == 1'b1 )
rgpio_ptrig [23:16] <= #1 wb_dat_i [23:16] ;
if ( wb_sel_i [1] == 1'b1 )
rgpio_ptrig [15:8] <= #1 wb_dat_i [15:8] ;
if ( wb_sel_i [0] == 1'b1 )
rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ;
`endif
`ifdef GPIO_WB_BYTES3
if ( wb_sel_i [2] == 1'b1 )
rgpio_ptrig [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
if ( wb_sel_i [1] == 1'b1 )
rgpio_ptrig [15:8] <= #1 wb_dat_i [15:8] ;
if ( wb_sel_i [0] == 1'b1 )
rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ;
`endif
`ifdef GPIO_WB_BYTES2
if ( wb_sel_i [1] == 1'b1 )
rgpio_ptrig [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
if ( wb_sel_i [0] == 1'b1 )
rgpio_ptrig [7:0] <= #1 wb_dat_i [7:0] ;
`endif
`ifdef GPIO_WB_BYTES1
if ( wb_sel_i [0] == 1'b1 )
rgpio_ptrig [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
`endif
end
`else
assign rgpio_ptrig = `GPIO_DEF_RGPIO_PTRIG; // RGPIO_PTRIG = 0x0
`endif
//
// Write to RGPIO_AUX
//
`ifdef GPIO_RGPIO_AUX
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
rgpio_aux <= #1 {gw{1'b0}};
else if (rgpio_aux_sel && wb_we_i)
begin
`ifdef GPIO_STRICT_32BIT_ACCESS
rgpio_aux <= #1 wb_dat_i[gw-1:0];
`endif
`ifdef GPIO_WB_BYTES4
if ( wb_sel_i [3] == 1'b1 )
rgpio_aux [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
if ( wb_sel_i [2] == 1'b1 )
rgpio_aux [23:16] <= #1 wb_dat_i [23:16] ;
if ( wb_sel_i [1] == 1'b1 )
rgpio_aux [15:8] <= #1 wb_dat_i [15:8] ;
if ( wb_sel_i [0] == 1'b1 )
rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ;
`endif
`ifdef GPIO_WB_BYTES3
if ( wb_sel_i [2] == 1'b1 )
rgpio_aux [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
if ( wb_sel_i [1] == 1'b1 )
rgpio_aux [15:8] <= #1 wb_dat_i [15:8] ;
if ( wb_sel_i [0] == 1'b1 )
rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ;
`endif
`ifdef GPIO_WB_BYTES2
if ( wb_sel_i [1] == 1'b1 )
rgpio_aux [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
if ( wb_sel_i [0] == 1'b1 )
rgpio_aux [7:0] <= #1 wb_dat_i [7:0] ;
`endif
`ifdef GPIO_WB_BYTES1
if ( wb_sel_i [0] == 1'b1 )
rgpio_aux [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
`endif
end
`else
assign rgpio_aux = `GPIO_DEF_RGPIO_AUX; // RGPIO_AUX = 0x0
`endif
//
// Write to RGPIO_ECLK
//
`ifdef GPIO_RGPIO_ECLK
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
rgpio_eclk <= #1 {gw{1'b0}};
else if (rgpio_eclk_sel && wb_we_i)
begin
`ifdef GPIO_STRICT_32BIT_ACCESS
rgpio_eclk <= #1 wb_dat_i[gw-1:0];
`endif
`ifdef GPIO_WB_BYTES4
if ( wb_sel_i [3] == 1'b1 )
rgpio_eclk [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
if ( wb_sel_i [2] == 1'b1 )
rgpio_eclk [23:16] <= #1 wb_dat_i [23:16] ;
if ( wb_sel_i [1] == 1'b1 )
rgpio_eclk [15:8] <= #1 wb_dat_i [15:8] ;
if ( wb_sel_i [0] == 1'b1 )
rgpio_eclk [7:0] <= #1 wb_dat_i [7:0] ;
`endif
`ifdef GPIO_WB_BYTES3
if ( wb_sel_i [2] == 1'b1 )
rgpio_eclk [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
if ( wb_sel_i [1] == 1'b1 )
rgpio_eclk [15:8] <= #1 wb_dat_i [15:8] ;
if ( wb_sel_i [0] == 1'b1 )
rgpio_eclk [7:0] <= #1 wb_dat_i [7:0] ;
`endif
`ifdef GPIO_WB_BYTES2
if ( wb_sel_i [1] == 1'b1 )
rgpio_eclk [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
if ( wb_sel_i [0] == 1'b1 )
rgpio_eclk [7:0] <= #1 wb_dat_i [7:0] ;
`endif
`ifdef GPIO_WB_BYTES1
if ( wb_sel_i [0] == 1'b1 )
rgpio_eclk [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
`endif
end
`else
assign rgpio_eclk = `GPIO_DEF_RGPIO_ECLK; // RGPIO_ECLK = 0x0
`endif
//
// Write to RGPIO_NEC
//
`ifdef GPIO_RGPIO_NEC
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
rgpio_nec <= #1 {gw{1'b0}};
else if (rgpio_nec_sel && wb_we_i)
begin
`ifdef GPIO_STRICT_32BIT_ACCESS
rgpio_nec <= #1 wb_dat_i[gw-1:0];
`endif
`ifdef GPIO_WB_BYTES4
if ( wb_sel_i [3] == 1'b1 )
rgpio_nec [gw-1:24] <= #1 wb_dat_i [gw-1:24] ;
if ( wb_sel_i [2] == 1'b1 )
rgpio_nec [23:16] <= #1 wb_dat_i [23:16] ;
if ( wb_sel_i [1] == 1'b1 )
rgpio_nec [15:8] <= #1 wb_dat_i [15:8] ;
if ( wb_sel_i [0] == 1'b1 )
rgpio_nec [7:0] <= #1 wb_dat_i [7:0] ;
`endif
`ifdef GPIO_WB_BYTES3
if ( wb_sel_i [2] == 1'b1 )
rgpio_nec [gw-1:16] <= #1 wb_dat_i [gw-1:16] ;
if ( wb_sel_i [1] == 1'b1 )
rgpio_nec [15:8] <= #1 wb_dat_i [15:8] ;
if ( wb_sel_i [0] == 1'b1 )
rgpio_nec [7:0] <= #1 wb_dat_i [7:0] ;
`endif
`ifdef GPIO_WB_BYTES2
if ( wb_sel_i [1] == 1'b1 )
rgpio_nec [gw-1:8] <= #1 wb_dat_i [gw-1:8] ;
if ( wb_sel_i [0] == 1'b1 )
rgpio_nec [7:0] <= #1 wb_dat_i [7:0] ;
`endif
`ifdef GPIO_WB_BYTES1
if ( wb_sel_i [0] == 1'b1 )
rgpio_nec [gw-1:0] <= #1 wb_dat_i [gw-1:0] ;
`endif
end
`else
assign rgpio_nec = `GPIO_DEF_RGPIO_NEC; // RGPIO_NEC = 0x0
`endif
//
// synchronize inputs to systam clock
//
`ifdef GPIO_SYNC_IN_WB
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i) begin
sync <= #1 {gw{1'b0}} ;
ext_pad_s <= #1 {gw{1'b0}} ;
end else begin
sync <= #1 ext_pad_i ;
ext_pad_s <= #1 sync ;
end
`else
assign ext_pad_s = ext_pad_i;
`endif // GPIO_SYNC_IN_WB
//
// Latch into RGPIO_IN
//
`ifdef GPIO_RGPIO_IN
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
rgpio_in <= #1 {gw{1'b0}};
else
rgpio_in <= #1 in_muxed;
`else
assign rgpio_in = in_muxed;
`endif
`ifdef GPIO_CLKPAD
`ifdef GPIO_SYNC_CLK_WB
//
// external clock enabled
// synchronized to system clock
// (one clock domain)
//
reg sync_clk,
clk_s ,
clk_r ;
wire pedge ,
nedge ;
wire [gw-1:0] pedge_vec ,
nedge_vec ;
wire [gw-1:0] in_lach ;
assign pedge = clk_s & !clk_r ;
assign nedge = !clk_s & clk_r ;
assign pedge_vec = {gw{pedge}} ;
assign nedge_vec = {gw{nedge}} ;
assign in_lach = (~rgpio_nec & pedge_vec) | (rgpio_nec & nedge_vec) ;
assign extc_in = (in_lach & ext_pad_s) | (~in_lach & pextc_sampled) ;
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i) begin
sync_clk <= #1 1'b0 ;
clk_s <= #1 1'b0 ;
clk_r <= #1 1'b0 ;
end else begin
sync_clk <= #1 clk_pad_i ;
clk_s <= #1 sync_clk ;
clk_r <= #1 clk_s ;
end
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i) begin
pextc_sampled <= #1 {gw{1'b0}};
end else begin
pextc_sampled <= #1 extc_in ;
end
assign in_muxed = (rgpio_eclk & pextc_sampled) | (~rgpio_eclk & ext_pad_s) ;
`else
//
// external clock enabled
// not synchronized to system clock
// (two clock domains)
//
`ifdef GPIO_SYNC_IN_CLK_WB
reg [gw-1:0] syn_extc ,
extc_s ;
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i) begin
syn_extc <= #1 {gw{1'b0}};
extc_s <= #1 {gw{1'b0}};
end else begin
syn_extc <= #1 extc_in ;
extc_s <= #1 syn_extc;
end
`else
wire [gw-1:0] extc_s ;
assign extc_s = syn_extc ;
`endif // GPIO_SYNC_IN_CLK_WB
`ifdef GPIO_SYNC_IN_CLK
reg [gw-1:0] syn_pclk ,
ext_pad_spc ;
always @(posedge clk_pad_i or posedge wb_rst_i)
if (wb_rst_i) begin
syn_pclk <= #1 {gw{1'b0}} ;
ext_pad_spc <= #1 {gw{1'b0}} ;
end else begin
syn_pclk <= #1 ext_pad_i ;
ext_pad_spc <= #1 syn_pclk ;
end
`else
wire [gw-1:0] ext_pad_spc ;
assign ext_pad_spc = ext_pad_i ;
`endif // GPIO_SYNC_IN_CLK
always @(posedge clk_pad_i or posedge wb_rst_i)
if (wb_rst_i) begin
pextc_sampled <= #1 {gw{1'b0}};
end else begin
pextc_sampled <= #1 ext_pad_spc ;
end
`ifdef GPIO_NO_NEGEDGE_FLOPS
`ifdef GPIO_NO_CLKPAD_LOGIC
assign extc_in = pextc_sampled;
`else
wire clk_n;
assign clk_n = !clk_pad_i;
`ifdef GPIO_SYNC_IN_CLK
reg [gw-1:0] syn_nclk ,
ext_pad_snc ;
always @(posedge clk_n or posedge wb_rst_i)
if (wb_rst_i) begin
syn_nclk <= #1 {gw{1'b0}} ;
ext_pad_snc <= #1 {gw{1'b0}} ;
end else begin
syn_nclk <= #1 ext_pad_i ;
ext_pad_snc <= #1 syn_nclk ;
end
`else
wire [gw-1:0] ext_pad_snc ;
assign ext_pad_snc = ext_pad_i ;
`endif // GPIO_SYNC_IN_CLK
always @(posedge clk_n or posedge wb_rst_i)
if (wb_rst_i) begin
nextc_sampled <= #1 {gw{1'b0}};
end else begin
nextc_sampled <= #1 ext_pad_snc ;
end
assign extc_in = (~rgpio_nec & pextc_sampled) | (rgpio_nec & nextc_sampled) ;
`endif // GPIO_NO_CLKPAD_LOGIC
`else
`ifdef GPIO_SYNC_IN_CLK
reg [gw-1:0] syn_nclk ,
ext_pad_snc ;
always @(negedge clk_n or posedge wb_rst_i)
if (wb_rst_i) begin
syn_nclk <= #1 {gw{1'b0}} ;
ext_pad_snc <= #1 {gw{1'b0}} ;
end else begin
syn_nclk <= #1 ext_pad_i ;
ext_pad_snc <= #1 syn_nclk ;
end
`else
wire [gw-1:0] ext_pad_snc ;
assign ext_pad_snc = ext_pad_i ;
`endif // GPIO_SYNC_IN_CLK
always @(negedge clk_pad_i or posedge wb_rst_i)
if (wb_rst_i) begin
nextc_sampled <= #1 {gw{1'b0}};
end else begin
nextc_sampled <= #1 ext_pad_snc ;
end
assign extc_in = (~rgpio_nec & pextc_sampled) | (rgpio_nec & nextc_sampled) ;
`endif // GPIO_NO_NEGEDGE_FLOPS
assign in_muxed = (rgpio_eclk & extc_s) | (~rgpio_eclk & ext_pad_s) ;
`endif // GPIO_SYNC_CLK_WB
`else
assign in_muxed = ext_pad_s ;
`endif // GPIO_CLKPAD
//
// Mux all registers when doing a read of GPIO registers
//
always @(wb_adr_i or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or
rgpio_ptrig or rgpio_aux or rgpio_ctrl or rgpio_ints or rgpio_eclk or rgpio_nec)
case (wb_adr_i[`GPIO_OFS_BITS]) // synopsys full_case parallel_case
`ifdef GPIO_READREGS
`ifdef GPIO_RGPIO_OUT
`GPIO_RGPIO_OUT: begin
wb_dat[dw-1:0] = rgpio_out;
end
`endif
`ifdef GPIO_RGPIO_OE
`GPIO_RGPIO_OE: begin
wb_dat[dw-1:0] = rgpio_oe;
end
`endif
`ifdef GPIO_RGPIO_INTE
`GPIO_RGPIO_INTE: begin
wb_dat[dw-1:0] = rgpio_inte;
end
`endif
`ifdef GPIO_RGPIO_PTRIG
`GPIO_RGPIO_PTRIG: begin
wb_dat[dw-1:0] = rgpio_ptrig;
end
`endif
`ifdef GPIO_RGPIO_NEC
`GPIO_RGPIO_NEC: begin
wb_dat[dw-1:0] = rgpio_nec;
end
`endif
`ifdef GPIO_RGPIO_ECLK
`GPIO_RGPIO_ECLK: begin
wb_dat[dw-1:0] = rgpio_eclk;
end
`endif
`ifdef GPIO_RGPIO_AUX
`GPIO_RGPIO_AUX: begin
wb_dat[dw-1:0] = rgpio_aux;
end
`endif
`ifdef GPIO_RGPIO_CTRL
`GPIO_RGPIO_CTRL: begin
wb_dat[1:0] = rgpio_ctrl;
wb_dat[dw-1:2] = {dw-2{1'b0}};
end
`endif
`endif
`ifdef GPIO_RGPIO_INTS
`GPIO_RGPIO_INTS: begin
wb_dat[dw-1:0] = rgpio_ints;
end
`endif
default: begin
wb_dat[dw-1:0] = rgpio_in;
end
endcase
//
// WB data output
//
`ifdef GPIO_REGISTERED_WB_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
wb_dat_o <= #1 {dw{1'b0}};
else
wb_dat_o <= #1 wb_dat;
`else
assign wb_dat_o = wb_dat;
`endif
//
// RGPIO_INTS
//
`ifdef GPIO_RGPIO_INTS
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
rgpio_ints <= #1 {gw{1'b0}};
else if (rgpio_ints_sel && wb_we_i)
rgpio_ints <= #1 wb_dat_i[gw-1:0];
else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE])
rgpio_ints <= #1 (rgpio_ints | ((in_muxed ^ rgpio_in) & ~(in_muxed ^ rgpio_ptrig)) & rgpio_inte);
`else
assign rgpio_ints = (rgpio_ints | ((in_muxed ^ rgpio_in) & ~(in_muxed ^ rgpio_ptrig)) & rgpio_inte);
`endif
//
// Generate interrupt request
//
assign wb_inta = |rgpio_ints ? rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE] : 1'b0;
//
// Optional registration of WB interrupt
//
`ifdef GPIO_REGISTERED_WB_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
wb_inta_o <= #1 1'b0;
else
wb_inta_o <= #1 wb_inta;
`else
assign wb_inta_o = wb_inta;
`endif // GPIO_REGISTERED_WB_OUTPUTS
//
// Output enables are RGPIO_OE bits
//
assign ext_padoe_o = rgpio_oe;
//
// Generate GPIO outputs
//
`ifdef GPIO_AUX_IMPLEMENT
assign out_pad = rgpio_out & ~rgpio_aux | aux_i & rgpio_aux;
`else
assign out_pad = rgpio_out ;
`endif // GPIO_AUX_IMPLEMENT
//
// Optional registration of GPIO outputs
//
`ifdef GPIO_REGISTERED_IO_OUTPUTS
always @(posedge wb_clk_i or posedge wb_rst_i)
if (wb_rst_i)
ext_pad_o <= #1 {gw{1'b0}};
else
ext_pad_o <= #1 out_pad;
`else
assign ext_pad_o = out_pad;
`endif // GPIO_REGISTERED_IO_OUTPUTS
`else
//
// When GPIO is not implemented, drive all outputs as would when RGPIO_CTRL
// is cleared and WISHBONE transfers complete with errors
//
assign wb_inta_o = 1'b0;
assign wb_ack_o = 1'b0;
assign wb_err_o = wb_cyc_i & wb_stb_i;
assign ext_padoe_o = {gw{1'b1}};
assign ext_pad_o = {gw{1'b0}};
//
// Read GPIO registers
//
assign wb_dat_o = {dw{1'b0}};
`endif // GPIO_IMPLEMENTED
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:ovld_reg:1.0
// IP Revision: 2
(* X_CORE_INFO = "ovld_reg,Vivado 2015.4" *)
(* CHECK_LICENSE_TYPE = "zc702_get_0_val_r_0,ovld_reg,{}" *)
(* CORE_GENERATION_INFO = "zc702_get_0_val_r_0,ovld_reg,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=ovld_reg,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,DATA_WIDTH=32}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zc702_get_0_val_r_0 (
data_in,
vld_in,
ap_done,
clk,
data_out,
vld_out
);
input wire [31 : 0] data_in;
input wire vld_in;
(* X_INTERFACE_INFO = "xilinx.com:interface:acc_handshake:1.0 AP_CTRL done" *)
input wire ap_done;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
input wire clk;
output wire [31 : 0] data_out;
output wire vld_out;
ovld_reg #(
.DATA_WIDTH(32)
) inst (
.data_in(data_in),
.vld_in(vld_in),
.ap_done(ap_done),
.clk(clk),
.data_out(data_out),
.vld_out(vld_out)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRTP_4_V
`define SKY130_FD_SC_HD__DLRTP_4_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog wrapper for dlrtp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlrtp_4 (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlrtp_4 (
Q ,
RESET_B,
D ,
GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRTP_4_V
|
(** * Logic: Logic in Coq *)
Set Warnings "-notation-overridden,-parsing".
From LF Require Export Tactics.
(** We have seen many examples of factual claims (_propositions_)
and ways of presenting evidence of their truth (_proofs_). In
particular, we have worked extensively with _equality
propositions_ ([e1 = e2]), implications ([P -> Q]), and quantified
propositions ([forall x, P]). In this chapter, we will see how
Coq can be used to carry out other familiar forms of logical
reasoning.
Before diving into details, let's talk a bit about the status of
mathematical statements in Coq. Recall that Coq is a _typed_
language, which means that every sensible expression in its world
has an associated type. Logical claims are no exception: any
statement we might try to prove in Coq has a type, namely [Prop],
the type of _propositions_. We can see this with the [Check]
command: *)
Check 3 = 3 : Prop.
Check forall n m : nat, n + m = m + n : Prop.
(** Note that _all_ syntactically well-formed propositions have type
[Prop] in Coq, regardless of whether they are true. *)
(** Simply _being_ a proposition is one thing; being _provable_ is
something else! *)
Check 2 = 2 : Prop.
Check 3 = 2 : Prop.
Check forall n : nat, n = 2 : Prop.
(** Indeed, propositions not only have types: they are
_first-class_ entities that can be manipulated in all the same
ways as any of the other things in Coq's world. *)
(** So far, we've seen one primary place that propositions can appear:
in [Theorem] (and [Lemma] and [Example]) declarations. *)
Theorem plus_2_2_is_4 :
2 + 2 = 4.
Proof. reflexivity. Qed.
(** But propositions can be used in many other ways. For example, we
can give a name to a proposition using a [Definition], just as we
have given names to other kinds of expressions. *)
Definition plus_claim : Prop := 2 + 2 = 4.
Check plus_claim : Prop.
(** We can later use this name in any situation where a proposition is
expected -- for example, as the claim in a [Theorem] declaration. *)
Theorem plus_claim_is_true :
plus_claim.
Proof. reflexivity. Qed.
(** We can also write _parameterized_ propositions -- that is,
functions that take arguments of some type and return a
proposition. *)
(** For instance, the following function takes a number
and returns a proposition asserting that this number is equal to
three: *)
Definition is_three (n : nat) : Prop :=
n = 3.
Check is_three : nat -> Prop.
(** In Coq, functions that return propositions are said to define
_properties_ of their arguments. For instance, here's a
(polymorphic) property defining the familiar notion of an
_injective function_. *)
Definition injective {A B} (f : A -> B) :=
forall x y : A, f x = f y -> x = y.
Lemma succ_inj : injective S.
Proof.
intros n m H. injection H as H1. apply H1.
Qed.
(** The equality operator [=] is also a function that returns a
[Prop].
The expression [n = m] is syntactic sugar for [eq n m] (defined in
Coq's standard library using the [Notation] mechanism). Because
[eq] can be used with elements of any type, it is also
polymorphic: *)
Check @eq : forall A : Type, A -> A -> Prop.
(** (Notice that we wrote [@eq] instead of [eq]: The type
argument [A] to [eq] is declared as implicit, and we need to turn
off the inference of this implicit argument to see the full type
of [eq].) *)
(* ################################################################# *)
(** * Logical Connectives *)
(* ================================================================= *)
(** ** Conjunction *)
(** The _conjunction_, or _logical and_, of propositions [A] and [B]
is written [A /\ B], representing the claim that both [A] and [B]
are true. *)
Example and_example : 3 + 4 = 7 /\ 2 * 2 = 4.
(** To prove a conjunction, use the [split] tactic. It will generate
two subgoals, one for each part of the statement: *)
Proof.
split.
- (* 3 + 4 = 7 *) reflexivity.
- (* 2 * 2 = 4 *) reflexivity.
Qed.
(** For any propositions [A] and [B], if we assume that [A] is true
and that [B] is true, we can conclude that [A /\ B] is also
true. *)
Lemma and_intro : forall A B : Prop, A -> B -> A /\ B.
Proof.
intros A B HA HB. split.
- apply HA.
- apply HB.
Qed.
(** Since applying a theorem with hypotheses to some goal has the
effect of generating as many subgoals as there are hypotheses for
that theorem, we can apply [and_intro] to achieve the same effect
as [split]. *)
Example and_example' : 3 + 4 = 7 /\ 2 * 2 = 4.
Proof.
apply and_intro.
- (* 3 + 4 = 7 *) reflexivity.
- (* 2 + 2 = 4 *) reflexivity.
Qed.
(** **** Exercise: 2 stars, standard (and_exercise) *)
Example and_exercise :
forall n m : nat, n + m = 0 -> n = 0 /\ m = 0.
Proof.
intros.
split.
- destruct n. reflexivity. discriminate H.
- destruct m. reflexivity. rewrite <- plus_n_Sm in H. discriminate H.
Qed.
(** [] *)
(** So much for proving conjunctive statements. To go in the other
direction -- i.e., to _use_ a conjunctive hypothesis to help prove
something else -- we employ the [destruct] tactic.
If the proof context contains a hypothesis [H] of the form
[A /\ B], writing [destruct H as [HA HB]] will remove [H] from the
context and add two new hypotheses: [HA], stating that [A] is
true, and [HB], stating that [B] is true. *)
Lemma and_example2 :
forall n m : nat, n = 0 /\ m = 0 -> n + m = 0.
Proof.
(* WORKED IN CLASS *)
intros n m H.
destruct H as [Hn Hm].
rewrite Hn. rewrite Hm.
reflexivity.
Qed.
(** As usual, we can also destruct [H] right when we introduce it,
instead of introducing and then destructing it: *)
Lemma and_example2' :
forall n m : nat, n = 0 /\ m = 0 -> n + m = 0.
Proof.
intros n m [Hn Hm].
rewrite Hn. rewrite Hm.
reflexivity.
Qed.
(** You may wonder why we bothered packing the two hypotheses [n = 0]
and [m = 0] into a single conjunction, since we could have also
stated the theorem with two separate premises: *)
Lemma and_example2'' :
forall n m : nat, n = 0 -> m = 0 -> n + m = 0.
Proof.
intros n m Hn Hm.
rewrite Hn. rewrite Hm.
reflexivity.
Qed.
(** For this specific theorem, both formulations are fine. But
it's important to understand how to work with conjunctive
hypotheses because conjunctions often arise from intermediate
steps in proofs, especially in larger developments. Here's a
simple example: *)
Lemma and_example3 :
forall n m : nat, n + m = 0 -> n * m = 0.
Proof.
(* WORKED IN CLASS *)
intros n m H.
apply and_exercise in H.
destruct H as [Hn Hm].
rewrite Hn. reflexivity.
Qed.
(** Another common situation with conjunctions is that we know
[A /\ B] but in some context we need just [A] or just [B].
In such cases we can do a [destruct] (possibly as part of
an [intros]) and use an underscore pattern [_] to indicate
that the unneeded conjunct should just be thrown away. *)
Lemma proj1 : forall P Q : Prop,
P /\ Q -> P.
Proof.
intros P Q HPQ.
destruct HPQ as [HP _].
apply HP. Qed.
(** **** Exercise: 1 star, standard, optional (proj2) *)
Lemma proj2 : forall P Q : Prop,
P /\ Q -> Q.
Proof.
intros.
destruct H.
assumption.
Qed.
(** [] *)
(** Finally, we sometimes need to rearrange the order of conjunctions
and/or the grouping of multi-way conjunctions. The following
commutativity and associativity theorems are handy in such
cases. *)
Theorem and_commut : forall P Q : Prop,
P /\ Q -> Q /\ P.
Proof.
intros P Q [HP HQ].
split.
- (* left *) apply HQ.
- (* right *) apply HP. Qed.
(** **** Exercise: 2 stars, standard (and_assoc)
(In the following proof of associativity, notice how the _nested_
[intros] pattern breaks the hypothesis [H : P /\ (Q /\ R)] down into
[HP : P], [HQ : Q], and [HR : R]. Finish the proof from
there.) *)
Theorem and_assoc : forall P Q R : Prop,
P /\ (Q /\ R) -> (P /\ Q) /\ R.
Proof.
intros P Q R [HP [HQ HR]].
split; try split; assumption.
Qed.
(** [] *)
(** By the way, the infix notation [/\] is actually just syntactic
sugar for [and A B]. That is, [and] is a Coq operator that takes
two propositions as arguments and yields a proposition. *)
Check and : Prop -> Prop -> Prop.
(* ================================================================= *)
(** ** Disjunction *)
(** Another important connective is the _disjunction_, or _logical or_,
of two propositions: [A \/ B] is true when either [A] or [B]
is. (This infix notation stands for [or A B], where [or : Prop ->
Prop -> Prop].) *)
(** To use a disjunctive hypothesis in a proof, we proceed by case
analysis (which, as with other data types like [nat], can be done
explicitly with [destruct] or implicitly with an [intros]
pattern): *)
Lemma eq_mult_0 :
forall n m : nat, n = 0 \/ m = 0 -> n * m = 0.
Proof.
(* This pattern implicitly does case analysis on
[n = 0 \/ m = 0] *)
intros n m [Hn | Hm].
- (* Here, [n = 0] *)
rewrite Hn. reflexivity.
- (* Here, [m = 0] *)
rewrite Hm. rewrite <- mult_n_O.
reflexivity.
Qed.
(** Conversely, to show that a disjunction holds, it suffices to show
that one of its sides holds. This is done via two tactics, [left]
and [right]. As their names imply, the first one requires proving
the left side of the disjunction, while the second requires
proving its right side. Here is a trivial use... *)
Lemma or_intro_l : forall A B : Prop, A -> A \/ B.
Proof.
intros A B HA.
left.
apply HA.
Qed.
(** ... and here is a slightly more interesting example requiring both
[left] and [right]: *)
Lemma zero_or_succ :
forall n : nat, n = 0 \/ n = S (pred n).
Proof.
(* WORKED IN CLASS *)
intros [|n'].
- left. reflexivity.
- right. reflexivity.
Qed.
(** **** Exercise: 1 star, standard (mult_eq_0) *)
Lemma mult_eq_0 :
forall n m, n * m = 0 -> n = 0 \/ m = 0.
Proof.
intros [|n'] [|m'] H.
- simpl in H. left. assumption.
- simpl in H. left. assumption.
- rewrite mult_0_r in H. right. assumption.
- simpl in H. discriminate H.
Qed.
(** [] *)
(** **** Exercise: 1 star, standard (or_commut) *)
Theorem or_commut : forall P Q : Prop,
P \/ Q -> Q \/ P.
Proof.
intros.
destruct H.
- right. assumption.
- left. assumption.
Qed.
(** [] *)
(* ================================================================= *)
(** ** Falsehood and Negation
So far, we have mostly been concerned with proving that certain
things are _true_ -- addition is commutative, appending lists is
associative, etc. Of course, we may also be interested in
negative results, demonstrating that some given proposition is
_not_ true. Such statements are expressed with the logical
negation operator [~]. *)
(** To see how negation works, recall the _principle of explosion_
from the [Tactics] chapter, which asserts that, if we assume a
contradiction, then any other proposition can be derived.
Following this intuition, we could define [~ P] ("not [P]") as
[forall Q, P -> Q].
Coq actually makes a slightly different (but equivalent) choice,
defining [~ P] as [P -> False], where [False] is a specific
contradictory proposition defined in the standard library. *)
Module MyNot.
Definition not (P:Prop) := P -> False.
Notation "~ x" := (not x) : type_scope.
Check not : Prop -> Prop.
End MyNot.
(** Since [False] is a contradictory proposition, the principle of
explosion also applies to it. If we get [False] into the proof
context, we can use [destruct] on it to complete any goal: *)
Theorem ex_falso_quodlibet : forall (P:Prop),
False -> P.
Proof.
(* WORKED IN CLASS *)
intros P contra.
destruct contra. Qed.
(** The Latin _ex falso quodlibet_ means, literally, "from falsehood
follows whatever you like"; this is another common name for the
principle of explosion. *)
(** **** Exercise: 2 stars, standard, optional (not_implies_our_not)
Show that Coq's definition of negation implies the intuitive one
mentioned above: *)
Fact not_implies_our_not : forall (P:Prop),
~ P -> (forall (Q:Prop), P -> Q).
Proof.
intros.
apply H in H0. destruct H0.
Qed.
(** [] *)
(** Inequality is a frequent enough example of negated statement
that there is a special notation for it, [x <> y]:
Notation "x <> y" := (~(x = y)).
*)
(** We can use [not] to state that [0] and [1] are different elements
of [nat]: *)
Theorem zero_not_one : 0 <> 1.
Proof.
(** The proposition [0 <> 1] is exactly the same as
[~(0 = 1)], that is [not (0 = 1)], which unfolds to
[(0 = 1) -> False]. (We use [unfold not] explicitly here
to illustrate that point, but generally it can be omitted.) *)
unfold not.
(** To prove an inequality, we may assume the opposite
equality... *)
intros contra.
(** ... and deduce a contradiction from it. Here, the
equality [O = S O] contradicts the disjointness of
constructors [O] and [S], so [discriminate] takes care
of it. *)
discriminate contra.
Qed.
(** It takes a little practice to get used to working with negation in
Coq. Even though you can see perfectly well why a statement
involving negation is true, it can be a little tricky at first to
make Coq understand it! Here are proofs of a few familiar facts
to get you warmed up. *)
Theorem not_False :
~ False.
Proof.
unfold not. intros H. destruct H. Qed.
Theorem contradiction_implies_anything : forall P Q : Prop,
(P /\ ~P) -> Q.
Proof.
(* WORKED IN CLASS *)
intros P Q [HP HNA]. unfold not in HNA.
apply HNA in HP. destruct HP. Qed.
Theorem double_neg : forall P : Prop,
P -> ~~P.
Proof.
(* WORKED IN CLASS *)
intros P H. unfold not. intros G. apply G. apply H. Qed.
(** **** Exercise: 2 stars, advanced (double_neg_inf)
Write an informal proof of [double_neg]:
_Theorem_: [P] implies [~~P], for any proposition [P].
*)
(*
Suppose P holds, we prove (P -> False) -> False holds.
We assume (H: P -> False) holds and prove False holds.
Given H holds and P holds, by conditional elimination law, False holds. Qed.
*)
(* Do not modify the following line: *)
Definition manual_grade_for_double_neg_inf : option (nat*string) := None.
(** [] *)
(** **** Exercise: 2 stars, standard, especially useful (contrapositive) *)
Theorem contrapositive : forall (P Q : Prop),
(P -> Q) -> (~Q -> ~P).
Proof.
intros P Q. unfold not. intros.
apply H0. apply H. apply H1.
Qed.
(** [] *)
(** **** Exercise: 1 star, standard (not_both_true_and_false) *)
Theorem not_both_true_and_false : forall P : Prop,
~ (P /\ ~P).
Proof.
intros. unfold not. intros.
destruct H. apply H0. apply H.
Qed.
(** [] *)
(** **** Exercise: 1 star, advanced (informal_not_PNP)
Write an informal proof (in English) of the proposition [forall P
: Prop, ~(P /\ ~P)].
*)
(*
We need to prove (P /\ (P -> False)) -> False holds.
Assume (P /\ (P -> False)), we need to prove False holds.
Assume P and (H: P -> False), we need to prove False holds.
Based on P and H, False holds.
*)
(* Do not modify the following line: *)
Definition manual_grade_for_informal_not_PNP : option (nat*string) := None.
(** [] *)
(** Since inequality involves a negation, it also requires a little
practice to be able to work with it fluently. Here is one useful
trick. If you are trying to prove a goal that is
nonsensical (e.g., the goal state is [false = true]), apply
[ex_falso_quodlibet] to change the goal to [False]. This makes it
easier to use assumptions of the form [~P] that may be available
in the context -- in particular, assumptions of the form
[x<>y]. *)
Theorem not_true_is_false : forall b : bool,
b <> true -> b = false.
Proof.
intros b H.
destruct b eqn:HE.
- (* b = true *)
unfold not in H.
apply ex_falso_quodlibet.
apply H. reflexivity.
- (* b = false *)
reflexivity.
Qed.
(** Since reasoning with [ex_falso_quodlibet] is quite common, Coq
provides a built-in tactic, [exfalso], for applying it. *)
Theorem not_true_is_false' : forall b : bool,
b <> true -> b = false.
Proof.
intros [] H. (* note implicit [destruct b] here *)
- (* b = true *)
unfold not in H.
exfalso. (* <=== *)
apply H. reflexivity.
- (* b = false *) reflexivity.
Qed.
(* ================================================================= *)
(** ** Truth *)
(** Besides [False], Coq's standard library also defines [True], a
proposition that is trivially true. To prove it, we use the
predefined constant [I : True]: *)
Lemma True_is_true : True.
Proof. apply I. Qed.
(** Unlike [False], which is used extensively, [True] is used quite
rarely, since it is trivial (and therefore uninteresting) to prove
as a goal, and it carries no useful information as a hypothesis.
But it can be quite useful when defining complex [Prop]s using
conditionals or as a parameter to higher-order [Prop]s. We will
see examples later on. *)
(* ================================================================= *)
(** ** Logical Equivalence *)
(** The handy "if and only if" connective, which asserts that two
propositions have the same truth value, is simply the conjunction
of two implications. *)
Module MyIff.
Definition iff (P Q : Prop) := (P -> Q) /\ (Q -> P).
Notation "P <-> Q" := (iff P Q)
(at level 95, no associativity)
: type_scope.
End MyIff.
Theorem iff_sym : forall P Q : Prop,
(P <-> Q) -> (Q <-> P).
Proof.
(* WORKED IN CLASS *)
intros P Q [HAB HBA].
split.
- (* -> *) apply HBA.
- (* <- *) apply HAB. Qed.
Lemma not_true_iff_false : forall b,
b <> true <-> b = false.
Proof.
(* WORKED IN CLASS *)
intros b. split.
- (* -> *) apply not_true_is_false.
- (* <- *)
intros H. rewrite H. intros H'. discriminate H'.
Qed.
(** **** Exercise: 1 star, standard, optional (iff_properties)
Using the above proof that [<->] is symmetric ([iff_sym]) as
a guide, prove that it is also reflexive and transitive. *)
Theorem iff_refl : forall P : Prop,
P <-> P.
Proof.
intros; split; intro; assumption.
Qed.
Theorem iff_trans : forall P Q R : Prop,
(P <-> Q) -> (Q <-> R) -> (P <-> R).
Proof.
intros. destruct H. destruct H0. split; intro.
- auto.
- auto.
Qed.
(** [] *)
(** **** Exercise: 3 stars, standard (or_distributes_over_and) *)
Theorem or_distributes_over_and : forall P Q R : Prop,
P \/ (Q /\ R) <-> (P \/ Q) /\ (P \/ R).
Proof.
intros.
split.
- intro. destruct H.
+ split. left. assumption. left. assumption.
+ destruct H. split. right. assumption. right. assumption.
- intro. destruct H. destruct H; destruct H0.
+ left. assumption.
+ left. assumption.
+ left. assumption.
+ right. split; assumption.
Qed.
(** [] *)
(* ================================================================= *)
(** ** Setoids and Logical Equivalence *)
(** Some of Coq's tactics treat [iff] statements specially, avoiding
the need for some low-level proof-state manipulation. In
particular, [rewrite] and [reflexivity] can be used with [iff]
statements, not just equalities. To enable this behavior, we have
to import the Coq library that supports it: *)
From Coq Require Import Setoids.Setoid.
(** A "setoid" is a set equipped with an equivalence relation,
that is, a relation that is reflexive, symmetric, and transitive.
When two elements of a set are equivalent according to the
relation, [rewrite] can be used to replace one element with the
other. We've seen that already with the equality relation [=] in
Coq: when [x = y], we can use [rewrite] to replace [x] with [y],
or vice-versa.
Similarly, the logical equivalence relation [<->] is reflexive,
symmetric, and transitive, so we can use it to replace one part of
a proposition with another: if [P <-> Q], then we can use
[rewrite] to replace [P] with [Q], or vice-versa. *)
(** Here is a simple example demonstrating how these tactics work with
[iff]. First, let's prove a couple of basic iff equivalences. *)
Lemma mult_0 : forall n m, n * m = 0 <-> n = 0 \/ m = 0.
Proof.
split.
- apply mult_eq_0.
- apply eq_mult_0.
Qed.
Theorem or_assoc :
forall P Q R : Prop, P \/ (Q \/ R) <-> (P \/ Q) \/ R.
Proof.
intros P Q R. split.
- intros [H | [H | H]].
+ left. left. apply H.
+ left. right. apply H.
+ right. apply H.
- intros [[H | H] | H].
+ left. apply H.
+ right. left. apply H.
+ right. right. apply H.
Qed.
(** We can now use these facts with [rewrite] and [reflexivity]
to give smooth proofs of statements involving equivalences. For
example, here is a ternary version of the previous [mult_0]
result: *)
Lemma mult_0_3 :
forall n m p, n * m * p = 0 <-> n = 0 \/ m = 0 \/ p = 0.
Proof.
intros n m p.
rewrite mult_0. rewrite mult_0. rewrite or_assoc.
reflexivity.
Qed.
(** The [apply] tactic can also be used with [<->]. When given an
equivalence as its argument, [apply] tries to guess which direction of
the equivalence will be useful. *)
Lemma apply_iff_example :
forall n m : nat, n * m = 0 -> n = 0 \/ m = 0.
Proof.
intros n m H. apply mult_0. apply H.
Qed.
(* ================================================================= *)
(** ** Existential Quantification *)
(** Another important logical connective is _existential
quantification_. To say that there is some [x] of type [T] such
that some property [P] holds of [x], we write [exists x : T,
P]. As with [forall], the type annotation [: T] can be omitted if
Coq is able to infer from the context what the type of [x] should
be. *)
(** To prove a statement of the form [exists x, P], we must show that
[P] holds for some specific choice of value for [x], known as the
_witness_ of the existential. This is done in two steps: First,
we explicitly tell Coq which witness [t] we have in mind by
invoking the tactic [exists t]. Then we prove that [P] holds after
all occurrences of [x] are replaced by [t]. *)
Definition even x := exists n : nat, x = double n.
Lemma four_is_even : even 4.
Proof.
unfold even. exists 2. reflexivity.
Qed.
(** Conversely, if we have an existential hypothesis [exists x, P] in
the context, we can destruct it to obtain a witness [x] and a
hypothesis stating that [P] holds of [x]. *)
Theorem exists_example_2 : forall n,
(exists m, n = 4 + m) ->
(exists o, n = 2 + o).
Proof.
(* WORKED IN CLASS *)
intros n [m Hm]. (* note implicit [destruct] here *)
exists (2 + m).
apply Hm. Qed.
(** **** Exercise: 1 star, standard, especially useful (dist_not_exists)
Prove that "[P] holds for all [x]" implies "there is no [x] for
which [P] does not hold." (Hint: [destruct H as [x E]] works on
existential assumptions!) *)
Theorem dist_not_exists : forall (X:Type) (P : X -> Prop),
(forall x, P x) -> ~ (exists x, ~ P x).
Proof.
intros. unfold not.
intro. destruct H0.
apply H0. apply H.
Qed.
(** [] *)
(** **** Exercise: 2 stars, standard (dist_exists_or)
Prove that existential quantification distributes over
disjunction. *)
Theorem dist_exists_or : forall (X:Type) (P Q : X -> Prop),
(exists x, P x \/ Q x) <-> (exists x, P x) \/ (exists x, Q x).
Proof.
intros.
split.
- intros [H]. destruct H0.
+ left. exists H. apply H0.
+ right. exists H. apply H0.
- intros. destruct H; destruct H.
+ exists x. left. apply H.
+ exists x. right. apply H.
Qed.
(** [] *)
(* ################################################################# *)
(** * Programming with Propositions *)
(** The logical connectives that we have seen provide a rich
vocabulary for defining complex propositions from simpler ones.
To illustrate, let's look at how to express the claim that an
element [x] occurs in a list [l]. Notice that this property has a
simple recursive structure:
- If [l] is the empty list, then [x] cannot occur in it, so the
property "[x] appears in [l]" is simply false.
- Otherwise, [l] has the form [x' :: l']. In this case, [x]
occurs in [l] if either it is equal to [x'] or it occurs in
[l']. *)
(** We can translate this directly into a straightforward recursive
function taking an element and a list and returning a proposition (!): *)
Fixpoint In {A : Type} (x : A) (l : list A) : Prop :=
match l with
| [] => False
| x' :: l' => x' = x \/ In x l'
end.
(** When [In] is applied to a concrete list, it expands into a
concrete sequence of nested disjunctions. *)
Example In_example_1 : In 4 [1; 2; 3; 4; 5].
Proof.
(* WORKED IN CLASS *)
simpl. right. right. right. left. reflexivity.
Qed.
Example In_example_2 :
forall n, In n [2; 4] ->
exists n', n = 2 * n'.
Proof.
(* WORKED IN CLASS *)
simpl.
intros n.
intros [H | [H | []]].
- exists 1. rewrite <- H. reflexivity.
- exists 2. rewrite <- H. reflexivity.
Qed.
(** (Notice the use of the empty pattern to discharge the last case
_en passant_.) *)
(** We can also prove more generic, higher-level lemmas about [In].
Note, in the first, how [In] starts out applied to a variable and
only gets expanded when we do case analysis on this variable: *)
Theorem In_map :
forall (A B : Type) (f : A -> B) (l : list A) (x : A),
In x l ->
In (f x) (map f l).
Proof.
intros A B f l x.
induction l as [|x' l' IHl'].
- (* l = nil, contradiction *)
simpl. intros [].
- (* l = x' :: l' *)
simpl. intros [H | H].
+ rewrite H. left. reflexivity.
+ right. apply IHl'. apply H.
Qed.
(** This way of defining propositions recursively, though convenient
in some cases, also has some drawbacks. In particular, it is
subject to Coq's usual restrictions regarding the definition of
recursive functions, e.g., the requirement that they be "obviously
terminating." In the next chapter, we will see how to define
propositions _inductively_, a different technique with its own set
of strengths and limitations. *)
(** **** Exercise: 3 stars, standard (In_map_iff) *)
Theorem In_map_iff :
forall (A B : Type) (f : A -> B) (l : list A) (y : B),
In y (map f l) <->
exists x, f x = y /\ In x l.
Proof.
intros A B f l y. split.
- induction l. simpl.
+ intro. exfalso. apply H.
+ simpl. intro. destruct H.
* exists x. split. apply H. left. reflexivity.
* apply IHl in H. destruct H. exists x0. destruct H. split.
-- apply H.
-- right. apply H0.
- intros [x]. induction l.
+ destruct H. apply H0.
+ simpl in H. simpl. destruct H. destruct H0.
* left. rewrite H0. apply H.
* right. apply IHl. split.
-- apply H.
-- apply H0.
Qed.
(** [] *)
(** **** Exercise: 2 stars, standard (In_app_iff) *)
Theorem In_app_iff : forall A l l' (a:A),
In a (l++l') <-> In a l \/ In a l'.
Proof.
intros A l. induction l as [|a' l' IH].
- split.
+ simpl. intro. right. apply H.
+ simpl. intro. destruct H. exfalso. apply H. apply H.
- split; intros.
+ simpl in H. simpl. destruct H.
* left. left. apply H.
* apply IH in H. destruct H. left. right. apply H. right. apply H.
+ simpl. simpl in H. destruct H. destruct H.
* left. apply H.
* right. apply IH. left. apply H.
* right. apply IH. right. apply H.
Qed.
(** [] *)
(** **** Exercise: 3 stars, standard, especially useful (All)
Recall that functions returning propositions can be seen as
_properties_ of their arguments. For instance, if [P] has type
[nat -> Prop], then [P n] states that property [P] holds of [n].
Drawing inspiration from [In], write a recursive function [All]
stating that some property [P] holds of all elements of a list
[l]. To make sure your definition is correct, prove the [All_In]
lemma below. (Of course, your definition should _not_ just
restate the left-hand side of [All_In].) *)
Fixpoint All {T : Type} (P : T -> Prop) (l : list T) : Prop :=
match l with
| [] => True
| (x :: l') => P x /\ All P l'
end.
Theorem All_In :
forall T (P : T -> Prop) (l : list T),
(forall x, In x l -> P x) <->
All P l.
Proof.
intros.
induction l as [|x l' IHl]; split.
- (* l := []; -> direction *)
intro. simpl. apply I.
- (* l := []; <- direction *)
intros. simpl in H0. exfalso. apply H0.
- (* l := x :: l'; -> direction *)
simpl. intros. split.
+ (* P x *)
apply H. left. reflexivity.
+ (* All P l' *)
apply IHl. intros. apply H. right. apply H0.
- (* l := x :: l'; <- direction *)
simpl. intros. destruct H. destruct H0.
+ (* when x = x0 *)
rewrite <- H0. apply H.
+ (* when In x0 l' *)
apply IHl in H0. apply H0. apply H1.
Qed.
(** [] *)
(** **** Exercise: 2 stars, standard, optional (combine_odd_even)
Complete the definition of the [combine_odd_even] function below.
It takes as arguments two properties of numbers, [Podd] and
[Peven], and it should return a property [P] such that [P n] is
equivalent to [Podd n] when [n] is odd and equivalent to [Peven n]
otherwise. *)
Definition combine_odd_even (Podd Peven : nat -> Prop) : nat -> Prop :=
fun n => match oddb n with
| true => Podd n
| false => Peven n
end.
(** To test your definition, prove the following facts: *)
Theorem combine_odd_even_intro :
forall (Podd Peven : nat -> Prop) (n : nat),
(oddb n = true -> Podd n) ->
(oddb n = false -> Peven n) ->
combine_odd_even Podd Peven n.
Proof.
intros * H1 H2. unfold combine_odd_even.
destruct (oddb n).
- (* oddb n = true *)
apply H1. reflexivity.
- (* oddb n = false *)
apply H2. reflexivity.
Qed.
Theorem combine_odd_even_elim_odd :
forall (Podd Peven : nat -> Prop) (n : nat),
combine_odd_even Podd Peven n ->
oddb n = true ->
Podd n.
Proof.
intros.
unfold combine_odd_even in H. rewrite H0 in H. apply H.
Qed.
Theorem combine_odd_even_elim_even :
forall (Podd Peven : nat -> Prop) (n : nat),
combine_odd_even Podd Peven n ->
oddb n = false ->
Peven n.
Proof.
intros.
unfold combine_odd_even in H. rewrite H0 in H. apply H.
Qed.
(** [] *)
(* ################################################################# *)
(** * Applying Theorems to Arguments *)
(** One feature that distinguishes Coq from some other popular
proof assistants (e.g., ACL2 and Isabelle) is that it treats
_proofs_ as first-class objects.
There is a great deal to be said about this, but it is not
necessary to understand it all in detail in order to use Coq.
This section gives just a taste, while a deeper exploration can be
found in the optional chapters [ProofObjects] and
[IndPrinciples]. *)
(** We have seen that we can use [Check] to ask Coq to print the type
of an expression. We can also use it to ask what theorem a
particular identifier refers to. *)
Check plus_comm : forall n m : nat, n + m = m + n.
(** Coq checks the _statement_ of the [plus_comm] theorem (or prints
it for us, if we leave off the part beginning with the colon) in
the same way that it checks the _type_ of any term that we ask it
to [Check]. Why? *)
(** The reason is that the identifier [plus_comm] actually refers to a
_proof object_, which represents a logical derivation establishing
of the truth of the statement [forall n m : nat, n + m = m + n]. The
type of this object is the proposition which it is a proof of. *)
(** Intuitively, this makes sense because the statement of a
theorem tells us what we can use that theorem for, just as the
type of a "computational" object tells us what we can do with that
object -- e.g., if we have a term of type [nat -> nat -> nat], we
can give it two [nat]s as arguments and get a [nat] back.
Similarly, if we have an object of type [n = m -> n + n = m + m]
and we provide it an "argument" of type [n = m], we can derive
[n + n = m + m]. *)
(** Operationally, this analogy goes even further: by applying a
theorem as if it were a function, i.e., applying it to hypotheses
with matching types, we can specialize its result without having
to resort to intermediate assertions. For example, suppose we
wanted to prove the following result: *)
Lemma plus_comm3 :
forall x y z, x + (y + z) = (z + y) + x.
(** It appears at first sight that we ought to be able to prove this
by rewriting with [plus_comm] twice to make the two sides match.
The problem, however, is that the second [rewrite] will undo the
effect of the first. *)
Proof.
(* WORKED IN CLASS *)
intros x y z.
rewrite plus_comm.
rewrite plus_comm.
(* We are back where we started... *)
Abort.
(** We saw similar problems back in Chapter [Induction], and saw one
way to work around them by using [assert] to derive a specialized
version of [plus_comm] that can be used to rewrite exactly where
we want. *)
Lemma plus_comm3_take2 :
forall x y z, x + (y + z) = (z + y) + x.
Proof.
intros x y z.
rewrite plus_comm.
assert (H : y + z = z + y).
{ rewrite plus_comm. reflexivity. }
rewrite H.
reflexivity.
Qed.
(** A more elegant alternative is to apply [plus_comm] directly
to the arguments we want to instantiate it with, in much the same
way as we apply a polymorphic function to a type argument. *)
Lemma plus_comm3_take3 :
forall x y z, x + (y + z) = (z + y) + x.
Proof.
intros x y z.
rewrite plus_comm.
rewrite (plus_comm y z).
reflexivity.
Qed.
(** Let's see another example of using a theorem like a
function. The following theorem says: any list [l]
containing some element must be nonempty. *)
Theorem in_not_nil :
forall A (x : A) (l : list A), In x l -> l <> [].
Proof.
intros A x l H. unfold not. intro Hl.
rewrite Hl in H.
simpl in H.
apply H.
Qed.
(** What makes this interesting is that one quantified variable
([x]) does not appear in the conclusion ([l <> []]). *)
(** We should be able to use this theorem to prove the special case
where [x] is [42]. However, naively, the tactic [apply in_not_nil]
will fail because it cannot infer the value of [x]. *)
Lemma in_not_nil_42 :
forall l : list nat, In 42 l -> l <> [].
Proof.
intros l H.
Fail apply in_not_nil.
Abort.
(** There are several ways to work around this: *)
(** Use [apply ... with ...] *)
Lemma in_not_nil_42_take2 :
forall l : list nat, In 42 l -> l <> [].
Proof.
intros l H.
apply in_not_nil with (x := 42).
apply H.
Qed.
(** Use [apply ... in ...] *)
Lemma in_not_nil_42_take3 :
forall l : list nat, In 42 l -> l <> [].
Proof.
intros l H.
apply in_not_nil in H.
apply H.
Qed.
(** Explicitly apply the lemma to the value for [x]. *)
Lemma in_not_nil_42_take4 :
forall l : list nat, In 42 l -> l <> [].
Proof.
intros l H.
apply (in_not_nil nat 42).
apply H.
Qed.
(** Explicitly apply the lemma to a hypothesis. *)
Lemma in_not_nil_42_take5 :
forall l : list nat, In 42 l -> l <> [].
Proof.
intros l H.
apply (in_not_nil _ _ _ H).
Qed.
(** You can "use theorems as functions" in this way with almost all
tactics that take a theorem name as an argument. Note also that
theorem application uses the same inference mechanisms as function
application; thus, it is possible, for example, to supply
wildcards as arguments to be inferred, or to declare some
hypotheses to a theorem as implicit by default. These features
are illustrated in the proof below. (The details of how this proof
works are not critical -- the goal here is just to illustrate what
can be done.) *)
Example lemma_application_ex :
forall {n : nat} {ns : list nat},
In n (map (fun m => m * 0) ns) ->
n = 0.
Proof.
intros n ns H.
destruct (proj1 _ _ (In_map_iff _ _ _ _ _) H)
as [m [Hm _]].
rewrite mult_0_r in Hm. rewrite <- Hm. reflexivity.
Qed.
(** We will see many more examples in later chapters. *)
(* ################################################################# *)
(** * Coq vs. Set Theory *)
(** Coq's logical core, the _Calculus of Inductive
Constructions_, differs in some important ways from other formal
systems that are used by mathematicians to write down precise and
rigorous definitions and proofs. For example, in the most popular
foundation for paper-and-pencil mathematics, Zermelo-Fraenkel Set
Theory (ZFC), a mathematical object can potentially be a member of
many different sets; a term in Coq's logic, on the other hand, is
a member of at most one type. This difference often leads to
slightly different ways of capturing informal mathematical
concepts, but these are, by and large, about equally natural and
easy to work with. For example, instead of saying that a natural
number [n] belongs to the set of even numbers, we would say in Coq
that [even n] holds, where [even : nat -> Prop] is a property
describing even numbers.
However, there are some cases where translating standard
mathematical reasoning into Coq can be cumbersome or sometimes
even impossible, unless we enrich the core logic with additional
axioms.
We conclude this chapter with a brief discussion of some of the
most significant differences between the two worlds. *)
(* ================================================================= *)
(** ** Functional Extensionality *)
(** The equality assertions that we have seen so far mostly have
concerned elements of inductive types ([nat], [bool], etc.). But,
since Coq's equality operator is polymorphic, we can use it at
_any_ type -- in particular, we can write propositions claiming
that two _functions_ are equal to each other: *)
Example function_equality_ex1 :
(fun x => 3 + x) = (fun x => (pred 4) + x).
Proof. reflexivity. Qed.
(** In common mathematical practice, two functions [f] and [g] are
considered equal if they produce the same output on every input:
(forall x, f x = g x) -> f = g
This is known as the principle of _functional extensionality_. *)
(** Informally, an "extensional property" is one that pertains to an
object's observable behavior. Thus, functional extensionality
simply means that a function's identity is completely determined
by what we can observe from it -- i.e., the results we obtain
after applying it. *)
(** However, functional extensionality is not part of Coq's built-in
logic. This means that some apparently "obvious" propositions are
not provable. *)
Example function_equality_ex2 :
(fun x => plus x 1) = (fun x => plus 1 x).
Proof.
(* Stuck *)
Abort.
(** However, we can add functional extensionality to Coq's core using
the [Axiom] command. *)
Axiom functional_extensionality : forall {X Y: Type}
{f g : X -> Y},
(forall (x:X), f x = g x) -> f = g.
(** Defining something as an [Axiom] has the same effect as stating a
theorem and skipping its proof using [Admitted], but it alerts the
reader that this isn't just something we're going to come back and
fill in later! *)
(** We can now invoke functional extensionality in proofs: *)
Example function_equality_ex2 :
(fun x => plus x 1) = (fun x => plus 1 x).
Proof.
apply functional_extensionality. intros x.
apply plus_comm.
Qed.
(** Naturally, we must be careful when adding new axioms into Coq's
logic, as this can render it _inconsistent_ -- that is, it may
become possible to prove every proposition, including [False],
[2+2=5], etc.!
Unfortunately, there is no simple way of telling whether an axiom
is safe to add: hard work by highly trained mathematicians is
often required to establish the consistency of any particular
combination of axioms.
Fortunately, it is known that adding functional extensionality, in
particular, _is_ consistent. *)
(** To check whether a particular proof relies on any additional
axioms, use the [Print Assumptions] command. *)
Print Assumptions function_equality_ex2.
(* ===>
Axioms:
functional_extensionality :
forall (X Y : Type) (f g : X -> Y),
(forall x : X, f x = g x) -> f = g *)
(** **** Exercise: 4 stars, standard (tr_rev_correct)
One problem with the definition of the list-reversing function
[rev] that we have is that it performs a call to [app] on each
step; running [app] takes time asymptotically linear in the size
of the list, which means that [rev] is asymptotically quadratic.
We can improve this with the following definitions: *)
Fixpoint rev_append {X} (l1 l2 : list X) : list X :=
match l1 with
| [] => l2
| x :: l1' => rev_append l1' (x :: l2)
end.
Definition tr_rev {X} (l : list X) : list X :=
rev_append l [].
(** This version of [rev] is said to be _tail-recursive_, because the
recursive call to the function is the last operation that needs to
be performed (i.e., we don't have to execute [++] after the
recursive call); a decent compiler will generate very efficient
code in this case.
Prove that the two definitions are indeed equivalent. *)
Lemma rev_append_appends :
forall X (l xs: list X) (x : X), rev_append l (x::xs) = rev_append l [x] ++ xs.
Proof.
intros X l.
induction l.
- simpl. intros. reflexivity.
- simpl. intros. rewrite (IHl [x0]). rewrite IHl. rewrite <- app_assoc.
simpl. reflexivity.
Qed.
Lemma rev_append_recur :
forall X (l: list X) (x : X), rev_append l [x] = rev_append l [] ++ [x].
Proof.
intros X l.
induction l.
- simpl. reflexivity.
- simpl. intro. apply rev_append_appends.
Qed.
Theorem tr_rev_correct : forall X, @tr_rev X = @rev X.
Proof.
intro.
apply functional_extensionality.
intros l. induction l as [|x l' IHl].
- (* l = [] *)
intros. reflexivity.
- (* l = x :: l' *)
simpl. unfold tr_rev. simpl. rewrite <- IHl.
unfold tr_rev. apply rev_append_recur.
Qed.
(** [] *)
(* ================================================================= *)
(** ** Propositions vs. Booleans *)
(** We've seen two different ways of expressing logical claims in Coq:
with _booleans_ (of type [bool]), and with _propositions_ (of type
[Prop]).
For instance, to claim that a number [n] is even, we can say
either... *)
(** ... that [evenb n] evaluates to [true]... *)
Example even_42_bool : evenb 42 = true.
Proof. reflexivity. Qed.
(** ... or that there exists some [k] such that [n = double k]. *)
Example even_42_prop : even 42.
Proof. unfold even. exists 21. reflexivity. Qed.
(** Of course, it would be pretty strange if these two
characterizations of evenness did not describe the same set of
natural numbers! Fortunately, we can prove that they do... *)
(** We first need two helper lemmas. *)
Lemma evenb_double : forall k, evenb (double k) = true.
Proof.
intros k. induction k as [|k' IHk'].
- reflexivity.
- simpl. apply IHk'.
Qed.
(** **** Exercise: 3 stars, standard (evenb_double_conv) *)
Lemma negb_true : forall b, (negb b) = true -> b = false.
Proof.
intros []; simpl; intro.
- discriminate H.
- reflexivity.
Qed.
Lemma evenb_double_conv : forall n, exists k,
n = if evenb n then double k else S (double k).
Proof.
intros.
induction n as [|n' IHn].
- (* n = 0 *) exists 0. reflexivity.
- destruct (evenb n') eqn:Heven; destruct IHn as [k0 IHn].
+ (* n = S n', evenb n' = true *)
assert (Hodd: evenb (S n') = false).
{ rewrite evenb_S. rewrite Heven. reflexivity. }
rewrite Hodd. exists k0. rewrite IHn. reflexivity.
+ (* n = S n', evenb n' = false *)
assert (Hodd: evenb (S n') = true).
{ rewrite evenb_S. rewrite Heven. reflexivity. }
rewrite Hodd. rewrite IHn. exists (S k0). simpl. reflexivity.
Qed.
(** [] *)
(** Now the main theorem: *)
Theorem even_bool_prop : forall n,
evenb n = true <-> even n.
Proof.
intros n. split.
- intros H. destruct (evenb_double_conv n) as [k Hk].
rewrite Hk. rewrite H. exists k. reflexivity.
- intros [k Hk]. rewrite Hk. apply evenb_double.
Qed.
(** In view of this theorem, we say that the boolean computation
[evenb n] is _reflected_ in the truth of the proposition
[exists k, n = double k]. *)
(** Similarly, to state that two numbers [n] and [m] are equal, we can
say either
- (1) that [n =? m] returns [true], or
- (2) that [n = m].
Again, these two notions are equivalent. *)
Theorem eqb_eq : forall n1 n2 : nat,
n1 =? n2 = true <-> n1 = n2.
Proof.
intros n1 n2. split.
- apply eqb_true.
- intros H. rewrite H. rewrite <- eqb_refl. reflexivity.
Qed.
(** However, even when the boolean and propositional formulations of a
claim are equivalent from a purely logical perspective, they are
often not equivalent from the point of view of convenience for
some specific purpose. *)
(** In the case of even numbers above, when proving the
backwards direction of [even_bool_prop] (i.e., [evenb_double],
going from the propositional to the boolean claim), we used a
simple induction on [k]. On the other hand, the converse (the
[evenb_double_conv] exercise) required a clever generalization,
since we can't directly prove [(evenb n = true) -> even n]. *)
(** For these examples, the propositional claims are more useful than
their boolean counterparts, but this is not always the case. For
instance, we cannot test whether a general proposition is true or
not in a function definition; as a consequence, the following code
fragment is rejected: *)
Fail
Definition is_even_prime n :=
if n = 2 then true
else false.
(** Coq complains that [n = 2] has type [Prop], while it expects
an element of [bool] (or some other inductive type with two
elements). The reason has to do with the _computational_ nature
of Coq's core language, which is designed so that every function
it can express is computable and total. One reason for this is to
allow the extraction of executable programs from Coq developments.
As a consequence, [Prop] in Coq does _not_ have a universal case
analysis operation telling whether any given proposition is true
or false, since such an operation would allow us to write
non-computable functions.
Beyond the fact that non-computable properties are impossible in
general to phrase as boolean computations, even many _computable_
properties are easier to express using [Prop] than [bool], since
recursive function definitions in Coq are subject to significant
restrictions. For instance, the next chapter shows how to define
the property that a regular expression matches a given string
using [Prop]. Doing the same with [bool] would amount to writing
a regular expression matching algorithm, which would be more
complicated, harder to understand, and harder to reason about than
a simple (non-algorithmic) definition of this property.
Conversely, an important side benefit of stating facts using
booleans is enabling some proof automation through computation
with Coq terms, a technique known as _proof by reflection_.
Consider the following statement: *)
Example even_1000 : even 1000.
(** The most direct way to prove this is to give the value of [k]
explicitly. *)
Proof. unfold even. exists 500. reflexivity. Qed.
(** The proof of the corresponding boolean statement is even
simpler (because we don't have to invent the witness: Coq's
computation mechanism does it for us!). *)
Example even_1000' : evenb 1000 = true.
Proof. reflexivity. Qed.
(** What is interesting is that, since the two notions are equivalent,
we can use the boolean formulation to prove the other one without
mentioning the value 500 explicitly: *)
Example even_1000'' : even 1000.
Proof. apply even_bool_prop. reflexivity. Qed.
(** Although we haven't gained much in terms of proof-script
size in this case, larger proofs can often be made considerably
simpler by the use of reflection. As an extreme example, a famous
Coq proof of the even more famous _4-color theorem_ uses
reflection to reduce the analysis of hundreds of different cases
to a boolean computation. *)
(** Another notable difference is that the negation of a "boolean
fact" is straightforward to state and prove: simply flip the
expected boolean result. *)
Example not_even_1001 : evenb 1001 = false.
Proof.
(* WORKED IN CLASS *)
reflexivity.
Qed.
(** In contrast, propositional negation can be more difficult
to work with directly. *)
Example not_even_1001' : ~(even 1001).
Proof.
(* WORKED IN CLASS *)
rewrite <- even_bool_prop.
unfold not.
simpl.
intro H.
discriminate H.
Qed.
(** Equality provides a complementary example, where it is sometimes
easier to work in the propositional world. Knowing that
[n =? m = true] is generally of little direct help in the middle of a
proof involving [n] and [m]; however, if we convert the statement
to the equivalent form [n = m], we can rewrite with it. *)
Lemma plus_eqb_example : forall n m p : nat,
n =? m = true -> n + p =? m + p = true.
Proof.
(* WORKED IN CLASS *)
intros n m p H.
rewrite eqb_eq in H.
rewrite H.
rewrite eqb_eq.
reflexivity.
Qed.
(** We won't discuss reflection any further here, but it serves as a
good example showing the complementary strengths of booleans and
general propositions, and being able to cross back and forth
between the boolean and propositional worlds will often be
convenient in later chapters. *)
(** **** Exercise: 2 stars, standard (logical_connectives)
The following theorems relate the propositional connectives studied
in this chapter to the corresponding boolean operations. *)
Theorem andb_true_iff : forall b1 b2:bool,
b1 && b2 = true <-> b1 = true /\ b2 = true.
Proof.
(* semi-auto proof *grim* *)
destruct b1; destruct b2;
split; intros; try split; try destruct H;
simpl; try simpl in H;
try reflexivity; try discriminate H; try discriminate H0.
Qed.
Theorem orb_true_iff : forall b1 b2,
b1 || b2 = true <-> b1 = true \/ b2 = true.
Proof.
destruct b1; destruct b2;
split; intros; try split; try destruct H;
simpl; try simpl in H;
try reflexivity; try discriminate H; try discriminate H0.
(* left with four disjunctions *)
left. reflexivity.
left. reflexivity.
right. reflexivity.
right. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 1 star, standard (eqb_neq)
The following theorem is an alternate "negative" formulation of
[eqb_eq] that is more convenient in certain situations. (We'll see
examples in later chapters.) Hint: [not_true_iff_false]. *)
Theorem eqb_neq : forall x y : nat,
x =? y = false <-> x <> y.
Proof.
intros. unfold not. split; intros.
- apply not_true_iff_false in H.
apply H.
rewrite <- H0.
rewrite <- eqb_refl.
reflexivity.
- apply not_true_iff_false.
intro.
apply H.
apply eqb_eq in H0.
apply H0.
Qed.
(** [] *)
(** **** Exercise: 3 stars, standard (eqb_list)
Given a boolean operator [eqb] for testing equality of elements of
some type [A], we can define a function [eqb_list] for testing
equality of lists with elements in [A]. Complete the definition
of the [eqb_list] function below. To make sure that your
definition is correct, prove the lemma [eqb_list_true_iff]. *)
Fixpoint eqb_list {A : Type} (eqb : A -> A -> bool)
(l1 l2 : list A) : bool :=
match (l1, l2) with
| ([], []) => true
| (x::l1', y::l2') => eqb x y && eqb_list eqb l1' l2'
| _ => false
end.
Theorem eqb_list_true_iff :
forall A (eqb : A -> A -> bool),
(forall a1 a2, eqb a1 a2 = true <-> a1 = a2) ->
forall l1 l2, eqb_list eqb l1 l2 = true <-> l1 = l2.
Proof.
split.
- (* eqb_list eqb l1 l2 = true -> l1 = l2 *)
generalize dependent l2.
induction l1 as [|x l1'].
+ (* l1 := [] *)
intros. destruct l2 as [|y l2'].
* (* l2 := [] *) reflexivity.
* (* l2 := y::l2' *) simpl in H0. discriminate H0.
+ (* l1 := x::l1' *)
destruct l2 as [|y l2'].
* (* l2 := [] *) intros. simpl in H0. discriminate H0.
* simpl. intros. f_equal.
-- (* x = y *)
apply H.
apply andb_true_iff in H0.
destruct H0.
apply H0.
-- (* l1' = l2' *)
apply IHl1'.
apply andb_true_iff in H0.
destruct H0.
apply H1.
- (* eqb_list eqb l1 l2 = true <- l1 = l2 *)
generalize dependent l2.
induction l1 as [|x l1'].
+ (* l1 := [] *)
intros. rewrite <- H0. reflexivity.
+ (* l1 := x::l1' *)
destruct l2 as [|y l2'].
* (* l2 := [] *) intros. discriminate H0.
* (* l2 := y::l2' *) intros. simpl. injection H0 as H0 H1.
apply andb_true_iff. split.
-- (* eqb x y = true *)
rewrite H0. apply H. reflexivity.
-- (* eqb_list eqb l1' l2' = true *)
rewrite <- H1. apply IHl1'. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars, standard, especially useful (All_forallb)
Recall the function [forallb], from the exercise
[forall_exists_challenge] in chapter [Tactics]: *)
Fixpoint forallb {X : Type} (test : X -> bool) (l : list X) : bool :=
match l with
| [] => true
| x :: l' => andb (test x) (forallb test l')
end.
(** Prove the theorem below, which relates [forallb] to the [All]
property defined above. *)
Theorem forallb_true_iff : forall X test (l : list X),
forallb test l = true <-> All (fun x => test x = true) l.
Proof.
intros.
induction l as [|x l' IHl].
- (* l := [] *) split.
+ (* -> direction *) intros. reflexivity.
+ (* <- direction *) intros. reflexivity.
- (* l := x :: l' *) split.
+ (* -> direction *)
simpl. intros. apply andb_true_iff in H. destruct H.
split.
* apply H.
* apply IHl. apply H0.
+ (* <- direction *) simpl. intros. destruct H.
apply andb_true_iff. split.
* apply H.
* apply IHl. apply H0.
Qed.
(** (Ungraded thought question) Are there any important properties of
the function [forallb] which are not captured by this
specification? *)
(*
This is an important property to test:
forallb test l = false <-> exists x, In x l /\ test x = false.
And below is the proof.
[] *)
Theorem andb_false_iff: forall b1 b2,
b1 && b2 = false <-> b1 = false \/ b2 = false.
Proof.
(* copy-pasting my semi-auto proof *)
destruct b1; destruct b2;
split; intros; try split; try destruct H;
simpl; try simpl in H;
try reflexivity; try discriminate H; try discriminate H0.
- left. reflexivity.
- right. reflexivity.
- left. reflexivity.
- right. reflexivity.
Qed.
Theorem negb_forallb_exists: forall A (test : A -> bool) (l : list A),
forallb test l = false <-> exists x, In x l /\ test x = false.
Proof.
intros.
induction l as [|x l' IHl].
- (* l := [] *)
simpl. split.
+ (* -> direction *) intro. discriminate H.
+ (* <- direction *) intros. destruct H. destruct H. exfalso. apply H.
- (* l := x::l' *)
simpl. split.
+ (* -> direction *)
intro.
destruct IHl.
apply andb_false_iff in H. destruct H.
* (* test x = false *) exists x. split.
left. reflexivity. apply H.
* (* forallb test l' = false *) destruct H0.
apply H. exists x0. destruct H0. split.
right. apply H0.
apply H2.
+ (* <- direction *)
intro. destruct H. destruct H.
apply andb_false_iff.
destruct H.
* left. rewrite H. apply H0.
* right. apply IHl. exists x0. split. apply H. apply H0.
Qed.
(* ================================================================= *)
(** ** Classical vs. Constructive Logic *)
(** We have seen that it is not possible to test whether or not a
proposition [P] holds while defining a Coq function. You may be
surprised to learn that a similar restriction applies to _proofs_!
In other words, the following intuitive reasoning principle is not
derivable in Coq: *)
Definition excluded_middle := forall P : Prop,
P \/ ~ P.
(** To understand operationally why this is the case, recall
that, to prove a statement of the form [P \/ Q], we use the [left]
and [right] tactics, which effectively require knowing which side
of the disjunction holds. But the universally quantified [P] in
[excluded_middle] is an _arbitrary_ proposition, which we know
nothing about. We don't have enough information to choose which
of [left] or [right] to apply, just as Coq doesn't have enough
information to mechanically decide whether [P] holds or not inside
a function. *)
(** However, if we happen to know that [P] is reflected in some
boolean term [b], then knowing whether it holds or not is trivial:
we just have to check the value of [b]. *)
Theorem restricted_excluded_middle : forall P b,
(P <-> b = true) -> P \/ ~ P.
Proof.
intros P [] H.
- left. rewrite H. reflexivity.
- right. rewrite H. intros contra. discriminate contra.
Qed.
(** In particular, the excluded middle is valid for equations [n = m],
between natural numbers [n] and [m]. *)
Theorem restricted_excluded_middle_eq : forall (n m : nat),
n = m \/ n <> m.
Proof.
intros n m.
apply (restricted_excluded_middle (n = m) (n =? m)).
symmetry.
apply eqb_eq.
Qed.
(** It may seem strange that the general excluded middle is not
available by default in Coq, since it is a standard feature of
familiar logics like ZFC. But there is a distinct advantage in
not assuming the excluded middle: statements in Coq make stronger
claims than the analogous statements in standard mathematics.
Notably, when there is a Coq proof of [exists x, P x], it is
always possible to explicitly exhibit a value of [x] for which we
can prove [P x] -- in other words, every proof of existence is
_constructive_. *)
(** Logics like Coq's, which do not assume the excluded middle, are
referred to as _constructive logics_.
More conventional logical systems such as ZFC, in which the
excluded middle does hold for arbitrary propositions, are referred
to as _classical_. *)
(** The following example illustrates why assuming the excluded middle
may lead to non-constructive proofs:
_Claim_: There exist irrational numbers [a] and [b] such that
[a ^ b] ([a] to the power [b]) is rational.
_Proof_: It is not difficult to show that [sqrt 2] is irrational.
If [sqrt 2 ^ sqrt 2] is rational, it suffices to take [a = b =
sqrt 2] and we are done. Otherwise, [sqrt 2 ^ sqrt 2] is
irrational. In this case, we can take [a = sqrt 2 ^ sqrt 2] and
[b = sqrt 2], since [a ^ b = sqrt 2 ^ (sqrt 2 * sqrt 2) = sqrt 2 ^
2 = 2]. []
Do you see what happened here? We used the excluded middle to
consider separately the cases where [sqrt 2 ^ sqrt 2] is rational
and where it is not, without knowing which one actually holds!
Because of that, we finish the proof knowing that such [a] and [b]
exist but we cannot determine what their actual values are (at least,
not from this line of argument).
As useful as constructive logic is, it does have its limitations:
There are many statements that can easily be proven in classical
logic but that have only much more complicated constructive proofs, and
there are some that are known to have no constructive proof at
all! Fortunately, like functional extensionality, the excluded
middle is known to be compatible with Coq's logic, allowing us to
add it safely as an axiom. However, we will not need to do so
here: the results that we cover can be developed entirely
within constructive logic at negligible extra cost.
It takes some practice to understand which proof techniques must
be avoided in constructive reasoning, but arguments by
contradiction, in particular, are infamous for leading to
non-constructive proofs. Here's a typical example: suppose that
we want to show that there exists [x] with some property [P],
i.e., such that [P x]. We start by assuming that our conclusion
is false; that is, [~ exists x, P x]. From this premise, it is not
hard to derive [forall x, ~ P x]. If we manage to show that this
intermediate fact results in a contradiction, we arrive at an
existence proof without ever exhibiting a value of [x] for which
[P x] holds!
The technical flaw here, from a constructive standpoint, is that
we claimed to prove [exists x, P x] using a proof of
[~ ~ (exists x, P x)]. Allowing ourselves to remove double
negations from arbitrary statements is equivalent to assuming the
excluded middle, as shown in one of the exercises below. Thus,
this line of reasoning cannot be encoded in Coq without assuming
additional axioms. *)
(** **** Exercise: 3 stars, standard (excluded_middle_irrefutable)
Proving the consistency of Coq with the general excluded middle
axiom requires complicated reasoning that cannot be carried out
within Coq itself. However, the following theorem implies that it
is always safe to assume a decidability axiom (i.e., an instance
of excluded middle) for any _particular_ Prop [P]. Why? Because
we cannot prove the negation of such an axiom. If we could, we
would have both [~ (P \/ ~P)] and [~ ~ (P \/ ~P)] (since [P]
implies [~ ~ P], by lemma [double_neg], which we proved above),
which would be a contradiction. But since we can't, it is safe
to add [P \/ ~P] as an axiom.
Succinctly: for any proposition P,
[Coq is consistent ==> (Coq + P \/ ~P) is consistent].
(Hint: you will need to come up with a clever assertion as the
next step in the proof.) *)
Theorem excluded_middle_irrefutable: forall (P:Prop),
~ ~ (P \/ ~ P).
Proof.
unfold not. intros P H.
apply H. right. intro HH. apply H. left. apply HH.
Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced (not_exists_dist)
It is a theorem of classical logic that the following two
assertions are equivalent:
~ (exists x, ~ P x)
forall x, P x
The [dist_not_exists] theorem above proves one side of this
equivalence. Interestingly, the other direction cannot be proved
in constructive logic. Your job is to show that it is implied by
the excluded middle. *)
Theorem not_exists_dist :
excluded_middle ->
forall (X:Type) (P : X -> Prop),
~ (exists x, ~ P x) -> (forall x, P x).
Proof.
intros.
assert (HH: P x \/ ~ (P x)).
{ apply H. }
destruct HH.
- apply H1.
- unfold not in H0. unfold not in H1. exfalso. apply H0.
exists x. apply H1.
Qed.
(* I proved these two above, but I still don't understand why they
work. I also can't explain how I did it. *)
(** [] *)
(** **** Exercise: 5 stars, standard, optional (classical_axioms)
For those who like a challenge, here is an exercise taken from the
Coq'Art book by Bertot and Casteran (p. 123). Each of the
following four statements, together with [excluded_middle], can be
considered as characterizing classical logic. We can't prove any
of them in Coq, but we can consistently add any one of them as an
axiom if we wish to work in classical logic.
Prove that all five propositions (these four plus [excluded_middle])
are equivalent.
Hint: Rather than considering all pairs of statements pairwise,
prove a single circular chain of implications that connects them
all. *)
Definition peirce := forall P Q: Prop,
((P->Q)->P)->P.
Definition double_negation_elimination := forall P:Prop,
~~P -> P.
Definition de_morgan_not_and_not := forall P Q:Prop,
~(~P /\ ~Q) -> P\/Q.
Definition implies_to_or := forall P Q:Prop,
(P->Q) -> (~P\/Q).
Theorem excluded_middle_implies_peirce :
excluded_middle -> peirce.
Proof.
unfold excluded_middle. unfold peirce. intros.
assert (HH: (P \/ ~P)).
{ apply H. }
destruct HH.
apply H1.
apply H0. unfold not in H1.
intro. exfalso. apply H1. apply H2.
Qed.
(* WTF? How did it work? *)
Theorem peirce_implies_double_negation_elimination :
peirce -> double_negation_elimination.
Proof.
unfold double_negation_elimination. unfold peirce. unfold not. intros.
apply (H _ False).
intro. apply H0 in H1. exfalso. apply H1.
Qed.
(* WTF???? How did it work? *)
Theorem double_negation_elimination_implies_de_morgan_not_and_not :
double_negation_elimination -> de_morgan_not_and_not.
Proof.
unfold double_negation_elimination. unfold de_morgan_not_and_not.
intros.
assert (HH: ~~(P \/ Q)).
intro. apply H0. split.
- intro. apply H1. left. apply H2.
- intro. apply H1. right. apply H2.
- apply H in HH. apply HH.
Qed.
(* I still don't understand how I did it... The symmetry looks neat though. *)
Theorem de_morgan_not_and_not_implies_implies_to_or :
de_morgan_not_and_not -> implies_to_or.
Proof.
unfold implies_to_or. unfold de_morgan_not_and_not.
intros.
assert (HH: ~(~~ P /\ ~Q) -> ~P \/ Q).
{ apply H. }
apply HH. intro. destruct H1.
apply H1. intro. apply H2. apply H0. apply H3.
Qed.
(*
I'm slowly getting it.. at least I gain some heuristic on where
should I look.
In this theorem, I know I need to use the assumption to derive the goal I was
trying to prove, namely (~P \/ Q). Then somehow it just worked.
*)
Theorem implies_implies_to_or_implies_excluded_middle :
implies_to_or -> excluded_middle.
Proof.
unfold implies_to_or. unfold excluded_middle.
intros.
assert (HH: (P -> P) -> ~P \/ P).
{ apply H. }
assert (HHH: ~P \/ P).
{ apply HH. intro. apply H0. }
destruct HHH.
- right. apply H0.
- left. apply H0.
Qed.
(* with that heuristic in mind it's much easier to work it out.
I remembered last time I was stuck here. It's really rewarding to have
proved this 5-star problem this time! Excited!
*)
(* [] *)
(* 2020-09-09 20:51 *)
|
// megafunction wizard: %Altera PLL v14.0%
// GENERATION: XML
// audio_clock.v
// Generated using ACDS version 14.0 200 at 2018.11.23.20:22:53
`timescale 1 ps / 1 ps
module audio_clock (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0 // outclk0.clk
);
audio_clock_0002 audio_clock_inst (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.reset
.outclk_0 (outclk_0), // outclk0.clk
.locked () // (terminated)
);
endmodule
// Retrieval info: <?xml version="1.0"?>
//<!--
// Generated by Altera MegaWizard Launcher Utility version 1.0
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2018 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_pll" version="14.0" >
// Retrieval info: <generic name="debug_print_output" value="false" />
// Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
// Retrieval info: <generic name="device_family" value="Cyclone V" />
// Retrieval info: <generic name="device" value="Unknown" />
// Retrieval info: <generic name="gui_device_speed_grade" value="8" />
// Retrieval info: <generic name="gui_pll_mode" value="Fractional-N PLL" />
// Retrieval info: <generic name="gui_reference_clock_frequency" value="50.0" />
// Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
// Retrieval info: <generic name="gui_operation_mode" value="direct" />
// Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
// Retrieval info: <generic name="gui_fractional_cout" value="32" />
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// Retrieval info: <generic name="gui_ps_units1" value="ps" />
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// Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_duty_cycle2" value="50" />
// Retrieval info: <generic name="gui_cascade_counter3" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency3" value="1.0" />
// Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units3" value="ps" />
// Retrieval info: <generic name="gui_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_duty_cycle3" value="50" />
// Retrieval info: <generic name="gui_cascade_counter4" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units4" value="ps" />
// Retrieval info: <generic name="gui_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_duty_cycle4" value="50" />
// Retrieval info: <generic name="gui_cascade_counter5" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c5" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units5" value="ps" />
// Retrieval info: <generic name="gui_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_duty_cycle5" value="50" />
// Retrieval info: <generic name="gui_cascade_counter6" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c6" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units6" value="ps" />
// Retrieval info: <generic name="gui_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_duty_cycle6" value="50" />
// Retrieval info: <generic name="gui_cascade_counter7" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c7" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units7" value="ps" />
// Retrieval info: <generic name="gui_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_duty_cycle7" value="50" />
// Retrieval info: <generic name="gui_cascade_counter8" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c8" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units8" value="ps" />
// Retrieval info: <generic name="gui_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_duty_cycle8" value="50" />
// Retrieval info: <generic name="gui_cascade_counter9" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c9" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units9" value="ps" />
// Retrieval info: <generic name="gui_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_duty_cycle9" value="50" />
// Retrieval info: <generic name="gui_cascade_counter10" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units10" value="ps" />
// Retrieval info: <generic name="gui_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_duty_cycle10" value="50" />
// Retrieval info: <generic name="gui_cascade_counter11" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c11" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units11" value="ps" />
// Retrieval info: <generic name="gui_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_duty_cycle11" value="50" />
// Retrieval info: <generic name="gui_cascade_counter12" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c12" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units12" value="ps" />
// Retrieval info: <generic name="gui_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_duty_cycle12" value="50" />
// Retrieval info: <generic name="gui_cascade_counter13" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c13" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units13" value="ps" />
// Retrieval info: <generic name="gui_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_duty_cycle13" value="50" />
// Retrieval info: <generic name="gui_cascade_counter14" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c14" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units14" value="ps" />
// Retrieval info: <generic name="gui_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_duty_cycle14" value="50" />
// Retrieval info: <generic name="gui_cascade_counter15" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c15" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units15" value="ps" />
// Retrieval info: <generic name="gui_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_duty_cycle15" value="50" />
// Retrieval info: <generic name="gui_cascade_counter16" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c16" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units16" value="ps" />
// Retrieval info: <generic name="gui_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_duty_cycle16" value="50" />
// Retrieval info: <generic name="gui_cascade_counter17" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c17" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units17" value="ps" />
// Retrieval info: <generic name="gui_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_duty_cycle17" value="50" />
// Retrieval info: <generic name="gui_pll_auto_reset" value="On" />
// Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
// Retrieval info: <generic name="gui_en_reconf" value="false" />
// Retrieval info: <generic name="gui_en_dps_ports" value="false" />
// Retrieval info: <generic name="gui_en_phout_ports" value="false" />
// Retrieval info: <generic name="gui_phout_division" value="1" />
// Retrieval info: <generic name="gui_en_lvds_ports" value="false" />
// Retrieval info: <generic name="gui_mif_generate" value="false" />
// Retrieval info: <generic name="gui_enable_mif_dps" value="false" />
// Retrieval info: <generic name="gui_dps_cntr" value="C0" />
// Retrieval info: <generic name="gui_dps_num" value="1" />
// Retrieval info: <generic name="gui_dps_dir" value="Positive" />
// Retrieval info: <generic name="gui_refclk_switch" value="false" />
// Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
// Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
// Retrieval info: <generic name="gui_switchover_delay" value="0" />
// Retrieval info: <generic name="gui_active_clk" value="false" />
// Retrieval info: <generic name="gui_clk_bad" value="false" />
// Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
// Retrieval info: <generic name="gui_cascade_outclk_index" value="0" />
// Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
// Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
// Retrieval info: <generic name="AUTO_REFCLK_CLOCK_RATE" value="-1" />
// Retrieval info: </instance>
// IPFS_FILES : audio_clock.vo
// RELATED_FILES: audio_clock.v, audio_clock_0002.v
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:46:23 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_mdm_1_0/system_mdm_1_0_sim_netlist.v
// Design : system_mdm_1_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_mdm_1_0,MDM,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "MDM,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_mdm_1_0
(Debug_SYS_Rst,
Dbg_Clk_0,
Dbg_TDI_0,
Dbg_TDO_0,
Dbg_Reg_En_0,
Dbg_Capture_0,
Dbg_Shift_0,
Dbg_Update_0,
Dbg_Rst_0,
Dbg_Disable_0);
(* x_interface_info = "xilinx.com:signal:reset:1.0 RST.Debug_SYS_Rst RST" *) output Debug_SYS_Rst;
(* x_interface_info = "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 CLK" *) output Dbg_Clk_0;
(* x_interface_info = "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 TDI" *) output Dbg_TDI_0;
(* x_interface_info = "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 TDO" *) input Dbg_TDO_0;
(* x_interface_info = "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 REG_EN" *) output [0:7]Dbg_Reg_En_0;
(* x_interface_info = "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 CAPTURE" *) output Dbg_Capture_0;
(* x_interface_info = "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 SHIFT" *) output Dbg_Shift_0;
(* x_interface_info = "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 UPDATE" *) output Dbg_Update_0;
(* x_interface_info = "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 RST" *) output Dbg_Rst_0;
(* x_interface_info = "xilinx.com:interface:mbdebug:3.0 MBDEBUG_0 DISABLE" *) output Dbg_Disable_0;
wire Dbg_Capture_0;
wire Dbg_Clk_0;
wire Dbg_Disable_0;
wire [0:7]Dbg_Reg_En_0;
wire Dbg_Rst_0;
wire Dbg_Shift_0;
wire Dbg_TDI_0;
wire Dbg_TDO_0;
wire Dbg_Update_0;
wire Debug_SYS_Rst;
wire NLW_U0_Dbg_ARVALID_0_UNCONNECTED;
wire NLW_U0_Dbg_ARVALID_1_UNCONNECTED;
wire NLW_U0_Dbg_ARVALID_10_UNCONNECTED;
wire NLW_U0_Dbg_ARVALID_11_UNCONNECTED;
wire NLW_U0_Dbg_ARVALID_12_UNCONNECTED;
wire NLW_U0_Dbg_ARVALID_13_UNCONNECTED;
wire NLW_U0_Dbg_ARVALID_14_UNCONNECTED;
wire NLW_U0_Dbg_ARVALID_15_UNCONNECTED;
wire NLW_U0_Dbg_ARVALID_16_UNCONNECTED;
wire NLW_U0_Dbg_ARVALID_17_UNCONNECTED;
wire NLW_U0_Dbg_ARVALID_18_UNCONNECTED;
wire NLW_U0_Dbg_ARVALID_19_UNCONNECTED;
wire NLW_U0_Dbg_ARVALID_2_UNCONNECTED;
wire NLW_U0_Dbg_ARVALID_20_UNCONNECTED;
wire NLW_U0_Dbg_ARVALID_21_UNCONNECTED;
wire NLW_U0_Dbg_ARVALID_22_UNCONNECTED;
wire NLW_U0_Dbg_ARVALID_23_UNCONNECTED;
wire NLW_U0_Dbg_ARVALID_24_UNCONNECTED;
wire NLW_U0_Dbg_ARVALID_25_UNCONNECTED;
wire NLW_U0_Dbg_ARVALID_26_UNCONNECTED;
wire NLW_U0_Dbg_ARVALID_27_UNCONNECTED;
wire NLW_U0_Dbg_ARVALID_28_UNCONNECTED;
wire NLW_U0_Dbg_ARVALID_29_UNCONNECTED;
wire NLW_U0_Dbg_ARVALID_3_UNCONNECTED;
wire NLW_U0_Dbg_ARVALID_30_UNCONNECTED;
wire NLW_U0_Dbg_ARVALID_31_UNCONNECTED;
wire NLW_U0_Dbg_ARVALID_4_UNCONNECTED;
wire NLW_U0_Dbg_ARVALID_5_UNCONNECTED;
wire NLW_U0_Dbg_ARVALID_6_UNCONNECTED;
wire NLW_U0_Dbg_ARVALID_7_UNCONNECTED;
wire NLW_U0_Dbg_ARVALID_8_UNCONNECTED;
wire NLW_U0_Dbg_ARVALID_9_UNCONNECTED;
wire NLW_U0_Dbg_AWVALID_0_UNCONNECTED;
wire NLW_U0_Dbg_AWVALID_1_UNCONNECTED;
wire NLW_U0_Dbg_AWVALID_10_UNCONNECTED;
wire NLW_U0_Dbg_AWVALID_11_UNCONNECTED;
wire NLW_U0_Dbg_AWVALID_12_UNCONNECTED;
wire NLW_U0_Dbg_AWVALID_13_UNCONNECTED;
wire NLW_U0_Dbg_AWVALID_14_UNCONNECTED;
wire NLW_U0_Dbg_AWVALID_15_UNCONNECTED;
wire NLW_U0_Dbg_AWVALID_16_UNCONNECTED;
wire NLW_U0_Dbg_AWVALID_17_UNCONNECTED;
wire NLW_U0_Dbg_AWVALID_18_UNCONNECTED;
wire NLW_U0_Dbg_AWVALID_19_UNCONNECTED;
wire NLW_U0_Dbg_AWVALID_2_UNCONNECTED;
wire NLW_U0_Dbg_AWVALID_20_UNCONNECTED;
wire NLW_U0_Dbg_AWVALID_21_UNCONNECTED;
wire NLW_U0_Dbg_AWVALID_22_UNCONNECTED;
wire NLW_U0_Dbg_AWVALID_23_UNCONNECTED;
wire NLW_U0_Dbg_AWVALID_24_UNCONNECTED;
wire NLW_U0_Dbg_AWVALID_25_UNCONNECTED;
wire NLW_U0_Dbg_AWVALID_26_UNCONNECTED;
wire NLW_U0_Dbg_AWVALID_27_UNCONNECTED;
wire NLW_U0_Dbg_AWVALID_28_UNCONNECTED;
wire NLW_U0_Dbg_AWVALID_29_UNCONNECTED;
wire NLW_U0_Dbg_AWVALID_3_UNCONNECTED;
wire NLW_U0_Dbg_AWVALID_30_UNCONNECTED;
wire NLW_U0_Dbg_AWVALID_31_UNCONNECTED;
wire NLW_U0_Dbg_AWVALID_4_UNCONNECTED;
wire NLW_U0_Dbg_AWVALID_5_UNCONNECTED;
wire NLW_U0_Dbg_AWVALID_6_UNCONNECTED;
wire NLW_U0_Dbg_AWVALID_7_UNCONNECTED;
wire NLW_U0_Dbg_AWVALID_8_UNCONNECTED;
wire NLW_U0_Dbg_AWVALID_9_UNCONNECTED;
wire NLW_U0_Dbg_BREADY_0_UNCONNECTED;
wire NLW_U0_Dbg_BREADY_1_UNCONNECTED;
wire NLW_U0_Dbg_BREADY_10_UNCONNECTED;
wire NLW_U0_Dbg_BREADY_11_UNCONNECTED;
wire NLW_U0_Dbg_BREADY_12_UNCONNECTED;
wire NLW_U0_Dbg_BREADY_13_UNCONNECTED;
wire NLW_U0_Dbg_BREADY_14_UNCONNECTED;
wire NLW_U0_Dbg_BREADY_15_UNCONNECTED;
wire NLW_U0_Dbg_BREADY_16_UNCONNECTED;
wire NLW_U0_Dbg_BREADY_17_UNCONNECTED;
wire NLW_U0_Dbg_BREADY_18_UNCONNECTED;
wire NLW_U0_Dbg_BREADY_19_UNCONNECTED;
wire NLW_U0_Dbg_BREADY_2_UNCONNECTED;
wire NLW_U0_Dbg_BREADY_20_UNCONNECTED;
wire NLW_U0_Dbg_BREADY_21_UNCONNECTED;
wire NLW_U0_Dbg_BREADY_22_UNCONNECTED;
wire NLW_U0_Dbg_BREADY_23_UNCONNECTED;
wire NLW_U0_Dbg_BREADY_24_UNCONNECTED;
wire NLW_U0_Dbg_BREADY_25_UNCONNECTED;
wire NLW_U0_Dbg_BREADY_26_UNCONNECTED;
wire NLW_U0_Dbg_BREADY_27_UNCONNECTED;
wire NLW_U0_Dbg_BREADY_28_UNCONNECTED;
wire NLW_U0_Dbg_BREADY_29_UNCONNECTED;
wire NLW_U0_Dbg_BREADY_3_UNCONNECTED;
wire NLW_U0_Dbg_BREADY_30_UNCONNECTED;
wire NLW_U0_Dbg_BREADY_31_UNCONNECTED;
wire NLW_U0_Dbg_BREADY_4_UNCONNECTED;
wire NLW_U0_Dbg_BREADY_5_UNCONNECTED;
wire NLW_U0_Dbg_BREADY_6_UNCONNECTED;
wire NLW_U0_Dbg_BREADY_7_UNCONNECTED;
wire NLW_U0_Dbg_BREADY_8_UNCONNECTED;
wire NLW_U0_Dbg_BREADY_9_UNCONNECTED;
wire NLW_U0_Dbg_Capture_1_UNCONNECTED;
wire NLW_U0_Dbg_Capture_10_UNCONNECTED;
wire NLW_U0_Dbg_Capture_11_UNCONNECTED;
wire NLW_U0_Dbg_Capture_12_UNCONNECTED;
wire NLW_U0_Dbg_Capture_13_UNCONNECTED;
wire NLW_U0_Dbg_Capture_14_UNCONNECTED;
wire NLW_U0_Dbg_Capture_15_UNCONNECTED;
wire NLW_U0_Dbg_Capture_16_UNCONNECTED;
wire NLW_U0_Dbg_Capture_17_UNCONNECTED;
wire NLW_U0_Dbg_Capture_18_UNCONNECTED;
wire NLW_U0_Dbg_Capture_19_UNCONNECTED;
wire NLW_U0_Dbg_Capture_2_UNCONNECTED;
wire NLW_U0_Dbg_Capture_20_UNCONNECTED;
wire NLW_U0_Dbg_Capture_21_UNCONNECTED;
wire NLW_U0_Dbg_Capture_22_UNCONNECTED;
wire NLW_U0_Dbg_Capture_23_UNCONNECTED;
wire NLW_U0_Dbg_Capture_24_UNCONNECTED;
wire NLW_U0_Dbg_Capture_25_UNCONNECTED;
wire NLW_U0_Dbg_Capture_26_UNCONNECTED;
wire NLW_U0_Dbg_Capture_27_UNCONNECTED;
wire NLW_U0_Dbg_Capture_28_UNCONNECTED;
wire NLW_U0_Dbg_Capture_29_UNCONNECTED;
wire NLW_U0_Dbg_Capture_3_UNCONNECTED;
wire NLW_U0_Dbg_Capture_30_UNCONNECTED;
wire NLW_U0_Dbg_Capture_31_UNCONNECTED;
wire NLW_U0_Dbg_Capture_4_UNCONNECTED;
wire NLW_U0_Dbg_Capture_5_UNCONNECTED;
wire NLW_U0_Dbg_Capture_6_UNCONNECTED;
wire NLW_U0_Dbg_Capture_7_UNCONNECTED;
wire NLW_U0_Dbg_Capture_8_UNCONNECTED;
wire NLW_U0_Dbg_Capture_9_UNCONNECTED;
wire NLW_U0_Dbg_Clk_1_UNCONNECTED;
wire NLW_U0_Dbg_Clk_10_UNCONNECTED;
wire NLW_U0_Dbg_Clk_11_UNCONNECTED;
wire NLW_U0_Dbg_Clk_12_UNCONNECTED;
wire NLW_U0_Dbg_Clk_13_UNCONNECTED;
wire NLW_U0_Dbg_Clk_14_UNCONNECTED;
wire NLW_U0_Dbg_Clk_15_UNCONNECTED;
wire NLW_U0_Dbg_Clk_16_UNCONNECTED;
wire NLW_U0_Dbg_Clk_17_UNCONNECTED;
wire NLW_U0_Dbg_Clk_18_UNCONNECTED;
wire NLW_U0_Dbg_Clk_19_UNCONNECTED;
wire NLW_U0_Dbg_Clk_2_UNCONNECTED;
wire NLW_U0_Dbg_Clk_20_UNCONNECTED;
wire NLW_U0_Dbg_Clk_21_UNCONNECTED;
wire NLW_U0_Dbg_Clk_22_UNCONNECTED;
wire NLW_U0_Dbg_Clk_23_UNCONNECTED;
wire NLW_U0_Dbg_Clk_24_UNCONNECTED;
wire NLW_U0_Dbg_Clk_25_UNCONNECTED;
wire NLW_U0_Dbg_Clk_26_UNCONNECTED;
wire NLW_U0_Dbg_Clk_27_UNCONNECTED;
wire NLW_U0_Dbg_Clk_28_UNCONNECTED;
wire NLW_U0_Dbg_Clk_29_UNCONNECTED;
wire NLW_U0_Dbg_Clk_3_UNCONNECTED;
wire NLW_U0_Dbg_Clk_30_UNCONNECTED;
wire NLW_U0_Dbg_Clk_31_UNCONNECTED;
wire NLW_U0_Dbg_Clk_4_UNCONNECTED;
wire NLW_U0_Dbg_Clk_5_UNCONNECTED;
wire NLW_U0_Dbg_Clk_6_UNCONNECTED;
wire NLW_U0_Dbg_Clk_7_UNCONNECTED;
wire NLW_U0_Dbg_Clk_8_UNCONNECTED;
wire NLW_U0_Dbg_Clk_9_UNCONNECTED;
wire NLW_U0_Dbg_Disable_1_UNCONNECTED;
wire NLW_U0_Dbg_Disable_10_UNCONNECTED;
wire NLW_U0_Dbg_Disable_11_UNCONNECTED;
wire NLW_U0_Dbg_Disable_12_UNCONNECTED;
wire NLW_U0_Dbg_Disable_13_UNCONNECTED;
wire NLW_U0_Dbg_Disable_14_UNCONNECTED;
wire NLW_U0_Dbg_Disable_15_UNCONNECTED;
wire NLW_U0_Dbg_Disable_16_UNCONNECTED;
wire NLW_U0_Dbg_Disable_17_UNCONNECTED;
wire NLW_U0_Dbg_Disable_18_UNCONNECTED;
wire NLW_U0_Dbg_Disable_19_UNCONNECTED;
wire NLW_U0_Dbg_Disable_2_UNCONNECTED;
wire NLW_U0_Dbg_Disable_20_UNCONNECTED;
wire NLW_U0_Dbg_Disable_21_UNCONNECTED;
wire NLW_U0_Dbg_Disable_22_UNCONNECTED;
wire NLW_U0_Dbg_Disable_23_UNCONNECTED;
wire NLW_U0_Dbg_Disable_24_UNCONNECTED;
wire NLW_U0_Dbg_Disable_25_UNCONNECTED;
wire NLW_U0_Dbg_Disable_26_UNCONNECTED;
wire NLW_U0_Dbg_Disable_27_UNCONNECTED;
wire NLW_U0_Dbg_Disable_28_UNCONNECTED;
wire NLW_U0_Dbg_Disable_29_UNCONNECTED;
wire NLW_U0_Dbg_Disable_3_UNCONNECTED;
wire NLW_U0_Dbg_Disable_30_UNCONNECTED;
wire NLW_U0_Dbg_Disable_31_UNCONNECTED;
wire NLW_U0_Dbg_Disable_4_UNCONNECTED;
wire NLW_U0_Dbg_Disable_5_UNCONNECTED;
wire NLW_U0_Dbg_Disable_6_UNCONNECTED;
wire NLW_U0_Dbg_Disable_7_UNCONNECTED;
wire NLW_U0_Dbg_Disable_8_UNCONNECTED;
wire NLW_U0_Dbg_Disable_9_UNCONNECTED;
wire NLW_U0_Dbg_RREADY_0_UNCONNECTED;
wire NLW_U0_Dbg_RREADY_1_UNCONNECTED;
wire NLW_U0_Dbg_RREADY_10_UNCONNECTED;
wire NLW_U0_Dbg_RREADY_11_UNCONNECTED;
wire NLW_U0_Dbg_RREADY_12_UNCONNECTED;
wire NLW_U0_Dbg_RREADY_13_UNCONNECTED;
wire NLW_U0_Dbg_RREADY_14_UNCONNECTED;
wire NLW_U0_Dbg_RREADY_15_UNCONNECTED;
wire NLW_U0_Dbg_RREADY_16_UNCONNECTED;
wire NLW_U0_Dbg_RREADY_17_UNCONNECTED;
wire NLW_U0_Dbg_RREADY_18_UNCONNECTED;
wire NLW_U0_Dbg_RREADY_19_UNCONNECTED;
wire NLW_U0_Dbg_RREADY_2_UNCONNECTED;
wire NLW_U0_Dbg_RREADY_20_UNCONNECTED;
wire NLW_U0_Dbg_RREADY_21_UNCONNECTED;
wire NLW_U0_Dbg_RREADY_22_UNCONNECTED;
wire NLW_U0_Dbg_RREADY_23_UNCONNECTED;
wire NLW_U0_Dbg_RREADY_24_UNCONNECTED;
wire NLW_U0_Dbg_RREADY_25_UNCONNECTED;
wire NLW_U0_Dbg_RREADY_26_UNCONNECTED;
wire NLW_U0_Dbg_RREADY_27_UNCONNECTED;
wire NLW_U0_Dbg_RREADY_28_UNCONNECTED;
wire NLW_U0_Dbg_RREADY_29_UNCONNECTED;
wire NLW_U0_Dbg_RREADY_3_UNCONNECTED;
wire NLW_U0_Dbg_RREADY_30_UNCONNECTED;
wire NLW_U0_Dbg_RREADY_31_UNCONNECTED;
wire NLW_U0_Dbg_RREADY_4_UNCONNECTED;
wire NLW_U0_Dbg_RREADY_5_UNCONNECTED;
wire NLW_U0_Dbg_RREADY_6_UNCONNECTED;
wire NLW_U0_Dbg_RREADY_7_UNCONNECTED;
wire NLW_U0_Dbg_RREADY_8_UNCONNECTED;
wire NLW_U0_Dbg_RREADY_9_UNCONNECTED;
wire NLW_U0_Dbg_Rst_1_UNCONNECTED;
wire NLW_U0_Dbg_Rst_10_UNCONNECTED;
wire NLW_U0_Dbg_Rst_11_UNCONNECTED;
wire NLW_U0_Dbg_Rst_12_UNCONNECTED;
wire NLW_U0_Dbg_Rst_13_UNCONNECTED;
wire NLW_U0_Dbg_Rst_14_UNCONNECTED;
wire NLW_U0_Dbg_Rst_15_UNCONNECTED;
wire NLW_U0_Dbg_Rst_16_UNCONNECTED;
wire NLW_U0_Dbg_Rst_17_UNCONNECTED;
wire NLW_U0_Dbg_Rst_18_UNCONNECTED;
wire NLW_U0_Dbg_Rst_19_UNCONNECTED;
wire NLW_U0_Dbg_Rst_2_UNCONNECTED;
wire NLW_U0_Dbg_Rst_20_UNCONNECTED;
wire NLW_U0_Dbg_Rst_21_UNCONNECTED;
wire NLW_U0_Dbg_Rst_22_UNCONNECTED;
wire NLW_U0_Dbg_Rst_23_UNCONNECTED;
wire NLW_U0_Dbg_Rst_24_UNCONNECTED;
wire NLW_U0_Dbg_Rst_25_UNCONNECTED;
wire NLW_U0_Dbg_Rst_26_UNCONNECTED;
wire NLW_U0_Dbg_Rst_27_UNCONNECTED;
wire NLW_U0_Dbg_Rst_28_UNCONNECTED;
wire NLW_U0_Dbg_Rst_29_UNCONNECTED;
wire NLW_U0_Dbg_Rst_3_UNCONNECTED;
wire NLW_U0_Dbg_Rst_30_UNCONNECTED;
wire NLW_U0_Dbg_Rst_31_UNCONNECTED;
wire NLW_U0_Dbg_Rst_4_UNCONNECTED;
wire NLW_U0_Dbg_Rst_5_UNCONNECTED;
wire NLW_U0_Dbg_Rst_6_UNCONNECTED;
wire NLW_U0_Dbg_Rst_7_UNCONNECTED;
wire NLW_U0_Dbg_Rst_8_UNCONNECTED;
wire NLW_U0_Dbg_Rst_9_UNCONNECTED;
wire NLW_U0_Dbg_Shift_1_UNCONNECTED;
wire NLW_U0_Dbg_Shift_10_UNCONNECTED;
wire NLW_U0_Dbg_Shift_11_UNCONNECTED;
wire NLW_U0_Dbg_Shift_12_UNCONNECTED;
wire NLW_U0_Dbg_Shift_13_UNCONNECTED;
wire NLW_U0_Dbg_Shift_14_UNCONNECTED;
wire NLW_U0_Dbg_Shift_15_UNCONNECTED;
wire NLW_U0_Dbg_Shift_16_UNCONNECTED;
wire NLW_U0_Dbg_Shift_17_UNCONNECTED;
wire NLW_U0_Dbg_Shift_18_UNCONNECTED;
wire NLW_U0_Dbg_Shift_19_UNCONNECTED;
wire NLW_U0_Dbg_Shift_2_UNCONNECTED;
wire NLW_U0_Dbg_Shift_20_UNCONNECTED;
wire NLW_U0_Dbg_Shift_21_UNCONNECTED;
wire NLW_U0_Dbg_Shift_22_UNCONNECTED;
wire NLW_U0_Dbg_Shift_23_UNCONNECTED;
wire NLW_U0_Dbg_Shift_24_UNCONNECTED;
wire NLW_U0_Dbg_Shift_25_UNCONNECTED;
wire NLW_U0_Dbg_Shift_26_UNCONNECTED;
wire NLW_U0_Dbg_Shift_27_UNCONNECTED;
wire NLW_U0_Dbg_Shift_28_UNCONNECTED;
wire NLW_U0_Dbg_Shift_29_UNCONNECTED;
wire NLW_U0_Dbg_Shift_3_UNCONNECTED;
wire NLW_U0_Dbg_Shift_30_UNCONNECTED;
wire NLW_U0_Dbg_Shift_31_UNCONNECTED;
wire NLW_U0_Dbg_Shift_4_UNCONNECTED;
wire NLW_U0_Dbg_Shift_5_UNCONNECTED;
wire NLW_U0_Dbg_Shift_6_UNCONNECTED;
wire NLW_U0_Dbg_Shift_7_UNCONNECTED;
wire NLW_U0_Dbg_Shift_8_UNCONNECTED;
wire NLW_U0_Dbg_Shift_9_UNCONNECTED;
wire NLW_U0_Dbg_TDI_1_UNCONNECTED;
wire NLW_U0_Dbg_TDI_10_UNCONNECTED;
wire NLW_U0_Dbg_TDI_11_UNCONNECTED;
wire NLW_U0_Dbg_TDI_12_UNCONNECTED;
wire NLW_U0_Dbg_TDI_13_UNCONNECTED;
wire NLW_U0_Dbg_TDI_14_UNCONNECTED;
wire NLW_U0_Dbg_TDI_15_UNCONNECTED;
wire NLW_U0_Dbg_TDI_16_UNCONNECTED;
wire NLW_U0_Dbg_TDI_17_UNCONNECTED;
wire NLW_U0_Dbg_TDI_18_UNCONNECTED;
wire NLW_U0_Dbg_TDI_19_UNCONNECTED;
wire NLW_U0_Dbg_TDI_2_UNCONNECTED;
wire NLW_U0_Dbg_TDI_20_UNCONNECTED;
wire NLW_U0_Dbg_TDI_21_UNCONNECTED;
wire NLW_U0_Dbg_TDI_22_UNCONNECTED;
wire NLW_U0_Dbg_TDI_23_UNCONNECTED;
wire NLW_U0_Dbg_TDI_24_UNCONNECTED;
wire NLW_U0_Dbg_TDI_25_UNCONNECTED;
wire NLW_U0_Dbg_TDI_26_UNCONNECTED;
wire NLW_U0_Dbg_TDI_27_UNCONNECTED;
wire NLW_U0_Dbg_TDI_28_UNCONNECTED;
wire NLW_U0_Dbg_TDI_29_UNCONNECTED;
wire NLW_U0_Dbg_TDI_3_UNCONNECTED;
wire NLW_U0_Dbg_TDI_30_UNCONNECTED;
wire NLW_U0_Dbg_TDI_31_UNCONNECTED;
wire NLW_U0_Dbg_TDI_4_UNCONNECTED;
wire NLW_U0_Dbg_TDI_5_UNCONNECTED;
wire NLW_U0_Dbg_TDI_6_UNCONNECTED;
wire NLW_U0_Dbg_TDI_7_UNCONNECTED;
wire NLW_U0_Dbg_TDI_8_UNCONNECTED;
wire NLW_U0_Dbg_TDI_9_UNCONNECTED;
wire NLW_U0_Dbg_TrClk_0_UNCONNECTED;
wire NLW_U0_Dbg_TrClk_1_UNCONNECTED;
wire NLW_U0_Dbg_TrClk_10_UNCONNECTED;
wire NLW_U0_Dbg_TrClk_11_UNCONNECTED;
wire NLW_U0_Dbg_TrClk_12_UNCONNECTED;
wire NLW_U0_Dbg_TrClk_13_UNCONNECTED;
wire NLW_U0_Dbg_TrClk_14_UNCONNECTED;
wire NLW_U0_Dbg_TrClk_15_UNCONNECTED;
wire NLW_U0_Dbg_TrClk_16_UNCONNECTED;
wire NLW_U0_Dbg_TrClk_17_UNCONNECTED;
wire NLW_U0_Dbg_TrClk_18_UNCONNECTED;
wire NLW_U0_Dbg_TrClk_19_UNCONNECTED;
wire NLW_U0_Dbg_TrClk_2_UNCONNECTED;
wire NLW_U0_Dbg_TrClk_20_UNCONNECTED;
wire NLW_U0_Dbg_TrClk_21_UNCONNECTED;
wire NLW_U0_Dbg_TrClk_22_UNCONNECTED;
wire NLW_U0_Dbg_TrClk_23_UNCONNECTED;
wire NLW_U0_Dbg_TrClk_24_UNCONNECTED;
wire NLW_U0_Dbg_TrClk_25_UNCONNECTED;
wire NLW_U0_Dbg_TrClk_26_UNCONNECTED;
wire NLW_U0_Dbg_TrClk_27_UNCONNECTED;
wire NLW_U0_Dbg_TrClk_28_UNCONNECTED;
wire NLW_U0_Dbg_TrClk_29_UNCONNECTED;
wire NLW_U0_Dbg_TrClk_3_UNCONNECTED;
wire NLW_U0_Dbg_TrClk_30_UNCONNECTED;
wire NLW_U0_Dbg_TrClk_31_UNCONNECTED;
wire NLW_U0_Dbg_TrClk_4_UNCONNECTED;
wire NLW_U0_Dbg_TrClk_5_UNCONNECTED;
wire NLW_U0_Dbg_TrClk_6_UNCONNECTED;
wire NLW_U0_Dbg_TrClk_7_UNCONNECTED;
wire NLW_U0_Dbg_TrClk_8_UNCONNECTED;
wire NLW_U0_Dbg_TrClk_9_UNCONNECTED;
wire NLW_U0_Dbg_TrReady_0_UNCONNECTED;
wire NLW_U0_Dbg_TrReady_1_UNCONNECTED;
wire NLW_U0_Dbg_TrReady_10_UNCONNECTED;
wire NLW_U0_Dbg_TrReady_11_UNCONNECTED;
wire NLW_U0_Dbg_TrReady_12_UNCONNECTED;
wire NLW_U0_Dbg_TrReady_13_UNCONNECTED;
wire NLW_U0_Dbg_TrReady_14_UNCONNECTED;
wire NLW_U0_Dbg_TrReady_15_UNCONNECTED;
wire NLW_U0_Dbg_TrReady_16_UNCONNECTED;
wire NLW_U0_Dbg_TrReady_17_UNCONNECTED;
wire NLW_U0_Dbg_TrReady_18_UNCONNECTED;
wire NLW_U0_Dbg_TrReady_19_UNCONNECTED;
wire NLW_U0_Dbg_TrReady_2_UNCONNECTED;
wire NLW_U0_Dbg_TrReady_20_UNCONNECTED;
wire NLW_U0_Dbg_TrReady_21_UNCONNECTED;
wire NLW_U0_Dbg_TrReady_22_UNCONNECTED;
wire NLW_U0_Dbg_TrReady_23_UNCONNECTED;
wire NLW_U0_Dbg_TrReady_24_UNCONNECTED;
wire NLW_U0_Dbg_TrReady_25_UNCONNECTED;
wire NLW_U0_Dbg_TrReady_26_UNCONNECTED;
wire NLW_U0_Dbg_TrReady_27_UNCONNECTED;
wire NLW_U0_Dbg_TrReady_28_UNCONNECTED;
wire NLW_U0_Dbg_TrReady_29_UNCONNECTED;
wire NLW_U0_Dbg_TrReady_3_UNCONNECTED;
wire NLW_U0_Dbg_TrReady_30_UNCONNECTED;
wire NLW_U0_Dbg_TrReady_31_UNCONNECTED;
wire NLW_U0_Dbg_TrReady_4_UNCONNECTED;
wire NLW_U0_Dbg_TrReady_5_UNCONNECTED;
wire NLW_U0_Dbg_TrReady_6_UNCONNECTED;
wire NLW_U0_Dbg_TrReady_7_UNCONNECTED;
wire NLW_U0_Dbg_TrReady_8_UNCONNECTED;
wire NLW_U0_Dbg_TrReady_9_UNCONNECTED;
wire NLW_U0_Dbg_Update_1_UNCONNECTED;
wire NLW_U0_Dbg_Update_10_UNCONNECTED;
wire NLW_U0_Dbg_Update_11_UNCONNECTED;
wire NLW_U0_Dbg_Update_12_UNCONNECTED;
wire NLW_U0_Dbg_Update_13_UNCONNECTED;
wire NLW_U0_Dbg_Update_14_UNCONNECTED;
wire NLW_U0_Dbg_Update_15_UNCONNECTED;
wire NLW_U0_Dbg_Update_16_UNCONNECTED;
wire NLW_U0_Dbg_Update_17_UNCONNECTED;
wire NLW_U0_Dbg_Update_18_UNCONNECTED;
wire NLW_U0_Dbg_Update_19_UNCONNECTED;
wire NLW_U0_Dbg_Update_2_UNCONNECTED;
wire NLW_U0_Dbg_Update_20_UNCONNECTED;
wire NLW_U0_Dbg_Update_21_UNCONNECTED;
wire NLW_U0_Dbg_Update_22_UNCONNECTED;
wire NLW_U0_Dbg_Update_23_UNCONNECTED;
wire NLW_U0_Dbg_Update_24_UNCONNECTED;
wire NLW_U0_Dbg_Update_25_UNCONNECTED;
wire NLW_U0_Dbg_Update_26_UNCONNECTED;
wire NLW_U0_Dbg_Update_27_UNCONNECTED;
wire NLW_U0_Dbg_Update_28_UNCONNECTED;
wire NLW_U0_Dbg_Update_29_UNCONNECTED;
wire NLW_U0_Dbg_Update_3_UNCONNECTED;
wire NLW_U0_Dbg_Update_30_UNCONNECTED;
wire NLW_U0_Dbg_Update_31_UNCONNECTED;
wire NLW_U0_Dbg_Update_4_UNCONNECTED;
wire NLW_U0_Dbg_Update_5_UNCONNECTED;
wire NLW_U0_Dbg_Update_6_UNCONNECTED;
wire NLW_U0_Dbg_Update_7_UNCONNECTED;
wire NLW_U0_Dbg_Update_8_UNCONNECTED;
wire NLW_U0_Dbg_Update_9_UNCONNECTED;
wire NLW_U0_Dbg_WVALID_0_UNCONNECTED;
wire NLW_U0_Dbg_WVALID_1_UNCONNECTED;
wire NLW_U0_Dbg_WVALID_10_UNCONNECTED;
wire NLW_U0_Dbg_WVALID_11_UNCONNECTED;
wire NLW_U0_Dbg_WVALID_12_UNCONNECTED;
wire NLW_U0_Dbg_WVALID_13_UNCONNECTED;
wire NLW_U0_Dbg_WVALID_14_UNCONNECTED;
wire NLW_U0_Dbg_WVALID_15_UNCONNECTED;
wire NLW_U0_Dbg_WVALID_16_UNCONNECTED;
wire NLW_U0_Dbg_WVALID_17_UNCONNECTED;
wire NLW_U0_Dbg_WVALID_18_UNCONNECTED;
wire NLW_U0_Dbg_WVALID_19_UNCONNECTED;
wire NLW_U0_Dbg_WVALID_2_UNCONNECTED;
wire NLW_U0_Dbg_WVALID_20_UNCONNECTED;
wire NLW_U0_Dbg_WVALID_21_UNCONNECTED;
wire NLW_U0_Dbg_WVALID_22_UNCONNECTED;
wire NLW_U0_Dbg_WVALID_23_UNCONNECTED;
wire NLW_U0_Dbg_WVALID_24_UNCONNECTED;
wire NLW_U0_Dbg_WVALID_25_UNCONNECTED;
wire NLW_U0_Dbg_WVALID_26_UNCONNECTED;
wire NLW_U0_Dbg_WVALID_27_UNCONNECTED;
wire NLW_U0_Dbg_WVALID_28_UNCONNECTED;
wire NLW_U0_Dbg_WVALID_29_UNCONNECTED;
wire NLW_U0_Dbg_WVALID_3_UNCONNECTED;
wire NLW_U0_Dbg_WVALID_30_UNCONNECTED;
wire NLW_U0_Dbg_WVALID_31_UNCONNECTED;
wire NLW_U0_Dbg_WVALID_4_UNCONNECTED;
wire NLW_U0_Dbg_WVALID_5_UNCONNECTED;
wire NLW_U0_Dbg_WVALID_6_UNCONNECTED;
wire NLW_U0_Dbg_WVALID_7_UNCONNECTED;
wire NLW_U0_Dbg_WVALID_8_UNCONNECTED;
wire NLW_U0_Dbg_WVALID_9_UNCONNECTED;
wire NLW_U0_Ext_BRK_UNCONNECTED;
wire NLW_U0_Ext_JTAG_CAPTURE_UNCONNECTED;
wire NLW_U0_Ext_JTAG_DRCK_UNCONNECTED;
wire NLW_U0_Ext_JTAG_RESET_UNCONNECTED;
wire NLW_U0_Ext_JTAG_SEL_UNCONNECTED;
wire NLW_U0_Ext_JTAG_SHIFT_UNCONNECTED;
wire NLW_U0_Ext_JTAG_TDI_UNCONNECTED;
wire NLW_U0_Ext_JTAG_UPDATE_UNCONNECTED;
wire NLW_U0_Ext_NM_BRK_UNCONNECTED;
wire NLW_U0_Interrupt_UNCONNECTED;
wire NLW_U0_LMB_Addr_Strobe_0_UNCONNECTED;
wire NLW_U0_LMB_Addr_Strobe_1_UNCONNECTED;
wire NLW_U0_LMB_Addr_Strobe_10_UNCONNECTED;
wire NLW_U0_LMB_Addr_Strobe_11_UNCONNECTED;
wire NLW_U0_LMB_Addr_Strobe_12_UNCONNECTED;
wire NLW_U0_LMB_Addr_Strobe_13_UNCONNECTED;
wire NLW_U0_LMB_Addr_Strobe_14_UNCONNECTED;
wire NLW_U0_LMB_Addr_Strobe_15_UNCONNECTED;
wire NLW_U0_LMB_Addr_Strobe_16_UNCONNECTED;
wire NLW_U0_LMB_Addr_Strobe_17_UNCONNECTED;
wire NLW_U0_LMB_Addr_Strobe_18_UNCONNECTED;
wire NLW_U0_LMB_Addr_Strobe_19_UNCONNECTED;
wire NLW_U0_LMB_Addr_Strobe_2_UNCONNECTED;
wire NLW_U0_LMB_Addr_Strobe_20_UNCONNECTED;
wire NLW_U0_LMB_Addr_Strobe_21_UNCONNECTED;
wire NLW_U0_LMB_Addr_Strobe_22_UNCONNECTED;
wire NLW_U0_LMB_Addr_Strobe_23_UNCONNECTED;
wire NLW_U0_LMB_Addr_Strobe_24_UNCONNECTED;
wire NLW_U0_LMB_Addr_Strobe_25_UNCONNECTED;
wire NLW_U0_LMB_Addr_Strobe_26_UNCONNECTED;
wire NLW_U0_LMB_Addr_Strobe_27_UNCONNECTED;
wire NLW_U0_LMB_Addr_Strobe_28_UNCONNECTED;
wire NLW_U0_LMB_Addr_Strobe_29_UNCONNECTED;
wire NLW_U0_LMB_Addr_Strobe_3_UNCONNECTED;
wire NLW_U0_LMB_Addr_Strobe_30_UNCONNECTED;
wire NLW_U0_LMB_Addr_Strobe_31_UNCONNECTED;
wire NLW_U0_LMB_Addr_Strobe_4_UNCONNECTED;
wire NLW_U0_LMB_Addr_Strobe_5_UNCONNECTED;
wire NLW_U0_LMB_Addr_Strobe_6_UNCONNECTED;
wire NLW_U0_LMB_Addr_Strobe_7_UNCONNECTED;
wire NLW_U0_LMB_Addr_Strobe_8_UNCONNECTED;
wire NLW_U0_LMB_Addr_Strobe_9_UNCONNECTED;
wire NLW_U0_LMB_Read_Strobe_0_UNCONNECTED;
wire NLW_U0_LMB_Read_Strobe_1_UNCONNECTED;
wire NLW_U0_LMB_Read_Strobe_10_UNCONNECTED;
wire NLW_U0_LMB_Read_Strobe_11_UNCONNECTED;
wire NLW_U0_LMB_Read_Strobe_12_UNCONNECTED;
wire NLW_U0_LMB_Read_Strobe_13_UNCONNECTED;
wire NLW_U0_LMB_Read_Strobe_14_UNCONNECTED;
wire NLW_U0_LMB_Read_Strobe_15_UNCONNECTED;
wire NLW_U0_LMB_Read_Strobe_16_UNCONNECTED;
wire NLW_U0_LMB_Read_Strobe_17_UNCONNECTED;
wire NLW_U0_LMB_Read_Strobe_18_UNCONNECTED;
wire NLW_U0_LMB_Read_Strobe_19_UNCONNECTED;
wire NLW_U0_LMB_Read_Strobe_2_UNCONNECTED;
wire NLW_U0_LMB_Read_Strobe_20_UNCONNECTED;
wire NLW_U0_LMB_Read_Strobe_21_UNCONNECTED;
wire NLW_U0_LMB_Read_Strobe_22_UNCONNECTED;
wire NLW_U0_LMB_Read_Strobe_23_UNCONNECTED;
wire NLW_U0_LMB_Read_Strobe_24_UNCONNECTED;
wire NLW_U0_LMB_Read_Strobe_25_UNCONNECTED;
wire NLW_U0_LMB_Read_Strobe_26_UNCONNECTED;
wire NLW_U0_LMB_Read_Strobe_27_UNCONNECTED;
wire NLW_U0_LMB_Read_Strobe_28_UNCONNECTED;
wire NLW_U0_LMB_Read_Strobe_29_UNCONNECTED;
wire NLW_U0_LMB_Read_Strobe_3_UNCONNECTED;
wire NLW_U0_LMB_Read_Strobe_30_UNCONNECTED;
wire NLW_U0_LMB_Read_Strobe_31_UNCONNECTED;
wire NLW_U0_LMB_Read_Strobe_4_UNCONNECTED;
wire NLW_U0_LMB_Read_Strobe_5_UNCONNECTED;
wire NLW_U0_LMB_Read_Strobe_6_UNCONNECTED;
wire NLW_U0_LMB_Read_Strobe_7_UNCONNECTED;
wire NLW_U0_LMB_Read_Strobe_8_UNCONNECTED;
wire NLW_U0_LMB_Read_Strobe_9_UNCONNECTED;
wire NLW_U0_LMB_Write_Strobe_0_UNCONNECTED;
wire NLW_U0_LMB_Write_Strobe_1_UNCONNECTED;
wire NLW_U0_LMB_Write_Strobe_10_UNCONNECTED;
wire NLW_U0_LMB_Write_Strobe_11_UNCONNECTED;
wire NLW_U0_LMB_Write_Strobe_12_UNCONNECTED;
wire NLW_U0_LMB_Write_Strobe_13_UNCONNECTED;
wire NLW_U0_LMB_Write_Strobe_14_UNCONNECTED;
wire NLW_U0_LMB_Write_Strobe_15_UNCONNECTED;
wire NLW_U0_LMB_Write_Strobe_16_UNCONNECTED;
wire NLW_U0_LMB_Write_Strobe_17_UNCONNECTED;
wire NLW_U0_LMB_Write_Strobe_18_UNCONNECTED;
wire NLW_U0_LMB_Write_Strobe_19_UNCONNECTED;
wire NLW_U0_LMB_Write_Strobe_2_UNCONNECTED;
wire NLW_U0_LMB_Write_Strobe_20_UNCONNECTED;
wire NLW_U0_LMB_Write_Strobe_21_UNCONNECTED;
wire NLW_U0_LMB_Write_Strobe_22_UNCONNECTED;
wire NLW_U0_LMB_Write_Strobe_23_UNCONNECTED;
wire NLW_U0_LMB_Write_Strobe_24_UNCONNECTED;
wire NLW_U0_LMB_Write_Strobe_25_UNCONNECTED;
wire NLW_U0_LMB_Write_Strobe_26_UNCONNECTED;
wire NLW_U0_LMB_Write_Strobe_27_UNCONNECTED;
wire NLW_U0_LMB_Write_Strobe_28_UNCONNECTED;
wire NLW_U0_LMB_Write_Strobe_29_UNCONNECTED;
wire NLW_U0_LMB_Write_Strobe_3_UNCONNECTED;
wire NLW_U0_LMB_Write_Strobe_30_UNCONNECTED;
wire NLW_U0_LMB_Write_Strobe_31_UNCONNECTED;
wire NLW_U0_LMB_Write_Strobe_4_UNCONNECTED;
wire NLW_U0_LMB_Write_Strobe_5_UNCONNECTED;
wire NLW_U0_LMB_Write_Strobe_6_UNCONNECTED;
wire NLW_U0_LMB_Write_Strobe_7_UNCONNECTED;
wire NLW_U0_LMB_Write_Strobe_8_UNCONNECTED;
wire NLW_U0_LMB_Write_Strobe_9_UNCONNECTED;
wire NLW_U0_M_AXIS_TVALID_UNCONNECTED;
wire NLW_U0_M_AXI_ARLOCK_UNCONNECTED;
wire NLW_U0_M_AXI_ARVALID_UNCONNECTED;
wire NLW_U0_M_AXI_AWLOCK_UNCONNECTED;
wire NLW_U0_M_AXI_AWVALID_UNCONNECTED;
wire NLW_U0_M_AXI_BREADY_UNCONNECTED;
wire NLW_U0_M_AXI_RREADY_UNCONNECTED;
wire NLW_U0_M_AXI_WLAST_UNCONNECTED;
wire NLW_U0_M_AXI_WVALID_UNCONNECTED;
wire NLW_U0_S_AXI_ARREADY_UNCONNECTED;
wire NLW_U0_S_AXI_AWREADY_UNCONNECTED;
wire NLW_U0_S_AXI_BVALID_UNCONNECTED;
wire NLW_U0_S_AXI_RVALID_UNCONNECTED;
wire NLW_U0_S_AXI_WREADY_UNCONNECTED;
wire NLW_U0_TRACE_CLK_OUT_UNCONNECTED;
wire NLW_U0_TRACE_CTL_UNCONNECTED;
wire NLW_U0_Trig_Ack_In_0_UNCONNECTED;
wire NLW_U0_Trig_Ack_In_1_UNCONNECTED;
wire NLW_U0_Trig_Ack_In_2_UNCONNECTED;
wire NLW_U0_Trig_Ack_In_3_UNCONNECTED;
wire NLW_U0_Trig_Out_0_UNCONNECTED;
wire NLW_U0_Trig_Out_1_UNCONNECTED;
wire NLW_U0_Trig_Out_2_UNCONNECTED;
wire NLW_U0_Trig_Out_3_UNCONNECTED;
wire NLW_U0_bscan_ext_tdo_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_ARADDR_0_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_ARADDR_1_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_ARADDR_10_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_ARADDR_11_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_ARADDR_12_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_ARADDR_13_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_ARADDR_14_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_ARADDR_15_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_ARADDR_16_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_ARADDR_17_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_ARADDR_18_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_ARADDR_19_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_ARADDR_2_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_ARADDR_20_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_ARADDR_21_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_ARADDR_22_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_ARADDR_23_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_ARADDR_24_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_ARADDR_25_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_ARADDR_26_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_ARADDR_27_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_ARADDR_28_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_ARADDR_29_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_ARADDR_3_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_ARADDR_30_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_ARADDR_31_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_ARADDR_4_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_ARADDR_5_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_ARADDR_6_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_ARADDR_7_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_ARADDR_8_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_ARADDR_9_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_AWADDR_0_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_AWADDR_1_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_AWADDR_10_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_AWADDR_11_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_AWADDR_12_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_AWADDR_13_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_AWADDR_14_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_AWADDR_15_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_AWADDR_16_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_AWADDR_17_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_AWADDR_18_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_AWADDR_19_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_AWADDR_2_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_AWADDR_20_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_AWADDR_21_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_AWADDR_22_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_AWADDR_23_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_AWADDR_24_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_AWADDR_25_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_AWADDR_26_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_AWADDR_27_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_AWADDR_28_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_AWADDR_29_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_AWADDR_3_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_AWADDR_30_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_AWADDR_31_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_AWADDR_4_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_AWADDR_5_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_AWADDR_6_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_AWADDR_7_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_AWADDR_8_UNCONNECTED;
wire [14:2]NLW_U0_Dbg_AWADDR_9_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Reg_En_1_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Reg_En_10_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Reg_En_11_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Reg_En_12_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Reg_En_13_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Reg_En_14_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Reg_En_15_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Reg_En_16_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Reg_En_17_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Reg_En_18_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Reg_En_19_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Reg_En_2_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Reg_En_20_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Reg_En_21_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Reg_En_22_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Reg_En_23_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Reg_En_24_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Reg_En_25_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Reg_En_26_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Reg_En_27_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Reg_En_28_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Reg_En_29_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Reg_En_3_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Reg_En_30_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Reg_En_31_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Reg_En_4_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Reg_En_5_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Reg_En_6_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Reg_En_7_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Reg_En_8_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Reg_En_9_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Ack_In_0_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Ack_In_1_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Ack_In_10_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Ack_In_11_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Ack_In_12_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Ack_In_13_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Ack_In_14_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Ack_In_15_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Ack_In_16_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Ack_In_17_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Ack_In_18_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Ack_In_19_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Ack_In_2_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Ack_In_20_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Ack_In_21_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Ack_In_22_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Ack_In_23_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Ack_In_24_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Ack_In_25_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Ack_In_26_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Ack_In_27_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Ack_In_28_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Ack_In_29_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Ack_In_3_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Ack_In_30_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Ack_In_31_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Ack_In_4_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Ack_In_5_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Ack_In_6_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Ack_In_7_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Ack_In_8_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Ack_In_9_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Out_0_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Out_1_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Out_10_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Out_11_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Out_12_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Out_13_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Out_14_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Out_15_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Out_16_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Out_17_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Out_18_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Out_19_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Out_2_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Out_20_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Out_21_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Out_22_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Out_23_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Out_24_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Out_25_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Out_26_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Out_27_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Out_28_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Out_29_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Out_3_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Out_30_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Out_31_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Out_4_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Out_5_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Out_6_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Out_7_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Out_8_UNCONNECTED;
wire [0:7]NLW_U0_Dbg_Trig_Out_9_UNCONNECTED;
wire [31:0]NLW_U0_Dbg_WDATA_0_UNCONNECTED;
wire [31:0]NLW_U0_Dbg_WDATA_1_UNCONNECTED;
wire [31:0]NLW_U0_Dbg_WDATA_10_UNCONNECTED;
wire [31:0]NLW_U0_Dbg_WDATA_11_UNCONNECTED;
wire [31:0]NLW_U0_Dbg_WDATA_12_UNCONNECTED;
wire [31:0]NLW_U0_Dbg_WDATA_13_UNCONNECTED;
wire [31:0]NLW_U0_Dbg_WDATA_14_UNCONNECTED;
wire [31:0]NLW_U0_Dbg_WDATA_15_UNCONNECTED;
wire [31:0]NLW_U0_Dbg_WDATA_16_UNCONNECTED;
wire [31:0]NLW_U0_Dbg_WDATA_17_UNCONNECTED;
wire [31:0]NLW_U0_Dbg_WDATA_18_UNCONNECTED;
wire [31:0]NLW_U0_Dbg_WDATA_19_UNCONNECTED;
wire [31:0]NLW_U0_Dbg_WDATA_2_UNCONNECTED;
wire [31:0]NLW_U0_Dbg_WDATA_20_UNCONNECTED;
wire [31:0]NLW_U0_Dbg_WDATA_21_UNCONNECTED;
wire [31:0]NLW_U0_Dbg_WDATA_22_UNCONNECTED;
wire [31:0]NLW_U0_Dbg_WDATA_23_UNCONNECTED;
wire [31:0]NLW_U0_Dbg_WDATA_24_UNCONNECTED;
wire [31:0]NLW_U0_Dbg_WDATA_25_UNCONNECTED;
wire [31:0]NLW_U0_Dbg_WDATA_26_UNCONNECTED;
wire [31:0]NLW_U0_Dbg_WDATA_27_UNCONNECTED;
wire [31:0]NLW_U0_Dbg_WDATA_28_UNCONNECTED;
wire [31:0]NLW_U0_Dbg_WDATA_29_UNCONNECTED;
wire [31:0]NLW_U0_Dbg_WDATA_3_UNCONNECTED;
wire [31:0]NLW_U0_Dbg_WDATA_30_UNCONNECTED;
wire [31:0]NLW_U0_Dbg_WDATA_31_UNCONNECTED;
wire [31:0]NLW_U0_Dbg_WDATA_4_UNCONNECTED;
wire [31:0]NLW_U0_Dbg_WDATA_5_UNCONNECTED;
wire [31:0]NLW_U0_Dbg_WDATA_6_UNCONNECTED;
wire [31:0]NLW_U0_Dbg_WDATA_7_UNCONNECTED;
wire [31:0]NLW_U0_Dbg_WDATA_8_UNCONNECTED;
wire [31:0]NLW_U0_Dbg_WDATA_9_UNCONNECTED;
wire [0:3]NLW_U0_LMB_Byte_Enable_0_UNCONNECTED;
wire [0:3]NLW_U0_LMB_Byte_Enable_1_UNCONNECTED;
wire [0:3]NLW_U0_LMB_Byte_Enable_10_UNCONNECTED;
wire [0:3]NLW_U0_LMB_Byte_Enable_11_UNCONNECTED;
wire [0:3]NLW_U0_LMB_Byte_Enable_12_UNCONNECTED;
wire [0:3]NLW_U0_LMB_Byte_Enable_13_UNCONNECTED;
wire [0:3]NLW_U0_LMB_Byte_Enable_14_UNCONNECTED;
wire [0:3]NLW_U0_LMB_Byte_Enable_15_UNCONNECTED;
wire [0:3]NLW_U0_LMB_Byte_Enable_16_UNCONNECTED;
wire [0:3]NLW_U0_LMB_Byte_Enable_17_UNCONNECTED;
wire [0:3]NLW_U0_LMB_Byte_Enable_18_UNCONNECTED;
wire [0:3]NLW_U0_LMB_Byte_Enable_19_UNCONNECTED;
wire [0:3]NLW_U0_LMB_Byte_Enable_2_UNCONNECTED;
wire [0:3]NLW_U0_LMB_Byte_Enable_20_UNCONNECTED;
wire [0:3]NLW_U0_LMB_Byte_Enable_21_UNCONNECTED;
wire [0:3]NLW_U0_LMB_Byte_Enable_22_UNCONNECTED;
wire [0:3]NLW_U0_LMB_Byte_Enable_23_UNCONNECTED;
wire [0:3]NLW_U0_LMB_Byte_Enable_24_UNCONNECTED;
wire [0:3]NLW_U0_LMB_Byte_Enable_25_UNCONNECTED;
wire [0:3]NLW_U0_LMB_Byte_Enable_26_UNCONNECTED;
wire [0:3]NLW_U0_LMB_Byte_Enable_27_UNCONNECTED;
wire [0:3]NLW_U0_LMB_Byte_Enable_28_UNCONNECTED;
wire [0:3]NLW_U0_LMB_Byte_Enable_29_UNCONNECTED;
wire [0:3]NLW_U0_LMB_Byte_Enable_3_UNCONNECTED;
wire [0:3]NLW_U0_LMB_Byte_Enable_30_UNCONNECTED;
wire [0:3]NLW_U0_LMB_Byte_Enable_31_UNCONNECTED;
wire [0:3]NLW_U0_LMB_Byte_Enable_4_UNCONNECTED;
wire [0:3]NLW_U0_LMB_Byte_Enable_5_UNCONNECTED;
wire [0:3]NLW_U0_LMB_Byte_Enable_6_UNCONNECTED;
wire [0:3]NLW_U0_LMB_Byte_Enable_7_UNCONNECTED;
wire [0:3]NLW_U0_LMB_Byte_Enable_8_UNCONNECTED;
wire [0:3]NLW_U0_LMB_Byte_Enable_9_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Addr_0_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Addr_1_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Addr_10_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Addr_11_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Addr_12_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Addr_13_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Addr_14_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Addr_15_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Addr_16_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Addr_17_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Addr_18_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Addr_19_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Addr_2_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Addr_20_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Addr_21_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Addr_22_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Addr_23_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Addr_24_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Addr_25_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Addr_26_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Addr_27_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Addr_28_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Addr_29_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Addr_3_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Addr_30_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Addr_31_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Addr_4_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Addr_5_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Addr_6_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Addr_7_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Addr_8_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Addr_9_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Write_0_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Write_1_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Write_10_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Write_11_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Write_12_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Write_13_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Write_14_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Write_15_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Write_16_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Write_17_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Write_18_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Write_19_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Write_2_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Write_20_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Write_21_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Write_22_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Write_23_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Write_24_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Write_25_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Write_26_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Write_27_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Write_28_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Write_29_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Write_3_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Write_30_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Write_31_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Write_4_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Write_5_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Write_6_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Write_7_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Write_8_UNCONNECTED;
wire [0:31]NLW_U0_LMB_Data_Write_9_UNCONNECTED;
wire [31:0]NLW_U0_M_AXIS_TDATA_UNCONNECTED;
wire [6:0]NLW_U0_M_AXIS_TID_UNCONNECTED;
wire [31:0]NLW_U0_M_AXI_ARADDR_UNCONNECTED;
wire [1:0]NLW_U0_M_AXI_ARBURST_UNCONNECTED;
wire [3:0]NLW_U0_M_AXI_ARCACHE_UNCONNECTED;
wire [0:0]NLW_U0_M_AXI_ARID_UNCONNECTED;
wire [7:0]NLW_U0_M_AXI_ARLEN_UNCONNECTED;
wire [2:0]NLW_U0_M_AXI_ARPROT_UNCONNECTED;
wire [3:0]NLW_U0_M_AXI_ARQOS_UNCONNECTED;
wire [2:0]NLW_U0_M_AXI_ARSIZE_UNCONNECTED;
wire [31:0]NLW_U0_M_AXI_AWADDR_UNCONNECTED;
wire [1:0]NLW_U0_M_AXI_AWBURST_UNCONNECTED;
wire [3:0]NLW_U0_M_AXI_AWCACHE_UNCONNECTED;
wire [0:0]NLW_U0_M_AXI_AWID_UNCONNECTED;
wire [7:0]NLW_U0_M_AXI_AWLEN_UNCONNECTED;
wire [2:0]NLW_U0_M_AXI_AWPROT_UNCONNECTED;
wire [3:0]NLW_U0_M_AXI_AWQOS_UNCONNECTED;
wire [2:0]NLW_U0_M_AXI_AWSIZE_UNCONNECTED;
wire [31:0]NLW_U0_M_AXI_WDATA_UNCONNECTED;
wire [3:0]NLW_U0_M_AXI_WSTRB_UNCONNECTED;
wire [1:0]NLW_U0_S_AXI_BRESP_UNCONNECTED;
wire [31:0]NLW_U0_S_AXI_RDATA_UNCONNECTED;
wire [1:0]NLW_U0_S_AXI_RRESP_UNCONNECTED;
wire [31:0]NLW_U0_TRACE_DATA_UNCONNECTED;
(* C_DATA_SIZE = "32" *)
(* C_DBG_MEM_ACCESS = "0" *)
(* C_DBG_REG_ACCESS = "0" *)
(* C_DEBUG_INTERFACE = "0" *)
(* C_FAMILY = "artix7" *)
(* C_INTERCONNECT = "2" *)
(* C_JTAG_CHAIN = "2" *)
(* C_MB_DBG_PORTS = "1" *)
(* C_M_AXIS_DATA_WIDTH = "32" *)
(* C_M_AXIS_ID_WIDTH = "7" *)
(* C_M_AXI_ADDR_WIDTH = "32" *)
(* C_M_AXI_DATA_WIDTH = "32" *)
(* C_M_AXI_THREAD_ID_WIDTH = "1" *)
(* C_S_AXI_ACLK_FREQ_HZ = "100000000" *)
(* C_S_AXI_ADDR_WIDTH = "4" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_TRACE_CLK_FREQ_HZ = "200000000" *)
(* C_TRACE_CLK_OUT_PHASE = "90" *)
(* C_TRACE_DATA_WIDTH = "32" *)
(* C_TRACE_OUTPUT = "0" *)
(* C_USE_BSCAN = "0" *)
(* C_USE_CONFIG_RESET = "0" *)
(* C_USE_CROSS_TRIGGER = "0" *)
(* C_USE_UART = "0" *)
system_mdm_1_0_MDM U0
(.Config_Reset(1'b0),
.Dbg_ARADDR_0(NLW_U0_Dbg_ARADDR_0_UNCONNECTED[14:2]),
.Dbg_ARADDR_1(NLW_U0_Dbg_ARADDR_1_UNCONNECTED[14:2]),
.Dbg_ARADDR_10(NLW_U0_Dbg_ARADDR_10_UNCONNECTED[14:2]),
.Dbg_ARADDR_11(NLW_U0_Dbg_ARADDR_11_UNCONNECTED[14:2]),
.Dbg_ARADDR_12(NLW_U0_Dbg_ARADDR_12_UNCONNECTED[14:2]),
.Dbg_ARADDR_13(NLW_U0_Dbg_ARADDR_13_UNCONNECTED[14:2]),
.Dbg_ARADDR_14(NLW_U0_Dbg_ARADDR_14_UNCONNECTED[14:2]),
.Dbg_ARADDR_15(NLW_U0_Dbg_ARADDR_15_UNCONNECTED[14:2]),
.Dbg_ARADDR_16(NLW_U0_Dbg_ARADDR_16_UNCONNECTED[14:2]),
.Dbg_ARADDR_17(NLW_U0_Dbg_ARADDR_17_UNCONNECTED[14:2]),
.Dbg_ARADDR_18(NLW_U0_Dbg_ARADDR_18_UNCONNECTED[14:2]),
.Dbg_ARADDR_19(NLW_U0_Dbg_ARADDR_19_UNCONNECTED[14:2]),
.Dbg_ARADDR_2(NLW_U0_Dbg_ARADDR_2_UNCONNECTED[14:2]),
.Dbg_ARADDR_20(NLW_U0_Dbg_ARADDR_20_UNCONNECTED[14:2]),
.Dbg_ARADDR_21(NLW_U0_Dbg_ARADDR_21_UNCONNECTED[14:2]),
.Dbg_ARADDR_22(NLW_U0_Dbg_ARADDR_22_UNCONNECTED[14:2]),
.Dbg_ARADDR_23(NLW_U0_Dbg_ARADDR_23_UNCONNECTED[14:2]),
.Dbg_ARADDR_24(NLW_U0_Dbg_ARADDR_24_UNCONNECTED[14:2]),
.Dbg_ARADDR_25(NLW_U0_Dbg_ARADDR_25_UNCONNECTED[14:2]),
.Dbg_ARADDR_26(NLW_U0_Dbg_ARADDR_26_UNCONNECTED[14:2]),
.Dbg_ARADDR_27(NLW_U0_Dbg_ARADDR_27_UNCONNECTED[14:2]),
.Dbg_ARADDR_28(NLW_U0_Dbg_ARADDR_28_UNCONNECTED[14:2]),
.Dbg_ARADDR_29(NLW_U0_Dbg_ARADDR_29_UNCONNECTED[14:2]),
.Dbg_ARADDR_3(NLW_U0_Dbg_ARADDR_3_UNCONNECTED[14:2]),
.Dbg_ARADDR_30(NLW_U0_Dbg_ARADDR_30_UNCONNECTED[14:2]),
.Dbg_ARADDR_31(NLW_U0_Dbg_ARADDR_31_UNCONNECTED[14:2]),
.Dbg_ARADDR_4(NLW_U0_Dbg_ARADDR_4_UNCONNECTED[14:2]),
.Dbg_ARADDR_5(NLW_U0_Dbg_ARADDR_5_UNCONNECTED[14:2]),
.Dbg_ARADDR_6(NLW_U0_Dbg_ARADDR_6_UNCONNECTED[14:2]),
.Dbg_ARADDR_7(NLW_U0_Dbg_ARADDR_7_UNCONNECTED[14:2]),
.Dbg_ARADDR_8(NLW_U0_Dbg_ARADDR_8_UNCONNECTED[14:2]),
.Dbg_ARADDR_9(NLW_U0_Dbg_ARADDR_9_UNCONNECTED[14:2]),
.Dbg_ARREADY_0(1'b0),
.Dbg_ARREADY_1(1'b0),
.Dbg_ARREADY_10(1'b0),
.Dbg_ARREADY_11(1'b0),
.Dbg_ARREADY_12(1'b0),
.Dbg_ARREADY_13(1'b0),
.Dbg_ARREADY_14(1'b0),
.Dbg_ARREADY_15(1'b0),
.Dbg_ARREADY_16(1'b0),
.Dbg_ARREADY_17(1'b0),
.Dbg_ARREADY_18(1'b0),
.Dbg_ARREADY_19(1'b0),
.Dbg_ARREADY_2(1'b0),
.Dbg_ARREADY_20(1'b0),
.Dbg_ARREADY_21(1'b0),
.Dbg_ARREADY_22(1'b0),
.Dbg_ARREADY_23(1'b0),
.Dbg_ARREADY_24(1'b0),
.Dbg_ARREADY_25(1'b0),
.Dbg_ARREADY_26(1'b0),
.Dbg_ARREADY_27(1'b0),
.Dbg_ARREADY_28(1'b0),
.Dbg_ARREADY_29(1'b0),
.Dbg_ARREADY_3(1'b0),
.Dbg_ARREADY_30(1'b0),
.Dbg_ARREADY_31(1'b0),
.Dbg_ARREADY_4(1'b0),
.Dbg_ARREADY_5(1'b0),
.Dbg_ARREADY_6(1'b0),
.Dbg_ARREADY_7(1'b0),
.Dbg_ARREADY_8(1'b0),
.Dbg_ARREADY_9(1'b0),
.Dbg_ARVALID_0(NLW_U0_Dbg_ARVALID_0_UNCONNECTED),
.Dbg_ARVALID_1(NLW_U0_Dbg_ARVALID_1_UNCONNECTED),
.Dbg_ARVALID_10(NLW_U0_Dbg_ARVALID_10_UNCONNECTED),
.Dbg_ARVALID_11(NLW_U0_Dbg_ARVALID_11_UNCONNECTED),
.Dbg_ARVALID_12(NLW_U0_Dbg_ARVALID_12_UNCONNECTED),
.Dbg_ARVALID_13(NLW_U0_Dbg_ARVALID_13_UNCONNECTED),
.Dbg_ARVALID_14(NLW_U0_Dbg_ARVALID_14_UNCONNECTED),
.Dbg_ARVALID_15(NLW_U0_Dbg_ARVALID_15_UNCONNECTED),
.Dbg_ARVALID_16(NLW_U0_Dbg_ARVALID_16_UNCONNECTED),
.Dbg_ARVALID_17(NLW_U0_Dbg_ARVALID_17_UNCONNECTED),
.Dbg_ARVALID_18(NLW_U0_Dbg_ARVALID_18_UNCONNECTED),
.Dbg_ARVALID_19(NLW_U0_Dbg_ARVALID_19_UNCONNECTED),
.Dbg_ARVALID_2(NLW_U0_Dbg_ARVALID_2_UNCONNECTED),
.Dbg_ARVALID_20(NLW_U0_Dbg_ARVALID_20_UNCONNECTED),
.Dbg_ARVALID_21(NLW_U0_Dbg_ARVALID_21_UNCONNECTED),
.Dbg_ARVALID_22(NLW_U0_Dbg_ARVALID_22_UNCONNECTED),
.Dbg_ARVALID_23(NLW_U0_Dbg_ARVALID_23_UNCONNECTED),
.Dbg_ARVALID_24(NLW_U0_Dbg_ARVALID_24_UNCONNECTED),
.Dbg_ARVALID_25(NLW_U0_Dbg_ARVALID_25_UNCONNECTED),
.Dbg_ARVALID_26(NLW_U0_Dbg_ARVALID_26_UNCONNECTED),
.Dbg_ARVALID_27(NLW_U0_Dbg_ARVALID_27_UNCONNECTED),
.Dbg_ARVALID_28(NLW_U0_Dbg_ARVALID_28_UNCONNECTED),
.Dbg_ARVALID_29(NLW_U0_Dbg_ARVALID_29_UNCONNECTED),
.Dbg_ARVALID_3(NLW_U0_Dbg_ARVALID_3_UNCONNECTED),
.Dbg_ARVALID_30(NLW_U0_Dbg_ARVALID_30_UNCONNECTED),
.Dbg_ARVALID_31(NLW_U0_Dbg_ARVALID_31_UNCONNECTED),
.Dbg_ARVALID_4(NLW_U0_Dbg_ARVALID_4_UNCONNECTED),
.Dbg_ARVALID_5(NLW_U0_Dbg_ARVALID_5_UNCONNECTED),
.Dbg_ARVALID_6(NLW_U0_Dbg_ARVALID_6_UNCONNECTED),
.Dbg_ARVALID_7(NLW_U0_Dbg_ARVALID_7_UNCONNECTED),
.Dbg_ARVALID_8(NLW_U0_Dbg_ARVALID_8_UNCONNECTED),
.Dbg_ARVALID_9(NLW_U0_Dbg_ARVALID_9_UNCONNECTED),
.Dbg_AWADDR_0(NLW_U0_Dbg_AWADDR_0_UNCONNECTED[14:2]),
.Dbg_AWADDR_1(NLW_U0_Dbg_AWADDR_1_UNCONNECTED[14:2]),
.Dbg_AWADDR_10(NLW_U0_Dbg_AWADDR_10_UNCONNECTED[14:2]),
.Dbg_AWADDR_11(NLW_U0_Dbg_AWADDR_11_UNCONNECTED[14:2]),
.Dbg_AWADDR_12(NLW_U0_Dbg_AWADDR_12_UNCONNECTED[14:2]),
.Dbg_AWADDR_13(NLW_U0_Dbg_AWADDR_13_UNCONNECTED[14:2]),
.Dbg_AWADDR_14(NLW_U0_Dbg_AWADDR_14_UNCONNECTED[14:2]),
.Dbg_AWADDR_15(NLW_U0_Dbg_AWADDR_15_UNCONNECTED[14:2]),
.Dbg_AWADDR_16(NLW_U0_Dbg_AWADDR_16_UNCONNECTED[14:2]),
.Dbg_AWADDR_17(NLW_U0_Dbg_AWADDR_17_UNCONNECTED[14:2]),
.Dbg_AWADDR_18(NLW_U0_Dbg_AWADDR_18_UNCONNECTED[14:2]),
.Dbg_AWADDR_19(NLW_U0_Dbg_AWADDR_19_UNCONNECTED[14:2]),
.Dbg_AWADDR_2(NLW_U0_Dbg_AWADDR_2_UNCONNECTED[14:2]),
.Dbg_AWADDR_20(NLW_U0_Dbg_AWADDR_20_UNCONNECTED[14:2]),
.Dbg_AWADDR_21(NLW_U0_Dbg_AWADDR_21_UNCONNECTED[14:2]),
.Dbg_AWADDR_22(NLW_U0_Dbg_AWADDR_22_UNCONNECTED[14:2]),
.Dbg_AWADDR_23(NLW_U0_Dbg_AWADDR_23_UNCONNECTED[14:2]),
.Dbg_AWADDR_24(NLW_U0_Dbg_AWADDR_24_UNCONNECTED[14:2]),
.Dbg_AWADDR_25(NLW_U0_Dbg_AWADDR_25_UNCONNECTED[14:2]),
.Dbg_AWADDR_26(NLW_U0_Dbg_AWADDR_26_UNCONNECTED[14:2]),
.Dbg_AWADDR_27(NLW_U0_Dbg_AWADDR_27_UNCONNECTED[14:2]),
.Dbg_AWADDR_28(NLW_U0_Dbg_AWADDR_28_UNCONNECTED[14:2]),
.Dbg_AWADDR_29(NLW_U0_Dbg_AWADDR_29_UNCONNECTED[14:2]),
.Dbg_AWADDR_3(NLW_U0_Dbg_AWADDR_3_UNCONNECTED[14:2]),
.Dbg_AWADDR_30(NLW_U0_Dbg_AWADDR_30_UNCONNECTED[14:2]),
.Dbg_AWADDR_31(NLW_U0_Dbg_AWADDR_31_UNCONNECTED[14:2]),
.Dbg_AWADDR_4(NLW_U0_Dbg_AWADDR_4_UNCONNECTED[14:2]),
.Dbg_AWADDR_5(NLW_U0_Dbg_AWADDR_5_UNCONNECTED[14:2]),
.Dbg_AWADDR_6(NLW_U0_Dbg_AWADDR_6_UNCONNECTED[14:2]),
.Dbg_AWADDR_7(NLW_U0_Dbg_AWADDR_7_UNCONNECTED[14:2]),
.Dbg_AWADDR_8(NLW_U0_Dbg_AWADDR_8_UNCONNECTED[14:2]),
.Dbg_AWADDR_9(NLW_U0_Dbg_AWADDR_9_UNCONNECTED[14:2]),
.Dbg_AWREADY_0(1'b0),
.Dbg_AWREADY_1(1'b0),
.Dbg_AWREADY_10(1'b0),
.Dbg_AWREADY_11(1'b0),
.Dbg_AWREADY_12(1'b0),
.Dbg_AWREADY_13(1'b0),
.Dbg_AWREADY_14(1'b0),
.Dbg_AWREADY_15(1'b0),
.Dbg_AWREADY_16(1'b0),
.Dbg_AWREADY_17(1'b0),
.Dbg_AWREADY_18(1'b0),
.Dbg_AWREADY_19(1'b0),
.Dbg_AWREADY_2(1'b0),
.Dbg_AWREADY_20(1'b0),
.Dbg_AWREADY_21(1'b0),
.Dbg_AWREADY_22(1'b0),
.Dbg_AWREADY_23(1'b0),
.Dbg_AWREADY_24(1'b0),
.Dbg_AWREADY_25(1'b0),
.Dbg_AWREADY_26(1'b0),
.Dbg_AWREADY_27(1'b0),
.Dbg_AWREADY_28(1'b0),
.Dbg_AWREADY_29(1'b0),
.Dbg_AWREADY_3(1'b0),
.Dbg_AWREADY_30(1'b0),
.Dbg_AWREADY_31(1'b0),
.Dbg_AWREADY_4(1'b0),
.Dbg_AWREADY_5(1'b0),
.Dbg_AWREADY_6(1'b0),
.Dbg_AWREADY_7(1'b0),
.Dbg_AWREADY_8(1'b0),
.Dbg_AWREADY_9(1'b0),
.Dbg_AWVALID_0(NLW_U0_Dbg_AWVALID_0_UNCONNECTED),
.Dbg_AWVALID_1(NLW_U0_Dbg_AWVALID_1_UNCONNECTED),
.Dbg_AWVALID_10(NLW_U0_Dbg_AWVALID_10_UNCONNECTED),
.Dbg_AWVALID_11(NLW_U0_Dbg_AWVALID_11_UNCONNECTED),
.Dbg_AWVALID_12(NLW_U0_Dbg_AWVALID_12_UNCONNECTED),
.Dbg_AWVALID_13(NLW_U0_Dbg_AWVALID_13_UNCONNECTED),
.Dbg_AWVALID_14(NLW_U0_Dbg_AWVALID_14_UNCONNECTED),
.Dbg_AWVALID_15(NLW_U0_Dbg_AWVALID_15_UNCONNECTED),
.Dbg_AWVALID_16(NLW_U0_Dbg_AWVALID_16_UNCONNECTED),
.Dbg_AWVALID_17(NLW_U0_Dbg_AWVALID_17_UNCONNECTED),
.Dbg_AWVALID_18(NLW_U0_Dbg_AWVALID_18_UNCONNECTED),
.Dbg_AWVALID_19(NLW_U0_Dbg_AWVALID_19_UNCONNECTED),
.Dbg_AWVALID_2(NLW_U0_Dbg_AWVALID_2_UNCONNECTED),
.Dbg_AWVALID_20(NLW_U0_Dbg_AWVALID_20_UNCONNECTED),
.Dbg_AWVALID_21(NLW_U0_Dbg_AWVALID_21_UNCONNECTED),
.Dbg_AWVALID_22(NLW_U0_Dbg_AWVALID_22_UNCONNECTED),
.Dbg_AWVALID_23(NLW_U0_Dbg_AWVALID_23_UNCONNECTED),
.Dbg_AWVALID_24(NLW_U0_Dbg_AWVALID_24_UNCONNECTED),
.Dbg_AWVALID_25(NLW_U0_Dbg_AWVALID_25_UNCONNECTED),
.Dbg_AWVALID_26(NLW_U0_Dbg_AWVALID_26_UNCONNECTED),
.Dbg_AWVALID_27(NLW_U0_Dbg_AWVALID_27_UNCONNECTED),
.Dbg_AWVALID_28(NLW_U0_Dbg_AWVALID_28_UNCONNECTED),
.Dbg_AWVALID_29(NLW_U0_Dbg_AWVALID_29_UNCONNECTED),
.Dbg_AWVALID_3(NLW_U0_Dbg_AWVALID_3_UNCONNECTED),
.Dbg_AWVALID_30(NLW_U0_Dbg_AWVALID_30_UNCONNECTED),
.Dbg_AWVALID_31(NLW_U0_Dbg_AWVALID_31_UNCONNECTED),
.Dbg_AWVALID_4(NLW_U0_Dbg_AWVALID_4_UNCONNECTED),
.Dbg_AWVALID_5(NLW_U0_Dbg_AWVALID_5_UNCONNECTED),
.Dbg_AWVALID_6(NLW_U0_Dbg_AWVALID_6_UNCONNECTED),
.Dbg_AWVALID_7(NLW_U0_Dbg_AWVALID_7_UNCONNECTED),
.Dbg_AWVALID_8(NLW_U0_Dbg_AWVALID_8_UNCONNECTED),
.Dbg_AWVALID_9(NLW_U0_Dbg_AWVALID_9_UNCONNECTED),
.Dbg_BREADY_0(NLW_U0_Dbg_BREADY_0_UNCONNECTED),
.Dbg_BREADY_1(NLW_U0_Dbg_BREADY_1_UNCONNECTED),
.Dbg_BREADY_10(NLW_U0_Dbg_BREADY_10_UNCONNECTED),
.Dbg_BREADY_11(NLW_U0_Dbg_BREADY_11_UNCONNECTED),
.Dbg_BREADY_12(NLW_U0_Dbg_BREADY_12_UNCONNECTED),
.Dbg_BREADY_13(NLW_U0_Dbg_BREADY_13_UNCONNECTED),
.Dbg_BREADY_14(NLW_U0_Dbg_BREADY_14_UNCONNECTED),
.Dbg_BREADY_15(NLW_U0_Dbg_BREADY_15_UNCONNECTED),
.Dbg_BREADY_16(NLW_U0_Dbg_BREADY_16_UNCONNECTED),
.Dbg_BREADY_17(NLW_U0_Dbg_BREADY_17_UNCONNECTED),
.Dbg_BREADY_18(NLW_U0_Dbg_BREADY_18_UNCONNECTED),
.Dbg_BREADY_19(NLW_U0_Dbg_BREADY_19_UNCONNECTED),
.Dbg_BREADY_2(NLW_U0_Dbg_BREADY_2_UNCONNECTED),
.Dbg_BREADY_20(NLW_U0_Dbg_BREADY_20_UNCONNECTED),
.Dbg_BREADY_21(NLW_U0_Dbg_BREADY_21_UNCONNECTED),
.Dbg_BREADY_22(NLW_U0_Dbg_BREADY_22_UNCONNECTED),
.Dbg_BREADY_23(NLW_U0_Dbg_BREADY_23_UNCONNECTED),
.Dbg_BREADY_24(NLW_U0_Dbg_BREADY_24_UNCONNECTED),
.Dbg_BREADY_25(NLW_U0_Dbg_BREADY_25_UNCONNECTED),
.Dbg_BREADY_26(NLW_U0_Dbg_BREADY_26_UNCONNECTED),
.Dbg_BREADY_27(NLW_U0_Dbg_BREADY_27_UNCONNECTED),
.Dbg_BREADY_28(NLW_U0_Dbg_BREADY_28_UNCONNECTED),
.Dbg_BREADY_29(NLW_U0_Dbg_BREADY_29_UNCONNECTED),
.Dbg_BREADY_3(NLW_U0_Dbg_BREADY_3_UNCONNECTED),
.Dbg_BREADY_30(NLW_U0_Dbg_BREADY_30_UNCONNECTED),
.Dbg_BREADY_31(NLW_U0_Dbg_BREADY_31_UNCONNECTED),
.Dbg_BREADY_4(NLW_U0_Dbg_BREADY_4_UNCONNECTED),
.Dbg_BREADY_5(NLW_U0_Dbg_BREADY_5_UNCONNECTED),
.Dbg_BREADY_6(NLW_U0_Dbg_BREADY_6_UNCONNECTED),
.Dbg_BREADY_7(NLW_U0_Dbg_BREADY_7_UNCONNECTED),
.Dbg_BREADY_8(NLW_U0_Dbg_BREADY_8_UNCONNECTED),
.Dbg_BREADY_9(NLW_U0_Dbg_BREADY_9_UNCONNECTED),
.Dbg_BRESP_0({1'b0,1'b0}),
.Dbg_BRESP_1({1'b0,1'b0}),
.Dbg_BRESP_10({1'b0,1'b0}),
.Dbg_BRESP_11({1'b0,1'b0}),
.Dbg_BRESP_12({1'b0,1'b0}),
.Dbg_BRESP_13({1'b0,1'b0}),
.Dbg_BRESP_14({1'b0,1'b0}),
.Dbg_BRESP_15({1'b0,1'b0}),
.Dbg_BRESP_16({1'b0,1'b0}),
.Dbg_BRESP_17({1'b0,1'b0}),
.Dbg_BRESP_18({1'b0,1'b0}),
.Dbg_BRESP_19({1'b0,1'b0}),
.Dbg_BRESP_2({1'b0,1'b0}),
.Dbg_BRESP_20({1'b0,1'b0}),
.Dbg_BRESP_21({1'b0,1'b0}),
.Dbg_BRESP_22({1'b0,1'b0}),
.Dbg_BRESP_23({1'b0,1'b0}),
.Dbg_BRESP_24({1'b0,1'b0}),
.Dbg_BRESP_25({1'b0,1'b0}),
.Dbg_BRESP_26({1'b0,1'b0}),
.Dbg_BRESP_27({1'b0,1'b0}),
.Dbg_BRESP_28({1'b0,1'b0}),
.Dbg_BRESP_29({1'b0,1'b0}),
.Dbg_BRESP_3({1'b0,1'b0}),
.Dbg_BRESP_30({1'b0,1'b0}),
.Dbg_BRESP_31({1'b0,1'b0}),
.Dbg_BRESP_4({1'b0,1'b0}),
.Dbg_BRESP_5({1'b0,1'b0}),
.Dbg_BRESP_6({1'b0,1'b0}),
.Dbg_BRESP_7({1'b0,1'b0}),
.Dbg_BRESP_8({1'b0,1'b0}),
.Dbg_BRESP_9({1'b0,1'b0}),
.Dbg_BVALID_0(1'b0),
.Dbg_BVALID_1(1'b0),
.Dbg_BVALID_10(1'b0),
.Dbg_BVALID_11(1'b0),
.Dbg_BVALID_12(1'b0),
.Dbg_BVALID_13(1'b0),
.Dbg_BVALID_14(1'b0),
.Dbg_BVALID_15(1'b0),
.Dbg_BVALID_16(1'b0),
.Dbg_BVALID_17(1'b0),
.Dbg_BVALID_18(1'b0),
.Dbg_BVALID_19(1'b0),
.Dbg_BVALID_2(1'b0),
.Dbg_BVALID_20(1'b0),
.Dbg_BVALID_21(1'b0),
.Dbg_BVALID_22(1'b0),
.Dbg_BVALID_23(1'b0),
.Dbg_BVALID_24(1'b0),
.Dbg_BVALID_25(1'b0),
.Dbg_BVALID_26(1'b0),
.Dbg_BVALID_27(1'b0),
.Dbg_BVALID_28(1'b0),
.Dbg_BVALID_29(1'b0),
.Dbg_BVALID_3(1'b0),
.Dbg_BVALID_30(1'b0),
.Dbg_BVALID_31(1'b0),
.Dbg_BVALID_4(1'b0),
.Dbg_BVALID_5(1'b0),
.Dbg_BVALID_6(1'b0),
.Dbg_BVALID_7(1'b0),
.Dbg_BVALID_8(1'b0),
.Dbg_BVALID_9(1'b0),
.Dbg_Capture_0(Dbg_Capture_0),
.Dbg_Capture_1(NLW_U0_Dbg_Capture_1_UNCONNECTED),
.Dbg_Capture_10(NLW_U0_Dbg_Capture_10_UNCONNECTED),
.Dbg_Capture_11(NLW_U0_Dbg_Capture_11_UNCONNECTED),
.Dbg_Capture_12(NLW_U0_Dbg_Capture_12_UNCONNECTED),
.Dbg_Capture_13(NLW_U0_Dbg_Capture_13_UNCONNECTED),
.Dbg_Capture_14(NLW_U0_Dbg_Capture_14_UNCONNECTED),
.Dbg_Capture_15(NLW_U0_Dbg_Capture_15_UNCONNECTED),
.Dbg_Capture_16(NLW_U0_Dbg_Capture_16_UNCONNECTED),
.Dbg_Capture_17(NLW_U0_Dbg_Capture_17_UNCONNECTED),
.Dbg_Capture_18(NLW_U0_Dbg_Capture_18_UNCONNECTED),
.Dbg_Capture_19(NLW_U0_Dbg_Capture_19_UNCONNECTED),
.Dbg_Capture_2(NLW_U0_Dbg_Capture_2_UNCONNECTED),
.Dbg_Capture_20(NLW_U0_Dbg_Capture_20_UNCONNECTED),
.Dbg_Capture_21(NLW_U0_Dbg_Capture_21_UNCONNECTED),
.Dbg_Capture_22(NLW_U0_Dbg_Capture_22_UNCONNECTED),
.Dbg_Capture_23(NLW_U0_Dbg_Capture_23_UNCONNECTED),
.Dbg_Capture_24(NLW_U0_Dbg_Capture_24_UNCONNECTED),
.Dbg_Capture_25(NLW_U0_Dbg_Capture_25_UNCONNECTED),
.Dbg_Capture_26(NLW_U0_Dbg_Capture_26_UNCONNECTED),
.Dbg_Capture_27(NLW_U0_Dbg_Capture_27_UNCONNECTED),
.Dbg_Capture_28(NLW_U0_Dbg_Capture_28_UNCONNECTED),
.Dbg_Capture_29(NLW_U0_Dbg_Capture_29_UNCONNECTED),
.Dbg_Capture_3(NLW_U0_Dbg_Capture_3_UNCONNECTED),
.Dbg_Capture_30(NLW_U0_Dbg_Capture_30_UNCONNECTED),
.Dbg_Capture_31(NLW_U0_Dbg_Capture_31_UNCONNECTED),
.Dbg_Capture_4(NLW_U0_Dbg_Capture_4_UNCONNECTED),
.Dbg_Capture_5(NLW_U0_Dbg_Capture_5_UNCONNECTED),
.Dbg_Capture_6(NLW_U0_Dbg_Capture_6_UNCONNECTED),
.Dbg_Capture_7(NLW_U0_Dbg_Capture_7_UNCONNECTED),
.Dbg_Capture_8(NLW_U0_Dbg_Capture_8_UNCONNECTED),
.Dbg_Capture_9(NLW_U0_Dbg_Capture_9_UNCONNECTED),
.Dbg_Clk_0(Dbg_Clk_0),
.Dbg_Clk_1(NLW_U0_Dbg_Clk_1_UNCONNECTED),
.Dbg_Clk_10(NLW_U0_Dbg_Clk_10_UNCONNECTED),
.Dbg_Clk_11(NLW_U0_Dbg_Clk_11_UNCONNECTED),
.Dbg_Clk_12(NLW_U0_Dbg_Clk_12_UNCONNECTED),
.Dbg_Clk_13(NLW_U0_Dbg_Clk_13_UNCONNECTED),
.Dbg_Clk_14(NLW_U0_Dbg_Clk_14_UNCONNECTED),
.Dbg_Clk_15(NLW_U0_Dbg_Clk_15_UNCONNECTED),
.Dbg_Clk_16(NLW_U0_Dbg_Clk_16_UNCONNECTED),
.Dbg_Clk_17(NLW_U0_Dbg_Clk_17_UNCONNECTED),
.Dbg_Clk_18(NLW_U0_Dbg_Clk_18_UNCONNECTED),
.Dbg_Clk_19(NLW_U0_Dbg_Clk_19_UNCONNECTED),
.Dbg_Clk_2(NLW_U0_Dbg_Clk_2_UNCONNECTED),
.Dbg_Clk_20(NLW_U0_Dbg_Clk_20_UNCONNECTED),
.Dbg_Clk_21(NLW_U0_Dbg_Clk_21_UNCONNECTED),
.Dbg_Clk_22(NLW_U0_Dbg_Clk_22_UNCONNECTED),
.Dbg_Clk_23(NLW_U0_Dbg_Clk_23_UNCONNECTED),
.Dbg_Clk_24(NLW_U0_Dbg_Clk_24_UNCONNECTED),
.Dbg_Clk_25(NLW_U0_Dbg_Clk_25_UNCONNECTED),
.Dbg_Clk_26(NLW_U0_Dbg_Clk_26_UNCONNECTED),
.Dbg_Clk_27(NLW_U0_Dbg_Clk_27_UNCONNECTED),
.Dbg_Clk_28(NLW_U0_Dbg_Clk_28_UNCONNECTED),
.Dbg_Clk_29(NLW_U0_Dbg_Clk_29_UNCONNECTED),
.Dbg_Clk_3(NLW_U0_Dbg_Clk_3_UNCONNECTED),
.Dbg_Clk_30(NLW_U0_Dbg_Clk_30_UNCONNECTED),
.Dbg_Clk_31(NLW_U0_Dbg_Clk_31_UNCONNECTED),
.Dbg_Clk_4(NLW_U0_Dbg_Clk_4_UNCONNECTED),
.Dbg_Clk_5(NLW_U0_Dbg_Clk_5_UNCONNECTED),
.Dbg_Clk_6(NLW_U0_Dbg_Clk_6_UNCONNECTED),
.Dbg_Clk_7(NLW_U0_Dbg_Clk_7_UNCONNECTED),
.Dbg_Clk_8(NLW_U0_Dbg_Clk_8_UNCONNECTED),
.Dbg_Clk_9(NLW_U0_Dbg_Clk_9_UNCONNECTED),
.Dbg_Disable_0(Dbg_Disable_0),
.Dbg_Disable_1(NLW_U0_Dbg_Disable_1_UNCONNECTED),
.Dbg_Disable_10(NLW_U0_Dbg_Disable_10_UNCONNECTED),
.Dbg_Disable_11(NLW_U0_Dbg_Disable_11_UNCONNECTED),
.Dbg_Disable_12(NLW_U0_Dbg_Disable_12_UNCONNECTED),
.Dbg_Disable_13(NLW_U0_Dbg_Disable_13_UNCONNECTED),
.Dbg_Disable_14(NLW_U0_Dbg_Disable_14_UNCONNECTED),
.Dbg_Disable_15(NLW_U0_Dbg_Disable_15_UNCONNECTED),
.Dbg_Disable_16(NLW_U0_Dbg_Disable_16_UNCONNECTED),
.Dbg_Disable_17(NLW_U0_Dbg_Disable_17_UNCONNECTED),
.Dbg_Disable_18(NLW_U0_Dbg_Disable_18_UNCONNECTED),
.Dbg_Disable_19(NLW_U0_Dbg_Disable_19_UNCONNECTED),
.Dbg_Disable_2(NLW_U0_Dbg_Disable_2_UNCONNECTED),
.Dbg_Disable_20(NLW_U0_Dbg_Disable_20_UNCONNECTED),
.Dbg_Disable_21(NLW_U0_Dbg_Disable_21_UNCONNECTED),
.Dbg_Disable_22(NLW_U0_Dbg_Disable_22_UNCONNECTED),
.Dbg_Disable_23(NLW_U0_Dbg_Disable_23_UNCONNECTED),
.Dbg_Disable_24(NLW_U0_Dbg_Disable_24_UNCONNECTED),
.Dbg_Disable_25(NLW_U0_Dbg_Disable_25_UNCONNECTED),
.Dbg_Disable_26(NLW_U0_Dbg_Disable_26_UNCONNECTED),
.Dbg_Disable_27(NLW_U0_Dbg_Disable_27_UNCONNECTED),
.Dbg_Disable_28(NLW_U0_Dbg_Disable_28_UNCONNECTED),
.Dbg_Disable_29(NLW_U0_Dbg_Disable_29_UNCONNECTED),
.Dbg_Disable_3(NLW_U0_Dbg_Disable_3_UNCONNECTED),
.Dbg_Disable_30(NLW_U0_Dbg_Disable_30_UNCONNECTED),
.Dbg_Disable_31(NLW_U0_Dbg_Disable_31_UNCONNECTED),
.Dbg_Disable_4(NLW_U0_Dbg_Disable_4_UNCONNECTED),
.Dbg_Disable_5(NLW_U0_Dbg_Disable_5_UNCONNECTED),
.Dbg_Disable_6(NLW_U0_Dbg_Disable_6_UNCONNECTED),
.Dbg_Disable_7(NLW_U0_Dbg_Disable_7_UNCONNECTED),
.Dbg_Disable_8(NLW_U0_Dbg_Disable_8_UNCONNECTED),
.Dbg_Disable_9(NLW_U0_Dbg_Disable_9_UNCONNECTED),
.Dbg_RDATA_0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_RDATA_1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_RDATA_10({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_RDATA_11({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_RDATA_12({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_RDATA_13({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_RDATA_14({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_RDATA_15({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_RDATA_16({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_RDATA_17({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_RDATA_18({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_RDATA_19({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_RDATA_2({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_RDATA_20({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_RDATA_21({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_RDATA_22({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_RDATA_23({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_RDATA_24({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_RDATA_25({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_RDATA_26({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_RDATA_27({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_RDATA_28({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_RDATA_29({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_RDATA_3({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_RDATA_30({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_RDATA_31({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_RDATA_4({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_RDATA_5({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_RDATA_6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_RDATA_7({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_RDATA_8({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_RDATA_9({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_RREADY_0(NLW_U0_Dbg_RREADY_0_UNCONNECTED),
.Dbg_RREADY_1(NLW_U0_Dbg_RREADY_1_UNCONNECTED),
.Dbg_RREADY_10(NLW_U0_Dbg_RREADY_10_UNCONNECTED),
.Dbg_RREADY_11(NLW_U0_Dbg_RREADY_11_UNCONNECTED),
.Dbg_RREADY_12(NLW_U0_Dbg_RREADY_12_UNCONNECTED),
.Dbg_RREADY_13(NLW_U0_Dbg_RREADY_13_UNCONNECTED),
.Dbg_RREADY_14(NLW_U0_Dbg_RREADY_14_UNCONNECTED),
.Dbg_RREADY_15(NLW_U0_Dbg_RREADY_15_UNCONNECTED),
.Dbg_RREADY_16(NLW_U0_Dbg_RREADY_16_UNCONNECTED),
.Dbg_RREADY_17(NLW_U0_Dbg_RREADY_17_UNCONNECTED),
.Dbg_RREADY_18(NLW_U0_Dbg_RREADY_18_UNCONNECTED),
.Dbg_RREADY_19(NLW_U0_Dbg_RREADY_19_UNCONNECTED),
.Dbg_RREADY_2(NLW_U0_Dbg_RREADY_2_UNCONNECTED),
.Dbg_RREADY_20(NLW_U0_Dbg_RREADY_20_UNCONNECTED),
.Dbg_RREADY_21(NLW_U0_Dbg_RREADY_21_UNCONNECTED),
.Dbg_RREADY_22(NLW_U0_Dbg_RREADY_22_UNCONNECTED),
.Dbg_RREADY_23(NLW_U0_Dbg_RREADY_23_UNCONNECTED),
.Dbg_RREADY_24(NLW_U0_Dbg_RREADY_24_UNCONNECTED),
.Dbg_RREADY_25(NLW_U0_Dbg_RREADY_25_UNCONNECTED),
.Dbg_RREADY_26(NLW_U0_Dbg_RREADY_26_UNCONNECTED),
.Dbg_RREADY_27(NLW_U0_Dbg_RREADY_27_UNCONNECTED),
.Dbg_RREADY_28(NLW_U0_Dbg_RREADY_28_UNCONNECTED),
.Dbg_RREADY_29(NLW_U0_Dbg_RREADY_29_UNCONNECTED),
.Dbg_RREADY_3(NLW_U0_Dbg_RREADY_3_UNCONNECTED),
.Dbg_RREADY_30(NLW_U0_Dbg_RREADY_30_UNCONNECTED),
.Dbg_RREADY_31(NLW_U0_Dbg_RREADY_31_UNCONNECTED),
.Dbg_RREADY_4(NLW_U0_Dbg_RREADY_4_UNCONNECTED),
.Dbg_RREADY_5(NLW_U0_Dbg_RREADY_5_UNCONNECTED),
.Dbg_RREADY_6(NLW_U0_Dbg_RREADY_6_UNCONNECTED),
.Dbg_RREADY_7(NLW_U0_Dbg_RREADY_7_UNCONNECTED),
.Dbg_RREADY_8(NLW_U0_Dbg_RREADY_8_UNCONNECTED),
.Dbg_RREADY_9(NLW_U0_Dbg_RREADY_9_UNCONNECTED),
.Dbg_RRESP_0({1'b0,1'b0}),
.Dbg_RRESP_1({1'b0,1'b0}),
.Dbg_RRESP_10({1'b0,1'b0}),
.Dbg_RRESP_11({1'b0,1'b0}),
.Dbg_RRESP_12({1'b0,1'b0}),
.Dbg_RRESP_13({1'b0,1'b0}),
.Dbg_RRESP_14({1'b0,1'b0}),
.Dbg_RRESP_15({1'b0,1'b0}),
.Dbg_RRESP_16({1'b0,1'b0}),
.Dbg_RRESP_17({1'b0,1'b0}),
.Dbg_RRESP_18({1'b0,1'b0}),
.Dbg_RRESP_19({1'b0,1'b0}),
.Dbg_RRESP_2({1'b0,1'b0}),
.Dbg_RRESP_20({1'b0,1'b0}),
.Dbg_RRESP_21({1'b0,1'b0}),
.Dbg_RRESP_22({1'b0,1'b0}),
.Dbg_RRESP_23({1'b0,1'b0}),
.Dbg_RRESP_24({1'b0,1'b0}),
.Dbg_RRESP_25({1'b0,1'b0}),
.Dbg_RRESP_26({1'b0,1'b0}),
.Dbg_RRESP_27({1'b0,1'b0}),
.Dbg_RRESP_28({1'b0,1'b0}),
.Dbg_RRESP_29({1'b0,1'b0}),
.Dbg_RRESP_3({1'b0,1'b0}),
.Dbg_RRESP_30({1'b0,1'b0}),
.Dbg_RRESP_31({1'b0,1'b0}),
.Dbg_RRESP_4({1'b0,1'b0}),
.Dbg_RRESP_5({1'b0,1'b0}),
.Dbg_RRESP_6({1'b0,1'b0}),
.Dbg_RRESP_7({1'b0,1'b0}),
.Dbg_RRESP_8({1'b0,1'b0}),
.Dbg_RRESP_9({1'b0,1'b0}),
.Dbg_RVALID_0(1'b0),
.Dbg_RVALID_1(1'b0),
.Dbg_RVALID_10(1'b0),
.Dbg_RVALID_11(1'b0),
.Dbg_RVALID_12(1'b0),
.Dbg_RVALID_13(1'b0),
.Dbg_RVALID_14(1'b0),
.Dbg_RVALID_15(1'b0),
.Dbg_RVALID_16(1'b0),
.Dbg_RVALID_17(1'b0),
.Dbg_RVALID_18(1'b0),
.Dbg_RVALID_19(1'b0),
.Dbg_RVALID_2(1'b0),
.Dbg_RVALID_20(1'b0),
.Dbg_RVALID_21(1'b0),
.Dbg_RVALID_22(1'b0),
.Dbg_RVALID_23(1'b0),
.Dbg_RVALID_24(1'b0),
.Dbg_RVALID_25(1'b0),
.Dbg_RVALID_26(1'b0),
.Dbg_RVALID_27(1'b0),
.Dbg_RVALID_28(1'b0),
.Dbg_RVALID_29(1'b0),
.Dbg_RVALID_3(1'b0),
.Dbg_RVALID_30(1'b0),
.Dbg_RVALID_31(1'b0),
.Dbg_RVALID_4(1'b0),
.Dbg_RVALID_5(1'b0),
.Dbg_RVALID_6(1'b0),
.Dbg_RVALID_7(1'b0),
.Dbg_RVALID_8(1'b0),
.Dbg_RVALID_9(1'b0),
.Dbg_Reg_En_0(Dbg_Reg_En_0),
.Dbg_Reg_En_1(NLW_U0_Dbg_Reg_En_1_UNCONNECTED[0:7]),
.Dbg_Reg_En_10(NLW_U0_Dbg_Reg_En_10_UNCONNECTED[0:7]),
.Dbg_Reg_En_11(NLW_U0_Dbg_Reg_En_11_UNCONNECTED[0:7]),
.Dbg_Reg_En_12(NLW_U0_Dbg_Reg_En_12_UNCONNECTED[0:7]),
.Dbg_Reg_En_13(NLW_U0_Dbg_Reg_En_13_UNCONNECTED[0:7]),
.Dbg_Reg_En_14(NLW_U0_Dbg_Reg_En_14_UNCONNECTED[0:7]),
.Dbg_Reg_En_15(NLW_U0_Dbg_Reg_En_15_UNCONNECTED[0:7]),
.Dbg_Reg_En_16(NLW_U0_Dbg_Reg_En_16_UNCONNECTED[0:7]),
.Dbg_Reg_En_17(NLW_U0_Dbg_Reg_En_17_UNCONNECTED[0:7]),
.Dbg_Reg_En_18(NLW_U0_Dbg_Reg_En_18_UNCONNECTED[0:7]),
.Dbg_Reg_En_19(NLW_U0_Dbg_Reg_En_19_UNCONNECTED[0:7]),
.Dbg_Reg_En_2(NLW_U0_Dbg_Reg_En_2_UNCONNECTED[0:7]),
.Dbg_Reg_En_20(NLW_U0_Dbg_Reg_En_20_UNCONNECTED[0:7]),
.Dbg_Reg_En_21(NLW_U0_Dbg_Reg_En_21_UNCONNECTED[0:7]),
.Dbg_Reg_En_22(NLW_U0_Dbg_Reg_En_22_UNCONNECTED[0:7]),
.Dbg_Reg_En_23(NLW_U0_Dbg_Reg_En_23_UNCONNECTED[0:7]),
.Dbg_Reg_En_24(NLW_U0_Dbg_Reg_En_24_UNCONNECTED[0:7]),
.Dbg_Reg_En_25(NLW_U0_Dbg_Reg_En_25_UNCONNECTED[0:7]),
.Dbg_Reg_En_26(NLW_U0_Dbg_Reg_En_26_UNCONNECTED[0:7]),
.Dbg_Reg_En_27(NLW_U0_Dbg_Reg_En_27_UNCONNECTED[0:7]),
.Dbg_Reg_En_28(NLW_U0_Dbg_Reg_En_28_UNCONNECTED[0:7]),
.Dbg_Reg_En_29(NLW_U0_Dbg_Reg_En_29_UNCONNECTED[0:7]),
.Dbg_Reg_En_3(NLW_U0_Dbg_Reg_En_3_UNCONNECTED[0:7]),
.Dbg_Reg_En_30(NLW_U0_Dbg_Reg_En_30_UNCONNECTED[0:7]),
.Dbg_Reg_En_31(NLW_U0_Dbg_Reg_En_31_UNCONNECTED[0:7]),
.Dbg_Reg_En_4(NLW_U0_Dbg_Reg_En_4_UNCONNECTED[0:7]),
.Dbg_Reg_En_5(NLW_U0_Dbg_Reg_En_5_UNCONNECTED[0:7]),
.Dbg_Reg_En_6(NLW_U0_Dbg_Reg_En_6_UNCONNECTED[0:7]),
.Dbg_Reg_En_7(NLW_U0_Dbg_Reg_En_7_UNCONNECTED[0:7]),
.Dbg_Reg_En_8(NLW_U0_Dbg_Reg_En_8_UNCONNECTED[0:7]),
.Dbg_Reg_En_9(NLW_U0_Dbg_Reg_En_9_UNCONNECTED[0:7]),
.Dbg_Rst_0(Dbg_Rst_0),
.Dbg_Rst_1(NLW_U0_Dbg_Rst_1_UNCONNECTED),
.Dbg_Rst_10(NLW_U0_Dbg_Rst_10_UNCONNECTED),
.Dbg_Rst_11(NLW_U0_Dbg_Rst_11_UNCONNECTED),
.Dbg_Rst_12(NLW_U0_Dbg_Rst_12_UNCONNECTED),
.Dbg_Rst_13(NLW_U0_Dbg_Rst_13_UNCONNECTED),
.Dbg_Rst_14(NLW_U0_Dbg_Rst_14_UNCONNECTED),
.Dbg_Rst_15(NLW_U0_Dbg_Rst_15_UNCONNECTED),
.Dbg_Rst_16(NLW_U0_Dbg_Rst_16_UNCONNECTED),
.Dbg_Rst_17(NLW_U0_Dbg_Rst_17_UNCONNECTED),
.Dbg_Rst_18(NLW_U0_Dbg_Rst_18_UNCONNECTED),
.Dbg_Rst_19(NLW_U0_Dbg_Rst_19_UNCONNECTED),
.Dbg_Rst_2(NLW_U0_Dbg_Rst_2_UNCONNECTED),
.Dbg_Rst_20(NLW_U0_Dbg_Rst_20_UNCONNECTED),
.Dbg_Rst_21(NLW_U0_Dbg_Rst_21_UNCONNECTED),
.Dbg_Rst_22(NLW_U0_Dbg_Rst_22_UNCONNECTED),
.Dbg_Rst_23(NLW_U0_Dbg_Rst_23_UNCONNECTED),
.Dbg_Rst_24(NLW_U0_Dbg_Rst_24_UNCONNECTED),
.Dbg_Rst_25(NLW_U0_Dbg_Rst_25_UNCONNECTED),
.Dbg_Rst_26(NLW_U0_Dbg_Rst_26_UNCONNECTED),
.Dbg_Rst_27(NLW_U0_Dbg_Rst_27_UNCONNECTED),
.Dbg_Rst_28(NLW_U0_Dbg_Rst_28_UNCONNECTED),
.Dbg_Rst_29(NLW_U0_Dbg_Rst_29_UNCONNECTED),
.Dbg_Rst_3(NLW_U0_Dbg_Rst_3_UNCONNECTED),
.Dbg_Rst_30(NLW_U0_Dbg_Rst_30_UNCONNECTED),
.Dbg_Rst_31(NLW_U0_Dbg_Rst_31_UNCONNECTED),
.Dbg_Rst_4(NLW_U0_Dbg_Rst_4_UNCONNECTED),
.Dbg_Rst_5(NLW_U0_Dbg_Rst_5_UNCONNECTED),
.Dbg_Rst_6(NLW_U0_Dbg_Rst_6_UNCONNECTED),
.Dbg_Rst_7(NLW_U0_Dbg_Rst_7_UNCONNECTED),
.Dbg_Rst_8(NLW_U0_Dbg_Rst_8_UNCONNECTED),
.Dbg_Rst_9(NLW_U0_Dbg_Rst_9_UNCONNECTED),
.Dbg_Shift_0(Dbg_Shift_0),
.Dbg_Shift_1(NLW_U0_Dbg_Shift_1_UNCONNECTED),
.Dbg_Shift_10(NLW_U0_Dbg_Shift_10_UNCONNECTED),
.Dbg_Shift_11(NLW_U0_Dbg_Shift_11_UNCONNECTED),
.Dbg_Shift_12(NLW_U0_Dbg_Shift_12_UNCONNECTED),
.Dbg_Shift_13(NLW_U0_Dbg_Shift_13_UNCONNECTED),
.Dbg_Shift_14(NLW_U0_Dbg_Shift_14_UNCONNECTED),
.Dbg_Shift_15(NLW_U0_Dbg_Shift_15_UNCONNECTED),
.Dbg_Shift_16(NLW_U0_Dbg_Shift_16_UNCONNECTED),
.Dbg_Shift_17(NLW_U0_Dbg_Shift_17_UNCONNECTED),
.Dbg_Shift_18(NLW_U0_Dbg_Shift_18_UNCONNECTED),
.Dbg_Shift_19(NLW_U0_Dbg_Shift_19_UNCONNECTED),
.Dbg_Shift_2(NLW_U0_Dbg_Shift_2_UNCONNECTED),
.Dbg_Shift_20(NLW_U0_Dbg_Shift_20_UNCONNECTED),
.Dbg_Shift_21(NLW_U0_Dbg_Shift_21_UNCONNECTED),
.Dbg_Shift_22(NLW_U0_Dbg_Shift_22_UNCONNECTED),
.Dbg_Shift_23(NLW_U0_Dbg_Shift_23_UNCONNECTED),
.Dbg_Shift_24(NLW_U0_Dbg_Shift_24_UNCONNECTED),
.Dbg_Shift_25(NLW_U0_Dbg_Shift_25_UNCONNECTED),
.Dbg_Shift_26(NLW_U0_Dbg_Shift_26_UNCONNECTED),
.Dbg_Shift_27(NLW_U0_Dbg_Shift_27_UNCONNECTED),
.Dbg_Shift_28(NLW_U0_Dbg_Shift_28_UNCONNECTED),
.Dbg_Shift_29(NLW_U0_Dbg_Shift_29_UNCONNECTED),
.Dbg_Shift_3(NLW_U0_Dbg_Shift_3_UNCONNECTED),
.Dbg_Shift_30(NLW_U0_Dbg_Shift_30_UNCONNECTED),
.Dbg_Shift_31(NLW_U0_Dbg_Shift_31_UNCONNECTED),
.Dbg_Shift_4(NLW_U0_Dbg_Shift_4_UNCONNECTED),
.Dbg_Shift_5(NLW_U0_Dbg_Shift_5_UNCONNECTED),
.Dbg_Shift_6(NLW_U0_Dbg_Shift_6_UNCONNECTED),
.Dbg_Shift_7(NLW_U0_Dbg_Shift_7_UNCONNECTED),
.Dbg_Shift_8(NLW_U0_Dbg_Shift_8_UNCONNECTED),
.Dbg_Shift_9(NLW_U0_Dbg_Shift_9_UNCONNECTED),
.Dbg_TDI_0(Dbg_TDI_0),
.Dbg_TDI_1(NLW_U0_Dbg_TDI_1_UNCONNECTED),
.Dbg_TDI_10(NLW_U0_Dbg_TDI_10_UNCONNECTED),
.Dbg_TDI_11(NLW_U0_Dbg_TDI_11_UNCONNECTED),
.Dbg_TDI_12(NLW_U0_Dbg_TDI_12_UNCONNECTED),
.Dbg_TDI_13(NLW_U0_Dbg_TDI_13_UNCONNECTED),
.Dbg_TDI_14(NLW_U0_Dbg_TDI_14_UNCONNECTED),
.Dbg_TDI_15(NLW_U0_Dbg_TDI_15_UNCONNECTED),
.Dbg_TDI_16(NLW_U0_Dbg_TDI_16_UNCONNECTED),
.Dbg_TDI_17(NLW_U0_Dbg_TDI_17_UNCONNECTED),
.Dbg_TDI_18(NLW_U0_Dbg_TDI_18_UNCONNECTED),
.Dbg_TDI_19(NLW_U0_Dbg_TDI_19_UNCONNECTED),
.Dbg_TDI_2(NLW_U0_Dbg_TDI_2_UNCONNECTED),
.Dbg_TDI_20(NLW_U0_Dbg_TDI_20_UNCONNECTED),
.Dbg_TDI_21(NLW_U0_Dbg_TDI_21_UNCONNECTED),
.Dbg_TDI_22(NLW_U0_Dbg_TDI_22_UNCONNECTED),
.Dbg_TDI_23(NLW_U0_Dbg_TDI_23_UNCONNECTED),
.Dbg_TDI_24(NLW_U0_Dbg_TDI_24_UNCONNECTED),
.Dbg_TDI_25(NLW_U0_Dbg_TDI_25_UNCONNECTED),
.Dbg_TDI_26(NLW_U0_Dbg_TDI_26_UNCONNECTED),
.Dbg_TDI_27(NLW_U0_Dbg_TDI_27_UNCONNECTED),
.Dbg_TDI_28(NLW_U0_Dbg_TDI_28_UNCONNECTED),
.Dbg_TDI_29(NLW_U0_Dbg_TDI_29_UNCONNECTED),
.Dbg_TDI_3(NLW_U0_Dbg_TDI_3_UNCONNECTED),
.Dbg_TDI_30(NLW_U0_Dbg_TDI_30_UNCONNECTED),
.Dbg_TDI_31(NLW_U0_Dbg_TDI_31_UNCONNECTED),
.Dbg_TDI_4(NLW_U0_Dbg_TDI_4_UNCONNECTED),
.Dbg_TDI_5(NLW_U0_Dbg_TDI_5_UNCONNECTED),
.Dbg_TDI_6(NLW_U0_Dbg_TDI_6_UNCONNECTED),
.Dbg_TDI_7(NLW_U0_Dbg_TDI_7_UNCONNECTED),
.Dbg_TDI_8(NLW_U0_Dbg_TDI_8_UNCONNECTED),
.Dbg_TDI_9(NLW_U0_Dbg_TDI_9_UNCONNECTED),
.Dbg_TDO_0(Dbg_TDO_0),
.Dbg_TDO_1(1'b0),
.Dbg_TDO_10(1'b0),
.Dbg_TDO_11(1'b0),
.Dbg_TDO_12(1'b0),
.Dbg_TDO_13(1'b0),
.Dbg_TDO_14(1'b0),
.Dbg_TDO_15(1'b0),
.Dbg_TDO_16(1'b0),
.Dbg_TDO_17(1'b0),
.Dbg_TDO_18(1'b0),
.Dbg_TDO_19(1'b0),
.Dbg_TDO_2(1'b0),
.Dbg_TDO_20(1'b0),
.Dbg_TDO_21(1'b0),
.Dbg_TDO_22(1'b0),
.Dbg_TDO_23(1'b0),
.Dbg_TDO_24(1'b0),
.Dbg_TDO_25(1'b0),
.Dbg_TDO_26(1'b0),
.Dbg_TDO_27(1'b0),
.Dbg_TDO_28(1'b0),
.Dbg_TDO_29(1'b0),
.Dbg_TDO_3(1'b0),
.Dbg_TDO_30(1'b0),
.Dbg_TDO_31(1'b0),
.Dbg_TDO_4(1'b0),
.Dbg_TDO_5(1'b0),
.Dbg_TDO_6(1'b0),
.Dbg_TDO_7(1'b0),
.Dbg_TDO_8(1'b0),
.Dbg_TDO_9(1'b0),
.Dbg_TrClk_0(NLW_U0_Dbg_TrClk_0_UNCONNECTED),
.Dbg_TrClk_1(NLW_U0_Dbg_TrClk_1_UNCONNECTED),
.Dbg_TrClk_10(NLW_U0_Dbg_TrClk_10_UNCONNECTED),
.Dbg_TrClk_11(NLW_U0_Dbg_TrClk_11_UNCONNECTED),
.Dbg_TrClk_12(NLW_U0_Dbg_TrClk_12_UNCONNECTED),
.Dbg_TrClk_13(NLW_U0_Dbg_TrClk_13_UNCONNECTED),
.Dbg_TrClk_14(NLW_U0_Dbg_TrClk_14_UNCONNECTED),
.Dbg_TrClk_15(NLW_U0_Dbg_TrClk_15_UNCONNECTED),
.Dbg_TrClk_16(NLW_U0_Dbg_TrClk_16_UNCONNECTED),
.Dbg_TrClk_17(NLW_U0_Dbg_TrClk_17_UNCONNECTED),
.Dbg_TrClk_18(NLW_U0_Dbg_TrClk_18_UNCONNECTED),
.Dbg_TrClk_19(NLW_U0_Dbg_TrClk_19_UNCONNECTED),
.Dbg_TrClk_2(NLW_U0_Dbg_TrClk_2_UNCONNECTED),
.Dbg_TrClk_20(NLW_U0_Dbg_TrClk_20_UNCONNECTED),
.Dbg_TrClk_21(NLW_U0_Dbg_TrClk_21_UNCONNECTED),
.Dbg_TrClk_22(NLW_U0_Dbg_TrClk_22_UNCONNECTED),
.Dbg_TrClk_23(NLW_U0_Dbg_TrClk_23_UNCONNECTED),
.Dbg_TrClk_24(NLW_U0_Dbg_TrClk_24_UNCONNECTED),
.Dbg_TrClk_25(NLW_U0_Dbg_TrClk_25_UNCONNECTED),
.Dbg_TrClk_26(NLW_U0_Dbg_TrClk_26_UNCONNECTED),
.Dbg_TrClk_27(NLW_U0_Dbg_TrClk_27_UNCONNECTED),
.Dbg_TrClk_28(NLW_U0_Dbg_TrClk_28_UNCONNECTED),
.Dbg_TrClk_29(NLW_U0_Dbg_TrClk_29_UNCONNECTED),
.Dbg_TrClk_3(NLW_U0_Dbg_TrClk_3_UNCONNECTED),
.Dbg_TrClk_30(NLW_U0_Dbg_TrClk_30_UNCONNECTED),
.Dbg_TrClk_31(NLW_U0_Dbg_TrClk_31_UNCONNECTED),
.Dbg_TrClk_4(NLW_U0_Dbg_TrClk_4_UNCONNECTED),
.Dbg_TrClk_5(NLW_U0_Dbg_TrClk_5_UNCONNECTED),
.Dbg_TrClk_6(NLW_U0_Dbg_TrClk_6_UNCONNECTED),
.Dbg_TrClk_7(NLW_U0_Dbg_TrClk_7_UNCONNECTED),
.Dbg_TrClk_8(NLW_U0_Dbg_TrClk_8_UNCONNECTED),
.Dbg_TrClk_9(NLW_U0_Dbg_TrClk_9_UNCONNECTED),
.Dbg_TrData_0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_TrData_1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_TrData_10({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_TrData_11({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_TrData_12({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_TrData_13({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_TrData_14({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_TrData_15({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_TrData_16({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_TrData_17({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_TrData_18({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_TrData_19({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_TrData_2({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_TrData_20({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_TrData_21({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_TrData_22({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_TrData_23({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_TrData_24({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_TrData_25({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_TrData_26({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_TrData_27({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_TrData_28({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_TrData_29({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_TrData_3({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_TrData_30({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_TrData_31({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_TrData_4({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_TrData_5({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_TrData_6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_TrData_7({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_TrData_8({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_TrData_9({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_TrReady_0(NLW_U0_Dbg_TrReady_0_UNCONNECTED),
.Dbg_TrReady_1(NLW_U0_Dbg_TrReady_1_UNCONNECTED),
.Dbg_TrReady_10(NLW_U0_Dbg_TrReady_10_UNCONNECTED),
.Dbg_TrReady_11(NLW_U0_Dbg_TrReady_11_UNCONNECTED),
.Dbg_TrReady_12(NLW_U0_Dbg_TrReady_12_UNCONNECTED),
.Dbg_TrReady_13(NLW_U0_Dbg_TrReady_13_UNCONNECTED),
.Dbg_TrReady_14(NLW_U0_Dbg_TrReady_14_UNCONNECTED),
.Dbg_TrReady_15(NLW_U0_Dbg_TrReady_15_UNCONNECTED),
.Dbg_TrReady_16(NLW_U0_Dbg_TrReady_16_UNCONNECTED),
.Dbg_TrReady_17(NLW_U0_Dbg_TrReady_17_UNCONNECTED),
.Dbg_TrReady_18(NLW_U0_Dbg_TrReady_18_UNCONNECTED),
.Dbg_TrReady_19(NLW_U0_Dbg_TrReady_19_UNCONNECTED),
.Dbg_TrReady_2(NLW_U0_Dbg_TrReady_2_UNCONNECTED),
.Dbg_TrReady_20(NLW_U0_Dbg_TrReady_20_UNCONNECTED),
.Dbg_TrReady_21(NLW_U0_Dbg_TrReady_21_UNCONNECTED),
.Dbg_TrReady_22(NLW_U0_Dbg_TrReady_22_UNCONNECTED),
.Dbg_TrReady_23(NLW_U0_Dbg_TrReady_23_UNCONNECTED),
.Dbg_TrReady_24(NLW_U0_Dbg_TrReady_24_UNCONNECTED),
.Dbg_TrReady_25(NLW_U0_Dbg_TrReady_25_UNCONNECTED),
.Dbg_TrReady_26(NLW_U0_Dbg_TrReady_26_UNCONNECTED),
.Dbg_TrReady_27(NLW_U0_Dbg_TrReady_27_UNCONNECTED),
.Dbg_TrReady_28(NLW_U0_Dbg_TrReady_28_UNCONNECTED),
.Dbg_TrReady_29(NLW_U0_Dbg_TrReady_29_UNCONNECTED),
.Dbg_TrReady_3(NLW_U0_Dbg_TrReady_3_UNCONNECTED),
.Dbg_TrReady_30(NLW_U0_Dbg_TrReady_30_UNCONNECTED),
.Dbg_TrReady_31(NLW_U0_Dbg_TrReady_31_UNCONNECTED),
.Dbg_TrReady_4(NLW_U0_Dbg_TrReady_4_UNCONNECTED),
.Dbg_TrReady_5(NLW_U0_Dbg_TrReady_5_UNCONNECTED),
.Dbg_TrReady_6(NLW_U0_Dbg_TrReady_6_UNCONNECTED),
.Dbg_TrReady_7(NLW_U0_Dbg_TrReady_7_UNCONNECTED),
.Dbg_TrReady_8(NLW_U0_Dbg_TrReady_8_UNCONNECTED),
.Dbg_TrReady_9(NLW_U0_Dbg_TrReady_9_UNCONNECTED),
.Dbg_TrValid_0(1'b0),
.Dbg_TrValid_1(1'b0),
.Dbg_TrValid_10(1'b0),
.Dbg_TrValid_11(1'b0),
.Dbg_TrValid_12(1'b0),
.Dbg_TrValid_13(1'b0),
.Dbg_TrValid_14(1'b0),
.Dbg_TrValid_15(1'b0),
.Dbg_TrValid_16(1'b0),
.Dbg_TrValid_17(1'b0),
.Dbg_TrValid_18(1'b0),
.Dbg_TrValid_19(1'b0),
.Dbg_TrValid_2(1'b0),
.Dbg_TrValid_20(1'b0),
.Dbg_TrValid_21(1'b0),
.Dbg_TrValid_22(1'b0),
.Dbg_TrValid_23(1'b0),
.Dbg_TrValid_24(1'b0),
.Dbg_TrValid_25(1'b0),
.Dbg_TrValid_26(1'b0),
.Dbg_TrValid_27(1'b0),
.Dbg_TrValid_28(1'b0),
.Dbg_TrValid_29(1'b0),
.Dbg_TrValid_3(1'b0),
.Dbg_TrValid_30(1'b0),
.Dbg_TrValid_31(1'b0),
.Dbg_TrValid_4(1'b0),
.Dbg_TrValid_5(1'b0),
.Dbg_TrValid_6(1'b0),
.Dbg_TrValid_7(1'b0),
.Dbg_TrValid_8(1'b0),
.Dbg_TrValid_9(1'b0),
.Dbg_Trig_Ack_In_0(NLW_U0_Dbg_Trig_Ack_In_0_UNCONNECTED[0:7]),
.Dbg_Trig_Ack_In_1(NLW_U0_Dbg_Trig_Ack_In_1_UNCONNECTED[0:7]),
.Dbg_Trig_Ack_In_10(NLW_U0_Dbg_Trig_Ack_In_10_UNCONNECTED[0:7]),
.Dbg_Trig_Ack_In_11(NLW_U0_Dbg_Trig_Ack_In_11_UNCONNECTED[0:7]),
.Dbg_Trig_Ack_In_12(NLW_U0_Dbg_Trig_Ack_In_12_UNCONNECTED[0:7]),
.Dbg_Trig_Ack_In_13(NLW_U0_Dbg_Trig_Ack_In_13_UNCONNECTED[0:7]),
.Dbg_Trig_Ack_In_14(NLW_U0_Dbg_Trig_Ack_In_14_UNCONNECTED[0:7]),
.Dbg_Trig_Ack_In_15(NLW_U0_Dbg_Trig_Ack_In_15_UNCONNECTED[0:7]),
.Dbg_Trig_Ack_In_16(NLW_U0_Dbg_Trig_Ack_In_16_UNCONNECTED[0:7]),
.Dbg_Trig_Ack_In_17(NLW_U0_Dbg_Trig_Ack_In_17_UNCONNECTED[0:7]),
.Dbg_Trig_Ack_In_18(NLW_U0_Dbg_Trig_Ack_In_18_UNCONNECTED[0:7]),
.Dbg_Trig_Ack_In_19(NLW_U0_Dbg_Trig_Ack_In_19_UNCONNECTED[0:7]),
.Dbg_Trig_Ack_In_2(NLW_U0_Dbg_Trig_Ack_In_2_UNCONNECTED[0:7]),
.Dbg_Trig_Ack_In_20(NLW_U0_Dbg_Trig_Ack_In_20_UNCONNECTED[0:7]),
.Dbg_Trig_Ack_In_21(NLW_U0_Dbg_Trig_Ack_In_21_UNCONNECTED[0:7]),
.Dbg_Trig_Ack_In_22(NLW_U0_Dbg_Trig_Ack_In_22_UNCONNECTED[0:7]),
.Dbg_Trig_Ack_In_23(NLW_U0_Dbg_Trig_Ack_In_23_UNCONNECTED[0:7]),
.Dbg_Trig_Ack_In_24(NLW_U0_Dbg_Trig_Ack_In_24_UNCONNECTED[0:7]),
.Dbg_Trig_Ack_In_25(NLW_U0_Dbg_Trig_Ack_In_25_UNCONNECTED[0:7]),
.Dbg_Trig_Ack_In_26(NLW_U0_Dbg_Trig_Ack_In_26_UNCONNECTED[0:7]),
.Dbg_Trig_Ack_In_27(NLW_U0_Dbg_Trig_Ack_In_27_UNCONNECTED[0:7]),
.Dbg_Trig_Ack_In_28(NLW_U0_Dbg_Trig_Ack_In_28_UNCONNECTED[0:7]),
.Dbg_Trig_Ack_In_29(NLW_U0_Dbg_Trig_Ack_In_29_UNCONNECTED[0:7]),
.Dbg_Trig_Ack_In_3(NLW_U0_Dbg_Trig_Ack_In_3_UNCONNECTED[0:7]),
.Dbg_Trig_Ack_In_30(NLW_U0_Dbg_Trig_Ack_In_30_UNCONNECTED[0:7]),
.Dbg_Trig_Ack_In_31(NLW_U0_Dbg_Trig_Ack_In_31_UNCONNECTED[0:7]),
.Dbg_Trig_Ack_In_4(NLW_U0_Dbg_Trig_Ack_In_4_UNCONNECTED[0:7]),
.Dbg_Trig_Ack_In_5(NLW_U0_Dbg_Trig_Ack_In_5_UNCONNECTED[0:7]),
.Dbg_Trig_Ack_In_6(NLW_U0_Dbg_Trig_Ack_In_6_UNCONNECTED[0:7]),
.Dbg_Trig_Ack_In_7(NLW_U0_Dbg_Trig_Ack_In_7_UNCONNECTED[0:7]),
.Dbg_Trig_Ack_In_8(NLW_U0_Dbg_Trig_Ack_In_8_UNCONNECTED[0:7]),
.Dbg_Trig_Ack_In_9(NLW_U0_Dbg_Trig_Ack_In_9_UNCONNECTED[0:7]),
.Dbg_Trig_Ack_Out_0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_Ack_Out_1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_Ack_Out_10({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_Ack_Out_11({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_Ack_Out_12({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_Ack_Out_13({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_Ack_Out_14({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_Ack_Out_15({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_Ack_Out_16({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_Ack_Out_17({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_Ack_Out_18({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_Ack_Out_19({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_Ack_Out_2({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_Ack_Out_20({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_Ack_Out_21({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_Ack_Out_22({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_Ack_Out_23({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_Ack_Out_24({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_Ack_Out_25({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_Ack_Out_26({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_Ack_Out_27({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_Ack_Out_28({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_Ack_Out_29({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_Ack_Out_3({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_Ack_Out_30({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_Ack_Out_31({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_Ack_Out_4({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_Ack_Out_5({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_Ack_Out_6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_Ack_Out_7({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_Ack_Out_8({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_Ack_Out_9({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_In_0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_In_1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_In_10({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_In_11({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_In_12({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_In_13({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_In_14({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_In_15({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_In_16({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_In_17({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_In_18({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_In_19({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_In_2({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_In_20({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_In_21({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_In_22({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_In_23({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_In_24({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_In_25({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_In_26({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_In_27({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_In_28({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_In_29({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_In_3({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_In_30({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_In_31({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_In_4({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_In_5({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_In_6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_In_7({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_In_8({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_In_9({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.Dbg_Trig_Out_0(NLW_U0_Dbg_Trig_Out_0_UNCONNECTED[0:7]),
.Dbg_Trig_Out_1(NLW_U0_Dbg_Trig_Out_1_UNCONNECTED[0:7]),
.Dbg_Trig_Out_10(NLW_U0_Dbg_Trig_Out_10_UNCONNECTED[0:7]),
.Dbg_Trig_Out_11(NLW_U0_Dbg_Trig_Out_11_UNCONNECTED[0:7]),
.Dbg_Trig_Out_12(NLW_U0_Dbg_Trig_Out_12_UNCONNECTED[0:7]),
.Dbg_Trig_Out_13(NLW_U0_Dbg_Trig_Out_13_UNCONNECTED[0:7]),
.Dbg_Trig_Out_14(NLW_U0_Dbg_Trig_Out_14_UNCONNECTED[0:7]),
.Dbg_Trig_Out_15(NLW_U0_Dbg_Trig_Out_15_UNCONNECTED[0:7]),
.Dbg_Trig_Out_16(NLW_U0_Dbg_Trig_Out_16_UNCONNECTED[0:7]),
.Dbg_Trig_Out_17(NLW_U0_Dbg_Trig_Out_17_UNCONNECTED[0:7]),
.Dbg_Trig_Out_18(NLW_U0_Dbg_Trig_Out_18_UNCONNECTED[0:7]),
.Dbg_Trig_Out_19(NLW_U0_Dbg_Trig_Out_19_UNCONNECTED[0:7]),
.Dbg_Trig_Out_2(NLW_U0_Dbg_Trig_Out_2_UNCONNECTED[0:7]),
.Dbg_Trig_Out_20(NLW_U0_Dbg_Trig_Out_20_UNCONNECTED[0:7]),
.Dbg_Trig_Out_21(NLW_U0_Dbg_Trig_Out_21_UNCONNECTED[0:7]),
.Dbg_Trig_Out_22(NLW_U0_Dbg_Trig_Out_22_UNCONNECTED[0:7]),
.Dbg_Trig_Out_23(NLW_U0_Dbg_Trig_Out_23_UNCONNECTED[0:7]),
.Dbg_Trig_Out_24(NLW_U0_Dbg_Trig_Out_24_UNCONNECTED[0:7]),
.Dbg_Trig_Out_25(NLW_U0_Dbg_Trig_Out_25_UNCONNECTED[0:7]),
.Dbg_Trig_Out_26(NLW_U0_Dbg_Trig_Out_26_UNCONNECTED[0:7]),
.Dbg_Trig_Out_27(NLW_U0_Dbg_Trig_Out_27_UNCONNECTED[0:7]),
.Dbg_Trig_Out_28(NLW_U0_Dbg_Trig_Out_28_UNCONNECTED[0:7]),
.Dbg_Trig_Out_29(NLW_U0_Dbg_Trig_Out_29_UNCONNECTED[0:7]),
.Dbg_Trig_Out_3(NLW_U0_Dbg_Trig_Out_3_UNCONNECTED[0:7]),
.Dbg_Trig_Out_30(NLW_U0_Dbg_Trig_Out_30_UNCONNECTED[0:7]),
.Dbg_Trig_Out_31(NLW_U0_Dbg_Trig_Out_31_UNCONNECTED[0:7]),
.Dbg_Trig_Out_4(NLW_U0_Dbg_Trig_Out_4_UNCONNECTED[0:7]),
.Dbg_Trig_Out_5(NLW_U0_Dbg_Trig_Out_5_UNCONNECTED[0:7]),
.Dbg_Trig_Out_6(NLW_U0_Dbg_Trig_Out_6_UNCONNECTED[0:7]),
.Dbg_Trig_Out_7(NLW_U0_Dbg_Trig_Out_7_UNCONNECTED[0:7]),
.Dbg_Trig_Out_8(NLW_U0_Dbg_Trig_Out_8_UNCONNECTED[0:7]),
.Dbg_Trig_Out_9(NLW_U0_Dbg_Trig_Out_9_UNCONNECTED[0:7]),
.Dbg_Update_0(Dbg_Update_0),
.Dbg_Update_1(NLW_U0_Dbg_Update_1_UNCONNECTED),
.Dbg_Update_10(NLW_U0_Dbg_Update_10_UNCONNECTED),
.Dbg_Update_11(NLW_U0_Dbg_Update_11_UNCONNECTED),
.Dbg_Update_12(NLW_U0_Dbg_Update_12_UNCONNECTED),
.Dbg_Update_13(NLW_U0_Dbg_Update_13_UNCONNECTED),
.Dbg_Update_14(NLW_U0_Dbg_Update_14_UNCONNECTED),
.Dbg_Update_15(NLW_U0_Dbg_Update_15_UNCONNECTED),
.Dbg_Update_16(NLW_U0_Dbg_Update_16_UNCONNECTED),
.Dbg_Update_17(NLW_U0_Dbg_Update_17_UNCONNECTED),
.Dbg_Update_18(NLW_U0_Dbg_Update_18_UNCONNECTED),
.Dbg_Update_19(NLW_U0_Dbg_Update_19_UNCONNECTED),
.Dbg_Update_2(NLW_U0_Dbg_Update_2_UNCONNECTED),
.Dbg_Update_20(NLW_U0_Dbg_Update_20_UNCONNECTED),
.Dbg_Update_21(NLW_U0_Dbg_Update_21_UNCONNECTED),
.Dbg_Update_22(NLW_U0_Dbg_Update_22_UNCONNECTED),
.Dbg_Update_23(NLW_U0_Dbg_Update_23_UNCONNECTED),
.Dbg_Update_24(NLW_U0_Dbg_Update_24_UNCONNECTED),
.Dbg_Update_25(NLW_U0_Dbg_Update_25_UNCONNECTED),
.Dbg_Update_26(NLW_U0_Dbg_Update_26_UNCONNECTED),
.Dbg_Update_27(NLW_U0_Dbg_Update_27_UNCONNECTED),
.Dbg_Update_28(NLW_U0_Dbg_Update_28_UNCONNECTED),
.Dbg_Update_29(NLW_U0_Dbg_Update_29_UNCONNECTED),
.Dbg_Update_3(NLW_U0_Dbg_Update_3_UNCONNECTED),
.Dbg_Update_30(NLW_U0_Dbg_Update_30_UNCONNECTED),
.Dbg_Update_31(NLW_U0_Dbg_Update_31_UNCONNECTED),
.Dbg_Update_4(NLW_U0_Dbg_Update_4_UNCONNECTED),
.Dbg_Update_5(NLW_U0_Dbg_Update_5_UNCONNECTED),
.Dbg_Update_6(NLW_U0_Dbg_Update_6_UNCONNECTED),
.Dbg_Update_7(NLW_U0_Dbg_Update_7_UNCONNECTED),
.Dbg_Update_8(NLW_U0_Dbg_Update_8_UNCONNECTED),
.Dbg_Update_9(NLW_U0_Dbg_Update_9_UNCONNECTED),
.Dbg_WDATA_0(NLW_U0_Dbg_WDATA_0_UNCONNECTED[31:0]),
.Dbg_WDATA_1(NLW_U0_Dbg_WDATA_1_UNCONNECTED[31:0]),
.Dbg_WDATA_10(NLW_U0_Dbg_WDATA_10_UNCONNECTED[31:0]),
.Dbg_WDATA_11(NLW_U0_Dbg_WDATA_11_UNCONNECTED[31:0]),
.Dbg_WDATA_12(NLW_U0_Dbg_WDATA_12_UNCONNECTED[31:0]),
.Dbg_WDATA_13(NLW_U0_Dbg_WDATA_13_UNCONNECTED[31:0]),
.Dbg_WDATA_14(NLW_U0_Dbg_WDATA_14_UNCONNECTED[31:0]),
.Dbg_WDATA_15(NLW_U0_Dbg_WDATA_15_UNCONNECTED[31:0]),
.Dbg_WDATA_16(NLW_U0_Dbg_WDATA_16_UNCONNECTED[31:0]),
.Dbg_WDATA_17(NLW_U0_Dbg_WDATA_17_UNCONNECTED[31:0]),
.Dbg_WDATA_18(NLW_U0_Dbg_WDATA_18_UNCONNECTED[31:0]),
.Dbg_WDATA_19(NLW_U0_Dbg_WDATA_19_UNCONNECTED[31:0]),
.Dbg_WDATA_2(NLW_U0_Dbg_WDATA_2_UNCONNECTED[31:0]),
.Dbg_WDATA_20(NLW_U0_Dbg_WDATA_20_UNCONNECTED[31:0]),
.Dbg_WDATA_21(NLW_U0_Dbg_WDATA_21_UNCONNECTED[31:0]),
.Dbg_WDATA_22(NLW_U0_Dbg_WDATA_22_UNCONNECTED[31:0]),
.Dbg_WDATA_23(NLW_U0_Dbg_WDATA_23_UNCONNECTED[31:0]),
.Dbg_WDATA_24(NLW_U0_Dbg_WDATA_24_UNCONNECTED[31:0]),
.Dbg_WDATA_25(NLW_U0_Dbg_WDATA_25_UNCONNECTED[31:0]),
.Dbg_WDATA_26(NLW_U0_Dbg_WDATA_26_UNCONNECTED[31:0]),
.Dbg_WDATA_27(NLW_U0_Dbg_WDATA_27_UNCONNECTED[31:0]),
.Dbg_WDATA_28(NLW_U0_Dbg_WDATA_28_UNCONNECTED[31:0]),
.Dbg_WDATA_29(NLW_U0_Dbg_WDATA_29_UNCONNECTED[31:0]),
.Dbg_WDATA_3(NLW_U0_Dbg_WDATA_3_UNCONNECTED[31:0]),
.Dbg_WDATA_30(NLW_U0_Dbg_WDATA_30_UNCONNECTED[31:0]),
.Dbg_WDATA_31(NLW_U0_Dbg_WDATA_31_UNCONNECTED[31:0]),
.Dbg_WDATA_4(NLW_U0_Dbg_WDATA_4_UNCONNECTED[31:0]),
.Dbg_WDATA_5(NLW_U0_Dbg_WDATA_5_UNCONNECTED[31:0]),
.Dbg_WDATA_6(NLW_U0_Dbg_WDATA_6_UNCONNECTED[31:0]),
.Dbg_WDATA_7(NLW_U0_Dbg_WDATA_7_UNCONNECTED[31:0]),
.Dbg_WDATA_8(NLW_U0_Dbg_WDATA_8_UNCONNECTED[31:0]),
.Dbg_WDATA_9(NLW_U0_Dbg_WDATA_9_UNCONNECTED[31:0]),
.Dbg_WREADY_0(1'b0),
.Dbg_WREADY_1(1'b0),
.Dbg_WREADY_10(1'b0),
.Dbg_WREADY_11(1'b0),
.Dbg_WREADY_12(1'b0),
.Dbg_WREADY_13(1'b0),
.Dbg_WREADY_14(1'b0),
.Dbg_WREADY_15(1'b0),
.Dbg_WREADY_16(1'b0),
.Dbg_WREADY_17(1'b0),
.Dbg_WREADY_18(1'b0),
.Dbg_WREADY_19(1'b0),
.Dbg_WREADY_2(1'b0),
.Dbg_WREADY_20(1'b0),
.Dbg_WREADY_21(1'b0),
.Dbg_WREADY_22(1'b0),
.Dbg_WREADY_23(1'b0),
.Dbg_WREADY_24(1'b0),
.Dbg_WREADY_25(1'b0),
.Dbg_WREADY_26(1'b0),
.Dbg_WREADY_27(1'b0),
.Dbg_WREADY_28(1'b0),
.Dbg_WREADY_29(1'b0),
.Dbg_WREADY_3(1'b0),
.Dbg_WREADY_30(1'b0),
.Dbg_WREADY_31(1'b0),
.Dbg_WREADY_4(1'b0),
.Dbg_WREADY_5(1'b0),
.Dbg_WREADY_6(1'b0),
.Dbg_WREADY_7(1'b0),
.Dbg_WREADY_8(1'b0),
.Dbg_WREADY_9(1'b0),
.Dbg_WVALID_0(NLW_U0_Dbg_WVALID_0_UNCONNECTED),
.Dbg_WVALID_1(NLW_U0_Dbg_WVALID_1_UNCONNECTED),
.Dbg_WVALID_10(NLW_U0_Dbg_WVALID_10_UNCONNECTED),
.Dbg_WVALID_11(NLW_U0_Dbg_WVALID_11_UNCONNECTED),
.Dbg_WVALID_12(NLW_U0_Dbg_WVALID_12_UNCONNECTED),
.Dbg_WVALID_13(NLW_U0_Dbg_WVALID_13_UNCONNECTED),
.Dbg_WVALID_14(NLW_U0_Dbg_WVALID_14_UNCONNECTED),
.Dbg_WVALID_15(NLW_U0_Dbg_WVALID_15_UNCONNECTED),
.Dbg_WVALID_16(NLW_U0_Dbg_WVALID_16_UNCONNECTED),
.Dbg_WVALID_17(NLW_U0_Dbg_WVALID_17_UNCONNECTED),
.Dbg_WVALID_18(NLW_U0_Dbg_WVALID_18_UNCONNECTED),
.Dbg_WVALID_19(NLW_U0_Dbg_WVALID_19_UNCONNECTED),
.Dbg_WVALID_2(NLW_U0_Dbg_WVALID_2_UNCONNECTED),
.Dbg_WVALID_20(NLW_U0_Dbg_WVALID_20_UNCONNECTED),
.Dbg_WVALID_21(NLW_U0_Dbg_WVALID_21_UNCONNECTED),
.Dbg_WVALID_22(NLW_U0_Dbg_WVALID_22_UNCONNECTED),
.Dbg_WVALID_23(NLW_U0_Dbg_WVALID_23_UNCONNECTED),
.Dbg_WVALID_24(NLW_U0_Dbg_WVALID_24_UNCONNECTED),
.Dbg_WVALID_25(NLW_U0_Dbg_WVALID_25_UNCONNECTED),
.Dbg_WVALID_26(NLW_U0_Dbg_WVALID_26_UNCONNECTED),
.Dbg_WVALID_27(NLW_U0_Dbg_WVALID_27_UNCONNECTED),
.Dbg_WVALID_28(NLW_U0_Dbg_WVALID_28_UNCONNECTED),
.Dbg_WVALID_29(NLW_U0_Dbg_WVALID_29_UNCONNECTED),
.Dbg_WVALID_3(NLW_U0_Dbg_WVALID_3_UNCONNECTED),
.Dbg_WVALID_30(NLW_U0_Dbg_WVALID_30_UNCONNECTED),
.Dbg_WVALID_31(NLW_U0_Dbg_WVALID_31_UNCONNECTED),
.Dbg_WVALID_4(NLW_U0_Dbg_WVALID_4_UNCONNECTED),
.Dbg_WVALID_5(NLW_U0_Dbg_WVALID_5_UNCONNECTED),
.Dbg_WVALID_6(NLW_U0_Dbg_WVALID_6_UNCONNECTED),
.Dbg_WVALID_7(NLW_U0_Dbg_WVALID_7_UNCONNECTED),
.Dbg_WVALID_8(NLW_U0_Dbg_WVALID_8_UNCONNECTED),
.Dbg_WVALID_9(NLW_U0_Dbg_WVALID_9_UNCONNECTED),
.Debug_SYS_Rst(Debug_SYS_Rst),
.Ext_BRK(NLW_U0_Ext_BRK_UNCONNECTED),
.Ext_JTAG_CAPTURE(NLW_U0_Ext_JTAG_CAPTURE_UNCONNECTED),
.Ext_JTAG_DRCK(NLW_U0_Ext_JTAG_DRCK_UNCONNECTED),
.Ext_JTAG_RESET(NLW_U0_Ext_JTAG_RESET_UNCONNECTED),
.Ext_JTAG_SEL(NLW_U0_Ext_JTAG_SEL_UNCONNECTED),
.Ext_JTAG_SHIFT(NLW_U0_Ext_JTAG_SHIFT_UNCONNECTED),
.Ext_JTAG_TDI(NLW_U0_Ext_JTAG_TDI_UNCONNECTED),
.Ext_JTAG_TDO(1'b0),
.Ext_JTAG_UPDATE(NLW_U0_Ext_JTAG_UPDATE_UNCONNECTED),
.Ext_NM_BRK(NLW_U0_Ext_NM_BRK_UNCONNECTED),
.Interrupt(NLW_U0_Interrupt_UNCONNECTED),
.LMB_Addr_Strobe_0(NLW_U0_LMB_Addr_Strobe_0_UNCONNECTED),
.LMB_Addr_Strobe_1(NLW_U0_LMB_Addr_Strobe_1_UNCONNECTED),
.LMB_Addr_Strobe_10(NLW_U0_LMB_Addr_Strobe_10_UNCONNECTED),
.LMB_Addr_Strobe_11(NLW_U0_LMB_Addr_Strobe_11_UNCONNECTED),
.LMB_Addr_Strobe_12(NLW_U0_LMB_Addr_Strobe_12_UNCONNECTED),
.LMB_Addr_Strobe_13(NLW_U0_LMB_Addr_Strobe_13_UNCONNECTED),
.LMB_Addr_Strobe_14(NLW_U0_LMB_Addr_Strobe_14_UNCONNECTED),
.LMB_Addr_Strobe_15(NLW_U0_LMB_Addr_Strobe_15_UNCONNECTED),
.LMB_Addr_Strobe_16(NLW_U0_LMB_Addr_Strobe_16_UNCONNECTED),
.LMB_Addr_Strobe_17(NLW_U0_LMB_Addr_Strobe_17_UNCONNECTED),
.LMB_Addr_Strobe_18(NLW_U0_LMB_Addr_Strobe_18_UNCONNECTED),
.LMB_Addr_Strobe_19(NLW_U0_LMB_Addr_Strobe_19_UNCONNECTED),
.LMB_Addr_Strobe_2(NLW_U0_LMB_Addr_Strobe_2_UNCONNECTED),
.LMB_Addr_Strobe_20(NLW_U0_LMB_Addr_Strobe_20_UNCONNECTED),
.LMB_Addr_Strobe_21(NLW_U0_LMB_Addr_Strobe_21_UNCONNECTED),
.LMB_Addr_Strobe_22(NLW_U0_LMB_Addr_Strobe_22_UNCONNECTED),
.LMB_Addr_Strobe_23(NLW_U0_LMB_Addr_Strobe_23_UNCONNECTED),
.LMB_Addr_Strobe_24(NLW_U0_LMB_Addr_Strobe_24_UNCONNECTED),
.LMB_Addr_Strobe_25(NLW_U0_LMB_Addr_Strobe_25_UNCONNECTED),
.LMB_Addr_Strobe_26(NLW_U0_LMB_Addr_Strobe_26_UNCONNECTED),
.LMB_Addr_Strobe_27(NLW_U0_LMB_Addr_Strobe_27_UNCONNECTED),
.LMB_Addr_Strobe_28(NLW_U0_LMB_Addr_Strobe_28_UNCONNECTED),
.LMB_Addr_Strobe_29(NLW_U0_LMB_Addr_Strobe_29_UNCONNECTED),
.LMB_Addr_Strobe_3(NLW_U0_LMB_Addr_Strobe_3_UNCONNECTED),
.LMB_Addr_Strobe_30(NLW_U0_LMB_Addr_Strobe_30_UNCONNECTED),
.LMB_Addr_Strobe_31(NLW_U0_LMB_Addr_Strobe_31_UNCONNECTED),
.LMB_Addr_Strobe_4(NLW_U0_LMB_Addr_Strobe_4_UNCONNECTED),
.LMB_Addr_Strobe_5(NLW_U0_LMB_Addr_Strobe_5_UNCONNECTED),
.LMB_Addr_Strobe_6(NLW_U0_LMB_Addr_Strobe_6_UNCONNECTED),
.LMB_Addr_Strobe_7(NLW_U0_LMB_Addr_Strobe_7_UNCONNECTED),
.LMB_Addr_Strobe_8(NLW_U0_LMB_Addr_Strobe_8_UNCONNECTED),
.LMB_Addr_Strobe_9(NLW_U0_LMB_Addr_Strobe_9_UNCONNECTED),
.LMB_Byte_Enable_0(NLW_U0_LMB_Byte_Enable_0_UNCONNECTED[0:3]),
.LMB_Byte_Enable_1(NLW_U0_LMB_Byte_Enable_1_UNCONNECTED[0:3]),
.LMB_Byte_Enable_10(NLW_U0_LMB_Byte_Enable_10_UNCONNECTED[0:3]),
.LMB_Byte_Enable_11(NLW_U0_LMB_Byte_Enable_11_UNCONNECTED[0:3]),
.LMB_Byte_Enable_12(NLW_U0_LMB_Byte_Enable_12_UNCONNECTED[0:3]),
.LMB_Byte_Enable_13(NLW_U0_LMB_Byte_Enable_13_UNCONNECTED[0:3]),
.LMB_Byte_Enable_14(NLW_U0_LMB_Byte_Enable_14_UNCONNECTED[0:3]),
.LMB_Byte_Enable_15(NLW_U0_LMB_Byte_Enable_15_UNCONNECTED[0:3]),
.LMB_Byte_Enable_16(NLW_U0_LMB_Byte_Enable_16_UNCONNECTED[0:3]),
.LMB_Byte_Enable_17(NLW_U0_LMB_Byte_Enable_17_UNCONNECTED[0:3]),
.LMB_Byte_Enable_18(NLW_U0_LMB_Byte_Enable_18_UNCONNECTED[0:3]),
.LMB_Byte_Enable_19(NLW_U0_LMB_Byte_Enable_19_UNCONNECTED[0:3]),
.LMB_Byte_Enable_2(NLW_U0_LMB_Byte_Enable_2_UNCONNECTED[0:3]),
.LMB_Byte_Enable_20(NLW_U0_LMB_Byte_Enable_20_UNCONNECTED[0:3]),
.LMB_Byte_Enable_21(NLW_U0_LMB_Byte_Enable_21_UNCONNECTED[0:3]),
.LMB_Byte_Enable_22(NLW_U0_LMB_Byte_Enable_22_UNCONNECTED[0:3]),
.LMB_Byte_Enable_23(NLW_U0_LMB_Byte_Enable_23_UNCONNECTED[0:3]),
.LMB_Byte_Enable_24(NLW_U0_LMB_Byte_Enable_24_UNCONNECTED[0:3]),
.LMB_Byte_Enable_25(NLW_U0_LMB_Byte_Enable_25_UNCONNECTED[0:3]),
.LMB_Byte_Enable_26(NLW_U0_LMB_Byte_Enable_26_UNCONNECTED[0:3]),
.LMB_Byte_Enable_27(NLW_U0_LMB_Byte_Enable_27_UNCONNECTED[0:3]),
.LMB_Byte_Enable_28(NLW_U0_LMB_Byte_Enable_28_UNCONNECTED[0:3]),
.LMB_Byte_Enable_29(NLW_U0_LMB_Byte_Enable_29_UNCONNECTED[0:3]),
.LMB_Byte_Enable_3(NLW_U0_LMB_Byte_Enable_3_UNCONNECTED[0:3]),
.LMB_Byte_Enable_30(NLW_U0_LMB_Byte_Enable_30_UNCONNECTED[0:3]),
.LMB_Byte_Enable_31(NLW_U0_LMB_Byte_Enable_31_UNCONNECTED[0:3]),
.LMB_Byte_Enable_4(NLW_U0_LMB_Byte_Enable_4_UNCONNECTED[0:3]),
.LMB_Byte_Enable_5(NLW_U0_LMB_Byte_Enable_5_UNCONNECTED[0:3]),
.LMB_Byte_Enable_6(NLW_U0_LMB_Byte_Enable_6_UNCONNECTED[0:3]),
.LMB_Byte_Enable_7(NLW_U0_LMB_Byte_Enable_7_UNCONNECTED[0:3]),
.LMB_Byte_Enable_8(NLW_U0_LMB_Byte_Enable_8_UNCONNECTED[0:3]),
.LMB_Byte_Enable_9(NLW_U0_LMB_Byte_Enable_9_UNCONNECTED[0:3]),
.LMB_CE_0(1'b0),
.LMB_CE_1(1'b0),
.LMB_CE_10(1'b0),
.LMB_CE_11(1'b0),
.LMB_CE_12(1'b0),
.LMB_CE_13(1'b0),
.LMB_CE_14(1'b0),
.LMB_CE_15(1'b0),
.LMB_CE_16(1'b0),
.LMB_CE_17(1'b0),
.LMB_CE_18(1'b0),
.LMB_CE_19(1'b0),
.LMB_CE_2(1'b0),
.LMB_CE_20(1'b0),
.LMB_CE_21(1'b0),
.LMB_CE_22(1'b0),
.LMB_CE_23(1'b0),
.LMB_CE_24(1'b0),
.LMB_CE_25(1'b0),
.LMB_CE_26(1'b0),
.LMB_CE_27(1'b0),
.LMB_CE_28(1'b0),
.LMB_CE_29(1'b0),
.LMB_CE_3(1'b0),
.LMB_CE_30(1'b0),
.LMB_CE_31(1'b0),
.LMB_CE_4(1'b0),
.LMB_CE_5(1'b0),
.LMB_CE_6(1'b0),
.LMB_CE_7(1'b0),
.LMB_CE_8(1'b0),
.LMB_CE_9(1'b0),
.LMB_Data_Addr_0(NLW_U0_LMB_Data_Addr_0_UNCONNECTED[0:31]),
.LMB_Data_Addr_1(NLW_U0_LMB_Data_Addr_1_UNCONNECTED[0:31]),
.LMB_Data_Addr_10(NLW_U0_LMB_Data_Addr_10_UNCONNECTED[0:31]),
.LMB_Data_Addr_11(NLW_U0_LMB_Data_Addr_11_UNCONNECTED[0:31]),
.LMB_Data_Addr_12(NLW_U0_LMB_Data_Addr_12_UNCONNECTED[0:31]),
.LMB_Data_Addr_13(NLW_U0_LMB_Data_Addr_13_UNCONNECTED[0:31]),
.LMB_Data_Addr_14(NLW_U0_LMB_Data_Addr_14_UNCONNECTED[0:31]),
.LMB_Data_Addr_15(NLW_U0_LMB_Data_Addr_15_UNCONNECTED[0:31]),
.LMB_Data_Addr_16(NLW_U0_LMB_Data_Addr_16_UNCONNECTED[0:31]),
.LMB_Data_Addr_17(NLW_U0_LMB_Data_Addr_17_UNCONNECTED[0:31]),
.LMB_Data_Addr_18(NLW_U0_LMB_Data_Addr_18_UNCONNECTED[0:31]),
.LMB_Data_Addr_19(NLW_U0_LMB_Data_Addr_19_UNCONNECTED[0:31]),
.LMB_Data_Addr_2(NLW_U0_LMB_Data_Addr_2_UNCONNECTED[0:31]),
.LMB_Data_Addr_20(NLW_U0_LMB_Data_Addr_20_UNCONNECTED[0:31]),
.LMB_Data_Addr_21(NLW_U0_LMB_Data_Addr_21_UNCONNECTED[0:31]),
.LMB_Data_Addr_22(NLW_U0_LMB_Data_Addr_22_UNCONNECTED[0:31]),
.LMB_Data_Addr_23(NLW_U0_LMB_Data_Addr_23_UNCONNECTED[0:31]),
.LMB_Data_Addr_24(NLW_U0_LMB_Data_Addr_24_UNCONNECTED[0:31]),
.LMB_Data_Addr_25(NLW_U0_LMB_Data_Addr_25_UNCONNECTED[0:31]),
.LMB_Data_Addr_26(NLW_U0_LMB_Data_Addr_26_UNCONNECTED[0:31]),
.LMB_Data_Addr_27(NLW_U0_LMB_Data_Addr_27_UNCONNECTED[0:31]),
.LMB_Data_Addr_28(NLW_U0_LMB_Data_Addr_28_UNCONNECTED[0:31]),
.LMB_Data_Addr_29(NLW_U0_LMB_Data_Addr_29_UNCONNECTED[0:31]),
.LMB_Data_Addr_3(NLW_U0_LMB_Data_Addr_3_UNCONNECTED[0:31]),
.LMB_Data_Addr_30(NLW_U0_LMB_Data_Addr_30_UNCONNECTED[0:31]),
.LMB_Data_Addr_31(NLW_U0_LMB_Data_Addr_31_UNCONNECTED[0:31]),
.LMB_Data_Addr_4(NLW_U0_LMB_Data_Addr_4_UNCONNECTED[0:31]),
.LMB_Data_Addr_5(NLW_U0_LMB_Data_Addr_5_UNCONNECTED[0:31]),
.LMB_Data_Addr_6(NLW_U0_LMB_Data_Addr_6_UNCONNECTED[0:31]),
.LMB_Data_Addr_7(NLW_U0_LMB_Data_Addr_7_UNCONNECTED[0:31]),
.LMB_Data_Addr_8(NLW_U0_LMB_Data_Addr_8_UNCONNECTED[0:31]),
.LMB_Data_Addr_9(NLW_U0_LMB_Data_Addr_9_UNCONNECTED[0:31]),
.LMB_Data_Read_0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB_Data_Read_1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB_Data_Read_10({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB_Data_Read_11({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB_Data_Read_12({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB_Data_Read_13({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB_Data_Read_14({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB_Data_Read_15({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB_Data_Read_16({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB_Data_Read_17({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB_Data_Read_18({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB_Data_Read_19({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB_Data_Read_2({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB_Data_Read_20({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB_Data_Read_21({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB_Data_Read_22({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB_Data_Read_23({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB_Data_Read_24({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB_Data_Read_25({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB_Data_Read_26({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB_Data_Read_27({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB_Data_Read_28({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB_Data_Read_29({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB_Data_Read_3({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB_Data_Read_30({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB_Data_Read_31({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB_Data_Read_4({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB_Data_Read_5({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB_Data_Read_6({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB_Data_Read_7({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB_Data_Read_8({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB_Data_Read_9({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB_Data_Write_0(NLW_U0_LMB_Data_Write_0_UNCONNECTED[0:31]),
.LMB_Data_Write_1(NLW_U0_LMB_Data_Write_1_UNCONNECTED[0:31]),
.LMB_Data_Write_10(NLW_U0_LMB_Data_Write_10_UNCONNECTED[0:31]),
.LMB_Data_Write_11(NLW_U0_LMB_Data_Write_11_UNCONNECTED[0:31]),
.LMB_Data_Write_12(NLW_U0_LMB_Data_Write_12_UNCONNECTED[0:31]),
.LMB_Data_Write_13(NLW_U0_LMB_Data_Write_13_UNCONNECTED[0:31]),
.LMB_Data_Write_14(NLW_U0_LMB_Data_Write_14_UNCONNECTED[0:31]),
.LMB_Data_Write_15(NLW_U0_LMB_Data_Write_15_UNCONNECTED[0:31]),
.LMB_Data_Write_16(NLW_U0_LMB_Data_Write_16_UNCONNECTED[0:31]),
.LMB_Data_Write_17(NLW_U0_LMB_Data_Write_17_UNCONNECTED[0:31]),
.LMB_Data_Write_18(NLW_U0_LMB_Data_Write_18_UNCONNECTED[0:31]),
.LMB_Data_Write_19(NLW_U0_LMB_Data_Write_19_UNCONNECTED[0:31]),
.LMB_Data_Write_2(NLW_U0_LMB_Data_Write_2_UNCONNECTED[0:31]),
.LMB_Data_Write_20(NLW_U0_LMB_Data_Write_20_UNCONNECTED[0:31]),
.LMB_Data_Write_21(NLW_U0_LMB_Data_Write_21_UNCONNECTED[0:31]),
.LMB_Data_Write_22(NLW_U0_LMB_Data_Write_22_UNCONNECTED[0:31]),
.LMB_Data_Write_23(NLW_U0_LMB_Data_Write_23_UNCONNECTED[0:31]),
.LMB_Data_Write_24(NLW_U0_LMB_Data_Write_24_UNCONNECTED[0:31]),
.LMB_Data_Write_25(NLW_U0_LMB_Data_Write_25_UNCONNECTED[0:31]),
.LMB_Data_Write_26(NLW_U0_LMB_Data_Write_26_UNCONNECTED[0:31]),
.LMB_Data_Write_27(NLW_U0_LMB_Data_Write_27_UNCONNECTED[0:31]),
.LMB_Data_Write_28(NLW_U0_LMB_Data_Write_28_UNCONNECTED[0:31]),
.LMB_Data_Write_29(NLW_U0_LMB_Data_Write_29_UNCONNECTED[0:31]),
.LMB_Data_Write_3(NLW_U0_LMB_Data_Write_3_UNCONNECTED[0:31]),
.LMB_Data_Write_30(NLW_U0_LMB_Data_Write_30_UNCONNECTED[0:31]),
.LMB_Data_Write_31(NLW_U0_LMB_Data_Write_31_UNCONNECTED[0:31]),
.LMB_Data_Write_4(NLW_U0_LMB_Data_Write_4_UNCONNECTED[0:31]),
.LMB_Data_Write_5(NLW_U0_LMB_Data_Write_5_UNCONNECTED[0:31]),
.LMB_Data_Write_6(NLW_U0_LMB_Data_Write_6_UNCONNECTED[0:31]),
.LMB_Data_Write_7(NLW_U0_LMB_Data_Write_7_UNCONNECTED[0:31]),
.LMB_Data_Write_8(NLW_U0_LMB_Data_Write_8_UNCONNECTED[0:31]),
.LMB_Data_Write_9(NLW_U0_LMB_Data_Write_9_UNCONNECTED[0:31]),
.LMB_Read_Strobe_0(NLW_U0_LMB_Read_Strobe_0_UNCONNECTED),
.LMB_Read_Strobe_1(NLW_U0_LMB_Read_Strobe_1_UNCONNECTED),
.LMB_Read_Strobe_10(NLW_U0_LMB_Read_Strobe_10_UNCONNECTED),
.LMB_Read_Strobe_11(NLW_U0_LMB_Read_Strobe_11_UNCONNECTED),
.LMB_Read_Strobe_12(NLW_U0_LMB_Read_Strobe_12_UNCONNECTED),
.LMB_Read_Strobe_13(NLW_U0_LMB_Read_Strobe_13_UNCONNECTED),
.LMB_Read_Strobe_14(NLW_U0_LMB_Read_Strobe_14_UNCONNECTED),
.LMB_Read_Strobe_15(NLW_U0_LMB_Read_Strobe_15_UNCONNECTED),
.LMB_Read_Strobe_16(NLW_U0_LMB_Read_Strobe_16_UNCONNECTED),
.LMB_Read_Strobe_17(NLW_U0_LMB_Read_Strobe_17_UNCONNECTED),
.LMB_Read_Strobe_18(NLW_U0_LMB_Read_Strobe_18_UNCONNECTED),
.LMB_Read_Strobe_19(NLW_U0_LMB_Read_Strobe_19_UNCONNECTED),
.LMB_Read_Strobe_2(NLW_U0_LMB_Read_Strobe_2_UNCONNECTED),
.LMB_Read_Strobe_20(NLW_U0_LMB_Read_Strobe_20_UNCONNECTED),
.LMB_Read_Strobe_21(NLW_U0_LMB_Read_Strobe_21_UNCONNECTED),
.LMB_Read_Strobe_22(NLW_U0_LMB_Read_Strobe_22_UNCONNECTED),
.LMB_Read_Strobe_23(NLW_U0_LMB_Read_Strobe_23_UNCONNECTED),
.LMB_Read_Strobe_24(NLW_U0_LMB_Read_Strobe_24_UNCONNECTED),
.LMB_Read_Strobe_25(NLW_U0_LMB_Read_Strobe_25_UNCONNECTED),
.LMB_Read_Strobe_26(NLW_U0_LMB_Read_Strobe_26_UNCONNECTED),
.LMB_Read_Strobe_27(NLW_U0_LMB_Read_Strobe_27_UNCONNECTED),
.LMB_Read_Strobe_28(NLW_U0_LMB_Read_Strobe_28_UNCONNECTED),
.LMB_Read_Strobe_29(NLW_U0_LMB_Read_Strobe_29_UNCONNECTED),
.LMB_Read_Strobe_3(NLW_U0_LMB_Read_Strobe_3_UNCONNECTED),
.LMB_Read_Strobe_30(NLW_U0_LMB_Read_Strobe_30_UNCONNECTED),
.LMB_Read_Strobe_31(NLW_U0_LMB_Read_Strobe_31_UNCONNECTED),
.LMB_Read_Strobe_4(NLW_U0_LMB_Read_Strobe_4_UNCONNECTED),
.LMB_Read_Strobe_5(NLW_U0_LMB_Read_Strobe_5_UNCONNECTED),
.LMB_Read_Strobe_6(NLW_U0_LMB_Read_Strobe_6_UNCONNECTED),
.LMB_Read_Strobe_7(NLW_U0_LMB_Read_Strobe_7_UNCONNECTED),
.LMB_Read_Strobe_8(NLW_U0_LMB_Read_Strobe_8_UNCONNECTED),
.LMB_Read_Strobe_9(NLW_U0_LMB_Read_Strobe_9_UNCONNECTED),
.LMB_Ready_0(1'b0),
.LMB_Ready_1(1'b0),
.LMB_Ready_10(1'b0),
.LMB_Ready_11(1'b0),
.LMB_Ready_12(1'b0),
.LMB_Ready_13(1'b0),
.LMB_Ready_14(1'b0),
.LMB_Ready_15(1'b0),
.LMB_Ready_16(1'b0),
.LMB_Ready_17(1'b0),
.LMB_Ready_18(1'b0),
.LMB_Ready_19(1'b0),
.LMB_Ready_2(1'b0),
.LMB_Ready_20(1'b0),
.LMB_Ready_21(1'b0),
.LMB_Ready_22(1'b0),
.LMB_Ready_23(1'b0),
.LMB_Ready_24(1'b0),
.LMB_Ready_25(1'b0),
.LMB_Ready_26(1'b0),
.LMB_Ready_27(1'b0),
.LMB_Ready_28(1'b0),
.LMB_Ready_29(1'b0),
.LMB_Ready_3(1'b0),
.LMB_Ready_30(1'b0),
.LMB_Ready_31(1'b0),
.LMB_Ready_4(1'b0),
.LMB_Ready_5(1'b0),
.LMB_Ready_6(1'b0),
.LMB_Ready_7(1'b0),
.LMB_Ready_8(1'b0),
.LMB_Ready_9(1'b0),
.LMB_UE_0(1'b0),
.LMB_UE_1(1'b0),
.LMB_UE_10(1'b0),
.LMB_UE_11(1'b0),
.LMB_UE_12(1'b0),
.LMB_UE_13(1'b0),
.LMB_UE_14(1'b0),
.LMB_UE_15(1'b0),
.LMB_UE_16(1'b0),
.LMB_UE_17(1'b0),
.LMB_UE_18(1'b0),
.LMB_UE_19(1'b0),
.LMB_UE_2(1'b0),
.LMB_UE_20(1'b0),
.LMB_UE_21(1'b0),
.LMB_UE_22(1'b0),
.LMB_UE_23(1'b0),
.LMB_UE_24(1'b0),
.LMB_UE_25(1'b0),
.LMB_UE_26(1'b0),
.LMB_UE_27(1'b0),
.LMB_UE_28(1'b0),
.LMB_UE_29(1'b0),
.LMB_UE_3(1'b0),
.LMB_UE_30(1'b0),
.LMB_UE_31(1'b0),
.LMB_UE_4(1'b0),
.LMB_UE_5(1'b0),
.LMB_UE_6(1'b0),
.LMB_UE_7(1'b0),
.LMB_UE_8(1'b0),
.LMB_UE_9(1'b0),
.LMB_Wait_0(1'b0),
.LMB_Wait_1(1'b0),
.LMB_Wait_10(1'b0),
.LMB_Wait_11(1'b0),
.LMB_Wait_12(1'b0),
.LMB_Wait_13(1'b0),
.LMB_Wait_14(1'b0),
.LMB_Wait_15(1'b0),
.LMB_Wait_16(1'b0),
.LMB_Wait_17(1'b0),
.LMB_Wait_18(1'b0),
.LMB_Wait_19(1'b0),
.LMB_Wait_2(1'b0),
.LMB_Wait_20(1'b0),
.LMB_Wait_21(1'b0),
.LMB_Wait_22(1'b0),
.LMB_Wait_23(1'b0),
.LMB_Wait_24(1'b0),
.LMB_Wait_25(1'b0),
.LMB_Wait_26(1'b0),
.LMB_Wait_27(1'b0),
.LMB_Wait_28(1'b0),
.LMB_Wait_29(1'b0),
.LMB_Wait_3(1'b0),
.LMB_Wait_30(1'b0),
.LMB_Wait_31(1'b0),
.LMB_Wait_4(1'b0),
.LMB_Wait_5(1'b0),
.LMB_Wait_6(1'b0),
.LMB_Wait_7(1'b0),
.LMB_Wait_8(1'b0),
.LMB_Wait_9(1'b0),
.LMB_Write_Strobe_0(NLW_U0_LMB_Write_Strobe_0_UNCONNECTED),
.LMB_Write_Strobe_1(NLW_U0_LMB_Write_Strobe_1_UNCONNECTED),
.LMB_Write_Strobe_10(NLW_U0_LMB_Write_Strobe_10_UNCONNECTED),
.LMB_Write_Strobe_11(NLW_U0_LMB_Write_Strobe_11_UNCONNECTED),
.LMB_Write_Strobe_12(NLW_U0_LMB_Write_Strobe_12_UNCONNECTED),
.LMB_Write_Strobe_13(NLW_U0_LMB_Write_Strobe_13_UNCONNECTED),
.LMB_Write_Strobe_14(NLW_U0_LMB_Write_Strobe_14_UNCONNECTED),
.LMB_Write_Strobe_15(NLW_U0_LMB_Write_Strobe_15_UNCONNECTED),
.LMB_Write_Strobe_16(NLW_U0_LMB_Write_Strobe_16_UNCONNECTED),
.LMB_Write_Strobe_17(NLW_U0_LMB_Write_Strobe_17_UNCONNECTED),
.LMB_Write_Strobe_18(NLW_U0_LMB_Write_Strobe_18_UNCONNECTED),
.LMB_Write_Strobe_19(NLW_U0_LMB_Write_Strobe_19_UNCONNECTED),
.LMB_Write_Strobe_2(NLW_U0_LMB_Write_Strobe_2_UNCONNECTED),
.LMB_Write_Strobe_20(NLW_U0_LMB_Write_Strobe_20_UNCONNECTED),
.LMB_Write_Strobe_21(NLW_U0_LMB_Write_Strobe_21_UNCONNECTED),
.LMB_Write_Strobe_22(NLW_U0_LMB_Write_Strobe_22_UNCONNECTED),
.LMB_Write_Strobe_23(NLW_U0_LMB_Write_Strobe_23_UNCONNECTED),
.LMB_Write_Strobe_24(NLW_U0_LMB_Write_Strobe_24_UNCONNECTED),
.LMB_Write_Strobe_25(NLW_U0_LMB_Write_Strobe_25_UNCONNECTED),
.LMB_Write_Strobe_26(NLW_U0_LMB_Write_Strobe_26_UNCONNECTED),
.LMB_Write_Strobe_27(NLW_U0_LMB_Write_Strobe_27_UNCONNECTED),
.LMB_Write_Strobe_28(NLW_U0_LMB_Write_Strobe_28_UNCONNECTED),
.LMB_Write_Strobe_29(NLW_U0_LMB_Write_Strobe_29_UNCONNECTED),
.LMB_Write_Strobe_3(NLW_U0_LMB_Write_Strobe_3_UNCONNECTED),
.LMB_Write_Strobe_30(NLW_U0_LMB_Write_Strobe_30_UNCONNECTED),
.LMB_Write_Strobe_31(NLW_U0_LMB_Write_Strobe_31_UNCONNECTED),
.LMB_Write_Strobe_4(NLW_U0_LMB_Write_Strobe_4_UNCONNECTED),
.LMB_Write_Strobe_5(NLW_U0_LMB_Write_Strobe_5_UNCONNECTED),
.LMB_Write_Strobe_6(NLW_U0_LMB_Write_Strobe_6_UNCONNECTED),
.LMB_Write_Strobe_7(NLW_U0_LMB_Write_Strobe_7_UNCONNECTED),
.LMB_Write_Strobe_8(NLW_U0_LMB_Write_Strobe_8_UNCONNECTED),
.LMB_Write_Strobe_9(NLW_U0_LMB_Write_Strobe_9_UNCONNECTED),
.M_AXIS_ACLK(1'b0),
.M_AXIS_ARESETN(1'b0),
.M_AXIS_TDATA(NLW_U0_M_AXIS_TDATA_UNCONNECTED[31:0]),
.M_AXIS_TID(NLW_U0_M_AXIS_TID_UNCONNECTED[6:0]),
.M_AXIS_TREADY(1'b1),
.M_AXIS_TVALID(NLW_U0_M_AXIS_TVALID_UNCONNECTED),
.M_AXI_ACLK(1'b0),
.M_AXI_ARADDR(NLW_U0_M_AXI_ARADDR_UNCONNECTED[31:0]),
.M_AXI_ARBURST(NLW_U0_M_AXI_ARBURST_UNCONNECTED[1:0]),
.M_AXI_ARCACHE(NLW_U0_M_AXI_ARCACHE_UNCONNECTED[3:0]),
.M_AXI_ARESETN(1'b0),
.M_AXI_ARID(NLW_U0_M_AXI_ARID_UNCONNECTED[0]),
.M_AXI_ARLEN(NLW_U0_M_AXI_ARLEN_UNCONNECTED[7:0]),
.M_AXI_ARLOCK(NLW_U0_M_AXI_ARLOCK_UNCONNECTED),
.M_AXI_ARPROT(NLW_U0_M_AXI_ARPROT_UNCONNECTED[2:0]),
.M_AXI_ARQOS(NLW_U0_M_AXI_ARQOS_UNCONNECTED[3:0]),
.M_AXI_ARREADY(1'b0),
.M_AXI_ARSIZE(NLW_U0_M_AXI_ARSIZE_UNCONNECTED[2:0]),
.M_AXI_ARVALID(NLW_U0_M_AXI_ARVALID_UNCONNECTED),
.M_AXI_AWADDR(NLW_U0_M_AXI_AWADDR_UNCONNECTED[31:0]),
.M_AXI_AWBURST(NLW_U0_M_AXI_AWBURST_UNCONNECTED[1:0]),
.M_AXI_AWCACHE(NLW_U0_M_AXI_AWCACHE_UNCONNECTED[3:0]),
.M_AXI_AWID(NLW_U0_M_AXI_AWID_UNCONNECTED[0]),
.M_AXI_AWLEN(NLW_U0_M_AXI_AWLEN_UNCONNECTED[7:0]),
.M_AXI_AWLOCK(NLW_U0_M_AXI_AWLOCK_UNCONNECTED),
.M_AXI_AWPROT(NLW_U0_M_AXI_AWPROT_UNCONNECTED[2:0]),
.M_AXI_AWQOS(NLW_U0_M_AXI_AWQOS_UNCONNECTED[3:0]),
.M_AXI_AWREADY(1'b0),
.M_AXI_AWSIZE(NLW_U0_M_AXI_AWSIZE_UNCONNECTED[2:0]),
.M_AXI_AWVALID(NLW_U0_M_AXI_AWVALID_UNCONNECTED),
.M_AXI_BID(1'b0),
.M_AXI_BREADY(NLW_U0_M_AXI_BREADY_UNCONNECTED),
.M_AXI_BRESP({1'b0,1'b0}),
.M_AXI_BVALID(1'b0),
.M_AXI_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_RID(1'b0),
.M_AXI_RLAST(1'b0),
.M_AXI_RREADY(NLW_U0_M_AXI_RREADY_UNCONNECTED),
.M_AXI_RRESP({1'b0,1'b0}),
.M_AXI_RVALID(1'b0),
.M_AXI_WDATA(NLW_U0_M_AXI_WDATA_UNCONNECTED[31:0]),
.M_AXI_WLAST(NLW_U0_M_AXI_WLAST_UNCONNECTED),
.M_AXI_WREADY(1'b0),
.M_AXI_WSTRB(NLW_U0_M_AXI_WSTRB_UNCONNECTED[3:0]),
.M_AXI_WVALID(NLW_U0_M_AXI_WVALID_UNCONNECTED),
.S_AXI_ACLK(1'b0),
.S_AXI_ARADDR({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ARESETN(1'b0),
.S_AXI_ARREADY(NLW_U0_S_AXI_ARREADY_UNCONNECTED),
.S_AXI_ARVALID(1'b0),
.S_AXI_AWADDR({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_AWREADY(NLW_U0_S_AXI_AWREADY_UNCONNECTED),
.S_AXI_AWVALID(1'b0),
.S_AXI_BREADY(1'b0),
.S_AXI_BRESP(NLW_U0_S_AXI_BRESP_UNCONNECTED[1:0]),
.S_AXI_BVALID(NLW_U0_S_AXI_BVALID_UNCONNECTED),
.S_AXI_RDATA(NLW_U0_S_AXI_RDATA_UNCONNECTED[31:0]),
.S_AXI_RREADY(1'b0),
.S_AXI_RRESP(NLW_U0_S_AXI_RRESP_UNCONNECTED[1:0]),
.S_AXI_RVALID(NLW_U0_S_AXI_RVALID_UNCONNECTED),
.S_AXI_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_WREADY(NLW_U0_S_AXI_WREADY_UNCONNECTED),
.S_AXI_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_WVALID(1'b0),
.Scan_Reset(1'b0),
.Scan_Reset_Sel(1'b0),
.TRACE_CLK(1'b0),
.TRACE_CLK_OUT(NLW_U0_TRACE_CLK_OUT_UNCONNECTED),
.TRACE_CTL(NLW_U0_TRACE_CTL_UNCONNECTED),
.TRACE_DATA(NLW_U0_TRACE_DATA_UNCONNECTED[31:0]),
.Trig_Ack_In_0(NLW_U0_Trig_Ack_In_0_UNCONNECTED),
.Trig_Ack_In_1(NLW_U0_Trig_Ack_In_1_UNCONNECTED),
.Trig_Ack_In_2(NLW_U0_Trig_Ack_In_2_UNCONNECTED),
.Trig_Ack_In_3(NLW_U0_Trig_Ack_In_3_UNCONNECTED),
.Trig_Ack_Out_0(1'b0),
.Trig_Ack_Out_1(1'b0),
.Trig_Ack_Out_2(1'b0),
.Trig_Ack_Out_3(1'b0),
.Trig_In_0(1'b0),
.Trig_In_1(1'b0),
.Trig_In_2(1'b0),
.Trig_In_3(1'b0),
.Trig_Out_0(NLW_U0_Trig_Out_0_UNCONNECTED),
.Trig_Out_1(NLW_U0_Trig_Out_1_UNCONNECTED),
.Trig_Out_2(NLW_U0_Trig_Out_2_UNCONNECTED),
.Trig_Out_3(NLW_U0_Trig_Out_3_UNCONNECTED),
.bscan_ext_capture(1'b0),
.bscan_ext_drck(1'b0),
.bscan_ext_reset(1'b0),
.bscan_ext_sel(1'b0),
.bscan_ext_shift(1'b0),
.bscan_ext_tdi(1'b0),
.bscan_ext_tdo(NLW_U0_bscan_ext_tdo_UNCONNECTED),
.bscan_ext_update(1'b0));
endmodule
(* ORIG_REF_NAME = "JTAG_CONTROL" *)
module system_mdm_1_0_JTAG_CONTROL
(Q,
AR,
Ext_NM_BRK,
Debug_SYS_Rst,
Dbg_Rst_0,
Dbg_Shift_0,
p_20_out__0,
\Use_Serial_Unified_Completion.completion_block_reg_0 ,
Dbg_Reg_En_0,
tdo,
\Use_Serial_Unified_Completion.count_reg[4]_0 ,
\Use_Serial_Unified_Completion.completion_status_reg[15]_0 ,
\Use_BSCAN.PORT_Selector_reg[0] ,
\Use_BSCAN.PORT_Selector_reg[0]_0 ,
\Use_BSCAN.PORT_Selector_reg[0]_1 ,
\Use_BSCAN.PORT_Selector_reg[0]_2 ,
\Use_BSCAN.PORT_Selector_reg[3] ,
sel,
\Use_BSCAN.PORT_Selector_reg[2] ,
Dbg_TDO_0,
Scan_Reset,
Scan_Reset_Sel,
\Use_BSCAN.PORT_Selector_reg[0]_3 ,
Ext_JTAG_TDI,
E,
D,
\command_reg[5]_0 ,
\Use_Serial_Unified_Completion.count_reg[5]_0 ,
\shift_Count_reg[0]_0 );
output [0:0]Q;
output [0:0]AR;
output Ext_NM_BRK;
output Debug_SYS_Rst;
output Dbg_Rst_0;
output Dbg_Shift_0;
output p_20_out__0;
output \Use_Serial_Unified_Completion.completion_block_reg_0 ;
output [0:7]Dbg_Reg_En_0;
output tdo;
output [0:0]\Use_Serial_Unified_Completion.count_reg[4]_0 ;
output [0:0]\Use_Serial_Unified_Completion.completion_status_reg[15]_0 ;
input \Use_BSCAN.PORT_Selector_reg[0] ;
input \Use_BSCAN.PORT_Selector_reg[0]_0 ;
input \Use_BSCAN.PORT_Selector_reg[0]_1 ;
input \Use_BSCAN.PORT_Selector_reg[0]_2 ;
input [3:0]\Use_BSCAN.PORT_Selector_reg[3] ;
input sel;
input \Use_BSCAN.PORT_Selector_reg[2] ;
input Dbg_TDO_0;
input Scan_Reset;
input Scan_Reset_Sel;
input \Use_BSCAN.PORT_Selector_reg[0]_3 ;
input Ext_JTAG_TDI;
input [0:0]E;
input [0:0]D;
input [0:0]\command_reg[5]_0 ;
input [0:0]\Use_Serial_Unified_Completion.count_reg[5]_0 ;
input [0:0]\shift_Count_reg[0]_0 ;
wire A1;
wire A2;
wire A3;
wire [0:0]AR;
wire CE;
wire [0:0]D;
wire D_0;
wire [0:7]Dbg_Reg_En_0;
wire Dbg_Rst_0;
wire Dbg_Shift_0;
wire Dbg_Shift_31_INST_0_i_1_n_0;
wire Dbg_Shift_31_INST_0_i_3_n_0;
wire Dbg_Shift_31_INST_0_i_4_n_0;
wire Dbg_TDO_0;
wire Debug_SYS_Rst;
wire [0:0]E;
wire Ext_JTAG_TDI;
wire Ext_NM_BRK;
wire Ext_NM_BRK_i_i_4_n_0;
wire FDC_I_n_15;
wire FDC_I_n_16;
wire FDC_I_n_17;
wire FDC_I_n_18;
wire FDC_I_n_30;
wire FDC_I_n_31;
wire FDC_I_n_32;
wire FDC_I_n_33;
wire FDC_I_n_34;
wire FDC_I_n_35;
wire FDC_I_n_36;
wire FDC_I_n_37;
wire FDC_I_n_38;
wire ID_TDO_2;
wire [0:0]Q;
wire Scan_Reset;
wire Scan_Reset_Sel;
wire \Use_BSCAN.PORT_Selector_reg[0] ;
wire \Use_BSCAN.PORT_Selector_reg[0]_0 ;
wire \Use_BSCAN.PORT_Selector_reg[0]_1 ;
wire \Use_BSCAN.PORT_Selector_reg[0]_2 ;
wire \Use_BSCAN.PORT_Selector_reg[0]_3 ;
wire \Use_BSCAN.PORT_Selector_reg[2] ;
wire [3:0]\Use_BSCAN.PORT_Selector_reg[3] ;
wire \Use_E2.BSCANE2_I_i_10_n_0 ;
wire \Use_E2.BSCANE2_I_i_11_n_0 ;
wire \Use_E2.BSCANE2_I_i_3_n_0 ;
wire \Use_E2.BSCANE2_I_i_6_n_0 ;
wire \Use_E2.BSCANE2_I_i_7_n_0 ;
wire \Use_ID_SRL16E.SRL16E_ID_1_n_0 ;
wire \Use_Serial_Unified_Completion.completion_block_i_2_n_0 ;
wire \Use_Serial_Unified_Completion.completion_block_i_3_n_0 ;
wire \Use_Serial_Unified_Completion.completion_block_i_4_n_0 ;
wire \Use_Serial_Unified_Completion.completion_block_reg_0 ;
wire \Use_Serial_Unified_Completion.completion_block_reg_n_0 ;
wire \Use_Serial_Unified_Completion.completion_status[3]_i_2_n_0 ;
wire \Use_Serial_Unified_Completion.completion_status[4]_i_2_n_0 ;
wire \Use_Serial_Unified_Completion.completion_status[5]_i_2_n_0 ;
wire \Use_Serial_Unified_Completion.completion_status[7]_i_2_n_0 ;
wire \Use_Serial_Unified_Completion.completion_status[9]_i_4_n_0 ;
wire [0:0]\Use_Serial_Unified_Completion.completion_status_reg[15]_0 ;
wire \Use_Serial_Unified_Completion.count[0]__0_i_4_n_0 ;
wire \Use_Serial_Unified_Completion.count[0]_i_1_n_0 ;
wire \Use_Serial_Unified_Completion.count[1]_i_1_n_0 ;
wire [0:0]\Use_Serial_Unified_Completion.count_reg[4]_0 ;
wire [0:0]\Use_Serial_Unified_Completion.count_reg[5]_0 ;
wire [0:4]\Use_Serial_Unified_Completion.count_reg__1 ;
wire \Use_Serial_Unified_Completion.count_reg_n_0_[0] ;
wire \Use_Serial_Unified_Completion.count_reg_n_0_[1] ;
wire \Use_Serial_Unified_Completion.mb_data_overrun_i_2_n_0 ;
wire \Use_Serial_Unified_Completion.mb_data_overrun_i_3_n_0 ;
wire \Use_Serial_Unified_Completion.mb_data_overrun_reg_n_0 ;
wire \Use_Serial_Unified_Completion.mb_instr_error_reg_n_0 ;
wire \Use_Serial_Unified_Completion.sample_1_reg_n_0_[10] ;
wire \Use_Serial_Unified_Completion.sample_1_reg_n_0_[11] ;
wire \Use_Serial_Unified_Completion.sample_1_reg_n_0_[12] ;
wire \Use_Serial_Unified_Completion.sample_1_reg_n_0_[13] ;
wire \Use_Serial_Unified_Completion.sample_1_reg_n_0_[14] ;
wire [0:7]command;
wire \command[0]_i_1_n_0 ;
wire [0:7]command_1;
wire command_10;
wire [0:0]\command_reg[5]_0 ;
wire command_regn_0_0;
wire completion_ctrl;
wire [15:0]completion_status;
wire config_TDO_2;
wire mb_instr_overrun;
wire [5:1]p_0_in;
wire p_0_in_1;
wire [4:1]p_0_in__0;
wire [14:0]p_1_in;
wire p_20_out__0;
wire p_22_out__0;
(* async_reg = "true" *) wire [15:13]sample;
wire sample_1;
wire sel;
wire sel_n;
wire sel_n_i_1_n_0;
wire [0:0]\shift_Count_reg[0]_0 ;
wire [4:4]shift_Count_reg__0;
wire shifting_Data1__0;
wire sync;
wire tdi_shifter0;
wire \tdi_shifter_reg_n_0_[1] ;
wire \tdi_shifter_reg_n_0_[2] ;
wire \tdi_shifter_reg_n_0_[3] ;
wire \tdi_shifter_reg_n_0_[4] ;
wire \tdi_shifter_reg_n_0_[5] ;
wire \tdi_shifter_reg_n_0_[6] ;
wire \tdi_shifter_reg_n_0_[7] ;
wire tdo;
LUT3 #(
.INIT(8'h04))
Dbg_Shift_31_INST_0_i_1
(.I0(command[6]),
.I1(command[5]),
.I2(command[7]),
.O(Dbg_Shift_31_INST_0_i_1_n_0));
LUT2 #(
.INIT(4'hE))
Dbg_Shift_31_INST_0_i_3
(.I0(command[4]),
.I1(command[2]),
.O(Dbg_Shift_31_INST_0_i_3_n_0));
LUT3 #(
.INIT(8'h01))
Dbg_Shift_31_INST_0_i_4
(.I0(command[0]),
.I1(command[1]),
.I2(command[3]),
.O(Dbg_Shift_31_INST_0_i_4_n_0));
FDCE #(
.INIT(1'b0))
Debug_Rst_i_reg
(.C(\Use_BSCAN.PORT_Selector_reg[0] ),
.CE(1'b1),
.CLR(AR),
.D(FDC_I_n_36),
.Q(Dbg_Rst_0));
FDCE #(
.INIT(1'b0))
Debug_SYS_Rst_i_reg
(.C(\Use_BSCAN.PORT_Selector_reg[0] ),
.CE(1'b1),
.CLR(AR),
.D(FDC_I_n_37),
.Q(Debug_SYS_Rst));
LUT2 #(
.INIT(4'h8))
Ext_NM_BRK_i_i_2
(.I0(Scan_Reset),
.I1(Scan_Reset_Sel),
.O(AR));
LUT6 #(
.INIT(64'h0000000000000004))
Ext_NM_BRK_i_i_4
(.I0(command[7]),
.I1(command[4]),
.I2(command[5]),
.I3(command[3]),
.I4(command[1]),
.I5(command[0]),
.O(Ext_NM_BRK_i_i_4_n_0));
FDCE #(
.INIT(1'b0))
Ext_NM_BRK_i_reg
(.C(\Use_BSCAN.PORT_Selector_reg[0] ),
.CE(1'b1),
.CLR(AR),
.D(FDC_I_n_38),
.Q(Ext_NM_BRK));
system_mdm_1_0_MB_FDC_1 FDC_I
(.CE(CE),
.D(p_1_in[9:0]),
.D_0(D_0),
.Dbg_Reg_En_0(Dbg_Reg_En_0),
.Dbg_Rst_0(Dbg_Rst_0),
.Dbg_Shift_0(Dbg_Shift_0),
.Dbg_TDO_0(Dbg_TDO_0),
.Debug_Rst_i_reg(FDC_I_n_36),
.Debug_SYS_Rst(Debug_SYS_Rst),
.Debug_SYS_Rst_i_reg(FDC_I_n_37),
.E(FDC_I_n_15),
.Ext_NM_BRK(Ext_NM_BRK),
.Ext_NM_BRK_i_reg(FDC_I_n_38),
.Q({command[0],command[1],command[2],command[3],command[4],command[5],command[6],command[7]}),
.\Use_BSCAN.PORT_Selector_reg[0] (\Use_BSCAN.PORT_Selector_reg[0] ),
.\Use_BSCAN.PORT_Selector_reg[0]_0 (\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.\Use_BSCAN.PORT_Selector_reg[0]_1 (\Use_BSCAN.PORT_Selector_reg[0]_2 ),
.\Use_BSCAN.PORT_Selector_reg[0]_2 (\Use_BSCAN.PORT_Selector_reg[0]_3 ),
.\Use_BSCAN.PORT_Selector_reg[3] (\Use_BSCAN.PORT_Selector_reg[3] ),
.\Use_Serial_Unified_Completion.completion_block_reg (\Use_Serial_Unified_Completion.completion_block_reg_0 ),
.\Use_Serial_Unified_Completion.completion_block_reg_0 (FDC_I_n_35),
.\Use_Serial_Unified_Completion.completion_block_reg_1 (\Use_Serial_Unified_Completion.completion_block_reg_n_0 ),
.\Use_Serial_Unified_Completion.completion_status_reg[10] (completion_status[10:0]),
.\Use_Serial_Unified_Completion.completion_status_reg[2] (\Use_Serial_Unified_Completion.completion_status[3]_i_2_n_0 ),
.\Use_Serial_Unified_Completion.completion_status_reg[3] (\Use_Serial_Unified_Completion.completion_status[4]_i_2_n_0 ),
.\Use_Serial_Unified_Completion.completion_status_reg[4] (\Use_Serial_Unified_Completion.completion_status[5]_i_2_n_0 ),
.\Use_Serial_Unified_Completion.completion_status_reg[5] (\Use_Serial_Unified_Completion.completion_status[7]_i_2_n_0 ),
.\Use_Serial_Unified_Completion.completion_status_reg[7] (\Use_Serial_Unified_Completion.completion_status[9]_i_4_n_0 ),
.\Use_Serial_Unified_Completion.count_reg[1] (\Use_Serial_Unified_Completion.count_reg_n_0_[1] ),
.\Use_Serial_Unified_Completion.count_reg[5] (\Use_Serial_Unified_Completion.mb_data_overrun_i_2_n_0 ),
.\Use_Serial_Unified_Completion.mb_data_overrun_reg (FDC_I_n_33),
.\Use_Serial_Unified_Completion.mb_instr_error_reg (FDC_I_n_32),
.\Use_Serial_Unified_Completion.mb_instr_overrun_reg (FDC_I_n_30),
.\Use_Serial_Unified_Completion.mb_instr_overrun_reg_0 (FDC_I_n_31),
.\Use_Serial_Unified_Completion.sample_1_reg[15] (\Use_Serial_Unified_Completion.completion_block_i_2_n_0 ),
.\Use_Serial_Unified_Completion.sample_reg[15] ({FDC_I_n_16,FDC_I_n_17,FDC_I_n_18}),
.\Use_Serial_Unified_Completion.sample_reg[15]_0 ({sample,\Use_Serial_Unified_Completion.mb_data_overrun_reg_n_0 ,\Use_Serial_Unified_Completion.mb_instr_error_reg_n_0 ,mb_instr_overrun}),
.\command_1_reg[7] (command_10),
.\command_reg[0] (Dbg_Shift_31_INST_0_i_4_n_0),
.\command_reg[4] (Dbg_Shift_31_INST_0_i_3_n_0),
.\command_reg[6] (Dbg_Shift_31_INST_0_i_1_n_0),
.\command_reg[7] (Ext_NM_BRK_i_i_4_n_0),
.completion_ctrl(completion_ctrl),
.\completion_ctrl_reg[0] (FDC_I_n_34),
.p_20_out__0(p_20_out__0),
.p_22_out__0(p_22_out__0),
.sample_1(sample_1),
.sel(sel),
.sel_n(sel_n),
.shifting_Data1__0(shifting_Data1__0),
.sync(sync),
.\tdi_shifter_reg[0] ({p_0_in_1,\tdi_shifter_reg_n_0_[1] ,\tdi_shifter_reg_n_0_[2] ,\tdi_shifter_reg_n_0_[3] ,\tdi_shifter_reg_n_0_[4] ,\tdi_shifter_reg_n_0_[5] ,\tdi_shifter_reg_n_0_[6] ,\tdi_shifter_reg_n_0_[7] }));
system_mdm_1_0_MB_FDRE_1 SYNC_FDRE
(.CE(CE),
.D_0(D_0),
.\Use_BSCAN.PORT_Selector_reg[0] (\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.\Use_BSCAN.PORT_Selector_reg[0]_0 (\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.\Use_Serial_Unified_Completion.completion_block_reg (FDC_I_n_30),
.\Use_Serial_Unified_Completion.count_reg[0] (\Use_Serial_Unified_Completion.count_reg_n_0_[0] ),
.\command_reg[0] (Dbg_Shift_31_INST_0_i_4_n_0),
.\command_reg[6] (Dbg_Shift_31_INST_0_i_1_n_0),
.p_22_out__0(p_22_out__0),
.sync(sync));
system_mdm_1_0_MB_SRL16E \Use_Config_SRL16E.SRL16E_1
(.Dbg_TDO_0(Dbg_TDO_0),
.Q({shift_Count_reg__0,A3,A2,A1,Q}),
.\Use_BSCAN.PORT_Selector_reg[0] (\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.\Use_BSCAN.PORT_Selector_reg[0]_0 (\Use_BSCAN.PORT_Selector_reg[3] [0]),
.\Use_BSCAN.PORT_Selector_reg[2] (\Use_BSCAN.PORT_Selector_reg[2] ),
.\Use_Serial_Unified_Completion.completion_status_reg[0] (completion_status[0]),
.\command_reg[0] (\Use_E2.BSCANE2_I_i_3_n_0 ),
.\command_reg[0]_0 (\Use_E2.BSCANE2_I_i_6_n_0 ),
.\command_reg[3] (\Use_E2.BSCANE2_I_i_7_n_0 ),
.\command_reg[4] ({command[4],command[5],command[7]}),
.\command_reg[5] (\Use_ID_SRL16E.SRL16E_ID_1_n_0 ),
.config_TDO_2(config_TDO_2),
.tdo(tdo));
system_mdm_1_0_MB_SRL16E__parameterized1 \Use_Config_SRL16E.SRL16E_2
(.Q({A3,A2,A1,Q}),
.\Use_BSCAN.PORT_Selector_reg[0] (\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.config_TDO_2(config_TDO_2));
LUT6 #(
.INIT(64'hFEFEFCFFFFFFFFFF))
\Use_E2.BSCANE2_I_i_10
(.I0(command[1]),
.I1(command[3]),
.I2(command[5]),
.I3(command[4]),
.I4(command[2]),
.I5(command[6]),
.O(\Use_E2.BSCANE2_I_i_10_n_0 ));
LUT6 #(
.INIT(64'h0001000010000001))
\Use_E2.BSCANE2_I_i_11
(.I0(command[1]),
.I1(command[3]),
.I2(command[2]),
.I3(command[6]),
.I4(command[4]),
.I5(command[5]),
.O(\Use_E2.BSCANE2_I_i_11_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hF8))
\Use_E2.BSCANE2_I_i_3
(.I0(command[0]),
.I1(Dbg_TDO_0),
.I2(\Use_BSCAN.PORT_Selector_reg[3] [1]),
.O(\Use_E2.BSCANE2_I_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'h00F8))
\Use_E2.BSCANE2_I_i_6
(.I0(\Use_E2.BSCANE2_I_i_10_n_0 ),
.I1(Dbg_TDO_0),
.I2(\Use_E2.BSCANE2_I_i_11_n_0 ),
.I3(command[0]),
.O(\Use_E2.BSCANE2_I_i_6_n_0 ));
LUT6 #(
.INIT(64'h88BC88FFAABEAABE))
\Use_E2.BSCANE2_I_i_7
(.I0(command[3]),
.I1(command[4]),
.I2(command[5]),
.I3(command[6]),
.I4(command[1]),
.I5(command[2]),
.O(\Use_E2.BSCANE2_I_i_7_n_0 ));
system_mdm_1_0_MB_SRL16E__parameterized3 \Use_ID_SRL16E.SRL16E_ID_1
(.ID_TDO_2(ID_TDO_2),
.Q({shift_Count_reg__0,A3,A2,A1,Q}),
.\Use_BSCAN.PORT_Selector_reg[0] (\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.\command_reg[1] ({command[1],command[2],command[4],command[5],command[6],command[7]}),
.\tdi_shifter_reg[0] (\Use_ID_SRL16E.SRL16E_ID_1_n_0 ));
system_mdm_1_0_MB_SRL16E__parameterized5 \Use_ID_SRL16E.SRL16E_ID_2
(.ID_TDO_2(ID_TDO_2),
.Q({A3,A2,A1,Q}),
.\Use_BSCAN.PORT_Selector_reg[0] (\Use_BSCAN.PORT_Selector_reg[0]_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFBAFFBABA))
\Use_Serial_Unified_Completion.completion_block_i_2
(.I0(\Use_Serial_Unified_Completion.completion_block_i_3_n_0 ),
.I1(\Use_Serial_Unified_Completion.completion_status_reg[15]_0 ),
.I2(sample[15]),
.I3(\Use_Serial_Unified_Completion.sample_1_reg_n_0_[10] ),
.I4(mb_instr_overrun),
.I5(\Use_Serial_Unified_Completion.completion_block_i_4_n_0 ),
.O(\Use_Serial_Unified_Completion.completion_block_i_2_n_0 ));
LUT4 #(
.INIT(16'h4F44))
\Use_Serial_Unified_Completion.completion_block_i_3
(.I0(\Use_Serial_Unified_Completion.sample_1_reg_n_0_[11] ),
.I1(\Use_Serial_Unified_Completion.mb_instr_error_reg_n_0 ),
.I2(\Use_Serial_Unified_Completion.sample_1_reg_n_0_[13] ),
.I3(sample[13]),
.O(\Use_Serial_Unified_Completion.completion_block_i_3_n_0 ));
LUT4 #(
.INIT(16'h4F44))
\Use_Serial_Unified_Completion.completion_block_i_4
(.I0(\Use_Serial_Unified_Completion.sample_1_reg_n_0_[12] ),
.I1(\Use_Serial_Unified_Completion.mb_data_overrun_reg_n_0 ),
.I2(\Use_Serial_Unified_Completion.sample_1_reg_n_0_[14] ),
.I3(sample[14]),
.O(\Use_Serial_Unified_Completion.completion_block_i_4_n_0 ));
FDCE #(
.INIT(1'b0))
\Use_Serial_Unified_Completion.completion_block_reg
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(1'b1),
.CLR(AR),
.D(FDC_I_n_35),
.Q(\Use_Serial_Unified_Completion.completion_block_reg_n_0 ));
LUT3 #(
.INIT(8'hB8))
\Use_Serial_Unified_Completion.completion_status[10]_i_1
(.I0(\Use_Serial_Unified_Completion.sample_1_reg_n_0_[10] ),
.I1(\Use_BSCAN.PORT_Selector_reg[0]_2 ),
.I2(completion_status[11]),
.O(p_1_in[10]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hB8))
\Use_Serial_Unified_Completion.completion_status[11]_i_1
(.I0(\Use_Serial_Unified_Completion.sample_1_reg_n_0_[11] ),
.I1(\Use_BSCAN.PORT_Selector_reg[0]_2 ),
.I2(completion_status[12]),
.O(p_1_in[11]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hB8))
\Use_Serial_Unified_Completion.completion_status[12]_i_1
(.I0(\Use_Serial_Unified_Completion.sample_1_reg_n_0_[12] ),
.I1(\Use_BSCAN.PORT_Selector_reg[0]_2 ),
.I2(completion_status[13]),
.O(p_1_in[12]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\Use_Serial_Unified_Completion.completion_status[13]_i_1
(.I0(\Use_Serial_Unified_Completion.sample_1_reg_n_0_[13] ),
.I1(\Use_BSCAN.PORT_Selector_reg[0]_2 ),
.I2(completion_status[14]),
.O(p_1_in[13]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\Use_Serial_Unified_Completion.completion_status[14]_i_1
(.I0(\Use_Serial_Unified_Completion.sample_1_reg_n_0_[14] ),
.I1(\Use_BSCAN.PORT_Selector_reg[0]_2 ),
.I2(completion_status[15]),
.O(p_1_in[14]));
LUT3 #(
.INIT(8'h80))
\Use_Serial_Unified_Completion.completion_status[3]_i_2
(.I0(completion_status[2]),
.I1(completion_status[0]),
.I2(completion_status[1]),
.O(\Use_Serial_Unified_Completion.completion_status[3]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'h8000))
\Use_Serial_Unified_Completion.completion_status[4]_i_2
(.I0(completion_status[3]),
.I1(completion_status[1]),
.I2(completion_status[0]),
.I3(completion_status[2]),
.O(\Use_Serial_Unified_Completion.completion_status[4]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'h80000000))
\Use_Serial_Unified_Completion.completion_status[5]_i_2
(.I0(completion_status[4]),
.I1(completion_status[2]),
.I2(completion_status[0]),
.I3(completion_status[1]),
.I4(completion_status[3]),
.O(\Use_Serial_Unified_Completion.completion_status[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'h8000000000000000))
\Use_Serial_Unified_Completion.completion_status[7]_i_2
(.I0(completion_status[5]),
.I1(completion_status[3]),
.I2(completion_status[1]),
.I3(completion_status[0]),
.I4(completion_status[2]),
.I5(completion_status[4]),
.O(\Use_Serial_Unified_Completion.completion_status[7]_i_2_n_0 ));
LUT3 #(
.INIT(8'h80))
\Use_Serial_Unified_Completion.completion_status[9]_i_4
(.I0(completion_status[7]),
.I1(\Use_Serial_Unified_Completion.completion_status[7]_i_2_n_0 ),
.I2(completion_status[6]),
.O(\Use_Serial_Unified_Completion.completion_status[9]_i_4_n_0 ));
FDCE #(
.INIT(1'b0))
\Use_Serial_Unified_Completion.completion_status_reg[0]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(FDC_I_n_15),
.CLR(AR),
.D(p_1_in[0]),
.Q(completion_status[0]));
FDCE #(
.INIT(1'b0))
\Use_Serial_Unified_Completion.completion_status_reg[10]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(E),
.CLR(AR),
.D(p_1_in[10]),
.Q(completion_status[10]));
FDCE #(
.INIT(1'b0))
\Use_Serial_Unified_Completion.completion_status_reg[11]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(E),
.CLR(AR),
.D(p_1_in[11]),
.Q(completion_status[11]));
FDCE #(
.INIT(1'b0))
\Use_Serial_Unified_Completion.completion_status_reg[12]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(E),
.CLR(AR),
.D(p_1_in[12]),
.Q(completion_status[12]));
FDCE #(
.INIT(1'b0))
\Use_Serial_Unified_Completion.completion_status_reg[13]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(E),
.CLR(AR),
.D(p_1_in[13]),
.Q(completion_status[13]));
FDCE #(
.INIT(1'b0))
\Use_Serial_Unified_Completion.completion_status_reg[14]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(E),
.CLR(AR),
.D(p_1_in[14]),
.Q(completion_status[14]));
FDCE #(
.INIT(1'b0))
\Use_Serial_Unified_Completion.completion_status_reg[15]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(E),
.CLR(AR),
.D(D),
.Q(completion_status[15]));
FDCE #(
.INIT(1'b0))
\Use_Serial_Unified_Completion.completion_status_reg[1]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(FDC_I_n_15),
.CLR(AR),
.D(p_1_in[1]),
.Q(completion_status[1]));
FDCE #(
.INIT(1'b0))
\Use_Serial_Unified_Completion.completion_status_reg[2]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(FDC_I_n_15),
.CLR(AR),
.D(p_1_in[2]),
.Q(completion_status[2]));
FDCE #(
.INIT(1'b0))
\Use_Serial_Unified_Completion.completion_status_reg[3]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(FDC_I_n_15),
.CLR(AR),
.D(p_1_in[3]),
.Q(completion_status[3]));
FDCE #(
.INIT(1'b0))
\Use_Serial_Unified_Completion.completion_status_reg[4]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(FDC_I_n_15),
.CLR(AR),
.D(p_1_in[4]),
.Q(completion_status[4]));
FDCE #(
.INIT(1'b0))
\Use_Serial_Unified_Completion.completion_status_reg[5]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(FDC_I_n_15),
.CLR(AR),
.D(p_1_in[5]),
.Q(completion_status[5]));
FDCE #(
.INIT(1'b0))
\Use_Serial_Unified_Completion.completion_status_reg[6]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(FDC_I_n_15),
.CLR(AR),
.D(p_1_in[6]),
.Q(completion_status[6]));
FDCE #(
.INIT(1'b0))
\Use_Serial_Unified_Completion.completion_status_reg[7]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(FDC_I_n_15),
.CLR(AR),
.D(p_1_in[7]),
.Q(completion_status[7]));
FDCE #(
.INIT(1'b0))
\Use_Serial_Unified_Completion.completion_status_reg[8]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(FDC_I_n_15),
.CLR(AR),
.D(p_1_in[8]),
.Q(completion_status[8]));
FDCE #(
.INIT(1'b0))
\Use_Serial_Unified_Completion.completion_status_reg[9]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(FDC_I_n_15),
.CLR(AR),
.D(p_1_in[9]),
.Q(completion_status[9]));
LUT4 #(
.INIT(16'h0078))
\Use_Serial_Unified_Completion.count[0]__0_i_2
(.I0(\Use_Serial_Unified_Completion.count_reg__1 [1]),
.I1(\Use_Serial_Unified_Completion.count[0]__0_i_4_n_0 ),
.I2(\Use_Serial_Unified_Completion.count_reg__1 [0]),
.I3(\Use_BSCAN.PORT_Selector_reg[0]_2 ),
.O(p_0_in[5]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h8000))
\Use_Serial_Unified_Completion.count[0]__0_i_4
(.I0(\Use_Serial_Unified_Completion.count_reg__1 [2]),
.I1(\Use_Serial_Unified_Completion.count_reg__1 [4]),
.I2(\Use_Serial_Unified_Completion.count_reg[4]_0 ),
.I3(\Use_Serial_Unified_Completion.count_reg__1 [3]),
.O(\Use_Serial_Unified_Completion.count[0]__0_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000FF80FF00FF00))
\Use_Serial_Unified_Completion.count[0]_i_1
(.I0(\Use_Serial_Unified_Completion.count_reg_n_0_[1] ),
.I1(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.I2(sync),
.I3(\Use_Serial_Unified_Completion.count_reg_n_0_[0] ),
.I4(\Use_BSCAN.PORT_Selector_reg[0]_2 ),
.I5(shifting_Data1__0),
.O(\Use_Serial_Unified_Completion.count[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h000000007FFF8000))
\Use_Serial_Unified_Completion.count[1]__0_i_1
(.I0(\Use_Serial_Unified_Completion.count_reg__1 [2]),
.I1(\Use_Serial_Unified_Completion.count_reg__1 [4]),
.I2(\Use_Serial_Unified_Completion.count_reg[4]_0 ),
.I3(\Use_Serial_Unified_Completion.count_reg__1 [3]),
.I4(\Use_Serial_Unified_Completion.count_reg__1 [1]),
.I5(\Use_BSCAN.PORT_Selector_reg[0]_2 ),
.O(p_0_in[4]));
LUT6 #(
.INIT(64'h00F7FFFF00080000))
\Use_Serial_Unified_Completion.count[1]_i_1
(.I0(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.I1(sync),
.I2(\Use_Serial_Unified_Completion.count_reg_n_0_[0] ),
.I3(\Use_BSCAN.PORT_Selector_reg[0]_2 ),
.I4(shifting_Data1__0),
.I5(\Use_Serial_Unified_Completion.count_reg_n_0_[1] ),
.O(\Use_Serial_Unified_Completion.count[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT5 #(
.INIT(32'h00007F80))
\Use_Serial_Unified_Completion.count[2]_i_1
(.I0(\Use_Serial_Unified_Completion.count_reg__1 [3]),
.I1(\Use_Serial_Unified_Completion.count_reg[4]_0 ),
.I2(\Use_Serial_Unified_Completion.count_reg__1 [4]),
.I3(\Use_Serial_Unified_Completion.count_reg__1 [2]),
.I4(\Use_BSCAN.PORT_Selector_reg[0]_2 ),
.O(p_0_in[3]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'h0078))
\Use_Serial_Unified_Completion.count[3]_i_1
(.I0(\Use_Serial_Unified_Completion.count_reg__1 [4]),
.I1(\Use_Serial_Unified_Completion.count_reg[4]_0 ),
.I2(\Use_Serial_Unified_Completion.count_reg__1 [3]),
.I3(\Use_BSCAN.PORT_Selector_reg[0]_2 ),
.O(p_0_in[2]));
LUT3 #(
.INIT(8'h06))
\Use_Serial_Unified_Completion.count[4]_i_1
(.I0(\Use_Serial_Unified_Completion.count_reg[4]_0 ),
.I1(\Use_Serial_Unified_Completion.count_reg__1 [4]),
.I2(\Use_BSCAN.PORT_Selector_reg[0]_2 ),
.O(p_0_in[1]));
FDCE #(
.INIT(1'b0))
\Use_Serial_Unified_Completion.count_reg[0]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(1'b1),
.CLR(AR),
.D(\Use_Serial_Unified_Completion.count[0]_i_1_n_0 ),
.Q(\Use_Serial_Unified_Completion.count_reg_n_0_[0] ));
FDCE #(
.INIT(1'b0))
\Use_Serial_Unified_Completion.count_reg[0]__0
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(\command_reg[5]_0 ),
.CLR(AR),
.D(p_0_in[5]),
.Q(\Use_Serial_Unified_Completion.count_reg__1 [0]));
FDCE #(
.INIT(1'b0))
\Use_Serial_Unified_Completion.count_reg[1]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(1'b1),
.CLR(AR),
.D(\Use_Serial_Unified_Completion.count[1]_i_1_n_0 ),
.Q(\Use_Serial_Unified_Completion.count_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\Use_Serial_Unified_Completion.count_reg[1]__0
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(\command_reg[5]_0 ),
.CLR(AR),
.D(p_0_in[4]),
.Q(\Use_Serial_Unified_Completion.count_reg__1 [1]));
FDCE #(
.INIT(1'b0))
\Use_Serial_Unified_Completion.count_reg[2]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(\command_reg[5]_0 ),
.CLR(AR),
.D(p_0_in[3]),
.Q(\Use_Serial_Unified_Completion.count_reg__1 [2]));
FDCE #(
.INIT(1'b0))
\Use_Serial_Unified_Completion.count_reg[3]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(\command_reg[5]_0 ),
.CLR(AR),
.D(p_0_in[2]),
.Q(\Use_Serial_Unified_Completion.count_reg__1 [3]));
FDCE #(
.INIT(1'b0))
\Use_Serial_Unified_Completion.count_reg[4]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(\command_reg[5]_0 ),
.CLR(AR),
.D(p_0_in[1]),
.Q(\Use_Serial_Unified_Completion.count_reg__1 [4]));
FDCE #(
.INIT(1'b0))
\Use_Serial_Unified_Completion.count_reg[5]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(\command_reg[5]_0 ),
.CLR(AR),
.D(\Use_Serial_Unified_Completion.count_reg[5]_0 ),
.Q(\Use_Serial_Unified_Completion.count_reg[4]_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'h0002))
\Use_Serial_Unified_Completion.mb_data_overrun_i_2
(.I0(\Use_Serial_Unified_Completion.mb_data_overrun_i_3_n_0 ),
.I1(\Use_Serial_Unified_Completion.count_reg[4]_0 ),
.I2(\Use_Serial_Unified_Completion.count_reg__1 [4]),
.I3(\Use_Serial_Unified_Completion.count_reg__1 [3]),
.O(\Use_Serial_Unified_Completion.mb_data_overrun_i_2_n_0 ));
LUT4 #(
.INIT(16'h0008))
\Use_Serial_Unified_Completion.mb_data_overrun_i_3
(.I0(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.I1(\Use_Serial_Unified_Completion.count_reg__1 [0]),
.I2(\Use_Serial_Unified_Completion.count_reg__1 [1]),
.I3(\Use_Serial_Unified_Completion.count_reg__1 [2]),
.O(\Use_Serial_Unified_Completion.mb_data_overrun_i_3_n_0 ));
FDCE #(
.INIT(1'b0))
\Use_Serial_Unified_Completion.mb_data_overrun_reg
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(1'b1),
.CLR(AR),
.D(FDC_I_n_33),
.Q(\Use_Serial_Unified_Completion.mb_data_overrun_reg_n_0 ));
FDCE #(
.INIT(1'b0))
\Use_Serial_Unified_Completion.mb_instr_error_reg
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(1'b1),
.CLR(AR),
.D(FDC_I_n_32),
.Q(\Use_Serial_Unified_Completion.mb_instr_error_reg_n_0 ));
FDCE #(
.INIT(1'b0))
\Use_Serial_Unified_Completion.mb_instr_overrun_reg
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(1'b1),
.CLR(AR),
.D(FDC_I_n_31),
.Q(mb_instr_overrun));
FDCE \Use_Serial_Unified_Completion.sample_1_reg[10]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(sample_1),
.CLR(AR),
.D(mb_instr_overrun),
.Q(\Use_Serial_Unified_Completion.sample_1_reg_n_0_[10] ));
FDCE \Use_Serial_Unified_Completion.sample_1_reg[11]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(sample_1),
.CLR(AR),
.D(\Use_Serial_Unified_Completion.mb_instr_error_reg_n_0 ),
.Q(\Use_Serial_Unified_Completion.sample_1_reg_n_0_[11] ));
FDCE \Use_Serial_Unified_Completion.sample_1_reg[12]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(sample_1),
.CLR(AR),
.D(\Use_Serial_Unified_Completion.mb_data_overrun_reg_n_0 ),
.Q(\Use_Serial_Unified_Completion.sample_1_reg_n_0_[12] ));
FDCE \Use_Serial_Unified_Completion.sample_1_reg[13]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(sample_1),
.CLR(AR),
.D(sample[13]),
.Q(\Use_Serial_Unified_Completion.sample_1_reg_n_0_[13] ));
FDCE \Use_Serial_Unified_Completion.sample_1_reg[14]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(sample_1),
.CLR(AR),
.D(sample[14]),
.Q(\Use_Serial_Unified_Completion.sample_1_reg_n_0_[14] ));
FDCE \Use_Serial_Unified_Completion.sample_1_reg[15]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(sample_1),
.CLR(AR),
.D(sample[15]),
.Q(\Use_Serial_Unified_Completion.completion_status_reg[15]_0 ));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE \Use_Serial_Unified_Completion.sample_reg[13]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(1'b1),
.CLR(AR),
.D(FDC_I_n_18),
.Q(sample[13]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE \Use_Serial_Unified_Completion.sample_reg[14]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(1'b1),
.CLR(AR),
.D(FDC_I_n_17),
.Q(sample[14]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE \Use_Serial_Unified_Completion.sample_reg[15]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(1'b1),
.CLR(AR),
.D(FDC_I_n_16),
.Q(sample[15]));
LUT5 #(
.INIT(32'h00000008))
\command[0]_i_1
(.I0(sel),
.I1(\Use_BSCAN.PORT_Selector_reg[3] [0]),
.I2(\Use_BSCAN.PORT_Selector_reg[3] [1]),
.I3(\Use_BSCAN.PORT_Selector_reg[3] [3]),
.I4(\Use_BSCAN.PORT_Selector_reg[3] [2]),
.O(\command[0]_i_1_n_0 ));
FDCE #(
.INIT(1'b0))
\command_1_reg[0]
(.C(\Use_BSCAN.PORT_Selector_reg[0] ),
.CE(command_10),
.CLR(AR),
.D(p_0_in_1),
.Q(command_1[0]));
FDCE #(
.INIT(1'b0))
\command_1_reg[1]
(.C(\Use_BSCAN.PORT_Selector_reg[0] ),
.CE(command_10),
.CLR(AR),
.D(\tdi_shifter_reg_n_0_[1] ),
.Q(command_1[1]));
FDCE #(
.INIT(1'b0))
\command_1_reg[2]
(.C(\Use_BSCAN.PORT_Selector_reg[0] ),
.CE(command_10),
.CLR(AR),
.D(\tdi_shifter_reg_n_0_[2] ),
.Q(command_1[2]));
FDCE #(
.INIT(1'b0))
\command_1_reg[3]
(.C(\Use_BSCAN.PORT_Selector_reg[0] ),
.CE(command_10),
.CLR(AR),
.D(\tdi_shifter_reg_n_0_[3] ),
.Q(command_1[3]));
FDCE #(
.INIT(1'b0))
\command_1_reg[4]
(.C(\Use_BSCAN.PORT_Selector_reg[0] ),
.CE(command_10),
.CLR(AR),
.D(\tdi_shifter_reg_n_0_[4] ),
.Q(command_1[4]));
FDCE #(
.INIT(1'b0))
\command_1_reg[5]
(.C(\Use_BSCAN.PORT_Selector_reg[0] ),
.CE(command_10),
.CLR(AR),
.D(\tdi_shifter_reg_n_0_[5] ),
.Q(command_1[5]));
FDCE #(
.INIT(1'b0))
\command_1_reg[6]
(.C(\Use_BSCAN.PORT_Selector_reg[0] ),
.CE(command_10),
.CLR(AR),
.D(\tdi_shifter_reg_n_0_[6] ),
.Q(command_1[6]));
FDCE #(
.INIT(1'b0))
\command_1_reg[7]
(.C(\Use_BSCAN.PORT_Selector_reg[0] ),
.CE(command_10),
.CLR(AR),
.D(\tdi_shifter_reg_n_0_[7] ),
.Q(command_1[7]));
FDCE #(
.INIT(1'b0))
\command_reg[0]
(.C(command_regn_0_0),
.CE(\command[0]_i_1_n_0 ),
.CLR(AR),
.D(command_1[0]),
.Q(command[0]));
FDCE #(
.INIT(1'b0))
\command_reg[1]
(.C(command_regn_0_0),
.CE(\command[0]_i_1_n_0 ),
.CLR(AR),
.D(command_1[1]),
.Q(command[1]));
FDCE #(
.INIT(1'b0))
\command_reg[2]
(.C(command_regn_0_0),
.CE(\command[0]_i_1_n_0 ),
.CLR(AR),
.D(command_1[2]),
.Q(command[2]));
FDCE #(
.INIT(1'b0))
\command_reg[3]
(.C(command_regn_0_0),
.CE(\command[0]_i_1_n_0 ),
.CLR(AR),
.D(command_1[3]),
.Q(command[3]));
FDCE #(
.INIT(1'b0))
\command_reg[4]
(.C(command_regn_0_0),
.CE(\command[0]_i_1_n_0 ),
.CLR(AR),
.D(command_1[4]),
.Q(command[4]));
FDCE #(
.INIT(1'b0))
\command_reg[5]
(.C(command_regn_0_0),
.CE(\command[0]_i_1_n_0 ),
.CLR(AR),
.D(command_1[5]),
.Q(command[5]));
FDCE #(
.INIT(1'b0))
\command_reg[6]
(.C(command_regn_0_0),
.CE(\command[0]_i_1_n_0 ),
.CLR(AR),
.D(command_1[6]),
.Q(command[6]));
FDCE #(
.INIT(1'b0))
\command_reg[7]
(.C(command_regn_0_0),
.CE(\command[0]_i_1_n_0 ),
.CLR(AR),
.D(command_1[7]),
.Q(command[7]));
LUT1 #(
.INIT(2'h1))
command_regi_0
(.I0(\Use_BSCAN.PORT_Selector_reg[0] ),
.O(command_regn_0_0));
FDCE #(
.INIT(1'b0))
\completion_ctrl_reg[0]
(.C(\Use_BSCAN.PORT_Selector_reg[0] ),
.CE(1'b1),
.CLR(AR),
.D(FDC_I_n_34),
.Q(completion_ctrl));
LUT3 #(
.INIT(8'h74))
sel_n_i_1
(.I0(\command[0]_i_1_n_0 ),
.I1(\Use_BSCAN.PORT_Selector_reg[0]_2 ),
.I2(sel_n),
.O(sel_n_i_1_n_0));
FDPE sel_n_reg
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(1'b1),
.D(sel_n_i_1_n_0),
.PRE(AR),
.Q(sel_n));
LUT3 #(
.INIT(8'h48))
\shift_Count[1]_i_1
(.I0(Q),
.I1(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.I2(A1),
.O(p_0_in__0[1]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h7080))
\shift_Count[2]_i_1
(.I0(A1),
.I1(Q),
.I2(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.I3(A2),
.O(p_0_in__0[2]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'h7F008000))
\shift_Count[3]_i_1
(.I0(A2),
.I1(Q),
.I2(A1),
.I3(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.I4(A3),
.O(p_0_in__0[3]));
LUT6 #(
.INIT(64'h7FFF000080000000))
\shift_Count[4]_i_1
(.I0(A3),
.I1(A1),
.I2(Q),
.I3(A2),
.I4(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.I5(shift_Count_reg__0),
.O(p_0_in__0[4]));
FDCE #(
.INIT(1'b0))
\shift_Count_reg[0]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(1'b1),
.CLR(AR),
.D(\shift_Count_reg[0]_0 ),
.Q(Q));
FDCE #(
.INIT(1'b0))
\shift_Count_reg[1]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(1'b1),
.CLR(AR),
.D(p_0_in__0[1]),
.Q(A1));
FDCE #(
.INIT(1'b0))
\shift_Count_reg[2]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(1'b1),
.CLR(AR),
.D(p_0_in__0[2]),
.Q(A2));
FDCE #(
.INIT(1'b0))
\shift_Count_reg[3]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(1'b1),
.CLR(AR),
.D(p_0_in__0[3]),
.Q(A3));
FDCE #(
.INIT(1'b0))
\shift_Count_reg[4]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(1'b1),
.CLR(AR),
.D(p_0_in__0[4]),
.Q(shift_Count_reg__0));
LUT6 #(
.INIT(64'h0100000000000000))
\tdi_shifter[0]_i_1
(.I0(\Use_BSCAN.PORT_Selector_reg[3] [2]),
.I1(\Use_BSCAN.PORT_Selector_reg[3] [3]),
.I2(\Use_BSCAN.PORT_Selector_reg[3] [1]),
.I3(\Use_BSCAN.PORT_Selector_reg[3] [0]),
.I4(sel),
.I5(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.O(tdi_shifter0));
FDCE #(
.INIT(1'b0))
\tdi_shifter_reg[0]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(tdi_shifter0),
.CLR(AR),
.D(Ext_JTAG_TDI),
.Q(p_0_in_1));
FDCE #(
.INIT(1'b0))
\tdi_shifter_reg[1]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(tdi_shifter0),
.CLR(AR),
.D(p_0_in_1),
.Q(\tdi_shifter_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\tdi_shifter_reg[2]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(tdi_shifter0),
.CLR(AR),
.D(\tdi_shifter_reg_n_0_[1] ),
.Q(\tdi_shifter_reg_n_0_[2] ));
FDCE #(
.INIT(1'b0))
\tdi_shifter_reg[3]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(tdi_shifter0),
.CLR(AR),
.D(\tdi_shifter_reg_n_0_[2] ),
.Q(\tdi_shifter_reg_n_0_[3] ));
FDCE #(
.INIT(1'b0))
\tdi_shifter_reg[4]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(tdi_shifter0),
.CLR(AR),
.D(\tdi_shifter_reg_n_0_[3] ),
.Q(\tdi_shifter_reg_n_0_[4] ));
FDCE #(
.INIT(1'b0))
\tdi_shifter_reg[5]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(tdi_shifter0),
.CLR(AR),
.D(\tdi_shifter_reg_n_0_[4] ),
.Q(\tdi_shifter_reg_n_0_[5] ));
FDCE #(
.INIT(1'b0))
\tdi_shifter_reg[6]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(tdi_shifter0),
.CLR(AR),
.D(\tdi_shifter_reg_n_0_[5] ),
.Q(\tdi_shifter_reg_n_0_[6] ));
FDCE #(
.INIT(1'b0))
\tdi_shifter_reg[7]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(tdi_shifter0),
.CLR(AR),
.D(\tdi_shifter_reg_n_0_[6] ),
.Q(\tdi_shifter_reg_n_0_[7] ));
endmodule
(* ORIG_REF_NAME = "MB_BSCANE2" *)
module system_mdm_1_0_MB_BSCANE2
(Dbg_Capture_0,
drck_i,
Ext_JTAG_RESET,
sel,
\Use_Serial_Unified_Completion.count_reg[5] ,
Ext_JTAG_TDI,
Dbg_Update_31,
\Use_Serial_Unified_Completion.count_reg[5]_0 ,
E,
shift_n_reset,
AR,
\Use_Serial_Unified_Completion.count_reg[5]_1 ,
\shift_Count_reg[0] ,
\Use_Serial_Unified_Completion.mb_instr_overrun_reg ,
D,
tdo,
p_20_out__0,
p_43_out__0,
Scan_Reset,
Scan_Reset_Sel,
\Use_Serial_Unified_Completion.count_reg[5]_2 ,
Q,
Dbg_TDO_0,
\Use_Serial_Unified_Completion.sample_1_reg[15] );
output Dbg_Capture_0;
output drck_i;
output Ext_JTAG_RESET;
output sel;
output \Use_Serial_Unified_Completion.count_reg[5] ;
output Ext_JTAG_TDI;
output Dbg_Update_31;
output [0:0]\Use_Serial_Unified_Completion.count_reg[5]_0 ;
output [0:0]E;
output shift_n_reset;
output [0:0]AR;
output [0:0]\Use_Serial_Unified_Completion.count_reg[5]_1 ;
output [0:0]\shift_Count_reg[0] ;
output \Use_Serial_Unified_Completion.mb_instr_overrun_reg ;
output [0:0]D;
input tdo;
input p_20_out__0;
input p_43_out__0;
input Scan_Reset;
input Scan_Reset_Sel;
input [0:0]\Use_Serial_Unified_Completion.count_reg[5]_2 ;
input [0:0]Q;
input Dbg_TDO_0;
input [0:0]\Use_Serial_Unified_Completion.sample_1_reg[15] ;
wire [0:0]AR;
wire [0:0]D;
wire Dbg_Capture_0;
wire Dbg_TDO_0;
wire Dbg_Update_31;
wire [0:0]E;
wire Ext_JTAG_RESET;
wire Ext_JTAG_TDI;
wire [0:0]Q;
wire Scan_Reset;
wire Scan_Reset_Sel;
wire \Use_E2.BSCANE2_I_n_3 ;
wire \Use_E2.BSCANE2_I_n_6 ;
wire \Use_E2.BSCANE2_I_n_8 ;
wire \Use_Serial_Unified_Completion.count_reg[5] ;
wire [0:0]\Use_Serial_Unified_Completion.count_reg[5]_0 ;
wire [0:0]\Use_Serial_Unified_Completion.count_reg[5]_1 ;
wire [0:0]\Use_Serial_Unified_Completion.count_reg[5]_2 ;
wire \Use_Serial_Unified_Completion.mb_instr_overrun_reg ;
wire [0:0]\Use_Serial_Unified_Completion.sample_1_reg[15] ;
wire drck_i;
wire p_20_out__0;
wire p_43_out__0;
wire sel;
wire [0:0]\shift_Count_reg[0] ;
wire shift_n_reset;
wire tdo;
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'h8B))
\Use_BSCAN.Config_Reg[30]_i_1
(.I0(Scan_Reset),
.I1(Scan_Reset_Sel),
.I2(\Use_Serial_Unified_Completion.count_reg[5] ),
.O(shift_n_reset));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'h8B))
\Use_BSCAN.PORT_Selector[3]_i_1
(.I0(Scan_Reset),
.I1(Scan_Reset_Sel),
.I2(sel),
.O(AR));
(* box_type = "PRIMITIVE" *)
BSCANE2 #(
.DISABLE_JTAG("FALSE"),
.JTAG_CHAIN(2))
\Use_E2.BSCANE2_I
(.CAPTURE(Dbg_Capture_0),
.DRCK(drck_i),
.RESET(Ext_JTAG_RESET),
.RUNTEST(\Use_E2.BSCANE2_I_n_3 ),
.SEL(sel),
.SHIFT(\Use_Serial_Unified_Completion.count_reg[5] ),
.TCK(\Use_E2.BSCANE2_I_n_6 ),
.TDI(Ext_JTAG_TDI),
.TDO(tdo),
.TMS(\Use_E2.BSCANE2_I_n_8 ),
.UPDATE(Dbg_Update_31));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hA8))
\Use_Serial_Unified_Completion.completion_status[15]_i_1
(.I0(p_43_out__0),
.I1(Dbg_Capture_0),
.I2(\Use_Serial_Unified_Completion.count_reg[5] ),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h8))
\Use_Serial_Unified_Completion.completion_status[15]_i_2
(.I0(Dbg_Capture_0),
.I1(\Use_Serial_Unified_Completion.sample_1_reg[15] ),
.O(D));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hA8))
\Use_Serial_Unified_Completion.count[0]__0_i_1
(.I0(p_20_out__0),
.I1(Dbg_Capture_0),
.I2(\Use_Serial_Unified_Completion.count_reg[5] ),
.O(\Use_Serial_Unified_Completion.count_reg[5]_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h1))
\Use_Serial_Unified_Completion.count[5]_i_1
(.I0(Dbg_Capture_0),
.I1(\Use_Serial_Unified_Completion.count_reg[5]_2 ),
.O(\Use_Serial_Unified_Completion.count_reg[5]_1 ));
LUT2 #(
.INIT(4'h2))
\Use_Serial_Unified_Completion.mb_instr_overrun_i_2
(.I0(Dbg_TDO_0),
.I1(Dbg_Capture_0),
.O(\Use_Serial_Unified_Completion.mb_instr_overrun_reg ));
LUT2 #(
.INIT(4'h2))
\shift_Count[0]_i_1
(.I0(\Use_Serial_Unified_Completion.count_reg[5] ),
.I1(Q),
.O(\shift_Count_reg[0] ));
endmodule
(* ORIG_REF_NAME = "MB_BUFG" *)
module system_mdm_1_0_MB_BUFG
(Dbg_Clk_31,
drck_i);
output Dbg_Clk_31;
input drck_i;
wire Dbg_Clk_31;
wire drck_i;
(* box_type = "PRIMITIVE" *)
BUFG \Using_FPGA.Native
(.I(drck_i),
.O(Dbg_Clk_31));
endmodule
(* ORIG_REF_NAME = "MB_FDC_1" *)
module system_mdm_1_0_MB_FDC_1
(D_0,
Dbg_Shift_0,
p_20_out__0,
D,
\Use_Serial_Unified_Completion.completion_block_reg ,
sample_1,
E,
\Use_Serial_Unified_Completion.sample_reg[15] ,
shifting_Data1__0,
Dbg_Reg_En_0,
CE,
\command_1_reg[7] ,
\Use_Serial_Unified_Completion.mb_instr_overrun_reg ,
\Use_Serial_Unified_Completion.mb_instr_overrun_reg_0 ,
\Use_Serial_Unified_Completion.mb_instr_error_reg ,
\Use_Serial_Unified_Completion.mb_data_overrun_reg ,
\completion_ctrl_reg[0] ,
\Use_Serial_Unified_Completion.completion_block_reg_0 ,
Debug_Rst_i_reg,
Debug_SYS_Rst_i_reg,
Ext_NM_BRK_i_reg,
\Use_BSCAN.PORT_Selector_reg[0] ,
sel_n,
\command_reg[6] ,
\command_reg[4] ,
\command_reg[0] ,
sync,
\Use_BSCAN.PORT_Selector_reg[0]_0 ,
Q,
\Use_Serial_Unified_Completion.completion_block_reg_1 ,
\command_reg[7] ,
\Use_Serial_Unified_Completion.completion_status_reg[10] ,
\Use_Serial_Unified_Completion.completion_status_reg[2] ,
\Use_Serial_Unified_Completion.completion_status_reg[3] ,
\Use_Serial_Unified_Completion.completion_status_reg[4] ,
\Use_Serial_Unified_Completion.completion_status_reg[5] ,
\Use_Serial_Unified_Completion.completion_status_reg[7] ,
\Use_BSCAN.PORT_Selector_reg[0]_1 ,
\Use_Serial_Unified_Completion.sample_reg[15]_0 ,
\tdi_shifter_reg[0] ,
\Use_BSCAN.PORT_Selector_reg[3] ,
sel,
\Use_BSCAN.PORT_Selector_reg[0]_2 ,
p_22_out__0,
\Use_Serial_Unified_Completion.count_reg[1] ,
Dbg_TDO_0,
\Use_Serial_Unified_Completion.count_reg[5] ,
completion_ctrl,
\Use_Serial_Unified_Completion.sample_1_reg[15] ,
Dbg_Rst_0,
Debug_SYS_Rst,
Ext_NM_BRK);
output D_0;
output Dbg_Shift_0;
output p_20_out__0;
output [9:0]D;
output \Use_Serial_Unified_Completion.completion_block_reg ;
output sample_1;
output [0:0]E;
output [2:0]\Use_Serial_Unified_Completion.sample_reg[15] ;
output shifting_Data1__0;
output [0:7]Dbg_Reg_En_0;
output CE;
output [0:0]\command_1_reg[7] ;
output \Use_Serial_Unified_Completion.mb_instr_overrun_reg ;
output \Use_Serial_Unified_Completion.mb_instr_overrun_reg_0 ;
output \Use_Serial_Unified_Completion.mb_instr_error_reg ;
output \Use_Serial_Unified_Completion.mb_data_overrun_reg ;
output \completion_ctrl_reg[0] ;
output \Use_Serial_Unified_Completion.completion_block_reg_0 ;
output Debug_Rst_i_reg;
output Debug_SYS_Rst_i_reg;
output Ext_NM_BRK_i_reg;
input \Use_BSCAN.PORT_Selector_reg[0] ;
input sel_n;
input \command_reg[6] ;
input \command_reg[4] ;
input \command_reg[0] ;
input sync;
input \Use_BSCAN.PORT_Selector_reg[0]_0 ;
input [7:0]Q;
input \Use_Serial_Unified_Completion.completion_block_reg_1 ;
input \command_reg[7] ;
input [10:0]\Use_Serial_Unified_Completion.completion_status_reg[10] ;
input \Use_Serial_Unified_Completion.completion_status_reg[2] ;
input \Use_Serial_Unified_Completion.completion_status_reg[3] ;
input \Use_Serial_Unified_Completion.completion_status_reg[4] ;
input \Use_Serial_Unified_Completion.completion_status_reg[5] ;
input \Use_Serial_Unified_Completion.completion_status_reg[7] ;
input \Use_BSCAN.PORT_Selector_reg[0]_1 ;
input [5:0]\Use_Serial_Unified_Completion.sample_reg[15]_0 ;
input [7:0]\tdi_shifter_reg[0] ;
input [3:0]\Use_BSCAN.PORT_Selector_reg[3] ;
input sel;
input \Use_BSCAN.PORT_Selector_reg[0]_2 ;
input p_22_out__0;
input \Use_Serial_Unified_Completion.count_reg[1] ;
input Dbg_TDO_0;
input \Use_Serial_Unified_Completion.count_reg[5] ;
input completion_ctrl;
input \Use_Serial_Unified_Completion.sample_1_reg[15] ;
input Dbg_Rst_0;
input Debug_SYS_Rst;
input Ext_NM_BRK;
wire CE;
wire [9:0]D;
wire D_0;
wire [0:7]Dbg_Reg_En_0;
wire Dbg_Rst_0;
wire Dbg_Shift_0;
wire Dbg_Shift_31_INST_0_i_2_n_0;
wire Dbg_TDO_0;
wire Debug_Rst_i0;
wire Debug_Rst_i_reg;
wire Debug_SYS_Rst;
wire Debug_SYS_Rst_i_reg;
wire [0:0]E;
wire Ext_NM_BRK;
wire Ext_NM_BRK_i_reg;
wire [7:0]Q;
wire \Use_BSCAN.PORT_Selector_reg[0] ;
wire \Use_BSCAN.PORT_Selector_reg[0]_0 ;
wire \Use_BSCAN.PORT_Selector_reg[0]_1 ;
wire \Use_BSCAN.PORT_Selector_reg[0]_2 ;
wire [3:0]\Use_BSCAN.PORT_Selector_reg[3] ;
wire \Use_Serial_Unified_Completion.completion_block_reg ;
wire \Use_Serial_Unified_Completion.completion_block_reg_0 ;
wire \Use_Serial_Unified_Completion.completion_block_reg_1 ;
wire [10:0]\Use_Serial_Unified_Completion.completion_status_reg[10] ;
wire \Use_Serial_Unified_Completion.completion_status_reg[2] ;
wire \Use_Serial_Unified_Completion.completion_status_reg[3] ;
wire \Use_Serial_Unified_Completion.completion_status_reg[4] ;
wire \Use_Serial_Unified_Completion.completion_status_reg[5] ;
wire \Use_Serial_Unified_Completion.completion_status_reg[7] ;
wire \Use_Serial_Unified_Completion.count_reg[1] ;
wire \Use_Serial_Unified_Completion.count_reg[5] ;
wire \Use_Serial_Unified_Completion.mb_data_overrun_reg ;
wire \Use_Serial_Unified_Completion.mb_instr_error_reg ;
wire \Use_Serial_Unified_Completion.mb_instr_overrun_i_4_n_0 ;
wire \Use_Serial_Unified_Completion.mb_instr_overrun_i_6_n_0 ;
wire \Use_Serial_Unified_Completion.mb_instr_overrun_reg ;
wire \Use_Serial_Unified_Completion.mb_instr_overrun_reg_0 ;
wire \Use_Serial_Unified_Completion.sample_1[15]_i_2_n_0 ;
wire \Use_Serial_Unified_Completion.sample_1_reg[15] ;
wire [2:0]\Use_Serial_Unified_Completion.sample_reg[15] ;
wire [5:0]\Use_Serial_Unified_Completion.sample_reg[15]_0 ;
wire \Using_FPGA.Native_i_2_n_0 ;
wire [0:0]\command_1_reg[7] ;
wire \command_reg[0] ;
wire \command_reg[4] ;
wire \command_reg[6] ;
wire \command_reg[7] ;
wire completion_ctrl;
wire completion_ctrl0;
wire \completion_ctrl_reg[0] ;
wire data_cmd_noblock;
wire p_20_out__0;
wire p_22_out__0;
wire sample_1;
wire sel;
wire sel_n;
wire shifting_Data1__0;
wire sync;
wire [7:0]\tdi_shifter_reg[0] ;
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h40))
\Dbg_Reg_En_0[0]_INST_0
(.I0(\Use_Serial_Unified_Completion.completion_block_reg_1 ),
.I1(data_cmd_noblock),
.I2(Q[7]),
.O(Dbg_Reg_En_0[0]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h40))
\Dbg_Reg_En_0[1]_INST_0
(.I0(\Use_Serial_Unified_Completion.completion_block_reg_1 ),
.I1(data_cmd_noblock),
.I2(Q[6]),
.O(Dbg_Reg_En_0[1]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h40))
\Dbg_Reg_En_0[2]_INST_0
(.I0(\Use_Serial_Unified_Completion.completion_block_reg_1 ),
.I1(data_cmd_noblock),
.I2(Q[5]),
.O(Dbg_Reg_En_0[2]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h40))
\Dbg_Reg_En_0[3]_INST_0
(.I0(\Use_Serial_Unified_Completion.completion_block_reg_1 ),
.I1(data_cmd_noblock),
.I2(Q[4]),
.O(Dbg_Reg_En_0[3]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h40))
\Dbg_Reg_En_0[4]_INST_0
(.I0(\Use_Serial_Unified_Completion.completion_block_reg_1 ),
.I1(data_cmd_noblock),
.I2(Q[3]),
.O(Dbg_Reg_En_0[4]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h40))
\Dbg_Reg_En_0[5]_INST_0
(.I0(\Use_Serial_Unified_Completion.completion_block_reg_1 ),
.I1(data_cmd_noblock),
.I2(Q[2]),
.O(Dbg_Reg_En_0[5]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h40))
\Dbg_Reg_En_0[6]_INST_0
(.I0(\Use_Serial_Unified_Completion.completion_block_reg_1 ),
.I1(data_cmd_noblock),
.I2(Q[1]),
.O(Dbg_Reg_En_0[6]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h40))
\Dbg_Reg_En_0[7]_INST_0
(.I0(\Use_Serial_Unified_Completion.completion_block_reg_1 ),
.I1(data_cmd_noblock),
.I2(Q[0]),
.O(Dbg_Reg_En_0[7]));
LUT6 #(
.INIT(64'hFFFFF7FF00000000))
Dbg_Shift_31_INST_0
(.I0(\command_reg[6] ),
.I1(Dbg_Shift_31_INST_0_i_2_n_0),
.I2(\command_reg[4] ),
.I3(\command_reg[0] ),
.I4(sync),
.I5(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.O(Dbg_Shift_0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h2))
Dbg_Shift_31_INST_0_i_2
(.I0(data_cmd_noblock),
.I1(\Use_Serial_Unified_Completion.completion_block_reg_1 ),
.O(Dbg_Shift_31_INST_0_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hB8))
Debug_Rst_i_i_1
(.I0(\tdi_shifter_reg[0] [7]),
.I1(Debug_Rst_i0),
.I2(Dbg_Rst_0),
.O(Debug_Rst_i_reg));
LUT3 #(
.INIT(8'hB8))
Debug_SYS_Rst_i_i_1
(.I0(\tdi_shifter_reg[0] [6]),
.I1(Debug_Rst_i0),
.I2(Debug_SYS_Rst),
.O(Debug_SYS_Rst_i_reg));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hB8))
Ext_NM_BRK_i_i_1
(.I0(\tdi_shifter_reg[0] [4]),
.I1(Debug_Rst_i0),
.I2(Ext_NM_BRK),
.O(Ext_NM_BRK_i_reg));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h00020000))
Ext_NM_BRK_i_i_3
(.I0(data_cmd_noblock),
.I1(\Use_Serial_Unified_Completion.completion_block_reg_1 ),
.I2(Q[1]),
.I3(Q[5]),
.I4(\command_reg[7] ),
.O(Debug_Rst_i0));
LUT6 #(
.INIT(64'hFF5FFF5F000C0000))
\Use_Serial_Unified_Completion.completion_block_i_1
(.I0(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.I1(\Use_Serial_Unified_Completion.sample_1_reg[15] ),
.I2(completion_ctrl0),
.I3(\Use_Serial_Unified_Completion.completion_block_reg ),
.I4(completion_ctrl),
.I5(\Use_Serial_Unified_Completion.completion_block_reg_1 ),
.O(\Use_Serial_Unified_Completion.completion_block_reg_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h8F88))
\Use_Serial_Unified_Completion.completion_status[0]_i_1
(.I0(\Use_Serial_Unified_Completion.completion_block_reg ),
.I1(\Use_Serial_Unified_Completion.completion_status_reg[10] [1]),
.I2(\Use_Serial_Unified_Completion.completion_status_reg[10] [0]),
.I3(sample_1),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h8000))
\Use_Serial_Unified_Completion.completion_status[15]_i_3
(.I0(Q[1]),
.I1(Q[5]),
.I2(data_cmd_noblock),
.I3(\command_reg[7] ),
.O(\Use_Serial_Unified_Completion.completion_block_reg ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'hFF606060))
\Use_Serial_Unified_Completion.completion_status[1]_i_1
(.I0(\Use_Serial_Unified_Completion.completion_status_reg[10] [1]),
.I1(\Use_Serial_Unified_Completion.completion_status_reg[10] [0]),
.I2(sample_1),
.I3(\Use_Serial_Unified_Completion.completion_block_reg ),
.I4(\Use_Serial_Unified_Completion.completion_status_reg[10] [2]),
.O(D[1]));
LUT6 #(
.INIT(64'hFFFF6A006A006A00))
\Use_Serial_Unified_Completion.completion_status[2]_i_1
(.I0(\Use_Serial_Unified_Completion.completion_status_reg[10] [2]),
.I1(\Use_Serial_Unified_Completion.completion_status_reg[10] [1]),
.I2(\Use_Serial_Unified_Completion.completion_status_reg[10] [0]),
.I3(sample_1),
.I4(\Use_Serial_Unified_Completion.completion_block_reg ),
.I5(\Use_Serial_Unified_Completion.completion_status_reg[10] [3]),
.O(D[2]));
LUT5 #(
.INIT(32'hFF606060))
\Use_Serial_Unified_Completion.completion_status[3]_i_1
(.I0(\Use_Serial_Unified_Completion.completion_status_reg[10] [3]),
.I1(\Use_Serial_Unified_Completion.completion_status_reg[2] ),
.I2(sample_1),
.I3(\Use_Serial_Unified_Completion.completion_block_reg ),
.I4(\Use_Serial_Unified_Completion.completion_status_reg[10] [4]),
.O(D[3]));
LUT5 #(
.INIT(32'hFF606060))
\Use_Serial_Unified_Completion.completion_status[4]_i_1
(.I0(\Use_Serial_Unified_Completion.completion_status_reg[10] [4]),
.I1(\Use_Serial_Unified_Completion.completion_status_reg[3] ),
.I2(sample_1),
.I3(\Use_Serial_Unified_Completion.completion_block_reg ),
.I4(\Use_Serial_Unified_Completion.completion_status_reg[10] [5]),
.O(D[4]));
LUT5 #(
.INIT(32'hFF484848))
\Use_Serial_Unified_Completion.completion_status[5]_i_1
(.I0(\Use_Serial_Unified_Completion.completion_status_reg[10] [5]),
.I1(sample_1),
.I2(\Use_Serial_Unified_Completion.completion_status_reg[4] ),
.I3(\Use_Serial_Unified_Completion.completion_block_reg ),
.I4(\Use_Serial_Unified_Completion.completion_status_reg[10] [6]),
.O(D[5]));
LUT5 #(
.INIT(32'hFF484848))
\Use_Serial_Unified_Completion.completion_status[6]_i_1
(.I0(\Use_Serial_Unified_Completion.completion_status_reg[10] [6]),
.I1(sample_1),
.I2(\Use_Serial_Unified_Completion.completion_status_reg[5] ),
.I3(\Use_Serial_Unified_Completion.completion_block_reg ),
.I4(\Use_Serial_Unified_Completion.completion_status_reg[10] [7]),
.O(D[6]));
LUT6 #(
.INIT(64'hFFFF488848884888))
\Use_Serial_Unified_Completion.completion_status[7]_i_1
(.I0(\Use_Serial_Unified_Completion.completion_status_reg[10] [7]),
.I1(sample_1),
.I2(\Use_Serial_Unified_Completion.completion_status_reg[5] ),
.I3(\Use_Serial_Unified_Completion.completion_status_reg[10] [6]),
.I4(\Use_Serial_Unified_Completion.completion_block_reg ),
.I5(\Use_Serial_Unified_Completion.completion_status_reg[10] [8]),
.O(D[7]));
LUT5 #(
.INIT(32'hFF484848))
\Use_Serial_Unified_Completion.completion_status[8]_i_1
(.I0(\Use_Serial_Unified_Completion.completion_status_reg[10] [8]),
.I1(sample_1),
.I2(\Use_Serial_Unified_Completion.completion_status_reg[7] ),
.I3(\Use_Serial_Unified_Completion.completion_block_reg ),
.I4(\Use_Serial_Unified_Completion.completion_status_reg[10] [9]),
.O(D[8]));
LUT6 #(
.INIT(64'h0CA00CA00CA00FA0))
\Use_Serial_Unified_Completion.completion_status[9]_i_1
(.I0(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.I1(completion_ctrl0),
.I2(\Use_Serial_Unified_Completion.completion_block_reg ),
.I3(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.I4(\Use_Serial_Unified_Completion.completion_block_reg_1 ),
.I5(data_cmd_noblock),
.O(E));
LUT6 #(
.INIT(64'hFFFF488848884888))
\Use_Serial_Unified_Completion.completion_status[9]_i_2
(.I0(\Use_Serial_Unified_Completion.completion_status_reg[10] [9]),
.I1(sample_1),
.I2(\Use_Serial_Unified_Completion.completion_status_reg[7] ),
.I3(\Use_Serial_Unified_Completion.completion_status_reg[10] [8]),
.I4(\Use_Serial_Unified_Completion.completion_block_reg ),
.I5(\Use_Serial_Unified_Completion.completion_status_reg[10] [10]),
.O(D[9]));
LUT6 #(
.INIT(64'h2000000000000000))
\Use_Serial_Unified_Completion.completion_status[9]_i_3
(.I0(\Use_Serial_Unified_Completion.sample_1[15]_i_2_n_0 ),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[3]),
.I4(Q[2]),
.I5(\command_reg[0] ),
.O(completion_ctrl0));
LUT6 #(
.INIT(64'h0000080000000000))
\Use_Serial_Unified_Completion.count[0]__0_i_3
(.I0(Q[2]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Dbg_Shift_31_INST_0_i_2_n_0),
.I4(\command_reg[4] ),
.I5(\command_reg[0] ),
.O(p_20_out__0));
LUT6 #(
.INIT(64'h0000040000000000))
\Use_Serial_Unified_Completion.count[0]_i_2
(.I0(Q[1]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Dbg_Shift_31_INST_0_i_2_n_0),
.I4(\command_reg[4] ),
.I5(\command_reg[0] ),
.O(shifting_Data1__0));
LUT6 #(
.INIT(64'h113F333F11000000))
\Use_Serial_Unified_Completion.mb_data_overrun_i_1
(.I0(Dbg_TDO_0),
.I1(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.I2(completion_ctrl0),
.I3(p_20_out__0),
.I4(\Use_Serial_Unified_Completion.count_reg[5] ),
.I5(\Use_Serial_Unified_Completion.sample_reg[15]_0 [2]),
.O(\Use_Serial_Unified_Completion.mb_data_overrun_reg ));
LUT6 #(
.INIT(64'hA0A0BFFFA0A08000))
\Use_Serial_Unified_Completion.mb_instr_error_i_1
(.I0(\Use_BSCAN.PORT_Selector_reg[0]_2 ),
.I1(p_22_out__0),
.I2(shifting_Data1__0),
.I3(\Use_Serial_Unified_Completion.count_reg[1] ),
.I4(\Use_Serial_Unified_Completion.mb_instr_overrun_i_4_n_0 ),
.I5(\Use_Serial_Unified_Completion.sample_reg[15]_0 [1]),
.O(\Use_Serial_Unified_Completion.mb_instr_error_reg ));
LUT6 #(
.INIT(64'hA0A0FFBFA0A00080))
\Use_Serial_Unified_Completion.mb_instr_overrun_i_1
(.I0(\Use_BSCAN.PORT_Selector_reg[0]_2 ),
.I1(p_22_out__0),
.I2(shifting_Data1__0),
.I3(\Use_Serial_Unified_Completion.count_reg[1] ),
.I4(\Use_Serial_Unified_Completion.mb_instr_overrun_i_4_n_0 ),
.I5(\Use_Serial_Unified_Completion.sample_reg[15]_0 [0]),
.O(\Use_Serial_Unified_Completion.mb_instr_overrun_reg_0 ));
LUT6 #(
.INIT(64'hFF00000008000000))
\Use_Serial_Unified_Completion.mb_instr_overrun_i_4
(.I0(\command_reg[6] ),
.I1(Dbg_Shift_31_INST_0_i_2_n_0),
.I2(\command_reg[4] ),
.I3(\command_reg[0] ),
.I4(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.I5(\Use_Serial_Unified_Completion.mb_instr_overrun_i_6_n_0 ),
.O(\Use_Serial_Unified_Completion.mb_instr_overrun_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h0004))
\Use_Serial_Unified_Completion.mb_instr_overrun_i_5
(.I0(\Use_Serial_Unified_Completion.completion_block_reg_1 ),
.I1(data_cmd_noblock),
.I2(Q[5]),
.I3(Q[3]),
.O(\Use_Serial_Unified_Completion.mb_instr_overrun_reg ));
LUT6 #(
.INIT(64'h0080000000000000))
\Use_Serial_Unified_Completion.mb_instr_overrun_i_6
(.I0(Q[2]),
.I1(Q[3]),
.I2(Q[0]),
.I3(Q[1]),
.I4(data_cmd_noblock),
.I5(Q[5]),
.O(\Use_Serial_Unified_Completion.mb_instr_overrun_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h2))
\Use_Serial_Unified_Completion.sample[13]_i_1
(.I0(\Use_Serial_Unified_Completion.sample_reg[15]_0 [3]),
.I1(sample_1),
.O(\Use_Serial_Unified_Completion.sample_reg[15] [0]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h2))
\Use_Serial_Unified_Completion.sample[14]_i_1
(.I0(\Use_Serial_Unified_Completion.sample_reg[15]_0 [4]),
.I1(sample_1),
.O(\Use_Serial_Unified_Completion.sample_reg[15] [1]));
LUT2 #(
.INIT(4'h2))
\Use_Serial_Unified_Completion.sample[15]_i_1
(.I0(\Use_Serial_Unified_Completion.sample_reg[15]_0 [5]),
.I1(sample_1),
.O(\Use_Serial_Unified_Completion.sample_reg[15] [2]));
LUT6 #(
.INIT(64'hFFDF7FFFFFFFFFFF))
\Use_Serial_Unified_Completion.sample_1[15]_i_1
(.I0(\command_reg[0] ),
.I1(Q[2]),
.I2(Q[3]),
.I3(Q[0]),
.I4(Q[1]),
.I5(\Use_Serial_Unified_Completion.sample_1[15]_i_2_n_0 ),
.O(sample_1));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'h8))
\Use_Serial_Unified_Completion.sample_1[15]_i_2
(.I0(Q[5]),
.I1(data_cmd_noblock),
.O(\Use_Serial_Unified_Completion.sample_1[15]_i_2_n_0 ));
(* XILINX_LEGACY_PRIM = "FDC_1" *)
(* box_type = "PRIMITIVE" *)
FDCE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b1))
\Using_FPGA.Native
(.C(\Use_BSCAN.PORT_Selector_reg[0] ),
.CE(1'b1),
.CLR(sel_n),
.D(D_0),
.Q(data_cmd_noblock));
LUT5 #(
.INIT(32'h00000800))
\Using_FPGA.Native_i_1
(.I0(\Using_FPGA.Native_i_2_n_0 ),
.I1(\tdi_shifter_reg[0] [3]),
.I2(\tdi_shifter_reg[0] [2]),
.I3(\tdi_shifter_reg[0] [0]),
.I4(\tdi_shifter_reg[0] [1]),
.O(CE));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT1 #(
.INIT(2'h1))
\Using_FPGA.Native_i_1__0
(.I0(data_cmd_noblock),
.O(D_0));
LUT6 #(
.INIT(64'h0000002000000000))
\Using_FPGA.Native_i_2
(.I0(\tdi_shifter_reg[0] [5]),
.I1(\tdi_shifter_reg[0] [4]),
.I2(\tdi_shifter_reg[0] [6]),
.I3(\tdi_shifter_reg[0] [7]),
.I4(\Use_Serial_Unified_Completion.completion_block_reg_1 ),
.I5(data_cmd_noblock),
.O(\Using_FPGA.Native_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000001000000))
\command_1[0]_i_1
(.I0(\Use_BSCAN.PORT_Selector_reg[3] [2]),
.I1(\Use_BSCAN.PORT_Selector_reg[3] [3]),
.I2(\Use_BSCAN.PORT_Selector_reg[3] [1]),
.I3(\Use_BSCAN.PORT_Selector_reg[3] [0]),
.I4(sel),
.I5(Dbg_Shift_31_INST_0_i_2_n_0),
.O(\command_1_reg[7] ));
LUT3 #(
.INIT(8'hB8))
\completion_ctrl[0]_i_1
(.I0(\tdi_shifter_reg[0] [7]),
.I1(completion_ctrl0),
.I2(completion_ctrl),
.O(\completion_ctrl_reg[0] ));
endmodule
(* ORIG_REF_NAME = "MB_FDRE_1" *)
module system_mdm_1_0_MB_FDRE_1
(sync,
p_22_out__0,
D_0,
CE,
\Use_BSCAN.PORT_Selector_reg[0] ,
\Use_BSCAN.PORT_Selector_reg[0]_0 ,
\command_reg[0] ,
\Use_Serial_Unified_Completion.completion_block_reg ,
\command_reg[6] ,
\Use_Serial_Unified_Completion.count_reg[0] );
output sync;
output p_22_out__0;
input D_0;
input CE;
input \Use_BSCAN.PORT_Selector_reg[0] ;
input \Use_BSCAN.PORT_Selector_reg[0]_0 ;
input \command_reg[0] ;
input \Use_Serial_Unified_Completion.completion_block_reg ;
input \command_reg[6] ;
input \Use_Serial_Unified_Completion.count_reg[0] ;
wire CE;
wire D_0;
wire \Use_BSCAN.PORT_Selector_reg[0] ;
wire \Use_BSCAN.PORT_Selector_reg[0]_0 ;
wire \Use_Serial_Unified_Completion.completion_block_reg ;
wire \Use_Serial_Unified_Completion.count_reg[0] ;
wire \command_reg[0] ;
wire \command_reg[6] ;
wire p_22_out__0;
wire sync;
LUT6 #(
.INIT(64'h000000008AAAAAAA))
\Use_Serial_Unified_Completion.mb_instr_overrun_i_3
(.I0(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.I1(sync),
.I2(\command_reg[0] ),
.I3(\Use_Serial_Unified_Completion.completion_block_reg ),
.I4(\command_reg[6] ),
.I5(\Use_Serial_Unified_Completion.count_reg[0] ),
.O(p_22_out__0));
(* XILINX_LEGACY_PRIM = "FDRE_1" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b1))
\Using_FPGA.Native
(.C(\Use_BSCAN.PORT_Selector_reg[0] ),
.CE(CE),
.D(1'b1),
.Q(sync),
.R(D_0));
endmodule
(* ORIG_REF_NAME = "MB_SRL16E" *)
module system_mdm_1_0_MB_SRL16E
(tdo,
Q,
\Use_BSCAN.PORT_Selector_reg[0] ,
\Use_BSCAN.PORT_Selector_reg[2] ,
\Use_BSCAN.PORT_Selector_reg[0]_0 ,
\command_reg[0] ,
\command_reg[5] ,
\command_reg[0]_0 ,
\command_reg[3] ,
\command_reg[4] ,
Dbg_TDO_0,
\Use_Serial_Unified_Completion.completion_status_reg[0] ,
config_TDO_2);
output tdo;
input [4:0]Q;
input \Use_BSCAN.PORT_Selector_reg[0] ;
input \Use_BSCAN.PORT_Selector_reg[2] ;
input [0:0]\Use_BSCAN.PORT_Selector_reg[0]_0 ;
input \command_reg[0] ;
input \command_reg[5] ;
input \command_reg[0]_0 ;
input \command_reg[3] ;
input [2:0]\command_reg[4] ;
input Dbg_TDO_0;
input [0:0]\Use_Serial_Unified_Completion.completion_status_reg[0] ;
input config_TDO_2;
wire Dbg_TDO_0;
wire [4:0]Q;
wire \Use_BSCAN.PORT_Selector_reg[0] ;
wire [0:0]\Use_BSCAN.PORT_Selector_reg[0]_0 ;
wire \Use_BSCAN.PORT_Selector_reg[2] ;
wire \Use_E2.BSCANE2_I_i_4_n_0 ;
wire \Use_E2.BSCANE2_I_i_8_n_0 ;
wire [0:0]\Use_Serial_Unified_Completion.completion_status_reg[0] ;
wire \Use_unisim.MB_SRL16E_I1_n_0 ;
wire \command_reg[0] ;
wire \command_reg[0]_0 ;
wire \command_reg[3] ;
wire [2:0]\command_reg[4] ;
wire \command_reg[5] ;
wire config_TDO_2;
wire tdo;
LUT6 #(
.INIT(64'hEEEEEEEAEAEAEAEA))
\Use_E2.BSCANE2_I_i_1
(.I0(\Use_BSCAN.PORT_Selector_reg[2] ),
.I1(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.I2(\command_reg[0] ),
.I3(\Use_E2.BSCANE2_I_i_4_n_0 ),
.I4(\command_reg[5] ),
.I5(\command_reg[0]_0 ),
.O(tdo));
LUT5 #(
.INIT(32'hFEEEBAAA))
\Use_E2.BSCANE2_I_i_4
(.I0(\command_reg[3] ),
.I1(\command_reg[4] [0]),
.I2(\command_reg[4] [2]),
.I3(\Use_E2.BSCANE2_I_i_8_n_0 ),
.I4(Dbg_TDO_0),
.O(\Use_E2.BSCANE2_I_i_4_n_0 ));
LUT5 #(
.INIT(32'hFACA0ACA))
\Use_E2.BSCANE2_I_i_8
(.I0(\Use_Serial_Unified_Completion.completion_status_reg[0] ),
.I1(\Use_unisim.MB_SRL16E_I1_n_0 ),
.I2(\command_reg[4] [1]),
.I3(Q[4]),
.I4(config_TDO_2),
.O(\Use_E2.BSCANE2_I_i_8_n_0 ));
(* box_type = "PRIMITIVE" *)
(* srl_name = "U0/\MDM_Core_I1/JTAG_CONTROL_I/Use_Config_SRL16E.SRL16E_1/Use_unisim.MB_SRL16E_I1 " *)
SRL16E #(
.INIT(16'h0167),
.IS_CLK_INVERTED(1'b0))
\Use_unisim.MB_SRL16E_I1
(.A0(Q[0]),
.A1(Q[1]),
.A2(Q[2]),
.A3(Q[3]),
.CE(1'b0),
.CLK(\Use_BSCAN.PORT_Selector_reg[0] ),
.D(1'b0),
.Q(\Use_unisim.MB_SRL16E_I1_n_0 ));
endmodule
(* ORIG_REF_NAME = "MB_SRL16E" *)
module system_mdm_1_0_MB_SRL16E__parameterized1
(config_TDO_2,
Q,
\Use_BSCAN.PORT_Selector_reg[0] );
output config_TDO_2;
input [3:0]Q;
input \Use_BSCAN.PORT_Selector_reg[0] ;
wire [3:0]Q;
wire \Use_BSCAN.PORT_Selector_reg[0] ;
wire config_TDO_2;
(* box_type = "PRIMITIVE" *)
(* srl_name = "U0/\MDM_Core_I1/JTAG_CONTROL_I/Use_Config_SRL16E.SRL16E_2/Use_unisim.MB_SRL16E_I1 " *)
SRL16E #(
.INIT(16'h4287),
.IS_CLK_INVERTED(1'b0))
\Use_unisim.MB_SRL16E_I1
(.A0(Q[0]),
.A1(Q[1]),
.A2(Q[2]),
.A3(Q[3]),
.CE(1'b0),
.CLK(\Use_BSCAN.PORT_Selector_reg[0] ),
.D(1'b0),
.Q(config_TDO_2));
endmodule
(* ORIG_REF_NAME = "MB_SRL16E" *)
module system_mdm_1_0_MB_SRL16E__parameterized3
(\tdi_shifter_reg[0] ,
Q,
\Use_BSCAN.PORT_Selector_reg[0] ,
\command_reg[1] ,
ID_TDO_2);
output \tdi_shifter_reg[0] ;
input [4:0]Q;
input \Use_BSCAN.PORT_Selector_reg[0] ;
input [5:0]\command_reg[1] ;
input ID_TDO_2;
wire ID_TDO_2;
wire [4:0]Q;
wire Q0_out;
wire \Use_BSCAN.PORT_Selector_reg[0] ;
wire \Use_E2.BSCANE2_I_i_9_n_0 ;
wire [5:0]\command_reg[1] ;
wire \tdi_shifter_reg[0] ;
LUT6 #(
.INIT(64'hFFFFFFFFFFFB88CC))
\Use_E2.BSCANE2_I_i_5
(.I0(\command_reg[1] [2]),
.I1(\command_reg[1] [1]),
.I2(\command_reg[1] [3]),
.I3(\command_reg[1] [4]),
.I4(\command_reg[1] [5]),
.I5(\Use_E2.BSCANE2_I_i_9_n_0 ),
.O(\tdi_shifter_reg[0] ));
LUT6 #(
.INIT(64'h0101010000000100))
\Use_E2.BSCANE2_I_i_9
(.I0(\command_reg[1] [1]),
.I1(\command_reg[1] [0]),
.I2(\command_reg[1] [2]),
.I3(Q0_out),
.I4(Q[4]),
.I5(ID_TDO_2),
.O(\Use_E2.BSCANE2_I_i_9_n_0 ));
(* box_type = "PRIMITIVE" *)
(* srl_name = "U0/\MDM_Core_I1/JTAG_CONTROL_I/Use_ID_SRL16E.SRL16E_ID_1/Use_unisim.MB_SRL16E_I1 " *)
SRL16E #(
.INIT(16'h4443),
.IS_CLK_INVERTED(1'b0))
\Use_unisim.MB_SRL16E_I1
(.A0(Q[0]),
.A1(Q[1]),
.A2(Q[2]),
.A3(Q[3]),
.CE(1'b0),
.CLK(\Use_BSCAN.PORT_Selector_reg[0] ),
.D(1'b0),
.Q(Q0_out));
endmodule
(* ORIG_REF_NAME = "MB_SRL16E" *)
module system_mdm_1_0_MB_SRL16E__parameterized5
(ID_TDO_2,
Q,
\Use_BSCAN.PORT_Selector_reg[0] );
output ID_TDO_2;
input [3:0]Q;
input \Use_BSCAN.PORT_Selector_reg[0] ;
wire ID_TDO_2;
wire [3:0]Q;
wire \Use_BSCAN.PORT_Selector_reg[0] ;
(* box_type = "PRIMITIVE" *)
(* srl_name = "U0/\MDM_Core_I1/JTAG_CONTROL_I/Use_ID_SRL16E.SRL16E_ID_2/Use_unisim.MB_SRL16E_I1 " *)
SRL16E #(
.INIT(16'h584D),
.IS_CLK_INVERTED(1'b0))
\Use_unisim.MB_SRL16E_I1
(.A0(Q[0]),
.A1(Q[1]),
.A2(Q[2]),
.A3(Q[3]),
.CE(1'b0),
.CLK(\Use_BSCAN.PORT_Selector_reg[0] ),
.D(1'b0),
.Q(ID_TDO_2));
endmodule
(* C_DATA_SIZE = "32" *) (* C_DBG_MEM_ACCESS = "0" *) (* C_DBG_REG_ACCESS = "0" *)
(* C_DEBUG_INTERFACE = "0" *) (* C_FAMILY = "artix7" *) (* C_INTERCONNECT = "2" *)
(* C_JTAG_CHAIN = "2" *) (* C_MB_DBG_PORTS = "1" *) (* C_M_AXIS_DATA_WIDTH = "32" *)
(* C_M_AXIS_ID_WIDTH = "7" *) (* C_M_AXI_ADDR_WIDTH = "32" *) (* C_M_AXI_DATA_WIDTH = "32" *)
(* C_M_AXI_THREAD_ID_WIDTH = "1" *) (* C_S_AXI_ACLK_FREQ_HZ = "100000000" *) (* C_S_AXI_ADDR_WIDTH = "4" *)
(* C_S_AXI_DATA_WIDTH = "32" *) (* C_TRACE_CLK_FREQ_HZ = "200000000" *) (* C_TRACE_CLK_OUT_PHASE = "90" *)
(* C_TRACE_DATA_WIDTH = "32" *) (* C_TRACE_OUTPUT = "0" *) (* C_USE_BSCAN = "0" *)
(* C_USE_CONFIG_RESET = "0" *) (* C_USE_CROSS_TRIGGER = "0" *) (* C_USE_UART = "0" *)
(* ORIG_REF_NAME = "MDM" *)
module system_mdm_1_0_MDM
(Config_Reset,
Scan_Reset_Sel,
Scan_Reset,
S_AXI_ACLK,
S_AXI_ARESETN,
M_AXI_ACLK,
M_AXI_ARESETN,
M_AXIS_ACLK,
M_AXIS_ARESETN,
Interrupt,
Ext_BRK,
Ext_NM_BRK,
Debug_SYS_Rst,
Trig_In_0,
Trig_Ack_In_0,
Trig_Out_0,
Trig_Ack_Out_0,
Trig_In_1,
Trig_Ack_In_1,
Trig_Out_1,
Trig_Ack_Out_1,
Trig_In_2,
Trig_Ack_In_2,
Trig_Out_2,
Trig_Ack_Out_2,
Trig_In_3,
Trig_Ack_In_3,
Trig_Out_3,
Trig_Ack_Out_3,
S_AXI_AWADDR,
S_AXI_AWVALID,
S_AXI_AWREADY,
S_AXI_WDATA,
S_AXI_WSTRB,
S_AXI_WVALID,
S_AXI_WREADY,
S_AXI_BRESP,
S_AXI_BVALID,
S_AXI_BREADY,
S_AXI_ARADDR,
S_AXI_ARVALID,
S_AXI_ARREADY,
S_AXI_RDATA,
S_AXI_RRESP,
S_AXI_RVALID,
S_AXI_RREADY,
M_AXI_AWID,
M_AXI_AWADDR,
M_AXI_AWLEN,
M_AXI_AWSIZE,
M_AXI_AWBURST,
M_AXI_AWLOCK,
M_AXI_AWCACHE,
M_AXI_AWPROT,
M_AXI_AWQOS,
M_AXI_AWVALID,
M_AXI_AWREADY,
M_AXI_WDATA,
M_AXI_WSTRB,
M_AXI_WLAST,
M_AXI_WVALID,
M_AXI_WREADY,
M_AXI_BRESP,
M_AXI_BID,
M_AXI_BVALID,
M_AXI_BREADY,
M_AXI_ARID,
M_AXI_ARADDR,
M_AXI_ARLEN,
M_AXI_ARSIZE,
M_AXI_ARBURST,
M_AXI_ARLOCK,
M_AXI_ARCACHE,
M_AXI_ARPROT,
M_AXI_ARQOS,
M_AXI_ARVALID,
M_AXI_ARREADY,
M_AXI_RID,
M_AXI_RDATA,
M_AXI_RRESP,
M_AXI_RLAST,
M_AXI_RVALID,
M_AXI_RREADY,
LMB_Data_Addr_0,
LMB_Data_Read_0,
LMB_Data_Write_0,
LMB_Addr_Strobe_0,
LMB_Read_Strobe_0,
LMB_Write_Strobe_0,
LMB_Ready_0,
LMB_Wait_0,
LMB_CE_0,
LMB_UE_0,
LMB_Byte_Enable_0,
LMB_Data_Addr_1,
LMB_Data_Read_1,
LMB_Data_Write_1,
LMB_Addr_Strobe_1,
LMB_Read_Strobe_1,
LMB_Write_Strobe_1,
LMB_Ready_1,
LMB_Wait_1,
LMB_CE_1,
LMB_UE_1,
LMB_Byte_Enable_1,
LMB_Data_Addr_2,
LMB_Data_Read_2,
LMB_Data_Write_2,
LMB_Addr_Strobe_2,
LMB_Read_Strobe_2,
LMB_Write_Strobe_2,
LMB_Ready_2,
LMB_Wait_2,
LMB_CE_2,
LMB_UE_2,
LMB_Byte_Enable_2,
LMB_Data_Addr_3,
LMB_Data_Read_3,
LMB_Data_Write_3,
LMB_Addr_Strobe_3,
LMB_Read_Strobe_3,
LMB_Write_Strobe_3,
LMB_Ready_3,
LMB_Wait_3,
LMB_CE_3,
LMB_UE_3,
LMB_Byte_Enable_3,
LMB_Data_Addr_4,
LMB_Data_Read_4,
LMB_Data_Write_4,
LMB_Addr_Strobe_4,
LMB_Read_Strobe_4,
LMB_Write_Strobe_4,
LMB_Ready_4,
LMB_Wait_4,
LMB_CE_4,
LMB_UE_4,
LMB_Byte_Enable_4,
LMB_Data_Addr_5,
LMB_Data_Read_5,
LMB_Data_Write_5,
LMB_Addr_Strobe_5,
LMB_Read_Strobe_5,
LMB_Write_Strobe_5,
LMB_Ready_5,
LMB_Wait_5,
LMB_CE_5,
LMB_UE_5,
LMB_Byte_Enable_5,
LMB_Data_Addr_6,
LMB_Data_Read_6,
LMB_Data_Write_6,
LMB_Addr_Strobe_6,
LMB_Read_Strobe_6,
LMB_Write_Strobe_6,
LMB_Ready_6,
LMB_Wait_6,
LMB_CE_6,
LMB_UE_6,
LMB_Byte_Enable_6,
LMB_Data_Addr_7,
LMB_Data_Read_7,
LMB_Data_Write_7,
LMB_Addr_Strobe_7,
LMB_Read_Strobe_7,
LMB_Write_Strobe_7,
LMB_Ready_7,
LMB_Wait_7,
LMB_CE_7,
LMB_UE_7,
LMB_Byte_Enable_7,
LMB_Data_Addr_8,
LMB_Data_Read_8,
LMB_Data_Write_8,
LMB_Addr_Strobe_8,
LMB_Read_Strobe_8,
LMB_Write_Strobe_8,
LMB_Ready_8,
LMB_Wait_8,
LMB_CE_8,
LMB_UE_8,
LMB_Byte_Enable_8,
LMB_Data_Addr_9,
LMB_Data_Read_9,
LMB_Data_Write_9,
LMB_Addr_Strobe_9,
LMB_Read_Strobe_9,
LMB_Write_Strobe_9,
LMB_Ready_9,
LMB_Wait_9,
LMB_CE_9,
LMB_UE_9,
LMB_Byte_Enable_9,
LMB_Data_Addr_10,
LMB_Data_Read_10,
LMB_Data_Write_10,
LMB_Addr_Strobe_10,
LMB_Read_Strobe_10,
LMB_Write_Strobe_10,
LMB_Ready_10,
LMB_Wait_10,
LMB_CE_10,
LMB_UE_10,
LMB_Byte_Enable_10,
LMB_Data_Addr_11,
LMB_Data_Read_11,
LMB_Data_Write_11,
LMB_Addr_Strobe_11,
LMB_Read_Strobe_11,
LMB_Write_Strobe_11,
LMB_Ready_11,
LMB_Wait_11,
LMB_CE_11,
LMB_UE_11,
LMB_Byte_Enable_11,
LMB_Data_Addr_12,
LMB_Data_Read_12,
LMB_Data_Write_12,
LMB_Addr_Strobe_12,
LMB_Read_Strobe_12,
LMB_Write_Strobe_12,
LMB_Ready_12,
LMB_Wait_12,
LMB_CE_12,
LMB_UE_12,
LMB_Byte_Enable_12,
LMB_Data_Addr_13,
LMB_Data_Read_13,
LMB_Data_Write_13,
LMB_Addr_Strobe_13,
LMB_Read_Strobe_13,
LMB_Write_Strobe_13,
LMB_Ready_13,
LMB_Wait_13,
LMB_CE_13,
LMB_UE_13,
LMB_Byte_Enable_13,
LMB_Data_Addr_14,
LMB_Data_Read_14,
LMB_Data_Write_14,
LMB_Addr_Strobe_14,
LMB_Read_Strobe_14,
LMB_Write_Strobe_14,
LMB_Ready_14,
LMB_Wait_14,
LMB_CE_14,
LMB_UE_14,
LMB_Byte_Enable_14,
LMB_Data_Addr_15,
LMB_Data_Read_15,
LMB_Data_Write_15,
LMB_Addr_Strobe_15,
LMB_Read_Strobe_15,
LMB_Write_Strobe_15,
LMB_Ready_15,
LMB_Wait_15,
LMB_CE_15,
LMB_UE_15,
LMB_Byte_Enable_15,
LMB_Data_Addr_16,
LMB_Data_Read_16,
LMB_Data_Write_16,
LMB_Addr_Strobe_16,
LMB_Read_Strobe_16,
LMB_Write_Strobe_16,
LMB_Ready_16,
LMB_Wait_16,
LMB_CE_16,
LMB_UE_16,
LMB_Byte_Enable_16,
LMB_Data_Addr_17,
LMB_Data_Read_17,
LMB_Data_Write_17,
LMB_Addr_Strobe_17,
LMB_Read_Strobe_17,
LMB_Write_Strobe_17,
LMB_Ready_17,
LMB_Wait_17,
LMB_CE_17,
LMB_UE_17,
LMB_Byte_Enable_17,
LMB_Data_Addr_18,
LMB_Data_Read_18,
LMB_Data_Write_18,
LMB_Addr_Strobe_18,
LMB_Read_Strobe_18,
LMB_Write_Strobe_18,
LMB_Ready_18,
LMB_Wait_18,
LMB_CE_18,
LMB_UE_18,
LMB_Byte_Enable_18,
LMB_Data_Addr_19,
LMB_Data_Read_19,
LMB_Data_Write_19,
LMB_Addr_Strobe_19,
LMB_Read_Strobe_19,
LMB_Write_Strobe_19,
LMB_Ready_19,
LMB_Wait_19,
LMB_CE_19,
LMB_UE_19,
LMB_Byte_Enable_19,
LMB_Data_Addr_20,
LMB_Data_Read_20,
LMB_Data_Write_20,
LMB_Addr_Strobe_20,
LMB_Read_Strobe_20,
LMB_Write_Strobe_20,
LMB_Ready_20,
LMB_Wait_20,
LMB_CE_20,
LMB_UE_20,
LMB_Byte_Enable_20,
LMB_Data_Addr_21,
LMB_Data_Read_21,
LMB_Data_Write_21,
LMB_Addr_Strobe_21,
LMB_Read_Strobe_21,
LMB_Write_Strobe_21,
LMB_Ready_21,
LMB_Wait_21,
LMB_CE_21,
LMB_UE_21,
LMB_Byte_Enable_21,
LMB_Data_Addr_22,
LMB_Data_Read_22,
LMB_Data_Write_22,
LMB_Addr_Strobe_22,
LMB_Read_Strobe_22,
LMB_Write_Strobe_22,
LMB_Ready_22,
LMB_Wait_22,
LMB_CE_22,
LMB_UE_22,
LMB_Byte_Enable_22,
LMB_Data_Addr_23,
LMB_Data_Read_23,
LMB_Data_Write_23,
LMB_Addr_Strobe_23,
LMB_Read_Strobe_23,
LMB_Write_Strobe_23,
LMB_Ready_23,
LMB_Wait_23,
LMB_CE_23,
LMB_UE_23,
LMB_Byte_Enable_23,
LMB_Data_Addr_24,
LMB_Data_Read_24,
LMB_Data_Write_24,
LMB_Addr_Strobe_24,
LMB_Read_Strobe_24,
LMB_Write_Strobe_24,
LMB_Ready_24,
LMB_Wait_24,
LMB_CE_24,
LMB_UE_24,
LMB_Byte_Enable_24,
LMB_Data_Addr_25,
LMB_Data_Read_25,
LMB_Data_Write_25,
LMB_Addr_Strobe_25,
LMB_Read_Strobe_25,
LMB_Write_Strobe_25,
LMB_Ready_25,
LMB_Wait_25,
LMB_CE_25,
LMB_UE_25,
LMB_Byte_Enable_25,
LMB_Data_Addr_26,
LMB_Data_Read_26,
LMB_Data_Write_26,
LMB_Addr_Strobe_26,
LMB_Read_Strobe_26,
LMB_Write_Strobe_26,
LMB_Ready_26,
LMB_Wait_26,
LMB_CE_26,
LMB_UE_26,
LMB_Byte_Enable_26,
LMB_Data_Addr_27,
LMB_Data_Read_27,
LMB_Data_Write_27,
LMB_Addr_Strobe_27,
LMB_Read_Strobe_27,
LMB_Write_Strobe_27,
LMB_Ready_27,
LMB_Wait_27,
LMB_CE_27,
LMB_UE_27,
LMB_Byte_Enable_27,
LMB_Data_Addr_28,
LMB_Data_Read_28,
LMB_Data_Write_28,
LMB_Addr_Strobe_28,
LMB_Read_Strobe_28,
LMB_Write_Strobe_28,
LMB_Ready_28,
LMB_Wait_28,
LMB_CE_28,
LMB_UE_28,
LMB_Byte_Enable_28,
LMB_Data_Addr_29,
LMB_Data_Read_29,
LMB_Data_Write_29,
LMB_Addr_Strobe_29,
LMB_Read_Strobe_29,
LMB_Write_Strobe_29,
LMB_Ready_29,
LMB_Wait_29,
LMB_CE_29,
LMB_UE_29,
LMB_Byte_Enable_29,
LMB_Data_Addr_30,
LMB_Data_Read_30,
LMB_Data_Write_30,
LMB_Addr_Strobe_30,
LMB_Read_Strobe_30,
LMB_Write_Strobe_30,
LMB_Ready_30,
LMB_Wait_30,
LMB_CE_30,
LMB_UE_30,
LMB_Byte_Enable_30,
LMB_Data_Addr_31,
LMB_Data_Read_31,
LMB_Data_Write_31,
LMB_Addr_Strobe_31,
LMB_Read_Strobe_31,
LMB_Write_Strobe_31,
LMB_Ready_31,
LMB_Wait_31,
LMB_CE_31,
LMB_UE_31,
LMB_Byte_Enable_31,
M_AXIS_TDATA,
M_AXIS_TID,
M_AXIS_TREADY,
M_AXIS_TVALID,
TRACE_CLK_OUT,
TRACE_CLK,
TRACE_CTL,
TRACE_DATA,
Dbg_Disable_0,
Dbg_Clk_0,
Dbg_TDI_0,
Dbg_TDO_0,
Dbg_Reg_En_0,
Dbg_Capture_0,
Dbg_Shift_0,
Dbg_Update_0,
Dbg_Rst_0,
Dbg_Trig_In_0,
Dbg_Trig_Ack_In_0,
Dbg_Trig_Out_0,
Dbg_Trig_Ack_Out_0,
Dbg_TrClk_0,
Dbg_TrData_0,
Dbg_TrReady_0,
Dbg_TrValid_0,
Dbg_AWADDR_0,
Dbg_AWVALID_0,
Dbg_AWREADY_0,
Dbg_WDATA_0,
Dbg_WVALID_0,
Dbg_WREADY_0,
Dbg_BRESP_0,
Dbg_BVALID_0,
Dbg_BREADY_0,
Dbg_ARADDR_0,
Dbg_ARVALID_0,
Dbg_ARREADY_0,
Dbg_RDATA_0,
Dbg_RRESP_0,
Dbg_RVALID_0,
Dbg_RREADY_0,
Dbg_Disable_1,
Dbg_Clk_1,
Dbg_TDI_1,
Dbg_TDO_1,
Dbg_Reg_En_1,
Dbg_Capture_1,
Dbg_Shift_1,
Dbg_Update_1,
Dbg_Rst_1,
Dbg_Trig_In_1,
Dbg_Trig_Ack_In_1,
Dbg_Trig_Out_1,
Dbg_Trig_Ack_Out_1,
Dbg_TrClk_1,
Dbg_TrData_1,
Dbg_TrReady_1,
Dbg_TrValid_1,
Dbg_AWADDR_1,
Dbg_AWVALID_1,
Dbg_AWREADY_1,
Dbg_WDATA_1,
Dbg_WVALID_1,
Dbg_WREADY_1,
Dbg_BRESP_1,
Dbg_BVALID_1,
Dbg_BREADY_1,
Dbg_ARADDR_1,
Dbg_ARVALID_1,
Dbg_ARREADY_1,
Dbg_RDATA_1,
Dbg_RRESP_1,
Dbg_RVALID_1,
Dbg_RREADY_1,
Dbg_Disable_2,
Dbg_Clk_2,
Dbg_TDI_2,
Dbg_TDO_2,
Dbg_Reg_En_2,
Dbg_Capture_2,
Dbg_Shift_2,
Dbg_Update_2,
Dbg_Rst_2,
Dbg_Trig_In_2,
Dbg_Trig_Ack_In_2,
Dbg_Trig_Out_2,
Dbg_Trig_Ack_Out_2,
Dbg_TrClk_2,
Dbg_TrData_2,
Dbg_TrReady_2,
Dbg_TrValid_2,
Dbg_AWADDR_2,
Dbg_AWVALID_2,
Dbg_AWREADY_2,
Dbg_WDATA_2,
Dbg_WVALID_2,
Dbg_WREADY_2,
Dbg_BRESP_2,
Dbg_BVALID_2,
Dbg_BREADY_2,
Dbg_ARADDR_2,
Dbg_ARVALID_2,
Dbg_ARREADY_2,
Dbg_RDATA_2,
Dbg_RRESP_2,
Dbg_RVALID_2,
Dbg_RREADY_2,
Dbg_Disable_3,
Dbg_Clk_3,
Dbg_TDI_3,
Dbg_TDO_3,
Dbg_Reg_En_3,
Dbg_Capture_3,
Dbg_Shift_3,
Dbg_Update_3,
Dbg_Rst_3,
Dbg_Trig_In_3,
Dbg_Trig_Ack_In_3,
Dbg_Trig_Out_3,
Dbg_Trig_Ack_Out_3,
Dbg_TrClk_3,
Dbg_TrData_3,
Dbg_TrReady_3,
Dbg_TrValid_3,
Dbg_AWADDR_3,
Dbg_AWVALID_3,
Dbg_AWREADY_3,
Dbg_WDATA_3,
Dbg_WVALID_3,
Dbg_WREADY_3,
Dbg_BRESP_3,
Dbg_BVALID_3,
Dbg_BREADY_3,
Dbg_ARADDR_3,
Dbg_ARVALID_3,
Dbg_ARREADY_3,
Dbg_RDATA_3,
Dbg_RRESP_3,
Dbg_RVALID_3,
Dbg_RREADY_3,
Dbg_Disable_4,
Dbg_Clk_4,
Dbg_TDI_4,
Dbg_TDO_4,
Dbg_Reg_En_4,
Dbg_Capture_4,
Dbg_Shift_4,
Dbg_Update_4,
Dbg_Rst_4,
Dbg_Trig_In_4,
Dbg_Trig_Ack_In_4,
Dbg_Trig_Out_4,
Dbg_Trig_Ack_Out_4,
Dbg_TrClk_4,
Dbg_TrData_4,
Dbg_TrReady_4,
Dbg_TrValid_4,
Dbg_AWADDR_4,
Dbg_AWVALID_4,
Dbg_AWREADY_4,
Dbg_WDATA_4,
Dbg_WVALID_4,
Dbg_WREADY_4,
Dbg_BRESP_4,
Dbg_BVALID_4,
Dbg_BREADY_4,
Dbg_ARADDR_4,
Dbg_ARVALID_4,
Dbg_ARREADY_4,
Dbg_RDATA_4,
Dbg_RRESP_4,
Dbg_RVALID_4,
Dbg_RREADY_4,
Dbg_Disable_5,
Dbg_Clk_5,
Dbg_TDI_5,
Dbg_TDO_5,
Dbg_Reg_En_5,
Dbg_Capture_5,
Dbg_Shift_5,
Dbg_Update_5,
Dbg_Rst_5,
Dbg_Trig_In_5,
Dbg_Trig_Ack_In_5,
Dbg_Trig_Out_5,
Dbg_Trig_Ack_Out_5,
Dbg_TrClk_5,
Dbg_TrData_5,
Dbg_TrReady_5,
Dbg_TrValid_5,
Dbg_AWADDR_5,
Dbg_AWVALID_5,
Dbg_AWREADY_5,
Dbg_WDATA_5,
Dbg_WVALID_5,
Dbg_WREADY_5,
Dbg_BRESP_5,
Dbg_BVALID_5,
Dbg_BREADY_5,
Dbg_ARADDR_5,
Dbg_ARVALID_5,
Dbg_ARREADY_5,
Dbg_RDATA_5,
Dbg_RRESP_5,
Dbg_RVALID_5,
Dbg_RREADY_5,
Dbg_Disable_6,
Dbg_Clk_6,
Dbg_TDI_6,
Dbg_TDO_6,
Dbg_Reg_En_6,
Dbg_Capture_6,
Dbg_Shift_6,
Dbg_Update_6,
Dbg_Rst_6,
Dbg_Trig_In_6,
Dbg_Trig_Ack_In_6,
Dbg_Trig_Out_6,
Dbg_Trig_Ack_Out_6,
Dbg_TrClk_6,
Dbg_TrData_6,
Dbg_TrReady_6,
Dbg_TrValid_6,
Dbg_AWADDR_6,
Dbg_AWVALID_6,
Dbg_AWREADY_6,
Dbg_WDATA_6,
Dbg_WVALID_6,
Dbg_WREADY_6,
Dbg_BRESP_6,
Dbg_BVALID_6,
Dbg_BREADY_6,
Dbg_ARADDR_6,
Dbg_ARVALID_6,
Dbg_ARREADY_6,
Dbg_RDATA_6,
Dbg_RRESP_6,
Dbg_RVALID_6,
Dbg_RREADY_6,
Dbg_Disable_7,
Dbg_Clk_7,
Dbg_TDI_7,
Dbg_TDO_7,
Dbg_Reg_En_7,
Dbg_Capture_7,
Dbg_Shift_7,
Dbg_Update_7,
Dbg_Rst_7,
Dbg_Trig_In_7,
Dbg_Trig_Ack_In_7,
Dbg_Trig_Out_7,
Dbg_Trig_Ack_Out_7,
Dbg_TrClk_7,
Dbg_TrData_7,
Dbg_TrReady_7,
Dbg_TrValid_7,
Dbg_AWADDR_7,
Dbg_AWVALID_7,
Dbg_AWREADY_7,
Dbg_WDATA_7,
Dbg_WVALID_7,
Dbg_WREADY_7,
Dbg_BRESP_7,
Dbg_BVALID_7,
Dbg_BREADY_7,
Dbg_ARADDR_7,
Dbg_ARVALID_7,
Dbg_ARREADY_7,
Dbg_RDATA_7,
Dbg_RRESP_7,
Dbg_RVALID_7,
Dbg_RREADY_7,
Dbg_Disable_8,
Dbg_Clk_8,
Dbg_TDI_8,
Dbg_TDO_8,
Dbg_Reg_En_8,
Dbg_Capture_8,
Dbg_Shift_8,
Dbg_Update_8,
Dbg_Rst_8,
Dbg_Trig_In_8,
Dbg_Trig_Ack_In_8,
Dbg_Trig_Out_8,
Dbg_Trig_Ack_Out_8,
Dbg_TrClk_8,
Dbg_TrData_8,
Dbg_TrReady_8,
Dbg_TrValid_8,
Dbg_AWADDR_8,
Dbg_AWVALID_8,
Dbg_AWREADY_8,
Dbg_WDATA_8,
Dbg_WVALID_8,
Dbg_WREADY_8,
Dbg_BRESP_8,
Dbg_BVALID_8,
Dbg_BREADY_8,
Dbg_ARADDR_8,
Dbg_ARVALID_8,
Dbg_ARREADY_8,
Dbg_RDATA_8,
Dbg_RRESP_8,
Dbg_RVALID_8,
Dbg_RREADY_8,
Dbg_Disable_9,
Dbg_Clk_9,
Dbg_TDI_9,
Dbg_TDO_9,
Dbg_Reg_En_9,
Dbg_Capture_9,
Dbg_Shift_9,
Dbg_Update_9,
Dbg_Rst_9,
Dbg_Trig_In_9,
Dbg_Trig_Ack_In_9,
Dbg_Trig_Out_9,
Dbg_Trig_Ack_Out_9,
Dbg_TrClk_9,
Dbg_TrData_9,
Dbg_TrReady_9,
Dbg_TrValid_9,
Dbg_AWADDR_9,
Dbg_AWVALID_9,
Dbg_AWREADY_9,
Dbg_WDATA_9,
Dbg_WVALID_9,
Dbg_WREADY_9,
Dbg_BRESP_9,
Dbg_BVALID_9,
Dbg_BREADY_9,
Dbg_ARADDR_9,
Dbg_ARVALID_9,
Dbg_ARREADY_9,
Dbg_RDATA_9,
Dbg_RRESP_9,
Dbg_RVALID_9,
Dbg_RREADY_9,
Dbg_Disable_10,
Dbg_Clk_10,
Dbg_TDI_10,
Dbg_TDO_10,
Dbg_Reg_En_10,
Dbg_Capture_10,
Dbg_Shift_10,
Dbg_Update_10,
Dbg_Rst_10,
Dbg_Trig_In_10,
Dbg_Trig_Ack_In_10,
Dbg_Trig_Out_10,
Dbg_Trig_Ack_Out_10,
Dbg_TrClk_10,
Dbg_TrData_10,
Dbg_TrReady_10,
Dbg_TrValid_10,
Dbg_AWADDR_10,
Dbg_AWVALID_10,
Dbg_AWREADY_10,
Dbg_WDATA_10,
Dbg_WVALID_10,
Dbg_WREADY_10,
Dbg_BRESP_10,
Dbg_BVALID_10,
Dbg_BREADY_10,
Dbg_ARADDR_10,
Dbg_ARVALID_10,
Dbg_ARREADY_10,
Dbg_RDATA_10,
Dbg_RRESP_10,
Dbg_RVALID_10,
Dbg_RREADY_10,
Dbg_Disable_11,
Dbg_Clk_11,
Dbg_TDI_11,
Dbg_TDO_11,
Dbg_Reg_En_11,
Dbg_Capture_11,
Dbg_Shift_11,
Dbg_Update_11,
Dbg_Rst_11,
Dbg_Trig_In_11,
Dbg_Trig_Ack_In_11,
Dbg_Trig_Out_11,
Dbg_Trig_Ack_Out_11,
Dbg_TrClk_11,
Dbg_TrData_11,
Dbg_TrReady_11,
Dbg_TrValid_11,
Dbg_AWADDR_11,
Dbg_AWVALID_11,
Dbg_AWREADY_11,
Dbg_WDATA_11,
Dbg_WVALID_11,
Dbg_WREADY_11,
Dbg_BRESP_11,
Dbg_BVALID_11,
Dbg_BREADY_11,
Dbg_ARADDR_11,
Dbg_ARVALID_11,
Dbg_ARREADY_11,
Dbg_RDATA_11,
Dbg_RRESP_11,
Dbg_RVALID_11,
Dbg_RREADY_11,
Dbg_Disable_12,
Dbg_Clk_12,
Dbg_TDI_12,
Dbg_TDO_12,
Dbg_Reg_En_12,
Dbg_Capture_12,
Dbg_Shift_12,
Dbg_Update_12,
Dbg_Rst_12,
Dbg_Trig_In_12,
Dbg_Trig_Ack_In_12,
Dbg_Trig_Out_12,
Dbg_Trig_Ack_Out_12,
Dbg_TrClk_12,
Dbg_TrData_12,
Dbg_TrReady_12,
Dbg_TrValid_12,
Dbg_AWADDR_12,
Dbg_AWVALID_12,
Dbg_AWREADY_12,
Dbg_WDATA_12,
Dbg_WVALID_12,
Dbg_WREADY_12,
Dbg_BRESP_12,
Dbg_BVALID_12,
Dbg_BREADY_12,
Dbg_ARADDR_12,
Dbg_ARVALID_12,
Dbg_ARREADY_12,
Dbg_RDATA_12,
Dbg_RRESP_12,
Dbg_RVALID_12,
Dbg_RREADY_12,
Dbg_Disable_13,
Dbg_Clk_13,
Dbg_TDI_13,
Dbg_TDO_13,
Dbg_Reg_En_13,
Dbg_Capture_13,
Dbg_Shift_13,
Dbg_Update_13,
Dbg_Rst_13,
Dbg_Trig_In_13,
Dbg_Trig_Ack_In_13,
Dbg_Trig_Out_13,
Dbg_Trig_Ack_Out_13,
Dbg_TrClk_13,
Dbg_TrData_13,
Dbg_TrReady_13,
Dbg_TrValid_13,
Dbg_AWADDR_13,
Dbg_AWVALID_13,
Dbg_AWREADY_13,
Dbg_WDATA_13,
Dbg_WVALID_13,
Dbg_WREADY_13,
Dbg_BRESP_13,
Dbg_BVALID_13,
Dbg_BREADY_13,
Dbg_ARADDR_13,
Dbg_ARVALID_13,
Dbg_ARREADY_13,
Dbg_RDATA_13,
Dbg_RRESP_13,
Dbg_RVALID_13,
Dbg_RREADY_13,
Dbg_Disable_14,
Dbg_Clk_14,
Dbg_TDI_14,
Dbg_TDO_14,
Dbg_Reg_En_14,
Dbg_Capture_14,
Dbg_Shift_14,
Dbg_Update_14,
Dbg_Rst_14,
Dbg_Trig_In_14,
Dbg_Trig_Ack_In_14,
Dbg_Trig_Out_14,
Dbg_Trig_Ack_Out_14,
Dbg_TrClk_14,
Dbg_TrData_14,
Dbg_TrReady_14,
Dbg_TrValid_14,
Dbg_AWADDR_14,
Dbg_AWVALID_14,
Dbg_AWREADY_14,
Dbg_WDATA_14,
Dbg_WVALID_14,
Dbg_WREADY_14,
Dbg_BRESP_14,
Dbg_BVALID_14,
Dbg_BREADY_14,
Dbg_ARADDR_14,
Dbg_ARVALID_14,
Dbg_ARREADY_14,
Dbg_RDATA_14,
Dbg_RRESP_14,
Dbg_RVALID_14,
Dbg_RREADY_14,
Dbg_Disable_15,
Dbg_Clk_15,
Dbg_TDI_15,
Dbg_TDO_15,
Dbg_Reg_En_15,
Dbg_Capture_15,
Dbg_Shift_15,
Dbg_Update_15,
Dbg_Rst_15,
Dbg_Trig_In_15,
Dbg_Trig_Ack_In_15,
Dbg_Trig_Out_15,
Dbg_Trig_Ack_Out_15,
Dbg_TrClk_15,
Dbg_TrData_15,
Dbg_TrReady_15,
Dbg_TrValid_15,
Dbg_AWADDR_15,
Dbg_AWVALID_15,
Dbg_AWREADY_15,
Dbg_WDATA_15,
Dbg_WVALID_15,
Dbg_WREADY_15,
Dbg_BRESP_15,
Dbg_BVALID_15,
Dbg_BREADY_15,
Dbg_ARADDR_15,
Dbg_ARVALID_15,
Dbg_ARREADY_15,
Dbg_RDATA_15,
Dbg_RRESP_15,
Dbg_RVALID_15,
Dbg_RREADY_15,
Dbg_Disable_16,
Dbg_Clk_16,
Dbg_TDI_16,
Dbg_TDO_16,
Dbg_Reg_En_16,
Dbg_Capture_16,
Dbg_Shift_16,
Dbg_Update_16,
Dbg_Rst_16,
Dbg_Trig_In_16,
Dbg_Trig_Ack_In_16,
Dbg_Trig_Out_16,
Dbg_Trig_Ack_Out_16,
Dbg_TrClk_16,
Dbg_TrData_16,
Dbg_TrReady_16,
Dbg_TrValid_16,
Dbg_AWADDR_16,
Dbg_AWVALID_16,
Dbg_AWREADY_16,
Dbg_WDATA_16,
Dbg_WVALID_16,
Dbg_WREADY_16,
Dbg_BRESP_16,
Dbg_BVALID_16,
Dbg_BREADY_16,
Dbg_ARADDR_16,
Dbg_ARVALID_16,
Dbg_ARREADY_16,
Dbg_RDATA_16,
Dbg_RRESP_16,
Dbg_RVALID_16,
Dbg_RREADY_16,
Dbg_Disable_17,
Dbg_Clk_17,
Dbg_TDI_17,
Dbg_TDO_17,
Dbg_Reg_En_17,
Dbg_Capture_17,
Dbg_Shift_17,
Dbg_Update_17,
Dbg_Rst_17,
Dbg_Trig_In_17,
Dbg_Trig_Ack_In_17,
Dbg_Trig_Out_17,
Dbg_Trig_Ack_Out_17,
Dbg_TrClk_17,
Dbg_TrData_17,
Dbg_TrReady_17,
Dbg_TrValid_17,
Dbg_AWADDR_17,
Dbg_AWVALID_17,
Dbg_AWREADY_17,
Dbg_WDATA_17,
Dbg_WVALID_17,
Dbg_WREADY_17,
Dbg_BRESP_17,
Dbg_BVALID_17,
Dbg_BREADY_17,
Dbg_ARADDR_17,
Dbg_ARVALID_17,
Dbg_ARREADY_17,
Dbg_RDATA_17,
Dbg_RRESP_17,
Dbg_RVALID_17,
Dbg_RREADY_17,
Dbg_Disable_18,
Dbg_Clk_18,
Dbg_TDI_18,
Dbg_TDO_18,
Dbg_Reg_En_18,
Dbg_Capture_18,
Dbg_Shift_18,
Dbg_Update_18,
Dbg_Rst_18,
Dbg_Trig_In_18,
Dbg_Trig_Ack_In_18,
Dbg_Trig_Out_18,
Dbg_Trig_Ack_Out_18,
Dbg_TrClk_18,
Dbg_TrData_18,
Dbg_TrReady_18,
Dbg_TrValid_18,
Dbg_AWADDR_18,
Dbg_AWVALID_18,
Dbg_AWREADY_18,
Dbg_WDATA_18,
Dbg_WVALID_18,
Dbg_WREADY_18,
Dbg_BRESP_18,
Dbg_BVALID_18,
Dbg_BREADY_18,
Dbg_ARADDR_18,
Dbg_ARVALID_18,
Dbg_ARREADY_18,
Dbg_RDATA_18,
Dbg_RRESP_18,
Dbg_RVALID_18,
Dbg_RREADY_18,
Dbg_Disable_19,
Dbg_Clk_19,
Dbg_TDI_19,
Dbg_TDO_19,
Dbg_Reg_En_19,
Dbg_Capture_19,
Dbg_Shift_19,
Dbg_Update_19,
Dbg_Rst_19,
Dbg_Trig_In_19,
Dbg_Trig_Ack_In_19,
Dbg_Trig_Out_19,
Dbg_Trig_Ack_Out_19,
Dbg_TrClk_19,
Dbg_TrData_19,
Dbg_TrReady_19,
Dbg_TrValid_19,
Dbg_AWADDR_19,
Dbg_AWVALID_19,
Dbg_AWREADY_19,
Dbg_WDATA_19,
Dbg_WVALID_19,
Dbg_WREADY_19,
Dbg_BRESP_19,
Dbg_BVALID_19,
Dbg_BREADY_19,
Dbg_ARADDR_19,
Dbg_ARVALID_19,
Dbg_ARREADY_19,
Dbg_RDATA_19,
Dbg_RRESP_19,
Dbg_RVALID_19,
Dbg_RREADY_19,
Dbg_Disable_20,
Dbg_Clk_20,
Dbg_TDI_20,
Dbg_TDO_20,
Dbg_Reg_En_20,
Dbg_Capture_20,
Dbg_Shift_20,
Dbg_Update_20,
Dbg_Rst_20,
Dbg_Trig_In_20,
Dbg_Trig_Ack_In_20,
Dbg_Trig_Out_20,
Dbg_Trig_Ack_Out_20,
Dbg_TrClk_20,
Dbg_TrData_20,
Dbg_TrReady_20,
Dbg_TrValid_20,
Dbg_AWADDR_20,
Dbg_AWVALID_20,
Dbg_AWREADY_20,
Dbg_WDATA_20,
Dbg_WVALID_20,
Dbg_WREADY_20,
Dbg_BRESP_20,
Dbg_BVALID_20,
Dbg_BREADY_20,
Dbg_ARADDR_20,
Dbg_ARVALID_20,
Dbg_ARREADY_20,
Dbg_RDATA_20,
Dbg_RRESP_20,
Dbg_RVALID_20,
Dbg_RREADY_20,
Dbg_Disable_21,
Dbg_Clk_21,
Dbg_TDI_21,
Dbg_TDO_21,
Dbg_Reg_En_21,
Dbg_Capture_21,
Dbg_Shift_21,
Dbg_Update_21,
Dbg_Rst_21,
Dbg_Trig_In_21,
Dbg_Trig_Ack_In_21,
Dbg_Trig_Out_21,
Dbg_Trig_Ack_Out_21,
Dbg_TrClk_21,
Dbg_TrData_21,
Dbg_TrReady_21,
Dbg_TrValid_21,
Dbg_AWADDR_21,
Dbg_AWVALID_21,
Dbg_AWREADY_21,
Dbg_WDATA_21,
Dbg_WVALID_21,
Dbg_WREADY_21,
Dbg_BRESP_21,
Dbg_BVALID_21,
Dbg_BREADY_21,
Dbg_ARADDR_21,
Dbg_ARVALID_21,
Dbg_ARREADY_21,
Dbg_RDATA_21,
Dbg_RRESP_21,
Dbg_RVALID_21,
Dbg_RREADY_21,
Dbg_Disable_22,
Dbg_Clk_22,
Dbg_TDI_22,
Dbg_TDO_22,
Dbg_Reg_En_22,
Dbg_Capture_22,
Dbg_Shift_22,
Dbg_Update_22,
Dbg_Rst_22,
Dbg_Trig_In_22,
Dbg_Trig_Ack_In_22,
Dbg_Trig_Out_22,
Dbg_Trig_Ack_Out_22,
Dbg_TrClk_22,
Dbg_TrData_22,
Dbg_TrReady_22,
Dbg_TrValid_22,
Dbg_AWADDR_22,
Dbg_AWVALID_22,
Dbg_AWREADY_22,
Dbg_WDATA_22,
Dbg_WVALID_22,
Dbg_WREADY_22,
Dbg_BRESP_22,
Dbg_BVALID_22,
Dbg_BREADY_22,
Dbg_ARADDR_22,
Dbg_ARVALID_22,
Dbg_ARREADY_22,
Dbg_RDATA_22,
Dbg_RRESP_22,
Dbg_RVALID_22,
Dbg_RREADY_22,
Dbg_Disable_23,
Dbg_Clk_23,
Dbg_TDI_23,
Dbg_TDO_23,
Dbg_Reg_En_23,
Dbg_Capture_23,
Dbg_Shift_23,
Dbg_Update_23,
Dbg_Rst_23,
Dbg_Trig_In_23,
Dbg_Trig_Ack_In_23,
Dbg_Trig_Out_23,
Dbg_Trig_Ack_Out_23,
Dbg_TrClk_23,
Dbg_TrData_23,
Dbg_TrReady_23,
Dbg_TrValid_23,
Dbg_AWADDR_23,
Dbg_AWVALID_23,
Dbg_AWREADY_23,
Dbg_WDATA_23,
Dbg_WVALID_23,
Dbg_WREADY_23,
Dbg_BRESP_23,
Dbg_BVALID_23,
Dbg_BREADY_23,
Dbg_ARADDR_23,
Dbg_ARVALID_23,
Dbg_ARREADY_23,
Dbg_RDATA_23,
Dbg_RRESP_23,
Dbg_RVALID_23,
Dbg_RREADY_23,
Dbg_Disable_24,
Dbg_Clk_24,
Dbg_TDI_24,
Dbg_TDO_24,
Dbg_Reg_En_24,
Dbg_Capture_24,
Dbg_Shift_24,
Dbg_Update_24,
Dbg_Rst_24,
Dbg_Trig_In_24,
Dbg_Trig_Ack_In_24,
Dbg_Trig_Out_24,
Dbg_Trig_Ack_Out_24,
Dbg_TrClk_24,
Dbg_TrData_24,
Dbg_TrReady_24,
Dbg_TrValid_24,
Dbg_AWADDR_24,
Dbg_AWVALID_24,
Dbg_AWREADY_24,
Dbg_WDATA_24,
Dbg_WVALID_24,
Dbg_WREADY_24,
Dbg_BRESP_24,
Dbg_BVALID_24,
Dbg_BREADY_24,
Dbg_ARADDR_24,
Dbg_ARVALID_24,
Dbg_ARREADY_24,
Dbg_RDATA_24,
Dbg_RRESP_24,
Dbg_RVALID_24,
Dbg_RREADY_24,
Dbg_Disable_25,
Dbg_Clk_25,
Dbg_TDI_25,
Dbg_TDO_25,
Dbg_Reg_En_25,
Dbg_Capture_25,
Dbg_Shift_25,
Dbg_Update_25,
Dbg_Rst_25,
Dbg_Trig_In_25,
Dbg_Trig_Ack_In_25,
Dbg_Trig_Out_25,
Dbg_Trig_Ack_Out_25,
Dbg_TrClk_25,
Dbg_TrData_25,
Dbg_TrReady_25,
Dbg_TrValid_25,
Dbg_AWADDR_25,
Dbg_AWVALID_25,
Dbg_AWREADY_25,
Dbg_WDATA_25,
Dbg_WVALID_25,
Dbg_WREADY_25,
Dbg_BRESP_25,
Dbg_BVALID_25,
Dbg_BREADY_25,
Dbg_ARADDR_25,
Dbg_ARVALID_25,
Dbg_ARREADY_25,
Dbg_RDATA_25,
Dbg_RRESP_25,
Dbg_RVALID_25,
Dbg_RREADY_25,
Dbg_Disable_26,
Dbg_Clk_26,
Dbg_TDI_26,
Dbg_TDO_26,
Dbg_Reg_En_26,
Dbg_Capture_26,
Dbg_Shift_26,
Dbg_Update_26,
Dbg_Rst_26,
Dbg_Trig_In_26,
Dbg_Trig_Ack_In_26,
Dbg_Trig_Out_26,
Dbg_Trig_Ack_Out_26,
Dbg_TrClk_26,
Dbg_TrData_26,
Dbg_TrReady_26,
Dbg_TrValid_26,
Dbg_AWADDR_26,
Dbg_AWVALID_26,
Dbg_AWREADY_26,
Dbg_WDATA_26,
Dbg_WVALID_26,
Dbg_WREADY_26,
Dbg_BRESP_26,
Dbg_BVALID_26,
Dbg_BREADY_26,
Dbg_ARADDR_26,
Dbg_ARVALID_26,
Dbg_ARREADY_26,
Dbg_RDATA_26,
Dbg_RRESP_26,
Dbg_RVALID_26,
Dbg_RREADY_26,
Dbg_Disable_27,
Dbg_Clk_27,
Dbg_TDI_27,
Dbg_TDO_27,
Dbg_Reg_En_27,
Dbg_Capture_27,
Dbg_Shift_27,
Dbg_Update_27,
Dbg_Rst_27,
Dbg_Trig_In_27,
Dbg_Trig_Ack_In_27,
Dbg_Trig_Out_27,
Dbg_Trig_Ack_Out_27,
Dbg_TrClk_27,
Dbg_TrData_27,
Dbg_TrReady_27,
Dbg_TrValid_27,
Dbg_AWADDR_27,
Dbg_AWVALID_27,
Dbg_AWREADY_27,
Dbg_WDATA_27,
Dbg_WVALID_27,
Dbg_WREADY_27,
Dbg_BRESP_27,
Dbg_BVALID_27,
Dbg_BREADY_27,
Dbg_ARADDR_27,
Dbg_ARVALID_27,
Dbg_ARREADY_27,
Dbg_RDATA_27,
Dbg_RRESP_27,
Dbg_RVALID_27,
Dbg_RREADY_27,
Dbg_Disable_28,
Dbg_Clk_28,
Dbg_TDI_28,
Dbg_TDO_28,
Dbg_Reg_En_28,
Dbg_Capture_28,
Dbg_Shift_28,
Dbg_Update_28,
Dbg_Rst_28,
Dbg_Trig_In_28,
Dbg_Trig_Ack_In_28,
Dbg_Trig_Out_28,
Dbg_Trig_Ack_Out_28,
Dbg_TrClk_28,
Dbg_TrData_28,
Dbg_TrReady_28,
Dbg_TrValid_28,
Dbg_AWADDR_28,
Dbg_AWVALID_28,
Dbg_AWREADY_28,
Dbg_WDATA_28,
Dbg_WVALID_28,
Dbg_WREADY_28,
Dbg_BRESP_28,
Dbg_BVALID_28,
Dbg_BREADY_28,
Dbg_ARADDR_28,
Dbg_ARVALID_28,
Dbg_ARREADY_28,
Dbg_RDATA_28,
Dbg_RRESP_28,
Dbg_RVALID_28,
Dbg_RREADY_28,
Dbg_Disable_29,
Dbg_Clk_29,
Dbg_TDI_29,
Dbg_TDO_29,
Dbg_Reg_En_29,
Dbg_Capture_29,
Dbg_Shift_29,
Dbg_Update_29,
Dbg_Rst_29,
Dbg_Trig_In_29,
Dbg_Trig_Ack_In_29,
Dbg_Trig_Out_29,
Dbg_Trig_Ack_Out_29,
Dbg_TrClk_29,
Dbg_TrData_29,
Dbg_TrReady_29,
Dbg_TrValid_29,
Dbg_AWADDR_29,
Dbg_AWVALID_29,
Dbg_AWREADY_29,
Dbg_WDATA_29,
Dbg_WVALID_29,
Dbg_WREADY_29,
Dbg_BRESP_29,
Dbg_BVALID_29,
Dbg_BREADY_29,
Dbg_ARADDR_29,
Dbg_ARVALID_29,
Dbg_ARREADY_29,
Dbg_RDATA_29,
Dbg_RRESP_29,
Dbg_RVALID_29,
Dbg_RREADY_29,
Dbg_Disable_30,
Dbg_Clk_30,
Dbg_TDI_30,
Dbg_TDO_30,
Dbg_Reg_En_30,
Dbg_Capture_30,
Dbg_Shift_30,
Dbg_Update_30,
Dbg_Rst_30,
Dbg_Trig_In_30,
Dbg_Trig_Ack_In_30,
Dbg_Trig_Out_30,
Dbg_Trig_Ack_Out_30,
Dbg_TrClk_30,
Dbg_TrData_30,
Dbg_TrReady_30,
Dbg_TrValid_30,
Dbg_AWADDR_30,
Dbg_AWVALID_30,
Dbg_AWREADY_30,
Dbg_WDATA_30,
Dbg_WVALID_30,
Dbg_WREADY_30,
Dbg_BRESP_30,
Dbg_BVALID_30,
Dbg_BREADY_30,
Dbg_ARADDR_30,
Dbg_ARVALID_30,
Dbg_ARREADY_30,
Dbg_RDATA_30,
Dbg_RRESP_30,
Dbg_RVALID_30,
Dbg_RREADY_30,
Dbg_Disable_31,
Dbg_Clk_31,
Dbg_TDI_31,
Dbg_TDO_31,
Dbg_Reg_En_31,
Dbg_Capture_31,
Dbg_Shift_31,
Dbg_Update_31,
Dbg_Rst_31,
Dbg_Trig_In_31,
Dbg_Trig_Ack_In_31,
Dbg_Trig_Out_31,
Dbg_Trig_Ack_Out_31,
Dbg_TrClk_31,
Dbg_TrData_31,
Dbg_TrReady_31,
Dbg_TrValid_31,
Dbg_AWADDR_31,
Dbg_AWVALID_31,
Dbg_AWREADY_31,
Dbg_WDATA_31,
Dbg_WVALID_31,
Dbg_WREADY_31,
Dbg_BRESP_31,
Dbg_BVALID_31,
Dbg_BREADY_31,
Dbg_ARADDR_31,
Dbg_ARVALID_31,
Dbg_ARREADY_31,
Dbg_RDATA_31,
Dbg_RRESP_31,
Dbg_RVALID_31,
Dbg_RREADY_31,
bscan_ext_tdi,
bscan_ext_reset,
bscan_ext_shift,
bscan_ext_update,
bscan_ext_capture,
bscan_ext_sel,
bscan_ext_drck,
bscan_ext_tdo,
Ext_JTAG_DRCK,
Ext_JTAG_RESET,
Ext_JTAG_SEL,
Ext_JTAG_CAPTURE,
Ext_JTAG_SHIFT,
Ext_JTAG_UPDATE,
Ext_JTAG_TDI,
Ext_JTAG_TDO);
input Config_Reset;
input Scan_Reset_Sel;
input Scan_Reset;
input S_AXI_ACLK;
input S_AXI_ARESETN;
input M_AXI_ACLK;
input M_AXI_ARESETN;
input M_AXIS_ACLK;
input M_AXIS_ARESETN;
output Interrupt;
output Ext_BRK;
output Ext_NM_BRK;
output Debug_SYS_Rst;
input Trig_In_0;
output Trig_Ack_In_0;
output Trig_Out_0;
input Trig_Ack_Out_0;
input Trig_In_1;
output Trig_Ack_In_1;
output Trig_Out_1;
input Trig_Ack_Out_1;
input Trig_In_2;
output Trig_Ack_In_2;
output Trig_Out_2;
input Trig_Ack_Out_2;
input Trig_In_3;
output Trig_Ack_In_3;
output Trig_Out_3;
input Trig_Ack_Out_3;
input [3:0]S_AXI_AWADDR;
input S_AXI_AWVALID;
output S_AXI_AWREADY;
input [31:0]S_AXI_WDATA;
input [3:0]S_AXI_WSTRB;
input S_AXI_WVALID;
output S_AXI_WREADY;
output [1:0]S_AXI_BRESP;
output S_AXI_BVALID;
input S_AXI_BREADY;
input [3:0]S_AXI_ARADDR;
input S_AXI_ARVALID;
output S_AXI_ARREADY;
output [31:0]S_AXI_RDATA;
output [1:0]S_AXI_RRESP;
output S_AXI_RVALID;
input S_AXI_RREADY;
output [0:0]M_AXI_AWID;
output [31:0]M_AXI_AWADDR;
output [7:0]M_AXI_AWLEN;
output [2:0]M_AXI_AWSIZE;
output [1:0]M_AXI_AWBURST;
output M_AXI_AWLOCK;
output [3:0]M_AXI_AWCACHE;
output [2:0]M_AXI_AWPROT;
output [3:0]M_AXI_AWQOS;
output M_AXI_AWVALID;
input M_AXI_AWREADY;
output [31:0]M_AXI_WDATA;
output [3:0]M_AXI_WSTRB;
output M_AXI_WLAST;
output M_AXI_WVALID;
input M_AXI_WREADY;
input [1:0]M_AXI_BRESP;
input [0:0]M_AXI_BID;
input M_AXI_BVALID;
output M_AXI_BREADY;
output [0:0]M_AXI_ARID;
output [31:0]M_AXI_ARADDR;
output [7:0]M_AXI_ARLEN;
output [2:0]M_AXI_ARSIZE;
output [1:0]M_AXI_ARBURST;
output M_AXI_ARLOCK;
output [3:0]M_AXI_ARCACHE;
output [2:0]M_AXI_ARPROT;
output [3:0]M_AXI_ARQOS;
output M_AXI_ARVALID;
input M_AXI_ARREADY;
input [0:0]M_AXI_RID;
input [31:0]M_AXI_RDATA;
input [1:0]M_AXI_RRESP;
input M_AXI_RLAST;
input M_AXI_RVALID;
output M_AXI_RREADY;
output [0:31]LMB_Data_Addr_0;
input [0:31]LMB_Data_Read_0;
output [0:31]LMB_Data_Write_0;
output LMB_Addr_Strobe_0;
output LMB_Read_Strobe_0;
output LMB_Write_Strobe_0;
input LMB_Ready_0;
input LMB_Wait_0;
input LMB_CE_0;
input LMB_UE_0;
output [0:3]LMB_Byte_Enable_0;
output [0:31]LMB_Data_Addr_1;
input [0:31]LMB_Data_Read_1;
output [0:31]LMB_Data_Write_1;
output LMB_Addr_Strobe_1;
output LMB_Read_Strobe_1;
output LMB_Write_Strobe_1;
input LMB_Ready_1;
input LMB_Wait_1;
input LMB_CE_1;
input LMB_UE_1;
output [0:3]LMB_Byte_Enable_1;
output [0:31]LMB_Data_Addr_2;
input [0:31]LMB_Data_Read_2;
output [0:31]LMB_Data_Write_2;
output LMB_Addr_Strobe_2;
output LMB_Read_Strobe_2;
output LMB_Write_Strobe_2;
input LMB_Ready_2;
input LMB_Wait_2;
input LMB_CE_2;
input LMB_UE_2;
output [0:3]LMB_Byte_Enable_2;
output [0:31]LMB_Data_Addr_3;
input [0:31]LMB_Data_Read_3;
output [0:31]LMB_Data_Write_3;
output LMB_Addr_Strobe_3;
output LMB_Read_Strobe_3;
output LMB_Write_Strobe_3;
input LMB_Ready_3;
input LMB_Wait_3;
input LMB_CE_3;
input LMB_UE_3;
output [0:3]LMB_Byte_Enable_3;
output [0:31]LMB_Data_Addr_4;
input [0:31]LMB_Data_Read_4;
output [0:31]LMB_Data_Write_4;
output LMB_Addr_Strobe_4;
output LMB_Read_Strobe_4;
output LMB_Write_Strobe_4;
input LMB_Ready_4;
input LMB_Wait_4;
input LMB_CE_4;
input LMB_UE_4;
output [0:3]LMB_Byte_Enable_4;
output [0:31]LMB_Data_Addr_5;
input [0:31]LMB_Data_Read_5;
output [0:31]LMB_Data_Write_5;
output LMB_Addr_Strobe_5;
output LMB_Read_Strobe_5;
output LMB_Write_Strobe_5;
input LMB_Ready_5;
input LMB_Wait_5;
input LMB_CE_5;
input LMB_UE_5;
output [0:3]LMB_Byte_Enable_5;
output [0:31]LMB_Data_Addr_6;
input [0:31]LMB_Data_Read_6;
output [0:31]LMB_Data_Write_6;
output LMB_Addr_Strobe_6;
output LMB_Read_Strobe_6;
output LMB_Write_Strobe_6;
input LMB_Ready_6;
input LMB_Wait_6;
input LMB_CE_6;
input LMB_UE_6;
output [0:3]LMB_Byte_Enable_6;
output [0:31]LMB_Data_Addr_7;
input [0:31]LMB_Data_Read_7;
output [0:31]LMB_Data_Write_7;
output LMB_Addr_Strobe_7;
output LMB_Read_Strobe_7;
output LMB_Write_Strobe_7;
input LMB_Ready_7;
input LMB_Wait_7;
input LMB_CE_7;
input LMB_UE_7;
output [0:3]LMB_Byte_Enable_7;
output [0:31]LMB_Data_Addr_8;
input [0:31]LMB_Data_Read_8;
output [0:31]LMB_Data_Write_8;
output LMB_Addr_Strobe_8;
output LMB_Read_Strobe_8;
output LMB_Write_Strobe_8;
input LMB_Ready_8;
input LMB_Wait_8;
input LMB_CE_8;
input LMB_UE_8;
output [0:3]LMB_Byte_Enable_8;
output [0:31]LMB_Data_Addr_9;
input [0:31]LMB_Data_Read_9;
output [0:31]LMB_Data_Write_9;
output LMB_Addr_Strobe_9;
output LMB_Read_Strobe_9;
output LMB_Write_Strobe_9;
input LMB_Ready_9;
input LMB_Wait_9;
input LMB_CE_9;
input LMB_UE_9;
output [0:3]LMB_Byte_Enable_9;
output [0:31]LMB_Data_Addr_10;
input [0:31]LMB_Data_Read_10;
output [0:31]LMB_Data_Write_10;
output LMB_Addr_Strobe_10;
output LMB_Read_Strobe_10;
output LMB_Write_Strobe_10;
input LMB_Ready_10;
input LMB_Wait_10;
input LMB_CE_10;
input LMB_UE_10;
output [0:3]LMB_Byte_Enable_10;
output [0:31]LMB_Data_Addr_11;
input [0:31]LMB_Data_Read_11;
output [0:31]LMB_Data_Write_11;
output LMB_Addr_Strobe_11;
output LMB_Read_Strobe_11;
output LMB_Write_Strobe_11;
input LMB_Ready_11;
input LMB_Wait_11;
input LMB_CE_11;
input LMB_UE_11;
output [0:3]LMB_Byte_Enable_11;
output [0:31]LMB_Data_Addr_12;
input [0:31]LMB_Data_Read_12;
output [0:31]LMB_Data_Write_12;
output LMB_Addr_Strobe_12;
output LMB_Read_Strobe_12;
output LMB_Write_Strobe_12;
input LMB_Ready_12;
input LMB_Wait_12;
input LMB_CE_12;
input LMB_UE_12;
output [0:3]LMB_Byte_Enable_12;
output [0:31]LMB_Data_Addr_13;
input [0:31]LMB_Data_Read_13;
output [0:31]LMB_Data_Write_13;
output LMB_Addr_Strobe_13;
output LMB_Read_Strobe_13;
output LMB_Write_Strobe_13;
input LMB_Ready_13;
input LMB_Wait_13;
input LMB_CE_13;
input LMB_UE_13;
output [0:3]LMB_Byte_Enable_13;
output [0:31]LMB_Data_Addr_14;
input [0:31]LMB_Data_Read_14;
output [0:31]LMB_Data_Write_14;
output LMB_Addr_Strobe_14;
output LMB_Read_Strobe_14;
output LMB_Write_Strobe_14;
input LMB_Ready_14;
input LMB_Wait_14;
input LMB_CE_14;
input LMB_UE_14;
output [0:3]LMB_Byte_Enable_14;
output [0:31]LMB_Data_Addr_15;
input [0:31]LMB_Data_Read_15;
output [0:31]LMB_Data_Write_15;
output LMB_Addr_Strobe_15;
output LMB_Read_Strobe_15;
output LMB_Write_Strobe_15;
input LMB_Ready_15;
input LMB_Wait_15;
input LMB_CE_15;
input LMB_UE_15;
output [0:3]LMB_Byte_Enable_15;
output [0:31]LMB_Data_Addr_16;
input [0:31]LMB_Data_Read_16;
output [0:31]LMB_Data_Write_16;
output LMB_Addr_Strobe_16;
output LMB_Read_Strobe_16;
output LMB_Write_Strobe_16;
input LMB_Ready_16;
input LMB_Wait_16;
input LMB_CE_16;
input LMB_UE_16;
output [0:3]LMB_Byte_Enable_16;
output [0:31]LMB_Data_Addr_17;
input [0:31]LMB_Data_Read_17;
output [0:31]LMB_Data_Write_17;
output LMB_Addr_Strobe_17;
output LMB_Read_Strobe_17;
output LMB_Write_Strobe_17;
input LMB_Ready_17;
input LMB_Wait_17;
input LMB_CE_17;
input LMB_UE_17;
output [0:3]LMB_Byte_Enable_17;
output [0:31]LMB_Data_Addr_18;
input [0:31]LMB_Data_Read_18;
output [0:31]LMB_Data_Write_18;
output LMB_Addr_Strobe_18;
output LMB_Read_Strobe_18;
output LMB_Write_Strobe_18;
input LMB_Ready_18;
input LMB_Wait_18;
input LMB_CE_18;
input LMB_UE_18;
output [0:3]LMB_Byte_Enable_18;
output [0:31]LMB_Data_Addr_19;
input [0:31]LMB_Data_Read_19;
output [0:31]LMB_Data_Write_19;
output LMB_Addr_Strobe_19;
output LMB_Read_Strobe_19;
output LMB_Write_Strobe_19;
input LMB_Ready_19;
input LMB_Wait_19;
input LMB_CE_19;
input LMB_UE_19;
output [0:3]LMB_Byte_Enable_19;
output [0:31]LMB_Data_Addr_20;
input [0:31]LMB_Data_Read_20;
output [0:31]LMB_Data_Write_20;
output LMB_Addr_Strobe_20;
output LMB_Read_Strobe_20;
output LMB_Write_Strobe_20;
input LMB_Ready_20;
input LMB_Wait_20;
input LMB_CE_20;
input LMB_UE_20;
output [0:3]LMB_Byte_Enable_20;
output [0:31]LMB_Data_Addr_21;
input [0:31]LMB_Data_Read_21;
output [0:31]LMB_Data_Write_21;
output LMB_Addr_Strobe_21;
output LMB_Read_Strobe_21;
output LMB_Write_Strobe_21;
input LMB_Ready_21;
input LMB_Wait_21;
input LMB_CE_21;
input LMB_UE_21;
output [0:3]LMB_Byte_Enable_21;
output [0:31]LMB_Data_Addr_22;
input [0:31]LMB_Data_Read_22;
output [0:31]LMB_Data_Write_22;
output LMB_Addr_Strobe_22;
output LMB_Read_Strobe_22;
output LMB_Write_Strobe_22;
input LMB_Ready_22;
input LMB_Wait_22;
input LMB_CE_22;
input LMB_UE_22;
output [0:3]LMB_Byte_Enable_22;
output [0:31]LMB_Data_Addr_23;
input [0:31]LMB_Data_Read_23;
output [0:31]LMB_Data_Write_23;
output LMB_Addr_Strobe_23;
output LMB_Read_Strobe_23;
output LMB_Write_Strobe_23;
input LMB_Ready_23;
input LMB_Wait_23;
input LMB_CE_23;
input LMB_UE_23;
output [0:3]LMB_Byte_Enable_23;
output [0:31]LMB_Data_Addr_24;
input [0:31]LMB_Data_Read_24;
output [0:31]LMB_Data_Write_24;
output LMB_Addr_Strobe_24;
output LMB_Read_Strobe_24;
output LMB_Write_Strobe_24;
input LMB_Ready_24;
input LMB_Wait_24;
input LMB_CE_24;
input LMB_UE_24;
output [0:3]LMB_Byte_Enable_24;
output [0:31]LMB_Data_Addr_25;
input [0:31]LMB_Data_Read_25;
output [0:31]LMB_Data_Write_25;
output LMB_Addr_Strobe_25;
output LMB_Read_Strobe_25;
output LMB_Write_Strobe_25;
input LMB_Ready_25;
input LMB_Wait_25;
input LMB_CE_25;
input LMB_UE_25;
output [0:3]LMB_Byte_Enable_25;
output [0:31]LMB_Data_Addr_26;
input [0:31]LMB_Data_Read_26;
output [0:31]LMB_Data_Write_26;
output LMB_Addr_Strobe_26;
output LMB_Read_Strobe_26;
output LMB_Write_Strobe_26;
input LMB_Ready_26;
input LMB_Wait_26;
input LMB_CE_26;
input LMB_UE_26;
output [0:3]LMB_Byte_Enable_26;
output [0:31]LMB_Data_Addr_27;
input [0:31]LMB_Data_Read_27;
output [0:31]LMB_Data_Write_27;
output LMB_Addr_Strobe_27;
output LMB_Read_Strobe_27;
output LMB_Write_Strobe_27;
input LMB_Ready_27;
input LMB_Wait_27;
input LMB_CE_27;
input LMB_UE_27;
output [0:3]LMB_Byte_Enable_27;
output [0:31]LMB_Data_Addr_28;
input [0:31]LMB_Data_Read_28;
output [0:31]LMB_Data_Write_28;
output LMB_Addr_Strobe_28;
output LMB_Read_Strobe_28;
output LMB_Write_Strobe_28;
input LMB_Ready_28;
input LMB_Wait_28;
input LMB_CE_28;
input LMB_UE_28;
output [0:3]LMB_Byte_Enable_28;
output [0:31]LMB_Data_Addr_29;
input [0:31]LMB_Data_Read_29;
output [0:31]LMB_Data_Write_29;
output LMB_Addr_Strobe_29;
output LMB_Read_Strobe_29;
output LMB_Write_Strobe_29;
input LMB_Ready_29;
input LMB_Wait_29;
input LMB_CE_29;
input LMB_UE_29;
output [0:3]LMB_Byte_Enable_29;
output [0:31]LMB_Data_Addr_30;
input [0:31]LMB_Data_Read_30;
output [0:31]LMB_Data_Write_30;
output LMB_Addr_Strobe_30;
output LMB_Read_Strobe_30;
output LMB_Write_Strobe_30;
input LMB_Ready_30;
input LMB_Wait_30;
input LMB_CE_30;
input LMB_UE_30;
output [0:3]LMB_Byte_Enable_30;
output [0:31]LMB_Data_Addr_31;
input [0:31]LMB_Data_Read_31;
output [0:31]LMB_Data_Write_31;
output LMB_Addr_Strobe_31;
output LMB_Read_Strobe_31;
output LMB_Write_Strobe_31;
input LMB_Ready_31;
input LMB_Wait_31;
input LMB_CE_31;
input LMB_UE_31;
output [0:3]LMB_Byte_Enable_31;
output [31:0]M_AXIS_TDATA;
output [6:0]M_AXIS_TID;
input M_AXIS_TREADY;
output M_AXIS_TVALID;
output TRACE_CLK_OUT;
input TRACE_CLK;
output TRACE_CTL;
output [31:0]TRACE_DATA;
output Dbg_Disable_0;
output Dbg_Clk_0;
output Dbg_TDI_0;
input Dbg_TDO_0;
output [0:7]Dbg_Reg_En_0;
output Dbg_Capture_0;
output Dbg_Shift_0;
output Dbg_Update_0;
output Dbg_Rst_0;
input [0:7]Dbg_Trig_In_0;
output [0:7]Dbg_Trig_Ack_In_0;
output [0:7]Dbg_Trig_Out_0;
input [0:7]Dbg_Trig_Ack_Out_0;
output Dbg_TrClk_0;
input [0:35]Dbg_TrData_0;
output Dbg_TrReady_0;
input Dbg_TrValid_0;
output [14:2]Dbg_AWADDR_0;
output Dbg_AWVALID_0;
input Dbg_AWREADY_0;
output [31:0]Dbg_WDATA_0;
output Dbg_WVALID_0;
input Dbg_WREADY_0;
input [1:0]Dbg_BRESP_0;
input Dbg_BVALID_0;
output Dbg_BREADY_0;
output [14:2]Dbg_ARADDR_0;
output Dbg_ARVALID_0;
input Dbg_ARREADY_0;
input [31:0]Dbg_RDATA_0;
input [1:0]Dbg_RRESP_0;
input Dbg_RVALID_0;
output Dbg_RREADY_0;
output Dbg_Disable_1;
output Dbg_Clk_1;
output Dbg_TDI_1;
input Dbg_TDO_1;
output [0:7]Dbg_Reg_En_1;
output Dbg_Capture_1;
output Dbg_Shift_1;
output Dbg_Update_1;
output Dbg_Rst_1;
input [0:7]Dbg_Trig_In_1;
output [0:7]Dbg_Trig_Ack_In_1;
output [0:7]Dbg_Trig_Out_1;
input [0:7]Dbg_Trig_Ack_Out_1;
output Dbg_TrClk_1;
input [0:35]Dbg_TrData_1;
output Dbg_TrReady_1;
input Dbg_TrValid_1;
output [14:2]Dbg_AWADDR_1;
output Dbg_AWVALID_1;
input Dbg_AWREADY_1;
output [31:0]Dbg_WDATA_1;
output Dbg_WVALID_1;
input Dbg_WREADY_1;
input [1:0]Dbg_BRESP_1;
input Dbg_BVALID_1;
output Dbg_BREADY_1;
output [14:2]Dbg_ARADDR_1;
output Dbg_ARVALID_1;
input Dbg_ARREADY_1;
input [31:0]Dbg_RDATA_1;
input [1:0]Dbg_RRESP_1;
input Dbg_RVALID_1;
output Dbg_RREADY_1;
output Dbg_Disable_2;
output Dbg_Clk_2;
output Dbg_TDI_2;
input Dbg_TDO_2;
output [0:7]Dbg_Reg_En_2;
output Dbg_Capture_2;
output Dbg_Shift_2;
output Dbg_Update_2;
output Dbg_Rst_2;
input [0:7]Dbg_Trig_In_2;
output [0:7]Dbg_Trig_Ack_In_2;
output [0:7]Dbg_Trig_Out_2;
input [0:7]Dbg_Trig_Ack_Out_2;
output Dbg_TrClk_2;
input [0:35]Dbg_TrData_2;
output Dbg_TrReady_2;
input Dbg_TrValid_2;
output [14:2]Dbg_AWADDR_2;
output Dbg_AWVALID_2;
input Dbg_AWREADY_2;
output [31:0]Dbg_WDATA_2;
output Dbg_WVALID_2;
input Dbg_WREADY_2;
input [1:0]Dbg_BRESP_2;
input Dbg_BVALID_2;
output Dbg_BREADY_2;
output [14:2]Dbg_ARADDR_2;
output Dbg_ARVALID_2;
input Dbg_ARREADY_2;
input [31:0]Dbg_RDATA_2;
input [1:0]Dbg_RRESP_2;
input Dbg_RVALID_2;
output Dbg_RREADY_2;
output Dbg_Disable_3;
output Dbg_Clk_3;
output Dbg_TDI_3;
input Dbg_TDO_3;
output [0:7]Dbg_Reg_En_3;
output Dbg_Capture_3;
output Dbg_Shift_3;
output Dbg_Update_3;
output Dbg_Rst_3;
input [0:7]Dbg_Trig_In_3;
output [0:7]Dbg_Trig_Ack_In_3;
output [0:7]Dbg_Trig_Out_3;
input [0:7]Dbg_Trig_Ack_Out_3;
output Dbg_TrClk_3;
input [0:35]Dbg_TrData_3;
output Dbg_TrReady_3;
input Dbg_TrValid_3;
output [14:2]Dbg_AWADDR_3;
output Dbg_AWVALID_3;
input Dbg_AWREADY_3;
output [31:0]Dbg_WDATA_3;
output Dbg_WVALID_3;
input Dbg_WREADY_3;
input [1:0]Dbg_BRESP_3;
input Dbg_BVALID_3;
output Dbg_BREADY_3;
output [14:2]Dbg_ARADDR_3;
output Dbg_ARVALID_3;
input Dbg_ARREADY_3;
input [31:0]Dbg_RDATA_3;
input [1:0]Dbg_RRESP_3;
input Dbg_RVALID_3;
output Dbg_RREADY_3;
output Dbg_Disable_4;
output Dbg_Clk_4;
output Dbg_TDI_4;
input Dbg_TDO_4;
output [0:7]Dbg_Reg_En_4;
output Dbg_Capture_4;
output Dbg_Shift_4;
output Dbg_Update_4;
output Dbg_Rst_4;
input [0:7]Dbg_Trig_In_4;
output [0:7]Dbg_Trig_Ack_In_4;
output [0:7]Dbg_Trig_Out_4;
input [0:7]Dbg_Trig_Ack_Out_4;
output Dbg_TrClk_4;
input [0:35]Dbg_TrData_4;
output Dbg_TrReady_4;
input Dbg_TrValid_4;
output [14:2]Dbg_AWADDR_4;
output Dbg_AWVALID_4;
input Dbg_AWREADY_4;
output [31:0]Dbg_WDATA_4;
output Dbg_WVALID_4;
input Dbg_WREADY_4;
input [1:0]Dbg_BRESP_4;
input Dbg_BVALID_4;
output Dbg_BREADY_4;
output [14:2]Dbg_ARADDR_4;
output Dbg_ARVALID_4;
input Dbg_ARREADY_4;
input [31:0]Dbg_RDATA_4;
input [1:0]Dbg_RRESP_4;
input Dbg_RVALID_4;
output Dbg_RREADY_4;
output Dbg_Disable_5;
output Dbg_Clk_5;
output Dbg_TDI_5;
input Dbg_TDO_5;
output [0:7]Dbg_Reg_En_5;
output Dbg_Capture_5;
output Dbg_Shift_5;
output Dbg_Update_5;
output Dbg_Rst_5;
input [0:7]Dbg_Trig_In_5;
output [0:7]Dbg_Trig_Ack_In_5;
output [0:7]Dbg_Trig_Out_5;
input [0:7]Dbg_Trig_Ack_Out_5;
output Dbg_TrClk_5;
input [0:35]Dbg_TrData_5;
output Dbg_TrReady_5;
input Dbg_TrValid_5;
output [14:2]Dbg_AWADDR_5;
output Dbg_AWVALID_5;
input Dbg_AWREADY_5;
output [31:0]Dbg_WDATA_5;
output Dbg_WVALID_5;
input Dbg_WREADY_5;
input [1:0]Dbg_BRESP_5;
input Dbg_BVALID_5;
output Dbg_BREADY_5;
output [14:2]Dbg_ARADDR_5;
output Dbg_ARVALID_5;
input Dbg_ARREADY_5;
input [31:0]Dbg_RDATA_5;
input [1:0]Dbg_RRESP_5;
input Dbg_RVALID_5;
output Dbg_RREADY_5;
output Dbg_Disable_6;
output Dbg_Clk_6;
output Dbg_TDI_6;
input Dbg_TDO_6;
output [0:7]Dbg_Reg_En_6;
output Dbg_Capture_6;
output Dbg_Shift_6;
output Dbg_Update_6;
output Dbg_Rst_6;
input [0:7]Dbg_Trig_In_6;
output [0:7]Dbg_Trig_Ack_In_6;
output [0:7]Dbg_Trig_Out_6;
input [0:7]Dbg_Trig_Ack_Out_6;
output Dbg_TrClk_6;
input [0:35]Dbg_TrData_6;
output Dbg_TrReady_6;
input Dbg_TrValid_6;
output [14:2]Dbg_AWADDR_6;
output Dbg_AWVALID_6;
input Dbg_AWREADY_6;
output [31:0]Dbg_WDATA_6;
output Dbg_WVALID_6;
input Dbg_WREADY_6;
input [1:0]Dbg_BRESP_6;
input Dbg_BVALID_6;
output Dbg_BREADY_6;
output [14:2]Dbg_ARADDR_6;
output Dbg_ARVALID_6;
input Dbg_ARREADY_6;
input [31:0]Dbg_RDATA_6;
input [1:0]Dbg_RRESP_6;
input Dbg_RVALID_6;
output Dbg_RREADY_6;
output Dbg_Disable_7;
output Dbg_Clk_7;
output Dbg_TDI_7;
input Dbg_TDO_7;
output [0:7]Dbg_Reg_En_7;
output Dbg_Capture_7;
output Dbg_Shift_7;
output Dbg_Update_7;
output Dbg_Rst_7;
input [0:7]Dbg_Trig_In_7;
output [0:7]Dbg_Trig_Ack_In_7;
output [0:7]Dbg_Trig_Out_7;
input [0:7]Dbg_Trig_Ack_Out_7;
output Dbg_TrClk_7;
input [0:35]Dbg_TrData_7;
output Dbg_TrReady_7;
input Dbg_TrValid_7;
output [14:2]Dbg_AWADDR_7;
output Dbg_AWVALID_7;
input Dbg_AWREADY_7;
output [31:0]Dbg_WDATA_7;
output Dbg_WVALID_7;
input Dbg_WREADY_7;
input [1:0]Dbg_BRESP_7;
input Dbg_BVALID_7;
output Dbg_BREADY_7;
output [14:2]Dbg_ARADDR_7;
output Dbg_ARVALID_7;
input Dbg_ARREADY_7;
input [31:0]Dbg_RDATA_7;
input [1:0]Dbg_RRESP_7;
input Dbg_RVALID_7;
output Dbg_RREADY_7;
output Dbg_Disable_8;
output Dbg_Clk_8;
output Dbg_TDI_8;
input Dbg_TDO_8;
output [0:7]Dbg_Reg_En_8;
output Dbg_Capture_8;
output Dbg_Shift_8;
output Dbg_Update_8;
output Dbg_Rst_8;
input [0:7]Dbg_Trig_In_8;
output [0:7]Dbg_Trig_Ack_In_8;
output [0:7]Dbg_Trig_Out_8;
input [0:7]Dbg_Trig_Ack_Out_8;
output Dbg_TrClk_8;
input [0:35]Dbg_TrData_8;
output Dbg_TrReady_8;
input Dbg_TrValid_8;
output [14:2]Dbg_AWADDR_8;
output Dbg_AWVALID_8;
input Dbg_AWREADY_8;
output [31:0]Dbg_WDATA_8;
output Dbg_WVALID_8;
input Dbg_WREADY_8;
input [1:0]Dbg_BRESP_8;
input Dbg_BVALID_8;
output Dbg_BREADY_8;
output [14:2]Dbg_ARADDR_8;
output Dbg_ARVALID_8;
input Dbg_ARREADY_8;
input [31:0]Dbg_RDATA_8;
input [1:0]Dbg_RRESP_8;
input Dbg_RVALID_8;
output Dbg_RREADY_8;
output Dbg_Disable_9;
output Dbg_Clk_9;
output Dbg_TDI_9;
input Dbg_TDO_9;
output [0:7]Dbg_Reg_En_9;
output Dbg_Capture_9;
output Dbg_Shift_9;
output Dbg_Update_9;
output Dbg_Rst_9;
input [0:7]Dbg_Trig_In_9;
output [0:7]Dbg_Trig_Ack_In_9;
output [0:7]Dbg_Trig_Out_9;
input [0:7]Dbg_Trig_Ack_Out_9;
output Dbg_TrClk_9;
input [0:35]Dbg_TrData_9;
output Dbg_TrReady_9;
input Dbg_TrValid_9;
output [14:2]Dbg_AWADDR_9;
output Dbg_AWVALID_9;
input Dbg_AWREADY_9;
output [31:0]Dbg_WDATA_9;
output Dbg_WVALID_9;
input Dbg_WREADY_9;
input [1:0]Dbg_BRESP_9;
input Dbg_BVALID_9;
output Dbg_BREADY_9;
output [14:2]Dbg_ARADDR_9;
output Dbg_ARVALID_9;
input Dbg_ARREADY_9;
input [31:0]Dbg_RDATA_9;
input [1:0]Dbg_RRESP_9;
input Dbg_RVALID_9;
output Dbg_RREADY_9;
output Dbg_Disable_10;
output Dbg_Clk_10;
output Dbg_TDI_10;
input Dbg_TDO_10;
output [0:7]Dbg_Reg_En_10;
output Dbg_Capture_10;
output Dbg_Shift_10;
output Dbg_Update_10;
output Dbg_Rst_10;
input [0:7]Dbg_Trig_In_10;
output [0:7]Dbg_Trig_Ack_In_10;
output [0:7]Dbg_Trig_Out_10;
input [0:7]Dbg_Trig_Ack_Out_10;
output Dbg_TrClk_10;
input [0:35]Dbg_TrData_10;
output Dbg_TrReady_10;
input Dbg_TrValid_10;
output [14:2]Dbg_AWADDR_10;
output Dbg_AWVALID_10;
input Dbg_AWREADY_10;
output [31:0]Dbg_WDATA_10;
output Dbg_WVALID_10;
input Dbg_WREADY_10;
input [1:0]Dbg_BRESP_10;
input Dbg_BVALID_10;
output Dbg_BREADY_10;
output [14:2]Dbg_ARADDR_10;
output Dbg_ARVALID_10;
input Dbg_ARREADY_10;
input [31:0]Dbg_RDATA_10;
input [1:0]Dbg_RRESP_10;
input Dbg_RVALID_10;
output Dbg_RREADY_10;
output Dbg_Disable_11;
output Dbg_Clk_11;
output Dbg_TDI_11;
input Dbg_TDO_11;
output [0:7]Dbg_Reg_En_11;
output Dbg_Capture_11;
output Dbg_Shift_11;
output Dbg_Update_11;
output Dbg_Rst_11;
input [0:7]Dbg_Trig_In_11;
output [0:7]Dbg_Trig_Ack_In_11;
output [0:7]Dbg_Trig_Out_11;
input [0:7]Dbg_Trig_Ack_Out_11;
output Dbg_TrClk_11;
input [0:35]Dbg_TrData_11;
output Dbg_TrReady_11;
input Dbg_TrValid_11;
output [14:2]Dbg_AWADDR_11;
output Dbg_AWVALID_11;
input Dbg_AWREADY_11;
output [31:0]Dbg_WDATA_11;
output Dbg_WVALID_11;
input Dbg_WREADY_11;
input [1:0]Dbg_BRESP_11;
input Dbg_BVALID_11;
output Dbg_BREADY_11;
output [14:2]Dbg_ARADDR_11;
output Dbg_ARVALID_11;
input Dbg_ARREADY_11;
input [31:0]Dbg_RDATA_11;
input [1:0]Dbg_RRESP_11;
input Dbg_RVALID_11;
output Dbg_RREADY_11;
output Dbg_Disable_12;
output Dbg_Clk_12;
output Dbg_TDI_12;
input Dbg_TDO_12;
output [0:7]Dbg_Reg_En_12;
output Dbg_Capture_12;
output Dbg_Shift_12;
output Dbg_Update_12;
output Dbg_Rst_12;
input [0:7]Dbg_Trig_In_12;
output [0:7]Dbg_Trig_Ack_In_12;
output [0:7]Dbg_Trig_Out_12;
input [0:7]Dbg_Trig_Ack_Out_12;
output Dbg_TrClk_12;
input [0:35]Dbg_TrData_12;
output Dbg_TrReady_12;
input Dbg_TrValid_12;
output [14:2]Dbg_AWADDR_12;
output Dbg_AWVALID_12;
input Dbg_AWREADY_12;
output [31:0]Dbg_WDATA_12;
output Dbg_WVALID_12;
input Dbg_WREADY_12;
input [1:0]Dbg_BRESP_12;
input Dbg_BVALID_12;
output Dbg_BREADY_12;
output [14:2]Dbg_ARADDR_12;
output Dbg_ARVALID_12;
input Dbg_ARREADY_12;
input [31:0]Dbg_RDATA_12;
input [1:0]Dbg_RRESP_12;
input Dbg_RVALID_12;
output Dbg_RREADY_12;
output Dbg_Disable_13;
output Dbg_Clk_13;
output Dbg_TDI_13;
input Dbg_TDO_13;
output [0:7]Dbg_Reg_En_13;
output Dbg_Capture_13;
output Dbg_Shift_13;
output Dbg_Update_13;
output Dbg_Rst_13;
input [0:7]Dbg_Trig_In_13;
output [0:7]Dbg_Trig_Ack_In_13;
output [0:7]Dbg_Trig_Out_13;
input [0:7]Dbg_Trig_Ack_Out_13;
output Dbg_TrClk_13;
input [0:35]Dbg_TrData_13;
output Dbg_TrReady_13;
input Dbg_TrValid_13;
output [14:2]Dbg_AWADDR_13;
output Dbg_AWVALID_13;
input Dbg_AWREADY_13;
output [31:0]Dbg_WDATA_13;
output Dbg_WVALID_13;
input Dbg_WREADY_13;
input [1:0]Dbg_BRESP_13;
input Dbg_BVALID_13;
output Dbg_BREADY_13;
output [14:2]Dbg_ARADDR_13;
output Dbg_ARVALID_13;
input Dbg_ARREADY_13;
input [31:0]Dbg_RDATA_13;
input [1:0]Dbg_RRESP_13;
input Dbg_RVALID_13;
output Dbg_RREADY_13;
output Dbg_Disable_14;
output Dbg_Clk_14;
output Dbg_TDI_14;
input Dbg_TDO_14;
output [0:7]Dbg_Reg_En_14;
output Dbg_Capture_14;
output Dbg_Shift_14;
output Dbg_Update_14;
output Dbg_Rst_14;
input [0:7]Dbg_Trig_In_14;
output [0:7]Dbg_Trig_Ack_In_14;
output [0:7]Dbg_Trig_Out_14;
input [0:7]Dbg_Trig_Ack_Out_14;
output Dbg_TrClk_14;
input [0:35]Dbg_TrData_14;
output Dbg_TrReady_14;
input Dbg_TrValid_14;
output [14:2]Dbg_AWADDR_14;
output Dbg_AWVALID_14;
input Dbg_AWREADY_14;
output [31:0]Dbg_WDATA_14;
output Dbg_WVALID_14;
input Dbg_WREADY_14;
input [1:0]Dbg_BRESP_14;
input Dbg_BVALID_14;
output Dbg_BREADY_14;
output [14:2]Dbg_ARADDR_14;
output Dbg_ARVALID_14;
input Dbg_ARREADY_14;
input [31:0]Dbg_RDATA_14;
input [1:0]Dbg_RRESP_14;
input Dbg_RVALID_14;
output Dbg_RREADY_14;
output Dbg_Disable_15;
output Dbg_Clk_15;
output Dbg_TDI_15;
input Dbg_TDO_15;
output [0:7]Dbg_Reg_En_15;
output Dbg_Capture_15;
output Dbg_Shift_15;
output Dbg_Update_15;
output Dbg_Rst_15;
input [0:7]Dbg_Trig_In_15;
output [0:7]Dbg_Trig_Ack_In_15;
output [0:7]Dbg_Trig_Out_15;
input [0:7]Dbg_Trig_Ack_Out_15;
output Dbg_TrClk_15;
input [0:35]Dbg_TrData_15;
output Dbg_TrReady_15;
input Dbg_TrValid_15;
output [14:2]Dbg_AWADDR_15;
output Dbg_AWVALID_15;
input Dbg_AWREADY_15;
output [31:0]Dbg_WDATA_15;
output Dbg_WVALID_15;
input Dbg_WREADY_15;
input [1:0]Dbg_BRESP_15;
input Dbg_BVALID_15;
output Dbg_BREADY_15;
output [14:2]Dbg_ARADDR_15;
output Dbg_ARVALID_15;
input Dbg_ARREADY_15;
input [31:0]Dbg_RDATA_15;
input [1:0]Dbg_RRESP_15;
input Dbg_RVALID_15;
output Dbg_RREADY_15;
output Dbg_Disable_16;
output Dbg_Clk_16;
output Dbg_TDI_16;
input Dbg_TDO_16;
output [0:7]Dbg_Reg_En_16;
output Dbg_Capture_16;
output Dbg_Shift_16;
output Dbg_Update_16;
output Dbg_Rst_16;
input [0:7]Dbg_Trig_In_16;
output [0:7]Dbg_Trig_Ack_In_16;
output [0:7]Dbg_Trig_Out_16;
input [0:7]Dbg_Trig_Ack_Out_16;
output Dbg_TrClk_16;
input [0:35]Dbg_TrData_16;
output Dbg_TrReady_16;
input Dbg_TrValid_16;
output [14:2]Dbg_AWADDR_16;
output Dbg_AWVALID_16;
input Dbg_AWREADY_16;
output [31:0]Dbg_WDATA_16;
output Dbg_WVALID_16;
input Dbg_WREADY_16;
input [1:0]Dbg_BRESP_16;
input Dbg_BVALID_16;
output Dbg_BREADY_16;
output [14:2]Dbg_ARADDR_16;
output Dbg_ARVALID_16;
input Dbg_ARREADY_16;
input [31:0]Dbg_RDATA_16;
input [1:0]Dbg_RRESP_16;
input Dbg_RVALID_16;
output Dbg_RREADY_16;
output Dbg_Disable_17;
output Dbg_Clk_17;
output Dbg_TDI_17;
input Dbg_TDO_17;
output [0:7]Dbg_Reg_En_17;
output Dbg_Capture_17;
output Dbg_Shift_17;
output Dbg_Update_17;
output Dbg_Rst_17;
input [0:7]Dbg_Trig_In_17;
output [0:7]Dbg_Trig_Ack_In_17;
output [0:7]Dbg_Trig_Out_17;
input [0:7]Dbg_Trig_Ack_Out_17;
output Dbg_TrClk_17;
input [0:35]Dbg_TrData_17;
output Dbg_TrReady_17;
input Dbg_TrValid_17;
output [14:2]Dbg_AWADDR_17;
output Dbg_AWVALID_17;
input Dbg_AWREADY_17;
output [31:0]Dbg_WDATA_17;
output Dbg_WVALID_17;
input Dbg_WREADY_17;
input [1:0]Dbg_BRESP_17;
input Dbg_BVALID_17;
output Dbg_BREADY_17;
output [14:2]Dbg_ARADDR_17;
output Dbg_ARVALID_17;
input Dbg_ARREADY_17;
input [31:0]Dbg_RDATA_17;
input [1:0]Dbg_RRESP_17;
input Dbg_RVALID_17;
output Dbg_RREADY_17;
output Dbg_Disable_18;
output Dbg_Clk_18;
output Dbg_TDI_18;
input Dbg_TDO_18;
output [0:7]Dbg_Reg_En_18;
output Dbg_Capture_18;
output Dbg_Shift_18;
output Dbg_Update_18;
output Dbg_Rst_18;
input [0:7]Dbg_Trig_In_18;
output [0:7]Dbg_Trig_Ack_In_18;
output [0:7]Dbg_Trig_Out_18;
input [0:7]Dbg_Trig_Ack_Out_18;
output Dbg_TrClk_18;
input [0:35]Dbg_TrData_18;
output Dbg_TrReady_18;
input Dbg_TrValid_18;
output [14:2]Dbg_AWADDR_18;
output Dbg_AWVALID_18;
input Dbg_AWREADY_18;
output [31:0]Dbg_WDATA_18;
output Dbg_WVALID_18;
input Dbg_WREADY_18;
input [1:0]Dbg_BRESP_18;
input Dbg_BVALID_18;
output Dbg_BREADY_18;
output [14:2]Dbg_ARADDR_18;
output Dbg_ARVALID_18;
input Dbg_ARREADY_18;
input [31:0]Dbg_RDATA_18;
input [1:0]Dbg_RRESP_18;
input Dbg_RVALID_18;
output Dbg_RREADY_18;
output Dbg_Disable_19;
output Dbg_Clk_19;
output Dbg_TDI_19;
input Dbg_TDO_19;
output [0:7]Dbg_Reg_En_19;
output Dbg_Capture_19;
output Dbg_Shift_19;
output Dbg_Update_19;
output Dbg_Rst_19;
input [0:7]Dbg_Trig_In_19;
output [0:7]Dbg_Trig_Ack_In_19;
output [0:7]Dbg_Trig_Out_19;
input [0:7]Dbg_Trig_Ack_Out_19;
output Dbg_TrClk_19;
input [0:35]Dbg_TrData_19;
output Dbg_TrReady_19;
input Dbg_TrValid_19;
output [14:2]Dbg_AWADDR_19;
output Dbg_AWVALID_19;
input Dbg_AWREADY_19;
output [31:0]Dbg_WDATA_19;
output Dbg_WVALID_19;
input Dbg_WREADY_19;
input [1:0]Dbg_BRESP_19;
input Dbg_BVALID_19;
output Dbg_BREADY_19;
output [14:2]Dbg_ARADDR_19;
output Dbg_ARVALID_19;
input Dbg_ARREADY_19;
input [31:0]Dbg_RDATA_19;
input [1:0]Dbg_RRESP_19;
input Dbg_RVALID_19;
output Dbg_RREADY_19;
output Dbg_Disable_20;
output Dbg_Clk_20;
output Dbg_TDI_20;
input Dbg_TDO_20;
output [0:7]Dbg_Reg_En_20;
output Dbg_Capture_20;
output Dbg_Shift_20;
output Dbg_Update_20;
output Dbg_Rst_20;
input [0:7]Dbg_Trig_In_20;
output [0:7]Dbg_Trig_Ack_In_20;
output [0:7]Dbg_Trig_Out_20;
input [0:7]Dbg_Trig_Ack_Out_20;
output Dbg_TrClk_20;
input [0:35]Dbg_TrData_20;
output Dbg_TrReady_20;
input Dbg_TrValid_20;
output [14:2]Dbg_AWADDR_20;
output Dbg_AWVALID_20;
input Dbg_AWREADY_20;
output [31:0]Dbg_WDATA_20;
output Dbg_WVALID_20;
input Dbg_WREADY_20;
input [1:0]Dbg_BRESP_20;
input Dbg_BVALID_20;
output Dbg_BREADY_20;
output [14:2]Dbg_ARADDR_20;
output Dbg_ARVALID_20;
input Dbg_ARREADY_20;
input [31:0]Dbg_RDATA_20;
input [1:0]Dbg_RRESP_20;
input Dbg_RVALID_20;
output Dbg_RREADY_20;
output Dbg_Disable_21;
output Dbg_Clk_21;
output Dbg_TDI_21;
input Dbg_TDO_21;
output [0:7]Dbg_Reg_En_21;
output Dbg_Capture_21;
output Dbg_Shift_21;
output Dbg_Update_21;
output Dbg_Rst_21;
input [0:7]Dbg_Trig_In_21;
output [0:7]Dbg_Trig_Ack_In_21;
output [0:7]Dbg_Trig_Out_21;
input [0:7]Dbg_Trig_Ack_Out_21;
output Dbg_TrClk_21;
input [0:35]Dbg_TrData_21;
output Dbg_TrReady_21;
input Dbg_TrValid_21;
output [14:2]Dbg_AWADDR_21;
output Dbg_AWVALID_21;
input Dbg_AWREADY_21;
output [31:0]Dbg_WDATA_21;
output Dbg_WVALID_21;
input Dbg_WREADY_21;
input [1:0]Dbg_BRESP_21;
input Dbg_BVALID_21;
output Dbg_BREADY_21;
output [14:2]Dbg_ARADDR_21;
output Dbg_ARVALID_21;
input Dbg_ARREADY_21;
input [31:0]Dbg_RDATA_21;
input [1:0]Dbg_RRESP_21;
input Dbg_RVALID_21;
output Dbg_RREADY_21;
output Dbg_Disable_22;
output Dbg_Clk_22;
output Dbg_TDI_22;
input Dbg_TDO_22;
output [0:7]Dbg_Reg_En_22;
output Dbg_Capture_22;
output Dbg_Shift_22;
output Dbg_Update_22;
output Dbg_Rst_22;
input [0:7]Dbg_Trig_In_22;
output [0:7]Dbg_Trig_Ack_In_22;
output [0:7]Dbg_Trig_Out_22;
input [0:7]Dbg_Trig_Ack_Out_22;
output Dbg_TrClk_22;
input [0:35]Dbg_TrData_22;
output Dbg_TrReady_22;
input Dbg_TrValid_22;
output [14:2]Dbg_AWADDR_22;
output Dbg_AWVALID_22;
input Dbg_AWREADY_22;
output [31:0]Dbg_WDATA_22;
output Dbg_WVALID_22;
input Dbg_WREADY_22;
input [1:0]Dbg_BRESP_22;
input Dbg_BVALID_22;
output Dbg_BREADY_22;
output [14:2]Dbg_ARADDR_22;
output Dbg_ARVALID_22;
input Dbg_ARREADY_22;
input [31:0]Dbg_RDATA_22;
input [1:0]Dbg_RRESP_22;
input Dbg_RVALID_22;
output Dbg_RREADY_22;
output Dbg_Disable_23;
output Dbg_Clk_23;
output Dbg_TDI_23;
input Dbg_TDO_23;
output [0:7]Dbg_Reg_En_23;
output Dbg_Capture_23;
output Dbg_Shift_23;
output Dbg_Update_23;
output Dbg_Rst_23;
input [0:7]Dbg_Trig_In_23;
output [0:7]Dbg_Trig_Ack_In_23;
output [0:7]Dbg_Trig_Out_23;
input [0:7]Dbg_Trig_Ack_Out_23;
output Dbg_TrClk_23;
input [0:35]Dbg_TrData_23;
output Dbg_TrReady_23;
input Dbg_TrValid_23;
output [14:2]Dbg_AWADDR_23;
output Dbg_AWVALID_23;
input Dbg_AWREADY_23;
output [31:0]Dbg_WDATA_23;
output Dbg_WVALID_23;
input Dbg_WREADY_23;
input [1:0]Dbg_BRESP_23;
input Dbg_BVALID_23;
output Dbg_BREADY_23;
output [14:2]Dbg_ARADDR_23;
output Dbg_ARVALID_23;
input Dbg_ARREADY_23;
input [31:0]Dbg_RDATA_23;
input [1:0]Dbg_RRESP_23;
input Dbg_RVALID_23;
output Dbg_RREADY_23;
output Dbg_Disable_24;
output Dbg_Clk_24;
output Dbg_TDI_24;
input Dbg_TDO_24;
output [0:7]Dbg_Reg_En_24;
output Dbg_Capture_24;
output Dbg_Shift_24;
output Dbg_Update_24;
output Dbg_Rst_24;
input [0:7]Dbg_Trig_In_24;
output [0:7]Dbg_Trig_Ack_In_24;
output [0:7]Dbg_Trig_Out_24;
input [0:7]Dbg_Trig_Ack_Out_24;
output Dbg_TrClk_24;
input [0:35]Dbg_TrData_24;
output Dbg_TrReady_24;
input Dbg_TrValid_24;
output [14:2]Dbg_AWADDR_24;
output Dbg_AWVALID_24;
input Dbg_AWREADY_24;
output [31:0]Dbg_WDATA_24;
output Dbg_WVALID_24;
input Dbg_WREADY_24;
input [1:0]Dbg_BRESP_24;
input Dbg_BVALID_24;
output Dbg_BREADY_24;
output [14:2]Dbg_ARADDR_24;
output Dbg_ARVALID_24;
input Dbg_ARREADY_24;
input [31:0]Dbg_RDATA_24;
input [1:0]Dbg_RRESP_24;
input Dbg_RVALID_24;
output Dbg_RREADY_24;
output Dbg_Disable_25;
output Dbg_Clk_25;
output Dbg_TDI_25;
input Dbg_TDO_25;
output [0:7]Dbg_Reg_En_25;
output Dbg_Capture_25;
output Dbg_Shift_25;
output Dbg_Update_25;
output Dbg_Rst_25;
input [0:7]Dbg_Trig_In_25;
output [0:7]Dbg_Trig_Ack_In_25;
output [0:7]Dbg_Trig_Out_25;
input [0:7]Dbg_Trig_Ack_Out_25;
output Dbg_TrClk_25;
input [0:35]Dbg_TrData_25;
output Dbg_TrReady_25;
input Dbg_TrValid_25;
output [14:2]Dbg_AWADDR_25;
output Dbg_AWVALID_25;
input Dbg_AWREADY_25;
output [31:0]Dbg_WDATA_25;
output Dbg_WVALID_25;
input Dbg_WREADY_25;
input [1:0]Dbg_BRESP_25;
input Dbg_BVALID_25;
output Dbg_BREADY_25;
output [14:2]Dbg_ARADDR_25;
output Dbg_ARVALID_25;
input Dbg_ARREADY_25;
input [31:0]Dbg_RDATA_25;
input [1:0]Dbg_RRESP_25;
input Dbg_RVALID_25;
output Dbg_RREADY_25;
output Dbg_Disable_26;
output Dbg_Clk_26;
output Dbg_TDI_26;
input Dbg_TDO_26;
output [0:7]Dbg_Reg_En_26;
output Dbg_Capture_26;
output Dbg_Shift_26;
output Dbg_Update_26;
output Dbg_Rst_26;
input [0:7]Dbg_Trig_In_26;
output [0:7]Dbg_Trig_Ack_In_26;
output [0:7]Dbg_Trig_Out_26;
input [0:7]Dbg_Trig_Ack_Out_26;
output Dbg_TrClk_26;
input [0:35]Dbg_TrData_26;
output Dbg_TrReady_26;
input Dbg_TrValid_26;
output [14:2]Dbg_AWADDR_26;
output Dbg_AWVALID_26;
input Dbg_AWREADY_26;
output [31:0]Dbg_WDATA_26;
output Dbg_WVALID_26;
input Dbg_WREADY_26;
input [1:0]Dbg_BRESP_26;
input Dbg_BVALID_26;
output Dbg_BREADY_26;
output [14:2]Dbg_ARADDR_26;
output Dbg_ARVALID_26;
input Dbg_ARREADY_26;
input [31:0]Dbg_RDATA_26;
input [1:0]Dbg_RRESP_26;
input Dbg_RVALID_26;
output Dbg_RREADY_26;
output Dbg_Disable_27;
output Dbg_Clk_27;
output Dbg_TDI_27;
input Dbg_TDO_27;
output [0:7]Dbg_Reg_En_27;
output Dbg_Capture_27;
output Dbg_Shift_27;
output Dbg_Update_27;
output Dbg_Rst_27;
input [0:7]Dbg_Trig_In_27;
output [0:7]Dbg_Trig_Ack_In_27;
output [0:7]Dbg_Trig_Out_27;
input [0:7]Dbg_Trig_Ack_Out_27;
output Dbg_TrClk_27;
input [0:35]Dbg_TrData_27;
output Dbg_TrReady_27;
input Dbg_TrValid_27;
output [14:2]Dbg_AWADDR_27;
output Dbg_AWVALID_27;
input Dbg_AWREADY_27;
output [31:0]Dbg_WDATA_27;
output Dbg_WVALID_27;
input Dbg_WREADY_27;
input [1:0]Dbg_BRESP_27;
input Dbg_BVALID_27;
output Dbg_BREADY_27;
output [14:2]Dbg_ARADDR_27;
output Dbg_ARVALID_27;
input Dbg_ARREADY_27;
input [31:0]Dbg_RDATA_27;
input [1:0]Dbg_RRESP_27;
input Dbg_RVALID_27;
output Dbg_RREADY_27;
output Dbg_Disable_28;
output Dbg_Clk_28;
output Dbg_TDI_28;
input Dbg_TDO_28;
output [0:7]Dbg_Reg_En_28;
output Dbg_Capture_28;
output Dbg_Shift_28;
output Dbg_Update_28;
output Dbg_Rst_28;
input [0:7]Dbg_Trig_In_28;
output [0:7]Dbg_Trig_Ack_In_28;
output [0:7]Dbg_Trig_Out_28;
input [0:7]Dbg_Trig_Ack_Out_28;
output Dbg_TrClk_28;
input [0:35]Dbg_TrData_28;
output Dbg_TrReady_28;
input Dbg_TrValid_28;
output [14:2]Dbg_AWADDR_28;
output Dbg_AWVALID_28;
input Dbg_AWREADY_28;
output [31:0]Dbg_WDATA_28;
output Dbg_WVALID_28;
input Dbg_WREADY_28;
input [1:0]Dbg_BRESP_28;
input Dbg_BVALID_28;
output Dbg_BREADY_28;
output [14:2]Dbg_ARADDR_28;
output Dbg_ARVALID_28;
input Dbg_ARREADY_28;
input [31:0]Dbg_RDATA_28;
input [1:0]Dbg_RRESP_28;
input Dbg_RVALID_28;
output Dbg_RREADY_28;
output Dbg_Disable_29;
output Dbg_Clk_29;
output Dbg_TDI_29;
input Dbg_TDO_29;
output [0:7]Dbg_Reg_En_29;
output Dbg_Capture_29;
output Dbg_Shift_29;
output Dbg_Update_29;
output Dbg_Rst_29;
input [0:7]Dbg_Trig_In_29;
output [0:7]Dbg_Trig_Ack_In_29;
output [0:7]Dbg_Trig_Out_29;
input [0:7]Dbg_Trig_Ack_Out_29;
output Dbg_TrClk_29;
input [0:35]Dbg_TrData_29;
output Dbg_TrReady_29;
input Dbg_TrValid_29;
output [14:2]Dbg_AWADDR_29;
output Dbg_AWVALID_29;
input Dbg_AWREADY_29;
output [31:0]Dbg_WDATA_29;
output Dbg_WVALID_29;
input Dbg_WREADY_29;
input [1:0]Dbg_BRESP_29;
input Dbg_BVALID_29;
output Dbg_BREADY_29;
output [14:2]Dbg_ARADDR_29;
output Dbg_ARVALID_29;
input Dbg_ARREADY_29;
input [31:0]Dbg_RDATA_29;
input [1:0]Dbg_RRESP_29;
input Dbg_RVALID_29;
output Dbg_RREADY_29;
output Dbg_Disable_30;
output Dbg_Clk_30;
output Dbg_TDI_30;
input Dbg_TDO_30;
output [0:7]Dbg_Reg_En_30;
output Dbg_Capture_30;
output Dbg_Shift_30;
output Dbg_Update_30;
output Dbg_Rst_30;
input [0:7]Dbg_Trig_In_30;
output [0:7]Dbg_Trig_Ack_In_30;
output [0:7]Dbg_Trig_Out_30;
input [0:7]Dbg_Trig_Ack_Out_30;
output Dbg_TrClk_30;
input [0:35]Dbg_TrData_30;
output Dbg_TrReady_30;
input Dbg_TrValid_30;
output [14:2]Dbg_AWADDR_30;
output Dbg_AWVALID_30;
input Dbg_AWREADY_30;
output [31:0]Dbg_WDATA_30;
output Dbg_WVALID_30;
input Dbg_WREADY_30;
input [1:0]Dbg_BRESP_30;
input Dbg_BVALID_30;
output Dbg_BREADY_30;
output [14:2]Dbg_ARADDR_30;
output Dbg_ARVALID_30;
input Dbg_ARREADY_30;
input [31:0]Dbg_RDATA_30;
input [1:0]Dbg_RRESP_30;
input Dbg_RVALID_30;
output Dbg_RREADY_30;
output Dbg_Disable_31;
output Dbg_Clk_31;
output Dbg_TDI_31;
input Dbg_TDO_31;
output [0:7]Dbg_Reg_En_31;
output Dbg_Capture_31;
output Dbg_Shift_31;
output Dbg_Update_31;
output Dbg_Rst_31;
input [0:7]Dbg_Trig_In_31;
output [0:7]Dbg_Trig_Ack_In_31;
output [0:7]Dbg_Trig_Out_31;
input [0:7]Dbg_Trig_Ack_Out_31;
output Dbg_TrClk_31;
input [0:35]Dbg_TrData_31;
output Dbg_TrReady_31;
input Dbg_TrValid_31;
output [14:2]Dbg_AWADDR_31;
output Dbg_AWVALID_31;
input Dbg_AWREADY_31;
output [31:0]Dbg_WDATA_31;
output Dbg_WVALID_31;
input Dbg_WREADY_31;
input [1:0]Dbg_BRESP_31;
input Dbg_BVALID_31;
output Dbg_BREADY_31;
output [14:2]Dbg_ARADDR_31;
output Dbg_ARVALID_31;
input Dbg_ARREADY_31;
input [31:0]Dbg_RDATA_31;
input [1:0]Dbg_RRESP_31;
input Dbg_RVALID_31;
output Dbg_RREADY_31;
input bscan_ext_tdi;
input bscan_ext_reset;
input bscan_ext_shift;
input bscan_ext_update;
input bscan_ext_capture;
input bscan_ext_sel;
input bscan_ext_drck;
output bscan_ext_tdo;
output Ext_JTAG_DRCK;
output Ext_JTAG_RESET;
output Ext_JTAG_SEL;
output Ext_JTAG_CAPTURE;
output Ext_JTAG_SHIFT;
output Ext_JTAG_UPDATE;
output Ext_JTAG_TDI;
input Ext_JTAG_TDO;
wire \<const0> ;
wire \<const1> ;
wire Dbg_Clk_31;
wire Dbg_Disable_0;
wire [0:7]Dbg_Reg_En_0;
wire Dbg_Rst_0;
wire Dbg_Shift_0;
wire Dbg_TDO_0;
wire Dbg_Update_31;
wire Debug_SYS_Rst;
wire Ext_JTAG_CAPTURE;
wire Ext_JTAG_RESET;
wire Ext_JTAG_SEL;
wire Ext_JTAG_SHIFT;
wire Ext_JTAG_TDI;
wire Ext_JTAG_TDO;
wire Ext_NM_BRK;
wire [5:5]\JTAG_CONTROL_I/Use_Serial_Unified_Completion.count_reg ;
wire \JTAG_CONTROL_I/p_20_out__0 ;
wire \JTAG_CONTROL_I/p_43_out__0 ;
wire \JTAG_CONTROL_I/sel ;
wire MDM_Core_I1_n_0;
wire MDM_Core_I1_n_19;
wire Scan_Reset;
wire Scan_Reset_Sel;
wire \Use_E2.BSCAN_I_n_13 ;
wire \Use_E2.BSCAN_I_n_8 ;
wire drck_i;
wire [0:0]p_0_in;
wire [0:0]p_0_in__0;
wire [15:15]p_1_in;
wire sel;
wire sel_n_reset;
wire shift_n_reset;
wire tdo;
assign Dbg_ARADDR_0[14] = \<const0> ;
assign Dbg_ARADDR_0[13] = \<const0> ;
assign Dbg_ARADDR_0[12] = \<const0> ;
assign Dbg_ARADDR_0[11] = \<const0> ;
assign Dbg_ARADDR_0[10] = \<const0> ;
assign Dbg_ARADDR_0[9] = \<const0> ;
assign Dbg_ARADDR_0[8] = \<const0> ;
assign Dbg_ARADDR_0[7] = \<const0> ;
assign Dbg_ARADDR_0[6] = \<const0> ;
assign Dbg_ARADDR_0[5] = \<const0> ;
assign Dbg_ARADDR_0[4] = \<const0> ;
assign Dbg_ARADDR_0[3] = \<const0> ;
assign Dbg_ARADDR_0[2] = \<const0> ;
assign Dbg_ARADDR_1[14] = \<const0> ;
assign Dbg_ARADDR_1[13] = \<const0> ;
assign Dbg_ARADDR_1[12] = \<const0> ;
assign Dbg_ARADDR_1[11] = \<const0> ;
assign Dbg_ARADDR_1[10] = \<const0> ;
assign Dbg_ARADDR_1[9] = \<const0> ;
assign Dbg_ARADDR_1[8] = \<const0> ;
assign Dbg_ARADDR_1[7] = \<const0> ;
assign Dbg_ARADDR_1[6] = \<const0> ;
assign Dbg_ARADDR_1[5] = \<const0> ;
assign Dbg_ARADDR_1[4] = \<const0> ;
assign Dbg_ARADDR_1[3] = \<const0> ;
assign Dbg_ARADDR_1[2] = \<const0> ;
assign Dbg_ARADDR_10[14] = \<const0> ;
assign Dbg_ARADDR_10[13] = \<const0> ;
assign Dbg_ARADDR_10[12] = \<const0> ;
assign Dbg_ARADDR_10[11] = \<const0> ;
assign Dbg_ARADDR_10[10] = \<const0> ;
assign Dbg_ARADDR_10[9] = \<const0> ;
assign Dbg_ARADDR_10[8] = \<const0> ;
assign Dbg_ARADDR_10[7] = \<const0> ;
assign Dbg_ARADDR_10[6] = \<const0> ;
assign Dbg_ARADDR_10[5] = \<const0> ;
assign Dbg_ARADDR_10[4] = \<const0> ;
assign Dbg_ARADDR_10[3] = \<const0> ;
assign Dbg_ARADDR_10[2] = \<const0> ;
assign Dbg_ARADDR_11[14] = \<const0> ;
assign Dbg_ARADDR_11[13] = \<const0> ;
assign Dbg_ARADDR_11[12] = \<const0> ;
assign Dbg_ARADDR_11[11] = \<const0> ;
assign Dbg_ARADDR_11[10] = \<const0> ;
assign Dbg_ARADDR_11[9] = \<const0> ;
assign Dbg_ARADDR_11[8] = \<const0> ;
assign Dbg_ARADDR_11[7] = \<const0> ;
assign Dbg_ARADDR_11[6] = \<const0> ;
assign Dbg_ARADDR_11[5] = \<const0> ;
assign Dbg_ARADDR_11[4] = \<const0> ;
assign Dbg_ARADDR_11[3] = \<const0> ;
assign Dbg_ARADDR_11[2] = \<const0> ;
assign Dbg_ARADDR_12[14] = \<const0> ;
assign Dbg_ARADDR_12[13] = \<const0> ;
assign Dbg_ARADDR_12[12] = \<const0> ;
assign Dbg_ARADDR_12[11] = \<const0> ;
assign Dbg_ARADDR_12[10] = \<const0> ;
assign Dbg_ARADDR_12[9] = \<const0> ;
assign Dbg_ARADDR_12[8] = \<const0> ;
assign Dbg_ARADDR_12[7] = \<const0> ;
assign Dbg_ARADDR_12[6] = \<const0> ;
assign Dbg_ARADDR_12[5] = \<const0> ;
assign Dbg_ARADDR_12[4] = \<const0> ;
assign Dbg_ARADDR_12[3] = \<const0> ;
assign Dbg_ARADDR_12[2] = \<const0> ;
assign Dbg_ARADDR_13[14] = \<const0> ;
assign Dbg_ARADDR_13[13] = \<const0> ;
assign Dbg_ARADDR_13[12] = \<const0> ;
assign Dbg_ARADDR_13[11] = \<const0> ;
assign Dbg_ARADDR_13[10] = \<const0> ;
assign Dbg_ARADDR_13[9] = \<const0> ;
assign Dbg_ARADDR_13[8] = \<const0> ;
assign Dbg_ARADDR_13[7] = \<const0> ;
assign Dbg_ARADDR_13[6] = \<const0> ;
assign Dbg_ARADDR_13[5] = \<const0> ;
assign Dbg_ARADDR_13[4] = \<const0> ;
assign Dbg_ARADDR_13[3] = \<const0> ;
assign Dbg_ARADDR_13[2] = \<const0> ;
assign Dbg_ARADDR_14[14] = \<const0> ;
assign Dbg_ARADDR_14[13] = \<const0> ;
assign Dbg_ARADDR_14[12] = \<const0> ;
assign Dbg_ARADDR_14[11] = \<const0> ;
assign Dbg_ARADDR_14[10] = \<const0> ;
assign Dbg_ARADDR_14[9] = \<const0> ;
assign Dbg_ARADDR_14[8] = \<const0> ;
assign Dbg_ARADDR_14[7] = \<const0> ;
assign Dbg_ARADDR_14[6] = \<const0> ;
assign Dbg_ARADDR_14[5] = \<const0> ;
assign Dbg_ARADDR_14[4] = \<const0> ;
assign Dbg_ARADDR_14[3] = \<const0> ;
assign Dbg_ARADDR_14[2] = \<const0> ;
assign Dbg_ARADDR_15[14] = \<const0> ;
assign Dbg_ARADDR_15[13] = \<const0> ;
assign Dbg_ARADDR_15[12] = \<const0> ;
assign Dbg_ARADDR_15[11] = \<const0> ;
assign Dbg_ARADDR_15[10] = \<const0> ;
assign Dbg_ARADDR_15[9] = \<const0> ;
assign Dbg_ARADDR_15[8] = \<const0> ;
assign Dbg_ARADDR_15[7] = \<const0> ;
assign Dbg_ARADDR_15[6] = \<const0> ;
assign Dbg_ARADDR_15[5] = \<const0> ;
assign Dbg_ARADDR_15[4] = \<const0> ;
assign Dbg_ARADDR_15[3] = \<const0> ;
assign Dbg_ARADDR_15[2] = \<const0> ;
assign Dbg_ARADDR_16[14] = \<const0> ;
assign Dbg_ARADDR_16[13] = \<const0> ;
assign Dbg_ARADDR_16[12] = \<const0> ;
assign Dbg_ARADDR_16[11] = \<const0> ;
assign Dbg_ARADDR_16[10] = \<const0> ;
assign Dbg_ARADDR_16[9] = \<const0> ;
assign Dbg_ARADDR_16[8] = \<const0> ;
assign Dbg_ARADDR_16[7] = \<const0> ;
assign Dbg_ARADDR_16[6] = \<const0> ;
assign Dbg_ARADDR_16[5] = \<const0> ;
assign Dbg_ARADDR_16[4] = \<const0> ;
assign Dbg_ARADDR_16[3] = \<const0> ;
assign Dbg_ARADDR_16[2] = \<const0> ;
assign Dbg_ARADDR_17[14] = \<const0> ;
assign Dbg_ARADDR_17[13] = \<const0> ;
assign Dbg_ARADDR_17[12] = \<const0> ;
assign Dbg_ARADDR_17[11] = \<const0> ;
assign Dbg_ARADDR_17[10] = \<const0> ;
assign Dbg_ARADDR_17[9] = \<const0> ;
assign Dbg_ARADDR_17[8] = \<const0> ;
assign Dbg_ARADDR_17[7] = \<const0> ;
assign Dbg_ARADDR_17[6] = \<const0> ;
assign Dbg_ARADDR_17[5] = \<const0> ;
assign Dbg_ARADDR_17[4] = \<const0> ;
assign Dbg_ARADDR_17[3] = \<const0> ;
assign Dbg_ARADDR_17[2] = \<const0> ;
assign Dbg_ARADDR_18[14] = \<const0> ;
assign Dbg_ARADDR_18[13] = \<const0> ;
assign Dbg_ARADDR_18[12] = \<const0> ;
assign Dbg_ARADDR_18[11] = \<const0> ;
assign Dbg_ARADDR_18[10] = \<const0> ;
assign Dbg_ARADDR_18[9] = \<const0> ;
assign Dbg_ARADDR_18[8] = \<const0> ;
assign Dbg_ARADDR_18[7] = \<const0> ;
assign Dbg_ARADDR_18[6] = \<const0> ;
assign Dbg_ARADDR_18[5] = \<const0> ;
assign Dbg_ARADDR_18[4] = \<const0> ;
assign Dbg_ARADDR_18[3] = \<const0> ;
assign Dbg_ARADDR_18[2] = \<const0> ;
assign Dbg_ARADDR_19[14] = \<const0> ;
assign Dbg_ARADDR_19[13] = \<const0> ;
assign Dbg_ARADDR_19[12] = \<const0> ;
assign Dbg_ARADDR_19[11] = \<const0> ;
assign Dbg_ARADDR_19[10] = \<const0> ;
assign Dbg_ARADDR_19[9] = \<const0> ;
assign Dbg_ARADDR_19[8] = \<const0> ;
assign Dbg_ARADDR_19[7] = \<const0> ;
assign Dbg_ARADDR_19[6] = \<const0> ;
assign Dbg_ARADDR_19[5] = \<const0> ;
assign Dbg_ARADDR_19[4] = \<const0> ;
assign Dbg_ARADDR_19[3] = \<const0> ;
assign Dbg_ARADDR_19[2] = \<const0> ;
assign Dbg_ARADDR_2[14] = \<const0> ;
assign Dbg_ARADDR_2[13] = \<const0> ;
assign Dbg_ARADDR_2[12] = \<const0> ;
assign Dbg_ARADDR_2[11] = \<const0> ;
assign Dbg_ARADDR_2[10] = \<const0> ;
assign Dbg_ARADDR_2[9] = \<const0> ;
assign Dbg_ARADDR_2[8] = \<const0> ;
assign Dbg_ARADDR_2[7] = \<const0> ;
assign Dbg_ARADDR_2[6] = \<const0> ;
assign Dbg_ARADDR_2[5] = \<const0> ;
assign Dbg_ARADDR_2[4] = \<const0> ;
assign Dbg_ARADDR_2[3] = \<const0> ;
assign Dbg_ARADDR_2[2] = \<const0> ;
assign Dbg_ARADDR_20[14] = \<const0> ;
assign Dbg_ARADDR_20[13] = \<const0> ;
assign Dbg_ARADDR_20[12] = \<const0> ;
assign Dbg_ARADDR_20[11] = \<const0> ;
assign Dbg_ARADDR_20[10] = \<const0> ;
assign Dbg_ARADDR_20[9] = \<const0> ;
assign Dbg_ARADDR_20[8] = \<const0> ;
assign Dbg_ARADDR_20[7] = \<const0> ;
assign Dbg_ARADDR_20[6] = \<const0> ;
assign Dbg_ARADDR_20[5] = \<const0> ;
assign Dbg_ARADDR_20[4] = \<const0> ;
assign Dbg_ARADDR_20[3] = \<const0> ;
assign Dbg_ARADDR_20[2] = \<const0> ;
assign Dbg_ARADDR_21[14] = \<const0> ;
assign Dbg_ARADDR_21[13] = \<const0> ;
assign Dbg_ARADDR_21[12] = \<const0> ;
assign Dbg_ARADDR_21[11] = \<const0> ;
assign Dbg_ARADDR_21[10] = \<const0> ;
assign Dbg_ARADDR_21[9] = \<const0> ;
assign Dbg_ARADDR_21[8] = \<const0> ;
assign Dbg_ARADDR_21[7] = \<const0> ;
assign Dbg_ARADDR_21[6] = \<const0> ;
assign Dbg_ARADDR_21[5] = \<const0> ;
assign Dbg_ARADDR_21[4] = \<const0> ;
assign Dbg_ARADDR_21[3] = \<const0> ;
assign Dbg_ARADDR_21[2] = \<const0> ;
assign Dbg_ARADDR_22[14] = \<const0> ;
assign Dbg_ARADDR_22[13] = \<const0> ;
assign Dbg_ARADDR_22[12] = \<const0> ;
assign Dbg_ARADDR_22[11] = \<const0> ;
assign Dbg_ARADDR_22[10] = \<const0> ;
assign Dbg_ARADDR_22[9] = \<const0> ;
assign Dbg_ARADDR_22[8] = \<const0> ;
assign Dbg_ARADDR_22[7] = \<const0> ;
assign Dbg_ARADDR_22[6] = \<const0> ;
assign Dbg_ARADDR_22[5] = \<const0> ;
assign Dbg_ARADDR_22[4] = \<const0> ;
assign Dbg_ARADDR_22[3] = \<const0> ;
assign Dbg_ARADDR_22[2] = \<const0> ;
assign Dbg_ARADDR_23[14] = \<const0> ;
assign Dbg_ARADDR_23[13] = \<const0> ;
assign Dbg_ARADDR_23[12] = \<const0> ;
assign Dbg_ARADDR_23[11] = \<const0> ;
assign Dbg_ARADDR_23[10] = \<const0> ;
assign Dbg_ARADDR_23[9] = \<const0> ;
assign Dbg_ARADDR_23[8] = \<const0> ;
assign Dbg_ARADDR_23[7] = \<const0> ;
assign Dbg_ARADDR_23[6] = \<const0> ;
assign Dbg_ARADDR_23[5] = \<const0> ;
assign Dbg_ARADDR_23[4] = \<const0> ;
assign Dbg_ARADDR_23[3] = \<const0> ;
assign Dbg_ARADDR_23[2] = \<const0> ;
assign Dbg_ARADDR_24[14] = \<const0> ;
assign Dbg_ARADDR_24[13] = \<const0> ;
assign Dbg_ARADDR_24[12] = \<const0> ;
assign Dbg_ARADDR_24[11] = \<const0> ;
assign Dbg_ARADDR_24[10] = \<const0> ;
assign Dbg_ARADDR_24[9] = \<const0> ;
assign Dbg_ARADDR_24[8] = \<const0> ;
assign Dbg_ARADDR_24[7] = \<const0> ;
assign Dbg_ARADDR_24[6] = \<const0> ;
assign Dbg_ARADDR_24[5] = \<const0> ;
assign Dbg_ARADDR_24[4] = \<const0> ;
assign Dbg_ARADDR_24[3] = \<const0> ;
assign Dbg_ARADDR_24[2] = \<const0> ;
assign Dbg_ARADDR_25[14] = \<const0> ;
assign Dbg_ARADDR_25[13] = \<const0> ;
assign Dbg_ARADDR_25[12] = \<const0> ;
assign Dbg_ARADDR_25[11] = \<const0> ;
assign Dbg_ARADDR_25[10] = \<const0> ;
assign Dbg_ARADDR_25[9] = \<const0> ;
assign Dbg_ARADDR_25[8] = \<const0> ;
assign Dbg_ARADDR_25[7] = \<const0> ;
assign Dbg_ARADDR_25[6] = \<const0> ;
assign Dbg_ARADDR_25[5] = \<const0> ;
assign Dbg_ARADDR_25[4] = \<const0> ;
assign Dbg_ARADDR_25[3] = \<const0> ;
assign Dbg_ARADDR_25[2] = \<const0> ;
assign Dbg_ARADDR_26[14] = \<const0> ;
assign Dbg_ARADDR_26[13] = \<const0> ;
assign Dbg_ARADDR_26[12] = \<const0> ;
assign Dbg_ARADDR_26[11] = \<const0> ;
assign Dbg_ARADDR_26[10] = \<const0> ;
assign Dbg_ARADDR_26[9] = \<const0> ;
assign Dbg_ARADDR_26[8] = \<const0> ;
assign Dbg_ARADDR_26[7] = \<const0> ;
assign Dbg_ARADDR_26[6] = \<const0> ;
assign Dbg_ARADDR_26[5] = \<const0> ;
assign Dbg_ARADDR_26[4] = \<const0> ;
assign Dbg_ARADDR_26[3] = \<const0> ;
assign Dbg_ARADDR_26[2] = \<const0> ;
assign Dbg_ARADDR_27[14] = \<const0> ;
assign Dbg_ARADDR_27[13] = \<const0> ;
assign Dbg_ARADDR_27[12] = \<const0> ;
assign Dbg_ARADDR_27[11] = \<const0> ;
assign Dbg_ARADDR_27[10] = \<const0> ;
assign Dbg_ARADDR_27[9] = \<const0> ;
assign Dbg_ARADDR_27[8] = \<const0> ;
assign Dbg_ARADDR_27[7] = \<const0> ;
assign Dbg_ARADDR_27[6] = \<const0> ;
assign Dbg_ARADDR_27[5] = \<const0> ;
assign Dbg_ARADDR_27[4] = \<const0> ;
assign Dbg_ARADDR_27[3] = \<const0> ;
assign Dbg_ARADDR_27[2] = \<const0> ;
assign Dbg_ARADDR_28[14] = \<const0> ;
assign Dbg_ARADDR_28[13] = \<const0> ;
assign Dbg_ARADDR_28[12] = \<const0> ;
assign Dbg_ARADDR_28[11] = \<const0> ;
assign Dbg_ARADDR_28[10] = \<const0> ;
assign Dbg_ARADDR_28[9] = \<const0> ;
assign Dbg_ARADDR_28[8] = \<const0> ;
assign Dbg_ARADDR_28[7] = \<const0> ;
assign Dbg_ARADDR_28[6] = \<const0> ;
assign Dbg_ARADDR_28[5] = \<const0> ;
assign Dbg_ARADDR_28[4] = \<const0> ;
assign Dbg_ARADDR_28[3] = \<const0> ;
assign Dbg_ARADDR_28[2] = \<const0> ;
assign Dbg_ARADDR_29[14] = \<const0> ;
assign Dbg_ARADDR_29[13] = \<const0> ;
assign Dbg_ARADDR_29[12] = \<const0> ;
assign Dbg_ARADDR_29[11] = \<const0> ;
assign Dbg_ARADDR_29[10] = \<const0> ;
assign Dbg_ARADDR_29[9] = \<const0> ;
assign Dbg_ARADDR_29[8] = \<const0> ;
assign Dbg_ARADDR_29[7] = \<const0> ;
assign Dbg_ARADDR_29[6] = \<const0> ;
assign Dbg_ARADDR_29[5] = \<const0> ;
assign Dbg_ARADDR_29[4] = \<const0> ;
assign Dbg_ARADDR_29[3] = \<const0> ;
assign Dbg_ARADDR_29[2] = \<const0> ;
assign Dbg_ARADDR_3[14] = \<const0> ;
assign Dbg_ARADDR_3[13] = \<const0> ;
assign Dbg_ARADDR_3[12] = \<const0> ;
assign Dbg_ARADDR_3[11] = \<const0> ;
assign Dbg_ARADDR_3[10] = \<const0> ;
assign Dbg_ARADDR_3[9] = \<const0> ;
assign Dbg_ARADDR_3[8] = \<const0> ;
assign Dbg_ARADDR_3[7] = \<const0> ;
assign Dbg_ARADDR_3[6] = \<const0> ;
assign Dbg_ARADDR_3[5] = \<const0> ;
assign Dbg_ARADDR_3[4] = \<const0> ;
assign Dbg_ARADDR_3[3] = \<const0> ;
assign Dbg_ARADDR_3[2] = \<const0> ;
assign Dbg_ARADDR_30[14] = \<const0> ;
assign Dbg_ARADDR_30[13] = \<const0> ;
assign Dbg_ARADDR_30[12] = \<const0> ;
assign Dbg_ARADDR_30[11] = \<const0> ;
assign Dbg_ARADDR_30[10] = \<const0> ;
assign Dbg_ARADDR_30[9] = \<const0> ;
assign Dbg_ARADDR_30[8] = \<const0> ;
assign Dbg_ARADDR_30[7] = \<const0> ;
assign Dbg_ARADDR_30[6] = \<const0> ;
assign Dbg_ARADDR_30[5] = \<const0> ;
assign Dbg_ARADDR_30[4] = \<const0> ;
assign Dbg_ARADDR_30[3] = \<const0> ;
assign Dbg_ARADDR_30[2] = \<const0> ;
assign Dbg_ARADDR_31[14] = \<const0> ;
assign Dbg_ARADDR_31[13] = \<const0> ;
assign Dbg_ARADDR_31[12] = \<const0> ;
assign Dbg_ARADDR_31[11] = \<const0> ;
assign Dbg_ARADDR_31[10] = \<const0> ;
assign Dbg_ARADDR_31[9] = \<const0> ;
assign Dbg_ARADDR_31[8] = \<const0> ;
assign Dbg_ARADDR_31[7] = \<const0> ;
assign Dbg_ARADDR_31[6] = \<const0> ;
assign Dbg_ARADDR_31[5] = \<const0> ;
assign Dbg_ARADDR_31[4] = \<const0> ;
assign Dbg_ARADDR_31[3] = \<const0> ;
assign Dbg_ARADDR_31[2] = \<const0> ;
assign Dbg_ARADDR_4[14] = \<const0> ;
assign Dbg_ARADDR_4[13] = \<const0> ;
assign Dbg_ARADDR_4[12] = \<const0> ;
assign Dbg_ARADDR_4[11] = \<const0> ;
assign Dbg_ARADDR_4[10] = \<const0> ;
assign Dbg_ARADDR_4[9] = \<const0> ;
assign Dbg_ARADDR_4[8] = \<const0> ;
assign Dbg_ARADDR_4[7] = \<const0> ;
assign Dbg_ARADDR_4[6] = \<const0> ;
assign Dbg_ARADDR_4[5] = \<const0> ;
assign Dbg_ARADDR_4[4] = \<const0> ;
assign Dbg_ARADDR_4[3] = \<const0> ;
assign Dbg_ARADDR_4[2] = \<const0> ;
assign Dbg_ARADDR_5[14] = \<const0> ;
assign Dbg_ARADDR_5[13] = \<const0> ;
assign Dbg_ARADDR_5[12] = \<const0> ;
assign Dbg_ARADDR_5[11] = \<const0> ;
assign Dbg_ARADDR_5[10] = \<const0> ;
assign Dbg_ARADDR_5[9] = \<const0> ;
assign Dbg_ARADDR_5[8] = \<const0> ;
assign Dbg_ARADDR_5[7] = \<const0> ;
assign Dbg_ARADDR_5[6] = \<const0> ;
assign Dbg_ARADDR_5[5] = \<const0> ;
assign Dbg_ARADDR_5[4] = \<const0> ;
assign Dbg_ARADDR_5[3] = \<const0> ;
assign Dbg_ARADDR_5[2] = \<const0> ;
assign Dbg_ARADDR_6[14] = \<const0> ;
assign Dbg_ARADDR_6[13] = \<const0> ;
assign Dbg_ARADDR_6[12] = \<const0> ;
assign Dbg_ARADDR_6[11] = \<const0> ;
assign Dbg_ARADDR_6[10] = \<const0> ;
assign Dbg_ARADDR_6[9] = \<const0> ;
assign Dbg_ARADDR_6[8] = \<const0> ;
assign Dbg_ARADDR_6[7] = \<const0> ;
assign Dbg_ARADDR_6[6] = \<const0> ;
assign Dbg_ARADDR_6[5] = \<const0> ;
assign Dbg_ARADDR_6[4] = \<const0> ;
assign Dbg_ARADDR_6[3] = \<const0> ;
assign Dbg_ARADDR_6[2] = \<const0> ;
assign Dbg_ARADDR_7[14] = \<const0> ;
assign Dbg_ARADDR_7[13] = \<const0> ;
assign Dbg_ARADDR_7[12] = \<const0> ;
assign Dbg_ARADDR_7[11] = \<const0> ;
assign Dbg_ARADDR_7[10] = \<const0> ;
assign Dbg_ARADDR_7[9] = \<const0> ;
assign Dbg_ARADDR_7[8] = \<const0> ;
assign Dbg_ARADDR_7[7] = \<const0> ;
assign Dbg_ARADDR_7[6] = \<const0> ;
assign Dbg_ARADDR_7[5] = \<const0> ;
assign Dbg_ARADDR_7[4] = \<const0> ;
assign Dbg_ARADDR_7[3] = \<const0> ;
assign Dbg_ARADDR_7[2] = \<const0> ;
assign Dbg_ARADDR_8[14] = \<const0> ;
assign Dbg_ARADDR_8[13] = \<const0> ;
assign Dbg_ARADDR_8[12] = \<const0> ;
assign Dbg_ARADDR_8[11] = \<const0> ;
assign Dbg_ARADDR_8[10] = \<const0> ;
assign Dbg_ARADDR_8[9] = \<const0> ;
assign Dbg_ARADDR_8[8] = \<const0> ;
assign Dbg_ARADDR_8[7] = \<const0> ;
assign Dbg_ARADDR_8[6] = \<const0> ;
assign Dbg_ARADDR_8[5] = \<const0> ;
assign Dbg_ARADDR_8[4] = \<const0> ;
assign Dbg_ARADDR_8[3] = \<const0> ;
assign Dbg_ARADDR_8[2] = \<const0> ;
assign Dbg_ARADDR_9[14] = \<const0> ;
assign Dbg_ARADDR_9[13] = \<const0> ;
assign Dbg_ARADDR_9[12] = \<const0> ;
assign Dbg_ARADDR_9[11] = \<const0> ;
assign Dbg_ARADDR_9[10] = \<const0> ;
assign Dbg_ARADDR_9[9] = \<const0> ;
assign Dbg_ARADDR_9[8] = \<const0> ;
assign Dbg_ARADDR_9[7] = \<const0> ;
assign Dbg_ARADDR_9[6] = \<const0> ;
assign Dbg_ARADDR_9[5] = \<const0> ;
assign Dbg_ARADDR_9[4] = \<const0> ;
assign Dbg_ARADDR_9[3] = \<const0> ;
assign Dbg_ARADDR_9[2] = \<const0> ;
assign Dbg_ARVALID_0 = \<const0> ;
assign Dbg_ARVALID_1 = \<const0> ;
assign Dbg_ARVALID_10 = \<const0> ;
assign Dbg_ARVALID_11 = \<const0> ;
assign Dbg_ARVALID_12 = \<const0> ;
assign Dbg_ARVALID_13 = \<const0> ;
assign Dbg_ARVALID_14 = \<const0> ;
assign Dbg_ARVALID_15 = \<const0> ;
assign Dbg_ARVALID_16 = \<const0> ;
assign Dbg_ARVALID_17 = \<const0> ;
assign Dbg_ARVALID_18 = \<const0> ;
assign Dbg_ARVALID_19 = \<const0> ;
assign Dbg_ARVALID_2 = \<const0> ;
assign Dbg_ARVALID_20 = \<const0> ;
assign Dbg_ARVALID_21 = \<const0> ;
assign Dbg_ARVALID_22 = \<const0> ;
assign Dbg_ARVALID_23 = \<const0> ;
assign Dbg_ARVALID_24 = \<const0> ;
assign Dbg_ARVALID_25 = \<const0> ;
assign Dbg_ARVALID_26 = \<const0> ;
assign Dbg_ARVALID_27 = \<const0> ;
assign Dbg_ARVALID_28 = \<const0> ;
assign Dbg_ARVALID_29 = \<const0> ;
assign Dbg_ARVALID_3 = \<const0> ;
assign Dbg_ARVALID_30 = \<const0> ;
assign Dbg_ARVALID_31 = \<const0> ;
assign Dbg_ARVALID_4 = \<const0> ;
assign Dbg_ARVALID_5 = \<const0> ;
assign Dbg_ARVALID_6 = \<const0> ;
assign Dbg_ARVALID_7 = \<const0> ;
assign Dbg_ARVALID_8 = \<const0> ;
assign Dbg_ARVALID_9 = \<const0> ;
assign Dbg_AWADDR_0[14] = \<const0> ;
assign Dbg_AWADDR_0[13] = \<const0> ;
assign Dbg_AWADDR_0[12] = \<const0> ;
assign Dbg_AWADDR_0[11] = \<const0> ;
assign Dbg_AWADDR_0[10] = \<const0> ;
assign Dbg_AWADDR_0[9] = \<const0> ;
assign Dbg_AWADDR_0[8] = \<const0> ;
assign Dbg_AWADDR_0[7] = \<const0> ;
assign Dbg_AWADDR_0[6] = \<const0> ;
assign Dbg_AWADDR_0[5] = \<const0> ;
assign Dbg_AWADDR_0[4] = \<const0> ;
assign Dbg_AWADDR_0[3] = \<const0> ;
assign Dbg_AWADDR_0[2] = \<const0> ;
assign Dbg_AWADDR_1[14] = \<const0> ;
assign Dbg_AWADDR_1[13] = \<const0> ;
assign Dbg_AWADDR_1[12] = \<const0> ;
assign Dbg_AWADDR_1[11] = \<const0> ;
assign Dbg_AWADDR_1[10] = \<const0> ;
assign Dbg_AWADDR_1[9] = \<const0> ;
assign Dbg_AWADDR_1[8] = \<const0> ;
assign Dbg_AWADDR_1[7] = \<const0> ;
assign Dbg_AWADDR_1[6] = \<const0> ;
assign Dbg_AWADDR_1[5] = \<const0> ;
assign Dbg_AWADDR_1[4] = \<const0> ;
assign Dbg_AWADDR_1[3] = \<const0> ;
assign Dbg_AWADDR_1[2] = \<const0> ;
assign Dbg_AWADDR_10[14] = \<const0> ;
assign Dbg_AWADDR_10[13] = \<const0> ;
assign Dbg_AWADDR_10[12] = \<const0> ;
assign Dbg_AWADDR_10[11] = \<const0> ;
assign Dbg_AWADDR_10[10] = \<const0> ;
assign Dbg_AWADDR_10[9] = \<const0> ;
assign Dbg_AWADDR_10[8] = \<const0> ;
assign Dbg_AWADDR_10[7] = \<const0> ;
assign Dbg_AWADDR_10[6] = \<const0> ;
assign Dbg_AWADDR_10[5] = \<const0> ;
assign Dbg_AWADDR_10[4] = \<const0> ;
assign Dbg_AWADDR_10[3] = \<const0> ;
assign Dbg_AWADDR_10[2] = \<const0> ;
assign Dbg_AWADDR_11[14] = \<const0> ;
assign Dbg_AWADDR_11[13] = \<const0> ;
assign Dbg_AWADDR_11[12] = \<const0> ;
assign Dbg_AWADDR_11[11] = \<const0> ;
assign Dbg_AWADDR_11[10] = \<const0> ;
assign Dbg_AWADDR_11[9] = \<const0> ;
assign Dbg_AWADDR_11[8] = \<const0> ;
assign Dbg_AWADDR_11[7] = \<const0> ;
assign Dbg_AWADDR_11[6] = \<const0> ;
assign Dbg_AWADDR_11[5] = \<const0> ;
assign Dbg_AWADDR_11[4] = \<const0> ;
assign Dbg_AWADDR_11[3] = \<const0> ;
assign Dbg_AWADDR_11[2] = \<const0> ;
assign Dbg_AWADDR_12[14] = \<const0> ;
assign Dbg_AWADDR_12[13] = \<const0> ;
assign Dbg_AWADDR_12[12] = \<const0> ;
assign Dbg_AWADDR_12[11] = \<const0> ;
assign Dbg_AWADDR_12[10] = \<const0> ;
assign Dbg_AWADDR_12[9] = \<const0> ;
assign Dbg_AWADDR_12[8] = \<const0> ;
assign Dbg_AWADDR_12[7] = \<const0> ;
assign Dbg_AWADDR_12[6] = \<const0> ;
assign Dbg_AWADDR_12[5] = \<const0> ;
assign Dbg_AWADDR_12[4] = \<const0> ;
assign Dbg_AWADDR_12[3] = \<const0> ;
assign Dbg_AWADDR_12[2] = \<const0> ;
assign Dbg_AWADDR_13[14] = \<const0> ;
assign Dbg_AWADDR_13[13] = \<const0> ;
assign Dbg_AWADDR_13[12] = \<const0> ;
assign Dbg_AWADDR_13[11] = \<const0> ;
assign Dbg_AWADDR_13[10] = \<const0> ;
assign Dbg_AWADDR_13[9] = \<const0> ;
assign Dbg_AWADDR_13[8] = \<const0> ;
assign Dbg_AWADDR_13[7] = \<const0> ;
assign Dbg_AWADDR_13[6] = \<const0> ;
assign Dbg_AWADDR_13[5] = \<const0> ;
assign Dbg_AWADDR_13[4] = \<const0> ;
assign Dbg_AWADDR_13[3] = \<const0> ;
assign Dbg_AWADDR_13[2] = \<const0> ;
assign Dbg_AWADDR_14[14] = \<const0> ;
assign Dbg_AWADDR_14[13] = \<const0> ;
assign Dbg_AWADDR_14[12] = \<const0> ;
assign Dbg_AWADDR_14[11] = \<const0> ;
assign Dbg_AWADDR_14[10] = \<const0> ;
assign Dbg_AWADDR_14[9] = \<const0> ;
assign Dbg_AWADDR_14[8] = \<const0> ;
assign Dbg_AWADDR_14[7] = \<const0> ;
assign Dbg_AWADDR_14[6] = \<const0> ;
assign Dbg_AWADDR_14[5] = \<const0> ;
assign Dbg_AWADDR_14[4] = \<const0> ;
assign Dbg_AWADDR_14[3] = \<const0> ;
assign Dbg_AWADDR_14[2] = \<const0> ;
assign Dbg_AWADDR_15[14] = \<const0> ;
assign Dbg_AWADDR_15[13] = \<const0> ;
assign Dbg_AWADDR_15[12] = \<const0> ;
assign Dbg_AWADDR_15[11] = \<const0> ;
assign Dbg_AWADDR_15[10] = \<const0> ;
assign Dbg_AWADDR_15[9] = \<const0> ;
assign Dbg_AWADDR_15[8] = \<const0> ;
assign Dbg_AWADDR_15[7] = \<const0> ;
assign Dbg_AWADDR_15[6] = \<const0> ;
assign Dbg_AWADDR_15[5] = \<const0> ;
assign Dbg_AWADDR_15[4] = \<const0> ;
assign Dbg_AWADDR_15[3] = \<const0> ;
assign Dbg_AWADDR_15[2] = \<const0> ;
assign Dbg_AWADDR_16[14] = \<const0> ;
assign Dbg_AWADDR_16[13] = \<const0> ;
assign Dbg_AWADDR_16[12] = \<const0> ;
assign Dbg_AWADDR_16[11] = \<const0> ;
assign Dbg_AWADDR_16[10] = \<const0> ;
assign Dbg_AWADDR_16[9] = \<const0> ;
assign Dbg_AWADDR_16[8] = \<const0> ;
assign Dbg_AWADDR_16[7] = \<const0> ;
assign Dbg_AWADDR_16[6] = \<const0> ;
assign Dbg_AWADDR_16[5] = \<const0> ;
assign Dbg_AWADDR_16[4] = \<const0> ;
assign Dbg_AWADDR_16[3] = \<const0> ;
assign Dbg_AWADDR_16[2] = \<const0> ;
assign Dbg_AWADDR_17[14] = \<const0> ;
assign Dbg_AWADDR_17[13] = \<const0> ;
assign Dbg_AWADDR_17[12] = \<const0> ;
assign Dbg_AWADDR_17[11] = \<const0> ;
assign Dbg_AWADDR_17[10] = \<const0> ;
assign Dbg_AWADDR_17[9] = \<const0> ;
assign Dbg_AWADDR_17[8] = \<const0> ;
assign Dbg_AWADDR_17[7] = \<const0> ;
assign Dbg_AWADDR_17[6] = \<const0> ;
assign Dbg_AWADDR_17[5] = \<const0> ;
assign Dbg_AWADDR_17[4] = \<const0> ;
assign Dbg_AWADDR_17[3] = \<const0> ;
assign Dbg_AWADDR_17[2] = \<const0> ;
assign Dbg_AWADDR_18[14] = \<const0> ;
assign Dbg_AWADDR_18[13] = \<const0> ;
assign Dbg_AWADDR_18[12] = \<const0> ;
assign Dbg_AWADDR_18[11] = \<const0> ;
assign Dbg_AWADDR_18[10] = \<const0> ;
assign Dbg_AWADDR_18[9] = \<const0> ;
assign Dbg_AWADDR_18[8] = \<const0> ;
assign Dbg_AWADDR_18[7] = \<const0> ;
assign Dbg_AWADDR_18[6] = \<const0> ;
assign Dbg_AWADDR_18[5] = \<const0> ;
assign Dbg_AWADDR_18[4] = \<const0> ;
assign Dbg_AWADDR_18[3] = \<const0> ;
assign Dbg_AWADDR_18[2] = \<const0> ;
assign Dbg_AWADDR_19[14] = \<const0> ;
assign Dbg_AWADDR_19[13] = \<const0> ;
assign Dbg_AWADDR_19[12] = \<const0> ;
assign Dbg_AWADDR_19[11] = \<const0> ;
assign Dbg_AWADDR_19[10] = \<const0> ;
assign Dbg_AWADDR_19[9] = \<const0> ;
assign Dbg_AWADDR_19[8] = \<const0> ;
assign Dbg_AWADDR_19[7] = \<const0> ;
assign Dbg_AWADDR_19[6] = \<const0> ;
assign Dbg_AWADDR_19[5] = \<const0> ;
assign Dbg_AWADDR_19[4] = \<const0> ;
assign Dbg_AWADDR_19[3] = \<const0> ;
assign Dbg_AWADDR_19[2] = \<const0> ;
assign Dbg_AWADDR_2[14] = \<const0> ;
assign Dbg_AWADDR_2[13] = \<const0> ;
assign Dbg_AWADDR_2[12] = \<const0> ;
assign Dbg_AWADDR_2[11] = \<const0> ;
assign Dbg_AWADDR_2[10] = \<const0> ;
assign Dbg_AWADDR_2[9] = \<const0> ;
assign Dbg_AWADDR_2[8] = \<const0> ;
assign Dbg_AWADDR_2[7] = \<const0> ;
assign Dbg_AWADDR_2[6] = \<const0> ;
assign Dbg_AWADDR_2[5] = \<const0> ;
assign Dbg_AWADDR_2[4] = \<const0> ;
assign Dbg_AWADDR_2[3] = \<const0> ;
assign Dbg_AWADDR_2[2] = \<const0> ;
assign Dbg_AWADDR_20[14] = \<const0> ;
assign Dbg_AWADDR_20[13] = \<const0> ;
assign Dbg_AWADDR_20[12] = \<const0> ;
assign Dbg_AWADDR_20[11] = \<const0> ;
assign Dbg_AWADDR_20[10] = \<const0> ;
assign Dbg_AWADDR_20[9] = \<const0> ;
assign Dbg_AWADDR_20[8] = \<const0> ;
assign Dbg_AWADDR_20[7] = \<const0> ;
assign Dbg_AWADDR_20[6] = \<const0> ;
assign Dbg_AWADDR_20[5] = \<const0> ;
assign Dbg_AWADDR_20[4] = \<const0> ;
assign Dbg_AWADDR_20[3] = \<const0> ;
assign Dbg_AWADDR_20[2] = \<const0> ;
assign Dbg_AWADDR_21[14] = \<const0> ;
assign Dbg_AWADDR_21[13] = \<const0> ;
assign Dbg_AWADDR_21[12] = \<const0> ;
assign Dbg_AWADDR_21[11] = \<const0> ;
assign Dbg_AWADDR_21[10] = \<const0> ;
assign Dbg_AWADDR_21[9] = \<const0> ;
assign Dbg_AWADDR_21[8] = \<const0> ;
assign Dbg_AWADDR_21[7] = \<const0> ;
assign Dbg_AWADDR_21[6] = \<const0> ;
assign Dbg_AWADDR_21[5] = \<const0> ;
assign Dbg_AWADDR_21[4] = \<const0> ;
assign Dbg_AWADDR_21[3] = \<const0> ;
assign Dbg_AWADDR_21[2] = \<const0> ;
assign Dbg_AWADDR_22[14] = \<const0> ;
assign Dbg_AWADDR_22[13] = \<const0> ;
assign Dbg_AWADDR_22[12] = \<const0> ;
assign Dbg_AWADDR_22[11] = \<const0> ;
assign Dbg_AWADDR_22[10] = \<const0> ;
assign Dbg_AWADDR_22[9] = \<const0> ;
assign Dbg_AWADDR_22[8] = \<const0> ;
assign Dbg_AWADDR_22[7] = \<const0> ;
assign Dbg_AWADDR_22[6] = \<const0> ;
assign Dbg_AWADDR_22[5] = \<const0> ;
assign Dbg_AWADDR_22[4] = \<const0> ;
assign Dbg_AWADDR_22[3] = \<const0> ;
assign Dbg_AWADDR_22[2] = \<const0> ;
assign Dbg_AWADDR_23[14] = \<const0> ;
assign Dbg_AWADDR_23[13] = \<const0> ;
assign Dbg_AWADDR_23[12] = \<const0> ;
assign Dbg_AWADDR_23[11] = \<const0> ;
assign Dbg_AWADDR_23[10] = \<const0> ;
assign Dbg_AWADDR_23[9] = \<const0> ;
assign Dbg_AWADDR_23[8] = \<const0> ;
assign Dbg_AWADDR_23[7] = \<const0> ;
assign Dbg_AWADDR_23[6] = \<const0> ;
assign Dbg_AWADDR_23[5] = \<const0> ;
assign Dbg_AWADDR_23[4] = \<const0> ;
assign Dbg_AWADDR_23[3] = \<const0> ;
assign Dbg_AWADDR_23[2] = \<const0> ;
assign Dbg_AWADDR_24[14] = \<const0> ;
assign Dbg_AWADDR_24[13] = \<const0> ;
assign Dbg_AWADDR_24[12] = \<const0> ;
assign Dbg_AWADDR_24[11] = \<const0> ;
assign Dbg_AWADDR_24[10] = \<const0> ;
assign Dbg_AWADDR_24[9] = \<const0> ;
assign Dbg_AWADDR_24[8] = \<const0> ;
assign Dbg_AWADDR_24[7] = \<const0> ;
assign Dbg_AWADDR_24[6] = \<const0> ;
assign Dbg_AWADDR_24[5] = \<const0> ;
assign Dbg_AWADDR_24[4] = \<const0> ;
assign Dbg_AWADDR_24[3] = \<const0> ;
assign Dbg_AWADDR_24[2] = \<const0> ;
assign Dbg_AWADDR_25[14] = \<const0> ;
assign Dbg_AWADDR_25[13] = \<const0> ;
assign Dbg_AWADDR_25[12] = \<const0> ;
assign Dbg_AWADDR_25[11] = \<const0> ;
assign Dbg_AWADDR_25[10] = \<const0> ;
assign Dbg_AWADDR_25[9] = \<const0> ;
assign Dbg_AWADDR_25[8] = \<const0> ;
assign Dbg_AWADDR_25[7] = \<const0> ;
assign Dbg_AWADDR_25[6] = \<const0> ;
assign Dbg_AWADDR_25[5] = \<const0> ;
assign Dbg_AWADDR_25[4] = \<const0> ;
assign Dbg_AWADDR_25[3] = \<const0> ;
assign Dbg_AWADDR_25[2] = \<const0> ;
assign Dbg_AWADDR_26[14] = \<const0> ;
assign Dbg_AWADDR_26[13] = \<const0> ;
assign Dbg_AWADDR_26[12] = \<const0> ;
assign Dbg_AWADDR_26[11] = \<const0> ;
assign Dbg_AWADDR_26[10] = \<const0> ;
assign Dbg_AWADDR_26[9] = \<const0> ;
assign Dbg_AWADDR_26[8] = \<const0> ;
assign Dbg_AWADDR_26[7] = \<const0> ;
assign Dbg_AWADDR_26[6] = \<const0> ;
assign Dbg_AWADDR_26[5] = \<const0> ;
assign Dbg_AWADDR_26[4] = \<const0> ;
assign Dbg_AWADDR_26[3] = \<const0> ;
assign Dbg_AWADDR_26[2] = \<const0> ;
assign Dbg_AWADDR_27[14] = \<const0> ;
assign Dbg_AWADDR_27[13] = \<const0> ;
assign Dbg_AWADDR_27[12] = \<const0> ;
assign Dbg_AWADDR_27[11] = \<const0> ;
assign Dbg_AWADDR_27[10] = \<const0> ;
assign Dbg_AWADDR_27[9] = \<const0> ;
assign Dbg_AWADDR_27[8] = \<const0> ;
assign Dbg_AWADDR_27[7] = \<const0> ;
assign Dbg_AWADDR_27[6] = \<const0> ;
assign Dbg_AWADDR_27[5] = \<const0> ;
assign Dbg_AWADDR_27[4] = \<const0> ;
assign Dbg_AWADDR_27[3] = \<const0> ;
assign Dbg_AWADDR_27[2] = \<const0> ;
assign Dbg_AWADDR_28[14] = \<const0> ;
assign Dbg_AWADDR_28[13] = \<const0> ;
assign Dbg_AWADDR_28[12] = \<const0> ;
assign Dbg_AWADDR_28[11] = \<const0> ;
assign Dbg_AWADDR_28[10] = \<const0> ;
assign Dbg_AWADDR_28[9] = \<const0> ;
assign Dbg_AWADDR_28[8] = \<const0> ;
assign Dbg_AWADDR_28[7] = \<const0> ;
assign Dbg_AWADDR_28[6] = \<const0> ;
assign Dbg_AWADDR_28[5] = \<const0> ;
assign Dbg_AWADDR_28[4] = \<const0> ;
assign Dbg_AWADDR_28[3] = \<const0> ;
assign Dbg_AWADDR_28[2] = \<const0> ;
assign Dbg_AWADDR_29[14] = \<const0> ;
assign Dbg_AWADDR_29[13] = \<const0> ;
assign Dbg_AWADDR_29[12] = \<const0> ;
assign Dbg_AWADDR_29[11] = \<const0> ;
assign Dbg_AWADDR_29[10] = \<const0> ;
assign Dbg_AWADDR_29[9] = \<const0> ;
assign Dbg_AWADDR_29[8] = \<const0> ;
assign Dbg_AWADDR_29[7] = \<const0> ;
assign Dbg_AWADDR_29[6] = \<const0> ;
assign Dbg_AWADDR_29[5] = \<const0> ;
assign Dbg_AWADDR_29[4] = \<const0> ;
assign Dbg_AWADDR_29[3] = \<const0> ;
assign Dbg_AWADDR_29[2] = \<const0> ;
assign Dbg_AWADDR_3[14] = \<const0> ;
assign Dbg_AWADDR_3[13] = \<const0> ;
assign Dbg_AWADDR_3[12] = \<const0> ;
assign Dbg_AWADDR_3[11] = \<const0> ;
assign Dbg_AWADDR_3[10] = \<const0> ;
assign Dbg_AWADDR_3[9] = \<const0> ;
assign Dbg_AWADDR_3[8] = \<const0> ;
assign Dbg_AWADDR_3[7] = \<const0> ;
assign Dbg_AWADDR_3[6] = \<const0> ;
assign Dbg_AWADDR_3[5] = \<const0> ;
assign Dbg_AWADDR_3[4] = \<const0> ;
assign Dbg_AWADDR_3[3] = \<const0> ;
assign Dbg_AWADDR_3[2] = \<const0> ;
assign Dbg_AWADDR_30[14] = \<const0> ;
assign Dbg_AWADDR_30[13] = \<const0> ;
assign Dbg_AWADDR_30[12] = \<const0> ;
assign Dbg_AWADDR_30[11] = \<const0> ;
assign Dbg_AWADDR_30[10] = \<const0> ;
assign Dbg_AWADDR_30[9] = \<const0> ;
assign Dbg_AWADDR_30[8] = \<const0> ;
assign Dbg_AWADDR_30[7] = \<const0> ;
assign Dbg_AWADDR_30[6] = \<const0> ;
assign Dbg_AWADDR_30[5] = \<const0> ;
assign Dbg_AWADDR_30[4] = \<const0> ;
assign Dbg_AWADDR_30[3] = \<const0> ;
assign Dbg_AWADDR_30[2] = \<const0> ;
assign Dbg_AWADDR_31[14] = \<const0> ;
assign Dbg_AWADDR_31[13] = \<const0> ;
assign Dbg_AWADDR_31[12] = \<const0> ;
assign Dbg_AWADDR_31[11] = \<const0> ;
assign Dbg_AWADDR_31[10] = \<const0> ;
assign Dbg_AWADDR_31[9] = \<const0> ;
assign Dbg_AWADDR_31[8] = \<const0> ;
assign Dbg_AWADDR_31[7] = \<const0> ;
assign Dbg_AWADDR_31[6] = \<const0> ;
assign Dbg_AWADDR_31[5] = \<const0> ;
assign Dbg_AWADDR_31[4] = \<const0> ;
assign Dbg_AWADDR_31[3] = \<const0> ;
assign Dbg_AWADDR_31[2] = \<const0> ;
assign Dbg_AWADDR_4[14] = \<const0> ;
assign Dbg_AWADDR_4[13] = \<const0> ;
assign Dbg_AWADDR_4[12] = \<const0> ;
assign Dbg_AWADDR_4[11] = \<const0> ;
assign Dbg_AWADDR_4[10] = \<const0> ;
assign Dbg_AWADDR_4[9] = \<const0> ;
assign Dbg_AWADDR_4[8] = \<const0> ;
assign Dbg_AWADDR_4[7] = \<const0> ;
assign Dbg_AWADDR_4[6] = \<const0> ;
assign Dbg_AWADDR_4[5] = \<const0> ;
assign Dbg_AWADDR_4[4] = \<const0> ;
assign Dbg_AWADDR_4[3] = \<const0> ;
assign Dbg_AWADDR_4[2] = \<const0> ;
assign Dbg_AWADDR_5[14] = \<const0> ;
assign Dbg_AWADDR_5[13] = \<const0> ;
assign Dbg_AWADDR_5[12] = \<const0> ;
assign Dbg_AWADDR_5[11] = \<const0> ;
assign Dbg_AWADDR_5[10] = \<const0> ;
assign Dbg_AWADDR_5[9] = \<const0> ;
assign Dbg_AWADDR_5[8] = \<const0> ;
assign Dbg_AWADDR_5[7] = \<const0> ;
assign Dbg_AWADDR_5[6] = \<const0> ;
assign Dbg_AWADDR_5[5] = \<const0> ;
assign Dbg_AWADDR_5[4] = \<const0> ;
assign Dbg_AWADDR_5[3] = \<const0> ;
assign Dbg_AWADDR_5[2] = \<const0> ;
assign Dbg_AWADDR_6[14] = \<const0> ;
assign Dbg_AWADDR_6[13] = \<const0> ;
assign Dbg_AWADDR_6[12] = \<const0> ;
assign Dbg_AWADDR_6[11] = \<const0> ;
assign Dbg_AWADDR_6[10] = \<const0> ;
assign Dbg_AWADDR_6[9] = \<const0> ;
assign Dbg_AWADDR_6[8] = \<const0> ;
assign Dbg_AWADDR_6[7] = \<const0> ;
assign Dbg_AWADDR_6[6] = \<const0> ;
assign Dbg_AWADDR_6[5] = \<const0> ;
assign Dbg_AWADDR_6[4] = \<const0> ;
assign Dbg_AWADDR_6[3] = \<const0> ;
assign Dbg_AWADDR_6[2] = \<const0> ;
assign Dbg_AWADDR_7[14] = \<const0> ;
assign Dbg_AWADDR_7[13] = \<const0> ;
assign Dbg_AWADDR_7[12] = \<const0> ;
assign Dbg_AWADDR_7[11] = \<const0> ;
assign Dbg_AWADDR_7[10] = \<const0> ;
assign Dbg_AWADDR_7[9] = \<const0> ;
assign Dbg_AWADDR_7[8] = \<const0> ;
assign Dbg_AWADDR_7[7] = \<const0> ;
assign Dbg_AWADDR_7[6] = \<const0> ;
assign Dbg_AWADDR_7[5] = \<const0> ;
assign Dbg_AWADDR_7[4] = \<const0> ;
assign Dbg_AWADDR_7[3] = \<const0> ;
assign Dbg_AWADDR_7[2] = \<const0> ;
assign Dbg_AWADDR_8[14] = \<const0> ;
assign Dbg_AWADDR_8[13] = \<const0> ;
assign Dbg_AWADDR_8[12] = \<const0> ;
assign Dbg_AWADDR_8[11] = \<const0> ;
assign Dbg_AWADDR_8[10] = \<const0> ;
assign Dbg_AWADDR_8[9] = \<const0> ;
assign Dbg_AWADDR_8[8] = \<const0> ;
assign Dbg_AWADDR_8[7] = \<const0> ;
assign Dbg_AWADDR_8[6] = \<const0> ;
assign Dbg_AWADDR_8[5] = \<const0> ;
assign Dbg_AWADDR_8[4] = \<const0> ;
assign Dbg_AWADDR_8[3] = \<const0> ;
assign Dbg_AWADDR_8[2] = \<const0> ;
assign Dbg_AWADDR_9[14] = \<const0> ;
assign Dbg_AWADDR_9[13] = \<const0> ;
assign Dbg_AWADDR_9[12] = \<const0> ;
assign Dbg_AWADDR_9[11] = \<const0> ;
assign Dbg_AWADDR_9[10] = \<const0> ;
assign Dbg_AWADDR_9[9] = \<const0> ;
assign Dbg_AWADDR_9[8] = \<const0> ;
assign Dbg_AWADDR_9[7] = \<const0> ;
assign Dbg_AWADDR_9[6] = \<const0> ;
assign Dbg_AWADDR_9[5] = \<const0> ;
assign Dbg_AWADDR_9[4] = \<const0> ;
assign Dbg_AWADDR_9[3] = \<const0> ;
assign Dbg_AWADDR_9[2] = \<const0> ;
assign Dbg_AWVALID_0 = \<const0> ;
assign Dbg_AWVALID_1 = \<const0> ;
assign Dbg_AWVALID_10 = \<const0> ;
assign Dbg_AWVALID_11 = \<const0> ;
assign Dbg_AWVALID_12 = \<const0> ;
assign Dbg_AWVALID_13 = \<const0> ;
assign Dbg_AWVALID_14 = \<const0> ;
assign Dbg_AWVALID_15 = \<const0> ;
assign Dbg_AWVALID_16 = \<const0> ;
assign Dbg_AWVALID_17 = \<const0> ;
assign Dbg_AWVALID_18 = \<const0> ;
assign Dbg_AWVALID_19 = \<const0> ;
assign Dbg_AWVALID_2 = \<const0> ;
assign Dbg_AWVALID_20 = \<const0> ;
assign Dbg_AWVALID_21 = \<const0> ;
assign Dbg_AWVALID_22 = \<const0> ;
assign Dbg_AWVALID_23 = \<const0> ;
assign Dbg_AWVALID_24 = \<const0> ;
assign Dbg_AWVALID_25 = \<const0> ;
assign Dbg_AWVALID_26 = \<const0> ;
assign Dbg_AWVALID_27 = \<const0> ;
assign Dbg_AWVALID_28 = \<const0> ;
assign Dbg_AWVALID_29 = \<const0> ;
assign Dbg_AWVALID_3 = \<const0> ;
assign Dbg_AWVALID_30 = \<const0> ;
assign Dbg_AWVALID_31 = \<const0> ;
assign Dbg_AWVALID_4 = \<const0> ;
assign Dbg_AWVALID_5 = \<const0> ;
assign Dbg_AWVALID_6 = \<const0> ;
assign Dbg_AWVALID_7 = \<const0> ;
assign Dbg_AWVALID_8 = \<const0> ;
assign Dbg_AWVALID_9 = \<const0> ;
assign Dbg_BREADY_0 = \<const0> ;
assign Dbg_BREADY_1 = \<const0> ;
assign Dbg_BREADY_10 = \<const0> ;
assign Dbg_BREADY_11 = \<const0> ;
assign Dbg_BREADY_12 = \<const0> ;
assign Dbg_BREADY_13 = \<const0> ;
assign Dbg_BREADY_14 = \<const0> ;
assign Dbg_BREADY_15 = \<const0> ;
assign Dbg_BREADY_16 = \<const0> ;
assign Dbg_BREADY_17 = \<const0> ;
assign Dbg_BREADY_18 = \<const0> ;
assign Dbg_BREADY_19 = \<const0> ;
assign Dbg_BREADY_2 = \<const0> ;
assign Dbg_BREADY_20 = \<const0> ;
assign Dbg_BREADY_21 = \<const0> ;
assign Dbg_BREADY_22 = \<const0> ;
assign Dbg_BREADY_23 = \<const0> ;
assign Dbg_BREADY_24 = \<const0> ;
assign Dbg_BREADY_25 = \<const0> ;
assign Dbg_BREADY_26 = \<const0> ;
assign Dbg_BREADY_27 = \<const0> ;
assign Dbg_BREADY_28 = \<const0> ;
assign Dbg_BREADY_29 = \<const0> ;
assign Dbg_BREADY_3 = \<const0> ;
assign Dbg_BREADY_30 = \<const0> ;
assign Dbg_BREADY_31 = \<const0> ;
assign Dbg_BREADY_4 = \<const0> ;
assign Dbg_BREADY_5 = \<const0> ;
assign Dbg_BREADY_6 = \<const0> ;
assign Dbg_BREADY_7 = \<const0> ;
assign Dbg_BREADY_8 = \<const0> ;
assign Dbg_BREADY_9 = \<const0> ;
assign Dbg_Capture_0 = Ext_JTAG_CAPTURE;
assign Dbg_Capture_1 = Ext_JTAG_CAPTURE;
assign Dbg_Capture_10 = Ext_JTAG_CAPTURE;
assign Dbg_Capture_11 = Ext_JTAG_CAPTURE;
assign Dbg_Capture_12 = Ext_JTAG_CAPTURE;
assign Dbg_Capture_13 = Ext_JTAG_CAPTURE;
assign Dbg_Capture_14 = Ext_JTAG_CAPTURE;
assign Dbg_Capture_15 = Ext_JTAG_CAPTURE;
assign Dbg_Capture_16 = Ext_JTAG_CAPTURE;
assign Dbg_Capture_17 = Ext_JTAG_CAPTURE;
assign Dbg_Capture_18 = Ext_JTAG_CAPTURE;
assign Dbg_Capture_19 = Ext_JTAG_CAPTURE;
assign Dbg_Capture_2 = Ext_JTAG_CAPTURE;
assign Dbg_Capture_20 = Ext_JTAG_CAPTURE;
assign Dbg_Capture_21 = Ext_JTAG_CAPTURE;
assign Dbg_Capture_22 = Ext_JTAG_CAPTURE;
assign Dbg_Capture_23 = Ext_JTAG_CAPTURE;
assign Dbg_Capture_24 = Ext_JTAG_CAPTURE;
assign Dbg_Capture_25 = Ext_JTAG_CAPTURE;
assign Dbg_Capture_26 = Ext_JTAG_CAPTURE;
assign Dbg_Capture_27 = Ext_JTAG_CAPTURE;
assign Dbg_Capture_28 = Ext_JTAG_CAPTURE;
assign Dbg_Capture_29 = Ext_JTAG_CAPTURE;
assign Dbg_Capture_3 = Ext_JTAG_CAPTURE;
assign Dbg_Capture_30 = Ext_JTAG_CAPTURE;
assign Dbg_Capture_31 = Ext_JTAG_CAPTURE;
assign Dbg_Capture_4 = Ext_JTAG_CAPTURE;
assign Dbg_Capture_5 = Ext_JTAG_CAPTURE;
assign Dbg_Capture_6 = Ext_JTAG_CAPTURE;
assign Dbg_Capture_7 = Ext_JTAG_CAPTURE;
assign Dbg_Capture_8 = Ext_JTAG_CAPTURE;
assign Dbg_Capture_9 = Ext_JTAG_CAPTURE;
assign Dbg_Clk_0 = Dbg_Clk_31;
assign Dbg_Clk_1 = Dbg_Clk_31;
assign Dbg_Clk_10 = Dbg_Clk_31;
assign Dbg_Clk_11 = Dbg_Clk_31;
assign Dbg_Clk_12 = Dbg_Clk_31;
assign Dbg_Clk_13 = Dbg_Clk_31;
assign Dbg_Clk_14 = Dbg_Clk_31;
assign Dbg_Clk_15 = Dbg_Clk_31;
assign Dbg_Clk_16 = Dbg_Clk_31;
assign Dbg_Clk_17 = Dbg_Clk_31;
assign Dbg_Clk_18 = Dbg_Clk_31;
assign Dbg_Clk_19 = Dbg_Clk_31;
assign Dbg_Clk_2 = Dbg_Clk_31;
assign Dbg_Clk_20 = Dbg_Clk_31;
assign Dbg_Clk_21 = Dbg_Clk_31;
assign Dbg_Clk_22 = Dbg_Clk_31;
assign Dbg_Clk_23 = Dbg_Clk_31;
assign Dbg_Clk_24 = Dbg_Clk_31;
assign Dbg_Clk_25 = Dbg_Clk_31;
assign Dbg_Clk_26 = Dbg_Clk_31;
assign Dbg_Clk_27 = Dbg_Clk_31;
assign Dbg_Clk_28 = Dbg_Clk_31;
assign Dbg_Clk_29 = Dbg_Clk_31;
assign Dbg_Clk_3 = Dbg_Clk_31;
assign Dbg_Clk_30 = Dbg_Clk_31;
assign Dbg_Clk_4 = Dbg_Clk_31;
assign Dbg_Clk_5 = Dbg_Clk_31;
assign Dbg_Clk_6 = Dbg_Clk_31;
assign Dbg_Clk_7 = Dbg_Clk_31;
assign Dbg_Clk_8 = Dbg_Clk_31;
assign Dbg_Clk_9 = Dbg_Clk_31;
assign Dbg_Disable_1 = \<const1> ;
assign Dbg_Disable_10 = \<const1> ;
assign Dbg_Disable_11 = \<const1> ;
assign Dbg_Disable_12 = \<const1> ;
assign Dbg_Disable_13 = \<const1> ;
assign Dbg_Disable_14 = \<const1> ;
assign Dbg_Disable_15 = \<const1> ;
assign Dbg_Disable_16 = \<const1> ;
assign Dbg_Disable_17 = \<const1> ;
assign Dbg_Disable_18 = \<const1> ;
assign Dbg_Disable_19 = \<const1> ;
assign Dbg_Disable_2 = \<const1> ;
assign Dbg_Disable_20 = \<const1> ;
assign Dbg_Disable_21 = \<const1> ;
assign Dbg_Disable_22 = \<const1> ;
assign Dbg_Disable_23 = \<const1> ;
assign Dbg_Disable_24 = \<const1> ;
assign Dbg_Disable_25 = \<const1> ;
assign Dbg_Disable_26 = \<const1> ;
assign Dbg_Disable_27 = \<const1> ;
assign Dbg_Disable_28 = \<const1> ;
assign Dbg_Disable_29 = \<const1> ;
assign Dbg_Disable_3 = \<const1> ;
assign Dbg_Disable_30 = \<const1> ;
assign Dbg_Disable_31 = \<const1> ;
assign Dbg_Disable_4 = \<const1> ;
assign Dbg_Disable_5 = \<const1> ;
assign Dbg_Disable_6 = \<const1> ;
assign Dbg_Disable_7 = \<const1> ;
assign Dbg_Disable_8 = \<const1> ;
assign Dbg_Disable_9 = \<const1> ;
assign Dbg_RREADY_0 = \<const0> ;
assign Dbg_RREADY_1 = \<const0> ;
assign Dbg_RREADY_10 = \<const0> ;
assign Dbg_RREADY_11 = \<const0> ;
assign Dbg_RREADY_12 = \<const0> ;
assign Dbg_RREADY_13 = \<const0> ;
assign Dbg_RREADY_14 = \<const0> ;
assign Dbg_RREADY_15 = \<const0> ;
assign Dbg_RREADY_16 = \<const0> ;
assign Dbg_RREADY_17 = \<const0> ;
assign Dbg_RREADY_18 = \<const0> ;
assign Dbg_RREADY_19 = \<const0> ;
assign Dbg_RREADY_2 = \<const0> ;
assign Dbg_RREADY_20 = \<const0> ;
assign Dbg_RREADY_21 = \<const0> ;
assign Dbg_RREADY_22 = \<const0> ;
assign Dbg_RREADY_23 = \<const0> ;
assign Dbg_RREADY_24 = \<const0> ;
assign Dbg_RREADY_25 = \<const0> ;
assign Dbg_RREADY_26 = \<const0> ;
assign Dbg_RREADY_27 = \<const0> ;
assign Dbg_RREADY_28 = \<const0> ;
assign Dbg_RREADY_29 = \<const0> ;
assign Dbg_RREADY_3 = \<const0> ;
assign Dbg_RREADY_30 = \<const0> ;
assign Dbg_RREADY_31 = \<const0> ;
assign Dbg_RREADY_4 = \<const0> ;
assign Dbg_RREADY_5 = \<const0> ;
assign Dbg_RREADY_6 = \<const0> ;
assign Dbg_RREADY_7 = \<const0> ;
assign Dbg_RREADY_8 = \<const0> ;
assign Dbg_RREADY_9 = \<const0> ;
assign Dbg_Reg_En_1[0] = \<const0> ;
assign Dbg_Reg_En_1[1] = \<const0> ;
assign Dbg_Reg_En_1[2] = \<const0> ;
assign Dbg_Reg_En_1[3] = \<const0> ;
assign Dbg_Reg_En_1[4] = \<const0> ;
assign Dbg_Reg_En_1[5] = \<const0> ;
assign Dbg_Reg_En_1[6] = \<const0> ;
assign Dbg_Reg_En_1[7] = \<const0> ;
assign Dbg_Reg_En_10[0] = \<const0> ;
assign Dbg_Reg_En_10[1] = \<const0> ;
assign Dbg_Reg_En_10[2] = \<const0> ;
assign Dbg_Reg_En_10[3] = \<const0> ;
assign Dbg_Reg_En_10[4] = \<const0> ;
assign Dbg_Reg_En_10[5] = \<const0> ;
assign Dbg_Reg_En_10[6] = \<const0> ;
assign Dbg_Reg_En_10[7] = \<const0> ;
assign Dbg_Reg_En_11[0] = \<const0> ;
assign Dbg_Reg_En_11[1] = \<const0> ;
assign Dbg_Reg_En_11[2] = \<const0> ;
assign Dbg_Reg_En_11[3] = \<const0> ;
assign Dbg_Reg_En_11[4] = \<const0> ;
assign Dbg_Reg_En_11[5] = \<const0> ;
assign Dbg_Reg_En_11[6] = \<const0> ;
assign Dbg_Reg_En_11[7] = \<const0> ;
assign Dbg_Reg_En_12[0] = \<const0> ;
assign Dbg_Reg_En_12[1] = \<const0> ;
assign Dbg_Reg_En_12[2] = \<const0> ;
assign Dbg_Reg_En_12[3] = \<const0> ;
assign Dbg_Reg_En_12[4] = \<const0> ;
assign Dbg_Reg_En_12[5] = \<const0> ;
assign Dbg_Reg_En_12[6] = \<const0> ;
assign Dbg_Reg_En_12[7] = \<const0> ;
assign Dbg_Reg_En_13[0] = \<const0> ;
assign Dbg_Reg_En_13[1] = \<const0> ;
assign Dbg_Reg_En_13[2] = \<const0> ;
assign Dbg_Reg_En_13[3] = \<const0> ;
assign Dbg_Reg_En_13[4] = \<const0> ;
assign Dbg_Reg_En_13[5] = \<const0> ;
assign Dbg_Reg_En_13[6] = \<const0> ;
assign Dbg_Reg_En_13[7] = \<const0> ;
assign Dbg_Reg_En_14[0] = \<const0> ;
assign Dbg_Reg_En_14[1] = \<const0> ;
assign Dbg_Reg_En_14[2] = \<const0> ;
assign Dbg_Reg_En_14[3] = \<const0> ;
assign Dbg_Reg_En_14[4] = \<const0> ;
assign Dbg_Reg_En_14[5] = \<const0> ;
assign Dbg_Reg_En_14[6] = \<const0> ;
assign Dbg_Reg_En_14[7] = \<const0> ;
assign Dbg_Reg_En_15[0] = \<const0> ;
assign Dbg_Reg_En_15[1] = \<const0> ;
assign Dbg_Reg_En_15[2] = \<const0> ;
assign Dbg_Reg_En_15[3] = \<const0> ;
assign Dbg_Reg_En_15[4] = \<const0> ;
assign Dbg_Reg_En_15[5] = \<const0> ;
assign Dbg_Reg_En_15[6] = \<const0> ;
assign Dbg_Reg_En_15[7] = \<const0> ;
assign Dbg_Reg_En_16[0] = \<const0> ;
assign Dbg_Reg_En_16[1] = \<const0> ;
assign Dbg_Reg_En_16[2] = \<const0> ;
assign Dbg_Reg_En_16[3] = \<const0> ;
assign Dbg_Reg_En_16[4] = \<const0> ;
assign Dbg_Reg_En_16[5] = \<const0> ;
assign Dbg_Reg_En_16[6] = \<const0> ;
assign Dbg_Reg_En_16[7] = \<const0> ;
assign Dbg_Reg_En_17[0] = \<const0> ;
assign Dbg_Reg_En_17[1] = \<const0> ;
assign Dbg_Reg_En_17[2] = \<const0> ;
assign Dbg_Reg_En_17[3] = \<const0> ;
assign Dbg_Reg_En_17[4] = \<const0> ;
assign Dbg_Reg_En_17[5] = \<const0> ;
assign Dbg_Reg_En_17[6] = \<const0> ;
assign Dbg_Reg_En_17[7] = \<const0> ;
assign Dbg_Reg_En_18[0] = \<const0> ;
assign Dbg_Reg_En_18[1] = \<const0> ;
assign Dbg_Reg_En_18[2] = \<const0> ;
assign Dbg_Reg_En_18[3] = \<const0> ;
assign Dbg_Reg_En_18[4] = \<const0> ;
assign Dbg_Reg_En_18[5] = \<const0> ;
assign Dbg_Reg_En_18[6] = \<const0> ;
assign Dbg_Reg_En_18[7] = \<const0> ;
assign Dbg_Reg_En_19[0] = \<const0> ;
assign Dbg_Reg_En_19[1] = \<const0> ;
assign Dbg_Reg_En_19[2] = \<const0> ;
assign Dbg_Reg_En_19[3] = \<const0> ;
assign Dbg_Reg_En_19[4] = \<const0> ;
assign Dbg_Reg_En_19[5] = \<const0> ;
assign Dbg_Reg_En_19[6] = \<const0> ;
assign Dbg_Reg_En_19[7] = \<const0> ;
assign Dbg_Reg_En_2[0] = \<const0> ;
assign Dbg_Reg_En_2[1] = \<const0> ;
assign Dbg_Reg_En_2[2] = \<const0> ;
assign Dbg_Reg_En_2[3] = \<const0> ;
assign Dbg_Reg_En_2[4] = \<const0> ;
assign Dbg_Reg_En_2[5] = \<const0> ;
assign Dbg_Reg_En_2[6] = \<const0> ;
assign Dbg_Reg_En_2[7] = \<const0> ;
assign Dbg_Reg_En_20[0] = \<const0> ;
assign Dbg_Reg_En_20[1] = \<const0> ;
assign Dbg_Reg_En_20[2] = \<const0> ;
assign Dbg_Reg_En_20[3] = \<const0> ;
assign Dbg_Reg_En_20[4] = \<const0> ;
assign Dbg_Reg_En_20[5] = \<const0> ;
assign Dbg_Reg_En_20[6] = \<const0> ;
assign Dbg_Reg_En_20[7] = \<const0> ;
assign Dbg_Reg_En_21[0] = \<const0> ;
assign Dbg_Reg_En_21[1] = \<const0> ;
assign Dbg_Reg_En_21[2] = \<const0> ;
assign Dbg_Reg_En_21[3] = \<const0> ;
assign Dbg_Reg_En_21[4] = \<const0> ;
assign Dbg_Reg_En_21[5] = \<const0> ;
assign Dbg_Reg_En_21[6] = \<const0> ;
assign Dbg_Reg_En_21[7] = \<const0> ;
assign Dbg_Reg_En_22[0] = \<const0> ;
assign Dbg_Reg_En_22[1] = \<const0> ;
assign Dbg_Reg_En_22[2] = \<const0> ;
assign Dbg_Reg_En_22[3] = \<const0> ;
assign Dbg_Reg_En_22[4] = \<const0> ;
assign Dbg_Reg_En_22[5] = \<const0> ;
assign Dbg_Reg_En_22[6] = \<const0> ;
assign Dbg_Reg_En_22[7] = \<const0> ;
assign Dbg_Reg_En_23[0] = \<const0> ;
assign Dbg_Reg_En_23[1] = \<const0> ;
assign Dbg_Reg_En_23[2] = \<const0> ;
assign Dbg_Reg_En_23[3] = \<const0> ;
assign Dbg_Reg_En_23[4] = \<const0> ;
assign Dbg_Reg_En_23[5] = \<const0> ;
assign Dbg_Reg_En_23[6] = \<const0> ;
assign Dbg_Reg_En_23[7] = \<const0> ;
assign Dbg_Reg_En_24[0] = \<const0> ;
assign Dbg_Reg_En_24[1] = \<const0> ;
assign Dbg_Reg_En_24[2] = \<const0> ;
assign Dbg_Reg_En_24[3] = \<const0> ;
assign Dbg_Reg_En_24[4] = \<const0> ;
assign Dbg_Reg_En_24[5] = \<const0> ;
assign Dbg_Reg_En_24[6] = \<const0> ;
assign Dbg_Reg_En_24[7] = \<const0> ;
assign Dbg_Reg_En_25[0] = \<const0> ;
assign Dbg_Reg_En_25[1] = \<const0> ;
assign Dbg_Reg_En_25[2] = \<const0> ;
assign Dbg_Reg_En_25[3] = \<const0> ;
assign Dbg_Reg_En_25[4] = \<const0> ;
assign Dbg_Reg_En_25[5] = \<const0> ;
assign Dbg_Reg_En_25[6] = \<const0> ;
assign Dbg_Reg_En_25[7] = \<const0> ;
assign Dbg_Reg_En_26[0] = \<const0> ;
assign Dbg_Reg_En_26[1] = \<const0> ;
assign Dbg_Reg_En_26[2] = \<const0> ;
assign Dbg_Reg_En_26[3] = \<const0> ;
assign Dbg_Reg_En_26[4] = \<const0> ;
assign Dbg_Reg_En_26[5] = \<const0> ;
assign Dbg_Reg_En_26[6] = \<const0> ;
assign Dbg_Reg_En_26[7] = \<const0> ;
assign Dbg_Reg_En_27[0] = \<const0> ;
assign Dbg_Reg_En_27[1] = \<const0> ;
assign Dbg_Reg_En_27[2] = \<const0> ;
assign Dbg_Reg_En_27[3] = \<const0> ;
assign Dbg_Reg_En_27[4] = \<const0> ;
assign Dbg_Reg_En_27[5] = \<const0> ;
assign Dbg_Reg_En_27[6] = \<const0> ;
assign Dbg_Reg_En_27[7] = \<const0> ;
assign Dbg_Reg_En_28[0] = \<const0> ;
assign Dbg_Reg_En_28[1] = \<const0> ;
assign Dbg_Reg_En_28[2] = \<const0> ;
assign Dbg_Reg_En_28[3] = \<const0> ;
assign Dbg_Reg_En_28[4] = \<const0> ;
assign Dbg_Reg_En_28[5] = \<const0> ;
assign Dbg_Reg_En_28[6] = \<const0> ;
assign Dbg_Reg_En_28[7] = \<const0> ;
assign Dbg_Reg_En_29[0] = \<const0> ;
assign Dbg_Reg_En_29[1] = \<const0> ;
assign Dbg_Reg_En_29[2] = \<const0> ;
assign Dbg_Reg_En_29[3] = \<const0> ;
assign Dbg_Reg_En_29[4] = \<const0> ;
assign Dbg_Reg_En_29[5] = \<const0> ;
assign Dbg_Reg_En_29[6] = \<const0> ;
assign Dbg_Reg_En_29[7] = \<const0> ;
assign Dbg_Reg_En_3[0] = \<const0> ;
assign Dbg_Reg_En_3[1] = \<const0> ;
assign Dbg_Reg_En_3[2] = \<const0> ;
assign Dbg_Reg_En_3[3] = \<const0> ;
assign Dbg_Reg_En_3[4] = \<const0> ;
assign Dbg_Reg_En_3[5] = \<const0> ;
assign Dbg_Reg_En_3[6] = \<const0> ;
assign Dbg_Reg_En_3[7] = \<const0> ;
assign Dbg_Reg_En_30[0] = \<const0> ;
assign Dbg_Reg_En_30[1] = \<const0> ;
assign Dbg_Reg_En_30[2] = \<const0> ;
assign Dbg_Reg_En_30[3] = \<const0> ;
assign Dbg_Reg_En_30[4] = \<const0> ;
assign Dbg_Reg_En_30[5] = \<const0> ;
assign Dbg_Reg_En_30[6] = \<const0> ;
assign Dbg_Reg_En_30[7] = \<const0> ;
assign Dbg_Reg_En_31[0] = \<const0> ;
assign Dbg_Reg_En_31[1] = \<const0> ;
assign Dbg_Reg_En_31[2] = \<const0> ;
assign Dbg_Reg_En_31[3] = \<const0> ;
assign Dbg_Reg_En_31[4] = \<const0> ;
assign Dbg_Reg_En_31[5] = \<const0> ;
assign Dbg_Reg_En_31[6] = \<const0> ;
assign Dbg_Reg_En_31[7] = \<const0> ;
assign Dbg_Reg_En_4[0] = \<const0> ;
assign Dbg_Reg_En_4[1] = \<const0> ;
assign Dbg_Reg_En_4[2] = \<const0> ;
assign Dbg_Reg_En_4[3] = \<const0> ;
assign Dbg_Reg_En_4[4] = \<const0> ;
assign Dbg_Reg_En_4[5] = \<const0> ;
assign Dbg_Reg_En_4[6] = \<const0> ;
assign Dbg_Reg_En_4[7] = \<const0> ;
assign Dbg_Reg_En_5[0] = \<const0> ;
assign Dbg_Reg_En_5[1] = \<const0> ;
assign Dbg_Reg_En_5[2] = \<const0> ;
assign Dbg_Reg_En_5[3] = \<const0> ;
assign Dbg_Reg_En_5[4] = \<const0> ;
assign Dbg_Reg_En_5[5] = \<const0> ;
assign Dbg_Reg_En_5[6] = \<const0> ;
assign Dbg_Reg_En_5[7] = \<const0> ;
assign Dbg_Reg_En_6[0] = \<const0> ;
assign Dbg_Reg_En_6[1] = \<const0> ;
assign Dbg_Reg_En_6[2] = \<const0> ;
assign Dbg_Reg_En_6[3] = \<const0> ;
assign Dbg_Reg_En_6[4] = \<const0> ;
assign Dbg_Reg_En_6[5] = \<const0> ;
assign Dbg_Reg_En_6[6] = \<const0> ;
assign Dbg_Reg_En_6[7] = \<const0> ;
assign Dbg_Reg_En_7[0] = \<const0> ;
assign Dbg_Reg_En_7[1] = \<const0> ;
assign Dbg_Reg_En_7[2] = \<const0> ;
assign Dbg_Reg_En_7[3] = \<const0> ;
assign Dbg_Reg_En_7[4] = \<const0> ;
assign Dbg_Reg_En_7[5] = \<const0> ;
assign Dbg_Reg_En_7[6] = \<const0> ;
assign Dbg_Reg_En_7[7] = \<const0> ;
assign Dbg_Reg_En_8[0] = \<const0> ;
assign Dbg_Reg_En_8[1] = \<const0> ;
assign Dbg_Reg_En_8[2] = \<const0> ;
assign Dbg_Reg_En_8[3] = \<const0> ;
assign Dbg_Reg_En_8[4] = \<const0> ;
assign Dbg_Reg_En_8[5] = \<const0> ;
assign Dbg_Reg_En_8[6] = \<const0> ;
assign Dbg_Reg_En_8[7] = \<const0> ;
assign Dbg_Reg_En_9[0] = \<const0> ;
assign Dbg_Reg_En_9[1] = \<const0> ;
assign Dbg_Reg_En_9[2] = \<const0> ;
assign Dbg_Reg_En_9[3] = \<const0> ;
assign Dbg_Reg_En_9[4] = \<const0> ;
assign Dbg_Reg_En_9[5] = \<const0> ;
assign Dbg_Reg_En_9[6] = \<const0> ;
assign Dbg_Reg_En_9[7] = \<const0> ;
assign Dbg_Rst_1 = \<const0> ;
assign Dbg_Rst_10 = \<const0> ;
assign Dbg_Rst_11 = \<const0> ;
assign Dbg_Rst_12 = \<const0> ;
assign Dbg_Rst_13 = \<const0> ;
assign Dbg_Rst_14 = \<const0> ;
assign Dbg_Rst_15 = \<const0> ;
assign Dbg_Rst_16 = \<const0> ;
assign Dbg_Rst_17 = \<const0> ;
assign Dbg_Rst_18 = \<const0> ;
assign Dbg_Rst_19 = \<const0> ;
assign Dbg_Rst_2 = \<const0> ;
assign Dbg_Rst_20 = \<const0> ;
assign Dbg_Rst_21 = \<const0> ;
assign Dbg_Rst_22 = \<const0> ;
assign Dbg_Rst_23 = \<const0> ;
assign Dbg_Rst_24 = \<const0> ;
assign Dbg_Rst_25 = \<const0> ;
assign Dbg_Rst_26 = \<const0> ;
assign Dbg_Rst_27 = \<const0> ;
assign Dbg_Rst_28 = \<const0> ;
assign Dbg_Rst_29 = \<const0> ;
assign Dbg_Rst_3 = \<const0> ;
assign Dbg_Rst_30 = \<const0> ;
assign Dbg_Rst_31 = \<const0> ;
assign Dbg_Rst_4 = \<const0> ;
assign Dbg_Rst_5 = \<const0> ;
assign Dbg_Rst_6 = \<const0> ;
assign Dbg_Rst_7 = \<const0> ;
assign Dbg_Rst_8 = \<const0> ;
assign Dbg_Rst_9 = \<const0> ;
assign Dbg_Shift_1 = Dbg_Shift_0;
assign Dbg_Shift_10 = Dbg_Shift_0;
assign Dbg_Shift_11 = Dbg_Shift_0;
assign Dbg_Shift_12 = Dbg_Shift_0;
assign Dbg_Shift_13 = Dbg_Shift_0;
assign Dbg_Shift_14 = Dbg_Shift_0;
assign Dbg_Shift_15 = Dbg_Shift_0;
assign Dbg_Shift_16 = Dbg_Shift_0;
assign Dbg_Shift_17 = Dbg_Shift_0;
assign Dbg_Shift_18 = Dbg_Shift_0;
assign Dbg_Shift_19 = Dbg_Shift_0;
assign Dbg_Shift_2 = Dbg_Shift_0;
assign Dbg_Shift_20 = Dbg_Shift_0;
assign Dbg_Shift_21 = Dbg_Shift_0;
assign Dbg_Shift_22 = Dbg_Shift_0;
assign Dbg_Shift_23 = Dbg_Shift_0;
assign Dbg_Shift_24 = Dbg_Shift_0;
assign Dbg_Shift_25 = Dbg_Shift_0;
assign Dbg_Shift_26 = Dbg_Shift_0;
assign Dbg_Shift_27 = Dbg_Shift_0;
assign Dbg_Shift_28 = Dbg_Shift_0;
assign Dbg_Shift_29 = Dbg_Shift_0;
assign Dbg_Shift_3 = Dbg_Shift_0;
assign Dbg_Shift_30 = Dbg_Shift_0;
assign Dbg_Shift_31 = Dbg_Shift_0;
assign Dbg_Shift_4 = Dbg_Shift_0;
assign Dbg_Shift_5 = Dbg_Shift_0;
assign Dbg_Shift_6 = Dbg_Shift_0;
assign Dbg_Shift_7 = Dbg_Shift_0;
assign Dbg_Shift_8 = Dbg_Shift_0;
assign Dbg_Shift_9 = Dbg_Shift_0;
assign Dbg_TDI_0 = Ext_JTAG_TDI;
assign Dbg_TDI_1 = Ext_JTAG_TDI;
assign Dbg_TDI_10 = Ext_JTAG_TDI;
assign Dbg_TDI_11 = Ext_JTAG_TDI;
assign Dbg_TDI_12 = Ext_JTAG_TDI;
assign Dbg_TDI_13 = Ext_JTAG_TDI;
assign Dbg_TDI_14 = Ext_JTAG_TDI;
assign Dbg_TDI_15 = Ext_JTAG_TDI;
assign Dbg_TDI_16 = Ext_JTAG_TDI;
assign Dbg_TDI_17 = Ext_JTAG_TDI;
assign Dbg_TDI_18 = Ext_JTAG_TDI;
assign Dbg_TDI_19 = Ext_JTAG_TDI;
assign Dbg_TDI_2 = Ext_JTAG_TDI;
assign Dbg_TDI_20 = Ext_JTAG_TDI;
assign Dbg_TDI_21 = Ext_JTAG_TDI;
assign Dbg_TDI_22 = Ext_JTAG_TDI;
assign Dbg_TDI_23 = Ext_JTAG_TDI;
assign Dbg_TDI_24 = Ext_JTAG_TDI;
assign Dbg_TDI_25 = Ext_JTAG_TDI;
assign Dbg_TDI_26 = Ext_JTAG_TDI;
assign Dbg_TDI_27 = Ext_JTAG_TDI;
assign Dbg_TDI_28 = Ext_JTAG_TDI;
assign Dbg_TDI_29 = Ext_JTAG_TDI;
assign Dbg_TDI_3 = Ext_JTAG_TDI;
assign Dbg_TDI_30 = Ext_JTAG_TDI;
assign Dbg_TDI_31 = Ext_JTAG_TDI;
assign Dbg_TDI_4 = Ext_JTAG_TDI;
assign Dbg_TDI_5 = Ext_JTAG_TDI;
assign Dbg_TDI_6 = Ext_JTAG_TDI;
assign Dbg_TDI_7 = Ext_JTAG_TDI;
assign Dbg_TDI_8 = Ext_JTAG_TDI;
assign Dbg_TDI_9 = Ext_JTAG_TDI;
assign Dbg_TrClk_0 = \<const0> ;
assign Dbg_TrClk_1 = \<const0> ;
assign Dbg_TrClk_10 = \<const0> ;
assign Dbg_TrClk_11 = \<const0> ;
assign Dbg_TrClk_12 = \<const0> ;
assign Dbg_TrClk_13 = \<const0> ;
assign Dbg_TrClk_14 = \<const0> ;
assign Dbg_TrClk_15 = \<const0> ;
assign Dbg_TrClk_16 = \<const0> ;
assign Dbg_TrClk_17 = \<const0> ;
assign Dbg_TrClk_18 = \<const0> ;
assign Dbg_TrClk_19 = \<const0> ;
assign Dbg_TrClk_2 = \<const0> ;
assign Dbg_TrClk_20 = \<const0> ;
assign Dbg_TrClk_21 = \<const0> ;
assign Dbg_TrClk_22 = \<const0> ;
assign Dbg_TrClk_23 = \<const0> ;
assign Dbg_TrClk_24 = \<const0> ;
assign Dbg_TrClk_25 = \<const0> ;
assign Dbg_TrClk_26 = \<const0> ;
assign Dbg_TrClk_27 = \<const0> ;
assign Dbg_TrClk_28 = \<const0> ;
assign Dbg_TrClk_29 = \<const0> ;
assign Dbg_TrClk_3 = \<const0> ;
assign Dbg_TrClk_30 = \<const0> ;
assign Dbg_TrClk_31 = \<const0> ;
assign Dbg_TrClk_4 = \<const0> ;
assign Dbg_TrClk_5 = \<const0> ;
assign Dbg_TrClk_6 = \<const0> ;
assign Dbg_TrClk_7 = \<const0> ;
assign Dbg_TrClk_8 = \<const0> ;
assign Dbg_TrClk_9 = \<const0> ;
assign Dbg_TrReady_0 = \<const0> ;
assign Dbg_TrReady_1 = \<const0> ;
assign Dbg_TrReady_10 = \<const0> ;
assign Dbg_TrReady_11 = \<const0> ;
assign Dbg_TrReady_12 = \<const0> ;
assign Dbg_TrReady_13 = \<const0> ;
assign Dbg_TrReady_14 = \<const0> ;
assign Dbg_TrReady_15 = \<const0> ;
assign Dbg_TrReady_16 = \<const0> ;
assign Dbg_TrReady_17 = \<const0> ;
assign Dbg_TrReady_18 = \<const0> ;
assign Dbg_TrReady_19 = \<const0> ;
assign Dbg_TrReady_2 = \<const0> ;
assign Dbg_TrReady_20 = \<const0> ;
assign Dbg_TrReady_21 = \<const0> ;
assign Dbg_TrReady_22 = \<const0> ;
assign Dbg_TrReady_23 = \<const0> ;
assign Dbg_TrReady_24 = \<const0> ;
assign Dbg_TrReady_25 = \<const0> ;
assign Dbg_TrReady_26 = \<const0> ;
assign Dbg_TrReady_27 = \<const0> ;
assign Dbg_TrReady_28 = \<const0> ;
assign Dbg_TrReady_29 = \<const0> ;
assign Dbg_TrReady_3 = \<const0> ;
assign Dbg_TrReady_30 = \<const0> ;
assign Dbg_TrReady_31 = \<const0> ;
assign Dbg_TrReady_4 = \<const0> ;
assign Dbg_TrReady_5 = \<const0> ;
assign Dbg_TrReady_6 = \<const0> ;
assign Dbg_TrReady_7 = \<const0> ;
assign Dbg_TrReady_8 = \<const0> ;
assign Dbg_TrReady_9 = \<const0> ;
assign Dbg_Trig_Ack_In_0[0] = \<const0> ;
assign Dbg_Trig_Ack_In_0[1] = \<const0> ;
assign Dbg_Trig_Ack_In_0[2] = \<const0> ;
assign Dbg_Trig_Ack_In_0[3] = \<const0> ;
assign Dbg_Trig_Ack_In_0[4] = \<const0> ;
assign Dbg_Trig_Ack_In_0[5] = \<const0> ;
assign Dbg_Trig_Ack_In_0[6] = \<const0> ;
assign Dbg_Trig_Ack_In_0[7] = \<const0> ;
assign Dbg_Trig_Ack_In_1[0] = \<const0> ;
assign Dbg_Trig_Ack_In_1[1] = \<const0> ;
assign Dbg_Trig_Ack_In_1[2] = \<const0> ;
assign Dbg_Trig_Ack_In_1[3] = \<const0> ;
assign Dbg_Trig_Ack_In_1[4] = \<const0> ;
assign Dbg_Trig_Ack_In_1[5] = \<const0> ;
assign Dbg_Trig_Ack_In_1[6] = \<const0> ;
assign Dbg_Trig_Ack_In_1[7] = \<const0> ;
assign Dbg_Trig_Ack_In_10[0] = \<const0> ;
assign Dbg_Trig_Ack_In_10[1] = \<const0> ;
assign Dbg_Trig_Ack_In_10[2] = \<const0> ;
assign Dbg_Trig_Ack_In_10[3] = \<const0> ;
assign Dbg_Trig_Ack_In_10[4] = \<const0> ;
assign Dbg_Trig_Ack_In_10[5] = \<const0> ;
assign Dbg_Trig_Ack_In_10[6] = \<const0> ;
assign Dbg_Trig_Ack_In_10[7] = \<const0> ;
assign Dbg_Trig_Ack_In_11[0] = \<const0> ;
assign Dbg_Trig_Ack_In_11[1] = \<const0> ;
assign Dbg_Trig_Ack_In_11[2] = \<const0> ;
assign Dbg_Trig_Ack_In_11[3] = \<const0> ;
assign Dbg_Trig_Ack_In_11[4] = \<const0> ;
assign Dbg_Trig_Ack_In_11[5] = \<const0> ;
assign Dbg_Trig_Ack_In_11[6] = \<const0> ;
assign Dbg_Trig_Ack_In_11[7] = \<const0> ;
assign Dbg_Trig_Ack_In_12[0] = \<const0> ;
assign Dbg_Trig_Ack_In_12[1] = \<const0> ;
assign Dbg_Trig_Ack_In_12[2] = \<const0> ;
assign Dbg_Trig_Ack_In_12[3] = \<const0> ;
assign Dbg_Trig_Ack_In_12[4] = \<const0> ;
assign Dbg_Trig_Ack_In_12[5] = \<const0> ;
assign Dbg_Trig_Ack_In_12[6] = \<const0> ;
assign Dbg_Trig_Ack_In_12[7] = \<const0> ;
assign Dbg_Trig_Ack_In_13[0] = \<const0> ;
assign Dbg_Trig_Ack_In_13[1] = \<const0> ;
assign Dbg_Trig_Ack_In_13[2] = \<const0> ;
assign Dbg_Trig_Ack_In_13[3] = \<const0> ;
assign Dbg_Trig_Ack_In_13[4] = \<const0> ;
assign Dbg_Trig_Ack_In_13[5] = \<const0> ;
assign Dbg_Trig_Ack_In_13[6] = \<const0> ;
assign Dbg_Trig_Ack_In_13[7] = \<const0> ;
assign Dbg_Trig_Ack_In_14[0] = \<const0> ;
assign Dbg_Trig_Ack_In_14[1] = \<const0> ;
assign Dbg_Trig_Ack_In_14[2] = \<const0> ;
assign Dbg_Trig_Ack_In_14[3] = \<const0> ;
assign Dbg_Trig_Ack_In_14[4] = \<const0> ;
assign Dbg_Trig_Ack_In_14[5] = \<const0> ;
assign Dbg_Trig_Ack_In_14[6] = \<const0> ;
assign Dbg_Trig_Ack_In_14[7] = \<const0> ;
assign Dbg_Trig_Ack_In_15[0] = \<const0> ;
assign Dbg_Trig_Ack_In_15[1] = \<const0> ;
assign Dbg_Trig_Ack_In_15[2] = \<const0> ;
assign Dbg_Trig_Ack_In_15[3] = \<const0> ;
assign Dbg_Trig_Ack_In_15[4] = \<const0> ;
assign Dbg_Trig_Ack_In_15[5] = \<const0> ;
assign Dbg_Trig_Ack_In_15[6] = \<const0> ;
assign Dbg_Trig_Ack_In_15[7] = \<const0> ;
assign Dbg_Trig_Ack_In_16[0] = \<const0> ;
assign Dbg_Trig_Ack_In_16[1] = \<const0> ;
assign Dbg_Trig_Ack_In_16[2] = \<const0> ;
assign Dbg_Trig_Ack_In_16[3] = \<const0> ;
assign Dbg_Trig_Ack_In_16[4] = \<const0> ;
assign Dbg_Trig_Ack_In_16[5] = \<const0> ;
assign Dbg_Trig_Ack_In_16[6] = \<const0> ;
assign Dbg_Trig_Ack_In_16[7] = \<const0> ;
assign Dbg_Trig_Ack_In_17[0] = \<const0> ;
assign Dbg_Trig_Ack_In_17[1] = \<const0> ;
assign Dbg_Trig_Ack_In_17[2] = \<const0> ;
assign Dbg_Trig_Ack_In_17[3] = \<const0> ;
assign Dbg_Trig_Ack_In_17[4] = \<const0> ;
assign Dbg_Trig_Ack_In_17[5] = \<const0> ;
assign Dbg_Trig_Ack_In_17[6] = \<const0> ;
assign Dbg_Trig_Ack_In_17[7] = \<const0> ;
assign Dbg_Trig_Ack_In_18[0] = \<const0> ;
assign Dbg_Trig_Ack_In_18[1] = \<const0> ;
assign Dbg_Trig_Ack_In_18[2] = \<const0> ;
assign Dbg_Trig_Ack_In_18[3] = \<const0> ;
assign Dbg_Trig_Ack_In_18[4] = \<const0> ;
assign Dbg_Trig_Ack_In_18[5] = \<const0> ;
assign Dbg_Trig_Ack_In_18[6] = \<const0> ;
assign Dbg_Trig_Ack_In_18[7] = \<const0> ;
assign Dbg_Trig_Ack_In_19[0] = \<const0> ;
assign Dbg_Trig_Ack_In_19[1] = \<const0> ;
assign Dbg_Trig_Ack_In_19[2] = \<const0> ;
assign Dbg_Trig_Ack_In_19[3] = \<const0> ;
assign Dbg_Trig_Ack_In_19[4] = \<const0> ;
assign Dbg_Trig_Ack_In_19[5] = \<const0> ;
assign Dbg_Trig_Ack_In_19[6] = \<const0> ;
assign Dbg_Trig_Ack_In_19[7] = \<const0> ;
assign Dbg_Trig_Ack_In_2[0] = \<const0> ;
assign Dbg_Trig_Ack_In_2[1] = \<const0> ;
assign Dbg_Trig_Ack_In_2[2] = \<const0> ;
assign Dbg_Trig_Ack_In_2[3] = \<const0> ;
assign Dbg_Trig_Ack_In_2[4] = \<const0> ;
assign Dbg_Trig_Ack_In_2[5] = \<const0> ;
assign Dbg_Trig_Ack_In_2[6] = \<const0> ;
assign Dbg_Trig_Ack_In_2[7] = \<const0> ;
assign Dbg_Trig_Ack_In_20[0] = \<const0> ;
assign Dbg_Trig_Ack_In_20[1] = \<const0> ;
assign Dbg_Trig_Ack_In_20[2] = \<const0> ;
assign Dbg_Trig_Ack_In_20[3] = \<const0> ;
assign Dbg_Trig_Ack_In_20[4] = \<const0> ;
assign Dbg_Trig_Ack_In_20[5] = \<const0> ;
assign Dbg_Trig_Ack_In_20[6] = \<const0> ;
assign Dbg_Trig_Ack_In_20[7] = \<const0> ;
assign Dbg_Trig_Ack_In_21[0] = \<const0> ;
assign Dbg_Trig_Ack_In_21[1] = \<const0> ;
assign Dbg_Trig_Ack_In_21[2] = \<const0> ;
assign Dbg_Trig_Ack_In_21[3] = \<const0> ;
assign Dbg_Trig_Ack_In_21[4] = \<const0> ;
assign Dbg_Trig_Ack_In_21[5] = \<const0> ;
assign Dbg_Trig_Ack_In_21[6] = \<const0> ;
assign Dbg_Trig_Ack_In_21[7] = \<const0> ;
assign Dbg_Trig_Ack_In_22[0] = \<const0> ;
assign Dbg_Trig_Ack_In_22[1] = \<const0> ;
assign Dbg_Trig_Ack_In_22[2] = \<const0> ;
assign Dbg_Trig_Ack_In_22[3] = \<const0> ;
assign Dbg_Trig_Ack_In_22[4] = \<const0> ;
assign Dbg_Trig_Ack_In_22[5] = \<const0> ;
assign Dbg_Trig_Ack_In_22[6] = \<const0> ;
assign Dbg_Trig_Ack_In_22[7] = \<const0> ;
assign Dbg_Trig_Ack_In_23[0] = \<const0> ;
assign Dbg_Trig_Ack_In_23[1] = \<const0> ;
assign Dbg_Trig_Ack_In_23[2] = \<const0> ;
assign Dbg_Trig_Ack_In_23[3] = \<const0> ;
assign Dbg_Trig_Ack_In_23[4] = \<const0> ;
assign Dbg_Trig_Ack_In_23[5] = \<const0> ;
assign Dbg_Trig_Ack_In_23[6] = \<const0> ;
assign Dbg_Trig_Ack_In_23[7] = \<const0> ;
assign Dbg_Trig_Ack_In_24[0] = \<const0> ;
assign Dbg_Trig_Ack_In_24[1] = \<const0> ;
assign Dbg_Trig_Ack_In_24[2] = \<const0> ;
assign Dbg_Trig_Ack_In_24[3] = \<const0> ;
assign Dbg_Trig_Ack_In_24[4] = \<const0> ;
assign Dbg_Trig_Ack_In_24[5] = \<const0> ;
assign Dbg_Trig_Ack_In_24[6] = \<const0> ;
assign Dbg_Trig_Ack_In_24[7] = \<const0> ;
assign Dbg_Trig_Ack_In_25[0] = \<const0> ;
assign Dbg_Trig_Ack_In_25[1] = \<const0> ;
assign Dbg_Trig_Ack_In_25[2] = \<const0> ;
assign Dbg_Trig_Ack_In_25[3] = \<const0> ;
assign Dbg_Trig_Ack_In_25[4] = \<const0> ;
assign Dbg_Trig_Ack_In_25[5] = \<const0> ;
assign Dbg_Trig_Ack_In_25[6] = \<const0> ;
assign Dbg_Trig_Ack_In_25[7] = \<const0> ;
assign Dbg_Trig_Ack_In_26[0] = \<const0> ;
assign Dbg_Trig_Ack_In_26[1] = \<const0> ;
assign Dbg_Trig_Ack_In_26[2] = \<const0> ;
assign Dbg_Trig_Ack_In_26[3] = \<const0> ;
assign Dbg_Trig_Ack_In_26[4] = \<const0> ;
assign Dbg_Trig_Ack_In_26[5] = \<const0> ;
assign Dbg_Trig_Ack_In_26[6] = \<const0> ;
assign Dbg_Trig_Ack_In_26[7] = \<const0> ;
assign Dbg_Trig_Ack_In_27[0] = \<const0> ;
assign Dbg_Trig_Ack_In_27[1] = \<const0> ;
assign Dbg_Trig_Ack_In_27[2] = \<const0> ;
assign Dbg_Trig_Ack_In_27[3] = \<const0> ;
assign Dbg_Trig_Ack_In_27[4] = \<const0> ;
assign Dbg_Trig_Ack_In_27[5] = \<const0> ;
assign Dbg_Trig_Ack_In_27[6] = \<const0> ;
assign Dbg_Trig_Ack_In_27[7] = \<const0> ;
assign Dbg_Trig_Ack_In_28[0] = \<const0> ;
assign Dbg_Trig_Ack_In_28[1] = \<const0> ;
assign Dbg_Trig_Ack_In_28[2] = \<const0> ;
assign Dbg_Trig_Ack_In_28[3] = \<const0> ;
assign Dbg_Trig_Ack_In_28[4] = \<const0> ;
assign Dbg_Trig_Ack_In_28[5] = \<const0> ;
assign Dbg_Trig_Ack_In_28[6] = \<const0> ;
assign Dbg_Trig_Ack_In_28[7] = \<const0> ;
assign Dbg_Trig_Ack_In_29[0] = \<const0> ;
assign Dbg_Trig_Ack_In_29[1] = \<const0> ;
assign Dbg_Trig_Ack_In_29[2] = \<const0> ;
assign Dbg_Trig_Ack_In_29[3] = \<const0> ;
assign Dbg_Trig_Ack_In_29[4] = \<const0> ;
assign Dbg_Trig_Ack_In_29[5] = \<const0> ;
assign Dbg_Trig_Ack_In_29[6] = \<const0> ;
assign Dbg_Trig_Ack_In_29[7] = \<const0> ;
assign Dbg_Trig_Ack_In_3[0] = \<const0> ;
assign Dbg_Trig_Ack_In_3[1] = \<const0> ;
assign Dbg_Trig_Ack_In_3[2] = \<const0> ;
assign Dbg_Trig_Ack_In_3[3] = \<const0> ;
assign Dbg_Trig_Ack_In_3[4] = \<const0> ;
assign Dbg_Trig_Ack_In_3[5] = \<const0> ;
assign Dbg_Trig_Ack_In_3[6] = \<const0> ;
assign Dbg_Trig_Ack_In_3[7] = \<const0> ;
assign Dbg_Trig_Ack_In_30[0] = \<const0> ;
assign Dbg_Trig_Ack_In_30[1] = \<const0> ;
assign Dbg_Trig_Ack_In_30[2] = \<const0> ;
assign Dbg_Trig_Ack_In_30[3] = \<const0> ;
assign Dbg_Trig_Ack_In_30[4] = \<const0> ;
assign Dbg_Trig_Ack_In_30[5] = \<const0> ;
assign Dbg_Trig_Ack_In_30[6] = \<const0> ;
assign Dbg_Trig_Ack_In_30[7] = \<const0> ;
assign Dbg_Trig_Ack_In_31[0] = \<const0> ;
assign Dbg_Trig_Ack_In_31[1] = \<const0> ;
assign Dbg_Trig_Ack_In_31[2] = \<const0> ;
assign Dbg_Trig_Ack_In_31[3] = \<const0> ;
assign Dbg_Trig_Ack_In_31[4] = \<const0> ;
assign Dbg_Trig_Ack_In_31[5] = \<const0> ;
assign Dbg_Trig_Ack_In_31[6] = \<const0> ;
assign Dbg_Trig_Ack_In_31[7] = \<const0> ;
assign Dbg_Trig_Ack_In_4[0] = \<const0> ;
assign Dbg_Trig_Ack_In_4[1] = \<const0> ;
assign Dbg_Trig_Ack_In_4[2] = \<const0> ;
assign Dbg_Trig_Ack_In_4[3] = \<const0> ;
assign Dbg_Trig_Ack_In_4[4] = \<const0> ;
assign Dbg_Trig_Ack_In_4[5] = \<const0> ;
assign Dbg_Trig_Ack_In_4[6] = \<const0> ;
assign Dbg_Trig_Ack_In_4[7] = \<const0> ;
assign Dbg_Trig_Ack_In_5[0] = \<const0> ;
assign Dbg_Trig_Ack_In_5[1] = \<const0> ;
assign Dbg_Trig_Ack_In_5[2] = \<const0> ;
assign Dbg_Trig_Ack_In_5[3] = \<const0> ;
assign Dbg_Trig_Ack_In_5[4] = \<const0> ;
assign Dbg_Trig_Ack_In_5[5] = \<const0> ;
assign Dbg_Trig_Ack_In_5[6] = \<const0> ;
assign Dbg_Trig_Ack_In_5[7] = \<const0> ;
assign Dbg_Trig_Ack_In_6[0] = \<const0> ;
assign Dbg_Trig_Ack_In_6[1] = \<const0> ;
assign Dbg_Trig_Ack_In_6[2] = \<const0> ;
assign Dbg_Trig_Ack_In_6[3] = \<const0> ;
assign Dbg_Trig_Ack_In_6[4] = \<const0> ;
assign Dbg_Trig_Ack_In_6[5] = \<const0> ;
assign Dbg_Trig_Ack_In_6[6] = \<const0> ;
assign Dbg_Trig_Ack_In_6[7] = \<const0> ;
assign Dbg_Trig_Ack_In_7[0] = \<const0> ;
assign Dbg_Trig_Ack_In_7[1] = \<const0> ;
assign Dbg_Trig_Ack_In_7[2] = \<const0> ;
assign Dbg_Trig_Ack_In_7[3] = \<const0> ;
assign Dbg_Trig_Ack_In_7[4] = \<const0> ;
assign Dbg_Trig_Ack_In_7[5] = \<const0> ;
assign Dbg_Trig_Ack_In_7[6] = \<const0> ;
assign Dbg_Trig_Ack_In_7[7] = \<const0> ;
assign Dbg_Trig_Ack_In_8[0] = \<const0> ;
assign Dbg_Trig_Ack_In_8[1] = \<const0> ;
assign Dbg_Trig_Ack_In_8[2] = \<const0> ;
assign Dbg_Trig_Ack_In_8[3] = \<const0> ;
assign Dbg_Trig_Ack_In_8[4] = \<const0> ;
assign Dbg_Trig_Ack_In_8[5] = \<const0> ;
assign Dbg_Trig_Ack_In_8[6] = \<const0> ;
assign Dbg_Trig_Ack_In_8[7] = \<const0> ;
assign Dbg_Trig_Ack_In_9[0] = \<const0> ;
assign Dbg_Trig_Ack_In_9[1] = \<const0> ;
assign Dbg_Trig_Ack_In_9[2] = \<const0> ;
assign Dbg_Trig_Ack_In_9[3] = \<const0> ;
assign Dbg_Trig_Ack_In_9[4] = \<const0> ;
assign Dbg_Trig_Ack_In_9[5] = \<const0> ;
assign Dbg_Trig_Ack_In_9[6] = \<const0> ;
assign Dbg_Trig_Ack_In_9[7] = \<const0> ;
assign Dbg_Trig_Out_0[0] = \<const0> ;
assign Dbg_Trig_Out_0[1] = \<const0> ;
assign Dbg_Trig_Out_0[2] = \<const0> ;
assign Dbg_Trig_Out_0[3] = \<const0> ;
assign Dbg_Trig_Out_0[4] = \<const0> ;
assign Dbg_Trig_Out_0[5] = \<const0> ;
assign Dbg_Trig_Out_0[6] = \<const0> ;
assign Dbg_Trig_Out_0[7] = \<const0> ;
assign Dbg_Trig_Out_1[0] = \<const0> ;
assign Dbg_Trig_Out_1[1] = \<const0> ;
assign Dbg_Trig_Out_1[2] = \<const0> ;
assign Dbg_Trig_Out_1[3] = \<const0> ;
assign Dbg_Trig_Out_1[4] = \<const0> ;
assign Dbg_Trig_Out_1[5] = \<const0> ;
assign Dbg_Trig_Out_1[6] = \<const0> ;
assign Dbg_Trig_Out_1[7] = \<const0> ;
assign Dbg_Trig_Out_10[0] = \<const0> ;
assign Dbg_Trig_Out_10[1] = \<const0> ;
assign Dbg_Trig_Out_10[2] = \<const0> ;
assign Dbg_Trig_Out_10[3] = \<const0> ;
assign Dbg_Trig_Out_10[4] = \<const0> ;
assign Dbg_Trig_Out_10[5] = \<const0> ;
assign Dbg_Trig_Out_10[6] = \<const0> ;
assign Dbg_Trig_Out_10[7] = \<const0> ;
assign Dbg_Trig_Out_11[0] = \<const0> ;
assign Dbg_Trig_Out_11[1] = \<const0> ;
assign Dbg_Trig_Out_11[2] = \<const0> ;
assign Dbg_Trig_Out_11[3] = \<const0> ;
assign Dbg_Trig_Out_11[4] = \<const0> ;
assign Dbg_Trig_Out_11[5] = \<const0> ;
assign Dbg_Trig_Out_11[6] = \<const0> ;
assign Dbg_Trig_Out_11[7] = \<const0> ;
assign Dbg_Trig_Out_12[0] = \<const0> ;
assign Dbg_Trig_Out_12[1] = \<const0> ;
assign Dbg_Trig_Out_12[2] = \<const0> ;
assign Dbg_Trig_Out_12[3] = \<const0> ;
assign Dbg_Trig_Out_12[4] = \<const0> ;
assign Dbg_Trig_Out_12[5] = \<const0> ;
assign Dbg_Trig_Out_12[6] = \<const0> ;
assign Dbg_Trig_Out_12[7] = \<const0> ;
assign Dbg_Trig_Out_13[0] = \<const0> ;
assign Dbg_Trig_Out_13[1] = \<const0> ;
assign Dbg_Trig_Out_13[2] = \<const0> ;
assign Dbg_Trig_Out_13[3] = \<const0> ;
assign Dbg_Trig_Out_13[4] = \<const0> ;
assign Dbg_Trig_Out_13[5] = \<const0> ;
assign Dbg_Trig_Out_13[6] = \<const0> ;
assign Dbg_Trig_Out_13[7] = \<const0> ;
assign Dbg_Trig_Out_14[0] = \<const0> ;
assign Dbg_Trig_Out_14[1] = \<const0> ;
assign Dbg_Trig_Out_14[2] = \<const0> ;
assign Dbg_Trig_Out_14[3] = \<const0> ;
assign Dbg_Trig_Out_14[4] = \<const0> ;
assign Dbg_Trig_Out_14[5] = \<const0> ;
assign Dbg_Trig_Out_14[6] = \<const0> ;
assign Dbg_Trig_Out_14[7] = \<const0> ;
assign Dbg_Trig_Out_15[0] = \<const0> ;
assign Dbg_Trig_Out_15[1] = \<const0> ;
assign Dbg_Trig_Out_15[2] = \<const0> ;
assign Dbg_Trig_Out_15[3] = \<const0> ;
assign Dbg_Trig_Out_15[4] = \<const0> ;
assign Dbg_Trig_Out_15[5] = \<const0> ;
assign Dbg_Trig_Out_15[6] = \<const0> ;
assign Dbg_Trig_Out_15[7] = \<const0> ;
assign Dbg_Trig_Out_16[0] = \<const0> ;
assign Dbg_Trig_Out_16[1] = \<const0> ;
assign Dbg_Trig_Out_16[2] = \<const0> ;
assign Dbg_Trig_Out_16[3] = \<const0> ;
assign Dbg_Trig_Out_16[4] = \<const0> ;
assign Dbg_Trig_Out_16[5] = \<const0> ;
assign Dbg_Trig_Out_16[6] = \<const0> ;
assign Dbg_Trig_Out_16[7] = \<const0> ;
assign Dbg_Trig_Out_17[0] = \<const0> ;
assign Dbg_Trig_Out_17[1] = \<const0> ;
assign Dbg_Trig_Out_17[2] = \<const0> ;
assign Dbg_Trig_Out_17[3] = \<const0> ;
assign Dbg_Trig_Out_17[4] = \<const0> ;
assign Dbg_Trig_Out_17[5] = \<const0> ;
assign Dbg_Trig_Out_17[6] = \<const0> ;
assign Dbg_Trig_Out_17[7] = \<const0> ;
assign Dbg_Trig_Out_18[0] = \<const0> ;
assign Dbg_Trig_Out_18[1] = \<const0> ;
assign Dbg_Trig_Out_18[2] = \<const0> ;
assign Dbg_Trig_Out_18[3] = \<const0> ;
assign Dbg_Trig_Out_18[4] = \<const0> ;
assign Dbg_Trig_Out_18[5] = \<const0> ;
assign Dbg_Trig_Out_18[6] = \<const0> ;
assign Dbg_Trig_Out_18[7] = \<const0> ;
assign Dbg_Trig_Out_19[0] = \<const0> ;
assign Dbg_Trig_Out_19[1] = \<const0> ;
assign Dbg_Trig_Out_19[2] = \<const0> ;
assign Dbg_Trig_Out_19[3] = \<const0> ;
assign Dbg_Trig_Out_19[4] = \<const0> ;
assign Dbg_Trig_Out_19[5] = \<const0> ;
assign Dbg_Trig_Out_19[6] = \<const0> ;
assign Dbg_Trig_Out_19[7] = \<const0> ;
assign Dbg_Trig_Out_2[0] = \<const0> ;
assign Dbg_Trig_Out_2[1] = \<const0> ;
assign Dbg_Trig_Out_2[2] = \<const0> ;
assign Dbg_Trig_Out_2[3] = \<const0> ;
assign Dbg_Trig_Out_2[4] = \<const0> ;
assign Dbg_Trig_Out_2[5] = \<const0> ;
assign Dbg_Trig_Out_2[6] = \<const0> ;
assign Dbg_Trig_Out_2[7] = \<const0> ;
assign Dbg_Trig_Out_20[0] = \<const0> ;
assign Dbg_Trig_Out_20[1] = \<const0> ;
assign Dbg_Trig_Out_20[2] = \<const0> ;
assign Dbg_Trig_Out_20[3] = \<const0> ;
assign Dbg_Trig_Out_20[4] = \<const0> ;
assign Dbg_Trig_Out_20[5] = \<const0> ;
assign Dbg_Trig_Out_20[6] = \<const0> ;
assign Dbg_Trig_Out_20[7] = \<const0> ;
assign Dbg_Trig_Out_21[0] = \<const0> ;
assign Dbg_Trig_Out_21[1] = \<const0> ;
assign Dbg_Trig_Out_21[2] = \<const0> ;
assign Dbg_Trig_Out_21[3] = \<const0> ;
assign Dbg_Trig_Out_21[4] = \<const0> ;
assign Dbg_Trig_Out_21[5] = \<const0> ;
assign Dbg_Trig_Out_21[6] = \<const0> ;
assign Dbg_Trig_Out_21[7] = \<const0> ;
assign Dbg_Trig_Out_22[0] = \<const0> ;
assign Dbg_Trig_Out_22[1] = \<const0> ;
assign Dbg_Trig_Out_22[2] = \<const0> ;
assign Dbg_Trig_Out_22[3] = \<const0> ;
assign Dbg_Trig_Out_22[4] = \<const0> ;
assign Dbg_Trig_Out_22[5] = \<const0> ;
assign Dbg_Trig_Out_22[6] = \<const0> ;
assign Dbg_Trig_Out_22[7] = \<const0> ;
assign Dbg_Trig_Out_23[0] = \<const0> ;
assign Dbg_Trig_Out_23[1] = \<const0> ;
assign Dbg_Trig_Out_23[2] = \<const0> ;
assign Dbg_Trig_Out_23[3] = \<const0> ;
assign Dbg_Trig_Out_23[4] = \<const0> ;
assign Dbg_Trig_Out_23[5] = \<const0> ;
assign Dbg_Trig_Out_23[6] = \<const0> ;
assign Dbg_Trig_Out_23[7] = \<const0> ;
assign Dbg_Trig_Out_24[0] = \<const0> ;
assign Dbg_Trig_Out_24[1] = \<const0> ;
assign Dbg_Trig_Out_24[2] = \<const0> ;
assign Dbg_Trig_Out_24[3] = \<const0> ;
assign Dbg_Trig_Out_24[4] = \<const0> ;
assign Dbg_Trig_Out_24[5] = \<const0> ;
assign Dbg_Trig_Out_24[6] = \<const0> ;
assign Dbg_Trig_Out_24[7] = \<const0> ;
assign Dbg_Trig_Out_25[0] = \<const0> ;
assign Dbg_Trig_Out_25[1] = \<const0> ;
assign Dbg_Trig_Out_25[2] = \<const0> ;
assign Dbg_Trig_Out_25[3] = \<const0> ;
assign Dbg_Trig_Out_25[4] = \<const0> ;
assign Dbg_Trig_Out_25[5] = \<const0> ;
assign Dbg_Trig_Out_25[6] = \<const0> ;
assign Dbg_Trig_Out_25[7] = \<const0> ;
assign Dbg_Trig_Out_26[0] = \<const0> ;
assign Dbg_Trig_Out_26[1] = \<const0> ;
assign Dbg_Trig_Out_26[2] = \<const0> ;
assign Dbg_Trig_Out_26[3] = \<const0> ;
assign Dbg_Trig_Out_26[4] = \<const0> ;
assign Dbg_Trig_Out_26[5] = \<const0> ;
assign Dbg_Trig_Out_26[6] = \<const0> ;
assign Dbg_Trig_Out_26[7] = \<const0> ;
assign Dbg_Trig_Out_27[0] = \<const0> ;
assign Dbg_Trig_Out_27[1] = \<const0> ;
assign Dbg_Trig_Out_27[2] = \<const0> ;
assign Dbg_Trig_Out_27[3] = \<const0> ;
assign Dbg_Trig_Out_27[4] = \<const0> ;
assign Dbg_Trig_Out_27[5] = \<const0> ;
assign Dbg_Trig_Out_27[6] = \<const0> ;
assign Dbg_Trig_Out_27[7] = \<const0> ;
assign Dbg_Trig_Out_28[0] = \<const0> ;
assign Dbg_Trig_Out_28[1] = \<const0> ;
assign Dbg_Trig_Out_28[2] = \<const0> ;
assign Dbg_Trig_Out_28[3] = \<const0> ;
assign Dbg_Trig_Out_28[4] = \<const0> ;
assign Dbg_Trig_Out_28[5] = \<const0> ;
assign Dbg_Trig_Out_28[6] = \<const0> ;
assign Dbg_Trig_Out_28[7] = \<const0> ;
assign Dbg_Trig_Out_29[0] = \<const0> ;
assign Dbg_Trig_Out_29[1] = \<const0> ;
assign Dbg_Trig_Out_29[2] = \<const0> ;
assign Dbg_Trig_Out_29[3] = \<const0> ;
assign Dbg_Trig_Out_29[4] = \<const0> ;
assign Dbg_Trig_Out_29[5] = \<const0> ;
assign Dbg_Trig_Out_29[6] = \<const0> ;
assign Dbg_Trig_Out_29[7] = \<const0> ;
assign Dbg_Trig_Out_3[0] = \<const0> ;
assign Dbg_Trig_Out_3[1] = \<const0> ;
assign Dbg_Trig_Out_3[2] = \<const0> ;
assign Dbg_Trig_Out_3[3] = \<const0> ;
assign Dbg_Trig_Out_3[4] = \<const0> ;
assign Dbg_Trig_Out_3[5] = \<const0> ;
assign Dbg_Trig_Out_3[6] = \<const0> ;
assign Dbg_Trig_Out_3[7] = \<const0> ;
assign Dbg_Trig_Out_30[0] = \<const0> ;
assign Dbg_Trig_Out_30[1] = \<const0> ;
assign Dbg_Trig_Out_30[2] = \<const0> ;
assign Dbg_Trig_Out_30[3] = \<const0> ;
assign Dbg_Trig_Out_30[4] = \<const0> ;
assign Dbg_Trig_Out_30[5] = \<const0> ;
assign Dbg_Trig_Out_30[6] = \<const0> ;
assign Dbg_Trig_Out_30[7] = \<const0> ;
assign Dbg_Trig_Out_31[0] = \<const0> ;
assign Dbg_Trig_Out_31[1] = \<const0> ;
assign Dbg_Trig_Out_31[2] = \<const0> ;
assign Dbg_Trig_Out_31[3] = \<const0> ;
assign Dbg_Trig_Out_31[4] = \<const0> ;
assign Dbg_Trig_Out_31[5] = \<const0> ;
assign Dbg_Trig_Out_31[6] = \<const0> ;
assign Dbg_Trig_Out_31[7] = \<const0> ;
assign Dbg_Trig_Out_4[0] = \<const0> ;
assign Dbg_Trig_Out_4[1] = \<const0> ;
assign Dbg_Trig_Out_4[2] = \<const0> ;
assign Dbg_Trig_Out_4[3] = \<const0> ;
assign Dbg_Trig_Out_4[4] = \<const0> ;
assign Dbg_Trig_Out_4[5] = \<const0> ;
assign Dbg_Trig_Out_4[6] = \<const0> ;
assign Dbg_Trig_Out_4[7] = \<const0> ;
assign Dbg_Trig_Out_5[0] = \<const0> ;
assign Dbg_Trig_Out_5[1] = \<const0> ;
assign Dbg_Trig_Out_5[2] = \<const0> ;
assign Dbg_Trig_Out_5[3] = \<const0> ;
assign Dbg_Trig_Out_5[4] = \<const0> ;
assign Dbg_Trig_Out_5[5] = \<const0> ;
assign Dbg_Trig_Out_5[6] = \<const0> ;
assign Dbg_Trig_Out_5[7] = \<const0> ;
assign Dbg_Trig_Out_6[0] = \<const0> ;
assign Dbg_Trig_Out_6[1] = \<const0> ;
assign Dbg_Trig_Out_6[2] = \<const0> ;
assign Dbg_Trig_Out_6[3] = \<const0> ;
assign Dbg_Trig_Out_6[4] = \<const0> ;
assign Dbg_Trig_Out_6[5] = \<const0> ;
assign Dbg_Trig_Out_6[6] = \<const0> ;
assign Dbg_Trig_Out_6[7] = \<const0> ;
assign Dbg_Trig_Out_7[0] = \<const0> ;
assign Dbg_Trig_Out_7[1] = \<const0> ;
assign Dbg_Trig_Out_7[2] = \<const0> ;
assign Dbg_Trig_Out_7[3] = \<const0> ;
assign Dbg_Trig_Out_7[4] = \<const0> ;
assign Dbg_Trig_Out_7[5] = \<const0> ;
assign Dbg_Trig_Out_7[6] = \<const0> ;
assign Dbg_Trig_Out_7[7] = \<const0> ;
assign Dbg_Trig_Out_8[0] = \<const0> ;
assign Dbg_Trig_Out_8[1] = \<const0> ;
assign Dbg_Trig_Out_8[2] = \<const0> ;
assign Dbg_Trig_Out_8[3] = \<const0> ;
assign Dbg_Trig_Out_8[4] = \<const0> ;
assign Dbg_Trig_Out_8[5] = \<const0> ;
assign Dbg_Trig_Out_8[6] = \<const0> ;
assign Dbg_Trig_Out_8[7] = \<const0> ;
assign Dbg_Trig_Out_9[0] = \<const0> ;
assign Dbg_Trig_Out_9[1] = \<const0> ;
assign Dbg_Trig_Out_9[2] = \<const0> ;
assign Dbg_Trig_Out_9[3] = \<const0> ;
assign Dbg_Trig_Out_9[4] = \<const0> ;
assign Dbg_Trig_Out_9[5] = \<const0> ;
assign Dbg_Trig_Out_9[6] = \<const0> ;
assign Dbg_Trig_Out_9[7] = \<const0> ;
assign Dbg_Update_0 = Dbg_Update_31;
assign Dbg_Update_1 = Dbg_Update_31;
assign Dbg_Update_10 = Dbg_Update_31;
assign Dbg_Update_11 = Dbg_Update_31;
assign Dbg_Update_12 = Dbg_Update_31;
assign Dbg_Update_13 = Dbg_Update_31;
assign Dbg_Update_14 = Dbg_Update_31;
assign Dbg_Update_15 = Dbg_Update_31;
assign Dbg_Update_16 = Dbg_Update_31;
assign Dbg_Update_17 = Dbg_Update_31;
assign Dbg_Update_18 = Dbg_Update_31;
assign Dbg_Update_19 = Dbg_Update_31;
assign Dbg_Update_2 = Dbg_Update_31;
assign Dbg_Update_20 = Dbg_Update_31;
assign Dbg_Update_21 = Dbg_Update_31;
assign Dbg_Update_22 = Dbg_Update_31;
assign Dbg_Update_23 = Dbg_Update_31;
assign Dbg_Update_24 = Dbg_Update_31;
assign Dbg_Update_25 = Dbg_Update_31;
assign Dbg_Update_26 = Dbg_Update_31;
assign Dbg_Update_27 = Dbg_Update_31;
assign Dbg_Update_28 = Dbg_Update_31;
assign Dbg_Update_29 = Dbg_Update_31;
assign Dbg_Update_3 = Dbg_Update_31;
assign Dbg_Update_30 = Dbg_Update_31;
assign Dbg_Update_4 = Dbg_Update_31;
assign Dbg_Update_5 = Dbg_Update_31;
assign Dbg_Update_6 = Dbg_Update_31;
assign Dbg_Update_7 = Dbg_Update_31;
assign Dbg_Update_8 = Dbg_Update_31;
assign Dbg_Update_9 = Dbg_Update_31;
assign Dbg_WDATA_0[31] = \<const0> ;
assign Dbg_WDATA_0[30] = \<const0> ;
assign Dbg_WDATA_0[29] = \<const0> ;
assign Dbg_WDATA_0[28] = \<const0> ;
assign Dbg_WDATA_0[27] = \<const0> ;
assign Dbg_WDATA_0[26] = \<const0> ;
assign Dbg_WDATA_0[25] = \<const0> ;
assign Dbg_WDATA_0[24] = \<const0> ;
assign Dbg_WDATA_0[23] = \<const0> ;
assign Dbg_WDATA_0[22] = \<const0> ;
assign Dbg_WDATA_0[21] = \<const0> ;
assign Dbg_WDATA_0[20] = \<const0> ;
assign Dbg_WDATA_0[19] = \<const0> ;
assign Dbg_WDATA_0[18] = \<const0> ;
assign Dbg_WDATA_0[17] = \<const0> ;
assign Dbg_WDATA_0[16] = \<const0> ;
assign Dbg_WDATA_0[15] = \<const0> ;
assign Dbg_WDATA_0[14] = \<const0> ;
assign Dbg_WDATA_0[13] = \<const0> ;
assign Dbg_WDATA_0[12] = \<const0> ;
assign Dbg_WDATA_0[11] = \<const0> ;
assign Dbg_WDATA_0[10] = \<const0> ;
assign Dbg_WDATA_0[9] = \<const0> ;
assign Dbg_WDATA_0[8] = \<const0> ;
assign Dbg_WDATA_0[7] = \<const0> ;
assign Dbg_WDATA_0[6] = \<const0> ;
assign Dbg_WDATA_0[5] = \<const0> ;
assign Dbg_WDATA_0[4] = \<const0> ;
assign Dbg_WDATA_0[3] = \<const0> ;
assign Dbg_WDATA_0[2] = \<const0> ;
assign Dbg_WDATA_0[1] = \<const0> ;
assign Dbg_WDATA_0[0] = \<const0> ;
assign Dbg_WDATA_1[31] = \<const0> ;
assign Dbg_WDATA_1[30] = \<const0> ;
assign Dbg_WDATA_1[29] = \<const0> ;
assign Dbg_WDATA_1[28] = \<const0> ;
assign Dbg_WDATA_1[27] = \<const0> ;
assign Dbg_WDATA_1[26] = \<const0> ;
assign Dbg_WDATA_1[25] = \<const0> ;
assign Dbg_WDATA_1[24] = \<const0> ;
assign Dbg_WDATA_1[23] = \<const0> ;
assign Dbg_WDATA_1[22] = \<const0> ;
assign Dbg_WDATA_1[21] = \<const0> ;
assign Dbg_WDATA_1[20] = \<const0> ;
assign Dbg_WDATA_1[19] = \<const0> ;
assign Dbg_WDATA_1[18] = \<const0> ;
assign Dbg_WDATA_1[17] = \<const0> ;
assign Dbg_WDATA_1[16] = \<const0> ;
assign Dbg_WDATA_1[15] = \<const0> ;
assign Dbg_WDATA_1[14] = \<const0> ;
assign Dbg_WDATA_1[13] = \<const0> ;
assign Dbg_WDATA_1[12] = \<const0> ;
assign Dbg_WDATA_1[11] = \<const0> ;
assign Dbg_WDATA_1[10] = \<const0> ;
assign Dbg_WDATA_1[9] = \<const0> ;
assign Dbg_WDATA_1[8] = \<const0> ;
assign Dbg_WDATA_1[7] = \<const0> ;
assign Dbg_WDATA_1[6] = \<const0> ;
assign Dbg_WDATA_1[5] = \<const0> ;
assign Dbg_WDATA_1[4] = \<const0> ;
assign Dbg_WDATA_1[3] = \<const0> ;
assign Dbg_WDATA_1[2] = \<const0> ;
assign Dbg_WDATA_1[1] = \<const0> ;
assign Dbg_WDATA_1[0] = \<const0> ;
assign Dbg_WDATA_10[31] = \<const0> ;
assign Dbg_WDATA_10[30] = \<const0> ;
assign Dbg_WDATA_10[29] = \<const0> ;
assign Dbg_WDATA_10[28] = \<const0> ;
assign Dbg_WDATA_10[27] = \<const0> ;
assign Dbg_WDATA_10[26] = \<const0> ;
assign Dbg_WDATA_10[25] = \<const0> ;
assign Dbg_WDATA_10[24] = \<const0> ;
assign Dbg_WDATA_10[23] = \<const0> ;
assign Dbg_WDATA_10[22] = \<const0> ;
assign Dbg_WDATA_10[21] = \<const0> ;
assign Dbg_WDATA_10[20] = \<const0> ;
assign Dbg_WDATA_10[19] = \<const0> ;
assign Dbg_WDATA_10[18] = \<const0> ;
assign Dbg_WDATA_10[17] = \<const0> ;
assign Dbg_WDATA_10[16] = \<const0> ;
assign Dbg_WDATA_10[15] = \<const0> ;
assign Dbg_WDATA_10[14] = \<const0> ;
assign Dbg_WDATA_10[13] = \<const0> ;
assign Dbg_WDATA_10[12] = \<const0> ;
assign Dbg_WDATA_10[11] = \<const0> ;
assign Dbg_WDATA_10[10] = \<const0> ;
assign Dbg_WDATA_10[9] = \<const0> ;
assign Dbg_WDATA_10[8] = \<const0> ;
assign Dbg_WDATA_10[7] = \<const0> ;
assign Dbg_WDATA_10[6] = \<const0> ;
assign Dbg_WDATA_10[5] = \<const0> ;
assign Dbg_WDATA_10[4] = \<const0> ;
assign Dbg_WDATA_10[3] = \<const0> ;
assign Dbg_WDATA_10[2] = \<const0> ;
assign Dbg_WDATA_10[1] = \<const0> ;
assign Dbg_WDATA_10[0] = \<const0> ;
assign Dbg_WDATA_11[31] = \<const0> ;
assign Dbg_WDATA_11[30] = \<const0> ;
assign Dbg_WDATA_11[29] = \<const0> ;
assign Dbg_WDATA_11[28] = \<const0> ;
assign Dbg_WDATA_11[27] = \<const0> ;
assign Dbg_WDATA_11[26] = \<const0> ;
assign Dbg_WDATA_11[25] = \<const0> ;
assign Dbg_WDATA_11[24] = \<const0> ;
assign Dbg_WDATA_11[23] = \<const0> ;
assign Dbg_WDATA_11[22] = \<const0> ;
assign Dbg_WDATA_11[21] = \<const0> ;
assign Dbg_WDATA_11[20] = \<const0> ;
assign Dbg_WDATA_11[19] = \<const0> ;
assign Dbg_WDATA_11[18] = \<const0> ;
assign Dbg_WDATA_11[17] = \<const0> ;
assign Dbg_WDATA_11[16] = \<const0> ;
assign Dbg_WDATA_11[15] = \<const0> ;
assign Dbg_WDATA_11[14] = \<const0> ;
assign Dbg_WDATA_11[13] = \<const0> ;
assign Dbg_WDATA_11[12] = \<const0> ;
assign Dbg_WDATA_11[11] = \<const0> ;
assign Dbg_WDATA_11[10] = \<const0> ;
assign Dbg_WDATA_11[9] = \<const0> ;
assign Dbg_WDATA_11[8] = \<const0> ;
assign Dbg_WDATA_11[7] = \<const0> ;
assign Dbg_WDATA_11[6] = \<const0> ;
assign Dbg_WDATA_11[5] = \<const0> ;
assign Dbg_WDATA_11[4] = \<const0> ;
assign Dbg_WDATA_11[3] = \<const0> ;
assign Dbg_WDATA_11[2] = \<const0> ;
assign Dbg_WDATA_11[1] = \<const0> ;
assign Dbg_WDATA_11[0] = \<const0> ;
assign Dbg_WDATA_12[31] = \<const0> ;
assign Dbg_WDATA_12[30] = \<const0> ;
assign Dbg_WDATA_12[29] = \<const0> ;
assign Dbg_WDATA_12[28] = \<const0> ;
assign Dbg_WDATA_12[27] = \<const0> ;
assign Dbg_WDATA_12[26] = \<const0> ;
assign Dbg_WDATA_12[25] = \<const0> ;
assign Dbg_WDATA_12[24] = \<const0> ;
assign Dbg_WDATA_12[23] = \<const0> ;
assign Dbg_WDATA_12[22] = \<const0> ;
assign Dbg_WDATA_12[21] = \<const0> ;
assign Dbg_WDATA_12[20] = \<const0> ;
assign Dbg_WDATA_12[19] = \<const0> ;
assign Dbg_WDATA_12[18] = \<const0> ;
assign Dbg_WDATA_12[17] = \<const0> ;
assign Dbg_WDATA_12[16] = \<const0> ;
assign Dbg_WDATA_12[15] = \<const0> ;
assign Dbg_WDATA_12[14] = \<const0> ;
assign Dbg_WDATA_12[13] = \<const0> ;
assign Dbg_WDATA_12[12] = \<const0> ;
assign Dbg_WDATA_12[11] = \<const0> ;
assign Dbg_WDATA_12[10] = \<const0> ;
assign Dbg_WDATA_12[9] = \<const0> ;
assign Dbg_WDATA_12[8] = \<const0> ;
assign Dbg_WDATA_12[7] = \<const0> ;
assign Dbg_WDATA_12[6] = \<const0> ;
assign Dbg_WDATA_12[5] = \<const0> ;
assign Dbg_WDATA_12[4] = \<const0> ;
assign Dbg_WDATA_12[3] = \<const0> ;
assign Dbg_WDATA_12[2] = \<const0> ;
assign Dbg_WDATA_12[1] = \<const0> ;
assign Dbg_WDATA_12[0] = \<const0> ;
assign Dbg_WDATA_13[31] = \<const0> ;
assign Dbg_WDATA_13[30] = \<const0> ;
assign Dbg_WDATA_13[29] = \<const0> ;
assign Dbg_WDATA_13[28] = \<const0> ;
assign Dbg_WDATA_13[27] = \<const0> ;
assign Dbg_WDATA_13[26] = \<const0> ;
assign Dbg_WDATA_13[25] = \<const0> ;
assign Dbg_WDATA_13[24] = \<const0> ;
assign Dbg_WDATA_13[23] = \<const0> ;
assign Dbg_WDATA_13[22] = \<const0> ;
assign Dbg_WDATA_13[21] = \<const0> ;
assign Dbg_WDATA_13[20] = \<const0> ;
assign Dbg_WDATA_13[19] = \<const0> ;
assign Dbg_WDATA_13[18] = \<const0> ;
assign Dbg_WDATA_13[17] = \<const0> ;
assign Dbg_WDATA_13[16] = \<const0> ;
assign Dbg_WDATA_13[15] = \<const0> ;
assign Dbg_WDATA_13[14] = \<const0> ;
assign Dbg_WDATA_13[13] = \<const0> ;
assign Dbg_WDATA_13[12] = \<const0> ;
assign Dbg_WDATA_13[11] = \<const0> ;
assign Dbg_WDATA_13[10] = \<const0> ;
assign Dbg_WDATA_13[9] = \<const0> ;
assign Dbg_WDATA_13[8] = \<const0> ;
assign Dbg_WDATA_13[7] = \<const0> ;
assign Dbg_WDATA_13[6] = \<const0> ;
assign Dbg_WDATA_13[5] = \<const0> ;
assign Dbg_WDATA_13[4] = \<const0> ;
assign Dbg_WDATA_13[3] = \<const0> ;
assign Dbg_WDATA_13[2] = \<const0> ;
assign Dbg_WDATA_13[1] = \<const0> ;
assign Dbg_WDATA_13[0] = \<const0> ;
assign Dbg_WDATA_14[31] = \<const0> ;
assign Dbg_WDATA_14[30] = \<const0> ;
assign Dbg_WDATA_14[29] = \<const0> ;
assign Dbg_WDATA_14[28] = \<const0> ;
assign Dbg_WDATA_14[27] = \<const0> ;
assign Dbg_WDATA_14[26] = \<const0> ;
assign Dbg_WDATA_14[25] = \<const0> ;
assign Dbg_WDATA_14[24] = \<const0> ;
assign Dbg_WDATA_14[23] = \<const0> ;
assign Dbg_WDATA_14[22] = \<const0> ;
assign Dbg_WDATA_14[21] = \<const0> ;
assign Dbg_WDATA_14[20] = \<const0> ;
assign Dbg_WDATA_14[19] = \<const0> ;
assign Dbg_WDATA_14[18] = \<const0> ;
assign Dbg_WDATA_14[17] = \<const0> ;
assign Dbg_WDATA_14[16] = \<const0> ;
assign Dbg_WDATA_14[15] = \<const0> ;
assign Dbg_WDATA_14[14] = \<const0> ;
assign Dbg_WDATA_14[13] = \<const0> ;
assign Dbg_WDATA_14[12] = \<const0> ;
assign Dbg_WDATA_14[11] = \<const0> ;
assign Dbg_WDATA_14[10] = \<const0> ;
assign Dbg_WDATA_14[9] = \<const0> ;
assign Dbg_WDATA_14[8] = \<const0> ;
assign Dbg_WDATA_14[7] = \<const0> ;
assign Dbg_WDATA_14[6] = \<const0> ;
assign Dbg_WDATA_14[5] = \<const0> ;
assign Dbg_WDATA_14[4] = \<const0> ;
assign Dbg_WDATA_14[3] = \<const0> ;
assign Dbg_WDATA_14[2] = \<const0> ;
assign Dbg_WDATA_14[1] = \<const0> ;
assign Dbg_WDATA_14[0] = \<const0> ;
assign Dbg_WDATA_15[31] = \<const0> ;
assign Dbg_WDATA_15[30] = \<const0> ;
assign Dbg_WDATA_15[29] = \<const0> ;
assign Dbg_WDATA_15[28] = \<const0> ;
assign Dbg_WDATA_15[27] = \<const0> ;
assign Dbg_WDATA_15[26] = \<const0> ;
assign Dbg_WDATA_15[25] = \<const0> ;
assign Dbg_WDATA_15[24] = \<const0> ;
assign Dbg_WDATA_15[23] = \<const0> ;
assign Dbg_WDATA_15[22] = \<const0> ;
assign Dbg_WDATA_15[21] = \<const0> ;
assign Dbg_WDATA_15[20] = \<const0> ;
assign Dbg_WDATA_15[19] = \<const0> ;
assign Dbg_WDATA_15[18] = \<const0> ;
assign Dbg_WDATA_15[17] = \<const0> ;
assign Dbg_WDATA_15[16] = \<const0> ;
assign Dbg_WDATA_15[15] = \<const0> ;
assign Dbg_WDATA_15[14] = \<const0> ;
assign Dbg_WDATA_15[13] = \<const0> ;
assign Dbg_WDATA_15[12] = \<const0> ;
assign Dbg_WDATA_15[11] = \<const0> ;
assign Dbg_WDATA_15[10] = \<const0> ;
assign Dbg_WDATA_15[9] = \<const0> ;
assign Dbg_WDATA_15[8] = \<const0> ;
assign Dbg_WDATA_15[7] = \<const0> ;
assign Dbg_WDATA_15[6] = \<const0> ;
assign Dbg_WDATA_15[5] = \<const0> ;
assign Dbg_WDATA_15[4] = \<const0> ;
assign Dbg_WDATA_15[3] = \<const0> ;
assign Dbg_WDATA_15[2] = \<const0> ;
assign Dbg_WDATA_15[1] = \<const0> ;
assign Dbg_WDATA_15[0] = \<const0> ;
assign Dbg_WDATA_16[31] = \<const0> ;
assign Dbg_WDATA_16[30] = \<const0> ;
assign Dbg_WDATA_16[29] = \<const0> ;
assign Dbg_WDATA_16[28] = \<const0> ;
assign Dbg_WDATA_16[27] = \<const0> ;
assign Dbg_WDATA_16[26] = \<const0> ;
assign Dbg_WDATA_16[25] = \<const0> ;
assign Dbg_WDATA_16[24] = \<const0> ;
assign Dbg_WDATA_16[23] = \<const0> ;
assign Dbg_WDATA_16[22] = \<const0> ;
assign Dbg_WDATA_16[21] = \<const0> ;
assign Dbg_WDATA_16[20] = \<const0> ;
assign Dbg_WDATA_16[19] = \<const0> ;
assign Dbg_WDATA_16[18] = \<const0> ;
assign Dbg_WDATA_16[17] = \<const0> ;
assign Dbg_WDATA_16[16] = \<const0> ;
assign Dbg_WDATA_16[15] = \<const0> ;
assign Dbg_WDATA_16[14] = \<const0> ;
assign Dbg_WDATA_16[13] = \<const0> ;
assign Dbg_WDATA_16[12] = \<const0> ;
assign Dbg_WDATA_16[11] = \<const0> ;
assign Dbg_WDATA_16[10] = \<const0> ;
assign Dbg_WDATA_16[9] = \<const0> ;
assign Dbg_WDATA_16[8] = \<const0> ;
assign Dbg_WDATA_16[7] = \<const0> ;
assign Dbg_WDATA_16[6] = \<const0> ;
assign Dbg_WDATA_16[5] = \<const0> ;
assign Dbg_WDATA_16[4] = \<const0> ;
assign Dbg_WDATA_16[3] = \<const0> ;
assign Dbg_WDATA_16[2] = \<const0> ;
assign Dbg_WDATA_16[1] = \<const0> ;
assign Dbg_WDATA_16[0] = \<const0> ;
assign Dbg_WDATA_17[31] = \<const0> ;
assign Dbg_WDATA_17[30] = \<const0> ;
assign Dbg_WDATA_17[29] = \<const0> ;
assign Dbg_WDATA_17[28] = \<const0> ;
assign Dbg_WDATA_17[27] = \<const0> ;
assign Dbg_WDATA_17[26] = \<const0> ;
assign Dbg_WDATA_17[25] = \<const0> ;
assign Dbg_WDATA_17[24] = \<const0> ;
assign Dbg_WDATA_17[23] = \<const0> ;
assign Dbg_WDATA_17[22] = \<const0> ;
assign Dbg_WDATA_17[21] = \<const0> ;
assign Dbg_WDATA_17[20] = \<const0> ;
assign Dbg_WDATA_17[19] = \<const0> ;
assign Dbg_WDATA_17[18] = \<const0> ;
assign Dbg_WDATA_17[17] = \<const0> ;
assign Dbg_WDATA_17[16] = \<const0> ;
assign Dbg_WDATA_17[15] = \<const0> ;
assign Dbg_WDATA_17[14] = \<const0> ;
assign Dbg_WDATA_17[13] = \<const0> ;
assign Dbg_WDATA_17[12] = \<const0> ;
assign Dbg_WDATA_17[11] = \<const0> ;
assign Dbg_WDATA_17[10] = \<const0> ;
assign Dbg_WDATA_17[9] = \<const0> ;
assign Dbg_WDATA_17[8] = \<const0> ;
assign Dbg_WDATA_17[7] = \<const0> ;
assign Dbg_WDATA_17[6] = \<const0> ;
assign Dbg_WDATA_17[5] = \<const0> ;
assign Dbg_WDATA_17[4] = \<const0> ;
assign Dbg_WDATA_17[3] = \<const0> ;
assign Dbg_WDATA_17[2] = \<const0> ;
assign Dbg_WDATA_17[1] = \<const0> ;
assign Dbg_WDATA_17[0] = \<const0> ;
assign Dbg_WDATA_18[31] = \<const0> ;
assign Dbg_WDATA_18[30] = \<const0> ;
assign Dbg_WDATA_18[29] = \<const0> ;
assign Dbg_WDATA_18[28] = \<const0> ;
assign Dbg_WDATA_18[27] = \<const0> ;
assign Dbg_WDATA_18[26] = \<const0> ;
assign Dbg_WDATA_18[25] = \<const0> ;
assign Dbg_WDATA_18[24] = \<const0> ;
assign Dbg_WDATA_18[23] = \<const0> ;
assign Dbg_WDATA_18[22] = \<const0> ;
assign Dbg_WDATA_18[21] = \<const0> ;
assign Dbg_WDATA_18[20] = \<const0> ;
assign Dbg_WDATA_18[19] = \<const0> ;
assign Dbg_WDATA_18[18] = \<const0> ;
assign Dbg_WDATA_18[17] = \<const0> ;
assign Dbg_WDATA_18[16] = \<const0> ;
assign Dbg_WDATA_18[15] = \<const0> ;
assign Dbg_WDATA_18[14] = \<const0> ;
assign Dbg_WDATA_18[13] = \<const0> ;
assign Dbg_WDATA_18[12] = \<const0> ;
assign Dbg_WDATA_18[11] = \<const0> ;
assign Dbg_WDATA_18[10] = \<const0> ;
assign Dbg_WDATA_18[9] = \<const0> ;
assign Dbg_WDATA_18[8] = \<const0> ;
assign Dbg_WDATA_18[7] = \<const0> ;
assign Dbg_WDATA_18[6] = \<const0> ;
assign Dbg_WDATA_18[5] = \<const0> ;
assign Dbg_WDATA_18[4] = \<const0> ;
assign Dbg_WDATA_18[3] = \<const0> ;
assign Dbg_WDATA_18[2] = \<const0> ;
assign Dbg_WDATA_18[1] = \<const0> ;
assign Dbg_WDATA_18[0] = \<const0> ;
assign Dbg_WDATA_19[31] = \<const0> ;
assign Dbg_WDATA_19[30] = \<const0> ;
assign Dbg_WDATA_19[29] = \<const0> ;
assign Dbg_WDATA_19[28] = \<const0> ;
assign Dbg_WDATA_19[27] = \<const0> ;
assign Dbg_WDATA_19[26] = \<const0> ;
assign Dbg_WDATA_19[25] = \<const0> ;
assign Dbg_WDATA_19[24] = \<const0> ;
assign Dbg_WDATA_19[23] = \<const0> ;
assign Dbg_WDATA_19[22] = \<const0> ;
assign Dbg_WDATA_19[21] = \<const0> ;
assign Dbg_WDATA_19[20] = \<const0> ;
assign Dbg_WDATA_19[19] = \<const0> ;
assign Dbg_WDATA_19[18] = \<const0> ;
assign Dbg_WDATA_19[17] = \<const0> ;
assign Dbg_WDATA_19[16] = \<const0> ;
assign Dbg_WDATA_19[15] = \<const0> ;
assign Dbg_WDATA_19[14] = \<const0> ;
assign Dbg_WDATA_19[13] = \<const0> ;
assign Dbg_WDATA_19[12] = \<const0> ;
assign Dbg_WDATA_19[11] = \<const0> ;
assign Dbg_WDATA_19[10] = \<const0> ;
assign Dbg_WDATA_19[9] = \<const0> ;
assign Dbg_WDATA_19[8] = \<const0> ;
assign Dbg_WDATA_19[7] = \<const0> ;
assign Dbg_WDATA_19[6] = \<const0> ;
assign Dbg_WDATA_19[5] = \<const0> ;
assign Dbg_WDATA_19[4] = \<const0> ;
assign Dbg_WDATA_19[3] = \<const0> ;
assign Dbg_WDATA_19[2] = \<const0> ;
assign Dbg_WDATA_19[1] = \<const0> ;
assign Dbg_WDATA_19[0] = \<const0> ;
assign Dbg_WDATA_2[31] = \<const0> ;
assign Dbg_WDATA_2[30] = \<const0> ;
assign Dbg_WDATA_2[29] = \<const0> ;
assign Dbg_WDATA_2[28] = \<const0> ;
assign Dbg_WDATA_2[27] = \<const0> ;
assign Dbg_WDATA_2[26] = \<const0> ;
assign Dbg_WDATA_2[25] = \<const0> ;
assign Dbg_WDATA_2[24] = \<const0> ;
assign Dbg_WDATA_2[23] = \<const0> ;
assign Dbg_WDATA_2[22] = \<const0> ;
assign Dbg_WDATA_2[21] = \<const0> ;
assign Dbg_WDATA_2[20] = \<const0> ;
assign Dbg_WDATA_2[19] = \<const0> ;
assign Dbg_WDATA_2[18] = \<const0> ;
assign Dbg_WDATA_2[17] = \<const0> ;
assign Dbg_WDATA_2[16] = \<const0> ;
assign Dbg_WDATA_2[15] = \<const0> ;
assign Dbg_WDATA_2[14] = \<const0> ;
assign Dbg_WDATA_2[13] = \<const0> ;
assign Dbg_WDATA_2[12] = \<const0> ;
assign Dbg_WDATA_2[11] = \<const0> ;
assign Dbg_WDATA_2[10] = \<const0> ;
assign Dbg_WDATA_2[9] = \<const0> ;
assign Dbg_WDATA_2[8] = \<const0> ;
assign Dbg_WDATA_2[7] = \<const0> ;
assign Dbg_WDATA_2[6] = \<const0> ;
assign Dbg_WDATA_2[5] = \<const0> ;
assign Dbg_WDATA_2[4] = \<const0> ;
assign Dbg_WDATA_2[3] = \<const0> ;
assign Dbg_WDATA_2[2] = \<const0> ;
assign Dbg_WDATA_2[1] = \<const0> ;
assign Dbg_WDATA_2[0] = \<const0> ;
assign Dbg_WDATA_20[31] = \<const0> ;
assign Dbg_WDATA_20[30] = \<const0> ;
assign Dbg_WDATA_20[29] = \<const0> ;
assign Dbg_WDATA_20[28] = \<const0> ;
assign Dbg_WDATA_20[27] = \<const0> ;
assign Dbg_WDATA_20[26] = \<const0> ;
assign Dbg_WDATA_20[25] = \<const0> ;
assign Dbg_WDATA_20[24] = \<const0> ;
assign Dbg_WDATA_20[23] = \<const0> ;
assign Dbg_WDATA_20[22] = \<const0> ;
assign Dbg_WDATA_20[21] = \<const0> ;
assign Dbg_WDATA_20[20] = \<const0> ;
assign Dbg_WDATA_20[19] = \<const0> ;
assign Dbg_WDATA_20[18] = \<const0> ;
assign Dbg_WDATA_20[17] = \<const0> ;
assign Dbg_WDATA_20[16] = \<const0> ;
assign Dbg_WDATA_20[15] = \<const0> ;
assign Dbg_WDATA_20[14] = \<const0> ;
assign Dbg_WDATA_20[13] = \<const0> ;
assign Dbg_WDATA_20[12] = \<const0> ;
assign Dbg_WDATA_20[11] = \<const0> ;
assign Dbg_WDATA_20[10] = \<const0> ;
assign Dbg_WDATA_20[9] = \<const0> ;
assign Dbg_WDATA_20[8] = \<const0> ;
assign Dbg_WDATA_20[7] = \<const0> ;
assign Dbg_WDATA_20[6] = \<const0> ;
assign Dbg_WDATA_20[5] = \<const0> ;
assign Dbg_WDATA_20[4] = \<const0> ;
assign Dbg_WDATA_20[3] = \<const0> ;
assign Dbg_WDATA_20[2] = \<const0> ;
assign Dbg_WDATA_20[1] = \<const0> ;
assign Dbg_WDATA_20[0] = \<const0> ;
assign Dbg_WDATA_21[31] = \<const0> ;
assign Dbg_WDATA_21[30] = \<const0> ;
assign Dbg_WDATA_21[29] = \<const0> ;
assign Dbg_WDATA_21[28] = \<const0> ;
assign Dbg_WDATA_21[27] = \<const0> ;
assign Dbg_WDATA_21[26] = \<const0> ;
assign Dbg_WDATA_21[25] = \<const0> ;
assign Dbg_WDATA_21[24] = \<const0> ;
assign Dbg_WDATA_21[23] = \<const0> ;
assign Dbg_WDATA_21[22] = \<const0> ;
assign Dbg_WDATA_21[21] = \<const0> ;
assign Dbg_WDATA_21[20] = \<const0> ;
assign Dbg_WDATA_21[19] = \<const0> ;
assign Dbg_WDATA_21[18] = \<const0> ;
assign Dbg_WDATA_21[17] = \<const0> ;
assign Dbg_WDATA_21[16] = \<const0> ;
assign Dbg_WDATA_21[15] = \<const0> ;
assign Dbg_WDATA_21[14] = \<const0> ;
assign Dbg_WDATA_21[13] = \<const0> ;
assign Dbg_WDATA_21[12] = \<const0> ;
assign Dbg_WDATA_21[11] = \<const0> ;
assign Dbg_WDATA_21[10] = \<const0> ;
assign Dbg_WDATA_21[9] = \<const0> ;
assign Dbg_WDATA_21[8] = \<const0> ;
assign Dbg_WDATA_21[7] = \<const0> ;
assign Dbg_WDATA_21[6] = \<const0> ;
assign Dbg_WDATA_21[5] = \<const0> ;
assign Dbg_WDATA_21[4] = \<const0> ;
assign Dbg_WDATA_21[3] = \<const0> ;
assign Dbg_WDATA_21[2] = \<const0> ;
assign Dbg_WDATA_21[1] = \<const0> ;
assign Dbg_WDATA_21[0] = \<const0> ;
assign Dbg_WDATA_22[31] = \<const0> ;
assign Dbg_WDATA_22[30] = \<const0> ;
assign Dbg_WDATA_22[29] = \<const0> ;
assign Dbg_WDATA_22[28] = \<const0> ;
assign Dbg_WDATA_22[27] = \<const0> ;
assign Dbg_WDATA_22[26] = \<const0> ;
assign Dbg_WDATA_22[25] = \<const0> ;
assign Dbg_WDATA_22[24] = \<const0> ;
assign Dbg_WDATA_22[23] = \<const0> ;
assign Dbg_WDATA_22[22] = \<const0> ;
assign Dbg_WDATA_22[21] = \<const0> ;
assign Dbg_WDATA_22[20] = \<const0> ;
assign Dbg_WDATA_22[19] = \<const0> ;
assign Dbg_WDATA_22[18] = \<const0> ;
assign Dbg_WDATA_22[17] = \<const0> ;
assign Dbg_WDATA_22[16] = \<const0> ;
assign Dbg_WDATA_22[15] = \<const0> ;
assign Dbg_WDATA_22[14] = \<const0> ;
assign Dbg_WDATA_22[13] = \<const0> ;
assign Dbg_WDATA_22[12] = \<const0> ;
assign Dbg_WDATA_22[11] = \<const0> ;
assign Dbg_WDATA_22[10] = \<const0> ;
assign Dbg_WDATA_22[9] = \<const0> ;
assign Dbg_WDATA_22[8] = \<const0> ;
assign Dbg_WDATA_22[7] = \<const0> ;
assign Dbg_WDATA_22[6] = \<const0> ;
assign Dbg_WDATA_22[5] = \<const0> ;
assign Dbg_WDATA_22[4] = \<const0> ;
assign Dbg_WDATA_22[3] = \<const0> ;
assign Dbg_WDATA_22[2] = \<const0> ;
assign Dbg_WDATA_22[1] = \<const0> ;
assign Dbg_WDATA_22[0] = \<const0> ;
assign Dbg_WDATA_23[31] = \<const0> ;
assign Dbg_WDATA_23[30] = \<const0> ;
assign Dbg_WDATA_23[29] = \<const0> ;
assign Dbg_WDATA_23[28] = \<const0> ;
assign Dbg_WDATA_23[27] = \<const0> ;
assign Dbg_WDATA_23[26] = \<const0> ;
assign Dbg_WDATA_23[25] = \<const0> ;
assign Dbg_WDATA_23[24] = \<const0> ;
assign Dbg_WDATA_23[23] = \<const0> ;
assign Dbg_WDATA_23[22] = \<const0> ;
assign Dbg_WDATA_23[21] = \<const0> ;
assign Dbg_WDATA_23[20] = \<const0> ;
assign Dbg_WDATA_23[19] = \<const0> ;
assign Dbg_WDATA_23[18] = \<const0> ;
assign Dbg_WDATA_23[17] = \<const0> ;
assign Dbg_WDATA_23[16] = \<const0> ;
assign Dbg_WDATA_23[15] = \<const0> ;
assign Dbg_WDATA_23[14] = \<const0> ;
assign Dbg_WDATA_23[13] = \<const0> ;
assign Dbg_WDATA_23[12] = \<const0> ;
assign Dbg_WDATA_23[11] = \<const0> ;
assign Dbg_WDATA_23[10] = \<const0> ;
assign Dbg_WDATA_23[9] = \<const0> ;
assign Dbg_WDATA_23[8] = \<const0> ;
assign Dbg_WDATA_23[7] = \<const0> ;
assign Dbg_WDATA_23[6] = \<const0> ;
assign Dbg_WDATA_23[5] = \<const0> ;
assign Dbg_WDATA_23[4] = \<const0> ;
assign Dbg_WDATA_23[3] = \<const0> ;
assign Dbg_WDATA_23[2] = \<const0> ;
assign Dbg_WDATA_23[1] = \<const0> ;
assign Dbg_WDATA_23[0] = \<const0> ;
assign Dbg_WDATA_24[31] = \<const0> ;
assign Dbg_WDATA_24[30] = \<const0> ;
assign Dbg_WDATA_24[29] = \<const0> ;
assign Dbg_WDATA_24[28] = \<const0> ;
assign Dbg_WDATA_24[27] = \<const0> ;
assign Dbg_WDATA_24[26] = \<const0> ;
assign Dbg_WDATA_24[25] = \<const0> ;
assign Dbg_WDATA_24[24] = \<const0> ;
assign Dbg_WDATA_24[23] = \<const0> ;
assign Dbg_WDATA_24[22] = \<const0> ;
assign Dbg_WDATA_24[21] = \<const0> ;
assign Dbg_WDATA_24[20] = \<const0> ;
assign Dbg_WDATA_24[19] = \<const0> ;
assign Dbg_WDATA_24[18] = \<const0> ;
assign Dbg_WDATA_24[17] = \<const0> ;
assign Dbg_WDATA_24[16] = \<const0> ;
assign Dbg_WDATA_24[15] = \<const0> ;
assign Dbg_WDATA_24[14] = \<const0> ;
assign Dbg_WDATA_24[13] = \<const0> ;
assign Dbg_WDATA_24[12] = \<const0> ;
assign Dbg_WDATA_24[11] = \<const0> ;
assign Dbg_WDATA_24[10] = \<const0> ;
assign Dbg_WDATA_24[9] = \<const0> ;
assign Dbg_WDATA_24[8] = \<const0> ;
assign Dbg_WDATA_24[7] = \<const0> ;
assign Dbg_WDATA_24[6] = \<const0> ;
assign Dbg_WDATA_24[5] = \<const0> ;
assign Dbg_WDATA_24[4] = \<const0> ;
assign Dbg_WDATA_24[3] = \<const0> ;
assign Dbg_WDATA_24[2] = \<const0> ;
assign Dbg_WDATA_24[1] = \<const0> ;
assign Dbg_WDATA_24[0] = \<const0> ;
assign Dbg_WDATA_25[31] = \<const0> ;
assign Dbg_WDATA_25[30] = \<const0> ;
assign Dbg_WDATA_25[29] = \<const0> ;
assign Dbg_WDATA_25[28] = \<const0> ;
assign Dbg_WDATA_25[27] = \<const0> ;
assign Dbg_WDATA_25[26] = \<const0> ;
assign Dbg_WDATA_25[25] = \<const0> ;
assign Dbg_WDATA_25[24] = \<const0> ;
assign Dbg_WDATA_25[23] = \<const0> ;
assign Dbg_WDATA_25[22] = \<const0> ;
assign Dbg_WDATA_25[21] = \<const0> ;
assign Dbg_WDATA_25[20] = \<const0> ;
assign Dbg_WDATA_25[19] = \<const0> ;
assign Dbg_WDATA_25[18] = \<const0> ;
assign Dbg_WDATA_25[17] = \<const0> ;
assign Dbg_WDATA_25[16] = \<const0> ;
assign Dbg_WDATA_25[15] = \<const0> ;
assign Dbg_WDATA_25[14] = \<const0> ;
assign Dbg_WDATA_25[13] = \<const0> ;
assign Dbg_WDATA_25[12] = \<const0> ;
assign Dbg_WDATA_25[11] = \<const0> ;
assign Dbg_WDATA_25[10] = \<const0> ;
assign Dbg_WDATA_25[9] = \<const0> ;
assign Dbg_WDATA_25[8] = \<const0> ;
assign Dbg_WDATA_25[7] = \<const0> ;
assign Dbg_WDATA_25[6] = \<const0> ;
assign Dbg_WDATA_25[5] = \<const0> ;
assign Dbg_WDATA_25[4] = \<const0> ;
assign Dbg_WDATA_25[3] = \<const0> ;
assign Dbg_WDATA_25[2] = \<const0> ;
assign Dbg_WDATA_25[1] = \<const0> ;
assign Dbg_WDATA_25[0] = \<const0> ;
assign Dbg_WDATA_26[31] = \<const0> ;
assign Dbg_WDATA_26[30] = \<const0> ;
assign Dbg_WDATA_26[29] = \<const0> ;
assign Dbg_WDATA_26[28] = \<const0> ;
assign Dbg_WDATA_26[27] = \<const0> ;
assign Dbg_WDATA_26[26] = \<const0> ;
assign Dbg_WDATA_26[25] = \<const0> ;
assign Dbg_WDATA_26[24] = \<const0> ;
assign Dbg_WDATA_26[23] = \<const0> ;
assign Dbg_WDATA_26[22] = \<const0> ;
assign Dbg_WDATA_26[21] = \<const0> ;
assign Dbg_WDATA_26[20] = \<const0> ;
assign Dbg_WDATA_26[19] = \<const0> ;
assign Dbg_WDATA_26[18] = \<const0> ;
assign Dbg_WDATA_26[17] = \<const0> ;
assign Dbg_WDATA_26[16] = \<const0> ;
assign Dbg_WDATA_26[15] = \<const0> ;
assign Dbg_WDATA_26[14] = \<const0> ;
assign Dbg_WDATA_26[13] = \<const0> ;
assign Dbg_WDATA_26[12] = \<const0> ;
assign Dbg_WDATA_26[11] = \<const0> ;
assign Dbg_WDATA_26[10] = \<const0> ;
assign Dbg_WDATA_26[9] = \<const0> ;
assign Dbg_WDATA_26[8] = \<const0> ;
assign Dbg_WDATA_26[7] = \<const0> ;
assign Dbg_WDATA_26[6] = \<const0> ;
assign Dbg_WDATA_26[5] = \<const0> ;
assign Dbg_WDATA_26[4] = \<const0> ;
assign Dbg_WDATA_26[3] = \<const0> ;
assign Dbg_WDATA_26[2] = \<const0> ;
assign Dbg_WDATA_26[1] = \<const0> ;
assign Dbg_WDATA_26[0] = \<const0> ;
assign Dbg_WDATA_27[31] = \<const0> ;
assign Dbg_WDATA_27[30] = \<const0> ;
assign Dbg_WDATA_27[29] = \<const0> ;
assign Dbg_WDATA_27[28] = \<const0> ;
assign Dbg_WDATA_27[27] = \<const0> ;
assign Dbg_WDATA_27[26] = \<const0> ;
assign Dbg_WDATA_27[25] = \<const0> ;
assign Dbg_WDATA_27[24] = \<const0> ;
assign Dbg_WDATA_27[23] = \<const0> ;
assign Dbg_WDATA_27[22] = \<const0> ;
assign Dbg_WDATA_27[21] = \<const0> ;
assign Dbg_WDATA_27[20] = \<const0> ;
assign Dbg_WDATA_27[19] = \<const0> ;
assign Dbg_WDATA_27[18] = \<const0> ;
assign Dbg_WDATA_27[17] = \<const0> ;
assign Dbg_WDATA_27[16] = \<const0> ;
assign Dbg_WDATA_27[15] = \<const0> ;
assign Dbg_WDATA_27[14] = \<const0> ;
assign Dbg_WDATA_27[13] = \<const0> ;
assign Dbg_WDATA_27[12] = \<const0> ;
assign Dbg_WDATA_27[11] = \<const0> ;
assign Dbg_WDATA_27[10] = \<const0> ;
assign Dbg_WDATA_27[9] = \<const0> ;
assign Dbg_WDATA_27[8] = \<const0> ;
assign Dbg_WDATA_27[7] = \<const0> ;
assign Dbg_WDATA_27[6] = \<const0> ;
assign Dbg_WDATA_27[5] = \<const0> ;
assign Dbg_WDATA_27[4] = \<const0> ;
assign Dbg_WDATA_27[3] = \<const0> ;
assign Dbg_WDATA_27[2] = \<const0> ;
assign Dbg_WDATA_27[1] = \<const0> ;
assign Dbg_WDATA_27[0] = \<const0> ;
assign Dbg_WDATA_28[31] = \<const0> ;
assign Dbg_WDATA_28[30] = \<const0> ;
assign Dbg_WDATA_28[29] = \<const0> ;
assign Dbg_WDATA_28[28] = \<const0> ;
assign Dbg_WDATA_28[27] = \<const0> ;
assign Dbg_WDATA_28[26] = \<const0> ;
assign Dbg_WDATA_28[25] = \<const0> ;
assign Dbg_WDATA_28[24] = \<const0> ;
assign Dbg_WDATA_28[23] = \<const0> ;
assign Dbg_WDATA_28[22] = \<const0> ;
assign Dbg_WDATA_28[21] = \<const0> ;
assign Dbg_WDATA_28[20] = \<const0> ;
assign Dbg_WDATA_28[19] = \<const0> ;
assign Dbg_WDATA_28[18] = \<const0> ;
assign Dbg_WDATA_28[17] = \<const0> ;
assign Dbg_WDATA_28[16] = \<const0> ;
assign Dbg_WDATA_28[15] = \<const0> ;
assign Dbg_WDATA_28[14] = \<const0> ;
assign Dbg_WDATA_28[13] = \<const0> ;
assign Dbg_WDATA_28[12] = \<const0> ;
assign Dbg_WDATA_28[11] = \<const0> ;
assign Dbg_WDATA_28[10] = \<const0> ;
assign Dbg_WDATA_28[9] = \<const0> ;
assign Dbg_WDATA_28[8] = \<const0> ;
assign Dbg_WDATA_28[7] = \<const0> ;
assign Dbg_WDATA_28[6] = \<const0> ;
assign Dbg_WDATA_28[5] = \<const0> ;
assign Dbg_WDATA_28[4] = \<const0> ;
assign Dbg_WDATA_28[3] = \<const0> ;
assign Dbg_WDATA_28[2] = \<const0> ;
assign Dbg_WDATA_28[1] = \<const0> ;
assign Dbg_WDATA_28[0] = \<const0> ;
assign Dbg_WDATA_29[31] = \<const0> ;
assign Dbg_WDATA_29[30] = \<const0> ;
assign Dbg_WDATA_29[29] = \<const0> ;
assign Dbg_WDATA_29[28] = \<const0> ;
assign Dbg_WDATA_29[27] = \<const0> ;
assign Dbg_WDATA_29[26] = \<const0> ;
assign Dbg_WDATA_29[25] = \<const0> ;
assign Dbg_WDATA_29[24] = \<const0> ;
assign Dbg_WDATA_29[23] = \<const0> ;
assign Dbg_WDATA_29[22] = \<const0> ;
assign Dbg_WDATA_29[21] = \<const0> ;
assign Dbg_WDATA_29[20] = \<const0> ;
assign Dbg_WDATA_29[19] = \<const0> ;
assign Dbg_WDATA_29[18] = \<const0> ;
assign Dbg_WDATA_29[17] = \<const0> ;
assign Dbg_WDATA_29[16] = \<const0> ;
assign Dbg_WDATA_29[15] = \<const0> ;
assign Dbg_WDATA_29[14] = \<const0> ;
assign Dbg_WDATA_29[13] = \<const0> ;
assign Dbg_WDATA_29[12] = \<const0> ;
assign Dbg_WDATA_29[11] = \<const0> ;
assign Dbg_WDATA_29[10] = \<const0> ;
assign Dbg_WDATA_29[9] = \<const0> ;
assign Dbg_WDATA_29[8] = \<const0> ;
assign Dbg_WDATA_29[7] = \<const0> ;
assign Dbg_WDATA_29[6] = \<const0> ;
assign Dbg_WDATA_29[5] = \<const0> ;
assign Dbg_WDATA_29[4] = \<const0> ;
assign Dbg_WDATA_29[3] = \<const0> ;
assign Dbg_WDATA_29[2] = \<const0> ;
assign Dbg_WDATA_29[1] = \<const0> ;
assign Dbg_WDATA_29[0] = \<const0> ;
assign Dbg_WDATA_3[31] = \<const0> ;
assign Dbg_WDATA_3[30] = \<const0> ;
assign Dbg_WDATA_3[29] = \<const0> ;
assign Dbg_WDATA_3[28] = \<const0> ;
assign Dbg_WDATA_3[27] = \<const0> ;
assign Dbg_WDATA_3[26] = \<const0> ;
assign Dbg_WDATA_3[25] = \<const0> ;
assign Dbg_WDATA_3[24] = \<const0> ;
assign Dbg_WDATA_3[23] = \<const0> ;
assign Dbg_WDATA_3[22] = \<const0> ;
assign Dbg_WDATA_3[21] = \<const0> ;
assign Dbg_WDATA_3[20] = \<const0> ;
assign Dbg_WDATA_3[19] = \<const0> ;
assign Dbg_WDATA_3[18] = \<const0> ;
assign Dbg_WDATA_3[17] = \<const0> ;
assign Dbg_WDATA_3[16] = \<const0> ;
assign Dbg_WDATA_3[15] = \<const0> ;
assign Dbg_WDATA_3[14] = \<const0> ;
assign Dbg_WDATA_3[13] = \<const0> ;
assign Dbg_WDATA_3[12] = \<const0> ;
assign Dbg_WDATA_3[11] = \<const0> ;
assign Dbg_WDATA_3[10] = \<const0> ;
assign Dbg_WDATA_3[9] = \<const0> ;
assign Dbg_WDATA_3[8] = \<const0> ;
assign Dbg_WDATA_3[7] = \<const0> ;
assign Dbg_WDATA_3[6] = \<const0> ;
assign Dbg_WDATA_3[5] = \<const0> ;
assign Dbg_WDATA_3[4] = \<const0> ;
assign Dbg_WDATA_3[3] = \<const0> ;
assign Dbg_WDATA_3[2] = \<const0> ;
assign Dbg_WDATA_3[1] = \<const0> ;
assign Dbg_WDATA_3[0] = \<const0> ;
assign Dbg_WDATA_30[31] = \<const0> ;
assign Dbg_WDATA_30[30] = \<const0> ;
assign Dbg_WDATA_30[29] = \<const0> ;
assign Dbg_WDATA_30[28] = \<const0> ;
assign Dbg_WDATA_30[27] = \<const0> ;
assign Dbg_WDATA_30[26] = \<const0> ;
assign Dbg_WDATA_30[25] = \<const0> ;
assign Dbg_WDATA_30[24] = \<const0> ;
assign Dbg_WDATA_30[23] = \<const0> ;
assign Dbg_WDATA_30[22] = \<const0> ;
assign Dbg_WDATA_30[21] = \<const0> ;
assign Dbg_WDATA_30[20] = \<const0> ;
assign Dbg_WDATA_30[19] = \<const0> ;
assign Dbg_WDATA_30[18] = \<const0> ;
assign Dbg_WDATA_30[17] = \<const0> ;
assign Dbg_WDATA_30[16] = \<const0> ;
assign Dbg_WDATA_30[15] = \<const0> ;
assign Dbg_WDATA_30[14] = \<const0> ;
assign Dbg_WDATA_30[13] = \<const0> ;
assign Dbg_WDATA_30[12] = \<const0> ;
assign Dbg_WDATA_30[11] = \<const0> ;
assign Dbg_WDATA_30[10] = \<const0> ;
assign Dbg_WDATA_30[9] = \<const0> ;
assign Dbg_WDATA_30[8] = \<const0> ;
assign Dbg_WDATA_30[7] = \<const0> ;
assign Dbg_WDATA_30[6] = \<const0> ;
assign Dbg_WDATA_30[5] = \<const0> ;
assign Dbg_WDATA_30[4] = \<const0> ;
assign Dbg_WDATA_30[3] = \<const0> ;
assign Dbg_WDATA_30[2] = \<const0> ;
assign Dbg_WDATA_30[1] = \<const0> ;
assign Dbg_WDATA_30[0] = \<const0> ;
assign Dbg_WDATA_31[31] = \<const0> ;
assign Dbg_WDATA_31[30] = \<const0> ;
assign Dbg_WDATA_31[29] = \<const0> ;
assign Dbg_WDATA_31[28] = \<const0> ;
assign Dbg_WDATA_31[27] = \<const0> ;
assign Dbg_WDATA_31[26] = \<const0> ;
assign Dbg_WDATA_31[25] = \<const0> ;
assign Dbg_WDATA_31[24] = \<const0> ;
assign Dbg_WDATA_31[23] = \<const0> ;
assign Dbg_WDATA_31[22] = \<const0> ;
assign Dbg_WDATA_31[21] = \<const0> ;
assign Dbg_WDATA_31[20] = \<const0> ;
assign Dbg_WDATA_31[19] = \<const0> ;
assign Dbg_WDATA_31[18] = \<const0> ;
assign Dbg_WDATA_31[17] = \<const0> ;
assign Dbg_WDATA_31[16] = \<const0> ;
assign Dbg_WDATA_31[15] = \<const0> ;
assign Dbg_WDATA_31[14] = \<const0> ;
assign Dbg_WDATA_31[13] = \<const0> ;
assign Dbg_WDATA_31[12] = \<const0> ;
assign Dbg_WDATA_31[11] = \<const0> ;
assign Dbg_WDATA_31[10] = \<const0> ;
assign Dbg_WDATA_31[9] = \<const0> ;
assign Dbg_WDATA_31[8] = \<const0> ;
assign Dbg_WDATA_31[7] = \<const0> ;
assign Dbg_WDATA_31[6] = \<const0> ;
assign Dbg_WDATA_31[5] = \<const0> ;
assign Dbg_WDATA_31[4] = \<const0> ;
assign Dbg_WDATA_31[3] = \<const0> ;
assign Dbg_WDATA_31[2] = \<const0> ;
assign Dbg_WDATA_31[1] = \<const0> ;
assign Dbg_WDATA_31[0] = \<const0> ;
assign Dbg_WDATA_4[31] = \<const0> ;
assign Dbg_WDATA_4[30] = \<const0> ;
assign Dbg_WDATA_4[29] = \<const0> ;
assign Dbg_WDATA_4[28] = \<const0> ;
assign Dbg_WDATA_4[27] = \<const0> ;
assign Dbg_WDATA_4[26] = \<const0> ;
assign Dbg_WDATA_4[25] = \<const0> ;
assign Dbg_WDATA_4[24] = \<const0> ;
assign Dbg_WDATA_4[23] = \<const0> ;
assign Dbg_WDATA_4[22] = \<const0> ;
assign Dbg_WDATA_4[21] = \<const0> ;
assign Dbg_WDATA_4[20] = \<const0> ;
assign Dbg_WDATA_4[19] = \<const0> ;
assign Dbg_WDATA_4[18] = \<const0> ;
assign Dbg_WDATA_4[17] = \<const0> ;
assign Dbg_WDATA_4[16] = \<const0> ;
assign Dbg_WDATA_4[15] = \<const0> ;
assign Dbg_WDATA_4[14] = \<const0> ;
assign Dbg_WDATA_4[13] = \<const0> ;
assign Dbg_WDATA_4[12] = \<const0> ;
assign Dbg_WDATA_4[11] = \<const0> ;
assign Dbg_WDATA_4[10] = \<const0> ;
assign Dbg_WDATA_4[9] = \<const0> ;
assign Dbg_WDATA_4[8] = \<const0> ;
assign Dbg_WDATA_4[7] = \<const0> ;
assign Dbg_WDATA_4[6] = \<const0> ;
assign Dbg_WDATA_4[5] = \<const0> ;
assign Dbg_WDATA_4[4] = \<const0> ;
assign Dbg_WDATA_4[3] = \<const0> ;
assign Dbg_WDATA_4[2] = \<const0> ;
assign Dbg_WDATA_4[1] = \<const0> ;
assign Dbg_WDATA_4[0] = \<const0> ;
assign Dbg_WDATA_5[31] = \<const0> ;
assign Dbg_WDATA_5[30] = \<const0> ;
assign Dbg_WDATA_5[29] = \<const0> ;
assign Dbg_WDATA_5[28] = \<const0> ;
assign Dbg_WDATA_5[27] = \<const0> ;
assign Dbg_WDATA_5[26] = \<const0> ;
assign Dbg_WDATA_5[25] = \<const0> ;
assign Dbg_WDATA_5[24] = \<const0> ;
assign Dbg_WDATA_5[23] = \<const0> ;
assign Dbg_WDATA_5[22] = \<const0> ;
assign Dbg_WDATA_5[21] = \<const0> ;
assign Dbg_WDATA_5[20] = \<const0> ;
assign Dbg_WDATA_5[19] = \<const0> ;
assign Dbg_WDATA_5[18] = \<const0> ;
assign Dbg_WDATA_5[17] = \<const0> ;
assign Dbg_WDATA_5[16] = \<const0> ;
assign Dbg_WDATA_5[15] = \<const0> ;
assign Dbg_WDATA_5[14] = \<const0> ;
assign Dbg_WDATA_5[13] = \<const0> ;
assign Dbg_WDATA_5[12] = \<const0> ;
assign Dbg_WDATA_5[11] = \<const0> ;
assign Dbg_WDATA_5[10] = \<const0> ;
assign Dbg_WDATA_5[9] = \<const0> ;
assign Dbg_WDATA_5[8] = \<const0> ;
assign Dbg_WDATA_5[7] = \<const0> ;
assign Dbg_WDATA_5[6] = \<const0> ;
assign Dbg_WDATA_5[5] = \<const0> ;
assign Dbg_WDATA_5[4] = \<const0> ;
assign Dbg_WDATA_5[3] = \<const0> ;
assign Dbg_WDATA_5[2] = \<const0> ;
assign Dbg_WDATA_5[1] = \<const0> ;
assign Dbg_WDATA_5[0] = \<const0> ;
assign Dbg_WDATA_6[31] = \<const0> ;
assign Dbg_WDATA_6[30] = \<const0> ;
assign Dbg_WDATA_6[29] = \<const0> ;
assign Dbg_WDATA_6[28] = \<const0> ;
assign Dbg_WDATA_6[27] = \<const0> ;
assign Dbg_WDATA_6[26] = \<const0> ;
assign Dbg_WDATA_6[25] = \<const0> ;
assign Dbg_WDATA_6[24] = \<const0> ;
assign Dbg_WDATA_6[23] = \<const0> ;
assign Dbg_WDATA_6[22] = \<const0> ;
assign Dbg_WDATA_6[21] = \<const0> ;
assign Dbg_WDATA_6[20] = \<const0> ;
assign Dbg_WDATA_6[19] = \<const0> ;
assign Dbg_WDATA_6[18] = \<const0> ;
assign Dbg_WDATA_6[17] = \<const0> ;
assign Dbg_WDATA_6[16] = \<const0> ;
assign Dbg_WDATA_6[15] = \<const0> ;
assign Dbg_WDATA_6[14] = \<const0> ;
assign Dbg_WDATA_6[13] = \<const0> ;
assign Dbg_WDATA_6[12] = \<const0> ;
assign Dbg_WDATA_6[11] = \<const0> ;
assign Dbg_WDATA_6[10] = \<const0> ;
assign Dbg_WDATA_6[9] = \<const0> ;
assign Dbg_WDATA_6[8] = \<const0> ;
assign Dbg_WDATA_6[7] = \<const0> ;
assign Dbg_WDATA_6[6] = \<const0> ;
assign Dbg_WDATA_6[5] = \<const0> ;
assign Dbg_WDATA_6[4] = \<const0> ;
assign Dbg_WDATA_6[3] = \<const0> ;
assign Dbg_WDATA_6[2] = \<const0> ;
assign Dbg_WDATA_6[1] = \<const0> ;
assign Dbg_WDATA_6[0] = \<const0> ;
assign Dbg_WDATA_7[31] = \<const0> ;
assign Dbg_WDATA_7[30] = \<const0> ;
assign Dbg_WDATA_7[29] = \<const0> ;
assign Dbg_WDATA_7[28] = \<const0> ;
assign Dbg_WDATA_7[27] = \<const0> ;
assign Dbg_WDATA_7[26] = \<const0> ;
assign Dbg_WDATA_7[25] = \<const0> ;
assign Dbg_WDATA_7[24] = \<const0> ;
assign Dbg_WDATA_7[23] = \<const0> ;
assign Dbg_WDATA_7[22] = \<const0> ;
assign Dbg_WDATA_7[21] = \<const0> ;
assign Dbg_WDATA_7[20] = \<const0> ;
assign Dbg_WDATA_7[19] = \<const0> ;
assign Dbg_WDATA_7[18] = \<const0> ;
assign Dbg_WDATA_7[17] = \<const0> ;
assign Dbg_WDATA_7[16] = \<const0> ;
assign Dbg_WDATA_7[15] = \<const0> ;
assign Dbg_WDATA_7[14] = \<const0> ;
assign Dbg_WDATA_7[13] = \<const0> ;
assign Dbg_WDATA_7[12] = \<const0> ;
assign Dbg_WDATA_7[11] = \<const0> ;
assign Dbg_WDATA_7[10] = \<const0> ;
assign Dbg_WDATA_7[9] = \<const0> ;
assign Dbg_WDATA_7[8] = \<const0> ;
assign Dbg_WDATA_7[7] = \<const0> ;
assign Dbg_WDATA_7[6] = \<const0> ;
assign Dbg_WDATA_7[5] = \<const0> ;
assign Dbg_WDATA_7[4] = \<const0> ;
assign Dbg_WDATA_7[3] = \<const0> ;
assign Dbg_WDATA_7[2] = \<const0> ;
assign Dbg_WDATA_7[1] = \<const0> ;
assign Dbg_WDATA_7[0] = \<const0> ;
assign Dbg_WDATA_8[31] = \<const0> ;
assign Dbg_WDATA_8[30] = \<const0> ;
assign Dbg_WDATA_8[29] = \<const0> ;
assign Dbg_WDATA_8[28] = \<const0> ;
assign Dbg_WDATA_8[27] = \<const0> ;
assign Dbg_WDATA_8[26] = \<const0> ;
assign Dbg_WDATA_8[25] = \<const0> ;
assign Dbg_WDATA_8[24] = \<const0> ;
assign Dbg_WDATA_8[23] = \<const0> ;
assign Dbg_WDATA_8[22] = \<const0> ;
assign Dbg_WDATA_8[21] = \<const0> ;
assign Dbg_WDATA_8[20] = \<const0> ;
assign Dbg_WDATA_8[19] = \<const0> ;
assign Dbg_WDATA_8[18] = \<const0> ;
assign Dbg_WDATA_8[17] = \<const0> ;
assign Dbg_WDATA_8[16] = \<const0> ;
assign Dbg_WDATA_8[15] = \<const0> ;
assign Dbg_WDATA_8[14] = \<const0> ;
assign Dbg_WDATA_8[13] = \<const0> ;
assign Dbg_WDATA_8[12] = \<const0> ;
assign Dbg_WDATA_8[11] = \<const0> ;
assign Dbg_WDATA_8[10] = \<const0> ;
assign Dbg_WDATA_8[9] = \<const0> ;
assign Dbg_WDATA_8[8] = \<const0> ;
assign Dbg_WDATA_8[7] = \<const0> ;
assign Dbg_WDATA_8[6] = \<const0> ;
assign Dbg_WDATA_8[5] = \<const0> ;
assign Dbg_WDATA_8[4] = \<const0> ;
assign Dbg_WDATA_8[3] = \<const0> ;
assign Dbg_WDATA_8[2] = \<const0> ;
assign Dbg_WDATA_8[1] = \<const0> ;
assign Dbg_WDATA_8[0] = \<const0> ;
assign Dbg_WDATA_9[31] = \<const0> ;
assign Dbg_WDATA_9[30] = \<const0> ;
assign Dbg_WDATA_9[29] = \<const0> ;
assign Dbg_WDATA_9[28] = \<const0> ;
assign Dbg_WDATA_9[27] = \<const0> ;
assign Dbg_WDATA_9[26] = \<const0> ;
assign Dbg_WDATA_9[25] = \<const0> ;
assign Dbg_WDATA_9[24] = \<const0> ;
assign Dbg_WDATA_9[23] = \<const0> ;
assign Dbg_WDATA_9[22] = \<const0> ;
assign Dbg_WDATA_9[21] = \<const0> ;
assign Dbg_WDATA_9[20] = \<const0> ;
assign Dbg_WDATA_9[19] = \<const0> ;
assign Dbg_WDATA_9[18] = \<const0> ;
assign Dbg_WDATA_9[17] = \<const0> ;
assign Dbg_WDATA_9[16] = \<const0> ;
assign Dbg_WDATA_9[15] = \<const0> ;
assign Dbg_WDATA_9[14] = \<const0> ;
assign Dbg_WDATA_9[13] = \<const0> ;
assign Dbg_WDATA_9[12] = \<const0> ;
assign Dbg_WDATA_9[11] = \<const0> ;
assign Dbg_WDATA_9[10] = \<const0> ;
assign Dbg_WDATA_9[9] = \<const0> ;
assign Dbg_WDATA_9[8] = \<const0> ;
assign Dbg_WDATA_9[7] = \<const0> ;
assign Dbg_WDATA_9[6] = \<const0> ;
assign Dbg_WDATA_9[5] = \<const0> ;
assign Dbg_WDATA_9[4] = \<const0> ;
assign Dbg_WDATA_9[3] = \<const0> ;
assign Dbg_WDATA_9[2] = \<const0> ;
assign Dbg_WDATA_9[1] = \<const0> ;
assign Dbg_WDATA_9[0] = \<const0> ;
assign Dbg_WVALID_0 = \<const0> ;
assign Dbg_WVALID_1 = \<const0> ;
assign Dbg_WVALID_10 = \<const0> ;
assign Dbg_WVALID_11 = \<const0> ;
assign Dbg_WVALID_12 = \<const0> ;
assign Dbg_WVALID_13 = \<const0> ;
assign Dbg_WVALID_14 = \<const0> ;
assign Dbg_WVALID_15 = \<const0> ;
assign Dbg_WVALID_16 = \<const0> ;
assign Dbg_WVALID_17 = \<const0> ;
assign Dbg_WVALID_18 = \<const0> ;
assign Dbg_WVALID_19 = \<const0> ;
assign Dbg_WVALID_2 = \<const0> ;
assign Dbg_WVALID_20 = \<const0> ;
assign Dbg_WVALID_21 = \<const0> ;
assign Dbg_WVALID_22 = \<const0> ;
assign Dbg_WVALID_23 = \<const0> ;
assign Dbg_WVALID_24 = \<const0> ;
assign Dbg_WVALID_25 = \<const0> ;
assign Dbg_WVALID_26 = \<const0> ;
assign Dbg_WVALID_27 = \<const0> ;
assign Dbg_WVALID_28 = \<const0> ;
assign Dbg_WVALID_29 = \<const0> ;
assign Dbg_WVALID_3 = \<const0> ;
assign Dbg_WVALID_30 = \<const0> ;
assign Dbg_WVALID_31 = \<const0> ;
assign Dbg_WVALID_4 = \<const0> ;
assign Dbg_WVALID_5 = \<const0> ;
assign Dbg_WVALID_6 = \<const0> ;
assign Dbg_WVALID_7 = \<const0> ;
assign Dbg_WVALID_8 = \<const0> ;
assign Dbg_WVALID_9 = \<const0> ;
assign Ext_BRK = \<const0> ;
assign Ext_JTAG_DRCK = Dbg_Clk_31;
assign Ext_JTAG_UPDATE = Dbg_Update_31;
assign Interrupt = \<const0> ;
assign LMB_Addr_Strobe_0 = \<const0> ;
assign LMB_Addr_Strobe_1 = \<const0> ;
assign LMB_Addr_Strobe_10 = \<const0> ;
assign LMB_Addr_Strobe_11 = \<const0> ;
assign LMB_Addr_Strobe_12 = \<const0> ;
assign LMB_Addr_Strobe_13 = \<const0> ;
assign LMB_Addr_Strobe_14 = \<const0> ;
assign LMB_Addr_Strobe_15 = \<const0> ;
assign LMB_Addr_Strobe_16 = \<const0> ;
assign LMB_Addr_Strobe_17 = \<const0> ;
assign LMB_Addr_Strobe_18 = \<const0> ;
assign LMB_Addr_Strobe_19 = \<const0> ;
assign LMB_Addr_Strobe_2 = \<const0> ;
assign LMB_Addr_Strobe_20 = \<const0> ;
assign LMB_Addr_Strobe_21 = \<const0> ;
assign LMB_Addr_Strobe_22 = \<const0> ;
assign LMB_Addr_Strobe_23 = \<const0> ;
assign LMB_Addr_Strobe_24 = \<const0> ;
assign LMB_Addr_Strobe_25 = \<const0> ;
assign LMB_Addr_Strobe_26 = \<const0> ;
assign LMB_Addr_Strobe_27 = \<const0> ;
assign LMB_Addr_Strobe_28 = \<const0> ;
assign LMB_Addr_Strobe_29 = \<const0> ;
assign LMB_Addr_Strobe_3 = \<const0> ;
assign LMB_Addr_Strobe_30 = \<const0> ;
assign LMB_Addr_Strobe_31 = \<const0> ;
assign LMB_Addr_Strobe_4 = \<const0> ;
assign LMB_Addr_Strobe_5 = \<const0> ;
assign LMB_Addr_Strobe_6 = \<const0> ;
assign LMB_Addr_Strobe_7 = \<const0> ;
assign LMB_Addr_Strobe_8 = \<const0> ;
assign LMB_Addr_Strobe_9 = \<const0> ;
assign LMB_Byte_Enable_0[0] = \<const0> ;
assign LMB_Byte_Enable_0[1] = \<const0> ;
assign LMB_Byte_Enable_0[2] = \<const0> ;
assign LMB_Byte_Enable_0[3] = \<const0> ;
assign LMB_Byte_Enable_1[0] = \<const0> ;
assign LMB_Byte_Enable_1[1] = \<const0> ;
assign LMB_Byte_Enable_1[2] = \<const0> ;
assign LMB_Byte_Enable_1[3] = \<const0> ;
assign LMB_Byte_Enable_10[0] = \<const0> ;
assign LMB_Byte_Enable_10[1] = \<const0> ;
assign LMB_Byte_Enable_10[2] = \<const0> ;
assign LMB_Byte_Enable_10[3] = \<const0> ;
assign LMB_Byte_Enable_11[0] = \<const0> ;
assign LMB_Byte_Enable_11[1] = \<const0> ;
assign LMB_Byte_Enable_11[2] = \<const0> ;
assign LMB_Byte_Enable_11[3] = \<const0> ;
assign LMB_Byte_Enable_12[0] = \<const0> ;
assign LMB_Byte_Enable_12[1] = \<const0> ;
assign LMB_Byte_Enable_12[2] = \<const0> ;
assign LMB_Byte_Enable_12[3] = \<const0> ;
assign LMB_Byte_Enable_13[0] = \<const0> ;
assign LMB_Byte_Enable_13[1] = \<const0> ;
assign LMB_Byte_Enable_13[2] = \<const0> ;
assign LMB_Byte_Enable_13[3] = \<const0> ;
assign LMB_Byte_Enable_14[0] = \<const0> ;
assign LMB_Byte_Enable_14[1] = \<const0> ;
assign LMB_Byte_Enable_14[2] = \<const0> ;
assign LMB_Byte_Enable_14[3] = \<const0> ;
assign LMB_Byte_Enable_15[0] = \<const0> ;
assign LMB_Byte_Enable_15[1] = \<const0> ;
assign LMB_Byte_Enable_15[2] = \<const0> ;
assign LMB_Byte_Enable_15[3] = \<const0> ;
assign LMB_Byte_Enable_16[0] = \<const0> ;
assign LMB_Byte_Enable_16[1] = \<const0> ;
assign LMB_Byte_Enable_16[2] = \<const0> ;
assign LMB_Byte_Enable_16[3] = \<const0> ;
assign LMB_Byte_Enable_17[0] = \<const0> ;
assign LMB_Byte_Enable_17[1] = \<const0> ;
assign LMB_Byte_Enable_17[2] = \<const0> ;
assign LMB_Byte_Enable_17[3] = \<const0> ;
assign LMB_Byte_Enable_18[0] = \<const0> ;
assign LMB_Byte_Enable_18[1] = \<const0> ;
assign LMB_Byte_Enable_18[2] = \<const0> ;
assign LMB_Byte_Enable_18[3] = \<const0> ;
assign LMB_Byte_Enable_19[0] = \<const0> ;
assign LMB_Byte_Enable_19[1] = \<const0> ;
assign LMB_Byte_Enable_19[2] = \<const0> ;
assign LMB_Byte_Enable_19[3] = \<const0> ;
assign LMB_Byte_Enable_2[0] = \<const0> ;
assign LMB_Byte_Enable_2[1] = \<const0> ;
assign LMB_Byte_Enable_2[2] = \<const0> ;
assign LMB_Byte_Enable_2[3] = \<const0> ;
assign LMB_Byte_Enable_20[0] = \<const0> ;
assign LMB_Byte_Enable_20[1] = \<const0> ;
assign LMB_Byte_Enable_20[2] = \<const0> ;
assign LMB_Byte_Enable_20[3] = \<const0> ;
assign LMB_Byte_Enable_21[0] = \<const0> ;
assign LMB_Byte_Enable_21[1] = \<const0> ;
assign LMB_Byte_Enable_21[2] = \<const0> ;
assign LMB_Byte_Enable_21[3] = \<const0> ;
assign LMB_Byte_Enable_22[0] = \<const0> ;
assign LMB_Byte_Enable_22[1] = \<const0> ;
assign LMB_Byte_Enable_22[2] = \<const0> ;
assign LMB_Byte_Enable_22[3] = \<const0> ;
assign LMB_Byte_Enable_23[0] = \<const0> ;
assign LMB_Byte_Enable_23[1] = \<const0> ;
assign LMB_Byte_Enable_23[2] = \<const0> ;
assign LMB_Byte_Enable_23[3] = \<const0> ;
assign LMB_Byte_Enable_24[0] = \<const0> ;
assign LMB_Byte_Enable_24[1] = \<const0> ;
assign LMB_Byte_Enable_24[2] = \<const0> ;
assign LMB_Byte_Enable_24[3] = \<const0> ;
assign LMB_Byte_Enable_25[0] = \<const0> ;
assign LMB_Byte_Enable_25[1] = \<const0> ;
assign LMB_Byte_Enable_25[2] = \<const0> ;
assign LMB_Byte_Enable_25[3] = \<const0> ;
assign LMB_Byte_Enable_26[0] = \<const0> ;
assign LMB_Byte_Enable_26[1] = \<const0> ;
assign LMB_Byte_Enable_26[2] = \<const0> ;
assign LMB_Byte_Enable_26[3] = \<const0> ;
assign LMB_Byte_Enable_27[0] = \<const0> ;
assign LMB_Byte_Enable_27[1] = \<const0> ;
assign LMB_Byte_Enable_27[2] = \<const0> ;
assign LMB_Byte_Enable_27[3] = \<const0> ;
assign LMB_Byte_Enable_28[0] = \<const0> ;
assign LMB_Byte_Enable_28[1] = \<const0> ;
assign LMB_Byte_Enable_28[2] = \<const0> ;
assign LMB_Byte_Enable_28[3] = \<const0> ;
assign LMB_Byte_Enable_29[0] = \<const0> ;
assign LMB_Byte_Enable_29[1] = \<const0> ;
assign LMB_Byte_Enable_29[2] = \<const0> ;
assign LMB_Byte_Enable_29[3] = \<const0> ;
assign LMB_Byte_Enable_3[0] = \<const0> ;
assign LMB_Byte_Enable_3[1] = \<const0> ;
assign LMB_Byte_Enable_3[2] = \<const0> ;
assign LMB_Byte_Enable_3[3] = \<const0> ;
assign LMB_Byte_Enable_30[0] = \<const0> ;
assign LMB_Byte_Enable_30[1] = \<const0> ;
assign LMB_Byte_Enable_30[2] = \<const0> ;
assign LMB_Byte_Enable_30[3] = \<const0> ;
assign LMB_Byte_Enable_31[0] = \<const0> ;
assign LMB_Byte_Enable_31[1] = \<const0> ;
assign LMB_Byte_Enable_31[2] = \<const0> ;
assign LMB_Byte_Enable_31[3] = \<const0> ;
assign LMB_Byte_Enable_4[0] = \<const0> ;
assign LMB_Byte_Enable_4[1] = \<const0> ;
assign LMB_Byte_Enable_4[2] = \<const0> ;
assign LMB_Byte_Enable_4[3] = \<const0> ;
assign LMB_Byte_Enable_5[0] = \<const0> ;
assign LMB_Byte_Enable_5[1] = \<const0> ;
assign LMB_Byte_Enable_5[2] = \<const0> ;
assign LMB_Byte_Enable_5[3] = \<const0> ;
assign LMB_Byte_Enable_6[0] = \<const0> ;
assign LMB_Byte_Enable_6[1] = \<const0> ;
assign LMB_Byte_Enable_6[2] = \<const0> ;
assign LMB_Byte_Enable_6[3] = \<const0> ;
assign LMB_Byte_Enable_7[0] = \<const0> ;
assign LMB_Byte_Enable_7[1] = \<const0> ;
assign LMB_Byte_Enable_7[2] = \<const0> ;
assign LMB_Byte_Enable_7[3] = \<const0> ;
assign LMB_Byte_Enable_8[0] = \<const0> ;
assign LMB_Byte_Enable_8[1] = \<const0> ;
assign LMB_Byte_Enable_8[2] = \<const0> ;
assign LMB_Byte_Enable_8[3] = \<const0> ;
assign LMB_Byte_Enable_9[0] = \<const0> ;
assign LMB_Byte_Enable_9[1] = \<const0> ;
assign LMB_Byte_Enable_9[2] = \<const0> ;
assign LMB_Byte_Enable_9[3] = \<const0> ;
assign LMB_Data_Addr_0[0] = \<const0> ;
assign LMB_Data_Addr_0[1] = \<const0> ;
assign LMB_Data_Addr_0[2] = \<const0> ;
assign LMB_Data_Addr_0[3] = \<const0> ;
assign LMB_Data_Addr_0[4] = \<const0> ;
assign LMB_Data_Addr_0[5] = \<const0> ;
assign LMB_Data_Addr_0[6] = \<const0> ;
assign LMB_Data_Addr_0[7] = \<const0> ;
assign LMB_Data_Addr_0[8] = \<const0> ;
assign LMB_Data_Addr_0[9] = \<const0> ;
assign LMB_Data_Addr_0[10] = \<const0> ;
assign LMB_Data_Addr_0[11] = \<const0> ;
assign LMB_Data_Addr_0[12] = \<const0> ;
assign LMB_Data_Addr_0[13] = \<const0> ;
assign LMB_Data_Addr_0[14] = \<const0> ;
assign LMB_Data_Addr_0[15] = \<const0> ;
assign LMB_Data_Addr_0[16] = \<const0> ;
assign LMB_Data_Addr_0[17] = \<const0> ;
assign LMB_Data_Addr_0[18] = \<const0> ;
assign LMB_Data_Addr_0[19] = \<const0> ;
assign LMB_Data_Addr_0[20] = \<const0> ;
assign LMB_Data_Addr_0[21] = \<const0> ;
assign LMB_Data_Addr_0[22] = \<const0> ;
assign LMB_Data_Addr_0[23] = \<const0> ;
assign LMB_Data_Addr_0[24] = \<const0> ;
assign LMB_Data_Addr_0[25] = \<const0> ;
assign LMB_Data_Addr_0[26] = \<const0> ;
assign LMB_Data_Addr_0[27] = \<const0> ;
assign LMB_Data_Addr_0[28] = \<const0> ;
assign LMB_Data_Addr_0[29] = \<const0> ;
assign LMB_Data_Addr_0[30] = \<const0> ;
assign LMB_Data_Addr_0[31] = \<const0> ;
assign LMB_Data_Addr_1[0] = \<const0> ;
assign LMB_Data_Addr_1[1] = \<const0> ;
assign LMB_Data_Addr_1[2] = \<const0> ;
assign LMB_Data_Addr_1[3] = \<const0> ;
assign LMB_Data_Addr_1[4] = \<const0> ;
assign LMB_Data_Addr_1[5] = \<const0> ;
assign LMB_Data_Addr_1[6] = \<const0> ;
assign LMB_Data_Addr_1[7] = \<const0> ;
assign LMB_Data_Addr_1[8] = \<const0> ;
assign LMB_Data_Addr_1[9] = \<const0> ;
assign LMB_Data_Addr_1[10] = \<const0> ;
assign LMB_Data_Addr_1[11] = \<const0> ;
assign LMB_Data_Addr_1[12] = \<const0> ;
assign LMB_Data_Addr_1[13] = \<const0> ;
assign LMB_Data_Addr_1[14] = \<const0> ;
assign LMB_Data_Addr_1[15] = \<const0> ;
assign LMB_Data_Addr_1[16] = \<const0> ;
assign LMB_Data_Addr_1[17] = \<const0> ;
assign LMB_Data_Addr_1[18] = \<const0> ;
assign LMB_Data_Addr_1[19] = \<const0> ;
assign LMB_Data_Addr_1[20] = \<const0> ;
assign LMB_Data_Addr_1[21] = \<const0> ;
assign LMB_Data_Addr_1[22] = \<const0> ;
assign LMB_Data_Addr_1[23] = \<const0> ;
assign LMB_Data_Addr_1[24] = \<const0> ;
assign LMB_Data_Addr_1[25] = \<const0> ;
assign LMB_Data_Addr_1[26] = \<const0> ;
assign LMB_Data_Addr_1[27] = \<const0> ;
assign LMB_Data_Addr_1[28] = \<const0> ;
assign LMB_Data_Addr_1[29] = \<const0> ;
assign LMB_Data_Addr_1[30] = \<const0> ;
assign LMB_Data_Addr_1[31] = \<const0> ;
assign LMB_Data_Addr_10[0] = \<const0> ;
assign LMB_Data_Addr_10[1] = \<const0> ;
assign LMB_Data_Addr_10[2] = \<const0> ;
assign LMB_Data_Addr_10[3] = \<const0> ;
assign LMB_Data_Addr_10[4] = \<const0> ;
assign LMB_Data_Addr_10[5] = \<const0> ;
assign LMB_Data_Addr_10[6] = \<const0> ;
assign LMB_Data_Addr_10[7] = \<const0> ;
assign LMB_Data_Addr_10[8] = \<const0> ;
assign LMB_Data_Addr_10[9] = \<const0> ;
assign LMB_Data_Addr_10[10] = \<const0> ;
assign LMB_Data_Addr_10[11] = \<const0> ;
assign LMB_Data_Addr_10[12] = \<const0> ;
assign LMB_Data_Addr_10[13] = \<const0> ;
assign LMB_Data_Addr_10[14] = \<const0> ;
assign LMB_Data_Addr_10[15] = \<const0> ;
assign LMB_Data_Addr_10[16] = \<const0> ;
assign LMB_Data_Addr_10[17] = \<const0> ;
assign LMB_Data_Addr_10[18] = \<const0> ;
assign LMB_Data_Addr_10[19] = \<const0> ;
assign LMB_Data_Addr_10[20] = \<const0> ;
assign LMB_Data_Addr_10[21] = \<const0> ;
assign LMB_Data_Addr_10[22] = \<const0> ;
assign LMB_Data_Addr_10[23] = \<const0> ;
assign LMB_Data_Addr_10[24] = \<const0> ;
assign LMB_Data_Addr_10[25] = \<const0> ;
assign LMB_Data_Addr_10[26] = \<const0> ;
assign LMB_Data_Addr_10[27] = \<const0> ;
assign LMB_Data_Addr_10[28] = \<const0> ;
assign LMB_Data_Addr_10[29] = \<const0> ;
assign LMB_Data_Addr_10[30] = \<const0> ;
assign LMB_Data_Addr_10[31] = \<const0> ;
assign LMB_Data_Addr_11[0] = \<const0> ;
assign LMB_Data_Addr_11[1] = \<const0> ;
assign LMB_Data_Addr_11[2] = \<const0> ;
assign LMB_Data_Addr_11[3] = \<const0> ;
assign LMB_Data_Addr_11[4] = \<const0> ;
assign LMB_Data_Addr_11[5] = \<const0> ;
assign LMB_Data_Addr_11[6] = \<const0> ;
assign LMB_Data_Addr_11[7] = \<const0> ;
assign LMB_Data_Addr_11[8] = \<const0> ;
assign LMB_Data_Addr_11[9] = \<const0> ;
assign LMB_Data_Addr_11[10] = \<const0> ;
assign LMB_Data_Addr_11[11] = \<const0> ;
assign LMB_Data_Addr_11[12] = \<const0> ;
assign LMB_Data_Addr_11[13] = \<const0> ;
assign LMB_Data_Addr_11[14] = \<const0> ;
assign LMB_Data_Addr_11[15] = \<const0> ;
assign LMB_Data_Addr_11[16] = \<const0> ;
assign LMB_Data_Addr_11[17] = \<const0> ;
assign LMB_Data_Addr_11[18] = \<const0> ;
assign LMB_Data_Addr_11[19] = \<const0> ;
assign LMB_Data_Addr_11[20] = \<const0> ;
assign LMB_Data_Addr_11[21] = \<const0> ;
assign LMB_Data_Addr_11[22] = \<const0> ;
assign LMB_Data_Addr_11[23] = \<const0> ;
assign LMB_Data_Addr_11[24] = \<const0> ;
assign LMB_Data_Addr_11[25] = \<const0> ;
assign LMB_Data_Addr_11[26] = \<const0> ;
assign LMB_Data_Addr_11[27] = \<const0> ;
assign LMB_Data_Addr_11[28] = \<const0> ;
assign LMB_Data_Addr_11[29] = \<const0> ;
assign LMB_Data_Addr_11[30] = \<const0> ;
assign LMB_Data_Addr_11[31] = \<const0> ;
assign LMB_Data_Addr_12[0] = \<const0> ;
assign LMB_Data_Addr_12[1] = \<const0> ;
assign LMB_Data_Addr_12[2] = \<const0> ;
assign LMB_Data_Addr_12[3] = \<const0> ;
assign LMB_Data_Addr_12[4] = \<const0> ;
assign LMB_Data_Addr_12[5] = \<const0> ;
assign LMB_Data_Addr_12[6] = \<const0> ;
assign LMB_Data_Addr_12[7] = \<const0> ;
assign LMB_Data_Addr_12[8] = \<const0> ;
assign LMB_Data_Addr_12[9] = \<const0> ;
assign LMB_Data_Addr_12[10] = \<const0> ;
assign LMB_Data_Addr_12[11] = \<const0> ;
assign LMB_Data_Addr_12[12] = \<const0> ;
assign LMB_Data_Addr_12[13] = \<const0> ;
assign LMB_Data_Addr_12[14] = \<const0> ;
assign LMB_Data_Addr_12[15] = \<const0> ;
assign LMB_Data_Addr_12[16] = \<const0> ;
assign LMB_Data_Addr_12[17] = \<const0> ;
assign LMB_Data_Addr_12[18] = \<const0> ;
assign LMB_Data_Addr_12[19] = \<const0> ;
assign LMB_Data_Addr_12[20] = \<const0> ;
assign LMB_Data_Addr_12[21] = \<const0> ;
assign LMB_Data_Addr_12[22] = \<const0> ;
assign LMB_Data_Addr_12[23] = \<const0> ;
assign LMB_Data_Addr_12[24] = \<const0> ;
assign LMB_Data_Addr_12[25] = \<const0> ;
assign LMB_Data_Addr_12[26] = \<const0> ;
assign LMB_Data_Addr_12[27] = \<const0> ;
assign LMB_Data_Addr_12[28] = \<const0> ;
assign LMB_Data_Addr_12[29] = \<const0> ;
assign LMB_Data_Addr_12[30] = \<const0> ;
assign LMB_Data_Addr_12[31] = \<const0> ;
assign LMB_Data_Addr_13[0] = \<const0> ;
assign LMB_Data_Addr_13[1] = \<const0> ;
assign LMB_Data_Addr_13[2] = \<const0> ;
assign LMB_Data_Addr_13[3] = \<const0> ;
assign LMB_Data_Addr_13[4] = \<const0> ;
assign LMB_Data_Addr_13[5] = \<const0> ;
assign LMB_Data_Addr_13[6] = \<const0> ;
assign LMB_Data_Addr_13[7] = \<const0> ;
assign LMB_Data_Addr_13[8] = \<const0> ;
assign LMB_Data_Addr_13[9] = \<const0> ;
assign LMB_Data_Addr_13[10] = \<const0> ;
assign LMB_Data_Addr_13[11] = \<const0> ;
assign LMB_Data_Addr_13[12] = \<const0> ;
assign LMB_Data_Addr_13[13] = \<const0> ;
assign LMB_Data_Addr_13[14] = \<const0> ;
assign LMB_Data_Addr_13[15] = \<const0> ;
assign LMB_Data_Addr_13[16] = \<const0> ;
assign LMB_Data_Addr_13[17] = \<const0> ;
assign LMB_Data_Addr_13[18] = \<const0> ;
assign LMB_Data_Addr_13[19] = \<const0> ;
assign LMB_Data_Addr_13[20] = \<const0> ;
assign LMB_Data_Addr_13[21] = \<const0> ;
assign LMB_Data_Addr_13[22] = \<const0> ;
assign LMB_Data_Addr_13[23] = \<const0> ;
assign LMB_Data_Addr_13[24] = \<const0> ;
assign LMB_Data_Addr_13[25] = \<const0> ;
assign LMB_Data_Addr_13[26] = \<const0> ;
assign LMB_Data_Addr_13[27] = \<const0> ;
assign LMB_Data_Addr_13[28] = \<const0> ;
assign LMB_Data_Addr_13[29] = \<const0> ;
assign LMB_Data_Addr_13[30] = \<const0> ;
assign LMB_Data_Addr_13[31] = \<const0> ;
assign LMB_Data_Addr_14[0] = \<const0> ;
assign LMB_Data_Addr_14[1] = \<const0> ;
assign LMB_Data_Addr_14[2] = \<const0> ;
assign LMB_Data_Addr_14[3] = \<const0> ;
assign LMB_Data_Addr_14[4] = \<const0> ;
assign LMB_Data_Addr_14[5] = \<const0> ;
assign LMB_Data_Addr_14[6] = \<const0> ;
assign LMB_Data_Addr_14[7] = \<const0> ;
assign LMB_Data_Addr_14[8] = \<const0> ;
assign LMB_Data_Addr_14[9] = \<const0> ;
assign LMB_Data_Addr_14[10] = \<const0> ;
assign LMB_Data_Addr_14[11] = \<const0> ;
assign LMB_Data_Addr_14[12] = \<const0> ;
assign LMB_Data_Addr_14[13] = \<const0> ;
assign LMB_Data_Addr_14[14] = \<const0> ;
assign LMB_Data_Addr_14[15] = \<const0> ;
assign LMB_Data_Addr_14[16] = \<const0> ;
assign LMB_Data_Addr_14[17] = \<const0> ;
assign LMB_Data_Addr_14[18] = \<const0> ;
assign LMB_Data_Addr_14[19] = \<const0> ;
assign LMB_Data_Addr_14[20] = \<const0> ;
assign LMB_Data_Addr_14[21] = \<const0> ;
assign LMB_Data_Addr_14[22] = \<const0> ;
assign LMB_Data_Addr_14[23] = \<const0> ;
assign LMB_Data_Addr_14[24] = \<const0> ;
assign LMB_Data_Addr_14[25] = \<const0> ;
assign LMB_Data_Addr_14[26] = \<const0> ;
assign LMB_Data_Addr_14[27] = \<const0> ;
assign LMB_Data_Addr_14[28] = \<const0> ;
assign LMB_Data_Addr_14[29] = \<const0> ;
assign LMB_Data_Addr_14[30] = \<const0> ;
assign LMB_Data_Addr_14[31] = \<const0> ;
assign LMB_Data_Addr_15[0] = \<const0> ;
assign LMB_Data_Addr_15[1] = \<const0> ;
assign LMB_Data_Addr_15[2] = \<const0> ;
assign LMB_Data_Addr_15[3] = \<const0> ;
assign LMB_Data_Addr_15[4] = \<const0> ;
assign LMB_Data_Addr_15[5] = \<const0> ;
assign LMB_Data_Addr_15[6] = \<const0> ;
assign LMB_Data_Addr_15[7] = \<const0> ;
assign LMB_Data_Addr_15[8] = \<const0> ;
assign LMB_Data_Addr_15[9] = \<const0> ;
assign LMB_Data_Addr_15[10] = \<const0> ;
assign LMB_Data_Addr_15[11] = \<const0> ;
assign LMB_Data_Addr_15[12] = \<const0> ;
assign LMB_Data_Addr_15[13] = \<const0> ;
assign LMB_Data_Addr_15[14] = \<const0> ;
assign LMB_Data_Addr_15[15] = \<const0> ;
assign LMB_Data_Addr_15[16] = \<const0> ;
assign LMB_Data_Addr_15[17] = \<const0> ;
assign LMB_Data_Addr_15[18] = \<const0> ;
assign LMB_Data_Addr_15[19] = \<const0> ;
assign LMB_Data_Addr_15[20] = \<const0> ;
assign LMB_Data_Addr_15[21] = \<const0> ;
assign LMB_Data_Addr_15[22] = \<const0> ;
assign LMB_Data_Addr_15[23] = \<const0> ;
assign LMB_Data_Addr_15[24] = \<const0> ;
assign LMB_Data_Addr_15[25] = \<const0> ;
assign LMB_Data_Addr_15[26] = \<const0> ;
assign LMB_Data_Addr_15[27] = \<const0> ;
assign LMB_Data_Addr_15[28] = \<const0> ;
assign LMB_Data_Addr_15[29] = \<const0> ;
assign LMB_Data_Addr_15[30] = \<const0> ;
assign LMB_Data_Addr_15[31] = \<const0> ;
assign LMB_Data_Addr_16[0] = \<const0> ;
assign LMB_Data_Addr_16[1] = \<const0> ;
assign LMB_Data_Addr_16[2] = \<const0> ;
assign LMB_Data_Addr_16[3] = \<const0> ;
assign LMB_Data_Addr_16[4] = \<const0> ;
assign LMB_Data_Addr_16[5] = \<const0> ;
assign LMB_Data_Addr_16[6] = \<const0> ;
assign LMB_Data_Addr_16[7] = \<const0> ;
assign LMB_Data_Addr_16[8] = \<const0> ;
assign LMB_Data_Addr_16[9] = \<const0> ;
assign LMB_Data_Addr_16[10] = \<const0> ;
assign LMB_Data_Addr_16[11] = \<const0> ;
assign LMB_Data_Addr_16[12] = \<const0> ;
assign LMB_Data_Addr_16[13] = \<const0> ;
assign LMB_Data_Addr_16[14] = \<const0> ;
assign LMB_Data_Addr_16[15] = \<const0> ;
assign LMB_Data_Addr_16[16] = \<const0> ;
assign LMB_Data_Addr_16[17] = \<const0> ;
assign LMB_Data_Addr_16[18] = \<const0> ;
assign LMB_Data_Addr_16[19] = \<const0> ;
assign LMB_Data_Addr_16[20] = \<const0> ;
assign LMB_Data_Addr_16[21] = \<const0> ;
assign LMB_Data_Addr_16[22] = \<const0> ;
assign LMB_Data_Addr_16[23] = \<const0> ;
assign LMB_Data_Addr_16[24] = \<const0> ;
assign LMB_Data_Addr_16[25] = \<const0> ;
assign LMB_Data_Addr_16[26] = \<const0> ;
assign LMB_Data_Addr_16[27] = \<const0> ;
assign LMB_Data_Addr_16[28] = \<const0> ;
assign LMB_Data_Addr_16[29] = \<const0> ;
assign LMB_Data_Addr_16[30] = \<const0> ;
assign LMB_Data_Addr_16[31] = \<const0> ;
assign LMB_Data_Addr_17[0] = \<const0> ;
assign LMB_Data_Addr_17[1] = \<const0> ;
assign LMB_Data_Addr_17[2] = \<const0> ;
assign LMB_Data_Addr_17[3] = \<const0> ;
assign LMB_Data_Addr_17[4] = \<const0> ;
assign LMB_Data_Addr_17[5] = \<const0> ;
assign LMB_Data_Addr_17[6] = \<const0> ;
assign LMB_Data_Addr_17[7] = \<const0> ;
assign LMB_Data_Addr_17[8] = \<const0> ;
assign LMB_Data_Addr_17[9] = \<const0> ;
assign LMB_Data_Addr_17[10] = \<const0> ;
assign LMB_Data_Addr_17[11] = \<const0> ;
assign LMB_Data_Addr_17[12] = \<const0> ;
assign LMB_Data_Addr_17[13] = \<const0> ;
assign LMB_Data_Addr_17[14] = \<const0> ;
assign LMB_Data_Addr_17[15] = \<const0> ;
assign LMB_Data_Addr_17[16] = \<const0> ;
assign LMB_Data_Addr_17[17] = \<const0> ;
assign LMB_Data_Addr_17[18] = \<const0> ;
assign LMB_Data_Addr_17[19] = \<const0> ;
assign LMB_Data_Addr_17[20] = \<const0> ;
assign LMB_Data_Addr_17[21] = \<const0> ;
assign LMB_Data_Addr_17[22] = \<const0> ;
assign LMB_Data_Addr_17[23] = \<const0> ;
assign LMB_Data_Addr_17[24] = \<const0> ;
assign LMB_Data_Addr_17[25] = \<const0> ;
assign LMB_Data_Addr_17[26] = \<const0> ;
assign LMB_Data_Addr_17[27] = \<const0> ;
assign LMB_Data_Addr_17[28] = \<const0> ;
assign LMB_Data_Addr_17[29] = \<const0> ;
assign LMB_Data_Addr_17[30] = \<const0> ;
assign LMB_Data_Addr_17[31] = \<const0> ;
assign LMB_Data_Addr_18[0] = \<const0> ;
assign LMB_Data_Addr_18[1] = \<const0> ;
assign LMB_Data_Addr_18[2] = \<const0> ;
assign LMB_Data_Addr_18[3] = \<const0> ;
assign LMB_Data_Addr_18[4] = \<const0> ;
assign LMB_Data_Addr_18[5] = \<const0> ;
assign LMB_Data_Addr_18[6] = \<const0> ;
assign LMB_Data_Addr_18[7] = \<const0> ;
assign LMB_Data_Addr_18[8] = \<const0> ;
assign LMB_Data_Addr_18[9] = \<const0> ;
assign LMB_Data_Addr_18[10] = \<const0> ;
assign LMB_Data_Addr_18[11] = \<const0> ;
assign LMB_Data_Addr_18[12] = \<const0> ;
assign LMB_Data_Addr_18[13] = \<const0> ;
assign LMB_Data_Addr_18[14] = \<const0> ;
assign LMB_Data_Addr_18[15] = \<const0> ;
assign LMB_Data_Addr_18[16] = \<const0> ;
assign LMB_Data_Addr_18[17] = \<const0> ;
assign LMB_Data_Addr_18[18] = \<const0> ;
assign LMB_Data_Addr_18[19] = \<const0> ;
assign LMB_Data_Addr_18[20] = \<const0> ;
assign LMB_Data_Addr_18[21] = \<const0> ;
assign LMB_Data_Addr_18[22] = \<const0> ;
assign LMB_Data_Addr_18[23] = \<const0> ;
assign LMB_Data_Addr_18[24] = \<const0> ;
assign LMB_Data_Addr_18[25] = \<const0> ;
assign LMB_Data_Addr_18[26] = \<const0> ;
assign LMB_Data_Addr_18[27] = \<const0> ;
assign LMB_Data_Addr_18[28] = \<const0> ;
assign LMB_Data_Addr_18[29] = \<const0> ;
assign LMB_Data_Addr_18[30] = \<const0> ;
assign LMB_Data_Addr_18[31] = \<const0> ;
assign LMB_Data_Addr_19[0] = \<const0> ;
assign LMB_Data_Addr_19[1] = \<const0> ;
assign LMB_Data_Addr_19[2] = \<const0> ;
assign LMB_Data_Addr_19[3] = \<const0> ;
assign LMB_Data_Addr_19[4] = \<const0> ;
assign LMB_Data_Addr_19[5] = \<const0> ;
assign LMB_Data_Addr_19[6] = \<const0> ;
assign LMB_Data_Addr_19[7] = \<const0> ;
assign LMB_Data_Addr_19[8] = \<const0> ;
assign LMB_Data_Addr_19[9] = \<const0> ;
assign LMB_Data_Addr_19[10] = \<const0> ;
assign LMB_Data_Addr_19[11] = \<const0> ;
assign LMB_Data_Addr_19[12] = \<const0> ;
assign LMB_Data_Addr_19[13] = \<const0> ;
assign LMB_Data_Addr_19[14] = \<const0> ;
assign LMB_Data_Addr_19[15] = \<const0> ;
assign LMB_Data_Addr_19[16] = \<const0> ;
assign LMB_Data_Addr_19[17] = \<const0> ;
assign LMB_Data_Addr_19[18] = \<const0> ;
assign LMB_Data_Addr_19[19] = \<const0> ;
assign LMB_Data_Addr_19[20] = \<const0> ;
assign LMB_Data_Addr_19[21] = \<const0> ;
assign LMB_Data_Addr_19[22] = \<const0> ;
assign LMB_Data_Addr_19[23] = \<const0> ;
assign LMB_Data_Addr_19[24] = \<const0> ;
assign LMB_Data_Addr_19[25] = \<const0> ;
assign LMB_Data_Addr_19[26] = \<const0> ;
assign LMB_Data_Addr_19[27] = \<const0> ;
assign LMB_Data_Addr_19[28] = \<const0> ;
assign LMB_Data_Addr_19[29] = \<const0> ;
assign LMB_Data_Addr_19[30] = \<const0> ;
assign LMB_Data_Addr_19[31] = \<const0> ;
assign LMB_Data_Addr_2[0] = \<const0> ;
assign LMB_Data_Addr_2[1] = \<const0> ;
assign LMB_Data_Addr_2[2] = \<const0> ;
assign LMB_Data_Addr_2[3] = \<const0> ;
assign LMB_Data_Addr_2[4] = \<const0> ;
assign LMB_Data_Addr_2[5] = \<const0> ;
assign LMB_Data_Addr_2[6] = \<const0> ;
assign LMB_Data_Addr_2[7] = \<const0> ;
assign LMB_Data_Addr_2[8] = \<const0> ;
assign LMB_Data_Addr_2[9] = \<const0> ;
assign LMB_Data_Addr_2[10] = \<const0> ;
assign LMB_Data_Addr_2[11] = \<const0> ;
assign LMB_Data_Addr_2[12] = \<const0> ;
assign LMB_Data_Addr_2[13] = \<const0> ;
assign LMB_Data_Addr_2[14] = \<const0> ;
assign LMB_Data_Addr_2[15] = \<const0> ;
assign LMB_Data_Addr_2[16] = \<const0> ;
assign LMB_Data_Addr_2[17] = \<const0> ;
assign LMB_Data_Addr_2[18] = \<const0> ;
assign LMB_Data_Addr_2[19] = \<const0> ;
assign LMB_Data_Addr_2[20] = \<const0> ;
assign LMB_Data_Addr_2[21] = \<const0> ;
assign LMB_Data_Addr_2[22] = \<const0> ;
assign LMB_Data_Addr_2[23] = \<const0> ;
assign LMB_Data_Addr_2[24] = \<const0> ;
assign LMB_Data_Addr_2[25] = \<const0> ;
assign LMB_Data_Addr_2[26] = \<const0> ;
assign LMB_Data_Addr_2[27] = \<const0> ;
assign LMB_Data_Addr_2[28] = \<const0> ;
assign LMB_Data_Addr_2[29] = \<const0> ;
assign LMB_Data_Addr_2[30] = \<const0> ;
assign LMB_Data_Addr_2[31] = \<const0> ;
assign LMB_Data_Addr_20[0] = \<const0> ;
assign LMB_Data_Addr_20[1] = \<const0> ;
assign LMB_Data_Addr_20[2] = \<const0> ;
assign LMB_Data_Addr_20[3] = \<const0> ;
assign LMB_Data_Addr_20[4] = \<const0> ;
assign LMB_Data_Addr_20[5] = \<const0> ;
assign LMB_Data_Addr_20[6] = \<const0> ;
assign LMB_Data_Addr_20[7] = \<const0> ;
assign LMB_Data_Addr_20[8] = \<const0> ;
assign LMB_Data_Addr_20[9] = \<const0> ;
assign LMB_Data_Addr_20[10] = \<const0> ;
assign LMB_Data_Addr_20[11] = \<const0> ;
assign LMB_Data_Addr_20[12] = \<const0> ;
assign LMB_Data_Addr_20[13] = \<const0> ;
assign LMB_Data_Addr_20[14] = \<const0> ;
assign LMB_Data_Addr_20[15] = \<const0> ;
assign LMB_Data_Addr_20[16] = \<const0> ;
assign LMB_Data_Addr_20[17] = \<const0> ;
assign LMB_Data_Addr_20[18] = \<const0> ;
assign LMB_Data_Addr_20[19] = \<const0> ;
assign LMB_Data_Addr_20[20] = \<const0> ;
assign LMB_Data_Addr_20[21] = \<const0> ;
assign LMB_Data_Addr_20[22] = \<const0> ;
assign LMB_Data_Addr_20[23] = \<const0> ;
assign LMB_Data_Addr_20[24] = \<const0> ;
assign LMB_Data_Addr_20[25] = \<const0> ;
assign LMB_Data_Addr_20[26] = \<const0> ;
assign LMB_Data_Addr_20[27] = \<const0> ;
assign LMB_Data_Addr_20[28] = \<const0> ;
assign LMB_Data_Addr_20[29] = \<const0> ;
assign LMB_Data_Addr_20[30] = \<const0> ;
assign LMB_Data_Addr_20[31] = \<const0> ;
assign LMB_Data_Addr_21[0] = \<const0> ;
assign LMB_Data_Addr_21[1] = \<const0> ;
assign LMB_Data_Addr_21[2] = \<const0> ;
assign LMB_Data_Addr_21[3] = \<const0> ;
assign LMB_Data_Addr_21[4] = \<const0> ;
assign LMB_Data_Addr_21[5] = \<const0> ;
assign LMB_Data_Addr_21[6] = \<const0> ;
assign LMB_Data_Addr_21[7] = \<const0> ;
assign LMB_Data_Addr_21[8] = \<const0> ;
assign LMB_Data_Addr_21[9] = \<const0> ;
assign LMB_Data_Addr_21[10] = \<const0> ;
assign LMB_Data_Addr_21[11] = \<const0> ;
assign LMB_Data_Addr_21[12] = \<const0> ;
assign LMB_Data_Addr_21[13] = \<const0> ;
assign LMB_Data_Addr_21[14] = \<const0> ;
assign LMB_Data_Addr_21[15] = \<const0> ;
assign LMB_Data_Addr_21[16] = \<const0> ;
assign LMB_Data_Addr_21[17] = \<const0> ;
assign LMB_Data_Addr_21[18] = \<const0> ;
assign LMB_Data_Addr_21[19] = \<const0> ;
assign LMB_Data_Addr_21[20] = \<const0> ;
assign LMB_Data_Addr_21[21] = \<const0> ;
assign LMB_Data_Addr_21[22] = \<const0> ;
assign LMB_Data_Addr_21[23] = \<const0> ;
assign LMB_Data_Addr_21[24] = \<const0> ;
assign LMB_Data_Addr_21[25] = \<const0> ;
assign LMB_Data_Addr_21[26] = \<const0> ;
assign LMB_Data_Addr_21[27] = \<const0> ;
assign LMB_Data_Addr_21[28] = \<const0> ;
assign LMB_Data_Addr_21[29] = \<const0> ;
assign LMB_Data_Addr_21[30] = \<const0> ;
assign LMB_Data_Addr_21[31] = \<const0> ;
assign LMB_Data_Addr_22[0] = \<const0> ;
assign LMB_Data_Addr_22[1] = \<const0> ;
assign LMB_Data_Addr_22[2] = \<const0> ;
assign LMB_Data_Addr_22[3] = \<const0> ;
assign LMB_Data_Addr_22[4] = \<const0> ;
assign LMB_Data_Addr_22[5] = \<const0> ;
assign LMB_Data_Addr_22[6] = \<const0> ;
assign LMB_Data_Addr_22[7] = \<const0> ;
assign LMB_Data_Addr_22[8] = \<const0> ;
assign LMB_Data_Addr_22[9] = \<const0> ;
assign LMB_Data_Addr_22[10] = \<const0> ;
assign LMB_Data_Addr_22[11] = \<const0> ;
assign LMB_Data_Addr_22[12] = \<const0> ;
assign LMB_Data_Addr_22[13] = \<const0> ;
assign LMB_Data_Addr_22[14] = \<const0> ;
assign LMB_Data_Addr_22[15] = \<const0> ;
assign LMB_Data_Addr_22[16] = \<const0> ;
assign LMB_Data_Addr_22[17] = \<const0> ;
assign LMB_Data_Addr_22[18] = \<const0> ;
assign LMB_Data_Addr_22[19] = \<const0> ;
assign LMB_Data_Addr_22[20] = \<const0> ;
assign LMB_Data_Addr_22[21] = \<const0> ;
assign LMB_Data_Addr_22[22] = \<const0> ;
assign LMB_Data_Addr_22[23] = \<const0> ;
assign LMB_Data_Addr_22[24] = \<const0> ;
assign LMB_Data_Addr_22[25] = \<const0> ;
assign LMB_Data_Addr_22[26] = \<const0> ;
assign LMB_Data_Addr_22[27] = \<const0> ;
assign LMB_Data_Addr_22[28] = \<const0> ;
assign LMB_Data_Addr_22[29] = \<const0> ;
assign LMB_Data_Addr_22[30] = \<const0> ;
assign LMB_Data_Addr_22[31] = \<const0> ;
assign LMB_Data_Addr_23[0] = \<const0> ;
assign LMB_Data_Addr_23[1] = \<const0> ;
assign LMB_Data_Addr_23[2] = \<const0> ;
assign LMB_Data_Addr_23[3] = \<const0> ;
assign LMB_Data_Addr_23[4] = \<const0> ;
assign LMB_Data_Addr_23[5] = \<const0> ;
assign LMB_Data_Addr_23[6] = \<const0> ;
assign LMB_Data_Addr_23[7] = \<const0> ;
assign LMB_Data_Addr_23[8] = \<const0> ;
assign LMB_Data_Addr_23[9] = \<const0> ;
assign LMB_Data_Addr_23[10] = \<const0> ;
assign LMB_Data_Addr_23[11] = \<const0> ;
assign LMB_Data_Addr_23[12] = \<const0> ;
assign LMB_Data_Addr_23[13] = \<const0> ;
assign LMB_Data_Addr_23[14] = \<const0> ;
assign LMB_Data_Addr_23[15] = \<const0> ;
assign LMB_Data_Addr_23[16] = \<const0> ;
assign LMB_Data_Addr_23[17] = \<const0> ;
assign LMB_Data_Addr_23[18] = \<const0> ;
assign LMB_Data_Addr_23[19] = \<const0> ;
assign LMB_Data_Addr_23[20] = \<const0> ;
assign LMB_Data_Addr_23[21] = \<const0> ;
assign LMB_Data_Addr_23[22] = \<const0> ;
assign LMB_Data_Addr_23[23] = \<const0> ;
assign LMB_Data_Addr_23[24] = \<const0> ;
assign LMB_Data_Addr_23[25] = \<const0> ;
assign LMB_Data_Addr_23[26] = \<const0> ;
assign LMB_Data_Addr_23[27] = \<const0> ;
assign LMB_Data_Addr_23[28] = \<const0> ;
assign LMB_Data_Addr_23[29] = \<const0> ;
assign LMB_Data_Addr_23[30] = \<const0> ;
assign LMB_Data_Addr_23[31] = \<const0> ;
assign LMB_Data_Addr_24[0] = \<const0> ;
assign LMB_Data_Addr_24[1] = \<const0> ;
assign LMB_Data_Addr_24[2] = \<const0> ;
assign LMB_Data_Addr_24[3] = \<const0> ;
assign LMB_Data_Addr_24[4] = \<const0> ;
assign LMB_Data_Addr_24[5] = \<const0> ;
assign LMB_Data_Addr_24[6] = \<const0> ;
assign LMB_Data_Addr_24[7] = \<const0> ;
assign LMB_Data_Addr_24[8] = \<const0> ;
assign LMB_Data_Addr_24[9] = \<const0> ;
assign LMB_Data_Addr_24[10] = \<const0> ;
assign LMB_Data_Addr_24[11] = \<const0> ;
assign LMB_Data_Addr_24[12] = \<const0> ;
assign LMB_Data_Addr_24[13] = \<const0> ;
assign LMB_Data_Addr_24[14] = \<const0> ;
assign LMB_Data_Addr_24[15] = \<const0> ;
assign LMB_Data_Addr_24[16] = \<const0> ;
assign LMB_Data_Addr_24[17] = \<const0> ;
assign LMB_Data_Addr_24[18] = \<const0> ;
assign LMB_Data_Addr_24[19] = \<const0> ;
assign LMB_Data_Addr_24[20] = \<const0> ;
assign LMB_Data_Addr_24[21] = \<const0> ;
assign LMB_Data_Addr_24[22] = \<const0> ;
assign LMB_Data_Addr_24[23] = \<const0> ;
assign LMB_Data_Addr_24[24] = \<const0> ;
assign LMB_Data_Addr_24[25] = \<const0> ;
assign LMB_Data_Addr_24[26] = \<const0> ;
assign LMB_Data_Addr_24[27] = \<const0> ;
assign LMB_Data_Addr_24[28] = \<const0> ;
assign LMB_Data_Addr_24[29] = \<const0> ;
assign LMB_Data_Addr_24[30] = \<const0> ;
assign LMB_Data_Addr_24[31] = \<const0> ;
assign LMB_Data_Addr_25[0] = \<const0> ;
assign LMB_Data_Addr_25[1] = \<const0> ;
assign LMB_Data_Addr_25[2] = \<const0> ;
assign LMB_Data_Addr_25[3] = \<const0> ;
assign LMB_Data_Addr_25[4] = \<const0> ;
assign LMB_Data_Addr_25[5] = \<const0> ;
assign LMB_Data_Addr_25[6] = \<const0> ;
assign LMB_Data_Addr_25[7] = \<const0> ;
assign LMB_Data_Addr_25[8] = \<const0> ;
assign LMB_Data_Addr_25[9] = \<const0> ;
assign LMB_Data_Addr_25[10] = \<const0> ;
assign LMB_Data_Addr_25[11] = \<const0> ;
assign LMB_Data_Addr_25[12] = \<const0> ;
assign LMB_Data_Addr_25[13] = \<const0> ;
assign LMB_Data_Addr_25[14] = \<const0> ;
assign LMB_Data_Addr_25[15] = \<const0> ;
assign LMB_Data_Addr_25[16] = \<const0> ;
assign LMB_Data_Addr_25[17] = \<const0> ;
assign LMB_Data_Addr_25[18] = \<const0> ;
assign LMB_Data_Addr_25[19] = \<const0> ;
assign LMB_Data_Addr_25[20] = \<const0> ;
assign LMB_Data_Addr_25[21] = \<const0> ;
assign LMB_Data_Addr_25[22] = \<const0> ;
assign LMB_Data_Addr_25[23] = \<const0> ;
assign LMB_Data_Addr_25[24] = \<const0> ;
assign LMB_Data_Addr_25[25] = \<const0> ;
assign LMB_Data_Addr_25[26] = \<const0> ;
assign LMB_Data_Addr_25[27] = \<const0> ;
assign LMB_Data_Addr_25[28] = \<const0> ;
assign LMB_Data_Addr_25[29] = \<const0> ;
assign LMB_Data_Addr_25[30] = \<const0> ;
assign LMB_Data_Addr_25[31] = \<const0> ;
assign LMB_Data_Addr_26[0] = \<const0> ;
assign LMB_Data_Addr_26[1] = \<const0> ;
assign LMB_Data_Addr_26[2] = \<const0> ;
assign LMB_Data_Addr_26[3] = \<const0> ;
assign LMB_Data_Addr_26[4] = \<const0> ;
assign LMB_Data_Addr_26[5] = \<const0> ;
assign LMB_Data_Addr_26[6] = \<const0> ;
assign LMB_Data_Addr_26[7] = \<const0> ;
assign LMB_Data_Addr_26[8] = \<const0> ;
assign LMB_Data_Addr_26[9] = \<const0> ;
assign LMB_Data_Addr_26[10] = \<const0> ;
assign LMB_Data_Addr_26[11] = \<const0> ;
assign LMB_Data_Addr_26[12] = \<const0> ;
assign LMB_Data_Addr_26[13] = \<const0> ;
assign LMB_Data_Addr_26[14] = \<const0> ;
assign LMB_Data_Addr_26[15] = \<const0> ;
assign LMB_Data_Addr_26[16] = \<const0> ;
assign LMB_Data_Addr_26[17] = \<const0> ;
assign LMB_Data_Addr_26[18] = \<const0> ;
assign LMB_Data_Addr_26[19] = \<const0> ;
assign LMB_Data_Addr_26[20] = \<const0> ;
assign LMB_Data_Addr_26[21] = \<const0> ;
assign LMB_Data_Addr_26[22] = \<const0> ;
assign LMB_Data_Addr_26[23] = \<const0> ;
assign LMB_Data_Addr_26[24] = \<const0> ;
assign LMB_Data_Addr_26[25] = \<const0> ;
assign LMB_Data_Addr_26[26] = \<const0> ;
assign LMB_Data_Addr_26[27] = \<const0> ;
assign LMB_Data_Addr_26[28] = \<const0> ;
assign LMB_Data_Addr_26[29] = \<const0> ;
assign LMB_Data_Addr_26[30] = \<const0> ;
assign LMB_Data_Addr_26[31] = \<const0> ;
assign LMB_Data_Addr_27[0] = \<const0> ;
assign LMB_Data_Addr_27[1] = \<const0> ;
assign LMB_Data_Addr_27[2] = \<const0> ;
assign LMB_Data_Addr_27[3] = \<const0> ;
assign LMB_Data_Addr_27[4] = \<const0> ;
assign LMB_Data_Addr_27[5] = \<const0> ;
assign LMB_Data_Addr_27[6] = \<const0> ;
assign LMB_Data_Addr_27[7] = \<const0> ;
assign LMB_Data_Addr_27[8] = \<const0> ;
assign LMB_Data_Addr_27[9] = \<const0> ;
assign LMB_Data_Addr_27[10] = \<const0> ;
assign LMB_Data_Addr_27[11] = \<const0> ;
assign LMB_Data_Addr_27[12] = \<const0> ;
assign LMB_Data_Addr_27[13] = \<const0> ;
assign LMB_Data_Addr_27[14] = \<const0> ;
assign LMB_Data_Addr_27[15] = \<const0> ;
assign LMB_Data_Addr_27[16] = \<const0> ;
assign LMB_Data_Addr_27[17] = \<const0> ;
assign LMB_Data_Addr_27[18] = \<const0> ;
assign LMB_Data_Addr_27[19] = \<const0> ;
assign LMB_Data_Addr_27[20] = \<const0> ;
assign LMB_Data_Addr_27[21] = \<const0> ;
assign LMB_Data_Addr_27[22] = \<const0> ;
assign LMB_Data_Addr_27[23] = \<const0> ;
assign LMB_Data_Addr_27[24] = \<const0> ;
assign LMB_Data_Addr_27[25] = \<const0> ;
assign LMB_Data_Addr_27[26] = \<const0> ;
assign LMB_Data_Addr_27[27] = \<const0> ;
assign LMB_Data_Addr_27[28] = \<const0> ;
assign LMB_Data_Addr_27[29] = \<const0> ;
assign LMB_Data_Addr_27[30] = \<const0> ;
assign LMB_Data_Addr_27[31] = \<const0> ;
assign LMB_Data_Addr_28[0] = \<const0> ;
assign LMB_Data_Addr_28[1] = \<const0> ;
assign LMB_Data_Addr_28[2] = \<const0> ;
assign LMB_Data_Addr_28[3] = \<const0> ;
assign LMB_Data_Addr_28[4] = \<const0> ;
assign LMB_Data_Addr_28[5] = \<const0> ;
assign LMB_Data_Addr_28[6] = \<const0> ;
assign LMB_Data_Addr_28[7] = \<const0> ;
assign LMB_Data_Addr_28[8] = \<const0> ;
assign LMB_Data_Addr_28[9] = \<const0> ;
assign LMB_Data_Addr_28[10] = \<const0> ;
assign LMB_Data_Addr_28[11] = \<const0> ;
assign LMB_Data_Addr_28[12] = \<const0> ;
assign LMB_Data_Addr_28[13] = \<const0> ;
assign LMB_Data_Addr_28[14] = \<const0> ;
assign LMB_Data_Addr_28[15] = \<const0> ;
assign LMB_Data_Addr_28[16] = \<const0> ;
assign LMB_Data_Addr_28[17] = \<const0> ;
assign LMB_Data_Addr_28[18] = \<const0> ;
assign LMB_Data_Addr_28[19] = \<const0> ;
assign LMB_Data_Addr_28[20] = \<const0> ;
assign LMB_Data_Addr_28[21] = \<const0> ;
assign LMB_Data_Addr_28[22] = \<const0> ;
assign LMB_Data_Addr_28[23] = \<const0> ;
assign LMB_Data_Addr_28[24] = \<const0> ;
assign LMB_Data_Addr_28[25] = \<const0> ;
assign LMB_Data_Addr_28[26] = \<const0> ;
assign LMB_Data_Addr_28[27] = \<const0> ;
assign LMB_Data_Addr_28[28] = \<const0> ;
assign LMB_Data_Addr_28[29] = \<const0> ;
assign LMB_Data_Addr_28[30] = \<const0> ;
assign LMB_Data_Addr_28[31] = \<const0> ;
assign LMB_Data_Addr_29[0] = \<const0> ;
assign LMB_Data_Addr_29[1] = \<const0> ;
assign LMB_Data_Addr_29[2] = \<const0> ;
assign LMB_Data_Addr_29[3] = \<const0> ;
assign LMB_Data_Addr_29[4] = \<const0> ;
assign LMB_Data_Addr_29[5] = \<const0> ;
assign LMB_Data_Addr_29[6] = \<const0> ;
assign LMB_Data_Addr_29[7] = \<const0> ;
assign LMB_Data_Addr_29[8] = \<const0> ;
assign LMB_Data_Addr_29[9] = \<const0> ;
assign LMB_Data_Addr_29[10] = \<const0> ;
assign LMB_Data_Addr_29[11] = \<const0> ;
assign LMB_Data_Addr_29[12] = \<const0> ;
assign LMB_Data_Addr_29[13] = \<const0> ;
assign LMB_Data_Addr_29[14] = \<const0> ;
assign LMB_Data_Addr_29[15] = \<const0> ;
assign LMB_Data_Addr_29[16] = \<const0> ;
assign LMB_Data_Addr_29[17] = \<const0> ;
assign LMB_Data_Addr_29[18] = \<const0> ;
assign LMB_Data_Addr_29[19] = \<const0> ;
assign LMB_Data_Addr_29[20] = \<const0> ;
assign LMB_Data_Addr_29[21] = \<const0> ;
assign LMB_Data_Addr_29[22] = \<const0> ;
assign LMB_Data_Addr_29[23] = \<const0> ;
assign LMB_Data_Addr_29[24] = \<const0> ;
assign LMB_Data_Addr_29[25] = \<const0> ;
assign LMB_Data_Addr_29[26] = \<const0> ;
assign LMB_Data_Addr_29[27] = \<const0> ;
assign LMB_Data_Addr_29[28] = \<const0> ;
assign LMB_Data_Addr_29[29] = \<const0> ;
assign LMB_Data_Addr_29[30] = \<const0> ;
assign LMB_Data_Addr_29[31] = \<const0> ;
assign LMB_Data_Addr_3[0] = \<const0> ;
assign LMB_Data_Addr_3[1] = \<const0> ;
assign LMB_Data_Addr_3[2] = \<const0> ;
assign LMB_Data_Addr_3[3] = \<const0> ;
assign LMB_Data_Addr_3[4] = \<const0> ;
assign LMB_Data_Addr_3[5] = \<const0> ;
assign LMB_Data_Addr_3[6] = \<const0> ;
assign LMB_Data_Addr_3[7] = \<const0> ;
assign LMB_Data_Addr_3[8] = \<const0> ;
assign LMB_Data_Addr_3[9] = \<const0> ;
assign LMB_Data_Addr_3[10] = \<const0> ;
assign LMB_Data_Addr_3[11] = \<const0> ;
assign LMB_Data_Addr_3[12] = \<const0> ;
assign LMB_Data_Addr_3[13] = \<const0> ;
assign LMB_Data_Addr_3[14] = \<const0> ;
assign LMB_Data_Addr_3[15] = \<const0> ;
assign LMB_Data_Addr_3[16] = \<const0> ;
assign LMB_Data_Addr_3[17] = \<const0> ;
assign LMB_Data_Addr_3[18] = \<const0> ;
assign LMB_Data_Addr_3[19] = \<const0> ;
assign LMB_Data_Addr_3[20] = \<const0> ;
assign LMB_Data_Addr_3[21] = \<const0> ;
assign LMB_Data_Addr_3[22] = \<const0> ;
assign LMB_Data_Addr_3[23] = \<const0> ;
assign LMB_Data_Addr_3[24] = \<const0> ;
assign LMB_Data_Addr_3[25] = \<const0> ;
assign LMB_Data_Addr_3[26] = \<const0> ;
assign LMB_Data_Addr_3[27] = \<const0> ;
assign LMB_Data_Addr_3[28] = \<const0> ;
assign LMB_Data_Addr_3[29] = \<const0> ;
assign LMB_Data_Addr_3[30] = \<const0> ;
assign LMB_Data_Addr_3[31] = \<const0> ;
assign LMB_Data_Addr_30[0] = \<const0> ;
assign LMB_Data_Addr_30[1] = \<const0> ;
assign LMB_Data_Addr_30[2] = \<const0> ;
assign LMB_Data_Addr_30[3] = \<const0> ;
assign LMB_Data_Addr_30[4] = \<const0> ;
assign LMB_Data_Addr_30[5] = \<const0> ;
assign LMB_Data_Addr_30[6] = \<const0> ;
assign LMB_Data_Addr_30[7] = \<const0> ;
assign LMB_Data_Addr_30[8] = \<const0> ;
assign LMB_Data_Addr_30[9] = \<const0> ;
assign LMB_Data_Addr_30[10] = \<const0> ;
assign LMB_Data_Addr_30[11] = \<const0> ;
assign LMB_Data_Addr_30[12] = \<const0> ;
assign LMB_Data_Addr_30[13] = \<const0> ;
assign LMB_Data_Addr_30[14] = \<const0> ;
assign LMB_Data_Addr_30[15] = \<const0> ;
assign LMB_Data_Addr_30[16] = \<const0> ;
assign LMB_Data_Addr_30[17] = \<const0> ;
assign LMB_Data_Addr_30[18] = \<const0> ;
assign LMB_Data_Addr_30[19] = \<const0> ;
assign LMB_Data_Addr_30[20] = \<const0> ;
assign LMB_Data_Addr_30[21] = \<const0> ;
assign LMB_Data_Addr_30[22] = \<const0> ;
assign LMB_Data_Addr_30[23] = \<const0> ;
assign LMB_Data_Addr_30[24] = \<const0> ;
assign LMB_Data_Addr_30[25] = \<const0> ;
assign LMB_Data_Addr_30[26] = \<const0> ;
assign LMB_Data_Addr_30[27] = \<const0> ;
assign LMB_Data_Addr_30[28] = \<const0> ;
assign LMB_Data_Addr_30[29] = \<const0> ;
assign LMB_Data_Addr_30[30] = \<const0> ;
assign LMB_Data_Addr_30[31] = \<const0> ;
assign LMB_Data_Addr_31[0] = \<const0> ;
assign LMB_Data_Addr_31[1] = \<const0> ;
assign LMB_Data_Addr_31[2] = \<const0> ;
assign LMB_Data_Addr_31[3] = \<const0> ;
assign LMB_Data_Addr_31[4] = \<const0> ;
assign LMB_Data_Addr_31[5] = \<const0> ;
assign LMB_Data_Addr_31[6] = \<const0> ;
assign LMB_Data_Addr_31[7] = \<const0> ;
assign LMB_Data_Addr_31[8] = \<const0> ;
assign LMB_Data_Addr_31[9] = \<const0> ;
assign LMB_Data_Addr_31[10] = \<const0> ;
assign LMB_Data_Addr_31[11] = \<const0> ;
assign LMB_Data_Addr_31[12] = \<const0> ;
assign LMB_Data_Addr_31[13] = \<const0> ;
assign LMB_Data_Addr_31[14] = \<const0> ;
assign LMB_Data_Addr_31[15] = \<const0> ;
assign LMB_Data_Addr_31[16] = \<const0> ;
assign LMB_Data_Addr_31[17] = \<const0> ;
assign LMB_Data_Addr_31[18] = \<const0> ;
assign LMB_Data_Addr_31[19] = \<const0> ;
assign LMB_Data_Addr_31[20] = \<const0> ;
assign LMB_Data_Addr_31[21] = \<const0> ;
assign LMB_Data_Addr_31[22] = \<const0> ;
assign LMB_Data_Addr_31[23] = \<const0> ;
assign LMB_Data_Addr_31[24] = \<const0> ;
assign LMB_Data_Addr_31[25] = \<const0> ;
assign LMB_Data_Addr_31[26] = \<const0> ;
assign LMB_Data_Addr_31[27] = \<const0> ;
assign LMB_Data_Addr_31[28] = \<const0> ;
assign LMB_Data_Addr_31[29] = \<const0> ;
assign LMB_Data_Addr_31[30] = \<const0> ;
assign LMB_Data_Addr_31[31] = \<const0> ;
assign LMB_Data_Addr_4[0] = \<const0> ;
assign LMB_Data_Addr_4[1] = \<const0> ;
assign LMB_Data_Addr_4[2] = \<const0> ;
assign LMB_Data_Addr_4[3] = \<const0> ;
assign LMB_Data_Addr_4[4] = \<const0> ;
assign LMB_Data_Addr_4[5] = \<const0> ;
assign LMB_Data_Addr_4[6] = \<const0> ;
assign LMB_Data_Addr_4[7] = \<const0> ;
assign LMB_Data_Addr_4[8] = \<const0> ;
assign LMB_Data_Addr_4[9] = \<const0> ;
assign LMB_Data_Addr_4[10] = \<const0> ;
assign LMB_Data_Addr_4[11] = \<const0> ;
assign LMB_Data_Addr_4[12] = \<const0> ;
assign LMB_Data_Addr_4[13] = \<const0> ;
assign LMB_Data_Addr_4[14] = \<const0> ;
assign LMB_Data_Addr_4[15] = \<const0> ;
assign LMB_Data_Addr_4[16] = \<const0> ;
assign LMB_Data_Addr_4[17] = \<const0> ;
assign LMB_Data_Addr_4[18] = \<const0> ;
assign LMB_Data_Addr_4[19] = \<const0> ;
assign LMB_Data_Addr_4[20] = \<const0> ;
assign LMB_Data_Addr_4[21] = \<const0> ;
assign LMB_Data_Addr_4[22] = \<const0> ;
assign LMB_Data_Addr_4[23] = \<const0> ;
assign LMB_Data_Addr_4[24] = \<const0> ;
assign LMB_Data_Addr_4[25] = \<const0> ;
assign LMB_Data_Addr_4[26] = \<const0> ;
assign LMB_Data_Addr_4[27] = \<const0> ;
assign LMB_Data_Addr_4[28] = \<const0> ;
assign LMB_Data_Addr_4[29] = \<const0> ;
assign LMB_Data_Addr_4[30] = \<const0> ;
assign LMB_Data_Addr_4[31] = \<const0> ;
assign LMB_Data_Addr_5[0] = \<const0> ;
assign LMB_Data_Addr_5[1] = \<const0> ;
assign LMB_Data_Addr_5[2] = \<const0> ;
assign LMB_Data_Addr_5[3] = \<const0> ;
assign LMB_Data_Addr_5[4] = \<const0> ;
assign LMB_Data_Addr_5[5] = \<const0> ;
assign LMB_Data_Addr_5[6] = \<const0> ;
assign LMB_Data_Addr_5[7] = \<const0> ;
assign LMB_Data_Addr_5[8] = \<const0> ;
assign LMB_Data_Addr_5[9] = \<const0> ;
assign LMB_Data_Addr_5[10] = \<const0> ;
assign LMB_Data_Addr_5[11] = \<const0> ;
assign LMB_Data_Addr_5[12] = \<const0> ;
assign LMB_Data_Addr_5[13] = \<const0> ;
assign LMB_Data_Addr_5[14] = \<const0> ;
assign LMB_Data_Addr_5[15] = \<const0> ;
assign LMB_Data_Addr_5[16] = \<const0> ;
assign LMB_Data_Addr_5[17] = \<const0> ;
assign LMB_Data_Addr_5[18] = \<const0> ;
assign LMB_Data_Addr_5[19] = \<const0> ;
assign LMB_Data_Addr_5[20] = \<const0> ;
assign LMB_Data_Addr_5[21] = \<const0> ;
assign LMB_Data_Addr_5[22] = \<const0> ;
assign LMB_Data_Addr_5[23] = \<const0> ;
assign LMB_Data_Addr_5[24] = \<const0> ;
assign LMB_Data_Addr_5[25] = \<const0> ;
assign LMB_Data_Addr_5[26] = \<const0> ;
assign LMB_Data_Addr_5[27] = \<const0> ;
assign LMB_Data_Addr_5[28] = \<const0> ;
assign LMB_Data_Addr_5[29] = \<const0> ;
assign LMB_Data_Addr_5[30] = \<const0> ;
assign LMB_Data_Addr_5[31] = \<const0> ;
assign LMB_Data_Addr_6[0] = \<const0> ;
assign LMB_Data_Addr_6[1] = \<const0> ;
assign LMB_Data_Addr_6[2] = \<const0> ;
assign LMB_Data_Addr_6[3] = \<const0> ;
assign LMB_Data_Addr_6[4] = \<const0> ;
assign LMB_Data_Addr_6[5] = \<const0> ;
assign LMB_Data_Addr_6[6] = \<const0> ;
assign LMB_Data_Addr_6[7] = \<const0> ;
assign LMB_Data_Addr_6[8] = \<const0> ;
assign LMB_Data_Addr_6[9] = \<const0> ;
assign LMB_Data_Addr_6[10] = \<const0> ;
assign LMB_Data_Addr_6[11] = \<const0> ;
assign LMB_Data_Addr_6[12] = \<const0> ;
assign LMB_Data_Addr_6[13] = \<const0> ;
assign LMB_Data_Addr_6[14] = \<const0> ;
assign LMB_Data_Addr_6[15] = \<const0> ;
assign LMB_Data_Addr_6[16] = \<const0> ;
assign LMB_Data_Addr_6[17] = \<const0> ;
assign LMB_Data_Addr_6[18] = \<const0> ;
assign LMB_Data_Addr_6[19] = \<const0> ;
assign LMB_Data_Addr_6[20] = \<const0> ;
assign LMB_Data_Addr_6[21] = \<const0> ;
assign LMB_Data_Addr_6[22] = \<const0> ;
assign LMB_Data_Addr_6[23] = \<const0> ;
assign LMB_Data_Addr_6[24] = \<const0> ;
assign LMB_Data_Addr_6[25] = \<const0> ;
assign LMB_Data_Addr_6[26] = \<const0> ;
assign LMB_Data_Addr_6[27] = \<const0> ;
assign LMB_Data_Addr_6[28] = \<const0> ;
assign LMB_Data_Addr_6[29] = \<const0> ;
assign LMB_Data_Addr_6[30] = \<const0> ;
assign LMB_Data_Addr_6[31] = \<const0> ;
assign LMB_Data_Addr_7[0] = \<const0> ;
assign LMB_Data_Addr_7[1] = \<const0> ;
assign LMB_Data_Addr_7[2] = \<const0> ;
assign LMB_Data_Addr_7[3] = \<const0> ;
assign LMB_Data_Addr_7[4] = \<const0> ;
assign LMB_Data_Addr_7[5] = \<const0> ;
assign LMB_Data_Addr_7[6] = \<const0> ;
assign LMB_Data_Addr_7[7] = \<const0> ;
assign LMB_Data_Addr_7[8] = \<const0> ;
assign LMB_Data_Addr_7[9] = \<const0> ;
assign LMB_Data_Addr_7[10] = \<const0> ;
assign LMB_Data_Addr_7[11] = \<const0> ;
assign LMB_Data_Addr_7[12] = \<const0> ;
assign LMB_Data_Addr_7[13] = \<const0> ;
assign LMB_Data_Addr_7[14] = \<const0> ;
assign LMB_Data_Addr_7[15] = \<const0> ;
assign LMB_Data_Addr_7[16] = \<const0> ;
assign LMB_Data_Addr_7[17] = \<const0> ;
assign LMB_Data_Addr_7[18] = \<const0> ;
assign LMB_Data_Addr_7[19] = \<const0> ;
assign LMB_Data_Addr_7[20] = \<const0> ;
assign LMB_Data_Addr_7[21] = \<const0> ;
assign LMB_Data_Addr_7[22] = \<const0> ;
assign LMB_Data_Addr_7[23] = \<const0> ;
assign LMB_Data_Addr_7[24] = \<const0> ;
assign LMB_Data_Addr_7[25] = \<const0> ;
assign LMB_Data_Addr_7[26] = \<const0> ;
assign LMB_Data_Addr_7[27] = \<const0> ;
assign LMB_Data_Addr_7[28] = \<const0> ;
assign LMB_Data_Addr_7[29] = \<const0> ;
assign LMB_Data_Addr_7[30] = \<const0> ;
assign LMB_Data_Addr_7[31] = \<const0> ;
assign LMB_Data_Addr_8[0] = \<const0> ;
assign LMB_Data_Addr_8[1] = \<const0> ;
assign LMB_Data_Addr_8[2] = \<const0> ;
assign LMB_Data_Addr_8[3] = \<const0> ;
assign LMB_Data_Addr_8[4] = \<const0> ;
assign LMB_Data_Addr_8[5] = \<const0> ;
assign LMB_Data_Addr_8[6] = \<const0> ;
assign LMB_Data_Addr_8[7] = \<const0> ;
assign LMB_Data_Addr_8[8] = \<const0> ;
assign LMB_Data_Addr_8[9] = \<const0> ;
assign LMB_Data_Addr_8[10] = \<const0> ;
assign LMB_Data_Addr_8[11] = \<const0> ;
assign LMB_Data_Addr_8[12] = \<const0> ;
assign LMB_Data_Addr_8[13] = \<const0> ;
assign LMB_Data_Addr_8[14] = \<const0> ;
assign LMB_Data_Addr_8[15] = \<const0> ;
assign LMB_Data_Addr_8[16] = \<const0> ;
assign LMB_Data_Addr_8[17] = \<const0> ;
assign LMB_Data_Addr_8[18] = \<const0> ;
assign LMB_Data_Addr_8[19] = \<const0> ;
assign LMB_Data_Addr_8[20] = \<const0> ;
assign LMB_Data_Addr_8[21] = \<const0> ;
assign LMB_Data_Addr_8[22] = \<const0> ;
assign LMB_Data_Addr_8[23] = \<const0> ;
assign LMB_Data_Addr_8[24] = \<const0> ;
assign LMB_Data_Addr_8[25] = \<const0> ;
assign LMB_Data_Addr_8[26] = \<const0> ;
assign LMB_Data_Addr_8[27] = \<const0> ;
assign LMB_Data_Addr_8[28] = \<const0> ;
assign LMB_Data_Addr_8[29] = \<const0> ;
assign LMB_Data_Addr_8[30] = \<const0> ;
assign LMB_Data_Addr_8[31] = \<const0> ;
assign LMB_Data_Addr_9[0] = \<const0> ;
assign LMB_Data_Addr_9[1] = \<const0> ;
assign LMB_Data_Addr_9[2] = \<const0> ;
assign LMB_Data_Addr_9[3] = \<const0> ;
assign LMB_Data_Addr_9[4] = \<const0> ;
assign LMB_Data_Addr_9[5] = \<const0> ;
assign LMB_Data_Addr_9[6] = \<const0> ;
assign LMB_Data_Addr_9[7] = \<const0> ;
assign LMB_Data_Addr_9[8] = \<const0> ;
assign LMB_Data_Addr_9[9] = \<const0> ;
assign LMB_Data_Addr_9[10] = \<const0> ;
assign LMB_Data_Addr_9[11] = \<const0> ;
assign LMB_Data_Addr_9[12] = \<const0> ;
assign LMB_Data_Addr_9[13] = \<const0> ;
assign LMB_Data_Addr_9[14] = \<const0> ;
assign LMB_Data_Addr_9[15] = \<const0> ;
assign LMB_Data_Addr_9[16] = \<const0> ;
assign LMB_Data_Addr_9[17] = \<const0> ;
assign LMB_Data_Addr_9[18] = \<const0> ;
assign LMB_Data_Addr_9[19] = \<const0> ;
assign LMB_Data_Addr_9[20] = \<const0> ;
assign LMB_Data_Addr_9[21] = \<const0> ;
assign LMB_Data_Addr_9[22] = \<const0> ;
assign LMB_Data_Addr_9[23] = \<const0> ;
assign LMB_Data_Addr_9[24] = \<const0> ;
assign LMB_Data_Addr_9[25] = \<const0> ;
assign LMB_Data_Addr_9[26] = \<const0> ;
assign LMB_Data_Addr_9[27] = \<const0> ;
assign LMB_Data_Addr_9[28] = \<const0> ;
assign LMB_Data_Addr_9[29] = \<const0> ;
assign LMB_Data_Addr_9[30] = \<const0> ;
assign LMB_Data_Addr_9[31] = \<const0> ;
assign LMB_Data_Write_0[0] = \<const0> ;
assign LMB_Data_Write_0[1] = \<const0> ;
assign LMB_Data_Write_0[2] = \<const0> ;
assign LMB_Data_Write_0[3] = \<const0> ;
assign LMB_Data_Write_0[4] = \<const0> ;
assign LMB_Data_Write_0[5] = \<const0> ;
assign LMB_Data_Write_0[6] = \<const0> ;
assign LMB_Data_Write_0[7] = \<const0> ;
assign LMB_Data_Write_0[8] = \<const0> ;
assign LMB_Data_Write_0[9] = \<const0> ;
assign LMB_Data_Write_0[10] = \<const0> ;
assign LMB_Data_Write_0[11] = \<const0> ;
assign LMB_Data_Write_0[12] = \<const0> ;
assign LMB_Data_Write_0[13] = \<const0> ;
assign LMB_Data_Write_0[14] = \<const0> ;
assign LMB_Data_Write_0[15] = \<const0> ;
assign LMB_Data_Write_0[16] = \<const0> ;
assign LMB_Data_Write_0[17] = \<const0> ;
assign LMB_Data_Write_0[18] = \<const0> ;
assign LMB_Data_Write_0[19] = \<const0> ;
assign LMB_Data_Write_0[20] = \<const0> ;
assign LMB_Data_Write_0[21] = \<const0> ;
assign LMB_Data_Write_0[22] = \<const0> ;
assign LMB_Data_Write_0[23] = \<const0> ;
assign LMB_Data_Write_0[24] = \<const0> ;
assign LMB_Data_Write_0[25] = \<const0> ;
assign LMB_Data_Write_0[26] = \<const0> ;
assign LMB_Data_Write_0[27] = \<const0> ;
assign LMB_Data_Write_0[28] = \<const0> ;
assign LMB_Data_Write_0[29] = \<const0> ;
assign LMB_Data_Write_0[30] = \<const0> ;
assign LMB_Data_Write_0[31] = \<const0> ;
assign LMB_Data_Write_1[0] = \<const0> ;
assign LMB_Data_Write_1[1] = \<const0> ;
assign LMB_Data_Write_1[2] = \<const0> ;
assign LMB_Data_Write_1[3] = \<const0> ;
assign LMB_Data_Write_1[4] = \<const0> ;
assign LMB_Data_Write_1[5] = \<const0> ;
assign LMB_Data_Write_1[6] = \<const0> ;
assign LMB_Data_Write_1[7] = \<const0> ;
assign LMB_Data_Write_1[8] = \<const0> ;
assign LMB_Data_Write_1[9] = \<const0> ;
assign LMB_Data_Write_1[10] = \<const0> ;
assign LMB_Data_Write_1[11] = \<const0> ;
assign LMB_Data_Write_1[12] = \<const0> ;
assign LMB_Data_Write_1[13] = \<const0> ;
assign LMB_Data_Write_1[14] = \<const0> ;
assign LMB_Data_Write_1[15] = \<const0> ;
assign LMB_Data_Write_1[16] = \<const0> ;
assign LMB_Data_Write_1[17] = \<const0> ;
assign LMB_Data_Write_1[18] = \<const0> ;
assign LMB_Data_Write_1[19] = \<const0> ;
assign LMB_Data_Write_1[20] = \<const0> ;
assign LMB_Data_Write_1[21] = \<const0> ;
assign LMB_Data_Write_1[22] = \<const0> ;
assign LMB_Data_Write_1[23] = \<const0> ;
assign LMB_Data_Write_1[24] = \<const0> ;
assign LMB_Data_Write_1[25] = \<const0> ;
assign LMB_Data_Write_1[26] = \<const0> ;
assign LMB_Data_Write_1[27] = \<const0> ;
assign LMB_Data_Write_1[28] = \<const0> ;
assign LMB_Data_Write_1[29] = \<const0> ;
assign LMB_Data_Write_1[30] = \<const0> ;
assign LMB_Data_Write_1[31] = \<const0> ;
assign LMB_Data_Write_10[0] = \<const0> ;
assign LMB_Data_Write_10[1] = \<const0> ;
assign LMB_Data_Write_10[2] = \<const0> ;
assign LMB_Data_Write_10[3] = \<const0> ;
assign LMB_Data_Write_10[4] = \<const0> ;
assign LMB_Data_Write_10[5] = \<const0> ;
assign LMB_Data_Write_10[6] = \<const0> ;
assign LMB_Data_Write_10[7] = \<const0> ;
assign LMB_Data_Write_10[8] = \<const0> ;
assign LMB_Data_Write_10[9] = \<const0> ;
assign LMB_Data_Write_10[10] = \<const0> ;
assign LMB_Data_Write_10[11] = \<const0> ;
assign LMB_Data_Write_10[12] = \<const0> ;
assign LMB_Data_Write_10[13] = \<const0> ;
assign LMB_Data_Write_10[14] = \<const0> ;
assign LMB_Data_Write_10[15] = \<const0> ;
assign LMB_Data_Write_10[16] = \<const0> ;
assign LMB_Data_Write_10[17] = \<const0> ;
assign LMB_Data_Write_10[18] = \<const0> ;
assign LMB_Data_Write_10[19] = \<const0> ;
assign LMB_Data_Write_10[20] = \<const0> ;
assign LMB_Data_Write_10[21] = \<const0> ;
assign LMB_Data_Write_10[22] = \<const0> ;
assign LMB_Data_Write_10[23] = \<const0> ;
assign LMB_Data_Write_10[24] = \<const0> ;
assign LMB_Data_Write_10[25] = \<const0> ;
assign LMB_Data_Write_10[26] = \<const0> ;
assign LMB_Data_Write_10[27] = \<const0> ;
assign LMB_Data_Write_10[28] = \<const0> ;
assign LMB_Data_Write_10[29] = \<const0> ;
assign LMB_Data_Write_10[30] = \<const0> ;
assign LMB_Data_Write_10[31] = \<const0> ;
assign LMB_Data_Write_11[0] = \<const0> ;
assign LMB_Data_Write_11[1] = \<const0> ;
assign LMB_Data_Write_11[2] = \<const0> ;
assign LMB_Data_Write_11[3] = \<const0> ;
assign LMB_Data_Write_11[4] = \<const0> ;
assign LMB_Data_Write_11[5] = \<const0> ;
assign LMB_Data_Write_11[6] = \<const0> ;
assign LMB_Data_Write_11[7] = \<const0> ;
assign LMB_Data_Write_11[8] = \<const0> ;
assign LMB_Data_Write_11[9] = \<const0> ;
assign LMB_Data_Write_11[10] = \<const0> ;
assign LMB_Data_Write_11[11] = \<const0> ;
assign LMB_Data_Write_11[12] = \<const0> ;
assign LMB_Data_Write_11[13] = \<const0> ;
assign LMB_Data_Write_11[14] = \<const0> ;
assign LMB_Data_Write_11[15] = \<const0> ;
assign LMB_Data_Write_11[16] = \<const0> ;
assign LMB_Data_Write_11[17] = \<const0> ;
assign LMB_Data_Write_11[18] = \<const0> ;
assign LMB_Data_Write_11[19] = \<const0> ;
assign LMB_Data_Write_11[20] = \<const0> ;
assign LMB_Data_Write_11[21] = \<const0> ;
assign LMB_Data_Write_11[22] = \<const0> ;
assign LMB_Data_Write_11[23] = \<const0> ;
assign LMB_Data_Write_11[24] = \<const0> ;
assign LMB_Data_Write_11[25] = \<const0> ;
assign LMB_Data_Write_11[26] = \<const0> ;
assign LMB_Data_Write_11[27] = \<const0> ;
assign LMB_Data_Write_11[28] = \<const0> ;
assign LMB_Data_Write_11[29] = \<const0> ;
assign LMB_Data_Write_11[30] = \<const0> ;
assign LMB_Data_Write_11[31] = \<const0> ;
assign LMB_Data_Write_12[0] = \<const0> ;
assign LMB_Data_Write_12[1] = \<const0> ;
assign LMB_Data_Write_12[2] = \<const0> ;
assign LMB_Data_Write_12[3] = \<const0> ;
assign LMB_Data_Write_12[4] = \<const0> ;
assign LMB_Data_Write_12[5] = \<const0> ;
assign LMB_Data_Write_12[6] = \<const0> ;
assign LMB_Data_Write_12[7] = \<const0> ;
assign LMB_Data_Write_12[8] = \<const0> ;
assign LMB_Data_Write_12[9] = \<const0> ;
assign LMB_Data_Write_12[10] = \<const0> ;
assign LMB_Data_Write_12[11] = \<const0> ;
assign LMB_Data_Write_12[12] = \<const0> ;
assign LMB_Data_Write_12[13] = \<const0> ;
assign LMB_Data_Write_12[14] = \<const0> ;
assign LMB_Data_Write_12[15] = \<const0> ;
assign LMB_Data_Write_12[16] = \<const0> ;
assign LMB_Data_Write_12[17] = \<const0> ;
assign LMB_Data_Write_12[18] = \<const0> ;
assign LMB_Data_Write_12[19] = \<const0> ;
assign LMB_Data_Write_12[20] = \<const0> ;
assign LMB_Data_Write_12[21] = \<const0> ;
assign LMB_Data_Write_12[22] = \<const0> ;
assign LMB_Data_Write_12[23] = \<const0> ;
assign LMB_Data_Write_12[24] = \<const0> ;
assign LMB_Data_Write_12[25] = \<const0> ;
assign LMB_Data_Write_12[26] = \<const0> ;
assign LMB_Data_Write_12[27] = \<const0> ;
assign LMB_Data_Write_12[28] = \<const0> ;
assign LMB_Data_Write_12[29] = \<const0> ;
assign LMB_Data_Write_12[30] = \<const0> ;
assign LMB_Data_Write_12[31] = \<const0> ;
assign LMB_Data_Write_13[0] = \<const0> ;
assign LMB_Data_Write_13[1] = \<const0> ;
assign LMB_Data_Write_13[2] = \<const0> ;
assign LMB_Data_Write_13[3] = \<const0> ;
assign LMB_Data_Write_13[4] = \<const0> ;
assign LMB_Data_Write_13[5] = \<const0> ;
assign LMB_Data_Write_13[6] = \<const0> ;
assign LMB_Data_Write_13[7] = \<const0> ;
assign LMB_Data_Write_13[8] = \<const0> ;
assign LMB_Data_Write_13[9] = \<const0> ;
assign LMB_Data_Write_13[10] = \<const0> ;
assign LMB_Data_Write_13[11] = \<const0> ;
assign LMB_Data_Write_13[12] = \<const0> ;
assign LMB_Data_Write_13[13] = \<const0> ;
assign LMB_Data_Write_13[14] = \<const0> ;
assign LMB_Data_Write_13[15] = \<const0> ;
assign LMB_Data_Write_13[16] = \<const0> ;
assign LMB_Data_Write_13[17] = \<const0> ;
assign LMB_Data_Write_13[18] = \<const0> ;
assign LMB_Data_Write_13[19] = \<const0> ;
assign LMB_Data_Write_13[20] = \<const0> ;
assign LMB_Data_Write_13[21] = \<const0> ;
assign LMB_Data_Write_13[22] = \<const0> ;
assign LMB_Data_Write_13[23] = \<const0> ;
assign LMB_Data_Write_13[24] = \<const0> ;
assign LMB_Data_Write_13[25] = \<const0> ;
assign LMB_Data_Write_13[26] = \<const0> ;
assign LMB_Data_Write_13[27] = \<const0> ;
assign LMB_Data_Write_13[28] = \<const0> ;
assign LMB_Data_Write_13[29] = \<const0> ;
assign LMB_Data_Write_13[30] = \<const0> ;
assign LMB_Data_Write_13[31] = \<const0> ;
assign LMB_Data_Write_14[0] = \<const0> ;
assign LMB_Data_Write_14[1] = \<const0> ;
assign LMB_Data_Write_14[2] = \<const0> ;
assign LMB_Data_Write_14[3] = \<const0> ;
assign LMB_Data_Write_14[4] = \<const0> ;
assign LMB_Data_Write_14[5] = \<const0> ;
assign LMB_Data_Write_14[6] = \<const0> ;
assign LMB_Data_Write_14[7] = \<const0> ;
assign LMB_Data_Write_14[8] = \<const0> ;
assign LMB_Data_Write_14[9] = \<const0> ;
assign LMB_Data_Write_14[10] = \<const0> ;
assign LMB_Data_Write_14[11] = \<const0> ;
assign LMB_Data_Write_14[12] = \<const0> ;
assign LMB_Data_Write_14[13] = \<const0> ;
assign LMB_Data_Write_14[14] = \<const0> ;
assign LMB_Data_Write_14[15] = \<const0> ;
assign LMB_Data_Write_14[16] = \<const0> ;
assign LMB_Data_Write_14[17] = \<const0> ;
assign LMB_Data_Write_14[18] = \<const0> ;
assign LMB_Data_Write_14[19] = \<const0> ;
assign LMB_Data_Write_14[20] = \<const0> ;
assign LMB_Data_Write_14[21] = \<const0> ;
assign LMB_Data_Write_14[22] = \<const0> ;
assign LMB_Data_Write_14[23] = \<const0> ;
assign LMB_Data_Write_14[24] = \<const0> ;
assign LMB_Data_Write_14[25] = \<const0> ;
assign LMB_Data_Write_14[26] = \<const0> ;
assign LMB_Data_Write_14[27] = \<const0> ;
assign LMB_Data_Write_14[28] = \<const0> ;
assign LMB_Data_Write_14[29] = \<const0> ;
assign LMB_Data_Write_14[30] = \<const0> ;
assign LMB_Data_Write_14[31] = \<const0> ;
assign LMB_Data_Write_15[0] = \<const0> ;
assign LMB_Data_Write_15[1] = \<const0> ;
assign LMB_Data_Write_15[2] = \<const0> ;
assign LMB_Data_Write_15[3] = \<const0> ;
assign LMB_Data_Write_15[4] = \<const0> ;
assign LMB_Data_Write_15[5] = \<const0> ;
assign LMB_Data_Write_15[6] = \<const0> ;
assign LMB_Data_Write_15[7] = \<const0> ;
assign LMB_Data_Write_15[8] = \<const0> ;
assign LMB_Data_Write_15[9] = \<const0> ;
assign LMB_Data_Write_15[10] = \<const0> ;
assign LMB_Data_Write_15[11] = \<const0> ;
assign LMB_Data_Write_15[12] = \<const0> ;
assign LMB_Data_Write_15[13] = \<const0> ;
assign LMB_Data_Write_15[14] = \<const0> ;
assign LMB_Data_Write_15[15] = \<const0> ;
assign LMB_Data_Write_15[16] = \<const0> ;
assign LMB_Data_Write_15[17] = \<const0> ;
assign LMB_Data_Write_15[18] = \<const0> ;
assign LMB_Data_Write_15[19] = \<const0> ;
assign LMB_Data_Write_15[20] = \<const0> ;
assign LMB_Data_Write_15[21] = \<const0> ;
assign LMB_Data_Write_15[22] = \<const0> ;
assign LMB_Data_Write_15[23] = \<const0> ;
assign LMB_Data_Write_15[24] = \<const0> ;
assign LMB_Data_Write_15[25] = \<const0> ;
assign LMB_Data_Write_15[26] = \<const0> ;
assign LMB_Data_Write_15[27] = \<const0> ;
assign LMB_Data_Write_15[28] = \<const0> ;
assign LMB_Data_Write_15[29] = \<const0> ;
assign LMB_Data_Write_15[30] = \<const0> ;
assign LMB_Data_Write_15[31] = \<const0> ;
assign LMB_Data_Write_16[0] = \<const0> ;
assign LMB_Data_Write_16[1] = \<const0> ;
assign LMB_Data_Write_16[2] = \<const0> ;
assign LMB_Data_Write_16[3] = \<const0> ;
assign LMB_Data_Write_16[4] = \<const0> ;
assign LMB_Data_Write_16[5] = \<const0> ;
assign LMB_Data_Write_16[6] = \<const0> ;
assign LMB_Data_Write_16[7] = \<const0> ;
assign LMB_Data_Write_16[8] = \<const0> ;
assign LMB_Data_Write_16[9] = \<const0> ;
assign LMB_Data_Write_16[10] = \<const0> ;
assign LMB_Data_Write_16[11] = \<const0> ;
assign LMB_Data_Write_16[12] = \<const0> ;
assign LMB_Data_Write_16[13] = \<const0> ;
assign LMB_Data_Write_16[14] = \<const0> ;
assign LMB_Data_Write_16[15] = \<const0> ;
assign LMB_Data_Write_16[16] = \<const0> ;
assign LMB_Data_Write_16[17] = \<const0> ;
assign LMB_Data_Write_16[18] = \<const0> ;
assign LMB_Data_Write_16[19] = \<const0> ;
assign LMB_Data_Write_16[20] = \<const0> ;
assign LMB_Data_Write_16[21] = \<const0> ;
assign LMB_Data_Write_16[22] = \<const0> ;
assign LMB_Data_Write_16[23] = \<const0> ;
assign LMB_Data_Write_16[24] = \<const0> ;
assign LMB_Data_Write_16[25] = \<const0> ;
assign LMB_Data_Write_16[26] = \<const0> ;
assign LMB_Data_Write_16[27] = \<const0> ;
assign LMB_Data_Write_16[28] = \<const0> ;
assign LMB_Data_Write_16[29] = \<const0> ;
assign LMB_Data_Write_16[30] = \<const0> ;
assign LMB_Data_Write_16[31] = \<const0> ;
assign LMB_Data_Write_17[0] = \<const0> ;
assign LMB_Data_Write_17[1] = \<const0> ;
assign LMB_Data_Write_17[2] = \<const0> ;
assign LMB_Data_Write_17[3] = \<const0> ;
assign LMB_Data_Write_17[4] = \<const0> ;
assign LMB_Data_Write_17[5] = \<const0> ;
assign LMB_Data_Write_17[6] = \<const0> ;
assign LMB_Data_Write_17[7] = \<const0> ;
assign LMB_Data_Write_17[8] = \<const0> ;
assign LMB_Data_Write_17[9] = \<const0> ;
assign LMB_Data_Write_17[10] = \<const0> ;
assign LMB_Data_Write_17[11] = \<const0> ;
assign LMB_Data_Write_17[12] = \<const0> ;
assign LMB_Data_Write_17[13] = \<const0> ;
assign LMB_Data_Write_17[14] = \<const0> ;
assign LMB_Data_Write_17[15] = \<const0> ;
assign LMB_Data_Write_17[16] = \<const0> ;
assign LMB_Data_Write_17[17] = \<const0> ;
assign LMB_Data_Write_17[18] = \<const0> ;
assign LMB_Data_Write_17[19] = \<const0> ;
assign LMB_Data_Write_17[20] = \<const0> ;
assign LMB_Data_Write_17[21] = \<const0> ;
assign LMB_Data_Write_17[22] = \<const0> ;
assign LMB_Data_Write_17[23] = \<const0> ;
assign LMB_Data_Write_17[24] = \<const0> ;
assign LMB_Data_Write_17[25] = \<const0> ;
assign LMB_Data_Write_17[26] = \<const0> ;
assign LMB_Data_Write_17[27] = \<const0> ;
assign LMB_Data_Write_17[28] = \<const0> ;
assign LMB_Data_Write_17[29] = \<const0> ;
assign LMB_Data_Write_17[30] = \<const0> ;
assign LMB_Data_Write_17[31] = \<const0> ;
assign LMB_Data_Write_18[0] = \<const0> ;
assign LMB_Data_Write_18[1] = \<const0> ;
assign LMB_Data_Write_18[2] = \<const0> ;
assign LMB_Data_Write_18[3] = \<const0> ;
assign LMB_Data_Write_18[4] = \<const0> ;
assign LMB_Data_Write_18[5] = \<const0> ;
assign LMB_Data_Write_18[6] = \<const0> ;
assign LMB_Data_Write_18[7] = \<const0> ;
assign LMB_Data_Write_18[8] = \<const0> ;
assign LMB_Data_Write_18[9] = \<const0> ;
assign LMB_Data_Write_18[10] = \<const0> ;
assign LMB_Data_Write_18[11] = \<const0> ;
assign LMB_Data_Write_18[12] = \<const0> ;
assign LMB_Data_Write_18[13] = \<const0> ;
assign LMB_Data_Write_18[14] = \<const0> ;
assign LMB_Data_Write_18[15] = \<const0> ;
assign LMB_Data_Write_18[16] = \<const0> ;
assign LMB_Data_Write_18[17] = \<const0> ;
assign LMB_Data_Write_18[18] = \<const0> ;
assign LMB_Data_Write_18[19] = \<const0> ;
assign LMB_Data_Write_18[20] = \<const0> ;
assign LMB_Data_Write_18[21] = \<const0> ;
assign LMB_Data_Write_18[22] = \<const0> ;
assign LMB_Data_Write_18[23] = \<const0> ;
assign LMB_Data_Write_18[24] = \<const0> ;
assign LMB_Data_Write_18[25] = \<const0> ;
assign LMB_Data_Write_18[26] = \<const0> ;
assign LMB_Data_Write_18[27] = \<const0> ;
assign LMB_Data_Write_18[28] = \<const0> ;
assign LMB_Data_Write_18[29] = \<const0> ;
assign LMB_Data_Write_18[30] = \<const0> ;
assign LMB_Data_Write_18[31] = \<const0> ;
assign LMB_Data_Write_19[0] = \<const0> ;
assign LMB_Data_Write_19[1] = \<const0> ;
assign LMB_Data_Write_19[2] = \<const0> ;
assign LMB_Data_Write_19[3] = \<const0> ;
assign LMB_Data_Write_19[4] = \<const0> ;
assign LMB_Data_Write_19[5] = \<const0> ;
assign LMB_Data_Write_19[6] = \<const0> ;
assign LMB_Data_Write_19[7] = \<const0> ;
assign LMB_Data_Write_19[8] = \<const0> ;
assign LMB_Data_Write_19[9] = \<const0> ;
assign LMB_Data_Write_19[10] = \<const0> ;
assign LMB_Data_Write_19[11] = \<const0> ;
assign LMB_Data_Write_19[12] = \<const0> ;
assign LMB_Data_Write_19[13] = \<const0> ;
assign LMB_Data_Write_19[14] = \<const0> ;
assign LMB_Data_Write_19[15] = \<const0> ;
assign LMB_Data_Write_19[16] = \<const0> ;
assign LMB_Data_Write_19[17] = \<const0> ;
assign LMB_Data_Write_19[18] = \<const0> ;
assign LMB_Data_Write_19[19] = \<const0> ;
assign LMB_Data_Write_19[20] = \<const0> ;
assign LMB_Data_Write_19[21] = \<const0> ;
assign LMB_Data_Write_19[22] = \<const0> ;
assign LMB_Data_Write_19[23] = \<const0> ;
assign LMB_Data_Write_19[24] = \<const0> ;
assign LMB_Data_Write_19[25] = \<const0> ;
assign LMB_Data_Write_19[26] = \<const0> ;
assign LMB_Data_Write_19[27] = \<const0> ;
assign LMB_Data_Write_19[28] = \<const0> ;
assign LMB_Data_Write_19[29] = \<const0> ;
assign LMB_Data_Write_19[30] = \<const0> ;
assign LMB_Data_Write_19[31] = \<const0> ;
assign LMB_Data_Write_2[0] = \<const0> ;
assign LMB_Data_Write_2[1] = \<const0> ;
assign LMB_Data_Write_2[2] = \<const0> ;
assign LMB_Data_Write_2[3] = \<const0> ;
assign LMB_Data_Write_2[4] = \<const0> ;
assign LMB_Data_Write_2[5] = \<const0> ;
assign LMB_Data_Write_2[6] = \<const0> ;
assign LMB_Data_Write_2[7] = \<const0> ;
assign LMB_Data_Write_2[8] = \<const0> ;
assign LMB_Data_Write_2[9] = \<const0> ;
assign LMB_Data_Write_2[10] = \<const0> ;
assign LMB_Data_Write_2[11] = \<const0> ;
assign LMB_Data_Write_2[12] = \<const0> ;
assign LMB_Data_Write_2[13] = \<const0> ;
assign LMB_Data_Write_2[14] = \<const0> ;
assign LMB_Data_Write_2[15] = \<const0> ;
assign LMB_Data_Write_2[16] = \<const0> ;
assign LMB_Data_Write_2[17] = \<const0> ;
assign LMB_Data_Write_2[18] = \<const0> ;
assign LMB_Data_Write_2[19] = \<const0> ;
assign LMB_Data_Write_2[20] = \<const0> ;
assign LMB_Data_Write_2[21] = \<const0> ;
assign LMB_Data_Write_2[22] = \<const0> ;
assign LMB_Data_Write_2[23] = \<const0> ;
assign LMB_Data_Write_2[24] = \<const0> ;
assign LMB_Data_Write_2[25] = \<const0> ;
assign LMB_Data_Write_2[26] = \<const0> ;
assign LMB_Data_Write_2[27] = \<const0> ;
assign LMB_Data_Write_2[28] = \<const0> ;
assign LMB_Data_Write_2[29] = \<const0> ;
assign LMB_Data_Write_2[30] = \<const0> ;
assign LMB_Data_Write_2[31] = \<const0> ;
assign LMB_Data_Write_20[0] = \<const0> ;
assign LMB_Data_Write_20[1] = \<const0> ;
assign LMB_Data_Write_20[2] = \<const0> ;
assign LMB_Data_Write_20[3] = \<const0> ;
assign LMB_Data_Write_20[4] = \<const0> ;
assign LMB_Data_Write_20[5] = \<const0> ;
assign LMB_Data_Write_20[6] = \<const0> ;
assign LMB_Data_Write_20[7] = \<const0> ;
assign LMB_Data_Write_20[8] = \<const0> ;
assign LMB_Data_Write_20[9] = \<const0> ;
assign LMB_Data_Write_20[10] = \<const0> ;
assign LMB_Data_Write_20[11] = \<const0> ;
assign LMB_Data_Write_20[12] = \<const0> ;
assign LMB_Data_Write_20[13] = \<const0> ;
assign LMB_Data_Write_20[14] = \<const0> ;
assign LMB_Data_Write_20[15] = \<const0> ;
assign LMB_Data_Write_20[16] = \<const0> ;
assign LMB_Data_Write_20[17] = \<const0> ;
assign LMB_Data_Write_20[18] = \<const0> ;
assign LMB_Data_Write_20[19] = \<const0> ;
assign LMB_Data_Write_20[20] = \<const0> ;
assign LMB_Data_Write_20[21] = \<const0> ;
assign LMB_Data_Write_20[22] = \<const0> ;
assign LMB_Data_Write_20[23] = \<const0> ;
assign LMB_Data_Write_20[24] = \<const0> ;
assign LMB_Data_Write_20[25] = \<const0> ;
assign LMB_Data_Write_20[26] = \<const0> ;
assign LMB_Data_Write_20[27] = \<const0> ;
assign LMB_Data_Write_20[28] = \<const0> ;
assign LMB_Data_Write_20[29] = \<const0> ;
assign LMB_Data_Write_20[30] = \<const0> ;
assign LMB_Data_Write_20[31] = \<const0> ;
assign LMB_Data_Write_21[0] = \<const0> ;
assign LMB_Data_Write_21[1] = \<const0> ;
assign LMB_Data_Write_21[2] = \<const0> ;
assign LMB_Data_Write_21[3] = \<const0> ;
assign LMB_Data_Write_21[4] = \<const0> ;
assign LMB_Data_Write_21[5] = \<const0> ;
assign LMB_Data_Write_21[6] = \<const0> ;
assign LMB_Data_Write_21[7] = \<const0> ;
assign LMB_Data_Write_21[8] = \<const0> ;
assign LMB_Data_Write_21[9] = \<const0> ;
assign LMB_Data_Write_21[10] = \<const0> ;
assign LMB_Data_Write_21[11] = \<const0> ;
assign LMB_Data_Write_21[12] = \<const0> ;
assign LMB_Data_Write_21[13] = \<const0> ;
assign LMB_Data_Write_21[14] = \<const0> ;
assign LMB_Data_Write_21[15] = \<const0> ;
assign LMB_Data_Write_21[16] = \<const0> ;
assign LMB_Data_Write_21[17] = \<const0> ;
assign LMB_Data_Write_21[18] = \<const0> ;
assign LMB_Data_Write_21[19] = \<const0> ;
assign LMB_Data_Write_21[20] = \<const0> ;
assign LMB_Data_Write_21[21] = \<const0> ;
assign LMB_Data_Write_21[22] = \<const0> ;
assign LMB_Data_Write_21[23] = \<const0> ;
assign LMB_Data_Write_21[24] = \<const0> ;
assign LMB_Data_Write_21[25] = \<const0> ;
assign LMB_Data_Write_21[26] = \<const0> ;
assign LMB_Data_Write_21[27] = \<const0> ;
assign LMB_Data_Write_21[28] = \<const0> ;
assign LMB_Data_Write_21[29] = \<const0> ;
assign LMB_Data_Write_21[30] = \<const0> ;
assign LMB_Data_Write_21[31] = \<const0> ;
assign LMB_Data_Write_22[0] = \<const0> ;
assign LMB_Data_Write_22[1] = \<const0> ;
assign LMB_Data_Write_22[2] = \<const0> ;
assign LMB_Data_Write_22[3] = \<const0> ;
assign LMB_Data_Write_22[4] = \<const0> ;
assign LMB_Data_Write_22[5] = \<const0> ;
assign LMB_Data_Write_22[6] = \<const0> ;
assign LMB_Data_Write_22[7] = \<const0> ;
assign LMB_Data_Write_22[8] = \<const0> ;
assign LMB_Data_Write_22[9] = \<const0> ;
assign LMB_Data_Write_22[10] = \<const0> ;
assign LMB_Data_Write_22[11] = \<const0> ;
assign LMB_Data_Write_22[12] = \<const0> ;
assign LMB_Data_Write_22[13] = \<const0> ;
assign LMB_Data_Write_22[14] = \<const0> ;
assign LMB_Data_Write_22[15] = \<const0> ;
assign LMB_Data_Write_22[16] = \<const0> ;
assign LMB_Data_Write_22[17] = \<const0> ;
assign LMB_Data_Write_22[18] = \<const0> ;
assign LMB_Data_Write_22[19] = \<const0> ;
assign LMB_Data_Write_22[20] = \<const0> ;
assign LMB_Data_Write_22[21] = \<const0> ;
assign LMB_Data_Write_22[22] = \<const0> ;
assign LMB_Data_Write_22[23] = \<const0> ;
assign LMB_Data_Write_22[24] = \<const0> ;
assign LMB_Data_Write_22[25] = \<const0> ;
assign LMB_Data_Write_22[26] = \<const0> ;
assign LMB_Data_Write_22[27] = \<const0> ;
assign LMB_Data_Write_22[28] = \<const0> ;
assign LMB_Data_Write_22[29] = \<const0> ;
assign LMB_Data_Write_22[30] = \<const0> ;
assign LMB_Data_Write_22[31] = \<const0> ;
assign LMB_Data_Write_23[0] = \<const0> ;
assign LMB_Data_Write_23[1] = \<const0> ;
assign LMB_Data_Write_23[2] = \<const0> ;
assign LMB_Data_Write_23[3] = \<const0> ;
assign LMB_Data_Write_23[4] = \<const0> ;
assign LMB_Data_Write_23[5] = \<const0> ;
assign LMB_Data_Write_23[6] = \<const0> ;
assign LMB_Data_Write_23[7] = \<const0> ;
assign LMB_Data_Write_23[8] = \<const0> ;
assign LMB_Data_Write_23[9] = \<const0> ;
assign LMB_Data_Write_23[10] = \<const0> ;
assign LMB_Data_Write_23[11] = \<const0> ;
assign LMB_Data_Write_23[12] = \<const0> ;
assign LMB_Data_Write_23[13] = \<const0> ;
assign LMB_Data_Write_23[14] = \<const0> ;
assign LMB_Data_Write_23[15] = \<const0> ;
assign LMB_Data_Write_23[16] = \<const0> ;
assign LMB_Data_Write_23[17] = \<const0> ;
assign LMB_Data_Write_23[18] = \<const0> ;
assign LMB_Data_Write_23[19] = \<const0> ;
assign LMB_Data_Write_23[20] = \<const0> ;
assign LMB_Data_Write_23[21] = \<const0> ;
assign LMB_Data_Write_23[22] = \<const0> ;
assign LMB_Data_Write_23[23] = \<const0> ;
assign LMB_Data_Write_23[24] = \<const0> ;
assign LMB_Data_Write_23[25] = \<const0> ;
assign LMB_Data_Write_23[26] = \<const0> ;
assign LMB_Data_Write_23[27] = \<const0> ;
assign LMB_Data_Write_23[28] = \<const0> ;
assign LMB_Data_Write_23[29] = \<const0> ;
assign LMB_Data_Write_23[30] = \<const0> ;
assign LMB_Data_Write_23[31] = \<const0> ;
assign LMB_Data_Write_24[0] = \<const0> ;
assign LMB_Data_Write_24[1] = \<const0> ;
assign LMB_Data_Write_24[2] = \<const0> ;
assign LMB_Data_Write_24[3] = \<const0> ;
assign LMB_Data_Write_24[4] = \<const0> ;
assign LMB_Data_Write_24[5] = \<const0> ;
assign LMB_Data_Write_24[6] = \<const0> ;
assign LMB_Data_Write_24[7] = \<const0> ;
assign LMB_Data_Write_24[8] = \<const0> ;
assign LMB_Data_Write_24[9] = \<const0> ;
assign LMB_Data_Write_24[10] = \<const0> ;
assign LMB_Data_Write_24[11] = \<const0> ;
assign LMB_Data_Write_24[12] = \<const0> ;
assign LMB_Data_Write_24[13] = \<const0> ;
assign LMB_Data_Write_24[14] = \<const0> ;
assign LMB_Data_Write_24[15] = \<const0> ;
assign LMB_Data_Write_24[16] = \<const0> ;
assign LMB_Data_Write_24[17] = \<const0> ;
assign LMB_Data_Write_24[18] = \<const0> ;
assign LMB_Data_Write_24[19] = \<const0> ;
assign LMB_Data_Write_24[20] = \<const0> ;
assign LMB_Data_Write_24[21] = \<const0> ;
assign LMB_Data_Write_24[22] = \<const0> ;
assign LMB_Data_Write_24[23] = \<const0> ;
assign LMB_Data_Write_24[24] = \<const0> ;
assign LMB_Data_Write_24[25] = \<const0> ;
assign LMB_Data_Write_24[26] = \<const0> ;
assign LMB_Data_Write_24[27] = \<const0> ;
assign LMB_Data_Write_24[28] = \<const0> ;
assign LMB_Data_Write_24[29] = \<const0> ;
assign LMB_Data_Write_24[30] = \<const0> ;
assign LMB_Data_Write_24[31] = \<const0> ;
assign LMB_Data_Write_25[0] = \<const0> ;
assign LMB_Data_Write_25[1] = \<const0> ;
assign LMB_Data_Write_25[2] = \<const0> ;
assign LMB_Data_Write_25[3] = \<const0> ;
assign LMB_Data_Write_25[4] = \<const0> ;
assign LMB_Data_Write_25[5] = \<const0> ;
assign LMB_Data_Write_25[6] = \<const0> ;
assign LMB_Data_Write_25[7] = \<const0> ;
assign LMB_Data_Write_25[8] = \<const0> ;
assign LMB_Data_Write_25[9] = \<const0> ;
assign LMB_Data_Write_25[10] = \<const0> ;
assign LMB_Data_Write_25[11] = \<const0> ;
assign LMB_Data_Write_25[12] = \<const0> ;
assign LMB_Data_Write_25[13] = \<const0> ;
assign LMB_Data_Write_25[14] = \<const0> ;
assign LMB_Data_Write_25[15] = \<const0> ;
assign LMB_Data_Write_25[16] = \<const0> ;
assign LMB_Data_Write_25[17] = \<const0> ;
assign LMB_Data_Write_25[18] = \<const0> ;
assign LMB_Data_Write_25[19] = \<const0> ;
assign LMB_Data_Write_25[20] = \<const0> ;
assign LMB_Data_Write_25[21] = \<const0> ;
assign LMB_Data_Write_25[22] = \<const0> ;
assign LMB_Data_Write_25[23] = \<const0> ;
assign LMB_Data_Write_25[24] = \<const0> ;
assign LMB_Data_Write_25[25] = \<const0> ;
assign LMB_Data_Write_25[26] = \<const0> ;
assign LMB_Data_Write_25[27] = \<const0> ;
assign LMB_Data_Write_25[28] = \<const0> ;
assign LMB_Data_Write_25[29] = \<const0> ;
assign LMB_Data_Write_25[30] = \<const0> ;
assign LMB_Data_Write_25[31] = \<const0> ;
assign LMB_Data_Write_26[0] = \<const0> ;
assign LMB_Data_Write_26[1] = \<const0> ;
assign LMB_Data_Write_26[2] = \<const0> ;
assign LMB_Data_Write_26[3] = \<const0> ;
assign LMB_Data_Write_26[4] = \<const0> ;
assign LMB_Data_Write_26[5] = \<const0> ;
assign LMB_Data_Write_26[6] = \<const0> ;
assign LMB_Data_Write_26[7] = \<const0> ;
assign LMB_Data_Write_26[8] = \<const0> ;
assign LMB_Data_Write_26[9] = \<const0> ;
assign LMB_Data_Write_26[10] = \<const0> ;
assign LMB_Data_Write_26[11] = \<const0> ;
assign LMB_Data_Write_26[12] = \<const0> ;
assign LMB_Data_Write_26[13] = \<const0> ;
assign LMB_Data_Write_26[14] = \<const0> ;
assign LMB_Data_Write_26[15] = \<const0> ;
assign LMB_Data_Write_26[16] = \<const0> ;
assign LMB_Data_Write_26[17] = \<const0> ;
assign LMB_Data_Write_26[18] = \<const0> ;
assign LMB_Data_Write_26[19] = \<const0> ;
assign LMB_Data_Write_26[20] = \<const0> ;
assign LMB_Data_Write_26[21] = \<const0> ;
assign LMB_Data_Write_26[22] = \<const0> ;
assign LMB_Data_Write_26[23] = \<const0> ;
assign LMB_Data_Write_26[24] = \<const0> ;
assign LMB_Data_Write_26[25] = \<const0> ;
assign LMB_Data_Write_26[26] = \<const0> ;
assign LMB_Data_Write_26[27] = \<const0> ;
assign LMB_Data_Write_26[28] = \<const0> ;
assign LMB_Data_Write_26[29] = \<const0> ;
assign LMB_Data_Write_26[30] = \<const0> ;
assign LMB_Data_Write_26[31] = \<const0> ;
assign LMB_Data_Write_27[0] = \<const0> ;
assign LMB_Data_Write_27[1] = \<const0> ;
assign LMB_Data_Write_27[2] = \<const0> ;
assign LMB_Data_Write_27[3] = \<const0> ;
assign LMB_Data_Write_27[4] = \<const0> ;
assign LMB_Data_Write_27[5] = \<const0> ;
assign LMB_Data_Write_27[6] = \<const0> ;
assign LMB_Data_Write_27[7] = \<const0> ;
assign LMB_Data_Write_27[8] = \<const0> ;
assign LMB_Data_Write_27[9] = \<const0> ;
assign LMB_Data_Write_27[10] = \<const0> ;
assign LMB_Data_Write_27[11] = \<const0> ;
assign LMB_Data_Write_27[12] = \<const0> ;
assign LMB_Data_Write_27[13] = \<const0> ;
assign LMB_Data_Write_27[14] = \<const0> ;
assign LMB_Data_Write_27[15] = \<const0> ;
assign LMB_Data_Write_27[16] = \<const0> ;
assign LMB_Data_Write_27[17] = \<const0> ;
assign LMB_Data_Write_27[18] = \<const0> ;
assign LMB_Data_Write_27[19] = \<const0> ;
assign LMB_Data_Write_27[20] = \<const0> ;
assign LMB_Data_Write_27[21] = \<const0> ;
assign LMB_Data_Write_27[22] = \<const0> ;
assign LMB_Data_Write_27[23] = \<const0> ;
assign LMB_Data_Write_27[24] = \<const0> ;
assign LMB_Data_Write_27[25] = \<const0> ;
assign LMB_Data_Write_27[26] = \<const0> ;
assign LMB_Data_Write_27[27] = \<const0> ;
assign LMB_Data_Write_27[28] = \<const0> ;
assign LMB_Data_Write_27[29] = \<const0> ;
assign LMB_Data_Write_27[30] = \<const0> ;
assign LMB_Data_Write_27[31] = \<const0> ;
assign LMB_Data_Write_28[0] = \<const0> ;
assign LMB_Data_Write_28[1] = \<const0> ;
assign LMB_Data_Write_28[2] = \<const0> ;
assign LMB_Data_Write_28[3] = \<const0> ;
assign LMB_Data_Write_28[4] = \<const0> ;
assign LMB_Data_Write_28[5] = \<const0> ;
assign LMB_Data_Write_28[6] = \<const0> ;
assign LMB_Data_Write_28[7] = \<const0> ;
assign LMB_Data_Write_28[8] = \<const0> ;
assign LMB_Data_Write_28[9] = \<const0> ;
assign LMB_Data_Write_28[10] = \<const0> ;
assign LMB_Data_Write_28[11] = \<const0> ;
assign LMB_Data_Write_28[12] = \<const0> ;
assign LMB_Data_Write_28[13] = \<const0> ;
assign LMB_Data_Write_28[14] = \<const0> ;
assign LMB_Data_Write_28[15] = \<const0> ;
assign LMB_Data_Write_28[16] = \<const0> ;
assign LMB_Data_Write_28[17] = \<const0> ;
assign LMB_Data_Write_28[18] = \<const0> ;
assign LMB_Data_Write_28[19] = \<const0> ;
assign LMB_Data_Write_28[20] = \<const0> ;
assign LMB_Data_Write_28[21] = \<const0> ;
assign LMB_Data_Write_28[22] = \<const0> ;
assign LMB_Data_Write_28[23] = \<const0> ;
assign LMB_Data_Write_28[24] = \<const0> ;
assign LMB_Data_Write_28[25] = \<const0> ;
assign LMB_Data_Write_28[26] = \<const0> ;
assign LMB_Data_Write_28[27] = \<const0> ;
assign LMB_Data_Write_28[28] = \<const0> ;
assign LMB_Data_Write_28[29] = \<const0> ;
assign LMB_Data_Write_28[30] = \<const0> ;
assign LMB_Data_Write_28[31] = \<const0> ;
assign LMB_Data_Write_29[0] = \<const0> ;
assign LMB_Data_Write_29[1] = \<const0> ;
assign LMB_Data_Write_29[2] = \<const0> ;
assign LMB_Data_Write_29[3] = \<const0> ;
assign LMB_Data_Write_29[4] = \<const0> ;
assign LMB_Data_Write_29[5] = \<const0> ;
assign LMB_Data_Write_29[6] = \<const0> ;
assign LMB_Data_Write_29[7] = \<const0> ;
assign LMB_Data_Write_29[8] = \<const0> ;
assign LMB_Data_Write_29[9] = \<const0> ;
assign LMB_Data_Write_29[10] = \<const0> ;
assign LMB_Data_Write_29[11] = \<const0> ;
assign LMB_Data_Write_29[12] = \<const0> ;
assign LMB_Data_Write_29[13] = \<const0> ;
assign LMB_Data_Write_29[14] = \<const0> ;
assign LMB_Data_Write_29[15] = \<const0> ;
assign LMB_Data_Write_29[16] = \<const0> ;
assign LMB_Data_Write_29[17] = \<const0> ;
assign LMB_Data_Write_29[18] = \<const0> ;
assign LMB_Data_Write_29[19] = \<const0> ;
assign LMB_Data_Write_29[20] = \<const0> ;
assign LMB_Data_Write_29[21] = \<const0> ;
assign LMB_Data_Write_29[22] = \<const0> ;
assign LMB_Data_Write_29[23] = \<const0> ;
assign LMB_Data_Write_29[24] = \<const0> ;
assign LMB_Data_Write_29[25] = \<const0> ;
assign LMB_Data_Write_29[26] = \<const0> ;
assign LMB_Data_Write_29[27] = \<const0> ;
assign LMB_Data_Write_29[28] = \<const0> ;
assign LMB_Data_Write_29[29] = \<const0> ;
assign LMB_Data_Write_29[30] = \<const0> ;
assign LMB_Data_Write_29[31] = \<const0> ;
assign LMB_Data_Write_3[0] = \<const0> ;
assign LMB_Data_Write_3[1] = \<const0> ;
assign LMB_Data_Write_3[2] = \<const0> ;
assign LMB_Data_Write_3[3] = \<const0> ;
assign LMB_Data_Write_3[4] = \<const0> ;
assign LMB_Data_Write_3[5] = \<const0> ;
assign LMB_Data_Write_3[6] = \<const0> ;
assign LMB_Data_Write_3[7] = \<const0> ;
assign LMB_Data_Write_3[8] = \<const0> ;
assign LMB_Data_Write_3[9] = \<const0> ;
assign LMB_Data_Write_3[10] = \<const0> ;
assign LMB_Data_Write_3[11] = \<const0> ;
assign LMB_Data_Write_3[12] = \<const0> ;
assign LMB_Data_Write_3[13] = \<const0> ;
assign LMB_Data_Write_3[14] = \<const0> ;
assign LMB_Data_Write_3[15] = \<const0> ;
assign LMB_Data_Write_3[16] = \<const0> ;
assign LMB_Data_Write_3[17] = \<const0> ;
assign LMB_Data_Write_3[18] = \<const0> ;
assign LMB_Data_Write_3[19] = \<const0> ;
assign LMB_Data_Write_3[20] = \<const0> ;
assign LMB_Data_Write_3[21] = \<const0> ;
assign LMB_Data_Write_3[22] = \<const0> ;
assign LMB_Data_Write_3[23] = \<const0> ;
assign LMB_Data_Write_3[24] = \<const0> ;
assign LMB_Data_Write_3[25] = \<const0> ;
assign LMB_Data_Write_3[26] = \<const0> ;
assign LMB_Data_Write_3[27] = \<const0> ;
assign LMB_Data_Write_3[28] = \<const0> ;
assign LMB_Data_Write_3[29] = \<const0> ;
assign LMB_Data_Write_3[30] = \<const0> ;
assign LMB_Data_Write_3[31] = \<const0> ;
assign LMB_Data_Write_30[0] = \<const0> ;
assign LMB_Data_Write_30[1] = \<const0> ;
assign LMB_Data_Write_30[2] = \<const0> ;
assign LMB_Data_Write_30[3] = \<const0> ;
assign LMB_Data_Write_30[4] = \<const0> ;
assign LMB_Data_Write_30[5] = \<const0> ;
assign LMB_Data_Write_30[6] = \<const0> ;
assign LMB_Data_Write_30[7] = \<const0> ;
assign LMB_Data_Write_30[8] = \<const0> ;
assign LMB_Data_Write_30[9] = \<const0> ;
assign LMB_Data_Write_30[10] = \<const0> ;
assign LMB_Data_Write_30[11] = \<const0> ;
assign LMB_Data_Write_30[12] = \<const0> ;
assign LMB_Data_Write_30[13] = \<const0> ;
assign LMB_Data_Write_30[14] = \<const0> ;
assign LMB_Data_Write_30[15] = \<const0> ;
assign LMB_Data_Write_30[16] = \<const0> ;
assign LMB_Data_Write_30[17] = \<const0> ;
assign LMB_Data_Write_30[18] = \<const0> ;
assign LMB_Data_Write_30[19] = \<const0> ;
assign LMB_Data_Write_30[20] = \<const0> ;
assign LMB_Data_Write_30[21] = \<const0> ;
assign LMB_Data_Write_30[22] = \<const0> ;
assign LMB_Data_Write_30[23] = \<const0> ;
assign LMB_Data_Write_30[24] = \<const0> ;
assign LMB_Data_Write_30[25] = \<const0> ;
assign LMB_Data_Write_30[26] = \<const0> ;
assign LMB_Data_Write_30[27] = \<const0> ;
assign LMB_Data_Write_30[28] = \<const0> ;
assign LMB_Data_Write_30[29] = \<const0> ;
assign LMB_Data_Write_30[30] = \<const0> ;
assign LMB_Data_Write_30[31] = \<const0> ;
assign LMB_Data_Write_31[0] = \<const0> ;
assign LMB_Data_Write_31[1] = \<const0> ;
assign LMB_Data_Write_31[2] = \<const0> ;
assign LMB_Data_Write_31[3] = \<const0> ;
assign LMB_Data_Write_31[4] = \<const0> ;
assign LMB_Data_Write_31[5] = \<const0> ;
assign LMB_Data_Write_31[6] = \<const0> ;
assign LMB_Data_Write_31[7] = \<const0> ;
assign LMB_Data_Write_31[8] = \<const0> ;
assign LMB_Data_Write_31[9] = \<const0> ;
assign LMB_Data_Write_31[10] = \<const0> ;
assign LMB_Data_Write_31[11] = \<const0> ;
assign LMB_Data_Write_31[12] = \<const0> ;
assign LMB_Data_Write_31[13] = \<const0> ;
assign LMB_Data_Write_31[14] = \<const0> ;
assign LMB_Data_Write_31[15] = \<const0> ;
assign LMB_Data_Write_31[16] = \<const0> ;
assign LMB_Data_Write_31[17] = \<const0> ;
assign LMB_Data_Write_31[18] = \<const0> ;
assign LMB_Data_Write_31[19] = \<const0> ;
assign LMB_Data_Write_31[20] = \<const0> ;
assign LMB_Data_Write_31[21] = \<const0> ;
assign LMB_Data_Write_31[22] = \<const0> ;
assign LMB_Data_Write_31[23] = \<const0> ;
assign LMB_Data_Write_31[24] = \<const0> ;
assign LMB_Data_Write_31[25] = \<const0> ;
assign LMB_Data_Write_31[26] = \<const0> ;
assign LMB_Data_Write_31[27] = \<const0> ;
assign LMB_Data_Write_31[28] = \<const0> ;
assign LMB_Data_Write_31[29] = \<const0> ;
assign LMB_Data_Write_31[30] = \<const0> ;
assign LMB_Data_Write_31[31] = \<const0> ;
assign LMB_Data_Write_4[0] = \<const0> ;
assign LMB_Data_Write_4[1] = \<const0> ;
assign LMB_Data_Write_4[2] = \<const0> ;
assign LMB_Data_Write_4[3] = \<const0> ;
assign LMB_Data_Write_4[4] = \<const0> ;
assign LMB_Data_Write_4[5] = \<const0> ;
assign LMB_Data_Write_4[6] = \<const0> ;
assign LMB_Data_Write_4[7] = \<const0> ;
assign LMB_Data_Write_4[8] = \<const0> ;
assign LMB_Data_Write_4[9] = \<const0> ;
assign LMB_Data_Write_4[10] = \<const0> ;
assign LMB_Data_Write_4[11] = \<const0> ;
assign LMB_Data_Write_4[12] = \<const0> ;
assign LMB_Data_Write_4[13] = \<const0> ;
assign LMB_Data_Write_4[14] = \<const0> ;
assign LMB_Data_Write_4[15] = \<const0> ;
assign LMB_Data_Write_4[16] = \<const0> ;
assign LMB_Data_Write_4[17] = \<const0> ;
assign LMB_Data_Write_4[18] = \<const0> ;
assign LMB_Data_Write_4[19] = \<const0> ;
assign LMB_Data_Write_4[20] = \<const0> ;
assign LMB_Data_Write_4[21] = \<const0> ;
assign LMB_Data_Write_4[22] = \<const0> ;
assign LMB_Data_Write_4[23] = \<const0> ;
assign LMB_Data_Write_4[24] = \<const0> ;
assign LMB_Data_Write_4[25] = \<const0> ;
assign LMB_Data_Write_4[26] = \<const0> ;
assign LMB_Data_Write_4[27] = \<const0> ;
assign LMB_Data_Write_4[28] = \<const0> ;
assign LMB_Data_Write_4[29] = \<const0> ;
assign LMB_Data_Write_4[30] = \<const0> ;
assign LMB_Data_Write_4[31] = \<const0> ;
assign LMB_Data_Write_5[0] = \<const0> ;
assign LMB_Data_Write_5[1] = \<const0> ;
assign LMB_Data_Write_5[2] = \<const0> ;
assign LMB_Data_Write_5[3] = \<const0> ;
assign LMB_Data_Write_5[4] = \<const0> ;
assign LMB_Data_Write_5[5] = \<const0> ;
assign LMB_Data_Write_5[6] = \<const0> ;
assign LMB_Data_Write_5[7] = \<const0> ;
assign LMB_Data_Write_5[8] = \<const0> ;
assign LMB_Data_Write_5[9] = \<const0> ;
assign LMB_Data_Write_5[10] = \<const0> ;
assign LMB_Data_Write_5[11] = \<const0> ;
assign LMB_Data_Write_5[12] = \<const0> ;
assign LMB_Data_Write_5[13] = \<const0> ;
assign LMB_Data_Write_5[14] = \<const0> ;
assign LMB_Data_Write_5[15] = \<const0> ;
assign LMB_Data_Write_5[16] = \<const0> ;
assign LMB_Data_Write_5[17] = \<const0> ;
assign LMB_Data_Write_5[18] = \<const0> ;
assign LMB_Data_Write_5[19] = \<const0> ;
assign LMB_Data_Write_5[20] = \<const0> ;
assign LMB_Data_Write_5[21] = \<const0> ;
assign LMB_Data_Write_5[22] = \<const0> ;
assign LMB_Data_Write_5[23] = \<const0> ;
assign LMB_Data_Write_5[24] = \<const0> ;
assign LMB_Data_Write_5[25] = \<const0> ;
assign LMB_Data_Write_5[26] = \<const0> ;
assign LMB_Data_Write_5[27] = \<const0> ;
assign LMB_Data_Write_5[28] = \<const0> ;
assign LMB_Data_Write_5[29] = \<const0> ;
assign LMB_Data_Write_5[30] = \<const0> ;
assign LMB_Data_Write_5[31] = \<const0> ;
assign LMB_Data_Write_6[0] = \<const0> ;
assign LMB_Data_Write_6[1] = \<const0> ;
assign LMB_Data_Write_6[2] = \<const0> ;
assign LMB_Data_Write_6[3] = \<const0> ;
assign LMB_Data_Write_6[4] = \<const0> ;
assign LMB_Data_Write_6[5] = \<const0> ;
assign LMB_Data_Write_6[6] = \<const0> ;
assign LMB_Data_Write_6[7] = \<const0> ;
assign LMB_Data_Write_6[8] = \<const0> ;
assign LMB_Data_Write_6[9] = \<const0> ;
assign LMB_Data_Write_6[10] = \<const0> ;
assign LMB_Data_Write_6[11] = \<const0> ;
assign LMB_Data_Write_6[12] = \<const0> ;
assign LMB_Data_Write_6[13] = \<const0> ;
assign LMB_Data_Write_6[14] = \<const0> ;
assign LMB_Data_Write_6[15] = \<const0> ;
assign LMB_Data_Write_6[16] = \<const0> ;
assign LMB_Data_Write_6[17] = \<const0> ;
assign LMB_Data_Write_6[18] = \<const0> ;
assign LMB_Data_Write_6[19] = \<const0> ;
assign LMB_Data_Write_6[20] = \<const0> ;
assign LMB_Data_Write_6[21] = \<const0> ;
assign LMB_Data_Write_6[22] = \<const0> ;
assign LMB_Data_Write_6[23] = \<const0> ;
assign LMB_Data_Write_6[24] = \<const0> ;
assign LMB_Data_Write_6[25] = \<const0> ;
assign LMB_Data_Write_6[26] = \<const0> ;
assign LMB_Data_Write_6[27] = \<const0> ;
assign LMB_Data_Write_6[28] = \<const0> ;
assign LMB_Data_Write_6[29] = \<const0> ;
assign LMB_Data_Write_6[30] = \<const0> ;
assign LMB_Data_Write_6[31] = \<const0> ;
assign LMB_Data_Write_7[0] = \<const0> ;
assign LMB_Data_Write_7[1] = \<const0> ;
assign LMB_Data_Write_7[2] = \<const0> ;
assign LMB_Data_Write_7[3] = \<const0> ;
assign LMB_Data_Write_7[4] = \<const0> ;
assign LMB_Data_Write_7[5] = \<const0> ;
assign LMB_Data_Write_7[6] = \<const0> ;
assign LMB_Data_Write_7[7] = \<const0> ;
assign LMB_Data_Write_7[8] = \<const0> ;
assign LMB_Data_Write_7[9] = \<const0> ;
assign LMB_Data_Write_7[10] = \<const0> ;
assign LMB_Data_Write_7[11] = \<const0> ;
assign LMB_Data_Write_7[12] = \<const0> ;
assign LMB_Data_Write_7[13] = \<const0> ;
assign LMB_Data_Write_7[14] = \<const0> ;
assign LMB_Data_Write_7[15] = \<const0> ;
assign LMB_Data_Write_7[16] = \<const0> ;
assign LMB_Data_Write_7[17] = \<const0> ;
assign LMB_Data_Write_7[18] = \<const0> ;
assign LMB_Data_Write_7[19] = \<const0> ;
assign LMB_Data_Write_7[20] = \<const0> ;
assign LMB_Data_Write_7[21] = \<const0> ;
assign LMB_Data_Write_7[22] = \<const0> ;
assign LMB_Data_Write_7[23] = \<const0> ;
assign LMB_Data_Write_7[24] = \<const0> ;
assign LMB_Data_Write_7[25] = \<const0> ;
assign LMB_Data_Write_7[26] = \<const0> ;
assign LMB_Data_Write_7[27] = \<const0> ;
assign LMB_Data_Write_7[28] = \<const0> ;
assign LMB_Data_Write_7[29] = \<const0> ;
assign LMB_Data_Write_7[30] = \<const0> ;
assign LMB_Data_Write_7[31] = \<const0> ;
assign LMB_Data_Write_8[0] = \<const0> ;
assign LMB_Data_Write_8[1] = \<const0> ;
assign LMB_Data_Write_8[2] = \<const0> ;
assign LMB_Data_Write_8[3] = \<const0> ;
assign LMB_Data_Write_8[4] = \<const0> ;
assign LMB_Data_Write_8[5] = \<const0> ;
assign LMB_Data_Write_8[6] = \<const0> ;
assign LMB_Data_Write_8[7] = \<const0> ;
assign LMB_Data_Write_8[8] = \<const0> ;
assign LMB_Data_Write_8[9] = \<const0> ;
assign LMB_Data_Write_8[10] = \<const0> ;
assign LMB_Data_Write_8[11] = \<const0> ;
assign LMB_Data_Write_8[12] = \<const0> ;
assign LMB_Data_Write_8[13] = \<const0> ;
assign LMB_Data_Write_8[14] = \<const0> ;
assign LMB_Data_Write_8[15] = \<const0> ;
assign LMB_Data_Write_8[16] = \<const0> ;
assign LMB_Data_Write_8[17] = \<const0> ;
assign LMB_Data_Write_8[18] = \<const0> ;
assign LMB_Data_Write_8[19] = \<const0> ;
assign LMB_Data_Write_8[20] = \<const0> ;
assign LMB_Data_Write_8[21] = \<const0> ;
assign LMB_Data_Write_8[22] = \<const0> ;
assign LMB_Data_Write_8[23] = \<const0> ;
assign LMB_Data_Write_8[24] = \<const0> ;
assign LMB_Data_Write_8[25] = \<const0> ;
assign LMB_Data_Write_8[26] = \<const0> ;
assign LMB_Data_Write_8[27] = \<const0> ;
assign LMB_Data_Write_8[28] = \<const0> ;
assign LMB_Data_Write_8[29] = \<const0> ;
assign LMB_Data_Write_8[30] = \<const0> ;
assign LMB_Data_Write_8[31] = \<const0> ;
assign LMB_Data_Write_9[0] = \<const0> ;
assign LMB_Data_Write_9[1] = \<const0> ;
assign LMB_Data_Write_9[2] = \<const0> ;
assign LMB_Data_Write_9[3] = \<const0> ;
assign LMB_Data_Write_9[4] = \<const0> ;
assign LMB_Data_Write_9[5] = \<const0> ;
assign LMB_Data_Write_9[6] = \<const0> ;
assign LMB_Data_Write_9[7] = \<const0> ;
assign LMB_Data_Write_9[8] = \<const0> ;
assign LMB_Data_Write_9[9] = \<const0> ;
assign LMB_Data_Write_9[10] = \<const0> ;
assign LMB_Data_Write_9[11] = \<const0> ;
assign LMB_Data_Write_9[12] = \<const0> ;
assign LMB_Data_Write_9[13] = \<const0> ;
assign LMB_Data_Write_9[14] = \<const0> ;
assign LMB_Data_Write_9[15] = \<const0> ;
assign LMB_Data_Write_9[16] = \<const0> ;
assign LMB_Data_Write_9[17] = \<const0> ;
assign LMB_Data_Write_9[18] = \<const0> ;
assign LMB_Data_Write_9[19] = \<const0> ;
assign LMB_Data_Write_9[20] = \<const0> ;
assign LMB_Data_Write_9[21] = \<const0> ;
assign LMB_Data_Write_9[22] = \<const0> ;
assign LMB_Data_Write_9[23] = \<const0> ;
assign LMB_Data_Write_9[24] = \<const0> ;
assign LMB_Data_Write_9[25] = \<const0> ;
assign LMB_Data_Write_9[26] = \<const0> ;
assign LMB_Data_Write_9[27] = \<const0> ;
assign LMB_Data_Write_9[28] = \<const0> ;
assign LMB_Data_Write_9[29] = \<const0> ;
assign LMB_Data_Write_9[30] = \<const0> ;
assign LMB_Data_Write_9[31] = \<const0> ;
assign LMB_Read_Strobe_0 = \<const0> ;
assign LMB_Read_Strobe_1 = \<const0> ;
assign LMB_Read_Strobe_10 = \<const0> ;
assign LMB_Read_Strobe_11 = \<const0> ;
assign LMB_Read_Strobe_12 = \<const0> ;
assign LMB_Read_Strobe_13 = \<const0> ;
assign LMB_Read_Strobe_14 = \<const0> ;
assign LMB_Read_Strobe_15 = \<const0> ;
assign LMB_Read_Strobe_16 = \<const0> ;
assign LMB_Read_Strobe_17 = \<const0> ;
assign LMB_Read_Strobe_18 = \<const0> ;
assign LMB_Read_Strobe_19 = \<const0> ;
assign LMB_Read_Strobe_2 = \<const0> ;
assign LMB_Read_Strobe_20 = \<const0> ;
assign LMB_Read_Strobe_21 = \<const0> ;
assign LMB_Read_Strobe_22 = \<const0> ;
assign LMB_Read_Strobe_23 = \<const0> ;
assign LMB_Read_Strobe_24 = \<const0> ;
assign LMB_Read_Strobe_25 = \<const0> ;
assign LMB_Read_Strobe_26 = \<const0> ;
assign LMB_Read_Strobe_27 = \<const0> ;
assign LMB_Read_Strobe_28 = \<const0> ;
assign LMB_Read_Strobe_29 = \<const0> ;
assign LMB_Read_Strobe_3 = \<const0> ;
assign LMB_Read_Strobe_30 = \<const0> ;
assign LMB_Read_Strobe_31 = \<const0> ;
assign LMB_Read_Strobe_4 = \<const0> ;
assign LMB_Read_Strobe_5 = \<const0> ;
assign LMB_Read_Strobe_6 = \<const0> ;
assign LMB_Read_Strobe_7 = \<const0> ;
assign LMB_Read_Strobe_8 = \<const0> ;
assign LMB_Read_Strobe_9 = \<const0> ;
assign LMB_Write_Strobe_0 = \<const0> ;
assign LMB_Write_Strobe_1 = \<const0> ;
assign LMB_Write_Strobe_10 = \<const0> ;
assign LMB_Write_Strobe_11 = \<const0> ;
assign LMB_Write_Strobe_12 = \<const0> ;
assign LMB_Write_Strobe_13 = \<const0> ;
assign LMB_Write_Strobe_14 = \<const0> ;
assign LMB_Write_Strobe_15 = \<const0> ;
assign LMB_Write_Strobe_16 = \<const0> ;
assign LMB_Write_Strobe_17 = \<const0> ;
assign LMB_Write_Strobe_18 = \<const0> ;
assign LMB_Write_Strobe_19 = \<const0> ;
assign LMB_Write_Strobe_2 = \<const0> ;
assign LMB_Write_Strobe_20 = \<const0> ;
assign LMB_Write_Strobe_21 = \<const0> ;
assign LMB_Write_Strobe_22 = \<const0> ;
assign LMB_Write_Strobe_23 = \<const0> ;
assign LMB_Write_Strobe_24 = \<const0> ;
assign LMB_Write_Strobe_25 = \<const0> ;
assign LMB_Write_Strobe_26 = \<const0> ;
assign LMB_Write_Strobe_27 = \<const0> ;
assign LMB_Write_Strobe_28 = \<const0> ;
assign LMB_Write_Strobe_29 = \<const0> ;
assign LMB_Write_Strobe_3 = \<const0> ;
assign LMB_Write_Strobe_30 = \<const0> ;
assign LMB_Write_Strobe_31 = \<const0> ;
assign LMB_Write_Strobe_4 = \<const0> ;
assign LMB_Write_Strobe_5 = \<const0> ;
assign LMB_Write_Strobe_6 = \<const0> ;
assign LMB_Write_Strobe_7 = \<const0> ;
assign LMB_Write_Strobe_8 = \<const0> ;
assign LMB_Write_Strobe_9 = \<const0> ;
assign M_AXIS_TDATA[31] = \<const0> ;
assign M_AXIS_TDATA[30] = \<const0> ;
assign M_AXIS_TDATA[29] = \<const0> ;
assign M_AXIS_TDATA[28] = \<const0> ;
assign M_AXIS_TDATA[27] = \<const0> ;
assign M_AXIS_TDATA[26] = \<const0> ;
assign M_AXIS_TDATA[25] = \<const0> ;
assign M_AXIS_TDATA[24] = \<const0> ;
assign M_AXIS_TDATA[23] = \<const0> ;
assign M_AXIS_TDATA[22] = \<const0> ;
assign M_AXIS_TDATA[21] = \<const0> ;
assign M_AXIS_TDATA[20] = \<const0> ;
assign M_AXIS_TDATA[19] = \<const0> ;
assign M_AXIS_TDATA[18] = \<const0> ;
assign M_AXIS_TDATA[17] = \<const0> ;
assign M_AXIS_TDATA[16] = \<const0> ;
assign M_AXIS_TDATA[15] = \<const0> ;
assign M_AXIS_TDATA[14] = \<const0> ;
assign M_AXIS_TDATA[13] = \<const0> ;
assign M_AXIS_TDATA[12] = \<const0> ;
assign M_AXIS_TDATA[11] = \<const0> ;
assign M_AXIS_TDATA[10] = \<const0> ;
assign M_AXIS_TDATA[9] = \<const0> ;
assign M_AXIS_TDATA[8] = \<const0> ;
assign M_AXIS_TDATA[7] = \<const0> ;
assign M_AXIS_TDATA[6] = \<const0> ;
assign M_AXIS_TDATA[5] = \<const0> ;
assign M_AXIS_TDATA[4] = \<const0> ;
assign M_AXIS_TDATA[3] = \<const0> ;
assign M_AXIS_TDATA[2] = \<const0> ;
assign M_AXIS_TDATA[1] = \<const0> ;
assign M_AXIS_TDATA[0] = \<const0> ;
assign M_AXIS_TID[6] = \<const0> ;
assign M_AXIS_TID[5] = \<const0> ;
assign M_AXIS_TID[4] = \<const0> ;
assign M_AXIS_TID[3] = \<const0> ;
assign M_AXIS_TID[2] = \<const0> ;
assign M_AXIS_TID[1] = \<const0> ;
assign M_AXIS_TID[0] = \<const0> ;
assign M_AXIS_TVALID = \<const0> ;
assign M_AXI_ARADDR[31] = \<const0> ;
assign M_AXI_ARADDR[30] = \<const0> ;
assign M_AXI_ARADDR[29] = \<const0> ;
assign M_AXI_ARADDR[28] = \<const0> ;
assign M_AXI_ARADDR[27] = \<const0> ;
assign M_AXI_ARADDR[26] = \<const0> ;
assign M_AXI_ARADDR[25] = \<const0> ;
assign M_AXI_ARADDR[24] = \<const0> ;
assign M_AXI_ARADDR[23] = \<const0> ;
assign M_AXI_ARADDR[22] = \<const0> ;
assign M_AXI_ARADDR[21] = \<const0> ;
assign M_AXI_ARADDR[20] = \<const0> ;
assign M_AXI_ARADDR[19] = \<const0> ;
assign M_AXI_ARADDR[18] = \<const0> ;
assign M_AXI_ARADDR[17] = \<const0> ;
assign M_AXI_ARADDR[16] = \<const0> ;
assign M_AXI_ARADDR[15] = \<const0> ;
assign M_AXI_ARADDR[14] = \<const0> ;
assign M_AXI_ARADDR[13] = \<const0> ;
assign M_AXI_ARADDR[12] = \<const0> ;
assign M_AXI_ARADDR[11] = \<const0> ;
assign M_AXI_ARADDR[10] = \<const0> ;
assign M_AXI_ARADDR[9] = \<const0> ;
assign M_AXI_ARADDR[8] = \<const0> ;
assign M_AXI_ARADDR[7] = \<const0> ;
assign M_AXI_ARADDR[6] = \<const0> ;
assign M_AXI_ARADDR[5] = \<const0> ;
assign M_AXI_ARADDR[4] = \<const0> ;
assign M_AXI_ARADDR[3] = \<const0> ;
assign M_AXI_ARADDR[2] = \<const0> ;
assign M_AXI_ARADDR[1] = \<const0> ;
assign M_AXI_ARADDR[0] = \<const0> ;
assign M_AXI_ARBURST[1] = \<const0> ;
assign M_AXI_ARBURST[0] = \<const0> ;
assign M_AXI_ARCACHE[3] = \<const0> ;
assign M_AXI_ARCACHE[2] = \<const0> ;
assign M_AXI_ARCACHE[1] = \<const0> ;
assign M_AXI_ARCACHE[0] = \<const0> ;
assign M_AXI_ARID[0] = \<const0> ;
assign M_AXI_ARLEN[7] = \<const0> ;
assign M_AXI_ARLEN[6] = \<const0> ;
assign M_AXI_ARLEN[5] = \<const0> ;
assign M_AXI_ARLEN[4] = \<const0> ;
assign M_AXI_ARLEN[3] = \<const0> ;
assign M_AXI_ARLEN[2] = \<const0> ;
assign M_AXI_ARLEN[1] = \<const0> ;
assign M_AXI_ARLEN[0] = \<const0> ;
assign M_AXI_ARLOCK = \<const0> ;
assign M_AXI_ARPROT[2] = \<const0> ;
assign M_AXI_ARPROT[1] = \<const0> ;
assign M_AXI_ARPROT[0] = \<const0> ;
assign M_AXI_ARQOS[3] = \<const0> ;
assign M_AXI_ARQOS[2] = \<const0> ;
assign M_AXI_ARQOS[1] = \<const0> ;
assign M_AXI_ARQOS[0] = \<const0> ;
assign M_AXI_ARSIZE[2] = \<const0> ;
assign M_AXI_ARSIZE[1] = \<const0> ;
assign M_AXI_ARSIZE[0] = \<const0> ;
assign M_AXI_ARVALID = \<const0> ;
assign M_AXI_AWADDR[31] = \<const0> ;
assign M_AXI_AWADDR[30] = \<const0> ;
assign M_AXI_AWADDR[29] = \<const0> ;
assign M_AXI_AWADDR[28] = \<const0> ;
assign M_AXI_AWADDR[27] = \<const0> ;
assign M_AXI_AWADDR[26] = \<const0> ;
assign M_AXI_AWADDR[25] = \<const0> ;
assign M_AXI_AWADDR[24] = \<const0> ;
assign M_AXI_AWADDR[23] = \<const0> ;
assign M_AXI_AWADDR[22] = \<const0> ;
assign M_AXI_AWADDR[21] = \<const0> ;
assign M_AXI_AWADDR[20] = \<const0> ;
assign M_AXI_AWADDR[19] = \<const0> ;
assign M_AXI_AWADDR[18] = \<const0> ;
assign M_AXI_AWADDR[17] = \<const0> ;
assign M_AXI_AWADDR[16] = \<const0> ;
assign M_AXI_AWADDR[15] = \<const0> ;
assign M_AXI_AWADDR[14] = \<const0> ;
assign M_AXI_AWADDR[13] = \<const0> ;
assign M_AXI_AWADDR[12] = \<const0> ;
assign M_AXI_AWADDR[11] = \<const0> ;
assign M_AXI_AWADDR[10] = \<const0> ;
assign M_AXI_AWADDR[9] = \<const0> ;
assign M_AXI_AWADDR[8] = \<const0> ;
assign M_AXI_AWADDR[7] = \<const0> ;
assign M_AXI_AWADDR[6] = \<const0> ;
assign M_AXI_AWADDR[5] = \<const0> ;
assign M_AXI_AWADDR[4] = \<const0> ;
assign M_AXI_AWADDR[3] = \<const0> ;
assign M_AXI_AWADDR[2] = \<const0> ;
assign M_AXI_AWADDR[1] = \<const0> ;
assign M_AXI_AWADDR[0] = \<const0> ;
assign M_AXI_AWBURST[1] = \<const0> ;
assign M_AXI_AWBURST[0] = \<const0> ;
assign M_AXI_AWCACHE[3] = \<const0> ;
assign M_AXI_AWCACHE[2] = \<const0> ;
assign M_AXI_AWCACHE[1] = \<const0> ;
assign M_AXI_AWCACHE[0] = \<const0> ;
assign M_AXI_AWID[0] = \<const0> ;
assign M_AXI_AWLEN[7] = \<const0> ;
assign M_AXI_AWLEN[6] = \<const0> ;
assign M_AXI_AWLEN[5] = \<const0> ;
assign M_AXI_AWLEN[4] = \<const0> ;
assign M_AXI_AWLEN[3] = \<const0> ;
assign M_AXI_AWLEN[2] = \<const0> ;
assign M_AXI_AWLEN[1] = \<const0> ;
assign M_AXI_AWLEN[0] = \<const0> ;
assign M_AXI_AWLOCK = \<const0> ;
assign M_AXI_AWPROT[2] = \<const0> ;
assign M_AXI_AWPROT[1] = \<const0> ;
assign M_AXI_AWPROT[0] = \<const0> ;
assign M_AXI_AWQOS[3] = \<const0> ;
assign M_AXI_AWQOS[2] = \<const0> ;
assign M_AXI_AWQOS[1] = \<const0> ;
assign M_AXI_AWQOS[0] = \<const0> ;
assign M_AXI_AWSIZE[2] = \<const0> ;
assign M_AXI_AWSIZE[1] = \<const0> ;
assign M_AXI_AWSIZE[0] = \<const0> ;
assign M_AXI_AWVALID = \<const0> ;
assign M_AXI_BREADY = \<const0> ;
assign M_AXI_RREADY = \<const0> ;
assign M_AXI_WDATA[31] = \<const0> ;
assign M_AXI_WDATA[30] = \<const0> ;
assign M_AXI_WDATA[29] = \<const0> ;
assign M_AXI_WDATA[28] = \<const0> ;
assign M_AXI_WDATA[27] = \<const0> ;
assign M_AXI_WDATA[26] = \<const0> ;
assign M_AXI_WDATA[25] = \<const0> ;
assign M_AXI_WDATA[24] = \<const0> ;
assign M_AXI_WDATA[23] = \<const0> ;
assign M_AXI_WDATA[22] = \<const0> ;
assign M_AXI_WDATA[21] = \<const0> ;
assign M_AXI_WDATA[20] = \<const0> ;
assign M_AXI_WDATA[19] = \<const0> ;
assign M_AXI_WDATA[18] = \<const0> ;
assign M_AXI_WDATA[17] = \<const0> ;
assign M_AXI_WDATA[16] = \<const0> ;
assign M_AXI_WDATA[15] = \<const0> ;
assign M_AXI_WDATA[14] = \<const0> ;
assign M_AXI_WDATA[13] = \<const0> ;
assign M_AXI_WDATA[12] = \<const0> ;
assign M_AXI_WDATA[11] = \<const0> ;
assign M_AXI_WDATA[10] = \<const0> ;
assign M_AXI_WDATA[9] = \<const0> ;
assign M_AXI_WDATA[8] = \<const0> ;
assign M_AXI_WDATA[7] = \<const0> ;
assign M_AXI_WDATA[6] = \<const0> ;
assign M_AXI_WDATA[5] = \<const0> ;
assign M_AXI_WDATA[4] = \<const0> ;
assign M_AXI_WDATA[3] = \<const0> ;
assign M_AXI_WDATA[2] = \<const0> ;
assign M_AXI_WDATA[1] = \<const0> ;
assign M_AXI_WDATA[0] = \<const0> ;
assign M_AXI_WLAST = \<const0> ;
assign M_AXI_WSTRB[3] = \<const0> ;
assign M_AXI_WSTRB[2] = \<const0> ;
assign M_AXI_WSTRB[1] = \<const0> ;
assign M_AXI_WSTRB[0] = \<const0> ;
assign M_AXI_WVALID = \<const0> ;
assign S_AXI_ARREADY = \<const0> ;
assign S_AXI_AWREADY = \<const0> ;
assign S_AXI_BRESP[1] = \<const0> ;
assign S_AXI_BRESP[0] = \<const0> ;
assign S_AXI_BVALID = \<const0> ;
assign S_AXI_RDATA[31] = \<const0> ;
assign S_AXI_RDATA[30] = \<const0> ;
assign S_AXI_RDATA[29] = \<const0> ;
assign S_AXI_RDATA[28] = \<const0> ;
assign S_AXI_RDATA[27] = \<const0> ;
assign S_AXI_RDATA[26] = \<const0> ;
assign S_AXI_RDATA[25] = \<const0> ;
assign S_AXI_RDATA[24] = \<const0> ;
assign S_AXI_RDATA[23] = \<const0> ;
assign S_AXI_RDATA[22] = \<const0> ;
assign S_AXI_RDATA[21] = \<const0> ;
assign S_AXI_RDATA[20] = \<const0> ;
assign S_AXI_RDATA[19] = \<const0> ;
assign S_AXI_RDATA[18] = \<const0> ;
assign S_AXI_RDATA[17] = \<const0> ;
assign S_AXI_RDATA[16] = \<const0> ;
assign S_AXI_RDATA[15] = \<const0> ;
assign S_AXI_RDATA[14] = \<const0> ;
assign S_AXI_RDATA[13] = \<const0> ;
assign S_AXI_RDATA[12] = \<const0> ;
assign S_AXI_RDATA[11] = \<const0> ;
assign S_AXI_RDATA[10] = \<const0> ;
assign S_AXI_RDATA[9] = \<const0> ;
assign S_AXI_RDATA[8] = \<const0> ;
assign S_AXI_RDATA[7] = \<const0> ;
assign S_AXI_RDATA[6] = \<const0> ;
assign S_AXI_RDATA[5] = \<const0> ;
assign S_AXI_RDATA[4] = \<const0> ;
assign S_AXI_RDATA[3] = \<const0> ;
assign S_AXI_RDATA[2] = \<const0> ;
assign S_AXI_RDATA[1] = \<const0> ;
assign S_AXI_RDATA[0] = \<const0> ;
assign S_AXI_RRESP[1] = \<const0> ;
assign S_AXI_RRESP[0] = \<const0> ;
assign S_AXI_RVALID = \<const0> ;
assign S_AXI_WREADY = \<const0> ;
assign TRACE_CLK_OUT = \<const0> ;
assign TRACE_CTL = \<const1> ;
assign TRACE_DATA[31] = \<const0> ;
assign TRACE_DATA[30] = \<const0> ;
assign TRACE_DATA[29] = \<const0> ;
assign TRACE_DATA[28] = \<const0> ;
assign TRACE_DATA[27] = \<const0> ;
assign TRACE_DATA[26] = \<const0> ;
assign TRACE_DATA[25] = \<const0> ;
assign TRACE_DATA[24] = \<const0> ;
assign TRACE_DATA[23] = \<const0> ;
assign TRACE_DATA[22] = \<const0> ;
assign TRACE_DATA[21] = \<const0> ;
assign TRACE_DATA[20] = \<const0> ;
assign TRACE_DATA[19] = \<const0> ;
assign TRACE_DATA[18] = \<const0> ;
assign TRACE_DATA[17] = \<const0> ;
assign TRACE_DATA[16] = \<const0> ;
assign TRACE_DATA[15] = \<const0> ;
assign TRACE_DATA[14] = \<const0> ;
assign TRACE_DATA[13] = \<const0> ;
assign TRACE_DATA[12] = \<const0> ;
assign TRACE_DATA[11] = \<const0> ;
assign TRACE_DATA[10] = \<const0> ;
assign TRACE_DATA[9] = \<const0> ;
assign TRACE_DATA[8] = \<const0> ;
assign TRACE_DATA[7] = \<const0> ;
assign TRACE_DATA[6] = \<const0> ;
assign TRACE_DATA[5] = \<const0> ;
assign TRACE_DATA[4] = \<const0> ;
assign TRACE_DATA[3] = \<const0> ;
assign TRACE_DATA[2] = \<const0> ;
assign TRACE_DATA[1] = \<const0> ;
assign TRACE_DATA[0] = \<const0> ;
assign Trig_Ack_In_0 = \<const0> ;
assign Trig_Ack_In_1 = \<const0> ;
assign Trig_Ack_In_2 = \<const0> ;
assign Trig_Ack_In_3 = \<const0> ;
assign Trig_Out_0 = \<const0> ;
assign Trig_Out_1 = \<const0> ;
assign Trig_Out_2 = \<const0> ;
assign Trig_Out_3 = \<const0> ;
assign bscan_ext_tdo = \<const0> ;
GND GND
(.G(\<const0> ));
system_mdm_1_0_MDM_Core MDM_Core_I1
(.AR(sel_n_reset),
.D(p_1_in),
.Dbg_Disable_0(Dbg_Disable_0),
.Dbg_Reg_En_0(Dbg_Reg_En_0),
.Dbg_Rst_0(Dbg_Rst_0),
.Dbg_Shift_0(Dbg_Shift_0),
.Dbg_TDO_0(Dbg_TDO_0),
.Debug_SYS_Rst(Debug_SYS_Rst),
.E(\Use_E2.BSCAN_I_n_8 ),
.Ext_JTAG_SEL(Ext_JTAG_SEL),
.Ext_JTAG_TDI(Ext_JTAG_TDI),
.Ext_JTAG_TDO(Ext_JTAG_TDO),
.Ext_NM_BRK(Ext_NM_BRK),
.Q(MDM_Core_I1_n_0),
.Scan_Reset(Scan_Reset),
.Scan_Reset_Sel(Scan_Reset_Sel),
.\Use_BSCAN.PORT_Selector_reg[0]_0 (Dbg_Update_31),
.\Use_BSCAN.PORT_Selector_reg[0]_1 (Dbg_Clk_31),
.\Use_BSCAN.PORT_Selector_reg[0]_2 (Ext_JTAG_SHIFT),
.\Use_BSCAN.PORT_Selector_reg[0]_3 (Ext_JTAG_CAPTURE),
.\Use_BSCAN.PORT_Selector_reg[0]_4 (\Use_E2.BSCAN_I_n_13 ),
.\Use_Serial_Unified_Completion.completion_status_reg[15] (MDM_Core_I1_n_19),
.\Use_Serial_Unified_Completion.count_reg[4] (\JTAG_CONTROL_I/Use_Serial_Unified_Completion.count_reg ),
.\Use_Serial_Unified_Completion.count_reg[5] (p_0_in),
.\command_reg[5] (\JTAG_CONTROL_I/sel ),
.p_20_out__0(\JTAG_CONTROL_I/p_20_out__0 ),
.p_43_out__0(\JTAG_CONTROL_I/p_43_out__0 ),
.sel(sel),
.\shift_Count_reg[0] (p_0_in__0),
.shift_n_reset(shift_n_reset),
.tdo(tdo));
system_mdm_1_0_MB_BUFG \No_Dbg_Reg_Access.BUFG_DRCK
(.Dbg_Clk_31(Dbg_Clk_31),
.drck_i(drck_i));
system_mdm_1_0_MB_BSCANE2 \Use_E2.BSCAN_I
(.AR(sel_n_reset),
.D(p_1_in),
.Dbg_Capture_0(Ext_JTAG_CAPTURE),
.Dbg_TDO_0(Dbg_TDO_0),
.Dbg_Update_31(Dbg_Update_31),
.E(\Use_E2.BSCAN_I_n_8 ),
.Ext_JTAG_RESET(Ext_JTAG_RESET),
.Ext_JTAG_TDI(Ext_JTAG_TDI),
.Q(MDM_Core_I1_n_0),
.Scan_Reset(Scan_Reset),
.Scan_Reset_Sel(Scan_Reset_Sel),
.\Use_Serial_Unified_Completion.count_reg[5] (Ext_JTAG_SHIFT),
.\Use_Serial_Unified_Completion.count_reg[5]_0 (\JTAG_CONTROL_I/sel ),
.\Use_Serial_Unified_Completion.count_reg[5]_1 (p_0_in),
.\Use_Serial_Unified_Completion.count_reg[5]_2 (\JTAG_CONTROL_I/Use_Serial_Unified_Completion.count_reg ),
.\Use_Serial_Unified_Completion.mb_instr_overrun_reg (\Use_E2.BSCAN_I_n_13 ),
.\Use_Serial_Unified_Completion.sample_1_reg[15] (MDM_Core_I1_n_19),
.drck_i(drck_i),
.p_20_out__0(\JTAG_CONTROL_I/p_20_out__0 ),
.p_43_out__0(\JTAG_CONTROL_I/p_43_out__0 ),
.sel(sel),
.\shift_Count_reg[0] (p_0_in__0),
.shift_n_reset(shift_n_reset),
.tdo(tdo));
VCC VCC
(.P(\<const1> ));
endmodule
(* ORIG_REF_NAME = "MDM_Core" *)
module system_mdm_1_0_MDM_Core
(Q,
Dbg_Disable_0,
Ext_NM_BRK,
Debug_SYS_Rst,
Dbg_Rst_0,
Dbg_Shift_0,
p_20_out__0,
p_43_out__0,
Dbg_Reg_En_0,
tdo,
Ext_JTAG_SEL,
\Use_Serial_Unified_Completion.count_reg[4] ,
\Use_Serial_Unified_Completion.completion_status_reg[15] ,
\Use_BSCAN.PORT_Selector_reg[0]_0 ,
\Use_BSCAN.PORT_Selector_reg[0]_1 ,
shift_n_reset,
\Use_BSCAN.PORT_Selector_reg[0]_2 ,
D,
\Use_BSCAN.PORT_Selector_reg[0]_3 ,
sel,
Dbg_TDO_0,
Ext_JTAG_TDO,
\Use_Serial_Unified_Completion.count_reg[5] ,
\shift_Count_reg[0] ,
Scan_Reset,
Scan_Reset_Sel,
\Use_BSCAN.PORT_Selector_reg[0]_4 ,
AR,
Ext_JTAG_TDI,
E,
\command_reg[5] );
output [0:0]Q;
output Dbg_Disable_0;
output Ext_NM_BRK;
output Debug_SYS_Rst;
output Dbg_Rst_0;
output Dbg_Shift_0;
output p_20_out__0;
output p_43_out__0;
output [0:7]Dbg_Reg_En_0;
output tdo;
output Ext_JTAG_SEL;
output [0:0]\Use_Serial_Unified_Completion.count_reg[4] ;
output [0:0]\Use_Serial_Unified_Completion.completion_status_reg[15] ;
input \Use_BSCAN.PORT_Selector_reg[0]_0 ;
input \Use_BSCAN.PORT_Selector_reg[0]_1 ;
input shift_n_reset;
input \Use_BSCAN.PORT_Selector_reg[0]_2 ;
input [0:0]D;
input \Use_BSCAN.PORT_Selector_reg[0]_3 ;
input sel;
input Dbg_TDO_0;
input Ext_JTAG_TDO;
input [0:0]\Use_Serial_Unified_Completion.count_reg[5] ;
input [0:0]\shift_Count_reg[0] ;
input Scan_Reset;
input Scan_Reset_Sel;
input \Use_BSCAN.PORT_Selector_reg[0]_4 ;
input [0:0]AR;
input Ext_JTAG_TDI;
input [0:0]E;
input [0:0]\command_reg[5] ;
wire [0:0]AR;
wire [0:0]Config_Reg;
wire [0:0]D;
wire Dbg_Disable_0;
wire [0:7]Dbg_Reg_En_0;
wire Dbg_Rst_0;
wire Dbg_Shift_0;
wire Dbg_TDO_0;
wire Debug_SYS_Rst;
wire [0:0]E;
wire Ext_JTAG_SEL;
wire Ext_JTAG_TDI;
wire Ext_JTAG_TDO;
wire Ext_NM_BRK;
wire MDM_SEL;
wire [3:0]PORT_Selector;
wire [3:0]PORT_Selector_1;
wire [0:0]Q;
wire Scan_Reset;
wire Scan_Reset_Sel;
wire [3:0]TDI_Shifter;
wire \Use_BSCAN.Config_Reg_reg[11]_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_12_n_0 ;
wire \Use_BSCAN.Config_Reg_reg[12]_srl13_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_11_n_0 ;
wire \Use_BSCAN.Config_Reg_reg[27]_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_1_n_0 ;
wire \Use_BSCAN.Config_Reg_reg[28]_srl2_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_0_n_0 ;
wire \Use_BSCAN.Config_Reg_reg[4]_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_3_n_0 ;
wire \Use_BSCAN.Config_Reg_reg[5]_srl4_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_2_n_0 ;
wire \Use_BSCAN.Config_Reg_reg_c_0_n_0 ;
wire \Use_BSCAN.Config_Reg_reg_c_10_n_0 ;
wire \Use_BSCAN.Config_Reg_reg_c_11_n_0 ;
wire \Use_BSCAN.Config_Reg_reg_c_12_n_0 ;
wire \Use_BSCAN.Config_Reg_reg_c_1_n_0 ;
wire \Use_BSCAN.Config_Reg_reg_c_2_n_0 ;
wire \Use_BSCAN.Config_Reg_reg_c_3_n_0 ;
wire \Use_BSCAN.Config_Reg_reg_c_4_n_0 ;
wire \Use_BSCAN.Config_Reg_reg_c_5_n_0 ;
wire \Use_BSCAN.Config_Reg_reg_c_6_n_0 ;
wire \Use_BSCAN.Config_Reg_reg_c_7_n_0 ;
wire \Use_BSCAN.Config_Reg_reg_c_8_n_0 ;
wire \Use_BSCAN.Config_Reg_reg_c_9_n_0 ;
wire \Use_BSCAN.Config_Reg_reg_c_n_0 ;
wire \Use_BSCAN.Config_Reg_reg_gate__0_n_0 ;
wire \Use_BSCAN.Config_Reg_reg_gate__1_n_0 ;
wire \Use_BSCAN.Config_Reg_reg_gate_n_0 ;
wire \Use_BSCAN.Config_Reg_reg_n_0_[10] ;
wire \Use_BSCAN.Config_Reg_reg_n_0_[1] ;
wire \Use_BSCAN.Config_Reg_reg_n_0_[25] ;
wire \Use_BSCAN.Config_Reg_reg_n_0_[26] ;
wire \Use_BSCAN.Config_Reg_reg_n_0_[2] ;
wire \Use_BSCAN.Config_Reg_reg_n_0_[30] ;
wire \Use_BSCAN.Config_Reg_reg_n_0_[3] ;
wire \Use_BSCAN.Config_Reg_reg_n_0_[9] ;
wire \Use_BSCAN.PORT_Selector_reg[0]_0 ;
wire \Use_BSCAN.PORT_Selector_reg[0]_1 ;
wire \Use_BSCAN.PORT_Selector_reg[0]_2 ;
wire \Use_BSCAN.PORT_Selector_reg[0]_3 ;
wire \Use_BSCAN.PORT_Selector_reg[0]_4 ;
wire \Use_BSCAN.PORT_Selector_regn_0_0 ;
wire \Use_E2.BSCANE2_I_i_2_n_0 ;
wire [0:0]\Use_Serial_Unified_Completion.completion_status_reg[15] ;
wire [0:0]\Use_Serial_Unified_Completion.count_reg[4] ;
wire [0:0]\Use_Serial_Unified_Completion.count_reg[5] ;
wire [0:0]\command_reg[5] ;
wire config_with_scan_reset;
wire p_0_out;
wire p_20_out__0;
wire p_43_out__0;
wire sel;
wire [0:0]\shift_Count_reg[0] ;
wire shift_n_reset;
wire tdo;
LUT5 #(
.INIT(32'h00000008))
Ext_JTAG_SEL_INST_0
(.I0(sel),
.I1(PORT_Selector[1]),
.I2(PORT_Selector[0]),
.I3(PORT_Selector[3]),
.I4(PORT_Selector[2]),
.O(Ext_JTAG_SEL));
system_mdm_1_0_JTAG_CONTROL JTAG_CONTROL_I
(.AR(config_with_scan_reset),
.D(D),
.Dbg_Reg_En_0(Dbg_Reg_En_0),
.Dbg_Rst_0(Dbg_Rst_0),
.Dbg_Shift_0(Dbg_Shift_0),
.Dbg_TDO_0(Dbg_TDO_0),
.Debug_SYS_Rst(Debug_SYS_Rst),
.E(E),
.Ext_JTAG_TDI(Ext_JTAG_TDI),
.Ext_NM_BRK(Ext_NM_BRK),
.Q(Q),
.Scan_Reset(Scan_Reset),
.Scan_Reset_Sel(Scan_Reset_Sel),
.\Use_BSCAN.PORT_Selector_reg[0] (\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.\Use_BSCAN.PORT_Selector_reg[0]_0 (\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.\Use_BSCAN.PORT_Selector_reg[0]_1 (\Use_BSCAN.PORT_Selector_reg[0]_2 ),
.\Use_BSCAN.PORT_Selector_reg[0]_2 (\Use_BSCAN.PORT_Selector_reg[0]_3 ),
.\Use_BSCAN.PORT_Selector_reg[0]_3 (\Use_BSCAN.PORT_Selector_reg[0]_4 ),
.\Use_BSCAN.PORT_Selector_reg[2] (\Use_E2.BSCANE2_I_i_2_n_0 ),
.\Use_BSCAN.PORT_Selector_reg[3] (PORT_Selector),
.\Use_Serial_Unified_Completion.completion_block_reg_0 (p_43_out__0),
.\Use_Serial_Unified_Completion.completion_status_reg[15]_0 (\Use_Serial_Unified_Completion.completion_status_reg[15] ),
.\Use_Serial_Unified_Completion.count_reg[4]_0 (\Use_Serial_Unified_Completion.count_reg[4] ),
.\Use_Serial_Unified_Completion.count_reg[5]_0 (\Use_Serial_Unified_Completion.count_reg[5] ),
.\command_reg[5]_0 (\command_reg[5] ),
.p_20_out__0(p_20_out__0),
.sel(sel),
.\shift_Count_reg[0]_0 (\shift_Count_reg[0] ),
.tdo(tdo));
FDCE #(
.INIT(1'b0))
\Use_BSCAN.Config_Reg_reg[0]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.CE(1'b1),
.CLR(shift_n_reset),
.D(\Use_BSCAN.Config_Reg_reg_n_0_[1] ),
.Q(Config_Reg));
FDCE \Use_BSCAN.Config_Reg_reg[10]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.CE(1'b1),
.CLR(shift_n_reset),
.D(\Use_BSCAN.Config_Reg_reg_gate__0_n_0 ),
.Q(\Use_BSCAN.Config_Reg_reg_n_0_[10] ));
FDRE \Use_BSCAN.Config_Reg_reg[11]_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_12
(.C(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.CE(1'b1),
.D(\Use_BSCAN.Config_Reg_reg[12]_srl13_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_11_n_0 ),
.Q(\Use_BSCAN.Config_Reg_reg[11]_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_12_n_0 ),
.R(1'b0));
(* srl_bus_name = "U0/\MDM_Core_I1/Use_BSCAN.Config_Reg_reg " *)
(* srl_name = "U0/\MDM_Core_I1/Use_BSCAN.Config_Reg_reg[12]_srl13_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_11 " *)
SRL16E #(
.INIT(16'h0000))
\Use_BSCAN.Config_Reg_reg[12]_srl13_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_11
(.A0(1'b0),
.A1(1'b0),
.A2(1'b1),
.A3(1'b1),
.CE(1'b1),
.CLK(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.D(\Use_BSCAN.Config_Reg_reg_n_0_[25] ),
.Q(\Use_BSCAN.Config_Reg_reg[12]_srl13_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_11_n_0 ));
FDPE #(
.INIT(1'b1))
\Use_BSCAN.Config_Reg_reg[1]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.CE(1'b1),
.D(\Use_BSCAN.Config_Reg_reg_n_0_[2] ),
.PRE(shift_n_reset),
.Q(\Use_BSCAN.Config_Reg_reg_n_0_[1] ));
FDPE #(
.INIT(1'b1))
\Use_BSCAN.Config_Reg_reg[25]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.CE(1'b1),
.D(\Use_BSCAN.Config_Reg_reg_n_0_[26] ),
.PRE(shift_n_reset),
.Q(\Use_BSCAN.Config_Reg_reg_n_0_[25] ));
FDCE \Use_BSCAN.Config_Reg_reg[26]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.CE(1'b1),
.CLR(shift_n_reset),
.D(\Use_BSCAN.Config_Reg_reg_gate_n_0 ),
.Q(\Use_BSCAN.Config_Reg_reg_n_0_[26] ));
FDRE \Use_BSCAN.Config_Reg_reg[27]_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_1
(.C(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.CE(1'b1),
.D(\Use_BSCAN.Config_Reg_reg[28]_srl2_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_0_n_0 ),
.Q(\Use_BSCAN.Config_Reg_reg[27]_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_1_n_0 ),
.R(1'b0));
(* srl_bus_name = "U0/\MDM_Core_I1/Use_BSCAN.Config_Reg_reg " *)
(* srl_name = "U0/\MDM_Core_I1/Use_BSCAN.Config_Reg_reg[28]_srl2_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_0 " *)
SRL16E #(
.INIT(16'h0000))
\Use_BSCAN.Config_Reg_reg[28]_srl2_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_0
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(1'b1),
.CLK(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.D(\Use_BSCAN.Config_Reg_reg_n_0_[30] ),
.Q(\Use_BSCAN.Config_Reg_reg[28]_srl2_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_0_n_0 ));
FDPE #(
.INIT(1'b1))
\Use_BSCAN.Config_Reg_reg[2]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.CE(1'b1),
.D(\Use_BSCAN.Config_Reg_reg_n_0_[3] ),
.PRE(shift_n_reset),
.Q(\Use_BSCAN.Config_Reg_reg_n_0_[2] ));
FDPE #(
.INIT(1'b1))
\Use_BSCAN.Config_Reg_reg[30]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.CE(1'b1),
.D(1'b0),
.PRE(shift_n_reset),
.Q(\Use_BSCAN.Config_Reg_reg_n_0_[30] ));
FDCE \Use_BSCAN.Config_Reg_reg[3]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.CE(1'b1),
.CLR(shift_n_reset),
.D(\Use_BSCAN.Config_Reg_reg_gate__1_n_0 ),
.Q(\Use_BSCAN.Config_Reg_reg_n_0_[3] ));
FDRE \Use_BSCAN.Config_Reg_reg[4]_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_3
(.C(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.CE(1'b1),
.D(\Use_BSCAN.Config_Reg_reg[5]_srl4_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_2_n_0 ),
.Q(\Use_BSCAN.Config_Reg_reg[4]_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_3_n_0 ),
.R(1'b0));
(* srl_bus_name = "U0/\MDM_Core_I1/Use_BSCAN.Config_Reg_reg " *)
(* srl_name = "U0/\MDM_Core_I1/Use_BSCAN.Config_Reg_reg[5]_srl4_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_2 " *)
SRL16E #(
.INIT(16'h0000))
\Use_BSCAN.Config_Reg_reg[5]_srl4_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_2
(.A0(1'b1),
.A1(1'b1),
.A2(1'b0),
.A3(1'b0),
.CE(1'b1),
.CLK(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.D(\Use_BSCAN.Config_Reg_reg_n_0_[9] ),
.Q(\Use_BSCAN.Config_Reg_reg[5]_srl4_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_2_n_0 ));
FDPE #(
.INIT(1'b1))
\Use_BSCAN.Config_Reg_reg[9]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.CE(1'b1),
.D(\Use_BSCAN.Config_Reg_reg_n_0_[10] ),
.PRE(shift_n_reset),
.Q(\Use_BSCAN.Config_Reg_reg_n_0_[9] ));
FDCE \Use_BSCAN.Config_Reg_reg_c
(.C(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.CE(1'b1),
.CLR(shift_n_reset),
.D(1'b1),
.Q(\Use_BSCAN.Config_Reg_reg_c_n_0 ));
FDCE \Use_BSCAN.Config_Reg_reg_c_0
(.C(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.CE(1'b1),
.CLR(shift_n_reset),
.D(\Use_BSCAN.Config_Reg_reg_c_n_0 ),
.Q(\Use_BSCAN.Config_Reg_reg_c_0_n_0 ));
FDCE \Use_BSCAN.Config_Reg_reg_c_1
(.C(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.CE(1'b1),
.CLR(shift_n_reset),
.D(\Use_BSCAN.Config_Reg_reg_c_0_n_0 ),
.Q(\Use_BSCAN.Config_Reg_reg_c_1_n_0 ));
FDCE \Use_BSCAN.Config_Reg_reg_c_10
(.C(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.CE(1'b1),
.CLR(shift_n_reset),
.D(\Use_BSCAN.Config_Reg_reg_c_9_n_0 ),
.Q(\Use_BSCAN.Config_Reg_reg_c_10_n_0 ));
FDCE \Use_BSCAN.Config_Reg_reg_c_11
(.C(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.CE(1'b1),
.CLR(shift_n_reset),
.D(\Use_BSCAN.Config_Reg_reg_c_10_n_0 ),
.Q(\Use_BSCAN.Config_Reg_reg_c_11_n_0 ));
FDCE \Use_BSCAN.Config_Reg_reg_c_12
(.C(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.CE(1'b1),
.CLR(shift_n_reset),
.D(\Use_BSCAN.Config_Reg_reg_c_11_n_0 ),
.Q(\Use_BSCAN.Config_Reg_reg_c_12_n_0 ));
FDCE \Use_BSCAN.Config_Reg_reg_c_2
(.C(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.CE(1'b1),
.CLR(shift_n_reset),
.D(\Use_BSCAN.Config_Reg_reg_c_1_n_0 ),
.Q(\Use_BSCAN.Config_Reg_reg_c_2_n_0 ));
FDCE \Use_BSCAN.Config_Reg_reg_c_3
(.C(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.CE(1'b1),
.CLR(shift_n_reset),
.D(\Use_BSCAN.Config_Reg_reg_c_2_n_0 ),
.Q(\Use_BSCAN.Config_Reg_reg_c_3_n_0 ));
FDCE \Use_BSCAN.Config_Reg_reg_c_4
(.C(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.CE(1'b1),
.CLR(shift_n_reset),
.D(\Use_BSCAN.Config_Reg_reg_c_3_n_0 ),
.Q(\Use_BSCAN.Config_Reg_reg_c_4_n_0 ));
FDCE \Use_BSCAN.Config_Reg_reg_c_5
(.C(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.CE(1'b1),
.CLR(shift_n_reset),
.D(\Use_BSCAN.Config_Reg_reg_c_4_n_0 ),
.Q(\Use_BSCAN.Config_Reg_reg_c_5_n_0 ));
FDCE \Use_BSCAN.Config_Reg_reg_c_6
(.C(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.CE(1'b1),
.CLR(shift_n_reset),
.D(\Use_BSCAN.Config_Reg_reg_c_5_n_0 ),
.Q(\Use_BSCAN.Config_Reg_reg_c_6_n_0 ));
FDCE \Use_BSCAN.Config_Reg_reg_c_7
(.C(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.CE(1'b1),
.CLR(shift_n_reset),
.D(\Use_BSCAN.Config_Reg_reg_c_6_n_0 ),
.Q(\Use_BSCAN.Config_Reg_reg_c_7_n_0 ));
FDCE \Use_BSCAN.Config_Reg_reg_c_8
(.C(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.CE(1'b1),
.CLR(shift_n_reset),
.D(\Use_BSCAN.Config_Reg_reg_c_7_n_0 ),
.Q(\Use_BSCAN.Config_Reg_reg_c_8_n_0 ));
FDCE \Use_BSCAN.Config_Reg_reg_c_9
(.C(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.CE(1'b1),
.CLR(shift_n_reset),
.D(\Use_BSCAN.Config_Reg_reg_c_8_n_0 ),
.Q(\Use_BSCAN.Config_Reg_reg_c_9_n_0 ));
LUT2 #(
.INIT(4'h8))
\Use_BSCAN.Config_Reg_reg_gate
(.I0(\Use_BSCAN.Config_Reg_reg[27]_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_1_n_0 ),
.I1(\Use_BSCAN.Config_Reg_reg_c_1_n_0 ),
.O(\Use_BSCAN.Config_Reg_reg_gate_n_0 ));
LUT2 #(
.INIT(4'h8))
\Use_BSCAN.Config_Reg_reg_gate__0
(.I0(\Use_BSCAN.Config_Reg_reg[11]_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_12_n_0 ),
.I1(\Use_BSCAN.Config_Reg_reg_c_12_n_0 ),
.O(\Use_BSCAN.Config_Reg_reg_gate__0_n_0 ));
LUT2 #(
.INIT(4'h8))
\Use_BSCAN.Config_Reg_reg_gate__1
(.I0(\Use_BSCAN.Config_Reg_reg[4]_MDM_Core_I1_Use_BSCAN.Config_Reg_reg_c_3_n_0 ),
.I1(\Use_BSCAN.Config_Reg_reg_c_3_n_0 ),
.O(\Use_BSCAN.Config_Reg_reg_gate__1_n_0 ));
LUT5 #(
.INIT(32'h00000002))
\Use_BSCAN.PORT_Selector_1[3]_i_1
(.I0(sel),
.I1(PORT_Selector[0]),
.I2(PORT_Selector[1]),
.I3(PORT_Selector[3]),
.I4(PORT_Selector[2]),
.O(MDM_SEL));
FDCE #(
.INIT(1'b0))
\Use_BSCAN.PORT_Selector_1_reg[0]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(MDM_SEL),
.CLR(AR),
.D(TDI_Shifter[0]),
.Q(PORT_Selector_1[0]));
FDCE #(
.INIT(1'b0))
\Use_BSCAN.PORT_Selector_1_reg[1]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(MDM_SEL),
.CLR(AR),
.D(TDI_Shifter[1]),
.Q(PORT_Selector_1[1]));
FDCE #(
.INIT(1'b0))
\Use_BSCAN.PORT_Selector_1_reg[2]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(MDM_SEL),
.CLR(AR),
.D(TDI_Shifter[2]),
.Q(PORT_Selector_1[2]));
FDCE #(
.INIT(1'b0))
\Use_BSCAN.PORT_Selector_1_reg[3]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(MDM_SEL),
.CLR(AR),
.D(TDI_Shifter[3]),
.Q(PORT_Selector_1[3]));
FDCE #(
.INIT(1'b0))
\Use_BSCAN.PORT_Selector_reg[0]
(.C(\Use_BSCAN.PORT_Selector_regn_0_0 ),
.CE(1'b1),
.CLR(AR),
.D(PORT_Selector_1[0]),
.Q(PORT_Selector[0]));
FDCE #(
.INIT(1'b0))
\Use_BSCAN.PORT_Selector_reg[1]
(.C(\Use_BSCAN.PORT_Selector_regn_0_0 ),
.CE(1'b1),
.CLR(AR),
.D(PORT_Selector_1[1]),
.Q(PORT_Selector[1]));
FDCE #(
.INIT(1'b0))
\Use_BSCAN.PORT_Selector_reg[2]
(.C(\Use_BSCAN.PORT_Selector_regn_0_0 ),
.CE(1'b1),
.CLR(AR),
.D(PORT_Selector_1[2]),
.Q(PORT_Selector[2]));
FDCE #(
.INIT(1'b0))
\Use_BSCAN.PORT_Selector_reg[3]
(.C(\Use_BSCAN.PORT_Selector_regn_0_0 ),
.CE(1'b1),
.CLR(AR),
.D(PORT_Selector_1[3]),
.Q(PORT_Selector[3]));
LUT1 #(
.INIT(2'h1))
\Use_BSCAN.PORT_Selector_regi_0
(.I0(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.O(\Use_BSCAN.PORT_Selector_regn_0_0 ));
LUT6 #(
.INIT(64'h0001000000000000))
\Use_BSCAN.TDI_Shifter[3]_i_1
(.I0(PORT_Selector[2]),
.I1(PORT_Selector[3]),
.I2(PORT_Selector[1]),
.I3(PORT_Selector[0]),
.I4(sel),
.I5(\Use_BSCAN.PORT_Selector_reg[0]_2 ),
.O(p_0_out));
FDCE #(
.INIT(1'b0))
\Use_BSCAN.TDI_Shifter_reg[0]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.CE(p_0_out),
.CLR(AR),
.D(TDI_Shifter[1]),
.Q(TDI_Shifter[0]));
FDCE #(
.INIT(1'b0))
\Use_BSCAN.TDI_Shifter_reg[1]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.CE(p_0_out),
.CLR(AR),
.D(TDI_Shifter[2]),
.Q(TDI_Shifter[1]));
FDCE #(
.INIT(1'b0))
\Use_BSCAN.TDI_Shifter_reg[2]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.CE(p_0_out),
.CLR(AR),
.D(TDI_Shifter[3]),
.Q(TDI_Shifter[2]));
FDCE #(
.INIT(1'b0))
\Use_BSCAN.TDI_Shifter_reg[3]
(.C(\Use_BSCAN.PORT_Selector_reg[0]_1 ),
.CE(p_0_out),
.CLR(AR),
.D(Ext_JTAG_TDI),
.Q(TDI_Shifter[3]));
FDPE #(
.INIT(1'b1))
\Use_BSCAN.jtag_disable_reg
(.C(\Use_BSCAN.PORT_Selector_reg[0]_0 ),
.CE(1'b1),
.D(1'b0),
.PRE(config_with_scan_reset),
.Q(Dbg_Disable_0));
LUT6 #(
.INIT(64'hFEFEFEFEEEFFEEEE))
\Use_E2.BSCANE2_I_i_2
(.I0(PORT_Selector[2]),
.I1(PORT_Selector[3]),
.I2(Ext_JTAG_TDO),
.I3(PORT_Selector[0]),
.I4(Config_Reg),
.I5(PORT_Selector[1]),
.O(\Use_E2.BSCANE2_I_i_2_n_0 ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1ns/1ns
//Select Real or Sim
//`define PAGE_SIZE 14'd8192 //Real NAND
`define PAGE_SIZE 14'd9168 //Real NAND ... Full Page
//`define PAGE_SIZE 4 //Simluation
//`define PATTERN_WOM 8'h01
`define PATTERN_WOM cnt_data[7:0]
module NAND_RWE(
input CLKM,
input RST,
input [1:0] pOPER,
input [39:0] pADDR,
input inverse_pattern,
input start,
output done_wire,
output [31:0] latency,
output [31:0] badbits,
output [7:0] Led,
input pattern_usr_0, // 0=addr, 1=usr
input [7:0] pattern_0,
input pattern_usr_1, // 0=addr, 1=usr
input [7:0] pattern_1,
// NAND Wires
output CE_wire, // Chip Enable
output RE_wire, // Rd Enable
output WE_wire, // Wr Enable
output CLE_wire, // Cmd Latch Enable
output ALE_wire, // Adr Latch Enable
output WP_wire, // Wr Protect
input RB_wire, // Ready/Busy : 0=BUSY, 1=READY
inout [7:0] DQ_wire // Data
);
wire CLK;
assign CLK = (pOPER[1:0]==oRS[1:0]) ? CLKx5: CLKM;
wire CLKx5;
assign CLKx5 = (cnt_reset<3 ? 1'b1: 1'b0);
always@(posedge CLKM)
begin
if(RST)
cnt_reset <= 0;
else if ( cnt_reset < 4 )
cnt_reset <= cnt_reset + 1'b1;
else
cnt_reset <= 0;
end
// FSM
parameter
INIT = 30, INIT_T = 31, STOP = 00,
CMDA_0 = 01, CMDA_1 = 02, CMDA_2 = 03,
ADDR_0 = 04, ADDR_1 = 05, ADDR_2 = 06, ADDR_3 = 07,
CMDB_0 = 08, CMDB_1 = 09, CMDB_2 = 10,
WAIT_CYL = 11,
WAIT_RB_0 = 12, WAIT_RB_1 = 13,
DATA_IN_0 = 14, DATA_IN_1 = 15, DATA_IN_2 = 16, DATA_IN_3 = 17, DATA_IN_4 = 18, //WRITE
DATA_OUT_0 = 19, DATA_OUT_1 = 20, DATA_OUT_2 = 21, DATA_OUT_3 = 22, DATA_OUT_4 = 23, DATA_OUT_5 = 24, //READ
RESET_0 = 25, RESET_1 = 26, RESET_2 = 27, RESET_3 = 28, RESET_4 = 29;
parameter
oWR = 0,
oRD = 1,
oER = 2,
oRS = 3;
// Internal Variables
reg [ 2:0] cnt_addr;
reg [ 3:0] cnt_wait;
reg [31:0] cnt_latency;
reg [13:0] cnt_data; //8192=13bit, 9168=14bit
reg [ 2:0] cnt_reset;
reg [31:0] cnt_badbits;
reg [4:0] NSTAT;
wire [13:0] inv_cnt_data;
assign inv_cnt_data = ~cnt_data;
// Address Mux
// 4 4 3 3 2 2 1 1 0 0
// 4[39:32] 3[31:24] 2[23:16] 1[15:8] 0[7:0]
wire [7:0] vADDR;
assign vADDR[7:0]= (pOPER==oRS)?8'h01:( (cnt_addr == 0) ? pADDR[39:32] :
( (cnt_addr == 1) ? pADDR[31:24] :
( (cnt_addr == 2) ? pADDR[23:16] :
((cnt_addr == 3) ? pADDR[15: 8] :
pADDR[ 7: 0]
)
)
)
);
// NAND Reg & Wires
// reg CE; // Chip Enable
reg RE; // Rd Enable
reg WE; // Wr Enable
reg CLE; // Cmd Latch Enable
reg ALE; // Adr Latch Enable
// reg WP; // Wr Protect
wire RB; // Ready/Busy : 0=BUSY, 1=READY
reg [7:0] DQ, DQ_comp; // Data
reg DQ_input_en;
reg RdSt_en; //Status Register Read
assign CE_wire = 0;//CE;
assign RE_wire = RE;
assign WE_wire = WE;
assign CLE_wire = CLE;
assign ALE_wire = ALE;
assign WP_wire = 1;//WP;
assign RB = RB_wire;
// assign DQ_wire[7:0] = (ALE)? vADDR[7:0] : DQ[7:0];
assign DQ_wire[7:0] = (DQ_input_en)? 8'bzzzzzzzz: DQ[7:0];
assign latency[31:0] = cnt_latency[31:0];
assign badbits[31:0] = cnt_badbits[31:0];
//debug led
assign Led[7:0] = {start,done_wire,CLK,NSTAT[4:0]};
assign done_wire = (NSTAT == STOP) ? 1'b1 : 1'b0;
// ASSUME CE = 0 (enabled) already
always@(posedge CLK)
begin
if(RST)
begin
//CE <= 0;
NSTAT <= INIT;
end
else
begin
case (NSTAT)
INIT_T:
begin
NSTAT <= INIT;
end
INIT:
begin
//CE <= 0;
cnt_addr <= 0;
cnt_wait <= 0;
cnt_latency <= 0;
cnt_data <= 0;
cnt_badbits <= 0;
DQ_input_en <= 0;
RdSt_en <= 0;
if( start == 0 )
NSTAT <= INIT_T;
else if( start == 1 )
NSTAT <= CMDA_0;
else
NSTAT <= INIT_T;
end
// FSM: RESET =======================================================
// SEQ: CMDA(FF), RESET_0(tWB+tRST), CMDB(EF), ADDR(01), RESET_1(SET Mode DATA)
RESET_0: // Sent CMD FF, after that...
begin
// NEXT STATE
if( cnt_data < 110-1) // wait tWB+tRST = 5200ns
begin
cnt_data <= cnt_data + 1'b1;
NSTAT <= RESET_0;
end
else if( RB == 1 )
begin
cnt_data <= 0;
NSTAT <= CMDB_0; // Send CMD EF¨
end
else
begin
cnt_data <= 0;
NSTAT <= RESET_0; //wait tRST
end
end
RESET_1: //SET_SET-FEAT : DATA x 4
begin
// ACTION
WE <= 0;
ALE <= 0;
CLE <= 0;
RE <= 1;
cnt_data <= 0; // Reset Data Counter
// NEXT STATE
NSTAT <= RESET_2;
end
RESET_2:
begin
WE <= 0;
DQ <= ( (cnt_data==0) ? 8'h05 : 8'h00 ); //Set MODE 5
NSTAT <= RESET_3;
end
RESET_3:
begin
WE <= 1; //Rising Edge of WE
if (cnt_data < 4-1)
begin
cnt_data <= cnt_data + 1'b1;
NSTAT <= RESET_2;
end
else
begin
cnt_data <= 0; //Stop Data Counter
NSTAT <= RESET_4;
end
end
RESET_4:
begin
//WE <= 0;
//NSTAT <= WAIT_RB_0;// Do NOT wait RB, instead¸more than 1200ns would be precise !
if (cnt_data < 25-1)
begin
cnt_data <= cnt_data + 1'b1;
NSTAT <=RESET_4;
end
else
begin
cnt_data <= 0;
NSTAT <=STOP;
end
end
// FSM: CMDA =======================================================
CMDA_0:
begin
// ACTION
WE <= 0;
ALE <= 0;
CLE <= 1; // Command Latch Open
RE <= 1;
if(RdSt_en) DQ <= 8'h70; //Read Status
else if(pOPER == oRD) DQ <= 8'h00;
else if(pOPER == oWR) DQ <= 8'h80;
else if(pOPER == oER) DQ <= 8'h60;
else DQ <=8'hFF; // RESET CMD
// NEXT STATE
if(RB)
NSTAT <= CMDA_1;
else
NSTAT <= CMDA_0;
end
CMDA_1:
begin
// ACTION
WE <= 1; //Rising edge of WE
// NEXT STATE
NSTAT <= CMDA_2;
end
CMDA_2:
begin
// ACTION
//WE <= 0;
CLE <= 0; // Command Latch Close
// NEXT STATE
if(RdSt_en)
NSTAT <= WAIT_CYL;
else if(pOPER != oRS)
NSTAT <= ADDR_0;
else
NSTAT <= RESET_0;
end
// FSM: ADDR =======================================================
ADDR_0:
begin
// ACTION
WE <= 0;
ALE <= 1; //Address Latch Open
CLE <= 0;
RE <= 1;
// DQ <= vADDR;
//WP <= 1; // LOW = WrPrct
// Counter Config
cnt_wait <= 0;
if (pOPER == oER)
cnt_addr <= 2;
else
cnt_addr <= 0;
// NEXT STATE
NSTAT <= ADDR_1;
end
//cnt_addr trick:
ADDR_1:
begin
WE <= 0;
DQ <= vADDR;
NSTAT <= ADDR_2;
end
ADDR_2:
begin
WE <= 1; //Rising edge of WE
if (pOPER == oRS) // SET-FEAT : only 1 address
begin
NSTAT <= ADDR_3;
end
else //if pOPER == oWR or oRD or oER
begin
if(cnt_addr < 5-1) // ... ( 00 01 ) 02 03 04
begin
cnt_addr <= cnt_addr + 1'b1;
NSTAT <= ADDR_1;
end
else
begin
NSTAT <= ADDR_3;
end
end
end
ADDR_3:
begin
//WE <= 0;
ALE <= 0; //Address Latch Close
if(pOPER == oRD) NSTAT <= CMDB_0;
else if (pOPER == oER) NSTAT <= CMDB_0;
else NSTAT <= WAIT_CYL; //oWR and oRS(SET-FEAT)
end
// FSM: CMDB =======================================================
CMDB_0:
begin
// ACTION
WE <= 0;
ALE <= 0;
CLE <= 1; // Command Latch Open
RE <= 1;
//cnt_latency <= 0; //Reset Latency Counter
if(pOPER == oRD) DQ <= 8'h30;
else if (pOPER == oWR) DQ <= 8'h10;
else if (pOPER == oER) DQ <= 8'hD0;
else DQ <= 8'hEF; // SET-FEATURE
// NEXT STATE
NSTAT <= CMDB_1;
end
CMDB_1:
begin
// ACTION
WE <= 1; //Rising edge of WE
//cnt_latency <= cnt_latency+1;
// NEXT STATE
NSTAT <= CMDB_2;
end
CMDB_2:
begin
// ACTION
//WE <= 1;
CLE <= 0; // Command Latch Close
// NEXT STATE
if (pOPER != oRS)
NSTAT <= WAIT_RB_0;
else
NSTAT <= ADDR_0; // SET-FEAT ADDRESS
//if (pOPER == oRD) NSTAT <= WAIT_RB_0;
//else if (pOPER == oWR) NSTAT <= WAIT_RB_0;
//else if (pOPER == oER) NSTAT <= WAIT_RB_0;
end
// FSM: WAIT_CYL =======================================================
WAIT_CYL: // only for oWR, tADL / oRS(SET-FEAT), tADL / RdSt_en, tWHR
begin
if (cnt_wait < 4'd10-1)
begin
cnt_wait <= cnt_wait + 1'b1;
NSTAT <= WAIT_CYL;
end
else if(RdSt_en) //Rd Status
begin
cnt_wait <= 0;
NSTAT <= DATA_OUT_0;
end
else if(pOPER == oWR) //oWR
begin
cnt_wait <= 0;
NSTAT <= DATA_IN_0;
end
else // RESET - SET-FEAT
begin
cnt_wait <= 0;
NSTAT <= RESET_1;
end
end
// FSM: WAIT_RDY =======================================================
WAIT_RB_0:
begin
//NEXT STATE
if (RB == 0) //while BUSY
begin
cnt_latency <= cnt_latency + 1'b1;
NSTAT <= WAIT_RB_1;
end
else if ( cnt_latency[31:0] < 32'd10 ) //wait RB, but consider tWB (100ns)
begin
cnt_latency <= cnt_latency + 1'b1;
NSTAT <= WAIT_RB_0;
end
else
begin
NSTAT <= WAIT_RB_1;
end
end
WAIT_RB_1:
begin
//NEXT STATE
if (RB == 0) //while BUSY
begin
cnt_latency <= cnt_latency + 1'b1;
NSTAT <= WAIT_RB_1;
end
else
begin
//cnt_latency <= 0; //Stop Latency counter
if (pOPER == oWR || pOPER == oER)
begin
RdSt_en <= 1;
NSTAT <= CMDA_0; //Read Status
end
else if (pOPER == oRD)
begin
cnt_wait <= 0;
NSTAT <= DATA_OUT_0;
end
else
begin
NSTAT <= STOP;
end
end
end
// ToDo: ERROR check on status bit !!!!!
// FSM: DATA_IN =======================================================
//WRITE (think you're NAND) : only for oWR, Use WE(Write Enable)
DATA_IN_0:
begin
// ACTION
WE <= 0;
ALE <= 0;
CLE <= 0;
RE <= 1;
DQ_input_en <= 0;
cnt_data <= 0; // Reset Data Counter
// NEXT STATE
NSTAT <= DATA_IN_1;
end
DATA_IN_1:
begin
WE <= 0;
if ( inverse_pattern==0 && pattern_usr_0==0 ) //norm address
DQ <= cnt_data[7:0];
else if ( inverse_pattern==1 && pattern_usr_1==0 ) //inv address
DQ <= inv_cnt_data[7:0];
else if ( inverse_pattern==0 && pattern_usr_0==1 ) //norm =ptrn_0
DQ <= pattern_0;
else//if( inverse_pattern==1 && pattern_usr_1==1 ) //inv =ptrn_1
DQ <= pattern_1;
/*
if(inverse_pattern)
DQ <= inv_cnt_data[7:0]; //use addr as data
else
DQ <= cnt_data[7:0];
*/
// DQ <= `PATTERN_WOM; //WOM-CODE Test Baseline
//DQ <= cnt_data[7:0];
NSTAT <= DATA_IN_2;
end
DATA_IN_2:
begin
WE <= 1; //Rising Edge of WE
if (cnt_data < `PAGE_SIZE-1)
begin
cnt_data <= cnt_data + 1'b1;
NSTAT <= DATA_IN_3;
end
else
begin
cnt_data <= 0; //Stop Data Counter
NSTAT <= DATA_IN_4;
end
end
DATA_IN_3: //add one more clock for stability
begin
NSTAT <= DATA_IN_1;
end
DATA_IN_4:
begin
//WE <= 1;
NSTAT <= CMDB_0;
end
// FSM: DATA_OUT =======================================================
//READ (think you're NAND) : only for oRD, Use RE(Read Enable)
DATA_OUT_0: // tRR wait
begin
if (cnt_wait < 4'd10-1)
begin
cnt_wait <= cnt_wait + 1'b1;
NSTAT <= DATA_OUT_0;
end
else
begin
cnt_wait <= 0;
NSTAT <= DATA_OUT_1;
end
end
DATA_OUT_1:
begin
// ACTION
cnt_wait <= 0;
RE <= 1;
ALE <= 0;
CLE <= 0;
WE <= 1;
cnt_data <= 0; // Reset Data Counter
cnt_badbits <= 0;
DQ <= 0;
DQ_comp <= 0;
DQ_input_en <= 1;
// NEXT STATE
NSTAT <= DATA_OUT_2;
end
DATA_OUT_2:
begin
RE <= 1;
/* //DEBUG
if( cnt_data == 14'h201 )
begin
cnt_badbits <= {DQ_comp[7:0], DQ_wire[7:0]};
end
*/
//COUNT BIT
if(RdSt_en && cnt_data==1) //when Rd Status register
begin
cnt_badbits[15:0] <= { 8'd0, DQ_wire[7:0] };
end
else if(cnt_data != 0) //when normal read
begin
cnt_badbits <= cnt_badbits + ( DQ_comp[7] ^ DQ_wire[7] ) + ( DQ_comp[6] ^ DQ_wire[6] )
+ ( DQ_comp[5] ^ DQ_wire[5] ) + ( DQ_comp[4] ^ DQ_wire[4] )
+ ( DQ_comp[3] ^ DQ_wire[3] ) + ( DQ_comp[2] ^ DQ_wire[2] )
+ ( DQ_comp[1] ^ DQ_wire[1] ) + ( DQ_comp[0] ^ DQ_wire[0] );
end
if (cnt_data == `PAGE_SIZE)
begin
NSTAT <= DATA_OUT_5;
end
else if(RdSt_en && cnt_data==1)
begin
NSTAT <= DATA_OUT_5;
end
else
begin
NSTAT <= DATA_OUT_3;
end
end
DATA_OUT_3:
begin
RE <= 0; // falling edge of RE#
if ( inverse_pattern==0 && pattern_usr_0==0 ) //norm address
DQ_comp[7:0] <= cnt_data[7:0];
else if ( inverse_pattern==1 && pattern_usr_1==0 ) //inv address
DQ_comp[7:0] <= inv_cnt_data[7:0];
else if ( inverse_pattern==0 && pattern_usr_0==1 ) //norm =ptrn_0
DQ_comp[7:0] <= pattern_0;
else//if( inverse_pattern==1 && pattern_usr_1==1 ) //inv =ptrn_1
DQ_comp[7:0] <= pattern_1;
//DQ_comp[7:0] <= `PATTERN_WOM; //Compare-data : WOM-CODE Test Baseline
//DQ_comp <= cnt_data[7:0]; //Compare-data
/*
if(inverse_pattern)
DQ_comp <= inv_cnt_data[7:0]; //Compare-data
else
DQ_comp <= cnt_data[7:0]; //Compare-data
*/
cnt_data <= cnt_data + 1'b1;
NSTAT <= DATA_OUT_4;
/*
if (cnt_data < `PAGE_SIZE-1)
begin
cnt_data <= cnt_data + 1'b1;
NSTAT <= DATA_OUT_4;
end
else
begin
cnt_data <= 0;
NSTAT <= DATA_OUT_5;
end
*/
end
DATA_OUT_4: //add more clocks for stable DQ sensing
begin
if (cnt_wait < 4'd6-1)
begin
cnt_wait <= cnt_wait + 1'b1;
NSTAT <= DATA_OUT_4;
end
else
begin
cnt_wait <= 0;
NSTAT <= DATA_OUT_2;
end
end
DATA_OUT_5:
begin
RE <= 1;
DQ_input_en <= 0;
RdSt_en <= 0;
NSTAT <= STOP;
end
//ToDo: Data Verification
// FSM: STOP =======================================================
STOP:
begin
if(start==1)
NSTAT <= STOP;
else if(start==0)
NSTAT <= INIT;
else
NSTAT <= STOP;
end
default:
begin
NSTAT <= INIT_T;
end
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR3B_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__NOR3B_PP_BLACKBOX_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nor3b (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR3B_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAP_FUNCTIONAL_V
`define SKY130_FD_SC_HD__TAP_FUNCTIONAL_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__tap ();
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAP_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND2_LP_V
`define SKY130_FD_SC_LP__AND2_LP_V
/**
* and2: 2-input AND.
*
* Verilog wrapper for and2 with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and2_lp (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and2_lp (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND2_LP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2111AI_PP_SYMBOL_V
`define SKY130_FD_SC_LP__O2111AI_PP_SYMBOL_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o2111ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input C1 ,
input D1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2111AI_PP_SYMBOL_V
|
// ============================================================
// File Name: VGAFrequency.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.0.0 Build 211 04/27/2016 SJ Lite Edition
// ************************************************************
//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module VGAFrequency (
areset,
inclk0,
c0);
input areset;
input inclk0;
output c0;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "108.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "108.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "VGAFrequency.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "25"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "54"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL VGAFrequency.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGAFrequency.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGAFrequency.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGAFrequency.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGAFrequency.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGAFrequency_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGAFrequency_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKBUF_16_V
`define SKY130_FD_SC_LS__CLKBUF_16_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog wrapper for clkbuf with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__clkbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__clkbuf_16 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__clkbuf_16 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__clkbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKBUF_16_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRBN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__DLRBN_BEHAVIORAL_PP_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_lp__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dlrbn (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire intgate ;
reg notifier ;
wire D_delayed ;
wire GATE_N_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intgate, GATE_N_delayed );
sky130_fd_sc_lp__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, intgate, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRBN_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR2_TB_V
`define SKY130_FD_SC_LP__OR2_TB_V
/**
* or2: 2-input OR.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_lp__or2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR2_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFRBP_SYMBOL_V
`define SKY130_FD_SC_HS__DFRBP_SYMBOL_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dfrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFRBP_SYMBOL_V
|
/* -------------------------------------------------------------------------------
* (C)2012 Korotkyi Ievgen
* National Technical University of Ukraine "Kiev Polytechnic Institute"
* -------------------------------------------------------------------------------
*
* *** NOT FOR SYNTHESIS ***
*
* Traffic Sink
*
* Collects incoming packets and produces statistics.
*
* - check flit id's are sequential
*
*/
//`include "parameters.v"
`timescale 1 ps/ 1 ps
`include "types.v"
`include "LAG_functions.v"
`include "parameters.v"
module LAG_traffic_sink (flit_in, cntrl_out, rec_count, stats, clk, rst_n);
parameter xdim = 4;
parameter ydim = 4;
parameter xpos = 0;
parameter ypos = 0;
parameter warmup_packets = 100;
parameter measurement_packets = 1000;
parameter router_num_pls_on_exit = 1;
input flit_t [router_num_pls_on_exit-1:0] flit_in;
output chan_cntrl_t cntrl_out;
output sim_stats_t stats;
input clk, rst_n;
output integer rec_count;
logic [7:0] expected_flit_id [router_num_pls_on_exit-1:0]; //in test version our packets is only 255 flit length
logic [15:0] expected_packet_id[router_num_pls_on_exit-1:0];
logic [15:0] arrived_packet_id[router_num_pls_on_exit-1:0];
logic [31:0] head_injection_time [router_num_pls_on_exit-1:0];
logic [31:0] latency, sys_time;
logic [31:0] crc_computed [router_num_pls_on_exit-1:0];
logic [31:0] crc_received [router_num_pls_on_exit-1:0];
integer j, i;
integer error_count;
genvar ch;
for (ch=0; ch<router_num_pls; ch++) begin:flow_control
always@(posedge clk) begin
if (!rst_n) begin
cntrl_out.credits[ch] <= 0;
end else begin
if (flit_in[ch].control.valid) begin
if (ch < router_num_pls_on_exit) begin
cntrl_out.credits[ch] <= 1;
end else begin
$display ("%m: Error: Flit Channel ID is out-of-range for exit from network!");
$display ("Channel ID = %1d (router_num_pls_on_exit=%1d)", ch, router_num_pls_on_exit);
$finish;
end
end else begin
cntrl_out.credits[ch] <= 0;
end
end
end
end
always@(posedge clk) begin
if (!rst_n) begin
rec_count=0;
stats.total_latency=0;
stats.total_hops=0;
stats.max_hops=0;
stats.min_hops=MAXINT;
stats.max_latency=0;
stats.min_latency=MAXINT;
stats.measure_start=-1;
stats.measure_end=-1;
stats.flit_count=0;
error_count = 0;
for (j=0; j<router_num_pls_on_exit; j++) begin
expected_flit_id[j]=1;
expected_packet_id[j]=1;
head_injection_time[j]='0;
crc_computed[i] = '0;
crc_received[i] = '0;
end
for (j=0; j<=100; j++) begin
stats.lat_freq[j]=0;
end
sys_time = 0;
end else begin // if (!rst_n)
#3000 sys_time++;
for (i=0; i<router_num_pls_on_exit; i++) begin
if (flit_in[i].control.valid) begin
//
// check flits for each packet are received in order
//
if(~flit_in[i].control.head && expected_flit_id[i] != flit_in[i].data[7:0]) begin
error_count++;
$display("%m Error: flit out of sequence.");
$display("-- Flit ID = %1d, Expected = %1d", flit_in[i].data[7:0], expected_flit_id[i]);
end
/*$display($time, " ----> Flit %d is received in x[%1d]y[%1d], ch=%1d", flit_in[i].data[7:0], xpos, ypos, i);
$display("****************************************************************************"); */
if(expected_flit_id[i] > 1 && expected_flit_id[i] < 9) crc_computed[i] = crc32(flit_in[i].data, crc_computed[i]);
if(expected_flit_id[i] == 1) begin
if(~flit_in[i].control.head) begin
error_count++;
$display("%m Error: flit out of sequence. Expected 1st flit");
end
head_injection_time[i] = '0;
expected_flit_id[i]++;
end else if (expected_flit_id[i] == 2) begin
arrived_packet_id[i][7:0] = flit_in[i].data[15:8];
expected_flit_id[i]++;
end else if (expected_flit_id[i] == 3) begin
arrived_packet_id[i][15:8] = flit_in[i].data[15:8];
if ((arrived_packet_id[i] > warmup_packets) && (stats.measure_start==-1)) stats.measure_start = sys_time - 2;
expected_flit_id[i]++;
end else if (expected_flit_id[i] == 4) begin
if(xpos != flit_in[i].data[11:8] && ypos != flit_in[i].data[15:12] )begin
error_count++;
$display("Packet arrived at wrong destination");
end
expected_flit_id[i]++;
end else if (expected_flit_id[i] == 5) begin
head_injection_time[i][7:0] = flit_in[i].data[15:8];
expected_flit_id[i]++;
end else if (expected_flit_id[i] == 6) begin
head_injection_time[i][15:8] = flit_in[i].data[15:8];
expected_flit_id[i]++;
end else if (expected_flit_id[i] == 7) begin
head_injection_time[i][23:16] = flit_in[i].data[15:8];
expected_flit_id[i]++;
end else if (expected_flit_id[i] == 8) begin
head_injection_time[i][31:24] = flit_in[i].data[15:8];
expected_flit_id[i]++;
end else if (expected_flit_id[i] == 9) begin
crc_received[i][7:0] = flit_in[i].data[15:8];
expected_flit_id[i]++;
end else if (expected_flit_id[i] == 10) begin
crc_received[i][15:8] = flit_in[i].data[15:8];
expected_flit_id[i]++;
end else if (expected_flit_id[i] == 11) begin
crc_received[i][23:16] = flit_in[i].data[15:8];
expected_flit_id[i]++;
end else if (expected_flit_id[i] == 12) begin //last (tail) flit
crc_received[i][31:24] = flit_in[i].data[15:8];
if (crc_received[i] != crc_computed[i]) begin
error_count++;
$display("%m Error: checksum do not match");
$display("--------> crc_computed = %h, crc_received = %h", crc_computed[i], crc_received[i]);
$finish;
end else begin
/*$display($time, " ---------> Packet is received in x[%1d]y[%1d], ch=%1d", xpos, ypos, i);
$display("****************************************************************************"); */
end
crc_computed[i] = '0;
crc_received[i] = '0;
expected_flit_id[i] = 1;
expected_packet_id[i]++;
//----------> count statistics
if ((arrived_packet_id[i] > warmup_packets) &&
(arrived_packet_id[i] <= warmup_packets + measurement_packets)) begin
rec_count++;
// time last measurement packet was received
stats.measure_end = sys_time;
//
// gather latency stats.
//
latency = sys_time - head_injection_time[i];
stats.total_latency = stats.total_latency + latency;
stats.min_latency = min (stats.min_latency, latency);
stats.max_latency = max (stats.max_latency, latency);
//
// display progress estimate
//
if (rec_count%(measurement_packets/100)==0)
$display ("%1d: %m: %1.2f%% complete (this packet's latency was %1d)", sys_time,
$itor(rec_count*100)/$itor(measurement_packets),
latency);
//
// bin latencies
//
stats.lat_freq[min(latency, 100)]++;
end
end
if(error_count) begin
$display("At least %1d errors occured during simulation", error_count);
$finish;
end
// count all flits received in measurement period
if (arrived_packet_id[i] <= warmup_packets + measurement_packets)
if (stats.measure_start!=-1) stats.flit_count++;
end // if flit valid
end //for
end //if(!rst_n)
end //always
endmodule
|
module TOP(CLK, RST, IN, IN2, reg1, OUT);
input CLK, RST, IN, IN2;
reg reg1,reg2,reg3;
output reg1,OUT;
wire in1;
wire OUT;
wire IN;
wire IN2;
always @(posedge CLK or negedge RST) begin
if(RST) begin
reg1 <= 1'b0;
end else begin
reg1 <= IN;
end
end
always @(posedge CLK or negedge RST) begin
if(RST) begin
reg2 <= 1'b0;
end else begin
reg2 <= func1(reg1);
end
end
SUB sub(CLK,RST,in1,OUT);
SUB2 ccc(CLK,RST,in1);
function func1;
input bit1;
if(bit1)
func1 = !bit1;
else
func1 = bit1;
endfunction
endmodule
module SUB(CLK,RST,IN, OUT);
input CLK, RST, IN;
output OUT;
reg reg1;
wire IN;
wire OUT = reg1;
always @(posedge CLK or negedge RST) begin
if(RST) begin
reg1 <= 1'b0;
end else begin
reg1 <= 1'b1;
end
end
endmodule
module SUB2(input CLK,input RST,input IN, output OUT);
reg reg1;
wire IN;
always @(posedge CLK or negedge RST) begin
if(RST) begin
reg1 <= 1'b0;
end else if(IN) begin
reg1 <= 1'b0;
end else begin
reg1 <= 1'b1;
end
end
endmodule
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2014, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//
//-------------------------------------------------------------------
//
// Filename : intra_pred.v
// Author : Liu Cong
// Created : 2014-4
// Description : do the reference pixel PADDING and FILTER
//
//-------------------------------------------------------------------
//
// Modified : 2014-08-25 by HLL
// Description : prediction to chroma supported
//
// $Id$
//
//-------------------------------------------------------------------
`include "./enc_defines.v"
module intra_pred(
clk,rst_n,
start_i,
done_o,
mode_i,
pre_sel_i,
size_i,
i4x4_x_i,
i4x4_y_i,
ref_tl_i,
ref_t00_i,ref_t01_i,ref_t02_i,ref_t03_i,ref_t04_i,ref_t05_i,ref_t06_i,ref_t07_i,
ref_t08_i,ref_t09_i,ref_t10_i,ref_t11_i,ref_t12_i,ref_t13_i,ref_t14_i,ref_t15_i,
ref_t16_i,ref_t17_i,ref_t18_i,ref_t19_i,ref_t20_i,ref_t21_i,ref_t22_i,ref_t23_i,
ref_t24_i,ref_t25_i,ref_t26_i,ref_t27_i,ref_t28_i,ref_t29_i,ref_t30_i,ref_t31_i,
ref_r00_i,ref_r01_i,ref_r02_i,ref_r03_i,ref_r04_i,ref_r05_i,ref_r06_i,ref_r07_i,
ref_r08_i,ref_r09_i,ref_r10_i,ref_r11_i,ref_r12_i,ref_r13_i,ref_r14_i,ref_r15_i,
ref_r16_i,ref_r17_i,ref_r18_i,ref_r19_i,ref_r20_i,ref_r21_i,ref_r22_i,ref_r23_i,
ref_r24_i,ref_r25_i,ref_r26_i,ref_r27_i,ref_r28_i,ref_r29_i,ref_r30_i,ref_r31_i,
ref_l00_i,ref_l01_i,ref_l02_i,ref_l03_i,ref_l04_i,ref_l05_i,ref_l06_i,ref_l07_i,
ref_l08_i,ref_l09_i,ref_l10_i,ref_l11_i,ref_l12_i,ref_l13_i,ref_l14_i,ref_l15_i,
ref_l16_i,ref_l17_i,ref_l18_i,ref_l19_i,ref_l20_i,ref_l21_i,ref_l22_i,ref_l23_i,
ref_l24_i,ref_l25_i,ref_l26_i,ref_l27_i,ref_l28_i,ref_l29_i,ref_l30_i,ref_l31_i,
ref_d00_i,ref_d01_i,ref_d02_i,ref_d03_i,ref_d04_i,ref_d05_i,ref_d06_i,ref_d07_i,
ref_d08_i,ref_d09_i,ref_d10_i,ref_d11_i,ref_d12_i,ref_d13_i,ref_d14_i,ref_d15_i,
ref_d16_i,ref_d17_i,ref_d18_i,ref_d19_i,ref_d20_i,ref_d21_i,ref_d22_i,ref_d23_i,
ref_d24_i,ref_d25_i,ref_d26_i,ref_d27_i,ref_d28_i,ref_d29_i,ref_d30_i,ref_d31_i,
pred_00_o,pred_01_o,pred_02_o,pred_03_o,
pred_10_o,pred_11_o,pred_12_o,pred_13_o,
pred_20_o,pred_21_o,pred_22_o,pred_23_o,
pred_30_o,pred_31_o,pred_32_o,pred_33_o,
//pre_sel_o
size_o,
i4x4_x_o,
i4x4_y_o
);
//********************************* INPUT/OUTPUT DECLARATION *****************************************
input clk,rst_n;
input start_i;
output done_o;
input [5:0] mode_i; //total 35 modes
input [1:0] pre_sel_i;
input [1:0] size_i;//00:4x4 01:8x8 10:16x16 11:32x32
input [3:0] i4x4_x_i,i4x4_y_i;//(x,y) of 4x4 block
input [`PIXEL_WIDTH-1:0] ref_tl_i;
input [`PIXEL_WIDTH-1:0] ref_t00_i,ref_t01_i,ref_t02_i,ref_t03_i,ref_t04_i,ref_t05_i,ref_t06_i,ref_t07_i;
input [`PIXEL_WIDTH-1:0] ref_t08_i,ref_t09_i,ref_t10_i,ref_t11_i,ref_t12_i,ref_t13_i,ref_t14_i,ref_t15_i;
input [`PIXEL_WIDTH-1:0] ref_t16_i,ref_t17_i,ref_t18_i,ref_t19_i,ref_t20_i,ref_t21_i,ref_t22_i,ref_t23_i;
input [`PIXEL_WIDTH-1:0] ref_t24_i,ref_t25_i,ref_t26_i,ref_t27_i,ref_t28_i,ref_t29_i,ref_t30_i,ref_t31_i;
input [`PIXEL_WIDTH-1:0] ref_r00_i,ref_r01_i,ref_r02_i,ref_r03_i,ref_r04_i,ref_r05_i,ref_r06_i,ref_r07_i;
input [`PIXEL_WIDTH-1:0] ref_r08_i,ref_r09_i,ref_r10_i,ref_r11_i,ref_r12_i,ref_r13_i,ref_r14_i,ref_r15_i;
input [`PIXEL_WIDTH-1:0] ref_r16_i,ref_r17_i,ref_r18_i,ref_r19_i,ref_r20_i,ref_r21_i,ref_r22_i,ref_r23_i;
input [`PIXEL_WIDTH-1:0] ref_r24_i,ref_r25_i,ref_r26_i,ref_r27_i,ref_r28_i,ref_r29_i,ref_r30_i,ref_r31_i;
input [`PIXEL_WIDTH-1:0] ref_l00_i,ref_l01_i,ref_l02_i,ref_l03_i,ref_l04_i,ref_l05_i,ref_l06_i,ref_l07_i;
input [`PIXEL_WIDTH-1:0] ref_l08_i,ref_l09_i,ref_l10_i,ref_l11_i,ref_l12_i,ref_l13_i,ref_l14_i,ref_l15_i;
input [`PIXEL_WIDTH-1:0] ref_l16_i,ref_l17_i,ref_l18_i,ref_l19_i,ref_l20_i,ref_l21_i,ref_l22_i,ref_l23_i;
input [`PIXEL_WIDTH-1:0] ref_l24_i,ref_l25_i,ref_l26_i,ref_l27_i,ref_l28_i,ref_l29_i,ref_l30_i,ref_l31_i;
input [`PIXEL_WIDTH-1:0] ref_d00_i,ref_d01_i,ref_d02_i,ref_d03_i,ref_d04_i,ref_d05_i,ref_d06_i,ref_d07_i;
input [`PIXEL_WIDTH-1:0] ref_d08_i,ref_d09_i,ref_d10_i,ref_d11_i,ref_d12_i,ref_d13_i,ref_d14_i,ref_d15_i;
input [`PIXEL_WIDTH-1:0] ref_d16_i,ref_d17_i,ref_d18_i,ref_d19_i,ref_d20_i,ref_d21_i,ref_d22_i,ref_d23_i;
input [`PIXEL_WIDTH-1:0] ref_d24_i,ref_d25_i,ref_d26_i,ref_d27_i,ref_d28_i,ref_d29_i,ref_d30_i,ref_d31_i;
output [`PIXEL_WIDTH-1:0] pred_00_o,pred_01_o,pred_02_o,pred_03_o;
output [`PIXEL_WIDTH-1:0] pred_10_o,pred_11_o,pred_12_o,pred_13_o;
output [`PIXEL_WIDTH-1:0] pred_20_o,pred_21_o,pred_22_o,pred_23_o;
output [`PIXEL_WIDTH-1:0] pred_30_o,pred_31_o,pred_32_o,pred_33_o;
//pre_sel_o
output [1:0] size_o;
output [3:0] i4x4_x_o, i4x4_y_o;
//*******************************************************************************************************
//*************************************** REG/WIRE DELARATION ********************************************
reg [1:0] size_o;
reg [3:0] i4x4_x_o, i4x4_y_o;
reg start_r0,start_r1,done_o;
reg signed [6:0] pred_angle;
reg signed [6:0] idx0, idx1, idx2, idx3;
reg signed [10:0] fact0,fact1,fact2,fact3;
reg [4:0] ifact0,ifact1,ifact2,ifact3;
reg [5:0] mode_r0,mode_r1;
reg [1:0] size_r0,size_r1;
reg signed [5:0] delta_idx_r;
reg [4:0] y0,y1,y2,y3,x0,x1,x2,x3;
wire signed [5:0] y0_sign_w,y1_sign_w,y2_sign_w,y3_sign_w;
wire signed [5:0] x0_sign_w,x1_sign_w,x2_sign_w,x3_sign_w;
reg [4:0] y0_r0,y1_r0,y2_r0,y3_r0,x0_r0,x1_r0,x2_r0,x3_r0;
reg [4:0] y0_r1,y1_r1,y2_r1,y3_r1,x0_r1,x1_r1,x2_r1,x3_r1;
reg [3:0] i4x4_x_r,i4x4_y_r;
reg [3:0] i4x4_x_r1,i4x4_y_r1;
reg [`PIXEL_WIDTH-1:0] dc_value_r;
reg [`PIXEL_WIDTH-1:0] top0_r, top1_r, top2_r, top3_r;
reg [`PIXEL_WIDTH-1:0] left0_r,left1_r,left2_r,left3_r;
reg [`PIXEL_WIDTH-1:0] ref_l00_w,ref_l04_w,ref_l08_w,ref_l12_w,ref_l16_w,ref_l20_w,ref_l24_w,ref_l28_w;
reg [`PIXEL_WIDTH-1:0] ref_l01_w,ref_l05_w,ref_l09_w,ref_l13_w,ref_l17_w,ref_l21_w,ref_l25_w,ref_l29_w;
reg [`PIXEL_WIDTH-1:0] ref_l02_w,ref_l06_w,ref_l10_w,ref_l14_w,ref_l18_w,ref_l22_w,ref_l26_w,ref_l30_w;
reg [`PIXEL_WIDTH-1:0] ref_l03_w,ref_l07_w,ref_l11_w,ref_l15_w,ref_l19_w,ref_l23_w,ref_l27_w,ref_l31_w;
reg [`PIXEL_WIDTH-1:0] ref_l32_w,ref_l36_w,ref_l40_w,ref_l44_w,ref_l48_w,ref_l52_w,ref_l56_w,ref_l60_w;
reg [`PIXEL_WIDTH-1:0] ref_l33_w,ref_l37_w,ref_l41_w,ref_l45_w,ref_l49_w,ref_l53_w,ref_l57_w,ref_l61_w;
reg [`PIXEL_WIDTH-1:0] ref_l34_w,ref_l38_w,ref_l42_w,ref_l46_w,ref_l50_w,ref_l54_w,ref_l58_w,ref_l62_w;
reg [`PIXEL_WIDTH-1:0] ref_l35_w,ref_l39_w,ref_l43_w,ref_l47_w,ref_l51_w,ref_l55_w,ref_l59_w,ref_l63_w;
reg [`PIXEL_WIDTH-1:0] ref_t00_w,ref_t04_w,ref_t08_w,ref_t12_w,ref_t16_w,ref_t20_w,ref_t24_w,ref_t28_w;
reg [`PIXEL_WIDTH-1:0] ref_t01_w,ref_t05_w,ref_t09_w,ref_t13_w,ref_t17_w,ref_t21_w,ref_t25_w,ref_t29_w;
reg [`PIXEL_WIDTH-1:0] ref_t02_w,ref_t06_w,ref_t10_w,ref_t14_w,ref_t18_w,ref_t22_w,ref_t26_w,ref_t30_w;
reg [`PIXEL_WIDTH-1:0] ref_t03_w,ref_t07_w,ref_t11_w,ref_t15_w,ref_t19_w,ref_t23_w,ref_t27_w,ref_t31_w;
reg [`PIXEL_WIDTH-1:0] ref_t32_w,ref_t36_w,ref_t40_w,ref_t44_w,ref_t48_w,ref_t52_w,ref_t56_w,ref_t60_w;
reg [`PIXEL_WIDTH-1:0] ref_t33_w,ref_t37_w,ref_t41_w,ref_t45_w,ref_t49_w,ref_t53_w,ref_t57_w,ref_t61_w;
reg [`PIXEL_WIDTH-1:0] ref_t34_w,ref_t38_w,ref_t42_w,ref_t46_w,ref_t50_w,ref_t54_w,ref_t58_w,ref_t62_w;
reg [`PIXEL_WIDTH-1:0] ref_t35_w,ref_t39_w,ref_t43_w,ref_t47_w,ref_t51_w,ref_t55_w,ref_t59_w,ref_t63_w;
reg [`PIXEL_WIDTH-1:0] ref_00_r;
reg [`PIXEL_WIDTH-1:0] ref_01_r,ref_05_r,ref_09_r,ref_13_r,ref_17_r,ref_21_r,ref_25_r,ref_29_r;
reg [`PIXEL_WIDTH-1:0] ref_02_r,ref_06_r,ref_10_r,ref_14_r,ref_18_r,ref_22_r,ref_26_r,ref_30_r;
reg [`PIXEL_WIDTH-1:0] ref_03_r,ref_07_r,ref_11_r,ref_15_r,ref_19_r,ref_23_r,ref_27_r,ref_31_r;
reg [`PIXEL_WIDTH-1:0] ref_04_r,ref_08_r,ref_12_r,ref_16_r,ref_20_r,ref_24_r,ref_28_r,ref_32_r;
reg [`PIXEL_WIDTH-1:0] ref_33_r,ref_37_r,ref_41_r,ref_45_r,ref_49_r,ref_53_r,ref_57_r,ref_61_r;
reg [`PIXEL_WIDTH-1:0] ref_34_r,ref_38_r,ref_42_r,ref_46_r,ref_50_r,ref_54_r,ref_58_r,ref_62_r;
reg [`PIXEL_WIDTH-1:0] ref_35_r,ref_39_r,ref_43_r,ref_47_r,ref_51_r,ref_55_r,ref_59_r,ref_63_r;
reg [`PIXEL_WIDTH-1:0] ref_36_r,ref_40_r,ref_44_r,ref_48_r,ref_52_r,ref_56_r,ref_60_r,ref_64_r;
reg [`PIXEL_WIDTH-1:0] ref_x01_r,ref_x05_r,ref_x09_r,ref_x13_r,ref_x17_r,ref_x21_r,ref_x25_r,ref_x29_r;
reg [`PIXEL_WIDTH-1:0] ref_x02_r,ref_x06_r,ref_x10_r,ref_x14_r,ref_x18_r,ref_x22_r,ref_x26_r,ref_x30_r;
reg [`PIXEL_WIDTH-1:0] ref_x03_r,ref_x07_r,ref_x11_r,ref_x15_r,ref_x19_r,ref_x23_r,ref_x27_r,ref_x31_r;
reg [`PIXEL_WIDTH-1:0] ref_x04_r,ref_x08_r,ref_x12_r,ref_x16_r,ref_x20_r,ref_x24_r,ref_x28_r,ref_x32_r;
reg [`PIXEL_WIDTH-1:0] ref_0_0,ref_0_1,ref_0_2,ref_0_3,ref_0_4;
reg [`PIXEL_WIDTH-1:0] ref_1_0,ref_1_1,ref_1_2,ref_1_3,ref_1_4;
reg [`PIXEL_WIDTH-1:0] ref_2_0,ref_2_1,ref_2_2,ref_2_3,ref_2_4;
reg [`PIXEL_WIDTH-1:0] ref_3_0,ref_3_1,ref_3_2,ref_3_3,ref_3_4;
reg [`PIXEL_WIDTH-1:0] pred_00_o,pred_01_o,pred_02_o,pred_03_o;
reg [`PIXEL_WIDTH-1:0] pred_10_o,pred_11_o,pred_12_o,pred_13_o;
reg [`PIXEL_WIDTH-1:0] pred_20_o,pred_21_o,pred_22_o,pred_23_o;
reg [`PIXEL_WIDTH-1:0] pred_30_o,pred_31_o,pred_32_o,pred_33_o;
reg [`PIXEL_WIDTH-1:0] pre_0_0_w,pre_0_1_w,pre_0_2_w,pre_0_3_w;
reg [`PIXEL_WIDTH-1:0] pre_1_0_w,pre_1_1_w,pre_1_2_w,pre_1_3_w;
reg [`PIXEL_WIDTH-1:0] pre_2_0_w,pre_2_1_w,pre_2_2_w,pre_2_3_w;
reg [`PIXEL_WIDTH-1:0] pre_3_0_w,pre_3_1_w,pre_3_2_w,pre_3_3_w;
reg [`PIXEL_WIDTH+1:0] mid_t0_r,mid_l0_r;
reg [`PIXEL_WIDTH+2:0] mid_t2_r,mid_t3_r,mid_t4_r,mid_t5_r;
reg [`PIXEL_WIDTH+2:0] mid_l2_r,mid_l3_r,mid_l4_r,mid_l5_r;
//*********************************************************************************************************
//stage0
//********************************************************************************
//lookup table to get pred_angle
always @( * ) begin
case (mode_i)
2 ,34:pred_angle='d32; 11,25:pred_angle=-'d2;
3 ,33:pred_angle='d26; 12,24:pred_angle=-'d5;
4 ,32:pred_angle='d21; 13,23:pred_angle=-'d9;
5 ,31:pred_angle='d17; 14,22:pred_angle=-'d13;
6 ,30:pred_angle='d13; 15,21:pred_angle=-'d17;
7 ,29:pred_angle='d9; 16,20:pred_angle=-'d21;
8 ,28:pred_angle='d5; 17,19:pred_angle=-'d26;
9 ,27:pred_angle='d2; 18: pred_angle=-'d32;
10,26:pred_angle='d0;
default:pred_angle='d0;
endcase
end
//********************************************************************************
//get the location information of current 4x4 block
always @( * ) begin//x
case(size_i)
2'b00:begin//4x4
x0='d0; x1='d1; x2='d2; x3='d3;
end
2'b01:begin//8x8
if(!i4x4_x_i[0]) begin
x0='d0; x1='d1; x2='d2; x3='d3;
end
else begin
x0='d4; x1='d5; x2='d6; x3='d7;
end
end
2'b10:begin//16x16
case(i4x4_x_i[1:0])
2'b00:begin
x0='d0; x1='d1; x2='d2; x3='d3;
end
2'b01:begin
x0='d4; x1='d5; x2='d6; x3='d7;
end
2'b10:begin
x0='d8; x1='d9; x2='d10; x3='d11;
end
2'b11:begin
x0='d12; x1='d13; x2='d14; x3='d15;
end
endcase
end
2'b11:begin//32x32
case(i4x4_x_i[2:0])
3'b000:begin
x0='d0; x1='d1; x2='d2; x3='d3;
end
3'b001:begin
x0='d4; x1='d5; x2='d6; x3='d7;
end
3'b010:begin
x0='d8; x1='d9; x2='d10; x3='d11;
end
3'b011:begin
x0='d12; x1='d13; x2='d14; x3='d15;
end
3'b100:begin
x0='d16; x1='d17; x2='d18; x3='d19;
end
3'b101:begin
x0='d20; x1='d21; x2='d22; x3='d23;
end
3'b110:begin
x0='d24; x1='d25; x2='d26; x3='d27;
end
3'b111:begin
x0='d28; x1='d29; x2='d30; x3='d31;
end
endcase
end
endcase
end
always @( * ) begin//y
case(size_i)
2'b00:begin//4x4
y0='d0; y1='d1; y2='d2; y3='d3;
end
2'b01:begin//8x8
if(!i4x4_y_i[0]) begin
y0='d0; y1='d1; y2='d2; y3='d3;
end
else begin
y0='d4; y1='d5; y2='d6; y3='d7;
end
end
2'b10:begin//16x16
case(i4x4_y_i[1:0])
2'b00:begin
y0='d0; y1='d1; y2='d2; y3='d3;
end
2'b01:begin
y0='d4; y1='d5; y2='d6; y3='d7;
end
2'b10:begin
y0='d8; y1='d9; y2='d10; y3='d11;
end
2'b11:begin
y0='d12; y1='d13; y2='d14; y3='d15;
end
endcase
end
2'b11:begin//32x32
case(i4x4_y_i[2:0])
3'b000:begin
y0='d0; y1='d1; y2='d2; y3='d3;
end
3'b001:begin
y0='d4; y1='d5; y2='d6; y3='d7;
end
3'b010:begin
y0='d8; y1='d9; y2='d10; y3='d11;
end
3'b011:begin
y0='d12; y1='d13; y2='d14; y3='d15;
end
3'b100:begin
y0='d16; y1='d17; y2='d18; y3='d19;
end
3'b101:begin
y0='d20; y1='d21; y2='d22; y3='d23;
end
3'b110:begin
y0='d24; y1='d25; y2='d26; y3='d27;
end
3'b111:begin
y0='d28; y1='d29; y2='d30; y3='d31;
end
endcase
end
endcase
end
always @(posedge clk or negedge rst_n) begin//help to choose the reference pixel
if(!rst_n) begin
delta_idx_r <= 'd0;
end
else begin
if(mode_i>=18)
delta_idx_r <= {1'b0,x0};
else
delta_idx_r <= {1'b0,y0};
end
end
//*********************************************************************************
//calculate idx and ifact for intra prediction
assign x0_sign_w={1'b0,x0};
assign x1_sign_w={1'b0,x1};
assign x2_sign_w={1'b0,x2};
assign x3_sign_w={1'b0,x3};
assign y0_sign_w={1'b0,y0};
assign y1_sign_w={1'b0,y1};
assign y2_sign_w={1'b0,y2};
assign y3_sign_w={1'b0,y3};
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
fact0<='d0; idx0<='d0;
fact1<='d0; idx1<='d0;
fact2<='d0; idx2<='d0;
fact3<='d0; idx3<='d0;
end
else begin
if (mode_i >= 18) begin
fact0<=((y0+1)*pred_angle);
fact1<=((y1+1)*pred_angle);
fact2<=((y2+1)*pred_angle);
fact3<=((y3+1)*pred_angle);
idx0<=((y0_sign_w+1)*pred_angle)>>>5;
idx1<=((y1_sign_w+1)*pred_angle)>>>5;
idx2<=((y2_sign_w+1)*pred_angle)>>>5;
idx3<=((y3_sign_w+1)*pred_angle)>>>5;
end
else begin
fact0<=((x0+1)*pred_angle);
fact1<=((x1+1)*pred_angle);
fact2<=((x2+1)*pred_angle);
fact3<=((x3+1)*pred_angle);
idx0<=((x0_sign_w+1)*pred_angle)>>>5;
idx1<=((x1_sign_w+1)*pred_angle)>>>5;
idx2<=((x2_sign_w+1)*pred_angle)>>>5;
idx3<=((x3_sign_w+1)*pred_angle)>>>5;
end
end
end
//**********************************************************************************
//get the real reference pixel
always @( * ) begin
ref_l00_w = 'd0; ref_l04_w = 'd0; ref_l08_w = 'd0; ref_l12_w = 'd0; ref_l16_w = 'd0; ref_l20_w = 'd0; ref_l24_w = 'd0; ref_l28_w = 'd0;
ref_l01_w = 'd0; ref_l05_w = 'd0; ref_l09_w = 'd0; ref_l13_w = 'd0; ref_l17_w = 'd0; ref_l21_w = 'd0; ref_l25_w = 'd0; ref_l29_w = 'd0;
ref_l02_w = 'd0; ref_l06_w = 'd0; ref_l10_w = 'd0; ref_l14_w = 'd0; ref_l18_w = 'd0; ref_l22_w = 'd0; ref_l26_w = 'd0; ref_l30_w = 'd0;
ref_l03_w = 'd0; ref_l07_w = 'd0; ref_l11_w = 'd0; ref_l15_w = 'd0; ref_l19_w = 'd0; ref_l23_w = 'd0; ref_l27_w = 'd0; ref_l31_w = 'd0;
ref_l32_w = 'd0; ref_l36_w = 'd0; ref_l40_w = 'd0; ref_l44_w = 'd0; ref_l48_w = 'd0; ref_l52_w = 'd0; ref_l56_w = 'd0; ref_l60_w = 'd0;
ref_l33_w = 'd0; ref_l37_w = 'd0; ref_l41_w = 'd0; ref_l45_w = 'd0; ref_l49_w = 'd0; ref_l53_w = 'd0; ref_l57_w = 'd0; ref_l61_w = 'd0;
ref_l34_w = 'd0; ref_l38_w = 'd0; ref_l42_w = 'd0; ref_l46_w = 'd0; ref_l50_w = 'd0; ref_l54_w = 'd0; ref_l58_w = 'd0; ref_l62_w = 'd0;
ref_l35_w = 'd0; ref_l39_w = 'd0; ref_l43_w = 'd0; ref_l47_w = 'd0; ref_l51_w = 'd0; ref_l55_w = 'd0; ref_l59_w = 'd0; ref_l63_w = 'd0;
ref_t00_w = 'd0; ref_t04_w = 'd0; ref_t08_w = 'd0; ref_t12_w = 'd0; ref_t16_w = 'd0; ref_t20_w = 'd0; ref_t24_w = 'd0; ref_t28_w = 'd0;
ref_t01_w = 'd0; ref_t05_w = 'd0; ref_t09_w = 'd0; ref_t13_w = 'd0; ref_t17_w = 'd0; ref_t21_w = 'd0; ref_t25_w = 'd0; ref_t29_w = 'd0;
ref_t02_w = 'd0; ref_t06_w = 'd0; ref_t10_w = 'd0; ref_t14_w = 'd0; ref_t18_w = 'd0; ref_t22_w = 'd0; ref_t26_w = 'd0; ref_t30_w = 'd0;
ref_t03_w = 'd0; ref_t07_w = 'd0; ref_t11_w = 'd0; ref_t15_w = 'd0; ref_t19_w = 'd0; ref_t23_w = 'd0; ref_t27_w = 'd0; ref_t31_w = 'd0;
ref_t32_w = 'd0; ref_t36_w = 'd0; ref_t40_w = 'd0; ref_t44_w = 'd0; ref_t48_w = 'd0; ref_t52_w = 'd0; ref_t56_w = 'd0; ref_t60_w = 'd0;
ref_t33_w = 'd0; ref_t37_w = 'd0; ref_t41_w = 'd0; ref_t45_w = 'd0; ref_t49_w = 'd0; ref_t53_w = 'd0; ref_t57_w = 'd0; ref_t61_w = 'd0;
ref_t34_w = 'd0; ref_t38_w = 'd0; ref_t42_w = 'd0; ref_t46_w = 'd0; ref_t50_w = 'd0; ref_t54_w = 'd0; ref_t58_w = 'd0; ref_t62_w = 'd0;
ref_t35_w = 'd0; ref_t39_w = 'd0; ref_t43_w = 'd0; ref_t47_w = 'd0; ref_t51_w = 'd0; ref_t55_w = 'd0; ref_t59_w = 'd0; ref_t63_w = 'd0;
case(size_i)
2'b00:begin
ref_l00_w = ref_l00_i; ref_l04_w = ref_d00_i; ref_t00_w = ref_t00_i; ref_t04_w = ref_r00_i;
ref_l01_w = ref_l01_i; ref_l05_w = ref_d01_i; ref_t01_w = ref_t01_i; ref_t05_w = ref_r01_i;
ref_l02_w = ref_l02_i; ref_l06_w = ref_d02_i; ref_t02_w = ref_t02_i; ref_t06_w = ref_r02_i;
ref_l03_w = ref_l03_i; ref_l07_w = ref_d03_i; ref_t03_w = ref_t03_i; ref_t07_w = ref_r03_i;
end
2'b01:begin
ref_l00_w = ref_l00_i; ref_l04_w = ref_l04_i; ref_l08_w = ref_d00_i; ref_l12_w = ref_d04_i;
ref_l01_w = ref_l01_i; ref_l05_w = ref_l05_i; ref_l09_w = ref_d01_i; ref_l13_w = ref_d05_i;
ref_l02_w = ref_l02_i; ref_l06_w = ref_l06_i; ref_l10_w = ref_d02_i; ref_l14_w = ref_d06_i;
ref_l03_w = ref_l03_i; ref_l07_w = ref_l07_i; ref_l11_w = ref_d03_i; ref_l15_w = ref_d07_i;
ref_t00_w = ref_t00_i; ref_t04_w = ref_t04_i; ref_t08_w = ref_r00_i; ref_t12_w = ref_r04_i;
ref_t01_w = ref_t01_i; ref_t05_w = ref_t05_i; ref_t09_w = ref_r01_i; ref_t13_w = ref_r05_i;
ref_t02_w = ref_t02_i; ref_t06_w = ref_t06_i; ref_t10_w = ref_r02_i; ref_t14_w = ref_r06_i;
ref_t03_w = ref_t03_i; ref_t07_w = ref_t07_i; ref_t11_w = ref_r03_i; ref_t15_w = ref_r07_i;
end
2'b10:begin
ref_l00_w = ref_l00_i; ref_l04_w = ref_l04_i; ref_l08_w = ref_l08_i; ref_l12_w = ref_l12_i;
ref_l01_w = ref_l01_i; ref_l05_w = ref_l05_i; ref_l09_w = ref_l09_i; ref_l13_w = ref_l13_i;
ref_l02_w = ref_l02_i; ref_l06_w = ref_l06_i; ref_l10_w = ref_l10_i; ref_l14_w = ref_l14_i;
ref_l03_w = ref_l03_i; ref_l07_w = ref_l07_i; ref_l11_w = ref_l11_i; ref_l15_w = ref_l15_i;
ref_l16_w = ref_d00_i; ref_l20_w = ref_d04_i; ref_l24_w = ref_d08_i; ref_l28_w = ref_d12_i;
ref_l17_w = ref_d01_i; ref_l21_w = ref_d05_i; ref_l25_w = ref_d09_i; ref_l29_w = ref_d13_i;
ref_l18_w = ref_d02_i; ref_l22_w = ref_d06_i; ref_l26_w = ref_d10_i; ref_l30_w = ref_d14_i;
ref_l19_w = ref_d03_i; ref_l23_w = ref_d07_i; ref_l27_w = ref_d11_i; ref_l31_w = ref_d15_i;
ref_t00_w = ref_t00_i; ref_t04_w = ref_t04_i; ref_t08_w = ref_t08_i; ref_t12_w = ref_t12_i;
ref_t01_w = ref_t01_i; ref_t05_w = ref_t05_i; ref_t09_w = ref_t09_i; ref_t13_w = ref_t13_i;
ref_t02_w = ref_t02_i; ref_t06_w = ref_t06_i; ref_t10_w = ref_t10_i; ref_t14_w = ref_t14_i;
ref_t03_w = ref_t03_i; ref_t07_w = ref_t07_i; ref_t11_w = ref_t11_i; ref_t15_w = ref_t15_i;
ref_t16_w = ref_r00_i; ref_t20_w = ref_r04_i; ref_t24_w = ref_r08_i; ref_t28_w = ref_r12_i;
ref_t17_w = ref_r01_i; ref_t21_w = ref_r05_i; ref_t25_w = ref_r09_i; ref_t29_w = ref_r13_i;
ref_t18_w = ref_r02_i; ref_t22_w = ref_r06_i; ref_t26_w = ref_r10_i; ref_t30_w = ref_r14_i;
ref_t19_w = ref_r03_i; ref_t23_w = ref_r07_i; ref_t27_w = ref_r11_i; ref_t31_w = ref_r15_i;
end
2'b11:begin
ref_l00_w = ref_l00_i; ref_l04_w = ref_l04_i; ref_l08_w = ref_l08_i; ref_l12_w = ref_l12_i;
ref_l01_w = ref_l01_i; ref_l05_w = ref_l05_i; ref_l09_w = ref_l09_i; ref_l13_w = ref_l13_i;
ref_l02_w = ref_l02_i; ref_l06_w = ref_l06_i; ref_l10_w = ref_l10_i; ref_l14_w = ref_l14_i;
ref_l03_w = ref_l03_i; ref_l07_w = ref_l07_i; ref_l11_w = ref_l11_i; ref_l15_w = ref_l15_i;
ref_l16_w = ref_l16_i; ref_l20_w = ref_l20_i; ref_l24_w = ref_l24_i; ref_l28_w = ref_l28_i;
ref_l17_w = ref_l17_i; ref_l21_w = ref_l21_i; ref_l25_w = ref_l25_i; ref_l29_w = ref_l29_i;
ref_l18_w = ref_l18_i; ref_l22_w = ref_l22_i; ref_l26_w = ref_l26_i; ref_l30_w = ref_l30_i;
ref_l19_w = ref_l19_i; ref_l23_w = ref_l23_i; ref_l27_w = ref_l27_i; ref_l31_w = ref_l31_i;
ref_l32_w = ref_d00_i; ref_l36_w = ref_d04_i; ref_l40_w = ref_d08_i; ref_l44_w = ref_d12_i;
ref_l33_w = ref_d01_i; ref_l37_w = ref_d05_i; ref_l41_w = ref_d09_i; ref_l45_w = ref_d13_i;
ref_l34_w = ref_d02_i; ref_l38_w = ref_d06_i; ref_l42_w = ref_d10_i; ref_l46_w = ref_d14_i;
ref_l35_w = ref_d03_i; ref_l39_w = ref_d07_i; ref_l43_w = ref_d11_i; ref_l47_w = ref_d15_i;
ref_l48_w = ref_d16_i; ref_l52_w = ref_d20_i; ref_l56_w = ref_d24_i; ref_l60_w = ref_d28_i;
ref_l49_w = ref_d17_i; ref_l53_w = ref_d21_i; ref_l57_w = ref_d25_i; ref_l61_w = ref_d29_i;
ref_l50_w = ref_d18_i; ref_l54_w = ref_d22_i; ref_l58_w = ref_d26_i; ref_l62_w = ref_d30_i;
ref_l51_w = ref_d19_i; ref_l55_w = ref_d23_i; ref_l59_w = ref_d27_i; ref_l63_w = ref_d31_i;
ref_t00_w = ref_t00_i; ref_t04_w = ref_t04_i; ref_t08_w = ref_t08_i; ref_t12_w = ref_t12_i;
ref_t01_w = ref_t01_i; ref_t05_w = ref_t05_i; ref_t09_w = ref_t09_i; ref_t13_w = ref_t13_i;
ref_t02_w = ref_t02_i; ref_t06_w = ref_t06_i; ref_t10_w = ref_t10_i; ref_t14_w = ref_t14_i;
ref_t03_w = ref_t03_i; ref_t07_w = ref_t07_i; ref_t11_w = ref_t11_i; ref_t15_w = ref_t15_i;
ref_t16_w = ref_t16_i; ref_t20_w = ref_t20_i; ref_t24_w = ref_t24_i; ref_t28_w = ref_t28_i;
ref_t17_w = ref_t17_i; ref_t21_w = ref_t21_i; ref_t25_w = ref_t25_i; ref_t29_w = ref_t29_i;
ref_t18_w = ref_t18_i; ref_t22_w = ref_t22_i; ref_t26_w = ref_t26_i; ref_t30_w = ref_t30_i;
ref_t19_w = ref_t19_i; ref_t23_w = ref_t23_i; ref_t27_w = ref_t27_i; ref_t31_w = ref_t31_i;
ref_t32_w = ref_r00_i; ref_t36_w = ref_r04_i; ref_t40_w = ref_r08_i; ref_t44_w = ref_r12_i;
ref_t33_w = ref_r01_i; ref_t37_w = ref_r05_i; ref_t41_w = ref_r09_i; ref_t45_w = ref_r13_i;
ref_t34_w = ref_r02_i; ref_t38_w = ref_r06_i; ref_t42_w = ref_r10_i; ref_t46_w = ref_r14_i;
ref_t35_w = ref_r03_i; ref_t39_w = ref_r07_i; ref_t43_w = ref_r11_i; ref_t47_w = ref_r15_i;
ref_t48_w = ref_r16_i; ref_t52_w = ref_r20_i; ref_t56_w = ref_r24_i; ref_t60_w = ref_r28_i;
ref_t49_w = ref_r17_i; ref_t53_w = ref_r21_i; ref_t57_w = ref_r25_i; ref_t61_w = ref_r29_i;
ref_t50_w = ref_r18_i; ref_t54_w = ref_r22_i; ref_t58_w = ref_r26_i; ref_t62_w = ref_r30_i;
ref_t51_w = ref_r19_i; ref_t55_w = ref_r23_i; ref_t59_w = ref_r27_i; ref_t63_w = ref_r31_i;
end
endcase
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
ref_00_r <= 'd0;
ref_01_r <= 'd0; ref_05_r <= 'd0; ref_09_r <= 'd0; ref_13_r <= 'd0; ref_17_r <= 'd0; ref_21_r <= 'd0; ref_25_r <= 'd0; ref_29_r <= 'd0;
ref_02_r <= 'd0; ref_06_r <= 'd0; ref_10_r <= 'd0; ref_14_r <= 'd0; ref_18_r <= 'd0; ref_22_r <= 'd0; ref_26_r <= 'd0; ref_30_r <= 'd0;
ref_03_r <= 'd0; ref_07_r <= 'd0; ref_11_r <= 'd0; ref_15_r <= 'd0; ref_19_r <= 'd0; ref_23_r <= 'd0; ref_27_r <= 'd0; ref_31_r <= 'd0;
ref_04_r <= 'd0; ref_08_r <= 'd0; ref_12_r <= 'd0; ref_16_r <= 'd0; ref_20_r <= 'd0; ref_24_r <= 'd0; ref_28_r <= 'd0; ref_32_r <= 'd0;
ref_33_r <= 'd0; ref_37_r <= 'd0; ref_41_r <= 'd0; ref_45_r <= 'd0; ref_49_r <= 'd0; ref_53_r <= 'd0; ref_57_r <= 'd0; ref_61_r <= 'd0;
ref_34_r <= 'd0; ref_38_r <= 'd0; ref_42_r <= 'd0; ref_46_r <= 'd0; ref_50_r <= 'd0; ref_54_r <= 'd0; ref_58_r <= 'd0; ref_62_r <= 'd0;
ref_35_r <= 'd0; ref_39_r <= 'd0; ref_43_r <= 'd0; ref_47_r <= 'd0; ref_51_r <= 'd0; ref_55_r <= 'd0; ref_59_r <= 'd0; ref_63_r <= 'd0;
ref_36_r <= 'd0; ref_40_r <= 'd0; ref_44_r <= 'd0; ref_48_r <= 'd0; ref_52_r <= 'd0; ref_56_r <= 'd0; ref_60_r <= 'd0; ref_64_r <= 'd0;
ref_x01_r <= 'd0; ref_x05_r <= 'd0; ref_x09_r <= 'd0; ref_x13_r <= 'd0; ref_x17_r <= 'd0; ref_x21_r <= 'd0; ref_x25_r <= 'd0; ref_x29_r <= 'd0;
ref_x02_r <= 'd0; ref_x06_r <= 'd0; ref_x10_r <= 'd0; ref_x14_r <= 'd0; ref_x18_r <= 'd0; ref_x22_r <= 'd0; ref_x26_r <= 'd0; ref_x30_r <= 'd0;
ref_x03_r <= 'd0; ref_x07_r <= 'd0; ref_x11_r <= 'd0; ref_x15_r <= 'd0; ref_x19_r <= 'd0; ref_x23_r <= 'd0; ref_x27_r <= 'd0; ref_x31_r <= 'd0;
ref_x04_r <= 'd0; ref_x08_r <= 'd0; ref_x12_r <= 'd0; ref_x16_r <= 'd0; ref_x20_r <= 'd0; ref_x24_r <= 'd0; ref_x28_r <= 'd0; ref_x32_r <= 'd0;
end
else begin
ref_00_r <= ref_tl_i;
if(mode_i >= 18) begin
ref_01_r <= ref_t00_w; ref_05_r <= ref_t04_w; ref_09_r <= ref_t08_w; ref_13_r <= ref_t12_w;
ref_02_r <= ref_t01_w; ref_06_r <= ref_t05_w; ref_10_r <= ref_t09_w; ref_14_r <= ref_t13_w;
ref_03_r <= ref_t02_w; ref_07_r <= ref_t06_w; ref_11_r <= ref_t10_w; ref_15_r <= ref_t14_w;
ref_04_r <= ref_t03_w; ref_08_r <= ref_t07_w; ref_12_r <= ref_t11_w; ref_16_r <= ref_t15_w;
ref_17_r <= ref_t16_w; ref_21_r <= ref_t20_w; ref_25_r <= ref_t24_w; ref_29_r <= ref_t28_w;
ref_18_r <= ref_t17_w; ref_22_r <= ref_t21_w; ref_26_r <= ref_t25_w; ref_30_r <= ref_t29_w;
ref_19_r <= ref_t18_w; ref_23_r <= ref_t22_w; ref_27_r <= ref_t26_w; ref_31_r <= ref_t30_w;
ref_20_r <= ref_t19_w; ref_24_r <= ref_t23_w; ref_28_r <= ref_t27_w; ref_32_r <= ref_t31_w;
ref_33_r <= ref_t32_w; ref_37_r <= ref_t36_w; ref_41_r <= ref_t40_w; ref_45_r <= ref_t44_w;
ref_34_r <= ref_t33_w; ref_38_r <= ref_t37_w; ref_42_r <= ref_t41_w; ref_46_r <= ref_t45_w;
ref_35_r <= ref_t34_w; ref_39_r <= ref_t38_w; ref_43_r <= ref_t42_w; ref_47_r <= ref_t46_w;
ref_36_r <= ref_t35_w; ref_40_r <= ref_t39_w; ref_44_r <= ref_t43_w; ref_48_r <= ref_t47_w;
ref_49_r <= ref_t48_w; ref_53_r <= ref_t52_w; ref_57_r <= ref_t56_w; ref_61_r <= ref_t60_w;
ref_50_r <= ref_t49_w; ref_54_r <= ref_t53_w; ref_58_r <= ref_t57_w; ref_62_r <= ref_t61_w;
ref_51_r <= ref_t50_w; ref_55_r <= ref_t54_w; ref_59_r <= ref_t58_w; ref_63_r <= ref_t62_w;
ref_52_r <= ref_t51_w; ref_56_r <= ref_t55_w; ref_60_r <= ref_t59_w; ref_64_r <= ref_t63_w;
case (mode_i)
'd19:begin
ref_x01_r <= ref_l00_w; ref_x05_r <= ref_l05_w; ref_x09_r <= ref_l10_w; ref_x13_r <= ref_l15_w;
ref_x02_r <= ref_l01_w; ref_x06_r <= ref_l06_w; ref_x10_r <= ref_l11_w; ref_x14_r <= ref_l16_w;
ref_x03_r <= ref_l03_w; ref_x07_r <= ref_l08_w; ref_x11_r <= ref_l13_w; ref_x15_r <= ref_l17_w;
ref_x04_r <= ref_l04_w; ref_x08_r <= ref_l09_w; ref_x12_r <= ref_l14_w; ref_x16_r <= ref_l19_w;
ref_x17_r <= ref_l20_w; ref_x21_r <= ref_l25_w; ref_x25_r <= ref_l30_w;
ref_x18_r <= ref_l21_w; ref_x22_r <= ref_l26_w; ref_x26_r <= ref_l31_w;
ref_x19_r <= ref_l22_w; ref_x23_r <= ref_l27_w;
ref_x20_r <= ref_l24_w; ref_x24_r <= ref_l29_w;
end
'd20:begin
ref_x01_r <= ref_l01_w; ref_x05_r <= ref_l07_w; ref_x09_r <= ref_l13_w; ref_x13_r <= ref_l19_w;
ref_x02_r <= ref_l02_w; ref_x06_r <= ref_l08_w; ref_x10_r <= ref_l14_w; ref_x14_r <= ref_l20_w;
ref_x03_r <= ref_l04_w; ref_x07_r <= ref_l10_w; ref_x11_r <= ref_l16_w; ref_x15_r <= ref_l22_w;
ref_x04_r <= ref_l05_w; ref_x08_r <= ref_l11_w; ref_x12_r <= ref_l17_w; ref_x16_r <= ref_l23_w;
ref_x17_r <= ref_l25_w; ref_x21_r <= ref_l31_w;
ref_x18_r <= ref_l26_w;
ref_x19_r <= ref_l28_w;
ref_x20_r <= ref_l29_w;
end
'd21:begin
ref_x01_r <= ref_l01_w; ref_x05_r <= ref_l08_w; ref_x09_r <= ref_l16_w; ref_x13_r <= ref_l23_w;
ref_x02_r <= ref_l03_w; ref_x06_r <= ref_l10_w; ref_x10_r <= ref_l18_w; ref_x14_r <= ref_l25_w;
ref_x03_r <= ref_l05_w; ref_x07_r <= ref_l12_w; ref_x11_r <= ref_l20_w; ref_x15_r <= ref_l27_w;
ref_x04_r <= ref_l07_w; ref_x08_r <= ref_l14_w; ref_x12_r <= ref_l22_w; ref_x16_r <= ref_l29_w;
ref_x17_r <= ref_l31_w;
end
'd22:begin
ref_x01_r <= ref_l01_w; ref_x05_r <= ref_l11_w; ref_x09_r <= ref_l21_w; ref_x13_r <= ref_l31_w;
ref_x02_r <= ref_l04_w; ref_x06_r <= ref_l14_w; ref_x10_r <= ref_l24_w;
ref_x03_r <= ref_l06_w; ref_x07_r <= ref_l16_w; ref_x11_r <= ref_l26_w;
ref_x04_r <= ref_l09_w; ref_x08_r <= ref_l19_w; ref_x12_r <= ref_l29_w;
end
'd23:begin
ref_x01_r <= ref_l03_w; ref_x05_r <= ref_l17_w; ref_x09_r <= ref_l31_w;
ref_x02_r <= ref_l06_w; ref_x06_r <= ref_l20_w;
ref_x03_r <= ref_l10_w; ref_x07_r <= ref_l24_w;
ref_x04_r <= ref_l13_w; ref_x08_r <= ref_l27_w;
end
'd24:begin
ref_x01_r <= ref_l05_w; ref_x05_r <= ref_l31_w;
ref_x02_r <= ref_l12_w;
ref_x03_r <= ref_l18_w;
ref_x04_r <= ref_l25_w;
end
'd25:begin
ref_x01_r <= ref_l15_w;
ref_x02_r <= ref_l31_w;
end
default begin
ref_x01_r <= ref_l00_w; ref_x05_r <= ref_l04_w; ref_x09_r <= ref_l08_w; ref_x13_r <= ref_l12_w;
ref_x02_r <= ref_l01_w; ref_x06_r <= ref_l05_w; ref_x10_r <= ref_l09_w; ref_x14_r <= ref_l13_w;
ref_x03_r <= ref_l02_w; ref_x07_r <= ref_l06_w; ref_x11_r <= ref_l10_w; ref_x15_r <= ref_l14_w;
ref_x04_r <= ref_l03_w; ref_x08_r <= ref_l07_w; ref_x12_r <= ref_l11_w; ref_x16_r <= ref_l15_w;
ref_x17_r <= ref_l16_w; ref_x21_r <= ref_l20_w; ref_x25_r <= ref_l24_w; ref_x29_r <= ref_l28_w;
ref_x18_r <= ref_l17_w; ref_x22_r <= ref_l21_w; ref_x26_r <= ref_l25_w; ref_x30_r <= ref_l29_w;
ref_x19_r <= ref_l18_w; ref_x23_r <= ref_l22_w; ref_x27_r <= ref_l26_w; ref_x31_r <= ref_l30_w;
ref_x20_r <= ref_l19_w; ref_x24_r <= ref_l23_w; ref_x28_r <= ref_l27_w; ref_x32_r <= ref_l31_w;
end
endcase
end
else begin
ref_01_r <= ref_l00_w; ref_05_r <= ref_l04_w; ref_09_r <= ref_l08_w; ref_13_r <= ref_l12_w;
ref_02_r <= ref_l01_w; ref_06_r <= ref_l05_w; ref_10_r <= ref_l09_w; ref_14_r <= ref_l13_w;
ref_03_r <= ref_l02_w; ref_07_r <= ref_l06_w; ref_11_r <= ref_l10_w; ref_15_r <= ref_l14_w;
ref_04_r <= ref_l03_w; ref_08_r <= ref_l07_w; ref_12_r <= ref_l11_w; ref_16_r <= ref_l15_w;
ref_17_r <= ref_l16_w; ref_21_r <= ref_l20_w; ref_25_r <= ref_l24_w; ref_29_r <= ref_l28_w;
ref_18_r <= ref_l17_w; ref_22_r <= ref_l21_w; ref_26_r <= ref_l25_w; ref_30_r <= ref_l29_w;
ref_19_r <= ref_l18_w; ref_23_r <= ref_l22_w; ref_27_r <= ref_l26_w; ref_31_r <= ref_l30_w;
ref_20_r <= ref_l19_w; ref_24_r <= ref_l23_w; ref_28_r <= ref_l27_w; ref_32_r <= ref_l31_w;
ref_33_r <= ref_l32_w; ref_37_r <= ref_l36_w; ref_41_r <= ref_l40_w; ref_45_r <= ref_l44_w;
ref_34_r <= ref_l33_w; ref_38_r <= ref_l37_w; ref_42_r <= ref_l41_w; ref_46_r <= ref_l45_w;
ref_35_r <= ref_l34_w; ref_39_r <= ref_l38_w; ref_43_r <= ref_l42_w; ref_47_r <= ref_l46_w;
ref_36_r <= ref_l35_w; ref_40_r <= ref_l39_w; ref_44_r <= ref_l43_w; ref_48_r <= ref_l47_w;
ref_49_r <= ref_l48_w; ref_53_r <= ref_l52_w; ref_57_r <= ref_l56_w; ref_61_r <= ref_l60_w;
ref_50_r <= ref_l49_w; ref_54_r <= ref_l53_w; ref_58_r <= ref_l57_w; ref_62_r <= ref_l61_w;
ref_51_r <= ref_l50_w; ref_55_r <= ref_l54_w; ref_59_r <= ref_l58_w; ref_63_r <= ref_l62_w;
ref_52_r <= ref_l51_w; ref_56_r <= ref_l55_w; ref_60_r <= ref_l59_w; ref_64_r <= ref_l63_w;
case (mode_i)
'd17:begin
ref_x01_r <= ref_t00_w; ref_x05_r <= ref_t05_w; ref_x09_r <= ref_t10_w; ref_x13_r <= ref_t15_w;
ref_x02_r <= ref_t01_w; ref_x06_r <= ref_t06_w; ref_x10_r <= ref_t11_w; ref_x14_r <= ref_t16_w;
ref_x03_r <= ref_t03_w; ref_x07_r <= ref_t08_w; ref_x11_r <= ref_t13_w; ref_x15_r <= ref_t17_w;
ref_x04_r <= ref_t04_w; ref_x08_r <= ref_t09_w; ref_x12_r <= ref_t14_w; ref_x16_r <= ref_t19_w;
ref_x17_r <= ref_t20_w; ref_x21_r <= ref_t25_w; ref_x25_r <= ref_t30_w;
ref_x18_r <= ref_t21_w; ref_x22_r <= ref_t26_w; ref_x26_r <= ref_t31_w;
ref_x19_r <= ref_t22_w; ref_x23_r <= ref_t27_w;
ref_x20_r <= ref_t24_w; ref_x24_r <= ref_t29_w;
end
'd16:begin
ref_x01_r <= ref_t01_w; ref_x05_r <= ref_t07_w; ref_x09_r <= ref_t13_w; ref_x13_r <= ref_t19_w;
ref_x02_r <= ref_t02_w; ref_x06_r <= ref_t08_w; ref_x10_r <= ref_t14_w; ref_x14_r <= ref_t20_w;
ref_x03_r <= ref_t04_w; ref_x07_r <= ref_t10_w; ref_x11_r <= ref_t16_w; ref_x15_r <= ref_t22_w;
ref_x04_r <= ref_t05_w; ref_x08_r <= ref_t11_w; ref_x12_r <= ref_t17_w; ref_x16_r <= ref_t23_w;
ref_x17_r <= ref_t25_w; ref_x21_r <= ref_t31_w;
ref_x18_r <= ref_t26_w;
ref_x19_r <= ref_t28_w;
ref_x20_r <= ref_t29_w;
end
'd15:begin
ref_x01_r <= ref_t01_w; ref_x05_r <= ref_t08_w; ref_x09_r <= ref_t16_w; ref_x13_r <= ref_t23_w;
ref_x02_r <= ref_t03_w; ref_x06_r <= ref_t10_w; ref_x10_r <= ref_t18_w; ref_x14_r <= ref_t25_w;
ref_x03_r <= ref_t05_w; ref_x07_r <= ref_t12_w; ref_x11_r <= ref_t20_w; ref_x15_r <= ref_t27_w;
ref_x04_r <= ref_t07_w; ref_x08_r <= ref_t14_w; ref_x12_r <= ref_t22_w; ref_x16_r <= ref_t29_w;
ref_x17_r <= ref_t31_w;
end
'd14:begin
ref_x01_r <= ref_t01_w; ref_x05_r <= ref_t11_w; ref_x09_r <= ref_t21_w; ref_x13_r <= ref_t31_w;
ref_x02_r <= ref_t04_w; ref_x06_r <= ref_t14_w; ref_x10_r <= ref_t24_w;
ref_x03_r <= ref_t06_w; ref_x07_r <= ref_t16_w; ref_x11_r <= ref_t26_w;
ref_x04_r <= ref_t09_w; ref_x08_r <= ref_t19_w; ref_x12_r <= ref_t29_w;
end
'd13:begin
ref_x01_r <= ref_t03_w; ref_x05_r <= ref_t17_w; ref_x09_r <= ref_t31_w;
ref_x02_r <= ref_t06_w; ref_x06_r <= ref_t20_w;
ref_x03_r <= ref_t10_w; ref_x07_r <= ref_t24_w;
ref_x04_r <= ref_t13_w; ref_x08_r <= ref_t27_w;
end
'd12:begin
ref_x01_r <= ref_t05_w; ref_x05_r <= ref_t31_w;
ref_x02_r <= ref_t12_w;
ref_x03_r <= ref_t18_w;
ref_x04_r <= ref_t25_w;
end
'd11:begin
ref_x01_r <= ref_t15_w;
ref_x02_r <= ref_t31_w;
end
default begin
ref_x01_r <= ref_t00_w; ref_x05_r <= ref_t04_w; ref_x09_r <= ref_t08_w; ref_x13_r <= ref_t12_w;
ref_x02_r <= ref_t01_w; ref_x06_r <= ref_t05_w; ref_x10_r <= ref_t09_w; ref_x14_r <= ref_t13_w;
ref_x03_r <= ref_t02_w; ref_x07_r <= ref_t06_w; ref_x11_r <= ref_t10_w; ref_x15_r <= ref_t14_w;
ref_x04_r <= ref_t03_w; ref_x08_r <= ref_t07_w; ref_x12_r <= ref_t11_w; ref_x16_r <= ref_t15_w;
ref_x17_r <= ref_t16_w; ref_x21_r <= ref_t20_w; ref_x25_r <= ref_t24_w; ref_x29_r <= ref_t28_w;
ref_x18_r <= ref_t17_w; ref_x22_r <= ref_t21_w; ref_x26_r <= ref_t25_w; ref_x30_r <= ref_t29_w;
ref_x19_r <= ref_t18_w; ref_x23_r <= ref_t22_w; ref_x27_r <= ref_t26_w; ref_x31_r <= ref_t30_w;
ref_x20_r <= ref_t19_w; ref_x24_r <= ref_t23_w; ref_x28_r <= ref_t27_w; ref_x32_r <= ref_t31_w;
end
endcase
end
end
end
//**********************************************************************************
//calculate the middle value for DC
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
mid_t0_r <= 'd0; mid_l0_r <= 'd0;
mid_t2_r <= 'd0; mid_l2_r <= 'd0;
mid_t3_r <= 'd0; mid_l3_r <= 'd0;
mid_t4_r <= 'd0; mid_l4_r <= 'd0;
mid_t5_r <= 'd0; mid_l5_r <= 'd0;
end
else begin
mid_t0_r <= ref_t00_i+ref_t01_i+ref_t02_i+ref_t03_i;
mid_t2_r <= ref_t00_i+ref_t01_i+ref_t02_i+ref_t03_i+ref_t04_i+ref_t05_i+ref_t06_i+ref_t07_i;
mid_t3_r <= ref_t08_i+ref_t09_i+ref_t10_i+ref_t11_i+ref_t12_i+ref_t13_i+ref_t14_i+ref_t15_i;
mid_t4_r <= ref_t16_i+ref_t17_i+ref_t18_i+ref_t19_i+ref_t20_i+ref_t21_i+ref_t22_i+ref_t23_i;
mid_t5_r <= ref_t24_i+ref_t25_i+ref_t26_i+ref_t27_i+ref_t28_i+ref_t29_i+ref_t30_i+ref_t31_i;
mid_l0_r <= ref_l00_i+ref_l01_i+ref_l02_i+ref_l03_i;
mid_l2_r <= ref_l00_i+ref_l01_i+ref_l02_i+ref_l03_i+ref_l04_i+ref_l05_i+ref_l06_i+ref_l07_i;
mid_l3_r <= ref_l08_i+ref_l09_i+ref_l10_i+ref_l11_i+ref_l12_i+ref_l13_i+ref_l14_i+ref_l15_i;
mid_l4_r <= ref_l16_i+ref_l17_i+ref_l18_i+ref_l19_i+ref_l20_i+ref_l21_i+ref_l22_i+ref_l23_i;
mid_l5_r <= ref_l24_i+ref_l25_i+ref_l26_i+ref_l27_i+ref_l28_i+ref_l29_i+ref_l30_i+ref_l31_i;
end
end
//stage1
//**********************************************************************************
//buffer ifact for Angular mode
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
ifact0 <= 'd0;
ifact1 <= 'd0;
ifact2 <= 'd0;
ifact3 <= 'd0;
end
else begin
ifact0 <= fact0[4:0];
ifact1 <= fact1[4:0];
ifact2 <= fact2[4:0];
ifact3 <= fact3[4:0];
end
end
//**********************************************************************************
//select the reference pixel for Angular mode
wire signed [6:0] ref_idx0_w,ref_idx1_w,ref_idx2_w,ref_idx3_w;
assign ref_idx0_w=delta_idx_r+idx0;
assign ref_idx1_w=delta_idx_r+idx1;
assign ref_idx2_w=delta_idx_r+idx2;
assign ref_idx3_w=delta_idx_r+idx3;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
ref_0_0<='d0; ref_0_1<='d0; ref_0_2<='d0; ref_0_3<='d0; ref_0_4<='d0;
end
else begin
case (ref_idx0_w)
-32 :begin ref_0_0<=ref_x31_r; ref_0_1<=ref_x30_r; ref_0_2<=ref_x29_r; ref_0_3<=ref_x28_r; ref_0_4<=ref_x27_r; end
-31 :begin ref_0_0<=ref_x30_r; ref_0_1<=ref_x29_r; ref_0_2<=ref_x28_r; ref_0_3<=ref_x27_r; ref_0_4<=ref_x26_r; end
-30 :begin ref_0_0<=ref_x29_r; ref_0_1<=ref_x28_r; ref_0_2<=ref_x27_r; ref_0_3<=ref_x26_r; ref_0_4<=ref_x25_r; end
-29 :begin ref_0_0<=ref_x28_r; ref_0_1<=ref_x27_r; ref_0_2<=ref_x26_r; ref_0_3<=ref_x25_r; ref_0_4<=ref_x24_r; end
-28 :begin ref_0_0<=ref_x27_r; ref_0_1<=ref_x26_r; ref_0_2<=ref_x25_r; ref_0_3<=ref_x24_r; ref_0_4<=ref_x23_r; end
-27 :begin ref_0_0<=ref_x26_r; ref_0_1<=ref_x25_r; ref_0_2<=ref_x24_r; ref_0_3<=ref_x23_r; ref_0_4<=ref_x22_r; end
-26 :begin ref_0_0<=ref_x25_r; ref_0_1<=ref_x24_r; ref_0_2<=ref_x23_r; ref_0_3<=ref_x22_r; ref_0_4<=ref_x21_r; end
-25 :begin ref_0_0<=ref_x24_r; ref_0_1<=ref_x23_r; ref_0_2<=ref_x22_r; ref_0_3<=ref_x21_r; ref_0_4<=ref_x20_r; end
-24 :begin ref_0_0<=ref_x23_r; ref_0_1<=ref_x22_r; ref_0_2<=ref_x21_r; ref_0_3<=ref_x20_r; ref_0_4<=ref_x19_r; end
-23 :begin ref_0_0<=ref_x22_r; ref_0_1<=ref_x21_r; ref_0_2<=ref_x20_r; ref_0_3<=ref_x19_r; ref_0_4<=ref_x18_r; end
-22 :begin ref_0_0<=ref_x21_r; ref_0_1<=ref_x20_r; ref_0_2<=ref_x19_r; ref_0_3<=ref_x18_r; ref_0_4<=ref_x17_r; end
-21 :begin ref_0_0<=ref_x20_r; ref_0_1<=ref_x19_r; ref_0_2<=ref_x18_r; ref_0_3<=ref_x17_r; ref_0_4<=ref_x16_r; end
-20 :begin ref_0_0<=ref_x19_r; ref_0_1<=ref_x18_r; ref_0_2<=ref_x17_r; ref_0_3<=ref_x16_r; ref_0_4<=ref_x15_r; end
-19 :begin ref_0_0<=ref_x18_r; ref_0_1<=ref_x17_r; ref_0_2<=ref_x16_r; ref_0_3<=ref_x15_r; ref_0_4<=ref_x14_r; end
-18 :begin ref_0_0<=ref_x17_r; ref_0_1<=ref_x16_r; ref_0_2<=ref_x15_r; ref_0_3<=ref_x14_r; ref_0_4<=ref_x13_r; end
-17 :begin ref_0_0<=ref_x16_r; ref_0_1<=ref_x15_r; ref_0_2<=ref_x14_r; ref_0_3<=ref_x13_r; ref_0_4<=ref_x12_r; end
-16 :begin ref_0_0<=ref_x15_r; ref_0_1<=ref_x14_r; ref_0_2<=ref_x13_r; ref_0_3<=ref_x12_r; ref_0_4<=ref_x11_r; end
-15 :begin ref_0_0<=ref_x14_r; ref_0_1<=ref_x13_r; ref_0_2<=ref_x12_r; ref_0_3<=ref_x11_r; ref_0_4<=ref_x10_r; end
-14 :begin ref_0_0<=ref_x13_r; ref_0_1<=ref_x12_r; ref_0_2<=ref_x11_r; ref_0_3<=ref_x10_r; ref_0_4<=ref_x09_r; end
-13 :begin ref_0_0<=ref_x12_r; ref_0_1<=ref_x11_r; ref_0_2<=ref_x10_r; ref_0_3<=ref_x09_r; ref_0_4<=ref_x08_r; end
-12 :begin ref_0_0<=ref_x11_r; ref_0_1<=ref_x10_r; ref_0_2<=ref_x09_r; ref_0_3<=ref_x08_r; ref_0_4<=ref_x07_r; end
-11 :begin ref_0_0<=ref_x10_r; ref_0_1<=ref_x09_r; ref_0_2<=ref_x08_r; ref_0_3<=ref_x07_r; ref_0_4<=ref_x06_r; end
-10 :begin ref_0_0<=ref_x09_r; ref_0_1<=ref_x08_r; ref_0_2<=ref_x07_r; ref_0_3<=ref_x06_r; ref_0_4<=ref_x05_r; end
- 9 :begin ref_0_0<=ref_x08_r; ref_0_1<=ref_x07_r; ref_0_2<=ref_x06_r; ref_0_3<=ref_x05_r; ref_0_4<=ref_x04_r; end
- 8 :begin ref_0_0<=ref_x07_r; ref_0_1<=ref_x06_r; ref_0_2<=ref_x05_r; ref_0_3<=ref_x04_r; ref_0_4<=ref_x03_r; end
- 7 :begin ref_0_0<=ref_x06_r; ref_0_1<=ref_x05_r; ref_0_2<=ref_x04_r; ref_0_3<=ref_x03_r; ref_0_4<=ref_x02_r; end
- 6 :begin ref_0_0<=ref_x05_r; ref_0_1<=ref_x04_r; ref_0_2<=ref_x03_r; ref_0_3<=ref_x02_r; ref_0_4<=ref_x01_r; end
- 5 :begin ref_0_0<=ref_x04_r; ref_0_1<=ref_x03_r; ref_0_2<=ref_x02_r; ref_0_3<=ref_x01_r; ref_0_4<=ref_00_r; end
- 4 :begin ref_0_0<=ref_x03_r; ref_0_1<=ref_x02_r; ref_0_2<=ref_x01_r; ref_0_3<=ref_00_r; ref_0_4<=ref_01_r; end
- 3 :begin ref_0_0<=ref_x02_r; ref_0_1<=ref_x01_r; ref_0_2<=ref_00_r; ref_0_3<=ref_01_r; ref_0_4<=ref_02_r; end
- 2 :begin ref_0_0<=ref_x01_r; ref_0_1<=ref_00_r; ref_0_2<=ref_01_r; ref_0_3<=ref_02_r; ref_0_4<=ref_03_r; end
- 1 :begin ref_0_0<=ref_00_r; ref_0_1<=ref_01_r; ref_0_2<=ref_02_r; ref_0_3<=ref_03_r; ref_0_4<=ref_04_r; end
0 :begin ref_0_0<=ref_01_r; ref_0_1<=ref_02_r; ref_0_2<=ref_03_r; ref_0_3<=ref_04_r; ref_0_4<=ref_05_r; end
1 :begin ref_0_0<=ref_02_r; ref_0_1<=ref_03_r; ref_0_2<=ref_04_r; ref_0_3<=ref_05_r; ref_0_4<=ref_06_r; end
2 :begin ref_0_0<=ref_03_r; ref_0_1<=ref_04_r; ref_0_2<=ref_05_r; ref_0_3<=ref_06_r; ref_0_4<=ref_07_r; end
3 :begin ref_0_0<=ref_04_r; ref_0_1<=ref_05_r; ref_0_2<=ref_06_r; ref_0_3<=ref_07_r; ref_0_4<=ref_08_r; end
4 :begin ref_0_0<=ref_05_r; ref_0_1<=ref_06_r; ref_0_2<=ref_07_r; ref_0_3<=ref_08_r; ref_0_4<=ref_09_r; end
5 :begin ref_0_0<=ref_06_r; ref_0_1<=ref_07_r; ref_0_2<=ref_08_r; ref_0_3<=ref_09_r; ref_0_4<=ref_10_r; end
6 :begin ref_0_0<=ref_07_r; ref_0_1<=ref_08_r; ref_0_2<=ref_09_r; ref_0_3<=ref_10_r; ref_0_4<=ref_11_r; end
7 :begin ref_0_0<=ref_08_r; ref_0_1<=ref_09_r; ref_0_2<=ref_10_r; ref_0_3<=ref_11_r; ref_0_4<=ref_12_r; end
8 :begin ref_0_0<=ref_09_r; ref_0_1<=ref_10_r; ref_0_2<=ref_11_r; ref_0_3<=ref_12_r; ref_0_4<=ref_13_r; end
9 :begin ref_0_0<=ref_10_r; ref_0_1<=ref_11_r; ref_0_2<=ref_12_r; ref_0_3<=ref_13_r; ref_0_4<=ref_14_r; end
10 :begin ref_0_0<=ref_11_r; ref_0_1<=ref_12_r; ref_0_2<=ref_13_r; ref_0_3<=ref_14_r; ref_0_4<=ref_15_r; end
11 :begin ref_0_0<=ref_12_r; ref_0_1<=ref_13_r; ref_0_2<=ref_14_r; ref_0_3<=ref_15_r; ref_0_4<=ref_16_r; end
12 :begin ref_0_0<=ref_13_r; ref_0_1<=ref_14_r; ref_0_2<=ref_15_r; ref_0_3<=ref_16_r; ref_0_4<=ref_17_r; end
13 :begin ref_0_0<=ref_14_r; ref_0_1<=ref_15_r; ref_0_2<=ref_16_r; ref_0_3<=ref_17_r; ref_0_4<=ref_18_r; end
14 :begin ref_0_0<=ref_15_r; ref_0_1<=ref_16_r; ref_0_2<=ref_17_r; ref_0_3<=ref_18_r; ref_0_4<=ref_19_r; end
15 :begin ref_0_0<=ref_16_r; ref_0_1<=ref_17_r; ref_0_2<=ref_18_r; ref_0_3<=ref_19_r; ref_0_4<=ref_20_r; end
16 :begin ref_0_0<=ref_17_r; ref_0_1<=ref_18_r; ref_0_2<=ref_19_r; ref_0_3<=ref_20_r; ref_0_4<=ref_21_r; end
17 :begin ref_0_0<=ref_18_r; ref_0_1<=ref_19_r; ref_0_2<=ref_20_r; ref_0_3<=ref_21_r; ref_0_4<=ref_22_r; end
18 :begin ref_0_0<=ref_19_r; ref_0_1<=ref_20_r; ref_0_2<=ref_21_r; ref_0_3<=ref_22_r; ref_0_4<=ref_23_r; end
19 :begin ref_0_0<=ref_20_r; ref_0_1<=ref_21_r; ref_0_2<=ref_22_r; ref_0_3<=ref_23_r; ref_0_4<=ref_24_r; end
20 :begin ref_0_0<=ref_21_r; ref_0_1<=ref_22_r; ref_0_2<=ref_23_r; ref_0_3<=ref_24_r; ref_0_4<=ref_25_r; end
21 :begin ref_0_0<=ref_22_r; ref_0_1<=ref_23_r; ref_0_2<=ref_24_r; ref_0_3<=ref_25_r; ref_0_4<=ref_26_r; end
22 :begin ref_0_0<=ref_23_r; ref_0_1<=ref_24_r; ref_0_2<=ref_25_r; ref_0_3<=ref_26_r; ref_0_4<=ref_27_r; end
23 :begin ref_0_0<=ref_24_r; ref_0_1<=ref_25_r; ref_0_2<=ref_26_r; ref_0_3<=ref_27_r; ref_0_4<=ref_28_r; end
24 :begin ref_0_0<=ref_25_r; ref_0_1<=ref_26_r; ref_0_2<=ref_27_r; ref_0_3<=ref_28_r; ref_0_4<=ref_29_r; end
25 :begin ref_0_0<=ref_26_r; ref_0_1<=ref_27_r; ref_0_2<=ref_28_r; ref_0_3<=ref_29_r; ref_0_4<=ref_30_r; end
26 :begin ref_0_0<=ref_27_r; ref_0_1<=ref_28_r; ref_0_2<=ref_29_r; ref_0_3<=ref_30_r; ref_0_4<=ref_31_r; end
27 :begin ref_0_0<=ref_28_r; ref_0_1<=ref_29_r; ref_0_2<=ref_30_r; ref_0_3<=ref_31_r; ref_0_4<=ref_32_r; end
28 :begin ref_0_0<=ref_29_r; ref_0_1<=ref_30_r; ref_0_2<=ref_31_r; ref_0_3<=ref_32_r; ref_0_4<=ref_33_r; end
29 :begin ref_0_0<=ref_30_r; ref_0_1<=ref_31_r; ref_0_2<=ref_32_r; ref_0_3<=ref_33_r; ref_0_4<=ref_34_r; end
30 :begin ref_0_0<=ref_31_r; ref_0_1<=ref_32_r; ref_0_2<=ref_33_r; ref_0_3<=ref_34_r; ref_0_4<=ref_35_r; end
31 :begin ref_0_0<=ref_32_r; ref_0_1<=ref_33_r; ref_0_2<=ref_34_r; ref_0_3<=ref_35_r; ref_0_4<=ref_36_r; end
32 :begin ref_0_0<=ref_33_r; ref_0_1<=ref_34_r; ref_0_2<=ref_35_r; ref_0_3<=ref_36_r; ref_0_4<=ref_37_r; end
33 :begin ref_0_0<=ref_34_r; ref_0_1<=ref_35_r; ref_0_2<=ref_36_r; ref_0_3<=ref_37_r; ref_0_4<=ref_38_r; end
34 :begin ref_0_0<=ref_35_r; ref_0_1<=ref_36_r; ref_0_2<=ref_37_r; ref_0_3<=ref_38_r; ref_0_4<=ref_39_r; end
35 :begin ref_0_0<=ref_36_r; ref_0_1<=ref_37_r; ref_0_2<=ref_38_r; ref_0_3<=ref_39_r; ref_0_4<=ref_40_r; end
36 :begin ref_0_0<=ref_37_r; ref_0_1<=ref_38_r; ref_0_2<=ref_39_r; ref_0_3<=ref_40_r; ref_0_4<=ref_41_r; end
37 :begin ref_0_0<=ref_38_r; ref_0_1<=ref_39_r; ref_0_2<=ref_40_r; ref_0_3<=ref_41_r; ref_0_4<=ref_42_r; end
38 :begin ref_0_0<=ref_39_r; ref_0_1<=ref_40_r; ref_0_2<=ref_41_r; ref_0_3<=ref_42_r; ref_0_4<=ref_43_r; end
39 :begin ref_0_0<=ref_40_r; ref_0_1<=ref_41_r; ref_0_2<=ref_42_r; ref_0_3<=ref_43_r; ref_0_4<=ref_44_r; end
40 :begin ref_0_0<=ref_41_r; ref_0_1<=ref_42_r; ref_0_2<=ref_43_r; ref_0_3<=ref_44_r; ref_0_4<=ref_45_r; end
41 :begin ref_0_0<=ref_42_r; ref_0_1<=ref_43_r; ref_0_2<=ref_44_r; ref_0_3<=ref_45_r; ref_0_4<=ref_46_r; end
42 :begin ref_0_0<=ref_43_r; ref_0_1<=ref_44_r; ref_0_2<=ref_45_r; ref_0_3<=ref_46_r; ref_0_4<=ref_47_r; end
43 :begin ref_0_0<=ref_44_r; ref_0_1<=ref_45_r; ref_0_2<=ref_46_r; ref_0_3<=ref_47_r; ref_0_4<=ref_48_r; end
44 :begin ref_0_0<=ref_45_r; ref_0_1<=ref_46_r; ref_0_2<=ref_47_r; ref_0_3<=ref_48_r; ref_0_4<=ref_49_r; end
45 :begin ref_0_0<=ref_46_r; ref_0_1<=ref_47_r; ref_0_2<=ref_48_r; ref_0_3<=ref_49_r; ref_0_4<=ref_50_r; end
46 :begin ref_0_0<=ref_47_r; ref_0_1<=ref_48_r; ref_0_2<=ref_49_r; ref_0_3<=ref_50_r; ref_0_4<=ref_51_r; end
47 :begin ref_0_0<=ref_48_r; ref_0_1<=ref_49_r; ref_0_2<=ref_50_r; ref_0_3<=ref_51_r; ref_0_4<=ref_52_r; end
48 :begin ref_0_0<=ref_49_r; ref_0_1<=ref_50_r; ref_0_2<=ref_51_r; ref_0_3<=ref_52_r; ref_0_4<=ref_53_r; end
49 :begin ref_0_0<=ref_50_r; ref_0_1<=ref_51_r; ref_0_2<=ref_52_r; ref_0_3<=ref_53_r; ref_0_4<=ref_54_r; end
50 :begin ref_0_0<=ref_51_r; ref_0_1<=ref_52_r; ref_0_2<=ref_53_r; ref_0_3<=ref_54_r; ref_0_4<=ref_55_r; end
51 :begin ref_0_0<=ref_52_r; ref_0_1<=ref_53_r; ref_0_2<=ref_54_r; ref_0_3<=ref_55_r; ref_0_4<=ref_56_r; end
52 :begin ref_0_0<=ref_53_r; ref_0_1<=ref_54_r; ref_0_2<=ref_55_r; ref_0_3<=ref_56_r; ref_0_4<=ref_57_r; end
53 :begin ref_0_0<=ref_54_r; ref_0_1<=ref_55_r; ref_0_2<=ref_56_r; ref_0_3<=ref_57_r; ref_0_4<=ref_58_r; end
54 :begin ref_0_0<=ref_55_r; ref_0_1<=ref_56_r; ref_0_2<=ref_57_r; ref_0_3<=ref_58_r; ref_0_4<=ref_59_r; end
55 :begin ref_0_0<=ref_56_r; ref_0_1<=ref_57_r; ref_0_2<=ref_58_r; ref_0_3<=ref_59_r; ref_0_4<=ref_60_r; end
56 :begin ref_0_0<=ref_57_r; ref_0_1<=ref_58_r; ref_0_2<=ref_59_r; ref_0_3<=ref_60_r; ref_0_4<=ref_61_r; end
57 :begin ref_0_0<=ref_58_r; ref_0_1<=ref_59_r; ref_0_2<=ref_60_r; ref_0_3<=ref_61_r; ref_0_4<=ref_62_r; end
58 :begin ref_0_0<=ref_59_r; ref_0_1<=ref_60_r; ref_0_2<=ref_61_r; ref_0_3<=ref_62_r; ref_0_4<=ref_63_r; end
59 :begin ref_0_0<=ref_60_r; ref_0_1<=ref_61_r; ref_0_2<=ref_62_r; ref_0_3<=ref_63_r; ref_0_4<=ref_64_r; end
60 :begin ref_0_0<=ref_61_r; ref_0_1<=ref_62_r; ref_0_2<=ref_63_r; ref_0_3<=ref_64_r; ref_0_4<=ref_64_r; end
endcase
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
ref_1_0<='d0; ref_1_1<='d0; ref_1_2<='d0; ref_1_3<='d0; ref_1_4<='d0;
end
else begin
case (ref_idx1_w)
-32 :begin ref_1_0<=ref_x31_r; ref_1_1<=ref_x30_r; ref_1_2<=ref_x29_r; ref_1_3<=ref_x28_r; ref_1_4<=ref_x27_r; end
-31 :begin ref_1_0<=ref_x30_r; ref_1_1<=ref_x29_r; ref_1_2<=ref_x28_r; ref_1_3<=ref_x27_r; ref_1_4<=ref_x26_r; end
-30 :begin ref_1_0<=ref_x29_r; ref_1_1<=ref_x28_r; ref_1_2<=ref_x27_r; ref_1_3<=ref_x26_r; ref_1_4<=ref_x25_r; end
-29 :begin ref_1_0<=ref_x28_r; ref_1_1<=ref_x27_r; ref_1_2<=ref_x26_r; ref_1_3<=ref_x25_r; ref_1_4<=ref_x24_r; end
-28 :begin ref_1_0<=ref_x27_r; ref_1_1<=ref_x26_r; ref_1_2<=ref_x25_r; ref_1_3<=ref_x24_r; ref_1_4<=ref_x23_r; end
-27 :begin ref_1_0<=ref_x26_r; ref_1_1<=ref_x25_r; ref_1_2<=ref_x24_r; ref_1_3<=ref_x23_r; ref_1_4<=ref_x22_r; end
-26 :begin ref_1_0<=ref_x25_r; ref_1_1<=ref_x24_r; ref_1_2<=ref_x23_r; ref_1_3<=ref_x22_r; ref_1_4<=ref_x21_r; end
-25 :begin ref_1_0<=ref_x24_r; ref_1_1<=ref_x23_r; ref_1_2<=ref_x22_r; ref_1_3<=ref_x21_r; ref_1_4<=ref_x20_r; end
-24 :begin ref_1_0<=ref_x23_r; ref_1_1<=ref_x22_r; ref_1_2<=ref_x21_r; ref_1_3<=ref_x20_r; ref_1_4<=ref_x19_r; end
-23 :begin ref_1_0<=ref_x22_r; ref_1_1<=ref_x21_r; ref_1_2<=ref_x20_r; ref_1_3<=ref_x19_r; ref_1_4<=ref_x18_r; end
-22 :begin ref_1_0<=ref_x21_r; ref_1_1<=ref_x20_r; ref_1_2<=ref_x19_r; ref_1_3<=ref_x18_r; ref_1_4<=ref_x17_r; end
-21 :begin ref_1_0<=ref_x20_r; ref_1_1<=ref_x19_r; ref_1_2<=ref_x18_r; ref_1_3<=ref_x17_r; ref_1_4<=ref_x16_r; end
-20 :begin ref_1_0<=ref_x19_r; ref_1_1<=ref_x18_r; ref_1_2<=ref_x17_r; ref_1_3<=ref_x16_r; ref_1_4<=ref_x15_r; end
-19 :begin ref_1_0<=ref_x18_r; ref_1_1<=ref_x17_r; ref_1_2<=ref_x16_r; ref_1_3<=ref_x15_r; ref_1_4<=ref_x14_r; end
-18 :begin ref_1_0<=ref_x17_r; ref_1_1<=ref_x16_r; ref_1_2<=ref_x15_r; ref_1_3<=ref_x14_r; ref_1_4<=ref_x13_r; end
-17 :begin ref_1_0<=ref_x16_r; ref_1_1<=ref_x15_r; ref_1_2<=ref_x14_r; ref_1_3<=ref_x13_r; ref_1_4<=ref_x12_r; end
-16 :begin ref_1_0<=ref_x15_r; ref_1_1<=ref_x14_r; ref_1_2<=ref_x13_r; ref_1_3<=ref_x12_r; ref_1_4<=ref_x11_r; end
-15 :begin ref_1_0<=ref_x14_r; ref_1_1<=ref_x13_r; ref_1_2<=ref_x12_r; ref_1_3<=ref_x11_r; ref_1_4<=ref_x10_r; end
-14 :begin ref_1_0<=ref_x13_r; ref_1_1<=ref_x12_r; ref_1_2<=ref_x11_r; ref_1_3<=ref_x10_r; ref_1_4<=ref_x09_r; end
-13 :begin ref_1_0<=ref_x12_r; ref_1_1<=ref_x11_r; ref_1_2<=ref_x10_r; ref_1_3<=ref_x09_r; ref_1_4<=ref_x08_r; end
-12 :begin ref_1_0<=ref_x11_r; ref_1_1<=ref_x10_r; ref_1_2<=ref_x09_r; ref_1_3<=ref_x08_r; ref_1_4<=ref_x07_r; end
-11 :begin ref_1_0<=ref_x10_r; ref_1_1<=ref_x09_r; ref_1_2<=ref_x08_r; ref_1_3<=ref_x07_r; ref_1_4<=ref_x06_r; end
-10 :begin ref_1_0<=ref_x09_r; ref_1_1<=ref_x08_r; ref_1_2<=ref_x07_r; ref_1_3<=ref_x06_r; ref_1_4<=ref_x05_r; end
- 9 :begin ref_1_0<=ref_x08_r; ref_1_1<=ref_x07_r; ref_1_2<=ref_x06_r; ref_1_3<=ref_x05_r; ref_1_4<=ref_x04_r; end
- 8 :begin ref_1_0<=ref_x07_r; ref_1_1<=ref_x06_r; ref_1_2<=ref_x05_r; ref_1_3<=ref_x04_r; ref_1_4<=ref_x03_r; end
- 7 :begin ref_1_0<=ref_x06_r; ref_1_1<=ref_x05_r; ref_1_2<=ref_x04_r; ref_1_3<=ref_x03_r; ref_1_4<=ref_x02_r; end
- 6 :begin ref_1_0<=ref_x05_r; ref_1_1<=ref_x04_r; ref_1_2<=ref_x03_r; ref_1_3<=ref_x02_r; ref_1_4<=ref_x01_r; end
- 5 :begin ref_1_0<=ref_x04_r; ref_1_1<=ref_x03_r; ref_1_2<=ref_x02_r; ref_1_3<=ref_x01_r; ref_1_4<=ref_00_r; end
- 4 :begin ref_1_0<=ref_x03_r; ref_1_1<=ref_x02_r; ref_1_2<=ref_x01_r; ref_1_3<=ref_00_r; ref_1_4<=ref_01_r; end
- 3 :begin ref_1_0<=ref_x02_r; ref_1_1<=ref_x01_r; ref_1_2<=ref_00_r; ref_1_3<=ref_01_r; ref_1_4<=ref_02_r; end
- 2 :begin ref_1_0<=ref_x01_r; ref_1_1<=ref_00_r; ref_1_2<=ref_01_r; ref_1_3<=ref_02_r; ref_1_4<=ref_03_r; end
- 1 :begin ref_1_0<=ref_00_r; ref_1_1<=ref_01_r; ref_1_2<=ref_02_r; ref_1_3<=ref_03_r; ref_1_4<=ref_04_r; end
0 :begin ref_1_0<=ref_01_r; ref_1_1<=ref_02_r; ref_1_2<=ref_03_r; ref_1_3<=ref_04_r; ref_1_4<=ref_05_r; end
1 :begin ref_1_0<=ref_02_r; ref_1_1<=ref_03_r; ref_1_2<=ref_04_r; ref_1_3<=ref_05_r; ref_1_4<=ref_06_r; end
2 :begin ref_1_0<=ref_03_r; ref_1_1<=ref_04_r; ref_1_2<=ref_05_r; ref_1_3<=ref_06_r; ref_1_4<=ref_07_r; end
3 :begin ref_1_0<=ref_04_r; ref_1_1<=ref_05_r; ref_1_2<=ref_06_r; ref_1_3<=ref_07_r; ref_1_4<=ref_08_r; end
4 :begin ref_1_0<=ref_05_r; ref_1_1<=ref_06_r; ref_1_2<=ref_07_r; ref_1_3<=ref_08_r; ref_1_4<=ref_09_r; end
5 :begin ref_1_0<=ref_06_r; ref_1_1<=ref_07_r; ref_1_2<=ref_08_r; ref_1_3<=ref_09_r; ref_1_4<=ref_10_r; end
6 :begin ref_1_0<=ref_07_r; ref_1_1<=ref_08_r; ref_1_2<=ref_09_r; ref_1_3<=ref_10_r; ref_1_4<=ref_11_r; end
7 :begin ref_1_0<=ref_08_r; ref_1_1<=ref_09_r; ref_1_2<=ref_10_r; ref_1_3<=ref_11_r; ref_1_4<=ref_12_r; end
8 :begin ref_1_0<=ref_09_r; ref_1_1<=ref_10_r; ref_1_2<=ref_11_r; ref_1_3<=ref_12_r; ref_1_4<=ref_13_r; end
9 :begin ref_1_0<=ref_10_r; ref_1_1<=ref_11_r; ref_1_2<=ref_12_r; ref_1_3<=ref_13_r; ref_1_4<=ref_14_r; end
10 :begin ref_1_0<=ref_11_r; ref_1_1<=ref_12_r; ref_1_2<=ref_13_r; ref_1_3<=ref_14_r; ref_1_4<=ref_15_r; end
11 :begin ref_1_0<=ref_12_r; ref_1_1<=ref_13_r; ref_1_2<=ref_14_r; ref_1_3<=ref_15_r; ref_1_4<=ref_16_r; end
12 :begin ref_1_0<=ref_13_r; ref_1_1<=ref_14_r; ref_1_2<=ref_15_r; ref_1_3<=ref_16_r; ref_1_4<=ref_17_r; end
13 :begin ref_1_0<=ref_14_r; ref_1_1<=ref_15_r; ref_1_2<=ref_16_r; ref_1_3<=ref_17_r; ref_1_4<=ref_18_r; end
14 :begin ref_1_0<=ref_15_r; ref_1_1<=ref_16_r; ref_1_2<=ref_17_r; ref_1_3<=ref_18_r; ref_1_4<=ref_19_r; end
15 :begin ref_1_0<=ref_16_r; ref_1_1<=ref_17_r; ref_1_2<=ref_18_r; ref_1_3<=ref_19_r; ref_1_4<=ref_20_r; end
16 :begin ref_1_0<=ref_17_r; ref_1_1<=ref_18_r; ref_1_2<=ref_19_r; ref_1_3<=ref_20_r; ref_1_4<=ref_21_r; end
17 :begin ref_1_0<=ref_18_r; ref_1_1<=ref_19_r; ref_1_2<=ref_20_r; ref_1_3<=ref_21_r; ref_1_4<=ref_22_r; end
18 :begin ref_1_0<=ref_19_r; ref_1_1<=ref_20_r; ref_1_2<=ref_21_r; ref_1_3<=ref_22_r; ref_1_4<=ref_23_r; end
19 :begin ref_1_0<=ref_20_r; ref_1_1<=ref_21_r; ref_1_2<=ref_22_r; ref_1_3<=ref_23_r; ref_1_4<=ref_24_r; end
20 :begin ref_1_0<=ref_21_r; ref_1_1<=ref_22_r; ref_1_2<=ref_23_r; ref_1_3<=ref_24_r; ref_1_4<=ref_25_r; end
21 :begin ref_1_0<=ref_22_r; ref_1_1<=ref_23_r; ref_1_2<=ref_24_r; ref_1_3<=ref_25_r; ref_1_4<=ref_26_r; end
22 :begin ref_1_0<=ref_23_r; ref_1_1<=ref_24_r; ref_1_2<=ref_25_r; ref_1_3<=ref_26_r; ref_1_4<=ref_27_r; end
23 :begin ref_1_0<=ref_24_r; ref_1_1<=ref_25_r; ref_1_2<=ref_26_r; ref_1_3<=ref_27_r; ref_1_4<=ref_28_r; end
24 :begin ref_1_0<=ref_25_r; ref_1_1<=ref_26_r; ref_1_2<=ref_27_r; ref_1_3<=ref_28_r; ref_1_4<=ref_29_r; end
25 :begin ref_1_0<=ref_26_r; ref_1_1<=ref_27_r; ref_1_2<=ref_28_r; ref_1_3<=ref_29_r; ref_1_4<=ref_30_r; end
26 :begin ref_1_0<=ref_27_r; ref_1_1<=ref_28_r; ref_1_2<=ref_29_r; ref_1_3<=ref_30_r; ref_1_4<=ref_31_r; end
27 :begin ref_1_0<=ref_28_r; ref_1_1<=ref_29_r; ref_1_2<=ref_30_r; ref_1_3<=ref_31_r; ref_1_4<=ref_32_r; end
28 :begin ref_1_0<=ref_29_r; ref_1_1<=ref_30_r; ref_1_2<=ref_31_r; ref_1_3<=ref_32_r; ref_1_4<=ref_33_r; end
29 :begin ref_1_0<=ref_30_r; ref_1_1<=ref_31_r; ref_1_2<=ref_32_r; ref_1_3<=ref_33_r; ref_1_4<=ref_34_r; end
30 :begin ref_1_0<=ref_31_r; ref_1_1<=ref_32_r; ref_1_2<=ref_33_r; ref_1_3<=ref_34_r; ref_1_4<=ref_35_r; end
31 :begin ref_1_0<=ref_32_r; ref_1_1<=ref_33_r; ref_1_2<=ref_34_r; ref_1_3<=ref_35_r; ref_1_4<=ref_36_r; end
32 :begin ref_1_0<=ref_33_r; ref_1_1<=ref_34_r; ref_1_2<=ref_35_r; ref_1_3<=ref_36_r; ref_1_4<=ref_37_r; end
33 :begin ref_1_0<=ref_34_r; ref_1_1<=ref_35_r; ref_1_2<=ref_36_r; ref_1_3<=ref_37_r; ref_1_4<=ref_38_r; end
34 :begin ref_1_0<=ref_35_r; ref_1_1<=ref_36_r; ref_1_2<=ref_37_r; ref_1_3<=ref_38_r; ref_1_4<=ref_39_r; end
35 :begin ref_1_0<=ref_36_r; ref_1_1<=ref_37_r; ref_1_2<=ref_38_r; ref_1_3<=ref_39_r; ref_1_4<=ref_40_r; end
36 :begin ref_1_0<=ref_37_r; ref_1_1<=ref_38_r; ref_1_2<=ref_39_r; ref_1_3<=ref_40_r; ref_1_4<=ref_41_r; end
37 :begin ref_1_0<=ref_38_r; ref_1_1<=ref_39_r; ref_1_2<=ref_40_r; ref_1_3<=ref_41_r; ref_1_4<=ref_42_r; end
38 :begin ref_1_0<=ref_39_r; ref_1_1<=ref_40_r; ref_1_2<=ref_41_r; ref_1_3<=ref_42_r; ref_1_4<=ref_43_r; end
39 :begin ref_1_0<=ref_40_r; ref_1_1<=ref_41_r; ref_1_2<=ref_42_r; ref_1_3<=ref_43_r; ref_1_4<=ref_44_r; end
40 :begin ref_1_0<=ref_41_r; ref_1_1<=ref_42_r; ref_1_2<=ref_43_r; ref_1_3<=ref_44_r; ref_1_4<=ref_45_r; end
41 :begin ref_1_0<=ref_42_r; ref_1_1<=ref_43_r; ref_1_2<=ref_44_r; ref_1_3<=ref_45_r; ref_1_4<=ref_46_r; end
42 :begin ref_1_0<=ref_43_r; ref_1_1<=ref_44_r; ref_1_2<=ref_45_r; ref_1_3<=ref_46_r; ref_1_4<=ref_47_r; end
43 :begin ref_1_0<=ref_44_r; ref_1_1<=ref_45_r; ref_1_2<=ref_46_r; ref_1_3<=ref_47_r; ref_1_4<=ref_48_r; end
44 :begin ref_1_0<=ref_45_r; ref_1_1<=ref_46_r; ref_1_2<=ref_47_r; ref_1_3<=ref_48_r; ref_1_4<=ref_49_r; end
45 :begin ref_1_0<=ref_46_r; ref_1_1<=ref_47_r; ref_1_2<=ref_48_r; ref_1_3<=ref_49_r; ref_1_4<=ref_50_r; end
46 :begin ref_1_0<=ref_47_r; ref_1_1<=ref_48_r; ref_1_2<=ref_49_r; ref_1_3<=ref_50_r; ref_1_4<=ref_51_r; end
47 :begin ref_1_0<=ref_48_r; ref_1_1<=ref_49_r; ref_1_2<=ref_50_r; ref_1_3<=ref_51_r; ref_1_4<=ref_52_r; end
48 :begin ref_1_0<=ref_49_r; ref_1_1<=ref_50_r; ref_1_2<=ref_51_r; ref_1_3<=ref_52_r; ref_1_4<=ref_53_r; end
49 :begin ref_1_0<=ref_50_r; ref_1_1<=ref_51_r; ref_1_2<=ref_52_r; ref_1_3<=ref_53_r; ref_1_4<=ref_54_r; end
50 :begin ref_1_0<=ref_51_r; ref_1_1<=ref_52_r; ref_1_2<=ref_53_r; ref_1_3<=ref_54_r; ref_1_4<=ref_55_r; end
51 :begin ref_1_0<=ref_52_r; ref_1_1<=ref_53_r; ref_1_2<=ref_54_r; ref_1_3<=ref_55_r; ref_1_4<=ref_56_r; end
52 :begin ref_1_0<=ref_53_r; ref_1_1<=ref_54_r; ref_1_2<=ref_55_r; ref_1_3<=ref_56_r; ref_1_4<=ref_57_r; end
53 :begin ref_1_0<=ref_54_r; ref_1_1<=ref_55_r; ref_1_2<=ref_56_r; ref_1_3<=ref_57_r; ref_1_4<=ref_58_r; end
54 :begin ref_1_0<=ref_55_r; ref_1_1<=ref_56_r; ref_1_2<=ref_57_r; ref_1_3<=ref_58_r; ref_1_4<=ref_59_r; end
55 :begin ref_1_0<=ref_56_r; ref_1_1<=ref_57_r; ref_1_2<=ref_58_r; ref_1_3<=ref_59_r; ref_1_4<=ref_60_r; end
56 :begin ref_1_0<=ref_57_r; ref_1_1<=ref_58_r; ref_1_2<=ref_59_r; ref_1_3<=ref_60_r; ref_1_4<=ref_61_r; end
57 :begin ref_1_0<=ref_58_r; ref_1_1<=ref_59_r; ref_1_2<=ref_60_r; ref_1_3<=ref_61_r; ref_1_4<=ref_62_r; end
58 :begin ref_1_0<=ref_59_r; ref_1_1<=ref_60_r; ref_1_2<=ref_61_r; ref_1_3<=ref_62_r; ref_1_4<=ref_63_r; end
59 :begin ref_1_0<=ref_60_r; ref_1_1<=ref_61_r; ref_1_2<=ref_62_r; ref_1_3<=ref_63_r; ref_1_4<=ref_64_r; end
60 :begin ref_1_0<=ref_61_r; ref_1_1<=ref_62_r; ref_1_2<=ref_63_r; ref_1_3<=ref_64_r; ref_1_4<=ref_64_r; end
endcase
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
ref_2_0<='d0; ref_2_1<='d0; ref_2_2<='d0; ref_2_3<='d0; ref_2_4<='d0;
end
else begin
case (ref_idx2_w)
-32 :begin ref_2_0<=ref_x31_r; ref_2_1<=ref_x30_r; ref_2_2<=ref_x29_r; ref_2_3<=ref_x28_r; ref_2_4<=ref_x27_r; end
-31 :begin ref_2_0<=ref_x30_r; ref_2_1<=ref_x29_r; ref_2_2<=ref_x28_r; ref_2_3<=ref_x27_r; ref_2_4<=ref_x26_r; end
-30 :begin ref_2_0<=ref_x29_r; ref_2_1<=ref_x28_r; ref_2_2<=ref_x27_r; ref_2_3<=ref_x26_r; ref_2_4<=ref_x25_r; end
-29 :begin ref_2_0<=ref_x28_r; ref_2_1<=ref_x27_r; ref_2_2<=ref_x26_r; ref_2_3<=ref_x25_r; ref_2_4<=ref_x24_r; end
-28 :begin ref_2_0<=ref_x27_r; ref_2_1<=ref_x26_r; ref_2_2<=ref_x25_r; ref_2_3<=ref_x24_r; ref_2_4<=ref_x23_r; end
-27 :begin ref_2_0<=ref_x26_r; ref_2_1<=ref_x25_r; ref_2_2<=ref_x24_r; ref_2_3<=ref_x23_r; ref_2_4<=ref_x22_r; end
-26 :begin ref_2_0<=ref_x25_r; ref_2_1<=ref_x24_r; ref_2_2<=ref_x23_r; ref_2_3<=ref_x22_r; ref_2_4<=ref_x21_r; end
-25 :begin ref_2_0<=ref_x24_r; ref_2_1<=ref_x23_r; ref_2_2<=ref_x22_r; ref_2_3<=ref_x21_r; ref_2_4<=ref_x20_r; end
-24 :begin ref_2_0<=ref_x23_r; ref_2_1<=ref_x22_r; ref_2_2<=ref_x21_r; ref_2_3<=ref_x20_r; ref_2_4<=ref_x19_r; end
-23 :begin ref_2_0<=ref_x22_r; ref_2_1<=ref_x21_r; ref_2_2<=ref_x20_r; ref_2_3<=ref_x19_r; ref_2_4<=ref_x18_r; end
-22 :begin ref_2_0<=ref_x21_r; ref_2_1<=ref_x20_r; ref_2_2<=ref_x19_r; ref_2_3<=ref_x18_r; ref_2_4<=ref_x17_r; end
-21 :begin ref_2_0<=ref_x20_r; ref_2_1<=ref_x19_r; ref_2_2<=ref_x18_r; ref_2_3<=ref_x17_r; ref_2_4<=ref_x16_r; end
-20 :begin ref_2_0<=ref_x19_r; ref_2_1<=ref_x18_r; ref_2_2<=ref_x17_r; ref_2_3<=ref_x16_r; ref_2_4<=ref_x15_r; end
-19 :begin ref_2_0<=ref_x18_r; ref_2_1<=ref_x17_r; ref_2_2<=ref_x16_r; ref_2_3<=ref_x15_r; ref_2_4<=ref_x14_r; end
-18 :begin ref_2_0<=ref_x17_r; ref_2_1<=ref_x16_r; ref_2_2<=ref_x15_r; ref_2_3<=ref_x14_r; ref_2_4<=ref_x13_r; end
-17 :begin ref_2_0<=ref_x16_r; ref_2_1<=ref_x15_r; ref_2_2<=ref_x14_r; ref_2_3<=ref_x13_r; ref_2_4<=ref_x12_r; end
-16 :begin ref_2_0<=ref_x15_r; ref_2_1<=ref_x14_r; ref_2_2<=ref_x13_r; ref_2_3<=ref_x12_r; ref_2_4<=ref_x11_r; end
-15 :begin ref_2_0<=ref_x14_r; ref_2_1<=ref_x13_r; ref_2_2<=ref_x12_r; ref_2_3<=ref_x11_r; ref_2_4<=ref_x10_r; end
-14 :begin ref_2_0<=ref_x13_r; ref_2_1<=ref_x12_r; ref_2_2<=ref_x11_r; ref_2_3<=ref_x10_r; ref_2_4<=ref_x09_r; end
-13 :begin ref_2_0<=ref_x12_r; ref_2_1<=ref_x11_r; ref_2_2<=ref_x10_r; ref_2_3<=ref_x09_r; ref_2_4<=ref_x08_r; end
-12 :begin ref_2_0<=ref_x11_r; ref_2_1<=ref_x10_r; ref_2_2<=ref_x09_r; ref_2_3<=ref_x08_r; ref_2_4<=ref_x07_r; end
-11 :begin ref_2_0<=ref_x10_r; ref_2_1<=ref_x09_r; ref_2_2<=ref_x08_r; ref_2_3<=ref_x07_r; ref_2_4<=ref_x06_r; end
-10 :begin ref_2_0<=ref_x09_r; ref_2_1<=ref_x08_r; ref_2_2<=ref_x07_r; ref_2_3<=ref_x06_r; ref_2_4<=ref_x05_r; end
- 9 :begin ref_2_0<=ref_x08_r; ref_2_1<=ref_x07_r; ref_2_2<=ref_x06_r; ref_2_3<=ref_x05_r; ref_2_4<=ref_x04_r; end
- 8 :begin ref_2_0<=ref_x07_r; ref_2_1<=ref_x06_r; ref_2_2<=ref_x05_r; ref_2_3<=ref_x04_r; ref_2_4<=ref_x03_r; end
- 7 :begin ref_2_0<=ref_x06_r; ref_2_1<=ref_x05_r; ref_2_2<=ref_x04_r; ref_2_3<=ref_x03_r; ref_2_4<=ref_x02_r; end
- 6 :begin ref_2_0<=ref_x05_r; ref_2_1<=ref_x04_r; ref_2_2<=ref_x03_r; ref_2_3<=ref_x02_r; ref_2_4<=ref_x01_r; end
- 5 :begin ref_2_0<=ref_x04_r; ref_2_1<=ref_x03_r; ref_2_2<=ref_x02_r; ref_2_3<=ref_x01_r; ref_2_4<=ref_00_r; end
- 4 :begin ref_2_0<=ref_x03_r; ref_2_1<=ref_x02_r; ref_2_2<=ref_x01_r; ref_2_3<=ref_00_r; ref_2_4<=ref_01_r; end
- 3 :begin ref_2_0<=ref_x02_r; ref_2_1<=ref_x01_r; ref_2_2<=ref_00_r; ref_2_3<=ref_01_r; ref_2_4<=ref_02_r; end
- 2 :begin ref_2_0<=ref_x01_r; ref_2_1<=ref_00_r; ref_2_2<=ref_01_r; ref_2_3<=ref_02_r; ref_2_4<=ref_03_r; end
- 1 :begin ref_2_0<=ref_00_r; ref_2_1<=ref_01_r; ref_2_2<=ref_02_r; ref_2_3<=ref_03_r; ref_2_4<=ref_04_r; end
0 :begin ref_2_0<=ref_01_r; ref_2_1<=ref_02_r; ref_2_2<=ref_03_r; ref_2_3<=ref_04_r; ref_2_4<=ref_05_r; end
1 :begin ref_2_0<=ref_02_r; ref_2_1<=ref_03_r; ref_2_2<=ref_04_r; ref_2_3<=ref_05_r; ref_2_4<=ref_06_r; end
2 :begin ref_2_0<=ref_03_r; ref_2_1<=ref_04_r; ref_2_2<=ref_05_r; ref_2_3<=ref_06_r; ref_2_4<=ref_07_r; end
3 :begin ref_2_0<=ref_04_r; ref_2_1<=ref_05_r; ref_2_2<=ref_06_r; ref_2_3<=ref_07_r; ref_2_4<=ref_08_r; end
4 :begin ref_2_0<=ref_05_r; ref_2_1<=ref_06_r; ref_2_2<=ref_07_r; ref_2_3<=ref_08_r; ref_2_4<=ref_09_r; end
5 :begin ref_2_0<=ref_06_r; ref_2_1<=ref_07_r; ref_2_2<=ref_08_r; ref_2_3<=ref_09_r; ref_2_4<=ref_10_r; end
6 :begin ref_2_0<=ref_07_r; ref_2_1<=ref_08_r; ref_2_2<=ref_09_r; ref_2_3<=ref_10_r; ref_2_4<=ref_11_r; end
7 :begin ref_2_0<=ref_08_r; ref_2_1<=ref_09_r; ref_2_2<=ref_10_r; ref_2_3<=ref_11_r; ref_2_4<=ref_12_r; end
8 :begin ref_2_0<=ref_09_r; ref_2_1<=ref_10_r; ref_2_2<=ref_11_r; ref_2_3<=ref_12_r; ref_2_4<=ref_13_r; end
9 :begin ref_2_0<=ref_10_r; ref_2_1<=ref_11_r; ref_2_2<=ref_12_r; ref_2_3<=ref_13_r; ref_2_4<=ref_14_r; end
10 :begin ref_2_0<=ref_11_r; ref_2_1<=ref_12_r; ref_2_2<=ref_13_r; ref_2_3<=ref_14_r; ref_2_4<=ref_15_r; end
11 :begin ref_2_0<=ref_12_r; ref_2_1<=ref_13_r; ref_2_2<=ref_14_r; ref_2_3<=ref_15_r; ref_2_4<=ref_16_r; end
12 :begin ref_2_0<=ref_13_r; ref_2_1<=ref_14_r; ref_2_2<=ref_15_r; ref_2_3<=ref_16_r; ref_2_4<=ref_17_r; end
13 :begin ref_2_0<=ref_14_r; ref_2_1<=ref_15_r; ref_2_2<=ref_16_r; ref_2_3<=ref_17_r; ref_2_4<=ref_18_r; end
14 :begin ref_2_0<=ref_15_r; ref_2_1<=ref_16_r; ref_2_2<=ref_17_r; ref_2_3<=ref_18_r; ref_2_4<=ref_19_r; end
15 :begin ref_2_0<=ref_16_r; ref_2_1<=ref_17_r; ref_2_2<=ref_18_r; ref_2_3<=ref_19_r; ref_2_4<=ref_20_r; end
16 :begin ref_2_0<=ref_17_r; ref_2_1<=ref_18_r; ref_2_2<=ref_19_r; ref_2_3<=ref_20_r; ref_2_4<=ref_21_r; end
17 :begin ref_2_0<=ref_18_r; ref_2_1<=ref_19_r; ref_2_2<=ref_20_r; ref_2_3<=ref_21_r; ref_2_4<=ref_22_r; end
18 :begin ref_2_0<=ref_19_r; ref_2_1<=ref_20_r; ref_2_2<=ref_21_r; ref_2_3<=ref_22_r; ref_2_4<=ref_23_r; end
19 :begin ref_2_0<=ref_20_r; ref_2_1<=ref_21_r; ref_2_2<=ref_22_r; ref_2_3<=ref_23_r; ref_2_4<=ref_24_r; end
20 :begin ref_2_0<=ref_21_r; ref_2_1<=ref_22_r; ref_2_2<=ref_23_r; ref_2_3<=ref_24_r; ref_2_4<=ref_25_r; end
21 :begin ref_2_0<=ref_22_r; ref_2_1<=ref_23_r; ref_2_2<=ref_24_r; ref_2_3<=ref_25_r; ref_2_4<=ref_26_r; end
22 :begin ref_2_0<=ref_23_r; ref_2_1<=ref_24_r; ref_2_2<=ref_25_r; ref_2_3<=ref_26_r; ref_2_4<=ref_27_r; end
23 :begin ref_2_0<=ref_24_r; ref_2_1<=ref_25_r; ref_2_2<=ref_26_r; ref_2_3<=ref_27_r; ref_2_4<=ref_28_r; end
24 :begin ref_2_0<=ref_25_r; ref_2_1<=ref_26_r; ref_2_2<=ref_27_r; ref_2_3<=ref_28_r; ref_2_4<=ref_29_r; end
25 :begin ref_2_0<=ref_26_r; ref_2_1<=ref_27_r; ref_2_2<=ref_28_r; ref_2_3<=ref_29_r; ref_2_4<=ref_30_r; end
26 :begin ref_2_0<=ref_27_r; ref_2_1<=ref_28_r; ref_2_2<=ref_29_r; ref_2_3<=ref_30_r; ref_2_4<=ref_31_r; end
27 :begin ref_2_0<=ref_28_r; ref_2_1<=ref_29_r; ref_2_2<=ref_30_r; ref_2_3<=ref_31_r; ref_2_4<=ref_32_r; end
28 :begin ref_2_0<=ref_29_r; ref_2_1<=ref_30_r; ref_2_2<=ref_31_r; ref_2_3<=ref_32_r; ref_2_4<=ref_33_r; end
29 :begin ref_2_0<=ref_30_r; ref_2_1<=ref_31_r; ref_2_2<=ref_32_r; ref_2_3<=ref_33_r; ref_2_4<=ref_34_r; end
30 :begin ref_2_0<=ref_31_r; ref_2_1<=ref_32_r; ref_2_2<=ref_33_r; ref_2_3<=ref_34_r; ref_2_4<=ref_35_r; end
31 :begin ref_2_0<=ref_32_r; ref_2_1<=ref_33_r; ref_2_2<=ref_34_r; ref_2_3<=ref_35_r; ref_2_4<=ref_36_r; end
32 :begin ref_2_0<=ref_33_r; ref_2_1<=ref_34_r; ref_2_2<=ref_35_r; ref_2_3<=ref_36_r; ref_2_4<=ref_37_r; end
33 :begin ref_2_0<=ref_34_r; ref_2_1<=ref_35_r; ref_2_2<=ref_36_r; ref_2_3<=ref_37_r; ref_2_4<=ref_38_r; end
34 :begin ref_2_0<=ref_35_r; ref_2_1<=ref_36_r; ref_2_2<=ref_37_r; ref_2_3<=ref_38_r; ref_2_4<=ref_39_r; end
35 :begin ref_2_0<=ref_36_r; ref_2_1<=ref_37_r; ref_2_2<=ref_38_r; ref_2_3<=ref_39_r; ref_2_4<=ref_40_r; end
36 :begin ref_2_0<=ref_37_r; ref_2_1<=ref_38_r; ref_2_2<=ref_39_r; ref_2_3<=ref_40_r; ref_2_4<=ref_41_r; end
37 :begin ref_2_0<=ref_38_r; ref_2_1<=ref_39_r; ref_2_2<=ref_40_r; ref_2_3<=ref_41_r; ref_2_4<=ref_42_r; end
38 :begin ref_2_0<=ref_39_r; ref_2_1<=ref_40_r; ref_2_2<=ref_41_r; ref_2_3<=ref_42_r; ref_2_4<=ref_43_r; end
39 :begin ref_2_0<=ref_40_r; ref_2_1<=ref_41_r; ref_2_2<=ref_42_r; ref_2_3<=ref_43_r; ref_2_4<=ref_44_r; end
40 :begin ref_2_0<=ref_41_r; ref_2_1<=ref_42_r; ref_2_2<=ref_43_r; ref_2_3<=ref_44_r; ref_2_4<=ref_45_r; end
41 :begin ref_2_0<=ref_42_r; ref_2_1<=ref_43_r; ref_2_2<=ref_44_r; ref_2_3<=ref_45_r; ref_2_4<=ref_46_r; end
42 :begin ref_2_0<=ref_43_r; ref_2_1<=ref_44_r; ref_2_2<=ref_45_r; ref_2_3<=ref_46_r; ref_2_4<=ref_47_r; end
43 :begin ref_2_0<=ref_44_r; ref_2_1<=ref_45_r; ref_2_2<=ref_46_r; ref_2_3<=ref_47_r; ref_2_4<=ref_48_r; end
44 :begin ref_2_0<=ref_45_r; ref_2_1<=ref_46_r; ref_2_2<=ref_47_r; ref_2_3<=ref_48_r; ref_2_4<=ref_49_r; end
45 :begin ref_2_0<=ref_46_r; ref_2_1<=ref_47_r; ref_2_2<=ref_48_r; ref_2_3<=ref_49_r; ref_2_4<=ref_50_r; end
46 :begin ref_2_0<=ref_47_r; ref_2_1<=ref_48_r; ref_2_2<=ref_49_r; ref_2_3<=ref_50_r; ref_2_4<=ref_51_r; end
47 :begin ref_2_0<=ref_48_r; ref_2_1<=ref_49_r; ref_2_2<=ref_50_r; ref_2_3<=ref_51_r; ref_2_4<=ref_52_r; end
48 :begin ref_2_0<=ref_49_r; ref_2_1<=ref_50_r; ref_2_2<=ref_51_r; ref_2_3<=ref_52_r; ref_2_4<=ref_53_r; end
49 :begin ref_2_0<=ref_50_r; ref_2_1<=ref_51_r; ref_2_2<=ref_52_r; ref_2_3<=ref_53_r; ref_2_4<=ref_54_r; end
50 :begin ref_2_0<=ref_51_r; ref_2_1<=ref_52_r; ref_2_2<=ref_53_r; ref_2_3<=ref_54_r; ref_2_4<=ref_55_r; end
51 :begin ref_2_0<=ref_52_r; ref_2_1<=ref_53_r; ref_2_2<=ref_54_r; ref_2_3<=ref_55_r; ref_2_4<=ref_56_r; end
52 :begin ref_2_0<=ref_53_r; ref_2_1<=ref_54_r; ref_2_2<=ref_55_r; ref_2_3<=ref_56_r; ref_2_4<=ref_57_r; end
53 :begin ref_2_0<=ref_54_r; ref_2_1<=ref_55_r; ref_2_2<=ref_56_r; ref_2_3<=ref_57_r; ref_2_4<=ref_58_r; end
54 :begin ref_2_0<=ref_55_r; ref_2_1<=ref_56_r; ref_2_2<=ref_57_r; ref_2_3<=ref_58_r; ref_2_4<=ref_59_r; end
55 :begin ref_2_0<=ref_56_r; ref_2_1<=ref_57_r; ref_2_2<=ref_58_r; ref_2_3<=ref_59_r; ref_2_4<=ref_60_r; end
56 :begin ref_2_0<=ref_57_r; ref_2_1<=ref_58_r; ref_2_2<=ref_59_r; ref_2_3<=ref_60_r; ref_2_4<=ref_61_r; end
57 :begin ref_2_0<=ref_58_r; ref_2_1<=ref_59_r; ref_2_2<=ref_60_r; ref_2_3<=ref_61_r; ref_2_4<=ref_62_r; end
58 :begin ref_2_0<=ref_59_r; ref_2_1<=ref_60_r; ref_2_2<=ref_61_r; ref_2_3<=ref_62_r; ref_2_4<=ref_63_r; end
59 :begin ref_2_0<=ref_60_r; ref_2_1<=ref_61_r; ref_2_2<=ref_62_r; ref_2_3<=ref_63_r; ref_2_4<=ref_64_r; end
60 :begin ref_2_0<=ref_61_r; ref_2_1<=ref_62_r; ref_2_2<=ref_63_r; ref_2_3<=ref_64_r; ref_2_4<=ref_64_r; end
endcase
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
ref_3_0<='d0; ref_3_1<='d0; ref_3_2<='d0; ref_3_3<='d0; ref_3_4<='d0;
end
else begin
case (ref_idx3_w)
-32 :begin ref_3_0<=ref_x31_r; ref_3_1<=ref_x30_r; ref_3_2<=ref_x29_r; ref_3_3<=ref_x28_r; ref_3_4<=ref_x27_r; end
-31 :begin ref_3_0<=ref_x30_r; ref_3_1<=ref_x29_r; ref_3_2<=ref_x28_r; ref_3_3<=ref_x27_r; ref_3_4<=ref_x26_r; end
-30 :begin ref_3_0<=ref_x29_r; ref_3_1<=ref_x28_r; ref_3_2<=ref_x27_r; ref_3_3<=ref_x26_r; ref_3_4<=ref_x25_r; end
-29 :begin ref_3_0<=ref_x28_r; ref_3_1<=ref_x27_r; ref_3_2<=ref_x26_r; ref_3_3<=ref_x25_r; ref_3_4<=ref_x24_r; end
-28 :begin ref_3_0<=ref_x27_r; ref_3_1<=ref_x26_r; ref_3_2<=ref_x25_r; ref_3_3<=ref_x24_r; ref_3_4<=ref_x23_r; end
-27 :begin ref_3_0<=ref_x26_r; ref_3_1<=ref_x25_r; ref_3_2<=ref_x24_r; ref_3_3<=ref_x23_r; ref_3_4<=ref_x22_r; end
-26 :begin ref_3_0<=ref_x25_r; ref_3_1<=ref_x24_r; ref_3_2<=ref_x23_r; ref_3_3<=ref_x22_r; ref_3_4<=ref_x21_r; end
-25 :begin ref_3_0<=ref_x24_r; ref_3_1<=ref_x23_r; ref_3_2<=ref_x22_r; ref_3_3<=ref_x21_r; ref_3_4<=ref_x20_r; end
-24 :begin ref_3_0<=ref_x23_r; ref_3_1<=ref_x22_r; ref_3_2<=ref_x21_r; ref_3_3<=ref_x20_r; ref_3_4<=ref_x19_r; end
-23 :begin ref_3_0<=ref_x22_r; ref_3_1<=ref_x21_r; ref_3_2<=ref_x20_r; ref_3_3<=ref_x19_r; ref_3_4<=ref_x18_r; end
-22 :begin ref_3_0<=ref_x21_r; ref_3_1<=ref_x20_r; ref_3_2<=ref_x19_r; ref_3_3<=ref_x18_r; ref_3_4<=ref_x17_r; end
-21 :begin ref_3_0<=ref_x20_r; ref_3_1<=ref_x19_r; ref_3_2<=ref_x18_r; ref_3_3<=ref_x17_r; ref_3_4<=ref_x16_r; end
-20 :begin ref_3_0<=ref_x19_r; ref_3_1<=ref_x18_r; ref_3_2<=ref_x17_r; ref_3_3<=ref_x16_r; ref_3_4<=ref_x15_r; end
-19 :begin ref_3_0<=ref_x18_r; ref_3_1<=ref_x17_r; ref_3_2<=ref_x16_r; ref_3_3<=ref_x15_r; ref_3_4<=ref_x14_r; end
-18 :begin ref_3_0<=ref_x17_r; ref_3_1<=ref_x16_r; ref_3_2<=ref_x15_r; ref_3_3<=ref_x14_r; ref_3_4<=ref_x13_r; end
-17 :begin ref_3_0<=ref_x16_r; ref_3_1<=ref_x15_r; ref_3_2<=ref_x14_r; ref_3_3<=ref_x13_r; ref_3_4<=ref_x12_r; end
-16 :begin ref_3_0<=ref_x15_r; ref_3_1<=ref_x14_r; ref_3_2<=ref_x13_r; ref_3_3<=ref_x12_r; ref_3_4<=ref_x11_r; end
-15 :begin ref_3_0<=ref_x14_r; ref_3_1<=ref_x13_r; ref_3_2<=ref_x12_r; ref_3_3<=ref_x11_r; ref_3_4<=ref_x10_r; end
-14 :begin ref_3_0<=ref_x13_r; ref_3_1<=ref_x12_r; ref_3_2<=ref_x11_r; ref_3_3<=ref_x10_r; ref_3_4<=ref_x09_r; end
-13 :begin ref_3_0<=ref_x12_r; ref_3_1<=ref_x11_r; ref_3_2<=ref_x10_r; ref_3_3<=ref_x09_r; ref_3_4<=ref_x08_r; end
-12 :begin ref_3_0<=ref_x11_r; ref_3_1<=ref_x10_r; ref_3_2<=ref_x09_r; ref_3_3<=ref_x08_r; ref_3_4<=ref_x07_r; end
-11 :begin ref_3_0<=ref_x10_r; ref_3_1<=ref_x09_r; ref_3_2<=ref_x08_r; ref_3_3<=ref_x07_r; ref_3_4<=ref_x06_r; end
-10 :begin ref_3_0<=ref_x09_r; ref_3_1<=ref_x08_r; ref_3_2<=ref_x07_r; ref_3_3<=ref_x06_r; ref_3_4<=ref_x05_r; end
- 9 :begin ref_3_0<=ref_x08_r; ref_3_1<=ref_x07_r; ref_3_2<=ref_x06_r; ref_3_3<=ref_x05_r; ref_3_4<=ref_x04_r; end
- 8 :begin ref_3_0<=ref_x07_r; ref_3_1<=ref_x06_r; ref_3_2<=ref_x05_r; ref_3_3<=ref_x04_r; ref_3_4<=ref_x03_r; end
- 7 :begin ref_3_0<=ref_x06_r; ref_3_1<=ref_x05_r; ref_3_2<=ref_x04_r; ref_3_3<=ref_x03_r; ref_3_4<=ref_x02_r; end
- 6 :begin ref_3_0<=ref_x05_r; ref_3_1<=ref_x04_r; ref_3_2<=ref_x03_r; ref_3_3<=ref_x02_r; ref_3_4<=ref_x01_r; end
- 5 :begin ref_3_0<=ref_x04_r; ref_3_1<=ref_x03_r; ref_3_2<=ref_x02_r; ref_3_3<=ref_x01_r; ref_3_4<=ref_00_r; end
- 4 :begin ref_3_0<=ref_x03_r; ref_3_1<=ref_x02_r; ref_3_2<=ref_x01_r; ref_3_3<=ref_00_r; ref_3_4<=ref_01_r; end
- 3 :begin ref_3_0<=ref_x02_r; ref_3_1<=ref_x01_r; ref_3_2<=ref_00_r; ref_3_3<=ref_01_r; ref_3_4<=ref_02_r; end
- 2 :begin ref_3_0<=ref_x01_r; ref_3_1<=ref_00_r; ref_3_2<=ref_01_r; ref_3_3<=ref_02_r; ref_3_4<=ref_03_r; end
- 1 :begin ref_3_0<=ref_00_r; ref_3_1<=ref_01_r; ref_3_2<=ref_02_r; ref_3_3<=ref_03_r; ref_3_4<=ref_04_r; end
0 :begin ref_3_0<=ref_01_r; ref_3_1<=ref_02_r; ref_3_2<=ref_03_r; ref_3_3<=ref_04_r; ref_3_4<=ref_05_r; end
1 :begin ref_3_0<=ref_02_r; ref_3_1<=ref_03_r; ref_3_2<=ref_04_r; ref_3_3<=ref_05_r; ref_3_4<=ref_06_r; end
2 :begin ref_3_0<=ref_03_r; ref_3_1<=ref_04_r; ref_3_2<=ref_05_r; ref_3_3<=ref_06_r; ref_3_4<=ref_07_r; end
3 :begin ref_3_0<=ref_04_r; ref_3_1<=ref_05_r; ref_3_2<=ref_06_r; ref_3_3<=ref_07_r; ref_3_4<=ref_08_r; end
4 :begin ref_3_0<=ref_05_r; ref_3_1<=ref_06_r; ref_3_2<=ref_07_r; ref_3_3<=ref_08_r; ref_3_4<=ref_09_r; end
5 :begin ref_3_0<=ref_06_r; ref_3_1<=ref_07_r; ref_3_2<=ref_08_r; ref_3_3<=ref_09_r; ref_3_4<=ref_10_r; end
6 :begin ref_3_0<=ref_07_r; ref_3_1<=ref_08_r; ref_3_2<=ref_09_r; ref_3_3<=ref_10_r; ref_3_4<=ref_11_r; end
7 :begin ref_3_0<=ref_08_r; ref_3_1<=ref_09_r; ref_3_2<=ref_10_r; ref_3_3<=ref_11_r; ref_3_4<=ref_12_r; end
8 :begin ref_3_0<=ref_09_r; ref_3_1<=ref_10_r; ref_3_2<=ref_11_r; ref_3_3<=ref_12_r; ref_3_4<=ref_13_r; end
9 :begin ref_3_0<=ref_10_r; ref_3_1<=ref_11_r; ref_3_2<=ref_12_r; ref_3_3<=ref_13_r; ref_3_4<=ref_14_r; end
10 :begin ref_3_0<=ref_11_r; ref_3_1<=ref_12_r; ref_3_2<=ref_13_r; ref_3_3<=ref_14_r; ref_3_4<=ref_15_r; end
11 :begin ref_3_0<=ref_12_r; ref_3_1<=ref_13_r; ref_3_2<=ref_14_r; ref_3_3<=ref_15_r; ref_3_4<=ref_16_r; end
12 :begin ref_3_0<=ref_13_r; ref_3_1<=ref_14_r; ref_3_2<=ref_15_r; ref_3_3<=ref_16_r; ref_3_4<=ref_17_r; end
13 :begin ref_3_0<=ref_14_r; ref_3_1<=ref_15_r; ref_3_2<=ref_16_r; ref_3_3<=ref_17_r; ref_3_4<=ref_18_r; end
14 :begin ref_3_0<=ref_15_r; ref_3_1<=ref_16_r; ref_3_2<=ref_17_r; ref_3_3<=ref_18_r; ref_3_4<=ref_19_r; end
15 :begin ref_3_0<=ref_16_r; ref_3_1<=ref_17_r; ref_3_2<=ref_18_r; ref_3_3<=ref_19_r; ref_3_4<=ref_20_r; end
16 :begin ref_3_0<=ref_17_r; ref_3_1<=ref_18_r; ref_3_2<=ref_19_r; ref_3_3<=ref_20_r; ref_3_4<=ref_21_r; end
17 :begin ref_3_0<=ref_18_r; ref_3_1<=ref_19_r; ref_3_2<=ref_20_r; ref_3_3<=ref_21_r; ref_3_4<=ref_22_r; end
18 :begin ref_3_0<=ref_19_r; ref_3_1<=ref_20_r; ref_3_2<=ref_21_r; ref_3_3<=ref_22_r; ref_3_4<=ref_23_r; end
19 :begin ref_3_0<=ref_20_r; ref_3_1<=ref_21_r; ref_3_2<=ref_22_r; ref_3_3<=ref_23_r; ref_3_4<=ref_24_r; end
20 :begin ref_3_0<=ref_21_r; ref_3_1<=ref_22_r; ref_3_2<=ref_23_r; ref_3_3<=ref_24_r; ref_3_4<=ref_25_r; end
21 :begin ref_3_0<=ref_22_r; ref_3_1<=ref_23_r; ref_3_2<=ref_24_r; ref_3_3<=ref_25_r; ref_3_4<=ref_26_r; end
22 :begin ref_3_0<=ref_23_r; ref_3_1<=ref_24_r; ref_3_2<=ref_25_r; ref_3_3<=ref_26_r; ref_3_4<=ref_27_r; end
23 :begin ref_3_0<=ref_24_r; ref_3_1<=ref_25_r; ref_3_2<=ref_26_r; ref_3_3<=ref_27_r; ref_3_4<=ref_28_r; end
24 :begin ref_3_0<=ref_25_r; ref_3_1<=ref_26_r; ref_3_2<=ref_27_r; ref_3_3<=ref_28_r; ref_3_4<=ref_29_r; end
25 :begin ref_3_0<=ref_26_r; ref_3_1<=ref_27_r; ref_3_2<=ref_28_r; ref_3_3<=ref_29_r; ref_3_4<=ref_30_r; end
26 :begin ref_3_0<=ref_27_r; ref_3_1<=ref_28_r; ref_3_2<=ref_29_r; ref_3_3<=ref_30_r; ref_3_4<=ref_31_r; end
27 :begin ref_3_0<=ref_28_r; ref_3_1<=ref_29_r; ref_3_2<=ref_30_r; ref_3_3<=ref_31_r; ref_3_4<=ref_32_r; end
28 :begin ref_3_0<=ref_29_r; ref_3_1<=ref_30_r; ref_3_2<=ref_31_r; ref_3_3<=ref_32_r; ref_3_4<=ref_33_r; end
29 :begin ref_3_0<=ref_30_r; ref_3_1<=ref_31_r; ref_3_2<=ref_32_r; ref_3_3<=ref_33_r; ref_3_4<=ref_34_r; end
30 :begin ref_3_0<=ref_31_r; ref_3_1<=ref_32_r; ref_3_2<=ref_33_r; ref_3_3<=ref_34_r; ref_3_4<=ref_35_r; end
31 :begin ref_3_0<=ref_32_r; ref_3_1<=ref_33_r; ref_3_2<=ref_34_r; ref_3_3<=ref_35_r; ref_3_4<=ref_36_r; end
32 :begin ref_3_0<=ref_33_r; ref_3_1<=ref_34_r; ref_3_2<=ref_35_r; ref_3_3<=ref_36_r; ref_3_4<=ref_37_r; end
33 :begin ref_3_0<=ref_34_r; ref_3_1<=ref_35_r; ref_3_2<=ref_36_r; ref_3_3<=ref_37_r; ref_3_4<=ref_38_r; end
34 :begin ref_3_0<=ref_35_r; ref_3_1<=ref_36_r; ref_3_2<=ref_37_r; ref_3_3<=ref_38_r; ref_3_4<=ref_39_r; end
35 :begin ref_3_0<=ref_36_r; ref_3_1<=ref_37_r; ref_3_2<=ref_38_r; ref_3_3<=ref_39_r; ref_3_4<=ref_40_r; end
36 :begin ref_3_0<=ref_37_r; ref_3_1<=ref_38_r; ref_3_2<=ref_39_r; ref_3_3<=ref_40_r; ref_3_4<=ref_41_r; end
37 :begin ref_3_0<=ref_38_r; ref_3_1<=ref_39_r; ref_3_2<=ref_40_r; ref_3_3<=ref_41_r; ref_3_4<=ref_42_r; end
38 :begin ref_3_0<=ref_39_r; ref_3_1<=ref_40_r; ref_3_2<=ref_41_r; ref_3_3<=ref_42_r; ref_3_4<=ref_43_r; end
39 :begin ref_3_0<=ref_40_r; ref_3_1<=ref_41_r; ref_3_2<=ref_42_r; ref_3_3<=ref_43_r; ref_3_4<=ref_44_r; end
40 :begin ref_3_0<=ref_41_r; ref_3_1<=ref_42_r; ref_3_2<=ref_43_r; ref_3_3<=ref_44_r; ref_3_4<=ref_45_r; end
41 :begin ref_3_0<=ref_42_r; ref_3_1<=ref_43_r; ref_3_2<=ref_44_r; ref_3_3<=ref_45_r; ref_3_4<=ref_46_r; end
42 :begin ref_3_0<=ref_43_r; ref_3_1<=ref_44_r; ref_3_2<=ref_45_r; ref_3_3<=ref_46_r; ref_3_4<=ref_47_r; end
43 :begin ref_3_0<=ref_44_r; ref_3_1<=ref_45_r; ref_3_2<=ref_46_r; ref_3_3<=ref_47_r; ref_3_4<=ref_48_r; end
44 :begin ref_3_0<=ref_45_r; ref_3_1<=ref_46_r; ref_3_2<=ref_47_r; ref_3_3<=ref_48_r; ref_3_4<=ref_49_r; end
45 :begin ref_3_0<=ref_46_r; ref_3_1<=ref_47_r; ref_3_2<=ref_48_r; ref_3_3<=ref_49_r; ref_3_4<=ref_50_r; end
46 :begin ref_3_0<=ref_47_r; ref_3_1<=ref_48_r; ref_3_2<=ref_49_r; ref_3_3<=ref_50_r; ref_3_4<=ref_51_r; end
47 :begin ref_3_0<=ref_48_r; ref_3_1<=ref_49_r; ref_3_2<=ref_50_r; ref_3_3<=ref_51_r; ref_3_4<=ref_52_r; end
48 :begin ref_3_0<=ref_49_r; ref_3_1<=ref_50_r; ref_3_2<=ref_51_r; ref_3_3<=ref_52_r; ref_3_4<=ref_53_r; end
49 :begin ref_3_0<=ref_50_r; ref_3_1<=ref_51_r; ref_3_2<=ref_52_r; ref_3_3<=ref_53_r; ref_3_4<=ref_54_r; end
50 :begin ref_3_0<=ref_51_r; ref_3_1<=ref_52_r; ref_3_2<=ref_53_r; ref_3_3<=ref_54_r; ref_3_4<=ref_55_r; end
51 :begin ref_3_0<=ref_52_r; ref_3_1<=ref_53_r; ref_3_2<=ref_54_r; ref_3_3<=ref_55_r; ref_3_4<=ref_56_r; end
52 :begin ref_3_0<=ref_53_r; ref_3_1<=ref_54_r; ref_3_2<=ref_55_r; ref_3_3<=ref_56_r; ref_3_4<=ref_57_r; end
53 :begin ref_3_0<=ref_54_r; ref_3_1<=ref_55_r; ref_3_2<=ref_56_r; ref_3_3<=ref_57_r; ref_3_4<=ref_58_r; end
54 :begin ref_3_0<=ref_55_r; ref_3_1<=ref_56_r; ref_3_2<=ref_57_r; ref_3_3<=ref_58_r; ref_3_4<=ref_59_r; end
55 :begin ref_3_0<=ref_56_r; ref_3_1<=ref_57_r; ref_3_2<=ref_58_r; ref_3_3<=ref_59_r; ref_3_4<=ref_60_r; end
56 :begin ref_3_0<=ref_57_r; ref_3_1<=ref_58_r; ref_3_2<=ref_59_r; ref_3_3<=ref_60_r; ref_3_4<=ref_61_r; end
57 :begin ref_3_0<=ref_58_r; ref_3_1<=ref_59_r; ref_3_2<=ref_60_r; ref_3_3<=ref_61_r; ref_3_4<=ref_62_r; end
58 :begin ref_3_0<=ref_59_r; ref_3_1<=ref_60_r; ref_3_2<=ref_61_r; ref_3_3<=ref_62_r; ref_3_4<=ref_63_r; end
59 :begin ref_3_0<=ref_60_r; ref_3_1<=ref_61_r; ref_3_2<=ref_62_r; ref_3_3<=ref_63_r; ref_3_4<=ref_64_r; end
60 :begin ref_3_0<=ref_61_r; ref_3_1<=ref_62_r; ref_3_2<=ref_63_r; ref_3_3<=ref_64_r; ref_3_4<=ref_64_r; end
endcase
end
end
//***********************************************************************************
//select # around the 4x4 block for Angular(filter), DC(filter) and Planar mode
// # # # #
// # * * * *
// # * * * *
// # * * * *
// # * * * *
//top
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
top0_r<='d0; top1_r<='d0;
top2_r<='d0; top3_r<='d0;
end
else begin
case(size_r0)
2'b00:begin//4x4
top0_r<=ref_t00_i; top1_r<=ref_t01_i;
top2_r<=ref_t02_i; top3_r<=ref_t03_i;
end
2'b01:begin//8x8
if(!i4x4_x_r[0]) begin
top0_r<=ref_t00_i; top1_r<=ref_t01_i;
top2_r<=ref_t02_i; top3_r<=ref_t03_i;
end
else begin
top0_r<=ref_t04_i; top1_r<=ref_t05_i;
top2_r<=ref_t06_i; top3_r<=ref_t07_i;
end
end
2'b10:begin//16x16
case(i4x4_x_r[1:0])
2'b00:begin
top0_r<=ref_t00_i; top1_r<=ref_t01_i;
top2_r<=ref_t02_i; top3_r<=ref_t03_i;
end
2'b01:begin
top0_r<=ref_t04_i; top1_r<=ref_t05_i;
top2_r<=ref_t06_i; top3_r<=ref_t07_i;
end
2'b10:begin
top0_r<=ref_t08_i; top1_r<=ref_t09_i;
top2_r<=ref_t10_i; top3_r<=ref_t11_i;
end
2'b11:begin
top0_r<=ref_t12_i; top1_r<=ref_t13_i;
top2_r<=ref_t14_i; top3_r<=ref_t15_i;
end
endcase
end
2'b11:begin//32x32
case(i4x4_x_r[2:0])
3'b000:begin
top0_r<=ref_t00_i; top1_r<=ref_t01_i;
top2_r<=ref_t02_i; top3_r<=ref_t03_i;
end
3'b001:begin
top0_r<=ref_t04_i; top1_r<=ref_t05_i;
top2_r<=ref_t06_i; top3_r<=ref_t07_i;
end
3'b010:begin
top0_r<=ref_t08_i; top1_r<=ref_t09_i;
top2_r<=ref_t10_i; top3_r<=ref_t11_i;
end
3'b011:begin
top0_r<=ref_t12_i; top1_r<=ref_t13_i;
top2_r<=ref_t14_i; top3_r<=ref_t15_i;
end
3'b100:begin
top0_r<=ref_t16_i; top1_r<=ref_t17_i;
top2_r<=ref_t18_i; top3_r<=ref_t19_i;
end
3'b101:begin
top0_r<=ref_t20_i; top1_r<=ref_t21_i;
top2_r<=ref_t22_i; top3_r<=ref_t23_i;
end
3'b110:begin
top0_r<=ref_t24_i; top1_r<=ref_t25_i;
top2_r<=ref_t26_i; top3_r<=ref_t27_i;
end
3'b111:begin
top0_r<=ref_t28_i; top1_r<=ref_t29_i;
top2_r<=ref_t30_i; top3_r<=ref_t31_i;
end
endcase
end
endcase
end
end
//left
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
left0_r<='d0; left1_r<='d0;
left2_r<='d0; left3_r<='d0;
end
else begin
case(size_r0)
2'b00:begin//4x4
left0_r<=ref_l00_i; left1_r<=ref_l01_i;
left2_r<=ref_l02_i; left3_r<=ref_l03_i;
end
2'b01:begin//8x8
if(!i4x4_y_r[0]) begin
left0_r<=ref_l00_i; left1_r<=ref_l01_i;
left2_r<=ref_l02_i; left3_r<=ref_l03_i;
end
else begin
left0_r<=ref_l04_i; left1_r<=ref_l05_i;
left2_r<=ref_l06_i; left3_r<=ref_l07_i;
end
end
2'b10:begin//16x16
case(i4x4_y_r[1:0])
2'b00:begin
left0_r<=ref_l00_i; left1_r<=ref_l01_i;
left2_r<=ref_l02_i; left3_r<=ref_l03_i;
end
2'b01:begin
left0_r<=ref_l04_i; left1_r<=ref_l05_i;
left2_r<=ref_l06_i; left3_r<=ref_l07_i;
end
2'b10:begin
left0_r<=ref_l08_i; left1_r<=ref_l09_i;
left2_r<=ref_l10_i; left3_r<=ref_l11_i;
end
2'b11:begin
left0_r<=ref_l12_i; left1_r<=ref_l13_i;
left2_r<=ref_l14_i; left3_r<=ref_l15_i;
end
endcase
end
2'b11:begin//32x32
case(i4x4_y_r[2:0])
3'b000:begin
left0_r<=ref_l00_i; left1_r<=ref_l01_i;
left2_r<=ref_l02_i; left3_r<=ref_l03_i;
end
3'b001:begin
left0_r<=ref_l04_i; left1_r<=ref_l05_i;
left2_r<=ref_l06_i; left3_r<=ref_l07_i;
end
3'b010:begin
left0_r<=ref_l08_i; left1_r<=ref_l09_i;
left2_r<=ref_l10_i; left3_r<=ref_l11_i;
end
3'b011:begin
left0_r<=ref_l12_i; left1_r<=ref_l13_i;
left2_r<=ref_l14_i; left3_r<=ref_l15_i;
end
3'b100:begin
left0_r<=ref_l16_i; left1_r<=ref_l17_i;
left2_r<=ref_l18_i; left3_r<=ref_l19_i;
end
3'b101:begin
left0_r<=ref_l20_i; left1_r<=ref_l21_i;
left2_r<=ref_l22_i; left3_r<=ref_l23_i;
end
3'b110:begin
left0_r<=ref_l24_i; left1_r<=ref_l25_i;
left2_r<=ref_l26_i; left3_r<=ref_l27_i;
end
3'b111:begin
left0_r<=ref_l28_i; left1_r<=ref_l29_i;
left2_r<=ref_l30_i; left3_r<=ref_l31_i;
end
endcase
end
endcase
end
end
//************************************************************************************
//calculate (x+1)*p[nT][-1] and (y+1)*p[-1][nT] for Planar mode
reg [`PIXEL_WIDTH+4:0] planar_x0_r,planar_x1_r,planar_x2_r,planar_x3_r;
reg [`PIXEL_WIDTH+4:0] planar_y0_r,planar_y1_r,planar_y2_r,planar_y3_r;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
planar_x0_r<='d0;planar_x1_r<='d0;planar_x2_r<='d0;planar_x3_r<='d0;
planar_y0_r<='d0;planar_y1_r<='d0;planar_y2_r<='d0;planar_y3_r<='d0;
end
else begin
planar_x0_r<=(x0_r0+1)*ref_r00_i; planar_x1_r<=(x1_r0+1)*ref_r00_i;
planar_x2_r<=(x2_r0+1)*ref_r00_i; planar_x3_r<=(x3_r0+1)*ref_r00_i;
planar_y0_r<=(y0_r0+1)*ref_d00_i; planar_y1_r<=(y1_r0+1)*ref_d00_i;
planar_y2_r<=(y2_r0+1)*ref_d00_i; planar_y3_r<=(y3_r0+1)*ref_d00_i;
end
end
//**********************************************************************************
//calculate DC value for DC mode
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
dc_value_r <= 'd0;
else begin
case(size_r0)
2'b00:dc_value_r<=(mid_t0_r+mid_l0_r+4)>>3;
2'b01:dc_value_r<=(mid_t2_r+mid_l2_r+8)>>4;
2'b10:dc_value_r<=(mid_t2_r+mid_t3_r+mid_l2_r+mid_l3_r+16)>>5;
2'b11:dc_value_r<=(mid_t2_r+mid_t3_r+mid_t4_r+mid_t5_r+
mid_l2_r+mid_l3_r+mid_l4_r+mid_l5_r+32)>>6;
endcase
end
end
//stage2
//***********************************************************************************
//predict process
//Angular
always @( * ) begin
if(ifact0) begin
pre_0_0_w = ( (32-ifact0)*ref_0_0 + ifact0*ref_0_1 + 16 ) >>5;
pre_0_1_w = ( (32-ifact0)*ref_0_1 + ifact0*ref_0_2 + 16 ) >>5;
pre_0_2_w = ( (32-ifact0)*ref_0_2 + ifact0*ref_0_3 + 16 ) >>5;
pre_0_3_w = ( (32-ifact0)*ref_0_3 + ifact0*ref_0_4 + 16 ) >>5;
end
else begin
pre_0_0_w = ref_0_0 ;
pre_0_1_w = ref_0_1 ;
pre_0_2_w = ref_0_2 ;
pre_0_3_w = ref_0_3 ;
end
end
always @( * ) begin
if(ifact0) begin
pre_1_0_w = ( (32-ifact1)*ref_1_0 + ifact1*ref_1_1 + 16 ) >>5;
pre_1_1_w = ( (32-ifact1)*ref_1_1 + ifact1*ref_1_2 + 16 ) >>5;
pre_1_2_w = ( (32-ifact1)*ref_1_2 + ifact1*ref_1_3 + 16 ) >>5;
pre_1_3_w = ( (32-ifact1)*ref_1_3 + ifact1*ref_1_4 + 16 ) >>5;
end
else begin
pre_1_0_w = ref_1_0 ;
pre_1_1_w = ref_1_1 ;
pre_1_2_w = ref_1_2 ;
pre_1_3_w = ref_1_3 ;
end
end
always @( * ) begin
if(ifact0) begin
pre_2_0_w = ( (32-ifact2)*ref_2_0 + ifact2*ref_2_1 + 16 ) >>5;
pre_2_1_w = ( (32-ifact2)*ref_2_1 + ifact2*ref_2_2 + 16 ) >>5;
pre_2_2_w = ( (32-ifact2)*ref_2_2 + ifact2*ref_2_3 + 16 ) >>5;
pre_2_3_w = ( (32-ifact2)*ref_2_3 + ifact2*ref_2_4 + 16 ) >>5;
end
else begin
pre_2_0_w = ref_2_0 ;
pre_2_1_w = ref_2_1 ;
pre_2_2_w = ref_2_2 ;
pre_2_3_w = ref_2_3 ;
end
end
always @( * ) begin
if(ifact0) begin
pre_3_0_w = ( (32-ifact3)*ref_3_0 + ifact3*ref_3_1 + 16 ) >>5;
pre_3_1_w = ( (32-ifact3)*ref_3_1 + ifact3*ref_3_2 + 16 ) >>5;
pre_3_2_w = ( (32-ifact3)*ref_3_2 + ifact3*ref_3_3 + 16 ) >>5;
pre_3_3_w = ( (32-ifact3)*ref_3_3 + ifact3*ref_3_4 + 16 ) >>5;
end
else begin
pre_3_0_w = ref_3_0 ;
pre_3_1_w = ref_3_1 ;
pre_3_2_w = ref_3_2 ;
pre_3_3_w = ref_3_3 ;
end
end
//Planar
reg [`PIXEL_WIDTH-1:0] planar_00_w,planar_01_w,planar_02_w,planar_03_w;
reg [`PIXEL_WIDTH-1:0] planar_10_w,planar_11_w,planar_12_w,planar_13_w;
reg [`PIXEL_WIDTH-1:0] planar_20_w,planar_21_w,planar_22_w,planar_23_w;
reg [`PIXEL_WIDTH-1:0] planar_30_w,planar_31_w,planar_32_w,planar_33_w;
always @( * ) begin
case(size_r1)
2'b00:begin
planar_00_w=(3*left0_r+3*top0_r+planar_x0_r+planar_y0_r+4)>>3;
planar_01_w=(2*left0_r+3*top1_r+planar_x1_r+planar_y0_r+4)>>3;
planar_02_w=(1*left0_r+3*top2_r+planar_x2_r+planar_y0_r+4)>>3;
planar_03_w=(0*left0_r+3*top3_r+planar_x3_r+planar_y0_r+4)>>3;
planar_10_w=(3*left1_r+2*top0_r+planar_x0_r+planar_y1_r+4)>>3;
planar_11_w=(2*left1_r+2*top1_r+planar_x1_r+planar_y1_r+4)>>3;
planar_12_w=(1*left1_r+2*top2_r+planar_x2_r+planar_y1_r+4)>>3;
planar_13_w=(0*left1_r+2*top3_r+planar_x3_r+planar_y1_r+4)>>3;
planar_20_w=(3*left2_r+1*top0_r+planar_x0_r+planar_y2_r+4)>>3;
planar_21_w=(2*left2_r+1*top1_r+planar_x1_r+planar_y2_r+4)>>3;
planar_22_w=(1*left2_r+1*top2_r+planar_x2_r+planar_y2_r+4)>>3;
planar_23_w=(0*left2_r+1*top3_r+planar_x3_r+planar_y2_r+4)>>3;
planar_30_w=(3*left3_r+0*top0_r+planar_x0_r+planar_y3_r+4)>>3;
planar_31_w=(2*left3_r+0*top1_r+planar_x1_r+planar_y3_r+4)>>3;
planar_32_w=(1*left3_r+0*top2_r+planar_x2_r+planar_y3_r+4)>>3;
planar_33_w=(0*left3_r+0*top3_r+planar_x3_r+planar_y3_r+4)>>3;
end
2'b01:begin
planar_00_w=((7-x0_r1)*left0_r+(7-y0_r1)*top0_r+planar_x0_r+planar_y0_r+8)>>4;
planar_01_w=((7-x1_r1)*left0_r+(7-y0_r1)*top1_r+planar_x1_r+planar_y0_r+8)>>4;
planar_02_w=((7-x2_r1)*left0_r+(7-y0_r1)*top2_r+planar_x2_r+planar_y0_r+8)>>4;
planar_03_w=((7-x3_r1)*left0_r+(7-y0_r1)*top3_r+planar_x3_r+planar_y0_r+8)>>4;
planar_10_w=((7-x0_r1)*left1_r+(7-y1_r1)*top0_r+planar_x0_r+planar_y1_r+8)>>4;
planar_11_w=((7-x1_r1)*left1_r+(7-y1_r1)*top1_r+planar_x1_r+planar_y1_r+8)>>4;
planar_12_w=((7-x2_r1)*left1_r+(7-y1_r1)*top2_r+planar_x2_r+planar_y1_r+8)>>4;
planar_13_w=((7-x3_r1)*left1_r+(7-y1_r1)*top3_r+planar_x3_r+planar_y1_r+8)>>4;
planar_20_w=((7-x0_r1)*left2_r+(7-y2_r1)*top0_r+planar_x0_r+planar_y2_r+8)>>4;
planar_21_w=((7-x1_r1)*left2_r+(7-y2_r1)*top1_r+planar_x1_r+planar_y2_r+8)>>4;
planar_22_w=((7-x2_r1)*left2_r+(7-y2_r1)*top2_r+planar_x2_r+planar_y2_r+8)>>4;
planar_23_w=((7-x3_r1)*left2_r+(7-y2_r1)*top3_r+planar_x3_r+planar_y2_r+8)>>4;
planar_30_w=((7-x0_r1)*left3_r+(7-y3_r1)*top0_r+planar_x0_r+planar_y3_r+8)>>4;
planar_31_w=((7-x1_r1)*left3_r+(7-y3_r1)*top1_r+planar_x1_r+planar_y3_r+8)>>4;
planar_32_w=((7-x2_r1)*left3_r+(7-y3_r1)*top2_r+planar_x2_r+planar_y3_r+8)>>4;
planar_33_w=((7-x3_r1)*left3_r+(7-y3_r1)*top3_r+planar_x3_r+planar_y3_r+8)>>4;
end
2'b10:begin
planar_00_w=((15-x0_r1)*left0_r+(15-y0_r1)*top0_r+planar_x0_r+planar_y0_r+16)>>5;
planar_01_w=((15-x1_r1)*left0_r+(15-y0_r1)*top1_r+planar_x1_r+planar_y0_r+16)>>5;
planar_02_w=((15-x2_r1)*left0_r+(15-y0_r1)*top2_r+planar_x2_r+planar_y0_r+16)>>5;
planar_03_w=((15-x3_r1)*left0_r+(15-y0_r1)*top3_r+planar_x3_r+planar_y0_r+16)>>5;
planar_10_w=((15-x0_r1)*left1_r+(15-y1_r1)*top0_r+planar_x0_r+planar_y1_r+16)>>5;
planar_11_w=((15-x1_r1)*left1_r+(15-y1_r1)*top1_r+planar_x1_r+planar_y1_r+16)>>5;
planar_12_w=((15-x2_r1)*left1_r+(15-y1_r1)*top2_r+planar_x2_r+planar_y1_r+16)>>5;
planar_13_w=((15-x3_r1)*left1_r+(15-y1_r1)*top3_r+planar_x3_r+planar_y1_r+16)>>5;
planar_20_w=((15-x0_r1)*left2_r+(15-y2_r1)*top0_r+planar_x0_r+planar_y2_r+16)>>5;
planar_21_w=((15-x1_r1)*left2_r+(15-y2_r1)*top1_r+planar_x1_r+planar_y2_r+16)>>5;
planar_22_w=((15-x2_r1)*left2_r+(15-y2_r1)*top2_r+planar_x2_r+planar_y2_r+16)>>5;
planar_23_w=((15-x3_r1)*left2_r+(15-y2_r1)*top3_r+planar_x3_r+planar_y2_r+16)>>5;
planar_30_w=((15-x0_r1)*left3_r+(15-y3_r1)*top0_r+planar_x0_r+planar_y3_r+16)>>5;
planar_31_w=((15-x1_r1)*left3_r+(15-y3_r1)*top1_r+planar_x1_r+planar_y3_r+16)>>5;
planar_32_w=((15-x2_r1)*left3_r+(15-y3_r1)*top2_r+planar_x2_r+planar_y3_r+16)>>5;
planar_33_w=((15-x3_r1)*left3_r+(15-y3_r1)*top3_r+planar_x3_r+planar_y3_r+16)>>5;
end
2'b11:begin
planar_00_w=((31-x0_r1)*left0_r+(31-y0_r1)*top0_r+planar_x0_r+planar_y0_r+32)>>6;
planar_01_w=((31-x1_r1)*left0_r+(31-y0_r1)*top1_r+planar_x1_r+planar_y0_r+32)>>6;
planar_02_w=((31-x2_r1)*left0_r+(31-y0_r1)*top2_r+planar_x2_r+planar_y0_r+32)>>6;
planar_03_w=((31-x3_r1)*left0_r+(31-y0_r1)*top3_r+planar_x3_r+planar_y0_r+32)>>6;
planar_10_w=((31-x0_r1)*left1_r+(31-y1_r1)*top0_r+planar_x0_r+planar_y1_r+32)>>6;
planar_11_w=((31-x1_r1)*left1_r+(31-y1_r1)*top1_r+planar_x1_r+planar_y1_r+32)>>6;
planar_12_w=((31-x2_r1)*left1_r+(31-y1_r1)*top2_r+planar_x2_r+planar_y1_r+32)>>6;
planar_13_w=((31-x3_r1)*left1_r+(31-y1_r1)*top3_r+planar_x3_r+planar_y1_r+32)>>6;
planar_20_w=((31-x0_r1)*left2_r+(31-y2_r1)*top0_r+planar_x0_r+planar_y2_r+32)>>6;
planar_21_w=((31-x1_r1)*left2_r+(31-y2_r1)*top1_r+planar_x1_r+planar_y2_r+32)>>6;
planar_22_w=((31-x2_r1)*left2_r+(31-y2_r1)*top2_r+planar_x2_r+planar_y2_r+32)>>6;
planar_23_w=((31-x3_r1)*left2_r+(31-y2_r1)*top3_r+planar_x3_r+planar_y2_r+32)>>6;
planar_30_w=((31-x0_r1)*left3_r+(31-y3_r1)*top0_r+planar_x0_r+planar_y3_r+32)>>6;
planar_31_w=((31-x1_r1)*left3_r+(31-y3_r1)*top1_r+planar_x1_r+planar_y3_r+32)>>6;
planar_32_w=((31-x2_r1)*left3_r+(31-y3_r1)*top2_r+planar_x2_r+planar_y3_r+32)>>6;
planar_33_w=((31-x3_r1)*left3_r+(31-y3_r1)*top3_r+planar_x3_r+planar_y3_r+32)>>6;
end
endcase
end
//DC
reg [`PIXEL_WIDTH-1:0] DC_00_w,DC_01_w,DC_02_w,DC_03_w;
reg [`PIXEL_WIDTH-1:0] DC_10_w;
reg [`PIXEL_WIDTH-1:0] DC_20_w;
reg [`PIXEL_WIDTH-1:0] DC_30_w;
always @( * ) begin
if(pre_sel_i==2'b00) begin
if(!x0_r1 && !y0_r1 && size_r1!=2'b11)
DC_00_w = (top0_r+left0_r+(dc_value_r<<1)+2)>>2;
else if(!x0_r1 && size_r1!=2'b11)
DC_00_w = (left0_r+(dc_value_r*3)+2)>>2;
else if(!y0_r1 && size_r1!=2'b11)
DC_00_w = (top0_r +(dc_value_r*3)+2)>>2;
else begin
DC_00_w = dc_value_r;
end
end
else begin
DC_00_w = dc_value_r;
end
end
always @( * ) begin
if(!x0_r1 && size_r1!=2'b11 && (pre_sel_i==2'b00) ) begin
DC_10_w = (left1_r+(dc_value_r*3)+2)>>2;
DC_20_w = (left2_r+(dc_value_r*3)+2)>>2;
DC_30_w = (left3_r+(dc_value_r*3)+2)>>2;
end
else begin
DC_10_w = dc_value_r;
DC_20_w = dc_value_r;
DC_30_w = dc_value_r;
end
end
always @( * ) begin
if(!y0_r1 && size_r1!=2'b11 && (pre_sel_i==2'b00) ) begin
DC_01_w = (top1_r+(dc_value_r*3)+2)>>2;
DC_02_w = (top2_r+(dc_value_r*3)+2)>>2;
DC_03_w = (top3_r+(dc_value_r*3)+2)>>2;
end
else begin
DC_01_w = dc_value_r;
DC_02_w = dc_value_r;
DC_03_w = dc_value_r;
end
end
//Angular26 and Angular10 filter
wire signed [`PIXEL_WIDTH:0] top0_w, top1_w, top2_w, top3_w;
wire signed [`PIXEL_WIDTH:0] left0_w,left1_w,left2_w,left3_w;
wire signed [`PIXEL_WIDTH:0] ref_tl;
assign top0_w={1'b0,top0_r}; assign left0_w={1'b0,left0_r};
assign top1_w={1'b0,top1_r}; assign left1_w={1'b0,left1_r};
assign top2_w={1'b0,top2_r}; assign left2_w={1'b0,left2_r};
assign top3_w={1'b0,top3_r}; assign left3_w={1'b0,left3_r};
assign ref_tl={1'b0,ref_tl_i};
wire signed [`PIXEL_WIDTH+1:0] ver_0_w, ver_1_w, ver_2_w, ver_3_w;
wire signed [`PIXEL_WIDTH+1:0] hor_0_w, hor_1_w, hor_2_w, hor_3_w;
reg [`PIXEL_WIDTH-1:0] ver_00_w,ver_10_w,ver_20_w,ver_30_w;
reg [`PIXEL_WIDTH-1:0] hor_00_w,hor_01_w,hor_02_w,hor_03_w;
assign ver_0_w=top0_w+((left0_w-ref_tl)>>>1);
assign ver_1_w=top0_w+((left1_w-ref_tl)>>>1);
assign ver_2_w=top0_w+((left2_w-ref_tl)>>>1);
assign ver_3_w=top0_w+((left3_w-ref_tl)>>>1);
assign hor_0_w=left0_w+((top0_w-ref_tl)>>>1);
assign hor_1_w=left0_w+((top1_w-ref_tl)>>>1);
assign hor_2_w=left0_w+((top2_w-ref_tl)>>>1);
assign hor_3_w=left0_w+((top3_w-ref_tl)>>>1);
//Angular26
always @( * ) begin
if(!x0_r1 && size_r1!=2'b11 && (pre_sel_i==2'b00) ) begin
ver_00_w=(ver_0_w[9] ? 'd0 : ( ver_0_w[8] ? 'd255 : ver_0_w[7:0] ));
ver_10_w=(ver_1_w[9] ? 'd0 : ( ver_1_w[8] ? 'd255 : ver_1_w[7:0] ));
ver_20_w=(ver_2_w[9] ? 'd0 : ( ver_2_w[8] ? 'd255 : ver_2_w[7:0] ));
ver_30_w=(ver_3_w[9] ? 'd0 : ( ver_3_w[8] ? 'd255 : ver_3_w[7:0] ));
end
else begin
ver_00_w=top0_r;
ver_10_w=top0_r;
ver_20_w=top0_r;
ver_30_w=top0_r;
end
end
//Angular10
always @( * ) begin
if(!y0_r1 && size_r1!=2'b11 && (pre_sel_i==2'b00) ) begin
hor_00_w=(hor_0_w[9] ? 'd0 : ( hor_0_w[8] ? 'd255 : hor_0_w[7:0] ));
hor_01_w=(hor_1_w[9] ? 'd0 : ( hor_1_w[8] ? 'd255 : hor_1_w[7:0] ));
hor_02_w=(hor_2_w[9] ? 'd0 : ( hor_2_w[8] ? 'd255 : hor_2_w[7:0] ));
hor_03_w=(hor_3_w[9] ? 'd0 : ( hor_3_w[8] ? 'd255 : hor_3_w[7:0] ));
end
else begin
hor_00_w=left0_r;
hor_01_w=left0_r;
hor_02_w=left0_r;
hor_03_w=left0_r;
end
end
//***************************************************************************
//output
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
pred_00_o<='d0; pred_01_o<='d0; pred_02_o<='d0; pred_03_o<='d0;
pred_10_o<='d0; pred_11_o<='d0; pred_12_o<='d0; pred_13_o<='d0;
pred_20_o<='d0; pred_21_o<='d0; pred_22_o<='d0; pred_23_o<='d0;
pred_30_o<='d0; pred_31_o<='d0; pred_32_o<='d0; pred_33_o<='d0;
end
else begin
case(mode_r1)
'd0:begin
pred_00_o<=planar_00_w; pred_01_o<=planar_01_w; pred_02_o<=planar_02_w; pred_03_o<=planar_03_w;
pred_10_o<=planar_10_w; pred_11_o<=planar_11_w; pred_12_o<=planar_12_w; pred_13_o<=planar_13_w;
pred_20_o<=planar_20_w; pred_21_o<=planar_21_w; pred_22_o<=planar_22_w; pred_23_o<=planar_23_w;
pred_30_o<=planar_30_w; pred_31_o<=planar_31_w; pred_32_o<=planar_32_w; pred_33_o<=planar_33_w;
end
'd1:begin
pred_00_o<=DC_00_w; pred_01_o<=DC_01_w; pred_02_o<=DC_02_w; pred_03_o<=DC_03_w;
pred_10_o<=DC_10_w; pred_11_o<=dc_value_r; pred_12_o<=dc_value_r; pred_13_o<=dc_value_r;
pred_20_o<=DC_20_w; pred_21_o<=dc_value_r; pred_22_o<=dc_value_r; pred_23_o<=dc_value_r;
pred_30_o<=DC_30_w; pred_31_o<=dc_value_r; pred_32_o<=dc_value_r; pred_33_o<=dc_value_r;
end
'd10:begin
pred_00_o<=hor_00_w; pred_01_o<=hor_01_w; pred_02_o<=hor_02_w; pred_03_o<=hor_03_w;
pred_10_o<=left1_r; pred_11_o<=left1_r; pred_12_o<=left1_r; pred_13_o<=left1_r;
pred_20_o<=left2_r; pred_21_o<=left2_r; pred_22_o<=left2_r; pred_23_o<=left2_r;
pred_30_o<=left3_r; pred_31_o<=left3_r; pred_32_o<=left3_r; pred_33_o<=left3_r;
end
'd26:begin
pred_00_o<=ver_00_w; pred_01_o<=top1_r; pred_02_o<=top2_r; pred_03_o<=top3_r;
pred_10_o<=ver_10_w; pred_11_o<=top1_r; pred_12_o<=top2_r; pred_13_o<=top3_r;
pred_20_o<=ver_20_w; pred_21_o<=top1_r; pred_22_o<=top2_r; pred_23_o<=top3_r;
pred_30_o<=ver_30_w; pred_31_o<=top1_r; pred_32_o<=top2_r; pred_33_o<=top3_r;
end
default:begin
if(mode_r1>=18)begin
pred_00_o<=pre_0_0_w; pred_01_o<=pre_0_1_w; pred_02_o<=pre_0_2_w; pred_03_o<=pre_0_3_w;
pred_10_o<=pre_1_0_w; pred_11_o<=pre_1_1_w; pred_12_o<=pre_1_2_w; pred_13_o<=pre_1_3_w;
pred_20_o<=pre_2_0_w; pred_21_o<=pre_2_1_w; pred_22_o<=pre_2_2_w; pred_23_o<=pre_2_3_w;
pred_30_o<=pre_3_0_w; pred_31_o<=pre_3_1_w; pred_32_o<=pre_3_2_w; pred_33_o<=pre_3_3_w;
end
else begin
pred_00_o<=pre_0_0_w; pred_01_o<=pre_1_0_w; pred_02_o<=pre_2_0_w; pred_03_o<=pre_3_0_w;
pred_10_o<=pre_0_1_w; pred_11_o<=pre_1_1_w; pred_12_o<=pre_2_1_w; pred_13_o<=pre_3_1_w;
pred_20_o<=pre_0_2_w; pred_21_o<=pre_1_2_w; pred_22_o<=pre_2_2_w; pred_23_o<=pre_3_2_w;
pred_30_o<=pre_0_3_w; pred_31_o<=pre_1_3_w; pred_32_o<=pre_2_3_w; pred_33_o<=pre_3_3_w;
end
end
endcase
end
end
//***********************************************************************************
//buffering mode/size/x0/y0
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
mode_r0<='d0; size_r0<='d0; start_r0<='d0;
mode_r1<='d0; size_r1<='d0; start_r1<='d0;
x0_r0<='d0; x0_r1<='d0;
y0_r0<='d0; y0_r1<='d0;
x1_r0<='d0; x1_r1<='d0;
y1_r0<='d0; y1_r1<='d0;
x2_r0<='d0; x2_r1<='d0;
y2_r0<='d0; y2_r1<='d0;
x3_r0<='d0; x3_r1<='d0;
y3_r0<='d0; y3_r1<='d0;
i4x4_x_r<='d0;i4x4_y_r<='d0;
i4x4_x_r1<='d0;i4x4_y_r1<='d0;
i4x4_x_o<='d0;i4x4_y_o<='d0;
size_o <= 'd0;
done_o <= 'd0;
end
else begin
mode_r0 <= mode_i; size_r0 <= size_i; start_r0 <= start_i;
mode_r1 <= mode_r0; size_r1 <= size_r0;start_r1 <= start_r0;
x0_r0<=x0; x0_r1<=x0_r0;
y0_r0<=y0; y0_r1<=y0_r0;
x1_r0<=x1; x1_r1<=x1_r0;
y1_r0<=y1; y1_r1<=y1_r0;
x2_r0<=x2; x2_r1<=x2_r0;
y2_r0<=y2; y2_r1<=y2_r0;
x3_r0<=x3; x3_r1<=x3_r0;
y3_r0<=y3; y3_r1<=y3_r0;
i4x4_x_r<=i4x4_x_i;
i4x4_y_r<=i4x4_y_i;
i4x4_x_r1<=i4x4_x_r;
i4x4_y_r1<=i4x4_y_r;
i4x4_x_o<=i4x4_x_r1;
i4x4_y_o<=i4x4_y_r1;
size_o <= size_r1;
done_o <= start_r1;
end
end
endmodule |
/*
reset...init...save.start_write.stop_write.restore.start_read(compare).stop_read.loop
error...
*/
module mem_tester(
clk,
rst_n,
led, // LED flashing or not
// SRAM signals
SRAM_DQ, // sram inout databus
SRAM_ADDR, // sram address bus
SRAM_UB_N,
SRAM_LB_N,
SRAM_WE_N, //
SRAM_CE_N, //
SRAM_OE_N //
);
parameter SRAM_DATA_SIZE = 8;
parameter SRAM_ADDR_SIZE = 19;
inout [SRAM_DATA_SIZE-1:0] SRAM_DQ;
wire [SRAM_DATA_SIZE-1:0] SRAM_DQ;
output [SRAM_ADDR_SIZE-1:0] SRAM_ADDR;
wire [SRAM_ADDR_SIZE-1:0] SRAM_ADDR;
output SRAM_UB_N,SRAM_LB_N,SRAM_WE_N,SRAM_CE_N,SRAM_OE_N;
wire SRAM_UB_N,SRAM_LB_N,SRAM_WE_N,SRAM_CE_N,SRAM_OE_N;
input clk;
input rst_n;
output led; reg led;
reg inc_pass_ctr; // increment passes counter (0000-9999 BCD)
reg inc_err_ctr; // increment errors counter (10 red binary LEDs)
reg check_in_progress; // when 1 - enables errors checking
reg [19:0] ledflash;
always @(posedge clk)
begin
if( inc_pass_ctr )
ledflash <= 20'd0;
else if( !ledflash[19] )
ledflash <= ledflash + 20'd1;
end
always @(posedge clk)
begin
led <= ledflash[19] ^ was_error;
end
reg was_error;
always @(posedge clk, negedge rst_n)
begin
if( !rst_n )
was_error <= 1'b0;
else if( inc_err_ctr )
was_error <= 1'b1;
end
reg rnd_init,rnd_save,rnd_restore; // rnd_vec_gen control
wire [SRAM_DATA_SIZE-1:0] rnd_out; // rnd_vec_gen output
rnd_vec_gen my_rnd( .clk(clk), .init(rnd_init), .next(sram_ready), .save(rnd_save), .restore(rnd_restore), .out(rnd_out) );
defparam my_rnd.OUT_SIZE = SRAM_DATA_SIZE;
defparam my_rnd.LFSR_LENGTH = 41;
defparam my_rnd.LFSR_FEEDBACK = 3;
reg sram_start,sram_rnw;
wire sram_stop,sram_ready;
wire [SRAM_DATA_SIZE-1:0] sram_rdat;
sram_control my_sram( .clk(clk), .clk2(clk), .start(sram_start), .rnw(sram_rnw), .stop(sram_stop), .ready(sram_ready),
.rdat(sram_rdat), .wdat(rnd_out),
.SRAM_DQ(SRAM_DQ), .SRAM_ADDR(SRAM_ADDR),
.SRAM_CE_N(SRAM_CE_N), .SRAM_OE_N(SRAM_OE_N), .SRAM_WE_N(SRAM_WE_N) );
defparam my_sram.SRAM_DATA_SIZE = SRAM_DATA_SIZE;
defparam my_sram.SRAM_ADDR_SIZE = SRAM_ADDR_SIZE;
// FSM states and registers
reg [3:0] curr_state,next_state;
parameter RESET = 4'h0;
parameter INIT1 = 4'h1;
parameter INIT2 = 4'h2;
parameter BEGIN_WRITE1 = 4'h3;
parameter BEGIN_WRITE2 = 4'h4;
parameter BEGIN_WRITE3 = 4'h5;
parameter BEGIN_WRITE4 = 4'h6;
parameter WRITE = 4'h7;
parameter BEGIN_READ1 = 4'h8;
parameter BEGIN_READ2 = 4'h9;
parameter BEGIN_READ3 = 4'hA;
parameter BEGIN_READ4 = 4'hB;
parameter READ = 4'hC;
parameter END_READ = 4'hD;
parameter INC_PASSES1 = 4'hE;
parameter INC_PASSES2 = 4'hF;
// FSM dispatcher
always @*
begin
case( curr_state )
RESET:
next_state <= INIT1;
INIT1:
if( sram_stop )
next_state <= INIT2;
else
next_state <= INIT1;
INIT2:
next_state <= BEGIN_WRITE1;
BEGIN_WRITE1:
next_state <= BEGIN_WRITE2;
BEGIN_WRITE2:
next_state <= BEGIN_WRITE3;
BEGIN_WRITE3:
next_state <= BEGIN_WRITE4;
BEGIN_WRITE4:
next_state <= WRITE;
WRITE:
if( sram_stop )
next_state <= BEGIN_READ1;
else
next_state <= WRITE;
BEGIN_READ1:
next_state <= BEGIN_READ2;
BEGIN_READ2:
next_state <= BEGIN_READ3;
BEGIN_READ3:
next_state <= BEGIN_READ4;
BEGIN_READ4:
next_state <= READ;
READ:
if( sram_stop )
next_state <= END_READ;
else
next_state <= READ;
END_READ:
next_state <= INC_PASSES1;
INC_PASSES1:
next_state <= INC_PASSES2;
INC_PASSES2:
next_state <= BEGIN_WRITE1;
default:
next_state <= RESET;
endcase
end
// FSM sequencer
always @(posedge clk,negedge rst_n)
begin
if( !rst_n )
curr_state <= RESET;
else
curr_state <= next_state;
end
// FSM controller
always @(posedge clk)
begin
case( curr_state )
//////////////////////////////////////////////////
RESET:
begin
// various initializings begin
inc_pass_ctr <= 1'b0;
check_in_progress <= 1'b0;
rnd_init <= 1'b1; //begin RND init
rnd_save <= 1'b0;
rnd_restore <= 1'b0;
sram_start <= 1'b1;
sram_rnw <= 1'b1; // start condition for sram controller, in read mode
end
INIT1:
begin
sram_start <= 1'b0; // end sram start
end
INIT2:
begin
rnd_init <= 1'b0; // end rnd init
end
//////////////////////////////////////////////////
BEGIN_WRITE1:
begin
rnd_save <= 1'b1;
sram_rnw <= 1'b0;
end
BEGIN_WRITE2:
begin
rnd_save <= 1'b0;
sram_start <= 1'b1;
end
BEGIN_WRITE3:
begin
sram_start <= 1'b0;
end
/* BEGIN_WRITE4:
begin
rnd_save <= 1'b0;
sram_start <= 1'b1;
end
WRITE:
begin
sram_start <= 1'b0;
end
*/
//////////////////////////////////////////////////
BEGIN_READ1:
begin
rnd_restore <= 1'b1;
sram_rnw <= 1'b1;
end
BEGIN_READ2:
begin
rnd_restore <= 1'b0;
sram_start <= 1'b1;
end
BEGIN_READ3:
begin
sram_start <= 1'b0;
check_in_progress <= 1'b1;
end
/* BEGIN_READ4:
begin
rnd_restore <= 1'b0;
sram_start <= 1'b1;
end
READ:
begin
sram_start <= 1'b0;
check_in_progress <= 1'b1;
end
*/
END_READ:
begin
check_in_progress <= 1'b0;
end
INC_PASSES1:
begin
inc_pass_ctr <= 1'b1;
end
INC_PASSES2:
begin
inc_pass_ctr <= 1'b0;
end
endcase
end
// errors counter
always @(posedge clk)
inc_err_ctr <= check_in_progress & sram_ready & ((sram_rdat==rnd_out)?0:1);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_FUNCTIONAL_V
/**
* lsbuflv2hv_symmetric: Level shifting buffer, Low Voltage to High
* Voltage, Symmetrical.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_symmetric (
X,
A
);
// Module ports
output X;
input A;
// Name Output Other arguments
buf buf0 (X , A );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4B_BLACKBOX_V
`define SKY130_FD_SC_LP__OR4B_BLACKBOX_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__or4b (
X ,
A ,
B ,
C ,
D_N
);
output X ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4B_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND4_BEHAVIORAL_V
`define SKY130_FD_SC_LP__AND4_BEHAVIORAL_V
/**
* and4: 4-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__and4 (
X,
A,
B,
C,
D
);
// Module ports
output X;
input A;
input B;
input C;
input D;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, B, C, D );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND4_BEHAVIORAL_V |
//--------------------------------------------------------------------------------
// controller.vhd
//
// Copyright (C) 2006 Michael Poppitz
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details: http://www.sump.org/projects/analyzer/
//
// Controls the capturing & readback operation.
//
// If no other operation has been activated, the controller samples data
// into the memory. When the run signal is received, it continues to do so
// for fwd * 4 samples and then sends bwd * 4 samples to the transmitter.
// This allows to capture data from before the trigger match which is a nice
// feature.
//
//--------------------------------------------------------------------------------
//
// 12/29/2010 - Verilog Version + cleanups created by Ian Davis - mygizmos.org
//
`timescale 1ns/100ps
module controller(
clock, reset, run,
wrSize, config_data,
validIn, dataIn, busy, arm,
// outputs...
send, memoryWrData, memoryRead,
memoryWrite, memoryLastWrite);
input clock;
input reset;
input run;
input wrSize;
input [31:0] config_data;
input validIn;
input [31:0] dataIn;
input busy;
input arm;
output send;
output [31:0] memoryWrData;
output memoryRead;
output memoryWrite;
output memoryLastWrite;
reg [15:0] fwd, next_fwd; // Config registers...
reg [15:0] bwd, next_bwd;
reg send, next_send;
reg memoryRead, next_memoryRead;
reg memoryWrite, next_memoryWrite;
reg memoryLastWrite, next_memoryLastWrite;
reg [17:0] counter, next_counter;
wire [17:0] counter_inc = counter+1'b1;
reg [31:0] memoryWrData, next_memoryWrData;
always @(posedge clock)
begin
memoryWrData = next_memoryWrData;
end
always @*
begin
#1; next_memoryWrData = dataIn;
end
//
// Control FSM...
//
parameter [2:0]
IDLE = 3'h0,
SAMPLE = 3'h1,
DELAY = 3'h2,
READ = 3'h3,
READWAIT = 3'h4;
reg [2:0] state, next_state;
initial state = IDLE;
always @(posedge clock or posedge reset)
begin
if (reset)
begin
state = IDLE;
memoryWrite = 1'b0;
memoryLastWrite = 1'b0;
memoryRead = 1'b0;
end
else
begin
state = next_state;
memoryWrite = next_memoryWrite;
memoryLastWrite = next_memoryLastWrite;
memoryRead = next_memoryRead;
end
end
always @(posedge clock)
begin
counter = next_counter;
send = next_send;
end
// FSM to control the controller action
always @*
begin
#1;
next_state = state;
next_counter = counter;
next_memoryWrite = 1'b0;
next_memoryLastWrite = 1'b0;
next_memoryRead = 1'b0;
next_send = 1'b0;
case(state)
IDLE :
begin
next_counter = 0;
next_memoryWrite = 1;
if (run) next_state = DELAY;
else if (arm) next_state = SAMPLE;
end
// default mode: write data samples to memory
SAMPLE :
begin
next_counter = 0;
next_memoryWrite = validIn;
if (run) next_state = DELAY;
end
// keep sampling for 4 * fwd + 4 samples after run condition
DELAY :
begin
if (validIn)
begin
next_memoryWrite = 1'b1;
next_counter = counter_inc;
if (counter == {fwd,2'b11}) // IED - Evaluate only on validIn to make behavior
begin // match between sampling on all-clocks verses occasionally.
next_memoryLastWrite = 1'b1; // Added LastWrite flag to simplify write->read memory handling.
next_counter = 0;
next_state = READ;
end
end
end
// read back 4 * bwd + 4 samples after DELAY
// go into wait state after each sample to give transmitter time
READ :
begin
next_memoryRead = 1'b1;
next_send = 1'b1;
if (counter == {bwd,2'b11})
begin
next_counter = 0;
next_state = IDLE;
end
else
begin
next_counter = counter_inc;
next_state = READWAIT;
end
end
// wait for the transmitter to become ready again
READWAIT :
begin
if (!busy && !send) next_state = READ;
end
endcase
end
//
// Set speed and size registers if indicated...
//
always @(posedge clock)
begin
fwd = next_fwd;
bwd = next_bwd;
end
always @*
begin
#1;
next_fwd = fwd;
next_bwd = bwd;
if (wrSize)
begin
next_fwd = config_data[31:16];
next_bwd = config_data[15:0];
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jan 22 23:54:06 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top design_1_axi_gpio_1_0 -prefix
// design_1_axi_gpio_1_0_ design_1_axi_gpio_1_0_stub.v
// Design : design_1_axi_gpio_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_gpio,Vivado 2016.4" *)
module design_1_axi_gpio_1_0(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_i, gpio_io_o, gpio_io_t)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[3:0],gpio_io_o[3:0],gpio_io_t[3:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
input [3:0]gpio_io_i;
output [3:0]gpio_io_o;
output [3:0]gpio_io_t;
endmodule
|
`define bsg_buf_macro(bits) \
if (harden_p && (width_p==bits) && vertical_p) \
begin: macro \
bsg_rp_tsmc_40_BUFFD8BWP_b``bits buf_gate (.i0(i),.o); \
end \
else \
if (harden_p && (width_p==bits) && ~vertical_p) \
begin: macro \
bsg_rp_tsmc_40_BUFFD8BWP_horiz_b``bits buf_gate (.i0(i),.o);\
end
module bsg_buf #(parameter `BSG_INV_PARAM(width_p)
, parameter harden_p=1
, parameter vertical_p=1
)
(input [width_p-1:0] i
, output [width_p-1:0] o
);
`bsg_buf_macro(89) else
`bsg_buf_macro(88) else
`bsg_buf_macro(87) else
`bsg_buf_macro(86) else
`bsg_buf_macro(85) else
`bsg_buf_macro(84) else
`bsg_buf_macro(83) else
`bsg_buf_macro(82) else
`bsg_buf_macro(81) else
`bsg_buf_macro(80) else
`bsg_buf_macro(79) else
`bsg_buf_macro(78) else
`bsg_buf_macro(77) else
`bsg_buf_macro(76) else
`bsg_buf_macro(75) else
`bsg_buf_macro(74) else
`bsg_buf_macro(73) else
`bsg_buf_macro(72) else
`bsg_buf_macro(71) else
`bsg_buf_macro(70) else
`bsg_buf_macro(69) else
`bsg_buf_macro(68) else
`bsg_buf_macro(67) else
`bsg_buf_macro(66) else
`bsg_buf_macro(65) else
`bsg_buf_macro(64) else
`bsg_buf_macro(63) else
`bsg_buf_macro(62) else
`bsg_buf_macro(61) else
`bsg_buf_macro(60) else
`bsg_buf_macro(59) else
`bsg_buf_macro(58) else
`bsg_buf_macro(57) else
`bsg_buf_macro(56) else
`bsg_buf_macro(55) else
`bsg_buf_macro(54) else
`bsg_buf_macro(53) else
`bsg_buf_macro(52) else
`bsg_buf_macro(51) else
`bsg_buf_macro(50) else
`bsg_buf_macro(49) else
`bsg_buf_macro(48) else
`bsg_buf_macro(47) else
`bsg_buf_macro(46) else
`bsg_buf_macro(45) else
`bsg_buf_macro(44) else
`bsg_buf_macro(43) else
`bsg_buf_macro(42) else
`bsg_buf_macro(41) else
`bsg_buf_macro(40) else
`bsg_buf_macro(39) else
`bsg_buf_macro(38) else
`bsg_buf_macro(37) else
`bsg_buf_macro(36) else
`bsg_buf_macro(35) else
`bsg_buf_macro(34) else
`bsg_buf_macro(33) else
`bsg_buf_macro(32) else
`bsg_buf_macro(31) else
`bsg_buf_macro(30) else
`bsg_buf_macro(29) else
`bsg_buf_macro(28) else
`bsg_buf_macro(27) else
`bsg_buf_macro(26) else
`bsg_buf_macro(25) else
`bsg_buf_macro(24) else
`bsg_buf_macro(23) else
`bsg_buf_macro(22) else
`bsg_buf_macro(21) else
`bsg_buf_macro(20) else
`bsg_buf_macro(19) else
`bsg_buf_macro(18) else
`bsg_buf_macro(17) else
`bsg_buf_macro(16) else
`bsg_buf_macro(15) else
`bsg_buf_macro(14) else
`bsg_buf_macro(13) else
`bsg_buf_macro(12) else
`bsg_buf_macro(11) else
`bsg_buf_macro(10) else
`bsg_buf_macro(9) else
`bsg_buf_macro(8) else
`bsg_buf_macro(7) else
`bsg_buf_macro(6) else
`bsg_buf_macro(5) else
`bsg_buf_macro(4) else
`bsg_buf_macro(3) else
`bsg_buf_macro(2) else
`bsg_buf_macro(1) else
begin :notmacro
initial assert(harden_p==0) else $error("## %m wanted to harden but no macro");
assign o = i;
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_buf)
|
`default_nettype none
`timescale 1ns/1ns
`define simulation
module tb_apr();
wire clk, reset;
clock clock(clk, reset);
// membus
wire membus_rq_cyc;
wire membus_rd_rq;
wire membus_wr_rq;
wire [21:35] membus_ma;
wire [18:21] membus_sel;
wire membus_fmc_select;
wire [0:35] membus_mb_write;
wire membus_wr_rs;
wire [0:35] membus_mb_read = membus_mb_write | membus_mb_read_0 | membus_mb_read_1;
wire membus_addr_ack = membus_addr_ack_0 | membus_addr_ack_1;
wire membus_rd_rs = membus_rd_rs_0 | membus_rd_rs_1;
// iobus
wire iobus_iob_poweron;
wire iobus_iob_reset;
wire iobus_datao_clear;
wire iobus_datao_set;
wire iobus_cono_clear;
wire iobus_cono_set;
wire iobus_iob_fm_datai;
wire iobus_iob_fm_status;
wire [3:9] iobus_ios;
wire [0:35] iobus_iob_in;
wire [1:7] iobus_pi_req = 0;
wire [0:35] iobus_iob_out = 0;
reg key_start = 0;
reg key_read_in = 0;
reg key_mem_cont = 0;
reg key_inst_cont = 0;
reg key_mem_stop = 0;
reg key_inst_stop = 0;
reg key_exec = 0;
reg key_io_reset = 0;
reg key_dep = 0;
reg key_dep_nxt = 0;
reg key_ex = 0;
reg key_ex_nxt = 0;
reg sw_addr_stop = 0;
reg sw_mem_disable = 0;
reg sw_repeat = 0;
reg sw_power = 0;
reg [0:35] datasw = 0;
reg [18:35] mas = 0;
reg sw_rim_maint = 0;
reg sw_repeat_bypass = 0;
reg sw_art3_maint = 0;
reg sw_sct_maint = 0;
reg sw_split_cyc = 0;
apr apr(
.clk(clk),
.reset(~reset),
.key_start(key_start),
.key_read_in(key_read_in),
.key_mem_cont(key_mem_cont),
.key_inst_cont(key_inst_cont),
.key_mem_stop(key_mem_stop),
.key_inst_stop(key_inst_stop),
.key_exec(key_exec),
.key_io_reset(key_io_reset),
.key_dep(key_dep),
.key_dep_nxt(key_dep_nxt),
.key_ex(key_ex),
.key_ex_nxt(key_ex_nxt),
.sw_addr_stop(sw_addr_stop),
.sw_mem_disable(sw_mem_disable),
.sw_repeat(sw_repeat),
.sw_power(sw_power),
.datasw(datasw),
.mas(mas),
.sw_rim_maint(sw_rim_maint),
.sw_repeat_bypass(sw_repeat_bypass),
.sw_art3_maint(sw_art3_maint),
.sw_sct_maint(sw_sct_maint),
.sw_split_cyc(sw_split_cyc),
.membus_wr_rs(membus_wr_rs),
.membus_rq_cyc(membus_rq_cyc),
.membus_rd_rq(membus_rd_rq),
.membus_wr_rq(membus_wr_rq),
.membus_ma(membus_ma),
.membus_sel(membus_sel),
.membus_fmc_select(membus_fmc_select),
.membus_mb_out(membus_mb_write),
.membus_addr_ack(membus_addr_ack),
.membus_rd_rs(membus_rd_rs),
.membus_mb_in(membus_mb_read),
.iobus_pi_req(iobus_pi_req),
.iobus_iob_in(iobus_iob_in)
);
wire [17:0] av_address;
wire av_write;
wire av_read;
wire [35:0] av_writedata;
wire [35:0] av_readdata;
wire av_waitrequest;
memory_32k mem(
.i_clk(clk),
.i_reset_n(reset),
.i_address(av_address),
.i_write(av_write),
.i_read(av_read),
.i_writedata(av_writedata),
.o_readdata(av_readdata),
.o_waitrequest(av_waitrequest)
);
wire [0:35] membus_mb_read_0;
wire membus_addr_ack_0;
wire membus_rd_rs_0;
core32k cmem(
.clk(clk),
.reset(~reset),
.power(1'b1),
.sw_single_step(1'b0),
.sw_restart(1'b0),
.membus_rq_cyc_p0(membus_rq_cyc),
.membus_rd_rq_p0(membus_rd_rq),
.membus_wr_rq_p0(membus_wr_rq),
.membus_ma_p0(membus_ma),
.membus_sel_p0(membus_sel),
.membus_fmc_select_p0(membus_fmc_select),
.membus_mb_in_p0(membus_mb_write),
.membus_wr_rs_p0(membus_wr_rs),
.membus_mb_out_p0(membus_mb_read_0),
.membus_addr_ack_p0(membus_addr_ack_0),
.membus_rd_rs_p0(membus_rd_rs_0),
.membus_wr_rs_p1(1'b0),
.membus_rq_cyc_p1(1'b0),
.membus_rd_rq_p1(1'b0),
.membus_wr_rq_p1(1'b0),
.membus_ma_p1(15'b0),
.membus_sel_p1(4'b0),
.membus_fmc_select_p1(1'b0),
.membus_mb_in_p1(36'b0),
.membus_wr_rs_p2(1'b0),
.membus_rq_cyc_p2(1'b0),
.membus_rd_rq_p2(1'b0),
.membus_wr_rq_p2(1'b0),
.membus_ma_p2(15'b0),
.membus_sel_p2(4'b0),
.membus_fmc_select_p2(1'b0),
.membus_mb_in_p2(36'b0),
.membus_wr_rs_p3(1'b0),
.membus_rq_cyc_p3(1'b0),
.membus_rd_rq_p3(1'b0),
.membus_wr_rq_p3(1'b0),
.membus_ma_p3(15'b0),
.membus_sel_p3(4'b0),
.membus_fmc_select_p3(1'b0),
.membus_mb_in_p3(36'b0),
.m_address(av_address),
.m_write(av_write),
.m_read(av_read),
.m_writedata(av_writedata),
.m_readdata(av_readdata),
.m_waitrequest(av_waitrequest)
);
wire [0:35] membus_mb_read_1;
wire membus_addr_ack_1;
wire membus_rd_rs_1;
fast162 fmem(
.clk(clk),
.reset(~reset),
.power(1'b1),
.sw_single_step(1'b0),
.sw_restart(1'b0),
.membus_rq_cyc_p0(membus_rq_cyc),
.membus_rd_rq_p0(membus_rd_rq),
.membus_wr_rq_p0(membus_wr_rq),
.membus_ma_p0(membus_ma),
.membus_sel_p0(membus_sel),
.membus_fmc_select_p0(membus_fmc_select),
.membus_mb_in_p0(membus_mb_write),
.membus_wr_rs_p0(membus_wr_rs),
.membus_mb_out_p0(membus_mb_read_1),
.membus_addr_ack_p0(membus_addr_ack_1),
.membus_rd_rs_p0(membus_rd_rs_1),
.membus_wr_rs_p1(1'b0),
.membus_rq_cyc_p1(1'b0),
.membus_rd_rq_p1(1'b0),
.membus_wr_rq_p1(1'b0),
.membus_ma_p1(15'b0),
.membus_sel_p1(4'b0),
.membus_fmc_select_p1(1'b0),
.membus_mb_in_p1(36'b0),
.membus_wr_rs_p2(1'b0),
.membus_rq_cyc_p2(1'b0),
.membus_rd_rq_p2(1'b0),
.membus_wr_rq_p2(1'b0),
.membus_ma_p2(15'b0),
.membus_sel_p2(4'b0),
.membus_fmc_select_p2(1'b0),
.membus_mb_in_p2(36'b0),
.membus_wr_rs_p3(1'b0),
.membus_rq_cyc_p3(1'b0),
.membus_rd_rq_p3(1'b0),
.membus_wr_rq_p3(1'b0),
.membus_ma_p3(15'b0),
.membus_sel_p3(4'b0),
.membus_fmc_select_p3(1'b0),
.membus_mb_in_p3(36'b0)
);
initial begin: init
integer i;
$dumpfile("dump.vcd");
$dumpvars();
for(i = 0; i < 'o40000; i = i + 1)
mem.ram.ram[i] <= 0;
#10;
mem.ram.ram['o42] <= 36'o334000_000000;
mem.ram.ram['o43] <= 36'o000000_000000;
mem.ram.ram['o44] <= 36'o334000_000000;
mem.ram.ram['o45] <= 36'o000000_000000;
mem.ram.ram['o46] <= 36'o334000_000000;
mem.ram.ram['o47] <= 36'o000000_000000;
mem.ram.ram['o50] <= 36'o334000_000000;
mem.ram.ram['o51] <= 36'o000000_000000;
mem.ram.ram['o52] <= 36'o334000_000000;
mem.ram.ram['o53] <= 36'o000000_000000;
mem.ram.ram['o100] <= 36'o202000001000;
mem.ram.ram['o101] <= 36'o254200000000;
mem.ram.ram['o1000] <= 36'o123321456654;
fmem.ff[0] <= 36'o611042323251;
fmem.ff[1] <= 36'o472340710317;
fmem.ff[2] <= 36'o545777777776;
mas <= 'o100;
#200;
sw_power <= 1;
#200;
// key_mem_stop <= 1;
key_start <= 1;
#1000;
key_start <= 0;
/*
#500;
key_mem_stop <= 0;
key_inst_stop <= 1;
#1000;
key_inst_stop <= 0;
#1000;
key_inst_cont <= 1;
#500;
key_inst_cont <= 0;
*/
end
initial begin
#50000;
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFBBP_BLACKBOX_V
`define SKY130_FD_SC_LP__SDFBBP_BLACKBOX_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFBBP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MUX2_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__MUX2_PP_BLACKBOX_V
/**
* mux2: 2-input multiplexer.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__mux2 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__MUX2_PP_BLACKBOX_V
|
//-----------------------------------------------------------------
// MPX 32-bit Soft-Core Processor
// V0.1
// Ultra-Embedded.com
// Copyright 2011 - 2012
//
// Email: [email protected]
//
// License: LGPL
//
// If you would like a version with a different license for use
// in commercial projects please contact the above email address
// for more details.
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2012 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
`include "mpx_defs.v"
//-----------------------------------------------------------------
// Module
//-----------------------------------------------------------------
module mpx_regfile_sim
(
clk_i,
rst_i,
en_i,
wr_i,
rs_i,
rt_i,
rd_i,
reg_rs_o,
reg_rt_o,
reg_rd_i
);
//-----------------------------------------------------------------
// I/O
//-----------------------------------------------------------------
input clk_i /*verilator public*/;
input rst_i /*verilator public*/;
input en_i /*verilator public*/;
input wr_i /*verilator public*/;
input [4:0] rs_i /*verilator public*/;
input [4:0] rt_i /*verilator public*/;
input [4:0] rd_i /*verilator public*/;
output [31:0] reg_rs_o /*verilator public*/;
output [31:0] reg_rt_o /*verilator public*/;
input [31:0] reg_rd_i /*verilator public*/;
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
// Register file
reg [31:0] reg_r1_at;
reg [31:0] reg_r2_v0;
reg [31:0] reg_r3_v1;
reg [31:0] reg_r4_a0;
reg [31:0] reg_r5_a1;
reg [31:0] reg_r6_a2;
reg [31:0] reg_r7_a3;
reg [31:0] reg_r8;
reg [31:0] reg_r9;
reg [31:0] reg_r10;
reg [31:0] reg_r11;
reg [31:0] reg_r12;
reg [31:0] reg_r13;
reg [31:0] reg_r14;
reg [31:0] reg_r15;
reg [31:0] reg_r16;
reg [31:0] reg_r17;
reg [31:0] reg_r18;
reg [31:0] reg_r19;
reg [31:0] reg_r20;
reg [31:0] reg_r21;
reg [31:0] reg_r22;
reg [31:0] reg_r23;
reg [31:0] reg_r24;
reg [31:0] reg_r25;
reg [31:0] reg_k0;
reg [31:0] reg_k1;
reg [31:0] reg_gp;
reg [31:0] reg_sp;
reg [31:0] reg_fp;
reg [31:0] reg_ra;
//-----------------------------------------------------------------
// Register File (for simulation)
//-----------------------------------------------------------------
// Synchronous register write back
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i)
begin
reg_r1_at <= 32'h00000000;
reg_r2_v0 <= 32'h00000000;
reg_r3_v1 <= 32'h00000000;
reg_r4_a0 <= 32'h00000000;
reg_r5_a1 <= 32'h00000000;
reg_r6_a2 <= 32'h00000000;
reg_r7_a3 <= 32'h00000000;
reg_r8 <= 32'h00000000;
reg_r9 <= 32'h00000000;
reg_r10 <= 32'h00000000;
reg_r11 <= 32'h00000000;
reg_r12 <= 32'h00000000;
reg_r13 <= 32'h00000000;
reg_r14 <= 32'h00000000;
reg_r15 <= 32'h00000000;
reg_r16 <= 32'h00000000;
reg_r17 <= 32'h00000000;
reg_r18 <= 32'h00000000;
reg_r19 <= 32'h00000000;
reg_r20 <= 32'h00000000;
reg_r21 <= 32'h00000000;
reg_r22 <= 32'h00000000;
reg_r23 <= 32'h00000000;
reg_r24 <= 32'h00000000;
reg_r25 <= 32'h00000000;
reg_k0 <= 32'h00000000;
reg_k1 <= 32'h00000000;
reg_gp <= 32'h00000000;
reg_sp <= 32'h00000000;
reg_fp <= 32'h00000000;
reg_ra <= 32'h00000000;
end
else if (en_i == 1'b1)
begin
if (wr_i == 1'b1)
case (rd_i[4:0])
5'b00001 :
reg_r1_at <= reg_rd_i;
5'b00010 :
reg_r2_v0 <= reg_rd_i;
5'b00011 :
reg_r3_v1 <= reg_rd_i;
5'b00100 :
reg_r4_a0 <= reg_rd_i;
5'b00101 :
reg_r5_a1 <= reg_rd_i;
5'b00110 :
reg_r6_a2 <= reg_rd_i;
5'b00111 :
reg_r7_a3 <= reg_rd_i;
5'b01000 :
reg_r8 <= reg_rd_i;
5'b01001 :
reg_r9 <= reg_rd_i;
5'b01010 :
reg_r10 <= reg_rd_i;
5'b01011 :
reg_r11 <= reg_rd_i;
5'b01100 :
reg_r12 <= reg_rd_i;
5'b01101 :
reg_r13 <= reg_rd_i;
5'b01110 :
reg_r14 <= reg_rd_i;
5'b01111 :
reg_r15 <= reg_rd_i;
5'b10000 :
reg_r16 <= reg_rd_i;
5'b10001 :
reg_r17 <= reg_rd_i;
5'b10010 :
reg_r18 <= reg_rd_i;
5'b10011 :
reg_r19 <= reg_rd_i;
5'b10100 :
reg_r20 <= reg_rd_i;
5'b10101 :
reg_r21 <= reg_rd_i;
5'b10110 :
reg_r22 <= reg_rd_i;
5'b10111 :
reg_r23 <= reg_rd_i;
5'b11000 :
reg_r24 <= reg_rd_i;
5'b11001 :
reg_r25 <= reg_rd_i;
5'b11010 :
reg_k0 <= reg_rd_i;
5'b11011 :
reg_k1 <= reg_rd_i;
5'b11100 :
reg_gp <= reg_rd_i;
5'b11101 :
reg_sp <= reg_rd_i;
5'b11110 :
reg_fp <= reg_rd_i;
5'b11111 :
reg_ra <= reg_rd_i;
default :
;
endcase
end
end
// Asynchronous Register read (Rs & Rd)
always @ (rs_i or rt_i or reg_r1_at or reg_r2_v0 or reg_r3_v1 or reg_r4_a0 or reg_r5_a1 or reg_r6_a2 or reg_r7_a3 or reg_r8 or reg_r9 or reg_r10 or reg_r11 or reg_r12 or reg_r13 or reg_r14 or reg_r15 or reg_r16 or reg_r17 or reg_r18 or reg_r19 or reg_r20 or reg_r21 or reg_r22 or reg_r23 or reg_r24 or reg_r25 or reg_k0 or reg_k1 or reg_gp or reg_sp or reg_fp or reg_ra )
begin
case (rs_i)
5'b00000 :
reg_rs_o = 32'h00000000;
5'b00001 :
reg_rs_o = reg_r1_at;
5'b00010 :
reg_rs_o = reg_r2_v0;
5'b00011 :
reg_rs_o = reg_r3_v1;
5'b00100 :
reg_rs_o = reg_r4_a0;
5'b00101 :
reg_rs_o = reg_r5_a1;
5'b00110 :
reg_rs_o = reg_r6_a2;
5'b00111 :
reg_rs_o = reg_r7_a3;
5'b01000 :
reg_rs_o = reg_r8;
5'b01001 :
reg_rs_o = reg_r9;
5'b01010 :
reg_rs_o = reg_r10;
5'b01011 :
reg_rs_o = reg_r11;
5'b01100 :
reg_rs_o = reg_r12;
5'b01101 :
reg_rs_o = reg_r13;
5'b01110 :
reg_rs_o = reg_r14;
5'b01111 :
reg_rs_o = reg_r15;
5'b10000 :
reg_rs_o = reg_r16;
5'b10001 :
reg_rs_o = reg_r17;
5'b10010 :
reg_rs_o = reg_r18;
5'b10011 :
reg_rs_o = reg_r19;
5'b10100 :
reg_rs_o = reg_r20;
5'b10101 :
reg_rs_o = reg_r21;
5'b10110 :
reg_rs_o = reg_r22;
5'b10111 :
reg_rs_o = reg_r23;
5'b11000 :
reg_rs_o = reg_r24;
5'b11001 :
reg_rs_o = reg_r25;
5'b11010 :
reg_rs_o = reg_k0;
5'b11011 :
reg_rs_o = reg_k1;
5'b11100 :
reg_rs_o = reg_gp;
5'b11101 :
reg_rs_o = reg_sp;
5'b11110 :
reg_rs_o = reg_fp;
5'b11111 :
reg_rs_o = reg_ra;
default :
reg_rs_o = 32'h00000000;
endcase
case (rt_i)
5'b00000 :
reg_rt_o = 32'h00000000;
5'b00001 :
reg_rt_o = reg_r1_at;
5'b00010 :
reg_rt_o = reg_r2_v0;
5'b00011 :
reg_rt_o = reg_r3_v1;
5'b00100 :
reg_rt_o = reg_r4_a0;
5'b00101 :
reg_rt_o = reg_r5_a1;
5'b00110 :
reg_rt_o = reg_r6_a2;
5'b00111 :
reg_rt_o = reg_r7_a3;
5'b01000 :
reg_rt_o = reg_r8;
5'b01001 :
reg_rt_o = reg_r9;
5'b01010 :
reg_rt_o = reg_r10;
5'b01011 :
reg_rt_o = reg_r11;
5'b01100 :
reg_rt_o = reg_r12;
5'b01101 :
reg_rt_o = reg_r13;
5'b01110 :
reg_rt_o = reg_r14;
5'b01111 :
reg_rt_o = reg_r15;
5'b10000 :
reg_rt_o = reg_r16;
5'b10001 :
reg_rt_o = reg_r17;
5'b10010 :
reg_rt_o = reg_r18;
5'b10011 :
reg_rt_o = reg_r19;
5'b10100 :
reg_rt_o = reg_r20;
5'b10101 :
reg_rt_o = reg_r21;
5'b10110 :
reg_rt_o = reg_r22;
5'b10111 :
reg_rt_o = reg_r23;
5'b11000 :
reg_rt_o = reg_r24;
5'b11001 :
reg_rt_o = reg_r25;
5'b11010 :
reg_rt_o = reg_k0;
5'b11011 :
reg_rt_o = reg_k1;
5'b11100 :
reg_rt_o = reg_gp;
5'b11101 :
reg_rt_o = reg_sp;
5'b11110 :
reg_rt_o = reg_fp;
5'b11111 :
reg_rt_o = reg_ra;
default :
reg_rt_o = 32'h00000000;
endcase
end
endmodule
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