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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A31O_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__A31O_PP_BLACKBOX_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a31o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A31O_PP_BLACKBOX_V
|
/* lab3_part4.v - Three different storage elements:
* - gated D latch;
* - positive-edge triggered D flipflop;
* - negative-edge triggered D flip-flop.
*
* Copyright (c) 2014, Artem Tovbin <arty99 at gmail dot com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
+----+
D ---+-+D Q+--- Qa
| | _| _
Clock-+-+-+ClkQ+--- Qa
| | +----+
| |
| |
| |
| | +----+
| +-+D Q+--- Qb
| | | _| _
+--+-+> Q+--- Qb
| | +----+
| |
| |
| |
| | +----+
| +-+D Q+--- Qc
| | _| _
+---o+> Q+--- Qc
+----+
*/
module lab3_part4 (D, Clk, Qa, Qb, Qc);
input D, Clk;
output Qa, Qb, Qc;
wire D, Clk;
Dflop D0 (D, Clk, Qa);
PED P0 (D, Clk, Qb);
NED N0 (D, Clk, Qc);
endmodule
module NED (D, Clk, Q);
input D, Clk;
output reg Q;
always @ (negedge Clk)
Q = D;
endmodule
module PED (D, Clk, Q);
input D, Clk;
output reg Q;
always @ (posedge Clk)
Q = D;
endmodule
module Dflop (D, Clk, Q);
input D, Clk;
output reg Q;
always @ (D, Clk)
if (Clk)
Q = D;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MUX4_FUNCTIONAL_V
`define SKY130_FD_SC_LS__MUX4_FUNCTIONAL_V
/**
* mux4: 4-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_4to2/sky130_fd_sc_ls__udp_mux_4to2.v"
`celldefine
module sky130_fd_sc_ls__mux4 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
// Module ports
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
// Local signals
wire mux_4to20_out_X;
// Name Output Other arguments
sky130_fd_sc_ls__udp_mux_4to2 mux_4to20 (mux_4to20_out_X, A0, A1, A2, A3, S0, S1);
buf buf0 (X , mux_4to20_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__MUX4_FUNCTIONAL_V |
/**************************************************************************************************/
/* FPGA Sort for VC707 ArchLab. TOKYO TECH */
/**************************************************************************************************/
`default_nettype none
`include "define.v"
/***** Sorter Cell *****/
/**************************************************************************************************/
module SCELL(input wire valid1,
input wire valid2,
output wire deq1,
output wire deq2,
input wire [`SORTW-1:0] din1,
input wire [`SORTW-1:0] din2,
input wire full,
output wire [`SORTW-1:0] dout,
output wire enq);
wire cmp1 = (din1 < din2);
function [`SORTW-1:0] mux;
input [`SORTW-1:0] a;
input [`SORTW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
assign enq = (!full && valid1 && valid2);
assign deq1 = (enq && cmp1);
assign deq2 = (enq && !cmp1);
assign dout = mux(din2, din1, cmp1);
endmodule
/***** FIFO of only two entries *****/
/**************************************************************************************************/
module MRE2 #(parameter FIFO_SIZE = 1, // dummy, just for portability
parameter FIFO_WIDTH = 32) // fifo width in bit
(input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wire [FIFO_WIDTH-1:0] din,
output wire [FIFO_WIDTH-1:0] dot,
output wire emp,
output wire full,
output reg [FIFO_SIZE:0] cnt);
reg head, tail;
reg [FIFO_WIDTH-1:0] mem [(1<<FIFO_SIZE)-1:0];
assign emp = (cnt==0);
assign full = (cnt==2);
assign dot = mem[head];
always @(posedge CLK) begin
if (RST) {cnt, head, tail} <= 0;
else begin
case ({enq, deq})
2'b01: begin head<=~head; cnt<=cnt-1; end
2'b10: begin mem[tail]<=din; tail<=~tail; cnt<=cnt+1; end
2'b11: begin mem[tail]<=din; head<=~head; tail<=~tail; end
endcase
end
end
endmodule
/***** general FIFO (BRAM Version) *****/
/**************************************************************************************************/
module BFIFO #(parameter FIFO_SIZE = 2, // size in log scale, 2 for 4 entry, 3 for 8 entry
parameter FIFO_WIDTH = 32) // fifo width in bit
(input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wire [FIFO_WIDTH-1:0] din,
output reg [FIFO_WIDTH-1:0] dot,
output wire emp,
output wire full,
output reg [FIFO_SIZE:0] cnt);
reg [FIFO_SIZE-1:0] head, tail;
reg [FIFO_WIDTH-1:0] mem [(1<<FIFO_SIZE)-1:0];
assign emp = (cnt==0);
assign full = (cnt==(1<<FIFO_SIZE));
always @(posedge CLK) dot <= mem[head];
always @(posedge CLK) begin
if (RST) {cnt, head, tail} <= 0;
else begin
case ({enq, deq})
2'b01: begin head<=head+1; cnt<=cnt-1; end
2'b10: begin mem[tail]<=din; tail<=tail+1; cnt<=cnt+1; end
2'b11: begin mem[tail]<=din; head<=head+1; tail<=tail+1; end
endcase
end
end
endmodule
/***** Input Module Pre *****/
/**************************************************************************************************/
module INMOD2(input wire CLK,
input wire RST,
input wire [`DRAMW-1:0] din, // input data
input wire den, // input data enable
input wire IB_full, // the next module is full ?
output wire [`SORTW-1:0] dot, // this module's data output
output wire IB_enq, // the next module's enqueue signal
output reg [1:0] im_req); // DRAM data request
wire req;
reg deq;
wire [`DRAMW-1:0] im_dot;
wire [`IB_SIZE:0] im_cnt;
wire im_full, im_emp;
wire im_enq = den; // (!im_full && den);
wire im_deq = (req && !im_emp);
always @(posedge CLK) im_req <= (im_cnt==0) ? 3 : (im_cnt<`REQ_THRE);
always @(posedge CLK) deq <= im_deq;
BFIFO #(`IB_SIZE, `DRAMW) // note, using BRAM
imf(.CLK(CLK), .RST(RST), .enq(im_enq), .deq(im_deq), .din(din),
.dot(im_dot), .emp(im_emp), .full(im_full), .cnt(im_cnt));
INMOD inmod(.CLK(CLK), .RST(RST), .d_dout(im_dot), .d_douten(deq),
.IB_full(IB_full), .im_dot(dot), .IB_enq(IB_enq), .im_req(req));
endmodule
/***** Input Module *****/
/**************************************************************************************************/
module INMOD(input wire CLK,
input wire RST,
input wire [`DRAMW-1:0] d_dout, // DRAM output
input wire d_douten, // DRAM output enable
input wire IB_full, // INBUF is full ?
output wire [`SORTW-1:0] im_dot, // this module's data output
output wire IB_enq,
output wire im_req); // DRAM data request
reg [`DRAMW-1:0] dot_t; // shift register to feed 32bit data
reg [3:0] cnte; // the number of enqueued elements in one block
reg cntez; // cnte==0 ?
reg cntef; // cnte==15 ?
wire [`DRAMW-1:0] dot;
wire im_emp, im_full;
wire im_enq = d_douten; // (!im_full && d_douten);
wire im_deq = (IB_enq && cntef); // old version may have a bug here!!
function [`SORTW-1:0] mux;
input [`SORTW-1:0] a;
input [`SORTW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
assign IB_enq = (!IB_full && !im_emp); // enqueue signal for the next module
assign im_req = (im_emp || im_deq); // note!!!
assign im_dot = mux(dot_t[31:0], dot[31:0], cntez);
always @(posedge CLK) begin
if (RST) begin
cnte <= 0;
end else begin
if (IB_enq) cnte <= cnte + 1;
end
end
always @(posedge CLK) begin
if (RST) begin
cntez <= 1;
end else begin
case ({IB_enq, (cnte==15)})
2'b10: cntez <= 0;
2'b11: cntez <= 1;
endcase
end
end
always @(posedge CLK) begin
if (RST) begin
cntef <= 0;
end else begin
case ({IB_enq, (cnte==14)})
2'b10: cntef <= 0;
2'b11: cntef <= 1;
endcase
end
end
always @(posedge CLK) begin
case ({IB_enq, cntez})
2'b10: dot_t <= {32'b0, dot_t[`DRAMW-1:32]};
2'b11: dot_t <= {32'b0, dot[`DRAMW-1:32]};
endcase
end
MRE2 #(1, `DRAMW) imf(.CLK(CLK), .RST(RST), .enq(im_enq), .deq(im_deq),
.din(d_dout), .dot(dot), .emp(im_emp), .full(im_full));
endmodule
/***** input buffer module *****/
/**************************************************************************************************/
module INBUF(input wire CLK,
input wire RST,
output wire ib_full, // this module is full
input wire full, // next moldule's full
output wire enq, // next module's enqueue
input wire [`SORTW-1:0] din, // data in
output wire [`SORTW-1:0] dot, // data out
input wire ib_enq, // this module's enqueue
input wire [`PHASE_W] phase, // current phase
input wire idone); // iteration done, this module's enqueue
function mux1;
input a;
input b;
input sel;
begin
case (sel)
1'b0: mux1 = a;
1'b1: mux1 = b;
endcase
end
endfunction
function [`SORTW-1:0] mux32;
input [`SORTW-1:0] a;
input [`SORTW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux32 = a;
1'b1: mux32 = b;
endcase
end
endfunction
/*****************************************/
wire [`SORTW-1:0] F_dout;
wire F_deq, F_emp;
reg [31:0] ecnt; // the number of elements in one iteration
reg ecntz; // ecnt==0 ?
wire f_full;
MRE2 #(1,`SORTW) F(.CLK(CLK), .RST(RST), .enq(ib_enq), .deq(F_deq), // input buffer FIFO
.din(din), .dot(F_dout), .emp(F_emp), .full(f_full));
assign ib_full = mux1(f_full, 0, F_deq); // INBUF back_pressure
/*****************************************/
assign enq = !full && (!F_emp || ecntz); // enqueue for the next buffer
assign F_deq = enq && (ecnt!=0); //
assign dot = mux32(F_dout, `MAX_VALUE, ecntz);
always @(posedge CLK) begin
if (RST || idone) begin
ecnt <= (`ELEMS_PER_UNIT << (phase * `WAY_LOG)); /// note
ecntz <= 0;
end else begin
if (ecnt!=0 && enq) ecnt <= ecnt - 1;
if (ecnt==1 && enq) ecntz <= 1; // old version has a bug here!
end
end
endmodule
/**************************************************************************************************/
module STREE(input wire CLK,
input wire RST_in,
input wire irst,
input wire frst,
input wire [`PHASE_W] phase_in,
input wire [`SORTW*`SORT_WAY-1:0] s_din, // sorting-tree input data
input wire [`SORT_WAY-1:0] enq, // enqueue
output wire [`SORT_WAY-1:0] full, // buffer is full ?
input wire deq,
output wire [`SORTW-1:0] dot, // output data
output wire emp);
reg RST;
always @(posedge CLK) RST <= RST_in;
reg [`PHASE_W] phase;
always @(posedge CLK) phase <= phase_in;
wire [`SORTW-1:0] d00, d01, d02, d03, d04, d05, d06, d07;
wire [`SORTW-1:0] d08, d09, d10, d11, d12, d13, d14, d15;
assign {d00, d01, d02, d03, d04, d05, d06, d07, d08, d09, d10, d11, d12, d13, d14, d15} = s_din;
wire F01_enq, F01_deq, F01_emp, F01_full; wire [31:0] F01_din, F01_dot; wire [1:0] F01_cnt;
wire F02_enq, F02_deq, F02_emp, F02_full; wire [31:0] F02_din, F02_dot; wire [1:0] F02_cnt;
wire F03_enq, F03_deq, F03_emp, F03_full; wire [31:0] F03_din, F03_dot; wire [1:0] F03_cnt;
wire F04_enq, F04_deq, F04_emp, F04_full; wire [31:0] F04_din, F04_dot; wire [1:0] F04_cnt;
wire F05_enq, F05_deq, F05_emp, F05_full; wire [31:0] F05_din, F05_dot; wire [1:0] F05_cnt;
wire F06_enq, F06_deq, F06_emp, F06_full; wire [31:0] F06_din, F06_dot; wire [1:0] F06_cnt;
wire F07_enq, F07_deq, F07_emp, F07_full; wire [31:0] F07_din, F07_dot; wire [1:0] F07_cnt;
wire F08_enq, F08_deq, F08_emp, F08_full; wire [31:0] F08_din, F08_dot; wire [1:0] F08_cnt;
wire F09_enq, F09_deq, F09_emp, F09_full; wire [31:0] F09_din, F09_dot; wire [1:0] F09_cnt;
wire F10_enq, F10_deq, F10_emp, F10_full; wire [31:0] F10_din, F10_dot; wire [1:0] F10_cnt;
wire F11_enq, F11_deq, F11_emp, F11_full; wire [31:0] F11_din, F11_dot; wire [1:0] F11_cnt;
wire F12_enq, F12_deq, F12_emp, F12_full; wire [31:0] F12_din, F12_dot; wire [1:0] F12_cnt;
wire F13_enq, F13_deq, F13_emp, F13_full; wire [31:0] F13_din, F13_dot; wire [1:0] F13_cnt;
wire F14_enq, F14_deq, F14_emp, F14_full; wire [31:0] F14_din, F14_dot; wire [1:0] F14_cnt;
wire F15_enq, F15_deq, F15_emp, F15_full; wire [31:0] F15_din, F15_dot; wire [1:0] F15_cnt;
wire F16_enq, F16_deq, F16_emp, F16_full; wire [31:0] F16_din, F16_dot; wire [1:0] F16_cnt;
wire F17_enq, F17_deq, F17_emp, F17_full; wire [31:0] F17_din, F17_dot; wire [1:0] F17_cnt;
wire F18_enq, F18_deq, F18_emp, F18_full; wire [31:0] F18_din, F18_dot; wire [1:0] F18_cnt;
wire F19_enq, F19_deq, F19_emp, F19_full; wire [31:0] F19_din, F19_dot; wire [1:0] F19_cnt;
wire F20_enq, F20_deq, F20_emp, F20_full; wire [31:0] F20_din, F20_dot; wire [1:0] F20_cnt;
wire F21_enq, F21_deq, F21_emp, F21_full; wire [31:0] F21_din, F21_dot; wire [1:0] F21_cnt;
wire F22_enq, F22_deq, F22_emp, F22_full; wire [31:0] F22_din, F22_dot; wire [1:0] F22_cnt;
wire F23_enq, F23_deq, F23_emp, F23_full; wire [31:0] F23_din, F23_dot; wire [1:0] F23_cnt;
wire F24_enq, F24_deq, F24_emp, F24_full; wire [31:0] F24_din, F24_dot; wire [1:0] F24_cnt;
wire F25_enq, F25_deq, F25_emp, F25_full; wire [31:0] F25_din, F25_dot; wire [1:0] F25_cnt;
wire F26_enq, F26_deq, F26_emp, F26_full; wire [31:0] F26_din, F26_dot; wire [1:0] F26_cnt;
wire F27_enq, F27_deq, F27_emp, F27_full; wire [31:0] F27_din, F27_dot; wire [1:0] F27_cnt;
wire F28_enq, F28_deq, F28_emp, F28_full; wire [31:0] F28_din, F28_dot; wire [1:0] F28_cnt;
wire F29_enq, F29_deq, F29_emp, F29_full; wire [31:0] F29_din, F29_dot; wire [1:0] F29_cnt;
wire F30_enq, F30_deq, F30_emp, F30_full; wire [31:0] F30_din, F30_dot; wire [1:0] F30_cnt;
wire F31_enq, F31_deq, F31_emp, F31_full; wire [31:0] F31_din, F31_dot; wire [1:0] F31_cnt;
INBUF IN16(CLK, RST, full[0], F16_full, F16_enq, d00, F16_din, enq[0], phase, irst);
INBUF IN17(CLK, RST, full[1], F17_full, F17_enq, d01, F17_din, enq[1], phase, irst);
INBUF IN18(CLK, RST, full[2], F18_full, F18_enq, d02, F18_din, enq[2], phase, irst);
INBUF IN19(CLK, RST, full[3], F19_full, F19_enq, d03, F19_din, enq[3], phase, irst);
INBUF IN20(CLK, RST, full[4], F20_full, F20_enq, d04, F20_din, enq[4], phase, irst);
INBUF IN21(CLK, RST, full[5], F21_full, F21_enq, d05, F21_din, enq[5], phase, irst);
INBUF IN22(CLK, RST, full[6], F22_full, F22_enq, d06, F22_din, enq[6], phase, irst);
INBUF IN23(CLK, RST, full[7], F23_full, F23_enq, d07, F23_din, enq[7], phase, irst);
INBUF IN24(CLK, RST, full[8], F24_full, F24_enq, d08, F24_din, enq[8], phase, irst);
INBUF IN25(CLK, RST, full[9], F25_full, F25_enq, d09, F25_din, enq[9], phase, irst);
INBUF IN26(CLK, RST, full[10], F26_full, F26_enq, d10, F26_din, enq[10], phase, irst);
INBUF IN27(CLK, RST, full[11], F27_full, F27_enq, d11, F27_din, enq[11], phase, irst);
INBUF IN28(CLK, RST, full[12], F28_full, F28_enq, d12, F28_din, enq[12], phase, irst);
INBUF IN29(CLK, RST, full[13], F29_full, F29_enq, d13, F29_din, enq[13], phase, irst);
INBUF IN30(CLK, RST, full[14], F30_full, F30_enq, d14, F30_din, enq[14], phase, irst);
INBUF IN31(CLK, RST, full[15], F31_full, F31_enq, d15, F31_din, enq[15], phase, irst);
MRE2 #(1,32) F01(CLK, frst, F01_enq, F01_deq, F01_din, F01_dot, F01_emp, F01_full, F01_cnt);
MRE2 #(1,32) F02(CLK, frst, F02_enq, F02_deq, F02_din, F02_dot, F02_emp, F02_full, F02_cnt);
MRE2 #(1,32) F03(CLK, frst, F03_enq, F03_deq, F03_din, F03_dot, F03_emp, F03_full, F03_cnt);
MRE2 #(1,32) F04(CLK, frst, F04_enq, F04_deq, F04_din, F04_dot, F04_emp, F04_full, F04_cnt);
MRE2 #(1,32) F05(CLK, frst, F05_enq, F05_deq, F05_din, F05_dot, F05_emp, F05_full, F05_cnt);
MRE2 #(1,32) F06(CLK, frst, F06_enq, F06_deq, F06_din, F06_dot, F06_emp, F06_full, F06_cnt);
MRE2 #(1,32) F07(CLK, frst, F07_enq, F07_deq, F07_din, F07_dot, F07_emp, F07_full, F07_cnt);
MRE2 #(1,32) F08(CLK, frst, F08_enq, F08_deq, F08_din, F08_dot, F08_emp, F08_full, F08_cnt);
MRE2 #(1,32) F09(CLK, frst, F09_enq, F09_deq, F09_din, F09_dot, F09_emp, F09_full, F09_cnt);
MRE2 #(1,32) F10(CLK, frst, F10_enq, F10_deq, F10_din, F10_dot, F10_emp, F10_full, F10_cnt);
MRE2 #(1,32) F11(CLK, frst, F11_enq, F11_deq, F11_din, F11_dot, F11_emp, F11_full, F11_cnt);
MRE2 #(1,32) F12(CLK, frst, F12_enq, F12_deq, F12_din, F12_dot, F12_emp, F12_full, F12_cnt);
MRE2 #(1,32) F13(CLK, frst, F13_enq, F13_deq, F13_din, F13_dot, F13_emp, F13_full, F13_cnt);
MRE2 #(1,32) F14(CLK, frst, F14_enq, F14_deq, F14_din, F14_dot, F14_emp, F14_full, F14_cnt);
MRE2 #(1,32) F15(CLK, frst, F15_enq, F15_deq, F15_din, F15_dot, F15_emp, F15_full, F15_cnt);
MRE2 #(1,32) F16(CLK, frst, F16_enq, F16_deq, F16_din, F16_dot, F16_emp, F16_full, F16_cnt);
MRE2 #(1,32) F17(CLK, frst, F17_enq, F17_deq, F17_din, F17_dot, F17_emp, F17_full, F17_cnt);
MRE2 #(1,32) F18(CLK, frst, F18_enq, F18_deq, F18_din, F18_dot, F18_emp, F18_full, F18_cnt);
MRE2 #(1,32) F19(CLK, frst, F19_enq, F19_deq, F19_din, F19_dot, F19_emp, F19_full, F19_cnt);
MRE2 #(1,32) F20(CLK, frst, F20_enq, F20_deq, F20_din, F20_dot, F20_emp, F20_full, F20_cnt);
MRE2 #(1,32) F21(CLK, frst, F21_enq, F21_deq, F21_din, F21_dot, F21_emp, F21_full, F21_cnt);
MRE2 #(1,32) F22(CLK, frst, F22_enq, F22_deq, F22_din, F22_dot, F22_emp, F22_full, F22_cnt);
MRE2 #(1,32) F23(CLK, frst, F23_enq, F23_deq, F23_din, F23_dot, F23_emp, F23_full, F23_cnt);
MRE2 #(1,32) F24(CLK, frst, F24_enq, F24_deq, F24_din, F24_dot, F24_emp, F24_full, F24_cnt);
MRE2 #(1,32) F25(CLK, frst, F25_enq, F25_deq, F25_din, F25_dot, F25_emp, F25_full, F25_cnt);
MRE2 #(1,32) F26(CLK, frst, F26_enq, F26_deq, F26_din, F26_dot, F26_emp, F26_full, F26_cnt);
MRE2 #(1,32) F27(CLK, frst, F27_enq, F27_deq, F27_din, F27_dot, F27_emp, F27_full, F27_cnt);
MRE2 #(1,32) F28(CLK, frst, F28_enq, F28_deq, F28_din, F28_dot, F28_emp, F28_full, F28_cnt);
MRE2 #(1,32) F29(CLK, frst, F29_enq, F29_deq, F29_din, F29_dot, F29_emp, F29_full, F29_cnt);
MRE2 #(1,32) F30(CLK, frst, F30_enq, F30_deq, F30_din, F30_dot, F30_emp, F30_full, F30_cnt);
MRE2 #(1,32) F31(CLK, frst, F31_enq, F31_deq, F31_din, F31_dot, F31_emp, F31_full, F31_cnt);
SCELL S01(!F02_emp, !F03_emp, F02_deq, F03_deq, F02_dot, F03_dot, F01_full, F01_din, F01_enq);
SCELL S02(!F04_emp, !F05_emp, F04_deq, F05_deq, F04_dot, F05_dot, F02_full, F02_din, F02_enq);
SCELL S03(!F06_emp, !F07_emp, F06_deq, F07_deq, F06_dot, F07_dot, F03_full, F03_din, F03_enq);
SCELL S04(!F08_emp, !F09_emp, F08_deq, F09_deq, F08_dot, F09_dot, F04_full, F04_din, F04_enq);
SCELL S05(!F10_emp, !F11_emp, F10_deq, F11_deq, F10_dot, F11_dot, F05_full, F05_din, F05_enq);
SCELL S06(!F12_emp, !F13_emp, F12_deq, F13_deq, F12_dot, F13_dot, F06_full, F06_din, F06_enq);
SCELL S07(!F14_emp, !F15_emp, F14_deq, F15_deq, F14_dot, F15_dot, F07_full, F07_din, F07_enq);
SCELL S08(!F16_emp, !F17_emp, F16_deq, F17_deq, F16_dot, F17_dot, F08_full, F08_din, F08_enq);
SCELL S09(!F18_emp, !F19_emp, F18_deq, F19_deq, F18_dot, F19_dot, F09_full, F09_din, F09_enq);
SCELL S10(!F20_emp, !F21_emp, F20_deq, F21_deq, F20_dot, F21_dot, F10_full, F10_din, F10_enq);
SCELL S11(!F22_emp, !F23_emp, F22_deq, F23_deq, F22_dot, F23_dot, F11_full, F11_din, F11_enq);
SCELL S12(!F24_emp, !F25_emp, F24_deq, F25_deq, F24_dot, F25_dot, F12_full, F12_din, F12_enq);
SCELL S13(!F26_emp, !F27_emp, F26_deq, F27_deq, F26_dot, F27_dot, F13_full, F13_din, F13_enq);
SCELL S14(!F28_emp, !F29_emp, F28_deq, F29_deq, F28_dot, F29_dot, F14_full, F14_din, F14_enq);
SCELL S15(!F30_emp, !F31_emp, F30_deq, F31_deq, F30_dot, F31_dot, F15_full, F15_din, F15_enq);
assign F01_deq = deq;
assign dot = F01_dot;
assign emp = F01_emp;
endmodule
/***** Output Module *****/
/**************************************************************************************************/
module OTMOD(input wire CLK,
input wire RST,
input wire F01_deq,
input wire [`SORTW-1:0] F01_dot,
input wire OB_deq,
output wire [`DRAMW-1:0] OB_dot,
output wire OB_full,
output reg OB_req);
reg [3:0] ob_buf_t_cnt; // counter for temporary register
reg ob_enque;
reg [`DRAMW-1:0] ob_buf_t;
wire [`DRAMW-1:0] OB_din = ob_buf_t;
wire OB_enq = ob_enque;
wire [`OB_SIZE:0] OB_cnt;
always @(posedge CLK) OB_req <= (OB_cnt>=`DRAM_WBLOCKS);
always @(posedge CLK) begin
if (F01_deq) ob_buf_t <= {F01_dot, ob_buf_t[`DRAMW-1:32]};
end
always @(posedge CLK) begin
if (RST) begin
ob_buf_t_cnt <= 0;
end else begin
if (F01_deq) ob_buf_t_cnt <= ob_buf_t_cnt + 1;
end
end
always @(posedge CLK) ob_enque <= (F01_deq && ob_buf_t_cnt == 15);
BFIFO #(`OB_SIZE, `DRAMW) OB(.CLK(CLK), .RST(RST), .enq(OB_enq), .deq(OB_deq),
.din(OB_din), .dot(OB_dot), .full(OB_full), .cnt(OB_cnt));
endmodule
/**************************************************************************************************/
module COMPARATOR #(parameter WIDTH = 32)
(input wire [WIDTH-1:0] DIN0,
input wire [WIDTH-1:0] DIN1,
output wire [WIDTH-1:0] DOUT0,
output wire [WIDTH-1:0] DOUT1);
wire comp_rslt = (DIN0 < DIN1);
function [WIDTH-1:0] mux;
input [WIDTH-1:0] a;
input [WIDTH-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
assign DOUT0 = mux(DIN1, DIN0, comp_rslt);
assign DOUT1 = mux(DIN0, DIN1, comp_rslt);
endmodule
/**************************************************************************************************/
module SORTINGNETWORK(input wire CLK,
input wire RST_IN,
input wire [`SORT_WAY:0] DATAEN_IN,
input wire [511:0] DIN_T,
output reg [511:0] DOUT,
output reg [`SORT_WAY:0] DATAEN_OUT);
reg RST;
reg [511:0] DIN;
reg [`SORT_WAY:0] DATAEN;
always @(posedge CLK) RST <= RST_IN;
always @(posedge CLK) DIN <= DIN_T;
always @(posedge CLK) DATAEN <= (RST) ? 0 : DATAEN_IN;
// Stage A
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] A15,A14,A13,A12,A11,A10,A09,A08,A07,A06,A05,A04,A03,A02,A01,A00; // output
wire [`WW] a15,a14,a13,a12,a11,a10,a09,a08,a07,a06,a05,a04,a03,a02,a01,a00; // input
assign {a15,a14,a13,a12,a11,a10,a09,a08,a07,a06,a05,a04,a03,a02,a01,a00} = DIN;
COMPARATOR comp00(a00, a01, A00, A01);
COMPARATOR comp01(a02, a03, A02, A03);
COMPARATOR comp02(a04, a05, A04, A05);
COMPARATOR comp03(a06, a07, A06, A07);
COMPARATOR comp04(a08, a09, A08, A09);
COMPARATOR comp05(a10, a11, A10, A11);
COMPARATOR comp06(a12, a13, A12, A13);
COMPARATOR comp07(a14, a15, A14, A15);
reg [511:0] pdA; // pipeline regester A for data
reg [`SORT_WAY:0] pcA; // pipeline regester A for control
always @(posedge CLK) pdA <= {A15,A14,A13,A12,A11,A10,A09,A08,A07,A06,A05,A04,A03,A02,A01,A00};
always @(posedge CLK) pcA <= (RST) ? 0 : DATAEN;
// Stage B
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] B15,B14,B13,B12,B11,B10,B09,B08,B07,B06,B05,B04,B03,B02,B01,B00; // output
wire [`WW] b15,b14,b13,b12,b11,b10,b09,b08,b07,b06,b05,b04,b03,b02,b01,b00; // input
assign {b15,b14,b13,b12,b11,b10,b09,b08,b07,b06,b05,b04,b03,b02,b01,b00} = pdA;
COMPARATOR comp10(b00, b02, B00, B02);
COMPARATOR comp11(b04, b06, B04, B06);
COMPARATOR comp12(b08, b10, B08, B10);
COMPARATOR comp13(b12, b14, B12, B14);
COMPARATOR comp14(b01, b03, B01, B03);
COMPARATOR comp15(b05, b07, B05, B07);
COMPARATOR comp16(b09, b11, B09, B11);
COMPARATOR comp17(b13, b15, B13, B15);
reg [511:0] pdB; // pipeline regester A for data
reg [`SORT_WAY:0] pcB; // pipeline regester A for control
always @(posedge CLK) pdB <= {B15,B14,B13,B12,B11,B10,B09,B08,B07,B06,B05,B04,B03,B02,B01,B00};
always @(posedge CLK) pcB <= (RST) ? 0 : pcA;
// Stage C
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] C15,C14,C13,C12,C11,C10,C09,C08,C07,C06,C05,C04,C03,C02,C01,C00; // output
wire [`WW] c15,c14,c13,c12,c11,c10,c09,c08,c07,c06,c05,c04,c03,c02,c01,c00; // input
assign {c15,c14,c13,c12,c11,c10,c09,c08,c07,c06,c05,c04,c03,c02,c01,c00} = pdB;
assign {C00,C03,C04,C07,C08,C11,C12,C15} = {c00,c03,c04,c07,c08,c11,c12,c15};
COMPARATOR comp20(c01, c02, C01, C02);
COMPARATOR comp21(c05, c06, C05, C06);
COMPARATOR comp22(c09, c10, C09, C10);
COMPARATOR comp23(c13, c14, C13, C14);
reg [511:0] pdC; // pipeline regester A for data
reg [`SORT_WAY:0] pcC; // pipeline regester A for control
always @(posedge CLK) pdC <= {C15,C14,C13,C12,C11,C10,C09,C08,C07,C06,C05,C04,C03,C02,C01,C00};
always @(posedge CLK) pcC <= (RST) ? 0 : pcB;
// Stage D
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] D15,D14,D13,D12,D11,D10,D09,D08,D07,D06,D05,D04,D03,D02,D01,D00; // output
wire [`WW] d15,d14,d13,d12,d11,d10,d09,d08,d07,d06,d05,d04,d03,d02,d01,d00; // input
assign {d15,d14,d13,d12,d11,d10,d09,d08,d07,d06,d05,d04,d03,d02,d01,d00} = pdC;
COMPARATOR comp30(d00, d04, D00, D04);
COMPARATOR comp31(d08, d12, D08, D12);
COMPARATOR comp32(d01, d05, D01, D05);
COMPARATOR comp33(d09, d13, D09, D13);
COMPARATOR comp34(d02, d06, D02, D06);
COMPARATOR comp35(d10, d14, D10, D14);
COMPARATOR comp36(d03, d07, D03, D07);
COMPARATOR comp37(d11, d15, D11, D15);
reg [511:0] pdD; // pipeline regester A for data
reg [`SORT_WAY:0] pcD; // pipeline regester A for control
always @(posedge CLK) pdD <= {D15,D14,D13,D12,D11,D10,D09,D08,D07,D06,D05,D04,D03,D02,D01,D00};
always @(posedge CLK) pcD <= (RST) ? 0 : pcC;
// Stage E
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] E15,E14,E13,E12,E11,E10,E09,E08,E07,E06,E05,E04,E03,E02,E01,E00; // output
wire [`WW] e15,e14,e13,e12,e11,e10,e09,e08,e07,e06,e05,e04,e03,e02,e01,e00; // input
assign {e15,e14,e13,e12,e11,e10,e09,e08,e07,e06,e05,e04,e03,e02,e01,e00} = pdD;
assign {E00,E01,E06,E07,E08,E09,E14,E15} = {e00,e01,e06,e07,e08,e09,e14,e15};
COMPARATOR comp40(e02, e04, E02, E04);
COMPARATOR comp41(e10, e12, E10, E12);
COMPARATOR comp42(e03, e05, E03, E05);
COMPARATOR comp43(e11, e13, E11, E13);
reg [511:0] pdE; // pipeline regester A for data
reg [`SORT_WAY:0] pcE; // pipeline regester A for control
always @(posedge CLK) pdE <= {E15,E14,E13,E12,E11,E10,E09,E08,E07,E06,E05,E04,E03,E02,E01,E00};
always @(posedge CLK) pcE <= (RST) ? 0 : pcD;
// Stage F
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] F15,F14,F13,F12,F11,F10,F09,F08,F07,F06,F05,F04,F03,F02,F01,F00; // output
wire [`WW] f15,f14,f13,f12,f11,f10,f09,f08,f07,f06,f05,f04,f03,f02,f01,f00; // input
assign {f15,f14,f13,f12,f11,f10,f09,f08,f07,f06,f05,f04,f03,f02,f01,f00} = pdE;
assign {F00,F07,F08,F15} = {f00,f07,f08,f15};
COMPARATOR comp50(f01, f02, F01, F02);
COMPARATOR comp51(f03, f04, F03, F04);
COMPARATOR comp52(f05, f06, F05, F06);
COMPARATOR comp53(f09, f10, F09, F10);
COMPARATOR comp54(f11, f12, F11, F12);
COMPARATOR comp55(f13, f14, F13, F14);
reg [511:0] pdF; // pipeline regester A for data
reg [`SORT_WAY:0] pcF; // pipeline regester A for control
always @(posedge CLK) pdF <= {F15,F14,F13,F12,F11,F10,F09,F08,F07,F06,F05,F04,F03,F02,F01,F00};
always @(posedge CLK) pcF <= (RST) ? 0 : pcE;
// Stage G
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] G15,G14,G13,G12,G11,G10,G09,G08,G07,G06,G05,G04,G03,G02,G01,G00; // output
wire [`WW] g15,g14,g13,g12,g11,g10,g09,g08,g07,g06,g05,g04,g03,g02,g01,g00; // input
assign {g15,g14,g13,g12,g11,g10,g09,g08,g07,g06,g05,g04,g03,g02,g01,g00} = pdF;
COMPARATOR comp60(g00, g08, G00, G08);
COMPARATOR comp61(g01, g09, G01, G09);
COMPARATOR comp62(g02, g10, G02, G10);
COMPARATOR comp63(g03, g11, G03, G11);
COMPARATOR comp64(g04, g12, G04, G12);
COMPARATOR comp65(g05, g13, G05, G13);
COMPARATOR comp66(g06, g14, G06, G14);
COMPARATOR comp67(g07, g15, G07, G15);
reg [511:0] pdG; // pipeline regester A for data
reg [`SORT_WAY:0] pcG; // pipeline regester A for control
always @(posedge CLK) pdG <= {G15,G14,G13,G12,G11,G10,G09,G08,G07,G06,G05,G04,G03,G02,G01,G00};
always @(posedge CLK) pcG <= (RST) ? 0 : pcF;
// Stage H
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] H15,H14,H13,H12,H11,H10,H09,H08,H07,H06,H05,H04,H03,H02,H01,H00; // output
wire [`WW] h15,h14,h13,h12,h11,h10,h09,h08,h07,h06,h05,h04,h03,h02,h01,h00; // input
assign {h15,h14,h13,h12,h11,h10,h09,h08,h07,h06,h05,h04,h03,h02,h01,h00} = pdG;
assign {H00,H01,H02,H03,H12,H13,H14,H15} = {h00,h01,h02,h03,h12,h13,h14,h15};
COMPARATOR comp70(h04, h08, H04, H08);
COMPARATOR comp71(h05, h09, H05, H09);
COMPARATOR comp72(h06, h10, H06, H10);
COMPARATOR comp73(h07, h11, H07, H11);
reg [511:0] pdH; // pipeline regester A for data
reg [`SORT_WAY:0] pcH; // pipeline regester A for control
always @(posedge CLK) pdH <= {H15,H14,H13,H12,H11,H10,H09,H08,H07,H06,H05,H04,H03,H02,H01,H00};
always @(posedge CLK) pcH <= (RST) ? 0 : pcG;
// Stage I
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] I15,I14,I13,I12,I11,I10,I09,I08,I07,I06,I05,I04,I03,I02,I01,I00; // output
wire [`WW] i15,i14,i13,i12,i11,i10,i09,i08,i07,i06,i05,i04,i03,i02,i01,i00; // input
assign {i15,i14,i13,i12,i11,i10,i09,i08,i07,i06,i05,i04,i03,i02,i01,i00} = pdH;
assign {I00,I01,I14,I15} = {i00,i01,i14,i15};
COMPARATOR comp80(i02, i04, I02, I04);
COMPARATOR comp81(i06, i08, I06, I08);
COMPARATOR comp82(i10, i12, I10, I12);
COMPARATOR comp83(i03, i05, I03, I05);
COMPARATOR comp84(i07, i09, I07, I09);
COMPARATOR comp85(i11, i13, I11, I13);
reg [511:0] pdI; // pipeline regester A for data
reg [`SORT_WAY:0] pcI; // pipeline regester A for control
always @(posedge CLK) pdI <= {I15,I14,I13,I12,I11,I10,I09,I08,I07,I06,I05,I04,I03,I02,I01,I00};
always @(posedge CLK) pcI <= (RST) ? 0 : pcH;
// Stage J
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] J15,J14,J13,J12,J11,J10,J09,J08,J07,J06,J05,J04,J03,J02,J01,J00; // output
wire [`WW] j15,j14,j13,j12,j11,j10,j09,j08,j07,j06,j05,j04,j03,j02,j01,j00; // input
assign {j15,j14,j13,j12,j11,j10,j09,j08,j07,j06,j05,j04,j03,j02,j01,j00} = pdI;
assign {J00,J15} = {j00,j15};
COMPARATOR comp90(j01, j02, J01, J02);
COMPARATOR comp91(j03, j04, J03, J04);
COMPARATOR comp92(j05, j06, J05, J06);
COMPARATOR comp93(j07, j08, J07, J08);
COMPARATOR comp94(j09, j10, J09, J10);
COMPARATOR comp95(j11, j12, J11, J12);
COMPARATOR comp96(j13, j14, J13, J14);
always @(posedge CLK) DOUT <= {J15,J14,J13,J12,J11,J10,J09,J08,J07,J06,J05,J04,J03,J02,J01,J00};
always @(posedge CLK) DATAEN_OUT <= (RST) ? 0 : pcI;
endmodule
/**************************************************************************************************/
/***** Xorshift *****/
/**************************************************************************************************/
module XORSHIFT #(parameter WIDTH = 32,
parameter SEED = 1)
(input wire CLK,
input wire RST,
input wire EN,
output wire [WIDTH-1:0] RAND_VAL);
reg [WIDTH-1:0] x;
reg [WIDTH-1:0] y;
reg [WIDTH-1:0] z;
reg [WIDTH-1:0] w;
wire [WIDTH-1:0] t = x^(x<<11);
// Mask MSB for not generating the maximum value
assign RAND_VAL = {1'b0, w[WIDTH-2:0]};
reg ocen;
always @(posedge CLK) ocen <= RST;
always @(posedge CLK) begin
if (RST) begin
x <= 123456789;
y <= 362436069;
z <= 521288629;
w <= 88675123 ^ SEED;
end else begin
if (EN || ocen) begin
x <= y;
y <= z;
z <= w;
w <= (w^(w>>19))^(t^(t>>8));
end
end
end
endmodule
/***** dummy logic *****/
/**************************************************************************************************/
module CORE_W(input wire CLK, // clock
input wire RST_in, // reset
output reg initdone, // dram initialize is done
output reg sortdone, // sort is finished
input wire d_busy_in, // DRAM busy
input wire [1:0] d_mode_in, // DRAM mode
input wire din_bit, // DRAM data out
input wire din_en_in, // DRAM data out enable
output reg [3:0] data_out, // DRAM data in
input wire d_w_in, // DRAM write flag
output reg [1:0] d_req, // DRAM REQ access request (read/write)
output reg [31:0] d_initadr, // DRAM REQ initial address for the access
output reg [31:0] d_blocks, // DRAM REQ the number of blocks per one access
output wire ERROR); //
reg RST; always @(posedge CLK) RST <= RST_in;
wire initdone_w; always @(posedge CLK) initdone <= initdone_w;
wire sortdone_w; always @(posedge CLK) sortdone <= sortdone_w;
reg d_busy; always @(posedge CLK) d_busy <= d_busy_in;
reg [1:0] d_mode; always @(posedge CLK) d_mode <= d_mode_in;
reg [`DRAMW-1:0] din; always @(posedge CLK) din <= (RST) ? 0 : {din[`DRAMW-2:0], din_bit};
reg din_en; always @(posedge CLK) din_en <= din_en_in;
wire [1:0] d_req_w; always @(posedge CLK) d_req <= d_req_w;
wire dout_en;
wire [`DRAMW-1:0] dout;
reg [`DRAMW-1:0] dout_r;
always @(posedge CLK) dout_r <= dout;
reg d_w; always @(posedge CLK) d_w <= d_w_in;
always @(posedge CLK) data_out <= {^dout_r[127:0], ^dout_r[128+127:128],
^dout_r[256+127:256], ^dout_r[384+127:384]};
wire [31:0] d_initadr_w, d_blocks_w;
always @(posedge CLK) d_initadr <= d_initadr_w;
always @(posedge CLK) d_blocks <= d_blocks_w;
CORE core(CLK, RST, initdone_w, sortdone_w,
d_busy, dout, d_w, din, din_en, d_req_w, d_initadr_w, d_blocks_w, ERROR);
endmodule
/***** Core User Logic *****/
/**************************************************************************************************/
module CORE(input wire CLK, // clock
input wire RST_IN, // reset
output reg initdone, // dram initialize is done
output reg sortdone, // sort is finished
input wire d_busy, // DRAM busy
output wire [`DRAMW-1:0] d_din, // DRAM data in
input wire d_w, // DRAM write flag
input wire [`DRAMW-1:0] d_dout, // DRAM data out
input wire d_douten, // DRAM data out enable
output reg [1:0] d_req, // DRAM REQ access request (read/write)
output reg [31:0] d_initadr, // DRAM REQ initial address for the access
output reg [31:0] d_blocks, // DRAM REQ the number of blocks per one access
output reg ERROR); // Sorting value ERROR ?
function [32-1:0] mux32;
input [32-1:0] a;
input [32-1:0] b;
input sel;
begin
case (sel)
1'b0: mux32 = a;
1'b1: mux32 = b;
endcase
end
endfunction
function [256-1:0] mux256;
input [256-1:0] a;
input [256-1:0] b;
input sel;
begin
case (sel)
1'b0: mux256 = a;
1'b1: mux256 = b;
endcase
end
endfunction
/**********************************************************************************************/
reg idone_a;
reg idone_b;
wire [`DRAMW-1:0] OB_dot;
wire OB_req;
wire OB_full;
reg [`DRAMW-1:0] dout_t, dout_ta, dout_tb, dout_tc, dout_td; //
reg doen_t, doen_ta, doen_tb, doen_tc, doen_td; //
reg [`SORT_WAY-1:0] req_tt; //
reg [`SORT_WAY-1:0] req_t; //
reg [`SORT_WAY-1:0] req; // use n-bit for n-way sorting, data read request from ways
reg [31:0] elem; // sorted elements in a phase
reg [`PHASE_W] phase; //
reg pchange; // phase_change to reset some registers
reg iter_done; //
reg [31:0] ecnt; // sorted elements in an iteration
reg irst; // INBUF reset
reg frst; // sort-tree FIFO reset
reg RST;
always @(posedge CLK) RST <= RST_IN;
/**********************************************************************************************/
wire [`SORTW-1:0] d00, d01, d02, d03, d04, d05, d06, d07, d08, d09, d10, d11, d12, d13, d14, d15;
wire [1:0] ib00_req, ib01_req, ib02_req, ib03_req, ib04_req, ib05_req, ib06_req, ib07_req, ib08_req, ib09_req, ib10_req, ib11_req, ib12_req, ib13_req, ib14_req, ib15_req;
wire F01_emp;
wire F01_deq = !F01_emp && !OB_full;
wire [`SORTW-1:0] F01_dot;
wire [`SORTW*`SORT_WAY-1:0] s_din = {d00, d01, d02, d03, d04, d05, d06, d07,
d08, d09, d10, d11, d12, d13, d14, d15};
wire [`SORT_WAY-1:0] enq;
wire [`SORT_WAY-1:0] s_ful;
wire [`DRAMW-1:0] stnet_dout;
wire [`SORT_WAY:0] stnet_douten;
SORTINGNETWORK sortingnetwork(CLK,
RST,
{req_t, doen_t},
dout_t,
stnet_dout,
stnet_douten);
INMOD2 im00(CLK, RST, dout_ta, doen_ta & req_tt[0], s_ful[0], d00, enq[0], ib00_req);
INMOD2 im01(CLK, RST, dout_ta, doen_ta & req_tt[1], s_ful[1], d01, enq[1], ib01_req);
INMOD2 im02(CLK, RST, dout_ta, doen_ta & req_tt[2], s_ful[2], d02, enq[2], ib02_req);
INMOD2 im03(CLK, RST, dout_ta, doen_ta & req_tt[3], s_ful[3], d03, enq[3], ib03_req);
INMOD2 im04(CLK, RST, dout_tb, doen_tb & req_tt[4], s_ful[4], d04, enq[4], ib04_req);
INMOD2 im05(CLK, RST, dout_tb, doen_tb & req_tt[5], s_ful[5], d05, enq[5], ib05_req);
INMOD2 im06(CLK, RST, dout_tb, doen_tb & req_tt[6], s_ful[6], d06, enq[6], ib06_req);
INMOD2 im07(CLK, RST, dout_tb, doen_tb & req_tt[7], s_ful[7], d07, enq[7], ib07_req);
INMOD2 im08(CLK, RST, dout_tc, doen_tc & req_tt[8], s_ful[8], d08, enq[8], ib08_req);
INMOD2 im09(CLK, RST, dout_tc, doen_tc & req_tt[9], s_ful[9], d09, enq[9], ib09_req);
INMOD2 im10(CLK, RST, dout_tc, doen_tc & req_tt[10], s_ful[10], d10, enq[10], ib10_req);
INMOD2 im11(CLK, RST, dout_tc, doen_tc & req_tt[11], s_ful[11], d11, enq[11], ib11_req);
INMOD2 im12(CLK, RST, dout_td, doen_td & req_tt[12], s_ful[12], d12, enq[12], ib12_req);
INMOD2 im13(CLK, RST, dout_td, doen_td & req_tt[13], s_ful[13], d13, enq[13], ib13_req);
INMOD2 im14(CLK, RST, dout_td, doen_td & req_tt[14], s_ful[14], d14, enq[14], ib14_req);
INMOD2 im15(CLK, RST, dout_td, doen_td & req_tt[15], s_ful[15], d15, enq[15], ib15_req);
STREE stree(CLK, RST, irst, frst, phase, s_din, enq, s_ful, F01_deq, F01_dot, F01_emp);
wire OB_deq = idone_a && d_w;
OTMOD ob(CLK, RST, F01_deq, F01_dot, OB_deq, OB_dot, OB_full, OB_req);
/********************************** Error Check ***********************************************/
generate
if (`INITTYPE=="reverse" || `INITTYPE=="sorted") begin
reg [`SORTW-1:0] check_cnt;
always @(posedge CLK) begin
if (RST) begin check_cnt<=1; ERROR<=0; end
if (phase==`LAST_PHASE && F01_deq) begin
if (check_cnt != F01_dot) begin
ERROR <= 1;
$write("Error in core.v: %d %d\n", F01_dot, check_cnt); // for simulation
$finish(); // for simulation
end
check_cnt <= check_cnt + 1;
end
end
end else if (`INITTYPE != "xorshift") begin
always @(posedge CLK) begin
ERROR <= 1;
// for simulation
$write("Error! INITTYPE is wrong.\n");
$write("Please make sure src/define.v\n");
$finish();
end
end
endgenerate
/***** dram READ/WRITE controller *****/
/**********************************************************************************************/
reg [31:0] w_addr; //
reg [2:0] state; // state
/********* generated by gen.c[2] ( 8-way): begin *********************************************/
reg [31:0] radr_a, radr_b, radr_c, radr_d, radr_e, radr_f, radr_g, radr_h, radr_i, radr_j, radr_k, radr_l, radr_m, radr_n, radr_o, radr_p;
reg [27:0] cnt_a, cnt_b, cnt_c, cnt_d, cnt_e, cnt_f, cnt_g, cnt_h, cnt_i, cnt_j, cnt_k, cnt_l, cnt_m, cnt_n, cnt_o, cnt_p;
reg c_a, c_b, c_c, c_d, c_e, c_f, c_g, c_h, c_i, c_j, c_k, c_l, c_m, c_n, c_o, c_p; // counter is full ?
always @(posedge CLK) begin
if (RST || pchange) begin // sortdone ??
if (RST) {initdone, state} <= 0;
if (RST) {d_req, d_initadr, d_blocks} <= 0;
req <= 0;
w_addr <= mux32((`SORT_ELM>>1), 0, phase[0]);
radr_a <= ((`SELM_PER_WAY>>3)*0);
radr_b <= ((`SELM_PER_WAY>>3)*1);
radr_c <= ((`SELM_PER_WAY>>3)*2);
radr_d <= ((`SELM_PER_WAY>>3)*3);
radr_e <= ((`SELM_PER_WAY>>3)*4);
radr_f <= ((`SELM_PER_WAY>>3)*5);
radr_g <= ((`SELM_PER_WAY>>3)*6);
radr_h <= ((`SELM_PER_WAY>>3)*7);
radr_i <= ((`SELM_PER_WAY>>3)*8);
radr_j <= ((`SELM_PER_WAY>>3)*9);
radr_k <= ((`SELM_PER_WAY>>3)*10);
radr_l <= ((`SELM_PER_WAY>>3)*11);
radr_m <= ((`SELM_PER_WAY>>3)*12);
radr_n <= ((`SELM_PER_WAY>>3)*13);
radr_o <= ((`SELM_PER_WAY>>3)*14);
radr_p <= ((`SELM_PER_WAY>>3)*15);
{cnt_a, cnt_b, cnt_c, cnt_d, cnt_e, cnt_f, cnt_g, cnt_h, cnt_i, cnt_j, cnt_k, cnt_l, cnt_m, cnt_n, cnt_o, cnt_p} <= 0;
{c_a, c_b, c_c, c_d, c_e, c_f, c_g, c_h, c_i, c_j, c_k, c_l, c_m, c_n, c_o, c_p} <= 0;
end else begin
case (state)
////////////////////////////////////////////////////////////////////////////////////////
0: begin ///// Initialize memory, write data to DRAM
if (d_req!=0) begin d_req<=0; state<=1; end
else if (!d_busy) begin
d_req <= `DRAM_REQ_WRITE; //
d_blocks <= (`SORT_ELM>>4); // 16word/block for VC_H07, 2word/b for Tokuden
d_initadr <= 0; //
end
end
/////////////////////////////////////////////////////////////////////////////////////
1: begin ///// request arbitration
if (!d_busy) begin
initdone<=1;
if (ib00_req[1] && !c_a) begin req<=16'h0001; state<=3; end // first priority
else if (ib01_req[1] && !c_b) begin req<=16'h0002; state<=3; end //
else if (ib02_req[1] && !c_c) begin req<=16'h0004; state<=3; end //
else if (ib03_req[1] && !c_d) begin req<=16'h0008; state<=3; end //
else if (ib04_req[1] && !c_e) begin req<=16'h0010; state<=3; end //
else if (ib05_req[1] && !c_f) begin req<=16'h0020; state<=3; end //
else if (ib06_req[1] && !c_g) begin req<=16'h0040; state<=3; end //
else if (ib07_req[1] && !c_h) begin req<=16'h0080; state<=3; end //
else if (ib08_req[1] && !c_i) begin req<=16'h0100; state<=3; end //
else if (ib09_req[1] && !c_j) begin req<=16'h0200; state<=3; end //
else if (ib10_req[1] && !c_k) begin req<=16'h0400; state<=3; end //
else if (ib11_req[1] && !c_l) begin req<=16'h0800; state<=3; end //
else if (ib12_req[1] && !c_m) begin req<=16'h1000; state<=3; end //
else if (ib13_req[1] && !c_n) begin req<=16'h2000; state<=3; end //
else if (ib14_req[1] && !c_o) begin req<=16'h4000; state<=3; end //
else if (ib15_req[1] && !c_p) begin req<=16'h8000; state<=3; end //
else state<=2;
end
end
/////////////////////////////////////////////////////////////////////////////////////
2: begin ///// request arbitration
if (!d_busy) begin
if (ib00_req[0] && !c_a) begin req<=16'h0001; state<=3; end // second priority
else if (ib01_req[0] && !c_b) begin req<=16'h0002; state<=3; end //
else if (ib02_req[0] && !c_c) begin req<=16'h0004; state<=3; end //
else if (ib03_req[0] && !c_d) begin req<=16'h0008; state<=3; end //
else if (ib04_req[0] && !c_e) begin req<=16'h0010; state<=3; end //
else if (ib05_req[0] && !c_f) begin req<=16'h0020; state<=3; end //
else if (ib06_req[0] && !c_g) begin req<=16'h0040; state<=3; end //
else if (ib07_req[0] && !c_h) begin req<=16'h0080; state<=3; end //
else if (ib08_req[0] && !c_i) begin req<=16'h0100; state<=3; end //
else if (ib09_req[0] && !c_j) begin req<=16'h0200; state<=3; end //
else if (ib10_req[0] && !c_k) begin req<=16'h0400; state<=3; end //
else if (ib11_req[0] && !c_l) begin req<=16'h0800; state<=3; end //
else if (ib12_req[0] && !c_m) begin req<=16'h1000; state<=3; end //
else if (ib13_req[0] && !c_n) begin req<=16'h2000; state<=3; end //
else if (ib14_req[0] && !c_o) begin req<=16'h4000; state<=3; end //
else if (ib15_req[0] && !c_p) begin req<=16'h8000; state<=3; end //
else if (OB_req) begin state<=4; end // WRITE
end
end
/////////////////////////////////////////////////////////////////////////////////////
3: begin ///// READ data from DRAM
if (d_req!=0) begin d_req<=0; state<=1; end
else if (!d_busy) begin
case (req)
16'h0001: begin
d_initadr <= mux32(radr_a, (radr_a | (`SORT_ELM>>1)), phase[0]);
radr_a <= radr_a+(`D_RS);
cnt_a <= cnt_a+1;
c_a <= (cnt_a>=`WAY_CN_);
end
16'h0002: begin
d_initadr <= mux32(radr_b, (radr_b | (`SORT_ELM>>1)), phase[0]);
radr_b <= radr_b+(`D_RS);
cnt_b <= cnt_b+1;
c_b <= (cnt_b>=`WAY_CN_);
end
16'h0004: begin
d_initadr <= mux32(radr_c, (radr_c | (`SORT_ELM>>1)), phase[0]);
radr_c <= radr_c+(`D_RS);
cnt_c <= cnt_c+1;
c_c <= (cnt_c>=`WAY_CN_);
end
16'h0008: begin
d_initadr <= mux32(radr_d, (radr_d | (`SORT_ELM>>1)), phase[0]);
radr_d <= radr_d+(`D_RS);
cnt_d <= cnt_d+1;
c_d <= (cnt_d>=`WAY_CN_);
end
16'h0010: begin
d_initadr <= mux32(radr_e, (radr_e | (`SORT_ELM>>1)), phase[0]);
radr_e <= radr_e+(`D_RS);
cnt_e <= cnt_e+1;
c_e <= (cnt_e>=`WAY_CN_);
end
16'h0020: begin
d_initadr <= mux32(radr_f, (radr_f | (`SORT_ELM>>1)), phase[0]);
radr_f <= radr_f+(`D_RS);
cnt_f <= cnt_f+1;
c_f <= (cnt_f>=`WAY_CN_);
end
16'h0040: begin
d_initadr <= mux32(radr_g, (radr_g | (`SORT_ELM>>1)), phase[0]);
radr_g <= radr_g+(`D_RS);
cnt_g <= cnt_g+1;
c_g <= (cnt_g>=`WAY_CN_);
end
16'h0080: begin
d_initadr <= mux32(radr_h, (radr_h | (`SORT_ELM>>1)), phase[0]);
radr_h <= radr_h+(`D_RS);
cnt_h <= cnt_h+1;
c_h <= (cnt_h>=`WAY_CN_);
end
16'h0100: begin
d_initadr <= mux32(radr_i, (radr_i | (`SORT_ELM>>1)), phase[0]);
radr_i <= radr_i+(`D_RS);
cnt_i <= cnt_i+1;
c_i <= (cnt_i>=`WAY_CN_);
end
16'h0200: begin
d_initadr <= mux32(radr_j, (radr_j | (`SORT_ELM>>1)), phase[0]);
radr_j <= radr_j+(`D_RS);
cnt_j <= cnt_j+1;
c_j <= (cnt_j>=`WAY_CN_);
end
16'h0400: begin
d_initadr <= mux32(radr_k, (radr_k | (`SORT_ELM>>1)), phase[0]);
radr_k <= radr_k+(`D_RS);
cnt_k <= cnt_k+1;
c_k <= (cnt_k>=`WAY_CN_);
end
16'h0800: begin
d_initadr <= mux32(radr_l, (radr_l | (`SORT_ELM>>1)), phase[0]);
radr_l <= radr_l+(`D_RS);
cnt_l <= cnt_l+1;
c_l <= (cnt_l>=`WAY_CN_);
end
16'h1000: begin
d_initadr <= mux32(radr_m, (radr_m | (`SORT_ELM>>1)), phase[0]);
radr_m <= radr_m+(`D_RS);
cnt_m <= cnt_m+1;
c_m <= (cnt_m>=`WAY_CN_);
end
16'h2000: begin
d_initadr <= mux32(radr_n, (radr_n | (`SORT_ELM>>1)), phase[0]);
radr_n <= radr_n+(`D_RS);
cnt_n <= cnt_n+1;
c_n <= (cnt_n>=`WAY_CN_);
end
16'h4000: begin
d_initadr <= mux32(radr_o, (radr_o | (`SORT_ELM>>1)), phase[0]);
radr_o <= radr_o+(`D_RS);
cnt_o <= cnt_o+1;
c_o <= (cnt_o>=`WAY_CN_);
end
16'h8000: begin
d_initadr <= mux32(radr_p, (radr_p | (`SORT_ELM>>1)), phase[0]);
radr_p <= radr_p+(`D_RS);
cnt_p <= cnt_p+1;
c_p <= (cnt_p>=`WAY_CN_);
end
endcase
d_req <= `DRAM_REQ_READ;
d_blocks <= `DRAM_RBLOCKS;
req_t <= req;
end
end
////////////////////////////////////////////////////////////////////////////////////////
4: begin ///// WRITE data to DRAM
if (d_req!=0) begin d_req<=0; state<=1; end
else if (!d_busy) begin
d_req <= `DRAM_REQ_WRITE;
d_blocks <= `DRAM_WBLOCKS;
d_initadr <= w_addr;
w_addr <= w_addr + (`D_WS); // address for the next write
end
end
////////////////////////////////////////////////////////////////////////////////////////
endcase
end
end
/***** WRITE : feed the initial data to be stored to DRAM *****/
/**********************************************************************************************/
reg RST_INI; // reset signal for value initialization module
always @(posedge CLK) RST_INI <= RST;
reg [`SORTW-1:0] i_p,i_o,i_n,i_m,i_l,i_k,i_j,i_i,i_h,i_g,i_f,i_e,i_d,i_c,i_b,i_a;
generate
if (`INITTYPE == "xorshift") begin
wire [`SORTW-1:0] r15,r14,r13,r12,r11,r10,r09,r08,r07,r06,r05,r04,r03,r02,r01,r00;
XORSHIFT #(`SORTW, 32'h00000001) xorshift00(CLK, RST_INI, d_w, r00);
XORSHIFT #(`SORTW, 32'h00000002) xorshift01(CLK, RST_INI, d_w, r01);
XORSHIFT #(`SORTW, 32'h00000004) xorshift02(CLK, RST_INI, d_w, r02);
XORSHIFT #(`SORTW, 32'h00000008) xorshift03(CLK, RST_INI, d_w, r03);
XORSHIFT #(`SORTW, 32'h00000010) xorshift04(CLK, RST_INI, d_w, r04);
XORSHIFT #(`SORTW, 32'h00000020) xorshift05(CLK, RST_INI, d_w, r05);
XORSHIFT #(`SORTW, 32'h00000040) xorshift06(CLK, RST_INI, d_w, r06);
XORSHIFT #(`SORTW, 32'h00000080) xorshift07(CLK, RST_INI, d_w, r07);
XORSHIFT #(`SORTW, 32'h00000100) xorshift08(CLK, RST_INI, d_w, r08);
XORSHIFT #(`SORTW, 32'h00000200) xorshift09(CLK, RST_INI, d_w, r09);
XORSHIFT #(`SORTW, 32'h00000400) xorshift10(CLK, RST_INI, d_w, r10);
XORSHIFT #(`SORTW, 32'h00000800) xorshift11(CLK, RST_INI, d_w, r11);
XORSHIFT #(`SORTW, 32'h00001000) xorshift12(CLK, RST_INI, d_w, r12);
XORSHIFT #(`SORTW, 32'h00002000) xorshift13(CLK, RST_INI, d_w, r13);
XORSHIFT #(`SORTW, 32'h00004000) xorshift14(CLK, RST_INI, d_w, r14);
XORSHIFT #(`SORTW, 32'h00008000) xorshift15(CLK, RST_INI, d_w, r15);
always @(posedge CLK) begin
i_a <= r00;
i_b <= r01;
i_c <= r02;
i_d <= r03;
i_e <= r04;
i_f <= r05;
i_g <= r06;
i_h <= r07;
i_i <= r08;
i_j <= r09;
i_k <= r10;
i_l <= r11;
i_m <= r12;
i_n <= r13;
i_o <= r14;
i_p <= r15;
end
end else if (`INITTYPE == "reverse") begin
always @(posedge CLK) begin
if (RST_INI) begin
i_a <= `SORT_ELM+16;
i_b <= `SORT_ELM+16-1;
i_c <= `SORT_ELM+16-2;
i_d <= `SORT_ELM+16-3;
i_e <= `SORT_ELM+16-4;
i_f <= `SORT_ELM+16-5;
i_g <= `SORT_ELM+16-6;
i_h <= `SORT_ELM+16-7;
i_i <= `SORT_ELM+16-8;
i_j <= `SORT_ELM+16-9;
i_k <= `SORT_ELM+16-10;
i_l <= `SORT_ELM+16-11;
i_m <= `SORT_ELM+16-12;
i_n <= `SORT_ELM+16-13;
i_o <= `SORT_ELM+16-14;
i_p <= `SORT_ELM+16-15;
end else begin
if (d_w) begin
i_a <= i_a-16;
i_b <= i_b-16;
i_c <= i_c-16;
i_d <= i_d-16;
i_e <= i_e-16;
i_f <= i_f-16;
i_g <= i_g-16;
i_h <= i_h-16;
i_i <= i_i-16;
i_j <= i_j-16;
i_k <= i_k-16;
i_l <= i_l-16;
i_m <= i_m-16;
i_n <= i_n-16;
i_o <= i_o-16;
i_p <= i_p-16;
end
end
end
end else if (`INITTYPE == "sorted") begin
reg ocen;
always @(posedge CLK) begin
if (RST_INI) begin
ocen <= 0;
i_a <= 1;
i_b <= 2;
i_c <= 3;
i_d <= 4;
i_e <= 5;
i_f <= 6;
i_g <= 7;
i_h <= 8;
i_i <= 9;
i_j <= 10;
i_k <= 11;
i_l <= 12;
i_m <= 13;
i_n <= 14;
i_o <= 15;
i_p <= 16;
end else begin
if (d_w) begin
ocen <= 1;
i_a <= mux32(i_a, i_a+16, ocen);
i_b <= mux32(i_b, i_b+16, ocen);
i_c <= mux32(i_c, i_c+16, ocen);
i_d <= mux32(i_d, i_d+16, ocen);
i_e <= mux32(i_e, i_e+16, ocen);
i_f <= mux32(i_f, i_f+16, ocen);
i_g <= mux32(i_g, i_g+16, ocen);
i_h <= mux32(i_h, i_h+16, ocen);
i_i <= mux32(i_i, i_i+16, ocen);
i_j <= mux32(i_j, i_j+16, ocen);
i_k <= mux32(i_k, i_k+16, ocen);
i_l <= mux32(i_l, i_l+16, ocen);
i_m <= mux32(i_m, i_m+16, ocen);
i_n <= mux32(i_n, i_n+16, ocen);
i_o <= mux32(i_o, i_o+16, ocen);
i_p <= mux32(i_p, i_p+16, ocen);
end
end
end
end
endgenerate
always @(posedge CLK) idone_a <= initdone;
always @(posedge CLK) idone_b <= initdone;
assign d_din[255: 0] = mux256({i_h,i_g,i_f,i_e,i_d,i_c,i_b,i_a}, OB_dot[255: 0], idone_a);
assign d_din[511:256] = mux256({i_p,i_o,i_n,i_m,i_l,i_k,i_j,i_i}, OB_dot[511:256], idone_b);
/**********************************************************************************************/
always @(posedge CLK) begin
dout_t <= d_dout;
doen_t <= d_douten;
// Stage 0
////////////////////////////////////
dout_ta <= stnet_dout;
dout_tb <= stnet_dout;
dout_tc <= stnet_dout;
dout_td <= stnet_dout;
doen_ta <= stnet_douten[0];
doen_tb <= stnet_douten[0];
doen_tc <= stnet_douten[0];
doen_td <= stnet_douten[0];
req_tt <= stnet_douten[`SORT_WAY:1];
end
// for phase
// ###########################################################################
always @(posedge CLK) begin
if (RST) begin
phase <= 0;
end else begin
if (elem==`SORT_ELM) phase <= phase+1;
end
end
// for elem
// ###########################################################################
always @(posedge CLK) begin
if (RST) begin
elem <= 0;
end else begin
case ({OB_deq, (elem==`SORT_ELM)})
2'b01: elem <= 0;
2'b10: elem <= elem + 16;
endcase
end
end
// for iter_done
// ###########################################################################
always @(posedge CLK) iter_done <= (ecnt==2);
// for pchange
// ###########################################################################
always @(posedge CLK) pchange <= (elem==`SORT_ELM);
// for irst
// ###########################################################################
always @(posedge CLK) irst <= (ecnt==2) || pchange;
// for frst
// ###########################################################################
always @(posedge CLK) frst <= RST || (ecnt==2) || (elem==`SORT_ELM);
// for ecnt
// ###########################################################################
always @(posedge CLK) begin
if (RST || iter_done || pchange) begin
ecnt <= ((`ELEMS_PER_UNIT<<`WAY_LOG) << (phase * `WAY_LOG));
end else begin
if (ecnt!=0 && F01_deq) ecnt <= ecnt - 1;
end
end
// for sortdone
// ###########################################################################
always @(posedge CLK) begin
if (RST) begin
sortdone <= 0;
end else begin
if (phase==(`LAST_PHASE+1)) sortdone <= 1;
end
end
endmodule
/**************************************************************************************************/
`default_nettype wire
|
module top (
input clk_12mhz,
btn1, btn2,
rpi_ice_mosi, rpi_ice_miso, rpi_ice_clk, rpi_ice_ss,
output reg led1, led2, led3, pmod1_1, pmod1_2,
pmod4_1, pmod4_2, pmod4_3, pmod4_4,
pmod4_9, pmod4_10, pmod4_11, pmod4_12,
// output reg [31:0] P6,
// output reg [31:0] P8,
// memory interface to SRAM on back side of the board
// output n_mem_CE, n_mem_WE, n_mem_OE, n_mem_LB, n_mem_UB,
output [15:0] mem_data
// output [15:0] mem_data // set to IO by SB_IO primitive */
);
// (external) SRAM memory interface
/* wire [15:0] mem_data_in;
wire [15:0] mem_data_out;
wire [15:0] mem_data_oe;
SB_IO #(
.PIN_TYPE(6'b 1010_01),
.PULLUP (1'b 0)
) tristate_io [15:0] (
.PACKAGE_PIN (mem_data),
.OUTPUT_ENABLE(mem_data_oe),
.D_OUT_0 (mem_data_out),
.D_IN_0 (mem_data_in)
);
reg [16:0] r_address = 0;
wire [7:0] r_data;
reg [0:0] r_request = 0;
wire [0:0] r_started;
wire [0:0] r_done;
reg [16:0] w_address = 0;
reg [7:0] w_data = 0;
reg [0:0] w_request = 0;
wire [0:0] w_started;
wire [0:0] w_done;
wire [15:0] hw_address;
wire [0:0] hw_n_cs;
wire [0:0] hw_n_we;
wire [0:0] hw_n_oe;
wire [0:0] hw_n_ub;
wire [0:0] hw_n_lb;
wire [15:0] hw_data_out;
wire [0:0] hw_data_oe;
RAM_IS61WV6416BLL memory(
.clk(clk), .n_reset(resetn),
.w_address(w_address), .w_data(w_data),
.w_request(w_request), .r_started(r_started), .w_done(w_done),
.r_address(r_address), .r_data(r_data),
.r_request(r_request), .w_started(w_started), .r_done(r_done),
.hw_n_cs(hw_n_cs), .hw_n_we(hw_n_we), .hw_n_oe(hw_n_oe),
.hw_n_ub(hw_n_ub), .hw_n_lb(hw_n_lb),
.hw_address (hw_address),
.hw_data_in (mem_data_in),
.hw_data_out (hw_data_out),
.hw_data_oe (hw_data_oe));
assign mem_data_out = hw_data_out;
assign mem_data_oe = hw_data_oe && btn1; // safety measure, set port to output
// only as long as btn1 is pressed
assign mem_addr = hw_address;
assign n_mem_CE = hw_n_cs;
assign n_mem_OE = hw_n_oe;
assign n_mem_WE = hw_n_we;
assign n_mem_UB = hw_n_ub;
assign n_mem_LB = hw_n_lb;
// */
// block ram instantiation
parameter ADDR_WIDTH = 14;
parameter DATA_WIDTH = 8;
reg [7:0] data_in = 0;
reg [ADDR_WIDTH-1:0] addr_in = 12;
reg [ADDR_WIDTH-1:0] addr_out = 0;
wire [7:0] data_out;
bram #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH))
memory_inst (.clk(clk), .read(), .write(), .addr_in(addr_in), .data_in(data_in), .addr_out(addr_out), .data_out(data_out));
// Clock Generation
localparam FCLK = 17000000; // required for several timing calculations, depends
wire [0:0] pll_locked; // on pll_config.v content which is generated using
wire [0:0] clk_pll; // icepll -mf pll_config.v -o 17
pll pll_inst (.clock_in (clk_12mhz), .clock_out(clk_pll), .locked(pll_locked));
wire [0:0] clk; // clock actually used
// assign clk = clk_pll; // use pll generated clock (regular mode)
assign clk = clk_12mhz; // use clock directly (for use within testbench)
// Reset Generator
reg [3:0] resetn_gen = 0;
reg [0:0] resetn;
always @(posedge clk) begin
resetn <= &resetn_gen;
resetn_gen <= {resetn_gen[2:0], pll_locked};
end
// FPS-clock
localparam FPS = 20;
reg [0:0] fps_clk;
clk_gen #(.CLK_CYCLES(FCLK / FPS)) fps_clk_inst (.clk(clk), .resetn(resetn), .clk_out(fps_clk));
// ws2812b output
localparam STRIPE_COUNT = 3;
localparam LEDCOUNT = 2;
reg [$clog2(LEDCOUNT)-1:0] LED_counter = 0;
wire [0:0] bitstream_read;
reg [0:0] bitstream_available = 0;
reg [0:0] start = 0;
reg [0:0] next_LED = 0;
reg [24*STRIPE_COUNT-1:0] bitstream;
reg [$clog2(STRIPE_COUNT-1):0] next_byte_to_read;
// generation of the bitstream
always @(posedge clk) begin
if (!resetn) begin
LED_counter <= 0;
start <= 0;
next_LED <= 0;
bitstream_available <= 0;
end else begin
if (start) begin
start <= 0;
bitstream_available <= 0;
next_LED <= 1;
next_byte_to_read <= 0;
end
if (next_LED && (bitstream_read || (next_byte_to_read < STRIPE_COUNT*3))) begin
// build bitstream for next LEDs
if (next_byte_to_read < STRIPE_COUNT*3) begin
next_byte_to_read <= next_byte_to_read + 1;
end else begin
next_byte_to_read <= 0;
next_LED <= 0;
bitstream_available <= 1;
LED_counter <= LED_counter - 1;
end
addr_out <= next_byte_to_read;
bitstream <= {bitstream[24*STRIPE_COUNT-1:8], data_out};
// build bitstream for next LED
/* bitstream <= 2*{2'b0, green_int[0], 5'b0,
2'b0, red_int[0], 5'b0,
2'b0, blue_int[0], 5'b0};// */
end
if (fps_clk) begin // & !LED_counter) begin
// after sending all LEDs wait for the fps_clk signal
LED_counter <= LEDCOUNT;
start <= 1;
end
end
end
// actual output of the bitstream
wire [STRIPE_COUNT-1:0] ws2812b_data;
wire [3:0] ws2812b_debug_info;
ws2812b_out_parallel_module #(
// ws2812b_out_module #(
.STRIPECOUNT (STRIPE_COUNT),
.CYCLES_SHORT (FCLK/2500000), // ~0.4 us
.CYCLES_LONG (FCLK/1250000), // ~0.8 us
.CYCLES_RET (0)) // ~50 us, but realized using clk_fps
ws2812b_out_inst (
.clk (clk),
.resetn (resetn),
.bitstream_available (bitstream_available),
.bitstream (bitstream),
.bitstream_read (bitstream_read),
.ws2812b_data (ws2812b_data),
.ws2812b_data (pmod1_2),
.debug_info (ws2812b_debug_info)
);
// assign pmod1_1 = pmod1_2;
assign pmod1_1 = ws2812b_data[0];
assign pmod1_2 = ws2812b_data[1];
reg [3:0] mem_dbgout;
reg [0:0] mem_dbgclk;
reg [4:0] mem_dbgcnt;
reg [31:0] mem_dbgbuf;
always @(posedge clk) begin
if (!resetn) begin
mem_dbgcnt <= 0;
mem_dbgclk <= 0;
mem_dbgout <= 0;
// end else if (debugdooutput) begin
end else if (fps_clk) begin
mem_dbgbuf <= spi_buffer;
// mem_dbgbuf <= 32'h1248;
mem_dbgcnt <= 1;
mem_dbgout <= 15;
end else if ((|mem_dbgcnt) && (mem_dbgcnt < 9)) begin
mem_dbgcnt <= mem_dbgcnt + 1;
mem_dbgclk <= mem_dbgcnt[0];
mem_dbgout <= mem_dbgbuf[3:0];
mem_dbgbuf <= {mem_dbgbuf[3:0], mem_dbgbuf[31:4]};
end else begin
mem_dbgcnt <= 0;
mem_dbgclk <= 0;
mem_dbgout <= 0;
end
end
// instantiation of a SPI slave
localparam CPOL = 0;
localparam CPHA = 0;
localparam LSBFIRST = 0;
localparam TIMEOUT__NOT_CS = 1; // 0: use CS, 1: use timeout
localparam SPI_TIMEOUT_us = 1000; // when to finish a transmitted frame
wire [7:0] spi_value;
wire [7:0] spi_debug_info;
wire [0:0] spi_first_byte;
wire [0:0] spi_done;
wire [0:0] spi_timeout;
reg [31:0] spi_buffer;
always @(posedge clk) begin
if (!resetn) begin
end
else begin
// blockram variant
if (spi_done) begin
data_in <= spi_value;
addr_in <= addr_in + 1;
end else if (spi_timeout) begin
addr_in <= 2**ADDR_WIDTH-1;
end
// external SRAM variant
/* if (spi_done) begin
w_data <= spi_value;
w_address <= 0;
w_request <= 1;
end else if (w_done) begin
w_request <= 0;
w_address <= w_address + 1;
addr_in <= addr_out +1;
end else if (spi_timeout) begin
w_address <= 0;
addr_in <= 0;
end // */
/* if (spi_done) begin
spi_buffer <= {spi_buffer[23:0], spi_value};
end
if (spi_timeout) begin
green[ 7: 0] <= spi_buffer[ 7: 0];
blue [15: 8] <= spi_buffer[15: 8];
green[23:16] <= spi_buffer[23:15];
blue [31:24] <= spi_buffer[31:24];
end // */
end
end
spi_slave #(.CPOL (CPOL),
.CPHA (CPHA),
.LSBFIRST (LSBFIRST),
.TIMEOUT__NOT_CS(1-TIMEOUT__NOT_CS),
.TIMEOUT_CYCLES ((FCLK * SPI_TIMEOUT_us) / 1000000))
spi_slave_int (.clk (clk),
.resetn (resetn),
.spi_clk (rpi_ice_clk),
.spi_mosi (rpi_ice_mosi),
.spi_cs (rpi_ice_ss),
.read_value (spi_value),
.done (spi_done),
.timeout_expired (spi_timeout),
.first_byte (spi_first_byte),
.debug_info (spi_debug_info)
);
reg [7:0] last_spi_value;
reg [0:0] ram_read_step;
always @(posedge clk) begin
if (fps_clk) begin
// alternatively writing to RAM and output from there
addr_out <= 0;
ram_read_step <= 1;
end
if (ram_read_step == 1) begin
last_spi_value <= data_out;
end
end
assign {pmod4_12, pmod4_11, pmod4_10, pmod4_9,
pmod4_4, pmod4_3, pmod4_2, pmod4_1} = //debug_info;
// {ws2812b_debug_info,
// {start, |next_byte_to_read, next_byte_to_read[1:0],
// {start, next_byte_to_read[2:0],
// {bitstream_read, start, bitstream_available, next_LED,
// {spi_debug_info[3:0],
// {spi_debug_info[7:4],
// {spi_value[3:0],
{spi_done, last_spi_value[2:0],
// {spi_first_byte, rpi_ice_ss, mem_dbgcnt[1:0],
// {n_mem_CE, n_mem_OE, n_mem_WE, btn2,
// {w_done, w_request, r_done, r_request,
// {mem_dbgout[2:0], pmod1_2,
// {mem_dbgcnt,
// {data_out[3:0],
// {mem_addr[3:0],
// {mem_data_in[7:4],
// {w_request, w_started, r_request, r_started,
// {hw_n_oe, hw_n_cs, r_started, r_request,
// {0, 0, fps_clk, pmod1_1,
// r_done || w_done, rpi_ice_mosi, rpi_ice_clk, resetn};
// pmod1_1, rpi_ice_mosi, rpi_ice_clk, resetn};
pmod1_1, rpi_ice_mosi, rpi_ice_clk, rpi_ice_ss};
assign mem_data = {8'b0, last_spi_value};
// assign {n_mem_CE, n_mem_WE, n_mem_LB, n_mem_UB, n_mem_OE} = {last_spi_value[4:0]};
// assign pins to value of leds
// assign {led3, led2, led1} = {rpi_ice_ss, rpi_ice_ss, fps_clk};
assign {led3, led2, led1} = last_spi_value[2:0];
endmodule
|
//////////////////////////////////////////////////////////////////////////////
//name : server
//input : input_eth_rx:16
//input : input_socket:16
//output : output_socket:16
//output : output_eth_tx:16
//source_file : ../source/server.c
///======
///
///Created by C2CHIP
//////////////////////////////////////////////////////////////////////////////
// Register Allocation
// ===================
// Register Name Size
// 0 put_eth return address 2
// 1 variable i 2
// 2 put_socket return address 2
// 3 variable i 2
// 4 get_eth return address 2
// 5 variable get_eth return value 2
// 6 rdy_eth return address 2
// 7 variable rdy_eth return value 2
// 8 get_socket return address 2
// 9 variable get_socket return value 2
// 10 array 2
// 11 variable checksum 4
// 12 reset_checksum return address 2
// 13 add_checksum return address 2
// 14 variable data 2
// 15 check_checksum return address 2
// 16 variable check_checksum return value 2
// 17 calc_ack return address 2
// 18 variable calc_ack return value 2
// 19 array 2
// 20 array 2
// 21 variable length 2
// 22 variable new_ack_0 2
// 23 variable new_ack_1 2
// 24 variable return_value 2
// 25 put_ethernet_packet return address 2
// 26 array 2
// 27 variable number_of_bytes 2
// 28 variable destination_mac_address_hi 2
// 29 variable destination_mac_address_med 2
// 30 variable destination_mac_address_lo 2
// 31 variable protocol 2
// 32 variable byte 2
// 33 variable index 2
// 34 get_ethernet_packet return address 2
// 35 variable get_ethernet_packet return value 2
// 36 array 2
// 37 variable number_of_bytes 2
// 38 variable index 2
// 39 variable byte 2
// 40 array 2
// 41 array 2
// 42 array 2
// 43 array 2
// 44 array 2
// 45 variable arp_pounsigneder 2
// 46 get_arp_cache return address 2
// 47 variable get_arp_cache return value 2
// 48 variable ip_hi 2
// 49 variable ip_lo 2
// 50 variable number_of_bytes 2
// 51 variable byte 2
// 52 array 2
// 53 variable i 2
// 54 put_ip_packet return address 2
// 55 array 2
// 56 variable total_length 2
// 57 variable protocol 2
// 58 variable ip_hi 2
// 59 variable ip_lo 2
// 60 variable number_of_bytes 2
// 61 variable i 2
// 62 variable arp_cache 2
// 63 get_ip_packet return address 2
// 64 variable get_ip_packet return value 2
// 65 array 2
// 66 variable total_length 2
// 67 variable header_length 2
// 68 variable payload_start 2
// 69 variable payload_length 2
// 70 variable i 2
// 71 variable from 2
// 72 variable to 2
// 73 variable payload_end 2
// 74 variable number_of_bytes 2
// 75 variable remote_ip_hi 2
// 76 variable remote_ip_lo 2
// 77 variable tx_source 2
// 78 variable tx_dest 2
// 79 array 2
// 80 array 2
// 81 array 2
// 82 variable tx_window 2
// 83 variable tx_fin_flag 2
// 84 variable tx_syn_flag 2
// 85 variable tx_rst_flag 2
// 86 variable tx_psh_flag 2
// 87 variable tx_ack_flag 2
// 88 variable tx_urg_flag 2
// 89 variable rx_source 2
// 90 variable rx_dest 2
// 91 array 2
// 92 array 2
// 93 variable rx_fin_flag 2
// 94 variable rx_syn_flag 2
// 95 variable rx_rst_flag 2
// 96 variable rx_ack_flag 2
// 97 put_tcp_packet return address 2
// 98 array 2
// 99 variable tx_length 2
// 100 variable payload_start 2
// 101 variable packet_length 2
// 102 variable index 2
// 103 variable i 2
// 104 variable rx_length 2
// 105 variable rx_start 2
// 106 get_tcp_packet return address 2
// 107 variable get_tcp_packet return value 2
// 108 array 2
// 109 variable number_of_bytes 2
// 110 variable header_length 2
// 111 variable payload_start 2
// 112 variable total_length 2
// 113 variable payload_length 2
// 114 variable tcp_header_length 2
// 115 application_put_data return address 2
// 116 array 2
// 117 variable start 2
// 118 variable length 2
// 119 variable i 2
// 120 variable index 2
// 121 application_get_data return address 2
// 122 variable application_get_data return value 2
// 123 array 2
// 124 variable start 2
// 125 variable i 2
// 126 variable index 2
// 127 variable length 2
// 128 server return address 2
// 129 array 2
// 130 array 2
// 131 variable tx_start 2
// 132 variable tx_length 2
// 133 variable timeout 2
// 134 variable resend_wait 2
// 135 variable bytes 2
// 136 variable index 2
// 137 variable last_state 2
// 138 variable new_rx_data 2
// 139 variable state 2
// 140 temporary_register 2
// 141 temporary_register 2
// 142 temporary_register 2
// 143 temporary_register 4
// 144 temporary_register 4
// 145 temporary_register 4
// 146 temporary_register 2
// 147 temporary_register 2
// 148 temporary_register 1024
// 149 temporary_register 2
// 150 temporary_register 2
// 151 temporary_register 2048
module server(input_eth_rx,input_socket,input_eth_rx_stb,input_socket_stb,output_socket_ack,output_eth_tx_ack,clk,rst,output_socket,output_eth_tx,output_socket_stb,output_eth_tx_stb,input_eth_rx_ack,input_socket_ack);
integer file_count;
real fp_value;
input [15:0] input_eth_rx;
input [15:0] input_socket;
input input_eth_rx_stb;
input input_socket_stb;
input output_socket_ack;
input output_eth_tx_ack;
input clk;
input rst;
output [15:0] output_socket;
output [15:0] output_eth_tx;
output output_socket_stb;
output output_eth_tx_stb;
output input_eth_rx_ack;
output input_socket_ack;
reg [15:0] timer;
reg timer_enable;
reg stage_0_enable;
reg stage_1_enable;
reg stage_2_enable;
reg [11:0] program_counter;
reg [11:0] program_counter_0;
reg [53:0] instruction_0;
reg [5:0] opcode_0;
reg [7:0] dest_0;
reg [7:0] src_0;
reg [7:0] srcb_0;
reg [31:0] literal_0;
reg [11:0] program_counter_1;
reg [5:0] opcode_1;
reg [7:0] dest_1;
reg [31:0] register_1;
reg [31:0] registerb_1;
reg [31:0] literal_1;
reg [7:0] dest_2;
reg [31:0] result_2;
reg write_enable_2;
reg [15:0] address_2;
reg [15:0] data_out_2;
reg [15:0] data_in_2;
reg memory_enable_2;
reg [15:0] address_4;
reg [31:0] data_out_4;
reg [31:0] data_in_4;
reg memory_enable_4;
reg [15:0] s_output_socket_stb;
reg [15:0] s_output_eth_tx_stb;
reg [15:0] s_output_socket;
reg [15:0] s_output_eth_tx;
reg [15:0] s_input_eth_rx_ack;
reg [15:0] s_input_socket_ack;
reg [15:0] memory_2 [2685:0];
reg [53:0] instructions [3437:0];
reg [31:0] registers [151:0];
//////////////////////////////////////////////////////////////////////////////
// INSTRUCTION INITIALIZATION
//
// Initialise the contents of the instruction memory
//
// Intruction Set
// ==============
// 0 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'literal'}
// 1 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'jmp_and_link'}
// 2 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'stop'}
// 3 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'move'}
// 4 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'nop'}
// 5 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'output': 'eth_tx', 'op': 'write'}
// 6 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'jmp_to_reg'}
// 7 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'output': 'socket', 'op': 'write'}
// 8 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'input': 'eth_rx', 'op': 'read'}
// 9 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'input': 'eth_rx', 'op': 'ready'}
// 10 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'input': 'socket', 'op': 'read'}
// 11 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '+'}
// 12 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '&'}
// 13 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'jmp_if_false'}
// 14 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '+'}
// 15 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'goto'}
// 16 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': '~'}
// 17 {'right': False, 'element_size': 2, 'float': False, 'unsigned': False, 'literal': False, 'op': 'memory_read_request'}
// 18 {'right': False, 'element_size': 2, 'float': False, 'unsigned': False, 'literal': False, 'op': 'memory_read_wait'}
// 19 {'right': False, 'element_size': 2, 'float': False, 'unsigned': False, 'literal': False, 'op': 'memory_read'}
// 20 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '<'}
// 21 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '!='}
// 22 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'jmp_if_true'}
// 23 {'right': False, 'element_size': 2, 'float': False, 'unsigned': False, 'literal': False, 'op': 'memory_write'}
// 24 {'right': False, 'float': False, 'unsigned': True, 'literal': False, 'file': '/home/amer/Nexys3/GitHub/TCP11/source/server.h', 'line': 107, 'op': 'report'}
// 25 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '=='}
// 26 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': '+'}
// 27 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '<'}
// 28 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '=='}
// 29 {'float': False, 'literal': True, 'right': False, 'unsigned': True, 'op': '|'}
// 30 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '<='}
// 31 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '!='}
// 32 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '>>'}
// 33 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '<<'}
// 34 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '-'}
// 35 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '-'}
// 36 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '<='}
// 37 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '|'}
// 38 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'input': 'socket', 'op': 'ready'}
// 39 {'float': False, 'literal': True, 'right': True, 'unsigned': False, 'op': '=='}
// 40 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'file': '/home/amer/Nexys3/GitHub/TCP11/source/server.h', 'line': 552, 'op': 'report'}
// 41 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'wait_clocks'}
// Intructions
// ===========
initial
begin
instructions[0] = {6'd0, 8'd10, 8'd0, 32'd0};//{'dest': 10, 'literal': 0, 'op': 'literal'}
instructions[1] = {6'd0, 8'd11, 8'd0, 32'd0};//{'dest': 11, 'literal': 0, 'size': 4, 'signed': 4, 'op': 'literal'}
instructions[2] = {6'd0, 8'd40, 8'd0, 32'd520};//{'dest': 40, 'literal': 520, 'op': 'literal'}
instructions[3] = {6'd0, 8'd41, 8'd0, 32'd536};//{'dest': 41, 'literal': 536, 'op': 'literal'}
instructions[4] = {6'd0, 8'd42, 8'd0, 32'd552};//{'dest': 42, 'literal': 552, 'op': 'literal'}
instructions[5] = {6'd0, 8'd43, 8'd0, 32'd568};//{'dest': 43, 'literal': 568, 'op': 'literal'}
instructions[6] = {6'd0, 8'd44, 8'd0, 32'd584};//{'dest': 44, 'literal': 584, 'op': 'literal'}
instructions[7] = {6'd0, 8'd45, 8'd0, 32'd0};//{'dest': 45, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[8] = {6'd0, 8'd75, 8'd0, 32'd0};//{'dest': 75, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[9] = {6'd0, 8'd76, 8'd0, 32'd0};//{'dest': 76, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[10] = {6'd0, 8'd77, 8'd0, 32'd0};//{'dest': 77, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[11] = {6'd0, 8'd78, 8'd0, 32'd0};//{'dest': 78, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[12] = {6'd0, 8'd79, 8'd0, 32'd620};//{'dest': 79, 'literal': 620, 'op': 'literal'}
instructions[13] = {6'd0, 8'd80, 8'd0, 32'd622};//{'dest': 80, 'literal': 622, 'op': 'literal'}
instructions[14] = {6'd0, 8'd81, 8'd0, 32'd624};//{'dest': 81, 'literal': 624, 'op': 'literal'}
instructions[15] = {6'd0, 8'd82, 8'd0, 32'd1460};//{'dest': 82, 'literal': 1460, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[16] = {6'd0, 8'd83, 8'd0, 32'd0};//{'dest': 83, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[17] = {6'd0, 8'd84, 8'd0, 32'd0};//{'dest': 84, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[18] = {6'd0, 8'd85, 8'd0, 32'd0};//{'dest': 85, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[19] = {6'd0, 8'd86, 8'd0, 32'd0};//{'dest': 86, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[20] = {6'd0, 8'd87, 8'd0, 32'd0};//{'dest': 87, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[21] = {6'd0, 8'd88, 8'd0, 32'd0};//{'dest': 88, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[22] = {6'd0, 8'd89, 8'd0, 32'd0};//{'dest': 89, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[23] = {6'd0, 8'd90, 8'd0, 32'd0};//{'dest': 90, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[24] = {6'd0, 8'd91, 8'd0, 32'd626};//{'dest': 91, 'literal': 626, 'op': 'literal'}
instructions[25] = {6'd0, 8'd92, 8'd0, 32'd628};//{'dest': 92, 'literal': 628, 'op': 'literal'}
instructions[26] = {6'd0, 8'd93, 8'd0, 32'd0};//{'dest': 93, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[27] = {6'd0, 8'd94, 8'd0, 32'd0};//{'dest': 94, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[28] = {6'd0, 8'd95, 8'd0, 32'd0};//{'dest': 95, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[29] = {6'd0, 8'd96, 8'd0, 32'd0};//{'dest': 96, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[30] = {6'd0, 8'd104, 8'd0, 32'd0};//{'dest': 104, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[31] = {6'd0, 8'd105, 8'd0, 32'd0};//{'dest': 105, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[32] = {6'd1, 8'd128, 8'd0, 32'd2513};//{'dest': 128, 'label': 2513, 'op': 'jmp_and_link'}
instructions[33] = {6'd2, 8'd0, 8'd0, 32'd0};//{'op': 'stop'}
instructions[34] = {6'd3, 8'd140, 8'd1, 32'd0};//{'dest': 140, 'src': 1, 'op': 'move'}
instructions[35] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[36] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[37] = {6'd5, 8'd0, 8'd140, 32'd0};//{'src': 140, 'output': 'eth_tx', 'op': 'write'}
instructions[38] = {6'd6, 8'd0, 8'd0, 32'd0};//{'src': 0, 'op': 'jmp_to_reg'}
instructions[39] = {6'd3, 8'd140, 8'd3, 32'd0};//{'dest': 140, 'src': 3, 'op': 'move'}
instructions[40] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[41] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[42] = {6'd7, 8'd0, 8'd140, 32'd0};//{'src': 140, 'output': 'socket', 'op': 'write'}
instructions[43] = {6'd6, 8'd0, 8'd2, 32'd0};//{'src': 2, 'op': 'jmp_to_reg'}
instructions[44] = {6'd8, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'input': 'eth_rx', 'op': 'read'}
instructions[45] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[46] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[47] = {6'd3, 8'd5, 8'd140, 32'd0};//{'dest': 5, 'src': 140, 'op': 'move'}
instructions[48] = {6'd6, 8'd0, 8'd4, 32'd0};//{'src': 4, 'op': 'jmp_to_reg'}
instructions[49] = {6'd9, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'input': 'eth_rx', 'op': 'ready'}
instructions[50] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[51] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[52] = {6'd3, 8'd7, 8'd140, 32'd0};//{'dest': 7, 'src': 140, 'op': 'move'}
instructions[53] = {6'd6, 8'd0, 8'd6, 32'd0};//{'src': 6, 'op': 'jmp_to_reg'}
instructions[54] = {6'd10, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'input': 'socket', 'op': 'read'}
instructions[55] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[56] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[57] = {6'd3, 8'd9, 8'd140, 32'd0};//{'dest': 9, 'src': 140, 'op': 'move'}
instructions[58] = {6'd6, 8'd0, 8'd8, 32'd0};//{'src': 8, 'op': 'jmp_to_reg'}
instructions[59] = {6'd0, 8'd143, 8'd0, 32'd0};//{'dest': 143, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[60] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[61] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[62] = {6'd3, 8'd11, 8'd143, 32'd0};//{'dest': 11, 'src': 143, 'op': 'move'}
instructions[63] = {6'd6, 8'd0, 8'd12, 32'd0};//{'src': 12, 'op': 'jmp_to_reg'}
instructions[64] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[65] = {6'd3, 8'd144, 8'd11, 32'd0};//{'dest': 144, 'src': 11, 'op': 'move'}
instructions[66] = {6'd3, 8'd145, 8'd14, 32'd0};//{'dest': 145, 'src': 14, 'op': 'move'}
instructions[67] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[68] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[69] = {6'd11, 8'd143, 8'd144, 32'd145};//{'srcb': 145, 'src': 144, 'dest': 143, 'signed': False, 'op': '+', 'type': 'int', 'size': 4}
instructions[70] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[71] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[72] = {6'd3, 8'd11, 8'd143, 32'd0};//{'dest': 11, 'src': 143, 'op': 'move'}
instructions[73] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[74] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[75] = {6'd3, 8'd144, 8'd11, 32'd0};//{'dest': 144, 'src': 11, 'op': 'move'}
instructions[76] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[77] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[78] = {6'd12, 8'd143, 8'd144, 32'd65536};//{'src': 144, 'right': 65536, 'dest': 143, 'signed': False, 'op': '&', 'type': 'int', 'size': 4}
instructions[79] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[80] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[81] = {6'd13, 8'd0, 8'd143, 32'd99};//{'src': 143, 'label': 99, 'op': 'jmp_if_false'}
instructions[82] = {6'd3, 8'd144, 8'd11, 32'd0};//{'dest': 144, 'src': 11, 'op': 'move'}
instructions[83] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[84] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[85] = {6'd12, 8'd143, 8'd144, 32'd65535};//{'src': 144, 'right': 65535, 'dest': 143, 'signed': False, 'op': '&', 'type': 'int', 'size': 4}
instructions[86] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[87] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[88] = {6'd3, 8'd11, 8'd143, 32'd0};//{'dest': 11, 'src': 143, 'op': 'move'}
instructions[89] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[90] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[91] = {6'd3, 8'd144, 8'd11, 32'd0};//{'dest': 144, 'src': 11, 'op': 'move'}
instructions[92] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[93] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[94] = {6'd14, 8'd143, 8'd144, 32'd1};//{'src': 144, 'right': 1, 'dest': 143, 'signed': False, 'op': '+', 'type': 'int', 'size': 4}
instructions[95] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[96] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[97] = {6'd3, 8'd11, 8'd143, 32'd0};//{'dest': 11, 'src': 143, 'op': 'move'}
instructions[98] = {6'd15, 8'd0, 8'd0, 32'd99};//{'label': 99, 'op': 'goto'}
instructions[99] = {6'd6, 8'd0, 8'd13, 32'd0};//{'src': 13, 'op': 'jmp_to_reg'}
instructions[100] = {6'd3, 8'd143, 8'd11, 32'd0};//{'dest': 143, 'src': 11, 'op': 'move'}
instructions[101] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[102] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[103] = {6'd16, 8'd140, 8'd143, 32'd0};//{'dest': 140, 'src': 143, 'op': '~'}
instructions[104] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[105] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[106] = {6'd3, 8'd16, 8'd140, 32'd0};//{'dest': 16, 'src': 140, 'op': 'move'}
instructions[107] = {6'd6, 8'd0, 8'd15, 32'd0};//{'src': 15, 'op': 'jmp_to_reg'}
instructions[108] = {6'd0, 8'd22, 8'd0, 32'd0};//{'dest': 22, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[109] = {6'd0, 8'd23, 8'd0, 32'd0};//{'dest': 23, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[110] = {6'd0, 8'd24, 8'd0, 32'd0};//{'dest': 24, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[111] = {6'd0, 8'd142, 8'd0, 32'd0};//{'dest': 142, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[112] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[113] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[114] = {6'd11, 8'd146, 8'd142, 32'd20};//{'dest': 146, 'src': 142, 'srcb': 20, 'signed': False, 'op': '+'}
instructions[115] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[116] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[117] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592953344, 'op': 'memory_read_request'}
instructions[118] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[119] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592953344, 'op': 'memory_read_wait'}
instructions[120] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592953344, 'element_size': 2, 'op': 'memory_read'}
instructions[121] = {6'd3, 8'd142, 8'd21, 32'd0};//{'dest': 142, 'src': 21, 'op': 'move'}
instructions[122] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[123] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[124] = {6'd11, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[125] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[126] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[127] = {6'd3, 8'd22, 8'd140, 32'd0};//{'dest': 22, 'src': 140, 'op': 'move'}
instructions[128] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[129] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[130] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[131] = {6'd11, 8'd142, 8'd141, 32'd20};//{'dest': 142, 'src': 141, 'srcb': 20, 'signed': False, 'op': '+'}
instructions[132] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[133] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[134] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139709592953848, 'op': 'memory_read_request'}
instructions[135] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[136] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139709592953848, 'op': 'memory_read_wait'}
instructions[137] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 139709592953848, 'element_size': 2, 'op': 'memory_read'}
instructions[138] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[139] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[140] = {6'd3, 8'd23, 8'd140, 32'd0};//{'dest': 23, 'src': 140, 'op': 'move'}
instructions[141] = {6'd3, 8'd141, 8'd22, 32'd0};//{'dest': 141, 'src': 22, 'op': 'move'}
instructions[142] = {6'd3, 8'd142, 8'd21, 32'd0};//{'dest': 142, 'src': 21, 'op': 'move'}
instructions[143] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[144] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[145] = {6'd20, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[146] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[147] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[148] = {6'd13, 8'd0, 8'd140, 32'd157};//{'src': 140, 'label': 157, 'op': 'jmp_if_false'}
instructions[149] = {6'd3, 8'd141, 8'd23, 32'd0};//{'dest': 141, 'src': 23, 'op': 'move'}
instructions[150] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[151] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[152] = {6'd14, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[153] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[154] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[155] = {6'd3, 8'd23, 8'd140, 32'd0};//{'dest': 23, 'src': 140, 'op': 'move'}
instructions[156] = {6'd15, 8'd0, 8'd0, 32'd157};//{'label': 157, 'op': 'goto'}
instructions[157] = {6'd3, 8'd141, 8'd22, 32'd0};//{'dest': 141, 'src': 22, 'op': 'move'}
instructions[158] = {6'd0, 8'd146, 8'd0, 32'd0};//{'dest': 146, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[159] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[160] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[161] = {6'd11, 8'd147, 8'd146, 32'd19};//{'dest': 147, 'src': 146, 'srcb': 19, 'signed': False, 'op': '+'}
instructions[162] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[163] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[164] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592975624, 'op': 'memory_read_request'}
instructions[165] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[166] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592975624, 'op': 'memory_read_wait'}
instructions[167] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 139709592975624, 'element_size': 2, 'op': 'memory_read'}
instructions[168] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[169] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[170] = {6'd21, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[171] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[172] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[173] = {6'd22, 8'd0, 8'd140, 32'd188};//{'src': 140, 'label': 188, 'op': 'jmp_if_true'}
instructions[174] = {6'd3, 8'd141, 8'd23, 32'd0};//{'dest': 141, 'src': 23, 'op': 'move'}
instructions[175] = {6'd0, 8'd146, 8'd0, 32'd1};//{'dest': 146, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[176] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[177] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[178] = {6'd11, 8'd147, 8'd146, 32'd19};//{'dest': 147, 'src': 146, 'srcb': 19, 'signed': False, 'op': '+'}
instructions[179] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[180] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[181] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592975912, 'op': 'memory_read_request'}
instructions[182] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[183] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592975912, 'op': 'memory_read_wait'}
instructions[184] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 139709592975912, 'element_size': 2, 'op': 'memory_read'}
instructions[185] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[186] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[187] = {6'd21, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[188] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[189] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[190] = {6'd13, 8'd0, 8'd140, 32'd212};//{'src': 140, 'label': 212, 'op': 'jmp_if_false'}
instructions[191] = {6'd3, 8'd140, 8'd22, 32'd0};//{'dest': 140, 'src': 22, 'op': 'move'}
instructions[192] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[193] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[194] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[195] = {6'd11, 8'd142, 8'd141, 32'd19};//{'dest': 142, 'src': 141, 'srcb': 19, 'signed': False, 'op': '+'}
instructions[196] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[197] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[198] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[199] = {6'd3, 8'd140, 8'd23, 32'd0};//{'dest': 140, 'src': 23, 'op': 'move'}
instructions[200] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[201] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[202] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[203] = {6'd11, 8'd142, 8'd141, 32'd19};//{'dest': 142, 'src': 141, 'srcb': 19, 'signed': False, 'op': '+'}
instructions[204] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[205] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[206] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[207] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[208] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[209] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[210] = {6'd3, 8'd24, 8'd140, 32'd0};//{'dest': 24, 'src': 140, 'op': 'move'}
instructions[211] = {6'd15, 8'd0, 8'd0, 32'd212};//{'label': 212, 'op': 'goto'}
instructions[212] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[213] = {6'd3, 8'd140, 8'd24, 32'd0};//{'dest': 140, 'src': 24, 'op': 'move'}
instructions[214] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[215] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[216] = {6'd3, 8'd18, 8'd140, 32'd0};//{'dest': 18, 'src': 140, 'op': 'move'}
instructions[217] = {6'd6, 8'd0, 8'd17, 32'd0};//{'src': 17, 'op': 'jmp_to_reg'}
instructions[218] = {6'd0, 8'd32, 8'd0, 32'd0};//{'dest': 32, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[219] = {6'd0, 8'd33, 8'd0, 32'd0};//{'dest': 33, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[220] = {6'd3, 8'd140, 8'd27, 32'd0};//{'dest': 140, 'src': 27, 'op': 'move'}
instructions[221] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[222] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[223] = {6'd24, 8'd0, 8'd140, 32'd0};//{'src': 140, 'signed': False, 'file': '/home/amer/Nexys3/GitHub/TCP11/source/server.h', 'line': 107, 'type': 'int', 'op': 'report'}
instructions[224] = {6'd3, 8'd140, 8'd28, 32'd0};//{'dest': 140, 'src': 28, 'op': 'move'}
instructions[225] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[226] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[227] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[228] = {6'd11, 8'd142, 8'd141, 32'd26};//{'dest': 142, 'src': 141, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[229] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[230] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[231] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[232] = {6'd3, 8'd140, 8'd29, 32'd0};//{'dest': 140, 'src': 29, 'op': 'move'}
instructions[233] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[234] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[235] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[236] = {6'd11, 8'd142, 8'd141, 32'd26};//{'dest': 142, 'src': 141, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[237] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[238] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[239] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[240] = {6'd3, 8'd140, 8'd30, 32'd0};//{'dest': 140, 'src': 30, 'op': 'move'}
instructions[241] = {6'd0, 8'd141, 8'd0, 32'd2};//{'dest': 141, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[242] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[243] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[244] = {6'd11, 8'd142, 8'd141, 32'd26};//{'dest': 142, 'src': 141, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[245] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[246] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[247] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[248] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[249] = {6'd0, 8'd141, 8'd0, 32'd3};//{'dest': 141, 'literal': 3, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[250] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[251] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[252] = {6'd11, 8'd142, 8'd141, 32'd26};//{'dest': 142, 'src': 141, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[253] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[254] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[255] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[256] = {6'd0, 8'd140, 8'd0, 32'd515};//{'dest': 140, 'literal': 515, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[257] = {6'd0, 8'd141, 8'd0, 32'd4};//{'dest': 141, 'literal': 4, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[258] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[259] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[260] = {6'd11, 8'd142, 8'd141, 32'd26};//{'dest': 142, 'src': 141, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[261] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[262] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[263] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[264] = {6'd0, 8'd140, 8'd0, 32'd1029};//{'dest': 140, 'literal': 1029, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[265] = {6'd0, 8'd141, 8'd0, 32'd5};//{'dest': 141, 'literal': 5, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[266] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[267] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[268] = {6'd11, 8'd142, 8'd141, 32'd26};//{'dest': 142, 'src': 141, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[269] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[270] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[271] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[272] = {6'd3, 8'd140, 8'd31, 32'd0};//{'dest': 140, 'src': 31, 'op': 'move'}
instructions[273] = {6'd0, 8'd141, 8'd0, 32'd6};//{'dest': 141, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[274] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[275] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[276] = {6'd11, 8'd142, 8'd141, 32'd26};//{'dest': 142, 'src': 141, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[277] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[278] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[279] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[280] = {6'd3, 8'd141, 8'd27, 32'd0};//{'dest': 141, 'src': 27, 'op': 'move'}
instructions[281] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[282] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[283] = {6'd3, 8'd1, 8'd141, 32'd0};//{'dest': 1, 'src': 141, 'op': 'move'}
instructions[284] = {6'd1, 8'd0, 8'd0, 32'd34};//{'dest': 0, 'label': 34, 'op': 'jmp_and_link'}
instructions[285] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[286] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[287] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[288] = {6'd3, 8'd33, 8'd140, 32'd0};//{'dest': 33, 'src': 140, 'op': 'move'}
instructions[289] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[290] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[291] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[292] = {6'd3, 8'd32, 8'd140, 32'd0};//{'dest': 32, 'src': 140, 'op': 'move'}
instructions[293] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[294] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[295] = {6'd3, 8'd141, 8'd32, 32'd0};//{'dest': 141, 'src': 32, 'op': 'move'}
instructions[296] = {6'd3, 8'd142, 8'd27, 32'd0};//{'dest': 142, 'src': 27, 'op': 'move'}
instructions[297] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[298] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[299] = {6'd20, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[300] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[301] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[302] = {6'd13, 8'd0, 8'd140, 32'd327};//{'src': 140, 'label': 327, 'op': 'jmp_if_false'}
instructions[303] = {6'd3, 8'd142, 8'd33, 32'd0};//{'dest': 142, 'src': 33, 'op': 'move'}
instructions[304] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[305] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[306] = {6'd11, 8'd146, 8'd142, 32'd26};//{'dest': 146, 'src': 142, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[307] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[308] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[309] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592496104, 'op': 'memory_read_request'}
instructions[310] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[311] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592496104, 'op': 'memory_read_wait'}
instructions[312] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592496104, 'element_size': 2, 'op': 'memory_read'}
instructions[313] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[314] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[315] = {6'd3, 8'd1, 8'd141, 32'd0};//{'dest': 1, 'src': 141, 'op': 'move'}
instructions[316] = {6'd1, 8'd0, 8'd0, 32'd34};//{'dest': 0, 'label': 34, 'op': 'jmp_and_link'}
instructions[317] = {6'd3, 8'd140, 8'd33, 32'd0};//{'dest': 140, 'src': 33, 'op': 'move'}
instructions[318] = {6'd14, 8'd33, 8'd33, 32'd1};//{'src': 33, 'right': 1, 'dest': 33, 'signed': False, 'op': '+', 'size': 2}
instructions[319] = {6'd3, 8'd141, 8'd32, 32'd0};//{'dest': 141, 'src': 32, 'op': 'move'}
instructions[320] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[321] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[322] = {6'd14, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[323] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[324] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[325] = {6'd3, 8'd32, 8'd140, 32'd0};//{'dest': 32, 'src': 140, 'op': 'move'}
instructions[326] = {6'd15, 8'd0, 8'd0, 32'd293};//{'label': 293, 'op': 'goto'}
instructions[327] = {6'd6, 8'd0, 8'd25, 32'd0};//{'src': 25, 'op': 'jmp_to_reg'}
instructions[328] = {6'd0, 8'd37, 8'd0, 32'd0};//{'dest': 37, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[329] = {6'd0, 8'd38, 8'd0, 32'd0};//{'dest': 38, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[330] = {6'd0, 8'd39, 8'd0, 32'd0};//{'dest': 39, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[331] = {6'd1, 8'd6, 8'd0, 32'd49};//{'dest': 6, 'label': 49, 'op': 'jmp_and_link'}
instructions[332] = {6'd3, 8'd141, 8'd7, 32'd0};//{'dest': 141, 'src': 7, 'op': 'move'}
instructions[333] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[334] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[335] = {6'd25, 8'd140, 8'd141, 32'd0};//{'src': 141, 'right': 0, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[336] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[337] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[338] = {6'd13, 8'd0, 8'd140, 32'd345};//{'src': 140, 'label': 345, 'op': 'jmp_if_false'}
instructions[339] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[340] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[341] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[342] = {6'd3, 8'd35, 8'd140, 32'd0};//{'dest': 35, 'src': 140, 'op': 'move'}
instructions[343] = {6'd6, 8'd0, 8'd34, 32'd0};//{'src': 34, 'op': 'jmp_to_reg'}
instructions[344] = {6'd15, 8'd0, 8'd0, 32'd345};//{'label': 345, 'op': 'goto'}
instructions[345] = {6'd1, 8'd4, 8'd0, 32'd44};//{'dest': 4, 'label': 44, 'op': 'jmp_and_link'}
instructions[346] = {6'd3, 8'd140, 8'd5, 32'd0};//{'dest': 140, 'src': 5, 'op': 'move'}
instructions[347] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[348] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[349] = {6'd3, 8'd37, 8'd140, 32'd0};//{'dest': 37, 'src': 140, 'op': 'move'}
instructions[350] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[351] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[352] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[353] = {6'd3, 8'd38, 8'd140, 32'd0};//{'dest': 38, 'src': 140, 'op': 'move'}
instructions[354] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[355] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[356] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[357] = {6'd3, 8'd39, 8'd140, 32'd0};//{'dest': 39, 'src': 140, 'op': 'move'}
instructions[358] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[359] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[360] = {6'd3, 8'd141, 8'd39, 32'd0};//{'dest': 141, 'src': 39, 'op': 'move'}
instructions[361] = {6'd3, 8'd142, 8'd37, 32'd0};//{'dest': 142, 'src': 37, 'op': 'move'}
instructions[362] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[363] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[364] = {6'd20, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[365] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[366] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[367] = {6'd13, 8'd0, 8'd140, 32'd387};//{'src': 140, 'label': 387, 'op': 'jmp_if_false'}
instructions[368] = {6'd1, 8'd4, 8'd0, 32'd44};//{'dest': 4, 'label': 44, 'op': 'jmp_and_link'}
instructions[369] = {6'd3, 8'd140, 8'd5, 32'd0};//{'dest': 140, 'src': 5, 'op': 'move'}
instructions[370] = {6'd3, 8'd141, 8'd38, 32'd0};//{'dest': 141, 'src': 38, 'op': 'move'}
instructions[371] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[372] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[373] = {6'd11, 8'd142, 8'd141, 32'd36};//{'dest': 142, 'src': 141, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[374] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[375] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[376] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[377] = {6'd3, 8'd140, 8'd38, 32'd0};//{'dest': 140, 'src': 38, 'op': 'move'}
instructions[378] = {6'd14, 8'd38, 8'd38, 32'd1};//{'src': 38, 'right': 1, 'dest': 38, 'signed': False, 'op': '+', 'size': 2}
instructions[379] = {6'd3, 8'd141, 8'd39, 32'd0};//{'dest': 141, 'src': 39, 'op': 'move'}
instructions[380] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[381] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[382] = {6'd14, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[383] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[384] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[385] = {6'd3, 8'd39, 8'd140, 32'd0};//{'dest': 39, 'src': 140, 'op': 'move'}
instructions[386] = {6'd15, 8'd0, 8'd0, 32'd358};//{'label': 358, 'op': 'goto'}
instructions[387] = {6'd0, 8'd142, 8'd0, 32'd6};//{'dest': 142, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[388] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[389] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[390] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[391] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[392] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[393] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592497112, 'op': 'memory_read_request'}
instructions[394] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[395] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592497112, 'op': 'memory_read_wait'}
instructions[396] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592497112, 'element_size': 2, 'op': 'memory_read'}
instructions[397] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[398] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[399] = {6'd25, 8'd140, 8'd141, 32'd2054};//{'src': 141, 'right': 2054, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[400] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[401] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[402] = {6'd13, 8'd0, 8'd140, 32'd635};//{'src': 140, 'label': 635, 'op': 'jmp_if_false'}
instructions[403] = {6'd0, 8'd142, 8'd0, 32'd10};//{'dest': 142, 'literal': 10, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[404] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[405] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[406] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[407] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[408] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[409] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592497616, 'op': 'memory_read_request'}
instructions[410] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[411] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592497616, 'op': 'memory_read_wait'}
instructions[412] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592497616, 'element_size': 2, 'op': 'memory_read'}
instructions[413] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[414] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[415] = {6'd25, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[416] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[417] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[418] = {6'd13, 8'd0, 8'd140, 32'd629};//{'src': 140, 'label': 629, 'op': 'jmp_if_false'}
instructions[419] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[420] = {6'd0, 8'd141, 8'd0, 32'd7};//{'dest': 141, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[421] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[422] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[423] = {6'd26, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': True, 'op': '+'}
instructions[424] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[425] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[426] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[427] = {6'd0, 8'd140, 8'd0, 32'd2048};//{'dest': 140, 'literal': 2048, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[428] = {6'd0, 8'd141, 8'd0, 32'd8};//{'dest': 141, 'literal': 8, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[429] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[430] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[431] = {6'd26, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': True, 'op': '+'}
instructions[432] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[433] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[434] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[435] = {6'd0, 8'd140, 8'd0, 32'd1540};//{'dest': 140, 'literal': 1540, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[436] = {6'd0, 8'd141, 8'd0, 32'd9};//{'dest': 141, 'literal': 9, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[437] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[438] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[439] = {6'd26, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': True, 'op': '+'}
instructions[440] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[441] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[442] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[443] = {6'd0, 8'd140, 8'd0, 32'd2};//{'dest': 140, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[444] = {6'd0, 8'd141, 8'd0, 32'd10};//{'dest': 141, 'literal': 10, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[445] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[446] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[447] = {6'd26, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': True, 'op': '+'}
instructions[448] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[449] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[450] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[451] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[452] = {6'd0, 8'd141, 8'd0, 32'd11};//{'dest': 141, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[453] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[454] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[455] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[456] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[457] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[458] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[459] = {6'd0, 8'd140, 8'd0, 32'd515};//{'dest': 140, 'literal': 515, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[460] = {6'd0, 8'd141, 8'd0, 32'd12};//{'dest': 141, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[461] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[462] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[463] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[464] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[465] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[466] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[467] = {6'd0, 8'd140, 8'd0, 32'd1029};//{'dest': 140, 'literal': 1029, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[468] = {6'd0, 8'd141, 8'd0, 32'd13};//{'dest': 141, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[469] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[470] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[471] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[472] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[473] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[474] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[475] = {6'd0, 8'd140, 8'd0, 32'd49320};//{'dest': 140, 'literal': 49320, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[476] = {6'd0, 8'd141, 8'd0, 32'd14};//{'dest': 141, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[477] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[478] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[479] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[480] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[481] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[482] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[483] = {6'd0, 8'd140, 8'd0, 32'd119};//{'dest': 140, 'literal': 119, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[484] = {6'd0, 8'd141, 8'd0, 32'd15};//{'dest': 141, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[485] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[486] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[487] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[488] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[489] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[490] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[491] = {6'd0, 8'd146, 8'd0, 32'd11};//{'dest': 146, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[492] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[493] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[494] = {6'd11, 8'd147, 8'd146, 32'd36};//{'dest': 147, 'src': 146, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[495] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[496] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[497] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592521976, 'op': 'memory_read_request'}
instructions[498] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[499] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592521976, 'op': 'memory_read_wait'}
instructions[500] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709592521976, 'element_size': 2, 'op': 'memory_read'}
instructions[501] = {6'd0, 8'd141, 8'd0, 32'd16};//{'dest': 141, 'literal': 16, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[502] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[503] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[504] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[505] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[506] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[507] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[508] = {6'd0, 8'd146, 8'd0, 32'd12};//{'dest': 146, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[509] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[510] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[511] = {6'd11, 8'd147, 8'd146, 32'd36};//{'dest': 147, 'src': 146, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[512] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[513] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[514] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592522408, 'op': 'memory_read_request'}
instructions[515] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[516] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592522408, 'op': 'memory_read_wait'}
instructions[517] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709592522408, 'element_size': 2, 'op': 'memory_read'}
instructions[518] = {6'd0, 8'd141, 8'd0, 32'd17};//{'dest': 141, 'literal': 17, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[519] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[520] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[521] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[522] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[523] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[524] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[525] = {6'd0, 8'd146, 8'd0, 32'd13};//{'dest': 146, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[526] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[527] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[528] = {6'd11, 8'd147, 8'd146, 32'd36};//{'dest': 147, 'src': 146, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[529] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[530] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[531] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592539288, 'op': 'memory_read_request'}
instructions[532] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[533] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592539288, 'op': 'memory_read_wait'}
instructions[534] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709592539288, 'element_size': 2, 'op': 'memory_read'}
instructions[535] = {6'd0, 8'd141, 8'd0, 32'd18};//{'dest': 141, 'literal': 18, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[536] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[537] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[538] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[539] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[540] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[541] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[542] = {6'd0, 8'd146, 8'd0, 32'd14};//{'dest': 146, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[543] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[544] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[545] = {6'd11, 8'd147, 8'd146, 32'd36};//{'dest': 147, 'src': 146, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[546] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[547] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[548] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592539720, 'op': 'memory_read_request'}
instructions[549] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[550] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592539720, 'op': 'memory_read_wait'}
instructions[551] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709592539720, 'element_size': 2, 'op': 'memory_read'}
instructions[552] = {6'd0, 8'd141, 8'd0, 32'd19};//{'dest': 141, 'literal': 19, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[553] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[554] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[555] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[556] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[557] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[558] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[559] = {6'd0, 8'd146, 8'd0, 32'd15};//{'dest': 146, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[560] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[561] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[562] = {6'd11, 8'd147, 8'd146, 32'd36};//{'dest': 147, 'src': 146, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[563] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[564] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[565] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592540152, 'op': 'memory_read_request'}
instructions[566] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[567] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592540152, 'op': 'memory_read_wait'}
instructions[568] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709592540152, 'element_size': 2, 'op': 'memory_read'}
instructions[569] = {6'd0, 8'd141, 8'd0, 32'd20};//{'dest': 141, 'literal': 20, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[570] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[571] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[572] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[573] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[574] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[575] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[576] = {6'd3, 8'd148, 8'd10, 32'd0};//{'dest': 148, 'src': 10, 'op': 'move'}
instructions[577] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[578] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[579] = {6'd3, 8'd26, 8'd148, 32'd0};//{'dest': 26, 'src': 148, 'op': 'move'}
instructions[580] = {6'd0, 8'd141, 8'd0, 32'd64};//{'dest': 141, 'literal': 64, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[581] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[582] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[583] = {6'd3, 8'd27, 8'd141, 32'd0};//{'dest': 27, 'src': 141, 'op': 'move'}
instructions[584] = {6'd0, 8'd142, 8'd0, 32'd11};//{'dest': 142, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[585] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[586] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[587] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[588] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[589] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[590] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592549136, 'op': 'memory_read_request'}
instructions[591] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[592] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592549136, 'op': 'memory_read_wait'}
instructions[593] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592549136, 'element_size': 2, 'op': 'memory_read'}
instructions[594] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[595] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[596] = {6'd3, 8'd28, 8'd141, 32'd0};//{'dest': 28, 'src': 141, 'op': 'move'}
instructions[597] = {6'd0, 8'd142, 8'd0, 32'd12};//{'dest': 142, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[598] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[599] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[600] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[601] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[602] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[603] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592549280, 'op': 'memory_read_request'}
instructions[604] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[605] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592549280, 'op': 'memory_read_wait'}
instructions[606] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592549280, 'element_size': 2, 'op': 'memory_read'}
instructions[607] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[608] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[609] = {6'd3, 8'd29, 8'd141, 32'd0};//{'dest': 29, 'src': 141, 'op': 'move'}
instructions[610] = {6'd0, 8'd142, 8'd0, 32'd13};//{'dest': 142, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[611] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[612] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[613] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[614] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[615] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[616] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592549424, 'op': 'memory_read_request'}
instructions[617] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[618] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592549424, 'op': 'memory_read_wait'}
instructions[619] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592549424, 'element_size': 2, 'op': 'memory_read'}
instructions[620] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[621] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[622] = {6'd3, 8'd30, 8'd141, 32'd0};//{'dest': 30, 'src': 141, 'op': 'move'}
instructions[623] = {6'd0, 8'd141, 8'd0, 32'd2054};//{'dest': 141, 'literal': 2054, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[624] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[625] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[626] = {6'd3, 8'd31, 8'd141, 32'd0};//{'dest': 31, 'src': 141, 'op': 'move'}
instructions[627] = {6'd1, 8'd25, 8'd0, 32'd218};//{'dest': 25, 'label': 218, 'op': 'jmp_and_link'}
instructions[628] = {6'd15, 8'd0, 8'd0, 32'd629};//{'label': 629, 'op': 'goto'}
instructions[629] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[630] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[631] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[632] = {6'd3, 8'd35, 8'd140, 32'd0};//{'dest': 35, 'src': 140, 'op': 'move'}
instructions[633] = {6'd6, 8'd0, 8'd34, 32'd0};//{'src': 34, 'op': 'jmp_to_reg'}
instructions[634] = {6'd15, 8'd0, 8'd0, 32'd635};//{'label': 635, 'op': 'goto'}
instructions[635] = {6'd3, 8'd140, 8'd37, 32'd0};//{'dest': 140, 'src': 37, 'op': 'move'}
instructions[636] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[637] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[638] = {6'd3, 8'd35, 8'd140, 32'd0};//{'dest': 35, 'src': 140, 'op': 'move'}
instructions[639] = {6'd6, 8'd0, 8'd34, 32'd0};//{'src': 34, 'op': 'jmp_to_reg'}
instructions[640] = {6'd0, 8'd50, 8'd0, 32'd0};//{'dest': 50, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[641] = {6'd0, 8'd51, 8'd0, 32'd0};//{'dest': 51, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[642] = {6'd0, 8'd52, 8'd0, 32'd600};//{'dest': 52, 'literal': 600, 'op': 'literal'}
instructions[643] = {6'd0, 8'd53, 8'd0, 32'd0};//{'dest': 53, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[644] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[645] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[646] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[647] = {6'd3, 8'd53, 8'd140, 32'd0};//{'dest': 53, 'src': 140, 'op': 'move'}
instructions[648] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[649] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[650] = {6'd3, 8'd141, 8'd53, 32'd0};//{'dest': 141, 'src': 53, 'op': 'move'}
instructions[651] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[652] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[653] = {6'd27, 8'd140, 8'd141, 32'd16};//{'src': 141, 'right': 16, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[654] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[655] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[656] = {6'd13, 8'd0, 8'd140, 32'd700};//{'src': 140, 'label': 700, 'op': 'jmp_if_false'}
instructions[657] = {6'd3, 8'd142, 8'd53, 32'd0};//{'dest': 142, 'src': 53, 'op': 'move'}
instructions[658] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[659] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[660] = {6'd11, 8'd146, 8'd142, 32'd40};//{'dest': 146, 'src': 142, 'srcb': 40, 'signed': False, 'op': '+'}
instructions[661] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[662] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[663] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592549784, 'op': 'memory_read_request'}
instructions[664] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[665] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592549784, 'op': 'memory_read_wait'}
instructions[666] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592549784, 'element_size': 2, 'op': 'memory_read'}
instructions[667] = {6'd3, 8'd142, 8'd48, 32'd0};//{'dest': 142, 'src': 48, 'op': 'move'}
instructions[668] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[669] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[670] = {6'd28, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[671] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[672] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[673] = {6'd13, 8'd0, 8'd140, 32'd688};//{'src': 140, 'label': 688, 'op': 'jmp_if_false'}
instructions[674] = {6'd3, 8'd142, 8'd53, 32'd0};//{'dest': 142, 'src': 53, 'op': 'move'}
instructions[675] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[676] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[677] = {6'd11, 8'd146, 8'd142, 32'd41};//{'dest': 146, 'src': 142, 'srcb': 41, 'signed': False, 'op': '+'}
instructions[678] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[679] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[680] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592550072, 'op': 'memory_read_request'}
instructions[681] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[682] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592550072, 'op': 'memory_read_wait'}
instructions[683] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592550072, 'element_size': 2, 'op': 'memory_read'}
instructions[684] = {6'd3, 8'd142, 8'd49, 32'd0};//{'dest': 142, 'src': 49, 'op': 'move'}
instructions[685] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[686] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[687] = {6'd28, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[688] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[689] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[690] = {6'd13, 8'd0, 8'd140, 32'd697};//{'src': 140, 'label': 697, 'op': 'jmp_if_false'}
instructions[691] = {6'd3, 8'd140, 8'd53, 32'd0};//{'dest': 140, 'src': 53, 'op': 'move'}
instructions[692] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[693] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[694] = {6'd3, 8'd47, 8'd140, 32'd0};//{'dest': 47, 'src': 140, 'op': 'move'}
instructions[695] = {6'd6, 8'd0, 8'd46, 32'd0};//{'src': 46, 'op': 'jmp_to_reg'}
instructions[696] = {6'd15, 8'd0, 8'd0, 32'd697};//{'label': 697, 'op': 'goto'}
instructions[697] = {6'd3, 8'd140, 8'd53, 32'd0};//{'dest': 140, 'src': 53, 'op': 'move'}
instructions[698] = {6'd14, 8'd53, 8'd53, 32'd1};//{'src': 53, 'right': 1, 'dest': 53, 'signed': False, 'op': '+', 'size': 2}
instructions[699] = {6'd15, 8'd0, 8'd0, 32'd648};//{'label': 648, 'op': 'goto'}
instructions[700] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[701] = {6'd0, 8'd141, 8'd0, 32'd7};//{'dest': 141, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[702] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[703] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[704] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[705] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[706] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[707] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[708] = {6'd0, 8'd140, 8'd0, 32'd2048};//{'dest': 140, 'literal': 2048, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[709] = {6'd0, 8'd141, 8'd0, 32'd8};//{'dest': 141, 'literal': 8, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[710] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[711] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[712] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[713] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[714] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[715] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[716] = {6'd0, 8'd140, 8'd0, 32'd1540};//{'dest': 140, 'literal': 1540, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[717] = {6'd0, 8'd141, 8'd0, 32'd9};//{'dest': 141, 'literal': 9, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[718] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[719] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[720] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[721] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[722] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[723] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[724] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[725] = {6'd0, 8'd141, 8'd0, 32'd10};//{'dest': 141, 'literal': 10, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[726] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[727] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[728] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[729] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[730] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[731] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[732] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[733] = {6'd0, 8'd141, 8'd0, 32'd11};//{'dest': 141, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[734] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[735] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[736] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[737] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[738] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[739] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[740] = {6'd0, 8'd140, 8'd0, 32'd515};//{'dest': 140, 'literal': 515, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[741] = {6'd0, 8'd141, 8'd0, 32'd12};//{'dest': 141, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[742] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[743] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[744] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[745] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[746] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[747] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[748] = {6'd0, 8'd140, 8'd0, 32'd1029};//{'dest': 140, 'literal': 1029, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[749] = {6'd0, 8'd141, 8'd0, 32'd13};//{'dest': 141, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[750] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[751] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[752] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[753] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[754] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[755] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[756] = {6'd0, 8'd140, 8'd0, 32'd49320};//{'dest': 140, 'literal': 49320, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[757] = {6'd0, 8'd141, 8'd0, 32'd14};//{'dest': 141, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[758] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[759] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[760] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[761] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[762] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[763] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[764] = {6'd0, 8'd140, 8'd0, 32'd119};//{'dest': 140, 'literal': 119, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[765] = {6'd0, 8'd141, 8'd0, 32'd15};//{'dest': 141, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[766] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[767] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[768] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[769] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[770] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[771] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[772] = {6'd3, 8'd140, 8'd48, 32'd0};//{'dest': 140, 'src': 48, 'op': 'move'}
instructions[773] = {6'd0, 8'd141, 8'd0, 32'd19};//{'dest': 141, 'literal': 19, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[774] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[775] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[776] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[777] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[778] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[779] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[780] = {6'd3, 8'd140, 8'd49, 32'd0};//{'dest': 140, 'src': 49, 'op': 'move'}
instructions[781] = {6'd0, 8'd141, 8'd0, 32'd20};//{'dest': 141, 'literal': 20, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[782] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[783] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[784] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[785] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[786] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[787] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[788] = {6'd3, 8'd148, 8'd10, 32'd0};//{'dest': 148, 'src': 10, 'op': 'move'}
instructions[789] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[790] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[791] = {6'd3, 8'd26, 8'd148, 32'd0};//{'dest': 26, 'src': 148, 'op': 'move'}
instructions[792] = {6'd0, 8'd141, 8'd0, 32'd64};//{'dest': 141, 'literal': 64, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[793] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[794] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[795] = {6'd3, 8'd27, 8'd141, 32'd0};//{'dest': 27, 'src': 141, 'op': 'move'}
instructions[796] = {6'd0, 8'd141, 8'd0, 32'd65535};//{'dest': 141, 'literal': 65535, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[797] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[798] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[799] = {6'd3, 8'd28, 8'd141, 32'd0};//{'dest': 28, 'src': 141, 'op': 'move'}
instructions[800] = {6'd0, 8'd141, 8'd0, 32'd65535};//{'dest': 141, 'literal': 65535, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[801] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[802] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[803] = {6'd3, 8'd29, 8'd141, 32'd0};//{'dest': 29, 'src': 141, 'op': 'move'}
instructions[804] = {6'd0, 8'd141, 8'd0, 32'd65535};//{'dest': 141, 'literal': 65535, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[805] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[806] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[807] = {6'd3, 8'd30, 8'd141, 32'd0};//{'dest': 30, 'src': 141, 'op': 'move'}
instructions[808] = {6'd0, 8'd141, 8'd0, 32'd2054};//{'dest': 141, 'literal': 2054, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[809] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[810] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[811] = {6'd3, 8'd31, 8'd141, 32'd0};//{'dest': 31, 'src': 141, 'op': 'move'}
instructions[812] = {6'd1, 8'd25, 8'd0, 32'd218};//{'dest': 25, 'label': 218, 'op': 'jmp_and_link'}
instructions[813] = {6'd1, 8'd4, 8'd0, 32'd44};//{'dest': 4, 'label': 44, 'op': 'jmp_and_link'}
instructions[814] = {6'd3, 8'd140, 8'd5, 32'd0};//{'dest': 140, 'src': 5, 'op': 'move'}
instructions[815] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[816] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[817] = {6'd3, 8'd50, 8'd140, 32'd0};//{'dest': 50, 'src': 140, 'op': 'move'}
instructions[818] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[819] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[820] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[821] = {6'd3, 8'd53, 8'd140, 32'd0};//{'dest': 53, 'src': 140, 'op': 'move'}
instructions[822] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[823] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[824] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[825] = {6'd3, 8'd51, 8'd140, 32'd0};//{'dest': 51, 'src': 140, 'op': 'move'}
instructions[826] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[827] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[828] = {6'd3, 8'd141, 8'd51, 32'd0};//{'dest': 141, 'src': 51, 'op': 'move'}
instructions[829] = {6'd3, 8'd142, 8'd50, 32'd0};//{'dest': 142, 'src': 50, 'op': 'move'}
instructions[830] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[831] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[832] = {6'd20, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[833] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[834] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[835] = {6'd13, 8'd0, 8'd140, 32'd865};//{'src': 140, 'label': 865, 'op': 'jmp_if_false'}
instructions[836] = {6'd3, 8'd141, 8'd53, 32'd0};//{'dest': 141, 'src': 53, 'op': 'move'}
instructions[837] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[838] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[839] = {6'd27, 8'd140, 8'd141, 32'd16};//{'src': 141, 'right': 16, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[840] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[841] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[842] = {6'd13, 8'd0, 8'd140, 32'd853};//{'src': 140, 'label': 853, 'op': 'jmp_if_false'}
instructions[843] = {6'd1, 8'd4, 8'd0, 32'd44};//{'dest': 4, 'label': 44, 'op': 'jmp_and_link'}
instructions[844] = {6'd3, 8'd140, 8'd5, 32'd0};//{'dest': 140, 'src': 5, 'op': 'move'}
instructions[845] = {6'd3, 8'd141, 8'd53, 32'd0};//{'dest': 141, 'src': 53, 'op': 'move'}
instructions[846] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[847] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[848] = {6'd11, 8'd142, 8'd141, 32'd52};//{'dest': 142, 'src': 141, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[849] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[850] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[851] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[852] = {6'd15, 8'd0, 8'd0, 32'd855};//{'label': 855, 'op': 'goto'}
instructions[853] = {6'd1, 8'd4, 8'd0, 32'd44};//{'dest': 4, 'label': 44, 'op': 'jmp_and_link'}
instructions[854] = {6'd3, 8'd140, 8'd5, 32'd0};//{'dest': 140, 'src': 5, 'op': 'move'}
instructions[855] = {6'd3, 8'd140, 8'd53, 32'd0};//{'dest': 140, 'src': 53, 'op': 'move'}
instructions[856] = {6'd14, 8'd53, 8'd53, 32'd1};//{'src': 53, 'right': 1, 'dest': 53, 'signed': False, 'op': '+', 'size': 2}
instructions[857] = {6'd3, 8'd141, 8'd51, 32'd0};//{'dest': 141, 'src': 51, 'op': 'move'}
instructions[858] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[859] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[860] = {6'd14, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[861] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[862] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[863] = {6'd3, 8'd51, 8'd140, 32'd0};//{'dest': 51, 'src': 140, 'op': 'move'}
instructions[864] = {6'd15, 8'd0, 8'd0, 32'd826};//{'label': 826, 'op': 'goto'}
instructions[865] = {6'd0, 8'd142, 8'd0, 32'd6};//{'dest': 142, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[866] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[867] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[868] = {6'd11, 8'd146, 8'd142, 32'd52};//{'dest': 146, 'src': 142, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[869] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[870] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[871] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592600232, 'op': 'memory_read_request'}
instructions[872] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[873] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592600232, 'op': 'memory_read_wait'}
instructions[874] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592600232, 'element_size': 2, 'op': 'memory_read'}
instructions[875] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[876] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[877] = {6'd25, 8'd140, 8'd141, 32'd2054};//{'src': 141, 'right': 2054, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[878] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[879] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[880] = {6'd13, 8'd0, 8'd140, 32'd894};//{'src': 140, 'label': 894, 'op': 'jmp_if_false'}
instructions[881] = {6'd0, 8'd142, 8'd0, 32'd10};//{'dest': 142, 'literal': 10, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[882] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[883] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[884] = {6'd11, 8'd146, 8'd142, 32'd52};//{'dest': 146, 'src': 142, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[885] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[886] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[887] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592600520, 'op': 'memory_read_request'}
instructions[888] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[889] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592600520, 'op': 'memory_read_wait'}
instructions[890] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592600520, 'element_size': 2, 'op': 'memory_read'}
instructions[891] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[892] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[893] = {6'd25, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[894] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[895] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[896] = {6'd13, 8'd0, 8'd140, 32'd1025};//{'src': 140, 'label': 1025, 'op': 'jmp_if_false'}
instructions[897] = {6'd0, 8'd142, 8'd0, 32'd14};//{'dest': 142, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[898] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[899] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[900] = {6'd11, 8'd146, 8'd142, 32'd52};//{'dest': 146, 'src': 142, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[901] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[902] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[903] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592613448, 'op': 'memory_read_request'}
instructions[904] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[905] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592613448, 'op': 'memory_read_wait'}
instructions[906] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592613448, 'element_size': 2, 'op': 'memory_read'}
instructions[907] = {6'd3, 8'd142, 8'd48, 32'd0};//{'dest': 142, 'src': 48, 'op': 'move'}
instructions[908] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[909] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[910] = {6'd28, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[911] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[912] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[913] = {6'd13, 8'd0, 8'd140, 32'd928};//{'src': 140, 'label': 928, 'op': 'jmp_if_false'}
instructions[914] = {6'd0, 8'd142, 8'd0, 32'd15};//{'dest': 142, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[915] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[916] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[917] = {6'd11, 8'd146, 8'd142, 32'd52};//{'dest': 146, 'src': 142, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[918] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[919] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[920] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592613736, 'op': 'memory_read_request'}
instructions[921] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[922] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592613736, 'op': 'memory_read_wait'}
instructions[923] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592613736, 'element_size': 2, 'op': 'memory_read'}
instructions[924] = {6'd3, 8'd142, 8'd49, 32'd0};//{'dest': 142, 'src': 49, 'op': 'move'}
instructions[925] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[926] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[927] = {6'd28, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[928] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[929] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[930] = {6'd13, 8'd0, 8'd140, 32'd1024};//{'src': 140, 'label': 1024, 'op': 'jmp_if_false'}
instructions[931] = {6'd3, 8'd140, 8'd48, 32'd0};//{'dest': 140, 'src': 48, 'op': 'move'}
instructions[932] = {6'd3, 8'd141, 8'd45, 32'd0};//{'dest': 141, 'src': 45, 'op': 'move'}
instructions[933] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[934] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[935] = {6'd11, 8'd142, 8'd141, 32'd40};//{'dest': 142, 'src': 141, 'srcb': 40, 'signed': False, 'op': '+'}
instructions[936] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[937] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[938] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[939] = {6'd3, 8'd140, 8'd49, 32'd0};//{'dest': 140, 'src': 49, 'op': 'move'}
instructions[940] = {6'd3, 8'd141, 8'd45, 32'd0};//{'dest': 141, 'src': 45, 'op': 'move'}
instructions[941] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[942] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[943] = {6'd11, 8'd142, 8'd141, 32'd41};//{'dest': 142, 'src': 141, 'srcb': 41, 'signed': False, 'op': '+'}
instructions[944] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[945] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[946] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[947] = {6'd0, 8'd146, 8'd0, 32'd11};//{'dest': 146, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[948] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[949] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[950] = {6'd11, 8'd147, 8'd146, 32'd52};//{'dest': 147, 'src': 146, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[951] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[952] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[953] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592615104, 'op': 'memory_read_request'}
instructions[954] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[955] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592615104, 'op': 'memory_read_wait'}
instructions[956] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709592615104, 'element_size': 2, 'op': 'memory_read'}
instructions[957] = {6'd3, 8'd141, 8'd45, 32'd0};//{'dest': 141, 'src': 45, 'op': 'move'}
instructions[958] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[959] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[960] = {6'd11, 8'd142, 8'd141, 32'd42};//{'dest': 142, 'src': 141, 'srcb': 42, 'signed': False, 'op': '+'}
instructions[961] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[962] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[963] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[964] = {6'd0, 8'd146, 8'd0, 32'd12};//{'dest': 146, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[965] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[966] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[967] = {6'd11, 8'd147, 8'd146, 32'd52};//{'dest': 147, 'src': 146, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[968] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[969] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[970] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592615536, 'op': 'memory_read_request'}
instructions[971] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[972] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592615536, 'op': 'memory_read_wait'}
instructions[973] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709592615536, 'element_size': 2, 'op': 'memory_read'}
instructions[974] = {6'd3, 8'd141, 8'd45, 32'd0};//{'dest': 141, 'src': 45, 'op': 'move'}
instructions[975] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[976] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[977] = {6'd11, 8'd142, 8'd141, 32'd43};//{'dest': 142, 'src': 141, 'srcb': 43, 'signed': False, 'op': '+'}
instructions[978] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[979] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[980] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[981] = {6'd0, 8'd146, 8'd0, 32'd13};//{'dest': 146, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[982] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[983] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[984] = {6'd11, 8'd147, 8'd146, 32'd52};//{'dest': 147, 'src': 146, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[985] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[986] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[987] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592615968, 'op': 'memory_read_request'}
instructions[988] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[989] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592615968, 'op': 'memory_read_wait'}
instructions[990] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709592615968, 'element_size': 2, 'op': 'memory_read'}
instructions[991] = {6'd3, 8'd141, 8'd45, 32'd0};//{'dest': 141, 'src': 45, 'op': 'move'}
instructions[992] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[993] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[994] = {6'd11, 8'd142, 8'd141, 32'd44};//{'dest': 142, 'src': 141, 'srcb': 44, 'signed': False, 'op': '+'}
instructions[995] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[996] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[997] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[998] = {6'd3, 8'd140, 8'd45, 32'd0};//{'dest': 140, 'src': 45, 'op': 'move'}
instructions[999] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1000] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1001] = {6'd3, 8'd53, 8'd140, 32'd0};//{'dest': 53, 'src': 140, 'op': 'move'}
instructions[1002] = {6'd3, 8'd140, 8'd45, 32'd0};//{'dest': 140, 'src': 45, 'op': 'move'}
instructions[1003] = {6'd14, 8'd45, 8'd45, 32'd1};//{'src': 45, 'right': 1, 'dest': 45, 'signed': False, 'op': '+', 'size': 2}
instructions[1004] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1005] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1006] = {6'd3, 8'd141, 8'd45, 32'd0};//{'dest': 141, 'src': 45, 'op': 'move'}
instructions[1007] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1008] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1009] = {6'd25, 8'd140, 8'd141, 32'd16};//{'src': 141, 'right': 16, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1010] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1011] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1012] = {6'd13, 8'd0, 8'd140, 32'd1018};//{'src': 140, 'label': 1018, 'op': 'jmp_if_false'}
instructions[1013] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1014] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1015] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1016] = {6'd3, 8'd45, 8'd140, 32'd0};//{'dest': 45, 'src': 140, 'op': 'move'}
instructions[1017] = {6'd15, 8'd0, 8'd0, 32'd1018};//{'label': 1018, 'op': 'goto'}
instructions[1018] = {6'd3, 8'd140, 8'd53, 32'd0};//{'dest': 140, 'src': 53, 'op': 'move'}
instructions[1019] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1020] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1021] = {6'd3, 8'd47, 8'd140, 32'd0};//{'dest': 47, 'src': 140, 'op': 'move'}
instructions[1022] = {6'd6, 8'd0, 8'd46, 32'd0};//{'src': 46, 'op': 'jmp_to_reg'}
instructions[1023] = {6'd15, 8'd0, 8'd0, 32'd1024};//{'label': 1024, 'op': 'goto'}
instructions[1024] = {6'd15, 8'd0, 8'd0, 32'd1025};//{'label': 1025, 'op': 'goto'}
instructions[1025] = {6'd15, 8'd0, 8'd0, 32'd813};//{'label': 813, 'op': 'goto'}
instructions[1026] = {6'd0, 8'd60, 8'd0, 32'd0};//{'dest': 60, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1027] = {6'd0, 8'd61, 8'd0, 32'd0};//{'dest': 61, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1028] = {6'd0, 8'd62, 8'd0, 32'd0};//{'dest': 62, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1029] = {6'd3, 8'd141, 8'd58, 32'd0};//{'dest': 141, 'src': 58, 'op': 'move'}
instructions[1030] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1031] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1032] = {6'd3, 8'd48, 8'd141, 32'd0};//{'dest': 48, 'src': 141, 'op': 'move'}
instructions[1033] = {6'd3, 8'd141, 8'd59, 32'd0};//{'dest': 141, 'src': 59, 'op': 'move'}
instructions[1034] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1035] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1036] = {6'd3, 8'd49, 8'd141, 32'd0};//{'dest': 49, 'src': 141, 'op': 'move'}
instructions[1037] = {6'd1, 8'd46, 8'd0, 32'd640};//{'dest': 46, 'label': 640, 'op': 'jmp_and_link'}
instructions[1038] = {6'd3, 8'd140, 8'd47, 32'd0};//{'dest': 140, 'src': 47, 'op': 'move'}
instructions[1039] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1040] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1041] = {6'd3, 8'd62, 8'd140, 32'd0};//{'dest': 62, 'src': 140, 'op': 'move'}
instructions[1042] = {6'd0, 8'd140, 8'd0, 32'd17664};//{'dest': 140, 'literal': 17664, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1043] = {6'd0, 8'd141, 8'd0, 32'd7};//{'dest': 141, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1044] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1045] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1046] = {6'd26, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': True, 'op': '+'}
instructions[1047] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1048] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1049] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1050] = {6'd3, 8'd140, 8'd56, 32'd0};//{'dest': 140, 'src': 56, 'op': 'move'}
instructions[1051] = {6'd0, 8'd141, 8'd0, 32'd8};//{'dest': 141, 'literal': 8, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1052] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1053] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1054] = {6'd11, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1055] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1056] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1057] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1058] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1059] = {6'd0, 8'd141, 8'd0, 32'd9};//{'dest': 141, 'literal': 9, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1060] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1061] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1062] = {6'd26, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': True, 'op': '+'}
instructions[1063] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1064] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1065] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1066] = {6'd0, 8'd140, 8'd0, 32'd16384};//{'dest': 140, 'literal': 16384, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1067] = {6'd0, 8'd141, 8'd0, 32'd10};//{'dest': 141, 'literal': 10, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1068] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1069] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1070] = {6'd26, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': True, 'op': '+'}
instructions[1071] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1072] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1073] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1074] = {6'd3, 8'd146, 8'd57, 32'd0};//{'dest': 146, 'src': 57, 'op': 'move'}
instructions[1075] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1076] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1077] = {6'd29, 8'd140, 8'd146, 32'd65280};//{'src': 146, 'dest': 140, 'signed': False, 'op': '|', 'size': 2, 'type': 'int', 'left': 65280}
instructions[1078] = {6'd0, 8'd141, 8'd0, 32'd11};//{'dest': 141, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1079] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1080] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1081] = {6'd11, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1082] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1083] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1084] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1085] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1086] = {6'd0, 8'd141, 8'd0, 32'd12};//{'dest': 141, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1087] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1088] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1089] = {6'd26, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': True, 'op': '+'}
instructions[1090] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1091] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1092] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1093] = {6'd0, 8'd140, 8'd0, 32'd49320};//{'dest': 140, 'literal': 49320, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1094] = {6'd0, 8'd141, 8'd0, 32'd13};//{'dest': 141, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1095] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1096] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1097] = {6'd11, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1098] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1099] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1100] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1101] = {6'd0, 8'd140, 8'd0, 32'd119};//{'dest': 140, 'literal': 119, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1102] = {6'd0, 8'd141, 8'd0, 32'd14};//{'dest': 141, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1103] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1104] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1105] = {6'd11, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1106] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1107] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1108] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1109] = {6'd3, 8'd140, 8'd58, 32'd0};//{'dest': 140, 'src': 58, 'op': 'move'}
instructions[1110] = {6'd0, 8'd141, 8'd0, 32'd15};//{'dest': 141, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1111] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1112] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1113] = {6'd11, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1114] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1115] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1116] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1117] = {6'd3, 8'd140, 8'd59, 32'd0};//{'dest': 140, 'src': 59, 'op': 'move'}
instructions[1118] = {6'd0, 8'd141, 8'd0, 32'd16};//{'dest': 141, 'literal': 16, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1119] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1120] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1121] = {6'd11, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1122] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1123] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1124] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1125] = {6'd3, 8'd141, 8'd56, 32'd0};//{'dest': 141, 'src': 56, 'op': 'move'}
instructions[1126] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1127] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1128] = {6'd14, 8'd140, 8'd141, 32'd14};//{'src': 141, 'right': 14, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1129] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1130] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1131] = {6'd3, 8'd60, 8'd140, 32'd0};//{'dest': 60, 'src': 140, 'op': 'move'}
instructions[1132] = {6'd1, 8'd12, 8'd0, 32'd59};//{'dest': 12, 'label': 59, 'op': 'jmp_and_link'}
instructions[1133] = {6'd0, 8'd140, 8'd0, 32'd7};//{'dest': 140, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1134] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1135] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1136] = {6'd3, 8'd61, 8'd140, 32'd0};//{'dest': 61, 'src': 140, 'op': 'move'}
instructions[1137] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1138] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1139] = {6'd3, 8'd141, 8'd61, 32'd0};//{'dest': 141, 'src': 61, 'op': 'move'}
instructions[1140] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1141] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1142] = {6'd30, 8'd140, 8'd141, 32'd16};//{'src': 141, 'right': 16, 'dest': 140, 'signed': False, 'op': '<=', 'type': 'int', 'size': 2}
instructions[1143] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1144] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1145] = {6'd13, 8'd0, 8'd140, 32'd1163};//{'src': 140, 'label': 1163, 'op': 'jmp_if_false'}
instructions[1146] = {6'd3, 8'd142, 8'd61, 32'd0};//{'dest': 142, 'src': 61, 'op': 'move'}
instructions[1147] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1148] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1149] = {6'd11, 8'd146, 8'd142, 32'd55};//{'dest': 146, 'src': 142, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1150] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1151] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1152] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592674248, 'op': 'memory_read_request'}
instructions[1153] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1154] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592674248, 'op': 'memory_read_wait'}
instructions[1155] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592674248, 'element_size': 2, 'op': 'memory_read'}
instructions[1156] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1157] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1158] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[1159] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[1160] = {6'd3, 8'd140, 8'd61, 32'd0};//{'dest': 140, 'src': 61, 'op': 'move'}
instructions[1161] = {6'd14, 8'd61, 8'd61, 32'd1};//{'src': 61, 'right': 1, 'dest': 61, 'signed': False, 'op': '+', 'size': 2}
instructions[1162] = {6'd15, 8'd0, 8'd0, 32'd1137};//{'label': 1137, 'op': 'goto'}
instructions[1163] = {6'd1, 8'd15, 8'd0, 32'd100};//{'dest': 15, 'label': 100, 'op': 'jmp_and_link'}
instructions[1164] = {6'd3, 8'd140, 8'd16, 32'd0};//{'dest': 140, 'src': 16, 'op': 'move'}
instructions[1165] = {6'd0, 8'd141, 8'd0, 32'd12};//{'dest': 141, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1166] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1167] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1168] = {6'd11, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1169] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1170] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1171] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1172] = {6'd3, 8'd141, 8'd60, 32'd0};//{'dest': 141, 'src': 60, 'op': 'move'}
instructions[1173] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1174] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1175] = {6'd27, 8'd140, 8'd141, 32'd64};//{'src': 141, 'right': 64, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[1176] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1177] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1178] = {6'd13, 8'd0, 8'd140, 32'd1184};//{'src': 140, 'label': 1184, 'op': 'jmp_if_false'}
instructions[1179] = {6'd0, 8'd140, 8'd0, 32'd64};//{'dest': 140, 'literal': 64, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1180] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1181] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1182] = {6'd3, 8'd60, 8'd140, 32'd0};//{'dest': 60, 'src': 140, 'op': 'move'}
instructions[1183] = {6'd15, 8'd0, 8'd0, 32'd1184};//{'label': 1184, 'op': 'goto'}
instructions[1184] = {6'd3, 8'd143, 8'd55, 32'd0};//{'dest': 143, 'src': 55, 'op': 'move'}
instructions[1185] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1186] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1187] = {6'd3, 8'd26, 8'd143, 32'd0};//{'dest': 26, 'src': 143, 'op': 'move'}
instructions[1188] = {6'd3, 8'd141, 8'd60, 32'd0};//{'dest': 141, 'src': 60, 'op': 'move'}
instructions[1189] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1190] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1191] = {6'd3, 8'd27, 8'd141, 32'd0};//{'dest': 27, 'src': 141, 'op': 'move'}
instructions[1192] = {6'd3, 8'd142, 8'd62, 32'd0};//{'dest': 142, 'src': 62, 'op': 'move'}
instructions[1193] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1194] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1195] = {6'd11, 8'd146, 8'd142, 32'd42};//{'dest': 146, 'src': 142, 'srcb': 42, 'signed': False, 'op': '+'}
instructions[1196] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1197] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1198] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592684232, 'op': 'memory_read_request'}
instructions[1199] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1200] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592684232, 'op': 'memory_read_wait'}
instructions[1201] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592684232, 'element_size': 2, 'op': 'memory_read'}
instructions[1202] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1203] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1204] = {6'd3, 8'd28, 8'd141, 32'd0};//{'dest': 28, 'src': 141, 'op': 'move'}
instructions[1205] = {6'd3, 8'd142, 8'd62, 32'd0};//{'dest': 142, 'src': 62, 'op': 'move'}
instructions[1206] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1207] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1208] = {6'd11, 8'd146, 8'd142, 32'd43};//{'dest': 146, 'src': 142, 'srcb': 43, 'signed': False, 'op': '+'}
instructions[1209] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1210] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1211] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592684376, 'op': 'memory_read_request'}
instructions[1212] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1213] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592684376, 'op': 'memory_read_wait'}
instructions[1214] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592684376, 'element_size': 2, 'op': 'memory_read'}
instructions[1215] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1216] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1217] = {6'd3, 8'd29, 8'd141, 32'd0};//{'dest': 29, 'src': 141, 'op': 'move'}
instructions[1218] = {6'd3, 8'd142, 8'd62, 32'd0};//{'dest': 142, 'src': 62, 'op': 'move'}
instructions[1219] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1220] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1221] = {6'd11, 8'd146, 8'd142, 32'd44};//{'dest': 146, 'src': 142, 'srcb': 44, 'signed': False, 'op': '+'}
instructions[1222] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1223] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1224] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592684520, 'op': 'memory_read_request'}
instructions[1225] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1226] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592684520, 'op': 'memory_read_wait'}
instructions[1227] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592684520, 'element_size': 2, 'op': 'memory_read'}
instructions[1228] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1229] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1230] = {6'd3, 8'd30, 8'd141, 32'd0};//{'dest': 30, 'src': 141, 'op': 'move'}
instructions[1231] = {6'd0, 8'd141, 8'd0, 32'd2048};//{'dest': 141, 'literal': 2048, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1232] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1233] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1234] = {6'd3, 8'd31, 8'd141, 32'd0};//{'dest': 31, 'src': 141, 'op': 'move'}
instructions[1235] = {6'd1, 8'd25, 8'd0, 32'd218};//{'dest': 25, 'label': 218, 'op': 'jmp_and_link'}
instructions[1236] = {6'd6, 8'd0, 8'd54, 32'd0};//{'src': 54, 'op': 'jmp_to_reg'}
instructions[1237] = {6'd0, 8'd66, 8'd0, 32'd0};//{'dest': 66, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1238] = {6'd0, 8'd67, 8'd0, 32'd0};//{'dest': 67, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1239] = {6'd0, 8'd68, 8'd0, 32'd0};//{'dest': 68, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1240] = {6'd0, 8'd69, 8'd0, 32'd0};//{'dest': 69, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1241] = {6'd0, 8'd70, 8'd0, 32'd0};//{'dest': 70, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1242] = {6'd0, 8'd71, 8'd0, 32'd0};//{'dest': 71, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1243] = {6'd0, 8'd72, 8'd0, 32'd0};//{'dest': 72, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1244] = {6'd0, 8'd73, 8'd0, 32'd0};//{'dest': 73, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1245] = {6'd0, 8'd74, 8'd0, 32'd0};//{'dest': 74, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1246] = {6'd3, 8'd143, 8'd65, 32'd0};//{'dest': 143, 'src': 65, 'op': 'move'}
instructions[1247] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1248] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1249] = {6'd3, 8'd36, 8'd143, 32'd0};//{'dest': 36, 'src': 143, 'op': 'move'}
instructions[1250] = {6'd1, 8'd34, 8'd0, 32'd328};//{'dest': 34, 'label': 328, 'op': 'jmp_and_link'}
instructions[1251] = {6'd3, 8'd140, 8'd35, 32'd0};//{'dest': 140, 'src': 35, 'op': 'move'}
instructions[1252] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1253] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1254] = {6'd3, 8'd74, 8'd140, 32'd0};//{'dest': 74, 'src': 140, 'op': 'move'}
instructions[1255] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1256] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1257] = {6'd3, 8'd141, 8'd74, 32'd0};//{'dest': 141, 'src': 74, 'op': 'move'}
instructions[1258] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1259] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1260] = {6'd25, 8'd140, 8'd141, 32'd0};//{'src': 141, 'right': 0, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1261] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1262] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1263] = {6'd13, 8'd0, 8'd140, 32'd1270};//{'src': 140, 'label': 1270, 'op': 'jmp_if_false'}
instructions[1264] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1265] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1266] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1267] = {6'd3, 8'd64, 8'd140, 32'd0};//{'dest': 64, 'src': 140, 'op': 'move'}
instructions[1268] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1269] = {6'd15, 8'd0, 8'd0, 32'd1270};//{'label': 1270, 'op': 'goto'}
instructions[1270] = {6'd0, 8'd142, 8'd0, 32'd6};//{'dest': 142, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1271] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1272] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1273] = {6'd11, 8'd146, 8'd142, 32'd65};//{'dest': 146, 'src': 142, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1274] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1275] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1276] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592685240, 'op': 'memory_read_request'}
instructions[1277] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1278] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592685240, 'op': 'memory_read_wait'}
instructions[1279] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592685240, 'element_size': 2, 'op': 'memory_read'}
instructions[1280] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1281] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1282] = {6'd31, 8'd140, 8'd141, 32'd2048};//{'src': 141, 'right': 2048, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[1283] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1284] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1285] = {6'd13, 8'd0, 8'd140, 32'd1292};//{'src': 140, 'label': 1292, 'op': 'jmp_if_false'}
instructions[1286] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1287] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1288] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1289] = {6'd3, 8'd64, 8'd140, 32'd0};//{'dest': 64, 'src': 140, 'op': 'move'}
instructions[1290] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1291] = {6'd15, 8'd0, 8'd0, 32'd1292};//{'label': 1292, 'op': 'goto'}
instructions[1292] = {6'd0, 8'd142, 8'd0, 32'd15};//{'dest': 142, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1293] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1294] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1295] = {6'd11, 8'd146, 8'd142, 32'd65};//{'dest': 146, 'src': 142, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1296] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1297] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1298] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592685744, 'op': 'memory_read_request'}
instructions[1299] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1300] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592685744, 'op': 'memory_read_wait'}
instructions[1301] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592685744, 'element_size': 2, 'op': 'memory_read'}
instructions[1302] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1303] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1304] = {6'd31, 8'd140, 8'd141, 32'd49320};//{'src': 141, 'right': 49320, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[1305] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1306] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1307] = {6'd13, 8'd0, 8'd140, 32'd1314};//{'src': 140, 'label': 1314, 'op': 'jmp_if_false'}
instructions[1308] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1309] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1310] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1311] = {6'd3, 8'd64, 8'd140, 32'd0};//{'dest': 64, 'src': 140, 'op': 'move'}
instructions[1312] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1313] = {6'd15, 8'd0, 8'd0, 32'd1314};//{'label': 1314, 'op': 'goto'}
instructions[1314] = {6'd0, 8'd142, 8'd0, 32'd16};//{'dest': 142, 'literal': 16, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1315] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1316] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1317] = {6'd11, 8'd146, 8'd142, 32'd65};//{'dest': 146, 'src': 142, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1318] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1319] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1320] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592686248, 'op': 'memory_read_request'}
instructions[1321] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1322] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592686248, 'op': 'memory_read_wait'}
instructions[1323] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592686248, 'element_size': 2, 'op': 'memory_read'}
instructions[1324] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1325] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1326] = {6'd31, 8'd140, 8'd141, 32'd119};//{'src': 141, 'right': 119, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[1327] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1328] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1329] = {6'd13, 8'd0, 8'd140, 32'd1336};//{'src': 140, 'label': 1336, 'op': 'jmp_if_false'}
instructions[1330] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1331] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1332] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1333] = {6'd3, 8'd64, 8'd140, 32'd0};//{'dest': 64, 'src': 140, 'op': 'move'}
instructions[1334] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1335] = {6'd15, 8'd0, 8'd0, 32'd1336};//{'label': 1336, 'op': 'goto'}
instructions[1336] = {6'd0, 8'd146, 8'd0, 32'd11};//{'dest': 146, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1337] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1338] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1339] = {6'd11, 8'd147, 8'd146, 32'd65};//{'dest': 147, 'src': 146, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1340] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1341] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1342] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592707440, 'op': 'memory_read_request'}
instructions[1343] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1344] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592707440, 'op': 'memory_read_wait'}
instructions[1345] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 139709592707440, 'element_size': 2, 'op': 'memory_read'}
instructions[1346] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1347] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1348] = {6'd12, 8'd141, 8'd142, 32'd255};//{'src': 142, 'right': 255, 'dest': 141, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[1349] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1350] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1351] = {6'd25, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1352] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1353] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1354] = {6'd13, 8'd0, 8'd140, 32'd1561};//{'src': 140, 'label': 1561, 'op': 'jmp_if_false'}
instructions[1355] = {6'd0, 8'd147, 8'd0, 32'd7};//{'dest': 147, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1356] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1357] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1358] = {6'd11, 8'd149, 8'd147, 32'd65};//{'dest': 149, 'src': 147, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1359] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1360] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1361] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139709592716424, 'op': 'memory_read_request'}
instructions[1362] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1363] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139709592716424, 'op': 'memory_read_wait'}
instructions[1364] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 139709592716424, 'element_size': 2, 'op': 'memory_read'}
instructions[1365] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1366] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1367] = {6'd32, 8'd142, 8'd146, 32'd8};//{'src': 146, 'right': 8, 'dest': 142, 'signed': False, 'op': '>>', 'type': 'int', 'size': 2}
instructions[1368] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1369] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1370] = {6'd12, 8'd141, 8'd142, 32'd15};//{'src': 142, 'right': 15, 'dest': 141, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[1371] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1372] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1373] = {6'd33, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '<<', 'type': 'int', 'size': 2}
instructions[1374] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1375] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1376] = {6'd3, 8'd67, 8'd140, 32'd0};//{'dest': 67, 'src': 140, 'op': 'move'}
instructions[1377] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1378] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1379] = {6'd3, 8'd141, 8'd67, 32'd0};//{'dest': 141, 'src': 67, 'op': 'move'}
instructions[1380] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1381] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1382] = {6'd14, 8'd140, 8'd141, 32'd7};//{'src': 141, 'right': 7, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1383] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1384] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1385] = {6'd3, 8'd68, 8'd140, 32'd0};//{'dest': 68, 'src': 140, 'op': 'move'}
instructions[1386] = {6'd0, 8'd141, 8'd0, 32'd8};//{'dest': 141, 'literal': 8, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1387] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1388] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1389] = {6'd11, 8'd142, 8'd141, 32'd65};//{'dest': 142, 'src': 141, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1390] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1391] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1392] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139709593443864, 'op': 'memory_read_request'}
instructions[1393] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1394] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139709593443864, 'op': 'memory_read_wait'}
instructions[1395] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 139709593443864, 'element_size': 2, 'op': 'memory_read'}
instructions[1396] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1397] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1398] = {6'd3, 8'd66, 8'd140, 32'd0};//{'dest': 66, 'src': 140, 'op': 'move'}
instructions[1399] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1400] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1401] = {6'd3, 8'd146, 8'd66, 32'd0};//{'dest': 146, 'src': 66, 'op': 'move'}
instructions[1402] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1403] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1404] = {6'd14, 8'd142, 8'd146, 32'd1};//{'src': 146, 'right': 1, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1405] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1406] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1407] = {6'd32, 8'd141, 8'd142, 32'd1};//{'src': 142, 'right': 1, 'dest': 141, 'signed': False, 'op': '>>', 'type': 'int', 'size': 2}
instructions[1408] = {6'd3, 8'd142, 8'd67, 32'd0};//{'dest': 142, 'src': 67, 'op': 'move'}
instructions[1409] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1410] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1411] = {6'd34, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[1412] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1413] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1414] = {6'd3, 8'd69, 8'd140, 32'd0};//{'dest': 69, 'src': 140, 'op': 'move'}
instructions[1415] = {6'd3, 8'd142, 8'd68, 32'd0};//{'dest': 142, 'src': 68, 'op': 'move'}
instructions[1416] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1417] = {6'd3, 8'd146, 8'd69, 32'd0};//{'dest': 146, 'src': 69, 'op': 'move'}
instructions[1418] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1419] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1420] = {6'd11, 8'd141, 8'd142, 32'd146};//{'srcb': 146, 'src': 142, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1421] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1422] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1423] = {6'd35, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[1424] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1425] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1426] = {6'd3, 8'd73, 8'd140, 32'd0};//{'dest': 73, 'src': 140, 'op': 'move'}
instructions[1427] = {6'd3, 8'd142, 8'd68, 32'd0};//{'dest': 142, 'src': 68, 'op': 'move'}
instructions[1428] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1429] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1430] = {6'd11, 8'd146, 8'd142, 32'd65};//{'dest': 146, 'src': 142, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1431] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1432] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1433] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592709960, 'op': 'memory_read_request'}
instructions[1434] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1435] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592709960, 'op': 'memory_read_wait'}
instructions[1436] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592709960, 'element_size': 2, 'op': 'memory_read'}
instructions[1437] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1438] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1439] = {6'd25, 8'd140, 8'd141, 32'd2048};//{'src': 141, 'right': 2048, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1440] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1441] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1442] = {6'd13, 8'd0, 8'd140, 32'd1555};//{'src': 140, 'label': 1555, 'op': 'jmp_if_false'}
instructions[1443] = {6'd0, 8'd140, 8'd0, 32'd19};//{'dest': 140, 'literal': 19, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1444] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1445] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1446] = {6'd3, 8'd72, 8'd140, 32'd0};//{'dest': 72, 'src': 140, 'op': 'move'}
instructions[1447] = {6'd1, 8'd12, 8'd0, 32'd59};//{'dest': 12, 'label': 59, 'op': 'jmp_and_link'}
instructions[1448] = {6'd3, 8'd141, 8'd68, 32'd0};//{'dest': 141, 'src': 68, 'op': 'move'}
instructions[1449] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1450] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1451] = {6'd14, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1452] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1453] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1454] = {6'd3, 8'd71, 8'd140, 32'd0};//{'dest': 71, 'src': 140, 'op': 'move'}
instructions[1455] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1456] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1457] = {6'd3, 8'd141, 8'd71, 32'd0};//{'dest': 141, 'src': 71, 'op': 'move'}
instructions[1458] = {6'd3, 8'd142, 8'd73, 32'd0};//{'dest': 142, 'src': 73, 'op': 'move'}
instructions[1459] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1460] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1461] = {6'd36, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<=', 'type': 'int', 'size': 2}
instructions[1462] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1463] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1464] = {6'd13, 8'd0, 8'd140, 32'd1498};//{'src': 140, 'label': 1498, 'op': 'jmp_if_false'}
instructions[1465] = {6'd3, 8'd141, 8'd71, 32'd0};//{'dest': 141, 'src': 71, 'op': 'move'}
instructions[1466] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1467] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1468] = {6'd11, 8'd142, 8'd141, 32'd65};//{'dest': 142, 'src': 141, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1469] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1470] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1471] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139709592709240, 'op': 'memory_read_request'}
instructions[1472] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1473] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139709592709240, 'op': 'memory_read_wait'}
instructions[1474] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 139709592709240, 'element_size': 2, 'op': 'memory_read'}
instructions[1475] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1476] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1477] = {6'd3, 8'd70, 8'd140, 32'd0};//{'dest': 70, 'src': 140, 'op': 'move'}
instructions[1478] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1479] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1480] = {6'd3, 8'd141, 8'd70, 32'd0};//{'dest': 141, 'src': 70, 'op': 'move'}
instructions[1481] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1482] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1483] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[1484] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[1485] = {6'd3, 8'd140, 8'd70, 32'd0};//{'dest': 140, 'src': 70, 'op': 'move'}
instructions[1486] = {6'd3, 8'd141, 8'd72, 32'd0};//{'dest': 141, 'src': 72, 'op': 'move'}
instructions[1487] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1488] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1489] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[1490] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1491] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1492] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1493] = {6'd3, 8'd140, 8'd72, 32'd0};//{'dest': 140, 'src': 72, 'op': 'move'}
instructions[1494] = {6'd14, 8'd72, 8'd72, 32'd1};//{'src': 72, 'right': 1, 'dest': 72, 'signed': False, 'op': '+', 'size': 2}
instructions[1495] = {6'd3, 8'd140, 8'd71, 32'd0};//{'dest': 140, 'src': 71, 'op': 'move'}
instructions[1496] = {6'd14, 8'd71, 8'd71, 32'd1};//{'src': 71, 'right': 1, 'dest': 71, 'signed': False, 'op': '+', 'size': 2}
instructions[1497] = {6'd15, 8'd0, 8'd0, 32'd1455};//{'label': 1455, 'op': 'goto'}
instructions[1498] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1499] = {6'd0, 8'd141, 8'd0, 32'd17};//{'dest': 141, 'literal': 17, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1500] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1501] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1502] = {6'd26, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': True, 'op': '+'}
instructions[1503] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1504] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1505] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1506] = {6'd1, 8'd15, 8'd0, 32'd100};//{'dest': 15, 'label': 100, 'op': 'jmp_and_link'}
instructions[1507] = {6'd3, 8'd140, 8'd16, 32'd0};//{'dest': 140, 'src': 16, 'op': 'move'}
instructions[1508] = {6'd0, 8'd141, 8'd0, 32'd18};//{'dest': 141, 'literal': 18, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1509] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1510] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1511] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[1512] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1513] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1514] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1515] = {6'd3, 8'd148, 8'd10, 32'd0};//{'dest': 148, 'src': 10, 'op': 'move'}
instructions[1516] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1517] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1518] = {6'd3, 8'd55, 8'd148, 32'd0};//{'dest': 55, 'src': 148, 'op': 'move'}
instructions[1519] = {6'd3, 8'd141, 8'd66, 32'd0};//{'dest': 141, 'src': 66, 'op': 'move'}
instructions[1520] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1521] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1522] = {6'd3, 8'd56, 8'd141, 32'd0};//{'dest': 56, 'src': 141, 'op': 'move'}
instructions[1523] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1524] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1525] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1526] = {6'd3, 8'd57, 8'd141, 32'd0};//{'dest': 57, 'src': 141, 'op': 'move'}
instructions[1527] = {6'd0, 8'd142, 8'd0, 32'd13};//{'dest': 142, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1528] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1529] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1530] = {6'd11, 8'd146, 8'd142, 32'd65};//{'dest': 146, 'src': 142, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1531] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1532] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1533] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709593456936, 'op': 'memory_read_request'}
instructions[1534] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1535] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709593456936, 'op': 'memory_read_wait'}
instructions[1536] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709593456936, 'element_size': 2, 'op': 'memory_read'}
instructions[1537] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1538] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1539] = {6'd3, 8'd58, 8'd141, 32'd0};//{'dest': 58, 'src': 141, 'op': 'move'}
instructions[1540] = {6'd0, 8'd142, 8'd0, 32'd14};//{'dest': 142, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1541] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1542] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1543] = {6'd11, 8'd146, 8'd142, 32'd65};//{'dest': 146, 'src': 142, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1544] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1545] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1546] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709593457080, 'op': 'memory_read_request'}
instructions[1547] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1548] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709593457080, 'op': 'memory_read_wait'}
instructions[1549] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709593457080, 'element_size': 2, 'op': 'memory_read'}
instructions[1550] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1551] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1552] = {6'd3, 8'd59, 8'd141, 32'd0};//{'dest': 59, 'src': 141, 'op': 'move'}
instructions[1553] = {6'd1, 8'd54, 8'd0, 32'd1026};//{'dest': 54, 'label': 1026, 'op': 'jmp_and_link'}
instructions[1554] = {6'd15, 8'd0, 8'd0, 32'd1555};//{'label': 1555, 'op': 'goto'}
instructions[1555] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1556] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1557] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1558] = {6'd3, 8'd64, 8'd140, 32'd0};//{'dest': 64, 'src': 140, 'op': 'move'}
instructions[1559] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1560] = {6'd15, 8'd0, 8'd0, 32'd1561};//{'label': 1561, 'op': 'goto'}
instructions[1561] = {6'd0, 8'd146, 8'd0, 32'd11};//{'dest': 146, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1562] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1563] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1564] = {6'd11, 8'd147, 8'd146, 32'd65};//{'dest': 147, 'src': 146, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1565] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1566] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1567] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709593457512, 'op': 'memory_read_request'}
instructions[1568] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1569] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709593457512, 'op': 'memory_read_wait'}
instructions[1570] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 139709593457512, 'element_size': 2, 'op': 'memory_read'}
instructions[1571] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1572] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1573] = {6'd12, 8'd141, 8'd142, 32'd255};//{'src': 142, 'right': 255, 'dest': 141, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[1574] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1575] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1576] = {6'd31, 8'd140, 8'd141, 32'd6};//{'src': 141, 'right': 6, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[1577] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1578] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1579] = {6'd13, 8'd0, 8'd140, 32'd1586};//{'src': 140, 'label': 1586, 'op': 'jmp_if_false'}
instructions[1580] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1581] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1582] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1583] = {6'd3, 8'd64, 8'd140, 32'd0};//{'dest': 64, 'src': 140, 'op': 'move'}
instructions[1584] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1585] = {6'd15, 8'd0, 8'd0, 32'd1586};//{'label': 1586, 'op': 'goto'}
instructions[1586] = {6'd3, 8'd140, 8'd74, 32'd0};//{'dest': 140, 'src': 74, 'op': 'move'}
instructions[1587] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1588] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1589] = {6'd3, 8'd64, 8'd140, 32'd0};//{'dest': 64, 'src': 140, 'op': 'move'}
instructions[1590] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1591] = {6'd0, 8'd100, 8'd0, 32'd17};//{'dest': 100, 'literal': 17, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1592] = {6'd0, 8'd101, 8'd0, 32'd0};//{'dest': 101, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1593] = {6'd0, 8'd102, 8'd0, 32'd0};//{'dest': 102, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1594] = {6'd0, 8'd103, 8'd0, 32'd0};//{'dest': 103, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1595] = {6'd3, 8'd140, 8'd77, 32'd0};//{'dest': 140, 'src': 77, 'op': 'move'}
instructions[1596] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1597] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1598] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1599] = {6'd14, 8'd141, 8'd146, 32'd0};//{'src': 146, 'right': 0, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1600] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1601] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1602] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1603] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1604] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1605] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1606] = {6'd3, 8'd140, 8'd78, 32'd0};//{'dest': 140, 'src': 78, 'op': 'move'}
instructions[1607] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1608] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1609] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1610] = {6'd14, 8'd141, 8'd146, 32'd1};//{'src': 146, 'right': 1, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1611] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1612] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1613] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1614] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1615] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1616] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1617] = {6'd0, 8'd146, 8'd0, 32'd1};//{'dest': 146, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1618] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1619] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1620] = {6'd11, 8'd147, 8'd146, 32'd79};//{'dest': 147, 'src': 146, 'srcb': 79, 'signed': False, 'op': '+'}
instructions[1621] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1622] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1623] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709593471960, 'op': 'memory_read_request'}
instructions[1624] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1625] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709593471960, 'op': 'memory_read_wait'}
instructions[1626] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709593471960, 'element_size': 2, 'op': 'memory_read'}
instructions[1627] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1628] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1629] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1630] = {6'd14, 8'd141, 8'd146, 32'd2};//{'src': 146, 'right': 2, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1631] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1632] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1633] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1634] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1635] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1636] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1637] = {6'd0, 8'd146, 8'd0, 32'd0};//{'dest': 146, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1638] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1639] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1640] = {6'd11, 8'd147, 8'd146, 32'd79};//{'dest': 147, 'src': 146, 'srcb': 79, 'signed': False, 'op': '+'}
instructions[1641] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1642] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1643] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709593472536, 'op': 'memory_read_request'}
instructions[1644] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1645] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709593472536, 'op': 'memory_read_wait'}
instructions[1646] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709593472536, 'element_size': 2, 'op': 'memory_read'}
instructions[1647] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1648] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1649] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1650] = {6'd14, 8'd141, 8'd146, 32'd3};//{'src': 146, 'right': 3, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1651] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1652] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1653] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1654] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1655] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1656] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1657] = {6'd0, 8'd146, 8'd0, 32'd1};//{'dest': 146, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1658] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1659] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1660] = {6'd11, 8'd147, 8'd146, 32'd81};//{'dest': 147, 'src': 146, 'srcb': 81, 'signed': False, 'op': '+'}
instructions[1661] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1662] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1663] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592240424, 'op': 'memory_read_request'}
instructions[1664] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1665] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592240424, 'op': 'memory_read_wait'}
instructions[1666] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709592240424, 'element_size': 2, 'op': 'memory_read'}
instructions[1667] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1668] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1669] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1670] = {6'd14, 8'd141, 8'd146, 32'd4};//{'src': 146, 'right': 4, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1671] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1672] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1673] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1674] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1675] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1676] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1677] = {6'd0, 8'd146, 8'd0, 32'd0};//{'dest': 146, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1678] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1679] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1680] = {6'd11, 8'd147, 8'd146, 32'd81};//{'dest': 147, 'src': 146, 'srcb': 81, 'signed': False, 'op': '+'}
instructions[1681] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1682] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1683] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592240856, 'op': 'memory_read_request'}
instructions[1684] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1685] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592240856, 'op': 'memory_read_wait'}
instructions[1686] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709592240856, 'element_size': 2, 'op': 'memory_read'}
instructions[1687] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1688] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1689] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1690] = {6'd14, 8'd141, 8'd146, 32'd5};//{'src': 146, 'right': 5, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1691] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1692] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1693] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1694] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1695] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1696] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1697] = {6'd0, 8'd140, 8'd0, 32'd20480};//{'dest': 140, 'literal': 20480, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1698] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1699] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1700] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1701] = {6'd14, 8'd141, 8'd146, 32'd6};//{'src': 146, 'right': 6, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1702] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1703] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1704] = {6'd26, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': True, 'op': '+'}
instructions[1705] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1706] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1707] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1708] = {6'd3, 8'd140, 8'd82, 32'd0};//{'dest': 140, 'src': 82, 'op': 'move'}
instructions[1709] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1710] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1711] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1712] = {6'd14, 8'd141, 8'd146, 32'd7};//{'src': 146, 'right': 7, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1713] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1714] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1715] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1716] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1717] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1718] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1719] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1720] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1721] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1722] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1723] = {6'd14, 8'd141, 8'd146, 32'd8};//{'src': 146, 'right': 8, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1724] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1725] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1726] = {6'd26, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': True, 'op': '+'}
instructions[1727] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1728] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1729] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1730] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1731] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1732] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1733] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1734] = {6'd14, 8'd141, 8'd146, 32'd9};//{'src': 146, 'right': 9, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1735] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1736] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1737] = {6'd26, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': True, 'op': '+'}
instructions[1738] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1739] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1740] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1741] = {6'd3, 8'd140, 8'd83, 32'd0};//{'dest': 140, 'src': 83, 'op': 'move'}
instructions[1742] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1743] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1744] = {6'd13, 8'd0, 8'd140, 32'd1772};//{'src': 140, 'label': 1772, 'op': 'jmp_if_false'}
instructions[1745] = {6'd3, 8'd150, 8'd100, 32'd0};//{'dest': 150, 'src': 100, 'op': 'move'}
instructions[1746] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1747] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1748] = {6'd14, 8'd147, 8'd150, 32'd6};//{'src': 150, 'right': 6, 'dest': 147, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1749] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1750] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1751] = {6'd11, 8'd149, 8'd147, 32'd98};//{'dest': 149, 'src': 147, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1752] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1753] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1754] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139709592243736, 'op': 'memory_read_request'}
instructions[1755] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1756] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139709592243736, 'op': 'memory_read_wait'}
instructions[1757] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 139709592243736, 'element_size': 2, 'op': 'memory_read'}
instructions[1758] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1759] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1760] = {6'd37, 8'd140, 8'd146, 32'd1};//{'src': 146, 'right': 1, 'dest': 140, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1761] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1762] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1763] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1764] = {6'd14, 8'd141, 8'd146, 32'd6};//{'src': 146, 'right': 6, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1765] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1766] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1767] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1768] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1769] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1770] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1771] = {6'd15, 8'd0, 8'd0, 32'd1772};//{'label': 1772, 'op': 'goto'}
instructions[1772] = {6'd3, 8'd140, 8'd84, 32'd0};//{'dest': 140, 'src': 84, 'op': 'move'}
instructions[1773] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1774] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1775] = {6'd13, 8'd0, 8'd140, 32'd1803};//{'src': 140, 'label': 1803, 'op': 'jmp_if_false'}
instructions[1776] = {6'd3, 8'd150, 8'd100, 32'd0};//{'dest': 150, 'src': 100, 'op': 'move'}
instructions[1777] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1778] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1779] = {6'd14, 8'd147, 8'd150, 32'd6};//{'src': 150, 'right': 6, 'dest': 147, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1780] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1781] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1782] = {6'd11, 8'd149, 8'd147, 32'd98};//{'dest': 149, 'src': 147, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1783] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1784] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1785] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139709592244168, 'op': 'memory_read_request'}
instructions[1786] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1787] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139709592244168, 'op': 'memory_read_wait'}
instructions[1788] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 139709592244168, 'element_size': 2, 'op': 'memory_read'}
instructions[1789] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1790] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1791] = {6'd37, 8'd140, 8'd146, 32'd2};//{'src': 146, 'right': 2, 'dest': 140, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1792] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1793] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1794] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1795] = {6'd14, 8'd141, 8'd146, 32'd6};//{'src': 146, 'right': 6, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1796] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1797] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1798] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1799] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1800] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1801] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1802] = {6'd15, 8'd0, 8'd0, 32'd1803};//{'label': 1803, 'op': 'goto'}
instructions[1803] = {6'd3, 8'd140, 8'd85, 32'd0};//{'dest': 140, 'src': 85, 'op': 'move'}
instructions[1804] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1805] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1806] = {6'd13, 8'd0, 8'd140, 32'd1834};//{'src': 140, 'label': 1834, 'op': 'jmp_if_false'}
instructions[1807] = {6'd3, 8'd150, 8'd100, 32'd0};//{'dest': 150, 'src': 100, 'op': 'move'}
instructions[1808] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1809] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1810] = {6'd14, 8'd147, 8'd150, 32'd6};//{'src': 150, 'right': 6, 'dest': 147, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1811] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1812] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1813] = {6'd11, 8'd149, 8'd147, 32'd98};//{'dest': 149, 'src': 147, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1814] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1815] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1816] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139709593486328, 'op': 'memory_read_request'}
instructions[1817] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1818] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139709593486328, 'op': 'memory_read_wait'}
instructions[1819] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 139709593486328, 'element_size': 2, 'op': 'memory_read'}
instructions[1820] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1821] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1822] = {6'd37, 8'd140, 8'd146, 32'd4};//{'src': 146, 'right': 4, 'dest': 140, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1823] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1824] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1825] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1826] = {6'd14, 8'd141, 8'd146, 32'd6};//{'src': 146, 'right': 6, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1827] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1828] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1829] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1830] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1831] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1832] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1833] = {6'd15, 8'd0, 8'd0, 32'd1834};//{'label': 1834, 'op': 'goto'}
instructions[1834] = {6'd3, 8'd140, 8'd86, 32'd0};//{'dest': 140, 'src': 86, 'op': 'move'}
instructions[1835] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1836] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1837] = {6'd13, 8'd0, 8'd140, 32'd1865};//{'src': 140, 'label': 1865, 'op': 'jmp_if_false'}
instructions[1838] = {6'd3, 8'd150, 8'd100, 32'd0};//{'dest': 150, 'src': 100, 'op': 'move'}
instructions[1839] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1840] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1841] = {6'd14, 8'd147, 8'd150, 32'd6};//{'src': 150, 'right': 6, 'dest': 147, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1842] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1843] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1844] = {6'd11, 8'd149, 8'd147, 32'd98};//{'dest': 149, 'src': 147, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1845] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1846] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1847] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139709593487048, 'op': 'memory_read_request'}
instructions[1848] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1849] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139709593487048, 'op': 'memory_read_wait'}
instructions[1850] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 139709593487048, 'element_size': 2, 'op': 'memory_read'}
instructions[1851] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1852] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1853] = {6'd37, 8'd140, 8'd146, 32'd8};//{'src': 146, 'right': 8, 'dest': 140, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1854] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1855] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1856] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1857] = {6'd14, 8'd141, 8'd146, 32'd6};//{'src': 146, 'right': 6, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1858] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1859] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1860] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1861] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1862] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1863] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1864] = {6'd15, 8'd0, 8'd0, 32'd1865};//{'label': 1865, 'op': 'goto'}
instructions[1865] = {6'd3, 8'd140, 8'd87, 32'd0};//{'dest': 140, 'src': 87, 'op': 'move'}
instructions[1866] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1867] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1868] = {6'd13, 8'd0, 8'd140, 32'd1896};//{'src': 140, 'label': 1896, 'op': 'jmp_if_false'}
instructions[1869] = {6'd3, 8'd150, 8'd100, 32'd0};//{'dest': 150, 'src': 100, 'op': 'move'}
instructions[1870] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1871] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1872] = {6'd14, 8'd147, 8'd150, 32'd6};//{'src': 150, 'right': 6, 'dest': 147, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1873] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1874] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1875] = {6'd11, 8'd149, 8'd147, 32'd98};//{'dest': 149, 'src': 147, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1876] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1877] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1878] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139709593487768, 'op': 'memory_read_request'}
instructions[1879] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1880] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139709593487768, 'op': 'memory_read_wait'}
instructions[1881] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 139709593487768, 'element_size': 2, 'op': 'memory_read'}
instructions[1882] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1883] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1884] = {6'd37, 8'd140, 8'd146, 32'd16};//{'src': 146, 'right': 16, 'dest': 140, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1885] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1886] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1887] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1888] = {6'd14, 8'd141, 8'd146, 32'd6};//{'src': 146, 'right': 6, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1889] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1890] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1891] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1892] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1893] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1894] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1895] = {6'd15, 8'd0, 8'd0, 32'd1896};//{'label': 1896, 'op': 'goto'}
instructions[1896] = {6'd3, 8'd140, 8'd88, 32'd0};//{'dest': 140, 'src': 88, 'op': 'move'}
instructions[1897] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1898] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1899] = {6'd13, 8'd0, 8'd140, 32'd1927};//{'src': 140, 'label': 1927, 'op': 'jmp_if_false'}
instructions[1900] = {6'd3, 8'd150, 8'd100, 32'd0};//{'dest': 150, 'src': 100, 'op': 'move'}
instructions[1901] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1902] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1903] = {6'd14, 8'd147, 8'd150, 32'd6};//{'src': 150, 'right': 6, 'dest': 147, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1904] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1905] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1906] = {6'd11, 8'd149, 8'd147, 32'd98};//{'dest': 149, 'src': 147, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1907] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1908] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1909] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139709593488488, 'op': 'memory_read_request'}
instructions[1910] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1911] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139709593488488, 'op': 'memory_read_wait'}
instructions[1912] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 139709593488488, 'element_size': 2, 'op': 'memory_read'}
instructions[1913] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1914] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1915] = {6'd37, 8'd140, 8'd146, 32'd32};//{'src': 146, 'right': 32, 'dest': 140, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1916] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1917] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1918] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1919] = {6'd14, 8'd141, 8'd146, 32'd6};//{'src': 146, 'right': 6, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1920] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1921] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1922] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1923] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1924] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1925] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1926] = {6'd15, 8'd0, 8'd0, 32'd1927};//{'label': 1927, 'op': 'goto'}
instructions[1927] = {6'd1, 8'd12, 8'd0, 32'd59};//{'dest': 12, 'label': 59, 'op': 'jmp_and_link'}
instructions[1928] = {6'd0, 8'd141, 8'd0, 32'd49320};//{'dest': 141, 'literal': 49320, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1929] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1930] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1931] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[1932] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[1933] = {6'd0, 8'd141, 8'd0, 32'd119};//{'dest': 141, 'literal': 119, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1934] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1935] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1936] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[1937] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[1938] = {6'd3, 8'd141, 8'd75, 32'd0};//{'dest': 141, 'src': 75, 'op': 'move'}
instructions[1939] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1940] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1941] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[1942] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[1943] = {6'd3, 8'd141, 8'd76, 32'd0};//{'dest': 141, 'src': 76, 'op': 'move'}
instructions[1944] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1945] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1946] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[1947] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[1948] = {6'd0, 8'd141, 8'd0, 32'd6};//{'dest': 141, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1949] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1950] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1951] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[1952] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[1953] = {6'd3, 8'd142, 8'd99, 32'd0};//{'dest': 142, 'src': 99, 'op': 'move'}
instructions[1954] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1955] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1956] = {6'd14, 8'd141, 8'd142, 32'd20};//{'src': 142, 'right': 20, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1957] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1958] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1959] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[1960] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[1961] = {6'd3, 8'd146, 8'd99, 32'd0};//{'dest': 146, 'src': 99, 'op': 'move'}
instructions[1962] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1963] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1964] = {6'd14, 8'd142, 8'd146, 32'd20};//{'src': 146, 'right': 20, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1965] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1966] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1967] = {6'd14, 8'd141, 8'd142, 32'd1};//{'src': 142, 'right': 1, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1968] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1969] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1970] = {6'd32, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '>>', 'type': 'int', 'size': 2}
instructions[1971] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1972] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1973] = {6'd3, 8'd101, 8'd140, 32'd0};//{'dest': 101, 'src': 140, 'op': 'move'}
instructions[1974] = {6'd3, 8'd140, 8'd100, 32'd0};//{'dest': 140, 'src': 100, 'op': 'move'}
instructions[1975] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1976] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1977] = {6'd3, 8'd102, 8'd140, 32'd0};//{'dest': 102, 'src': 140, 'op': 'move'}
instructions[1978] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1979] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1980] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1981] = {6'd3, 8'd103, 8'd140, 32'd0};//{'dest': 103, 'src': 140, 'op': 'move'}
instructions[1982] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1983] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1984] = {6'd3, 8'd141, 8'd103, 32'd0};//{'dest': 141, 'src': 103, 'op': 'move'}
instructions[1985] = {6'd3, 8'd142, 8'd101, 32'd0};//{'dest': 142, 'src': 101, 'op': 'move'}
instructions[1986] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1987] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1988] = {6'd20, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[1989] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1990] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1991] = {6'd13, 8'd0, 8'd140, 32'd2011};//{'src': 140, 'label': 2011, 'op': 'jmp_if_false'}
instructions[1992] = {6'd3, 8'd142, 8'd102, 32'd0};//{'dest': 142, 'src': 102, 'op': 'move'}
instructions[1993] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1994] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1995] = {6'd11, 8'd146, 8'd142, 32'd98};//{'dest': 146, 'src': 142, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1996] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1997] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1998] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592280384, 'op': 'memory_read_request'}
instructions[1999] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2000] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592280384, 'op': 'memory_read_wait'}
instructions[2001] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592280384, 'element_size': 2, 'op': 'memory_read'}
instructions[2002] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2003] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2004] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[2005] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[2006] = {6'd3, 8'd140, 8'd102, 32'd0};//{'dest': 140, 'src': 102, 'op': 'move'}
instructions[2007] = {6'd14, 8'd102, 8'd102, 32'd1};//{'src': 102, 'right': 1, 'dest': 102, 'signed': False, 'op': '+', 'size': 2}
instructions[2008] = {6'd3, 8'd140, 8'd103, 32'd0};//{'dest': 140, 'src': 103, 'op': 'move'}
instructions[2009] = {6'd14, 8'd103, 8'd103, 32'd1};//{'src': 103, 'right': 1, 'dest': 103, 'signed': False, 'op': '+', 'size': 2}
instructions[2010] = {6'd15, 8'd0, 8'd0, 32'd1982};//{'label': 1982, 'op': 'goto'}
instructions[2011] = {6'd1, 8'd15, 8'd0, 32'd100};//{'dest': 15, 'label': 100, 'op': 'jmp_and_link'}
instructions[2012] = {6'd3, 8'd140, 8'd16, 32'd0};//{'dest': 140, 'src': 16, 'op': 'move'}
instructions[2013] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[2014] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2015] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2016] = {6'd14, 8'd141, 8'd146, 32'd8};//{'src': 146, 'right': 8, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2017] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2018] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2019] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[2020] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2021] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2022] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2023] = {6'd3, 8'd143, 8'd98, 32'd0};//{'dest': 143, 'src': 98, 'op': 'move'}
instructions[2024] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2025] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2026] = {6'd3, 8'd55, 8'd143, 32'd0};//{'dest': 55, 'src': 143, 'op': 'move'}
instructions[2027] = {6'd3, 8'd142, 8'd99, 32'd0};//{'dest': 142, 'src': 99, 'op': 'move'}
instructions[2028] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2029] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2030] = {6'd14, 8'd141, 8'd142, 32'd40};//{'src': 142, 'right': 40, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2031] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2032] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2033] = {6'd3, 8'd56, 8'd141, 32'd0};//{'dest': 56, 'src': 141, 'op': 'move'}
instructions[2034] = {6'd0, 8'd141, 8'd0, 32'd6};//{'dest': 141, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2035] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2036] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2037] = {6'd3, 8'd57, 8'd141, 32'd0};//{'dest': 57, 'src': 141, 'op': 'move'}
instructions[2038] = {6'd3, 8'd141, 8'd75, 32'd0};//{'dest': 141, 'src': 75, 'op': 'move'}
instructions[2039] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2040] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2041] = {6'd3, 8'd58, 8'd141, 32'd0};//{'dest': 58, 'src': 141, 'op': 'move'}
instructions[2042] = {6'd3, 8'd141, 8'd76, 32'd0};//{'dest': 141, 'src': 76, 'op': 'move'}
instructions[2043] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2044] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2045] = {6'd3, 8'd59, 8'd141, 32'd0};//{'dest': 59, 'src': 141, 'op': 'move'}
instructions[2046] = {6'd1, 8'd54, 8'd0, 32'd1026};//{'dest': 54, 'label': 1026, 'op': 'jmp_and_link'}
instructions[2047] = {6'd6, 8'd0, 8'd97, 32'd0};//{'src': 97, 'op': 'jmp_to_reg'}
instructions[2048] = {6'd0, 8'd109, 8'd0, 32'd0};//{'dest': 109, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2049] = {6'd0, 8'd110, 8'd0, 32'd0};//{'dest': 110, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2050] = {6'd0, 8'd111, 8'd0, 32'd0};//{'dest': 111, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2051] = {6'd0, 8'd112, 8'd0, 32'd0};//{'dest': 112, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2052] = {6'd0, 8'd113, 8'd0, 32'd0};//{'dest': 113, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2053] = {6'd0, 8'd114, 8'd0, 32'd0};//{'dest': 114, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2054] = {6'd3, 8'd143, 8'd108, 32'd0};//{'dest': 143, 'src': 108, 'op': 'move'}
instructions[2055] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2056] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2057] = {6'd3, 8'd65, 8'd143, 32'd0};//{'dest': 65, 'src': 143, 'op': 'move'}
instructions[2058] = {6'd1, 8'd63, 8'd0, 32'd1237};//{'dest': 63, 'label': 1237, 'op': 'jmp_and_link'}
instructions[2059] = {6'd3, 8'd140, 8'd64, 32'd0};//{'dest': 140, 'src': 64, 'op': 'move'}
instructions[2060] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2061] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2062] = {6'd3, 8'd109, 8'd140, 32'd0};//{'dest': 109, 'src': 140, 'op': 'move'}
instructions[2063] = {6'd0, 8'd147, 8'd0, 32'd7};//{'dest': 147, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2064] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2065] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2066] = {6'd11, 8'd149, 8'd147, 32'd108};//{'dest': 149, 'src': 147, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2067] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2068] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2069] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139709592314656, 'op': 'memory_read_request'}
instructions[2070] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2071] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139709592314656, 'op': 'memory_read_wait'}
instructions[2072] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 139709592314656, 'element_size': 2, 'op': 'memory_read'}
instructions[2073] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2074] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2075] = {6'd32, 8'd142, 8'd146, 32'd8};//{'src': 146, 'right': 8, 'dest': 142, 'signed': False, 'op': '>>', 'type': 'int', 'size': 2}
instructions[2076] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2077] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2078] = {6'd12, 8'd141, 8'd142, 32'd15};//{'src': 142, 'right': 15, 'dest': 141, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2079] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2080] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2081] = {6'd33, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '<<', 'type': 'int', 'size': 2}
instructions[2082] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2083] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2084] = {6'd3, 8'd110, 8'd140, 32'd0};//{'dest': 110, 'src': 140, 'op': 'move'}
instructions[2085] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2086] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2087] = {6'd3, 8'd141, 8'd110, 32'd0};//{'dest': 141, 'src': 110, 'op': 'move'}
instructions[2088] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2089] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2090] = {6'd14, 8'd140, 8'd141, 32'd7};//{'src': 141, 'right': 7, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2091] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2092] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2093] = {6'd3, 8'd111, 8'd140, 32'd0};//{'dest': 111, 'src': 140, 'op': 'move'}
instructions[2094] = {6'd0, 8'd141, 8'd0, 32'd8};//{'dest': 141, 'literal': 8, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2095] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2096] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2097] = {6'd11, 8'd142, 8'd141, 32'd108};//{'dest': 142, 'src': 141, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2098] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2099] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2100] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139709592278800, 'op': 'memory_read_request'}
instructions[2101] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2102] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139709592278800, 'op': 'memory_read_wait'}
instructions[2103] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 139709592278800, 'element_size': 2, 'op': 'memory_read'}
instructions[2104] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2105] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2106] = {6'd3, 8'd112, 8'd140, 32'd0};//{'dest': 112, 'src': 140, 'op': 'move'}
instructions[2107] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2108] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2109] = {6'd3, 8'd141, 8'd112, 32'd0};//{'dest': 141, 'src': 112, 'op': 'move'}
instructions[2110] = {6'd3, 8'd146, 8'd110, 32'd0};//{'dest': 146, 'src': 110, 'op': 'move'}
instructions[2111] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2112] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2113] = {6'd33, 8'd142, 8'd146, 32'd1};//{'src': 146, 'right': 1, 'dest': 142, 'signed': False, 'op': '<<', 'type': 'int', 'size': 2}
instructions[2114] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2115] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2116] = {6'd34, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[2117] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2118] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2119] = {6'd3, 8'd113, 8'd140, 32'd0};//{'dest': 113, 'src': 140, 'op': 'move'}
instructions[2120] = {6'd3, 8'd149, 8'd111, 32'd0};//{'dest': 149, 'src': 111, 'op': 'move'}
instructions[2121] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2122] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2123] = {6'd14, 8'd146, 8'd149, 32'd6};//{'src': 149, 'right': 6, 'dest': 146, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2124] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2125] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2126] = {6'd11, 8'd147, 8'd146, 32'd108};//{'dest': 147, 'src': 146, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2127] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2128] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2129] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709593509112, 'op': 'memory_read_request'}
instructions[2130] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2131] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709593509112, 'op': 'memory_read_wait'}
instructions[2132] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 139709593509112, 'element_size': 2, 'op': 'memory_read'}
instructions[2133] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2134] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2135] = {6'd12, 8'd141, 8'd142, 32'd61440};//{'src': 142, 'right': 61440, 'dest': 141, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2136] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2137] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2138] = {6'd32, 8'd140, 8'd141, 32'd10};//{'src': 141, 'right': 10, 'dest': 140, 'signed': False, 'op': '>>', 'type': 'int', 'size': 2}
instructions[2139] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2140] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2141] = {6'd3, 8'd114, 8'd140, 32'd0};//{'dest': 114, 'src': 140, 'op': 'move'}
instructions[2142] = {6'd3, 8'd141, 8'd113, 32'd0};//{'dest': 141, 'src': 113, 'op': 'move'}
instructions[2143] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2144] = {6'd3, 8'd142, 8'd114, 32'd0};//{'dest': 142, 'src': 114, 'op': 'move'}
instructions[2145] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2146] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2147] = {6'd34, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[2148] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2149] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2150] = {6'd3, 8'd104, 8'd140, 32'd0};//{'dest': 104, 'src': 140, 'op': 'move'}
instructions[2151] = {6'd3, 8'd141, 8'd111, 32'd0};//{'dest': 141, 'src': 111, 'op': 'move'}
instructions[2152] = {6'd3, 8'd146, 8'd114, 32'd0};//{'dest': 146, 'src': 114, 'op': 'move'}
instructions[2153] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2154] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2155] = {6'd32, 8'd142, 8'd146, 32'd1};//{'src': 146, 'right': 1, 'dest': 142, 'signed': False, 'op': '>>', 'type': 'int', 'size': 2}
instructions[2156] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2157] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2158] = {6'd11, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2159] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2160] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2161] = {6'd3, 8'd105, 8'd140, 32'd0};//{'dest': 105, 'src': 140, 'op': 'move'}
instructions[2162] = {6'd3, 8'd146, 8'd111, 32'd0};//{'dest': 146, 'src': 111, 'op': 'move'}
instructions[2163] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2164] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2165] = {6'd14, 8'd141, 8'd146, 32'd0};//{'src': 146, 'right': 0, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2166] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2167] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2168] = {6'd11, 8'd142, 8'd141, 32'd108};//{'dest': 142, 'src': 141, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2169] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2170] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2171] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139709592280168, 'op': 'memory_read_request'}
instructions[2172] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2173] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139709592280168, 'op': 'memory_read_wait'}
instructions[2174] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 139709592280168, 'element_size': 2, 'op': 'memory_read'}
instructions[2175] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2176] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2177] = {6'd3, 8'd89, 8'd140, 32'd0};//{'dest': 89, 'src': 140, 'op': 'move'}
instructions[2178] = {6'd3, 8'd146, 8'd111, 32'd0};//{'dest': 146, 'src': 111, 'op': 'move'}
instructions[2179] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2180] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2181] = {6'd14, 8'd141, 8'd146, 32'd1};//{'src': 146, 'right': 1, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2182] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2183] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2184] = {6'd11, 8'd142, 8'd141, 32'd108};//{'dest': 142, 'src': 141, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2185] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2186] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2187] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139709592315592, 'op': 'memory_read_request'}
instructions[2188] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2189] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139709592315592, 'op': 'memory_read_wait'}
instructions[2190] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 139709592315592, 'element_size': 2, 'op': 'memory_read'}
instructions[2191] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2192] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2193] = {6'd3, 8'd90, 8'd140, 32'd0};//{'dest': 90, 'src': 140, 'op': 'move'}
instructions[2194] = {6'd3, 8'd149, 8'd111, 32'd0};//{'dest': 149, 'src': 111, 'op': 'move'}
instructions[2195] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2196] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2197] = {6'd14, 8'd146, 8'd149, 32'd2};//{'src': 149, 'right': 2, 'dest': 146, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2198] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2199] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2200] = {6'd11, 8'd147, 8'd146, 32'd108};//{'dest': 147, 'src': 146, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2201] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2202] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2203] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592315952, 'op': 'memory_read_request'}
instructions[2204] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2205] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592315952, 'op': 'memory_read_wait'}
instructions[2206] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709592315952, 'element_size': 2, 'op': 'memory_read'}
instructions[2207] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2208] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2209] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2210] = {6'd11, 8'd142, 8'd141, 32'd91};//{'dest': 142, 'src': 141, 'srcb': 91, 'signed': False, 'op': '+'}
instructions[2211] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2212] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2213] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2214] = {6'd3, 8'd149, 8'd111, 32'd0};//{'dest': 149, 'src': 111, 'op': 'move'}
instructions[2215] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2216] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2217] = {6'd14, 8'd146, 8'd149, 32'd3};//{'src': 149, 'right': 3, 'dest': 146, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2218] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2219] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2220] = {6'd11, 8'd147, 8'd146, 32'd108};//{'dest': 147, 'src': 146, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2221] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2222] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2223] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592316960, 'op': 'memory_read_request'}
instructions[2224] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2225] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592316960, 'op': 'memory_read_wait'}
instructions[2226] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709592316960, 'element_size': 2, 'op': 'memory_read'}
instructions[2227] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2228] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2229] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2230] = {6'd11, 8'd142, 8'd141, 32'd91};//{'dest': 142, 'src': 141, 'srcb': 91, 'signed': False, 'op': '+'}
instructions[2231] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2232] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2233] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2234] = {6'd3, 8'd149, 8'd111, 32'd0};//{'dest': 149, 'src': 111, 'op': 'move'}
instructions[2235] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2236] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2237] = {6'd14, 8'd146, 8'd149, 32'd4};//{'src': 149, 'right': 4, 'dest': 146, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2238] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2239] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2240] = {6'd11, 8'd147, 8'd146, 32'd108};//{'dest': 147, 'src': 146, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2241] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2242] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2243] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592317032, 'op': 'memory_read_request'}
instructions[2244] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2245] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592317032, 'op': 'memory_read_wait'}
instructions[2246] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709592317032, 'element_size': 2, 'op': 'memory_read'}
instructions[2247] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2248] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2249] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2250] = {6'd11, 8'd142, 8'd141, 32'd92};//{'dest': 142, 'src': 141, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[2251] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2252] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2253] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2254] = {6'd3, 8'd149, 8'd111, 32'd0};//{'dest': 149, 'src': 111, 'op': 'move'}
instructions[2255] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2256] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2257] = {6'd14, 8'd146, 8'd149, 32'd5};//{'src': 149, 'right': 5, 'dest': 146, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2258] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2259] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2260] = {6'd11, 8'd147, 8'd146, 32'd108};//{'dest': 147, 'src': 146, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2261] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2262] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2263] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592314224, 'op': 'memory_read_request'}
instructions[2264] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2265] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592314224, 'op': 'memory_read_wait'}
instructions[2266] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709592314224, 'element_size': 2, 'op': 'memory_read'}
instructions[2267] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2268] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2269] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2270] = {6'd11, 8'd142, 8'd141, 32'd92};//{'dest': 142, 'src': 141, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[2271] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2272] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2273] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2274] = {6'd3, 8'd146, 8'd111, 32'd0};//{'dest': 146, 'src': 111, 'op': 'move'}
instructions[2275] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2276] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2277] = {6'd14, 8'd141, 8'd146, 32'd7};//{'src': 146, 'right': 7, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2278] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2279] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2280] = {6'd11, 8'd142, 8'd141, 32'd108};//{'dest': 142, 'src': 141, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2281] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2282] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2283] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139709592314008, 'op': 'memory_read_request'}
instructions[2284] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2285] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139709592314008, 'op': 'memory_read_wait'}
instructions[2286] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 139709592314008, 'element_size': 2, 'op': 'memory_read'}
instructions[2287] = {6'd3, 8'd147, 8'd111, 32'd0};//{'dest': 147, 'src': 111, 'op': 'move'}
instructions[2288] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2289] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2290] = {6'd14, 8'd142, 8'd147, 32'd6};//{'src': 147, 'right': 6, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2291] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2292] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2293] = {6'd11, 8'd146, 8'd142, 32'd108};//{'dest': 146, 'src': 142, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2294] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2295] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2296] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592314944, 'op': 'memory_read_request'}
instructions[2297] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2298] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592314944, 'op': 'memory_read_wait'}
instructions[2299] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592314944, 'element_size': 2, 'op': 'memory_read'}
instructions[2300] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2301] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2302] = {6'd12, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2303] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2304] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2305] = {6'd3, 8'd93, 8'd140, 32'd0};//{'dest': 93, 'src': 140, 'op': 'move'}
instructions[2306] = {6'd3, 8'd147, 8'd111, 32'd0};//{'dest': 147, 'src': 111, 'op': 'move'}
instructions[2307] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2308] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2309] = {6'd14, 8'd142, 8'd147, 32'd6};//{'src': 147, 'right': 6, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2310] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2311] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2312] = {6'd11, 8'd146, 8'd142, 32'd108};//{'dest': 146, 'src': 142, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2313] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2314] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2315] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709593507240, 'op': 'memory_read_request'}
instructions[2316] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2317] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709593507240, 'op': 'memory_read_wait'}
instructions[2318] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709593507240, 'element_size': 2, 'op': 'memory_read'}
instructions[2319] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2320] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2321] = {6'd12, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2322] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2323] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2324] = {6'd3, 8'd94, 8'd140, 32'd0};//{'dest': 94, 'src': 140, 'op': 'move'}
instructions[2325] = {6'd3, 8'd147, 8'd111, 32'd0};//{'dest': 147, 'src': 111, 'op': 'move'}
instructions[2326] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2327] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2328] = {6'd14, 8'd142, 8'd147, 32'd6};//{'src': 147, 'right': 6, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2329] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2330] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2331] = {6'd11, 8'd146, 8'd142, 32'd108};//{'dest': 146, 'src': 142, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2332] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2333] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2334] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709593507672, 'op': 'memory_read_request'}
instructions[2335] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2336] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709593507672, 'op': 'memory_read_wait'}
instructions[2337] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709593507672, 'element_size': 2, 'op': 'memory_read'}
instructions[2338] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2339] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2340] = {6'd12, 8'd140, 8'd141, 32'd4};//{'src': 141, 'right': 4, 'dest': 140, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2341] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2342] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2343] = {6'd3, 8'd95, 8'd140, 32'd0};//{'dest': 95, 'src': 140, 'op': 'move'}
instructions[2344] = {6'd3, 8'd147, 8'd111, 32'd0};//{'dest': 147, 'src': 111, 'op': 'move'}
instructions[2345] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2346] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2347] = {6'd14, 8'd142, 8'd147, 32'd6};//{'src': 147, 'right': 6, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2348] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2349] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2350] = {6'd11, 8'd146, 8'd142, 32'd108};//{'dest': 146, 'src': 142, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2351] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2352] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2353] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709593507960, 'op': 'memory_read_request'}
instructions[2354] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2355] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709593507960, 'op': 'memory_read_wait'}
instructions[2356] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709593507960, 'element_size': 2, 'op': 'memory_read'}
instructions[2357] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2358] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2359] = {6'd12, 8'd140, 8'd141, 32'd8};//{'src': 141, 'right': 8, 'dest': 140, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2360] = {6'd3, 8'd147, 8'd111, 32'd0};//{'dest': 147, 'src': 111, 'op': 'move'}
instructions[2361] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2362] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2363] = {6'd14, 8'd142, 8'd147, 32'd6};//{'src': 147, 'right': 6, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2364] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2365] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2366] = {6'd11, 8'd146, 8'd142, 32'd108};//{'dest': 146, 'src': 142, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2367] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2368] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2369] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709593506232, 'op': 'memory_read_request'}
instructions[2370] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2371] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709593506232, 'op': 'memory_read_wait'}
instructions[2372] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709593506232, 'element_size': 2, 'op': 'memory_read'}
instructions[2373] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2374] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2375] = {6'd12, 8'd140, 8'd141, 32'd16};//{'src': 141, 'right': 16, 'dest': 140, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2376] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2377] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2378] = {6'd3, 8'd96, 8'd140, 32'd0};//{'dest': 96, 'src': 140, 'op': 'move'}
instructions[2379] = {6'd3, 8'd147, 8'd111, 32'd0};//{'dest': 147, 'src': 111, 'op': 'move'}
instructions[2380] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2381] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2382] = {6'd14, 8'd142, 8'd147, 32'd6};//{'src': 147, 'right': 6, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2383] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2384] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2385] = {6'd11, 8'd146, 8'd142, 32'd108};//{'dest': 146, 'src': 142, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2386] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2387] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2388] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709593509616, 'op': 'memory_read_request'}
instructions[2389] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2390] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709593509616, 'op': 'memory_read_wait'}
instructions[2391] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709593509616, 'element_size': 2, 'op': 'memory_read'}
instructions[2392] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2393] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2394] = {6'd12, 8'd140, 8'd141, 32'd32};//{'src': 141, 'right': 32, 'dest': 140, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2395] = {6'd3, 8'd140, 8'd109, 32'd0};//{'dest': 140, 'src': 109, 'op': 'move'}
instructions[2396] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2397] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2398] = {6'd3, 8'd107, 8'd140, 32'd0};//{'dest': 107, 'src': 140, 'op': 'move'}
instructions[2399] = {6'd6, 8'd0, 8'd106, 32'd0};//{'src': 106, 'op': 'jmp_to_reg'}
instructions[2400] = {6'd0, 8'd119, 8'd0, 32'd0};//{'dest': 119, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2401] = {6'd0, 8'd120, 8'd0, 32'd0};//{'dest': 120, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2402] = {6'd3, 8'd140, 8'd117, 32'd0};//{'dest': 140, 'src': 117, 'op': 'move'}
instructions[2403] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2404] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2405] = {6'd3, 8'd120, 8'd140, 32'd0};//{'dest': 120, 'src': 140, 'op': 'move'}
instructions[2406] = {6'd3, 8'd141, 8'd118, 32'd0};//{'dest': 141, 'src': 118, 'op': 'move'}
instructions[2407] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2408] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2409] = {6'd3, 8'd3, 8'd141, 32'd0};//{'dest': 3, 'src': 141, 'op': 'move'}
instructions[2410] = {6'd1, 8'd2, 8'd0, 32'd39};//{'dest': 2, 'label': 39, 'op': 'jmp_and_link'}
instructions[2411] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2412] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2413] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2414] = {6'd3, 8'd119, 8'd140, 32'd0};//{'dest': 119, 'src': 140, 'op': 'move'}
instructions[2415] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2416] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2417] = {6'd3, 8'd141, 8'd119, 32'd0};//{'dest': 141, 'src': 119, 'op': 'move'}
instructions[2418] = {6'd3, 8'd142, 8'd118, 32'd0};//{'dest': 142, 'src': 118, 'op': 'move'}
instructions[2419] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2420] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2421] = {6'd20, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[2422] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2423] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2424] = {6'd13, 8'd0, 8'd140, 32'd2449};//{'src': 140, 'label': 2449, 'op': 'jmp_if_false'}
instructions[2425] = {6'd3, 8'd142, 8'd120, 32'd0};//{'dest': 142, 'src': 120, 'op': 'move'}
instructions[2426] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2427] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2428] = {6'd11, 8'd146, 8'd142, 32'd116};//{'dest': 146, 'src': 142, 'srcb': 116, 'signed': False, 'op': '+'}
instructions[2429] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2430] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2431] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592358208, 'op': 'memory_read_request'}
instructions[2432] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2433] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592358208, 'op': 'memory_read_wait'}
instructions[2434] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592358208, 'element_size': 2, 'op': 'memory_read'}
instructions[2435] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2436] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2437] = {6'd3, 8'd3, 8'd141, 32'd0};//{'dest': 3, 'src': 141, 'op': 'move'}
instructions[2438] = {6'd1, 8'd2, 8'd0, 32'd39};//{'dest': 2, 'label': 39, 'op': 'jmp_and_link'}
instructions[2439] = {6'd3, 8'd140, 8'd120, 32'd0};//{'dest': 140, 'src': 120, 'op': 'move'}
instructions[2440] = {6'd14, 8'd120, 8'd120, 32'd1};//{'src': 120, 'right': 1, 'dest': 120, 'signed': False, 'op': '+', 'size': 2}
instructions[2441] = {6'd3, 8'd141, 8'd119, 32'd0};//{'dest': 141, 'src': 119, 'op': 'move'}
instructions[2442] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2443] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2444] = {6'd14, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2445] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2446] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2447] = {6'd3, 8'd119, 8'd140, 32'd0};//{'dest': 119, 'src': 140, 'op': 'move'}
instructions[2448] = {6'd15, 8'd0, 8'd0, 32'd2415};//{'label': 2415, 'op': 'goto'}
instructions[2449] = {6'd6, 8'd0, 8'd115, 32'd0};//{'src': 115, 'op': 'jmp_to_reg'}
instructions[2450] = {6'd0, 8'd125, 8'd0, 32'd0};//{'dest': 125, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2451] = {6'd0, 8'd126, 8'd0, 32'd0};//{'dest': 126, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2452] = {6'd0, 8'd127, 8'd0, 32'd0};//{'dest': 127, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2453] = {6'd38, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'input': 'socket', 'op': 'ready'}
instructions[2454] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2455] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2456] = {6'd39, 8'd140, 8'd141, 32'd0};//{'src': 141, 'right': 0, 'dest': 140, 'signed': True, 'op': '==', 'type': 'int', 'size': 2}
instructions[2457] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2458] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2459] = {6'd13, 8'd0, 8'd140, 32'd2466};//{'src': 140, 'label': 2466, 'op': 'jmp_if_false'}
instructions[2460] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2461] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2462] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2463] = {6'd3, 8'd122, 8'd140, 32'd0};//{'dest': 122, 'src': 140, 'op': 'move'}
instructions[2464] = {6'd6, 8'd0, 8'd121, 32'd0};//{'src': 121, 'op': 'jmp_to_reg'}
instructions[2465] = {6'd15, 8'd0, 8'd0, 32'd2466};//{'label': 2466, 'op': 'goto'}
instructions[2466] = {6'd3, 8'd140, 8'd124, 32'd0};//{'dest': 140, 'src': 124, 'op': 'move'}
instructions[2467] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2468] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2469] = {6'd3, 8'd126, 8'd140, 32'd0};//{'dest': 126, 'src': 140, 'op': 'move'}
instructions[2470] = {6'd1, 8'd8, 8'd0, 32'd54};//{'dest': 8, 'label': 54, 'op': 'jmp_and_link'}
instructions[2471] = {6'd3, 8'd140, 8'd9, 32'd0};//{'dest': 140, 'src': 9, 'op': 'move'}
instructions[2472] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2473] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2474] = {6'd3, 8'd127, 8'd140, 32'd0};//{'dest': 127, 'src': 140, 'op': 'move'}
instructions[2475] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2476] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2477] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2478] = {6'd3, 8'd125, 8'd140, 32'd0};//{'dest': 125, 'src': 140, 'op': 'move'}
instructions[2479] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2480] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2481] = {6'd3, 8'd141, 8'd125, 32'd0};//{'dest': 141, 'src': 125, 'op': 'move'}
instructions[2482] = {6'd3, 8'd142, 8'd127, 32'd0};//{'dest': 142, 'src': 127, 'op': 'move'}
instructions[2483] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2484] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2485] = {6'd20, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[2486] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2487] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2488] = {6'd13, 8'd0, 8'd140, 32'd2508};//{'src': 140, 'label': 2508, 'op': 'jmp_if_false'}
instructions[2489] = {6'd1, 8'd8, 8'd0, 32'd54};//{'dest': 8, 'label': 54, 'op': 'jmp_and_link'}
instructions[2490] = {6'd3, 8'd140, 8'd9, 32'd0};//{'dest': 140, 'src': 9, 'op': 'move'}
instructions[2491] = {6'd3, 8'd141, 8'd126, 32'd0};//{'dest': 141, 'src': 126, 'op': 'move'}
instructions[2492] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2493] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2494] = {6'd11, 8'd142, 8'd141, 32'd123};//{'dest': 142, 'src': 141, 'srcb': 123, 'signed': False, 'op': '+'}
instructions[2495] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2496] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2497] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2498] = {6'd3, 8'd140, 8'd126, 32'd0};//{'dest': 140, 'src': 126, 'op': 'move'}
instructions[2499] = {6'd14, 8'd126, 8'd126, 32'd1};//{'src': 126, 'right': 1, 'dest': 126, 'signed': False, 'op': '+', 'size': 2}
instructions[2500] = {6'd3, 8'd141, 8'd125, 32'd0};//{'dest': 141, 'src': 125, 'op': 'move'}
instructions[2501] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2502] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2503] = {6'd14, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2504] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2505] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2506] = {6'd3, 8'd125, 8'd140, 32'd0};//{'dest': 125, 'src': 140, 'op': 'move'}
instructions[2507] = {6'd15, 8'd0, 8'd0, 32'd2479};//{'label': 2479, 'op': 'goto'}
instructions[2508] = {6'd3, 8'd140, 8'd127, 32'd0};//{'dest': 140, 'src': 127, 'op': 'move'}
instructions[2509] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2510] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2511] = {6'd3, 8'd122, 8'd140, 32'd0};//{'dest': 122, 'src': 140, 'op': 'move'}
instructions[2512] = {6'd6, 8'd0, 8'd121, 32'd0};//{'src': 121, 'op': 'jmp_to_reg'}
instructions[2513] = {6'd0, 8'd129, 8'd0, 32'd638};//{'dest': 129, 'literal': 638, 'op': 'literal'}
instructions[2514] = {6'd0, 8'd130, 8'd0, 32'd1662};//{'dest': 130, 'literal': 1662, 'op': 'literal'}
instructions[2515] = {6'd0, 8'd131, 8'd0, 32'd27};//{'dest': 131, 'literal': 27, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2516] = {6'd0, 8'd132, 8'd0, 32'd0};//{'dest': 132, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2517] = {6'd0, 8'd133, 8'd0, 32'd0};//{'dest': 133, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2518] = {6'd0, 8'd134, 8'd0, 32'd0};//{'dest': 134, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2519] = {6'd0, 8'd135, 8'd0, 32'd0};//{'dest': 135, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2520] = {6'd0, 8'd136, 8'd0, 32'd0};//{'dest': 136, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2521] = {6'd0, 8'd137, 8'd0, 32'd0};//{'dest': 137, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2522] = {6'd0, 8'd138, 8'd0, 32'd0};//{'dest': 138, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2523] = {6'd0, 8'd139, 8'd0, 32'd0};//{'dest': 139, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2524] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2525] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2526] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2527] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2528] = {6'd26, 8'd142, 8'd141, 32'd79};//{'dest': 142, 'src': 141, 'srcb': 79, 'signed': True, 'op': '+'}
instructions[2529] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2530] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2531] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2532] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2533] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2534] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2535] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2536] = {6'd26, 8'd142, 8'd141, 32'd79};//{'dest': 142, 'src': 141, 'srcb': 79, 'signed': True, 'op': '+'}
instructions[2537] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2538] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2539] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2540] = {6'd3, 8'd140, 8'd133, 32'd0};//{'dest': 140, 'src': 133, 'op': 'move'}
instructions[2541] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2542] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2543] = {6'd13, 8'd0, 8'd140, 32'd2547};//{'src': 140, 'label': 2547, 'op': 'jmp_if_false'}
instructions[2544] = {6'd3, 8'd140, 8'd133, 32'd0};//{'dest': 140, 'src': 133, 'op': 'move'}
instructions[2545] = {6'd35, 8'd133, 8'd133, 32'd1};//{'src': 133, 'right': 1, 'dest': 133, 'signed': False, 'op': '-', 'size': 2}
instructions[2546] = {6'd15, 8'd0, 8'd0, 32'd2814};//{'label': 2814, 'op': 'goto'}
instructions[2547] = {6'd0, 8'd140, 8'd0, 32'd120};//{'dest': 140, 'literal': 120, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2548] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2549] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2550] = {6'd3, 8'd133, 8'd140, 32'd0};//{'dest': 133, 'src': 140, 'op': 'move'}
instructions[2551] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2552] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2553] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2554] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[2555] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2556] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2557] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2558] = {6'd3, 8'd84, 8'd140, 32'd0};//{'dest': 84, 'src': 140, 'op': 'move'}
instructions[2559] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2560] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2561] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2562] = {6'd3, 8'd83, 8'd140, 32'd0};//{'dest': 83, 'src': 140, 'op': 'move'}
instructions[2563] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2564] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2565] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2566] = {6'd3, 8'd87, 8'd140, 32'd0};//{'dest': 87, 'src': 140, 'op': 'move'}
instructions[2567] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2568] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2569] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2570] = {6'd3, 8'd85, 8'd140, 32'd0};//{'dest': 85, 'src': 140, 'op': 'move'}
instructions[2571] = {6'd0, 8'd140, 8'd0, 32'd46};//{'dest': 140, 'literal': 46, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2572] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2573] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2574] = {6'd40, 8'd0, 8'd140, 32'd0};//{'src': 140, 'signed': True, 'file': '/home/amer/Nexys3/GitHub/TCP11/source/server.h', 'line': 552, 'type': 'int', 'op': 'report'}
instructions[2575] = {6'd0, 8'd141, 8'd0, 32'd46};//{'dest': 141, 'literal': 46, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2576] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2577] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2578] = {6'd3, 8'd1, 8'd141, 32'd0};//{'dest': 1, 'src': 141, 'op': 'move'}
instructions[2579] = {6'd1, 8'd0, 8'd0, 32'd34};//{'dest': 0, 'label': 34, 'op': 'jmp_and_link'}
instructions[2580] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2581] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2582] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2583] = {6'd3, 8'd136, 8'd140, 32'd0};//{'dest': 136, 'src': 140, 'op': 'move'}
instructions[2584] = {6'd0, 8'd140, 8'd0, 32'd24};//{'dest': 140, 'literal': 24, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2585] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2586] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2587] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2588] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2589] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2590] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2591] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2592] = {6'd0, 8'd140, 8'd0, 32'd62290};//{'dest': 140, 'literal': 62290, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2593] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2594] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2595] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2596] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2597] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2598] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2599] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2600] = {6'd0, 8'd140, 8'd0, 32'd64494};//{'dest': 140, 'literal': 64494, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2601] = {6'd0, 8'd141, 8'd0, 32'd2};//{'dest': 141, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2602] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2603] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2604] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2605] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2606] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2607] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2608] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2609] = {6'd0, 8'd141, 8'd0, 32'd3};//{'dest': 141, 'literal': 3, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2610] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2611] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2612] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2613] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2614] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2615] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2616] = {6'd0, 8'd140, 8'd0, 32'd515};//{'dest': 140, 'literal': 515, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2617] = {6'd0, 8'd141, 8'd0, 32'd4};//{'dest': 141, 'literal': 4, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2618] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2619] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2620] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2621] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2622] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2623] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2624] = {6'd0, 8'd140, 8'd0, 32'd1029};//{'dest': 140, 'literal': 1029, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2625] = {6'd0, 8'd141, 8'd0, 32'd5};//{'dest': 141, 'literal': 5, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2626] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2627] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2628] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2629] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2630] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2631] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2632] = {6'd0, 8'd140, 8'd0, 32'd2054};//{'dest': 140, 'literal': 2054, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2633] = {6'd0, 8'd141, 8'd0, 32'd6};//{'dest': 141, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2634] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2635] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2636] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2637] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2638] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2639] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2640] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2641] = {6'd0, 8'd141, 8'd0, 32'd7};//{'dest': 141, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2642] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2643] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2644] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2645] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2646] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2647] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2648] = {6'd0, 8'd140, 8'd0, 32'd2048};//{'dest': 140, 'literal': 2048, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2649] = {6'd0, 8'd141, 8'd0, 32'd8};//{'dest': 141, 'literal': 8, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2650] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2651] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2652] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2653] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2654] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2655] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2656] = {6'd0, 8'd140, 8'd0, 32'd1540};//{'dest': 140, 'literal': 1540, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2657] = {6'd0, 8'd141, 8'd0, 32'd9};//{'dest': 141, 'literal': 9, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2658] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2659] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2660] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2661] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2662] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2663] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2664] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2665] = {6'd0, 8'd141, 8'd0, 32'd10};//{'dest': 141, 'literal': 10, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2666] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2667] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2668] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2669] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2670] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2671] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2672] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2673] = {6'd0, 8'd141, 8'd0, 32'd11};//{'dest': 141, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2674] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2675] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2676] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2677] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2678] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2679] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2680] = {6'd0, 8'd140, 8'd0, 32'd515};//{'dest': 140, 'literal': 515, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2681] = {6'd0, 8'd141, 8'd0, 32'd12};//{'dest': 141, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2682] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2683] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2684] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2685] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2686] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2687] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2688] = {6'd0, 8'd140, 8'd0, 32'd1029};//{'dest': 140, 'literal': 1029, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2689] = {6'd0, 8'd141, 8'd0, 32'd13};//{'dest': 141, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2690] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2691] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2692] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2693] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2694] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2695] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2696] = {6'd0, 8'd140, 8'd0, 32'd49320};//{'dest': 140, 'literal': 49320, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2697] = {6'd0, 8'd141, 8'd0, 32'd14};//{'dest': 141, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2698] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2699] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2700] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2701] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2702] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2703] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2704] = {6'd0, 8'd140, 8'd0, 32'd119};//{'dest': 140, 'literal': 119, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2705] = {6'd0, 8'd141, 8'd0, 32'd15};//{'dest': 141, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2706] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2707] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2708] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2709] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2710] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2711] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2712] = {6'd0, 8'd140, 8'd0, 32'd24};//{'dest': 140, 'literal': 24, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2713] = {6'd0, 8'd141, 8'd0, 32'd16};//{'dest': 141, 'literal': 16, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2714] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2715] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2716] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2717] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2718] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2719] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2720] = {6'd0, 8'd140, 8'd0, 32'd62290};//{'dest': 140, 'literal': 62290, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2721] = {6'd0, 8'd141, 8'd0, 32'd17};//{'dest': 141, 'literal': 17, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2722] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2723] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2724] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2725] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2726] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2727] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2728] = {6'd0, 8'd140, 8'd0, 32'd64494};//{'dest': 140, 'literal': 64494, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2729] = {6'd0, 8'd141, 8'd0, 32'd18};//{'dest': 141, 'literal': 18, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2730] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2731] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2732] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2733] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2734] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2735] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2736] = {6'd0, 8'd140, 8'd0, 32'd49320};//{'dest': 140, 'literal': 49320, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2737] = {6'd0, 8'd141, 8'd0, 32'd19};//{'dest': 141, 'literal': 19, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2738] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2739] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2740] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2741] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2742] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2743] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2744] = {6'd0, 8'd140, 8'd0, 32'd105};//{'dest': 140, 'literal': 105, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2745] = {6'd0, 8'd141, 8'd0, 32'd20};//{'dest': 141, 'literal': 20, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2746] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2747] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2748] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2749] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2750] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2751] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2752] = {6'd0, 8'd140, 8'd0, 32'd58291};//{'dest': 140, 'literal': 58291, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2753] = {6'd0, 8'd141, 8'd0, 32'd21};//{'dest': 141, 'literal': 21, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2754] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2755] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2756] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2757] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2758] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2759] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2760] = {6'd0, 8'd140, 8'd0, 32'd12976};//{'dest': 140, 'literal': 12976, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2761] = {6'd0, 8'd141, 8'd0, 32'd22};//{'dest': 141, 'literal': 22, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2762] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2763] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2764] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2765] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2766] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2767] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2768] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2769] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2770] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2771] = {6'd3, 8'd135, 8'd140, 32'd0};//{'dest': 135, 'src': 140, 'op': 'move'}
instructions[2772] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2773] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2774] = {6'd3, 8'd141, 8'd135, 32'd0};//{'dest': 141, 'src': 135, 'op': 'move'}
instructions[2775] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2776] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2777] = {6'd27, 8'd140, 8'd141, 32'd46};//{'src': 141, 'right': 46, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[2778] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2779] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2780] = {6'd13, 8'd0, 8'd140, 32'd2805};//{'src': 140, 'label': 2805, 'op': 'jmp_if_false'}
instructions[2781] = {6'd3, 8'd142, 8'd136, 32'd0};//{'dest': 142, 'src': 136, 'op': 'move'}
instructions[2782] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2783] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2784] = {6'd11, 8'd146, 8'd142, 32'd130};//{'dest': 146, 'src': 142, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2785] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2786] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2787] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592441704, 'op': 'memory_read_request'}
instructions[2788] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2789] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709592441704, 'op': 'memory_read_wait'}
instructions[2790] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709592441704, 'element_size': 2, 'op': 'memory_read'}
instructions[2791] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2792] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2793] = {6'd3, 8'd1, 8'd141, 32'd0};//{'dest': 1, 'src': 141, 'op': 'move'}
instructions[2794] = {6'd1, 8'd0, 8'd0, 32'd34};//{'dest': 0, 'label': 34, 'op': 'jmp_and_link'}
instructions[2795] = {6'd3, 8'd140, 8'd136, 32'd0};//{'dest': 140, 'src': 136, 'op': 'move'}
instructions[2796] = {6'd14, 8'd136, 8'd136, 32'd1};//{'src': 136, 'right': 1, 'dest': 136, 'signed': False, 'op': '+', 'size': 2}
instructions[2797] = {6'd3, 8'd141, 8'd135, 32'd0};//{'dest': 141, 'src': 135, 'op': 'move'}
instructions[2798] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2799] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2800] = {6'd14, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2801] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2802] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2803] = {6'd3, 8'd135, 8'd140, 32'd0};//{'dest': 135, 'src': 140, 'op': 'move'}
instructions[2804] = {6'd15, 8'd0, 8'd0, 32'd2772};//{'label': 2772, 'op': 'goto'}
instructions[2805] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[2806] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2807] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2808] = {6'd3, 8'd98, 8'd151, 32'd0};//{'dest': 98, 'src': 151, 'op': 'move'}
instructions[2809] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2810] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2811] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2812] = {6'd3, 8'd99, 8'd141, 32'd0};//{'dest': 99, 'src': 141, 'op': 'move'}
instructions[2813] = {6'd1, 8'd97, 8'd0, 32'd1591};//{'dest': 97, 'label': 1591, 'op': 'jmp_and_link'}
instructions[2814] = {6'd3, 8'd140, 8'd139, 32'd0};//{'dest': 140, 'src': 139, 'op': 'move'}
instructions[2815] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2816] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2817] = {6'd39, 8'd141, 8'd140, 32'd0};//{'src': 140, 'right': 0, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[2818] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2819] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2820] = {6'd22, 8'd0, 8'd141, 32'd2837};//{'src': 141, 'label': 2837, 'op': 'jmp_if_true'}
instructions[2821] = {6'd39, 8'd141, 8'd140, 32'd1};//{'src': 140, 'right': 1, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[2822] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2823] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2824] = {6'd22, 8'd0, 8'd141, 32'd2854};//{'src': 141, 'label': 2854, 'op': 'jmp_if_true'}
instructions[2825] = {6'd39, 8'd141, 8'd140, 32'd2};//{'src': 140, 'right': 2, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[2826] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2827] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2828] = {6'd22, 8'd0, 8'd141, 32'd2920};//{'src': 141, 'label': 2920, 'op': 'jmp_if_true'}
instructions[2829] = {6'd39, 8'd141, 8'd140, 32'd3};//{'src': 140, 'right': 3, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[2830] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2831] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2832] = {6'd22, 8'd0, 8'd141, 32'd2999};//{'src': 141, 'label': 2999, 'op': 'jmp_if_true'}
instructions[2833] = {6'd39, 8'd141, 8'd140, 32'd4};//{'src': 140, 'right': 4, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[2834] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2835] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2836] = {6'd22, 8'd0, 8'd141, 32'd3009};//{'src': 141, 'label': 3009, 'op': 'jmp_if_true'}
instructions[2837] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2838] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2839] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2840] = {6'd3, 8'd85, 8'd140, 32'd0};//{'dest': 85, 'src': 140, 'op': 'move'}
instructions[2841] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2842] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2843] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2844] = {6'd3, 8'd84, 8'd140, 32'd0};//{'dest': 84, 'src': 140, 'op': 'move'}
instructions[2845] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2846] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2847] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2848] = {6'd3, 8'd83, 8'd140, 32'd0};//{'dest': 83, 'src': 140, 'op': 'move'}
instructions[2849] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2850] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2851] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2852] = {6'd3, 8'd87, 8'd140, 32'd0};//{'dest': 87, 'src': 140, 'op': 'move'}
instructions[2853] = {6'd15, 8'd0, 8'd0, 32'd3041};//{'label': 3041, 'op': 'goto'}
instructions[2854] = {6'd0, 8'd141, 8'd0, 32'd13};//{'dest': 141, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2855] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2856] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2857] = {6'd11, 8'd142, 8'd141, 32'd129};//{'dest': 142, 'src': 141, 'srcb': 129, 'signed': False, 'op': '+'}
instructions[2858] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2859] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2860] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139709592386376, 'op': 'memory_read_request'}
instructions[2861] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2862] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139709592386376, 'op': 'memory_read_wait'}
instructions[2863] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 139709592386376, 'element_size': 2, 'op': 'memory_read'}
instructions[2864] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2865] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2866] = {6'd3, 8'd75, 8'd140, 32'd0};//{'dest': 75, 'src': 140, 'op': 'move'}
instructions[2867] = {6'd0, 8'd141, 8'd0, 32'd14};//{'dest': 141, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2868] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2869] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2870] = {6'd11, 8'd142, 8'd141, 32'd129};//{'dest': 142, 'src': 141, 'srcb': 129, 'signed': False, 'op': '+'}
instructions[2871] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2872] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2873] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139709592386520, 'op': 'memory_read_request'}
instructions[2874] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2875] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139709592386520, 'op': 'memory_read_wait'}
instructions[2876] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 139709592386520, 'element_size': 2, 'op': 'memory_read'}
instructions[2877] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2878] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2879] = {6'd3, 8'd76, 8'd140, 32'd0};//{'dest': 76, 'src': 140, 'op': 'move'}
instructions[2880] = {6'd3, 8'd140, 8'd89, 32'd0};//{'dest': 140, 'src': 89, 'op': 'move'}
instructions[2881] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2882] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2883] = {6'd3, 8'd78, 8'd140, 32'd0};//{'dest': 78, 'src': 140, 'op': 'move'}
instructions[2884] = {6'd0, 8'd140, 8'd0, 32'd80};//{'dest': 140, 'literal': 80, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2885] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2886] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2887] = {6'd3, 8'd77, 8'd140, 32'd0};//{'dest': 77, 'src': 140, 'op': 'move'}
instructions[2888] = {6'd3, 8'd143, 8'd81, 32'd0};//{'dest': 143, 'src': 81, 'op': 'move'}
instructions[2889] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2890] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2891] = {6'd3, 8'd19, 8'd143, 32'd0};//{'dest': 19, 'src': 143, 'op': 'move'}
instructions[2892] = {6'd3, 8'd143, 8'd91, 32'd0};//{'dest': 143, 'src': 91, 'op': 'move'}
instructions[2893] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2894] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2895] = {6'd3, 8'd20, 8'd143, 32'd0};//{'dest': 20, 'src': 143, 'op': 'move'}
instructions[2896] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2897] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2898] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2899] = {6'd3, 8'd21, 8'd141, 32'd0};//{'dest': 21, 'src': 141, 'op': 'move'}
instructions[2900] = {6'd1, 8'd17, 8'd0, 32'd108};//{'dest': 17, 'label': 108, 'op': 'jmp_and_link'}
instructions[2901] = {6'd3, 8'd140, 8'd18, 32'd0};//{'dest': 140, 'src': 18, 'op': 'move'}
instructions[2902] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2903] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2904] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2905] = {6'd3, 8'd84, 8'd140, 32'd0};//{'dest': 84, 'src': 140, 'op': 'move'}
instructions[2906] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2907] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2908] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2909] = {6'd3, 8'd87, 8'd140, 32'd0};//{'dest': 87, 'src': 140, 'op': 'move'}
instructions[2910] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[2911] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2912] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2913] = {6'd3, 8'd98, 8'd151, 32'd0};//{'dest': 98, 'src': 151, 'op': 'move'}
instructions[2914] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2915] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2916] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2917] = {6'd3, 8'd99, 8'd141, 32'd0};//{'dest': 99, 'src': 141, 'op': 'move'}
instructions[2918] = {6'd1, 8'd97, 8'd0, 32'd1591};//{'dest': 97, 'label': 1591, 'op': 'jmp_and_link'}
instructions[2919] = {6'd15, 8'd0, 8'd0, 32'd3041};//{'label': 3041, 'op': 'goto'}
instructions[2920] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[2921] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2922] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2923] = {6'd3, 8'd123, 8'd151, 32'd0};//{'dest': 123, 'src': 151, 'op': 'move'}
instructions[2924] = {6'd3, 8'd141, 8'd131, 32'd0};//{'dest': 141, 'src': 131, 'op': 'move'}
instructions[2925] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2926] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2927] = {6'd3, 8'd124, 8'd141, 32'd0};//{'dest': 124, 'src': 141, 'op': 'move'}
instructions[2928] = {6'd1, 8'd121, 8'd0, 32'd2450};//{'dest': 121, 'label': 2450, 'op': 'jmp_and_link'}
instructions[2929] = {6'd3, 8'd140, 8'd122, 32'd0};//{'dest': 140, 'src': 122, 'op': 'move'}
instructions[2930] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2931] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2932] = {6'd3, 8'd132, 8'd140, 32'd0};//{'dest': 132, 'src': 140, 'op': 'move'}
instructions[2933] = {6'd0, 8'd146, 8'd0, 32'd0};//{'dest': 146, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2934] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2935] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2936] = {6'd11, 8'd147, 8'd146, 32'd80};//{'dest': 147, 'src': 146, 'srcb': 80, 'signed': False, 'op': '+'}
instructions[2937] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2938] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2939] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592443864, 'op': 'memory_read_request'}
instructions[2940] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2941] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592443864, 'op': 'memory_read_wait'}
instructions[2942] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709592443864, 'element_size': 2, 'op': 'memory_read'}
instructions[2943] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2944] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2945] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2946] = {6'd11, 8'd142, 8'd141, 32'd79};//{'dest': 142, 'src': 141, 'srcb': 79, 'signed': False, 'op': '+'}
instructions[2947] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2948] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2949] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2950] = {6'd0, 8'd146, 8'd0, 32'd1};//{'dest': 146, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2951] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2952] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2953] = {6'd11, 8'd147, 8'd146, 32'd80};//{'dest': 147, 'src': 146, 'srcb': 80, 'signed': False, 'op': '+'}
instructions[2954] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2955] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2956] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592444296, 'op': 'memory_read_request'}
instructions[2957] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2958] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709592444296, 'op': 'memory_read_wait'}
instructions[2959] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709592444296, 'element_size': 2, 'op': 'memory_read'}
instructions[2960] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2961] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2962] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2963] = {6'd11, 8'd142, 8'd141, 32'd79};//{'dest': 142, 'src': 141, 'srcb': 79, 'signed': False, 'op': '+'}
instructions[2964] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2965] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2966] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2967] = {6'd3, 8'd143, 8'd80, 32'd0};//{'dest': 143, 'src': 80, 'op': 'move'}
instructions[2968] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2969] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2970] = {6'd3, 8'd19, 8'd143, 32'd0};//{'dest': 19, 'src': 143, 'op': 'move'}
instructions[2971] = {6'd3, 8'd143, 8'd79, 32'd0};//{'dest': 143, 'src': 79, 'op': 'move'}
instructions[2972] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2973] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2974] = {6'd3, 8'd20, 8'd143, 32'd0};//{'dest': 20, 'src': 143, 'op': 'move'}
instructions[2975] = {6'd3, 8'd141, 8'd132, 32'd0};//{'dest': 141, 'src': 132, 'op': 'move'}
instructions[2976] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2977] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2978] = {6'd3, 8'd21, 8'd141, 32'd0};//{'dest': 21, 'src': 141, 'op': 'move'}
instructions[2979] = {6'd1, 8'd17, 8'd0, 32'd108};//{'dest': 17, 'label': 108, 'op': 'jmp_and_link'}
instructions[2980] = {6'd3, 8'd140, 8'd18, 32'd0};//{'dest': 140, 'src': 18, 'op': 'move'}
instructions[2981] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2982] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2983] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2984] = {6'd3, 8'd84, 8'd140, 32'd0};//{'dest': 84, 'src': 140, 'op': 'move'}
instructions[2985] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2986] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2987] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2988] = {6'd3, 8'd87, 8'd140, 32'd0};//{'dest': 87, 'src': 140, 'op': 'move'}
instructions[2989] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[2990] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2991] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2992] = {6'd3, 8'd98, 8'd151, 32'd0};//{'dest': 98, 'src': 151, 'op': 'move'}
instructions[2993] = {6'd3, 8'd141, 8'd132, 32'd0};//{'dest': 141, 'src': 132, 'op': 'move'}
instructions[2994] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2995] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2996] = {6'd3, 8'd99, 8'd141, 32'd0};//{'dest': 99, 'src': 141, 'op': 'move'}
instructions[2997] = {6'd1, 8'd97, 8'd0, 32'd1591};//{'dest': 97, 'label': 1591, 'op': 'jmp_and_link'}
instructions[2998] = {6'd15, 8'd0, 8'd0, 32'd3041};//{'label': 3041, 'op': 'goto'}
instructions[2999] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[3000] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3001] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3002] = {6'd3, 8'd98, 8'd151, 32'd0};//{'dest': 98, 'src': 151, 'op': 'move'}
instructions[3003] = {6'd3, 8'd141, 8'd132, 32'd0};//{'dest': 141, 'src': 132, 'op': 'move'}
instructions[3004] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3005] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3006] = {6'd3, 8'd99, 8'd141, 32'd0};//{'dest': 99, 'src': 141, 'op': 'move'}
instructions[3007] = {6'd1, 8'd97, 8'd0, 32'd1591};//{'dest': 97, 'label': 1591, 'op': 'jmp_and_link'}
instructions[3008] = {6'd15, 8'd0, 8'd0, 32'd3041};//{'label': 3041, 'op': 'goto'}
instructions[3009] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3010] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3011] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3012] = {6'd3, 8'd83, 8'd140, 32'd0};//{'dest': 83, 'src': 140, 'op': 'move'}
instructions[3013] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3014] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3015] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3016] = {6'd3, 8'd87, 8'd140, 32'd0};//{'dest': 87, 'src': 140, 'op': 'move'}
instructions[3017] = {6'd3, 8'd143, 8'd81, 32'd0};//{'dest': 143, 'src': 81, 'op': 'move'}
instructions[3018] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3019] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3020] = {6'd3, 8'd19, 8'd143, 32'd0};//{'dest': 19, 'src': 143, 'op': 'move'}
instructions[3021] = {6'd3, 8'd143, 8'd91, 32'd0};//{'dest': 143, 'src': 91, 'op': 'move'}
instructions[3022] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3023] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3024] = {6'd3, 8'd20, 8'd143, 32'd0};//{'dest': 20, 'src': 143, 'op': 'move'}
instructions[3025] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3026] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3027] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3028] = {6'd3, 8'd21, 8'd141, 32'd0};//{'dest': 21, 'src': 141, 'op': 'move'}
instructions[3029] = {6'd1, 8'd17, 8'd0, 32'd108};//{'dest': 17, 'label': 108, 'op': 'jmp_and_link'}
instructions[3030] = {6'd3, 8'd140, 8'd18, 32'd0};//{'dest': 140, 'src': 18, 'op': 'move'}
instructions[3031] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[3032] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3033] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3034] = {6'd3, 8'd98, 8'd151, 32'd0};//{'dest': 98, 'src': 151, 'op': 'move'}
instructions[3035] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3036] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3037] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3038] = {6'd3, 8'd99, 8'd141, 32'd0};//{'dest': 99, 'src': 141, 'op': 'move'}
instructions[3039] = {6'd1, 8'd97, 8'd0, 32'd1591};//{'dest': 97, 'label': 1591, 'op': 'jmp_and_link'}
instructions[3040] = {6'd15, 8'd0, 8'd0, 32'd3041};//{'label': 3041, 'op': 'goto'}
instructions[3041] = {6'd0, 8'd140, 8'd0, 32'd10000};//{'dest': 140, 'literal': 10000, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3042] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3043] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3044] = {6'd3, 8'd134, 8'd140, 32'd0};//{'dest': 134, 'src': 140, 'op': 'move'}
instructions[3045] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3046] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3047] = {6'd3, 8'd140, 8'd134, 32'd0};//{'dest': 140, 'src': 134, 'op': 'move'}
instructions[3048] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3049] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3050] = {6'd13, 8'd0, 8'd140, 32'd3436};//{'src': 140, 'label': 3436, 'op': 'jmp_if_false'}
instructions[3051] = {6'd3, 8'd151, 8'd129, 32'd0};//{'dest': 151, 'src': 129, 'op': 'move'}
instructions[3052] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3053] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3054] = {6'd3, 8'd108, 8'd151, 32'd0};//{'dest': 108, 'src': 151, 'op': 'move'}
instructions[3055] = {6'd1, 8'd106, 8'd0, 32'd2048};//{'dest': 106, 'label': 2048, 'op': 'jmp_and_link'}
instructions[3056] = {6'd3, 8'd140, 8'd107, 32'd0};//{'dest': 140, 'src': 107, 'op': 'move'}
instructions[3057] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3058] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3059] = {6'd3, 8'd135, 8'd140, 32'd0};//{'dest': 135, 'src': 140, 'op': 'move'}
instructions[3060] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3061] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3062] = {6'd3, 8'd140, 8'd135, 32'd0};//{'dest': 140, 'src': 135, 'op': 'move'}
instructions[3063] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3064] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3065] = {6'd13, 8'd0, 8'd140, 32'd3070};//{'src': 140, 'label': 3070, 'op': 'jmp_if_false'}
instructions[3066] = {6'd3, 8'd141, 8'd90, 32'd0};//{'dest': 141, 'src': 90, 'op': 'move'}
instructions[3067] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3068] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3069] = {6'd25, 8'd140, 8'd141, 32'd80};//{'src': 141, 'right': 80, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[3070] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3071] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3072] = {6'd13, 8'd0, 8'd140, 32'd3429};//{'src': 140, 'label': 3429, 'op': 'jmp_if_false'}
instructions[3073] = {6'd3, 8'd141, 8'd139, 32'd0};//{'dest': 141, 'src': 139, 'op': 'move'}
instructions[3074] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3075] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3076] = {6'd31, 8'd140, 8'd141, 32'd0};//{'src': 141, 'right': 0, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[3077] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3078] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3079] = {6'd13, 8'd0, 8'd140, 32'd3085};//{'src': 140, 'label': 3085, 'op': 'jmp_if_false'}
instructions[3080] = {6'd3, 8'd141, 8'd89, 32'd0};//{'dest': 141, 'src': 89, 'op': 'move'}
instructions[3081] = {6'd3, 8'd142, 8'd78, 32'd0};//{'dest': 142, 'src': 78, 'op': 'move'}
instructions[3082] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3083] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3084] = {6'd21, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[3085] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3086] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3087] = {6'd13, 8'd0, 8'd140, 32'd3090};//{'src': 140, 'label': 3090, 'op': 'jmp_if_false'}
instructions[3088] = {6'd15, 8'd0, 8'd0, 32'd3433};//{'label': 3433, 'op': 'goto'}
instructions[3089] = {6'd15, 8'd0, 8'd0, 32'd3090};//{'label': 3090, 'op': 'goto'}
instructions[3090] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3091] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3092] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3093] = {6'd3, 8'd138, 8'd140, 32'd0};//{'dest': 138, 'src': 140, 'op': 'move'}
instructions[3094] = {6'd3, 8'd140, 8'd139, 32'd0};//{'dest': 140, 'src': 139, 'op': 'move'}
instructions[3095] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3096] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3097] = {6'd3, 8'd137, 8'd140, 32'd0};//{'dest': 137, 'src': 140, 'op': 'move'}
instructions[3098] = {6'd3, 8'd140, 8'd139, 32'd0};//{'dest': 140, 'src': 139, 'op': 'move'}
instructions[3099] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3100] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3101] = {6'd39, 8'd141, 8'd140, 32'd0};//{'src': 140, 'right': 0, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[3102] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3103] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3104] = {6'd22, 8'd0, 8'd141, 32'd3121};//{'src': 141, 'label': 3121, 'op': 'jmp_if_true'}
instructions[3105] = {6'd39, 8'd141, 8'd140, 32'd1};//{'src': 140, 'right': 1, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[3106] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3107] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3108] = {6'd22, 8'd0, 8'd141, 32'd3144};//{'src': 141, 'label': 3144, 'op': 'jmp_if_true'}
instructions[3109] = {6'd39, 8'd141, 8'd140, 32'd2};//{'src': 140, 'right': 2, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[3110] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3111] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3112] = {6'd22, 8'd0, 8'd141, 32'd3222};//{'src': 141, 'label': 3222, 'op': 'jmp_if_true'}
instructions[3113] = {6'd39, 8'd141, 8'd140, 32'd3};//{'src': 140, 'right': 3, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[3114] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3115] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3116] = {6'd22, 8'd0, 8'd141, 32'd3258};//{'src': 141, 'label': 3258, 'op': 'jmp_if_true'}
instructions[3117] = {6'd39, 8'd141, 8'd140, 32'd4};//{'src': 140, 'right': 4, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[3118] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3119] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3120] = {6'd22, 8'd0, 8'd141, 32'd3346};//{'src': 141, 'label': 3346, 'op': 'jmp_if_true'}
instructions[3121] = {6'd3, 8'd140, 8'd94, 32'd0};//{'dest': 140, 'src': 94, 'op': 'move'}
instructions[3122] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3123] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3124] = {6'd13, 8'd0, 8'd140, 32'd3130};//{'src': 140, 'label': 3130, 'op': 'jmp_if_false'}
instructions[3125] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3126] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3127] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3128] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3129] = {6'd15, 8'd0, 8'd0, 32'd3143};//{'label': 3143, 'op': 'goto'}
instructions[3130] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3131] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3132] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3133] = {6'd3, 8'd85, 8'd140, 32'd0};//{'dest': 85, 'src': 140, 'op': 'move'}
instructions[3134] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[3135] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3136] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3137] = {6'd3, 8'd98, 8'd151, 32'd0};//{'dest': 98, 'src': 151, 'op': 'move'}
instructions[3138] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3139] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3140] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3141] = {6'd3, 8'd99, 8'd141, 32'd0};//{'dest': 99, 'src': 141, 'op': 'move'}
instructions[3142] = {6'd1, 8'd97, 8'd0, 32'd1591};//{'dest': 97, 'label': 1591, 'op': 'jmp_and_link'}
instructions[3143] = {6'd15, 8'd0, 8'd0, 32'd3356};//{'label': 3356, 'op': 'goto'}
instructions[3144] = {6'd3, 8'd140, 8'd96, 32'd0};//{'dest': 140, 'src': 96, 'op': 'move'}
instructions[3145] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3146] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3147] = {6'd13, 8'd0, 8'd140, 32'd3221};//{'src': 140, 'label': 3221, 'op': 'jmp_if_false'}
instructions[3148] = {6'd0, 8'd146, 8'd0, 32'd1};//{'dest': 146, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3149] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3150] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3151] = {6'd11, 8'd147, 8'd146, 32'd92};//{'dest': 147, 'src': 146, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[3152] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3153] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3154] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709591957944, 'op': 'memory_read_request'}
instructions[3155] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3156] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709591957944, 'op': 'memory_read_wait'}
instructions[3157] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709591957944, 'element_size': 2, 'op': 'memory_read'}
instructions[3158] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3159] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3160] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3161] = {6'd11, 8'd142, 8'd141, 32'd79};//{'dest': 142, 'src': 141, 'srcb': 79, 'signed': False, 'op': '+'}
instructions[3162] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3163] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3164] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[3165] = {6'd0, 8'd146, 8'd0, 32'd0};//{'dest': 146, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3166] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3167] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3168] = {6'd11, 8'd147, 8'd146, 32'd92};//{'dest': 147, 'src': 146, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[3169] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3170] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3171] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709591958376, 'op': 'memory_read_request'}
instructions[3172] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3173] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709591958376, 'op': 'memory_read_wait'}
instructions[3174] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709591958376, 'element_size': 2, 'op': 'memory_read'}
instructions[3175] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3176] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3177] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3178] = {6'd11, 8'd142, 8'd141, 32'd79};//{'dest': 142, 'src': 141, 'srcb': 79, 'signed': False, 'op': '+'}
instructions[3179] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3180] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3181] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[3182] = {6'd0, 8'd146, 8'd0, 32'd1};//{'dest': 146, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3183] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3184] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3185] = {6'd11, 8'd147, 8'd146, 32'd92};//{'dest': 147, 'src': 146, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[3186] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3187] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3188] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709591958808, 'op': 'memory_read_request'}
instructions[3189] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3190] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709591958808, 'op': 'memory_read_wait'}
instructions[3191] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709591958808, 'element_size': 2, 'op': 'memory_read'}
instructions[3192] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3193] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3194] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3195] = {6'd11, 8'd142, 8'd141, 32'd80};//{'dest': 142, 'src': 141, 'srcb': 80, 'signed': False, 'op': '+'}
instructions[3196] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3197] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3198] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[3199] = {6'd0, 8'd146, 8'd0, 32'd0};//{'dest': 146, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3200] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3201] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3202] = {6'd11, 8'd147, 8'd146, 32'd92};//{'dest': 147, 'src': 146, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[3203] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3204] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3205] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709591959240, 'op': 'memory_read_request'}
instructions[3206] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3207] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709591959240, 'op': 'memory_read_wait'}
instructions[3208] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139709591959240, 'element_size': 2, 'op': 'memory_read'}
instructions[3209] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3210] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3211] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3212] = {6'd11, 8'd142, 8'd141, 32'd80};//{'dest': 142, 'src': 141, 'srcb': 80, 'signed': False, 'op': '+'}
instructions[3213] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3214] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3215] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[3216] = {6'd0, 8'd140, 8'd0, 32'd2};//{'dest': 140, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3217] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3218] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3219] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3220] = {6'd15, 8'd0, 8'd0, 32'd3221};//{'label': 3221, 'op': 'goto'}
instructions[3221] = {6'd15, 8'd0, 8'd0, 32'd3356};//{'label': 3356, 'op': 'goto'}
instructions[3222] = {6'd3, 8'd143, 8'd81, 32'd0};//{'dest': 143, 'src': 81, 'op': 'move'}
instructions[3223] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3224] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3225] = {6'd3, 8'd19, 8'd143, 32'd0};//{'dest': 19, 'src': 143, 'op': 'move'}
instructions[3226] = {6'd3, 8'd143, 8'd91, 32'd0};//{'dest': 143, 'src': 91, 'op': 'move'}
instructions[3227] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3228] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3229] = {6'd3, 8'd20, 8'd143, 32'd0};//{'dest': 20, 'src': 143, 'op': 'move'}
instructions[3230] = {6'd3, 8'd141, 8'd104, 32'd0};//{'dest': 141, 'src': 104, 'op': 'move'}
instructions[3231] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3232] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3233] = {6'd3, 8'd21, 8'd141, 32'd0};//{'dest': 21, 'src': 141, 'op': 'move'}
instructions[3234] = {6'd1, 8'd17, 8'd0, 32'd108};//{'dest': 17, 'label': 108, 'op': 'jmp_and_link'}
instructions[3235] = {6'd3, 8'd140, 8'd18, 32'd0};//{'dest': 140, 'src': 18, 'op': 'move'}
instructions[3236] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3237] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3238] = {6'd3, 8'd138, 8'd140, 32'd0};//{'dest': 138, 'src': 140, 'op': 'move'}
instructions[3239] = {6'd3, 8'd140, 8'd93, 32'd0};//{'dest': 140, 'src': 93, 'op': 'move'}
instructions[3240] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3241] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3242] = {6'd13, 8'd0, 8'd140, 32'd3248};//{'src': 140, 'label': 3248, 'op': 'jmp_if_false'}
instructions[3243] = {6'd0, 8'd140, 8'd0, 32'd4};//{'dest': 140, 'literal': 4, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3244] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3245] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3246] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3247] = {6'd15, 8'd0, 8'd0, 32'd3257};//{'label': 3257, 'op': 'goto'}
instructions[3248] = {6'd3, 8'd140, 8'd132, 32'd0};//{'dest': 140, 'src': 132, 'op': 'move'}
instructions[3249] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3250] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3251] = {6'd13, 8'd0, 8'd140, 32'd3257};//{'src': 140, 'label': 3257, 'op': 'jmp_if_false'}
instructions[3252] = {6'd0, 8'd140, 8'd0, 32'd3};//{'dest': 140, 'literal': 3, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3253] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3254] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3255] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3256] = {6'd15, 8'd0, 8'd0, 32'd3257};//{'label': 3257, 'op': 'goto'}
instructions[3257] = {6'd15, 8'd0, 8'd0, 32'd3356};//{'label': 3356, 'op': 'goto'}
instructions[3258] = {6'd3, 8'd143, 8'd81, 32'd0};//{'dest': 143, 'src': 81, 'op': 'move'}
instructions[3259] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3260] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3261] = {6'd3, 8'd19, 8'd143, 32'd0};//{'dest': 19, 'src': 143, 'op': 'move'}
instructions[3262] = {6'd3, 8'd143, 8'd91, 32'd0};//{'dest': 143, 'src': 91, 'op': 'move'}
instructions[3263] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3264] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3265] = {6'd3, 8'd20, 8'd143, 32'd0};//{'dest': 20, 'src': 143, 'op': 'move'}
instructions[3266] = {6'd3, 8'd141, 8'd104, 32'd0};//{'dest': 141, 'src': 104, 'op': 'move'}
instructions[3267] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3268] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3269] = {6'd3, 8'd21, 8'd141, 32'd0};//{'dest': 21, 'src': 141, 'op': 'move'}
instructions[3270] = {6'd1, 8'd17, 8'd0, 32'd108};//{'dest': 17, 'label': 108, 'op': 'jmp_and_link'}
instructions[3271] = {6'd3, 8'd140, 8'd18, 32'd0};//{'dest': 140, 'src': 18, 'op': 'move'}
instructions[3272] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3273] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3274] = {6'd3, 8'd138, 8'd140, 32'd0};//{'dest': 138, 'src': 140, 'op': 'move'}
instructions[3275] = {6'd3, 8'd140, 8'd93, 32'd0};//{'dest': 140, 'src': 93, 'op': 'move'}
instructions[3276] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3277] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3278] = {6'd13, 8'd0, 8'd140, 32'd3284};//{'src': 140, 'label': 3284, 'op': 'jmp_if_false'}
instructions[3279] = {6'd0, 8'd140, 8'd0, 32'd4};//{'dest': 140, 'literal': 4, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3280] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3281] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3282] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3283] = {6'd15, 8'd0, 8'd0, 32'd3345};//{'label': 3345, 'op': 'goto'}
instructions[3284] = {6'd3, 8'd140, 8'd96, 32'd0};//{'dest': 140, 'src': 96, 'op': 'move'}
instructions[3285] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3286] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3287] = {6'd13, 8'd0, 8'd140, 32'd3311};//{'src': 140, 'label': 3311, 'op': 'jmp_if_false'}
instructions[3288] = {6'd0, 8'd142, 8'd0, 32'd1};//{'dest': 142, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3289] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3290] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3291] = {6'd11, 8'd146, 8'd142, 32'd80};//{'dest': 146, 'src': 142, 'srcb': 80, 'signed': False, 'op': '+'}
instructions[3292] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3293] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3294] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709591979720, 'op': 'memory_read_request'}
instructions[3295] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3296] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709591979720, 'op': 'memory_read_wait'}
instructions[3297] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709591979720, 'element_size': 2, 'op': 'memory_read'}
instructions[3298] = {6'd0, 8'd146, 8'd0, 32'd1};//{'dest': 146, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3299] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3300] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3301] = {6'd11, 8'd147, 8'd146, 32'd92};//{'dest': 147, 'src': 146, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[3302] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3303] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3304] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709591979864, 'op': 'memory_read_request'}
instructions[3305] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3306] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709591979864, 'op': 'memory_read_wait'}
instructions[3307] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 139709591979864, 'element_size': 2, 'op': 'memory_read'}
instructions[3308] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3309] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3310] = {6'd28, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[3311] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3312] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3313] = {6'd13, 8'd0, 8'd140, 32'd3337};//{'src': 140, 'label': 3337, 'op': 'jmp_if_false'}
instructions[3314] = {6'd0, 8'd142, 8'd0, 32'd0};//{'dest': 142, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3315] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3316] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3317] = {6'd11, 8'd146, 8'd142, 32'd80};//{'dest': 146, 'src': 142, 'srcb': 80, 'signed': False, 'op': '+'}
instructions[3318] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3319] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3320] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709591980152, 'op': 'memory_read_request'}
instructions[3321] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3322] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139709591980152, 'op': 'memory_read_wait'}
instructions[3323] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139709591980152, 'element_size': 2, 'op': 'memory_read'}
instructions[3324] = {6'd0, 8'd146, 8'd0, 32'd0};//{'dest': 146, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3325] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3326] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3327] = {6'd11, 8'd147, 8'd146, 32'd92};//{'dest': 147, 'src': 146, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[3328] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3329] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3330] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709591980296, 'op': 'memory_read_request'}
instructions[3331] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3332] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139709591980296, 'op': 'memory_read_wait'}
instructions[3333] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 139709591980296, 'element_size': 2, 'op': 'memory_read'}
instructions[3334] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3335] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3336] = {6'd28, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[3337] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3338] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3339] = {6'd13, 8'd0, 8'd140, 32'd3345};//{'src': 140, 'label': 3345, 'op': 'jmp_if_false'}
instructions[3340] = {6'd0, 8'd140, 8'd0, 32'd2};//{'dest': 140, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3341] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3342] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3343] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3344] = {6'd15, 8'd0, 8'd0, 32'd3345};//{'label': 3345, 'op': 'goto'}
instructions[3345] = {6'd15, 8'd0, 8'd0, 32'd3356};//{'label': 3356, 'op': 'goto'}
instructions[3346] = {6'd3, 8'd140, 8'd96, 32'd0};//{'dest': 140, 'src': 96, 'op': 'move'}
instructions[3347] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3348] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3349] = {6'd13, 8'd0, 8'd140, 32'd3355};//{'src': 140, 'label': 3355, 'op': 'jmp_if_false'}
instructions[3350] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3351] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3352] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3353] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3354] = {6'd15, 8'd0, 8'd0, 32'd3355};//{'label': 3355, 'op': 'goto'}
instructions[3355] = {6'd15, 8'd0, 8'd0, 32'd3356};//{'label': 3356, 'op': 'goto'}
instructions[3356] = {6'd3, 8'd140, 8'd95, 32'd0};//{'dest': 140, 'src': 95, 'op': 'move'}
instructions[3357] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3358] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3359] = {6'd13, 8'd0, 8'd140, 32'd3365};//{'src': 140, 'label': 3365, 'op': 'jmp_if_false'}
instructions[3360] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3361] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3362] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3363] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3364] = {6'd15, 8'd0, 8'd0, 32'd3365};//{'label': 3365, 'op': 'goto'}
instructions[3365] = {6'd3, 8'd140, 8'd138, 32'd0};//{'dest': 140, 'src': 138, 'op': 'move'}
instructions[3366] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3367] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3368] = {6'd13, 8'd0, 8'd140, 32'd3401};//{'src': 140, 'label': 3401, 'op': 'jmp_if_false'}
instructions[3369] = {6'd3, 8'd151, 8'd129, 32'd0};//{'dest': 151, 'src': 129, 'op': 'move'}
instructions[3370] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3371] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3372] = {6'd3, 8'd116, 8'd151, 32'd0};//{'dest': 116, 'src': 151, 'op': 'move'}
instructions[3373] = {6'd3, 8'd141, 8'd105, 32'd0};//{'dest': 141, 'src': 105, 'op': 'move'}
instructions[3374] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3375] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3376] = {6'd3, 8'd117, 8'd141, 32'd0};//{'dest': 117, 'src': 141, 'op': 'move'}
instructions[3377] = {6'd3, 8'd141, 8'd104, 32'd0};//{'dest': 141, 'src': 104, 'op': 'move'}
instructions[3378] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3379] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3380] = {6'd3, 8'd118, 8'd141, 32'd0};//{'dest': 118, 'src': 141, 'op': 'move'}
instructions[3381] = {6'd1, 8'd115, 8'd0, 32'd2400};//{'dest': 115, 'label': 2400, 'op': 'jmp_and_link'}
instructions[3382] = {6'd3, 8'd141, 8'd139, 32'd0};//{'dest': 141, 'src': 139, 'op': 'move'}
instructions[3383] = {6'd3, 8'd142, 8'd137, 32'd0};//{'dest': 142, 'src': 137, 'op': 'move'}
instructions[3384] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3385] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3386] = {6'd28, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[3387] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3388] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3389] = {6'd13, 8'd0, 8'd140, 32'd3400};//{'src': 140, 'label': 3400, 'op': 'jmp_if_false'}
instructions[3390] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[3391] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3392] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3393] = {6'd3, 8'd98, 8'd151, 32'd0};//{'dest': 98, 'src': 151, 'op': 'move'}
instructions[3394] = {6'd3, 8'd141, 8'd132, 32'd0};//{'dest': 141, 'src': 132, 'op': 'move'}
instructions[3395] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3396] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3397] = {6'd3, 8'd99, 8'd141, 32'd0};//{'dest': 99, 'src': 141, 'op': 'move'}
instructions[3398] = {6'd1, 8'd97, 8'd0, 32'd1591};//{'dest': 97, 'label': 1591, 'op': 'jmp_and_link'}
instructions[3399] = {6'd15, 8'd0, 8'd0, 32'd3400};//{'label': 3400, 'op': 'goto'}
instructions[3400] = {6'd15, 8'd0, 8'd0, 32'd3401};//{'label': 3401, 'op': 'goto'}
instructions[3401] = {6'd3, 8'd141, 8'd139, 32'd0};//{'dest': 141, 'src': 139, 'op': 'move'}
instructions[3402] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3403] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3404] = {6'd25, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[3405] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3406] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3407] = {6'd13, 8'd0, 8'd140, 32'd3409};//{'src': 140, 'label': 3409, 'op': 'jmp_if_false'}
instructions[3408] = {6'd38, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'input': 'socket', 'op': 'ready'}
instructions[3409] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3410] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3411] = {6'd13, 8'd0, 8'd140, 32'd3414};//{'src': 140, 'label': 3414, 'op': 'jmp_if_false'}
instructions[3412] = {6'd15, 8'd0, 8'd0, 32'd3436};//{'label': 3436, 'op': 'goto'}
instructions[3413] = {6'd15, 8'd0, 8'd0, 32'd3414};//{'label': 3414, 'op': 'goto'}
instructions[3414] = {6'd3, 8'd141, 8'd139, 32'd0};//{'dest': 141, 'src': 139, 'op': 'move'}
instructions[3415] = {6'd3, 8'd142, 8'd137, 32'd0};//{'dest': 142, 'src': 137, 'op': 'move'}
instructions[3416] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3417] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3418] = {6'd21, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[3419] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3420] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3421] = {6'd13, 8'd0, 8'd140, 32'd3428};//{'src': 140, 'label': 3428, 'op': 'jmp_if_false'}
instructions[3422] = {6'd0, 8'd140, 8'd0, 32'd120};//{'dest': 140, 'literal': 120, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3423] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3424] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3425] = {6'd3, 8'd133, 8'd140, 32'd0};//{'dest': 133, 'src': 140, 'op': 'move'}
instructions[3426] = {6'd15, 8'd0, 8'd0, 32'd3436};//{'label': 3436, 'op': 'goto'}
instructions[3427] = {6'd15, 8'd0, 8'd0, 32'd3428};//{'label': 3428, 'op': 'goto'}
instructions[3428] = {6'd15, 8'd0, 8'd0, 32'd3433};//{'label': 3433, 'op': 'goto'}
instructions[3429] = {6'd0, 8'd140, 8'd0, 32'd10000};//{'dest': 140, 'literal': 10000, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3430] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3431] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3432] = {6'd41, 8'd0, 8'd140, 32'd0};//{'src': 140, 'op': 'wait_clocks'}
instructions[3433] = {6'd3, 8'd140, 8'd134, 32'd0};//{'dest': 140, 'src': 134, 'op': 'move'}
instructions[3434] = {6'd35, 8'd134, 8'd134, 32'd1};//{'src': 134, 'right': 1, 'dest': 134, 'signed': False, 'op': '-', 'size': 2}
instructions[3435] = {6'd15, 8'd0, 8'd0, 32'd3045};//{'label': 3045, 'op': 'goto'}
instructions[3436] = {6'd15, 8'd0, 8'd0, 32'd2540};//{'label': 2540, 'op': 'goto'}
instructions[3437] = {6'd6, 8'd0, 8'd128, 32'd0};//{'src': 128, 'op': 'jmp_to_reg'}
end
//////////////////////////////////////////////////////////////////////////////
// CPU IMPLEMENTAION OF C PROCESS
//
// This section of the file contains a CPU implementing the C process.
always @(posedge clk)
begin
//implement memory for 2 byte x n arrays
if (memory_enable_2 == 1'b1) begin
memory_2[address_2] <= data_in_2;
end
data_out_2 <= memory_2[address_2];
memory_enable_2 <= 1'b0;
write_enable_2 <= 0;
//stage 0 instruction fetch
if (stage_0_enable) begin
stage_1_enable <= 1;
instruction_0 <= instructions[program_counter];
opcode_0 = instruction_0[53:48];
dest_0 = instruction_0[47:40];
src_0 = instruction_0[39:32];
srcb_0 = instruction_0[7:0];
literal_0 = instruction_0[31:0];
if(write_enable_2) begin
registers[dest_2] <= result_2;
end
program_counter_0 <= program_counter;
program_counter <= program_counter + 1;
end
//stage 1 opcode fetch
if (stage_1_enable) begin
stage_2_enable <= 1;
register_1 <= registers[src_0];
registerb_1 <= registers[srcb_0];
dest_1 <= dest_0;
literal_1 <= literal_0;
opcode_1 <= opcode_0;
program_counter_1 <= program_counter_0;
end
//stage 2 opcode fetch
if (stage_2_enable) begin
dest_2 <= dest_1;
case(opcode_1)
16'd0:
begin
result_2 <= literal_1;
write_enable_2 <= 1;
end
16'd1:
begin
program_counter <= literal_1;
result_2 <= program_counter_1 + 1;
write_enable_2 <= 1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
16'd2:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
16'd3:
begin
result_2 <= register_1;
write_enable_2 <= 1;
end
16'd5:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_output_eth_tx_stb <= 1'b1;
s_output_eth_tx <= register_1;
end
16'd6:
begin
program_counter <= register_1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
16'd7:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_output_socket_stb <= 1'b1;
s_output_socket <= register_1;
end
16'd8:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_input_eth_rx_ack <= 1'b1;
end
16'd9:
begin
result_2 <= 0;
result_2[0] <= input_eth_rx_stb;
write_enable_2 <= 1;
end
16'd10:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_input_socket_ack <= 1'b1;
end
16'd11:
begin
result_2 <= $unsigned(register_1) + $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd12:
begin
result_2 <= $unsigned(register_1) & $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd13:
begin
if (register_1 == 0) begin
program_counter <= literal_1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
end
16'd14:
begin
result_2 <= $unsigned(register_1) + $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd15:
begin
program_counter <= literal_1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
16'd16:
begin
result_2 <= ~register_1;
write_enable_2 <= 1;
end
16'd17:
begin
address_2 <= register_1;
end
16'd19:
begin
result_2 <= data_out_2;
write_enable_2 <= 1;
end
16'd20:
begin
result_2 <= $unsigned(register_1) < $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd21:
begin
result_2 <= $unsigned(register_1) != $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd22:
begin
if (register_1 != 0) begin
program_counter <= literal_1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
end
16'd23:
begin
address_2 <= register_1;
data_in_2 <= registerb_1;
memory_enable_2 <= 1'b1;
end
16'd24:
begin
$display ("%d (report at line: 107 in file: /home/amer/Nexys3/GitHub/TCP11/source/server.h)", $unsigned(register_1));
end
16'd25:
begin
result_2 <= $unsigned(register_1) == $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd26:
begin
result_2 <= $signed(register_1) + $signed(registerb_1);
write_enable_2 <= 1;
end
16'd27:
begin
result_2 <= $unsigned(register_1) < $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd28:
begin
result_2 <= $unsigned(register_1) == $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd29:
begin
result_2 <= $unsigned(literal_1) | $unsigned(register_1);
write_enable_2 <= 1;
end
16'd30:
begin
result_2 <= $unsigned(register_1) <= $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd31:
begin
result_2 <= $unsigned(register_1) != $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd32:
begin
result_2 <= $unsigned(register_1) >> $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd33:
begin
result_2 <= $unsigned(register_1) << $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd34:
begin
result_2 <= $unsigned(register_1) - $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd35:
begin
result_2 <= $unsigned(register_1) - $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd36:
begin
result_2 <= $unsigned(register_1) <= $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd37:
begin
result_2 <= $unsigned(register_1) | $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd38:
begin
result_2 <= 0;
result_2[0] <= input_socket_stb;
write_enable_2 <= 1;
end
16'd39:
begin
result_2 <= $signed(register_1) == $signed(literal_1);
write_enable_2 <= 1;
end
16'd40:
begin
$display ("%d (report at line: 552 in file: /home/amer/Nexys3/GitHub/TCP11/source/server.h)", $signed(register_1));
end
16'd41:
begin
timer <= register_1;
timer_enable <= 1;
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
endcase
end
if (s_output_eth_tx_stb == 1'b1 && output_eth_tx_ack == 1'b1) begin
s_output_eth_tx_stb <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (s_output_socket_stb == 1'b1 && output_socket_ack == 1'b1) begin
s_output_socket_stb <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (s_input_eth_rx_ack == 1'b1 && input_eth_rx_stb == 1'b1) begin
result_2 <= input_eth_rx;
write_enable_2 <= 1;
s_input_eth_rx_ack <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (s_input_socket_ack == 1'b1 && input_socket_stb == 1'b1) begin
result_2 <= input_socket;
write_enable_2 <= 1;
s_input_socket_ack <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (timer == 0) begin
if (timer_enable) begin
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
timer_enable <= 0;
end
end else begin
timer <= timer - 1;
end
if (rst == 1'b1) begin
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
timer <= 0;
timer_enable <= 0;
program_counter <= 0;
s_input_eth_rx_ack <= 0;
s_input_socket_ack <= 0;
s_output_socket_stb <= 0;
s_output_eth_tx_stb <= 0;
end
end
assign input_eth_rx_ack = s_input_eth_rx_ack;
assign input_socket_ack = s_input_socket_ack;
assign output_socket_stb = s_output_socket_stb;
assign output_socket = s_output_socket;
assign output_eth_tx_stb = s_output_eth_tx_stb;
assign output_eth_tx = s_output_eth_tx;
endmodule
|
//
// Copyright (C) 2015-2019 Markus Hiienkari <[email protected]>
//
// This file is part of Open Source Scan Converter project.
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//`define DEBUG
`define PO_RESET_WIDTH 27 //1us
module ossc (
input clk27,
input ir_rx,
inout scl,
inout sda,
input [1:0] btn,
input [7:0] R_in,
input [7:0] G_in,
input [7:0] B_in,
input FID_in,
input VSYNC_in,
input HSYNC_in,
input PCLK_in,
output HDMI_TX_PCLK,
output reg [7:0] HDMI_TX_RD,
output reg [7:0] HDMI_TX_GD,
output reg [7:0] HDMI_TX_BD,
output reg HDMI_TX_DE,
output reg HDMI_TX_HS,
output reg HDMI_TX_VS,
input HDMI_TX_INT_N,
input HDMI_TX_MODE,
output hw_reset_n,
output LED_G,
output LED_R,
output LCD_RS,
output LCD_CS_N,
output LCD_BL,
output SD_CLK,
inout SD_CMD,
inout [3:0] SD_DAT
);
wire [15:0] sys_ctrl;
wire h_unstable, pll_lock_lost;
wire [31:0] h_config, h_config2, v_config, misc_config, sl_config, sl_config2;
wire [10:0] vmax, vmax_tvp;
wire [1:0] fpga_vsyncgen;
wire ilace_flag, vsync_flag;
wire [19:0] pcnt_frame;
wire [15:0] ir_code;
wire [7:0] ir_code_cnt;
wire [7:0] R_out_sc, G_out_sc, B_out_sc;
wire HSYNC_out_sc;
wire VSYNC_out_sc;
wire PCLK_out;
wire DE_out_sc;
wire [7:0] R_out_vg, G_out_vg, B_out_vg;
wire HSYNC_out_vg;
wire VSYNC_out_vg;
wire DE_out_vg;
reg [7:0] po_reset_ctr = 0;
reg po_reset_n = 1'b0;
wire jtagm_reset_req;
wire sys_reset_n = (po_reset_n & ~jtagm_reset_req);
reg [7:0] R_in_L, G_in_L, B_in_L;
reg HSYNC_in_L, VSYNC_in_L, FID_in_L;
reg [1:0] btn_L, btn_LL;
reg ir_rx_L, ir_rx_LL, HDMI_TX_INT_N_L, HDMI_TX_INT_N_LL, HDMI_TX_MODE_L, HDMI_TX_MODE_LL;
wire lt_sensor = btn_LL[1];
wire lt_active = sys_ctrl[15];
wire lt_armed = sys_ctrl[14];
wire lt_trigger = HDMI_TX_DE & HDMI_TX_GD[0];
wire [1:0] lt_mode = sys_ctrl[13:12];
wire [1:0] lt_mode_synced;
wire [15:0] lt_lat_result;
wire [11:0] lt_stb_result;
wire lt_trig_waiting;
wire lt_finished;
wire remote_event = sys_ctrl[8];
reg remove_event_prev;
reg [14:0] to_ctr, to_ctr_ms;
wire lcd_bl_timeout;
wire [1:0] osd_color;
wire osd_enable_pre;
wire osd_enable = osd_enable_pre & ~lt_active;
wire [10:0] xpos, xpos_sc, xpos_vg;
wire [10:0] ypos, ypos_sc, ypos_vg;
wire pll_areset, pll_scanclk, pll_scanclkena, pll_configupdate, pll_scandata, pll_scandone, pll_activeclock;
// Latch inputs from TVP7002 (synchronized to PCLK_in)
always @(posedge PCLK_in or negedge hw_reset_n)
begin
if (!hw_reset_n) begin
R_in_L <= 8'h00;
G_in_L <= 8'h00;
B_in_L <= 8'h00;
HSYNC_in_L <= 1'b0;
VSYNC_in_L <= 1'b0;
FID_in_L <= 1'b0;
end else begin
R_in_L <= R_in;
G_in_L <= G_in;
B_in_L <= B_in;
HSYNC_in_L <= HSYNC_in;
VSYNC_in_L <= VSYNC_in;
FID_in_L <= FID_in;
end
end
// Insert synchronizers to async inputs (synchronize to CPU clock)
always @(posedge clk27 or negedge po_reset_n)
begin
if (!po_reset_n) begin
btn_L <= 2'b00;
btn_LL <= 2'b00;
ir_rx_L <= 1'b0;
ir_rx_LL <= 1'b0;
HDMI_TX_INT_N_L <= 1'b0;
HDMI_TX_INT_N_LL <= 1'b0;
HDMI_TX_MODE_L <= 1'b0;
HDMI_TX_MODE_LL <= 1'b0;
end else begin
btn_L <= btn;
btn_LL <= btn_L;
ir_rx_L <= ir_rx;
ir_rx_LL <= ir_rx_L;
HDMI_TX_INT_N_L <= HDMI_TX_INT_N;
HDMI_TX_INT_N_LL <= HDMI_TX_INT_N_L;
HDMI_TX_MODE_L <= HDMI_TX_MODE;
HDMI_TX_MODE_LL <= HDMI_TX_MODE_L;
end
end
// Power-on reset pulse generation (not strictly necessary)
always @(posedge clk27)
begin
if (po_reset_ctr == `PO_RESET_WIDTH)
po_reset_n <= 1'b1;
else
po_reset_ctr <= po_reset_ctr + 1'b1;
end
assign hw_reset_n = sys_ctrl[0]; //HDMI_TX_RST_N in v1.2 PCB
`ifdef DEBUG
assign LED_R = HSYNC_in_L;
assign LED_G = VSYNC_in_L;
`else
assign LED_R = lt_active ? lt_trig_waiting : (pll_lock_lost|h_unstable);
assign LED_G = lt_active ? ~lt_sensor : (ir_code == 0);
`endif
assign SD_DAT[3] = sys_ctrl[7]; //SD_SPI_SS_N
assign LCD_CS_N = sys_ctrl[6];
assign LCD_RS = sys_ctrl[5];
wire lcd_bl_on = sys_ctrl[4]; //hw_reset_n in v1.2 PCB
wire [1:0] lcd_bl_time = sys_ctrl[3:2];
assign LCD_BL = lcd_bl_on ? (~lcd_bl_timeout | lt_active) : 1'b0;
wire enable_sc = sys_ctrl[1];
assign xpos = enable_sc ? xpos_sc : xpos_vg;
assign ypos = enable_sc ? ypos_sc : ypos_vg;
assign HDMI_TX_PCLK = PCLK_out;
always @(posedge PCLK_out) begin
if (osd_enable) begin
if (osd_color == 2'h0) begin
{HDMI_TX_RD, HDMI_TX_GD, HDMI_TX_BD} <= 24'h000000;
end else if (osd_color == 2'h1) begin
{HDMI_TX_RD, HDMI_TX_GD, HDMI_TX_BD} <= 24'h0000ff;
end else if (osd_color == 2'h2) begin
{HDMI_TX_RD, HDMI_TX_GD, HDMI_TX_BD} <= 24'hffff00;
end else begin
{HDMI_TX_RD, HDMI_TX_GD, HDMI_TX_BD} <= 24'hffffff;
end
end else if (enable_sc) begin
{HDMI_TX_RD, HDMI_TX_GD, HDMI_TX_BD} <= {R_out_sc, G_out_sc, B_out_sc};
end else begin
{HDMI_TX_RD, HDMI_TX_GD, HDMI_TX_BD} <= {R_out_vg, G_out_vg, B_out_vg};
end
HDMI_TX_HS <= enable_sc ? HSYNC_out_sc : HSYNC_out_vg;
HDMI_TX_VS <= enable_sc ? VSYNC_out_sc : VSYNC_out_vg;
HDMI_TX_DE <= enable_sc ? DE_out_sc : DE_out_vg;
end
// LCD backlight timeout counters
always @(posedge clk27)
begin
if (remote_event != remove_event_prev) begin
to_ctr <= 15'd0;
to_ctr_ms <= 15'd0;
end else begin
if (to_ctr == 27000-1) begin
to_ctr <= 0;
if (to_ctr_ms < 15'h7fff)
to_ctr_ms <= to_ctr_ms + 1'b1;
end else begin
to_ctr <= to_ctr + 1'b1;
end
end
case (lcd_bl_time)
default: lcd_bl_timeout <= 0; //off
2'b01: lcd_bl_timeout <= (to_ctr_ms >= 3000); //3s
2'b10: lcd_bl_timeout <= (to_ctr_ms >= 10000); //10s
2'b11: lcd_bl_timeout <= (to_ctr_ms >= 30000); //30s
endcase
remove_event_prev <= remote_event;
end
sys sys_inst(
.clk_clk (clk27),
.reset_reset_n (sys_reset_n),
.pulpino_0_config_testmode_i (1'b0),
.pulpino_0_config_fetch_enable_i (1'b1),
.pulpino_0_config_clock_gating_i (1'b0),
.pulpino_0_config_boot_addr_i (32'h00010000),
.master_0_master_reset_reset (jtagm_reset_req),
.i2c_opencores_0_export_scl_pad_io (scl),
.i2c_opencores_0_export_sda_pad_io (sda),
.i2c_opencores_0_export_spi_miso_pad_i (1'b0),
.i2c_opencores_1_export_scl_pad_io (SD_CLK),
.i2c_opencores_1_export_sda_pad_io (SD_CMD),
.i2c_opencores_1_export_spi_miso_pad_i (SD_DAT[0]),
.pio_0_sys_ctrl_out_export (sys_ctrl),
.pio_1_controls_in_export ({ir_code_cnt, 4'b0000, pll_activeclock, HDMI_TX_MODE_LL, btn_LL, ir_code}),
.sc_config_0_sc_if_sc_status_i ({vsync_flag, 2'b00, vmax_tvp, fpga_vsyncgen, 4'h0, ilace_flag, vmax}),
.sc_config_0_sc_if_sc_status2_i ({12'h000, pcnt_frame}),
.sc_config_0_sc_if_lt_status_i ({lt_finished, 3'h0, lt_stb_result, lt_lat_result}),
.sc_config_0_sc_if_h_config_o (h_config),
.sc_config_0_sc_if_h_config2_o (h_config2),
.sc_config_0_sc_if_v_config_o (v_config),
.sc_config_0_sc_if_misc_config_o (misc_config),
.sc_config_0_sc_if_sl_config_o (sl_config),
.sc_config_0_sc_if_sl_config2_o (sl_config2),
.osd_generator_0_osd_if_vclk (PCLK_out),
.osd_generator_0_osd_if_xpos (xpos),
.osd_generator_0_osd_if_ypos (ypos),
.osd_generator_0_osd_if_osd_enable (osd_enable_pre),
.osd_generator_0_osd_if_osd_color (osd_color),
.pll_reconfig_0_pll_reconfig_if_areset (pll_areset),
.pll_reconfig_0_pll_reconfig_if_scanclk (pll_scanclk),
.pll_reconfig_0_pll_reconfig_if_scanclkena (pll_scanclkena),
.pll_reconfig_0_pll_reconfig_if_configupdate (pll_configupdate),
.pll_reconfig_0_pll_reconfig_if_scandata (pll_scandata),
.pll_reconfig_0_pll_reconfig_if_scandone (pll_scandone)
);
scanconverter scanconverter_inst (
.reset_n (hw_reset_n),
.PCLK_in (PCLK_in),
.clk27 (clk27),
.enable_sc (enable_sc),
.HSYNC_in (HSYNC_in_L),
.VSYNC_in (VSYNC_in_L),
.FID_in (FID_in_L),
.R_in (R_in_L),
.G_in (G_in_L),
.B_in (B_in_L),
.h_config (h_config),
.h_config2 (h_config2),
.v_config (v_config),
.misc_config (misc_config),
.sl_config (sl_config),
.sl_config2 (sl_config2),
.R_out (R_out_sc),
.G_out (G_out_sc),
.B_out (B_out_sc),
.PCLK_out (PCLK_out),
.HSYNC_out (HSYNC_out_sc),
.VSYNC_out (VSYNC_out_sc),
.DE_out (DE_out_sc),
.h_unstable (h_unstable),
.fpga_vsyncgen (fpga_vsyncgen),
.pll_lock_lost (pll_lock_lost),
.vmax (vmax),
.vmax_tvp (vmax_tvp),
.pcnt_frame (pcnt_frame),
.ilace_flag (ilace_flag),
.vsync_flag (vsync_flag),
.lt_active (lt_active),
.lt_mode (lt_mode_synced),
.xpos (xpos_sc),
.ypos (ypos_sc),
.pll_areset (pll_areset),
.pll_scanclk (pll_scanclk),
.pll_scanclkena (pll_scanclkena),
.pll_configupdate (pll_configupdate),
.pll_scandata (pll_scandata),
.pll_scandone (pll_scandone),
.pll_activeclock (pll_activeclock)
);
ir_rcv ir0 (
.clk27 (clk27),
.reset_n (po_reset_n),
.ir_rx (ir_rx_LL),
.ir_code (ir_code),
.ir_code_ack (),
.ir_code_cnt (ir_code_cnt)
);
lat_tester lt0 (
.clk27 (clk27),
.pclk (PCLK_out),
.active (lt_active),
.armed (lt_armed),
.sensor (lt_sensor),
.trigger (lt_trigger),
.VSYNC_in (HDMI_TX_VS),
.mode_in (lt_mode),
.mode_synced (lt_mode_synced),
.lat_result (lt_lat_result),
.stb_result (lt_stb_result),
.trig_waiting (lt_trig_waiting),
.finished (lt_finished)
);
videogen vg0 (
.clk27 (PCLK_out),
.reset_n (po_reset_n & ~enable_sc),
.lt_active (lt_active),
.lt_mode (lt_mode_synced),
.R_out (R_out_vg),
.G_out (G_out_vg),
.B_out (B_out_vg),
.HSYNC_out (HSYNC_out_vg),
.VSYNC_out (VSYNC_out_vg),
.DE_out (DE_out_vg),
.xpos (xpos_vg),
.ypos (ypos_vg)
);
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
// IP Revision: 7
(* X_CORE_INFO = "axi_dwidth_converter_v2_1_7_top,Vivado 2015.4" *)
(* CHECK_LICENSE_TYPE = "zc702_auto_us_df_1,axi_dwidth_converter_v2_1_7_top,{}" *)
(* CORE_GENERATION_INFO = "zc702_auto_us_df_1,axi_dwidth_converter_v2_1_7_top,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dwidth_converter,x_ipVersion=2.1,x_ipCoreRevision=7,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_AXI_PROTOCOL=0,C_S_AXI_ID_WIDTH=1,C_SUPPORTS_ID=0,C_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=32,C_M_AXI_DATA_WIDTH=64,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_FIFO_MODE=1,C_S_AXI_ACLK_RATIO=1,C_M_AXI_ACLK_RATIO=2,C_AXI_IS_ACLK_ASYNC=0,C_MAX_SPLIT_BEATS=16,C_PACKING_LEVEL=1,C_SYNCHRONIZER_STAGE=3}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zc702_auto_us_df_1 (
s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_dwidth_converter_v2_1_7_top #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(0),
.C_S_AXI_ID_WIDTH(1),
.C_SUPPORTS_ID(0),
.C_AXI_ADDR_WIDTH(32),
.C_S_AXI_DATA_WIDTH(32),
.C_M_AXI_DATA_WIDTH(64),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_FIFO_MODE(1),
.C_S_AXI_ACLK_RATIO(1),
.C_M_AXI_ACLK_RATIO(2),
.C_AXI_IS_ACLK_ASYNC(0),
.C_MAX_SPLIT_BEATS(16),
.C_PACKING_LEVEL(1),
.C_SYNCHRONIZER_STAGE(3)
) inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_aclk(1'H0),
.m_axi_aresetn(1'H0),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A31O_1_V
`define SKY130_FD_SC_LS__A31O_1_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a31o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a31o_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a31o_1 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A31O_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DECAP_FUNCTIONAL_V
`define SKY130_FD_SC_HS__DECAP_FUNCTIONAL_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hs__decap (
VGND,
VPWR
);
// Module ports
input VGND;
input VPWR;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DECAP_FUNCTIONAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A221OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__A221OI_BEHAVIORAL_PP_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a221oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
nor nor0 (nor0_out_Y , and0_out, C1, and1_out);
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A221OI_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__XNOR2_BLACKBOX_V
`define SKY130_FD_SC_HVL__XNOR2_BLACKBOX_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__xnor2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__XNOR2_BLACKBOX_V
|
`timescale 1ns / 1ps
module Codigo1(clk, ps2_data, ps2_clk, ps2_data_out, pulso_done
);
input clk;
input ps2_clk, ps2_data;
output [7:0]ps2_data_out;
output reg pulso_done;
//variables del programa
reg [7:0] filtro_antirebote;
reg ps2_clk_negedge;
reg [2:0] estado=0;
reg [7:0] contador=0;
reg [7:0] data_p;
reg data_in;
localparam [2:0]
idle = 3'b000,
uno = 3'b001,
dos = 3'b010,
tres = 3'b011,
cuatro = 3'b100;
always @ (posedge clk)
begin
filtro_antirebote [7:0]<= {ps2_clk, filtro_antirebote[7:1]};
end
always @ (posedge clk)
begin
if (filtro_antirebote == 8'b00001111)
ps2_clk_negedge <= 1'b1;
else
ps2_clk_negedge <= 1'b0;
end
always @ (posedge clk)
begin
if (ps2_clk_negedge)
data_in <= ps2_data;
else
data_in <= data_in;
end
always @ (posedge clk)
begin
case (estado)
idle: begin
data_p <= data_p;
contador <= 4'd0;
pulso_done <=1'b0;
if (ps2_clk_negedge)
estado<= uno;
else
estado<= uno;
end
uno: begin
data_p<=data_p;
contador <= contador;
pulso_done <= 1'b0;
if (ps2_clk_negedge)
begin
if (contador == 4'd8)
estado<=tres;
else
estado <= dos;
end
else
estado<= uno;
end
dos: begin
data_p [7:0] <= {data_in, data_p[7:1]};
contador <= contador +1;
pulso_done <= 1'b0;
estado <= uno;
end
tres: begin
estado <= cuatro;
pulso_done <=1'b1;
data_p <=data_p;
contador <= 4'd0;
end
cuatro: begin
data_p <= data_p;
contador <= 4'd0;
pulso_done <= 1'b0;
if (ps2_clk_negedge)
estado <= idle;
end
endcase
end
assign ps2_data_out = data_p;
endmodule
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:45:17 08/11/2015
// Design Name:
// Module Name: MaquinaE
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
//revisar estado profe
module MaquinaE(
input wire clk, reset,
input wire [3:0] sensores,
output reg [6:0] salida,
output reg [3:0] display,
output reg [7:0] sevenseg,
//output reg signed [3:0] state_reg /////Se ponen los estados como una salida para de esta forma supervisar el estado en el que se encuentra la maquina
output reg signed [3:0] estado /////the internal signal connected to the port is a signed reg data type
);
////Parametros de 0 a 15
parameter e0=4'b0000,e1=4'b0001,e2=4'b0010,e3=4'b0011,e4=4'b0100,e5=4'b0101,e6=4'b0110,e7=4'b0111,e8=4'b1000,e9=4'b1001,e10=4'b1010,e11=4'b1011,e12=4'b1100,e13=4'b1101,e14=4'b1110,e15=4'b1111;
parameter s0=4'b0000,s1=4'b0001,s2=4'b0010,s3=4'b0011,s4=4'b1000,s5=4'b0101,s6=4'b0110,s7=4'b0111,s8=4'b1000,s9=4'b1001,s10=4'b1010,s11=4'b1011,s12=4'b1100,s13=4'b1101,s14=4'b1110,s15=4'b1111;
reg [3:0] estado_p, estado_s;
always @(posedge clk, posedge reset)
if (reset)
begin
estado_p<=s0;
//display=4'b1111;
//sevenseg=8'b11111111;
end
else
estado_p<=estado_s;
always@* //logica de siguiente de estado y logica de salida
begin
//salida=7'b0000000;
estado_s = estado_p;
case (estado_p)
s0:
begin
///salida=7'b0000001;
if (sensores == 4'b0000)
begin
salida=7'b0000001;
display=4'b1111;
sevenseg=8'b11111111;
estado_s=s0;
end
else
if(sensores==e0)
estado_s=s0;
//salidas<=7'b0000001;
else if(sensores==e1)
//salidas<=7'b0000001;
estado_s=s1;
else if(sensores==e2)
//salidas<=7'b0000001;
estado_s=s2;
else if(sensores==e3)
//salidas<=7'b0000001;
estado_s=s3;
else if(sensores==e4)
//salidas<=7'b0000001;
estado_s=s4;
else if(sensores==e5)
//salidas<=7'b0000001;
estado_s=s5;
else if(sensores==e6)
//salidas<=7'b0000001;
estado_s=s6;
else if(sensores==e7)
//salidas<=7'b0000001;
estado_s=s7;
else if(sensores==e8)
//salidas<=7'b0000001;
estado_s=s8;
else if(sensores==e9)
//salidas<=7'b0000001;
estado_s=s9;
else if(sensores==e10)
//salidas<=7'b0000001;
estado_s=s10;
else if(sensores==e11)
//salidas<=7'b0000001;
estado_s=s11;
else if(sensores==e12)
//salidas<=7'b0000001;
estado_s=s12;
else if(sensores==e13)
//salidas<=7'b0000001;
estado_s=s13;
else if(sensores==e14)
//salidas<=7'b0000001;
estado_s=s14;
else if(sensores==e15)
//salidas<=7'b0000001;
estado_s=s15;
end
s1:
begin
salida=7'b1000000;
if (sensores == 4'b0001)
begin
estado_s=s1;
display=4'b1110;//hola
sevenseg=8'b10011111;
end
else
estado_s=s0;
end
s2:
begin
salida=7'b1011100;
if (sensores == 4'b0010)
begin
estado_s=s2;
display=4'b1101;
sevenseg=8'b10011111;
end
else
estado_s=s0;
end
s3:
begin
salida=7'b1011110;
if (sensores == 4'b0011)
begin
estado_s=s3;
display=4'b1100;
sevenseg=8'b10011111;
end
else
estado_s=s0;
end
s4:
begin
salida=7'b1100000;
if (sensores == 4'b0100)
begin
estado_s=s4;
display=4'b1011;
sevenseg=8'b10011111;
end
else
estado_s=s0;
end
s5:
begin
salida=7'b1100010;
if (sensores == 4'b0101)
begin
estado_s=s5;
display=4'b1010;
sevenseg=8'b10011111;
end
else
estado_s=s0;
end
s6:
begin
salida=7'b1111110;
if (sensores == 4'b0110)
begin
estado_s=s6;
display=4'b1001;
sevenseg=8'b10011111;
end
else
estado_s=s0;
end
s7:
begin
salida=7'b1111110;
if (sensores == 4'b0111)
begin
estado_s=s7;
display=4'b1000;
sevenseg=8'b10011111;
end
else
estado_s=s0;
end
s8:
begin
salida=7'b1110000;
if (sensores == 4'b1000)
begin
estado_s=s8;
display=4'b0111;
sevenseg=8'b10011111;
end
else
estado_s=s0;
end
s9:
begin
salida=7'b1010010;
if (sensores == 4'b1001)
begin
estado_s=s9;
display=4'b0110;
sevenseg=8'b10011111;
end
else
estado_s=s0;
end
s10:
begin
salida=7'b1011110;
if (sensores == 4'b1010)
begin
estado_s=s10;
display=4'b0101;
sevenseg=8'b10011111;
end
else
estado_s=s0;
end
s11:
begin
salida=7'b1011110;
if (sensores == 4'b1011)
begin
estado_s=s11;
display=4'b0100;
sevenseg=8'b10011111;
end
else
estado_s=s0;
end
s12:
begin
salida=7'b1110010;
if (sensores == 4'b1100)
begin
estado_s=s12;
display=4'b0011;
sevenseg=8'b10011111;
end
else
estado_s=s0;
end
s13:
begin
salida=7'b1110010;
if (sensores == 4'b1101)
begin
estado_s=s13;
display=4'b0010;
sevenseg=8'b10011111;
end
else
estado_s=s0;
end
s14:
begin
salida=7'b0000001;
if (sensores == 4'b1110)
begin
estado_s=s14;
display=4'b0001;
sevenseg=8'b10011111;
end
else
estado_s=s0;
end
s15:
begin
salida=7'b1111110;
if (sensores == 4'b1111)
begin
estado_s=s15;
display=4'b0000;
sevenseg=8'b10011111;
end
else
estado_s=s0;
end
default estado_s=s0;
endcase
end
endmodule
module comparador(
input wire clk,
output reg [3:0] sensores,
input wire [7:0]ps2_data_out, ////// Salidas del modulo que van a ir conectadas al otro
input wire pulso_done ////////
);
endmodule
|
/*
########################################################################
EPIPHANY eMesh Arbiter
########################################################################
This block takes three FIFO inputs (write, read request, read response),
arbitrates between the active channels, and forwards the result on to
the transmit channel.
The arbitration order is (fixed, highest to lowest)
1) host writes
2) read requests from host
3) read responses
*/
module etx_arbiter (/*AUTOARG*/
// Outputs
emwr_rd_en, emrq_rd_en, emrr_rd_en, etx_access, etx_write,
etx_datamode, etx_ctrlmode, etx_dstaddr, etx_srcaddr, etx_data,
// Inputs
tx_lclk_par, reset, emwr_fifo_access, emwr_fifo_write,
emwr_fifo_datamode, emwr_fifo_ctrlmode, emwr_fifo_dstaddr,
emwr_fifo_data, emwr_fifo_srcaddr, emrq_fifo_access,
emrq_fifo_write, emrq_fifo_datamode, emrq_fifo_ctrlmode,
emrq_fifo_dstaddr, emrq_fifo_data, emrq_fifo_srcaddr,
emrr_fifo_access, emrr_fifo_write, emrr_fifo_datamode,
emrr_fifo_ctrlmode, emrr_fifo_dstaddr, emrr_fifo_data,
emrr_fifo_srcaddr, etx_rd_wait, etx_wr_wait, etx_ack
);
// tx clock
input tx_lclk_par;
input reset;
//Write Request (from slave)
input emwr_fifo_access;
input emwr_fifo_write;
input [1:0] emwr_fifo_datamode;
input [3:0] emwr_fifo_ctrlmode;
input [31:0] emwr_fifo_dstaddr;
input [31:0] emwr_fifo_data;
input [31:0] emwr_fifo_srcaddr;
output emwr_rd_en;
//Read Request (from slave)
input emrq_fifo_access;
input emrq_fifo_write;
input [1:0] emrq_fifo_datamode;
input [3:0] emrq_fifo_ctrlmode;
input [31:0] emrq_fifo_dstaddr;
input [31:0] emrq_fifo_data;
input [31:0] emrq_fifo_srcaddr;
output emrq_rd_en;
//Read Response (from master)
input emrr_fifo_access;
input emrr_fifo_write;
input [1:0] emrr_fifo_datamode;
input [3:0] emrr_fifo_ctrlmode;
input [31:0] emrr_fifo_dstaddr;
input [31:0] emrr_fifo_data;
input [31:0] emrr_fifo_srcaddr;
output emrr_rd_en;
// eMesh master port, to TX
output etx_access;
output etx_write;
output [1:0] etx_datamode;
output [3:0] etx_ctrlmode;
output [31:0] etx_dstaddr;
output [31:0] etx_srcaddr;
output [31:0] etx_data;
input etx_rd_wait;
input etx_wr_wait;
// Ack from TX protocol module
input etx_ack;
//regs
reg ready;
reg etx_write;
reg [1:0] etx_datamode;
reg [3:0] etx_ctrlmode;
reg [31:0] etx_dstaddr;
reg [31:0] etx_srcaddr;
reg [31:0] etx_data;
//wires
wire rr_ready;
wire rq_ready;
wire wr_ready;
wire emrr_rd_en;
wire emwr_rd_en;
//############
//# Arbitrate & forward
//############
// priority-based ready signals
assign wr_ready = emwr_fifo_access & ~etx_wr_wait; //highest
assign rq_ready = emrq_fifo_access & ~etx_rd_wait & ~wr_ready;
assign rr_ready = emrr_fifo_access & ~etx_wr_wait & ~wr_ready & ~rq_ready;//lowest
// FIFO read enables, when we're idle or done with the current datum
assign emrr_rd_en = rr_ready & (~ready | etx_ack);
assign emrq_rd_en = rq_ready & (~ready | etx_ack);
assign emwr_rd_en = wr_ready & (~ready | etx_ack);
always @ (posedge tx_lclk_par)
if( reset )
begin
ready <= 1'b0;
etx_write <= 1'b0;
etx_datamode[1:0] <= 2'b0;
etx_ctrlmode[3:0] <= 4'b0;
etx_dstaddr[31:0] <= 32'b0;
etx_data[31:0] <= 32'b0;
etx_srcaddr[31:0] <= 32'b0;
end
else if (emrr_rd_en | emrq_rd_en | emwr_rd_en )
begin
ready <= 1'b1;
etx_write <= emrr_rd_en ? 1'b1 :
emrq_rd_en ? 1'b0 :
1'b1;
etx_datamode[1:0] <= emrr_rd_en ? emrr_fifo_datamode[1:0] :
emrq_rd_en ? emrq_fifo_datamode[1:0] :
emwr_fifo_datamode[1:0];
etx_ctrlmode[3:0] <= emrr_rd_en ? emrr_fifo_ctrlmode[3:0] :
emrq_rd_en ? emrq_fifo_ctrlmode[3:0] :
emwr_fifo_ctrlmode[3:0];
etx_dstaddr[31:0] <= emrr_rd_en ? emrr_fifo_dstaddr[31:0] :
emrq_rd_en ? emrq_fifo_dstaddr[31:0] :
emwr_fifo_dstaddr[31:0];
etx_data[31:0] <= emrr_rd_en ? emrr_fifo_data[31:0] :
emrq_rd_en ? emrq_fifo_data[31:0] :
emwr_fifo_data[31:0];
etx_srcaddr[31:0] <= emrr_rd_en ? emrr_fifo_srcaddr[31:0] :
emrq_rd_en ? emrq_fifo_srcaddr[31:0] :
emwr_fifo_srcaddr[31:0];
end
else if (etx_ack)
begin
ready <= 1'b0;
end
assign etx_access = ready;
endmodule // etx_arbiter
/*
File: etx_arbiter.v
This file is part of the Parallella Project.
Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <[email protected]>
Contributed by Andreas Olofsson <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
|
module xyz (/*AUTOARG*/
// Outputs
signal_f, signal_c,
// Inputs
signal_e3, signal_b
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [2:0] signal_b; // To u_abc of abc.v
input signal_e3; // To u_def of def.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output signal_c; // From u_abc of abc.v
output signal_f; // From u_def of def.v
// End of automatics
/*AUTOWIRE*/
/* abc AUTO_TEMPLATE
(
// Outputs
.signal_c (signal_c),
// Inputs
.signal_a (signal_f), // AUTONOHOOKUP
.signal_b (signal_b[2:0]));
*/
abc u_abc
(/*AUTOINST*/
// Outputs
.signal_c (signal_c), // Templated
// Inputs
.signal_a (signal_f), // Templated AUTONOHOOKUP
.signal_b (signal_b[2:0])); // Templated
/* def AUTO_TEMPLATE
(// Outputs
.signal_f (signal_f),
// Inputs
.signal_d (signal_c), // AUTONOHOOKUP
.signal_e (signal_e), // AUTONOHOOKUP
.signal_e2 (signal_e2), // AUTONOHOOKUP
.signal_e3 ((signal_e3)),
);
*/
def u_def
(/*AUTOINST*/
// Outputs
.signal_f (signal_f), // Templated
// Inputs
.signal_d (signal_c), // Templated AUTONOHOOKUP
.signal_e (signal_e), // Templated AUTONOHOOKUP
.signal_e2 (signal_e2), // Templated AUTONOHOOKUP
.signal_e3 ((signal_e3))); // Templated
endmodule // xyz
module abc (/*AUTOARG*/
// Outputs
signal_c,
// Inputs
signal_a, signal_b
);
input [1:0] signal_a;
input [2:0] signal_b;
output signal_c;
endmodule // abc
module def (/*AUTOARG*/
// Outputs
signal_f,
// Inputs
signal_d, signal_e, signal_e2, signal_e3
);
input [1:0] signal_d;
input [2:0] signal_e;
input [3:0] signal_e2;
input [3:0] signal_e3;
output signal_f;
endmodule // def
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : PIO_EP_MEM_ACCESS.v
// Version : 1.7
//--
//-- Description: Endpoint Memory Access Unit. This module provides access functions
//-- to the Endpoint memory aperture.
//--
//-- Read Access: Module returns data for the specifed address and
//-- byte enables selected.
//--
//-- Write Access: Module accepts data, byte enables and updates
//-- data when write enable is asserted. Modules signals write busy
//-- when data write is in progress.
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
`define TCQ 1
`define PIO_MEM_ACCESS_WR_RST 3'b000
`define PIO_MEM_ACCESS_WR_WAIT 3'b001
`define PIO_MEM_ACCESS_WR_READ 3'b010
`define PIO_MEM_ACCESS_WR_WRITE 3'b100
module PIO_EP_MEM_ACCESS (
clk,
rst_n,
// Read Access
rd_addr_i, // I [10:0]
rd_be_i, // I [3:0]
rd_data_o, // O [31:0]
// Write Access
wr_addr_i, // I [10:0]
wr_be_i, // I [7:0]
wr_data_i, // I [31:0]
wr_en_i, // I
wr_busy_o // O
);
input clk;
input rst_n;
// * Read Port
input [10:0] rd_addr_i;
input [3:0] rd_be_i;
output [31:0] rd_data_o;
// * Write Port
input [10:0] wr_addr_i;
input [7:0] wr_be_i;
input [31:0] wr_data_i;
input wr_en_i;
output wr_busy_o;
wire [31:0] rd_data_o;
reg [31:0] rd_data_raw_o;
wire [31:0] rd_data0_o, rd_data1_o, rd_data2_o, rd_data3_o;
wire wr_busy_o;
reg write_en;
reg [31:0] post_wr_data;
reg [31:0] w_pre_wr_data;
reg [2:0] wr_mem_state;
reg [31:0] pre_wr_data;
wire [31:0] w_pre_wr_data0;
wire [31:0] w_pre_wr_data1;
wire [31:0] w_pre_wr_data2;
wire [31:0] w_pre_wr_data3;
reg [31:0] pre_wr_data0_q, pre_wr_data1_q, pre_wr_data2_q, pre_wr_data3_q;
reg [31:0] DW0, DW1, DW2;
// ** Memory Write Process
// * Extract current data bytes. These need to be swizzled
// * BRAM storage format :
// * data[31:0] = { byte[3], byte[2], byte[1], byte[0] (lowest addr) }
wire [7:0] w_pre_wr_data_b3 = pre_wr_data[31:24];
wire [7:0] w_pre_wr_data_b2 = pre_wr_data[23:16];
wire [7:0] w_pre_wr_data_b1 = pre_wr_data[15:08];
wire [7:0] w_pre_wr_data_b0 = pre_wr_data[07:00];
// * Extract new data bytes from payload
// * TLP Payload format :
// * data[31:0] = { byte[0] (lowest addr), byte[2], byte[1], byte[3] }
wire [7:0] w_wr_data_b3 = wr_data_i[07:00];
wire [7:0] w_wr_data_b2 = wr_data_i[15:08];
wire [7:0] w_wr_data_b1 = wr_data_i[23:16];
wire [7:0] w_wr_data_b0 = wr_data_i[31:24];
always @(posedge clk or negedge rst_n) begin
if ( !rst_n ) begin
pre_wr_data <= 32'b0;
post_wr_data <= 32'b0;
pre_wr_data <= 32'b0;
write_en <= 1'b0;
pre_wr_data0_q <= 32'b0;
pre_wr_data1_q <= 32'b0;
pre_wr_data2_q <= 32'b0;
pre_wr_data3_q <= 32'b0;
wr_mem_state <= `PIO_MEM_ACCESS_WR_RST;
end else begin
case ( wr_mem_state )
`PIO_MEM_ACCESS_WR_RST : begin
if (wr_en_i) begin // read state
wr_mem_state <= `PIO_MEM_ACCESS_WR_WAIT; //Pipelining happens in RAM's internal output reg.
end else begin
write_en <= 1'b0;
wr_mem_state <= `PIO_MEM_ACCESS_WR_RST;
end
end
`PIO_MEM_ACCESS_WR_WAIT : begin
// * Pipeline B port data before processing. Virtex 5 Block RAMs have internal
// output register enabled.
//pre_wr_data0_q <= w_pre_wr_data0;
// pre_wr_data1_q <= w_pre_wr_data1;
// pre_wr_data2_q <= w_pre_wr_data2;
// pre_wr_data3_q <= w_pre_wr_data3;
write_en <= 1'b0;
wr_mem_state <= `PIO_MEM_ACCESS_WR_READ ;
end
`PIO_MEM_ACCESS_WR_READ : begin
// * Now save the selected BRAM B port data out
pre_wr_data <= w_pre_wr_data;
write_en <= 1'b0;
wr_mem_state <= `PIO_MEM_ACCESS_WR_WRITE;
end
`PIO_MEM_ACCESS_WR_WRITE : begin
// * Merge new enabled data and write target BlockRAM location
post_wr_data <= {{wr_be_i[3] ? w_wr_data_b3 : w_pre_wr_data_b3},
{wr_be_i[2] ? w_wr_data_b2 : w_pre_wr_data_b2},
{wr_be_i[1] ? w_wr_data_b1 : w_pre_wr_data_b1},
{wr_be_i[0] ? w_wr_data_b0 : w_pre_wr_data_b0}};
write_en <= 1'b1;
wr_mem_state <= `PIO_MEM_ACCESS_WR_RST;
end
endcase
end
end
// * Write controller busy
assign wr_busy_o = wr_en_i | (wr_mem_state != `PIO_MEM_ACCESS_WR_RST);
// * Select BlockRAM output based on higher 2 address bits
always @* // (wr_addr_i or pre_wr_data0_q or pre_wr_data1_q or pre_wr_data2_q or pre_wr_data3_q) begin
begin
case ({wr_addr_i[10:9]}) // synthesis parallel_case full_case
2'b00 : w_pre_wr_data = w_pre_wr_data0;
2'b01 : w_pre_wr_data = w_pre_wr_data1;
2'b10 : w_pre_wr_data = w_pre_wr_data2;
2'b11 : w_pre_wr_data = w_pre_wr_data3;
endcase
end
// * Memory Read Controller
wire rd_data0_en = {rd_addr_i[10:9] == 2'b00};
wire rd_data1_en = {rd_addr_i[10:9] == 2'b01};
wire rd_data2_en = {rd_addr_i[10:9] == 2'b10};
wire rd_data3_en = {rd_addr_i[10:9] == 2'b11};
always @(rd_addr_i or rd_data0_o or rd_data1_o or rd_data2_o or rd_data3_o)
begin
case ({rd_addr_i[10:9]}) // synthesis parallel_case full_case
2'b00 : rd_data_raw_o = rd_data0_o;
2'b01 : rd_data_raw_o = rd_data1_o;
2'b10 : rd_data_raw_o = rd_data2_o;
2'b11 : rd_data_raw_o = rd_data3_o;
endcase
end
// Handle Read byte enables
assign rd_data_o = {{rd_be_i[0] ? rd_data_raw_o[07:00] : 8'h0},
{rd_be_i[1] ? rd_data_raw_o[15:08] : 8'h0},
{rd_be_i[2] ? rd_data_raw_o[23:16] : 8'h0},
{rd_be_i[3] ? rd_data_raw_o[31:24] : 8'h0}};
EP_MEM EP_MEM (
.clk_i(clk),
.a_rd_a_i_0(rd_addr_i[8:0]), // I [8:0]
.a_rd_en_i_0(rd_data0_en), // I [1:0]
.a_rd_d_o_0(rd_data0_o), // O [31:0]
.b_wr_a_i_0(wr_addr_i[8:0]), // I [8:0]
.b_wr_d_i_0(post_wr_data), // I [31:0]
.b_wr_en_i_0({write_en & (wr_addr_i[10:9] == 2'b00)}), // I
.b_rd_d_o_0(w_pre_wr_data0[31:0]), // O [31:0]
.b_rd_en_i_0({wr_addr_i[10:9] == 2'b00}), // I
.a_rd_a_i_1(rd_addr_i[8:0]), // I [8:0]
.a_rd_en_i_1(rd_data1_en), // I [1:0]
.a_rd_d_o_1(rd_data1_o), // O [31:0]
.b_wr_a_i_1(wr_addr_i[8:0]), // [8:0]
.b_wr_d_i_1(post_wr_data), // [31:0]
.b_wr_en_i_1({write_en & (wr_addr_i[10:9] == 2'b01)}), // I
.b_rd_d_o_1(w_pre_wr_data1[31:0]), // [31:0]
.b_rd_en_i_1({wr_addr_i[10:9] == 2'b01}), // I
.a_rd_a_i_2(rd_addr_i[8:0]), // I [8:0]
.a_rd_en_i_2(rd_data2_en), // I [1:0]
.a_rd_d_o_2(rd_data2_o), // O [31:0]
.b_wr_a_i_2(wr_addr_i[8:0]), // I [8:0]
.b_wr_d_i_2(post_wr_data), // I [31:0]
.b_wr_en_i_2({write_en & (wr_addr_i[10:9] == 2'b10)}), // I
.b_rd_d_o_2(w_pre_wr_data2[31:0]), // I [31:0]
.b_rd_en_i_2({wr_addr_i[10:9] == 2'b10}), // I
.a_rd_a_i_3(rd_addr_i[8:0]), // [8:0]
.a_rd_en_i_3(rd_data3_en), // [1:0]
.a_rd_d_o_3(rd_data3_o), // O [31:0]
.b_wr_a_i_3(wr_addr_i[8:0]), // I [8:0]
.b_wr_d_i_3(post_wr_data), // I [31:0]
.b_wr_en_i_3({write_en & (wr_addr_i[10:9] == 2'b11)}), // I
.b_rd_d_o_3(w_pre_wr_data3[31:0]), // I [31:0]
.b_rd_en_i_3({wr_addr_i[10:9] == 2'b11}) // I
);
// synthesis translate_off
reg [8*20:1] state_ascii;
always @(wr_mem_state)
begin
if (wr_mem_state==`PIO_MEM_ACCESS_WR_RST) state_ascii <= #`TCQ "PIO_MEM_WR_RST";
else if (wr_mem_state==`PIO_MEM_ACCESS_WR_WAIT) state_ascii <= #`TCQ "PIO_MEM_WR_WAIT";
else if (wr_mem_state==`PIO_MEM_ACCESS_WR_READ) state_ascii <= #`TCQ "PIO_MEM_WR_READ";
else if (wr_mem_state==`PIO_MEM_ACCESS_WR_WRITE) state_ascii <= #`TCQ "PIO_MEM_WR_WRITE";
else state_ascii <= #`TCQ "PIO MEM STATE ERR";
end
// synthesis translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLXTP_BLACKBOX_V
`define SKY130_FD_SC_LS__DLXTP_BLACKBOX_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlxtp (
Q ,
D ,
GATE
);
output Q ;
input D ;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLXTP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O311AI_BLACKBOX_V
`define SKY130_FD_SC_LS__O311AI_BLACKBOX_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o311ai (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O311AI_BLACKBOX_V
|
module UAdder (out,carry_out,overflow,A,B,C_in);
output [31:0]out;
output carry_out,overflow;
input [31:0] A,B;
input C_in;
wire [6:0] carry;
CLA_4bit cc1(out[3:0],carry[0],A[3:0],B[3:0],C_in);
CLA_4bit cc2(out[7:4],carry[1],A[7:4],B[7:4],carry[0]);
CLA_4bit cc3(out[11:8],carry[2],A[11:8],B[11:8],carry[1]);
CLA_4bit cc4(out[15:12],carry[3],A[15:12],B[15:12],carry[2]);
CLA_4bit cc5(out[19:16],carry[4],A[19:16],B[19:16],carry[3]);
CLA_4bit cc6(out[23:20],carry[5],A[23:20],B[23:20],carry[4]);
CLA_4bit cc7(out[27:24],carry[6],A[27:24],B[27:24],carry[5]);
CLA_4bito cc8(out[31:28],carry_out,overflow,A[31:28],B[31:28],carry[6]);
endmodule
module CLA_4bit(out,carry_out,A,B,C_in);
output [3:0]out;
output carry_out;
input [3:0] A,B;
input C_in;
wire [3:0] p,g;
wire [9:0] andl1;
wire [3:0] carry ;
xor xx1(p[0],A[0],B[0]);
xor xx2(p[1],A[1],B[1]);
xor xx3(p[2],A[2],B[2]);
xor xx4(p[3],A[3],B[3]);
and aa1(g[0],A[0],B[0]);
and aa2(g[1],A[1],B[1]);
and aa3(g[2],A[2],B[2]);
and aa4(g[3],A[3],B[3]);
and al1(andl1[0],p[0],C_in);
and al2(andl1[1],p[1],g[0]);
and al3(andl1[2],p[1],p[0],C_in);
and al4(andl1[3],p[2],g[1]);
and al5(andl1[4],p[2],p[1],g[0]);
and al6(andl1[5],p[2],p[1],p[0],C_in);
and al7(andl1[6],p[3],g[2]);
and al8(andl1[7],p[3],p[2],g[1]);
and al9(andl1[8],p[3],p[2],p[1],g[0]);
and al10(andl1[9],p[3],p[2],p[1],p[0],C_in);
or oo1(carry[0],g[0],andl1[0]);
or oo2(carry[1],g[1],andl1[1],andl1[2]);
or oo3(carry[2],g[2],andl1[3],andl1[4],andl1[5]);
or oo4(carry_out,g[3],andl1[6],andl1[7],andl1[8],andl1[9]);
xor xs1(out[0],p[0],C_in);
xor xs2(out[1],p[1],carry[0]);
xor xs3(out[2],p[2],carry[1]);
xor xs4(out[3],p[3],carry[2]);
endmodule
module CLA_4bito(out,carry_out,overflow,A,B,C_in);
output [3:0]out;
output carry_out,overflow;
input [3:0] A,B;
input C_in;
wire [3:0] p,g;
wire [9:0] andl1;
wire [2:0] carry ;
xor xx1(p[0],A[0],B[0]);
xor xx2(p[1],A[1],B[1]);
xor xx3(p[2],A[2],B[2]);
xor xx4(p[3],A[3],B[3]);
and aa1(g[0],A[0],B[0]);
and aa2(g[1],A[1],B[1]);
and aa3(g[2],A[2],B[2]);
and aa4(g[3],A[3],B[3]);
and al1(andl1[0],p[0],C_in);
and al2(andl1[1],p[1],g[0]);
and al3(andl1[2],p[1],p[0],C_in);
and al4(andl1[3],p[2],g[1]);
and al5(andl1[4],p[2],p[1],g[0]);
and al6(andl1[5],p[2],p[1],p[0],C_in);
and al7(andl1[6],p[3],g[2]);
and al8(andl1[7],p[3],p[2],g[1]);
and al9(andl1[8],p[3],p[2],p[1],g[0]);
and al10(andl1[9],p[3],p[2],p[1],p[0],C_in);
or oo1(carry[0],g[0],andl1[0]);
or oo2(carry[1],g[1],andl1[1],andl1[2]);
or oo3(carry[2],g[2],andl1[3],andl1[4],andl1[5]);
or oo4(carry_out,g[3],andl1[6],andl1[7],andl1[8],andl1[9]);
xor xs1(out[0],p[0],C_in);
xor xs2(out[1],p[1],carry[0]);
xor xs3(out[2],p[2],carry[1]);
xor xs4(out[3],p[3],carry[2]);
assign overflow=carry_out^carry[2];
endmodule
/*
//Define the stimulus (top level module)
module stimulus;
//Set up variables
reg signed[31:0] A, B;
reg CIN;
wire signed[31:0] SUM;
wire COUT,overflow;
//Instantiate the 4-bit full adder
UAdder fa4bit(SUM, COUT,overflow, A, B, CIN);
//Setup the monitoring for signal values
initial
begin
$monitor($time,": A = %d, B = %d, CIN = %d, --- SUM = %d, COUT = %d,overflow=%d", A, B, CIN, SUM, COUT,overflow);
end
// Stimulate inputs
initial
begin
A=32'd1; B=-32'd1; CIN=1'b0;
#5 A=32'd13; B=-32'd64; CIN=1'b1;
#5 A=32'd2; B=32'd5; CIN=1'b0;
#5 A=32'd9; B=32'd9; CIN=1'b0;
#5 A=32'd10; B=32'd15; CIN=1'b0;
end
endmodule
*/
|
module random_gen(
input reset,
input clock,
input init,
input [3:0] retry_count,
output reg trigger
);
reg [9:0] random_sequence;
reg [9:0] random;
reg [9:0] random_counter;
reg [7:0] slot_time_counter;
always @ (posedge clock)
if (reset)
random_sequence <= 0;
else
random_sequence <= {random_sequence[8:0],~(random_sequence[2]^random_sequence[9])};
always @ (*)
case (retry_count)
4'h0 : random = {9'b0, random_sequence[0]};
4'h1 : random = {8'b0, random_sequence[1:0]};
4'h2 : random = {7'b0, random_sequence[2:0]};
4'h3 : random = {6'b0, random_sequence[3:0]};
4'h4 : random = {5'b0, random_sequence[4:0]};
4'h5 : random = {4'b0, random_sequence[5:0]};
4'h6 : random = {3'b0, random_sequence[6:0]};
4'h7 : random = {2'b0, random_sequence[7:0]};
4'h8 : random = {1'b0, random_sequence[8:0]};
4'h9 : random = { random_sequence[9:0]};
default : random = { random_sequence[9:0]};
endcase
always @ (posedge clock)
if (reset)
slot_time_counter <= 0;
else if(init)
slot_time_counter <= 0;
else if(!trigger)
slot_time_counter <= slot_time_counter + 1;
always @ (posedge clock)
if (reset)
random_counter <= 0;
else if (init)
random_counter <= random;
else if (random_counter != 0 && slot_time_counter == 255)
random_counter <= random_counter - 1;
always @ (posedge clock)
if (reset)
trigger <= 1;
else if (init)
trigger <= 0;
else if (random_counter == 0)
trigger <= 1;
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// //
// CDC (clock domain crossing) general purpose FIFO with gray counter //
// //
// Copyright (C) 2011 Iztok Jeras //
// //
////////////////////////////////////////////////////////////////////////////////
// //
// This RTL is free hardware: you can redistribute it and/or modify //
// it under the terms of the GNU Lesser General Public License //
// as published by the Free Software Foundation, either //
// version 3 of the License, or (at your option) any later version. //
// //
// This RTL is distributed in the hope that it will be useful, //
// but WITHOUT ANY WARRANTY; without even the implied warranty of //
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the //
// GNU General Public License for more details. //
// //
// You should have received a copy of the GNU General Public License //
// along with this program. If not, see <http://www.gnu.org/licenses/>. //
// //
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// //
// Handshaking protocol: //
// //
// Both the input and the output port employ the same handshaking mechanism. //
// The data source sets the valid signal (*_vld) and the data drain confirms //
// the transfer by setting the ready signal (*_rdy). //
// //
// -------- vld ----------------- vld -------- //
// ) S | ------> | D S | ------> | D ( //
// ( R | | R CDC R | | R ) //
// ) C | <------ | N C | <------ | N ( //
// -------- rdy ----------------- rdy -------- //
// //
////////////////////////////////////////////////////////////////////////////////
module cdc #(
// size parameters
parameter integer DW = 1, // data width
parameter integer FF = 4, // FIFO depth
// implementation parameters
parameter integer SS = 2, // synchronization stages
// interface parameters
parameter RI = 1, // registered input data
parameter RO = 1 // registered output data
)(
// input port
input wire ffi_clk, // clock
input wire ffi_rst, // reset
input wire [DW-1:0] ffi_dat, // data
input wire ffi_vld, // valid
output wire ffi_rdy, // ready
// output port
input wire ffo_clk, // clock
input wire ffo_rst, // reset
output wor [DW-1:0] ffo_dat, // data
output wire ffo_vld, // valid
input wire ffo_rdy // ready
);
`ifdef XC3S250E
// Xilinx ISE used to compile the Spartan 3E device does not support the $clog2 function
function integer clog2 (input integer value); begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end endfunction
localparam CW = clog2(FF)+1; // counter width
`else
localparam CW = $clog2(FF)+1; // counter width
`endif
localparam G0 = {1'b1,{CW-1{1'b0}}};
////////////////////////////////////////////////////////////////////////////////
// gray code related functions
////////////////////////////////////////////////////////////////////////////////
// conversion from integer to gray
function [CW-1:0] int2gry (input [CW-1:0] val);
integer i;
begin
for (i=0; i<CW-1; i=i+1) int2gry[i] = val[i+1] ^ val[i];
int2gry[CW-1] = val[CW-1];
end
endfunction
// conversion from gray to integer
function [CW-1:0] gry2int (input [CW-1:0] val);
integer i;
begin
gry2int[CW-1] = val[CW-1];
for (i=CW-1; i>0; i=i-1) gry2int[i-1] = val[i-1] ^ gry2int[i];
end
endfunction
// gray increment (with conversion into integer and back to gray)
function [CW-1:0] gry_inc (input [CW-1:0] gry_gry);
begin
gry_inc = int2gry (gry2int (gry_gry) + 'd1);
end
endfunction
////////////////////////////////////////////////////////////////////////////////
// local signals //
////////////////////////////////////////////////////////////////////////////////
// input port
wire ffi_trn; // transfer
wire ffi_end; // counter end
reg [CW-1:0] ffi_ref; // counter gray reference
reg [CW-1:0] ffi_gry; // counter gray
reg [CW-1:0] ffi_syn [SS-1:0]; // synchronization
// CDC FIFO memory
reg [DW-1:0] cdc_mem [0:FF-1];
// output port
wire ffo_trn; // transfer
wire ffo_end; // counter end
reg [CW-1:0] ffo_gry; // counter gray
reg [CW-1:0] ffo_syn [SS-1:0]; // synchronization
// generate loop index
genvar i;
////////////////////////////////////////////////////////////////////////////////
// input port control/status logic //
////////////////////////////////////////////////////////////////////////////////
// transfer
assign ffi_trn = ffi_vld & ffi_rdy;
// synchronization
generate for (i=0; i<SS; i=i+1) begin : ffi_cdc
if (i==0) begin
always @ (posedge ffi_clk, posedge ffi_rst)
if (ffi_rst) ffi_syn [i] <= {CW{1'b0}};
else ffi_syn [i] <= ffo_gry;
end else begin
always @ (posedge ffi_clk, posedge ffi_rst)
if (ffi_rst) ffi_syn [i] <= {CW{1'b0}};
else ffi_syn [i] <= ffi_syn [i-1];
end
end endgenerate
// counter gray
always @ (posedge ffi_clk, posedge ffi_rst)
if (ffi_rst) ffi_gry <= {CW{1'b0}};
else if (ffi_trn) ffi_gry <= ffi_end ? ffi_gry ^ G0 : gry_inc (ffi_gry);
// counter gray reference
always @ (posedge ffi_clk, posedge ffi_rst)
if (ffi_rst) ffi_ref <= int2gry(-FF);
else if (ffi_trn) ffi_ref <= ffi_end ? ffi_ref ^ G0 : gry_inc (ffi_ref);
// status
assign ffi_rdy = ffi_syn [SS-1] != ffi_ref;
////////////////////////////////////////////////////////////////////////////////
// input port data/memory logic //
////////////////////////////////////////////////////////////////////////////////
// binary counter
reg [CW-2:0] ffi_cnt;
// counter end
assign ffi_end = ffi_cnt == (FF-1);
// counter binary
always @ (posedge ffi_clk, posedge ffi_rst)
if (ffi_rst) ffi_cnt <= 'b0;
else if (ffi_trn) ffi_cnt <= ffi_end ? 'b0 : ffi_cnt + 'b1;
// data memory
always @ (posedge ffi_clk)
if (ffi_trn) cdc_mem [ffi_cnt] <= ffi_dat;
////////////////////////////////////////////////////////////////////////////////
// output port data/memory logic //
////////////////////////////////////////////////////////////////////////////////
// one hot counter
reg [CW-2:0] ffo_cnt;
// counter end
assign ffo_end = ffo_cnt == (FF-1);
// counter one hot
always @ (posedge ffo_clk, posedge ffo_rst)
if (ffo_rst) ffo_cnt <= 'b0;
else if (ffo_trn) ffo_cnt <= ffo_end ? 'b0 : ffo_cnt + 'b1;
// asynchronous output data
assign ffo_dat = cdc_mem [ffo_cnt];
////////////////////////////////////////////////////////////////////////////////
// output port control/status logic //
////////////////////////////////////////////////////////////////////////////////
// transfer
assign ffo_trn = ffo_vld & ffo_rdy;
// synchronization
generate for (i=0; i<SS; i=i+1) begin : ffo_cdc
if (i==0) begin
always @ (posedge ffo_clk, posedge ffo_rst)
if (ffo_rst) ffo_syn [i] <= {CW{1'b0}};
else ffo_syn [i] <= ffi_gry;
end else begin
always @ (posedge ffo_clk, posedge ffo_rst)
if (ffo_rst) ffo_syn [i] <= {CW{1'b0}};
else ffo_syn [i] <= ffo_syn [i-1];
end
end endgenerate
// counter gray
always @ (posedge ffo_clk, posedge ffo_rst)
if (ffo_rst) ffo_gry <= {CW{1'b0}};
else if (ffo_trn) ffo_gry <= ffo_end ? ffo_gry ^ G0 : gry_inc (ffo_gry);
// status
assign ffo_vld = ffo_syn [SS-1] != ffo_gry;
endmodule
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 24080 $
// $Date: 2011-05-18 15:32:52 -0400 (Wed, 18 May 2011) $
`ifdef BSV_WARN_REGFILE_ADDR_RANGE
`else
`define BSV_WARN_REGFILE_ADDR_RANGE 0
`endif
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// Multi-ported Register File -- initializable from a file.
module RegFileLoad(CLK,
ADDR_IN, D_IN, WE,
ADDR_1, D_OUT_1,
ADDR_2, D_OUT_2,
ADDR_3, D_OUT_3,
ADDR_4, D_OUT_4,
ADDR_5, D_OUT_5
);
parameter file = "";
parameter addr_width = 1;
parameter data_width = 1;
parameter lo = 0;
parameter hi = 1;
parameter binary = 0;
input CLK;
input [addr_width - 1 : 0] ADDR_IN;
input [data_width - 1 : 0] D_IN;
input WE;
input [addr_width - 1 : 0] ADDR_1;
output [data_width - 1 : 0] D_OUT_1;
input [addr_width - 1 : 0] ADDR_2;
output [data_width - 1 : 0] D_OUT_2;
input [addr_width - 1 : 0] ADDR_3;
output [data_width - 1 : 0] D_OUT_3;
input [addr_width - 1 : 0] ADDR_4;
output [data_width - 1 : 0] D_OUT_4;
input [addr_width - 1 : 0] ADDR_5;
output [data_width - 1 : 0] D_OUT_5;
reg [data_width - 1 : 0] arr[lo:hi];
initial
begin : init_rom_block
if (binary)
$readmemb(file, arr, lo, hi);
else
$readmemh(file, arr, lo, hi);
end // initial begin
always@(posedge CLK)
begin
if (WE)
arr[ADDR_IN] <= `BSV_ASSIGNMENT_DELAY D_IN;
end // always@ (posedge CLK)
assign D_OUT_1 = arr[ADDR_1];
assign D_OUT_2 = arr[ADDR_2];
assign D_OUT_3 = arr[ADDR_3];
assign D_OUT_4 = arr[ADDR_4];
assign D_OUT_5 = arr[ADDR_5];
// synopsys translate_off
always@(posedge CLK)
begin : runtime_check
reg enable_check;
enable_check = `BSV_WARN_REGFILE_ADDR_RANGE ;
if ( enable_check )
begin
if (( ADDR_1 < lo ) || (ADDR_1 > hi) )
$display( "Warning: RegFile: %m -- Address port 1 is out of bounds: %h", ADDR_1 ) ;
if (( ADDR_2 < lo ) || (ADDR_2 > hi) )
$display( "Warning: RegFile: %m -- Address port 2 is out of bounds: %h", ADDR_2 ) ;
if (( ADDR_3 < lo ) || (ADDR_3 > hi) )
$display( "Warning: RegFile: %m -- Address port 3 is out of bounds: %h", ADDR_3 ) ;
if (( ADDR_4 < lo ) || (ADDR_4 > hi) )
$display( "Warning: RegFile: %m -- Address port 4 is out of bounds: %h", ADDR_4 ) ;
if (( ADDR_5 < lo ) || (ADDR_5 > hi) )
$display( "Warning: RegFile: %m -- Address port 5 is out of bounds: %h", ADDR_5 ) ;
if ( WE && ( ADDR_IN < lo ) || (ADDR_IN > hi) )
$display( "Warning: RegFile: %m -- Write Address port is out of bounds: %h", ADDR_IN ) ;
end
end
// synopsys translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A32OI_BLACKBOX_V
`define SKY130_FD_SC_HS__A32OI_BLACKBOX_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a32oi (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A32OI_BLACKBOX_V
|
[利用verilog实现FIFO]
/* 摘自 http://lihaichuan.blog.51cto.com/498079/1307686 */
// 摘要：本文先介绍了一下关于FIFO的基本概念，工作原理，功能，同步与异步的分类等。
// 然后基于RAM实现了一个同步FIFO。该FIFO通过巧妙地应用地址位和状态位的结合实现对空、满标志位的控制。从而减小了设计的复杂度。
[关键词：FIFO，同步，仿真，quartus。]
#1. [FIFO简介]
// FIFO(FirstInputFirstOutput)一种先进先出的数据缓存器，
// 先进入的数据先从FIFO缓存器中读出，与RAM相比没有外部读写地址线,使用比较简单，
// 但只能顺序写入数据，顺序的读出数据，
// 不能像普通存储器那样可以由地址线决定读取或写入某个指定的地址。
#1.1 [FIFO的工作原理]
// 对于FIFO，读写指针都指向一个存储器的初始位置，每进行一次读写操作，相应的指针就递增一次，指向下一个存储器位置。
// 当指针移动到了存储器的最后一个位置时，它又重新跳回初始位置。在FIFO非满或非空的情况下，这个过程将随着读写控制信号的变化一直进行下去。
// 如果FIFO处于空的状态，下一个读动作将会导致向下溢(underflow)，一个无效的数据被读人；同样，对于一个满了的FIFO，进行写动作将会导致向上溢出(overflow)，一个有用的数据被新写入的数据覆盖。
// 这两种情况都属于误动作，因此需要设置满和空两个信号，对满信号置位表示FIFO处于满状态，对满信号复位表示FIFO非满，还有空间可以写入数据；对空信号置位表示FIFO处于空状态，对空信号复位表示FIFO非空，
// 还有有效的数据可以读出。
// FIFO设计的难点在于怎样判断FIFO的空/满状态。
// 为了保证数据正确的写入或读出，而不发生溢出或读空的状态出现，
// 必须保证FIFO在满的情况下，不能进行写操作。在空的状态下不能进行读操作。
#1.2 [FIFO的一些重要参数]
// FIFO的宽度：也就是英文资料里常看到的THEWIDTH，它指的是FIFO一次读写操作的数据位，就像MCU有8位和16位，ARM32位等等。
// FIFO的深度：THEDEEPTH，它指的是FIFO可以存储多少个N位的数据（如果宽度为N）。如一个8位的FIFO，若深度为8，它可以存储8个8位的数据，深度为12，就可以存储12个8位的数据。
// 满标志：FIFO已满或将要满时由FIFO的状态电路送出的一个信号，以阻止FIFO的写操作继续向FIFO中写数据而造成溢出（overflow）。
// 空标志：FIFO已空或将要空时由FIFO的状态电路送出的一个信号，以阻止FIFO的读操作继续从FIFO中读出数据而造成无效数据的读出（underflow）。
// 读指针：指向下一个读出地址。读完后自动加1。
// 写指针：指向下一个要写入的地址的，写完自动加1。
// FIFO读时钟：读操作所遵循的时钟，在每个时钟沿来临时读数据。
// FIFO写时钟：写操作所遵循的时钟，在每个时钟沿来临时写数据。
#1.3 [FIFO的功能]
// FIFO作为一种先进先出的缓存，适合于对连续的数据流进行缓存。可将数据储存集中起来。减少频繁的总线操作。减少CPU的负担。
// FIFO一般用于不同时钟域之间的数据传输。比如FIFO的一端是AD数据采集，另一端为PCI总线，那么在两个不同的时钟域间就可以采用FIFO来作为数据缓冲。
// 另外对于不同宽度的数据接口也可以用FIFO，例如单片机位8位数据输出，而DSP可能是16位数据输入，在单片机与DSP连接时就可以使用FIFO来达到数据匹配的目的。
#2. [FIFO的分类]
// 根均FIFO工作的时钟域，可以将FIFO分为同步FIFO和异步FIFO。同步FIFO是指读时钟和写时钟为同一个时钟。
// 在时钟沿来临时同时发生读写操作。异步FIFO是指读写时钟不一致，读写时钟是互相独立的。
// 对于异步FIFO一般有两种理解，一种是读写操作不使用时钟，而是直接采用wr_en(WriteEnabled)和rd_en(ReadEnabled)来进行控制；
// 另一种，是指在FPGA和ASIC设计中，异步FIFO具有两个时钟的双口FIFO,读些操作在各自的时钟延上进行，在两个不同时钟下，可以同时进行读或写。
// 异步FIFO在FPGA设计汇总占用的资源比同步FIFO大很多，所以尽量采用同步FIFO设计。
// 而当物理系统中存在多个时钟信号，并且需要在这几个时钟域之间传输数据的时候，寄存器会由于时钟信号的频率不匹配而产生数据丢失等情况，
// 这个时候需要用异步FIFO来进行缓存，保证数据能够正确传输。所以异步FIFO功能更强。所以，对于一些常用的嵌入式环境中，如ARM系统内绝大部分外设接口都是异步FIFO。
// 由于异步FIFO的实现复杂。本文将实现的为同步FIFO。
#3. [同步FIFO的实现]
// FIFO存储器的实现目前主要是分为基于移位寄存器的类型和基于RAM的类型。本文要实现的是基于RAM的FIFO寄存器。
#3.1 [用verilog实现RAM]
// 本文编写了一个具有通用性的RAM的verilog代码。通过预编译宏定义RAM的深度和宽度为16和8，所以最后实现的是一个168的RAM。
`define DEL 1//用于检查输出的延迟
`define RAM_WIDTH 8//Ram的宽度
`define RAM_DEPTH 16//Ram的深度
`define ADDR_SZ 4//所需要的地址线位数
module ram16X8(clk,dataIn,dataOut,addr,wrN,oe);
//inout[`RAM_WIDTH-1:0]data;
input [`RAM_WIDTH-1:0]dataIn;//数据线
input clk;
input [`ADDR_SZ-1:0]addr;//地址线
input wrN;//写选择线
input oe;//允许输出线
output [`RAM_WIDTH-1:0]dataOut;
wire [`RAM_WIDTH-1:0]dataIn,dataOut;
wire [`ADDR_SZ-1:0]addr;
wire wrN,oe;
//RAM
reg[`RAM_WIDTH-1:0]mem[`RAM_DEPTH-1:0];
assign#`DELdataOut=oe?`RAM_WIDTH'bz:mem[addr];
always@(posedgeclk)begin
if(!wrN)
mem[addr]=dataIn;
end
endmodule
// 值得注意的一点是，在输出数据到数据线时，
[必须要有个延时（代码中的DEL）。]
// 这是因为硬件对输出允许线的判断本来就有个时间，如果没有这个延时，则容易使得系统出错。
#3.2 [FIFO具体实现]
#3.2.1 [基本实现思路]
// 空/满标志的产生是FIFO的核心部分。如何正确设计此部分的逻辑,直接影响到FIFO的性能。
// 本文所应用的方法是分别将读、写地址寄存器扩展一位,将最高位设置为状态位,其余低位作为地址位,指针由地址位以及状态位组成。
// 巧妙地应用地址位和状态位的结合实现对空、满标志位的控制。当读写指针的地址位和状态位全部吻合的时候,读写指针经历了相同次数的循环移动,
// 也就是说,FIFO处于空状态(图1(a));如果读写指针的地址位相同而状态位相反,写指针比读指针多循环一次,标志FIFO处于满状态(图1(b))。
// 在synFIFO的实现中，这两个读写地址寄存器分别是wr_cntr,rd_cntr。
#3.2.2 [FIFO外部接口]
// 同步FIFO的对外接口包括时钟，清零，读请求，写请求，数据输入总线，数据输出总线，空以及满信号。下面分别对同步FIFO的对外接口信号作一描述：
// 1．时钟，输入，用于同步FIFO的读和写，上升沿有效；
// 2．清零，输入，异步清零信号，低电平有效，该信号有效时，FIFO被清空；
// 3．写请求，输入，低电平有效，该信号有效时，表明外部电路请求向FIFO写入数据；
// 4．读请求，输入，低电平有效，该信号有效时，表明外部电路请求从FIFO中读取数据；
// 5．数据输入总线，输入，当写信号有效时，数据输入总线上的数据被写入到FIFO中；
// 6．数据输出总线，输出，当读信号有效时，数据从FIFO中被读出并放到数据输出总线上；
// 7．空，输出，高电平有效，当该信号有效时，表明FIFO中没有任何数据，全部为空；
// 8．满，输出，高电平有效，当该信号有效时，表明FIFO已经满了，没有空间可用来存贮数据。
// 以上的八种外接接口分别对应synFIFO模块代码中的clk，rstN，wrN，rdN，dataIn，dataOut，empty,full。
// 3.2.3synFIFO代码
//FIFORAM
module synFIFO(dataIn,dataOut,clk,rstN,wrN,rdN,empty,full);
input [7:0]dataIn;
input clk,rstN,wrN,rdN;
output empty,full;
output[7:0]dataOut;
reg[4:0]wr_cntr,rd_cntr;
wire[3:0]addr;
/*调用ram16X8模块，当wrN为低平有效且full为0时才写，而rdN为低平有效且empy为0时才读*/
ram16X8ram(.clk(clk),.dataIn(dataIn),.dataOut(dataOut),.addr(addr),.wrN(wrN||full),.oe(rdN||empty));
always@(posedgeclkornegedgerstN)
if(!rstN)wr_cntr<=0;
else if(!wrN&&!full)wr_cntr<=wr_cntr+1;
always@(posedgeclkornegedgerstN)
if(!rstN)rd_cntr<=0;
elseif(!rdN&&!empty)rd_cntr<=rd_cntr+1;
assignaddr=wrN?rd_cntr[3:0]:wr_cntr[3:0];
assignempty=(wr_cntr[3:0]==rd_cntr[3:0])&&!(wr_cntr[4]^rd_cntr[4]);
assignfull=(wr_cntr[3:0]==rd_cntr[3:0])&&(wr_cntr[4]^rd_cntr[4]);
endmodule
#4. [Quartus仿真] |
`timescale 1ns / 1ps
// nexys3MIPSSoC is a MIPS implementation originated from COAD projects
// Copyright (C) 2014 @Wenri, @dtopn, @Speed
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
module seven_seg_Dev_IO( input clk,
input rst,
input GPIOe0000000_we,
input [2:0] Test,
input [31:0] disp_cpudata,
input [31:0] Test_data0,
input [31:0] Test_data1,
input [31:0] Test_data2,
input [31:0] Test_data3,
input [31:0] Test_data4,
input [31:0] Test_data5,
input [31:0] Test_data6,
output[31:0] disp_num
);
endmodule
|
// MBT 7-28-2014
//
// Test source synchronous link.
//
// We model here two cores that have different clocks and are
// communicating over an I/O channel which has a third clock.
//
// Includes model reset logic with synchronizers and delayed
// communication after reset.
//
`include "bsg_defines.v"
module test_bsg_source_sync_input;
initial begin
$vcdpluson;
end
// three separate clocks: I/O, and the two cores communicating with each other
localparam core_0_half_period_lp = 5;
localparam io_master_half_period_lp = 7;
localparam core_1_half_period_lp = 6;
// across all frequency combinations, we need a little over 20 fifo slots
// so we round up to 32.
localparam lg_input_fifo_depth_lp = 5;
// for DDR at 500 mbps, we make token go at / 8 = 66 mbps
// this will keep the token clock nice and slow
localparam lg_credit_to_token_decimation_lp=3;
// number of bits width of a channel
localparam channel_width_lp=8;
// *************************************************
// independent clocks
//
//
logic core_0_clk, core_1_clk, io_master_clk;
initial core_0_clk = 0;
always #(core_0_half_period_lp) core_0_clk = ~core_0_clk;
initial io_master_clk = 0;
always #(io_master_half_period_lp) io_master_clk = ~io_master_clk;
initial core_1_clk = 0;
always #(core_1_half_period_lp) core_1_clk = ~core_1_clk;
// *************************************************
// master resets
//
logic core_0_reset, core_1_reset;
localparam core_reset_cycles_hi_lp = 256;
localparam core_reset_cycles_lo_lp = 16;
// we model this as if the FPGA is driving this with an unknown clock.
initial
begin
core_0_reset = 0;
core_1_reset = 0;
// simple hack to wait based on maximum of clock periods
repeat (core_reset_cycles_lo_lp)
begin
@(negedge core_0_clk);
@(negedge core_1_clk);
@(negedge io_master_clk);
end
core_0_reset = 1;
core_1_reset = 1;
// simple hack to wait based on maximum of clock periods
repeat (core_reset_cycles_hi_lp)
begin
@(negedge core_0_clk);
@(negedge core_1_clk);
@(negedge io_master_clk);
end
core_0_reset = 0;
core_1_reset = 0;
$display("__________ ___________ _______________________________");
$display("\\______ \\\\_ _____/ / _____/\\_ _____/\\__ ___/");
$display(" | _/ | __)_ \\_____ \\ | __)_ | | ");
$display(" | | \\ | \\ / \\ | \\ | | ");
$display(" |____|_ //_______ //_______ //_______ / |____| ");
$display(" \\/ \\/ \\/ \\/ ");
end
// *****************************************
// * CORE 0 (sender)
// *
// *
// *
wire core_0_reset_sync, io_master_reset_sync, token_reset_sync;
// reset synchronizer: core clock reset
bsg_sync_sync #(.width_p(1)) bss_core_reset
(.oclk_i(core_0_clk)
,.iclk_data_i(core_0_reset)
,.oclk_data_o(core_0_reset_sync)
);
// reset synchronizer: master clock reset
bsg_sync_sync #(.width_p(1)) bss_io_master_reset
(.oclk_i(io_master_clk)
,.iclk_data_i(core_0_reset)
,.oclk_data_o(io_master_reset_sync)
);
// reset synchronizer: token reset
bsg_sync_sync #(.width_p(1)) bss_token_reset
(.oclk_i(io_master_clk)
,.iclk_data_i(core_0_reset)
,.oclk_data_o(token_reset_sync)
);
logic [channel_width_lp-1:0] core_0_data_r;
logic core_0_valid_r;
// wait a certain number of cycles after reset before restarting
localparam lg_wait_cycles_activate_lp = 4;
wire core_reset_ready;
bsg_wait_after_reset #(.lg_wait_cycles_p(lg_wait_cycles_activate_lp)) bwar
(.reset_i(core_0_reset_sync)
,.clk_i(core_0_clk)
,.ready_r_o(core_reset_ready)
);
// only start sending after a certain number of cycles
assign core_0_valid_r = core_reset_ready;
wire core_0_yumi;
// transmit sequence of data values
always @(posedge core_0_clk)
if (core_0_reset_sync)
core_0_data_r <= 0;
else
if (core_0_yumi)
core_0_data_r <= core_0_data_r + 1;
// ***********************************************
// TOKEN RESET LOGIC
//
// reset logic for clearing output channel's
// token-clocked logic.
//
logic io_override_en;
logic [channel_width_lp+1-1:0] io_override_valid_data;
logic io_master_reset_sync_r;
logic [10:0] io_reset_counter_r;
always @(posedge io_master_clk)
begin
io_master_reset_sync_r <= io_master_reset_sync;
// on positive edge of reset, we initialize the counter
// the counter continuously counts during reset
// and is zero'd when not in reset
if (io_master_reset_sync)
begin
if (~io_master_reset_sync_r)
io_reset_counter_r <= 1;
else
io_reset_counter_r <= io_reset_counter_r + 1;
end
else
io_reset_counter_r <= 0;
end
// this asserts the override data while the reset counter
// is in its active portion
always_comb
begin
io_override_en = io_master_reset_sync;
io_override_valid_data = { 0'b0, 0'h00 };
// for 2^6 cycles, assert the "token reset code"
if (io_reset_counter_r[10:6] == 5'b00001)
io_override_valid_data = { 1'b1, 8'h80 };
end
// ***********************************************
// declare signals going out over transmission lines
// between input and output channel
//
wire io_clk_tline, io_valid_tline;
wire [channel_width_lp-1:0] io_data_tline;
wire token_clk_tline;
bsg_source_sync_output #(.lg_start_credits_p(lg_input_fifo_depth_lp)
,.lg_credit_to_token_decimation_p(lg_credit_to_token_decimation_lp)
,.channel_width_p(channel_width_lp)
) bsso_o1
(.core_clk_i(core_0_clk)
,.core_reset_i(core_0_reset_sync)
// core 0 side logical signals
,.core_data_i(core_0_data_r)
,.core_valid_i(core_0_valid_r)
,.core_yumi_o(core_0_yumi)
,.io_master_clk_i(io_master_clk)
,.io_reset_i(io_master_reset_sync)
,.io_override_en_i(io_override_en)
,.io_override_valid_data_i(io_override_valid_data)
,.io_clk_r_o(io_clk_tline) // output to other node
,.io_data_r_o(io_data_tline) // output to other node
,.io_valid_r_o(io_valid_tline) // output to other node
,.token_clk_i(token_clk_tline) // input from other node
,.token_reset_i(token_reset_sync) // from core 0
);
// *****************************************
// * CORE 1 (input side)
// *
// *
// *
localparam lg_io_delay_reset_lp = 6;
wire io_1_reset_sync, core_1_reset_sync;
bsg_sync_sync #(.width_p(1)) bss_core_1_reset
(.oclk_i(core_1_clk)
,.iclk_data_i(core_1_reset)
,.oclk_data_o(core_1_reset_sync)
);
bsg_sync_sync #(.width_p(1)) bss_io_1_reset
(.oclk_i(io_clk_tline)
,.iclk_data_i(core_1_reset)
,.oclk_data_o(io_1_reset_sync)
);
wire core_1_yumi;
wire core_1_valid;
wire [channel_width_lp-1:0] core_1_data;
bsg_source_sync_input #(.lg_fifo_depth_p(lg_input_fifo_depth_lp)
,.lg_credit_to_token_decimation_p(lg_credit_to_token_decimation_lp)
,.channel_width_p(channel_width_lp)
) bssi_i1
(.io_clk_i(io_clk_tline) // input from other node; starts on reset
,.io_reset_i(io_1_reset_sync)
,.io_data_i(io_data_tline) // input from other node
,.io_valid_i(io_valid_tline) // input from other node
,.io_edge_i(2'b11) // latch on both edges
,.io_token_r_o(token_clk_tline) // output to other node
,.io_snoop_r_o() // snoop input channel;
// for establishing calibration state
// on reset
,.io_trigger_mode_en_i(1'b0) // enable loop-back trigger mode
,.io_trigger_mode_alt_en_i(1'b0) // enable loop-back trigger mode: alternate trigger
,.core_clk_i(core_1_clk)
,.core_reset_i(core_1_reset_sync)
// core 1 side logical signals
,.core_data_o(core_1_data)
,.core_valid_o(core_1_valid)
,.core_yumi_i(core_1_yumi)
);
// consume all data
assign core_1_yumi = core_1_valid;
localparam cycle_counter_width_lp=32;
logic [cycle_counter_width_lp-1:0] core_0_ctr;
bsg_cycle_counter #(.width_p(cycle_counter_width_lp)) bcc_core0 (core_0_clk, core_0_reset_sync, core_0_ctr);
logic [cycle_counter_width_lp-1:0] core_1_ctr;
bsg_cycle_counter #(.width_p(cycle_counter_width_lp)) bcc_core1 (core_1_clk, core_1_reset_sync, core_1_ctr);
logic [cycle_counter_width_lp-1:0] io_ctr;
bsg_cycle_counter #(.width_p(cycle_counter_width_lp)) bcc_io (io_master_clk, io_master_reset_sync, io_ctr);
// non-synthesizable, TEST ONLY
logic [7:0] core_1_last_n, core_1_last_r = -1;
logic [5:0] top_bits = 0;
assign core_1_last_n = core_1_last_r+8'b1;
// *******************************************************
// *
// * Logging.
// *
// * These statements allow you to see, in time, when values are transmitted and received.
// *
// *
// * For this test, the number of cycles on the slowest clock should match the number of words
// * transmitted plus a small constant.
// *
// *
always @(negedge core_1_clk)
if (core_1_valid)
begin
$display("## ", core_0_ctr, io_ctr, core_1_ctr, " ## core 1 recv %d, %d",top_bits*256,core_1_data);
assert (core_1_last_n == core_1_data) else $error("##transmission error", core_1_last_r, core_1_data);
core_1_last_r <= core_1_last_n;
if (core_1_data == 8'hff)
begin
if (top_bits == 6'b000_111)
$finish("## DONE");
top_bits = top_bits+1;
end
end
always @(negedge core_0_clk)
if (core_0_yumi)
$display("## ", core_0_ctr, io_ctr, core_1_ctr, " ## core 0 sent %d",core_0_data_r);
always @(negedge io_master_clk)
if (io_valid_tline)
$display("## ", core_0_ctr, io_ctr, core_1_ctr, " ## io xmit %d",io_data_tline);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__INV_16_V
`define SKY130_FD_SC_LS__INV_16_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__inv_16 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__inv_16 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__INV_16_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRTN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__DLRTN_FUNCTIONAL_PP_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_lp__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dlrtn (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire intgate;
wire buf_Q ;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intgate, GATE_N );
sky130_fd_sc_lp__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, intgate, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRTN_FUNCTIONAL_PP_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19.04.2017 02:00:33
// Design Name:
// Module Name: dragster_spi_adapter
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module dragster_spi_adapter #
(
EXTENDED_CLOCKS = 3,
TRANSACTION_DEPTH = 128,
DATA_WIDTH = 16
)
(
input wire clk,
input wire reset,
input wire internal_mosi,
output wire internal_miso,
input wire internal_sck,
input wire[1:0] internal_ss,
output reg external_mosi,
input wire external_miso,
output wire external_sck,
output reg[1:0] external_ss
);
/* Ìû íå ìîæåì äåëàòü ñåëåêòû íà ïàìÿòè, ïîýòîìó äëÿ ýòîãî äåëà áóäåò âûäåëåí îòäåëüíûé ðåãèñòð. */
reg[DATA_WIDTH - 1 : 0] transactions[TRANSACTION_DEPTH - 1 : 0];
/* Ïîëó÷àòåëè. */
reg[1:0] slaves[TRANSACTION_DEPTH - 1 : 0];
/* Ðåãèñòð äëÿ àíàëèçà äàííûõ. Çäåñü ìû äåëàåì ñåëåêò è óòî÷íÿåì òèï îïåðàöèè, ïðîâåðÿÿ àäðåñíûé áàéò íà íàëè÷èå çíà÷åíèÿ 15. */
//reg[15:0] transaction;
/* Ñ÷åò÷èêè áèò */
reg[3:0] bit_counter;
reg[3:0] internal_bit_count;
reg[7:0] external_clock_count;
reg generate_external_clock;
reg clock_enable;
/* Êîëè÷åñòâî áóôåðèçèðîâàííûõ òðàíçàêöèé. */
reg[7:0] buffered_transaction_count;
/* Êîëè÷åñòâî òðàíçàêöèé îòïðàâëåííûõ â ñåíñîð. */
reg[7:0] forwarded_transaction_count;
/* Èíäåêñ òðàíçàêöèè áóôåðèçèðóåìîé â äàííûé ìîìåíò. Îòñþäà ìû ÷èòàòü íå áóäåì. */
reg[7:0] transaction_about_to_be_buffered;
integer counter;
assign external_sck = clock_enable ? clk : 0;
/* always ïî êëîêó èñòî÷íèêà */
always @ (negedge clk)
begin
if(!reset)
begin
forwarded_transaction_count <= 0;
bit_counter <= 0;
external_mosi <= 0;
external_ss <= 3;
clock_enable <= 0;
generate_external_clock <= 0;
external_clock_count <= 0;
end
else
begin
if(buffered_transaction_count > 0 && forwarded_transaction_count < buffered_transaction_count)
begin
clock_enable <= 1;
if(clock_enable && ~generate_external_clock)
begin
bit_counter <= bit_counter + 1;
external_ss <= slaves[forwarded_transaction_count];
external_mosi <= transactions[forwarded_transaction_count][bit_counter];
if(bit_counter == DATA_WIDTH - 1)
generate_external_clock <= 1;
end
else
begin
external_clock_count <= external_clock_count + 1;
if(EXTENDED_CLOCKS == 0 || external_clock_count == EXTENDED_CLOCKS)
begin
external_clock_count <= 0;
generate_external_clock <= 0;
clock_enable <= 0;
external_ss <= 3;
external_mosi <= 0;
if(forwarded_transaction_count == TRANSACTION_DEPTH - 1)
forwarded_transaction_count <= 0;
else forwarded_transaction_count <= forwarded_transaction_count + 1;
bit_counter <= 0;
end
end
end
end
end
/* Èíäåêñ áèòà. */
//reg[5:0] bit_count;
/* Áóôåð â êîòîðûé ìû ñêëàäûâàåì áèòû ïåðåä ñîõðàíåíèåì èõ â ïàìÿòü. */
reg[15:0] internal_transaction_buffer;
/* always ïî êëîêó AXI Quad SPI */
always @ (negedge reset or negedge internal_sck)
begin
if(!reset)
begin
for(counter = 0; counter < TRANSACTION_DEPTH; counter = counter + 1)
begin
slaves[counter] = 3;
transactions[counter] = 0;
end
buffered_transaction_count = 0;
internal_bit_count = 0;
end
else
begin
internal_bit_count = internal_bit_count + 1;
internal_transaction_buffer[internal_bit_count - 1] = internal_mosi;
if(internal_bit_count == 0) //DATA_WIDTH - 1)
begin
internal_transaction_buffer[15] = internal_mosi;
transactions[buffered_transaction_count] = internal_transaction_buffer;
slaves[buffered_transaction_count] = internal_ss;
if(buffered_transaction_count == TRANSACTION_DEPTH - 1)
buffered_transaction_count = 0;
else buffered_transaction_count = buffered_transaction_count + 1;
internal_bit_count = 0;
end
end
end
endmodule
|
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
// Date : Sun Sep 22 03:34:18 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ gcd_block_design_auto_pc_1_sim_netlist.v
// Design : gcd_block_design_auto_pc_1
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "32" *) (* C_AXI_ID_WIDTH = "12" *)
(* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_SUPPORTS_READ = "1" *) (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_SUPPORTS_WRITE = "1" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_FAMILY = "zynq" *)
(* C_IGNORE_ID = "0" *) (* C_M_AXI_PROTOCOL = "2" *) (* C_S_AXI_PROTOCOL = "1" *)
(* C_TRANSLATION_MODE = "2" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* P_AXI3 = "1" *)
(* P_AXI4 = "0" *) (* P_AXILITE = "2" *) (* P_AXILITE_SIZE = "3'b010" *)
(* P_CONVERSION = "2" *) (* P_DECERR = "2'b11" *) (* P_INCR = "2'b01" *)
(* P_PROTECTION = "1" *) (* P_SLVERR = "2'b10" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready);
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [3:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [3:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [11:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [11:0]m_axi_wid;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [11:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
output [11:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [11:0]m_axi_rid;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
wire \<const0> ;
wire \<const1> ;
wire aclk;
wire aresetn;
wire [31:0]m_axi_araddr;
wire [2:0]m_axi_arprot;
wire m_axi_arready;
wire m_axi_arvalid;
wire [31:0]m_axi_awaddr;
wire [2:0]m_axi_awprot;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire m_axi_wready;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [3:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [3:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const1> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[11] = \<const0> ;
assign m_axi_arid[10] = \<const0> ;
assign m_axi_arid[9] = \<const0> ;
assign m_axi_arid[8] = \<const0> ;
assign m_axi_arid[7] = \<const0> ;
assign m_axi_arid[6] = \<const0> ;
assign m_axi_arid[5] = \<const0> ;
assign m_axi_arid[4] = \<const0> ;
assign m_axi_arid[3] = \<const0> ;
assign m_axi_arid[2] = \<const0> ;
assign m_axi_arid[1] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const1> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const1> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[11] = \<const0> ;
assign m_axi_awid[10] = \<const0> ;
assign m_axi_awid[9] = \<const0> ;
assign m_axi_awid[8] = \<const0> ;
assign m_axi_awid[7] = \<const0> ;
assign m_axi_awid[6] = \<const0> ;
assign m_axi_awid[5] = \<const0> ;
assign m_axi_awid[4] = \<const0> ;
assign m_axi_awid[3] = \<const0> ;
assign m_axi_awid[2] = \<const0> ;
assign m_axi_awid[1] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const1> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_wdata[31:0] = s_axi_wdata;
assign m_axi_wid[11] = \<const0> ;
assign m_axi_wid[10] = \<const0> ;
assign m_axi_wid[9] = \<const0> ;
assign m_axi_wid[8] = \<const0> ;
assign m_axi_wid[7] = \<const0> ;
assign m_axi_wid[6] = \<const0> ;
assign m_axi_wid[5] = \<const0> ;
assign m_axi_wid[4] = \<const0> ;
assign m_axi_wid[3] = \<const0> ;
assign m_axi_wid[2] = \<const0> ;
assign m_axi_wid[1] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const1> ;
assign m_axi_wstrb[3:0] = s_axi_wstrb;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = s_axi_wvalid;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_wready = m_axi_wready;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s \gen_axilite.gen_b2s_conv.axilite_b2s
(.Q({m_axi_awprot,m_axi_awaddr[31:12]}),
.aclk(aclk),
.aresetn(aresetn),
.in({m_axi_rresp,m_axi_rdata}),
.m_axi_araddr(m_axi_araddr[11:0]),
.\m_axi_arprot[2] ({m_axi_arprot,m_axi_araddr[31:12]}),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr[11:0]),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize[1:0]),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize[1:0]),
.s_axi_awvalid(s_axi_awvalid),
.\s_axi_bid[11] ({s_axi_bid,s_axi_bresp}),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.\s_axi_rid[11] ({s_axi_rid,s_axi_rlast,s_axi_rresp,s_axi_rdata}),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s
(s_axi_rvalid,
s_axi_awready,
Q,
s_axi_arready,
\m_axi_arprot[2] ,
s_axi_bvalid,
\s_axi_bid[11] ,
\s_axi_rid[11] ,
m_axi_awvalid,
m_axi_bready,
m_axi_arvalid,
m_axi_rready,
m_axi_awaddr,
m_axi_araddr,
m_axi_awready,
m_axi_arready,
s_axi_rready,
aclk,
in,
s_axi_awid,
s_axi_awlen,
s_axi_awburst,
s_axi_awsize,
s_axi_awprot,
s_axi_awaddr,
m_axi_bresp,
s_axi_arid,
s_axi_arlen,
s_axi_arburst,
s_axi_arsize,
s_axi_arprot,
s_axi_araddr,
s_axi_awvalid,
m_axi_bvalid,
m_axi_rvalid,
s_axi_bready,
s_axi_arvalid,
aresetn);
output s_axi_rvalid;
output s_axi_awready;
output [22:0]Q;
output s_axi_arready;
output [22:0]\m_axi_arprot[2] ;
output s_axi_bvalid;
output [13:0]\s_axi_bid[11] ;
output [46:0]\s_axi_rid[11] ;
output m_axi_awvalid;
output m_axi_bready;
output m_axi_arvalid;
output m_axi_rready;
output [11:0]m_axi_awaddr;
output [11:0]m_axi_araddr;
input m_axi_awready;
input m_axi_arready;
input s_axi_rready;
input aclk;
input [33:0]in;
input [11:0]s_axi_awid;
input [3:0]s_axi_awlen;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awsize;
input [2:0]s_axi_awprot;
input [31:0]s_axi_awaddr;
input [1:0]m_axi_bresp;
input [11:0]s_axi_arid;
input [3:0]s_axi_arlen;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arsize;
input [2:0]s_axi_arprot;
input [31:0]s_axi_araddr;
input s_axi_awvalid;
input m_axi_bvalid;
input m_axi_rvalid;
input s_axi_bready;
input s_axi_arvalid;
input aresetn;
wire [22:0]Q;
wire \RD.ar_channel_0_n_0 ;
wire \RD.ar_channel_0_n_10 ;
wire \RD.ar_channel_0_n_11 ;
wire \RD.ar_channel_0_n_16 ;
wire \RD.ar_channel_0_n_3 ;
wire \RD.ar_channel_0_n_4 ;
wire \RD.ar_channel_0_n_46 ;
wire \RD.ar_channel_0_n_47 ;
wire \RD.ar_channel_0_n_48 ;
wire \RD.ar_channel_0_n_49 ;
wire \RD.ar_channel_0_n_5 ;
wire \RD.r_channel_0_n_0 ;
wire \RD.r_channel_0_n_1 ;
wire SI_REG_n_132;
wire SI_REG_n_133;
wire SI_REG_n_134;
wire SI_REG_n_135;
wire SI_REG_n_136;
wire SI_REG_n_137;
wire SI_REG_n_138;
wire SI_REG_n_139;
wire SI_REG_n_140;
wire SI_REG_n_141;
wire SI_REG_n_142;
wire SI_REG_n_143;
wire SI_REG_n_149;
wire SI_REG_n_153;
wire SI_REG_n_154;
wire SI_REG_n_155;
wire SI_REG_n_156;
wire SI_REG_n_157;
wire SI_REG_n_161;
wire SI_REG_n_165;
wire SI_REG_n_166;
wire SI_REG_n_167;
wire SI_REG_n_168;
wire SI_REG_n_169;
wire SI_REG_n_170;
wire SI_REG_n_171;
wire SI_REG_n_172;
wire SI_REG_n_173;
wire SI_REG_n_174;
wire SI_REG_n_175;
wire SI_REG_n_176;
wire SI_REG_n_177;
wire SI_REG_n_178;
wire SI_REG_n_179;
wire SI_REG_n_180;
wire SI_REG_n_181;
wire SI_REG_n_182;
wire SI_REG_n_26;
wire SI_REG_n_64;
wire SI_REG_n_8;
wire SI_REG_n_82;
wire \WR.aw_channel_0_n_0 ;
wire \WR.aw_channel_0_n_10 ;
wire \WR.aw_channel_0_n_15 ;
wire \WR.aw_channel_0_n_3 ;
wire \WR.aw_channel_0_n_4 ;
wire \WR.aw_channel_0_n_47 ;
wire \WR.aw_channel_0_n_48 ;
wire \WR.aw_channel_0_n_49 ;
wire \WR.aw_channel_0_n_50 ;
wire \WR.aw_channel_0_n_9 ;
wire \WR.b_channel_0_n_1 ;
wire \WR.b_channel_0_n_2 ;
wire aclk;
wire \ar.ar_pipe/m_valid_i0 ;
wire \ar.ar_pipe/p_1_in ;
wire \ar.ar_pipe/s_ready_i0 ;
wire [1:0]\ar_cmd_fsm_0/state ;
wire areset_d1;
wire areset_d1_i_1_n_0;
wire aresetn;
wire \aw.aw_pipe/p_1_in ;
wire [1:0]\aw_cmd_fsm_0/state ;
wire [11:0]axaddr_incr;
wire [11:0]b_awid;
wire [3:0]b_awlen;
wire b_push;
wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2 ;
wire [3:1]\cmd_translator_0/wrap_cmd_0/wrap_second_len ;
wire [3:1]\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/wrap_second_len_r ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3 ;
wire [33:0]in;
wire [11:0]m_axi_araddr;
wire [22:0]\m_axi_arprot[2] ;
wire m_axi_arready;
wire m_axi_arvalid;
wire [11:0]m_axi_awaddr;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire m_axi_rready;
wire m_axi_rvalid;
wire r_rlast;
wire [11:0]s_arid;
wire [11:0]s_arid_r;
wire [11:0]s_awid;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [3:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [1:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [3:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [1:0]s_axi_awsize;
wire s_axi_awvalid;
wire [13:0]\s_axi_bid[11] ;
wire s_axi_bready;
wire s_axi_bvalid;
wire [46:0]\s_axi_rid[11] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [11:0]si_rs_araddr;
wire [1:1]si_rs_arburst;
wire [3:0]si_rs_arlen;
wire [1:0]si_rs_arsize;
wire si_rs_arvalid;
wire [11:0]si_rs_awaddr;
wire [1:1]si_rs_awburst;
wire [3:0]si_rs_awlen;
wire [1:0]si_rs_awsize;
wire si_rs_awvalid;
wire [11:0]si_rs_bid;
wire si_rs_bready;
wire [1:0]si_rs_bresp;
wire si_rs_bvalid;
wire [31:0]si_rs_rdata;
wire [11:0]si_rs_rid;
wire si_rs_rlast;
wire si_rs_rready;
wire [1:0]si_rs_rresp;
wire [3:2]wrap_cnt;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_ar_channel \RD.ar_channel_0
(.D(\cmd_translator_0/wrap_cmd_0/wrap_second_len ),
.E(\ar.ar_pipe/p_1_in ),
.O({SI_REG_n_140,SI_REG_n_141,SI_REG_n_142,SI_REG_n_143}),
.Q({s_arid,si_rs_arlen,si_rs_arburst,SI_REG_n_82,si_rs_arsize,si_rs_araddr}),
.S({\RD.ar_channel_0_n_46 ,\RD.ar_channel_0_n_47 ,\RD.ar_channel_0_n_48 ,\RD.ar_channel_0_n_49 }),
.aclk(aclk),
.areset_d1(areset_d1),
.axaddr_offset({\cmd_translator_0/wrap_cmd_0/axaddr_offset [3],\cmd_translator_0/wrap_cmd_0/axaddr_offset [1:0]}),
.\axaddr_offset_r_reg[2] (\cmd_translator_0/wrap_cmd_0/axaddr_offset [2]),
.\axaddr_offset_r_reg[3] ({\cmd_translator_0/wrap_cmd_0/axaddr_offset_r [3],\cmd_translator_0/wrap_cmd_0/axaddr_offset_r [1:0]}),
.\axaddr_offset_r_reg[3]_0 (SI_REG_n_161),
.\axaddr_offset_r_reg[3]_1 (SI_REG_n_165),
.\cnt_read_reg[2]_rep__0 (\RD.r_channel_0_n_1 ),
.m_axi_araddr(m_axi_araddr),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.\m_payload_i_reg[0] (\RD.ar_channel_0_n_4 ),
.\m_payload_i_reg[0]_0 (\RD.ar_channel_0_n_5 ),
.\m_payload_i_reg[3] ({SI_REG_n_132,SI_REG_n_133,SI_REG_n_134,SI_REG_n_135}),
.\m_payload_i_reg[47] (SI_REG_n_64),
.\m_payload_i_reg[47]_0 (SI_REG_n_167),
.\m_payload_i_reg[5] (SI_REG_n_166),
.\m_payload_i_reg[6] ({SI_REG_n_176,SI_REG_n_177,SI_REG_n_178,SI_REG_n_179,SI_REG_n_180,SI_REG_n_181,SI_REG_n_182}),
.\m_payload_i_reg[7] ({SI_REG_n_136,SI_REG_n_137,SI_REG_n_138,SI_REG_n_139}),
.m_valid_i0(\ar.ar_pipe/m_valid_i0 ),
.\r_arid_r_reg[11] (s_arid_r),
.r_push_r_reg(\RD.ar_channel_0_n_3 ),
.r_rlast(r_rlast),
.s_axi_arvalid(s_axi_arvalid),
.s_ready_i0(\ar.ar_pipe/s_ready_i0 ),
.s_ready_i_reg(s_axi_arready),
.si_rs_arvalid(si_rs_arvalid),
.\state_reg[0]_rep (\ar_cmd_fsm_0/state ),
.\wrap_boundary_axaddr_r_reg[11] (\RD.ar_channel_0_n_0 ),
.\wrap_cnt_r_reg[3] (\RD.ar_channel_0_n_10 ),
.\wrap_cnt_r_reg[3]_0 (\RD.ar_channel_0_n_11 ),
.\wrap_cnt_r_reg[3]_1 (\RD.ar_channel_0_n_16 ),
.\wrap_second_len_r_reg[3] (\cmd_translator_0/wrap_cmd_0/wrap_second_len_r ),
.\wrap_second_len_r_reg[3]_0 ({SI_REG_n_156,SI_REG_n_157}));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_r_channel \RD.r_channel_0
(.D(s_arid_r),
.aclk(aclk),
.areset_d1(areset_d1),
.in(in),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.m_valid_i_reg(\RD.r_channel_0_n_0 ),
.out({si_rs_rresp,si_rs_rdata}),
.r_rlast(r_rlast),
.s_ready_i_reg(SI_REG_n_168),
.si_rs_rready(si_rs_rready),
.\skid_buffer_reg[46] ({si_rs_rid,si_rs_rlast}),
.\state_reg[1]_rep (\RD.r_channel_0_n_1 ),
.\state_reg[1]_rep_0 (\RD.ar_channel_0_n_3 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axi_register_slice SI_REG
(.D(wrap_cnt),
.E(\aw.aw_pipe/p_1_in ),
.O({SI_REG_n_140,SI_REG_n_141,SI_REG_n_142,SI_REG_n_143}),
.Q({s_awid,si_rs_awlen,si_rs_awburst,SI_REG_n_26,si_rs_awsize,Q,si_rs_awaddr}),
.S({\WR.aw_channel_0_n_47 ,\WR.aw_channel_0_n_48 ,\WR.aw_channel_0_n_49 ,\WR.aw_channel_0_n_50 }),
.aclk(aclk),
.aresetn(aresetn),
.axaddr_incr(axaddr_incr),
.\axaddr_incr_reg[3] ({SI_REG_n_132,SI_REG_n_133,SI_REG_n_134,SI_REG_n_135}),
.\axaddr_incr_reg[7] ({SI_REG_n_136,SI_REG_n_137,SI_REG_n_138,SI_REG_n_139}),
.axaddr_offset({\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 [3],\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 [1:0]}),
.axaddr_offset_0({\cmd_translator_0/wrap_cmd_0/axaddr_offset [3],\cmd_translator_0/wrap_cmd_0/axaddr_offset [1:0]}),
.\axaddr_offset_r_reg[2] (SI_REG_n_154),
.\axaddr_offset_r_reg[2]_0 (SI_REG_n_166),
.\axaddr_offset_r_reg[2]_1 (\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 [2]),
.\axaddr_offset_r_reg[2]_2 (\WR.aw_channel_0_n_15 ),
.\axaddr_offset_r_reg[2]_3 (\cmd_translator_0/wrap_cmd_0/axaddr_offset [2]),
.\axaddr_offset_r_reg[2]_4 (\RD.ar_channel_0_n_16 ),
.\axaddr_offset_r_reg[3] ({\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2 [3],\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2 [1:0]}),
.\axaddr_offset_r_reg[3]_0 (\WR.aw_channel_0_n_10 ),
.\axaddr_offset_r_reg[3]_1 ({\cmd_translator_0/wrap_cmd_0/axaddr_offset_r [3],\cmd_translator_0/wrap_cmd_0/axaddr_offset_r [1:0]}),
.\axaddr_offset_r_reg[3]_2 (\RD.ar_channel_0_n_11 ),
.\axlen_cnt_reg[3] (SI_REG_n_8),
.\axlen_cnt_reg[3]_0 (SI_REG_n_64),
.b_push(b_push),
.\cnt_read_reg[2]_rep__0 (SI_REG_n_168),
.\cnt_read_reg[4] ({si_rs_rresp,si_rs_rdata}),
.\cnt_read_reg[4]_rep__0 (\RD.r_channel_0_n_0 ),
.\m_payload_i_reg[3] ({\RD.ar_channel_0_n_46 ,\RD.ar_channel_0_n_47 ,\RD.ar_channel_0_n_48 ,\RD.ar_channel_0_n_49 }),
.m_valid_i0(\ar.ar_pipe/m_valid_i0 ),
.m_valid_i_reg(\ar.ar_pipe/p_1_in ),
.next_pending_r_reg(SI_REG_n_155),
.next_pending_r_reg_0(SI_REG_n_167),
.out(si_rs_bid),
.r_push_r_reg({si_rs_rid,si_rs_rlast}),
.\s_arid_r_reg[11] ({s_arid,si_rs_arlen,si_rs_arburst,SI_REG_n_82,si_rs_arsize,\m_axi_arprot[2] ,si_rs_araddr}),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize),
.s_axi_awvalid(s_axi_awvalid),
.\s_axi_bid[11] (\s_axi_bid[11] ),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.\s_axi_rid[11] (\s_axi_rid[11] ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.\s_bresp_acc_reg[1] (si_rs_bresp),
.s_ready_i0(\ar.ar_pipe/s_ready_i0 ),
.si_rs_arvalid(si_rs_arvalid),
.si_rs_awvalid(si_rs_awvalid),
.si_rs_bready(si_rs_bready),
.si_rs_bvalid(si_rs_bvalid),
.si_rs_rready(si_rs_rready),
.\state_reg[0]_rep (\WR.aw_channel_0_n_4 ),
.\state_reg[0]_rep_0 (\RD.ar_channel_0_n_5 ),
.\state_reg[1] (\aw_cmd_fsm_0/state ),
.\state_reg[1]_0 (\ar_cmd_fsm_0/state ),
.\state_reg[1]_rep (\WR.aw_channel_0_n_0 ),
.\state_reg[1]_rep_0 (\WR.aw_channel_0_n_3 ),
.\state_reg[1]_rep_1 (\RD.ar_channel_0_n_0 ),
.\state_reg[1]_rep_2 (\RD.ar_channel_0_n_4 ),
.\wrap_boundary_axaddr_r_reg[6] ({SI_REG_n_169,SI_REG_n_170,SI_REG_n_171,SI_REG_n_172,SI_REG_n_173,SI_REG_n_174,SI_REG_n_175}),
.\wrap_boundary_axaddr_r_reg[6]_0 ({SI_REG_n_176,SI_REG_n_177,SI_REG_n_178,SI_REG_n_179,SI_REG_n_180,SI_REG_n_181,SI_REG_n_182}),
.\wrap_cnt_r_reg[2] (SI_REG_n_149),
.\wrap_cnt_r_reg[2]_0 (SI_REG_n_161),
.\wrap_cnt_r_reg[3] (SI_REG_n_153),
.\wrap_cnt_r_reg[3]_0 ({SI_REG_n_156,SI_REG_n_157}),
.\wrap_cnt_r_reg[3]_1 (SI_REG_n_165),
.\wrap_second_len_r_reg[1] (\WR.aw_channel_0_n_9 ),
.\wrap_second_len_r_reg[1]_0 (\RD.ar_channel_0_n_10 ),
.\wrap_second_len_r_reg[3] (\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 ),
.\wrap_second_len_r_reg[3]_0 (\cmd_translator_0/wrap_cmd_0/wrap_second_len ),
.\wrap_second_len_r_reg[3]_1 (\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3 ),
.\wrap_second_len_r_reg[3]_2 (\cmd_translator_0/wrap_cmd_0/wrap_second_len_r ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_aw_channel \WR.aw_channel_0
(.D(wrap_cnt),
.E(\aw.aw_pipe/p_1_in ),
.Q({s_awid,si_rs_awlen,si_rs_awburst,SI_REG_n_26,si_rs_awsize,si_rs_awaddr}),
.S({\WR.aw_channel_0_n_47 ,\WR.aw_channel_0_n_48 ,\WR.aw_channel_0_n_49 ,\WR.aw_channel_0_n_50 }),
.aclk(aclk),
.areset_d1(areset_d1),
.axaddr_incr(axaddr_incr),
.axaddr_offset({\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 [3],\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 [1:0]}),
.\axaddr_offset_r_reg[2] (\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 [2]),
.\axaddr_offset_r_reg[3] ({\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2 [3],\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2 [1:0]}),
.\axaddr_offset_r_reg[3]_0 (SI_REG_n_149),
.\axaddr_offset_r_reg[3]_1 (SI_REG_n_153),
.\axlen_cnt_reg[7] (\WR.aw_channel_0_n_3 ),
.\axlen_cnt_reg[7]_0 (\WR.aw_channel_0_n_4 ),
.b_push(b_push),
.\cnt_read_reg[0]_rep__0 (\WR.b_channel_0_n_1 ),
.\cnt_read_reg[1]_rep__0 (\WR.b_channel_0_n_2 ),
.in({b_awid,b_awlen}),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.\m_payload_i_reg[47] (SI_REG_n_8),
.\m_payload_i_reg[47]_0 (SI_REG_n_155),
.\m_payload_i_reg[5] (SI_REG_n_154),
.\m_payload_i_reg[6] ({SI_REG_n_169,SI_REG_n_170,SI_REG_n_171,SI_REG_n_172,SI_REG_n_173,SI_REG_n_174,SI_REG_n_175}),
.si_rs_awvalid(si_rs_awvalid),
.\state_reg[0]_rep (\aw_cmd_fsm_0/state ),
.\wrap_boundary_axaddr_r_reg[11] (\WR.aw_channel_0_n_0 ),
.\wrap_cnt_r_reg[3] (\WR.aw_channel_0_n_9 ),
.\wrap_cnt_r_reg[3]_0 (\WR.aw_channel_0_n_10 ),
.\wrap_cnt_r_reg[3]_1 (\WR.aw_channel_0_n_15 ),
.\wrap_second_len_r_reg[3] (\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3 ),
.\wrap_second_len_r_reg[3]_0 (\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_b_channel \WR.b_channel_0
(.aclk(aclk),
.areset_d1(areset_d1),
.b_push(b_push),
.\cnt_read_reg[0]_rep__0 (\WR.b_channel_0_n_1 ),
.\cnt_read_reg[1]_rep__0 (\WR.b_channel_0_n_2 ),
.in({b_awid,b_awlen}),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.out(si_rs_bid),
.si_rs_bready(si_rs_bready),
.si_rs_bvalid(si_rs_bvalid),
.\skid_buffer_reg[1] (si_rs_bresp));
LUT1 #(
.INIT(2'h1))
areset_d1_i_1
(.I0(aresetn),
.O(areset_d1_i_1_n_0));
FDRE #(
.INIT(1'b0))
areset_d1_reg
(.C(aclk),
.CE(1'b1),
.D(areset_d1_i_1_n_0),
.Q(areset_d1),
.R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_ar_channel
(\wrap_boundary_axaddr_r_reg[11] ,
\state_reg[0]_rep ,
r_push_r_reg,
\m_payload_i_reg[0] ,
\m_payload_i_reg[0]_0 ,
\wrap_second_len_r_reg[3] ,
\wrap_cnt_r_reg[3] ,
\wrap_cnt_r_reg[3]_0 ,
\axaddr_offset_r_reg[3] ,
\axaddr_offset_r_reg[2] ,
\wrap_cnt_r_reg[3]_1 ,
m_axi_arvalid,
m_valid_i0,
s_ready_i0,
E,
r_rlast,
m_axi_araddr,
\r_arid_r_reg[11] ,
S,
aclk,
Q,
m_axi_arready,
si_rs_arvalid,
\cnt_read_reg[2]_rep__0 ,
\m_payload_i_reg[47] ,
\axaddr_offset_r_reg[3]_0 ,
axaddr_offset,
\axaddr_offset_r_reg[3]_1 ,
D,
\m_payload_i_reg[47]_0 ,
areset_d1,
\m_payload_i_reg[5] ,
s_axi_arvalid,
s_ready_i_reg,
O,
\m_payload_i_reg[7] ,
\m_payload_i_reg[3] ,
\wrap_second_len_r_reg[3]_0 ,
\m_payload_i_reg[6] );
output \wrap_boundary_axaddr_r_reg[11] ;
output [1:0]\state_reg[0]_rep ;
output r_push_r_reg;
output \m_payload_i_reg[0] ;
output \m_payload_i_reg[0]_0 ;
output [3:0]\wrap_second_len_r_reg[3] ;
output \wrap_cnt_r_reg[3] ;
output \wrap_cnt_r_reg[3]_0 ;
output [2:0]\axaddr_offset_r_reg[3] ;
output [0:0]\axaddr_offset_r_reg[2] ;
output \wrap_cnt_r_reg[3]_1 ;
output m_axi_arvalid;
output m_valid_i0;
output s_ready_i0;
output [0:0]E;
output r_rlast;
output [11:0]m_axi_araddr;
output [11:0]\r_arid_r_reg[11] ;
output [3:0]S;
input aclk;
input [31:0]Q;
input m_axi_arready;
input si_rs_arvalid;
input \cnt_read_reg[2]_rep__0 ;
input \m_payload_i_reg[47] ;
input \axaddr_offset_r_reg[3]_0 ;
input [2:0]axaddr_offset;
input \axaddr_offset_r_reg[3]_1 ;
input [2:0]D;
input \m_payload_i_reg[47]_0 ;
input areset_d1;
input \m_payload_i_reg[5] ;
input s_axi_arvalid;
input s_ready_i_reg;
input [3:0]O;
input [3:0]\m_payload_i_reg[7] ;
input [3:0]\m_payload_i_reg[3] ;
input [1:0]\wrap_second_len_r_reg[3]_0 ;
input [6:0]\m_payload_i_reg[6] ;
wire [2:0]D;
wire [0:0]E;
wire [3:0]O;
wire [31:0]Q;
wire [3:0]S;
wire aclk;
wire ar_cmd_fsm_0_n_0;
wire ar_cmd_fsm_0_n_10;
wire ar_cmd_fsm_0_n_16;
wire ar_cmd_fsm_0_n_6;
wire ar_cmd_fsm_0_n_8;
wire ar_cmd_fsm_0_n_9;
wire areset_d1;
wire [2:0]axaddr_offset;
wire [0:0]\axaddr_offset_r_reg[2] ;
wire [2:0]\axaddr_offset_r_reg[3] ;
wire \axaddr_offset_r_reg[3]_0 ;
wire \axaddr_offset_r_reg[3]_1 ;
wire cmd_translator_0_n_0;
wire cmd_translator_0_n_10;
wire cmd_translator_0_n_2;
wire cmd_translator_0_n_3;
wire \cnt_read_reg[2]_rep__0 ;
wire \incr_cmd_0/sel_first ;
wire [11:0]m_axi_araddr;
wire m_axi_arready;
wire m_axi_arvalid;
wire \m_payload_i_reg[0] ;
wire \m_payload_i_reg[0]_0 ;
wire [3:0]\m_payload_i_reg[3] ;
wire \m_payload_i_reg[47] ;
wire \m_payload_i_reg[47]_0 ;
wire \m_payload_i_reg[5] ;
wire [6:0]\m_payload_i_reg[6] ;
wire [3:0]\m_payload_i_reg[7] ;
wire m_valid_i0;
wire [11:0]\r_arid_r_reg[11] ;
wire r_push_r_reg;
wire r_rlast;
wire s_axi_arvalid;
wire s_ready_i0;
wire s_ready_i_reg;
wire sel_first_i;
wire si_rs_arvalid;
wire [1:0]\state_reg[0]_rep ;
wire \wrap_boundary_axaddr_r_reg[11] ;
wire [2:2]\wrap_cmd_0/axaddr_offset_r ;
wire [0:0]\wrap_cmd_0/wrap_second_len ;
wire \wrap_cnt_r_reg[3] ;
wire \wrap_cnt_r_reg[3]_0 ;
wire \wrap_cnt_r_reg[3]_1 ;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [1:0]\wrap_second_len_r_reg[3]_0 ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm ar_cmd_fsm_0
(.D(ar_cmd_fsm_0_n_6),
.E(ar_cmd_fsm_0_n_8),
.Q(\state_reg[0]_rep ),
.aclk(aclk),
.areset_d1(areset_d1),
.\axaddr_incr_reg[0] (ar_cmd_fsm_0_n_16),
.axaddr_offset(axaddr_offset[0]),
.\axaddr_offset_r_reg[2] (\axaddr_offset_r_reg[2] ),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3]_0 ),
.\axaddr_offset_r_reg[3]_0 ({\axaddr_offset_r_reg[3] [2],\wrap_cmd_0/axaddr_offset_r }),
.\axlen_cnt_reg[7] (ar_cmd_fsm_0_n_0),
.\axlen_cnt_reg[7]_0 (cmd_translator_0_n_3),
.\cnt_read_reg[2]_rep__0 (\cnt_read_reg[2]_rep__0 ),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.\m_payload_i_reg[0] (\m_payload_i_reg[0] ),
.\m_payload_i_reg[0]_0 (\m_payload_i_reg[0]_0 ),
.\m_payload_i_reg[0]_1 (E),
.\m_payload_i_reg[46] (Q[18]),
.\m_payload_i_reg[5] (\m_payload_i_reg[5] ),
.m_valid_i0(m_valid_i0),
.r_push_r_reg(r_push_r_reg),
.s_axburst_eq1_reg(cmd_translator_0_n_10),
.s_axi_arvalid(s_axi_arvalid),
.s_ready_i0(s_ready_i0),
.s_ready_i_reg(s_ready_i_reg),
.sel_first(\incr_cmd_0/sel_first ),
.sel_first_i(sel_first_i),
.sel_first_reg(ar_cmd_fsm_0_n_9),
.sel_first_reg_0(ar_cmd_fsm_0_n_10),
.sel_first_reg_1(cmd_translator_0_n_2),
.sel_first_reg_2(cmd_translator_0_n_0),
.si_rs_arvalid(si_rs_arvalid),
.\wrap_boundary_axaddr_r_reg[11] (\wrap_boundary_axaddr_r_reg[11] ),
.\wrap_cnt_r_reg[3] (\wrap_cnt_r_reg[3]_0 ),
.\wrap_cnt_r_reg[3]_0 (\wrap_cnt_r_reg[3]_1 ),
.\wrap_second_len_r_reg[0] (\wrap_cmd_0/wrap_second_len ),
.\wrap_second_len_r_reg[0]_0 (\wrap_second_len_r_reg[3] [0]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1 cmd_translator_0
(.D({axaddr_offset[2],\axaddr_offset_r_reg[2] ,axaddr_offset[1:0]}),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.O(O),
.Q(Q[19:0]),
.S(S),
.aclk(aclk),
.\axaddr_offset_r_reg[3] ({\axaddr_offset_r_reg[3] [2],\wrap_cmd_0/axaddr_offset_r ,\axaddr_offset_r_reg[3] [1:0]}),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3]_1 ),
.\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3]_0 ),
.\axlen_cnt_reg[0] (cmd_translator_0_n_3),
.m_axi_araddr(m_axi_araddr),
.m_axi_arready(m_axi_arready),
.\m_payload_i_reg[3] (\m_payload_i_reg[3] ),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[47]_0 (\m_payload_i_reg[47]_0 ),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.\m_payload_i_reg[7] (\m_payload_i_reg[7] ),
.m_valid_i_reg(ar_cmd_fsm_0_n_8),
.r_rlast(r_rlast),
.sel_first(\incr_cmd_0/sel_first ),
.sel_first_i(sel_first_i),
.sel_first_reg_0(cmd_translator_0_n_0),
.sel_first_reg_1(cmd_translator_0_n_2),
.sel_first_reg_2(ar_cmd_fsm_0_n_10),
.sel_first_reg_3(ar_cmd_fsm_0_n_9),
.sel_first_reg_4(ar_cmd_fsm_0_n_16),
.si_rs_arvalid(si_rs_arvalid),
.\state_reg[0]_rep (cmd_translator_0_n_10),
.\state_reg[0]_rep_0 (\m_payload_i_reg[0]_0 ),
.\state_reg[1] (\state_reg[0]_rep ),
.\state_reg[1]_0 (ar_cmd_fsm_0_n_0),
.\state_reg[1]_rep (r_push_r_reg),
.\wrap_cnt_r_reg[3] (\wrap_cnt_r_reg[3] ),
.\wrap_second_len_r_reg[3] (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_0 ({D,\wrap_cmd_0/wrap_second_len }),
.\wrap_second_len_r_reg[3]_1 ({\wrap_second_len_r_reg[3]_0 ,ar_cmd_fsm_0_n_6}));
FDRE \s_arid_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(Q[20]),
.Q(\r_arid_r_reg[11] [0]),
.R(1'b0));
FDRE \s_arid_r_reg[10]
(.C(aclk),
.CE(1'b1),
.D(Q[30]),
.Q(\r_arid_r_reg[11] [10]),
.R(1'b0));
FDRE \s_arid_r_reg[11]
(.C(aclk),
.CE(1'b1),
.D(Q[31]),
.Q(\r_arid_r_reg[11] [11]),
.R(1'b0));
FDRE \s_arid_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(Q[21]),
.Q(\r_arid_r_reg[11] [1]),
.R(1'b0));
FDRE \s_arid_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(Q[22]),
.Q(\r_arid_r_reg[11] [2]),
.R(1'b0));
FDRE \s_arid_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(Q[23]),
.Q(\r_arid_r_reg[11] [3]),
.R(1'b0));
FDRE \s_arid_r_reg[4]
(.C(aclk),
.CE(1'b1),
.D(Q[24]),
.Q(\r_arid_r_reg[11] [4]),
.R(1'b0));
FDRE \s_arid_r_reg[5]
(.C(aclk),
.CE(1'b1),
.D(Q[25]),
.Q(\r_arid_r_reg[11] [5]),
.R(1'b0));
FDRE \s_arid_r_reg[6]
(.C(aclk),
.CE(1'b1),
.D(Q[26]),
.Q(\r_arid_r_reg[11] [6]),
.R(1'b0));
FDRE \s_arid_r_reg[7]
(.C(aclk),
.CE(1'b1),
.D(Q[27]),
.Q(\r_arid_r_reg[11] [7]),
.R(1'b0));
FDRE \s_arid_r_reg[8]
(.C(aclk),
.CE(1'b1),
.D(Q[28]),
.Q(\r_arid_r_reg[11] [8]),
.R(1'b0));
FDRE \s_arid_r_reg[9]
(.C(aclk),
.CE(1'b1),
.D(Q[29]),
.Q(\r_arid_r_reg[11] [9]),
.R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_aw_channel
(\wrap_boundary_axaddr_r_reg[11] ,
\state_reg[0]_rep ,
\axlen_cnt_reg[7] ,
\axlen_cnt_reg[7]_0 ,
\wrap_second_len_r_reg[3] ,
\wrap_cnt_r_reg[3] ,
\wrap_cnt_r_reg[3]_0 ,
\axaddr_offset_r_reg[3] ,
\axaddr_offset_r_reg[2] ,
\wrap_cnt_r_reg[3]_1 ,
E,
b_push,
m_axi_awvalid,
m_axi_awaddr,
in,
S,
aclk,
Q,
si_rs_awvalid,
\cnt_read_reg[1]_rep__0 ,
\cnt_read_reg[0]_rep__0 ,
m_axi_awready,
D,
\axaddr_offset_r_reg[3]_0 ,
axaddr_offset,
\axaddr_offset_r_reg[3]_1 ,
\wrap_second_len_r_reg[3]_0 ,
\m_payload_i_reg[47] ,
\m_payload_i_reg[47]_0 ,
areset_d1,
\m_payload_i_reg[5] ,
axaddr_incr,
\m_payload_i_reg[6] );
output \wrap_boundary_axaddr_r_reg[11] ;
output [1:0]\state_reg[0]_rep ;
output \axlen_cnt_reg[7] ;
output \axlen_cnt_reg[7]_0 ;
output [3:0]\wrap_second_len_r_reg[3] ;
output \wrap_cnt_r_reg[3] ;
output \wrap_cnt_r_reg[3]_0 ;
output [2:0]\axaddr_offset_r_reg[3] ;
output [0:0]\axaddr_offset_r_reg[2] ;
output \wrap_cnt_r_reg[3]_1 ;
output [0:0]E;
output b_push;
output m_axi_awvalid;
output [11:0]m_axi_awaddr;
output [15:0]in;
output [3:0]S;
input aclk;
input [31:0]Q;
input si_rs_awvalid;
input \cnt_read_reg[1]_rep__0 ;
input \cnt_read_reg[0]_rep__0 ;
input m_axi_awready;
input [1:0]D;
input \axaddr_offset_r_reg[3]_0 ;
input [2:0]axaddr_offset;
input \axaddr_offset_r_reg[3]_1 ;
input [2:0]\wrap_second_len_r_reg[3]_0 ;
input \m_payload_i_reg[47] ;
input \m_payload_i_reg[47]_0 ;
input areset_d1;
input \m_payload_i_reg[5] ;
input [11:0]axaddr_incr;
input [6:0]\m_payload_i_reg[6] ;
wire [1:0]D;
wire [0:0]E;
wire [31:0]Q;
wire [3:0]S;
wire aclk;
wire areset_d1;
wire aw_cmd_fsm_0_n_12;
wire aw_cmd_fsm_0_n_14;
wire aw_cmd_fsm_0_n_15;
wire aw_cmd_fsm_0_n_16;
wire aw_cmd_fsm_0_n_2;
wire aw_cmd_fsm_0_n_8;
wire aw_cmd_fsm_0_n_9;
wire [11:0]axaddr_incr;
wire [2:0]axaddr_offset;
wire [0:0]\axaddr_offset_r_reg[2] ;
wire [2:0]\axaddr_offset_r_reg[3] ;
wire \axaddr_offset_r_reg[3]_0 ;
wire \axaddr_offset_r_reg[3]_1 ;
wire \axlen_cnt_reg[7] ;
wire \axlen_cnt_reg[7]_0 ;
wire b_push;
wire cmd_translator_0_n_0;
wire cmd_translator_0_n_12;
wire cmd_translator_0_n_2;
wire cmd_translator_0_n_5;
wire cmd_translator_0_n_6;
wire \cnt_read_reg[0]_rep__0 ;
wire \cnt_read_reg[1]_rep__0 ;
wire [15:0]in;
wire \incr_cmd_0/sel_first ;
wire incr_next_pending;
wire [11:0]m_axi_awaddr;
wire m_axi_awready;
wire m_axi_awvalid;
wire \m_payload_i_reg[47] ;
wire \m_payload_i_reg[47]_0 ;
wire \m_payload_i_reg[5] ;
wire [6:0]\m_payload_i_reg[6] ;
wire next;
wire sel_first;
wire sel_first_i;
wire si_rs_awvalid;
wire [1:0]\state_reg[0]_rep ;
wire \wrap_boundary_axaddr_r_reg[11] ;
wire [2:2]\wrap_cmd_0/axaddr_offset_r ;
wire [0:0]\wrap_cmd_0/wrap_second_len ;
wire [0:0]wrap_cnt;
wire \wrap_cnt_r_reg[3] ;
wire \wrap_cnt_r_reg[3]_0 ;
wire \wrap_cnt_r_reg[3]_1 ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [2:0]\wrap_second_len_r_reg[3]_0 ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm aw_cmd_fsm_0
(.D(wrap_cnt),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.Q(\state_reg[0]_rep ),
.aclk(aclk),
.areset_d1(areset_d1),
.axaddr_offset(axaddr_offset[0]),
.\axaddr_offset_r_reg[2] (\axaddr_offset_r_reg[2] ),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3]_0 ),
.\axaddr_offset_r_reg[3]_0 ({\axaddr_offset_r_reg[3] [2],\wrap_cmd_0/axaddr_offset_r }),
.\axaddr_wrap_reg[11] (aw_cmd_fsm_0_n_14),
.\axlen_cnt_reg[0] (aw_cmd_fsm_0_n_8),
.\axlen_cnt_reg[0]_0 (cmd_translator_0_n_5),
.\axlen_cnt_reg[7] (\axlen_cnt_reg[7] ),
.\axlen_cnt_reg[7]_0 (\axlen_cnt_reg[7]_0 ),
.\axlen_cnt_reg[7]_1 (aw_cmd_fsm_0_n_2),
.\axlen_cnt_reg[7]_2 (cmd_translator_0_n_6),
.b_push(b_push),
.\cnt_read_reg[0]_rep__0 (\cnt_read_reg[0]_rep__0 ),
.\cnt_read_reg[1]_rep__0 (\cnt_read_reg[1]_rep__0 ),
.incr_next_pending(incr_next_pending),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.\m_payload_i_reg[0] (E),
.\m_payload_i_reg[46] ({Q[18],Q[16:15]}),
.\m_payload_i_reg[47] (\m_payload_i_reg[47]_0 ),
.\m_payload_i_reg[5] (\m_payload_i_reg[5] ),
.next(next),
.next_pending_r_reg(cmd_translator_0_n_0),
.s_axburst_eq0_reg(aw_cmd_fsm_0_n_9),
.s_axburst_eq1_reg(aw_cmd_fsm_0_n_12),
.s_axburst_eq1_reg_0(cmd_translator_0_n_12),
.sel_first(sel_first),
.sel_first_0(\incr_cmd_0/sel_first ),
.sel_first_i(sel_first_i),
.sel_first_reg(aw_cmd_fsm_0_n_15),
.sel_first_reg_0(aw_cmd_fsm_0_n_16),
.sel_first_reg_1(cmd_translator_0_n_2),
.si_rs_awvalid(si_rs_awvalid),
.\wrap_cnt_r_reg[3] (\wrap_cnt_r_reg[3]_0 ),
.\wrap_cnt_r_reg[3]_0 (\wrap_cnt_r_reg[3]_1 ),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[0] (\wrap_cmd_0/wrap_second_len ),
.\wrap_second_len_r_reg[0]_0 (\wrap_second_len_r_reg[3] [0]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_cmd_translator cmd_translator_0
(.D({axaddr_offset[2],\axaddr_offset_r_reg[2] ,axaddr_offset[1:0]}),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.Q(cmd_translator_0_n_5),
.S(S),
.aclk(aclk),
.axaddr_incr(axaddr_incr),
.\axaddr_offset_r_reg[3] ({\axaddr_offset_r_reg[3] [2],\wrap_cmd_0/axaddr_offset_r ,\axaddr_offset_r_reg[3] [1:0]}),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3]_1 ),
.\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3]_0 ),
.\axlen_cnt_reg[2] (cmd_translator_0_n_6),
.incr_next_pending(incr_next_pending),
.m_axi_awaddr(m_axi_awaddr),
.\m_payload_i_reg[39] (aw_cmd_fsm_0_n_9),
.\m_payload_i_reg[39]_0 (aw_cmd_fsm_0_n_12),
.\m_payload_i_reg[47] (Q[19:0]),
.\m_payload_i_reg[47]_0 (\m_payload_i_reg[47] ),
.\m_payload_i_reg[47]_1 (\m_payload_i_reg[47]_0 ),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.next(next),
.next_pending_r_reg(cmd_translator_0_n_0),
.sel_first(sel_first),
.sel_first_0(\incr_cmd_0/sel_first ),
.sel_first_i(sel_first_i),
.sel_first_reg_0(cmd_translator_0_n_2),
.sel_first_reg_1(aw_cmd_fsm_0_n_16),
.sel_first_reg_2(aw_cmd_fsm_0_n_15),
.si_rs_awvalid(si_rs_awvalid),
.\state_reg[0] (aw_cmd_fsm_0_n_14),
.\state_reg[0]_rep (aw_cmd_fsm_0_n_2),
.\state_reg[1] (\state_reg[0]_rep ),
.\state_reg[1]_0 (aw_cmd_fsm_0_n_8),
.\state_reg[1]_rep (cmd_translator_0_n_12),
.\wrap_cnt_r_reg[3] (\wrap_cnt_r_reg[3] ),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3] (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_0 ({D,wrap_cnt}),
.\wrap_second_len_r_reg[3]_1 ({\wrap_second_len_r_reg[3]_0 ,\wrap_cmd_0/wrap_second_len }));
FDRE \s_awid_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(Q[20]),
.Q(in[4]),
.R(1'b0));
FDRE \s_awid_r_reg[10]
(.C(aclk),
.CE(1'b1),
.D(Q[30]),
.Q(in[14]),
.R(1'b0));
FDRE \s_awid_r_reg[11]
(.C(aclk),
.CE(1'b1),
.D(Q[31]),
.Q(in[15]),
.R(1'b0));
FDRE \s_awid_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(Q[21]),
.Q(in[5]),
.R(1'b0));
FDRE \s_awid_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(Q[22]),
.Q(in[6]),
.R(1'b0));
FDRE \s_awid_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(Q[23]),
.Q(in[7]),
.R(1'b0));
FDRE \s_awid_r_reg[4]
(.C(aclk),
.CE(1'b1),
.D(Q[24]),
.Q(in[8]),
.R(1'b0));
FDRE \s_awid_r_reg[5]
(.C(aclk),
.CE(1'b1),
.D(Q[25]),
.Q(in[9]),
.R(1'b0));
FDRE \s_awid_r_reg[6]
(.C(aclk),
.CE(1'b1),
.D(Q[26]),
.Q(in[10]),
.R(1'b0));
FDRE \s_awid_r_reg[7]
(.C(aclk),
.CE(1'b1),
.D(Q[27]),
.Q(in[11]),
.R(1'b0));
FDRE \s_awid_r_reg[8]
(.C(aclk),
.CE(1'b1),
.D(Q[28]),
.Q(in[12]),
.R(1'b0));
FDRE \s_awid_r_reg[9]
(.C(aclk),
.CE(1'b1),
.D(Q[29]),
.Q(in[13]),
.R(1'b0));
FDRE \s_awlen_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(Q[16]),
.Q(in[0]),
.R(1'b0));
FDRE \s_awlen_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(Q[17]),
.Q(in[1]),
.R(1'b0));
FDRE \s_awlen_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(Q[18]),
.Q(in[2]),
.R(1'b0));
FDRE \s_awlen_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(Q[19]),
.Q(in[3]),
.R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_b_channel
(si_rs_bvalid,
\cnt_read_reg[0]_rep__0 ,
\cnt_read_reg[1]_rep__0 ,
m_axi_bready,
out,
\skid_buffer_reg[1] ,
areset_d1,
aclk,
b_push,
si_rs_bready,
m_axi_bvalid,
in,
m_axi_bresp);
output si_rs_bvalid;
output \cnt_read_reg[0]_rep__0 ;
output \cnt_read_reg[1]_rep__0 ;
output m_axi_bready;
output [11:0]out;
output [1:0]\skid_buffer_reg[1] ;
input areset_d1;
input aclk;
input b_push;
input si_rs_bready;
input m_axi_bvalid;
input [15:0]in;
input [1:0]m_axi_bresp;
wire aclk;
wire areset_d1;
wire b_push;
wire bid_fifo_0_n_3;
wire bid_fifo_0_n_5;
wire \bresp_cnt[7]_i_6_n_0 ;
wire [7:0]bresp_cnt_reg__0;
wire bresp_push;
wire [1:0]cnt_read;
wire \cnt_read_reg[0]_rep__0 ;
wire \cnt_read_reg[1]_rep__0 ;
wire [15:0]in;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire mhandshake;
wire mhandshake_r;
wire [11:0]out;
wire [7:0]p_0_in;
wire s_bresp_acc0;
wire \s_bresp_acc[0]_i_1_n_0 ;
wire \s_bresp_acc[1]_i_1_n_0 ;
wire \s_bresp_acc_reg_n_0_[0] ;
wire \s_bresp_acc_reg_n_0_[1] ;
wire shandshake;
wire shandshake_r;
wire si_rs_bready;
wire si_rs_bvalid;
wire [1:0]\skid_buffer_reg[1] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo bid_fifo_0
(.D(bid_fifo_0_n_3),
.Q(cnt_read),
.SR(s_bresp_acc0),
.aclk(aclk),
.areset_d1(areset_d1),
.b_push(b_push),
.\bresp_cnt_reg[7] (bresp_cnt_reg__0),
.bresp_push(bresp_push),
.bvalid_i_reg(bid_fifo_0_n_5),
.bvalid_i_reg_0(si_rs_bvalid),
.\cnt_read_reg[0]_rep__0_0 (\cnt_read_reg[0]_rep__0 ),
.\cnt_read_reg[1]_rep__0_0 (\cnt_read_reg[1]_rep__0 ),
.in(in),
.mhandshake_r(mhandshake_r),
.out(out),
.shandshake_r(shandshake_r),
.si_rs_bready(si_rs_bready));
LUT1 #(
.INIT(2'h1))
\bresp_cnt[0]_i_1
(.I0(bresp_cnt_reg__0[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair125" *)
LUT2 #(
.INIT(4'h6))
\bresp_cnt[1]_i_1
(.I0(bresp_cnt_reg__0[1]),
.I1(bresp_cnt_reg__0[0]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair125" *)
LUT3 #(
.INIT(8'h6A))
\bresp_cnt[2]_i_1
(.I0(bresp_cnt_reg__0[2]),
.I1(bresp_cnt_reg__0[0]),
.I2(bresp_cnt_reg__0[1]),
.O(p_0_in[2]));
(* SOFT_HLUTNM = "soft_lutpair123" *)
LUT4 #(
.INIT(16'h6AAA))
\bresp_cnt[3]_i_1
(.I0(bresp_cnt_reg__0[3]),
.I1(bresp_cnt_reg__0[1]),
.I2(bresp_cnt_reg__0[0]),
.I3(bresp_cnt_reg__0[2]),
.O(p_0_in[3]));
(* SOFT_HLUTNM = "soft_lutpair123" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\bresp_cnt[4]_i_1
(.I0(bresp_cnt_reg__0[4]),
.I1(bresp_cnt_reg__0[2]),
.I2(bresp_cnt_reg__0[0]),
.I3(bresp_cnt_reg__0[1]),
.I4(bresp_cnt_reg__0[3]),
.O(p_0_in[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\bresp_cnt[5]_i_1
(.I0(bresp_cnt_reg__0[5]),
.I1(bresp_cnt_reg__0[3]),
.I2(bresp_cnt_reg__0[1]),
.I3(bresp_cnt_reg__0[0]),
.I4(bresp_cnt_reg__0[2]),
.I5(bresp_cnt_reg__0[4]),
.O(p_0_in[5]));
(* SOFT_HLUTNM = "soft_lutpair124" *)
LUT2 #(
.INIT(4'h6))
\bresp_cnt[6]_i_1
(.I0(bresp_cnt_reg__0[6]),
.I1(\bresp_cnt[7]_i_6_n_0 ),
.O(p_0_in[6]));
(* SOFT_HLUTNM = "soft_lutpair124" *)
LUT3 #(
.INIT(8'h6A))
\bresp_cnt[7]_i_2
(.I0(bresp_cnt_reg__0[7]),
.I1(\bresp_cnt[7]_i_6_n_0 ),
.I2(bresp_cnt_reg__0[6]),
.O(p_0_in[7]));
LUT6 #(
.INIT(64'h8000000000000000))
\bresp_cnt[7]_i_6
(.I0(bresp_cnt_reg__0[5]),
.I1(bresp_cnt_reg__0[3]),
.I2(bresp_cnt_reg__0[1]),
.I3(bresp_cnt_reg__0[0]),
.I4(bresp_cnt_reg__0[2]),
.I5(bresp_cnt_reg__0[4]),
.O(\bresp_cnt[7]_i_6_n_0 ));
FDRE \bresp_cnt_reg[0]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[0]),
.Q(bresp_cnt_reg__0[0]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[1]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[1]),
.Q(bresp_cnt_reg__0[1]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[2]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[2]),
.Q(bresp_cnt_reg__0[2]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[3]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[3]),
.Q(bresp_cnt_reg__0[3]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[4]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[4]),
.Q(bresp_cnt_reg__0[4]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[5]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[5]),
.Q(bresp_cnt_reg__0[5]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[6]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[6]),
.Q(bresp_cnt_reg__0[6]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[7]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[7]),
.Q(bresp_cnt_reg__0[7]),
.R(s_bresp_acc0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0 bresp_fifo_0
(.D(bid_fifo_0_n_3),
.Q(cnt_read),
.aclk(aclk),
.areset_d1(areset_d1),
.in({\s_bresp_acc_reg_n_0_[1] ,\s_bresp_acc_reg_n_0_[0] }),
.m_axi_bready(m_axi_bready),
.m_axi_bvalid(m_axi_bvalid),
.mhandshake(mhandshake),
.mhandshake_r(mhandshake_r),
.sel(bresp_push),
.shandshake_r(shandshake_r),
.\skid_buffer_reg[1] (\skid_buffer_reg[1] ));
FDRE #(
.INIT(1'b0))
bvalid_i_reg
(.C(aclk),
.CE(1'b1),
.D(bid_fifo_0_n_5),
.Q(si_rs_bvalid),
.R(1'b0));
FDRE #(
.INIT(1'b0))
mhandshake_r_reg
(.C(aclk),
.CE(1'b1),
.D(mhandshake),
.Q(mhandshake_r),
.R(areset_d1));
LUT6 #(
.INIT(64'h00000000EACEAAAA))
\s_bresp_acc[0]_i_1
(.I0(\s_bresp_acc_reg_n_0_[0] ),
.I1(m_axi_bresp[0]),
.I2(m_axi_bresp[1]),
.I3(\s_bresp_acc_reg_n_0_[1] ),
.I4(mhandshake),
.I5(s_bresp_acc0),
.O(\s_bresp_acc[0]_i_1_n_0 ));
LUT4 #(
.INIT(16'h00EC))
\s_bresp_acc[1]_i_1
(.I0(m_axi_bresp[1]),
.I1(\s_bresp_acc_reg_n_0_[1] ),
.I2(mhandshake),
.I3(s_bresp_acc0),
.O(\s_bresp_acc[1]_i_1_n_0 ));
FDRE \s_bresp_acc_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\s_bresp_acc[0]_i_1_n_0 ),
.Q(\s_bresp_acc_reg_n_0_[0] ),
.R(1'b0));
FDRE \s_bresp_acc_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\s_bresp_acc[1]_i_1_n_0 ),
.Q(\s_bresp_acc_reg_n_0_[1] ),
.R(1'b0));
LUT2 #(
.INIT(4'h8))
shandshake_r_i_1
(.I0(si_rs_bvalid),
.I1(si_rs_bready),
.O(shandshake));
FDRE #(
.INIT(1'b0))
shandshake_r_reg
(.C(aclk),
.CE(1'b1),
.D(shandshake),
.Q(shandshake_r),
.R(areset_d1));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_cmd_translator
(next_pending_r_reg,
wrap_next_pending,
sel_first_reg_0,
sel_first_0,
sel_first,
Q,
\axlen_cnt_reg[2] ,
\wrap_cnt_r_reg[3] ,
\wrap_second_len_r_reg[3] ,
\state_reg[1]_rep ,
m_axi_awaddr,
\axaddr_offset_r_reg[3] ,
S,
incr_next_pending,
aclk,
sel_first_i,
\m_payload_i_reg[39] ,
\m_payload_i_reg[39]_0 ,
sel_first_reg_1,
sel_first_reg_2,
E,
\m_payload_i_reg[47] ,
\state_reg[1] ,
si_rs_awvalid,
\axaddr_offset_r_reg[3]_0 ,
D,
\m_payload_i_reg[47]_0 ,
\m_payload_i_reg[47]_1 ,
next,
axaddr_incr,
\wrap_second_len_r_reg[3]_0 ,
\axaddr_offset_r_reg[3]_1 ,
\state_reg[0] ,
\state_reg[1]_0 ,
\state_reg[0]_rep ,
\wrap_second_len_r_reg[3]_1 ,
\m_payload_i_reg[6] );
output next_pending_r_reg;
output wrap_next_pending;
output sel_first_reg_0;
output sel_first_0;
output sel_first;
output [0:0]Q;
output \axlen_cnt_reg[2] ;
output \wrap_cnt_r_reg[3] ;
output [3:0]\wrap_second_len_r_reg[3] ;
output \state_reg[1]_rep ;
output [11:0]m_axi_awaddr;
output [3:0]\axaddr_offset_r_reg[3] ;
output [3:0]S;
input incr_next_pending;
input aclk;
input sel_first_i;
input \m_payload_i_reg[39] ;
input \m_payload_i_reg[39]_0 ;
input sel_first_reg_1;
input sel_first_reg_2;
input [0:0]E;
input [19:0]\m_payload_i_reg[47] ;
input [1:0]\state_reg[1] ;
input si_rs_awvalid;
input \axaddr_offset_r_reg[3]_0 ;
input [3:0]D;
input \m_payload_i_reg[47]_0 ;
input \m_payload_i_reg[47]_1 ;
input next;
input [11:0]axaddr_incr;
input [2:0]\wrap_second_len_r_reg[3]_0 ;
input \axaddr_offset_r_reg[3]_1 ;
input [0:0]\state_reg[0] ;
input [0:0]\state_reg[1]_0 ;
input \state_reg[0]_rep ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [6:0]\m_payload_i_reg[6] ;
wire [3:0]D;
wire [0:0]E;
wire [0:0]Q;
wire [3:0]S;
wire aclk;
wire [11:0]axaddr_incr;
wire [3:0]\axaddr_offset_r_reg[3] ;
wire \axaddr_offset_r_reg[3]_0 ;
wire \axaddr_offset_r_reg[3]_1 ;
wire \axlen_cnt_reg[2] ;
wire incr_cmd_0_n_10;
wire incr_cmd_0_n_11;
wire incr_cmd_0_n_12;
wire incr_cmd_0_n_13;
wire incr_cmd_0_n_14;
wire incr_cmd_0_n_15;
wire incr_cmd_0_n_16;
wire incr_cmd_0_n_4;
wire incr_cmd_0_n_5;
wire incr_cmd_0_n_6;
wire incr_cmd_0_n_7;
wire incr_cmd_0_n_8;
wire incr_cmd_0_n_9;
wire incr_next_pending;
wire [11:0]m_axi_awaddr;
wire \m_payload_i_reg[39] ;
wire \m_payload_i_reg[39]_0 ;
wire [19:0]\m_payload_i_reg[47] ;
wire \m_payload_i_reg[47]_0 ;
wire \m_payload_i_reg[47]_1 ;
wire [6:0]\m_payload_i_reg[6] ;
wire next;
wire next_pending_r_reg;
wire s_axburst_eq0;
wire s_axburst_eq1;
wire sel_first;
wire sel_first_0;
wire sel_first_i;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire si_rs_awvalid;
wire [0:0]\state_reg[0] ;
wire \state_reg[0]_rep ;
wire [1:0]\state_reg[1] ;
wire [0:0]\state_reg[1]_0 ;
wire \state_reg[1]_rep ;
wire \wrap_cnt_r_reg[3] ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [2:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_incr_cmd incr_cmd_0
(.E(E),
.Q(Q),
.S(S),
.aclk(aclk),
.axaddr_incr(axaddr_incr),
.\axaddr_incr_reg[0]_0 (sel_first_0),
.\axaddr_incr_reg[11]_0 ({incr_cmd_0_n_4,incr_cmd_0_n_5,incr_cmd_0_n_6,incr_cmd_0_n_7,incr_cmd_0_n_8,incr_cmd_0_n_9,incr_cmd_0_n_10,incr_cmd_0_n_11,incr_cmd_0_n_12,incr_cmd_0_n_13,incr_cmd_0_n_14}),
.\axlen_cnt_reg[2]_0 (\axlen_cnt_reg[2] ),
.incr_next_pending(incr_next_pending),
.\m_axi_awaddr[11] (incr_cmd_0_n_15),
.\m_axi_awaddr[5] (incr_cmd_0_n_16),
.\m_payload_i_reg[46] ({\m_payload_i_reg[47] [18:17],\m_payload_i_reg[47] [14:12],\m_payload_i_reg[47] [5],\m_payload_i_reg[47] [3:0]}),
.\m_payload_i_reg[47] (\m_payload_i_reg[47]_0 ),
.next(next),
.next_pending_r_reg_0(next_pending_r_reg),
.sel_first_reg_0(sel_first_reg_1),
.\state_reg[0] (\state_reg[0] ),
.\state_reg[0]_rep (\state_reg[0]_rep ),
.\state_reg[1] (\state_reg[1]_0 ));
LUT3 #(
.INIT(8'hB8))
\memory_reg[3][0]_srl4_i_2
(.I0(s_axburst_eq1),
.I1(\m_payload_i_reg[47] [15]),
.I2(s_axburst_eq0),
.O(\state_reg[1]_rep ));
FDRE s_axburst_eq0_reg
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[39] ),
.Q(s_axburst_eq0),
.R(1'b0));
FDRE s_axburst_eq1_reg
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[39]_0 ),
.Q(s_axburst_eq1),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_i),
.Q(sel_first_reg_0),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wrap_cmd wrap_cmd_0
(.D(D),
.E(E),
.aclk(aclk),
.\axaddr_incr_reg[11] ({incr_cmd_0_n_4,incr_cmd_0_n_5,incr_cmd_0_n_6,incr_cmd_0_n_7,incr_cmd_0_n_8,incr_cmd_0_n_9,incr_cmd_0_n_10,incr_cmd_0_n_11,incr_cmd_0_n_12,incr_cmd_0_n_13,incr_cmd_0_n_14}),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3] ),
.\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3]_0 ),
.\axaddr_offset_r_reg[3]_2 (\axaddr_offset_r_reg[3]_1 ),
.m_axi_awaddr(m_axi_awaddr),
.\m_payload_i_reg[47] ({\m_payload_i_reg[47] [19:15],\m_payload_i_reg[47] [13:0]}),
.\m_payload_i_reg[47]_0 (\m_payload_i_reg[47]_1 ),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.next(next),
.sel_first_reg_0(sel_first),
.sel_first_reg_1(sel_first_reg_2),
.sel_first_reg_2(incr_cmd_0_n_15),
.sel_first_reg_3(incr_cmd_0_n_16),
.si_rs_awvalid(si_rs_awvalid),
.\state_reg[0] (\state_reg[0] ),
.\state_reg[1] (\state_reg[1] ),
.\wrap_cnt_r_reg[3]_0 (\wrap_cnt_r_reg[3] ),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_1 (\wrap_second_len_r_reg[3]_1 ),
.\wrap_second_len_r_reg[3]_2 (\wrap_second_len_r_reg[3]_0 ));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_17_b2s_cmd_translator" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_cmd_translator_1
(sel_first_reg_0,
sel_first,
sel_first_reg_1,
\axlen_cnt_reg[0] ,
\wrap_cnt_r_reg[3] ,
\wrap_second_len_r_reg[3] ,
r_rlast,
\state_reg[0]_rep ,
m_axi_araddr,
\axaddr_offset_r_reg[3] ,
S,
aclk,
sel_first_i,
sel_first_reg_2,
sel_first_reg_3,
E,
Q,
\state_reg[1] ,
si_rs_arvalid,
\m_payload_i_reg[47] ,
\axaddr_offset_r_reg[3]_0 ,
D,
\m_payload_i_reg[47]_0 ,
\state_reg[1]_rep ,
O,
\m_payload_i_reg[7] ,
\m_payload_i_reg[3] ,
\state_reg[0]_rep_0 ,
\axaddr_offset_r_reg[3]_1 ,
m_valid_i_reg,
\state_reg[1]_0 ,
\wrap_second_len_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_1 ,
\m_payload_i_reg[6] ,
sel_first_reg_4,
m_axi_arready);
output sel_first_reg_0;
output sel_first;
output sel_first_reg_1;
output \axlen_cnt_reg[0] ;
output \wrap_cnt_r_reg[3] ;
output [3:0]\wrap_second_len_r_reg[3] ;
output r_rlast;
output \state_reg[0]_rep ;
output [11:0]m_axi_araddr;
output [3:0]\axaddr_offset_r_reg[3] ;
output [3:0]S;
input aclk;
input sel_first_i;
input sel_first_reg_2;
input sel_first_reg_3;
input [0:0]E;
input [19:0]Q;
input [1:0]\state_reg[1] ;
input si_rs_arvalid;
input \m_payload_i_reg[47] ;
input \axaddr_offset_r_reg[3]_0 ;
input [3:0]D;
input \m_payload_i_reg[47]_0 ;
input \state_reg[1]_rep ;
input [3:0]O;
input [3:0]\m_payload_i_reg[7] ;
input [3:0]\m_payload_i_reg[3] ;
input \state_reg[0]_rep_0 ;
input \axaddr_offset_r_reg[3]_1 ;
input [0:0]m_valid_i_reg;
input \state_reg[1]_0 ;
input [3:0]\wrap_second_len_r_reg[3]_0 ;
input [2:0]\wrap_second_len_r_reg[3]_1 ;
input [6:0]\m_payload_i_reg[6] ;
input [0:0]sel_first_reg_4;
input m_axi_arready;
wire [3:0]D;
wire [0:0]E;
wire [3:0]O;
wire [19:0]Q;
wire [3:0]S;
wire aclk;
wire [3:0]\axaddr_offset_r_reg[3] ;
wire \axaddr_offset_r_reg[3]_0 ;
wire \axaddr_offset_r_reg[3]_1 ;
wire \axlen_cnt_reg[0] ;
wire incr_cmd_0_n_10;
wire incr_cmd_0_n_11;
wire incr_cmd_0_n_12;
wire incr_cmd_0_n_13;
wire incr_cmd_0_n_14;
wire incr_cmd_0_n_15;
wire incr_cmd_0_n_3;
wire incr_cmd_0_n_4;
wire incr_cmd_0_n_5;
wire incr_cmd_0_n_6;
wire incr_cmd_0_n_7;
wire incr_cmd_0_n_8;
wire incr_cmd_0_n_9;
wire incr_next_pending;
wire [11:0]m_axi_araddr;
wire m_axi_arready;
wire [3:0]\m_payload_i_reg[3] ;
wire \m_payload_i_reg[47] ;
wire \m_payload_i_reg[47]_0 ;
wire [6:0]\m_payload_i_reg[6] ;
wire [3:0]\m_payload_i_reg[7] ;
wire [0:0]m_valid_i_reg;
wire r_rlast;
wire s_axburst_eq0;
wire s_axburst_eq1;
wire sel_first;
wire sel_first_i;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire sel_first_reg_3;
wire [0:0]sel_first_reg_4;
wire si_rs_arvalid;
wire \state_reg[0]_rep ;
wire \state_reg[0]_rep_0 ;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_0 ;
wire \state_reg[1]_rep ;
wire wrap_cmd_0_n_6;
wire wrap_cmd_0_n_7;
wire \wrap_cnt_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [2:0]\wrap_second_len_r_reg[3]_1 ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2 incr_cmd_0
(.E(E),
.O(O),
.Q({Q[18:16],Q[14:12],Q[5],Q[3:0]}),
.S(S),
.aclk(aclk),
.\axaddr_incr_reg[0]_0 (sel_first),
.\axaddr_incr_reg[11]_0 ({incr_cmd_0_n_3,incr_cmd_0_n_4,incr_cmd_0_n_5,incr_cmd_0_n_6,incr_cmd_0_n_7,incr_cmd_0_n_8,incr_cmd_0_n_9,incr_cmd_0_n_10}),
.\axlen_cnt_reg[0]_0 (\axlen_cnt_reg[0] ),
.incr_next_pending(incr_next_pending),
.\m_axi_araddr[11] (incr_cmd_0_n_11),
.\m_axi_araddr[1] (incr_cmd_0_n_15),
.\m_axi_araddr[2] (incr_cmd_0_n_14),
.\m_axi_araddr[3] (incr_cmd_0_n_13),
.\m_axi_araddr[5] (incr_cmd_0_n_12),
.m_axi_arready(m_axi_arready),
.\m_payload_i_reg[3] (\m_payload_i_reg[3] ),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[47]_0 (\m_payload_i_reg[47]_0 ),
.\m_payload_i_reg[7] (\m_payload_i_reg[7] ),
.m_valid_i_reg(m_valid_i_reg),
.sel_first_reg_0(sel_first_reg_2),
.sel_first_reg_1(sel_first_reg_4),
.si_rs_arvalid(si_rs_arvalid),
.\state_reg[0]_rep (\state_reg[0]_rep_0 ),
.\state_reg[1] (\state_reg[1]_0 ),
.\state_reg[1]_0 (\state_reg[1] ),
.\state_reg[1]_rep (\state_reg[1]_rep ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'h1D))
r_rlast_r_i_1
(.I0(s_axburst_eq0),
.I1(Q[15]),
.I2(s_axburst_eq1),
.O(r_rlast));
FDRE s_axburst_eq0_reg
(.C(aclk),
.CE(1'b1),
.D(wrap_cmd_0_n_6),
.Q(s_axburst_eq0),
.R(1'b0));
FDRE s_axburst_eq1_reg
(.C(aclk),
.CE(1'b1),
.D(wrap_cmd_0_n_7),
.Q(s_axburst_eq1),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_i),
.Q(sel_first_reg_0),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hB8))
\state[1]_i_3
(.I0(s_axburst_eq1),
.I1(Q[15]),
.I2(s_axburst_eq0),
.O(\state_reg[0]_rep ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3 wrap_cmd_0
(.D(D),
.E(E),
.Q({Q[19:15],Q[13:0]}),
.aclk(aclk),
.\axaddr_incr_reg[11] ({incr_cmd_0_n_3,incr_cmd_0_n_4,incr_cmd_0_n_5,incr_cmd_0_n_6,incr_cmd_0_n_7,incr_cmd_0_n_8,incr_cmd_0_n_9,incr_cmd_0_n_10}),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3] ),
.\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3]_0 ),
.\axaddr_offset_r_reg[3]_2 (\axaddr_offset_r_reg[3]_1 ),
.incr_next_pending(incr_next_pending),
.m_axi_araddr(m_axi_araddr),
.\m_payload_i_reg[47] (\m_payload_i_reg[47]_0 ),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.m_valid_i_reg(m_valid_i_reg),
.s_axburst_eq0_reg(wrap_cmd_0_n_6),
.s_axburst_eq1_reg(wrap_cmd_0_n_7),
.sel_first_i(sel_first_i),
.sel_first_reg_0(sel_first_reg_1),
.sel_first_reg_1(sel_first_reg_3),
.sel_first_reg_2(incr_cmd_0_n_11),
.sel_first_reg_3(incr_cmd_0_n_12),
.sel_first_reg_4(incr_cmd_0_n_13),
.sel_first_reg_5(incr_cmd_0_n_14),
.sel_first_reg_6(incr_cmd_0_n_15),
.si_rs_arvalid(si_rs_arvalid),
.\state_reg[1] (\state_reg[1] ),
.\state_reg[1]_rep (\state_reg[1]_rep ),
.\wrap_cnt_r_reg[3]_0 (\wrap_cnt_r_reg[3] ),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_1 (\wrap_second_len_r_reg[3]_0 ),
.\wrap_second_len_r_reg[3]_2 (\wrap_second_len_r_reg[3]_1 ));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_incr_cmd
(next_pending_r_reg_0,
\axaddr_incr_reg[0]_0 ,
Q,
\axlen_cnt_reg[2]_0 ,
\axaddr_incr_reg[11]_0 ,
\m_axi_awaddr[11] ,
\m_axi_awaddr[5] ,
S,
incr_next_pending,
aclk,
sel_first_reg_0,
E,
\m_payload_i_reg[46] ,
\m_payload_i_reg[47] ,
next,
axaddr_incr,
\state_reg[0] ,
\state_reg[1] ,
\state_reg[0]_rep );
output next_pending_r_reg_0;
output \axaddr_incr_reg[0]_0 ;
output [0:0]Q;
output \axlen_cnt_reg[2]_0 ;
output [10:0]\axaddr_incr_reg[11]_0 ;
output \m_axi_awaddr[11] ;
output \m_axi_awaddr[5] ;
output [3:0]S;
input incr_next_pending;
input aclk;
input sel_first_reg_0;
input [0:0]E;
input [9:0]\m_payload_i_reg[46] ;
input \m_payload_i_reg[47] ;
input next;
input [11:0]axaddr_incr;
input [0:0]\state_reg[0] ;
input [0:0]\state_reg[1] ;
input \state_reg[0]_rep ;
wire [0:0]E;
wire [0:0]Q;
wire [3:0]S;
wire aclk;
wire [11:0]axaddr_incr;
wire \axaddr_incr[0]_i_1_n_0 ;
wire \axaddr_incr[10]_i_1_n_0 ;
wire \axaddr_incr[11]_i_1_n_0 ;
wire \axaddr_incr[11]_i_2_n_0 ;
wire \axaddr_incr[1]_i_1_n_0 ;
wire \axaddr_incr[2]_i_1_n_0 ;
wire \axaddr_incr[3]_i_11_n_0 ;
wire \axaddr_incr[3]_i_12_n_0 ;
wire \axaddr_incr[3]_i_13_n_0 ;
wire \axaddr_incr[3]_i_14_n_0 ;
wire \axaddr_incr[3]_i_1_n_0 ;
wire \axaddr_incr[4]_i_1_n_0 ;
wire \axaddr_incr[5]_i_1_n_0 ;
wire \axaddr_incr[6]_i_1_n_0 ;
wire \axaddr_incr[7]_i_1_n_0 ;
wire \axaddr_incr[8]_i_1_n_0 ;
wire \axaddr_incr[9]_i_1_n_0 ;
wire \axaddr_incr_reg[0]_0 ;
wire [10:0]\axaddr_incr_reg[11]_0 ;
wire \axaddr_incr_reg[11]_i_4_n_1 ;
wire \axaddr_incr_reg[11]_i_4_n_2 ;
wire \axaddr_incr_reg[11]_i_4_n_3 ;
wire \axaddr_incr_reg[11]_i_4_n_4 ;
wire \axaddr_incr_reg[11]_i_4_n_5 ;
wire \axaddr_incr_reg[11]_i_4_n_6 ;
wire \axaddr_incr_reg[11]_i_4_n_7 ;
wire \axaddr_incr_reg[3]_i_3_n_0 ;
wire \axaddr_incr_reg[3]_i_3_n_1 ;
wire \axaddr_incr_reg[3]_i_3_n_2 ;
wire \axaddr_incr_reg[3]_i_3_n_3 ;
wire \axaddr_incr_reg[3]_i_3_n_4 ;
wire \axaddr_incr_reg[3]_i_3_n_5 ;
wire \axaddr_incr_reg[3]_i_3_n_6 ;
wire \axaddr_incr_reg[3]_i_3_n_7 ;
wire \axaddr_incr_reg[7]_i_3_n_0 ;
wire \axaddr_incr_reg[7]_i_3_n_1 ;
wire \axaddr_incr_reg[7]_i_3_n_2 ;
wire \axaddr_incr_reg[7]_i_3_n_3 ;
wire \axaddr_incr_reg[7]_i_3_n_4 ;
wire \axaddr_incr_reg[7]_i_3_n_5 ;
wire \axaddr_incr_reg[7]_i_3_n_6 ;
wire \axaddr_incr_reg[7]_i_3_n_7 ;
wire \axaddr_incr_reg_n_0_[5] ;
wire \axlen_cnt[1]_i_1__0_n_0 ;
wire \axlen_cnt[2]_i_1_n_0 ;
wire \axlen_cnt[3]_i_2_n_0 ;
wire \axlen_cnt[4]_i_1_n_0 ;
wire \axlen_cnt[5]_i_1_n_0 ;
wire \axlen_cnt[6]_i_1_n_0 ;
wire \axlen_cnt[7]_i_2_n_0 ;
wire \axlen_cnt[7]_i_3_n_0 ;
wire \axlen_cnt_reg[2]_0 ;
wire \axlen_cnt_reg_n_0_[1] ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire \axlen_cnt_reg_n_0_[4] ;
wire \axlen_cnt_reg_n_0_[5] ;
wire \axlen_cnt_reg_n_0_[6] ;
wire \axlen_cnt_reg_n_0_[7] ;
wire incr_next_pending;
wire \m_axi_awaddr[11] ;
wire \m_axi_awaddr[5] ;
wire [9:0]\m_payload_i_reg[46] ;
wire \m_payload_i_reg[47] ;
wire next;
wire next_pending_r_i_5_n_0;
wire next_pending_r_reg_0;
wire sel_first_reg_0;
wire [0:0]\state_reg[0] ;
wire \state_reg[0]_rep ;
wire [0:0]\state_reg[1] ;
wire [3:3]\NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED ;
(* SOFT_HLUTNM = "soft_lutpair116" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[0]_i_1
(.I0(axaddr_incr[0]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3_n_7 ),
.O(\axaddr_incr[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair117" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[10]_i_1
(.I0(axaddr_incr[10]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4_n_5 ),
.O(\axaddr_incr[10]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\axaddr_incr[11]_i_1
(.I0(\axaddr_incr_reg[0]_0 ),
.I1(next),
.O(\axaddr_incr[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair116" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[11]_i_2
(.I0(axaddr_incr[11]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4_n_4 ),
.O(\axaddr_incr[11]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair117" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[1]_i_1
(.I0(axaddr_incr[1]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3_n_6 ),
.O(\axaddr_incr[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair115" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[2]_i_1
(.I0(axaddr_incr[2]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3_n_5 ),
.O(\axaddr_incr[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair120" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[3]_i_1
(.I0(axaddr_incr[3]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3_n_4 ),
.O(\axaddr_incr[3]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0102))
\axaddr_incr[3]_i_10
(.I0(\m_payload_i_reg[46] [0]),
.I1(\m_payload_i_reg[46] [6]),
.I2(\m_payload_i_reg[46] [5]),
.I3(next),
.O(S[0]));
LUT3 #(
.INIT(8'h6A))
\axaddr_incr[3]_i_11
(.I0(\axaddr_incr_reg[11]_0 [3]),
.I1(\m_payload_i_reg[46] [5]),
.I2(\m_payload_i_reg[46] [6]),
.O(\axaddr_incr[3]_i_11_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_incr[3]_i_12
(.I0(\axaddr_incr_reg[11]_0 [2]),
.I1(\m_payload_i_reg[46] [5]),
.I2(\m_payload_i_reg[46] [6]),
.O(\axaddr_incr[3]_i_12_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_incr[3]_i_13
(.I0(\axaddr_incr_reg[11]_0 [1]),
.I1(\m_payload_i_reg[46] [6]),
.I2(\m_payload_i_reg[46] [5]),
.O(\axaddr_incr[3]_i_13_n_0 ));
LUT3 #(
.INIT(8'hA9))
\axaddr_incr[3]_i_14
(.I0(\axaddr_incr_reg[11]_0 [0]),
.I1(\m_payload_i_reg[46] [5]),
.I2(\m_payload_i_reg[46] [6]),
.O(\axaddr_incr[3]_i_14_n_0 ));
LUT4 #(
.INIT(16'h6AAA))
\axaddr_incr[3]_i_7
(.I0(\m_payload_i_reg[46] [3]),
.I1(\m_payload_i_reg[46] [6]),
.I2(\m_payload_i_reg[46] [5]),
.I3(next),
.O(S[3]));
LUT4 #(
.INIT(16'h262A))
\axaddr_incr[3]_i_8
(.I0(\m_payload_i_reg[46] [2]),
.I1(\m_payload_i_reg[46] [6]),
.I2(\m_payload_i_reg[46] [5]),
.I3(next),
.O(S[2]));
LUT4 #(
.INIT(16'h060A))
\axaddr_incr[3]_i_9
(.I0(\m_payload_i_reg[46] [1]),
.I1(\m_payload_i_reg[46] [5]),
.I2(\m_payload_i_reg[46] [6]),
.I3(next),
.O(S[1]));
(* SOFT_HLUTNM = "soft_lutpair118" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_1
(.I0(axaddr_incr[4]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3_n_7 ),
.O(\axaddr_incr[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair119" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[5]_i_1
(.I0(axaddr_incr[5]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3_n_6 ),
.O(\axaddr_incr[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair119" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[6]_i_1
(.I0(axaddr_incr[6]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3_n_5 ),
.O(\axaddr_incr[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair120" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[7]_i_1
(.I0(axaddr_incr[7]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3_n_4 ),
.O(\axaddr_incr[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair118" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_1
(.I0(axaddr_incr[8]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4_n_7 ),
.O(\axaddr_incr[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair115" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[9]_i_1
(.I0(axaddr_incr[9]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4_n_6 ),
.O(\axaddr_incr[9]_i_1_n_0 ));
FDRE \axaddr_incr_reg[0]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(\axaddr_incr[0]_i_1_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [0]),
.R(1'b0));
FDRE \axaddr_incr_reg[10]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(\axaddr_incr[10]_i_1_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [9]),
.R(1'b0));
FDRE \axaddr_incr_reg[11]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(\axaddr_incr[11]_i_2_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [10]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[11]_i_4
(.CI(\axaddr_incr_reg[7]_i_3_n_0 ),
.CO({\NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED [3],\axaddr_incr_reg[11]_i_4_n_1 ,\axaddr_incr_reg[11]_i_4_n_2 ,\axaddr_incr_reg[11]_i_4_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[11]_i_4_n_4 ,\axaddr_incr_reg[11]_i_4_n_5 ,\axaddr_incr_reg[11]_i_4_n_6 ,\axaddr_incr_reg[11]_i_4_n_7 }),
.S(\axaddr_incr_reg[11]_0 [10:7]));
FDRE \axaddr_incr_reg[1]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(\axaddr_incr[1]_i_1_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [1]),
.R(1'b0));
FDRE \axaddr_incr_reg[2]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(\axaddr_incr[2]_i_1_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [2]),
.R(1'b0));
FDRE \axaddr_incr_reg[3]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(\axaddr_incr[3]_i_1_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [3]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[3]_i_3
(.CI(1'b0),
.CO({\axaddr_incr_reg[3]_i_3_n_0 ,\axaddr_incr_reg[3]_i_3_n_1 ,\axaddr_incr_reg[3]_i_3_n_2 ,\axaddr_incr_reg[3]_i_3_n_3 }),
.CYINIT(1'b0),
.DI(\axaddr_incr_reg[11]_0 [3:0]),
.O({\axaddr_incr_reg[3]_i_3_n_4 ,\axaddr_incr_reg[3]_i_3_n_5 ,\axaddr_incr_reg[3]_i_3_n_6 ,\axaddr_incr_reg[3]_i_3_n_7 }),
.S({\axaddr_incr[3]_i_11_n_0 ,\axaddr_incr[3]_i_12_n_0 ,\axaddr_incr[3]_i_13_n_0 ,\axaddr_incr[3]_i_14_n_0 }));
FDRE \axaddr_incr_reg[4]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(\axaddr_incr[4]_i_1_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [4]),
.R(1'b0));
FDRE \axaddr_incr_reg[5]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(\axaddr_incr[5]_i_1_n_0 ),
.Q(\axaddr_incr_reg_n_0_[5] ),
.R(1'b0));
FDRE \axaddr_incr_reg[6]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(\axaddr_incr[6]_i_1_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [5]),
.R(1'b0));
FDRE \axaddr_incr_reg[7]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(\axaddr_incr[7]_i_1_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [6]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[7]_i_3
(.CI(\axaddr_incr_reg[3]_i_3_n_0 ),
.CO({\axaddr_incr_reg[7]_i_3_n_0 ,\axaddr_incr_reg[7]_i_3_n_1 ,\axaddr_incr_reg[7]_i_3_n_2 ,\axaddr_incr_reg[7]_i_3_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[7]_i_3_n_4 ,\axaddr_incr_reg[7]_i_3_n_5 ,\axaddr_incr_reg[7]_i_3_n_6 ,\axaddr_incr_reg[7]_i_3_n_7 }),
.S({\axaddr_incr_reg[11]_0 [6:5],\axaddr_incr_reg_n_0_[5] ,\axaddr_incr_reg[11]_0 [4]}));
FDRE \axaddr_incr_reg[8]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(\axaddr_incr[8]_i_1_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [7]),
.R(1'b0));
FDRE \axaddr_incr_reg[9]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(\axaddr_incr[9]_i_1_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [8]),
.R(1'b0));
LUT5 #(
.INIT(32'hF88F8888))
\axlen_cnt[1]_i_1__0
(.I0(E),
.I1(\m_payload_i_reg[46] [8]),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(Q),
.I4(\axlen_cnt_reg[2]_0 ),
.O(\axlen_cnt[1]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFA900A900A900))
\axlen_cnt[2]_i_1
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(Q),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg[2]_0 ),
.I4(E),
.I5(\m_payload_i_reg[46] [9]),
.O(\axlen_cnt[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hEEEEEEEBAAAAAAAA))
\axlen_cnt[3]_i_2
(.I0(\m_payload_i_reg[47] ),
.I1(\axlen_cnt_reg_n_0_[3] ),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\axlen_cnt_reg_n_0_[1] ),
.I4(Q),
.I5(\axlen_cnt_reg[2]_0 ),
.O(\axlen_cnt[3]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair112" *)
LUT5 #(
.INIT(32'hAAAAAAA9))
\axlen_cnt[4]_i_1
(.I0(\axlen_cnt_reg_n_0_[4] ),
.I1(\axlen_cnt_reg_n_0_[3] ),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\axlen_cnt_reg_n_0_[1] ),
.I4(Q),
.O(\axlen_cnt[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAAAA9))
\axlen_cnt[5]_i_1
(.I0(\axlen_cnt_reg_n_0_[5] ),
.I1(\axlen_cnt_reg_n_0_[4] ),
.I2(Q),
.I3(\axlen_cnt_reg_n_0_[1] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\axlen_cnt_reg_n_0_[3] ),
.O(\axlen_cnt[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair114" *)
LUT3 #(
.INIT(8'h9A))
\axlen_cnt[6]_i_1
(.I0(\axlen_cnt_reg_n_0_[6] ),
.I1(\axlen_cnt_reg_n_0_[5] ),
.I2(\axlen_cnt[7]_i_3_n_0 ),
.O(\axlen_cnt[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair114" *)
LUT4 #(
.INIT(16'hA9AA))
\axlen_cnt[7]_i_2
(.I0(\axlen_cnt_reg_n_0_[7] ),
.I1(\axlen_cnt_reg_n_0_[6] ),
.I2(\axlen_cnt_reg_n_0_[5] ),
.I3(\axlen_cnt[7]_i_3_n_0 ),
.O(\axlen_cnt[7]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair112" *)
LUT5 #(
.INIT(32'h00000001))
\axlen_cnt[7]_i_3
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(Q),
.I4(\axlen_cnt_reg_n_0_[4] ),
.O(\axlen_cnt[7]_i_3_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\state_reg[1] ),
.Q(Q),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[1]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[2]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[3]_i_2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
FDRE \axlen_cnt_reg[4]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[4]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[4] ),
.R(\state_reg[0]_rep ));
FDRE \axlen_cnt_reg[5]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[5]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[5] ),
.R(\state_reg[0]_rep ));
FDRE \axlen_cnt_reg[6]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[6]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[6] ),
.R(\state_reg[0]_rep ));
FDRE \axlen_cnt_reg[7]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[7]_i_2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[7] ),
.R(\state_reg[0]_rep ));
(* SOFT_HLUTNM = "soft_lutpair113" *)
LUT2 #(
.INIT(4'hB))
\m_axi_awaddr[11]_INST_0_i_1
(.I0(\axaddr_incr_reg[0]_0 ),
.I1(\m_payload_i_reg[46] [7]),
.O(\m_axi_awaddr[11] ));
(* SOFT_HLUTNM = "soft_lutpair113" *)
LUT4 #(
.INIT(16'hEF40))
\m_axi_awaddr[5]_INST_0_i_1
(.I0(\axaddr_incr_reg[0]_0 ),
.I1(\axaddr_incr_reg_n_0_[5] ),
.I2(\m_payload_i_reg[46] [7]),
.I3(\m_payload_i_reg[46] [4]),
.O(\m_axi_awaddr[5] ));
LUT5 #(
.INIT(32'h55545555))
next_pending_r_i_3__0
(.I0(E),
.I1(\axlen_cnt_reg_n_0_[7] ),
.I2(\axlen_cnt_reg_n_0_[5] ),
.I3(\axlen_cnt_reg_n_0_[6] ),
.I4(next_pending_r_i_5_n_0),
.O(\axlen_cnt_reg[2]_0 ));
LUT4 #(
.INIT(16'h0001))
next_pending_r_i_5
(.I0(\axlen_cnt_reg_n_0_[1] ),
.I1(\axlen_cnt_reg_n_0_[4] ),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.O(next_pending_r_i_5_n_0));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(incr_next_pending),
.Q(next_pending_r_reg_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_0),
.Q(\axaddr_incr_reg[0]_0 ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_17_b2s_incr_cmd" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_incr_cmd_2
(incr_next_pending,
\axaddr_incr_reg[0]_0 ,
\axlen_cnt_reg[0]_0 ,
\axaddr_incr_reg[11]_0 ,
\m_axi_araddr[11] ,
\m_axi_araddr[5] ,
\m_axi_araddr[3] ,
\m_axi_araddr[2] ,
\m_axi_araddr[1] ,
S,
aclk,
sel_first_reg_0,
E,
Q,
\m_payload_i_reg[47] ,
\state_reg[1]_rep ,
\m_payload_i_reg[47]_0 ,
O,
\m_payload_i_reg[7] ,
\m_payload_i_reg[3] ,
si_rs_arvalid,
\state_reg[0]_rep ,
m_valid_i_reg,
\state_reg[1] ,
sel_first_reg_1,
\state_reg[1]_0 ,
m_axi_arready);
output incr_next_pending;
output \axaddr_incr_reg[0]_0 ;
output \axlen_cnt_reg[0]_0 ;
output [7:0]\axaddr_incr_reg[11]_0 ;
output \m_axi_araddr[11] ;
output \m_axi_araddr[5] ;
output \m_axi_araddr[3] ;
output \m_axi_araddr[2] ;
output \m_axi_araddr[1] ;
output [3:0]S;
input aclk;
input sel_first_reg_0;
input [0:0]E;
input [10:0]Q;
input \m_payload_i_reg[47] ;
input \state_reg[1]_rep ;
input \m_payload_i_reg[47]_0 ;
input [3:0]O;
input [3:0]\m_payload_i_reg[7] ;
input [3:0]\m_payload_i_reg[3] ;
input si_rs_arvalid;
input \state_reg[0]_rep ;
input [0:0]m_valid_i_reg;
input \state_reg[1] ;
input [0:0]sel_first_reg_1;
input [1:0]\state_reg[1]_0 ;
input m_axi_arready;
wire [0:0]E;
wire [3:0]O;
wire [10:0]Q;
wire [3:0]S;
wire aclk;
wire \axaddr_incr[0]_i_1__0_n_0 ;
wire \axaddr_incr[10]_i_1__0_n_0 ;
wire \axaddr_incr[11]_i_2__0_n_0 ;
wire \axaddr_incr[1]_i_1__0_n_0 ;
wire \axaddr_incr[2]_i_1__0_n_0 ;
wire \axaddr_incr[3]_i_11_n_0 ;
wire \axaddr_incr[3]_i_12_n_0 ;
wire \axaddr_incr[3]_i_13_n_0 ;
wire \axaddr_incr[3]_i_14_n_0 ;
wire \axaddr_incr[3]_i_1__0_n_0 ;
wire \axaddr_incr[4]_i_1__0_n_0 ;
wire \axaddr_incr[5]_i_1__0_n_0 ;
wire \axaddr_incr[6]_i_1__0_n_0 ;
wire \axaddr_incr[7]_i_1__0_n_0 ;
wire \axaddr_incr[8]_i_1__0_n_0 ;
wire \axaddr_incr[9]_i_1__0_n_0 ;
wire \axaddr_incr_reg[0]_0 ;
wire [7:0]\axaddr_incr_reg[11]_0 ;
wire \axaddr_incr_reg[11]_i_4__0_n_1 ;
wire \axaddr_incr_reg[11]_i_4__0_n_2 ;
wire \axaddr_incr_reg[11]_i_4__0_n_3 ;
wire \axaddr_incr_reg[11]_i_4__0_n_4 ;
wire \axaddr_incr_reg[11]_i_4__0_n_5 ;
wire \axaddr_incr_reg[11]_i_4__0_n_6 ;
wire \axaddr_incr_reg[11]_i_4__0_n_7 ;
wire \axaddr_incr_reg[3]_i_3__0_n_0 ;
wire \axaddr_incr_reg[3]_i_3__0_n_1 ;
wire \axaddr_incr_reg[3]_i_3__0_n_2 ;
wire \axaddr_incr_reg[3]_i_3__0_n_3 ;
wire \axaddr_incr_reg[3]_i_3__0_n_4 ;
wire \axaddr_incr_reg[3]_i_3__0_n_5 ;
wire \axaddr_incr_reg[3]_i_3__0_n_6 ;
wire \axaddr_incr_reg[3]_i_3__0_n_7 ;
wire \axaddr_incr_reg[7]_i_3__0_n_0 ;
wire \axaddr_incr_reg[7]_i_3__0_n_1 ;
wire \axaddr_incr_reg[7]_i_3__0_n_2 ;
wire \axaddr_incr_reg[7]_i_3__0_n_3 ;
wire \axaddr_incr_reg[7]_i_3__0_n_4 ;
wire \axaddr_incr_reg[7]_i_3__0_n_5 ;
wire \axaddr_incr_reg[7]_i_3__0_n_6 ;
wire \axaddr_incr_reg[7]_i_3__0_n_7 ;
wire \axaddr_incr_reg_n_0_[1] ;
wire \axaddr_incr_reg_n_0_[2] ;
wire \axaddr_incr_reg_n_0_[3] ;
wire \axaddr_incr_reg_n_0_[5] ;
wire \axlen_cnt[0]_i_1__2_n_0 ;
wire \axlen_cnt[1]_i_1__1_n_0 ;
wire \axlen_cnt[2]_i_1__1_n_0 ;
wire \axlen_cnt[3]_i_2__0_n_0 ;
wire \axlen_cnt[4]_i_1__0_n_0 ;
wire \axlen_cnt[5]_i_1__0_n_0 ;
wire \axlen_cnt[6]_i_1__0_n_0 ;
wire \axlen_cnt[7]_i_2__0_n_0 ;
wire \axlen_cnt[7]_i_3__0_n_0 ;
wire \axlen_cnt_reg[0]_0 ;
wire \axlen_cnt_reg_n_0_[0] ;
wire \axlen_cnt_reg_n_0_[1] ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire \axlen_cnt_reg_n_0_[4] ;
wire \axlen_cnt_reg_n_0_[5] ;
wire \axlen_cnt_reg_n_0_[6] ;
wire \axlen_cnt_reg_n_0_[7] ;
wire incr_next_pending;
wire \m_axi_araddr[11] ;
wire \m_axi_araddr[1] ;
wire \m_axi_araddr[2] ;
wire \m_axi_araddr[3] ;
wire \m_axi_araddr[5] ;
wire m_axi_arready;
wire [3:0]\m_payload_i_reg[3] ;
wire \m_payload_i_reg[47] ;
wire \m_payload_i_reg[47]_0 ;
wire [3:0]\m_payload_i_reg[7] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_i_2__0_n_0;
wire next_pending_r_i_4__0_n_0;
wire next_pending_r_reg_n_0;
wire sel_first_reg_0;
wire [0:0]sel_first_reg_1;
wire si_rs_arvalid;
wire \state_reg[0]_rep ;
wire \state_reg[1] ;
wire [1:0]\state_reg[1]_0 ;
wire \state_reg[1]_rep ;
wire [3:3]\NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED ;
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[0]_i_1__0
(.I0(\m_payload_i_reg[3] [0]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3__0_n_7 ),
.O(\axaddr_incr[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[10]_i_1__0
(.I0(O[2]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4__0_n_5 ),
.O(\axaddr_incr[10]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[11]_i_2__0
(.I0(O[3]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4__0_n_4 ),
.O(\axaddr_incr[11]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[1]_i_1__0
(.I0(\m_payload_i_reg[3] [1]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3__0_n_6 ),
.O(\axaddr_incr[1]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[2]_i_1__0
(.I0(\m_payload_i_reg[3] [2]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3__0_n_5 ),
.O(\axaddr_incr[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h0201020202020202))
\axaddr_incr[3]_i_10
(.I0(Q[0]),
.I1(Q[6]),
.I2(Q[5]),
.I3(\state_reg[1]_0 [1]),
.I4(\state_reg[1]_0 [0]),
.I5(m_axi_arready),
.O(S[0]));
LUT3 #(
.INIT(8'h6A))
\axaddr_incr[3]_i_11
(.I0(\axaddr_incr_reg_n_0_[3] ),
.I1(Q[5]),
.I2(Q[6]),
.O(\axaddr_incr[3]_i_11_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_incr[3]_i_12
(.I0(\axaddr_incr_reg_n_0_[2] ),
.I1(Q[5]),
.I2(Q[6]),
.O(\axaddr_incr[3]_i_12_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_incr[3]_i_13
(.I0(\axaddr_incr_reg_n_0_[1] ),
.I1(Q[6]),
.I2(Q[5]),
.O(\axaddr_incr[3]_i_13_n_0 ));
LUT3 #(
.INIT(8'hA9))
\axaddr_incr[3]_i_14
(.I0(\axaddr_incr_reg[11]_0 [0]),
.I1(Q[5]),
.I2(Q[6]),
.O(\axaddr_incr[3]_i_14_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[3]_i_1__0
(.I0(\m_payload_i_reg[3] [3]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3__0_n_4 ),
.O(\axaddr_incr[3]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hAA6AAAAAAAAAAAAA))
\axaddr_incr[3]_i_7
(.I0(Q[3]),
.I1(Q[6]),
.I2(Q[5]),
.I3(\state_reg[1]_0 [1]),
.I4(\state_reg[1]_0 [0]),
.I5(m_axi_arready),
.O(S[3]));
LUT6 #(
.INIT(64'h2A262A2A2A2A2A2A))
\axaddr_incr[3]_i_8
(.I0(Q[2]),
.I1(Q[6]),
.I2(Q[5]),
.I3(\state_reg[1]_0 [1]),
.I4(\state_reg[1]_0 [0]),
.I5(m_axi_arready),
.O(S[2]));
LUT6 #(
.INIT(64'h0A060A0A0A0A0A0A))
\axaddr_incr[3]_i_9
(.I0(Q[1]),
.I1(Q[5]),
.I2(Q[6]),
.I3(\state_reg[1]_0 [1]),
.I4(\state_reg[1]_0 [0]),
.I5(m_axi_arready),
.O(S[1]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_1__0
(.I0(\m_payload_i_reg[7] [0]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3__0_n_7 ),
.O(\axaddr_incr[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[5]_i_1__0
(.I0(\m_payload_i_reg[7] [1]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3__0_n_6 ),
.O(\axaddr_incr[5]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[6]_i_1__0
(.I0(\m_payload_i_reg[7] [2]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3__0_n_5 ),
.O(\axaddr_incr[6]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[7]_i_1__0
(.I0(\m_payload_i_reg[7] [3]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3__0_n_4 ),
.O(\axaddr_incr[7]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_1__0
(.I0(O[0]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4__0_n_7 ),
.O(\axaddr_incr[8]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[9]_i_1__0
(.I0(O[1]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4__0_n_6 ),
.O(\axaddr_incr[9]_i_1__0_n_0 ));
FDRE \axaddr_incr_reg[0]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[0]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [0]),
.R(1'b0));
FDRE \axaddr_incr_reg[10]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[10]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [6]),
.R(1'b0));
FDRE \axaddr_incr_reg[11]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[11]_i_2__0_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [7]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[11]_i_4__0
(.CI(\axaddr_incr_reg[7]_i_3__0_n_0 ),
.CO({\NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED [3],\axaddr_incr_reg[11]_i_4__0_n_1 ,\axaddr_incr_reg[11]_i_4__0_n_2 ,\axaddr_incr_reg[11]_i_4__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[11]_i_4__0_n_4 ,\axaddr_incr_reg[11]_i_4__0_n_5 ,\axaddr_incr_reg[11]_i_4__0_n_6 ,\axaddr_incr_reg[11]_i_4__0_n_7 }),
.S(\axaddr_incr_reg[11]_0 [7:4]));
FDRE \axaddr_incr_reg[1]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[1]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg_n_0_[1] ),
.R(1'b0));
FDRE \axaddr_incr_reg[2]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[2]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg_n_0_[2] ),
.R(1'b0));
FDRE \axaddr_incr_reg[3]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[3]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg_n_0_[3] ),
.R(1'b0));
CARRY4 \axaddr_incr_reg[3]_i_3__0
(.CI(1'b0),
.CO({\axaddr_incr_reg[3]_i_3__0_n_0 ,\axaddr_incr_reg[3]_i_3__0_n_1 ,\axaddr_incr_reg[3]_i_3__0_n_2 ,\axaddr_incr_reg[3]_i_3__0_n_3 }),
.CYINIT(1'b0),
.DI({\axaddr_incr_reg_n_0_[3] ,\axaddr_incr_reg_n_0_[2] ,\axaddr_incr_reg_n_0_[1] ,\axaddr_incr_reg[11]_0 [0]}),
.O({\axaddr_incr_reg[3]_i_3__0_n_4 ,\axaddr_incr_reg[3]_i_3__0_n_5 ,\axaddr_incr_reg[3]_i_3__0_n_6 ,\axaddr_incr_reg[3]_i_3__0_n_7 }),
.S({\axaddr_incr[3]_i_11_n_0 ,\axaddr_incr[3]_i_12_n_0 ,\axaddr_incr[3]_i_13_n_0 ,\axaddr_incr[3]_i_14_n_0 }));
FDRE \axaddr_incr_reg[4]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[4]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [1]),
.R(1'b0));
FDRE \axaddr_incr_reg[5]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[5]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg_n_0_[5] ),
.R(1'b0));
FDRE \axaddr_incr_reg[6]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[6]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [2]),
.R(1'b0));
FDRE \axaddr_incr_reg[7]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[7]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [3]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[7]_i_3__0
(.CI(\axaddr_incr_reg[3]_i_3__0_n_0 ),
.CO({\axaddr_incr_reg[7]_i_3__0_n_0 ,\axaddr_incr_reg[7]_i_3__0_n_1 ,\axaddr_incr_reg[7]_i_3__0_n_2 ,\axaddr_incr_reg[7]_i_3__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[7]_i_3__0_n_4 ,\axaddr_incr_reg[7]_i_3__0_n_5 ,\axaddr_incr_reg[7]_i_3__0_n_6 ,\axaddr_incr_reg[7]_i_3__0_n_7 }),
.S({\axaddr_incr_reg[11]_0 [3:2],\axaddr_incr_reg_n_0_[5] ,\axaddr_incr_reg[11]_0 [1]}));
FDRE \axaddr_incr_reg[8]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[8]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [4]),
.R(1'b0));
FDRE \axaddr_incr_reg[9]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[9]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [5]),
.R(1'b0));
LUT5 #(
.INIT(32'h20FF2020))
\axlen_cnt[0]_i_1__2
(.I0(si_rs_arvalid),
.I1(\state_reg[0]_rep ),
.I2(Q[8]),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(\axlen_cnt_reg[0]_0 ),
.O(\axlen_cnt[0]_i_1__2_n_0 ));
LUT5 #(
.INIT(32'hF88F8888))
\axlen_cnt[1]_i_1__1
(.I0(E),
.I1(Q[9]),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(\axlen_cnt_reg[0]_0 ),
.O(\axlen_cnt[1]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'hFFFFA900A900A900))
\axlen_cnt[2]_i_1__1
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg[0]_0 ),
.I4(E),
.I5(Q[10]),
.O(\axlen_cnt[2]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'hEEEEEEEBAAAAAAAA))
\axlen_cnt[3]_i_2__0
(.I0(\m_payload_i_reg[47] ),
.I1(\axlen_cnt_reg_n_0_[3] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\axlen_cnt_reg[0]_0 ),
.O(\axlen_cnt[3]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'h55545555))
\axlen_cnt[3]_i_4
(.I0(E),
.I1(\axlen_cnt_reg_n_0_[7] ),
.I2(\axlen_cnt_reg_n_0_[5] ),
.I3(\axlen_cnt_reg_n_0_[6] ),
.I4(next_pending_r_i_4__0_n_0),
.O(\axlen_cnt_reg[0]_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'hAAAAAAA9))
\axlen_cnt[4]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[4] ),
.I1(\axlen_cnt_reg_n_0_[1] ),
.I2(\axlen_cnt_reg_n_0_[0] ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.O(\axlen_cnt[4]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAAAAAAAA9))
\axlen_cnt[5]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[5] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[1] ),
.I5(\axlen_cnt_reg_n_0_[4] ),
.O(\axlen_cnt[5]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'h9A))
\axlen_cnt[6]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[6] ),
.I1(\axlen_cnt_reg_n_0_[5] ),
.I2(\axlen_cnt[7]_i_3__0_n_0 ),
.O(\axlen_cnt[6]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'hA9AA))
\axlen_cnt[7]_i_2__0
(.I0(\axlen_cnt_reg_n_0_[7] ),
.I1(\axlen_cnt_reg_n_0_[6] ),
.I2(\axlen_cnt_reg_n_0_[5] ),
.I3(\axlen_cnt[7]_i_3__0_n_0 ),
.O(\axlen_cnt[7]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h00000001))
\axlen_cnt[7]_i_3__0
(.I0(\axlen_cnt_reg_n_0_[4] ),
.I1(\axlen_cnt_reg_n_0_[1] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(\axlen_cnt_reg_n_0_[0] ),
.O(\axlen_cnt[7]_i_3__0_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[0]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[0] ),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[1]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[2]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[3]_i_2__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
FDRE \axlen_cnt_reg[4]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[4]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[4] ),
.R(\state_reg[1] ));
FDRE \axlen_cnt_reg[5]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[5]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[5] ),
.R(\state_reg[1] ));
FDRE \axlen_cnt_reg[6]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[6]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[6] ),
.R(\state_reg[1] ));
FDRE \axlen_cnt_reg[7]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[7]_i_2__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[7] ),
.R(\state_reg[1] ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'hB))
\m_axi_araddr[11]_INST_0_i_1
(.I0(\axaddr_incr_reg[0]_0 ),
.I1(Q[7]),
.O(\m_axi_araddr[11] ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'hEF40))
\m_axi_araddr[1]_INST_0_i_1
(.I0(\axaddr_incr_reg[0]_0 ),
.I1(\axaddr_incr_reg_n_0_[1] ),
.I2(Q[7]),
.I3(Q[1]),
.O(\m_axi_araddr[1] ));
LUT4 #(
.INIT(16'hEF40))
\m_axi_araddr[2]_INST_0_i_1
(.I0(\axaddr_incr_reg[0]_0 ),
.I1(\axaddr_incr_reg_n_0_[2] ),
.I2(Q[7]),
.I3(Q[2]),
.O(\m_axi_araddr[2] ));
LUT4 #(
.INIT(16'hEF40))
\m_axi_araddr[3]_INST_0_i_1
(.I0(\axaddr_incr_reg[0]_0 ),
.I1(\axaddr_incr_reg_n_0_[3] ),
.I2(Q[7]),
.I3(Q[3]),
.O(\m_axi_araddr[3] ));
LUT4 #(
.INIT(16'hEF40))
\m_axi_araddr[5]_INST_0_i_1
(.I0(\axaddr_incr_reg[0]_0 ),
.I1(\axaddr_incr_reg_n_0_[5] ),
.I2(Q[7]),
.I3(Q[4]),
.O(\m_axi_araddr[5] ));
LUT5 #(
.INIT(32'hFFFF505C))
next_pending_r_i_1__2
(.I0(next_pending_r_i_2__0_n_0),
.I1(next_pending_r_reg_n_0),
.I2(\state_reg[1]_rep ),
.I3(E),
.I4(\m_payload_i_reg[47]_0 ),
.O(incr_next_pending));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h0002))
next_pending_r_i_2__0
(.I0(next_pending_r_i_4__0_n_0),
.I1(\axlen_cnt_reg_n_0_[6] ),
.I2(\axlen_cnt_reg_n_0_[5] ),
.I3(\axlen_cnt_reg_n_0_[7] ),
.O(next_pending_r_i_2__0_n_0));
LUT4 #(
.INIT(16'h0001))
next_pending_r_i_4__0
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(\axlen_cnt_reg_n_0_[3] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[4] ),
.O(next_pending_r_i_4__0_n_0));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(incr_next_pending),
.Q(next_pending_r_reg_n_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_0),
.Q(\axaddr_incr_reg[0]_0 ),
.R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_r_channel
(m_valid_i_reg,
\state_reg[1]_rep ,
m_axi_rready,
out,
\skid_buffer_reg[46] ,
\state_reg[1]_rep_0 ,
aclk,
r_rlast,
s_ready_i_reg,
si_rs_rready,
m_axi_rvalid,
in,
areset_d1,
D);
output m_valid_i_reg;
output \state_reg[1]_rep ;
output m_axi_rready;
output [33:0]out;
output [12:0]\skid_buffer_reg[46] ;
input \state_reg[1]_rep_0 ;
input aclk;
input r_rlast;
input s_ready_i_reg;
input si_rs_rready;
input m_axi_rvalid;
input [33:0]in;
input areset_d1;
input [11:0]D;
wire [11:0]D;
wire aclk;
wire areset_d1;
wire [33:0]in;
wire m_axi_rready;
wire m_axi_rvalid;
wire m_valid_i_reg;
wire [33:0]out;
wire r_push_r;
wire r_rlast;
wire rd_data_fifo_0_n_0;
wire rd_data_fifo_0_n_1;
wire rd_data_fifo_0_n_2;
wire rd_data_fifo_0_n_4;
wire s_ready_i_reg;
wire si_rs_rready;
wire [12:0]\skid_buffer_reg[46] ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire [12:0]trans_in;
FDRE \r_arid_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(D[0]),
.Q(trans_in[1]),
.R(1'b0));
FDRE \r_arid_r_reg[10]
(.C(aclk),
.CE(1'b1),
.D(D[10]),
.Q(trans_in[11]),
.R(1'b0));
FDRE \r_arid_r_reg[11]
(.C(aclk),
.CE(1'b1),
.D(D[11]),
.Q(trans_in[12]),
.R(1'b0));
FDRE \r_arid_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(D[1]),
.Q(trans_in[2]),
.R(1'b0));
FDRE \r_arid_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(D[2]),
.Q(trans_in[3]),
.R(1'b0));
FDRE \r_arid_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(D[3]),
.Q(trans_in[4]),
.R(1'b0));
FDRE \r_arid_r_reg[4]
(.C(aclk),
.CE(1'b1),
.D(D[4]),
.Q(trans_in[5]),
.R(1'b0));
FDRE \r_arid_r_reg[5]
(.C(aclk),
.CE(1'b1),
.D(D[5]),
.Q(trans_in[6]),
.R(1'b0));
FDRE \r_arid_r_reg[6]
(.C(aclk),
.CE(1'b1),
.D(D[6]),
.Q(trans_in[7]),
.R(1'b0));
FDRE \r_arid_r_reg[7]
(.C(aclk),
.CE(1'b1),
.D(D[7]),
.Q(trans_in[8]),
.R(1'b0));
FDRE \r_arid_r_reg[8]
(.C(aclk),
.CE(1'b1),
.D(D[8]),
.Q(trans_in[9]),
.R(1'b0));
FDRE \r_arid_r_reg[9]
(.C(aclk),
.CE(1'b1),
.D(D[9]),
.Q(trans_in[10]),
.R(1'b0));
FDRE r_push_r_reg
(.C(aclk),
.CE(1'b1),
.D(\state_reg[1]_rep_0 ),
.Q(r_push_r),
.R(1'b0));
FDRE r_rlast_r_reg
(.C(aclk),
.CE(1'b1),
.D(r_rlast),
.Q(trans_in[0]),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1 rd_data_fifo_0
(.aclk(aclk),
.areset_d1(areset_d1),
.\cnt_read_reg[4]_rep__0_0 (m_valid_i_reg),
.\cnt_read_reg[4]_rep__2_0 (rd_data_fifo_0_n_0),
.\cnt_read_reg[4]_rep__2_1 (rd_data_fifo_0_n_1),
.\cnt_read_reg[4]_rep__2_2 (rd_data_fifo_0_n_2),
.in(in),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.out(out),
.s_ready_i_reg(s_ready_i_reg),
.si_rs_rready(si_rs_rready),
.\state_reg[1]_rep (rd_data_fifo_0_n_4));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2 transaction_fifo_0
(.aclk(aclk),
.areset_d1(areset_d1),
.\cnt_read_reg[0]_rep__3 (rd_data_fifo_0_n_2),
.\cnt_read_reg[0]_rep__3_0 (rd_data_fifo_0_n_4),
.\cnt_read_reg[3]_rep__2 (rd_data_fifo_0_n_0),
.\cnt_read_reg[4]_rep__2 (rd_data_fifo_0_n_1),
.in(trans_in),
.m_valid_i_reg(m_valid_i_reg),
.r_push_r(r_push_r),
.s_ready_i_reg(s_ready_i_reg),
.si_rs_rready(si_rs_rready),
.\skid_buffer_reg[46] (\skid_buffer_reg[46] ),
.\state_reg[1]_rep (\state_reg[1]_rep ));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_rd_cmd_fsm
(\axlen_cnt_reg[7] ,
Q,
r_push_r_reg,
\m_payload_i_reg[0] ,
\m_payload_i_reg[0]_0 ,
D,
\wrap_second_len_r_reg[0] ,
E,
sel_first_reg,
sel_first_reg_0,
sel_first_i,
\wrap_cnt_r_reg[3] ,
\axaddr_offset_r_reg[2] ,
\wrap_cnt_r_reg[3]_0 ,
\wrap_boundary_axaddr_r_reg[11] ,
\axaddr_incr_reg[0] ,
m_axi_arvalid,
m_valid_i0,
s_ready_i0,
\m_payload_i_reg[0]_1 ,
m_axi_arready,
si_rs_arvalid,
\axlen_cnt_reg[7]_0 ,
s_axburst_eq1_reg,
\cnt_read_reg[2]_rep__0 ,
\wrap_second_len_r_reg[0]_0 ,
\axaddr_offset_r_reg[3] ,
axaddr_offset,
sel_first_reg_1,
areset_d1,
sel_first,
sel_first_reg_2,
\axaddr_offset_r_reg[3]_0 ,
\m_payload_i_reg[46] ,
\m_payload_i_reg[5] ,
s_axi_arvalid,
s_ready_i_reg,
aclk);
output \axlen_cnt_reg[7] ;
output [1:0]Q;
output r_push_r_reg;
output \m_payload_i_reg[0] ;
output \m_payload_i_reg[0]_0 ;
output [0:0]D;
output [0:0]\wrap_second_len_r_reg[0] ;
output [0:0]E;
output sel_first_reg;
output sel_first_reg_0;
output sel_first_i;
output \wrap_cnt_r_reg[3] ;
output [0:0]\axaddr_offset_r_reg[2] ;
output \wrap_cnt_r_reg[3]_0 ;
output [0:0]\wrap_boundary_axaddr_r_reg[11] ;
output [0:0]\axaddr_incr_reg[0] ;
output m_axi_arvalid;
output m_valid_i0;
output s_ready_i0;
output [0:0]\m_payload_i_reg[0]_1 ;
input m_axi_arready;
input si_rs_arvalid;
input \axlen_cnt_reg[7]_0 ;
input s_axburst_eq1_reg;
input \cnt_read_reg[2]_rep__0 ;
input [0:0]\wrap_second_len_r_reg[0]_0 ;
input \axaddr_offset_r_reg[3] ;
input [0:0]axaddr_offset;
input sel_first_reg_1;
input areset_d1;
input sel_first;
input sel_first_reg_2;
input [1:0]\axaddr_offset_r_reg[3]_0 ;
input [0:0]\m_payload_i_reg[46] ;
input \m_payload_i_reg[5] ;
input s_axi_arvalid;
input s_ready_i_reg;
input aclk;
wire [0:0]D;
wire [0:0]E;
wire [1:0]Q;
wire aclk;
wire areset_d1;
wire [0:0]\axaddr_incr_reg[0] ;
wire [0:0]axaddr_offset;
wire [0:0]\axaddr_offset_r_reg[2] ;
wire \axaddr_offset_r_reg[3] ;
wire [1:0]\axaddr_offset_r_reg[3]_0 ;
wire \axlen_cnt_reg[7] ;
wire \axlen_cnt_reg[7]_0 ;
wire \cnt_read_reg[2]_rep__0 ;
wire m_axi_arready;
wire m_axi_arvalid;
wire \m_payload_i_reg[0] ;
wire \m_payload_i_reg[0]_0 ;
wire [0:0]\m_payload_i_reg[0]_1 ;
wire [0:0]\m_payload_i_reg[46] ;
wire \m_payload_i_reg[5] ;
wire m_valid_i0;
wire [1:0]next_state__0;
wire r_push_r_reg;
wire s_axburst_eq1_reg;
wire s_axi_arvalid;
wire s_ready_i0;
wire s_ready_i_reg;
wire sel_first;
wire sel_first_i;
wire sel_first_reg;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire si_rs_arvalid;
wire [0:0]\wrap_boundary_axaddr_r_reg[11] ;
wire \wrap_cnt_r_reg[3] ;
wire \wrap_cnt_r_reg[3]_0 ;
wire [0:0]\wrap_second_len_r_reg[0] ;
wire [0:0]\wrap_second_len_r_reg[0]_0 ;
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'hAAEA))
\axaddr_incr[11]_i_1__0
(.I0(sel_first),
.I1(m_axi_arready),
.I2(\m_payload_i_reg[0]_0 ),
.I3(\m_payload_i_reg[0] ),
.O(\axaddr_incr_reg[0] ));
LUT6 #(
.INIT(64'hAAAAACAAAAAAA0AA))
\axaddr_offset_r[2]_i_1__0
(.I0(\axaddr_offset_r_reg[3]_0 [0]),
.I1(\m_payload_i_reg[46] ),
.I2(\m_payload_i_reg[0]_0 ),
.I3(si_rs_arvalid),
.I4(\m_payload_i_reg[0] ),
.I5(\m_payload_i_reg[5] ),
.O(\axaddr_offset_r_reg[2] ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h00CA))
\axlen_cnt[3]_i_1__2
(.I0(si_rs_arvalid),
.I1(m_axi_arready),
.I2(Q[0]),
.I3(Q[1]),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h00005140))
\axlen_cnt[7]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(m_axi_arready),
.I3(si_rs_arvalid),
.I4(\axlen_cnt_reg[7]_0 ),
.O(\axlen_cnt_reg[7] ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h2))
m_axi_arvalid_INST_0
(.I0(\m_payload_i_reg[0]_0 ),
.I1(\m_payload_i_reg[0] ),
.O(m_axi_arvalid));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'hD5))
\m_payload_i[31]_i_1__0
(.I0(si_rs_arvalid),
.I1(\m_payload_i_reg[0] ),
.I2(\m_payload_i_reg[0]_0 ),
.O(\m_payload_i_reg[0]_1 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hFF70FFFF))
m_valid_i_i_1__1
(.I0(\m_payload_i_reg[0]_0 ),
.I1(\m_payload_i_reg[0] ),
.I2(si_rs_arvalid),
.I3(s_axi_arvalid),
.I4(s_ready_i_reg),
.O(m_valid_i0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h40))
r_push_r_i_1
(.I0(\m_payload_i_reg[0] ),
.I1(\m_payload_i_reg[0]_0 ),
.I2(m_axi_arready),
.O(r_push_r_reg));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h8FFF8F8F))
s_ready_i_i_1__0
(.I0(\m_payload_i_reg[0]_0 ),
.I1(\m_payload_i_reg[0] ),
.I2(si_rs_arvalid),
.I3(s_axi_arvalid),
.I4(s_ready_i_reg),
.O(s_ready_i0));
LUT6 #(
.INIT(64'hFFFFFFFFC4C4CFCC))
sel_first_i_1__2
(.I0(m_axi_arready),
.I1(sel_first_reg_1),
.I2(Q[1]),
.I3(si_rs_arvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg));
LUT6 #(
.INIT(64'hFFFFFFFFC4C4CFCC))
sel_first_i_1__3
(.I0(m_axi_arready),
.I1(sel_first),
.I2(\m_payload_i_reg[0] ),
.I3(si_rs_arvalid),
.I4(\m_payload_i_reg[0]_0 ),
.I5(areset_d1),
.O(sel_first_reg_0));
LUT6 #(
.INIT(64'hFCFFFFFFCCCECCCE))
sel_first_i_1__4
(.I0(si_rs_arvalid),
.I1(areset_d1),
.I2(\m_payload_i_reg[0] ),
.I3(\m_payload_i_reg[0]_0 ),
.I4(m_axi_arready),
.I5(sel_first_reg_2),
.O(sel_first_i));
LUT6 #(
.INIT(64'h003030303E3E3E3E))
\state[0]_i_1__0
(.I0(si_rs_arvalid),
.I1(Q[1]),
.I2(Q[0]),
.I3(m_axi_arready),
.I4(s_axburst_eq1_reg),
.I5(\cnt_read_reg[2]_rep__0 ),
.O(next_state__0[0]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h00AAB000))
\state[1]_i_1
(.I0(\cnt_read_reg[2]_rep__0 ),
.I1(s_axburst_eq1_reg),
.I2(m_axi_arready),
.I3(\m_payload_i_reg[0]_0 ),
.I4(\m_payload_i_reg[0] ),
.O(next_state__0[1]));
(* FSM_ENCODED_STATES = "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]
(.C(aclk),
.CE(1'b1),
.D(next_state__0[0]),
.Q(Q[0]),
.R(areset_d1));
(* FSM_ENCODED_STATES = "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11" *)
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(next_state__0[0]),
.Q(\m_payload_i_reg[0]_0 ),
.R(areset_d1));
(* FSM_ENCODED_STATES = "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]
(.C(aclk),
.CE(1'b1),
.D(next_state__0[1]),
.Q(Q[1]),
.R(areset_d1));
(* FSM_ENCODED_STATES = "SM_IDLE:00,SM_CMD_EN:01,SM_CMD_ACCEPTED:10,SM_DONE:11" *)
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(next_state__0[1]),
.Q(\m_payload_i_reg[0] ),
.R(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'h04))
\wrap_boundary_axaddr_r[11]_i_1__0
(.I0(\m_payload_i_reg[0] ),
.I1(si_rs_arvalid),
.I2(\m_payload_i_reg[0]_0 ),
.O(\wrap_boundary_axaddr_r_reg[11] ));
LUT6 #(
.INIT(64'hAA8A5575AA8A5545))
\wrap_cnt_r[0]_i_1__0
(.I0(\wrap_second_len_r_reg[0]_0 ),
.I1(Q[0]),
.I2(si_rs_arvalid),
.I3(Q[1]),
.I4(\axaddr_offset_r_reg[3] ),
.I5(axaddr_offset),
.O(D));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'hAA8A))
\wrap_cnt_r[3]_i_4__0
(.I0(\axaddr_offset_r_reg[3]_0 [1]),
.I1(\m_payload_i_reg[0]_0 ),
.I2(si_rs_arvalid),
.I3(\m_payload_i_reg[0] ),
.O(\wrap_cnt_r_reg[3] ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hAA8A))
\wrap_cnt_r[3]_i_6__0
(.I0(\axaddr_offset_r_reg[3]_0 [0]),
.I1(\m_payload_i_reg[0]_0 ),
.I2(si_rs_arvalid),
.I3(\m_payload_i_reg[0] ),
.O(\wrap_cnt_r_reg[3]_0 ));
LUT6 #(
.INIT(64'hAA8AAA8AAA8AAABA))
\wrap_second_len_r[0]_i_1__0
(.I0(\wrap_second_len_r_reg[0]_0 ),
.I1(Q[0]),
.I2(si_rs_arvalid),
.I3(Q[1]),
.I4(\axaddr_offset_r_reg[3] ),
.I5(axaddr_offset),
.O(\wrap_second_len_r_reg[0] ));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo
(\cnt_read_reg[0]_rep__0_0 ,
\cnt_read_reg[1]_rep__0_0 ,
SR,
D,
bresp_push,
bvalid_i_reg,
out,
b_push,
shandshake_r,
areset_d1,
Q,
\bresp_cnt_reg[7] ,
mhandshake_r,
si_rs_bready,
bvalid_i_reg_0,
in,
aclk);
output \cnt_read_reg[0]_rep__0_0 ;
output \cnt_read_reg[1]_rep__0_0 ;
output [0:0]SR;
output [0:0]D;
output bresp_push;
output bvalid_i_reg;
output [11:0]out;
input b_push;
input shandshake_r;
input areset_d1;
input [1:0]Q;
input [7:0]\bresp_cnt_reg[7] ;
input mhandshake_r;
input si_rs_bready;
input bvalid_i_reg_0;
input [15:0]in;
input aclk;
wire [0:0]D;
wire [1:0]Q;
wire [0:0]SR;
wire aclk;
wire areset_d1;
wire b_push;
wire \bresp_cnt[7]_i_3_n_0 ;
wire \bresp_cnt[7]_i_4_n_0 ;
wire \bresp_cnt[7]_i_5_n_0 ;
wire [7:0]\bresp_cnt_reg[7] ;
wire bresp_push;
wire bvalid_i_i_2_n_0;
wire bvalid_i_reg;
wire bvalid_i_reg_0;
wire [1:0]cnt_read;
wire \cnt_read[0]_i_1__2_n_0 ;
wire \cnt_read[1]_i_1_n_0 ;
wire \cnt_read_reg[0]_rep__0_0 ;
wire \cnt_read_reg[0]_rep_n_0 ;
wire \cnt_read_reg[1]_rep__0_0 ;
wire \cnt_read_reg[1]_rep_n_0 ;
wire [15:0]in;
wire \memory_reg[3][0]_srl4_i_2__0_n_0 ;
wire \memory_reg[3][0]_srl4_i_3_n_0 ;
wire \memory_reg[3][0]_srl4_n_0 ;
wire \memory_reg[3][1]_srl4_n_0 ;
wire \memory_reg[3][2]_srl4_n_0 ;
wire \memory_reg[3][3]_srl4_n_0 ;
wire mhandshake_r;
wire [11:0]out;
wire shandshake_r;
wire si_rs_bready;
LUT4 #(
.INIT(16'hABAA))
\bresp_cnt[7]_i_1
(.I0(areset_d1),
.I1(\bresp_cnt[7]_i_3_n_0 ),
.I2(\bresp_cnt[7]_i_4_n_0 ),
.I3(\bresp_cnt[7]_i_5_n_0 ),
.O(SR));
LUT6 #(
.INIT(64'hEEFEFFFFFFFFEEFE))
\bresp_cnt[7]_i_3
(.I0(\bresp_cnt_reg[7] [7]),
.I1(\bresp_cnt_reg[7] [6]),
.I2(\bresp_cnt_reg[7] [0]),
.I3(\memory_reg[3][0]_srl4_n_0 ),
.I4(\bresp_cnt_reg[7] [3]),
.I5(\memory_reg[3][3]_srl4_n_0 ),
.O(\bresp_cnt[7]_i_3_n_0 ));
LUT5 #(
.INIT(32'hFFF6FFFF))
\bresp_cnt[7]_i_4
(.I0(\bresp_cnt_reg[7] [1]),
.I1(\memory_reg[3][1]_srl4_n_0 ),
.I2(\bresp_cnt_reg[7] [4]),
.I3(\bresp_cnt_reg[7] [5]),
.I4(mhandshake_r),
.O(\bresp_cnt[7]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000D00DD00DD00D))
\bresp_cnt[7]_i_5
(.I0(\memory_reg[3][0]_srl4_n_0 ),
.I1(\bresp_cnt_reg[7] [0]),
.I2(\bresp_cnt_reg[7] [2]),
.I3(\memory_reg[3][2]_srl4_n_0 ),
.I4(\cnt_read_reg[1]_rep__0_0 ),
.I5(\cnt_read_reg[0]_rep__0_0 ),
.O(\bresp_cnt[7]_i_5_n_0 ));
LUT4 #(
.INIT(16'h0444))
bvalid_i_i_1
(.I0(areset_d1),
.I1(bvalid_i_i_2_n_0),
.I2(si_rs_bready),
.I3(bvalid_i_reg_0),
.O(bvalid_i_reg));
LUT6 #(
.INIT(64'hFFFFFFFF00070707))
bvalid_i_i_2
(.I0(\cnt_read_reg[1]_rep__0_0 ),
.I1(\cnt_read_reg[0]_rep__0_0 ),
.I2(shandshake_r),
.I3(Q[1]),
.I4(Q[0]),
.I5(bvalid_i_reg_0),
.O(bvalid_i_i_2_n_0));
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1
(.I0(bresp_push),
.I1(shandshake_r),
.I2(Q[0]),
.O(D));
(* SOFT_HLUTNM = "soft_lutpair121" *)
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1__2
(.I0(\cnt_read_reg[0]_rep__0_0 ),
.I1(b_push),
.I2(shandshake_r),
.O(\cnt_read[0]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair121" *)
LUT4 #(
.INIT(16'hE718))
\cnt_read[1]_i_1
(.I0(\cnt_read_reg[0]_rep__0_0 ),
.I1(b_push),
.I2(shandshake_r),
.I3(\cnt_read_reg[1]_rep__0_0 ),
.O(\cnt_read[1]_i_1_n_0 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__2_n_0 ),
.Q(cnt_read[0]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__2_n_0 ),
.Q(\cnt_read_reg[0]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__2_n_0 ),
.Q(\cnt_read_reg[0]_rep__0_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1_n_0 ),
.Q(cnt_read[1]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1_n_0 ),
.Q(\cnt_read_reg[1]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1_n_0 ),
.Q(\cnt_read_reg[1]_rep__0_0 ),
.S(areset_d1));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][0]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[0]),
.Q(\memory_reg[3][0]_srl4_n_0 ));
LUT6 #(
.INIT(64'h0000000041004141))
\memory_reg[3][0]_srl4_i_1__0
(.I0(\memory_reg[3][0]_srl4_i_2__0_n_0 ),
.I1(\memory_reg[3][2]_srl4_n_0 ),
.I2(\bresp_cnt_reg[7] [2]),
.I3(\bresp_cnt_reg[7] [0]),
.I4(\memory_reg[3][0]_srl4_n_0 ),
.I5(\memory_reg[3][0]_srl4_i_3_n_0 ),
.O(bresp_push));
LUT2 #(
.INIT(4'h8))
\memory_reg[3][0]_srl4_i_2__0
(.I0(\cnt_read_reg[1]_rep__0_0 ),
.I1(\cnt_read_reg[0]_rep__0_0 ),
.O(\memory_reg[3][0]_srl4_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hFFFBFFFFFFFFFFFB))
\memory_reg[3][0]_srl4_i_3
(.I0(\bresp_cnt[7]_i_3_n_0 ),
.I1(mhandshake_r),
.I2(\bresp_cnt_reg[7] [5]),
.I3(\bresp_cnt_reg[7] [4]),
.I4(\memory_reg[3][1]_srl4_n_0 ),
.I5(\bresp_cnt_reg[7] [1]),
.O(\memory_reg[3][0]_srl4_i_3_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][10]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[6]),
.Q(out[2]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][11]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[7]),
.Q(out[3]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][12]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[8]),
.Q(out[4]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][13]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[9]),
.Q(out[5]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][14]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[10]),
.Q(out[6]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][15]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[11]),
.Q(out[7]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][16]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[12]),
.Q(out[8]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][17]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[13]),
.Q(out[9]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][18]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[14]),
.Q(out[10]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][19]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[15]),
.Q(out[11]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][1]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[1]),
.Q(\memory_reg[3][1]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][2]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[2]),
.Q(\memory_reg[3][2]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][3]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[3]),
.Q(\memory_reg[3][3]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][8]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[4]),
.Q(out[0]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][9]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[5]),
.Q(out[1]));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_17_b2s_simple_fifo" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized0
(Q,
mhandshake,
m_axi_bready,
\skid_buffer_reg[1] ,
shandshake_r,
sel,
m_axi_bvalid,
mhandshake_r,
in,
aclk,
areset_d1,
D);
output [1:0]Q;
output mhandshake;
output m_axi_bready;
output [1:0]\skid_buffer_reg[1] ;
input shandshake_r;
input sel;
input m_axi_bvalid;
input mhandshake_r;
input [1:0]in;
input aclk;
input areset_d1;
input [0:0]D;
wire [0:0]D;
wire [1:0]Q;
wire aclk;
wire areset_d1;
wire \cnt_read[1]_i_1__0_n_0 ;
wire [1:0]in;
wire m_axi_bready;
wire m_axi_bvalid;
wire mhandshake;
wire mhandshake_r;
wire sel;
wire shandshake_r;
wire [1:0]\skid_buffer_reg[1] ;
(* SOFT_HLUTNM = "soft_lutpair122" *)
LUT4 #(
.INIT(16'hA69A))
\cnt_read[1]_i_1__0
(.I0(Q[1]),
.I1(Q[0]),
.I2(shandshake_r),
.I3(sel),
.O(\cnt_read[1]_i_1__0_n_0 ));
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(D),
.Q(Q[0]),
.S(areset_d1));
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__0_n_0 ),
.Q(Q[1]),
.S(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair122" *)
LUT3 #(
.INIT(8'h08))
m_axi_bready_INST_0
(.I0(Q[1]),
.I1(Q[0]),
.I2(mhandshake_r),
.O(m_axi_bready));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][0]_srl4
(.A0(Q[0]),
.A1(Q[1]),
.A2(1'b0),
.A3(1'b0),
.CE(sel),
.CLK(aclk),
.D(in[0]),
.Q(\skid_buffer_reg[1] [0]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][1]_srl4
(.A0(Q[0]),
.A1(Q[1]),
.A2(1'b0),
.A3(1'b0),
.CE(sel),
.CLK(aclk),
.D(in[1]),
.Q(\skid_buffer_reg[1] [1]));
LUT4 #(
.INIT(16'h2000))
mhandshake_r_i_1
(.I0(m_axi_bvalid),
.I1(mhandshake_r),
.I2(Q[0]),
.I3(Q[1]),
.O(mhandshake));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_17_b2s_simple_fifo" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized1
(\cnt_read_reg[4]_rep__2_0 ,
\cnt_read_reg[4]_rep__2_1 ,
\cnt_read_reg[4]_rep__2_2 ,
m_axi_rready,
\state_reg[1]_rep ,
out,
s_ready_i_reg,
\cnt_read_reg[4]_rep__0_0 ,
si_rs_rready,
m_axi_rvalid,
in,
aclk,
areset_d1);
output \cnt_read_reg[4]_rep__2_0 ;
output \cnt_read_reg[4]_rep__2_1 ;
output \cnt_read_reg[4]_rep__2_2 ;
output m_axi_rready;
output \state_reg[1]_rep ;
output [33:0]out;
input s_ready_i_reg;
input \cnt_read_reg[4]_rep__0_0 ;
input si_rs_rready;
input m_axi_rvalid;
input [33:0]in;
input aclk;
input areset_d1;
wire aclk;
wire areset_d1;
wire [4:0]cnt_read;
wire \cnt_read[0]_i_1__1_n_0 ;
wire \cnt_read[1]_i_1__2_n_0 ;
wire \cnt_read[2]_i_1_n_0 ;
wire \cnt_read[3]_i_1__0_n_0 ;
wire \cnt_read[4]_i_1_n_0 ;
wire \cnt_read[4]_i_3__0_n_0 ;
wire \cnt_read[4]_i_5_n_0 ;
wire \cnt_read_reg[0]_rep__0_n_0 ;
wire \cnt_read_reg[0]_rep__1_n_0 ;
wire \cnt_read_reg[0]_rep__2_n_0 ;
wire \cnt_read_reg[0]_rep__3_n_0 ;
wire \cnt_read_reg[0]_rep_n_0 ;
wire \cnt_read_reg[1]_rep__0_n_0 ;
wire \cnt_read_reg[1]_rep__1_n_0 ;
wire \cnt_read_reg[1]_rep__2_n_0 ;
wire \cnt_read_reg[1]_rep_n_0 ;
wire \cnt_read_reg[2]_rep__0_n_0 ;
wire \cnt_read_reg[2]_rep__1_n_0 ;
wire \cnt_read_reg[2]_rep__2_n_0 ;
wire \cnt_read_reg[2]_rep_n_0 ;
wire \cnt_read_reg[3]_rep__0_n_0 ;
wire \cnt_read_reg[3]_rep__1_n_0 ;
wire \cnt_read_reg[3]_rep_n_0 ;
wire \cnt_read_reg[4]_rep__0_0 ;
wire \cnt_read_reg[4]_rep__0_n_0 ;
wire \cnt_read_reg[4]_rep__1_n_0 ;
wire \cnt_read_reg[4]_rep__2_0 ;
wire \cnt_read_reg[4]_rep__2_1 ;
wire \cnt_read_reg[4]_rep__2_2 ;
wire \cnt_read_reg[4]_rep_n_0 ;
wire [33:0]in;
wire m_axi_rready;
wire m_axi_rvalid;
wire [33:0]out;
wire s_ready_i_reg;
wire si_rs_rready;
wire \state_reg[1]_rep ;
wire wr_en0;
wire \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ;
LUT3 #(
.INIT(8'h69))
\cnt_read[0]_i_1__1
(.I0(\cnt_read_reg[0]_rep__2_n_0 ),
.I1(s_ready_i_reg),
.I2(\cnt_read[4]_i_5_n_0 ),
.O(\cnt_read[0]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT4 #(
.INIT(16'h9AA6))
\cnt_read[1]_i_1__2
(.I0(\cnt_read_reg[1]_rep__2_n_0 ),
.I1(\cnt_read_reg[0]_rep__2_n_0 ),
.I2(s_ready_i_reg),
.I3(\cnt_read[4]_i_5_n_0 ),
.O(\cnt_read[1]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT5 #(
.INIT(32'hA9AAAA6A))
\cnt_read[2]_i_1
(.I0(\cnt_read_reg[2]_rep__2_n_0 ),
.I1(\cnt_read_reg[1]_rep__2_n_0 ),
.I2(\cnt_read_reg[0]_rep__2_n_0 ),
.I3(\cnt_read[4]_i_5_n_0 ),
.I4(s_ready_i_reg),
.O(\cnt_read[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAAAAA6AA9AAAAAA))
\cnt_read[3]_i_1__0
(.I0(\cnt_read_reg[4]_rep__2_0 ),
.I1(\cnt_read_reg[2]_rep__2_n_0 ),
.I2(\cnt_read_reg[1]_rep__2_n_0 ),
.I3(\cnt_read[4]_i_5_n_0 ),
.I4(s_ready_i_reg),
.I5(\cnt_read_reg[0]_rep__2_n_0 ),
.O(\cnt_read[3]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h99AA99AA99AA55A6))
\cnt_read[4]_i_1
(.I0(\cnt_read_reg[4]_rep__2_1 ),
.I1(\cnt_read_reg[4]_rep__2_0 ),
.I2(\cnt_read_reg[4]_rep__2_2 ),
.I3(\cnt_read[4]_i_3__0_n_0 ),
.I4(s_ready_i_reg),
.I5(\cnt_read[4]_i_5_n_0 ),
.O(\cnt_read[4]_i_1_n_0 ));
LUT3 #(
.INIT(8'h7F))
\cnt_read[4]_i_2__0
(.I0(\cnt_read_reg[0]_rep__3_n_0 ),
.I1(\cnt_read_reg[1]_rep__2_n_0 ),
.I2(\cnt_read_reg[2]_rep__2_n_0 ),
.O(\cnt_read_reg[4]_rep__2_2 ));
LUT6 #(
.INIT(64'h0000000000100000))
\cnt_read[4]_i_3__0
(.I0(\cnt_read_reg[2]_rep__2_n_0 ),
.I1(\cnt_read_reg[1]_rep__2_n_0 ),
.I2(\cnt_read[4]_i_5_n_0 ),
.I3(\cnt_read_reg[4]_rep__0_0 ),
.I4(si_rs_rready),
.I5(\cnt_read_reg[0]_rep__2_n_0 ),
.O(\cnt_read[4]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'h6000E000FFFFFFFF))
\cnt_read[4]_i_5
(.I0(\cnt_read_reg[2]_rep__2_n_0 ),
.I1(\cnt_read_reg[1]_rep__2_n_0 ),
.I2(\cnt_read_reg[4]_rep__2_1 ),
.I3(\cnt_read_reg[4]_rep__2_0 ),
.I4(\cnt_read_reg[0]_rep__3_n_0 ),
.I5(m_axi_rvalid),
.O(\cnt_read[4]_i_5_n_0 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(cnt_read[0]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep__2_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__3
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep__3_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(cnt_read[1]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep__2_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(cnt_read[2]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep__2_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(cnt_read[3]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(\cnt_read_reg[3]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(\cnt_read_reg[3]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(\cnt_read_reg[3]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(\cnt_read_reg[4]_rep__2_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(cnt_read[4]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep__2_1 ),
.S(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT5 #(
.INIT(32'h9FFF1FFF))
m_axi_rready_INST_0
(.I0(\cnt_read_reg[2]_rep__2_n_0 ),
.I1(\cnt_read_reg[1]_rep__2_n_0 ),
.I2(\cnt_read_reg[4]_rep__2_1 ),
.I3(\cnt_read_reg[4]_rep__2_0 ),
.I4(\cnt_read_reg[0]_rep__3_n_0 ),
.O(m_axi_rready));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][0]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[0]),
.Q(out[0]),
.Q31(\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ));
LUT6 #(
.INIT(64'h8AAA0AAA0AAAAAAA))
\memory_reg[31][0]_srl32_i_1
(.I0(m_axi_rvalid),
.I1(\cnt_read_reg[0]_rep__3_n_0 ),
.I2(\cnt_read_reg[4]_rep__2_0 ),
.I3(\cnt_read_reg[4]_rep__2_1 ),
.I4(\cnt_read_reg[1]_rep__2_n_0 ),
.I5(\cnt_read_reg[2]_rep__2_n_0 ),
.O(wr_en0));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][10]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[10]),
.Q(out[10]),
.Q31(\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][11]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[11]),
.Q(out[11]),
.Q31(\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][12]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[12]),
.Q(out[12]),
.Q31(\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][13]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[13]),
.Q(out[13]),
.Q31(\NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][14]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[14]),
.Q(out[14]),
.Q31(\NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][15]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[15]),
.Q(out[15]),
.Q31(\NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][16]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[16]),
.Q(out[16]),
.Q31(\NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][17]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[17]),
.Q(out[17]),
.Q31(\NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][18]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[18]),
.Q(out[18]),
.Q31(\NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][19]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[19]),
.Q(out[19]),
.Q31(\NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][1]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[1]),
.Q(out[1]),
.Q31(\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][20]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[20]),
.Q(out[20]),
.Q31(\NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][21]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[21]),
.Q(out[21]),
.Q31(\NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][22]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[22]),
.Q(out[22]),
.Q31(\NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][23]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[23]),
.Q(out[23]),
.Q31(\NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][24]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[24]),
.Q(out[24]),
.Q31(\NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][25]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[25]),
.Q(out[25]),
.Q31(\NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][26]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[26]),
.Q(out[26]),
.Q31(\NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][27]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[27]),
.Q(out[27]),
.Q31(\NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][28]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[28]),
.Q(out[28]),
.Q31(\NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][29]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[29]),
.Q(out[29]),
.Q31(\NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][2]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[2]),
.Q(out[2]),
.Q31(\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][30]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[30]),
.Q(out[30]),
.Q31(\NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][31]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[31]),
.Q(out[31]),
.Q31(\NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][32]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[32]),
.Q(out[32]),
.Q31(\NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][33]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[33]),
.Q(out[33]),
.Q31(\NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][3]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[3]),
.Q(out[3]),
.Q31(\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][4]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[4]),
.Q(out[4]),
.Q31(\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][5]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[5]),
.Q(out[5]),
.Q31(\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][6]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[6]),
.Q(out[6]),
.Q31(\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][7]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[7]),
.Q(out[7]),
.Q31(\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][8]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[8]),
.Q(out[8]),
.Q31(\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][9]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[9]),
.Q(out[9]),
.Q31(\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT5 #(
.INIT(32'h40C0C000))
\state[1]_i_4
(.I0(\cnt_read_reg[0]_rep__3_n_0 ),
.I1(\cnt_read_reg[4]_rep__2_0 ),
.I2(\cnt_read_reg[4]_rep__2_1 ),
.I3(\cnt_read_reg[1]_rep__2_n_0 ),
.I4(\cnt_read_reg[2]_rep__2_n_0 ),
.O(\state_reg[1]_rep ));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_17_b2s_simple_fifo" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_simple_fifo__parameterized2
(m_valid_i_reg,
\state_reg[1]_rep ,
\skid_buffer_reg[46] ,
s_ready_i_reg,
r_push_r,
si_rs_rready,
\cnt_read_reg[3]_rep__2 ,
\cnt_read_reg[4]_rep__2 ,
\cnt_read_reg[0]_rep__3 ,
\cnt_read_reg[0]_rep__3_0 ,
in,
aclk,
areset_d1);
output m_valid_i_reg;
output \state_reg[1]_rep ;
output [12:0]\skid_buffer_reg[46] ;
input s_ready_i_reg;
input r_push_r;
input si_rs_rready;
input \cnt_read_reg[3]_rep__2 ;
input \cnt_read_reg[4]_rep__2 ;
input \cnt_read_reg[0]_rep__3 ;
input \cnt_read_reg[0]_rep__3_0 ;
input [12:0]in;
input aclk;
input areset_d1;
wire aclk;
wire areset_d1;
wire [4:0]cnt_read;
wire \cnt_read[0]_i_1__0_n_0 ;
wire \cnt_read[1]_i_1__1_n_0 ;
wire \cnt_read[2]_i_1__0_n_0 ;
wire \cnt_read[3]_i_1_n_0 ;
wire \cnt_read[4]_i_1__0_n_0 ;
wire \cnt_read[4]_i_2_n_0 ;
wire \cnt_read[4]_i_3_n_0 ;
wire \cnt_read_reg[0]_rep__0_n_0 ;
wire \cnt_read_reg[0]_rep__1_n_0 ;
wire \cnt_read_reg[0]_rep__3 ;
wire \cnt_read_reg[0]_rep__3_0 ;
wire \cnt_read_reg[0]_rep_n_0 ;
wire \cnt_read_reg[1]_rep__0_n_0 ;
wire \cnt_read_reg[1]_rep_n_0 ;
wire \cnt_read_reg[2]_rep__0_n_0 ;
wire \cnt_read_reg[2]_rep_n_0 ;
wire \cnt_read_reg[3]_rep__0_n_0 ;
wire \cnt_read_reg[3]_rep__2 ;
wire \cnt_read_reg[3]_rep_n_0 ;
wire \cnt_read_reg[4]_rep__0_n_0 ;
wire \cnt_read_reg[4]_rep__2 ;
wire \cnt_read_reg[4]_rep_n_0 ;
wire [12:0]in;
wire m_valid_i_i_3_n_0;
wire m_valid_i_reg;
wire r_push_r;
wire s_ready_i_reg;
wire si_rs_rready;
wire [12:0]\skid_buffer_reg[46] ;
wire \state_reg[1]_rep ;
wire \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ;
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1__0
(.I0(\cnt_read_reg[0]_rep__0_n_0 ),
.I1(r_push_r),
.I2(s_ready_i_reg),
.O(\cnt_read[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT4 #(
.INIT(16'hDB24))
\cnt_read[1]_i_1__1
(.I0(\cnt_read_reg[0]_rep__0_n_0 ),
.I1(s_ready_i_reg),
.I2(r_push_r),
.I3(\cnt_read_reg[1]_rep__0_n_0 ),
.O(\cnt_read[1]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\cnt_read[2]_i_1__0
(.I0(\cnt_read_reg[2]_rep__0_n_0 ),
.I1(s_ready_i_reg),
.I2(r_push_r),
.I3(\cnt_read_reg[0]_rep__0_n_0 ),
.I4(\cnt_read_reg[1]_rep__0_n_0 ),
.O(\cnt_read[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hFF7F0080FEFF0100))
\cnt_read[3]_i_1
(.I0(\cnt_read_reg[1]_rep__0_n_0 ),
.I1(\cnt_read_reg[0]_rep__0_n_0 ),
.I2(r_push_r),
.I3(s_ready_i_reg),
.I4(\cnt_read_reg[3]_rep__0_n_0 ),
.I5(\cnt_read_reg[2]_rep__0_n_0 ),
.O(\cnt_read[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'h9A999AAA))
\cnt_read[4]_i_1__0
(.I0(\cnt_read_reg[4]_rep__0_n_0 ),
.I1(\cnt_read[4]_i_2_n_0 ),
.I2(\cnt_read_reg[2]_rep__0_n_0 ),
.I3(\cnt_read_reg[3]_rep__0_n_0 ),
.I4(\cnt_read[4]_i_3_n_0 ),
.O(\cnt_read[4]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h2AAAAAAA2AAA2AAA))
\cnt_read[4]_i_2
(.I0(\cnt_read_reg[2]_rep__0_n_0 ),
.I1(\cnt_read_reg[1]_rep__0_n_0 ),
.I2(\cnt_read_reg[0]_rep__1_n_0 ),
.I3(r_push_r),
.I4(m_valid_i_reg),
.I5(si_rs_rready),
.O(\cnt_read[4]_i_2_n_0 ));
LUT5 #(
.INIT(32'h00000004))
\cnt_read[4]_i_3
(.I0(r_push_r),
.I1(si_rs_rready),
.I2(m_valid_i_reg),
.I3(\cnt_read_reg[0]_rep__1_n_0 ),
.I4(\cnt_read_reg[1]_rep__0_n_0 ),
.O(\cnt_read[4]_i_3_n_0 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(cnt_read[0]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(\cnt_read_reg[0]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(\cnt_read_reg[0]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(\cnt_read_reg[0]_rep__1_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(cnt_read[1]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(\cnt_read_reg[1]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(\cnt_read_reg[1]_rep__0_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1__0_n_0 ),
.Q(cnt_read[2]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1__0_n_0 ),
.Q(\cnt_read_reg[2]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1__0_n_0 ),
.Q(\cnt_read_reg[2]_rep__0_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(cnt_read[3]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(\cnt_read_reg[3]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(\cnt_read_reg[3]_rep__0_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1__0_n_0 ),
.Q(cnt_read[4]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1__0_n_0 ),
.Q(\cnt_read_reg[4]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1__0_n_0 ),
.Q(\cnt_read_reg[4]_rep__0_n_0 ),
.S(areset_d1));
LUT6 #(
.INIT(64'h80808080FF808080))
m_valid_i_i_2
(.I0(\cnt_read_reg[4]_rep__0_n_0 ),
.I1(\cnt_read_reg[3]_rep__0_n_0 ),
.I2(m_valid_i_i_3_n_0),
.I3(\cnt_read_reg[3]_rep__2 ),
.I4(\cnt_read_reg[4]_rep__2 ),
.I5(\cnt_read_reg[0]_rep__3 ),
.O(m_valid_i_reg));
LUT3 #(
.INIT(8'h80))
m_valid_i_i_3
(.I0(\cnt_read_reg[2]_rep__0_n_0 ),
.I1(\cnt_read_reg[0]_rep__1_n_0 ),
.I2(\cnt_read_reg[1]_rep__0_n_0 ),
.O(m_valid_i_i_3_n_0));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][0]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[0]),
.Q(\skid_buffer_reg[46] [0]),
.Q31(\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][10]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[10]),
.Q(\skid_buffer_reg[46] [10]),
.Q31(\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][11]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[11]),
.Q(\skid_buffer_reg[46] [11]),
.Q31(\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][12]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[12]),
.Q(\skid_buffer_reg[46] [12]),
.Q31(\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][1]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[1]),
.Q(\skid_buffer_reg[46] [1]),
.Q31(\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][2]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[2]),
.Q(\skid_buffer_reg[46] [2]),
.Q31(\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][3]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[3]),
.Q(\skid_buffer_reg[46] [3]),
.Q31(\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][4]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[4]),
.Q(\skid_buffer_reg[46] [4]),
.Q31(\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][5]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[5]),
.Q(\skid_buffer_reg[46] [5]),
.Q31(\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][6]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[6]),
.Q(\skid_buffer_reg[46] [6]),
.Q31(\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][7]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[7]),
.Q(\skid_buffer_reg[46] [7]),
.Q31(\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][8]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[8]),
.Q(\skid_buffer_reg[46] [8]),
.Q31(\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][9]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[9]),
.Q(\skid_buffer_reg[46] [9]),
.Q31(\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ));
LUT6 #(
.INIT(64'hBFEEAAAAAAAAAAAA))
\state[1]_i_2
(.I0(\cnt_read_reg[0]_rep__3_0 ),
.I1(\cnt_read_reg[2]_rep__0_n_0 ),
.I2(\cnt_read_reg[0]_rep__1_n_0 ),
.I3(\cnt_read_reg[1]_rep__0_n_0 ),
.I4(\cnt_read_reg[3]_rep__0_n_0 ),
.I5(\cnt_read_reg[4]_rep__0_n_0 ),
.O(\state_reg[1]_rep ));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wr_cmd_fsm
(\axlen_cnt_reg[7] ,
\axlen_cnt_reg[7]_0 ,
\axlen_cnt_reg[7]_1 ,
next,
Q,
D,
\wrap_second_len_r_reg[0] ,
\axlen_cnt_reg[0] ,
s_axburst_eq0_reg,
incr_next_pending,
sel_first_i,
s_axburst_eq1_reg,
E,
\axaddr_wrap_reg[11] ,
sel_first_reg,
sel_first_reg_0,
\wrap_cnt_r_reg[3] ,
\axaddr_offset_r_reg[2] ,
\wrap_cnt_r_reg[3]_0 ,
\m_payload_i_reg[0] ,
b_push,
m_axi_awvalid,
s_axburst_eq1_reg_0,
\cnt_read_reg[1]_rep__0 ,
\cnt_read_reg[0]_rep__0 ,
m_axi_awready,
si_rs_awvalid,
\axlen_cnt_reg[7]_2 ,
\wrap_second_len_r_reg[0]_0 ,
\axaddr_offset_r_reg[3] ,
axaddr_offset,
\m_payload_i_reg[46] ,
\axlen_cnt_reg[0]_0 ,
wrap_next_pending,
next_pending_r_reg,
\m_payload_i_reg[47] ,
sel_first,
areset_d1,
sel_first_0,
sel_first_reg_1,
\axaddr_offset_r_reg[3]_0 ,
\m_payload_i_reg[5] ,
aclk);
output \axlen_cnt_reg[7] ;
output \axlen_cnt_reg[7]_0 ;
output \axlen_cnt_reg[7]_1 ;
output next;
output [1:0]Q;
output [0:0]D;
output [0:0]\wrap_second_len_r_reg[0] ;
output [0:0]\axlen_cnt_reg[0] ;
output s_axburst_eq0_reg;
output incr_next_pending;
output sel_first_i;
output s_axburst_eq1_reg;
output [0:0]E;
output [0:0]\axaddr_wrap_reg[11] ;
output sel_first_reg;
output sel_first_reg_0;
output \wrap_cnt_r_reg[3] ;
output [0:0]\axaddr_offset_r_reg[2] ;
output \wrap_cnt_r_reg[3]_0 ;
output [0:0]\m_payload_i_reg[0] ;
output b_push;
output m_axi_awvalid;
input s_axburst_eq1_reg_0;
input \cnt_read_reg[1]_rep__0 ;
input \cnt_read_reg[0]_rep__0 ;
input m_axi_awready;
input si_rs_awvalid;
input \axlen_cnt_reg[7]_2 ;
input [0:0]\wrap_second_len_r_reg[0]_0 ;
input \axaddr_offset_r_reg[3] ;
input [0:0]axaddr_offset;
input [2:0]\m_payload_i_reg[46] ;
input [0:0]\axlen_cnt_reg[0]_0 ;
input wrap_next_pending;
input next_pending_r_reg;
input \m_payload_i_reg[47] ;
input sel_first;
input areset_d1;
input sel_first_0;
input sel_first_reg_1;
input [1:0]\axaddr_offset_r_reg[3]_0 ;
input \m_payload_i_reg[5] ;
input aclk;
wire [0:0]D;
wire [0:0]E;
wire [1:0]Q;
wire aclk;
wire areset_d1;
wire [0:0]axaddr_offset;
wire [0:0]\axaddr_offset_r_reg[2] ;
wire \axaddr_offset_r_reg[3] ;
wire [1:0]\axaddr_offset_r_reg[3]_0 ;
wire [0:0]\axaddr_wrap_reg[11] ;
wire [0:0]\axlen_cnt_reg[0] ;
wire [0:0]\axlen_cnt_reg[0]_0 ;
wire \axlen_cnt_reg[7] ;
wire \axlen_cnt_reg[7]_0 ;
wire \axlen_cnt_reg[7]_1 ;
wire \axlen_cnt_reg[7]_2 ;
wire b_push;
wire \cnt_read_reg[0]_rep__0 ;
wire \cnt_read_reg[1]_rep__0 ;
wire incr_next_pending;
wire m_axi_awready;
wire m_axi_awvalid;
wire [0:0]\m_payload_i_reg[0] ;
wire [2:0]\m_payload_i_reg[46] ;
wire \m_payload_i_reg[47] ;
wire \m_payload_i_reg[5] ;
wire next;
wire next_pending_r_reg;
wire s_axburst_eq0_reg;
wire s_axburst_eq1_reg;
wire s_axburst_eq1_reg_0;
wire sel_first;
wire sel_first_0;
wire sel_first_i;
wire sel_first_reg;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire si_rs_awvalid;
wire \state[0]_i_1_n_0 ;
wire \state[0]_i_2_n_0 ;
wire \state[1]_i_1__0_n_0 ;
wire \wrap_cnt_r_reg[3] ;
wire \wrap_cnt_r_reg[3]_0 ;
wire wrap_next_pending;
wire [0:0]\wrap_second_len_r_reg[0] ;
wire [0:0]\wrap_second_len_r_reg[0]_0 ;
LUT6 #(
.INIT(64'hAAAAACAAAAAAA0AA))
\axaddr_offset_r[2]_i_1
(.I0(\axaddr_offset_r_reg[3]_0 [0]),
.I1(\m_payload_i_reg[46] [2]),
.I2(\axlen_cnt_reg[7]_0 ),
.I3(si_rs_awvalid),
.I4(\axlen_cnt_reg[7] ),
.I5(\m_payload_i_reg[5] ),
.O(\axaddr_offset_r_reg[2] ));
LUT6 #(
.INIT(64'h0400FFFF04000400))
\axlen_cnt[0]_i_1__0
(.I0(Q[1]),
.I1(si_rs_awvalid),
.I2(Q[0]),
.I3(\m_payload_i_reg[46] [1]),
.I4(\axlen_cnt_reg[0]_0 ),
.I5(\axlen_cnt_reg[7]_2 ),
.O(\axlen_cnt_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair109" *)
LUT4 #(
.INIT(16'hFF04))
\axlen_cnt[3]_i_1__0
(.I0(Q[0]),
.I1(si_rs_awvalid),
.I2(Q[1]),
.I3(next),
.O(\axaddr_wrap_reg[11] ));
(* SOFT_HLUTNM = "soft_lutpair108" *)
LUT5 #(
.INIT(32'h0000FF04))
\axlen_cnt[7]_i_1__0
(.I0(\axlen_cnt_reg[7]_0 ),
.I1(si_rs_awvalid),
.I2(\axlen_cnt_reg[7] ),
.I3(next),
.I4(\axlen_cnt_reg[7]_2 ),
.O(\axlen_cnt_reg[7]_1 ));
LUT2 #(
.INIT(4'h2))
m_axi_awvalid_INST_0
(.I0(\axlen_cnt_reg[7]_0 ),
.I1(\axlen_cnt_reg[7] ),
.O(m_axi_awvalid));
LUT2 #(
.INIT(4'hB))
\m_payload_i[31]_i_1
(.I0(b_push),
.I1(si_rs_awvalid),
.O(\m_payload_i_reg[0] ));
LUT6 #(
.INIT(64'h88008888A800A8A8))
\memory_reg[3][0]_srl4_i_1
(.I0(\axlen_cnt_reg[7]_0 ),
.I1(\axlen_cnt_reg[7] ),
.I2(m_axi_awready),
.I3(\cnt_read_reg[0]_rep__0 ),
.I4(\cnt_read_reg[1]_rep__0 ),
.I5(s_axburst_eq1_reg_0),
.O(b_push));
LUT5 #(
.INIT(32'hFFFFF404))
next_pending_r_i_1
(.I0(E),
.I1(next_pending_r_reg),
.I2(next),
.I3(\axlen_cnt_reg[7]_2 ),
.I4(\m_payload_i_reg[47] ),
.O(incr_next_pending));
LUT6 #(
.INIT(64'hF3F3FFFF51000000))
next_pending_r_i_2
(.I0(s_axburst_eq1_reg_0),
.I1(\cnt_read_reg[1]_rep__0 ),
.I2(\cnt_read_reg[0]_rep__0 ),
.I3(m_axi_awready),
.I4(\axlen_cnt_reg[7]_0 ),
.I5(\axlen_cnt_reg[7] ),
.O(next));
(* SOFT_HLUTNM = "soft_lutpair110" *)
LUT4 #(
.INIT(16'hBA8A))
s_axburst_eq0_i_1
(.I0(incr_next_pending),
.I1(sel_first_i),
.I2(\m_payload_i_reg[46] [0]),
.I3(wrap_next_pending),
.O(s_axburst_eq0_reg));
(* SOFT_HLUTNM = "soft_lutpair110" *)
LUT4 #(
.INIT(16'hFE02))
s_axburst_eq1_i_1
(.I0(incr_next_pending),
.I1(\m_payload_i_reg[46] [0]),
.I2(sel_first_i),
.I3(wrap_next_pending),
.O(s_axburst_eq1_reg));
LUT6 #(
.INIT(64'hFFFFFFFF44444F44))
sel_first_i_1
(.I0(next),
.I1(sel_first),
.I2(Q[1]),
.I3(si_rs_awvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg));
LUT6 #(
.INIT(64'hFFFFFFFF44444F44))
sel_first_i_1__0
(.I0(next),
.I1(sel_first_0),
.I2(Q[1]),
.I3(si_rs_awvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg_0));
LUT6 #(
.INIT(64'hFF04FFFFFF04FF04))
sel_first_i_1__1
(.I0(\axlen_cnt_reg[7] ),
.I1(si_rs_awvalid),
.I2(\axlen_cnt_reg[7]_0 ),
.I3(areset_d1),
.I4(next),
.I5(sel_first_reg_1),
.O(sel_first_i));
(* SOFT_HLUTNM = "soft_lutpair109" *)
LUT4 #(
.INIT(16'hBBBA))
\state[0]_i_1
(.I0(\state[0]_i_2_n_0 ),
.I1(Q[0]),
.I2(si_rs_awvalid),
.I3(Q[1]),
.O(\state[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h00F000F055750000))
\state[0]_i_2
(.I0(m_axi_awready),
.I1(s_axburst_eq1_reg_0),
.I2(\cnt_read_reg[1]_rep__0 ),
.I3(\cnt_read_reg[0]_rep__0 ),
.I4(\axlen_cnt_reg[7]_0 ),
.I5(\axlen_cnt_reg[7] ),
.O(\state[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0C0CAE0000000000))
\state[1]_i_1__0
(.I0(s_axburst_eq1_reg_0),
.I1(\cnt_read_reg[1]_rep__0 ),
.I2(\cnt_read_reg[0]_rep__0 ),
.I3(m_axi_awready),
.I4(\axlen_cnt_reg[7] ),
.I5(\axlen_cnt_reg[7]_0 ),
.O(\state[1]_i_1__0_n_0 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\state[0]_i_1_n_0 ),
.Q(Q[0]),
.R(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(\state[0]_i_1_n_0 ),
.Q(\axlen_cnt_reg[7]_0 ),
.R(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\state[1]_i_1__0_n_0 ),
.Q(Q[1]),
.R(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\state[1]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg[7] ),
.R(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair108" *)
LUT3 #(
.INIT(8'h04))
\wrap_boundary_axaddr_r[11]_i_1
(.I0(\axlen_cnt_reg[7] ),
.I1(si_rs_awvalid),
.I2(\axlen_cnt_reg[7]_0 ),
.O(E));
LUT6 #(
.INIT(64'hAA8A5575AA8A5545))
\wrap_cnt_r[0]_i_1
(.I0(\wrap_second_len_r_reg[0]_0 ),
.I1(Q[0]),
.I2(si_rs_awvalid),
.I3(Q[1]),
.I4(\axaddr_offset_r_reg[3] ),
.I5(axaddr_offset),
.O(D));
(* SOFT_HLUTNM = "soft_lutpair111" *)
LUT4 #(
.INIT(16'hAA8A))
\wrap_cnt_r[3]_i_4
(.I0(\axaddr_offset_r_reg[3]_0 [1]),
.I1(\axlen_cnt_reg[7]_0 ),
.I2(si_rs_awvalid),
.I3(\axlen_cnt_reg[7] ),
.O(\wrap_cnt_r_reg[3] ));
(* SOFT_HLUTNM = "soft_lutpair111" *)
LUT4 #(
.INIT(16'hAA8A))
\wrap_cnt_r[3]_i_6
(.I0(\axaddr_offset_r_reg[3]_0 [0]),
.I1(\axlen_cnt_reg[7]_0 ),
.I2(si_rs_awvalid),
.I3(\axlen_cnt_reg[7] ),
.O(\wrap_cnt_r_reg[3]_0 ));
LUT6 #(
.INIT(64'hAA8AAA8AAA8AAABA))
\wrap_second_len_r[0]_i_1
(.I0(\wrap_second_len_r_reg[0]_0 ),
.I1(Q[0]),
.I2(si_rs_awvalid),
.I3(Q[1]),
.I4(\axaddr_offset_r_reg[3] ),
.I5(axaddr_offset),
.O(\wrap_second_len_r_reg[0] ));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wrap_cmd
(wrap_next_pending,
sel_first_reg_0,
\wrap_cnt_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
m_axi_awaddr,
\axaddr_offset_r_reg[3]_0 ,
aclk,
sel_first_reg_1,
E,
\m_payload_i_reg[47] ,
\state_reg[1] ,
si_rs_awvalid,
\axaddr_offset_r_reg[3]_1 ,
D,
\m_payload_i_reg[47]_0 ,
next,
sel_first_reg_2,
\axaddr_incr_reg[11] ,
sel_first_reg_3,
\axaddr_offset_r_reg[3]_2 ,
\wrap_second_len_r_reg[3]_1 ,
\state_reg[0] ,
\wrap_second_len_r_reg[3]_2 ,
\m_payload_i_reg[6] );
output wrap_next_pending;
output sel_first_reg_0;
output \wrap_cnt_r_reg[3]_0 ;
output [3:0]\wrap_second_len_r_reg[3]_0 ;
output [11:0]m_axi_awaddr;
output [3:0]\axaddr_offset_r_reg[3]_0 ;
input aclk;
input sel_first_reg_1;
input [0:0]E;
input [18:0]\m_payload_i_reg[47] ;
input [1:0]\state_reg[1] ;
input si_rs_awvalid;
input \axaddr_offset_r_reg[3]_1 ;
input [3:0]D;
input \m_payload_i_reg[47]_0 ;
input next;
input sel_first_reg_2;
input [10:0]\axaddr_incr_reg[11] ;
input sel_first_reg_3;
input \axaddr_offset_r_reg[3]_2 ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [0:0]\state_reg[0] ;
input [2:0]\wrap_second_len_r_reg[3]_2 ;
input [6:0]\m_payload_i_reg[6] ;
wire [3:0]D;
wire [0:0]E;
wire aclk;
wire [10:0]\axaddr_incr_reg[11] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire \axaddr_offset_r_reg[3]_1 ;
wire \axaddr_offset_r_reg[3]_2 ;
wire [11:0]axaddr_wrap;
wire [11:0]axaddr_wrap0;
wire \axaddr_wrap[0]_i_1_n_0 ;
wire \axaddr_wrap[10]_i_1_n_0 ;
wire \axaddr_wrap[11]_i_1_n_0 ;
wire \axaddr_wrap[11]_i_2_n_0 ;
wire \axaddr_wrap[11]_i_4_n_0 ;
wire \axaddr_wrap[1]_i_1_n_0 ;
wire \axaddr_wrap[2]_i_1_n_0 ;
wire \axaddr_wrap[3]_i_1_n_0 ;
wire \axaddr_wrap[3]_i_3_n_0 ;
wire \axaddr_wrap[3]_i_4_n_0 ;
wire \axaddr_wrap[3]_i_5_n_0 ;
wire \axaddr_wrap[3]_i_6_n_0 ;
wire \axaddr_wrap[4]_i_1_n_0 ;
wire \axaddr_wrap[5]_i_1_n_0 ;
wire \axaddr_wrap[6]_i_1_n_0 ;
wire \axaddr_wrap[7]_i_1_n_0 ;
wire \axaddr_wrap[8]_i_1_n_0 ;
wire \axaddr_wrap[9]_i_1_n_0 ;
wire \axaddr_wrap_reg[11]_i_3_n_1 ;
wire \axaddr_wrap_reg[11]_i_3_n_2 ;
wire \axaddr_wrap_reg[11]_i_3_n_3 ;
wire \axaddr_wrap_reg[3]_i_2_n_0 ;
wire \axaddr_wrap_reg[3]_i_2_n_1 ;
wire \axaddr_wrap_reg[3]_i_2_n_2 ;
wire \axaddr_wrap_reg[3]_i_2_n_3 ;
wire \axaddr_wrap_reg[7]_i_2_n_0 ;
wire \axaddr_wrap_reg[7]_i_2_n_1 ;
wire \axaddr_wrap_reg[7]_i_2_n_2 ;
wire \axaddr_wrap_reg[7]_i_2_n_3 ;
wire \axlen_cnt[0]_i_1_n_0 ;
wire \axlen_cnt[1]_i_1_n_0 ;
wire \axlen_cnt[2]_i_1__0_n_0 ;
wire \axlen_cnt[3]_i_1_n_0 ;
wire \axlen_cnt_reg_n_0_[0] ;
wire \axlen_cnt_reg_n_0_[1] ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire [11:0]m_axi_awaddr;
wire [18:0]\m_payload_i_reg[47] ;
wire \m_payload_i_reg[47]_0 ;
wire [6:0]\m_payload_i_reg[6] ;
wire next;
wire next_pending_r_i_2__1_n_0;
wire next_pending_r_reg_n_0;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire sel_first_reg_3;
wire si_rs_awvalid;
wire [0:0]\state_reg[0] ;
wire [1:0]\state_reg[1] ;
wire [11:0]wrap_boundary_axaddr_r;
wire [1:1]wrap_cnt;
wire [3:0]wrap_cnt_r;
wire \wrap_cnt_r_reg[3]_0 ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
wire [2:0]\wrap_second_len_r_reg[3]_2 ;
wire [3:3]\NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED ;
FDRE \axaddr_offset_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(D[0]),
.Q(\axaddr_offset_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(D[1]),
.Q(\axaddr_offset_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(D[2]),
.Q(\axaddr_offset_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(D[3]),
.Q(\axaddr_offset_r_reg[3]_0 [3]),
.R(1'b0));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[0]_i_1
(.I0(wrap_boundary_axaddr_r[0]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[0]),
.I3(next),
.I4(\m_payload_i_reg[47] [0]),
.O(\axaddr_wrap[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[10]_i_1
(.I0(wrap_boundary_axaddr_r[10]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[10]),
.I3(next),
.I4(\m_payload_i_reg[47] [10]),
.O(\axaddr_wrap[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[11]_i_1
(.I0(wrap_boundary_axaddr_r[11]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[11]),
.I3(next),
.I4(\m_payload_i_reg[47] [11]),
.O(\axaddr_wrap[11]_i_1_n_0 ));
LUT3 #(
.INIT(8'h41))
\axaddr_wrap[11]_i_2
(.I0(\axaddr_wrap[11]_i_4_n_0 ),
.I1(wrap_cnt_r[3]),
.I2(\axlen_cnt_reg_n_0_[3] ),
.O(\axaddr_wrap[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6FF6FFFFFFFF6FF6))
\axaddr_wrap[11]_i_4
(.I0(wrap_cnt_r[0]),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(wrap_cnt_r[1]),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(wrap_cnt_r[2]),
.O(\axaddr_wrap[11]_i_4_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[1]_i_1
(.I0(wrap_boundary_axaddr_r[1]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[1]),
.I3(next),
.I4(\m_payload_i_reg[47] [1]),
.O(\axaddr_wrap[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[2]_i_1
(.I0(wrap_boundary_axaddr_r[2]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[2]),
.I3(next),
.I4(\m_payload_i_reg[47] [2]),
.O(\axaddr_wrap[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[3]_i_1
(.I0(wrap_boundary_axaddr_r[3]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[3]),
.I3(next),
.I4(\m_payload_i_reg[47] [3]),
.O(\axaddr_wrap[3]_i_1_n_0 ));
LUT3 #(
.INIT(8'h6A))
\axaddr_wrap[3]_i_3
(.I0(axaddr_wrap[3]),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_3_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_4
(.I0(axaddr_wrap[2]),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_4_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_5
(.I0(axaddr_wrap[1]),
.I1(\m_payload_i_reg[47] [13]),
.I2(\m_payload_i_reg[47] [12]),
.O(\axaddr_wrap[3]_i_5_n_0 ));
LUT3 #(
.INIT(8'hA9))
\axaddr_wrap[3]_i_6
(.I0(axaddr_wrap[0]),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[4]_i_1
(.I0(wrap_boundary_axaddr_r[4]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[4]),
.I3(next),
.I4(\m_payload_i_reg[47] [4]),
.O(\axaddr_wrap[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[5]_i_1
(.I0(wrap_boundary_axaddr_r[5]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[5]),
.I3(next),
.I4(\m_payload_i_reg[47] [5]),
.O(\axaddr_wrap[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[6]_i_1
(.I0(wrap_boundary_axaddr_r[6]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[6]),
.I3(next),
.I4(\m_payload_i_reg[47] [6]),
.O(\axaddr_wrap[6]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[7]_i_1
(.I0(wrap_boundary_axaddr_r[7]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[7]),
.I3(next),
.I4(\m_payload_i_reg[47] [7]),
.O(\axaddr_wrap[7]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[8]_i_1
(.I0(wrap_boundary_axaddr_r[8]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[8]),
.I3(next),
.I4(\m_payload_i_reg[47] [8]),
.O(\axaddr_wrap[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[9]_i_1
(.I0(wrap_boundary_axaddr_r[9]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[9]),
.I3(next),
.I4(\m_payload_i_reg[47] [9]),
.O(\axaddr_wrap[9]_i_1_n_0 ));
FDRE \axaddr_wrap_reg[0]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[0]_i_1_n_0 ),
.Q(axaddr_wrap[0]),
.R(1'b0));
FDRE \axaddr_wrap_reg[10]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[10]_i_1_n_0 ),
.Q(axaddr_wrap[10]),
.R(1'b0));
FDRE \axaddr_wrap_reg[11]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[11]_i_1_n_0 ),
.Q(axaddr_wrap[11]),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[11]_i_3
(.CI(\axaddr_wrap_reg[7]_i_2_n_0 ),
.CO({\NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED [3],\axaddr_wrap_reg[11]_i_3_n_1 ,\axaddr_wrap_reg[11]_i_3_n_2 ,\axaddr_wrap_reg[11]_i_3_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(axaddr_wrap0[11:8]),
.S(axaddr_wrap[11:8]));
FDRE \axaddr_wrap_reg[1]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[1]_i_1_n_0 ),
.Q(axaddr_wrap[1]),
.R(1'b0));
FDRE \axaddr_wrap_reg[2]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[2]_i_1_n_0 ),
.Q(axaddr_wrap[2]),
.R(1'b0));
FDRE \axaddr_wrap_reg[3]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[3]_i_1_n_0 ),
.Q(axaddr_wrap[3]),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[3]_i_2
(.CI(1'b0),
.CO({\axaddr_wrap_reg[3]_i_2_n_0 ,\axaddr_wrap_reg[3]_i_2_n_1 ,\axaddr_wrap_reg[3]_i_2_n_2 ,\axaddr_wrap_reg[3]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(axaddr_wrap[3:0]),
.O(axaddr_wrap0[3:0]),
.S({\axaddr_wrap[3]_i_3_n_0 ,\axaddr_wrap[3]_i_4_n_0 ,\axaddr_wrap[3]_i_5_n_0 ,\axaddr_wrap[3]_i_6_n_0 }));
FDRE \axaddr_wrap_reg[4]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[4]_i_1_n_0 ),
.Q(axaddr_wrap[4]),
.R(1'b0));
FDRE \axaddr_wrap_reg[5]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[5]_i_1_n_0 ),
.Q(axaddr_wrap[5]),
.R(1'b0));
FDRE \axaddr_wrap_reg[6]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[6]_i_1_n_0 ),
.Q(axaddr_wrap[6]),
.R(1'b0));
FDRE \axaddr_wrap_reg[7]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[7]_i_1_n_0 ),
.Q(axaddr_wrap[7]),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[7]_i_2
(.CI(\axaddr_wrap_reg[3]_i_2_n_0 ),
.CO({\axaddr_wrap_reg[7]_i_2_n_0 ,\axaddr_wrap_reg[7]_i_2_n_1 ,\axaddr_wrap_reg[7]_i_2_n_2 ,\axaddr_wrap_reg[7]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(axaddr_wrap0[7:4]),
.S(axaddr_wrap[7:4]));
FDRE \axaddr_wrap_reg[8]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[8]_i_1_n_0 ),
.Q(axaddr_wrap[8]),
.R(1'b0));
FDRE \axaddr_wrap_reg[9]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[9]_i_1_n_0 ),
.Q(axaddr_wrap[9]),
.R(1'b0));
LUT6 #(
.INIT(64'hA3A3A3A3A3A3A3A0))
\axlen_cnt[0]_i_1
(.I0(\m_payload_i_reg[47] [15]),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(E),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\axlen_cnt_reg_n_0_[1] ),
.O(\axlen_cnt[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAC3AAC3AAC3AAC0))
\axlen_cnt[1]_i_1
(.I0(\m_payload_i_reg[47] [16]),
.I1(\axlen_cnt_reg_n_0_[1] ),
.I2(\axlen_cnt_reg_n_0_[0] ),
.I3(E),
.I4(\axlen_cnt_reg_n_0_[3] ),
.I5(\axlen_cnt_reg_n_0_[2] ),
.O(\axlen_cnt[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFA9A80000A9A8))
\axlen_cnt[2]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(E),
.I5(\m_payload_i_reg[47] [17]),
.O(\axlen_cnt[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAACCCCCCC0))
\axlen_cnt[3]_i_1
(.I0(\m_payload_i_reg[47] [18]),
.I1(\axlen_cnt_reg_n_0_[3] ),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\axlen_cnt_reg_n_0_[1] ),
.I4(\axlen_cnt_reg_n_0_[0] ),
.I5(E),
.O(\axlen_cnt[3]_i_1_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[0]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[0] ),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[1]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[2]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[3]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[0]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[0]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [0]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [0]),
.O(m_axi_awaddr[0]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[10]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[10]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [10]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [9]),
.O(m_axi_awaddr[10]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[11]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[11]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [11]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [10]),
.O(m_axi_awaddr[11]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[1]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[1]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [1]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [1]),
.O(m_axi_awaddr[1]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[2]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[2]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [2]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [2]),
.O(m_axi_awaddr[2]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[3]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[3]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [3]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [3]),
.O(m_axi_awaddr[3]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[4]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[4]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [4]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [4]),
.O(m_axi_awaddr[4]));
LUT5 #(
.INIT(32'hB8FFB800))
\m_axi_awaddr[5]_INST_0
(.I0(\m_payload_i_reg[47] [5]),
.I1(sel_first_reg_0),
.I2(axaddr_wrap[5]),
.I3(\m_payload_i_reg[47] [14]),
.I4(sel_first_reg_3),
.O(m_axi_awaddr[5]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[6]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[6]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [6]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [5]),
.O(m_axi_awaddr[6]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[7]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[7]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [7]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [6]),
.O(m_axi_awaddr[7]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[8]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[8]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [8]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [7]),
.O(m_axi_awaddr[8]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[9]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[9]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [9]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [8]),
.O(m_axi_awaddr[9]));
LUT5 #(
.INIT(32'hFEAAFEAE))
next_pending_r_i_1__0
(.I0(\m_payload_i_reg[47]_0 ),
.I1(next_pending_r_reg_n_0),
.I2(next),
.I3(next_pending_r_i_2__1_n_0),
.I4(E),
.O(wrap_next_pending));
LUT6 #(
.INIT(64'hFBFBFBFBFBFBFB00))
next_pending_r_i_2__1
(.I0(\state_reg[1] [0]),
.I1(si_rs_awvalid),
.I2(\state_reg[1] [1]),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\axlen_cnt_reg_n_0_[1] ),
.O(next_pending_r_i_2__1_n_0));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(wrap_next_pending),
.Q(next_pending_r_reg_n_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_1),
.Q(sel_first_reg_0),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[0]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [0]),
.Q(wrap_boundary_axaddr_r[0]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[10]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [10]),
.Q(wrap_boundary_axaddr_r[10]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[11]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [11]),
.Q(wrap_boundary_axaddr_r[11]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[1]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [1]),
.Q(wrap_boundary_axaddr_r[1]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[2]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [2]),
.Q(wrap_boundary_axaddr_r[2]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[3]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [3]),
.Q(wrap_boundary_axaddr_r[3]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[4]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [4]),
.Q(wrap_boundary_axaddr_r[4]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[5]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [5]),
.Q(wrap_boundary_axaddr_r[5]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[6]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [6]),
.Q(wrap_boundary_axaddr_r[6]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[7]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [7]),
.Q(wrap_boundary_axaddr_r[7]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[8]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [8]),
.Q(wrap_boundary_axaddr_r[8]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[9]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [9]),
.Q(wrap_boundary_axaddr_r[9]),
.R(1'b0));
LUT5 #(
.INIT(32'h3D310E02))
\wrap_cnt_r[1]_i_1
(.I0(\wrap_second_len_r_reg[3]_0 [0]),
.I1(E),
.I2(\axaddr_offset_r_reg[3]_2 ),
.I3(D[1]),
.I4(\wrap_second_len_r_reg[3]_0 [1]),
.O(wrap_cnt));
LUT6 #(
.INIT(64'h000CAAA8000C0000))
\wrap_cnt_r[3]_i_2
(.I0(\wrap_second_len_r_reg[3]_0 [1]),
.I1(\axaddr_offset_r_reg[3]_1 ),
.I2(D[1]),
.I3(D[0]),
.I4(E),
.I5(\wrap_second_len_r_reg[3]_0 [0]),
.O(\wrap_cnt_r_reg[3]_0 ));
FDRE \wrap_cnt_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [0]),
.Q(wrap_cnt_r[0]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(wrap_cnt),
.Q(wrap_cnt_r[1]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [1]),
.Q(wrap_cnt_r[2]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [2]),
.Q(wrap_cnt_r[3]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [0]),
.Q(\wrap_second_len_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [1]),
.Q(\wrap_second_len_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [2]),
.Q(\wrap_second_len_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [3]),
.Q(\wrap_second_len_r_reg[3]_0 [3]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_17_b2s_wrap_cmd" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_b2s_wrap_cmd_3
(sel_first_reg_0,
\wrap_cnt_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
s_axburst_eq0_reg,
s_axburst_eq1_reg,
m_axi_araddr,
\axaddr_offset_r_reg[3]_0 ,
aclk,
sel_first_reg_1,
E,
Q,
\state_reg[1] ,
si_rs_arvalid,
\axaddr_offset_r_reg[3]_1 ,
D,
sel_first_i,
incr_next_pending,
\m_payload_i_reg[47] ,
\state_reg[1]_rep ,
sel_first_reg_2,
\axaddr_incr_reg[11] ,
sel_first_reg_3,
sel_first_reg_4,
sel_first_reg_5,
sel_first_reg_6,
\axaddr_offset_r_reg[3]_2 ,
\wrap_second_len_r_reg[3]_1 ,
m_valid_i_reg,
\wrap_second_len_r_reg[3]_2 ,
\m_payload_i_reg[6] );
output sel_first_reg_0;
output \wrap_cnt_r_reg[3]_0 ;
output [3:0]\wrap_second_len_r_reg[3]_0 ;
output s_axburst_eq0_reg;
output s_axburst_eq1_reg;
output [11:0]m_axi_araddr;
output [3:0]\axaddr_offset_r_reg[3]_0 ;
input aclk;
input sel_first_reg_1;
input [0:0]E;
input [18:0]Q;
input [1:0]\state_reg[1] ;
input si_rs_arvalid;
input \axaddr_offset_r_reg[3]_1 ;
input [3:0]D;
input sel_first_i;
input incr_next_pending;
input \m_payload_i_reg[47] ;
input \state_reg[1]_rep ;
input sel_first_reg_2;
input [7:0]\axaddr_incr_reg[11] ;
input sel_first_reg_3;
input sel_first_reg_4;
input sel_first_reg_5;
input sel_first_reg_6;
input \axaddr_offset_r_reg[3]_2 ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [0:0]m_valid_i_reg;
input [2:0]\wrap_second_len_r_reg[3]_2 ;
input [6:0]\m_payload_i_reg[6] ;
wire [3:0]D;
wire [0:0]E;
wire [18:0]Q;
wire aclk;
wire [7:0]\axaddr_incr_reg[11] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire \axaddr_offset_r_reg[3]_1 ;
wire \axaddr_offset_r_reg[3]_2 ;
wire \axaddr_wrap[0]_i_1__0_n_0 ;
wire \axaddr_wrap[10]_i_1__0_n_0 ;
wire \axaddr_wrap[11]_i_1__0_n_0 ;
wire \axaddr_wrap[11]_i_2__0_n_0 ;
wire \axaddr_wrap[11]_i_4__0_n_0 ;
wire \axaddr_wrap[1]_i_1__0_n_0 ;
wire \axaddr_wrap[2]_i_1__0_n_0 ;
wire \axaddr_wrap[3]_i_1__0_n_0 ;
wire \axaddr_wrap[3]_i_3_n_0 ;
wire \axaddr_wrap[3]_i_4_n_0 ;
wire \axaddr_wrap[3]_i_5_n_0 ;
wire \axaddr_wrap[3]_i_6_n_0 ;
wire \axaddr_wrap[4]_i_1__0_n_0 ;
wire \axaddr_wrap[5]_i_1__0_n_0 ;
wire \axaddr_wrap[6]_i_1__0_n_0 ;
wire \axaddr_wrap[7]_i_1__0_n_0 ;
wire \axaddr_wrap[8]_i_1__0_n_0 ;
wire \axaddr_wrap[9]_i_1__0_n_0 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_1 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_2 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_3 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_4 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_5 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_6 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_7 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_0 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_1 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_2 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_3 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_4 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_5 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_6 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_7 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_0 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_1 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_2 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_3 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_4 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_5 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_6 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_7 ;
wire \axaddr_wrap_reg_n_0_[0] ;
wire \axaddr_wrap_reg_n_0_[10] ;
wire \axaddr_wrap_reg_n_0_[11] ;
wire \axaddr_wrap_reg_n_0_[1] ;
wire \axaddr_wrap_reg_n_0_[2] ;
wire \axaddr_wrap_reg_n_0_[3] ;
wire \axaddr_wrap_reg_n_0_[4] ;
wire \axaddr_wrap_reg_n_0_[5] ;
wire \axaddr_wrap_reg_n_0_[6] ;
wire \axaddr_wrap_reg_n_0_[7] ;
wire \axaddr_wrap_reg_n_0_[8] ;
wire \axaddr_wrap_reg_n_0_[9] ;
wire \axlen_cnt[0]_i_1__1_n_0 ;
wire \axlen_cnt[1]_i_1__2_n_0 ;
wire \axlen_cnt[2]_i_1__2_n_0 ;
wire \axlen_cnt[3]_i_1__1_n_0 ;
wire \axlen_cnt_reg_n_0_[0] ;
wire \axlen_cnt_reg_n_0_[1] ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire incr_next_pending;
wire [11:0]m_axi_araddr;
wire \m_payload_i_reg[47] ;
wire [6:0]\m_payload_i_reg[6] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_i_2__2_n_0;
wire next_pending_r_reg_n_0;
wire s_axburst_eq0_reg;
wire s_axburst_eq1_reg;
wire sel_first_i;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire sel_first_reg_3;
wire sel_first_reg_4;
wire sel_first_reg_5;
wire sel_first_reg_6;
wire si_rs_arvalid;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_rep ;
wire \wrap_boundary_axaddr_r_reg_n_0_[0] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[10] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[11] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[1] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[2] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[3] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[4] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[5] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[6] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[7] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[8] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[9] ;
wire \wrap_cnt_r[1]_i_1__0_n_0 ;
wire \wrap_cnt_r_reg[3]_0 ;
wire \wrap_cnt_r_reg_n_0_[0] ;
wire \wrap_cnt_r_reg_n_0_[1] ;
wire \wrap_cnt_r_reg_n_0_[2] ;
wire \wrap_cnt_r_reg_n_0_[3] ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
wire [2:0]\wrap_second_len_r_reg[3]_2 ;
wire [3:3]\NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED ;
FDRE \axaddr_offset_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(D[0]),
.Q(\axaddr_offset_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(D[1]),
.Q(\axaddr_offset_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(D[2]),
.Q(\axaddr_offset_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(D[3]),
.Q(\axaddr_offset_r_reg[3]_0 [3]),
.R(1'b0));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[0]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[0] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[3]_i_2__0_n_7 ),
.I3(\state_reg[1]_rep ),
.I4(Q[0]),
.O(\axaddr_wrap[0]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[10]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[10] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[11]_i_3__0_n_5 ),
.I3(\state_reg[1]_rep ),
.I4(Q[10]),
.O(\axaddr_wrap[10]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[11]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[11] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[11]_i_3__0_n_4 ),
.I3(\state_reg[1]_rep ),
.I4(Q[11]),
.O(\axaddr_wrap[11]_i_1__0_n_0 ));
LUT3 #(
.INIT(8'h41))
\axaddr_wrap[11]_i_2__0
(.I0(\axaddr_wrap[11]_i_4__0_n_0 ),
.I1(\wrap_cnt_r_reg_n_0_[3] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.O(\axaddr_wrap[11]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h6FF6FFFFFFFF6FF6))
\axaddr_wrap[11]_i_4__0
(.I0(\wrap_cnt_r_reg_n_0_[0] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\wrap_cnt_r_reg_n_0_[2] ),
.I4(\axlen_cnt_reg_n_0_[1] ),
.I5(\wrap_cnt_r_reg_n_0_[1] ),
.O(\axaddr_wrap[11]_i_4__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[1]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[1] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[3]_i_2__0_n_6 ),
.I3(\state_reg[1]_rep ),
.I4(Q[1]),
.O(\axaddr_wrap[1]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[2]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[2] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[3]_i_2__0_n_5 ),
.I3(\state_reg[1]_rep ),
.I4(Q[2]),
.O(\axaddr_wrap[2]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[3]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[3] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[3]_i_2__0_n_4 ),
.I3(\state_reg[1]_rep ),
.I4(Q[3]),
.O(\axaddr_wrap[3]_i_1__0_n_0 ));
LUT3 #(
.INIT(8'h6A))
\axaddr_wrap[3]_i_3
(.I0(\axaddr_wrap_reg_n_0_[3] ),
.I1(Q[12]),
.I2(Q[13]),
.O(\axaddr_wrap[3]_i_3_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_4
(.I0(\axaddr_wrap_reg_n_0_[2] ),
.I1(Q[12]),
.I2(Q[13]),
.O(\axaddr_wrap[3]_i_4_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_5
(.I0(\axaddr_wrap_reg_n_0_[1] ),
.I1(Q[13]),
.I2(Q[12]),
.O(\axaddr_wrap[3]_i_5_n_0 ));
LUT3 #(
.INIT(8'hA9))
\axaddr_wrap[3]_i_6
(.I0(\axaddr_wrap_reg_n_0_[0] ),
.I1(Q[12]),
.I2(Q[13]),
.O(\axaddr_wrap[3]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[4]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[4] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[7]_i_2__0_n_7 ),
.I3(\state_reg[1]_rep ),
.I4(Q[4]),
.O(\axaddr_wrap[4]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[5]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[5] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[7]_i_2__0_n_6 ),
.I3(\state_reg[1]_rep ),
.I4(Q[5]),
.O(\axaddr_wrap[5]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[6]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[6] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[7]_i_2__0_n_5 ),
.I3(\state_reg[1]_rep ),
.I4(Q[6]),
.O(\axaddr_wrap[6]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[7]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[7] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[7]_i_2__0_n_4 ),
.I3(\state_reg[1]_rep ),
.I4(Q[7]),
.O(\axaddr_wrap[7]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[8]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[8] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[11]_i_3__0_n_7 ),
.I3(\state_reg[1]_rep ),
.I4(Q[8]),
.O(\axaddr_wrap[8]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[9]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[9] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[11]_i_3__0_n_6 ),
.I3(\state_reg[1]_rep ),
.I4(Q[9]),
.O(\axaddr_wrap[9]_i_1__0_n_0 ));
FDRE \axaddr_wrap_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[0]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[0] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[10]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[10]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[10] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[11]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[11]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[11] ),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[11]_i_3__0
(.CI(\axaddr_wrap_reg[7]_i_2__0_n_0 ),
.CO({\NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED [3],\axaddr_wrap_reg[11]_i_3__0_n_1 ,\axaddr_wrap_reg[11]_i_3__0_n_2 ,\axaddr_wrap_reg[11]_i_3__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_wrap_reg[11]_i_3__0_n_4 ,\axaddr_wrap_reg[11]_i_3__0_n_5 ,\axaddr_wrap_reg[11]_i_3__0_n_6 ,\axaddr_wrap_reg[11]_i_3__0_n_7 }),
.S({\axaddr_wrap_reg_n_0_[11] ,\axaddr_wrap_reg_n_0_[10] ,\axaddr_wrap_reg_n_0_[9] ,\axaddr_wrap_reg_n_0_[8] }));
FDRE \axaddr_wrap_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[1]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[1] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[2]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[2] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[3]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[3] ),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[3]_i_2__0
(.CI(1'b0),
.CO({\axaddr_wrap_reg[3]_i_2__0_n_0 ,\axaddr_wrap_reg[3]_i_2__0_n_1 ,\axaddr_wrap_reg[3]_i_2__0_n_2 ,\axaddr_wrap_reg[3]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({\axaddr_wrap_reg_n_0_[3] ,\axaddr_wrap_reg_n_0_[2] ,\axaddr_wrap_reg_n_0_[1] ,\axaddr_wrap_reg_n_0_[0] }),
.O({\axaddr_wrap_reg[3]_i_2__0_n_4 ,\axaddr_wrap_reg[3]_i_2__0_n_5 ,\axaddr_wrap_reg[3]_i_2__0_n_6 ,\axaddr_wrap_reg[3]_i_2__0_n_7 }),
.S({\axaddr_wrap[3]_i_3_n_0 ,\axaddr_wrap[3]_i_4_n_0 ,\axaddr_wrap[3]_i_5_n_0 ,\axaddr_wrap[3]_i_6_n_0 }));
FDRE \axaddr_wrap_reg[4]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[4]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[4] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[5]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[5]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[5] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[6]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[6]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[6] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[7]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[7]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[7] ),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[7]_i_2__0
(.CI(\axaddr_wrap_reg[3]_i_2__0_n_0 ),
.CO({\axaddr_wrap_reg[7]_i_2__0_n_0 ,\axaddr_wrap_reg[7]_i_2__0_n_1 ,\axaddr_wrap_reg[7]_i_2__0_n_2 ,\axaddr_wrap_reg[7]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_wrap_reg[7]_i_2__0_n_4 ,\axaddr_wrap_reg[7]_i_2__0_n_5 ,\axaddr_wrap_reg[7]_i_2__0_n_6 ,\axaddr_wrap_reg[7]_i_2__0_n_7 }),
.S({\axaddr_wrap_reg_n_0_[7] ,\axaddr_wrap_reg_n_0_[6] ,\axaddr_wrap_reg_n_0_[5] ,\axaddr_wrap_reg_n_0_[4] }));
FDRE \axaddr_wrap_reg[8]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[8]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[8] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[9]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[9]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[9] ),
.R(1'b0));
LUT6 #(
.INIT(64'hA3A3A3A3A3A3A3A0))
\axlen_cnt[0]_i_1__1
(.I0(Q[15]),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(E),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\axlen_cnt_reg_n_0_[1] ),
.O(\axlen_cnt[0]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'hAAC3AAC3AAC3AAC0))
\axlen_cnt[1]_i_1__2
(.I0(Q[16]),
.I1(\axlen_cnt_reg_n_0_[1] ),
.I2(\axlen_cnt_reg_n_0_[0] ),
.I3(E),
.I4(\axlen_cnt_reg_n_0_[3] ),
.I5(\axlen_cnt_reg_n_0_[2] ),
.O(\axlen_cnt[1]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'hFFFFA9A80000A9A8))
\axlen_cnt[2]_i_1__2
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(E),
.I5(Q[17]),
.O(\axlen_cnt[2]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAACCCCCCC0))
\axlen_cnt[3]_i_1__1
(.I0(Q[18]),
.I1(\axlen_cnt_reg_n_0_[3] ),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(\axlen_cnt_reg_n_0_[1] ),
.I4(\axlen_cnt_reg_n_0_[0] ),
.I5(E),
.O(\axlen_cnt[3]_i_1__1_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[0]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[0] ),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[1]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[2]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[3]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[0]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[0] ),
.I2(Q[14]),
.I3(Q[0]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [0]),
.O(m_axi_araddr[0]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[10]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[10] ),
.I2(Q[14]),
.I3(Q[10]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [6]),
.O(m_axi_araddr[10]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[11]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[11] ),
.I2(Q[14]),
.I3(Q[11]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [7]),
.O(m_axi_araddr[11]));
LUT5 #(
.INIT(32'hB8FFB800))
\m_axi_araddr[1]_INST_0
(.I0(Q[1]),
.I1(sel_first_reg_0),
.I2(\axaddr_wrap_reg_n_0_[1] ),
.I3(Q[14]),
.I4(sel_first_reg_6),
.O(m_axi_araddr[1]));
LUT5 #(
.INIT(32'hB8FFB800))
\m_axi_araddr[2]_INST_0
(.I0(Q[2]),
.I1(sel_first_reg_0),
.I2(\axaddr_wrap_reg_n_0_[2] ),
.I3(Q[14]),
.I4(sel_first_reg_5),
.O(m_axi_araddr[2]));
LUT5 #(
.INIT(32'hB8FFB800))
\m_axi_araddr[3]_INST_0
(.I0(Q[3]),
.I1(sel_first_reg_0),
.I2(\axaddr_wrap_reg_n_0_[3] ),
.I3(Q[14]),
.I4(sel_first_reg_4),
.O(m_axi_araddr[3]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[4]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[4] ),
.I2(Q[14]),
.I3(Q[4]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [1]),
.O(m_axi_araddr[4]));
LUT5 #(
.INIT(32'hB8FFB800))
\m_axi_araddr[5]_INST_0
(.I0(Q[5]),
.I1(sel_first_reg_0),
.I2(\axaddr_wrap_reg_n_0_[5] ),
.I3(Q[14]),
.I4(sel_first_reg_3),
.O(m_axi_araddr[5]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[6]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[6] ),
.I2(Q[14]),
.I3(Q[6]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [2]),
.O(m_axi_araddr[6]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[7]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[7] ),
.I2(Q[14]),
.I3(Q[7]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [3]),
.O(m_axi_araddr[7]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[8]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[8] ),
.I2(Q[14]),
.I3(Q[8]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [4]),
.O(m_axi_araddr[8]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[9]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[9] ),
.I2(Q[14]),
.I3(Q[9]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [5]),
.O(m_axi_araddr[9]));
LUT5 #(
.INIT(32'hFEAAFEAE))
next_pending_r_i_1__1
(.I0(\m_payload_i_reg[47] ),
.I1(next_pending_r_reg_n_0),
.I2(\state_reg[1]_rep ),
.I3(next_pending_r_i_2__2_n_0),
.I4(E),
.O(wrap_next_pending));
LUT6 #(
.INIT(64'hFBFBFBFBFBFBFB00))
next_pending_r_i_2__2
(.I0(\state_reg[1] [0]),
.I1(si_rs_arvalid),
.I2(\state_reg[1] [1]),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\axlen_cnt_reg_n_0_[1] ),
.O(next_pending_r_i_2__2_n_0));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(wrap_next_pending),
.Q(next_pending_r_reg_n_0),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT4 #(
.INIT(16'hFB08))
s_axburst_eq0_i_1__0
(.I0(wrap_next_pending),
.I1(Q[14]),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq0_reg));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT4 #(
.INIT(16'hABA8))
s_axburst_eq1_i_1__0
(.I0(wrap_next_pending),
.I1(Q[14]),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq1_reg));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_1),
.Q(sel_first_reg_0),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[0]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [0]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[0] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[10]
(.C(aclk),
.CE(E),
.D(Q[10]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[10] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[11]
(.C(aclk),
.CE(E),
.D(Q[11]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[11] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[1]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [1]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[1] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[2]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [2]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[2] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[3]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [3]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[3] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[4]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [4]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[4] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[5]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [5]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[5] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[6]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [6]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[6] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[7]
(.C(aclk),
.CE(E),
.D(Q[7]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[7] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[8]
(.C(aclk),
.CE(E),
.D(Q[8]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[8] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[9]
(.C(aclk),
.CE(E),
.D(Q[9]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[9] ),
.R(1'b0));
LUT5 #(
.INIT(32'h3D310E02))
\wrap_cnt_r[1]_i_1__0
(.I0(\wrap_second_len_r_reg[3]_0 [0]),
.I1(E),
.I2(\axaddr_offset_r_reg[3]_2 ),
.I3(D[1]),
.I4(\wrap_second_len_r_reg[3]_0 [1]),
.O(\wrap_cnt_r[1]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h000CAAA8000C0000))
\wrap_cnt_r[3]_i_2__0
(.I0(\wrap_second_len_r_reg[3]_0 [1]),
.I1(\axaddr_offset_r_reg[3]_1 ),
.I2(D[1]),
.I3(D[0]),
.I4(E),
.I5(\wrap_second_len_r_reg[3]_0 [0]),
.O(\wrap_cnt_r_reg[3]_0 ));
FDRE \wrap_cnt_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [0]),
.Q(\wrap_cnt_r_reg_n_0_[0] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_cnt_r[1]_i_1__0_n_0 ),
.Q(\wrap_cnt_r_reg_n_0_[1] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [1]),
.Q(\wrap_cnt_r_reg_n_0_[2] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [2]),
.Q(\wrap_cnt_r_reg_n_0_[3] ),
.R(1'b0));
FDRE \wrap_second_len_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [0]),
.Q(\wrap_second_len_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [1]),
.Q(\wrap_second_len_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [2]),
.Q(\wrap_second_len_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [3]),
.Q(\wrap_second_len_r_reg[3]_0 [3]),
.R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axi_register_slice
(s_axi_awready,
s_axi_arready,
si_rs_awvalid,
s_axi_bvalid,
si_rs_bready,
si_rs_arvalid,
s_axi_rvalid,
si_rs_rready,
\axlen_cnt_reg[3] ,
Q,
\axlen_cnt_reg[3]_0 ,
\s_arid_r_reg[11] ,
axaddr_incr,
\axaddr_incr_reg[3] ,
\axaddr_incr_reg[7] ,
O,
D,
\wrap_second_len_r_reg[3] ,
\wrap_cnt_r_reg[2] ,
axaddr_offset,
\wrap_cnt_r_reg[3] ,
\axaddr_offset_r_reg[2] ,
next_pending_r_reg,
\wrap_cnt_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
\wrap_cnt_r_reg[2]_0 ,
axaddr_offset_0,
\wrap_cnt_r_reg[3]_1 ,
\axaddr_offset_r_reg[2]_0 ,
next_pending_r_reg_0,
\cnt_read_reg[2]_rep__0 ,
\wrap_boundary_axaddr_r_reg[6] ,
\wrap_boundary_axaddr_r_reg[6]_0 ,
\s_axi_bid[11] ,
\s_axi_rid[11] ,
aclk,
s_ready_i0,
m_valid_i0,
aresetn,
\state_reg[1] ,
\state_reg[1]_0 ,
\cnt_read_reg[4]_rep__0 ,
s_axi_rready,
S,
\m_payload_i_reg[3] ,
\wrap_second_len_r_reg[3]_1 ,
\state_reg[1]_rep ,
\wrap_second_len_r_reg[1] ,
\axaddr_offset_r_reg[2]_1 ,
\axaddr_offset_r_reg[3] ,
\axaddr_offset_r_reg[3]_0 ,
\axaddr_offset_r_reg[2]_2 ,
\state_reg[0]_rep ,
\state_reg[1]_rep_0 ,
s_axi_awvalid,
b_push,
\wrap_second_len_r_reg[3]_2 ,
\state_reg[1]_rep_1 ,
\wrap_second_len_r_reg[1]_0 ,
\axaddr_offset_r_reg[2]_3 ,
\axaddr_offset_r_reg[3]_1 ,
\axaddr_offset_r_reg[3]_2 ,
\axaddr_offset_r_reg[2]_4 ,
\state_reg[0]_rep_0 ,
\state_reg[1]_rep_2 ,
si_rs_bvalid,
s_axi_bready,
s_axi_awid,
s_axi_awlen,
s_axi_awburst,
s_axi_awsize,
s_axi_awprot,
s_axi_awaddr,
s_axi_arid,
s_axi_arlen,
s_axi_arburst,
s_axi_arsize,
s_axi_arprot,
s_axi_araddr,
out,
\s_bresp_acc_reg[1] ,
r_push_r_reg,
\cnt_read_reg[4] ,
E,
m_valid_i_reg);
output s_axi_awready;
output s_axi_arready;
output si_rs_awvalid;
output s_axi_bvalid;
output si_rs_bready;
output si_rs_arvalid;
output s_axi_rvalid;
output si_rs_rready;
output \axlen_cnt_reg[3] ;
output [54:0]Q;
output \axlen_cnt_reg[3]_0 ;
output [54:0]\s_arid_r_reg[11] ;
output [11:0]axaddr_incr;
output [3:0]\axaddr_incr_reg[3] ;
output [3:0]\axaddr_incr_reg[7] ;
output [3:0]O;
output [1:0]D;
output [2:0]\wrap_second_len_r_reg[3] ;
output \wrap_cnt_r_reg[2] ;
output [2:0]axaddr_offset;
output \wrap_cnt_r_reg[3] ;
output \axaddr_offset_r_reg[2] ;
output next_pending_r_reg;
output [1:0]\wrap_cnt_r_reg[3]_0 ;
output [2:0]\wrap_second_len_r_reg[3]_0 ;
output \wrap_cnt_r_reg[2]_0 ;
output [2:0]axaddr_offset_0;
output \wrap_cnt_r_reg[3]_1 ;
output \axaddr_offset_r_reg[2]_0 ;
output next_pending_r_reg_0;
output \cnt_read_reg[2]_rep__0 ;
output [6:0]\wrap_boundary_axaddr_r_reg[6] ;
output [6:0]\wrap_boundary_axaddr_r_reg[6]_0 ;
output [13:0]\s_axi_bid[11] ;
output [46:0]\s_axi_rid[11] ;
input aclk;
input s_ready_i0;
input m_valid_i0;
input aresetn;
input [1:0]\state_reg[1] ;
input [1:0]\state_reg[1]_0 ;
input \cnt_read_reg[4]_rep__0 ;
input s_axi_rready;
input [3:0]S;
input [3:0]\m_payload_i_reg[3] ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input \state_reg[1]_rep ;
input \wrap_second_len_r_reg[1] ;
input [0:0]\axaddr_offset_r_reg[2]_1 ;
input [2:0]\axaddr_offset_r_reg[3] ;
input \axaddr_offset_r_reg[3]_0 ;
input \axaddr_offset_r_reg[2]_2 ;
input \state_reg[0]_rep ;
input \state_reg[1]_rep_0 ;
input s_axi_awvalid;
input b_push;
input [3:0]\wrap_second_len_r_reg[3]_2 ;
input \state_reg[1]_rep_1 ;
input \wrap_second_len_r_reg[1]_0 ;
input [0:0]\axaddr_offset_r_reg[2]_3 ;
input [2:0]\axaddr_offset_r_reg[3]_1 ;
input \axaddr_offset_r_reg[3]_2 ;
input \axaddr_offset_r_reg[2]_4 ;
input \state_reg[0]_rep_0 ;
input \state_reg[1]_rep_2 ;
input si_rs_bvalid;
input s_axi_bready;
input [11:0]s_axi_awid;
input [3:0]s_axi_awlen;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awsize;
input [2:0]s_axi_awprot;
input [31:0]s_axi_awaddr;
input [11:0]s_axi_arid;
input [3:0]s_axi_arlen;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arsize;
input [2:0]s_axi_arprot;
input [31:0]s_axi_araddr;
input [11:0]out;
input [1:0]\s_bresp_acc_reg[1] ;
input [12:0]r_push_r_reg;
input [33:0]\cnt_read_reg[4] ;
input [0:0]E;
input [0:0]m_valid_i_reg;
wire [1:0]D;
wire [0:0]E;
wire [3:0]O;
wire [54:0]Q;
wire [3:0]S;
wire aclk;
wire \ar.ar_pipe_n_2 ;
wire aresetn;
wire \aw.aw_pipe_n_1 ;
wire \aw.aw_pipe_n_90 ;
wire [11:0]axaddr_incr;
wire [3:0]\axaddr_incr_reg[3] ;
wire [3:0]\axaddr_incr_reg[7] ;
wire [2:0]axaddr_offset;
wire [2:0]axaddr_offset_0;
wire \axaddr_offset_r_reg[2] ;
wire \axaddr_offset_r_reg[2]_0 ;
wire [0:0]\axaddr_offset_r_reg[2]_1 ;
wire \axaddr_offset_r_reg[2]_2 ;
wire [0:0]\axaddr_offset_r_reg[2]_3 ;
wire \axaddr_offset_r_reg[2]_4 ;
wire [2:0]\axaddr_offset_r_reg[3] ;
wire \axaddr_offset_r_reg[3]_0 ;
wire [2:0]\axaddr_offset_r_reg[3]_1 ;
wire \axaddr_offset_r_reg[3]_2 ;
wire \axlen_cnt_reg[3] ;
wire \axlen_cnt_reg[3]_0 ;
wire b_push;
wire \cnt_read_reg[2]_rep__0 ;
wire [33:0]\cnt_read_reg[4] ;
wire \cnt_read_reg[4]_rep__0 ;
wire [3:0]\m_payload_i_reg[3] ;
wire m_valid_i0;
wire [0:0]m_valid_i_reg;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire [11:0]out;
wire [12:0]r_push_r_reg;
wire [54:0]\s_arid_r_reg[11] ;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [3:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [1:0]s_axi_arsize;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [3:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [1:0]s_axi_awsize;
wire s_axi_awvalid;
wire [13:0]\s_axi_bid[11] ;
wire s_axi_bready;
wire s_axi_bvalid;
wire [46:0]\s_axi_rid[11] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [1:0]\s_bresp_acc_reg[1] ;
wire s_ready_i0;
wire si_rs_arvalid;
wire si_rs_awvalid;
wire si_rs_bready;
wire si_rs_bvalid;
wire si_rs_rready;
wire \state_reg[0]_rep ;
wire \state_reg[0]_rep_0 ;
wire [1:0]\state_reg[1] ;
wire [1:0]\state_reg[1]_0 ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire \state_reg[1]_rep_1 ;
wire \state_reg[1]_rep_2 ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6]_0 ;
wire \wrap_cnt_r_reg[2] ;
wire \wrap_cnt_r_reg[2]_0 ;
wire \wrap_cnt_r_reg[3] ;
wire [1:0]\wrap_cnt_r_reg[3]_0 ;
wire \wrap_cnt_r_reg[3]_1 ;
wire \wrap_second_len_r_reg[1] ;
wire \wrap_second_len_r_reg[1]_0 ;
wire [2:0]\wrap_second_len_r_reg[3] ;
wire [2:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
wire [3:0]\wrap_second_len_r_reg[3]_2 ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice \ar.ar_pipe
(.O(O),
.Q(\s_arid_r_reg[11] ),
.aclk(aclk),
.\aresetn_d_reg[0] (\aw.aw_pipe_n_1 ),
.\aresetn_d_reg[0]_0 (\aw.aw_pipe_n_90 ),
.\axaddr_incr_reg[3] (\axaddr_incr_reg[3] ),
.\axaddr_incr_reg[7] (\axaddr_incr_reg[7] ),
.axaddr_offset_0(axaddr_offset_0[2:1]),
.\axaddr_offset_r_reg[0] (axaddr_offset_0[0]),
.\axaddr_offset_r_reg[2] (\axaddr_offset_r_reg[2]_0 ),
.\axaddr_offset_r_reg[2]_0 (\axaddr_offset_r_reg[2]_3 ),
.\axaddr_offset_r_reg[2]_1 (\axaddr_offset_r_reg[2]_4 ),
.\axaddr_offset_r_reg[3] (si_rs_arvalid),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3]_1 ),
.\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3]_2 ),
.\axlen_cnt_reg[3] (\axlen_cnt_reg[3]_0 ),
.\m_payload_i_reg[3]_0 (\m_payload_i_reg[3] ),
.m_valid_i0(m_valid_i0),
.m_valid_i_reg_0(\ar.ar_pipe_n_2 ),
.m_valid_i_reg_1(m_valid_i_reg),
.next_pending_r_reg(next_pending_r_reg_0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize),
.s_ready_i0(s_ready_i0),
.\state_reg[0]_rep (\state_reg[0]_rep_0 ),
.\state_reg[1] (\state_reg[1]_0 ),
.\state_reg[1]_rep (\state_reg[1]_rep_1 ),
.\state_reg[1]_rep_0 (\state_reg[1]_rep_2 ),
.\wrap_boundary_axaddr_r_reg[6] (\wrap_boundary_axaddr_r_reg[6]_0 ),
.\wrap_cnt_r_reg[2] (\wrap_cnt_r_reg[2]_0 ),
.\wrap_cnt_r_reg[3] (\wrap_cnt_r_reg[3]_0 ),
.\wrap_cnt_r_reg[3]_0 (\wrap_cnt_r_reg[3]_1 ),
.\wrap_second_len_r_reg[1] (\wrap_second_len_r_reg[1]_0 ),
.\wrap_second_len_r_reg[3] (\wrap_second_len_r_reg[3]_0 ),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3]_2 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice_0 \aw.aw_pipe
(.D(D),
.E(E),
.Q(Q),
.S(S),
.aclk(aclk),
.aresetn(aresetn),
.\aresetn_d_reg[1]_inv (\aw.aw_pipe_n_90 ),
.\aresetn_d_reg[1]_inv_0 (\ar.ar_pipe_n_2 ),
.axaddr_incr(axaddr_incr),
.axaddr_offset(axaddr_offset[2:1]),
.\axaddr_offset_r_reg[0] (axaddr_offset[0]),
.\axaddr_offset_r_reg[2] (\axaddr_offset_r_reg[2] ),
.\axaddr_offset_r_reg[2]_0 (\axaddr_offset_r_reg[2]_1 ),
.\axaddr_offset_r_reg[2]_1 (\axaddr_offset_r_reg[2]_2 ),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3] ),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3]_0 ),
.\axlen_cnt_reg[3] (\axlen_cnt_reg[3] ),
.b_push(b_push),
.m_valid_i_reg_0(si_rs_awvalid),
.next_pending_r_reg(next_pending_r_reg),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize),
.s_axi_awvalid(s_axi_awvalid),
.s_ready_i_reg_0(\aw.aw_pipe_n_1 ),
.\state_reg[0]_rep (\state_reg[0]_rep ),
.\state_reg[1] (\state_reg[1] ),
.\state_reg[1]_rep (\state_reg[1]_rep ),
.\state_reg[1]_rep_0 (\state_reg[1]_rep_0 ),
.\wrap_boundary_axaddr_r_reg[6] (\wrap_boundary_axaddr_r_reg[6] ),
.\wrap_cnt_r_reg[2] (\wrap_cnt_r_reg[2] ),
.\wrap_cnt_r_reg[3] (\wrap_cnt_r_reg[3] ),
.\wrap_second_len_r_reg[1] (\wrap_second_len_r_reg[1] ),
.\wrap_second_len_r_reg[3] (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3]_1 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice__parameterized1 \b.b_pipe
(.aclk(aclk),
.\aresetn_d_reg[0] (\aw.aw_pipe_n_1 ),
.\aresetn_d_reg[1]_inv (\ar.ar_pipe_n_2 ),
.out(out),
.\s_axi_bid[11] (\s_axi_bid[11] ),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.\s_bresp_acc_reg[1] (\s_bresp_acc_reg[1] ),
.si_rs_bvalid(si_rs_bvalid),
.\skid_buffer_reg[0]_0 (si_rs_bready));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice__parameterized2 \r.r_pipe
(.aclk(aclk),
.\aresetn_d_reg[0] (\aw.aw_pipe_n_1 ),
.\aresetn_d_reg[1]_inv (\ar.ar_pipe_n_2 ),
.\cnt_read_reg[2]_rep__0 (\cnt_read_reg[2]_rep__0 ),
.\cnt_read_reg[4] (\cnt_read_reg[4] ),
.\cnt_read_reg[4]_rep__0 (\cnt_read_reg[4]_rep__0 ),
.r_push_r_reg(r_push_r_reg),
.\s_axi_rid[11] (\s_axi_rid[11] ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.\skid_buffer_reg[0]_0 (si_rs_rready));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice
(s_axi_arready,
\axaddr_offset_r_reg[3] ,
m_valid_i_reg_0,
\axlen_cnt_reg[3] ,
Q,
\axaddr_incr_reg[3] ,
\axaddr_incr_reg[7] ,
O,
\wrap_cnt_r_reg[3] ,
\wrap_second_len_r_reg[3] ,
\wrap_cnt_r_reg[2] ,
\axaddr_offset_r_reg[0] ,
axaddr_offset_0,
\wrap_cnt_r_reg[3]_0 ,
\axaddr_offset_r_reg[2] ,
next_pending_r_reg,
\wrap_boundary_axaddr_r_reg[6] ,
\aresetn_d_reg[0] ,
s_ready_i0,
aclk,
m_valid_i0,
\aresetn_d_reg[0]_0 ,
\state_reg[1] ,
\m_payload_i_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
\state_reg[1]_rep ,
\wrap_second_len_r_reg[1] ,
\axaddr_offset_r_reg[2]_0 ,
\axaddr_offset_r_reg[3]_0 ,
\axaddr_offset_r_reg[3]_1 ,
\axaddr_offset_r_reg[2]_1 ,
\state_reg[0]_rep ,
\state_reg[1]_rep_0 ,
s_axi_arid,
s_axi_arlen,
s_axi_arburst,
s_axi_arsize,
s_axi_arprot,
s_axi_araddr,
m_valid_i_reg_1);
output s_axi_arready;
output \axaddr_offset_r_reg[3] ;
output m_valid_i_reg_0;
output \axlen_cnt_reg[3] ;
output [54:0]Q;
output [3:0]\axaddr_incr_reg[3] ;
output [3:0]\axaddr_incr_reg[7] ;
output [3:0]O;
output [1:0]\wrap_cnt_r_reg[3] ;
output [2:0]\wrap_second_len_r_reg[3] ;
output \wrap_cnt_r_reg[2] ;
output \axaddr_offset_r_reg[0] ;
output [1:0]axaddr_offset_0;
output \wrap_cnt_r_reg[3]_0 ;
output \axaddr_offset_r_reg[2] ;
output next_pending_r_reg;
output [6:0]\wrap_boundary_axaddr_r_reg[6] ;
input \aresetn_d_reg[0] ;
input s_ready_i0;
input aclk;
input m_valid_i0;
input \aresetn_d_reg[0]_0 ;
input [1:0]\state_reg[1] ;
input [3:0]\m_payload_i_reg[3]_0 ;
input [3:0]\wrap_second_len_r_reg[3]_0 ;
input \state_reg[1]_rep ;
input \wrap_second_len_r_reg[1] ;
input [0:0]\axaddr_offset_r_reg[2]_0 ;
input [2:0]\axaddr_offset_r_reg[3]_0 ;
input \axaddr_offset_r_reg[3]_1 ;
input \axaddr_offset_r_reg[2]_1 ;
input \state_reg[0]_rep ;
input \state_reg[1]_rep_0 ;
input [11:0]s_axi_arid;
input [3:0]s_axi_arlen;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arsize;
input [2:0]s_axi_arprot;
input [31:0]s_axi_araddr;
input [0:0]m_valid_i_reg_1;
wire [3:0]O;
wire [54:0]Q;
wire aclk;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[0]_0 ;
wire \axaddr_incr[3]_i_4__0_n_0 ;
wire \axaddr_incr[3]_i_5__0_n_0 ;
wire \axaddr_incr[3]_i_6__0_n_0 ;
wire \axaddr_incr_reg[11]_i_3__0_n_1 ;
wire \axaddr_incr_reg[11]_i_3__0_n_2 ;
wire \axaddr_incr_reg[11]_i_3__0_n_3 ;
wire [3:0]\axaddr_incr_reg[3] ;
wire \axaddr_incr_reg[3]_i_2__0_n_0 ;
wire \axaddr_incr_reg[3]_i_2__0_n_1 ;
wire \axaddr_incr_reg[3]_i_2__0_n_2 ;
wire \axaddr_incr_reg[3]_i_2__0_n_3 ;
wire [3:0]\axaddr_incr_reg[7] ;
wire \axaddr_incr_reg[7]_i_2__0_n_0 ;
wire \axaddr_incr_reg[7]_i_2__0_n_1 ;
wire \axaddr_incr_reg[7]_i_2__0_n_2 ;
wire \axaddr_incr_reg[7]_i_2__0_n_3 ;
wire [1:0]axaddr_offset_0;
wire \axaddr_offset_r[0]_i_2__0_n_0 ;
wire \axaddr_offset_r[1]_i_2__0_n_0 ;
wire \axaddr_offset_r[3]_i_2__0_n_0 ;
wire \axaddr_offset_r_reg[0] ;
wire \axaddr_offset_r_reg[2] ;
wire [0:0]\axaddr_offset_r_reg[2]_0 ;
wire \axaddr_offset_r_reg[2]_1 ;
wire \axaddr_offset_r_reg[3] ;
wire [2:0]\axaddr_offset_r_reg[3]_0 ;
wire \axaddr_offset_r_reg[3]_1 ;
wire \axlen_cnt_reg[3] ;
wire \m_payload_i[0]_i_1__0_n_0 ;
wire \m_payload_i[10]_i_1__0_n_0 ;
wire \m_payload_i[11]_i_1__0_n_0 ;
wire \m_payload_i[12]_i_1__0_n_0 ;
wire \m_payload_i[13]_i_1__1_n_0 ;
wire \m_payload_i[14]_i_1__0_n_0 ;
wire \m_payload_i[15]_i_1__0_n_0 ;
wire \m_payload_i[16]_i_1__0_n_0 ;
wire \m_payload_i[17]_i_1__0_n_0 ;
wire \m_payload_i[18]_i_1__0_n_0 ;
wire \m_payload_i[19]_i_1__0_n_0 ;
wire \m_payload_i[1]_i_1__0_n_0 ;
wire \m_payload_i[20]_i_1__0_n_0 ;
wire \m_payload_i[21]_i_1__0_n_0 ;
wire \m_payload_i[22]_i_1__0_n_0 ;
wire \m_payload_i[23]_i_1__0_n_0 ;
wire \m_payload_i[24]_i_1__0_n_0 ;
wire \m_payload_i[25]_i_1__0_n_0 ;
wire \m_payload_i[26]_i_1__0_n_0 ;
wire \m_payload_i[27]_i_1__0_n_0 ;
wire \m_payload_i[28]_i_1__0_n_0 ;
wire \m_payload_i[29]_i_1__0_n_0 ;
wire \m_payload_i[2]_i_1__0_n_0 ;
wire \m_payload_i[30]_i_1__0_n_0 ;
wire \m_payload_i[31]_i_2__0_n_0 ;
wire \m_payload_i[32]_i_1__0_n_0 ;
wire \m_payload_i[33]_i_1__0_n_0 ;
wire \m_payload_i[34]_i_1__0_n_0 ;
wire \m_payload_i[35]_i_1__0_n_0 ;
wire \m_payload_i[36]_i_1__0_n_0 ;
wire \m_payload_i[38]_i_1__0_n_0 ;
wire \m_payload_i[39]_i_1__0_n_0 ;
wire \m_payload_i[3]_i_1__0_n_0 ;
wire \m_payload_i[44]_i_1__0_n_0 ;
wire \m_payload_i[45]_i_1__0_n_0 ;
wire \m_payload_i[46]_i_1__1_n_0 ;
wire \m_payload_i[47]_i_1__0_n_0 ;
wire \m_payload_i[4]_i_1__0_n_0 ;
wire \m_payload_i[50]_i_1__0_n_0 ;
wire \m_payload_i[51]_i_1__0_n_0 ;
wire \m_payload_i[52]_i_1__0_n_0 ;
wire \m_payload_i[53]_i_1__0_n_0 ;
wire \m_payload_i[54]_i_1__0_n_0 ;
wire \m_payload_i[55]_i_1__0_n_0 ;
wire \m_payload_i[56]_i_1__0_n_0 ;
wire \m_payload_i[57]_i_1__0_n_0 ;
wire \m_payload_i[58]_i_1__0_n_0 ;
wire \m_payload_i[59]_i_1__0_n_0 ;
wire \m_payload_i[5]_i_1__0_n_0 ;
wire \m_payload_i[60]_i_1__0_n_0 ;
wire \m_payload_i[61]_i_1__0_n_0 ;
wire \m_payload_i[6]_i_1__0_n_0 ;
wire \m_payload_i[7]_i_1__0_n_0 ;
wire \m_payload_i[8]_i_1__0_n_0 ;
wire \m_payload_i[9]_i_1__0_n_0 ;
wire [3:0]\m_payload_i_reg[3]_0 ;
wire m_valid_i0;
wire m_valid_i_reg_0;
wire [0:0]m_valid_i_reg_1;
wire next_pending_r_reg;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [3:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [1:0]s_axi_arsize;
wire s_ready_i0;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[47] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[50] ;
wire \skid_buffer_reg_n_0_[51] ;
wire \skid_buffer_reg_n_0_[52] ;
wire \skid_buffer_reg_n_0_[53] ;
wire \skid_buffer_reg_n_0_[54] ;
wire \skid_buffer_reg_n_0_[55] ;
wire \skid_buffer_reg_n_0_[56] ;
wire \skid_buffer_reg_n_0_[57] ;
wire \skid_buffer_reg_n_0_[58] ;
wire \skid_buffer_reg_n_0_[59] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[60] ;
wire \skid_buffer_reg_n_0_[61] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
wire \state_reg[0]_rep ;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire \wrap_boundary_axaddr_r[3]_i_2__0_n_0 ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
wire \wrap_cnt_r[3]_i_5__0_n_0 ;
wire \wrap_cnt_r_reg[2] ;
wire [1:0]\wrap_cnt_r_reg[3] ;
wire \wrap_cnt_r_reg[3]_0 ;
wire \wrap_second_len_r[3]_i_2__0_n_0 ;
wire \wrap_second_len_r[3]_i_3__0_n_0 ;
wire \wrap_second_len_r_reg[1] ;
wire [2:0]\wrap_second_len_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:3]\NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED ;
FDRE #(
.INIT(1'b1))
\aresetn_d_reg[1]_inv
(.C(aclk),
.CE(1'b1),
.D(\aresetn_d_reg[0]_0 ),
.Q(m_valid_i_reg_0),
.R(1'b0));
LUT3 #(
.INIT(8'h2A))
\axaddr_incr[3]_i_4__0
(.I0(Q[2]),
.I1(Q[35]),
.I2(Q[36]),
.O(\axaddr_incr[3]_i_4__0_n_0 ));
LUT2 #(
.INIT(4'h2))
\axaddr_incr[3]_i_5__0
(.I0(Q[1]),
.I1(Q[36]),
.O(\axaddr_incr[3]_i_5__0_n_0 ));
LUT3 #(
.INIT(8'h02))
\axaddr_incr[3]_i_6__0
(.I0(Q[0]),
.I1(Q[35]),
.I2(Q[36]),
.O(\axaddr_incr[3]_i_6__0_n_0 ));
CARRY4 \axaddr_incr_reg[11]_i_3__0
(.CI(\axaddr_incr_reg[7]_i_2__0_n_0 ),
.CO({\NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED [3],\axaddr_incr_reg[11]_i_3__0_n_1 ,\axaddr_incr_reg[11]_i_3__0_n_2 ,\axaddr_incr_reg[11]_i_3__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(O),
.S(Q[11:8]));
CARRY4 \axaddr_incr_reg[3]_i_2__0
(.CI(1'b0),
.CO({\axaddr_incr_reg[3]_i_2__0_n_0 ,\axaddr_incr_reg[3]_i_2__0_n_1 ,\axaddr_incr_reg[3]_i_2__0_n_2 ,\axaddr_incr_reg[3]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({Q[3],\axaddr_incr[3]_i_4__0_n_0 ,\axaddr_incr[3]_i_5__0_n_0 ,\axaddr_incr[3]_i_6__0_n_0 }),
.O(\axaddr_incr_reg[3] ),
.S(\m_payload_i_reg[3]_0 ));
CARRY4 \axaddr_incr_reg[7]_i_2__0
(.CI(\axaddr_incr_reg[3]_i_2__0_n_0 ),
.CO({\axaddr_incr_reg[7]_i_2__0_n_0 ,\axaddr_incr_reg[7]_i_2__0_n_1 ,\axaddr_incr_reg[7]_i_2__0_n_2 ,\axaddr_incr_reg[7]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\axaddr_incr_reg[7] ),
.S(Q[7:4]));
LUT6 #(
.INIT(64'hFFFFF8FF00000800))
\axaddr_offset_r[0]_i_1__0
(.I0(\axaddr_offset_r[0]_i_2__0_n_0 ),
.I1(Q[39]),
.I2(\state_reg[1] [1]),
.I3(\axaddr_offset_r_reg[3] ),
.I4(\state_reg[1] [0]),
.I5(\axaddr_offset_r_reg[3]_0 [0]),
.O(\axaddr_offset_r_reg[0] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[0]_i_2__0
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[36]),
.I3(Q[1]),
.I4(Q[35]),
.I5(Q[0]),
.O(\axaddr_offset_r[0]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFF8FF00000800))
\axaddr_offset_r[1]_i_1__0
(.I0(\axaddr_offset_r[1]_i_2__0_n_0 ),
.I1(Q[40]),
.I2(\state_reg[1] [1]),
.I3(\axaddr_offset_r_reg[3] ),
.I4(\state_reg[1] [0]),
.I5(\axaddr_offset_r_reg[3]_0 [1]),
.O(axaddr_offset_0[0]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[1]_i_2__0
(.I0(Q[4]),
.I1(Q[3]),
.I2(Q[36]),
.I3(Q[2]),
.I4(Q[35]),
.I5(Q[1]),
.O(\axaddr_offset_r[1]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[2]_i_2__0
(.I0(Q[5]),
.I1(Q[4]),
.I2(Q[36]),
.I3(Q[3]),
.I4(Q[35]),
.I5(Q[2]),
.O(\axaddr_offset_r_reg[2] ));
LUT6 #(
.INIT(64'hFFFFF8FF00000800))
\axaddr_offset_r[3]_i_1__0
(.I0(\axaddr_offset_r[3]_i_2__0_n_0 ),
.I1(Q[42]),
.I2(\state_reg[1] [1]),
.I3(\axaddr_offset_r_reg[3] ),
.I4(\state_reg[1] [0]),
.I5(\axaddr_offset_r_reg[3]_0 [2]),
.O(axaddr_offset_0[1]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[3]_i_2__0
(.I0(Q[6]),
.I1(Q[5]),
.I2(Q[36]),
.I3(Q[4]),
.I4(Q[35]),
.I5(Q[3]),
.O(\axaddr_offset_r[3]_i_2__0_n_0 ));
LUT4 #(
.INIT(16'h0020))
\axlen_cnt[3]_i_3__0
(.I0(Q[42]),
.I1(\state_reg[1] [0]),
.I2(\axaddr_offset_r_reg[3] ),
.I3(\state_reg[1] [1]),
.O(\axlen_cnt_reg[3] ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__0
(.I0(s_axi_araddr[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(\m_payload_i[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__0
(.I0(s_axi_araddr[10]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(\m_payload_i[10]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__0
(.I0(s_axi_araddr[11]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(\m_payload_i[11]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__0
(.I0(s_axi_araddr[12]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(\m_payload_i[12]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__1
(.I0(s_axi_araddr[13]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(\m_payload_i[13]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1__0
(.I0(s_axi_araddr[14]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(\m_payload_i[14]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1__0
(.I0(s_axi_araddr[15]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(\m_payload_i[15]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1__0
(.I0(s_axi_araddr[16]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(\m_payload_i[16]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1__0
(.I0(s_axi_araddr[17]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(\m_payload_i[17]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1__0
(.I0(s_axi_araddr[18]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(\m_payload_i[18]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1__0
(.I0(s_axi_araddr[19]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(\m_payload_i[19]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__0
(.I0(s_axi_araddr[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(\m_payload_i[1]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1__0
(.I0(s_axi_araddr[20]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(\m_payload_i[20]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1__0
(.I0(s_axi_araddr[21]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(\m_payload_i[21]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1__0
(.I0(s_axi_araddr[22]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(\m_payload_i[22]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1__0
(.I0(s_axi_araddr[23]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(\m_payload_i[23]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1__0
(.I0(s_axi_araddr[24]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(\m_payload_i[24]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1__0
(.I0(s_axi_araddr[25]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(\m_payload_i[25]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1__0
(.I0(s_axi_araddr[26]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(\m_payload_i[26]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1__0
(.I0(s_axi_araddr[27]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(\m_payload_i[27]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1__0
(.I0(s_axi_araddr[28]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(\m_payload_i[28]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1__0
(.I0(s_axi_araddr[29]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(\m_payload_i[29]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__0
(.I0(s_axi_araddr[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(\m_payload_i[2]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1__0
(.I0(s_axi_araddr[30]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(\m_payload_i[30]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_2__0
(.I0(s_axi_araddr[31]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(\m_payload_i[31]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1__0
(.I0(s_axi_arprot[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(\m_payload_i[32]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1__0
(.I0(s_axi_arprot[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(\m_payload_i[33]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1__0
(.I0(s_axi_arprot[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(\m_payload_i[34]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1__0
(.I0(s_axi_arsize[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(\m_payload_i[35]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1__0
(.I0(s_axi_arsize[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(\m_payload_i[36]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1__0
(.I0(s_axi_arburst[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(\m_payload_i[38]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1__0
(.I0(s_axi_arburst[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(\m_payload_i[39]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__0
(.I0(s_axi_araddr[3]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(\m_payload_i[3]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1__0
(.I0(s_axi_arlen[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(\m_payload_i[44]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1__0
(.I0(s_axi_arlen[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(\m_payload_i[45]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_1__1
(.I0(s_axi_arlen[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(\m_payload_i[46]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[47]_i_1__0
(.I0(s_axi_arlen[3]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[47] ),
.O(\m_payload_i[47]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__0
(.I0(s_axi_araddr[4]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(\m_payload_i[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[50]_i_1__0
(.I0(s_axi_arid[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[50] ),
.O(\m_payload_i[50]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[51]_i_1__0
(.I0(s_axi_arid[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[51] ),
.O(\m_payload_i[51]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[52]_i_1__0
(.I0(s_axi_arid[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[52] ),
.O(\m_payload_i[52]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[53]_i_1__0
(.I0(s_axi_arid[3]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[53] ),
.O(\m_payload_i[53]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[54]_i_1__0
(.I0(s_axi_arid[4]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[54] ),
.O(\m_payload_i[54]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[55]_i_1__0
(.I0(s_axi_arid[5]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[55] ),
.O(\m_payload_i[55]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[56]_i_1__0
(.I0(s_axi_arid[6]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[56] ),
.O(\m_payload_i[56]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[57]_i_1__0
(.I0(s_axi_arid[7]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[57] ),
.O(\m_payload_i[57]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[58]_i_1__0
(.I0(s_axi_arid[8]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[58] ),
.O(\m_payload_i[58]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[59]_i_1__0
(.I0(s_axi_arid[9]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[59] ),
.O(\m_payload_i[59]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__0
(.I0(s_axi_araddr[5]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(\m_payload_i[5]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[60]_i_1__0
(.I0(s_axi_arid[10]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[60] ),
.O(\m_payload_i[60]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[61]_i_1__0
(.I0(s_axi_arid[11]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[61] ),
.O(\m_payload_i[61]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__0
(.I0(s_axi_araddr[6]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(\m_payload_i[6]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__0
(.I0(s_axi_araddr[7]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(\m_payload_i[7]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__0
(.I0(s_axi_araddr[8]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(\m_payload_i[8]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__0
(.I0(s_axi_araddr[9]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(\m_payload_i[9]_i_1__0_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[0]_i_1__0_n_0 ),
.Q(Q[0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[10]_i_1__0_n_0 ),
.Q(Q[10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[11]_i_1__0_n_0 ),
.Q(Q[11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[12]_i_1__0_n_0 ),
.Q(Q[12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[13]_i_1__1_n_0 ),
.Q(Q[13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[14]_i_1__0_n_0 ),
.Q(Q[14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[15]_i_1__0_n_0 ),
.Q(Q[15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[16]_i_1__0_n_0 ),
.Q(Q[16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[17]_i_1__0_n_0 ),
.Q(Q[17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[18]_i_1__0_n_0 ),
.Q(Q[18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[19]_i_1__0_n_0 ),
.Q(Q[19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[1]_i_1__0_n_0 ),
.Q(Q[1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[20]_i_1__0_n_0 ),
.Q(Q[20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[21]_i_1__0_n_0 ),
.Q(Q[21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[22]_i_1__0_n_0 ),
.Q(Q[22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[23]_i_1__0_n_0 ),
.Q(Q[23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[24]_i_1__0_n_0 ),
.Q(Q[24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[25]_i_1__0_n_0 ),
.Q(Q[25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[26]_i_1__0_n_0 ),
.Q(Q[26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[27]_i_1__0_n_0 ),
.Q(Q[27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[28]_i_1__0_n_0 ),
.Q(Q[28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[29]_i_1__0_n_0 ),
.Q(Q[29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[2]_i_1__0_n_0 ),
.Q(Q[2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[30]_i_1__0_n_0 ),
.Q(Q[30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[31]_i_2__0_n_0 ),
.Q(Q[31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[32]_i_1__0_n_0 ),
.Q(Q[32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[33]_i_1__0_n_0 ),
.Q(Q[33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[34]_i_1__0_n_0 ),
.Q(Q[34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[35]_i_1__0_n_0 ),
.Q(Q[35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[36]_i_1__0_n_0 ),
.Q(Q[36]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[38]_i_1__0_n_0 ),
.Q(Q[37]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[39]_i_1__0_n_0 ),
.Q(Q[38]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[3]_i_1__0_n_0 ),
.Q(Q[3]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[44]_i_1__0_n_0 ),
.Q(Q[39]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[45]_i_1__0_n_0 ),
.Q(Q[40]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[46]_i_1__1_n_0 ),
.Q(Q[41]),
.R(1'b0));
FDRE \m_payload_i_reg[47]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[47]_i_1__0_n_0 ),
.Q(Q[42]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[4]_i_1__0_n_0 ),
.Q(Q[4]),
.R(1'b0));
FDRE \m_payload_i_reg[50]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[50]_i_1__0_n_0 ),
.Q(Q[43]),
.R(1'b0));
FDRE \m_payload_i_reg[51]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[51]_i_1__0_n_0 ),
.Q(Q[44]),
.R(1'b0));
FDRE \m_payload_i_reg[52]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[52]_i_1__0_n_0 ),
.Q(Q[45]),
.R(1'b0));
FDRE \m_payload_i_reg[53]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[53]_i_1__0_n_0 ),
.Q(Q[46]),
.R(1'b0));
FDRE \m_payload_i_reg[54]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[54]_i_1__0_n_0 ),
.Q(Q[47]),
.R(1'b0));
FDRE \m_payload_i_reg[55]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[55]_i_1__0_n_0 ),
.Q(Q[48]),
.R(1'b0));
FDRE \m_payload_i_reg[56]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[56]_i_1__0_n_0 ),
.Q(Q[49]),
.R(1'b0));
FDRE \m_payload_i_reg[57]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[57]_i_1__0_n_0 ),
.Q(Q[50]),
.R(1'b0));
FDRE \m_payload_i_reg[58]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[58]_i_1__0_n_0 ),
.Q(Q[51]),
.R(1'b0));
FDRE \m_payload_i_reg[59]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[59]_i_1__0_n_0 ),
.Q(Q[52]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[5]_i_1__0_n_0 ),
.Q(Q[5]),
.R(1'b0));
FDRE \m_payload_i_reg[60]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[60]_i_1__0_n_0 ),
.Q(Q[53]),
.R(1'b0));
FDRE \m_payload_i_reg[61]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[61]_i_1__0_n_0 ),
.Q(Q[54]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[6]_i_1__0_n_0 ),
.Q(Q[6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[7]_i_1__0_n_0 ),
.Q(Q[7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[8]_i_1__0_n_0 ),
.Q(Q[8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[9]_i_1__0_n_0 ),
.Q(Q[9]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(\axaddr_offset_r_reg[3] ),
.R(m_valid_i_reg_0));
LUT5 #(
.INIT(32'hAAAAAAA8))
next_pending_r_i_3
(.I0(\state_reg[1]_rep ),
.I1(Q[42]),
.I2(Q[40]),
.I3(Q[39]),
.I4(Q[41]),
.O(next_pending_r_reg));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(s_axi_arready),
.R(\aresetn_d_reg[0] ));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arprot[0]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arprot[1]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arprot[2]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arsize[0]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arsize[1]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arburst[0]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arburst[1]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[0]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[1]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[2]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[47]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[3]),
.Q(\skid_buffer_reg_n_0_[47] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[50]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[0]),
.Q(\skid_buffer_reg_n_0_[50] ),
.R(1'b0));
FDRE \skid_buffer_reg[51]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[1]),
.Q(\skid_buffer_reg_n_0_[51] ),
.R(1'b0));
FDRE \skid_buffer_reg[52]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[2]),
.Q(\skid_buffer_reg_n_0_[52] ),
.R(1'b0));
FDRE \skid_buffer_reg[53]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[3]),
.Q(\skid_buffer_reg_n_0_[53] ),
.R(1'b0));
FDRE \skid_buffer_reg[54]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[4]),
.Q(\skid_buffer_reg_n_0_[54] ),
.R(1'b0));
FDRE \skid_buffer_reg[55]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[5]),
.Q(\skid_buffer_reg_n_0_[55] ),
.R(1'b0));
FDRE \skid_buffer_reg[56]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[6]),
.Q(\skid_buffer_reg_n_0_[56] ),
.R(1'b0));
FDRE \skid_buffer_reg[57]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[7]),
.Q(\skid_buffer_reg_n_0_[57] ),
.R(1'b0));
FDRE \skid_buffer_reg[58]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[8]),
.Q(\skid_buffer_reg_n_0_[58] ),
.R(1'b0));
FDRE \skid_buffer_reg[59]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[9]),
.Q(\skid_buffer_reg_n_0_[59] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[60]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[10]),
.Q(\skid_buffer_reg_n_0_[60] ),
.R(1'b0));
FDRE \skid_buffer_reg[61]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[11]),
.Q(\skid_buffer_reg_n_0_[61] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'hAA8A))
\wrap_boundary_axaddr_r[0]_i_1__0
(.I0(Q[0]),
.I1(Q[35]),
.I2(Q[39]),
.I3(Q[36]),
.O(\wrap_boundary_axaddr_r_reg[6] [0]));
LUT5 #(
.INIT(32'h8A888AAA))
\wrap_boundary_axaddr_r[1]_i_1__0
(.I0(Q[1]),
.I1(Q[36]),
.I2(Q[39]),
.I3(Q[35]),
.I4(Q[40]),
.O(\wrap_boundary_axaddr_r_reg[6] [1]));
LUT6 #(
.INIT(64'hFF0F553300000000))
\wrap_boundary_axaddr_r[2]_i_1__0
(.I0(Q[40]),
.I1(Q[41]),
.I2(Q[39]),
.I3(Q[35]),
.I4(Q[36]),
.I5(Q[2]),
.O(\wrap_boundary_axaddr_r_reg[6] [2]));
LUT6 #(
.INIT(64'h020202A2A2A202A2))
\wrap_boundary_axaddr_r[3]_i_1__0
(.I0(Q[3]),
.I1(\wrap_boundary_axaddr_r[3]_i_2__0_n_0 ),
.I2(Q[36]),
.I3(Q[40]),
.I4(Q[35]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [3]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\wrap_boundary_axaddr_r[3]_i_2__0
(.I0(Q[41]),
.I1(Q[35]),
.I2(Q[42]),
.O(\wrap_boundary_axaddr_r[3]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h503F5F3F00000000))
\wrap_boundary_axaddr_r[4]_i_1__0
(.I0(Q[40]),
.I1(Q[41]),
.I2(Q[36]),
.I3(Q[35]),
.I4(Q[42]),
.I5(Q[4]),
.O(\wrap_boundary_axaddr_r_reg[6] [4]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT5 #(
.INIT(32'h2A222AAA))
\wrap_boundary_axaddr_r[5]_i_1__0
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[41]),
.I3(Q[35]),
.I4(Q[42]),
.O(\wrap_boundary_axaddr_r_reg[6] [5]));
LUT4 #(
.INIT(16'h2AAA))
\wrap_boundary_axaddr_r[6]_i_1__0
(.I0(Q[6]),
.I1(Q[42]),
.I2(Q[35]),
.I3(Q[36]),
.O(\wrap_boundary_axaddr_r_reg[6] [6]));
LUT6 #(
.INIT(64'hAAA6AA56AAAAAAAA))
\wrap_cnt_r[2]_i_1__0
(.I0(\wrap_second_len_r_reg[3] [1]),
.I1(\wrap_second_len_r_reg[3]_0 [0]),
.I2(\state_reg[1]_rep ),
.I3(\wrap_cnt_r_reg[2] ),
.I4(\axaddr_offset_r_reg[0] ),
.I5(\wrap_second_len_r_reg[3] [0]),
.O(\wrap_cnt_r_reg[3] [0]));
LUT3 #(
.INIT(8'h6A))
\wrap_cnt_r[3]_i_1__0
(.I0(\wrap_second_len_r_reg[3] [2]),
.I1(\wrap_second_len_r_reg[1] ),
.I2(\wrap_second_len_r_reg[3] [1]),
.O(\wrap_cnt_r_reg[3] [1]));
LUT6 #(
.INIT(64'hFFFFFFFFEAEAFFEA))
\wrap_cnt_r[3]_i_3__0
(.I0(\axaddr_offset_r_reg[3]_1 ),
.I1(\axlen_cnt_reg[3] ),
.I2(\axaddr_offset_r[3]_i_2__0_n_0 ),
.I3(\axaddr_offset_r_reg[2] ),
.I4(\wrap_cnt_r[3]_i_5__0_n_0 ),
.I5(\axaddr_offset_r_reg[2]_1 ),
.O(\wrap_cnt_r_reg[3]_0 ));
LUT4 #(
.INIT(16'hFFDF))
\wrap_cnt_r[3]_i_5__0
(.I0(Q[41]),
.I1(\state_reg[0]_rep ),
.I2(\axaddr_offset_r_reg[3] ),
.I3(\state_reg[1]_rep_0 ),
.O(\wrap_cnt_r[3]_i_5__0_n_0 ));
LUT6 #(
.INIT(64'h0001000000010001))
\wrap_second_len_r[0]_i_2__0
(.I0(\axaddr_offset_r_reg[0] ),
.I1(axaddr_offset_0[0]),
.I2(\axaddr_offset_r_reg[2]_0 ),
.I3(\wrap_second_len_r[3]_i_2__0_n_0 ),
.I4(\state_reg[1]_rep ),
.I5(\axaddr_offset_r_reg[3]_0 [2]),
.O(\wrap_cnt_r_reg[2] ));
LUT6 #(
.INIT(64'hF00EFFFFF00E0000))
\wrap_second_len_r[1]_i_1__0
(.I0(axaddr_offset_0[1]),
.I1(\axaddr_offset_r_reg[2]_0 ),
.I2(\axaddr_offset_r_reg[0] ),
.I3(axaddr_offset_0[0]),
.I4(\state_reg[1]_rep ),
.I5(\wrap_second_len_r_reg[3]_0 [1]),
.O(\wrap_second_len_r_reg[3] [0]));
LUT6 #(
.INIT(64'hCCC2FFFFCCC20000))
\wrap_second_len_r[2]_i_1__0
(.I0(axaddr_offset_0[1]),
.I1(\axaddr_offset_r_reg[2]_0 ),
.I2(axaddr_offset_0[0]),
.I3(\axaddr_offset_r_reg[0] ),
.I4(\state_reg[1]_rep ),
.I5(\wrap_second_len_r_reg[3]_0 [2]),
.O(\wrap_second_len_r_reg[3] [1]));
LUT6 #(
.INIT(64'hFE00FFFFFE00FE00))
\wrap_second_len_r[3]_i_1__0
(.I0(\axaddr_offset_r_reg[0] ),
.I1(axaddr_offset_0[0]),
.I2(\axaddr_offset_r_reg[2]_0 ),
.I3(\wrap_second_len_r[3]_i_2__0_n_0 ),
.I4(\state_reg[1]_rep ),
.I5(\wrap_second_len_r_reg[3]_0 [3]),
.O(\wrap_second_len_r_reg[3] [2]));
LUT6 #(
.INIT(64'hA8A8A8080808A808))
\wrap_second_len_r[3]_i_2__0
(.I0(\axlen_cnt_reg[3] ),
.I1(\wrap_second_len_r[3]_i_3__0_n_0 ),
.I2(Q[36]),
.I3(Q[5]),
.I4(Q[35]),
.I5(Q[6]),
.O(\wrap_second_len_r[3]_i_2__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\wrap_second_len_r[3]_i_3__0
(.I0(Q[4]),
.I1(Q[35]),
.I2(Q[3]),
.O(\wrap_second_len_r[3]_i_3__0_n_0 ));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_17_axic_register_slice" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice_0
(s_axi_awready,
s_ready_i_reg_0,
m_valid_i_reg_0,
\axlen_cnt_reg[3] ,
Q,
axaddr_incr,
D,
\wrap_second_len_r_reg[3] ,
\wrap_cnt_r_reg[2] ,
\axaddr_offset_r_reg[0] ,
axaddr_offset,
\wrap_cnt_r_reg[3] ,
\axaddr_offset_r_reg[2] ,
next_pending_r_reg,
\wrap_boundary_axaddr_r_reg[6] ,
\aresetn_d_reg[1]_inv ,
aclk,
\aresetn_d_reg[1]_inv_0 ,
aresetn,
\state_reg[1] ,
S,
\wrap_second_len_r_reg[3]_0 ,
\state_reg[1]_rep ,
\wrap_second_len_r_reg[1] ,
\axaddr_offset_r_reg[2]_0 ,
\axaddr_offset_r_reg[3] ,
\axaddr_offset_r_reg[3]_0 ,
\axaddr_offset_r_reg[2]_1 ,
\state_reg[0]_rep ,
\state_reg[1]_rep_0 ,
s_axi_awvalid,
b_push,
s_axi_awid,
s_axi_awlen,
s_axi_awburst,
s_axi_awsize,
s_axi_awprot,
s_axi_awaddr,
E);
output s_axi_awready;
output s_ready_i_reg_0;
output m_valid_i_reg_0;
output \axlen_cnt_reg[3] ;
output [54:0]Q;
output [11:0]axaddr_incr;
output [1:0]D;
output [2:0]\wrap_second_len_r_reg[3] ;
output \wrap_cnt_r_reg[2] ;
output \axaddr_offset_r_reg[0] ;
output [1:0]axaddr_offset;
output \wrap_cnt_r_reg[3] ;
output \axaddr_offset_r_reg[2] ;
output next_pending_r_reg;
output [6:0]\wrap_boundary_axaddr_r_reg[6] ;
output \aresetn_d_reg[1]_inv ;
input aclk;
input \aresetn_d_reg[1]_inv_0 ;
input aresetn;
input [1:0]\state_reg[1] ;
input [3:0]S;
input [3:0]\wrap_second_len_r_reg[3]_0 ;
input \state_reg[1]_rep ;
input \wrap_second_len_r_reg[1] ;
input [0:0]\axaddr_offset_r_reg[2]_0 ;
input [2:0]\axaddr_offset_r_reg[3] ;
input \axaddr_offset_r_reg[3]_0 ;
input \axaddr_offset_r_reg[2]_1 ;
input \state_reg[0]_rep ;
input \state_reg[1]_rep_0 ;
input s_axi_awvalid;
input b_push;
input [11:0]s_axi_awid;
input [3:0]s_axi_awlen;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awsize;
input [2:0]s_axi_awprot;
input [31:0]s_axi_awaddr;
input [0:0]E;
wire [1:0]D;
wire [0:0]E;
wire [54:0]Q;
wire [3:0]S;
wire aclk;
wire aresetn;
wire \aresetn_d_reg[1]_inv ;
wire \aresetn_d_reg[1]_inv_0 ;
wire \aresetn_d_reg_n_0_[0] ;
wire [11:0]axaddr_incr;
wire \axaddr_incr[3]_i_4_n_0 ;
wire \axaddr_incr[3]_i_5_n_0 ;
wire \axaddr_incr[3]_i_6_n_0 ;
wire \axaddr_incr_reg[11]_i_3_n_1 ;
wire \axaddr_incr_reg[11]_i_3_n_2 ;
wire \axaddr_incr_reg[11]_i_3_n_3 ;
wire \axaddr_incr_reg[3]_i_2_n_0 ;
wire \axaddr_incr_reg[3]_i_2_n_1 ;
wire \axaddr_incr_reg[3]_i_2_n_2 ;
wire \axaddr_incr_reg[3]_i_2_n_3 ;
wire \axaddr_incr_reg[7]_i_2_n_0 ;
wire \axaddr_incr_reg[7]_i_2_n_1 ;
wire \axaddr_incr_reg[7]_i_2_n_2 ;
wire \axaddr_incr_reg[7]_i_2_n_3 ;
wire [1:0]axaddr_offset;
wire \axaddr_offset_r[0]_i_2_n_0 ;
wire \axaddr_offset_r[1]_i_2_n_0 ;
wire \axaddr_offset_r[3]_i_2_n_0 ;
wire \axaddr_offset_r_reg[0] ;
wire \axaddr_offset_r_reg[2] ;
wire [0:0]\axaddr_offset_r_reg[2]_0 ;
wire \axaddr_offset_r_reg[2]_1 ;
wire [2:0]\axaddr_offset_r_reg[3] ;
wire \axaddr_offset_r_reg[3]_0 ;
wire \axlen_cnt_reg[3] ;
wire b_push;
wire m_valid_i0;
wire m_valid_i_reg_0;
wire next_pending_r_reg;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [3:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [1:0]s_axi_awsize;
wire s_axi_awvalid;
wire s_ready_i0;
wire s_ready_i_reg_0;
wire [61:0]skid_buffer;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[47] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[50] ;
wire \skid_buffer_reg_n_0_[51] ;
wire \skid_buffer_reg_n_0_[52] ;
wire \skid_buffer_reg_n_0_[53] ;
wire \skid_buffer_reg_n_0_[54] ;
wire \skid_buffer_reg_n_0_[55] ;
wire \skid_buffer_reg_n_0_[56] ;
wire \skid_buffer_reg_n_0_[57] ;
wire \skid_buffer_reg_n_0_[58] ;
wire \skid_buffer_reg_n_0_[59] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[60] ;
wire \skid_buffer_reg_n_0_[61] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
wire \state_reg[0]_rep ;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire \wrap_boundary_axaddr_r[3]_i_2_n_0 ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
wire \wrap_cnt_r[3]_i_5_n_0 ;
wire \wrap_cnt_r_reg[2] ;
wire \wrap_cnt_r_reg[3] ;
wire \wrap_second_len_r[3]_i_2_n_0 ;
wire \wrap_second_len_r[3]_i_3_n_0 ;
wire \wrap_second_len_r_reg[1] ;
wire [2:0]\wrap_second_len_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:3]\NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED ;
LUT2 #(
.INIT(4'h7))
\aresetn_d[1]_inv_i_1
(.I0(\aresetn_d_reg_n_0_[0] ),
.I1(aresetn),
.O(\aresetn_d_reg[1]_inv ));
FDRE #(
.INIT(1'b0))
\aresetn_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(aresetn),
.Q(\aresetn_d_reg_n_0_[0] ),
.R(1'b0));
LUT3 #(
.INIT(8'h2A))
\axaddr_incr[3]_i_4
(.I0(Q[2]),
.I1(Q[35]),
.I2(Q[36]),
.O(\axaddr_incr[3]_i_4_n_0 ));
LUT2 #(
.INIT(4'h2))
\axaddr_incr[3]_i_5
(.I0(Q[1]),
.I1(Q[36]),
.O(\axaddr_incr[3]_i_5_n_0 ));
LUT3 #(
.INIT(8'h02))
\axaddr_incr[3]_i_6
(.I0(Q[0]),
.I1(Q[35]),
.I2(Q[36]),
.O(\axaddr_incr[3]_i_6_n_0 ));
CARRY4 \axaddr_incr_reg[11]_i_3
(.CI(\axaddr_incr_reg[7]_i_2_n_0 ),
.CO({\NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED [3],\axaddr_incr_reg[11]_i_3_n_1 ,\axaddr_incr_reg[11]_i_3_n_2 ,\axaddr_incr_reg[11]_i_3_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(axaddr_incr[11:8]),
.S(Q[11:8]));
CARRY4 \axaddr_incr_reg[3]_i_2
(.CI(1'b0),
.CO({\axaddr_incr_reg[3]_i_2_n_0 ,\axaddr_incr_reg[3]_i_2_n_1 ,\axaddr_incr_reg[3]_i_2_n_2 ,\axaddr_incr_reg[3]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({Q[3],\axaddr_incr[3]_i_4_n_0 ,\axaddr_incr[3]_i_5_n_0 ,\axaddr_incr[3]_i_6_n_0 }),
.O(axaddr_incr[3:0]),
.S(S));
CARRY4 \axaddr_incr_reg[7]_i_2
(.CI(\axaddr_incr_reg[3]_i_2_n_0 ),
.CO({\axaddr_incr_reg[7]_i_2_n_0 ,\axaddr_incr_reg[7]_i_2_n_1 ,\axaddr_incr_reg[7]_i_2_n_2 ,\axaddr_incr_reg[7]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(axaddr_incr[7:4]),
.S(Q[7:4]));
LUT6 #(
.INIT(64'hFFFFF8FF00000800))
\axaddr_offset_r[0]_i_1
(.I0(\axaddr_offset_r[0]_i_2_n_0 ),
.I1(Q[39]),
.I2(\state_reg[1] [1]),
.I3(m_valid_i_reg_0),
.I4(\state_reg[1] [0]),
.I5(\axaddr_offset_r_reg[3] [0]),
.O(\axaddr_offset_r_reg[0] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[0]_i_2
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[36]),
.I3(Q[1]),
.I4(Q[35]),
.I5(Q[0]),
.O(\axaddr_offset_r[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFF8FF00000800))
\axaddr_offset_r[1]_i_1
(.I0(\axaddr_offset_r[1]_i_2_n_0 ),
.I1(Q[40]),
.I2(\state_reg[1] [1]),
.I3(m_valid_i_reg_0),
.I4(\state_reg[1] [0]),
.I5(\axaddr_offset_r_reg[3] [1]),
.O(axaddr_offset[0]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[1]_i_2
(.I0(Q[4]),
.I1(Q[3]),
.I2(Q[36]),
.I3(Q[2]),
.I4(Q[35]),
.I5(Q[1]),
.O(\axaddr_offset_r[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[2]_i_2
(.I0(Q[5]),
.I1(Q[4]),
.I2(Q[36]),
.I3(Q[3]),
.I4(Q[35]),
.I5(Q[2]),
.O(\axaddr_offset_r_reg[2] ));
LUT6 #(
.INIT(64'hFFFFF8FF00000800))
\axaddr_offset_r[3]_i_1
(.I0(\axaddr_offset_r[3]_i_2_n_0 ),
.I1(Q[42]),
.I2(\state_reg[1] [1]),
.I3(m_valid_i_reg_0),
.I4(\state_reg[1] [0]),
.I5(\axaddr_offset_r_reg[3] [2]),
.O(axaddr_offset[1]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[3]_i_2
(.I0(Q[6]),
.I1(Q[5]),
.I2(Q[36]),
.I3(Q[4]),
.I4(Q[35]),
.I5(Q[3]),
.O(\axaddr_offset_r[3]_i_2_n_0 ));
LUT4 #(
.INIT(16'h0020))
\axlen_cnt[3]_i_3
(.I0(Q[42]),
.I1(\state_reg[1] [0]),
.I2(m_valid_i_reg_0),
.I3(\state_reg[1] [1]),
.O(\axlen_cnt_reg[3] ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1
(.I0(s_axi_awaddr[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(skid_buffer[0]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1
(.I0(s_axi_awaddr[10]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(skid_buffer[10]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1
(.I0(s_axi_awaddr[11]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(skid_buffer[11]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1
(.I0(s_axi_awaddr[12]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(skid_buffer[12]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__0
(.I0(s_axi_awaddr[13]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(skid_buffer[13]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1
(.I0(s_axi_awaddr[14]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(skid_buffer[14]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1
(.I0(s_axi_awaddr[15]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(skid_buffer[15]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1
(.I0(s_axi_awaddr[16]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(skid_buffer[16]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1
(.I0(s_axi_awaddr[17]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(skid_buffer[17]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1
(.I0(s_axi_awaddr[18]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(skid_buffer[18]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1
(.I0(s_axi_awaddr[19]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(skid_buffer[19]));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1
(.I0(s_axi_awaddr[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(skid_buffer[1]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1
(.I0(s_axi_awaddr[20]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(skid_buffer[20]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1
(.I0(s_axi_awaddr[21]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(skid_buffer[21]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1
(.I0(s_axi_awaddr[22]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(skid_buffer[22]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1
(.I0(s_axi_awaddr[23]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(skid_buffer[23]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1
(.I0(s_axi_awaddr[24]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(skid_buffer[24]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1
(.I0(s_axi_awaddr[25]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(skid_buffer[25]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1
(.I0(s_axi_awaddr[26]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(skid_buffer[26]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1
(.I0(s_axi_awaddr[27]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(skid_buffer[27]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1
(.I0(s_axi_awaddr[28]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(skid_buffer[28]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1
(.I0(s_axi_awaddr[29]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(skid_buffer[29]));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1
(.I0(s_axi_awaddr[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(skid_buffer[2]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1
(.I0(s_axi_awaddr[30]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(skid_buffer[30]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_2
(.I0(s_axi_awaddr[31]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(skid_buffer[31]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1
(.I0(s_axi_awprot[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(skid_buffer[32]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1
(.I0(s_axi_awprot[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(skid_buffer[33]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1
(.I0(s_axi_awprot[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(skid_buffer[34]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1
(.I0(s_axi_awsize[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(skid_buffer[35]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1
(.I0(s_axi_awsize[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(skid_buffer[36]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1
(.I0(s_axi_awburst[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(skid_buffer[38]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1
(.I0(s_axi_awburst[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(skid_buffer[39]));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1
(.I0(s_axi_awaddr[3]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(skid_buffer[3]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1
(.I0(s_axi_awlen[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(skid_buffer[44]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1
(.I0(s_axi_awlen[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(skid_buffer[45]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_1__0
(.I0(s_axi_awlen[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(skid_buffer[46]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[47]_i_1
(.I0(s_axi_awlen[3]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[47] ),
.O(skid_buffer[47]));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1
(.I0(s_axi_awaddr[4]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(skid_buffer[4]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[50]_i_1
(.I0(s_axi_awid[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[50] ),
.O(skid_buffer[50]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[51]_i_1
(.I0(s_axi_awid[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[51] ),
.O(skid_buffer[51]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[52]_i_1
(.I0(s_axi_awid[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[52] ),
.O(skid_buffer[52]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[53]_i_1
(.I0(s_axi_awid[3]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[53] ),
.O(skid_buffer[53]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[54]_i_1
(.I0(s_axi_awid[4]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[54] ),
.O(skid_buffer[54]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[55]_i_1
(.I0(s_axi_awid[5]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[55] ),
.O(skid_buffer[55]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[56]_i_1
(.I0(s_axi_awid[6]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[56] ),
.O(skid_buffer[56]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[57]_i_1
(.I0(s_axi_awid[7]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[57] ),
.O(skid_buffer[57]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[58]_i_1
(.I0(s_axi_awid[8]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[58] ),
.O(skid_buffer[58]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[59]_i_1
(.I0(s_axi_awid[9]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[59] ),
.O(skid_buffer[59]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1
(.I0(s_axi_awaddr[5]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(skid_buffer[5]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[60]_i_1
(.I0(s_axi_awid[10]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[60] ),
.O(skid_buffer[60]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[61]_i_1
(.I0(s_axi_awid[11]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[61] ),
.O(skid_buffer[61]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1
(.I0(s_axi_awaddr[6]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(skid_buffer[6]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1
(.I0(s_axi_awaddr[7]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(skid_buffer[7]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1
(.I0(s_axi_awaddr[8]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(skid_buffer[8]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1
(.I0(s_axi_awaddr[9]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(skid_buffer[9]));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(E),
.D(skid_buffer[0]),
.Q(Q[0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(E),
.D(skid_buffer[10]),
.Q(Q[10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(E),
.D(skid_buffer[11]),
.Q(Q[11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(E),
.D(skid_buffer[12]),
.Q(Q[12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(E),
.D(skid_buffer[13]),
.Q(Q[13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(E),
.D(skid_buffer[14]),
.Q(Q[14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(E),
.D(skid_buffer[15]),
.Q(Q[15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(E),
.D(skid_buffer[16]),
.Q(Q[16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(E),
.D(skid_buffer[17]),
.Q(Q[17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(E),
.D(skid_buffer[18]),
.Q(Q[18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(E),
.D(skid_buffer[19]),
.Q(Q[19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(E),
.D(skid_buffer[1]),
.Q(Q[1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(E),
.D(skid_buffer[20]),
.Q(Q[20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(E),
.D(skid_buffer[21]),
.Q(Q[21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(E),
.D(skid_buffer[22]),
.Q(Q[22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(E),
.D(skid_buffer[23]),
.Q(Q[23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(E),
.D(skid_buffer[24]),
.Q(Q[24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(E),
.D(skid_buffer[25]),
.Q(Q[25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(E),
.D(skid_buffer[26]),
.Q(Q[26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(E),
.D(skid_buffer[27]),
.Q(Q[27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(E),
.D(skid_buffer[28]),
.Q(Q[28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(E),
.D(skid_buffer[29]),
.Q(Q[29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(E),
.D(skid_buffer[2]),
.Q(Q[2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(E),
.D(skid_buffer[30]),
.Q(Q[30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(E),
.D(skid_buffer[31]),
.Q(Q[31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(E),
.D(skid_buffer[32]),
.Q(Q[32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(E),
.D(skid_buffer[33]),
.Q(Q[33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(E),
.D(skid_buffer[34]),
.Q(Q[34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(E),
.D(skid_buffer[35]),
.Q(Q[35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(E),
.D(skid_buffer[36]),
.Q(Q[36]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(E),
.D(skid_buffer[38]),
.Q(Q[37]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(E),
.D(skid_buffer[39]),
.Q(Q[38]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(E),
.D(skid_buffer[3]),
.Q(Q[3]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(E),
.D(skid_buffer[44]),
.Q(Q[39]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(E),
.D(skid_buffer[45]),
.Q(Q[40]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(E),
.D(skid_buffer[46]),
.Q(Q[41]),
.R(1'b0));
FDRE \m_payload_i_reg[47]
(.C(aclk),
.CE(E),
.D(skid_buffer[47]),
.Q(Q[42]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(E),
.D(skid_buffer[4]),
.Q(Q[4]),
.R(1'b0));
FDRE \m_payload_i_reg[50]
(.C(aclk),
.CE(E),
.D(skid_buffer[50]),
.Q(Q[43]),
.R(1'b0));
FDRE \m_payload_i_reg[51]
(.C(aclk),
.CE(E),
.D(skid_buffer[51]),
.Q(Q[44]),
.R(1'b0));
FDRE \m_payload_i_reg[52]
(.C(aclk),
.CE(E),
.D(skid_buffer[52]),
.Q(Q[45]),
.R(1'b0));
FDRE \m_payload_i_reg[53]
(.C(aclk),
.CE(E),
.D(skid_buffer[53]),
.Q(Q[46]),
.R(1'b0));
FDRE \m_payload_i_reg[54]
(.C(aclk),
.CE(E),
.D(skid_buffer[54]),
.Q(Q[47]),
.R(1'b0));
FDRE \m_payload_i_reg[55]
(.C(aclk),
.CE(E),
.D(skid_buffer[55]),
.Q(Q[48]),
.R(1'b0));
FDRE \m_payload_i_reg[56]
(.C(aclk),
.CE(E),
.D(skid_buffer[56]),
.Q(Q[49]),
.R(1'b0));
FDRE \m_payload_i_reg[57]
(.C(aclk),
.CE(E),
.D(skid_buffer[57]),
.Q(Q[50]),
.R(1'b0));
FDRE \m_payload_i_reg[58]
(.C(aclk),
.CE(E),
.D(skid_buffer[58]),
.Q(Q[51]),
.R(1'b0));
FDRE \m_payload_i_reg[59]
(.C(aclk),
.CE(E),
.D(skid_buffer[59]),
.Q(Q[52]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(E),
.D(skid_buffer[5]),
.Q(Q[5]),
.R(1'b0));
FDRE \m_payload_i_reg[60]
(.C(aclk),
.CE(E),
.D(skid_buffer[60]),
.Q(Q[53]),
.R(1'b0));
FDRE \m_payload_i_reg[61]
(.C(aclk),
.CE(E),
.D(skid_buffer[61]),
.Q(Q[54]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(E),
.D(skid_buffer[6]),
.Q(Q[6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(E),
.D(skid_buffer[7]),
.Q(Q[7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(E),
.D(skid_buffer[8]),
.Q(Q[8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(E),
.D(skid_buffer[9]),
.Q(Q[9]),
.R(1'b0));
LUT4 #(
.INIT(16'hF4FF))
m_valid_i_i_1
(.I0(b_push),
.I1(m_valid_i_reg_0),
.I2(s_axi_awvalid),
.I3(s_axi_awready),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(m_valid_i_reg_0),
.R(\aresetn_d_reg[1]_inv_0 ));
LUT5 #(
.INIT(32'hAAAAAAA8))
next_pending_r_i_4
(.I0(\state_reg[1]_rep ),
.I1(Q[42]),
.I2(Q[40]),
.I3(Q[39]),
.I4(Q[41]),
.O(next_pending_r_reg));
LUT1 #(
.INIT(2'h1))
s_ready_i_i_1__1
(.I0(\aresetn_d_reg_n_0_[0] ),
.O(s_ready_i_reg_0));
LUT4 #(
.INIT(16'hF4FF))
s_ready_i_i_2
(.I0(s_axi_awvalid),
.I1(s_axi_awready),
.I2(b_push),
.I3(m_valid_i_reg_0),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(s_axi_awready),
.R(s_ready_i_reg_0));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awprot[0]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awprot[1]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awprot[2]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awsize[0]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awsize[1]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awburst[0]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awburst[1]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[0]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[1]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[2]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[47]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[3]),
.Q(\skid_buffer_reg_n_0_[47] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[50]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[0]),
.Q(\skid_buffer_reg_n_0_[50] ),
.R(1'b0));
FDRE \skid_buffer_reg[51]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[1]),
.Q(\skid_buffer_reg_n_0_[51] ),
.R(1'b0));
FDRE \skid_buffer_reg[52]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[2]),
.Q(\skid_buffer_reg_n_0_[52] ),
.R(1'b0));
FDRE \skid_buffer_reg[53]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[3]),
.Q(\skid_buffer_reg_n_0_[53] ),
.R(1'b0));
FDRE \skid_buffer_reg[54]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[4]),
.Q(\skid_buffer_reg_n_0_[54] ),
.R(1'b0));
FDRE \skid_buffer_reg[55]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[5]),
.Q(\skid_buffer_reg_n_0_[55] ),
.R(1'b0));
FDRE \skid_buffer_reg[56]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[6]),
.Q(\skid_buffer_reg_n_0_[56] ),
.R(1'b0));
FDRE \skid_buffer_reg[57]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[7]),
.Q(\skid_buffer_reg_n_0_[57] ),
.R(1'b0));
FDRE \skid_buffer_reg[58]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[8]),
.Q(\skid_buffer_reg_n_0_[58] ),
.R(1'b0));
FDRE \skid_buffer_reg[59]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[9]),
.Q(\skid_buffer_reg_n_0_[59] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[60]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[10]),
.Q(\skid_buffer_reg_n_0_[60] ),
.R(1'b0));
FDRE \skid_buffer_reg[61]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[11]),
.Q(\skid_buffer_reg_n_0_[61] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'hAA8A))
\wrap_boundary_axaddr_r[0]_i_1
(.I0(Q[0]),
.I1(Q[35]),
.I2(Q[39]),
.I3(Q[36]),
.O(\wrap_boundary_axaddr_r_reg[6] [0]));
LUT5 #(
.INIT(32'h8A888AAA))
\wrap_boundary_axaddr_r[1]_i_1
(.I0(Q[1]),
.I1(Q[36]),
.I2(Q[39]),
.I3(Q[35]),
.I4(Q[40]),
.O(\wrap_boundary_axaddr_r_reg[6] [1]));
LUT6 #(
.INIT(64'hFF0F553300000000))
\wrap_boundary_axaddr_r[2]_i_1
(.I0(Q[40]),
.I1(Q[41]),
.I2(Q[39]),
.I3(Q[35]),
.I4(Q[36]),
.I5(Q[2]),
.O(\wrap_boundary_axaddr_r_reg[6] [2]));
LUT6 #(
.INIT(64'h020202A2A2A202A2))
\wrap_boundary_axaddr_r[3]_i_1
(.I0(Q[3]),
.I1(\wrap_boundary_axaddr_r[3]_i_2_n_0 ),
.I2(Q[36]),
.I3(Q[40]),
.I4(Q[35]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [3]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\wrap_boundary_axaddr_r[3]_i_2
(.I0(Q[41]),
.I1(Q[35]),
.I2(Q[42]),
.O(\wrap_boundary_axaddr_r[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h503F5F3F00000000))
\wrap_boundary_axaddr_r[4]_i_1
(.I0(Q[40]),
.I1(Q[41]),
.I2(Q[36]),
.I3(Q[35]),
.I4(Q[42]),
.I5(Q[4]),
.O(\wrap_boundary_axaddr_r_reg[6] [4]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT5 #(
.INIT(32'h2A222AAA))
\wrap_boundary_axaddr_r[5]_i_1
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[41]),
.I3(Q[35]),
.I4(Q[42]),
.O(\wrap_boundary_axaddr_r_reg[6] [5]));
LUT4 #(
.INIT(16'h2AAA))
\wrap_boundary_axaddr_r[6]_i_1
(.I0(Q[6]),
.I1(Q[42]),
.I2(Q[35]),
.I3(Q[36]),
.O(\wrap_boundary_axaddr_r_reg[6] [6]));
LUT6 #(
.INIT(64'hAAA6AA56AAAAAAAA))
\wrap_cnt_r[2]_i_1
(.I0(\wrap_second_len_r_reg[3] [1]),
.I1(\wrap_second_len_r_reg[3]_0 [0]),
.I2(\state_reg[1]_rep ),
.I3(\wrap_cnt_r_reg[2] ),
.I4(\axaddr_offset_r_reg[0] ),
.I5(\wrap_second_len_r_reg[3] [0]),
.O(D[0]));
LUT3 #(
.INIT(8'h6A))
\wrap_cnt_r[3]_i_1
(.I0(\wrap_second_len_r_reg[3] [2]),
.I1(\wrap_second_len_r_reg[1] ),
.I2(\wrap_second_len_r_reg[3] [1]),
.O(D[1]));
LUT6 #(
.INIT(64'hFFFFFFFFEAEAFFEA))
\wrap_cnt_r[3]_i_3
(.I0(\axaddr_offset_r_reg[3]_0 ),
.I1(\axlen_cnt_reg[3] ),
.I2(\axaddr_offset_r[3]_i_2_n_0 ),
.I3(\axaddr_offset_r_reg[2] ),
.I4(\wrap_cnt_r[3]_i_5_n_0 ),
.I5(\axaddr_offset_r_reg[2]_1 ),
.O(\wrap_cnt_r_reg[3] ));
LUT4 #(
.INIT(16'hFFDF))
\wrap_cnt_r[3]_i_5
(.I0(Q[41]),
.I1(\state_reg[0]_rep ),
.I2(m_valid_i_reg_0),
.I3(\state_reg[1]_rep_0 ),
.O(\wrap_cnt_r[3]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0001000000010001))
\wrap_second_len_r[0]_i_2
(.I0(\axaddr_offset_r_reg[0] ),
.I1(axaddr_offset[0]),
.I2(\axaddr_offset_r_reg[2]_0 ),
.I3(\wrap_second_len_r[3]_i_2_n_0 ),
.I4(\state_reg[1]_rep ),
.I5(\axaddr_offset_r_reg[3] [2]),
.O(\wrap_cnt_r_reg[2] ));
LUT6 #(
.INIT(64'hF00EFFFFF00E0000))
\wrap_second_len_r[1]_i_1
(.I0(axaddr_offset[1]),
.I1(\axaddr_offset_r_reg[2]_0 ),
.I2(\axaddr_offset_r_reg[0] ),
.I3(axaddr_offset[0]),
.I4(\state_reg[1]_rep ),
.I5(\wrap_second_len_r_reg[3]_0 [1]),
.O(\wrap_second_len_r_reg[3] [0]));
LUT6 #(
.INIT(64'hCCC2FFFFCCC20000))
\wrap_second_len_r[2]_i_1
(.I0(axaddr_offset[1]),
.I1(\axaddr_offset_r_reg[2]_0 ),
.I2(axaddr_offset[0]),
.I3(\axaddr_offset_r_reg[0] ),
.I4(\state_reg[1]_rep ),
.I5(\wrap_second_len_r_reg[3]_0 [2]),
.O(\wrap_second_len_r_reg[3] [1]));
LUT6 #(
.INIT(64'hFE00FFFFFE00FE00))
\wrap_second_len_r[3]_i_1
(.I0(\axaddr_offset_r_reg[0] ),
.I1(axaddr_offset[0]),
.I2(\axaddr_offset_r_reg[2]_0 ),
.I3(\wrap_second_len_r[3]_i_2_n_0 ),
.I4(\state_reg[1]_rep ),
.I5(\wrap_second_len_r_reg[3]_0 [3]),
.O(\wrap_second_len_r_reg[3] [2]));
LUT6 #(
.INIT(64'hA8A8A8080808A808))
\wrap_second_len_r[3]_i_2
(.I0(\axlen_cnt_reg[3] ),
.I1(\wrap_second_len_r[3]_i_3_n_0 ),
.I2(Q[36]),
.I3(Q[5]),
.I4(Q[35]),
.I5(Q[6]),
.O(\wrap_second_len_r[3]_i_2_n_0 ));
LUT3 #(
.INIT(8'hB8))
\wrap_second_len_r[3]_i_3
(.I0(Q[4]),
.I1(Q[35]),
.I2(Q[3]),
.O(\wrap_second_len_r[3]_i_3_n_0 ));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_17_axic_register_slice" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice__parameterized1
(s_axi_bvalid,
\skid_buffer_reg[0]_0 ,
\s_axi_bid[11] ,
\aresetn_d_reg[1]_inv ,
aclk,
\aresetn_d_reg[0] ,
si_rs_bvalid,
s_axi_bready,
out,
\s_bresp_acc_reg[1] );
output s_axi_bvalid;
output \skid_buffer_reg[0]_0 ;
output [13:0]\s_axi_bid[11] ;
input \aresetn_d_reg[1]_inv ;
input aclk;
input \aresetn_d_reg[0] ;
input si_rs_bvalid;
input s_axi_bready;
input [11:0]out;
input [1:0]\s_bresp_acc_reg[1] ;
wire aclk;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[1]_inv ;
wire \m_payload_i[0]_i_1__1_n_0 ;
wire \m_payload_i[10]_i_1__1_n_0 ;
wire \m_payload_i[11]_i_1__1_n_0 ;
wire \m_payload_i[12]_i_1__1_n_0 ;
wire \m_payload_i[13]_i_2_n_0 ;
wire \m_payload_i[1]_i_1__1_n_0 ;
wire \m_payload_i[2]_i_1__1_n_0 ;
wire \m_payload_i[3]_i_1__1_n_0 ;
wire \m_payload_i[4]_i_1__1_n_0 ;
wire \m_payload_i[5]_i_1__1_n_0 ;
wire \m_payload_i[6]_i_1__1_n_0 ;
wire \m_payload_i[7]_i_1__1_n_0 ;
wire \m_payload_i[8]_i_1__1_n_0 ;
wire \m_payload_i[9]_i_1__1_n_0 ;
wire m_valid_i0;
wire [11:0]out;
wire p_1_in;
wire [13:0]\s_axi_bid[11] ;
wire s_axi_bready;
wire s_axi_bvalid;
wire [1:0]\s_bresp_acc_reg[1] ;
wire s_ready_i0;
wire si_rs_bvalid;
wire \skid_buffer_reg[0]_0 ;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__1
(.I0(\s_bresp_acc_reg[1] [0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(\m_payload_i[0]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__1
(.I0(out[8]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(\m_payload_i[10]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__1
(.I0(out[9]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(\m_payload_i[11]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__1
(.I0(out[10]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(\m_payload_i[12]_i_1__1_n_0 ));
LUT2 #(
.INIT(4'hB))
\m_payload_i[13]_i_1
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.O(p_1_in));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_2
(.I0(out[11]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(\m_payload_i[13]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__1
(.I0(\s_bresp_acc_reg[1] [1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(\m_payload_i[1]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__1
(.I0(out[0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(\m_payload_i[2]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__1
(.I0(out[1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(\m_payload_i[3]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__1
(.I0(out[2]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(\m_payload_i[4]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__1
(.I0(out[3]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(\m_payload_i[5]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__1
(.I0(out[4]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(\m_payload_i[6]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__1
(.I0(out[5]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(\m_payload_i[7]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__1
(.I0(out[6]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(\m_payload_i[8]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__1
(.I0(out[7]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(\m_payload_i[9]_i_1__1_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[0]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[10]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[11]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[12]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[13]_i_2_n_0 ),
.Q(\s_axi_bid[11] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[1]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[2]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[3]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[4]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[5]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[6]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[7]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[8]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[9]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [9]),
.R(1'b0));
LUT4 #(
.INIT(16'hF4FF))
m_valid_i_i_1__0
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.I2(si_rs_bvalid),
.I3(\skid_buffer_reg[0]_0 ),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(s_axi_bvalid),
.R(\aresetn_d_reg[1]_inv ));
LUT4 #(
.INIT(16'hF4FF))
s_ready_i_i_1
(.I0(si_rs_bvalid),
.I1(\skid_buffer_reg[0]_0 ),
.I2(s_axi_bready),
.I3(s_axi_bvalid),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(\skid_buffer_reg[0]_0 ),
.R(\aresetn_d_reg[0] ));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\s_bresp_acc_reg[1] [0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[8]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[9]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[10]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[11]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\s_bresp_acc_reg[1] [1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[0]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[1]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[2]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[3]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[4]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[5]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[6]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[7]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_17_axic_register_slice" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_17_axic_register_slice__parameterized2
(s_axi_rvalid,
\skid_buffer_reg[0]_0 ,
\cnt_read_reg[2]_rep__0 ,
\s_axi_rid[11] ,
\aresetn_d_reg[1]_inv ,
aclk,
\aresetn_d_reg[0] ,
\cnt_read_reg[4]_rep__0 ,
s_axi_rready,
r_push_r_reg,
\cnt_read_reg[4] );
output s_axi_rvalid;
output \skid_buffer_reg[0]_0 ;
output \cnt_read_reg[2]_rep__0 ;
output [46:0]\s_axi_rid[11] ;
input \aresetn_d_reg[1]_inv ;
input aclk;
input \aresetn_d_reg[0] ;
input \cnt_read_reg[4]_rep__0 ;
input s_axi_rready;
input [12:0]r_push_r_reg;
input [33:0]\cnt_read_reg[4] ;
wire aclk;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[1]_inv ;
wire \cnt_read_reg[2]_rep__0 ;
wire [33:0]\cnt_read_reg[4] ;
wire \cnt_read_reg[4]_rep__0 ;
wire \m_payload_i[0]_i_1__2_n_0 ;
wire \m_payload_i[10]_i_1__2_n_0 ;
wire \m_payload_i[11]_i_1__2_n_0 ;
wire \m_payload_i[12]_i_1__2_n_0 ;
wire \m_payload_i[13]_i_1__2_n_0 ;
wire \m_payload_i[14]_i_1__1_n_0 ;
wire \m_payload_i[15]_i_1__1_n_0 ;
wire \m_payload_i[16]_i_1__1_n_0 ;
wire \m_payload_i[17]_i_1__1_n_0 ;
wire \m_payload_i[18]_i_1__1_n_0 ;
wire \m_payload_i[19]_i_1__1_n_0 ;
wire \m_payload_i[1]_i_1__2_n_0 ;
wire \m_payload_i[20]_i_1__1_n_0 ;
wire \m_payload_i[21]_i_1__1_n_0 ;
wire \m_payload_i[22]_i_1__1_n_0 ;
wire \m_payload_i[23]_i_1__1_n_0 ;
wire \m_payload_i[24]_i_1__1_n_0 ;
wire \m_payload_i[25]_i_1__1_n_0 ;
wire \m_payload_i[26]_i_1__1_n_0 ;
wire \m_payload_i[27]_i_1__1_n_0 ;
wire \m_payload_i[28]_i_1__1_n_0 ;
wire \m_payload_i[29]_i_1__1_n_0 ;
wire \m_payload_i[2]_i_1__2_n_0 ;
wire \m_payload_i[30]_i_1__1_n_0 ;
wire \m_payload_i[31]_i_1__1_n_0 ;
wire \m_payload_i[32]_i_1__1_n_0 ;
wire \m_payload_i[33]_i_1__1_n_0 ;
wire \m_payload_i[34]_i_1__1_n_0 ;
wire \m_payload_i[35]_i_1__1_n_0 ;
wire \m_payload_i[36]_i_1__1_n_0 ;
wire \m_payload_i[37]_i_1_n_0 ;
wire \m_payload_i[38]_i_1__1_n_0 ;
wire \m_payload_i[39]_i_1__1_n_0 ;
wire \m_payload_i[3]_i_1__2_n_0 ;
wire \m_payload_i[40]_i_1_n_0 ;
wire \m_payload_i[41]_i_1_n_0 ;
wire \m_payload_i[42]_i_1_n_0 ;
wire \m_payload_i[43]_i_1_n_0 ;
wire \m_payload_i[44]_i_1__1_n_0 ;
wire \m_payload_i[45]_i_1__1_n_0 ;
wire \m_payload_i[46]_i_2_n_0 ;
wire \m_payload_i[4]_i_1__2_n_0 ;
wire \m_payload_i[5]_i_1__2_n_0 ;
wire \m_payload_i[6]_i_1__2_n_0 ;
wire \m_payload_i[7]_i_1__2_n_0 ;
wire \m_payload_i[8]_i_1__2_n_0 ;
wire \m_payload_i[9]_i_1__2_n_0 ;
wire m_valid_i_i_1__2_n_0;
wire p_1_in;
wire [12:0]r_push_r_reg;
wire [46:0]\s_axi_rid[11] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_ready_i_i_1__2_n_0;
wire \skid_buffer_reg[0]_0 ;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[37] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[40] ;
wire \skid_buffer_reg_n_0_[41] ;
wire \skid_buffer_reg_n_0_[42] ;
wire \skid_buffer_reg_n_0_[43] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT2 #(
.INIT(4'h2))
\cnt_read[4]_i_4
(.I0(\skid_buffer_reg[0]_0 ),
.I1(\cnt_read_reg[4]_rep__0 ),
.O(\cnt_read_reg[2]_rep__0 ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__2
(.I0(\cnt_read_reg[4] [0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(\m_payload_i[0]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__2
(.I0(\cnt_read_reg[4] [10]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(\m_payload_i[10]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__2
(.I0(\cnt_read_reg[4] [11]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(\m_payload_i[11]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__2
(.I0(\cnt_read_reg[4] [12]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(\m_payload_i[12]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__2
(.I0(\cnt_read_reg[4] [13]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(\m_payload_i[13]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1__1
(.I0(\cnt_read_reg[4] [14]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(\m_payload_i[14]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1__1
(.I0(\cnt_read_reg[4] [15]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(\m_payload_i[15]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1__1
(.I0(\cnt_read_reg[4] [16]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(\m_payload_i[16]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1__1
(.I0(\cnt_read_reg[4] [17]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(\m_payload_i[17]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1__1
(.I0(\cnt_read_reg[4] [18]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(\m_payload_i[18]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1__1
(.I0(\cnt_read_reg[4] [19]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(\m_payload_i[19]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__2
(.I0(\cnt_read_reg[4] [1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(\m_payload_i[1]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1__1
(.I0(\cnt_read_reg[4] [20]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(\m_payload_i[20]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1__1
(.I0(\cnt_read_reg[4] [21]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(\m_payload_i[21]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1__1
(.I0(\cnt_read_reg[4] [22]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(\m_payload_i[22]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1__1
(.I0(\cnt_read_reg[4] [23]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(\m_payload_i[23]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1__1
(.I0(\cnt_read_reg[4] [24]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(\m_payload_i[24]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1__1
(.I0(\cnt_read_reg[4] [25]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(\m_payload_i[25]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1__1
(.I0(\cnt_read_reg[4] [26]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(\m_payload_i[26]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1__1
(.I0(\cnt_read_reg[4] [27]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(\m_payload_i[27]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1__1
(.I0(\cnt_read_reg[4] [28]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(\m_payload_i[28]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1__1
(.I0(\cnt_read_reg[4] [29]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(\m_payload_i[29]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__2
(.I0(\cnt_read_reg[4] [2]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(\m_payload_i[2]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1__1
(.I0(\cnt_read_reg[4] [30]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(\m_payload_i[30]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_1__1
(.I0(\cnt_read_reg[4] [31]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(\m_payload_i[31]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1__1
(.I0(\cnt_read_reg[4] [32]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(\m_payload_i[32]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1__1
(.I0(\cnt_read_reg[4] [33]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(\m_payload_i[33]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1__1
(.I0(r_push_r_reg[0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(\m_payload_i[34]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1__1
(.I0(r_push_r_reg[1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(\m_payload_i[35]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1__1
(.I0(r_push_r_reg[2]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(\m_payload_i[36]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[37]_i_1
(.I0(r_push_r_reg[3]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[37] ),
.O(\m_payload_i[37]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1__1
(.I0(r_push_r_reg[4]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(\m_payload_i[38]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1__1
(.I0(r_push_r_reg[5]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(\m_payload_i[39]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__2
(.I0(\cnt_read_reg[4] [3]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(\m_payload_i[3]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[40]_i_1
(.I0(r_push_r_reg[6]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[40] ),
.O(\m_payload_i[40]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[41]_i_1
(.I0(r_push_r_reg[7]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[41] ),
.O(\m_payload_i[41]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[42]_i_1
(.I0(r_push_r_reg[8]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[42] ),
.O(\m_payload_i[42]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[43]_i_1
(.I0(r_push_r_reg[9]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[43] ),
.O(\m_payload_i[43]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1__1
(.I0(r_push_r_reg[10]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(\m_payload_i[44]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1__1
(.I0(r_push_r_reg[11]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(\m_payload_i[45]_i_1__1_n_0 ));
LUT2 #(
.INIT(4'hB))
\m_payload_i[46]_i_1
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.O(p_1_in));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_2
(.I0(r_push_r_reg[12]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(\m_payload_i[46]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__2
(.I0(\cnt_read_reg[4] [4]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(\m_payload_i[4]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__2
(.I0(\cnt_read_reg[4] [5]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(\m_payload_i[5]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__2
(.I0(\cnt_read_reg[4] [6]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(\m_payload_i[6]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__2
(.I0(\cnt_read_reg[4] [7]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(\m_payload_i[7]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__2
(.I0(\cnt_read_reg[4] [8]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(\m_payload_i[8]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__2
(.I0(\cnt_read_reg[4] [9]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(\m_payload_i[9]_i_1__2_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[0]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[10]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[11]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[12]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[13]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[14]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[15]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[16]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[17]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[18]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[19]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[1]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[20]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[21]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[22]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[23]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[24]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[25]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[26]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[27]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[28]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[29]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[2]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[30]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[31]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[32]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[33]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[34]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[35]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[36]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [36]),
.R(1'b0));
FDRE \m_payload_i_reg[37]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[37]_i_1_n_0 ),
.Q(\s_axi_rid[11] [37]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[38]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [38]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[39]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [39]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[3]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[40]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[40]_i_1_n_0 ),
.Q(\s_axi_rid[11] [40]),
.R(1'b0));
FDRE \m_payload_i_reg[41]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[41]_i_1_n_0 ),
.Q(\s_axi_rid[11] [41]),
.R(1'b0));
FDRE \m_payload_i_reg[42]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[42]_i_1_n_0 ),
.Q(\s_axi_rid[11] [42]),
.R(1'b0));
FDRE \m_payload_i_reg[43]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[43]_i_1_n_0 ),
.Q(\s_axi_rid[11] [43]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[44]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [44]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[45]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [45]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[46]_i_2_n_0 ),
.Q(\s_axi_rid[11] [46]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[4]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[5]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[6]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[7]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[8]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[9]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [9]),
.R(1'b0));
LUT4 #(
.INIT(16'h4FFF))
m_valid_i_i_1__2
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.I2(\cnt_read_reg[4]_rep__0 ),
.I3(\skid_buffer_reg[0]_0 ),
.O(m_valid_i_i_1__2_n_0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i_i_1__2_n_0),
.Q(s_axi_rvalid),
.R(\aresetn_d_reg[1]_inv ));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT4 #(
.INIT(16'hF8FF))
s_ready_i_i_1__2
(.I0(\cnt_read_reg[4]_rep__0 ),
.I1(\skid_buffer_reg[0]_0 ),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.O(s_ready_i_i_1__2_n_0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i_i_1__2_n_0),
.Q(\skid_buffer_reg[0]_0 ),
.R(\aresetn_d_reg[0] ));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [32]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [33]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[0]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[1]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[2]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[37]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[3]),
.Q(\skid_buffer_reg_n_0_[37] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[4]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[5]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[40]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[6]),
.Q(\skid_buffer_reg_n_0_[40] ),
.R(1'b0));
FDRE \skid_buffer_reg[41]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[7]),
.Q(\skid_buffer_reg_n_0_[41] ),
.R(1'b0));
FDRE \skid_buffer_reg[42]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[8]),
.Q(\skid_buffer_reg_n_0_[42] ),
.R(1'b0));
FDRE \skid_buffer_reg[43]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[9]),
.Q(\skid_buffer_reg_n_0_[43] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[10]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[11]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[12]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule
(* CHECK_LICENSE_TYPE = "gcd_block_design_auto_pc_1,axi_protocol_converter_v2_1_17_axi_protocol_converter,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_protocol_converter_v2_1_17_axi_protocol_converter,Vivado 2018.2" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_2_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN" *) input aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT" *) input aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *) input [11:0]s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [31:0]s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *) input [3:0]s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *) input [2:0]s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *) input [1:0]s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *) input [1:0]s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *) input [3:0]s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) input [2:0]s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *) input [3:0]s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *) input [11:0]s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *) input s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *) output [11:0]s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *) input [11:0]s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [31:0]s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) input [3:0]s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) input [2:0]s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *) input [1:0]s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *) input [1:0]s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *) input [3:0]s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *) input [3:0]s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *) output [11:0]s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) output s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_2_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) output [31:0]m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) output [2:0]m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) output m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) input m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) output [31:0]m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) output [3:0]m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) output m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) input m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) input [1:0]m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output [31:0]m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) output [2:0]m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) output m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) input m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input [31:0]m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) input [1:0]m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) input m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_2_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) output m_axi_rready;
wire aclk;
wire aresetn;
wire [31:0]m_axi_araddr;
wire [2:0]m_axi_arprot;
wire m_axi_arready;
wire m_axi_arvalid;
wire [31:0]m_axi_awaddr;
wire [2:0]m_axi_awprot;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire [31:0]m_axi_wdata;
wire m_axi_wready;
wire [3:0]m_axi_wstrb;
wire m_axi_wvalid;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [11:0]s_axi_arid;
wire [3:0]s_axi_arlen;
wire [1:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire s_axi_arready;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [11:0]s_axi_awid;
wire [3:0]s_axi_awlen;
wire [1:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire s_axi_awready;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [11:0]s_axi_wid;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire NLW_inst_m_axi_wlast_UNCONNECTED;
wire [1:0]NLW_inst_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arcache_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_inst_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_arlock_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_aruser_UNCONNECTED;
wire [1:0]NLW_inst_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awcache_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_inst_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_awlock_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_awuser_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_wid_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_wuser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "32" *)
(* C_AXI_ID_WIDTH = "12" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_SUPPORTS_READ = "1" *)
(* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_SUPPORTS_WRITE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_FAMILY = "zynq" *)
(* C_IGNORE_ID = "0" *)
(* C_M_AXI_PROTOCOL = "2" *)
(* C_S_AXI_PROTOCOL = "1" *)
(* C_TRANSLATION_MODE = "2" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
(* P_AXI3 = "1" *)
(* P_AXI4 = "0" *)
(* P_AXILITE = "2" *)
(* P_AXILITE_SIZE = "3'b010" *)
(* P_CONVERSION = "2" *)
(* P_DECERR = "2'b11" *)
(* P_INCR = "2'b01" *)
(* P_PROTECTION = "1" *)
(* P_SLVERR = "2'b10" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_17_axi_protocol_converter inst
(.aclk(aclk),
.aresetn(aresetn),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(NLW_inst_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_inst_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[11:0]),
.m_axi_arlen(NLW_inst_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_inst_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(NLW_inst_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(m_axi_arready),
.m_axi_arregion(NLW_inst_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_inst_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[11:0]),
.m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(m_axi_awready),
.m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_inst_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'b0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rlast(1'b1),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_ruser(1'b0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[11:0]),
.m_axi_wlast(NLW_inst_m_axi_wlast_UNCONNECTED),
.m_axi_wready(m_axi_wready),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(m_axi_wvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arcache(s_axi_arcache),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arlock(s_axi_arlock),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_arready(s_axi_arready),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize(s_axi_arsize),
.s_axi_aruser(1'b0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awcache(s_axi_awcache),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awlock(s_axi_awlock),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awready(s_axi_awready),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize(s_axi_awsize),
.s_axi_awuser(1'b0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wid(s_axi_wid),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wuser(1'b0),
.s_axi_wvalid(s_axi_wvalid));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Tue Nov 8 02:15:24 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire n3682, Shift_reg_FLAGS_7_6, Shift_reg_FLAGS_7_5, intAS, OP_FLAG_EXP,
ZERO_FLAG_EXP, SIGN_FLAG_SHT1, OP_FLAG_SHT1, ZERO_FLAG_SHT1,
left_right_SHT2, bit_shift_SHT2, SIGN_FLAG_SHT2, OP_FLAG_SHT2,
ZERO_FLAG_SHT2, SIGN_FLAG_SHT1SHT2, ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM,
ZERO_FLAG_NRM, SIGN_FLAG_SFG, OP_FLAG_SFG, ZERO_FLAG_SFG,
inst_FSM_INPUT_ENABLE_state_next_1_, n541, n542, n543, n544, n545,
n546, n547, n548, n550, n551, n552, n553, n555, n557, n558, n559,
n560, n562, n565, n589, n590, n591, n593, n594, n595, n596, n597,
n598, n599, n600, n601, n602, n603, n604, n605, n606, n607, n608,
n609, n610, n611, n612, n613, n614, n615, n616, n617, n618, n619,
n620, n622, n623, n624, n625, n626, n627, n628, n629, n630, n631,
n632, n633, n634, n635, n636, n637, n638, n639, n645, n647, n649,
n651, n653, n655, n657, n659, n661, n663, n665, n667, n669, n671,
n673, n675, n677, n679, n681, n683, n685, n687, n689, n691, n692,
n693, n694, n695, n696, n697, n698, n699, n700, n701, n702, n703,
n704, n705, n706, n707, n708, n709, n710, n711, n712, n713, n714,
n715, n716, n717, n718, n719, n720, n721, n722, n723, n724, n725,
n726, n727, n728, n729, n730, n731, n732, n733, n734, n735, n736,
n737, n738, n739, n740, n741, n742, n743, n744, n745, n746, n747,
n748, n749, n750, n751, n752, n753, n754, n755, n756, n757, n758,
n759, n760, n761, n762, n763, n765, n766, n767, n768, n769, n770,
n771, n772, n773, n774, n775, n776, n777, n778, n779, n780, n781,
n783, n784, n785, n786, n787, n788, n789, n790, n791, n792, n793,
n794, n795, n796, n798, n799, n801, n802, n835, n836, n837, n838,
n839, n840, n841, n842, n843, n844, n845, n846, n847, n849, n850,
n870, n876, n877, n878, n879, n880, n881, n882, n883, n884, n885,
n886, n887, n888, n889, n890, n891, n892, n893, n894, n895, n896,
n897, n898, n899, n900, n901, n902, n903, n904, n905, n906, n907,
n908, n909, n910, n911, n912, n913, n914, n915, n916, n917, n918,
n919, n920, n921, n922, n923, n924, n925, n926, n927, n928, n929,
n930, n931, n932, n933, n934, n935, n936, n937, n938, n939, n940,
n941, n942, n943, n944, n945, n946, n947, n948, n949, n950, n951,
n952, n592, sub_x_5_A_13_, sub_x_5_A_11_, sub_x_5_A_10_, sub_x_5_A_7_,
sub_x_5_A_5_, sub_x_5_A_3_, sub_x_5_B_17_, sub_x_5_B_11_,
sub_x_5_B_10_, sub_x_5_B_5_, sub_x_5_B_3_, sub_x_5_B_2_, sub_x_5_B_1_,
sub_x_5_B_0_, sub_x_5_n251, sub_x_5_n249, sub_x_5_n245, sub_x_5_n244,
sub_x_5_n237, sub_x_5_n206, sub_x_5_n204, sub_x_5_n203, sub_x_5_n201,
sub_x_5_n198, sub_x_5_n190, add_x_6_A_21_, add_x_6_A_20_,
add_x_6_A_18_, add_x_6_A_14_, add_x_6_A_13_, add_x_6_A_12_,
add_x_6_A_11_, add_x_6_A_10_, add_x_6_A_9_, add_x_6_A_8_,
add_x_6_A_7_, add_x_6_A_6_, add_x_6_A_5_, add_x_6_A_4_, add_x_6_A_2_,
add_x_6_B_21_, add_x_6_B_20_, add_x_6_B_18_, add_x_6_B_14_,
add_x_6_B_13_, add_x_6_B_12_, add_x_6_B_11_, add_x_6_B_10_,
add_x_6_B_9_, add_x_6_B_8_, add_x_6_B_7_, add_x_6_B_6_, add_x_6_B_5_,
add_x_6_B_4_, add_x_6_n197, add_x_6_n194, add_x_6_n189, add_x_6_n183,
add_x_6_n172, add_x_6_n167, add_x_6_n160, add_x_6_n145, add_x_6_n138,
add_x_6_n128, add_x_6_n121, add_x_6_n120, add_x_6_n115, add_x_6_n92,
add_x_6_n89, add_x_6_n88, add_x_6_n77, add_x_6_n70, n955, n958, n959,
n960, n961, n962, n963, n965, n966, n967, n968, n969, n970, n971,
n972, n973, n974, n975, n976, n977, n978, n979, n980, n981, n982,
n983, n984, n985, n986, n987, n988, n989, n990, n991, n992, n994,
n995, n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004,
n1005, n1006, n1007, n1008, n1010, n1011, n1012, n1013, n1014, n1015,
n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025,
n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035,
n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045,
n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055,
n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065,
n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075,
n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085,
n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095,
n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105,
n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115,
n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125,
n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135,
n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145,
n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155,
n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165,
n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175,
n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185,
n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195,
n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205,
n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215,
n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225,
n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235,
n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245,
n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255,
n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265,
n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275,
n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285,
n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295,
n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305,
n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315,
n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325,
n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335,
n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345,
n1346, n1347, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356,
n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366,
n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376,
n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386,
n1387, n1388, n1389, n1391, n1392, n1393, n1394, n1395, n1396, n1397,
n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407,
n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417,
n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426, n1427,
n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1437,
n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447,
n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456, n1457,
n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466, n1467,
n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477,
n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487,
n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497,
n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507,
n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517,
n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527,
n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537,
n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547,
n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557,
n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567,
n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577,
n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587,
n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597,
n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607,
n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617,
n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627,
n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636, n1637,
n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646, n1647,
n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656, n1657,
n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666, n1667,
n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676, n1677,
n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686, n1687,
n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696, n1697,
n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706, n1707,
n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716, n1717,
n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726, n1727,
n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737,
n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747,
n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755, n1756, n1757,
n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766, n1767,
n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776, n1777,
n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1786, n1787,
n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795, n1796, n1797,
n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805, n1806, n1807,
n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815, n1816, n1817,
n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825, n1826, n1827,
n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835, n1836, n1837,
n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845, n1846, n1847,
n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855, n1856, n1857,
n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865, n1866, n1867,
n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875, n1876, n1877,
n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885, n1886, n1887,
n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895, n1896, n1897,
n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905, n1906, n1907,
n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915, n1916, n1917,
n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925, n1926, n1927,
n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935, n1936, n1937,
n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945, n1946, n1947,
n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955, n1956, n1957,
n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965, n1966, n1967,
n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975, n1976, n1977,
n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985, n1986, n1987,
n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995, n1996, n1997,
n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005, n2006, n2007,
n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015, n2016, n2017,
n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025, n2026, n2027,
n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035, n2036, n2037,
n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045, n2046, n2047,
n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055, n2056, n2057,
n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065, n2066, n2067,
n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075, n2076, n2077,
n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085, n2086, n2087,
n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095, n2096, n2097,
n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105, n2106, n2107,
n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115, n2116, n2117,
n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125, n2126, n2127,
n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135, n2136, n2137,
n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145, n2146, n2147,
n2148, n2149, n2150, n2151, n2152, n2153, n2154, n2155, n2156, n2157,
n2158, n2159, n2160, n2161, n2162, n2163, n2164, n2165, n2166, n2167,
n2168, n2169, n2170, n2171, n2172, n2173, n2174, n2175, n2176, n2177,
n2178, n2179, n2180, n2181, n2182, n2183, n2184, n2185, n2186, n2187,
n2188, n2189, n2190, n2191, n2192, n2193, n2194, n2195, n2196, n2197,
n2198, n2199, n2200, n2201, n2202, n2203, n2204, n2205, n2206, n2207,
n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215, n2216, n2217,
n2218, n2219, n2220, n2221, n2222, n2223, n2224, n2225, n2226, n2227,
n2228, n2229, n2230, n2231, n2232, n2233, n2234, n2235, n2236, n2237,
n2238, n2239, n2240, n2241, n2242, n2243, n2244, n2245, n2246, n2247,
n2248, n2249, n2250, n2251, n2252, n2253, n2254, n2255, n2256, n2257,
n2258, n2259, n2260, n2261, n2262, n2263, n2264, n2265, n2266, n2267,
n2268, n2269, n2270, n2271, n2272, n2273, n2274, n2275, n2276, n2277,
n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285, n2286, n2287,
n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295, n2296, n2297,
n2298, n2299, n2300, n2301, n2302, n2303, n2304, n2305, n2306, n2307,
n2308, n2309, n2310, n2311, n2312, n2313, n2314, n2315, n2316, n2317,
n2318, n2319, n2320, n2321, n2322, n2323, n2324, n2325, n2326, n2327,
n2328, n2329, n2330, n2331, n2332, n2333, n2334, n2335, n2336, n2337,
n2338, n2339, n2340, n2341, n2342, n2343, n2344, n2345, n2346, n2347,
n2348, n2349, n2350, n2351, n2352, n2353, n2354, n2355, n2356, n2357,
n2358, n2359, n2360, n2361, n2362, n2363, n2364, n2365, n2366, n2367,
n2368, n2369, n2370, n2371, n2372, n2373, n2374, n2375, n2376, n2377,
n2378, n2379, n2380, n2381, n2382, n2383, n2384, n2385, n2386, n2387,
n2388, n2389, n2390, n2391, n2392, n2393, n2394, n2395, n2396, n2397,
n2398, n2399, n2400, n2401, n2402, n2403, n2404, n2405, n2406, n2407,
n2408, n2409, n2410, n2411, n2412, n2413, n2414, n2415, n2416, n2417,
n2418, n2419, n2420, n2421, n2422, n2423, n2424, n2425, n2426, n2427,
n2428, n2429, n2430, n2431, n2432, n2433, n2434, n2435, n2436, n2437,
n2438, n2439, n2440, n2441, n2442, n2443, n2444, n2445, n2446, n2447,
n2448, n2449, n2450, n2451, n2452, n2453, n2454, n2455, n2456, n2457,
n2458, n2459, n2460, n2461, n2462, n2463, n2464, n2465, n2466, n2467,
n2468, n2469, n2470, n2471, n2472, n2473, n2474, n2475, n2476, n2477,
n2478, n2479, n2480, n2481, n2482, n2483, n2484, n2485, n2486, n2487,
n2488, n2489, n2490, n2491, n2492, n2493, n2494, n2495, n2496, n2497,
n2498, n2499, n2500, n2501, n2502, n2503, n2504, n2505, n2506, n2507,
n2508, n2509, n2510, n2511, n2512, n2513, n2514, n2515, n2516, n2517,
n2518, n2519, n2520, n2521, n2522, n2523, n2524, n2525, n2526, n2527,
n2528, n2529, n2530, n2531, n2532, n2533, n2534, n2535, n2536, n2537,
n2538, n2539, n2540, n2541, n2542, n2543, n2544, n2545, n2546, n2547,
n2548, n2549, n2550, n2551, n2552, n2553, n2554, n2555, n2556, n2557,
n2558, n2559, n2560, n2561, n2562, n2563, n2564, n2565, n2566, n2567,
n2568, n2569, n2570, n2571, n2572, n2573, n2574, n2575, n2576, n2577,
n2578, n2579, n2580, n2581, n2582, n2583, n2584, n2585, n2586, n2587,
n2588, n2589, n2590, n2591, n2592, n2593, n2594, n2595, n2596, n2597,
n2598, n2599, n2600, n2601, n2602, n2603, n2604, n2605, n2606, n2607,
n2608, n2609, n2610, n2611, n2612, n2613, n2614, n2615, n2616, n2617,
n2618, n2619, n2620, n2621, n2622, n2623, n2624, n2625, n2626, n2627,
n2628, n2629, n2630, n2631, n2632, n2633, n2634, n2635, n2636, n2637,
n2638, n2639, n2640, n2641, n2642, n2643, n2644, n2645, n2646, n2647,
n2648, n2649, n2650, n2651, n2652, n2653, n2654, n2655, n2656, n2657,
n2658, n2659, n2660, n2661, n2662, n2663, n2664, n2665, n2666, n2667,
n2668, n2669, n2670, n2671, n2672, n2673, n2674, n2675, n2676, n2677,
n2678, n2679, n2680, n2681, n2682, n2683, n2684, n2685, n2686, n2687,
n2688, n2689, n2690, n2691, n2692, n2693, n2694, n2695, n2696, n2697,
n2698, n2699, n2700, n2701, n2702, n2703, n2704, n2705, n2706, n2707,
n2708, n2709, n2710, n2711, n2712, n2713, n2714, n2715, n2716, n2717,
n2718, n2719, n2720, n2721, n2722, n2723, n2724, n2725, n2726, n2727,
n2728, n2729, n2730, n2731, n2732, n2733, n2734, n2735, n2736, n2737,
n2738, n2739, n2740, n2744, n2745, n2746, n2747, n2748, n2749, n2750,
n2751, n2752, n2753, n2754, n2755, n2756, n2757, n2758, n2759, n2760,
n2761, n2762, n2763, n2764, n2765, n2766, n2767, n2768, n2769, n2770,
n2771, n2772, n2773, n2774, n2775, n2776, n2777, n2778, n2779, n2780,
n2781, n2782, n2783, n2784, n2785, n2786, n2787, n2788, n2789, n2790,
n2791, n2792, n2793, n2794, n2795, n2796, n2797, n2798, n2799, n2800,
n2801, n2802, n2803, n2804, n2805, n2806, n2807, n2808, n2809, n2810,
n2811, n2812, n2813, n2814, n2815, n2816, n2817, n2818, n2819, n2820,
n2821, n2822, n2823, n2824, n2825, n2826, n2827, n2828, n2829, n2830,
n2831, n2832, n2833, n2834, n2835, n2836, n2837, n2838, n2839, n2840,
n2841, n2842, n2843, n2844, n2845, n2846, n2847, n2848, n2849, n2850,
n2851, n2852, n2853, n2854, n2855, n2856, n2857, n2858, n2859, n2860,
n2861, n2862, n2863, n2864, n2865, n2866, n2867, n2868, n2869, n2870,
n2871, n2872, n2873, n2874, n2875, n2876, n2877, n2878, n2879, n2880,
n2881, n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889, n2890,
n2891, n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900,
n2901, n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910,
n2911, n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2920,
n2921, n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930,
n2931, n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940,
n2941, n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949, n2950,
n2951, n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959, n2960,
n2961, n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969, n2970,
n2971, n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980,
n2981, n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989, n2990,
n2991, n2992, n2993, n2994, n2995, n2996, n2997, n2998, n2999, n3000,
n3001, n3002, n3003, n3004, n3005, n3006, n3007, n3008, n3009, n3010,
n3011, n3012, n3013, n3014, n3015, n3016, n3017, n3018, n3019, n3020,
n3021, n3022, n3023, n3024, n3025, n3026, n3027, n3028, n3029, n3030,
n3031, n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040,
n3041, n3042, n3043, n3044, n3045, n3046, n3047, n3048, n3049, n3050,
n3051, n3052, n3053, n3054, n3055, n3056, n3057, n3058, n3059, n3060,
n3061, n3062, n3063, n3064, n3065, n3066, n3067, n3068, n3069, n3070,
n3071, n3072, n3073, n3074, n3075, n3076, n3077, n3078, n3079, n3080,
n3081, n3082, n3083, n3084, n3085, n3086, n3087, n3088, n3089, n3090,
n3091, n3092, n3093, n3094, n3095, n3096, n3097, n3098, n3099, n3100,
n3101, n3102, n3103, n3104, n3105, n3106, n3107, n3108, n3109, n3110,
n3111, n3112, n3113, n3114, n3115, n3116, n3117, n3118, n3119, n3120,
n3121, n3122, n3123, n3124, n3125, n3126, n3127, n3128, n3129, n3130,
n3131, n3132, n3133, n3134, n3135, n3136, n3137, n3138, n3139, n3140,
n3141, n3142, n3143, n3144, n3145, n3146, n3147, n3148, n3149, n3150,
n3151, n3152, n3153, n3154, n3155, n3156, n3157, n3158, n3159, n3160,
n3161, n3162, n3163, n3164, n3165, n3166, n3167, n3168, n3169, n3170,
n3171, n3172, n3173, n3174, n3175, n3176, n3177, n3178, n3179, n3180,
n3181, n3182, n3183, n3184, n3185, n3186, n3187, n3188, n3189, n3190,
n3191, n3192, n3193, n3194, n3195, n3196, n3197, n3198, n3199, n3200,
n3201, n3202, n3203, n3204, n3205, n3206, n3207, n3208, n3209, n3210,
n3211, n3212, n3213, n3214, n3215, n3216, n3217, n3218, n3219, n3220,
n3221, n3222, n3223, n3224, n3225, n3226, n3227, n3228, n3229, n3230,
n3231, n3232, n3233, n3234, n3235, n3236, n3237, n3238, n3239, n3240,
n3241, n3242, n3243, n3244, n3245, n3246, n3247, n3248, n3249, n3250,
n3251, n3252, n3253, n3254, n3255, n3256, n3257, n3258, n3259, n3260,
n3261, n3262, n3263, n3264, n3265, n3266, n3267, n3268, n3269, n3270,
n3271, n3272, n3273, n3274, n3275, n3276, n3277, n3278, n3279, n3280,
n3281, n3282, n3283, n3284, n3285, n3286, n3287, n3288, n3289, n3290,
n3291, n3292, n3293, n3294, n3295, n3296, n3297, n3298, n3299, n3300,
n3301, n3302, n3303, n3304, n3305, n3306, n3307, n3308, n3309, n3310,
n3311, n3312, n3313, n3314, n3315, n3316, n3317, n3318, n3319, n3320,
n3321, n3322, n3323, n3324, n3325, n3326, n3327, n3328, n3329, n3330,
n3331, n3332, n3333, n3334, n3335, n3336, n3337, n3338, n3339, n3340,
n3341, n3342, n3343, n3344, n3346, n3347, n3348, n3349, n3350, n3351,
n3352, n3353, n3354, n3355, n3356, n3357, n3358, n3359, n3360, n3361,
n3362, n3363, n3364, n3365, n3366, n3367, n3368, n3369, n3370, n3371,
n3372, n3373, n3374, n3375, n3376, n3377, n3378, n3379, n3380, n3381,
n3382, n3383, n3384, n3385, n3386, n3387, n3388, n3389, n3390, n3391,
n3392, n3393, n3394, n3395, n3396, n3397, n3398, n3399, n3400, n3401,
n3402, n3403, n3404, n3405, n3406, n3407, n3408, n3409, n3410, n3411,
n3412, n3413, n3414, n3415, n3416, n3417, n3418, n3419, n3420, n3421,
n3422, n3423, n3424, n3425, n3426, n3427, n3428, n3429, n3430, n3431,
n3432, n3433, n3434, n3435, n3436, n3437, n3438, n3439, n3440, n3441,
n3442, n3443, n3444, n3445, n3446, n3447, n3448, n3449, n3450, n3451,
n3452, n3453, n3454, n3455, n3456, n3457, n3458, n3459, n3460, n3461,
n3462, n3463, n3464, n3465, n3466, n3467, n3468, n3469, n3470, n3471,
n3472, n3473, n3474, n3475, n3476, n3477, n3478, n3479, n3480, n3481,
n3482, n3483, n3484, n3485, n3486, n3487, n3488, n3489, n3490, n3491,
n3492, n3493, n3494, n3495, n3496, n3497, n3498, n3499, n3500, n3501,
n3502, n3503, n3504, n3505, n3506, n3507, n3508, n3509, n3510, n3511,
n3512, n3513, n3514, n3515, n3516, n3517, n3518, n3519, n3520, n3521,
n3522, n3523, n3524, n3525, n3526, n3527, n3528, n3529, n3530, n3531,
n3532, n3533, n3534, n3535, n3536, n3537, n3538, n3539, n3540, n3541,
n3542, n3543, n3544, n3545, n3546, n3547, n3548, n3549, n3550, n3551,
n3552, n3553, n3554, n3555, n3556, n3557, n3558, n3559, n3560, n3561,
n3562, n3563, n3564, n3565, n3566, n3567, n3568, n3569, n3570, n3571,
n3572, n3573, n3574, n3575, n3576, n3577, n3578, n3579, n3580, n3581,
n3582, n3583, n3584, n3585, n3586, n3587, n3588, n3589, n3590, n3591,
n3592, n3593, n3594, n3595, n3596, n3597, n3598, n3599, n3600, n3601,
n3602, n3603, n3604, n3605, n3606, n3607, n3608, n3609, n3610, n3611,
n3612, n3613, n3614, n3615, n3616, n3617, n3618, n3619, n3620, n3621,
n3622, n3623, n3624, n3625, n3626, n3627, n3628, n3629, n3630, n3631,
n3632, n3633, n3634, n3635, n3636, n3637, n3638, n3639, n3640, n3641,
n3642, n3643, n3644, n3645, n3646, n3647, n3648, n3649, n3650, n3651,
n3652, n3653, n3654, n3655, n3656, n3657, n3658, n3659, n3660, n3661,
n3662, n3663, n3664, n3665, n3666, n3667, n3668, n3669, n3670, n3671,
n3672, n3673, n3674, n3675, n3676, n3677, n3678, n3679, n3680, n3681;
wire [3:0] Shift_reg_FLAGS_7;
wire [31:0] intDX_EWSW;
wire [31:0] intDY_EWSW;
wire [30:0] DMP_SHT1_EWSW;
wire [22:0] DmP_mant_SHT1_SW;
wire [4:0] Shift_amount_SHT1_EWR;
wire [24:0] Raw_mant_NRM_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [4:2] shift_value_SHT2_EWR;
wire [7:2] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [4:0] LZD_output_NRM2_EW;
wire [30:1] DMP_SFG;
wire [25:0] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRX4TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n951), .CK(clk), .RN(
n3341), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n2898) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n941), .CK(clk), .RN(n3337), .Q(
intDX_EWSW[2]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n939), .CK(clk), .RN(n3337), .Q(
intDX_EWSW[4]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n935), .CK(clk), .RN(n3337), .Q(
intDX_EWSW[8]), .QN(n1120) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n934), .CK(clk), .RN(n3338), .Q(
intDX_EWSW[9]), .QN(n1161) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n933), .CK(clk), .RN(n3338),
.Q(intDX_EWSW[10]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n930), .CK(clk), .RN(n3338),
.Q(intDX_EWSW[13]), .QN(n1168) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n924), .CK(clk), .RN(n3339),
.Q(intDX_EWSW[19]), .QN(n1159) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n919), .CK(clk), .RN(n3339),
.Q(intDX_EWSW[24]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n918), .CK(clk), .RN(n3339),
.Q(intDX_EWSW[25]) );
DFFRX4TS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n877), .CK(clk), .RN(n3323), .Q(
left_right_SHT2), .QN(n2832) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n844), .CK(clk), .RN(n2590),
.Q(Shift_amount_SHT1_EWR[2]), .QN(n2823) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n842), .CK(clk), .RN(n3328),
.Q(Shift_amount_SHT1_EWR[4]), .QN(n2882) );
DFFRX1TS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n802), .CK(clk), .RN(n3328), .Q(
OP_FLAG_EXP) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n799), .CK(clk), .RN(n3329), .Q(
DMP_SHT1_EWSW[0]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n798), .CK(clk), .RN(n3342), .Q(
DMP_SHT2_EWSW[0]), .QN(n2820) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n796), .CK(clk), .RN(n3342), .Q(
DMP_SHT1_EWSW[1]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n795), .CK(clk), .RN(n2953), .Q(
DMP_SHT2_EWSW[1]), .QN(n2819) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n793), .CK(clk), .RN(n3342), .Q(
DMP_SHT1_EWSW[2]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n792), .CK(clk), .RN(n3329), .Q(
DMP_SHT2_EWSW[2]), .QN(n2818) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n790), .CK(clk), .RN(n2954), .Q(
DMP_SHT1_EWSW[3]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n789), .CK(clk), .RN(n2954), .Q(
DMP_SHT2_EWSW[3]), .QN(n2817) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n787), .CK(clk), .RN(n2954), .Q(
DMP_SHT1_EWSW[4]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n786), .CK(clk), .RN(n2954), .Q(
DMP_SHT2_EWSW[4]), .QN(n2816) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n784), .CK(clk), .RN(n1245), .Q(
DMP_SHT1_EWSW[5]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n783), .CK(clk), .RN(n1245), .Q(
DMP_SHT2_EWSW[5]), .QN(n2880) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n781), .CK(clk), .RN(n3323), .Q(
DMP_SHT1_EWSW[6]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n780), .CK(clk), .RN(n1245), .Q(
DMP_SHT2_EWSW[6]), .QN(n2815) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n778), .CK(clk), .RN(n1245), .Q(
DMP_SHT1_EWSW[7]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n777), .CK(clk), .RN(n1245), .Q(
DMP_SHT2_EWSW[7]), .QN(n2814) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n775), .CK(clk), .RN(n2955), .Q(
DMP_SHT1_EWSW[8]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n774), .CK(clk), .RN(n2955), .Q(
DMP_SHT2_EWSW[8]), .QN(n2895) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n772), .CK(clk), .RN(n2955), .Q(
DMP_SHT1_EWSW[9]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n771), .CK(clk), .RN(n2955), .Q(
DMP_SHT2_EWSW[9]), .QN(n2802) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n769), .CK(clk), .RN(n1245), .Q(
DMP_SHT1_EWSW[10]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n768), .CK(clk), .RN(n3343), .Q(
DMP_SHT2_EWSW[10]), .QN(n2813) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n766), .CK(clk), .RN(n2338), .Q(
DMP_SHT1_EWSW[11]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n763), .CK(clk), .RN(n2337), .Q(
DMP_SHT1_EWSW[12]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n762), .CK(clk), .RN(n1245), .Q(
DMP_SHT2_EWSW[12]), .QN(n2812) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n760), .CK(clk), .RN(n3334), .Q(
DMP_SHT1_EWSW[13]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n759), .CK(clk), .RN(n3330), .Q(
DMP_SHT2_EWSW[13]), .QN(n2811) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n757), .CK(clk), .RN(n3333), .Q(
DMP_SHT1_EWSW[14]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n756), .CK(clk), .RN(n3332), .Q(
DMP_SHT2_EWSW[14]), .QN(n2810) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n754), .CK(clk), .RN(n1251), .Q(
DMP_SHT1_EWSW[15]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n753), .CK(clk), .RN(n3335), .Q(
DMP_SHT2_EWSW[15]), .QN(n2809) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n751), .CK(clk), .RN(n3331), .Q(
DMP_SHT1_EWSW[16]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n750), .CK(clk), .RN(n1250), .Q(
DMP_SHT2_EWSW[16]), .QN(n2808) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n748), .CK(clk), .RN(n3333), .Q(
DMP_SHT1_EWSW[17]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n747), .CK(clk), .RN(n1250), .Q(
DMP_SHT2_EWSW[17]), .QN(n2807) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n745), .CK(clk), .RN(n3316), .Q(
DMP_SHT1_EWSW[18]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n744), .CK(clk), .RN(n3326), .Q(
DMP_SHT2_EWSW[18]), .QN(n2806) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n742), .CK(clk), .RN(n1231), .Q(
DMP_SHT1_EWSW[19]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n741), .CK(clk), .RN(n1245), .Q(
DMP_SHT2_EWSW[19]), .QN(n2805) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n739), .CK(clk), .RN(n3330), .Q(
DMP_SHT1_EWSW[20]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n738), .CK(clk), .RN(n3332), .Q(
DMP_SHT2_EWSW[20]), .QN(n2804) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n736), .CK(clk), .RN(n1251), .Q(
DMP_SHT1_EWSW[21]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n735), .CK(clk), .RN(n3335), .Q(
DMP_SHT2_EWSW[21]), .QN(n2803) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n733), .CK(clk), .RN(n1250), .Q(
DMP_SHT1_EWSW[22]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n730), .CK(clk), .RN(n3318), .Q(
DMP_SHT1_EWSW[23]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n729), .CK(clk), .RN(n3319), .Q(
DMP_SHT2_EWSW[23]), .QN(n2821) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n727), .CK(clk), .RN(n3322), .Q(
DMP_exp_NRM_EW[0]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n725), .CK(clk), .RN(n3323), .Q(
DMP_SHT1_EWSW[24]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n724), .CK(clk), .RN(n3320), .Q(
DMP_SHT2_EWSW[24]), .QN(n2794) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n722), .CK(clk), .RN(n3321), .Q(
DMP_exp_NRM_EW[1]) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n716), .CK(clk), .RN(n3319), .Q(
DMP_exp_NRM2_EW[2]), .QN(n3307) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n715), .CK(clk), .RN(n3320), .Q(
DMP_SHT1_EWSW[26]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n714), .CK(clk), .RN(n3318), .Q(
DMP_SHT2_EWSW[26]), .QN(n2825) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n712), .CK(clk), .RN(n3319), .Q(
DMP_exp_NRM_EW[3]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n710), .CK(clk), .RN(n3317), .Q(
DMP_SHT1_EWSW[27]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n709), .CK(clk), .RN(n3317), .Q(
DMP_SHT2_EWSW[27]), .QN(n2827) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n707), .CK(clk), .RN(n3317), .Q(
DMP_exp_NRM_EW[4]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n705), .CK(clk), .RN(n3317), .Q(
DMP_SHT1_EWSW[28]) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n702), .CK(clk), .RN(n2934), .Q(
DMP_exp_NRM_EW[5]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n700), .CK(clk), .RN(n3320), .Q(
DMP_SHT1_EWSW[29]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n699), .CK(clk), .RN(n3318), .Q(
DMP_SHT2_EWSW[29]), .QN(n2795) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n697), .CK(clk), .RN(n3320), .Q(
DMP_exp_NRM_EW[6]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n695), .CK(clk), .RN(n3321), .Q(
DMP_SHT1_EWSW[30]) );
DFFRX2TS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n692), .CK(clk), .RN(n3318), .Q(
DMP_exp_NRM_EW[7]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n689), .CK(clk), .RN(n1248), .Q(
DmP_mant_SHT1_SW[0]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n687), .CK(clk), .RN(n1248), .Q(
DmP_mant_SHT1_SW[1]), .QN(n2892) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n685), .CK(clk), .RN(n2948), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n683), .CK(clk), .RN(n2948), .Q(
DmP_mant_SHT1_SW[3]), .QN(n2877) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n681), .CK(clk), .RN(n3318), .Q(
DmP_mant_SHT1_SW[4]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n677), .CK(clk), .RN(n1252), .Q(
DmP_mant_SHT1_SW[6]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n675), .CK(clk), .RN(n1252), .Q(
DmP_mant_SHT1_SW[7]), .QN(n2876) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n673), .CK(clk), .RN(n1252), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n671), .CK(clk), .RN(n1252), .Q(
DmP_mant_SHT1_SW[9]), .QN(n2891) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n669), .CK(clk), .RN(n1248), .Q(
DmP_mant_SHT1_SW[10]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n667), .CK(clk), .RN(n1248), .Q(
DmP_mant_SHT1_SW[11]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n665), .CK(clk), .RN(n2948), .Q(
DmP_mant_SHT1_SW[12]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n661), .CK(clk), .RN(n2946), .Q(
DmP_mant_SHT1_SW[14]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n659), .CK(clk), .RN(n2946), .Q(
DmP_mant_SHT1_SW[15]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n657), .CK(clk), .RN(n2946), .Q(
DmP_mant_SHT1_SW[16]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n655), .CK(clk), .RN(n2946), .Q(
DmP_mant_SHT1_SW[17]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n653), .CK(clk), .RN(n2941), .Q(
DmP_mant_SHT1_SW[18]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n651), .CK(clk), .RN(n1231), .Q(
DmP_mant_SHT1_SW[19]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n649), .CK(clk), .RN(n2939), .Q(
DmP_mant_SHT1_SW[20]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n647), .CK(clk), .RN(n1231), .Q(
DmP_mant_SHT1_SW[21]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n645), .CK(clk), .RN(n2938), .Q(
DmP_mant_SHT1_SW[22]) );
DFFRX1TS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n637), .CK(clk), .RN(n3314), .Q(
ZERO_FLAG_SHT1) );
DFFRX1TS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n636), .CK(clk), .RN(n3314), .Q(
ZERO_FLAG_SHT2), .QN(n2798) );
DFFRX2TS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n634), .CK(clk), .RN(n3314), .Q(
ZERO_FLAG_NRM) );
DFFRX2TS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n633), .CK(clk), .RN(n3314), .Q(
ZERO_FLAG_SHT1SHT2) );
DFFRX1TS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n631), .CK(clk), .RN(n3328), .Q(
OP_FLAG_SHT1) );
DFFRX1TS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n630), .CK(clk), .RN(n3328), .Q(
OP_FLAG_SHT2), .QN(n2881) );
DFFRX1TS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n626), .CK(clk), .RN(n2933), .Q(
SIGN_FLAG_SHT1) );
DFFRX1TS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n625), .CK(clk), .RN(n1245), .Q(
SIGN_FLAG_SHT2), .QN(n2797) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n620), .CK(clk), .RN(n3344), .Q(
Raw_mant_NRM_SWR[0]), .QN(n2799) );
DFFRXLTS R_208 ( .D(sub_x_5_B_5_), .CK(clk), .RN(n1253), .Q(
DmP_mant_SFG_SWR[5]) );
DFFRXLTS R_479 ( .D(sub_x_5_B_10_), .CK(clk), .RN(n3320), .Q(
DmP_mant_SFG_SWR[10]) );
DFFRX4TS R_51 ( .D(n3557), .CK(clk), .RN(n2939), .Q(n3272) );
DFFSX2TS R_65 ( .D(n3472), .CK(clk), .SN(n1249), .Q(n3262) );
DFFSX2TS R_66 ( .D(n3471), .CK(clk), .SN(n1249), .Q(n3261) );
DFFSX2TS R_64 ( .D(n3473), .CK(clk), .SN(n1249), .Q(n3263) );
DFFSX2TS R_68 ( .D(n3575), .CK(clk), .SN(n1234), .Q(n3259) );
DFFSX2TS R_69 ( .D(n3574), .CK(clk), .SN(n1252), .Q(n3258) );
DFFSX2TS R_67 ( .D(n3576), .CK(clk), .SN(n1234), .Q(n3260) );
DFFSX1TS R_75 ( .D(n3578), .CK(clk), .SN(n2943), .Q(n3254) );
DFFSX1TS R_76 ( .D(n3579), .CK(clk), .SN(n2943), .Q(n3253) );
DFFSX1TS R_77 ( .D(n3577), .CK(clk), .SN(n2943), .Q(n3252) );
DFFSX1TS R_79 ( .D(n3588), .CK(clk), .SN(n2940), .Q(n3250) );
DFFSX1TS R_78 ( .D(n3587), .CK(clk), .SN(n2940), .Q(n3251) );
DFFSX1TS R_80 ( .D(n3586), .CK(clk), .SN(n2940), .Q(n3249) );
DFFSX1TS R_82 ( .D(n3599), .CK(clk), .SN(n2940), .Q(n3247) );
DFFSX1TS R_81 ( .D(n3598), .CK(clk), .SN(n2940), .Q(n3248) );
DFFSX1TS R_83 ( .D(n3597), .CK(clk), .SN(n2940), .Q(n3246) );
DFFSX1TS R_84 ( .D(n3539), .CK(clk), .SN(n3344), .Q(n3245) );
DFFSX2TS R_88 ( .D(n3548), .CK(clk), .SN(n3317), .Q(n3241) );
DFFSX2TS R_87 ( .D(n3547), .CK(clk), .SN(n2336), .Q(n3242) );
DFFSX2TS R_89 ( .D(n3546), .CK(clk), .SN(n3344), .Q(n3240) );
DFFSX1TS R_121 ( .D(n3482), .CK(clk), .SN(n1253), .Q(n3223) );
DFFSX2TS R_122 ( .D(n3541), .CK(clk), .SN(n1254), .Q(n3222) );
DFFSX1TS R_124 ( .D(n3480), .CK(clk), .SN(n1254), .Q(n3220) );
DFFSX1TS R_126 ( .D(n3537), .CK(clk), .SN(n3326), .Q(n3218) );
DFFSX1TS R_125 ( .D(n3536), .CK(clk), .SN(n1252), .Q(n3219) );
DFFSX1TS R_129 ( .D(n3582), .CK(clk), .SN(n2940), .Q(n3215) );
DFFSX1TS R_128 ( .D(n3581), .CK(clk), .SN(n1236), .Q(n3216) );
DFFSX2TS R_132 ( .D(n3511), .CK(clk), .SN(n2946), .Q(n3214) );
DFFSX2TS R_133 ( .D(n3510), .CK(clk), .SN(n2946), .Q(n3213) );
DFFSX2TS R_135 ( .D(n3532), .CK(clk), .SN(n3316), .Q(n3212) );
DFFSX2TS R_136 ( .D(n3531), .CK(clk), .SN(n2933), .Q(n3211) );
DFFSX2TS R_138 ( .D(n3525), .CK(clk), .SN(n2933), .Q(n3210) );
DFFSX1TS R_145 ( .D(n3545), .CK(clk), .SN(n2944), .Q(n3208) );
DFFSX1TS R_148 ( .D(n3542), .CK(clk), .SN(n2944), .Q(n3205) );
DFFSX1TS R_146 ( .D(n3544), .CK(clk), .SN(n2944), .Q(n3207) );
DFFSX1TS R_147 ( .D(n3543), .CK(clk), .SN(n1233), .Q(n3206) );
DFFSX1TS R_151 ( .D(n3572), .CK(clk), .SN(n2943), .Q(n3203) );
DFFSX1TS R_149 ( .D(n3573), .CK(clk), .SN(n1233), .Q(n3204) );
DFFSX2TS R_152 ( .D(n3592), .CK(clk), .SN(n1237), .Q(n3202) );
DFFSX2TS R_154 ( .D(n3591), .CK(clk), .SN(n1237), .Q(n3201) );
DFFSX2TS R_157 ( .D(n3533), .CK(clk), .SN(n3316), .QN(n1043) );
DFFSX1TS R_182 ( .D(n3458), .CK(clk), .SN(n2948), .Q(n3181) );
DFFSX1TS R_184 ( .D(n3457), .CK(clk), .SN(n2948), .Q(n3180) );
DFFSX1TS R_186 ( .D(n3596), .CK(clk), .SN(n1236), .Q(n3179) );
DFFSX1TS R_187 ( .D(n3595), .CK(clk), .SN(n1236), .Q(n3178) );
DFFSX2TS R_199 ( .D(n3567), .CK(clk), .SN(n1234), .Q(n3177) );
DFFSX2TS R_201 ( .D(n3566), .CK(clk), .SN(n1233), .Q(n3176) );
DFFSX2TS R_220 ( .D(n3679), .CK(clk), .SN(n1232), .Q(n3175) );
DFFSX2TS R_359 ( .D(n3417), .CK(clk), .SN(n2952), .Q(n3079) );
DFFSX2TS R_360 ( .D(n3416), .CK(clk), .SN(n2952), .Q(n3078) );
DFFSX2TS R_361 ( .D(n3415), .CK(clk), .SN(n2952), .Q(n3077) );
DFFSX1TS R_493 ( .D(n3593), .CK(clk), .SN(n1237), .Q(n2983) );
DFFRX1TS R_491 ( .D(n3594), .CK(clk), .RN(n2939), .Q(n2984) );
DFFRX2TS R_495 ( .D(n3568), .CK(clk), .RN(n2948), .Q(n2982) );
DFFRX2TS R_507 ( .D(n3590), .CK(clk), .RN(n2941), .Q(n2970) );
DFFSX4TS R_513 ( .D(n3569), .CK(clk), .SN(n3681), .Q(n2965) );
DFFRX1TS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n635), .CK(clk), .RN(n3314), .Q(
ZERO_FLAG_SFG), .QN(n2925) );
DFFRX1TS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n624), .CK(clk), .RN(n1245), .Q(
SIGN_FLAG_SFG), .QN(n2924) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_28_ ( .D(n703), .CK(clk), .RN(n3317), .Q(
DMP_SFG[28]), .QN(n2923) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_27_ ( .D(n708), .CK(clk), .RN(n3317), .Q(
DMP_SFG[27]), .QN(n2922) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_29_ ( .D(n698), .CK(clk), .RN(n3322), .Q(
DMP_SFG[29]), .QN(n2921) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_30_ ( .D(n693), .CK(clk), .RN(n3319), .Q(
DMP_SFG[30]), .QN(n2920) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_24_ ( .D(n723), .CK(clk), .RN(n3318), .Q(
DMP_SFG[24]), .QN(n2919) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_26_ ( .D(n713), .CK(clk), .RN(n3322), .Q(
DMP_SFG[26]), .QN(n2917) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_23_ ( .D(n728), .CK(clk), .RN(n3322), .Q(
DMP_SFG[23]), .QN(n2907) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n589), .CK(clk), .RN(n1234), .Q(
final_result_ieee[10]), .QN(n2914) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(n3312), .CK(clk), .RN(n3314), .Q(ready) );
DFFRXLTS R_55 ( .D(final_result_ieee[31]), .CK(clk), .RN(n1233), .Q(n3270)
);
DFFSX2TS R_258 ( .D(n3528), .CK(clk), .SN(n2947), .Q(n3169) );
DFFSX2TS R_261 ( .D(n3523), .CK(clk), .SN(n3324), .Q(n3166) );
DFFSX2TS R_264 ( .D(n3514), .CK(clk), .SN(n2945), .Q(n3163) );
DFFSX2TS R_267 ( .D(n3517), .CK(clk), .SN(n2947), .Q(n3160) );
DFFSX2TS R_270 ( .D(n3520), .CK(clk), .SN(n2940), .Q(n3157) );
DFFSX2TS R_273 ( .D(n3509), .CK(clk), .SN(n3326), .Q(n3154) );
DFFSX2TS R_285 ( .D(n3488), .CK(clk), .SN(n1254), .Q(n3151) );
DFFSX2TS R_291 ( .D(n3500), .CK(clk), .SN(n1233), .Q(n3145) );
DFFSX2TS R_297 ( .D(n3506), .CK(clk), .SN(n2947), .Q(n3139) );
DFFSX2TS R_300 ( .D(n3494), .CK(clk), .SN(n1252), .Q(n3136) );
DFFSX2TS R_303 ( .D(n3491), .CK(clk), .SN(n1254), .Q(n3133) );
DFFSX2TS R_306 ( .D(n3479), .CK(clk), .SN(n1248), .Q(n3130) );
DFFSX2TS R_315 ( .D(n3485), .CK(clk), .SN(n2941), .Q(n3121) );
DFFSX2TS R_318 ( .D(n3470), .CK(clk), .SN(n1248), .Q(n3118) );
DFFSX2TS R_321 ( .D(n3461), .CK(clk), .SN(n2949), .Q(n3115) );
DFFSX2TS R_324 ( .D(n3464), .CK(clk), .SN(n2949), .Q(n3112) );
DFFSX2TS R_327 ( .D(n3467), .CK(clk), .SN(n1249), .Q(n3109) );
DFFSX2TS R_330 ( .D(n3456), .CK(clk), .SN(n2949), .Q(n3106) );
DFFSX2TS R_336 ( .D(n3450), .CK(clk), .SN(n2950), .Q(n3100) );
DFFSX2TS R_339 ( .D(n3453), .CK(clk), .SN(n2950), .Q(n3097) );
DFFSX2TS R_350 ( .D(n3414), .CK(clk), .SN(n2953), .Q(n3088) );
DFFSX2TS R_353 ( .D(n3348), .CK(clk), .SN(n3331), .Q(n3085) );
DFFSX2TS R_356 ( .D(n3354), .CK(clk), .SN(n3332), .Q(n3082) );
DFFSX2TS R_362 ( .D(n3387), .CK(clk), .SN(n2339), .Q(n3076) );
DFFSX2TS R_368 ( .D(n3390), .CK(clk), .SN(n2955), .Q(n3070) );
DFFSX2TS R_371 ( .D(n3396), .CK(clk), .SN(n1246), .Q(n3067) );
DFFSX2TS R_374 ( .D(n3399), .CK(clk), .SN(n2931), .Q(n3064) );
DFFSX2TS R_377 ( .D(n3402), .CK(clk), .SN(n3340), .Q(n3061) );
DFFSX2TS R_380 ( .D(n3405), .CK(clk), .SN(n2954), .Q(n3058) );
DFFSX2TS R_383 ( .D(n3408), .CK(clk), .SN(n2954), .Q(n3055) );
DFFSX2TS R_386 ( .D(n3411), .CK(clk), .SN(n2953), .Q(n3052) );
DFFSX2TS R_389 ( .D(n3351), .CK(clk), .SN(n1251), .Q(n3049) );
DFFSX2TS R_392 ( .D(n3357), .CK(clk), .SN(n1246), .Q(n3046) );
DFFSX2TS R_395 ( .D(n3360), .CK(clk), .SN(n1234), .Q(n3043) );
DFFSX2TS R_398 ( .D(n3363), .CK(clk), .SN(n3326), .Q(n3040) );
DFFSX2TS R_401 ( .D(n3366), .CK(clk), .SN(n3334), .Q(n3037) );
DFFSX2TS R_404 ( .D(n3369), .CK(clk), .SN(n3331), .Q(n3034) );
DFFSX2TS R_407 ( .D(n3372), .CK(clk), .SN(n1251), .Q(n3031) );
DFFSX2TS R_410 ( .D(n3375), .CK(clk), .SN(n1250), .Q(n3028) );
DFFSX2TS R_413 ( .D(n3378), .CK(clk), .SN(n3332), .Q(n3025) );
DFFSX2TS R_428 ( .D(n3393), .CK(clk), .SN(n2955), .Q(n3013) );
DFFSX2TS R_442 ( .D(n3602), .CK(clk), .SN(n3320), .Q(n3003) );
DFFSX2TS R_445 ( .D(n3608), .CK(clk), .SN(n3315), .Q(n3000) );
DFFSX2TS R_448 ( .D(n3605), .CK(clk), .SN(n3319), .Q(n2997) );
DFFRXLTS R_235 ( .D(n3676), .CK(clk), .RN(n1254), .Q(n3171) );
DFFSX2TS R_221 ( .D(n3678), .CK(clk), .SN(n1252), .Q(n3174) );
DFFSX2TS R_259 ( .D(n3527), .CK(clk), .SN(n3324), .Q(n3168) );
DFFSX2TS R_262 ( .D(n3522), .CK(clk), .SN(n2947), .Q(n3165) );
DFFSX2TS R_265 ( .D(n3513), .CK(clk), .SN(n2946), .Q(n3162) );
DFFSX2TS R_268 ( .D(n3516), .CK(clk), .SN(n3324), .Q(n3159) );
DFFSX2TS R_271 ( .D(n3519), .CK(clk), .SN(n2336), .Q(n3156) );
DFFSX1TS R_274 ( .D(n3508), .CK(clk), .SN(n1264), .Q(n3153) );
DFFSX2TS R_286 ( .D(n3487), .CK(clk), .SN(n3333), .Q(n3150) );
DFFSX2TS R_292 ( .D(n3499), .CK(clk), .SN(n1234), .Q(n3144) );
DFFSX2TS R_295 ( .D(n3502), .CK(clk), .SN(n2947), .Q(n3141) );
DFFSX2TS R_298 ( .D(n3505), .CK(clk), .SN(n2947), .Q(n3138) );
DFFSX2TS R_301 ( .D(n3493), .CK(clk), .SN(n1253), .Q(n3135) );
DFFSX2TS R_304 ( .D(n3490), .CK(clk), .SN(n1248), .Q(n3132) );
DFFSX2TS R_307 ( .D(n3478), .CK(clk), .SN(n1249), .Q(n3129) );
DFFSX2TS R_316 ( .D(n3484), .CK(clk), .SN(n1253), .Q(n3120) );
DFFSX2TS R_319 ( .D(n3469), .CK(clk), .SN(n1248), .Q(n3117) );
DFFSX2TS R_322 ( .D(n3460), .CK(clk), .SN(n2949), .Q(n3114) );
DFFSX2TS R_325 ( .D(n3463), .CK(clk), .SN(n2949), .Q(n3111) );
DFFSX2TS R_328 ( .D(n3466), .CK(clk), .SN(n1249), .Q(n3108) );
DFFSX2TS R_331 ( .D(n3455), .CK(clk), .SN(n2949), .Q(n3105) );
DFFSX2TS R_334 ( .D(n3446), .CK(clk), .SN(n2590), .Q(n3102) );
DFFSX2TS R_337 ( .D(n3449), .CK(clk), .SN(n2950), .Q(n3099) );
DFFSX2TS R_340 ( .D(n3452), .CK(clk), .SN(n2950), .Q(n3096) );
DFFSX2TS R_351 ( .D(n3413), .CK(clk), .SN(n3329), .Q(n3087) );
DFFSX2TS R_354 ( .D(n3347), .CK(clk), .SN(n3335), .Q(n3084) );
DFFSX2TS R_357 ( .D(n3353), .CK(clk), .SN(n3333), .Q(n3081) );
DFFSX2TS R_363 ( .D(n3386), .CK(clk), .SN(n2338), .Q(n3075) );
DFFSX2TS R_366 ( .D(n3380), .CK(clk), .SN(n1246), .Q(n3072) );
DFFSX2TS R_369 ( .D(n3389), .CK(clk), .SN(n2337), .Q(n3069) );
DFFSX2TS R_372 ( .D(n3395), .CK(clk), .SN(n3329), .Q(n3066) );
DFFSX2TS R_378 ( .D(n3401), .CK(clk), .SN(n2338), .Q(n3060) );
DFFSX2TS R_381 ( .D(n3404), .CK(clk), .SN(n3341), .Q(n3057) );
DFFSX2TS R_384 ( .D(n3407), .CK(clk), .SN(n1239), .Q(n3054) );
DFFSX2TS R_387 ( .D(n3410), .CK(clk), .SN(n3329), .Q(n3051) );
DFFSX2TS R_390 ( .D(n3350), .CK(clk), .SN(n3331), .Q(n3048) );
DFFSX2TS R_393 ( .D(n3356), .CK(clk), .SN(n1235), .Q(n3045) );
DFFSX2TS R_396 ( .D(n3359), .CK(clk), .SN(n2938), .Q(n3042) );
DFFSX2TS R_399 ( .D(n3362), .CK(clk), .SN(n1246), .Q(n3039) );
DFFSX2TS R_402 ( .D(n3365), .CK(clk), .SN(n3335), .Q(n3036) );
DFFSX2TS R_405 ( .D(n3368), .CK(clk), .SN(n1250), .Q(n3033) );
DFFSX2TS R_408 ( .D(n3371), .CK(clk), .SN(n1250), .Q(n3030) );
DFFSX2TS R_411 ( .D(n3374), .CK(clk), .SN(n3335), .Q(n3027) );
DFFSX2TS R_414 ( .D(n3377), .CK(clk), .SN(n3334), .Q(n3024) );
DFFSX2TS R_429 ( .D(n3392), .CK(clk), .SN(n2338), .Q(n3012) );
DFFSX2TS R_440 ( .D(n3475), .CK(clk), .SN(n1248), .Q(n3005) );
DFFSX2TS R_443 ( .D(n3601), .CK(clk), .SN(n3318), .Q(n3002) );
DFFSX2TS R_449 ( .D(n3604), .CK(clk), .SN(n3321), .Q(n2996) );
DFFSX2TS R_222 ( .D(n3677), .CK(clk), .SN(n1254), .Q(n3173) );
DFFSX2TS R_260 ( .D(n3526), .CK(clk), .SN(n2944), .Q(n3167) );
DFFSX2TS R_263 ( .D(n3521), .CK(clk), .SN(n3324), .Q(n3164) );
DFFSX2TS R_266 ( .D(n3512), .CK(clk), .SN(n2946), .Q(n3161) );
DFFSX2TS R_269 ( .D(n3515), .CK(clk), .SN(n2947), .Q(n3158) );
DFFSX2TS R_272 ( .D(n3518), .CK(clk), .SN(n3324), .Q(n3155) );
DFFSX2TS R_275 ( .D(n3507), .CK(clk), .SN(n2336), .Q(n3152) );
DFFSX2TS R_287 ( .D(n3486), .CK(clk), .SN(n3331), .Q(n3149) );
DFFSX2TS R_293 ( .D(n3498), .CK(clk), .SN(n1233), .Q(n3143) );
DFFSX2TS R_296 ( .D(n3501), .CK(clk), .SN(n1234), .Q(n3140) );
DFFSX2TS R_299 ( .D(n3504), .CK(clk), .SN(n2947), .Q(n3137) );
DFFSX2TS R_302 ( .D(n3492), .CK(clk), .SN(n1254), .Q(n3134) );
DFFSX2TS R_305 ( .D(n3489), .CK(clk), .SN(n1253), .Q(n3131) );
DFFSX2TS R_308 ( .D(n3477), .CK(clk), .SN(n1249), .Q(n3128) );
DFFSX2TS R_317 ( .D(n3483), .CK(clk), .SN(n1253), .Q(n3119) );
DFFSX2TS R_320 ( .D(n3468), .CK(clk), .SN(n1249), .Q(n3116) );
DFFSX2TS R_323 ( .D(n3459), .CK(clk), .SN(n2949), .Q(n3113) );
DFFSX2TS R_326 ( .D(n3462), .CK(clk), .SN(n2949), .Q(n3110) );
DFFSX2TS R_329 ( .D(n3465), .CK(clk), .SN(n1248), .Q(n3107) );
DFFSX2TS R_332 ( .D(n3454), .CK(clk), .SN(n2949), .Q(n3104) );
DFFSX2TS R_335 ( .D(n3445), .CK(clk), .SN(n3327), .Q(n3101) );
DFFSX2TS R_338 ( .D(n3448), .CK(clk), .SN(n2950), .Q(n3098) );
DFFSX2TS R_341 ( .D(n3451), .CK(clk), .SN(n2949), .Q(n3095) );
DFFSX2TS R_352 ( .D(n3412), .CK(clk), .SN(n3342), .Q(n3086) );
DFFSX2TS R_355 ( .D(n3346), .CK(clk), .SN(n3332), .Q(n3083) );
DFFSX2TS R_358 ( .D(n3352), .CK(clk), .SN(n3334), .Q(n3080) );
DFFSX2TS R_364 ( .D(n3385), .CK(clk), .SN(n2337), .Q(n3074) );
DFFSX2TS R_367 ( .D(n3379), .CK(clk), .SN(n3341), .Q(n3071) );
DFFSX2TS R_370 ( .D(n3388), .CK(clk), .SN(n2339), .Q(n3068) );
DFFSX2TS R_373 ( .D(n3394), .CK(clk), .SN(n3340), .Q(n3065) );
DFFSX2TS R_376 ( .D(n3397), .CK(clk), .SN(n1246), .Q(n3062) );
DFFSX2TS R_379 ( .D(n3400), .CK(clk), .SN(n2590), .Q(n3059) );
DFFSX2TS R_382 ( .D(n3403), .CK(clk), .SN(n3341), .Q(n3056) );
DFFSX2TS R_385 ( .D(n3406), .CK(clk), .SN(n3340), .Q(n3053) );
DFFSX2TS R_388 ( .D(n3409), .CK(clk), .SN(n3342), .Q(n3050) );
DFFSX2TS R_391 ( .D(n3349), .CK(clk), .SN(n3330), .Q(n3047) );
DFFSX2TS R_394 ( .D(n3355), .CK(clk), .SN(n1253), .Q(n3044) );
DFFSX2TS R_397 ( .D(n3358), .CK(clk), .SN(n1252), .Q(n3041) );
DFFSX2TS R_400 ( .D(n3361), .CK(clk), .SN(n1246), .Q(n3038) );
DFFSX2TS R_403 ( .D(n3364), .CK(clk), .SN(n3335), .Q(n3035) );
DFFSX2TS R_406 ( .D(n3367), .CK(clk), .SN(n1251), .Q(n3032) );
DFFSX2TS R_409 ( .D(n3370), .CK(clk), .SN(n3333), .Q(n3029) );
DFFSX2TS R_412 ( .D(n3373), .CK(clk), .SN(n3331), .Q(n3026) );
DFFSX2TS R_415 ( .D(n3376), .CK(clk), .SN(n3330), .Q(n3023) );
DFFSX2TS R_418 ( .D(n3382), .CK(clk), .SN(n2933), .Q(n3020) );
DFFSX2TS R_430 ( .D(n3391), .CK(clk), .SN(n2338), .Q(n3011) );
DFFSX2TS R_441 ( .D(n3474), .CK(clk), .SN(n1249), .Q(n3004) );
DFFSX2TS R_444 ( .D(n3600), .CK(clk), .SN(n3323), .Q(n3001) );
DFFSX2TS R_447 ( .D(n3606), .CK(clk), .SN(n3315), .Q(n2998) );
DFFSX2TS R_450 ( .D(n3603), .CK(clk), .SN(n3322), .Q(n2995) );
DFFSX2TS R_57 ( .D(n3680), .CK(clk), .SN(n1236), .Q(n3269) );
DFFSX2TS R_505 ( .D(n3639), .CK(clk), .SN(n2934), .Q(n2972) );
DFFSX2TS R_503 ( .D(n3640), .CK(clk), .SN(n2932), .Q(n2974) );
DFFSX2TS R_502 ( .D(n3641), .CK(clk), .SN(n2932), .Q(n2975) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n639), .CK(clk), .RN(n3314), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n836), .CK(clk), .RN(n2940), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n638), .CK(clk), .RN(n3314), .Q(
overflow_flag) );
DFFSX2TS R_37 ( .D(n3638), .CK(clk), .SN(n2934), .Q(n3276) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n632), .CK(clk), .RN(n3314), .Q(
zero_flag) );
DFFSX2TS R_30 ( .D(n3633), .CK(clk), .SN(n2932), .Q(n3283) );
DFFSX2TS R_33 ( .D(n3645), .CK(clk), .SN(n2933), .Q(n3280) );
DFFSX2TS R_36 ( .D(n3642), .CK(clk), .SN(n3316), .Q(n3277) );
DFFSX2TS R_39 ( .D(n3636), .CK(clk), .SN(n3315), .Q(n3274) );
DFFSX2TS R_10 ( .D(n3655), .CK(clk), .SN(n2935), .Q(n3298) );
DFFSX2TS R_14 ( .D(n3658), .CK(clk), .SN(n2932), .Q(n3296) );
DFFSX2TS R_18 ( .D(n3652), .CK(clk), .SN(n2935), .Q(n3293) );
DFFSX2TS R_26 ( .D(n3673), .CK(clk), .SN(n2930), .Q(n3287) );
DFFSX2TS R_92 ( .D(n3667), .CK(clk), .SN(n2930), .Q(n3238) );
DFFSX2TS R_96 ( .D(n3661), .CK(clk), .SN(n2930), .Q(n3235) );
DFFSX2TS R_167 ( .D(n3625), .CK(clk), .SN(n2934), .Q(n3192) );
DFFSX2TS R_3 ( .D(n3669), .CK(clk), .SN(n2929), .Q(n3303) );
DFFSX2TS R_7 ( .D(n3630), .CK(clk), .SN(n2933), .Q(n3300) );
DFFSX2TS R_11 ( .D(n3654), .CK(clk), .SN(n2932), .Q(n3297) );
DFFSX2TS R_15 ( .D(n3657), .CK(clk), .SN(n2936), .Q(n3295) );
DFFSX2TS R_19 ( .D(n3651), .CK(clk), .SN(n2932), .Q(n3292) );
DFFSX2TS R_23 ( .D(n3648), .CK(clk), .SN(n2932), .Q(n3289) );
DFFSX2TS R_27 ( .D(n3672), .CK(clk), .SN(n2929), .Q(n3286) );
DFFSX2TS R_93 ( .D(n3666), .CK(clk), .SN(n2930), .Q(n3237) );
DFFSX2TS R_97 ( .D(n3660), .CK(clk), .SN(n2930), .Q(n3234) );
DFFSX2TS R_101 ( .D(n3663), .CK(clk), .SN(n2931), .Q(n3231) );
DFFSX2TS R_105 ( .D(n3627), .CK(clk), .SN(n2935), .Q(n3228) );
DFFSX2TS R_161 ( .D(n3612), .CK(clk), .SN(n2935), .Q(n3197) );
DFFSX2TS R_165 ( .D(n3609), .CK(clk), .SN(n2935), .Q(n3194) );
DFFSX2TS R_169 ( .D(n3624), .CK(clk), .SN(n2937), .Q(n3191) );
DFFSX2TS R_177 ( .D(n3618), .CK(clk), .SN(n2936), .Q(n3185) );
DFFSX2TS R_181 ( .D(n3615), .CK(clk), .SN(n2937), .Q(n3182) );
DFFSX2TS R_0 ( .D(n3671), .CK(clk), .SN(n2929), .Q(n3305) );
DFFSX1TS R_8 ( .D(n3656), .CK(clk), .SN(n2932), .Q(n3299) );
DFFSX2TS R_16 ( .D(n3653), .CK(clk), .SN(n2935), .Q(n3294) );
DFFSX1TS R_20 ( .D(n3650), .CK(clk), .SN(n2932), .Q(n3291) );
DFFSX2TS R_24 ( .D(n3675), .CK(clk), .SN(n2930), .Q(n3288) );
DFFSX2TS R_90 ( .D(n3668), .CK(clk), .SN(n2930), .Q(n3239) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n719), .CK(clk), .RN(n3321), .QN(
n2828) );
DFFRXLTS R_247 ( .D(sub_x_5_B_0_), .CK(clk), .RN(n1231), .Q(
DmP_mant_SFG_SWR[0]), .QN(n2926) );
DFFSX2TS R_309 ( .D(n3420), .CK(clk), .SN(n2951), .Q(n3127) );
DFFSX2TS R_310 ( .D(n3419), .CK(clk), .SN(n2951), .Q(n3126) );
DFFSX2TS R_311 ( .D(n3418), .CK(clk), .SN(n2951), .Q(n3125) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n841), .CK(clk), .RN(n2929), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n840), .CK(clk), .RN(n2929), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n839), .CK(clk), .RN(n2929), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n838), .CK(clk), .RN(n2929), .Q(
final_result_ieee[26]) );
DFFSX2TS R_289 ( .D(n3425), .CK(clk), .SN(n2951), .Q(n3147) );
DFFSX2TS R_313 ( .D(n3431), .CK(clk), .SN(n2951), .Q(n3123) );
DFFSX2TS R_346 ( .D(n3443), .CK(clk), .SN(n1238), .Q(n3090) );
DFFSX2TS R_423 ( .D(n3428), .CK(clk), .SN(n2952), .QN(n1193) );
DFFSX2TS R_432 ( .D(n3422), .CK(clk), .SN(n2953), .Q(n3009) );
DFFSX2TS R_288 ( .D(n3426), .CK(clk), .SN(n2951), .Q(n3148) );
DFFSX2TS R_312 ( .D(n3432), .CK(clk), .SN(n2952), .Q(n3124) );
DFFSX2TS R_345 ( .D(n3444), .CK(clk), .SN(n2338), .Q(n3091) );
DFFSX2TS R_422 ( .D(n3429), .CK(clk), .SN(n2952), .QN(n1192) );
DFFSX2TS R_431 ( .D(n3423), .CK(clk), .SN(n2953), .Q(n3010) );
DFFSX2TS R_314 ( .D(n3430), .CK(clk), .SN(n2951), .Q(n3122) );
DFFSX2TS R_347 ( .D(n3442), .CK(clk), .SN(n3325), .Q(n3089) );
DFFSX2TS R_433 ( .D(n3421), .CK(clk), .SN(n2953), .Q(n3008) );
DFFSX2TS R_343 ( .D(n3434), .CK(clk), .SN(n2952), .Q(n3093) );
DFFSX2TS R_426 ( .D(n3437), .CK(clk), .SN(n2953), .Q(n3015) );
DFFSX2TS R_342 ( .D(n3435), .CK(clk), .SN(n2952), .Q(n3094) );
DFFSX2TS R_425 ( .D(n3438), .CK(clk), .SN(n2953), .Q(n3016) );
DFFSX2TS R_344 ( .D(n3433), .CK(clk), .SN(n2952), .Q(n3092) );
DFFSX2TS R_421 ( .D(n3439), .CK(clk), .SN(n3325), .Q(n3017) );
DFFSX2TS R_427 ( .D(n3436), .CK(clk), .SN(n2953), .Q(n3014) );
DFFSX2TS R_497 ( .D(n3571), .CK(clk), .SN(n2948), .Q(n2980) );
DFFSX2TS R_496 ( .D(n1256), .CK(clk), .SN(n2948), .Q(n2981) );
DFFSX2TS R_488 ( .D(n1537), .CK(clk), .SN(n3344), .Q(n2986) );
DFFSX2TS R_500 ( .D(n1256), .CK(clk), .SN(n1232), .Q(n2977) );
DFFSX2TS R_508 ( .D(n1537), .CK(clk), .SN(n1237), .Q(n2969) );
DFFSX2TS R_512 ( .D(n1256), .CK(clk), .SN(n2336), .Q(n2966) );
DFFSX2TS R_516 ( .D(n1537), .CK(clk), .SN(n2938), .Q(n2962) );
DFFSX2TS R_524 ( .D(n1256), .CK(clk), .SN(n2946), .Q(n2957) );
DFFSX2TS R_489 ( .D(n3563), .CK(clk), .SN(n3344), .Q(n2985) );
DFFSX2TS R_501 ( .D(n3551), .CK(clk), .SN(n1232), .Q(n2976) );
DFFSX2TS R_509 ( .D(n3589), .CK(clk), .SN(n2939), .Q(n2968) );
DFFSX2TS R_517 ( .D(n3558), .CK(clk), .SN(n1232), .Q(n2961) );
DFFSX2TS R_521 ( .D(n3583), .CK(clk), .SN(n2336), .Q(n2959) );
DFFSX2TS R_525 ( .D(n3565), .CK(clk), .SN(n2947), .Q(n2956) );
DFFSX2TS R_72 ( .D(n3559), .CK(clk), .SN(n2943), .Q(n3255) );
DFFSX2TS R_70 ( .D(n3561), .CK(clk), .SN(n2943), .Q(n3257) );
DFFSX2TS R_476 ( .D(n870), .CK(clk), .SN(n1237), .Q(n2990) );
DFFSX2TS R_506 ( .D(n3308), .CK(clk), .SN(n2941), .Q(n2971) );
DFFSX2TS R_118 ( .D(n3554), .CK(clk), .SN(n2943), .Q(n3226) );
DFFSX2TS R_117 ( .D(n3555), .CK(clk), .SN(n2943), .Q(n3227) );
DFFSX2TS R_60 ( .D(n3584), .CK(clk), .SN(n2939), .Q(n3267) );
DFFSX1TS R_35 ( .D(n3643), .CK(clk), .SN(n3316), .Q(n3278) );
DFFSX1TS R_28 ( .D(n3635), .CK(clk), .SN(n3316), .Q(n3285) );
DFFSX1TS R_31 ( .D(n3647), .CK(clk), .SN(n3315), .Q(n3282) );
DFFSX1TS R_34 ( .D(n3644), .CK(clk), .SN(n3315), .Q(n3279) );
DFFSX1TS R_5 ( .D(n3631), .CK(clk), .SN(n2931), .Q(n3301) );
DFFSX1TS R_103 ( .D(n3628), .CK(clk), .SN(n2935), .Q(n3229) );
DFFSX1TS R_159 ( .D(n3613), .CK(clk), .SN(n2935), .Q(n3198) );
DFFSX1TS R_163 ( .D(n3610), .CK(clk), .SN(n2936), .Q(n3195) );
DFFSX1TS R_171 ( .D(n3622), .CK(clk), .SN(n2936), .Q(n3189) );
DFFSX1TS R_175 ( .D(n3619), .CK(clk), .SN(n2936), .Q(n3186) );
DFFSX1TS R_179 ( .D(n3616), .CK(clk), .SN(n2937), .Q(n3183) );
DFFSX1TS R_4 ( .D(n3632), .CK(clk), .SN(n3343), .Q(n3302) );
DFFSX1TS R_94 ( .D(n3662), .CK(clk), .SN(n2931), .Q(n3236) );
DFFSX1TS R_98 ( .D(n3665), .CK(clk), .SN(n2931), .Q(n3233) );
DFFSX1TS R_102 ( .D(n3629), .CK(clk), .SN(n2935), .Q(n3230) );
DFFSX1TS R_158 ( .D(n3614), .CK(clk), .SN(n2935), .Q(n3199) );
DFFSX1TS R_162 ( .D(n3611), .CK(clk), .SN(n2936), .Q(n3196) );
DFFSX1TS R_170 ( .D(n3623), .CK(clk), .SN(n2936), .Q(n3190) );
DFFSX1TS R_174 ( .D(n3620), .CK(clk), .SN(n2937), .Q(n3187) );
DFFSX1TS R_178 ( .D(n3617), .CK(clk), .SN(n3343), .Q(n3184) );
DFFSX2TS sub_x_5_R_278 ( .D(n2783), .CK(clk), .SN(n2939), .Q(sub_x_5_n190),
.QN(n2791) );
DFFSX2TS sub_x_5_R_276 ( .D(n2778), .CK(clk), .SN(n1232), .Q(sub_x_5_n249)
);
DFFSX2TS sub_x_5_R_454 ( .D(n2785), .CK(clk), .SN(n2942), .Q(sub_x_5_n201),
.QN(n2789) );
DFFSX1TS sub_x_5_R_457 ( .D(n2787), .CK(clk), .SN(n2942), .Q(sub_x_5_n203)
);
DFFSX1TS sub_x_5_R_452 ( .D(n2782), .CK(clk), .SN(n3681), .Q(sub_x_5_n206)
);
DFFRXLTS sub_x_5_R_456 ( .D(n1347), .CK(clk), .RN(n2942), .Q(sub_x_5_B_1_)
);
DFFRXLTS sub_x_5_R_455 ( .D(n2786), .CK(clk), .RN(n2942), .Q(sub_x_5_n204)
);
DFFSX2TS add_x_6_R_240 ( .D(n2753), .CK(clk), .SN(n1254), .Q(add_x_6_n70),
.QN(n2766) );
DFFSX2TS add_x_6_R_471 ( .D(n2761), .CK(clk), .SN(n1234), .Q(add_x_6_n77),
.QN(n2774) );
DFFSX2TS add_x_6_R_244 ( .D(n2747), .CK(clk), .SN(n3315), .Q(add_x_6_n128),
.QN(n2772) );
DFFSX1TS add_x_6_R_257 ( .D(n2758), .CK(clk), .SN(n3334), .Q(add_x_6_n89) );
DFFSX1TS add_x_6_R_246 ( .D(n2755), .CK(clk), .SN(n3333), .Q(add_x_6_n121)
);
DFFRX2TS add_x_6_R_242 ( .D(n545), .CK(clk), .RN(n2945), .Q(add_x_6_B_21_)
);
DFFRX2TS add_x_6_R_241 ( .D(n740), .CK(clk), .RN(n1237), .Q(add_x_6_A_21_)
);
DFFRX4TS R_459 ( .D(n849), .CK(clk), .RN(n2942), .Q(shift_value_SHT2_EWR[3]),
.QN(n1042) );
DFFRX4TS R_250 ( .D(n1077), .CK(clk), .RN(n3318), .Q(DmP_mant_SFG_SWR[12]),
.QN(n1638) );
DFFRX4TS R_195 ( .D(n560), .CK(clk), .RN(n3328), .Q(DmP_mant_SFG_SWR[6]),
.QN(n1636) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n543), .CK(clk), .RN(n2941), .Q(
DmP_mant_SFG_SWR[23]), .QN(n1634) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n544), .CK(clk), .RN(n2939), .Q(
DmP_mant_SFG_SWR[22]), .QN(n1622) );
DFFRX4TS R_41 ( .D(n562), .CK(clk), .RN(n3322), .Q(DmP_mant_SFG_SWR[4]),
.QN(n1641) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n542), .CK(clk), .RN(n2942), .Q(
DmP_mant_SFG_SWR[24]), .QN(n1627) );
DFFRX4TS R_202 ( .D(n749), .CK(clk), .RN(n3334), .Q(DMP_SFG[16]), .QN(n2886)
);
DFFRX4TS SGF_STAGE_DMP_Q_reg_20_ ( .D(n737), .CK(clk), .RN(n2938), .Q(
DMP_SFG[20]), .QN(n2902) );
DFFRX4TS R_462 ( .D(n776), .CK(clk), .RN(n3341), .Q(DMP_SFG[7]), .QN(n2910)
);
DFFRX4TS SGF_STAGE_DMP_Q_reg_15_ ( .D(n752), .CK(clk), .RN(n3333), .Q(
DMP_SFG[15]), .QN(n2904) );
DFFRX4TS R_189 ( .D(n558), .CK(clk), .RN(n2939), .Q(DmP_mant_SFG_SWR[8]),
.QN(n1643) );
DFFRX4TS R_470 ( .D(n546), .CK(clk), .RN(n2938), .Q(DmP_mant_SFG_SWR[20]),
.QN(n1626) );
DFFRX4TS SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n878), .CK(clk), .RN(n2951), .Q(
bit_shift_SHT2) );
DFFRX4TS R_113 ( .D(n551), .CK(clk), .RN(n3322), .Q(DmP_mant_SFG_SWR[15]),
.QN(n1047) );
DFFRX4TS R_478 ( .D(n773), .CK(clk), .RN(n2955), .Q(sub_x_5_A_10_), .QN(
n2831) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n550), .CK(clk), .RN(n3319), .Q(
DmP_mant_SFG_SWR[16]), .QN(n1629) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n903), .CK(clk), .RN(n1251), .Q(
intDY_EWSW[7]), .QN(n2856) );
DFFRX2TS add_x_6_R_473 ( .D(n546), .CK(clk), .RN(n1232), .Q(add_x_6_B_20_)
);
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n895), .CK(clk), .RN(n1250),
.Q(intDY_EWSW[15]), .QN(n2854) );
DFFRX4TS R_215 ( .D(n559), .CK(clk), .RN(n3328), .Q(DmP_mant_SFG_SWR[7]),
.QN(n1630) );
DFFRX4TS R_348 ( .D(sub_x_5_B_17_), .CK(clk), .RN(n3322), .Q(
DmP_mant_SFG_SWR[17]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n892), .CK(clk), .RN(n3335),
.Q(intDY_EWSW[18]), .QN(n2873) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n592), .CK(clk), .RN(n3321), .Q(
LZD_output_NRM2_EW[2]), .QN(n1000) );
DFFRX4TS R_40 ( .D(n791), .CK(clk), .RN(n3329), .Q(DMP_SFG[2]), .QN(n2906)
);
DFFRX4TS R_280 ( .D(n553), .CK(clk), .RN(n3321), .Q(DmP_mant_SFG_SWR[13]),
.QN(n1639) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n899), .CK(clk), .RN(n3331),
.Q(intDY_EWSW[11]), .QN(n2855) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_14_ ( .D(n755), .CK(clk), .RN(n3334), .Q(
DMP_SFG[14]), .QN(n2901) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n619), .CK(clk), .RN(n2942), .Q(
Raw_mant_NRM_SWR[1]), .QN(n2842) );
DFFRX4TS R_46 ( .D(n547), .CK(clk), .RN(n3323), .Q(DmP_mant_SFG_SWR[19]),
.QN(n1637) );
DFFRX4TS R_141 ( .D(n552), .CK(clk), .RN(n3320), .Q(DmP_mant_SFG_SWR[14]),
.QN(n1631) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n596), .CK(clk), .RN(n3332), .Q(
Raw_mant_NRM_SWR[24]), .QN(n3309) );
DFFRX4TS R_224 ( .D(n555), .CK(clk), .RN(n3318), .Q(sub_x_5_B_11_), .QN(
n1632) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n909), .CK(clk), .RN(n1250), .Q(
intDY_EWSW[1]), .QN(n2846) );
DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n696), .CK(clk), .RN(n3321), .Q(
DMP_exp_NRM2_EW[6]), .QN(n2837) );
DFFRX4TS R_231 ( .D(n2792), .CK(clk), .RN(n2951), .Q(add_x_6_A_2_), .QN(
n2889) );
DFFRX4TS R_469 ( .D(n743), .CK(clk), .RN(n2945), .Q(DMP_SFG[18]), .QN(n2912)
);
DFFRX4TS SGF_STAGE_DMP_Q_reg_21_ ( .D(n734), .CK(clk), .RN(n3332), .Q(
DMP_SFG[21]), .QN(n2903) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n701), .CK(clk), .RN(n2934), .Q(
DMP_exp_NRM2_EW[5]), .QN(n2834) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n943), .CK(clk), .RN(n3337), .Q(
intDX_EWSW[0]) );
DFFRX4TS inst_ShiftRegister_Q_reg_2_ ( .D(n946), .CK(clk), .RN(n3340), .Q(
Shift_reg_FLAGS_7[2]), .QN(n2899) );
DFFRX4TS R_458 ( .D(n1204), .CK(clk), .RN(n3326), .Q(shift_value_SHT2_EWR[2]), .QN(n1053) );
DFFRX4TS add_x_6_R_227 ( .D(n555), .CK(clk), .RN(n2950), .Q(add_x_6_B_11_)
);
DFFSX4TS add_x_6_R_281 ( .D(n2759), .CK(clk), .SN(n3342), .Q(add_x_6_n138),
.QN(n2767) );
DFFRX2TS R_238 ( .D(n740), .CK(clk), .RN(n2944), .Q(DMP_SFG[19]), .QN(n2911)
);
DFFRX2TS add_x_6_R_481 ( .D(n773), .CK(clk), .RN(n2953), .Q(add_x_6_A_10_)
);
DFFRX4TS R_45 ( .D(n746), .CK(clk), .RN(n1251), .Q(DMP_SFG[17]), .QN(n2888)
);
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n593), .CK(clk), .RN(n3320), .Q(
LZD_output_NRM2_EW[0]), .QN(n2839) );
DFFRX4TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n847), .CK(clk), .RN(n1234), .Q(
shift_value_SHT2_EWR[4]), .QN(n2848) );
DFFSX4TS R_461 ( .D(n2993), .CK(clk), .SN(n3344), .Q(n3530) );
DFFRX2TS sub_x_5_R_279 ( .D(n788), .CK(clk), .RN(n1239), .Q(sub_x_5_A_5_) );
DFFRX2TS add_x_6_R_192 ( .D(n558), .CK(clk), .RN(n3327), .Q(add_x_6_B_8_) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n893), .CK(clk), .RN(n3333),
.Q(intDY_EWSW[17]), .QN(n2853) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n897), .CK(clk), .RN(n3332),
.Q(intDY_EWSW[13]), .QN(n2868) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n590), .CK(clk), .RN(n3317), .Q(
LZD_output_NRM2_EW[4]), .QN(n2905) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n915), .CK(clk), .RN(n3339),
.Q(intDX_EWSW[28]) );
DFFRX4TS R_188 ( .D(n779), .CK(clk), .RN(n1246), .Q(DMP_SFG[6]), .QN(n2908)
);
DFFRX2TS add_x_6_R_191 ( .D(n779), .CK(clk), .RN(n3341), .Q(add_x_6_A_8_) );
DFFRX4TS R_467 ( .D(n604), .CK(clk), .RN(n1238), .Q(Raw_mant_NRM_SWR[16]),
.QN(n1022) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n887), .CK(clk), .RN(n3336),
.Q(intDY_EWSW[23]), .QN(n2851) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n905), .CK(clk), .RN(n3335), .Q(
intDY_EWSW[5]), .QN(n2870) );
DFFRX2TS R_52 ( .D(n3529), .CK(clk), .RN(n1231), .Q(n3271) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n891), .CK(clk), .RN(n3336),
.Q(intDY_EWSW[19]), .QN(n2867) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_22_ ( .D(n731), .CK(clk), .RN(n3331), .Q(
DMP_SFG[22]), .QN(n2916) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n706), .CK(clk), .RN(n3317), .Q(
DMP_exp_NRM2_EW[4]), .QN(n2838) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n901), .CK(clk), .RN(n3334), .Q(
intDY_EWSW[9]), .QN(n2849) );
DFFRX2TS R_477 ( .D(n1242), .CK(clk), .RN(n2938), .Q(n2989) );
DFFSX4TS sub_x_5_R_54 ( .D(n2777), .CK(clk), .SN(n3322), .Q(sub_x_5_n244) );
DFFSRHQX4TS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n623), .CK(clk), .SN(1'b1), .RN(
n1264), .Q(SIGN_FLAG_NRM) );
DFFRX1TS R_236 ( .D(final_result_ieee[30]), .CK(clk), .RN(n2933), .Q(n3170)
);
DFFSRHQX4TS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n679), .CK(clk), .SN(1'b1),
.RN(n1233), .Q(DmP_mant_SHT1_SW[5]) );
DFFRHQX8TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n3330), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]) );
DFFRHQX8TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n952), .CK(clk), .RN(
n1236), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRHQX2TS inst_ShiftRegister_Q_reg_5_ ( .D(n949), .CK(clk), .RN(n1264), .Q(
Shift_reg_FLAGS_7_5) );
DFFRX4TS inst_ShiftRegister_Q_reg_3_ ( .D(n947), .CK(clk), .RN(n3681), .Q(
Shift_reg_FLAGS_7[3]), .QN(n2801) );
DFFSX4TS add_x_6_R_254 ( .D(n2745), .CK(clk), .SN(n1238), .Q(add_x_6_n88),
.QN(n2771) );
DFFSX1TS R_173 ( .D(n3621), .CK(clk), .SN(n2936), .Q(n3188) );
DFFSX1TS R_294 ( .D(n3503), .CK(clk), .SN(n2947), .Q(n3142) );
DFFSHQX8TS add_x_6_R_251 ( .D(n2756), .CK(clk), .SN(n3681), .Q(add_x_6_n145)
);
DFFSX4TS R_463_IP ( .D(n2739), .CK(clk), .SN(n3681), .Q(sub_x_5_n245), .QN(
DmP_mant_SFG_SWR[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n765), .CK(clk), .RN(n3343), .Q(
DMP_SHT2_EWSW[11]), .QN(n2879) );
DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n717), .CK(clk), .RN(n3321), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n694), .CK(clk), .RN(n3323), .Q(
DMP_SHT2_EWSW[30]), .QN(n2826) );
DFFSX1TS R_139 ( .D(n3524), .CK(clk), .SN(n1233), .Q(n3209) );
DFFSX1TS R_155 ( .D(n3534), .CK(clk), .SN(n1232), .Q(n3200) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_25_ ( .D(n718), .CK(clk), .RN(n3323), .Q(
DMP_SFG[25]), .QN(n2918) );
DFFSX1TS R_166 ( .D(n3626), .CK(clk), .SN(n2934), .Q(n3193) );
DFFRX1TS add_x_6_R_245 ( .D(n2754), .CK(clk), .RN(n1251), .Q(add_x_6_n115),
.QN(n2775) );
DFFRX4TS inst_ShiftRegister_Q_reg_0_ ( .D(n944), .CK(clk), .RN(n3340), .Q(
Shift_reg_FLAGS_7[0]), .QN(n1644) );
DFFRX4TS sub_x_5_R_109 ( .D(n2779), .CK(clk), .RN(n1231), .Q(sub_x_5_n198),
.QN(n2788) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n883), .CK(clk), .RN(n3336),
.Q(intDY_EWSW[27]), .QN(n2850) );
DFFRX4TS R_283 ( .D(n2897), .CK(clk), .RN(n3343), .Q(sub_x_5_A_13_), .QN(
n2830) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n711), .CK(clk), .RN(n3318), .Q(
DMP_exp_NRM2_EW[3]), .QN(n2861) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n618), .CK(clk), .RN(n2590), .Q(
Raw_mant_NRM_SWR[2]), .QN(n2835) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n598), .CK(clk), .RN(n2939), .Q(
Raw_mant_NRM_SWR[22]), .QN(n977) );
DFFRX4TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n846), .CK(clk), .RN(n3330),
.Q(Shift_amount_SHT1_EWR[0]), .QN(n2915) );
DFFRX4TS add_x_6_R_197 ( .D(n785), .CK(clk), .RN(n2950), .Q(add_x_6_A_6_) );
DFFRX4TS add_x_6_R_211 ( .D(sub_x_5_B_5_), .CK(clk), .RN(n2950), .Q(
add_x_6_B_5_) );
DFFRX4TS add_x_6_R_210 ( .D(n788), .CK(clk), .RN(n2950), .Q(add_x_6_A_5_) );
DFFRX4TS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n911), .CK(clk), .RN(n3328), .Q(
intAS) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n879), .CK(clk), .RN(n3328),
.Q(intDY_EWSW[31]) );
DFFRX4TS add_x_6_R_217 ( .D(n2896), .CK(clk), .RN(n3325), .Q(add_x_6_A_7_)
);
DFFRX4TS add_x_6_R_252 ( .D(n767), .CK(clk), .RN(n2948), .Q(add_x_6_A_12_)
);
DFFRX4TS add_x_6_R_144 ( .D(n552), .CK(clk), .RN(n2336), .Q(add_x_6_B_14_)
);
DFFRX4TS add_x_6_R_143 ( .D(n761), .CK(clk), .RN(n2339), .Q(add_x_6_A_14_)
);
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n900), .CK(clk), .RN(n3330),
.Q(intDY_EWSW[10]), .QN(n2862) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n896), .CK(clk), .RN(n1251),
.Q(intDY_EWSW[14]), .QN(n2845) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n888), .CK(clk), .RN(n3340),
.Q(intDY_EWSW[22]), .QN(n2844) );
DFFRX4TS R_108 ( .D(n794), .CK(clk), .RN(n3329), .Q(DMP_SFG[1]), .QN(n2885)
);
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n885), .CK(clk), .RN(n3336),
.Q(intDY_EWSW[25]), .QN(n2871) );
DFFRX4TS R_212 ( .D(sub_x_5_B_2_), .CK(clk), .RN(n1236), .Q(
DmP_mant_SFG_SWR[2]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n886), .CK(clk), .RN(n3336),
.Q(intDY_EWSW[24]), .QN(n2843) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n904), .CK(clk), .RN(n3331), .Q(
intDY_EWSW[6]), .QN(n2863) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n890), .CK(clk), .RN(n3336),
.Q(intDY_EWSW[20]), .QN(n2872) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n907), .CK(clk), .RN(n3333), .Q(
intDY_EWSW[3]), .QN(n2869) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n889), .CK(clk), .RN(n3336),
.Q(intDY_EWSW[21]), .QN(n2852) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n902), .CK(clk), .RN(n3334), .Q(
intDY_EWSW[8]), .QN(n2858) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n615), .CK(clk), .RN(n1238), .Q(
Raw_mant_NRM_SWR[5]), .QN(n2833) );
DFFRX4TS inst_ShiftRegister_Q_reg_4_ ( .D(n948), .CK(clk), .RN(n3340), .Q(
n3682), .QN(n2928) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n881), .CK(clk), .RN(n3336),
.Q(intDY_EWSW[29]), .QN(n2866) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n894), .CK(clk), .RN(n1250),
.Q(intDY_EWSW[16]), .QN(n2874) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n884), .CK(clk), .RN(n3336),
.Q(intDY_EWSW[26]), .QN(n2864) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n898), .CK(clk), .RN(n3335),
.Q(intDY_EWSW[12]), .QN(n2857) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n882), .CK(clk), .RN(n3336),
.Q(intDY_EWSW[28]), .QN(n2847) );
DFFRX4TS R_218 ( .D(n2896), .CK(clk), .RN(n2954), .Q(sub_x_5_A_7_), .QN(
n2829) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n591), .CK(clk), .RN(n3323), .Q(
LZD_output_NRM2_EW[1]), .QN(n2840) );
DFFRX4TS R_194 ( .D(n785), .CK(clk), .RN(n2954), .Q(DMP_SFG[4]), .QN(n2909)
);
DFFRX4TS R_112 ( .D(n758), .CK(clk), .RN(n3330), .Q(DMP_SFG[13]), .QN(n2883)
);
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n906), .CK(clk), .RN(n3330), .Q(
intDY_EWSW[4]), .QN(n2859) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n912), .CK(clk), .RN(n3328),
.Q(intDX_EWSW[31]), .QN(n2890) );
DFFRX4TS R_223 ( .D(n770), .CK(clk), .RN(n2955), .Q(sub_x_5_A_11_), .QN(
n2887) );
DFFRX4TS add_x_6_R_226 ( .D(n770), .CK(clk), .RN(n2950), .Q(add_x_6_A_11_)
);
DFFRX4TS R_239 ( .D(n545), .CK(clk), .RN(n2939), .Q(DmP_mant_SFG_SWR[21]),
.QN(n1642) );
DFFSX4TS add_x_6_R_216 ( .D(n2752), .CK(clk), .SN(n2931), .Q(add_x_6_n183),
.QN(n2765) );
DFFSX4TS add_x_6_R_209 ( .D(n2751), .CK(clk), .SN(n2931), .Q(add_x_6_n194),
.QN(n2769) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n908), .CK(clk), .RN(n1251), .Q(
intDY_EWSW[2]), .QN(n2860) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n594), .CK(clk), .RN(n3322), .Q(
LZD_output_NRM2_EW[3]), .QN(n3306) );
DFFSX2TS R_86 ( .D(n3538), .CK(clk), .SN(n2336), .Q(n3243) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n617), .CK(clk), .RN(n3325), .Q(
Raw_mant_NRM_SWR[3]), .QN(n2894) );
DFFRX4TS inst_ShiftRegister_Q_reg_6_ ( .D(n950), .CK(clk), .RN(n3340), .Q(
Shift_reg_FLAGS_7_6), .QN(n2927) );
DFFSX4TS R_514 ( .D(n3308), .CK(clk), .SN(n1236), .Q(n2964) );
DFFRX4TS R_249 ( .D(n767), .CK(clk), .RN(n2955), .Q(DMP_SFG[10]), .QN(n2913)
);
DFFSX2TS R_127 ( .D(n3535), .CK(clk), .SN(n3344), .Q(n3217) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n880), .CK(clk), .RN(n3337),
.Q(intDY_EWSW[30]), .QN(n2865) );
DFFSX4TS R_438 ( .D(n3007), .CK(clk), .SN(n1239), .Q(n3549) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n616), .CK(clk), .RN(n1238), .Q(
Raw_mant_NRM_SWR[4]), .QN(n2893) );
DFFRX4TS R_515 ( .D(n3556), .CK(clk), .RN(n1231), .Q(n2963) );
DFFRX2TS add_x_6_R_465 ( .D(n776), .CK(clk), .RN(n2937), .Q(add_x_6_A_9_) );
DFFRX4TS R_140 ( .D(n761), .CK(clk), .RN(n3343), .Q(DMP_SFG[12]), .QN(n2884)
);
DFFRX4TS add_x_6_R_219 ( .D(n559), .CK(clk), .RN(n2954), .Q(add_x_6_B_7_) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n910), .CK(clk), .RN(n1250), .Q(
intDY_EWSW[0]), .QN(n2875) );
DFFSX4TS add_x_6_R_196 ( .D(n2749), .CK(clk), .SN(n2931), .Q(add_x_6_n189),
.QN(n2773) );
DFFSX4TS R_290 ( .D(n3424), .CK(clk), .SN(n2951), .Q(n3146) );
DFFSX4TS add_x_6_R_190 ( .D(n2748), .CK(clk), .SN(n2934), .Q(add_x_6_n172),
.QN(n2764) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n541), .CK(clk), .RN(n3319), .Q(
DmP_mant_SFG_SWR[25]), .QN(n1640) );
DFFRX4TS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n801), .CK(clk), .RN(n3314), .Q(
ZERO_FLAG_EXP), .QN(n2878) );
DFFSX4TS R_50 ( .D(n1263), .CK(clk), .SN(n2945), .Q(n3273) );
DFFRX2TS add_x_6_R_282 ( .D(n2897), .CK(clk), .RN(n2337), .Q(add_x_6_A_13_)
);
DFFSX4TS add_x_6_R_480 ( .D(n2762), .CK(clk), .SN(n3681), .Q(add_x_6_n160)
);
DFFRX4TS add_x_6_R_284 ( .D(n553), .CK(clk), .RN(n2339), .Q(add_x_6_B_13_)
);
DFFSX4TS add_x_6_R_464 ( .D(n2760), .CK(clk), .SN(n2934), .Q(add_x_6_n167),
.QN(n2768) );
DFFSX4TS sub_x_5_R_349 ( .D(n2784), .CK(clk), .SN(n3319), .Q(sub_x_5_n237)
);
DFFSX4TS R_474 ( .D(n3313), .CK(clk), .SN(n2938), .Q(n2991) );
DFFSX2TS R_63 ( .D(n3495), .CK(clk), .SN(n1253), .Q(n3264) );
DFFSX4TS add_x_6_R_42 ( .D(n2744), .CK(clk), .SN(n3342), .Q(add_x_6_n197),
.QN(n2763) );
DFFRX2TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n629), .CK(clk), .RN(n3327), .Q(
OP_FLAG_SFG), .QN(n2800) );
DFFRX4TS add_x_6_R_253 ( .D(n1077), .CK(clk), .RN(n2955), .Q(add_x_6_B_12_)
);
DFFSX4TS R_486 ( .D(n3308), .CK(clk), .SN(n3344), .Q(n2988) );
DFFRX4TS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n843), .CK(clk), .RN(n3328),
.QN(n2822) );
DFFRX4TS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n835), .CK(clk), .RN(n1252), .Q(
final_result_ieee[29]) );
DFFRHQX2TS add_x_6_R_472 ( .D(n743), .CK(clk), .RN(n1237), .Q(add_x_6_A_20_)
);
DFFRX1TS sub_x_5_R_453 ( .D(n2781), .CK(clk), .RN(n3681), .QN(n2790) );
DFFSX2TS R_518 ( .D(n1368), .CK(clk), .SN(n3326), .Q(n2960) );
DFFSX4TS R_365 ( .D(n3381), .CK(clk), .SN(n2336), .Q(n3073) );
DFFSX4TS R_375 ( .D(n3398), .CK(clk), .SN(n2336), .Q(n3063) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n612), .CK(clk), .RN(n3324), .Q(
n1220) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n601), .CK(clk), .RN(n3325),
.Q(n1218) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n597), .CK(clk), .RN(n3327),
.Q(n1216) );
DFFRHQX8TS NRM_STAGE_FLAGS_Q_reg_2_ ( .D(n628), .CK(clk), .RN(n3320), .Q(
n1212) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n600), .CK(clk), .RN(n3325),
.Q(n1210) );
DFFRHQX8TS inst_ShiftRegister_Q_reg_1_ ( .D(n945), .CK(clk), .RN(n3340), .Q(
n1207) );
DFFRX4TS add_x_6_R_206 ( .D(n548), .CK(clk), .RN(n3332), .Q(add_x_6_B_18_)
);
DFFRX4TS add_x_6_R_205 ( .D(n749), .CK(clk), .RN(n3335), .Q(add_x_6_A_18_)
);
DFFSX2TS R_29 ( .D(n3634), .CK(clk), .SN(n2933), .Q(n3284) );
DFFSX2TS R_22 ( .D(n3649), .CK(clk), .SN(n2932), .Q(n3290) );
DFFSX2TS R_38 ( .D(n3637), .CK(clk), .SN(n2933), .Q(n3275) );
DFFSX2TS R_2 ( .D(n3670), .CK(clk), .SN(n2929), .Q(n3304) );
DFFSX2TS R_32 ( .D(n3646), .CK(clk), .SN(n3315), .Q(n3281) );
DFFSX2TS R_100 ( .D(n3664), .CK(clk), .SN(n2931), .Q(n3232) );
DFFSX1TS R_234 ( .D(n1405), .CK(clk), .SN(n2941), .Q(n3172) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n942), .CK(clk), .RN(n3337),
.Q(n1205) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n595), .CK(clk), .RN(n2590),
.Q(n1202) );
DFFSX4TS R_59 ( .D(n3585), .CK(clk), .SN(n2938), .Q(n3268) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n914), .CK(clk), .RN(n3340),
.Q(n1195) );
DFFSX2TS R_424 ( .D(n3427), .CK(clk), .SN(n2952), .QN(n1194) );
DFFSX4TS sub_x_5_R_110 ( .D(n2780), .CK(clk), .SN(n3319), .Q(sub_x_5_n251)
);
DFFRX4TS sub_x_5_R_111 ( .D(n794), .CK(clk), .RN(n1233), .Q(sub_x_5_A_3_) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n932), .CK(clk), .RN(n3338),
.Q(n1187) );
DFFRHQX2TS add_x_6_R_256 ( .D(n2757), .CK(clk), .RN(n3330), .Q(n1185) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n940), .CK(clk), .RN(n3337),
.Q(n1178) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n937), .CK(clk), .RN(n3337),
.Q(n1177) );
DFFRHQX8TS R_203 ( .D(n548), .CK(clk), .RN(n3319), .Q(n1175) );
DFFRHQX8TS SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n627), .CK(clk), .RN(n3321),
.Q(n1170) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n605), .CK(clk), .RN(n1239),
.Q(n1166) );
DFFSX1TS R_420 ( .D(n3440), .CK(clk), .SN(n2590), .Q(n3018) );
DFFRHQX8TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n721), .CK(clk), .RN(n3320),
.Q(n1163) );
DFFSX2TS R_120 ( .D(n3552), .CK(clk), .SN(n2943), .Q(n3224) );
DFFSX2TS R_62 ( .D(n3496), .CK(clk), .SN(n1254), .Q(n3265) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n607), .CK(clk), .RN(n1238),
.Q(n1152) );
DFFRX4TS add_x_6_R_43 ( .D(n791), .CK(clk), .RN(n3342), .Q(add_x_6_A_4_) );
DFFSX2TS add_x_6_R_243 ( .D(n2746), .CK(clk), .SN(n3334), .Q(add_x_6_n120),
.QN(n2770) );
DFFSX1TS R_333 ( .D(n3447), .CK(clk), .SN(n3325), .Q(n3103) );
DFFSX2TS R_85 ( .D(n3540), .CK(clk), .SN(n3326), .Q(n3244) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n603), .CK(clk), .RN(n1239),
.Q(n1135) );
DFFSX1TS R_417 ( .D(n3383), .CK(clk), .SN(n3316), .Q(n3021) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n610), .CK(clk), .RN(n1239),
.Q(n1129) );
DFFRX4TS add_x_6_R_466 ( .D(n557), .CK(clk), .RN(n3327), .Q(add_x_6_B_9_) );
DFFRX4TS add_x_6_R_44 ( .D(n562), .CK(clk), .RN(n3342), .Q(add_x_6_B_4_) );
DFFSX1TS R_439 ( .D(n3476), .CK(clk), .SN(n1249), .Q(n3006) );
DFFRX4TS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n837), .CK(clk), .RN(n2929), .Q(
final_result_ieee[27]), .QN(n1122) );
DFFSX1TS R_419 ( .D(n3441), .CK(clk), .SN(n2590), .Q(n3019) );
DFFSX1TS R_446 ( .D(n3607), .CK(clk), .SN(n3315), .Q(n2999) );
DFFRX4TS add_x_6_R_482 ( .D(sub_x_5_B_10_), .CK(clk), .RN(n2590), .Q(
add_x_6_B_10_) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n614), .CK(clk), .RN(n1238), .Q(
n1032) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n611), .CK(clk), .RN(n3325), .Q(
n1024) );
DFFSHQX8TS R_468 ( .D(n2992), .CK(clk), .SN(n1239), .Q(n1020) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n609), .CK(clk), .RN(n1239),
.Q(n1018) );
DFFSX2TS R_71 ( .D(n3560), .CK(clk), .SN(n3681), .Q(n3256) );
DFFSX2TS R_119 ( .D(n3553), .CK(clk), .SN(n2943), .Q(n3225) );
DFFSX2TS R_532 ( .D(n1039), .CK(clk), .SN(n1231), .Q(n1011) );
DFFRX2TS R_533 ( .D(n2734), .CK(clk), .RN(n3681), .Q(n1010) );
DFFSX2TS R_541 ( .D(n2841), .CK(clk), .SN(n2936), .Q(n1008) );
DFFSX4TS R_498 ( .D(n3308), .CK(clk), .SN(n1232), .Q(n2979) );
DFFRX2TS R_499 ( .D(n3550), .CK(clk), .RN(n3326), .Q(n2978) );
DFFRX4TS R_545 ( .D(n2281), .CK(clk), .RN(n3326), .Q(n1006) );
DFFSX2TS R_546 ( .D(n1368), .CK(clk), .SN(n1236), .Q(n1005) );
DFFRX4TS R_511 ( .D(n3570), .CK(clk), .RN(n2942), .Q(n2967) );
DFFSX4TS R_547 ( .D(n1545), .CK(clk), .SN(n2944), .Q(n1004) );
DFFSX2TS R_548 ( .D(n1710), .CK(clk), .SN(n1253), .Q(n1003) );
DFFSX2TS R_549 ( .D(n1012), .CK(clk), .SN(n1236), .Q(n1002) );
DFFSX2TS R_130 ( .D(n3580), .CK(clk), .SN(n2940), .QN(n1059) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n691), .CK(clk), .RN(n3323), .Q(
DMP_exp_NRM2_EW[7]), .QN(n2836) );
DFFRX4TS R_487 ( .D(n3564), .CK(clk), .RN(n2942), .Q(n2987) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n732), .CK(clk), .RN(n3331), .Q(
DMP_SHT2_EWSW[22]), .QN(n2793) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n704), .CK(clk), .RN(n3317), .Q(
DMP_SHT2_EWSW[28]), .QN(n2796) );
DFFRHQX2TS R_277 ( .D(n788), .CK(clk), .RN(n1239), .Q(n2740) );
DFFRHQX4TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n931), .CK(clk), .RN(n3338),
.Q(n1143) );
DFFRX4TS add_x_6_R_198 ( .D(n560), .CK(clk), .RN(n2954), .Q(add_x_6_B_6_) );
DFFRX4TS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n845), .CK(clk), .RN(n3325),
.Q(Shift_amount_SHT1_EWR[1]), .QN(n2824) );
DFFRX4TS R_523 ( .D(n3562), .CK(clk), .RN(n2946), .Q(n2958) );
DFFSX2TS R_61 ( .D(n3497), .CK(clk), .SN(n1239), .Q(n3266) );
DFFRHQX4TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n726), .CK(clk), .RN(n3323),
.Q(n1162) );
DFFRHQX4TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n602), .CK(clk), .RN(n2590),
.Q(n1214) );
DFFRHQX4TS R_107 ( .D(sub_x_5_B_3_), .CK(clk), .RN(n1237), .Q(n1123) );
DFFRHQX4TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n608), .CK(clk), .RN(n3332),
.Q(n1147) );
DFFRHQX4TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n599), .CK(clk), .RN(n3327),
.Q(n1110) );
DFFRHQX4TS R_437 ( .D(n606), .CK(clk), .RN(n1238), .Q(n1029) );
DFFRHQX4TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n613), .CK(clk), .RN(n2590), .Q(
n1208) );
DFFRHQX2TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n876), .CK(clk), .RN(n3327), .Q(
n1199) );
DFFSX2TS add_x_6_R_225_IP ( .D(n1633), .CK(clk), .SN(n1264), .Q(n2776) );
DFFRHQX4TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n922), .CK(clk), .RN(n3339),
.Q(n1157) );
DFFRHQX4TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n920), .CK(clk), .RN(n3339),
.Q(n1158) );
DFFRHQX4TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n923), .CK(clk), .RN(n3339),
.Q(n1150) );
DFFRHQX4TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n938), .CK(clk), .RN(n3337),
.Q(n1180) );
DFFRHQX4TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n926), .CK(clk), .RN(n3338),
.Q(n1198) );
DFFRHQX4TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n925), .CK(clk), .RN(n3338),
.Q(n1191) );
DFFRHQX4TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n928), .CK(clk), .RN(n3338),
.Q(n1151) );
DFFRHQX4TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n936), .CK(clk), .RN(n3337),
.Q(n1183) );
DFFRHQX4TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n921), .CK(clk), .RN(n3339),
.Q(n1184) );
DFFRHQX4TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n916), .CK(clk), .RN(n3339),
.Q(n1149) );
DFFRHQX4TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n929), .CK(clk), .RN(n3338),
.Q(n1154) );
DFFRHQX4TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n927), .CK(clk), .RN(n3338),
.Q(n1190) );
DFFRHQX4TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n917), .CK(clk), .RN(n3339),
.Q(n1155) );
DFFRHQX2TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n913), .CK(clk), .RN(n1264),
.Q(intDX_EWSW[30]) );
DFFRHQX4TS R_460 ( .D(n2994), .CK(clk), .RN(n2941), .Q(n1174) );
DFFSX1TS R_123 ( .D(n3481), .CK(clk), .SN(n1238), .Q(n3221) );
DFFRX1TS R_451 ( .D(n1347), .CK(clk), .RN(n2942), .Q(DmP_mant_SFG_SWR[1]),
.QN(n1045) );
DFFRHQX2TS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n663), .CK(clk), .RN(n1264),
.Q(DmP_mant_SHT1_SW[13]) );
DFFSX1TS add_x_6_R_255 ( .D(n2750), .CK(clk), .SN(n3333), .Q(add_x_6_n92),
.QN(n1068) );
DFFSX4TS R_540 ( .D(n3674), .CK(clk), .SN(n2931), .QN(n955) );
DFFSX1TS R_416 ( .D(n3384), .CK(clk), .SN(n2336), .Q(n3022) );
DFFSX2TS R_504 ( .D(n3312), .CK(clk), .SN(n2934), .Q(n2973) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n720), .CK(clk), .RN(n3681), .QN(
n2900) );
DFFSRHQX2TS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n622), .CK(clk), .SN(1'b1),
.RN(n1264), .Q(SIGN_FLAG_SHT1SHT2) );
OR2X6TS U958 ( .A(n2526), .B(n3589), .Y(n3531) );
NAND2X2TS U959 ( .A(n1228), .B(intDY_EWSW[18]), .Y(n3519) );
OR2X6TS U960 ( .A(n2526), .B(n3551), .Y(n3554) );
NAND2X2TS U961 ( .A(n2727), .B(intDX_EWSW[24]), .Y(n3432) );
INVX3TS U962 ( .A(sub_x_5_B_3_), .Y(n2780) );
NAND2X2TS U963 ( .A(n1228), .B(intDX_EWSW[28]), .Y(n3607) );
NAND3X2TS U964 ( .A(n1410), .B(n1405), .C(n973), .Y(n3667) );
NAND2X2TS U965 ( .A(n1225), .B(intDY_EWSW[16]), .Y(n3499) );
BUFX6TS U966 ( .A(n2306), .Y(n1381) );
OR2X6TS U967 ( .A(sub_x_5_B_2_), .B(n1094), .Y(n2787) );
CLKMX2X2TS U968 ( .A(n1122), .B(n966), .S0(Shift_reg_FLAGS_7[0]), .Y(n2376)
);
INVX2TS U969 ( .A(n3562), .Y(n3589) );
BUFX6TS U970 ( .A(n2737), .Y(n1410) );
INVX4TS U971 ( .A(n2678), .Y(n2639) );
INVX4TS U972 ( .A(n2678), .Y(n2621) );
NAND2XLTS U973 ( .A(n2569), .B(Raw_mant_NRM_SWR[1]), .Y(n1393) );
INVX2TS U974 ( .A(n2540), .Y(n2535) );
NAND2X2TS U975 ( .A(n1430), .B(n1429), .Y(n850) );
INVX4TS U976 ( .A(n2678), .Y(n2675) );
NAND2X4TS U977 ( .A(n552), .B(n761), .Y(n2747) );
NAND2X4TS U978 ( .A(n548), .B(n749), .Y(n2750) );
NAND2X1TS U979 ( .A(n1038), .B(n1706), .Y(n2404) );
NAND2XLTS U980 ( .A(n1762), .B(n2065), .Y(n1266) );
INVX2TS U981 ( .A(n1425), .Y(n1257) );
NAND2X1TS U982 ( .A(n2414), .B(n2413), .Y(n2418) );
INVX2TS U983 ( .A(n2547), .Y(n3590) );
NAND2X2TS U984 ( .A(n1301), .B(n1352), .Y(n1531) );
NAND2X2TS U985 ( .A(n973), .B(n1726), .Y(n2406) );
NAND2X6TS U986 ( .A(n991), .B(n1616), .Y(n990) );
INVX2TS U987 ( .A(n1243), .Y(n2491) );
NAND2X2TS U988 ( .A(n2321), .B(n1265), .Y(n1370) );
AOI22X2TS U989 ( .A0(n1541), .A1(n1265), .B0(n1129), .B1(n1391), .Y(n2217)
);
NAND2X1TS U990 ( .A(n2717), .B(n1135), .Y(n1397) );
INVX1TS U991 ( .A(n2610), .Y(n2514) );
INVX6TS U992 ( .A(n1537), .Y(n1013) );
NAND2XLTS U993 ( .A(n1391), .B(n1016), .Y(n1422) );
NAND2BX1TS U994 ( .AN(n2370), .B(DmP_mant_SFG_SWR[1]), .Y(n1395) );
INVX3TS U995 ( .A(n2545), .Y(n2529) );
CLKBUFX2TS U996 ( .A(n2678), .Y(n2362) );
INVX6TS U997 ( .A(n1256), .Y(n1014) );
XOR2X2TS U998 ( .A(n1785), .B(n1784), .Y(n1790) );
XOR2X2TS U999 ( .A(n1197), .B(n2198), .Y(n2207) );
BUFX6TS U1000 ( .A(n1513), .Y(n1425) );
NAND2X1TS U1001 ( .A(n2465), .B(DmP_mant_SHT1_SW[18]), .Y(n2456) );
NOR2X1TS U1002 ( .A(n2365), .B(inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n2366) );
NAND2X1TS U1003 ( .A(n1230), .B(DmP_mant_SFG_SWR[13]), .Y(n1426) );
NAND2X1TS U1004 ( .A(n2476), .B(n2475), .Y(n2478) );
INVX12TS U1005 ( .A(n1140), .Y(n2728) );
NAND2X1TS U1006 ( .A(n2408), .B(DmP_mant_SFG_SWR[10]), .Y(n2326) );
NAND2XLTS U1007 ( .A(n2089), .B(n2088), .Y(n2090) );
AOI21X2TS U1008 ( .A0(n2576), .A1(n2575), .B0(n2791), .Y(n2580) );
NOR2BX2TS U1009 ( .AN(Raw_mant_NRM_SWR[4]), .B(n1017), .Y(n1305) );
OAI2BB1X1TS U1010 ( .A0N(DmP_mant_SFG_SWR[16]), .A1N(n2421), .B0(n2420), .Y(
n2422) );
NAND2BX2TS U1011 ( .AN(n2309), .B(n1373), .Y(n2515) );
XNOR2X1TS U1012 ( .A(n1362), .B(n2582), .Y(n2584) );
INVX2TS U1013 ( .A(n2541), .Y(n2543) );
NOR2X2TS U1014 ( .A(n2305), .B(n2304), .Y(n2545) );
INVX2TS U1015 ( .A(n2792), .Y(n1094) );
NOR2X2TS U1016 ( .A(n2242), .B(n2241), .Y(n2540) );
NAND3X2TS U1017 ( .A(n2483), .B(n2482), .C(n2481), .Y(n2537) );
NOR2X2TS U1018 ( .A(n2494), .B(n2493), .Y(n2610) );
CLKINVX2TS U1019 ( .A(n2539), .Y(n2530) );
CLKINVX2TS U1020 ( .A(n2546), .Y(n2534) );
NOR2X2TS U1021 ( .A(n1952), .B(n1951), .Y(n1975) );
OR2X2TS U1022 ( .A(n2389), .B(n1623), .Y(n1079) );
XOR2X2TS U1023 ( .A(n2397), .B(n2093), .Y(n2094) );
INVX4TS U1024 ( .A(n565), .Y(n1095) );
NAND3X2TS U1025 ( .A(n2468), .B(n2467), .C(n2466), .Y(n2548) );
NOR2X4TS U1026 ( .A(n984), .B(n983), .Y(n1197) );
NAND2X1TS U1027 ( .A(n1345), .B(Raw_mant_NRM_SWR[2]), .Y(n2439) );
OR2X2TS U1028 ( .A(n1424), .B(n1217), .Y(n1621) );
NOR2X2TS U1029 ( .A(n2250), .B(n2197), .Y(n984) );
NAND2X1TS U1030 ( .A(n2498), .B(DmP_mant_SHT1_SW[4]), .Y(n2471) );
AND2X6TS U1031 ( .A(n1736), .B(n1735), .Y(n1737) );
NAND2X1TS U1032 ( .A(n2724), .B(n1110), .Y(n2482) );
AOI21X2TS U1033 ( .A0(n1362), .A1(n2007), .B0(n2009), .Y(n1787) );
NAND2X1TS U1034 ( .A(n2476), .B(Raw_mant_NRM_SWR[4]), .Y(n2483) );
AOI21X2TS U1035 ( .A0(n999), .A1(n1073), .B0(n1189), .Y(n1379) );
OAI2BB1X2TS U1036 ( .A0N(DmP_mant_SFG_SWR[17]), .A1N(n2663), .B0(n2420), .Y(
n2335) );
CLKAND2X2TS U1037 ( .A(n2476), .B(n1018), .Y(n2308) );
CLKAND2X2TS U1038 ( .A(n2476), .B(n1024), .Y(n2301) );
NAND2X1TS U1039 ( .A(n2385), .B(n3312), .Y(n2386) );
OAI2BB1X2TS U1040 ( .A0N(DmP_mant_SFG_SWR[20]), .A1N(n2421), .B0(n2420), .Y(
n2084) );
BUFX3TS U1041 ( .A(n1391), .Y(n2717) );
BUFX3TS U1042 ( .A(n1994), .Y(n2295) );
NAND2X4TS U1043 ( .A(n2588), .B(n2413), .Y(n2003) );
NOR2X1TS U1044 ( .A(n1388), .B(n1209), .Y(n2508) );
NAND2X2TS U1045 ( .A(n2573), .B(n2330), .Y(n1728) );
NAND2X4TS U1046 ( .A(n1520), .B(n2413), .Y(n1322) );
NAND2X1TS U1047 ( .A(n2186), .B(n2315), .Y(n2190) );
BUFX6TS U1048 ( .A(n2595), .Y(n1342) );
AOI21X2TS U1049 ( .A0(n1706), .A1(n2734), .B0(n1709), .Y(n1319) );
NOR2X2TS U1050 ( .A(n980), .B(n1033), .Y(n2271) );
NOR2X4TS U1051 ( .A(n2139), .B(n2603), .Y(n2141) );
NAND2X2TS U1052 ( .A(n1313), .B(n2484), .Y(n1913) );
NAND3X2TS U1053 ( .A(n2487), .B(n2486), .C(n2485), .Y(n2541) );
NOR2X2TS U1054 ( .A(n1338), .B(n1337), .Y(n2061) );
NAND3X2TS U1055 ( .A(n2453), .B(n2452), .C(n2451), .Y(n2539) );
NAND3X2TS U1056 ( .A(n2501), .B(n2500), .C(n2499), .Y(n2546) );
NAND2X2TS U1057 ( .A(n1314), .B(n2437), .Y(n1912) );
INVX6TS U1058 ( .A(n2370), .Y(n1265) );
MXI2X2TS U1059 ( .A(n2820), .B(n2889), .S0(n2665), .Y(n2792) );
NOR2X1TS U1060 ( .A(n1262), .B(n1221), .Y(n2444) );
AND2X2TS U1061 ( .A(n1104), .B(n2138), .Y(n1078) );
NOR2X1TS U1062 ( .A(n1262), .B(n1130), .Y(n2304) );
NAND2X1TS U1063 ( .A(n1568), .B(n2290), .Y(n2292) );
AOI21X2TS U1064 ( .A0(n2181), .A1(n2163), .B0(n2162), .Y(n2164) );
INVX2TS U1065 ( .A(n2121), .Y(n2123) );
NAND2X1TS U1066 ( .A(n2476), .B(n1218), .Y(n2278) );
OAI2BB1X1TS U1067 ( .A0N(DmP_mant_SFG_SWR[5]), .A1N(n2421), .B0(n2331), .Y(
n2332) );
NAND2X1TS U1068 ( .A(n2476), .B(n1110), .Y(n2461) );
NAND2X1TS U1069 ( .A(n2476), .B(n1152), .Y(n2240) );
NAND3X1TS U1070 ( .A(n1419), .B(n2227), .C(n1219), .Y(n2230) );
INVX2TS U1071 ( .A(n2185), .Y(n2315) );
CLKINVX6TS U1072 ( .A(n2718), .Y(n2370) );
INVX1TS U1073 ( .A(n1061), .Y(n2148) );
CLKINVX2TS U1074 ( .A(n1208), .Y(n1209) );
AOI21X2TS U1075 ( .A0(n983), .A1(n2174), .B0(n1377), .Y(n1303) );
AO22X2TS U1076 ( .A0(n2063), .A1(n2469), .B0(n1649), .B1(n2459), .Y(n1188)
);
NAND2XLTS U1077 ( .A(n2199), .B(n2202), .Y(n2204) );
INVX12TS U1078 ( .A(n1027), .Y(n1706) );
AOI21X2TS U1079 ( .A0(n2181), .A1(n2258), .B0(n2772), .Y(n2182) );
AND2X2TS U1080 ( .A(n2391), .B(n2390), .Y(n1076) );
INVX3TS U1081 ( .A(n1497), .Y(n1260) );
OAI2BB1X2TS U1082 ( .A0N(n1175), .A1N(n1655), .B0(n2420), .Y(n1909) );
INVX6TS U1083 ( .A(n999), .Y(n2397) );
NAND2X1TS U1084 ( .A(n2465), .B(DmP_mant_SHT1_SW[6]), .Y(n2434) );
NAND2X1TS U1085 ( .A(n2465), .B(DmP_mant_SHT1_SW[15]), .Y(n2442) );
NAND2X1TS U1086 ( .A(n2498), .B(DmP_mant_SHT1_SW[13]), .Y(n2302) );
OR2X2TS U1087 ( .A(n1424), .B(n1019), .Y(n2501) );
NAND2X4TS U1088 ( .A(n1145), .B(n1568), .Y(n1564) );
NAND2X2TS U1089 ( .A(n2136), .B(n1498), .Y(n1386) );
NAND2X2TS U1090 ( .A(Raw_mant_NRM_SWR[5]), .B(n2124), .Y(n1160) );
AOI21X2TS U1091 ( .A0(n1607), .A1(n1606), .B0(n1049), .Y(n1586) );
AOI2BB2X2TS U1092 ( .B0(n2391), .B1(n2392), .A0N(n2393), .A1N(n2394), .Y(
n1383) );
NAND3X2TS U1093 ( .A(n2265), .B(n2266), .C(n2264), .Y(n2270) );
INVX12TS U1094 ( .A(n1521), .Y(n1520) );
AOI22X1TS U1095 ( .A0(n2064), .A1(n2490), .B0(n1624), .B1(n2512), .Y(n1651)
);
NAND2X2TS U1096 ( .A(n2243), .B(n2174), .Y(n1304) );
INVX2TS U1097 ( .A(n2139), .Y(n2606) );
OAI21X1TS U1098 ( .A0(n1186), .A1(add_x_6_n77), .B0(n2318), .Y(n1189) );
OAI21X2TS U1099 ( .A0(n1364), .A1(n2822), .B0(n1401), .Y(n1338) );
OR2X2TS U1100 ( .A(n1424), .B(n1167), .Y(n2453) );
NAND2X2TS U1101 ( .A(n1624), .B(n2502), .Y(n1666) );
AND2X6TS U1102 ( .A(n1041), .B(n1898), .Y(n2410) );
NAND2X1TS U1103 ( .A(n1243), .B(shift_value_SHT2_EWR[3]), .Y(n1401) );
INVX6TS U1104 ( .A(n2634), .Y(n2465) );
NAND2X6TS U1105 ( .A(n1462), .B(n1566), .Y(n999) );
INVX12TS U1106 ( .A(n1986), .Y(n2250) );
NAND2X4TS U1107 ( .A(n2059), .B(n1080), .Y(n2058) );
INVX2TS U1108 ( .A(n2191), .Y(n2290) );
INVX6TS U1109 ( .A(n1497), .Y(n2330) );
NAND2X4TS U1110 ( .A(n2131), .B(n982), .Y(n2139) );
CLKINVX2TS U1111 ( .A(n2077), .Y(n1606) );
NAND2X4TS U1112 ( .A(n2115), .B(n1387), .Y(n2056) );
NOR2X6TS U1113 ( .A(n969), .B(n1503), .Y(n1502) );
NAND2X2TS U1114 ( .A(n1624), .B(n2454), .Y(n1182) );
XNOR2X2TS U1115 ( .A(intDY_EWSW[1]), .B(n1205), .Y(n1935) );
CLKXOR2X2TS U1116 ( .A(intDY_EWSW[8]), .B(n1120), .Y(n1967) );
NOR2X4TS U1117 ( .A(n2121), .B(n2117), .Y(n1309) );
NAND2X2TS U1118 ( .A(n1916), .B(n1200), .Y(n1645) );
CLKINVX6TS U1119 ( .A(n2197), .Y(n2243) );
NAND2XLTS U1120 ( .A(n1174), .B(n1199), .Y(n1918) );
OR2X4TS U1121 ( .A(n2394), .B(n1699), .Y(n1485) );
NAND2X4TS U1122 ( .A(n976), .B(n1031), .Y(n2121) );
CLKAND2X2TS U1123 ( .A(n2118), .B(Raw_mant_NRM_SWR[1]), .Y(n1387) );
CLKAND2X4TS U1124 ( .A(n1563), .B(n1030), .Y(n2059) );
NOR2X4TS U1125 ( .A(n2051), .B(n2043), .Y(n2298) );
NAND2X2TS U1126 ( .A(n2063), .B(n2459), .Y(n2067) );
NOR2X6TS U1127 ( .A(n1384), .B(n1261), .Y(n2385) );
INVX3TS U1128 ( .A(n2353), .Y(n2036) );
INVX3TS U1129 ( .A(n1563), .Y(n2051) );
AND2X6TS U1130 ( .A(n1442), .B(n1441), .Y(n1440) );
BUFX8TS U1131 ( .A(n2446), .Y(n1134) );
INVX4TS U1132 ( .A(n2288), .Y(n1568) );
INVX4TS U1133 ( .A(n2331), .Y(n1932) );
CLKINVX6TS U1134 ( .A(n1384), .Y(n1498) );
INVX8TS U1135 ( .A(n2256), .Y(n2180) );
INVX4TS U1136 ( .A(n1664), .Y(n1508) );
BUFX6TS U1137 ( .A(n2255), .Y(n1300) );
INVX3TS U1138 ( .A(n2174), .Y(n1987) );
CLKINVX2TS U1139 ( .A(n1032), .Y(n1033) );
INVX12TS U1140 ( .A(n1458), .Y(n1261) );
NAND2X4TS U1141 ( .A(n1553), .B(n1057), .Y(n1443) );
BUFX8TS U1142 ( .A(n2064), .Y(n1314) );
NAND2X2TS U1143 ( .A(n1174), .B(n2480), .Y(n1907) );
NAND4X2TS U1144 ( .A(n3208), .B(n3207), .C(n3206), .D(n3205), .Y(n2426) );
NAND2X2TS U1145 ( .A(n1065), .B(n1563), .Y(n1493) );
AND2X4TS U1146 ( .A(n1444), .B(n1901), .Y(n1051) );
NAND2X2TS U1147 ( .A(n1916), .B(n1703), .Y(n1704) );
NAND3X4TS U1148 ( .A(n1730), .B(n3179), .C(n3178), .Y(n2495) );
NAND4X4TS U1149 ( .A(n967), .B(n1595), .C(n976), .D(n1594), .Y(n1494) );
INVX2TS U1150 ( .A(n2480), .Y(n1703) );
OR2X6TS U1151 ( .A(n1916), .B(bit_shift_SHT2), .Y(n1041) );
INVX6TS U1152 ( .A(n1573), .Y(n2265) );
AND2X4TS U1153 ( .A(n1366), .B(n1758), .Y(n1057) );
NAND3X4TS U1154 ( .A(n3204), .B(n1705), .C(n3203), .Y(n2474) );
BUFX6TS U1155 ( .A(left_right_SHT2), .Y(n1384) );
NAND2X6TS U1156 ( .A(n1454), .B(n1063), .Y(n2503) );
NAND3X6TS U1157 ( .A(n1654), .B(n3214), .C(n3213), .Y(n2469) );
NOR2X6TS U1158 ( .A(n1310), .B(n1721), .Y(n1571) );
AOI21X1TS U1159 ( .A0(n2043), .A1(n3549), .B0(n1777), .Y(n1065) );
NOR2X6TS U1160 ( .A(n2103), .B(n2099), .Y(n1679) );
INVX2TS U1161 ( .A(n2437), .Y(n1460) );
NAND2X2TS U1162 ( .A(n1758), .B(n2498), .Y(n1441) );
NAND4X6TS U1163 ( .A(n1480), .B(n1613), .C(n1722), .D(n1721), .Y(n1097) );
AOI21X2TS U1164 ( .A0(n2268), .A1(n2424), .B0(n1777), .Y(n1596) );
AND2X4TS U1165 ( .A(n2266), .B(n1496), .Y(n970) );
NAND2X4TS U1166 ( .A(n1744), .B(n1419), .Y(n2228) );
INVX2TS U1167 ( .A(n1750), .Y(n1744) );
NAND2X4TS U1168 ( .A(n1258), .B(n2446), .Y(n1900) );
INVX4TS U1169 ( .A(n1400), .Y(n1613) );
NAND2X4TS U1170 ( .A(DMP_SFG[14]), .B(DmP_mant_SFG_SWR[16]), .Y(n2160) );
INVX2TS U1171 ( .A(n1777), .Y(n1343) );
AO21X2TS U1172 ( .A0(n2223), .A1(n1153), .B0(n1029), .Y(n1054) );
INVX2TS U1173 ( .A(n1766), .Y(n1761) );
NAND2X4TS U1174 ( .A(n1745), .B(n2497), .Y(n1758) );
NOR2X4TS U1175 ( .A(n2113), .B(add_x_6_n88), .Y(n2317) );
NOR2X6TS U1176 ( .A(sub_x_5_n237), .B(DMP_SFG[15]), .Y(n2154) );
NAND2X2TS U1177 ( .A(n1626), .B(DMP_SFG[18]), .Y(n2104) );
NAND2X6TS U1178 ( .A(n1174), .B(n2464), .Y(n1899) );
CLKAND2X2TS U1179 ( .A(n2865), .B(intDX_EWSW[30]), .Y(n1886) );
NOR2X6TS U1180 ( .A(n1093), .B(n1831), .Y(n1817) );
NAND2X4TS U1181 ( .A(n1576), .B(n1575), .Y(n1573) );
NOR2X6TS U1182 ( .A(n1615), .B(n1774), .Y(n2266) );
NAND2X2TS U1183 ( .A(n2424), .B(n2229), .Y(n1741) );
INVX4TS U1184 ( .A(n1678), .Y(n1287) );
CLKAND2X2TS U1185 ( .A(n2264), .B(n2634), .Y(n1496) );
NOR2X6TS U1186 ( .A(n2138), .B(n2832), .Y(n2383) );
OR2X4TS U1187 ( .A(n2865), .B(intDX_EWSW[30]), .Y(n1887) );
CLKINVX6TS U1188 ( .A(n1663), .Y(n1901) );
INVX6TS U1189 ( .A(n2634), .Y(n2498) );
NOR3X4TS U1190 ( .A(n1760), .B(n2497), .C(n2118), .Y(n1552) );
AND2X4TS U1191 ( .A(n2007), .B(n1691), .Y(n1058) );
NAND2X4TS U1192 ( .A(n1176), .B(DMP_SFG[16]), .Y(n2088) );
BUFX8TS U1193 ( .A(n2226), .Y(n1419) );
NOR2X4TS U1194 ( .A(add_x_6_A_14_), .B(add_x_6_B_14_), .Y(n2179) );
NOR2X4TS U1195 ( .A(n2843), .B(intDX_EWSW[24]), .Y(n986) );
NAND2X4TS U1196 ( .A(n1637), .B(DMP_SFG[17]), .Y(n2110) );
INVX2TS U1197 ( .A(n1199), .Y(n1200) );
NOR2X6TS U1198 ( .A(n2850), .B(n1149), .Y(n1879) );
NAND2X1TS U1199 ( .A(n1629), .B(DMP_SFG[14]), .Y(n1674) );
NAND2X2TS U1200 ( .A(n2844), .B(n1184), .Y(n1868) );
NOR2X6TS U1201 ( .A(n972), .B(n3530), .Y(n1663) );
NOR2BX2TS U1202 ( .AN(n1136), .B(n1202), .Y(n1770) );
CLKINVX3TS U1203 ( .A(n1175), .Y(n1176) );
BUFX8TS U1204 ( .A(n1916), .Y(n1258) );
INVX2TS U1205 ( .A(n1275), .Y(n1280) );
NOR2X2TS U1206 ( .A(n1215), .B(n1202), .Y(n1756) );
NAND2X2TS U1207 ( .A(n2868), .B(intDX_EWSW[13]), .Y(n1088) );
NAND2X2TS U1208 ( .A(n2849), .B(intDX_EWSW[9]), .Y(n1822) );
INVX3TS U1209 ( .A(n1774), .Y(n1577) );
NOR2X4TS U1210 ( .A(n2352), .B(Shift_amount_SHT1_EWR[0]), .Y(n1777) );
NAND2X4TS U1211 ( .A(n1139), .B(n1611), .Y(n1277) );
BUFX12TS U1212 ( .A(n1299), .Y(n961) );
NAND2X6TS U1213 ( .A(n2558), .B(n1294), .Y(n1291) );
OR2X4TS U1214 ( .A(Raw_mant_NRM_SWR[4]), .B(n1208), .Y(n1585) );
NOR2X6TS U1215 ( .A(n2475), .B(n1016), .Y(n1773) );
NAND2X2TS U1216 ( .A(n1210), .B(n1111), .Y(n1581) );
NAND2X2TS U1217 ( .A(n1527), .B(n1716), .Y(n1144) );
NOR2X4TS U1218 ( .A(n1332), .B(n1331), .Y(n1330) );
NOR2X4TS U1219 ( .A(add_x_6_n172), .B(add_x_6_n167), .Y(n1691) );
NOR2X4TS U1220 ( .A(n2864), .B(n1155), .Y(n987) );
NOR2X4TS U1221 ( .A(add_x_6_n145), .B(add_x_6_n138), .Y(n1692) );
INVX2TS U1222 ( .A(n1298), .Y(n1715) );
INVX4TS U1223 ( .A(n1767), .Y(n2122) );
OR2X6TS U1224 ( .A(n1087), .B(DMP_exp_NRM2_EW[2]), .Y(n1044) );
OR2X4TS U1225 ( .A(n1016), .B(n1110), .Y(n1754) );
NOR2X6TS U1226 ( .A(add_x_6_A_6_), .B(add_x_6_B_6_), .Y(n2565) );
INVX4TS U1227 ( .A(n1018), .Y(n1019) );
NOR2X6TS U1228 ( .A(n1210), .B(n1218), .Y(n1775) );
NAND2X4TS U1229 ( .A(n2604), .B(n2127), .Y(n2140) );
NAND2X4TS U1230 ( .A(n2608), .B(n1086), .Y(n1275) );
NOR2X2TS U1231 ( .A(n1020), .B(n1216), .Y(n1772) );
INVX6TS U1232 ( .A(n1172), .Y(n2577) );
NOR2X4TS U1233 ( .A(n1024), .B(n1220), .Y(n1767) );
NOR2X4TS U1234 ( .A(n1629), .B(DMP_SFG[14]), .Y(n1675) );
INVX4TS U1235 ( .A(n1020), .Y(n1021) );
CLKINVX6TS U1236 ( .A(n1619), .Y(n2608) );
INVX8TS U1237 ( .A(n1716), .Y(n1572) );
NOR2X2TS U1238 ( .A(n1018), .B(n1029), .Y(n1752) );
INVX4TS U1239 ( .A(n1129), .Y(n1130) );
INVX2TS U1240 ( .A(n1218), .Y(n1219) );
NOR2X6TS U1241 ( .A(sub_x_5_n249), .B(sub_x_5_A_5_), .Y(n2549) );
NOR2X4TS U1242 ( .A(sub_x_5_n245), .B(DMP_SFG[7]), .Y(n2209) );
NOR2X4TS U1243 ( .A(n1162), .B(n1171), .Y(n1713) );
NOR2X2TS U1244 ( .A(n1717), .B(DMP_exp_NRM2_EW[4]), .Y(n1279) );
INVX6TS U1245 ( .A(n1518), .Y(n1086) );
CLKINVX6TS U1246 ( .A(sub_x_5_A_11_), .Y(n1121) );
CLKINVX6TS U1247 ( .A(DMP_SFG[6]), .Y(n1125) );
INVX12TS U1248 ( .A(n2251), .Y(n1290) );
INVX3TS U1249 ( .A(DMP_SFG[4]), .Y(n1173) );
NAND2X4TS U1250 ( .A(sub_x_5_n251), .B(sub_x_5_A_3_), .Y(n2710) );
AND2X4TS U1251 ( .A(n1164), .B(LZD_output_NRM2_EW[1]), .Y(n1408) );
NAND2X8TS U1252 ( .A(n1557), .B(n1081), .Y(n3619) );
INVX12TS U1253 ( .A(n1491), .Y(n1614) );
OAI21X4TS U1254 ( .A0(n2022), .A1(n2147), .B0(n2023), .Y(n1672) );
INVX8TS U1255 ( .A(n1587), .Y(n989) );
BUFX12TS U1256 ( .A(n1990), .Y(n1420) );
AOI21X2TS U1257 ( .A0(n1123), .A1(n2408), .B0(n1932), .Y(n1736) );
AOI21X2TS U1258 ( .A0(n2410), .A1(n1706), .B0(n2409), .Y(n2411) );
OAI2BB1X1TS U1259 ( .A0N(DmP_mant_SFG_SWR[24]), .A1N(n2408), .B0(n2420), .Y(
n2409) );
NAND2X4TS U1260 ( .A(n2573), .B(n2413), .Y(n1669) );
NAND2X4TS U1261 ( .A(n2738), .B(n2330), .Y(n1670) );
NAND2X4TS U1262 ( .A(n2734), .B(n1261), .Y(n1734) );
NAND3X8TS U1263 ( .A(n1926), .B(n1924), .C(n1925), .Y(n2407) );
NAND2X4TS U1264 ( .A(n1313), .B(n2495), .Y(n1732) );
CLKINVX6TS U1265 ( .A(sub_x_5_B_5_), .Y(n2778) );
BUFX20TS U1266 ( .A(n3310), .Y(n1537) );
NAND2X4TS U1267 ( .A(n2407), .B(n2330), .Y(n1930) );
NAND2X4TS U1268 ( .A(n2345), .B(n2344), .Y(n2347) );
INVX4TS U1269 ( .A(n2343), .Y(n2344) );
BUFX20TS U1270 ( .A(n2408), .Y(n1230) );
INVX16TS U1271 ( .A(n1037), .Y(n2408) );
NAND2X4TS U1272 ( .A(n1271), .B(n2450), .Y(n1505) );
NAND2X4TS U1273 ( .A(n1508), .B(n2450), .Y(n1996) );
XNOR2X4TS U1274 ( .A(n2554), .B(n2553), .Y(n2555) );
OAI21X4TS U1275 ( .A0(n2716), .A1(add_x_6_n197), .B0(n2714), .Y(n2554) );
NAND2X8TS U1276 ( .A(n2086), .B(n2085), .Y(n546) );
NAND2X6TS U1277 ( .A(n2736), .B(n1726), .Y(n2086) );
XOR2X4TS U1278 ( .A(n2609), .B(n2608), .Y(n3676) );
INVX4TS U1279 ( .A(n1617), .Y(n3674) );
NAND2X8TS U1280 ( .A(n1499), .B(n1064), .Y(n2450) );
OR2X8TS U1281 ( .A(n2985), .B(n2986), .Y(n1064) );
AOI22X2TS U1282 ( .A0(n1265), .A1(n2584), .B0(n2717), .B1(n1032), .Y(n2585)
);
NAND2X8TS U1283 ( .A(n1322), .B(n1321), .Y(n548) );
NAND2X2TS U1284 ( .A(n1405), .B(n1516), .Y(n3643) );
NAND3X6TS U1285 ( .A(n1670), .B(n1669), .C(n1668), .Y(n555) );
OAI2BB1X2TS U1286 ( .A0N(DmP_mant_SFG_SWR[25]), .A1N(n2421), .B0(n2420), .Y(
n2415) );
OAI2BB1X4TS U1287 ( .A0N(DmP_mant_SFG_SWR[21]), .A1N(n2421), .B0(n2420), .Y(
n1919) );
INVX4TS U1288 ( .A(n2420), .Y(n2403) );
AOI22X2TS U1289 ( .A0(n1635), .A1(n1265), .B0(n2717), .B1(
Raw_mant_NRM_SWR[2]), .Y(n2698) );
AOI21X2TS U1290 ( .A0(n2576), .A1(n1781), .B0(n1780), .Y(n1785) );
NAND3X6TS U1291 ( .A(n2328), .B(n2327), .C(n2326), .Y(sub_x_5_B_10_) );
INVX6TS U1292 ( .A(n849), .Y(n1428) );
NAND2X8TS U1293 ( .A(n2062), .B(n2061), .Y(n849) );
NAND2X8TS U1294 ( .A(n1339), .B(n1090), .Y(n2600) );
NOR2X8TS U1295 ( .A(n1188), .B(n1060), .Y(n1090) );
NAND3X8TS U1296 ( .A(n1653), .B(n3210), .C(n3209), .Y(n2459) );
NOR2X8TS U1297 ( .A(n2645), .B(n2036), .Y(n2343) );
NAND2X4TS U1298 ( .A(n1368), .B(n2515), .Y(n3552) );
NAND2X2TS U1299 ( .A(n1228), .B(intDY_EWSW[2]), .Y(n3452) );
NAND2X2TS U1300 ( .A(n1225), .B(intDY_EWSW[26]), .Y(n3425) );
INVX8TS U1301 ( .A(n1142), .Y(n2576) );
INVX6TS U1302 ( .A(n2490), .Y(n1509) );
AOI22X2TS U1303 ( .A0(n1014), .A1(n3556), .B0(n3308), .B1(n2542), .Y(n3585)
);
NAND3X6TS U1304 ( .A(n2222), .B(n2221), .C(n2220), .Y(n847) );
NAND4X2TS U1305 ( .A(n1966), .B(n1965), .C(n1964), .D(n1963), .Y(n1972) );
NAND2X4TS U1306 ( .A(n1169), .B(intDY_EWSW[11]), .Y(n3381) );
NAND2X4TS U1307 ( .A(n1169), .B(intDY_EWSW[24]), .Y(n3429) );
NAND2X4TS U1308 ( .A(n1169), .B(intDY_EWSW[15]), .Y(n3369) );
NAND2X4TS U1309 ( .A(n1169), .B(intDY_EWSW[5]), .Y(n3399) );
NAND2X4TS U1310 ( .A(n1169), .B(n1205), .Y(n3479) );
NAND2X4TS U1311 ( .A(n1169), .B(intDY_EWSW[28]), .Y(n3608) );
NAND2X2TS U1312 ( .A(n1225), .B(intDY_EWSW[1]), .Y(n3478) );
NAND2X4TS U1313 ( .A(n2726), .B(intDY_EWSW[1]), .Y(n3411) );
MX2X4TS U1314 ( .A(Data_Y[1]), .B(intDY_EWSW[1]), .S0(n1115), .Y(n909) );
NAND2X6TS U1315 ( .A(n1098), .B(n2262), .Y(n606) );
MXI2X4TS U1316 ( .A(n2802), .B(n2887), .S0(n2664), .Y(n770) );
NAND2X2TS U1317 ( .A(n1649), .B(n2065), .Y(n2066) );
BUFX20TS U1318 ( .A(n1649), .Y(n2080) );
NAND2X8TS U1319 ( .A(n1051), .B(n1461), .Y(n2735) );
AOI21X2TS U1320 ( .A0(n2333), .A1(n2734), .B0(n1984), .Y(n1985) );
BUFX16TS U1321 ( .A(n2247), .Y(n983) );
NAND2X8TS U1322 ( .A(n1427), .B(n1426), .Y(n553) );
NAND2X6TS U1323 ( .A(n2419), .B(n1028), .Y(n1427) );
NAND2X4TS U1324 ( .A(n1381), .B(n2281), .Y(n3566) );
NOR2X6TS U1325 ( .A(n2120), .B(n1282), .Y(n1308) );
OR2X8TS U1326 ( .A(n1256), .B(n2610), .Y(n3482) );
NAND2X2TS U1327 ( .A(n1624), .B(n2432), .Y(n2081) );
AOI22X2TS U1328 ( .A0(n2064), .A1(n2489), .B0(n1624), .B1(n2510), .Y(n1723)
);
OAI2BB1X4TS U1329 ( .A0N(n2323), .A1N(n2034), .B0(n2033), .Y(n608) );
NAND3X8TS U1330 ( .A(n2125), .B(n1307), .C(n1306), .Y(n2218) );
AOI2BB2X4TS U1331 ( .B0(n870), .B1(n1271), .A0N(n1510), .A1N(n1664), .Y(
n1724) );
AOI2BB2X4TS U1332 ( .B0(n1271), .B1(n2503), .A0N(n1664), .A1N(n1511), .Y(
n1733) );
INVX16TS U1333 ( .A(n1664), .Y(n2063) );
NAND2X6TS U1334 ( .A(n2599), .B(n2413), .Y(n1320) );
NAND2X8TS U1335 ( .A(n1317), .B(n2082), .Y(n2736) );
BUFX16TS U1336 ( .A(n1515), .Y(n1411) );
NAND2X4TS U1337 ( .A(n1034), .B(n2423), .Y(n550) );
NAND2X8TS U1338 ( .A(n1033), .B(n2124), .Y(n1017) );
INVX8TS U1339 ( .A(n2124), .Y(n980) );
NAND2X8TS U1340 ( .A(n1658), .B(n1657), .Y(n557) );
OR2X6TS U1341 ( .A(n2526), .B(n3593), .Y(n3535) );
OR2X6TS U1342 ( .A(n2526), .B(n2528), .Y(n3591) );
INVX16TS U1343 ( .A(n2728), .Y(n962) );
INVX16TS U1344 ( .A(n2728), .Y(n963) );
NAND3X2TS U1345 ( .A(n2406), .B(n2405), .C(n2404), .Y(n544) );
OR2X6TS U1346 ( .A(n2595), .B(n1458), .Y(n1926) );
NOR4X4TS U1347 ( .A(n1942), .B(n1941), .C(n1940), .D(n1939), .Y(n1976) );
NAND3X2TS U1348 ( .A(n1410), .B(n1405), .C(n2599), .Y(n3658) );
NOR2X8TS U1349 ( .A(add_x_6_A_10_), .B(add_x_6_B_10_), .Y(n2214) );
NAND4X6TS U1350 ( .A(n1666), .B(n1667), .C(n2000), .D(n1665), .Y(n2573) );
NAND3X4TS U1351 ( .A(n1453), .B(n2000), .C(n1449), .Y(n1448) );
NAND2X4TS U1352 ( .A(n2400), .B(n2330), .Y(n1500) );
NAND2X2TS U1353 ( .A(n2135), .B(n2730), .Y(n835) );
NAND3X4TS U1354 ( .A(n1514), .B(n2737), .C(n2400), .Y(n3670) );
NAND3X6TS U1355 ( .A(n2449), .B(n2448), .C(n2447), .Y(n3562) );
BUFX20TS U1356 ( .A(n1366), .Y(n1031) );
NAND3X4TS U1357 ( .A(n1423), .B(n1421), .C(n1422), .Y(n596) );
XNOR2X4TS U1358 ( .A(n2091), .B(n2090), .Y(n2096) );
NAND2X2TS U1359 ( .A(n1038), .B(n1039), .Y(n3668) );
NAND3X4TS U1360 ( .A(n1402), .B(n1403), .C(n1404), .Y(n597) );
NOR2X8TS U1361 ( .A(n1096), .B(n2173), .Y(n1618) );
AND4X8TS U1362 ( .A(n1443), .B(n1440), .C(n1439), .D(n1438), .Y(n1131) );
NAND2X4TS U1363 ( .A(n1587), .B(n1616), .Y(n3641) );
NAND2X4TS U1364 ( .A(n2263), .B(n2722), .Y(n1098) );
NAND2X4TS U1365 ( .A(n1169), .B(intDY_EWSW[8]), .Y(n3390) );
NAND2X4TS U1366 ( .A(n1169), .B(intDY_EWSW[7]), .Y(n3393) );
OAI21X4TS U1367 ( .A0(n2257), .A1(n2256), .B0(n1300), .Y(n2260) );
XNOR2X2TS U1368 ( .A(n2695), .B(n2688), .Y(n2349) );
NAND3X4TS U1369 ( .A(n3019), .B(n3018), .C(n3017), .Y(n2695) );
NAND2X8TS U1370 ( .A(n2492), .B(n1217), .Y(n1222) );
NAND2X4TS U1371 ( .A(n1345), .B(n1016), .Y(n2523) );
MX2X2TS U1372 ( .A(n1406), .B(n2427), .S0(n1373), .Y(n592) );
NAND2X4TS U1373 ( .A(n1228), .B(intDY_EWSW[17]), .Y(n3508) );
NAND2X4TS U1374 ( .A(n1228), .B(intDY_EWSW[10]), .Y(n3466) );
NAND2X4TS U1375 ( .A(n1228), .B(intDY_EWSW[21]), .Y(n3522) );
NAND2X4TS U1376 ( .A(n1228), .B(n1195), .Y(n3604) );
NAND2X2TS U1377 ( .A(n1228), .B(intDY_EWSW[8]), .Y(n3484) );
INVX16TS U1378 ( .A(n1222), .Y(n2226) );
NAND2X8TS U1379 ( .A(n1738), .B(n1737), .Y(sub_x_5_B_3_) );
NAND2X8TS U1380 ( .A(n1374), .B(n1435), .Y(n604) );
NAND2X4TS U1381 ( .A(n1226), .B(intDY_EWSW[0]), .Y(n3475) );
NAND2X4TS U1382 ( .A(n1226), .B(n1205), .Y(n3410) );
NAND2X4TS U1383 ( .A(n1226), .B(n1198), .Y(n3362) );
NAND2X4TS U1384 ( .A(n1226), .B(n1150), .Y(n3353) );
NAND2X2TS U1385 ( .A(n1226), .B(intDY_EWSW[13]), .Y(n3469) );
NAND2X2TS U1386 ( .A(n1226), .B(n959), .Y(n3407) );
NAND2X4TS U1387 ( .A(n1229), .B(intDY_EWSW[23]), .Y(n3434) );
NAND2X4TS U1388 ( .A(n1229), .B(intDY_EWSW[6]), .Y(n3490) );
NAND2X4TS U1389 ( .A(n1229), .B(intDY_EWSW[7]), .Y(n3487) );
NAND2X4TS U1390 ( .A(n1229), .B(intDY_EWSW[25]), .Y(n3443) );
NAND2X4TS U1391 ( .A(n2729), .B(n1151), .Y(n3503) );
NAND2X4TS U1392 ( .A(n2729), .B(intDY_EWSW[26]), .Y(n3423) );
NAND2X4TS U1393 ( .A(n2729), .B(intDY_EWSW[4]), .Y(n3402) );
NAND2X4TS U1394 ( .A(n2729), .B(n1149), .Y(n3420) );
NAND2X4TS U1395 ( .A(n2729), .B(n1187), .Y(n3464) );
NAND2X4TS U1396 ( .A(n2729), .B(n1190), .Y(n3500) );
NAND2X4TS U1397 ( .A(n2729), .B(intDY_EWSW[30]), .Y(n3602) );
NAND2X4TS U1398 ( .A(n2729), .B(intDX_EWSW[19]), .Y(n3517) );
NAND2X4TS U1399 ( .A(n2727), .B(intDX_EWSW[0]), .Y(n3476) );
NAND2X4TS U1400 ( .A(n2727), .B(intDY_EWSW[12]), .Y(n3378) );
NAND2X4TS U1401 ( .A(n2727), .B(intDY_EWSW[2]), .Y(n3408) );
NAND2X4TS U1402 ( .A(n2727), .B(intDY_EWSW[16]), .Y(n3366) );
NAND2X4TS U1403 ( .A(n2727), .B(n1154), .Y(n3506) );
NAND2X4TS U1404 ( .A(n2727), .B(intDY_EWSW[29]), .Y(n3605) );
NAND2X4TS U1405 ( .A(n2727), .B(intDY_EWSW[13]), .Y(n3375) );
NAND2X4TS U1406 ( .A(n1225), .B(intDY_EWSW[14]), .Y(n3505) );
NAND2X4TS U1407 ( .A(n1225), .B(intDY_EWSW[27]), .Y(n3419) );
NAND2X2TS U1408 ( .A(n1225), .B(intDY_EWSW[4]), .Y(n3446) );
NAND2X2TS U1409 ( .A(n1225), .B(n1183), .Y(n3392) );
NAND2X2TS U1410 ( .A(n1225), .B(n1187), .Y(n3380) );
NAND2X2TS U1411 ( .A(n1225), .B(intDX_EWSW[19]), .Y(n3356) );
NAND2X2TS U1412 ( .A(n1225), .B(intDX_EWSW[9]), .Y(n3386) );
CLKINVX3TS U1413 ( .A(n1687), .Y(n958) );
OAI2BB1X4TS U1414 ( .A0N(n1478), .A1N(n958), .B0(n1686), .Y(n1688) );
AOI22X4TS U1415 ( .A0(n1788), .A1(n2718), .B0(n1220), .B1(n2569), .Y(n1789)
);
NOR2X8TS U1416 ( .A(n1819), .B(n1827), .Y(n1829) );
NAND2X6TS U1417 ( .A(n2862), .B(intDX_EWSW[10]), .Y(n1826) );
INVX16TS U1418 ( .A(n1380), .Y(n2725) );
CLKBUFX2TS U1419 ( .A(intDX_EWSW[2]), .Y(n959) );
INVX2TS U1420 ( .A(n1992), .Y(n960) );
OAI2BB1X4TS U1421 ( .A0N(n1990), .A1N(n960), .B0(n1991), .Y(n1437) );
INVX16TS U1422 ( .A(n2130), .Y(n982) );
BUFX20TS U1423 ( .A(n1140), .Y(n2727) );
NAND4X2TS U1424 ( .A(n1970), .B(n1969), .C(n1968), .D(n1967), .Y(n1971) );
NOR2X6TS U1425 ( .A(n2565), .B(add_x_6_n183), .Y(n2007) );
NAND2X8TS U1426 ( .A(n1413), .B(n1491), .Y(n1412) );
NAND3X6TS U1427 ( .A(n1568), .B(n1420), .C(n1570), .Y(n1565) );
OAI21X4TS U1428 ( .A0(n1824), .A1(n1823), .B0(n1822), .Y(n1830) );
AND2X8TS U1429 ( .A(n1161), .B(intDY_EWSW[9]), .Y(n1824) );
NAND2BX2TS U1430 ( .AN(n2728), .B(n1143), .Y(n3461) );
INVX12TS U1431 ( .A(n1380), .Y(n1140) );
INVX16TS U1432 ( .A(n955), .Y(n965) );
NOR2X2TS U1433 ( .A(n1032), .B(n1208), .Y(n1747) );
NAND2X2TS U1434 ( .A(n1048), .B(n1418), .Y(n1417) );
CLKBUFX2TS U1435 ( .A(n2246), .Y(n1109) );
OR2X2TS U1436 ( .A(n1507), .B(n1200), .Y(n1376) );
AOI21X2TS U1437 ( .A0(n1567), .A1(n2290), .B0(n1490), .Y(n2291) );
NAND2X6TS U1438 ( .A(n1746), .B(n2228), .Y(n1438) );
NAND2X2TS U1439 ( .A(n1459), .B(n1458), .Y(n1456) );
XNOR2X1TS U1440 ( .A(intDY_EWSW[18]), .B(n1191), .Y(n1945) );
OR2X1TS U1441 ( .A(n1152), .B(n1018), .Y(n1080) );
OR2X1TS U1442 ( .A(n2384), .B(n1644), .Y(n1075) );
NAND2X4TS U1443 ( .A(n973), .B(n1260), .Y(n1738) );
NAND2X1TS U1444 ( .A(n2408), .B(DmP_mant_SFG_SWR[15]), .Y(n2001) );
AND2X2TS U1445 ( .A(n1999), .B(n2666), .Y(n1196) );
AND2X2TS U1446 ( .A(n1345), .B(Raw_mant_NRM_SWR[3]), .Y(n2494) );
NAND2X1TS U1447 ( .A(n1297), .B(n2462), .Y(n2220) );
NAND2X1TS U1448 ( .A(n1230), .B(n1104), .Y(n1101) );
NAND2X1TS U1449 ( .A(n2724), .B(n1218), .Y(n2472) );
INVX2TS U1450 ( .A(n3569), .Y(n2531) );
INVX6TS U1451 ( .A(n2678), .Y(n2632) );
XNOR2X4TS U1452 ( .A(n2375), .B(n1206), .Y(n966) );
AND2X8TS U1453 ( .A(n1343), .B(n1366), .Y(n967) );
AND2X8TS U1454 ( .A(n2129), .B(n1559), .Y(n968) );
AO22X4TS U1455 ( .A0(n2063), .A1(n2454), .B0(n2080), .B1(n2502), .Y(n969) );
CLKINVX6TS U1456 ( .A(n2065), .Y(n2310) );
AND2X8TS U1457 ( .A(DmP_mant_SFG_SWR[8]), .B(n1125), .Y(n971) );
NAND2X8TS U1458 ( .A(shift_value_SHT2_EWR[3]), .B(bit_shift_SHT2), .Y(n972)
);
CLKINVX12TS U1459 ( .A(n1312), .Y(n1366) );
NAND3X6TS U1460 ( .A(n1519), .B(n1733), .C(n1734), .Y(n973) );
NAND2X1TS U1461 ( .A(n2064), .B(n2512), .Y(n974) );
AND2X6TS U1462 ( .A(n1506), .B(n1505), .Y(n975) );
NOR2X8TS U1463 ( .A(n1578), .B(n1766), .Y(n976) );
INVX2TS U1464 ( .A(n1166), .Y(n1167) );
INVX12TS U1465 ( .A(n2663), .Y(n1028) );
NAND2X4TS U1466 ( .A(n979), .B(n1589), .Y(n3616) );
XOR2X2TS U1467 ( .A(n1592), .B(n1069), .Y(n1349) );
INVX16TS U1468 ( .A(n1620), .Y(n978) );
OAI2BB1X2TS U1469 ( .A0N(n1352), .A1N(n2572), .B0(n2571), .Y(n613) );
AOI21X2TS U1470 ( .A0(n1706), .A1(n2733), .B0(n1909), .Y(n1321) );
INVX2TS U1471 ( .A(n2536), .Y(n3594) );
XOR2X2TS U1472 ( .A(n2568), .B(n2567), .Y(n2570) );
INVX4TS U1473 ( .A(n2079), .Y(n1700) );
MXI2X4TS U1474 ( .A(n2814), .B(n2910), .S0(n2665), .Y(n776) );
NAND2X2TS U1475 ( .A(n1352), .B(n2371), .Y(n1394) );
NAND2X4TS U1476 ( .A(n1038), .B(n1261), .Y(n1316) );
INVX3TS U1477 ( .A(n2392), .Y(n1698) );
INVX3TS U1478 ( .A(n2393), .Y(n1488) );
BUFX8TS U1479 ( .A(n2476), .Y(n1345) );
NAND2X1TS U1480 ( .A(n2574), .B(final_result_ieee[13]), .Y(n3645) );
BUFX12TS U1481 ( .A(n1994), .Y(n2718) );
INVX2TS U1482 ( .A(n1076), .Y(n1351) );
INVX3TS U1483 ( .A(n1782), .Y(n1331) );
INVX4TS U1484 ( .A(n2354), .Y(n2039) );
CLKAND2X2TS U1485 ( .A(n1640), .B(n2390), .Y(n1605) );
NAND3X4TS U1486 ( .A(n3181), .B(n1911), .C(n3180), .Y(n2484) );
BUFX16TS U1487 ( .A(n2899), .Y(n1391) );
INVX2TS U1488 ( .A(n1163), .Y(n1164) );
INVX8TS U1489 ( .A(n1202), .Y(n1203) );
NAND2X1TS U1490 ( .A(n1011), .B(n1010), .Y(n3659) );
INVX2TS U1491 ( .A(add_x_6_n145), .Y(n2202) );
NAND3X4TS U1492 ( .A(n1372), .B(n1370), .C(n1371), .Y(n599) );
NAND3X4TS U1493 ( .A(n1399), .B(n1398), .C(n1397), .Y(n603) );
NAND3X4TS U1494 ( .A(n1473), .B(n1470), .C(n1469), .Y(n601) );
INVX12TS U1495 ( .A(n978), .Y(n1616) );
NAND3X4TS U1496 ( .A(n1357), .B(n1356), .C(n1353), .Y(n595) );
NAND2X4TS U1497 ( .A(n1281), .B(n2424), .Y(n2062) );
NOR2X4TS U1498 ( .A(n1409), .B(n1075), .Y(n1588) );
NAND3X4TS U1499 ( .A(n1531), .B(n1529), .C(n1528), .Y(n605) );
INVX6TS U1500 ( .A(n1017), .Y(n1297) );
OAI21X2TS U1501 ( .A0(n1396), .A1(n1358), .B0(n2217), .Y(n610) );
NOR2X4TS U1502 ( .A(n980), .B(n2046), .Y(n1333) );
NOR2X4TS U1503 ( .A(n2060), .B(n2225), .Y(n1337) );
AOI21X2TS U1504 ( .A0(n1706), .A1(n1081), .B0(n2084), .Y(n2085) );
NAND2X4TS U1505 ( .A(n1386), .B(n1385), .Y(n2419) );
XNOR2X2TS U1506 ( .A(n1296), .B(n2149), .Y(n2153) );
NAND2X4TS U1507 ( .A(n2059), .B(n1153), .Y(n2225) );
XOR2X2TS U1508 ( .A(n2213), .B(n2212), .Y(n1396) );
NAND3X4TS U1509 ( .A(n1565), .B(n1564), .C(n2394), .Y(n1569) );
INVX12TS U1510 ( .A(n1542), .Y(n2124) );
INVX2TS U1511 ( .A(n2519), .Y(n2520) );
INVX2TS U1512 ( .A(n3565), .Y(n2281) );
NAND3X2TS U1513 ( .A(n1395), .B(n1394), .C(n1393), .Y(n619) );
NAND2X4TS U1514 ( .A(n2738), .B(n2413), .Y(n1729) );
NAND2X6TS U1515 ( .A(n2137), .B(n1498), .Y(n1108) );
INVX2TS U1516 ( .A(n794), .Y(n1740) );
NOR2X4TS U1517 ( .A(n2445), .B(n2444), .Y(n2547) );
INVX2TS U1518 ( .A(n1721), .Y(n2377) );
INVX2TS U1519 ( .A(n2738), .Y(n1512) );
NAND2X4TS U1520 ( .A(n2282), .B(n1685), .Y(n1687) );
XOR2X1TS U1521 ( .A(n2580), .B(n2579), .Y(n2586) );
INVX2TS U1522 ( .A(n2537), .Y(n2589) );
CLKMX2X2TS U1523 ( .A(Data_X[18]), .B(n1191), .S0(n1116), .Y(n925) );
CLKMX2X2TS U1524 ( .A(Data_X[1]), .B(n1205), .S0(n1115), .Y(n942) );
INVX3TS U1525 ( .A(n2396), .Y(n1487) );
NAND4X6TS U1526 ( .A(n1182), .B(n1997), .C(n1996), .D(n1998), .Y(n2588) );
INVX16TS U1527 ( .A(n1037), .Y(n2665) );
NAND2X4TS U1528 ( .A(n1568), .B(n1488), .Y(n2396) );
INVX12TS U1529 ( .A(n981), .Y(n1117) );
NAND2X6TS U1530 ( .A(n1901), .B(n1900), .Y(n1902) );
INVX12TS U1531 ( .A(n2424), .Y(n1262) );
INVX12TS U1532 ( .A(n981), .Y(n1118) );
BUFX12TS U1533 ( .A(n2497), .Y(n1424) );
INVX12TS U1534 ( .A(n981), .Y(n1119) );
NAND2X1TS U1535 ( .A(n2574), .B(final_result_ieee[4]), .Y(n3621) );
INVX8TS U1536 ( .A(n1388), .Y(n2517) );
NAND2X6TS U1537 ( .A(n1899), .B(n1376), .Y(n1375) );
INVX12TS U1538 ( .A(n2724), .Y(n2497) );
INVX8TS U1539 ( .A(n1240), .Y(n1241) );
NOR2X4TS U1540 ( .A(n1341), .B(n1713), .Y(n1431) );
CLKMX2X2TS U1541 ( .A(DMP_exp_NRM_EW[6]), .B(DMP_SFG[29]), .S0(n1255), .Y(
n697) );
AOI22X2TS U1542 ( .A0(n1314), .A1(n2484), .B0(n2723), .B1(n1624), .Y(n1323)
);
NOR2X2TS U1543 ( .A(n1388), .B(n2833), .Y(n2237) );
NAND2X1TS U1544 ( .A(n2662), .B(n2635), .Y(n3600) );
NOR2X6TS U1545 ( .A(n2367), .B(n2366), .Y(n2667) );
NAND2X6TS U1546 ( .A(n1752), .B(n1753), .Y(n1774) );
BUFX20TS U1547 ( .A(n1710), .Y(n2574) );
NAND2X2TS U1548 ( .A(n1391), .B(n1216), .Y(n1403) );
CLKAND2X2TS U1549 ( .A(n2317), .B(n2774), .Y(n1073) );
NAND2X1TS U1550 ( .A(n2662), .B(n2631), .Y(n3526) );
NAND2X1TS U1551 ( .A(n2662), .B(n2629), .Y(n3521) );
NAND2X1TS U1552 ( .A(n2662), .B(n2628), .Y(n3512) );
NAND2X1TS U1553 ( .A(n2662), .B(n2623), .Y(n3515) );
NAND2X1TS U1554 ( .A(n2662), .B(n2624), .Y(n3518) );
AND2X2TS U1555 ( .A(n1127), .B(n2104), .Y(n1069) );
OR2X4TS U1556 ( .A(n2004), .B(n1644), .Y(n1623) );
NAND2X1TS U1557 ( .A(n1710), .B(final_result_ieee[7]), .Y(n3630) );
NAND2X1TS U1558 ( .A(n1710), .B(final_result_ieee[6]), .Y(n3627) );
NAND2X6TS U1559 ( .A(n2656), .B(beg_OP), .Y(n2655) );
INVX8TS U1560 ( .A(n1137), .Y(n2560) );
INVX16TS U1561 ( .A(n1762), .Y(n1240) );
BUFX3TS U1562 ( .A(n3327), .Y(n3326) );
BUFX8TS U1563 ( .A(n2352), .Y(n1373) );
INVX3TS U1564 ( .A(n2641), .Y(n2035) );
CLKMX2X2TS U1565 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(n2634),
.Y(n711) );
BUFX20TS U1566 ( .A(n2638), .Y(n2652) );
NAND2X2TS U1567 ( .A(n1771), .B(n1772), .Y(n1597) );
BUFX8TS U1568 ( .A(n2638), .Y(n2662) );
NAND2X1TS U1569 ( .A(n1517), .B(final_result_ieee[1]), .Y(n3612) );
NAND2X1TS U1570 ( .A(n1644), .B(final_result_ieee[2]), .Y(n3615) );
NAND2X1TS U1571 ( .A(n1517), .B(final_result_ieee[0]), .Y(n3609) );
NAND2X1TS U1572 ( .A(n1517), .B(final_result_ieee[3]), .Y(n3618) );
AND2X4TS U1573 ( .A(n1148), .B(n1130), .Y(n1763) );
NAND2X1TS U1574 ( .A(n1517), .B(final_result_ieee[5]), .Y(n3624) );
NAND2X4TS U1575 ( .A(add_x_6_B_13_), .B(add_x_6_A_13_), .Y(n1048) );
NAND2X2TS U1576 ( .A(DMP_SFG[22]), .B(DmP_mant_SFG_SWR[24]), .Y(n2390) );
INVX2TS U1577 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n2592) );
INVX6TS U1578 ( .A(n1210), .Y(n1211) );
NAND2X4TS U1579 ( .A(add_x_6_A_5_), .B(add_x_6_B_5_), .Y(n2552) );
NAND2X4TS U1580 ( .A(add_x_6_A_7_), .B(add_x_6_B_7_), .Y(n2566) );
NAND3X4TS U1581 ( .A(n3091), .B(n3090), .C(n3089), .Y(n2688) );
INVX4TS U1582 ( .A(n1220), .Y(n1221) );
INVX4TS U1583 ( .A(n1110), .Y(n1111) );
INVX12TS U1584 ( .A(Shift_reg_FLAGS_7_5), .Y(n2678) );
INVX6TS U1585 ( .A(n1147), .Y(n1148) );
NAND2X4TS U1586 ( .A(n1643), .B(DMP_SFG[6]), .Y(n1782) );
NAND2X4TS U1587 ( .A(add_x_6_A_20_), .B(add_x_6_B_20_), .Y(n2318) );
INVX4TS U1588 ( .A(n1212), .Y(n1213) );
NOR2X6TS U1589 ( .A(add_x_6_n77), .B(add_x_6_n70), .Y(n1697) );
BUFX16TS U1590 ( .A(n1207), .Y(n2352) );
INVX2TS U1591 ( .A(DmP_mant_SHT1_SW[5]), .Y(n2504) );
NAND2X4TS U1592 ( .A(n2990), .B(n2989), .Y(n1450) );
INVX8TS U1593 ( .A(n2928), .Y(busy) );
OAI2BB1X2TS U1594 ( .A0N(n3270), .A1N(n1003), .B0(n3269), .Y(
final_result_ieee[31]) );
INVX4TS U1595 ( .A(n1204), .Y(n2993) );
NAND2X4TS U1596 ( .A(n2322), .B(n1352), .Y(n1372) );
NAND2X4TS U1597 ( .A(n1616), .B(n1588), .Y(n2841) );
NAND2X6TS U1598 ( .A(n2297), .B(n1352), .Y(n1404) );
INVX3TS U1599 ( .A(n606), .Y(n3007) );
NAND2X6TS U1600 ( .A(n1350), .B(n1352), .Y(n1423) );
NAND2X4TS U1601 ( .A(n2296), .B(n2295), .Y(n1402) );
INVX12TS U1602 ( .A(n978), .Y(n979) );
NAND2X4TS U1603 ( .A(n1359), .B(n1352), .Y(n1357) );
NAND2X4TS U1604 ( .A(n1354), .B(n2295), .Y(n1353) );
NAND2X4TS U1605 ( .A(n1471), .B(n2295), .Y(n1470) );
OAI2BB1X2TS U1606 ( .A0N(n1212), .A1N(n1391), .B0(n2399), .Y(n628) );
NAND2X4TS U1607 ( .A(n2114), .B(n1352), .Y(n1473) );
NAND2X6TS U1608 ( .A(n1702), .B(n2295), .Y(n1421) );
NAND2X6TS U1609 ( .A(n1156), .B(n1240), .Y(n1536) );
OAI2BB1X2TS U1610 ( .A0N(n2722), .A1N(n2153), .B0(n2152), .Y(n609) );
NAND2X2TS U1611 ( .A(n2398), .B(n2718), .Y(n2399) );
NOR3X4TS U1612 ( .A(n2273), .B(n2272), .C(n2271), .Y(n2274) );
NOR2X4TS U1613 ( .A(n1409), .B(n1079), .Y(n1589) );
NOR2X4TS U1614 ( .A(n1425), .B(n1512), .Y(n1516) );
NAND3X4TS U1615 ( .A(n1486), .B(n1484), .C(n2390), .Y(n1355) );
NAND2X4TS U1616 ( .A(n1530), .B(n1265), .Y(n1529) );
NAND2X4TS U1617 ( .A(n2778), .B(n788), .Y(n2783) );
NAND2BX2TS U1618 ( .AN(n1068), .B(n1535), .Y(n1472) );
NAND2X4TS U1619 ( .A(n2171), .B(n1265), .Y(n1399) );
NAND2X6TS U1620 ( .A(n1436), .B(n2295), .Y(n1435) );
NAND2X4TS U1621 ( .A(n2414), .B(n2330), .Y(n1326) );
NAND3X4TS U1622 ( .A(n1108), .B(n1105), .C(n1078), .Y(n1102) );
NAND3X6TS U1623 ( .A(n1729), .B(n1728), .C(n1727), .Y(n552) );
OAI2BB1X2TS U1624 ( .A0N(n1352), .A1N(n2018), .B0(n2017), .Y(n611) );
INVX8TS U1625 ( .A(n1100), .Y(n991) );
NAND3X2TS U1626 ( .A(n2270), .B(n2269), .C(n2268), .Y(n2272) );
AOI21X2TS U1627 ( .A0(n2735), .A1(n1706), .B0(n2422), .Y(n1034) );
XNOR2X2TS U1628 ( .A(n2031), .B(n2030), .Y(n2032) );
NAND2X6TS U1629 ( .A(n1327), .B(n1323), .Y(n2414) );
INVX2TS U1630 ( .A(n3551), .Y(n3557) );
INVX2TS U1631 ( .A(n3564), .Y(n3583) );
NAND2X4TS U1632 ( .A(n1230), .B(DmP_mant_SFG_SWR[12]), .Y(n1104) );
NAND3X4TS U1633 ( .A(n2479), .B(n2478), .C(n2477), .Y(n3556) );
NAND2X4TS U1634 ( .A(n1457), .B(n1456), .Y(n1327) );
NOR2X4TS U1635 ( .A(n2238), .B(n2237), .Y(n2536) );
NAND2X6TS U1636 ( .A(n2136), .B(n1384), .Y(n1105) );
NAND2X4TS U1637 ( .A(n2243), .B(n1988), .Y(n998) );
NAND2X6TS U1638 ( .A(n1028), .B(n2385), .Y(n1027) );
NAND2X4TS U1639 ( .A(n1040), .B(n1602), .Y(n1612) );
INVX12TS U1640 ( .A(n1028), .Y(n2677) );
MX2X2TS U1641 ( .A(Data_X[15]), .B(n1151), .S0(n1114), .Y(n928) );
MX2X2TS U1642 ( .A(Data_X[10]), .B(intDX_EWSW[10]), .S0(n1118), .Y(n933) );
CLKMX2X2TS U1643 ( .A(Data_X[5]), .B(n1180), .S0(n1114), .Y(n938) );
MX2X2TS U1644 ( .A(Data_Y[30]), .B(intDY_EWSW[30]), .S0(n1113), .Y(n880) );
MX2X2TS U1645 ( .A(Data_X[9]), .B(intDX_EWSW[9]), .S0(n1114), .Y(n934) );
MX2X2TS U1646 ( .A(Data_X[13]), .B(intDX_EWSW[13]), .S0(n1119), .Y(n930) );
CLKMX2X2TS U1647 ( .A(Data_X[26]), .B(n1155), .S0(n1116), .Y(n917) );
CLKMX2X2TS U1648 ( .A(Data_X[20]), .B(n1150), .S0(n1113), .Y(n923) );
CLKMX2X2TS U1649 ( .A(Data_X[22]), .B(n1184), .S0(n1117), .Y(n921) );
CLKMX2X2TS U1650 ( .A(Data_X[11]), .B(n1187), .S0(n1115), .Y(n932) );
MX2X2TS U1651 ( .A(Data_X[25]), .B(n1268), .S0(n1117), .Y(n918) );
NOR2X6TS U1652 ( .A(n2313), .B(n1683), .Y(n2282) );
MX2X2TS U1653 ( .A(Data_X[16]), .B(n1190), .S0(n1113), .Y(n927) );
CLKMX2X2TS U1654 ( .A(Data_X[21]), .B(n1157), .S0(n1118), .Y(n922) );
CLKMX2X2TS U1655 ( .A(Data_X[3]), .B(n1178), .S0(n1114), .Y(n940) );
CLKMX2X2TS U1656 ( .A(Data_X[12]), .B(n1143), .S0(n1119), .Y(n931) );
MX2X2TS U1657 ( .A(Data_X[8]), .B(intDX_EWSW[8]), .S0(n1117), .Y(n935) );
CLKMX2X2TS U1658 ( .A(Data_X[17]), .B(n1198), .S0(n1119), .Y(n926) );
CLKMX2X2TS U1659 ( .A(Data_X[6]), .B(n1177), .S0(n1119), .Y(n937) );
MX2X2TS U1660 ( .A(Data_X[2]), .B(n959), .S0(n1117), .Y(n941) );
CLKMX2X2TS U1661 ( .A(Data_X[14]), .B(n1154), .S0(n1117), .Y(n929) );
MX2X2TS U1662 ( .A(Data_X[24]), .B(intDX_EWSW[24]), .S0(n1119), .Y(n919) );
CLKMX2X2TS U1663 ( .A(Data_X[7]), .B(n1183), .S0(n1113), .Y(n936) );
MX2X2TS U1664 ( .A(Data_X[19]), .B(intDX_EWSW[19]), .S0(n1115), .Y(n924) );
MX2X2TS U1665 ( .A(Data_X[4]), .B(intDX_EWSW[4]), .S0(n1113), .Y(n939) );
NAND2X2TS U1666 ( .A(n2443), .B(n2442), .Y(n2445) );
MX2X2TS U1667 ( .A(Data_Y[28]), .B(intDY_EWSW[28]), .S0(n1116), .Y(n882) );
MX2X2TS U1668 ( .A(Data_Y[12]), .B(intDY_EWSW[12]), .S0(n1115), .Y(n898) );
MX2X2TS U1669 ( .A(Data_Y[26]), .B(intDY_EWSW[26]), .S0(n1113), .Y(n884) );
MX2X2TS U1670 ( .A(Data_Y[16]), .B(intDY_EWSW[16]), .S0(n1116), .Y(n894) );
MX2X2TS U1671 ( .A(Data_Y[29]), .B(intDY_EWSW[29]), .S0(n1113), .Y(n881) );
MX2X2TS U1672 ( .A(Data_Y[8]), .B(intDY_EWSW[8]), .S0(n1119), .Y(n902) );
MX2X2TS U1673 ( .A(Data_Y[21]), .B(intDY_EWSW[21]), .S0(n1114), .Y(n889) );
MX2X2TS U1674 ( .A(Data_Y[3]), .B(intDY_EWSW[3]), .S0(n1119), .Y(n907) );
MX2X2TS U1675 ( .A(Data_Y[20]), .B(intDY_EWSW[20]), .S0(n1113), .Y(n890) );
MX2X2TS U1676 ( .A(Data_Y[6]), .B(intDY_EWSW[6]), .S0(n1118), .Y(n904) );
MX2X2TS U1677 ( .A(Data_Y[24]), .B(intDY_EWSW[24]), .S0(n1114), .Y(n886) );
MX2X2TS U1678 ( .A(Data_Y[25]), .B(intDY_EWSW[25]), .S0(n1118), .Y(n885) );
MX2X2TS U1679 ( .A(Data_Y[22]), .B(intDY_EWSW[22]), .S0(n1118), .Y(n888) );
MX2X2TS U1680 ( .A(Data_Y[14]), .B(intDY_EWSW[14]), .S0(n1119), .Y(n896) );
MX2X2TS U1681 ( .A(Data_Y[10]), .B(intDY_EWSW[10]), .S0(n1117), .Y(n900) );
MX2X2TS U1682 ( .A(Data_Y[31]), .B(intDY_EWSW[31]), .S0(n1116), .Y(n879) );
MX2X2TS U1683 ( .A(add_subt), .B(intAS), .S0(n1115), .Y(n911) );
MX2X2TS U1684 ( .A(Data_Y[27]), .B(intDY_EWSW[27]), .S0(n1119), .Y(n883) );
NAND2X2TS U1685 ( .A(n2303), .B(n2302), .Y(n2305) );
OR2X4TS U1686 ( .A(n1424), .B(n1136), .Y(n2436) );
NAND2X1TS U1687 ( .A(n1388), .B(n2368), .Y(n878) );
NAND3X6TS U1688 ( .A(n1103), .B(n1106), .C(n1107), .Y(n2136) );
MX2X2TS U1689 ( .A(Data_X[0]), .B(intDX_EWSW[0]), .S0(n1115), .Y(n943) );
BUFX8TS U1690 ( .A(n2323), .Y(n2722) );
MX2X2TS U1691 ( .A(Data_Y[4]), .B(intDY_EWSW[4]), .S0(n1116), .Y(n906) );
MX2X2TS U1692 ( .A(Data_Y[23]), .B(intDY_EWSW[23]), .S0(n1114), .Y(n887) );
MX2X2TS U1693 ( .A(Data_Y[2]), .B(intDY_EWSW[2]), .S0(n1117), .Y(n908) );
INVX8TS U1694 ( .A(n1311), .Y(n1721) );
CLKMX2X2TS U1695 ( .A(Data_X[30]), .B(intDX_EWSW[30]), .S0(n1118), .Y(n913)
);
OAI2BB1X2TS U1696 ( .A0N(OP_FLAG_EXP), .A1N(n2652), .B0(n2364), .Y(n802) );
INVX12TS U1697 ( .A(n2424), .Y(n2506) );
NAND2X6TS U1698 ( .A(n1044), .B(n1062), .Y(n1400) );
NAND2X2TS U1699 ( .A(n2517), .B(n1210), .Y(n2457) );
NAND2X2TS U1700 ( .A(n2240), .B(n2239), .Y(n2242) );
NAND2X4TS U1701 ( .A(n1739), .B(n1498), .Y(n1497) );
INVX8TS U1702 ( .A(n1358), .Y(n2323) );
AND2X4TS U1703 ( .A(n1605), .B(n1383), .Y(n2395) );
NAND2X6TS U1704 ( .A(n1698), .B(n1485), .Y(n2079) );
AOI22X2TS U1705 ( .A0(n1314), .A1(n2488), .B0(n1313), .B1(n2437), .Y(n1339)
);
INVX16TS U1706 ( .A(n1655), .Y(n1037) );
INVX12TS U1707 ( .A(n1240), .Y(n1243) );
NOR2X4TS U1708 ( .A(n2103), .B(n2110), .Y(n1604) );
OA21X4TS U1709 ( .A0(n1032), .A1(n2833), .B0(n2044), .Y(n1595) );
INVX6TS U1710 ( .A(n1240), .Y(n1242) );
CLKMX2X2TS U1711 ( .A(SIGN_FLAG_NRM), .B(SIGN_FLAG_SFG), .S0(n1255), .Y(n623) );
INVX2TS U1712 ( .A(n1615), .Y(n2050) );
NAND2X1TS U1713 ( .A(n2646), .B(n2354), .Y(n3424) );
NAND2X6TS U1714 ( .A(n1881), .B(n985), .Y(n1846) );
NAND2X1TS U1715 ( .A(n2662), .B(n2636), .Y(n3606) );
NAND2X1TS U1716 ( .A(n2646), .B(n2641), .Y(n3433) );
NAND2X2TS U1717 ( .A(n2064), .B(n2474), .Y(n1112) );
NAND2X1TS U1718 ( .A(n2356), .B(n2614), .Y(n3391) );
AND2X2TS U1719 ( .A(n1489), .B(n2286), .Y(n2293) );
INVX3TS U1720 ( .A(n1141), .Y(n1179) );
NAND2X1TS U1721 ( .A(n2646), .B(n2682), .Y(n3483) );
INVX8TS U1722 ( .A(n1127), .Y(n2103) );
NAND2X4TS U1723 ( .A(n2459), .B(n1174), .Y(n1444) );
INVX12TS U1724 ( .A(n1035), .Y(n1655) );
NAND2X1TS U1725 ( .A(n2356), .B(n2630), .Y(n3409) );
NAND2X1TS U1726 ( .A(n2356), .B(n2625), .Y(n3412) );
NAND2X1TS U1727 ( .A(n2356), .B(n2626), .Y(n3406) );
INVX12TS U1728 ( .A(n1554), .Y(n2724) );
NAND2X1TS U1729 ( .A(n2356), .B(n2627), .Y(n3403) );
CLKMX2X2TS U1730 ( .A(DMP_SHT1_EWSW[27]), .B(n2642), .S0(n2639), .Y(n710) );
NAND2X1TS U1731 ( .A(n2356), .B(n2616), .Y(n3400) );
NAND2X1TS U1732 ( .A(n2356), .B(n2615), .Y(n3397) );
NAND2X1TS U1733 ( .A(n2646), .B(n2355), .Y(n3418) );
INVX16TS U1734 ( .A(n2655), .Y(n981) );
NAND2X1TS U1735 ( .A(n2356), .B(n2619), .Y(n3394) );
NAND2X1TS U1736 ( .A(n2356), .B(n2622), .Y(n3388) );
NAND2X1TS U1737 ( .A(n2356), .B(n2618), .Y(n3379) );
NAND2X1TS U1738 ( .A(n2646), .B(n2617), .Y(n3385) );
INVX2TS U1739 ( .A(n1369), .Y(n2211) );
NAND2X1TS U1740 ( .A(n2647), .B(n2612), .Y(n3373) );
NAND2X1TS U1741 ( .A(n2647), .B(n2620), .Y(n3376) );
NAND2X1TS U1742 ( .A(n2611), .B(n2593), .Y(n952) );
NAND2X6TS U1743 ( .A(n1753), .B(n3549), .Y(n1766) );
NAND2X6TS U1744 ( .A(n2602), .B(n2605), .Y(n1522) );
NAND2X1TS U1745 ( .A(n1517), .B(final_result_ieee[9]), .Y(n3636) );
INVX8TS U1746 ( .A(n2678), .Y(n2633) );
NAND2X6TS U1747 ( .A(DmP_mant_SFG_SWR[6]), .B(n1173), .Y(n1172) );
NAND2X4TS U1748 ( .A(n2045), .B(n1767), .Y(n1759) );
NAND2X6TS U1749 ( .A(n1171), .B(n1162), .Y(n1712) );
NAND2X6TS U1750 ( .A(n1518), .B(n2837), .Y(n2602) );
NAND2X6TS U1751 ( .A(n1171), .B(DMP_exp_NRM2_EW[5]), .Y(n2604) );
NAND2X6TS U1752 ( .A(n1212), .B(n2505), .Y(n2507) );
NAND2X6TS U1753 ( .A(n1213), .B(n2352), .Y(n1554) );
NOR2X4TS U1754 ( .A(n1019), .B(n1147), .Y(n2223) );
INVX12TS U1755 ( .A(n3312), .Y(n1710) );
NAND2X6TS U1756 ( .A(DmP_mant_SFG_SWR[20]), .B(n1128), .Y(n1127) );
NAND2X4TS U1757 ( .A(n1775), .B(n1111), .Y(n1615) );
NAND2X1TS U1758 ( .A(n1517), .B(final_result_ieee[8]), .Y(n3633) );
NAND2X4TS U1759 ( .A(n1776), .B(n1147), .Y(n2043) );
NAND2X1TS U1760 ( .A(n1517), .B(final_result_ieee[12]), .Y(n3642) );
NOR2X6TS U1761 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n2898), .Y(n2654) );
INVX2TS U1762 ( .A(n1185), .Y(n1186) );
AND2X2TS U1763 ( .A(n2771), .B(add_x_6_n89), .Y(n1072) );
INVX2TS U1764 ( .A(n3682), .Y(n2660) );
INVX8TS U1765 ( .A(Shift_reg_FLAGS_7[3]), .Y(n1036) );
NAND2X6TS U1766 ( .A(n2840), .B(n1163), .Y(n1091) );
OR2X4TS U1767 ( .A(n2968), .B(n2969), .Y(n1063) );
MX2X1TS U1768 ( .A(DMP_SHT2_EWSW[27]), .B(DMP_SHT1_EWSW[27]), .S0(n3682),
.Y(n709) );
NOR2X6TS U1769 ( .A(add_x_6_A_18_), .B(add_x_6_B_18_), .Y(n2113) );
INVX2TS U1770 ( .A(n3306), .Y(n1611) );
MX2X1TS U1771 ( .A(DMP_SHT2_EWSW[6]), .B(DMP_SHT1_EWSW[6]), .S0(n3682), .Y(
n780) );
MX2X1TS U1772 ( .A(DMP_SHT2_EWSW[26]), .B(DMP_SHT1_EWSW[26]), .S0(n3682),
.Y(n714) );
NAND3X4TS U1773 ( .A(n3148), .B(n3147), .C(n3146), .Y(n2354) );
NAND3X2TS U1774 ( .A(n3079), .B(n3078), .C(n3077), .Y(n2642) );
INVX2TS U1775 ( .A(inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n2365) );
INVX12TS U1776 ( .A(Shift_reg_FLAGS_7_6), .Y(n2638) );
INVX2TS U1777 ( .A(n1029), .Y(n1030) );
INVX6TS U1778 ( .A(sub_x_5_A_7_), .Y(n1138) );
NAND2X6TS U1779 ( .A(n1630), .B(sub_x_5_A_7_), .Y(n2561) );
BUFX8TS U1780 ( .A(n3682), .Y(n2661) );
MX2X1TS U1781 ( .A(DMP_SHT2_EWSW[4]), .B(DMP_SHT1_EWSW[4]), .S0(n3682), .Y(
n786) );
NAND2X6TS U1782 ( .A(n2843), .B(intDX_EWSW[24]), .Y(n994) );
INVX8TS U1783 ( .A(n1152), .Y(n1153) );
INVX12TS U1784 ( .A(n1214), .Y(n1215) );
INVX8TS U1785 ( .A(n1216), .Y(n1217) );
AND2X8TS U1786 ( .A(n1159), .B(intDY_EWSW[19]), .Y(n1860) );
OAI22X4TS U1787 ( .A0(n1983), .A1(n2364), .B0(Shift_reg_FLAGS_7_6), .B1(
n2878), .Y(n801) );
NAND3BX4TS U1788 ( .AN(n1363), .B(n1975), .C(n1974), .Y(n1983) );
AND2X8TS U1789 ( .A(n3309), .B(n1203), .Y(n2229) );
INVX16TS U1790 ( .A(n2732), .Y(n1228) );
NAND2X4TS U1791 ( .A(n2874), .B(n1190), .Y(n1856) );
NAND2X4TS U1792 ( .A(n2733), .B(n1261), .Y(n1504) );
OR2X8TS U1793 ( .A(n1274), .B(n1498), .Y(n1513) );
AOI21X4TS U1794 ( .A0(n2265), .A1(n970), .B0(n1593), .Y(n1492) );
NAND2X8TS U1795 ( .A(n1287), .B(n2247), .Y(n1286) );
OR2X8TS U1796 ( .A(n1288), .B(n1672), .Y(n2247) );
NOR2X8TS U1797 ( .A(n1876), .B(n986), .Y(n985) );
NOR2X8TS U1798 ( .A(n2871), .B(intDX_EWSW[25]), .Y(n1876) );
NOR2X8TS U1799 ( .A(n1879), .B(n987), .Y(n1881) );
BUFX12TS U1800 ( .A(n1479), .Y(n988) );
CLKINVX12TS U1801 ( .A(n1479), .Y(n1579) );
NAND4X8TS U1802 ( .A(n1477), .B(n1474), .C(n1475), .D(n1476), .Y(n1479) );
OAI22X4TS U1803 ( .A0(n990), .A1(n989), .B0(n3312), .B1(n2914), .Y(n589) );
NOR2X8TS U1804 ( .A(n2862), .B(intDX_EWSW[10]), .Y(n1819) );
OAI22X4TS U1805 ( .A0(n1876), .A1(n994), .B0(intDY_EWSW[25]), .B1(n992), .Y(
n1882) );
INVX2TS U1806 ( .A(intDX_EWSW[25]), .Y(n992) );
XOR2X4TS U1807 ( .A(n995), .B(n1993), .Y(n1434) );
OAI21X4TS U1808 ( .A0(n2250), .A1(n998), .B0(n996), .Y(n995) );
AOI21X4TS U1809 ( .A0(n2247), .A1(n1988), .B0(n997), .Y(n996) );
OAI21X4TS U1810 ( .A0(n1181), .A1(n2175), .B0(n2176), .Y(n997) );
BUFX4TS U1811 ( .A(n1096), .Y(n1409) );
NOR2X6TS U1812 ( .A(n2855), .B(n1187), .Y(n1827) );
AOI2BB1X4TS U1813 ( .A0N(n1170), .A1N(LZD_output_NRM2_EW[3]), .B0(
DMP_exp_NRM2_EW[3]), .Y(n1367) );
NAND2X8TS U1814 ( .A(DMP_exp_NRM2_EW[2]), .B(n1000), .Y(n1055) );
NAND2X6TS U1815 ( .A(n1557), .B(n2733), .Y(n3625) );
INVX8TS U1816 ( .A(n1201), .Y(n1001) );
INVX8TS U1817 ( .A(n1532), .Y(n1201) );
AO22X2TS U1818 ( .A0(n3172), .A1(n3171), .B0(n3170), .B1(n1003), .Y(
final_result_ieee[30]) );
AND2X8TS U1819 ( .A(n2066), .B(n2068), .Y(n1525) );
NAND3X4TS U1820 ( .A(n1051), .B(n1459), .C(n1461), .Y(n1457) );
AOI2BB2X4TS U1821 ( .B0(n1004), .B1(n2967), .A0N(n2966), .A1N(n2965), .Y(
n1705) );
AOI2BB2X4TS U1822 ( .B0(n2979), .B1(n2978), .A0N(n2977), .A1N(n2976), .Y(
n1647) );
AOI2BB2X4TS U1823 ( .B0(n1005), .B1(n2982), .A0N(n2981), .A1N(n2980), .Y(
n1911) );
NAND2X4TS U1824 ( .A(n3177), .B(n3176), .Y(n1007) );
AOI21X4TS U1825 ( .A0(n2987), .A1(n2988), .B0(n1007), .Y(n1499) );
AOI2BB2X4TS U1826 ( .B0(n2960), .B1(n1006), .A0N(n1002), .A1N(n2959), .Y(
n1646) );
AOI21X4TS U1827 ( .A0(n2970), .A1(n2971), .B0(n1455), .Y(n1454) );
OAI21X1TS U1828 ( .A0(n2789), .A1(sub_x_5_n198), .B0(n2710), .Y(n2713) );
NAND2X1TS U1829 ( .A(n2788), .B(n2710), .Y(n2700) );
XOR2X1TS U1830 ( .A(n2789), .B(n2700), .Y(n2708) );
NAND4X2TS U1831 ( .A(n3659), .B(n965), .C(n3296), .D(n3295), .Y(
final_result_ieee[17]) );
BUFX12TS U1832 ( .A(n3311), .Y(n1405) );
OAI21X4TS U1833 ( .A0(n2250), .A1(n2249), .B0(n2248), .Y(n2254) );
NAND2X6TS U1834 ( .A(n1609), .B(n988), .Y(n1608) );
NAND2X4TS U1835 ( .A(n1491), .B(n1539), .Y(n1012) );
NAND2X6TS U1836 ( .A(n1491), .B(n1539), .Y(n3310) );
CLKINVX12TS U1837 ( .A(Raw_mant_NRM_SWR[24]), .Y(n1015) );
INVX16TS U1838 ( .A(n1015), .Y(n1016) );
NOR2X8TS U1839 ( .A(n1517), .B(n1276), .Y(n3311) );
NOR2X6TS U1840 ( .A(n1218), .B(n1110), .Y(n1771) );
NAND2X2TS U1841 ( .A(n2064), .B(n2450), .Y(n1667) );
NOR2X4TS U1842 ( .A(n1406), .B(n1518), .Y(n1087) );
NOR2X4TS U1843 ( .A(n1152), .B(n1029), .Y(n1776) );
NAND2X6TS U1844 ( .A(n2106), .B(n1679), .Y(n2313) );
NAND2X4TS U1845 ( .A(n1134), .B(n1314), .Y(n1107) );
INVX4TS U1846 ( .A(n1124), .Y(n1103) );
NAND2X4TS U1847 ( .A(n1575), .B(n1215), .Y(n1433) );
NAND3X4TS U1848 ( .A(n3242), .B(n3241), .C(n3240), .Y(n2512) );
NAND2X4TS U1849 ( .A(n1624), .B(n2503), .Y(n1453) );
NOR2X4TS U1850 ( .A(n2852), .B(n1157), .Y(n1866) );
NOR2X6TS U1851 ( .A(n2851), .B(n1158), .Y(n1869) );
NOR2X4TS U1852 ( .A(n2839), .B(n1162), .Y(n1092) );
NOR2X4TS U1853 ( .A(n1627), .B(DMP_SFG[22]), .Y(n2073) );
OR2X6TS U1854 ( .A(n2200), .B(add_x_6_n138), .Y(n1418) );
NAND2X6TS U1855 ( .A(n2158), .B(n1694), .Y(n1695) );
NAND2X6TS U1856 ( .A(n1639), .B(sub_x_5_A_13_), .Y(n2244) );
NAND2X6TS U1857 ( .A(sub_x_5_n237), .B(DMP_SFG[15]), .Y(n2155) );
OAI21X2TS U1858 ( .A0(n2166), .A1(n2160), .B0(n2167), .Y(n1693) );
NOR2X4TS U1859 ( .A(n1024), .B(n1221), .Y(n2264) );
INVX2TS U1860 ( .A(LZD_output_NRM2_EW[1]), .Y(n1599) );
NAND2X4TS U1861 ( .A(n1086), .B(DMP_exp_NRM2_EW[2]), .Y(n1085) );
NOR2X4TS U1862 ( .A(n1711), .B(n1163), .Y(n1720) );
NOR2X4TS U1863 ( .A(n1518), .B(n2839), .Y(n1714) );
NAND2X1TS U1864 ( .A(n2063), .B(n2502), .Y(n1506) );
INVX2TS U1865 ( .A(n2503), .Y(n1510) );
NOR2X2TS U1866 ( .A(n1972), .B(n1971), .Y(n1973) );
OAI21X2TS U1867 ( .A0(n2257), .A1(n2183), .B0(n2182), .Y(n1392) );
INVX2TS U1868 ( .A(DmP_mant_SFG_SWR[25]), .Y(n1415) );
NAND2X2TS U1869 ( .A(n2079), .B(n2391), .Y(n1484) );
NOR2X2TS U1870 ( .A(Raw_mant_NRM_SWR[16]), .B(n1135), .Y(n1544) );
NAND2X4TS U1871 ( .A(n2600), .B(n1260), .Y(n1906) );
NAND3X4TS U1872 ( .A(n1651), .B(n1652), .C(n1650), .Y(n2598) );
NAND2X2TS U1873 ( .A(n2064), .B(n870), .Y(n1449) );
NAND2X2TS U1874 ( .A(n1391), .B(n1110), .Y(n1371) );
NAND2X1TS U1875 ( .A(n2663), .B(sub_x_5_B_11_), .Y(n1668) );
NAND2X1TS U1876 ( .A(n2663), .B(DmP_mant_SFG_SWR[14]), .Y(n1727) );
NAND2X4TS U1877 ( .A(n1557), .B(n2734), .Y(n3622) );
NOR2X6TS U1878 ( .A(n2869), .B(n1178), .Y(n1797) );
NOR2X4TS U1879 ( .A(n2870), .B(n1180), .Y(n1806) );
NOR2X6TS U1880 ( .A(n2854), .B(n1151), .Y(n1834) );
NAND2X4TS U1881 ( .A(n2857), .B(n1143), .Y(n1089) );
NOR2X4TS U1882 ( .A(n2853), .B(n1198), .Y(n1857) );
NAND2X6TS U1883 ( .A(n1849), .B(n1871), .Y(n1874) );
NAND2X4TS U1884 ( .A(n982), .B(n968), .Y(n1139) );
NAND3X6TS U1885 ( .A(n1163), .B(n1162), .C(DMP_exp_NRM2_EW[2]), .Y(n1590) );
INVX6TS U1886 ( .A(n1754), .Y(n1755) );
NOR2X6TS U1887 ( .A(n971), .B(n2561), .Y(n1332) );
NOR2X6TS U1888 ( .A(n1637), .B(DMP_SFG[17]), .Y(n2099) );
NOR2X4TS U1889 ( .A(n1110), .B(n1210), .Y(n1750) );
NAND2X4TS U1890 ( .A(n1634), .B(DMP_SFG[21]), .Y(n2072) );
NAND2X2TS U1891 ( .A(n2064), .B(n2469), .Y(n2068) );
NAND2X4TS U1892 ( .A(n1748), .B(n2116), .Y(n1749) );
NAND2X4TS U1893 ( .A(n2842), .B(Raw_mant_NRM_SWR[0]), .Y(n1768) );
INVX2TS U1894 ( .A(n2009), .Y(n2011) );
INVX8TS U1895 ( .A(n2312), .Y(n1607) );
NOR2X2TS U1896 ( .A(n1518), .B(LZD_output_NRM2_EW[4]), .Y(n1717) );
NAND3X4TS U1897 ( .A(n1765), .B(n1763), .C(n1764), .Y(n1578) );
INVX2TS U1898 ( .A(n1024), .Y(n1025) );
OAI21X2TS U1899 ( .A0(n2257), .A1(n2029), .B0(n2028), .Y(n2031) );
INVX2TS U1900 ( .A(n2199), .Y(n2029) );
INVX2TS U1901 ( .A(n2147), .Y(n2019) );
AOI21X2TS U1902 ( .A0(n2576), .A1(n2559), .B0(n2558), .Y(n2564) );
CLKINVX6TS U1903 ( .A(DMP_SFG[18]), .Y(n1128) );
XOR2X2TS U1904 ( .A(n1787), .B(n1786), .Y(n1788) );
NAND2X4TS U1905 ( .A(n2603), .B(n2127), .Y(n2132) );
INVX2TS U1906 ( .A(n1389), .Y(n2232) );
NOR2X4TS U1907 ( .A(n1241), .B(n2634), .Y(n2219) );
INVX2TS U1908 ( .A(n2333), .Y(n1904) );
INVX2TS U1909 ( .A(n2219), .Y(n1364) );
NAND3X2TS U1910 ( .A(n1171), .B(n1599), .C(n1163), .Y(n1598) );
INVX4TS U1911 ( .A(n1712), .Y(n1341) );
NAND2X2TS U1912 ( .A(n1916), .B(n1583), .Y(n1582) );
INVX2TS U1913 ( .A(n2666), .Y(n1583) );
INVX12TS U1914 ( .A(n1082), .Y(n2603) );
NAND2X2TS U1915 ( .A(n1973), .B(n1976), .Y(n1363) );
NAND2X4TS U1916 ( .A(n3202), .B(n3201), .Y(n1455) );
NOR2X1TS U1917 ( .A(n1980), .B(n2652), .Y(n1981) );
INVX2TS U1918 ( .A(n2515), .Y(n2527) );
NAND2X2TS U1919 ( .A(n1391), .B(n1166), .Y(n1528) );
NAND2X2TS U1920 ( .A(n1391), .B(n1202), .Y(n1356) );
NAND2X2TS U1921 ( .A(n1391), .B(n1218), .Y(n1469) );
NAND2X2TS U1922 ( .A(n1229), .B(n1180), .Y(n3398) );
MXI2X2TS U1923 ( .A(n2363), .B(n2822), .S0(n2362), .Y(n843) );
NOR2X2TS U1924 ( .A(n562), .B(n791), .Y(n2744) );
INVX2TS U1925 ( .A(sub_x_5_B_17_), .Y(n2784) );
NOR2X4TS U1926 ( .A(n776), .B(n557), .Y(n2760) );
NAND2X2TS U1927 ( .A(n773), .B(sub_x_5_B_10_), .Y(n2762) );
NAND2X2TS U1928 ( .A(n785), .B(n560), .Y(n2749) );
NOR2X2TS U1929 ( .A(sub_x_5_B_5_), .B(n788), .Y(n2751) );
NOR2X2TS U1930 ( .A(n559), .B(n2896), .Y(n2752) );
MX2X1TS U1931 ( .A(Data_Y[9]), .B(intDY_EWSW[9]), .S0(n1117), .Y(n901) );
NAND2X4TS U1932 ( .A(n1267), .B(n1266), .Y(n3529) );
NAND2X2TS U1933 ( .A(n2598), .B(n1726), .Y(n2423) );
NAND2X4TS U1934 ( .A(n1906), .B(n1905), .Y(n558) );
NAND2X2TS U1935 ( .A(n2407), .B(n1726), .Y(n2412) );
AOI21X1TS U1936 ( .A0(n1706), .A1(n2388), .B0(n1919), .Y(n1920) );
AOI21X1TS U1937 ( .A0(n2416), .A1(n2333), .B0(n1325), .Y(n1324) );
NAND2X4TS U1938 ( .A(n3268), .B(n3267), .Y(n1452) );
INVX3TS U1939 ( .A(rst), .Y(n1238) );
NAND2BX1TS U1940 ( .AN(final_result_ieee[24]), .B(n1644), .Y(n1601) );
INVX2TS U1941 ( .A(n2782), .Y(sub_x_5_B_0_) );
NAND3X2TS U1942 ( .A(n1257), .B(n1405), .C(n1520), .Y(n3655) );
MX2X1TS U1943 ( .A(zero_flag), .B(ZERO_FLAG_SHT1SHT2), .S0(n3312), .Y(n632)
);
NAND2X2TS U1944 ( .A(n1259), .B(n2738), .Y(n3638) );
NAND2X1TS U1945 ( .A(n2647), .B(n2613), .Y(n3382) );
CLKINVX3TS U1946 ( .A(n1244), .Y(n1246) );
AND3X4TS U1947 ( .A(n1108), .B(n1105), .C(n2138), .Y(n1100) );
NAND2X2TS U1948 ( .A(n1381), .B(n3556), .Y(n3533) );
CLKBUFX3TS U1949 ( .A(n1232), .Y(n2336) );
CLKBUFX3TS U1950 ( .A(n3324), .Y(n2940) );
CLKBUFX3TS U1951 ( .A(n1264), .Y(n3344) );
CLKMX2X2TS U1952 ( .A(ZERO_FLAG_NRM), .B(ZERO_FLAG_SFG), .S0(
Shift_reg_FLAGS_7[2]), .Y(n634) );
CLKBUFX3TS U1953 ( .A(n3324), .Y(n2938) );
CLKINVX3TS U1954 ( .A(rst), .Y(n1248) );
CLKMX2X2TS U1955 ( .A(DMP_exp_NRM_EW[5]), .B(DMP_SFG[28]), .S0(
Shift_reg_FLAGS_7[2]), .Y(n702) );
BUFX3TS U1956 ( .A(n3343), .Y(n3317) );
MX2X1TS U1957 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(n1373),
.Y(n716) );
CLKMX2X2TS U1958 ( .A(DMP_exp_NRM_EW[1]), .B(DMP_SFG[24]), .S0(
Shift_reg_FLAGS_7[2]), .Y(n722) );
BUFX3TS U1959 ( .A(n2339), .Y(n3322) );
CLKMX2X2TS U1960 ( .A(DMP_exp_NRM_EW[0]), .B(DMP_SFG[23]), .S0(
Shift_reg_FLAGS_7[2]), .Y(n727) );
BUFX3TS U1961 ( .A(n2339), .Y(n3319) );
BUFX3TS U1962 ( .A(n1235), .Y(n3335) );
CLKINVX3TS U1963 ( .A(n1244), .Y(n1245) );
BUFX3TS U1964 ( .A(n2338), .Y(n3328) );
BUFX3TS U1965 ( .A(n2338), .Y(n3325) );
BUFX3TS U1966 ( .A(n2339), .Y(n3323) );
NOR2X6TS U1967 ( .A(n1537), .B(n2540), .Y(n1548) );
NOR2X6TS U1968 ( .A(n2536), .B(n1537), .Y(n1549) );
NAND2X2TS U1969 ( .A(n1013), .B(n2537), .Y(n3545) );
AOI2BB2X1TS U1970 ( .B0(n2426), .B1(n1242), .A0N(n3541), .A1N(n1491), .Y(
n3543) );
CLKINVX1TS U1971 ( .A(n1576), .Y(n1026) );
NAND2X8TS U1972 ( .A(n1022), .B(n1023), .Y(n1543) );
NOR2X6TS U1973 ( .A(n1135), .B(n1166), .Y(n1023) );
NAND2X4TS U1974 ( .A(n3307), .B(n1406), .Y(n1474) );
CLKINVX12TS U1975 ( .A(n2049), .Y(n1576) );
NOR2X8TS U1976 ( .A(n1096), .B(n2386), .Y(n2387) );
NOR2X8TS U1977 ( .A(n2214), .B(n961), .Y(n2199) );
NAND4X8TS U1978 ( .A(n1755), .B(n1775), .C(n1419), .D(n1756), .Y(n1757) );
NOR2X4TS U1979 ( .A(n1747), .B(n2122), .Y(n2116) );
NOR2X2TS U1980 ( .A(n1032), .B(Raw_mant_NRM_SWR[4]), .Y(n1769) );
NAND2X2TS U1981 ( .A(n1345), .B(n1032), .Y(n2473) );
OAI2BB1X2TS U1982 ( .A0N(n2722), .A1N(n2586), .B0(n2585), .Y(n614) );
NOR2X4TS U1983 ( .A(n2218), .B(n1305), .Y(n2126) );
NAND2X4TS U1984 ( .A(n1297), .B(Raw_mant_NRM_SWR[5]), .Y(n1335) );
NOR2X8TS U1985 ( .A(n1016), .B(n1066), .Y(n1584) );
NAND2X4TS U1986 ( .A(n976), .B(n2048), .Y(n1282) );
NAND4X4TS U1987 ( .A(n1366), .B(n1552), .C(n2048), .D(n1761), .Y(n1442) );
NAND2X6TS U1988 ( .A(n2047), .B(n1758), .Y(n1439) );
NAND4X4TS U1989 ( .A(n1495), .B(n1492), .C(n1494), .D(n1493), .Y(n2425) );
NOR2X8TS U1990 ( .A(Shift_reg_FLAGS_7[0]), .B(n1036), .Y(n1035) );
INVX16TS U1991 ( .A(n1739), .Y(n2663) );
AND2X8TS U1992 ( .A(n1704), .B(n1041), .Y(n1038) );
INVX8TS U1993 ( .A(n1391), .Y(n1255) );
INVX12TS U1994 ( .A(n1170), .Y(n1171) );
AND2X8TS U1995 ( .A(n2387), .B(n1620), .Y(n1039) );
XNOR2X4TS U1996 ( .A(n1407), .B(n1400), .Y(n1040) );
INVX2TS U1997 ( .A(n1575), .Y(n2052) );
INVX8TS U1998 ( .A(shift_value_SHT2_EWR[4]), .Y(n1458) );
NOR2X4TS U1999 ( .A(DMP_SFG[21]), .B(DmP_mant_SFG_SWR[23]), .Y(n2285) );
INVX2TS U2000 ( .A(n2285), .Y(n1489) );
BUFX12TS U2001 ( .A(n2323), .Y(n1352) );
BUFX12TS U2002 ( .A(n2899), .Y(n2569) );
CLKBUFX3TS U2003 ( .A(n3344), .Y(n3324) );
INVX8TS U2004 ( .A(n1990), .Y(n2257) );
BUFX4TS U2005 ( .A(n2583), .Y(n1362) );
NOR2X6TS U2006 ( .A(n2051), .B(n3549), .Y(n2273) );
AO21X4TS U2007 ( .A0(n1768), .A1(n2835), .B0(Raw_mant_NRM_SWR[3]), .Y(n1046)
);
AO21X2TS U2008 ( .A0(n2076), .A1(n2075), .B0(n2074), .Y(n1049) );
AND2X8TS U2009 ( .A(n1582), .B(n1041), .Y(n1050) );
NAND2X4TS U2010 ( .A(add_x_6_A_9_), .B(add_x_6_B_9_), .Y(n1052) );
INVX2TS U2011 ( .A(n2469), .Y(n2470) );
OA21X4TS U2012 ( .A0(n2714), .A1(add_x_6_n194), .B0(n2552), .Y(n1056) );
AND2X8TS U2013 ( .A(n2410), .B(n1261), .Y(n1060) );
AND2X8TS U2014 ( .A(n1121), .B(sub_x_5_B_11_), .Y(n1061) );
OR2X4TS U2015 ( .A(n1406), .B(n1085), .Y(n1062) );
NAND2X4TS U2016 ( .A(n1203), .B(n1211), .Y(n1066) );
NOR2X1TS U2017 ( .A(n2288), .B(n1699), .Y(n1067) );
INVX12TS U2018 ( .A(n2505), .Y(n2653) );
NAND3X6TS U2019 ( .A(n1908), .B(n1907), .C(n972), .Y(n2733) );
INVX12TS U2020 ( .A(n1739), .Y(n2421) );
INVX2TS U2021 ( .A(n2489), .Y(n1511) );
NAND3X6TS U2022 ( .A(n3245), .B(n3244), .C(n3243), .Y(n2490) );
AND2X2TS U2023 ( .A(n2111), .B(n2110), .Y(n1070) );
AND2X2TS U2024 ( .A(n2315), .B(n2314), .Y(n1071) );
OR2X8TS U2025 ( .A(n1641), .B(DMP_SFG[2]), .Y(n1074) );
NOR2X6TS U2026 ( .A(n1631), .B(DMP_SFG[12]), .Y(n2251) );
INVX2TS U2027 ( .A(n2394), .Y(n1567) );
AND2X8TS U2028 ( .A(n1102), .B(n1101), .Y(n1077) );
NAND2X4TS U2029 ( .A(n2317), .B(n1697), .Y(n2288) );
NAND2X4TS U2030 ( .A(DmP_mant_SFG_SWR[22]), .B(DMP_SFG[20]), .Y(n2289) );
INVX2TS U2031 ( .A(n2289), .Y(n1490) );
NAND3X6TS U2032 ( .A(n1628), .B(n1910), .C(n972), .Y(n1081) );
CLKINVX3TS U2033 ( .A(rst), .Y(n1252) );
BUFX3TS U2034 ( .A(n1235), .Y(n3333) );
BUFX3TS U2035 ( .A(n1235), .Y(n3331) );
INVX2TS U2036 ( .A(n1244), .Y(n1236) );
INVX2TS U2037 ( .A(n1244), .Y(n1237) );
INVX2TS U2038 ( .A(n1244), .Y(n1231) );
INVX2TS U2039 ( .A(rst), .Y(n1234) );
INVX2TS U2040 ( .A(rst), .Y(n1233) );
CLKBUFX2TS U2041 ( .A(n2938), .Y(n2945) );
BUFX3TS U2042 ( .A(n3324), .Y(n2939) );
CLKBUFX2TS U2043 ( .A(n2941), .Y(n2944) );
INVX2TS U2044 ( .A(n3344), .Y(n1244) );
CLKINVX3TS U2045 ( .A(rst), .Y(n3681) );
CLKINVX3TS U2046 ( .A(rst), .Y(n1264) );
BUFX12TS U2047 ( .A(n1340), .Y(n1082) );
NOR2X8TS U2048 ( .A(n1084), .B(n1083), .Y(n1610) );
NAND2X4TS U2049 ( .A(n1280), .B(n1722), .Y(n1083) );
NAND2X8TS U2050 ( .A(n1277), .B(n1340), .Y(n1084) );
NAND2X8TS U2051 ( .A(n1579), .B(n1278), .Y(n1340) );
OR2X8TS U2052 ( .A(n2838), .B(LZD_output_NRM2_EW[4]), .Y(n1558) );
OAI21X4TS U2053 ( .A0(n1831), .A1(n1089), .B0(n1088), .Y(n1837) );
AND2X8TS U2054 ( .A(n1168), .B(intDY_EWSW[13]), .Y(n1831) );
OAI2BB1X4TS U2055 ( .A0N(n2413), .A1N(n2600), .B0(n1445), .Y(sub_x_5_B_17_)
);
NAND3X8TS U2056 ( .A(n1055), .B(n1092), .C(n1091), .Y(n1477) );
NOR2X4TS U2057 ( .A(n2857), .B(n1143), .Y(n1093) );
OAI21X4TS U2058 ( .A0(n2786), .A1(n2781), .B0(n2787), .Y(n2785) );
AND2X8TS U2059 ( .A(sub_x_5_B_2_), .B(n1094), .Y(n2781) );
NAND2X8TS U2060 ( .A(n1500), .B(n1501), .Y(sub_x_5_B_2_) );
NAND2X8TS U2061 ( .A(n1095), .B(n2782), .Y(n2786) );
AND2X8TS U2062 ( .A(n1326), .B(n1324), .Y(n2782) );
NAND2X8TS U2063 ( .A(n1930), .B(n1929), .Y(n565) );
BUFX20TS U2064 ( .A(n1274), .Y(n1096) );
NAND2X8TS U2065 ( .A(n1096), .B(n3312), .Y(n2730) );
NOR3X6TS U2066 ( .A(n2380), .B(n1097), .C(n1602), .Y(n1274) );
XNOR2X4TS U2067 ( .A(n1579), .B(n1298), .Y(n2380) );
OR2X8TS U2068 ( .A(n1021), .B(n1099), .Y(n1760) );
NAND2BX4TS U2069 ( .AN(n1147), .B(n1765), .Y(n1099) );
AOI22X4TS U2070 ( .A0(n2464), .A1(n1508), .B0(n2080), .B1(n1199), .Y(n1106)
);
NAND3X8TS U2071 ( .A(n1526), .B(n1525), .C(n2067), .Y(n2137) );
NOR2X4TS U2072 ( .A(n2861), .B(LZD_output_NRM2_EW[3]), .Y(n2128) );
OR2X8TS U2073 ( .A(n1639), .B(sub_x_5_A_13_), .Y(n2246) );
OAI21X2TS U2074 ( .A0(n2250), .A1(n2209), .B0(n2208), .Y(n2213) );
NAND2X6TS U2075 ( .A(n2427), .B(n2424), .Y(n1430) );
NAND2X6TS U2076 ( .A(n1430), .B(n1429), .Y(n1204) );
NAND2X2TS U2077 ( .A(n962), .B(n1198), .Y(n3509) );
NAND2X2TS U2078 ( .A(n962), .B(n1178), .Y(n3450) );
NAND2X2TS U2079 ( .A(n962), .B(intDY_EWSW[3]), .Y(n3405) );
NAND2X2TS U2080 ( .A(n963), .B(intDY_EWSW[14]), .Y(n3372) );
NAND2X2TS U2081 ( .A(n963), .B(intDY_EWSW[22]), .Y(n3348) );
NAND2X2TS U2082 ( .A(n963), .B(intDY_EWSW[25]), .Y(n3441) );
INVX16TS U2083 ( .A(n2732), .Y(n1229) );
NAND2X2TS U2084 ( .A(n1999), .B(n870), .Y(n1659) );
NAND2X2TS U2085 ( .A(n2575), .B(sub_x_5_n190), .Y(n2550) );
CLKINVX6TS U2086 ( .A(sub_x_5_n190), .Y(n1328) );
NAND2X4TS U2087 ( .A(n2036), .B(n2645), .Y(n2345) );
INVX12TS U2088 ( .A(n2732), .Y(n1226) );
BUFX20TS U2089 ( .A(n2725), .Y(n2726) );
NAND3X2TS U2090 ( .A(n2129), .B(n1171), .C(n2128), .Y(n2131) );
OAI2BB1X4TS U2091 ( .A0N(n1540), .A1N(n1067), .B0(n1700), .Y(n1701) );
INVX8TS U2092 ( .A(n981), .Y(n1113) );
INVX8TS U2093 ( .A(n981), .Y(n1114) );
INVX8TS U2094 ( .A(n981), .Y(n1115) );
INVX8TS U2095 ( .A(n981), .Y(n1116) );
CLKINVX12TS U2096 ( .A(n2732), .Y(n1223) );
OAI21X2TS U2097 ( .A0(n2250), .A1(n1304), .B0(n1303), .Y(n1302) );
OAI21X2TS U2098 ( .A0(n2250), .A1(n2021), .B0(n2020), .Y(n2026) );
BUFX20TS U2099 ( .A(n1624), .Y(n1313) );
NAND2X4TS U2100 ( .A(sub_x_5_n244), .B(sub_x_5_A_10_), .Y(n2210) );
OR2X4TS U2101 ( .A(n2521), .B(n2540), .Y(n3471) );
BUFX20TS U2102 ( .A(n2725), .Y(n1169) );
AND2X8TS U2103 ( .A(n982), .B(n968), .Y(n1206) );
AND2X4TS U2104 ( .A(n1624), .B(n2490), .Y(n1124) );
AOI21X4TS U2105 ( .A0(n1607), .A1(n2315), .B0(n2187), .Y(n2189) );
INVX6TS U2106 ( .A(n2188), .Y(n2312) );
NOR2X4TS U2107 ( .A(n1642), .B(DMP_SFG[19]), .Y(n2185) );
NAND3BX4TS U2108 ( .AN(n1126), .B(n2402), .C(n2401), .Y(n543) );
AND2X4TS U2109 ( .A(n2400), .B(n2413), .Y(n1126) );
INVX8TS U2110 ( .A(n2732), .Y(n1224) );
NAND3BX4TS U2111 ( .AN(n1082), .B(n2602), .C(n2127), .Y(n2607) );
NOR2X6TS U2112 ( .A(n2543), .B(n1537), .Y(n1550) );
NAND2X8TS U2113 ( .A(n1131), .B(n1240), .Y(n2311) );
INVX2TS U2114 ( .A(n779), .Y(n1132) );
NOR2BX4TS U2115 ( .AN(n1906), .B(n1133), .Y(n2748) );
NAND2X4TS U2116 ( .A(n1905), .B(n1132), .Y(n1133) );
NAND2X6TS U2117 ( .A(n2551), .B(n1689), .Y(n1361) );
NAND2X8TS U2118 ( .A(n1677), .B(n2174), .Y(n1678) );
AND2X8TS U2119 ( .A(n1270), .B(Shift_reg_FLAGS_7[0]), .Y(n1587) );
INVX12TS U2120 ( .A(n1270), .Y(n1515) );
INVX16TS U2121 ( .A(n1096), .Y(n1270) );
INVX12TS U2122 ( .A(n1276), .Y(n1620) );
INVX6TS U2123 ( .A(n1135), .Y(n1136) );
NAND2X2TS U2124 ( .A(n1039), .B(n2733), .Y(n3656) );
NAND2X2TS U2125 ( .A(n1039), .B(n2735), .Y(n3650) );
NAND2X2TS U2126 ( .A(n1039), .B(n1081), .Y(n3662) );
NAND2X2TS U2127 ( .A(n1039), .B(n1050), .Y(n3671) );
AOI2BB2X4TS U2128 ( .B0(n1271), .B1(n2490), .A0N(n1664), .A1N(n2513), .Y(
n1925) );
NAND2X8TS U2129 ( .A(DmP_mant_SFG_SWR[7]), .B(n1138), .Y(n1137) );
BUFX20TS U2130 ( .A(n2080), .Y(n1271) );
AOI21X4TS U2131 ( .A0(n2080), .A1(n2480), .B0(n1995), .Y(n1997) );
NAND2X6TS U2132 ( .A(n1447), .B(n2710), .Y(n1329) );
NAND2X6TS U2133 ( .A(n1618), .B(n1620), .Y(n1600) );
NAND2X4TS U2134 ( .A(n2863), .B(n1177), .Y(n1808) );
NOR2X6TS U2135 ( .A(n2856), .B(n1183), .Y(n1809) );
OA21X2TS U2136 ( .A0(n1671), .A1(n2208), .B0(n2210), .Y(n1141) );
NAND2X6TS U2137 ( .A(add_x_6_B_4_), .B(add_x_6_A_4_), .Y(n2714) );
NOR2X8TS U2138 ( .A(add_x_6_n120), .B(n2179), .Y(n2158) );
NAND2X4TS U2139 ( .A(n1694), .B(add_x_6_n115), .Y(n1467) );
INVX8TS U2140 ( .A(n2311), .Y(n1413) );
AND2X4TS U2141 ( .A(n2711), .B(n1295), .Y(n1142) );
NAND2X4TS U2142 ( .A(n1641), .B(DMP_SFG[2]), .Y(n2711) );
MXI2X4TS U2143 ( .A(n2818), .B(n2906), .S0(n2665), .Y(n791) );
INVX8TS U2144 ( .A(n1367), .Y(n1716) );
OR2X8TS U2145 ( .A(n1464), .B(n1463), .Y(n1145) );
NOR2X8TS U2146 ( .A(n2255), .B(n1695), .Y(n1464) );
OAI21X1TS U2147 ( .A0(n1299), .A1(add_x_6_n160), .B0(n2776), .Y(n1146) );
OAI21X2TS U2148 ( .A0(n1532), .A1(n1625), .B0(n1586), .Y(n1360) );
OAI21X2TS U2149 ( .A0(n1532), .A1(n2109), .B0(n2108), .Y(n2112) );
OAI21X2TS U2150 ( .A0(n2154), .A1(n1532), .B0(n2155), .Y(n2091) );
OAI21X2TS U2151 ( .A0(n1532), .A1(n2102), .B0(n2101), .Y(n1592) );
AOI22X2TS U2152 ( .A0(n1134), .A1(n2063), .B0(n1271), .B1(n2464), .Y(n1650)
);
BUFX20TS U2153 ( .A(n1726), .Y(n2413) );
AOI2BB2X4TS U2154 ( .B0(n1434), .B1(n2722), .A0N(n1020), .A1N(
Shift_reg_FLAGS_7[2]), .Y(n1374) );
NAND2X4TS U2155 ( .A(n2172), .B(n2722), .Y(n1398) );
XOR2X4TS U2156 ( .A(n2192), .B(n2193), .Y(n2196) );
NOR2X8TS U2157 ( .A(n2175), .B(n1675), .Y(n1677) );
NOR2X8TS U2158 ( .A(n1047), .B(DMP_SFG[13]), .Y(n2175) );
AOI22X2TS U2159 ( .A0(n1313), .A1(n2474), .B0(n1314), .B1(n2454), .Y(n1315)
);
NAND2X4TS U2160 ( .A(n1313), .B(n2488), .Y(n1526) );
BUFX20TS U2161 ( .A(n3308), .Y(n1545) );
NAND4X6TS U2162 ( .A(n1443), .B(n1440), .C(n1439), .D(n1438), .Y(n1156) );
NOR2X4TS U2163 ( .A(n2859), .B(intDX_EWSW[4]), .Y(n1801) );
AOI2BB2X2TS U2164 ( .B0(n1263), .B1(n2519), .A0N(n2441), .A1N(n2491), .Y(
n3579) );
AOI22X2TS U2165 ( .A0(n3313), .A1(n2542), .B0(n2464), .B1(n1243), .Y(n3534)
);
NAND2X4TS U2166 ( .A(n2515), .B(n1414), .Y(n1560) );
AOI2BB2X2TS U2167 ( .B0(n2535), .B1(n1414), .A0N(n1509), .A1N(n2491), .Y(
n3540) );
AOI2BB2X2TS U2168 ( .B0(n1414), .B1(n2548), .A0N(n2470), .A1N(n2491), .Y(
n3511) );
NOR2X4TS U2169 ( .A(n1256), .B(n2530), .Y(n1546) );
NOR2X4TS U2170 ( .A(n1256), .B(n2534), .Y(n1547) );
NAND2X2TS U2171 ( .A(n1229), .B(intDX_EWSW[4]), .Y(n3401) );
NAND2X4TS U2172 ( .A(n2306), .B(n2515), .Y(n1267) );
NAND2X6TS U2173 ( .A(n2144), .B(n1673), .Y(n2197) );
BUFX16TS U2174 ( .A(n2516), .Y(n1414) );
NAND2X6TS U2175 ( .A(n2860), .B(intDX_EWSW[2]), .Y(n1796) );
NAND3X6TS U2176 ( .A(n2057), .B(n2056), .C(n2058), .Y(n1281) );
NAND2X2TS U2177 ( .A(n1540), .B(n2092), .Y(n1535) );
NAND2X4TS U2178 ( .A(n1557), .B(n2735), .Y(n3631) );
NAND2X4TS U2179 ( .A(n1557), .B(n1050), .Y(n3610) );
NAND2X4TS U2180 ( .A(n1557), .B(n1038), .Y(n3613) );
NAND2X4TS U2181 ( .A(n1557), .B(n2596), .Y(n3628) );
AND3X4TS U2182 ( .A(n3019), .B(n3018), .C(n3017), .Y(n1165) );
NAND2X4TS U2183 ( .A(n2859), .B(intDX_EWSW[4]), .Y(n1805) );
AOI2BB2X2TS U2184 ( .B0(n3308), .B1(n2539), .A0N(n2538), .A1N(n1012), .Y(
n3496) );
NAND2X8TS U2185 ( .A(n1836), .B(n1817), .Y(n1839) );
NAND2X6TS U2186 ( .A(shift_value_SHT2_EWR[3]), .B(shift_value_SHT2_EWR[2]),
.Y(n1648) );
OA21X4TS U2187 ( .A0(n2251), .A1(n2244), .B0(n2252), .Y(n1181) );
INVX8TS U2188 ( .A(n1181), .Y(n1377) );
NAND3X8TS U2189 ( .A(n1446), .B(n2559), .C(n1294), .Y(n1293) );
NAND3X8TS U2190 ( .A(n1286), .B(n1284), .C(n1283), .Y(n1478) );
NOR2X6TS U2191 ( .A(n1166), .B(n1135), .Y(n1765) );
OR2X8TS U2192 ( .A(n2526), .B(n2530), .Y(n3546) );
OR2X8TS U2193 ( .A(n2526), .B(n2545), .Y(n3574) );
NOR2X8TS U2194 ( .A(n1987), .B(n2175), .Y(n1988) );
NAND2X6TS U2195 ( .A(n2188), .B(n2070), .Y(n1269) );
NAND4BX2TS U2196 ( .AN(n2273), .B(n2233), .C(n2232), .D(n2231), .Y(n2234) );
NOR2X4TS U2197 ( .A(n2234), .B(n2235), .Y(n2236) );
OR3X8TS U2198 ( .A(n1192), .B(n1193), .C(n1194), .Y(n2645) );
NOR2X2TS U2199 ( .A(n2298), .B(n1281), .Y(n2299) );
OR2X8TS U2200 ( .A(n1448), .B(n1196), .Y(n2597) );
OAI2BB1X1TS U2201 ( .A0N(n1046), .A1N(n2893), .B0(n2045), .Y(n2046) );
AOI2BB2X4TS U2202 ( .B0(n3557), .B1(n3308), .A0N(n1537), .A1N(n2527), .Y(
n3560) );
NOR2X4TS U2203 ( .A(n2138), .B(n1384), .Y(n2372) );
NAND2X2TS U2204 ( .A(n1368), .B(n2514), .Y(n3542) );
NAND2X4TS U2205 ( .A(n2054), .B(n2053), .Y(n2055) );
NOR2X4TS U2206 ( .A(n1847), .B(n1866), .Y(n1849) );
NAND2X4TS U2207 ( .A(n1487), .B(n1540), .Y(n1486) );
OAI2BB1X2TS U2208 ( .A0N(n2317), .A1N(n999), .B0(n1186), .Y(n2098) );
NAND2X6TS U2209 ( .A(n2597), .B(n2330), .Y(n2002) );
NOR2X4TS U2210 ( .A(n1514), .B(n1977), .Y(n638) );
OAI21X2TS U2211 ( .A0(n1411), .A1(SIGN_FLAG_SHT1SHT2), .B0(n1514), .Y(n3680)
);
NAND2X2TS U2212 ( .A(n2274), .B(n2275), .Y(n2276) );
BUFX4TS U2213 ( .A(n2047), .Y(n1389) );
NAND3X2TS U2214 ( .A(n1247), .B(n1983), .C(n1979), .Y(n3679) );
NAND3X4TS U2215 ( .A(n1031), .B(n2052), .C(n1215), .Y(n2053) );
NAND2X4TS U2216 ( .A(n1560), .B(n2518), .Y(n876) );
INVX12TS U2217 ( .A(n2492), .Y(n2475) );
CLKINVX12TS U2218 ( .A(Raw_mant_NRM_SWR[22]), .Y(n2492) );
NAND3X2TS U2219 ( .A(n2266), .B(n1129), .C(n2265), .Y(n2054) );
NAND2X4TS U2220 ( .A(n1916), .B(n2450), .Y(n1908) );
NAND3X6TS U2221 ( .A(n3257), .B(n3256), .C(n3255), .Y(n2480) );
BUFX12TS U2222 ( .A(n2516), .Y(n1263) );
BUFX12TS U2223 ( .A(n2516), .Y(n3313) );
NAND2X2TS U2224 ( .A(n1229), .B(intDY_EWSW[24]), .Y(n3431) );
NAND2X2TS U2225 ( .A(n1223), .B(intDY_EWSW[22]), .Y(n3527) );
NAND2X2TS U2226 ( .A(n1223), .B(intDY_EWSW[20]), .Y(n3513) );
NAND2X2TS U2227 ( .A(n1228), .B(intDY_EWSW[15]), .Y(n3502) );
NAND2X2TS U2228 ( .A(n1224), .B(intDY_EWSW[19]), .Y(n3516) );
NAND2X2TS U2229 ( .A(n1224), .B(intDY_EWSW[9]), .Y(n3493) );
NAND2X2TS U2230 ( .A(n1224), .B(intDY_EWSW[11]), .Y(n3463) );
NAND2X2TS U2231 ( .A(n1224), .B(intDY_EWSW[12]), .Y(n3460) );
NAND2X2TS U2232 ( .A(n1223), .B(intDX_EWSW[8]), .Y(n3389) );
NAND2X2TS U2233 ( .A(n1223), .B(n1143), .Y(n3377) );
NAND2X2TS U2234 ( .A(n1223), .B(intDX_EWSW[0]), .Y(n3413) );
NAND2X2TS U2235 ( .A(n1224), .B(intDX_EWSW[30]), .Y(n3601) );
NAND2X2TS U2236 ( .A(n1227), .B(intDY_EWSW[5]), .Y(n3455) );
INVX16TS U2237 ( .A(n2732), .Y(n1227) );
INVX16TS U2238 ( .A(n2732), .Y(n1225) );
INVX16TS U2239 ( .A(n2731), .Y(n2732) );
NAND2X2TS U2240 ( .A(n1229), .B(intDX_EWSW[13]), .Y(n3374) );
NAND2X2TS U2241 ( .A(n1226), .B(n1157), .Y(n3350) );
NAND2X2TS U2242 ( .A(n1229), .B(n1149), .Y(n3416) );
NAND2X2TS U2243 ( .A(n2726), .B(intDY_EWSW[10]), .Y(n3384) );
NAND2X2TS U2244 ( .A(n2726), .B(n1183), .Y(n3488) );
NAND2X2TS U2245 ( .A(n2726), .B(n1157), .Y(n3523) );
NAND2X2TS U2246 ( .A(n963), .B(intDX_EWSW[10]), .Y(n3467) );
NAND2X2TS U2247 ( .A(n963), .B(n1155), .Y(n3426) );
NAND2X2TS U2248 ( .A(n2729), .B(n1150), .Y(n3514) );
NAND2X2TS U2249 ( .A(n1169), .B(intDX_EWSW[9]), .Y(n3494) );
NAND2X2TS U2250 ( .A(n962), .B(n1180), .Y(n3456) );
NAND2X2TS U2251 ( .A(n1247), .B(intDX_EWSW[13]), .Y(n3470) );
NAND2X2TS U2252 ( .A(n1247), .B(n959), .Y(n3453) );
NAND2X2TS U2253 ( .A(n962), .B(n1177), .Y(n3491) );
NAND2X2TS U2254 ( .A(n2727), .B(intDX_EWSW[8]), .Y(n3485) );
NAND2X2TS U2255 ( .A(n1223), .B(n1191), .Y(n3359) );
NAND2X2TS U2256 ( .A(n1224), .B(n1151), .Y(n3368) );
NAND2X2TS U2257 ( .A(n1223), .B(n1158), .Y(n3437) );
NAND2X2TS U2258 ( .A(n1223), .B(intDX_EWSW[10]), .Y(n3383) );
NAND2X2TS U2259 ( .A(n1224), .B(n1155), .Y(n3422) );
INVX2TS U2260 ( .A(n1244), .Y(n1232) );
INVX2TS U2261 ( .A(n1244), .Y(n1235) );
BUFX3TS U2262 ( .A(n1235), .Y(n3332) );
BUFX3TS U2263 ( .A(n1235), .Y(n3334) );
NAND2X2TS U2264 ( .A(n962), .B(n1191), .Y(n3520) );
CLKBUFX3TS U2265 ( .A(n3343), .Y(n3315) );
INVX3TS U2266 ( .A(rst), .Y(n1239) );
BUFX20TS U2267 ( .A(n2725), .Y(n1247) );
CLKINVX3TS U2268 ( .A(rst), .Y(n1249) );
BUFX3TS U2269 ( .A(n1235), .Y(n1250) );
BUFX3TS U2270 ( .A(n1235), .Y(n1251) );
BUFX3TS U2271 ( .A(n1235), .Y(n3330) );
INVX2TS U2272 ( .A(n1244), .Y(n1253) );
INVX2TS U2273 ( .A(rst), .Y(n1254) );
OR2X4TS U2274 ( .A(n2521), .B(n3569), .Y(n3495) );
BUFX20TS U2275 ( .A(n3310), .Y(n1256) );
NOR2X4TS U2276 ( .A(n2532), .B(n1012), .Y(n1551) );
AOI2BB2X4TS U2277 ( .B0(n1368), .B1(n2529), .A0N(n1256), .A1N(n2528), .Y(
n3539) );
NAND3X2TS U2278 ( .A(n1405), .B(n2737), .C(n2407), .Y(n3673) );
NAND3X2TS U2279 ( .A(n1514), .B(n2737), .C(n2573), .Y(n3637) );
NAND3X2TS U2280 ( .A(n1405), .B(n2737), .C(n2598), .Y(n3649) );
NAND3X2TS U2281 ( .A(n1405), .B(n2737), .C(n2597), .Y(n3634) );
INVX16TS U2282 ( .A(n1513), .Y(n2737) );
NAND2X4TS U2283 ( .A(n1916), .B(n2310), .Y(n1898) );
NAND2X4TS U2284 ( .A(n1916), .B(n2459), .Y(n1910) );
NAND2X2TS U2285 ( .A(n1368), .B(n2519), .Y(n3480) );
INVX12TS U2286 ( .A(n1600), .Y(n1259) );
NAND2X2TS U2287 ( .A(n2601), .B(n2588), .Y(n3635) );
NAND2X2TS U2288 ( .A(n2601), .B(n2573), .Y(n3644) );
NAND2X2TS U2289 ( .A(n2601), .B(n2736), .Y(n3620) );
NAND2X2TS U2290 ( .A(n2601), .B(n973), .Y(n3614) );
NAND2X2TS U2291 ( .A(n2601), .B(n2400), .Y(n3611) );
NAND2X2TS U2292 ( .A(n2601), .B(n2587), .Y(n3617) );
INVX12TS U2293 ( .A(n1600), .Y(n2601) );
NAND2X2TS U2294 ( .A(n2588), .B(n2330), .Y(n2328) );
NAND2X4TS U2295 ( .A(n1050), .B(n1261), .Y(n1725) );
NOR2X4TS U2296 ( .A(n1424), .B(n1148), .Y(n2241) );
MXI2X4TS U2297 ( .A(n2799), .B(n1203), .S0(n1424), .Y(n2309) );
AOI22X2TS U2298 ( .A0(n3313), .A1(n2537), .B0(n1241), .B1(n2484), .Y(n3458)
);
AOI2BB2X2TS U2299 ( .B0(n3594), .B1(n1414), .A0N(n2433), .A1N(n2491), .Y(
n3537) );
MXI2X4TS U2300 ( .A(n2808), .B(n2886), .S0(n2663), .Y(n749) );
AOI2BB1X4TS U2301 ( .A0N(n1904), .A1N(n1342), .B0(n1903), .Y(n1905) );
INVX16TS U2302 ( .A(n2306), .Y(n2526) );
NAND2X4TS U2303 ( .A(n1458), .B(left_right_SHT2), .Y(n2004) );
NOR2X6TS U2304 ( .A(n1794), .B(n1797), .Y(n1799) );
XOR2X4TS U2305 ( .A(n1701), .B(n1076), .Y(n1702) );
BUFX6TS U2306 ( .A(intDX_EWSW[25]), .Y(n1268) );
INVX2TS U2307 ( .A(n1031), .Y(n1432) );
NAND2X4TS U2308 ( .A(n2869), .B(n1178), .Y(n1795) );
NAND2X8TS U2309 ( .A(n1058), .B(n2583), .Y(n1465) );
NAND2X8TS U2310 ( .A(n1361), .B(n1056), .Y(n2583) );
CLKINVX12TS U2311 ( .A(n1543), .Y(n1575) );
NAND2X4TS U2312 ( .A(n2846), .B(n1205), .Y(n1791) );
NAND4X8TS U2313 ( .A(n2275), .B(n2058), .C(n1335), .D(n1336), .Y(n2427) );
NOR2X8TS U2314 ( .A(n1333), .B(n1334), .Y(n2275) );
NAND2X6TS U2315 ( .A(add_x_6_A_2_), .B(DmP_mant_SFG_SWR[2]), .Y(n2704) );
MXI2X4TS U2316 ( .A(n2236), .B(n2840), .S0(n2653), .Y(n591) );
AOI21X4TS U2317 ( .A0(n2283), .A1(n1685), .B0(n1684), .Y(n1686) );
NAND2X8TS U2318 ( .A(n1682), .B(n1269), .Y(n2283) );
NOR2X8TS U2319 ( .A(n988), .B(n1144), .Y(n1310) );
NOR2X6TS U2320 ( .A(n1176), .B(DMP_SFG[16]), .Y(n2087) );
BUFX20TS U2321 ( .A(n3308), .Y(n1368) );
NAND4X2TS U2322 ( .A(n1946), .B(n1945), .C(n1944), .D(n1943), .Y(n1952) );
NAND2X8TS U2323 ( .A(n1757), .B(n1272), .Y(n2047) );
NAND4X8TS U2324 ( .A(n1574), .B(n1576), .C(n1577), .D(n1750), .Y(n1272) );
AOI22X4TS U2325 ( .A0(n1016), .A1(n2424), .B0(n2517), .B1(
Raw_mant_NRM_SWR[1]), .Y(n3541) );
NOR2X2TS U2326 ( .A(n1962), .B(n1961), .Y(n1974) );
MXI2X2TS U2327 ( .A(n2142), .B(final_result_ieee[28]), .S0(n1710), .Y(n2143)
);
AOI21X4TS U2328 ( .A0(n2080), .A1(n2666), .B0(n1995), .Y(n1662) );
OAI22X2TS U2329 ( .A0(n2506), .A1(n1211), .B0(n2505), .B1(n2877), .Y(n2238)
);
NOR2X8TS U2330 ( .A(n1809), .B(n1802), .Y(n1811) );
NAND2X8TS U2331 ( .A(n1042), .B(n1053), .Y(n1524) );
NAND3X8TS U2332 ( .A(n976), .B(n1031), .C(n2044), .Y(n1542) );
NAND2X2TS U2333 ( .A(n1624), .B(n2440), .Y(n1931) );
NOR2X8TS U2334 ( .A(n1275), .B(n1273), .Y(n1480) );
NAND2X8TS U2335 ( .A(n982), .B(n968), .Y(n1273) );
NOR2X8TS U2336 ( .A(n1346), .B(n1612), .Y(n1276) );
NOR2X8TS U2337 ( .A(n2140), .B(n1522), .Y(n1722) );
NAND2X4TS U2338 ( .A(DMP_exp_NRM2_EW[6]), .B(n1171), .Y(n2605) );
NAND2X4TS U2339 ( .A(n1518), .B(n2834), .Y(n2127) );
NOR2X8TS U2340 ( .A(n1572), .B(n1279), .Y(n1278) );
NOR2X8TS U2341 ( .A(LZD_output_NRM2_EW[1]), .B(n1170), .Y(n1711) );
NOR2X8TS U2342 ( .A(n1282), .B(n1432), .Y(n2115) );
INVX16TS U2343 ( .A(n1478), .Y(n1532) );
AOI21X4TS U2344 ( .A0(n1377), .A1(n1677), .B0(n1676), .Y(n1283) );
NAND2X8TS U2345 ( .A(n1986), .B(n1285), .Y(n1284) );
NOR2X8TS U2346 ( .A(n1678), .B(n2197), .Y(n1285) );
NAND3X8TS U2347 ( .A(n1293), .B(n1291), .C(n1330), .Y(n1986) );
AND2X8TS U2348 ( .A(n1673), .B(n2145), .Y(n1288) );
INVX16TS U2349 ( .A(n1289), .Y(n2174) );
NAND2X8TS U2350 ( .A(n2246), .B(n1290), .Y(n1289) );
NAND2X8TS U2351 ( .A(n1292), .B(n2578), .Y(n2558) );
NAND2X8TS U2352 ( .A(n1172), .B(n1328), .Y(n1292) );
NOR2X8TS U2353 ( .A(n971), .B(n2560), .Y(n1294) );
NOR2X8TS U2354 ( .A(n2549), .B(n2577), .Y(n2559) );
NAND2X8TS U2355 ( .A(n1295), .B(n2711), .Y(n1446) );
NAND2X8TS U2356 ( .A(n1329), .B(n1074), .Y(n1295) );
OAI21X4TS U2357 ( .A0(n2250), .A1(n2146), .B0(n1141), .Y(n1296) );
NAND2X8TS U2358 ( .A(n1527), .B(n1716), .Y(n1298) );
CLKINVX1TS U2359 ( .A(n961), .Y(n2150) );
OAI21X4TS U2360 ( .A0(n1299), .A1(add_x_6_n160), .B0(n2776), .Y(n2027) );
NOR2X8TS U2361 ( .A(add_x_6_A_11_), .B(add_x_6_B_11_), .Y(n1299) );
NOR2X8TS U2362 ( .A(n1468), .B(n1417), .Y(n2255) );
NOR2X8TS U2363 ( .A(n2022), .B(n1061), .Y(n1673) );
NOR2X8TS U2364 ( .A(n1638), .B(DMP_SFG[10]), .Y(n2022) );
XNOR2X4TS U2365 ( .A(n1302), .B(n2178), .Y(n1301) );
OAI21X4TS U2366 ( .A0(Raw_mant_NRM_SWR[1]), .A1(Raw_mant_NRM_SWR[0]), .B0(
n2115), .Y(n1306) );
AND2X8TS U2367 ( .A(n2233), .B(n1160), .Y(n1307) );
NOR2X8TS U2368 ( .A(n1309), .B(n1308), .Y(n2233) );
XNOR2X4TS U2369 ( .A(n1431), .B(n1714), .Y(n1311) );
AOI22X2TS U2370 ( .A0(n3313), .A1(n3564), .B0(n1241), .B1(n2459), .Y(n3525)
);
NAND3X8TS U2371 ( .A(n1584), .B(n1771), .C(n2226), .Y(n1312) );
NOR2X8TS U2372 ( .A(n1433), .B(n1312), .Y(n1563) );
NAND3X8TS U2373 ( .A(n1316), .B(n975), .C(n1315), .Y(n2599) );
NAND3BX4TS U2374 ( .AN(n1059), .B(n3216), .C(n3215), .Y(n2454) );
NOR2X8TS U2375 ( .A(DMP_SFG[15]), .B(DmP_mant_SFG_SWR[17]), .Y(n2166) );
OAI2BB1X4TS U2376 ( .A0N(n2330), .A1N(n2736), .B0(n2334), .Y(sub_x_5_B_5_)
);
NOR2BX4TS U2377 ( .AN(n2081), .B(n1318), .Y(n1317) );
NAND2X4TS U2378 ( .A(n974), .B(n2083), .Y(n1318) );
OAI21X4TS U2379 ( .A0(n2750), .A1(n2745), .B0(n2758), .Y(n2757) );
NAND2X4TS U2380 ( .A(n547), .B(n746), .Y(n2758) );
NOR2X6TS U2381 ( .A(n547), .B(n746), .Y(n2745) );
NAND2X8TS U2382 ( .A(n1320), .B(n1319), .Y(n547) );
OAI2BB1X4TS U2383 ( .A0N(DmP_mant_SFG_SWR[0]), .A1N(n2408), .B0(n2331), .Y(
n1325) );
NAND2X8TS U2384 ( .A(n2383), .B(n1037), .Y(n2331) );
NOR2X8TS U2385 ( .A(n2663), .B(n2004), .Y(n2333) );
OAI2BB1X4TS U2386 ( .A0N(n2323), .A1N(n1349), .B0(n1591), .Y(n600) );
NAND2X4TS U2387 ( .A(n1636), .B(DMP_SFG[4]), .Y(n2578) );
OR2X8TS U2388 ( .A(n2298), .B(n1389), .Y(n1334) );
AOI2BB2X4TS U2389 ( .B0(n2115), .B1(Raw_mant_NRM_SWR[3]), .A0N(n1026), .A1N(
n2050), .Y(n1336) );
NAND2X4TS U2390 ( .A(n1893), .B(n1854), .Y(n1896) );
NOR2X4TS U2391 ( .A(n2847), .B(intDX_EWSW[28]), .Y(n1844) );
NOR2X8TS U2392 ( .A(n1816), .B(n1834), .Y(n1836) );
NAND3X6TS U2393 ( .A(n2132), .B(n2606), .C(n2604), .Y(n2133) );
MXI2X4TS U2394 ( .A(n2134), .B(final_result_ieee[29]), .S0(n1710), .Y(n2135)
);
NAND2X1TS U2395 ( .A(n2306), .B(n3564), .Y(n3584) );
NAND2X8TS U2396 ( .A(n1171), .B(n2128), .Y(n1527) );
AOI2BB2X4TS U2397 ( .B0(n1368), .B1(n2548), .A0N(n1012), .A1N(n2547), .Y(
n3575) );
NAND3X4TS U2398 ( .A(n3266), .B(n3265), .C(n3264), .Y(n2437) );
AOI22X2TS U2399 ( .A0(n1414), .A1(n3590), .B0(n1134), .B1(n1243), .Y(n3532)
);
AOI22X2TS U2400 ( .A0(n3313), .A1(n3570), .B0(n1241), .B1(n2437), .Y(n3497)
);
OAI21X4TS U2401 ( .A0(n2747), .A1(n2746), .B0(n2755), .Y(n2754) );
NOR2X6TS U2402 ( .A(n551), .B(n758), .Y(n2746) );
INVX16TS U2403 ( .A(n1412), .Y(n2306) );
CLKINVX12TS U2404 ( .A(n1536), .Y(n1539) );
NAND2X4TS U2405 ( .A(n1829), .B(n1820), .Y(n1821) );
NAND2X4TS U2406 ( .A(n2070), .B(n2075), .Y(n2077) );
NAND2X2TS U2407 ( .A(n2461), .B(n2460), .Y(n2463) );
BUFX16TS U2408 ( .A(n2838), .Y(n1344) );
NOR2X8TS U2409 ( .A(n1208), .B(n2122), .Y(n2044) );
NAND3X8TS U2410 ( .A(n1610), .B(n1608), .C(n1571), .Y(n1346) );
NAND2X8TS U2411 ( .A(n1365), .B(n2003), .Y(n551) );
NAND2X2TS U2412 ( .A(n2416), .B(n1261), .Y(n1652) );
BUFX6TS U2413 ( .A(n565), .Y(n1347) );
NOR2X6TS U2414 ( .A(n2161), .B(n2166), .Y(n1694) );
NAND2X6TS U2415 ( .A(add_x_6_A_12_), .B(add_x_6_B_12_), .Y(n2200) );
NOR2X4TS U2416 ( .A(n1096), .B(n2373), .Y(n2374) );
AOI21X2TS U2417 ( .A0(n1382), .A1(n2408), .B0(n1932), .Y(n1934) );
AND3X8TS U2418 ( .A(n1219), .B(n1148), .C(n1129), .Y(n1751) );
XOR2X4TS U2419 ( .A(n1688), .B(n1351), .Y(n1350) );
NAND2X6TS U2420 ( .A(n1632), .B(sub_x_5_A_11_), .Y(n2147) );
XOR2X4TS U2421 ( .A(n2112), .B(n1070), .Y(n2114) );
XOR2X4TS U2422 ( .A(n2316), .B(n1071), .Y(n2322) );
OAI21X4TS U2423 ( .A0(n988), .A1(n1572), .B0(n1527), .Y(n2375) );
NAND4X6TS U2424 ( .A(n1660), .B(n1661), .C(n1662), .D(n1659), .Y(n2738) );
NOR2X4TS U2425 ( .A(intDX_EWSW[2]), .B(n2860), .Y(n1794) );
OAI21X4TS U2426 ( .A0(n1833), .A1(n1834), .B0(n1832), .Y(n1835) );
OAI2BB1X2TS U2427 ( .A0N(n2722), .A1N(n2708), .B0(n2707), .Y(n617) );
OAI2BB1X2TS U2428 ( .A0N(n2722), .A1N(n2721), .B0(n2720), .Y(n616) );
AOI22X4TS U2429 ( .A0(n2261), .A1(n1265), .B0(n2717), .B1(n1029), .Y(n2262)
);
AOI22X4TS U2430 ( .A0(n1561), .A1(n1265), .B0(n2717), .B1(n1152), .Y(n2206)
);
AOI2BB2X4TS U2431 ( .B0(n1533), .B1(n1265), .A0N(n1019), .A1N(n1255), .Y(
n2152) );
XOR2X4TS U2432 ( .A(n1355), .B(n1415), .Y(n1354) );
NAND2BX4TS U2433 ( .AN(n2800), .B(n1255), .Y(n1358) );
XOR2X4TS U2434 ( .A(n1360), .B(DmP_mant_SFG_SWR[25]), .Y(n1359) );
NAND2X2TS U2435 ( .A(n2064), .B(n2503), .Y(n1660) );
OAI21X4TS U2436 ( .A0(n2155), .A1(n2087), .B0(n2088), .Y(n2107) );
XOR2X4TS U2437 ( .A(n1472), .B(n1072), .Y(n1471) );
AND2X8TS U2438 ( .A(n2002), .B(n2001), .Y(n1365) );
INVX16TS U2439 ( .A(n1999), .Y(n1664) );
NOR2X2TS U2440 ( .A(n1718), .B(n1162), .Y(n1719) );
AOI22X2TS U2441 ( .A0(n2063), .A1(n2488), .B0(n1271), .B1(n2469), .Y(n1915)
);
INVX16TS U2442 ( .A(n1524), .Y(n1916) );
NAND2X2TS U2443 ( .A(n2123), .B(n2122), .Y(n2125) );
AOI22X4TS U2444 ( .A0(n2094), .A1(n2718), .B0(n1214), .B1(n2569), .Y(n2095)
);
BUFX6TS U2445 ( .A(n1671), .Y(n1369) );
BUFX20TS U2446 ( .A(n1140), .Y(n2729) );
NOR2X4TS U2447 ( .A(n2643), .B(n2035), .Y(n2346) );
NOR2X6TS U2448 ( .A(n2866), .B(n1195), .Y(n1885) );
AOI2BB2X4TS U2449 ( .B0(n2105), .B1(n2295), .A0N(n1211), .A1N(n1255), .Y(
n1591) );
NOR2X8TS U2450 ( .A(n1902), .B(n1375), .Y(n2595) );
NAND2X8TS U2451 ( .A(n1647), .B(n1378), .Y(n2464) );
NOR2BX4TS U2452 ( .AN(n3200), .B(n1043), .Y(n1378) );
BUFX8TS U2453 ( .A(n2507), .Y(n1388) );
XOR2X4TS U2454 ( .A(n1379), .B(n2320), .Y(n2321) );
OAI2BB1X4TS U2455 ( .A0N(n1054), .A1N(n1575), .B0(n1749), .Y(n1553) );
OR2X8TS U2456 ( .A(n1923), .B(n2652), .Y(n1380) );
INVX16TS U2457 ( .A(n1538), .Y(n3308) );
NAND2X2TS U2458 ( .A(n1174), .B(n2065), .Y(n1628) );
NAND4X2TS U2459 ( .A(n1948), .B(n1949), .C(n1950), .D(n1947), .Y(n1951) );
CLKBUFX2TS U2460 ( .A(DmP_mant_SFG_SWR[2]), .Y(n1382) );
OAI2BB1X4TS U2461 ( .A0N(n1260), .A1N(n2587), .B0(n1922), .Y(n562) );
NAND3X4TS U2462 ( .A(n3263), .B(n3262), .C(n3261), .Y(n2488) );
NOR2X8TS U2463 ( .A(n1848), .B(n1869), .Y(n1871) );
NOR2X4TS U2464 ( .A(n545), .B(n740), .Y(n2753) );
NAND2X8TS U2465 ( .A(n1570), .B(n1990), .Y(n1462) );
NAND2X8TS U2466 ( .A(n1465), .B(n1466), .Y(n1990) );
NAND2X8TS U2467 ( .A(n1518), .B(n1344), .Y(n1559) );
NAND2X2TS U2468 ( .A(n2866), .B(n1195), .Y(n1883) );
AOI21X4TS U2469 ( .A0(n1830), .A1(n1829), .B0(n1828), .Y(n1840) );
NAND2X4TS U2470 ( .A(n2858), .B(intDX_EWSW[8]), .Y(n1823) );
AOI21X4TS U2471 ( .A0(n2137), .A1(n1384), .B0(n1995), .Y(n1385) );
AOI21X4TS U2472 ( .A0(n1691), .A1(n2009), .B0(n1690), .Y(n1466) );
BUFX16TS U2473 ( .A(n1207), .Y(n2505) );
NOR2X2TS U2474 ( .A(n2644), .B(n2039), .Y(n2358) );
NAND3X2TS U2475 ( .A(n3219), .B(n3218), .C(n3217), .Y(n2432) );
AOI22X2TS U2476 ( .A0(n1314), .A1(n2432), .B0(n1313), .B1(n2426), .Y(n1924)
);
NOR2X8TS U2477 ( .A(sub_x_5_n244), .B(sub_x_5_A_10_), .Y(n1671) );
NOR2X4TS U2478 ( .A(n2846), .B(n1205), .Y(n1793) );
AND2X8TS U2479 ( .A(n2848), .B(n1174), .Y(n2064) );
AND2X4TS U2480 ( .A(n1732), .B(n1731), .Y(n1519) );
OAI2BB1X4TS U2481 ( .A0N(DmP_mant_SFG_SWR[19]), .A1N(n1230), .B0(n2420), .Y(
n1709) );
NOR2X4TS U2482 ( .A(n2845), .B(n1154), .Y(n1816) );
NAND3X4TS U2483 ( .A(n3016), .B(n3015), .C(n3014), .Y(n2643) );
XNOR2X4TS U2484 ( .A(n1392), .B(n2184), .Y(n1530) );
NAND2X8TS U2485 ( .A(n1715), .B(n1206), .Y(n1609) );
OAI2BB1X4TS U2486 ( .A0N(n2282), .A1N(n1201), .B0(n2284), .Y(n2287) );
AND2X8TS U2487 ( .A(n1163), .B(n1711), .Y(n1483) );
OAI21X4TS U2488 ( .A0(n1826), .A1(n1827), .B0(n1825), .Y(n1828) );
OAI21X2TS U2489 ( .A0(n2011), .A1(add_x_6_n172), .B0(n2010), .Y(n2012) );
XOR2X4TS U2490 ( .A(n2015), .B(n2014), .Y(n2016) );
NAND2X4TS U2491 ( .A(n1112), .B(n1931), .Y(n1503) );
NAND2X2TS U2492 ( .A(n2856), .B(n1183), .Y(n1807) );
OAI21X4TS U2493 ( .A0(n1809), .A1(n1808), .B0(n1807), .Y(n1810) );
NAND2X2TS U2494 ( .A(n1174), .B(n2666), .Y(n1707) );
NAND3X8TS U2495 ( .A(n1708), .B(n1707), .C(n972), .Y(n2734) );
NOR2X6TS U2496 ( .A(n1846), .B(n1890), .Y(n1893) );
NOR2X8TS U2497 ( .A(n1844), .B(n1885), .Y(n1845) );
NAND2X2TS U2498 ( .A(n2870), .B(n1180), .Y(n1804) );
NAND3X2TS U2499 ( .A(n1621), .B(n2439), .C(n2438), .Y(n2519) );
BUFX6TS U2500 ( .A(LZD_output_NRM2_EW[2]), .Y(n1406) );
NAND3X2TS U2501 ( .A(n2737), .B(n1514), .C(n2736), .Y(n3661) );
OAI21X4TS U2502 ( .A0(n1719), .A1(n1720), .B0(n1598), .Y(n1407) );
OR2X8TS U2503 ( .A(n2589), .B(n2526), .Y(n3595) );
NOR2X2TS U2504 ( .A(n1170), .B(LZD_output_NRM2_EW[0]), .Y(n1718) );
MXI2X2TS U2505 ( .A(n2351), .B(n2823), .S0(n2362), .Y(n844) );
BUFX20TS U2506 ( .A(n2425), .Y(n1491) );
MXI2X2TS U2507 ( .A(n2348), .B(n2824), .S0(n2362), .Y(n845) );
NAND2X8TS U2508 ( .A(n1408), .B(n1055), .Y(n1475) );
AOI21X4TS U2509 ( .A0(n1837), .A1(n1836), .B0(n1835), .Y(n1838) );
NAND3X4TS U2510 ( .A(n3260), .B(n3259), .C(n3258), .Y(n2502) );
AOI21X4TS U2511 ( .A0(n1894), .A1(n1893), .B0(n1892), .Y(n1895) );
NAND3X4TS U2512 ( .A(n3248), .B(n3247), .C(n3246), .Y(n2489) );
NOR2X4TS U2513 ( .A(n1874), .B(n1853), .Y(n1854) );
AOI22X2TS U2514 ( .A0(n1263), .A1(n2541), .B0(n1241), .B1(n2488), .Y(n3473)
);
AOI22X2TS U2515 ( .A0(n1263), .A1(n2546), .B0(n1243), .B1(n2502), .Y(n3576)
);
NAND2X4TS U2516 ( .A(n2598), .B(n1260), .Y(n1658) );
AOI21X4TS U2517 ( .A0(n2410), .A1(n2333), .B0(n1928), .Y(n1929) );
NOR2X8TS U2518 ( .A(n1416), .B(n1696), .Y(n2394) );
AND2X8TS U2519 ( .A(n1697), .B(n1185), .Y(n1416) );
NAND2X2TS U2520 ( .A(n2855), .B(n1187), .Y(n1825) );
NAND2X2TS U2521 ( .A(n2850), .B(n1149), .Y(n1877) );
NAND2X2TS U2522 ( .A(n2847), .B(intDX_EWSW[28]), .Y(n1884) );
OAI2BB1X4TS U2523 ( .A0N(n2413), .A1N(n2587), .B0(n1920), .Y(n545) );
NAND2X4TS U2524 ( .A(n551), .B(n758), .Y(n2755) );
NAND2X2TS U2525 ( .A(n2854), .B(n1151), .Y(n1832) );
NAND2X2TS U2526 ( .A(n2852), .B(n1157), .Y(n1864) );
OAI21X4TS U2527 ( .A0(n1866), .A1(n1865), .B0(n1864), .Y(n1872) );
NOR2X4TS U2528 ( .A(n2844), .B(n1184), .Y(n1848) );
NAND2X2TS U2529 ( .A(n2867), .B(intDX_EWSW[19]), .Y(n1858) );
OAI21X4TS U2530 ( .A0(n1860), .A1(n1859), .B0(n1858), .Y(n1861) );
NAND2X2TS U2531 ( .A(n2851), .B(n1158), .Y(n1867) );
XOR2X4TS U2532 ( .A(n2294), .B(n2293), .Y(n2296) );
NAND2X8TS U2533 ( .A(n1462), .B(n1566), .Y(n1540) );
NAND2X8TS U2534 ( .A(n1614), .B(n1539), .Y(n1538) );
NOR2X8TS U2535 ( .A(DMP_SFG[1]), .B(n1123), .Y(n2701) );
NAND2X2TS U2536 ( .A(n1031), .B(n2119), .Y(n2120) );
NAND2X2TS U2537 ( .A(n2872), .B(n1150), .Y(n1865) );
NOR2X2TS U2538 ( .A(n2359), .B(n2358), .Y(n2360) );
XOR2X4TS U2539 ( .A(n2361), .B(n2360), .Y(n2363) );
NAND2X4TS U2540 ( .A(n2039), .B(n2644), .Y(n2357) );
NOR2X2TS U2541 ( .A(n1165), .B(n2688), .Y(n2038) );
OAI21X4TS U2542 ( .A0(n2361), .A1(n2358), .B0(n2357), .Y(n2041) );
AOI2BB2X2TS U2543 ( .B0(n2546), .B1(n3308), .A0N(n2545), .A1N(n1012), .Y(
n3472) );
AOI21X4TS U2544 ( .A0(n1800), .A1(n1799), .B0(n1798), .Y(n1815) );
XOR2X4TS U2545 ( .A(n2257), .B(n2216), .Y(n1541) );
NOR2X6TS U2546 ( .A(n2185), .B(n1681), .Y(n2070) );
NOR2X8TS U2547 ( .A(n1483), .B(n1720), .Y(n1482) );
OAI21X4TS U2548 ( .A0(n1875), .A1(n1874), .B0(n1873), .Y(n1894) );
NAND2X2TS U2549 ( .A(n2853), .B(n1198), .Y(n1855) );
NAND2X6TS U2550 ( .A(n1258), .B(n2464), .Y(n1917) );
AOI21X4TS U2551 ( .A0(n1882), .A1(n1881), .B0(n1880), .Y(n1891) );
NOR2X4TS U2552 ( .A(n2863), .B(n1177), .Y(n1802) );
NOR2X4TS U2553 ( .A(n1806), .B(n1801), .Y(n1803) );
NOR2X4TS U2554 ( .A(n1634), .B(DMP_SFG[21]), .Y(n2069) );
NOR2X8TS U2555 ( .A(n1515), .B(n1623), .Y(n1556) );
AND2X8TS U2556 ( .A(n850), .B(n1428), .Y(n2994) );
AOI22X4TS U2557 ( .A0(n2219), .A1(Shift_amount_SHT1_EWR[2]), .B0(n1243),
.B1(shift_value_SHT2_EWR[2]), .Y(n1429) );
XNOR2X4TS U2558 ( .A(n1437), .B(n1993), .Y(n1436) );
AOI2BB2X4TS U2559 ( .B0(n2469), .B1(n1916), .A0N(n2310), .A1N(n1507), .Y(
n1461) );
INVX12TS U2560 ( .A(n2507), .Y(n2476) );
AOI2BB1X4TS U2561 ( .A0N(n1342), .A1N(n1027), .B0(n2335), .Y(n1445) );
NAND2BX4TS U2562 ( .AN(sub_x_5_n198), .B(sub_x_5_n201), .Y(n1447) );
NAND2X8TS U2563 ( .A(n1451), .B(n1450), .Y(n870) );
AOI21X4TS U2564 ( .A0(n1006), .A1(n2991), .B0(n1452), .Y(n1451) );
NOR2X8TS U2565 ( .A(n1995), .B(n1663), .Y(n2000) );
AOI2BB2X4TS U2566 ( .B0(n2080), .B1(n2488), .A0N(n1460), .A1N(n1664), .Y(
n1459) );
NOR2X8TS U2567 ( .A(n1464), .B(n1463), .Y(n1566) );
NAND2BX4TS U2568 ( .AN(n1693), .B(n1467), .Y(n1463) );
AND2X8TS U2569 ( .A(n2027), .B(n1692), .Y(n1468) );
NAND2X8TS U2570 ( .A(n1590), .B(n1518), .Y(n1476) );
XOR2X4TS U2571 ( .A(n1481), .B(n1482), .Y(n1602) );
OAI21X4TS U2572 ( .A0(n1713), .A1(n1714), .B0(n1712), .Y(n1481) );
OAI2BB1X4TS U2573 ( .A0N(n1679), .A1N(n2107), .B0(n1603), .Y(n2188) );
OAI2BB1X4TS U2574 ( .A0N(n1490), .A1N(n1489), .B0(n2286), .Y(n2392) );
AOI21X4TS U2575 ( .A0(n2047), .A1(n1343), .B0(n1596), .Y(n1495) );
AND2X6TS U2576 ( .A(n1934), .B(n1933), .Y(n1501) );
NAND2X8TS U2577 ( .A(n1502), .B(n1504), .Y(n2400) );
OAI2BB1X4TS U2578 ( .A0N(n1260), .A1N(n2599), .B0(n1985), .Y(n560) );
NOR2X8TS U2579 ( .A(shift_value_SHT2_EWR[4]), .B(n1507), .Y(n1999) );
NAND2X8TS U2580 ( .A(n3530), .B(shift_value_SHT2_EWR[3]), .Y(n1507) );
AOI2BB2X4TS U2581 ( .B0(n2080), .B1(n2446), .A0N(n1664), .A1N(n1509), .Y(
n2083) );
BUFX20TS U2582 ( .A(n3311), .Y(n1514) );
INVX6TS U2583 ( .A(Shift_reg_FLAGS_7[0]), .Y(n1517) );
BUFX20TS U2584 ( .A(n1170), .Y(n1518) );
OAI2BB1X4TS U2585 ( .A0N(n1260), .A1N(n1520), .B0(n2325), .Y(n559) );
AND3X8TS U2586 ( .A(n1725), .B(n1724), .C(n1723), .Y(n1521) );
XNOR2X4TS U2587 ( .A(n2133), .B(n1522), .Y(n2134) );
INVX16TS U2588 ( .A(n1523), .Y(n1624) );
OR2X8TS U2589 ( .A(n1524), .B(shift_value_SHT2_EWR[4]), .Y(n1523) );
NAND2X8TS U2590 ( .A(n2199), .B(n1692), .Y(n2256) );
XNOR2X4TS U2591 ( .A(n1534), .B(n2151), .Y(n1533) );
OAI2BB1X4TS U2592 ( .A0N(n1420), .A1N(n2215), .B0(add_x_6_n160), .Y(n1534)
);
NAND2XLTS U2593 ( .A(n1544), .B(n1166), .Y(n2227) );
AOI21X4TS U2594 ( .A0(n1545), .A1(n2531), .B0(n1546), .Y(n3587) );
AOI21X4TS U2595 ( .A0(n1545), .A1(n2535), .B0(n1547), .Y(n3598) );
AOI21X4TS U2596 ( .A0(n1545), .A1(n2541), .B0(n1548), .Y(n3581) );
AOI21X4TS U2597 ( .A0(n1545), .A1(n2537), .B0(n1549), .Y(n3578) );
AOI21X4TS U2598 ( .A0(n1545), .A1(n2544), .B0(n1550), .Y(n3547) );
AOI21X4TS U2599 ( .A0(n1545), .A1(n2533), .B0(n1551), .Y(n3536) );
NOR2X8TS U2600 ( .A(n1585), .B(n1759), .Y(n2048) );
OR3X6TS U2601 ( .A(n2475), .B(n1216), .C(n1218), .Y(n1743) );
OAI21X4TS U2602 ( .A0(n2190), .A1(n1532), .B0(n2189), .Y(n2192) );
XOR2X4TS U2603 ( .A(n1001), .B(n2157), .Y(n2172) );
INVX16TS U2604 ( .A(n1555), .Y(n1557) );
NAND2X8TS U2605 ( .A(n1556), .B(n979), .Y(n1555) );
NOR2X8TS U2606 ( .A(n1558), .B(n1518), .Y(n2130) );
NAND2X8TS U2607 ( .A(n1344), .B(LZD_output_NRM2_EW[4]), .Y(n2129) );
XNOR2X4TS U2608 ( .A(n1562), .B(n2205), .Y(n1561) );
OAI21X2TS U2609 ( .A0(n2257), .A1(n2204), .B0(n2203), .Y(n1562) );
OAI2BB1X4TS U2610 ( .A0N(n2323), .A1N(n2196), .B0(n2195), .Y(n598) );
XNOR2X4TS U2611 ( .A(n1569), .B(n2193), .Y(n2194) );
OAI22X4TS U2612 ( .A0(n2836), .A1(n1518), .B0(DMP_exp_NRM2_EW[7]), .B1(n1171), .Y(n1619) );
NOR2X8TS U2613 ( .A(n1695), .B(n2256), .Y(n1570) );
AND2X8TS U2614 ( .A(n1751), .B(n1575), .Y(n1574) );
NAND2X8TS U2615 ( .A(n2229), .B(n2226), .Y(n2049) );
AND2X8TS U2616 ( .A(n2267), .B(n2634), .Y(n1593) );
AOI21X4TS U2617 ( .A0(n1581), .A1(n1773), .B0(n1580), .Y(n2267) );
OAI21X4TS U2618 ( .A0(n1217), .A1(n1016), .B0(n1203), .Y(n1580) );
NOR2X8TS U2619 ( .A(Raw_mant_NRM_SWR[5]), .B(n1032), .Y(n2045) );
NAND2X4TS U2620 ( .A(n1046), .B(n1769), .Y(n1594) );
NAND2BX4TS U2621 ( .AN(n1597), .B(n1770), .Y(n2268) );
OAI21X1TS U2622 ( .A0(n1644), .A1(n1602), .B0(n1601), .Y(n2379) );
NOR2BX4TS U2623 ( .AN(n2104), .B(n1604), .Y(n1603) );
AND2X8TS U2624 ( .A(n1215), .B(n1153), .Y(n1753) );
NOR2BX4TS U2625 ( .AN(n2374), .B(n978), .Y(n1617) );
AOI21X4TS U2626 ( .A0(n983), .A1(n1109), .B0(n2245), .Y(n2248) );
AND2X8TS U2627 ( .A(n1041), .B(n1645), .Y(n2416) );
NAND2X8TS U2628 ( .A(shift_value_SHT2_EWR[4]), .B(bit_shift_SHT2), .Y(n2138)
);
BUFX20TS U2629 ( .A(Shift_reg_FLAGS_7[0]), .Y(n3312) );
XNOR2X4TS U2630 ( .A(n2260), .B(n2259), .Y(n2261) );
NAND2X2TS U2631 ( .A(n963), .B(n1268), .Y(n3444) );
NAND2X2TS U2632 ( .A(n1223), .B(n1268), .Y(n3440) );
XNOR2X4TS U2633 ( .A(intDY_EWSW[25]), .B(n1268), .Y(n1938) );
XNOR2X4TS U2634 ( .A(n2287), .B(n2293), .Y(n2297) );
OAI21X4TS U2635 ( .A0(n1891), .A1(n1890), .B0(n1889), .Y(n1892) );
OAI2BB1X2TS U2636 ( .A0N(n2722), .A1N(n2557), .B0(n2556), .Y(n615) );
AO21X4TS U2637 ( .A0(n3273), .A1(n3272), .B0(n3271), .Y(n2065) );
NAND2X4TS U2638 ( .A(n2875), .B(intDX_EWSW[0]), .Y(n1792) );
OAI2BB1X2TS U2639 ( .A0N(underflow_flag), .A1N(n1644), .B0(n2730), .Y(n639)
);
NAND2X4TS U2640 ( .A(n1314), .B(n2502), .Y(n1998) );
OAI2BB1X2TS U2641 ( .A0N(DmP_mant_SFG_SWR[7]), .A1N(n2421), .B0(n2331), .Y(
n2324) );
AOI21X4TS U2642 ( .A0(n1863), .A1(n1862), .B0(n1861), .Y(n1875) );
NOR2X8TS U2643 ( .A(n1851), .B(n1860), .Y(n1862) );
NAND2X4TS U2644 ( .A(n1313), .B(n2489), .Y(n1661) );
INVX6TS U2645 ( .A(n2138), .Y(n1995) );
OR2X4TS U2646 ( .A(n2521), .B(n2538), .Y(n3580) );
OR2X8TS U2647 ( .A(n2526), .B(n2543), .Y(n3597) );
OR2X8TS U2648 ( .A(n2526), .B(n2534), .Y(n3538) );
OR2X4TS U2649 ( .A(n2521), .B(n2547), .Y(n3510) );
OAI21X4TS U2650 ( .A0(add_x_6_n167), .A1(n2010), .B0(n1052), .Y(n1690) );
MXI2X4TS U2651 ( .A(n2819), .B(n2885), .S0(n2665), .Y(n794) );
AOI22X2TS U2652 ( .A0(n1263), .A1(n3568), .B0(n2474), .B1(n1242), .Y(n3573)
);
AOI22X2TS U2653 ( .A0(n1263), .A1(n2529), .B0(n2503), .B1(n1243), .Y(n3592)
);
AOI22X2TS U2654 ( .A0(n3313), .A1(n3562), .B0(n2450), .B1(n1242), .Y(n3567)
);
AOI22X2TS U2655 ( .A0(n3313), .A1(n3556), .B0(n2480), .B1(n1243), .Y(n3561)
);
AOI2BB2X2TS U2656 ( .B0(n1263), .B1(n2533), .A0N(n2511), .A1N(n2491), .Y(
n3588) );
AOI2BB2X2TS U2657 ( .B0(n3313), .B1(n2514), .A0N(n2496), .A1N(n2491), .Y(
n3596) );
AOI2BB2X2TS U2658 ( .B0(n1414), .B1(n2544), .A0N(n1511), .A1N(n2491), .Y(
n3599) );
AOI2BB2X2TS U2659 ( .B0(n1414), .B1(n2539), .A0N(n2455), .A1N(n2491), .Y(
n3582) );
AOI2BB2X2TS U2660 ( .B0(n1414), .B1(n2531), .A0N(n2513), .A1N(n2491), .Y(
n3548) );
NAND2X4TS U2661 ( .A(n2724), .B(n2218), .Y(n2222) );
AOI21X4TS U2662 ( .A0(n1872), .A1(n1871), .B0(n1870), .Y(n1873) );
NAND4X2TS U2663 ( .A(n2605), .B(n2606), .C(n2607), .D(n2604), .Y(n2609) );
NAND4X6TS U2664 ( .A(n1915), .B(n1914), .C(n1913), .D(n1912), .Y(n2587) );
MXI2X4TS U2665 ( .A(n2812), .B(n2884), .S0(n2664), .Y(n761) );
NOR2X6TS U2666 ( .A(n2569), .B(OP_FLAG_SFG), .Y(n1994) );
NAND3X8TS U2667 ( .A(n1918), .B(n1917), .C(n972), .Y(n2388) );
NOR2X6TS U2668 ( .A(DMP_SFG[20]), .B(DmP_mant_SFG_SWR[22]), .Y(n2191) );
NAND2X4TS U2669 ( .A(DMP_SFG[15]), .B(DmP_mant_SFG_SWR[17]), .Y(n2167) );
NAND2X4TS U2670 ( .A(n1642), .B(DMP_SFG[19]), .Y(n2314) );
OR2X4TS U2671 ( .A(n2521), .B(n2536), .Y(n3457) );
OR2X4TS U2672 ( .A(n2521), .B(n3563), .Y(n3524) );
OR2X4TS U2673 ( .A(n2521), .B(n2610), .Y(n3577) );
OR2X8TS U2674 ( .A(n2526), .B(n2520), .Y(n3544) );
OR2X4TS U2675 ( .A(n2521), .B(n3571), .Y(n3572) );
OR2X4TS U2676 ( .A(n2521), .B(n2532), .Y(n3586) );
OR2X4TS U2677 ( .A(n2521), .B(n3558), .Y(n3559) );
NAND2X2TS U2678 ( .A(n2873), .B(n1191), .Y(n1859) );
NOR2X4TS U2679 ( .A(n2873), .B(n1191), .Y(n1851) );
NOR2X4TS U2680 ( .A(add_x_6_n197), .B(add_x_6_n194), .Y(n1689) );
NOR2X8TS U2681 ( .A(n2421), .B(n2832), .Y(n1726) );
NAND2X4TS U2682 ( .A(n1631), .B(DMP_SFG[12]), .Y(n2252) );
MXI2X4TS U2683 ( .A(n2813), .B(n2913), .S0(n2664), .Y(n767) );
MXI2X4TS U2684 ( .A(n2880), .B(n2829), .S0(n2665), .Y(n2896) );
NOR2X4TS U2685 ( .A(n1839), .B(n1821), .Y(n1842) );
NAND2X2TS U2686 ( .A(n2845), .B(n1154), .Y(n1833) );
NAND2X6TS U2687 ( .A(n1047), .B(DMP_SFG[13]), .Y(n2176) );
AOI21X4TS U2688 ( .A0(n1812), .A1(n1811), .B0(n1810), .Y(n1813) );
NAND4X2TS U2689 ( .A(n1938), .B(n1937), .C(n1936), .D(n1935), .Y(n1942) );
AOI2BB2X4TS U2690 ( .B0(n1005), .B1(n2984), .A0N(n1002), .A1N(n2983), .Y(
n1730) );
NAND3X4TS U2691 ( .A(n3251), .B(n3250), .C(n3249), .Y(n2510) );
OAI21X4TS U2692 ( .A0(n1868), .A1(n1869), .B0(n1867), .Y(n1870) );
NOR2X8TS U2693 ( .A(n2209), .B(n1369), .Y(n2144) );
NAND3X6TS U2694 ( .A(n3124), .B(n3123), .C(n3122), .Y(n2353) );
OAI21X4TS U2695 ( .A0(n1879), .A1(n1878), .B0(n1877), .Y(n1880) );
NAND2X2TS U2696 ( .A(n2864), .B(n1155), .Y(n1878) );
NOR2X4TS U2697 ( .A(n1760), .B(n1766), .Y(n1748) );
OAI21X4TS U2698 ( .A0(n1797), .A1(n1796), .B0(n1795), .Y(n1798) );
OAI21X4TS U2699 ( .A0(n1806), .A1(n1805), .B0(n1804), .Y(n1812) );
NOR2X4TS U2700 ( .A(n1018), .B(n1021), .Y(n1764) );
AOI21X2TS U2701 ( .A0(n2735), .A1(n2333), .B0(n1656), .Y(n1657) );
NOR2X8TS U2702 ( .A(DMP_SFG[14]), .B(DmP_mant_SFG_SWR[16]), .Y(n2161) );
NAND2X8TS U2703 ( .A(add_x_6_A_8_), .B(add_x_6_B_8_), .Y(n2010) );
NAND2X4TS U2704 ( .A(n1803), .B(n1811), .Y(n1814) );
NOR2X6TS U2705 ( .A(n1648), .B(shift_value_SHT2_EWR[4]), .Y(n1649) );
OAI21X2TS U2706 ( .A0(n1675), .A1(n2176), .B0(n1674), .Y(n1676) );
MXI2X4TS U2707 ( .A(n2816), .B(n2909), .S0(n2665), .Y(n785) );
NOR2X4TS U2708 ( .A(n1850), .B(n1857), .Y(n1852) );
NOR2X2TS U2709 ( .A(n2874), .B(n1190), .Y(n1850) );
BUFX20TS U2710 ( .A(n2724), .Y(n2424) );
NOR2X4TS U2711 ( .A(n1818), .B(n1824), .Y(n1820) );
NOR2X2TS U2712 ( .A(n2858), .B(intDX_EWSW[8]), .Y(n1818) );
MXI2X2TS U2713 ( .A(n2915), .B(n2342), .S0(n2639), .Y(n846) );
NOR2X2TS U2714 ( .A(n2872), .B(n1150), .Y(n1847) );
NAND2X4TS U2715 ( .A(n1638), .B(DMP_SFG[10]), .Y(n2023) );
NOR2X8TS U2716 ( .A(Raw_mant_NRM_SWR[2]), .B(Raw_mant_NRM_SWR[3]), .Y(n2118)
);
OAI2BB1X2TS U2717 ( .A0N(n2722), .A1N(n2699), .B0(n2698), .Y(n618) );
OAI21X4TS U2718 ( .A0(n1857), .A1(n1856), .B0(n1855), .Y(n1863) );
NAND2X4TS U2719 ( .A(DMP_SFG[1]), .B(n1123), .Y(n2702) );
XOR2X4TS U2720 ( .A(n2041), .B(n2040), .Y(n2042) );
NOR2X4TS U2721 ( .A(n2154), .B(n2087), .Y(n2106) );
NAND2X8TS U2722 ( .A(sub_x_5_n245), .B(DMP_SFG[7]), .Y(n2208) );
MXI2X4TS U2723 ( .A(n2879), .B(n2830), .S0(n2664), .Y(n2897) );
NAND3X8TS U2724 ( .A(n1646), .B(n3212), .C(n3211), .Y(n2446) );
NAND4X6TS U2725 ( .A(n3227), .B(n3226), .C(n3225), .D(n3224), .Y(n2666) );
NAND3X6TS U2726 ( .A(n3094), .B(n3093), .C(n3092), .Y(n2641) );
OR2X4TS U2727 ( .A(n2313), .B(n2077), .Y(n1625) );
BUFX3TS U2728 ( .A(n2337), .Y(n3340) );
CLKBUFX2TS U2729 ( .A(n2337), .Y(n3341) );
BUFX3TS U2730 ( .A(n2338), .Y(n2590) );
BUFX3TS U2731 ( .A(n2339), .Y(n3320) );
NAND2X2TS U2732 ( .A(n770), .B(n555), .Y(n1633) );
AND2X2TS U2733 ( .A(n2697), .B(n2704), .Y(n1635) );
AOI22X2TS U2734 ( .A0(n2016), .A1(n2718), .B0(n1024), .B1(n2569), .Y(n2017)
);
NAND2X2TS U2735 ( .A(n2465), .B(DmP_mant_SHT1_SW[16]), .Y(n2447) );
INVX2TS U2736 ( .A(n557), .Y(n2739) );
BUFX3TS U2737 ( .A(n2337), .Y(n3336) );
NAND2X1TS U2738 ( .A(n1227), .B(intDX_EWSW[31]), .Y(n3678) );
NAND2X1TS U2739 ( .A(n1247), .B(intDY_EWSW[9]), .Y(n3387) );
CLKBUFX3TS U2740 ( .A(n3326), .Y(n2943) );
BUFX3TS U2741 ( .A(n2337), .Y(n3338) );
INVX16TS U2742 ( .A(n1655), .Y(n1739) );
AOI2BB2X4TS U2743 ( .B0(n2964), .B1(n2963), .A0N(n2962), .A1N(n2961), .Y(
n1653) );
AOI2BB2X4TS U2744 ( .B0(n1004), .B1(n2958), .A0N(n2957), .A1N(n2956), .Y(
n1654) );
OAI2BB1X1TS U2745 ( .A0N(DmP_mant_SFG_SWR[9]), .A1N(n2663), .B0(n2331), .Y(
n1656) );
INVX12TS U2746 ( .A(n1037), .Y(n2664) );
NAND2X4TS U2747 ( .A(n2063), .B(n2480), .Y(n1665) );
OAI21X4TS U2751 ( .A0(n1671), .A1(n2208), .B0(n2210), .Y(n2145) );
NOR2X4TS U2752 ( .A(n1622), .B(DMP_SFG[20]), .Y(n1681) );
INVX2TS U2753 ( .A(n2070), .Y(n1683) );
INVX2TS U2754 ( .A(n2069), .Y(n1685) );
NAND2X1TS U2755 ( .A(n1622), .B(DMP_SFG[20]), .Y(n1680) );
OAI21X2TS U2756 ( .A0(n1681), .A1(n2314), .B0(n1680), .Y(n2076) );
INVX2TS U2757 ( .A(n2076), .Y(n1682) );
INVX2TS U2758 ( .A(n2072), .Y(n1684) );
OR2X2TS U2759 ( .A(DMP_SFG[22]), .B(DmP_mant_SFG_SWR[24]), .Y(n2391) );
OAI21X4TS U2760 ( .A0(n2701), .A1(n2704), .B0(n2702), .Y(n2551) );
OAI21X4TS U2761 ( .A0(add_x_6_n183), .A1(add_x_6_n189), .B0(n2566), .Y(n2009) );
NOR2X4TS U2762 ( .A(n2191), .B(n2285), .Y(n2078) );
INVX2TS U2763 ( .A(n2078), .Y(n1699) );
NAND2X2TS U2764 ( .A(add_x_6_A_21_), .B(add_x_6_B_21_), .Y(n2319) );
OAI21X4TS U2765 ( .A0(add_x_6_n70), .A1(n2318), .B0(n2319), .Y(n1696) );
NAND2X1TS U2766 ( .A(DMP_SFG[21]), .B(DmP_mant_SFG_SWR[23]), .Y(n2286) );
MXI2X4TS U2767 ( .A(n2807), .B(n2888), .S0(n2664), .Y(n746) );
NAND2X4TS U2768 ( .A(n1916), .B(n870), .Y(n1708) );
NAND2X8TS U2769 ( .A(n1037), .B(n2372), .Y(n2420) );
NAND2X1TS U2770 ( .A(n2064), .B(n2510), .Y(n1731) );
NAND2X2TS U2771 ( .A(n1038), .B(n2333), .Y(n1735) );
AND2X8TS U2772 ( .A(sub_x_5_B_3_), .B(n1740), .Y(n2779) );
NOR2X8TS U2773 ( .A(n3682), .B(n2352), .Y(n1762) );
AND3X2TS U2774 ( .A(n1136), .B(n1020), .C(n1166), .Y(n1742) );
AOI2BB1X4TS U2775 ( .A0N(n1743), .A1N(n1742), .B0(n1741), .Y(n1746) );
BUFX12TS U2776 ( .A(n1207), .Y(n2634) );
NAND2X2TS U2777 ( .A(n2653), .B(Shift_amount_SHT1_EWR[1]), .Y(n1745) );
INVX2TS U2778 ( .A(n2559), .Y(n1778) );
NOR2X1TS U2779 ( .A(n1778), .B(n2560), .Y(n1781) );
INVX2TS U2780 ( .A(n2558), .Y(n1779) );
OAI21X1TS U2781 ( .A0(n1779), .A1(n2560), .B0(n2561), .Y(n1780) );
INVX2TS U2782 ( .A(n971), .Y(n1783) );
NAND2X1TS U2783 ( .A(n1783), .B(n1782), .Y(n1784) );
NAND2X1TS U2784 ( .A(n2764), .B(n2010), .Y(n1786) );
OAI2BB1X4TS U2785 ( .A0N(n2323), .A1N(n1790), .B0(n1789), .Y(n612) );
OAI21X4TS U2786 ( .A0(n1793), .A1(n1792), .B0(n1791), .Y(n1800) );
OAI21X4TS U2787 ( .A0(n1815), .A1(n1814), .B0(n1813), .Y(n1843) );
OAI21X4TS U2788 ( .A0(n1840), .A1(n1839), .B0(n1838), .Y(n1841) );
AOI21X4TS U2789 ( .A0(n1843), .A1(n1842), .B0(n1841), .Y(n1897) );
NAND2X6TS U2790 ( .A(n1845), .B(n1887), .Y(n1890) );
NAND2X4TS U2791 ( .A(n1852), .B(n1862), .Y(n1853) );
OAI21X4TS U2792 ( .A0(n1885), .A1(n1884), .B0(n1883), .Y(n1888) );
AOI21X4TS U2793 ( .A0(n1888), .A1(n1887), .B0(n1886), .Y(n1889) );
OAI21X4TS U2794 ( .A0(n1897), .A1(n1896), .B0(n1895), .Y(n1923) );
AND2X8TS U2795 ( .A(n1923), .B(Shift_reg_FLAGS_7_6), .Y(n2731) );
MXI2X2TS U2796 ( .A(n2815), .B(n2908), .S0(n2665), .Y(n779) );
OAI2BB1X1TS U2797 ( .A0N(DmP_mant_SFG_SWR[8]), .A1N(n2421), .B0(n2331), .Y(
n1903) );
NAND2X4TS U2798 ( .A(n1081), .B(n1261), .Y(n1914) );
OAI2BB1X1TS U2799 ( .A0N(DmP_mant_SFG_SWR[4]), .A1N(n2421), .B0(n2331), .Y(
n1921) );
AOI21X1TS U2800 ( .A0(n2333), .A1(n2388), .B0(n1921), .Y(n1922) );
AOI2BB1X4TS U2801 ( .A0N(n1045), .A1N(n1037), .B0(n1932), .Y(n1927) );
INVX4TS U2802 ( .A(n1927), .Y(n1928) );
NAND4X1TS U2803 ( .A(n3223), .B(n3222), .C(n3221), .D(n3220), .Y(n2723) );
NAND3X1TS U2804 ( .A(n3254), .B(n3253), .C(n3252), .Y(n2440) );
NAND2X2TS U2805 ( .A(n1050), .B(n2333), .Y(n1933) );
CLKXOR2X2TS U2806 ( .A(intDY_EWSW[31]), .B(intAS), .Y(n1979) );
XNOR2X1TS U2807 ( .A(intDY_EWSW[27]), .B(n1149), .Y(n1937) );
XNOR2X1TS U2808 ( .A(intDY_EWSW[17]), .B(n1198), .Y(n1936) );
XOR2X1TS U2809 ( .A(intDY_EWSW[29]), .B(n1195), .Y(n1941) );
XOR2X1TS U2810 ( .A(intDY_EWSW[7]), .B(n1183), .Y(n1940) );
XOR2X1TS U2811 ( .A(intDY_EWSW[26]), .B(n1155), .Y(n1939) );
XNOR2X1TS U2812 ( .A(intDY_EWSW[19]), .B(intDX_EWSW[19]), .Y(n1946) );
XNOR2X1TS U2813 ( .A(intDY_EWSW[21]), .B(n1157), .Y(n1944) );
XNOR2X1TS U2814 ( .A(intDY_EWSW[20]), .B(n1150), .Y(n1943) );
XNOR2X1TS U2815 ( .A(intDY_EWSW[23]), .B(n1158), .Y(n1950) );
XNOR2X1TS U2816 ( .A(intDY_EWSW[22]), .B(n1184), .Y(n1949) );
XNOR2X1TS U2817 ( .A(intDY_EWSW[10]), .B(intDX_EWSW[10]), .Y(n1948) );
XNOR2X1TS U2818 ( .A(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n1947) );
XNOR2X1TS U2819 ( .A(intDY_EWSW[12]), .B(n1143), .Y(n1956) );
XNOR2X1TS U2820 ( .A(intDY_EWSW[11]), .B(n1187), .Y(n1955) );
XNOR2X1TS U2821 ( .A(intDY_EWSW[14]), .B(n1154), .Y(n1954) );
XNOR2X1TS U2822 ( .A(intDY_EWSW[13]), .B(intDX_EWSW[13]), .Y(n1953) );
NAND4X1TS U2823 ( .A(n1956), .B(n1955), .C(n1954), .D(n1953), .Y(n1962) );
XNOR2X1TS U2824 ( .A(intDY_EWSW[24]), .B(intDX_EWSW[24]), .Y(n1960) );
XNOR2X1TS U2825 ( .A(intDY_EWSW[15]), .B(n1151), .Y(n1959) );
XNOR2X1TS U2826 ( .A(intDY_EWSW[2]), .B(intDX_EWSW[2]), .Y(n1958) );
XNOR2X1TS U2827 ( .A(intDY_EWSW[4]), .B(intDX_EWSW[4]), .Y(n1957) );
NAND4X1TS U2828 ( .A(n1960), .B(n1959), .C(n1958), .D(n1957), .Y(n1961) );
XNOR2X1TS U2829 ( .A(intDY_EWSW[3]), .B(n1178), .Y(n1966) );
XNOR2X1TS U2830 ( .A(intDY_EWSW[6]), .B(n1177), .Y(n1965) );
XNOR2X1TS U2831 ( .A(intDY_EWSW[5]), .B(n1180), .Y(n1964) );
XNOR2X1TS U2832 ( .A(intDY_EWSW[16]), .B(n1190), .Y(n1963) );
XNOR2X1TS U2833 ( .A(intDX_EWSW[0]), .B(intDY_EWSW[0]), .Y(n1970) );
XNOR2X1TS U2834 ( .A(intDY_EWSW[28]), .B(intDX_EWSW[28]), .Y(n1969) );
XNOR2X1TS U2835 ( .A(intDY_EWSW[30]), .B(intDX_EWSW[30]), .Y(n1968) );
NOR2X1TS U2836 ( .A(n3312), .B(overflow_flag), .Y(n1977) );
INVX2TS U2837 ( .A(n1979), .Y(n1978) );
NOR2X4TS U2838 ( .A(n1978), .B(n2890), .Y(n2659) );
INVX2TS U2839 ( .A(n2659), .Y(n1982) );
NOR2X1TS U2840 ( .A(intDX_EWSW[31]), .B(n1979), .Y(n1980) );
NAND2X4TS U2841 ( .A(n1982), .B(n1981), .Y(n2364) );
OAI2BB1X1TS U2842 ( .A0N(DmP_mant_SFG_SWR[6]), .A1N(n2421), .B0(n2331), .Y(
n1984) );
INVX2TS U2843 ( .A(n2161), .Y(n1989) );
NAND2X2TS U2844 ( .A(n1989), .B(n2160), .Y(n1993) );
NAND2X1TS U2845 ( .A(n2180), .B(n2158), .Y(n1992) );
INVX6TS U2846 ( .A(n1300), .Y(n2181) );
AOI21X4TS U2847 ( .A0(n2181), .A1(n2158), .B0(add_x_6_n115), .Y(n1991) );
INVX4TS U2848 ( .A(n604), .Y(n2992) );
MXI2X4TS U2849 ( .A(n2811), .B(n2883), .S0(n2664), .Y(n758) );
INVX2TS U2850 ( .A(n2209), .Y(n2005) );
NAND2X1TS U2851 ( .A(n2005), .B(n2208), .Y(n2006) );
XOR2X1TS U2852 ( .A(n2250), .B(n2006), .Y(n2018) );
INVX2TS U2853 ( .A(n2007), .Y(n2008) );
NOR2X1TS U2854 ( .A(n2008), .B(add_x_6_n172), .Y(n2013) );
AOI21X4TS U2855 ( .A0(n1362), .A1(n2013), .B0(n2012), .Y(n2015) );
NAND2X1TS U2856 ( .A(n2768), .B(n1052), .Y(n2014) );
NAND2X1TS U2857 ( .A(n2148), .B(n2144), .Y(n2021) );
AOI21X1TS U2858 ( .A0(n1179), .A1(n2148), .B0(n2019), .Y(n2020) );
INVX2TS U2859 ( .A(n2022), .Y(n2024) );
NAND2X1TS U2860 ( .A(n2024), .B(n2023), .Y(n2025) );
XNOR2X2TS U2861 ( .A(n2026), .B(n2025), .Y(n2034) );
INVX2TS U2862 ( .A(n1146), .Y(n2028) );
NAND2X1TS U2863 ( .A(n2202), .B(n2200), .Y(n2030) );
AOI22X2TS U2864 ( .A0(n2032), .A1(n2718), .B0(n1147), .B1(n2569), .Y(n2033)
);
OAI21X4TS U2865 ( .A0(n2346), .A1(n2343), .B0(n2345), .Y(n2350) );
INVX2TS U2866 ( .A(n2688), .Y(n2037) );
OAI22X4TS U2867 ( .A0(n2350), .A1(n2038), .B0(n2695), .B1(n2037), .Y(n2361)
);
NAND3X2TS U2868 ( .A(n3010), .B(n3009), .C(n3008), .Y(n2644) );
NAND3X1TS U2869 ( .A(n3127), .B(n3126), .C(n3125), .Y(n2355) );
XOR2X1TS U2870 ( .A(n2642), .B(n2355), .Y(n2040) );
MXI2X4TS U2871 ( .A(n2042), .B(n2882), .S0(n2678), .Y(n842) );
NOR2X4TS U2872 ( .A(n2273), .B(n2055), .Y(n2057) );
INVX2TS U2873 ( .A(n2241), .Y(n2060) );
MXI2X2TS U2874 ( .A(n2805), .B(n2911), .S0(n2663), .Y(n740) );
NOR2X2TS U2875 ( .A(n2069), .B(n2073), .Y(n2075) );
NAND2X1TS U2876 ( .A(n1627), .B(DMP_SFG[22]), .Y(n2071) );
OAI21X1TS U2877 ( .A0(n2073), .A1(n2072), .B0(n2071), .Y(n2074) );
NAND2X4TS U2878 ( .A(n2078), .B(n2391), .Y(n2393) );
MXI2X2TS U2879 ( .A(n2806), .B(n2912), .S0(n2663), .Y(n743) );
NAND2X4TS U2880 ( .A(n2388), .B(n1261), .Y(n2082) );
NOR2X4TS U2881 ( .A(n743), .B(n546), .Y(n2761) );
INVX2TS U2882 ( .A(n2087), .Y(n2089) );
INVX2TS U2883 ( .A(n2113), .Y(n2092) );
NAND2X1TS U2884 ( .A(n2092), .B(add_x_6_n92), .Y(n2093) );
OAI2BB1X4TS U2885 ( .A0N(n1352), .A1N(n2096), .B0(n2095), .Y(n602) );
NAND2X1TS U2886 ( .A(n2774), .B(n2318), .Y(n2097) );
XNOR2X4TS U2887 ( .A(n2098), .B(n2097), .Y(n2105) );
INVX2TS U2888 ( .A(n2099), .Y(n2111) );
NAND2X1TS U2889 ( .A(n2106), .B(n2111), .Y(n2102) );
INVX2TS U2890 ( .A(n2110), .Y(n2100) );
AOI21X1TS U2891 ( .A0(n2107), .A1(n2111), .B0(n2100), .Y(n2101) );
INVX2TS U2892 ( .A(n2106), .Y(n2109) );
INVX2TS U2893 ( .A(n2107), .Y(n2108) );
INVX2TS U2894 ( .A(n2116), .Y(n2117) );
INVX2TS U2895 ( .A(n2118), .Y(n2119) );
MXI2X4TS U2896 ( .A(n2126), .B(n2905), .S0(n2653), .Y(n590) );
XOR2X4TS U2897 ( .A(n2141), .B(n2140), .Y(n2142) );
NAND2X2TS U2898 ( .A(n2143), .B(n2730), .Y(n836) );
INVX2TS U2899 ( .A(n2144), .Y(n2146) );
NAND2X1TS U2900 ( .A(n2148), .B(n2147), .Y(n2149) );
NAND2X1TS U2901 ( .A(n2150), .B(n2776), .Y(n2151) );
INVX2TS U2902 ( .A(n2154), .Y(n2156) );
NAND2X1TS U2903 ( .A(n2156), .B(n2155), .Y(n2157) );
INVX2TS U2904 ( .A(n2158), .Y(n2159) );
NOR2X6TS U2905 ( .A(n2159), .B(n2161), .Y(n2163) );
NAND2X1TS U2906 ( .A(n2163), .B(n2180), .Y(n2165) );
OAI21X1TS U2907 ( .A0(n2775), .A1(n2161), .B0(n2160), .Y(n2162) );
OAI21X4TS U2908 ( .A0(n2257), .A1(n2165), .B0(n2164), .Y(n2170) );
INVX2TS U2909 ( .A(n2166), .Y(n2168) );
NAND2X1TS U2910 ( .A(n2168), .B(n2167), .Y(n2169) );
XNOR2X4TS U2911 ( .A(n2170), .B(n2169), .Y(n2171) );
NAND2X2TS U2912 ( .A(n2832), .B(n3312), .Y(n2173) );
INVX2TS U2913 ( .A(n2175), .Y(n2177) );
NAND2X1TS U2914 ( .A(n2177), .B(n2176), .Y(n2178) );
INVX2TS U2915 ( .A(n2179), .Y(n2258) );
NAND2X1TS U2916 ( .A(n2180), .B(n2258), .Y(n2183) );
NAND2X1TS U2917 ( .A(n2770), .B(add_x_6_n121), .Y(n2184) );
INVX2TS U2918 ( .A(n2313), .Y(n2186) );
INVX2TS U2919 ( .A(n2314), .Y(n2187) );
NAND2X2TS U2920 ( .A(n2290), .B(n2289), .Y(n2193) );
AOI2BB2X4TS U2921 ( .B0(n2194), .B1(n2295), .A0N(n977), .A1N(
Shift_reg_FLAGS_7[2]), .Y(n2195) );
NAND2X1TS U2922 ( .A(n2246), .B(n2244), .Y(n2198) );
INVX2TS U2923 ( .A(n2200), .Y(n2201) );
AOI21X1TS U2924 ( .A0(n1146), .A1(n2202), .B0(n2201), .Y(n2203) );
NAND2X1TS U2925 ( .A(n2767), .B(n1048), .Y(n2205) );
OAI2BB1X4TS U2926 ( .A0N(n2722), .A1N(n2207), .B0(n2206), .Y(n607) );
NAND2X1TS U2927 ( .A(n2211), .B(n2210), .Y(n2212) );
INVX2TS U2928 ( .A(n2214), .Y(n2215) );
NAND2X1TS U2929 ( .A(n2215), .B(add_x_6_n160), .Y(n2216) );
AOI22X1TS U2930 ( .A0(n2219), .A1(Shift_amount_SHT1_EWR[4]), .B0(n1261),
.B1(n1242), .Y(n2221) );
NOR2X2TS U2931 ( .A(n1424), .B(n2893), .Y(n2462) );
INVX2TS U2932 ( .A(n2223), .Y(n2224) );
NOR2X2TS U2933 ( .A(n2225), .B(n2224), .Y(n2235) );
NAND3X1TS U2934 ( .A(n2230), .B(n2229), .C(n2228), .Y(n2231) );
INVX16TS U2935 ( .A(n2306), .Y(n2521) );
NOR2X4TS U2936 ( .A(n2897), .B(n553), .Y(n2759) );
NAND2X1TS U2937 ( .A(n2465), .B(DmP_mant_SHT1_SW[11]), .Y(n2239) );
NAND2X2TS U2938 ( .A(n2243), .B(n1109), .Y(n2249) );
INVX2TS U2939 ( .A(n2244), .Y(n2245) );
NAND2X1TS U2940 ( .A(n1290), .B(n2252), .Y(n2253) );
XNOR2X4TS U2941 ( .A(n2254), .B(n2253), .Y(n2263) );
NAND2X1TS U2942 ( .A(n2258), .B(add_x_6_n128), .Y(n2259) );
CLKINVX1TS U2943 ( .A(n2267), .Y(n2269) );
AO22X4TS U2944 ( .A0(n2276), .A1(n1373), .B0(LZD_output_NRM2_EW[0]), .B1(
n2498), .Y(n593) );
NAND2X2TS U2945 ( .A(n2498), .B(DmP_mant_SHT1_SW[17]), .Y(n2277) );
NAND2X2TS U2946 ( .A(n2278), .B(n2277), .Y(n2280) );
NOR2X2TS U2947 ( .A(n1262), .B(n1033), .Y(n2279) );
NOR2X4TS U2948 ( .A(n2280), .B(n2279), .Y(n3565) );
INVX2TS U2949 ( .A(n2283), .Y(n2284) );
OAI21X4TS U2950 ( .A0(n2397), .A1(n2292), .B0(n2291), .Y(n2294) );
MXI2X4TS U2951 ( .A(n2299), .B(n3306), .S0(n2465), .Y(n594) );
OAI22X1TS U2952 ( .A0(n2506), .A1(n1020), .B0(n1373), .B1(n2876), .Y(n2300)
);
NOR2X2TS U2953 ( .A(n2301), .B(n2300), .Y(n3569) );
NAND2X1TS U2954 ( .A(n1345), .B(n1166), .Y(n2303) );
OAI22X1TS U2955 ( .A0(n2506), .A1(n3549), .B0(n2505), .B1(n2891), .Y(n2307)
);
NOR2X2TS U2956 ( .A(n2308), .B(n2307), .Y(n2538) );
NOR2X8TS U2957 ( .A(n2311), .B(n1491), .Y(n2516) );
OAI21X4TS U2958 ( .A0(n1001), .A1(n2313), .B0(n2312), .Y(n2316) );
NAND2X1TS U2959 ( .A(n2766), .B(n2319), .Y(n2320) );
NOR2X4TS U2960 ( .A(n767), .B(n1077), .Y(n2756) );
AOI21X1TS U2961 ( .A0(n2333), .A1(n2733), .B0(n2324), .Y(n2325) );
MXI2X2TS U2962 ( .A(n2895), .B(n2831), .S0(n2664), .Y(n773) );
NAND2X2TS U2963 ( .A(n2597), .B(n1726), .Y(n2327) );
INVX2TS U2964 ( .A(n2740), .Y(n2329) );
MXI2X4TS U2965 ( .A(n2817), .B(n2329), .S0(n2665), .Y(n788) );
AOI21X2TS U2966 ( .A0(n2333), .A1(n1081), .B0(n2332), .Y(n2334) );
BUFX3TS U2967 ( .A(n1246), .Y(n2955) );
BUFX3TS U2968 ( .A(n1246), .Y(n2954) );
INVX2TS U2969 ( .A(sub_x_5_B_10_), .Y(n2777) );
CLKBUFX3TS U2970 ( .A(n1264), .Y(n2338) );
BUFX3TS U2971 ( .A(n3325), .Y(n2950) );
CLKBUFX3TS U2972 ( .A(n1238), .Y(n3343) );
CLKBUFX3TS U2973 ( .A(n3343), .Y(n3316) );
CLKBUFX3TS U2974 ( .A(n3315), .Y(n2937) );
CLKBUFX2TS U2975 ( .A(n2937), .Y(n2930) );
CLKBUFX3TS U2976 ( .A(n3324), .Y(n2941) );
CLKBUFX3TS U2977 ( .A(n3316), .Y(n2931) );
CLKBUFX3TS U2978 ( .A(n3343), .Y(n2933) );
CLKBUFX3TS U2979 ( .A(n2941), .Y(n2337) );
CLKBUFX3TS U2980 ( .A(n3321), .Y(n2948) );
CLKBUFX3TS U2981 ( .A(n2937), .Y(n2934) );
BUFX3TS U2982 ( .A(n2934), .Y(n3314) );
BUFX3TS U2983 ( .A(n1237), .Y(n2946) );
CLKBUFX3TS U2984 ( .A(n1264), .Y(n2339) );
BUFX3TS U2985 ( .A(n2339), .Y(n3321) );
BUFX3TS U2986 ( .A(n1246), .Y(n3342) );
CLKBUFX3TS U2987 ( .A(n3342), .Y(n3329) );
BUFX3TS U2988 ( .A(n2337), .Y(n3339) );
BUFX3TS U2989 ( .A(n2337), .Y(n3337) );
BUFX3TS U2990 ( .A(n2945), .Y(n2942) );
CLKBUFX3TS U2991 ( .A(n2338), .Y(n3327) );
BUFX3TS U2992 ( .A(n2339), .Y(n3318) );
OAI22X1TS U2993 ( .A0(n2975), .A1(n2974), .B0(n2973), .B1(n2972), .Y(
final_result_ieee[11]) );
CLKMX2X2TS U2994 ( .A(SIGN_FLAG_SHT1SHT2), .B(SIGN_FLAG_NRM), .S0(n2634),
.Y(n622) );
CLKMX2X2TS U2995 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(n2634),
.Y(n706) );
CLKMX2X2TS U2996 ( .A(ZERO_FLAG_SHT1SHT2), .B(ZERO_FLAG_NRM), .S0(n1373),
.Y(n633) );
CLKMX2X2TS U2997 ( .A(n1162), .B(DMP_exp_NRM_EW[0]), .S0(n2505), .Y(n726) );
OAI21X1TS U2998 ( .A0(n2634), .A1(n1171), .B0(n1388), .Y(n627) );
INVX2TS U2999 ( .A(n2643), .Y(n2340) );
NOR2X1TS U3000 ( .A(n2340), .B(n2641), .Y(n2341) );
NOR2X1TS U3001 ( .A(n2346), .B(n2341), .Y(n2342) );
NAND4X2TS U3002 ( .A(n3288), .B(n965), .C(n3287), .D(n3286), .Y(
final_result_ieee[22]) );
NAND2X2TS U3003 ( .A(n1710), .B(final_result_ieee[22]), .Y(n3672) );
CLKMX2X2TS U3004 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(n2505),
.Y(n701) );
NAND4X2TS U3005 ( .A(n3299), .B(n965), .C(n3298), .D(n3297), .Y(
final_result_ieee[16]) );
NAND4X2TS U3006 ( .A(n3236), .B(n965), .C(n3235), .D(n3234), .Y(
final_result_ieee[18]) );
XNOR2X1TS U3007 ( .A(n2347), .B(n2346), .Y(n2348) );
XNOR2X1TS U3008 ( .A(n2349), .B(n2350), .Y(n2351) );
CLKMX2X2TS U3009 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(n1373),
.Y(n696) );
CLKMX2X2TS U3010 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(n1373),
.Y(n691) );
BUFX8TS U3011 ( .A(n2638), .Y(n2646) );
NAND2X2TS U3012 ( .A(n2353), .B(n2646), .Y(n3430) );
BUFX8TS U3013 ( .A(n2638), .Y(n2356) );
NAND3X1TS U3014 ( .A(n3055), .B(n3054), .C(n3053), .Y(n2626) );
NAND3X1TS U3015 ( .A(n3058), .B(n3057), .C(n3056), .Y(n2627) );
NAND3X1TS U3016 ( .A(n3052), .B(n3051), .C(n3050), .Y(n2630) );
NAND3X1TS U3017 ( .A(n3088), .B(n3087), .C(n3086), .Y(n2625) );
NAND3X1TS U3018 ( .A(n3013), .B(n3012), .C(n3011), .Y(n2614) );
NAND3X1TS U3019 ( .A(n3076), .B(n3075), .C(n3074), .Y(n2617) );
NAND3X1TS U3020 ( .A(n3061), .B(n3060), .C(n3059), .Y(n2616) );
NAND3X1TS U3021 ( .A(n3073), .B(n3072), .C(n3071), .Y(n2618) );
NAND3X1TS U3022 ( .A(n3121), .B(n3120), .C(n3119), .Y(n2682) );
BUFX8TS U3023 ( .A(n2638), .Y(n2647) );
NAND3X1TS U3024 ( .A(n3028), .B(n3027), .C(n3026), .Y(n2612) );
NAND3X1TS U3025 ( .A(n3070), .B(n3069), .C(n3068), .Y(n2622) );
NAND3X1TS U3026 ( .A(n3025), .B(n3024), .C(n3023), .Y(n2620) );
NAND3X1TS U3027 ( .A(n3067), .B(n3066), .C(n3065), .Y(n2619) );
NAND3X1TS U3028 ( .A(n3064), .B(n3063), .C(n3062), .Y(n2615) );
NAND3X1TS U3029 ( .A(n3022), .B(n3021), .C(n3020), .Y(n2613) );
NAND3X1TS U3030 ( .A(n3003), .B(n3002), .C(n3001), .Y(n2635) );
NAND3X1TS U3031 ( .A(n3157), .B(n3156), .C(n3155), .Y(n2624) );
NAND3X1TS U3032 ( .A(n3160), .B(n3159), .C(n3158), .Y(n2623) );
NAND3X1TS U3033 ( .A(n3000), .B(n2999), .C(n2998), .Y(n2636) );
NAND3X1TS U3034 ( .A(n3169), .B(n3168), .C(n3167), .Y(n2631) );
NAND3X1TS U3035 ( .A(n3163), .B(n3162), .C(n3161), .Y(n2628) );
NAND3X1TS U3036 ( .A(n3166), .B(n3165), .C(n3164), .Y(n2629) );
INVX2TS U3037 ( .A(n2357), .Y(n2359) );
MXI2X2TS U3038 ( .A(n2592), .B(inst_FSM_INPUT_ENABLE_state_reg[1]), .S0(
inst_FSM_INPUT_ENABLE_state_reg[0]), .Y(n2367) );
MXI2X1TS U3039 ( .A(n2801), .B(n2569), .S0(n2667), .Y(n946) );
MXI2X1TS U3040 ( .A(n2569), .B(n2653), .S0(n2667), .Y(n945) );
NAND2X1TS U3041 ( .A(n1242), .B(bit_shift_SHT2), .Y(n2368) );
NAND2X2TS U3042 ( .A(n1243), .B(n1384), .Y(n2369) );
NAND2X2TS U3043 ( .A(n2369), .B(n1262), .Y(n877) );
XNOR2X1TS U3044 ( .A(sub_x_5_B_1_), .B(sub_x_5_n206), .Y(n2371) );
NAND2X1TS U3045 ( .A(n2372), .B(n3312), .Y(n2373) );
NAND2X1TS U3046 ( .A(n1247), .B(n1158), .Y(n3435) );
NAND2X2TS U3047 ( .A(n2376), .B(n2730), .Y(n837) );
MXI2X1TS U3048 ( .A(n2377), .B(final_result_ieee[23]), .S0(n1644), .Y(n2378)
);
NAND2X2TS U3049 ( .A(n2730), .B(n2378), .Y(n841) );
NAND2X2TS U3050 ( .A(n2730), .B(n2379), .Y(n840) );
MXI2X1TS U3051 ( .A(n2380), .B(final_result_ieee[26]), .S0(n1644), .Y(n2381)
);
NAND2X2TS U3052 ( .A(n2730), .B(n2381), .Y(n838) );
MXI2X1TS U3053 ( .A(n1040), .B(final_result_ieee[25]), .S0(n1644), .Y(n2382)
);
NAND2X2TS U3054 ( .A(n2730), .B(n2382), .Y(n839) );
INVX2TS U3055 ( .A(n2383), .Y(n2384) );
NAND2X2TS U3056 ( .A(n1039), .B(n2388), .Y(n3665) );
NAND2X2TS U3057 ( .A(n1039), .B(n2410), .Y(n3675) );
INVX2TS U3058 ( .A(n2388), .Y(n2389) );
OAI21X4TS U3059 ( .A0(n2397), .A1(n2396), .B0(n2395), .Y(n2398) );
AOI21X1TS U3060 ( .A0(DmP_mant_SFG_SWR[23]), .A1(n2408), .B0(n2403), .Y(
n2402) );
NAND2X1TS U3061 ( .A(n1050), .B(n1706), .Y(n2401) );
AOI21X1TS U3062 ( .A0(DmP_mant_SFG_SWR[22]), .A1(n2408), .B0(n2403), .Y(
n2405) );
NAND2X2TS U3063 ( .A(n2412), .B(n2411), .Y(n542) );
AOI21X1TS U3064 ( .A0(n2416), .A1(n1706), .B0(n2415), .Y(n2417) );
NAND2X2TS U3065 ( .A(n2418), .B(n2417), .Y(n541) );
INVX2TS U3066 ( .A(n2419), .Y(n3640) );
NAND2X2TS U3067 ( .A(n2517), .B(n1216), .Y(n2429) );
NAND2X2TS U3068 ( .A(n2653), .B(DmP_mant_SHT1_SW[21]), .Y(n2428) );
NAND2X2TS U3069 ( .A(n2429), .B(n2428), .Y(n2431) );
NOR2X2TS U3070 ( .A(n1262), .B(n2835), .Y(n2430) );
NOR2X4TS U3071 ( .A(n2431), .B(n2430), .Y(n3558) );
INVX2TS U3072 ( .A(n3558), .Y(n3550) );
INVX2TS U3073 ( .A(n2432), .Y(n2433) );
NAND2X1TS U3074 ( .A(n2476), .B(n1220), .Y(n2435) );
NAND3X2TS U3075 ( .A(n2436), .B(n2435), .C(n2434), .Y(n3570) );
NAND2X1TS U3076 ( .A(n2465), .B(DmP_mant_SHT1_SW[0]), .Y(n2438) );
INVX2TS U3077 ( .A(n2440), .Y(n2441) );
NAND2X1TS U3078 ( .A(n2517), .B(n1135), .Y(n2443) );
OR2X2TS U3079 ( .A(n2497), .B(n1209), .Y(n2449) );
NAND2X2TS U3080 ( .A(n2517), .B(n1214), .Y(n2448) );
NAND2X1TS U3081 ( .A(n1345), .B(n1129), .Y(n2452) );
NAND2X1TS U3082 ( .A(n2465), .B(DmP_mant_SHT1_SW[8]), .Y(n2451) );
INVX2TS U3083 ( .A(n2454), .Y(n2455) );
OR2X4TS U3084 ( .A(n1262), .B(n2833), .Y(n2458) );
NAND3X4TS U3085 ( .A(n2458), .B(n2457), .C(n2456), .Y(n3564) );
NAND2X2TS U3086 ( .A(n2465), .B(DmP_mant_SHT1_SW[19]), .Y(n2460) );
NOR2X4TS U3087 ( .A(n2463), .B(n2462), .Y(n3563) );
INVX2TS U3088 ( .A(n3563), .Y(n2542) );
OR2X2TS U3089 ( .A(n2497), .B(n1025), .Y(n2468) );
NAND2X1TS U3090 ( .A(n2517), .B(n1021), .Y(n2467) );
NAND2X1TS U3091 ( .A(n2465), .B(DmP_mant_SHT1_SW[14]), .Y(n2466) );
NAND3X2TS U3092 ( .A(n2473), .B(n2472), .C(n2471), .Y(n3568) );
OR2X2TS U3093 ( .A(n2497), .B(n2894), .Y(n2479) );
NAND2X2TS U3094 ( .A(n2498), .B(DmP_mant_SHT1_SW[20]), .Y(n2477) );
NAND2X1TS U3095 ( .A(n2653), .B(DmP_mant_SHT1_SW[2]), .Y(n2481) );
OR2X2TS U3096 ( .A(n1424), .B(n1153), .Y(n2487) );
NAND2X1TS U3097 ( .A(n1345), .B(n1147), .Y(n2486) );
NAND2X1TS U3098 ( .A(n2498), .B(DmP_mant_SHT1_SW[10]), .Y(n2485) );
INVX2TS U3099 ( .A(n2538), .Y(n2544) );
OAI22X1TS U3100 ( .A0(n2506), .A1(n977), .B0(n2505), .B1(n2892), .Y(n2493)
);
INVX2TS U3101 ( .A(n2495), .Y(n2496) );
NAND2X1TS U3102 ( .A(n1345), .B(n1029), .Y(n2500) );
NAND2X1TS U3103 ( .A(n2498), .B(DmP_mant_SHT1_SW[12]), .Y(n2499) );
OAI22X1TS U3104 ( .A0(n2506), .A1(n1215), .B0(n2505), .B1(n2504), .Y(n2509)
);
NOR2X2TS U3105 ( .A(n2509), .B(n2508), .Y(n3571) );
INVX2TS U3106 ( .A(n3571), .Y(n2533) );
INVX2TS U3107 ( .A(n2510), .Y(n2511) );
INVX2TS U3108 ( .A(n2512), .Y(n2513) );
AOI21X1TS U3109 ( .A0(n1762), .A1(n1199), .B0(n2517), .Y(n2518) );
INVX2TS U3110 ( .A(n3570), .Y(n2532) );
INVX2TS U3111 ( .A(n3568), .Y(n3593) );
NAND2X2TS U3112 ( .A(n2498), .B(DmP_mant_SHT1_SW[22]), .Y(n2522) );
NAND2X2TS U3113 ( .A(n2523), .B(n2522), .Y(n2525) );
NOR2X2TS U3114 ( .A(n1262), .B(n2842), .Y(n2524) );
NOR2X4TS U3115 ( .A(n2525), .B(n2524), .Y(n3551) );
INVX2TS U3116 ( .A(n2548), .Y(n2528) );
NAND4X2TS U3117 ( .A(n3187), .B(n3186), .C(n1008), .D(n3185), .Y(
final_result_ieee[3]) );
NAND4X2TS U3118 ( .A(n3302), .B(n3301), .C(n1008), .D(n3300), .Y(
final_result_ieee[7]) );
NAND4X2TS U3119 ( .A(n3230), .B(n3229), .C(n1008), .D(n3228), .Y(
final_result_ieee[6]) );
NAND4X2TS U3120 ( .A(n3190), .B(n3189), .C(n1008), .D(n3188), .Y(
final_result_ieee[4]) );
NAND4X2TS U3121 ( .A(n3199), .B(n3198), .C(n1008), .D(n3197), .Y(
final_result_ieee[1]) );
NAND4X2TS U3122 ( .A(n3196), .B(n3195), .C(n1008), .D(n3194), .Y(
final_result_ieee[0]) );
NAND3X1TS U3123 ( .A(n1514), .B(n2737), .C(n2600), .Y(n3652) );
NAND4X2TS U3124 ( .A(n3305), .B(n965), .C(n3304), .D(n3303), .Y(
final_result_ieee[21]) );
NAND4X2TS U3125 ( .A(n3193), .B(n3192), .C(n1008), .D(n3191), .Y(
final_result_ieee[5]) );
NAND4X2TS U3126 ( .A(n3184), .B(n3183), .C(n1008), .D(n3182), .Y(
final_result_ieee[2]) );
NAND4X2TS U3127 ( .A(n3291), .B(n965), .C(n3290), .D(n3289), .Y(
final_result_ieee[14]) );
NAND4X2TS U3128 ( .A(n3233), .B(n965), .C(n3232), .D(n3231), .Y(
final_result_ieee[19]) );
INVX2TS U3129 ( .A(n2549), .Y(n2575) );
XNOR2X1TS U3130 ( .A(n2576), .B(n2550), .Y(n2557) );
INVX2TS U3131 ( .A(n2551), .Y(n2716) );
NAND2X1TS U3132 ( .A(n2769), .B(n2552), .Y(n2553) );
AOI22X1TS U3133 ( .A0(n2555), .A1(n2718), .B0(Raw_mant_NRM_SWR[5]), .B1(
n2717), .Y(n2556) );
NAND2X1TS U3134 ( .A(n2726), .B(n1184), .Y(n3528) );
NAND2X2TS U3135 ( .A(n2574), .B(final_result_ieee[21]), .Y(n3669) );
NAND2X2TS U3136 ( .A(n2574), .B(final_result_ieee[16]), .Y(n3654) );
NAND2X2TS U3137 ( .A(n2574), .B(final_result_ieee[18]), .Y(n3660) );
NAND2X2TS U3138 ( .A(n2574), .B(final_result_ieee[14]), .Y(n3648) );
NAND2X2TS U3139 ( .A(n2574), .B(final_result_ieee[19]), .Y(n3663) );
INVX2TS U3140 ( .A(n2560), .Y(n2562) );
NAND2X1TS U3141 ( .A(n2562), .B(n2561), .Y(n2563) );
XOR2X1TS U3142 ( .A(n2564), .B(n2563), .Y(n2572) );
INVX2TS U3143 ( .A(n2565), .Y(n2581) );
AOI21X4TS U3144 ( .A0(n1362), .A1(n2581), .B0(n2773), .Y(n2568) );
NAND2X1TS U3145 ( .A(n2765), .B(n2566), .Y(n2567) );
AOI22X2TS U3146 ( .A0(n2570), .A1(n2718), .B0(n1208), .B1(n2569), .Y(n2571)
);
NAND3X2TS U3147 ( .A(n3276), .B(n3275), .C(n3274), .Y(final_result_ieee[9])
);
NAND4X2TS U3148 ( .A(n3294), .B(n965), .C(n3293), .D(n3292), .Y(
final_result_ieee[15]) );
NAND2X2TS U3149 ( .A(n2574), .B(final_result_ieee[15]), .Y(n3651) );
NAND3X2TS U3150 ( .A(n3282), .B(n3281), .C(n3280), .Y(final_result_ieee[13])
);
NAND2X2TS U3151 ( .A(n2574), .B(final_result_ieee[17]), .Y(n3657) );
NAND4X2TS U3152 ( .A(n3239), .B(n965), .C(n3238), .D(n3237), .Y(
final_result_ieee[20]) );
NAND2X2TS U3153 ( .A(n2574), .B(final_result_ieee[20]), .Y(n3666) );
NAND3X2TS U3154 ( .A(n3285), .B(n3284), .C(n3283), .Y(final_result_ieee[8])
);
NAND3X2TS U3155 ( .A(n3279), .B(n3278), .C(n3277), .Y(final_result_ieee[12])
);
NAND2X1TS U3156 ( .A(n1172), .B(n2578), .Y(n2579) );
NAND2X1TS U3157 ( .A(n2581), .B(add_x_6_n189), .Y(n2582) );
NAND3X1TS U3158 ( .A(n1514), .B(n2737), .C(n2587), .Y(n3664) );
NAND3X1TS U3159 ( .A(n1514), .B(n2737), .C(n2588), .Y(n3646) );
NAND2X2TS U3160 ( .A(n1263), .B(n3550), .Y(n3555) );
CLKBUFX3TS U3161 ( .A(n3327), .Y(n2949) );
CLKBUFX3TS U3162 ( .A(n2945), .Y(n2947) );
CLKBUFX3TS U3163 ( .A(n2933), .Y(n2936) );
CLKBUFX3TS U3164 ( .A(n3315), .Y(n2935) );
CLKBUFX3TS U3165 ( .A(n3316), .Y(n2932) );
CLKBUFX3TS U3166 ( .A(n3329), .Y(n2952) );
CLKBUFX3TS U3167 ( .A(n3329), .Y(n2953) );
CLKBUFX3TS U3168 ( .A(n3329), .Y(n2951) );
CLKBUFX3TS U3169 ( .A(n3316), .Y(n2929) );
INVX2TS U3170 ( .A(final_result_ieee[11]), .Y(n3639) );
INVX2TS U3171 ( .A(n2654), .Y(n2611) );
NOR2X1TS U3172 ( .A(inst_FSM_INPUT_ENABLE_state_reg[1]), .B(
inst_FSM_INPUT_ENABLE_state_reg[0]), .Y(n2591) );
NAND2X2TS U3173 ( .A(n2591), .B(inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(
n2593) );
MXI2X1TS U3174 ( .A(beg_OP), .B(n2592), .S0(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n2594) );
OAI21X1TS U3175 ( .A0(n2594), .A1(n2654), .B0(n2593), .Y(n951) );
INVX2TS U3176 ( .A(n1342), .Y(n2596) );
NAND2X2TS U3177 ( .A(n1039), .B(n2596), .Y(n3653) );
NAND2X2TS U3178 ( .A(n1259), .B(n2597), .Y(n3647) );
NAND2X2TS U3179 ( .A(n1259), .B(n2598), .Y(n3632) );
NAND2X2TS U3180 ( .A(n1259), .B(n2599), .Y(n3623) );
NAND2X2TS U3181 ( .A(n1259), .B(n1520), .Y(n3626) );
NAND2X2TS U3182 ( .A(n1259), .B(n2600), .Y(n3629) );
MXI2X1TS U3183 ( .A(n2611), .B(inst_FSM_INPUT_ENABLE_state_reg[0]), .S0(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
CLKMX2X2TS U3184 ( .A(DMP_SHT1_EWSW[13]), .B(n2612), .S0(n2621), .Y(n760) );
CLKMX2X2TS U3185 ( .A(DMP_SHT1_EWSW[10]), .B(n2613), .S0(n2621), .Y(n769) );
CLKMX2X2TS U3186 ( .A(DMP_SHT1_EWSW[7]), .B(n2614), .S0(n2621), .Y(n778) );
CLKMX2X2TS U3187 ( .A(DMP_SHT1_EWSW[5]), .B(n2615), .S0(n2621), .Y(n784) );
CLKMX2X2TS U3188 ( .A(DMP_SHT1_EWSW[4]), .B(n2616), .S0(n2621), .Y(n787) );
CLKMX2X2TS U3189 ( .A(DMP_SHT1_EWSW[9]), .B(n2617), .S0(n2621), .Y(n772) );
CLKMX2X2TS U3190 ( .A(DMP_SHT1_EWSW[11]), .B(n2618), .S0(n2621), .Y(n766) );
CLKMX2X2TS U3191 ( .A(DMP_SHT1_EWSW[6]), .B(n2619), .S0(n2621), .Y(n781) );
CLKMX2X2TS U3192 ( .A(DMP_SHT1_EWSW[12]), .B(n2620), .S0(n2621), .Y(n763) );
CLKMX2X2TS U3193 ( .A(DMP_SHT1_EWSW[8]), .B(n2622), .S0(n2621), .Y(n775) );
CLKMX2X2TS U3194 ( .A(DmP_mant_SHT1_SW[19]), .B(n2623), .S0(n2632), .Y(n651)
);
CLKMX2X2TS U3195 ( .A(DmP_mant_SHT1_SW[18]), .B(n2624), .S0(n2632), .Y(n653)
);
NAND3X1TS U3196 ( .A(n3154), .B(n3153), .C(n3152), .Y(n2651) );
CLKMX2X2TS U3197 ( .A(DmP_mant_SHT1_SW[17]), .B(n2651), .S0(n2632), .Y(n655)
);
NAND3X1TS U3198 ( .A(n3100), .B(n3099), .C(n3098), .Y(n2690) );
CLKMX2X2TS U3199 ( .A(DmP_mant_SHT1_SW[3]), .B(n2690), .S0(n2633), .Y(n683)
);
NAND3X1TS U3200 ( .A(n3097), .B(n3096), .C(n3095), .Y(n2692) );
CLKMX2X2TS U3201 ( .A(DmP_mant_SHT1_SW[2]), .B(n2692), .S0(n2633), .Y(n685)
);
CLKMX2X2TS U3202 ( .A(DMP_SHT1_EWSW[0]), .B(n2625), .S0(n2633), .Y(n799) );
NAND3X1TS U3203 ( .A(n3139), .B(n3138), .C(n3137), .Y(n2649) );
CLKMX2X2TS U3204 ( .A(DmP_mant_SHT1_SW[14]), .B(n2649), .S0(n2632), .Y(n661)
);
NAND3X1TS U3205 ( .A(n3106), .B(n3105), .C(n3104), .Y(n2694) );
CLKMX2X2TS U3206 ( .A(DmP_mant_SHT1_SW[5]), .B(n2694), .S0(n2633), .Y(n679)
);
CLKMX2X2TS U3207 ( .A(DMP_SHT1_EWSW[2]), .B(n2626), .S0(n2633), .Y(n793) );
NAND3X1TS U3208 ( .A(n3115), .B(n3114), .C(n3113), .Y(n2691) );
CLKMX2X2TS U3209 ( .A(DmP_mant_SHT1_SW[12]), .B(n2691), .S0(n2633), .Y(n665)
);
CLKMX2X2TS U3210 ( .A(DMP_SHT1_EWSW[3]), .B(n2627), .S0(n2633), .Y(n790) );
NAND3X1TS U3211 ( .A(n3136), .B(n3135), .C(n3134), .Y(n2650) );
CLKMX2X2TS U3212 ( .A(DmP_mant_SHT1_SW[9]), .B(n2650), .S0(n2632), .Y(n671)
);
NAND3X1TS U3213 ( .A(n3142), .B(n3141), .C(n3140), .Y(n2648) );
CLKMX2X2TS U3214 ( .A(DmP_mant_SHT1_SW[15]), .B(n2648), .S0(n2632), .Y(n659)
);
CLKMX2X2TS U3215 ( .A(DmP_mant_SHT1_SW[20]), .B(n2628), .S0(n2632), .Y(n649)
);
CLKMX2X2TS U3216 ( .A(DmP_mant_SHT1_SW[21]), .B(n2629), .S0(n2632), .Y(n647)
);
CLKMX2X2TS U3217 ( .A(DMP_SHT1_EWSW[1]), .B(n2630), .S0(n2633), .Y(n796) );
NAND3X1TS U3218 ( .A(n3103), .B(n3102), .C(n3101), .Y(n2687) );
CLKMX2X2TS U3219 ( .A(DmP_mant_SHT1_SW[4]), .B(n2687), .S0(n2633), .Y(n681)
);
CLKMX2X2TS U3220 ( .A(DmP_mant_SHT1_SW[22]), .B(n2631), .S0(n2632), .Y(n645)
);
CLKMX2X2TS U3221 ( .A(DMP_SHT1_EWSW[23]), .B(n2643), .S0(n2632), .Y(n730) );
CLKMX2X2TS U3222 ( .A(OP_FLAG_SHT1), .B(OP_FLAG_EXP), .S0(n2633), .Y(n631)
);
CLKMX2X2TS U3223 ( .A(n1163), .B(DMP_exp_NRM_EW[1]), .S0(n2634), .Y(n721) );
NAND3X1TS U3224 ( .A(n3085), .B(n3084), .C(n3083), .Y(n2640) );
CLKMX2X2TS U3225 ( .A(DMP_SHT1_EWSW[22]), .B(n2640), .S0(n2639), .Y(n733) );
NAND3X1TS U3226 ( .A(n2997), .B(n2996), .C(n2995), .Y(n2637) );
CLKMX2X2TS U3227 ( .A(DMP_SHT1_EWSW[29]), .B(n2637), .S0(n2639), .Y(n700) );
CLKMX2X2TS U3228 ( .A(DMP_SHT1_EWSW[30]), .B(n2635), .S0(n2639), .Y(n695) );
NAND3X1TS U3229 ( .A(n3175), .B(n3174), .C(n3173), .Y(n2658) );
CLKMX2X2TS U3230 ( .A(SIGN_FLAG_SHT1), .B(n2658), .S0(n2639), .Y(n626) );
CLKMX2X2TS U3231 ( .A(DMP_SHT1_EWSW[24]), .B(n2645), .S0(n2639), .Y(n725) );
CLKMX2X2TS U3232 ( .A(DMP_SHT1_EWSW[26]), .B(n2644), .S0(n2639), .Y(n715) );
CLKMX2X2TS U3233 ( .A(DMP_SHT1_EWSW[28]), .B(n2636), .S0(n2639), .Y(n705) );
MXI2X1TS U3234 ( .A(n2799), .B(n2926), .S0(n1255), .Y(n620) );
NAND3X1TS U3235 ( .A(n3130), .B(n3129), .C(n3128), .Y(n2683) );
NAND2X1TS U3236 ( .A(n2638), .B(n2683), .Y(n3477) );
NAND3X1TS U3237 ( .A(n3151), .B(n3150), .C(n3149), .Y(n2684) );
NAND2X1TS U3238 ( .A(n2638), .B(n2684), .Y(n3486) );
NAND3X1TS U3239 ( .A(n3145), .B(n3144), .C(n3143), .Y(n2679) );
NAND2X1TS U3240 ( .A(n2638), .B(n2679), .Y(n3498) );
NAND3X1TS U3241 ( .A(n3133), .B(n3132), .C(n3131), .Y(n2680) );
NAND2X1TS U3242 ( .A(n2638), .B(n2680), .Y(n3489) );
NAND2X1TS U3243 ( .A(n2638), .B(n2637), .Y(n3603) );
CLKMX2X2TS U3244 ( .A(DMP_exp_NRM_EW[4]), .B(DMP_SFG[27]), .S0(
Shift_reg_FLAGS_7[2]), .Y(n707) );
CLKMX2X2TS U3245 ( .A(DMP_exp_NRM_EW[7]), .B(DMP_SFG[30]), .S0(
Shift_reg_FLAGS_7[2]), .Y(n692) );
CLKMX2X2TS U3246 ( .A(DMP_exp_NRM_EW[2]), .B(DMP_SFG[25]), .S0(
Shift_reg_FLAGS_7[2]), .Y(n717) );
CLKMX2X2TS U3247 ( .A(DMP_exp_NRM_EW[3]), .B(DMP_SFG[26]), .S0(
Shift_reg_FLAGS_7[2]), .Y(n712) );
MXI2X1TS U3248 ( .A(n2900), .B(n1165), .S0(n2639), .Y(n720) );
NAND2X1TS U3249 ( .A(n2652), .B(n2640), .Y(n3346) );
NAND3X1TS U3250 ( .A(n3082), .B(n3081), .C(n3080), .Y(n2671) );
NAND2X1TS U3251 ( .A(n2652), .B(n2671), .Y(n3352) );
NAND2X1TS U3252 ( .A(n2646), .B(n2642), .Y(n3415) );
NAND2X1TS U3253 ( .A(n2646), .B(n2643), .Y(n3436) );
NAND2X1TS U3254 ( .A(n2646), .B(n2644), .Y(n3421) );
NAND2X1TS U3255 ( .A(n2646), .B(n2645), .Y(n3427) );
NAND3X1TS U3256 ( .A(n3034), .B(n3033), .C(n3032), .Y(n2669) );
NAND2X1TS U3257 ( .A(n2647), .B(n2669), .Y(n3367) );
NAND3X1TS U3258 ( .A(n3049), .B(n3048), .C(n3047), .Y(n2672) );
NAND2X1TS U3259 ( .A(n2647), .B(n2672), .Y(n3349) );
NAND3X1TS U3260 ( .A(n3046), .B(n3045), .C(n3044), .Y(n2674) );
NAND2X1TS U3261 ( .A(n2647), .B(n2674), .Y(n3355) );
NAND3X1TS U3262 ( .A(n3031), .B(n3030), .C(n3029), .Y(n2668) );
NAND2X1TS U3263 ( .A(n2647), .B(n2668), .Y(n3370) );
NAND3X1TS U3264 ( .A(n3040), .B(n3039), .C(n3038), .Y(n2676) );
NAND2X1TS U3265 ( .A(n2647), .B(n2676), .Y(n3361) );
NAND3X1TS U3266 ( .A(n3037), .B(n3036), .C(n3035), .Y(n2670) );
NAND2X1TS U3267 ( .A(n2647), .B(n2670), .Y(n3364) );
NAND3X1TS U3268 ( .A(n3043), .B(n3042), .C(n3041), .Y(n2673) );
NAND2X1TS U3269 ( .A(n2647), .B(n2673), .Y(n3358) );
NAND2X1TS U3270 ( .A(n2652), .B(n2648), .Y(n3501) );
NAND2X1TS U3271 ( .A(n2652), .B(n2649), .Y(n3504) );
NAND2X1TS U3272 ( .A(n2652), .B(n2650), .Y(n3492) );
NAND2X1TS U3273 ( .A(n2652), .B(n2651), .Y(n3507) );
NAND3X1TS U3274 ( .A(n3006), .B(n3005), .C(n3004), .Y(n2681) );
NAND2X1TS U3275 ( .A(n2652), .B(n2681), .Y(n3474) );
MXI2X1TS U3276 ( .A(n2653), .B(n1710), .S0(n2667), .Y(n944) );
MXI2X4TS U3277 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n2654), .S0(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n2656) );
CLKMX2X2TS U3278 ( .A(Data_Y[13]), .B(intDY_EWSW[13]), .S0(n1116), .Y(n897)
);
CLKMX2X2TS U3279 ( .A(Data_Y[19]), .B(intDY_EWSW[19]), .S0(n1114), .Y(n891)
);
CLKMX2X2TS U3280 ( .A(Data_Y[17]), .B(intDY_EWSW[17]), .S0(n1115), .Y(n893)
);
CLKMX2X2TS U3281 ( .A(Data_X[29]), .B(n1195), .S0(n1117), .Y(n914) );
CLKMX2X3TS U3282 ( .A(Data_X[28]), .B(intDX_EWSW[28]), .S0(n1116), .Y(n915)
);
CLKMX2X2TS U3283 ( .A(Data_X[27]), .B(n1149), .S0(n1117), .Y(n916) );
CLKMX2X2TS U3284 ( .A(Data_X[23]), .B(n1158), .S0(n1118), .Y(n920) );
CLKINVX1TS U3285 ( .A(n2656), .Y(n2657) );
MXI2X1TS U3286 ( .A(n2657), .B(n2662), .S0(n2667), .Y(n950) );
CLKMX2X2TS U3287 ( .A(Data_X[31]), .B(intDX_EWSW[31]), .S0(n1118), .Y(n912)
);
MXI2X1TS U3288 ( .A(n2828), .B(n2900), .S0(n2661), .Y(n719) );
MXI2X1TS U3289 ( .A(n2659), .B(n2658), .S0(n2662), .Y(n3677) );
CLKMX2X2TS U3290 ( .A(DMP_SHT2_EWSW[0]), .B(DMP_SHT1_EWSW[0]), .S0(n2661),
.Y(n798) );
CLKMX2X2TS U3291 ( .A(DMP_SHT2_EWSW[3]), .B(DMP_SHT1_EWSW[3]), .S0(busy),
.Y(n789) );
CLKMX2X2TS U3292 ( .A(DMP_SHT2_EWSW[2]), .B(DMP_SHT1_EWSW[2]), .S0(busy),
.Y(n792) );
CLKMX2X2TS U3293 ( .A(DMP_SHT2_EWSW[1]), .B(DMP_SHT1_EWSW[1]), .S0(busy),
.Y(n795) );
CLKMX2X2TS U3294 ( .A(DMP_SHT2_EWSW[5]), .B(DMP_SHT1_EWSW[5]), .S0(busy),
.Y(n783) );
CLKMX2X2TS U3295 ( .A(OP_FLAG_SHT2), .B(OP_FLAG_SHT1), .S0(busy), .Y(n630)
);
CLKMX2X2TS U3296 ( .A(DMP_SHT2_EWSW[28]), .B(DMP_SHT1_EWSW[28]), .S0(n2661),
.Y(n704) );
CLKMX2X2TS U3297 ( .A(DMP_SHT2_EWSW[29]), .B(DMP_SHT1_EWSW[29]), .S0(n2661),
.Y(n699) );
CLKMX2X2TS U3298 ( .A(DMP_SHT2_EWSW[30]), .B(DMP_SHT1_EWSW[30]), .S0(n2661),
.Y(n694) );
CLKMX2X2TS U3299 ( .A(DMP_SHT2_EWSW[22]), .B(DMP_SHT1_EWSW[22]), .S0(n2661),
.Y(n732) );
CLKMX2X2TS U3300 ( .A(DMP_SHT2_EWSW[24]), .B(DMP_SHT1_EWSW[24]), .S0(n2661),
.Y(n724) );
CLKMX2X2TS U3301 ( .A(ZERO_FLAG_SHT2), .B(ZERO_FLAG_SHT1), .S0(n2661), .Y(
n636) );
CLKMX2X2TS U3302 ( .A(DMP_SHT2_EWSW[23]), .B(DMP_SHT1_EWSW[23]), .S0(n2661),
.Y(n729) );
CLKMX2X2TS U3303 ( .A(SIGN_FLAG_SHT2), .B(SIGN_FLAG_SHT1), .S0(n2661), .Y(
n625) );
MXI2X1TS U3304 ( .A(n2662), .B(n2678), .S0(n2667), .Y(n949) );
MXI2X1TS U3305 ( .A(n2804), .B(n2902), .S0(n2663), .Y(n737) );
MXI2X1TS U3306 ( .A(n2810), .B(n2901), .S0(n2664), .Y(n755) );
MXI2X1TS U3307 ( .A(n2821), .B(n2907), .S0(n2665), .Y(n728) );
MXI2X1TS U3308 ( .A(n2809), .B(n2904), .S0(n2664), .Y(n752) );
MXI2X1TS U3309 ( .A(n2803), .B(n2903), .S0(n2664), .Y(n734) );
MXI2X1TS U3310 ( .A(n2881), .B(n2800), .S0(n2665), .Y(n629) );
NAND2X1TS U3311 ( .A(n1243), .B(n2666), .Y(n3553) );
MXI2X1TS U3312 ( .A(n2660), .B(n2801), .S0(n2667), .Y(n947) );
MXI2X1TS U3313 ( .A(n2678), .B(n2660), .S0(n2667), .Y(n948) );
CLKMX2X2TS U3314 ( .A(DMP_SHT1_EWSW[14]), .B(n2668), .S0(n2675), .Y(n757) );
CLKMX2X2TS U3315 ( .A(DMP_SHT1_EWSW[15]), .B(n2669), .S0(n2675), .Y(n754) );
CLKMX2X2TS U3316 ( .A(DMP_SHT1_EWSW[16]), .B(n2670), .S0(n2675), .Y(n751) );
CLKMX2X2TS U3317 ( .A(DMP_SHT1_EWSW[20]), .B(n2671), .S0(n2675), .Y(n739) );
CLKMX2X2TS U3318 ( .A(DMP_SHT1_EWSW[21]), .B(n2672), .S0(n2675), .Y(n736) );
CLKMX2X2TS U3319 ( .A(DMP_SHT1_EWSW[18]), .B(n2673), .S0(n2675), .Y(n745) );
CLKMX2X2TS U3320 ( .A(DMP_SHT1_EWSW[19]), .B(n2674), .S0(n2675), .Y(n742) );
CLKMX2X2TS U3321 ( .A(DMP_SHT1_EWSW[17]), .B(n2676), .S0(n2675), .Y(n748) );
MXI2X1TS U3322 ( .A(n2793), .B(n2916), .S0(n2677), .Y(n731) );
MXI2X1TS U3323 ( .A(n2798), .B(n2925), .S0(n2677), .Y(n635) );
MXI2X1TS U3324 ( .A(n2826), .B(n2920), .S0(n2677), .Y(n693) );
MXI2X1TS U3325 ( .A(n2825), .B(n2917), .S0(n2677), .Y(n713) );
MXI2X1TS U3326 ( .A(n2797), .B(n2924), .S0(n2677), .Y(n624) );
MXI2X1TS U3327 ( .A(n2795), .B(n2921), .S0(n2677), .Y(n698) );
MXI2X1TS U3328 ( .A(n2796), .B(n2923), .S0(n2677), .Y(n703) );
MXI2X1TS U3329 ( .A(n2827), .B(n2922), .S0(n2677), .Y(n708) );
MXI2X1TS U3330 ( .A(n2794), .B(n2919), .S0(n2677), .Y(n723) );
MXI2X1TS U3331 ( .A(n2828), .B(n2918), .S0(n2677), .Y(n718) );
INVX8TS U3332 ( .A(n2678), .Y(n2685) );
CLKMX2X2TS U3333 ( .A(ZERO_FLAG_SHT1), .B(ZERO_FLAG_EXP), .S0(n2685), .Y(
n637) );
CLKMX2X2TS U3334 ( .A(DmP_mant_SHT1_SW[16]), .B(n2679), .S0(n2685), .Y(n657)
);
CLKMX2X2TS U3335 ( .A(DmP_mant_SHT1_SW[6]), .B(n2680), .S0(n2685), .Y(n677)
);
NAND3X1TS U3336 ( .A(n3112), .B(n3111), .C(n3110), .Y(n2693) );
CLKMX2X2TS U3337 ( .A(DmP_mant_SHT1_SW[11]), .B(n2693), .S0(n2685), .Y(n667)
);
CLKMX2X2TS U3338 ( .A(DmP_mant_SHT1_SW[0]), .B(n2681), .S0(n2685), .Y(n689)
);
NAND3X1TS U3339 ( .A(n3118), .B(n3117), .C(n3116), .Y(n2689) );
CLKMX2X2TS U3340 ( .A(DmP_mant_SHT1_SW[13]), .B(n2689), .S0(n2685), .Y(n663)
);
CLKMX2X2TS U3341 ( .A(DmP_mant_SHT1_SW[8]), .B(n2682), .S0(n2685), .Y(n673)
);
CLKMX2X2TS U3342 ( .A(DmP_mant_SHT1_SW[1]), .B(n2683), .S0(n2685), .Y(n687)
);
CLKMX2X2TS U3343 ( .A(DmP_mant_SHT1_SW[7]), .B(n2684), .S0(n2685), .Y(n675)
);
NAND3X1TS U3344 ( .A(n3109), .B(n3108), .C(n3107), .Y(n2686) );
CLKMX2X2TS U3345 ( .A(DmP_mant_SHT1_SW[10]), .B(n2686), .S0(n2685), .Y(n669)
);
CLKMX2X2TS U3346 ( .A(Data_Y[7]), .B(intDY_EWSW[7]), .S0(n1118), .Y(n903) );
CLKMX2X2TS U3347 ( .A(Data_Y[15]), .B(intDY_EWSW[15]), .S0(n1113), .Y(n895)
);
CLKMX2X2TS U3348 ( .A(Data_Y[11]), .B(intDY_EWSW[11]), .S0(n1119), .Y(n899)
);
CLKMX2X2TS U3349 ( .A(Data_Y[5]), .B(intDY_EWSW[5]), .S0(n1118), .Y(n905) );
CLKMX2X2TS U3350 ( .A(Data_Y[18]), .B(intDY_EWSW[18]), .S0(n1116), .Y(n892)
);
CLKMX2X2TS U3351 ( .A(Data_Y[0]), .B(intDY_EWSW[0]), .S0(n1114), .Y(n910) );
NAND2X1TS U3352 ( .A(n2927), .B(n2686), .Y(n3465) );
NAND2X1TS U3353 ( .A(n2927), .B(n2687), .Y(n3445) );
NAND2X1TS U3354 ( .A(n2927), .B(n2688), .Y(n3442) );
NAND2X1TS U3355 ( .A(n2927), .B(n2689), .Y(n3468) );
NAND2X1TS U3356 ( .A(n2927), .B(n2690), .Y(n3448) );
NAND2X1TS U3357 ( .A(n2927), .B(n2691), .Y(n3459) );
NAND2X1TS U3358 ( .A(n2927), .B(n2692), .Y(n3451) );
NAND2X1TS U3359 ( .A(n2927), .B(n2693), .Y(n3462) );
NAND2X1TS U3360 ( .A(n2927), .B(n2694), .Y(n3454) );
NAND2X1TS U3361 ( .A(n2927), .B(n2695), .Y(n3439) );
NAND2X1TS U3362 ( .A(n2790), .B(sub_x_5_n203), .Y(n2696) );
XOR2X1TS U3363 ( .A(n2696), .B(sub_x_5_n204), .Y(n2699) );
OR2X2TS U3364 ( .A(add_x_6_A_2_), .B(n1382), .Y(n2697) );
CLKMX2X2TS U3365 ( .A(DMP_SHT2_EWSW[18]), .B(DMP_SHT1_EWSW[18]), .S0(busy),
.Y(n744) );
CLKMX2X2TS U3366 ( .A(DMP_SHT2_EWSW[17]), .B(DMP_SHT1_EWSW[17]), .S0(busy),
.Y(n747) );
CLKMX2X2TS U3367 ( .A(DMP_SHT2_EWSW[19]), .B(DMP_SHT1_EWSW[19]), .S0(busy),
.Y(n741) );
CLKMX2X2TS U3368 ( .A(DMP_SHT2_EWSW[21]), .B(DMP_SHT1_EWSW[21]), .S0(busy),
.Y(n735) );
CLKMX2X2TS U3369 ( .A(DMP_SHT2_EWSW[20]), .B(DMP_SHT1_EWSW[20]), .S0(busy),
.Y(n738) );
INVX2TS U3370 ( .A(n2701), .Y(n2703) );
NAND2X1TS U3371 ( .A(n2703), .B(n2702), .Y(n2705) );
XOR2X1TS U3372 ( .A(n2705), .B(n2704), .Y(n2706) );
AOI22X1TS U3373 ( .A0(n2706), .A1(n2718), .B0(Raw_mant_NRM_SWR[3]), .B1(
n2717), .Y(n2707) );
INVX8TS U3374 ( .A(n2928), .Y(n2709) );
CLKMX2X2TS U3375 ( .A(DMP_SHT2_EWSW[13]), .B(DMP_SHT1_EWSW[13]), .S0(n2709),
.Y(n759) );
CLKMX2X2TS U3376 ( .A(DMP_SHT2_EWSW[15]), .B(DMP_SHT1_EWSW[15]), .S0(n2709),
.Y(n753) );
CLKMX2X2TS U3377 ( .A(DMP_SHT2_EWSW[9]), .B(DMP_SHT1_EWSW[9]), .S0(n2709),
.Y(n771) );
CLKMX2X2TS U3378 ( .A(DMP_SHT2_EWSW[10]), .B(DMP_SHT1_EWSW[10]), .S0(n2709),
.Y(n768) );
CLKMX2X2TS U3379 ( .A(DMP_SHT2_EWSW[8]), .B(DMP_SHT1_EWSW[8]), .S0(n2709),
.Y(n774) );
CLKMX2X2TS U3380 ( .A(DMP_SHT2_EWSW[16]), .B(DMP_SHT1_EWSW[16]), .S0(n2709),
.Y(n750) );
CLKMX2X2TS U3381 ( .A(DMP_SHT2_EWSW[14]), .B(DMP_SHT1_EWSW[14]), .S0(n2709),
.Y(n756) );
CLKMX2X2TS U3382 ( .A(DMP_SHT2_EWSW[11]), .B(DMP_SHT1_EWSW[11]), .S0(n2709),
.Y(n765) );
CLKMX2X2TS U3383 ( .A(DMP_SHT2_EWSW[7]), .B(DMP_SHT1_EWSW[7]), .S0(n2709),
.Y(n777) );
CLKMX2X2TS U3384 ( .A(DMP_SHT2_EWSW[12]), .B(DMP_SHT1_EWSW[12]), .S0(n2709),
.Y(n762) );
NAND2X1TS U3385 ( .A(n1074), .B(n2711), .Y(n2712) );
XNOR2X1TS U3386 ( .A(n2713), .B(n2712), .Y(n2721) );
NAND2X1TS U3387 ( .A(n2763), .B(n2714), .Y(n2715) );
XOR2X1TS U3388 ( .A(n2716), .B(n2715), .Y(n2719) );
AOI22X1TS U3389 ( .A0(n2719), .A1(n2718), .B0(Raw_mant_NRM_SWR[4]), .B1(
n2717), .Y(n2720) );
AOI22X1TS U3390 ( .A0(n2724), .A1(n1202), .B0(n1242), .B1(n2723), .Y(n3481)
);
NAND2X1TS U3391 ( .A(n2726), .B(intDX_EWSW[4]), .Y(n3447) );
NAND2X1TS U3392 ( .A(n2726), .B(intDY_EWSW[27]), .Y(n3417) );
NAND2X1TS U3393 ( .A(n2726), .B(intDY_EWSW[23]), .Y(n3438) );
NAND2X1TS U3394 ( .A(n2726), .B(intDY_EWSW[19]), .Y(n3357) );
NAND2X1TS U3395 ( .A(n1247), .B(intDY_EWSW[17]), .Y(n3363) );
NAND2X1TS U3396 ( .A(n2726), .B(intDY_EWSW[20]), .Y(n3354) );
NAND2X1TS U3397 ( .A(n1247), .B(intDY_EWSW[21]), .Y(n3351) );
NAND2X1TS U3398 ( .A(n1247), .B(intDY_EWSW[18]), .Y(n3360) );
NAND2X1TS U3399 ( .A(n1247), .B(intDY_EWSW[6]), .Y(n3396) );
NAND2X1TS U3400 ( .A(n1247), .B(intDY_EWSW[0]), .Y(n3414) );
NAND2X1TS U3401 ( .A(n1227), .B(n1190), .Y(n3365) );
NAND2X1TS U3402 ( .A(n1227), .B(n1184), .Y(n3347) );
NAND2X1TS U3403 ( .A(n1227), .B(n1177), .Y(n3395) );
NAND2X1TS U3404 ( .A(n1227), .B(intDX_EWSW[24]), .Y(n3428) );
NAND2X1TS U3405 ( .A(n1227), .B(n1154), .Y(n3371) );
NAND2X1TS U3406 ( .A(n1227), .B(n1178), .Y(n3404) );
NAND2X1TS U3407 ( .A(n1227), .B(intDY_EWSW[3]), .Y(n3449) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk1.tcl_syn.sdf");
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Fri Oct 27 10:19:56 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/RATCPU/Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Mux2x1_10_0_0/RAT_Mux2x1_10_0_0_sim_netlist.v
// Design : RAT_Mux2x1_10_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "RAT_Mux2x1_10_0_0,Mux2x1_10,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "Mux2x1_10,Vivado 2016.4" *)
(* NotValidForBitStream *)
module RAT_Mux2x1_10_0_0
(A,
B,
SEL,
X);
input [9:0]A;
input [9:0]B;
input SEL;
output [9:0]X;
wire [9:0]A;
wire [9:0]B;
wire SEL;
wire [9:0]X;
RAT_Mux2x1_10_0_0_Mux2x1_10 U0
(.A(A),
.B(B),
.SEL(SEL),
.X(X));
endmodule
(* ORIG_REF_NAME = "Mux2x1_10" *)
module RAT_Mux2x1_10_0_0_Mux2x1_10
(X,
B,
A,
SEL);
output [9:0]X;
input [9:0]B;
input [9:0]A;
input SEL;
wire [9:0]A;
wire [9:0]B;
wire SEL;
wire [9:0]X;
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'hAC))
\X[0]_INST_0
(.I0(B[0]),
.I1(A[0]),
.I2(SEL),
.O(X[0]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'hAC))
\X[1]_INST_0
(.I0(B[1]),
.I1(A[1]),
.I2(SEL),
.O(X[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'hAC))
\X[2]_INST_0
(.I0(B[2]),
.I1(A[2]),
.I2(SEL),
.O(X[2]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'hAC))
\X[3]_INST_0
(.I0(B[3]),
.I1(A[3]),
.I2(SEL),
.O(X[3]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hAC))
\X[4]_INST_0
(.I0(B[4]),
.I1(A[4]),
.I2(SEL),
.O(X[4]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hAC))
\X[5]_INST_0
(.I0(B[5]),
.I1(A[5]),
.I2(SEL),
.O(X[5]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hAC))
\X[6]_INST_0
(.I0(B[6]),
.I1(A[6]),
.I2(SEL),
.O(X[6]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hAC))
\X[7]_INST_0
(.I0(B[7]),
.I1(A[7]),
.I2(SEL),
.O(X[7]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'hAC))
\X[8]_INST_0
(.I0(B[8]),
.I1(A[8]),
.I2(SEL),
.O(X[8]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'hAC))
\X[9]_INST_0
(.I0(B[9]),
.I1(A[9]),
.I2(SEL),
.O(X[9]));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
* HIFIFO: Harmon Instruments PCI Express to FIFO
* Copyright (C) 2014 Harmon Instruments, LLC
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/
*/
`timescale 1ns/1ps
module hififo_fetch_descriptor
(
input clock,
input reset,
output [AMSB:0] request_addr,
output request_valid,
input request_ack,
input [DMSB:0] wdata,
input wvalid,
output [SMSB:0] status,
output interrupt
);
parameter BS = 0; // bit shift, number of LSBs to ignore in address
parameter AMSB = 63; // address MSB
parameter DMSB = 63; // data MSB
parameter SMSB = 31; // status MSB
parameter CBITS = 22; // count bits
parameter CMSB = CBITS - 1; // count MSB
reg [CMSB-BS:0] p_current = 0, p_interrupt = 0, p_stop = 0;
reg reset_or_abort;
reg abort = 1;
reg [AMSB-CBITS:0] addr_high;
wire write_interrupt = wvalid && (wdata[2:0] == 1);
wire write_stop = wvalid && (wdata[2:0] == 2);
wire write_addr_high = wvalid && (wdata[2:0] == 3);
wire write_abort = wvalid && (wdata[2:0] == 4);
assign request_addr = {addr_high,p_current,{BS{1'b0}}};
assign request_valid = (p_current != p_stop) && ~request_ack;
assign status = {p_current, {BS{1'b0}}};
always @ (posedge clock)
begin
reset_or_abort <= reset | abort;
if(write_abort)
abort <= wdata[8];
if(write_addr_high)
addr_high <= wdata[AMSB:CBITS];
p_stop <= reset_or_abort ? 1'b0 :
write_stop ? wdata[CMSB:BS] : p_stop;
if(write_interrupt)
p_interrupt <= wdata[CMSB:BS];
p_current <= reset_or_abort ? 1'b0 : p_current + request_ack;
end
one_shot one_shot_i0
(.clock(clock),
.in(p_current == p_interrupt),
.out(interrupt));
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21BO_SYMBOL_V
`define SKY130_FD_SC_HDLL__A21BO_SYMBOL_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a21bo (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21BO_SYMBOL_V
|
module ledtest (
clk_clk,
hps_io_hps_io_emac1_inst_TX_CLK,
hps_io_hps_io_emac1_inst_TXD0,
hps_io_hps_io_emac1_inst_TXD1,
hps_io_hps_io_emac1_inst_TXD2,
hps_io_hps_io_emac1_inst_TXD3,
hps_io_hps_io_emac1_inst_RXD0,
hps_io_hps_io_emac1_inst_MDIO,
hps_io_hps_io_emac1_inst_MDC,
hps_io_hps_io_emac1_inst_RX_CTL,
hps_io_hps_io_emac1_inst_TX_CTL,
hps_io_hps_io_emac1_inst_RX_CLK,
hps_io_hps_io_emac1_inst_RXD1,
hps_io_hps_io_emac1_inst_RXD2,
hps_io_hps_io_emac1_inst_RXD3,
jtag_debug_master_reset_reset,
led_array_io_export,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
switch_array_io_export);
input clk_clk;
output hps_io_hps_io_emac1_inst_TX_CLK;
output hps_io_hps_io_emac1_inst_TXD0;
output hps_io_hps_io_emac1_inst_TXD1;
output hps_io_hps_io_emac1_inst_TXD2;
output hps_io_hps_io_emac1_inst_TXD3;
input hps_io_hps_io_emac1_inst_RXD0;
inout hps_io_hps_io_emac1_inst_MDIO;
output hps_io_hps_io_emac1_inst_MDC;
input hps_io_hps_io_emac1_inst_RX_CTL;
output hps_io_hps_io_emac1_inst_TX_CTL;
input hps_io_hps_io_emac1_inst_RX_CLK;
input hps_io_hps_io_emac1_inst_RXD1;
input hps_io_hps_io_emac1_inst_RXD2;
input hps_io_hps_io_emac1_inst_RXD3;
output jtag_debug_master_reset_reset;
output [7:0] led_array_io_export;
output [14:0] memory_mem_a;
output [2:0] memory_mem_ba;
output memory_mem_ck;
output memory_mem_ck_n;
output memory_mem_cke;
output memory_mem_cs_n;
output memory_mem_ras_n;
output memory_mem_cas_n;
output memory_mem_we_n;
output memory_mem_reset_n;
inout [31:0] memory_mem_dq;
inout [3:0] memory_mem_dqs;
inout [3:0] memory_mem_dqs_n;
output memory_mem_odt;
output [3:0] memory_mem_dm;
input memory_oct_rzqin;
input [3:0] switch_array_io_export;
endmodule
|
/**
* Embedded System in Soongsil University
* Author : Namyun Kim, Hanter Jung
* Date : 19. June. 2014
**/
module ElevatorSimulator(clk,push_btns,motor_out,dot_col,dot_row);
input clk;
input [8:0] push_btns;
output [3:0] motor_out;
output [11:0] dot_col, dot_row;
reg [3:0] motor_out;
reg motor_count;
reg motor_dir;
reg motor_power;
// About elevator control
reg [8:0] ready_queue [2:0];
reg [1:0] current;
reg [1:0] direction;
reg input_status;
// Initialize variables
initial
begin
// Motor
motor_count = 0;
motor_dir = 0;
motor_power = 0;
motor_out = 0;
ready_queue[0] = 8'd1; // Located at 1st floor at first time
ready_queue[1] = 8'd1; // Located at 1st floor at first time
current = 0;
direction = 0;
input_status = 0;
end
// Push buttons
always@(posedge push_btns[0])
begin
if(input_status == 0)
begin
input_status = 1;
end
else if(input_status == 1)
begin
input_status = 0;
end
end
// Motor Control
always@(posedge clk)
begin
if(motor_power == 0)
begin
if(motor_count == 30'd960000)
begin
case(motor_dir)
1'b0: begin motor_out = 4'b1001; end
1'b1: begin motor_out = 4'b0101; end
endcase
motor_count = 0;
end
else if(motor_count == 30'd240000)
begin
case(motor_dir)
1'b0: begin motor_out = 4'b1010; end
1'b1: begin motor_out = 4'b0110; end
endcase
motor_count = motor_count + 1;
end
else if(motor_count == 30'd480000)
begin
case(motor_dir)
1'b0: begin motor_out = 4'b0110; end
1'b1: begin motor_out = 4'b1010; end
endcase
motor_count = motor_count + 1;
end
else if(motor_count == 30'd720000)
begin
case(motor_dir)
1'b0: begin motor_out = 4'b0101; end
1'b1: begin motor_out = 4'b1001; end
endcase
motor_count = motor_count + 1;
end
else
begin
motor_count = motor_count + 1;
end
end
end
// Elevator Schduling Algorithm
function schedule;
input current;
input destination;
begin
reg min = minimum((destination-current[0]),(destination-current[1]));
// Check same direction
// Check ready queue
end
endfunction
// Get Ready Queue Status
function get_ready_status;
input elevator;
begin
reg ready_count = 0, i;
for(i = 0; i < 10; i = i+1)
begin
if(ready_queue[elevator][i] == 1)
begin
ready_count = ready_count + 1;
end
end
end
endfunction
// Get minimum
function minimum;
input a,b;
begin
minimum = (a<=b)?0:1;
end
endfunction
endmodule |
module Create (Init, creaenhe, D, rst, RS, RW, Out_display, MsbOD, clk, scrinit);
input Init;
input creaenhe;
input clk;
input [2:0] scrinit;
input [6:0] D;
input rst;
output reg MsbOD;
output reg [6:0] Out_display;
output reg RS;
output reg RW;
always @(negedge clk) begin
if(rst) begin
MsbOD=0;
Out_display=7'b0;
end
else begin
case (scrinit)
3'b001: begin
Out_display={7'b0111000};
MsbOD=0;
RW=0;
RS=0;
end
3'b010: begin
Out_display={7'b0000100};
MsbOD=0;
RW=0;
RS=0;
end
3'b011: begin
Out_display={7'b0001100};
MsbOD=0;
RW=0;
RS=0;
end
3'b100: begin
Out_display={7'b0000001};
MsbOD=0;
RW=0;
RS=0;
end
3'b101: begin
Out_display={7'b0110000};
MsbOD=0;
RW=0;
RS=0;
end
default begin
if (creaenhe) begin
Out_display={7'b1101110};
MsbOD=1;
RW=0;
RS=1;
end
else begin
if(Init) begin
Out_display={7'b0000001};
MsbOD=0;
RS=0;
RW=0;
end
else begin
Out_display=D;
MsbOD=0;
RW=0;
RS=1;
end
end
end
endcase
end
end
endmodule
|
`include "datapath/pc.v"
`include "datapath/alu.v"
`include "datapath/dm.v"
`include "datapath/ext.v"
`include "datapath/im.v"
`include "datapath/npc.v"
`include "datapath/rf.v"
`include "datapath/mux.v"
`include "control/ctrl.v"
module mips (clk, rst);
input clk;
input rst;
wire [31:0] pc_next;
wire [31:0] pc_cur;
wire [31:0] ins;
wire [31:0] ext_imm;
wire [31:0] routa;
wire [31:0] routb;
wire [31:0] rin;
wire [31:0] aluSrc_mux_out;
wire [31:0] alu_out;
wire [31:0] dm_out;
wire [4:0] rWin;
wire [3:0] aluCtr;
wire branch;
wire jump;
wire regDst;
wire aluSrc;
wire regWr;
wire memWr;
wire extOp;
wire memtoReg;
wire zero;
pc pc(
.clk(clk),
.rst(rst),
.niaddr(pc_next),
.iaddr(pc_cur)
);
npc npc(
.iaddr(pc_cur),
.branch(branch),
.jump(jump),
.zero(zero),
.imm16(ins[15:0]),
.imm26(ins[25:0]),
.niaddr(pc_next)
);
im_4k im(
.iaddr(pc_cur[11:2]),
.ins(ins)
);
ext extOp_ext(
.imm16(ins[15:0]),
.extOp(extOp),
.dout(ext_imm)
);
mux #(32) aluSrc_mux(
.a(routb),
.b(ext_imm),
.ctrl_s(aluSrc),
.dout(aluSrc_mux_out)
);
mux #(5) regDst_mux(
.a(ins[20:16]),
.b(ins[15:11]),
.ctrl_s(regDst),
.dout(rWin)
);
regFile rf(
.busW(rin),
.clk(clk),
.wE(regWr),
.rW(rWin),
.rA(ins[25:21]),
.rB(ins[20:16]),
.busA(routa),
.busB(routb)
);
alu alu(
.ALUop(aluCtr),
.a(routa),
.b(aluSrc_mux_out),
.result(alu_out),
.zero(zero)
);
dm_4k dm(
.addr(alu_out[11:2]),
.din(routb),
.wEn(memWr),
.clk(clk),
.dout(dm_out)
);
mux memtoReg_mux(
.a(alu_out),
.b(dm_out),
.ctrl_s(memtoReg),
.dout(rin)
);
ctrl ctrl(
.ins(ins),
.branch(branch),
.jump(jump),
.regDst(regDst),
.aluSrc(aluSrc),
.aluCtr(aluCtr),
.regWr(regWr),
.memWr(memWr),
.extOp(extOp),
.memtoReg(memtoReg)
);
endmodule // MIPS main program;
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_28_V
`define SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_28_V
/**
* sleep_sergate_plv: connect vpr to virtpwr when not in sleep mode.
*
* Verilog wrapper for sleep_sergate_plv with size of 28 units
* (invalid?).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sleep_sergate_plv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sleep_sergate_plv_28 (
VIRTPWR,
SLEEP ,
VPWR ,
VPB ,
VNB
);
output VIRTPWR;
input SLEEP ;
input VPWR ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sleep_sergate_plv base (
.VIRTPWR(VIRTPWR),
.SLEEP(SLEEP),
.VPWR(VPWR),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sleep_sergate_plv_28 (
VIRTPWR,
SLEEP
);
output VIRTPWR;
input SLEEP ;
// Voltage supply signals
supply1 VPWR;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sleep_sergate_plv base (
.VIRTPWR(VIRTPWR),
.SLEEP(SLEEP)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_28_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__XOR3_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__XOR3_PP_BLACKBOX_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__xor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__XOR3_PP_BLACKBOX_V
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
module altera_up_video_dma_control_slave (
// Inputs
clk,
reset,
address,
byteenable,
read,
write,
writedata,
swap_addresses_enable,
// Bi-Directional
// Outputs
readdata,
current_start_address,
dma_enabled
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
// Parameters
parameter DEFAULT_BUFFER_ADDRESS = 32'h00000000;
parameter DEFAULT_BACK_BUF_ADDRESS = 32'h00000000;
parameter WIDTH = 640; // Frame's width in pixels
parameter HEIGHT = 480; // Frame's height in lines
parameter ADDRESSING_BITS = 16'h0809;
parameter COLOR_BITS = 4'h7; // Bits per color plane minus 1
parameter COLOR_PLANES = 2'h2; // Color planes per pixel minus 1
parameter ADDRESSING_MODE = 1'b1; // 0: X-Y or 1: Consecutive
parameter DEFAULT_DMA_ENABLED = 1'b1; // 0: OFF or 1: ON
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [ 1: 0] address;
input [ 3: 0] byteenable;
input read;
input write;
input [31: 0] writedata;
input swap_addresses_enable;
// Bi-Directional
// Outputs
output reg [31: 0] readdata;
output [31: 0] current_start_address;
output reg dma_enabled;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg [31: 0] buffer_start_address;
reg [31: 0] back_buf_start_address;
reg buffer_swap;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
readdata <= 32'h00000000;
else if (read & (address == 2'h0))
readdata <= buffer_start_address;
else if (read & (address == 2'h1))
readdata <= back_buf_start_address;
else if (read & (address == 2'h2))
begin
readdata[31:16] <= HEIGHT;
readdata[15: 0] <= WIDTH;
end
else if (read)
begin
readdata[31:16] <= ADDRESSING_BITS;
readdata[15:12] <= 4'h0;
readdata[11: 8] <= COLOR_BITS;
readdata[ 7: 6] <= COLOR_PLANES;
readdata[ 5: 3] <= 3'h0;
readdata[ 2] <= dma_enabled;
readdata[ 1] <= ADDRESSING_MODE;
readdata[ 0] <= buffer_swap;
end
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
begin
buffer_start_address <= DEFAULT_BUFFER_ADDRESS;
back_buf_start_address <= DEFAULT_BACK_BUF_ADDRESS;
end
else if (write & (address == 2'h1))
begin
if (byteenable[0])
back_buf_start_address[ 7: 0] <= writedata[ 7: 0];
if (byteenable[1])
back_buf_start_address[15: 8] <= writedata[15: 8];
if (byteenable[2])
back_buf_start_address[23:16] <= writedata[23:16];
if (byteenable[3])
back_buf_start_address[31:24] <= writedata[31:24];
end
else if (buffer_swap & swap_addresses_enable)
begin
buffer_start_address <= back_buf_start_address;
back_buf_start_address <= buffer_start_address;
end
end
always @(posedge clk)
begin
if (reset)
buffer_swap <= 1'b0;
else if (write & (address == 2'h0))
buffer_swap <= 1'b1;
else if (swap_addresses_enable)
buffer_swap <= 1'b0;
end
always @(posedge clk)
begin
if (reset)
dma_enabled <= DEFAULT_DMA_ENABLED;
else if (write & (address == 2'h3) & byteenable[0])
dma_enabled <= writedata[2];
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign current_start_address = buffer_start_address;
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND4BB_BEHAVIORAL_V
`define SKY130_FD_SC_HS__NAND4BB_BEHAVIORAL_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nand4bb (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND
);
// Module ports
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
// Local signals
wire D nand0_out ;
wire or0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , D, C );
or or0 (or0_out_Y , B_N, A_N, nand0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND4BB_BEHAVIORAL_V |
module ctrl (ins, branch, jump, regDst, aluSrc, aluCtr, regWr, memWr, extOp, memtoReg);
input [31:0] ins;
output reg [3:0] aluCtr;
output reg branch;
output reg jump;
output reg regDst;
output reg aluSrc;
output reg regWr;
output reg memWr;
output reg extOp;
output reg memtoReg;
wire [5:0] op;
wire [5:0] func;
assign op = ins[31:26];
assign func = ins[5:0];
// Operation code;
parameter R = 6'b000000,
LW = 6'b100011,
SW = 6'b101011,
BEQ = 6'b000100,
J = 6'b000010,
ORI = 6'b001101;
// Function code;
parameter ADD = 6'b100000,
ADDU = 6'b100001,
SUB = 6'b100010,
SUBU = 6'b100011,
AND = 6'b100100,
OR = 6'b100101,
SLT = 6'b101010,
SLTU = 6'b101011;
always @ ( * ) begin
case (op)
R: begin// R-Type Instructions;
branch = 0;
jump = 0;
regDst = 1;
aluSrc = 0;
memtoReg = 0;
regWr = 1;
memWr = 0;
case (func)
ADD: aluCtr = 4'b0001;
ADDU: aluCtr = 4'b0000;
SUB: aluCtr = 4'b1001;
SUBU: aluCtr = 4'b1000;
AND: aluCtr = 4'b0010;
OR: aluCtr = 4'b0011;
SLT: aluCtr = 4'b1011;
SLTU: aluCtr = 4'b1010;
endcase
end
LW: begin// Load word;
branch = 0;
jump = 0;
regDst = 0;
aluSrc = 1;
memtoReg = 1;
regWr = 1;
memWr = 0;
extOp = 1;
aluCtr = 4'b0001;// add;
end
SW: begin// Store word;
branch = 0;
jump = 0;
aluSrc = 1;
regWr = 0;
memWr = 1;
extOp = 1;
aluCtr = 4'b0001;// add;
end
BEQ: begin// Branch on equal;
branch = 1;
jump = 0;
aluSrc = 0;
regWr = 0;
memWr = 0;
end
J: begin// J-Type Instructions；
branch = 0;
jump = 1;
regWr = 0;
memWr = 0;
end
ORI: begin// Or immediate;
branch = 0;
jump = 0;
regDst = 0;
aluSrc = 1;
memtoReg = 0;
regWr = 1;
memWr = 0;
extOp = 0;
aluCtr = 4'b0011;
end
endcase
end
endmodule // Control;
|
`include "assert.vh"
`include "cpu.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 6;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("br_table2.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
parameter HAS_FPU = 1;
parameter USE_64B = 1;
reg reset = 0;
wire [63:0] result;
wire [ 1:0] result_type;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.HAS_FPU(HAS_FPU),
.USE_64B(USE_64B),
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_type(result_type),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("br_table2_tb.vcd");
$dumpvars(0, cpu_tb);
if(USE_64B) begin
#72
`assert(result, 7);
`assert(result_type, `i64);
`assert(result_empty, 0);
`assert(trap, `ENDED);
end
else begin
#24
`assert(trap, `NO_64B);
end
$finish;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:11:30 08/20/2015
// Design Name:
// Module Name: Sixth_Phase
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Comparators
//Module Parameter
//W_Exp = 9 ; Single Precision Format
//W_Exp = 11; Double Precision Format
# (parameter W_Exp = 9)
/* # (parameter W_Exp = 12)*/
(
input wire [W_Exp-1:0] exp, //exponent of the fifth phase
output wire overflow, //overflow flag
output wire underflow //underflow flag
);
wire [W_Exp-1:0] U_limit; //Max Normal value of the standar ieee 754
wire [W_Exp-1:0] L_limit; //Min Normal value of the standar ieee 754
//Compares the exponent with the Max Normal Value, if the exponent is
//larger than U_limit then exist overflow
Greater_Comparator #(.W(W_Exp)) GTComparator (
.Data_A(exp),
.Data_B(U_limit),
.gthan(overflow)
);
//Compares the exponent with the Min Normal Value, if the exponent is
//smaller than L_limit then exist underflow
Comparator_Less #(.W(W_Exp)) LTComparator (
.Data_A(exp),
.Data_B(L_limit),
.less(underflow)
);
//This generate sentence creates the limit values based on the
//precision format
generate
if(W_Exp == 9) begin : LIMASSIGN_EXP_SGF_BLK1
assign U_limit = 9'hfe;
assign L_limit = 9'h01;
end
else begin : LIMASSIGN_EXP_SGF_BLK2
assign U_limit = 12'b111111111110;
assign L_limit = 12'b000000000001;
end
endgenerate
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_dtl_edgelogic.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// _____________________________________________________________________________
//
// bw_io_dtl_edgelogic -- DTL edge logic.
// _____________________________________________________________________________
//
module bw_io_dtl_edgelogic (/*AUTOARG*/
// Outputs
pad_up, pad_dn_l, pad_dn25_l, pad_clk_en_l, cmsi_clk_en_l, cmsi_l, se_buf,
bsr_up, bsr_dn_l, bsr_dn25_l, por,
// Inputs
data, oe, si, reset_l, sel_bypass, clk, bsr_mode, up_open, down_25, por_l,
se, bsr_data_to_core
);
input data;
input oe;
input si;
input reset_l;
input sel_bypass;
input clk;
input bsr_mode;
input up_open;
input down_25;
input por_l;
input se;
input bsr_data_to_core;
output pad_up;
output pad_dn_l;
output pad_dn25_l;
output pad_clk_en_l;
output cmsi_clk_en_l;
output cmsi_l;
output se_buf;
output bsr_up;
output bsr_dn_l;
output bsr_dn25_l;
output por;
reg cmsi_l;
reg edgelogic_so;
reg bypass_data;
reg net223;
reg pad_dn25_l;
reg net229;
reg pad_dn_l;
reg net217;
reg pad_up;
wire s0 = bsr_mode && ~se;
wire s2 = ~se && ~bsr_mode && ~reset_l;
wire se_buf = se;
wire die = ~se && reset_l;
wire s3 = ~bsr_mode && die;
wire pad_clk_en_l = sel_bypass || bsr_mode || ~die;
wire cmsi_clk_en_l = ~(sel_bypass || bsr_mode || ~die);
wire dn = data || ~oe;
wire dn25 = ~down_25 || ~oe || data;
wire up = oe ? data : ~up_open;
wire por = ~por_l;
wire bsr_up = pad_up;
wire bsr_dn_l = pad_dn_l;
wire bsr_dn25_l = pad_dn25_l;
always @ (s3 or s2 or se_buf or s0 or bypass_data or edgelogic_so or bsr_data_to_core) begin
casex ({s3, bypass_data, s2, 1'b0, se_buf, edgelogic_so, s0, bsr_data_to_core})
8'b0x0x0x10: cmsi_l = 1'b1;
8'b0x0x0x11: cmsi_l = 1'b0;
8'b0x0x100x: cmsi_l = 1'b1;
8'b0x0x110x: cmsi_l = 1'b0;
8'b0x0x1010: cmsi_l = 1'b1;
8'b0x0x1111: cmsi_l = 1'b0;
8'b0x100x0x: cmsi_l = 1'b1;
8'b0x110x0x: cmsi_l = 1'b0;
8'b0x100x10: cmsi_l = 1'b1;
8'b0x110x11: cmsi_l = 1'b0;
8'b0x10100x: cmsi_l = 1'b1;
8'b0x11110x: cmsi_l = 1'b0;
8'b0x101010: cmsi_l = 1'b1;
8'b0x111111: cmsi_l = 1'b0;
8'b100x0x0x: cmsi_l = 1'b1;
8'b110x0x0x: cmsi_l = 1'b0;
8'b100x0x10: cmsi_l = 1'b1;
8'b110x0x11: cmsi_l = 1'b0;
8'b100x100x: cmsi_l = 1'b1;
8'b110x110x: cmsi_l = 1'b0;
8'b100x1010: cmsi_l = 1'b1;
8'b110x1111: cmsi_l = 1'b0;
8'b10100x0x: cmsi_l = 1'b1;
8'b11110x0x: cmsi_l = 1'b0;
8'b10100x10: cmsi_l = 1'b1;
8'b11110x11: cmsi_l = 1'b0;
8'b1010100x: cmsi_l = 1'b1;
8'b1111110x: cmsi_l = 1'b0;
8'b10101010: cmsi_l = 1'b1;
8'b11111111: cmsi_l = 1'b0;
default: cmsi_l = 1'bx;
endcase
end
always @(posedge clk) begin
if (se_buf) // flop_bypass
begin
edgelogic_so <= net223;
bypass_data <= net223;
end
else
begin
edgelogic_so <= 1'b1;
bypass_data <= data;
end
if (se_buf) // flop_dn25
begin
net223 <= net229;
pad_dn25_l <= net229;
end
else
begin
net223 <= 1'b1;
pad_dn25_l <= dn25;
end
if (se_buf) // flop_dn
begin
net229 <= net217;
pad_dn_l <= net217;
end
else
begin
net229 <= 1'b1;
pad_dn_l <= dn;
end
if (se_buf) // flop_up
begin
net217 <= si; // so
pad_up <= si; // q
end
else
begin
net217 <= 1'b1; // so
pad_up <= up; // q
end
end
endmodule
// Local Variables:
// verilog-auto-sense-defines-constant:t
// End:
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FAHCON_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__FAHCON_FUNCTIONAL_PP_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__fahcon (
COUT_N,
SUM ,
A ,
B ,
CI ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_SUM ;
wire pwrgood_pp0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_coutn ;
wire pwrgood_pp1_out_coutn;
// Name Output Other arguments
xor xor0 (xor0_out_SUM , A, B, CI );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND );
buf buf0 (SUM , pwrgood_pp0_out_SUM );
nor nor0 (a_b , A, B );
nor nor1 (a_ci , A, CI );
nor nor2 (b_ci , B, CI );
or or0 (or0_out_coutn , a_b, a_ci, b_ci );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_coutn, or0_out_coutn, VPWR, VGND);
buf buf1 (COUT_N , pwrgood_pp1_out_coutn );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__FAHCON_FUNCTIONAL_PP_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: Matt McConnell
//
// Create Date: 14:48:00 01/25/2017
// Project Name: EECS301 Digital Design
// Design Name: Lab #3 Project
// Module Name: CLS_Scanner_Module
// Target Devices: Altera Cyclone V
// Tool versions: Quartus v17.0
// Description: CLS Scanner Module
//
// Dependencies:
//
//////////////////////////////////////////////////////////////////////////////////
module CLS_Scanner_Module
#(
parameter CLK_RATE_HZ = 50000000, // 50 MHz
parameter LED_NUM = 16,
parameter PWM_DUTY_RATE = 1000, // 1 kHz
parameter FADE_RATE_HZ = 10 // 10 Hz
)
(
// Input Signals
input RIGHT_KEY_EVENT,
input LEFT_KEY_EVENT,
// Output Signals
output [LED_NUM-1:0] LED_OUT,
// System Signals
input CLK
);
///////////////////////////////////////////////////////
//
// LED Scan Rate Timer
//
wire fadeout_tick;
CLS_Fadeout_Timer
#(
.CLK_RATE_HZ( CLK_RATE_HZ ),
.FADE_RATE_HZ(FADE_RATE_HZ) //added line
)
fade_out_timer
(
// Output Signals
.FADEOUT_TICK(fadeout_tick),//changed line
// System Signals
.CLK( CLK )
);
///////////////////////////////////////////////////////
//
// PWM Channels
//
// Generate 7 PWM Channels, synchronized to the same frequency,
// with fixed duty cycles ramping from full-on to full-off.
//
//
// PWM Interval Timer
//
wire pwm_timer_tick;
CLS_PWM_Interval_Timer
#(
.CLK_RATE_HZ( CLK_RATE_HZ ), // Hz
.DUTY_RATE_HZ( PWM_DUTY_RATE ) // Hz
)
pwm_interval_timer
(
// Output Signals
.PWM_TICK( pwm_timer_tick ),
// System Signals
.CLK( CLK )
);
//
// Verify in simulaiton that the generated PWM Interval period matches
// the rate defined by the PWM_DUTY_RATE parameter.
//
specify
specparam tPERIOD = (1.0 / PWM_DUTY_RATE) * 1000000000.0; // ns
$period( posedge pwm_timer_tick, tPERIOD );
endspecify
//
// Generate Simulation warning messages for common mistakes
//
always @(pwm_timer_tick)
begin
if (pwm_timer_tick === 1'bX)
begin
$display ("WARNING: pwm_timer_tick value is unknown (RED)! Check the CLS_PWM_Interval_Timer module.");
$display (" Remember to initialize any counter registers using the computed LOADVAL values.");
end
end
//
// PWM Duty Cycle Timer (one per LED channel)
//
// Note: A generate block is used here to simplify instantiating 7
// instances of the same module.
//
localparam [7*7-1:0] PWM_DutyCycle_List = { 7'd100, 7'd50, 7'd25, 7'd13, 7'd6, 7'd3, 7'd1 };
wire [6:0] pwm_channel_sigs;
genvar i; // General purpose variable used by generate for loops
generate
begin
for (i=0; i < 7; i=i+1)
begin : PWM_Channels
//
// PWM Duty Cycle Timer
//
CLS_PWM_DutyCycle_Timer
#(
.CLK_RATE_HZ( CLK_RATE_HZ ), // MHz
.DUTY_RATE_HZ( PWM_DUTY_RATE ), // Hz
.DUTY_PERCENT( PWM_DutyCycle_List[7*i +:7] ) // Cycle On-time %
)
pwm_dutycycle_timer
(
// Input Signals
.PWM_INTERVAL_TICK( pwm_timer_tick ),
// Output Signals
.PWM_OUT( pwm_channel_sigs[i] ),
// System Signals
.CLK( CLK )
);
end
end
endgenerate
///////////////////////////////////////////////////////
//
// LED Position Shift Register
//
reg [LED_NUM-1:0] led_pos_reg;
initial
begin
led_pos_reg <= { {LED_NUM-1{1'b0}}, 1'b1 }; // Initialize 1 LED on
led_pos_reg[LED_NUM-1:1] = 15'h00;
end
// !! LAB 3: Add Shift Register Implementation Here !!
// always @(posedge fadeout_tick )
always @(posedge CLK)
begin
if (RIGHT_KEY_EVENT)
// Rotate Data Right
led_pos_reg <= { led_pos_reg[LED_NUM-2:0], led_pos_reg[LED_NUM-1] };
else if (LEFT_KEY_EVENT)
// Rotate Data Left
led_pos_reg <= { led_pos_reg[0], led_pos_reg[LED_NUM-1:1]};
else led_pos_reg <= led_pos_reg;
end
///////////////////////////////////////////////////////
//
// LED Output Faders
//
// !! LAB 3: Add CLS_LED_Output_Fader Generation Block Here !!
// General purpose variable used by generate for loops
generate
begin
for (i=0; i < 16; i=i+1)
begin : PWM_Channels_0
//
// Creating 16 cls_led_output_fader
//
CLS_LED_Output_Fader cls_led_output_fader
(
// Input Signals
.LED_FULL_ON(led_pos_reg[i]),
.PWM_CHANNEL_SIGS(pwm_channel_sigs),
.PWM_TIMER_TICK(pwm_timer_tick),
.FADE_TIMER_TICK(fadeout_tick),
// Output Signals
.LEDR(LED_OUT[i]),
.CLK(CLK)
);
end
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A211OI_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__A211OI_PP_BLACKBOX_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a211oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A211OI_PP_BLACKBOX_V
|
// "and_tree.v"
// @vcs-flags@ -P pli.tab
`timescale 1ps / 1ps
// `include "standard.v"
`include "standard.v-wrap"
//-----------------------------------------------------------------------------
module timeunit;
initial $timeformat(-9,1," ns",9);
endmodule
module TOP;
reg a, b, c, d;
wire z;
initial
begin
// @haco@ and_tree.haco-c
$prsim("and_tree.haco-c");
$prsim_cmd("echo $start of simulation");
$prsim_cmd("watchall");
$to_prsim("TOP.a", "a");
$to_prsim("TOP.b", "b");
$to_prsim("TOP.c", "c");
$to_prsim("TOP.d", "d");
$from_prsim("z", "TOP.z");
end
// these could be automatically generated
// by finding all globally unique instances of processes
// along with their hierarchical names
// e.g. from hacobjdump of .haco-c file
HAC_AND2 and_0();
defparam and_0.prsim_name="mytree.and_0";
HAC_AND2 and_1();
defparam and_1.prsim_name="mytree.and_1";
HAC_AND2 and_2();
defparam and_2.prsim_name="mytree.and_2";
initial
begin
#10 a <= 1'b0;
b <= 1'b0;
c <= 1'b0;
d <= 1'b0;
#100 a <= 1'b1;
b <= 1'b1;
c <= 1'b1;
d <= 1'b1;
#100 a <= 1'b0;
#100 d <= 1'b0;
#100 a <= 1'b1;
#100 d <= 1'b1;
#50 $finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR2_4_V
`define SKY130_FD_SC_HDLL__NOR2_4_V
/**
* nor2: 2-input NOR.
*
* Verilog wrapper for nor2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor2_4 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor2_4 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR2_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EINVN_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__EINVN_PP_BLACKBOX_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__einvn (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__EINVN_PP_BLACKBOX_V
|
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : scfifo
//
// Description : Single Clock FIFO
//
// Limitation :
//
// Results expected:
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module scfifo ( data,
clock,
wrreq,
rdreq,
aclr,
sclr,
q,
eccstatus,
usedw,
full,
empty,
almost_full,
almost_empty);
/* verilator lint_off WIDTH */
/* verilator lint_off MULTIDRIVEN */
/* verilator lint_off SYNCASYNCNET */ // For aclr
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1;
parameter lpm_widthu = 1;
parameter lpm_numwords = 2;
parameter lpm_showahead = "OFF";
parameter lpm_type = "scfifo";
parameter lpm_hint = "USE_EAB=ON";
parameter intended_device_family = "Stratix";
parameter underflow_checking = "ON";
parameter overflow_checking = "ON";
parameter allow_rwcycle_when_full = "OFF";
parameter use_eab = "ON";
parameter add_ram_output_register = "OFF";
parameter almost_full_value = 0;
parameter almost_empty_value = 0;
parameter maximum_depth = 0;
parameter enable_ecc = "FALSE";
// LOCAL_PARAMETERS_BEGIN
parameter showahead_area = ((lpm_showahead == "ON") && (add_ram_output_register == "OFF"));
parameter showahead_speed = ((lpm_showahead == "ON") && (add_ram_output_register == "ON"));
parameter legacy_speed = ((lpm_showahead == "OFF") && (add_ram_output_register == "ON"));
parameter ram_block_type = "AUTO";
// LOCAL_PARAMETERS_END
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input clock;
input wrreq;
input rdreq;
input aclr;
input sclr;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] q;
output [lpm_widthu-1:0] usedw;
output full;
output empty;
output almost_full;
output almost_empty;
output [1:0] eccstatus;
// INTERNAL REGISTERS DECLARATION
reg [lpm_width-1:0] mem_data [(1<<lpm_widthu):0];
reg [lpm_widthu-1:0] count_id;
reg [lpm_widthu-1:0] read_id;
reg [lpm_widthu-1:0] write_id;
wire valid_rreq;
reg valid_wreq;
reg write_flag;
reg full_flag;
reg empty_flag;
reg almost_full_flag;
reg almost_empty_flag;
reg [lpm_width-1:0] tmp_q;
reg stratix_family;
reg set_q_to_x;
reg set_q_to_x_by_empty;
reg [lpm_widthu-1:0] write_latency1;
reg [lpm_widthu-1:0] write_latency2;
reg [lpm_widthu-1:0] write_latency3;
integer wrt_count;
reg empty_latency1;
reg empty_latency2;
reg [(1<<lpm_widthu)-1:0] data_ready;
reg [(1<<lpm_widthu)-1:0] data_shown;
// INTERNAL TRI DECLARATION
tri0 aclr;
// LOCAL INTEGER DECLARATION
integer i;
// COMPONENT INSTANTIATIONS
ALTERA_DEVICE_FAMILIES dev ();
// INITIAL CONSTRUCT BLOCK
initial
begin
stratix_family = (dev.FEATURE_FAMILY_STRATIX(intended_device_family));
if (lpm_width <= 0)
begin
$display ("Error! LPM_WIDTH must be greater than 0.");
$display ("Time: %0t Instance: %m", $time);
end
if ((lpm_widthu !=1) && (lpm_numwords > (1 << lpm_widthu)))
begin
$display ("Error! LPM_NUMWORDS must equal to the ceiling of log2(LPM_WIDTHU).");
$display ("Time: %0t Instance: %m", $time);
end
if (dev.IS_VALID_FAMILY(intended_device_family) == 0)
begin
$display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family);
$display ("Time: %0t Instance: %m", $time);
end
if((add_ram_output_register != "ON") && (add_ram_output_register != "OFF"))
begin
$display ("Error! add_ram_output_register must be ON or OFF.");
$display ("Time: %0t Instance: %m", $time);
end
for (i = 0; i < (1<<lpm_widthu); i = i + 1)
begin
if (dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family))
mem_data[i] = {lpm_width{1'b0}};
else if (dev.FEATURE_FAMILY_STRATIX(intended_device_family))
begin
if ((add_ram_output_register == "ON") || (use_eab == "OFF"))
mem_data[i] = {lpm_width{1'b0}};
else
mem_data[i] = {lpm_width{1'bx}};
end
else
mem_data[i] = {lpm_width{1'b0}};
end
if (dev.FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM(intended_device_family))
tmp_q = {lpm_width{1'b0}};
else if (dev.FEATURE_FAMILY_STRATIX(intended_device_family))
begin
if ((add_ram_output_register == "ON") || (use_eab == "OFF"))
tmp_q = {lpm_width{1'b0}};
else
tmp_q = {lpm_width{1'bx}};
end
else
tmp_q = {lpm_width{1'b0}};
write_flag = 1'b0;
count_id = 0;
read_id = 0;
write_id = 0;
full_flag = 1'b0;
empty_flag = 1'b1;
empty_latency1 = 1'b1;
empty_latency2 = 1'b1;
set_q_to_x = 1'b0;
set_q_to_x_by_empty = 1'b0;
wrt_count = 0;
if (almost_full_value == 0)
almost_full_flag = 1'b1;
else
almost_full_flag = 1'b0;
if (almost_empty_value == 0)
almost_empty_flag = 1'b0;
else
almost_empty_flag = 1'b1;
end
assign valid_rreq = (underflow_checking == "OFF")? rdreq : (rdreq && ~empty_flag);
always @(wrreq or rdreq or full_flag)
begin
if (overflow_checking == "OFF")
valid_wreq = wrreq;
else if (allow_rwcycle_when_full == "ON")
valid_wreq = wrreq && (!full_flag || rdreq);
else
valid_wreq = wrreq && !full_flag;
end
always @(posedge clock or posedge aclr)
begin
if (aclr)
begin
if (add_ram_output_register == "ON")
tmp_q <= {lpm_width{1'b0}};
else if ((lpm_showahead == "ON") && (use_eab == "ON"))
begin
tmp_q <= {lpm_width{1'bX}};
end
else
begin
if (!stratix_family)
begin
tmp_q <= {lpm_width{1'b0}};
end
else
tmp_q <= {lpm_width{1'bX}};
end
read_id <= 0;
count_id <= 0;
full_flag <= 1'b0;
empty_flag <= 1'b1;
empty_latency1 <= 1'b1;
empty_latency2 <= 1'b1;
set_q_to_x <= 1'b0;
set_q_to_x_by_empty <= 1'b0;
wrt_count <= 0;
if (almost_full_value > 0)
almost_full_flag <= 1'b0;
if (almost_empty_value > 0)
almost_empty_flag <= 1'b1;
write_id <= 0;
if ((use_eab == "ON") && (stratix_family) && ((showahead_speed) || (showahead_area) || (legacy_speed)))
begin
write_latency1 <= 1'bx;
write_latency2 <= 1'bx;
data_shown <= {lpm_width{1'b0}};
if (add_ram_output_register == "ON")
tmp_q <= {lpm_width{1'b0}};
else
tmp_q <= {lpm_width{1'bX}};
end
end
else
begin
if (sclr)
begin
if (add_ram_output_register == "ON")
tmp_q <= {lpm_width{1'b0}};
else
tmp_q <= {lpm_width{1'bX}};
read_id <= 0;
count_id <= 0;
full_flag <= 1'b0;
empty_flag <= 1'b1;
empty_latency1 <= 1'b1;
empty_latency2 <= 1'b1;
set_q_to_x <= 1'b0;
set_q_to_x_by_empty <= 1'b0;
wrt_count <= 0;
if (almost_full_value > 0)
almost_full_flag <= 1'b0;
if (almost_empty_value > 0)
almost_empty_flag <= 1'b1;
if (!stratix_family)
begin
if (valid_wreq)
begin
write_flag <= 1'b1;
end
else
write_id <= 0;
end
else
begin
write_id <= 0;
end
if ((use_eab == "ON") && (stratix_family) && ((showahead_speed) || (showahead_area) || (legacy_speed)))
begin
write_latency1 <= 1'bx;
write_latency2 <= 1'bx;
data_shown <= {lpm_width{1'b0}};
if (add_ram_output_register == "ON")
tmp_q <= {lpm_width{1'b0}};
else
tmp_q <= {lpm_width{1'bX}};
end
end
else
begin
//READ operation
if (valid_rreq)
begin
if (!(set_q_to_x || set_q_to_x_by_empty))
begin
if (!valid_wreq)
wrt_count <= wrt_count - 1;
if (!valid_wreq)
begin
full_flag <= 1'b0;
if (count_id <= 0)
count_id <= {lpm_widthu{1'b1}};
else
count_id <= count_id - 1;
end
if ((use_eab == "ON") && stratix_family && (showahead_speed || showahead_area || legacy_speed))
begin
if ((wrt_count == 1 && valid_rreq && !valid_wreq) || ((wrt_count == 1 ) && valid_wreq && valid_rreq))
begin
empty_flag <= 1'b1;
end
else
begin
if (showahead_speed)
begin
if (data_shown[write_latency2] == 1'b0)
begin
empty_flag <= 1'b1;
end
end
else if (showahead_area || legacy_speed)
begin
if (data_shown[write_latency1] == 1'b0)
begin
empty_flag <= 1'b1;
end
end
end
end
else
begin
if (!valid_wreq)
begin
if ((count_id == 1) && !(full_flag))
empty_flag <= 1'b1;
end
end
if (empty_flag)
begin
if (underflow_checking == "ON")
begin
if ((use_eab == "OFF") || (!stratix_family))
tmp_q <= {lpm_width{1'b0}};
end
else
begin
set_q_to_x_by_empty <= 1'b1;
$display ("Warning : Underflow occurred! Fifo output is unknown until the next reset is asserted.");
$display ("Time: %0t Instance: %m", $time);
end
end
else if (read_id >= ((1<<lpm_widthu) - 1))
begin
if (lpm_showahead == "ON")
begin
if ((use_eab == "ON") && stratix_family && (showahead_speed || showahead_area))
begin
if (showahead_speed)
begin
if ((write_latency2 == 0) || (data_ready[0] == 1'b1))
begin
if (data_shown[0] == 1'b1)
begin
tmp_q <= mem_data[0];
data_shown[0] <= 1'b0;
data_ready[0] <= 1'b0;
end
end
end
else
begin
if ((count_id == 1) && !(full_flag))
begin
if (underflow_checking == "ON")
begin
if ((use_eab == "OFF") || (!stratix_family))
tmp_q <= {lpm_width{1'b0}};
end
else
tmp_q <= {lpm_width{1'bX}};
end
else if ((write_latency1 == 0) || (data_ready[0] == 1'b1))
begin
if (data_shown[0] == 1'b1)
begin
tmp_q <= mem_data[0];
data_shown[0] <= 1'b0;
data_ready[0] <= 1'b0;
end
end
end
end
else
begin
if ((count_id == 1) && !(full_flag))
begin
if (valid_wreq)
tmp_q <= data;
else
if (underflow_checking == "ON")
begin
if ((use_eab == "OFF") || (!stratix_family))
tmp_q <= {lpm_width{1'b0}};
end
else
tmp_q <= {lpm_width{1'bX}};
end
else
tmp_q <= mem_data[0];
end
end
else
begin
if ((use_eab == "ON") && stratix_family && legacy_speed)
begin
if ((write_latency1 == read_id) || (data_ready[read_id] == 1'b1))
begin
if (data_shown[read_id] == 1'b1)
begin
tmp_q <= mem_data[read_id];
data_shown[read_id] <= 1'b0;
data_ready[read_id] <= 1'b0;
end
end
else
begin
tmp_q <= {lpm_width{1'bX}};
end
end
else
tmp_q <= mem_data[read_id];
end
read_id <= 0;
end // end if (read_id >= ((1<<lpm_widthu) - 1))
else
begin
if (lpm_showahead == "ON")
begin
if ((use_eab == "ON") && stratix_family && (showahead_speed || showahead_area))
begin
if (showahead_speed)
begin
if ((write_latency2 == read_id+1) || (data_ready[read_id+1] == 1'b1))
begin
if (data_shown[read_id+1] == 1'b1)
begin
tmp_q <= mem_data[read_id + 1];
data_shown[read_id+1] <= 1'b0;
data_ready[read_id+1] <= 1'b0;
end
end
end
else
begin
if ((count_id == 1) && !(full_flag))
begin
if (underflow_checking == "ON")
begin
if ((use_eab == "OFF") || (!stratix_family))
tmp_q <= {lpm_width{1'b0}};
end
else
tmp_q <= {lpm_width{1'bX}};
end
else if ((write_latency1 == read_id+1) || (data_ready[read_id+1] == 1'b1))
begin
if (data_shown[read_id+1] == 1'b1)
begin
tmp_q <= mem_data[read_id + 1];
data_shown[read_id+1] <= 1'b0;
data_ready[read_id+1] <= 1'b0;
end
end
end
end
else
begin
if ((count_id == 1) && !(full_flag))
begin
if ((use_eab == "OFF") && stratix_family)
begin
if (valid_wreq)
begin
tmp_q <= data;
end
else
begin
if (underflow_checking == "ON")
begin
if ((use_eab == "OFF") || (!stratix_family))
tmp_q <= {lpm_width{1'b0}};
end
else
tmp_q <= {lpm_width{1'bX}};
end
end
else
begin
tmp_q <= {lpm_width{1'bX}};
end
end
else
tmp_q <= mem_data[read_id + 1];
end
end
else
begin
if ((use_eab == "ON") && stratix_family && legacy_speed)
begin
if ((write_latency1 == read_id) || (data_ready[read_id] == 1'b1))
begin
if (data_shown[read_id] == 1'b1)
begin
tmp_q <= mem_data[read_id];
data_shown[read_id] <= 1'b0;
data_ready[read_id] <= 1'b0;
end
end
else
begin
tmp_q <= {lpm_width{1'bX}};
end
end
else
tmp_q <= mem_data[read_id];
end
read_id <= read_id + 1;
end
end
end
// WRITE operation
if (valid_wreq)
begin
if (!(set_q_to_x || set_q_to_x_by_empty))
begin
if (full_flag && (overflow_checking == "OFF"))
begin
set_q_to_x <= 1'b1;
$display ("Warning : Overflow occurred! Fifo output is unknown until the next reset is asserted.");
$display ("Time: %0t Instance: %m", $time);
end
else
begin
mem_data[write_id] <= data;
write_flag <= 1'b1;
if (!((use_eab == "ON") && stratix_family && (showahead_speed || showahead_area || legacy_speed)))
begin
empty_flag <= 1'b0;
end
else
begin
empty_latency1 <= 1'b0;
end
if (!valid_rreq)
wrt_count <= wrt_count + 1;
if (!valid_rreq)
begin
if (count_id >= (1 << lpm_widthu) - 1)
count_id <= 0;
else
count_id <= count_id + 1;
end
else
begin
if (allow_rwcycle_when_full == "OFF")
full_flag <= 1'b0;
end
if (!(stratix_family) || (stratix_family && !(showahead_speed || showahead_area || legacy_speed)))
begin
if (!valid_rreq)
if ((count_id == lpm_numwords - 1) && (empty_flag == 1'b0))
full_flag <= 1'b1;
end
else
begin
if (!valid_rreq)
if (count_id == lpm_numwords - 1)
full_flag <= 1'b1;
end
if (lpm_showahead == "ON")
begin
if ((use_eab == "ON") && stratix_family && (showahead_speed || showahead_area))
begin
write_latency1 <= write_id;
data_shown[write_id] <= 1'b1;
data_ready[write_id] <= 1'bx;
end
else
begin
if ((use_eab == "OFF") && stratix_family && (count_id == 0) && (!full_flag))
begin
tmp_q <= data;
end
else
begin
if ((!empty_flag) && (!valid_rreq))
begin
tmp_q <= mem_data[read_id];
end
end
end
end
else
begin
if ((use_eab == "ON") && stratix_family && legacy_speed)
begin
write_latency1 <= write_id;
data_shown[write_id] <= 1'b1;
data_ready[write_id] <= 1'bx;
end
end
end
end
end
if (almost_full_value == 0)
almost_full_flag <= 1'b1;
else if (lpm_numwords > almost_full_value)
begin
if (almost_full_flag)
begin
if ((count_id == almost_full_value) && !wrreq && rdreq)
almost_full_flag <= 1'b0;
end
else
begin
if ((almost_full_value == 1) && (count_id == 0) && wrreq)
almost_full_flag <= 1'b1;
else if ((almost_full_value > 1) && (count_id == almost_full_value - 1)
&& wrreq && !rdreq)
almost_full_flag <= 1'b1;
end
end
if (almost_empty_value == 0)
almost_empty_flag <= 1'b0;
else if (lpm_numwords > almost_empty_value)
begin
if (almost_empty_flag)
begin
if ((almost_empty_value == 1) && (count_id == 0) && wrreq)
almost_empty_flag <= 1'b0;
else if ((almost_empty_value > 1) && (count_id == almost_empty_value - 1)
&& wrreq && !rdreq)
almost_empty_flag <= 1'b0;
end
else
begin
if ((count_id == almost_empty_value) && !wrreq && rdreq)
almost_empty_flag <= 1'b1;
end
end
end
if ((use_eab == "ON") && stratix_family)
begin
if (showahead_speed)
begin
write_latency2 <= write_latency1;
write_latency3 <= write_latency2;
if (write_latency3 !== write_latency2)
data_ready[write_latency2] <= 1'b1;
empty_latency2 <= empty_latency1;
if (data_shown[write_latency2]==1'b1)
begin
if ((read_id == write_latency2) || aclr || sclr)
begin
if (!(aclr === 1'b1) && !(sclr === 1'b1))
begin
if (write_latency2 !== 1'bx)
begin
tmp_q <= mem_data[write_latency2];
data_shown[write_latency2] <= 1'b0;
data_ready[write_latency2] <= 1'b0;
if (!valid_rreq)
empty_flag <= empty_latency2;
end
end
end
end
end
else if (showahead_area)
begin
write_latency2 <= write_latency1;
if (write_latency2 !== write_latency1)
data_ready[write_latency1] <= 1'b1;
if (data_shown[write_latency1]==1'b1)
begin
if ((read_id == write_latency1) || aclr || sclr)
begin
if (!(aclr === 1'b1) && !(sclr === 1'b1))
begin
if (write_latency1 !== 1'bx)
begin
tmp_q <= mem_data[write_latency1];
data_shown[write_latency1] <= 1'b0;
data_ready[write_latency1] <= 1'b0;
if (!valid_rreq)
begin
empty_flag <= empty_latency1;
end
end
end
end
end
end
else
begin
if (legacy_speed)
begin
write_latency2 <= write_latency1;
if (write_latency2 !== write_latency1)
data_ready[write_latency1] <= 1'b1;
empty_flag <= empty_latency1;
if ((wrt_count == 1 && !valid_wreq && valid_rreq) || aclr || sclr)
begin
empty_flag <= 1'b1;
empty_latency1 <= 1'b1;
end
else
begin
if ((wrt_count == 1) && valid_wreq && valid_rreq)
begin
empty_flag <= 1'b1;
end
end
end
end
end
end
end
always @(negedge clock)
begin
if (write_flag)
begin
write_flag <= 1'b0;
if (sclr || aclr || (write_id >= ((1 << lpm_widthu) - 1)))
write_id <= 0;
else
write_id <= write_id + 1;
end
if (!(stratix_family))
begin
if (!empty)
begin
if ((lpm_showahead == "ON") && ($time > 0))
tmp_q <= mem_data[read_id];
end
end
end
always @(full_flag)
begin
if (lpm_numwords == almost_full_value)
if (full_flag)
almost_full_flag = 1'b1;
else
almost_full_flag = 1'b0;
if (lpm_numwords == almost_empty_value)
if (full_flag)
almost_empty_flag = 1'b0;
else
almost_empty_flag = 1'b1;
end
// CONTINOUS ASSIGNMENT
assign q = (set_q_to_x || set_q_to_x_by_empty)? {lpm_width{1'bX}} : tmp_q;
assign full = (set_q_to_x || set_q_to_x_by_empty)? 1'bX : full_flag;
assign empty = (set_q_to_x || set_q_to_x_by_empty)? 1'bX : empty_flag;
assign usedw = (set_q_to_x || set_q_to_x_by_empty)? {lpm_widthu{1'bX}} : count_id;
assign almost_full = (set_q_to_x || set_q_to_x_by_empty)? 1'bX : almost_full_flag;
assign almost_empty = (set_q_to_x || set_q_to_x_by_empty)? 1'bX : almost_empty_flag;
assign eccstatus = {2'b0};
/* verilator lint_on WIDTH */
/* verilator lint_on MULTIDRIVEN */
/* verilator lint_on SYNCASYNCNET */ // For aclr
endmodule // scfifo
// END OF MODULE
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_keycode (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 7: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 7: 0] data_out;
wire [ 7: 0] out_port;
wire [ 7: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[7 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
/// date:2016/3/4
/// engineer: ZhaiShaoMin
/// module function : just combine memory_fsm and memory_state_data_ram
module memory (//input
clk,
rst,
//fsm state of rep paralle-serial port corresponding to mem
m_rep_fsm_state,
//fsm state of req paralle-serial port corresponding to mem
m_req_fsm_state,
// fsm state of req paralle-serial port corresponding to data cache
d_fsm_state,
// input from local d cache
v_d_req,
v_d_rep,
local_d_head_in,
local_d_addr_in,
local_d_data_in,
// input from local i cache
v_i_rep,
// local_i_head, // no need for local i cache miss
local_i_addr_in,
// input form INfifos
v_INfifos,
infifos_head_in,
infifos_addr_in,
infifos_data_in,
// output to local d cache
v_req_d,
v_rep_d,
head_out_local_d,
addr_out_local_d,
data_out_local_d,
// output to local i cahce
v_rep_i,
data_out_local_i,
// output to OUT req fifo
en_inv_ids,
inv_ids_in,
flit_max_req,
en_flit_max_req,
v_req_out,
head_out_req_out,
addr_out_req_out,
// data_out_req_out,
// output to OUT rep fifo
flit_max_rep,
en_flit_max_rep,
v_rep_out,
head_out_rep_out,
addr_out_rep_out,
data_out_rep_out,
mem_access_done
);
// input
input clk;
input rst;
//fsm state of rep paralle-serial port corresponding to mem
input [1:0] m_rep_fsm_state;
//fsm state of req paralle-serial port corresponding to mem
input [1:0] m_req_fsm_state;
// fsm state of req paralle-serial port corresponding to data cache
input [1:0] d_fsm_state;
// input from local d cache
input v_d_req;
input v_d_rep;
input [15:0] local_d_head_in;
input [31:0] local_d_addr_in;
input [127:0] local_d_data_in;
// input from local i cache
input v_i_rep;
// local_i_head, // no need for local i cache miss
input [31:0] local_i_addr_in;
// input form INfifos
input v_INfifos;
input [15:0] infifos_head_in;
input [31:0] infifos_addr_in;
input [127:0] infifos_data_in;
// output
// output to local d cache
output v_req_d;
output v_rep_d;
output [15:0] head_out_local_d;
output [31:0] addr_out_local_d;
output [127:0] data_out_local_d;
// output to local i cahce
output v_rep_i;
output [127:0] data_out_local_i;
// output to OUT req fifo
output en_inv_ids;
output [3:0] inv_ids_in;
output [1:0] flit_max_req;
output en_flit_max_req;
output v_req_out;
output [15:0] head_out_req_out;
output [31:0] addr_out_req_out;
//output [127:0] data_out_req_out;
// output to OUT rep fifo
output [3:0] flit_max_rep;
output en_flit_max_rep;
output v_rep_out;
output [15:0] head_out_rep_out;
output [31:0] addr_out_rep_out;
output [127:0] data_out_rep_out;
output mem_access_done;
wire state_we_net;
wire state_re_net;
wire data_we_net;
wire data_re_net;
wire [31:0] addr_net;
wire [127:0] data_in_net;
wire [127:0] data_out_net;
wire [5:0] state_in_net;
wire [5:0] state_out_net;
memory_state_data_ram mem_ram(// input
.clk(clk),
.state_we_in(state_we_net),
.state_re_in(state_re_net),
.addr_in(addr_net),
.state_in(state_in_net),
.data_we_in(data_we_net),
.data_re_in(data_re_net),
.data_in(data_in_net),
// output
.state_out(state_out_net),
.data_out(data_out_net));
memory_fsm mem_fsm(// global signals
.clk(clk),
.rst(rst),
//fsm state of rep paralle-serial port corresponding to mem
.m_rep_fsm_state(m_rep_fsm_state),
//fsm state of req paralle-serial port corresponding to mem
.m_req_fsm_state(m_req_fsm_state),
// fsm state of req paralle-serial port corresponding to data cache
.d_fsm_state(d_fsm_state),
// input from mem_ram
.mem_state_out(state_out_net),
.mem_data_in(data_out_net),
// input from local d cache
.v_d_req(v_d_req),
.v_d_rep(v_d_rep),
.local_d_head_in(local_d_head_in),
.local_d_addr_in(local_d_addr_in),
.local_d_data_in(local_d_data_in),
// input from local i cache
.v_i_rep(v_i_rep),
// local_i_head, // no need for local i cache miss
.local_i_addr_in(),
// input form INfifos
.v_INfifos(v_INfifos),
.infifos_head_in(infifos_head_in),
.infifos_addr_in(infifos_addr_in),
.infifos_data_in(infifos_data_in),
//output to mem_ram
.data_out_mem_ram(data_in_net),
.state_out_mem_ram(state_in_net),
.addr_out_mem_ram(addr_net),
.state_we_out(state_we_net),
.state_re_out(state_re_net),
.data_we_out(data_we_net),
.data_re_out(data_re_net),
// output to local d cache
.v_req_d(v_req_d),
.v_rep_d(v_rep_d),
.head_out_local_d(head_out_local_d),
.addr_out_local_d(addr_out_local_d),
.data_out_local_d(data_out_local_d),
// output to local i cahce
.v_rep_Icache(v_rep_i),
.data_out_local_i(data_out_local_i),
// output to OUT req fifo
.en_inv_ids(en_inv_ids),
.inv_ids_in(inv_ids_in),
.flit_max_req(flit_max_req),
.en_flit_max_req(en_flit_max_req),
.v_req_out(v_req_out),
.head_out_req_out(head_out_req_out),
.addr_out_req_out(addr_out_req_out),
//.data_out_req_out(data_out_req_out),
// output to OUT rep fifo
.flit_max_rep(flit_max_rep),
.en_flit_max_rep(en_flit_max_rep),
.v_rep_out(v_rep_out),
.head_out_rep_out(head_out_rep_out),
.addr_out_rep_out(addr_out_rep_out),
.data_out_rep_out(data_out_rep_out),
.mem_access_done(mem_access_done)
);
endmodule |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Thu Sep 14 10:54:36 2017
// Host : PC4719 running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_0_stub.v
// Design : ila_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
probe6, probe7)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[31:0],probe3[31:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[0:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [31:0]probe2;
input [31:0]probe3;
input [0:0]probe4;
input [0:0]probe5;
input [0:0]probe6;
input [0:0]probe7;
endmodule
|
//-----------------------------------------------------------------------------
// processing_system7
// processor sub system wrapper
//-----------------------------------------------------------------------------
//
// ************************************************************************
// ** DISCLAIMER OF LIABILITY **
// ** **
// ** This file contains proprietary and confidential information of **
// ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
// ** from Xilinx, and may be used, copied and/or diSCLosed only **
// ** pursuant to the terms of a valid license agreement with Xilinx. **
// ** **
// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
// ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
// ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
// ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
// ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
// ** does not warrant that functions included in the Materials will **
// ** meet the requirements of Licensee, or that the operation of the **
// ** Materials will be uninterrupted or error-free, or that defects **
// ** in the Materials will be corrected. Furthermore, Xilinx does **
// ** not warrant or make any representations regarding use, or the **
// ** results of the use, of the Materials in terms of correctness, **
// ** accuracy, reliability or otherwise. **
// ** **
// ** Xilinx products are not designed or intended to be fail-safe, **
// ** or for use in any application requiring fail-safe performance, **
// ** such as life-support or safety devices or systems, Class III **
// ** medical devices, nuclear facilities, applications related to **
// ** the deployment of airbags, or any other applications that could **
// ** lead to death, personal injury or severe property or **
// ** environmental damage (individually and collectively, "critical **
// ** applications"). Customer assumes the sole risk and liability **
// ** of any use of Xilinx products in critical applications, **
// ** subject only to applicable laws and regulations governing **
// ** limitations on product liability. **
// ** **
// ** Copyright 2010 Xilinx, Inc. **
// ** All rights reserved. **
// ** **
// ** This disclaimer and copyright notice must be retained as part **
// ** of this file at all times. **
// ************************************************************************
//
//-----------------------------------------------------------------------------
// Filename: processing_system7_v5_5_processing_system7.v
// Version: v1.00.a
// Description: This is the wrapper file for PSS.
//-----------------------------------------------------------------------------
// Structure: This section shows the hierarchical structure of
// pss_wrapper.
//
// --processing_system7_v5_5_processing_system7.v
// --PS7.v - Unisim component
//-----------------------------------------------------------------------------
// Author: SD
//
// History:
//
// SD 09/20/11 -- First version
// ~~~~~~
// Created the first version v2.00.a
// ^^^^^^
//------------------------------------------------------------------------------
// ^^^^^^
// SR 11/25/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// 1. Changed all clock, reset and clktrig ports to be individual
// signals instead of vectors. This is required for modeling of tools.
// 2. Interrupts are now defined as individual signals as well.
// 3. Added Clk buffer logic for FCLK_CLK
// 4. Includes the ACP related changes done
//
// TODO:
// 1. C_NUM_F2P_INTR_INPUTS needs to have control on the
// number of interrupt ports connected for IRQ_F2P.
//
//------------------------------------------------------------------------------
// ^^^^^^
// KP 12/07/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_NUM_F2P_INTR_INPUTS taken into account for IRQ_F2P
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/09/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_FCLK_CLK0_BUF to C_FCLK_CLK3_BUF parameters were updated
// to STRING and fix for CR 640523
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/13/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// Updated IRQ_F2P logic to address CR 641523.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/01/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Updated SDIO logic to address CR 636210.
// |
// Added C_PS7_SI_REV parameter to track SI Rev
// Removed compress/decompress logic to address CR 642527.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/27/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// TTC(0,1)_WAVE_OUT and TTC(0,1)_CLK_IN vector signals are made as individual
// ports as fix for CR 646379
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/05/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Added/updated compress/decompress logic to address 648393
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/14/12 -- v4.00.a version
// ~~~~~~~
// Unused parameters deleted CR 651120
// Addressed CR 651751
//------------------------------------------------------------------------------
// ^^^^^^
// NR 04/17/12 -- v4.01.a version
// ~~~~~~~
// Added FTM trace buffer functionality
// Added support for ACP AxUSER ports local update
//------------------------------------------------------------------------------
// ^^^^^^
// VR 05/18/12 -- v4.01.a version
// ~~~~~~~
// Fixed CR#659157
//------------------------------------------------------------------------------
// ^^^^^^
// VR 07/25/12 -- v4.01.a version
// ~~~~~~~
// Changed S_AXI_HP{1,2}_WACOUNT port's width to 6 from 8 to match unisim model
// Changed fclk_clktrig_gnd width to 4 from 16 to match unisim model
//------------------------------------------------------------------------------
// ^^^^^^
// VR 11/06/12 -- v5.00 version
// ~~~~~~~
// CR #682573
// Added BIBUF to fixed IO ports and IBUF to fixed input ports
//------------------------------------------------------------------------------
(*POWER= "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666666} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333333} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={22} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={CAN} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={23.809523} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={S_AXI_ACP} dataWidth={32} clockFreq={100} usageRate={0.5} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* CORE_GENERATION_INFO = "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=533.333333, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=15, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=7, PCW_UIPARAM_DDR_CWL=6, PCW_UIPARAM_DDR_T_RCD=7, PCW_UIPARAM_DDR_T_RP=7, PCW_UIPARAM_DDR_T_RC=49.5, PCW_UIPARAM_DDR_T_RAS_MIN=36.0, PCW_UIPARAM_DDR_T_FAW=30.0, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=0.217, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=0.133, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=0.089, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=0.248, PCW_UIPARAM_DDR_BOARD_DELAY0=0.537, PCW_UIPARAM_DDR_BOARD_DELAY1=0.442, PCW_UIPARAM_DDR_BOARD_DELAY2=0.464, PCW_UIPARAM_DDR_BOARD_DELAY3=0.521, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=68.4725, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=71.086, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=66.794, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=108.7385, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=64.1705, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=63.686, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=68.46, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=105.4895, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=33.333333, PCW_APU_PERIPHERAL_FREQMHZ=666.666666, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=50, PCW_UART_PERIPHERAL_FREQMHZ=50, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=23.8095, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=100, PCW_FPGA1_PERIPHERAL_FREQMHZ=50, PCW_FPGA2_PERIPHERAL_FREQMHZ=50, PCW_FPGA3_PERIPHERAL_FREQMHZ=50, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=40, PCW_IOPLL_CTRL_FBDIV=30, PCW_DDRPLL_CTRL_FBDIV=32, PCW_CPU_CPU_PLL_FREQMHZ=1333.333, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1066.667, PCW_USE_M_AXI_GP0=1, PCW_USE_M_AXI_GP1=0, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=1, PCW_USE_S_AXI_HP0=0, PCW_USE_S_AXI_HP1=0, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=100, PCW_M_AXI_GP1_FREQMHZ=10, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=100, PCW_S_AXI_HP0_FREQMHZ=10, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_FTM_CTI_IN0=DISABLED, PCW_FTM_CTI_IN1=DISABLED, PCW_FTM_CTI_IN2=DISABLED, PCW_FTM_CTI_IN3=DISABLED, PCW_FTM_CTI_OUT0=DISABLED, PCW_FTM_CTI_OUT1=DISABLED, PCW_FTM_CTI_OUT2=DISABLED, PCW_FTM_CTI_OUT3=DISABLED, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=64, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 1.8V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 1.8V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3, PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=32 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=MT41J256M8 HX-15E, PCW_UIPARAM_DDR_DRAM_WIDTH=8 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=2048 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=1, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=1, PCW_QSPI_GRP_FBCLK_IO=MIO 8, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_ENET0_PERIPHERAL_ENABLE=0, PCW_ENET0_GRP_MDIO_ENABLE=0, PCW_ENET0_RESET_ENABLE=1, PCW_ENET0_RESET_IO=MIO 11, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=0, PCW_SD0_GRP_CD_ENABLE=0, PCW_SD0_GRP_WP_ENABLE=0, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=0, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=0, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 48 .. 49, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=0, PCW_SPI0_GRP_SS0_ENABLE=0, PCW_SPI0_GRP_SS1_ENABLE=0, PCW_SPI0_GRP_SS2_ENABLE=0, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=1, PCW_CAN0_CAN0_IO=MIO 46 .. 47, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=0, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=1, PCW_USB0_USB0_IO=MIO 28 .. 39, PCW_USB0_RESET_ENABLE=1, PCW_USB0_RESET_IO=MIO 7, PCW_USB1_PERIPHERAL_ENABLE=0, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=0, PCW_I2C0_GRP_INT_ENABLE=0, PCW_I2C0_RESET_ENABLE=1, PCW_I2C0_RESET_IO=MIO 13, PCW_I2C1_PERIPHERAL_ENABLE=0, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=0, PCW_GPIO_MIO_GPIO_ENABLE=1, PCW_GPIO_MIO_GPIO_IO=MIO, PCW_GPIO_EMIO_GPIO_ENABLE=0, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=0, PCW_FPGA_FCLK2_ENABLE=0, PCW_FPGA_FCLK3_ENABLE=0, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=2, PCW_NOR_SRAM_CS0_T_RC=2, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=2, PCW_NOR_SRAM_CS1_T_RC=2, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=2, PCW_NOR_CS0_T_RC=2, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=2, PCW_NOR_CS1_T_RC=2, PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=2, PCW_NAND_CYCLES_T_RC=2 }" *)
module processing_system7_v5_5_processing_system7
#(
parameter integer C_USE_DEFAULT_ACP_USER_VAL = 1,
parameter integer C_S_AXI_ACP_ARUSER_VAL = 31,
parameter integer C_S_AXI_ACP_AWUSER_VAL = 31,
parameter integer C_M_AXI_GP0_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP0_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP1_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP0_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_ID_WIDTH = 12,
parameter integer C_S_AXI_GP0_ID_WIDTH = 6,
parameter integer C_S_AXI_GP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP0_ID_WIDTH = 6,
parameter integer C_S_AXI_HP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP2_ID_WIDTH = 6,
parameter integer C_S_AXI_HP3_ID_WIDTH = 6,
parameter integer C_S_AXI_ACP_ID_WIDTH = 3,
parameter integer C_S_AXI_HP0_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP1_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP2_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP3_DATA_WIDTH = 64,
parameter integer C_INCLUDE_ACP_TRANS_CHECK = 0,
parameter integer C_NUM_F2P_INTR_INPUTS = 1,
parameter C_FCLK_CLK0_BUF = "TRUE",
parameter C_FCLK_CLK1_BUF = "TRUE",
parameter C_FCLK_CLK2_BUF = "TRUE",
parameter C_FCLK_CLK3_BUF = "TRUE",
parameter integer C_EMIO_GPIO_WIDTH = 64,
parameter integer C_INCLUDE_TRACE_BUFFER = 0,
parameter integer C_TRACE_BUFFER_FIFO_SIZE = 128,
parameter integer C_TRACE_BUFFER_CLOCK_DELAY = 12,
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
parameter integer C_TRACE_PIPELINE_WIDTH = 8,
parameter C_PS7_SI_REV = "PRODUCTION",
parameter integer C_EN_EMIO_ENET0 = 0,
parameter integer C_EN_EMIO_ENET1 = 0,
parameter integer C_EN_EMIO_TRACE = 0,
parameter integer C_DQ_WIDTH = 32,
parameter integer C_DQS_WIDTH = 4,
parameter integer C_DM_WIDTH = 4,
parameter integer C_MIO_PRIMITIVE = 54,
parameter C_PACKAGE_NAME = "clg484",
parameter C_IRQ_F2P_MODE = "DIRECT",
parameter C_TRACE_INTERNAL_WIDTH = 32,
parameter integer C_EN_EMIO_PJTAG = 0
)
(
//FMIO =========================================
//FMIO CAN0
output CAN0_PHY_TX,
input CAN0_PHY_RX,
//FMIO CAN1
output CAN1_PHY_TX,
input CAN1_PHY_RX,
//FMIO ENET0
output reg ENET0_GMII_TX_EN,
output reg ENET0_GMII_TX_ER,
output ENET0_MDIO_MDC,
output ENET0_MDIO_O,
output ENET0_MDIO_T,
output ENET0_PTP_DELAY_REQ_RX,
output ENET0_PTP_DELAY_REQ_TX,
output ENET0_PTP_PDELAY_REQ_RX,
output ENET0_PTP_PDELAY_REQ_TX,
output ENET0_PTP_PDELAY_RESP_RX,
output ENET0_PTP_PDELAY_RESP_TX,
output ENET0_PTP_SYNC_FRAME_RX,
output ENET0_PTP_SYNC_FRAME_TX,
output ENET0_SOF_RX,
output ENET0_SOF_TX,
output reg [7:0] ENET0_GMII_TXD,
input ENET0_GMII_COL,
input ENET0_GMII_CRS,
input ENET0_GMII_RX_CLK,
input ENET0_GMII_RX_DV,
input ENET0_GMII_RX_ER,
input ENET0_GMII_TX_CLK,
input ENET0_MDIO_I,
input ENET0_EXT_INTIN,
input [7:0] ENET0_GMII_RXD,
//FMIO ENET1
output reg ENET1_GMII_TX_EN,
output reg ENET1_GMII_TX_ER,
output ENET1_MDIO_MDC,
output ENET1_MDIO_O,
output ENET1_MDIO_T,
output ENET1_PTP_DELAY_REQ_RX,
output ENET1_PTP_DELAY_REQ_TX,
output ENET1_PTP_PDELAY_REQ_RX,
output ENET1_PTP_PDELAY_REQ_TX,
output ENET1_PTP_PDELAY_RESP_RX,
output ENET1_PTP_PDELAY_RESP_TX,
output ENET1_PTP_SYNC_FRAME_RX,
output ENET1_PTP_SYNC_FRAME_TX,
output ENET1_SOF_RX,
output ENET1_SOF_TX,
output reg [7:0] ENET1_GMII_TXD,
input ENET1_GMII_COL,
input ENET1_GMII_CRS,
input ENET1_GMII_RX_CLK,
input ENET1_GMII_RX_DV,
input ENET1_GMII_RX_ER,
input ENET1_GMII_TX_CLK,
input ENET1_MDIO_I,
input ENET1_EXT_INTIN,
input [7:0] ENET1_GMII_RXD,
//FMIO GPIO
input [(C_EMIO_GPIO_WIDTH-1):0] GPIO_I,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_O,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T,
//FMIO I2C0
input I2C0_SDA_I,
output I2C0_SDA_O,
output I2C0_SDA_T,
input I2C0_SCL_I,
output I2C0_SCL_O,
output I2C0_SCL_T,
//FMIO I2C1
input I2C1_SDA_I,
output I2C1_SDA_O,
output I2C1_SDA_T,
input I2C1_SCL_I,
output I2C1_SCL_O,
output I2C1_SCL_T,
//FMIO PJTAG
input PJTAG_TCK,
input PJTAG_TMS,
input PJTAG_TDI,
output PJTAG_TDO,
//FMIO SDIO0
output SDIO0_CLK,
input SDIO0_CLK_FB,
output SDIO0_CMD_O,
input SDIO0_CMD_I,
output SDIO0_CMD_T,
input [3:0] SDIO0_DATA_I,
output [3:0] SDIO0_DATA_O,
output [3:0] SDIO0_DATA_T,
output SDIO0_LED,
input SDIO0_CDN,
input SDIO0_WP,
output SDIO0_BUSPOW,
output [2:0] SDIO0_BUSVOLT,
//FMIO SDIO1
output SDIO1_CLK,
input SDIO1_CLK_FB,
output SDIO1_CMD_O,
input SDIO1_CMD_I,
output SDIO1_CMD_T,
input [3:0] SDIO1_DATA_I,
output [3:0] SDIO1_DATA_O,
output [3:0] SDIO1_DATA_T,
output SDIO1_LED,
input SDIO1_CDN,
input SDIO1_WP,
output SDIO1_BUSPOW,
output [2:0] SDIO1_BUSVOLT,
//FMIO SPI0
input SPI0_SCLK_I,
output SPI0_SCLK_O,
output SPI0_SCLK_T,
input SPI0_MOSI_I,
output SPI0_MOSI_O,
output SPI0_MOSI_T,
input SPI0_MISO_I,
output SPI0_MISO_O,
output SPI0_MISO_T,
input SPI0_SS_I,
output SPI0_SS_O,
output SPI0_SS1_O,
output SPI0_SS2_O,
output SPI0_SS_T,
//FMIO SPI1
input SPI1_SCLK_I,
output SPI1_SCLK_O,
output SPI1_SCLK_T,
input SPI1_MOSI_I,
output SPI1_MOSI_O,
output SPI1_MOSI_T,
input SPI1_MISO_I,
output SPI1_MISO_O,
output SPI1_MISO_T,
input SPI1_SS_I,
output SPI1_SS_O,
output SPI1_SS1_O,
output SPI1_SS2_O,
output SPI1_SS_T,
//FMIO UART0
output UART0_DTRN,
output UART0_RTSN,
output UART0_TX,
input UART0_CTSN,
input UART0_DCDN,
input UART0_DSRN,
input UART0_RIN,
input UART0_RX,
//FMIO UART1
output UART1_DTRN,
output UART1_RTSN,
output UART1_TX,
input UART1_CTSN,
input UART1_DCDN,
input UART1_DSRN,
input UART1_RIN,
input UART1_RX,
//FMIO TTC0
output TTC0_WAVE0_OUT,
output TTC0_WAVE1_OUT,
output TTC0_WAVE2_OUT,
input TTC0_CLK0_IN,
input TTC0_CLK1_IN,
input TTC0_CLK2_IN,
//FMIO TTC1
output TTC1_WAVE0_OUT,
output TTC1_WAVE1_OUT,
output TTC1_WAVE2_OUT,
input TTC1_CLK0_IN,
input TTC1_CLK1_IN,
input TTC1_CLK2_IN,
//WDT
input WDT_CLK_IN,
output WDT_RST_OUT,
//FTPORT
input TRACE_CLK,
output TRACE_CTL,
output [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA,
output reg TRACE_CLK_OUT,
// USB
output [1:0] USB0_PORT_INDCTL,
output USB0_VBUS_PWRSELECT,
input USB0_VBUS_PWRFAULT,
output [1:0] USB1_PORT_INDCTL,
output USB1_VBUS_PWRSELECT,
input USB1_VBUS_PWRFAULT,
input SRAM_INTIN,
//AIO ===================================================
//M_AXI_GP0
// -- Output
output M_AXI_GP0_ARESETN,
output M_AXI_GP0_ARVALID,
output M_AXI_GP0_AWVALID,
output M_AXI_GP0_BREADY,
output M_AXI_GP0_RREADY,
output M_AXI_GP0_WLAST,
output M_AXI_GP0_WVALID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_ARID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_AWID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_WID,
output [1:0] M_AXI_GP0_ARBURST,
output [1:0] M_AXI_GP0_ARLOCK,
output [2:0] M_AXI_GP0_ARSIZE,
output [1:0] M_AXI_GP0_AWBURST,
output [1:0] M_AXI_GP0_AWLOCK,
output [2:0] M_AXI_GP0_AWSIZE,
output [2:0] M_AXI_GP0_ARPROT,
output [2:0] M_AXI_GP0_AWPROT,
output [31:0] M_AXI_GP0_ARADDR,
output [31:0] M_AXI_GP0_AWADDR,
output [31:0] M_AXI_GP0_WDATA,
output [3:0] M_AXI_GP0_ARCACHE,
output [3:0] M_AXI_GP0_ARLEN,
output [3:0] M_AXI_GP0_ARQOS,
output [3:0] M_AXI_GP0_AWCACHE,
output [3:0] M_AXI_GP0_AWLEN,
output [3:0] M_AXI_GP0_AWQOS,
output [3:0] M_AXI_GP0_WSTRB,
// -- Input
input M_AXI_GP0_ACLK,
input M_AXI_GP0_ARREADY,
input M_AXI_GP0_AWREADY,
input M_AXI_GP0_BVALID,
input M_AXI_GP0_RLAST,
input M_AXI_GP0_RVALID,
input M_AXI_GP0_WREADY,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_BID,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_RID,
input [1:0] M_AXI_GP0_BRESP,
input [1:0] M_AXI_GP0_RRESP,
input [31:0] M_AXI_GP0_RDATA,
//M_AXI_GP1
// -- Output
output M_AXI_GP1_ARESETN,
output M_AXI_GP1_ARVALID,
output M_AXI_GP1_AWVALID,
output M_AXI_GP1_BREADY,
output M_AXI_GP1_RREADY,
output M_AXI_GP1_WLAST,
output M_AXI_GP1_WVALID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_ARID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_AWID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_WID,
output [1:0] M_AXI_GP1_ARBURST,
output [1:0] M_AXI_GP1_ARLOCK,
output [2:0] M_AXI_GP1_ARSIZE,
output [1:0] M_AXI_GP1_AWBURST,
output [1:0] M_AXI_GP1_AWLOCK,
output [2:0] M_AXI_GP1_AWSIZE,
output [2:0] M_AXI_GP1_ARPROT,
output [2:0] M_AXI_GP1_AWPROT,
output [31:0] M_AXI_GP1_ARADDR,
output [31:0] M_AXI_GP1_AWADDR,
output [31:0] M_AXI_GP1_WDATA,
output [3:0] M_AXI_GP1_ARCACHE,
output [3:0] M_AXI_GP1_ARLEN,
output [3:0] M_AXI_GP1_ARQOS,
output [3:0] M_AXI_GP1_AWCACHE,
output [3:0] M_AXI_GP1_AWLEN,
output [3:0] M_AXI_GP1_AWQOS,
output [3:0] M_AXI_GP1_WSTRB,
// -- Input
input M_AXI_GP1_ACLK,
input M_AXI_GP1_ARREADY,
input M_AXI_GP1_AWREADY,
input M_AXI_GP1_BVALID,
input M_AXI_GP1_RLAST,
input M_AXI_GP1_RVALID,
input M_AXI_GP1_WREADY,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_BID,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_RID,
input [1:0] M_AXI_GP1_BRESP,
input [1:0] M_AXI_GP1_RRESP,
input [31:0] M_AXI_GP1_RDATA,
// S_AXI_GP0
// -- Output
output S_AXI_GP0_ARESETN,
output S_AXI_GP0_ARREADY,
output S_AXI_GP0_AWREADY,
output S_AXI_GP0_BVALID,
output S_AXI_GP0_RLAST,
output S_AXI_GP0_RVALID,
output S_AXI_GP0_WREADY,
output [1:0] S_AXI_GP0_BRESP,
output [1:0] S_AXI_GP0_RRESP,
output [31:0] S_AXI_GP0_RDATA,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID,
// -- Input
input S_AXI_GP0_ACLK,
input S_AXI_GP0_ARVALID,
input S_AXI_GP0_AWVALID,
input S_AXI_GP0_BREADY,
input S_AXI_GP0_RREADY,
input S_AXI_GP0_WLAST,
input S_AXI_GP0_WVALID,
input [1:0] S_AXI_GP0_ARBURST,
input [1:0] S_AXI_GP0_ARLOCK,
input [2:0] S_AXI_GP0_ARSIZE,
input [1:0] S_AXI_GP0_AWBURST,
input [1:0] S_AXI_GP0_AWLOCK,
input [2:0] S_AXI_GP0_AWSIZE,
input [2:0] S_AXI_GP0_ARPROT,
input [2:0] S_AXI_GP0_AWPROT,
input [31:0] S_AXI_GP0_ARADDR,
input [31:0] S_AXI_GP0_AWADDR,
input [31:0] S_AXI_GP0_WDATA,
input [3:0] S_AXI_GP0_ARCACHE,
input [3:0] S_AXI_GP0_ARLEN,
input [3:0] S_AXI_GP0_ARQOS,
input [3:0] S_AXI_GP0_AWCACHE,
input [3:0] S_AXI_GP0_AWLEN,
input [3:0] S_AXI_GP0_AWQOS,
input [3:0] S_AXI_GP0_WSTRB,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_ARID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_AWID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_WID,
// S_AXI_GP1
// -- Output
output S_AXI_GP1_ARESETN,
output S_AXI_GP1_ARREADY,
output S_AXI_GP1_AWREADY,
output S_AXI_GP1_BVALID,
output S_AXI_GP1_RLAST,
output S_AXI_GP1_RVALID,
output S_AXI_GP1_WREADY,
output [1:0] S_AXI_GP1_BRESP,
output [1:0] S_AXI_GP1_RRESP,
output [31:0] S_AXI_GP1_RDATA,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID,
// -- Input
input S_AXI_GP1_ACLK,
input S_AXI_GP1_ARVALID,
input S_AXI_GP1_AWVALID,
input S_AXI_GP1_BREADY,
input S_AXI_GP1_RREADY,
input S_AXI_GP1_WLAST,
input S_AXI_GP1_WVALID,
input [1:0] S_AXI_GP1_ARBURST,
input [1:0] S_AXI_GP1_ARLOCK,
input [2:0] S_AXI_GP1_ARSIZE,
input [1:0] S_AXI_GP1_AWBURST,
input [1:0] S_AXI_GP1_AWLOCK,
input [2:0] S_AXI_GP1_AWSIZE,
input [2:0] S_AXI_GP1_ARPROT,
input [2:0] S_AXI_GP1_AWPROT,
input [31:0] S_AXI_GP1_ARADDR,
input [31:0] S_AXI_GP1_AWADDR,
input [31:0] S_AXI_GP1_WDATA,
input [3:0] S_AXI_GP1_ARCACHE,
input [3:0] S_AXI_GP1_ARLEN,
input [3:0] S_AXI_GP1_ARQOS,
input [3:0] S_AXI_GP1_AWCACHE,
input [3:0] S_AXI_GP1_AWLEN,
input [3:0] S_AXI_GP1_AWQOS,
input [3:0] S_AXI_GP1_WSTRB,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_ARID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_AWID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_WID,
//S_AXI_ACP
// -- Output
output S_AXI_ACP_ARESETN,
output S_AXI_ACP_ARREADY,
output S_AXI_ACP_AWREADY,
output S_AXI_ACP_BVALID,
output S_AXI_ACP_RLAST,
output S_AXI_ACP_RVALID,
output S_AXI_ACP_WREADY,
output [1:0] S_AXI_ACP_BRESP,
output [1:0] S_AXI_ACP_RRESP,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_BID,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_RID,
output [63:0] S_AXI_ACP_RDATA,
// -- Input
input S_AXI_ACP_ACLK,
input S_AXI_ACP_ARVALID,
input S_AXI_ACP_AWVALID,
input S_AXI_ACP_BREADY,
input S_AXI_ACP_RREADY,
input S_AXI_ACP_WLAST,
input S_AXI_ACP_WVALID,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_ARID,
input [2:0] S_AXI_ACP_ARPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_AWID,
input [2:0] S_AXI_ACP_AWPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_WID,
input [31:0] S_AXI_ACP_ARADDR,
input [31:0] S_AXI_ACP_AWADDR,
input [3:0] S_AXI_ACP_ARCACHE,
input [3:0] S_AXI_ACP_ARLEN,
input [3:0] S_AXI_ACP_ARQOS,
input [3:0] S_AXI_ACP_AWCACHE,
input [3:0] S_AXI_ACP_AWLEN,
input [3:0] S_AXI_ACP_AWQOS,
input [1:0] S_AXI_ACP_ARBURST,
input [1:0] S_AXI_ACP_ARLOCK,
input [2:0] S_AXI_ACP_ARSIZE,
input [1:0] S_AXI_ACP_AWBURST,
input [1:0] S_AXI_ACP_AWLOCK,
input [2:0] S_AXI_ACP_AWSIZE,
input [4:0] S_AXI_ACP_ARUSER,
input [4:0] S_AXI_ACP_AWUSER,
input [63:0] S_AXI_ACP_WDATA,
input [7:0] S_AXI_ACP_WSTRB,
// S_AXI_HP_0
// -- Output
output S_AXI_HP0_ARESETN,
output S_AXI_HP0_ARREADY,
output S_AXI_HP0_AWREADY,
output S_AXI_HP0_BVALID,
output S_AXI_HP0_RLAST,
output S_AXI_HP0_RVALID,
output S_AXI_HP0_WREADY,
output [1:0] S_AXI_HP0_BRESP,
output [1:0] S_AXI_HP0_RRESP,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_BID,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_RID,
output [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_RDATA,
output [7:0] S_AXI_HP0_RCOUNT,
output [7:0] S_AXI_HP0_WCOUNT,
output [2:0] S_AXI_HP0_RACOUNT,
output [5:0] S_AXI_HP0_WACOUNT,
// -- Input
input S_AXI_HP0_ACLK,
input S_AXI_HP0_ARVALID,
input S_AXI_HP0_AWVALID,
input S_AXI_HP0_BREADY,
input S_AXI_HP0_RDISSUECAP1_EN,
input S_AXI_HP0_RREADY,
input S_AXI_HP0_WLAST,
input S_AXI_HP0_WRISSUECAP1_EN,
input S_AXI_HP0_WVALID,
input [1:0] S_AXI_HP0_ARBURST,
input [1:0] S_AXI_HP0_ARLOCK,
input [2:0] S_AXI_HP0_ARSIZE,
input [1:0] S_AXI_HP0_AWBURST,
input [1:0] S_AXI_HP0_AWLOCK,
input [2:0] S_AXI_HP0_AWSIZE,
input [2:0] S_AXI_HP0_ARPROT,
input [2:0] S_AXI_HP0_AWPROT,
input [31:0] S_AXI_HP0_ARADDR,
input [31:0] S_AXI_HP0_AWADDR,
input [3:0] S_AXI_HP0_ARCACHE,
input [3:0] S_AXI_HP0_ARLEN,
input [3:0] S_AXI_HP0_ARQOS,
input [3:0] S_AXI_HP0_AWCACHE,
input [3:0] S_AXI_HP0_AWLEN,
input [3:0] S_AXI_HP0_AWQOS,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_ARID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_AWID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_WID,
input [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_WDATA,
input [((C_S_AXI_HP0_DATA_WIDTH/8)-1):0] S_AXI_HP0_WSTRB,
// S_AXI_HP1
// -- Output
output S_AXI_HP1_ARESETN,
output S_AXI_HP1_ARREADY,
output S_AXI_HP1_AWREADY,
output S_AXI_HP1_BVALID,
output S_AXI_HP1_RLAST,
output S_AXI_HP1_RVALID,
output S_AXI_HP1_WREADY,
output [1:0] S_AXI_HP1_BRESP,
output [1:0] S_AXI_HP1_RRESP,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_BID,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_RID,
output [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_RDATA,
output [7:0] S_AXI_HP1_RCOUNT,
output [7:0] S_AXI_HP1_WCOUNT,
output [2:0] S_AXI_HP1_RACOUNT,
output [5:0] S_AXI_HP1_WACOUNT,
// -- Input
input S_AXI_HP1_ACLK,
input S_AXI_HP1_ARVALID,
input S_AXI_HP1_AWVALID,
input S_AXI_HP1_BREADY,
input S_AXI_HP1_RDISSUECAP1_EN,
input S_AXI_HP1_RREADY,
input S_AXI_HP1_WLAST,
input S_AXI_HP1_WRISSUECAP1_EN,
input S_AXI_HP1_WVALID,
input [1:0] S_AXI_HP1_ARBURST,
input [1:0] S_AXI_HP1_ARLOCK,
input [2:0] S_AXI_HP1_ARSIZE,
input [1:0] S_AXI_HP1_AWBURST,
input [1:0] S_AXI_HP1_AWLOCK,
input [2:0] S_AXI_HP1_AWSIZE,
input [2:0] S_AXI_HP1_ARPROT,
input [2:0] S_AXI_HP1_AWPROT,
input [31:0] S_AXI_HP1_ARADDR,
input [31:0] S_AXI_HP1_AWADDR,
input [3:0] S_AXI_HP1_ARCACHE,
input [3:0] S_AXI_HP1_ARLEN,
input [3:0] S_AXI_HP1_ARQOS,
input [3:0] S_AXI_HP1_AWCACHE,
input [3:0] S_AXI_HP1_AWLEN,
input [3:0] S_AXI_HP1_AWQOS,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_ARID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_AWID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_WID,
input [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_WDATA,
input [((C_S_AXI_HP1_DATA_WIDTH/8)-1):0] S_AXI_HP1_WSTRB,
// S_AXI_HP2
// -- Output
output S_AXI_HP2_ARESETN,
output S_AXI_HP2_ARREADY,
output S_AXI_HP2_AWREADY,
output S_AXI_HP2_BVALID,
output S_AXI_HP2_RLAST,
output S_AXI_HP2_RVALID,
output S_AXI_HP2_WREADY,
output [1:0] S_AXI_HP2_BRESP,
output [1:0] S_AXI_HP2_RRESP,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_BID,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_RID,
output [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_RDATA,
output [7:0] S_AXI_HP2_RCOUNT,
output [7:0] S_AXI_HP2_WCOUNT,
output [2:0] S_AXI_HP2_RACOUNT,
output [5:0] S_AXI_HP2_WACOUNT,
// -- Input
input S_AXI_HP2_ACLK,
input S_AXI_HP2_ARVALID,
input S_AXI_HP2_AWVALID,
input S_AXI_HP2_BREADY,
input S_AXI_HP2_RDISSUECAP1_EN,
input S_AXI_HP2_RREADY,
input S_AXI_HP2_WLAST,
input S_AXI_HP2_WRISSUECAP1_EN,
input S_AXI_HP2_WVALID,
input [1:0] S_AXI_HP2_ARBURST,
input [1:0] S_AXI_HP2_ARLOCK,
input [2:0] S_AXI_HP2_ARSIZE,
input [1:0] S_AXI_HP2_AWBURST,
input [1:0] S_AXI_HP2_AWLOCK,
input [2:0] S_AXI_HP2_AWSIZE,
input [2:0] S_AXI_HP2_ARPROT,
input [2:0] S_AXI_HP2_AWPROT,
input [31:0] S_AXI_HP2_ARADDR,
input [31:0] S_AXI_HP2_AWADDR,
input [3:0] S_AXI_HP2_ARCACHE,
input [3:0] S_AXI_HP2_ARLEN,
input [3:0] S_AXI_HP2_ARQOS,
input [3:0] S_AXI_HP2_AWCACHE,
input [3:0] S_AXI_HP2_AWLEN,
input [3:0] S_AXI_HP2_AWQOS,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_ARID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_AWID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_WID,
input [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_WDATA,
input [((C_S_AXI_HP2_DATA_WIDTH/8)-1):0] S_AXI_HP2_WSTRB,
// S_AXI_HP_3
// -- Output
output S_AXI_HP3_ARESETN,
output S_AXI_HP3_ARREADY,
output S_AXI_HP3_AWREADY,
output S_AXI_HP3_BVALID,
output S_AXI_HP3_RLAST,
output S_AXI_HP3_RVALID,
output S_AXI_HP3_WREADY,
output [1:0] S_AXI_HP3_BRESP,
output [1:0] S_AXI_HP3_RRESP,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_BID,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_RID,
output [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_RDATA,
output [7:0] S_AXI_HP3_RCOUNT,
output [7:0] S_AXI_HP3_WCOUNT,
output [2:0] S_AXI_HP3_RACOUNT,
output [5:0] S_AXI_HP3_WACOUNT,
// -- Input
input S_AXI_HP3_ACLK,
input S_AXI_HP3_ARVALID,
input S_AXI_HP3_AWVALID,
input S_AXI_HP3_BREADY,
input S_AXI_HP3_RDISSUECAP1_EN,
input S_AXI_HP3_RREADY,
input S_AXI_HP3_WLAST,
input S_AXI_HP3_WRISSUECAP1_EN,
input S_AXI_HP3_WVALID,
input [1:0] S_AXI_HP3_ARBURST,
input [1:0] S_AXI_HP3_ARLOCK,
input [2:0] S_AXI_HP3_ARSIZE,
input [1:0] S_AXI_HP3_AWBURST,
input [1:0] S_AXI_HP3_AWLOCK,
input [2:0] S_AXI_HP3_AWSIZE,
input [2:0] S_AXI_HP3_ARPROT,
input [2:0] S_AXI_HP3_AWPROT,
input [31:0] S_AXI_HP3_ARADDR,
input [31:0] S_AXI_HP3_AWADDR,
input [3:0] S_AXI_HP3_ARCACHE,
input [3:0] S_AXI_HP3_ARLEN,
input [3:0] S_AXI_HP3_ARQOS,
input [3:0] S_AXI_HP3_AWCACHE,
input [3:0] S_AXI_HP3_AWLEN,
input [3:0] S_AXI_HP3_AWQOS,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_ARID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_AWID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_WID,
input [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_WDATA,
input [((C_S_AXI_HP3_DATA_WIDTH/8)-1):0] S_AXI_HP3_WSTRB,
//FIO ========================================
//IRQ
//output [28:0] IRQ_P2F,
output IRQ_P2F_DMAC_ABORT ,
output IRQ_P2F_DMAC0,
output IRQ_P2F_DMAC1,
output IRQ_P2F_DMAC2,
output IRQ_P2F_DMAC3,
output IRQ_P2F_DMAC4,
output IRQ_P2F_DMAC5,
output IRQ_P2F_DMAC6,
output IRQ_P2F_DMAC7,
output IRQ_P2F_SMC,
output IRQ_P2F_QSPI,
output IRQ_P2F_CTI,
output IRQ_P2F_GPIO,
output IRQ_P2F_USB0,
output IRQ_P2F_ENET0,
output IRQ_P2F_ENET_WAKE0,
output IRQ_P2F_SDIO0,
output IRQ_P2F_I2C0,
output IRQ_P2F_SPI0,
output IRQ_P2F_UART0,
output IRQ_P2F_CAN0,
output IRQ_P2F_USB1,
output IRQ_P2F_ENET1,
output IRQ_P2F_ENET_WAKE1,
output IRQ_P2F_SDIO1,
output IRQ_P2F_I2C1,
output IRQ_P2F_SPI1,
output IRQ_P2F_UART1,
output IRQ_P2F_CAN1,
input [(C_NUM_F2P_INTR_INPUTS-1):0] IRQ_F2P,
input Core0_nFIQ,
input Core0_nIRQ,
input Core1_nFIQ,
input Core1_nIRQ,
//DMA
output [1:0] DMA0_DATYPE,
output DMA0_DAVALID,
output DMA0_DRREADY,
output DMA0_RSTN,
output [1:0] DMA1_DATYPE,
output DMA1_DAVALID,
output DMA1_DRREADY,
output DMA1_RSTN,
output [1:0] DMA2_DATYPE,
output DMA2_DAVALID,
output DMA2_DRREADY,
output DMA2_RSTN,
output [1:0] DMA3_DATYPE,
output DMA3_DAVALID,
output DMA3_DRREADY,
output DMA3_RSTN,
input DMA0_ACLK,
input DMA0_DAREADY,
input DMA0_DRLAST,
input DMA0_DRVALID,
input DMA1_ACLK,
input DMA1_DAREADY,
input DMA1_DRLAST,
input DMA1_DRVALID,
input DMA2_ACLK,
input DMA2_DAREADY,
input DMA2_DRLAST,
input DMA2_DRVALID,
input DMA3_ACLK,
input DMA3_DAREADY,
input DMA3_DRLAST,
input DMA3_DRVALID,
input [1:0] DMA0_DRTYPE,
input [1:0] DMA1_DRTYPE,
input [1:0] DMA2_DRTYPE,
input [1:0] DMA3_DRTYPE,
//FCLK
output FCLK_CLK3,
output FCLK_CLK2,
output FCLK_CLK1,
output FCLK_CLK0,
input FCLK_CLKTRIG3_N,
input FCLK_CLKTRIG2_N,
input FCLK_CLKTRIG1_N,
input FCLK_CLKTRIG0_N,
output FCLK_RESET3_N,
output FCLK_RESET2_N,
output FCLK_RESET1_N,
output FCLK_RESET0_N,
//FTMD
input [31:0] FTMD_TRACEIN_DATA,
input FTMD_TRACEIN_VALID,
input FTMD_TRACEIN_CLK,
input [3:0] FTMD_TRACEIN_ATID,
//FTMT
input FTMT_F2P_TRIG_0,
output FTMT_F2P_TRIGACK_0,
input FTMT_F2P_TRIG_1,
output FTMT_F2P_TRIGACK_1,
input FTMT_F2P_TRIG_2,
output FTMT_F2P_TRIGACK_2,
input FTMT_F2P_TRIG_3,
output FTMT_F2P_TRIGACK_3,
input [31:0] FTMT_F2P_DEBUG,
input FTMT_P2F_TRIGACK_0,
output FTMT_P2F_TRIG_0,
input FTMT_P2F_TRIGACK_1,
output FTMT_P2F_TRIG_1,
input FTMT_P2F_TRIGACK_2,
output FTMT_P2F_TRIG_2,
input FTMT_P2F_TRIGACK_3,
output FTMT_P2F_TRIG_3,
output [31:0] FTMT_P2F_DEBUG,
//FIDLE
input FPGA_IDLE_N,
//EVENT
output EVENT_EVENTO,
output [1:0] EVENT_STANDBYWFE,
output [1:0] EVENT_STANDBYWFI,
input EVENT_EVENTI,
//DARB
input [3:0] DDR_ARB,
inout [C_MIO_PRIMITIVE - 1:0] MIO,
//DDR
inout DDR_CAS_n, // CASB
inout DDR_CKE, // CKE
inout DDR_Clk_n, // CKN
inout DDR_Clk, // CKP
inout DDR_CS_n, // CSB
inout DDR_DRSTB, // DDR_DRSTB
inout DDR_ODT, // ODT
inout DDR_RAS_n, // RASB
inout DDR_WEB,
inout [2:0] DDR_BankAddr, // BA
inout [14:0] DDR_Addr, // A
inout DDR_VRN,
inout DDR_VRP,
inout [C_DM_WIDTH - 1:0] DDR_DM, // DM
inout [C_DQ_WIDTH - 1:0] DDR_DQ, // DQ
inout [C_DQS_WIDTH -1:0] DDR_DQS_n, // DQSN
inout [C_DQS_WIDTH - 1:0] DDR_DQS, // DQSP
inout PS_SRSTB, // SRSTB
inout PS_CLK, // CLK
inout PS_PORB // PORB
);
wire [11:0] M_AXI_GP0_AWID_FULL;
wire [11:0] M_AXI_GP0_WID_FULL;
wire [11:0] M_AXI_GP0_ARID_FULL;
wire [11:0] M_AXI_GP0_BID_FULL;
wire [11:0] M_AXI_GP0_RID_FULL;
wire [11:0] M_AXI_GP1_AWID_FULL;
wire [11:0] M_AXI_GP1_WID_FULL;
wire [11:0] M_AXI_GP1_ARID_FULL;
wire [11:0] M_AXI_GP1_BID_FULL;
wire [11:0] M_AXI_GP1_RID_FULL;
wire ENET0_GMII_TX_EN_i;
wire ENET0_GMII_TX_ER_i;
reg ENET0_GMII_COL_i;
reg ENET0_GMII_CRS_i;
reg ENET0_GMII_RX_DV_i;
reg ENET0_GMII_RX_ER_i;
reg [7:0] ENET0_GMII_RXD_i;
wire [7:0] ENET0_GMII_TXD_i;
wire ENET1_GMII_TX_EN_i;
wire ENET1_GMII_TX_ER_i;
reg ENET1_GMII_COL_i;
reg ENET1_GMII_CRS_i;
reg ENET1_GMII_RX_DV_i;
reg ENET1_GMII_RX_ER_i;
reg [7:0] ENET1_GMII_RXD_i;
wire [7:0] ENET1_GMII_TXD_i;
reg [31:0] FTMD_TRACEIN_DATA_notracebuf;
reg FTMD_TRACEIN_VALID_notracebuf;
reg [3:0] FTMD_TRACEIN_ATID_notracebuf;
wire [31:0] FTMD_TRACEIN_DATA_i;
wire FTMD_TRACEIN_VALID_i;
wire [3:0] FTMD_TRACEIN_ATID_i;
wire [31:0] FTMD_TRACEIN_DATA_tracebuf;
wire FTMD_TRACEIN_VALID_tracebuf;
wire [3:0] FTMD_TRACEIN_ATID_tracebuf;
wire [5:0] S_AXI_GP0_BID_out;
wire [5:0] S_AXI_GP0_RID_out;
wire [5:0] S_AXI_GP0_ARID_in;
wire [5:0] S_AXI_GP0_AWID_in;
wire [5:0] S_AXI_GP0_WID_in;
wire [5:0] S_AXI_GP1_BID_out;
wire [5:0] S_AXI_GP1_RID_out;
wire [5:0] S_AXI_GP1_ARID_in;
wire [5:0] S_AXI_GP1_AWID_in;
wire [5:0] S_AXI_GP1_WID_in;
wire [5:0] S_AXI_HP0_BID_out;
wire [5:0] S_AXI_HP0_RID_out;
wire [5:0] S_AXI_HP0_ARID_in;
wire [5:0] S_AXI_HP0_AWID_in;
wire [5:0] S_AXI_HP0_WID_in;
wire [5:0] S_AXI_HP1_BID_out;
wire [5:0] S_AXI_HP1_RID_out;
wire [5:0] S_AXI_HP1_ARID_in;
wire [5:0] S_AXI_HP1_AWID_in;
wire [5:0] S_AXI_HP1_WID_in;
wire [5:0] S_AXI_HP2_BID_out;
wire [5:0] S_AXI_HP2_RID_out;
wire [5:0] S_AXI_HP2_ARID_in;
wire [5:0] S_AXI_HP2_AWID_in;
wire [5:0] S_AXI_HP2_WID_in;
wire [5:0] S_AXI_HP3_BID_out;
wire [5:0] S_AXI_HP3_RID_out;
wire [5:0] S_AXI_HP3_ARID_in;
wire [5:0] S_AXI_HP3_AWID_in;
wire [5:0] S_AXI_HP3_WID_in;
wire [2:0] S_AXI_ACP_BID_out;
wire [2:0] S_AXI_ACP_RID_out;
wire [2:0] S_AXI_ACP_ARID_in;
wire [2:0] S_AXI_ACP_AWID_in;
wire [2:0] S_AXI_ACP_WID_in;
wire [63:0] S_AXI_HP0_WDATA_in;
wire [7:0] S_AXI_HP0_WSTRB_in;
wire [63:0] S_AXI_HP0_RDATA_out;
wire [63:0] S_AXI_HP1_WDATA_in;
wire [7:0] S_AXI_HP1_WSTRB_in;
wire [63:0] S_AXI_HP1_RDATA_out;
wire [63:0] S_AXI_HP2_WDATA_in;
wire [7:0] S_AXI_HP2_WSTRB_in;
wire [63:0] S_AXI_HP2_RDATA_out;
wire [63:0] S_AXI_HP3_WDATA_in;
wire [7:0] S_AXI_HP3_WSTRB_in;
wire [63:0] S_AXI_HP3_RDATA_out;
wire [1:0] M_AXI_GP0_ARSIZE_i;
wire [1:0] M_AXI_GP0_AWSIZE_i;
wire [1:0] M_AXI_GP1_ARSIZE_i;
wire [1:0] M_AXI_GP1_AWSIZE_i;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPBID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPRID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPARID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPAWID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPWID_W;
wire SAXIACPARREADY_W;
wire SAXIACPAWREADY_W;
wire SAXIACPBVALID_W;
wire SAXIACPRLAST_W;
wire SAXIACPRVALID_W;
wire SAXIACPWREADY_W;
wire [1:0] SAXIACPBRESP_W;
wire [1:0] SAXIACPRRESP_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_BID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_RID;
wire [63:0] SAXIACPRDATA_W;
wire S_AXI_ATC_ARVALID;
wire S_AXI_ATC_AWVALID;
wire S_AXI_ATC_BREADY;
wire S_AXI_ATC_RREADY;
wire S_AXI_ATC_WLAST;
wire S_AXI_ATC_WVALID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_ARID;
wire [2:0] S_AXI_ATC_ARPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_AWID;
wire [2:0] S_AXI_ATC_AWPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_WID;
wire [31:0] S_AXI_ATC_ARADDR;
wire [31:0] S_AXI_ATC_AWADDR;
wire [3:0] S_AXI_ATC_ARCACHE;
wire [3:0] S_AXI_ATC_ARLEN;
wire [3:0] S_AXI_ATC_ARQOS;
wire [3:0] S_AXI_ATC_AWCACHE;
wire [3:0] S_AXI_ATC_AWLEN;
wire [3:0] S_AXI_ATC_AWQOS;
wire [1:0] S_AXI_ATC_ARBURST;
wire [1:0] S_AXI_ATC_ARLOCK;
wire [2:0] S_AXI_ATC_ARSIZE;
wire [1:0] S_AXI_ATC_AWBURST;
wire [1:0] S_AXI_ATC_AWLOCK;
wire [2:0] S_AXI_ATC_AWSIZE;
wire [4:0] S_AXI_ATC_ARUSER;
wire [4:0] S_AXI_ATC_AWUSER;
wire [63:0] S_AXI_ATC_WDATA;
wire [7:0] S_AXI_ATC_WSTRB;
wire SAXIACPARVALID_W;
wire SAXIACPAWVALID_W;
wire SAXIACPBREADY_W;
wire SAXIACPRREADY_W;
wire SAXIACPWLAST_W;
wire SAXIACPWVALID_W;
wire [2:0] SAXIACPARPROT_W;
wire [2:0] SAXIACPAWPROT_W;
wire [31:0] SAXIACPARADDR_W;
wire [31:0] SAXIACPAWADDR_W;
wire [3:0] SAXIACPARCACHE_W;
wire [3:0] SAXIACPARLEN_W;
wire [3:0] SAXIACPARQOS_W;
wire [3:0] SAXIACPAWCACHE_W;
wire [3:0] SAXIACPAWLEN_W;
wire [3:0] SAXIACPAWQOS_W;
wire [1:0] SAXIACPARBURST_W;
wire [1:0] SAXIACPARLOCK_W;
wire [2:0] SAXIACPARSIZE_W;
wire [1:0] SAXIACPAWBURST_W;
wire [1:0] SAXIACPAWLOCK_W;
wire [2:0] SAXIACPAWSIZE_W;
wire [4:0] SAXIACPARUSER_W;
wire [4:0] SAXIACPAWUSER_W;
wire [63:0] SAXIACPWDATA_W;
wire [7:0] SAXIACPWSTRB_W;
// AxUSER signal update
wire [4:0] param_aruser;
wire [4:0] param_awuser;
// Added to address CR 651751
wire [3:0] fclk_clktrig_gnd = 4'h0;
wire [19:0] irq_f2p_i;
wire [15:0] irq_f2p_null = 16'h0000;
// EMIO I2C0
wire I2C0_SDA_T_n;
wire I2C0_SCL_T_n;
// EMIO I2C1
wire I2C1_SDA_T_n;
wire I2C1_SCL_T_n;
// EMIO SPI0
wire SPI0_SCLK_T_n;
wire SPI0_MOSI_T_n;
wire SPI0_MISO_T_n;
wire SPI0_SS_T_n;
// EMIO SPI1
wire SPI1_SCLK_T_n;
wire SPI1_MOSI_T_n;
wire SPI1_MISO_T_n;
wire SPI1_SS_T_n;
// EMIO GEM0
wire ENET0_MDIO_T_n;
// EMIO GEM1
wire ENET1_MDIO_T_n;
// EMIO GPIO
wire [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T_n;
wire [63:0] gpio_out_t_n;
wire [63:0] gpio_out;
wire [63:0] gpio_in63_0;
//For Clock buffering
wire [3:0] FCLK_CLK_unbuffered;
wire [3:0] FCLK_CLK_buffered;
// EMIO PJTAG
wire PJTAG_TDO_O;
wire PJTAG_TDO_T;
wire PJTAG_TDO_T_n;
// EMIO SDIO0
wire SDIO0_CMD_T_n;
wire [3:0] SDIO0_DATA_T_n;
// EMIO SDIO1
wire SDIO1_CMD_T_n;
wire [3:0] SDIO1_DATA_T_n;
// buffered IO
wire [C_MIO_PRIMITIVE - 1:0] buffered_MIO;
wire buffered_DDR_WEB;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_Clk_n;
wire buffered_DDR_Clk;
wire buffered_DDR_CS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire [2:0] buffered_DDR_BankAddr;
wire [14:0] buffered_DDR_Addr;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire [C_DM_WIDTH - 1:0] buffered_DDR_DM;
wire [C_DQ_WIDTH - 1:0] buffered_DDR_DQ;
wire [C_DQS_WIDTH -1:0] buffered_DDR_DQS_n;
wire [C_DQS_WIDTH - 1:0] buffered_DDR_DQS;
wire buffered_PS_SRSTB;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire [31:0] TRACE_DATA_i;
wire TRACE_CTL_i;
reg TRACE_CTL_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
reg [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
// fixed CR #665394
integer j;
generate
if (C_EN_EMIO_TRACE == 1) begin
always @(posedge TRACE_CLK)
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_CTL_i;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_DATA_i[(C_TRACE_INTERNAL_WIDTH-1):0];
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= TRACE_CTL_PIPE[j];
TRACE_DATA_PIPE[j-1] <= TRACE_DATA_PIPE[j];
end
TRACE_CLK_OUT <= ~TRACE_CLK_OUT;
end
end
endgenerate
assign TRACE_CTL = TRACE_CTL_PIPE[0];
assign TRACE_DATA = TRACE_DATA_PIPE[0];
//irq_p2f
// Updated IRQ_F2P logic to address CR 641523
generate
if(C_NUM_F2P_INTR_INPUTS == 0) begin : irq_f2p_select_null
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,irq_f2p_null[15:0]};
end else if(C_NUM_F2P_INTR_INPUTS == 16) begin : irq_f2p_select_all
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,IRQ_F2P[15:0]};
end else begin : irq_f2p_select
if (C_IRQ_F2P_MODE == "DIRECT") begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0],
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0]};
end else begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0],
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0]};
end
end
endgenerate
assign M_AXI_GP0_ARSIZE[2:0] = {1'b0, M_AXI_GP0_ARSIZE_i[1:0]};
assign M_AXI_GP0_AWSIZE[2:0] = {1'b0, M_AXI_GP0_AWSIZE_i[1:0]};
assign M_AXI_GP1_ARSIZE[2:0] = {1'b0, M_AXI_GP1_ARSIZE_i[1:0]};
assign M_AXI_GP1_AWSIZE[2:0] = {1'b0, M_AXI_GP1_AWSIZE_i[1:0]};
// Compress Function
// Modified as per CR 631955
//function [11:0] uncompress_id;
// input [5:0] id;
// begin
// case (id[5:0])
// // dmac0
// 6'd1 : uncompress_id = 12'b010000_1000_00 ;
// 6'd2 : uncompress_id = 12'b010000_0000_00 ;
// 6'd3 : uncompress_id = 12'b010000_0001_00 ;
// 6'd4 : uncompress_id = 12'b010000_0010_00 ;
// 6'd5 : uncompress_id = 12'b010000_0011_00 ;
// 6'd6 : uncompress_id = 12'b010000_0100_00 ;
// 6'd7 : uncompress_id = 12'b010000_0101_00 ;
// 6'd8 : uncompress_id = 12'b010000_0110_00 ;
// 6'd9 : uncompress_id = 12'b010000_0111_00 ;
// // ioum
// 6'd10 : uncompress_id = 12'b0100000_000_01 ;
// 6'd11 : uncompress_id = 12'b0100000_001_01 ;
// 6'd12 : uncompress_id = 12'b0100000_010_01 ;
// 6'd13 : uncompress_id = 12'b0100000_011_01 ;
// 6'd14 : uncompress_id = 12'b0100000_100_01 ;
// 6'd15 : uncompress_id = 12'b0100000_101_01 ;
// // devci
// 6'd16 : uncompress_id = 12'b1000_0000_0000 ;
// // dap
// 6'd17 : uncompress_id = 12'b1000_0000_0001 ;
// // l2m1 (CPU000)
// 6'd18 : uncompress_id = 12'b11_000_000_00_00 ;
// 6'd19 : uncompress_id = 12'b11_010_000_00_00 ;
// 6'd20 : uncompress_id = 12'b11_011_000_00_00 ;
// 6'd21 : uncompress_id = 12'b11_100_000_00_00 ;
// 6'd22 : uncompress_id = 12'b11_101_000_00_00 ;
// 6'd23 : uncompress_id = 12'b11_110_000_00_00 ;
// 6'd24 : uncompress_id = 12'b11_111_000_00_00 ;
// // l2m1 (CPU001)
// 6'd25 : uncompress_id = 12'b11_000_001_00_00 ;
// 6'd26 : uncompress_id = 12'b11_010_001_00_00 ;
// 6'd27 : uncompress_id = 12'b11_011_001_00_00 ;
// 6'd28 : uncompress_id = 12'b11_100_001_00_00 ;
// 6'd29 : uncompress_id = 12'b11_101_001_00_00 ;
// 6'd30 : uncompress_id = 12'b11_110_001_00_00 ;
// 6'd31 : uncompress_id = 12'b11_111_001_00_00 ;
// // l2m1 (L2CC)
// 6'd32 : uncompress_id = 12'b11_000_00101_00 ;
// 6'd33 : uncompress_id = 12'b11_000_01001_00 ;
// 6'd34 : uncompress_id = 12'b11_000_01101_00 ;
// 6'd35 : uncompress_id = 12'b11_000_10011_00 ;
// 6'd36 : uncompress_id = 12'b11_000_10111_00 ;
// 6'd37 : uncompress_id = 12'b11_000_11011_00 ;
// 6'd38 : uncompress_id = 12'b11_000_11111_00 ;
// 6'd39 : uncompress_id = 12'b11_000_00011_00 ;
// 6'd40 : uncompress_id = 12'b11_000_00111_00 ;
// 6'd41 : uncompress_id = 12'b11_000_01011_00 ;
// 6'd42 : uncompress_id = 12'b11_000_01111_00 ;
// 6'd43 : uncompress_id = 12'b11_000_00001_00 ;
// // l2m1 (ACP)
// 6'd44 : uncompress_id = 12'b11_000_10000_00 ;
// 6'd45 : uncompress_id = 12'b11_001_10000_00 ;
// 6'd46 : uncompress_id = 12'b11_010_10000_00 ;
// 6'd47 : uncompress_id = 12'b11_011_10000_00 ;
// 6'd48 : uncompress_id = 12'b11_100_10000_00 ;
// 6'd49 : uncompress_id = 12'b11_101_10000_00 ;
// 6'd50 : uncompress_id = 12'b11_110_10000_00 ;
// 6'd51 : uncompress_id = 12'b11_111_10000_00 ;
// default : uncompress_id = ~0;
// endcase
// end
//endfunction
//
//function [5:0] compress_id;
// input [11:0] id;
// begin
// case (id[11:0])
// // dmac0
// 12'b010000_1000_00 : compress_id = 'd1 ;
// 12'b010000_0000_00 : compress_id = 'd2 ;
// 12'b010000_0001_00 : compress_id = 'd3 ;
// 12'b010000_0010_00 : compress_id = 'd4 ;
// 12'b010000_0011_00 : compress_id = 'd5 ;
// 12'b010000_0100_00 : compress_id = 'd6 ;
// 12'b010000_0101_00 : compress_id = 'd7 ;
// 12'b010000_0110_00 : compress_id = 'd8 ;
// 12'b010000_0111_00 : compress_id = 'd9 ;
// // ioum
// 12'b0100000_000_01 : compress_id = 'd10 ;
// 12'b0100000_001_01 : compress_id = 'd11 ;
// 12'b0100000_010_01 : compress_id = 'd12 ;
// 12'b0100000_011_01 : compress_id = 'd13 ;
// 12'b0100000_100_01 : compress_id = 'd14 ;
// 12'b0100000_101_01 : compress_id = 'd15 ;
// // devci
// 12'b1000_0000_0000 : compress_id = 'd16 ;
// // dap
// 12'b1000_0000_0001 : compress_id = 'd17 ;
// // l2m1 (CPU000)
// 12'b11_000_000_00_00 : compress_id = 'd18 ;
// 12'b11_010_000_00_00 : compress_id = 'd19 ;
// 12'b11_011_000_00_00 : compress_id = 'd20 ;
// 12'b11_100_000_00_00 : compress_id = 'd21 ;
// 12'b11_101_000_00_00 : compress_id = 'd22 ;
// 12'b11_110_000_00_00 : compress_id = 'd23 ;
// 12'b11_111_000_00_00 : compress_id = 'd24 ;
// // l2m1 (CPU001)
// 12'b11_000_001_00_00 : compress_id = 'd25 ;
// 12'b11_010_001_00_00 : compress_id = 'd26 ;
// 12'b11_011_001_00_00 : compress_id = 'd27 ;
// 12'b11_100_001_00_00 : compress_id = 'd28 ;
// 12'b11_101_001_00_00 : compress_id = 'd29 ;
// 12'b11_110_001_00_00 : compress_id = 'd30 ;
// 12'b11_111_001_00_00 : compress_id = 'd31 ;
// // l2m1 (L2CC)
// 12'b11_000_00101_00 : compress_id = 'd32 ;
// 12'b11_000_01001_00 : compress_id = 'd33 ;
// 12'b11_000_01101_00 : compress_id = 'd34 ;
// 12'b11_000_10011_00 : compress_id = 'd35 ;
// 12'b11_000_10111_00 : compress_id = 'd36 ;
// 12'b11_000_11011_00 : compress_id = 'd37 ;
// 12'b11_000_11111_00 : compress_id = 'd38 ;
// 12'b11_000_00011_00 : compress_id = 'd39 ;
// 12'b11_000_00111_00 : compress_id = 'd40 ;
// 12'b11_000_01011_00 : compress_id = 'd41 ;
// 12'b11_000_01111_00 : compress_id = 'd42 ;
// 12'b11_000_00001_00 : compress_id = 'd43 ;
// // l2m1 (ACP)
// 12'b11_000_10000_00 : compress_id = 'd44 ;
// 12'b11_001_10000_00 : compress_id = 'd45 ;
// 12'b11_010_10000_00 : compress_id = 'd46 ;
// 12'b11_011_10000_00 : compress_id = 'd47 ;
// 12'b11_100_10000_00 : compress_id = 'd48 ;
// 12'b11_101_10000_00 : compress_id = 'd49 ;
// 12'b11_110_10000_00 : compress_id = 'd50 ;
// 12'b11_111_10000_00 : compress_id = 'd51 ;
// default: compress_id = ~0;
// endcase
// end
//endfunction
// Modified as per CR 648393
function [5:0] compress_id;
input [11:0] id;
begin
compress_id[0] = id[7] | (id[4] & id[2]) | (~id[11] & id[2]) | (id[11] & id[0]);
compress_id[1] = id[8] | id[5] | (~id[11] & id[3]);
compress_id[2] = id[9] | (id[6] & id[3] & id[2]) | (~id[11] & id[4]);
compress_id[3] = (id[11] & id[10] & id[4]) | (id[11] & id[10] & id[2]) | (~id[11] & id[10] & ~id[5] & ~id[0]);
compress_id[4] = (id[11] & id[3]) | (id[10] & id[0]) | (id[11] & id[10] & ~id[2] &~id[6]);
compress_id[5] = id[11] & id[10] & ~id[3];
end
endfunction
function [11:0] uncompress_id;
input [5:0] id;
begin
case (id[5:0])
// dmac0
6'b000_010 : uncompress_id = 12'b010000_1000_00 ;
6'b001_000 : uncompress_id = 12'b010000_0000_00 ;
6'b001_001 : uncompress_id = 12'b010000_0001_00 ;
6'b001_010 : uncompress_id = 12'b010000_0010_00 ;
6'b001_011 : uncompress_id = 12'b010000_0011_00 ;
6'b001_100 : uncompress_id = 12'b010000_0100_00 ;
6'b001_101 : uncompress_id = 12'b010000_0101_00 ;
6'b001_110 : uncompress_id = 12'b010000_0110_00 ;
6'b001_111 : uncompress_id = 12'b010000_0111_00 ;
// ioum
6'b010_000 : uncompress_id = 12'b0100000_000_01 ;
6'b010_001 : uncompress_id = 12'b0100000_001_01 ;
6'b010_010 : uncompress_id = 12'b0100000_010_01 ;
6'b010_011 : uncompress_id = 12'b0100000_011_01 ;
6'b010_100 : uncompress_id = 12'b0100000_100_01 ;
6'b010_101 : uncompress_id = 12'b0100000_101_01 ;
// devci
6'b000_000 : uncompress_id = 12'b1000_0000_0000 ;
// dap
6'b000_001 : uncompress_id = 12'b1000_0000_0001 ;
// l2m1 (CPU000)
6'b110_000 : uncompress_id = 12'b11_000_000_00_00 ;
6'b110_010 : uncompress_id = 12'b11_010_000_00_00 ;
6'b110_011 : uncompress_id = 12'b11_011_000_00_00 ;
6'b110_100 : uncompress_id = 12'b11_100_000_00_00 ;
6'b110_101 : uncompress_id = 12'b11_101_000_00_00 ;
6'b110_110 : uncompress_id = 12'b11_110_000_00_00 ;
6'b110_111 : uncompress_id = 12'b11_111_000_00_00 ;
// l2m1 (CPU001)
6'b111_000 : uncompress_id = 12'b11_000_001_00_00 ;
6'b111_010 : uncompress_id = 12'b11_010_001_00_00 ;
6'b111_011 : uncompress_id = 12'b11_011_001_00_00 ;
6'b111_100 : uncompress_id = 12'b11_100_001_00_00 ;
6'b111_101 : uncompress_id = 12'b11_101_001_00_00 ;
6'b111_110 : uncompress_id = 12'b11_110_001_00_00 ;
6'b111_111 : uncompress_id = 12'b11_111_001_00_00 ;
// l2m1 (L2CC)
6'b101_001 : uncompress_id = 12'b11_000_00101_00 ;
6'b101_010 : uncompress_id = 12'b11_000_01001_00 ;
6'b101_011 : uncompress_id = 12'b11_000_01101_00 ;
6'b011_100 : uncompress_id = 12'b11_000_10011_00 ;
6'b011_101 : uncompress_id = 12'b11_000_10111_00 ;
6'b011_110 : uncompress_id = 12'b11_000_11011_00 ;
6'b011_111 : uncompress_id = 12'b11_000_11111_00 ;
6'b011_000 : uncompress_id = 12'b11_000_00011_00 ;
6'b011_001 : uncompress_id = 12'b11_000_00111_00 ;
6'b011_010 : uncompress_id = 12'b11_000_01011_00 ;
6'b011_011 : uncompress_id = 12'b11_000_01111_00 ;
6'b101_000 : uncompress_id = 12'b11_000_00001_00 ;
// l2m1 (ACP)
6'b100_000 : uncompress_id = 12'b11_000_10000_00 ;
6'b100_001 : uncompress_id = 12'b11_001_10000_00 ;
6'b100_010 : uncompress_id = 12'b11_010_10000_00 ;
6'b100_011 : uncompress_id = 12'b11_011_10000_00 ;
6'b100_100 : uncompress_id = 12'b11_100_10000_00 ;
6'b100_101 : uncompress_id = 12'b11_101_10000_00 ;
6'b100_110 : uncompress_id = 12'b11_110_10000_00 ;
6'b100_111 : uncompress_id = 12'b11_111_10000_00 ;
default : uncompress_id = 12'hx ;
endcase
end
endfunction
// Static Remap logic Enablement and Disablement for C_M_AXI0 port
assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL;
assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL;
assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL;
assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID;
assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID;
// Static Remap logic Enablement and Disablement for C_M_AXI1 port
assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL;
assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL;
assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL;
assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID;
assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID;
//// Compress_id and uncompress_id has been removed to address CR 642527
//// AXI interconnect v1.05.a and beyond implements dynamic ID compression/decompression.
// assign M_AXI_GP0_AWID = M_AXI_GP0_AWID_FULL;
// assign M_AXI_GP0_WID = M_AXI_GP0_WID_FULL;
// assign M_AXI_GP0_ARID = M_AXI_GP0_ARID_FULL;
// assign M_AXI_GP0_BID_FULL = M_AXI_GP0_BID;
// assign M_AXI_GP0_RID_FULL = M_AXI_GP0_RID;
//
// assign M_AXI_GP1_AWID = M_AXI_GP1_AWID_FULL;
// assign M_AXI_GP1_WID = M_AXI_GP1_WID_FULL;
// assign M_AXI_GP1_ARID = M_AXI_GP1_ARID_FULL;
// assign M_AXI_GP1_BID_FULL = M_AXI_GP1_BID;
// assign M_AXI_GP1_RID_FULL = M_AXI_GP1_RID;
// Pipeline Stage for ENET0
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_TX_CLK)
begin
ENET0_GMII_TXD <= ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= ENET0_GMII_COL;
ENET0_GMII_CRS_i <= ENET0_GMII_CRS;
end
end
endgenerate
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_RX_CLK)
begin
ENET0_GMII_RXD_i <= ENET0_GMII_RXD;
ENET0_GMII_RX_DV_i <= ENET0_GMII_RX_DV;
ENET0_GMII_RX_ER_i <= ENET0_GMII_RX_ER;
end
end
endgenerate
// Pipeline Stage for ENET1
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_TX_CLK)
begin
ENET1_GMII_TXD <= ENET1_GMII_TXD_i;
ENET1_GMII_TX_EN <= ENET1_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= ENET1_GMII_TX_ER_i;
ENET1_GMII_COL_i <= ENET1_GMII_COL;
ENET1_GMII_CRS_i <= ENET1_GMII_CRS;
end
end
endgenerate
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_RX_CLK)
begin
ENET1_GMII_RXD_i <= ENET1_GMII_RXD;
ENET1_GMII_RX_DV_i <= ENET1_GMII_RX_DV;
ENET1_GMII_RX_ER_i <= ENET1_GMII_RX_ER;
end
end
endgenerate
// Trace buffer instantiated when C_INCLUDE_TRACE_BUFFER is 1.
generate
if (C_EN_EMIO_TRACE == 1) begin
if (C_INCLUDE_TRACE_BUFFER == 0) begin : gen_no_trace_buffer
// Pipeline Stage for Traceport ATID
always @(posedge FTMD_TRACEIN_CLK)
begin
FTMD_TRACEIN_DATA_notracebuf <= FTMD_TRACEIN_DATA;
FTMD_TRACEIN_VALID_notracebuf <= FTMD_TRACEIN_VALID;
FTMD_TRACEIN_ATID_notracebuf <= FTMD_TRACEIN_ATID;
end
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_notracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_notracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_notracebuf;
end else begin : gen_trace_buffer
processing_system7_v5_5_trace_buffer #(.FIFO_SIZE (C_TRACE_BUFFER_FIFO_SIZE),
.USE_TRACE_DATA_EDGE_DETECTOR(USE_TRACE_DATA_EDGE_DETECTOR),
.C_DELAY_CLKS(C_TRACE_BUFFER_CLOCK_DELAY)
)
trace_buffer_i (
.TRACE_CLK(FTMD_TRACEIN_CLK),
.RST(~FCLK_RESET0_N),
.TRACE_VALID_IN(FTMD_TRACEIN_VALID),
.TRACE_DATA_IN(FTMD_TRACEIN_DATA),
.TRACE_ATID_IN(FTMD_TRACEIN_ATID),
.TRACE_ATID_OUT(FTMD_TRACEIN_ATID_tracebuf),
.TRACE_VALID_OUT(FTMD_TRACEIN_VALID_tracebuf),
.TRACE_DATA_OUT(FTMD_TRACEIN_DATA_tracebuf)
);
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_tracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_tracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_tracebuf;
end
end
endgenerate
// ID Width Control on AXI Slave ports
// S_AXI_GP0
function [5:0] id_in_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_in;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_in_gp0 = {5'b0, axi_id_gp0_in};
2: id_in_gp0 = {4'b0, axi_id_gp0_in};
3: id_in_gp0 = {3'b0, axi_id_gp0_in};
4: id_in_gp0 = {2'b0, axi_id_gp0_in};
5: id_in_gp0 = {1'b0, axi_id_gp0_in};
6: id_in_gp0 = axi_id_gp0_in;
default : id_in_gp0 = axi_id_gp0_in;
endcase
end
endfunction
assign S_AXI_GP0_ARID_in = id_in_gp0(S_AXI_GP0_ARID);
assign S_AXI_GP0_AWID_in = id_in_gp0(S_AXI_GP0_AWID);
assign S_AXI_GP0_WID_in = id_in_gp0(S_AXI_GP0_WID);
function [5:0] id_out_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_out;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_out_gp0 = axi_id_gp0_out[0];
2: id_out_gp0 = axi_id_gp0_out[1:0];
3: id_out_gp0 = axi_id_gp0_out[2:0];
4: id_out_gp0 = axi_id_gp0_out[3:0];
5: id_out_gp0 = axi_id_gp0_out[4:0];
6: id_out_gp0 = axi_id_gp0_out;
default : id_out_gp0 = axi_id_gp0_out;
endcase
end
endfunction
assign S_AXI_GP0_BID = id_out_gp0(S_AXI_GP0_BID_out);
assign S_AXI_GP0_RID = id_out_gp0(S_AXI_GP0_RID_out);
// S_AXI_GP1
function [5:0] id_in_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_in;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_in_gp1 = {5'b0, axi_id_gp1_in};
2: id_in_gp1 = {4'b0, axi_id_gp1_in};
3: id_in_gp1 = {3'b0, axi_id_gp1_in};
4: id_in_gp1 = {2'b0, axi_id_gp1_in};
5: id_in_gp1 = {1'b0, axi_id_gp1_in};
6: id_in_gp1 = axi_id_gp1_in;
default : id_in_gp1 = axi_id_gp1_in;
endcase
end
endfunction
assign S_AXI_GP1_ARID_in = id_in_gp1(S_AXI_GP1_ARID);
assign S_AXI_GP1_AWID_in = id_in_gp1(S_AXI_GP1_AWID);
assign S_AXI_GP1_WID_in = id_in_gp1(S_AXI_GP1_WID);
function [5:0] id_out_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_out;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_out_gp1 = axi_id_gp1_out[0];
2: id_out_gp1 = axi_id_gp1_out[1:0];
3: id_out_gp1 = axi_id_gp1_out[2:0];
4: id_out_gp1 = axi_id_gp1_out[3:0];
5: id_out_gp1 = axi_id_gp1_out[4:0];
6: id_out_gp1 = axi_id_gp1_out;
default : id_out_gp1 = axi_id_gp1_out;
endcase
end
endfunction
assign S_AXI_GP1_BID = id_out_gp1(S_AXI_GP1_BID_out);
assign S_AXI_GP1_RID = id_out_gp1(S_AXI_GP1_RID_out);
// S_AXI_HP0
function [5:0] id_in_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_in;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_in_hp0 = {5'b0, axi_id_hp0_in};
2: id_in_hp0 = {4'b0, axi_id_hp0_in};
3: id_in_hp0 = {3'b0, axi_id_hp0_in};
4: id_in_hp0 = {2'b0, axi_id_hp0_in};
5: id_in_hp0 = {1'b0, axi_id_hp0_in};
6: id_in_hp0 = axi_id_hp0_in;
default : id_in_hp0 = axi_id_hp0_in;
endcase
end
endfunction
assign S_AXI_HP0_ARID_in = id_in_hp0(S_AXI_HP0_ARID);
assign S_AXI_HP0_AWID_in = id_in_hp0(S_AXI_HP0_AWID);
assign S_AXI_HP0_WID_in = id_in_hp0(S_AXI_HP0_WID);
function [5:0] id_out_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_out;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_out_hp0 = axi_id_hp0_out[0];
2: id_out_hp0 = axi_id_hp0_out[1:0];
3: id_out_hp0 = axi_id_hp0_out[2:0];
4: id_out_hp0 = axi_id_hp0_out[3:0];
5: id_out_hp0 = axi_id_hp0_out[4:0];
6: id_out_hp0 = axi_id_hp0_out;
default : id_out_hp0 = axi_id_hp0_out;
endcase
end
endfunction
assign S_AXI_HP0_BID = id_out_hp0(S_AXI_HP0_BID_out);
assign S_AXI_HP0_RID = id_out_hp0(S_AXI_HP0_RID_out);
assign S_AXI_HP0_WDATA_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WDATA : {32'b0,S_AXI_HP0_WDATA};
assign S_AXI_HP0_WSTRB_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WSTRB : {4'b0,S_AXI_HP0_WSTRB};
assign S_AXI_HP0_RDATA = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_RDATA_out : S_AXI_HP0_RDATA_out[31:0];
// S_AXI_HP1
function [5:0] id_in_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_in;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_in_hp1 = {5'b0, axi_id_hp1_in};
2: id_in_hp1 = {4'b0, axi_id_hp1_in};
3: id_in_hp1 = {3'b0, axi_id_hp1_in};
4: id_in_hp1 = {2'b0, axi_id_hp1_in};
5: id_in_hp1 = {1'b0, axi_id_hp1_in};
6: id_in_hp1 = axi_id_hp1_in;
default : id_in_hp1 = axi_id_hp1_in;
endcase
end
endfunction
assign S_AXI_HP1_ARID_in = id_in_hp1(S_AXI_HP1_ARID);
assign S_AXI_HP1_AWID_in = id_in_hp1(S_AXI_HP1_AWID);
assign S_AXI_HP1_WID_in = id_in_hp1(S_AXI_HP1_WID);
function [5:0] id_out_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_out;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_out_hp1 = axi_id_hp1_out[0];
2: id_out_hp1 = axi_id_hp1_out[1:0];
3: id_out_hp1 = axi_id_hp1_out[2:0];
4: id_out_hp1 = axi_id_hp1_out[3:0];
5: id_out_hp1 = axi_id_hp1_out[4:0];
6: id_out_hp1 = axi_id_hp1_out;
default : id_out_hp1 = axi_id_hp1_out;
endcase
end
endfunction
assign S_AXI_HP1_BID = id_out_hp1(S_AXI_HP1_BID_out);
assign S_AXI_HP1_RID = id_out_hp1(S_AXI_HP1_RID_out);
assign S_AXI_HP1_WDATA_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WDATA : {32'b0,S_AXI_HP1_WDATA};
assign S_AXI_HP1_WSTRB_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WSTRB : {4'b0,S_AXI_HP1_WSTRB};
assign S_AXI_HP1_RDATA = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_RDATA_out : S_AXI_HP1_RDATA_out[31:0];
// S_AXI_HP2
function [5:0] id_in_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_in;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_in_hp2 = {5'b0, axi_id_hp2_in};
2: id_in_hp2 = {4'b0, axi_id_hp2_in};
3: id_in_hp2 = {3'b0, axi_id_hp2_in};
4: id_in_hp2 = {2'b0, axi_id_hp2_in};
5: id_in_hp2 = {1'b0, axi_id_hp2_in};
6: id_in_hp2 = axi_id_hp2_in;
default : id_in_hp2 = axi_id_hp2_in;
endcase
end
endfunction
assign S_AXI_HP2_ARID_in = id_in_hp2(S_AXI_HP2_ARID);
assign S_AXI_HP2_AWID_in = id_in_hp2(S_AXI_HP2_AWID);
assign S_AXI_HP2_WID_in = id_in_hp2(S_AXI_HP2_WID);
function [5:0] id_out_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_out;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_out_hp2 = axi_id_hp2_out[0];
2: id_out_hp2 = axi_id_hp2_out[1:0];
3: id_out_hp2 = axi_id_hp2_out[2:0];
4: id_out_hp2 = axi_id_hp2_out[3:0];
5: id_out_hp2 = axi_id_hp2_out[4:0];
6: id_out_hp2 = axi_id_hp2_out;
default : id_out_hp2 = axi_id_hp2_out;
endcase
end
endfunction
assign S_AXI_HP2_BID = id_out_hp2(S_AXI_HP2_BID_out);
assign S_AXI_HP2_RID = id_out_hp2(S_AXI_HP2_RID_out);
assign S_AXI_HP2_WDATA_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WDATA : {32'b0,S_AXI_HP2_WDATA};
assign S_AXI_HP2_WSTRB_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WSTRB : {4'b0,S_AXI_HP2_WSTRB};
assign S_AXI_HP2_RDATA = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_RDATA_out : S_AXI_HP2_RDATA_out[31:0];
// S_AXI_HP3
function [5:0] id_in_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_in;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_in_hp3 = {5'b0, axi_id_hp3_in};
2: id_in_hp3 = {4'b0, axi_id_hp3_in};
3: id_in_hp3 = {3'b0, axi_id_hp3_in};
4: id_in_hp3 = {2'b0, axi_id_hp3_in};
5: id_in_hp3 = {1'b0, axi_id_hp3_in};
6: id_in_hp3 = axi_id_hp3_in;
default : id_in_hp3 = axi_id_hp3_in;
endcase
end
endfunction
assign S_AXI_HP3_ARID_in = id_in_hp3(S_AXI_HP3_ARID);
assign S_AXI_HP3_AWID_in = id_in_hp3(S_AXI_HP3_AWID);
assign S_AXI_HP3_WID_in = id_in_hp3(S_AXI_HP3_WID);
function [5:0] id_out_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_out;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_out_hp3 = axi_id_hp3_out[0];
2: id_out_hp3 = axi_id_hp3_out[1:0];
3: id_out_hp3 = axi_id_hp3_out[2:0];
4: id_out_hp3 = axi_id_hp3_out[3:0];
5: id_out_hp3 = axi_id_hp3_out[4:0];
6: id_out_hp3 = axi_id_hp3_out;
default : id_out_hp3 = axi_id_hp3_out;
endcase
end
endfunction
assign S_AXI_HP3_BID = id_out_hp3(S_AXI_HP3_BID_out);
assign S_AXI_HP3_RID = id_out_hp3(S_AXI_HP3_RID_out);
assign S_AXI_HP3_WDATA_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WDATA : {32'b0,S_AXI_HP3_WDATA};
assign S_AXI_HP3_WSTRB_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WSTRB : {4'b0,S_AXI_HP3_WSTRB};
assign S_AXI_HP3_RDATA = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_RDATA_out : S_AXI_HP3_RDATA_out[31:0];
// S_AXI_ACP
function [2:0] id_in_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_in;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_in_acp = {2'b0, axi_id_acp_in};
2: id_in_acp = {1'b0, axi_id_acp_in};
3: id_in_acp = axi_id_acp_in;
default : id_in_acp = axi_id_acp_in;
endcase
end
endfunction
assign S_AXI_ACP_ARID_in = id_in_acp(SAXIACPARID_W);
assign S_AXI_ACP_AWID_in = id_in_acp(SAXIACPAWID_W);
assign S_AXI_ACP_WID_in = id_in_acp(SAXIACPWID_W);
function [2:0] id_out_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_out;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_out_acp = axi_id_acp_out[0];
2: id_out_acp = axi_id_acp_out[1:0];
3: id_out_acp = axi_id_acp_out;
default : id_out_acp = axi_id_acp_out;
endcase
end
endfunction
assign SAXIACPBID_W = id_out_acp(S_AXI_ACP_BID_out);
assign SAXIACPRID_W = id_out_acp(S_AXI_ACP_RID_out);
// FMIO Tristate Inversion logic
//FMIO I2C0
assign I2C0_SDA_T = ~ I2C0_SDA_T_n;
assign I2C0_SCL_T = ~ I2C0_SCL_T_n;
//FMIO I2C1
assign I2C1_SDA_T = ~ I2C1_SDA_T_n;
assign I2C1_SCL_T = ~ I2C1_SCL_T_n;
//FMIO SPI0
assign SPI0_SCLK_T = ~ SPI0_SCLK_T_n;
assign SPI0_MOSI_T = ~ SPI0_MOSI_T_n;
assign SPI0_MISO_T = ~ SPI0_MISO_T_n;
assign SPI0_SS_T = ~ SPI0_SS_T_n;
//FMIO SPI1
assign SPI1_SCLK_T = ~ SPI1_SCLK_T_n;
assign SPI1_MOSI_T = ~ SPI1_MOSI_T_n;
assign SPI1_MISO_T = ~ SPI1_MISO_T_n;
assign SPI1_SS_T = ~ SPI1_SS_T_n;
// EMIO GEM0 MDIO
assign ENET0_MDIO_T = ~ ENET0_MDIO_T_n;
// EMIO GEM1 MDIO
assign ENET1_MDIO_T = ~ ENET1_MDIO_T_n;
// EMIO GPIO
assign GPIO_T = ~ GPIO_T_n;
// EMIO GPIO Width Control
function [63:0] gpio_width_adjust_in;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_in;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_in = {63'b0, gpio_in};
2: gpio_width_adjust_in = {62'b0, gpio_in};
3: gpio_width_adjust_in = {61'b0, gpio_in};
4: gpio_width_adjust_in = {60'b0, gpio_in};
5: gpio_width_adjust_in = {59'b0, gpio_in};
6: gpio_width_adjust_in = {58'b0, gpio_in};
7: gpio_width_adjust_in = {57'b0, gpio_in};
8: gpio_width_adjust_in = {56'b0, gpio_in};
9: gpio_width_adjust_in = {55'b0, gpio_in};
10: gpio_width_adjust_in = {54'b0, gpio_in};
11: gpio_width_adjust_in = {53'b0, gpio_in};
12: gpio_width_adjust_in = {52'b0, gpio_in};
13: gpio_width_adjust_in = {51'b0, gpio_in};
14: gpio_width_adjust_in = {50'b0, gpio_in};
15: gpio_width_adjust_in = {49'b0, gpio_in};
16: gpio_width_adjust_in = {48'b0, gpio_in};
17: gpio_width_adjust_in = {47'b0, gpio_in};
18: gpio_width_adjust_in = {46'b0, gpio_in};
19: gpio_width_adjust_in = {45'b0, gpio_in};
20: gpio_width_adjust_in = {44'b0, gpio_in};
21: gpio_width_adjust_in = {43'b0, gpio_in};
22: gpio_width_adjust_in = {42'b0, gpio_in};
23: gpio_width_adjust_in = {41'b0, gpio_in};
24: gpio_width_adjust_in = {40'b0, gpio_in};
25: gpio_width_adjust_in = {39'b0, gpio_in};
26: gpio_width_adjust_in = {38'b0, gpio_in};
27: gpio_width_adjust_in = {37'b0, gpio_in};
28: gpio_width_adjust_in = {36'b0, gpio_in};
29: gpio_width_adjust_in = {35'b0, gpio_in};
30: gpio_width_adjust_in = {34'b0, gpio_in};
31: gpio_width_adjust_in = {33'b0, gpio_in};
32: gpio_width_adjust_in = {32'b0, gpio_in};
33: gpio_width_adjust_in = {31'b0, gpio_in};
34: gpio_width_adjust_in = {30'b0, gpio_in};
35: gpio_width_adjust_in = {29'b0, gpio_in};
36: gpio_width_adjust_in = {28'b0, gpio_in};
37: gpio_width_adjust_in = {27'b0, gpio_in};
38: gpio_width_adjust_in = {26'b0, gpio_in};
39: gpio_width_adjust_in = {25'b0, gpio_in};
40: gpio_width_adjust_in = {24'b0, gpio_in};
41: gpio_width_adjust_in = {23'b0, gpio_in};
42: gpio_width_adjust_in = {22'b0, gpio_in};
43: gpio_width_adjust_in = {21'b0, gpio_in};
44: gpio_width_adjust_in = {20'b0, gpio_in};
45: gpio_width_adjust_in = {19'b0, gpio_in};
46: gpio_width_adjust_in = {18'b0, gpio_in};
47: gpio_width_adjust_in = {17'b0, gpio_in};
48: gpio_width_adjust_in = {16'b0, gpio_in};
49: gpio_width_adjust_in = {15'b0, gpio_in};
50: gpio_width_adjust_in = {14'b0, gpio_in};
51: gpio_width_adjust_in = {13'b0, gpio_in};
52: gpio_width_adjust_in = {12'b0, gpio_in};
53: gpio_width_adjust_in = {11'b0, gpio_in};
54: gpio_width_adjust_in = {10'b0, gpio_in};
55: gpio_width_adjust_in = {9'b0, gpio_in};
56: gpio_width_adjust_in = {8'b0, gpio_in};
57: gpio_width_adjust_in = {7'b0, gpio_in};
58: gpio_width_adjust_in = {6'b0, gpio_in};
59: gpio_width_adjust_in = {5'b0, gpio_in};
60: gpio_width_adjust_in = {4'b0, gpio_in};
61: gpio_width_adjust_in = {3'b0, gpio_in};
62: gpio_width_adjust_in = {2'b0, gpio_in};
63: gpio_width_adjust_in = {1'b0, gpio_in};
64: gpio_width_adjust_in = gpio_in;
default : gpio_width_adjust_in = gpio_in;
endcase
end
endfunction
assign gpio_in63_0 = gpio_width_adjust_in(GPIO_I);
function [63:0] gpio_width_adjust_out;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_o;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_out = gpio_o[0];
2: gpio_width_adjust_out = gpio_o[1:0];
3: gpio_width_adjust_out = gpio_o[2:0];
4: gpio_width_adjust_out = gpio_o[3:0];
5: gpio_width_adjust_out = gpio_o[4:0];
6: gpio_width_adjust_out = gpio_o[5:0];
7: gpio_width_adjust_out = gpio_o[6:0];
8: gpio_width_adjust_out = gpio_o[7:0];
9: gpio_width_adjust_out = gpio_o[8:0];
10: gpio_width_adjust_out = gpio_o[9:0];
11: gpio_width_adjust_out = gpio_o[10:0];
12: gpio_width_adjust_out = gpio_o[11:0];
13: gpio_width_adjust_out = gpio_o[12:0];
14: gpio_width_adjust_out = gpio_o[13:0];
15: gpio_width_adjust_out = gpio_o[14:0];
16: gpio_width_adjust_out = gpio_o[15:0];
17: gpio_width_adjust_out = gpio_o[16:0];
18: gpio_width_adjust_out = gpio_o[17:0];
19: gpio_width_adjust_out = gpio_o[18:0];
20: gpio_width_adjust_out = gpio_o[19:0];
21: gpio_width_adjust_out = gpio_o[20:0];
22: gpio_width_adjust_out = gpio_o[21:0];
23: gpio_width_adjust_out = gpio_o[22:0];
24: gpio_width_adjust_out = gpio_o[23:0];
25: gpio_width_adjust_out = gpio_o[24:0];
26: gpio_width_adjust_out = gpio_o[25:0];
27: gpio_width_adjust_out = gpio_o[26:0];
28: gpio_width_adjust_out = gpio_o[27:0];
29: gpio_width_adjust_out = gpio_o[28:0];
30: gpio_width_adjust_out = gpio_o[29:0];
31: gpio_width_adjust_out = gpio_o[30:0];
32: gpio_width_adjust_out = gpio_o[31:0];
33: gpio_width_adjust_out = gpio_o[32:0];
34: gpio_width_adjust_out = gpio_o[33:0];
35: gpio_width_adjust_out = gpio_o[34:0];
36: gpio_width_adjust_out = gpio_o[35:0];
37: gpio_width_adjust_out = gpio_o[36:0];
38: gpio_width_adjust_out = gpio_o[37:0];
39: gpio_width_adjust_out = gpio_o[38:0];
40: gpio_width_adjust_out = gpio_o[39:0];
41: gpio_width_adjust_out = gpio_o[40:0];
42: gpio_width_adjust_out = gpio_o[41:0];
43: gpio_width_adjust_out = gpio_o[42:0];
44: gpio_width_adjust_out = gpio_o[43:0];
45: gpio_width_adjust_out = gpio_o[44:0];
46: gpio_width_adjust_out = gpio_o[45:0];
47: gpio_width_adjust_out = gpio_o[46:0];
48: gpio_width_adjust_out = gpio_o[47:0];
49: gpio_width_adjust_out = gpio_o[48:0];
50: gpio_width_adjust_out = gpio_o[49:0];
51: gpio_width_adjust_out = gpio_o[50:0];
52: gpio_width_adjust_out = gpio_o[51:0];
53: gpio_width_adjust_out = gpio_o[52:0];
54: gpio_width_adjust_out = gpio_o[53:0];
55: gpio_width_adjust_out = gpio_o[54:0];
56: gpio_width_adjust_out = gpio_o[55:0];
57: gpio_width_adjust_out = gpio_o[56:0];
58: gpio_width_adjust_out = gpio_o[57:0];
59: gpio_width_adjust_out = gpio_o[58:0];
60: gpio_width_adjust_out = gpio_o[59:0];
61: gpio_width_adjust_out = gpio_o[60:0];
62: gpio_width_adjust_out = gpio_o[61:0];
63: gpio_width_adjust_out = gpio_o[62:0];
64: gpio_width_adjust_out = gpio_o;
default : gpio_width_adjust_out = gpio_o;
endcase
end
endfunction
assign GPIO_O[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out);
assign GPIO_T_n[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out_t_n);
// Adding OBUFT to JTAG out port
generate
if ( C_EN_EMIO_PJTAG == 1 ) begin : PJTAG_OBUFT_TRUE
OBUFT jtag_obuft_inst (
.O(PJTAG_TDO),
.I(PJTAG_TDO_O),
.T(PJTAG_TDO_T)
);
end
endgenerate
// -------
// EMIO PJTAG
assign PJTAG_TDO_T = ~ PJTAG_TDO_T_n;
// EMIO SDIO0 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO0_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO0_CMD_T_n) : (~ SDIO0_CMD_T_n);
assign SDIO0_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO0_DATA_T_n[3:0]) : (~ SDIO0_DATA_T_n[3:0]);
// EMIO SDIO1 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO1_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO1_CMD_T_n) : (~ SDIO1_CMD_T_n);
assign SDIO1_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO1_DATA_T_n[3:0]) : (~ SDIO1_DATA_T_n[3:0]);
// FCLK_CLK optional clock buffers
generate
if (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") begin : buffer_fclk_clk_0
BUFG FCLK_CLK_0_BUFG (.I(FCLK_CLK_unbuffered[0]), .O(FCLK_CLK_buffered[0]));
end
if (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") begin : buffer_fclk_clk_1
BUFG FCLK_CLK_1_BUFG (.I(FCLK_CLK_unbuffered[1]), .O(FCLK_CLK_buffered[1]));
end
if (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") begin : buffer_fclk_clk_2
BUFG FCLK_CLK_2_BUFG (.I(FCLK_CLK_unbuffered[2]), .O(FCLK_CLK_buffered[2]));
end
if (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") begin : buffer_fclk_clk_3
BUFG FCLK_CLK_3_BUFG (.I(FCLK_CLK_unbuffered[3]), .O(FCLK_CLK_buffered[3]));
end
endgenerate
assign FCLK_CLK0 = (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") ? FCLK_CLK_buffered[0] : FCLK_CLK_unbuffered[0];
assign FCLK_CLK1 = (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") ? FCLK_CLK_buffered[1] : FCLK_CLK_unbuffered[1];
assign FCLK_CLK2 = (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") ? FCLK_CLK_buffered[2] : FCLK_CLK_unbuffered[2];
assign FCLK_CLK3 = (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") ? FCLK_CLK_buffered[3] : FCLK_CLK_unbuffered[3];
// Adding BIBUF for fixed IO Ports and IBUF for fixed Input Ports
BIBUF DDR_CAS_n_BIBUF (.PAD(DDR_CAS_n), .IO(buffered_DDR_CAS_n));
BIBUF DDR_CKE_BIBUF (.PAD(DDR_CKE), .IO(buffered_DDR_CKE));
BIBUF DDR_Clk_n_BIBUF (.PAD(DDR_Clk_n), .IO(buffered_DDR_Clk_n));
BIBUF DDR_Clk_BIBUF (.PAD(DDR_Clk), .IO(buffered_DDR_Clk));
BIBUF DDR_CS_n_BIBUF (.PAD(DDR_CS_n), .IO(buffered_DDR_CS_n));
BIBUF DDR_DRSTB_BIBUF (.PAD(DDR_DRSTB), .IO(buffered_DDR_DRSTB));
BIBUF DDR_ODT_BIBUF (.PAD(DDR_ODT), .IO(buffered_DDR_ODT));
BIBUF DDR_RAS_n_BIBUF (.PAD(DDR_RAS_n), .IO(buffered_DDR_RAS_n));
BIBUF DDR_WEB_BIBUF (.PAD(DDR_WEB), .IO(buffered_DDR_WEB));
BIBUF DDR_VRN_BIBUF (.PAD(DDR_VRN), .IO(buffered_DDR_VRN));
BIBUF DDR_VRP_BIBUF (.PAD(DDR_VRP), .IO(buffered_DDR_VRP));
BIBUF PS_SRSTB_BIBUF (.PAD(PS_SRSTB), .IO(buffered_PS_SRSTB));
BIBUF PS_CLK_BIBUF (.PAD(PS_CLK), .IO(buffered_PS_CLK));
BIBUF PS_PORB_BIBUF (.PAD(PS_PORB), .IO(buffered_PS_PORB));
genvar i;
generate
for (i=0; i < C_MIO_PRIMITIVE; i=i+1) begin
BIBUF MIO_BIBUF (.PAD(MIO[i]), .IO(buffered_MIO[i]));
end
endgenerate
generate
for (i=0; i < 3; i=i+1) begin
BIBUF DDR_BankAddr_BIBUF (.PAD(DDR_BankAddr[i]), .IO(buffered_DDR_BankAddr[i]));
end
endgenerate
generate
for (i=0; i < 15; i=i+1) begin
BIBUF DDR_Addr_BIBUF (.PAD(DDR_Addr[i]), .IO(buffered_DDR_Addr[i]));
end
endgenerate
generate
for (i=0; i < C_DM_WIDTH; i=i+1) begin
BIBUF DDR_DM_BIBUF (.PAD(DDR_DM[i]), .IO(buffered_DDR_DM[i]));
end
endgenerate
generate
for (i=0; i < C_DQ_WIDTH; i=i+1) begin
BIBUF DDR_DQ_BIBUF (.PAD(DDR_DQ[i]), .IO(buffered_DDR_DQ[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_n_BIBUF (.PAD(DDR_DQS_n[i]), .IO(buffered_DDR_DQS_n[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_BIBUF (.PAD(DDR_DQS[i]), .IO(buffered_DDR_DQS[i]));
end
endgenerate
//====================
//PSS TOP
//====================
generate
if (C_PACKAGE_NAME == "clg225" ) begin
wire [21:0] dummy;
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O ),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK ),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO ({buffered_MIO[31:30],dummy[21:20],buffered_MIO[29:28],dummy[19:12],buffered_MIO[27:16],dummy[11:0],buffered_MIO[15:0]}),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
else begin
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O ),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK ),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO (buffered_MIO),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
endgenerate
// Generating the AxUSER Values locally when the C_USE_DEFAULT_ACP_USER_VAL is enabled.
// Otherwise a master connected to the ACP port will drive the AxUSER Ports
assign param_aruser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_ARUSER_VAL : S_AXI_ACP_ARUSER;
assign param_awuser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_AWUSER_VAL : S_AXI_ACP_AWUSER;
assign SAXIACPARADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARADDR : S_AXI_ACP_ARADDR;
assign SAXIACPARBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARBURST : S_AXI_ACP_ARBURST;
assign SAXIACPARCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARCACHE : S_AXI_ACP_ARCACHE;
assign SAXIACPARLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLEN : S_AXI_ACP_ARLEN;
assign SAXIACPARLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLOCK : S_AXI_ACP_ARLOCK;
assign SAXIACPARPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARPROT : S_AXI_ACP_ARPROT;
assign SAXIACPARSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARSIZE : S_AXI_ACP_ARSIZE;
//assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : S_AXI_ACP_ARUSER;
assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : param_aruser;
assign SAXIACPARVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARVALID : S_AXI_ACP_ARVALID ;
assign SAXIACPAWADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWADDR : S_AXI_ACP_AWADDR;
assign SAXIACPAWBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWBURST : S_AXI_ACP_AWBURST;
assign SAXIACPAWCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWCACHE : S_AXI_ACP_AWCACHE;
assign SAXIACPAWLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLEN : S_AXI_ACP_AWLEN;
assign SAXIACPAWLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLOCK : S_AXI_ACP_AWLOCK;
assign SAXIACPAWPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWPROT : S_AXI_ACP_AWPROT;
assign SAXIACPAWSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWSIZE : S_AXI_ACP_AWSIZE;
//assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : S_AXI_ACP_AWUSER;
assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : param_awuser;
assign SAXIACPAWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWVALID : S_AXI_ACP_AWVALID;
assign SAXIACPBREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_BREADY : S_AXI_ACP_BREADY;
assign SAXIACPRREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_RREADY : S_AXI_ACP_RREADY;
assign SAXIACPWDATA_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WDATA : S_AXI_ACP_WDATA;
assign SAXIACPWLAST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WLAST : S_AXI_ACP_WLAST;
assign SAXIACPWSTRB_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WSTRB : S_AXI_ACP_WSTRB;
assign SAXIACPWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WVALID : S_AXI_ACP_WVALID;
assign SAXIACPARID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARID : S_AXI_ACP_ARID;
assign SAXIACPAWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWID : S_AXI_ACP_AWID;
assign SAXIACPWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WID : S_AXI_ACP_WID;
generate
if (C_INCLUDE_ACP_TRANS_CHECK == 0) begin : gen_no_atc
assign S_AXI_ACP_AWREADY = SAXIACPAWREADY_W;
assign S_AXI_ACP_WREADY = SAXIACPWREADY_W;
assign S_AXI_ACP_BID = SAXIACPBID_W;
assign S_AXI_ACP_BRESP = SAXIACPBRESP_W;
assign S_AXI_ACP_BVALID = SAXIACPBVALID_W;
assign S_AXI_ACP_RDATA = SAXIACPRDATA_W;
assign S_AXI_ACP_RID = SAXIACPRID_W;
assign S_AXI_ACP_RLAST = SAXIACPRLAST_W;
assign S_AXI_ACP_RRESP = SAXIACPRRESP_W;
assign S_AXI_ACP_RVALID = SAXIACPRVALID_W;
assign S_AXI_ACP_ARREADY = SAXIACPARREADY_W;
end else begin : gen_atc
processing_system7_v5_5_atc #(
.C_AXI_ID_WIDTH (C_S_AXI_ACP_ID_WIDTH),
.C_AXI_AWUSER_WIDTH (5),
.C_AXI_ARUSER_WIDTH (5)
)
atc_i (
// Global Signals
.ACLK (S_AXI_ACP_ACLK),
.ARESETN (S_AXI_ACP_ARESETN),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_ACP_AWID),
.S_AXI_AWADDR (S_AXI_ACP_AWADDR),
.S_AXI_AWLEN (S_AXI_ACP_AWLEN),
.S_AXI_AWSIZE (S_AXI_ACP_AWSIZE),
.S_AXI_AWBURST (S_AXI_ACP_AWBURST),
.S_AXI_AWLOCK (S_AXI_ACP_AWLOCK),
.S_AXI_AWCACHE (S_AXI_ACP_AWCACHE),
.S_AXI_AWPROT (S_AXI_ACP_AWPROT),
//.S_AXI_AWUSER (S_AXI_ACP_AWUSER),
.S_AXI_AWUSER (param_awuser),
.S_AXI_AWVALID (S_AXI_ACP_AWVALID),
.S_AXI_AWREADY (S_AXI_ACP_AWREADY),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_ACP_WID),
.S_AXI_WDATA (S_AXI_ACP_WDATA),
.S_AXI_WSTRB (S_AXI_ACP_WSTRB),
.S_AXI_WLAST (S_AXI_ACP_WLAST),
.S_AXI_WUSER (),
.S_AXI_WVALID (S_AXI_ACP_WVALID),
.S_AXI_WREADY (S_AXI_ACP_WREADY),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_ACP_BID),
.S_AXI_BRESP (S_AXI_ACP_BRESP),
.S_AXI_BUSER (),
.S_AXI_BVALID (S_AXI_ACP_BVALID),
.S_AXI_BREADY (S_AXI_ACP_BREADY),
// Slave Interface Read Address Ports
.S_AXI_ARID (S_AXI_ACP_ARID),
.S_AXI_ARADDR (S_AXI_ACP_ARADDR),
.S_AXI_ARLEN (S_AXI_ACP_ARLEN),
.S_AXI_ARSIZE (S_AXI_ACP_ARSIZE),
.S_AXI_ARBURST (S_AXI_ACP_ARBURST),
.S_AXI_ARLOCK (S_AXI_ACP_ARLOCK),
.S_AXI_ARCACHE (S_AXI_ACP_ARCACHE),
.S_AXI_ARPROT (S_AXI_ACP_ARPROT),
//.S_AXI_ARUSER (S_AXI_ACP_ARUSER),
.S_AXI_ARUSER (param_aruser),
.S_AXI_ARVALID (S_AXI_ACP_ARVALID),
.S_AXI_ARREADY (S_AXI_ACP_ARREADY),
// Slave Interface Read Data Ports
.S_AXI_RID (S_AXI_ACP_RID),
.S_AXI_RDATA (S_AXI_ACP_RDATA),
.S_AXI_RRESP (S_AXI_ACP_RRESP),
.S_AXI_RLAST (S_AXI_ACP_RLAST),
.S_AXI_RUSER (),
.S_AXI_RVALID (S_AXI_ACP_RVALID),
.S_AXI_RREADY (S_AXI_ACP_RREADY),
// Slave Interface Write Address Ports
.M_AXI_AWID (S_AXI_ATC_AWID),
.M_AXI_AWADDR (S_AXI_ATC_AWADDR),
.M_AXI_AWLEN (S_AXI_ATC_AWLEN),
.M_AXI_AWSIZE (S_AXI_ATC_AWSIZE),
.M_AXI_AWBURST (S_AXI_ATC_AWBURST),
.M_AXI_AWLOCK (S_AXI_ATC_AWLOCK),
.M_AXI_AWCACHE (S_AXI_ATC_AWCACHE),
.M_AXI_AWPROT (S_AXI_ATC_AWPROT),
.M_AXI_AWUSER (S_AXI_ATC_AWUSER),
.M_AXI_AWVALID (S_AXI_ATC_AWVALID),
.M_AXI_AWREADY (SAXIACPAWREADY_W),
// Slave Interface Write Data Ports
.M_AXI_WID (S_AXI_ATC_WID),
.M_AXI_WDATA (S_AXI_ATC_WDATA),
.M_AXI_WSTRB (S_AXI_ATC_WSTRB),
.M_AXI_WLAST (S_AXI_ATC_WLAST),
.M_AXI_WUSER (),
.M_AXI_WVALID (S_AXI_ATC_WVALID),
.M_AXI_WREADY (SAXIACPWREADY_W),
// Slave Interface Write Response Ports
.M_AXI_BID (SAXIACPBID_W),
.M_AXI_BRESP (SAXIACPBRESP_W),
.M_AXI_BUSER (),
.M_AXI_BVALID (SAXIACPBVALID_W),
.M_AXI_BREADY (S_AXI_ATC_BREADY),
// Slave Interface Read Address Ports
.M_AXI_ARID (S_AXI_ATC_ARID),
.M_AXI_ARADDR (S_AXI_ATC_ARADDR),
.M_AXI_ARLEN (S_AXI_ATC_ARLEN),
.M_AXI_ARSIZE (S_AXI_ATC_ARSIZE),
.M_AXI_ARBURST (S_AXI_ATC_ARBURST),
.M_AXI_ARLOCK (S_AXI_ATC_ARLOCK),
.M_AXI_ARCACHE (S_AXI_ATC_ARCACHE),
.M_AXI_ARPROT (S_AXI_ATC_ARPROT),
.M_AXI_ARUSER (S_AXI_ATC_ARUSER),
.M_AXI_ARVALID (S_AXI_ATC_ARVALID),
.M_AXI_ARREADY (SAXIACPARREADY_W),
// Slave Interface Read Data Ports
.M_AXI_RID (SAXIACPRID_W),
.M_AXI_RDATA (SAXIACPRDATA_W),
.M_AXI_RRESP (SAXIACPRRESP_W),
.M_AXI_RLAST (SAXIACPRLAST_W),
.M_AXI_RUSER (),
.M_AXI_RVALID (SAXIACPRVALID_W),
.M_AXI_RREADY (S_AXI_ATC_RREADY),
.ERROR_TRIGGER(),
.ERROR_TRANSACTION_ID()
);
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFSBP_1_V
`define SKY130_FD_SC_LS__SDFSBP_1_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for sdfsbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__sdfsbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfsbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfsbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFSBP_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_P_PP_PG_N_TB_V
`define SKY130_FD_SC_HS__UDP_DFF_P_PP_PG_N_TB_V
/**
* udp_dff$P_pp$PG$N: Positive edge triggered D flip-flop
* (Q output UDP).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__udp_dff_p_pp_pg_n.v"
module top();
// Inputs are registered
reg D;
reg NOTIFIER;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
NOTIFIER = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 NOTIFIER = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 D = 1'b1;
#120 NOTIFIER = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 D = 1'b0;
#200 NOTIFIER = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 NOTIFIER = 1'b1;
#320 D = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 NOTIFIER = 1'bx;
#400 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__udp_dff$P_pp$PG$N dut (.D(D), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_P_PP_PG_N_TB_V
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
// Date : Fri May 27 23:50:21 2016
// Host : Dries007-Arch running 64-bit unknown
// Command : write_verilog -force -mode funcsim
// /home/dries/Projects/Basys3/FPGA-Z/FPGA-Z.srcs/sources_1/ip/ClockDivider/ClockDivider_sim_netlist.v
// Design : ClockDivider
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CORE_GENERATION_INFO = "ClockDivider,clk_wiz_v5_2_1,{component_name=ClockDivider,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=4,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
(* NotValidForBitStream *)
module ClockDivider
(clkIn,
clk108M,
clk_cpu,
clk2cpu,
clk6cpu);
input clkIn;
output clk108M;
output clk_cpu;
output clk2cpu;
output clk6cpu;
wire clk108M;
wire clk2cpu;
wire clk6cpu;
(* IBUF_LOW_PWR *) wire clkIn;
wire clk_cpu;
ClockDivider_ClockDivider_clk_wiz inst
(.clk108M(clk108M),
.clk2cpu(clk2cpu),
.clk6cpu(clk6cpu),
.clkIn(clkIn),
.clk_cpu(clk_cpu));
endmodule
(* ORIG_REF_NAME = "ClockDivider_clk_wiz" *)
module ClockDivider_ClockDivider_clk_wiz
(clkIn,
clk108M,
clk_cpu,
clk2cpu,
clk6cpu);
input clkIn;
output clk108M;
output clk_cpu;
output clk2cpu;
output clk6cpu;
wire clk108M;
wire clk108M_ClockDivider;
wire clk2cpu;
wire clk2cpu_ClockDivider;
wire clk6cpu;
wire clk6cpu_ClockDivider;
wire clkIn;
wire clkIn_ClockDivider;
wire clk_cpu;
wire clk_cpu_ClockDivider;
wire clkfbout_ClockDivider;
wire clkfbout_buf_ClockDivider;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_LOCKED_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_ClockDivider),
.O(clkfbout_buf_ClockDivider));
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clkIn),
.O(clkIn_ClockDivider));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk108M_ClockDivider),
.O(clk108M));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout2_buf
(.I(clk_cpu_ClockDivider),
.O(clk_cpu));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout3_buf
(.I(clk2cpu_ClockDivider),
.O(clk2cpu));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout4_buf
(.I(clk6cpu_ClockDivider),
.O(clk6cpu));
(* BOX_TYPE = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(54.000000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(10.000000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(72),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(36),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(12),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(5),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_ClockDivider),
.CLKFBOUT(clkfbout_ClockDivider),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clkIn_ClockDivider),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk108M_ClockDivider),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(clk_cpu_ClockDivider),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(clk2cpu_ClockDivider),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(clk6cpu_ClockDivider),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(NLW_mmcm_adv_inst_LOCKED_UNCONNECTED),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
module irq(
input WR_ACK,
input [2:0] ACK_BITS,
input RESET_IRQ,
input TIMER_IRQ,
input VBL_IRQ,
input CLK,
output IPL0, IPL1
);
wire [2:0] ACK;
wire [3:0] B32_Q;
assign nWR_ACK = ~WR_ACK;
assign ACK[0] = ~&{nWR_ACK, ACK_BITS[0]};
assign ACK[1] = ~&{nWR_ACK, ACK_BITS[1]};
assign ACK[2] = ~&{nWR_ACK, ACK_BITS[2]};
FD3 B56(RESET_IRQ, 1'b0, ACK[0], B56_Q, B56_nQ);
FD3 B52(TIMER_IRQ, 1'b0, ACK[1], B52_Q, B52_nQ);
FD3 C52(VBL_IRQ, 1'b0, ACK[2], C52_Q, );
// B49
assign B49_OUT = B52_Q | B56_nQ;
// B50A
assign B50A_OUT = ~|{C52_Q, B56_nQ, B52_nQ};
FDSCell B32(CLK, {1'b0, B50A_OUT, B49_OUT, B56_Q}, B32_Q);
assign IPL0 = ~|{~B32_Q[0], B32_Q[2]};
assign IPL1 = ~|{~B32_Q[1], ~B32_Q[0]};
// Interrupt priority encoder (is priority right ?)
// IRQ IPL
// xx1: 000 Reset IRQ
// x10: 001 Timer IRQ
// 100: 010 VBL IRQ
// 000: 011 No interrupt
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:11:08 08/25/2014
// Design Name:
// Module Name: conled
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module conled(
input clk,
output led0,
output led1,
output led2,
output led3,
output led4,
output led5
);
reg [25:0] counter;
reg [5:0] ledout;
//assign {led0,led1,led2,led3,led4,led5}=ledout;
assign {led0,led1,led2,led3,led4,led5}=6'b111111;
//generate 0,25,50,75, and 100% duty cycle signals
assign duty0=0;
assign duty1=counter[15]&counter[16]&counter[17];
assign duty2=counter[15]&counter[16];
assign duty3=counter[15];
assign duty4=1;
always @(posedge clk)
begin
//increment counter
counter<=counter+1;
//use high 3 bits as state, translate duty cycle accordingly
case (counter[25:23])
3'b000:ledout={duty0,duty4,duty3,duty2,duty1,duty0};
3'b001:ledout={duty4,duty3,duty2,duty1,duty0,duty0};
3'b010:ledout={duty3,duty2,duty1,duty0,duty0,duty0};
3'b011:ledout={duty2,duty1,duty0,duty0,duty0,duty0};
3'b100:ledout={duty1,duty0,duty0,duty0,duty0,duty4};
3'b101:ledout={duty0,duty0,duty0,duty0,duty4,duty3};
3'b110:ledout={duty0,duty0,duty0,duty4,duty3,duty2};
default:ledout={duty0,duty0,duty4,duty3,duty2,duty1};
// 3'b000:ledout={duty0,duty1,duty2,duty3,duty4,duty3};
// 3'b001:ledout={duty1,duty2,duty3,duty4,duty3,duty2};
// 3'b010:ledout={duty2,duty3,duty4,duty3,duty2,duty1};
// 3'b011:ledout={duty3,duty4,duty3,duty2,duty1,duty0};
// 3'b100:ledout={duty4,duty3,duty2,duty1,duty0,duty1};
// 3'b101:ledout={duty3,duty2,duty1,duty0,duty1,duty2};
// 3'b110:ledout={duty2,duty1,duty0,duty1,duty2,duty3};
// default:ledout={duty1,duty0,duty1,duty2,duty3,duty4};
endcase
end
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module control_status_slave_which_resides_within_amm_master_qsys_with_pcie_sgdma (
// inputs:
atlantic_error,
chain_run,
clk,
command_fifo_empty,
csr_address,
csr_chipselect,
csr_read,
csr_write,
csr_writedata,
desc_address_fifo_empty,
descriptor_read_address,
descriptor_read_read,
descriptor_write_busy,
descriptor_write_write,
owned_by_hw,
read_go,
reset_n,
status_token_fifo_empty,
status_token_fifo_rdreq,
write_go,
// outputs:
csr_irq,
csr_readdata,
descriptor_pointer_lower_reg_out,
descriptor_pointer_upper_reg_out,
park,
pollen_clear_run,
run,
sw_reset
)
;
output csr_irq;
output [ 31: 0] csr_readdata;
output [ 31: 0] descriptor_pointer_lower_reg_out;
output [ 31: 0] descriptor_pointer_upper_reg_out;
output park;
output pollen_clear_run;
output run;
output sw_reset;
input atlantic_error;
input chain_run;
input clk;
input command_fifo_empty;
input [ 3: 0] csr_address;
input csr_chipselect;
input csr_read;
input csr_write;
input [ 31: 0] csr_writedata;
input desc_address_fifo_empty;
input [ 31: 0] descriptor_read_address;
input descriptor_read_read;
input descriptor_write_busy;
input descriptor_write_write;
input owned_by_hw;
input read_go;
input reset_n;
input status_token_fifo_empty;
input status_token_fifo_rdreq;
input write_go;
reg busy;
reg can_have_new_chain_complete;
reg chain_completed;
reg chain_completed_int;
wire chain_completed_int_rise;
wire clear_chain_completed;
wire clear_descriptor_completed;
wire clear_error;
reg clear_interrupt;
wire clear_run;
reg [ 31: 0] control_reg;
wire control_reg_en;
wire csr_control;
reg csr_irq;
reg [ 31: 0] csr_readdata;
wire csr_status;
reg delayed_chain_completed_int;
reg delayed_csr_write;
reg [ 7: 0] delayed_descriptor_counter;
reg delayed_descriptor_write_write;
reg delayed_eop_encountered;
wire [ 7: 0] delayed_max_desc_processed;
reg delayed_run;
reg descriptor_completed;
reg [ 7: 0] descriptor_counter;
wire [ 31: 0] descriptor_pointer_data;
reg [ 31: 0] descriptor_pointer_lower_reg;
wire descriptor_pointer_lower_reg_en;
wire [ 31: 0] descriptor_pointer_lower_reg_out;
reg [ 31: 0] descriptor_pointer_upper_reg;
wire descriptor_pointer_upper_reg_en;
wire [ 31: 0] descriptor_pointer_upper_reg_out;
reg descriptor_read_read_r;
wire descriptor_read_read_rising;
wire descriptor_write_write_fall;
reg do_restart;
reg do_restart_compare;
wire eop_encountered;
wire eop_encountered_rise;
reg error;
wire [ 3: 0] hw_version;
wire ie_chain_completed;
wire ie_descriptor_completed;
wire ie_eop_encountered;
wire ie_error;
wire ie_global;
wire ie_max_desc_processed;
wire [ 7: 0] max_desc_processed;
wire park;
wire poll_en;
wire pollen_clear_run;
wire run;
wire [ 31: 0] status_reg;
wire stop_dma_error;
wire sw_reset;
reg [ 15: 0] timeout_counter;
wire [ 10: 0] timeout_reg;
wire version_reg;
//csr, which is an e_avalon_slave
//Control Status Register (Readdata)
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
csr_readdata <= 0;
else if (csr_read)
case (csr_address) // synthesis parallel_case
{4'b0000}: begin
csr_readdata <= status_reg;
end // {4'b0000}
{4'b0001}: begin
csr_readdata <= version_reg;
end // {4'b0001}
{4'b0100}: begin
csr_readdata <= control_reg;
end // {4'b0100}
{4'b1000}: begin
csr_readdata <= descriptor_pointer_lower_reg;
end // {4'b1000}
{4'b1100}: begin
csr_readdata <= descriptor_pointer_upper_reg;
end // {4'b1100}
default: begin
csr_readdata <= 32'b0;
end // default
endcase // csr_address
end
//register outs
assign descriptor_pointer_upper_reg_out = descriptor_pointer_upper_reg;
assign descriptor_pointer_lower_reg_out = descriptor_pointer_lower_reg;
//control register bits
assign ie_error = control_reg[0];
assign ie_eop_encountered = control_reg[1];
assign ie_descriptor_completed = control_reg[2];
assign ie_chain_completed = control_reg[3];
assign ie_global = control_reg[4];
assign run = control_reg[5] && (!(stop_dma_error && error) && ((!chain_completed_int ) ||( do_restart && poll_en && chain_completed_int)));
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_run <= 0;
else
delayed_run <= run;
end
assign stop_dma_error = control_reg[6];
assign ie_max_desc_processed = control_reg[7];
assign max_desc_processed = control_reg[15 : 8];
assign sw_reset = control_reg[16];
assign park = control_reg[17];
assign poll_en = control_reg[18];
assign timeout_reg = control_reg[30 : 20];
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
timeout_counter <= 0;
else if ((control_reg[5] && !busy && poll_en )|| do_restart)
timeout_counter <= do_restart ? 0:(timeout_counter + 1'b1);
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
do_restart_compare <= 0;
else
do_restart_compare <= timeout_counter == {timeout_reg,5'b11111};
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
do_restart <= 0;
else
do_restart <= poll_en && do_restart_compare;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
clear_interrupt <= 0;
else
clear_interrupt <= control_reg_en ? csr_writedata[31] : 0;
end
//control register
assign control_reg_en = (csr_address == { 4'b0100}) && csr_write && csr_chipselect;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
control_reg <= 0;
else if (control_reg_en)
control_reg <= {1'b0, csr_writedata[30 : 0]};
end
//descriptor_pointer_upper_reg
assign descriptor_pointer_upper_reg_en = (csr_address == { 4'b1100}) && csr_write && csr_chipselect;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
descriptor_pointer_upper_reg <= 0;
else if (descriptor_pointer_upper_reg_en)
descriptor_pointer_upper_reg <= csr_writedata;
end
//section to update the descriptor pointer
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
descriptor_read_read_r <= 0;
else
descriptor_read_read_r <= descriptor_read_read;
end
assign descriptor_read_read_rising = descriptor_read_read && !descriptor_read_read_r;
assign descriptor_pointer_data = descriptor_read_read_rising ? descriptor_read_address:csr_writedata;
//descriptor_pointer_lower_reg
assign descriptor_pointer_lower_reg_en = ((csr_address == { 4'b1000}) && csr_write && csr_chipselect) || (poll_en && descriptor_read_read_rising);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
descriptor_pointer_lower_reg <= 0;
else if (descriptor_pointer_lower_reg_en)
descriptor_pointer_lower_reg <= descriptor_pointer_data;
end
//Hardware Version Register
assign hw_version = 4'b0001;
assign version_reg = {24'h000000, hw_version};
//status register
assign status_reg = {27'b0, busy, chain_completed, descriptor_completed, eop_encountered, error};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
busy <= 0;
else
busy <= ~command_fifo_empty || ~status_token_fifo_empty || ~desc_address_fifo_empty || chain_run || descriptor_write_busy || delayed_csr_write || owned_by_hw || write_go || read_go;
end
//Chain Completed Status Register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
chain_completed <= 0;
else if ((run && ~owned_by_hw && ~busy) || clear_chain_completed || do_restart)
chain_completed <= (clear_chain_completed || do_restart)? 1'b0 : ~delayed_csr_write;
end
//chain_completed_int is the internal chain completed state for SGDMA.
//Will not be affected with clearing of chain_completed Status Register,to prevent SGDMA being restarted when the status bit is cleared
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
chain_completed_int <= 0;
else if ((run && ~owned_by_hw && ~busy) || clear_run || do_restart)
chain_completed_int <= (clear_run || do_restart) ? 1'b0 : ~delayed_csr_write;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_csr_write <= 0;
else
delayed_csr_write <= csr_write;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
descriptor_completed <= 0;
else if (descriptor_write_write_fall || clear_descriptor_completed)
descriptor_completed <= ~clear_descriptor_completed;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
error <= 0;
else if (atlantic_error || clear_error)
error <= ~clear_error;
end
assign csr_status = csr_write && csr_chipselect && (csr_address == 4'b0);
assign clear_chain_completed = csr_writedata[3] && csr_status;
assign clear_descriptor_completed = csr_writedata[2] && csr_status;
assign clear_error = csr_writedata[0] && csr_status;
assign csr_control = csr_write && csr_chipselect && (csr_address == 4'h4);
assign clear_run = !csr_writedata[5] && csr_control;
assign pollen_clear_run = poll_en & clear_run;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_eop_encountered <= 0;
else
delayed_eop_encountered <= eop_encountered;
end
assign eop_encountered_rise = ~delayed_eop_encountered && eop_encountered;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_descriptor_write_write <= 0;
else
delayed_descriptor_write_write <= descriptor_write_write;
end
assign descriptor_write_write_fall = delayed_descriptor_write_write && ~descriptor_write_write;
assign eop_encountered = 1'b0;
//chain_completed rising edge detector
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_chain_completed_int <= 0;
else
delayed_chain_completed_int <= chain_completed_int;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
can_have_new_chain_complete <= 0;
else if (descriptor_write_write || (~delayed_chain_completed_int && chain_completed_int))
can_have_new_chain_complete <= descriptor_write_write;
end
assign chain_completed_int_rise = ~delayed_chain_completed_int && chain_completed_int && can_have_new_chain_complete;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
descriptor_counter <= 0;
else if (status_token_fifo_rdreq)
descriptor_counter <= descriptor_counter + 1'b1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_descriptor_counter <= 0;
else
delayed_descriptor_counter <= descriptor_counter;
end
assign delayed_max_desc_processed = max_desc_processed - 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
csr_irq <= 0;
else
csr_irq <= csr_irq ? ~clear_interrupt : (delayed_run && ie_global && ((ie_error && error) || (ie_eop_encountered && eop_encountered_rise) || (ie_descriptor_completed && descriptor_write_write_fall) || (ie_chain_completed && chain_completed_int_rise) || (ie_max_desc_processed && (descriptor_counter == max_desc_processed) && (delayed_descriptor_counter == delayed_max_desc_processed) )));
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module descriptor_read_which_resides_within_amm_master_qsys_with_pcie_sgdma_control_bits_fifo (
// inputs:
clk,
controlbitsfifo_data,
controlbitsfifo_rdreq,
controlbitsfifo_wrreq,
reset,
// outputs:
controlbitsfifo_empty,
controlbitsfifo_full,
controlbitsfifo_q
)
;
output controlbitsfifo_empty;
output controlbitsfifo_full;
output [ 6: 0] controlbitsfifo_q;
input clk;
input [ 6: 0] controlbitsfifo_data;
input controlbitsfifo_rdreq;
input controlbitsfifo_wrreq;
input reset;
wire controlbitsfifo_empty;
wire controlbitsfifo_full;
wire [ 6: 0] controlbitsfifo_q;
scfifo descriptor_read_which_resides_within_amm_master_qsys_with_pcie_sgdma_control_bits_fifo_controlbitsfifo
(
.aclr (reset),
.clock (clk),
.data (controlbitsfifo_data),
.empty (controlbitsfifo_empty),
.full (controlbitsfifo_full),
.q (controlbitsfifo_q),
.rdreq (controlbitsfifo_rdreq),
.wrreq (controlbitsfifo_wrreq)
);
defparam descriptor_read_which_resides_within_amm_master_qsys_with_pcie_sgdma_control_bits_fifo_controlbitsfifo.add_ram_output_register = "ON",
descriptor_read_which_resides_within_amm_master_qsys_with_pcie_sgdma_control_bits_fifo_controlbitsfifo.intended_device_family = "CYCLONEIVGX",
descriptor_read_which_resides_within_amm_master_qsys_with_pcie_sgdma_control_bits_fifo_controlbitsfifo.lpm_numwords = 2,
descriptor_read_which_resides_within_amm_master_qsys_with_pcie_sgdma_control_bits_fifo_controlbitsfifo.lpm_showahead = "OFF",
descriptor_read_which_resides_within_amm_master_qsys_with_pcie_sgdma_control_bits_fifo_controlbitsfifo.lpm_type = "scfifo",
descriptor_read_which_resides_within_amm_master_qsys_with_pcie_sgdma_control_bits_fifo_controlbitsfifo.lpm_width = 7,
descriptor_read_which_resides_within_amm_master_qsys_with_pcie_sgdma_control_bits_fifo_controlbitsfifo.lpm_widthu = 1,
descriptor_read_which_resides_within_amm_master_qsys_with_pcie_sgdma_control_bits_fifo_controlbitsfifo.overflow_checking = "ON",
descriptor_read_which_resides_within_amm_master_qsys_with_pcie_sgdma_control_bits_fifo_controlbitsfifo.underflow_checking = "ON",
descriptor_read_which_resides_within_amm_master_qsys_with_pcie_sgdma_control_bits_fifo_controlbitsfifo.use_eab = "OFF";
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module descriptor_read_which_resides_within_amm_master_qsys_with_pcie_sgdma (
// inputs:
clk,
command_fifo_full,
controlbitsfifo_rdreq,
desc_address_fifo_full,
descriptor_pointer_lower_reg_out,
descriptor_pointer_upper_reg_out,
descriptor_read_readdata,
descriptor_read_readdatavalid,
descriptor_read_waitrequest,
pollen_clear_run,
reset,
reset_n,
run,
// outputs:
atlantic_channel,
chain_run,
command_fifo_data,
command_fifo_wrreq,
control,
controlbitsfifo_q,
desc_address_fifo_data,
desc_address_fifo_wrreq,
descriptor_read_address,
descriptor_read_read,
generate_eop,
next_desc,
owned_by_hw,
read_fixed_address,
write_fixed_address
)
;
output [ 3: 0] atlantic_channel;
output chain_run;
output [103: 0] command_fifo_data;
output command_fifo_wrreq;
output [ 7: 0] control;
output [ 6: 0] controlbitsfifo_q;
output [ 31: 0] desc_address_fifo_data;
output desc_address_fifo_wrreq;
output [ 31: 0] descriptor_read_address;
output descriptor_read_read;
output generate_eop;
output [ 31: 0] next_desc;
output owned_by_hw;
output read_fixed_address;
output write_fixed_address;
input clk;
input command_fifo_full;
input controlbitsfifo_rdreq;
input desc_address_fifo_full;
input [ 31: 0] descriptor_pointer_lower_reg_out;
input [ 31: 0] descriptor_pointer_upper_reg_out;
input [ 31: 0] descriptor_read_readdata;
input descriptor_read_readdatavalid;
input descriptor_read_waitrequest;
input pollen_clear_run;
input reset;
input reset_n;
input run;
wire [ 3: 0] atlantic_channel;
wire [ 15: 0] bytes_to_transfer;
reg chain_run;
wire [103: 0] command_fifo_data;
reg command_fifo_wrreq;
wire command_fifo_wrreq_in;
wire [ 7: 0] control;
wire [ 6: 0] controlbitsfifo_data;
wire controlbitsfifo_empty;
wire controlbitsfifo_full;
wire [ 6: 0] controlbitsfifo_q;
wire controlbitsfifo_wrreq;
reg delayed_desc_reg_en;
reg delayed_run;
reg [ 31: 0] desc_address_fifo_data;
wire desc_address_fifo_wrreq;
reg [255: 0] desc_assembler;
reg desc_read_start;
reg [255: 0] desc_reg;
wire desc_reg_en;
reg [ 31: 0] descriptor_read_address;
reg descriptor_read_completed;
wire descriptor_read_completed_in;
reg descriptor_read_read;
wire fifos_not_full;
wire generate_eop;
wire got_one_descriptor;
wire [255: 0] init_descriptor;
wire [ 31: 0] next_desc;
wire owned_by_hw;
wire [255: 0] pollen_clear_run_desc;
reg [ 3: 0] posted_desc_counter;
reg posted_read_queued;
wire [ 31: 0] read_address;
wire [ 7: 0] read_burst;
wire read_fixed_address;
reg [ 3: 0] received_desc_counter;
reg run_rising_edge;
wire run_rising_edge_in;
reg started;
wire started_in;
wire [ 31: 0] write_address;
wire [ 7: 0] write_burst;
wire write_fixed_address;
//descriptor_read, which is an e_avalon_master
//Control assignments
assign command_fifo_wrreq_in = chain_run && fifos_not_full && delayed_desc_reg_en && owned_by_hw;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
command_fifo_wrreq <= 0;
else
command_fifo_wrreq <= command_fifo_wrreq_in;
end
assign desc_address_fifo_wrreq = command_fifo_wrreq;
assign fifos_not_full = ~command_fifo_full && ~desc_address_fifo_full;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_desc_reg_en <= 0;
else
delayed_desc_reg_en <= desc_reg_en;
end
assign read_address = desc_reg[31 : 0];
assign write_address = desc_reg[95 : 64];
assign next_desc = desc_reg[159 : 128];
assign bytes_to_transfer = desc_reg[207 : 192];
assign read_burst = desc_reg[215 : 208];
assign write_burst = desc_reg[223 : 216];
assign control = desc_reg[255 : 248];
assign command_fifo_data = {control, write_burst, read_burst, bytes_to_transfer, write_address, read_address};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
desc_address_fifo_data <= 0;
else if (desc_reg_en)
desc_address_fifo_data <= next_desc;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
received_desc_counter <= 0;
else
received_desc_counter <= (received_desc_counter == 8)? 0 : (descriptor_read_readdatavalid ? (received_desc_counter + 1) : received_desc_counter);
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
posted_desc_counter <= 0;
else
posted_desc_counter <= (desc_read_start & owned_by_hw & (posted_desc_counter != 8)) ? 8 : ((|posted_desc_counter & ~descriptor_read_waitrequest & fifos_not_full) ? (posted_desc_counter - 1) : posted_desc_counter);
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
desc_read_start <= 0;
else if (~descriptor_read_waitrequest)
desc_read_start <= desc_read_start ? 0 : ((~(desc_reg_en | delayed_desc_reg_en | command_fifo_wrreq | |received_desc_counter)) ? (chain_run & fifos_not_full & ~|posted_desc_counter & ~posted_read_queued) : 0);
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
chain_run <= 0;
else
chain_run <= (run && owned_by_hw | (delayed_desc_reg_en | desc_reg_en) | |posted_desc_counter | |received_desc_counter) || run_rising_edge_in;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
descriptor_read_read <= 0;
else if (~descriptor_read_waitrequest)
descriptor_read_read <= |posted_desc_counter & fifos_not_full;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
descriptor_read_address <= 0;
else if (~descriptor_read_waitrequest)
descriptor_read_address <= (descriptor_read_read)? (descriptor_read_address + 4) : next_desc;
end
assign descriptor_read_completed_in = started ? (run && ~owned_by_hw && ~|posted_desc_counter) : descriptor_read_completed;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
posted_read_queued <= 0;
else
posted_read_queued <= posted_read_queued ? ~(got_one_descriptor) : (descriptor_read_read);
end
//control bits
assign generate_eop = control[0];
assign read_fixed_address = control[1];
assign write_fixed_address = control[2];
assign atlantic_channel = control[6 : 3];
assign owned_by_hw = control[7];
assign got_one_descriptor = received_desc_counter == 8;
//read descriptor
assign desc_reg_en = chain_run && got_one_descriptor;
assign init_descriptor = {1'b1, 31'b0, 32'b0, descriptor_pointer_upper_reg_out, descriptor_pointer_lower_reg_out, 128'b0};
//Clear owned_by_hw bit when run is clear in Descriptor Polling Mode
assign pollen_clear_run_desc = {1'b0, 31'b0, 32'b0, descriptor_pointer_upper_reg_out, descriptor_pointer_lower_reg_out, 128'b0};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
desc_reg <= 0;
else if (desc_reg_en || run_rising_edge_in || pollen_clear_run)
desc_reg <= run_rising_edge_in ? init_descriptor : pollen_clear_run ? pollen_clear_run_desc: desc_assembler;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
desc_assembler <= 0;
else if (descriptor_read_readdatavalid)
desc_assembler <= desc_assembler >> 32 | {descriptor_read_readdata, 224'b0};
end
//descriptor_read_completed register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
descriptor_read_completed <= 0;
else
descriptor_read_completed <= descriptor_read_completed_in;
end
//started register
assign started_in = (run_rising_edge || run_rising_edge_in) ? 1'b1 : (descriptor_read_completed ? 1'b0 : started);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
started <= 0;
else
started <= started_in;
end
//delayed_run signal for the rising edge detector
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_run <= 0;
else
delayed_run <= run;
end
//Run rising edge detector
assign run_rising_edge_in = run & ~delayed_run;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
run_rising_edge <= 0;
else if (run_rising_edge_in || desc_reg_en)
run_rising_edge <= run_rising_edge_in;
end
//the_descriptor_read_which_resides_within_amm_master_qsys_with_pcie_sgdma_control_bits_fifo, which is an e_instance
descriptor_read_which_resides_within_amm_master_qsys_with_pcie_sgdma_control_bits_fifo the_descriptor_read_which_resides_within_amm_master_qsys_with_pcie_sgdma_control_bits_fifo
(
.clk (clk),
.controlbitsfifo_data (controlbitsfifo_data),
.controlbitsfifo_empty (controlbitsfifo_empty),
.controlbitsfifo_full (controlbitsfifo_full),
.controlbitsfifo_q (controlbitsfifo_q),
.controlbitsfifo_rdreq (controlbitsfifo_rdreq),
.controlbitsfifo_wrreq (controlbitsfifo_wrreq),
.reset (reset)
);
assign controlbitsfifo_data = control[6 : 0];
assign controlbitsfifo_wrreq = command_fifo_wrreq;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module descriptor_write_which_resides_within_amm_master_qsys_with_pcie_sgdma (
// inputs:
clk,
controlbitsfifo_q,
desc_address_fifo_empty,
desc_address_fifo_q,
descriptor_write_waitrequest,
park,
reset_n,
status_token_fifo_data,
status_token_fifo_empty,
status_token_fifo_q,
// outputs:
atlantic_error,
controlbitsfifo_rdreq,
desc_address_fifo_rdreq,
descriptor_write_address,
descriptor_write_busy,
descriptor_write_write,
descriptor_write_writedata,
status_token_fifo_rdreq,
t_eop
)
;
output atlantic_error;
output controlbitsfifo_rdreq;
output desc_address_fifo_rdreq;
output [ 31: 0] descriptor_write_address;
output descriptor_write_busy;
output descriptor_write_write;
output [ 31: 0] descriptor_write_writedata;
output status_token_fifo_rdreq;
output t_eop;
input clk;
input [ 6: 0] controlbitsfifo_q;
input desc_address_fifo_empty;
input [ 31: 0] desc_address_fifo_q;
input descriptor_write_waitrequest;
input park;
input reset_n;
input [ 23: 0] status_token_fifo_data;
input status_token_fifo_empty;
input [ 23: 0] status_token_fifo_q;
wire atlantic_error;
wire can_write;
wire controlbitsfifo_rdreq;
wire desc_address_fifo_rdreq;
reg [ 31: 0] descriptor_write_address;
wire descriptor_write_busy;
reg descriptor_write_write;
reg descriptor_write_write0;
reg [ 31: 0] descriptor_write_writedata;
wire fifos_not_empty;
wire [ 7: 0] status_reg;
reg status_token_fifo_rdreq;
wire status_token_fifo_rdreq_in;
wire t_eop;
//descriptor_write, which is an e_avalon_master
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
descriptor_write_writedata <= 0;
else if (~descriptor_write_waitrequest)
descriptor_write_writedata <= {park, controlbitsfifo_q, status_token_fifo_q};
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
descriptor_write_address <= 0;
else if (~descriptor_write_waitrequest)
descriptor_write_address <= desc_address_fifo_q + 28;
end
assign fifos_not_empty = ~status_token_fifo_empty && ~desc_address_fifo_empty;
assign can_write = ~descriptor_write_waitrequest && fifos_not_empty;
//write register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
descriptor_write_write0 <= 0;
else if (~descriptor_write_waitrequest)
descriptor_write_write0 <= status_token_fifo_rdreq;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
descriptor_write_write <= 0;
else if (~descriptor_write_waitrequest)
descriptor_write_write <= descriptor_write_write0;
end
//status_token_fifo_rdreq register
assign status_token_fifo_rdreq_in = status_token_fifo_rdreq ? 1'b0 : can_write;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
status_token_fifo_rdreq <= 0;
else
status_token_fifo_rdreq <= status_token_fifo_rdreq_in;
end
assign desc_address_fifo_rdreq = status_token_fifo_rdreq;
assign descriptor_write_busy = descriptor_write_write0 | descriptor_write_write;
assign status_reg = status_token_fifo_data[23 : 16];
assign t_eop = status_reg[7];
assign atlantic_error = status_reg[6] | status_reg[5] | status_reg[4] | status_reg[3] | status_reg[2] | status_reg[1] | status_reg[0];
assign controlbitsfifo_rdreq = status_token_fifo_rdreq;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module amm_master_qsys_with_pcie_sgdma_chain (
// inputs:
clk,
command_fifo_empty,
command_fifo_full,
csr_address,
csr_chipselect,
csr_read,
csr_write,
csr_writedata,
desc_address_fifo_empty,
desc_address_fifo_full,
desc_address_fifo_q,
descriptor_read_readdata,
descriptor_read_readdatavalid,
descriptor_read_waitrequest,
descriptor_write_waitrequest,
read_go,
reset,
reset_n,
status_token_fifo_data,
status_token_fifo_empty,
status_token_fifo_q,
write_go,
// outputs:
command_fifo_data,
command_fifo_wrreq,
csr_irq,
csr_readdata,
desc_address_fifo_data,
desc_address_fifo_rdreq,
desc_address_fifo_wrreq,
descriptor_read_address,
descriptor_read_read,
descriptor_write_address,
descriptor_write_write,
descriptor_write_writedata,
status_token_fifo_rdreq,
sw_reset
)
;
output [103: 0] command_fifo_data;
output command_fifo_wrreq;
output csr_irq;
output [ 31: 0] csr_readdata;
output [ 31: 0] desc_address_fifo_data;
output desc_address_fifo_rdreq;
output desc_address_fifo_wrreq;
output [ 31: 0] descriptor_read_address;
output descriptor_read_read;
output [ 31: 0] descriptor_write_address;
output descriptor_write_write;
output [ 31: 0] descriptor_write_writedata;
output status_token_fifo_rdreq;
output sw_reset;
input clk;
input command_fifo_empty;
input command_fifo_full;
input [ 3: 0] csr_address;
input csr_chipselect;
input csr_read;
input csr_write;
input [ 31: 0] csr_writedata;
input desc_address_fifo_empty;
input desc_address_fifo_full;
input [ 31: 0] desc_address_fifo_q;
input [ 31: 0] descriptor_read_readdata;
input descriptor_read_readdatavalid;
input descriptor_read_waitrequest;
input descriptor_write_waitrequest;
input read_go;
input reset;
input reset_n;
input [ 23: 0] status_token_fifo_data;
input status_token_fifo_empty;
input [ 23: 0] status_token_fifo_q;
input write_go;
wire [ 3: 0] atlantic_channel;
wire atlantic_error;
wire chain_run;
wire [103: 0] command_fifo_data;
wire command_fifo_wrreq;
wire [ 7: 0] control;
wire [ 6: 0] controlbitsfifo_q;
wire controlbitsfifo_rdreq;
wire csr_irq;
wire [ 31: 0] csr_readdata;
wire [ 31: 0] desc_address_fifo_data;
wire desc_address_fifo_rdreq;
wire desc_address_fifo_wrreq;
wire [ 31: 0] descriptor_pointer_lower_reg_out;
wire [ 31: 0] descriptor_pointer_upper_reg_out;
wire [ 31: 0] descriptor_read_address;
wire descriptor_read_read;
wire [ 31: 0] descriptor_write_address;
wire descriptor_write_busy;
wire descriptor_write_write;
wire [ 31: 0] descriptor_write_writedata;
wire generate_eop;
wire [ 31: 0] next_desc;
wire owned_by_hw;
wire park;
wire pollen_clear_run;
wire read_fixed_address;
wire run;
wire status_token_fifo_rdreq;
wire sw_reset;
wire t_eop;
wire write_fixed_address;
control_status_slave_which_resides_within_amm_master_qsys_with_pcie_sgdma the_control_status_slave_which_resides_within_amm_master_qsys_with_pcie_sgdma
(
.atlantic_error (atlantic_error),
.chain_run (chain_run),
.clk (clk),
.command_fifo_empty (command_fifo_empty),
.csr_address (csr_address),
.csr_chipselect (csr_chipselect),
.csr_irq (csr_irq),
.csr_read (csr_read),
.csr_readdata (csr_readdata),
.csr_write (csr_write),
.csr_writedata (csr_writedata),
.desc_address_fifo_empty (desc_address_fifo_empty),
.descriptor_pointer_lower_reg_out (descriptor_pointer_lower_reg_out),
.descriptor_pointer_upper_reg_out (descriptor_pointer_upper_reg_out),
.descriptor_read_address (descriptor_read_address),
.descriptor_read_read (descriptor_read_read),
.descriptor_write_busy (descriptor_write_busy),
.descriptor_write_write (descriptor_write_write),
.owned_by_hw (owned_by_hw),
.park (park),
.pollen_clear_run (pollen_clear_run),
.read_go (read_go),
.reset_n (reset_n),
.run (run),
.status_token_fifo_empty (status_token_fifo_empty),
.status_token_fifo_rdreq (status_token_fifo_rdreq),
.sw_reset (sw_reset),
.write_go (write_go)
);
descriptor_read_which_resides_within_amm_master_qsys_with_pcie_sgdma the_descriptor_read_which_resides_within_amm_master_qsys_with_pcie_sgdma
(
.atlantic_channel (atlantic_channel),
.chain_run (chain_run),
.clk (clk),
.command_fifo_data (command_fifo_data),
.command_fifo_full (command_fifo_full),
.command_fifo_wrreq (command_fifo_wrreq),
.control (control),
.controlbitsfifo_q (controlbitsfifo_q),
.controlbitsfifo_rdreq (controlbitsfifo_rdreq),
.desc_address_fifo_data (desc_address_fifo_data),
.desc_address_fifo_full (desc_address_fifo_full),
.desc_address_fifo_wrreq (desc_address_fifo_wrreq),
.descriptor_pointer_lower_reg_out (descriptor_pointer_lower_reg_out),
.descriptor_pointer_upper_reg_out (descriptor_pointer_upper_reg_out),
.descriptor_read_address (descriptor_read_address),
.descriptor_read_read (descriptor_read_read),
.descriptor_read_readdata (descriptor_read_readdata),
.descriptor_read_readdatavalid (descriptor_read_readdatavalid),
.descriptor_read_waitrequest (descriptor_read_waitrequest),
.generate_eop (generate_eop),
.next_desc (next_desc),
.owned_by_hw (owned_by_hw),
.pollen_clear_run (pollen_clear_run),
.read_fixed_address (read_fixed_address),
.reset (reset),
.reset_n (reset_n),
.run (run),
.write_fixed_address (write_fixed_address)
);
descriptor_write_which_resides_within_amm_master_qsys_with_pcie_sgdma the_descriptor_write_which_resides_within_amm_master_qsys_with_pcie_sgdma
(
.atlantic_error (atlantic_error),
.clk (clk),
.controlbitsfifo_q (controlbitsfifo_q),
.controlbitsfifo_rdreq (controlbitsfifo_rdreq),
.desc_address_fifo_empty (desc_address_fifo_empty),
.desc_address_fifo_q (desc_address_fifo_q),
.desc_address_fifo_rdreq (desc_address_fifo_rdreq),
.descriptor_write_address (descriptor_write_address),
.descriptor_write_busy (descriptor_write_busy),
.descriptor_write_waitrequest (descriptor_write_waitrequest),
.descriptor_write_write (descriptor_write_write),
.descriptor_write_writedata (descriptor_write_writedata),
.park (park),
.reset_n (reset_n),
.status_token_fifo_data (status_token_fifo_data),
.status_token_fifo_empty (status_token_fifo_empty),
.status_token_fifo_q (status_token_fifo_q),
.status_token_fifo_rdreq (status_token_fifo_rdreq),
.t_eop (t_eop)
);
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module amm_master_qsys_with_pcie_sgdma_command_grabber (
// inputs:
clk,
command_fifo_empty,
command_fifo_q,
m_read_waitrequest,
m_write_waitrequest,
read_go,
reset_n,
write_go,
// outputs:
command_fifo_rdreq,
read_command_data,
read_command_valid,
write_command_data,
write_command_valid
)
;
output command_fifo_rdreq;
output [ 58: 0] read_command_data;
output read_command_valid;
output [ 56: 0] write_command_data;
output write_command_valid;
input clk;
input command_fifo_empty;
input [103: 0] command_fifo_q;
input m_read_waitrequest;
input m_write_waitrequest;
input read_go;
input reset_n;
input write_go;
wire [ 3: 0] atlantic_channel;
wire [ 15: 0] bytes_to_transfer;
wire command_fifo_rdreq;
wire command_fifo_rdreq_in;
reg command_fifo_rdreq_reg;
reg command_valid;
wire [ 7: 0] control;
reg delay1_command_valid;
wire generate_eop;
wire [ 31: 0] read_address;
wire [ 7: 0] read_burst;
reg [ 58: 0] read_command_data;
wire read_command_valid;
wire read_fixed_address;
wire [ 31: 0] write_address;
wire [ 7: 0] write_burst;
reg [ 56: 0] write_command_data;
wire write_command_valid;
wire write_fixed_address;
//Descriptor components
assign read_address = command_fifo_q[31 : 0];
assign write_address = command_fifo_q[63 : 32];
assign bytes_to_transfer = command_fifo_q[79 : 64];
assign read_burst = command_fifo_q[87 : 80];
assign write_burst = command_fifo_q[95 : 88];
assign control = command_fifo_q[103 : 96];
//control bits
assign generate_eop = control[0];
assign read_fixed_address = control[1];
assign write_fixed_address = control[2];
assign atlantic_channel = control[6 : 3];
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
read_command_data <= 0;
else
read_command_data <= {write_fixed_address, generate_eop, ~read_fixed_address, read_burst, bytes_to_transfer, read_address};
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
write_command_data <= 0;
else
write_command_data <= {~write_fixed_address, write_burst, bytes_to_transfer, write_address};
end
assign read_command_valid = command_valid;
assign write_command_valid = command_valid;
//command_fifo_rdreq register
assign command_fifo_rdreq_in = (command_fifo_rdreq_reg || command_valid) ? 1'b0 : (~read_go && ~write_go && ~m_read_waitrequest && ~m_write_waitrequest);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
command_fifo_rdreq_reg <= 0;
else if (~command_fifo_empty)
command_fifo_rdreq_reg <= command_fifo_rdreq_in;
end
assign command_fifo_rdreq = command_fifo_rdreq_reg;
//command_valid register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delay1_command_valid <= 0;
else
delay1_command_valid <= command_fifo_rdreq_reg;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
command_valid <= 0;
else
command_valid <= delay1_command_valid;
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module amm_master_qsys_with_pcie_sgdma_m_read (
// inputs:
clk,
m_read_readdata,
m_read_readdatavalid,
m_read_waitrequest,
m_readfifo_usedw,
read_command_data,
read_command_valid,
reset_n,
source_stream_ready,
// outputs:
m_read_address,
m_read_burstcount,
m_read_read,
read_go,
source_stream_data,
source_stream_empty,
source_stream_endofpacket,
source_stream_startofpacket,
source_stream_valid
)
;
output [ 31: 0] m_read_address;
output [ 3: 0] m_read_burstcount;
output m_read_read;
output read_go;
output [ 63: 0] source_stream_data;
output [ 2: 0] source_stream_empty;
output source_stream_endofpacket;
output source_stream_startofpacket;
output source_stream_valid;
input clk;
input [ 63: 0] m_read_readdata;
input m_read_readdatavalid;
input m_read_waitrequest;
input [ 4: 0] m_readfifo_usedw;
input [ 58: 0] read_command_data;
input read_command_valid;
input reset_n;
input source_stream_ready;
wire [ 3: 0] burst_size;
wire [ 6: 0] burst_size_right_shifted;
wire [ 3: 0] burst_value;
wire [ 15: 0] bytes_to_transfer;
wire [ 3: 0] empty_operand;
reg [ 3: 0] empty_value;
wire endofpacket;
wire generate_eop;
wire generate_sop;
wire has_transactions_to_post;
wire increment_address;
reg [ 31: 0] m_read_address;
wire [ 31: 0] m_read_address_inc;
reg [ 3: 0] m_read_burstcount;
reg m_read_read;
reg [ 6: 0] m_read_state;
wire maximum_transactions_in_queue;
reg [ 58: 0] read_command_data_reg;
wire read_go;
wire read_posted;
wire [ 5: 0] readfifo_remaining_space;
reg [ 15: 0] received_data_counter;
wire received_enough_data;
reg [ 15: 0] remaining_transactions;
wire single_transfer;
wire [ 63: 0] source_stream_data;
wire [ 2: 0] source_stream_empty;
wire source_stream_endofpacket;
reg source_stream_startofpacket;
wire source_stream_valid;
wire [ 31: 0] start_address;
wire still_got_full_burst;
reg [ 5: 0] transactions_in_queue;
reg [ 15: 0] transactions_left_to_post;
wire tx_shift;
//m_read, which is an e_avalon_master
//read_command_data_reg
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
read_command_data_reg <= 0;
else if (read_command_valid)
read_command_data_reg <= read_command_data;
end
//command input
assign start_address = read_command_data_reg[31 : 0];
assign bytes_to_transfer = read_command_data_reg[47 : 32];
assign increment_address = read_command_data_reg[56];
assign generate_eop = read_command_data_reg[57];
assign generate_sop = read_command_data_reg[58];
assign burst_size = 8;
assign burst_size_right_shifted = {burst_size, 3'b0};
//Request Path
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
transactions_left_to_post <= 0;
else if (m_read_state == 7'b0000100)
transactions_left_to_post <= (bytes_to_transfer >> 3) + |bytes_to_transfer[2 : 0];
else if (~m_read_waitrequest)
begin
if (m_read_state == 7'b0001000 & m_read_read)
transactions_left_to_post <= transactions_left_to_post - burst_value;
end
else if (m_read_state == 7'b1000000)
transactions_left_to_post <= 0;
end
assign still_got_full_burst = transactions_left_to_post >= burst_size;
assign burst_value = still_got_full_burst ? burst_size : transactions_left_to_post;
assign has_transactions_to_post = |transactions_left_to_post;
assign read_posted = m_read_read & ~m_read_waitrequest;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
transactions_in_queue <= 0;
else
transactions_in_queue <= (read_posted & ~m_read_readdatavalid) ? (transactions_in_queue + m_read_burstcount) : ((~read_posted & m_read_readdatavalid) ? (transactions_in_queue - 1) : ((read_posted & m_read_readdatavalid) ? (transactions_in_queue -1 + m_read_burstcount) : (transactions_in_queue)));
end
assign readfifo_remaining_space = 32-m_readfifo_usedw-transactions_in_queue-1;
assign maximum_transactions_in_queue = burst_value >= readfifo_remaining_space;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
m_read_read <= 0;
else if (~m_read_waitrequest)
m_read_read <= m_read_read? 0: read_go & (m_read_state == 7'b0001000) & has_transactions_to_post & ~maximum_transactions_in_queue;
end
assign m_read_address_inc = increment_address ? (m_read_address + burst_size_right_shifted) : m_read_address;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
m_read_address <= 0;
else if (m_read_state == 7'b0000100)
m_read_address <= {start_address[31 : 3], 3'b0};
else if (~m_read_waitrequest)
if (read_go & m_read_read)
m_read_address <= m_read_address_inc;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
m_read_burstcount <= 0;
else if (~m_read_waitrequest)
m_read_burstcount <= burst_value;
end
//Unaligned transfer not supported, tx_shift is always 0.
assign tx_shift = 0;
//Response Path
assign single_transfer = source_stream_startofpacket & source_stream_endofpacket;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
received_data_counter <= 0;
else if (m_read_readdatavalid)
begin
if (single_transfer)
received_data_counter <= received_data_counter + 8 - tx_shift - source_stream_empty;
else if (endofpacket)
received_data_counter <= received_data_counter + (|bytes_to_transfer[2 : 0] ? bytes_to_transfer[2 : 0] : 8);
else if (~|received_data_counter)
received_data_counter <= received_data_counter + 8 - tx_shift;
else
received_data_counter <= received_data_counter + 8;
end
else if (m_read_state == 7'b0000010)
received_data_counter <= 0;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
remaining_transactions <= 0;
else if (m_read_state == 7'b0000100)
remaining_transactions <= (bytes_to_transfer >> 3) + |bytes_to_transfer[2 : 0];
else if (read_go & m_read_readdatavalid)
remaining_transactions <= remaining_transactions -1;
end
assign endofpacket = remaining_transactions == 1;
//FSM
assign received_enough_data = received_data_counter >= bytes_to_transfer;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
m_read_state <= 7'b0000001;
else if (1)
case (m_read_state) // synthesis parallel_case
7'b0000001: begin
if (read_command_valid)
m_read_state <= 7'b0000010;
end // 7'b0000001
7'b0000010: begin
m_read_state <= 7'b0000100;
end // 7'b0000010
7'b0000100: begin
if (maximum_transactions_in_queue)
m_read_state <= 7'b0010000;
else
m_read_state <= 7'b0001000;
end // 7'b0000100
7'b0001000: begin
if (~m_read_waitrequest & maximum_transactions_in_queue)
m_read_state <= 7'b0010000;
else if (~has_transactions_to_post)
m_read_state <= 7'b0100000;
else if (received_enough_data)
m_read_state <= 7'b1000000;
end // 7'b0001000
7'b0010000: begin
if (received_enough_data)
m_read_state <= 7'b1000000;
else if (~has_transactions_to_post)
m_read_state <= 7'b0100000;
else if (~m_read_waitrequest & ~maximum_transactions_in_queue)
m_read_state <= 7'b0001000;
end // 7'b0010000
7'b0100000: begin
if (received_enough_data)
m_read_state <= 7'b1000000;
end // 7'b0100000
7'b1000000: begin
m_read_state <= 7'b0000001;
end // 7'b1000000
default: begin
m_read_state <= 7'b0000001;
end // default
endcase // m_read_state
end
assign read_go = |(m_read_state & (7'b0001000 | 7'b0010000 | 7'b0100000 | 7'b1000000));
//Output on the Av-ST Source
assign source_stream_data = m_read_readdata;
assign source_stream_valid = read_go & m_read_readdatavalid;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
source_stream_startofpacket <= 0;
else if (~source_stream_startofpacket)
source_stream_startofpacket <= m_read_state == 7'b0000100;
else if (source_stream_valid)
source_stream_startofpacket <= ~source_stream_ready;
end
assign source_stream_endofpacket = read_go & endofpacket & m_read_readdatavalid;
assign source_stream_empty = (endofpacket && source_stream_valid) ? empty_value : 0;
assign empty_operand = 4'b1000;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
empty_value <= 0;
else
empty_value <= empty_operand - bytes_to_transfer[2 : 0];
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module amm_master_qsys_with_pcie_sgdma_m_readfifo_m_readfifo (
// inputs:
clk,
m_readfifo_data,
m_readfifo_rdreq,
m_readfifo_wrreq,
reset,
// outputs:
m_readfifo_empty,
m_readfifo_full,
m_readfifo_q,
m_readfifo_usedw
)
;
output m_readfifo_empty;
output m_readfifo_full;
output [ 68: 0] m_readfifo_q;
output [ 4: 0] m_readfifo_usedw;
input clk;
input [ 68: 0] m_readfifo_data;
input m_readfifo_rdreq;
input m_readfifo_wrreq;
input reset;
wire m_readfifo_empty;
wire m_readfifo_full;
wire [ 68: 0] m_readfifo_q;
wire [ 4: 0] m_readfifo_usedw;
scfifo amm_master_qsys_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo
(
.aclr (reset),
.clock (clk),
.data (m_readfifo_data),
.empty (m_readfifo_empty),
.full (m_readfifo_full),
.q (m_readfifo_q),
.rdreq (m_readfifo_rdreq),
.usedw (m_readfifo_usedw),
.wrreq (m_readfifo_wrreq)
);
defparam amm_master_qsys_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.add_ram_output_register = "ON",
amm_master_qsys_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.intended_device_family = "CYCLONEIVGX",
amm_master_qsys_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.lpm_numwords = 32,
amm_master_qsys_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.lpm_showahead = "OFF",
amm_master_qsys_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.lpm_type = "scfifo",
amm_master_qsys_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.lpm_width = 69,
amm_master_qsys_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.lpm_widthu = 5,
amm_master_qsys_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.overflow_checking = "ON",
amm_master_qsys_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.underflow_checking = "ON",
amm_master_qsys_with_pcie_sgdma_m_readfifo_m_readfifo_m_readfifo.use_eab = "ON";
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module amm_master_qsys_with_pcie_sgdma_m_readfifo (
// inputs:
clk,
reset,
reset_n,
sink_stream_data,
sink_stream_empty,
sink_stream_endofpacket,
sink_stream_startofpacket,
sink_stream_valid,
source_stream_ready,
// outputs:
m_readfifo_usedw,
sink_stream_ready,
source_stream_data,
source_stream_empty,
source_stream_endofpacket,
source_stream_startofpacket,
source_stream_valid
)
;
output [ 4: 0] m_readfifo_usedw;
output sink_stream_ready;
output [ 63: 0] source_stream_data;
output [ 2: 0] source_stream_empty;
output source_stream_endofpacket;
output source_stream_startofpacket;
output source_stream_valid;
input clk;
input reset;
input reset_n;
input [ 63: 0] sink_stream_data;
input [ 2: 0] sink_stream_empty;
input sink_stream_endofpacket;
input sink_stream_startofpacket;
input sink_stream_valid;
input source_stream_ready;
reg delayed_m_readfifo_empty;
wire hold_condition;
reg [ 68: 0] m_readfifo_data;
wire m_readfifo_empty;
wire m_readfifo_empty_fall;
wire m_readfifo_full;
wire [ 68: 0] m_readfifo_q;
wire m_readfifo_rdreq;
reg m_readfifo_rdreq_delay;
wire [ 4: 0] m_readfifo_usedw;
reg m_readfifo_wrreq;
wire sink_stream_ready;
wire [ 63: 0] source_stream_data;
wire [ 2: 0] source_stream_empty;
reg [ 2: 0] source_stream_empty_hold;
wire [ 2: 0] source_stream_empty_sig;
wire source_stream_endofpacket;
wire source_stream_endofpacket_from_fifo;
reg source_stream_endofpacket_hold;
wire source_stream_endofpacket_sig;
wire source_stream_startofpacket;
wire source_stream_valid;
reg source_stream_valid_reg;
reg transmitted_eop;
//the_amm_master_qsys_with_pcie_sgdma_m_readfifo_m_readfifo, which is an e_instance
amm_master_qsys_with_pcie_sgdma_m_readfifo_m_readfifo the_amm_master_qsys_with_pcie_sgdma_m_readfifo_m_readfifo
(
.clk (clk),
.m_readfifo_data (m_readfifo_data),
.m_readfifo_empty (m_readfifo_empty),
.m_readfifo_full (m_readfifo_full),
.m_readfifo_q (m_readfifo_q),
.m_readfifo_rdreq (m_readfifo_rdreq),
.m_readfifo_usedw (m_readfifo_usedw),
.m_readfifo_wrreq (m_readfifo_wrreq),
.reset (reset)
);
assign sink_stream_ready = ~m_readfifo_full;
assign m_readfifo_rdreq = ~m_readfifo_empty & source_stream_ready | m_readfifo_empty_fall & ~hold_condition;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_m_readfifo_empty <= 0;
else
delayed_m_readfifo_empty <= m_readfifo_empty;
end
assign m_readfifo_empty_fall = ~m_readfifo_empty & delayed_m_readfifo_empty;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
source_stream_valid_reg <= 0;
else if (source_stream_ready | m_readfifo_rdreq)
source_stream_valid_reg <= m_readfifo_rdreq;
end
assign source_stream_valid = source_stream_valid_reg;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
m_readfifo_wrreq <= 0;
else
m_readfifo_wrreq <= sink_stream_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
m_readfifo_rdreq_delay <= 0;
else
m_readfifo_rdreq_delay <= m_readfifo_rdreq;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
transmitted_eop <= 0;
else
transmitted_eop <= transmitted_eop ? ~m_readfifo_rdreq : source_stream_endofpacket & source_stream_ready & source_stream_valid;
end
assign source_stream_endofpacket_sig = m_readfifo_rdreq_delay? source_stream_endofpacket_from_fifo | source_stream_endofpacket_hold : (source_stream_endofpacket_from_fifo & ~transmitted_eop) | source_stream_endofpacket_hold;
assign source_stream_endofpacket = source_stream_endofpacket_sig;
assign hold_condition = source_stream_valid & ~source_stream_ready;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
source_stream_endofpacket_hold <= 0;
else
source_stream_endofpacket_hold <= hold_condition ? source_stream_endofpacket_sig : (source_stream_ready ? 0 : source_stream_endofpacket_hold);
end
assign source_stream_empty_sig = m_readfifo_q[66 : 64];
assign source_stream_empty = source_stream_empty_sig | source_stream_empty_hold;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
source_stream_empty_hold <= 0;
else
source_stream_empty_hold <= hold_condition ? source_stream_empty_sig : (source_stream_ready ? 0 : source_stream_empty_hold);
end
assign source_stream_data = m_readfifo_q[63 : 0];
assign source_stream_endofpacket_from_fifo = m_readfifo_q[67];
assign source_stream_startofpacket = m_readfifo_q[68];
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
m_readfifo_data <= 0;
else
m_readfifo_data <= {sink_stream_startofpacket, sink_stream_endofpacket, sink_stream_empty, sink_stream_data};
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module amm_master_qsys_with_pcie_sgdma_m_writefifo_m_writefifo (
// inputs:
clk,
m_writefifo_data,
m_writefifo_rdreq,
m_writefifo_wrreq,
reset,
// outputs:
m_writefifo_empty,
m_writefifo_full,
m_writefifo_q,
m_writefifo_usedw
)
;
output m_writefifo_empty;
output m_writefifo_full;
output [ 68: 0] m_writefifo_q;
output [ 8: 0] m_writefifo_usedw;
input clk;
input [ 68: 0] m_writefifo_data;
input m_writefifo_rdreq;
input m_writefifo_wrreq;
input reset;
wire m_writefifo_empty;
wire m_writefifo_full;
wire [ 68: 0] m_writefifo_q;
wire [ 8: 0] m_writefifo_usedw;
scfifo amm_master_qsys_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo
(
.aclr (reset),
.clock (clk),
.data (m_writefifo_data),
.empty (m_writefifo_empty),
.full (m_writefifo_full),
.q (m_writefifo_q),
.rdreq (m_writefifo_rdreq),
.usedw (m_writefifo_usedw),
.wrreq (m_writefifo_wrreq)
);
defparam amm_master_qsys_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.add_ram_output_register = "ON",
amm_master_qsys_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.intended_device_family = "CYCLONEIVGX",
amm_master_qsys_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.lpm_numwords = 512,
amm_master_qsys_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.lpm_showahead = "ON",
amm_master_qsys_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.lpm_type = "scfifo",
amm_master_qsys_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.lpm_width = 69,
amm_master_qsys_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.lpm_widthu = 9,
amm_master_qsys_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.overflow_checking = "ON",
amm_master_qsys_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.underflow_checking = "ON",
amm_master_qsys_with_pcie_sgdma_m_writefifo_m_writefifo_m_writefifo.use_eab = "ON";
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module amm_master_qsys_with_pcie_sgdma_m_writefifo (
// inputs:
clk,
reset,
reset_n,
sink_stream_data,
sink_stream_empty,
sink_stream_endofpacket,
sink_stream_startofpacket,
sink_stream_valid,
source_stream_ready,
// outputs:
eop_found,
m_writefifo_fill,
sink_stream_ready,
source_stream_data,
source_stream_empty,
source_stream_endofpacket,
source_stream_startofpacket,
source_stream_valid
)
;
output eop_found;
output [ 8: 0] m_writefifo_fill;
output sink_stream_ready;
output [ 63: 0] source_stream_data;
output [ 2: 0] source_stream_empty;
output source_stream_endofpacket;
output source_stream_startofpacket;
output source_stream_valid;
input clk;
input reset;
input reset_n;
input [ 63: 0] sink_stream_data;
input [ 2: 0] sink_stream_empty;
input sink_stream_endofpacket;
input sink_stream_startofpacket;
input sink_stream_valid;
input source_stream_ready;
reg eop_found;
wire hold_condition;
wire in_eop_found;
reg [ 68: 0] m_writefifo_data;
wire m_writefifo_empty;
wire [ 8: 0] m_writefifo_fill;
wire m_writefifo_full;
wire [ 68: 0] m_writefifo_q;
wire m_writefifo_rdreq;
wire [ 8: 0] m_writefifo_usedw;
reg m_writefifo_wrreq;
reg pause_till_eop_out;
wire sink_stream_ready;
wire sink_stream_really_valid;
wire [ 63: 0] source_stream_data;
wire [ 2: 0] source_stream_empty;
reg [ 2: 0] source_stream_empty_hold;
wire [ 2: 0] source_stream_empty_sig;
wire source_stream_endofpacket;
wire source_stream_endofpacket_from_fifo;
reg source_stream_endofpacket_hold;
wire source_stream_endofpacket_sig;
wire source_stream_startofpacket;
wire source_stream_valid;
reg transmitted_eop;
//the_amm_master_qsys_with_pcie_sgdma_m_writefifo_m_writefifo, which is an e_instance
amm_master_qsys_with_pcie_sgdma_m_writefifo_m_writefifo the_amm_master_qsys_with_pcie_sgdma_m_writefifo_m_writefifo
(
.clk (clk),
.m_writefifo_data (m_writefifo_data),
.m_writefifo_empty (m_writefifo_empty),
.m_writefifo_full (m_writefifo_full),
.m_writefifo_q (m_writefifo_q),
.m_writefifo_rdreq (m_writefifo_rdreq),
.m_writefifo_usedw (m_writefifo_usedw),
.m_writefifo_wrreq (m_writefifo_wrreq),
.reset (reset)
);
assign sink_stream_ready = ~m_writefifo_usedw[8] && ~m_writefifo_full && ~pause_till_eop_out;
assign m_writefifo_rdreq = ~m_writefifo_empty & source_stream_ready;
assign source_stream_valid = ~m_writefifo_empty;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
m_writefifo_wrreq <= 0;
else
m_writefifo_wrreq <= sink_stream_really_valid;
end
assign sink_stream_really_valid = sink_stream_valid & sink_stream_ready;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
transmitted_eop <= 0;
else
transmitted_eop <= source_stream_endofpacket & source_stream_ready & source_stream_valid;
end
assign source_stream_endofpacket_sig = (source_stream_endofpacket_from_fifo & ~transmitted_eop) | source_stream_endofpacket_hold;
assign source_stream_endofpacket = source_stream_endofpacket_sig;
assign hold_condition = source_stream_valid & ~source_stream_ready;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
source_stream_endofpacket_hold <= 0;
else
source_stream_endofpacket_hold <= hold_condition ? source_stream_endofpacket_sig : (source_stream_ready ? 0 : source_stream_endofpacket_hold);
end
assign m_writefifo_fill = m_writefifo_empty ? 0 : m_writefifo_usedw;
assign source_stream_empty_sig = m_writefifo_q[66 : 64];
assign source_stream_empty = source_stream_empty_sig | source_stream_empty_hold;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
source_stream_empty_hold <= 0;
else
source_stream_empty_hold <= hold_condition ? source_stream_empty_sig : (source_stream_ready ? 0 : source_stream_empty_hold);
end
assign source_stream_data = m_writefifo_q[63 : 0];
assign source_stream_startofpacket = m_writefifo_q[68];
assign source_stream_endofpacket_from_fifo = m_writefifo_q[67];
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
m_writefifo_data <= 0;
else
m_writefifo_data <= {sink_stream_startofpacket, sink_stream_endofpacket, sink_stream_empty, sink_stream_data};
end
assign in_eop_found = sink_stream_really_valid & sink_stream_endofpacket;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
eop_found <= 0;
else
eop_found <= eop_found ? ~(source_stream_ready) : in_eop_found;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
pause_till_eop_out <= 0;
else
pause_till_eop_out <= pause_till_eop_out ? ~(source_stream_valid & source_stream_ready & source_stream_endofpacket): in_eop_found;
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module amm_master_qsys_with_pcie_sgdma_m_write (
// inputs:
clk,
e_00,
e_01,
e_02,
e_03,
e_04,
e_05,
e_06,
eop_found,
m_write_waitrequest,
m_writefifo_fill,
reset_n,
sink_stream_data,
sink_stream_empty,
sink_stream_endofpacket,
sink_stream_startofpacket,
sink_stream_valid,
status_token_fifo_full,
write_command_data,
write_command_valid,
// outputs:
m_write_address,
m_write_burstcount,
m_write_byteenable,
m_write_write,
m_write_writedata,
sink_stream_ready,
status_token_fifo_data,
status_token_fifo_wrreq,
write_go
)
;
output [ 31: 0] m_write_address;
output [ 7: 0] m_write_burstcount;
output [ 7: 0] m_write_byteenable;
output m_write_write;
output [ 63: 0] m_write_writedata;
output sink_stream_ready;
output [ 23: 0] status_token_fifo_data;
output status_token_fifo_wrreq;
output write_go;
input clk;
input e_00;
input e_01;
input e_02;
input e_03;
input e_04;
input e_05;
input e_06;
input eop_found;
input m_write_waitrequest;
input [ 8: 0] m_writefifo_fill;
input reset_n;
input [ 63: 0] sink_stream_data;
input [ 2: 0] sink_stream_empty;
input sink_stream_endofpacket;
input sink_stream_startofpacket;
input sink_stream_valid;
input status_token_fifo_full;
input [ 56: 0] write_command_data;
input write_command_valid;
wire [ 15: 0] actual_bytes_transferred;
wire [ 7: 0] all_one;
reg [ 7: 0] burst_counter;
wire burst_counter_decrement;
wire [ 7: 0] burst_counter_next;
reg [ 7: 0] burst_counter_reg;
reg [ 7: 0] burst_size;
reg byteenable_enable;
wire [ 15: 0] bytes_to_transfer;
reg [ 15: 0] counter;
wire [ 15: 0] counter_in;
reg delayed_write_command_valid;
reg delayed_write_go;
wire enough_data;
reg eop_found_hold;
reg eop_reg;
wire increment;
wire increment_address;
reg [ 31: 0] m_write_address;
reg [ 7: 0] m_write_burstcount;
wire [ 10: 0] m_write_burstcount_right_shifted;
wire [ 7: 0] m_write_byteenable;
wire [ 7: 0] m_write_byteenable_in;
reg [ 7: 0] m_write_byteenable_reg;
wire m_write_waitrequest_out;
reg m_write_write;
reg m_write_write_sig;
wire [ 63: 0] m_write_writedata;
reg [ 63: 0] m_write_writedata_reg;
wire [ 7: 0] shift0;
wire [ 7: 0] shift1;
wire [ 7: 0] shift2;
wire [ 7: 0] shift3;
wire [ 7: 0] shift4;
wire [ 7: 0] shift5;
wire [ 7: 0] shift6;
wire [ 7: 0] shift7;
wire single_transfer;
wire [ 7: 0] sink_stream_empty_shift;
wire sink_stream_ready;
wire sink_stream_really_valid;
wire [ 31: 0] start_address;
reg [ 7: 0] status_reg;
wire [ 7: 0] status_reg_in;
wire [ 23: 0] status_token_fifo_data;
wire status_token_fifo_wrreq;
wire [ 7: 0] status_word;
wire t_eop;
reg [ 15: 0] transfer_remaining;
reg [ 56: 0] write_command_data_reg;
wire write_go;
reg write_go_fall_reg;
wire write_go_fall_reg_in;
reg write_go_reg;
wire write_go_reg_in;
wire write_go_reg_in_teop;
//m_write, which is an e_avalon_master
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
transfer_remaining <= 0;
else
transfer_remaining <= (bytes_to_transfer-counter_in + 7)>>3;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
burst_size <= 0;
else
burst_size <= (!(|bytes_to_transfer)) ?128:
transfer_remaining>=128?128:transfer_remaining;
end
assign enough_data = m_writefifo_fill >= burst_size;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
m_write_write <= 0;
else if (~m_write_waitrequest_out)
m_write_write <= write_go_reg & ((|burst_counter & sink_stream_really_valid) | m_write_write_sig);
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
m_write_burstcount <= 0;
else if (~m_write_waitrequest_out)
if (~|burst_counter)
if (enough_data)
m_write_burstcount <= burst_size;
else if (eop_found_hold)
m_write_burstcount <= m_writefifo_fill;
end
//command input
assign start_address = write_command_data_reg[31 : 0];
assign bytes_to_transfer = write_command_data_reg[47 : 32];
assign increment_address = write_command_data_reg[56];
//increment or keep constant, the m_write_address depending on the command bit
assign m_write_writedata = m_write_writedata_reg;
assign increment = write_go_reg & sink_stream_really_valid;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
m_write_writedata_reg <= 0;
else if (~m_write_waitrequest_out)
m_write_writedata_reg <= sink_stream_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
m_write_write_sig <= 0;
else if (m_write_waitrequest_out)
m_write_write_sig <= sink_stream_really_valid & ~m_write_write;
end
assign m_write_burstcount_right_shifted = {m_write_burstcount, 3'b0};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
m_write_address <= 0;
else if (~m_write_waitrequest_out & ~|burst_counter)
m_write_address <= delayed_write_command_valid ? start_address : (increment_address ? (m_write_write ? (m_write_address + m_write_burstcount_right_shifted) : m_write_address) : start_address);
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
eop_found_hold <= 0;
else if (write_go_reg)
eop_found_hold <= eop_found_hold ? ~(sink_stream_endofpacket & sink_stream_really_valid) : eop_found;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
burst_counter_reg <= 0;
else if (~m_write_waitrequest_out)
burst_counter_reg <= burst_counter;
end
assign burst_counter_decrement = |burst_counter & write_go_reg & sink_stream_really_valid;
assign burst_counter_next = burst_counter - 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
burst_counter <= 0;
else if (~|burst_counter & ~|burst_counter_reg & write_go_reg)
begin
if (enough_data)
burst_counter <= burst_size;
else if (eop_found_hold)
burst_counter <= m_writefifo_fill;
end
else if (~m_write_waitrequest_out)
if (burst_counter_decrement)
burst_counter <= burst_counter_next;
end
assign shift7 = {7'b0, all_one[0]};
assign shift6 = {6'b0, all_one[1 : 0]};
assign shift5 = {5'b0, all_one[2 : 0]};
assign shift4 = {4'b0, all_one[3 : 0]};
assign shift3 = {3'b0, all_one[4 : 0]};
assign shift2 = {2'b0, all_one[5 : 0]};
assign shift1 = {1'b0, all_one[6 : 0]};
assign shift0 = all_one;
assign sink_stream_empty_shift = ((sink_stream_empty == 7) ? shift7 : 0) | ((sink_stream_empty == 6) ? shift6 : 0) | ((sink_stream_empty == 5) ? shift5 : 0) | ((sink_stream_empty == 4) ? shift4 : 0) | ((sink_stream_empty == 3) ? shift3 : 0) | ((sink_stream_empty == 2) ? shift2 : 0) | ((sink_stream_empty == 1) ? shift1 : 0) | ((sink_stream_empty == 0) ? shift0 : 0);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
m_write_byteenable_reg <= 0;
else if (~m_write_waitrequest_out)
m_write_byteenable_reg <= ((sink_stream_empty == 7) ? shift7 : 0) | ((sink_stream_empty == 6) ? shift6 : 0) | ((sink_stream_empty == 5) ? shift5 : 0) | ((sink_stream_empty == 4) ? shift4 : 0) | ((sink_stream_empty == 3) ? shift3 : 0) | ((sink_stream_empty == 2) ? shift2 : 0) | ((sink_stream_empty == 1) ? shift1 : 0) | ((sink_stream_empty == 0) ? shift0 : 0);
end
assign all_one = 8'b11111111;
assign m_write_byteenable_in = byteenable_enable ? m_write_byteenable_reg : all_one;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
byteenable_enable <= 0;
else if (~m_write_waitrequest_out)
byteenable_enable <= sink_stream_endofpacket;
end
assign sink_stream_ready = write_go_reg & ~m_write_waitrequest_out & ~eop_reg & |burst_counter;
//sink_stream_ready_sig
//sink_stream_valid is only really valid when we're ready
assign sink_stream_really_valid = sink_stream_valid && sink_stream_ready;
//write_command_data_reg
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
write_command_data_reg <= 0;
else if (write_command_valid)
write_command_data_reg <= write_command_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_write_command_valid <= 0;
else
delayed_write_command_valid <= write_command_valid;
end
//8-bits up-counter
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter <= 0;
else if (~m_write_waitrequest_out)
counter <= counter_in;
end
//write_go bit for all of this operation until count is up
assign write_go_reg_in = (delayed_write_command_valid) ? 1'b1 : (counter >= bytes_to_transfer) ? 1'b0 : write_go_reg;
assign write_go_reg_in_teop = eop_reg ? ~(m_write_write & ~m_write_waitrequest_out) : 1'b1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
eop_reg <= 0;
else
eop_reg <= eop_reg ? ~(m_write_write & ~m_write_waitrequest_out) : sink_stream_endofpacket & sink_stream_really_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
write_go_reg <= 0;
else if (~m_write_waitrequest_out)
write_go_reg <= (write_go_reg && (bytes_to_transfer == 0)) ? write_go_reg_in_teop : write_go_reg_in;
end
assign write_go = write_go_reg;
assign t_eop = (sink_stream_endofpacket && sink_stream_really_valid) && (bytes_to_transfer == 0);
assign single_transfer = sink_stream_startofpacket & sink_stream_endofpacket;
assign counter_in = (delayed_write_command_valid) ? 16'b0 : (increment ? (counter + 8 - (sink_stream_endofpacket ? sink_stream_empty : 0)) : counter);
//status register
assign status_reg_in = write_go_fall_reg ? 0 : (status_word | status_reg);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
status_reg <= 0;
else
status_reg <= status_reg_in;
end
//actual_bytes_transferred register
assign actual_bytes_transferred = counter;
//status_token consists of the status signals and actual_bytes_transferred
assign status_token_fifo_data = {status_reg, actual_bytes_transferred};
assign status_word = {t_eop, 7'b0};
//delayed write go register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_write_go <= 0;
else
delayed_write_go <= write_go_reg;
end
//write_go falling edge detector
assign write_go_fall_reg_in = delayed_write_go && ~write_go_reg;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
write_go_fall_reg <= 0;
else
write_go_fall_reg <= write_go_fall_reg_in;
end
assign status_token_fifo_wrreq = write_go_fall_reg && ~status_token_fifo_full;
assign m_write_waitrequest_out = m_write_waitrequest;
assign m_write_byteenable = m_write_byteenable_in;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module amm_master_qsys_with_pcie_sgdma_command_fifo (
// inputs:
clk,
command_fifo_data,
command_fifo_rdreq,
command_fifo_wrreq,
reset,
// outputs:
command_fifo_empty,
command_fifo_full,
command_fifo_q
)
;
output command_fifo_empty;
output command_fifo_full;
output [103: 0] command_fifo_q;
input clk;
input [103: 0] command_fifo_data;
input command_fifo_rdreq;
input command_fifo_wrreq;
input reset;
wire command_fifo_empty;
wire command_fifo_full;
wire [103: 0] command_fifo_q;
scfifo amm_master_qsys_with_pcie_sgdma_command_fifo_command_fifo
(
.aclr (reset),
.clock (clk),
.data (command_fifo_data),
.empty (command_fifo_empty),
.full (command_fifo_full),
.q (command_fifo_q),
.rdreq (command_fifo_rdreq),
.wrreq (command_fifo_wrreq)
);
defparam amm_master_qsys_with_pcie_sgdma_command_fifo_command_fifo.add_ram_output_register = "ON",
amm_master_qsys_with_pcie_sgdma_command_fifo_command_fifo.intended_device_family = "CYCLONEIVGX",
amm_master_qsys_with_pcie_sgdma_command_fifo_command_fifo.lpm_numwords = 2,
amm_master_qsys_with_pcie_sgdma_command_fifo_command_fifo.lpm_showahead = "OFF",
amm_master_qsys_with_pcie_sgdma_command_fifo_command_fifo.lpm_type = "scfifo",
amm_master_qsys_with_pcie_sgdma_command_fifo_command_fifo.lpm_width = 104,
amm_master_qsys_with_pcie_sgdma_command_fifo_command_fifo.lpm_widthu = 1,
amm_master_qsys_with_pcie_sgdma_command_fifo_command_fifo.overflow_checking = "ON",
amm_master_qsys_with_pcie_sgdma_command_fifo_command_fifo.underflow_checking = "ON",
amm_master_qsys_with_pcie_sgdma_command_fifo_command_fifo.use_eab = "ON";
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module amm_master_qsys_with_pcie_sgdma_desc_address_fifo (
// inputs:
clk,
desc_address_fifo_data,
desc_address_fifo_rdreq,
desc_address_fifo_wrreq,
reset,
// outputs:
desc_address_fifo_empty,
desc_address_fifo_full,
desc_address_fifo_q
)
;
output desc_address_fifo_empty;
output desc_address_fifo_full;
output [ 31: 0] desc_address_fifo_q;
input clk;
input [ 31: 0] desc_address_fifo_data;
input desc_address_fifo_rdreq;
input desc_address_fifo_wrreq;
input reset;
wire desc_address_fifo_empty;
wire desc_address_fifo_full;
wire [ 31: 0] desc_address_fifo_q;
scfifo amm_master_qsys_with_pcie_sgdma_desc_address_fifo_desc_address_fifo
(
.aclr (reset),
.clock (clk),
.data (desc_address_fifo_data),
.empty (desc_address_fifo_empty),
.full (desc_address_fifo_full),
.q (desc_address_fifo_q),
.rdreq (desc_address_fifo_rdreq),
.wrreq (desc_address_fifo_wrreq)
);
defparam amm_master_qsys_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.add_ram_output_register = "ON",
amm_master_qsys_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.intended_device_family = "CYCLONEIVGX",
amm_master_qsys_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.lpm_numwords = 2,
amm_master_qsys_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.lpm_showahead = "OFF",
amm_master_qsys_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.lpm_type = "scfifo",
amm_master_qsys_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.lpm_width = 32,
amm_master_qsys_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.lpm_widthu = 1,
amm_master_qsys_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.overflow_checking = "ON",
amm_master_qsys_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.underflow_checking = "ON",
amm_master_qsys_with_pcie_sgdma_desc_address_fifo_desc_address_fifo.use_eab = "OFF";
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module amm_master_qsys_with_pcie_sgdma_status_token_fifo (
// inputs:
clk,
reset,
status_token_fifo_data,
status_token_fifo_rdreq,
status_token_fifo_wrreq,
// outputs:
status_token_fifo_empty,
status_token_fifo_full,
status_token_fifo_q
)
;
output status_token_fifo_empty;
output status_token_fifo_full;
output [ 23: 0] status_token_fifo_q;
input clk;
input reset;
input [ 23: 0] status_token_fifo_data;
input status_token_fifo_rdreq;
input status_token_fifo_wrreq;
wire status_token_fifo_empty;
wire status_token_fifo_full;
wire [ 23: 0] status_token_fifo_q;
scfifo amm_master_qsys_with_pcie_sgdma_status_token_fifo_status_token_fifo
(
.aclr (reset),
.clock (clk),
.data (status_token_fifo_data),
.empty (status_token_fifo_empty),
.full (status_token_fifo_full),
.q (status_token_fifo_q),
.rdreq (status_token_fifo_rdreq),
.wrreq (status_token_fifo_wrreq)
);
defparam amm_master_qsys_with_pcie_sgdma_status_token_fifo_status_token_fifo.add_ram_output_register = "ON",
amm_master_qsys_with_pcie_sgdma_status_token_fifo_status_token_fifo.intended_device_family = "CYCLONEIVGX",
amm_master_qsys_with_pcie_sgdma_status_token_fifo_status_token_fifo.lpm_numwords = 2,
amm_master_qsys_with_pcie_sgdma_status_token_fifo_status_token_fifo.lpm_showahead = "OFF",
amm_master_qsys_with_pcie_sgdma_status_token_fifo_status_token_fifo.lpm_type = "scfifo",
amm_master_qsys_with_pcie_sgdma_status_token_fifo_status_token_fifo.lpm_width = 24,
amm_master_qsys_with_pcie_sgdma_status_token_fifo_status_token_fifo.lpm_widthu = 1,
amm_master_qsys_with_pcie_sgdma_status_token_fifo_status_token_fifo.overflow_checking = "ON",
amm_master_qsys_with_pcie_sgdma_status_token_fifo_status_token_fifo.underflow_checking = "ON",
amm_master_qsys_with_pcie_sgdma_status_token_fifo_status_token_fifo.use_eab = "ON";
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module amm_master_qsys_with_pcie_sgdma (
// inputs:
clk,
csr_address,
csr_chipselect,
csr_read,
csr_write,
csr_writedata,
descriptor_read_readdata,
descriptor_read_readdatavalid,
descriptor_read_waitrequest,
descriptor_write_waitrequest,
m_read_readdata,
m_read_readdatavalid,
m_read_waitrequest,
m_write_waitrequest,
system_reset_n,
// outputs:
csr_irq,
csr_readdata,
descriptor_read_address,
descriptor_read_read,
descriptor_write_address,
descriptor_write_write,
descriptor_write_writedata,
m_read_address,
m_read_burstcount,
m_read_read,
m_write_address,
m_write_burstcount,
m_write_byteenable,
m_write_write,
m_write_writedata
)
;
output csr_irq;
output [ 31: 0] csr_readdata;
output [ 31: 0] descriptor_read_address;
output descriptor_read_read;
output [ 31: 0] descriptor_write_address;
output descriptor_write_write;
output [ 31: 0] descriptor_write_writedata;
output [ 31: 0] m_read_address;
output [ 3: 0] m_read_burstcount;
output m_read_read;
output [ 31: 0] m_write_address;
output [ 7: 0] m_write_burstcount;
output [ 7: 0] m_write_byteenable;
output m_write_write;
output [ 63: 0] m_write_writedata;
input clk;
input [ 3: 0] csr_address;
input csr_chipselect;
input csr_read;
input csr_write;
input [ 31: 0] csr_writedata;
input [ 31: 0] descriptor_read_readdata;
input descriptor_read_readdatavalid;
input descriptor_read_waitrequest;
input descriptor_write_waitrequest;
input [ 63: 0] m_read_readdata;
input m_read_readdatavalid;
input m_read_waitrequest;
input m_write_waitrequest;
input system_reset_n;
wire [103: 0] command_fifo_data;
wire command_fifo_empty;
wire command_fifo_full;
wire [103: 0] command_fifo_q;
wire command_fifo_rdreq;
wire command_fifo_wrreq;
wire csr_irq;
wire [ 31: 0] csr_readdata;
wire [ 63: 0] data_to_fifo;
wire [ 31: 0] desc_address_fifo_data;
wire desc_address_fifo_empty;
wire desc_address_fifo_full;
wire [ 31: 0] desc_address_fifo_q;
wire desc_address_fifo_rdreq;
wire desc_address_fifo_wrreq;
wire [ 31: 0] descriptor_read_address;
wire descriptor_read_read;
wire [ 31: 0] descriptor_write_address;
wire descriptor_write_write;
wire [ 31: 0] descriptor_write_writedata;
wire e_00;
wire e_01;
wire e_02;
wire e_03;
wire e_04;
wire e_05;
wire e_06;
wire [ 2: 0] empty_to_fifo;
wire eop_found;
wire eop_to_fifo;
wire [ 31: 0] m_read_address;
wire [ 3: 0] m_read_burstcount;
wire m_read_read;
wire [ 4: 0] m_readfifo_usedw;
wire [ 31: 0] m_write_address;
wire [ 7: 0] m_write_burstcount;
wire [ 7: 0] m_write_byteenable;
wire m_write_write;
wire [ 63: 0] m_write_writedata;
wire [ 8: 0] m_writefifo_fill;
wire [ 58: 0] read_command_data;
wire read_command_valid;
wire read_go;
wire ready_from_fifo;
wire reset;
reg reset_n;
wire [ 63: 0] sink_stream_data;
wire [ 2: 0] sink_stream_empty;
wire sink_stream_endofpacket;
wire sink_stream_ready;
wire sink_stream_startofpacket;
wire sink_stream_valid;
wire sop_to_fifo;
wire [ 63: 0] source_stream_data;
wire [ 2: 0] source_stream_empty;
wire source_stream_endofpacket;
wire source_stream_ready;
wire source_stream_startofpacket;
wire source_stream_valid;
wire [ 23: 0] status_token_fifo_data;
wire status_token_fifo_empty;
wire status_token_fifo_full;
wire [ 23: 0] status_token_fifo_q;
wire status_token_fifo_rdreq;
wire status_token_fifo_wrreq;
wire sw_reset;
reg sw_reset_d1;
reg sw_reset_request;
wire valid_to_fifo;
wire [ 56: 0] write_command_data;
wire write_command_valid;
wire [ 63: 0] write_fifo_out_data;
wire [ 2: 0] write_fifo_out_empty;
wire write_fifo_out_endofpacket;
wire write_fifo_out_ready;
wire write_fifo_out_startofpacket;
wire write_fifo_out_valid;
wire write_go;
always @(posedge clk or negedge system_reset_n)
begin
if (system_reset_n == 0)
reset_n <= 0;
else
reset_n <= ~(~system_reset_n | sw_reset_request);
end
always @(posedge clk or negedge system_reset_n)
begin
if (system_reset_n == 0)
sw_reset_d1 <= 0;
else if (sw_reset | sw_reset_request)
sw_reset_d1 <= sw_reset & ~sw_reset_request;
end
always @(posedge clk or negedge system_reset_n)
begin
if (system_reset_n == 0)
sw_reset_request <= 0;
else if (sw_reset | sw_reset_request)
sw_reset_request <= sw_reset_d1 & ~sw_reset_request;
end
assign reset = ~reset_n;
amm_master_qsys_with_pcie_sgdma_chain the_amm_master_qsys_with_pcie_sgdma_chain
(
.clk (clk),
.command_fifo_data (command_fifo_data),
.command_fifo_empty (command_fifo_empty),
.command_fifo_full (command_fifo_full),
.command_fifo_wrreq (command_fifo_wrreq),
.csr_address (csr_address),
.csr_chipselect (csr_chipselect),
.csr_irq (csr_irq),
.csr_read (csr_read),
.csr_readdata (csr_readdata),
.csr_write (csr_write),
.csr_writedata (csr_writedata),
.desc_address_fifo_data (desc_address_fifo_data),
.desc_address_fifo_empty (desc_address_fifo_empty),
.desc_address_fifo_full (desc_address_fifo_full),
.desc_address_fifo_q (desc_address_fifo_q),
.desc_address_fifo_rdreq (desc_address_fifo_rdreq),
.desc_address_fifo_wrreq (desc_address_fifo_wrreq),
.descriptor_read_address (descriptor_read_address),
.descriptor_read_read (descriptor_read_read),
.descriptor_read_readdata (descriptor_read_readdata),
.descriptor_read_readdatavalid (descriptor_read_readdatavalid),
.descriptor_read_waitrequest (descriptor_read_waitrequest & descriptor_read_read),
.descriptor_write_address (descriptor_write_address),
.descriptor_write_waitrequest (descriptor_write_waitrequest & descriptor_write_write),
.descriptor_write_write (descriptor_write_write),
.descriptor_write_writedata (descriptor_write_writedata),
.read_go (read_go),
.reset (reset),
.reset_n (reset_n),
.status_token_fifo_data (status_token_fifo_data),
.status_token_fifo_empty (status_token_fifo_empty),
.status_token_fifo_q (status_token_fifo_q),
.status_token_fifo_rdreq (status_token_fifo_rdreq),
.sw_reset (sw_reset),
.write_go (write_go)
);
amm_master_qsys_with_pcie_sgdma_command_grabber the_amm_master_qsys_with_pcie_sgdma_command_grabber
(
.clk (clk),
.command_fifo_empty (command_fifo_empty),
.command_fifo_q (command_fifo_q),
.command_fifo_rdreq (command_fifo_rdreq),
.m_read_waitrequest (m_read_waitrequest & m_read_read),
.m_write_waitrequest (m_write_waitrequest & m_write_write),
.read_command_data (read_command_data),
.read_command_valid (read_command_valid),
.read_go (read_go),
.reset_n (reset_n),
.write_command_data (write_command_data),
.write_command_valid (write_command_valid),
.write_go (write_go)
);
amm_master_qsys_with_pcie_sgdma_m_read the_amm_master_qsys_with_pcie_sgdma_m_read
(
.clk (clk),
.m_read_address (m_read_address),
.m_read_burstcount (m_read_burstcount),
.m_read_read (m_read_read),
.m_read_readdata (m_read_readdata),
.m_read_readdatavalid (m_read_readdatavalid),
.m_read_waitrequest (m_read_waitrequest & m_read_read),
.m_readfifo_usedw (m_readfifo_usedw),
.read_command_data (read_command_data),
.read_command_valid (read_command_valid),
.read_go (read_go),
.reset_n (reset_n),
.source_stream_data (data_to_fifo),
.source_stream_empty (empty_to_fifo),
.source_stream_endofpacket (eop_to_fifo),
.source_stream_ready (ready_from_fifo),
.source_stream_startofpacket (sop_to_fifo),
.source_stream_valid (valid_to_fifo)
);
amm_master_qsys_with_pcie_sgdma_m_readfifo the_amm_master_qsys_with_pcie_sgdma_m_readfifo
(
.clk (clk),
.m_readfifo_usedw (m_readfifo_usedw),
.reset (reset),
.reset_n (reset_n),
.sink_stream_data (data_to_fifo),
.sink_stream_empty (empty_to_fifo),
.sink_stream_endofpacket (eop_to_fifo),
.sink_stream_ready (ready_from_fifo),
.sink_stream_startofpacket (sop_to_fifo),
.sink_stream_valid (valid_to_fifo),
.source_stream_data (source_stream_data),
.source_stream_empty (source_stream_empty),
.source_stream_endofpacket (source_stream_endofpacket),
.source_stream_ready (source_stream_ready),
.source_stream_startofpacket (source_stream_startofpacket),
.source_stream_valid (source_stream_valid)
);
amm_master_qsys_with_pcie_sgdma_m_writefifo the_amm_master_qsys_with_pcie_sgdma_m_writefifo
(
.clk (clk),
.eop_found (eop_found),
.m_writefifo_fill (m_writefifo_fill),
.reset (reset),
.reset_n (reset_n),
.sink_stream_data (sink_stream_data),
.sink_stream_empty (sink_stream_empty),
.sink_stream_endofpacket (sink_stream_endofpacket),
.sink_stream_ready (sink_stream_ready),
.sink_stream_startofpacket (sink_stream_startofpacket),
.sink_stream_valid (sink_stream_valid),
.source_stream_data (write_fifo_out_data),
.source_stream_empty (write_fifo_out_empty),
.source_stream_endofpacket (write_fifo_out_endofpacket),
.source_stream_ready (write_fifo_out_ready),
.source_stream_startofpacket (write_fifo_out_startofpacket),
.source_stream_valid (write_fifo_out_valid)
);
amm_master_qsys_with_pcie_sgdma_m_write the_amm_master_qsys_with_pcie_sgdma_m_write
(
.clk (clk),
.e_00 (e_00),
.e_01 (e_01),
.e_02 (e_02),
.e_03 (e_03),
.e_04 (e_04),
.e_05 (e_05),
.e_06 (e_06),
.eop_found (eop_found),
.m_write_address (m_write_address),
.m_write_burstcount (m_write_burstcount),
.m_write_byteenable (m_write_byteenable),
.m_write_waitrequest (m_write_waitrequest & m_write_write),
.m_write_write (m_write_write),
.m_write_writedata (m_write_writedata),
.m_writefifo_fill (m_writefifo_fill),
.reset_n (reset_n),
.sink_stream_data (write_fifo_out_data),
.sink_stream_empty (write_fifo_out_empty),
.sink_stream_endofpacket (write_fifo_out_endofpacket),
.sink_stream_ready (write_fifo_out_ready),
.sink_stream_startofpacket (write_fifo_out_startofpacket),
.sink_stream_valid (write_fifo_out_valid),
.status_token_fifo_data (status_token_fifo_data),
.status_token_fifo_full (status_token_fifo_full),
.status_token_fifo_wrreq (status_token_fifo_wrreq),
.write_command_data (write_command_data),
.write_command_valid (write_command_valid),
.write_go (write_go)
);
//the_amm_master_qsys_with_pcie_sgdma_command_fifo, which is an e_instance
amm_master_qsys_with_pcie_sgdma_command_fifo the_amm_master_qsys_with_pcie_sgdma_command_fifo
(
.clk (clk),
.command_fifo_data (command_fifo_data),
.command_fifo_empty (command_fifo_empty),
.command_fifo_full (command_fifo_full),
.command_fifo_q (command_fifo_q),
.command_fifo_rdreq (command_fifo_rdreq),
.command_fifo_wrreq (command_fifo_wrreq),
.reset (reset)
);
//the_amm_master_qsys_with_pcie_sgdma_desc_address_fifo, which is an e_instance
amm_master_qsys_with_pcie_sgdma_desc_address_fifo the_amm_master_qsys_with_pcie_sgdma_desc_address_fifo
(
.clk (clk),
.desc_address_fifo_data (desc_address_fifo_data),
.desc_address_fifo_empty (desc_address_fifo_empty),
.desc_address_fifo_full (desc_address_fifo_full),
.desc_address_fifo_q (desc_address_fifo_q),
.desc_address_fifo_rdreq (desc_address_fifo_rdreq),
.desc_address_fifo_wrreq (desc_address_fifo_wrreq),
.reset (reset)
);
//the_amm_master_qsys_with_pcie_sgdma_status_token_fifo, which is an e_instance
amm_master_qsys_with_pcie_sgdma_status_token_fifo the_amm_master_qsys_with_pcie_sgdma_status_token_fifo
(
.clk (clk),
.reset (reset),
.status_token_fifo_data (status_token_fifo_data),
.status_token_fifo_empty (status_token_fifo_empty),
.status_token_fifo_full (status_token_fifo_full),
.status_token_fifo_q (status_token_fifo_q),
.status_token_fifo_rdreq (status_token_fifo_rdreq),
.status_token_fifo_wrreq (status_token_fifo_wrreq)
);
//descriptor_read, which is an e_avalon_master
//descriptor_write, which is an e_avalon_master
//csr, which is an e_avalon_slave
//m_read, which is an e_avalon_master
//m_write, which is an e_avalon_master
assign sink_stream_valid = source_stream_valid;
assign sink_stream_data = source_stream_data;
assign sink_stream_startofpacket = source_stream_startofpacket;
assign sink_stream_endofpacket = source_stream_endofpacket;
assign source_stream_ready = sink_stream_ready;
assign sink_stream_empty = source_stream_empty;
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_11_0_pcie_bram_top_7x.v
// Version : 1.11
// Description : bram wrapper for Tx and Rx
// given the pcie block attributes calculate the number of brams
// and pipeline stages and instantiate the brams
//
// Hierarchy:
// pcie_bram_top top level
// pcie_brams pcie_bram instantiations,
// pipeline stages (if any),
// address decode logic (if any),
// datapath muxing (if any)
// pcie_bram bram library cell wrapper
// the pcie_bram module can have a paramter that
// specifies the family (V6, V5, V4)
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
module pcie_7x_v1_11_0_pcie_bram_top_7x
#(
parameter IMPL_TARGET = "HARD", // the implementation target : HARD, SOFT
parameter DEV_CAP_MAX_PAYLOAD_SUPPORTED = 0, // MPS Supported : 0 - 128 B, 1 - 256 B, 2 - 512 B, 3 - 1024 B
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1, // PCIe Link Speed : 1 - 2.5 GT/s; 2 - 5.0 GT/s
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08, // PCIe Link Width : 1 / 2 / 4 / 8
parameter VC0_TX_LASTPACKET = 31, // Number of Packets in Transmit
parameter TLM_TX_OVERHEAD = 24, // Overhead Bytes for Packets (Transmit)
parameter TL_TX_RAM_RADDR_LATENCY = 1, // BRAM Read Address Latency (Transmit)
parameter TL_TX_RAM_RDATA_LATENCY = 2, // BRAM Read Data Latency (Transmit)
parameter TL_TX_RAM_WRITE_LATENCY = 1, // BRAM Write Latency (Transmit)
parameter VC0_RX_RAM_LIMIT = 'h1FFF, // RAM Size (Receive)
parameter TL_RX_RAM_RADDR_LATENCY = 1, // BRAM Read Address Latency (Receive)
parameter TL_RX_RAM_RDATA_LATENCY = 2, // BRAM Read Data Latency (Receive)
parameter TL_RX_RAM_WRITE_LATENCY = 1 // BRAM Write Latency (Receive)
)
(
input user_clk_i, // Clock input
input reset_i, // Reset input
input mim_tx_wen, // Write Enable for Transmit path BRAM
input [12:0] mim_tx_waddr, // Write Address for Transmit path BRAM
input [71:0] mim_tx_wdata, // Write Data for Transmit path BRAM
input mim_tx_ren, // Read Enable for Transmit path BRAM
input mim_tx_rce, // Read Output Register Clock Enable for Transmit path BRAM
input [12:0] mim_tx_raddr, // Read Address for Transmit path BRAM
output [71:0] mim_tx_rdata, // Read Data for Transmit path BRAM
input mim_rx_wen, // Write Enable for Receive path BRAM
input [12:0] mim_rx_waddr, // Write Enable for Receive path BRAM
input [71:0] mim_rx_wdata, // Write Enable for Receive path BRAM
input mim_rx_ren, // Read Enable for Receive path BRAM
input mim_rx_rce, // Read Output Register Clock Enable for Receive path BRAM
input [12:0] mim_rx_raddr, // Read Address for Receive path BRAM
output [71:0] mim_rx_rdata // Read Data for Receive path BRAM
);
// TX calculations
localparam MPS_BYTES = ((DEV_CAP_MAX_PAYLOAD_SUPPORTED == 0) ? 128 :
(DEV_CAP_MAX_PAYLOAD_SUPPORTED == 1) ? 256 :
(DEV_CAP_MAX_PAYLOAD_SUPPORTED == 2) ? 512 :
1024 );
localparam BYTES_TX = (VC0_TX_LASTPACKET + 1) * (MPS_BYTES + TLM_TX_OVERHEAD);
localparam ROWS_TX = 1;
localparam COLS_TX = ((BYTES_TX <= 4096) ? 1 :
(BYTES_TX <= 8192) ? 2 :
(BYTES_TX <= 16384) ? 4 :
(BYTES_TX <= 32768) ? 8 :
18
);
// RX calculations
localparam ROWS_RX = 1;
localparam COLS_RX = ((VC0_RX_RAM_LIMIT < 'h0200) ? 1 :
(VC0_RX_RAM_LIMIT < 'h0400) ? 2 :
(VC0_RX_RAM_LIMIT < 'h0800) ? 4 :
(VC0_RX_RAM_LIMIT < 'h1000) ? 8 :
18
);
initial begin
$display("[%t] %m ROWS_TX %0d COLS_TX %0d", $time, ROWS_TX, COLS_TX);
$display("[%t] %m ROWS_RX %0d COLS_RX %0d", $time, ROWS_RX, COLS_RX);
end
pcie_7x_v1_11_0_pcie_brams_7x #(
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ),
.IMPL_TARGET ( IMPL_TARGET ),
.NUM_BRAMS ( COLS_TX ),
.RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ),
.RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ),
.RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY )
)
pcie_brams_tx (
.user_clk_i ( user_clk_i ),
.reset_i ( reset_i ),
.waddr ( mim_tx_waddr ),
.wen ( mim_tx_wen ),
.ren ( mim_tx_ren ),
.rce ( mim_tx_rce ),
.wdata ( mim_tx_wdata ),
.raddr ( mim_tx_raddr ),
.rdata ( mim_tx_rdata )
);
pcie_7x_v1_11_0_pcie_brams_7x #(
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ),
.IMPL_TARGET ( IMPL_TARGET ),
.NUM_BRAMS ( COLS_RX ),
.RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ),
.RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ),
.RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY )
) pcie_brams_rx (
.user_clk_i ( user_clk_i ),
.reset_i ( reset_i ),
.waddr ( mim_rx_waddr ),
.wen ( mim_rx_wen ),
.ren ( mim_rx_ren ),
.rce ( mim_rx_rce ),
.wdata ( mim_rx_wdata ),
.raddr ( mim_rx_raddr ),
.rdata ( mim_rx_rdata )
);
endmodule // pcie_bram_top
|
`include "constants.vh"
`include "alu_ops.vh"
`include "rv32_opcodes.vh"
`default_nettype none
module exunit_branch
(
input wire clk,
input wire reset,
input wire [`DATA_LEN-1:0] ex_src1,
input wire [`DATA_LEN-1:0] ex_src2,
input wire [`ADDR_LEN-1:0] pc,
input wire [`DATA_LEN-1:0] imm,
input wire dstval,
input wire [`ALU_OP_WIDTH-1:0] alu_op,
input wire [`SPECTAG_LEN-1:0] spectag,
input wire specbit,
input wire [`ADDR_LEN-1:0] praddr,
input wire [6:0] opcode,
input wire issue,
output wire [`DATA_LEN-1:0] result,
output wire rrf_we,
output wire rob_we, //set finish
output wire prsuccess,
output wire prmiss,
output wire [`ADDR_LEN-1:0] jmpaddr,
output wire [`ADDR_LEN-1:0] jmpaddr_taken,
output wire brcond,
output wire [`SPECTAG_LEN-1:0] tagregfix
);
reg busy;
wire [`DATA_LEN-1:0] comprslt;
wire addrmatch = (jmpaddr == praddr) ? 1'b1 : 1'b0;
assign rob_we = busy;
assign rrf_we = busy & dstval;
assign result = pc + 4;
assign prsuccess = busy & addrmatch;
assign prmiss = busy & ~addrmatch;
assign jmpaddr = brcond ? jmpaddr_taken : (pc + 4);
assign jmpaddr_taken = (((opcode == `RV32_JALR) ? ex_src1 : pc) + imm);
assign brcond = ((opcode == `RV32_JAL) || (opcode == `RV32_JALR)) ?
1'b1 : comprslt[0];
assign tagregfix = {spectag[0], spectag[`SPECTAG_LEN-1:1]};
always @ (posedge clk) begin
if (reset) begin
busy <= 0;
end else begin
busy <= issue;
end
end
alu comparator
(
.op(alu_op),
.in1(ex_src1),
.in2(ex_src2),
.out(comprslt)
);
endmodule // exunit_branch
`default_nettype wire
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKINV_4_V
`define SKY130_FD_SC_HS__CLKINV_4_V
/**
* clkinv: Clock tree inverter.
*
* Verilog wrapper for clkinv with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__clkinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__clkinv_4 (
Y ,
A ,
VPWR,
VGND
);
output Y ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__clkinv_4 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__clkinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKINV_4_V
|
`default_nettype none
`timescale 1ns / 1ps
module oled_spi(
input wire clock,
input wire reset,
input wire shutdown,
output wire cs,
output reg sdin,
output wire sclk,
output reg dc,
output reg res,
output reg vbatc,
output reg vddc
);
parameter WAIT = 1;
parameter SEND = 2; // send 1 byte
parameter SEND2 = 3; // send 2 bytes
parameter SEND3 = 4; // send 3 bytes
parameter SEND4 = 5; // send 4 bytes
parameter STARTUP_1 = 10;
parameter STARTUP_2 = 11;
parameter STARTUP_3 = 12;
parameter STARTUP_4 = 13;
parameter STARTUP_5 = 14;
parameter STARTUP_6 = 15;
parameter STARTUP_7 = 16;
parameter STARTUP_8 = 17;
parameter STARTUP_9 = 18;
parameter SHUTDOWN_1 = 6;
parameter SHUTDOWN_2 = 7;
parameter SHUTDOWN_3 = 8;
reg [31:0] send_buf;
reg [4:0] send_idx;
reg [1:0] send_ctr;
reg [1:0] send_max;
reg [31:0] wait_ctr;
reg [31:0] wait_max;
// TODO probably don't need 7 bits for state
reg [7:0] state;
reg [7:0] next_state;
always @(posedge clock) begin
// RESET
if (reset) begin
send_buf <= 32'b0;
send_idx <= 5'b0;
send_ctr <= 2'b0;
send_max <= 2'b0;
wait_ctr <= 32'b0;
wait_max <= 32'b0;
state <= STARTUP_1;
next_state <= 1'b0;
sdin <= 1'b0;
dc <= 1'b0;
res <= 1'b1;
vddc <= 1'b1;
vbatc <= 1'b1;
end
// SHUTDOWN
else if (shutdown) begin
if (state > 0 && state < 10) begin
next_state <= SHUTDOWN_1;
end else begin
state <= SHUTDOWN_1;
end
end
// STATES
else begin
// SEND - send up to four serial bytes
if (state == SEND) begin
sdin <= send_buf[(7 - send_idx) + (8 * send_ctr)];
if (send_idx == 7 && send_ctr == send_max) begin
send_idx <= 0;
send_ctr <= 0;
send_max <= 0;
state <= next_state;
end else if (send_idx == 7) begin
send_idx <= 0;
send_ctr <= send_ctr + 1;
end else begin
send_idx <= send_idx + 1;
end
end
// SEND2 - send two bytes
if (state == SEND2) begin
send_max = 1;
state <= SEND;
end
// SEND3 - send three bytes
else if (state == SEND3) begin
send_max = 2;
state <= SEND;
end
// SEND4 - send four bytes
else if (state == SEND4) begin
send_max = 3;
state <= SEND;
end
// WAIT - wait for # of cycles
else if (state == WAIT) begin
if (wait_ctr == wait_max) begin
wait_ctr <= 0;
state <= next_state;
end else begin
wait_ctr <= wait_ctr + 1;
end
end
// STARTUP_1 -- apply power to VDD
else if (state == STARTUP_1) begin
dc <= 0;
vddc <= 0;
wait_max <= 5000; // 1ms
state <= WAIT;
next_state <= STARTUP_2;
end
// STARTUP_2 -- send display off cmd
else if (state == STARTUP_2) begin
send_buf <= 8'hAE;
state <= SEND;
next_state <= STARTUP_3;
end
// STARTUP_3 -- clear screen
else if (state == STARTUP_3) begin
res <= 0;
wait_max <= 5000; // 1ms
state <= WAIT;
next_state <= STARTUP_4;
end
// STARTUP_4 -- set charge pump
else if (state == STARTUP_4) begin
res <= 1;
send_buf <= 16'h148D;
state <= SEND2;
next_state <= STARTUP_5;
end
// STARTUP_5 -- set pre-charge period
else if (state == STARTUP_5) begin
send_buf <= 16'hF1D9;
state <= SEND2;
next_state <= STARTUP_6;
end
// STARTUP_6 -- apply power to VBAT
else if (state == STARTUP_6) begin
vbatc <= 0;
wait_max <= 500000; // 100ms
state <= WAIT;
next_state <= STARTUP_7;
end
// STARTUP_7 -- invert the display
else if (state == STARTUP_7) begin
send_buf <= 16'hC8A1;
state <= SEND2;
next_state <= STARTUP_8;
end
// STARTUP_8 -- select squential COM configuration
else if (state == STARTUP_8) begin
send_buf <= 16'h20DA;
state <= SEND2;
next_state <= STARTUP_9;
end
// STARTUP_9 -- send display on cmd
else if (state == STARTUP_9) begin
send_buf <= 8'hAF;
state <= SEND;
next_state <= 0; // TODO
end
// SHUTDOWN_1 -- send display off cmd
else if (state == SHUTDOWN_1) begin
send_buf <= 8'hAE;
state <= SEND;
next_state <= SHUTDOWN_2;
end
// SHUTDOWN_2 -- turn off VBAT
else if (state == SHUTDOWN_2) begin
vbatc <= 1;
wait_max <= 500000; // 100ms
state <= WAIT;
next_state <= SHUTDOWN_3;
end
// SHUTDOWN_4 -- turn off VDD
else if (state == SHUTDOWN_3) begin
vddc <= 1;
state <= 0; // TODO
end
end
end
assign cs = 0;
assign sclk = !clock;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EINVP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__EINVP_FUNCTIONAL_PP_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__einvp (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_TE;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_TE, TE, VPWR, VGND );
notif1 notif10 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_TE);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EINVP_FUNCTIONAL_PP_V |
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ledtest_SWITCH_ARRAY (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 3: 0] in_port;
input reset_n;
wire clk_en;
wire [ 3: 0] data_in;
wire [ 3: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {4 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND3_2_V
`define SKY130_FD_SC_MS__AND3_2_V
/**
* and3: 3-input AND.
*
* Verilog wrapper for and3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__and3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__and3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__and3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND3_2_V
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module aceusb(
/* WISHBONE interface */
input sys_clk,
input sys_rst,
input [31:0] wb_adr_i,
input [31:0] wb_dat_i,
output [31:0] wb_dat_o,
input wb_cyc_i,
input wb_stb_i,
input wb_we_i,
output reg wb_ack_o,
/* Signals shared between SystemACE and USB */
output [6:0] aceusb_a,
inout [15:0] aceusb_d,
output aceusb_oe_n,
output aceusb_we_n,
/* SystemACE signals */
input ace_clkin,
output ace_mpce_n,
input ace_mpirq,
output usb_cs_n,
output usb_hpi_reset_n,
input usb_hpi_int
);
wire access_read1;
wire access_write1;
wire access_ack1;
/* Avoid potential glitches by sampling wb_adr_i and wb_dat_i only at the appropriate time */
reg load_adr_dat;
reg [5:0] address_reg;
reg [15:0] data_reg;
always @(posedge sys_clk) begin
if(load_adr_dat) begin
address_reg <= wb_adr_i[7:2];
data_reg <= wb_dat_i[15:0];
end
end
aceusb_access access(
.ace_clkin(ace_clkin),
.rst(sys_rst),
.a(address_reg),
.di(data_reg),
.do(wb_dat_o[15:0]),
.read(access_read1),
.write(access_write1),
.ack(access_ack1),
.aceusb_a(aceusb_a),
.aceusb_d(aceusb_d),
.aceusb_oe_n(aceusb_oe_n),
.aceusb_we_n(aceusb_we_n),
.ace_mpce_n(ace_mpce_n),
.ace_mpirq(ace_mpirq),
.usb_cs_n(usb_cs_n),
.usb_hpi_reset_n(usb_hpi_reset_n),
.usb_hpi_int(usb_hpi_int)
);
assign wb_dat_o[31:16] = 16'h0000;
/* Synchronize read, write and acknowledgement pulses */
reg access_read;
reg access_write;
wire access_ack;
aceusb_sync sync_read(
.clk0(sys_clk),
.flagi(access_read),
.clk1(ace_clkin),
.flago(access_read1)
);
aceusb_sync sync_write(
.clk0(sys_clk),
.flagi(access_write),
.clk1(ace_clkin),
.flago(access_write1)
);
aceusb_sync sync_ack(
.clk0(ace_clkin),
.flagi(access_ack1),
.clk1(sys_clk),
.flago(access_ack)
);
/* Main FSM */
reg state;
reg next_state;
parameter IDLE = 1'd0;
parameter WAIT = 1'd1;
always @(posedge sys_clk) begin
if(sys_rst)
state <= IDLE;
else
state <= next_state;
end
always @(*) begin
load_adr_dat = 1'b0;
wb_ack_o = 1'b0;
access_read = 1'b0;
access_write = 1'b0;
next_state = state;
case(state)
IDLE: begin
if(wb_cyc_i & wb_stb_i) begin
load_adr_dat = 1'b1;
if(wb_we_i)
access_write = 1'b1;
else
access_read = 1'b1;
next_state = WAIT;
end
end
WAIT: begin
if(access_ack) begin
wb_ack_o = 1'b1;
next_state = IDLE;
end
end
endcase
end
endmodule
|
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2013 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// Permission:
//
// Lattice SG Pte. Ltd. grants permission to use this code
// pursuant to the terms of the Lattice Reference Design License Agreement.
//
//
// Disclaimer:
//
// This VHDL or Verilog source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Lattice provides no warranty
// regarding the use or functionality of this code.
//
// --------------------------------------------------------------------
//
// Lattice SG Pte. Ltd.
// 101 Thomson Road, United Square #07-02
// Singapore 307591
//
//
// TEL: 1-800-Lattice (USA and Canada)
// +65-6631-2000 (Singapore)
// +1-503-268-8001 (other locations)
//
// web: http://www.latticesemi.com/
// email: [email protected]
//
// --------------------------------------------------------------------
//
`timescale 1 ns / 1 ps
`define DISABLE_CPU_IO_BUS 1
module sdram_controller (/*AUTOARG*/
// Outputs
o_data_valid, o_data_req, o_busy, o_init_done, o_ack,
o_sdram_addr, o_sdram_blkaddr, o_sdram_casn, o_sdram_cke,
o_sdram_csn, o_sdram_dqm, o_sdram_rasn, o_sdram_wen, o_sdram_clk,
o_write_done, o_read_done,
// Inouts
`ifdef DISABLE_CPU_IO_BUS
i_data,
o_data,
`else
io_data,
`endif
io_sdram_dq,
// Inputs
i_addr, i_adv, i_clk, i_rst, i_rwn,
i_selfrefresh_req, i_loadmod_req, i_burststop_req, i_disable_active, i_disable_precharge, i_precharge_req, i_power_down, i_disable_autorefresh
);
`include "sdram_defines.vh"
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [26:0] i_addr; // To U0 of sdram_control_fsm.v
input i_adv; // To U0 of sdram_control_fsm.v
input i_clk; // To U0 of sdram_control_fsm.v
input i_rst; // To U0 of sdram_control_fsm.v
input i_rwn; // To U0 of sdram_control_fsm.v
input i_selfrefresh_req; // To U0 of sdram_control_fsm.v
input i_loadmod_req; // To U0 of sdram_control_fsm.v
input i_burststop_req; // To U0 of sdram_control_fsm.v
input i_disable_active;
input i_disable_precharge;
input i_precharge_req;
input i_power_down;
input i_disable_autorefresh;
/*AUTOOUTPUT*/
// End of automatics
output o_data_valid; // From U0 of sdram_control_fsm.v
output o_data_req; // From U0 of sdram_control_fsm.v
output o_busy; // From U0 of sdram_control_fsm.v
output o_init_done; // From U0 of sdram_control_fsm.v
output o_ack; // From U0 of sdram_control_fsm.v
output [12:0] o_sdram_addr; // From U0 of sdram_control_fsm.v
output [1:0] o_sdram_blkaddr;// From U0 of sdram_control_fsm.v
output o_sdram_casn; // From U0 of sdram_control_fsm.v
output o_sdram_cke; // From U0 of sdram_control_fsm.v
output o_sdram_csn; // From U0 of sdram_control_fsm.v
output [3:0] o_sdram_dqm; // From U0 of sdram_control_fsm.v
output o_sdram_rasn; // From U0 of sdram_control_fsm.v
output o_sdram_wen; // From U0 of sdram_control_fsm.v
output o_sdram_clk; // From U0 of sdram_control_fsm.v
output o_write_done;
output o_read_done;
/*AUTOINOUT*/
`ifdef DISABLE_CPU_IO_BUS
input [31:0] i_data; // To/From U0 of sdram_control_fsm.v
output [31:0] o_data; // To/From U0 of sdram_control_fsm.v
`else
inout [31:0] io_data; // To/From U0 of sdram_control_fsm.v
`endif
inout [31:0] io_sdram_dq; // To/From U0 of sdram_control_fsm.v
wire delay_done150us_i; // To U0 of sdram_control_fsm.v
wire refresh_count_done_i; // From U2 of autorefresh_counter.v
wire autoref_ack_i, init_done_i, sdrctl_busyn_i;
reg latch_ref_req_i;
reg refresh_req_i;
reg autorefresh_enable_i;
wire cpu_den_i;
wire [CPU_DATA_WIDTH-1:0] cpu_datain_i; // To/From U0 of sdram_control_fsm.v
wire [CPU_DATA_WIDTH-1:0] cpu_dataout_i; // To/From U0 of sdram_control_fsm.v
`ifdef DISABLE_CPU_IO_BUS
assign #WIREDLY o_data = cpu_dataout_i;
assign #WIREDLY cpu_datain_i = i_data;
`else
assign #WIREDLY io_data = (cpu_den_i) ? cpu_dataout_i : {`CPU_DBUS_LEN{1'bz}};
assign #WIREDLY cpu_datain_i = io_data;
`endif
reg power_down_reg1_i;
reg power_down_reg2_i;
reg power_down_reg3_i;
always @(posedge i_clk or posedge i_rst) begin
if (i_rst) begin
power_down_reg1_i <= 1'b0; end
else begin
power_down_reg1_i <= i_power_down; end
end
assign o_sdram_clk = i_clk ? ~(power_down_reg1_i) : 1'b0;
assign o_init_done = init_done_i;
assign sys_clk_i = i_clk;
assign sys_rst_i = i_rst;
assign o_busy = sdrctl_busyn_i;
sdram_control_fsm U0 (/*AUTOINST*/
// Outputs
.o_ack (o_ack),
.o_autoref_ack (autoref_ack_i),
.o_busy (sdrctl_busyn_i),
.o_init_done (init_done_i),
.o_sdram_cke (o_sdram_cke),
.o_sdram_csn (o_sdram_csn),
.o_sdram_rasn (o_sdram_rasn),
.o_sdram_casn (o_sdram_casn),
.o_sdram_wen (o_sdram_wen),
.o_sdram_blkaddr (o_sdram_blkaddr[SDRAM_BLKADR_WIDTH-1:0]),
.o_sdram_addr (o_sdram_addr[SDRAM_ADDR_WIDTH-1:0]),
.o_data_valid (o_data_valid),
.o_data_req (o_data_req),
.o_sdram_dqm (o_sdram_dqm[SDRAM_DQM_WIDTH-1:0]),
.o_write_done (o_write_done),
.o_read_done (o_read_done),
// Inouts
.i_data (i_data[CPU_DATA_WIDTH-1:0]),
.o_data (cpu_dataout_i[CPU_DATA_WIDTH-1:0]),
.o_den (cpu_den_i),
.io_sdram_dq (io_sdram_dq[SDRAM_DATA_WIDTH-1:0]),
// Inputs
.i_clk (i_clk),
.i_rst (i_rst),
.i_rwn (i_rwn),
.i_adv (i_adv),
.i_delay_done_100us (delay_done150us_i),
.i_refresh_req (refresh_req_i),
.i_selfrefresh_req (i_selfrefresh_req),
.i_loadmod_req (i_loadmod_req),
.i_burststop_req (i_burststop_req),
.i_disable_active (i_disable_active),
.i_disable_precharge (i_disable_precharge),
.i_precharge_req (i_precharge_req),
.i_power_down (i_power_down),
.i_addr (i_addr[ROWADDR_MSB:COLADDR_LSB]));
delay_gen150us U1 (/*AUTOINST*/
// Outputs
.o_lfsr_256_done (delay_done150us_i),
// Inputs
.i_sys_clk (sys_clk_i),
.i_sys_rst (sys_rst_i));
autorefresh_counter U2(/*AUTOINST*/
// Outputs
.o_refresh_count_done(refresh_count_done_i),
// Inputs
.i_sys_clk (sys_clk_i),
.i_sys_rst (sys_rst_i),
.i_autorefresh_enable(autorefresh_enable_i));
//Latch auto refresh request and clear it after ack
always @(posedge i_clk or posedge i_rst)
if (i_rst)
latch_ref_req_i <= #WIREDLY 0;
else if (latch_ref_req_i && autoref_ack_i)
latch_ref_req_i <= #WIREDLY 0;
else
latch_ref_req_i <= #WIREDLY refresh_count_done_i;
//Issue refresh request when SDRAM Controller initialization done and is not busy
always @(posedge i_clk or posedge i_rst)
if (i_rst)
refresh_req_i <= #WIREDLY 0;
else if (i_disable_autorefresh)
refresh_req_i <= #WIREDLY 0;
else if (init_done_i && ~sdrctl_busyn_i)
refresh_req_i <= #WIREDLY latch_ref_req_i;
else
refresh_req_i <= #WIREDLY 0;
//Enable auto refresh counter after initialization and not under self refresh state
always @(posedge i_clk or posedge i_rst)
if (i_rst)
autorefresh_enable_i <= #WIREDLY 0;
else if (init_done_i && ~i_selfrefresh_req)
autorefresh_enable_i <= #WIREDLY 1;
else
autorefresh_enable_i <= #WIREDLY 0;
endmodule // sdram_controller
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Fri Sep 22 22:04:20 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_xbar_0_stub.v
// Design : zqynq_lab_1_design_xbar_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_crossbar_v2_1_14_axi_crossbar,Vivado 2017.2.1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize,
m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awregion, m_axi_awqos,
m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid,
m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_arid, m_axi_araddr,
m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot,
m_axi_arregion, m_axi_arqos, m_axi_arvalid, m_axi_arready, m_axi_rid, m_axi_rdata,
m_axi_rresp, m_axi_rlast, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast[0:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast[0:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awid[47:0],m_axi_awaddr[127:0],m_axi_awlen[31:0],m_axi_awsize[11:0],m_axi_awburst[7:0],m_axi_awlock[3:0],m_axi_awcache[15:0],m_axi_awprot[11:0],m_axi_awregion[15:0],m_axi_awqos[15:0],m_axi_awvalid[3:0],m_axi_awready[3:0],m_axi_wdata[127:0],m_axi_wstrb[15:0],m_axi_wlast[3:0],m_axi_wvalid[3:0],m_axi_wready[3:0],m_axi_bid[47:0],m_axi_bresp[7:0],m_axi_bvalid[3:0],m_axi_bready[3:0],m_axi_arid[47:0],m_axi_araddr[127:0],m_axi_arlen[31:0],m_axi_arsize[11:0],m_axi_arburst[7:0],m_axi_arlock[3:0],m_axi_arcache[15:0],m_axi_arprot[11:0],m_axi_arregion[15:0],m_axi_arqos[15:0],m_axi_arvalid[3:0],m_axi_arready[3:0],m_axi_rid[47:0],m_axi_rdata[127:0],m_axi_rresp[7:0],m_axi_rlast[3:0],m_axi_rvalid[3:0],m_axi_rready[3:0]" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [0:0]s_axi_awvalid;
output [0:0]s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input [0:0]s_axi_wlast;
input [0:0]s_axi_wvalid;
output [0:0]s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_bvalid;
input [0:0]s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [0:0]s_axi_arvalid;
output [0:0]s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output [0:0]s_axi_rlast;
output [0:0]s_axi_rvalid;
input [0:0]s_axi_rready;
output [47:0]m_axi_awid;
output [127:0]m_axi_awaddr;
output [31:0]m_axi_awlen;
output [11:0]m_axi_awsize;
output [7:0]m_axi_awburst;
output [3:0]m_axi_awlock;
output [15:0]m_axi_awcache;
output [11:0]m_axi_awprot;
output [15:0]m_axi_awregion;
output [15:0]m_axi_awqos;
output [3:0]m_axi_awvalid;
input [3:0]m_axi_awready;
output [127:0]m_axi_wdata;
output [15:0]m_axi_wstrb;
output [3:0]m_axi_wlast;
output [3:0]m_axi_wvalid;
input [3:0]m_axi_wready;
input [47:0]m_axi_bid;
input [7:0]m_axi_bresp;
input [3:0]m_axi_bvalid;
output [3:0]m_axi_bready;
output [47:0]m_axi_arid;
output [127:0]m_axi_araddr;
output [31:0]m_axi_arlen;
output [11:0]m_axi_arsize;
output [7:0]m_axi_arburst;
output [3:0]m_axi_arlock;
output [15:0]m_axi_arcache;
output [11:0]m_axi_arprot;
output [15:0]m_axi_arregion;
output [15:0]m_axi_arqos;
output [3:0]m_axi_arvalid;
input [3:0]m_axi_arready;
input [47:0]m_axi_rid;
input [127:0]m_axi_rdata;
input [7:0]m_axi_rresp;
input [3:0]m_axi_rlast;
input [3:0]m_axi_rvalid;
output [3:0]m_axi_rready;
endmodule
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream SRL-based FIFO (64 bit datapath)
*/
module axis_srl_fifo_64 #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter DEPTH = 16
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser,
/*
* Status
*/
output wire [$clog2(DEPTH+1)-1:0] count
);
reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] data_reg[DEPTH-1:0];
reg [$clog2(DEPTH+1)-1:0] ptr_reg = 0, ptr_next;
reg full_reg = 0, full_next;
reg empty_reg = 1, empty_next;
assign {output_axis_tlast, output_axis_tuser, output_axis_tkeep, output_axis_tdata} = data_reg[ptr_reg-1];
assign input_axis_tready = ~full_reg;
assign output_axis_tvalid = ~empty_reg;
assign count = ptr_reg;
wire ptr_empty = ptr_reg == 0;
wire ptr_empty1 = ptr_reg == 1;
wire ptr_full = ptr_reg == DEPTH;
wire ptr_full1 = ptr_reg == DEPTH-1;
reg shift;
reg inc;
reg dec;
integer i;
initial begin
for (i = 0; i < DEPTH; i = i + 1) begin
data_reg[i] <= 0;
end
end
always @* begin
shift = 0;
inc = 0;
dec = 0;
ptr_next = ptr_reg;
full_next = full_reg;
empty_next = empty_reg;
if (output_axis_tready & input_axis_tvalid & ~full_reg) begin
shift = 1;
inc = ptr_empty;
empty_next = 0;
end else if (output_axis_tready & output_axis_tvalid) begin
dec = 1;
full_next = 0;
empty_next = ptr_empty1;
end else if (input_axis_tvalid & input_axis_tready) begin
shift = 1;
inc = 1;
full_next = ptr_full1;
empty_next = 0;
end
end
always @(posedge clk) begin
if (rst) begin
ptr_reg <= 0;
end else begin
if (shift) begin
data_reg[0] <= {input_axis_tlast, input_axis_tuser, input_axis_tkeep, input_axis_tdata};
for (i = 0; i < DEPTH-1; i = i + 1) begin
data_reg[i+1] <= data_reg[i];
end
end
if (inc) begin
ptr_reg <= ptr_reg + 1;
end else if (dec) begin
ptr_reg <= ptr_reg - 1;
end else begin
ptr_reg <= ptr_reg;
end
full_reg <= full_next;
empty_reg <= empty_next;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_DLATCH_PR_PP_PG_N_SYMBOL_V
`define SKY130_FD_SC_HVL__UDP_DLATCH_PR_PP_PG_N_SYMBOL_V
/**
* udp_dlatch$PR_pp$PG$N: D-latch, gated clear direct / gate active
* high (Q output UDP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__udp_dlatch$PR_pp$PG$N (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET ,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_DLATCH_PR_PP_PG_N_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKBUFLP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__CLKBUFLP_FUNCTIONAL_PP_V
/**
* clkbuflp: Clock tree buffer, Low Power.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__clkbuflp (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKBUFLP_FUNCTIONAL_PP_V |
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_cpu_cpu_debug_slave_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
limbus_cpu_cpu_debug_slave_tck the_limbus_cpu_cpu_debug_slave_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
limbus_cpu_cpu_debug_slave_sysclk the_limbus_cpu_cpu_debug_slave_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic limbus_cpu_cpu_debug_slave_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam limbus_cpu_cpu_debug_slave_phy.sld_auto_instance_index = "YES",
// limbus_cpu_cpu_debug_slave_phy.sld_instance_index = 0,
// limbus_cpu_cpu_debug_slave_phy.sld_ir_width = 2,
// limbus_cpu_cpu_debug_slave_phy.sld_mfg_id = 70,
// limbus_cpu_cpu_debug_slave_phy.sld_sim_action = "",
// limbus_cpu_cpu_debug_slave_phy.sld_sim_n_scan = 0,
// limbus_cpu_cpu_debug_slave_phy.sld_sim_total_length = 0,
// limbus_cpu_cpu_debug_slave_phy.sld_type_id = 34,
// limbus_cpu_cpu_debug_slave_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLCLKP_2_V
`define SKY130_FD_SC_MS__DLCLKP_2_V
/**
* dlclkp: Clock gate.
*
* Verilog wrapper for dlclkp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dlclkp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dlclkp_2 (
GCLK,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK(CLK),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dlclkp_2 (
GCLK,
GATE,
CLK
);
output GCLK;
input GATE;
input CLK ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK(CLK)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLCLKP_2_V
|
/**
# CordicRectToPolar - CORDIC Algorithm for Rectangular to Polar Coordinates #
Implements the CORDIC algorithm for the purpose of converting rectangular
coordinates to polar coordinates. It takes N cycles, where
`N = min(IN_WIDTH, ANGLE_WIDTH-1)`.
## Algorithm ##
The algorithm is based on doing iterative rotations of the x & y coordinates
using specially chosen angles. Rotation is done towards the positive X axis.
When complete, the X coordinate will equal the polar coordinate magnitude times
a constant, and the total rotation angle will be the polar coordinate angle.
```
[ cos(t) -sin(t) ] = (1+tan(t)^2)^(-1/2) * [ 1 -tan(t) ]
[ sin(t) cos(t) ] [ tan(t) 1 ]
Choose t such that tan(t) = 2^-i, where i is the iteration number:
= (1+2^(-2*i))^(-1/2) * [ 1 -2^-i ]
[ 2^-i 1 ]
```
The maximum number of rotations can be determined by how many bits are in the
input word and the output angle. When the bit shift implied by the `2^-i` amount
would be greater than the input word width, the algorithm would be adding +/- 0,
so it can terminate. Likewise, when the angle value in the lookup table is
smaller than the LSB of the output angle word, the algorithm would be adding +/-
0 to it, so it can terminate.
## Steps ##
1. Rotate coordinate into quadrant 1 (positive x, positive y)
2. Rotate using powers of two and a lookup table for the angle used.
3. Terminate when no more bits can be computed.
## Notes ##
1. This algorithm will not complete if inStrobe is set more than once every ITER_NUM cycles.
2. No optimizations are applied - there are no attempts to fit into DSP device primitives.
*/
module CordicRectToPolar #(
parameter STAGES = 1, ///< Number of stages in CORDIC
parameter IN_WIDTH = 16, ///< Input coordinate pair width
parameter ANGLE_WIDTH = 16, ///< Output angle register width
parameter SCALE_MAGNITUDE = 0, ///< Set to 1 to scale magnitude to true value
parameter MULT_WIDTH = 16 ///< Number of bits to use for magnitude scaling word, if SCALE_MAGNITUDE is 1
)
(
input clk, ///< System clock
input rst, ///< Reset, active high and synchronous
input inStrobe, ///< Input data strobe
input signed [IN_WIDTH-1:0] x, ///< X coordinate
input signed [IN_WIDTH-1:0] y, ///< Y coordinate
output reg [ANGLE_WIDTH-1:0] angle, ///< Angle
output reg [IN_WIDTH:0] magnitude, ///< Magnitude
output reg outStrobe ///< Output data strobe
);
//////////////////////////////////////////////////////////////////////////////
// Local Parameters (do not set externally)
//////////////////////////////////////////////////////////////////////////////
parameter ITER_NUM = (IN_WIDTH > (ANGLE_WIDTH-1)) ? (ANGLE_WIDTH-1) : IN_WIDTH;
parameter ITER_WIDTH = $clog2(ITER_NUM);
parameter M_PI = $acos(-1.0);
localparam STAGES_INT = (ITER_NUM > STAGES) ? STAGES : ITER_NUM; // Max out at `ITER_NUM` of stages
//////////////////////////////////////////////////////////////////////////////
// Constant Declarations (calculated on start)
//////////////////////////////////////////////////////////////////////////////
reg [MULT_WIDTH-1:0] MAG_SCALE; ///< Magnitude Scalar
reg [ANGLE_WIDTH-1:0] ANGLE_LOOKUP [ITER_NUM-1:0]; ///< Angle lookup table
//////////////////////////////////////////////////////////////////////////////
// Signal Declarations
//////////////////////////////////////////////////////////////////////////////
reg [ITER_WIDTH-1:0] iter; ///< Iteration counter
reg [ANGLE_WIDTH-1:0] angleReg; ///< Angle register
reg signed [IN_WIDTH:0] xReg; ///< X coordinate working register
reg signed [IN_WIDTH-1:0] yReg; ///< Y coordinate working register
reg doneD1;
wire signed [IN_WIDTH+MULT_WIDTH:0] magCalc;
wire done;
integer i;
real magScaleCalc;
//////////////////////////////////////////////////////////////////////////////
// Main Code
//////////////////////////////////////////////////////////////////////////////
// Calculate constants
initial begin
for (i=0; i<ITER_NUM; i=i+1) begin
ANGLE_LOOKUP[i] = $rtoi(($atan(2.0**(-i)) * 2.0**(ANGLE_WIDTH-1) / M_PI)+0.5);
end
magScaleCalc = 1.0;
for (i=0; i<ITER_NUM; i=i+1) begin
magScaleCalc = magScaleCalc * (1.0+2.0**(-2.0*i))**(-0.5);
end
MAG_SCALE = $rtoi(2.0**(MULT_WIDTH) * magScaleCalc);
end
if (SCALE_MAGNITUDE) begin
assign magCalc = xReg * MAG_SCALE;
end
else begin
assign magCalc = 'd0;
end
// Algorithm loop
assign done = (iter == (ITER_NUM-1));
always @(posedge clk) begin
if (rst) begin
iter <= ITER_NUM-1;
doneD1 <= 1'b1;
magnitude <= 'd0;
outStrobe <= 1'b0;
angle <= 'd0;
xReg <= 'd0;
yReg <= 'd0;
angleReg <= 'd0;
end
else begin
doneD1 <= done;
outStrobe <= done & ~doneD1;
if (done & ~doneD1) begin
angle <= angleReg;
if (SCALE_MAGNITUDE) begin
magnitude <= magCalc >>> MULT_WIDTH;
end
else begin
magnitude <= xReg;
end
end
if (inStrobe) begin
iter <= 'd0;
case ({y[IN_WIDTH-1], x[IN_WIDTH-1]}) // y<0, x<0
2'b00 : begin xReg <= x; yReg <= y; angleReg <= (0 << (ANGLE_WIDTH-2)); end // 0-90 degrees
2'b01 : begin xReg <= y; yReg <= -x; angleReg <= (1 << (ANGLE_WIDTH-2)); end // 90-180 degrees
2'b11 : begin xReg <= -x; yReg <= -y; angleReg <= (2 << (ANGLE_WIDTH-2)); end // 180-270 degrees
2'b10 : begin xReg <= -y; yReg <= x; angleReg <= (3 << (ANGLE_WIDTH-2)); end // 270-360 degrees
endcase
end
else if (!done) begin
iter <= iter + 2'd1;
if (yReg[IN_WIDTH-1]) begin // yReg < 0
xReg <= xReg - (yReg >>> iter);
yReg <= yReg + (xReg >>> iter);
angleReg <= angleReg - ANGLE_LOOKUP[iter];
end
else begin
xReg <= xReg + (yReg >>> iter);
yReg <= yReg - (xReg >>> iter);
angleReg <= angleReg + ANGLE_LOOKUP[iter];
end
end
end
end
endmodule
|
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE Connection Matrix Priority Encoder ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/wb_conmax/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: wb_conmax_pri_enc.v,v 1.1 2008/05/07 22:43:23 daughtry Exp $
//
// $Date: 2008/05/07 22:43:23 $
// $Revision: 1.1 $
// $Author: daughtry $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: wb_conmax_pri_enc.v,v $
// Revision 1.1 2008/05/07 22:43:23 daughtry
// Initial Demo RTL check-in
//
// Revision 1.2 2002/10/03 05:40:07 rudi
// Fixed a minor bug in parameter passing, updated headers and specification.
//
// Revision 1.1.1.1 2001/10/19 11:01:41 rudi
// WISHBONE CONMAX IP Core
//
//
//
//
//
`include "wb_conmax_defines.v"
module wb_conmax_pri_enc(
valid,
pri0, pri1, pri2, pri3,
pri4, pri5, pri6, pri7,
pri_out
);
////////////////////////////////////////////////////////////////////
//
// Module Parameters
//
parameter [1:0] pri_sel = 2'd0;
////////////////////////////////////////////////////////////////////
//
// Module IOs
//
input [7:0] valid;
input [1:0] pri0, pri1, pri2, pri3;
input [1:0] pri4, pri5, pri6, pri7;
output [1:0] pri_out;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
wire [3:0] pri0_out, pri1_out, pri2_out, pri3_out;
wire [3:0] pri4_out, pri5_out, pri6_out, pri7_out;
wire [3:0] pri_out_tmp;
reg [1:0] pri_out0, pri_out1;
wire [1:0] pri_out;
////////////////////////////////////////////////////////////////////
//
// Priority Decoders
//
wb_conmax_pri_dec #(pri_sel) pd0(
.valid( valid[0] ),
.pri_in( pri0 ),
.pri_out( pri0_out )
);
wb_conmax_pri_dec #(pri_sel) pd1(
.valid( valid[1] ),
.pri_in( pri1 ),
.pri_out( pri1_out )
);
wb_conmax_pri_dec #(pri_sel) pd2(
.valid( valid[2] ),
.pri_in( pri2 ),
.pri_out( pri2_out )
);
wb_conmax_pri_dec #(pri_sel) pd3(
.valid( valid[3] ),
.pri_in( pri3 ),
.pri_out( pri3_out )
);
wb_conmax_pri_dec #(pri_sel) pd4(
.valid( valid[4] ),
.pri_in( pri4 ),
.pri_out( pri4_out )
);
wb_conmax_pri_dec #(pri_sel) pd5(
.valid( valid[5] ),
.pri_in( pri5 ),
.pri_out( pri5_out )
);
wb_conmax_pri_dec #(pri_sel) pd6(
.valid( valid[6] ),
.pri_in( pri6 ),
.pri_out( pri6_out )
);
wb_conmax_pri_dec #(pri_sel) pd7(
.valid( valid[7] ),
.pri_in( pri7 ),
.pri_out( pri7_out )
);
////////////////////////////////////////////////////////////////////
//
// Priority Encoding
//
assign pri_out_tmp = pri0_out | pri1_out | pri2_out | pri3_out |
pri4_out | pri5_out | pri6_out | pri7_out;
// 4 Priority Levels
always @(pri_out_tmp)
if(pri_out_tmp[3]) pri_out1 = 2'h3;
else
if(pri_out_tmp[2]) pri_out1 = 2'h2;
else
if(pri_out_tmp[1]) pri_out1 = 2'h1;
else pri_out1 = 2'h0;
// 2 Priority Levels
always @(pri_out_tmp)
if(pri_out_tmp[1]) pri_out0 = 2'h1;
else pri_out0 = 2'h0;
////////////////////////////////////////////////////////////////////
//
// Final Priority Output
//
// Select configured priority
assign pri_out = (pri_sel==2'd0) ? 2'h0 : ( (pri_sel==2'd1) ? pri_out0 : pri_out1 );
endmodule
|
/*
* Verilog side Virtual Processor, for running host
* programs as control in simulation.
*
* Copyright (c) 2004-2016 Simon Southwell.
*
* This file is part of VProc.
*
* VProc is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* VProc is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with VProc. If not, see <http://www.gnu.org/licenses/>.
*
* $Id: f_VProc.v,v 1.5 2021/05/15 07:45:17 simon Exp $
* $Source: /home/simon/CVS/src/HDL/VProc/f_VProc.v,v $
*/
`include "extradefs.v"
`VProcTimeScale
`define WEbit 0
`define RDbit 1
`define DeltaCycle -1
module VProc (Clk, Addr, WE, RD, DataOut, DataIn, WRAck, RDAck, Interrupt, Update, UpdateResponse, Node);
input Clk;
input RDAck;
input WRAck;
input UpdateResponse;
input [3:0] Node;
input [2:0] Interrupt;
input [31:0] DataIn;
output [31:0] Addr, DataOut;
output WE;
output RD;
output Update;
integer VPDataOut;
integer VPAddr;
integer VPRW;
integer VPTicks;
integer TickVal;
reg [31:0] DataOut;
integer DataInSamp;
reg [31:0] Addr;
integer IntSamp;
integer NodeI;
reg WE;
reg RD;
reg RdAckSamp;
reg WRAckSamp;
reg Initialised;
reg Update;
initial
begin
TickVal = 1;
Initialised = 0;
WE = 0;
RD = 0;
Update = 0;
// Don't remove delay! Needed to allow Node to be assigned
#0
$vinit(Node);
Initialised = 1;
end
always @(posedge Clk)
begin
// Cleanly sample the inputs and make them integers
DataInSamp = DataIn;
RdAckSamp = RDAck;
WRAckSamp = WRAck;
IntSamp = {1'b0, Interrupt};
NodeI = Node;
if (Initialised == 1'b1)
begin
if (IntSamp > 0)
begin
$vsched(NodeI, IntSamp, DataInSamp, VPDataOut, VPAddr, VPRW, VPTicks);
// If interrupt routine returns non-zero tick, then override
// current tick value. Otherwise, leave at present value.
if (VPTicks > 0)
begin
TickVal = VPTicks;
end
end
// If tick, write or a read has completed...
if ((RD === 1'b0 && WE === 1'b0 && TickVal === 0) ||
(RD === 1'b1 && RdAckSamp === 1'b1) ||
(WE === 1'b1 && WRAckSamp === 1'b1))
begin
// Host process message scheduler called
IntSamp = 0;
$vsched(NodeI, IntSamp, DataInSamp, VPDataOut, VPAddr, VPRW, VPTicks);
#`RegDel
WE = VPRW[`WEbit];
RD = VPRW[`RDbit];
DataOut = VPDataOut;
Addr = VPAddr;
Update = ~Update;
@(UpdateResponse);
// Update current tick value with returned number (if not zero)
if (VPTicks > 0)
begin
TickVal = VPTicks;
end
else if ( VPTicks < 0)
begin
while (VPTicks == `DeltaCycle)
begin
// Resample delta input data
DataInSamp = DataIn;
IntSamp = 0;
$vsched(NodeI, IntSamp, DataInSamp, VPDataOut, VPAddr, VPRW, VPTicks);
WE = VPRW[`WEbit];
RD = VPRW[`RDbit];
DataOut = VPDataOut;
Addr = VPAddr;
Update = ~Update;
if (VPTicks >= 0)
begin
TickVal = VPTicks;
end
@(UpdateResponse);
end
end
end
else
begin
// Count down to zero and stop
TickVal = (TickVal > 0) ? TickVal - 1 : 0;
end
end
end
endmodule
|
module top (
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
reg nrst = 0;
wire tx_baud_edge;
wire rx_baud_edge;
// Data in.
wire [7:0] rx_data_wire;
wire rx_data_ready_wire;
// Data out.
wire tx_data_ready;
wire tx_data_accepted;
wire [7:0] tx_data;
assign led[14:0] = sw[14:0];
assign led[15] = rx_data_ready_wire ^ sw[15];
UART #(
.COUNTER(25),
.OVERSAMPLE(8)
) uart (
.clk(clk),
.rst(!nrst),
.rx(rx),
.tx(tx),
.tx_data_ready(tx_data_ready),
.tx_data(tx_data),
.tx_data_accepted(tx_data_accepted),
.rx_data(rx_data_wire),
.rx_data_ready(rx_data_ready_wire)
);
wire [4:0] write_address;
wire [4:0] read_address;
wire [0:0] read_data;
wire [0:0] write_data;
wire write_enable;
wire [0:0] rom_read_data;
wire [4:0] rom_read_address;
assign rom_read_data[0] = ^rom_read_address;
wire loop_complete;
wire error_detected;
wire [7:0] error_state;
wire [4:0] error_address;
wire [0:0] expected_data;
wire [0:0] actual_data;
RAM_TEST #(
.ADDR_WIDTH(5),
.DATA_WIDTH(1),
.IS_DUAL_PORT(1),
.ADDRESS_STEP(1),
// 32-bit LUT memories are 0-31
.MAX_ADDRESS(31)
) dram_test (
.rst(!nrst),
.clk(clk),
// Memory connection
.read_data(read_data),
.write_data(write_data),
.write_enable(write_enable),
.read_address(read_address),
.write_address(write_address),
// INIT ROM connection
.rom_read_data(rom_read_data),
.rom_read_address(rom_read_address),
// Reporting
.loop_complete(loop_complete),
.error(error_detected),
.error_state(error_state),
.error_address(error_address),
.expected_data(expected_data),
.actual_data(actual_data)
);
wire [0:0] read_data_pre_ff;
RAM32X1D #(
.INIT(32'b10010110_01101001_01101001_10010110)
) dram(
.WCLK(clk),
.A4(write_address[4]),
.A3(write_address[3]),
.A2(write_address[2]),
.A1(write_address[1]),
.A0(write_address[0]),
.DPRA4(read_address[4]),
.DPRA3(read_address[3]),
.DPRA2(read_address[2]),
.DPRA1(read_address[1]),
.DPRA0(read_address[0]),
.DPO(read_data_pre_ff[0]),
.D(write_data[0]),
.WE(write_enable)
);
FDRE ram_reg(
.D(read_data_pre_ff),
.Q(read_data[0]),
.C(clk),
.CE(1),
.R(0)
);
ERROR_OUTPUT_LOGIC #(
.DATA_WIDTH(1),
.ADDR_WIDTH(5)
) output_logic(
.clk(clk),
.rst(!nrst),
.loop_complete(loop_complete),
.error_detected(error_detected),
.error_state(error_state),
.error_address(error_address),
.expected_data(expected_data),
.actual_data(actual_data),
.tx_data(tx_data),
.tx_data_ready(tx_data_ready),
.tx_data_accepted(tx_data_accepted)
);
always @(posedge clk) begin
nrst <= 1;
end
endmodule
|
`timescale 1ns/10ps
module RAMDPSim;
reg clock;
reg reset;
reg we;
reg [3:0] addr0;
reg [3:0] addr1;
reg [7:0] data_i;
wire [7:0] data_o0;
wire [7:0] data_o1;
initial begin
#0 $dumpfile(`VCDFILE);
#0 $dumpvars;
#1000 $finish;
end
initial begin
#0 clock = 1;
forever #2 clock = ~clock;
end
initial begin
#0 reset = 0;
#1 reset = 1;
#4 reset = 0;
end
initial begin
#0.1 we = 0;
#8 we = 1;
addr0 = 4'hA;
data_i = 8'hBB;
addr1 = 4'hA;
#4 we = 1;
addr0 = 4'h2;
data_i = 8'hAA;
addr1 = 4'h2;
#4 we = 1;
addr0 = 4'h7;
data_i = 8'hEF;
addr1 = 4'hA;
#4 we = 1;
addr0 = 4'h1;
data_i = 8'hAE;
addr1 = 4'h2;
#4 we = 0;
addr0 = 4'hA;
addr1 = 4'h1;
#4 we = 0;
addr0 = 4'h2;
addr1 = 4'h7;
#4 we = 0;
addr0 = 4'h7;
addr1 = 4'h2;
#4 we = 0;
addr0 = 4'h1;
addr1 = 4'hA;
end // initial begin
RAMDP #(.AddrSize(4),
.DataSize(8))
ramdp (.clock(clock),
.reset(reset),
.we(we),
.addr0(addr0),
.addr1(addr1),
.data_i(data_i),
.data_o0(data_o0),
.data_o1(data_o1));
endmodule // RAMDPSim
|
module jcarrylookaheadadder(Y,carryout,A,B,carryin);
output [3:0]Y;
output carryout;
input [3:0]A,B;
input carryin;
wire [3:0]g,p;// generate and propogate
wire [4:0]c;// intermediate carry of adders, one extra for coding simplicity
assign c[0] = carryin; // this line is not needed can be directly written
assign Y[0] = A[0] ^ B[0] ^ c[0];
// The below single line is what reduces the delay
assign c[1] = ( ( A[0] & B[0] ) | ( ( A[0] ^ B[0] ) & c[0] ) );
assign Y[1] = A[1] ^ B[1] ^ c[1];
// The below single line is what reduces the delay
//assign c[2] = ( ( A[1] & B[1] ) | ( ( A[1] ^ B[1] ) & c[1] ) );
// Next substitue c[1] with the expanded logic
assign c[2] = ( ( A[1] & B[1] ) | ( ( A[1] ^ B[1] ) & ( ( A[0] & B[0] ) | ( ( A[0] ^ B[0] ) & c[0] ) ) ) ); // This line removed the delay in calculating carry logic
assign Y[2] = A[2] ^ B[2] ^ c[2];
// The below single line is what reduces the delay
//assign c[3] = ( ( A[2] & B[2] ) | ( ( A[2] ^ B[2] ) & c[2] ) );// // This line removed the delay in calculating propogate logic
// Next substitue c[2] with the expanded logic
//assign c[3] = ( ( A[2] & B[2] ) | ( ( A[2] ^ B[2] ) & ( ( A[1] & B[1] ) | ( ( A[1] ^ B[1] ) & c[1] ) ) ) );
// Next substitue c[1] with the expanded logic
assign c[3] = ( ( A[2] & B[2] ) | ( ( A[2] ^ B[2] ) & ( ( A[1] & B[1] ) | ( ( A[1] ^ B[1] ) & ( ( A[0] & B[0] ) | ( ( A[0] ^ B[0] ) & c[0] ) ) ) ) ) );
assign Y[3] = A[3] ^ B[3] ^ c[3];
// The below single line is what reduces the delay
//assign c[4] = ( ( A[0] & B[0] ) | ( ( A[0] ^ B[0] ) & c[3] ) );
// Next substitue c[3] with the expanded logic
//assign c[4] = ( ( A[0] & B[0] ) | ( ( A[0] ^ B[0] ) & ( ( A[2] & B[2] ) | ( ( A[2] ^ B[2] ) & c[2] ) ) ) );
// Next substitue c[2] with the expanded logic
//assign c[4] = ( ( A[0] & B[0] ) | ( ( A[0] ^ B[0] ) & ( ( A[2] & B[2] ) | ( ( A[2] ^ B[2] ) & ( ( A[1] & B[1] ) | ( ( A[1] ^ B[1] ) & c[1] ) ) ) ) ) );
// Next substitue c[1] with the expanded logic
assign c[4] = ( ( A[0] & B[0] ) | ( ( A[0] ^ B[0] ) & ( ( A[2] & B[2] ) | ( ( A[2] ^ B[2] ) & ( ( A[1] & B[1] ) | ( ( A[1] ^ B[1] ) & ( ( A[0] & B[0] ) | ( ( A[0] ^ B[0] ) & c[0] ) ) ) ) ) ) ) );
// finally assign the carryout
assign carryout = c[4];
endmodule
/*
// This will cause more delay into ckt
assign g[0] = A[0] & B[0];
assign p[0] = A[0] ^ B[0];
assign c[1] = g[0] | ( p[0] & c[0]);
assign Y[0] = A[0] ^ B[0] ^ c[0];
// This will cause more delay into ckt
assign g[1] = A[1] & B[1];
assign p[1] = A[1] ^ B[1];
assign c[2] = g[1] | ( p[1] & c[1]);
assign Y[1] = A[1] ^ B[1] ^ c[1];
// This will cause more delay into ckt
assign g[2] = A[2] & B[2];
assign p[2] = A[2] ^ B[2];
assign c[3] = g[2] | ( p[2] & c[2]);
assign Y[2] = A[2] ^ B[2] ^ c[2];
// This will cause more delay into ckt
assign g[3] = A[3] & B[3];
assign p[3] = A[3] ^ B[3];
assign carryout = g[3] | ( p[3] & c[3]);
assign Y[2] = A[2] ^ B[2] ^ c[3];
*/ |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MAJ3_PP_SYMBOL_V
`define SKY130_FD_SC_MS__MAJ3_PP_SYMBOL_V
/**
* maj3: 3-input majority vote.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__maj3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__MAJ3_PP_SYMBOL_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_img_4_data_stream_0_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_img_4_data_stream_0_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "auto";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_img_4_data_stream_0_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_img_4_data_stream_0_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
/*
* This file is part of the DSLogic-hdl project.
*
* Copyright (C) 2014 DreamSourceLab <[email protected]>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
`timescale 1ns/100ps
`define D #1
module sdram_ctl(
CLK, RST_,
// REG interface
STOP_CLK, PAA, SET_MODE, BLK_SIZE, IS_SEQ,
MODULE_BK_NUM, ROW_SIZE, COL_SIZE, BK_SIZE, BIT_SIZE,
tRCD, tCAS, tRAS, tRP,
tREF, tRC, //note: tRC minus 1
// from/to host side
ADDR, RD, WR, DAT_I, DAT_O,
RD_DAT_RDY, BURST_RDY, RW,
CPU_GNT_, MUX_EN,
// from/to DIMM
CKE, CS_,
RAS_, CAS_, WE_, DQM,
BA, DIMM_ADDR,
DQ_I, DQ_O, DQ_OE );
input CLK, RST_;
input STOP_CLK, PAA, SET_MODE;
input [2:0] BLK_SIZE;
input IS_SEQ, MODULE_BK_NUM;
input [1:0] ROW_SIZE, // 2'b00 : A0-A10, 2'b01 : A0-A11, 2'b10 : A0-A12
BIT_SIZE; // 2'b00 : 4, 2'b01 : 8, 2'b10 : 16, 2'b11 : 32
input BK_SIZE; // 1'b0 : B0, 1'b1 : B0-B1
input [1:0] COL_SIZE; // 3'b000: A0-A7 3'b001: A0-A8 3'b010: A0-A9
// 3'b011: A0-A9,A11 3'b100: A0-A9, A11, A12
input [1:0] tRCD, tCAS, tRP;
input [2:0] tRAS;
input [11:0] tREF;
input [3:0] tRC;
input [31:0] ADDR;
input RD, WR;
input [15:0] DAT_I;
output [15:0] DAT_O;
output RD_DAT_RDY, BURST_RDY;
output RW;
input CPU_GNT_;
output MUX_EN;
output CKE, RAS_, CAS_, WE_;
output CS_;
output DQM;
output [1:0] BA;
output [12:0] DIMM_ADDR;
input [15:0] DQ_I;
output [15:0] DQ_O;
output DQ_OE;
/*=============================================================
+ Parameters definition
+=============================================================*/
//parameter SD_IDLE = 0, SD_SET_MODE = 12,
//// SD_SELF_REF = 2, SD_POWER_DOWN = 4,
// SD_AUTO_REF = 3, SD_ROW_ACTIVE = 9,
// SD_READ = 8, SD_WRITE = 1,
// SD_BURST_TERM = 13, SD_PRECHARGE = 11,
// SD_RD2PRECH = 10;
//
//reg [3:0] D_SD, Q_SD;
parameter SD_IDLE = 9'b000000001;
parameter SD_SET_MODE = 9'b000000010;
parameter SD_AUTO_REF = 9'b000000100;
parameter SD_ROW_ACTIVE = 9'b000001000;
parameter SD_READ = 9'b000010000;
parameter SD_WRITE = 9'b000100000;
parameter SD_BURST_TERM = 9'b001000000;
parameter SD_PRECHARGE = 9'b010000000;
parameter SD_RD2PRECH = 9'b100000000;
reg [8:0] D_SD, Q_SD;
/*=============================================================
+ Z variables of main state machine
+=============================================================*/
reg q_precharge, q_idle, q_burst_term,
q_rd, q_wr, q_auto_ref, q_row_active,
q_set_mode, q_rd2prech;
reg d_precharge, d_idle, d_set_mode, d_burst_term,
d_auto_ref;
wire q_rw = q_rd | q_wr;
wire d_wr = (D_SD == SD_WRITE);
//wire d_wr = D_SD[5];
wire d_row_active = (D_SD == SD_ROW_ACTIVE);
/*=============================================================
+ init_finished
+=============================================================*/
reg init_finished = 1'b0, d_init_finished;
reg q_init_cnt = 1'b0, d_init_cnt;
wire RC_CNT_EQ_0;
always @(posedge CLK)
q_init_cnt <= `D d_init_cnt;
always @( q_init_cnt or init_finished or q_auto_ref or RC_CNT_EQ_0 ) begin
d_init_cnt = q_init_cnt;
if( !init_finished & q_auto_ref & RC_CNT_EQ_0 ) d_init_cnt = 1;
end
always @(posedge CLK)
init_finished <= `D d_init_finished;
always @(init_finished or q_init_cnt or q_auto_ref or RC_CNT_EQ_0 ) begin
d_init_finished = init_finished;
if( q_init_cnt & q_auto_ref & RC_CNT_EQ_0 ) d_init_finished = 1;
end
/*=============================================================
+ set_mode_finished
+=============================================================*/
reg set_mode_finished = 1'b0;
always @(posedge CLK)
if(q_set_mode) set_mode_finished <= 1;
/*=============================================================
+ Counters
+=============================================================*/
wire start_ref_timing;
reg inhibit_new_cmd_reg = 1'b0;
wire inhibit_new_cmd = inhibit_new_cmd_reg;
assign RW = RD | WR;
reg D_RW = 1'b0;
wire D_RWt = D_RW;
wire st_break_rw = !RW & D_RWt;
always @(posedge CLK)
D_RW <= RW;
reg break_rw = 1'b0;
always @(posedge CLK)
if( q_row_active & st_break_rw ) break_rw <= 1;
else if( d_idle | q_precharge & d_row_active ) break_rw <= 0; // q_idle -->d_idle
wire RP_CNT_EQ_0;
reg [1:0] TIMING_CNT = 2'b0;
wire [1:0] TIMING_CNT_DEC_1 = (TIMING_CNT - 1'b1);
wire TIMING_CNT_EQ_0 = (TIMING_CNT == 2'b0);
wire TIMING_CNT_EQ_1 = (TIMING_CNT == 2'd1);
wire start_row_active = ( q_idle | q_precharge & RP_CNT_EQ_0 ) & !inhibit_new_cmd & RW;
always @(posedge CLK)
if(start_row_active) TIMING_CNT <= tRCD; // tRCD - 1
else if(!TIMING_CNT_EQ_0) TIMING_CNT <= TIMING_CNT_DEC_1;
reg S_PAA = 1'b0;
wire start_init_prech = PAA & !S_PAA;
always @( posedge CLK ) S_PAA <= `D PAA;
reg [1:0] RP_CNT = 2'b0;
wire [1:0] RP_CNT_DEC_1 = (RP_CNT - 1'b1);
assign RP_CNT_EQ_0 = (RP_CNT == 2'b0);
wire start_norm_precharge = ( q_rd | q_burst_term | q_row_active | q_rd2prech ) & d_precharge;
wire start_precharge = start_init_prech | start_norm_precharge;
always @(posedge CLK)
if(!RST_) RP_CNT <= 2'h3;
else if(start_precharge) RP_CNT <= tRP; // tRP - 1
else if(!RP_CNT_EQ_0) RP_CNT <= RP_CNT_DEC_1;
reg [3:0] RC_CNT = 4'b0;
wire [3:0] RC_CNT_DEC_1 = (RC_CNT - 1'b1);
assign RC_CNT_EQ_0 = (RC_CNT == 4'b0);
always @( posedge CLK)
if(start_ref_timing) RC_CNT <= tRC;
else if( !RC_CNT_EQ_0 ) RC_CNT <= RC_CNT_DEC_1;
reg [2:0] RAS_CNT = 3'b0;
wire [2:0] RAS_CNT_DEC_1 = (RAS_CNT - 1'b1);
wire RAS_CNT_EQ_0 = (RAS_CNT == 3'b0);
wire PRECHARGE_EN = RAS_CNT_EQ_0;
always @(posedge CLK)
if(start_row_active) RAS_CNT <= tRAS;
else if(!RAS_CNT_EQ_0) RAS_CNT <= RAS_CNT_DEC_1;
//reg [1:0] CAS_CNT;
//wire [1:0] CAS_CNT_DEC_1 = CAS_CNT - 1;
//wire CAS_CNT_EQ_0 = CAS_CNT == 0;
//wire CAS_CNT_EQ_1 = CAS_CNT == 1;
//wire start_fst_rd = RD & TIMING_CNT_EQ_0 & q_row_active & !break_rw;
//wire start_fst_wr = WR & TIMING_CNT_EQ_0 & q_row_active & !break_rw;
//always @(posedge CLK)
// if( !RST_ ) CAS_CNT <= 0;
// else if( start_fst_rd ) CAS_CNT <= tCAS;
// else if( !CAS_CNT_EQ_0 ) CAS_CNT <= CAS_CNT_DEC_1;
reg [2:0] CAS_CNT = 3'b0;
wire [2:0] CAS_CNT_DEC_1 = (CAS_CNT - 1'b1);
wire CAS_CNT_EQ_0 = (CAS_CNT == 3'd0);
wire CAS_CNT_EQ_1 = (CAS_CNT == 3'd1);
wire start_fst_rd = RD & TIMING_CNT_EQ_0 & q_row_active & !break_rw;
wire start_fst_wr = WR & TIMING_CNT_EQ_0 & q_row_active & !break_rw;
always @(posedge CLK)
if( start_fst_rd ) CAS_CNT <= tCAS + 2'b10;
else if( !CAS_CNT_EQ_0 ) CAS_CNT <= CAS_CNT_DEC_1;
reg [11:0] REF_CNT = 12'b0;
wire [11:0] REF_CNTt = REF_CNT;
wire [11:0] REF_CNT_DEC_1 = (REF_CNT - 1'b1);
//wire REF_CNT_EQ_0 = (REF_CNT == 12'b0);
reg REF_CNT_EQ_0 = 1'b0;
always @(posedge CLK)
if(REF_CNT == 12'b0) REF_CNT_EQ_0 <= `D 1'b1;
else if (d_auto_ref) REF_CNT_EQ_0 <= `D 1'b0;
//assign start_ref_timing = REF_CNT_EQ_0 | !init_finished & q_idle & d_auto_ref;
assign start_ref_timing = (REF_CNT_EQ_0 & d_auto_ref) | (!init_finished & q_idle & d_auto_ref);
always @( posedge CLK)
if( !PAA ) REF_CNT <= `D 12'hFFF;
else if( REF_CNT_EQ_0 ) REF_CNT <= `D tREF;
else REF_CNT <= `D REF_CNT_DEC_1;
always @( posedge CLK)
if( REF_CNTt == 10 ) inhibit_new_cmd_reg <= 1;
//else if( REF_CNT_EQ_0 ) inhibit_new_cmd_reg <= 0;
else if( REF_CNTt == (tREF - 3) ) inhibit_new_cmd_reg <= 0;
reg inhibit_rw_reg = 1'b0;
wire inhibit_rw = inhibit_rw_reg;
always @(posedge CLK)
if( q_rw & inhibit_new_cmd ) inhibit_rw_reg <= 1'b1;
else inhibit_rw_reg <= 1'b0;
reg s_init_finished = 1'b0;
wire st_init_finished = !s_init_finished & init_finished;
always @( posedge CLK )
s_init_finished <= `D init_finished;
reg [5:0] M_CNT;
wire M_CNT_EQ_0 = M_CNT == 0;
wire MUX_EN = M_CNT_EQ_0 & q_idle;
always @( posedge CLK)
if( !RST_ ) M_CNT <= `D 6'h2F;
else if( st_init_finished ) M_CNT <= `D 6'h00;
else if( REF_CNT == 32) M_CNT <= `D 6'h2F;
else if( !M_CNT_EQ_0 ) M_CNT <= `D (M_CNT - 1'b1);
/*=============================================================
+ BURST_CNT : BURST_CNT
+=============================================================*/
wire [2:0] BLK_LENGTH = BLK_SIZE == 3'b000 ? 0 :
BLK_SIZE == 3'b001 ? 1 :
BLK_SIZE == 3'b010 ? 3 : 7;
wire [2:0] blk_addr = BLK_SIZE == 3'b000 ? 0 :
BLK_SIZE == 3'b001 ? ADDR[2] :
BLK_SIZE == 3'b010 ? ADDR[3:2] : ADDR[4:2];
wire FULL_PAGE = BLK_SIZE == 3'b111;
wire page_boundary;
reg [2:0] BURST_CNT = 3'b0;
wire start_burst = ((tRCD == 0) & start_row_active) |
((tRCD == 1 | tRCD == 2) & TIMING_CNT_EQ_1 & q_row_active );
wire [2:0] BURST_CNT_DEC_1 = (BURST_CNT - 1'b1);
wire BURST_CNT_EQ_0 = (BURST_CNT == 3'd0);
wire BURST_CNT_EQ_1 = (BURST_CNT == 3'd1);
wire last_blk_word = BURST_CNT_EQ_0 & !FULL_PAGE;
always @( posedge CLK)
if( q_row_active & TIMING_CNT_EQ_0 | RW & BURST_CNT_EQ_0 & q_rw )
BURST_CNT <= BLK_LENGTH - blk_addr;
else if( !BURST_CNT_EQ_0 & BURST_RDY & !FULL_PAGE )
BURST_CNT <= BURST_CNT_DEC_1;
reg d_page_boundary;
always @( ADDR or COL_SIZE or CPU_GNT_ ) begin
case( COL_SIZE ) // synopsys parallel_case full_case
//2'b00: d_page_boundary = CPU_GNT_ & ( ADDR[ 9:2] == 8'hFF );
//2'b01: d_page_boundary = CPU_GNT_ & ( ADDR[10:2] == 9'h1FF );
//2'b10: d_page_boundary = CPU_GNT_ & ( ADDR[11:2] == 10'h3FF );
//2'b11: d_page_boundary = CPU_GNT_ & ( ADDR[12:2] == 11'h7FF );
2'b00: d_page_boundary = ( ADDR[ 9:2] == 8'hFF ); // add by dengshan 2009-8-11
2'b01: d_page_boundary = ( ADDR[10:2] == 9'h1FF );
2'b10: d_page_boundary = ( ADDR[11:2] == 10'h3FF );
2'b11: d_page_boundary = ( ADDR[12:2] == 11'h7FF );
endcase
end
reg page_boundary_reg = 1'b0;
assign page_boundary = page_boundary_reg;
always @(posedge CLK)
if( BURST_RDY & d_page_boundary ) page_boundary_reg <= 1;
else page_boundary_reg <= 0;
wire start_nxt_rd = RD & BURST_CNT_EQ_0 & !page_boundary &
!inhibit_rw & q_rd;
wire start_nxt_wr = WR & BURST_CNT_EQ_0 & !page_boundary &
!inhibit_rw & q_wr;
/*=============================================================
+ BURST_RDY, RD_DAT_RDY
+=============================================================*/
reg BURST_RDY_D = 1'b0;
wire BURST_RDY = RW & BURST_RDY_D ;
always @(posedge CLK)
if( start_burst & !( st_break_rw | break_rw ) )
BURST_RDY_D <= 1'b1;
else if( !RW | q_rw & inhibit_new_cmd | d_page_boundary )
BURST_RDY_D <= 1'b0;
reg DQ_OE = 1'b0;
wire BURST_RDYt = BURST_RDY;
always @(posedge CLK)
if( q_row_active & d_wr ) DQ_OE <= `D 1'b1;
else if( q_wr & d_burst_term ) DQ_OE <= `D 1'b0;
//reg [1:0] last_dat_cnt;
//wire last_dat_cnt_EQ_0 = last_dat_cnt == 0;
//wire last_dat_cnt_EQ_1 = last_dat_cnt == 1;
//wire [1:0] last_dat_cnt_dec_1 = last_dat_cnt - 1;
//wire lst_rd = q_rd & ( !RD | page_boundary | inhibit_rw ); // added 1110
//reg lst_rd_d; // added 1110
//wire st_lst_rd = lst_rd & !lst_rd_d; // added 1110
////always @(posedge CLK) lst_rd_d <= lst_rd; // added 1110
//always @(posedge CLK) lst_rd_d <= lst_rd; // added 1110
//
//always @(posedge CLK)
// if(!RST_) last_dat_cnt <= 0;
// else if(st_lst_rd) last_dat_cnt <= tCAS;// + 2'b10; // start_lst_rd --> st_lst_rd @ 1110
// else if(!last_dat_cnt_EQ_0) last_dat_cnt <= last_dat_cnt_dec_1;
reg [2:0] last_dat_cnt = 3'b0;
wire last_dat_cnt_EQ_0 = (last_dat_cnt == 3'b0);
wire last_dat_cnt_EQ_1 = (last_dat_cnt == 3'd1);
wire [2:0] last_dat_cnt_dec_1 = (last_dat_cnt - 1'b1);
wire lst_rd = q_rd & ( !RD | page_boundary | inhibit_rw ); // added 1110
reg lst_rd_d = 1'b0; // added 1110
wire st_lst_rd = lst_rd & !lst_rd_d; // added 1110
always @(posedge CLK)
lst_rd_d <= lst_rd; // added 1110
always @(posedge CLK)
if(st_lst_rd) last_dat_cnt <= tCAS + 2'b10; // start_lst_rd --> st_lst_rd @ 1110
else if(!last_dat_cnt_EQ_0) last_dat_cnt <= last_dat_cnt_dec_1;
reg Q_DAT_RDY = 1'b0;
wire DAT_RDY = Q_DAT_RDY;
always @(posedge CLK)
if(last_dat_cnt_EQ_1) Q_DAT_RDY <= 1'b0;
else if(CAS_CNT_EQ_1) Q_DAT_RDY <= 1'b1;
reg Q_RD_DAT_RDY = 1'b0;
wire RD_DAT_RDY = Q_RD_DAT_RDY;
always @(posedge CLK) Q_RD_DAT_RDY <= DAT_RDY;
/*=============================================================
+ [15:0] DAT : Data Output to Master/DIMM
+=============================================================*/
reg [15:0] DAT = 16'b0;
wire [15:0] DAT_O = DAT;
wire [15:0] DQ_O = DAT;
always @(posedge CLK)
if( DAT_RDY ) DAT <= `D DQ_I;
else if( d_wr | q_wr ) DAT <= `D DAT_I;
/*=============================================================
+ CKE : Clock Enable
+=============================================================*/
reg CKE = 1'b0;
always @(posedge CLK) begin
if(!RST_ ) CKE <= 1;
else if(STOP_CLK & q_idle) CKE <= 0;
end
/*=============================================================
+ RAS_ : Row Address Select
+=============================================================*/
reg Q_RAS_, D_RAS_;
wire RAS_ = Q_RAS_;
wire start_burst_term = d_burst_term & !q_burst_term;
wire start_rd = start_fst_rd | start_nxt_rd;
wire start_wr = start_fst_wr | start_nxt_wr;
wire start_rw = start_rd | start_wr;
always @( Q_RAS_ or start_precharge or start_ref_timing or
start_rw or start_row_active or d_set_mode or start_burst_term ) begin
D_RAS_ = Q_RAS_;
if(start_precharge | start_ref_timing |
start_row_active | d_set_mode ) D_RAS_ = 1'b0;
else if(start_rw | start_burst_term ) D_RAS_ = 1'b1;
end
wire D_RASt_ = D_RAS_;
always @(posedge CLK)
if(!RST_) Q_RAS_ <= `D 1'b1;
else Q_RAS_ <= `D D_RASt_;
/*=============================================================
+ CAS_ : Column Address Select
+=============================================================*/
reg Q_CAS_, D_CAS_;
wire CAS_ = Q_CAS_;
always @( Q_CAS_ or start_precharge or start_ref_timing or
start_rw or start_row_active or d_set_mode or start_burst_term ) begin
D_CAS_ = Q_CAS_;
if( start_ref_timing |
start_rw | d_set_mode ) D_CAS_ = 1'b0;
else if( start_precharge | start_row_active |
start_burst_term ) D_CAS_ = 1'b1;
end
wire D_CASt_ = D_CAS_;
always @(posedge CLK)
if(!RST_) Q_CAS_ <= `D 1;
else Q_CAS_ <= `D D_CASt_;
/*=============================================================
+ WE_ : Write Enable
+=============================================================*/
reg Q_WE_, D_WE_;
wire WE_ = Q_WE_;
always @( Q_WE_ or start_precharge or start_ref_timing or
start_rd or start_wr or start_row_active or d_idle or d_set_mode or start_burst_term ) begin
D_WE_ = Q_WE_;
if(start_precharge | start_wr | d_set_mode | start_burst_term) D_WE_ = 1'b0;
else if(start_ref_timing | start_row_active | start_rd | d_idle) D_WE_ = 1'b1;
end
wire D_WEt_ = D_WE_;
always @(posedge CLK)
if(!RST_) Q_WE_ <= `D 1'b1;
else Q_WE_ <= `D D_WEt_;
/*=============================================================
+ [3:0] DQM : Data I/O Mask
+=============================================================*/
reg Q_DQM;
wire DQM = Q_DQM;
always @(posedge CLK)
if( !RST_ ) Q_DQM <= `D 1;
else if( d_row_active ) Q_DQM <= `D 0;
/*=============================================================
+ [12:0] DIMM_ADDR : DIMM Row/Column Address
+ MODULE_BK_NUM : Module banks number
+ CS_ : Chip Select
+ [1:0] BA : Bank Address
+ [1:0] ROW_SIZE 2'b00 : A0-A10, 2'b01 : A0-A11
+ 2'b10 : A0-A12
+ [1:0] BIT_SIZE 2'b00 : 4, 2'b01 : 8
+ 2'b10 : 16(not supported), 2'b11 : 32(not supported)
+ BK_SIZE 2'b0 : BA0, 2'b1 : BA0-BA1
+ [1:0] COL_SIZE 2'b00 : A0-A7 3'b01: A0-A8
+ 2'b10 : A0-A9 3'b11: A0-A9,A11
+=============================================================*/
reg [12:0] Q_DIMM_ADDR = 13'b0, D_DIMM_ADDR;
reg Q_CS_ = 1'b0, D_CS_;
reg [1:0] Q_BA = 2'b0, D_BA;
assign DIMM_ADDR = Q_DIMM_ADDR;
assign CS_ = Q_CS_;
assign BA = Q_BA;
always @(posedge CLK) begin
Q_DIMM_ADDR <= `D D_DIMM_ADDR;
Q_CS_ <= `D D_CS_;
Q_BA <= `D D_BA;
end
always @(Q_BA or Q_CS_ or Q_DIMM_ADDR or PAA or
BK_SIZE or ROW_SIZE or start_row_active or start_init_prech or
BIT_SIZE or d_set_mode or start_precharge or
start_ref_timing or start_rw or start_norm_precharge or
ADDR or COL_SIZE or start_burst_term or tCAS or
IS_SEQ or BLK_SIZE) begin
D_DIMM_ADDR = Q_DIMM_ADDR;
D_CS_ = Q_CS_; D_BA = Q_BA;
case({BK_SIZE,ROW_SIZE,COL_SIZE,BIT_SIZE}) //synopsys parallel_case full_case
//8'b1_01_01_01: begin // 4 X 4K X 512 X 8
// if(start_init_prech | start_norm_precharge | d_set_mode | start_ref_timing | !PAA)
// D_CS_ = 1'b0;
// else if( start_row_active | start_rw | start_burst_term )
// D_CS_ = 1'b0;
// else D_CS_ = 1'b1;
// if( start_row_active | start_rw ) D_BA = ADDR[24:23];
// casex({start_row_active, start_rw, d_set_mode, start_precharge})
// 4'b0001: D_DIMM_ADDR[10] = 1'b1;
// 4'b001x: D_DIMM_ADDR ={ 6'b0, 1'b0, tCAS, IS_SEQ, BLK_SIZE };
// 4'b01xx: D_DIMM_ADDR = ADDR[10:2];
// default: D_DIMM_ADDR = ADDR[22:11];
// endcase
//end
//8'b1_01_10_00: begin // 4 X 4K X 1K X 4
// if(start_init_prech | start_norm_precharge | d_set_mode | start_ref_timing | !PAA)
// D_CS_ = 1'b0;
// else if( start_row_active | start_rw | start_burst_term )
// D_CS_ = 1'b0;
// else D_CS_ = 1'b1;
// if( start_row_active | start_rw ) D_BA = ADDR[25:24];
// casex({start_row_active, start_rw, d_set_mode, start_precharge})
// 4'b0001: D_DIMM_ADDR[10] = 1'b1;
// 4'b001x: D_DIMM_ADDR ={ 6'b0, 1'b0, tCAS, IS_SEQ, BLK_SIZE };
// 4'b01xx: D_DIMM_ADDR = ADDR[11:2];
// default: D_DIMM_ADDR = ADDR[23:12];
// endcase
//
//end
//8'b1_01_10_01: begin // 4 X 4K X 1K X 8
// if(start_init_prech | start_norm_precharge | d_set_mode | start_ref_timing | !PAA)
// D_CS_ = 1'b0;
// else if( start_row_active | start_rw | start_burst_term )
// D_CS_ = 1'b0;
// else D_CS_ = 1'b1;
// if( start_row_active | start_rw ) D_BA = ADDR[25:24];
// casex({start_row_active, start_rw, d_set_mode, start_precharge})
// 4'b0001: D_DIMM_ADDR[10] = 1'b1;
// 4'b001x: D_DIMM_ADDR ={ 6'b0, 1'b0, tCAS, IS_SEQ, BLK_SIZE };
// 4'b01xx: D_DIMM_ADDR = ADDR[11:2];
// default: D_DIMM_ADDR = ADDR[23:12];
// endcase
//
//end
//8'b1_01_11_01: begin // 4 X 4K X 2K X 4
// if(start_init_prech | start_norm_precharge | d_set_mode | start_ref_timing | !PAA)
// D_CS_ = 1'b0;
// else if( start_row_active | start_rw | start_burst_term )
// D_CS_ = 1'b0;
// else D_CS_ = 1'b1;
// if( start_row_active | start_rw ) D_BA = ADDR[26:25];
//
// casex({start_row_active, start_rw, d_set_mode, start_precharge})
// 4'b0001: D_DIMM_ADDR[10] = 1'b1;
// 4'b001x: D_DIMM_ADDR ={ 6'b0, 1'b0, tCAS, IS_SEQ, BLK_SIZE };
// 4'b01xx: D_DIMM_ADDR = {ADDR[12], 1'b0, ADDR[11:2]};
// default: D_DIMM_ADDR = ADDR[24:13];
// endcase
//
//end
//8'b1_10_01_10: begin // 4 X 8K X 512 X 16
// if(start_init_prech | start_norm_precharge | d_set_mode | start_ref_timing | !PAA)
// D_CS_ = 1'b0;
// else if( start_row_active | start_rw | start_burst_term )
// D_CS_ = 1'b0;
// else D_CS_ = 1'b1;
// if( start_row_active | start_rw ) D_BA = ADDR[25:24];
// casex({start_row_active, start_rw, d_set_mode, start_precharge})
// 4'b0001: D_DIMM_ADDR[10] = 1'b1;
// 4'b001x: D_DIMM_ADDR ={ 6'b0, 1'b0, tCAS, IS_SEQ, BLK_SIZE };
// 4'b01xx: D_DIMM_ADDR = ADDR[10: 2];
// default: D_DIMM_ADDR = ADDR[23:11];
// endcase
//end
//8'b1_10_10_01: begin // 4 X 8K X 1K X 8
// if(start_init_prech | start_norm_precharge | d_set_mode | start_ref_timing | !PAA)
// D_CS_ = 1'b0;
// else if( start_row_active | start_rw | start_burst_term )
// D_CS_ = 1'b0;
// else D_CS_ = 1'b1;
// if( start_row_active | start_rw ) D_BA = ADDR[26:25];
// casex({start_row_active, start_rw, d_set_mode, start_precharge})
// 4'b0001: D_DIMM_ADDR[10] = 1'b1;
// 4'b001x: D_DIMM_ADDR ={ 6'b0, 1'b0, tCAS, IS_SEQ, BLK_SIZE };
// 4'b01xx: D_DIMM_ADDR = ADDR[11:2];
// default: D_DIMM_ADDR = {1'b0, ADDR[24:12]};
// endcase
//
//end
//8'b1_10_11_00: begin // 4 X 8K X 2K X 4
// if(start_init_prech | start_norm_precharge | d_set_mode | start_ref_timing | !PAA)
// D_CS_ = 1'b0;
// else if( start_row_active | start_rw | start_burst_term )
// D_CS_ = 1'b0;
// else D_CS_ = 1'b1;
// if( start_row_active | start_rw ) D_BA = ADDR[27:26];
// casex({start_row_active, start_rw, d_set_mode, start_precharge})
// 4'b0001: D_DIMM_ADDR[10] = 1'b1;
// 4'b001x: D_DIMM_ADDR ={ 6'b0, 1'b0, tCAS, IS_SEQ, BLK_SIZE };
// 4'b01xx: D_DIMM_ADDR = {ADDR[12], 1'b0, ADDR[11:2]};
// default: D_DIMM_ADDR = ADDR[25:13];
// endcase
//
//end
//8'b1_00_00_11: begin
// if( start_init_prech | start_norm_precharge | d_set_mode | start_ref_timing | !PAA)
// D_CS_ = 1'b0;
// else if( start_row_active | start_rw | start_burst_term )
// D_CS_ = 1'b0;
// else D_CS_ = 1'b1;
// if( start_row_active | start_rw ) D_BA = ADDR[22:21];
// casex({start_row_active, start_rw, d_set_mode, start_precharge})
// 4'b0001: D_DIMM_ADDR[10] = 1'b1;
// 4'b001x: D_DIMM_ADDR ={ 6'b0, 1'b0, tCAS, IS_SEQ, BLK_SIZE };
// 4'b01xx: D_DIMM_ADDR = ADDR[9:2];
// default: D_DIMM_ADDR = ADDR[20:10];
// endcase
//
//end
default: begin
if(start_init_prech | start_norm_precharge | d_set_mode | start_ref_timing | !PAA)
D_CS_ = 1'b0;
else if( start_row_active | start_rw | start_burst_term )
D_CS_ = 1'b0;
else D_CS_ = 1'b1;
if( start_row_active | start_rw ) D_BA = ADDR[25:24];
casex({start_row_active, start_rw, d_set_mode, start_precharge})
4'b0001: D_DIMM_ADDR[10] = 1'b1;
4'b001x: D_DIMM_ADDR ={ 6'b0, 1'b0, tCAS, IS_SEQ, BLK_SIZE };
4'b01xx: D_DIMM_ADDR = ADDR[10:2];
default: D_DIMM_ADDR = ADDR[23:11];
endcase
end
endcase
end
/*=============================================================
+ Main State Machine(Mealy) of SDRAM Controller
+=============================================================*/
always @( Q_SD or init_finished or start_init_prech or
PAA or SET_MODE or RP_CNT_EQ_0 or
WR or TIMING_CNT_EQ_0 or page_boundary or
RD or last_blk_word or inhibit_new_cmd or
RW or set_mode_finished or REF_CNT_EQ_0 or
break_rw or inhibit_rw or PRECHARGE_EN or RC_CNT_EQ_0 ) begin
q_idle = 0;
q_rd = 0; q_precharge = 0;
q_wr = 0; q_row_active = 0;
q_auto_ref = 0; q_burst_term = 0;
q_set_mode = 0; q_rd2prech = 0;
d_idle = 0; d_precharge = 0;
d_set_mode = 0; d_burst_term = 0;
d_auto_ref = 0;
D_SD = Q_SD;
case (Q_SD) // synthesis parallel_case
SD_IDLE: begin
q_idle = 1;
if( start_init_prech ) begin
d_precharge = 1;
D_SD = SD_PRECHARGE;
end
else if( REF_CNT_EQ_0 & set_mode_finished | PAA & !init_finished ) begin
d_auto_ref = 1;
D_SD = SD_AUTO_REF;
end
else if(SET_MODE & init_finished & !set_mode_finished) begin
d_set_mode = 1;
D_SD = SD_SET_MODE;
end
else if(RW & !inhibit_new_cmd) begin
D_SD = SD_ROW_ACTIVE;
end
end
SD_SET_MODE: begin
q_set_mode = 1;
d_idle = 1;
D_SD = SD_IDLE;
end
SD_AUTO_REF: begin
q_auto_ref = 1;
if( RC_CNT_EQ_0 ) begin
d_idle = 1;
D_SD = SD_IDLE;
end
end
SD_ROW_ACTIVE: begin
q_row_active = 1;
if( TIMING_CNT_EQ_0 ) begin
if( RD & !break_rw ) D_SD = SD_READ;
else if( WR & !break_rw ) D_SD = SD_WRITE;
else if( break_rw & PRECHARGE_EN ) begin
d_precharge = 1; // add by jzhang 1010
D_SD = SD_PRECHARGE; // For RD/WR signal by jzhang @ 1109
end
end
end
SD_READ: begin
q_rd = 1;
if( last_blk_word & ( !RD | inhibit_rw ) | page_boundary ) begin
if( PRECHARGE_EN ) begin
d_precharge = 1;
D_SD = SD_PRECHARGE;
end
else D_SD = SD_RD2PRECH;
end
else if(!RD | inhibit_rw ) begin
d_burst_term = 1;
D_SD = SD_BURST_TERM;
end
end
SD_WRITE: begin
q_wr = 1;
if( page_boundary |!WR | inhibit_rw ) begin //tWR > 1
d_burst_term = 1;
D_SD = SD_BURST_TERM;
end
end
SD_BURST_TERM: begin
q_burst_term = 1;
d_precharge = 1;
D_SD = SD_PRECHARGE;
end
SD_RD2PRECH : begin
q_rd2prech = 1;
if( PRECHARGE_EN ) begin
d_precharge = 1;
D_SD = SD_PRECHARGE;
end
end
SD_PRECHARGE: begin
q_precharge = 1;
if( RP_CNT_EQ_0 ) begin
if(RW & !inhibit_new_cmd) begin
D_SD = SD_ROW_ACTIVE;
end
else begin
d_idle = 1;
D_SD = SD_IDLE;
end
end
end
default: begin
d_idle = 1;
D_SD = SD_IDLE;
end
endcase
end
wire [8:0] D_SDt = D_SD;
always @(posedge CLK) begin
if(!RST_) Q_SD <= `D SD_IDLE;
else Q_SD <= `D D_SDt;
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_pipe_sync.v
// Version : 4.1
//----------------------------------------------------------------------------//
// Filename : pcie3_7x_0_pipe_sync.v
// Description : PIPE Sync Module for 7 Series Transceiver
// Version : 20.1
//------------------------------------------------------------------------------
// PCIE_TXSYNC_MODE : 0 = Manual TX sync (default).
// : 1 = Auto TX sync.
// PCIE_RXSYNC_MODE : 0 = Manual RX sync (default).
// : 1 = Auto RX sync.
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE Sync Module --------------------------------------------------
module pcie3_7x_0_pipe_sync #
(
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
parameter PCIE_RXBUF_EN = "TRUE", // PCIe TX buffer enable for Gen3 only
parameter PCIE_TXSYNC_MODE = 0, // PCIe TX sync mode
parameter PCIE_RXSYNC_MODE = 0, // PCIe RX sync mode
parameter PCIE_LANE = 1, // PCIe lane
parameter PCIE_LINK_SPEED = 3, // PCIe link speed
parameter BYPASS_TXDELAY_ALIGN = 0, // Bypass TX delay align
parameter BYPASS_RXDELAY_ALIGN = 0 // Bypass RX delay align
)
(
//---------- Input -------------------------------------
input SYNC_CLK,
input SYNC_RST_N,
input SYNC_SLAVE,
input SYNC_GEN3,
input SYNC_RATE_IDLE,
input SYNC_MMCM_LOCK,
input SYNC_RXELECIDLE,
input SYNC_RXCDRLOCK,
input SYNC_ACTIVE_LANE,
input SYNC_TXSYNC_START,
input SYNC_TXPHINITDONE,
input SYNC_TXDLYSRESETDONE,
input SYNC_TXPHALIGNDONE,
input SYNC_TXSYNCDONE,
input SYNC_RXSYNC_START,
input SYNC_RXDLYSRESETDONE,
input SYNC_RXPHALIGNDONE_M,
input SYNC_RXPHALIGNDONE_S,
input SYNC_RXSYNC_DONEM_IN,
input SYNC_RXSYNCDONE,
//---------- Output ------------------------------------
output SYNC_TXPHDLYRESET,
output SYNC_TXPHALIGN,
output SYNC_TXPHALIGNEN,
output SYNC_TXPHINIT,
output SYNC_TXDLYBYPASS,
output SYNC_TXDLYSRESET,
output SYNC_TXDLYEN,
output SYNC_TXSYNC_DONE,
output [ 5:0] SYNC_FSM_TX,
output SYNC_RXPHALIGN,
output SYNC_RXPHALIGNEN,
output SYNC_RXDLYBYPASS,
output SYNC_RXDLYSRESET,
output SYNC_RXDLYEN,
output SYNC_RXDDIEN,
output SYNC_RXSYNC_DONEM_OUT,
output SYNC_RXSYNC_DONE,
output [ 6:0] SYNC_FSM_RX
);
//---------- Input Register ----------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxelecidle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxelecidle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_start_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphinitdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txdlysresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphaligndone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsyncdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_start_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphinitdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txdlysresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphaligndone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsyncdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_start_reg3;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphinitdone_reg3;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txdlysresetdone_reg3;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphaligndone_reg3;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsyncdone_reg3;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_start_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxdlysresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_m_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_s_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_donem_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsyncdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_start_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxdlysresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_m_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_s_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_donem_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsyncdone_reg2;
//---------- Output Register ---------------------------
reg txdlyen = 1'd0;
reg txsync_done = 1'd0;
reg [ 5:0] fsm_tx = 6'd0;
reg rxdlyen = 1'd0;
reg rxsync_done = 1'd0;
reg [ 6:0] fsm_rx = 7'd0;
//---------- FSM ---------------------------------------
localparam FSM_TXSYNC_IDLE = 6'b000001;
localparam FSM_MMCM_LOCK = 6'b000010;
localparam FSM_TXSYNC_START = 6'b000100;
localparam FSM_TXPHINITDONE = 6'b001000; // Manual TX sync only
localparam FSM_TXSYNC_DONE1 = 6'b010000;
localparam FSM_TXSYNC_DONE2 = 6'b100000;
localparam FSM_RXSYNC_IDLE = 7'b0000001;
localparam FSM_RXCDRLOCK = 7'b0000010;
localparam FSM_RXSYNC_START = 7'b0000100;
localparam FSM_RXSYNC_DONE1 = 7'b0001000;
localparam FSM_RXSYNC_DONE2 = 7'b0010000;
localparam FSM_RXSYNC_DONES = 7'b0100000;
localparam FSM_RXSYNC_DONEM = 7'b1000000;
//---------- Input FF ----------------------------------------------------------
always @ (posedge SYNC_CLK)
begin
if (!SYNC_RST_N)
begin
//---------- 1st Stage FF --------------------------
gen3_reg1 <= 1'd0;
rate_idle_reg1 <= 1'd0;
mmcm_lock_reg1 <= 1'd0;
rxelecidle_reg1 <= 1'd0;
rxcdrlock_reg1 <= 1'd0;
txsync_start_reg1 <= 1'd0;
txphinitdone_reg1 <= 1'd0;
txdlysresetdone_reg1 <= 1'd0;
txphaligndone_reg1 <= 1'd0;
txsyncdone_reg1 <= 1'd0;
rxsync_start_reg1 <= 1'd0;
rxdlysresetdone_reg1 <= 1'd0;
rxphaligndone_m_reg1 <= 1'd0;
rxphaligndone_s_reg1 <= 1'd0;
rxsync_donem_reg1 <= 1'd0;
rxsyncdone_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
gen3_reg2 <= 1'd0;
rate_idle_reg2 <= 1'd0;
mmcm_lock_reg2 <= 1'd0;
rxelecidle_reg2 <= 1'd0;
rxcdrlock_reg2 <= 1'd0;
txsync_start_reg2 <= 1'd0;
txphinitdone_reg2 <= 1'd0;
txdlysresetdone_reg2 <= 1'd0;
txphaligndone_reg2 <= 1'd0;
txsyncdone_reg2 <= 1'd0;
rxsync_start_reg2 <= 1'd0;
rxdlysresetdone_reg2 <= 1'd0;
rxphaligndone_m_reg2 <= 1'd0;
rxphaligndone_s_reg2 <= 1'd0;
rxsync_donem_reg2 <= 1'd0;
rxsyncdone_reg2 <= 1'd0;
//---------- 3rd Stage FF --------------------------
txsync_start_reg3 <= 1'd0;
txphinitdone_reg3 <= 1'd0;
txdlysresetdone_reg3 <= 1'd0;
txphaligndone_reg3 <= 1'd0;
txsyncdone_reg3 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
gen3_reg1 <= SYNC_GEN3;
rate_idle_reg1 <= SYNC_RATE_IDLE;
mmcm_lock_reg1 <= SYNC_MMCM_LOCK;
rxelecidle_reg1 <= SYNC_RXELECIDLE;
rxcdrlock_reg1 <= SYNC_RXCDRLOCK;
txsync_start_reg1 <= SYNC_TXSYNC_START;
txphinitdone_reg1 <= SYNC_TXPHINITDONE;
txdlysresetdone_reg1 <= SYNC_TXDLYSRESETDONE;
txphaligndone_reg1 <= SYNC_TXPHALIGNDONE;
txsyncdone_reg1 <= SYNC_TXSYNCDONE;
rxsync_start_reg1 <= SYNC_RXSYNC_START;
rxdlysresetdone_reg1 <= SYNC_RXDLYSRESETDONE;
rxphaligndone_m_reg1 <= SYNC_RXPHALIGNDONE_M;
rxphaligndone_s_reg1 <= SYNC_RXPHALIGNDONE_S;
rxsync_donem_reg1 <= SYNC_RXSYNC_DONEM_IN;
rxsyncdone_reg1 <= SYNC_RXSYNCDONE;
//---------- 2nd Stage FF --------------------------
gen3_reg2 <= gen3_reg1;
rate_idle_reg2 <= rate_idle_reg1;
mmcm_lock_reg2 <= mmcm_lock_reg1;
rxelecidle_reg2 <= rxelecidle_reg1;
rxcdrlock_reg2 <= rxcdrlock_reg1;
txsync_start_reg2 <= txsync_start_reg1;
txphinitdone_reg2 <= txphinitdone_reg1;
txdlysresetdone_reg2 <= txdlysresetdone_reg1;
txphaligndone_reg2 <= txphaligndone_reg1;
txsyncdone_reg2 <= txsyncdone_reg1;
rxsync_start_reg2 <= rxsync_start_reg1;
rxdlysresetdone_reg2 <= rxdlysresetdone_reg1;
rxphaligndone_m_reg2 <= rxphaligndone_m_reg1;
rxphaligndone_s_reg2 <= rxphaligndone_s_reg1;
rxsync_donem_reg2 <= rxsync_donem_reg1;
rxsyncdone_reg2 <= rxsyncdone_reg1;
//---------- 3rd Stage FF --------------------------
txsync_start_reg3 <= txsync_start_reg2;
txphinitdone_reg3 <= txphinitdone_reg2;
txdlysresetdone_reg3 <= txdlysresetdone_reg2;
txphaligndone_reg3 <= txphaligndone_reg2;
txsyncdone_reg3 <= txsyncdone_reg2;
end
end
//---------- Generate TX Sync FSM ----------------------------------------------
generate if ((PCIE_LINK_SPEED == 3) || (PCIE_TXBUF_EN == "FALSE"))
begin : txsync_fsm
//---------- PIPE TX Sync FSM ----------------------------------------------
always @ (posedge SYNC_CLK)
begin
if (!SYNC_RST_N)
begin
fsm_tx <= FSM_TXSYNC_IDLE;
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
else
begin
case (fsm_tx)
//---------- Idle State ------------------------
FSM_TXSYNC_IDLE :
begin
//---------- Exiting Reset or Rate Change --
if (txsync_start_reg2)
begin
fsm_tx <= FSM_MMCM_LOCK;
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
else
begin
fsm_tx <= FSM_TXSYNC_IDLE;
txdlyen <= txdlyen;
txsync_done <= txsync_done;
end
end
//---------- Check MMCM Lock -------------------
FSM_MMCM_LOCK :
begin
fsm_tx <= (mmcm_lock_reg2 ? FSM_TXSYNC_START : FSM_MMCM_LOCK);
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
//---------- TX Delay Soft Reset ---------------
FSM_TXSYNC_START :
begin
fsm_tx <= (((!txdlysresetdone_reg3 && txdlysresetdone_reg2) || (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE)) ? FSM_TXPHINITDONE : FSM_TXSYNC_START);
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
//---------- Wait for TX Phase Init Done (Manual Mode Only)
FSM_TXPHINITDONE :
begin
fsm_tx <= (((!txphinitdone_reg3 && txphinitdone_reg2) || (PCIE_TXSYNC_MODE == 1) || (!SYNC_ACTIVE_LANE)) ? FSM_TXSYNC_DONE1 : FSM_TXPHINITDONE);
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
//---------- Wait for TX Phase Alignment Done --
FSM_TXSYNC_DONE1 :
begin
if (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && !SYNC_SLAVE)
fsm_tx <= ((!txsyncdone_reg3 && txsyncdone_reg2) || (!SYNC_ACTIVE_LANE) ? FSM_TXSYNC_DONE2 : FSM_TXSYNC_DONE1);
else
fsm_tx <= ((!txphaligndone_reg3 && txphaligndone_reg2) || (!SYNC_ACTIVE_LANE) ? FSM_TXSYNC_DONE2 : FSM_TXSYNC_DONE1);
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
//---------- Wait for Master TX Delay Alignment Done
FSM_TXSYNC_DONE2 :
begin
if ((!txphaligndone_reg3 && txphaligndone_reg2) || (!SYNC_ACTIVE_LANE) || SYNC_SLAVE || (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1)) || (BYPASS_TXDELAY_ALIGN == 1))
begin
fsm_tx <= FSM_TXSYNC_IDLE;
txdlyen <= !SYNC_SLAVE;
txsync_done <= 1'd1;
end
else
begin
fsm_tx <= FSM_TXSYNC_DONE2;
txdlyen <= !SYNC_SLAVE;
txsync_done <= 1'd0;
end
end
//---------- Default State ---------------------
default :
begin
fsm_tx <= FSM_TXSYNC_IDLE;
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
endcase
end
end
end
//---------- TX Sync FSM Default------------------------------------------------
else
begin : txsync_fsm_disable
//---------- Default -------------------------------------------------------
always @ (posedge SYNC_CLK)
begin
fsm_tx <= FSM_TXSYNC_IDLE;
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
end
endgenerate
//---------- Generate RX Sync FSM ----------------------------------------------
generate if ((PCIE_LINK_SPEED == 3) && (PCIE_RXBUF_EN == "FALSE"))
begin : rxsync_fsm
//---------- PIPE RX Sync FSM ----------------------------------------------
always @ (posedge SYNC_CLK)
begin
if (!SYNC_RST_N)
begin
fsm_rx <= FSM_RXSYNC_IDLE;
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
else
begin
case (fsm_rx)
//---------- Idle State ------------------------
FSM_RXSYNC_IDLE :
begin
//---------- Exiting Rate Change -----------
if (rxsync_start_reg2)
begin
fsm_rx <= FSM_RXCDRLOCK;
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
//---------- Exiting Electrical Idle without Rate Change
else if (gen3_reg2 && rate_idle_reg2 && ((rxelecidle_reg2 == 1'd1) && (rxelecidle_reg1 == 1'd0)))
begin
fsm_rx <= FSM_RXCDRLOCK;
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
//---------- Idle --------------------------
else
begin
fsm_rx <= FSM_RXSYNC_IDLE;
rxdlyen <= rxelecidle_reg2 ? 1'd0 : rxdlyen;
rxsync_done <= rxelecidle_reg2 ? 1'd0 : rxsync_done;
end
end
//---------- Wait for RX Electrical Idle Exit and RX CDR Lock
FSM_RXCDRLOCK :
begin
fsm_rx <= ((!rxelecidle_reg2 && rxcdrlock_reg2) ? FSM_RXSYNC_START : FSM_RXCDRLOCK);
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
//---------- Start RX Sync with RX Delay Soft Reset
FSM_RXSYNC_START :
begin
fsm_rx <= ((!rxdlysresetdone_reg2 && rxdlysresetdone_reg1) ? FSM_RXSYNC_DONE1 : FSM_RXSYNC_START);
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
//---------- Wait for RX Phase Alignment Done --
FSM_RXSYNC_DONE1 :
begin
if (SYNC_SLAVE)
begin
fsm_rx <= ((!rxphaligndone_s_reg2 && rxphaligndone_s_reg1) ? FSM_RXSYNC_DONE2 : FSM_RXSYNC_DONE1);
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
else
begin
fsm_rx <= ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) ? FSM_RXSYNC_DONE2 : FSM_RXSYNC_DONE1);
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
end
//---------- Wait for Master RX Delay Alignment Done
FSM_RXSYNC_DONE2 :
begin
if (SYNC_SLAVE)
begin
fsm_rx <= FSM_RXSYNC_IDLE;
rxdlyen <= 1'd0;
rxsync_done <= 1'd1;
end
else if ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) || (BYPASS_RXDELAY_ALIGN == 1))
begin
fsm_rx <= ((PCIE_LANE == 1) ? FSM_RXSYNC_IDLE : FSM_RXSYNC_DONES);
rxdlyen <= (PCIE_LANE == 1);
rxsync_done <= (PCIE_LANE == 1);
end
else
begin
fsm_rx <= FSM_RXSYNC_DONE2;
rxdlyen <= 1'd1;
rxsync_done <= 1'd0;
end
end
//---------- Wait for Slave RX Phase Alignment Done
FSM_RXSYNC_DONES :
begin
if (!rxphaligndone_s_reg2 && rxphaligndone_s_reg1)
begin
fsm_rx <= FSM_RXSYNC_DONEM;
rxdlyen <= 1'd1;
rxsync_done <= 1'd0;
end
else
begin
fsm_rx <= FSM_RXSYNC_DONES;
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
end
//---------- Wait for Master RX Delay Alignment Done
FSM_RXSYNC_DONEM :
begin
if ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) || (BYPASS_RXDELAY_ALIGN == 1))
begin
fsm_rx <= FSM_RXSYNC_IDLE;
rxdlyen <= 1'd1;
rxsync_done <= 1'd1;
end
else
begin
fsm_rx <= FSM_RXSYNC_DONEM;
rxdlyen <= 1'd1;
rxsync_done <= 1'd0;
end
end
//---------- Default State ---------------------
default :
begin
fsm_rx <= FSM_RXSYNC_IDLE;
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
endcase
end
end
end
//---------- RX Sync FSM Default -----------------------------------------------
else
begin : rxsync_fsm_disable
//---------- Default -------------------------------------------------------
always @ (posedge SYNC_CLK)
begin
fsm_rx <= FSM_RXSYNC_IDLE;
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
end
endgenerate
//---------- PIPE Sync Output --------------------------------------------------
assign SYNC_TXPHALIGNEN = ((PCIE_TXSYNC_MODE == 1) || (!gen3_reg2 && (PCIE_TXBUF_EN == "TRUE"))) ? 1'd0 : 1'd1;
assign SYNC_TXDLYBYPASS = 1'd0;
//assign SYNC_TXDLYSRESET = !(((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE) ? (fsm_tx == FSM_TXSYNC_START) : 1'd0;
assign SYNC_TXDLYSRESET = (fsm_tx == FSM_TXSYNC_START);
assign SYNC_TXPHDLYRESET = (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE) ? (fsm_tx == FSM_TXSYNC_START) : 1'd0;
assign SYNC_TXPHINIT = PCIE_TXSYNC_MODE ? 1'd0 : (fsm_tx == FSM_TXPHINITDONE);
assign SYNC_TXPHALIGN = PCIE_TXSYNC_MODE ? 1'd0 : (fsm_tx == FSM_TXSYNC_DONE1);
assign SYNC_TXDLYEN = PCIE_TXSYNC_MODE ? 1'd0 : txdlyen;
assign SYNC_TXSYNC_DONE = txsync_done;
assign SYNC_FSM_TX = fsm_tx;
assign SYNC_RXPHALIGNEN = ((PCIE_RXSYNC_MODE == 1) || (!gen3_reg2) || (PCIE_RXBUF_EN == "TRUE")) ? 1'd0 : 1'd1;
assign SYNC_RXDLYBYPASS = !gen3_reg2 || (PCIE_RXBUF_EN == "TRUE");
assign SYNC_RXDLYSRESET = (fsm_rx == FSM_RXSYNC_START);
assign SYNC_RXPHALIGN = PCIE_RXSYNC_MODE ? 1'd0 : (!SYNC_SLAVE ? (fsm_rx == FSM_RXSYNC_DONE1) : (rxsync_donem_reg2 && (fsm_rx == FSM_RXSYNC_DONE1)));
assign SYNC_RXDLYEN = PCIE_RXSYNC_MODE ? 1'd0 : rxdlyen;
assign SYNC_RXDDIEN = gen3_reg2 && (PCIE_RXBUF_EN == "FALSE");
assign SYNC_RXSYNC_DONE = rxsync_done;
assign SYNC_RXSYNC_DONEM_OUT = (fsm_rx == FSM_RXSYNC_DONES);
assign SYNC_FSM_RX = fsm_rx;
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Tue May 13 23:58:38 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode funcsim
// /home/keith/Documents/VHDL-lib/top/lab_5/part_3/ip/clk_base/clk_base_funcsim.v
// Design : clk_base
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* core_generation_info = "clk_base,clk_wiz_v5_1,{component_name=clk_base,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
(* NotValidForBitStream *)
module clk_base
(clk_raw,
clk_250MHz,
locked);
input clk_raw;
output clk_250MHz;
output locked;
wire clk_250MHz;
(* IBUF_LOW_PWR *) wire clk_raw;
wire locked;
clk_baseclk_base_clk_wiz U0
(.clk_250MHz(clk_250MHz),
.clk_raw(clk_raw),
.locked(locked));
endmodule
(* ORIG_REF_NAME = "clk_base_clk_wiz" *)
module clk_baseclk_base_clk_wiz
(clk_raw,
clk_250MHz,
locked);
input clk_raw;
output clk_250MHz;
output locked;
wire clk_250MHz;
wire clk_250MHz_clk_base;
(* IBUF_LOW_PWR *) wire clk_raw;
wire clk_raw_clk_base;
wire clkfbout_buf_clk_base;
wire clkfbout_clk_base;
wire locked;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* box_type = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_clk_base),
.O(clkfbout_buf_clk_base));
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
(* box_type = "PRIMITIVE" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_raw),
.O(clk_raw_clk_base));
(* box_type = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_250MHz_clk_base),
.O(clk_250MHz));
(* box_type = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(10.000000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(4.000000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(1),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.000000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_clk_base),
.CLKFBOUT(clkfbout_clk_base),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_raw_clk_base),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_250MHz_clk_base),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A32O_BLACKBOX_V
`define SKY130_FD_SC_MS__A32O_BLACKBOX_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a32o (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A32O_BLACKBOX_V
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_cpu_s1_mult_cell (
// inputs:
A_mul_src1,
A_mul_src2,
clk,
reset_n,
// outputs:
A_mul_cell_result
)
;
output [ 31: 0] A_mul_cell_result;
input [ 31: 0] A_mul_src1;
input [ 31: 0] A_mul_src2;
input clk;
input reset_n;
wire [ 31: 0] A_mul_cell_result;
wire [ 31: 0] A_mul_cell_result_part_1;
wire [ 15: 0] A_mul_cell_result_part_2;
wire mul_clr;
assign mul_clr = ~reset_n;
altera_mult_add the_altmult_add_part_1
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (A_mul_src1[15 : 0]),
.datab (A_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (A_mul_cell_result_part_1)
);
defparam the_altmult_add_part_1.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_1.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_1.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_1.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_1.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_1.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_1.input_source_a0 = "DATAA",
the_altmult_add_part_1.input_source_b0 = "DATAB",
the_altmult_add_part_1.lpm_type = "altera_mult_add",
the_altmult_add_part_1.multiplier1_direction = "ADD",
the_altmult_add_part_1.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_1.multiplier_register0 = "CLOCK0",
the_altmult_add_part_1.number_of_multipliers = 1,
the_altmult_add_part_1.output_register = "UNREGISTERED",
the_altmult_add_part_1.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_1.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_part_1.port_signa = "PORT_UNUSED",
the_altmult_add_part_1.port_signb = "PORT_UNUSED",
the_altmult_add_part_1.representation_a = "UNSIGNED",
the_altmult_add_part_1.representation_b = "UNSIGNED",
the_altmult_add_part_1.selected_device_family = "CYCLONEV",
the_altmult_add_part_1.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_1.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_1.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_1.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_1.signed_register_a = "UNREGISTERED",
the_altmult_add_part_1.signed_register_b = "UNREGISTERED",
the_altmult_add_part_1.width_a = 16,
the_altmult_add_part_1.width_b = 16,
the_altmult_add_part_1.width_result = 32;
altera_mult_add the_altmult_add_part_2
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (A_mul_src1[31 : 16]),
.datab (A_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (A_mul_cell_result_part_2)
);
defparam the_altmult_add_part_2.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_2.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_2.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_2.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_2.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_2.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_2.input_source_a0 = "DATAA",
the_altmult_add_part_2.input_source_b0 = "DATAB",
the_altmult_add_part_2.lpm_type = "altera_mult_add",
the_altmult_add_part_2.multiplier1_direction = "ADD",
the_altmult_add_part_2.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_2.multiplier_register0 = "CLOCK0",
the_altmult_add_part_2.number_of_multipliers = 1,
the_altmult_add_part_2.output_register = "UNREGISTERED",
the_altmult_add_part_2.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_2.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_part_2.port_signa = "PORT_UNUSED",
the_altmult_add_part_2.port_signb = "PORT_UNUSED",
the_altmult_add_part_2.representation_a = "UNSIGNED",
the_altmult_add_part_2.representation_b = "UNSIGNED",
the_altmult_add_part_2.selected_device_family = "CYCLONEV",
the_altmult_add_part_2.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_2.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_2.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_2.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_2.signed_register_a = "UNREGISTERED",
the_altmult_add_part_2.signed_register_b = "UNREGISTERED",
the_altmult_add_part_2.width_a = 16,
the_altmult_add_part_2.width_b = 16,
the_altmult_add_part_2.width_result = 16;
assign A_mul_cell_result = {A_mul_cell_result_part_1[31 : 16] +
A_mul_cell_result_part_2,
A_mul_cell_result_part_1[15 : 0]};
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPVPWRVGND_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__TAPVPWRVGND_PP_BLACKBOX_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__tapvpwrvgnd (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPVPWRVGND_PP_BLACKBOX_V
|
//--------------------------------------------------------------------------------
// flags.vhd
//
// Copyright (C) 2006 Michael Poppitz
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details: http://www.sump.org/projects/analyzer/
//
// Flags register.
//
//--------------------------------------------------------------------------------
//
// 12/29/2010 - Verilog Version + cleanups created by Ian Davis - mygizmos.org
//
`timescale 1ns/100ps
module flags(
clock, wrFlags, config_data,
finish_now,
// outputs
flags_reg);
input clock;
input wrFlags;
input [31:0] config_data;
input finish_now;
output [31:0] flags_reg;
reg [31:0] flags_reg, next_flags_reg;
//
// Write flags register...
//
initial flags_reg = 0;
always @(posedge clock)
begin
flags_reg = next_flags_reg;
end
always @*
begin
#1;
next_flags_reg = (wrFlags) ? config_data : flags_reg;
if (finish_now) next_flags_reg[8] = 1'b0;
end
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module aesl_mux_load_7_3_x_s (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
empty_2_Addr_A,
empty_2_EN_A,
empty_2_WEN_A,
empty_2_Din_A,
empty_2_Dout_A,
empty_3_Addr_A,
empty_3_EN_A,
empty_3_WEN_A,
empty_3_Din_A,
empty_3_Dout_A,
empty_4_Addr_A,
empty_4_EN_A,
empty_4_WEN_A,
empty_4_Din_A,
empty_4_Dout_A,
empty_5_Addr_A,
empty_5_EN_A,
empty_5_WEN_A,
empty_5_Din_A,
empty_5_Dout_A,
empty_6_Addr_A,
empty_6_EN_A,
empty_6_WEN_A,
empty_6_Din_A,
empty_6_Dout_A,
empty_7_Addr_A,
empty_7_EN_A,
empty_7_WEN_A,
empty_7_Din_A,
empty_7_Dout_A,
empty_8_Addr_A,
empty_8_EN_A,
empty_8_WEN_A,
empty_8_Din_A,
empty_8_Dout_A,
empty_9,
empty_10,
empty,
ap_return
);
parameter ap_ST_fsm_pp0_stage0 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
output [31:0] empty_2_Addr_A;
output empty_2_EN_A;
output [3:0] empty_2_WEN_A;
output [31:0] empty_2_Din_A;
input [31:0] empty_2_Dout_A;
output [31:0] empty_3_Addr_A;
output empty_3_EN_A;
output [3:0] empty_3_WEN_A;
output [31:0] empty_3_Din_A;
input [31:0] empty_3_Dout_A;
output [31:0] empty_4_Addr_A;
output empty_4_EN_A;
output [3:0] empty_4_WEN_A;
output [31:0] empty_4_Din_A;
input [31:0] empty_4_Dout_A;
output [31:0] empty_5_Addr_A;
output empty_5_EN_A;
output [3:0] empty_5_WEN_A;
output [31:0] empty_5_Din_A;
input [31:0] empty_5_Dout_A;
output [31:0] empty_6_Addr_A;
output empty_6_EN_A;
output [3:0] empty_6_WEN_A;
output [31:0] empty_6_Din_A;
input [31:0] empty_6_Dout_A;
output [31:0] empty_7_Addr_A;
output empty_7_EN_A;
output [3:0] empty_7_WEN_A;
output [31:0] empty_7_Din_A;
input [31:0] empty_7_Dout_A;
output [31:0] empty_8_Addr_A;
output empty_8_EN_A;
output [3:0] empty_8_WEN_A;
output [31:0] empty_8_Din_A;
input [31:0] empty_8_Dout_A;
input [2:0] empty_9;
input [1:0] empty_10;
input [2:0] empty;
output [31:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg empty_2_EN_A;
reg empty_3_EN_A;
reg empty_4_EN_A;
reg empty_5_EN_A;
reg empty_6_EN_A;
reg empty_7_EN_A;
reg empty_8_EN_A;
(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_pp0_stage0;
wire ap_enable_reg_pp0_iter0;
wire ap_block_pp0_stage0_flag00000000;
reg ap_enable_reg_pp0_iter1;
reg ap_enable_reg_pp0_iter2;
reg ap_enable_reg_pp0_iter3;
reg ap_enable_reg_pp0_iter4;
reg ap_idle_pp0;
reg ap_block_state1_pp0_stage0_iter0;
wire ap_block_state2_pp0_stage0_iter1;
wire ap_block_state3_pp0_stage0_iter2;
wire ap_block_state4_pp0_stage0_iter3;
wire ap_block_state5_pp0_stage0_iter4;
reg ap_block_pp0_stage0_flag00011001;
reg [2:0] tmp_15_reg_246;
reg [2:0] ap_reg_pp0_iter1_tmp_15_reg_246;
reg [2:0] ap_reg_pp0_iter2_tmp_15_reg_246;
wire [31:0] tmp_22_fu_174_p2;
reg [31:0] tmp_22_reg_256;
reg [31:0] ap_reg_pp0_iter1_tmp_22_reg_256;
reg [31:0] empty_21_reg_302;
reg [31:0] empty_22_reg_307;
reg [31:0] empty_23_reg_312;
reg [31:0] empty_24_reg_317;
reg [31:0] empty_25_reg_322;
reg [31:0] empty_26_reg_327;
reg [31:0] empty_27_reg_332;
wire [31:0] sel_tmp3_fu_196_p3;
reg [31:0] sel_tmp3_reg_337;
wire [0:0] sel_tmp4_fu_203_p2;
reg [0:0] sel_tmp4_reg_342;
wire [0:0] sel_tmp6_fu_208_p2;
reg [0:0] sel_tmp6_reg_347;
wire [0:0] sel_tmp8_fu_213_p2;
reg [0:0] sel_tmp8_reg_352;
wire [0:0] sel_tmp10_fu_218_p2;
reg [0:0] sel_tmp10_reg_357;
reg ap_block_pp0_stage0_flag00011011;
wire [4:0] tmp_fu_156_p3;
wire [31:0] p_shl_fu_164_p1;
wire [31:0] p_cast_fu_152_p1;
wire [31:0] p_cast1_fu_148_p1;
wire [31:0] tmp_21_fu_168_p2;
wire [0:0] sel_tmp_fu_180_p2;
wire [0:0] sel_tmp2_fu_191_p2;
wire [31:0] sel_tmp1_fu_185_p3;
wire [31:0] sel_tmp5_fu_223_p3;
wire [31:0] sel_tmp7_fu_228_p3;
wire [31:0] sel_tmp9_fu_234_p3;
reg [0:0] ap_NS_fsm;
reg ap_idle_pp0_0to3;
reg ap_reset_idle_pp0;
wire ap_enable_pp0;
// power-on initialization
initial begin
#0 ap_CS_fsm = 1'd1;
#0 ap_enable_reg_pp0_iter1 = 1'b0;
#0 ap_enable_reg_pp0_iter2 = 1'b0;
#0 ap_enable_reg_pp0_iter3 = 1'b0;
#0 ap_enable_reg_pp0_iter4 = 1'b0;
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_pp0_stage0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter1 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter1 <= ap_start;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter2 <= 1'b0;
end else begin
if ((ap_block_pp0_stage0_flag00011011 == 1'b0)) begin
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter3 <= 1'b0;
end else begin
if ((ap_block_pp0_stage0_flag00011011 == 1'b0)) begin
ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter4 <= 1'b0;
end else begin
if ((ap_block_pp0_stage0_flag00011011 == 1'b0)) begin
ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
end
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
ap_reg_pp0_iter1_tmp_15_reg_246 <= tmp_15_reg_246;
ap_reg_pp0_iter1_tmp_22_reg_256 <= tmp_22_reg_256;
tmp_15_reg_246 <= empty_9;
tmp_22_reg_256 <= tmp_22_fu_174_p2;
end
end
always @ (posedge ap_clk) begin
if ((ap_block_pp0_stage0_flag00011001 == 1'b0)) begin
ap_reg_pp0_iter2_tmp_15_reg_246 <= ap_reg_pp0_iter1_tmp_15_reg_246;
empty_21_reg_302 <= empty_8_Dout_A;
empty_22_reg_307 <= empty_2_Dout_A;
empty_23_reg_312 <= empty_3_Dout_A;
empty_24_reg_317 <= empty_4_Dout_A;
empty_25_reg_322 <= empty_5_Dout_A;
empty_26_reg_327 <= empty_6_Dout_A;
empty_27_reg_332 <= empty_7_Dout_A;
sel_tmp10_reg_357 <= sel_tmp10_fu_218_p2;
sel_tmp3_reg_337 <= sel_tmp3_fu_196_p3;
sel_tmp4_reg_342 <= sel_tmp4_fu_203_p2;
sel_tmp6_reg_347 <= sel_tmp6_fu_208_p2;
sel_tmp8_reg_352 <= sel_tmp8_fu_213_p2;
end
end
always @ (*) begin
if ((((1'b0 == ap_start) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00000000 == 1'b0)) | ((ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter4)))) begin
ap_done = 1'b1;
end else begin
ap_done = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_start) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_idle_pp0))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_enable_reg_pp0_iter0) & (1'b0 == ap_enable_reg_pp0_iter1) & (1'b0 == ap_enable_reg_pp0_iter2) & (1'b0 == ap_enable_reg_pp0_iter3) & (1'b0 == ap_enable_reg_pp0_iter4))) begin
ap_idle_pp0 = 1'b1;
end else begin
ap_idle_pp0 = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_enable_reg_pp0_iter0) & (1'b0 == ap_enable_reg_pp0_iter1) & (1'b0 == ap_enable_reg_pp0_iter2) & (1'b0 == ap_enable_reg_pp0_iter3))) begin
ap_idle_pp0_0to3 = 1'b1;
end else begin
ap_idle_pp0_0to3 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_start) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_start) & (1'b1 == ap_idle_pp0_0to3))) begin
ap_reset_idle_pp0 = 1'b1;
end else begin
ap_reset_idle_pp0 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
empty_2_EN_A = 1'b1;
end else begin
empty_2_EN_A = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
empty_3_EN_A = 1'b1;
end else begin
empty_3_EN_A = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
empty_4_EN_A = 1'b1;
end else begin
empty_4_EN_A = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
empty_5_EN_A = 1'b1;
end else begin
empty_5_EN_A = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
empty_6_EN_A = 1'b1;
end else begin
empty_6_EN_A = 1'b0;
end
end
always @ (*) begin
if (((ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter2))) begin
empty_7_EN_A = 1'b1;
end else begin
empty_7_EN_A = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'b1 == ap_enable_reg_pp0_iter1))) begin
empty_8_EN_A = 1'b1;
end else begin
empty_8_EN_A = 1'b0;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_pp0_stage0 : begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd0];
assign ap_block_pp0_stage0_flag00000000 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage0_flag00011001 = ((1'b0 == ap_start) & (1'b1 == ap_start));
end
always @ (*) begin
ap_block_pp0_stage0_flag00011011 = ((1'b0 == ap_start) & (1'b1 == ap_start));
end
always @ (*) begin
ap_block_state1_pp0_stage0_iter0 = (1'b0 == ap_start);
end
assign ap_block_state2_pp0_stage0_iter1 = ~(1'b1 == 1'b1);
assign ap_block_state3_pp0_stage0_iter2 = ~(1'b1 == 1'b1);
assign ap_block_state4_pp0_stage0_iter3 = ~(1'b1 == 1'b1);
assign ap_block_state5_pp0_stage0_iter4 = ~(1'b1 == 1'b1);
assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1);
assign ap_enable_reg_pp0_iter0 = ap_start;
assign ap_return = ((sel_tmp10_reg_357[0:0] === 1'b1) ? empty_27_reg_332 : sel_tmp9_fu_234_p3);
assign empty_2_Addr_A = tmp_22_reg_256 << 32'd2;
assign empty_2_Din_A = 32'd0;
assign empty_2_WEN_A = 4'd0;
assign empty_3_Addr_A = tmp_22_reg_256 << 32'd2;
assign empty_3_Din_A = 32'd0;
assign empty_3_WEN_A = 4'd0;
assign empty_4_Addr_A = ap_reg_pp0_iter1_tmp_22_reg_256 << 32'd2;
assign empty_4_Din_A = 32'd0;
assign empty_4_WEN_A = 4'd0;
assign empty_5_Addr_A = ap_reg_pp0_iter1_tmp_22_reg_256 << 32'd2;
assign empty_5_Din_A = 32'd0;
assign empty_5_WEN_A = 4'd0;
assign empty_6_Addr_A = ap_reg_pp0_iter1_tmp_22_reg_256 << 32'd2;
assign empty_6_Din_A = 32'd0;
assign empty_6_WEN_A = 4'd0;
assign empty_7_Addr_A = ap_reg_pp0_iter1_tmp_22_reg_256 << 32'd2;
assign empty_7_Din_A = 32'd0;
assign empty_7_WEN_A = 4'd0;
assign empty_8_Addr_A = tmp_22_reg_256 << 32'd2;
assign empty_8_Din_A = 32'd0;
assign empty_8_WEN_A = 4'd0;
assign p_cast1_fu_148_p1 = empty;
assign p_cast_fu_152_p1 = empty_10;
assign p_shl_fu_164_p1 = tmp_fu_156_p3;
assign sel_tmp10_fu_218_p2 = ((ap_reg_pp0_iter2_tmp_15_reg_246 == 3'd5) ? 1'b1 : 1'b0);
assign sel_tmp1_fu_185_p3 = ((sel_tmp_fu_180_p2[0:0] === 1'b1) ? empty_22_reg_307 : empty_21_reg_302);
assign sel_tmp2_fu_191_p2 = ((ap_reg_pp0_iter2_tmp_15_reg_246 == 3'd1) ? 1'b1 : 1'b0);
assign sel_tmp3_fu_196_p3 = ((sel_tmp2_fu_191_p2[0:0] === 1'b1) ? empty_23_reg_312 : sel_tmp1_fu_185_p3);
assign sel_tmp4_fu_203_p2 = ((ap_reg_pp0_iter2_tmp_15_reg_246 == 3'd2) ? 1'b1 : 1'b0);
assign sel_tmp5_fu_223_p3 = ((sel_tmp4_reg_342[0:0] === 1'b1) ? empty_24_reg_317 : sel_tmp3_reg_337);
assign sel_tmp6_fu_208_p2 = ((ap_reg_pp0_iter2_tmp_15_reg_246 == 3'd3) ? 1'b1 : 1'b0);
assign sel_tmp7_fu_228_p3 = ((sel_tmp6_reg_347[0:0] === 1'b1) ? empty_25_reg_322 : sel_tmp5_fu_223_p3);
assign sel_tmp8_fu_213_p2 = ((ap_reg_pp0_iter2_tmp_15_reg_246 == 3'd4) ? 1'b1 : 1'b0);
assign sel_tmp9_fu_234_p3 = ((sel_tmp8_reg_352[0:0] === 1'b1) ? empty_26_reg_327 : sel_tmp7_fu_228_p3);
assign sel_tmp_fu_180_p2 = ((ap_reg_pp0_iter2_tmp_15_reg_246 == 3'd0) ? 1'b1 : 1'b0);
assign tmp_21_fu_168_p2 = (p_shl_fu_164_p1 - p_cast_fu_152_p1);
assign tmp_22_fu_174_p2 = (p_cast1_fu_148_p1 + tmp_21_fu_168_p2);
assign tmp_fu_156_p3 = {{empty_10}, {3'd0}};
endmodule //aesl_mux_load_7_3_x_s
|
/*!
btcminer -- BTCMiner for ZTEX USB-FPGA Modules: HDL code: double hash miner
Copyright (C) 2011 ZTEX GmbH
http://www.ztex.de
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License version 3 as
published by the Free Software Foundation.
This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, see http://www.gnu.org/licenses/.
!*/
module miner253 (clk, reset, midstate, data, golden_nonce, nonce2, hash2);
parameter NONCE_OFFS = 32'd0;
parameter NONCE_INCR = 32'd1;
parameter NONCE2_OFFS = 32'd0;
input clk, reset;
input [255:0] midstate;
input [95:0] data;
output reg [31:0] golden_nonce, hash2, nonce2;
reg [31:0] nonce;
wire [255:0] hash;
wire [31:0] hash2_w;
reg reset_b1, reset_b2, reset_b3, is_golden_nonce;
sha256_pipe130 p1 (
.clk(clk),
.state(midstate),
.state2(midstate),
.data({384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000, nonce, data}),
.hash(hash)
);
sha256_pipe123 p2 (
.clk(clk),
.data({256'h0000010000000000000000000000000000000000000000000000000080000000, hash}),
.hash(hash2_w)
);
always @ (posedge clk)
begin
if ( reset_b1 )
begin
nonce <= 32'd254 + NONCE_OFFS;
end else begin
nonce <= nonce + NONCE_INCR;
end
if ( reset_b2 )
begin
nonce2 <= NONCE_OFFS + NONCE2_OFFS;
end else begin
nonce2 <= nonce2 + NONCE_INCR;
end
if ( reset_b3 )
begin
golden_nonce1 <= 32'd0;
golden_nonce2 <= 32'd0;
end
else if ( is_golden_nonce )
begin
golden_nonce1 <= nonce2;
golden_nonce2 <= golden_nonce1;
end
reset_b1 <= reset;
reset_b2 <= reset;
reset_b3 <= reset;
hash2 <= hash2_w;
is_golden_nonce <= hash2_w == 32'ha41f32e7;
end
endmodule
|
module Control(Op_i,RegDst_o,Jump_o,Branch_o,MemRead_o,MemtoReg_o,ALUOp_o,MemWrite_o,ALUSrc_o,RegWrite_o);
parameter Op_lw=6'b100011,Op_sw=6'b101011,Op_beq=6'b000100,Op_ALU=6'b000000,Op_j=6'b000010,Op_addi=6'b001000;
input [5:0] Op_i;
output RegDst_o,Jump_o,Branch_o,MemRead_o,MemtoReg_o,MemWrite_o,ALUSrc_o,RegWrite_o;
output [1:0] ALUOp_o;
assign RegDst_o=(Op_i==0 || (Op_i&6'b111110)==6'b000010 ||
(Op_i&6'b111100)==6'b010000)?1:0;
assign Jump_o=(Op_i==Op_j)?1:0;
assign Branch_o=(Op_i==Op_beq)?1:0;
assign MemRead_o=(Op_i==Op_lw)?1:0;
assign MemtoReg_o=(Op_i==Op_lw)?1:0;
assign ALUOp_o=(Op_i==Op_beq)?2'b01:(Op_i==Op_lw || Op_i==Op_sw || Op_i==Op_addi)?2'b00:2'b10;
assign MemWrite_o=(Op_i==Op_sw)?1:0;
assign ALUSrc_o=(Op_i==Op_beq || Op_i==0 || (Op_i&6'b111110)==6'b000010 ||
(Op_i&6'b111100)==6'b010000)?0:1;
assign RegWrite_o=(Op_i==Op_lw || Op_i==Op_ALU || Op_i==6'b001000)?1:0;
endmodule
/*
and, or, add, sub, mul
100100
100101
100000
100010
000000 xxxxx xxxxx xxxxx xxxxx 011000
addi
001000 xxxxx xxxxx xxxxxxxxxxxxxxxx
lw
100011 xxxxx xxxxx xxxxxxxxxxxxxxxx
sw
101011 xxxxx xxxxx xxxxxxxxxxxxxxxx
beq
000100 xxxxx xxxxx xxxxxxxxxxxxxxxx
j
000010 xxxxxxxxxxxxxxxxxxxxxxxxxx
*/
|
`timescale 1ns / 1ps
/*
-- Module Name: Test Engine NiC Input Control Unit
-- Description: Unida de control para el bloque de entrada de la
interfaz de red. Este bloque se encarga de la captura de
nuevos paquetes provenientes de la red.
Ejerce control sobre registros de almacenamiento
individuales para cada flit de un paquete y lleva
a cabo las tares de control de flujo (creditos) con
respecto al router de la NoC.
-- Dependencies: -- system.vh
-- Parameters: -- BUFFER_DEPTH: Numero de flits que es capaz de
almacenar la cola de
almacenamiento de la NiC.
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas:
-- History:
-- 18 de Junio 2015: Creacion
*/
`include "system.vh"
module test_engine_nic_input_control_unit
(
input wire clk,
input wire reset,
// -- inputs ------------------------------------------------- >>>>>
input wire header_field_din,
input wire busy_engine_din,
input wire zero_credits_din,
// -- outputs ------------------------------------------------ >>>>>
output wire transfer2pe_strobe_dout,
output wire write_strobe_dout,
output wire [`DATA_FLITS:0] register_enable_dout
);
// -- Parametros locales ----------------------------------------- >>>>>
localparam IDLE = 2'b00;
localparam CAPTURE = 2'b01;
localparam WAIT = 2'b10;
/*
-- Descripcion: Maquina de estado finito para el control de recepcion de
paquetes para el PE del nodo.
La FSM espera el ingreso de un nuevo paquete a traves
del canal de entrada. Durante los siguientes 'n' ciclos
de reloj se registra cada flit perteneciente al paquete,
dando la primera posicion del medio de almacenamiento
al flit de cabecera.
Al finalizar la captura de flits de un paquete se
evalua la disponibilidad del elemento de procesamiento
(banderas:: busy_engine_din y zero_credits_din), en
caso de la presencia de cualquiera de las dos banderas
la FSM salta al estado WAIT para esperar disponibilidad
del elemento de procesamiento.
La señal capture_strobe indica la captura de un paquete
completo. esta señal se convierte en la señal de inicio
para el PE.
El control de flujo utiliza el mecanismo de creditos.
*/
// -- FSM ---------------------------------------------------- >>>>>
// -- Elementos de memoria ------------------------------- >>>>>
reg [1:0] state_reg;
reg [1:0] state_next;
always @(posedge clk)
if (reset)
state_reg <= IDLE;
else
state_reg <= state_next;
// -- Logica del estado siguiente ------------------------ >>>>>
always @(*)
begin
state_next = state_reg;
case (state_reg)
IDLE:
if (header_field_din)
state_next = CAPTURE;
CAPTURE:
if ((register_enable_reg == {`DATA_FLITS+1{1'b0}}) & (~busy_engine_din) & (~zero_credits_din))
state_next = IDLE;
else if ((register_enable_reg == {`DATA_FLITS+1{1'b0}}) & (busy_engine_din | zero_credits_din))
state_next = WAIT;
WAIT:
if (~busy_engine_din & ~zero_credits_din)
state_next = IDLE;
endcase // state_reg
end
// -- Logica de salidas -------------------------------------- >>>>>
assign transfer2pe_strobe_dout = ((state_reg == CAPTURE | state_reg == WAIT) & (state_next == IDLE)) ? 1'b1 : 1'b0;
assign write_strobe_dout = (state_next == CAPTURE) ? 1'b1 : 1'b0;
/*
-- Descripcion: Secuenciador para habilitacion de escritura en banco
de registro para flits. Los datos de trabajo para el
elemento de procesamiento se almacenan en registros
individuales, este contador habilita la escritura en
cada uno de ellos.
Este registro esta codificado en formato 'one hot',
y cada uno de sus bits habilita la captura de un
flit en un registro diferente.
Los elementos de memoria estan descritos en el
modulo test_engine_nic_input_block.v
*/
// -- Elementos de memoria ----------------------------------- >>>>>
reg [`DATA_FLITS:0] register_enable_reg;
wire [`DATA_FLITS:0] register_enable_next;
always @(posedge clk)
if (reset)
register_enable_reg <= {{`DATA_FLITS{1'b0}}, 1'b1};
else
register_enable_reg <= register_enable_next;
// -- Logica del estado siguiente ---------------------------- >>>>>
assign register_enable_next = (state_next == CAPTURE) ? register_enable_reg << 1 :
(state_next == IDLE) ? {{`DATA_FLITS{1'b0}}, 1'b1} :
register_enable_reg;
// -- Logica de salidas -------------------------------------- >>>>>
assign register_enable_dout = register_enable_reg;
// -- Codigo no sintetizable ------------------------------------- >>>>>
reg [7*8:0] state_reg_dbg;
always @(*)
case (state_reg)
IDLE: state_reg_dbg = " IDLE ";
WAIT: state_reg_dbg = " WAIT ";
CAPTURE: state_reg_dbg = "CAPTURE";
default : state_reg_dbg = " ERROR ";
endcase
endmodule
/* Plantilla de instancia ---------------------------------------- >>>>>
des_nic_input_control_unit des_nic_input_control_unit
(
.clk (clk),
.reset (reset),
// -- inputs ------------------------------------------------- >>>>>
.header_field_din (header_field),
.busy_engine_din (busy_engine),
.zero_credits_din (zero_credits),
// -- outputs ------------------------------------------------ >>>>>
.transfer2pe_strobe_dout(transfer2pe_strobe),
.write_strobe_dout (write_strobe),
.register_enable_dout (register_enable)
);
*/ |
`define bsg_buf_macro(bits) \
if (harden_p && (width_p==bits) && vertical_p) \
begin: macro \
bsg_rp_tsmc_250_BUFX8_b``bits buf_gate (.i0(i),.o); \
end \
else \
if (harden_p && (width_p==bits) && ~vertical_p) \
begin: macro \
bsg_rp_tsmc_250_BUFX8_horiz_b``bits buf_gate (.i0(i),.o);\
end
module bsg_buf #(parameter `BSG_INV_PARAM(width_p)
, parameter harden_p=1
, parameter vertical_p=1
)
(input [width_p-1:0] i
, output [width_p-1:0] o
);
`bsg_buf_macro(89) else
`bsg_buf_macro(88) else
`bsg_buf_macro(87) else
`bsg_buf_macro(86) else
`bsg_buf_macro(85) else
`bsg_buf_macro(84) else
`bsg_buf_macro(83) else
`bsg_buf_macro(82) else
`bsg_buf_macro(81) else
`bsg_buf_macro(80) else
`bsg_buf_macro(79) else
`bsg_buf_macro(78) else
`bsg_buf_macro(77) else
`bsg_buf_macro(76) else
`bsg_buf_macro(75) else
`bsg_buf_macro(74) else
`bsg_buf_macro(73) else
`bsg_buf_macro(72) else
`bsg_buf_macro(71) else
`bsg_buf_macro(70) else
`bsg_buf_macro(69) else
`bsg_buf_macro(68) else
`bsg_buf_macro(67) else
`bsg_buf_macro(66) else
`bsg_buf_macro(65) else
`bsg_buf_macro(64) else
`bsg_buf_macro(63) else
`bsg_buf_macro(62) else
`bsg_buf_macro(61) else
`bsg_buf_macro(60) else
`bsg_buf_macro(59) else
`bsg_buf_macro(58) else
`bsg_buf_macro(57) else
`bsg_buf_macro(56) else
`bsg_buf_macro(55) else
`bsg_buf_macro(54) else
`bsg_buf_macro(53) else
`bsg_buf_macro(52) else
`bsg_buf_macro(51) else
`bsg_buf_macro(50) else
`bsg_buf_macro(49) else
`bsg_buf_macro(48) else
`bsg_buf_macro(47) else
`bsg_buf_macro(46) else
`bsg_buf_macro(45) else
`bsg_buf_macro(44) else
`bsg_buf_macro(43) else
`bsg_buf_macro(42) else
`bsg_buf_macro(41) else
`bsg_buf_macro(40) else
`bsg_buf_macro(39) else
`bsg_buf_macro(38) else
`bsg_buf_macro(37) else
`bsg_buf_macro(36) else
`bsg_buf_macro(35) else
`bsg_buf_macro(34) else
`bsg_buf_macro(33) else
`bsg_buf_macro(32) else
`bsg_buf_macro(31) else
`bsg_buf_macro(30) else
`bsg_buf_macro(29) else
`bsg_buf_macro(28) else
`bsg_buf_macro(27) else
`bsg_buf_macro(26) else
`bsg_buf_macro(25) else
`bsg_buf_macro(24) else
`bsg_buf_macro(23) else
`bsg_buf_macro(22) else
`bsg_buf_macro(21) else
`bsg_buf_macro(20) else
`bsg_buf_macro(19) else
`bsg_buf_macro(18) else
`bsg_buf_macro(17) else
`bsg_buf_macro(16) else
`bsg_buf_macro(15) else
`bsg_buf_macro(14) else
`bsg_buf_macro(13) else
`bsg_buf_macro(12) else
`bsg_buf_macro(11) else
`bsg_buf_macro(10) else
`bsg_buf_macro(9) else
`bsg_buf_macro(8) else
`bsg_buf_macro(7) else
`bsg_buf_macro(6) else
`bsg_buf_macro(5) else
`bsg_buf_macro(4) else
`bsg_buf_macro(3) else
`bsg_buf_macro(2) else
`bsg_buf_macro(1) else
begin :notmacro
initial assert(harden_p==0) else $error("## %m wanted to harden but no macro");
assign o = i;
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_buf)
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Octoate, Nilquader
// ACID Reverse engineering by nocash
//
// Create Date : 00:45:53 09/03/2010
// Design Name : amsacid
// Module Name : amsacid
// Project Name :
// Target Devices: Xilinx XC9572
// Tool versions :
// Description : Reverse engineered Amstrad 40908 "ACID" Chip
//
// Revision:
// Revision 0.05
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module amsacid(PinCLK, PinA, PinOE, PinCCLR, PinSIN);
input PinCLK;
input [7:0]PinA;
input PinOE;
input PinCCLR;
output [7:0]PinSIN;
wire PinCLK;
reg [16:0]ShiftReg = 17'h1FFFF;
wire [16:0]CmpVal;
wire [16:0]XorVal;
assign CmpVal = 17'h13596 ^ (PinA[0] ? 17'h0000c : 0)
^ (PinA[1] ? 17'h06000 : 0)
^ (PinA[2] ? 17'h000c0 : 0)
^ (PinA[3] ? 17'h00030 : 0)
^ (PinA[4] ? 17'h18000 : 0)
^ (PinA[5] ? 17'h00003 : 0)
^ (PinA[6] ? 17'h00600 : 0)
^ (PinA[7] ? 17'h01800 : 0);
assign XorVal = 17'h0C820 ^ (PinA[0] ? 17'h00004 : 0)
^ (PinA[1] ? 17'h06000 : 0)
^ (PinA[2] ? 17'h00080 : 0)
^ (PinA[3] ? 17'h00020 : 0)
^ (PinA[4] ? 17'h08000 : 0)
^ (PinA[5] ? 17'h00000 : 0)
^ (PinA[6] ? 17'h00000 : 0)
^ (PinA[7] ? 17'h00800 : 0);
always@(negedge PinCLK)
begin
if (PinCCLR) // not in reset state
begin
if (!PinOE && ((ShiftReg | 17'h00100) == CmpVal))
begin
ShiftReg <= (ShiftReg ^ XorVal) >> 1;
ShiftReg[16] <= ShiftReg[0] ^ ShiftReg[9] ^ ShiftReg[12] ^ ShiftReg[16] ^ XorVal[0]; // hier xorval mit berüchsichtigen
end
else
begin
ShiftReg <= ShiftReg >> 1;
ShiftReg[16] <= ShiftReg[0] ^ ShiftReg[9] ^ ShiftReg[12] ^ ShiftReg[16];
end
end
else
begin
ShiftReg <= 17'h1FFFF;
end
end
//assign PinSIN = ShiftReg[7:0] ^ 8'hff;
assign PinSIN = ShiftReg[7:0];
//assign PinSIN[0] = PinCLK;
endmodule |
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Fri Sep 22 23:00:32 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_gpio_0_1/zqynq_lab_1_design_axi_gpio_0_1_stub.v
// Design : zqynq_lab_1_design_axi_gpio_0_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_gpio,Vivado 2017.2" *)
module zqynq_lab_1_design_axi_gpio_0_1(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_o)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_o[7:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
output [7:0]gpio_io_o;
endmodule
|
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