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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFSTP_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__SDFSTP_PP_SYMBOL_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__sdfstp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFSTP_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLXBP_PP_SYMBOL_V
`define SKY130_FD_SC_MS__DLXBP_PP_SYMBOL_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{clocks|Clocking}}
input GATE,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLXBP_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O32AI_PP_SYMBOL_V
`define SKY130_FD_SC_LS__O32AI_PP_SYMBOL_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o32ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O32AI_PP_SYMBOL_V
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Peripheral Controller
// File : hbi_per.v
// Author : Frank Bruno
// Created : 30-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// THis is the top level module of the peripheral devices controler.
// Entire controler is in host clock domain.
// Peripheral devices include:
// EPROM and/ or Flash PROM external RAMDAC and internal RAMDAC
// Soft switch (external write only register). Read data from the softswitch
// comes actually from an internal shadow register ( in HBI)
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
/****************************************************************************
* input per_soft_0 ; not used any more. Controls Default to soft switch write
* if request is not for DAC nor PROM
* output per_push; not used any more. Read data (registered in PER_ )
* has to be valid at the time of per_done or before,
* and will stay until next read cycle .
*****************************************************************************/
module hbi_per
(
input reset,
input hclock,
input ser_parn, // Serial Eprom Select
input per_req, // PERIPHERAL request
input per_read, // PER. read(h)/write(l) indicator
input per_dac, // DAC request indicator (active low!)
input per_prom, // PROM request indicator (active low!)
input per_lbe_f, // high if ALL byte enable are high
input [15:0] per_org, /* PER origin changed from [19:0] to [15:0]
* just for 64k */
input [7:0] per_data_wr, // PER write data from the host
input [2:0] dac_wait, /* DAC wait states
* dac_wait[2:1] make RD/WR low as below
* 00 => 3 clocks + 0 clocks
* (use it for IBM @ 33)
* 01 -> 3 clocks + 2 clocks
* (use it for IBM @ 66)
* 10 => 3 clocks + 4 clocks
* 11 => 3 clocks + 8 clocks
* dac_wait[0] makes minimum RD/WR high as
* below
* 0 => 4clocks (use it for TI like dacs)
* 1 => 16 (use it for IBM like dacs)
* to guarantee 6 pixel clocks @ 25 MHz with
* host running @ 66 MHz */
input [3:0] prom_wait, // EPROM wait states
input bios_rdat, // Serial Eprom Read Data.
output reg per_ready, /* PERIPHERAL interface READY
* there is no double buffering for requests,
* so per_ready goes low on the edge of clock
* when request is registered and stays low
* until a cycle (regardless the type) is
* completely finished */
output reg per_done, /* PER.read cycle finished,
* and valid data is present on per_data_rd
* Only to avoid other changes in HBI
* generate per_done after writes also ,
* but then issue per_done on next clock after
* request */
output reg [31:0] per_data_rd,/* registered read data from peripheral device
* to HBI */
input idac_en, /* from configuration ? register
* enables access to internal RAMDAC */
// signals to from internal RAMDAC
input [7:0] idac_data_in,// data from innternal RAMDAC
output idac_wr, // write strobe to internal RAMDAC
output idac_rd, // read strobe to internal RAMDAC
/// signals from/to peripheral devices I/O
output [15:0] aux_addr, // changed from 9:0 to 7:0 (max eprom size 64k)
// may not be enough for multiple BIOS images
input [7:0] aux_data_in, // input data from per. devices data bus
output reg [7:0]aux_data_out,// output data to per. devices data bus
output [1:0] aux_dac_wr, // DAC write strobe (act.low)
output [1:0] aux_dac_rd, // DAC read strobe (act.low)
output reg aux_prom_cs, /* EPROM chip select , (act.low)
* also used to latch upper addresses in an
* external latch 1(transp.) 0 latches */
output reg aux_prom_oe, // EPROM output enable select (act.low)
output reg aux_prom_we, // write strobe for flash prom (act.low)
output reg aux_ld_sft, // Soft switch load pulse (act.high)
output reg aux_buff_en, // output enable to data I/Os (act.low)
input [3:0] sepm_cmd, // Serial Eprom Command
input [18:0] sepm_addr, // Serial Eprom address for page clearing
input sepm_busy, // Kick off a command
output reg clr_sepm_busy,// Done w/ a serial eprom command
output bios_clk,
output bios_hld,
output bios_csn,
output reg bios_wdat
);
// For now we use the following connections for the serial eprom:
// pd_in[1] = ser_q
reg [15:0] per_addr;
reg [3:0] lcount;
reg [2:0] hcount;
reg [1:0] pcount;
reg read_cyc, incraddr, pdecr, ldecr, hdecr, reload_lcount,
reload_hcount, aux_prom_oe_i,
aux_prom_we_i, aux_buff_en_i, aux_ld_sft_i,
per_done_i, per_ready_i, dac_wr_i, dac_rd_i, aux_prom_cs_i,
per_clkd, prom_rd_cyc,
dac_wr, dac_rd, idac_sel;
reg [4:0] cstate,nstate;
reg [31:0] ser_cmd[8:0];
reg clear_serial_counter;
reg [5:0] serial_counter; // Counter used for shifting out addr
reg ser_inc; // Increment the serial counter
reg ser_s_i, ser_s_ii;
reg ser_addr_en, ser_addr_en_i;
reg load_command; // Load the serial command
reg ser_capt; // Capture incoming serial data
reg ser_h_i, ser_h_ii;
reg rdsr;
reg delay_dat;
reg clk_en, clk_en_i; // enable the clock out of the chip
reg [7:0] ser_data;
reg ser_c; // Serial Eprom Clock
reg ser_h; // Serial Eprom Hold signal
reg ser_s; // Serial Eprom Select Signal
wire l_wait, last;
wire [31:0] command;
parameter IDLE = 5'b00_000,
SOFT_ONE = 5'b00_001,
SOFT_TWO = 5'b00_010,
SOFT_THREE = 5'b00_011,
DAC_ZERO = 5'b00_100,
DAC_ONE = 5'b00_101,
DAC_TWO = 5'b00_110,
DAC_THREE = 5'b00_111,
PROM_ONE = 5'b01_000,
PROM_TWO = 5'b01_001,
PROM_THREE = 5'b01_010,
PROM_FOUR = 5'b01_011,
PROM_FIVE = 5'b01_100,
PROM_SIX = 5'b01_101,
PROM_SEVEN = 5'b01_110,
PERIPH_END = 5'b01_111,
SPROM1 = 5'b10_000,
SPROM_ADDR = 5'b10_001,
SPROM_READ = 5'b10_010,
SPROM_WIDLE = 5'b10_011,
SPROM_WIDLE1 = 5'b11_001,
SPROM_WRITE = 5'b10_100,
SPROM_RDSR_IDLE= 5'b10_101,
SPROM_RDSR_IDLE1= 5'b10_110,
SPROM_RDSR = 5'b10_111,
SPROM_WIP = 5'b11_000,
SPROM_S = 5'b11_010,
SEPM_READ = 4'b0000, // Read command (ignore)
SEPM_PP = 4'b0001, // Page Program Command
SEPM_SE = 4'b0010, // Sector Erase
SEPM_BE = 4'b0011, // Bulk Erase
SEPM_WREN = 4'b0100, // Write Enable
SEPM_WRDI = 4'b0101, // Write Disable
SEPM_RDSR = 4'b1000, // Internal Read status register
SEPM_EOP = 4'b1001; // External end PP sequence
// The serial eprom needs commands to be executed, so we will build them
// up here
always @* begin
// Read command: Read data from the PROM
ser_cmd[0] = {8'b00000011, 8'b0, per_addr[15:0]};
// PP commnds: Program the ROM Pages
ser_cmd[1] = {8'b00000010, 5'b0, sepm_addr};
// SE Command: Sector Erase
ser_cmd[2] = {8'b11011000, 5'b0, sepm_addr};
// BE Command: Bulk Erase
ser_cmd[3] = {8'b11000111, 24'b0};
// WREN command: Enable writing to the PROM
ser_cmd[4] = {8'b00000110, 24'b0}; // Only the upper 8 bits are used
// WRDI command: Disable writing to the prom
ser_cmd[5] = {8'b00000100, 24'b0}; // only the upper 8 bits are used
// Dummy's
ser_cmd[6] = 32'b0;
ser_cmd[7] = 32'b0;
// RDSR command: Read Status REgister
ser_cmd[8] = {8'b00000101, 24'b0}; // only the upper 8 bits are used
end // always @ *
/***************************************************************************
* register data / address coming with request
* request is reloading address immediately, incraddr (from PER_SM) may
* increment the address if needed for eprom's four reads
* Store also read_cycle for convienence in state machine
* and internal/external dac select at the time of any request
***************************************************************************/
always @* delay_dat = (ser_addr_en) ? command[~serial_counter[5:1]] :
ser_data[~serial_counter[3:1]];
always @(posedge hclock) if (ser_parn) bios_wdat <= delay_dat;
always @(posedge hclock)
begin
if (per_req) begin
aux_data_out <= per_data_wr;
ser_data <= per_data_wr;
per_addr <= per_org;
read_cyc <= per_read;
idac_sel <= idac_en;
end
else if (incraddr) per_addr <= per_addr + 1'b1;
end
/***************************************************************************
* mux per_addr into 8 address pins, for eprom addressing aux_prom_cs
* will latch first (high) byte of address in external latch
***************************************************************************/
assign aux_addr = per_addr[15:0];
assign bios_clk = (ser_c & clk_en);
assign bios_hld = ser_h;
assign bios_csn = ser_s;
// assign aux_addr = {serial_counter[0], ser_h, ser_s, per_addr[15:0]};
/**************************************************************************
* enable strobes to selected dac only internal/external
* disabled strobes remain high
***************************************************************************/
assign aux_dac_wr = {2{dac_wr | idac_sel}}; //idac_sel low enables strobes
assign aux_dac_rd = {2{dac_rd | idac_sel}}; // to external dac
assign idac_wr = dac_wr | ~idac_sel ;// idac_sel high enables strobes
assign idac_rd = dac_rd | ~idac_sel ; // internal dac
/***************************************************************************
* load wait state cunter lcount (for DAC and EPROM) with request or reload again
* between four reads prom cycles. Return "count=zero" to PER_SM.
* per_dac is active low!
*
* load wait state conter hcount for keeping minimum RD/WR high (for DAC only)
* reload the counter to extend the begining and the end of a sequence
* for total 6+6+4
*
* load "prom_read_cycle" counter. Always four read cycles are performed
* and the data is formated into one dword to be sent to HBI.
Return "count=zero" to PER_SM.
***************************************************************************/
always @(posedge hclock or negedge reset)
if(!reset) begin
lcount <= 4'b0;
hcount <= 3'b0;
pcount <= 2'b0; //who cares
end else begin
casex ({per_req, reload_lcount, ldecr, per_dac})
4'b000x: lcount <= lcount;
4'b001x: lcount <= lcount - 1'b1;
4'b01xx: lcount <= prom_wait;
4'b1xx0: lcount <= {1'b0, dac_wait[2:1] , 1'b0};
4'b1xx1: lcount <= prom_wait;
endcase
casex ({per_req, reload_hcount, hdecr, dac_wait[0]})
4'b000x: hcount <= hcount;
4'b001x: hcount <= hcount - 1'b1;
4'b01xx: hcount <= 3'b101; //load with five
4'b1xx0: hcount <= 3'b000; // load with zero on request
4'b1xx1: hcount <= 3'b101; //load with five on request
endcase
casex ({per_req , pdecr})
2'b00: pcount <= pcount;
2'b01: pcount <= pcount - 1'b1;
2'b1x: pcount <= 2'b11;
endcase
end
assign l_wait = |lcount ; // (wait in state machine if l_wait high)
assign last = (pcount==2'b0);
/*************************************************************************
* select and register data comming from peripheral devices data bus
* the registered data will be used by HBI when per_done impulse
* (after read cycle) is issued, or later. Nothing changes this data until
* next read cycle will run .
**************************************************************************/
always @(posedge hclock) begin
casex({(ser_capt & ~ser_c), per_clkd, prom_rd_cyc, per_addr[1:0]})
5'b010xx: begin // DAC cycle, replicate data on all bytes
if(idac_sel) begin//internal dac selected
per_data_rd[7:0] <= idac_data_in;
per_data_rd[15:8] <= idac_data_in;
per_data_rd[23:16] <= idac_data_in;
per_data_rd[31:24] <= idac_data_in;
end else begin //external ram dac selected
per_data_rd[7:0] <= aux_data_in;
per_data_rd[15:8] <= aux_data_in;
per_data_rd[23:16] <= aux_data_in;
per_data_rd[31:24] <= aux_data_in;
end
end
5'b01100: begin // EPROM cycle, first byte strobed
per_data_rd[7:0] <= aux_data_in;
end
5'b01101: begin // EPROM cycle, second byte strobed
per_data_rd[15:8] <= aux_data_in;
end
5'b01110: begin // EPROM cycle, third byte strobed
per_data_rd[23:16] <= aux_data_in;
end
5'b01111: begin // EPROM cycle, fourth byte strobed
per_data_rd[31:24] <= aux_data_in;
end
// Serial Eprom Capture
5'b1xxxx: begin
case (serial_counter[5:4])
2'b00: per_data_rd[7:0] <= {per_data_rd[6:0], bios_rdat};
2'b01: per_data_rd[15:8] <= {per_data_rd[14:8], bios_rdat};
2'b10: per_data_rd[23:16] <= {per_data_rd[22:16], bios_rdat};
2'b11: per_data_rd[31:24] <= {per_data_rd[30:24], bios_rdat};
endcase
end
default: per_data_rd <= per_data_rd;
endcase
end
/***************************************************************************
* PERIPHERAL STATE MACHINE *
***************************************************************************/
//signals to I/Os or host to be driven from flip-flops
always @(posedge hclock) begin
aux_prom_oe <= aux_prom_oe_i;
aux_prom_we <= aux_prom_we_i;
aux_buff_en <= aux_buff_en_i;
aux_ld_sft <= aux_ld_sft_i;
dac_wr <= dac_wr_i;
dac_rd <= dac_rd_i;
aux_prom_cs <= aux_prom_cs_i;
per_done <= per_done_i;
per_ready <= per_ready_i;
// Serial stuff--- figure out pins!
ser_c <= serial_counter[0];
ser_s_ii <= ser_s_i;
ser_s <= ser_s_ii;
clk_en <= clk_en_i;
ser_addr_en <= ser_addr_en_i;
end
// always @(negedge hclock) begin
always @(posedge hclock) begin
ser_h_ii <= ser_h_i;
ser_h <= ser_h_ii;
end
assign command = (rdsr) ? ser_cmd[SEPM_RDSR] : ser_cmd[sepm_cmd];
// Serial Counter
always @(posedge hclock or negedge reset)
if (!reset) serial_counter <= 6'b0;
else if (clear_serial_counter) serial_counter <= 6'b0;
else serial_counter <= serial_counter + ser_inc;
always @(posedge hclock or negedge reset)
if (!reset) cstate <= IDLE ;
else cstate <= nstate;
// PERIPHERAL CYCLES STATE MACHINE
always @* begin
aux_prom_oe_i = 1'b1;
aux_prom_we_i = 1'b1;
aux_buff_en_i = 1'b1;
aux_ld_sft_i = 1'b0;
dac_wr_i = 1'b1;
dac_rd_i = 1'b1;
aux_prom_cs_i = 1'b1;
per_clkd = 1'b0;
prom_rd_cyc = 1'b0; // set if data from eprom gets registered
incraddr = 1'b0; // The default is not to increment the address
pdecr = 1'b0; //
ldecr = 1'b0; //
hdecr = 1'b0; //
reload_lcount = 1'b0; // The default is to not re-load lcount
reload_hcount = 1'b0; // The default is to not re-load hcount
per_ready_i = 1'b0;
per_done_i = 1'b0;
clear_serial_counter = 1'b0; // Do not clear serial counter
ser_s_i = 1'b1; // Default to not selecting serial prom
ser_addr_en_i = 1'b0; // default to data mode
ser_capt = 1'b0;
ser_inc = 1'b0;
clr_sepm_busy = 1'b0;
ser_h_i = 1'b1; // Serial hold signal internal
rdsr = 1'b0;
clk_en_i = 1'b0;
nstate = cstate;
case (cstate) //synopsys parallel_case
IDLE: begin
per_ready_i=(per_req)? 1'b0: 1'b1; //send "not ready" on next cycle
per_done_i =(per_req && (!per_read || (per_read && per_dac && per_prom)
|| per_lbe_f));
// send done on next cycle for all writes cycles and
// in case of attempting reads from softsw
// ( error conditions),
// and any time request with per_lbe_f==1 occures
if (per_req & ~per_lbe_f) // All BEn's set, no data xfer
casex ({per_dac, per_prom, per_read}) //per_dac,per_eprom act.low
3'b0xx: nstate = DAC_ZERO ; //gives priority to DAC cycles
3'b10x: nstate = (ser_parn) ? SPROM1 : PROM_ONE ;
3'b110: nstate = SOFT_ONE ; // writes to soft switch
3'b111: nstate = IDLE ; /* ignore this type of request
* no reads from softswitch
* should occure */
endcase
else if (sepm_busy) nstate = SPROM1;
else nstate= IDLE ;
end
////////// SOFT SWITCH WRITE CYCLE
SOFT_ONE: begin
aux_buff_en_i = 1'b0;
nstate = SOFT_TWO ;
end
SOFT_TWO: begin
aux_buff_en_i = 1'b0;
nstate = SOFT_THREE ;
end
SOFT_THREE: begin
aux_ld_sft_i = 1'b1;
aux_buff_en_i = 1'b0;
nstate = PERIPH_END;
end
////////// DAC READ/WRITE CYCLE
DAC_ZERO : nstate = DAC_ONE;
// this makes minimum 2 clocks
// of address setup to falling edge of
// DAC's RW or RD signal
// hcount here can only be five or zero
// loaded with request
DAC_ONE :
begin
if (read_cyc) dac_rd_i = 1'b1;
else
begin
dac_wr_i = 1'b1;
aux_buff_en_i = 1'b0;
end
nstate = DAC_TWO ;
end
DAC_TWO :
begin
if (read_cyc)
dac_rd_i = 1'b0;
else
begin
dac_wr_i = 1'b0;
aux_buff_en_i = 1'b0;
end
nstate = DAC_THREE ;
end
DAC_THREE :
begin
if (read_cyc)
begin
per_clkd = 1'b1; // data gets registered,
per_done_i= 1'b1; // valid registered data and
// and per_done will occure after
// the same (next) rising edge of clock
end
else aux_buff_en_i = 1'b0; // dac_wr_i goes high acutal WR cycle
// this provides 1 clock of hold time for
// write data
nstate = PERIPH_END; //hcount can only be
end
//////////////////////////////////////////////////////////////////////
////////// EPROM CYCLES
PROM_ONE: begin
aux_prom_cs_i = 1'b0; // this gives one clock address setup
// to falling edge of Latch enable of F373
if (read_cyc) nstate = PROM_TWO ; // EPROM read
else nstate = PROM_FIVE ; // EPROM write
end
PROM_TWO: begin // sel_addr_high_i switched to 0
aux_prom_cs_i = 1'b0; // this gives one clock address hold time
aux_prom_oe_i = 1'b0; // to falling edge of Latch enable of F373
nstate = PROM_THREE ; // (uses prom_cs)
end
PROM_THREE: begin
aux_prom_cs_i = 1'b0;
aux_prom_oe_i = 1'b0;
ldecr = 1'b1;
// Decrement wait state count, if wait states count is
// zero it will overflow , but then who cares
// the state will jump to PROM_FOUR
// Mimimum time to rising edge of clock strobing
// data is 3 clocks from CS low
// and 2 (two!) clocks from OE low and complete address
// minus all delays from clock to
// address/CS/OE on PROM pins.
if (!l_wait) nstate = PROM_FOUR ;
else nstate = PROM_THREE ;
end
PROM_FOUR: begin
aux_prom_cs_i = (last)? 1'b1: 1'b0;
aux_prom_oe_i = (last)? 1'b1: 1'b0;
// don't toggle cs and oe between four reads
// but speed up turning off after last read.
// to have more turn-around time for other
// accesses (if ever used such mixed acces )
// in normal case eprom will be read in to
// shadow memory.
// hold time for last byte is O.K ( as below)
reload_lcount = 1'b1;
incraddr = 1'b1;
// hold time for data coming in to rising
// edge of clock is guaranteed by address output
// buffers delay + input_data_path
// + prom_data_delay_from address
// so it is safe to strobe on the clock in this
// state
pdecr = 1'b1;
// it will overflow if all 4 pages done, but
// who cares, the state will jump to PERIPH_END
per_clkd = 1'b1;
prom_rd_cyc = 1'b1; // prom read cycle indicator
per_done_i = (last)? 1'b1: 1'b0; // send done (valid data )to host
if (last) nstate = PERIPH_END ; // 4 pages done
else nstate = PROM_THREE ; // do next page
end
PROM_FIVE: begin //double check flash eprom spec !!
aux_prom_cs_i = 1'b0;
//sel_addr_high_i switched to low
//to make 1 clock of hold time on ext.latch
// (uses prom_cs)
aux_buff_en_i = 1'b0;
nstate = PROM_SIX ;
end
PROM_SIX: begin
aux_prom_cs_i = 1'b0;
aux_buff_en_i = 1'b0;
aux_prom_we_i = 1'b0;
// prom_WE low time is 1+prom_wait
// address (complete and valid) to falling
// edge WE is 1 clock
// address (complete and valid) to rising
// edge WE is 2 clocks + prom wait
ldecr = 1'b1; // Decrement wait state count
if (!l_wait) nstate = PROM_SEVEN ;
else nstate = PROM_SIX ;
end
PROM_SEVEN: begin
aux_prom_cs_i = 1'b0; //
aux_buff_en_i = 1'b0;
// this gives 1 clock of hold time for data
// from rising edge of eprom WE.
nstate = PERIPH_END ;
end
// Serial EPROM Cycles
SPROM1: begin
clk_en_i = 1'b1;
aux_buff_en_i = 1'b0;
if (read_cyc || sepm_busy) begin
clear_serial_counter = 1'b1;
ser_s_i = 1'b0; // drop the serial select low
ser_inc = 1'b1; // Increment the counter
ser_addr_en_i = 1'b1; // select the command output
// if we are writing an unsupported command, or if we are writing
// a read command, then we're done. Note that the EOP command is
// unsupported unless in a write loop.
if ((sepm_cmd > 4'b0101) ||
(sepm_busy && sepm_cmd == SEPM_READ)) begin
nstate = PERIPH_END; // Unsupported external command
clr_sepm_busy = 1'b1; // Clear the busy flag
per_done_i = 1'b1; // signal cycle done
end else
nstate = SPROM_ADDR;
end
end // case: SPROM1
SPROM_ADDR: begin
clk_en_i = 1'b1;
aux_buff_en_i = 1'b0;
ser_s_i = 1'b0; // keep the serial select low
ser_inc = 1'b1; // Keep incrementing the counter
ser_addr_en_i = 1'b1; // select the command output
// Determine if we are done w/ the address
casex ({sepm_cmd, serial_counter[5:0]})
{SEPM_WREN, 6'bxx1111}, {SEPM_WRDI, 6'bxx1111}: begin
// To set or reset the write latch takes only the instruction
nstate = PERIPH_END;
clr_sepm_busy = 1'b1; // Clear the busy flag
per_done_i = 1'b1; // signal cycle done
clear_serial_counter = 1'b1;
end
{SEPM_READ, 6'b111111}: begin
nstate = SPROM_READ;
ser_addr_en_i = 1'b0; // select the command output
end
{SEPM_PP, 6'b111111}: begin
// Here we are setting up for a programming session.
// Send out the programming command and then we will go to
// the write idle state
nstate = SPROM_WIDLE;
// ser_h_i = 1'b0;
// clr_sepm_busy = 1'b1; // Clear the busy flag
per_done_i = 1'b1; // signal cycle done
clear_serial_counter = 1'b1;
per_ready_i = 1'b1; // be ready in next idle state
end
{SEPM_SE, 6'b111111}: begin
// Send the command to clear the sector. Then we will go to the
// wait for WIP to go away state. However, release comtrol to the
// host so we can commence polling
clear_serial_counter = 1'b1;
nstate = SPROM_RDSR_IDLE;
per_done_i = 1'b1; // signal cycle done
end
{SEPM_BE, 6'b001111}: begin
clear_serial_counter = 1'b1;
nstate = SPROM_RDSR_IDLE;
per_done_i = 1'b1; // signal cycle done
end
default: nstate = SPROM_ADDR;
endcase // casex({sepm_cmd, serial_counter[5:1]})
end
SPROM_READ: begin
clk_en_i = 1'b1;
ser_s_i = 1'b0; // keep the serial select low
ser_inc = 1'b1; // Keep incrementing the counter
ser_capt = 1'b1; // Capture incoming data
// Read in 32 bits of data (4 bytes)
if (&serial_counter) begin
nstate = PERIPH_END;
per_done_i = 1'b1; // signal cycle done
end else
nstate = SPROM_READ;
end
SPROM_WIDLE: begin
per_ready_i = 1'b1; // be ready in next idle state
aux_buff_en_i = 1'b0;
ser_s_i = 1'b0; // keep the serial select low
ser_h_i = 1'b0;
ser_inc = 1'b1; // Keep incrementing the counter
clk_en_i = 1'b1;
if (sepm_cmd == SEPM_EOP && sepm_busy) begin
clk_en_i = 1'b0;
ser_h_i = 1'b1;
// ser_s_i = 1'b1;
clear_serial_counter = 1'b1;
nstate = SPROM_S;
per_done_i = 1'b1; // signal cycle done
end else if (!per_prom & per_req & ~per_lbe_f) begin
// clear_serial_counter = 1;
nstate = SPROM_WIDLE1;
end else nstate = SPROM_WIDLE;
end // case: SPROM_WIDLE
SPROM_S: begin
// Delay releasing S until 1 cycle after releasing hold
clk_en_i = 1'b0;
ser_s_i = 1'b1;
ser_inc = 1'b1; // Keep incrementing the counter
if (&serial_counter[2:0]) begin
clear_serial_counter = 1'b1;
nstate = SPROM_RDSR_IDLE;
ser_h_i = 1'b1;
end else nstate = SPROM_S;
end
SPROM_WIDLE1: begin
aux_buff_en_i = 1'b0;
ser_s_i = 1'b0; // keep the serial select low
ser_inc = 1'b1; // Keep incrementing the counter
clk_en_i = 1'b1;
ser_h_i = 1'b0;
if (~|serial_counter[3:0]) begin
nstate = SPROM_WRITE;
ser_h_i = 1'b1;
end else nstate = SPROM_WIDLE1;
end // case: SPROM_WIDLE
SPROM_WRITE: begin
clk_en_i = 1'b1;
aux_buff_en_i = 1'b0;
ser_s_i = 1'b0; // keep the serial select low
ser_inc = 1'b1; // Increment the counter
if (&serial_counter[3:0]) begin
per_done_i = 1'b1; // signal cycle done
nstate = SPROM_WIDLE;
end else
nstate = SPROM_WRITE;
end
SPROM_RDSR_IDLE: begin
ser_inc = 1'b1; // Increment the counter
if (&serial_counter[2:0]) begin
aux_buff_en_i = 1'b0;
clear_serial_counter = 1'b1;
nstate = SPROM_RDSR_IDLE1;
end else nstate = SPROM_RDSR_IDLE;
end
SPROM_RDSR_IDLE1: begin
clk_en_i = 1'b1;
aux_buff_en_i = 1'b0;
ser_s_i = 1'b0; // keep the serial select low
clear_serial_counter = 1'b1;
nstate = SPROM_RDSR;
rdsr = 1'b1;
end
SPROM_RDSR: begin
clk_en_i = 1'b1;
rdsr = 1'b1;
aux_buff_en_i = 1'b0;
ser_s_i = 1'b0; // keep the serial select low
ser_inc = 1'b1; // Increment the counter
ser_addr_en_i = 1'b1; // select the command output
if (&serial_counter[3:0]) begin
//clear_serial_counter = 1;
nstate = SPROM_WIP;
end else nstate = SPROM_RDSR;
end
SPROM_WIP: begin
clk_en_i = 1'b1;
ser_s_i = 1'b0; // keep the serial select low
ser_inc = 1'b1; // Increment the counter
if (&serial_counter[3:0] && ~aux_data_in[1]) begin
// The WIP bit has gone low, so we're done
clr_sepm_busy = 1'b1; // Clear the busy flag
nstate = PERIPH_END;
end else nstate = SPROM_WIP;
end
PERIPH_END: begin // disable all divers
per_ready_i = 1'b1; // be ready in next idle state
nstate = IDLE ;
end
default: nstate = IDLE ;
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFXTP_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__SDFXTP_PP_BLACKBOX_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sdfxtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFXTP_PP_BLACKBOX_V
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_nios2_qsys_0_mult_cell (
// inputs:
A_mul_src1,
A_mul_src2,
clk,
reset_n,
// outputs:
A_mul_cell_result
)
;
output [ 31: 0] A_mul_cell_result;
input [ 31: 0] A_mul_src1;
input [ 31: 0] A_mul_src2;
input clk;
input reset_n;
wire [ 31: 0] A_mul_cell_result;
wire [ 31: 0] A_mul_cell_result_part_1;
wire [ 15: 0] A_mul_cell_result_part_2;
wire mul_clr;
assign mul_clr = ~reset_n;
altera_mult_add the_altmult_add_part_1
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (A_mul_src1[15 : 0]),
.datab (A_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (A_mul_cell_result_part_1)
);
defparam the_altmult_add_part_1.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_1.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_1.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_1.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_1.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_1.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_1.input_source_a0 = "DATAA",
the_altmult_add_part_1.input_source_b0 = "DATAB",
the_altmult_add_part_1.lpm_type = "altera_mult_add",
the_altmult_add_part_1.multiplier1_direction = "ADD",
the_altmult_add_part_1.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_1.multiplier_register0 = "CLOCK0",
the_altmult_add_part_1.number_of_multipliers = 1,
the_altmult_add_part_1.output_register = "UNREGISTERED",
the_altmult_add_part_1.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_1.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_part_1.port_signa = "PORT_UNUSED",
the_altmult_add_part_1.port_signb = "PORT_UNUSED",
the_altmult_add_part_1.representation_a = "UNSIGNED",
the_altmult_add_part_1.representation_b = "UNSIGNED",
the_altmult_add_part_1.selected_device_family = "CYCLONEII",
the_altmult_add_part_1.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_1.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_1.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_1.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_1.signed_register_a = "UNREGISTERED",
the_altmult_add_part_1.signed_register_b = "UNREGISTERED",
the_altmult_add_part_1.width_a = 16,
the_altmult_add_part_1.width_b = 16,
the_altmult_add_part_1.width_result = 32;
altera_mult_add the_altmult_add_part_2
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (A_mul_src1[31 : 16]),
.datab (A_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (A_mul_cell_result_part_2)
);
defparam the_altmult_add_part_2.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_2.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_2.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_2.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_2.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_2.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_2.input_source_a0 = "DATAA",
the_altmult_add_part_2.input_source_b0 = "DATAB",
the_altmult_add_part_2.lpm_type = "altera_mult_add",
the_altmult_add_part_2.multiplier1_direction = "ADD",
the_altmult_add_part_2.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_2.multiplier_register0 = "CLOCK0",
the_altmult_add_part_2.number_of_multipliers = 1,
the_altmult_add_part_2.output_register = "UNREGISTERED",
the_altmult_add_part_2.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_2.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_part_2.port_signa = "PORT_UNUSED",
the_altmult_add_part_2.port_signb = "PORT_UNUSED",
the_altmult_add_part_2.representation_a = "UNSIGNED",
the_altmult_add_part_2.representation_b = "UNSIGNED",
the_altmult_add_part_2.selected_device_family = "CYCLONEII",
the_altmult_add_part_2.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_2.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_2.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_2.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_2.signed_register_a = "UNREGISTERED",
the_altmult_add_part_2.signed_register_b = "UNREGISTERED",
the_altmult_add_part_2.width_a = 16,
the_altmult_add_part_2.width_b = 16,
the_altmult_add_part_2.width_result = 16;
assign A_mul_cell_result = {A_mul_cell_result_part_1[31 : 16] +
A_mul_cell_result_part_2,
A_mul_cell_result_part_1[15 : 0]};
endmodule
|
//
// Copyright (c) 2013 Alexandre Joannou
// Copyright (c) 2014 A. Theodore Markettos
// All rights reserved.
//
// This software was developed by SRI International and the University of
// Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
// ("CTSRD"), as part of the DARPA CRASH research programme.
//
// @BERI_LICENSE_HEADER_START@
//
// Licensed to BERI Open Systems C.I.C. (BERI) under one or more contributor
// license agreements. See the NOTICE file distributed with this work for
// additional information regarding copyright ownership. BERI licenses this
// file to you under the BERI Hardware-Software License, Version 1.0 (the
// "License"); you may not use this file except in compliance with the
// License. You may obtain a copy of the License at:
//
// http://www.beri-open-systems.org/legal/license-1-0.txt
//
// Unless required by applicable law or agreed to in writing, Work distributed
// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// @BERI_LICENSE_HEADER_END@
//
module AsymmetricBRAM(
CLK,
RADDR,
RDATA,
REN,
WADDR,
WDATA,
WEN
);
parameter PIPELINED = 'd 0;
parameter FORWARDING = 'd 0;
parameter WADDR_WIDTH = 'd 0;
parameter WDATA_WIDTH = 'd 0;
parameter RADDR_WIDTH = 'd 0;
parameter RDATA_WIDTH = 'd 0;
parameter MEMSIZE = 'd 1;
parameter REGISTERED = (PIPELINED == 0) ? "UNREGISTERED":"CLOCK0";
input CLK;
input [RADDR_WIDTH-1:0] RADDR;
output [RDATA_WIDTH-1:0] RDATA;
input REN;
input [WADDR_WIDTH-1:0] WADDR;
input [WDATA_WIDTH-1:0] WDATA;
input WEN;
/*
wire [RDATA_WIDTH-1:0] BRAM_RDATA;
wire [RADDR_WIDTH-1:0] RADDR_MUXED;
reg [RADDR_WIDTH-1:0] LAST_RADDR;
reg [WDATA_WIDTH-1:0] LAST_WDATA;
reg [WADDR_WIDTH-1:0] LAST_WADDR;
always @(posedge CLK) begin
if (WEN) begin
LAST_WADDR <= WADDR;
LAST_WDATA <= WDATA;
end
LAST_RADDR <= RADDR_MUXED;
end
assign RADDR_MUXED = (REN) ? RADDR : LAST_RADDR;
assign RDATA = (LAST_RADDR==LAST_WADDR) ? LAST_WDATA : BRAM_RDATA;
*/
altsyncram altsyncram_component (
.address_a (WADDR),
.clock0 (CLK),
.data_a (WDATA),
.rden_b (REN),
.wren_a (WEN),
.address_b (RADDR),
.q_b (RDATA),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({32{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = MEMSIZE / (WDATA_WIDTH/RDATA_WIDTH),
altsyncram_component.numwords_b = MEMSIZE,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = REGISTERED,
altsyncram_component.power_up_uninitialized = "TRUE",
altsyncram_component.ram_block_type = "M9K",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = WADDR_WIDTH,
altsyncram_component.widthad_b = RADDR_WIDTH,
altsyncram_component.width_a = WDATA_WIDTH,
altsyncram_component.width_b = RDATA_WIDTH,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O32AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__O32AI_BEHAVIORAL_PP_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o32ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A3, A1, A2 );
nor nor1 (nor1_out , B1, B2 );
or or0 (or0_out_Y , nor1_out, nor0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O32AI_BEHAVIORAL_PP_V |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_img_2_cols_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_img_2_cols_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_img_2_cols_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_img_2_cols_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.1.0 Build 186 12/03/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module pll (
inclk0,
c0);
input inclk0;
output c0;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_dbg.v
//
// *Module Description:
// Debug interface
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 175 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2013-01-30 22:21:42 +0100 (Mit, 30. Jän 2013) $
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module omsp_dbg (
// OUTPUTs
dbg_cpu_reset, // Reset CPU from debug interface
dbg_freeze, // Freeze peripherals
dbg_halt_cmd, // Halt CPU command
dbg_i2c_sda_out, // Debug interface: I2C SDA OUT
dbg_mem_addr, // Debug address for rd/wr access
dbg_mem_dout, // Debug unit data output
dbg_mem_en, // Debug unit memory enable
dbg_mem_wr, // Debug unit memory write
dbg_reg_wr, // Debug unit CPU register write
dbg_uart_txd, // Debug interface: UART TXD
// INPUTs
cpu_en_s, // Enable CPU code execution (synchronous)
cpu_id, // CPU ID
cpu_nr_inst, // Current oMSP instance number
cpu_nr_total, // Total number of oMSP instances-1
dbg_clk, // Debug unit clock
dbg_en_s, // Debug interface enable (synchronous)
dbg_halt_st, // Halt/Run status from CPU
dbg_i2c_addr, // Debug interface: I2C Address
dbg_i2c_broadcast, // Debug interface: I2C Broadcast Address (for multicore systems)
dbg_i2c_scl, // Debug interface: I2C SCL
dbg_i2c_sda_in, // Debug interface: I2C SDA IN
dbg_mem_din, // Debug unit Memory data input
dbg_reg_din, // Debug unit CPU register data input
dbg_rst, // Debug unit reset
dbg_uart_rxd, // Debug interface: UART RXD (asynchronous)
decode_noirq, // Frontend decode instruction
eu_mab, // Execution-Unit Memory address bus
eu_mb_en, // Execution-Unit Memory bus enable
eu_mb_wr, // Execution-Unit Memory bus write transfer
fe_mdb_in, // Frontend Memory data bus input
pc, // Program counter
puc_pnd_set // PUC pending set for the serial debug interface
);
// OUTPUTs
//=========
output dbg_cpu_reset; // Reset CPU from debug interface
output dbg_freeze; // Freeze peripherals
output dbg_halt_cmd; // Halt CPU command
output dbg_i2c_sda_out; // Debug interface: I2C SDA OUT
output [15:0] dbg_mem_addr; // Debug address for rd/wr access
output [15:0] dbg_mem_dout; // Debug unit data output
output dbg_mem_en; // Debug unit memory enable
output [1:0] dbg_mem_wr; // Debug unit memory write
output dbg_reg_wr; // Debug unit CPU register write
output dbg_uart_txd; // Debug interface: UART TXD
// INPUTs
//=========
input cpu_en_s; // Enable CPU code execution (synchronous)
input [31:0] cpu_id; // CPU ID
input [7:0] cpu_nr_inst; // Current oMSP instance number
input [7:0] cpu_nr_total; // Total number of oMSP instances-1
input dbg_clk; // Debug unit clock
input dbg_en_s; // Debug interface enable (synchronous)
input dbg_halt_st; // Halt/Run status from CPU
input [6:0] dbg_i2c_addr; // Debug interface: I2C Address
input [6:0] dbg_i2c_broadcast; // Debug interface: I2C Broadcast Address (for multicore systems)
input dbg_i2c_scl; // Debug interface: I2C SCL
input dbg_i2c_sda_in; // Debug interface: I2C SDA IN
input [15:0] dbg_mem_din; // Debug unit Memory data input
input [15:0] dbg_reg_din; // Debug unit CPU register data input
input dbg_rst; // Debug unit reset
input dbg_uart_rxd; // Debug interface: UART RXD (asynchronous)
input decode_noirq; // Frontend decode instruction
input [15:0] eu_mab; // Execution-Unit Memory address bus
input eu_mb_en; // Execution-Unit Memory bus enable
input [1:0] eu_mb_wr; // Execution-Unit Memory bus write transfer
input [15:0] fe_mdb_in; // Frontend Memory data bus input
input [15:0] pc; // Program counter
input puc_pnd_set; // PUC pending set for the serial debug interface
//=============================================================================
// 1) WIRE & PARAMETER DECLARATION
//=============================================================================
// Diverse wires and registers
wire [5:0] dbg_addr;
wire [15:0] dbg_din;
wire dbg_wr;
reg mem_burst;
wire dbg_reg_rd;
wire dbg_mem_rd;
reg dbg_mem_rd_dly;
wire dbg_swbrk;
wire dbg_rd;
reg dbg_rd_rdy;
wire mem_burst_rd;
wire mem_burst_wr;
wire brk0_halt;
wire brk0_pnd;
wire [15:0] brk0_dout;
wire brk1_halt;
wire brk1_pnd;
wire [15:0] brk1_dout;
wire brk2_halt;
wire brk2_pnd;
wire [15:0] brk2_dout;
wire brk3_halt;
wire brk3_pnd;
wire [15:0] brk3_dout;
// Number of registers
parameter NR_REG = 25;
// Register addresses
parameter CPU_ID_LO = 6'h00;
parameter CPU_ID_HI = 6'h01;
parameter CPU_CTL = 6'h02;
parameter CPU_STAT = 6'h03;
parameter MEM_CTL = 6'h04;
parameter MEM_ADDR = 6'h05;
parameter MEM_DATA = 6'h06;
parameter MEM_CNT = 6'h07;
`ifdef DBG_HWBRK_0
parameter BRK0_CTL = 6'h08;
parameter BRK0_STAT = 6'h09;
parameter BRK0_ADDR0 = 6'h0A;
parameter BRK0_ADDR1 = 6'h0B;
`endif
`ifdef DBG_HWBRK_1
parameter BRK1_CTL = 6'h0C;
parameter BRK1_STAT = 6'h0D;
parameter BRK1_ADDR0 = 6'h0E;
parameter BRK1_ADDR1 = 6'h0F;
`endif
`ifdef DBG_HWBRK_2
parameter BRK2_CTL = 6'h10;
parameter BRK2_STAT = 6'h11;
parameter BRK2_ADDR0 = 6'h12;
parameter BRK2_ADDR1 = 6'h13;
`endif
`ifdef DBG_HWBRK_3
parameter BRK3_CTL = 6'h14;
parameter BRK3_STAT = 6'h15;
parameter BRK3_ADDR0 = 6'h16;
parameter BRK3_ADDR1 = 6'h17;
`endif
parameter CPU_NR = 6'h18;
// Register one-hot decoder
parameter BASE_D = {{NR_REG-1{1'b0}}, 1'b1};
parameter CPU_ID_LO_D = (BASE_D << CPU_ID_LO);
parameter CPU_ID_HI_D = (BASE_D << CPU_ID_HI);
parameter CPU_CTL_D = (BASE_D << CPU_CTL);
parameter CPU_STAT_D = (BASE_D << CPU_STAT);
parameter MEM_CTL_D = (BASE_D << MEM_CTL);
parameter MEM_ADDR_D = (BASE_D << MEM_ADDR);
parameter MEM_DATA_D = (BASE_D << MEM_DATA);
parameter MEM_CNT_D = (BASE_D << MEM_CNT);
`ifdef DBG_HWBRK_0
parameter BRK0_CTL_D = (BASE_D << BRK0_CTL);
parameter BRK0_STAT_D = (BASE_D << BRK0_STAT);
parameter BRK0_ADDR0_D = (BASE_D << BRK0_ADDR0);
parameter BRK0_ADDR1_D = (BASE_D << BRK0_ADDR1);
`endif
`ifdef DBG_HWBRK_1
parameter BRK1_CTL_D = (BASE_D << BRK1_CTL);
parameter BRK1_STAT_D = (BASE_D << BRK1_STAT);
parameter BRK1_ADDR0_D = (BASE_D << BRK1_ADDR0);
parameter BRK1_ADDR1_D = (BASE_D << BRK1_ADDR1);
`endif
`ifdef DBG_HWBRK_2
parameter BRK2_CTL_D = (BASE_D << BRK2_CTL);
parameter BRK2_STAT_D = (BASE_D << BRK2_STAT);
parameter BRK2_ADDR0_D = (BASE_D << BRK2_ADDR0);
parameter BRK2_ADDR1_D = (BASE_D << BRK2_ADDR1);
`endif
`ifdef DBG_HWBRK_3
parameter BRK3_CTL_D = (BASE_D << BRK3_CTL);
parameter BRK3_STAT_D = (BASE_D << BRK3_STAT);
parameter BRK3_ADDR0_D = (BASE_D << BRK3_ADDR0);
parameter BRK3_ADDR1_D = (BASE_D << BRK3_ADDR1);
`endif
parameter CPU_NR_D = (BASE_D << CPU_NR);
//============================================================================
// 2) REGISTER DECODER
//============================================================================
// Select Data register during a burst
wire [5:0] dbg_addr_in = mem_burst ? MEM_DATA : dbg_addr;
// Register address decode
reg [NR_REG-1:0] reg_dec;
always @(dbg_addr_in)
case (dbg_addr_in)
CPU_ID_LO : reg_dec = CPU_ID_LO_D;
CPU_ID_HI : reg_dec = CPU_ID_HI_D;
CPU_CTL : reg_dec = CPU_CTL_D;
CPU_STAT : reg_dec = CPU_STAT_D;
MEM_CTL : reg_dec = MEM_CTL_D;
MEM_ADDR : reg_dec = MEM_ADDR_D;
MEM_DATA : reg_dec = MEM_DATA_D;
MEM_CNT : reg_dec = MEM_CNT_D;
`ifdef DBG_HWBRK_0
BRK0_CTL : reg_dec = BRK0_CTL_D;
BRK0_STAT : reg_dec = BRK0_STAT_D;
BRK0_ADDR0: reg_dec = BRK0_ADDR0_D;
BRK0_ADDR1: reg_dec = BRK0_ADDR1_D;
`endif
`ifdef DBG_HWBRK_1
BRK1_CTL : reg_dec = BRK1_CTL_D;
BRK1_STAT : reg_dec = BRK1_STAT_D;
BRK1_ADDR0: reg_dec = BRK1_ADDR0_D;
BRK1_ADDR1: reg_dec = BRK1_ADDR1_D;
`endif
`ifdef DBG_HWBRK_2
BRK2_CTL : reg_dec = BRK2_CTL_D;
BRK2_STAT : reg_dec = BRK2_STAT_D;
BRK2_ADDR0: reg_dec = BRK2_ADDR0_D;
BRK2_ADDR1: reg_dec = BRK2_ADDR1_D;
`endif
`ifdef DBG_HWBRK_3
BRK3_CTL : reg_dec = BRK3_CTL_D;
BRK3_STAT : reg_dec = BRK3_STAT_D;
BRK3_ADDR0: reg_dec = BRK3_ADDR0_D;
BRK3_ADDR1: reg_dec = BRK3_ADDR1_D;
`endif
CPU_NR : reg_dec = CPU_NR_D;
// pragma coverage off
default: reg_dec = {NR_REG{1'b0}};
// pragma coverage on
endcase
// Read/Write probes
wire reg_write = dbg_wr;
wire reg_read = 1'b1;
// Read/Write vectors
wire [NR_REG-1:0] reg_wr = reg_dec & {NR_REG{reg_write}};
wire [NR_REG-1:0] reg_rd = reg_dec & {NR_REG{reg_read}};
//=============================================================================
// 3) REGISTER: CORE INTERFACE
//=============================================================================
// CPU_ID Register
//-----------------
// -------------------------------------------------------------------
// CPU_ID_LO: | 15 14 13 12 11 10 9 | 8 7 6 5 4 | 3 | 2 1 0 |
// |----------------------------+-----------------+------+-------------|
// | PER_SPACE | USER_VERSION | ASIC | CPU_VERSION |
// --------------------------------------------------------------------
// CPU_ID_HI: | 15 14 13 12 11 10 | 9 8 7 6 5 4 3 2 1 | 0 |
// |----------------------------+-------------------------------+------|
// | PMEM_SIZE | DMEM_SIZE | MPY |
// -------------------------------------------------------------------
// This register is assigned in the SFR module
// CPU_NR Register
//-----------------
// -------------------------------------------------------------------
// | 15 14 13 12 11 10 9 8 | 7 6 5 4 3 2 1 0 |
// |---------------------------------+---------------------------------|
// | CPU_TOTAL_NR | CPU_INST_NR |
// -------------------------------------------------------------------
wire [15:0] cpu_nr = {cpu_nr_total, cpu_nr_inst};
// CPU_CTL Register
//-----------------------------------------------------------------------------
// 7 6 5 4 3 2 1 0
// Reserved CPU_RST RST_BRK_EN FRZ_BRK_EN SW_BRK_EN ISTEP RUN HALT
//-----------------------------------------------------------------------------
reg [6:3] cpu_ctl;
wire cpu_ctl_wr = reg_wr[CPU_CTL];
always @ (posedge dbg_clk or posedge dbg_rst)
`ifdef DBG_RST_BRK_EN
if (dbg_rst) cpu_ctl <= 4'h6;
`else
if (dbg_rst) cpu_ctl <= 4'h2;
`endif
else if (cpu_ctl_wr) cpu_ctl <= dbg_din[6:3];
wire [7:0] cpu_ctl_full = {1'b0, cpu_ctl, 3'b000};
wire halt_cpu = cpu_ctl_wr & dbg_din[`HALT] & ~dbg_halt_st;
wire run_cpu = cpu_ctl_wr & dbg_din[`RUN] & dbg_halt_st;
wire istep = cpu_ctl_wr & dbg_din[`ISTEP] & dbg_halt_st;
// CPU_STAT Register
//------------------------------------------------------------------------------------
// 7 6 5 4 3 2 1 0
// HWBRK3_PND HWBRK2_PND HWBRK1_PND HWBRK0_PND SWBRK_PND PUC_PND Res. HALT_RUN
//------------------------------------------------------------------------------------
reg [3:2] cpu_stat;
wire cpu_stat_wr = reg_wr[CPU_STAT];
wire [3:2] cpu_stat_set = {dbg_swbrk, puc_pnd_set};
wire [3:2] cpu_stat_clr = ~dbg_din[3:2];
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) cpu_stat <= 2'b00;
else if (cpu_stat_wr) cpu_stat <= ((cpu_stat & cpu_stat_clr) | cpu_stat_set);
else cpu_stat <= (cpu_stat | cpu_stat_set);
wire [7:0] cpu_stat_full = {brk3_pnd, brk2_pnd, brk1_pnd, brk0_pnd,
cpu_stat, 1'b0, dbg_halt_st};
//=============================================================================
// 4) REGISTER: MEMORY INTERFACE
//=============================================================================
// MEM_CTL Register
//-----------------------------------------------------------------------------
// 7 6 5 4 3 2 1 0
// Reserved B/W MEM/REG RD/WR START
//
// START : - 0 : Do nothing.
// - 1 : Initiate memory transfer.
//
// RD/WR : - 0 : Read access.
// - 1 : Write access.
//
// MEM/REG: - 0 : Memory access.
// - 1 : CPU Register access.
//
// B/W : - 0 : 16 bit access.
// - 1 : 8 bit access (not valid for CPU Registers).
//
//-----------------------------------------------------------------------------
reg [3:1] mem_ctl;
wire mem_ctl_wr = reg_wr[MEM_CTL];
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_ctl <= 3'h0;
else if (mem_ctl_wr) mem_ctl <= dbg_din[3:1];
wire [7:0] mem_ctl_full = {4'b0000, mem_ctl, 1'b0};
reg mem_start;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_start <= 1'b0;
else mem_start <= mem_ctl_wr & dbg_din[0];
wire mem_bw = mem_ctl[3];
// MEM_DATA Register
//------------------
reg [15:0] mem_data;
reg [15:0] mem_addr;
wire mem_access;
wire mem_data_wr = reg_wr[MEM_DATA];
wire [15:0] dbg_mem_din_bw = ~mem_bw ? dbg_mem_din :
mem_addr[0] ? {8'h00, dbg_mem_din[15:8]} :
{8'h00, dbg_mem_din[7:0]};
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_data <= 16'h0000;
else if (mem_data_wr) mem_data <= dbg_din;
else if (dbg_reg_rd) mem_data <= dbg_reg_din;
else if (dbg_mem_rd_dly) mem_data <= dbg_mem_din_bw;
// MEM_ADDR Register
//------------------
reg [15:0] mem_cnt;
wire mem_addr_wr = reg_wr[MEM_ADDR];
wire dbg_mem_acc = (|dbg_mem_wr | (dbg_rd_rdy & ~mem_ctl[2]));
wire dbg_reg_acc = ( dbg_reg_wr | (dbg_rd_rdy & mem_ctl[2]));
wire [15:0] mem_addr_inc = (mem_cnt==16'h0000) ? 16'h0000 :
(mem_burst & dbg_mem_acc & ~mem_bw) ? 16'h0002 :
(mem_burst & (dbg_mem_acc | dbg_reg_acc)) ? 16'h0001 : 16'h0000;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_addr <= 16'h0000;
else if (mem_addr_wr) mem_addr <= dbg_din;
else mem_addr <= mem_addr + mem_addr_inc;
// MEM_CNT Register
//------------------
wire mem_cnt_wr = reg_wr[MEM_CNT];
wire [15:0] mem_cnt_dec = (mem_cnt==16'h0000) ? 16'h0000 :
(mem_burst & (dbg_mem_acc | dbg_reg_acc)) ? 16'hffff : 16'h0000;
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_cnt <= 16'h0000;
else if (mem_cnt_wr) mem_cnt <= dbg_din;
else mem_cnt <= mem_cnt + mem_cnt_dec;
//=============================================================================
// 5) BREAKPOINTS / WATCHPOINTS
//=============================================================================
`ifdef DBG_HWBRK_0
// Hardware Breakpoint/Watchpoint Register read select
wire [3:0] brk0_reg_rd = {reg_rd[BRK0_ADDR1],
reg_rd[BRK0_ADDR0],
reg_rd[BRK0_STAT],
reg_rd[BRK0_CTL]};
// Hardware Breakpoint/Watchpoint Register write select
wire [3:0] brk0_reg_wr = {reg_wr[BRK0_ADDR1],
reg_wr[BRK0_ADDR0],
reg_wr[BRK0_STAT],
reg_wr[BRK0_CTL]};
omsp_dbg_hwbrk dbg_hwbr_0 (
// OUTPUTs
.brk_halt (brk0_halt), // Hardware breakpoint command
.brk_pnd (brk0_pnd), // Hardware break/watch-point pending
.brk_dout (brk0_dout), // Hardware break/watch-point register data input
// INPUTs
.brk_reg_rd (brk0_reg_rd), // Hardware break/watch-point register read select
.brk_reg_wr (brk0_reg_wr), // Hardware break/watch-point register write select
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_din (dbg_din), // Debug register data input
.dbg_rst (dbg_rst), // Debug unit reset
.decode_noirq (decode_noirq), // Frontend decode instruction
.eu_mab (eu_mab), // Execution-Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
.pc (pc) // Program counter
);
`else
assign brk0_halt = 1'b0;
assign brk0_pnd = 1'b0;
assign brk0_dout = 16'h0000;
`endif
`ifdef DBG_HWBRK_1
// Hardware Breakpoint/Watchpoint Register read select
wire [3:0] brk1_reg_rd = {reg_rd[BRK1_ADDR1],
reg_rd[BRK1_ADDR0],
reg_rd[BRK1_STAT],
reg_rd[BRK1_CTL]};
// Hardware Breakpoint/Watchpoint Register write select
wire [3:0] brk1_reg_wr = {reg_wr[BRK1_ADDR1],
reg_wr[BRK1_ADDR0],
reg_wr[BRK1_STAT],
reg_wr[BRK1_CTL]};
omsp_dbg_hwbrk dbg_hwbr_1 (
// OUTPUTs
.brk_halt (brk1_halt), // Hardware breakpoint command
.brk_pnd (brk1_pnd), // Hardware break/watch-point pending
.brk_dout (brk1_dout), // Hardware break/watch-point register data input
// INPUTs
.brk_reg_rd (brk1_reg_rd), // Hardware break/watch-point register read select
.brk_reg_wr (brk1_reg_wr), // Hardware break/watch-point register write select
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_din (dbg_din), // Debug register data input
.dbg_rst (dbg_rst), // Debug unit reset
.decode_noirq (decode_noirq), // Frontend decode instruction
.eu_mab (eu_mab), // Execution-Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
.pc (pc) // Program counter
);
`else
assign brk1_halt = 1'b0;
assign brk1_pnd = 1'b0;
assign brk1_dout = 16'h0000;
`endif
`ifdef DBG_HWBRK_2
// Hardware Breakpoint/Watchpoint Register read select
wire [3:0] brk2_reg_rd = {reg_rd[BRK2_ADDR1],
reg_rd[BRK2_ADDR0],
reg_rd[BRK2_STAT],
reg_rd[BRK2_CTL]};
// Hardware Breakpoint/Watchpoint Register write select
wire [3:0] brk2_reg_wr = {reg_wr[BRK2_ADDR1],
reg_wr[BRK2_ADDR0],
reg_wr[BRK2_STAT],
reg_wr[BRK2_CTL]};
omsp_dbg_hwbrk dbg_hwbr_2 (
// OUTPUTs
.brk_halt (brk2_halt), // Hardware breakpoint command
.brk_pnd (brk2_pnd), // Hardware break/watch-point pending
.brk_dout (brk2_dout), // Hardware break/watch-point register data input
// INPUTs
.brk_reg_rd (brk2_reg_rd), // Hardware break/watch-point register read select
.brk_reg_wr (brk2_reg_wr), // Hardware break/watch-point register write select
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_din (dbg_din), // Debug register data input
.dbg_rst (dbg_rst), // Debug unit reset
.decode_noirq (decode_noirq), // Frontend decode instruction
.eu_mab (eu_mab), // Execution-Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
.pc (pc) // Program counter
);
`else
assign brk2_halt = 1'b0;
assign brk2_pnd = 1'b0;
assign brk2_dout = 16'h0000;
`endif
`ifdef DBG_HWBRK_3
// Hardware Breakpoint/Watchpoint Register read select
wire [3:0] brk3_reg_rd = {reg_rd[BRK3_ADDR1],
reg_rd[BRK3_ADDR0],
reg_rd[BRK3_STAT],
reg_rd[BRK3_CTL]};
// Hardware Breakpoint/Watchpoint Register write select
wire [3:0] brk3_reg_wr = {reg_wr[BRK3_ADDR1],
reg_wr[BRK3_ADDR0],
reg_wr[BRK3_STAT],
reg_wr[BRK3_CTL]};
omsp_dbg_hwbrk dbg_hwbr_3 (
// OUTPUTs
.brk_halt (brk3_halt), // Hardware breakpoint command
.brk_pnd (brk3_pnd), // Hardware break/watch-point pending
.brk_dout (brk3_dout), // Hardware break/watch-point register data input
// INPUTs
.brk_reg_rd (brk3_reg_rd), // Hardware break/watch-point register read select
.brk_reg_wr (brk3_reg_wr), // Hardware break/watch-point register write select
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_din (dbg_din), // Debug register data input
.dbg_rst (dbg_rst), // Debug unit reset
.decode_noirq (decode_noirq), // Frontend decode instruction
.eu_mab (eu_mab), // Execution-Unit Memory address bus
.eu_mb_en (eu_mb_en), // Execution-Unit Memory bus enable
.eu_mb_wr (eu_mb_wr), // Execution-Unit Memory bus write transfer
.pc (pc) // Program counter
);
`else
assign brk3_halt = 1'b0;
assign brk3_pnd = 1'b0;
assign brk3_dout = 16'h0000;
`endif
//============================================================================
// 6) DATA OUTPUT GENERATION
//============================================================================
wire [15:0] cpu_id_lo_rd = cpu_id[15:0] & {16{reg_rd[CPU_ID_LO]}};
wire [15:0] cpu_id_hi_rd = cpu_id[31:16] & {16{reg_rd[CPU_ID_HI]}};
wire [15:0] cpu_ctl_rd = {8'h00, cpu_ctl_full} & {16{reg_rd[CPU_CTL]}};
wire [15:0] cpu_stat_rd = {8'h00, cpu_stat_full} & {16{reg_rd[CPU_STAT]}};
wire [15:0] mem_ctl_rd = {8'h00, mem_ctl_full} & {16{reg_rd[MEM_CTL]}};
wire [15:0] mem_data_rd = mem_data & {16{reg_rd[MEM_DATA]}};
wire [15:0] mem_addr_rd = mem_addr & {16{reg_rd[MEM_ADDR]}};
wire [15:0] mem_cnt_rd = mem_cnt & {16{reg_rd[MEM_CNT]}};
wire [15:0] cpu_nr_rd = cpu_nr & {16{reg_rd[CPU_NR]}};
wire [15:0] dbg_dout = cpu_id_lo_rd |
cpu_id_hi_rd |
cpu_ctl_rd |
cpu_stat_rd |
mem_ctl_rd |
mem_data_rd |
mem_addr_rd |
mem_cnt_rd |
brk0_dout |
brk1_dout |
brk2_dout |
brk3_dout |
cpu_nr_rd;
// Tell UART/I2C interface that the data is ready to be read
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) dbg_rd_rdy <= 1'b0;
else if (mem_burst | mem_burst_rd) dbg_rd_rdy <= (dbg_reg_rd | dbg_mem_rd_dly);
else dbg_rd_rdy <= dbg_rd;
//============================================================================
// 7) CPU CONTROL
//============================================================================
// Reset CPU
//--------------------------
wire dbg_cpu_reset = cpu_ctl[`CPU_RST];
// Break after reset
//--------------------------
wire halt_rst = cpu_ctl[`RST_BRK_EN] & dbg_en_s & puc_pnd_set;
// Freeze peripherals
//--------------------------
wire dbg_freeze = dbg_halt_st & (cpu_ctl[`FRZ_BRK_EN] | ~cpu_en_s);
// Software break
//--------------------------
assign dbg_swbrk = (fe_mdb_in==`DBG_SWBRK_OP) & decode_noirq & cpu_ctl[`SW_BRK_EN];
// Single step
//--------------------------
reg [1:0] inc_step;
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) inc_step <= 2'b00;
else if (istep) inc_step <= 2'b11;
else inc_step <= {inc_step[0], 1'b0};
// Run / Halt
//--------------------------
reg halt_flag;
wire mem_halt_cpu;
wire mem_run_cpu;
wire halt_flag_clr = run_cpu | mem_run_cpu;
wire halt_flag_set = halt_cpu | halt_rst | dbg_swbrk | mem_halt_cpu |
brk0_halt | brk1_halt | brk2_halt | brk3_halt;
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) halt_flag <= 1'b0;
else if (halt_flag_clr) halt_flag <= 1'b0;
else if (halt_flag_set) halt_flag <= 1'b1;
wire dbg_halt_cmd = (halt_flag | halt_flag_set) & ~inc_step[1];
//============================================================================
// 8) MEMORY CONTROL
//============================================================================
// Control Memory bursts
//------------------------------
wire mem_burst_start = (mem_start & |mem_cnt);
wire mem_burst_end = ((dbg_wr | dbg_rd_rdy) & ~|mem_cnt);
// Detect when burst is on going
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_burst <= 1'b0;
else if (mem_burst_start) mem_burst <= 1'b1;
else if (mem_burst_end) mem_burst <= 1'b0;
// Control signals for UART/I2C interface
assign mem_burst_rd = (mem_burst_start & ~mem_ctl[1]);
assign mem_burst_wr = (mem_burst_start & mem_ctl[1]);
// Trigger CPU Register or memory access during a burst
reg mem_startb;
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_startb <= 1'b0;
else mem_startb <= (mem_burst & (dbg_wr | dbg_rd)) | mem_burst_rd;
// Combine single and burst memory start of sequence
wire mem_seq_start = ((mem_start & ~|mem_cnt) | mem_startb);
// Memory access state machine
//------------------------------
reg [1:0] mem_state;
reg [1:0] mem_state_nxt;
// State machine definition
parameter M_IDLE = 2'h0;
parameter M_SET_BRK = 2'h1;
parameter M_ACCESS_BRK = 2'h2;
parameter M_ACCESS = 2'h3;
// State transition
always @(mem_state or mem_seq_start or dbg_halt_st)
case (mem_state)
M_IDLE : mem_state_nxt = ~mem_seq_start ? M_IDLE :
dbg_halt_st ? M_ACCESS : M_SET_BRK;
M_SET_BRK : mem_state_nxt = dbg_halt_st ? M_ACCESS_BRK : M_SET_BRK;
M_ACCESS_BRK : mem_state_nxt = M_IDLE;
M_ACCESS : mem_state_nxt = M_IDLE;
// pragma coverage off
default : mem_state_nxt = M_IDLE;
// pragma coverage on
endcase
// State machine
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) mem_state <= M_IDLE;
else mem_state <= mem_state_nxt;
// Utility signals
assign mem_halt_cpu = (mem_state==M_IDLE) & (mem_state_nxt==M_SET_BRK);
assign mem_run_cpu = (mem_state==M_ACCESS_BRK) & (mem_state_nxt==M_IDLE);
assign mem_access = (mem_state==M_ACCESS) | (mem_state==M_ACCESS_BRK);
// Interface to CPU Registers and Memory bacbkone
//------------------------------------------------
assign dbg_mem_addr = mem_addr;
assign dbg_mem_dout = ~mem_bw ? mem_data :
mem_addr[0] ? {mem_data[7:0], 8'h00} :
{8'h00, mem_data[7:0]};
assign dbg_reg_wr = mem_access & mem_ctl[1] & mem_ctl[2];
assign dbg_reg_rd = mem_access & ~mem_ctl[1] & mem_ctl[2];
assign dbg_mem_en = mem_access & ~mem_ctl[2];
assign dbg_mem_rd = dbg_mem_en & ~mem_ctl[1];
wire [1:0] dbg_mem_wr_msk = ~mem_bw ? 2'b11 :
mem_addr[0] ? 2'b10 : 2'b01;
assign dbg_mem_wr = {2{dbg_mem_en & mem_ctl[1]}} & dbg_mem_wr_msk;
// It takes one additional cycle to read from Memory as from registers
always @(posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) dbg_mem_rd_dly <= 1'b0;
else dbg_mem_rd_dly <= dbg_mem_rd;
//=============================================================================
// 9) UART COMMUNICATION
//=============================================================================
`ifdef DBG_UART
omsp_dbg_uart dbg_uart_0 (
// OUTPUTs
.dbg_addr (dbg_addr), // Debug register address
.dbg_din (dbg_din), // Debug register data input
.dbg_rd (dbg_rd), // Debug register data read
.dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
.dbg_wr (dbg_wr), // Debug register data write
// INPUTs
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_dout (dbg_dout), // Debug register data output
.dbg_rd_rdy (dbg_rd_rdy), // Debug register data is ready for read
.dbg_rst (dbg_rst), // Debug unit reset
.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD
.mem_burst (mem_burst), // Burst on going
.mem_burst_end (mem_burst_end), // End TX/RX burst
.mem_burst_rd (mem_burst_rd), // Start TX burst
.mem_burst_wr (mem_burst_wr), // Start RX burst
.mem_bw (mem_bw) // Burst byte width
);
`else
assign dbg_uart_txd = 1'b1;
`ifdef DBG_I2C
`else
assign dbg_addr = 6'h00;
assign dbg_din = 16'h0000;
assign dbg_rd = 1'b0;
assign dbg_wr = 1'b0;
`endif
`endif
//=============================================================================
// 10) I2C COMMUNICATION
//=============================================================================
`ifdef DBG_I2C
omsp_dbg_i2c dbg_i2c_0 (
// OUTPUTs
.dbg_addr (dbg_addr), // Debug register address
.dbg_din (dbg_din), // Debug register data input
.dbg_i2c_sda_out (dbg_i2c_sda_out), // Debug interface: I2C SDA OUT
.dbg_rd (dbg_rd), // Debug register data read
.dbg_wr (dbg_wr), // Debug register data write
// INPUTs
.dbg_clk (dbg_clk), // Debug unit clock
.dbg_dout (dbg_dout), // Debug register data output
.dbg_i2c_addr (dbg_i2c_addr), // Debug interface: I2C Address
.dbg_i2c_broadcast (dbg_i2c_broadcast), // Debug interface: I2C Broadcast Address (for multicore systems)
.dbg_i2c_scl (dbg_i2c_scl), // Debug interface: I2C SCL
.dbg_i2c_sda_in (dbg_i2c_sda_in), // Debug interface: I2C SDA IN
.dbg_rd_rdy (dbg_rd_rdy), // Debug register data is ready for read
.dbg_rst (dbg_rst), // Debug unit reset
.mem_burst (mem_burst), // Burst on going
.mem_burst_end (mem_burst_end), // End TX/RX burst
.mem_burst_rd (mem_burst_rd), // Start TX burst
.mem_burst_wr (mem_burst_wr), // Start RX burst
.mem_bw (mem_bw) // Burst byte width
);
`else
assign dbg_i2c_sda_out = 1'b1;
`endif
endmodule // omsp_dbg
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Wed Mar 01 09:52:04 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_inverter_1_0/system_inverter_1_0_sim_netlist.v
// Design : system_inverter_1_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_inverter_1_0,inverter,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "inverter,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_inverter_1_0
(x,
x_not);
input x;
output x_not;
wire x;
wire x_not;
LUT1 #(
.INIT(2'h1))
x_not_INST_0
(.I0(x),
.O(x_not));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_clk_gl_vrt_all.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// ------------------------------------------------------------------
module bw_clk_gl_vrt1(c12 ,sctag_in ,sctag_out ,c7 );
output [1:0] sctag_out ;
output [7:0] c7 ;
input [1:0] sctag_in ;
input c12 ;
wire [1:0] c11 ;
wire [3:0] c8 ;
wire [1:0] c10 ;
wire [1:0] c9 ;
assign c8[2] = sctag_in[1] ;
assign c8[1] = sctag_in[0] ;
assign sctag_out[1] = c9[1] ;
assign sctag_out[0] = c9[0] ;
bw_clk_gclk_inv_r90_224x xc7_1_ (
.clkout (c7[1] ),
.clkin (c8[0] ) );
bw_clk_gclk_inv_r90_256x xc10a_0_ (
.clkout (c11[0] ),
.clkin (c12 ) );
bw_clk_gclk_inv_r90_224x xc7_2_ (
.clkout (c7[2] ),
.clkin (c8[1] ) );
bw_clk_gclk_inv_r90_192x xc8_0_ (
.clkout (c8[0] ),
.clkin (c9[0] ) );
bw_clk_gclk_inv_r90_256x xc10a_1_ (
.clkout (c11[1] ),
.clkin (c12 ) );
bw_clk_gclk_inv_r90_224x xc7_3_ (
.clkout (c7[3] ),
.clkin (c8[1] ) );
bw_clk_gclk_inv_r90_192x xc10b_0_ (
.clkout (c10[0] ),
.clkin (c11[0] ) );
bw_clk_gclk_inv_r90_224x xc7_4_ (
.clkout (c7[4] ),
.clkin (c8[2] ) );
bw_clk_gclk_inv_r90_224x xc9_0_ (
.clkout (c9[0] ),
.clkin (c10[0] ) );
bw_clk_gclk_inv_r90_192x xc10b_1_ (
.clkout (c10[1] ),
.clkin (c11[1] ) );
bw_clk_gclk_inv_r90_224x xc7_5_ (
.clkout (c7[5] ),
.clkin (c8[2] ) );
bw_clk_gclk_inv_r90_224x xc9_1_ (
.clkout (c9[1] ),
.clkin (c10[1] ) );
bw_clk_gclk_inv_r90_192x xc8_3_ (
.clkout (c8[3] ),
.clkin (c9[1] ) );
bw_clk_gclk_inv_r90_224x xc7_6_ (
.clkout (c7[6] ),
.clkin (c8[3] ) );
bw_clk_gclk_inv_r90_224x xc7_7_ (
.clkout (c7[7] ),
.clkin (c8[3] ) );
bw_clk_gclk_inv_r90_224x xc7_0_ (
.clkout (c7[0] ),
.clkin (c8[0] ) );
endmodule
module bw_clk_gl_vrt2(c7 ,sctag_out ,sctag_in ,c12 );
output [7:0] c7 ;
output [1:0] sctag_out ;
input [1:0] sctag_in ;
input c12 ;
wire [1:0] c11 ;
wire [3:0] c8 ;
wire [1:0] c10 ;
wire [1:0] c9 ;
assign sctag_out[1] = c9[1] ;
assign sctag_out[0] = c9[0] ;
assign c8[2] = sctag_in[1] ;
assign c8[1] = sctag_in[0] ;
bw_clk_gclk_inv_r90_224x xc7_1_ (
.clkout (c7[1] ),
.clkin (c8[0] ) );
bw_clk_gclk_inv_r90_256x xc10a_0_ (
.clkout (c11[0] ),
.clkin (c12 ) );
bw_clk_gclk_inv_r90_192x xc8_0_ (
.clkout (c8[0] ),
.clkin (c9[0] ) );
bw_clk_gclk_inv_r90_224x xc7_2_ (
.clkout (c7[2] ),
.clkin (c8[1] ) );
bw_clk_gclk_inv_r90_256x xc10a_1_ (
.clkout (c11[1] ),
.clkin (c12 ) );
bw_clk_gclk_inv_r90_224x xc7_3_ (
.clkout (c7[3] ),
.clkin (c8[1] ) );
bw_clk_gclk_inv_r90_192x xc10b_0_ (
.clkout (c10[0] ),
.clkin (c11[0] ) );
bw_clk_gclk_inv_r90_224x xc7_4_ (
.clkout (c7[4] ),
.clkin (c8[2] ) );
bw_clk_gclk_inv_r90_224x xc9_0_ (
.clkout (c9[0] ),
.clkin (c10[0] ) );
bw_clk_gclk_inv_r90_192x xc10b_1_ (
.clkout (c10[1] ),
.clkin (c11[1] ) );
bw_clk_gclk_inv_r90_192x xc8_3_ (
.clkout (c8[3] ),
.clkin (c9[1] ) );
bw_clk_gclk_inv_r90_224x xc7_5_ (
.clkout (c7[5] ),
.clkin (c8[2] ) );
bw_clk_gclk_inv_r90_224x xc9_1_ (
.clkout (c9[1] ),
.clkin (c10[1] ) );
bw_clk_gclk_inv_r90_224x xc7_6_ (
.clkout (c7[6] ),
.clkin (c8[3] ) );
bw_clk_gclk_inv_r90_224x xc7_7_ (
.clkout (c7[7] ),
.clkin (c8[3] ) );
bw_clk_gclk_inv_r90_224x xc7_0_ (
.clkout (c7[0] ),
.clkin (c8[0] ) );
endmodule
module bw_clk_gl_vrt3(c7 ,sctag_out ,sctag_in ,c12 );
output [7:0] c7 ;
output [1:0] sctag_out ;
input [1:0] sctag_in ;
input c12 ;
wire [1:0] c11 ;
wire [3:0] c8 ;
wire [1:0] c10 ;
wire [1:0] c9 ;
assign sctag_out[1] = c9[1] ;
assign sctag_out[0] = c9[0] ;
assign c8[2] = sctag_in[1] ;
assign c8[1] = sctag_in[0] ;
bw_clk_gclk_inv_r90_224x xc7_1_ (
.clkout (c7[1] ),
.clkin (c8[0] ) );
bw_clk_gclk_inv_r90_256x xc10a_0_ (
.clkout (c11[0] ),
.clkin (c12 ) );
bw_clk_gclk_inv_r90_224x xc7_2_ (
.clkout (c7[2] ),
.clkin (c8[1] ) );
bw_clk_gclk_inv_r90_192x xc8_0_ (
.clkout (c8[0] ),
.clkin (c9[0] ) );
bw_clk_gclk_inv_r90_256x xc10a_1_ (
.clkout (c11[1] ),
.clkin (c12 ) );
bw_clk_gclk_inv_r90_224x xc7_3_ (
.clkout (c7[3] ),
.clkin (c8[1] ) );
bw_clk_gclk_inv_r90_192x xc10b_0_ (
.clkout (c10[0] ),
.clkin (c11[0] ) );
bw_clk_gclk_inv_r90_224x xc9_0_ (
.clkout (c9[0] ),
.clkin (c10[0] ) );
bw_clk_gclk_inv_r90_224x xc7_4_ (
.clkout (c7[4] ),
.clkin (c8[2] ) );
bw_clk_gclk_inv_r90_192x xc10b_1_ (
.clkout (c10[1] ),
.clkin (c11[1] ) );
bw_clk_gclk_inv_r90_224x xc9_1_ (
.clkout (c9[1] ),
.clkin (c10[1] ) );
bw_clk_gclk_inv_r90_224x xc7_5_ (
.clkout (c7[5] ),
.clkin (c8[2] ) );
bw_clk_gclk_inv_r90_192x xc8_3_ (
.clkout (c8[3] ),
.clkin (c9[1] ) );
bw_clk_gclk_inv_r90_224x xc7_6_ (
.clkout (c7[6] ),
.clkin (c8[3] ) );
bw_clk_gclk_inv_r90_224x xc7_7_ (
.clkout (c7[7] ),
.clkin (c8[3] ) );
bw_clk_gclk_inv_r90_224x xc7_0_ (
.clkout (c7[0] ),
.clkin (c8[0] ) );
endmodule
module bw_clk_gl_vrt_all(jbus_c12 ,cmp_c12 ,cmp_sctag_out ,cmp_sctag_in
,ddr_sctag_in ,ddr_sctag_out ,jbus_sctag_in ,jbus_sctag_out ,
gclk_jbus ,gclk_cmp ,gclk_ddr ,ddr_c12 );
output [1:0] cmp_sctag_out ;
output [1:0] ddr_sctag_out ;
output [1:0] jbus_sctag_out ;
output [7:0] gclk_jbus ;
output [7:0] gclk_cmp ;
output [7:0] gclk_ddr ;
input [1:0] cmp_sctag_in ;
input [1:0] ddr_sctag_in ;
input [1:0] jbus_sctag_in ;
input jbus_c12 ;
input cmp_c12 ;
input ddr_c12 ;
bw_clk_gl_vrt1 xcmp (
.sctag_in ({cmp_sctag_in } ),
.sctag_out ({cmp_sctag_out } ),
.c7 ({gclk_cmp } ),
.c12 (cmp_c12 ) );
bw_clk_gl_vrt2 x0 (
.c7 ({gclk_ddr } ),
.sctag_out ({ddr_sctag_out } ),
.sctag_in ({ddr_sctag_in } ),
.c12 (ddr_c12 ) );
bw_clk_gl_vrt3 x1 (
.c7 ({gclk_jbus } ),
.sctag_out ({jbus_sctag_out } ),
.sctag_in ({jbus_sctag_in } ),
.c12 (jbus_c12 ) );
endmodule
|
`include "../../include/incparams.vh"
module tb_FIFOLOGIC;
reg clk, clk60, clk120;
wire tpulse;
reg EFB, TXE, FFA, RXF;
wire D1, WR, RB, D2, RD, WA;
FifoLogic_Gated uut
(
.clk (tpulse),
.FFA (FFA),
.RXF (RXF),
.TXE (TXE),
.EFB (EFB),
.RD (RD),
.WA (WA),
.RB (RB),
.WR (WR),
.D1 (D1),
.D2 (D2)
);
initial begin
$dumpfile("../../simulation/versim/waveGated.vcd");
$dumpvars(0,tb_FIFOLOGIC);
end
initial begin
clk = 0; clk60 = 0; clk120 = 0;
EFB = 0; TXE = 0; FFA = 0; RXF = 0;
#10
$display("\nSimulation Started...");
#100
simulate("U");
#5000
$display("\nSimulation Finished\n");
$finish;
end
task simulate;
input [7:0]cmd;
begin
{FFA,EFB,RXF,TXE} = 4'b0011;
#1000
if (cmd == "U") begin
{FFA,EFB,RXF,TXE} = 4'b1110;
writeUSB_UM(20, 630, 0);
{FFA,EFB,RXF,TXE} = 4'b1101;
readUSB_UM(40, 630, 0);
end
if (cmd == "F") begin
{FFA,EFB,RXF,TXE} = 4'b1110;
writeUSB_FM(20, 630, 0);
{FFA,EFB,RXF,TXE} = 4'b1101;
readUSB_FM(40, 630, 0);
end
{FFA,EFB,RXF,TXE} = 4'b0011;
end
endtask
task writeUSB_FM;
input [7:0] bytes;
input [32:0] t;
input [32:0] x;
reg [7:0] i;
begin
for (i=0; i<(bytes/2)+1; i=i+1) begin
@ (negedge WR);
{FFA,EFB,RXF,TXE} = 4'b0111;
#(t+x)
{FFA,EFB,RXF,TXE} = 4'b0110;
end
end
endtask
task readUSB_FM;
input [7:0] bytes;
input [32:0] t;
input [32:0] x;
reg [7:0] i;
begin
for (i=0; i<(bytes/2)+1; i=i+1) begin
@ (posedge RD);
{FFA,EFB,RXF,TXE} = 4'b1001;
#(t+x)
{FFA,EFB,RXF,TXE} = 4'b1011;
end
end
endtask
task writeUSB_UM;
input [7:0] bytes;
input [32:0] t;
input [32:0] x;
reg [7:0] i;
begin
for (i=0; i<(bytes); i=i+1) begin
@ (negedge WR);
{FFA,EFB,RXF,TXE} = 4'b1111;
#(t+x)
{FFA,EFB,RXF,TXE} = 4'b1110;
end
end
endtask
task readUSB_UM;
input [7:0] bytes;
input [32:0] t;
input [32:0] x;
reg [7:0] i;
begin
for (i=0; i<(bytes); i=i+1) begin
@ (posedge RD);
{FFA,EFB,RXF,TXE} = 4'b1111;
#(t+x)
{FFA,EFB,RXF,TXE} = 4'b1101;
end
end
endtask
always #`timeperiodby2 clk = ~clk;
always #300 clk60 = ~clk60;
always #600 clk120 = ~clk120;
assign tpulse = clk60 | clk120;
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:14:30 03/29/2014
// Design Name: regfile
// Module Name: D:/XilinxProject/CPU/regfile_test.v
// Project Name: CPU
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: regfile
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module regfile_test;
// Inputs
reg [4:0] rna;
reg [4:0] rnb;
reg [31:0] d;
reg [4:0] wn;
reg we;
reg clk;
reg clrn;
// Outputs
wire [31:0] qa;
wire [31:0] qb;
// Instantiate the Unit Under Test (UUT)
regfile uut (
.rna(rna),
.rnb(rnb),
.d(d),
.wn(wn),
.we(we),
.clk(clk),
.clrn(clrn),
.qa(qa),
.qb(qb)
);
initial begin
// Initialize Inputs
rna = 1;
rnb = 2;
d = 1;
wn = 1;
we = 1;
clk = 0;
clrn = 1;
// Wait 100 ns for global reset to finish
#100;
rna = 1;
rnb = 2;
d = 1;
wn = 1;
we = 1;
clk = ~clk;
#100;
rna = 1;
rnb = 2;
d = 1;
wn = 1;
we = 1;
clk = ~clk;
#100;
rna = 1;
rnb = 2;
d = 1;
wn = 1;
we = 0;
clk = ~clk;
// Add stimulus here
end
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_cpu_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
// GOLD VERSION
/*
*ALU Functions Included (in order coded below):
* SLL
* SRL
* ADD
* AND
* NOT
* OR
* XOR
* SUB
* PRM
* SLLI
* SRLI
* SRAI
* SRA
* mules
* mulos
* muleu
* mulou
*
*Other Functions:
* LD (NOP)
* WMV (ADD)
* WST (NOP)
*/
/**
* Reference:
* Nestoras Tzartzanis, EE 577B Verilog Example, Jan 25, 1996
* http://www-scf.usc.edu/~ee577/tutorial/verilog/alu.v
*/
/**
* Note that all instructions are 32-bits, and that Big-Endian
* byte and bit labeling is used. Hence, a[0] is the most
* significant bit, and a[31] is the least significant bit.
*
* Use of casex and casez may affect functionality, and produce
* larger and slower designs that omit the full_case directive
*
* Reference:
* Don Mills and Clifford E. Cummings, "RTL Coding Styles That
* Yield Simulation and Synthesis Mismatches", SNUG 1999
*
* ALU is a combinational logic block without clock signals
*/
`include "/home/scf-07/zhiyango/ee577b/projs/final/src/control.h"
// Behavioral model for the ALU
module shift (reg_A,reg_B,ctrl_ww,alu_op,result);
// Output signals...
// Result from copmputing an arithmetic or logical operation
output [0:127] result;
// Input signals
input [0:127] reg_A;
input [0:127] reg_B;
// Control signal bits - ww
input [0:1] ctrl_ww;
input [0:4] alu_op;
// Defining constants: parameter [name_of_constant] = value;
parameter max_128_bits = 128'hffffffffffffffffffffffffffffffff;
// Declare "reg" signals:
reg [0:127] result;
reg [0:127] p_pdt;
// Temporary reg variables for WW=8, for 8-bit multiplication
reg [0:15] p_pdt8a;
reg [0:15] p_pdt8a2;
reg [0:15] p_pdt8b;
reg [0:15] p_pdt8b2;
reg [0:15] p_pdt8c;
reg [0:15] p_pdt8c2;
reg [0:15] p_pdt8d;
reg [0:15] p_pdt8d2;
reg [0:15] p_pdt8e;
reg [0:15] p_pdt8e2;
reg [0:15] p_pdt8f;
reg [0:15] p_pdt8f2;
reg [0:15] p_pdt8g;
reg [0:15] p_pdt8g2;
reg [0:15] p_pdt8h;
reg [0:15] p_pdt8h2;
// Temporary reg variables for WW=16, for 16-bit multiplication
reg [0:31] p_pdt16a;
reg [0:31] p_pdt16a2;
reg [0:31] p_pdt16a3;
reg [0:31] p_pdt16b;
reg [0:31] p_pdt16b2;
reg [0:31] p_pdt16c;
reg [0:31] p_pdt16c2;
reg [0:31] p_pdt16d;
reg [0:31] p_pdt16d2;
integer sgn;
integer i;
integer j;
always @(reg_A or reg_B or ctrl_ww or alu_op)
begin
p_pdt=128'd0;
p_pdt8a=16'd0;
p_pdt8a2=16'd0;
p_pdt8b=16'd0;
p_pdt8b2=16'd0;
p_pdt8c=16'd0;
p_pdt8c2=16'd0;
p_pdt8d=16'd0;
p_pdt8d2=16'd0;
p_pdt8e=16'd0;
p_pdt8e2=16'd0;
p_pdt8f=16'd0;
p_pdt8f2=16'd0;
p_pdt8g=16'd0;
p_pdt8g2=16'd0;
p_pdt8h=16'd0;
p_pdt8h2=16'd0;
p_pdt16a=32'd0;
p_pdt16a2=32'd0;
p_pdt16b=32'd0;
p_pdt16b2=32'd0;
p_pdt16c=32'd0;
p_pdt16c2=32'd0;
p_pdt16d=32'd0;
p_pdt16d2=32'd0;
/**
* Based on the assigned arithmetic or logic instruction,
* carry out the appropriate function on the operands
*/
case(alu_op)
/**
* In computer science, a logical shift is a shift operator
* that shifts all the bits of its operand. Unlike an
* arithmetic shift, a logical shift does not preserve
* a number's sign bit or distinguish a number's exponent
* from its mantissa; every bit in the operand is simply
* moved a given number of bit positions, and the vacant
* bit-positions are filled in, generally with zeros
* (compare with a circular shift).
*
* SRL,SLL,Srli,sra,srai...
*/
// ================================================
// ======================================================
// SLL instruction << mv to LSB << bit 127
`aluwsll:
begin
case(ctrl_ww)
`w8: // aluwsll AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]<<reg_B[5:7];
result[8:15]<=reg_A[8:15]<<reg_B[13:15];
result[16:23]<=reg_A[16:23]<<reg_B[21:23];
result[24:31]<=reg_A[24:31]<<reg_B[29:31];
result[32:39]<=reg_A[32:39]<<reg_B[37:39];
result[40:47]<=reg_A[40:47]<<reg_B[45:47];
result[48:55]<=reg_A[48:55]<<reg_B[53:55];
result[56:63]<=reg_A[56:63]<<reg_B[61:63];
result[64:71]<=reg_A[64:71]<<reg_B[69:71];
result[72:79]<=reg_A[72:79]<<reg_B[77:79];
result[80:87]<=reg_A[80:87]<<reg_B[85:87];
result[88:95]<=reg_A[88:95]<<reg_B[93:95];
result[96:103]<=reg_A[96:103]<<reg_B[101:103];
result[104:111]<=reg_A[104:111]<<reg_B[109:111];
result[112:119]<=reg_A[112:119]<<reg_B[117:119];
result[120:127]<=reg_A[120:127]<<reg_B[125:127];
end
`w16: // aluwsll AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]<<reg_B[12:15];
result[16:31]<=reg_A[16:31]<<reg_B[28:31];
result[32:47]<=reg_A[32:47]<<reg_B[44:47];
result[48:63]<=reg_A[48:63]<<reg_B[60:63];
result[64:79]<=reg_A[64:79]<<reg_B[76:79];
result[80:95]<=reg_A[80:95]<<reg_B[92:95];
result[96:111]<=reg_A[96:111]<<reg_B[108:111];
result[112:127]<=reg_A[112:127]<<reg_B[124:127];
end
`w32: // aluwsll AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]<<reg_B[27:31];
result[32:63]<=reg_A[32:63]<<reg_B[59:63];
result[64:95]<=reg_A[64:95]<<reg_B[91:95];
result[96:127]<=reg_A[96:127]<<reg_B[123:127];
end
default: // aluwsll AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
/*
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
*/
// ======================================================
// SRL instruction >> mv to MSB >> bit 0
`aluwsrl:
begin
case(ctrl_ww)
`w8: // aluwsrl AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]>>reg_B[5:7];
result[8:15]<=reg_A[8:15]>>reg_B[13:15];
result[16:23]<=reg_A[16:23]>>reg_B[21:23];
result[24:31]<=reg_A[24:31]>>reg_B[29:31];
result[32:39]<=reg_A[32:39]>>reg_B[37:39];
result[40:47]<=reg_A[40:47]>>reg_B[45:47];
result[48:55]<=reg_A[48:55]>>reg_B[53:55];
result[56:63]<=reg_A[56:63]>>reg_B[61:63];
result[64:71]<=reg_A[64:71]>>reg_B[69:71];
result[72:79]<=reg_A[72:79]>>reg_B[77:79];
result[80:87]<=reg_A[80:87]>>reg_B[85:87];
result[88:95]<=reg_A[88:95]>>reg_B[93:95];
result[96:103]<=reg_A[96:103]>>reg_B[101:103];
result[104:111]<=reg_A[104:111]>>reg_B[109:111];
result[112:119]<=reg_A[112:119]>>reg_B[117:119];
result[120:127]<=reg_A[120:127]>>reg_B[125:127];
end
`w16: // aluwsrl AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]>>reg_B[12:15];
result[16:31]<=reg_A[16:31]>>reg_B[28:31];
result[32:47]<=reg_A[32:47]>>reg_B[44:47];
result[48:63]<=reg_A[48:63]>>reg_B[60:63];
result[64:79]<=reg_A[64:79]>>reg_B[76:79];
result[80:95]<=reg_A[80:95]>>reg_B[92:95];
result[96:111]<=reg_A[96:111]>>reg_B[108:111];
result[112:127]<=reg_A[112:127]>>reg_B[124:127];
end
`w32: // aluwsrl AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]>>reg_B[27:31];
result[32:63]<=reg_A[32:63]>>reg_B[59:63];
result[64:95]<=reg_A[64:95]>>reg_B[91:95];
result[96:127]<=reg_A[96:127]>>reg_B[123:127];
end
default: // aluwsrl AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
// ==============================================================
// SLLI instruction
`aluwslli:
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:127]<=reg_A[0:127];
end
3'd1:
begin
result[0:7]<={reg_A[1:7],{1'b0}};
result[8:15]<={reg_A[9:15],{1'b0}};
result[16:23]<={reg_A[17:23],{1'b0}};
result[24:31]<={reg_A[25:31],{1'b0}};
result[32:39]<={reg_A[33:39],{1'b0}};
result[40:47]<={reg_A[41:47],{1'b0}};
result[48:55]<={reg_A[49:55],{1'b0}};
result[56:63]<={reg_A[57:63],{1'b0}};
result[64:71]<={reg_A[65:71],{1'b0}};
result[72:79]<={reg_A[73:79],{1'b0}};
result[80:87]<={reg_A[81:87],{1'b0}};
result[88:95]<={reg_A[89:95],{1'b0}};
result[96:103]<={reg_A[97:103],{1'b0}};
result[104:111]<={reg_A[105:111],{1'b0}};
result[112:119]<={reg_A[113:119],{1'b0}};
result[120:127]<={reg_A[121:127],{1'b0}};
end
3'd2:
begin
result[0:7]<={reg_A[2:7],{2{1'b0}}};
result[8:15]<={reg_A[10:15],{2{1'b0}}};
result[16:23]<={reg_A[18:23],{2{1'b0}}};
result[24:31]<={reg_A[26:31],{2{1'b0}}};
result[32:39]<={reg_A[34:39],{2{1'b0}}};
result[40:47]<={reg_A[42:47],{2{1'b0}}};
result[48:55]<={reg_A[50:55],{2{1'b0}}};
result[56:63]<={reg_A[58:63],{2{1'b0}}};
result[64:71]<={reg_A[66:71],{2{1'b0}}};
result[72:79]<={reg_A[74:79],{2{1'b0}}};
result[80:87]<={reg_A[82:87],{2{1'b0}}};
result[88:95]<={reg_A[90:95],{2{1'b0}}};
result[96:103]<={reg_A[98:103],{2{1'b0}}};
result[104:111]<={reg_A[106:111],{2{1'b0}}};
result[112:119]<={reg_A[114:119],{2{1'b0}}};
result[120:127]<={reg_A[122:127],{2{1'b0}}};
end
3'd3:
begin
result[0:7]<={reg_A[3:7],{3{1'b0}}};
result[8:15]<={reg_A[11:15],{3{1'b0}}};
result[16:23]<={reg_A[19:23],{3{1'b0}}};
result[24:31]<={reg_A[27:31],{3{1'b0}}};
result[32:39]<={reg_A[35:39],{3{1'b0}}};
result[40:47]<={reg_A[43:47],{3{1'b0}}};
result[48:55]<={reg_A[51:55],{3{1'b0}}};
result[56:63]<={reg_A[59:63],{3{1'b0}}};
result[64:71]<={reg_A[67:71],{3{1'b0}}};
result[72:79]<={reg_A[75:79],{3{1'b0}}};
result[80:87]<={reg_A[83:87],{3{1'b0}}};
result[88:95]<={reg_A[91:95],{3{1'b0}}};
result[96:103]<={reg_A[99:103],{3{1'b0}}};
result[104:111]<={reg_A[107:111],{3{1'b0}}};
result[112:119]<={reg_A[115:119],{3{1'b0}}};
result[120:127]<={reg_A[123:127],{3{1'b0}}};
end
3'd4:
begin
result[0:7]<={reg_A[4:7],{4{1'b0}}};
result[8:15]<={reg_A[12:15],{4{1'b0}}};
result[16:23]<={reg_A[20:23],{4{1'b0}}};
result[24:31]<={reg_A[28:31],{4{1'b0}}};
result[32:39]<={reg_A[36:39],{4{1'b0}}};
result[40:47]<={reg_A[44:47],{4{1'b0}}};
result[48:55]<={reg_A[52:55],{4{1'b0}}};
result[56:63]<={reg_A[60:63],{4{1'b0}}};
result[64:71]<={reg_A[68:71],{4{1'b0}}};
result[72:79]<={reg_A[76:79],{4{1'b0}}};
result[80:87]<={reg_A[84:87],{4{1'b0}}};
result[88:95]<={reg_A[92:95],{4{1'b0}}};
result[96:103]<={reg_A[100:103],{4{1'b0}}};
result[104:111]<={reg_A[108:111],{4{1'b0}}};
result[112:119]<={reg_A[116:119],{4{1'b0}}};
result[120:127]<={reg_A[124:127],{4{1'b0}}};
end
3'd5:
begin
result[0:7]<={reg_A[5:7],{5{1'b0}}};
result[8:15]<={reg_A[13:15],{5{1'b0}}};
result[16:23]<={reg_A[21:23],{5{1'b0}}};
result[24:31]<={reg_A[29:31],{5{1'b0}}};
result[32:39]<={reg_A[37:39],{5{1'b0}}};
result[40:47]<={reg_A[45:47],{5{1'b0}}};
result[48:55]<={reg_A[53:55],{5{1'b0}}};
result[56:63]<={reg_A[61:63],{5{1'b0}}};
result[64:71]<={reg_A[69:71],{5{1'b0}}};
result[72:79]<={reg_A[77:79],{5{1'b0}}};
result[80:87]<={reg_A[85:87],{5{1'b0}}};
result[88:95]<={reg_A[93:95],{5{1'b0}}};
result[96:103]<={reg_A[101:103],{5{1'b0}}};
result[104:111]<={reg_A[109:111],{5{1'b0}}};
result[112:119]<={reg_A[117:119],{5{1'b0}}};
result[120:127]<={reg_A[125:127],{5{1'b0}}};
end
3'd6:
begin
result[0:7]<={reg_A[6:7],{6{1'b0}}};
result[8:15]<={reg_A[14:15],{6{1'b0}}};
result[16:23]<={reg_A[22:23],{6{1'b0}}};
result[24:31]<={reg_A[30:31],{6{1'b0}}};
result[32:39]<={reg_A[38:39],{6{1'b0}}};
result[40:47]<={reg_A[46:47],{6{1'b0}}};
result[48:55]<={reg_A[54:55],{6{1'b0}}};
result[56:63]<={reg_A[62:63],{6{1'b0}}};
result[64:71]<={reg_A[70:71],{6{1'b0}}};
result[72:79]<={reg_A[78:79],{6{1'b0}}};
result[80:87]<={reg_A[86:87],{6{1'b0}}};
result[88:95]<={reg_A[94:95],{6{1'b0}}};
result[96:103]<={reg_A[102:103],{6{1'b0}}};
result[104:111]<={reg_A[110:111],{6{1'b0}}};
result[112:119]<={reg_A[118:119],{6{1'b0}}};
result[120:127]<={reg_A[126:127],{6{1'b0}}};
end
3'd7:
begin
result[0:7]<={reg_A[7],{7{1'b0}}};
result[8:15]<={reg_A[15],{7{1'b0}}};
result[16:23]<={reg_A[23],{7{1'b0}}};
result[24:31]<={reg_A[31],{7{1'b0}}};
result[32:39]<={reg_A[39],{7{1'b0}}};
result[40:47]<={reg_A[47],{7{1'b0}}};
result[48:55]<={reg_A[55],{7{1'b0}}};
result[56:63]<={reg_A[63],{7{1'b0}}};
result[64:71]<={reg_A[71],{7{1'b0}}};
result[72:79]<={reg_A[79],{7{1'b0}}};
result[80:87]<={reg_A[87],{7{1'b0}}};
result[88:95]<={reg_A[95],{7{1'b0}}};
result[96:103]<={reg_A[103],{7{1'b0}}};
result[104:111]<={reg_A[111],{7{1'b0}}};
result[112:119]<={reg_A[119],{7{1'b0}}};
result[120:127]<={reg_A[127],{7{1'b0}}};
end
default:
begin
result<=128'b0;
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<={reg_A[1:15],{1'b0}};
result[16:31]<={reg_A[17:31],{1'b0}};
result[32:47]<={reg_A[33:47],{1'b0}};
result[48:63]<={reg_A[49:63],{1'b0}};
result[64:79]<={reg_A[65:79],{1'b0}};
result[80:95]<={reg_A[81:95],{1'b0}};
result[96:111]<={reg_A[97:111],{1'b0}};
result[112:127]<={reg_A[113:127],{1'b0}};
end
4'd2:
begin
result[0:15]<={reg_A[2:15],{2{1'b0}}};
result[16:31]<={reg_A[18:31],{2{1'b0}}};
result[32:47]<={reg_A[34:47],{2{1'b0}}};
result[48:63]<={reg_A[50:63],{2{1'b0}}};
result[64:79]<={reg_A[66:79],{2{1'b0}}};
result[80:95]<={reg_A[82:95],{2{1'b0}}};
result[96:111]<={reg_A[98:111],{2{1'b0}}};
result[112:127]<={reg_A[114:127],{2{1'b0}}};
end
4'd3:
begin
result[0:15]<={reg_A[3:15],{3{1'b0}}};
result[16:31]<={reg_A[19:31],{3{1'b0}}};
result[32:47]<={reg_A[35:47],{3{1'b0}}};
result[48:63]<={reg_A[51:63],{3{1'b0}}};
result[64:79]<={reg_A[67:79],{3{1'b0}}};
result[80:95]<={reg_A[83:95],{3{1'b0}}};
result[96:111]<={reg_A[99:111],{3{1'b0}}};
result[112:127]<={reg_A[115:127],{3{1'b0}}};
end
4'd4:
begin
result[0:15]<={reg_A[4:15],{4{1'b0}}};
result[16:31]<={reg_A[20:31],{4{1'b0}}};
result[32:47]<={reg_A[36:47],{4{1'b0}}};
result[48:63]<={reg_A[52:63],{4{1'b0}}};
result[64:79]<={reg_A[68:79],{4{1'b0}}};
result[80:95]<={reg_A[84:95],{4{1'b0}}};
result[96:111]<={reg_A[100:111],{4{1'b0}}};
result[112:127]<={reg_A[116:127],{4{1'b0}}};
end
4'd5:
begin
result[0:15]<={reg_A[5:15],{5{1'b0}}};
result[16:31]<={reg_A[21:31],{5{1'b0}}};
result[32:47]<={reg_A[37:47],{5{1'b0}}};
result[48:63]<={reg_A[52:63],{5{1'b0}}};
result[64:79]<={reg_A[69:79],{5{1'b0}}};
result[80:95]<={reg_A[85:95],{5{1'b0}}};
result[96:111]<={reg_A[101:111],{5{1'b0}}};
result[112:127]<={reg_A[117:127],{5{1'b0}}};
end
4'd6:
begin
result[0:15]<={reg_A[6:15],{6{1'b0}}};
result[16:31]<={reg_A[22:31],{6{1'b0}}};
result[32:47]<={reg_A[38:47],{6{1'b0}}};
result[48:63]<={reg_A[53:63],{6{1'b0}}};
result[64:79]<={reg_A[70:79],{6{1'b0}}};
result[80:95]<={reg_A[86:95],{6{1'b0}}};
result[96:111]<={reg_A[102:111],{6{1'b0}}};
result[112:127]<={reg_A[118:127],{6{1'b0}}};
end
4'd7:
begin
result[0:15]<={reg_A[7:15],{7{1'b0}}};
result[16:31]<={reg_A[23:31],{7{1'b0}}};
result[32:47]<={reg_A[39:47],{7{1'b0}}};
result[48:63]<={reg_A[54:63],{7{1'b0}}};
result[64:79]<={reg_A[71:79],{7{1'b0}}};
result[80:95]<={reg_A[87:95],{7{1'b0}}};
result[96:111]<={reg_A[103:111],{7{1'b0}}};
result[112:127]<={reg_A[119:127],{7{1'b0}}};
end
4'd8:
begin
result[0:15]<={reg_A[8:15],{8{1'b0}}};
result[16:31]<={reg_A[24:31],{8{1'b0}}};
result[32:47]<={reg_A[40:47],{8{1'b0}}};
result[48:63]<={reg_A[55:63],{8{1'b0}}};
result[64:79]<={reg_A[72:79],{8{1'b0}}};
result[80:95]<={reg_A[88:95],{8{1'b0}}};
result[96:111]<={reg_A[104:111],{8{1'b0}}};
result[112:127]<={reg_A[120:127],{8{1'b0}}};
end
4'd9:
begin
result[0:15]<={reg_A[9:15],{9{1'b0}}};
result[16:31]<={reg_A[25:31],{9{1'b0}}};
result[32:47]<={reg_A[41:47],{9{1'b0}}};
result[48:63]<={reg_A[56:63],{9{1'b0}}};
result[64:79]<={reg_A[73:79],{9{1'b0}}};
result[80:95]<={reg_A[89:95],{9{1'b0}}};
result[96:111]<={reg_A[105:111],{9{1'b0}}};
result[112:127]<={reg_A[121:127],{9{1'b0}}};
end
4'd10:
begin
result[0:15]<={reg_A[10:15],{10{1'b0}}};
result[16:31]<={reg_A[26:31],{10{1'b0}}};
result[32:47]<={reg_A[42:47],{10{1'b0}}};
result[48:63]<={reg_A[58:63],{10{1'b0}}};
result[64:79]<={reg_A[74:79],{10{1'b0}}};
result[80:95]<={reg_A[90:95],{10{1'b0}}};
result[96:111]<={reg_A[106:111],{10{1'b0}}};
result[112:127]<={reg_A[122:127],{10{1'b0}}};
end
4'd11:
begin
result[0:15]<={reg_A[11:15],{11{1'b0}}};
result[16:31]<={reg_A[27:31],{11{1'b0}}};
result[32:47]<={reg_A[43:47],{11{1'b0}}};
result[48:63]<={reg_A[59:63],{11{1'b0}}};
result[64:79]<={reg_A[75:79],{11{1'b0}}};
result[80:95]<={reg_A[91:95],{11{1'b0}}};
result[96:111]<={reg_A[107:111],{11{1'b0}}};
result[112:127]<={reg_A[123:127],{11{1'b0}}};
end
4'd12:
begin
result[0:15]<={reg_A[12:15],{12{1'b0}}};
result[16:31]<={reg_A[28:31],{12{1'b0}}};
result[32:47]<={reg_A[44:47],{12{1'b0}}};
result[48:63]<={reg_A[60:63],{12{1'b0}}};
result[64:79]<={reg_A[76:79],{12{1'b0}}};
result[80:95]<={reg_A[92:95],{12{1'b0}}};
result[96:111]<={reg_A[108:111],{12{1'b0}}};
result[112:127]<={reg_A[124:127],{12{1'b0}}};
end
4'd13:
begin
result[0:15]<={reg_A[13:15],{13{1'b0}}};
result[16:31]<={reg_A[29:31],{13{1'b0}}};
result[32:47]<={reg_A[45:47],{13{1'b0}}};
result[48:63]<={reg_A[61:63],{13{1'b0}}};
result[64:79]<={reg_A[77:79],{13{1'b0}}};
result[80:95]<={reg_A[93:95],{13{1'b0}}};
result[96:111]<={reg_A[109:111],{13{1'b0}}};
result[112:127]<={reg_A[125:127],{13{1'b0}}};
end
4'd14:
begin
result[0:15]<={reg_A[14:15],{14{1'b0}}};
result[16:31]<={reg_A[30:31],{14{1'b0}}};
result[32:47]<={reg_A[46:47],{14{1'b0}}};
result[48:63]<={reg_A[62:63],{14{1'b0}}};
result[64:79]<={reg_A[78:79],{14{1'b0}}};
result[80:95]<={reg_A[94:95],{14{1'b0}}};
result[96:111]<={reg_A[110:111],{14{1'b0}}};
result[112:127]<={reg_A[126:127],{14{1'b0}}};
end
4'd15:
begin
result[0:15]<={reg_A[15],{15{1'b0}}};
result[16:31]<={reg_A[31],{15{1'b0}}};
result[32:47]<={reg_A[47],{15{1'b0}}};
result[48:63]<={reg_A[63],{15{1'b0}}};
result[64:79]<={reg_A[79],{15{1'b0}}};
result[80:95]<={reg_A[95],{15{1'b0}}};
result[96:111]<={reg_A[111],{15{1'b0}}};
result[112:127]<={reg_A[127],{15{1'b0}}};
end
default:
begin
result<=128'b0;
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<={reg_A[1:31],{1'b0}};
result[32:63]<={reg_A[33:63],{1'b0}};
result[64:95]<={reg_A[65:95],{1'b0}};
result[96:127]<={reg_A[97:127],{1'b0}};
end
5'd2:
begin
result[0:31]<={reg_A[2:31],{2{1'b0}}};
result[32:63]<={reg_A[34:63],{2{1'b0}}};
result[64:95]<={reg_A[66:95],{2{1'b0}}};
result[96:127]<={reg_A[98:127],{2{1'b0}}};
end
5'd3:
begin
result[0:31]<={reg_A[3:31],{3{1'b0}}};
result[32:63]<={reg_A[35:63],{3{1'b0}}};
result[64:95]<={reg_A[67:95],{3{1'b0}}};
result[96:127]<={reg_A[99:127],{3{1'b0}}};
end
5'd4:
begin
result[0:31]<={reg_A[4:31],{4{1'b0}}};
result[32:63]<={reg_A[36:63],{4{1'b0}}};
result[64:95]<={reg_A[68:95],{4{1'b0}}};
result[96:127]<={reg_A[100:127],{4{1'b0}}};
end
5'd5:
begin
result[0:31]<={reg_A[5:31],{5{1'b0}}};
result[32:63]<={reg_A[37:63],{5{1'b0}}};
result[64:95]<={reg_A[69:95],{5{1'b0}}};
result[96:127]<={reg_A[101:127],{5{1'b0}}};
end
5'd6:
begin
result[0:31]<={reg_A[6:31],{6{1'b0}}};
result[32:63]<={reg_A[38:63],{6{1'b0}}};
result[64:95]<={reg_A[70:95],{6{1'b0}}};
result[96:127]<={reg_A[102:127],{6{1'b0}}};
end
5'd7:
begin
result[0:31]<={reg_A[7:31],{7{1'b0}}};
result[32:63]<={reg_A[39:63],{7{1'b0}}};
result[64:95]<={reg_A[71:95],{7{1'b0}}};
result[96:127]<={reg_A[103:127],{7{1'b0}}};
end
5'd8:
begin
result[0:31]<={reg_A[8:31],{8{1'b0}}};
result[32:63]<={reg_A[40:63],{8{1'b0}}};
result[64:95]<={reg_A[72:95],{8{1'b0}}};
result[96:127]<={reg_A[104:127],{8{1'b0}}};
end
5'd9:
begin
result[0:31]<={reg_A[9:31],{9{1'b0}}};
result[32:63]<={reg_A[41:63],{9{1'b0}}};
result[64:95]<={reg_A[73:95],{9{1'b0}}};
result[96:127]<={reg_A[105:127],{9{1'b0}}};
end
5'd10:
begin
result[0:31]<={reg_A[10:31],{10{1'b0}}};
result[32:63]<={reg_A[42:63],{10{1'b0}}};
result[64:95]<={reg_A[74:95],{10{1'b0}}};
result[96:127]<={reg_A[106:127],{10{1'b0}}};
end
5'd11:
begin
result[0:31]<={reg_A[11:31],{11{1'b0}}};
result[32:63]<={reg_A[43:63],{11{1'b0}}};
result[64:95]<={reg_A[75:95],{11{1'b0}}};
result[96:127]<={reg_A[107:127],{11{1'b0}}};
end
5'd12:
begin
result[0:31]<={reg_A[12:31],{12{1'b0}}};
result[32:63]<={reg_A[44:63],{12{1'b0}}};
result[64:95]<={reg_A[76:95],{12{1'b0}}};
result[96:127]<={reg_A[108:127],{12{1'b0}}};
end
5'd13:
begin
result[0:31]<={reg_A[13:31],{13{1'b0}}};
result[32:63]<={reg_A[45:63],{13{1'b0}}};
result[64:95]<={reg_A[77:95],{13{1'b0}}};
result[96:127]<={reg_A[109:127],{13{1'b0}}};
end
5'd14:
begin
result[0:31]<={reg_A[14:31],{14{1'b0}}};
result[32:63]<={reg_A[46:63],{14{1'b0}}};
result[64:95]<={reg_A[78:95],{14{1'b0}}};
result[96:127]<={reg_A[110:127],{14{1'b0}}};
end
5'd15:
begin
result[0:31]<={reg_A[15:31],{15{1'b0}}};
result[32:63]<={reg_A[47:63],{15{1'b0}}};
result[64:95]<={reg_A[79:95],{15{1'b0}}};
result[96:127]<={reg_A[111:127],{15{1'b0}}};
end
5'd16:
begin
result[0:31]<={reg_A[16:31],{16{1'b0}}};
result[32:63]<={reg_A[48:63],{16{1'b0}}};
result[64:95]<={reg_A[80:95],{16{1'b0}}};
result[96:127]<={reg_A[112:127],{16{1'b0}}};
end
5'd17:
begin
result[0:31]<={reg_A[17:31],{17{1'b0}}};
result[32:63]<={reg_A[49:63],{17{1'b0}}};
result[64:95]<={reg_A[81:95],{17{1'b0}}};
result[96:127]<={reg_A[113:127],{17{1'b0}}};
end
5'd18:
begin
result[0:31]<={reg_A[18:31],{18{1'b0}}};
result[32:63]<={reg_A[50:63],{18{1'b0}}};
result[64:95]<={reg_A[82:95],{18{1'b0}}};
result[96:127]<={reg_A[114:127],{18{1'b0}}};
end
5'd19:
begin
result[0:31]<={reg_A[19:31],{19{1'b0}}};
result[32:63]<={reg_A[51:63],{19{1'b0}}};
result[64:95]<={reg_A[83:95],{19{1'b0}}};
result[96:127]<={reg_A[115:127],{19{1'b0}}};
end
5'd20:
begin
result[0:31]<={reg_A[20:31],{20{1'b0}}};
result[32:63]<={reg_A[52:63],{20{1'b0}}};
result[64:95]<={reg_A[84:95],{20{1'b0}}};
result[96:127]<={reg_A[116:127],{20{1'b0}}};
end
5'd21:
begin
result[0:31]<={reg_A[21:31],{21{1'b0}}};
result[32:63]<={reg_A[53:63],{21{1'b0}}};
result[64:95]<={reg_A[85:95],{21{1'b0}}};
result[96:127]<={reg_A[117:127],{21{1'b0}}};
end
5'd22:
begin
result[0:31]<={reg_A[22:31],{22{1'b0}}};
result[32:63]<={reg_A[54:63],{22{1'b0}}};
result[64:95]<={reg_A[86:95],{22{1'b0}}};
result[96:127]<={reg_A[118:127],{22{1'b0}}};
end
5'd23:
begin
result[0:31]<={reg_A[23:31],{23{1'b0}}};
result[32:63]<={reg_A[55:63],{23{1'b0}}};
result[64:95]<={reg_A[87:95],{23{1'b0}}};
result[96:127]<={reg_A[119:127],{23{1'b0}}};
end
5'd24:
begin
result[0:31]<={reg_A[24:31],{24{1'b0}}};
result[32:63]<={reg_A[56:63],{24{1'b0}}};
result[64:95]<={reg_A[88:95],{24{1'b0}}};
result[96:127]<={reg_A[120:127],{24{1'b0}}};
end
5'd25:
begin
result[0:31]<={reg_A[25:31],{25{1'b0}}};
result[32:63]<={reg_A[57:63],{25{1'b0}}};
result[64:95]<={reg_A[89:95],{25{1'b0}}};
result[96:127]<={reg_A[121:127],{25{1'b0}}};
end
5'd26:
begin
result[0:31]<={reg_A[26:31],{26{1'b0}}};
result[32:63]<={reg_A[58:63],{26{1'b0}}};
result[64:95]<={reg_A[90:95],{26{1'b0}}};
result[96:127]<={reg_A[122:127],{26{1'b0}}};
end
5'd27:
begin
result[0:31]<={reg_A[27:31],{27{1'b0}}};
result[32:63]<={reg_A[59:63],{27{1'b0}}};
result[64:95]<={reg_A[91:95],{27{1'b0}}};
result[96:127]<={reg_A[123:127],{27{1'b0}}};
end
5'd28:
begin
result[0:31]<={reg_A[28:31],{28{1'b0}}};
result[32:63]<={reg_A[60:63],{28{1'b0}}};
result[64:95]<={reg_A[92:95],{28{1'b0}}};
result[96:127]<={reg_A[124:127],{28{1'b0}}};
end
5'd29:
begin
result[0:31]<={reg_A[29:31],{29{1'b0}}};
result[32:63]<={reg_A[61:63],{29{1'b0}}};
result[64:95]<={reg_A[93:95],{29{1'b0}}};
result[96:127]<={reg_A[125:127],{29{1'b0}}};
end
5'd30:
begin
result[0:31]<={reg_A[30:31],{30{1'b0}}};
result[32:63]<={reg_A[62:63],{30{1'b0}}};
result[64:95]<={reg_A[94:95],{30{1'b0}}};
result[96:127]<={reg_A[126:127],{30{1'b0}}};
end
5'd31:
begin
result[0:31]<={reg_A[31],{31{1'b0}}};
result[32:63]<={reg_A[63],{31{1'b0}}};
result[64:95]<={reg_A[95],{31{1'b0}}};
result[96:127]<={reg_A[127],{31{1'b0}}};
end
default:
begin
result<=128'b0;
end
endcase
end
default:
result<=128'b0;
endcase
end
// ==============================================================
// SRLI instruction
`aluwsrli:
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:127]<=reg_A[0:127];
end
3'd1:
begin
result[0:7]<={{1'b0},reg_A[0:6]};
result[8:15]<={{1'b0},reg_A[8:14]};
result[16:23]<={{1'b0},reg_A[16:22]};
result[24:31]<={{1'b0},reg_A[24:30]};
result[32:39]<={{1'b0},reg_A[32:38]};
result[40:47]<={{1'b0},reg_A[40:46]};
result[48:55]<={{1'b0},reg_A[48:54]};
result[56:63]<={{1'b0},reg_A[56:62]};
result[64:71]<={{1'b0},reg_A[64:70]};
result[72:79]<={{1'b0},reg_A[72:78]};
result[80:87]<={{1'b0},reg_A[80:86]};
result[88:95]<={{1'b0},reg_A[88:94]};
result[96:103]<={{1'b0},reg_A[96:102]};
result[104:111]<={{1'b0},reg_A[104:110]};
result[112:119]<={{1'b0},reg_A[112:118]};
result[120:127]<={{1'b0},reg_A[120:126]};
end
3'd2:
begin
result[0:7]<={{2{1'b0}},reg_A[0:5]};
result[8:15]<={{2{1'b0}},reg_A[8:13]};
result[16:23]<={{2{1'b0}},reg_A[16:21]};
result[24:31]<={{2{1'b0}},reg_A[24:29]};
result[32:39]<={{2{1'b0}},reg_A[32:37]};
result[40:47]<={{2{1'b0}},reg_A[40:45]};
result[48:55]<={{2{1'b0}},reg_A[48:53]};
result[56:63]<={{2{1'b0}},reg_A[56:61]};
result[64:71]<={{2{1'b0}},reg_A[64:69]};
result[72:79]<={{2{1'b0}},reg_A[72:77]};
result[80:87]<={{2{1'b0}},reg_A[80:85]};
result[88:95]<={{2{1'b0}},reg_A[88:93]};
result[96:103]<={{2{1'b0}},reg_A[96:101]};
result[104:111]<={{2{1'b0}},reg_A[104:109]};
result[112:119]<={{2{1'b0}},reg_A[112:117]};
result[120:127]<={{2{1'b0}},reg_A[120:125]};
end
3'd3:
begin
result[0:7]<={{3{1'b0}},reg_A[0:4]};
result[8:15]<={{3{1'b0}},reg_A[8:12]};
result[16:23]<={{3{1'b0}},reg_A[16:20]};
result[24:31]<={{3{1'b0}},reg_A[24:28]};
result[32:39]<={{3{1'b0}},reg_A[32:36]};
result[40:47]<={{3{1'b0}},reg_A[40:44]};
result[48:55]<={{3{1'b0}},reg_A[48:52]};
result[56:63]<={{3{1'b0}},reg_A[56:60]};
result[64:71]<={{3{1'b0}},reg_A[64:68]};
result[72:79]<={{3{1'b0}},reg_A[72:76]};
result[80:87]<={{3{1'b0}},reg_A[80:84]};
result[88:95]<={{3{1'b0}},reg_A[88:92]};
result[96:103]<={{3{1'b0}},reg_A[96:100]};
result[104:111]<={{3{1'b0}},reg_A[104:108]};
result[112:119]<={{3{1'b0}},reg_A[112:116]};
result[120:127]<={{3{1'b0}},reg_A[120:124]};
end
3'd4:
begin
result[0:7]<={{4{1'b0}},reg_A[0:3]};
result[8:15]<={{4{1'b0}},reg_A[8:11]};
result[16:23]<={{4{1'b0}},reg_A[16:19]};
result[24:31]<={{4{1'b0}},reg_A[24:27]};
result[32:39]<={{4{1'b0}},reg_A[32:35]};
result[40:47]<={{4{1'b0}},reg_A[40:43]};
result[48:55]<={{4{1'b0}},reg_A[48:51]};
result[56:63]<={{4{1'b0}},reg_A[56:69]};
result[64:71]<={{4{1'b0}},reg_A[64:67]};
result[72:79]<={{4{1'b0}},reg_A[72:75]};
result[80:87]<={{4{1'b0}},reg_A[80:83]};
result[88:95]<={{4{1'b0}},reg_A[88:91]};
result[96:103]<={{4{1'b0}},reg_A[96:99]};
result[104:111]<={{4{1'b0}},reg_A[104:107]};
result[112:119]<={{4{1'b0}},reg_A[112:115]};
result[120:127]<={{4{1'b0}},reg_A[120:123]};
end
3'd5:
begin
result[0:7]<={{5{1'b0}},reg_A[0:2]};
result[8:15]<={{5{1'b0}},reg_A[8:10]};
result[16:23]<={{5{1'b0}},reg_A[16:18]};
result[24:31]<={{5{1'b0}},reg_A[24:26]};
result[32:39]<={{5{1'b0}},reg_A[32:34]};
result[40:47]<={{5{1'b0}},reg_A[40:42]};
result[48:55]<={{5{1'b0}},reg_A[48:50]};
result[56:63]<={{5{1'b0}},reg_A[56:68]};
result[64:71]<={{5{1'b0}},reg_A[64:66]};
result[72:79]<={{5{1'b0}},reg_A[72:74]};
result[80:87]<={{5{1'b0}},reg_A[80:82]};
result[88:95]<={{5{1'b0}},reg_A[88:90]};
result[96:103]<={{5{1'b0}},reg_A[96:98]};
result[104:111]<={{5{1'b0}},reg_A[104:106]};
result[112:119]<={{5{1'b0}},reg_A[112:114]};
result[120:127]<={{5{1'b0}},reg_A[120:122]};
end
3'd6:
begin
result[0:7]<={{6{1'b0}},reg_A[0:1]};
result[8:15]<={{6{1'b0}},reg_A[8:9]};
result[16:23]<={{6{1'b0}},reg_A[16:17]};
result[24:31]<={{6{1'b0}},reg_A[24:25]};
result[32:39]<={{6{1'b0}},reg_A[32:33]};
result[40:47]<={{6{1'b0}},reg_A[40:41]};
result[48:55]<={{6{1'b0}},reg_A[48:49]};
result[56:63]<={{6{1'b0}},reg_A[56:67]};
result[64:71]<={{6{1'b0}},reg_A[64:65]};
result[72:79]<={{6{1'b0}},reg_A[72:73]};
result[80:87]<={{6{1'b0}},reg_A[80:81]};
result[88:95]<={{6{1'b0}},reg_A[88:89]};
result[96:103]<={{6{1'b0}},reg_A[96:97]};
result[104:111]<={{6{1'b0}},reg_A[104:105]};
result[112:119]<={{6{1'b0}},reg_A[112:113]};
result[120:127]<={{6{1'b0}},reg_A[120:121]};
end
3'd7:
begin
result[0:7]<={{7{1'b0}},reg_A[0]};
result[8:15]<={{7{1'b0}},reg_A[8]};
result[16:23]<={{7{1'b0}},reg_A[16]};
result[24:31]<={{7{1'b0}},reg_A[24]};
result[32:39]<={{7{1'b0}},reg_A[32]};
result[40:47]<={{7{1'b0}},reg_A[40]};
result[48:55]<={{7{1'b0}},reg_A[48]};
result[56:63]<={{7{1'b0}},reg_A[56]};
result[64:71]<={{7{1'b0}},reg_A[64]};
result[72:79]<={{7{1'b0}},reg_A[72]};
result[80:87]<={{7{1'b0}},reg_A[80]};
result[88:95]<={{7{1'b0}},reg_A[88]};
result[96:103]<={{7{1'b0}},reg_A[96]};
result[104:111]<={{7{1'b0}},reg_A[104]};
result[112:119]<={{7{1'b0}},reg_A[112]};
result[120:127]<={{7{1'b0}},reg_A[120]};
end
default:
begin
result<=128'b0;
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<={{1'b0},reg_A[0:14]};
result[16:31]<={{1'b0},reg_A[16:30]};
result[32:47]<={{1'b0},reg_A[32:46]};
result[48:63]<={{1'b0},reg_A[48:62]};
result[64:79]<={{1'b0},reg_A[64:78]};
result[80:95]<={{1'b0},reg_A[80:94]};
result[96:111]<={{1'b0},reg_A[96:110]};
result[112:127]<={{1'b0},reg_A[112:126]};
end
4'd2:
begin
result[0:15]<={{2{1'b0}},reg_A[0:13]};
result[16:31]<={{2{1'b0}},reg_A[16:29]};
result[32:47]<={{2{1'b0}},reg_A[32:45]};
result[48:63]<={{2{1'b0}},reg_A[48:61]};
result[64:79]<={{2{1'b0}},reg_A[64:77]};
result[80:95]<={{2{1'b0}},reg_A[80:93]};
result[96:111]<={{2{1'b0}},reg_A[96:109]};
result[112:127]<={{2{1'b0}},reg_A[112:125]};
end
4'd3:
begin
result[0:15]<={{3{1'b0}},reg_A[0:12]};
result[16:31]<={{3{1'b0}},reg_A[16:28]};
result[32:47]<={{3{1'b0}},reg_A[32:44]};
result[48:63]<={{3{1'b0}},reg_A[48:60]};
result[64:79]<={{3{1'b0}},reg_A[64:76]};
result[80:95]<={{3{1'b0}},reg_A[80:92]};
result[96:111]<={{3{1'b0}},reg_A[96:108]};
result[112:127]<={{3{1'b0}},reg_A[112:124]};
end
4'd4:
begin
result[0:15]<={{4{1'b0}},reg_A[0:11]};
result[16:31]<={{4{1'b0}},reg_A[16:27]};
result[32:47]<={{4{1'b0}},reg_A[32:43]};
result[48:63]<={{4{1'b0}},reg_A[48:59]};
result[64:79]<={{4{1'b0}},reg_A[64:75]};
result[80:95]<={{4{1'b0}},reg_A[80:91]};
result[96:111]<={{4{1'b0}},reg_A[96:107]};
result[112:127]<={{4{1'b0}},reg_A[112:123]};
end
4'd5:
begin
result[0:15]<={{5{1'b0}},reg_A[0:10]};
result[16:31]<={{5{1'b0}},reg_A[16:26]};
result[32:47]<={{5{1'b0}},reg_A[32:42]};
result[48:63]<={{5{1'b0}},reg_A[48:58]};
result[64:79]<={{5{1'b0}},reg_A[64:74]};
result[80:95]<={{5{1'b0}},reg_A[80:90]};
result[96:111]<={{5{1'b0}},reg_A[96:106]};
result[112:127]<={{5{1'b0}},reg_A[112:122]};
end
4'd6:
begin
result[0:15]<={{6{1'b0}},reg_A[0:9]};
result[16:31]<={{6{1'b0}},reg_A[16:25]};
result[32:47]<={{6{1'b0}},reg_A[32:41]};
result[48:63]<={{6{1'b0}},reg_A[48:57]};
result[64:79]<={{6{1'b0}},reg_A[64:73]};
result[80:95]<={{6{1'b0}},reg_A[80:89]};
result[96:111]<={{6{1'b0}},reg_A[96:105]};
result[112:127]<={{6{1'b0}},reg_A[112:121]};
end
4'd7:
begin
result[0:15]<={{7{1'b0}},reg_A[0:8]};
result[16:31]<={{7{1'b0}},reg_A[16:24]};
result[32:47]<={{7{1'b0}},reg_A[32:40]};
result[48:63]<={{7{1'b0}},reg_A[48:56]};
result[64:79]<={{7{1'b0}},reg_A[64:72]};
result[80:95]<={{7{1'b0}},reg_A[80:88]};
result[96:111]<={{7{1'b0}},reg_A[96:104]};
result[112:127]<={{7{1'b0}},reg_A[112:120]};
end
4'd8:
begin
result[0:15]<={{8{1'b0}},reg_A[0:7]};
result[16:31]<={{8{1'b0}},reg_A[16:23]};
result[32:47]<={{8{1'b0}},reg_A[32:39]};
result[48:63]<={{8{1'b0}},reg_A[48:55]};
result[64:79]<={{8{1'b0}},reg_A[64:71]};
result[80:95]<={{8{1'b0}},reg_A[80:87]};
result[96:111]<={{8{1'b0}},reg_A[96:103]};
result[112:127]<={{8{1'b0}},reg_A[112:119]};
end
4'd9:
begin
result[0:15]<={{9{1'b0}},reg_A[0:6]};
result[16:31]<={{9{1'b0}},reg_A[16:22]};
result[32:47]<={{9{1'b0}},reg_A[32:38]};
result[48:63]<={{9{1'b0}},reg_A[48:54]};
result[64:79]<={{9{1'b0}},reg_A[64:70]};
result[80:95]<={{9{1'b0}},reg_A[80:86]};
result[96:111]<={{9{1'b0}},reg_A[96:102]};
result[112:127]<={{9{1'b0}},reg_A[112:118]};
end
4'd10:
begin
result[0:15]<={{10{1'b0}},reg_A[0:5]};
result[16:31]<={{10{1'b0}},reg_A[16:21]};
result[32:47]<={{10{1'b0}},reg_A[32:37]};
result[48:63]<={{10{1'b0}},reg_A[48:53]};
result[64:79]<={{10{1'b0}},reg_A[64:69]};
result[80:95]<={{10{1'b0}},reg_A[80:85]};
result[96:111]<={{10{1'b0}},reg_A[96:101]};
result[112:127]<={{10{1'b0}},reg_A[112:117]};
end
4'd11:
begin
result[0:15]<={{11{1'b0}},reg_A[0:4]};
result[16:31]<={{11{1'b0}},reg_A[16:20]};
result[32:47]<={{11{1'b0}},reg_A[32:36]};
result[48:63]<={{11{1'b0}},reg_A[48:52]};
result[64:79]<={{11{1'b0}},reg_A[64:68]};
result[80:95]<={{11{1'b0}},reg_A[80:84]};
result[96:111]<={{11{1'b0}},reg_A[96:100]};
result[112:127]<={{11{1'b0}},reg_A[112:116]};
end
4'd12:
begin
result[0:15]<={{12{1'b0}},reg_A[0:3]};
result[16:31]<={{12{1'b0}},reg_A[16:19]};
result[32:47]<={{12{1'b0}},reg_A[32:35]};
result[48:63]<={{12{1'b0}},reg_A[48:51]};
result[64:79]<={{12{1'b0}},reg_A[64:67]};
result[80:95]<={{12{1'b0}},reg_A[80:83]};
result[96:111]<={{12{1'b0}},reg_A[96:99]};
result[112:127]<={{12{1'b0}},reg_A[112:115]};
end
4'd13:
begin
result[0:15]<={{13{1'b0}},reg_A[0:2]};
result[16:31]<={{13{1'b0}},reg_A[16:18]};
result[32:47]<={{13{1'b0}},reg_A[32:34]};
result[48:63]<={{13{1'b0}},reg_A[48:50]};
result[64:79]<={{13{1'b0}},reg_A[64:66]};
result[80:95]<={{13{1'b0}},reg_A[80:82]};
result[96:111]<={{13{1'b0}},reg_A[96:98]};
result[112:127]<={{13{1'b0}},reg_A[112:114]};
end
4'd14:
begin
result[0:15]<={{14{1'b0}},reg_A[0:1]};
result[16:31]<={{14{1'b0}},reg_A[16:17]};
result[32:47]<={{14{1'b0}},reg_A[32:33]};
result[48:63]<={{14{1'b0}},reg_A[48:49]};
result[64:79]<={{14{1'b0}},reg_A[64:65]};
result[80:95]<={{14{1'b0}},reg_A[80:81]};
result[96:111]<={{14{1'b0}},reg_A[96:97]};
result[112:127]<={{14{1'b0}},reg_A[112:113]};
end
4'd15:
begin
result[0:15]<={{15{1'b0}},reg_A[0]};
result[16:31]<={{15{1'b0}},reg_A[16]};
result[32:47]<={{15{1'b0}},reg_A[32]};
result[48:63]<={{15{1'b0}},reg_A[48]};
result[64:79]<={{15{1'b0}},reg_A[64]};
result[80:95]<={{15{1'b0}},reg_A[80]};
result[96:111]<={{15{1'b0}},reg_A[96]};
result[112:127]<={{15{1'b0}},reg_A[112]};
end
default:
begin
result<=128'b0;
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<={{1'b0},reg_A[0:30]};
result[32:63]<={{1'b0},reg_A[32:62]};
result[64:95]<={{1'b0},reg_A[64:94]};
result[96:127]<={{1'b0},reg_A[96:126]};
end
5'd2:
begin
result[0:31]<={{2{1'b0}},reg_A[0:29]};
result[32:63]<={{2{1'b0}},reg_A[32:61]};
result[64:95]<={{2{1'b0}},reg_A[64:93]};
result[96:127]<={{2{1'b0}},reg_A[96:125]};
end
5'd3:
begin
result[0:31]<={{3{1'b0}},reg_A[0:28]};
result[32:63]<={{3{1'b0}},reg_A[32:60]};
result[64:95]<={{3{1'b0}},reg_A[64:92]};
result[96:127]<={{3{1'b0}},reg_A[96:124]};
end
5'd4:
begin
result[0:31]<={{4{1'b0}},reg_A[0:27]};
result[32:63]<={{4{1'b0}},reg_A[32:59]};
result[64:95]<={{4{1'b0}},reg_A[64:91]};
result[96:127]<={{4{1'b0}},reg_A[96:123]};
end
5'd5:
begin
result[0:31]<={{5{1'b0}},reg_A[0:26]};
result[32:63]<={{5{1'b0}},reg_A[32:58]};
result[64:95]<={{5{1'b0}},reg_A[64:90]};
result[96:127]<={{5{1'b0}},reg_A[96:122]};
end
5'd6:
begin
result[0:31]<={{6{1'b0}},reg_A[0:25]};
result[32:63]<={{6{1'b0}},reg_A[32:57]};
result[64:95]<={{6{1'b0}},reg_A[64:89]};
result[96:127]<={{6{1'b0}},reg_A[96:121]};
end
5'd7:
begin
result[0:31]<={{7{1'b0}},reg_A[0:24]};
result[32:63]<={{7{1'b0}},reg_A[32:56]};
result[64:95]<={{7{1'b0}},reg_A[64:88]};
result[96:127]<={{7{1'b0}},reg_A[96:120]};
end
5'd8:
begin
result[0:31]<={{8{1'b0}},reg_A[0:23]};
result[32:63]<={{8{1'b0}},reg_A[32:55]};
result[64:95]<={{8{1'b0}},reg_A[64:87]};
result[96:127]<={{8{1'b0}},reg_A[96:119]};
end
5'd9:
begin
result[0:31]<={{9{1'b0}},reg_A[0:22]};
result[32:63]<={{9{1'b0}},reg_A[32:54]};
result[64:95]<={{9{1'b0}},reg_A[64:86]};
result[96:127]<={{9{1'b0}},reg_A[96:118]};
end
5'd10:
begin
result[0:31]<={{10{1'b0}},reg_A[0:21]};
result[32:63]<={{10{1'b0}},reg_A[32:53]};
result[64:95]<={{10{1'b0}},reg_A[64:85]};
result[96:127]<={{10{1'b0}},reg_A[96:117]};
end
5'd11:
begin
result[0:31]<={{11{1'b0}},reg_A[0:20]};
result[32:63]<={{11{1'b0}},reg_A[32:52]};
result[64:95]<={{11{1'b0}},reg_A[64:84]};
result[96:127]<={{11{1'b0}},reg_A[96:116]};
end
5'd12:
begin
result[0:31]<={{12{1'b0}},reg_A[0:19]};
result[32:63]<={{12{1'b0}},reg_A[32:51]};
result[64:95]<={{12{1'b0}},reg_A[64:83]};
result[96:127]<={{12{1'b0}},reg_A[96:115]};
end
5'd13:
begin
result[0:31]<={{13{1'b0}},reg_A[0:18]};
result[32:63]<={{13{1'b0}},reg_A[32:50]};
result[64:95]<={{13{1'b0}},reg_A[64:82]};
result[96:127]<={{13{1'b0}},reg_A[96:114]};
end
5'd14:
begin
result[0:31]<={{14{1'b0}},reg_A[0:17]};
result[32:63]<={{14{1'b0}},reg_A[32:49]};
result[64:95]<={{14{1'b0}},reg_A[64:81]};
result[96:127]<={{14{1'b0}},reg_A[96:113]};
end
5'd15:
begin
result[0:31]<={{15{1'b0}},reg_A[0:16]};
result[32:63]<={{15{1'b0}},reg_A[32:48]};
result[64:95]<={{15{1'b0}},reg_A[64:80]};
result[96:127]<={{15{1'b0}},reg_A[96:112]};
end
5'd16:
begin
result[0:31]<={{16{1'b0}},reg_A[0:15]};
result[32:63]<={{16{1'b0}},reg_A[32:47]};
result[64:95]<={{16{1'b0}},reg_A[64:79]};
result[96:127]<={{16{1'b0}},reg_A[96:111]};
end
5'd17:
begin
result[0:31]<={{17{1'b0}},reg_A[0:14]};
result[32:63]<={{17{1'b0}},reg_A[32:46]};
result[64:95]<={{17{1'b0}},reg_A[64:78]};
result[96:127]<={{17{1'b0}},reg_A[96:110]};
end
5'd18:
begin
result[0:31]<={{18{1'b0}},reg_A[0:13]};
result[32:63]<={{18{1'b0}},reg_A[32:45]};
result[64:95]<={{18{1'b0}},reg_A[64:77]};
result[96:127]<={{18{1'b0}},reg_A[96:109]};
end
5'd19:
begin
result[0:31]<={{19{1'b0}},reg_A[0:12]};
result[32:63]<={{19{1'b0}},reg_A[32:44]};
result[64:95]<={{19{1'b0}},reg_A[64:76]};
result[96:127]<={{19{1'b0}},reg_A[96:108]};
end
5'd20:
begin
result[0:31]<={{20{1'b0}},reg_A[0:11]};
result[32:63]<={{20{1'b0}},reg_A[32:43]};
result[64:95]<={{20{1'b0}},reg_A[64:75]};
result[96:127]<={{20{1'b0}},reg_A[96:107]};
end
5'd21:
begin
result[0:31]<={{21{1'b0}},reg_A[0:10]};
result[32:63]<={{21{1'b0}},reg_A[32:42]};
result[64:95]<={{21{1'b0}},reg_A[64:74]};
result[96:127]<={{21{1'b0}},reg_A[96:106]};
end
5'd22:
begin
result[0:31]<={{22{1'b0}},reg_A[0:9]};
result[32:63]<={{22{1'b0}},reg_A[32:41]};
result[64:95]<={{22{1'b0}},reg_A[64:73]};
result[96:127]<={{22{1'b0}},reg_A[96:105]};
end
5'd23:
begin
result[0:31]<={{23{1'b0}},reg_A[0:8]};
result[32:63]<={{23{1'b0}},reg_A[32:40]};
result[64:95]<={{23{1'b0}},reg_A[64:72]};
result[96:127]<={{23{1'b0}},reg_A[96:104]};
end
5'd24:
begin
result[0:31]<={{24{1'b0}},reg_A[0:7]};
result[32:63]<={{24{1'b0}},reg_A[32:39]};
result[64:95]<={{24{1'b0}},reg_A[64:71]};
result[96:127]<={{24{1'b0}},reg_A[96:103]};
end
5'd25:
begin
result[0:31]<={{25{1'b0}},reg_A[0:6]};
result[32:63]<={{25{1'b0}},reg_A[32:38]};
result[64:95]<={{25{1'b0}},reg_A[64:70]};
result[96:127]<={{25{1'b0}},reg_A[96:102]};
end
5'd26:
begin
result[0:31]<={{26{1'b0}},reg_A[0:5]};
result[32:63]<={{26{1'b0}},reg_A[32:37]};
result[64:95]<={{26{1'b0}},reg_A[64:69]};
result[96:127]<={{26{1'b0}},reg_A[96:101]};
end
5'd27:
begin
result[0:31]<={{27{1'b0}},reg_A[0:4]};
result[32:63]<={{27{1'b0}},reg_A[32:36]};
result[64:95]<={{27{1'b0}},reg_A[64:68]};
result[96:127]<={{27{1'b0}},reg_A[96:100]};
end
5'd28:
begin
result[0:31]<={{28{1'b0}},reg_A[0:3]};
result[32:63]<={{28{1'b0}},reg_A[32:35]};
result[64:95]<={{28{1'b0}},reg_A[64:67]};
result[96:127]<={{28{1'b0}},reg_A[96:99]};
end
5'd29:
begin
result[0:31]<={{29{1'b0}},reg_A[0:2]};
result[32:63]<={{29{1'b0}},reg_A[32:34]};
result[64:95]<={{29{1'b0}},reg_A[64:66]};
result[96:127]<={{29{1'b0}},reg_A[96:98]};
end
5'd30:
begin
result[0:31]<={{30{1'b0}},reg_A[0:1]};
result[32:63]<={{30{1'b0}},reg_A[32:33]};
result[64:95]<={{30{1'b0}},reg_A[64:65]};
result[96:127]<={{30{1'b0}},reg_A[96:97]};
end
5'd31:
begin
result[0:31]<={{31{1'b0}},reg_A[0]};
result[32:63]<={{31{1'b0}},reg_A[32]};
result[64:95]<={{31{1'b0}},reg_A[64]};
result[96:127]<={{31{1'b0}},reg_A[96]};
end
default:
begin
result<=128'b0;
end
endcase
end
default:
begin
result<=128'b0;
end
endcase
end
// ==============================================================
// SRAI instruction
`aluwsrai:
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:127]<=reg_A[0:127];
end
3'd1:
begin
result[0:7]<={{reg_A[0]},reg_A[0:6]};
result[8:15]<={{reg_A[8]},reg_A[8:14]};
result[16:23]<={{reg_A[16]},reg_A[16:22]};
result[24:31]<={{reg_A[24]},reg_A[24:30]};
result[32:39]<={{reg_A[32]},reg_A[32:38]};
result[40:47]<={{reg_A[40]},reg_A[40:46]};
result[48:55]<={{reg_A[48]},reg_A[48:54]};
result[56:63]<={{reg_A[56]},reg_A[56:62]};
result[64:71]<={{reg_A[64]},reg_A[64:70]};
result[72:79]<={{reg_A[72]},reg_A[72:78]};
result[80:87]<={{reg_A[80]},reg_A[80:86]};
result[88:95]<={{reg_A[88]},reg_A[88:94]};
result[96:103]<={{reg_A[96]},reg_A[96:102]};
result[104:111]<={{reg_A[104]},reg_A[104:110]};
result[112:119]<={{reg_A[112]},reg_A[112:118]};
result[120:127]<={{reg_A[120]},reg_A[120:126]};
end
3'd2:
begin
result[0:7]<={{2{reg_A[0]}},reg_A[0:5]};
result[8:15]<={{2{reg_A[8]}},reg_A[8:13]};
result[16:23]<={{2{reg_A[16]}},reg_A[16:21]};
result[24:31]<={{2{reg_A[24]}},reg_A[24:29]};
result[32:39]<={{2{reg_A[32]}},reg_A[32:37]};
result[40:47]<={{2{reg_A[40]}},reg_A[40:45]};
result[48:55]<={{2{reg_A[48]}},reg_A[48:53]};
result[56:63]<={{2{reg_A[56]}},reg_A[56:61]};
result[64:71]<={{2{reg_A[64]}},reg_A[64:69]};
result[72:79]<={{2{reg_A[72]}},reg_A[72:77]};
result[80:87]<={{2{reg_A[80]}},reg_A[80:85]};
result[88:95]<={{2{reg_A[88]}},reg_A[88:93]};
result[96:103]<={{2{reg_A[96]}},reg_A[96:101]};
result[104:111]<={{2{reg_A[104]}},reg_A[104:109]};
result[112:119]<={{2{reg_A[112]}},reg_A[112:117]};
result[120:127]<={{2{reg_A[120]}},reg_A[120:125]};
end
3'd3:
begin
result[0:7]<={{3{reg_A[0]}},reg_A[0:4]};
result[8:15]<={{3{reg_A[8]}},reg_A[8:12]};
result[16:23]<={{3{reg_A[16]}},reg_A[16:20]};
result[24:31]<={{3{reg_A[24]}},reg_A[24:28]};
result[32:39]<={{3{reg_A[32]}},reg_A[32:36]};
result[40:47]<={{3{reg_A[40]}},reg_A[40:44]};
result[48:55]<={{3{reg_A[48]}},reg_A[48:52]};
result[56:63]<={{3{reg_A[56]}},reg_A[56:60]};
result[64:71]<={{3{reg_A[64]}},reg_A[64:68]};
result[72:79]<={{3{reg_A[72]}},reg_A[72:76]};
result[80:87]<={{3{reg_A[80]}},reg_A[80:84]};
result[88:95]<={{3{reg_A[88]}},reg_A[88:92]};
result[96:103]<={{3{reg_A[96]}},reg_A[96:100]};
result[104:111]<={{3{reg_A[104]}},reg_A[104:108]};
result[112:119]<={{3{reg_A[112]}},reg_A[112:116]};
result[120:127]<={{3{reg_A[120]}},reg_A[120:124]};
end
3'd4:
begin
result[0:7]<={{4{reg_A[0]}},reg_A[0:3]};
result[8:15]<={{4{reg_A[8]}},reg_A[8:11]};
result[16:23]<={{4{reg_A[16]}},reg_A[16:19]};
result[24:31]<={{4{reg_A[24]}},reg_A[24:27]};
result[32:39]<={{4{reg_A[32]}},reg_A[32:35]};
result[40:47]<={{4{reg_A[40]}},reg_A[40:43]};
result[48:55]<={{4{reg_A[48]}},reg_A[48:51]};
result[56:63]<={{4{reg_A[56]}},reg_A[56:69]};
result[64:71]<={{4{reg_A[64]}},reg_A[64:67]};
result[72:79]<={{4{reg_A[72]}},reg_A[72:75]};
result[80:87]<={{4{reg_A[80]}},reg_A[80:83]};
result[88:95]<={{4{reg_A[88]}},reg_A[88:91]};
result[96:103]<={{4{reg_A[96]}},reg_A[96:99]};
result[104:111]<={{4{reg_A[104]}},reg_A[104:107]};
result[112:119]<={{4{reg_A[112]}},reg_A[112:115]};
result[120:127]<={{4{reg_A[120]}},reg_A[120:123]};
end
3'd5:
begin
result[0:7]<={{5{reg_A[0]}},reg_A[0:2]};
result[8:15]<={{5{reg_A[8]}},reg_A[8:10]};
result[16:23]<={{5{reg_A[16]}},reg_A[16:18]};
result[24:31]<={{5{reg_A[24]}},reg_A[24:26]};
result[32:39]<={{5{reg_A[32]}},reg_A[32:34]};
result[40:47]<={{5{reg_A[40]}},reg_A[40:42]};
result[48:55]<={{5{reg_A[48]}},reg_A[48:50]};
result[56:63]<={{5{reg_A[56]}},reg_A[56:68]};
result[64:71]<={{5{reg_A[64]}},reg_A[64:66]};
result[72:79]<={{5{reg_A[72]}},reg_A[72:74]};
result[80:87]<={{5{reg_A[80]}},reg_A[80:82]};
result[88:95]<={{5{reg_A[88]}},reg_A[88:90]};
result[96:103]<={{5{reg_A[96]}},reg_A[96:98]};
result[104:111]<={{5{reg_A[104]}},reg_A[104:106]};
result[112:119]<={{5{reg_A[112]}},reg_A[112:114]};
result[120:127]<={{5{reg_A[120]}},reg_A[120:122]};
end
3'd6:
begin
result[0:7]<={{6{reg_A[0]}},reg_A[0:1]};
result[8:15]<={{6{reg_A[8]}},reg_A[8:9]};
result[16:23]<={{6{reg_A[16]}},reg_A[16:17]};
result[24:31]<={{6{reg_A[24]}},reg_A[24:25]};
result[32:39]<={{6{reg_A[32]}},reg_A[32:33]};
result[40:47]<={{6{reg_A[40]}},reg_A[40:41]};
result[48:55]<={{6{reg_A[48]}},reg_A[48:49]};
result[56:63]<={{6{reg_A[56]}},reg_A[56:67]};
result[64:71]<={{6{reg_A[64]}},reg_A[64:65]};
result[72:79]<={{6{reg_A[72]}},reg_A[72:73]};
result[80:87]<={{6{reg_A[80]}},reg_A[80:81]};
result[88:95]<={{6{reg_A[88]}},reg_A[88:89]};
result[96:103]<={{6{reg_A[96]}},reg_A[96:97]};
result[104:111]<={{6{reg_A[104]}},reg_A[104:105]};
result[112:119]<={{6{reg_A[112]}},reg_A[112:113]};
result[120:127]<={{6{reg_A[120]}},reg_A[120:121]};
end
3'd7:
begin
result[0:7]<={{7{reg_A[0]}},reg_A[0]};
result[8:15]<={{7{reg_A[8]}},reg_A[8]};
result[16:23]<={{7{reg_A[16]}},reg_A[16]};
result[24:31]<={{7{reg_A[24]}},reg_A[24]};
result[32:39]<={{7{reg_A[32]}},reg_A[32]};
result[40:47]<={{7{reg_A[40]}},reg_A[40]};
result[48:55]<={{7{reg_A[48]}},reg_A[48]};
result[56:63]<={{7{reg_A[56]}},reg_A[56]};
result[64:71]<={{7{reg_A[64]}},reg_A[64]};
result[72:79]<={{7{reg_A[72]}},reg_A[72]};
result[80:87]<={{7{reg_A[80]}},reg_A[80]};
result[88:95]<={{7{reg_A[88]}},reg_A[88]};
result[96:103]<={{7{reg_A[96]}},reg_A[96]};
result[104:111]<={{7{reg_A[104]}},reg_A[104]};
result[112:119]<={{7{reg_A[112]}},reg_A[112]};
result[120:127]<={{7{reg_A[120]}},reg_A[120]};
end
default:
begin
result<=128'b0;
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<={{reg_A[0]},reg_A[0:14]};
result[16:31]<={{reg_A[16]},reg_A[16:30]};
result[32:47]<={{reg_A[32]},reg_A[32:46]};
result[48:63]<={{reg_A[48]},reg_A[48:62]};
result[64:79]<={{reg_A[64]},reg_A[64:78]};
result[80:95]<={{reg_A[80]},reg_A[80:94]};
result[96:111]<={{reg_A[96]},reg_A[96:110]};
result[112:127]<={{reg_A[112]},reg_A[112:126]};
end
4'd2:
begin
result[0:15]<={{2{reg_A[0]}},reg_A[0:13]};
result[16:31]<={{2{reg_A[16]}},reg_A[16:29]};
result[32:47]<={{2{reg_A[32]}},reg_A[32:45]};
result[48:63]<={{2{reg_A[48]}},reg_A[48:61]};
result[64:79]<={{2{reg_A[64]}},reg_A[64:77]};
result[80:95]<={{2{reg_A[80]}},reg_A[80:93]};
result[96:111]<={{2{reg_A[96]}},reg_A[96:109]};
result[112:127]<={{2{reg_A[112]}},reg_A[112:125]};
end
4'd3:
begin
result[0:15]<={{3{reg_A[0]}},reg_A[0:12]};
result[16:31]<={{3{reg_A[16]}},reg_A[16:28]};
result[32:47]<={{3{reg_A[32]}},reg_A[32:44]};
result[48:63]<={{3{reg_A[48]}},reg_A[48:60]};
result[64:79]<={{3{reg_A[64]}},reg_A[64:76]};
result[80:95]<={{3{reg_A[80]}},reg_A[80:92]};
result[96:111]<={{3{reg_A[96]}},reg_A[96:108]};
result[112:127]<={{3{reg_A[112]}},reg_A[112:124]};
end
4'd4:
begin
result[0:15]<={{4{reg_A[0]}},reg_A[0:11]};
result[16:31]<={{4{reg_A[8]}},reg_A[16:27]};
result[32:47]<={{4{reg_A[16]}},reg_A[32:43]};
result[48:63]<={{4{reg_A[32]}},reg_A[48:59]};
result[64:79]<={{4{reg_A[48]}},reg_A[64:75]};
result[80:95]<={{4{reg_A[64]}},reg_A[80:91]};
result[96:111]<={{4{reg_A[80]}},reg_A[96:107]};
result[112:127]<={{4{reg_A[112]}},reg_A[112:123]};
end
4'd5:
begin
result[0:15]<={{5{reg_A[0]}},reg_A[0:10]};
result[16:31]<={{5{reg_A[16]}},reg_A[16:26]};
result[32:47]<={{5{reg_A[32]}},reg_A[32:42]};
result[48:63]<={{5{reg_A[48]}},reg_A[48:58]};
result[64:79]<={{5{reg_A[64]}},reg_A[64:74]};
result[80:95]<={{5{reg_A[80]}},reg_A[80:90]};
result[96:111]<={{5{reg_A[96]}},reg_A[96:106]};
result[112:127]<={{5{reg_A[112]}},reg_A[112:122]};
end
4'd6:
begin
result[0:15]<={{6{reg_A[0]}},reg_A[0:9]};
result[16:31]<={{6{reg_A[16]}},reg_A[16:25]};
result[32:47]<={{6{reg_A[32]}},reg_A[32:41]};
result[48:63]<={{6{reg_A[48]}},reg_A[48:57]};
result[64:79]<={{6{reg_A[64]}},reg_A[64:73]};
result[80:95]<={{6{reg_A[80]}},reg_A[80:89]};
result[96:111]<={{6{reg_A[96]}},reg_A[96:105]};
result[112:127]<={{6{reg_A[112]}},reg_A[112:121]};
end
4'd7:
begin
result[0:15]<={{7{reg_A[0]}},reg_A[0:8]};
result[16:31]<={{7{reg_A[16]}},reg_A[16:24]};
result[32:47]<={{7{reg_A[32]}},reg_A[32:40]};
result[48:63]<={{7{reg_A[48]}},reg_A[48:56]};
result[64:79]<={{7{reg_A[64]}},reg_A[64:72]};
result[80:95]<={{7{reg_A[80]}},reg_A[80:88]};
result[96:111]<={{7{reg_A[96]}},reg_A[96:104]};
result[112:127]<={{7{reg_A[112]}},reg_A[112:120]};
end
4'd8:
begin
result[0:15]<={{8{reg_A[0]}},reg_A[0:7]};
result[16:31]<={{8{reg_A[16]}},reg_A[16:23]};
result[32:47]<={{8{reg_A[32]}},reg_A[32:39]};
result[48:63]<={{8{reg_A[48]}},reg_A[48:55]};
result[64:79]<={{8{reg_A[64]}},reg_A[64:71]};
result[80:95]<={{8{reg_A[80]}},reg_A[80:87]};
result[96:111]<={{8{reg_A[96]}},reg_A[96:103]};
result[112:127]<={{8{reg_A[112]}},reg_A[112:119]};
end
4'd9:
begin
result[0:15]<={{9{reg_A[0]}},reg_A[0:6]};
result[16:31]<={{9{reg_A[16]}},reg_A[16:22]};
result[32:47]<={{9{reg_A[32]}},reg_A[32:38]};
result[48:63]<={{9{reg_A[48]}},reg_A[48:54]};
result[64:79]<={{9{reg_A[64]}},reg_A[64:70]};
result[80:95]<={{9{reg_A[80]}},reg_A[80:86]};
result[96:111]<={{9{reg_A[96]}},reg_A[96:102]};
result[112:127]<={{9{reg_A[112]}},reg_A[112:118]};
end
4'd10:
begin
result[0:15]<={{10{reg_A[0]}},reg_A[0:5]};
result[16:31]<={{10{reg_A[16]}},reg_A[16:21]};
result[32:47]<={{10{reg_A[32]}},reg_A[32:37]};
result[48:63]<={{10{reg_A[48]}},reg_A[48:53]};
result[64:79]<={{10{reg_A[64]}},reg_A[64:69]};
result[80:95]<={{10{reg_A[80]}},reg_A[80:85]};
result[96:111]<={{10{reg_A[96]}},reg_A[96:101]};
result[112:127]<={{10{reg_A[112]}},reg_A[112:117]};
end
4'd11:
begin
result[0:15]<={{11{reg_A[0]}},reg_A[0:4]};
result[16:31]<={{11{reg_A[16]}},reg_A[16:20]};
result[32:47]<={{11{reg_A[32]}},reg_A[32:36]};
result[48:63]<={{11{reg_A[48]}},reg_A[48:52]};
result[64:79]<={{11{reg_A[64]}},reg_A[64:68]};
result[80:95]<={{11{reg_A[80]}},reg_A[80:84]};
result[96:111]<={{11{reg_A[96]}},reg_A[96:100]};
result[112:127]<={{11{reg_A[112]}},reg_A[112:116]};
end
4'd12:
begin
result[0:15]<={{12{reg_A[0]}},reg_A[0:3]};
result[16:31]<={{12{reg_A[16]}},reg_A[16:19]};
result[32:47]<={{12{reg_A[32]}},reg_A[32:35]};
result[48:63]<={{12{reg_A[48]}},reg_A[48:51]};
result[64:79]<={{12{reg_A[64]}},reg_A[64:67]};
result[80:95]<={{12{reg_A[80]}},reg_A[80:83]};
result[96:111]<={{12{reg_A[96]}},reg_A[96:99]};
result[112:127]<={{12{reg_A[112]}},reg_A[112:115]};
end
4'd13:
begin
result[0:15]<={{13{reg_A[0]}},reg_A[0:2]};
result[16:31]<={{13{reg_A[16]}},reg_A[16:18]};
result[32:47]<={{13{reg_A[32]}},reg_A[32:34]};
result[48:63]<={{13{reg_A[48]}},reg_A[48:50]};
result[64:79]<={{13{reg_A[64]}},reg_A[64:66]};
result[80:95]<={{13{reg_A[80]}},reg_A[80:82]};
result[96:111]<={{13{reg_A[96]}},reg_A[96:98]};
result[112:127]<={{13{reg_A[112]}},reg_A[112:114]};
end
4'd14:
begin
result[0:15]<={{14{reg_A[0]}},reg_A[0:1]};
result[16:31]<={{14{reg_A[16]}},reg_A[16:17]};
result[32:47]<={{14{reg_A[32]}},reg_A[32:33]};
result[48:63]<={{14{reg_A[48]}},reg_A[48:49]};
result[64:79]<={{14{reg_A[64]}},reg_A[64:65]};
result[80:95]<={{14{reg_A[80]}},reg_A[80:81]};
result[96:111]<={{14{reg_A[96]}},reg_A[96:97]};
result[112:127]<={{14{reg_A[112]}},reg_A[112:113]};
end
4'd15:
begin
result[0:15]<={{15{reg_A[0]}},reg_A[0]};
result[16:31]<={{15{reg_A[16]}},reg_A[16]};
result[32:47]<={{15{reg_A[32]}},reg_A[32]};
result[48:63]<={{15{reg_A[48]}},reg_A[48]};
result[64:79]<={{15{reg_A[64]}},reg_A[64]};
result[80:95]<={{15{reg_A[80]}},reg_A[80]};
result[96:111]<={{15{reg_A[96]}},reg_A[96]};
result[112:127]<={{15{reg_A[112]}},reg_A[112]};
end
default:
begin
result<=128'b0;
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<={{reg_A[0]},reg_A[0:30]};
result[32:63]<={{reg_A[32]},reg_A[32:62]};
result[64:95]<={{reg_A[64]},reg_A[64:94]};
result[96:127]<={{reg_A[96]},reg_A[96:126]};
end
5'd2:
begin
result[0:31]<={{2{reg_A[0]}},reg_A[0:29]};
result[32:63]<={{2{reg_A[32]}},reg_A[32:61]};
result[64:95]<={{2{reg_A[64]}},reg_A[64:93]};
result[96:127]<={{2{reg_A[96]}},reg_A[96:125]};
end
5'd3:
begin
result[0:31]<={{3{reg_A[0]}},reg_A[0:28]};
result[32:63]<={{3{reg_A[32]}},reg_A[32:60]};
result[64:95]<={{3{reg_A[64]}},reg_A[64:92]};
result[96:127]<={{3{reg_A[96]}},reg_A[96:124]};
end
5'd4:
begin
result[0:31]<={{4{reg_A[0]}},reg_A[0:27]};
result[32:63]<={{4{reg_A[32]}},reg_A[32:59]};
result[64:95]<={{4{reg_A[64]}},reg_A[64:91]};
result[96:127]<={{4{reg_A[96]}},reg_A[96:123]};
end
5'd5:
begin
result[0:31]<={{5{reg_A[0]}},reg_A[0:26]};
result[32:63]<={{5{reg_A[32]}},reg_A[32:58]};
result[64:95]<={{5{reg_A[64]}},reg_A[64:90]};
result[96:127]<={{5{reg_A[96]}},reg_A[96:122]};
end
5'd6:
begin
result[0:31]<={{6{reg_A[0]}},reg_A[0:25]};
result[32:63]<={{6{reg_A[32]}},reg_A[32:57]};
result[64:95]<={{6{reg_A[64]}},reg_A[64:89]};
result[96:127]<={{6{reg_A[96]}},reg_A[96:121]};
end
5'd7:
begin
result[0:31]<={{7{reg_A[0]}},reg_A[0:24]};
result[32:63]<={{7{reg_A[32]}},reg_A[32:56]};
result[64:95]<={{7{reg_A[64]}},reg_A[64:88]};
result[96:127]<={{7{reg_A[96]}},reg_A[96:120]};
end
5'd8:
begin
result[0:31]<={{8{reg_A[0]}},reg_A[0:23]};
result[32:63]<={{8{reg_A[32]}},reg_A[32:55]};
result[64:95]<={{8{reg_A[64]}},reg_A[64:87]};
result[96:127]<={{8{reg_A[96]}},reg_A[96:119]};
end
5'd9:
begin
result[0:31]<={{9{reg_A[0]}},reg_A[0:22]};
result[32:63]<={{9{reg_A[32]}},reg_A[32:54]};
result[64:95]<={{9{reg_A[64]}},reg_A[64:86]};
result[96:127]<={{9{reg_A[96]}},reg_A[96:118]};
end
5'd10:
begin
result[0:31]<={{10{reg_A[0]}},reg_A[0:21]};
result[32:63]<={{10{reg_A[32]}},reg_A[32:53]};
result[64:95]<={{10{reg_A[64]}},reg_A[64:85]};
result[96:127]<={{10{reg_A[96]}},reg_A[96:117]};
end
5'd11:
begin
result[0:31]<={{11{reg_A[0]}},reg_A[0:20]};
result[32:63]<={{11{reg_A[32]}},reg_A[32:52]};
result[64:95]<={{11{reg_A[64]}},reg_A[64:84]};
result[96:127]<={{11{reg_A[96]}},reg_A[96:116]};
end
5'd12:
begin
result[0:31]<={{12{reg_A[0]}},reg_A[0:19]};
result[32:63]<={{12{reg_A[32]}},reg_A[32:51]};
result[64:95]<={{12{reg_A[64]}},reg_A[64:83]};
result[96:127]<={{12{reg_A[96]}},reg_A[96:115]};
end
5'd13:
begin
result[0:31]<={{13{reg_A[0]}},reg_A[0:18]};
result[32:63]<={{13{reg_A[32]}},reg_A[32:50]};
result[64:95]<={{13{reg_A[64]}},reg_A[64:82]};
result[96:127]<={{13{reg_A[96]}},reg_A[96:114]};
end
5'd14:
begin
result[0:31]<={{14{reg_A[0]}},reg_A[0:17]};
result[32:63]<={{14{reg_A[32]}},reg_A[32:49]};
result[64:95]<={{14{reg_A[64]}},reg_A[64:81]};
result[96:127]<={{14{reg_A[96]}},reg_A[96:113]};
end
5'd15:
begin
result[0:31]<={{15{reg_A[0]}},reg_A[0:16]};
result[32:63]<={{15{reg_A[32]}},reg_A[32:48]};
result[64:95]<={{15{reg_A[64]}},reg_A[64:80]};
result[96:127]<={{15{reg_A[96]}},reg_A[96:112]};
end
5'd16:
begin
result[0:31]<={{16{reg_A[0]}},reg_A[0:15]};
result[32:63]<={{16{reg_A[32]}},reg_A[32:47]};
result[64:95]<={{16{reg_A[64]}},reg_A[64:79]};
result[96:127]<={{16{reg_A[96]}},reg_A[96:111]};
end
5'd17:
begin
result[0:31]<={{17{reg_A[0]}},reg_A[0:14]};
result[32:63]<={{17{reg_A[32]}},reg_A[32:46]};
result[64:95]<={{17{reg_A[64]}},reg_A[64:78]};
result[96:127]<={{17{reg_A[96]}},reg_A[96:110]};
end
5'd18:
begin
result[0:31]<={{18{reg_A[0]}},reg_A[0:13]};
result[32:63]<={{18{reg_A[32]}},reg_A[32:45]};
result[64:95]<={{18{reg_A[64]}},reg_A[64:77]};
result[96:127]<={{18{reg_A[96]}},reg_A[96:109]};
end
5'd19:
begin
result[0:31]<={{19{reg_A[0]}},reg_A[0:12]};
result[32:63]<={{19{reg_A[32]}},reg_A[32:44]};
result[64:95]<={{19{reg_A[64]}},reg_A[64:76]};
result[96:127]<={{19{reg_A[96]}},reg_A[96:108]};
end
5'd20:
begin
result[0:31]<={{20{reg_A[0]}},reg_A[0:11]};
result[32:63]<={{20{reg_A[32]}},reg_A[32:43]};
result[64:95]<={{20{reg_A[64]}},reg_A[64:75]};
result[96:127]<={{20{reg_A[96]}},reg_A[96:107]};
end
5'd21:
begin
result[0:31]<={{21{reg_A[0]}},reg_A[0:10]};
result[32:63]<={{21{reg_A[32]}},reg_A[32:42]};
result[64:95]<={{21{reg_A[64]}},reg_A[64:74]};
result[96:127]<={{21{reg_A[96]}},reg_A[96:106]};
end
5'd22:
begin
result[0:31]<={{22{reg_A[0]}},reg_A[0:9]};
result[32:63]<={{22{reg_A[32]}},reg_A[32:41]};
result[64:95]<={{22{reg_A[64]}},reg_A[64:73]};
result[96:127]<={{22{reg_A[96]}},reg_A[96:105]};
end
5'd23:
begin
result[0:31]<={{23{reg_A[0]}},reg_A[0:8]};
result[32:63]<={{23{reg_A[32]}},reg_A[32:40]};
result[64:95]<={{23{reg_A[64]}},reg_A[64:72]};
result[96:127]<={{23{reg_A[96]}},reg_A[96:104]};
end
5'd24:
begin
result[0:31]<={{24{reg_A[0]}},reg_A[0:7]};
result[32:63]<={{24{reg_A[32]}},reg_A[32:39]};
result[64:95]<={{24{reg_A[64]}},reg_A[64:71]};
result[96:127]<={{24{reg_A[96]}},reg_A[96:103]};
end
5'd25:
begin
result[0:31]<={{25{reg_A[0]}},reg_A[0:6]};
result[32:63]<={{25{reg_A[32]}},reg_A[32:38]};
result[64:95]<={{25{reg_A[64]}},reg_A[64:70]};
result[96:127]<={{25{reg_A[96]}},reg_A[96:102]};
end
5'd26:
begin
result[0:31]<={{26{reg_A[0]}},reg_A[0:5]};
result[32:63]<={{26{reg_A[32]}},reg_A[32:37]};
result[64:95]<={{26{reg_A[64]}},reg_A[64:69]};
result[96:127]<={{26{reg_A[96]}},reg_A[96:101]};
end
5'd27:
begin
result[0:31]<={{27{reg_A[0]}},reg_A[0:4]};
result[32:63]<={{27{reg_A[32]}},reg_A[32:36]};
result[64:95]<={{27{reg_A[64]}},reg_A[64:68]};
result[96:127]<={{27{reg_A[96]}},reg_A[96:100]};
end
5'd28:
begin
result[0:31]<={{28{reg_A[0]}},reg_A[0:3]};
result[32:63]<={{28{reg_A[32]}},reg_A[32:35]};
result[64:95]<={{28{reg_A[64]}},reg_A[64:67]};
result[96:127]<={{28{reg_A[96]}},reg_A[96:99]};
end
5'd29:
begin
result[0:31]<={{29{reg_A[0]}},reg_A[0:2]};
result[32:63]<={{29{reg_A[32]}},reg_A[32:34]};
result[64:95]<={{29{reg_A[64]}},reg_A[64:66]};
result[96:127]<={{29{reg_A[96]}},reg_A[96:98]};
end
5'd30:
begin
result[0:31]<={{30{reg_A[0]}},reg_A[0:1]};
result[32:63]<={{30{reg_A[32]}},reg_A[32:33]};
result[64:95]<={{30{reg_A[64]}},reg_A[64:65]};
result[96:127]<={{30{reg_A[96]}},reg_A[96:97]};
end
5'd31:
begin
result[0:31]<={{31{reg_A[0]}},reg_A[0]};
result[32:63]<={{31{reg_A[32]}},reg_A[32]};
result[64:95]<={{31{reg_A[64]}},reg_A[64]};
result[96:127]<={{31{reg_A[96]}},reg_A[96]};
end
default:
begin
result<=128'b0;
end
endcase
end
default:
begin
result<=128'b0;
end
endcase
end
// ==============================================================
// SRA instruction
`aluwsra:
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[5:7]) // byte 0
3'd0:
result[0:7]<=reg_A[0:7];
3'd1:
result[0:7]<={{1{reg_A[0]}},reg_A[0:6]};
3'd2:
result[0:7]<={{2{reg_A[0]}},reg_A[0:5]};
3'd3:
result[0:7]<={{3{reg_A[0]}},reg_A[0:4]};
3'd4:
result[0:7]<={{4{reg_A[0]}},reg_A[0:3]};
3'd5:
result[0:7]<={{5{reg_A[0]}},reg_A[0:2]};
3'd6:
result[0:7]<={{6{reg_A[0]}},reg_A[0:1]};
3'd7:
result[0:7]<={{7{reg_A[0]}},reg_A[0]};
default:
result[0:7]<=8'b0;
endcase
case(reg_B[13:15]) // byte 1
3'd0:
result[8:15]<=reg_A[8:15];
3'd1:
result[8:15]<={{1{reg_A[8]}},reg_A[8:14]};
3'd2:
result[8:15]<={{2{reg_A[8]}},reg_A[8:13]};
3'd3:
result[8:15]<={{3{reg_A[8]}},reg_A[8:12]};
3'd4:
result[8:15]<={{4{reg_A[8]}},reg_A[8:11]};
3'd5:
result[8:15]<={{5{reg_A[8]}},reg_A[8:10]};
3'd6:
result[8:15]<={{6{reg_A[8]}},reg_A[8:9]};
3'd7:
result[8:15]<={{7{reg_A[8]}},reg_A[8]};
default:
result[8:15]<=8'b0;
endcase
case(reg_B[21:23]) // byte 2
3'd0:
result[16:23]<=reg_A[16:23];
3'd1:
result[16:23]<={{1{reg_A[16]}},reg_A[16:22]};
3'd2:
result[16:23]<={{2{reg_A[16]}},reg_A[16:21]};
3'd3:
result[16:23]<={{3{reg_A[16]}},reg_A[16:20]};
3'd4:
result[16:23]<={{4{reg_A[16]}},reg_A[16:19]};
3'd5:
result[16:23]<={{5{reg_A[16]}},reg_A[16:18]};
3'd6:
result[16:23]<={{6{reg_A[16]}},reg_A[16:17]};
3'd7:
result[16:23]<={{7{reg_A[16]}},reg_A[16]};
default:
result[16:23]<=8'b0;
endcase
case(reg_B[29:31]) // byte 3
3'd0:
result[24:31]<=reg_A[24:31];
3'd1:
result[24:31]<={{1{reg_A[24]}},reg_A[24:30]};
3'd2:
result[24:31]<={{2{reg_A[24]}},reg_A[24:29]};
3'd3:
result[24:31]<={{3{reg_A[24]}},reg_A[24:28]};
3'd4:
result[24:31]<={{4{reg_A[24]}},reg_A[24:27]};
3'd5:
result[24:31]<={{5{reg_A[24]}},reg_A[24:26]};
3'd6:
result[24:31]<={{6{reg_A[24]}},reg_A[24:25]};
3'd7:
result[24:31]<={{7{reg_A[24]}},reg_A[24]};
default:
result[24:31]<=8'b0;
endcase
case(reg_B[37:39]) // byte 4
3'd0:
result[32:39]<=reg_A[32:39];
3'd1:
result[32:39]<={{1{reg_A[32]}},reg_A[32:38]};
3'd2:
result[32:39]<={{2{reg_A[32]}},reg_A[32:37]};
3'd3:
result[32:39]<={{3{reg_A[32]}},reg_A[32:36]};
3'd4:
result[32:39]<={{4{reg_A[32]}},reg_A[32:35]};
3'd5:
result[32:39]<={{5{reg_A[32]}},reg_A[32:34]};
3'd6:
result[32:39]<={{6{reg_A[32]}},reg_A[32:33]};
3'd7:
result[32:39]<={{7{reg_A[32]}},reg_A[32]};
default:
result[32:39]<=8'b0;
endcase
case(reg_B[45:47]) // byte 5
3'd0:
result[40:47]<=reg_A[40:47];
3'd1:
result[40:47]<={{1{reg_A[40]}},reg_A[40:46]};
3'd2:
result[40:47]<={{2{reg_A[40]}},reg_A[40:45]};
3'd3:
result[40:47]<={{3{reg_A[40]}},reg_A[40:44]};
3'd4:
result[40:47]<={{4{reg_A[40]}},reg_A[40:43]};
3'd5:
result[40:47]<={{5{reg_A[40]}},reg_A[40:42]};
3'd6:
result[40:47]<={{6{reg_A[40]}},reg_A[40:41]};
3'd7:
result[40:47]<={{7{reg_A[40]}},reg_A[40]};
default:
result[40:47]<=8'b0;
endcase
case(reg_B[53:55]) // byte 6
3'd0:
result[48:55]<=reg_A[48:55];
3'd1:
result[48:55]<={{1{reg_A[48]}},reg_A[48:54]};
3'd2:
result[48:55]<={{2{reg_A[48]}},reg_A[48:53]};
3'd3:
result[48:55]<={{3{reg_A[48]}},reg_A[48:52]};
3'd4:
result[48:55]<={{4{reg_A[48]}},reg_A[48:51]};
3'd5:
result[48:55]<={{5{reg_A[48]}},reg_A[48:50]};
3'd6:
result[48:55]<={{6{reg_A[48]}},reg_A[48:49]};
3'd7:
result[48:55]<={{7{reg_A[48]}},reg_A[48]};
default:
result[48:55]<=8'b0;
endcase
case(reg_B[61:63]) // byte 7
3'd0:
result[56:63]<=reg_A[56:63];
3'd1:
result[56:63]<={{1{reg_A[56]}},reg_A[56:62]};
3'd2:
result[56:63]<={{2{reg_A[56]}},reg_A[56:61]};
3'd3:
result[56:63]<={{3{reg_A[56]}},reg_A[56:60]};
3'd4:
result[56:63]<={{4{reg_A[56]}},reg_A[56:59]};
3'd5:
result[56:63]<={{5{reg_A[56]}},reg_A[56:58]};
3'd6:
result[56:63]<={{6{reg_A[56]}},reg_A[56:57]};
3'd7:
result[56:63]<={{7{reg_A[56]}},reg_A[56]};
default:
result[56:63]<=8'b0;
endcase
case(reg_B[69:71]) // byte 8
3'd0:
result[64:71]<=reg_A[64:71];
3'd1:
result[64:71]<={{1{reg_A[64]}},reg_A[64:70]};
3'd2:
result[64:71]<={{2{reg_A[64]}},reg_A[64:69]};
3'd3:
result[64:71]<={{3{reg_A[64]}},reg_A[64:68]};
3'd4:
result[64:71]<={{4{reg_A[64]}},reg_A[64:67]};
3'd5:
result[64:71]<={{5{reg_A[64]}},reg_A[64:66]};
3'd6:
result[64:71]<={{6{reg_A[64]}},reg_A[64:65]};
3'd7:
result[64:71]<={{7{reg_A[64]}},reg_A[64]};
default:
result[64:71]<=8'b0;
endcase
case(reg_B[77:79]) // byte 9
3'd0:
result[72:79]<=reg_A[72:79];
3'd1:
result[72:79]<={{1{reg_A[72]}},reg_A[72:78]};
3'd2:
result[72:79]<={{2{reg_A[72]}},reg_A[72:77]};
3'd3:
result[72:79]<={{3{reg_A[72]}},reg_A[72:76]};
3'd4:
result[72:79]<={{4{reg_A[72]}},reg_A[72:75]};
3'd5:
result[72:79]<={{5{reg_A[72]}},reg_A[72:74]};
3'd6:
result[72:79]<={{6{reg_A[72]}},reg_A[72:73]};
3'd7:
result[72:79]<={{7{reg_A[72]}},reg_A[72]};
default:
result[72:79]<=8'b0;
endcase
case(reg_B[85:87]) // byte 10
3'd0:
result[80:87]<=reg_A[80:87];
3'd1:
result[80:87]<={{1{reg_A[80]}},reg_A[80:86]};
3'd2:
result[80:87]<={{2{reg_A[80]}},reg_A[80:85]};
3'd3:
result[80:87]<={{3{reg_A[80]}},reg_A[80:84]};
3'd4:
result[80:87]<={{4{reg_A[80]}},reg_A[80:83]};
3'd5:
result[80:87]<={{5{reg_A[80]}},reg_A[80:82]};
3'd6:
result[80:87]<={{6{reg_A[80]}},reg_A[80:81]};
3'd7:
result[80:87]<={{7{reg_A[80]}},reg_A[80]};
default:
result[80:87]<=8'b0;
endcase
case(reg_B[93:95]) // byte 11
3'd0:
result[88:95]<=reg_A[88:95];
3'd1:
result[88:95]<={{1{reg_A[88]}},reg_A[88:94]};
3'd2:
result[88:95]<={{2{reg_A[88]}},reg_A[88:93]};
3'd3:
result[88:95]<={{3{reg_A[88]}},reg_A[88:92]};
3'd4:
result[88:95]<={{4{reg_A[88]}},reg_A[88:91]};
3'd5:
result[88:95]<={{5{reg_A[88]}},reg_A[88:90]};
3'd6:
result[88:95]<={{6{reg_A[88]}},reg_A[88:89]};
3'd7:
result[88:95]<={{7{reg_A[88]}},reg_A[88]};
default:
result[88:95]<=8'b0;
endcase
case(reg_B[101:103]) // byte 12
3'd0:
result[96:103]<=reg_A[96:103];
3'd1:
result[96:103]<={{1{reg_A[96]}},reg_A[96:102]};
3'd2:
result[96:103]<={{2{reg_A[96]}},reg_A[96:101]};
3'd3:
result[96:103]<={{3{reg_A[96]}},reg_A[96:100]};
3'd4:
result[96:103]<={{4{reg_A[96]}},reg_A[96:99]};
3'd5:
result[96:103]<={{5{reg_A[96]}},reg_A[96:98]};
3'd6:
result[96:103]<={{6{reg_A[96]}},reg_A[96:97]};
3'd7:
result[96:103]<={{7{reg_A[96]}},reg_A[96]};
default:
result[96:103]<=8'b0;
endcase
case(reg_B[109:111]) // byte 13
3'd0:
result[104:111]<=reg_A[104:111];
3'd1:
result[104:111]<={{1{reg_A[104]}},reg_A[104:110]};
3'd2:
result[104:111]<={{2{reg_A[104]}},reg_A[104:109]};
3'd3:
result[104:111]<={{3{reg_A[104]}},reg_A[104:108]};
3'd4:
result[104:111]<={{4{reg_A[104]}},reg_A[104:107]};
3'd5:
result[104:111]<={{5{reg_A[104]}},reg_A[104:106]};
3'd6:
result[104:111]<={{6{reg_A[104]}},reg_A[104:105]};
3'd7:
result[104:111]<={{7{reg_A[104]}},reg_A[104]};
default:
result[104:111]<=8'b0;
endcase
case(reg_B[117:119]) // byte 14
3'd0:
result[112:119]<=reg_A[112:119];
3'd1:
result[112:119]<={{1{reg_A[112]}},reg_A[112:118]};
3'd2:
result[112:119]<={{2{reg_A[112]}},reg_A[112:117]};
3'd3:
result[112:119]<={{3{reg_A[112]}},reg_A[112:116]};
3'd4:
result[112:119]<={{4{reg_A[112]}},reg_A[112:115]};
3'd5:
result[112:119]<={{5{reg_A[112]}},reg_A[112:114]};
3'd6:
result[112:119]<={{6{reg_A[112]}},reg_A[112:113]};
3'd7:
result[112:119]<={{7{reg_A[112]}},reg_A[112]};
default:
result[112:119]<=8'b0;
endcase
case(reg_B[125:127]) // byte 15
3'd0:
result[120:127]<=reg_A[120:127];
3'd1:
result[120:127]<={{1{reg_A[120]}},reg_A[120:126]};
3'd2:
result[120:127]<={{2{reg_A[120]}},reg_A[120:125]};
3'd3:
result[120:127]<={{3{reg_A[120]}},reg_A[120:124]};
3'd4:
result[120:127]<={{4{reg_A[120]}},reg_A[120:123]};
3'd5:
result[120:127]<={{5{reg_A[120]}},reg_A[120:122]};
3'd6:
result[120:127]<={{6{reg_A[120]}},reg_A[120:121]};
3'd7:
result[120:127]<={{7{reg_A[120]}},reg_A[120]};
default:
result[120:127]<=8'b0;
endcase
end
`w16:
begin
case(reg_B[12:15]) // word0
4'd0:
result[0:15]<=reg_A[0:15];
4'd1:
result[0:15]<={{1{reg_A[0]}},reg_A[0:14]};
4'd2:
result[0:15]<={{2{reg_A[0]}},reg_A[0:13]};
4'd3:
result[0:15]<={{3{reg_A[0]}},reg_A[0:12]};
4'd4:
result[0:15]<={{4{reg_A[0]}},reg_A[0:11]};
4'd5:
result[0:15]<={{5{reg_A[0]}},reg_A[0:10]};
4'd6:
result[0:15]<={{6{reg_A[0]}},reg_A[0:9]};
4'd7:
result[0:15]<={{7{reg_A[0]}},reg_A[0:8]};
4'd8:
result[0:15]<={{8{reg_A[0]}},reg_A[0:7]};
4'd9:
result[0:15]<={{9{reg_A[0]}},reg_A[0:6]};
4'd10:
result[0:15]<={{10{reg_A[0]}},reg_A[0:5]};
4'd11:
result[0:15]<={{11{reg_A[0]}},reg_A[0:4]};
4'd12:
result[0:15]<={{12{reg_A[0]}},reg_A[0:3]};
4'd13:
result[0:15]<={{13{reg_A[0]}},reg_A[0:2]};
4'd14:
result[0:15]<={{14{reg_A[0]}},reg_A[0:1]};
4'd15:
result[0:15]<={{15{reg_A[0]}},reg_A[0]};
default:
result[0:15]<=16'b0;
endcase
case(reg_B[28:31]) //word1
4'd0:
result[16:31]<=reg_A[16:31];
4'd1:
result[16:31]<={{1{reg_A[16]}},reg_A[16:30]};
4'd2:
result[16:31]<={{2{reg_A[16]}},reg_A[16:29]};
4'd3:
result[16:31]<={{3{reg_A[16]}},reg_A[16:28]};
4'd4:
result[16:31]<={{4{reg_A[16]}},reg_A[16:27]};
4'd5:
result[16:31]<={{5{reg_A[16]}},reg_A[16:26]};
4'd6:
result[16:31]<={{6{reg_A[16]}},reg_A[16:25]};
4'd7:
result[16:31]<={{7{reg_A[16]}},reg_A[16:24]};
4'd8:
result[16:31]<={{8{reg_A[16]}},reg_A[16:23]};
4'd9:
result[16:31]<={{9{reg_A[16]}},reg_A[16:22]};
4'd10:
result[16:31]<={{10{reg_A[16]}},reg_A[16:21]};
4'd11:
result[16:31]<={{11{reg_A[16]}},reg_A[16:20]};
4'd12:
result[16:31]<={{12{reg_A[16]}},reg_A[16:19]};
4'd13:
result[16:31]<={{13{reg_A[16]}},reg_A[16:18]};
4'd14:
result[16:31]<={{14{reg_A[16]}},reg_A[16:17]};
4'd15:
result[16:31]<={{15{reg_A[16]}},reg_A[16]};
default:
result[16:31]<=16'b0;
endcase
case(reg_B[44:47]) // word2
4'd0:
result[32:47]<=reg_A[32:47];
4'd1:
result[32:47]<={{1{reg_A[32]}},reg_A[32:46]};
4'd2:
result[32:47]<={{2{reg_A[32]}},reg_A[32:45]};
4'd3:
result[32:47]<={{3{reg_A[32]}},reg_A[32:44]};
4'd4:
result[32:47]<={{4{reg_A[32]}},reg_A[32:43]};
4'd5:
result[32:47]<={{5{reg_A[32]}},reg_A[32:42]};
4'd6:
result[32:47]<={{6{reg_A[32]}},reg_A[32:41]};
4'd7:
result[32:47]<={{7{reg_A[32]}},reg_A[32:40]};
4'd8:
result[32:47]<={{8{reg_A[32]}},reg_A[32:39]};
4'd9:
result[32:47]<={{9{reg_A[32]}},reg_A[32:38]};
4'd10:
result[32:47]<={{10{reg_A[32]}},reg_A[32:37]};
4'd11:
result[32:47]<={{11{reg_A[32]}},reg_A[32:36]};
4'd12:
result[32:47]<={{12{reg_A[32]}},reg_A[32:35]};
4'd13:
result[32:47]<={{13{reg_A[32]}},reg_A[32:34]};
4'd14:
result[32:47]<={{14{reg_A[32]}},reg_A[32:33]};
4'd15:
result[32:47]<={{15{reg_A[32]}},reg_A[32]};
endcase
case(reg_B[60:63]) // word3
4'd0:
result[48:63]<=reg_A[48:63];
4'd1:
result[48:63]<={{1{reg_A[48]}},reg_A[48:62]};
4'd2:
result[48:63]<={{2{reg_A[48]}},reg_A[48:61]};
4'd3:
result[48:63]<={{3{reg_A[48]}},reg_A[48:60]};
4'd4:
result[48:63]<={{4{reg_A[48]}},reg_A[48:59]};
4'd5:
result[48:63]<={{5{reg_A[48]}},reg_A[48:58]};
4'd6:
result[48:63]<={{6{reg_A[48]}},reg_A[48:57]};
4'd7:
result[48:63]<={{7{reg_A[48]}},reg_A[48:56]};
4'd8:
result[48:63]<={{8{reg_A[48]}},reg_A[48:55]};
4'd9:
result[48:63]<={{9{reg_A[48]}},reg_A[48:54]};
4'd10:
result[48:63]<={{10{reg_A[48]}},reg_A[48:53]};
4'd11:
result[48:63]<={{11{reg_A[48]}},reg_A[48:52]};
4'd12:
result[48:63]<={{12{reg_A[48]}},reg_A[48:51]};
4'd13:
result[48:63]<={{13{reg_A[48]}},reg_A[48:50]};
4'd14:
result[48:63]<={{14{reg_A[48]}},reg_A[48:49]};
4'd15:
result[48:63]<={{15{reg_A[48]}},reg_A[48]};
default:
result[48:63]<=16'b0;
endcase
case(reg_B[76:79]) // word4
4'd0:
result[64:79]<=reg_A[64:79];
4'd1:
result[64:79]<={{1{reg_A[64]}},reg_A[64:78]};
4'd2:
result[64:79]<={{2{reg_A[64]}},reg_A[64:77]};
4'd3:
result[64:79]<={{3{reg_A[64]}},reg_A[64:76]};
4'd4:
result[64:79]<={{4{reg_A[64]}},reg_A[64:75]};
4'd5:
result[64:79]<={{5{reg_A[64]}},reg_A[64:74]};
4'd6:
result[64:79]<={{6{reg_A[64]}},reg_A[64:73]};
4'd7:
result[64:79]<={{7{reg_A[64]}},reg_A[64:72]};
4'd8:
result[64:79]<={{8{reg_A[64]}},reg_A[64:71]};
4'd9:
result[64:79]<={{9{reg_A[64]}},reg_A[64:70]};
4'd10:
result[64:79]<={{10{reg_A[64]}},reg_A[64:69]};
4'd11:
result[64:79]<={{11{reg_A[64]}},reg_A[64:68]};
4'd12:
result[64:79]<={{12{reg_A[64]}},reg_A[64:67]};
4'd13:
result[64:79]<={{13{reg_A[64]}},reg_A[64:66]};
4'd14:
result[64:79]<={{14{reg_A[64]}},reg_A[64:65]};
4'd15:
result[64:79]<={{15{reg_A[64]}},reg_A[64]};
default:
result[64:79]<=16'b0;
endcase
case(reg_B[92:95]) // word5
4'd0:
result[80:95]<=reg_A[80:95];
4'd1:
result[80:95]<={{1{reg_A[80]}},reg_A[80:94]};
4'd2:
result[80:95]<={{2{reg_A[80]}},reg_A[80:93]};
4'd3:
result[80:95]<={{3{reg_A[80]}},reg_A[80:92]};
4'd4:
result[80:95]<={{4{reg_A[80]}},reg_A[80:91]};
4'd5:
result[80:95]<={{5{reg_A[80]}},reg_A[80:90]};
4'd6:
result[80:95]<={{6{reg_A[80]}},reg_A[80:89]};
4'd7:
result[80:95]<={{7{reg_A[80]}},reg_A[80:88]};
4'd8:
result[80:95]<={{8{reg_A[80]}},reg_A[80:87]};
4'd9:
result[80:95]<={{9{reg_A[80]}},reg_A[80:86]};
4'd10:
result[80:95]<={{10{reg_A[80]}},reg_A[80:85]};
4'd11:
result[80:95]<={{11{reg_A[80]}},reg_A[80:84]};
4'd12:
result[80:95]<={{12{reg_A[80]}},reg_A[80:83]};
4'd13:
result[80:95]<={{13{reg_A[80]}},reg_A[80:82]};
4'd14:
result[80:95]<={{14{reg_A[80]}},reg_A[80:81]};
4'd15:
result[80:95]<={{15{reg_A[80]}},reg_A[80]};
default:
result[80:95]<=16'b0;
endcase
case(reg_B[92:111]) // word6
4'd0:
result[96:111]<=reg_A[96:111];
4'd1:
result[96:111]<={{1{reg_A[96]}},reg_A[96:110]};
4'd2:
result[96:111]<={{2{reg_A[96]}},reg_A[96:109]};
4'd3:
result[96:111]<={{3{reg_A[96]}},reg_A[96:108]};
4'd4:
result[96:111]<={{4{reg_A[96]}},reg_A[96:107]};
4'd5:
result[96:111]<={{5{reg_A[96]}},reg_A[96:106]};
4'd6:
result[96:111]<={{6{reg_A[96]}},reg_A[96:105]};
4'd7:
result[96:111]<={{7{reg_A[96]}},reg_A[96:104]};
4'd8:
result[96:111]<={{8{reg_A[96]}},reg_A[96:103]};
4'd9:
result[96:111]<={{9{reg_A[96]}},reg_A[96:102]};
4'd10:
result[96:111]<={{10{reg_A[96]}},reg_A[96:101]};
4'd11:
result[96:111]<={{11{reg_A[96]}},reg_A[96:100]};
4'd12:
result[96:111]<={{12{reg_A[96]}},reg_A[96:99]};
4'd13:
result[96:111]<={{13{reg_A[96]}},reg_A[96:98]};
4'd14:
result[96:111]<={{14{reg_A[96]}},reg_A[96:97]};
4'd15:
result[96:111]<={{15{reg_A[96]}},reg_A[96]};
default:
result[96:111]<=16'b0;
endcase
case(reg_B[92:127]) // word7
4'd0:
result[112:127]<=reg_A[112:127];
4'd1:
result[112:127]<={{1{reg_A[112]}},reg_A[112:126]};
4'd2:
result[112:127]<={{2{reg_A[112]}},reg_A[112:125]};
4'd3:
result[112:127]<={{3{reg_A[112]}},reg_A[112:124]};
4'd4:
result[112:127]<={{4{reg_A[112]}},reg_A[112:123]};
4'd5:
result[112:127]<={{5{reg_A[112]}},reg_A[112:122]};
4'd6:
result[112:127]<={{6{reg_A[112]}},reg_A[112:121]};
4'd7:
result[112:127]<={{7{reg_A[112]}},reg_A[112:120]};
4'd8:
result[112:127]<={{8{reg_A[112]}},reg_A[112:119]};
4'd9:
result[112:127]<={{9{reg_A[112]}},reg_A[112:118]};
4'd10:
result[112:127]<={{10{reg_A[112]}},reg_A[112:117]};
4'd11:
result[112:127]<={{11{reg_A[112]}},reg_A[112:116]};
4'd12:
result[112:127]<={{12{reg_A[112]}},reg_A[112:115]};
4'd13:
result[112:127]<={{13{reg_A[112]}},reg_A[112:114]};
4'd14:
result[112:127]<={{14{reg_A[112]}},reg_A[112:113]};
4'd15:
result[112:127]<={{15{reg_A[112]}},reg_A[112]};
default:
result[112:127]<=16'b0;
endcase
end
`w32:
begin
case(reg_B[27:31])
5'd0:
result[0:31]<=reg_A[0:31];
5'd1:
result[0:31]<={{1{reg_A[0]}},reg_A[0:30]};
5'd2:
result[0:31]<={{2{reg_A[0]}},reg_A[0:29]};
5'd3:
result[0:31]<={{3{reg_A[0]}},reg_A[0:28]};
5'd4:
result[0:31]<={{4{reg_A[0]}},reg_A[0:27]};
5'd5:
result[0:31]<={{5{reg_A[0]}},reg_A[0:26]};
5'd6:
result[0:31]<={{6{reg_A[0]}},reg_A[0:25]};
5'd7:
result[0:31]<={{7{reg_A[0]}},reg_A[0:24]};
5'd8:
result[0:31]<={{8{reg_A[0]}},reg_A[0:23]};
5'd9:
result[0:31]<={{9{reg_A[0]}},reg_A[0:22]};
5'd10:
result[0:31]<={{10{reg_A[0]}},reg_A[0:21]};
5'd11:
result[0:31]<={{11{reg_A[0]}},reg_A[0:20]};
5'd12:
result[0:31]<={{12{reg_A[0]}},reg_A[0:19]};
5'd13:
result[0:31]<={{13{reg_A[0]}},reg_A[0:18]};
5'd14:
result[0:31]<={{14{reg_A[0]}},reg_A[0:17]};
5'd15:
result[0:31]<={{15{reg_A[0]}},reg_A[0:16]};
5'd16:
result[0:31]<={{16{reg_A[0]}},reg_A[0:15]};
5'd17:
result[0:31]<={{17{reg_A[0]}},reg_A[0:14]};
5'd18:
result[0:31]<={{18{reg_A[0]}},reg_A[0:13]};
5'd19:
result[0:31]<={{19{reg_A[0]}},reg_A[0:12]};
5'd20:
result[0:31]<={{20{reg_A[0]}},reg_A[0:11]};
5'd21:
result[0:31]<={{21{reg_A[0]}},reg_A[0:10]};
5'd22:
result[0:31]<={{22{reg_A[0]}},reg_A[0:9]};
5'd23:
result[0:31]<={{23{reg_A[0]}},reg_A[0:8]};
5'd24:
result[0:31]<={{24{reg_A[0]}},reg_A[0:7]};
5'd25:
result[0:31]<={{25{reg_A[0]}},reg_A[0:6]};
5'd26:
result[0:31]<={{26{reg_A[0]}},reg_A[0:5]};
5'd27:
result[0:31]<={{27{reg_A[0]}},reg_A[0:4]};
5'd28:
result[0:31]<={{28{reg_A[0]}},reg_A[0:3]};
5'd29:
result[0:31]<={{29{reg_A[0]}},reg_A[0:2]};
5'd30:
result[0:31]<={{30{reg_A[0]}},reg_A[0:1]};
5'd31:
result[0:31]<={{31{reg_A[0]}},reg_A[0]};
default:
result[0:31]<=32'b0;
endcase
case(reg_B[59:63])
5'd0:
result[32:63]<=reg_A[32:63];
5'd1:
result[32:63]<={{1{reg_A[32]}},reg_A[32:62]};
5'd2:
result[32:63]<={{2{reg_A[32]}},reg_A[32:61]};
5'd3:
result[32:63]<={{3{reg_A[32]}},reg_A[32:60]};
5'd4:
result[32:63]<={{4{reg_A[32]}},reg_A[32:59]};
5'd5:
result[32:63]<={{5{reg_A[32]}},reg_A[32:58]};
5'd6:
result[32:63]<={{6{reg_A[32]}},reg_A[32:57]};
5'd7:
result[32:63]<={{7{reg_A[32]}},reg_A[32:56]};
5'd8:
result[32:63]<={{8{reg_A[32]}},reg_A[32:55]};
5'd9:
result[32:63]<={{9{reg_A[32]}},reg_A[32:54]};
5'd10:
result[32:63]<={{10{reg_A[32]}},reg_A[32:53]};
5'd11:
result[32:63]<={{11{reg_A[32]}},reg_A[32:52]};
5'd12:
result[32:63]<={{12{reg_A[32]}},reg_A[32:51]};
5'd13:
result[32:63]<={{13{reg_A[32]}},reg_A[32:50]};
5'd14:
result[32:63]<={{14{reg_A[32]}},reg_A[32:49]};
5'd15:
result[32:63]<={{15{reg_A[32]}},reg_A[32:48]};
5'd16:
result[32:63]<={{16{reg_A[32]}},reg_A[32:47]};
5'd17:
result[32:63]<={{17{reg_A[32]}},reg_A[32:46]};
5'd18:
result[32:63]<={{18{reg_A[32]}},reg_A[32:45]};
5'd19:
result[32:63]<={{19{reg_A[32]}},reg_A[32:44]};
5'd20:
result[32:63]<={{20{reg_A[32]}},reg_A[32:43]};
5'd21:
result[32:63]<={{21{reg_A[32]}},reg_A[32:42]};
5'd22:
result[32:63]<={{22{reg_A[32]}},reg_A[32:41]};
5'd23:
result[32:63]<={{23{reg_A[32]}},reg_A[32:40]};
5'd24:
result[32:63]<={{24{reg_A[32]}},reg_A[32:39]};
5'd25:
result[32:63]<={{25{reg_A[32]}},reg_A[32:38]};
5'd26:
result[32:63]<={{26{reg_A[32]}},reg_A[32:37]};
5'd27:
result[32:63]<={{27{reg_A[32]}},reg_A[32:36]};
5'd28:
result[32:63]<={{28{reg_A[32]}},reg_A[32:35]};
5'd29:
result[32:63]<={{29{reg_A[32]}},reg_A[32:34]};
5'd30:
result[32:63]<={{30{reg_A[32]}},reg_A[32:33]};
5'd31:
result[32:63]<={{31{reg_A[32]}},reg_A[32]};
default:
result[32:63]<=32'b0;
endcase
case(reg_B[91:95])
5'd0:
result[64:95]<=reg_A[64:95];
5'd1:
result[64:95]<={{1{reg_A[64]}},reg_A[64:94]};
5'd2:
result[64:95]<={{2{reg_A[64]}},reg_A[64:93]};
5'd3:
result[64:95]<={{3{reg_A[64]}},reg_A[64:92]};
5'd4:
result[64:95]<={{4{reg_A[64]}},reg_A[64:91]};
5'd5:
result[64:95]<={{5{reg_A[64]}},reg_A[64:90]};
5'd6:
result[64:95]<={{6{reg_A[64]}},reg_A[64:89]};
5'd7:
result[64:95]<={{7{reg_A[64]}},reg_A[64:88]};
5'd8:
result[64:95]<={{8{reg_A[64]}},reg_A[64:87]};
5'd9:
result[64:95]<={{9{reg_A[64]}},reg_A[64:86]};
5'd10:
result[64:95]<={{10{reg_A[64]}},reg_A[64:85]};
5'd11:
result[64:95]<={{11{reg_A[64]}},reg_A[64:84]};
5'd12:
result[64:95]<={{12{reg_A[64]}},reg_A[64:83]};
5'd13:
result[64:95]<={{13{reg_A[64]}},reg_A[64:82]};
5'd14:
result[64:95]<={{14{reg_A[64]}},reg_A[64:81]};
5'd15:
result[64:95]<={{15{reg_A[64]}},reg_A[64:80]};
5'd16:
result[64:95]<={{16{reg_A[64]}},reg_A[64:79]};
5'd17:
result[64:95]<={{17{reg_A[64]}},reg_A[64:78]};
5'd18:
result[64:95]<={{18{reg_A[64]}},reg_A[64:77]};
5'd19:
result[64:95]<={{19{reg_A[64]}},reg_A[64:76]};
5'd20:
result[64:95]<={{20{reg_A[64]}},reg_A[64:75]};
5'd21:
result[64:95]<={{21{reg_A[64]}},reg_A[64:74]};
5'd22:
result[64:95]<={{22{reg_A[64]}},reg_A[64:73]};
5'd23:
result[64:95]<={{23{reg_A[64]}},reg_A[64:72]};
5'd24:
result[64:95]<={{24{reg_A[64]}},reg_A[64:71]};
5'd25:
result[64:95]<={{25{reg_A[64]}},reg_A[64:70]};
5'd26:
result[64:95]<={{26{reg_A[64]}},reg_A[64:69]};
5'd27:
result[64:95]<={{27{reg_A[64]}},reg_A[64:68]};
5'd28:
result[64:95]<={{28{reg_A[64]}},reg_A[64:67]};
5'd29:
result[64:95]<={{29{reg_A[64]}},reg_A[64:66]};
5'd30:
result[64:95]<={{30{reg_A[64]}},reg_A[64:65]};
5'd31:
result[64:95]<={{31{reg_A[64]}},reg_A[64]};
default:
result[64:95]<=32'b0;
endcase
case(reg_B[123:127])
5'd0:
result[96:127]<=reg_A[96:127];
5'd1:
result[96:127]<={{1{reg_A[96]}},reg_A[96:126]};
5'd2:
result[96:127]<={{2{reg_A[96]}},reg_A[96:125]};
5'd3:
result[96:127]<={{3{reg_A[96]}},reg_A[96:124]};
5'd4:
result[96:127]<={{4{reg_A[96]}},reg_A[96:123]};
5'd5:
result[96:127]<={{5{reg_A[96]}},reg_A[96:122]};
5'd6:
result[96:127]<={{6{reg_A[96]}},reg_A[96:121]};
5'd7:
result[96:127]<={{7{reg_A[96]}},reg_A[96:120]};
5'd8:
result[96:127]<={{8{reg_A[96]}},reg_A[96:119]};
5'd9:
result[96:127]<={{9{reg_A[96]}},reg_A[96:118]};
5'd10:
result[96:127]<={{10{reg_A[96]}},reg_A[96:117]};
5'd11:
result[96:127]<={{11{reg_A[96]}},reg_A[96:116]};
5'd12:
result[96:127]<={{12{reg_A[96]}},reg_A[96:115]};
5'd13:
result[96:127]<={{13{reg_A[96]}},reg_A[96:114]};
5'd14:
result[96:127]<={{14{reg_A[96]}},reg_A[96:113]};
5'd15:
result[96:127]<={{15{reg_A[96]}},reg_A[96:112]};
5'd16:
result[96:127]<={{16{reg_A[96]}},reg_A[96:111]};
5'd17:
result[96:127]<={{17{reg_A[96]}},reg_A[96:110]};
5'd18:
result[96:127]<={{18{reg_A[96]}},reg_A[96:109]};
5'd19:
result[96:127]<={{19{reg_A[96]}},reg_A[96:108]};
5'd20:
result[96:127]<={{20{reg_A[96]}},reg_A[96:107]};
5'd21:
result[96:127]<={{21{reg_A[96]}},reg_A[96:106]};
5'd22:
result[96:127]<={{22{reg_A[96]}},reg_A[96:105]};
5'd23:
result[96:127]<={{23{reg_A[96]}},reg_A[96:104]};
5'd24:
result[96:127]<={{24{reg_A[96]}},reg_A[96:103]};
5'd25:
result[96:127]<={{25{reg_A[96]}},reg_A[96:102]};
5'd26:
result[96:127]<={{26{reg_A[96]}},reg_A[96:101]};
5'd27:
result[96:127]<={{27{reg_A[96]}},reg_A[96:100]};
5'd28:
result[96:127]<={{28{reg_A[96]}},reg_A[96:99]};
5'd29:
result[96:127]<={{29{reg_A[96]}},reg_A[96:98]};
5'd30:
result[96:127]<={{30{reg_A[96]}},reg_A[96:97]};
5'd31:
result[96:127]<={{31{reg_A[96]}},reg_A[96]};
default:
result[96:127]<=32'b0;
endcase
end
default
result<=128'b0;
endcase
end
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// ==================================================================
// !!TROY PART 2 START!!
// ==================================================================
default:
begin
// Default arithmetic/logic operation
result<=128'd0;
end
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYMETAL6S2S_BEHAVIORAL_V
`define SKY130_FD_SC_HD__DLYMETAL6S2S_BEHAVIORAL_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__dlymetal6s2s (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYMETAL6S2S_BEHAVIORAL_V |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ab
//
// Generated
// by: wig
// on: Tue Jul 4 08:39:13 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ab.v,v 1.3 2007/03/05 13:33:59 wig Exp $
// $Date: 2007/03/05 13:33:59 $
// $Log: ent_ab.v,v $
// Revision 1.3 2007/03/05 13:33:59 wig
// Updated testcase output (only comments)!
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_ab
//
// No user `defines in this module
module ent_ab
//
// Generated Module inst_ab
//
(
port_ab_1, // Use internally test1
port_ab_2, // Use internally test2, no port generated
sig_13, // Create internal signal name
sig_14 // Multiline comment 1
// Multiline comment 2
// Multiline comment 3
);
// Generated Module Inputs:
input port_ab_1;
input [4:0] sig_13;
input [6:0] sig_14;
// Generated Module Outputs:
output port_ab_2;
// Generated Wires:
wire port_ab_1;
reg port_ab_2;
wire [4:0] sig_13;
wire [6:0] sig_14;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of ent_ab
//
//
//!End of Module/s
// --------------------------------------------------------------
|
//ALU operations
module ALU(ALUop, Ain, Bin, ALUComputedValue, overflow);
`define ADD 2'b00
`define SUB 2'b01
`define ANDVAL 2'b10
`define NOTB 2'b11
parameter width= 1;
input [1:0] ALUop;
input [15:0] Ain, Bin;
output [15:0] ALUComputedValue;
output overflow;
reg addSubVals, andVals, notBVal, sub;
always @(*) begin
case(ALUop) //Set the operation needed to be true and the rest to be false
`ADD: {addSubVals, andVals, notBVal, sub}= {4'b1000};
`SUB: {addSubVals, andVals, notBVal, sub}= {4'b1001};
`ANDVAL: {addSubVals, andVals, notBVal, sub}= {4'b0100};
`NOTB: {addSubVals, andVals, notBVal, sub}= {4'b0010};
default: {addSubVals, andVals, notBVal, sub}= {4'bxxxx}; //default all x
endcase
end
//Instantiate operation module to compute the specified operation
operation #(16) instantiateOperation(
.Ain(Ain),
.Bin(Bin),
.overflow(overflow),
.addSubVals(addSubVals),
.andVals(andVals),
.notBVal(notBVal),
.sub(sub),
.computedValue(ALUComputedValue)
);
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
//
// Author : Praveen Kumar Pendyala
// Create Date : 05/27/13
// Modify Date : 16/07/14
// Module Name : mapping
// Project Name : PDL
// Target Devices : Xilinx Vertix 5, XUPV5 110T
// Tool versions : 13.2 ISE
//
// Description:
// This module maps the data received from the SircHandler to the puf.
// Does all singal mappings to input, interconnect and output networks.
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
`default_nettype none
module mapping #(
parameter CHALLENGE_WIDTH = 32,
parameter PDL_CONFIG_WIDTH = 128,
parameter RESPONSE_WIDTH = 6
)(
input wire clk,
input wire reset,
input wire trigger,
input wire [CHALLENGE_WIDTH-1:0] challenge,
input wire [PDL_CONFIG_WIDTH-1:0] pdl_config,
output reg done,
output wire [RESPONSE_WIDTH-1:0] raw_response,
output wire xor_response
);
//FSM States
localparam IDLE = 0;
localparam COMPUTE = 1;
//State Register
reg mp_state;
//Actual challenge after transformation
wire [CHALLENGE_WIDTH-1:0] actual_challenge;
///////////// Input network /////////////
(* KEEP_HIERARCHY="TRUE" *)
pufInputNetwork #(.Width(CHALLENGE_WIDTH))
pin(
.dataIn(challenge[CHALLENGE_WIDTH-1:0]),
.dataOut(actual_challenge[CHALLENGE_WIDTH-1:0])
);
//////////// Interconnect network & PUF ///////////////
(* KEEP_HIERARCHY="TRUE" *)
pufInterconNetwork picn (
.CHALLENGE(actual_challenge[CHALLENGE_WIDTH-1:0]),
.PDL_CONFIG(pdl_config[PDL_CONFIG_WIDTH-1:0]),
.RESPONSE(raw_response),
.trigger(trigger),
.reset(reset)
);
//////////// Output network ///////////////
(* KEEP_HIERARCHY="TRUE" *)
pufOutputNetwork pon (
.response(raw_response),
.xor_response(xor_response)
);
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module sirv_pwm8(
input clock,
input reset,
output io_interrupts_0_0,
output io_interrupts_0_1,
output io_interrupts_0_2,
output io_interrupts_0_3,
output io_in_0_a_ready,
input io_in_0_a_valid,
input [2:0] io_in_0_a_bits_opcode,
input [2:0] io_in_0_a_bits_param,
input [2:0] io_in_0_a_bits_size,
input [4:0] io_in_0_a_bits_source,
input [28:0] io_in_0_a_bits_address,
input [3:0] io_in_0_a_bits_mask,
input [31:0] io_in_0_a_bits_data,
input io_in_0_b_ready,
output io_in_0_b_valid,
output [2:0] io_in_0_b_bits_opcode,
output [1:0] io_in_0_b_bits_param,
output [2:0] io_in_0_b_bits_size,
output [4:0] io_in_0_b_bits_source,
output [28:0] io_in_0_b_bits_address,
output [3:0] io_in_0_b_bits_mask,
output [31:0] io_in_0_b_bits_data,
output io_in_0_c_ready,
input io_in_0_c_valid,
input [2:0] io_in_0_c_bits_opcode,
input [2:0] io_in_0_c_bits_param,
input [2:0] io_in_0_c_bits_size,
input [4:0] io_in_0_c_bits_source,
input [28:0] io_in_0_c_bits_address,
input [31:0] io_in_0_c_bits_data,
input io_in_0_c_bits_error,
input io_in_0_d_ready,
output io_in_0_d_valid,
output [2:0] io_in_0_d_bits_opcode,
output [1:0] io_in_0_d_bits_param,
output [2:0] io_in_0_d_bits_size,
output [4:0] io_in_0_d_bits_source,
output io_in_0_d_bits_sink,
output [1:0] io_in_0_d_bits_addr_lo,
output [31:0] io_in_0_d_bits_data,
output io_in_0_d_bits_error,
output io_in_0_e_ready,
input io_in_0_e_valid,
input io_in_0_e_bits_sink,
output io_gpio_0,
output io_gpio_1,
output io_gpio_2,
output io_gpio_3
);
wire pwm_clock;
wire pwm_reset;
wire pwm_io_regs_cfg_write_valid;
wire [31:0] pwm_io_regs_cfg_write_bits;
wire [31:0] pwm_io_regs_cfg_read;
wire pwm_io_regs_countLo_write_valid;
wire [31:0] pwm_io_regs_countLo_write_bits;
wire [31:0] pwm_io_regs_countLo_read;
wire pwm_io_regs_countHi_write_valid;
wire [31:0] pwm_io_regs_countHi_write_bits;
wire [31:0] pwm_io_regs_countHi_read;
wire pwm_io_regs_s_write_valid;
wire [7:0] pwm_io_regs_s_write_bits;
wire [7:0] pwm_io_regs_s_read;
wire pwm_io_regs_cmp_0_write_valid;
wire [7:0] pwm_io_regs_cmp_0_write_bits;
wire [7:0] pwm_io_regs_cmp_0_read;
wire pwm_io_regs_cmp_1_write_valid;
wire [7:0] pwm_io_regs_cmp_1_write_bits;
wire [7:0] pwm_io_regs_cmp_1_read;
wire pwm_io_regs_cmp_2_write_valid;
wire [7:0] pwm_io_regs_cmp_2_write_bits;
wire [7:0] pwm_io_regs_cmp_2_read;
wire pwm_io_regs_cmp_3_write_valid;
wire [7:0] pwm_io_regs_cmp_3_write_bits;
wire [7:0] pwm_io_regs_cmp_3_read;
wire pwm_io_regs_feed_write_valid;
wire [31:0] pwm_io_regs_feed_write_bits;
wire [31:0] pwm_io_regs_feed_read;
wire pwm_io_regs_key_write_valid;
wire [31:0] pwm_io_regs_key_write_bits;
wire [31:0] pwm_io_regs_key_read;
wire pwm_io_ip_0;
wire pwm_io_ip_1;
wire pwm_io_ip_2;
wire pwm_io_ip_3;
wire pwm_io_gpio_0;
wire pwm_io_gpio_1;
wire pwm_io_gpio_2;
wire pwm_io_gpio_3;
wire T_912_ready;
wire T_912_valid;
wire T_912_bits_read;
wire [9:0] T_912_bits_index;
wire [31:0] T_912_bits_data;
wire [3:0] T_912_bits_mask;
wire [9:0] T_912_bits_extra;
wire T_929;
wire [26:0] T_930;
wire [1:0] T_931;
wire [6:0] T_932;
wire [9:0] T_933;
wire T_951_ready;
wire T_951_valid;
wire T_951_bits_read;
wire [31:0] T_951_bits_data;
wire [9:0] T_951_bits_extra;
wire T_987_ready;
wire T_987_valid;
wire T_987_bits_read;
wire [9:0] T_987_bits_index;
wire [31:0] T_987_bits_data;
wire [3:0] T_987_bits_mask;
wire [9:0] T_987_bits_extra;
wire [9:0] T_1040;
wire T_1042;
wire [9:0] T_1048;
wire [9:0] T_1049;
wire T_1051;
wire [9:0] T_1057;
wire [9:0] T_1058;
wire T_1060;
wire [9:0] T_1066;
wire [9:0] T_1067;
wire T_1069;
wire [9:0] T_1075;
wire [9:0] T_1076;
wire T_1078;
wire [9:0] T_1084;
wire [9:0] T_1085;
wire T_1087;
wire [9:0] T_1093;
wire [9:0] T_1094;
wire T_1096;
wire [9:0] T_1102;
wire [9:0] T_1103;
wire T_1105;
wire [9:0] T_1111;
wire [9:0] T_1112;
wire T_1114;
wire [9:0] T_1120;
wire [9:0] T_1121;
wire T_1123;
wire T_1131_0;
wire T_1131_1;
wire T_1131_2;
wire T_1131_3;
wire T_1131_4;
wire T_1131_5;
wire T_1131_6;
wire T_1131_7;
wire T_1131_8;
wire T_1131_9;
wire T_1136_0;
wire T_1136_1;
wire T_1136_2;
wire T_1136_3;
wire T_1136_4;
wire T_1136_5;
wire T_1136_6;
wire T_1136_7;
wire T_1136_8;
wire T_1136_9;
wire T_1141_0;
wire T_1141_1;
wire T_1141_2;
wire T_1141_3;
wire T_1141_4;
wire T_1141_5;
wire T_1141_6;
wire T_1141_7;
wire T_1141_8;
wire T_1141_9;
wire T_1146_0;
wire T_1146_1;
wire T_1146_2;
wire T_1146_3;
wire T_1146_4;
wire T_1146_5;
wire T_1146_6;
wire T_1146_7;
wire T_1146_8;
wire T_1146_9;
wire T_1151_0;
wire T_1151_1;
wire T_1151_2;
wire T_1151_3;
wire T_1151_4;
wire T_1151_5;
wire T_1151_6;
wire T_1151_7;
wire T_1151_8;
wire T_1151_9;
wire T_1156_0;
wire T_1156_1;
wire T_1156_2;
wire T_1156_3;
wire T_1156_4;
wire T_1156_5;
wire T_1156_6;
wire T_1156_7;
wire T_1156_8;
wire T_1156_9;
wire T_1161_0;
wire T_1161_1;
wire T_1161_2;
wire T_1161_3;
wire T_1161_4;
wire T_1161_5;
wire T_1161_6;
wire T_1161_7;
wire T_1161_8;
wire T_1161_9;
wire T_1166_0;
wire T_1166_1;
wire T_1166_2;
wire T_1166_3;
wire T_1166_4;
wire T_1166_5;
wire T_1166_6;
wire T_1166_7;
wire T_1166_8;
wire T_1166_9;
wire T_1248;
wire T_1249;
wire T_1250;
wire T_1251;
wire [7:0] T_1255;
wire [7:0] T_1259;
wire [7:0] T_1263;
wire [7:0] T_1267;
wire [15:0] T_1268;
wire [15:0] T_1269;
wire [31:0] T_1270;
wire [31:0] T_1298;
wire T_1300;
wire T_1313;
wire [31:0] T_1329;
wire [7:0] T_1334;
wire [7:0] T_1338;
wire T_1340;
wire T_1353;
wire [7:0] T_1354;
wire [7:0] T_1369;
wire T_1393;
wire [31:0] T_1409;
wire T_1433;
wire [7:0] T_1449;
wire T_1473;
wire [31:0] T_1489;
wire T_1513;
wire [31:0] T_1529;
wire T_1553;
wire [31:0] T_1569;
wire T_1593;
wire [7:0] T_1609;
wire T_1633;
wire [7:0] T_1649;
wire T_1673;
wire [7:0] T_1689;
wire T_1695;
wire T_1697;
wire T_1702;
wire T_1704;
wire T_1706;
wire T_1708;
wire T_1710;
wire T_1712;
wire T_1717;
wire T_1719;
wire T_1721;
wire T_1723;
wire T_1725;
wire T_1727;
wire T_1729;
wire T_1731;
wire T_1733;
wire T_1735;
wire T_1737;
wire T_1739;
wire T_1771_0;
wire T_1771_1;
wire T_1771_2;
wire T_1771_3;
wire T_1771_4;
wire T_1771_5;
wire T_1771_6;
wire T_1771_7;
wire T_1771_8;
wire T_1771_9;
wire T_1771_10;
wire T_1771_11;
wire T_1771_12;
wire T_1771_13;
wire T_1771_14;
wire T_1771_15;
wire T_1793;
wire T_1800;
wire T_1804;
wire T_1808;
wire T_1815;
wire T_1819;
wire T_1823;
wire T_1827;
wire T_1831;
wire T_1835;
wire T_1867_0;
wire T_1867_1;
wire T_1867_2;
wire T_1867_3;
wire T_1867_4;
wire T_1867_5;
wire T_1867_6;
wire T_1867_7;
wire T_1867_8;
wire T_1867_9;
wire T_1867_10;
wire T_1867_11;
wire T_1867_12;
wire T_1867_13;
wire T_1867_14;
wire T_1867_15;
wire T_1889;
wire T_1896;
wire T_1900;
wire T_1904;
wire T_1911;
wire T_1915;
wire T_1919;
wire T_1923;
wire T_1927;
wire T_1931;
wire T_1963_0;
wire T_1963_1;
wire T_1963_2;
wire T_1963_3;
wire T_1963_4;
wire T_1963_5;
wire T_1963_6;
wire T_1963_7;
wire T_1963_8;
wire T_1963_9;
wire T_1963_10;
wire T_1963_11;
wire T_1963_12;
wire T_1963_13;
wire T_1963_14;
wire T_1963_15;
wire T_1985;
wire T_1992;
wire T_1996;
wire T_2000;
wire T_2007;
wire T_2011;
wire T_2015;
wire T_2019;
wire T_2023;
wire T_2027;
wire T_2059_0;
wire T_2059_1;
wire T_2059_2;
wire T_2059_3;
wire T_2059_4;
wire T_2059_5;
wire T_2059_6;
wire T_2059_7;
wire T_2059_8;
wire T_2059_9;
wire T_2059_10;
wire T_2059_11;
wire T_2059_12;
wire T_2059_13;
wire T_2059_14;
wire T_2059_15;
wire T_2078;
wire T_2079;
wire T_2080;
wire T_2081;
wire [1:0] T_2088;
wire [1:0] T_2089;
wire [3:0] T_2090;
wire GEN_0;
wire GEN_6;
wire GEN_7;
wire GEN_8;
wire GEN_9;
wire GEN_10;
wire GEN_11;
wire GEN_12;
wire GEN_13;
wire GEN_14;
wire GEN_15;
wire GEN_16;
wire GEN_17;
wire GEN_18;
wire GEN_19;
wire GEN_20;
wire GEN_1;
wire GEN_21;
wire GEN_22;
wire GEN_23;
wire GEN_24;
wire GEN_25;
wire GEN_26;
wire GEN_27;
wire GEN_28;
wire GEN_29;
wire GEN_30;
wire GEN_31;
wire GEN_32;
wire GEN_33;
wire GEN_34;
wire GEN_35;
wire T_2106;
wire GEN_2;
wire GEN_36;
wire GEN_37;
wire GEN_38;
wire GEN_39;
wire GEN_40;
wire GEN_41;
wire GEN_42;
wire GEN_43;
wire GEN_44;
wire GEN_45;
wire GEN_46;
wire GEN_47;
wire GEN_48;
wire GEN_49;
wire GEN_50;
wire GEN_3;
wire GEN_51;
wire GEN_52;
wire GEN_53;
wire GEN_54;
wire GEN_55;
wire GEN_56;
wire GEN_57;
wire GEN_58;
wire GEN_59;
wire GEN_60;
wire GEN_61;
wire GEN_62;
wire GEN_63;
wire GEN_64;
wire GEN_65;
wire T_2109;
wire T_2110;
wire T_2111;
wire T_2112;
wire T_2113;
wire [15:0] T_2115;
wire [1:0] T_2116;
wire [1:0] T_2117;
wire [3:0] T_2118;
wire [1:0] T_2119;
wire [1:0] T_2120;
wire [3:0] T_2121;
wire [7:0] T_2122;
wire [1:0] T_2123;
wire [1:0] T_2124;
wire [3:0] T_2125;
wire [7:0] T_2129;
wire [15:0] T_2130;
wire [15:0] T_2131;
wire T_2150;
wire T_2151;
wire T_2152;
wire T_2153;
wire T_2156;
wire T_2157;
wire T_2159;
wire T_2160;
wire T_2161;
wire T_2163;
wire T_2167;
wire T_2169;
wire T_2192;
wire T_2193;
wire T_2199;
wire T_2203;
wire T_2209;
wire T_2212;
wire T_2213;
wire T_2219;
wire T_2223;
wire T_2229;
wire T_2232;
wire T_2233;
wire T_2239;
wire T_2243;
wire T_2249;
wire T_2272;
wire T_2273;
wire T_2279;
wire T_2283;
wire T_2289;
wire T_2292;
wire T_2293;
wire T_2299;
wire T_2303;
wire T_2309;
wire T_2312;
wire T_2313;
wire T_2319;
wire T_2323;
wire T_2329;
wire T_2332;
wire T_2333;
wire T_2339;
wire T_2343;
wire T_2349;
wire T_2352;
wire T_2353;
wire T_2359;
wire T_2363;
wire T_2369;
wire T_2372;
wire T_2373;
wire T_2379;
wire T_2383;
wire T_2389;
wire T_2529_0;
wire T_2529_1;
wire T_2529_2;
wire T_2529_3;
wire T_2529_4;
wire T_2529_5;
wire T_2529_6;
wire T_2529_7;
wire T_2529_8;
wire T_2529_9;
wire T_2529_10;
wire T_2529_11;
wire T_2529_12;
wire T_2529_13;
wire T_2529_14;
wire T_2529_15;
wire [31:0] T_2568_0;
wire [31:0] T_2568_1;
wire [31:0] T_2568_2;
wire [31:0] T_2568_3;
wire [31:0] T_2568_4;
wire [31:0] T_2568_5;
wire [31:0] T_2568_6;
wire [31:0] T_2568_7;
wire [31:0] T_2568_8;
wire [31:0] T_2568_9;
wire [31:0] T_2568_10;
wire [31:0] T_2568_11;
wire [31:0] T_2568_12;
wire [31:0] T_2568_13;
wire [31:0] T_2568_14;
wire [31:0] T_2568_15;
wire GEN_4;
wire GEN_66;
wire GEN_67;
wire GEN_68;
wire GEN_69;
wire GEN_70;
wire GEN_71;
wire GEN_72;
wire GEN_73;
wire GEN_74;
wire GEN_75;
wire GEN_76;
wire GEN_77;
wire GEN_78;
wire GEN_79;
wire GEN_80;
wire [31:0] GEN_5;
wire [31:0] GEN_81;
wire [31:0] GEN_82;
wire [31:0] GEN_83;
wire [31:0] GEN_84;
wire [31:0] GEN_85;
wire [31:0] GEN_86;
wire [31:0] GEN_87;
wire [31:0] GEN_88;
wire [31:0] GEN_89;
wire [31:0] GEN_90;
wire [31:0] GEN_91;
wire [31:0] GEN_92;
wire [31:0] GEN_93;
wire [31:0] GEN_94;
wire [31:0] GEN_95;
wire [31:0] T_2589;
wire [1:0] T_2590;
wire [4:0] T_2592;
wire [2:0] T_2593;
wire [2:0] T_2604_opcode;
wire [1:0] T_2604_param;
wire [2:0] T_2604_size;
wire [4:0] T_2604_source;
wire T_2604_sink;
wire [1:0] T_2604_addr_lo;
wire [31:0] T_2604_data;
wire T_2604_error;
wire [2:0] GEN_96 = 3'b0;
reg [31:0] GEN_103;
wire [1:0] GEN_97 = 2'b0;
reg [31:0] GEN_104;
wire [2:0] GEN_98 = 3'b0;
reg [31:0] GEN_105;
wire [4:0] GEN_99 = 5'b0;
reg [31:0] GEN_106;
wire [28:0] GEN_100 = 29'b0;
reg [31:0] GEN_107;
wire [3:0] GEN_101 = 4'b0;
reg [31:0] GEN_108;
wire [31:0] GEN_102 = 32'b0;
reg [31:0] GEN_109;
sirv_pwm8_core pwm (
.clock(pwm_clock),
.reset(pwm_reset),
.io_regs_cfg_write_valid(pwm_io_regs_cfg_write_valid),
.io_regs_cfg_write_bits(pwm_io_regs_cfg_write_bits),
.io_regs_cfg_read(pwm_io_regs_cfg_read),
.io_regs_countLo_write_valid(pwm_io_regs_countLo_write_valid),
.io_regs_countLo_write_bits(pwm_io_regs_countLo_write_bits),
.io_regs_countLo_read(pwm_io_regs_countLo_read),
.io_regs_countHi_write_valid(pwm_io_regs_countHi_write_valid),
.io_regs_countHi_write_bits(pwm_io_regs_countHi_write_bits),
.io_regs_countHi_read(pwm_io_regs_countHi_read),
.io_regs_s_write_valid(pwm_io_regs_s_write_valid),
.io_regs_s_write_bits(pwm_io_regs_s_write_bits),
.io_regs_s_read(pwm_io_regs_s_read),
.io_regs_cmp_0_write_valid(pwm_io_regs_cmp_0_write_valid),
.io_regs_cmp_0_write_bits(pwm_io_regs_cmp_0_write_bits),
.io_regs_cmp_0_read(pwm_io_regs_cmp_0_read),
.io_regs_cmp_1_write_valid(pwm_io_regs_cmp_1_write_valid),
.io_regs_cmp_1_write_bits(pwm_io_regs_cmp_1_write_bits),
.io_regs_cmp_1_read(pwm_io_regs_cmp_1_read),
.io_regs_cmp_2_write_valid(pwm_io_regs_cmp_2_write_valid),
.io_regs_cmp_2_write_bits(pwm_io_regs_cmp_2_write_bits),
.io_regs_cmp_2_read(pwm_io_regs_cmp_2_read),
.io_regs_cmp_3_write_valid(pwm_io_regs_cmp_3_write_valid),
.io_regs_cmp_3_write_bits(pwm_io_regs_cmp_3_write_bits),
.io_regs_cmp_3_read(pwm_io_regs_cmp_3_read),
.io_regs_feed_write_valid(pwm_io_regs_feed_write_valid),
.io_regs_feed_write_bits(pwm_io_regs_feed_write_bits),
.io_regs_feed_read(pwm_io_regs_feed_read),
.io_regs_key_write_valid(pwm_io_regs_key_write_valid),
.io_regs_key_write_bits(pwm_io_regs_key_write_bits),
.io_regs_key_read(pwm_io_regs_key_read),
.io_ip_0(pwm_io_ip_0),
.io_ip_1(pwm_io_ip_1),
.io_ip_2(pwm_io_ip_2),
.io_ip_3(pwm_io_ip_3),
.io_gpio_0(pwm_io_gpio_0),
.io_gpio_1(pwm_io_gpio_1),
.io_gpio_2(pwm_io_gpio_2),
.io_gpio_3(pwm_io_gpio_3)
);
assign io_interrupts_0_0 = pwm_io_ip_0;
assign io_interrupts_0_1 = pwm_io_ip_1;
assign io_interrupts_0_2 = pwm_io_ip_2;
assign io_interrupts_0_3 = pwm_io_ip_3;
assign io_in_0_a_ready = T_912_ready;
assign io_in_0_b_valid = 1'h0;
assign io_in_0_b_bits_opcode = GEN_96;
assign io_in_0_b_bits_param = GEN_97;
assign io_in_0_b_bits_size = GEN_98;
assign io_in_0_b_bits_source = GEN_99;
assign io_in_0_b_bits_address = GEN_100;
assign io_in_0_b_bits_mask = GEN_101;
assign io_in_0_b_bits_data = GEN_102;
assign io_in_0_c_ready = 1'h1;
assign io_in_0_d_valid = T_951_valid;
assign io_in_0_d_bits_opcode = {{2'd0}, T_951_bits_read};
assign io_in_0_d_bits_param = T_2604_param;
assign io_in_0_d_bits_size = T_2604_size;
assign io_in_0_d_bits_source = T_2604_source;
assign io_in_0_d_bits_sink = T_2604_sink;
assign io_in_0_d_bits_addr_lo = T_2604_addr_lo;
assign io_in_0_d_bits_data = T_951_bits_data;
assign io_in_0_d_bits_error = T_2604_error;
assign io_in_0_e_ready = 1'h1;
assign io_gpio_0 = pwm_io_gpio_0;
assign io_gpio_1 = pwm_io_gpio_1;
assign io_gpio_2 = pwm_io_gpio_2;
assign io_gpio_3 = pwm_io_gpio_3;
assign pwm_clock = clock;
assign pwm_reset = reset;
assign pwm_io_regs_cfg_write_valid = T_1313;
assign pwm_io_regs_cfg_write_bits = T_987_bits_data;
assign pwm_io_regs_countLo_write_valid = T_1473;
assign pwm_io_regs_countLo_write_bits = T_987_bits_data;
assign pwm_io_regs_countHi_write_valid = T_1553;
assign pwm_io_regs_countHi_write_bits = T_987_bits_data;
assign pwm_io_regs_s_write_valid = T_1673;
assign pwm_io_regs_s_write_bits = T_1354;
assign pwm_io_regs_cmp_0_write_valid = T_1633;
assign pwm_io_regs_cmp_0_write_bits = T_1354;
assign pwm_io_regs_cmp_1_write_valid = T_1433;
assign pwm_io_regs_cmp_1_write_bits = T_1354;
assign pwm_io_regs_cmp_2_write_valid = T_1353;
assign pwm_io_regs_cmp_2_write_bits = T_1354;
assign pwm_io_regs_cmp_3_write_valid = T_1593;
assign pwm_io_regs_cmp_3_write_bits = T_1354;
assign pwm_io_regs_feed_write_valid = T_1393;
assign pwm_io_regs_feed_write_bits = T_987_bits_data;
assign pwm_io_regs_key_write_valid = T_1513;
assign pwm_io_regs_key_write_bits = T_987_bits_data;
assign T_912_ready = T_2110;
assign T_912_valid = io_in_0_a_valid;
assign T_912_bits_read = T_929;
assign T_912_bits_index = T_930[9:0];
assign T_912_bits_data = io_in_0_a_bits_data;
assign T_912_bits_mask = io_in_0_a_bits_mask;
assign T_912_bits_extra = T_933;
assign T_929 = io_in_0_a_bits_opcode == 3'h4;
assign T_930 = io_in_0_a_bits_address[28:2];
assign T_931 = io_in_0_a_bits_address[1:0];
assign T_932 = {T_931,io_in_0_a_bits_source};
assign T_933 = {T_932,io_in_0_a_bits_size};
assign T_951_ready = io_in_0_d_ready;
assign T_951_valid = T_2113;
assign T_951_bits_read = T_987_bits_read;
assign T_951_bits_data = T_2589;
assign T_951_bits_extra = T_987_bits_extra;
assign T_987_ready = T_2112;
assign T_987_valid = T_2111;
assign T_987_bits_read = T_912_bits_read;
assign T_987_bits_index = T_912_bits_index;
assign T_987_bits_data = T_912_bits_data;
assign T_987_bits_mask = T_912_bits_mask;
assign T_987_bits_extra = T_912_bits_extra;
assign T_1040 = T_987_bits_index & 10'h3f0;
assign T_1042 = T_1040 == 10'h0;
assign T_1048 = T_987_bits_index ^ 10'ha;
assign T_1049 = T_1048 & 10'h3f0;
assign T_1051 = T_1049 == 10'h0;
assign T_1057 = T_987_bits_index ^ 10'h6;
assign T_1058 = T_1057 & 10'h3f0;
assign T_1060 = T_1058 == 10'h0;
assign T_1066 = T_987_bits_index ^ 10'h9;
assign T_1067 = T_1066 & 10'h3f0;
assign T_1069 = T_1067 == 10'h0;
assign T_1075 = T_987_bits_index ^ 10'h2;
assign T_1076 = T_1075 & 10'h3f0;
assign T_1078 = T_1076 == 10'h0;
assign T_1084 = T_987_bits_index ^ 10'h7;
assign T_1085 = T_1084 & 10'h3f0;
assign T_1087 = T_1085 == 10'h0;
assign T_1093 = T_987_bits_index ^ 10'h3;
assign T_1094 = T_1093 & 10'h3f0;
assign T_1096 = T_1094 == 10'h0;
assign T_1102 = T_987_bits_index ^ 10'hb;
assign T_1103 = T_1102 & 10'h3f0;
assign T_1105 = T_1103 == 10'h0;
assign T_1111 = T_987_bits_index ^ 10'h8;
assign T_1112 = T_1111 & 10'h3f0;
assign T_1114 = T_1112 == 10'h0;
assign T_1120 = T_987_bits_index ^ 10'h4;
assign T_1121 = T_1120 & 10'h3f0;
assign T_1123 = T_1121 == 10'h0;
assign T_1131_0 = T_2153;
assign T_1131_1 = T_2353;
assign T_1131_2 = T_2273;
assign T_1131_3 = T_2333;
assign T_1131_4 = T_2193;
assign T_1131_5 = T_2293;
assign T_1131_6 = T_2213;
assign T_1131_7 = T_2373;
assign T_1131_8 = T_2313;
assign T_1131_9 = T_2233;
assign T_1136_0 = T_2159;
assign T_1136_1 = T_2359;
assign T_1136_2 = T_2279;
assign T_1136_3 = T_2339;
assign T_1136_4 = T_2199;
assign T_1136_5 = T_2299;
assign T_1136_6 = T_2219;
assign T_1136_7 = T_2379;
assign T_1136_8 = T_2319;
assign T_1136_9 = T_2239;
assign T_1141_0 = 1'h1;
assign T_1141_1 = 1'h1;
assign T_1141_2 = 1'h1;
assign T_1141_3 = 1'h1;
assign T_1141_4 = 1'h1;
assign T_1141_5 = 1'h1;
assign T_1141_6 = 1'h1;
assign T_1141_7 = 1'h1;
assign T_1141_8 = 1'h1;
assign T_1141_9 = 1'h1;
assign T_1146_0 = 1'h1;
assign T_1146_1 = 1'h1;
assign T_1146_2 = 1'h1;
assign T_1146_3 = 1'h1;
assign T_1146_4 = 1'h1;
assign T_1146_5 = 1'h1;
assign T_1146_6 = 1'h1;
assign T_1146_7 = 1'h1;
assign T_1146_8 = 1'h1;
assign T_1146_9 = 1'h1;
assign T_1151_0 = 1'h1;
assign T_1151_1 = 1'h1;
assign T_1151_2 = 1'h1;
assign T_1151_3 = 1'h1;
assign T_1151_4 = 1'h1;
assign T_1151_5 = 1'h1;
assign T_1151_6 = 1'h1;
assign T_1151_7 = 1'h1;
assign T_1151_8 = 1'h1;
assign T_1151_9 = 1'h1;
assign T_1156_0 = 1'h1;
assign T_1156_1 = 1'h1;
assign T_1156_2 = 1'h1;
assign T_1156_3 = 1'h1;
assign T_1156_4 = 1'h1;
assign T_1156_5 = 1'h1;
assign T_1156_6 = 1'h1;
assign T_1156_7 = 1'h1;
assign T_1156_8 = 1'h1;
assign T_1156_9 = 1'h1;
assign T_1161_0 = T_2163;
assign T_1161_1 = T_2363;
assign T_1161_2 = T_2283;
assign T_1161_3 = T_2343;
assign T_1161_4 = T_2203;
assign T_1161_5 = T_2303;
assign T_1161_6 = T_2223;
assign T_1161_7 = T_2383;
assign T_1161_8 = T_2323;
assign T_1161_9 = T_2243;
assign T_1166_0 = T_2169;
assign T_1166_1 = T_2369;
assign T_1166_2 = T_2289;
assign T_1166_3 = T_2349;
assign T_1166_4 = T_2209;
assign T_1166_5 = T_2309;
assign T_1166_6 = T_2229;
assign T_1166_7 = T_2389;
assign T_1166_8 = T_2329;
assign T_1166_9 = T_2249;
assign T_1248 = T_987_bits_mask[0];
assign T_1249 = T_987_bits_mask[1];
assign T_1250 = T_987_bits_mask[2];
assign T_1251 = T_987_bits_mask[3];
assign T_1255 = T_1248 ? 8'hff : 8'h0;
assign T_1259 = T_1249 ? 8'hff : 8'h0;
assign T_1263 = T_1250 ? 8'hff : 8'h0;
assign T_1267 = T_1251 ? 8'hff : 8'h0;
assign T_1268 = {T_1259,T_1255};
assign T_1269 = {T_1267,T_1263};
assign T_1270 = {T_1269,T_1268};
assign T_1298 = ~ T_1270;
assign T_1300 = T_1298 == 32'h0;
assign T_1313 = T_1166_0 & T_1300;
assign T_1329 = pwm_io_regs_cfg_read;
assign T_1334 = T_1270[7:0];
assign T_1338 = ~ T_1334;
assign T_1340 = T_1338 == 8'h0;
assign T_1353 = T_1166_1 & T_1340;
assign T_1354 = T_987_bits_data[7:0];
assign T_1369 = pwm_io_regs_cmp_2_read;
assign T_1393 = T_1166_2 & T_1300;
assign T_1409 = pwm_io_regs_feed_read;
assign T_1433 = T_1166_3 & T_1340;
assign T_1449 = pwm_io_regs_cmp_1_read;
assign T_1473 = T_1166_4 & T_1300;
assign T_1489 = pwm_io_regs_countLo_read;
assign T_1513 = T_1166_5 & T_1300;
assign T_1529 = pwm_io_regs_key_read;
assign T_1553 = T_1166_6 & T_1300;
assign T_1569 = pwm_io_regs_countHi_read;
assign T_1593 = T_1166_7 & T_1340;
assign T_1609 = pwm_io_regs_cmp_3_read;
assign T_1633 = T_1166_8 & T_1340;
assign T_1649 = pwm_io_regs_cmp_0_read;
assign T_1673 = T_1166_9 & T_1340;
assign T_1689 = pwm_io_regs_s_read;
assign T_1695 = T_1042 == 1'h0;
assign T_1697 = T_1695 | T_1141_0;
assign T_1702 = T_1078 == 1'h0;
assign T_1704 = T_1702 | T_1141_4;
assign T_1706 = T_1096 == 1'h0;
assign T_1708 = T_1706 | T_1141_6;
assign T_1710 = T_1123 == 1'h0;
assign T_1712 = T_1710 | T_1141_9;
assign T_1717 = T_1060 == 1'h0;
assign T_1719 = T_1717 | T_1141_2;
assign T_1721 = T_1087 == 1'h0;
assign T_1723 = T_1721 | T_1141_5;
assign T_1725 = T_1114 == 1'h0;
assign T_1727 = T_1725 | T_1141_8;
assign T_1729 = T_1069 == 1'h0;
assign T_1731 = T_1729 | T_1141_3;
assign T_1733 = T_1051 == 1'h0;
assign T_1735 = T_1733 | T_1141_1;
assign T_1737 = T_1105 == 1'h0;
assign T_1739 = T_1737 | T_1141_7;
assign T_1771_0 = T_1697;
assign T_1771_1 = 1'h1;
assign T_1771_2 = T_1704;
assign T_1771_3 = T_1708;
assign T_1771_4 = T_1712;
assign T_1771_5 = 1'h1;
assign T_1771_6 = T_1719;
assign T_1771_7 = T_1723;
assign T_1771_8 = T_1727;
assign T_1771_9 = T_1731;
assign T_1771_10 = T_1735;
assign T_1771_11 = T_1739;
assign T_1771_12 = 1'h1;
assign T_1771_13 = 1'h1;
assign T_1771_14 = 1'h1;
assign T_1771_15 = 1'h1;
assign T_1793 = T_1695 | T_1146_0;
assign T_1800 = T_1702 | T_1146_4;
assign T_1804 = T_1706 | T_1146_6;
assign T_1808 = T_1710 | T_1146_9;
assign T_1815 = T_1717 | T_1146_2;
assign T_1819 = T_1721 | T_1146_5;
assign T_1823 = T_1725 | T_1146_8;
assign T_1827 = T_1729 | T_1146_3;
assign T_1831 = T_1733 | T_1146_1;
assign T_1835 = T_1737 | T_1146_7;
assign T_1867_0 = T_1793;
assign T_1867_1 = 1'h1;
assign T_1867_2 = T_1800;
assign T_1867_3 = T_1804;
assign T_1867_4 = T_1808;
assign T_1867_5 = 1'h1;
assign T_1867_6 = T_1815;
assign T_1867_7 = T_1819;
assign T_1867_8 = T_1823;
assign T_1867_9 = T_1827;
assign T_1867_10 = T_1831;
assign T_1867_11 = T_1835;
assign T_1867_12 = 1'h1;
assign T_1867_13 = 1'h1;
assign T_1867_14 = 1'h1;
assign T_1867_15 = 1'h1;
assign T_1889 = T_1695 | T_1151_0;
assign T_1896 = T_1702 | T_1151_4;
assign T_1900 = T_1706 | T_1151_6;
assign T_1904 = T_1710 | T_1151_9;
assign T_1911 = T_1717 | T_1151_2;
assign T_1915 = T_1721 | T_1151_5;
assign T_1919 = T_1725 | T_1151_8;
assign T_1923 = T_1729 | T_1151_3;
assign T_1927 = T_1733 | T_1151_1;
assign T_1931 = T_1737 | T_1151_7;
assign T_1963_0 = T_1889;
assign T_1963_1 = 1'h1;
assign T_1963_2 = T_1896;
assign T_1963_3 = T_1900;
assign T_1963_4 = T_1904;
assign T_1963_5 = 1'h1;
assign T_1963_6 = T_1911;
assign T_1963_7 = T_1915;
assign T_1963_8 = T_1919;
assign T_1963_9 = T_1923;
assign T_1963_10 = T_1927;
assign T_1963_11 = T_1931;
assign T_1963_12 = 1'h1;
assign T_1963_13 = 1'h1;
assign T_1963_14 = 1'h1;
assign T_1963_15 = 1'h1;
assign T_1985 = T_1695 | T_1156_0;
assign T_1992 = T_1702 | T_1156_4;
assign T_1996 = T_1706 | T_1156_6;
assign T_2000 = T_1710 | T_1156_9;
assign T_2007 = T_1717 | T_1156_2;
assign T_2011 = T_1721 | T_1156_5;
assign T_2015 = T_1725 | T_1156_8;
assign T_2019 = T_1729 | T_1156_3;
assign T_2023 = T_1733 | T_1156_1;
assign T_2027 = T_1737 | T_1156_7;
assign T_2059_0 = T_1985;
assign T_2059_1 = 1'h1;
assign T_2059_2 = T_1992;
assign T_2059_3 = T_1996;
assign T_2059_4 = T_2000;
assign T_2059_5 = 1'h1;
assign T_2059_6 = T_2007;
assign T_2059_7 = T_2011;
assign T_2059_8 = T_2015;
assign T_2059_9 = T_2019;
assign T_2059_10 = T_2023;
assign T_2059_11 = T_2027;
assign T_2059_12 = 1'h1;
assign T_2059_13 = 1'h1;
assign T_2059_14 = 1'h1;
assign T_2059_15 = 1'h1;
assign T_2078 = T_987_bits_index[0];
assign T_2079 = T_987_bits_index[1];
assign T_2080 = T_987_bits_index[2];
assign T_2081 = T_987_bits_index[3];
assign T_2088 = {T_2079,T_2078};
assign T_2089 = {T_2081,T_2080};
assign T_2090 = {T_2089,T_2088};
assign GEN_0 = GEN_20;
assign GEN_6 = 4'h1 == T_2090 ? T_1771_1 : T_1771_0;
assign GEN_7 = 4'h2 == T_2090 ? T_1771_2 : GEN_6;
assign GEN_8 = 4'h3 == T_2090 ? T_1771_3 : GEN_7;
assign GEN_9 = 4'h4 == T_2090 ? T_1771_4 : GEN_8;
assign GEN_10 = 4'h5 == T_2090 ? T_1771_5 : GEN_9;
assign GEN_11 = 4'h6 == T_2090 ? T_1771_6 : GEN_10;
assign GEN_12 = 4'h7 == T_2090 ? T_1771_7 : GEN_11;
assign GEN_13 = 4'h8 == T_2090 ? T_1771_8 : GEN_12;
assign GEN_14 = 4'h9 == T_2090 ? T_1771_9 : GEN_13;
assign GEN_15 = 4'ha == T_2090 ? T_1771_10 : GEN_14;
assign GEN_16 = 4'hb == T_2090 ? T_1771_11 : GEN_15;
assign GEN_17 = 4'hc == T_2090 ? T_1771_12 : GEN_16;
assign GEN_18 = 4'hd == T_2090 ? T_1771_13 : GEN_17;
assign GEN_19 = 4'he == T_2090 ? T_1771_14 : GEN_18;
assign GEN_20 = 4'hf == T_2090 ? T_1771_15 : GEN_19;
assign GEN_1 = GEN_35;
assign GEN_21 = 4'h1 == T_2090 ? T_1867_1 : T_1867_0;
assign GEN_22 = 4'h2 == T_2090 ? T_1867_2 : GEN_21;
assign GEN_23 = 4'h3 == T_2090 ? T_1867_3 : GEN_22;
assign GEN_24 = 4'h4 == T_2090 ? T_1867_4 : GEN_23;
assign GEN_25 = 4'h5 == T_2090 ? T_1867_5 : GEN_24;
assign GEN_26 = 4'h6 == T_2090 ? T_1867_6 : GEN_25;
assign GEN_27 = 4'h7 == T_2090 ? T_1867_7 : GEN_26;
assign GEN_28 = 4'h8 == T_2090 ? T_1867_8 : GEN_27;
assign GEN_29 = 4'h9 == T_2090 ? T_1867_9 : GEN_28;
assign GEN_30 = 4'ha == T_2090 ? T_1867_10 : GEN_29;
assign GEN_31 = 4'hb == T_2090 ? T_1867_11 : GEN_30;
assign GEN_32 = 4'hc == T_2090 ? T_1867_12 : GEN_31;
assign GEN_33 = 4'hd == T_2090 ? T_1867_13 : GEN_32;
assign GEN_34 = 4'he == T_2090 ? T_1867_14 : GEN_33;
assign GEN_35 = 4'hf == T_2090 ? T_1867_15 : GEN_34;
assign T_2106 = T_987_bits_read ? GEN_0 : GEN_1;
assign GEN_2 = GEN_50;
assign GEN_36 = 4'h1 == T_2090 ? T_1963_1 : T_1963_0;
assign GEN_37 = 4'h2 == T_2090 ? T_1963_2 : GEN_36;
assign GEN_38 = 4'h3 == T_2090 ? T_1963_3 : GEN_37;
assign GEN_39 = 4'h4 == T_2090 ? T_1963_4 : GEN_38;
assign GEN_40 = 4'h5 == T_2090 ? T_1963_5 : GEN_39;
assign GEN_41 = 4'h6 == T_2090 ? T_1963_6 : GEN_40;
assign GEN_42 = 4'h7 == T_2090 ? T_1963_7 : GEN_41;
assign GEN_43 = 4'h8 == T_2090 ? T_1963_8 : GEN_42;
assign GEN_44 = 4'h9 == T_2090 ? T_1963_9 : GEN_43;
assign GEN_45 = 4'ha == T_2090 ? T_1963_10 : GEN_44;
assign GEN_46 = 4'hb == T_2090 ? T_1963_11 : GEN_45;
assign GEN_47 = 4'hc == T_2090 ? T_1963_12 : GEN_46;
assign GEN_48 = 4'hd == T_2090 ? T_1963_13 : GEN_47;
assign GEN_49 = 4'he == T_2090 ? T_1963_14 : GEN_48;
assign GEN_50 = 4'hf == T_2090 ? T_1963_15 : GEN_49;
assign GEN_3 = GEN_65;
assign GEN_51 = 4'h1 == T_2090 ? T_2059_1 : T_2059_0;
assign GEN_52 = 4'h2 == T_2090 ? T_2059_2 : GEN_51;
assign GEN_53 = 4'h3 == T_2090 ? T_2059_3 : GEN_52;
assign GEN_54 = 4'h4 == T_2090 ? T_2059_4 : GEN_53;
assign GEN_55 = 4'h5 == T_2090 ? T_2059_5 : GEN_54;
assign GEN_56 = 4'h6 == T_2090 ? T_2059_6 : GEN_55;
assign GEN_57 = 4'h7 == T_2090 ? T_2059_7 : GEN_56;
assign GEN_58 = 4'h8 == T_2090 ? T_2059_8 : GEN_57;
assign GEN_59 = 4'h9 == T_2090 ? T_2059_9 : GEN_58;
assign GEN_60 = 4'ha == T_2090 ? T_2059_10 : GEN_59;
assign GEN_61 = 4'hb == T_2090 ? T_2059_11 : GEN_60;
assign GEN_62 = 4'hc == T_2090 ? T_2059_12 : GEN_61;
assign GEN_63 = 4'hd == T_2090 ? T_2059_13 : GEN_62;
assign GEN_64 = 4'he == T_2090 ? T_2059_14 : GEN_63;
assign GEN_65 = 4'hf == T_2090 ? T_2059_15 : GEN_64;
assign T_2109 = T_987_bits_read ? GEN_2 : GEN_3;
assign T_2110 = T_987_ready & T_2106;
assign T_2111 = T_912_valid & T_2106;
assign T_2112 = T_951_ready & T_2109;
assign T_2113 = T_987_valid & T_2109;
assign T_2115 = 16'h1 << T_2090;
assign T_2116 = {1'h1,T_1042};
assign T_2117 = {T_1096,T_1078};
assign T_2118 = {T_2117,T_2116};
assign T_2119 = {1'h1,T_1123};
assign T_2120 = {T_1087,T_1060};
assign T_2121 = {T_2120,T_2119};
assign T_2122 = {T_2121,T_2118};
assign T_2123 = {T_1069,T_1114};
assign T_2124 = {T_1105,T_1051};
assign T_2125 = {T_2124,T_2123};
assign T_2129 = {4'hf,T_2125};
assign T_2130 = {T_2129,T_2122};
assign T_2131 = T_2115 & T_2130;
assign T_2150 = T_912_valid & T_987_ready;
assign T_2151 = T_2150 & T_987_bits_read;
assign T_2152 = T_2131[0];
assign T_2153 = T_2151 & T_2152;
assign T_2156 = T_987_bits_read == 1'h0;
assign T_2157 = T_2150 & T_2156;
assign T_2159 = T_2157 & T_2152;
assign T_2160 = T_987_valid & T_951_ready;
assign T_2161 = T_2160 & T_987_bits_read;
assign T_2163 = T_2161 & T_2152;
assign T_2167 = T_2160 & T_2156;
assign T_2169 = T_2167 & T_2152;
assign T_2192 = T_2131[2];
assign T_2193 = T_2151 & T_2192;
assign T_2199 = T_2157 & T_2192;
assign T_2203 = T_2161 & T_2192;
assign T_2209 = T_2167 & T_2192;
assign T_2212 = T_2131[3];
assign T_2213 = T_2151 & T_2212;
assign T_2219 = T_2157 & T_2212;
assign T_2223 = T_2161 & T_2212;
assign T_2229 = T_2167 & T_2212;
assign T_2232 = T_2131[4];
assign T_2233 = T_2151 & T_2232;
assign T_2239 = T_2157 & T_2232;
assign T_2243 = T_2161 & T_2232;
assign T_2249 = T_2167 & T_2232;
assign T_2272 = T_2131[6];
assign T_2273 = T_2151 & T_2272;
assign T_2279 = T_2157 & T_2272;
assign T_2283 = T_2161 & T_2272;
assign T_2289 = T_2167 & T_2272;
assign T_2292 = T_2131[7];
assign T_2293 = T_2151 & T_2292;
assign T_2299 = T_2157 & T_2292;
assign T_2303 = T_2161 & T_2292;
assign T_2309 = T_2167 & T_2292;
assign T_2312 = T_2131[8];
assign T_2313 = T_2151 & T_2312;
assign T_2319 = T_2157 & T_2312;
assign T_2323 = T_2161 & T_2312;
assign T_2329 = T_2167 & T_2312;
assign T_2332 = T_2131[9];
assign T_2333 = T_2151 & T_2332;
assign T_2339 = T_2157 & T_2332;
assign T_2343 = T_2161 & T_2332;
assign T_2349 = T_2167 & T_2332;
assign T_2352 = T_2131[10];
assign T_2353 = T_2151 & T_2352;
assign T_2359 = T_2157 & T_2352;
assign T_2363 = T_2161 & T_2352;
assign T_2369 = T_2167 & T_2352;
assign T_2372 = T_2131[11];
assign T_2373 = T_2151 & T_2372;
assign T_2379 = T_2157 & T_2372;
assign T_2383 = T_2161 & T_2372;
assign T_2389 = T_2167 & T_2372;
assign T_2529_0 = T_1042;
assign T_2529_1 = 1'h1;
assign T_2529_2 = T_1078;
assign T_2529_3 = T_1096;
assign T_2529_4 = T_1123;
assign T_2529_5 = 1'h1;
assign T_2529_6 = T_1060;
assign T_2529_7 = T_1087;
assign T_2529_8 = T_1114;
assign T_2529_9 = T_1069;
assign T_2529_10 = T_1051;
assign T_2529_11 = T_1105;
assign T_2529_12 = 1'h1;
assign T_2529_13 = 1'h1;
assign T_2529_14 = 1'h1;
assign T_2529_15 = 1'h1;
assign T_2568_0 = T_1329;
assign T_2568_1 = 32'h0;
assign T_2568_2 = T_1489;
assign T_2568_3 = T_1569;
assign T_2568_4 = {{24'd0}, T_1689};
assign T_2568_5 = 32'h0;
assign T_2568_6 = T_1409;
assign T_2568_7 = T_1529;
assign T_2568_8 = {{24'd0}, T_1649};
assign T_2568_9 = {{24'd0}, T_1449};
assign T_2568_10 = {{24'd0}, T_1369};
assign T_2568_11 = {{24'd0}, T_1609};
assign T_2568_12 = 32'h0;
assign T_2568_13 = 32'h0;
assign T_2568_14 = 32'h0;
assign T_2568_15 = 32'h0;
assign GEN_4 = GEN_80;
assign GEN_66 = 4'h1 == T_2090 ? T_2529_1 : T_2529_0;
assign GEN_67 = 4'h2 == T_2090 ? T_2529_2 : GEN_66;
assign GEN_68 = 4'h3 == T_2090 ? T_2529_3 : GEN_67;
assign GEN_69 = 4'h4 == T_2090 ? T_2529_4 : GEN_68;
assign GEN_70 = 4'h5 == T_2090 ? T_2529_5 : GEN_69;
assign GEN_71 = 4'h6 == T_2090 ? T_2529_6 : GEN_70;
assign GEN_72 = 4'h7 == T_2090 ? T_2529_7 : GEN_71;
assign GEN_73 = 4'h8 == T_2090 ? T_2529_8 : GEN_72;
assign GEN_74 = 4'h9 == T_2090 ? T_2529_9 : GEN_73;
assign GEN_75 = 4'ha == T_2090 ? T_2529_10 : GEN_74;
assign GEN_76 = 4'hb == T_2090 ? T_2529_11 : GEN_75;
assign GEN_77 = 4'hc == T_2090 ? T_2529_12 : GEN_76;
assign GEN_78 = 4'hd == T_2090 ? T_2529_13 : GEN_77;
assign GEN_79 = 4'he == T_2090 ? T_2529_14 : GEN_78;
assign GEN_80 = 4'hf == T_2090 ? T_2529_15 : GEN_79;
assign GEN_5 = GEN_95;
assign GEN_81 = 4'h1 == T_2090 ? T_2568_1 : T_2568_0;
assign GEN_82 = 4'h2 == T_2090 ? T_2568_2 : GEN_81;
assign GEN_83 = 4'h3 == T_2090 ? T_2568_3 : GEN_82;
assign GEN_84 = 4'h4 == T_2090 ? T_2568_4 : GEN_83;
assign GEN_85 = 4'h5 == T_2090 ? T_2568_5 : GEN_84;
assign GEN_86 = 4'h6 == T_2090 ? T_2568_6 : GEN_85;
assign GEN_87 = 4'h7 == T_2090 ? T_2568_7 : GEN_86;
assign GEN_88 = 4'h8 == T_2090 ? T_2568_8 : GEN_87;
assign GEN_89 = 4'h9 == T_2090 ? T_2568_9 : GEN_88;
assign GEN_90 = 4'ha == T_2090 ? T_2568_10 : GEN_89;
assign GEN_91 = 4'hb == T_2090 ? T_2568_11 : GEN_90;
assign GEN_92 = 4'hc == T_2090 ? T_2568_12 : GEN_91;
assign GEN_93 = 4'hd == T_2090 ? T_2568_13 : GEN_92;
assign GEN_94 = 4'he == T_2090 ? T_2568_14 : GEN_93;
assign GEN_95 = 4'hf == T_2090 ? T_2568_15 : GEN_94;
assign T_2589 = GEN_4 ? GEN_5 : 32'h0;
assign T_2590 = T_951_bits_extra[9:8];
assign T_2592 = T_951_bits_extra[7:3];
assign T_2593 = T_951_bits_extra[2:0];
assign T_2604_opcode = 3'h0;
assign T_2604_param = 2'h0;
assign T_2604_size = T_2593;
assign T_2604_source = T_2592;
assign T_2604_sink = 1'h0;
assign T_2604_addr_lo = T_2590;
assign T_2604_data = 32'h0;
assign T_2604_error = 1'h0;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin end
`endif
`ifdef RANDOMIZE_REG_INIT
GEN_103 = {1{$random}};
GEN_96 = GEN_103[2:0];
`endif
`ifdef RANDOMIZE_REG_INIT
GEN_104 = {1{$random}};
GEN_97 = GEN_104[1:0];
`endif
`ifdef RANDOMIZE_REG_INIT
GEN_105 = {1{$random}};
GEN_98 = GEN_105[2:0];
`endif
`ifdef RANDOMIZE_REG_INIT
GEN_106 = {1{$random}};
GEN_99 = GEN_106[4:0];
`endif
`ifdef RANDOMIZE_REG_INIT
GEN_107 = {1{$random}};
GEN_100 = GEN_107[28:0];
`endif
`ifdef RANDOMIZE_REG_INIT
GEN_108 = {1{$random}};
GEN_101 = GEN_108[3:0];
`endif
`ifdef RANDOMIZE_REG_INIT
GEN_109 = {1{$random}};
GEN_102 = GEN_109[31:0];
`endif
end
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFXTP_SYMBOL_V
`define SKY130_FD_SC_HD__DFXTP_SYMBOL_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFXTP_SYMBOL_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_rxaddrcheck.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/cores/ethmac/ ////
//// ////
//// Author(s): ////
//// - Bill Dittenhofer ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_rxaddrcheck.v,v $
// Revision 1.9 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.8 2002/11/19 17:34:52 mohor
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
// that a frame was received because of the promiscous mode.
//
// Revision 1.7 2002/09/04 18:41:06 mohor
// Bug when last byte of destination address was not checked fixed.
//
// Revision 1.6 2002/03/20 15:14:11 mohor
// When in promiscous mode some frames were not received correctly. Fixed.
//
// Revision 1.5 2002/03/02 21:06:32 mohor
// Log info was missing.
//
//
// Revision 1.1 2002/02/08 12:51:54 ditt
// Initial release of the ethernet addresscheck module.
//
//
//
//
//
`include "timescale.v"
module eth_rxaddrcheck(MRxClk, Reset, RxData, Broadcast ,r_Bro ,r_Pro,
ByteCntEq2, ByteCntEq3, ByteCntEq4, ByteCntEq5,
ByteCntEq6, ByteCntEq7, HASH0, HASH1,
CrcHash, CrcHashGood, StateData, RxEndFrm,
Multicast, MAC, RxAbort, AddressMiss, PassAll,
ControlFrmAddressOK
);
parameter Tp = 1;
input MRxClk;
input Reset;
input [7:0] RxData;
input Broadcast;
input r_Bro;
input r_Pro;
input ByteCntEq2;
input ByteCntEq3;
input ByteCntEq4;
input ByteCntEq5;
input ByteCntEq6;
input ByteCntEq7;
input [31:0] HASH0;
input [31:0] HASH1;
input [5:0] CrcHash;
input CrcHashGood;
input Multicast;
input [47:0] MAC;
input [1:0] StateData;
input RxEndFrm;
input PassAll;
input ControlFrmAddressOK;
output RxAbort;
output AddressMiss;
wire BroadcastOK;
wire ByteCntEq2;
wire ByteCntEq3;
wire ByteCntEq4;
wire ByteCntEq5;
wire RxAddressInvalid;
wire RxCheckEn;
wire HashBit;
wire [31:0] IntHash;
reg [7:0] ByteHash;
reg MulticastOK;
reg UnicastOK;
reg RxAbort;
reg AddressMiss;
assign RxAddressInvalid = ~(UnicastOK | BroadcastOK | MulticastOK | r_Pro);
assign BroadcastOK = Broadcast & ~r_Bro;
assign RxCheckEn = | StateData;
// Address Error Reported at end of address cycle
// RxAbort clears after one cycle
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxAbort <= #Tp 1'b0;
else if(RxAddressInvalid & ByteCntEq7 & RxCheckEn)
RxAbort <= #Tp 1'b1;
else
RxAbort <= #Tp 1'b0;
end
// This ff holds the "Address Miss" information that is written to the RX BD status.
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
AddressMiss <= #Tp 1'b0;
else if(ByteCntEq7 & RxCheckEn)
AddressMiss <= #Tp (~(UnicastOK | BroadcastOK | MulticastOK | (PassAll & ControlFrmAddressOK)));
end
// Hash Address Check, Multicast
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
MulticastOK <= #Tp 1'b0;
else if(RxEndFrm | RxAbort)
MulticastOK <= #Tp 1'b0;
else if(CrcHashGood & Multicast)
MulticastOK <= #Tp HashBit;
end
// Address Detection (unicast)
// start with ByteCntEq2 due to delay of addres from RxData
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
UnicastOK <= #Tp 1'b0;
else
if(RxCheckEn & ByteCntEq2)
UnicastOK <= #Tp RxData[7:0] == MAC[47:40];
else
if(RxCheckEn & ByteCntEq3)
UnicastOK <= #Tp ( RxData[7:0] == MAC[39:32]) & UnicastOK;
else
if(RxCheckEn & ByteCntEq4)
UnicastOK <= #Tp ( RxData[7:0] == MAC[31:24]) & UnicastOK;
else
if(RxCheckEn & ByteCntEq5)
UnicastOK <= #Tp ( RxData[7:0] == MAC[23:16]) & UnicastOK;
else
if(RxCheckEn & ByteCntEq6)
UnicastOK <= #Tp ( RxData[7:0] == MAC[15:8]) & UnicastOK;
else
if(RxCheckEn & ByteCntEq7)
UnicastOK <= #Tp ( RxData[7:0] == MAC[7:0]) & UnicastOK;
else
if(RxEndFrm | RxAbort)
UnicastOK <= #Tp 1'b0;
end
assign IntHash = (CrcHash[5])? HASH1 : HASH0;
always@(CrcHash or IntHash)
begin
case(CrcHash[4:3])
2'b00: ByteHash = IntHash[7:0];
2'b01: ByteHash = IntHash[15:8];
2'b10: ByteHash = IntHash[23:16];
2'b11: ByteHash = IntHash[31:24];
endcase
end
assign HashBit = ByteHash[CrcHash[2:0]];
endmodule
|
///////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description :
// / /
// /__/ /\ Filename : PCIE_2_1.uniprim.v
// \ \ / \
// \__\/\__ \
//
// Generated by : /home/chen/xfoundry/HEAD/env/Databases/CAEInterfaces/LibraryWriters/bin/ltw.pl
// Revision: 1.0
// 01/18/13 - 695630 - added drp monitor
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module PCIE_2_1 (
CFGAERECRCCHECKEN,
CFGAERECRCGENEN,
CFGAERROOTERRCORRERRRECEIVED,
CFGAERROOTERRCORRERRREPORTINGEN,
CFGAERROOTERRFATALERRRECEIVED,
CFGAERROOTERRFATALERRREPORTINGEN,
CFGAERROOTERRNONFATALERRRECEIVED,
CFGAERROOTERRNONFATALERRREPORTINGEN,
CFGBRIDGESERREN,
CFGCOMMANDBUSMASTERENABLE,
CFGCOMMANDINTERRUPTDISABLE,
CFGCOMMANDIOENABLE,
CFGCOMMANDMEMENABLE,
CFGCOMMANDSERREN,
CFGDEVCONTROL2ARIFORWARDEN,
CFGDEVCONTROL2ATOMICEGRESSBLOCK,
CFGDEVCONTROL2ATOMICREQUESTEREN,
CFGDEVCONTROL2CPLTIMEOUTDIS,
CFGDEVCONTROL2CPLTIMEOUTVAL,
CFGDEVCONTROL2IDOCPLEN,
CFGDEVCONTROL2IDOREQEN,
CFGDEVCONTROL2LTREN,
CFGDEVCONTROL2TLPPREFIXBLOCK,
CFGDEVCONTROLAUXPOWEREN,
CFGDEVCONTROLCORRERRREPORTINGEN,
CFGDEVCONTROLENABLERO,
CFGDEVCONTROLEXTTAGEN,
CFGDEVCONTROLFATALERRREPORTINGEN,
CFGDEVCONTROLMAXPAYLOAD,
CFGDEVCONTROLMAXREADREQ,
CFGDEVCONTROLNONFATALREPORTINGEN,
CFGDEVCONTROLNOSNOOPEN,
CFGDEVCONTROLPHANTOMEN,
CFGDEVCONTROLURERRREPORTINGEN,
CFGDEVSTATUSCORRERRDETECTED,
CFGDEVSTATUSFATALERRDETECTED,
CFGDEVSTATUSNONFATALERRDETECTED,
CFGDEVSTATUSURDETECTED,
CFGERRAERHEADERLOGSETN,
CFGERRCPLRDYN,
CFGINTERRUPTDO,
CFGINTERRUPTMMENABLE,
CFGINTERRUPTMSIENABLE,
CFGINTERRUPTMSIXENABLE,
CFGINTERRUPTMSIXFM,
CFGINTERRUPTRDYN,
CFGLINKCONTROLASPMCONTROL,
CFGLINKCONTROLAUTOBANDWIDTHINTEN,
CFGLINKCONTROLBANDWIDTHINTEN,
CFGLINKCONTROLCLOCKPMEN,
CFGLINKCONTROLCOMMONCLOCK,
CFGLINKCONTROLEXTENDEDSYNC,
CFGLINKCONTROLHWAUTOWIDTHDIS,
CFGLINKCONTROLLINKDISABLE,
CFGLINKCONTROLRCB,
CFGLINKCONTROLRETRAINLINK,
CFGLINKSTATUSAUTOBANDWIDTHSTATUS,
CFGLINKSTATUSBANDWIDTHSTATUS,
CFGLINKSTATUSCURRENTSPEED,
CFGLINKSTATUSDLLACTIVE,
CFGLINKSTATUSLINKTRAINING,
CFGLINKSTATUSNEGOTIATEDWIDTH,
CFGMGMTDO,
CFGMGMTRDWRDONEN,
CFGMSGDATA,
CFGMSGRECEIVED,
CFGMSGRECEIVEDASSERTINTA,
CFGMSGRECEIVEDASSERTINTB,
CFGMSGRECEIVEDASSERTINTC,
CFGMSGRECEIVEDASSERTINTD,
CFGMSGRECEIVEDDEASSERTINTA,
CFGMSGRECEIVEDDEASSERTINTB,
CFGMSGRECEIVEDDEASSERTINTC,
CFGMSGRECEIVEDDEASSERTINTD,
CFGMSGRECEIVEDERRCOR,
CFGMSGRECEIVEDERRFATAL,
CFGMSGRECEIVEDERRNONFATAL,
CFGMSGRECEIVEDPMASNAK,
CFGMSGRECEIVEDPMETO,
CFGMSGRECEIVEDPMETOACK,
CFGMSGRECEIVEDPMPME,
CFGMSGRECEIVEDSETSLOTPOWERLIMIT,
CFGMSGRECEIVEDUNLOCK,
CFGPCIELINKSTATE,
CFGPMCSRPMEEN,
CFGPMCSRPMESTATUS,
CFGPMCSRPOWERSTATE,
CFGPMRCVASREQL1N,
CFGPMRCVENTERL1N,
CFGPMRCVENTERL23N,
CFGPMRCVREQACKN,
CFGROOTCONTROLPMEINTEN,
CFGROOTCONTROLSYSERRCORRERREN,
CFGROOTCONTROLSYSERRFATALERREN,
CFGROOTCONTROLSYSERRNONFATALERREN,
CFGSLOTCONTROLELECTROMECHILCTLPULSE,
CFGTRANSACTION,
CFGTRANSACTIONADDR,
CFGTRANSACTIONTYPE,
CFGVCTCVCMAP,
DBGSCLRA,
DBGSCLRB,
DBGSCLRC,
DBGSCLRD,
DBGSCLRE,
DBGSCLRF,
DBGSCLRG,
DBGSCLRH,
DBGSCLRI,
DBGSCLRJ,
DBGSCLRK,
DBGVECA,
DBGVECB,
DBGVECC,
DRPDO,
DRPRDY,
LL2BADDLLPERR,
LL2BADTLPERR,
LL2LINKSTATUS,
LL2PROTOCOLERR,
LL2RECEIVERERR,
LL2REPLAYROERR,
LL2REPLAYTOERR,
LL2SUSPENDOK,
LL2TFCINIT1SEQ,
LL2TFCINIT2SEQ,
LL2TXIDLE,
LNKCLKEN,
MIMRXRADDR,
MIMRXREN,
MIMRXWADDR,
MIMRXWDATA,
MIMRXWEN,
MIMTXRADDR,
MIMTXREN,
MIMTXWADDR,
MIMTXWDATA,
MIMTXWEN,
PIPERX0POLARITY,
PIPERX1POLARITY,
PIPERX2POLARITY,
PIPERX3POLARITY,
PIPERX4POLARITY,
PIPERX5POLARITY,
PIPERX6POLARITY,
PIPERX7POLARITY,
PIPETX0CHARISK,
PIPETX0COMPLIANCE,
PIPETX0DATA,
PIPETX0ELECIDLE,
PIPETX0POWERDOWN,
PIPETX1CHARISK,
PIPETX1COMPLIANCE,
PIPETX1DATA,
PIPETX1ELECIDLE,
PIPETX1POWERDOWN,
PIPETX2CHARISK,
PIPETX2COMPLIANCE,
PIPETX2DATA,
PIPETX2ELECIDLE,
PIPETX2POWERDOWN,
PIPETX3CHARISK,
PIPETX3COMPLIANCE,
PIPETX3DATA,
PIPETX3ELECIDLE,
PIPETX3POWERDOWN,
PIPETX4CHARISK,
PIPETX4COMPLIANCE,
PIPETX4DATA,
PIPETX4ELECIDLE,
PIPETX4POWERDOWN,
PIPETX5CHARISK,
PIPETX5COMPLIANCE,
PIPETX5DATA,
PIPETX5ELECIDLE,
PIPETX5POWERDOWN,
PIPETX6CHARISK,
PIPETX6COMPLIANCE,
PIPETX6DATA,
PIPETX6ELECIDLE,
PIPETX6POWERDOWN,
PIPETX7CHARISK,
PIPETX7COMPLIANCE,
PIPETX7DATA,
PIPETX7ELECIDLE,
PIPETX7POWERDOWN,
PIPETXDEEMPH,
PIPETXMARGIN,
PIPETXRATE,
PIPETXRCVRDET,
PIPETXRESET,
PL2L0REQ,
PL2LINKUP,
PL2RECEIVERERR,
PL2RECOVERY,
PL2RXELECIDLE,
PL2RXPMSTATE,
PL2SUSPENDOK,
PLDBGVEC,
PLDIRECTEDCHANGEDONE,
PLINITIALLINKWIDTH,
PLLANEREVERSALMODE,
PLLINKGEN2CAP,
PLLINKPARTNERGEN2SUPPORTED,
PLLINKUPCFGCAP,
PLLTSSMSTATE,
PLPHYLNKUPN,
PLRECEIVEDHOTRST,
PLRXPMSTATE,
PLSELLNKRATE,
PLSELLNKWIDTH,
PLTXPMSTATE,
RECEIVEDFUNCLVLRSTN,
TL2ASPMSUSPENDCREDITCHECKOK,
TL2ASPMSUSPENDREQ,
TL2ERRFCPE,
TL2ERRHDR,
TL2ERRMALFORMED,
TL2ERRRXOVERFLOW,
TL2PPMSUSPENDOK,
TRNFCCPLD,
TRNFCCPLH,
TRNFCNPD,
TRNFCNPH,
TRNFCPD,
TRNFCPH,
TRNLNKUP,
TRNRBARHIT,
TRNRD,
TRNRDLLPDATA,
TRNRDLLPSRCRDY,
TRNRECRCERR,
TRNREOF,
TRNRERRFWD,
TRNRREM,
TRNRSOF,
TRNRSRCDSC,
TRNRSRCRDY,
TRNTBUFAV,
TRNTCFGREQ,
TRNTDLLPDSTRDY,
TRNTDSTRDY,
TRNTERRDROP,
USERRSTN,
CFGAERINTERRUPTMSGNUM,
CFGDEVID,
CFGDSBUSNUMBER,
CFGDSDEVICENUMBER,
CFGDSFUNCTIONNUMBER,
CFGDSN,
CFGERRACSN,
CFGERRAERHEADERLOG,
CFGERRATOMICEGRESSBLOCKEDN,
CFGERRCORN,
CFGERRCPLABORTN,
CFGERRCPLTIMEOUTN,
CFGERRCPLUNEXPECTN,
CFGERRECRCN,
CFGERRINTERNALCORN,
CFGERRINTERNALUNCORN,
CFGERRLOCKEDN,
CFGERRMALFORMEDN,
CFGERRMCBLOCKEDN,
CFGERRNORECOVERYN,
CFGERRPOISONEDN,
CFGERRPOSTEDN,
CFGERRTLPCPLHEADER,
CFGERRURN,
CFGFORCECOMMONCLOCKOFF,
CFGFORCEEXTENDEDSYNCON,
CFGFORCEMPS,
CFGINTERRUPTASSERTN,
CFGINTERRUPTDI,
CFGINTERRUPTN,
CFGINTERRUPTSTATN,
CFGMGMTBYTEENN,
CFGMGMTDI,
CFGMGMTDWADDR,
CFGMGMTRDENN,
CFGMGMTWRENN,
CFGMGMTWRREADONLYN,
CFGMGMTWRRW1CASRWN,
CFGPCIECAPINTERRUPTMSGNUM,
CFGPMFORCESTATE,
CFGPMFORCESTATEENN,
CFGPMHALTASPML0SN,
CFGPMHALTASPML1N,
CFGPMSENDPMETON,
CFGPMTURNOFFOKN,
CFGPMWAKEN,
CFGPORTNUMBER,
CFGREVID,
CFGSUBSYSID,
CFGSUBSYSVENDID,
CFGTRNPENDINGN,
CFGVENDID,
CMRSTN,
CMSTICKYRSTN,
DBGMODE,
DBGSUBMODE,
DLRSTN,
DRPADDR,
DRPCLK,
DRPDI,
DRPEN,
DRPWE,
FUNCLVLRSTN,
LL2SENDASREQL1,
LL2SENDENTERL1,
LL2SENDENTERL23,
LL2SENDPMACK,
LL2SUSPENDNOW,
LL2TLPRCV,
MIMRXRDATA,
MIMTXRDATA,
PIPECLK,
PIPERX0CHANISALIGNED,
PIPERX0CHARISK,
PIPERX0DATA,
PIPERX0ELECIDLE,
PIPERX0PHYSTATUS,
PIPERX0STATUS,
PIPERX0VALID,
PIPERX1CHANISALIGNED,
PIPERX1CHARISK,
PIPERX1DATA,
PIPERX1ELECIDLE,
PIPERX1PHYSTATUS,
PIPERX1STATUS,
PIPERX1VALID,
PIPERX2CHANISALIGNED,
PIPERX2CHARISK,
PIPERX2DATA,
PIPERX2ELECIDLE,
PIPERX2PHYSTATUS,
PIPERX2STATUS,
PIPERX2VALID,
PIPERX3CHANISALIGNED,
PIPERX3CHARISK,
PIPERX3DATA,
PIPERX3ELECIDLE,
PIPERX3PHYSTATUS,
PIPERX3STATUS,
PIPERX3VALID,
PIPERX4CHANISALIGNED,
PIPERX4CHARISK,
PIPERX4DATA,
PIPERX4ELECIDLE,
PIPERX4PHYSTATUS,
PIPERX4STATUS,
PIPERX4VALID,
PIPERX5CHANISALIGNED,
PIPERX5CHARISK,
PIPERX5DATA,
PIPERX5ELECIDLE,
PIPERX5PHYSTATUS,
PIPERX5STATUS,
PIPERX5VALID,
PIPERX6CHANISALIGNED,
PIPERX6CHARISK,
PIPERX6DATA,
PIPERX6ELECIDLE,
PIPERX6PHYSTATUS,
PIPERX6STATUS,
PIPERX6VALID,
PIPERX7CHANISALIGNED,
PIPERX7CHARISK,
PIPERX7DATA,
PIPERX7ELECIDLE,
PIPERX7PHYSTATUS,
PIPERX7STATUS,
PIPERX7VALID,
PL2DIRECTEDLSTATE,
PLDBGMODE,
PLDIRECTEDLINKAUTON,
PLDIRECTEDLINKCHANGE,
PLDIRECTEDLINKSPEED,
PLDIRECTEDLINKWIDTH,
PLDIRECTEDLTSSMNEW,
PLDIRECTEDLTSSMNEWVLD,
PLDIRECTEDLTSSMSTALL,
PLDOWNSTREAMDEEMPHSOURCE,
PLRSTN,
PLTRANSMITHOTRST,
PLUPSTREAMPREFERDEEMPH,
SYSRSTN,
TL2ASPMSUSPENDCREDITCHECK,
TL2PPMSUSPENDREQ,
TLRSTN,
TRNFCSEL,
TRNRDSTRDY,
TRNRFCPRET,
TRNRNPOK,
TRNRNPREQ,
TRNTCFGGNT,
TRNTD,
TRNTDLLPDATA,
TRNTDLLPSRCRDY,
TRNTECRCGEN,
TRNTEOF,
TRNTERRFWD,
TRNTREM,
TRNTSOF,
TRNTSRCDSC,
TRNTSRCRDY,
TRNTSTR,
USERCLK,
USERCLK2
);
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED";
`endif
parameter [11:0] AER_BASE_PTR = 12'h140;
parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE";
parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE";
parameter [15:0] AER_CAP_ID = 16'h0001;
parameter AER_CAP_MULTIHEADER = "FALSE";
parameter [11:0] AER_CAP_NEXTPTR = 12'h178;
parameter AER_CAP_ON = "FALSE";
parameter [23:0] AER_CAP_OPTIONAL_ERR_SUPPORT = 24'h000000;
parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE";
parameter [3:0] AER_CAP_VERSION = 4'h2;
parameter ALLOW_X8_GEN2 = "FALSE";
parameter [31:0] BAR0 = 32'hFFFFFF00;
parameter [31:0] BAR1 = 32'hFFFF0000;
parameter [31:0] BAR2 = 32'hFFFF000C;
parameter [31:0] BAR3 = 32'hFFFFFFFF;
parameter [31:0] BAR4 = 32'h00000000;
parameter [31:0] BAR5 = 32'h00000000;
parameter [7:0] CAPABILITIES_PTR = 8'h40;
parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000;
parameter integer CFG_ECRC_ERR_CPLSTAT = 0;
parameter [23:0] CLASS_CODE = 24'h000000;
parameter CMD_INTX_IMPLEMENTED = "TRUE";
parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE";
parameter [3:0] CPL_TIMEOUT_RANGES_SUPPORTED = 4'h0;
parameter [6:0] CRM_MODULE_RSTS = 7'h00;
parameter DEV_CAP2_ARI_FORWARDING_SUPPORTED = "FALSE";
parameter DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED = "FALSE";
parameter DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED = "FALSE";
parameter DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED = "FALSE";
parameter DEV_CAP2_CAS128_COMPLETER_SUPPORTED = "FALSE";
parameter DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED = "FALSE";
parameter DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED = "FALSE";
parameter DEV_CAP2_LTR_MECHANISM_SUPPORTED = "FALSE";
parameter [1:0] DEV_CAP2_MAX_ENDEND_TLP_PREFIXES = 2'h0;
parameter DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING = "FALSE";
parameter [1:0] DEV_CAP2_TPH_COMPLETER_SUPPORTED = 2'h0;
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE";
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE";
parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 0;
parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 0;
parameter DEV_CAP_EXT_TAG_SUPPORTED = "TRUE";
parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE";
parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2;
parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0;
parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE";
parameter integer DEV_CAP_RSVD_14_12 = 0;
parameter integer DEV_CAP_RSVD_17_16 = 0;
parameter integer DEV_CAP_RSVD_31_29 = 0;
parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE";
parameter DEV_CONTROL_EXT_TAG_DEFAULT = "FALSE";
parameter DISABLE_ASPM_L1_TIMER = "FALSE";
parameter DISABLE_BAR_FILTERING = "FALSE";
parameter DISABLE_ERR_MSG = "FALSE";
parameter DISABLE_ID_CHECK = "FALSE";
parameter DISABLE_LANE_REVERSAL = "FALSE";
parameter DISABLE_LOCKED_FILTER = "FALSE";
parameter DISABLE_PPM_FILTER = "FALSE";
parameter DISABLE_RX_POISONED_RESP = "FALSE";
parameter DISABLE_RX_TC_FILTER = "FALSE";
parameter DISABLE_SCRAMBLING = "FALSE";
parameter [7:0] DNSTREAM_LINK_NUM = 8'h00;
parameter [11:0] DSN_BASE_PTR = 12'h100;
parameter [15:0] DSN_CAP_ID = 16'h0003;
parameter [11:0] DSN_CAP_NEXTPTR = 12'h10C;
parameter DSN_CAP_ON = "TRUE";
parameter [3:0] DSN_CAP_VERSION = 4'h1;
parameter [10:0] ENABLE_MSG_ROUTE = 11'h000;
parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE";
parameter ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED = "FALSE";
parameter ENTER_RVRY_EI_L0 = "TRUE";
parameter EXIT_LOOPBACK_ON_EI = "TRUE";
parameter [31:0] EXPANSION_ROM = 32'hFFFFF001;
parameter [5:0] EXT_CFG_CAP_PTR = 6'h3F;
parameter [9:0] EXT_CFG_XP_CAP_PTR = 10'h3FF;
parameter [7:0] HEADER_TYPE = 8'h00;
parameter [4:0] INFER_EI = 5'h00;
parameter [7:0] INTERRUPT_PIN = 8'h01;
parameter INTERRUPT_STAT_AUTO = "TRUE";
parameter IS_SWITCH = "FALSE";
parameter [9:0] LAST_CONFIG_DWORD = 10'h3FF;
parameter LINK_CAP_ASPM_OPTIONALITY = "TRUE";
parameter integer LINK_CAP_ASPM_SUPPORT = 1;
parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE";
parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE";
parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7;
parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7;
parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7;
parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7;
parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7;
parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7;
parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7;
parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7;
parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE";
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1;
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08;
parameter integer LINK_CAP_RSVD_23 = 0;
parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE";
parameter integer LINK_CONTROL_RCB = 0;
parameter LINK_CTRL2_DEEMPHASIS = "FALSE";
parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE";
parameter [3:0] LINK_CTRL2_TARGET_LINK_SPEED = 4'h2;
parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE";
parameter [14:0] LL_ACK_TIMEOUT = 15'h0000;
parameter LL_ACK_TIMEOUT_EN = "FALSE";
parameter integer LL_ACK_TIMEOUT_FUNC = 0;
parameter [14:0] LL_REPLAY_TIMEOUT = 15'h0000;
parameter LL_REPLAY_TIMEOUT_EN = "FALSE";
parameter integer LL_REPLAY_TIMEOUT_FUNC = 0;
parameter [5:0] LTSSM_MAX_LINK_WIDTH = 6'h01;
parameter MPS_FORCE = "FALSE";
parameter [7:0] MSIX_BASE_PTR = 8'h9C;
parameter [7:0] MSIX_CAP_ID = 8'h11;
parameter [7:0] MSIX_CAP_NEXTPTR = 8'h00;
parameter MSIX_CAP_ON = "FALSE";
parameter integer MSIX_CAP_PBA_BIR = 0;
parameter [28:0] MSIX_CAP_PBA_OFFSET = 29'h00000050;
parameter integer MSIX_CAP_TABLE_BIR = 0;
parameter [28:0] MSIX_CAP_TABLE_OFFSET = 29'h00000040;
parameter [10:0] MSIX_CAP_TABLE_SIZE = 11'h000;
parameter [7:0] MSI_BASE_PTR = 8'h48;
parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE";
parameter [7:0] MSI_CAP_ID = 8'h05;
parameter integer MSI_CAP_MULTIMSGCAP = 0;
parameter integer MSI_CAP_MULTIMSG_EXTENSION = 0;
parameter [7:0] MSI_CAP_NEXTPTR = 8'h60;
parameter MSI_CAP_ON = "FALSE";
parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "TRUE";
parameter integer N_FTS_COMCLK_GEN1 = 255;
parameter integer N_FTS_COMCLK_GEN2 = 255;
parameter integer N_FTS_GEN1 = 255;
parameter integer N_FTS_GEN2 = 255;
parameter [7:0] PCIE_BASE_PTR = 8'h60;
parameter [7:0] PCIE_CAP_CAPABILITY_ID = 8'h10;
parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h2;
parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0;
parameter [7:0] PCIE_CAP_NEXTPTR = 8'h9C;
parameter PCIE_CAP_ON = "TRUE";
parameter integer PCIE_CAP_RSVD_15_14 = 0;
parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE";
parameter integer PCIE_REVISION = 2;
parameter integer PL_AUTO_CONFIG = 0;
parameter PL_FAST_TRAIN = "FALSE";
parameter [14:0] PM_ASPML0S_TIMEOUT = 15'h0000;
parameter PM_ASPML0S_TIMEOUT_EN = "FALSE";
parameter integer PM_ASPML0S_TIMEOUT_FUNC = 0;
parameter PM_ASPM_FASTEXIT = "FALSE";
parameter [7:0] PM_BASE_PTR = 8'h40;
parameter integer PM_CAP_AUXCURRENT = 0;
parameter PM_CAP_D1SUPPORT = "TRUE";
parameter PM_CAP_D2SUPPORT = "TRUE";
parameter PM_CAP_DSI = "FALSE";
parameter [7:0] PM_CAP_ID = 8'h01;
parameter [7:0] PM_CAP_NEXTPTR = 8'h48;
parameter PM_CAP_ON = "TRUE";
parameter [4:0] PM_CAP_PMESUPPORT = 5'h0F;
parameter PM_CAP_PME_CLOCK = "FALSE";
parameter integer PM_CAP_RSVD_04 = 0;
parameter integer PM_CAP_VERSION = 3;
parameter PM_CSR_B2B3 = "FALSE";
parameter PM_CSR_BPCCEN = "FALSE";
parameter PM_CSR_NOSOFTRST = "TRUE";
parameter [7:0] PM_DATA0 = 8'h01;
parameter [7:0] PM_DATA1 = 8'h01;
parameter [7:0] PM_DATA2 = 8'h01;
parameter [7:0] PM_DATA3 = 8'h01;
parameter [7:0] PM_DATA4 = 8'h01;
parameter [7:0] PM_DATA5 = 8'h01;
parameter [7:0] PM_DATA6 = 8'h01;
parameter [7:0] PM_DATA7 = 8'h01;
parameter [1:0] PM_DATA_SCALE0 = 2'h1;
parameter [1:0] PM_DATA_SCALE1 = 2'h1;
parameter [1:0] PM_DATA_SCALE2 = 2'h1;
parameter [1:0] PM_DATA_SCALE3 = 2'h1;
parameter [1:0] PM_DATA_SCALE4 = 2'h1;
parameter [1:0] PM_DATA_SCALE5 = 2'h1;
parameter [1:0] PM_DATA_SCALE6 = 2'h1;
parameter [1:0] PM_DATA_SCALE7 = 2'h1;
parameter PM_MF = "FALSE";
parameter [11:0] RBAR_BASE_PTR = 12'h178;
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR0 = 5'h00;
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR1 = 5'h00;
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR2 = 5'h00;
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR3 = 5'h00;
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR4 = 5'h00;
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR5 = 5'h00;
parameter [15:0] RBAR_CAP_ID = 16'h0015;
parameter [2:0] RBAR_CAP_INDEX0 = 3'h0;
parameter [2:0] RBAR_CAP_INDEX1 = 3'h0;
parameter [2:0] RBAR_CAP_INDEX2 = 3'h0;
parameter [2:0] RBAR_CAP_INDEX3 = 3'h0;
parameter [2:0] RBAR_CAP_INDEX4 = 3'h0;
parameter [2:0] RBAR_CAP_INDEX5 = 3'h0;
parameter [11:0] RBAR_CAP_NEXTPTR = 12'h000;
parameter RBAR_CAP_ON = "FALSE";
parameter [31:0] RBAR_CAP_SUP0 = 32'h00000000;
parameter [31:0] RBAR_CAP_SUP1 = 32'h00000000;
parameter [31:0] RBAR_CAP_SUP2 = 32'h00000000;
parameter [31:0] RBAR_CAP_SUP3 = 32'h00000000;
parameter [31:0] RBAR_CAP_SUP4 = 32'h00000000;
parameter [31:0] RBAR_CAP_SUP5 = 32'h00000000;
parameter [3:0] RBAR_CAP_VERSION = 4'h1;
parameter [2:0] RBAR_NUM = 3'h1;
parameter integer RECRC_CHK = 0;
parameter RECRC_CHK_TRIM = "FALSE";
parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE";
parameter [1:0] RP_AUTO_SPD = 2'h1;
parameter [4:0] RP_AUTO_SPD_LOOPCNT = 5'h1F;
parameter SELECT_DLL_IF = "FALSE";
parameter SIM_VERSION = "1.0";
parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE";
parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE";
parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE";
parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE";
parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE";
parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE";
parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE";
parameter [12:0] SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000;
parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE";
parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE";
parameter integer SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0;
parameter [7:0] SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00;
parameter integer SPARE_BIT0 = 0;
parameter integer SPARE_BIT1 = 0;
parameter integer SPARE_BIT2 = 0;
parameter integer SPARE_BIT3 = 0;
parameter integer SPARE_BIT4 = 0;
parameter integer SPARE_BIT5 = 0;
parameter integer SPARE_BIT6 = 0;
parameter integer SPARE_BIT7 = 0;
parameter integer SPARE_BIT8 = 0;
parameter [7:0] SPARE_BYTE0 = 8'h00;
parameter [7:0] SPARE_BYTE1 = 8'h00;
parameter [7:0] SPARE_BYTE2 = 8'h00;
parameter [7:0] SPARE_BYTE3 = 8'h00;
parameter [31:0] SPARE_WORD0 = 32'h00000000;
parameter [31:0] SPARE_WORD1 = 32'h00000000;
parameter [31:0] SPARE_WORD2 = 32'h00000000;
parameter [31:0] SPARE_WORD3 = 32'h00000000;
parameter SSL_MESSAGE_AUTO = "FALSE";
parameter TECRC_EP_INV = "FALSE";
parameter TL_RBYPASS = "FALSE";
parameter integer TL_RX_RAM_RADDR_LATENCY = 0;
parameter integer TL_RX_RAM_RDATA_LATENCY = 2;
parameter integer TL_RX_RAM_WRITE_LATENCY = 0;
parameter TL_TFC_DISABLE = "FALSE";
parameter TL_TX_CHECKS_DISABLE = "FALSE";
parameter integer TL_TX_RAM_RADDR_LATENCY = 0;
parameter integer TL_TX_RAM_RDATA_LATENCY = 2;
parameter integer TL_TX_RAM_WRITE_LATENCY = 0;
parameter TRN_DW = "FALSE";
parameter TRN_NP_FC = "FALSE";
parameter UPCONFIG_CAPABLE = "TRUE";
parameter UPSTREAM_FACING = "TRUE";
parameter UR_ATOMIC = "TRUE";
parameter UR_CFG1 = "TRUE";
parameter UR_INV_REQ = "TRUE";
parameter UR_PRS_RESPONSE = "TRUE";
parameter USER_CLK2_DIV2 = "FALSE";
parameter integer USER_CLK_FREQ = 3;
parameter USE_RID_PINS = "FALSE";
parameter VC0_CPL_INFINITE = "TRUE";
parameter [12:0] VC0_RX_RAM_LIMIT = 13'h03FF;
parameter integer VC0_TOTAL_CREDITS_CD = 127;
parameter integer VC0_TOTAL_CREDITS_CH = 31;
parameter integer VC0_TOTAL_CREDITS_NPD = 24;
parameter integer VC0_TOTAL_CREDITS_NPH = 12;
parameter integer VC0_TOTAL_CREDITS_PD = 288;
parameter integer VC0_TOTAL_CREDITS_PH = 32;
parameter integer VC0_TX_LASTPACKET = 31;
parameter [11:0] VC_BASE_PTR = 12'h10C;
parameter [15:0] VC_CAP_ID = 16'h0002;
parameter [11:0] VC_CAP_NEXTPTR = 12'h000;
parameter VC_CAP_ON = "FALSE";
parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE";
parameter [3:0] VC_CAP_VERSION = 4'h1;
parameter [11:0] VSEC_BASE_PTR = 12'h128;
parameter [15:0] VSEC_CAP_HDR_ID = 16'h1234;
parameter [11:0] VSEC_CAP_HDR_LENGTH = 12'h018;
parameter [3:0] VSEC_CAP_HDR_REVISION = 4'h1;
parameter [15:0] VSEC_CAP_ID = 16'h000B;
parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE";
parameter [11:0] VSEC_CAP_NEXTPTR = 12'h140;
parameter VSEC_CAP_ON = "FALSE";
parameter [3:0] VSEC_CAP_VERSION = 4'h1;
localparam in_delay = 0;
localparam out_delay = 0;
localparam INCLK_DELAY = 0;
localparam OUTCLK_DELAY = 0;
output CFGAERECRCCHECKEN;
output CFGAERECRCGENEN;
output CFGAERROOTERRCORRERRRECEIVED;
output CFGAERROOTERRCORRERRREPORTINGEN;
output CFGAERROOTERRFATALERRRECEIVED;
output CFGAERROOTERRFATALERRREPORTINGEN;
output CFGAERROOTERRNONFATALERRRECEIVED;
output CFGAERROOTERRNONFATALERRREPORTINGEN;
output CFGBRIDGESERREN;
output CFGCOMMANDBUSMASTERENABLE;
output CFGCOMMANDINTERRUPTDISABLE;
output CFGCOMMANDIOENABLE;
output CFGCOMMANDMEMENABLE;
output CFGCOMMANDSERREN;
output CFGDEVCONTROL2ARIFORWARDEN;
output CFGDEVCONTROL2ATOMICEGRESSBLOCK;
output CFGDEVCONTROL2ATOMICREQUESTEREN;
output CFGDEVCONTROL2CPLTIMEOUTDIS;
output CFGDEVCONTROL2IDOCPLEN;
output CFGDEVCONTROL2IDOREQEN;
output CFGDEVCONTROL2LTREN;
output CFGDEVCONTROL2TLPPREFIXBLOCK;
output CFGDEVCONTROLAUXPOWEREN;
output CFGDEVCONTROLCORRERRREPORTINGEN;
output CFGDEVCONTROLENABLERO;
output CFGDEVCONTROLEXTTAGEN;
output CFGDEVCONTROLFATALERRREPORTINGEN;
output CFGDEVCONTROLNONFATALREPORTINGEN;
output CFGDEVCONTROLNOSNOOPEN;
output CFGDEVCONTROLPHANTOMEN;
output CFGDEVCONTROLURERRREPORTINGEN;
output CFGDEVSTATUSCORRERRDETECTED;
output CFGDEVSTATUSFATALERRDETECTED;
output CFGDEVSTATUSNONFATALERRDETECTED;
output CFGDEVSTATUSURDETECTED;
output CFGERRAERHEADERLOGSETN;
output CFGERRCPLRDYN;
output CFGINTERRUPTMSIENABLE;
output CFGINTERRUPTMSIXENABLE;
output CFGINTERRUPTMSIXFM;
output CFGINTERRUPTRDYN;
output CFGLINKCONTROLAUTOBANDWIDTHINTEN;
output CFGLINKCONTROLBANDWIDTHINTEN;
output CFGLINKCONTROLCLOCKPMEN;
output CFGLINKCONTROLCOMMONCLOCK;
output CFGLINKCONTROLEXTENDEDSYNC;
output CFGLINKCONTROLHWAUTOWIDTHDIS;
output CFGLINKCONTROLLINKDISABLE;
output CFGLINKCONTROLRCB;
output CFGLINKCONTROLRETRAINLINK;
output CFGLINKSTATUSAUTOBANDWIDTHSTATUS;
output CFGLINKSTATUSBANDWIDTHSTATUS;
output CFGLINKSTATUSDLLACTIVE;
output CFGLINKSTATUSLINKTRAINING;
output CFGMGMTRDWRDONEN;
output CFGMSGRECEIVED;
output CFGMSGRECEIVEDASSERTINTA;
output CFGMSGRECEIVEDASSERTINTB;
output CFGMSGRECEIVEDASSERTINTC;
output CFGMSGRECEIVEDASSERTINTD;
output CFGMSGRECEIVEDDEASSERTINTA;
output CFGMSGRECEIVEDDEASSERTINTB;
output CFGMSGRECEIVEDDEASSERTINTC;
output CFGMSGRECEIVEDDEASSERTINTD;
output CFGMSGRECEIVEDERRCOR;
output CFGMSGRECEIVEDERRFATAL;
output CFGMSGRECEIVEDERRNONFATAL;
output CFGMSGRECEIVEDPMASNAK;
output CFGMSGRECEIVEDPMETO;
output CFGMSGRECEIVEDPMETOACK;
output CFGMSGRECEIVEDPMPME;
output CFGMSGRECEIVEDSETSLOTPOWERLIMIT;
output CFGMSGRECEIVEDUNLOCK;
output CFGPMCSRPMEEN;
output CFGPMCSRPMESTATUS;
output CFGPMRCVASREQL1N;
output CFGPMRCVENTERL1N;
output CFGPMRCVENTERL23N;
output CFGPMRCVREQACKN;
output CFGROOTCONTROLPMEINTEN;
output CFGROOTCONTROLSYSERRCORRERREN;
output CFGROOTCONTROLSYSERRFATALERREN;
output CFGROOTCONTROLSYSERRNONFATALERREN;
output CFGSLOTCONTROLELECTROMECHILCTLPULSE;
output CFGTRANSACTION;
output CFGTRANSACTIONTYPE;
output DBGSCLRA;
output DBGSCLRB;
output DBGSCLRC;
output DBGSCLRD;
output DBGSCLRE;
output DBGSCLRF;
output DBGSCLRG;
output DBGSCLRH;
output DBGSCLRI;
output DBGSCLRJ;
output DBGSCLRK;
output DRPRDY;
output LL2BADDLLPERR;
output LL2BADTLPERR;
output LL2PROTOCOLERR;
output LL2RECEIVERERR;
output LL2REPLAYROERR;
output LL2REPLAYTOERR;
output LL2SUSPENDOK;
output LL2TFCINIT1SEQ;
output LL2TFCINIT2SEQ;
output LL2TXIDLE;
output LNKCLKEN;
output MIMRXREN;
output MIMRXWEN;
output MIMTXREN;
output MIMTXWEN;
output PIPERX0POLARITY;
output PIPERX1POLARITY;
output PIPERX2POLARITY;
output PIPERX3POLARITY;
output PIPERX4POLARITY;
output PIPERX5POLARITY;
output PIPERX6POLARITY;
output PIPERX7POLARITY;
output PIPETX0COMPLIANCE;
output PIPETX0ELECIDLE;
output PIPETX1COMPLIANCE;
output PIPETX1ELECIDLE;
output PIPETX2COMPLIANCE;
output PIPETX2ELECIDLE;
output PIPETX3COMPLIANCE;
output PIPETX3ELECIDLE;
output PIPETX4COMPLIANCE;
output PIPETX4ELECIDLE;
output PIPETX5COMPLIANCE;
output PIPETX5ELECIDLE;
output PIPETX6COMPLIANCE;
output PIPETX6ELECIDLE;
output PIPETX7COMPLIANCE;
output PIPETX7ELECIDLE;
output PIPETXDEEMPH;
output PIPETXRATE;
output PIPETXRCVRDET;
output PIPETXRESET;
output PL2L0REQ;
output PL2LINKUP;
output PL2RECEIVERERR;
output PL2RECOVERY;
output PL2RXELECIDLE;
output PL2SUSPENDOK;
output PLDIRECTEDCHANGEDONE;
output PLLINKGEN2CAP;
output PLLINKPARTNERGEN2SUPPORTED;
output PLLINKUPCFGCAP;
output PLPHYLNKUPN;
output PLRECEIVEDHOTRST;
output PLSELLNKRATE;
output RECEIVEDFUNCLVLRSTN;
output TL2ASPMSUSPENDCREDITCHECKOK;
output TL2ASPMSUSPENDREQ;
output TL2ERRFCPE;
output TL2ERRMALFORMED;
output TL2ERRRXOVERFLOW;
output TL2PPMSUSPENDOK;
output TRNLNKUP;
output TRNRECRCERR;
output TRNREOF;
output TRNRERRFWD;
output TRNRSOF;
output TRNRSRCDSC;
output TRNRSRCRDY;
output TRNTCFGREQ;
output TRNTDLLPDSTRDY;
output TRNTERRDROP;
output USERRSTN;
output [11:0] DBGVECC;
output [11:0] PLDBGVEC;
output [11:0] TRNFCCPLD;
output [11:0] TRNFCNPD;
output [11:0] TRNFCPD;
output [127:0] TRNRD;
output [12:0] MIMRXRADDR;
output [12:0] MIMRXWADDR;
output [12:0] MIMTXRADDR;
output [12:0] MIMTXWADDR;
output [15:0] CFGMSGDATA;
output [15:0] DRPDO;
output [15:0] PIPETX0DATA;
output [15:0] PIPETX1DATA;
output [15:0] PIPETX2DATA;
output [15:0] PIPETX3DATA;
output [15:0] PIPETX4DATA;
output [15:0] PIPETX5DATA;
output [15:0] PIPETX6DATA;
output [15:0] PIPETX7DATA;
output [1:0] CFGLINKCONTROLASPMCONTROL;
output [1:0] CFGLINKSTATUSCURRENTSPEED;
output [1:0] CFGPMCSRPOWERSTATE;
output [1:0] PIPETX0CHARISK;
output [1:0] PIPETX0POWERDOWN;
output [1:0] PIPETX1CHARISK;
output [1:0] PIPETX1POWERDOWN;
output [1:0] PIPETX2CHARISK;
output [1:0] PIPETX2POWERDOWN;
output [1:0] PIPETX3CHARISK;
output [1:0] PIPETX3POWERDOWN;
output [1:0] PIPETX4CHARISK;
output [1:0] PIPETX4POWERDOWN;
output [1:0] PIPETX5CHARISK;
output [1:0] PIPETX5POWERDOWN;
output [1:0] PIPETX6CHARISK;
output [1:0] PIPETX6POWERDOWN;
output [1:0] PIPETX7CHARISK;
output [1:0] PIPETX7POWERDOWN;
output [1:0] PL2RXPMSTATE;
output [1:0] PLLANEREVERSALMODE;
output [1:0] PLRXPMSTATE;
output [1:0] PLSELLNKWIDTH;
output [1:0] TRNRDLLPSRCRDY;
output [1:0] TRNRREM;
output [2:0] CFGDEVCONTROLMAXPAYLOAD;
output [2:0] CFGDEVCONTROLMAXREADREQ;
output [2:0] CFGINTERRUPTMMENABLE;
output [2:0] CFGPCIELINKSTATE;
output [2:0] PIPETXMARGIN;
output [2:0] PLINITIALLINKWIDTH;
output [2:0] PLTXPMSTATE;
output [31:0] CFGMGMTDO;
output [3:0] CFGDEVCONTROL2CPLTIMEOUTVAL;
output [3:0] CFGLINKSTATUSNEGOTIATEDWIDTH;
output [3:0] TRNTDSTRDY;
output [4:0] LL2LINKSTATUS;
output [5:0] PLLTSSMSTATE;
output [5:0] TRNTBUFAV;
output [63:0] DBGVECA;
output [63:0] DBGVECB;
output [63:0] TL2ERRHDR;
output [63:0] TRNRDLLPDATA;
output [67:0] MIMRXWDATA;
output [68:0] MIMTXWDATA;
output [6:0] CFGTRANSACTIONADDR;
output [6:0] CFGVCTCVCMAP;
output [7:0] CFGINTERRUPTDO;
output [7:0] TRNFCCPLH;
output [7:0] TRNFCNPH;
output [7:0] TRNFCPH;
output [7:0] TRNRBARHIT;
input CFGERRACSN;
input CFGERRATOMICEGRESSBLOCKEDN;
input CFGERRCORN;
input CFGERRCPLABORTN;
input CFGERRCPLTIMEOUTN;
input CFGERRCPLUNEXPECTN;
input CFGERRECRCN;
input CFGERRINTERNALCORN;
input CFGERRINTERNALUNCORN;
input CFGERRLOCKEDN;
input CFGERRMALFORMEDN;
input CFGERRMCBLOCKEDN;
input CFGERRNORECOVERYN;
input CFGERRPOISONEDN;
input CFGERRPOSTEDN;
input CFGERRURN;
input CFGFORCECOMMONCLOCKOFF;
input CFGFORCEEXTENDEDSYNCON;
input CFGINTERRUPTASSERTN;
input CFGINTERRUPTN;
input CFGINTERRUPTSTATN;
input CFGMGMTRDENN;
input CFGMGMTWRENN;
input CFGMGMTWRREADONLYN;
input CFGMGMTWRRW1CASRWN;
input CFGPMFORCESTATEENN;
input CFGPMHALTASPML0SN;
input CFGPMHALTASPML1N;
input CFGPMSENDPMETON;
input CFGPMTURNOFFOKN;
input CFGPMWAKEN;
input CFGTRNPENDINGN;
input CMRSTN;
input CMSTICKYRSTN;
input DBGSUBMODE;
input DLRSTN;
input DRPCLK;
input DRPEN;
input DRPWE;
input FUNCLVLRSTN;
input LL2SENDASREQL1;
input LL2SENDENTERL1;
input LL2SENDENTERL23;
input LL2SENDPMACK;
input LL2SUSPENDNOW;
input LL2TLPRCV;
input PIPECLK;
input PIPERX0CHANISALIGNED;
input PIPERX0ELECIDLE;
input PIPERX0PHYSTATUS;
input PIPERX0VALID;
input PIPERX1CHANISALIGNED;
input PIPERX1ELECIDLE;
input PIPERX1PHYSTATUS;
input PIPERX1VALID;
input PIPERX2CHANISALIGNED;
input PIPERX2ELECIDLE;
input PIPERX2PHYSTATUS;
input PIPERX2VALID;
input PIPERX3CHANISALIGNED;
input PIPERX3ELECIDLE;
input PIPERX3PHYSTATUS;
input PIPERX3VALID;
input PIPERX4CHANISALIGNED;
input PIPERX4ELECIDLE;
input PIPERX4PHYSTATUS;
input PIPERX4VALID;
input PIPERX5CHANISALIGNED;
input PIPERX5ELECIDLE;
input PIPERX5PHYSTATUS;
input PIPERX5VALID;
input PIPERX6CHANISALIGNED;
input PIPERX6ELECIDLE;
input PIPERX6PHYSTATUS;
input PIPERX6VALID;
input PIPERX7CHANISALIGNED;
input PIPERX7ELECIDLE;
input PIPERX7PHYSTATUS;
input PIPERX7VALID;
input PLDIRECTEDLINKAUTON;
input PLDIRECTEDLINKSPEED;
input PLDIRECTEDLTSSMNEWVLD;
input PLDIRECTEDLTSSMSTALL;
input PLDOWNSTREAMDEEMPHSOURCE;
input PLRSTN;
input PLTRANSMITHOTRST;
input PLUPSTREAMPREFERDEEMPH;
input SYSRSTN;
input TL2ASPMSUSPENDCREDITCHECK;
input TL2PPMSUSPENDREQ;
input TLRSTN;
input TRNRDSTRDY;
input TRNRFCPRET;
input TRNRNPOK;
input TRNRNPREQ;
input TRNTCFGGNT;
input TRNTDLLPSRCRDY;
input TRNTECRCGEN;
input TRNTEOF;
input TRNTERRFWD;
input TRNTSOF;
input TRNTSRCDSC;
input TRNTSRCRDY;
input TRNTSTR;
input USERCLK2;
input USERCLK;
input [127:0] CFGERRAERHEADERLOG;
input [127:0] TRNTD;
input [15:0] CFGDEVID;
input [15:0] CFGSUBSYSID;
input [15:0] CFGSUBSYSVENDID;
input [15:0] CFGVENDID;
input [15:0] DRPDI;
input [15:0] PIPERX0DATA;
input [15:0] PIPERX1DATA;
input [15:0] PIPERX2DATA;
input [15:0] PIPERX3DATA;
input [15:0] PIPERX4DATA;
input [15:0] PIPERX5DATA;
input [15:0] PIPERX6DATA;
input [15:0] PIPERX7DATA;
input [1:0] CFGPMFORCESTATE;
input [1:0] DBGMODE;
input [1:0] PIPERX0CHARISK;
input [1:0] PIPERX1CHARISK;
input [1:0] PIPERX2CHARISK;
input [1:0] PIPERX3CHARISK;
input [1:0] PIPERX4CHARISK;
input [1:0] PIPERX5CHARISK;
input [1:0] PIPERX6CHARISK;
input [1:0] PIPERX7CHARISK;
input [1:0] PLDIRECTEDLINKCHANGE;
input [1:0] PLDIRECTEDLINKWIDTH;
input [1:0] TRNTREM;
input [2:0] CFGDSFUNCTIONNUMBER;
input [2:0] CFGFORCEMPS;
input [2:0] PIPERX0STATUS;
input [2:0] PIPERX1STATUS;
input [2:0] PIPERX2STATUS;
input [2:0] PIPERX3STATUS;
input [2:0] PIPERX4STATUS;
input [2:0] PIPERX5STATUS;
input [2:0] PIPERX6STATUS;
input [2:0] PIPERX7STATUS;
input [2:0] PLDBGMODE;
input [2:0] TRNFCSEL;
input [31:0] CFGMGMTDI;
input [31:0] TRNTDLLPDATA;
input [3:0] CFGMGMTBYTEENN;
input [47:0] CFGERRTLPCPLHEADER;
input [4:0] CFGAERINTERRUPTMSGNUM;
input [4:0] CFGDSDEVICENUMBER;
input [4:0] CFGPCIECAPINTERRUPTMSGNUM;
input [4:0] PL2DIRECTEDLSTATE;
input [5:0] PLDIRECTEDLTSSMNEW;
input [63:0] CFGDSN;
input [67:0] MIMRXRDATA;
input [68:0] MIMTXRDATA;
input [7:0] CFGDSBUSNUMBER;
input [7:0] CFGINTERRUPTDI;
input [7:0] CFGPORTNUMBER;
input [7:0] CFGREVID;
input [8:0] DRPADDR;
input [9:0] CFGMGMTDWADDR;
reg SIM_VERSION_BINARY;
reg [0:0] AER_CAP_ECRC_CHECK_CAPABLE_BINARY;
reg [0:0] AER_CAP_ECRC_GEN_CAPABLE_BINARY;
reg [0:0] AER_CAP_MULTIHEADER_BINARY;
reg [0:0] AER_CAP_ON_BINARY;
reg [0:0] AER_CAP_PERMIT_ROOTERR_UPDATE_BINARY;
reg [0:0] ALLOW_X8_GEN2_BINARY;
reg [0:0] CMD_INTX_IMPLEMENTED_BINARY;
reg [0:0] CPL_TIMEOUT_DISABLE_SUPPORTED_BINARY;
reg [0:0] DEV_CAP2_ARI_FORWARDING_SUPPORTED_BINARY;
reg [0:0] DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED_BINARY;
reg [0:0] DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED_BINARY;
reg [0:0] DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED_BINARY;
reg [0:0] DEV_CAP2_CAS128_COMPLETER_SUPPORTED_BINARY;
reg [0:0] DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED_BINARY;
reg [0:0] DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED_BINARY;
reg [0:0] DEV_CAP2_LTR_MECHANISM_SUPPORTED_BINARY;
reg [0:0] DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING_BINARY;
reg [0:0] DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE_BINARY;
reg [0:0] DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE_BINARY;
reg [0:0] DEV_CAP_EXT_TAG_SUPPORTED_BINARY;
reg [0:0] DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_BINARY;
reg [0:0] DEV_CAP_ROLE_BASED_ERROR_BINARY;
reg [0:0] DEV_CONTROL_AUX_POWER_SUPPORTED_BINARY;
reg [0:0] DEV_CONTROL_EXT_TAG_DEFAULT_BINARY;
reg [0:0] DISABLE_ASPM_L1_TIMER_BINARY;
reg [0:0] DISABLE_BAR_FILTERING_BINARY;
reg [0:0] DISABLE_ERR_MSG_BINARY;
reg [0:0] DISABLE_ID_CHECK_BINARY;
reg [0:0] DISABLE_LANE_REVERSAL_BINARY;
reg [0:0] DISABLE_LOCKED_FILTER_BINARY;
reg [0:0] DISABLE_PPM_FILTER_BINARY;
reg [0:0] DISABLE_RX_POISONED_RESP_BINARY;
reg [0:0] DISABLE_RX_TC_FILTER_BINARY;
reg [0:0] DISABLE_SCRAMBLING_BINARY;
reg [0:0] DSN_CAP_ON_BINARY;
reg [0:0] ENABLE_RX_TD_ECRC_TRIM_BINARY;
reg [0:0] ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED_BINARY;
reg [0:0] ENTER_RVRY_EI_L0_BINARY;
reg [0:0] EXIT_LOOPBACK_ON_EI_BINARY;
reg [0:0] INTERRUPT_STAT_AUTO_BINARY;
reg [0:0] IS_SWITCH_BINARY;
reg [0:0] LINK_CAP_ASPM_OPTIONALITY_BINARY;
reg [0:0] LINK_CAP_CLOCK_POWER_MANAGEMENT_BINARY;
reg [0:0] LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP_BINARY;
reg [0:0] LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_BINARY;
reg [0:0] LINK_CAP_RSVD_23_BINARY;
reg [0:0] LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE_BINARY;
reg [0:0] LINK_CONTROL_RCB_BINARY;
reg [0:0] LINK_CTRL2_DEEMPHASIS_BINARY;
reg [0:0] LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE_BINARY;
reg [0:0] LINK_STATUS_SLOT_CLOCK_CONFIG_BINARY;
reg [0:0] LL_ACK_TIMEOUT_EN_BINARY;
reg [0:0] LL_REPLAY_TIMEOUT_EN_BINARY;
reg [0:0] MPS_FORCE_BINARY;
reg [0:0] MSIX_CAP_ON_BINARY;
reg [0:0] MSI_CAP_64_BIT_ADDR_CAPABLE_BINARY;
reg [0:0] MSI_CAP_MULTIMSG_EXTENSION_BINARY;
reg [0:0] MSI_CAP_ON_BINARY;
reg [0:0] MSI_CAP_PER_VECTOR_MASKING_CAPABLE_BINARY;
reg [0:0] PCIE_CAP_ON_BINARY;
reg [0:0] PCIE_CAP_SLOT_IMPLEMENTED_BINARY;
reg [0:0] PL_FAST_TRAIN_BINARY;
reg [0:0] PM_ASPML0S_TIMEOUT_EN_BINARY;
reg [0:0] PM_ASPM_FASTEXIT_BINARY;
reg [0:0] PM_CAP_D1SUPPORT_BINARY;
reg [0:0] PM_CAP_D2SUPPORT_BINARY;
reg [0:0] PM_CAP_DSI_BINARY;
reg [0:0] PM_CAP_ON_BINARY;
reg [0:0] PM_CAP_PME_CLOCK_BINARY;
reg [0:0] PM_CAP_RSVD_04_BINARY;
reg [0:0] PM_CSR_B2B3_BINARY;
reg [0:0] PM_CSR_BPCCEN_BINARY;
reg [0:0] PM_CSR_NOSOFTRST_BINARY;
reg [0:0] PM_MF_BINARY;
reg [0:0] RBAR_CAP_ON_BINARY;
reg [0:0] RECRC_CHK_TRIM_BINARY;
reg [0:0] ROOT_CAP_CRS_SW_VISIBILITY_BINARY;
reg [0:0] SELECT_DLL_IF_BINARY;
reg [0:0] SLOT_CAP_ATT_BUTTON_PRESENT_BINARY;
reg [0:0] SLOT_CAP_ATT_INDICATOR_PRESENT_BINARY;
reg [0:0] SLOT_CAP_ELEC_INTERLOCK_PRESENT_BINARY;
reg [0:0] SLOT_CAP_HOTPLUG_CAPABLE_BINARY;
reg [0:0] SLOT_CAP_HOTPLUG_SURPRISE_BINARY;
reg [0:0] SLOT_CAP_MRL_SENSOR_PRESENT_BINARY;
reg [0:0] SLOT_CAP_NO_CMD_COMPLETED_SUPPORT_BINARY;
reg [0:0] SLOT_CAP_POWER_CONTROLLER_PRESENT_BINARY;
reg [0:0] SLOT_CAP_POWER_INDICATOR_PRESENT_BINARY;
reg [0:0] SPARE_BIT0_BINARY;
reg [0:0] SPARE_BIT1_BINARY;
reg [0:0] SPARE_BIT2_BINARY;
reg [0:0] SPARE_BIT3_BINARY;
reg [0:0] SPARE_BIT4_BINARY;
reg [0:0] SPARE_BIT5_BINARY;
reg [0:0] SPARE_BIT6_BINARY;
reg [0:0] SPARE_BIT7_BINARY;
reg [0:0] SPARE_BIT8_BINARY;
reg [0:0] SSL_MESSAGE_AUTO_BINARY;
reg [0:0] TECRC_EP_INV_BINARY;
reg [0:0] TL_RBYPASS_BINARY;
reg [0:0] TL_RX_RAM_RADDR_LATENCY_BINARY;
reg [0:0] TL_RX_RAM_WRITE_LATENCY_BINARY;
reg [0:0] TL_TFC_DISABLE_BINARY;
reg [0:0] TL_TX_CHECKS_DISABLE_BINARY;
reg [0:0] TL_TX_RAM_RADDR_LATENCY_BINARY;
reg [0:0] TL_TX_RAM_WRITE_LATENCY_BINARY;
reg [0:0] TRN_DW_BINARY;
reg [0:0] TRN_NP_FC_BINARY;
reg [0:0] UPCONFIG_CAPABLE_BINARY;
reg [0:0] UPSTREAM_FACING_BINARY;
reg [0:0] UR_ATOMIC_BINARY;
reg [0:0] UR_CFG1_BINARY;
reg [0:0] UR_INV_REQ_BINARY;
reg [0:0] UR_PRS_RESPONSE_BINARY;
reg [0:0] USER_CLK2_DIV2_BINARY;
reg [0:0] USE_RID_PINS_BINARY;
reg [0:0] VC0_CPL_INFINITE_BINARY;
reg [0:0] VC_CAP_ON_BINARY;
reg [0:0] VC_CAP_REJECT_SNOOP_TRANSACTIONS_BINARY;
reg [0:0] VSEC_CAP_IS_LINK_VISIBLE_BINARY;
reg [0:0] VSEC_CAP_ON_BINARY;
reg [10:0] VC0_TOTAL_CREDITS_CD_BINARY;
reg [10:0] VC0_TOTAL_CREDITS_NPD_BINARY;
reg [10:0] VC0_TOTAL_CREDITS_PD_BINARY;
reg [1:0] CFG_ECRC_ERR_CPLSTAT_BINARY;
reg [1:0] DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT_BINARY;
reg [1:0] DEV_CAP_RSVD_17_16_BINARY;
reg [1:0] LINK_CAP_ASPM_SUPPORT_BINARY;
reg [1:0] LL_ACK_TIMEOUT_FUNC_BINARY;
reg [1:0] LL_REPLAY_TIMEOUT_FUNC_BINARY;
reg [1:0] PCIE_CAP_RSVD_15_14_BINARY;
reg [1:0] PM_ASPML0S_TIMEOUT_FUNC_BINARY;
reg [1:0] RECRC_CHK_BINARY;
reg [1:0] SLOT_CAP_SLOT_POWER_LIMIT_SCALE_BINARY;
reg [1:0] TL_RX_RAM_RDATA_LATENCY_BINARY;
reg [1:0] TL_TX_RAM_RDATA_LATENCY_BINARY;
reg [2:0] DEV_CAP_ENDPOINT_L0S_LATENCY_BINARY;
reg [2:0] DEV_CAP_ENDPOINT_L1_LATENCY_BINARY;
reg [2:0] DEV_CAP_MAX_PAYLOAD_SUPPORTED_BINARY;
reg [2:0] DEV_CAP_RSVD_14_12_BINARY;
reg [2:0] DEV_CAP_RSVD_31_29_BINARY;
reg [2:0] LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_BINARY;
reg [2:0] LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_BINARY;
reg [2:0] LINK_CAP_L0S_EXIT_LATENCY_GEN1_BINARY;
reg [2:0] LINK_CAP_L0S_EXIT_LATENCY_GEN2_BINARY;
reg [2:0] LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_BINARY;
reg [2:0] LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_BINARY;
reg [2:0] LINK_CAP_L1_EXIT_LATENCY_GEN1_BINARY;
reg [2:0] LINK_CAP_L1_EXIT_LATENCY_GEN2_BINARY;
reg [2:0] MSIX_CAP_PBA_BIR_BINARY;
reg [2:0] MSIX_CAP_TABLE_BIR_BINARY;
reg [2:0] MSI_CAP_MULTIMSGCAP_BINARY;
reg [2:0] PL_AUTO_CONFIG_BINARY;
reg [2:0] PM_CAP_AUXCURRENT_BINARY;
reg [2:0] PM_CAP_VERSION_BINARY;
reg [2:0] USER_CLK_FREQ_BINARY;
reg [3:0] PCIE_REVISION_BINARY;
reg [4:0] VC0_TX_LASTPACKET_BINARY;
reg [6:0] VC0_TOTAL_CREDITS_CH_BINARY;
reg [6:0] VC0_TOTAL_CREDITS_NPH_BINARY;
reg [6:0] VC0_TOTAL_CREDITS_PH_BINARY;
reg [7:0] N_FTS_COMCLK_GEN1_BINARY;
reg [7:0] N_FTS_COMCLK_GEN2_BINARY;
reg [7:0] N_FTS_GEN1_BINARY;
reg [7:0] N_FTS_GEN2_BINARY;
// tri0 GSR = glbl.GSR;
reg notifier;
initial begin
case (AER_CAP_ECRC_CHECK_CAPABLE)
"FALSE" : AER_CAP_ECRC_CHECK_CAPABLE_BINARY = 1'b0;
"TRUE" : AER_CAP_ECRC_CHECK_CAPABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute AER_CAP_ECRC_CHECK_CAPABLE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", AER_CAP_ECRC_CHECK_CAPABLE);
#1 $finish;
end
endcase
case (AER_CAP_ECRC_GEN_CAPABLE)
"FALSE" : AER_CAP_ECRC_GEN_CAPABLE_BINARY = 1'b0;
"TRUE" : AER_CAP_ECRC_GEN_CAPABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute AER_CAP_ECRC_GEN_CAPABLE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", AER_CAP_ECRC_GEN_CAPABLE);
#1 $finish;
end
endcase
case (AER_CAP_MULTIHEADER)
"FALSE" : AER_CAP_MULTIHEADER_BINARY = 1'b0;
"TRUE" : AER_CAP_MULTIHEADER_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute AER_CAP_MULTIHEADER on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", AER_CAP_MULTIHEADER);
#1 $finish;
end
endcase
case (AER_CAP_ON)
"FALSE" : AER_CAP_ON_BINARY = 1'b0;
"TRUE" : AER_CAP_ON_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute AER_CAP_ON on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", AER_CAP_ON);
#1 $finish;
end
endcase
case (AER_CAP_PERMIT_ROOTERR_UPDATE)
"TRUE" : AER_CAP_PERMIT_ROOTERR_UPDATE_BINARY = 1'b1;
"FALSE" : AER_CAP_PERMIT_ROOTERR_UPDATE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute AER_CAP_PERMIT_ROOTERR_UPDATE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", AER_CAP_PERMIT_ROOTERR_UPDATE);
#1 $finish;
end
endcase
case (ALLOW_X8_GEN2)
"FALSE" : ALLOW_X8_GEN2_BINARY = 1'b0;
"TRUE" : ALLOW_X8_GEN2_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute ALLOW_X8_GEN2 on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", ALLOW_X8_GEN2);
#1 $finish;
end
endcase
case (CMD_INTX_IMPLEMENTED)
"TRUE" : CMD_INTX_IMPLEMENTED_BINARY = 1'b1;
"FALSE" : CMD_INTX_IMPLEMENTED_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute CMD_INTX_IMPLEMENTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", CMD_INTX_IMPLEMENTED);
#1 $finish;
end
endcase
case (CPL_TIMEOUT_DISABLE_SUPPORTED)
"FALSE" : CPL_TIMEOUT_DISABLE_SUPPORTED_BINARY = 1'b0;
"TRUE" : CPL_TIMEOUT_DISABLE_SUPPORTED_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute CPL_TIMEOUT_DISABLE_SUPPORTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", CPL_TIMEOUT_DISABLE_SUPPORTED);
#1 $finish;
end
endcase
case (DEV_CAP2_ARI_FORWARDING_SUPPORTED)
"FALSE" : DEV_CAP2_ARI_FORWARDING_SUPPORTED_BINARY = 1'b0;
"TRUE" : DEV_CAP2_ARI_FORWARDING_SUPPORTED_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DEV_CAP2_ARI_FORWARDING_SUPPORTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DEV_CAP2_ARI_FORWARDING_SUPPORTED);
#1 $finish;
end
endcase
case (DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED)
"FALSE" : DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED_BINARY = 1'b0;
"TRUE" : DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED);
#1 $finish;
end
endcase
case (DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED)
"FALSE" : DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED_BINARY = 1'b0;
"TRUE" : DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED);
#1 $finish;
end
endcase
case (DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED)
"FALSE" : DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED_BINARY = 1'b0;
"TRUE" : DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED);
#1 $finish;
end
endcase
case (DEV_CAP2_CAS128_COMPLETER_SUPPORTED)
"FALSE" : DEV_CAP2_CAS128_COMPLETER_SUPPORTED_BINARY = 1'b0;
"TRUE" : DEV_CAP2_CAS128_COMPLETER_SUPPORTED_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DEV_CAP2_CAS128_COMPLETER_SUPPORTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DEV_CAP2_CAS128_COMPLETER_SUPPORTED);
#1 $finish;
end
endcase
case (DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED)
"FALSE" : DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED_BINARY = 1'b0;
"TRUE" : DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED);
#1 $finish;
end
endcase
case (DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED)
"FALSE" : DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED_BINARY = 1'b0;
"TRUE" : DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED);
#1 $finish;
end
endcase
case (DEV_CAP2_LTR_MECHANISM_SUPPORTED)
"FALSE" : DEV_CAP2_LTR_MECHANISM_SUPPORTED_BINARY = 1'b0;
"TRUE" : DEV_CAP2_LTR_MECHANISM_SUPPORTED_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DEV_CAP2_LTR_MECHANISM_SUPPORTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DEV_CAP2_LTR_MECHANISM_SUPPORTED);
#1 $finish;
end
endcase
case (DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING)
"FALSE" : DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING_BINARY = 1'b0;
"TRUE" : DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING);
#1 $finish;
end
endcase
case (DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE)
"TRUE" : DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE_BINARY = 1'b1;
"FALSE" : DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE);
#1 $finish;
end
endcase
case (DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE)
"TRUE" : DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE_BINARY = 1'b1;
"FALSE" : DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE);
#1 $finish;
end
endcase
case (DEV_CAP_EXT_TAG_SUPPORTED)
"TRUE" : DEV_CAP_EXT_TAG_SUPPORTED_BINARY = 1'b1;
"FALSE" : DEV_CAP_EXT_TAG_SUPPORTED_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute DEV_CAP_EXT_TAG_SUPPORTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DEV_CAP_EXT_TAG_SUPPORTED);
#1 $finish;
end
endcase
case (DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE)
"FALSE" : DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_BINARY = 1'b0;
"TRUE" : DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE);
#1 $finish;
end
endcase
case (DEV_CAP_ROLE_BASED_ERROR)
"TRUE" : DEV_CAP_ROLE_BASED_ERROR_BINARY = 1'b1;
"FALSE" : DEV_CAP_ROLE_BASED_ERROR_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute DEV_CAP_ROLE_BASED_ERROR on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DEV_CAP_ROLE_BASED_ERROR);
#1 $finish;
end
endcase
case (DEV_CONTROL_AUX_POWER_SUPPORTED)
"FALSE" : DEV_CONTROL_AUX_POWER_SUPPORTED_BINARY = 1'b0;
"TRUE" : DEV_CONTROL_AUX_POWER_SUPPORTED_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DEV_CONTROL_AUX_POWER_SUPPORTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DEV_CONTROL_AUX_POWER_SUPPORTED);
#1 $finish;
end
endcase
case (DEV_CONTROL_EXT_TAG_DEFAULT)
"FALSE" : DEV_CONTROL_EXT_TAG_DEFAULT_BINARY = 1'b0;
"TRUE" : DEV_CONTROL_EXT_TAG_DEFAULT_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DEV_CONTROL_EXT_TAG_DEFAULT on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DEV_CONTROL_EXT_TAG_DEFAULT);
#1 $finish;
end
endcase
case (DISABLE_ASPM_L1_TIMER)
"FALSE" : DISABLE_ASPM_L1_TIMER_BINARY = 1'b0;
"TRUE" : DISABLE_ASPM_L1_TIMER_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DISABLE_ASPM_L1_TIMER on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DISABLE_ASPM_L1_TIMER);
#1 $finish;
end
endcase
case (DISABLE_BAR_FILTERING)
"FALSE" : DISABLE_BAR_FILTERING_BINARY = 1'b0;
"TRUE" : DISABLE_BAR_FILTERING_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DISABLE_BAR_FILTERING on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DISABLE_BAR_FILTERING);
#1 $finish;
end
endcase
case (DISABLE_ERR_MSG)
"FALSE" : DISABLE_ERR_MSG_BINARY = 1'b0;
"TRUE" : DISABLE_ERR_MSG_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DISABLE_ERR_MSG on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DISABLE_ERR_MSG);
#1 $finish;
end
endcase
case (DISABLE_ID_CHECK)
"FALSE" : DISABLE_ID_CHECK_BINARY = 1'b0;
"TRUE" : DISABLE_ID_CHECK_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DISABLE_ID_CHECK on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DISABLE_ID_CHECK);
#1 $finish;
end
endcase
case (DISABLE_LANE_REVERSAL)
"FALSE" : DISABLE_LANE_REVERSAL_BINARY = 1'b0;
"TRUE" : DISABLE_LANE_REVERSAL_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DISABLE_LANE_REVERSAL on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DISABLE_LANE_REVERSAL);
#1 $finish;
end
endcase
case (DISABLE_LOCKED_FILTER)
"FALSE" : DISABLE_LOCKED_FILTER_BINARY = 1'b0;
"TRUE" : DISABLE_LOCKED_FILTER_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DISABLE_LOCKED_FILTER on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DISABLE_LOCKED_FILTER);
#1 $finish;
end
endcase
case (DISABLE_PPM_FILTER)
"FALSE" : DISABLE_PPM_FILTER_BINARY = 1'b0;
"TRUE" : DISABLE_PPM_FILTER_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DISABLE_PPM_FILTER on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DISABLE_PPM_FILTER);
#1 $finish;
end
endcase
case (DISABLE_RX_POISONED_RESP)
"FALSE" : DISABLE_RX_POISONED_RESP_BINARY = 1'b0;
"TRUE" : DISABLE_RX_POISONED_RESP_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DISABLE_RX_POISONED_RESP on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DISABLE_RX_POISONED_RESP);
#1 $finish;
end
endcase
case (DISABLE_RX_TC_FILTER)
"FALSE" : DISABLE_RX_TC_FILTER_BINARY = 1'b0;
"TRUE" : DISABLE_RX_TC_FILTER_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DISABLE_RX_TC_FILTER on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DISABLE_RX_TC_FILTER);
#1 $finish;
end
endcase
case (DISABLE_SCRAMBLING)
"FALSE" : DISABLE_SCRAMBLING_BINARY = 1'b0;
"TRUE" : DISABLE_SCRAMBLING_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute DISABLE_SCRAMBLING on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", DISABLE_SCRAMBLING);
#1 $finish;
end
endcase
case (DSN_CAP_ON)
"TRUE" : DSN_CAP_ON_BINARY = 1'b1;
"FALSE" : DSN_CAP_ON_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute DSN_CAP_ON on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", DSN_CAP_ON);
#1 $finish;
end
endcase
case (ENABLE_RX_TD_ECRC_TRIM)
"FALSE" : ENABLE_RX_TD_ECRC_TRIM_BINARY = 1'b0;
"TRUE" : ENABLE_RX_TD_ECRC_TRIM_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute ENABLE_RX_TD_ECRC_TRIM on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", ENABLE_RX_TD_ECRC_TRIM);
#1 $finish;
end
endcase
case (ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED)
"FALSE" : ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED_BINARY = 1'b0;
"TRUE" : ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED);
#1 $finish;
end
endcase
case (ENTER_RVRY_EI_L0)
"TRUE" : ENTER_RVRY_EI_L0_BINARY = 1'b1;
"FALSE" : ENTER_RVRY_EI_L0_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute ENTER_RVRY_EI_L0 on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", ENTER_RVRY_EI_L0);
#1 $finish;
end
endcase
case (EXIT_LOOPBACK_ON_EI)
"TRUE" : EXIT_LOOPBACK_ON_EI_BINARY = 1'b1;
"FALSE" : EXIT_LOOPBACK_ON_EI_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute EXIT_LOOPBACK_ON_EI on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", EXIT_LOOPBACK_ON_EI);
#1 $finish;
end
endcase
case (INTERRUPT_STAT_AUTO)
"TRUE" : INTERRUPT_STAT_AUTO_BINARY = 1'b1;
"FALSE" : INTERRUPT_STAT_AUTO_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute INTERRUPT_STAT_AUTO on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", INTERRUPT_STAT_AUTO);
#1 $finish;
end
endcase
case (IS_SWITCH)
"FALSE" : IS_SWITCH_BINARY = 1'b0;
"TRUE" : IS_SWITCH_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute IS_SWITCH on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", IS_SWITCH);
#1 $finish;
end
endcase
case (LINK_CAP_ASPM_OPTIONALITY)
"TRUE" : LINK_CAP_ASPM_OPTIONALITY_BINARY = 1'b1;
"FALSE" : LINK_CAP_ASPM_OPTIONALITY_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute LINK_CAP_ASPM_OPTIONALITY on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", LINK_CAP_ASPM_OPTIONALITY);
#1 $finish;
end
endcase
case (LINK_CAP_CLOCK_POWER_MANAGEMENT)
"FALSE" : LINK_CAP_CLOCK_POWER_MANAGEMENT_BINARY = 1'b0;
"TRUE" : LINK_CAP_CLOCK_POWER_MANAGEMENT_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute LINK_CAP_CLOCK_POWER_MANAGEMENT on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LINK_CAP_CLOCK_POWER_MANAGEMENT);
#1 $finish;
end
endcase
case (LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP)
"FALSE" : LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP_BINARY = 1'b0;
"TRUE" : LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP);
#1 $finish;
end
endcase
case (LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP)
"FALSE" : LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_BINARY = 1'b0;
"TRUE" : LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP);
#1 $finish;
end
endcase
case (LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE)
"FALSE" : LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE_BINARY = 1'b0;
"TRUE" : LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE);
#1 $finish;
end
endcase
case (LINK_CTRL2_DEEMPHASIS)
"FALSE" : LINK_CTRL2_DEEMPHASIS_BINARY = 1'b0;
"TRUE" : LINK_CTRL2_DEEMPHASIS_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute LINK_CTRL2_DEEMPHASIS on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LINK_CTRL2_DEEMPHASIS);
#1 $finish;
end
endcase
case (LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE)
"FALSE" : LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE_BINARY = 1'b0;
"TRUE" : LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE);
#1 $finish;
end
endcase
case (LINK_STATUS_SLOT_CLOCK_CONFIG)
"TRUE" : LINK_STATUS_SLOT_CLOCK_CONFIG_BINARY = 1'b1;
"FALSE" : LINK_STATUS_SLOT_CLOCK_CONFIG_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute LINK_STATUS_SLOT_CLOCK_CONFIG on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", LINK_STATUS_SLOT_CLOCK_CONFIG);
#1 $finish;
end
endcase
case (LL_ACK_TIMEOUT_EN)
"FALSE" : LL_ACK_TIMEOUT_EN_BINARY = 1'b0;
"TRUE" : LL_ACK_TIMEOUT_EN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute LL_ACK_TIMEOUT_EN on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LL_ACK_TIMEOUT_EN);
#1 $finish;
end
endcase
case (LL_REPLAY_TIMEOUT_EN)
"FALSE" : LL_REPLAY_TIMEOUT_EN_BINARY = 1'b0;
"TRUE" : LL_REPLAY_TIMEOUT_EN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute LL_REPLAY_TIMEOUT_EN on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LL_REPLAY_TIMEOUT_EN);
#1 $finish;
end
endcase
case (MPS_FORCE)
"FALSE" : MPS_FORCE_BINARY = 1'b0;
"TRUE" : MPS_FORCE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute MPS_FORCE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", MPS_FORCE);
#1 $finish;
end
endcase
case (MSIX_CAP_ON)
"FALSE" : MSIX_CAP_ON_BINARY = 1'b0;
"TRUE" : MSIX_CAP_ON_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute MSIX_CAP_ON on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", MSIX_CAP_ON);
#1 $finish;
end
endcase
case (MSI_CAP_64_BIT_ADDR_CAPABLE)
"TRUE" : MSI_CAP_64_BIT_ADDR_CAPABLE_BINARY = 1'b1;
"FALSE" : MSI_CAP_64_BIT_ADDR_CAPABLE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute MSI_CAP_64_BIT_ADDR_CAPABLE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", MSI_CAP_64_BIT_ADDR_CAPABLE);
#1 $finish;
end
endcase
case (MSI_CAP_ON)
"FALSE" : MSI_CAP_ON_BINARY = 1'b0;
"TRUE" : MSI_CAP_ON_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute MSI_CAP_ON on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", MSI_CAP_ON);
#1 $finish;
end
endcase
case (MSI_CAP_PER_VECTOR_MASKING_CAPABLE)
"TRUE" : MSI_CAP_PER_VECTOR_MASKING_CAPABLE_BINARY = 1'b1;
"FALSE" : MSI_CAP_PER_VECTOR_MASKING_CAPABLE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute MSI_CAP_PER_VECTOR_MASKING_CAPABLE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", MSI_CAP_PER_VECTOR_MASKING_CAPABLE);
#1 $finish;
end
endcase
case (PCIE_CAP_ON)
"TRUE" : PCIE_CAP_ON_BINARY = 1'b1;
"FALSE" : PCIE_CAP_ON_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PCIE_CAP_ON on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PCIE_CAP_ON);
#1 $finish;
end
endcase
case (PCIE_CAP_SLOT_IMPLEMENTED)
"FALSE" : PCIE_CAP_SLOT_IMPLEMENTED_BINARY = 1'b0;
"TRUE" : PCIE_CAP_SLOT_IMPLEMENTED_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PCIE_CAP_SLOT_IMPLEMENTED on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PCIE_CAP_SLOT_IMPLEMENTED);
#1 $finish;
end
endcase
case (PL_FAST_TRAIN)
"FALSE" : PL_FAST_TRAIN_BINARY = 1'b0;
"TRUE" : PL_FAST_TRAIN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PL_FAST_TRAIN on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PL_FAST_TRAIN);
#1 $finish;
end
endcase
case (PM_ASPML0S_TIMEOUT_EN)
"FALSE" : PM_ASPML0S_TIMEOUT_EN_BINARY = 1'b0;
"TRUE" : PM_ASPML0S_TIMEOUT_EN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PM_ASPML0S_TIMEOUT_EN on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PM_ASPML0S_TIMEOUT_EN);
#1 $finish;
end
endcase
case (PM_ASPM_FASTEXIT)
"FALSE" : PM_ASPM_FASTEXIT_BINARY = 1'b0;
"TRUE" : PM_ASPM_FASTEXIT_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PM_ASPM_FASTEXIT on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PM_ASPM_FASTEXIT);
#1 $finish;
end
endcase
case (PM_CAP_D1SUPPORT)
"TRUE" : PM_CAP_D1SUPPORT_BINARY = 1'b1;
"FALSE" : PM_CAP_D1SUPPORT_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PM_CAP_D1SUPPORT on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PM_CAP_D1SUPPORT);
#1 $finish;
end
endcase
case (PM_CAP_D2SUPPORT)
"TRUE" : PM_CAP_D2SUPPORT_BINARY = 1'b1;
"FALSE" : PM_CAP_D2SUPPORT_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PM_CAP_D2SUPPORT on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PM_CAP_D2SUPPORT);
#1 $finish;
end
endcase
case (PM_CAP_DSI)
"FALSE" : PM_CAP_DSI_BINARY = 1'b0;
"TRUE" : PM_CAP_DSI_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PM_CAP_DSI on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PM_CAP_DSI);
#1 $finish;
end
endcase
case (PM_CAP_ON)
"TRUE" : PM_CAP_ON_BINARY = 1'b1;
"FALSE" : PM_CAP_ON_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PM_CAP_ON on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PM_CAP_ON);
#1 $finish;
end
endcase
case (PM_CAP_PME_CLOCK)
"FALSE" : PM_CAP_PME_CLOCK_BINARY = 1'b0;
"TRUE" : PM_CAP_PME_CLOCK_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PM_CAP_PME_CLOCK on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PM_CAP_PME_CLOCK);
#1 $finish;
end
endcase
case (PM_CSR_B2B3)
"FALSE" : PM_CSR_B2B3_BINARY = 1'b0;
"TRUE" : PM_CSR_B2B3_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PM_CSR_B2B3 on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PM_CSR_B2B3);
#1 $finish;
end
endcase
case (PM_CSR_BPCCEN)
"FALSE" : PM_CSR_BPCCEN_BINARY = 1'b0;
"TRUE" : PM_CSR_BPCCEN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PM_CSR_BPCCEN on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PM_CSR_BPCCEN);
#1 $finish;
end
endcase
case (PM_CSR_NOSOFTRST)
"TRUE" : PM_CSR_NOSOFTRST_BINARY = 1'b1;
"FALSE" : PM_CSR_NOSOFTRST_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PM_CSR_NOSOFTRST on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PM_CSR_NOSOFTRST);
#1 $finish;
end
endcase
case (PM_MF)
"FALSE" : PM_MF_BINARY = 1'b0;
"TRUE" : PM_MF_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PM_MF on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PM_MF);
#1 $finish;
end
endcase
case (RBAR_CAP_ON)
"FALSE" : RBAR_CAP_ON_BINARY = 1'b0;
"TRUE" : RBAR_CAP_ON_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute RBAR_CAP_ON on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", RBAR_CAP_ON);
#1 $finish;
end
endcase
case (RECRC_CHK_TRIM)
"FALSE" : RECRC_CHK_TRIM_BINARY = 1'b0;
"TRUE" : RECRC_CHK_TRIM_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute RECRC_CHK_TRIM on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", RECRC_CHK_TRIM);
#1 $finish;
end
endcase
case (ROOT_CAP_CRS_SW_VISIBILITY)
"FALSE" : ROOT_CAP_CRS_SW_VISIBILITY_BINARY = 1'b0;
"TRUE" : ROOT_CAP_CRS_SW_VISIBILITY_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute ROOT_CAP_CRS_SW_VISIBILITY on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", ROOT_CAP_CRS_SW_VISIBILITY);
#1 $finish;
end
endcase
case (SELECT_DLL_IF)
"FALSE" : SELECT_DLL_IF_BINARY = 1'b0;
"TRUE" : SELECT_DLL_IF_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute SELECT_DLL_IF on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", SELECT_DLL_IF);
#1 $finish;
end
endcase
case (SIM_VERSION)
"1.0" : SIM_VERSION_BINARY = 0;
"1.1" : SIM_VERSION_BINARY = 0;
"1.2" : SIM_VERSION_BINARY = 0;
"1.3" : SIM_VERSION_BINARY = 0;
"2.0" : SIM_VERSION_BINARY = 0;
"3.0" : SIM_VERSION_BINARY = 0;
"4.0" : SIM_VERSION_BINARY = 0;
default : begin
$display("Attribute Syntax Error : The Attribute SIM_VERSION on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are 1.0, 1.1, 1.2, 1.3, 2.0, 3.0, or 4.0.", SIM_VERSION);
#1 $finish;
end
endcase
case (SLOT_CAP_ATT_BUTTON_PRESENT)
"FALSE" : SLOT_CAP_ATT_BUTTON_PRESENT_BINARY = 1'b0;
"TRUE" : SLOT_CAP_ATT_BUTTON_PRESENT_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute SLOT_CAP_ATT_BUTTON_PRESENT on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", SLOT_CAP_ATT_BUTTON_PRESENT);
#1 $finish;
end
endcase
case (SLOT_CAP_ATT_INDICATOR_PRESENT)
"FALSE" : SLOT_CAP_ATT_INDICATOR_PRESENT_BINARY = 1'b0;
"TRUE" : SLOT_CAP_ATT_INDICATOR_PRESENT_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute SLOT_CAP_ATT_INDICATOR_PRESENT on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", SLOT_CAP_ATT_INDICATOR_PRESENT);
#1 $finish;
end
endcase
case (SLOT_CAP_ELEC_INTERLOCK_PRESENT)
"FALSE" : SLOT_CAP_ELEC_INTERLOCK_PRESENT_BINARY = 1'b0;
"TRUE" : SLOT_CAP_ELEC_INTERLOCK_PRESENT_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute SLOT_CAP_ELEC_INTERLOCK_PRESENT on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", SLOT_CAP_ELEC_INTERLOCK_PRESENT);
#1 $finish;
end
endcase
case (SLOT_CAP_HOTPLUG_CAPABLE)
"FALSE" : SLOT_CAP_HOTPLUG_CAPABLE_BINARY = 1'b0;
"TRUE" : SLOT_CAP_HOTPLUG_CAPABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute SLOT_CAP_HOTPLUG_CAPABLE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", SLOT_CAP_HOTPLUG_CAPABLE);
#1 $finish;
end
endcase
case (SLOT_CAP_HOTPLUG_SURPRISE)
"FALSE" : SLOT_CAP_HOTPLUG_SURPRISE_BINARY = 1'b0;
"TRUE" : SLOT_CAP_HOTPLUG_SURPRISE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute SLOT_CAP_HOTPLUG_SURPRISE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", SLOT_CAP_HOTPLUG_SURPRISE);
#1 $finish;
end
endcase
case (SLOT_CAP_MRL_SENSOR_PRESENT)
"FALSE" : SLOT_CAP_MRL_SENSOR_PRESENT_BINARY = 1'b0;
"TRUE" : SLOT_CAP_MRL_SENSOR_PRESENT_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute SLOT_CAP_MRL_SENSOR_PRESENT on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", SLOT_CAP_MRL_SENSOR_PRESENT);
#1 $finish;
end
endcase
case (SLOT_CAP_NO_CMD_COMPLETED_SUPPORT)
"FALSE" : SLOT_CAP_NO_CMD_COMPLETED_SUPPORT_BINARY = 1'b0;
"TRUE" : SLOT_CAP_NO_CMD_COMPLETED_SUPPORT_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute SLOT_CAP_NO_CMD_COMPLETED_SUPPORT on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", SLOT_CAP_NO_CMD_COMPLETED_SUPPORT);
#1 $finish;
end
endcase
case (SLOT_CAP_POWER_CONTROLLER_PRESENT)
"FALSE" : SLOT_CAP_POWER_CONTROLLER_PRESENT_BINARY = 1'b0;
"TRUE" : SLOT_CAP_POWER_CONTROLLER_PRESENT_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute SLOT_CAP_POWER_CONTROLLER_PRESENT on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", SLOT_CAP_POWER_CONTROLLER_PRESENT);
#1 $finish;
end
endcase
case (SLOT_CAP_POWER_INDICATOR_PRESENT)
"FALSE" : SLOT_CAP_POWER_INDICATOR_PRESENT_BINARY = 1'b0;
"TRUE" : SLOT_CAP_POWER_INDICATOR_PRESENT_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute SLOT_CAP_POWER_INDICATOR_PRESENT on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", SLOT_CAP_POWER_INDICATOR_PRESENT);
#1 $finish;
end
endcase
case (SSL_MESSAGE_AUTO)
"FALSE" : SSL_MESSAGE_AUTO_BINARY = 1'b0;
"TRUE" : SSL_MESSAGE_AUTO_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute SSL_MESSAGE_AUTO on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", SSL_MESSAGE_AUTO);
#1 $finish;
end
endcase
case (TECRC_EP_INV)
"FALSE" : TECRC_EP_INV_BINARY = 1'b0;
"TRUE" : TECRC_EP_INV_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute TECRC_EP_INV on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TECRC_EP_INV);
#1 $finish;
end
endcase
case (TL_RBYPASS)
"FALSE" : TL_RBYPASS_BINARY = 1'b0;
"TRUE" : TL_RBYPASS_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute TL_RBYPASS on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TL_RBYPASS);
#1 $finish;
end
endcase
case (TL_TFC_DISABLE)
"FALSE" : TL_TFC_DISABLE_BINARY = 1'b0;
"TRUE" : TL_TFC_DISABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute TL_TFC_DISABLE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TL_TFC_DISABLE);
#1 $finish;
end
endcase
case (TL_TX_CHECKS_DISABLE)
"FALSE" : TL_TX_CHECKS_DISABLE_BINARY = 1'b0;
"TRUE" : TL_TX_CHECKS_DISABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute TL_TX_CHECKS_DISABLE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TL_TX_CHECKS_DISABLE);
#1 $finish;
end
endcase
case (TRN_DW)
"FALSE" : TRN_DW_BINARY = 1'b0;
"TRUE" : TRN_DW_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute TRN_DW on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TRN_DW);
#1 $finish;
end
endcase
case (TRN_NP_FC)
"FALSE" : TRN_NP_FC_BINARY = 1'b0;
"TRUE" : TRN_NP_FC_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute TRN_NP_FC on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TRN_NP_FC);
#1 $finish;
end
endcase
case (UPCONFIG_CAPABLE)
"TRUE" : UPCONFIG_CAPABLE_BINARY = 1'b1;
"FALSE" : UPCONFIG_CAPABLE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute UPCONFIG_CAPABLE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", UPCONFIG_CAPABLE);
#1 $finish;
end
endcase
case (UPSTREAM_FACING)
"TRUE" : UPSTREAM_FACING_BINARY = 1'b1;
"FALSE" : UPSTREAM_FACING_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute UPSTREAM_FACING on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", UPSTREAM_FACING);
#1 $finish;
end
endcase
case (UR_ATOMIC)
"TRUE" : UR_ATOMIC_BINARY = 1'b1;
"FALSE" : UR_ATOMIC_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute UR_ATOMIC on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", UR_ATOMIC);
#1 $finish;
end
endcase
case (UR_CFG1)
"TRUE" : UR_CFG1_BINARY = 1'b1;
"FALSE" : UR_CFG1_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute UR_CFG1 on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", UR_CFG1);
#1 $finish;
end
endcase
case (UR_INV_REQ)
"TRUE" : UR_INV_REQ_BINARY = 1'b1;
"FALSE" : UR_INV_REQ_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute UR_INV_REQ on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", UR_INV_REQ);
#1 $finish;
end
endcase
case (UR_PRS_RESPONSE)
"TRUE" : UR_PRS_RESPONSE_BINARY = 1'b1;
"FALSE" : UR_PRS_RESPONSE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute UR_PRS_RESPONSE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", UR_PRS_RESPONSE);
#1 $finish;
end
endcase
case (USER_CLK2_DIV2)
"FALSE" : USER_CLK2_DIV2_BINARY = 1'b0;
"TRUE" : USER_CLK2_DIV2_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute USER_CLK2_DIV2 on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", USER_CLK2_DIV2);
#1 $finish;
end
endcase
case (USE_RID_PINS)
"FALSE" : USE_RID_PINS_BINARY = 1'b0;
"TRUE" : USE_RID_PINS_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute USE_RID_PINS on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", USE_RID_PINS);
#1 $finish;
end
endcase
case (VC0_CPL_INFINITE)
"TRUE" : VC0_CPL_INFINITE_BINARY = 1'b1;
"FALSE" : VC0_CPL_INFINITE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute VC0_CPL_INFINITE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VC0_CPL_INFINITE);
#1 $finish;
end
endcase
case (VC_CAP_ON)
"FALSE" : VC_CAP_ON_BINARY = 1'b0;
"TRUE" : VC_CAP_ON_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute VC_CAP_ON on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", VC_CAP_ON);
#1 $finish;
end
endcase
case (VC_CAP_REJECT_SNOOP_TRANSACTIONS)
"FALSE" : VC_CAP_REJECT_SNOOP_TRANSACTIONS_BINARY = 1'b0;
"TRUE" : VC_CAP_REJECT_SNOOP_TRANSACTIONS_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute VC_CAP_REJECT_SNOOP_TRANSACTIONS on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", VC_CAP_REJECT_SNOOP_TRANSACTIONS);
#1 $finish;
end
endcase
case (VSEC_CAP_IS_LINK_VISIBLE)
"TRUE" : VSEC_CAP_IS_LINK_VISIBLE_BINARY = 1'b1;
"FALSE" : VSEC_CAP_IS_LINK_VISIBLE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute VSEC_CAP_IS_LINK_VISIBLE on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VSEC_CAP_IS_LINK_VISIBLE);
#1 $finish;
end
endcase
case (VSEC_CAP_ON)
"FALSE" : VSEC_CAP_ON_BINARY = 1'b0;
"TRUE" : VSEC_CAP_ON_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute VSEC_CAP_ON on X_PCIE_2_1 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", VSEC_CAP_ON);
#1 $finish;
end
endcase
if ((CFG_ECRC_ERR_CPLSTAT >= 0) && (CFG_ECRC_ERR_CPLSTAT <= 3))
CFG_ECRC_ERR_CPLSTAT_BINARY = CFG_ECRC_ERR_CPLSTAT;
else begin
$display("Attribute Syntax Error : The Attribute CFG_ECRC_ERR_CPLSTAT on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", CFG_ECRC_ERR_CPLSTAT);
#1 $finish;
end
if ((DEV_CAP_ENDPOINT_L0S_LATENCY >= 0) && (DEV_CAP_ENDPOINT_L0S_LATENCY <= 7))
DEV_CAP_ENDPOINT_L0S_LATENCY_BINARY = DEV_CAP_ENDPOINT_L0S_LATENCY;
else begin
$display("Attribute Syntax Error : The Attribute DEV_CAP_ENDPOINT_L0S_LATENCY on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", DEV_CAP_ENDPOINT_L0S_LATENCY);
#1 $finish;
end
if ((DEV_CAP_ENDPOINT_L1_LATENCY >= 0) && (DEV_CAP_ENDPOINT_L1_LATENCY <= 7))
DEV_CAP_ENDPOINT_L1_LATENCY_BINARY = DEV_CAP_ENDPOINT_L1_LATENCY;
else begin
$display("Attribute Syntax Error : The Attribute DEV_CAP_ENDPOINT_L1_LATENCY on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", DEV_CAP_ENDPOINT_L1_LATENCY);
#1 $finish;
end
if ((DEV_CAP_MAX_PAYLOAD_SUPPORTED >= 0) && (DEV_CAP_MAX_PAYLOAD_SUPPORTED <= 7))
DEV_CAP_MAX_PAYLOAD_SUPPORTED_BINARY = DEV_CAP_MAX_PAYLOAD_SUPPORTED;
else begin
$display("Attribute Syntax Error : The Attribute DEV_CAP_MAX_PAYLOAD_SUPPORTED on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", DEV_CAP_MAX_PAYLOAD_SUPPORTED);
#1 $finish;
end
if ((DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT >= 0) && (DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT <= 3))
DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT_BINARY = DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT;
else begin
$display("Attribute Syntax Error : The Attribute DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT);
#1 $finish;
end
if ((DEV_CAP_RSVD_14_12 >= 0) && (DEV_CAP_RSVD_14_12 <= 7))
DEV_CAP_RSVD_14_12_BINARY = DEV_CAP_RSVD_14_12;
else begin
$display("Attribute Syntax Error : The Attribute DEV_CAP_RSVD_14_12 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", DEV_CAP_RSVD_14_12);
#1 $finish;
end
if ((DEV_CAP_RSVD_17_16 >= 0) && (DEV_CAP_RSVD_17_16 <= 3))
DEV_CAP_RSVD_17_16_BINARY = DEV_CAP_RSVD_17_16;
else begin
$display("Attribute Syntax Error : The Attribute DEV_CAP_RSVD_17_16 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", DEV_CAP_RSVD_17_16);
#1 $finish;
end
if ((DEV_CAP_RSVD_31_29 >= 0) && (DEV_CAP_RSVD_31_29 <= 7))
DEV_CAP_RSVD_31_29_BINARY = DEV_CAP_RSVD_31_29;
else begin
$display("Attribute Syntax Error : The Attribute DEV_CAP_RSVD_31_29 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", DEV_CAP_RSVD_31_29);
#1 $finish;
end
if ((LINK_CAP_ASPM_SUPPORT >= 0) && (LINK_CAP_ASPM_SUPPORT <= 3))
LINK_CAP_ASPM_SUPPORT_BINARY = LINK_CAP_ASPM_SUPPORT;
else begin
$display("Attribute Syntax Error : The Attribute LINK_CAP_ASPM_SUPPORT on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", LINK_CAP_ASPM_SUPPORT);
#1 $finish;
end
if ((LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 >= 0) && (LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 <= 7))
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_BINARY = LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1;
else begin
$display("Attribute Syntax Error : The Attribute LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1);
#1 $finish;
end
if ((LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 >= 0) && (LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 <= 7))
LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_BINARY = LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2;
else begin
$display("Attribute Syntax Error : The Attribute LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2);
#1 $finish;
end
if ((LINK_CAP_L0S_EXIT_LATENCY_GEN1 >= 0) && (LINK_CAP_L0S_EXIT_LATENCY_GEN1 <= 7))
LINK_CAP_L0S_EXIT_LATENCY_GEN1_BINARY = LINK_CAP_L0S_EXIT_LATENCY_GEN1;
else begin
$display("Attribute Syntax Error : The Attribute LINK_CAP_L0S_EXIT_LATENCY_GEN1 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", LINK_CAP_L0S_EXIT_LATENCY_GEN1);
#1 $finish;
end
if ((LINK_CAP_L0S_EXIT_LATENCY_GEN2 >= 0) && (LINK_CAP_L0S_EXIT_LATENCY_GEN2 <= 7))
LINK_CAP_L0S_EXIT_LATENCY_GEN2_BINARY = LINK_CAP_L0S_EXIT_LATENCY_GEN2;
else begin
$display("Attribute Syntax Error : The Attribute LINK_CAP_L0S_EXIT_LATENCY_GEN2 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", LINK_CAP_L0S_EXIT_LATENCY_GEN2);
#1 $finish;
end
if ((LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 >= 0) && (LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 <= 7))
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_BINARY = LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1;
else begin
$display("Attribute Syntax Error : The Attribute LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1);
#1 $finish;
end
if ((LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 >= 0) && (LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 <= 7))
LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_BINARY = LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2;
else begin
$display("Attribute Syntax Error : The Attribute LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2);
#1 $finish;
end
if ((LINK_CAP_L1_EXIT_LATENCY_GEN1 >= 0) && (LINK_CAP_L1_EXIT_LATENCY_GEN1 <= 7))
LINK_CAP_L1_EXIT_LATENCY_GEN1_BINARY = LINK_CAP_L1_EXIT_LATENCY_GEN1;
else begin
$display("Attribute Syntax Error : The Attribute LINK_CAP_L1_EXIT_LATENCY_GEN1 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", LINK_CAP_L1_EXIT_LATENCY_GEN1);
#1 $finish;
end
if ((LINK_CAP_L1_EXIT_LATENCY_GEN2 >= 0) && (LINK_CAP_L1_EXIT_LATENCY_GEN2 <= 7))
LINK_CAP_L1_EXIT_LATENCY_GEN2_BINARY = LINK_CAP_L1_EXIT_LATENCY_GEN2;
else begin
$display("Attribute Syntax Error : The Attribute LINK_CAP_L1_EXIT_LATENCY_GEN2 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", LINK_CAP_L1_EXIT_LATENCY_GEN2);
#1 $finish;
end
if ((LINK_CAP_RSVD_23 >= 0) && (LINK_CAP_RSVD_23 <= 1))
LINK_CAP_RSVD_23_BINARY = LINK_CAP_RSVD_23;
else begin
$display("Attribute Syntax Error : The Attribute LINK_CAP_RSVD_23 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", LINK_CAP_RSVD_23);
#1 $finish;
end
if ((LINK_CONTROL_RCB >= 0) && (LINK_CONTROL_RCB <= 1))
LINK_CONTROL_RCB_BINARY = LINK_CONTROL_RCB;
else begin
$display("Attribute Syntax Error : The Attribute LINK_CONTROL_RCB on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", LINK_CONTROL_RCB);
#1 $finish;
end
if ((LL_ACK_TIMEOUT_FUNC >= 0) && (LL_ACK_TIMEOUT_FUNC <= 3))
LL_ACK_TIMEOUT_FUNC_BINARY = LL_ACK_TIMEOUT_FUNC;
else begin
$display("Attribute Syntax Error : The Attribute LL_ACK_TIMEOUT_FUNC on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", LL_ACK_TIMEOUT_FUNC);
#1 $finish;
end
if ((LL_REPLAY_TIMEOUT_FUNC >= 0) && (LL_REPLAY_TIMEOUT_FUNC <= 3))
LL_REPLAY_TIMEOUT_FUNC_BINARY = LL_REPLAY_TIMEOUT_FUNC;
else begin
$display("Attribute Syntax Error : The Attribute LL_REPLAY_TIMEOUT_FUNC on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", LL_REPLAY_TIMEOUT_FUNC);
#1 $finish;
end
if ((MSIX_CAP_PBA_BIR >= 0) && (MSIX_CAP_PBA_BIR <= 7))
MSIX_CAP_PBA_BIR_BINARY = MSIX_CAP_PBA_BIR;
else begin
$display("Attribute Syntax Error : The Attribute MSIX_CAP_PBA_BIR on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", MSIX_CAP_PBA_BIR);
#1 $finish;
end
if ((MSIX_CAP_TABLE_BIR >= 0) && (MSIX_CAP_TABLE_BIR <= 7))
MSIX_CAP_TABLE_BIR_BINARY = MSIX_CAP_TABLE_BIR;
else begin
$display("Attribute Syntax Error : The Attribute MSIX_CAP_TABLE_BIR on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", MSIX_CAP_TABLE_BIR);
#1 $finish;
end
if ((MSI_CAP_MULTIMSGCAP >= 0) && (MSI_CAP_MULTIMSGCAP <= 7))
MSI_CAP_MULTIMSGCAP_BINARY = MSI_CAP_MULTIMSGCAP;
else begin
$display("Attribute Syntax Error : The Attribute MSI_CAP_MULTIMSGCAP on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", MSI_CAP_MULTIMSGCAP);
#1 $finish;
end
if ((MSI_CAP_MULTIMSG_EXTENSION >= 0) && (MSI_CAP_MULTIMSG_EXTENSION <= 1))
MSI_CAP_MULTIMSG_EXTENSION_BINARY = MSI_CAP_MULTIMSG_EXTENSION;
else begin
$display("Attribute Syntax Error : The Attribute MSI_CAP_MULTIMSG_EXTENSION on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", MSI_CAP_MULTIMSG_EXTENSION);
#1 $finish;
end
if ((N_FTS_COMCLK_GEN1 >= 0) && (N_FTS_COMCLK_GEN1 <= 255))
N_FTS_COMCLK_GEN1_BINARY = N_FTS_COMCLK_GEN1;
else begin
$display("Attribute Syntax Error : The Attribute N_FTS_COMCLK_GEN1 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 255.", N_FTS_COMCLK_GEN1);
#1 $finish;
end
if ((N_FTS_COMCLK_GEN2 >= 0) && (N_FTS_COMCLK_GEN2 <= 255))
N_FTS_COMCLK_GEN2_BINARY = N_FTS_COMCLK_GEN2;
else begin
$display("Attribute Syntax Error : The Attribute N_FTS_COMCLK_GEN2 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 255.", N_FTS_COMCLK_GEN2);
#1 $finish;
end
if ((N_FTS_GEN1 >= 0) && (N_FTS_GEN1 <= 255))
N_FTS_GEN1_BINARY = N_FTS_GEN1;
else begin
$display("Attribute Syntax Error : The Attribute N_FTS_GEN1 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 255.", N_FTS_GEN1);
#1 $finish;
end
if ((N_FTS_GEN2 >= 0) && (N_FTS_GEN2 <= 255))
N_FTS_GEN2_BINARY = N_FTS_GEN2;
else begin
$display("Attribute Syntax Error : The Attribute N_FTS_GEN2 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 255.", N_FTS_GEN2);
#1 $finish;
end
if ((PCIE_CAP_RSVD_15_14 >= 0) && (PCIE_CAP_RSVD_15_14 <= 3))
PCIE_CAP_RSVD_15_14_BINARY = PCIE_CAP_RSVD_15_14;
else begin
$display("Attribute Syntax Error : The Attribute PCIE_CAP_RSVD_15_14 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", PCIE_CAP_RSVD_15_14);
#1 $finish;
end
if ((PCIE_REVISION >= 0) && (PCIE_REVISION <= 15))
PCIE_REVISION_BINARY = PCIE_REVISION;
else begin
$display("Attribute Syntax Error : The Attribute PCIE_REVISION on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 15.", PCIE_REVISION);
#1 $finish;
end
if ((PL_AUTO_CONFIG >= 0) && (PL_AUTO_CONFIG <= 7))
PL_AUTO_CONFIG_BINARY = PL_AUTO_CONFIG;
else begin
$display("Attribute Syntax Error : The Attribute PL_AUTO_CONFIG on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PL_AUTO_CONFIG);
#1 $finish;
end
if ((PM_ASPML0S_TIMEOUT_FUNC >= 0) && (PM_ASPML0S_TIMEOUT_FUNC <= 3))
PM_ASPML0S_TIMEOUT_FUNC_BINARY = PM_ASPML0S_TIMEOUT_FUNC;
else begin
$display("Attribute Syntax Error : The Attribute PM_ASPML0S_TIMEOUT_FUNC on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", PM_ASPML0S_TIMEOUT_FUNC);
#1 $finish;
end
if ((PM_CAP_AUXCURRENT >= 0) && (PM_CAP_AUXCURRENT <= 7))
PM_CAP_AUXCURRENT_BINARY = PM_CAP_AUXCURRENT;
else begin
$display("Attribute Syntax Error : The Attribute PM_CAP_AUXCURRENT on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PM_CAP_AUXCURRENT);
#1 $finish;
end
if ((PM_CAP_RSVD_04 >= 0) && (PM_CAP_RSVD_04 <= 1))
PM_CAP_RSVD_04_BINARY = PM_CAP_RSVD_04;
else begin
$display("Attribute Syntax Error : The Attribute PM_CAP_RSVD_04 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", PM_CAP_RSVD_04);
#1 $finish;
end
if ((PM_CAP_VERSION >= 0) && (PM_CAP_VERSION <= 7))
PM_CAP_VERSION_BINARY = PM_CAP_VERSION;
else begin
$display("Attribute Syntax Error : The Attribute PM_CAP_VERSION on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PM_CAP_VERSION);
#1 $finish;
end
if ((RECRC_CHK >= 0) && (RECRC_CHK <= 3))
RECRC_CHK_BINARY = RECRC_CHK;
else begin
$display("Attribute Syntax Error : The Attribute RECRC_CHK on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", RECRC_CHK);
#1 $finish;
end
if ((SLOT_CAP_SLOT_POWER_LIMIT_SCALE >= 0) && (SLOT_CAP_SLOT_POWER_LIMIT_SCALE <= 3))
SLOT_CAP_SLOT_POWER_LIMIT_SCALE_BINARY = SLOT_CAP_SLOT_POWER_LIMIT_SCALE;
else begin
$display("Attribute Syntax Error : The Attribute SLOT_CAP_SLOT_POWER_LIMIT_SCALE on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", SLOT_CAP_SLOT_POWER_LIMIT_SCALE);
#1 $finish;
end
if ((SPARE_BIT0 >= 0) && (SPARE_BIT0 <= 1))
SPARE_BIT0_BINARY = SPARE_BIT0;
else begin
$display("Attribute Syntax Error : The Attribute SPARE_BIT0 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT0);
#1 $finish;
end
if ((SPARE_BIT1 >= 0) && (SPARE_BIT1 <= 1))
SPARE_BIT1_BINARY = SPARE_BIT1;
else begin
$display("Attribute Syntax Error : The Attribute SPARE_BIT1 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT1);
#1 $finish;
end
if ((SPARE_BIT2 >= 0) && (SPARE_BIT2 <= 1))
SPARE_BIT2_BINARY = SPARE_BIT2;
else begin
$display("Attribute Syntax Error : The Attribute SPARE_BIT2 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT2);
#1 $finish;
end
if ((SPARE_BIT3 >= 0) && (SPARE_BIT3 <= 1))
SPARE_BIT3_BINARY = SPARE_BIT3;
else begin
$display("Attribute Syntax Error : The Attribute SPARE_BIT3 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT3);
#1 $finish;
end
if ((SPARE_BIT4 >= 0) && (SPARE_BIT4 <= 1))
SPARE_BIT4_BINARY = SPARE_BIT4;
else begin
$display("Attribute Syntax Error : The Attribute SPARE_BIT4 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT4);
#1 $finish;
end
if ((SPARE_BIT5 >= 0) && (SPARE_BIT5 <= 1))
SPARE_BIT5_BINARY = SPARE_BIT5;
else begin
$display("Attribute Syntax Error : The Attribute SPARE_BIT5 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT5);
#1 $finish;
end
if ((SPARE_BIT6 >= 0) && (SPARE_BIT6 <= 1))
SPARE_BIT6_BINARY = SPARE_BIT6;
else begin
$display("Attribute Syntax Error : The Attribute SPARE_BIT6 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT6);
#1 $finish;
end
if ((SPARE_BIT7 >= 0) && (SPARE_BIT7 <= 1))
SPARE_BIT7_BINARY = SPARE_BIT7;
else begin
$display("Attribute Syntax Error : The Attribute SPARE_BIT7 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT7);
#1 $finish;
end
if ((SPARE_BIT8 >= 0) && (SPARE_BIT8 <= 1))
SPARE_BIT8_BINARY = SPARE_BIT8;
else begin
$display("Attribute Syntax Error : The Attribute SPARE_BIT8 on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT8);
#1 $finish;
end
if ((TL_RX_RAM_RADDR_LATENCY >= 0) && (TL_RX_RAM_RADDR_LATENCY <= 1))
TL_RX_RAM_RADDR_LATENCY_BINARY = TL_RX_RAM_RADDR_LATENCY;
else begin
$display("Attribute Syntax Error : The Attribute TL_RX_RAM_RADDR_LATENCY on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", TL_RX_RAM_RADDR_LATENCY);
#1 $finish;
end
if ((TL_RX_RAM_RDATA_LATENCY >= 0) && (TL_RX_RAM_RDATA_LATENCY <= 3))
TL_RX_RAM_RDATA_LATENCY_BINARY = TL_RX_RAM_RDATA_LATENCY;
else begin
$display("Attribute Syntax Error : The Attribute TL_RX_RAM_RDATA_LATENCY on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", TL_RX_RAM_RDATA_LATENCY);
#1 $finish;
end
if ((TL_RX_RAM_WRITE_LATENCY >= 0) && (TL_RX_RAM_WRITE_LATENCY <= 1))
TL_RX_RAM_WRITE_LATENCY_BINARY = TL_RX_RAM_WRITE_LATENCY;
else begin
$display("Attribute Syntax Error : The Attribute TL_RX_RAM_WRITE_LATENCY on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", TL_RX_RAM_WRITE_LATENCY);
#1 $finish;
end
if ((TL_TX_RAM_RADDR_LATENCY >= 0) && (TL_TX_RAM_RADDR_LATENCY <= 1))
TL_TX_RAM_RADDR_LATENCY_BINARY = TL_TX_RAM_RADDR_LATENCY;
else begin
$display("Attribute Syntax Error : The Attribute TL_TX_RAM_RADDR_LATENCY on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", TL_TX_RAM_RADDR_LATENCY);
#1 $finish;
end
if ((TL_TX_RAM_RDATA_LATENCY >= 0) && (TL_TX_RAM_RDATA_LATENCY <= 3))
TL_TX_RAM_RDATA_LATENCY_BINARY = TL_TX_RAM_RDATA_LATENCY;
else begin
$display("Attribute Syntax Error : The Attribute TL_TX_RAM_RDATA_LATENCY on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 3.", TL_TX_RAM_RDATA_LATENCY);
#1 $finish;
end
if ((TL_TX_RAM_WRITE_LATENCY >= 0) && (TL_TX_RAM_WRITE_LATENCY <= 1))
TL_TX_RAM_WRITE_LATENCY_BINARY = TL_TX_RAM_WRITE_LATENCY;
else begin
$display("Attribute Syntax Error : The Attribute TL_TX_RAM_WRITE_LATENCY on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 1.", TL_TX_RAM_WRITE_LATENCY);
#1 $finish;
end
if ((USER_CLK_FREQ >= 0) && (USER_CLK_FREQ <= 7))
USER_CLK_FREQ_BINARY = USER_CLK_FREQ;
else begin
$display("Attribute Syntax Error : The Attribute USER_CLK_FREQ on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 7.", USER_CLK_FREQ);
#1 $finish;
end
if ((VC0_TOTAL_CREDITS_CD >= 0) && (VC0_TOTAL_CREDITS_CD <= 2047))
VC0_TOTAL_CREDITS_CD_BINARY = VC0_TOTAL_CREDITS_CD;
else begin
$display("Attribute Syntax Error : The Attribute VC0_TOTAL_CREDITS_CD on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 2047.", VC0_TOTAL_CREDITS_CD);
#1 $finish;
end
if ((VC0_TOTAL_CREDITS_CH >= 0) && (VC0_TOTAL_CREDITS_CH <= 127))
VC0_TOTAL_CREDITS_CH_BINARY = VC0_TOTAL_CREDITS_CH;
else begin
$display("Attribute Syntax Error : The Attribute VC0_TOTAL_CREDITS_CH on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 127.", VC0_TOTAL_CREDITS_CH);
#1 $finish;
end
if ((VC0_TOTAL_CREDITS_NPD >= 0) && (VC0_TOTAL_CREDITS_NPD <= 2047))
VC0_TOTAL_CREDITS_NPD_BINARY = VC0_TOTAL_CREDITS_NPD;
else begin
$display("Attribute Syntax Error : The Attribute VC0_TOTAL_CREDITS_NPD on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 2047.", VC0_TOTAL_CREDITS_NPD);
#1 $finish;
end
if ((VC0_TOTAL_CREDITS_NPH >= 0) && (VC0_TOTAL_CREDITS_NPH <= 127))
VC0_TOTAL_CREDITS_NPH_BINARY = VC0_TOTAL_CREDITS_NPH;
else begin
$display("Attribute Syntax Error : The Attribute VC0_TOTAL_CREDITS_NPH on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 127.", VC0_TOTAL_CREDITS_NPH);
#1 $finish;
end
if ((VC0_TOTAL_CREDITS_PD >= 0) && (VC0_TOTAL_CREDITS_PD <= 2047))
VC0_TOTAL_CREDITS_PD_BINARY = VC0_TOTAL_CREDITS_PD;
else begin
$display("Attribute Syntax Error : The Attribute VC0_TOTAL_CREDITS_PD on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 2047.", VC0_TOTAL_CREDITS_PD);
#1 $finish;
end
if ((VC0_TOTAL_CREDITS_PH >= 0) && (VC0_TOTAL_CREDITS_PH <= 127))
VC0_TOTAL_CREDITS_PH_BINARY = VC0_TOTAL_CREDITS_PH;
else begin
$display("Attribute Syntax Error : The Attribute VC0_TOTAL_CREDITS_PH on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 127.", VC0_TOTAL_CREDITS_PH);
#1 $finish;
end
if ((VC0_TX_LASTPACKET >= 0) && (VC0_TX_LASTPACKET <= 31))
VC0_TX_LASTPACKET_BINARY = VC0_TX_LASTPACKET;
else begin
$display("Attribute Syntax Error : The Attribute VC0_TX_LASTPACKET on X_PCIE_2_1 instance %m is set to %d. Legal values for this attribute are 0 to 31.", VC0_TX_LASTPACKET);
#1 $finish;
end
end
wire [11:0] delay_DBGVECC;
wire [11:0] delay_PLDBGVEC;
wire [11:0] delay_TRNFCCPLD;
wire [11:0] delay_TRNFCNPD;
wire [11:0] delay_TRNFCPD;
wire [127:0] delay_TRNRD;
wire [12:0] delay_MIMRXRADDR;
wire [12:0] delay_MIMRXWADDR;
wire [12:0] delay_MIMTXRADDR;
wire [12:0] delay_MIMTXWADDR;
wire [15:0] delay_CFGMSGDATA;
wire [15:0] delay_DRPDO;
wire [15:0] delay_PIPETX0DATA;
wire [15:0] delay_PIPETX1DATA;
wire [15:0] delay_PIPETX2DATA;
wire [15:0] delay_PIPETX3DATA;
wire [15:0] delay_PIPETX4DATA;
wire [15:0] delay_PIPETX5DATA;
wire [15:0] delay_PIPETX6DATA;
wire [15:0] delay_PIPETX7DATA;
wire [1:0] delay_CFGLINKCONTROLASPMCONTROL;
wire [1:0] delay_CFGLINKSTATUSCURRENTSPEED;
wire [1:0] delay_CFGPMCSRPOWERSTATE;
wire [1:0] delay_PIPETX0CHARISK;
wire [1:0] delay_PIPETX0POWERDOWN;
wire [1:0] delay_PIPETX1CHARISK;
wire [1:0] delay_PIPETX1POWERDOWN;
wire [1:0] delay_PIPETX2CHARISK;
wire [1:0] delay_PIPETX2POWERDOWN;
wire [1:0] delay_PIPETX3CHARISK;
wire [1:0] delay_PIPETX3POWERDOWN;
wire [1:0] delay_PIPETX4CHARISK;
wire [1:0] delay_PIPETX4POWERDOWN;
wire [1:0] delay_PIPETX5CHARISK;
wire [1:0] delay_PIPETX5POWERDOWN;
wire [1:0] delay_PIPETX6CHARISK;
wire [1:0] delay_PIPETX6POWERDOWN;
wire [1:0] delay_PIPETX7CHARISK;
wire [1:0] delay_PIPETX7POWERDOWN;
wire [1:0] delay_PL2RXPMSTATE;
wire [1:0] delay_PLLANEREVERSALMODE;
wire [1:0] delay_PLRXPMSTATE;
wire [1:0] delay_PLSELLNKWIDTH;
wire [1:0] delay_TRNRDLLPSRCRDY;
wire [1:0] delay_TRNRREM;
wire [2:0] delay_CFGDEVCONTROLMAXPAYLOAD;
wire [2:0] delay_CFGDEVCONTROLMAXREADREQ;
wire [2:0] delay_CFGINTERRUPTMMENABLE;
wire [2:0] delay_CFGPCIELINKSTATE;
wire [2:0] delay_PIPETXMARGIN;
wire [2:0] delay_PLINITIALLINKWIDTH;
wire [2:0] delay_PLTXPMSTATE;
wire [31:0] delay_CFGMGMTDO;
wire [3:0] delay_CFGDEVCONTROL2CPLTIMEOUTVAL;
wire [3:0] delay_CFGLINKSTATUSNEGOTIATEDWIDTH;
wire [3:0] delay_TRNTDSTRDY;
wire [4:0] delay_LL2LINKSTATUS;
wire [5:0] delay_PLLTSSMSTATE;
wire [5:0] delay_TRNTBUFAV;
wire [63:0] delay_DBGVECA;
wire [63:0] delay_DBGVECB;
wire [63:0] delay_TL2ERRHDR;
wire [63:0] delay_TRNRDLLPDATA;
wire [67:0] delay_MIMRXWDATA;
wire [68:0] delay_MIMTXWDATA;
wire [6:0] delay_CFGTRANSACTIONADDR;
wire [6:0] delay_CFGVCTCVCMAP;
wire [7:0] delay_CFGINTERRUPTDO;
wire [7:0] delay_TRNFCCPLH;
wire [7:0] delay_TRNFCNPH;
wire [7:0] delay_TRNFCPH;
wire [7:0] delay_TRNRBARHIT;
wire delay_CFGAERECRCCHECKEN;
wire delay_CFGAERECRCGENEN;
wire delay_CFGAERROOTERRCORRERRRECEIVED;
wire delay_CFGAERROOTERRCORRERRREPORTINGEN;
wire delay_CFGAERROOTERRFATALERRRECEIVED;
wire delay_CFGAERROOTERRFATALERRREPORTINGEN;
wire delay_CFGAERROOTERRNONFATALERRRECEIVED;
wire delay_CFGAERROOTERRNONFATALERRREPORTINGEN;
wire delay_CFGBRIDGESERREN;
wire delay_CFGCOMMANDBUSMASTERENABLE;
wire delay_CFGCOMMANDINTERRUPTDISABLE;
wire delay_CFGCOMMANDIOENABLE;
wire delay_CFGCOMMANDMEMENABLE;
wire delay_CFGCOMMANDSERREN;
wire delay_CFGDEVCONTROL2ARIFORWARDEN;
wire delay_CFGDEVCONTROL2ATOMICEGRESSBLOCK;
wire delay_CFGDEVCONTROL2ATOMICREQUESTEREN;
wire delay_CFGDEVCONTROL2CPLTIMEOUTDIS;
wire delay_CFGDEVCONTROL2IDOCPLEN;
wire delay_CFGDEVCONTROL2IDOREQEN;
wire delay_CFGDEVCONTROL2LTREN;
wire delay_CFGDEVCONTROL2TLPPREFIXBLOCK;
wire delay_CFGDEVCONTROLAUXPOWEREN;
wire delay_CFGDEVCONTROLCORRERRREPORTINGEN;
wire delay_CFGDEVCONTROLENABLERO;
wire delay_CFGDEVCONTROLEXTTAGEN;
wire delay_CFGDEVCONTROLFATALERRREPORTINGEN;
wire delay_CFGDEVCONTROLNONFATALREPORTINGEN;
wire delay_CFGDEVCONTROLNOSNOOPEN;
wire delay_CFGDEVCONTROLPHANTOMEN;
wire delay_CFGDEVCONTROLURERRREPORTINGEN;
wire delay_CFGDEVSTATUSCORRERRDETECTED;
wire delay_CFGDEVSTATUSFATALERRDETECTED;
wire delay_CFGDEVSTATUSNONFATALERRDETECTED;
wire delay_CFGDEVSTATUSURDETECTED;
wire delay_CFGERRAERHEADERLOGSETN;
wire delay_CFGERRCPLRDYN;
wire delay_CFGINTERRUPTMSIENABLE;
wire delay_CFGINTERRUPTMSIXENABLE;
wire delay_CFGINTERRUPTMSIXFM;
wire delay_CFGINTERRUPTRDYN;
wire delay_CFGLINKCONTROLAUTOBANDWIDTHINTEN;
wire delay_CFGLINKCONTROLBANDWIDTHINTEN;
wire delay_CFGLINKCONTROLCLOCKPMEN;
wire delay_CFGLINKCONTROLCOMMONCLOCK;
wire delay_CFGLINKCONTROLEXTENDEDSYNC;
wire delay_CFGLINKCONTROLHWAUTOWIDTHDIS;
wire delay_CFGLINKCONTROLLINKDISABLE;
wire delay_CFGLINKCONTROLRCB;
wire delay_CFGLINKCONTROLRETRAINLINK;
wire delay_CFGLINKSTATUSAUTOBANDWIDTHSTATUS;
wire delay_CFGLINKSTATUSBANDWIDTHSTATUS;
wire delay_CFGLINKSTATUSDLLACTIVE;
wire delay_CFGLINKSTATUSLINKTRAINING;
wire delay_CFGMGMTRDWRDONEN;
wire delay_CFGMSGRECEIVED;
wire delay_CFGMSGRECEIVEDASSERTINTA;
wire delay_CFGMSGRECEIVEDASSERTINTB;
wire delay_CFGMSGRECEIVEDASSERTINTC;
wire delay_CFGMSGRECEIVEDASSERTINTD;
wire delay_CFGMSGRECEIVEDDEASSERTINTA;
wire delay_CFGMSGRECEIVEDDEASSERTINTB;
wire delay_CFGMSGRECEIVEDDEASSERTINTC;
wire delay_CFGMSGRECEIVEDDEASSERTINTD;
wire delay_CFGMSGRECEIVEDERRCOR;
wire delay_CFGMSGRECEIVEDERRFATAL;
wire delay_CFGMSGRECEIVEDERRNONFATAL;
wire delay_CFGMSGRECEIVEDPMASNAK;
wire delay_CFGMSGRECEIVEDPMETO;
wire delay_CFGMSGRECEIVEDPMETOACK;
wire delay_CFGMSGRECEIVEDPMPME;
wire delay_CFGMSGRECEIVEDSETSLOTPOWERLIMIT;
wire delay_CFGMSGRECEIVEDUNLOCK;
wire delay_CFGPMCSRPMEEN;
wire delay_CFGPMCSRPMESTATUS;
wire delay_CFGPMRCVASREQL1N;
wire delay_CFGPMRCVENTERL1N;
wire delay_CFGPMRCVENTERL23N;
wire delay_CFGPMRCVREQACKN;
wire delay_CFGROOTCONTROLPMEINTEN;
wire delay_CFGROOTCONTROLSYSERRCORRERREN;
wire delay_CFGROOTCONTROLSYSERRFATALERREN;
wire delay_CFGROOTCONTROLSYSERRNONFATALERREN;
wire delay_CFGSLOTCONTROLELECTROMECHILCTLPULSE;
wire delay_CFGTRANSACTION;
wire delay_CFGTRANSACTIONTYPE;
wire delay_DBGSCLRA;
wire delay_DBGSCLRB;
wire delay_DBGSCLRC;
wire delay_DBGSCLRD;
wire delay_DBGSCLRE;
wire delay_DBGSCLRF;
wire delay_DBGSCLRG;
wire delay_DBGSCLRH;
wire delay_DBGSCLRI;
wire delay_DBGSCLRJ;
wire delay_DBGSCLRK;
wire delay_DRPRDY;
wire delay_LL2BADDLLPERR;
wire delay_LL2BADTLPERR;
wire delay_LL2PROTOCOLERR;
wire delay_LL2RECEIVERERR;
wire delay_LL2REPLAYROERR;
wire delay_LL2REPLAYTOERR;
wire delay_LL2SUSPENDOK;
wire delay_LL2TFCINIT1SEQ;
wire delay_LL2TFCINIT2SEQ;
wire delay_LL2TXIDLE;
wire delay_LNKCLKEN;
wire delay_MIMRXREN;
wire delay_MIMRXWEN;
wire delay_MIMTXREN;
wire delay_MIMTXWEN;
wire delay_PIPERX0POLARITY;
wire delay_PIPERX1POLARITY;
wire delay_PIPERX2POLARITY;
wire delay_PIPERX3POLARITY;
wire delay_PIPERX4POLARITY;
wire delay_PIPERX5POLARITY;
wire delay_PIPERX6POLARITY;
wire delay_PIPERX7POLARITY;
wire delay_PIPETX0COMPLIANCE;
wire delay_PIPETX0ELECIDLE;
wire delay_PIPETX1COMPLIANCE;
wire delay_PIPETX1ELECIDLE;
wire delay_PIPETX2COMPLIANCE;
wire delay_PIPETX2ELECIDLE;
wire delay_PIPETX3COMPLIANCE;
wire delay_PIPETX3ELECIDLE;
wire delay_PIPETX4COMPLIANCE;
wire delay_PIPETX4ELECIDLE;
wire delay_PIPETX5COMPLIANCE;
wire delay_PIPETX5ELECIDLE;
wire delay_PIPETX6COMPLIANCE;
wire delay_PIPETX6ELECIDLE;
wire delay_PIPETX7COMPLIANCE;
wire delay_PIPETX7ELECIDLE;
wire delay_PIPETXDEEMPH;
wire delay_PIPETXRATE;
wire delay_PIPETXRCVRDET;
wire delay_PIPETXRESET;
wire delay_PL2L0REQ;
wire delay_PL2LINKUP;
wire delay_PL2RECEIVERERR;
wire delay_PL2RECOVERY;
wire delay_PL2RXELECIDLE;
wire delay_PL2SUSPENDOK;
wire delay_PLDIRECTEDCHANGEDONE;
wire delay_PLLINKGEN2CAP;
wire delay_PLLINKPARTNERGEN2SUPPORTED;
wire delay_PLLINKUPCFGCAP;
wire delay_PLPHYLNKUPN;
wire delay_PLRECEIVEDHOTRST;
wire delay_PLSELLNKRATE;
wire delay_RECEIVEDFUNCLVLRSTN;
wire delay_TL2ASPMSUSPENDCREDITCHECKOK;
wire delay_TL2ASPMSUSPENDREQ;
wire delay_TL2ERRFCPE;
wire delay_TL2ERRMALFORMED;
wire delay_TL2ERRRXOVERFLOW;
wire delay_TL2PPMSUSPENDOK;
wire delay_TRNLNKUP;
wire delay_TRNRECRCERR;
wire delay_TRNREOF;
wire delay_TRNRERRFWD;
wire delay_TRNRSOF;
wire delay_TRNRSRCDSC;
wire delay_TRNRSRCRDY;
wire delay_TRNTCFGREQ;
wire delay_TRNTDLLPDSTRDY;
wire delay_TRNTERRDROP;
wire delay_USERRSTN;
wire [127:0] delay_CFGERRAERHEADERLOG;
wire [127:0] delay_TRNTD;
wire [15:0] delay_CFGDEVID;
wire [15:0] delay_CFGSUBSYSID;
wire [15:0] delay_CFGSUBSYSVENDID;
wire [15:0] delay_CFGVENDID;
wire [15:0] delay_DRPDI;
wire [15:0] delay_PIPERX0DATA;
wire [15:0] delay_PIPERX1DATA;
wire [15:0] delay_PIPERX2DATA;
wire [15:0] delay_PIPERX3DATA;
wire [15:0] delay_PIPERX4DATA;
wire [15:0] delay_PIPERX5DATA;
wire [15:0] delay_PIPERX6DATA;
wire [15:0] delay_PIPERX7DATA;
wire [1:0] delay_CFGPMFORCESTATE;
wire [1:0] delay_DBGMODE;
wire [1:0] delay_PIPERX0CHARISK;
wire [1:0] delay_PIPERX1CHARISK;
wire [1:0] delay_PIPERX2CHARISK;
wire [1:0] delay_PIPERX3CHARISK;
wire [1:0] delay_PIPERX4CHARISK;
wire [1:0] delay_PIPERX5CHARISK;
wire [1:0] delay_PIPERX6CHARISK;
wire [1:0] delay_PIPERX7CHARISK;
wire [1:0] delay_PLDIRECTEDLINKCHANGE;
wire [1:0] delay_PLDIRECTEDLINKWIDTH;
wire [1:0] delay_TRNTREM;
wire [2:0] delay_CFGDSFUNCTIONNUMBER;
wire [2:0] delay_CFGFORCEMPS;
wire [2:0] delay_PIPERX0STATUS;
wire [2:0] delay_PIPERX1STATUS;
wire [2:0] delay_PIPERX2STATUS;
wire [2:0] delay_PIPERX3STATUS;
wire [2:0] delay_PIPERX4STATUS;
wire [2:0] delay_PIPERX5STATUS;
wire [2:0] delay_PIPERX6STATUS;
wire [2:0] delay_PIPERX7STATUS;
wire [2:0] delay_PLDBGMODE;
wire [2:0] delay_TRNFCSEL;
wire [31:0] delay_CFGMGMTDI;
wire [31:0] delay_TRNTDLLPDATA;
wire [3:0] delay_CFGMGMTBYTEENN;
wire [47:0] delay_CFGERRTLPCPLHEADER;
wire [4:0] delay_CFGAERINTERRUPTMSGNUM;
wire [4:0] delay_CFGDSDEVICENUMBER;
wire [4:0] delay_CFGPCIECAPINTERRUPTMSGNUM;
wire [4:0] delay_PL2DIRECTEDLSTATE;
wire [5:0] delay_PLDIRECTEDLTSSMNEW;
wire [63:0] delay_CFGDSN;
wire [67:0] delay_MIMRXRDATA;
wire [68:0] delay_MIMTXRDATA;
wire [7:0] delay_CFGDSBUSNUMBER;
wire [7:0] delay_CFGINTERRUPTDI;
wire [7:0] delay_CFGPORTNUMBER;
wire [7:0] delay_CFGREVID;
wire [8:0] delay_DRPADDR;
wire [9:0] delay_CFGMGMTDWADDR;
wire delay_CFGERRACSN;
wire delay_CFGERRATOMICEGRESSBLOCKEDN;
wire delay_CFGERRCORN;
wire delay_CFGERRCPLABORTN;
wire delay_CFGERRCPLTIMEOUTN;
wire delay_CFGERRCPLUNEXPECTN;
wire delay_CFGERRECRCN;
wire delay_CFGERRINTERNALCORN;
wire delay_CFGERRINTERNALUNCORN;
wire delay_CFGERRLOCKEDN;
wire delay_CFGERRMALFORMEDN;
wire delay_CFGERRMCBLOCKEDN;
wire delay_CFGERRNORECOVERYN;
wire delay_CFGERRPOISONEDN;
wire delay_CFGERRPOSTEDN;
wire delay_CFGERRURN;
wire delay_CFGFORCECOMMONCLOCKOFF;
wire delay_CFGFORCEEXTENDEDSYNCON;
wire delay_CFGINTERRUPTASSERTN;
wire delay_CFGINTERRUPTN;
wire delay_CFGINTERRUPTSTATN;
wire delay_CFGMGMTRDENN;
wire delay_CFGMGMTWRENN;
wire delay_CFGMGMTWRREADONLYN;
wire delay_CFGMGMTWRRW1CASRWN;
wire delay_CFGPMFORCESTATEENN;
wire delay_CFGPMHALTASPML0SN;
wire delay_CFGPMHALTASPML1N;
wire delay_CFGPMSENDPMETON;
wire delay_CFGPMTURNOFFOKN;
wire delay_CFGPMWAKEN;
wire delay_CFGTRNPENDINGN;
wire delay_CMRSTN;
wire delay_CMSTICKYRSTN;
wire delay_DBGSUBMODE;
wire delay_DLRSTN;
wire delay_DRPCLK;
wire delay_DRPEN;
wire delay_DRPWE;
wire delay_FUNCLVLRSTN;
wire delay_LL2SENDASREQL1;
wire delay_LL2SENDENTERL1;
wire delay_LL2SENDENTERL23;
wire delay_LL2SENDPMACK;
wire delay_LL2SUSPENDNOW;
wire delay_LL2TLPRCV;
wire delay_PIPECLK;
wire delay_PIPERX0CHANISALIGNED;
wire delay_PIPERX0ELECIDLE;
wire delay_PIPERX0PHYSTATUS;
wire delay_PIPERX0VALID;
wire delay_PIPERX1CHANISALIGNED;
wire delay_PIPERX1ELECIDLE;
wire delay_PIPERX1PHYSTATUS;
wire delay_PIPERX1VALID;
wire delay_PIPERX2CHANISALIGNED;
wire delay_PIPERX2ELECIDLE;
wire delay_PIPERX2PHYSTATUS;
wire delay_PIPERX2VALID;
wire delay_PIPERX3CHANISALIGNED;
wire delay_PIPERX3ELECIDLE;
wire delay_PIPERX3PHYSTATUS;
wire delay_PIPERX3VALID;
wire delay_PIPERX4CHANISALIGNED;
wire delay_PIPERX4ELECIDLE;
wire delay_PIPERX4PHYSTATUS;
wire delay_PIPERX4VALID;
wire delay_PIPERX5CHANISALIGNED;
wire delay_PIPERX5ELECIDLE;
wire delay_PIPERX5PHYSTATUS;
wire delay_PIPERX5VALID;
wire delay_PIPERX6CHANISALIGNED;
wire delay_PIPERX6ELECIDLE;
wire delay_PIPERX6PHYSTATUS;
wire delay_PIPERX6VALID;
wire delay_PIPERX7CHANISALIGNED;
wire delay_PIPERX7ELECIDLE;
wire delay_PIPERX7PHYSTATUS;
wire delay_PIPERX7VALID;
wire delay_PLDIRECTEDLINKAUTON;
wire delay_PLDIRECTEDLINKSPEED;
wire delay_PLDIRECTEDLTSSMNEWVLD;
wire delay_PLDIRECTEDLTSSMSTALL;
wire delay_PLDOWNSTREAMDEEMPHSOURCE;
wire delay_PLRSTN;
wire delay_PLTRANSMITHOTRST;
wire delay_PLUPSTREAMPREFERDEEMPH;
wire delay_SYSRSTN;
wire delay_TL2ASPMSUSPENDCREDITCHECK;
wire delay_TL2PPMSUSPENDREQ;
wire delay_TLRSTN;
wire delay_TRNRDSTRDY;
wire delay_TRNRFCPRET;
wire delay_TRNRNPOK;
wire delay_TRNRNPREQ;
wire delay_TRNTCFGGNT;
wire delay_TRNTDLLPSRCRDY;
wire delay_TRNTECRCGEN;
wire delay_TRNTEOF;
wire delay_TRNTERRFWD;
wire delay_TRNTSOF;
wire delay_TRNTSRCDSC;
wire delay_TRNTSRCRDY;
wire delay_TRNTSTR;
wire delay_USERCLK2;
wire delay_USERCLK;
//drp monitor
reg drpen_r1 = 1'b0;
reg drpen_r2 = 1'b0;
reg drpwe_r1 = 1'b0;
reg drpwe_r2 = 1'b0;
reg [1:0] sfsm = 2'b01;
localparam FSM_IDLE = 2'b01;
localparam FSM_WAIT = 2'b10;
always @(posedge delay_DRPCLK)
begin
// pipeline the DRPEN and DRPWE
drpen_r1 <= delay_DRPEN;
drpwe_r1 <= delay_DRPWE;
drpen_r2 <= drpen_r1;
drpwe_r2 <= drpwe_r1;
// Check - if DRPEN or DRPWE is more than 1 DCLK
if ((drpen_r1 == 1'b1) && (drpen_r2 == 1'b1))
begin
$display("DRC Error : DRPEN is high for more than 1 DRPCLK on %m instance");
$finish;
end
if ((drpwe_r1 == 1'b1) && (drpwe_r2 == 1'b1))
begin
$display("DRC Error : DRPWE is high for more than 1 DRPCLK on %m instance");
$finish;
end
//After the 1st DRPEN pulse, check the DRPEN and DRPRDY.
case (sfsm)
FSM_IDLE:
begin
if(delay_DRPEN == 1'b1)
sfsm <= FSM_WAIT;
end
FSM_WAIT:
begin
// After the 1st DRPEN, 4 cases can happen
// DRPEN DRPRDY NEXT STATE
// 0 0 FSM_WAIT - wait for DRPRDY
// 0 1 FSM_IDLE - normal operation
// 1 0 FSM_WAIT - display error and wait for DRPRDY
// 1 1 FSM_WAIT - normal operation. Per UG470, DRPEN and DRPRDY can be at the same cycle.
//Add the check for another DPREN pulse
if(delay_DRPEN === 1'b1 && delay_DRPRDY === 1'b0)
begin
$display("DRC Error : DRPEN is enabled before DRPRDY returns on %m instance");
$finish;
end
//Add the check for another DRPWE pulse
if ((delay_DRPWE === 1'b1) && (delay_DRPEN === 1'b0))
begin
$display("DRC Error : DRPWE is enabled before DRPRDY returns on %m instance");
$finish;
end
if ((delay_DRPRDY === 1'b1) && (delay_DRPEN === 1'b0))
begin
sfsm <= FSM_IDLE;
end
if ((delay_DRPRDY === 1'b1)&& (delay_DRPEN === 1'b1))
begin
sfsm <= FSM_WAIT;
end
end
default:
begin
$display("DRC Error : Default state in DRP FSM.");
$finish;
end
endcase
end // always @ (posedge delay_DRPCLK)
//end drp monitor
assign #(out_delay) CFGAERECRCCHECKEN = delay_CFGAERECRCCHECKEN;
assign #(out_delay) CFGAERECRCGENEN = delay_CFGAERECRCGENEN;
assign #(out_delay) CFGAERROOTERRCORRERRRECEIVED = delay_CFGAERROOTERRCORRERRRECEIVED;
assign #(out_delay) CFGAERROOTERRCORRERRREPORTINGEN = delay_CFGAERROOTERRCORRERRREPORTINGEN;
assign #(out_delay) CFGAERROOTERRFATALERRRECEIVED = delay_CFGAERROOTERRFATALERRRECEIVED;
assign #(out_delay) CFGAERROOTERRFATALERRREPORTINGEN = delay_CFGAERROOTERRFATALERRREPORTINGEN;
assign #(out_delay) CFGAERROOTERRNONFATALERRRECEIVED = delay_CFGAERROOTERRNONFATALERRRECEIVED;
assign #(out_delay) CFGAERROOTERRNONFATALERRREPORTINGEN = delay_CFGAERROOTERRNONFATALERRREPORTINGEN;
assign #(out_delay) CFGBRIDGESERREN = delay_CFGBRIDGESERREN;
assign #(out_delay) CFGCOMMANDBUSMASTERENABLE = delay_CFGCOMMANDBUSMASTERENABLE;
assign #(out_delay) CFGCOMMANDINTERRUPTDISABLE = delay_CFGCOMMANDINTERRUPTDISABLE;
assign #(out_delay) CFGCOMMANDIOENABLE = delay_CFGCOMMANDIOENABLE;
assign #(out_delay) CFGCOMMANDMEMENABLE = delay_CFGCOMMANDMEMENABLE;
assign #(out_delay) CFGCOMMANDSERREN = delay_CFGCOMMANDSERREN;
assign #(out_delay) CFGDEVCONTROL2ARIFORWARDEN = delay_CFGDEVCONTROL2ARIFORWARDEN;
assign #(out_delay) CFGDEVCONTROL2ATOMICEGRESSBLOCK = delay_CFGDEVCONTROL2ATOMICEGRESSBLOCK;
assign #(out_delay) CFGDEVCONTROL2ATOMICREQUESTEREN = delay_CFGDEVCONTROL2ATOMICREQUESTEREN;
assign #(out_delay) CFGDEVCONTROL2CPLTIMEOUTDIS = delay_CFGDEVCONTROL2CPLTIMEOUTDIS;
assign #(out_delay) CFGDEVCONTROL2CPLTIMEOUTVAL = delay_CFGDEVCONTROL2CPLTIMEOUTVAL;
assign #(out_delay) CFGDEVCONTROL2IDOCPLEN = delay_CFGDEVCONTROL2IDOCPLEN;
assign #(out_delay) CFGDEVCONTROL2IDOREQEN = delay_CFGDEVCONTROL2IDOREQEN;
assign #(out_delay) CFGDEVCONTROL2LTREN = delay_CFGDEVCONTROL2LTREN;
assign #(out_delay) CFGDEVCONTROL2TLPPREFIXBLOCK = delay_CFGDEVCONTROL2TLPPREFIXBLOCK;
assign #(out_delay) CFGDEVCONTROLAUXPOWEREN = delay_CFGDEVCONTROLAUXPOWEREN;
assign #(out_delay) CFGDEVCONTROLCORRERRREPORTINGEN = delay_CFGDEVCONTROLCORRERRREPORTINGEN;
assign #(out_delay) CFGDEVCONTROLENABLERO = delay_CFGDEVCONTROLENABLERO;
assign #(out_delay) CFGDEVCONTROLEXTTAGEN = delay_CFGDEVCONTROLEXTTAGEN;
assign #(out_delay) CFGDEVCONTROLFATALERRREPORTINGEN = delay_CFGDEVCONTROLFATALERRREPORTINGEN;
assign #(out_delay) CFGDEVCONTROLMAXPAYLOAD = delay_CFGDEVCONTROLMAXPAYLOAD;
assign #(out_delay) CFGDEVCONTROLMAXREADREQ = delay_CFGDEVCONTROLMAXREADREQ;
assign #(out_delay) CFGDEVCONTROLNONFATALREPORTINGEN = delay_CFGDEVCONTROLNONFATALREPORTINGEN;
assign #(out_delay) CFGDEVCONTROLNOSNOOPEN = delay_CFGDEVCONTROLNOSNOOPEN;
assign #(out_delay) CFGDEVCONTROLPHANTOMEN = delay_CFGDEVCONTROLPHANTOMEN;
assign #(out_delay) CFGDEVCONTROLURERRREPORTINGEN = delay_CFGDEVCONTROLURERRREPORTINGEN;
assign #(out_delay) CFGDEVSTATUSCORRERRDETECTED = delay_CFGDEVSTATUSCORRERRDETECTED;
assign #(out_delay) CFGDEVSTATUSFATALERRDETECTED = delay_CFGDEVSTATUSFATALERRDETECTED;
assign #(out_delay) CFGDEVSTATUSNONFATALERRDETECTED = delay_CFGDEVSTATUSNONFATALERRDETECTED;
assign #(out_delay) CFGDEVSTATUSURDETECTED = delay_CFGDEVSTATUSURDETECTED;
assign #(out_delay) CFGERRAERHEADERLOGSETN = delay_CFGERRAERHEADERLOGSETN;
assign #(out_delay) CFGERRCPLRDYN = delay_CFGERRCPLRDYN;
assign #(out_delay) CFGINTERRUPTDO = delay_CFGINTERRUPTDO;
assign #(out_delay) CFGINTERRUPTMMENABLE = delay_CFGINTERRUPTMMENABLE;
assign #(out_delay) CFGINTERRUPTMSIENABLE = delay_CFGINTERRUPTMSIENABLE;
assign #(out_delay) CFGINTERRUPTMSIXENABLE = delay_CFGINTERRUPTMSIXENABLE;
assign #(out_delay) CFGINTERRUPTMSIXFM = delay_CFGINTERRUPTMSIXFM;
assign #(out_delay) CFGINTERRUPTRDYN = delay_CFGINTERRUPTRDYN;
assign #(out_delay) CFGLINKCONTROLASPMCONTROL = delay_CFGLINKCONTROLASPMCONTROL;
assign #(out_delay) CFGLINKCONTROLAUTOBANDWIDTHINTEN = delay_CFGLINKCONTROLAUTOBANDWIDTHINTEN;
assign #(out_delay) CFGLINKCONTROLBANDWIDTHINTEN = delay_CFGLINKCONTROLBANDWIDTHINTEN;
assign #(out_delay) CFGLINKCONTROLCLOCKPMEN = delay_CFGLINKCONTROLCLOCKPMEN;
assign #(out_delay) CFGLINKCONTROLCOMMONCLOCK = delay_CFGLINKCONTROLCOMMONCLOCK;
assign #(out_delay) CFGLINKCONTROLEXTENDEDSYNC = delay_CFGLINKCONTROLEXTENDEDSYNC;
assign #(out_delay) CFGLINKCONTROLHWAUTOWIDTHDIS = delay_CFGLINKCONTROLHWAUTOWIDTHDIS;
assign #(out_delay) CFGLINKCONTROLLINKDISABLE = delay_CFGLINKCONTROLLINKDISABLE;
assign #(out_delay) CFGLINKCONTROLRCB = delay_CFGLINKCONTROLRCB;
assign #(out_delay) CFGLINKCONTROLRETRAINLINK = delay_CFGLINKCONTROLRETRAINLINK;
assign #(out_delay) CFGLINKSTATUSAUTOBANDWIDTHSTATUS = delay_CFGLINKSTATUSAUTOBANDWIDTHSTATUS;
assign #(out_delay) CFGLINKSTATUSBANDWIDTHSTATUS = delay_CFGLINKSTATUSBANDWIDTHSTATUS;
assign #(out_delay) CFGLINKSTATUSCURRENTSPEED = delay_CFGLINKSTATUSCURRENTSPEED;
assign #(out_delay) CFGLINKSTATUSDLLACTIVE = delay_CFGLINKSTATUSDLLACTIVE;
assign #(out_delay) CFGLINKSTATUSLINKTRAINING = delay_CFGLINKSTATUSLINKTRAINING;
assign #(out_delay) CFGLINKSTATUSNEGOTIATEDWIDTH = delay_CFGLINKSTATUSNEGOTIATEDWIDTH;
assign #(out_delay) CFGMGMTDO = delay_CFGMGMTDO;
assign #(out_delay) CFGMGMTRDWRDONEN = delay_CFGMGMTRDWRDONEN;
assign #(out_delay) CFGMSGDATA = delay_CFGMSGDATA;
assign #(out_delay) CFGMSGRECEIVED = delay_CFGMSGRECEIVED;
assign #(out_delay) CFGMSGRECEIVEDASSERTINTA = delay_CFGMSGRECEIVEDASSERTINTA;
assign #(out_delay) CFGMSGRECEIVEDASSERTINTB = delay_CFGMSGRECEIVEDASSERTINTB;
assign #(out_delay) CFGMSGRECEIVEDASSERTINTC = delay_CFGMSGRECEIVEDASSERTINTC;
assign #(out_delay) CFGMSGRECEIVEDASSERTINTD = delay_CFGMSGRECEIVEDASSERTINTD;
assign #(out_delay) CFGMSGRECEIVEDDEASSERTINTA = delay_CFGMSGRECEIVEDDEASSERTINTA;
assign #(out_delay) CFGMSGRECEIVEDDEASSERTINTB = delay_CFGMSGRECEIVEDDEASSERTINTB;
assign #(out_delay) CFGMSGRECEIVEDDEASSERTINTC = delay_CFGMSGRECEIVEDDEASSERTINTC;
assign #(out_delay) CFGMSGRECEIVEDDEASSERTINTD = delay_CFGMSGRECEIVEDDEASSERTINTD;
assign #(out_delay) CFGMSGRECEIVEDERRCOR = delay_CFGMSGRECEIVEDERRCOR;
assign #(out_delay) CFGMSGRECEIVEDERRFATAL = delay_CFGMSGRECEIVEDERRFATAL;
assign #(out_delay) CFGMSGRECEIVEDERRNONFATAL = delay_CFGMSGRECEIVEDERRNONFATAL;
assign #(out_delay) CFGMSGRECEIVEDPMASNAK = delay_CFGMSGRECEIVEDPMASNAK;
assign #(out_delay) CFGMSGRECEIVEDPMETO = delay_CFGMSGRECEIVEDPMETO;
assign #(out_delay) CFGMSGRECEIVEDPMETOACK = delay_CFGMSGRECEIVEDPMETOACK;
assign #(out_delay) CFGMSGRECEIVEDPMPME = delay_CFGMSGRECEIVEDPMPME;
assign #(out_delay) CFGMSGRECEIVEDSETSLOTPOWERLIMIT = delay_CFGMSGRECEIVEDSETSLOTPOWERLIMIT;
assign #(out_delay) CFGMSGRECEIVEDUNLOCK = delay_CFGMSGRECEIVEDUNLOCK;
assign #(out_delay) CFGPCIELINKSTATE = delay_CFGPCIELINKSTATE;
assign #(out_delay) CFGPMCSRPMEEN = delay_CFGPMCSRPMEEN;
assign #(out_delay) CFGPMCSRPMESTATUS = delay_CFGPMCSRPMESTATUS;
assign #(out_delay) CFGPMCSRPOWERSTATE = delay_CFGPMCSRPOWERSTATE;
assign #(out_delay) CFGPMRCVASREQL1N = delay_CFGPMRCVASREQL1N;
assign #(out_delay) CFGPMRCVENTERL1N = delay_CFGPMRCVENTERL1N;
assign #(out_delay) CFGPMRCVENTERL23N = delay_CFGPMRCVENTERL23N;
assign #(out_delay) CFGPMRCVREQACKN = delay_CFGPMRCVREQACKN;
assign #(out_delay) CFGROOTCONTROLPMEINTEN = delay_CFGROOTCONTROLPMEINTEN;
assign #(out_delay) CFGROOTCONTROLSYSERRCORRERREN = delay_CFGROOTCONTROLSYSERRCORRERREN;
assign #(out_delay) CFGROOTCONTROLSYSERRFATALERREN = delay_CFGROOTCONTROLSYSERRFATALERREN;
assign #(out_delay) CFGROOTCONTROLSYSERRNONFATALERREN = delay_CFGROOTCONTROLSYSERRNONFATALERREN;
assign #(out_delay) CFGSLOTCONTROLELECTROMECHILCTLPULSE = delay_CFGSLOTCONTROLELECTROMECHILCTLPULSE;
assign #(out_delay) CFGTRANSACTION = delay_CFGTRANSACTION;
assign #(out_delay) CFGTRANSACTIONADDR = delay_CFGTRANSACTIONADDR;
assign #(out_delay) CFGTRANSACTIONTYPE = delay_CFGTRANSACTIONTYPE;
assign #(out_delay) CFGVCTCVCMAP = delay_CFGVCTCVCMAP;
assign #(out_delay) DBGSCLRA = delay_DBGSCLRA;
assign #(out_delay) DBGSCLRB = delay_DBGSCLRB;
assign #(out_delay) DBGSCLRC = delay_DBGSCLRC;
assign #(out_delay) DBGSCLRD = delay_DBGSCLRD;
assign #(out_delay) DBGSCLRE = delay_DBGSCLRE;
assign #(out_delay) DBGSCLRF = delay_DBGSCLRF;
assign #(out_delay) DBGSCLRG = delay_DBGSCLRG;
assign #(out_delay) DBGSCLRH = delay_DBGSCLRH;
assign #(out_delay) DBGSCLRI = delay_DBGSCLRI;
assign #(out_delay) DBGSCLRJ = delay_DBGSCLRJ;
assign #(out_delay) DBGSCLRK = delay_DBGSCLRK;
assign #(out_delay) DBGVECA = delay_DBGVECA;
assign #(out_delay) DBGVECB = delay_DBGVECB;
assign #(out_delay) DBGVECC = delay_DBGVECC;
assign #(out_delay) DRPDO = delay_DRPDO;
assign #(out_delay) DRPRDY = delay_DRPRDY;
assign #(out_delay) LL2BADDLLPERR = delay_LL2BADDLLPERR;
assign #(out_delay) LL2BADTLPERR = delay_LL2BADTLPERR;
assign #(out_delay) LL2LINKSTATUS = delay_LL2LINKSTATUS;
assign #(out_delay) LL2PROTOCOLERR = delay_LL2PROTOCOLERR;
assign #(out_delay) LL2RECEIVERERR = delay_LL2RECEIVERERR;
assign #(out_delay) LL2REPLAYROERR = delay_LL2REPLAYROERR;
assign #(out_delay) LL2REPLAYTOERR = delay_LL2REPLAYTOERR;
assign #(out_delay) LL2SUSPENDOK = delay_LL2SUSPENDOK;
assign #(out_delay) LL2TFCINIT1SEQ = delay_LL2TFCINIT1SEQ;
assign #(out_delay) LL2TFCINIT2SEQ = delay_LL2TFCINIT2SEQ;
assign #(out_delay) LL2TXIDLE = delay_LL2TXIDLE;
assign #(out_delay) LNKCLKEN = delay_LNKCLKEN;
assign #(out_delay) MIMRXRADDR = delay_MIMRXRADDR;
assign #(out_delay) MIMRXREN = delay_MIMRXREN;
assign #(out_delay) MIMRXWADDR = delay_MIMRXWADDR;
assign #(out_delay) MIMRXWDATA = delay_MIMRXWDATA;
assign #(out_delay) MIMRXWEN = delay_MIMRXWEN;
assign #(out_delay) MIMTXRADDR = delay_MIMTXRADDR;
assign #(out_delay) MIMTXREN = delay_MIMTXREN;
assign #(out_delay) MIMTXWADDR = delay_MIMTXWADDR;
assign #(out_delay) MIMTXWDATA = delay_MIMTXWDATA;
assign #(out_delay) MIMTXWEN = delay_MIMTXWEN;
assign #(out_delay) PIPERX0POLARITY = delay_PIPERX0POLARITY;
assign #(out_delay) PIPERX1POLARITY = delay_PIPERX1POLARITY;
assign #(out_delay) PIPERX2POLARITY = delay_PIPERX2POLARITY;
assign #(out_delay) PIPERX3POLARITY = delay_PIPERX3POLARITY;
assign #(out_delay) PIPERX4POLARITY = delay_PIPERX4POLARITY;
assign #(out_delay) PIPERX5POLARITY = delay_PIPERX5POLARITY;
assign #(out_delay) PIPERX6POLARITY = delay_PIPERX6POLARITY;
assign #(out_delay) PIPERX7POLARITY = delay_PIPERX7POLARITY;
assign #(out_delay) PIPETX0CHARISK = delay_PIPETX0CHARISK;
assign #(out_delay) PIPETX0COMPLIANCE = delay_PIPETX0COMPLIANCE;
assign #(out_delay) PIPETX0DATA = delay_PIPETX0DATA;
assign #(out_delay) PIPETX0ELECIDLE = delay_PIPETX0ELECIDLE;
assign #(out_delay) PIPETX0POWERDOWN = delay_PIPETX0POWERDOWN;
assign #(out_delay) PIPETX1CHARISK = delay_PIPETX1CHARISK;
assign #(out_delay) PIPETX1COMPLIANCE = delay_PIPETX1COMPLIANCE;
assign #(out_delay) PIPETX1DATA = delay_PIPETX1DATA;
assign #(out_delay) PIPETX1ELECIDLE = delay_PIPETX1ELECIDLE;
assign #(out_delay) PIPETX1POWERDOWN = delay_PIPETX1POWERDOWN;
assign #(out_delay) PIPETX2CHARISK = delay_PIPETX2CHARISK;
assign #(out_delay) PIPETX2COMPLIANCE = delay_PIPETX2COMPLIANCE;
assign #(out_delay) PIPETX2DATA = delay_PIPETX2DATA;
assign #(out_delay) PIPETX2ELECIDLE = delay_PIPETX2ELECIDLE;
assign #(out_delay) PIPETX2POWERDOWN = delay_PIPETX2POWERDOWN;
assign #(out_delay) PIPETX3CHARISK = delay_PIPETX3CHARISK;
assign #(out_delay) PIPETX3COMPLIANCE = delay_PIPETX3COMPLIANCE;
assign #(out_delay) PIPETX3DATA = delay_PIPETX3DATA;
assign #(out_delay) PIPETX3ELECIDLE = delay_PIPETX3ELECIDLE;
assign #(out_delay) PIPETX3POWERDOWN = delay_PIPETX3POWERDOWN;
assign #(out_delay) PIPETX4CHARISK = delay_PIPETX4CHARISK;
assign #(out_delay) PIPETX4COMPLIANCE = delay_PIPETX4COMPLIANCE;
assign #(out_delay) PIPETX4DATA = delay_PIPETX4DATA;
assign #(out_delay) PIPETX4ELECIDLE = delay_PIPETX4ELECIDLE;
assign #(out_delay) PIPETX4POWERDOWN = delay_PIPETX4POWERDOWN;
assign #(out_delay) PIPETX5CHARISK = delay_PIPETX5CHARISK;
assign #(out_delay) PIPETX5COMPLIANCE = delay_PIPETX5COMPLIANCE;
assign #(out_delay) PIPETX5DATA = delay_PIPETX5DATA;
assign #(out_delay) PIPETX5ELECIDLE = delay_PIPETX5ELECIDLE;
assign #(out_delay) PIPETX5POWERDOWN = delay_PIPETX5POWERDOWN;
assign #(out_delay) PIPETX6CHARISK = delay_PIPETX6CHARISK;
assign #(out_delay) PIPETX6COMPLIANCE = delay_PIPETX6COMPLIANCE;
assign #(out_delay) PIPETX6DATA = delay_PIPETX6DATA;
assign #(out_delay) PIPETX6ELECIDLE = delay_PIPETX6ELECIDLE;
assign #(out_delay) PIPETX6POWERDOWN = delay_PIPETX6POWERDOWN;
assign #(out_delay) PIPETX7CHARISK = delay_PIPETX7CHARISK;
assign #(out_delay) PIPETX7COMPLIANCE = delay_PIPETX7COMPLIANCE;
assign #(out_delay) PIPETX7DATA = delay_PIPETX7DATA;
assign #(out_delay) PIPETX7ELECIDLE = delay_PIPETX7ELECIDLE;
assign #(out_delay) PIPETX7POWERDOWN = delay_PIPETX7POWERDOWN;
assign #(out_delay) PIPETXDEEMPH = delay_PIPETXDEEMPH;
assign #(out_delay) PIPETXMARGIN = delay_PIPETXMARGIN;
assign #(out_delay) PIPETXRATE = delay_PIPETXRATE;
assign #(out_delay) PIPETXRCVRDET = delay_PIPETXRCVRDET;
assign #(out_delay) PIPETXRESET = delay_PIPETXRESET;
assign #(out_delay) PL2L0REQ = delay_PL2L0REQ;
assign #(out_delay) PL2LINKUP = delay_PL2LINKUP;
assign #(out_delay) PL2RECEIVERERR = delay_PL2RECEIVERERR;
assign #(out_delay) PL2RECOVERY = delay_PL2RECOVERY;
assign #(out_delay) PL2RXELECIDLE = delay_PL2RXELECIDLE;
assign #(out_delay) PL2RXPMSTATE = delay_PL2RXPMSTATE;
assign #(out_delay) PL2SUSPENDOK = delay_PL2SUSPENDOK;
assign #(out_delay) PLDBGVEC = delay_PLDBGVEC;
assign #(out_delay) PLDIRECTEDCHANGEDONE = delay_PLDIRECTEDCHANGEDONE;
assign #(out_delay) PLINITIALLINKWIDTH = delay_PLINITIALLINKWIDTH;
assign #(out_delay) PLLANEREVERSALMODE = delay_PLLANEREVERSALMODE;
assign #(out_delay) PLLINKGEN2CAP = delay_PLLINKGEN2CAP;
assign #(out_delay) PLLINKPARTNERGEN2SUPPORTED = delay_PLLINKPARTNERGEN2SUPPORTED;
assign #(out_delay) PLLINKUPCFGCAP = delay_PLLINKUPCFGCAP;
assign #(out_delay) PLLTSSMSTATE = delay_PLLTSSMSTATE;
assign #(out_delay) PLPHYLNKUPN = delay_PLPHYLNKUPN;
assign #(out_delay) PLRECEIVEDHOTRST = delay_PLRECEIVEDHOTRST;
assign #(out_delay) PLRXPMSTATE = delay_PLRXPMSTATE;
assign #(out_delay) PLSELLNKRATE = delay_PLSELLNKRATE;
assign #(out_delay) PLSELLNKWIDTH = delay_PLSELLNKWIDTH;
assign #(out_delay) PLTXPMSTATE = delay_PLTXPMSTATE;
assign #(out_delay) RECEIVEDFUNCLVLRSTN = delay_RECEIVEDFUNCLVLRSTN;
assign #(out_delay) TL2ASPMSUSPENDCREDITCHECKOK = delay_TL2ASPMSUSPENDCREDITCHECKOK;
assign #(out_delay) TL2ASPMSUSPENDREQ = delay_TL2ASPMSUSPENDREQ;
assign #(out_delay) TL2ERRFCPE = delay_TL2ERRFCPE;
assign #(out_delay) TL2ERRHDR = delay_TL2ERRHDR;
assign #(out_delay) TL2ERRMALFORMED = delay_TL2ERRMALFORMED;
assign #(out_delay) TL2ERRRXOVERFLOW = delay_TL2ERRRXOVERFLOW;
assign #(out_delay) TL2PPMSUSPENDOK = delay_TL2PPMSUSPENDOK;
assign #(out_delay) TRNFCCPLD = delay_TRNFCCPLD;
assign #(out_delay) TRNFCCPLH = delay_TRNFCCPLH;
assign #(out_delay) TRNFCNPD = delay_TRNFCNPD;
assign #(out_delay) TRNFCNPH = delay_TRNFCNPH;
assign #(out_delay) TRNFCPD = delay_TRNFCPD;
assign #(out_delay) TRNFCPH = delay_TRNFCPH;
assign #(out_delay) TRNLNKUP = delay_TRNLNKUP;
assign #(out_delay) TRNRBARHIT = delay_TRNRBARHIT;
assign #(out_delay) TRNRD = delay_TRNRD;
assign #(out_delay) TRNRDLLPDATA = delay_TRNRDLLPDATA;
assign #(out_delay) TRNRDLLPSRCRDY = delay_TRNRDLLPSRCRDY;
assign #(out_delay) TRNRECRCERR = delay_TRNRECRCERR;
assign #(out_delay) TRNREOF = delay_TRNREOF;
assign #(out_delay) TRNRERRFWD = delay_TRNRERRFWD;
assign #(out_delay) TRNRREM = delay_TRNRREM;
assign #(out_delay) TRNRSOF = delay_TRNRSOF;
assign #(out_delay) TRNRSRCDSC = delay_TRNRSRCDSC;
assign #(out_delay) TRNRSRCRDY = delay_TRNRSRCRDY;
assign #(out_delay) TRNTBUFAV = delay_TRNTBUFAV;
assign #(out_delay) TRNTCFGREQ = delay_TRNTCFGREQ;
assign #(out_delay) TRNTDLLPDSTRDY = delay_TRNTDLLPDSTRDY;
assign #(out_delay) TRNTDSTRDY = delay_TRNTDSTRDY;
assign #(out_delay) TRNTERRDROP = delay_TRNTERRDROP;
assign #(out_delay) USERRSTN = delay_USERRSTN;
`ifndef XIL_TIMING // unisim
assign #(INCLK_DELAY) delay_DRPCLK = DRPCLK;
assign #(INCLK_DELAY) delay_PIPECLK = PIPECLK;
assign #(INCLK_DELAY) delay_USERCLK = USERCLK;
assign #(INCLK_DELAY) delay_USERCLK2 = USERCLK2;
assign #(in_delay) delay_CFGAERINTERRUPTMSGNUM = CFGAERINTERRUPTMSGNUM;
assign #(in_delay) delay_CFGDEVID = CFGDEVID;
assign #(in_delay) delay_CFGDSBUSNUMBER = CFGDSBUSNUMBER;
assign #(in_delay) delay_CFGDSDEVICENUMBER = CFGDSDEVICENUMBER;
assign #(in_delay) delay_CFGDSFUNCTIONNUMBER = CFGDSFUNCTIONNUMBER;
assign #(in_delay) delay_CFGDSN = CFGDSN;
assign #(in_delay) delay_CFGERRACSN = CFGERRACSN;
assign #(in_delay) delay_CFGERRAERHEADERLOG = CFGERRAERHEADERLOG;
assign #(in_delay) delay_CFGERRATOMICEGRESSBLOCKEDN = CFGERRATOMICEGRESSBLOCKEDN;
assign #(in_delay) delay_CFGERRCORN = CFGERRCORN;
assign #(in_delay) delay_CFGERRCPLABORTN = CFGERRCPLABORTN;
assign #(in_delay) delay_CFGERRCPLTIMEOUTN = CFGERRCPLTIMEOUTN;
assign #(in_delay) delay_CFGERRCPLUNEXPECTN = CFGERRCPLUNEXPECTN;
assign #(in_delay) delay_CFGERRECRCN = CFGERRECRCN;
assign #(in_delay) delay_CFGERRINTERNALCORN = CFGERRINTERNALCORN;
assign #(in_delay) delay_CFGERRINTERNALUNCORN = CFGERRINTERNALUNCORN;
assign #(in_delay) delay_CFGERRLOCKEDN = CFGERRLOCKEDN;
assign #(in_delay) delay_CFGERRMALFORMEDN = CFGERRMALFORMEDN;
assign #(in_delay) delay_CFGERRMCBLOCKEDN = CFGERRMCBLOCKEDN;
assign #(in_delay) delay_CFGERRNORECOVERYN = CFGERRNORECOVERYN;
assign #(in_delay) delay_CFGERRPOISONEDN = CFGERRPOISONEDN;
assign #(in_delay) delay_CFGERRPOSTEDN = CFGERRPOSTEDN;
assign #(in_delay) delay_CFGERRTLPCPLHEADER = CFGERRTLPCPLHEADER;
assign #(in_delay) delay_CFGERRURN = CFGERRURN;
assign #(in_delay) delay_CFGFORCECOMMONCLOCKOFF = CFGFORCECOMMONCLOCKOFF;
assign #(in_delay) delay_CFGFORCEEXTENDEDSYNCON = CFGFORCEEXTENDEDSYNCON;
assign #(in_delay) delay_CFGFORCEMPS = CFGFORCEMPS;
assign #(in_delay) delay_CFGINTERRUPTASSERTN = CFGINTERRUPTASSERTN;
assign #(in_delay) delay_CFGINTERRUPTDI = CFGINTERRUPTDI;
assign #(in_delay) delay_CFGINTERRUPTN = CFGINTERRUPTN;
assign #(in_delay) delay_CFGINTERRUPTSTATN = CFGINTERRUPTSTATN;
assign #(in_delay) delay_CFGMGMTBYTEENN = CFGMGMTBYTEENN;
assign #(in_delay) delay_CFGMGMTDI = CFGMGMTDI;
assign #(in_delay) delay_CFGMGMTDWADDR = CFGMGMTDWADDR;
assign #(in_delay) delay_CFGMGMTRDENN = CFGMGMTRDENN;
assign #(in_delay) delay_CFGMGMTWRENN = CFGMGMTWRENN;
assign #(in_delay) delay_CFGMGMTWRREADONLYN = CFGMGMTWRREADONLYN;
assign #(in_delay) delay_CFGMGMTWRRW1CASRWN = CFGMGMTWRRW1CASRWN;
assign #(in_delay) delay_CFGPCIECAPINTERRUPTMSGNUM = CFGPCIECAPINTERRUPTMSGNUM;
assign #(in_delay) delay_CFGPMFORCESTATE = CFGPMFORCESTATE;
assign #(in_delay) delay_CFGPMFORCESTATEENN = CFGPMFORCESTATEENN;
assign #(in_delay) delay_CFGPMHALTASPML0SN = CFGPMHALTASPML0SN;
assign #(in_delay) delay_CFGPMHALTASPML1N = CFGPMHALTASPML1N;
assign #(in_delay) delay_CFGPMSENDPMETON = CFGPMSENDPMETON;
assign #(in_delay) delay_CFGPMTURNOFFOKN = CFGPMTURNOFFOKN;
assign #(in_delay) delay_CFGPMWAKEN = CFGPMWAKEN;
assign #(in_delay) delay_CFGPORTNUMBER = CFGPORTNUMBER;
assign #(in_delay) delay_CFGREVID = CFGREVID;
assign #(in_delay) delay_CFGSUBSYSID = CFGSUBSYSID;
assign #(in_delay) delay_CFGSUBSYSVENDID = CFGSUBSYSVENDID;
assign #(in_delay) delay_CFGTRNPENDINGN = CFGTRNPENDINGN;
assign #(in_delay) delay_CFGVENDID = CFGVENDID;
assign #(in_delay) delay_CMRSTN = CMRSTN;
assign #(in_delay) delay_CMSTICKYRSTN = CMSTICKYRSTN;
assign #(in_delay) delay_DBGMODE = DBGMODE;
assign #(in_delay) delay_DBGSUBMODE = DBGSUBMODE;
assign #(in_delay) delay_DLRSTN = DLRSTN;
assign #(in_delay) delay_DRPADDR = DRPADDR;
assign #(in_delay) delay_DRPDI = DRPDI;
assign #(in_delay) delay_DRPEN = DRPEN;
assign #(in_delay) delay_DRPWE = DRPWE;
assign #(in_delay) delay_FUNCLVLRSTN = FUNCLVLRSTN;
assign #(in_delay) delay_LL2SENDASREQL1 = LL2SENDASREQL1;
assign #(in_delay) delay_LL2SENDENTERL1 = LL2SENDENTERL1;
assign #(in_delay) delay_LL2SENDENTERL23 = LL2SENDENTERL23;
assign #(in_delay) delay_LL2SENDPMACK = LL2SENDPMACK;
assign #(in_delay) delay_LL2SUSPENDNOW = LL2SUSPENDNOW;
assign #(in_delay) delay_LL2TLPRCV = LL2TLPRCV;
assign #(in_delay) delay_MIMRXRDATA = MIMRXRDATA;
assign #(in_delay) delay_MIMTXRDATA = MIMTXRDATA;
assign #(in_delay) delay_PIPERX0CHANISALIGNED = PIPERX0CHANISALIGNED;
assign #(in_delay) delay_PIPERX0CHARISK = PIPERX0CHARISK;
assign #(in_delay) delay_PIPERX0DATA = PIPERX0DATA;
assign #(in_delay) delay_PIPERX0ELECIDLE = PIPERX0ELECIDLE;
assign #(in_delay) delay_PIPERX0PHYSTATUS = PIPERX0PHYSTATUS;
assign #(in_delay) delay_PIPERX0STATUS = PIPERX0STATUS;
assign #(in_delay) delay_PIPERX0VALID = PIPERX0VALID;
assign #(in_delay) delay_PIPERX1CHANISALIGNED = PIPERX1CHANISALIGNED;
assign #(in_delay) delay_PIPERX1CHARISK = PIPERX1CHARISK;
assign #(in_delay) delay_PIPERX1DATA = PIPERX1DATA;
assign #(in_delay) delay_PIPERX1ELECIDLE = PIPERX1ELECIDLE;
assign #(in_delay) delay_PIPERX1PHYSTATUS = PIPERX1PHYSTATUS;
assign #(in_delay) delay_PIPERX1STATUS = PIPERX1STATUS;
assign #(in_delay) delay_PIPERX1VALID = PIPERX1VALID;
assign #(in_delay) delay_PIPERX2CHANISALIGNED = PIPERX2CHANISALIGNED;
assign #(in_delay) delay_PIPERX2CHARISK = PIPERX2CHARISK;
assign #(in_delay) delay_PIPERX2DATA = PIPERX2DATA;
assign #(in_delay) delay_PIPERX2ELECIDLE = PIPERX2ELECIDLE;
assign #(in_delay) delay_PIPERX2PHYSTATUS = PIPERX2PHYSTATUS;
assign #(in_delay) delay_PIPERX2STATUS = PIPERX2STATUS;
assign #(in_delay) delay_PIPERX2VALID = PIPERX2VALID;
assign #(in_delay) delay_PIPERX3CHANISALIGNED = PIPERX3CHANISALIGNED;
assign #(in_delay) delay_PIPERX3CHARISK = PIPERX3CHARISK;
assign #(in_delay) delay_PIPERX3DATA = PIPERX3DATA;
assign #(in_delay) delay_PIPERX3ELECIDLE = PIPERX3ELECIDLE;
assign #(in_delay) delay_PIPERX3PHYSTATUS = PIPERX3PHYSTATUS;
assign #(in_delay) delay_PIPERX3STATUS = PIPERX3STATUS;
assign #(in_delay) delay_PIPERX3VALID = PIPERX3VALID;
assign #(in_delay) delay_PIPERX4CHANISALIGNED = PIPERX4CHANISALIGNED;
assign #(in_delay) delay_PIPERX4CHARISK = PIPERX4CHARISK;
assign #(in_delay) delay_PIPERX4DATA = PIPERX4DATA;
assign #(in_delay) delay_PIPERX4ELECIDLE = PIPERX4ELECIDLE;
assign #(in_delay) delay_PIPERX4PHYSTATUS = PIPERX4PHYSTATUS;
assign #(in_delay) delay_PIPERX4STATUS = PIPERX4STATUS;
assign #(in_delay) delay_PIPERX4VALID = PIPERX4VALID;
assign #(in_delay) delay_PIPERX5CHANISALIGNED = PIPERX5CHANISALIGNED;
assign #(in_delay) delay_PIPERX5CHARISK = PIPERX5CHARISK;
assign #(in_delay) delay_PIPERX5DATA = PIPERX5DATA;
assign #(in_delay) delay_PIPERX5ELECIDLE = PIPERX5ELECIDLE;
assign #(in_delay) delay_PIPERX5PHYSTATUS = PIPERX5PHYSTATUS;
assign #(in_delay) delay_PIPERX5STATUS = PIPERX5STATUS;
assign #(in_delay) delay_PIPERX5VALID = PIPERX5VALID;
assign #(in_delay) delay_PIPERX6CHANISALIGNED = PIPERX6CHANISALIGNED;
assign #(in_delay) delay_PIPERX6CHARISK = PIPERX6CHARISK;
assign #(in_delay) delay_PIPERX6DATA = PIPERX6DATA;
assign #(in_delay) delay_PIPERX6ELECIDLE = PIPERX6ELECIDLE;
assign #(in_delay) delay_PIPERX6PHYSTATUS = PIPERX6PHYSTATUS;
assign #(in_delay) delay_PIPERX6STATUS = PIPERX6STATUS;
assign #(in_delay) delay_PIPERX6VALID = PIPERX6VALID;
assign #(in_delay) delay_PIPERX7CHANISALIGNED = PIPERX7CHANISALIGNED;
assign #(in_delay) delay_PIPERX7CHARISK = PIPERX7CHARISK;
assign #(in_delay) delay_PIPERX7DATA = PIPERX7DATA;
assign #(in_delay) delay_PIPERX7ELECIDLE = PIPERX7ELECIDLE;
assign #(in_delay) delay_PIPERX7PHYSTATUS = PIPERX7PHYSTATUS;
assign #(in_delay) delay_PIPERX7STATUS = PIPERX7STATUS;
assign #(in_delay) delay_PIPERX7VALID = PIPERX7VALID;
assign #(in_delay) delay_PL2DIRECTEDLSTATE = PL2DIRECTEDLSTATE;
assign #(in_delay) delay_PLDBGMODE = PLDBGMODE;
assign #(in_delay) delay_PLDIRECTEDLINKAUTON = PLDIRECTEDLINKAUTON;
assign #(in_delay) delay_PLDIRECTEDLINKCHANGE = PLDIRECTEDLINKCHANGE;
assign #(in_delay) delay_PLDIRECTEDLINKSPEED = PLDIRECTEDLINKSPEED;
assign #(in_delay) delay_PLDIRECTEDLINKWIDTH = PLDIRECTEDLINKWIDTH;
assign #(in_delay) delay_PLDIRECTEDLTSSMNEW = PLDIRECTEDLTSSMNEW;
assign #(in_delay) delay_PLDIRECTEDLTSSMNEWVLD = PLDIRECTEDLTSSMNEWVLD;
assign #(in_delay) delay_PLDIRECTEDLTSSMSTALL = PLDIRECTEDLTSSMSTALL;
assign #(in_delay) delay_PLDOWNSTREAMDEEMPHSOURCE = PLDOWNSTREAMDEEMPHSOURCE;
assign #(in_delay) delay_PLRSTN = PLRSTN;
assign #(in_delay) delay_PLTRANSMITHOTRST = PLTRANSMITHOTRST;
assign #(in_delay) delay_PLUPSTREAMPREFERDEEMPH = PLUPSTREAMPREFERDEEMPH;
assign #(in_delay) delay_SYSRSTN = SYSRSTN;
assign #(in_delay) delay_TL2ASPMSUSPENDCREDITCHECK = TL2ASPMSUSPENDCREDITCHECK;
assign #(in_delay) delay_TL2PPMSUSPENDREQ = TL2PPMSUSPENDREQ;
assign #(in_delay) delay_TLRSTN = TLRSTN;
assign #(in_delay) delay_TRNFCSEL = TRNFCSEL;
assign #(in_delay) delay_TRNRDSTRDY = TRNRDSTRDY;
assign #(in_delay) delay_TRNRFCPRET = TRNRFCPRET;
assign #(in_delay) delay_TRNRNPOK = TRNRNPOK;
assign #(in_delay) delay_TRNRNPREQ = TRNRNPREQ;
assign #(in_delay) delay_TRNTCFGGNT = TRNTCFGGNT;
assign #(in_delay) delay_TRNTD = TRNTD;
assign #(in_delay) delay_TRNTDLLPDATA = TRNTDLLPDATA;
assign #(in_delay) delay_TRNTDLLPSRCRDY = TRNTDLLPSRCRDY;
assign #(in_delay) delay_TRNTECRCGEN = TRNTECRCGEN;
assign #(in_delay) delay_TRNTEOF = TRNTEOF;
assign #(in_delay) delay_TRNTERRFWD = TRNTERRFWD;
assign #(in_delay) delay_TRNTREM = TRNTREM;
assign #(in_delay) delay_TRNTSOF = TRNTSOF;
assign #(in_delay) delay_TRNTSRCDSC = TRNTSRCDSC;
assign #(in_delay) delay_TRNTSRCRDY = TRNTSRCRDY;
assign #(in_delay) delay_TRNTSTR = TRNTSTR;
`endif // `ifndef XIL_TIMING
`ifdef XIL_TIMING //Simprim
assign delay_SYSRSTN = SYSRSTN;
`endif
B_PCIE_2_1 #(
.AER_BASE_PTR (AER_BASE_PTR),
.AER_CAP_ECRC_CHECK_CAPABLE (AER_CAP_ECRC_CHECK_CAPABLE),
.AER_CAP_ECRC_GEN_CAPABLE (AER_CAP_ECRC_GEN_CAPABLE),
.AER_CAP_ID (AER_CAP_ID),
.AER_CAP_MULTIHEADER (AER_CAP_MULTIHEADER),
.AER_CAP_NEXTPTR (AER_CAP_NEXTPTR),
.AER_CAP_ON (AER_CAP_ON),
.AER_CAP_OPTIONAL_ERR_SUPPORT (AER_CAP_OPTIONAL_ERR_SUPPORT),
.AER_CAP_PERMIT_ROOTERR_UPDATE (AER_CAP_PERMIT_ROOTERR_UPDATE),
.AER_CAP_VERSION (AER_CAP_VERSION),
.ALLOW_X8_GEN2 (ALLOW_X8_GEN2),
.BAR0 (BAR0),
.BAR1 (BAR1),
.BAR2 (BAR2),
.BAR3 (BAR3),
.BAR4 (BAR4),
.BAR5 (BAR5),
.CAPABILITIES_PTR (CAPABILITIES_PTR),
.CARDBUS_CIS_POINTER (CARDBUS_CIS_POINTER),
.CFG_ECRC_ERR_CPLSTAT (CFG_ECRC_ERR_CPLSTAT),
.CLASS_CODE (CLASS_CODE),
.CMD_INTX_IMPLEMENTED (CMD_INTX_IMPLEMENTED),
.CPL_TIMEOUT_DISABLE_SUPPORTED (CPL_TIMEOUT_DISABLE_SUPPORTED),
.CPL_TIMEOUT_RANGES_SUPPORTED (CPL_TIMEOUT_RANGES_SUPPORTED),
.CRM_MODULE_RSTS (CRM_MODULE_RSTS),
.DEV_CAP2_ARI_FORWARDING_SUPPORTED (DEV_CAP2_ARI_FORWARDING_SUPPORTED),
.DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED (DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED),
.DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED (DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED),
.DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED (DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED),
.DEV_CAP2_CAS128_COMPLETER_SUPPORTED (DEV_CAP2_CAS128_COMPLETER_SUPPORTED),
.DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED (DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED),
.DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED (DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED),
.DEV_CAP2_LTR_MECHANISM_SUPPORTED (DEV_CAP2_LTR_MECHANISM_SUPPORTED),
.DEV_CAP2_MAX_ENDEND_TLP_PREFIXES (DEV_CAP2_MAX_ENDEND_TLP_PREFIXES),
.DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING (DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING),
.DEV_CAP2_TPH_COMPLETER_SUPPORTED (DEV_CAP2_TPH_COMPLETER_SUPPORTED),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE (DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE (DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE),
.DEV_CAP_ENDPOINT_L0S_LATENCY (DEV_CAP_ENDPOINT_L0S_LATENCY),
.DEV_CAP_ENDPOINT_L1_LATENCY (DEV_CAP_ENDPOINT_L1_LATENCY),
.DEV_CAP_EXT_TAG_SUPPORTED (DEV_CAP_EXT_TAG_SUPPORTED),
.DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE (DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE),
.DEV_CAP_MAX_PAYLOAD_SUPPORTED (DEV_CAP_MAX_PAYLOAD_SUPPORTED),
.DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT (DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT),
.DEV_CAP_ROLE_BASED_ERROR (DEV_CAP_ROLE_BASED_ERROR),
.DEV_CAP_RSVD_14_12 (DEV_CAP_RSVD_14_12),
.DEV_CAP_RSVD_17_16 (DEV_CAP_RSVD_17_16),
.DEV_CAP_RSVD_31_29 (DEV_CAP_RSVD_31_29),
.DEV_CONTROL_AUX_POWER_SUPPORTED (DEV_CONTROL_AUX_POWER_SUPPORTED),
.DEV_CONTROL_EXT_TAG_DEFAULT (DEV_CONTROL_EXT_TAG_DEFAULT),
.DISABLE_ASPM_L1_TIMER (DISABLE_ASPM_L1_TIMER),
.DISABLE_BAR_FILTERING (DISABLE_BAR_FILTERING),
.DISABLE_ERR_MSG (DISABLE_ERR_MSG),
.DISABLE_ID_CHECK (DISABLE_ID_CHECK),
.DISABLE_LANE_REVERSAL (DISABLE_LANE_REVERSAL),
.DISABLE_LOCKED_FILTER (DISABLE_LOCKED_FILTER),
.DISABLE_PPM_FILTER (DISABLE_PPM_FILTER),
.DISABLE_RX_POISONED_RESP (DISABLE_RX_POISONED_RESP),
.DISABLE_RX_TC_FILTER (DISABLE_RX_TC_FILTER),
.DISABLE_SCRAMBLING (DISABLE_SCRAMBLING),
.DNSTREAM_LINK_NUM (DNSTREAM_LINK_NUM),
.DSN_BASE_PTR (DSN_BASE_PTR),
.DSN_CAP_ID (DSN_CAP_ID),
.DSN_CAP_NEXTPTR (DSN_CAP_NEXTPTR),
.DSN_CAP_ON (DSN_CAP_ON),
.DSN_CAP_VERSION (DSN_CAP_VERSION),
.ENABLE_MSG_ROUTE (ENABLE_MSG_ROUTE),
.ENABLE_RX_TD_ECRC_TRIM (ENABLE_RX_TD_ECRC_TRIM),
.ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED (ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED),
.ENTER_RVRY_EI_L0 (ENTER_RVRY_EI_L0),
.EXIT_LOOPBACK_ON_EI (EXIT_LOOPBACK_ON_EI),
.EXPANSION_ROM (EXPANSION_ROM),
.EXT_CFG_CAP_PTR (EXT_CFG_CAP_PTR),
.EXT_CFG_XP_CAP_PTR (EXT_CFG_XP_CAP_PTR),
.HEADER_TYPE (HEADER_TYPE),
.INFER_EI (INFER_EI),
.INTERRUPT_PIN (INTERRUPT_PIN),
.INTERRUPT_STAT_AUTO (INTERRUPT_STAT_AUTO),
.IS_SWITCH (IS_SWITCH),
.LAST_CONFIG_DWORD (LAST_CONFIG_DWORD),
.LINK_CAP_ASPM_OPTIONALITY (LINK_CAP_ASPM_OPTIONALITY),
.LINK_CAP_ASPM_SUPPORT (LINK_CAP_ASPM_SUPPORT),
.LINK_CAP_CLOCK_POWER_MANAGEMENT (LINK_CAP_CLOCK_POWER_MANAGEMENT),
.LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP (LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 (LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 (LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2),
.LINK_CAP_L0S_EXIT_LATENCY_GEN1 (LINK_CAP_L0S_EXIT_LATENCY_GEN1),
.LINK_CAP_L0S_EXIT_LATENCY_GEN2 (LINK_CAP_L0S_EXIT_LATENCY_GEN2),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 (LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 (LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2),
.LINK_CAP_L1_EXIT_LATENCY_GEN1 (LINK_CAP_L1_EXIT_LATENCY_GEN1),
.LINK_CAP_L1_EXIT_LATENCY_GEN2 (LINK_CAP_L1_EXIT_LATENCY_GEN2),
.LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP (LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP),
.LINK_CAP_MAX_LINK_SPEED (LINK_CAP_MAX_LINK_SPEED),
.LINK_CAP_MAX_LINK_WIDTH (LINK_CAP_MAX_LINK_WIDTH),
.LINK_CAP_RSVD_23 (LINK_CAP_RSVD_23),
.LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE (LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE),
.LINK_CONTROL_RCB (LINK_CONTROL_RCB),
.LINK_CTRL2_DEEMPHASIS (LINK_CTRL2_DEEMPHASIS),
.LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE (LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE),
.LINK_CTRL2_TARGET_LINK_SPEED (LINK_CTRL2_TARGET_LINK_SPEED),
.LINK_STATUS_SLOT_CLOCK_CONFIG (LINK_STATUS_SLOT_CLOCK_CONFIG),
.LL_ACK_TIMEOUT (LL_ACK_TIMEOUT),
.LL_ACK_TIMEOUT_EN (LL_ACK_TIMEOUT_EN),
.LL_ACK_TIMEOUT_FUNC (LL_ACK_TIMEOUT_FUNC),
.LL_REPLAY_TIMEOUT (LL_REPLAY_TIMEOUT),
.LL_REPLAY_TIMEOUT_EN (LL_REPLAY_TIMEOUT_EN),
.LL_REPLAY_TIMEOUT_FUNC (LL_REPLAY_TIMEOUT_FUNC),
.LTSSM_MAX_LINK_WIDTH (LTSSM_MAX_LINK_WIDTH),
.MPS_FORCE (MPS_FORCE),
.MSIX_BASE_PTR (MSIX_BASE_PTR),
.MSIX_CAP_ID (MSIX_CAP_ID),
.MSIX_CAP_NEXTPTR (MSIX_CAP_NEXTPTR),
.MSIX_CAP_ON (MSIX_CAP_ON),
.MSIX_CAP_PBA_BIR (MSIX_CAP_PBA_BIR),
.MSIX_CAP_PBA_OFFSET (MSIX_CAP_PBA_OFFSET),
.MSIX_CAP_TABLE_BIR (MSIX_CAP_TABLE_BIR),
.MSIX_CAP_TABLE_OFFSET (MSIX_CAP_TABLE_OFFSET),
.MSIX_CAP_TABLE_SIZE (MSIX_CAP_TABLE_SIZE),
.MSI_BASE_PTR (MSI_BASE_PTR),
.MSI_CAP_64_BIT_ADDR_CAPABLE (MSI_CAP_64_BIT_ADDR_CAPABLE),
.MSI_CAP_ID (MSI_CAP_ID),
.MSI_CAP_MULTIMSGCAP (MSI_CAP_MULTIMSGCAP),
.MSI_CAP_MULTIMSG_EXTENSION (MSI_CAP_MULTIMSG_EXTENSION),
.MSI_CAP_NEXTPTR (MSI_CAP_NEXTPTR),
.MSI_CAP_ON (MSI_CAP_ON),
.MSI_CAP_PER_VECTOR_MASKING_CAPABLE (MSI_CAP_PER_VECTOR_MASKING_CAPABLE),
.N_FTS_COMCLK_GEN1 (N_FTS_COMCLK_GEN1),
.N_FTS_COMCLK_GEN2 (N_FTS_COMCLK_GEN2),
.N_FTS_GEN1 (N_FTS_GEN1),
.N_FTS_GEN2 (N_FTS_GEN2),
.PCIE_BASE_PTR (PCIE_BASE_PTR),
.PCIE_CAP_CAPABILITY_ID (PCIE_CAP_CAPABILITY_ID),
.PCIE_CAP_CAPABILITY_VERSION (PCIE_CAP_CAPABILITY_VERSION),
.PCIE_CAP_DEVICE_PORT_TYPE (PCIE_CAP_DEVICE_PORT_TYPE),
.PCIE_CAP_NEXTPTR (PCIE_CAP_NEXTPTR),
.PCIE_CAP_ON (PCIE_CAP_ON),
.PCIE_CAP_RSVD_15_14 (PCIE_CAP_RSVD_15_14),
.PCIE_CAP_SLOT_IMPLEMENTED (PCIE_CAP_SLOT_IMPLEMENTED),
.PCIE_REVISION (PCIE_REVISION),
.PL_AUTO_CONFIG (PL_AUTO_CONFIG),
.PL_FAST_TRAIN (PL_FAST_TRAIN),
.PM_ASPML0S_TIMEOUT (PM_ASPML0S_TIMEOUT),
.PM_ASPML0S_TIMEOUT_EN (PM_ASPML0S_TIMEOUT_EN),
.PM_ASPML0S_TIMEOUT_FUNC (PM_ASPML0S_TIMEOUT_FUNC),
.PM_ASPM_FASTEXIT (PM_ASPM_FASTEXIT),
.PM_BASE_PTR (PM_BASE_PTR),
.PM_CAP_AUXCURRENT (PM_CAP_AUXCURRENT),
.PM_CAP_D1SUPPORT (PM_CAP_D1SUPPORT),
.PM_CAP_D2SUPPORT (PM_CAP_D2SUPPORT),
.PM_CAP_DSI (PM_CAP_DSI),
.PM_CAP_ID (PM_CAP_ID),
.PM_CAP_NEXTPTR (PM_CAP_NEXTPTR),
.PM_CAP_ON (PM_CAP_ON),
.PM_CAP_PMESUPPORT (PM_CAP_PMESUPPORT),
.PM_CAP_PME_CLOCK (PM_CAP_PME_CLOCK),
.PM_CAP_RSVD_04 (PM_CAP_RSVD_04),
.PM_CAP_VERSION (PM_CAP_VERSION),
.PM_CSR_B2B3 (PM_CSR_B2B3),
.PM_CSR_BPCCEN (PM_CSR_BPCCEN),
.PM_CSR_NOSOFTRST (PM_CSR_NOSOFTRST),
.PM_DATA0 (PM_DATA0),
.PM_DATA1 (PM_DATA1),
.PM_DATA2 (PM_DATA2),
.PM_DATA3 (PM_DATA3),
.PM_DATA4 (PM_DATA4),
.PM_DATA5 (PM_DATA5),
.PM_DATA6 (PM_DATA6),
.PM_DATA7 (PM_DATA7),
.PM_DATA_SCALE0 (PM_DATA_SCALE0),
.PM_DATA_SCALE1 (PM_DATA_SCALE1),
.PM_DATA_SCALE2 (PM_DATA_SCALE2),
.PM_DATA_SCALE3 (PM_DATA_SCALE3),
.PM_DATA_SCALE4 (PM_DATA_SCALE4),
.PM_DATA_SCALE5 (PM_DATA_SCALE5),
.PM_DATA_SCALE6 (PM_DATA_SCALE6),
.PM_DATA_SCALE7 (PM_DATA_SCALE7),
.PM_MF (PM_MF),
.RBAR_BASE_PTR (RBAR_BASE_PTR),
.RBAR_CAP_CONTROL_ENCODEDBAR0 (RBAR_CAP_CONTROL_ENCODEDBAR0),
.RBAR_CAP_CONTROL_ENCODEDBAR1 (RBAR_CAP_CONTROL_ENCODEDBAR1),
.RBAR_CAP_CONTROL_ENCODEDBAR2 (RBAR_CAP_CONTROL_ENCODEDBAR2),
.RBAR_CAP_CONTROL_ENCODEDBAR3 (RBAR_CAP_CONTROL_ENCODEDBAR3),
.RBAR_CAP_CONTROL_ENCODEDBAR4 (RBAR_CAP_CONTROL_ENCODEDBAR4),
.RBAR_CAP_CONTROL_ENCODEDBAR5 (RBAR_CAP_CONTROL_ENCODEDBAR5),
.RBAR_CAP_ID (RBAR_CAP_ID),
.RBAR_CAP_INDEX0 (RBAR_CAP_INDEX0),
.RBAR_CAP_INDEX1 (RBAR_CAP_INDEX1),
.RBAR_CAP_INDEX2 (RBAR_CAP_INDEX2),
.RBAR_CAP_INDEX3 (RBAR_CAP_INDEX3),
.RBAR_CAP_INDEX4 (RBAR_CAP_INDEX4),
.RBAR_CAP_INDEX5 (RBAR_CAP_INDEX5),
.RBAR_CAP_NEXTPTR (RBAR_CAP_NEXTPTR),
.RBAR_CAP_ON (RBAR_CAP_ON),
.RBAR_CAP_SUP0 (RBAR_CAP_SUP0),
.RBAR_CAP_SUP1 (RBAR_CAP_SUP1),
.RBAR_CAP_SUP2 (RBAR_CAP_SUP2),
.RBAR_CAP_SUP3 (RBAR_CAP_SUP3),
.RBAR_CAP_SUP4 (RBAR_CAP_SUP4),
.RBAR_CAP_SUP5 (RBAR_CAP_SUP5),
.RBAR_CAP_VERSION (RBAR_CAP_VERSION),
.RBAR_NUM (RBAR_NUM),
.RECRC_CHK (RECRC_CHK),
.RECRC_CHK_TRIM (RECRC_CHK_TRIM),
.ROOT_CAP_CRS_SW_VISIBILITY (ROOT_CAP_CRS_SW_VISIBILITY),
.RP_AUTO_SPD (RP_AUTO_SPD),
.RP_AUTO_SPD_LOOPCNT (RP_AUTO_SPD_LOOPCNT),
.SELECT_DLL_IF (SELECT_DLL_IF),
.SIM_VERSION (SIM_VERSION),
.SLOT_CAP_ATT_BUTTON_PRESENT (SLOT_CAP_ATT_BUTTON_PRESENT),
.SLOT_CAP_ATT_INDICATOR_PRESENT (SLOT_CAP_ATT_INDICATOR_PRESENT),
.SLOT_CAP_ELEC_INTERLOCK_PRESENT (SLOT_CAP_ELEC_INTERLOCK_PRESENT),
.SLOT_CAP_HOTPLUG_CAPABLE (SLOT_CAP_HOTPLUG_CAPABLE),
.SLOT_CAP_HOTPLUG_SURPRISE (SLOT_CAP_HOTPLUG_SURPRISE),
.SLOT_CAP_MRL_SENSOR_PRESENT (SLOT_CAP_MRL_SENSOR_PRESENT),
.SLOT_CAP_NO_CMD_COMPLETED_SUPPORT (SLOT_CAP_NO_CMD_COMPLETED_SUPPORT),
.SLOT_CAP_PHYSICAL_SLOT_NUM (SLOT_CAP_PHYSICAL_SLOT_NUM),
.SLOT_CAP_POWER_CONTROLLER_PRESENT (SLOT_CAP_POWER_CONTROLLER_PRESENT),
.SLOT_CAP_POWER_INDICATOR_PRESENT (SLOT_CAP_POWER_INDICATOR_PRESENT),
.SLOT_CAP_SLOT_POWER_LIMIT_SCALE (SLOT_CAP_SLOT_POWER_LIMIT_SCALE),
.SLOT_CAP_SLOT_POWER_LIMIT_VALUE (SLOT_CAP_SLOT_POWER_LIMIT_VALUE),
.SPARE_BIT0 (SPARE_BIT0),
.SPARE_BIT1 (SPARE_BIT1),
.SPARE_BIT2 (SPARE_BIT2),
.SPARE_BIT3 (SPARE_BIT3),
.SPARE_BIT4 (SPARE_BIT4),
.SPARE_BIT5 (SPARE_BIT5),
.SPARE_BIT6 (SPARE_BIT6),
.SPARE_BIT7 (SPARE_BIT7),
.SPARE_BIT8 (SPARE_BIT8),
.SPARE_BYTE0 (SPARE_BYTE0),
.SPARE_BYTE1 (SPARE_BYTE1),
.SPARE_BYTE2 (SPARE_BYTE2),
.SPARE_BYTE3 (SPARE_BYTE3),
.SPARE_WORD0 (SPARE_WORD0),
.SPARE_WORD1 (SPARE_WORD1),
.SPARE_WORD2 (SPARE_WORD2),
.SPARE_WORD3 (SPARE_WORD3),
.SSL_MESSAGE_AUTO (SSL_MESSAGE_AUTO),
.TECRC_EP_INV (TECRC_EP_INV),
.TL_RBYPASS (TL_RBYPASS),
.TL_RX_RAM_RADDR_LATENCY (TL_RX_RAM_RADDR_LATENCY),
.TL_RX_RAM_RDATA_LATENCY (TL_RX_RAM_RDATA_LATENCY),
.TL_RX_RAM_WRITE_LATENCY (TL_RX_RAM_WRITE_LATENCY),
.TL_TFC_DISABLE (TL_TFC_DISABLE),
.TL_TX_CHECKS_DISABLE (TL_TX_CHECKS_DISABLE),
.TL_TX_RAM_RADDR_LATENCY (TL_TX_RAM_RADDR_LATENCY),
.TL_TX_RAM_RDATA_LATENCY (TL_TX_RAM_RDATA_LATENCY),
.TL_TX_RAM_WRITE_LATENCY (TL_TX_RAM_WRITE_LATENCY),
.TRN_DW (TRN_DW),
.TRN_NP_FC (TRN_NP_FC),
.UPCONFIG_CAPABLE (UPCONFIG_CAPABLE),
.UPSTREAM_FACING (UPSTREAM_FACING),
.UR_ATOMIC (UR_ATOMIC),
.UR_CFG1 (UR_CFG1),
.UR_INV_REQ (UR_INV_REQ),
.UR_PRS_RESPONSE (UR_PRS_RESPONSE),
.USER_CLK2_DIV2 (USER_CLK2_DIV2),
.USER_CLK_FREQ (USER_CLK_FREQ),
.USE_RID_PINS (USE_RID_PINS),
.VC0_CPL_INFINITE (VC0_CPL_INFINITE),
.VC0_RX_RAM_LIMIT (VC0_RX_RAM_LIMIT),
.VC0_TOTAL_CREDITS_CD (VC0_TOTAL_CREDITS_CD),
.VC0_TOTAL_CREDITS_CH (VC0_TOTAL_CREDITS_CH),
.VC0_TOTAL_CREDITS_NPD (VC0_TOTAL_CREDITS_NPD),
.VC0_TOTAL_CREDITS_NPH (VC0_TOTAL_CREDITS_NPH),
.VC0_TOTAL_CREDITS_PD (VC0_TOTAL_CREDITS_PD),
.VC0_TOTAL_CREDITS_PH (VC0_TOTAL_CREDITS_PH),
.VC0_TX_LASTPACKET (VC0_TX_LASTPACKET),
.VC_BASE_PTR (VC_BASE_PTR),
.VC_CAP_ID (VC_CAP_ID),
.VC_CAP_NEXTPTR (VC_CAP_NEXTPTR),
.VC_CAP_ON (VC_CAP_ON),
.VC_CAP_REJECT_SNOOP_TRANSACTIONS (VC_CAP_REJECT_SNOOP_TRANSACTIONS),
.VC_CAP_VERSION (VC_CAP_VERSION),
.VSEC_BASE_PTR (VSEC_BASE_PTR),
.VSEC_CAP_HDR_ID (VSEC_CAP_HDR_ID),
.VSEC_CAP_HDR_LENGTH (VSEC_CAP_HDR_LENGTH),
.VSEC_CAP_HDR_REVISION (VSEC_CAP_HDR_REVISION),
.VSEC_CAP_ID (VSEC_CAP_ID),
.VSEC_CAP_IS_LINK_VISIBLE (VSEC_CAP_IS_LINK_VISIBLE),
.VSEC_CAP_NEXTPTR (VSEC_CAP_NEXTPTR),
.VSEC_CAP_ON (VSEC_CAP_ON),
.VSEC_CAP_VERSION (VSEC_CAP_VERSION))
B_PCIE_2_1_INST (
.CFGAERECRCCHECKEN (delay_CFGAERECRCCHECKEN),
.CFGAERECRCGENEN (delay_CFGAERECRCGENEN),
.CFGAERROOTERRCORRERRRECEIVED (delay_CFGAERROOTERRCORRERRRECEIVED),
.CFGAERROOTERRCORRERRREPORTINGEN (delay_CFGAERROOTERRCORRERRREPORTINGEN),
.CFGAERROOTERRFATALERRRECEIVED (delay_CFGAERROOTERRFATALERRRECEIVED),
.CFGAERROOTERRFATALERRREPORTINGEN (delay_CFGAERROOTERRFATALERRREPORTINGEN),
.CFGAERROOTERRNONFATALERRRECEIVED (delay_CFGAERROOTERRNONFATALERRRECEIVED),
.CFGAERROOTERRNONFATALERRREPORTINGEN (delay_CFGAERROOTERRNONFATALERRREPORTINGEN),
.CFGBRIDGESERREN (delay_CFGBRIDGESERREN),
.CFGCOMMANDBUSMASTERENABLE (delay_CFGCOMMANDBUSMASTERENABLE),
.CFGCOMMANDINTERRUPTDISABLE (delay_CFGCOMMANDINTERRUPTDISABLE),
.CFGCOMMANDIOENABLE (delay_CFGCOMMANDIOENABLE),
.CFGCOMMANDMEMENABLE (delay_CFGCOMMANDMEMENABLE),
.CFGCOMMANDSERREN (delay_CFGCOMMANDSERREN),
.CFGDEVCONTROL2ARIFORWARDEN (delay_CFGDEVCONTROL2ARIFORWARDEN),
.CFGDEVCONTROL2ATOMICEGRESSBLOCK (delay_CFGDEVCONTROL2ATOMICEGRESSBLOCK),
.CFGDEVCONTROL2ATOMICREQUESTEREN (delay_CFGDEVCONTROL2ATOMICREQUESTEREN),
.CFGDEVCONTROL2CPLTIMEOUTDIS (delay_CFGDEVCONTROL2CPLTIMEOUTDIS),
.CFGDEVCONTROL2CPLTIMEOUTVAL (delay_CFGDEVCONTROL2CPLTIMEOUTVAL),
.CFGDEVCONTROL2IDOCPLEN (delay_CFGDEVCONTROL2IDOCPLEN),
.CFGDEVCONTROL2IDOREQEN (delay_CFGDEVCONTROL2IDOREQEN),
.CFGDEVCONTROL2LTREN (delay_CFGDEVCONTROL2LTREN),
.CFGDEVCONTROL2TLPPREFIXBLOCK (delay_CFGDEVCONTROL2TLPPREFIXBLOCK),
.CFGDEVCONTROLAUXPOWEREN (delay_CFGDEVCONTROLAUXPOWEREN),
.CFGDEVCONTROLCORRERRREPORTINGEN (delay_CFGDEVCONTROLCORRERRREPORTINGEN),
.CFGDEVCONTROLENABLERO (delay_CFGDEVCONTROLENABLERO),
.CFGDEVCONTROLEXTTAGEN (delay_CFGDEVCONTROLEXTTAGEN),
.CFGDEVCONTROLFATALERRREPORTINGEN (delay_CFGDEVCONTROLFATALERRREPORTINGEN),
.CFGDEVCONTROLMAXPAYLOAD (delay_CFGDEVCONTROLMAXPAYLOAD),
.CFGDEVCONTROLMAXREADREQ (delay_CFGDEVCONTROLMAXREADREQ),
.CFGDEVCONTROLNONFATALREPORTINGEN (delay_CFGDEVCONTROLNONFATALREPORTINGEN),
.CFGDEVCONTROLNOSNOOPEN (delay_CFGDEVCONTROLNOSNOOPEN),
.CFGDEVCONTROLPHANTOMEN (delay_CFGDEVCONTROLPHANTOMEN),
.CFGDEVCONTROLURERRREPORTINGEN (delay_CFGDEVCONTROLURERRREPORTINGEN),
.CFGDEVSTATUSCORRERRDETECTED (delay_CFGDEVSTATUSCORRERRDETECTED),
.CFGDEVSTATUSFATALERRDETECTED (delay_CFGDEVSTATUSFATALERRDETECTED),
.CFGDEVSTATUSNONFATALERRDETECTED (delay_CFGDEVSTATUSNONFATALERRDETECTED),
.CFGDEVSTATUSURDETECTED (delay_CFGDEVSTATUSURDETECTED),
.CFGERRAERHEADERLOGSETN (delay_CFGERRAERHEADERLOGSETN),
.CFGERRCPLRDYN (delay_CFGERRCPLRDYN),
.CFGINTERRUPTDO (delay_CFGINTERRUPTDO),
.CFGINTERRUPTMMENABLE (delay_CFGINTERRUPTMMENABLE),
.CFGINTERRUPTMSIENABLE (delay_CFGINTERRUPTMSIENABLE),
.CFGINTERRUPTMSIXENABLE (delay_CFGINTERRUPTMSIXENABLE),
.CFGINTERRUPTMSIXFM (delay_CFGINTERRUPTMSIXFM),
.CFGINTERRUPTRDYN (delay_CFGINTERRUPTRDYN),
.CFGLINKCONTROLASPMCONTROL (delay_CFGLINKCONTROLASPMCONTROL),
.CFGLINKCONTROLAUTOBANDWIDTHINTEN (delay_CFGLINKCONTROLAUTOBANDWIDTHINTEN),
.CFGLINKCONTROLBANDWIDTHINTEN (delay_CFGLINKCONTROLBANDWIDTHINTEN),
.CFGLINKCONTROLCLOCKPMEN (delay_CFGLINKCONTROLCLOCKPMEN),
.CFGLINKCONTROLCOMMONCLOCK (delay_CFGLINKCONTROLCOMMONCLOCK),
.CFGLINKCONTROLEXTENDEDSYNC (delay_CFGLINKCONTROLEXTENDEDSYNC),
.CFGLINKCONTROLHWAUTOWIDTHDIS (delay_CFGLINKCONTROLHWAUTOWIDTHDIS),
.CFGLINKCONTROLLINKDISABLE (delay_CFGLINKCONTROLLINKDISABLE),
.CFGLINKCONTROLRCB (delay_CFGLINKCONTROLRCB),
.CFGLINKCONTROLRETRAINLINK (delay_CFGLINKCONTROLRETRAINLINK),
.CFGLINKSTATUSAUTOBANDWIDTHSTATUS (delay_CFGLINKSTATUSAUTOBANDWIDTHSTATUS),
.CFGLINKSTATUSBANDWIDTHSTATUS (delay_CFGLINKSTATUSBANDWIDTHSTATUS),
.CFGLINKSTATUSCURRENTSPEED (delay_CFGLINKSTATUSCURRENTSPEED),
.CFGLINKSTATUSDLLACTIVE (delay_CFGLINKSTATUSDLLACTIVE),
.CFGLINKSTATUSLINKTRAINING (delay_CFGLINKSTATUSLINKTRAINING),
.CFGLINKSTATUSNEGOTIATEDWIDTH (delay_CFGLINKSTATUSNEGOTIATEDWIDTH),
.CFGMGMTDO (delay_CFGMGMTDO),
.CFGMGMTRDWRDONEN (delay_CFGMGMTRDWRDONEN),
.CFGMSGDATA (delay_CFGMSGDATA),
.CFGMSGRECEIVED (delay_CFGMSGRECEIVED),
.CFGMSGRECEIVEDASSERTINTA (delay_CFGMSGRECEIVEDASSERTINTA),
.CFGMSGRECEIVEDASSERTINTB (delay_CFGMSGRECEIVEDASSERTINTB),
.CFGMSGRECEIVEDASSERTINTC (delay_CFGMSGRECEIVEDASSERTINTC),
.CFGMSGRECEIVEDASSERTINTD (delay_CFGMSGRECEIVEDASSERTINTD),
.CFGMSGRECEIVEDDEASSERTINTA (delay_CFGMSGRECEIVEDDEASSERTINTA),
.CFGMSGRECEIVEDDEASSERTINTB (delay_CFGMSGRECEIVEDDEASSERTINTB),
.CFGMSGRECEIVEDDEASSERTINTC (delay_CFGMSGRECEIVEDDEASSERTINTC),
.CFGMSGRECEIVEDDEASSERTINTD (delay_CFGMSGRECEIVEDDEASSERTINTD),
.CFGMSGRECEIVEDERRCOR (delay_CFGMSGRECEIVEDERRCOR),
.CFGMSGRECEIVEDERRFATAL (delay_CFGMSGRECEIVEDERRFATAL),
.CFGMSGRECEIVEDERRNONFATAL (delay_CFGMSGRECEIVEDERRNONFATAL),
.CFGMSGRECEIVEDPMASNAK (delay_CFGMSGRECEIVEDPMASNAK),
.CFGMSGRECEIVEDPMETO (delay_CFGMSGRECEIVEDPMETO),
.CFGMSGRECEIVEDPMETOACK (delay_CFGMSGRECEIVEDPMETOACK),
.CFGMSGRECEIVEDPMPME (delay_CFGMSGRECEIVEDPMPME),
.CFGMSGRECEIVEDSETSLOTPOWERLIMIT (delay_CFGMSGRECEIVEDSETSLOTPOWERLIMIT),
.CFGMSGRECEIVEDUNLOCK (delay_CFGMSGRECEIVEDUNLOCK),
.CFGPCIELINKSTATE (delay_CFGPCIELINKSTATE),
.CFGPMCSRPMEEN (delay_CFGPMCSRPMEEN),
.CFGPMCSRPMESTATUS (delay_CFGPMCSRPMESTATUS),
.CFGPMCSRPOWERSTATE (delay_CFGPMCSRPOWERSTATE),
.CFGPMRCVASREQL1N (delay_CFGPMRCVASREQL1N),
.CFGPMRCVENTERL1N (delay_CFGPMRCVENTERL1N),
.CFGPMRCVENTERL23N (delay_CFGPMRCVENTERL23N),
.CFGPMRCVREQACKN (delay_CFGPMRCVREQACKN),
.CFGROOTCONTROLPMEINTEN (delay_CFGROOTCONTROLPMEINTEN),
.CFGROOTCONTROLSYSERRCORRERREN (delay_CFGROOTCONTROLSYSERRCORRERREN),
.CFGROOTCONTROLSYSERRFATALERREN (delay_CFGROOTCONTROLSYSERRFATALERREN),
.CFGROOTCONTROLSYSERRNONFATALERREN (delay_CFGROOTCONTROLSYSERRNONFATALERREN),
.CFGSLOTCONTROLELECTROMECHILCTLPULSE (delay_CFGSLOTCONTROLELECTROMECHILCTLPULSE),
.CFGTRANSACTION (delay_CFGTRANSACTION),
.CFGTRANSACTIONADDR (delay_CFGTRANSACTIONADDR),
.CFGTRANSACTIONTYPE (delay_CFGTRANSACTIONTYPE),
.CFGVCTCVCMAP (delay_CFGVCTCVCMAP),
.DBGSCLRA (delay_DBGSCLRA),
.DBGSCLRB (delay_DBGSCLRB),
.DBGSCLRC (delay_DBGSCLRC),
.DBGSCLRD (delay_DBGSCLRD),
.DBGSCLRE (delay_DBGSCLRE),
.DBGSCLRF (delay_DBGSCLRF),
.DBGSCLRG (delay_DBGSCLRG),
.DBGSCLRH (delay_DBGSCLRH),
.DBGSCLRI (delay_DBGSCLRI),
.DBGSCLRJ (delay_DBGSCLRJ),
.DBGSCLRK (delay_DBGSCLRK),
.DBGVECA (delay_DBGVECA),
.DBGVECB (delay_DBGVECB),
.DBGVECC (delay_DBGVECC),
.DRPDO (delay_DRPDO),
.DRPRDY (delay_DRPRDY),
.LL2BADDLLPERR (delay_LL2BADDLLPERR),
.LL2BADTLPERR (delay_LL2BADTLPERR),
.LL2LINKSTATUS (delay_LL2LINKSTATUS),
.LL2PROTOCOLERR (delay_LL2PROTOCOLERR),
.LL2RECEIVERERR (delay_LL2RECEIVERERR),
.LL2REPLAYROERR (delay_LL2REPLAYROERR),
.LL2REPLAYTOERR (delay_LL2REPLAYTOERR),
.LL2SUSPENDOK (delay_LL2SUSPENDOK),
.LL2TFCINIT1SEQ (delay_LL2TFCINIT1SEQ),
.LL2TFCINIT2SEQ (delay_LL2TFCINIT2SEQ),
.LL2TXIDLE (delay_LL2TXIDLE),
.LNKCLKEN (delay_LNKCLKEN),
.MIMRXRADDR (delay_MIMRXRADDR),
.MIMRXREN (delay_MIMRXREN),
.MIMRXWADDR (delay_MIMRXWADDR),
.MIMRXWDATA (delay_MIMRXWDATA),
.MIMRXWEN (delay_MIMRXWEN),
.MIMTXRADDR (delay_MIMTXRADDR),
.MIMTXREN (delay_MIMTXREN),
.MIMTXWADDR (delay_MIMTXWADDR),
.MIMTXWDATA (delay_MIMTXWDATA),
.MIMTXWEN (delay_MIMTXWEN),
.PIPERX0POLARITY (delay_PIPERX0POLARITY),
.PIPERX1POLARITY (delay_PIPERX1POLARITY),
.PIPERX2POLARITY (delay_PIPERX2POLARITY),
.PIPERX3POLARITY (delay_PIPERX3POLARITY),
.PIPERX4POLARITY (delay_PIPERX4POLARITY),
.PIPERX5POLARITY (delay_PIPERX5POLARITY),
.PIPERX6POLARITY (delay_PIPERX6POLARITY),
.PIPERX7POLARITY (delay_PIPERX7POLARITY),
.PIPETX0CHARISK (delay_PIPETX0CHARISK),
.PIPETX0COMPLIANCE (delay_PIPETX0COMPLIANCE),
.PIPETX0DATA (delay_PIPETX0DATA),
.PIPETX0ELECIDLE (delay_PIPETX0ELECIDLE),
.PIPETX0POWERDOWN (delay_PIPETX0POWERDOWN),
.PIPETX1CHARISK (delay_PIPETX1CHARISK),
.PIPETX1COMPLIANCE (delay_PIPETX1COMPLIANCE),
.PIPETX1DATA (delay_PIPETX1DATA),
.PIPETX1ELECIDLE (delay_PIPETX1ELECIDLE),
.PIPETX1POWERDOWN (delay_PIPETX1POWERDOWN),
.PIPETX2CHARISK (delay_PIPETX2CHARISK),
.PIPETX2COMPLIANCE (delay_PIPETX2COMPLIANCE),
.PIPETX2DATA (delay_PIPETX2DATA),
.PIPETX2ELECIDLE (delay_PIPETX2ELECIDLE),
.PIPETX2POWERDOWN (delay_PIPETX2POWERDOWN),
.PIPETX3CHARISK (delay_PIPETX3CHARISK),
.PIPETX3COMPLIANCE (delay_PIPETX3COMPLIANCE),
.PIPETX3DATA (delay_PIPETX3DATA),
.PIPETX3ELECIDLE (delay_PIPETX3ELECIDLE),
.PIPETX3POWERDOWN (delay_PIPETX3POWERDOWN),
.PIPETX4CHARISK (delay_PIPETX4CHARISK),
.PIPETX4COMPLIANCE (delay_PIPETX4COMPLIANCE),
.PIPETX4DATA (delay_PIPETX4DATA),
.PIPETX4ELECIDLE (delay_PIPETX4ELECIDLE),
.PIPETX4POWERDOWN (delay_PIPETX4POWERDOWN),
.PIPETX5CHARISK (delay_PIPETX5CHARISK),
.PIPETX5COMPLIANCE (delay_PIPETX5COMPLIANCE),
.PIPETX5DATA (delay_PIPETX5DATA),
.PIPETX5ELECIDLE (delay_PIPETX5ELECIDLE),
.PIPETX5POWERDOWN (delay_PIPETX5POWERDOWN),
.PIPETX6CHARISK (delay_PIPETX6CHARISK),
.PIPETX6COMPLIANCE (delay_PIPETX6COMPLIANCE),
.PIPETX6DATA (delay_PIPETX6DATA),
.PIPETX6ELECIDLE (delay_PIPETX6ELECIDLE),
.PIPETX6POWERDOWN (delay_PIPETX6POWERDOWN),
.PIPETX7CHARISK (delay_PIPETX7CHARISK),
.PIPETX7COMPLIANCE (delay_PIPETX7COMPLIANCE),
.PIPETX7DATA (delay_PIPETX7DATA),
.PIPETX7ELECIDLE (delay_PIPETX7ELECIDLE),
.PIPETX7POWERDOWN (delay_PIPETX7POWERDOWN),
.PIPETXDEEMPH (delay_PIPETXDEEMPH),
.PIPETXMARGIN (delay_PIPETXMARGIN),
.PIPETXRATE (delay_PIPETXRATE),
.PIPETXRCVRDET (delay_PIPETXRCVRDET),
.PIPETXRESET (delay_PIPETXRESET),
.PL2L0REQ (delay_PL2L0REQ),
.PL2LINKUP (delay_PL2LINKUP),
.PL2RECEIVERERR (delay_PL2RECEIVERERR),
.PL2RECOVERY (delay_PL2RECOVERY),
.PL2RXELECIDLE (delay_PL2RXELECIDLE),
.PL2RXPMSTATE (delay_PL2RXPMSTATE),
.PL2SUSPENDOK (delay_PL2SUSPENDOK),
.PLDBGVEC (delay_PLDBGVEC),
.PLDIRECTEDCHANGEDONE (delay_PLDIRECTEDCHANGEDONE),
.PLINITIALLINKWIDTH (delay_PLINITIALLINKWIDTH),
.PLLANEREVERSALMODE (delay_PLLANEREVERSALMODE),
.PLLINKGEN2CAP (delay_PLLINKGEN2CAP),
.PLLINKPARTNERGEN2SUPPORTED (delay_PLLINKPARTNERGEN2SUPPORTED),
.PLLINKUPCFGCAP (delay_PLLINKUPCFGCAP),
.PLLTSSMSTATE (delay_PLLTSSMSTATE),
.PLPHYLNKUPN (delay_PLPHYLNKUPN),
.PLRECEIVEDHOTRST (delay_PLRECEIVEDHOTRST),
.PLRXPMSTATE (delay_PLRXPMSTATE),
.PLSELLNKRATE (delay_PLSELLNKRATE),
.PLSELLNKWIDTH (delay_PLSELLNKWIDTH),
.PLTXPMSTATE (delay_PLTXPMSTATE),
.RECEIVEDFUNCLVLRSTN (delay_RECEIVEDFUNCLVLRSTN),
.TL2ASPMSUSPENDCREDITCHECKOK (delay_TL2ASPMSUSPENDCREDITCHECKOK),
.TL2ASPMSUSPENDREQ (delay_TL2ASPMSUSPENDREQ),
.TL2ERRFCPE (delay_TL2ERRFCPE),
.TL2ERRHDR (delay_TL2ERRHDR),
.TL2ERRMALFORMED (delay_TL2ERRMALFORMED),
.TL2ERRRXOVERFLOW (delay_TL2ERRRXOVERFLOW),
.TL2PPMSUSPENDOK (delay_TL2PPMSUSPENDOK),
.TRNFCCPLD (delay_TRNFCCPLD),
.TRNFCCPLH (delay_TRNFCCPLH),
.TRNFCNPD (delay_TRNFCNPD),
.TRNFCNPH (delay_TRNFCNPH),
.TRNFCPD (delay_TRNFCPD),
.TRNFCPH (delay_TRNFCPH),
.TRNLNKUP (delay_TRNLNKUP),
.TRNRBARHIT (delay_TRNRBARHIT),
.TRNRD (delay_TRNRD),
.TRNRDLLPDATA (delay_TRNRDLLPDATA),
.TRNRDLLPSRCRDY (delay_TRNRDLLPSRCRDY),
.TRNRECRCERR (delay_TRNRECRCERR),
.TRNREOF (delay_TRNREOF),
.TRNRERRFWD (delay_TRNRERRFWD),
.TRNRREM (delay_TRNRREM),
.TRNRSOF (delay_TRNRSOF),
.TRNRSRCDSC (delay_TRNRSRCDSC),
.TRNRSRCRDY (delay_TRNRSRCRDY),
.TRNTBUFAV (delay_TRNTBUFAV),
.TRNTCFGREQ (delay_TRNTCFGREQ),
.TRNTDLLPDSTRDY (delay_TRNTDLLPDSTRDY),
.TRNTDSTRDY (delay_TRNTDSTRDY),
.TRNTERRDROP (delay_TRNTERRDROP),
.USERRSTN (delay_USERRSTN),
.CFGAERINTERRUPTMSGNUM (delay_CFGAERINTERRUPTMSGNUM),
.CFGDEVID (delay_CFGDEVID),
.CFGDSBUSNUMBER (delay_CFGDSBUSNUMBER),
.CFGDSDEVICENUMBER (delay_CFGDSDEVICENUMBER),
.CFGDSFUNCTIONNUMBER (delay_CFGDSFUNCTIONNUMBER),
.CFGDSN (delay_CFGDSN),
.CFGERRACSN (delay_CFGERRACSN),
.CFGERRAERHEADERLOG (delay_CFGERRAERHEADERLOG),
.CFGERRATOMICEGRESSBLOCKEDN (delay_CFGERRATOMICEGRESSBLOCKEDN),
.CFGERRCORN (delay_CFGERRCORN),
.CFGERRCPLABORTN (delay_CFGERRCPLABORTN),
.CFGERRCPLTIMEOUTN (delay_CFGERRCPLTIMEOUTN),
.CFGERRCPLUNEXPECTN (delay_CFGERRCPLUNEXPECTN),
.CFGERRECRCN (delay_CFGERRECRCN),
.CFGERRINTERNALCORN (delay_CFGERRINTERNALCORN),
.CFGERRINTERNALUNCORN (delay_CFGERRINTERNALUNCORN),
.CFGERRLOCKEDN (delay_CFGERRLOCKEDN),
.CFGERRMALFORMEDN (delay_CFGERRMALFORMEDN),
.CFGERRMCBLOCKEDN (delay_CFGERRMCBLOCKEDN),
.CFGERRNORECOVERYN (delay_CFGERRNORECOVERYN),
.CFGERRPOISONEDN (delay_CFGERRPOISONEDN),
.CFGERRPOSTEDN (delay_CFGERRPOSTEDN),
.CFGERRTLPCPLHEADER (delay_CFGERRTLPCPLHEADER),
.CFGERRURN (delay_CFGERRURN),
.CFGFORCECOMMONCLOCKOFF (delay_CFGFORCECOMMONCLOCKOFF),
.CFGFORCEEXTENDEDSYNCON (delay_CFGFORCEEXTENDEDSYNCON),
.CFGFORCEMPS (delay_CFGFORCEMPS),
.CFGINTERRUPTASSERTN (delay_CFGINTERRUPTASSERTN),
.CFGINTERRUPTDI (delay_CFGINTERRUPTDI),
.CFGINTERRUPTN (delay_CFGINTERRUPTN),
.CFGINTERRUPTSTATN (delay_CFGINTERRUPTSTATN),
.CFGMGMTBYTEENN (delay_CFGMGMTBYTEENN),
.CFGMGMTDI (delay_CFGMGMTDI),
.CFGMGMTDWADDR (delay_CFGMGMTDWADDR),
.CFGMGMTRDENN (delay_CFGMGMTRDENN),
.CFGMGMTWRENN (delay_CFGMGMTWRENN),
.CFGMGMTWRREADONLYN (delay_CFGMGMTWRREADONLYN),
.CFGMGMTWRRW1CASRWN (delay_CFGMGMTWRRW1CASRWN),
.CFGPCIECAPINTERRUPTMSGNUM (delay_CFGPCIECAPINTERRUPTMSGNUM),
.CFGPMFORCESTATE (delay_CFGPMFORCESTATE),
.CFGPMFORCESTATEENN (delay_CFGPMFORCESTATEENN),
.CFGPMHALTASPML0SN (delay_CFGPMHALTASPML0SN),
.CFGPMHALTASPML1N (delay_CFGPMHALTASPML1N),
.CFGPMSENDPMETON (delay_CFGPMSENDPMETON),
.CFGPMTURNOFFOKN (delay_CFGPMTURNOFFOKN),
.CFGPMWAKEN (delay_CFGPMWAKEN),
.CFGPORTNUMBER (delay_CFGPORTNUMBER),
.CFGREVID (delay_CFGREVID),
.CFGSUBSYSID (delay_CFGSUBSYSID),
.CFGSUBSYSVENDID (delay_CFGSUBSYSVENDID),
.CFGTRNPENDINGN (delay_CFGTRNPENDINGN),
.CFGVENDID (delay_CFGVENDID),
.CMRSTN (delay_CMRSTN),
.CMSTICKYRSTN (delay_CMSTICKYRSTN),
.DBGMODE (delay_DBGMODE),
.DBGSUBMODE (delay_DBGSUBMODE),
.DLRSTN (delay_DLRSTN),
.DRPADDR (delay_DRPADDR),
.DRPCLK (delay_DRPCLK),
.DRPDI (delay_DRPDI),
.DRPEN (delay_DRPEN),
.DRPWE (delay_DRPWE),
.FUNCLVLRSTN (delay_FUNCLVLRSTN),
.LL2SENDASREQL1 (delay_LL2SENDASREQL1),
.LL2SENDENTERL1 (delay_LL2SENDENTERL1),
.LL2SENDENTERL23 (delay_LL2SENDENTERL23),
.LL2SENDPMACK (delay_LL2SENDPMACK),
.LL2SUSPENDNOW (delay_LL2SUSPENDNOW),
.LL2TLPRCV (delay_LL2TLPRCV),
.MIMRXRDATA (delay_MIMRXRDATA),
.MIMTXRDATA (delay_MIMTXRDATA),
.PIPECLK (delay_PIPECLK),
.PIPERX0CHANISALIGNED (delay_PIPERX0CHANISALIGNED),
.PIPERX0CHARISK (delay_PIPERX0CHARISK),
.PIPERX0DATA (delay_PIPERX0DATA),
.PIPERX0ELECIDLE (delay_PIPERX0ELECIDLE),
.PIPERX0PHYSTATUS (delay_PIPERX0PHYSTATUS),
.PIPERX0STATUS (delay_PIPERX0STATUS),
.PIPERX0VALID (delay_PIPERX0VALID),
.PIPERX1CHANISALIGNED (delay_PIPERX1CHANISALIGNED),
.PIPERX1CHARISK (delay_PIPERX1CHARISK),
.PIPERX1DATA (delay_PIPERX1DATA),
.PIPERX1ELECIDLE (delay_PIPERX1ELECIDLE),
.PIPERX1PHYSTATUS (delay_PIPERX1PHYSTATUS),
.PIPERX1STATUS (delay_PIPERX1STATUS),
.PIPERX1VALID (delay_PIPERX1VALID),
.PIPERX2CHANISALIGNED (delay_PIPERX2CHANISALIGNED),
.PIPERX2CHARISK (delay_PIPERX2CHARISK),
.PIPERX2DATA (delay_PIPERX2DATA),
.PIPERX2ELECIDLE (delay_PIPERX2ELECIDLE),
.PIPERX2PHYSTATUS (delay_PIPERX2PHYSTATUS),
.PIPERX2STATUS (delay_PIPERX2STATUS),
.PIPERX2VALID (delay_PIPERX2VALID),
.PIPERX3CHANISALIGNED (delay_PIPERX3CHANISALIGNED),
.PIPERX3CHARISK (delay_PIPERX3CHARISK),
.PIPERX3DATA (delay_PIPERX3DATA),
.PIPERX3ELECIDLE (delay_PIPERX3ELECIDLE),
.PIPERX3PHYSTATUS (delay_PIPERX3PHYSTATUS),
.PIPERX3STATUS (delay_PIPERX3STATUS),
.PIPERX3VALID (delay_PIPERX3VALID),
.PIPERX4CHANISALIGNED (delay_PIPERX4CHANISALIGNED),
.PIPERX4CHARISK (delay_PIPERX4CHARISK),
.PIPERX4DATA (delay_PIPERX4DATA),
.PIPERX4ELECIDLE (delay_PIPERX4ELECIDLE),
.PIPERX4PHYSTATUS (delay_PIPERX4PHYSTATUS),
.PIPERX4STATUS (delay_PIPERX4STATUS),
.PIPERX4VALID (delay_PIPERX4VALID),
.PIPERX5CHANISALIGNED (delay_PIPERX5CHANISALIGNED),
.PIPERX5CHARISK (delay_PIPERX5CHARISK),
.PIPERX5DATA (delay_PIPERX5DATA),
.PIPERX5ELECIDLE (delay_PIPERX5ELECIDLE),
.PIPERX5PHYSTATUS (delay_PIPERX5PHYSTATUS),
.PIPERX5STATUS (delay_PIPERX5STATUS),
.PIPERX5VALID (delay_PIPERX5VALID),
.PIPERX6CHANISALIGNED (delay_PIPERX6CHANISALIGNED),
.PIPERX6CHARISK (delay_PIPERX6CHARISK),
.PIPERX6DATA (delay_PIPERX6DATA),
.PIPERX6ELECIDLE (delay_PIPERX6ELECIDLE),
.PIPERX6PHYSTATUS (delay_PIPERX6PHYSTATUS),
.PIPERX6STATUS (delay_PIPERX6STATUS),
.PIPERX6VALID (delay_PIPERX6VALID),
.PIPERX7CHANISALIGNED (delay_PIPERX7CHANISALIGNED),
.PIPERX7CHARISK (delay_PIPERX7CHARISK),
.PIPERX7DATA (delay_PIPERX7DATA),
.PIPERX7ELECIDLE (delay_PIPERX7ELECIDLE),
.PIPERX7PHYSTATUS (delay_PIPERX7PHYSTATUS),
.PIPERX7STATUS (delay_PIPERX7STATUS),
.PIPERX7VALID (delay_PIPERX7VALID),
.PL2DIRECTEDLSTATE (delay_PL2DIRECTEDLSTATE),
.PLDBGMODE (delay_PLDBGMODE),
.PLDIRECTEDLINKAUTON (delay_PLDIRECTEDLINKAUTON),
.PLDIRECTEDLINKCHANGE (delay_PLDIRECTEDLINKCHANGE),
.PLDIRECTEDLINKSPEED (delay_PLDIRECTEDLINKSPEED),
.PLDIRECTEDLINKWIDTH (delay_PLDIRECTEDLINKWIDTH),
.PLDIRECTEDLTSSMNEW (delay_PLDIRECTEDLTSSMNEW),
.PLDIRECTEDLTSSMNEWVLD (delay_PLDIRECTEDLTSSMNEWVLD),
.PLDIRECTEDLTSSMSTALL (delay_PLDIRECTEDLTSSMSTALL),
.PLDOWNSTREAMDEEMPHSOURCE (delay_PLDOWNSTREAMDEEMPHSOURCE),
.PLRSTN (delay_PLRSTN),
.PLTRANSMITHOTRST (delay_PLTRANSMITHOTRST),
.PLUPSTREAMPREFERDEEMPH (delay_PLUPSTREAMPREFERDEEMPH),
.SYSRSTN (delay_SYSRSTN),
.TL2ASPMSUSPENDCREDITCHECK (delay_TL2ASPMSUSPENDCREDITCHECK),
.TL2PPMSUSPENDREQ (delay_TL2PPMSUSPENDREQ),
.TLRSTN (delay_TLRSTN),
.TRNFCSEL (delay_TRNFCSEL),
.TRNRDSTRDY (delay_TRNRDSTRDY),
.TRNRFCPRET (delay_TRNRFCPRET),
.TRNRNPOK (delay_TRNRNPOK),
.TRNRNPREQ (delay_TRNRNPREQ),
.TRNTCFGGNT (delay_TRNTCFGGNT),
.TRNTD (delay_TRNTD),
.TRNTDLLPDATA (delay_TRNTDLLPDATA),
.TRNTDLLPSRCRDY (delay_TRNTDLLPSRCRDY),
.TRNTECRCGEN (delay_TRNTECRCGEN),
.TRNTEOF (delay_TRNTEOF),
.TRNTERRFWD (delay_TRNTERRFWD),
.TRNTREM (delay_TRNTREM),
.TRNTSOF (delay_TRNTSOF),
.TRNTSRCDSC (delay_TRNTSRCDSC),
.TRNTSRCRDY (delay_TRNTSRCRDY),
.TRNTSTR (delay_TRNTSTR),
.USERCLK (delay_USERCLK),
.USERCLK2 (delay_USERCLK2)
// .GSR (GSR)
);
specify
`ifdef XIL_TIMING // Simprim
$period (posedge DRPCLK, 0:0:0, notifier);
$period (posedge PIPECLK, 0:0:0, notifier);
$period (posedge USERCLK, 0:0:0, notifier);
$period (posedge USERCLK2, 0:0:0, notifier);
$setuphold (posedge DRPCLK, negedge DRPADDR[0], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[0]);
$setuphold (posedge DRPCLK, negedge DRPADDR[1], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[1]);
$setuphold (posedge DRPCLK, negedge DRPADDR[2], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[2]);
$setuphold (posedge DRPCLK, negedge DRPADDR[3], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[3]);
$setuphold (posedge DRPCLK, negedge DRPADDR[4], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[4]);
$setuphold (posedge DRPCLK, negedge DRPADDR[5], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[5]);
$setuphold (posedge DRPCLK, negedge DRPADDR[6], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[6]);
$setuphold (posedge DRPCLK, negedge DRPADDR[7], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[7]);
$setuphold (posedge DRPCLK, negedge DRPADDR[8], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[8]);
$setuphold (posedge DRPCLK, negedge DRPDI[0], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[0]);
$setuphold (posedge DRPCLK, negedge DRPDI[10], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[10]);
$setuphold (posedge DRPCLK, negedge DRPDI[11], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[11]);
$setuphold (posedge DRPCLK, negedge DRPDI[12], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[12]);
$setuphold (posedge DRPCLK, negedge DRPDI[13], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[13]);
$setuphold (posedge DRPCLK, negedge DRPDI[14], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[14]);
$setuphold (posedge DRPCLK, negedge DRPDI[15], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[15]);
$setuphold (posedge DRPCLK, negedge DRPDI[1], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[1]);
$setuphold (posedge DRPCLK, negedge DRPDI[2], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[2]);
$setuphold (posedge DRPCLK, negedge DRPDI[3], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[3]);
$setuphold (posedge DRPCLK, negedge DRPDI[4], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[4]);
$setuphold (posedge DRPCLK, negedge DRPDI[5], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[5]);
$setuphold (posedge DRPCLK, negedge DRPDI[6], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[6]);
$setuphold (posedge DRPCLK, negedge DRPDI[7], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[7]);
$setuphold (posedge DRPCLK, negedge DRPDI[8], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[8]);
$setuphold (posedge DRPCLK, negedge DRPDI[9], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[9]);
$setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPEN);
$setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPWE);
$setuphold (posedge DRPCLK, posedge DRPADDR[0], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[0]);
$setuphold (posedge DRPCLK, posedge DRPADDR[1], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[1]);
$setuphold (posedge DRPCLK, posedge DRPADDR[2], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[2]);
$setuphold (posedge DRPCLK, posedge DRPADDR[3], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[3]);
$setuphold (posedge DRPCLK, posedge DRPADDR[4], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[4]);
$setuphold (posedge DRPCLK, posedge DRPADDR[5], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[5]);
$setuphold (posedge DRPCLK, posedge DRPADDR[6], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[6]);
$setuphold (posedge DRPCLK, posedge DRPADDR[7], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[7]);
$setuphold (posedge DRPCLK, posedge DRPADDR[8], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[8]);
$setuphold (posedge DRPCLK, posedge DRPDI[0], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[0]);
$setuphold (posedge DRPCLK, posedge DRPDI[10], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[10]);
$setuphold (posedge DRPCLK, posedge DRPDI[11], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[11]);
$setuphold (posedge DRPCLK, posedge DRPDI[12], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[12]);
$setuphold (posedge DRPCLK, posedge DRPDI[13], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[13]);
$setuphold (posedge DRPCLK, posedge DRPDI[14], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[14]);
$setuphold (posedge DRPCLK, posedge DRPDI[15], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[15]);
$setuphold (posedge DRPCLK, posedge DRPDI[1], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[1]);
$setuphold (posedge DRPCLK, posedge DRPDI[2], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[2]);
$setuphold (posedge DRPCLK, posedge DRPDI[3], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[3]);
$setuphold (posedge DRPCLK, posedge DRPDI[4], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[4]);
$setuphold (posedge DRPCLK, posedge DRPDI[5], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[5]);
$setuphold (posedge DRPCLK, posedge DRPDI[6], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[6]);
$setuphold (posedge DRPCLK, posedge DRPDI[7], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[7]);
$setuphold (posedge DRPCLK, posedge DRPDI[8], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[8]);
$setuphold (posedge DRPCLK, posedge DRPDI[9], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[9]);
$setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPEN);
$setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPWE);
$setuphold (posedge PIPECLK, negedge PIPERX0CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0CHANISALIGNED);
$setuphold (posedge PIPECLK, negedge PIPERX0CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0CHARISK[0]);
$setuphold (posedge PIPECLK, negedge PIPERX0CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0CHARISK[1]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[0]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[10]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[11]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[12]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[13]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[14]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[15]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[1]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[2]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[3]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[4]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[5]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[6]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[7]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[8]);
$setuphold (posedge PIPECLK, negedge PIPERX0DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[9]);
$setuphold (posedge PIPECLK, negedge PIPERX0ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0ELECIDLE);
$setuphold (posedge PIPECLK, negedge PIPERX0PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0PHYSTATUS);
$setuphold (posedge PIPECLK, negedge PIPERX0STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0STATUS[0]);
$setuphold (posedge PIPECLK, negedge PIPERX0STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0STATUS[1]);
$setuphold (posedge PIPECLK, negedge PIPERX0STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0STATUS[2]);
$setuphold (posedge PIPECLK, negedge PIPERX0VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0VALID);
$setuphold (posedge PIPECLK, negedge PIPERX1CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1CHANISALIGNED);
$setuphold (posedge PIPECLK, negedge PIPERX1CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1CHARISK[0]);
$setuphold (posedge PIPECLK, negedge PIPERX1CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1CHARISK[1]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[0]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[10]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[11]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[12]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[13]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[14]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[15]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[1]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[2]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[3]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[4]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[5]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[6]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[7]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[8]);
$setuphold (posedge PIPECLK, negedge PIPERX1DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[9]);
$setuphold (posedge PIPECLK, negedge PIPERX1ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1ELECIDLE);
$setuphold (posedge PIPECLK, negedge PIPERX1PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1PHYSTATUS);
$setuphold (posedge PIPECLK, negedge PIPERX1STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1STATUS[0]);
$setuphold (posedge PIPECLK, negedge PIPERX1STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1STATUS[1]);
$setuphold (posedge PIPECLK, negedge PIPERX1STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1STATUS[2]);
$setuphold (posedge PIPECLK, negedge PIPERX1VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1VALID);
$setuphold (posedge PIPECLK, negedge PIPERX2CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2CHANISALIGNED);
$setuphold (posedge PIPECLK, negedge PIPERX2CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2CHARISK[0]);
$setuphold (posedge PIPECLK, negedge PIPERX2CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2CHARISK[1]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[0]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[10]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[11]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[12]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[13]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[14]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[15]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[1]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[2]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[3]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[4]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[5]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[6]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[7]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[8]);
$setuphold (posedge PIPECLK, negedge PIPERX2DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[9]);
$setuphold (posedge PIPECLK, negedge PIPERX2ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2ELECIDLE);
$setuphold (posedge PIPECLK, negedge PIPERX2PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2PHYSTATUS);
$setuphold (posedge PIPECLK, negedge PIPERX2STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2STATUS[0]);
$setuphold (posedge PIPECLK, negedge PIPERX2STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2STATUS[1]);
$setuphold (posedge PIPECLK, negedge PIPERX2STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2STATUS[2]);
$setuphold (posedge PIPECLK, negedge PIPERX2VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2VALID);
$setuphold (posedge PIPECLK, negedge PIPERX3CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3CHANISALIGNED);
$setuphold (posedge PIPECLK, negedge PIPERX3CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3CHARISK[0]);
$setuphold (posedge PIPECLK, negedge PIPERX3CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3CHARISK[1]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[0]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[10]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[11]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[12]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[13]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[14]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[15]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[1]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[2]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[3]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[4]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[5]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[6]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[7]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[8]);
$setuphold (posedge PIPECLK, negedge PIPERX3DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[9]);
$setuphold (posedge PIPECLK, negedge PIPERX3ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3ELECIDLE);
$setuphold (posedge PIPECLK, negedge PIPERX3PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3PHYSTATUS);
$setuphold (posedge PIPECLK, negedge PIPERX3STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3STATUS[0]);
$setuphold (posedge PIPECLK, negedge PIPERX3STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3STATUS[1]);
$setuphold (posedge PIPECLK, negedge PIPERX3STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3STATUS[2]);
$setuphold (posedge PIPECLK, negedge PIPERX3VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3VALID);
$setuphold (posedge PIPECLK, negedge PIPERX4CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4CHANISALIGNED);
$setuphold (posedge PIPECLK, negedge PIPERX4CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4CHARISK[0]);
$setuphold (posedge PIPECLK, negedge PIPERX4CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4CHARISK[1]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[0]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[10]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[11]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[12]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[13]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[14]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[15]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[1]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[2]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[3]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[4]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[5]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[6]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[7]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[8]);
$setuphold (posedge PIPECLK, negedge PIPERX4DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[9]);
$setuphold (posedge PIPECLK, negedge PIPERX4ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4ELECIDLE);
$setuphold (posedge PIPECLK, negedge PIPERX4PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4PHYSTATUS);
$setuphold (posedge PIPECLK, negedge PIPERX4STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4STATUS[0]);
$setuphold (posedge PIPECLK, negedge PIPERX4STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4STATUS[1]);
$setuphold (posedge PIPECLK, negedge PIPERX4STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4STATUS[2]);
$setuphold (posedge PIPECLK, negedge PIPERX4VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4VALID);
$setuphold (posedge PIPECLK, negedge PIPERX5CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5CHANISALIGNED);
$setuphold (posedge PIPECLK, negedge PIPERX5CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5CHARISK[0]);
$setuphold (posedge PIPECLK, negedge PIPERX5CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5CHARISK[1]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[0]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[10]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[11]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[12]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[13]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[14]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[15]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[1]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[2]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[3]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[4]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[5]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[6]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[7]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[8]);
$setuphold (posedge PIPECLK, negedge PIPERX5DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[9]);
$setuphold (posedge PIPECLK, negedge PIPERX5ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5ELECIDLE);
$setuphold (posedge PIPECLK, negedge PIPERX5PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5PHYSTATUS);
$setuphold (posedge PIPECLK, negedge PIPERX5STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5STATUS[0]);
$setuphold (posedge PIPECLK, negedge PIPERX5STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5STATUS[1]);
$setuphold (posedge PIPECLK, negedge PIPERX5STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5STATUS[2]);
$setuphold (posedge PIPECLK, negedge PIPERX5VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5VALID);
$setuphold (posedge PIPECLK, negedge PIPERX6CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6CHANISALIGNED);
$setuphold (posedge PIPECLK, negedge PIPERX6CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6CHARISK[0]);
$setuphold (posedge PIPECLK, negedge PIPERX6CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6CHARISK[1]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[0]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[10]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[11]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[12]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[13]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[14]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[15]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[1]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[2]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[3]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[4]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[5]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[6]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[7]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[8]);
$setuphold (posedge PIPECLK, negedge PIPERX6DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[9]);
$setuphold (posedge PIPECLK, negedge PIPERX6ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6ELECIDLE);
$setuphold (posedge PIPECLK, negedge PIPERX6PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6PHYSTATUS);
$setuphold (posedge PIPECLK, negedge PIPERX6STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6STATUS[0]);
$setuphold (posedge PIPECLK, negedge PIPERX6STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6STATUS[1]);
$setuphold (posedge PIPECLK, negedge PIPERX6STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6STATUS[2]);
$setuphold (posedge PIPECLK, negedge PIPERX6VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6VALID);
$setuphold (posedge PIPECLK, negedge PIPERX7CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7CHANISALIGNED);
$setuphold (posedge PIPECLK, negedge PIPERX7CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7CHARISK[0]);
$setuphold (posedge PIPECLK, negedge PIPERX7CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7CHARISK[1]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[0]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[10]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[11]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[12]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[13]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[14]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[15]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[1]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[2]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[3]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[4]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[5]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[6]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[7]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[8]);
$setuphold (posedge PIPECLK, negedge PIPERX7DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[9]);
$setuphold (posedge PIPECLK, negedge PIPERX7ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7ELECIDLE);
$setuphold (posedge PIPECLK, negedge PIPERX7PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7PHYSTATUS);
$setuphold (posedge PIPECLK, negedge PIPERX7STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7STATUS[0]);
$setuphold (posedge PIPECLK, negedge PIPERX7STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7STATUS[1]);
$setuphold (posedge PIPECLK, negedge PIPERX7STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7STATUS[2]);
$setuphold (posedge PIPECLK, negedge PIPERX7VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7VALID);
$setuphold (posedge PIPECLK, negedge PLDBGMODE[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDBGMODE[0]);
$setuphold (posedge PIPECLK, negedge PLDBGMODE[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDBGMODE[1]);
$setuphold (posedge PIPECLK, negedge PLDBGMODE[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDBGMODE[2]);
$setuphold (posedge PIPECLK, negedge PLDIRECTEDLINKAUTON, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLINKAUTON);
$setuphold (posedge PIPECLK, negedge PLDIRECTEDLINKCHANGE[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLINKCHANGE[0]);
$setuphold (posedge PIPECLK, negedge PLDIRECTEDLINKCHANGE[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLINKCHANGE[1]);
$setuphold (posedge PIPECLK, negedge PLDIRECTEDLINKSPEED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLINKSPEED);
$setuphold (posedge PIPECLK, negedge PLDIRECTEDLINKWIDTH[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLINKWIDTH[0]);
$setuphold (posedge PIPECLK, negedge PLDIRECTEDLINKWIDTH[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLINKWIDTH[1]);
$setuphold (posedge PIPECLK, negedge PLDIRECTEDLTSSMNEWVLD, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEWVLD);
$setuphold (posedge PIPECLK, negedge PLDIRECTEDLTSSMNEW[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEW[0]);
$setuphold (posedge PIPECLK, negedge PLDIRECTEDLTSSMNEW[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEW[1]);
$setuphold (posedge PIPECLK, negedge PLDIRECTEDLTSSMNEW[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEW[2]);
$setuphold (posedge PIPECLK, negedge PLDIRECTEDLTSSMNEW[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEW[3]);
$setuphold (posedge PIPECLK, negedge PLDIRECTEDLTSSMNEW[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEW[4]);
$setuphold (posedge PIPECLK, negedge PLDIRECTEDLTSSMNEW[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEW[5]);
$setuphold (posedge PIPECLK, negedge PLDIRECTEDLTSSMSTALL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMSTALL);
$setuphold (posedge PIPECLK, negedge PLDOWNSTREAMDEEMPHSOURCE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDOWNSTREAMDEEMPHSOURCE);
$setuphold (posedge PIPECLK, negedge PLRSTN, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLRSTN);
$setuphold (posedge PIPECLK, negedge PLTRANSMITHOTRST, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLTRANSMITHOTRST);
$setuphold (posedge PIPECLK, negedge PLUPSTREAMPREFERDEEMPH, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLUPSTREAMPREFERDEEMPH);
$setuphold (posedge PIPECLK, posedge PIPERX0CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0CHANISALIGNED);
$setuphold (posedge PIPECLK, posedge PIPERX0CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0CHARISK[0]);
$setuphold (posedge PIPECLK, posedge PIPERX0CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0CHARISK[1]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[0]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[10]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[11]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[12]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[13]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[14]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[15]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[1]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[2]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[3]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[4]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[5]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[6]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[7]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[8]);
$setuphold (posedge PIPECLK, posedge PIPERX0DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0DATA[9]);
$setuphold (posedge PIPECLK, posedge PIPERX0ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0ELECIDLE);
$setuphold (posedge PIPECLK, posedge PIPERX0PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0PHYSTATUS);
$setuphold (posedge PIPECLK, posedge PIPERX0STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0STATUS[0]);
$setuphold (posedge PIPECLK, posedge PIPERX0STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0STATUS[1]);
$setuphold (posedge PIPECLK, posedge PIPERX0STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0STATUS[2]);
$setuphold (posedge PIPECLK, posedge PIPERX0VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0VALID);
$setuphold (posedge PIPECLK, posedge PIPERX1CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1CHANISALIGNED);
$setuphold (posedge PIPECLK, posedge PIPERX1CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1CHARISK[0]);
$setuphold (posedge PIPECLK, posedge PIPERX1CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1CHARISK[1]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[0]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[10]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[11]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[12]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[13]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[14]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[15]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[1]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[2]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[3]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[4]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[5]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[6]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[7]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[8]);
$setuphold (posedge PIPECLK, posedge PIPERX1DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1DATA[9]);
$setuphold (posedge PIPECLK, posedge PIPERX1ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1ELECIDLE);
$setuphold (posedge PIPECLK, posedge PIPERX1PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1PHYSTATUS);
$setuphold (posedge PIPECLK, posedge PIPERX1STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1STATUS[0]);
$setuphold (posedge PIPECLK, posedge PIPERX1STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1STATUS[1]);
$setuphold (posedge PIPECLK, posedge PIPERX1STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1STATUS[2]);
$setuphold (posedge PIPECLK, posedge PIPERX1VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1VALID);
$setuphold (posedge PIPECLK, posedge PIPERX2CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2CHANISALIGNED);
$setuphold (posedge PIPECLK, posedge PIPERX2CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2CHARISK[0]);
$setuphold (posedge PIPECLK, posedge PIPERX2CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2CHARISK[1]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[0]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[10]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[11]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[12]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[13]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[14]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[15]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[1]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[2]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[3]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[4]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[5]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[6]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[7]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[8]);
$setuphold (posedge PIPECLK, posedge PIPERX2DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2DATA[9]);
$setuphold (posedge PIPECLK, posedge PIPERX2ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2ELECIDLE);
$setuphold (posedge PIPECLK, posedge PIPERX2PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2PHYSTATUS);
$setuphold (posedge PIPECLK, posedge PIPERX2STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2STATUS[0]);
$setuphold (posedge PIPECLK, posedge PIPERX2STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2STATUS[1]);
$setuphold (posedge PIPECLK, posedge PIPERX2STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2STATUS[2]);
$setuphold (posedge PIPECLK, posedge PIPERX2VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2VALID);
$setuphold (posedge PIPECLK, posedge PIPERX3CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3CHANISALIGNED);
$setuphold (posedge PIPECLK, posedge PIPERX3CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3CHARISK[0]);
$setuphold (posedge PIPECLK, posedge PIPERX3CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3CHARISK[1]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[0]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[10]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[11]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[12]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[13]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[14]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[15]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[1]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[2]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[3]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[4]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[5]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[6]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[7]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[8]);
$setuphold (posedge PIPECLK, posedge PIPERX3DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3DATA[9]);
$setuphold (posedge PIPECLK, posedge PIPERX3ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3ELECIDLE);
$setuphold (posedge PIPECLK, posedge PIPERX3PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3PHYSTATUS);
$setuphold (posedge PIPECLK, posedge PIPERX3STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3STATUS[0]);
$setuphold (posedge PIPECLK, posedge PIPERX3STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3STATUS[1]);
$setuphold (posedge PIPECLK, posedge PIPERX3STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3STATUS[2]);
$setuphold (posedge PIPECLK, posedge PIPERX3VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3VALID);
$setuphold (posedge PIPECLK, posedge PIPERX4CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4CHANISALIGNED);
$setuphold (posedge PIPECLK, posedge PIPERX4CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4CHARISK[0]);
$setuphold (posedge PIPECLK, posedge PIPERX4CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4CHARISK[1]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[0]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[10]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[11]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[12]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[13]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[14]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[15]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[1]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[2]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[3]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[4]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[5]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[6]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[7]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[8]);
$setuphold (posedge PIPECLK, posedge PIPERX4DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4DATA[9]);
$setuphold (posedge PIPECLK, posedge PIPERX4ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4ELECIDLE);
$setuphold (posedge PIPECLK, posedge PIPERX4PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4PHYSTATUS);
$setuphold (posedge PIPECLK, posedge PIPERX4STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4STATUS[0]);
$setuphold (posedge PIPECLK, posedge PIPERX4STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4STATUS[1]);
$setuphold (posedge PIPECLK, posedge PIPERX4STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4STATUS[2]);
$setuphold (posedge PIPECLK, posedge PIPERX4VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4VALID);
$setuphold (posedge PIPECLK, posedge PIPERX5CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5CHANISALIGNED);
$setuphold (posedge PIPECLK, posedge PIPERX5CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5CHARISK[0]);
$setuphold (posedge PIPECLK, posedge PIPERX5CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5CHARISK[1]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[0]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[10]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[11]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[12]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[13]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[14]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[15]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[1]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[2]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[3]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[4]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[5]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[6]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[7]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[8]);
$setuphold (posedge PIPECLK, posedge PIPERX5DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5DATA[9]);
$setuphold (posedge PIPECLK, posedge PIPERX5ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5ELECIDLE);
$setuphold (posedge PIPECLK, posedge PIPERX5PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5PHYSTATUS);
$setuphold (posedge PIPECLK, posedge PIPERX5STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5STATUS[0]);
$setuphold (posedge PIPECLK, posedge PIPERX5STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5STATUS[1]);
$setuphold (posedge PIPECLK, posedge PIPERX5STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5STATUS[2]);
$setuphold (posedge PIPECLK, posedge PIPERX5VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5VALID);
$setuphold (posedge PIPECLK, posedge PIPERX6CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6CHANISALIGNED);
$setuphold (posedge PIPECLK, posedge PIPERX6CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6CHARISK[0]);
$setuphold (posedge PIPECLK, posedge PIPERX6CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6CHARISK[1]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[0]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[10]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[11]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[12]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[13]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[14]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[15]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[1]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[2]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[3]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[4]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[5]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[6]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[7]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[8]);
$setuphold (posedge PIPECLK, posedge PIPERX6DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6DATA[9]);
$setuphold (posedge PIPECLK, posedge PIPERX6ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6ELECIDLE);
$setuphold (posedge PIPECLK, posedge PIPERX6PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6PHYSTATUS);
$setuphold (posedge PIPECLK, posedge PIPERX6STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6STATUS[0]);
$setuphold (posedge PIPECLK, posedge PIPERX6STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6STATUS[1]);
$setuphold (posedge PIPECLK, posedge PIPERX6STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6STATUS[2]);
$setuphold (posedge PIPECLK, posedge PIPERX6VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6VALID);
$setuphold (posedge PIPECLK, posedge PIPERX7CHANISALIGNED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7CHANISALIGNED);
$setuphold (posedge PIPECLK, posedge PIPERX7CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7CHARISK[0]);
$setuphold (posedge PIPECLK, posedge PIPERX7CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7CHARISK[1]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[0]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[10]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[11]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[12]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[13]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[14]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[15]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[1]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[2]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[3]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[4]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[5]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[6]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[7]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[8]);
$setuphold (posedge PIPECLK, posedge PIPERX7DATA[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7DATA[9]);
$setuphold (posedge PIPECLK, posedge PIPERX7ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7ELECIDLE);
$setuphold (posedge PIPECLK, posedge PIPERX7PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7PHYSTATUS);
$setuphold (posedge PIPECLK, posedge PIPERX7STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7STATUS[0]);
$setuphold (posedge PIPECLK, posedge PIPERX7STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7STATUS[1]);
$setuphold (posedge PIPECLK, posedge PIPERX7STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7STATUS[2]);
$setuphold (posedge PIPECLK, posedge PIPERX7VALID, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7VALID);
$setuphold (posedge PIPECLK, posedge PLDBGMODE[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDBGMODE[0]);
$setuphold (posedge PIPECLK, posedge PLDBGMODE[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDBGMODE[1]);
$setuphold (posedge PIPECLK, posedge PLDBGMODE[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDBGMODE[2]);
$setuphold (posedge PIPECLK, posedge PLDIRECTEDLINKAUTON, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLINKAUTON);
$setuphold (posedge PIPECLK, posedge PLDIRECTEDLINKCHANGE[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLINKCHANGE[0]);
$setuphold (posedge PIPECLK, posedge PLDIRECTEDLINKCHANGE[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLINKCHANGE[1]);
$setuphold (posedge PIPECLK, posedge PLDIRECTEDLINKSPEED, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLINKSPEED);
$setuphold (posedge PIPECLK, posedge PLDIRECTEDLINKWIDTH[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLINKWIDTH[0]);
$setuphold (posedge PIPECLK, posedge PLDIRECTEDLINKWIDTH[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLINKWIDTH[1]);
$setuphold (posedge PIPECLK, posedge PLDIRECTEDLTSSMNEWVLD, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEWVLD);
$setuphold (posedge PIPECLK, posedge PLDIRECTEDLTSSMNEW[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEW[0]);
$setuphold (posedge PIPECLK, posedge PLDIRECTEDLTSSMNEW[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEW[1]);
$setuphold (posedge PIPECLK, posedge PLDIRECTEDLTSSMNEW[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEW[2]);
$setuphold (posedge PIPECLK, posedge PLDIRECTEDLTSSMNEW[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEW[3]);
$setuphold (posedge PIPECLK, posedge PLDIRECTEDLTSSMNEW[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEW[4]);
$setuphold (posedge PIPECLK, posedge PLDIRECTEDLTSSMNEW[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMNEW[5]);
$setuphold (posedge PIPECLK, posedge PLDIRECTEDLTSSMSTALL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDIRECTEDLTSSMSTALL);
$setuphold (posedge PIPECLK, posedge PLDOWNSTREAMDEEMPHSOURCE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDOWNSTREAMDEEMPHSOURCE);
$setuphold (posedge PIPECLK, posedge PLRSTN, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLRSTN);
$setuphold (posedge PIPECLK, posedge PLTRANSMITHOTRST, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLTRANSMITHOTRST);
$setuphold (posedge PIPECLK, posedge PLUPSTREAMPREFERDEEMPH, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLUPSTREAMPREFERDEEMPH);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[0]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[10]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[11]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[12]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[13]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[14]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[15]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[16]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[17]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[18]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[19]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[1]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[20]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[21]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[22]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[23]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[24]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[25]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[26]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[27]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[28]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[29]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[2]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[30]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[31]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[32]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[33]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[34]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[35]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[36]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[37]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[38]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[39]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[3]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[40]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[41]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[42]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[43]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[44]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[45]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[46]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[47]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[48]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[49]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[4]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[50]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[51]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[52]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[53]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[54]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[55]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[56]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[57]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[58]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[59]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[5]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[60]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[61]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[62]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[63]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[64], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[64]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[65], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[65]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[66], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[66]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[67], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[67]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[6]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[7]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[8]);
$setuphold (posedge USERCLK, negedge MIMRXRDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[9]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[0]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[10]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[11]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[12]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[13]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[14]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[15]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[16]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[17]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[18]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[19]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[1]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[20]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[21]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[22]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[23]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[24]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[25]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[26]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[27]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[28]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[29]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[2]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[30]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[31]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[32]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[33]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[34]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[35]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[36]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[37]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[38]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[39]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[3]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[40]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[41]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[42]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[43]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[44]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[45]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[46]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[47]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[48]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[49]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[4]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[50]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[51]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[52]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[53]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[54]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[55]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[56]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[57]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[58]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[59]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[5]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[60]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[61]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[62]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[63]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[64], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[64]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[65], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[65]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[66], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[66]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[67], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[67]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[68], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[68]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[6]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[7]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[8]);
$setuphold (posedge USERCLK, negedge MIMTXRDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[9]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[0]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[10]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[11]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[12]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[13]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[14]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[15]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[16]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[17]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[18]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[19]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[1]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[20]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[21]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[22]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[23]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[24]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[25]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[26]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[27]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[28]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[29]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[2]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[30]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[31]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[32]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[33]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[34]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[35]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[36]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[37]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[38]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[39]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[3]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[40]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[41]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[42]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[43]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[44]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[45]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[46]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[47]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[48]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[49]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[4]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[50]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[51]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[52]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[53]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[54]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[55]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[56]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[57]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[58]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[59]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[5]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[60]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[61]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[62]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[63]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[64], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[64]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[65], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[65]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[66], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[66]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[67], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[67]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[6]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[7]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[8]);
$setuphold (posedge USERCLK, posedge MIMRXRDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMRXRDATA[9]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[0]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[10]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[11]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[12]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[13]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[14]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[15]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[16]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[17]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[18]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[19]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[1]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[20]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[21]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[22]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[23]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[24]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[25]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[26]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[27]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[28]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[29]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[2]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[30]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[31]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[32]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[33]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[34]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[35]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[36]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[37]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[38]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[39]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[3]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[40]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[41]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[42]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[43]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[44]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[45]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[46]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[47]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[48]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[49]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[4]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[50]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[51]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[52]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[53]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[54]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[55]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[56]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[57]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[58]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[59]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[5]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[60]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[61]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[62]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[63]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[64], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[64]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[65], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[65]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[66], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[66]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[67], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[67]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[68], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[68]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[6]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[7]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[8]);
$setuphold (posedge USERCLK, posedge MIMTXRDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MIMTXRDATA[9]);
$setuphold (posedge USERCLK2, negedge CFGAERINTERRUPTMSGNUM[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGAERINTERRUPTMSGNUM[0]);
$setuphold (posedge USERCLK2, negedge CFGAERINTERRUPTMSGNUM[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGAERINTERRUPTMSGNUM[1]);
$setuphold (posedge USERCLK2, negedge CFGAERINTERRUPTMSGNUM[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGAERINTERRUPTMSGNUM[2]);
$setuphold (posedge USERCLK2, negedge CFGAERINTERRUPTMSGNUM[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGAERINTERRUPTMSGNUM[3]);
$setuphold (posedge USERCLK2, negedge CFGAERINTERRUPTMSGNUM[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGAERINTERRUPTMSGNUM[4]);
$setuphold (posedge USERCLK2, negedge CFGDEVID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[0]);
$setuphold (posedge USERCLK2, negedge CFGDEVID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[10]);
$setuphold (posedge USERCLK2, negedge CFGDEVID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[11]);
$setuphold (posedge USERCLK2, negedge CFGDEVID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[12]);
$setuphold (posedge USERCLK2, negedge CFGDEVID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[13]);
$setuphold (posedge USERCLK2, negedge CFGDEVID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[14]);
$setuphold (posedge USERCLK2, negedge CFGDEVID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[15]);
$setuphold (posedge USERCLK2, negedge CFGDEVID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[1]);
$setuphold (posedge USERCLK2, negedge CFGDEVID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[2]);
$setuphold (posedge USERCLK2, negedge CFGDEVID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[3]);
$setuphold (posedge USERCLK2, negedge CFGDEVID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[4]);
$setuphold (posedge USERCLK2, negedge CFGDEVID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[5]);
$setuphold (posedge USERCLK2, negedge CFGDEVID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[6]);
$setuphold (posedge USERCLK2, negedge CFGDEVID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[7]);
$setuphold (posedge USERCLK2, negedge CFGDEVID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[8]);
$setuphold (posedge USERCLK2, negedge CFGDEVID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[9]);
$setuphold (posedge USERCLK2, negedge CFGDSBUSNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[0]);
$setuphold (posedge USERCLK2, negedge CFGDSBUSNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[1]);
$setuphold (posedge USERCLK2, negedge CFGDSBUSNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[2]);
$setuphold (posedge USERCLK2, negedge CFGDSBUSNUMBER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[3]);
$setuphold (posedge USERCLK2, negedge CFGDSBUSNUMBER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[4]);
$setuphold (posedge USERCLK2, negedge CFGDSBUSNUMBER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[5]);
$setuphold (posedge USERCLK2, negedge CFGDSBUSNUMBER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[6]);
$setuphold (posedge USERCLK2, negedge CFGDSBUSNUMBER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[7]);
$setuphold (posedge USERCLK2, negedge CFGDSDEVICENUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSDEVICENUMBER[0]);
$setuphold (posedge USERCLK2, negedge CFGDSDEVICENUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSDEVICENUMBER[1]);
$setuphold (posedge USERCLK2, negedge CFGDSDEVICENUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSDEVICENUMBER[2]);
$setuphold (posedge USERCLK2, negedge CFGDSDEVICENUMBER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSDEVICENUMBER[3]);
$setuphold (posedge USERCLK2, negedge CFGDSDEVICENUMBER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSDEVICENUMBER[4]);
$setuphold (posedge USERCLK2, negedge CFGDSFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSFUNCTIONNUMBER[0]);
$setuphold (posedge USERCLK2, negedge CFGDSFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSFUNCTIONNUMBER[1]);
$setuphold (posedge USERCLK2, negedge CFGDSFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSFUNCTIONNUMBER[2]);
$setuphold (posedge USERCLK2, negedge CFGDSN[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[0]);
$setuphold (posedge USERCLK2, negedge CFGDSN[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[10]);
$setuphold (posedge USERCLK2, negedge CFGDSN[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[11]);
$setuphold (posedge USERCLK2, negedge CFGDSN[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[12]);
$setuphold (posedge USERCLK2, negedge CFGDSN[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[13]);
$setuphold (posedge USERCLK2, negedge CFGDSN[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[14]);
$setuphold (posedge USERCLK2, negedge CFGDSN[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[15]);
$setuphold (posedge USERCLK2, negedge CFGDSN[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[16]);
$setuphold (posedge USERCLK2, negedge CFGDSN[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[17]);
$setuphold (posedge USERCLK2, negedge CFGDSN[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[18]);
$setuphold (posedge USERCLK2, negedge CFGDSN[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[19]);
$setuphold (posedge USERCLK2, negedge CFGDSN[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[1]);
$setuphold (posedge USERCLK2, negedge CFGDSN[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[20]);
$setuphold (posedge USERCLK2, negedge CFGDSN[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[21]);
$setuphold (posedge USERCLK2, negedge CFGDSN[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[22]);
$setuphold (posedge USERCLK2, negedge CFGDSN[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[23]);
$setuphold (posedge USERCLK2, negedge CFGDSN[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[24]);
$setuphold (posedge USERCLK2, negedge CFGDSN[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[25]);
$setuphold (posedge USERCLK2, negedge CFGDSN[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[26]);
$setuphold (posedge USERCLK2, negedge CFGDSN[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[27]);
$setuphold (posedge USERCLK2, negedge CFGDSN[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[28]);
$setuphold (posedge USERCLK2, negedge CFGDSN[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[29]);
$setuphold (posedge USERCLK2, negedge CFGDSN[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[2]);
$setuphold (posedge USERCLK2, negedge CFGDSN[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[30]);
$setuphold (posedge USERCLK2, negedge CFGDSN[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[31]);
$setuphold (posedge USERCLK2, negedge CFGDSN[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[32]);
$setuphold (posedge USERCLK2, negedge CFGDSN[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[33]);
$setuphold (posedge USERCLK2, negedge CFGDSN[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[34]);
$setuphold (posedge USERCLK2, negedge CFGDSN[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[35]);
$setuphold (posedge USERCLK2, negedge CFGDSN[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[36]);
$setuphold (posedge USERCLK2, negedge CFGDSN[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[37]);
$setuphold (posedge USERCLK2, negedge CFGDSN[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[38]);
$setuphold (posedge USERCLK2, negedge CFGDSN[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[39]);
$setuphold (posedge USERCLK2, negedge CFGDSN[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[3]);
$setuphold (posedge USERCLK2, negedge CFGDSN[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[40]);
$setuphold (posedge USERCLK2, negedge CFGDSN[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[41]);
$setuphold (posedge USERCLK2, negedge CFGDSN[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[42]);
$setuphold (posedge USERCLK2, negedge CFGDSN[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[43]);
$setuphold (posedge USERCLK2, negedge CFGDSN[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[44]);
$setuphold (posedge USERCLK2, negedge CFGDSN[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[45]);
$setuphold (posedge USERCLK2, negedge CFGDSN[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[46]);
$setuphold (posedge USERCLK2, negedge CFGDSN[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[47]);
$setuphold (posedge USERCLK2, negedge CFGDSN[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[48]);
$setuphold (posedge USERCLK2, negedge CFGDSN[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[49]);
$setuphold (posedge USERCLK2, negedge CFGDSN[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[4]);
$setuphold (posedge USERCLK2, negedge CFGDSN[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[50]);
$setuphold (posedge USERCLK2, negedge CFGDSN[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[51]);
$setuphold (posedge USERCLK2, negedge CFGDSN[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[52]);
$setuphold (posedge USERCLK2, negedge CFGDSN[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[53]);
$setuphold (posedge USERCLK2, negedge CFGDSN[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[54]);
$setuphold (posedge USERCLK2, negedge CFGDSN[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[55]);
$setuphold (posedge USERCLK2, negedge CFGDSN[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[56]);
$setuphold (posedge USERCLK2, negedge CFGDSN[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[57]);
$setuphold (posedge USERCLK2, negedge CFGDSN[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[58]);
$setuphold (posedge USERCLK2, negedge CFGDSN[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[59]);
$setuphold (posedge USERCLK2, negedge CFGDSN[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[5]);
$setuphold (posedge USERCLK2, negedge CFGDSN[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[60]);
$setuphold (posedge USERCLK2, negedge CFGDSN[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[61]);
$setuphold (posedge USERCLK2, negedge CFGDSN[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[62]);
$setuphold (posedge USERCLK2, negedge CFGDSN[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[63]);
$setuphold (posedge USERCLK2, negedge CFGDSN[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[6]);
$setuphold (posedge USERCLK2, negedge CFGDSN[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[7]);
$setuphold (posedge USERCLK2, negedge CFGDSN[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[8]);
$setuphold (posedge USERCLK2, negedge CFGDSN[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[9]);
$setuphold (posedge USERCLK2, negedge CFGERRACSN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRACSN);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[0]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[100], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[100]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[101], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[101]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[102], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[102]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[103], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[103]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[104], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[104]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[105], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[105]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[106], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[106]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[107], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[107]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[108], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[108]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[109], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[109]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[10]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[110], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[110]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[111], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[111]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[112], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[112]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[113], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[113]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[114], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[114]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[115], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[115]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[116], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[116]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[117], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[117]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[118], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[118]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[119], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[119]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[11]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[120], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[120]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[121], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[121]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[122], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[122]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[123], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[123]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[124], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[124]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[125], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[125]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[126], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[126]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[127], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[127]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[12]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[13]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[14]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[15]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[16]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[17]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[18]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[19]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[1]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[20]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[21]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[22]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[23]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[24]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[25]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[26]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[27]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[28]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[29]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[2]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[30]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[31]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[32]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[33]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[34]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[35]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[36]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[37]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[38]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[39]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[3]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[40]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[41]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[42]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[43]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[44]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[45]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[46]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[47]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[48]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[49]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[4]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[50]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[51]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[52]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[53]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[54]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[55]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[56]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[57]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[58]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[59]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[5]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[60]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[61]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[62]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[63]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[64], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[64]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[65], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[65]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[66], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[66]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[67], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[67]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[68], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[68]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[69], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[69]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[6]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[70], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[70]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[71], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[71]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[72], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[72]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[73], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[73]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[74], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[74]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[75], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[75]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[76], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[76]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[77], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[77]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[78], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[78]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[79], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[79]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[7]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[80], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[80]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[81], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[81]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[82], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[82]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[83], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[83]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[84], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[84]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[85], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[85]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[86], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[86]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[87], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[87]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[88], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[88]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[89], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[89]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[8]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[90], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[90]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[91], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[91]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[92], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[92]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[93], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[93]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[94], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[94]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[95], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[95]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[96], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[96]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[97], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[97]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[98], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[98]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[99], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[99]);
$setuphold (posedge USERCLK2, negedge CFGERRAERHEADERLOG[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[9]);
$setuphold (posedge USERCLK2, negedge CFGERRATOMICEGRESSBLOCKEDN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRATOMICEGRESSBLOCKEDN);
$setuphold (posedge USERCLK2, negedge CFGERRCORN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRCORN);
$setuphold (posedge USERCLK2, negedge CFGERRCPLABORTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRCPLABORTN);
$setuphold (posedge USERCLK2, negedge CFGERRCPLTIMEOUTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRCPLTIMEOUTN);
$setuphold (posedge USERCLK2, negedge CFGERRCPLUNEXPECTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRCPLUNEXPECTN);
$setuphold (posedge USERCLK2, negedge CFGERRECRCN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRECRCN);
$setuphold (posedge USERCLK2, negedge CFGERRINTERNALCORN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRINTERNALCORN);
$setuphold (posedge USERCLK2, negedge CFGERRINTERNALUNCORN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRINTERNALUNCORN);
$setuphold (posedge USERCLK2, negedge CFGERRLOCKEDN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRLOCKEDN);
$setuphold (posedge USERCLK2, negedge CFGERRMALFORMEDN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRMALFORMEDN);
$setuphold (posedge USERCLK2, negedge CFGERRMCBLOCKEDN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRMCBLOCKEDN);
$setuphold (posedge USERCLK2, negedge CFGERRNORECOVERYN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRNORECOVERYN);
$setuphold (posedge USERCLK2, negedge CFGERRPOISONEDN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRPOISONEDN);
$setuphold (posedge USERCLK2, negedge CFGERRPOSTEDN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRPOSTEDN);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[0]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[10]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[11]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[12]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[13]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[14]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[15]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[16]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[17]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[18]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[19]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[1]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[20]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[21]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[22]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[23]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[24]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[25]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[26]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[27]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[28]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[29]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[2]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[30]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[31]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[32]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[33]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[34]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[35]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[36]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[37]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[38]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[39]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[3]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[40]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[41]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[42]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[43]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[44]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[45]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[46]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[47]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[4]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[5]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[6]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[7]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[8]);
$setuphold (posedge USERCLK2, negedge CFGERRTLPCPLHEADER[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[9]);
$setuphold (posedge USERCLK2, negedge CFGERRURN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRURN);
$setuphold (posedge USERCLK2, negedge CFGFORCECOMMONCLOCKOFF, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGFORCECOMMONCLOCKOFF);
$setuphold (posedge USERCLK2, negedge CFGFORCEEXTENDEDSYNCON, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGFORCEEXTENDEDSYNCON);
$setuphold (posedge USERCLK2, negedge CFGFORCEMPS[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGFORCEMPS[0]);
$setuphold (posedge USERCLK2, negedge CFGFORCEMPS[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGFORCEMPS[1]);
$setuphold (posedge USERCLK2, negedge CFGFORCEMPS[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGFORCEMPS[2]);
$setuphold (posedge USERCLK2, negedge CFGINTERRUPTASSERTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTASSERTN);
$setuphold (posedge USERCLK2, negedge CFGINTERRUPTDI[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[0]);
$setuphold (posedge USERCLK2, negedge CFGINTERRUPTDI[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[1]);
$setuphold (posedge USERCLK2, negedge CFGINTERRUPTDI[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[2]);
$setuphold (posedge USERCLK2, negedge CFGINTERRUPTDI[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[3]);
$setuphold (posedge USERCLK2, negedge CFGINTERRUPTDI[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[4]);
$setuphold (posedge USERCLK2, negedge CFGINTERRUPTDI[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[5]);
$setuphold (posedge USERCLK2, negedge CFGINTERRUPTDI[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[6]);
$setuphold (posedge USERCLK2, negedge CFGINTERRUPTDI[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[7]);
$setuphold (posedge USERCLK2, negedge CFGINTERRUPTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTN);
$setuphold (posedge USERCLK2, negedge CFGINTERRUPTSTATN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTSTATN);
$setuphold (posedge USERCLK2, negedge CFGMGMTBYTEENN[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTBYTEENN[0]);
$setuphold (posedge USERCLK2, negedge CFGMGMTBYTEENN[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTBYTEENN[1]);
$setuphold (posedge USERCLK2, negedge CFGMGMTBYTEENN[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTBYTEENN[2]);
$setuphold (posedge USERCLK2, negedge CFGMGMTBYTEENN[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTBYTEENN[3]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[0]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[10]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[11]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[12]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[13]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[14]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[15]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[16]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[17]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[18]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[19]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[1]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[20]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[21]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[22]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[23]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[24]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[25]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[26]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[27]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[28]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[29]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[2]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[30]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[31]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[3]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[4]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[5]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[6]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[7]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[8]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDI[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[9]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDWADDR[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[0]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDWADDR[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[1]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDWADDR[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[2]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDWADDR[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[3]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDWADDR[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[4]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDWADDR[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[5]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDWADDR[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[6]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDWADDR[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[7]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDWADDR[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[8]);
$setuphold (posedge USERCLK2, negedge CFGMGMTDWADDR[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[9]);
$setuphold (posedge USERCLK2, negedge CFGMGMTRDENN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTRDENN);
$setuphold (posedge USERCLK2, negedge CFGMGMTWRENN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTWRENN);
$setuphold (posedge USERCLK2, negedge CFGMGMTWRREADONLYN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTWRREADONLYN);
$setuphold (posedge USERCLK2, negedge CFGMGMTWRRW1CASRWN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTWRRW1CASRWN);
$setuphold (posedge USERCLK2, negedge CFGPCIECAPINTERRUPTMSGNUM[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPCIECAPINTERRUPTMSGNUM[0]);
$setuphold (posedge USERCLK2, negedge CFGPCIECAPINTERRUPTMSGNUM[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPCIECAPINTERRUPTMSGNUM[1]);
$setuphold (posedge USERCLK2, negedge CFGPCIECAPINTERRUPTMSGNUM[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPCIECAPINTERRUPTMSGNUM[2]);
$setuphold (posedge USERCLK2, negedge CFGPCIECAPINTERRUPTMSGNUM[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPCIECAPINTERRUPTMSGNUM[3]);
$setuphold (posedge USERCLK2, negedge CFGPCIECAPINTERRUPTMSGNUM[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPCIECAPINTERRUPTMSGNUM[4]);
$setuphold (posedge USERCLK2, negedge CFGPMFORCESTATEENN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMFORCESTATEENN);
$setuphold (posedge USERCLK2, negedge CFGPMFORCESTATE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMFORCESTATE[0]);
$setuphold (posedge USERCLK2, negedge CFGPMFORCESTATE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMFORCESTATE[1]);
$setuphold (posedge USERCLK2, negedge CFGPMHALTASPML0SN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMHALTASPML0SN);
$setuphold (posedge USERCLK2, negedge CFGPMHALTASPML1N, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMHALTASPML1N);
$setuphold (posedge USERCLK2, negedge CFGPMSENDPMETON, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMSENDPMETON);
$setuphold (posedge USERCLK2, negedge CFGPMTURNOFFOKN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMTURNOFFOKN);
$setuphold (posedge USERCLK2, negedge CFGPMWAKEN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMWAKEN);
$setuphold (posedge USERCLK2, negedge CFGPORTNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[0]);
$setuphold (posedge USERCLK2, negedge CFGPORTNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[1]);
$setuphold (posedge USERCLK2, negedge CFGPORTNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[2]);
$setuphold (posedge USERCLK2, negedge CFGPORTNUMBER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[3]);
$setuphold (posedge USERCLK2, negedge CFGPORTNUMBER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[4]);
$setuphold (posedge USERCLK2, negedge CFGPORTNUMBER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[5]);
$setuphold (posedge USERCLK2, negedge CFGPORTNUMBER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[6]);
$setuphold (posedge USERCLK2, negedge CFGPORTNUMBER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[7]);
$setuphold (posedge USERCLK2, negedge CFGREVID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[0]);
$setuphold (posedge USERCLK2, negedge CFGREVID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[1]);
$setuphold (posedge USERCLK2, negedge CFGREVID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[2]);
$setuphold (posedge USERCLK2, negedge CFGREVID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[3]);
$setuphold (posedge USERCLK2, negedge CFGREVID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[4]);
$setuphold (posedge USERCLK2, negedge CFGREVID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[5]);
$setuphold (posedge USERCLK2, negedge CFGREVID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[6]);
$setuphold (posedge USERCLK2, negedge CFGREVID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[7]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[0]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[10]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[11]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[12]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[13]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[14]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[15]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[1]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[2]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[3]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[4]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[5]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[6]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[7]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[8]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[9]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[0]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[10]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[11]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[12]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[13]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[14]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[15]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[1]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[2]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[3]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[4]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[5]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[6]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[7]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[8]);
$setuphold (posedge USERCLK2, negedge CFGSUBSYSVENDID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[9]);
$setuphold (posedge USERCLK2, negedge CFGTRNPENDINGN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGTRNPENDINGN);
$setuphold (posedge USERCLK2, negedge CFGVENDID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[0]);
$setuphold (posedge USERCLK2, negedge CFGVENDID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[10]);
$setuphold (posedge USERCLK2, negedge CFGVENDID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[11]);
$setuphold (posedge USERCLK2, negedge CFGVENDID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[12]);
$setuphold (posedge USERCLK2, negedge CFGVENDID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[13]);
$setuphold (posedge USERCLK2, negedge CFGVENDID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[14]);
$setuphold (posedge USERCLK2, negedge CFGVENDID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[15]);
$setuphold (posedge USERCLK2, negedge CFGVENDID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[1]);
$setuphold (posedge USERCLK2, negedge CFGVENDID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[2]);
$setuphold (posedge USERCLK2, negedge CFGVENDID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[3]);
$setuphold (posedge USERCLK2, negedge CFGVENDID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[4]);
$setuphold (posedge USERCLK2, negedge CFGVENDID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[5]);
$setuphold (posedge USERCLK2, negedge CFGVENDID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[6]);
$setuphold (posedge USERCLK2, negedge CFGVENDID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[7]);
$setuphold (posedge USERCLK2, negedge CFGVENDID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[8]);
$setuphold (posedge USERCLK2, negedge CFGVENDID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[9]);
$setuphold (posedge USERCLK2, negedge CMRSTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CMRSTN);
$setuphold (posedge USERCLK2, negedge CMSTICKYRSTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CMSTICKYRSTN);
$setuphold (posedge USERCLK2, negedge DBGMODE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_DBGMODE[0]);
$setuphold (posedge USERCLK2, negedge DBGMODE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_DBGMODE[1]);
$setuphold (posedge USERCLK2, negedge DBGSUBMODE, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_DBGSUBMODE);
$setuphold (posedge USERCLK2, negedge DLRSTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_DLRSTN);
$setuphold (posedge USERCLK2, negedge FUNCLVLRSTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_FUNCLVLRSTN);
$setuphold (posedge USERCLK2, negedge LL2SENDASREQL1, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_LL2SENDASREQL1);
$setuphold (posedge USERCLK2, negedge LL2SENDENTERL1, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_LL2SENDENTERL1);
$setuphold (posedge USERCLK2, negedge LL2SENDENTERL23, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_LL2SENDENTERL23);
$setuphold (posedge USERCLK2, negedge LL2SENDPMACK, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_LL2SENDPMACK);
$setuphold (posedge USERCLK2, negedge LL2SUSPENDNOW, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_LL2SUSPENDNOW);
$setuphold (posedge USERCLK2, negedge LL2TLPRCV, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_LL2TLPRCV);
$setuphold (posedge USERCLK2, negedge PL2DIRECTEDLSTATE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_PL2DIRECTEDLSTATE[0]);
$setuphold (posedge USERCLK2, negedge PL2DIRECTEDLSTATE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_PL2DIRECTEDLSTATE[1]);
$setuphold (posedge USERCLK2, negedge PL2DIRECTEDLSTATE[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_PL2DIRECTEDLSTATE[2]);
$setuphold (posedge USERCLK2, negedge PL2DIRECTEDLSTATE[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_PL2DIRECTEDLSTATE[3]);
$setuphold (posedge USERCLK2, negedge PL2DIRECTEDLSTATE[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_PL2DIRECTEDLSTATE[4]);
$setuphold (posedge USERCLK2, negedge TL2ASPMSUSPENDCREDITCHECK, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TL2ASPMSUSPENDCREDITCHECK);
$setuphold (posedge USERCLK2, negedge TL2PPMSUSPENDREQ, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TL2PPMSUSPENDREQ);
$setuphold (posedge USERCLK2, negedge TLRSTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TLRSTN);
$setuphold (posedge USERCLK2, negedge TRNFCSEL[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNFCSEL[0]);
$setuphold (posedge USERCLK2, negedge TRNFCSEL[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNFCSEL[1]);
$setuphold (posedge USERCLK2, negedge TRNFCSEL[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNFCSEL[2]);
$setuphold (posedge USERCLK2, negedge TRNRDSTRDY, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNRDSTRDY);
$setuphold (posedge USERCLK2, negedge TRNRFCPRET, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNRFCPRET);
$setuphold (posedge USERCLK2, negedge TRNRNPOK, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNRNPOK);
$setuphold (posedge USERCLK2, negedge TRNRNPREQ, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNRNPREQ);
$setuphold (posedge USERCLK2, negedge TRNTCFGGNT, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTCFGGNT);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[0]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[10]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[11]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[12]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[13]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[14]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[15]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[16]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[17]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[18]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[19]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[1]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[20]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[21]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[22]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[23]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[24]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[25]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[26]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[27]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[28]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[29]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[2]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[30]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[31]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[3]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[4]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[5]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[6]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[7]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[8]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[9]);
$setuphold (posedge USERCLK2, negedge TRNTDLLPSRCRDY, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPSRCRDY);
$setuphold (posedge USERCLK2, negedge TRNTD[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[0]);
$setuphold (posedge USERCLK2, negedge TRNTD[100], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[100]);
$setuphold (posedge USERCLK2, negedge TRNTD[101], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[101]);
$setuphold (posedge USERCLK2, negedge TRNTD[102], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[102]);
$setuphold (posedge USERCLK2, negedge TRNTD[103], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[103]);
$setuphold (posedge USERCLK2, negedge TRNTD[104], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[104]);
$setuphold (posedge USERCLK2, negedge TRNTD[105], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[105]);
$setuphold (posedge USERCLK2, negedge TRNTD[106], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[106]);
$setuphold (posedge USERCLK2, negedge TRNTD[107], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[107]);
$setuphold (posedge USERCLK2, negedge TRNTD[108], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[108]);
$setuphold (posedge USERCLK2, negedge TRNTD[109], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[109]);
$setuphold (posedge USERCLK2, negedge TRNTD[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[10]);
$setuphold (posedge USERCLK2, negedge TRNTD[110], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[110]);
$setuphold (posedge USERCLK2, negedge TRNTD[111], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[111]);
$setuphold (posedge USERCLK2, negedge TRNTD[112], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[112]);
$setuphold (posedge USERCLK2, negedge TRNTD[113], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[113]);
$setuphold (posedge USERCLK2, negedge TRNTD[114], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[114]);
$setuphold (posedge USERCLK2, negedge TRNTD[115], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[115]);
$setuphold (posedge USERCLK2, negedge TRNTD[116], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[116]);
$setuphold (posedge USERCLK2, negedge TRNTD[117], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[117]);
$setuphold (posedge USERCLK2, negedge TRNTD[118], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[118]);
$setuphold (posedge USERCLK2, negedge TRNTD[119], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[119]);
$setuphold (posedge USERCLK2, negedge TRNTD[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[11]);
$setuphold (posedge USERCLK2, negedge TRNTD[120], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[120]);
$setuphold (posedge USERCLK2, negedge TRNTD[121], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[121]);
$setuphold (posedge USERCLK2, negedge TRNTD[122], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[122]);
$setuphold (posedge USERCLK2, negedge TRNTD[123], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[123]);
$setuphold (posedge USERCLK2, negedge TRNTD[124], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[124]);
$setuphold (posedge USERCLK2, negedge TRNTD[125], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[125]);
$setuphold (posedge USERCLK2, negedge TRNTD[126], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[126]);
$setuphold (posedge USERCLK2, negedge TRNTD[127], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[127]);
$setuphold (posedge USERCLK2, negedge TRNTD[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[12]);
$setuphold (posedge USERCLK2, negedge TRNTD[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[13]);
$setuphold (posedge USERCLK2, negedge TRNTD[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[14]);
$setuphold (posedge USERCLK2, negedge TRNTD[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[15]);
$setuphold (posedge USERCLK2, negedge TRNTD[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[16]);
$setuphold (posedge USERCLK2, negedge TRNTD[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[17]);
$setuphold (posedge USERCLK2, negedge TRNTD[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[18]);
$setuphold (posedge USERCLK2, negedge TRNTD[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[19]);
$setuphold (posedge USERCLK2, negedge TRNTD[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[1]);
$setuphold (posedge USERCLK2, negedge TRNTD[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[20]);
$setuphold (posedge USERCLK2, negedge TRNTD[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[21]);
$setuphold (posedge USERCLK2, negedge TRNTD[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[22]);
$setuphold (posedge USERCLK2, negedge TRNTD[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[23]);
$setuphold (posedge USERCLK2, negedge TRNTD[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[24]);
$setuphold (posedge USERCLK2, negedge TRNTD[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[25]);
$setuphold (posedge USERCLK2, negedge TRNTD[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[26]);
$setuphold (posedge USERCLK2, negedge TRNTD[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[27]);
$setuphold (posedge USERCLK2, negedge TRNTD[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[28]);
$setuphold (posedge USERCLK2, negedge TRNTD[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[29]);
$setuphold (posedge USERCLK2, negedge TRNTD[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[2]);
$setuphold (posedge USERCLK2, negedge TRNTD[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[30]);
$setuphold (posedge USERCLK2, negedge TRNTD[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[31]);
$setuphold (posedge USERCLK2, negedge TRNTD[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[32]);
$setuphold (posedge USERCLK2, negedge TRNTD[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[33]);
$setuphold (posedge USERCLK2, negedge TRNTD[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[34]);
$setuphold (posedge USERCLK2, negedge TRNTD[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[35]);
$setuphold (posedge USERCLK2, negedge TRNTD[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[36]);
$setuphold (posedge USERCLK2, negedge TRNTD[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[37]);
$setuphold (posedge USERCLK2, negedge TRNTD[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[38]);
$setuphold (posedge USERCLK2, negedge TRNTD[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[39]);
$setuphold (posedge USERCLK2, negedge TRNTD[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[3]);
$setuphold (posedge USERCLK2, negedge TRNTD[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[40]);
$setuphold (posedge USERCLK2, negedge TRNTD[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[41]);
$setuphold (posedge USERCLK2, negedge TRNTD[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[42]);
$setuphold (posedge USERCLK2, negedge TRNTD[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[43]);
$setuphold (posedge USERCLK2, negedge TRNTD[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[44]);
$setuphold (posedge USERCLK2, negedge TRNTD[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[45]);
$setuphold (posedge USERCLK2, negedge TRNTD[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[46]);
$setuphold (posedge USERCLK2, negedge TRNTD[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[47]);
$setuphold (posedge USERCLK2, negedge TRNTD[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[48]);
$setuphold (posedge USERCLK2, negedge TRNTD[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[49]);
$setuphold (posedge USERCLK2, negedge TRNTD[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[4]);
$setuphold (posedge USERCLK2, negedge TRNTD[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[50]);
$setuphold (posedge USERCLK2, negedge TRNTD[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[51]);
$setuphold (posedge USERCLK2, negedge TRNTD[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[52]);
$setuphold (posedge USERCLK2, negedge TRNTD[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[53]);
$setuphold (posedge USERCLK2, negedge TRNTD[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[54]);
$setuphold (posedge USERCLK2, negedge TRNTD[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[55]);
$setuphold (posedge USERCLK2, negedge TRNTD[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[56]);
$setuphold (posedge USERCLK2, negedge TRNTD[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[57]);
$setuphold (posedge USERCLK2, negedge TRNTD[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[58]);
$setuphold (posedge USERCLK2, negedge TRNTD[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[59]);
$setuphold (posedge USERCLK2, negedge TRNTD[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[5]);
$setuphold (posedge USERCLK2, negedge TRNTD[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[60]);
$setuphold (posedge USERCLK2, negedge TRNTD[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[61]);
$setuphold (posedge USERCLK2, negedge TRNTD[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[62]);
$setuphold (posedge USERCLK2, negedge TRNTD[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[63]);
$setuphold (posedge USERCLK2, negedge TRNTD[64], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[64]);
$setuphold (posedge USERCLK2, negedge TRNTD[65], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[65]);
$setuphold (posedge USERCLK2, negedge TRNTD[66], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[66]);
$setuphold (posedge USERCLK2, negedge TRNTD[67], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[67]);
$setuphold (posedge USERCLK2, negedge TRNTD[68], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[68]);
$setuphold (posedge USERCLK2, negedge TRNTD[69], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[69]);
$setuphold (posedge USERCLK2, negedge TRNTD[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[6]);
$setuphold (posedge USERCLK2, negedge TRNTD[70], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[70]);
$setuphold (posedge USERCLK2, negedge TRNTD[71], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[71]);
$setuphold (posedge USERCLK2, negedge TRNTD[72], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[72]);
$setuphold (posedge USERCLK2, negedge TRNTD[73], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[73]);
$setuphold (posedge USERCLK2, negedge TRNTD[74], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[74]);
$setuphold (posedge USERCLK2, negedge TRNTD[75], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[75]);
$setuphold (posedge USERCLK2, negedge TRNTD[76], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[76]);
$setuphold (posedge USERCLK2, negedge TRNTD[77], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[77]);
$setuphold (posedge USERCLK2, negedge TRNTD[78], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[78]);
$setuphold (posedge USERCLK2, negedge TRNTD[79], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[79]);
$setuphold (posedge USERCLK2, negedge TRNTD[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[7]);
$setuphold (posedge USERCLK2, negedge TRNTD[80], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[80]);
$setuphold (posedge USERCLK2, negedge TRNTD[81], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[81]);
$setuphold (posedge USERCLK2, negedge TRNTD[82], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[82]);
$setuphold (posedge USERCLK2, negedge TRNTD[83], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[83]);
$setuphold (posedge USERCLK2, negedge TRNTD[84], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[84]);
$setuphold (posedge USERCLK2, negedge TRNTD[85], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[85]);
$setuphold (posedge USERCLK2, negedge TRNTD[86], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[86]);
$setuphold (posedge USERCLK2, negedge TRNTD[87], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[87]);
$setuphold (posedge USERCLK2, negedge TRNTD[88], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[88]);
$setuphold (posedge USERCLK2, negedge TRNTD[89], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[89]);
$setuphold (posedge USERCLK2, negedge TRNTD[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[8]);
$setuphold (posedge USERCLK2, negedge TRNTD[90], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[90]);
$setuphold (posedge USERCLK2, negedge TRNTD[91], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[91]);
$setuphold (posedge USERCLK2, negedge TRNTD[92], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[92]);
$setuphold (posedge USERCLK2, negedge TRNTD[93], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[93]);
$setuphold (posedge USERCLK2, negedge TRNTD[94], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[94]);
$setuphold (posedge USERCLK2, negedge TRNTD[95], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[95]);
$setuphold (posedge USERCLK2, negedge TRNTD[96], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[96]);
$setuphold (posedge USERCLK2, negedge TRNTD[97], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[97]);
$setuphold (posedge USERCLK2, negedge TRNTD[98], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[98]);
$setuphold (posedge USERCLK2, negedge TRNTD[99], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[99]);
$setuphold (posedge USERCLK2, negedge TRNTD[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[9]);
$setuphold (posedge USERCLK2, negedge TRNTECRCGEN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTECRCGEN);
$setuphold (posedge USERCLK2, negedge TRNTEOF, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTEOF);
$setuphold (posedge USERCLK2, negedge TRNTERRFWD, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTERRFWD);
$setuphold (posedge USERCLK2, negedge TRNTREM[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTREM[0]);
$setuphold (posedge USERCLK2, negedge TRNTREM[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTREM[1]);
$setuphold (posedge USERCLK2, negedge TRNTSOF, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTSOF);
$setuphold (posedge USERCLK2, negedge TRNTSRCDSC, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTSRCDSC);
$setuphold (posedge USERCLK2, negedge TRNTSRCRDY, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTSRCRDY);
$setuphold (posedge USERCLK2, negedge TRNTSTR, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTSTR);
$setuphold (posedge USERCLK2, posedge CFGAERINTERRUPTMSGNUM[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGAERINTERRUPTMSGNUM[0]);
$setuphold (posedge USERCLK2, posedge CFGAERINTERRUPTMSGNUM[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGAERINTERRUPTMSGNUM[1]);
$setuphold (posedge USERCLK2, posedge CFGAERINTERRUPTMSGNUM[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGAERINTERRUPTMSGNUM[2]);
$setuphold (posedge USERCLK2, posedge CFGAERINTERRUPTMSGNUM[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGAERINTERRUPTMSGNUM[3]);
$setuphold (posedge USERCLK2, posedge CFGAERINTERRUPTMSGNUM[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGAERINTERRUPTMSGNUM[4]);
$setuphold (posedge USERCLK2, posedge CFGDEVID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[0]);
$setuphold (posedge USERCLK2, posedge CFGDEVID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[10]);
$setuphold (posedge USERCLK2, posedge CFGDEVID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[11]);
$setuphold (posedge USERCLK2, posedge CFGDEVID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[12]);
$setuphold (posedge USERCLK2, posedge CFGDEVID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[13]);
$setuphold (posedge USERCLK2, posedge CFGDEVID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[14]);
$setuphold (posedge USERCLK2, posedge CFGDEVID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[15]);
$setuphold (posedge USERCLK2, posedge CFGDEVID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[1]);
$setuphold (posedge USERCLK2, posedge CFGDEVID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[2]);
$setuphold (posedge USERCLK2, posedge CFGDEVID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[3]);
$setuphold (posedge USERCLK2, posedge CFGDEVID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[4]);
$setuphold (posedge USERCLK2, posedge CFGDEVID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[5]);
$setuphold (posedge USERCLK2, posedge CFGDEVID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[6]);
$setuphold (posedge USERCLK2, posedge CFGDEVID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[7]);
$setuphold (posedge USERCLK2, posedge CFGDEVID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[8]);
$setuphold (posedge USERCLK2, posedge CFGDEVID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDEVID[9]);
$setuphold (posedge USERCLK2, posedge CFGDSBUSNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[0]);
$setuphold (posedge USERCLK2, posedge CFGDSBUSNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[1]);
$setuphold (posedge USERCLK2, posedge CFGDSBUSNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[2]);
$setuphold (posedge USERCLK2, posedge CFGDSBUSNUMBER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[3]);
$setuphold (posedge USERCLK2, posedge CFGDSBUSNUMBER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[4]);
$setuphold (posedge USERCLK2, posedge CFGDSBUSNUMBER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[5]);
$setuphold (posedge USERCLK2, posedge CFGDSBUSNUMBER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[6]);
$setuphold (posedge USERCLK2, posedge CFGDSBUSNUMBER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSBUSNUMBER[7]);
$setuphold (posedge USERCLK2, posedge CFGDSDEVICENUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSDEVICENUMBER[0]);
$setuphold (posedge USERCLK2, posedge CFGDSDEVICENUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSDEVICENUMBER[1]);
$setuphold (posedge USERCLK2, posedge CFGDSDEVICENUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSDEVICENUMBER[2]);
$setuphold (posedge USERCLK2, posedge CFGDSDEVICENUMBER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSDEVICENUMBER[3]);
$setuphold (posedge USERCLK2, posedge CFGDSDEVICENUMBER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSDEVICENUMBER[4]);
$setuphold (posedge USERCLK2, posedge CFGDSFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSFUNCTIONNUMBER[0]);
$setuphold (posedge USERCLK2, posedge CFGDSFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSFUNCTIONNUMBER[1]);
$setuphold (posedge USERCLK2, posedge CFGDSFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSFUNCTIONNUMBER[2]);
$setuphold (posedge USERCLK2, posedge CFGDSN[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[0]);
$setuphold (posedge USERCLK2, posedge CFGDSN[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[10]);
$setuphold (posedge USERCLK2, posedge CFGDSN[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[11]);
$setuphold (posedge USERCLK2, posedge CFGDSN[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[12]);
$setuphold (posedge USERCLK2, posedge CFGDSN[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[13]);
$setuphold (posedge USERCLK2, posedge CFGDSN[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[14]);
$setuphold (posedge USERCLK2, posedge CFGDSN[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[15]);
$setuphold (posedge USERCLK2, posedge CFGDSN[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[16]);
$setuphold (posedge USERCLK2, posedge CFGDSN[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[17]);
$setuphold (posedge USERCLK2, posedge CFGDSN[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[18]);
$setuphold (posedge USERCLK2, posedge CFGDSN[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[19]);
$setuphold (posedge USERCLK2, posedge CFGDSN[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[1]);
$setuphold (posedge USERCLK2, posedge CFGDSN[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[20]);
$setuphold (posedge USERCLK2, posedge CFGDSN[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[21]);
$setuphold (posedge USERCLK2, posedge CFGDSN[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[22]);
$setuphold (posedge USERCLK2, posedge CFGDSN[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[23]);
$setuphold (posedge USERCLK2, posedge CFGDSN[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[24]);
$setuphold (posedge USERCLK2, posedge CFGDSN[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[25]);
$setuphold (posedge USERCLK2, posedge CFGDSN[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[26]);
$setuphold (posedge USERCLK2, posedge CFGDSN[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[27]);
$setuphold (posedge USERCLK2, posedge CFGDSN[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[28]);
$setuphold (posedge USERCLK2, posedge CFGDSN[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[29]);
$setuphold (posedge USERCLK2, posedge CFGDSN[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[2]);
$setuphold (posedge USERCLK2, posedge CFGDSN[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[30]);
$setuphold (posedge USERCLK2, posedge CFGDSN[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[31]);
$setuphold (posedge USERCLK2, posedge CFGDSN[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[32]);
$setuphold (posedge USERCLK2, posedge CFGDSN[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[33]);
$setuphold (posedge USERCLK2, posedge CFGDSN[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[34]);
$setuphold (posedge USERCLK2, posedge CFGDSN[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[35]);
$setuphold (posedge USERCLK2, posedge CFGDSN[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[36]);
$setuphold (posedge USERCLK2, posedge CFGDSN[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[37]);
$setuphold (posedge USERCLK2, posedge CFGDSN[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[38]);
$setuphold (posedge USERCLK2, posedge CFGDSN[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[39]);
$setuphold (posedge USERCLK2, posedge CFGDSN[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[3]);
$setuphold (posedge USERCLK2, posedge CFGDSN[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[40]);
$setuphold (posedge USERCLK2, posedge CFGDSN[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[41]);
$setuphold (posedge USERCLK2, posedge CFGDSN[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[42]);
$setuphold (posedge USERCLK2, posedge CFGDSN[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[43]);
$setuphold (posedge USERCLK2, posedge CFGDSN[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[44]);
$setuphold (posedge USERCLK2, posedge CFGDSN[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[45]);
$setuphold (posedge USERCLK2, posedge CFGDSN[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[46]);
$setuphold (posedge USERCLK2, posedge CFGDSN[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[47]);
$setuphold (posedge USERCLK2, posedge CFGDSN[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[48]);
$setuphold (posedge USERCLK2, posedge CFGDSN[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[49]);
$setuphold (posedge USERCLK2, posedge CFGDSN[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[4]);
$setuphold (posedge USERCLK2, posedge CFGDSN[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[50]);
$setuphold (posedge USERCLK2, posedge CFGDSN[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[51]);
$setuphold (posedge USERCLK2, posedge CFGDSN[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[52]);
$setuphold (posedge USERCLK2, posedge CFGDSN[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[53]);
$setuphold (posedge USERCLK2, posedge CFGDSN[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[54]);
$setuphold (posedge USERCLK2, posedge CFGDSN[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[55]);
$setuphold (posedge USERCLK2, posedge CFGDSN[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[56]);
$setuphold (posedge USERCLK2, posedge CFGDSN[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[57]);
$setuphold (posedge USERCLK2, posedge CFGDSN[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[58]);
$setuphold (posedge USERCLK2, posedge CFGDSN[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[59]);
$setuphold (posedge USERCLK2, posedge CFGDSN[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[5]);
$setuphold (posedge USERCLK2, posedge CFGDSN[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[60]);
$setuphold (posedge USERCLK2, posedge CFGDSN[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[61]);
$setuphold (posedge USERCLK2, posedge CFGDSN[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[62]);
$setuphold (posedge USERCLK2, posedge CFGDSN[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[63]);
$setuphold (posedge USERCLK2, posedge CFGDSN[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[6]);
$setuphold (posedge USERCLK2, posedge CFGDSN[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[7]);
$setuphold (posedge USERCLK2, posedge CFGDSN[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[8]);
$setuphold (posedge USERCLK2, posedge CFGDSN[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGDSN[9]);
$setuphold (posedge USERCLK2, posedge CFGERRACSN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRACSN);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[0]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[100], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[100]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[101], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[101]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[102], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[102]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[103], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[103]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[104], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[104]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[105], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[105]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[106], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[106]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[107], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[107]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[108], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[108]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[109], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[109]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[10]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[110], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[110]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[111], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[111]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[112], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[112]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[113], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[113]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[114], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[114]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[115], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[115]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[116], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[116]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[117], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[117]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[118], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[118]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[119], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[119]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[11]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[120], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[120]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[121], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[121]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[122], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[122]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[123], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[123]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[124], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[124]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[125], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[125]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[126], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[126]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[127], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[127]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[12]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[13]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[14]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[15]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[16]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[17]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[18]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[19]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[1]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[20]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[21]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[22]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[23]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[24]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[25]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[26]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[27]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[28]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[29]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[2]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[30]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[31]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[32]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[33]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[34]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[35]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[36]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[37]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[38]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[39]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[3]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[40]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[41]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[42]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[43]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[44]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[45]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[46]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[47]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[48]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[49]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[4]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[50]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[51]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[52]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[53]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[54]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[55]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[56]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[57]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[58]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[59]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[5]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[60]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[61]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[62]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[63]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[64], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[64]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[65], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[65]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[66], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[66]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[67], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[67]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[68], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[68]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[69], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[69]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[6]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[70], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[70]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[71], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[71]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[72], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[72]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[73], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[73]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[74], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[74]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[75], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[75]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[76], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[76]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[77], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[77]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[78], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[78]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[79], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[79]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[7]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[80], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[80]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[81], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[81]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[82], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[82]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[83], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[83]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[84], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[84]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[85], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[85]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[86], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[86]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[87], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[87]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[88], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[88]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[89], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[89]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[8]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[90], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[90]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[91], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[91]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[92], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[92]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[93], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[93]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[94], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[94]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[95], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[95]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[96], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[96]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[97], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[97]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[98], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[98]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[99], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[99]);
$setuphold (posedge USERCLK2, posedge CFGERRAERHEADERLOG[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRAERHEADERLOG[9]);
$setuphold (posedge USERCLK2, posedge CFGERRATOMICEGRESSBLOCKEDN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRATOMICEGRESSBLOCKEDN);
$setuphold (posedge USERCLK2, posedge CFGERRCORN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRCORN);
$setuphold (posedge USERCLK2, posedge CFGERRCPLABORTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRCPLABORTN);
$setuphold (posedge USERCLK2, posedge CFGERRCPLTIMEOUTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRCPLTIMEOUTN);
$setuphold (posedge USERCLK2, posedge CFGERRCPLUNEXPECTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRCPLUNEXPECTN);
$setuphold (posedge USERCLK2, posedge CFGERRECRCN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRECRCN);
$setuphold (posedge USERCLK2, posedge CFGERRINTERNALCORN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRINTERNALCORN);
$setuphold (posedge USERCLK2, posedge CFGERRINTERNALUNCORN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRINTERNALUNCORN);
$setuphold (posedge USERCLK2, posedge CFGERRLOCKEDN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRLOCKEDN);
$setuphold (posedge USERCLK2, posedge CFGERRMALFORMEDN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRMALFORMEDN);
$setuphold (posedge USERCLK2, posedge CFGERRMCBLOCKEDN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRMCBLOCKEDN);
$setuphold (posedge USERCLK2, posedge CFGERRNORECOVERYN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRNORECOVERYN);
$setuphold (posedge USERCLK2, posedge CFGERRPOISONEDN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRPOISONEDN);
$setuphold (posedge USERCLK2, posedge CFGERRPOSTEDN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRPOSTEDN);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[0]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[10]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[11]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[12]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[13]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[14]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[15]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[16]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[17]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[18]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[19]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[1]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[20]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[21]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[22]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[23]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[24]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[25]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[26]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[27]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[28]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[29]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[2]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[30]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[31]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[32]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[33]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[34]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[35]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[36]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[37]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[38]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[39]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[3]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[40]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[41]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[42]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[43]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[44]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[45]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[46]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[47]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[4]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[5]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[6]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[7]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[8]);
$setuphold (posedge USERCLK2, posedge CFGERRTLPCPLHEADER[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRTLPCPLHEADER[9]);
$setuphold (posedge USERCLK2, posedge CFGERRURN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGERRURN);
$setuphold (posedge USERCLK2, posedge CFGFORCECOMMONCLOCKOFF, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGFORCECOMMONCLOCKOFF);
$setuphold (posedge USERCLK2, posedge CFGFORCEEXTENDEDSYNCON, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGFORCEEXTENDEDSYNCON);
$setuphold (posedge USERCLK2, posedge CFGFORCEMPS[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGFORCEMPS[0]);
$setuphold (posedge USERCLK2, posedge CFGFORCEMPS[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGFORCEMPS[1]);
$setuphold (posedge USERCLK2, posedge CFGFORCEMPS[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGFORCEMPS[2]);
$setuphold (posedge USERCLK2, posedge CFGINTERRUPTASSERTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTASSERTN);
$setuphold (posedge USERCLK2, posedge CFGINTERRUPTDI[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[0]);
$setuphold (posedge USERCLK2, posedge CFGINTERRUPTDI[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[1]);
$setuphold (posedge USERCLK2, posedge CFGINTERRUPTDI[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[2]);
$setuphold (posedge USERCLK2, posedge CFGINTERRUPTDI[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[3]);
$setuphold (posedge USERCLK2, posedge CFGINTERRUPTDI[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[4]);
$setuphold (posedge USERCLK2, posedge CFGINTERRUPTDI[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[5]);
$setuphold (posedge USERCLK2, posedge CFGINTERRUPTDI[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[6]);
$setuphold (posedge USERCLK2, posedge CFGINTERRUPTDI[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTDI[7]);
$setuphold (posedge USERCLK2, posedge CFGINTERRUPTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTN);
$setuphold (posedge USERCLK2, posedge CFGINTERRUPTSTATN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGINTERRUPTSTATN);
$setuphold (posedge USERCLK2, posedge CFGMGMTBYTEENN[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTBYTEENN[0]);
$setuphold (posedge USERCLK2, posedge CFGMGMTBYTEENN[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTBYTEENN[1]);
$setuphold (posedge USERCLK2, posedge CFGMGMTBYTEENN[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTBYTEENN[2]);
$setuphold (posedge USERCLK2, posedge CFGMGMTBYTEENN[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTBYTEENN[3]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[0]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[10]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[11]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[12]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[13]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[14]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[15]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[16]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[17]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[18]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[19]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[1]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[20]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[21]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[22]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[23]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[24]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[25]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[26]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[27]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[28]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[29]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[2]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[30]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[31]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[3]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[4]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[5]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[6]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[7]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[8]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDI[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDI[9]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDWADDR[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[0]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDWADDR[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[1]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDWADDR[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[2]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDWADDR[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[3]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDWADDR[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[4]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDWADDR[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[5]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDWADDR[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[6]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDWADDR[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[7]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDWADDR[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[8]);
$setuphold (posedge USERCLK2, posedge CFGMGMTDWADDR[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTDWADDR[9]);
$setuphold (posedge USERCLK2, posedge CFGMGMTRDENN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTRDENN);
$setuphold (posedge USERCLK2, posedge CFGMGMTWRENN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTWRENN);
$setuphold (posedge USERCLK2, posedge CFGMGMTWRREADONLYN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTWRREADONLYN);
$setuphold (posedge USERCLK2, posedge CFGMGMTWRRW1CASRWN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGMGMTWRRW1CASRWN);
$setuphold (posedge USERCLK2, posedge CFGPCIECAPINTERRUPTMSGNUM[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPCIECAPINTERRUPTMSGNUM[0]);
$setuphold (posedge USERCLK2, posedge CFGPCIECAPINTERRUPTMSGNUM[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPCIECAPINTERRUPTMSGNUM[1]);
$setuphold (posedge USERCLK2, posedge CFGPCIECAPINTERRUPTMSGNUM[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPCIECAPINTERRUPTMSGNUM[2]);
$setuphold (posedge USERCLK2, posedge CFGPCIECAPINTERRUPTMSGNUM[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPCIECAPINTERRUPTMSGNUM[3]);
$setuphold (posedge USERCLK2, posedge CFGPCIECAPINTERRUPTMSGNUM[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPCIECAPINTERRUPTMSGNUM[4]);
$setuphold (posedge USERCLK2, posedge CFGPMFORCESTATEENN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMFORCESTATEENN);
$setuphold (posedge USERCLK2, posedge CFGPMFORCESTATE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMFORCESTATE[0]);
$setuphold (posedge USERCLK2, posedge CFGPMFORCESTATE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMFORCESTATE[1]);
$setuphold (posedge USERCLK2, posedge CFGPMHALTASPML0SN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMHALTASPML0SN);
$setuphold (posedge USERCLK2, posedge CFGPMHALTASPML1N, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMHALTASPML1N);
$setuphold (posedge USERCLK2, posedge CFGPMSENDPMETON, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMSENDPMETON);
$setuphold (posedge USERCLK2, posedge CFGPMTURNOFFOKN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMTURNOFFOKN);
$setuphold (posedge USERCLK2, posedge CFGPMWAKEN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPMWAKEN);
$setuphold (posedge USERCLK2, posedge CFGPORTNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[0]);
$setuphold (posedge USERCLK2, posedge CFGPORTNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[1]);
$setuphold (posedge USERCLK2, posedge CFGPORTNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[2]);
$setuphold (posedge USERCLK2, posedge CFGPORTNUMBER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[3]);
$setuphold (posedge USERCLK2, posedge CFGPORTNUMBER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[4]);
$setuphold (posedge USERCLK2, posedge CFGPORTNUMBER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[5]);
$setuphold (posedge USERCLK2, posedge CFGPORTNUMBER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[6]);
$setuphold (posedge USERCLK2, posedge CFGPORTNUMBER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGPORTNUMBER[7]);
$setuphold (posedge USERCLK2, posedge CFGREVID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[0]);
$setuphold (posedge USERCLK2, posedge CFGREVID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[1]);
$setuphold (posedge USERCLK2, posedge CFGREVID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[2]);
$setuphold (posedge USERCLK2, posedge CFGREVID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[3]);
$setuphold (posedge USERCLK2, posedge CFGREVID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[4]);
$setuphold (posedge USERCLK2, posedge CFGREVID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[5]);
$setuphold (posedge USERCLK2, posedge CFGREVID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[6]);
$setuphold (posedge USERCLK2, posedge CFGREVID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGREVID[7]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[0]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[10]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[11]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[12]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[13]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[14]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[15]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[1]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[2]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[3]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[4]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[5]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[6]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[7]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[8]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSID[9]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[0]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[10]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[11]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[12]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[13]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[14]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[15]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[1]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[2]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[3]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[4]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[5]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[6]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[7]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[8]);
$setuphold (posedge USERCLK2, posedge CFGSUBSYSVENDID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGSUBSYSVENDID[9]);
$setuphold (posedge USERCLK2, posedge CFGTRNPENDINGN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGTRNPENDINGN);
$setuphold (posedge USERCLK2, posedge CFGVENDID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[0]);
$setuphold (posedge USERCLK2, posedge CFGVENDID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[10]);
$setuphold (posedge USERCLK2, posedge CFGVENDID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[11]);
$setuphold (posedge USERCLK2, posedge CFGVENDID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[12]);
$setuphold (posedge USERCLK2, posedge CFGVENDID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[13]);
$setuphold (posedge USERCLK2, posedge CFGVENDID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[14]);
$setuphold (posedge USERCLK2, posedge CFGVENDID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[15]);
$setuphold (posedge USERCLK2, posedge CFGVENDID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[1]);
$setuphold (posedge USERCLK2, posedge CFGVENDID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[2]);
$setuphold (posedge USERCLK2, posedge CFGVENDID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[3]);
$setuphold (posedge USERCLK2, posedge CFGVENDID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[4]);
$setuphold (posedge USERCLK2, posedge CFGVENDID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[5]);
$setuphold (posedge USERCLK2, posedge CFGVENDID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[6]);
$setuphold (posedge USERCLK2, posedge CFGVENDID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[7]);
$setuphold (posedge USERCLK2, posedge CFGVENDID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[8]);
$setuphold (posedge USERCLK2, posedge CFGVENDID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CFGVENDID[9]);
$setuphold (posedge USERCLK2, posedge CMRSTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CMRSTN);
$setuphold (posedge USERCLK2, posedge CMSTICKYRSTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_CMSTICKYRSTN);
$setuphold (posedge USERCLK2, posedge DBGMODE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_DBGMODE[0]);
$setuphold (posedge USERCLK2, posedge DBGMODE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_DBGMODE[1]);
$setuphold (posedge USERCLK2, posedge DBGSUBMODE, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_DBGSUBMODE);
$setuphold (posedge USERCLK2, posedge DLRSTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_DLRSTN);
$setuphold (posedge USERCLK2, posedge FUNCLVLRSTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_FUNCLVLRSTN);
$setuphold (posedge USERCLK2, posedge LL2SENDASREQL1, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_LL2SENDASREQL1);
$setuphold (posedge USERCLK2, posedge LL2SENDENTERL1, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_LL2SENDENTERL1);
$setuphold (posedge USERCLK2, posedge LL2SENDENTERL23, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_LL2SENDENTERL23);
$setuphold (posedge USERCLK2, posedge LL2SENDPMACK, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_LL2SENDPMACK);
$setuphold (posedge USERCLK2, posedge LL2SUSPENDNOW, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_LL2SUSPENDNOW);
$setuphold (posedge USERCLK2, posedge LL2TLPRCV, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_LL2TLPRCV);
$setuphold (posedge USERCLK2, posedge PL2DIRECTEDLSTATE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_PL2DIRECTEDLSTATE[0]);
$setuphold (posedge USERCLK2, posedge PL2DIRECTEDLSTATE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_PL2DIRECTEDLSTATE[1]);
$setuphold (posedge USERCLK2, posedge PL2DIRECTEDLSTATE[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_PL2DIRECTEDLSTATE[2]);
$setuphold (posedge USERCLK2, posedge PL2DIRECTEDLSTATE[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_PL2DIRECTEDLSTATE[3]);
$setuphold (posedge USERCLK2, posedge PL2DIRECTEDLSTATE[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_PL2DIRECTEDLSTATE[4]);
$setuphold (posedge USERCLK2, posedge TL2ASPMSUSPENDCREDITCHECK, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TL2ASPMSUSPENDCREDITCHECK);
$setuphold (posedge USERCLK2, posedge TL2PPMSUSPENDREQ, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TL2PPMSUSPENDREQ);
$setuphold (posedge USERCLK2, posedge TLRSTN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TLRSTN);
$setuphold (posedge USERCLK2, posedge TRNFCSEL[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNFCSEL[0]);
$setuphold (posedge USERCLK2, posedge TRNFCSEL[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNFCSEL[1]);
$setuphold (posedge USERCLK2, posedge TRNFCSEL[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNFCSEL[2]);
$setuphold (posedge USERCLK2, posedge TRNRDSTRDY, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNRDSTRDY);
$setuphold (posedge USERCLK2, posedge TRNRFCPRET, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNRFCPRET);
$setuphold (posedge USERCLK2, posedge TRNRNPOK, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNRNPOK);
$setuphold (posedge USERCLK2, posedge TRNRNPREQ, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNRNPREQ);
$setuphold (posedge USERCLK2, posedge TRNTCFGGNT, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTCFGGNT);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[0]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[10]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[11]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[12]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[13]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[14]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[15]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[16]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[17]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[18]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[19]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[1]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[20]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[21]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[22]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[23]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[24]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[25]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[26]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[27]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[28]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[29]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[2]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[30]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[31]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[3]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[4]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[5]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[6]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[7]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[8]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPDATA[9]);
$setuphold (posedge USERCLK2, posedge TRNTDLLPSRCRDY, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTDLLPSRCRDY);
$setuphold (posedge USERCLK2, posedge TRNTD[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[0]);
$setuphold (posedge USERCLK2, posedge TRNTD[100], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[100]);
$setuphold (posedge USERCLK2, posedge TRNTD[101], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[101]);
$setuphold (posedge USERCLK2, posedge TRNTD[102], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[102]);
$setuphold (posedge USERCLK2, posedge TRNTD[103], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[103]);
$setuphold (posedge USERCLK2, posedge TRNTD[104], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[104]);
$setuphold (posedge USERCLK2, posedge TRNTD[105], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[105]);
$setuphold (posedge USERCLK2, posedge TRNTD[106], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[106]);
$setuphold (posedge USERCLK2, posedge TRNTD[107], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[107]);
$setuphold (posedge USERCLK2, posedge TRNTD[108], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[108]);
$setuphold (posedge USERCLK2, posedge TRNTD[109], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[109]);
$setuphold (posedge USERCLK2, posedge TRNTD[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[10]);
$setuphold (posedge USERCLK2, posedge TRNTD[110], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[110]);
$setuphold (posedge USERCLK2, posedge TRNTD[111], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[111]);
$setuphold (posedge USERCLK2, posedge TRNTD[112], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[112]);
$setuphold (posedge USERCLK2, posedge TRNTD[113], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[113]);
$setuphold (posedge USERCLK2, posedge TRNTD[114], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[114]);
$setuphold (posedge USERCLK2, posedge TRNTD[115], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[115]);
$setuphold (posedge USERCLK2, posedge TRNTD[116], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[116]);
$setuphold (posedge USERCLK2, posedge TRNTD[117], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[117]);
$setuphold (posedge USERCLK2, posedge TRNTD[118], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[118]);
$setuphold (posedge USERCLK2, posedge TRNTD[119], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[119]);
$setuphold (posedge USERCLK2, posedge TRNTD[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[11]);
$setuphold (posedge USERCLK2, posedge TRNTD[120], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[120]);
$setuphold (posedge USERCLK2, posedge TRNTD[121], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[121]);
$setuphold (posedge USERCLK2, posedge TRNTD[122], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[122]);
$setuphold (posedge USERCLK2, posedge TRNTD[123], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[123]);
$setuphold (posedge USERCLK2, posedge TRNTD[124], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[124]);
$setuphold (posedge USERCLK2, posedge TRNTD[125], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[125]);
$setuphold (posedge USERCLK2, posedge TRNTD[126], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[126]);
$setuphold (posedge USERCLK2, posedge TRNTD[127], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[127]);
$setuphold (posedge USERCLK2, posedge TRNTD[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[12]);
$setuphold (posedge USERCLK2, posedge TRNTD[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[13]);
$setuphold (posedge USERCLK2, posedge TRNTD[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[14]);
$setuphold (posedge USERCLK2, posedge TRNTD[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[15]);
$setuphold (posedge USERCLK2, posedge TRNTD[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[16]);
$setuphold (posedge USERCLK2, posedge TRNTD[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[17]);
$setuphold (posedge USERCLK2, posedge TRNTD[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[18]);
$setuphold (posedge USERCLK2, posedge TRNTD[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[19]);
$setuphold (posedge USERCLK2, posedge TRNTD[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[1]);
$setuphold (posedge USERCLK2, posedge TRNTD[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[20]);
$setuphold (posedge USERCLK2, posedge TRNTD[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[21]);
$setuphold (posedge USERCLK2, posedge TRNTD[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[22]);
$setuphold (posedge USERCLK2, posedge TRNTD[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[23]);
$setuphold (posedge USERCLK2, posedge TRNTD[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[24]);
$setuphold (posedge USERCLK2, posedge TRNTD[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[25]);
$setuphold (posedge USERCLK2, posedge TRNTD[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[26]);
$setuphold (posedge USERCLK2, posedge TRNTD[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[27]);
$setuphold (posedge USERCLK2, posedge TRNTD[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[28]);
$setuphold (posedge USERCLK2, posedge TRNTD[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[29]);
$setuphold (posedge USERCLK2, posedge TRNTD[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[2]);
$setuphold (posedge USERCLK2, posedge TRNTD[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[30]);
$setuphold (posedge USERCLK2, posedge TRNTD[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[31]);
$setuphold (posedge USERCLK2, posedge TRNTD[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[32]);
$setuphold (posedge USERCLK2, posedge TRNTD[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[33]);
$setuphold (posedge USERCLK2, posedge TRNTD[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[34]);
$setuphold (posedge USERCLK2, posedge TRNTD[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[35]);
$setuphold (posedge USERCLK2, posedge TRNTD[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[36]);
$setuphold (posedge USERCLK2, posedge TRNTD[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[37]);
$setuphold (posedge USERCLK2, posedge TRNTD[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[38]);
$setuphold (posedge USERCLK2, posedge TRNTD[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[39]);
$setuphold (posedge USERCLK2, posedge TRNTD[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[3]);
$setuphold (posedge USERCLK2, posedge TRNTD[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[40]);
$setuphold (posedge USERCLK2, posedge TRNTD[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[41]);
$setuphold (posedge USERCLK2, posedge TRNTD[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[42]);
$setuphold (posedge USERCLK2, posedge TRNTD[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[43]);
$setuphold (posedge USERCLK2, posedge TRNTD[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[44]);
$setuphold (posedge USERCLK2, posedge TRNTD[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[45]);
$setuphold (posedge USERCLK2, posedge TRNTD[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[46]);
$setuphold (posedge USERCLK2, posedge TRNTD[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[47]);
$setuphold (posedge USERCLK2, posedge TRNTD[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[48]);
$setuphold (posedge USERCLK2, posedge TRNTD[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[49]);
$setuphold (posedge USERCLK2, posedge TRNTD[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[4]);
$setuphold (posedge USERCLK2, posedge TRNTD[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[50]);
$setuphold (posedge USERCLK2, posedge TRNTD[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[51]);
$setuphold (posedge USERCLK2, posedge TRNTD[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[52]);
$setuphold (posedge USERCLK2, posedge TRNTD[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[53]);
$setuphold (posedge USERCLK2, posedge TRNTD[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[54]);
$setuphold (posedge USERCLK2, posedge TRNTD[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[55]);
$setuphold (posedge USERCLK2, posedge TRNTD[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[56]);
$setuphold (posedge USERCLK2, posedge TRNTD[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[57]);
$setuphold (posedge USERCLK2, posedge TRNTD[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[58]);
$setuphold (posedge USERCLK2, posedge TRNTD[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[59]);
$setuphold (posedge USERCLK2, posedge TRNTD[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[5]);
$setuphold (posedge USERCLK2, posedge TRNTD[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[60]);
$setuphold (posedge USERCLK2, posedge TRNTD[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[61]);
$setuphold (posedge USERCLK2, posedge TRNTD[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[62]);
$setuphold (posedge USERCLK2, posedge TRNTD[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[63]);
$setuphold (posedge USERCLK2, posedge TRNTD[64], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[64]);
$setuphold (posedge USERCLK2, posedge TRNTD[65], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[65]);
$setuphold (posedge USERCLK2, posedge TRNTD[66], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[66]);
$setuphold (posedge USERCLK2, posedge TRNTD[67], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[67]);
$setuphold (posedge USERCLK2, posedge TRNTD[68], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[68]);
$setuphold (posedge USERCLK2, posedge TRNTD[69], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[69]);
$setuphold (posedge USERCLK2, posedge TRNTD[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[6]);
$setuphold (posedge USERCLK2, posedge TRNTD[70], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[70]);
$setuphold (posedge USERCLK2, posedge TRNTD[71], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[71]);
$setuphold (posedge USERCLK2, posedge TRNTD[72], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[72]);
$setuphold (posedge USERCLK2, posedge TRNTD[73], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[73]);
$setuphold (posedge USERCLK2, posedge TRNTD[74], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[74]);
$setuphold (posedge USERCLK2, posedge TRNTD[75], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[75]);
$setuphold (posedge USERCLK2, posedge TRNTD[76], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[76]);
$setuphold (posedge USERCLK2, posedge TRNTD[77], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[77]);
$setuphold (posedge USERCLK2, posedge TRNTD[78], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[78]);
$setuphold (posedge USERCLK2, posedge TRNTD[79], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[79]);
$setuphold (posedge USERCLK2, posedge TRNTD[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[7]);
$setuphold (posedge USERCLK2, posedge TRNTD[80], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[80]);
$setuphold (posedge USERCLK2, posedge TRNTD[81], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[81]);
$setuphold (posedge USERCLK2, posedge TRNTD[82], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[82]);
$setuphold (posedge USERCLK2, posedge TRNTD[83], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[83]);
$setuphold (posedge USERCLK2, posedge TRNTD[84], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[84]);
$setuphold (posedge USERCLK2, posedge TRNTD[85], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[85]);
$setuphold (posedge USERCLK2, posedge TRNTD[86], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[86]);
$setuphold (posedge USERCLK2, posedge TRNTD[87], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[87]);
$setuphold (posedge USERCLK2, posedge TRNTD[88], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[88]);
$setuphold (posedge USERCLK2, posedge TRNTD[89], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[89]);
$setuphold (posedge USERCLK2, posedge TRNTD[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[8]);
$setuphold (posedge USERCLK2, posedge TRNTD[90], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[90]);
$setuphold (posedge USERCLK2, posedge TRNTD[91], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[91]);
$setuphold (posedge USERCLK2, posedge TRNTD[92], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[92]);
$setuphold (posedge USERCLK2, posedge TRNTD[93], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[93]);
$setuphold (posedge USERCLK2, posedge TRNTD[94], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[94]);
$setuphold (posedge USERCLK2, posedge TRNTD[95], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[95]);
$setuphold (posedge USERCLK2, posedge TRNTD[96], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[96]);
$setuphold (posedge USERCLK2, posedge TRNTD[97], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[97]);
$setuphold (posedge USERCLK2, posedge TRNTD[98], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[98]);
$setuphold (posedge USERCLK2, posedge TRNTD[99], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[99]);
$setuphold (posedge USERCLK2, posedge TRNTD[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTD[9]);
$setuphold (posedge USERCLK2, posedge TRNTECRCGEN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTECRCGEN);
$setuphold (posedge USERCLK2, posedge TRNTEOF, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTEOF);
$setuphold (posedge USERCLK2, posedge TRNTERRFWD, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTERRFWD);
$setuphold (posedge USERCLK2, posedge TRNTREM[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTREM[0]);
$setuphold (posedge USERCLK2, posedge TRNTREM[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTREM[1]);
$setuphold (posedge USERCLK2, posedge TRNTSOF, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTSOF);
$setuphold (posedge USERCLK2, posedge TRNTSRCDSC, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTSRCDSC);
$setuphold (posedge USERCLK2, posedge TRNTSRCRDY, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTSRCRDY);
$setuphold (posedge USERCLK2, posedge TRNTSTR, 0:0:0, 0:0:0, notifier,,, delay_USERCLK2, delay_TRNTSTR);
`endif
( DRPCLK *> DRPDO[0]) = (0, 0);
( DRPCLK *> DRPDO[10]) = (0, 0);
( DRPCLK *> DRPDO[11]) = (0, 0);
( DRPCLK *> DRPDO[12]) = (0, 0);
( DRPCLK *> DRPDO[13]) = (0, 0);
( DRPCLK *> DRPDO[14]) = (0, 0);
( DRPCLK *> DRPDO[15]) = (0, 0);
( DRPCLK *> DRPDO[1]) = (0, 0);
( DRPCLK *> DRPDO[2]) = (0, 0);
( DRPCLK *> DRPDO[3]) = (0, 0);
( DRPCLK *> DRPDO[4]) = (0, 0);
( DRPCLK *> DRPDO[5]) = (0, 0);
( DRPCLK *> DRPDO[6]) = (0, 0);
( DRPCLK *> DRPDO[7]) = (0, 0);
( DRPCLK *> DRPDO[8]) = (0, 0);
( DRPCLK *> DRPDO[9]) = (0, 0);
( DRPCLK *> DRPRDY) = (0, 0);
( PIPECLK *> PIPERX0POLARITY) = (0, 0);
( PIPECLK *> PIPERX1POLARITY) = (0, 0);
( PIPECLK *> PIPERX2POLARITY) = (0, 0);
( PIPECLK *> PIPERX3POLARITY) = (0, 0);
( PIPECLK *> PIPERX4POLARITY) = (0, 0);
( PIPECLK *> PIPERX5POLARITY) = (0, 0);
( PIPECLK *> PIPERX6POLARITY) = (0, 0);
( PIPECLK *> PIPERX7POLARITY) = (0, 0);
( PIPECLK *> PIPETX0CHARISK[0]) = (0, 0);
( PIPECLK *> PIPETX0CHARISK[1]) = (0, 0);
( PIPECLK *> PIPETX0COMPLIANCE) = (0, 0);
( PIPECLK *> PIPETX0DATA[0]) = (0, 0);
( PIPECLK *> PIPETX0DATA[10]) = (0, 0);
( PIPECLK *> PIPETX0DATA[11]) = (0, 0);
( PIPECLK *> PIPETX0DATA[12]) = (0, 0);
( PIPECLK *> PIPETX0DATA[13]) = (0, 0);
( PIPECLK *> PIPETX0DATA[14]) = (0, 0);
( PIPECLK *> PIPETX0DATA[15]) = (0, 0);
( PIPECLK *> PIPETX0DATA[1]) = (0, 0);
( PIPECLK *> PIPETX0DATA[2]) = (0, 0);
( PIPECLK *> PIPETX0DATA[3]) = (0, 0);
( PIPECLK *> PIPETX0DATA[4]) = (0, 0);
( PIPECLK *> PIPETX0DATA[5]) = (0, 0);
( PIPECLK *> PIPETX0DATA[6]) = (0, 0);
( PIPECLK *> PIPETX0DATA[7]) = (0, 0);
( PIPECLK *> PIPETX0DATA[8]) = (0, 0);
( PIPECLK *> PIPETX0DATA[9]) = (0, 0);
( PIPECLK *> PIPETX0ELECIDLE) = (0, 0);
( PIPECLK *> PIPETX0POWERDOWN[0]) = (0, 0);
( PIPECLK *> PIPETX0POWERDOWN[1]) = (0, 0);
( PIPECLK *> PIPETX1CHARISK[0]) = (0, 0);
( PIPECLK *> PIPETX1CHARISK[1]) = (0, 0);
( PIPECLK *> PIPETX1COMPLIANCE) = (0, 0);
( PIPECLK *> PIPETX1DATA[0]) = (0, 0);
( PIPECLK *> PIPETX1DATA[10]) = (0, 0);
( PIPECLK *> PIPETX1DATA[11]) = (0, 0);
( PIPECLK *> PIPETX1DATA[12]) = (0, 0);
( PIPECLK *> PIPETX1DATA[13]) = (0, 0);
( PIPECLK *> PIPETX1DATA[14]) = (0, 0);
( PIPECLK *> PIPETX1DATA[15]) = (0, 0);
( PIPECLK *> PIPETX1DATA[1]) = (0, 0);
( PIPECLK *> PIPETX1DATA[2]) = (0, 0);
( PIPECLK *> PIPETX1DATA[3]) = (0, 0);
( PIPECLK *> PIPETX1DATA[4]) = (0, 0);
( PIPECLK *> PIPETX1DATA[5]) = (0, 0);
( PIPECLK *> PIPETX1DATA[6]) = (0, 0);
( PIPECLK *> PIPETX1DATA[7]) = (0, 0);
( PIPECLK *> PIPETX1DATA[8]) = (0, 0);
( PIPECLK *> PIPETX1DATA[9]) = (0, 0);
( PIPECLK *> PIPETX1ELECIDLE) = (0, 0);
( PIPECLK *> PIPETX1POWERDOWN[0]) = (0, 0);
( PIPECLK *> PIPETX1POWERDOWN[1]) = (0, 0);
( PIPECLK *> PIPETX2CHARISK[0]) = (0, 0);
( PIPECLK *> PIPETX2CHARISK[1]) = (0, 0);
( PIPECLK *> PIPETX2COMPLIANCE) = (0, 0);
( PIPECLK *> PIPETX2DATA[0]) = (0, 0);
( PIPECLK *> PIPETX2DATA[10]) = (0, 0);
( PIPECLK *> PIPETX2DATA[11]) = (0, 0);
( PIPECLK *> PIPETX2DATA[12]) = (0, 0);
( PIPECLK *> PIPETX2DATA[13]) = (0, 0);
( PIPECLK *> PIPETX2DATA[14]) = (0, 0);
( PIPECLK *> PIPETX2DATA[15]) = (0, 0);
( PIPECLK *> PIPETX2DATA[1]) = (0, 0);
( PIPECLK *> PIPETX2DATA[2]) = (0, 0);
( PIPECLK *> PIPETX2DATA[3]) = (0, 0);
( PIPECLK *> PIPETX2DATA[4]) = (0, 0);
( PIPECLK *> PIPETX2DATA[5]) = (0, 0);
( PIPECLK *> PIPETX2DATA[6]) = (0, 0);
( PIPECLK *> PIPETX2DATA[7]) = (0, 0);
( PIPECLK *> PIPETX2DATA[8]) = (0, 0);
( PIPECLK *> PIPETX2DATA[9]) = (0, 0);
( PIPECLK *> PIPETX2ELECIDLE) = (0, 0);
( PIPECLK *> PIPETX2POWERDOWN[0]) = (0, 0);
( PIPECLK *> PIPETX2POWERDOWN[1]) = (0, 0);
( PIPECLK *> PIPETX3CHARISK[0]) = (0, 0);
( PIPECLK *> PIPETX3CHARISK[1]) = (0, 0);
( PIPECLK *> PIPETX3COMPLIANCE) = (0, 0);
( PIPECLK *> PIPETX3DATA[0]) = (0, 0);
( PIPECLK *> PIPETX3DATA[10]) = (0, 0);
( PIPECLK *> PIPETX3DATA[11]) = (0, 0);
( PIPECLK *> PIPETX3DATA[12]) = (0, 0);
( PIPECLK *> PIPETX3DATA[13]) = (0, 0);
( PIPECLK *> PIPETX3DATA[14]) = (0, 0);
( PIPECLK *> PIPETX3DATA[15]) = (0, 0);
( PIPECLK *> PIPETX3DATA[1]) = (0, 0);
( PIPECLK *> PIPETX3DATA[2]) = (0, 0);
( PIPECLK *> PIPETX3DATA[3]) = (0, 0);
( PIPECLK *> PIPETX3DATA[4]) = (0, 0);
( PIPECLK *> PIPETX3DATA[5]) = (0, 0);
( PIPECLK *> PIPETX3DATA[6]) = (0, 0);
( PIPECLK *> PIPETX3DATA[7]) = (0, 0);
( PIPECLK *> PIPETX3DATA[8]) = (0, 0);
( PIPECLK *> PIPETX3DATA[9]) = (0, 0);
( PIPECLK *> PIPETX3ELECIDLE) = (0, 0);
( PIPECLK *> PIPETX3POWERDOWN[0]) = (0, 0);
( PIPECLK *> PIPETX3POWERDOWN[1]) = (0, 0);
( PIPECLK *> PIPETX4CHARISK[0]) = (0, 0);
( PIPECLK *> PIPETX4CHARISK[1]) = (0, 0);
( PIPECLK *> PIPETX4COMPLIANCE) = (0, 0);
( PIPECLK *> PIPETX4DATA[0]) = (0, 0);
( PIPECLK *> PIPETX4DATA[10]) = (0, 0);
( PIPECLK *> PIPETX4DATA[11]) = (0, 0);
( PIPECLK *> PIPETX4DATA[12]) = (0, 0);
( PIPECLK *> PIPETX4DATA[13]) = (0, 0);
( PIPECLK *> PIPETX4DATA[14]) = (0, 0);
( PIPECLK *> PIPETX4DATA[15]) = (0, 0);
( PIPECLK *> PIPETX4DATA[1]) = (0, 0);
( PIPECLK *> PIPETX4DATA[2]) = (0, 0);
( PIPECLK *> PIPETX4DATA[3]) = (0, 0);
( PIPECLK *> PIPETX4DATA[4]) = (0, 0);
( PIPECLK *> PIPETX4DATA[5]) = (0, 0);
( PIPECLK *> PIPETX4DATA[6]) = (0, 0);
( PIPECLK *> PIPETX4DATA[7]) = (0, 0);
( PIPECLK *> PIPETX4DATA[8]) = (0, 0);
( PIPECLK *> PIPETX4DATA[9]) = (0, 0);
( PIPECLK *> PIPETX4ELECIDLE) = (0, 0);
( PIPECLK *> PIPETX4POWERDOWN[0]) = (0, 0);
( PIPECLK *> PIPETX4POWERDOWN[1]) = (0, 0);
( PIPECLK *> PIPETX5CHARISK[0]) = (0, 0);
( PIPECLK *> PIPETX5CHARISK[1]) = (0, 0);
( PIPECLK *> PIPETX5COMPLIANCE) = (0, 0);
( PIPECLK *> PIPETX5DATA[0]) = (0, 0);
( PIPECLK *> PIPETX5DATA[10]) = (0, 0);
( PIPECLK *> PIPETX5DATA[11]) = (0, 0);
( PIPECLK *> PIPETX5DATA[12]) = (0, 0);
( PIPECLK *> PIPETX5DATA[13]) = (0, 0);
( PIPECLK *> PIPETX5DATA[14]) = (0, 0);
( PIPECLK *> PIPETX5DATA[15]) = (0, 0);
( PIPECLK *> PIPETX5DATA[1]) = (0, 0);
( PIPECLK *> PIPETX5DATA[2]) = (0, 0);
( PIPECLK *> PIPETX5DATA[3]) = (0, 0);
( PIPECLK *> PIPETX5DATA[4]) = (0, 0);
( PIPECLK *> PIPETX5DATA[5]) = (0, 0);
( PIPECLK *> PIPETX5DATA[6]) = (0, 0);
( PIPECLK *> PIPETX5DATA[7]) = (0, 0);
( PIPECLK *> PIPETX5DATA[8]) = (0, 0);
( PIPECLK *> PIPETX5DATA[9]) = (0, 0);
( PIPECLK *> PIPETX5ELECIDLE) = (0, 0);
( PIPECLK *> PIPETX5POWERDOWN[0]) = (0, 0);
( PIPECLK *> PIPETX5POWERDOWN[1]) = (0, 0);
( PIPECLK *> PIPETX6CHARISK[0]) = (0, 0);
( PIPECLK *> PIPETX6CHARISK[1]) = (0, 0);
( PIPECLK *> PIPETX6COMPLIANCE) = (0, 0);
( PIPECLK *> PIPETX6DATA[0]) = (0, 0);
( PIPECLK *> PIPETX6DATA[10]) = (0, 0);
( PIPECLK *> PIPETX6DATA[11]) = (0, 0);
( PIPECLK *> PIPETX6DATA[12]) = (0, 0);
( PIPECLK *> PIPETX6DATA[13]) = (0, 0);
( PIPECLK *> PIPETX6DATA[14]) = (0, 0);
( PIPECLK *> PIPETX6DATA[15]) = (0, 0);
( PIPECLK *> PIPETX6DATA[1]) = (0, 0);
( PIPECLK *> PIPETX6DATA[2]) = (0, 0);
( PIPECLK *> PIPETX6DATA[3]) = (0, 0);
( PIPECLK *> PIPETX6DATA[4]) = (0, 0);
( PIPECLK *> PIPETX6DATA[5]) = (0, 0);
( PIPECLK *> PIPETX6DATA[6]) = (0, 0);
( PIPECLK *> PIPETX6DATA[7]) = (0, 0);
( PIPECLK *> PIPETX6DATA[8]) = (0, 0);
( PIPECLK *> PIPETX6DATA[9]) = (0, 0);
( PIPECLK *> PIPETX6ELECIDLE) = (0, 0);
( PIPECLK *> PIPETX6POWERDOWN[0]) = (0, 0);
( PIPECLK *> PIPETX6POWERDOWN[1]) = (0, 0);
( PIPECLK *> PIPETX7CHARISK[0]) = (0, 0);
( PIPECLK *> PIPETX7CHARISK[1]) = (0, 0);
( PIPECLK *> PIPETX7COMPLIANCE) = (0, 0);
( PIPECLK *> PIPETX7DATA[0]) = (0, 0);
( PIPECLK *> PIPETX7DATA[10]) = (0, 0);
( PIPECLK *> PIPETX7DATA[11]) = (0, 0);
( PIPECLK *> PIPETX7DATA[12]) = (0, 0);
( PIPECLK *> PIPETX7DATA[13]) = (0, 0);
( PIPECLK *> PIPETX7DATA[14]) = (0, 0);
( PIPECLK *> PIPETX7DATA[15]) = (0, 0);
( PIPECLK *> PIPETX7DATA[1]) = (0, 0);
( PIPECLK *> PIPETX7DATA[2]) = (0, 0);
( PIPECLK *> PIPETX7DATA[3]) = (0, 0);
( PIPECLK *> PIPETX7DATA[4]) = (0, 0);
( PIPECLK *> PIPETX7DATA[5]) = (0, 0);
( PIPECLK *> PIPETX7DATA[6]) = (0, 0);
( PIPECLK *> PIPETX7DATA[7]) = (0, 0);
( PIPECLK *> PIPETX7DATA[8]) = (0, 0);
( PIPECLK *> PIPETX7DATA[9]) = (0, 0);
( PIPECLK *> PIPETX7ELECIDLE) = (0, 0);
( PIPECLK *> PIPETX7POWERDOWN[0]) = (0, 0);
( PIPECLK *> PIPETX7POWERDOWN[1]) = (0, 0);
( PIPECLK *> PIPETXDEEMPH) = (0, 0);
( PIPECLK *> PIPETXMARGIN[0]) = (0, 0);
( PIPECLK *> PIPETXMARGIN[1]) = (0, 0);
( PIPECLK *> PIPETXMARGIN[2]) = (0, 0);
( PIPECLK *> PIPETXRATE) = (0, 0);
( PIPECLK *> PIPETXRCVRDET) = (0, 0);
( PIPECLK *> PIPETXRESET) = (0, 0);
( PIPECLK *> PLDBGVEC[0]) = (0, 0);
( PIPECLK *> PLDBGVEC[10]) = (0, 0);
( PIPECLK *> PLDBGVEC[11]) = (0, 0);
( PIPECLK *> PLDBGVEC[1]) = (0, 0);
( PIPECLK *> PLDBGVEC[2]) = (0, 0);
( PIPECLK *> PLDBGVEC[3]) = (0, 0);
( PIPECLK *> PLDBGVEC[4]) = (0, 0);
( PIPECLK *> PLDBGVEC[5]) = (0, 0);
( PIPECLK *> PLDBGVEC[6]) = (0, 0);
( PIPECLK *> PLDBGVEC[7]) = (0, 0);
( PIPECLK *> PLDBGVEC[8]) = (0, 0);
( PIPECLK *> PLDBGVEC[9]) = (0, 0);
( PIPECLK *> PLDIRECTEDCHANGEDONE) = (0, 0);
( PIPECLK *> PLINITIALLINKWIDTH[0]) = (0, 0);
( PIPECLK *> PLINITIALLINKWIDTH[1]) = (0, 0);
( PIPECLK *> PLINITIALLINKWIDTH[2]) = (0, 0);
( PIPECLK *> PLLANEREVERSALMODE[0]) = (0, 0);
( PIPECLK *> PLLANEREVERSALMODE[1]) = (0, 0);
( PIPECLK *> PLLINKGEN2CAP) = (0, 0);
( PIPECLK *> PLLINKPARTNERGEN2SUPPORTED) = (0, 0);
( PIPECLK *> PLLINKUPCFGCAP) = (0, 0);
( PIPECLK *> PLLTSSMSTATE[0]) = (0, 0);
( PIPECLK *> PLLTSSMSTATE[1]) = (0, 0);
( PIPECLK *> PLLTSSMSTATE[2]) = (0, 0);
( PIPECLK *> PLLTSSMSTATE[3]) = (0, 0);
( PIPECLK *> PLLTSSMSTATE[4]) = (0, 0);
( PIPECLK *> PLLTSSMSTATE[5]) = (0, 0);
( PIPECLK *> PLPHYLNKUPN) = (0, 0);
( PIPECLK *> PLRECEIVEDHOTRST) = (0, 0);
( PIPECLK *> PLRXPMSTATE[0]) = (0, 0);
( PIPECLK *> PLRXPMSTATE[1]) = (0, 0);
( PIPECLK *> PLSELLNKRATE) = (0, 0);
( PIPECLK *> PLSELLNKWIDTH[0]) = (0, 0);
( PIPECLK *> PLSELLNKWIDTH[1]) = (0, 0);
( PIPECLK *> PLTXPMSTATE[0]) = (0, 0);
( PIPECLK *> PLTXPMSTATE[1]) = (0, 0);
( PIPECLK *> PLTXPMSTATE[2]) = (0, 0);
( USERCLK *> LNKCLKEN) = (0, 0);
( USERCLK *> MIMRXRADDR[0]) = (0, 0);
( USERCLK *> MIMRXRADDR[10]) = (0, 0);
( USERCLK *> MIMRXRADDR[11]) = (0, 0);
( USERCLK *> MIMRXRADDR[12]) = (0, 0);
( USERCLK *> MIMRXRADDR[1]) = (0, 0);
( USERCLK *> MIMRXRADDR[2]) = (0, 0);
( USERCLK *> MIMRXRADDR[3]) = (0, 0);
( USERCLK *> MIMRXRADDR[4]) = (0, 0);
( USERCLK *> MIMRXRADDR[5]) = (0, 0);
( USERCLK *> MIMRXRADDR[6]) = (0, 0);
( USERCLK *> MIMRXRADDR[7]) = (0, 0);
( USERCLK *> MIMRXRADDR[8]) = (0, 0);
( USERCLK *> MIMRXRADDR[9]) = (0, 0);
( USERCLK *> MIMRXREN) = (0, 0);
( USERCLK *> MIMRXWADDR[0]) = (0, 0);
( USERCLK *> MIMRXWADDR[10]) = (0, 0);
( USERCLK *> MIMRXWADDR[11]) = (0, 0);
( USERCLK *> MIMRXWADDR[12]) = (0, 0);
( USERCLK *> MIMRXWADDR[1]) = (0, 0);
( USERCLK *> MIMRXWADDR[2]) = (0, 0);
( USERCLK *> MIMRXWADDR[3]) = (0, 0);
( USERCLK *> MIMRXWADDR[4]) = (0, 0);
( USERCLK *> MIMRXWADDR[5]) = (0, 0);
( USERCLK *> MIMRXWADDR[6]) = (0, 0);
( USERCLK *> MIMRXWADDR[7]) = (0, 0);
( USERCLK *> MIMRXWADDR[8]) = (0, 0);
( USERCLK *> MIMRXWADDR[9]) = (0, 0);
( USERCLK *> MIMRXWDATA[0]) = (0, 0);
( USERCLK *> MIMRXWDATA[10]) = (0, 0);
( USERCLK *> MIMRXWDATA[11]) = (0, 0);
( USERCLK *> MIMRXWDATA[12]) = (0, 0);
( USERCLK *> MIMRXWDATA[13]) = (0, 0);
( USERCLK *> MIMRXWDATA[14]) = (0, 0);
( USERCLK *> MIMRXWDATA[15]) = (0, 0);
( USERCLK *> MIMRXWDATA[16]) = (0, 0);
( USERCLK *> MIMRXWDATA[17]) = (0, 0);
( USERCLK *> MIMRXWDATA[18]) = (0, 0);
( USERCLK *> MIMRXWDATA[19]) = (0, 0);
( USERCLK *> MIMRXWDATA[1]) = (0, 0);
( USERCLK *> MIMRXWDATA[20]) = (0, 0);
( USERCLK *> MIMRXWDATA[21]) = (0, 0);
( USERCLK *> MIMRXWDATA[22]) = (0, 0);
( USERCLK *> MIMRXWDATA[23]) = (0, 0);
( USERCLK *> MIMRXWDATA[24]) = (0, 0);
( USERCLK *> MIMRXWDATA[25]) = (0, 0);
( USERCLK *> MIMRXWDATA[26]) = (0, 0);
( USERCLK *> MIMRXWDATA[27]) = (0, 0);
( USERCLK *> MIMRXWDATA[28]) = (0, 0);
( USERCLK *> MIMRXWDATA[29]) = (0, 0);
( USERCLK *> MIMRXWDATA[2]) = (0, 0);
( USERCLK *> MIMRXWDATA[30]) = (0, 0);
( USERCLK *> MIMRXWDATA[31]) = (0, 0);
( USERCLK *> MIMRXWDATA[32]) = (0, 0);
( USERCLK *> MIMRXWDATA[33]) = (0, 0);
( USERCLK *> MIMRXWDATA[34]) = (0, 0);
( USERCLK *> MIMRXWDATA[35]) = (0, 0);
( USERCLK *> MIMRXWDATA[36]) = (0, 0);
( USERCLK *> MIMRXWDATA[37]) = (0, 0);
( USERCLK *> MIMRXWDATA[38]) = (0, 0);
( USERCLK *> MIMRXWDATA[39]) = (0, 0);
( USERCLK *> MIMRXWDATA[3]) = (0, 0);
( USERCLK *> MIMRXWDATA[40]) = (0, 0);
( USERCLK *> MIMRXWDATA[41]) = (0, 0);
( USERCLK *> MIMRXWDATA[42]) = (0, 0);
( USERCLK *> MIMRXWDATA[43]) = (0, 0);
( USERCLK *> MIMRXWDATA[44]) = (0, 0);
( USERCLK *> MIMRXWDATA[45]) = (0, 0);
( USERCLK *> MIMRXWDATA[46]) = (0, 0);
( USERCLK *> MIMRXWDATA[47]) = (0, 0);
( USERCLK *> MIMRXWDATA[48]) = (0, 0);
( USERCLK *> MIMRXWDATA[49]) = (0, 0);
( USERCLK *> MIMRXWDATA[4]) = (0, 0);
( USERCLK *> MIMRXWDATA[50]) = (0, 0);
( USERCLK *> MIMRXWDATA[51]) = (0, 0);
( USERCLK *> MIMRXWDATA[52]) = (0, 0);
( USERCLK *> MIMRXWDATA[53]) = (0, 0);
( USERCLK *> MIMRXWDATA[54]) = (0, 0);
( USERCLK *> MIMRXWDATA[55]) = (0, 0);
( USERCLK *> MIMRXWDATA[56]) = (0, 0);
( USERCLK *> MIMRXWDATA[57]) = (0, 0);
( USERCLK *> MIMRXWDATA[58]) = (0, 0);
( USERCLK *> MIMRXWDATA[59]) = (0, 0);
( USERCLK *> MIMRXWDATA[5]) = (0, 0);
( USERCLK *> MIMRXWDATA[60]) = (0, 0);
( USERCLK *> MIMRXWDATA[61]) = (0, 0);
( USERCLK *> MIMRXWDATA[62]) = (0, 0);
( USERCLK *> MIMRXWDATA[63]) = (0, 0);
( USERCLK *> MIMRXWDATA[64]) = (0, 0);
( USERCLK *> MIMRXWDATA[65]) = (0, 0);
( USERCLK *> MIMRXWDATA[66]) = (0, 0);
( USERCLK *> MIMRXWDATA[67]) = (0, 0);
( USERCLK *> MIMRXWDATA[6]) = (0, 0);
( USERCLK *> MIMRXWDATA[7]) = (0, 0);
( USERCLK *> MIMRXWDATA[8]) = (0, 0);
( USERCLK *> MIMRXWDATA[9]) = (0, 0);
( USERCLK *> MIMRXWEN) = (0, 0);
( USERCLK *> MIMTXRADDR[0]) = (0, 0);
( USERCLK *> MIMTXRADDR[10]) = (0, 0);
( USERCLK *> MIMTXRADDR[11]) = (0, 0);
( USERCLK *> MIMTXRADDR[12]) = (0, 0);
( USERCLK *> MIMTXRADDR[1]) = (0, 0);
( USERCLK *> MIMTXRADDR[2]) = (0, 0);
( USERCLK *> MIMTXRADDR[3]) = (0, 0);
( USERCLK *> MIMTXRADDR[4]) = (0, 0);
( USERCLK *> MIMTXRADDR[5]) = (0, 0);
( USERCLK *> MIMTXRADDR[6]) = (0, 0);
( USERCLK *> MIMTXRADDR[7]) = (0, 0);
( USERCLK *> MIMTXRADDR[8]) = (0, 0);
( USERCLK *> MIMTXRADDR[9]) = (0, 0);
( USERCLK *> MIMTXREN) = (0, 0);
( USERCLK *> MIMTXWADDR[0]) = (0, 0);
( USERCLK *> MIMTXWADDR[10]) = (0, 0);
( USERCLK *> MIMTXWADDR[11]) = (0, 0);
( USERCLK *> MIMTXWADDR[12]) = (0, 0);
( USERCLK *> MIMTXWADDR[1]) = (0, 0);
( USERCLK *> MIMTXWADDR[2]) = (0, 0);
( USERCLK *> MIMTXWADDR[3]) = (0, 0);
( USERCLK *> MIMTXWADDR[4]) = (0, 0);
( USERCLK *> MIMTXWADDR[5]) = (0, 0);
( USERCLK *> MIMTXWADDR[6]) = (0, 0);
( USERCLK *> MIMTXWADDR[7]) = (0, 0);
( USERCLK *> MIMTXWADDR[8]) = (0, 0);
( USERCLK *> MIMTXWADDR[9]) = (0, 0);
( USERCLK *> MIMTXWDATA[0]) = (0, 0);
( USERCLK *> MIMTXWDATA[10]) = (0, 0);
( USERCLK *> MIMTXWDATA[11]) = (0, 0);
( USERCLK *> MIMTXWDATA[12]) = (0, 0);
( USERCLK *> MIMTXWDATA[13]) = (0, 0);
( USERCLK *> MIMTXWDATA[14]) = (0, 0);
( USERCLK *> MIMTXWDATA[15]) = (0, 0);
( USERCLK *> MIMTXWDATA[16]) = (0, 0);
( USERCLK *> MIMTXWDATA[17]) = (0, 0);
( USERCLK *> MIMTXWDATA[18]) = (0, 0);
( USERCLK *> MIMTXWDATA[19]) = (0, 0);
( USERCLK *> MIMTXWDATA[1]) = (0, 0);
( USERCLK *> MIMTXWDATA[20]) = (0, 0);
( USERCLK *> MIMTXWDATA[21]) = (0, 0);
( USERCLK *> MIMTXWDATA[22]) = (0, 0);
( USERCLK *> MIMTXWDATA[23]) = (0, 0);
( USERCLK *> MIMTXWDATA[24]) = (0, 0);
( USERCLK *> MIMTXWDATA[25]) = (0, 0);
( USERCLK *> MIMTXWDATA[26]) = (0, 0);
( USERCLK *> MIMTXWDATA[27]) = (0, 0);
( USERCLK *> MIMTXWDATA[28]) = (0, 0);
( USERCLK *> MIMTXWDATA[29]) = (0, 0);
( USERCLK *> MIMTXWDATA[2]) = (0, 0);
( USERCLK *> MIMTXWDATA[30]) = (0, 0);
( USERCLK *> MIMTXWDATA[31]) = (0, 0);
( USERCLK *> MIMTXWDATA[32]) = (0, 0);
( USERCLK *> MIMTXWDATA[33]) = (0, 0);
( USERCLK *> MIMTXWDATA[34]) = (0, 0);
( USERCLK *> MIMTXWDATA[35]) = (0, 0);
( USERCLK *> MIMTXWDATA[36]) = (0, 0);
( USERCLK *> MIMTXWDATA[37]) = (0, 0);
( USERCLK *> MIMTXWDATA[38]) = (0, 0);
( USERCLK *> MIMTXWDATA[39]) = (0, 0);
( USERCLK *> MIMTXWDATA[3]) = (0, 0);
( USERCLK *> MIMTXWDATA[40]) = (0, 0);
( USERCLK *> MIMTXWDATA[41]) = (0, 0);
( USERCLK *> MIMTXWDATA[42]) = (0, 0);
( USERCLK *> MIMTXWDATA[43]) = (0, 0);
( USERCLK *> MIMTXWDATA[44]) = (0, 0);
( USERCLK *> MIMTXWDATA[45]) = (0, 0);
( USERCLK *> MIMTXWDATA[46]) = (0, 0);
( USERCLK *> MIMTXWDATA[47]) = (0, 0);
( USERCLK *> MIMTXWDATA[48]) = (0, 0);
( USERCLK *> MIMTXWDATA[49]) = (0, 0);
( USERCLK *> MIMTXWDATA[4]) = (0, 0);
( USERCLK *> MIMTXWDATA[50]) = (0, 0);
( USERCLK *> MIMTXWDATA[51]) = (0, 0);
( USERCLK *> MIMTXWDATA[52]) = (0, 0);
( USERCLK *> MIMTXWDATA[53]) = (0, 0);
( USERCLK *> MIMTXWDATA[54]) = (0, 0);
( USERCLK *> MIMTXWDATA[55]) = (0, 0);
( USERCLK *> MIMTXWDATA[56]) = (0, 0);
( USERCLK *> MIMTXWDATA[57]) = (0, 0);
( USERCLK *> MIMTXWDATA[58]) = (0, 0);
( USERCLK *> MIMTXWDATA[59]) = (0, 0);
( USERCLK *> MIMTXWDATA[5]) = (0, 0);
( USERCLK *> MIMTXWDATA[60]) = (0, 0);
( USERCLK *> MIMTXWDATA[61]) = (0, 0);
( USERCLK *> MIMTXWDATA[62]) = (0, 0);
( USERCLK *> MIMTXWDATA[63]) = (0, 0);
( USERCLK *> MIMTXWDATA[64]) = (0, 0);
( USERCLK *> MIMTXWDATA[65]) = (0, 0);
( USERCLK *> MIMTXWDATA[66]) = (0, 0);
( USERCLK *> MIMTXWDATA[67]) = (0, 0);
( USERCLK *> MIMTXWDATA[68]) = (0, 0);
( USERCLK *> MIMTXWDATA[6]) = (0, 0);
( USERCLK *> MIMTXWDATA[7]) = (0, 0);
( USERCLK *> MIMTXWDATA[8]) = (0, 0);
( USERCLK *> MIMTXWDATA[9]) = (0, 0);
( USERCLK *> MIMTXWEN) = (0, 0);
( USERCLK2 *> CFGAERECRCCHECKEN) = (0, 0);
( USERCLK2 *> CFGAERECRCGENEN) = (0, 0);
( USERCLK2 *> CFGAERROOTERRCORRERRRECEIVED) = (0, 0);
( USERCLK2 *> CFGAERROOTERRCORRERRREPORTINGEN) = (0, 0);
( USERCLK2 *> CFGAERROOTERRFATALERRRECEIVED) = (0, 0);
( USERCLK2 *> CFGAERROOTERRFATALERRREPORTINGEN) = (0, 0);
( USERCLK2 *> CFGAERROOTERRNONFATALERRRECEIVED) = (0, 0);
( USERCLK2 *> CFGAERROOTERRNONFATALERRREPORTINGEN) = (0, 0);
( USERCLK2 *> CFGBRIDGESERREN) = (0, 0);
( USERCLK2 *> CFGCOMMANDBUSMASTERENABLE) = (0, 0);
( USERCLK2 *> CFGCOMMANDINTERRUPTDISABLE) = (0, 0);
( USERCLK2 *> CFGCOMMANDIOENABLE) = (0, 0);
( USERCLK2 *> CFGCOMMANDMEMENABLE) = (0, 0);
( USERCLK2 *> CFGCOMMANDSERREN) = (0, 0);
( USERCLK2 *> CFGDEVCONTROL2ARIFORWARDEN) = (0, 0);
( USERCLK2 *> CFGDEVCONTROL2ATOMICEGRESSBLOCK) = (0, 0);
( USERCLK2 *> CFGDEVCONTROL2ATOMICREQUESTEREN) = (0, 0);
( USERCLK2 *> CFGDEVCONTROL2CPLTIMEOUTDIS) = (0, 0);
( USERCLK2 *> CFGDEVCONTROL2CPLTIMEOUTVAL[0]) = (0, 0);
( USERCLK2 *> CFGDEVCONTROL2CPLTIMEOUTVAL[1]) = (0, 0);
( USERCLK2 *> CFGDEVCONTROL2CPLTIMEOUTVAL[2]) = (0, 0);
( USERCLK2 *> CFGDEVCONTROL2CPLTIMEOUTVAL[3]) = (0, 0);
( USERCLK2 *> CFGDEVCONTROL2IDOCPLEN) = (0, 0);
( USERCLK2 *> CFGDEVCONTROL2IDOREQEN) = (0, 0);
( USERCLK2 *> CFGDEVCONTROL2LTREN) = (0, 0);
( USERCLK2 *> CFGDEVCONTROL2TLPPREFIXBLOCK) = (0, 0);
( USERCLK2 *> CFGDEVCONTROLAUXPOWEREN) = (0, 0);
( USERCLK2 *> CFGDEVCONTROLCORRERRREPORTINGEN) = (0, 0);
( USERCLK2 *> CFGDEVCONTROLENABLERO) = (0, 0);
( USERCLK2 *> CFGDEVCONTROLEXTTAGEN) = (0, 0);
( USERCLK2 *> CFGDEVCONTROLFATALERRREPORTINGEN) = (0, 0);
( USERCLK2 *> CFGDEVCONTROLMAXPAYLOAD[0]) = (0, 0);
( USERCLK2 *> CFGDEVCONTROLMAXPAYLOAD[1]) = (0, 0);
( USERCLK2 *> CFGDEVCONTROLMAXPAYLOAD[2]) = (0, 0);
( USERCLK2 *> CFGDEVCONTROLMAXREADREQ[0]) = (0, 0);
( USERCLK2 *> CFGDEVCONTROLMAXREADREQ[1]) = (0, 0);
( USERCLK2 *> CFGDEVCONTROLMAXREADREQ[2]) = (0, 0);
( USERCLK2 *> CFGDEVCONTROLNONFATALREPORTINGEN) = (0, 0);
( USERCLK2 *> CFGDEVCONTROLNOSNOOPEN) = (0, 0);
( USERCLK2 *> CFGDEVCONTROLPHANTOMEN) = (0, 0);
( USERCLK2 *> CFGDEVCONTROLURERRREPORTINGEN) = (0, 0);
( USERCLK2 *> CFGDEVSTATUSCORRERRDETECTED) = (0, 0);
( USERCLK2 *> CFGDEVSTATUSFATALERRDETECTED) = (0, 0);
( USERCLK2 *> CFGDEVSTATUSNONFATALERRDETECTED) = (0, 0);
( USERCLK2 *> CFGDEVSTATUSURDETECTED) = (0, 0);
( USERCLK2 *> CFGERRAERHEADERLOGSETN) = (0, 0);
( USERCLK2 *> CFGERRCPLRDYN) = (0, 0);
( USERCLK2 *> CFGINTERRUPTDO[0]) = (0, 0);
( USERCLK2 *> CFGINTERRUPTDO[1]) = (0, 0);
( USERCLK2 *> CFGINTERRUPTDO[2]) = (0, 0);
( USERCLK2 *> CFGINTERRUPTDO[3]) = (0, 0);
( USERCLK2 *> CFGINTERRUPTDO[4]) = (0, 0);
( USERCLK2 *> CFGINTERRUPTDO[5]) = (0, 0);
( USERCLK2 *> CFGINTERRUPTDO[6]) = (0, 0);
( USERCLK2 *> CFGINTERRUPTDO[7]) = (0, 0);
( USERCLK2 *> CFGINTERRUPTMMENABLE[0]) = (0, 0);
( USERCLK2 *> CFGINTERRUPTMMENABLE[1]) = (0, 0);
( USERCLK2 *> CFGINTERRUPTMMENABLE[2]) = (0, 0);
( USERCLK2 *> CFGINTERRUPTMSIENABLE) = (0, 0);
( USERCLK2 *> CFGINTERRUPTMSIXENABLE) = (0, 0);
( USERCLK2 *> CFGINTERRUPTMSIXFM) = (0, 0);
( USERCLK2 *> CFGINTERRUPTRDYN) = (0, 0);
( USERCLK2 *> CFGLINKCONTROLASPMCONTROL[0]) = (0, 0);
( USERCLK2 *> CFGLINKCONTROLASPMCONTROL[1]) = (0, 0);
( USERCLK2 *> CFGLINKCONTROLAUTOBANDWIDTHINTEN) = (0, 0);
( USERCLK2 *> CFGLINKCONTROLBANDWIDTHINTEN) = (0, 0);
( USERCLK2 *> CFGLINKCONTROLCLOCKPMEN) = (0, 0);
( USERCLK2 *> CFGLINKCONTROLCOMMONCLOCK) = (0, 0);
( USERCLK2 *> CFGLINKCONTROLEXTENDEDSYNC) = (0, 0);
( USERCLK2 *> CFGLINKCONTROLHWAUTOWIDTHDIS) = (0, 0);
( USERCLK2 *> CFGLINKCONTROLLINKDISABLE) = (0, 0);
( USERCLK2 *> CFGLINKCONTROLRCB) = (0, 0);
( USERCLK2 *> CFGLINKCONTROLRETRAINLINK) = (0, 0);
( USERCLK2 *> CFGLINKSTATUSAUTOBANDWIDTHSTATUS) = (0, 0);
( USERCLK2 *> CFGLINKSTATUSBANDWIDTHSTATUS) = (0, 0);
( USERCLK2 *> CFGLINKSTATUSCURRENTSPEED[0]) = (0, 0);
( USERCLK2 *> CFGLINKSTATUSCURRENTSPEED[1]) = (0, 0);
( USERCLK2 *> CFGLINKSTATUSDLLACTIVE) = (0, 0);
( USERCLK2 *> CFGLINKSTATUSLINKTRAINING) = (0, 0);
( USERCLK2 *> CFGLINKSTATUSNEGOTIATEDWIDTH[0]) = (0, 0);
( USERCLK2 *> CFGLINKSTATUSNEGOTIATEDWIDTH[1]) = (0, 0);
( USERCLK2 *> CFGLINKSTATUSNEGOTIATEDWIDTH[2]) = (0, 0);
( USERCLK2 *> CFGLINKSTATUSNEGOTIATEDWIDTH[3]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[0]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[10]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[11]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[12]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[13]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[14]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[15]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[16]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[17]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[18]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[19]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[1]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[20]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[21]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[22]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[23]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[24]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[25]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[26]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[27]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[28]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[29]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[2]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[30]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[31]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[3]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[4]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[5]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[6]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[7]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[8]) = (0, 0);
( USERCLK2 *> CFGMGMTDO[9]) = (0, 0);
( USERCLK2 *> CFGMGMTRDWRDONEN) = (0, 0);
( USERCLK2 *> CFGMSGDATA[0]) = (0, 0);
( USERCLK2 *> CFGMSGDATA[10]) = (0, 0);
( USERCLK2 *> CFGMSGDATA[11]) = (0, 0);
( USERCLK2 *> CFGMSGDATA[12]) = (0, 0);
( USERCLK2 *> CFGMSGDATA[13]) = (0, 0);
( USERCLK2 *> CFGMSGDATA[14]) = (0, 0);
( USERCLK2 *> CFGMSGDATA[15]) = (0, 0);
( USERCLK2 *> CFGMSGDATA[1]) = (0, 0);
( USERCLK2 *> CFGMSGDATA[2]) = (0, 0);
( USERCLK2 *> CFGMSGDATA[3]) = (0, 0);
( USERCLK2 *> CFGMSGDATA[4]) = (0, 0);
( USERCLK2 *> CFGMSGDATA[5]) = (0, 0);
( USERCLK2 *> CFGMSGDATA[6]) = (0, 0);
( USERCLK2 *> CFGMSGDATA[7]) = (0, 0);
( USERCLK2 *> CFGMSGDATA[8]) = (0, 0);
( USERCLK2 *> CFGMSGDATA[9]) = (0, 0);
( USERCLK2 *> CFGMSGRECEIVED) = (0, 0);
( USERCLK2 *> CFGMSGRECEIVEDASSERTINTA) = (0, 0);
( USERCLK2 *> CFGMSGRECEIVEDASSERTINTB) = (0, 0);
( USERCLK2 *> CFGMSGRECEIVEDASSERTINTC) = (0, 0);
( USERCLK2 *> CFGMSGRECEIVEDASSERTINTD) = (0, 0);
( USERCLK2 *> CFGMSGRECEIVEDDEASSERTINTA) = (0, 0);
( USERCLK2 *> CFGMSGRECEIVEDDEASSERTINTB) = (0, 0);
( USERCLK2 *> CFGMSGRECEIVEDDEASSERTINTC) = (0, 0);
( USERCLK2 *> CFGMSGRECEIVEDDEASSERTINTD) = (0, 0);
( USERCLK2 *> CFGMSGRECEIVEDERRCOR) = (0, 0);
( USERCLK2 *> CFGMSGRECEIVEDERRFATAL) = (0, 0);
( USERCLK2 *> CFGMSGRECEIVEDERRNONFATAL) = (0, 0);
( USERCLK2 *> CFGMSGRECEIVEDPMASNAK) = (0, 0);
( USERCLK2 *> CFGMSGRECEIVEDPMETO) = (0, 0);
( USERCLK2 *> CFGMSGRECEIVEDPMETOACK) = (0, 0);
( USERCLK2 *> CFGMSGRECEIVEDPMPME) = (0, 0);
( USERCLK2 *> CFGMSGRECEIVEDSETSLOTPOWERLIMIT) = (0, 0);
( USERCLK2 *> CFGMSGRECEIVEDUNLOCK) = (0, 0);
( USERCLK2 *> CFGPCIELINKSTATE[0]) = (0, 0);
( USERCLK2 *> CFGPCIELINKSTATE[1]) = (0, 0);
( USERCLK2 *> CFGPCIELINKSTATE[2]) = (0, 0);
( USERCLK2 *> CFGPMCSRPMEEN) = (0, 0);
( USERCLK2 *> CFGPMCSRPMESTATUS) = (0, 0);
( USERCLK2 *> CFGPMCSRPOWERSTATE[0]) = (0, 0);
( USERCLK2 *> CFGPMCSRPOWERSTATE[1]) = (0, 0);
( USERCLK2 *> CFGPMRCVASREQL1N) = (0, 0);
( USERCLK2 *> CFGPMRCVENTERL1N) = (0, 0);
( USERCLK2 *> CFGPMRCVENTERL23N) = (0, 0);
( USERCLK2 *> CFGPMRCVREQACKN) = (0, 0);
( USERCLK2 *> CFGROOTCONTROLPMEINTEN) = (0, 0);
( USERCLK2 *> CFGROOTCONTROLSYSERRCORRERREN) = (0, 0);
( USERCLK2 *> CFGROOTCONTROLSYSERRFATALERREN) = (0, 0);
( USERCLK2 *> CFGROOTCONTROLSYSERRNONFATALERREN) = (0, 0);
( USERCLK2 *> CFGSLOTCONTROLELECTROMECHILCTLPULSE) = (0, 0);
( USERCLK2 *> CFGTRANSACTION) = (0, 0);
( USERCLK2 *> CFGTRANSACTIONADDR[0]) = (0, 0);
( USERCLK2 *> CFGTRANSACTIONADDR[1]) = (0, 0);
( USERCLK2 *> CFGTRANSACTIONADDR[2]) = (0, 0);
( USERCLK2 *> CFGTRANSACTIONADDR[3]) = (0, 0);
( USERCLK2 *> CFGTRANSACTIONADDR[4]) = (0, 0);
( USERCLK2 *> CFGTRANSACTIONADDR[5]) = (0, 0);
( USERCLK2 *> CFGTRANSACTIONADDR[6]) = (0, 0);
( USERCLK2 *> CFGTRANSACTIONTYPE) = (0, 0);
( USERCLK2 *> CFGVCTCVCMAP[0]) = (0, 0);
( USERCLK2 *> CFGVCTCVCMAP[1]) = (0, 0);
( USERCLK2 *> CFGVCTCVCMAP[2]) = (0, 0);
( USERCLK2 *> CFGVCTCVCMAP[3]) = (0, 0);
( USERCLK2 *> CFGVCTCVCMAP[4]) = (0, 0);
( USERCLK2 *> CFGVCTCVCMAP[5]) = (0, 0);
( USERCLK2 *> CFGVCTCVCMAP[6]) = (0, 0);
( USERCLK2 *> DBGSCLRA) = (0, 0);
( USERCLK2 *> DBGSCLRB) = (0, 0);
( USERCLK2 *> DBGSCLRC) = (0, 0);
( USERCLK2 *> DBGSCLRD) = (0, 0);
( USERCLK2 *> DBGSCLRE) = (0, 0);
( USERCLK2 *> DBGSCLRF) = (0, 0);
( USERCLK2 *> DBGSCLRG) = (0, 0);
( USERCLK2 *> DBGSCLRH) = (0, 0);
( USERCLK2 *> DBGSCLRI) = (0, 0);
( USERCLK2 *> DBGSCLRJ) = (0, 0);
( USERCLK2 *> DBGSCLRK) = (0, 0);
( USERCLK2 *> DBGVECA[0]) = (0, 0);
( USERCLK2 *> DBGVECA[10]) = (0, 0);
( USERCLK2 *> DBGVECA[11]) = (0, 0);
( USERCLK2 *> DBGVECA[12]) = (0, 0);
( USERCLK2 *> DBGVECA[13]) = (0, 0);
( USERCLK2 *> DBGVECA[14]) = (0, 0);
( USERCLK2 *> DBGVECA[15]) = (0, 0);
( USERCLK2 *> DBGVECA[16]) = (0, 0);
( USERCLK2 *> DBGVECA[17]) = (0, 0);
( USERCLK2 *> DBGVECA[18]) = (0, 0);
( USERCLK2 *> DBGVECA[19]) = (0, 0);
( USERCLK2 *> DBGVECA[1]) = (0, 0);
( USERCLK2 *> DBGVECA[20]) = (0, 0);
( USERCLK2 *> DBGVECA[21]) = (0, 0);
( USERCLK2 *> DBGVECA[22]) = (0, 0);
( USERCLK2 *> DBGVECA[23]) = (0, 0);
( USERCLK2 *> DBGVECA[24]) = (0, 0);
( USERCLK2 *> DBGVECA[25]) = (0, 0);
( USERCLK2 *> DBGVECA[26]) = (0, 0);
( USERCLK2 *> DBGVECA[27]) = (0, 0);
( USERCLK2 *> DBGVECA[28]) = (0, 0);
( USERCLK2 *> DBGVECA[29]) = (0, 0);
( USERCLK2 *> DBGVECA[2]) = (0, 0);
( USERCLK2 *> DBGVECA[30]) = (0, 0);
( USERCLK2 *> DBGVECA[31]) = (0, 0);
( USERCLK2 *> DBGVECA[32]) = (0, 0);
( USERCLK2 *> DBGVECA[33]) = (0, 0);
( USERCLK2 *> DBGVECA[34]) = (0, 0);
( USERCLK2 *> DBGVECA[35]) = (0, 0);
( USERCLK2 *> DBGVECA[36]) = (0, 0);
( USERCLK2 *> DBGVECA[37]) = (0, 0);
( USERCLK2 *> DBGVECA[38]) = (0, 0);
( USERCLK2 *> DBGVECA[39]) = (0, 0);
( USERCLK2 *> DBGVECA[3]) = (0, 0);
( USERCLK2 *> DBGVECA[40]) = (0, 0);
( USERCLK2 *> DBGVECA[41]) = (0, 0);
( USERCLK2 *> DBGVECA[42]) = (0, 0);
( USERCLK2 *> DBGVECA[43]) = (0, 0);
( USERCLK2 *> DBGVECA[44]) = (0, 0);
( USERCLK2 *> DBGVECA[45]) = (0, 0);
( USERCLK2 *> DBGVECA[46]) = (0, 0);
( USERCLK2 *> DBGVECA[47]) = (0, 0);
( USERCLK2 *> DBGVECA[48]) = (0, 0);
( USERCLK2 *> DBGVECA[49]) = (0, 0);
( USERCLK2 *> DBGVECA[4]) = (0, 0);
( USERCLK2 *> DBGVECA[50]) = (0, 0);
( USERCLK2 *> DBGVECA[51]) = (0, 0);
( USERCLK2 *> DBGVECA[52]) = (0, 0);
( USERCLK2 *> DBGVECA[53]) = (0, 0);
( USERCLK2 *> DBGVECA[54]) = (0, 0);
( USERCLK2 *> DBGVECA[55]) = (0, 0);
( USERCLK2 *> DBGVECA[56]) = (0, 0);
( USERCLK2 *> DBGVECA[57]) = (0, 0);
( USERCLK2 *> DBGVECA[58]) = (0, 0);
( USERCLK2 *> DBGVECA[59]) = (0, 0);
( USERCLK2 *> DBGVECA[5]) = (0, 0);
( USERCLK2 *> DBGVECA[60]) = (0, 0);
( USERCLK2 *> DBGVECA[61]) = (0, 0);
( USERCLK2 *> DBGVECA[62]) = (0, 0);
( USERCLK2 *> DBGVECA[63]) = (0, 0);
( USERCLK2 *> DBGVECA[6]) = (0, 0);
( USERCLK2 *> DBGVECA[7]) = (0, 0);
( USERCLK2 *> DBGVECA[8]) = (0, 0);
( USERCLK2 *> DBGVECA[9]) = (0, 0);
( USERCLK2 *> DBGVECB[0]) = (0, 0);
( USERCLK2 *> DBGVECB[10]) = (0, 0);
( USERCLK2 *> DBGVECB[11]) = (0, 0);
( USERCLK2 *> DBGVECB[12]) = (0, 0);
( USERCLK2 *> DBGVECB[13]) = (0, 0);
( USERCLK2 *> DBGVECB[14]) = (0, 0);
( USERCLK2 *> DBGVECB[15]) = (0, 0);
( USERCLK2 *> DBGVECB[16]) = (0, 0);
( USERCLK2 *> DBGVECB[17]) = (0, 0);
( USERCLK2 *> DBGVECB[18]) = (0, 0);
( USERCLK2 *> DBGVECB[19]) = (0, 0);
( USERCLK2 *> DBGVECB[1]) = (0, 0);
( USERCLK2 *> DBGVECB[20]) = (0, 0);
( USERCLK2 *> DBGVECB[21]) = (0, 0);
( USERCLK2 *> DBGVECB[22]) = (0, 0);
( USERCLK2 *> DBGVECB[23]) = (0, 0);
( USERCLK2 *> DBGVECB[24]) = (0, 0);
( USERCLK2 *> DBGVECB[25]) = (0, 0);
( USERCLK2 *> DBGVECB[26]) = (0, 0);
( USERCLK2 *> DBGVECB[27]) = (0, 0);
( USERCLK2 *> DBGVECB[28]) = (0, 0);
( USERCLK2 *> DBGVECB[29]) = (0, 0);
( USERCLK2 *> DBGVECB[2]) = (0, 0);
( USERCLK2 *> DBGVECB[30]) = (0, 0);
( USERCLK2 *> DBGVECB[31]) = (0, 0);
( USERCLK2 *> DBGVECB[32]) = (0, 0);
( USERCLK2 *> DBGVECB[33]) = (0, 0);
( USERCLK2 *> DBGVECB[34]) = (0, 0);
( USERCLK2 *> DBGVECB[35]) = (0, 0);
( USERCLK2 *> DBGVECB[36]) = (0, 0);
( USERCLK2 *> DBGVECB[37]) = (0, 0);
( USERCLK2 *> DBGVECB[38]) = (0, 0);
( USERCLK2 *> DBGVECB[39]) = (0, 0);
( USERCLK2 *> DBGVECB[3]) = (0, 0);
( USERCLK2 *> DBGVECB[40]) = (0, 0);
( USERCLK2 *> DBGVECB[41]) = (0, 0);
( USERCLK2 *> DBGVECB[42]) = (0, 0);
( USERCLK2 *> DBGVECB[43]) = (0, 0);
( USERCLK2 *> DBGVECB[44]) = (0, 0);
( USERCLK2 *> DBGVECB[45]) = (0, 0);
( USERCLK2 *> DBGVECB[46]) = (0, 0);
( USERCLK2 *> DBGVECB[47]) = (0, 0);
( USERCLK2 *> DBGVECB[48]) = (0, 0);
( USERCLK2 *> DBGVECB[49]) = (0, 0);
( USERCLK2 *> DBGVECB[4]) = (0, 0);
( USERCLK2 *> DBGVECB[50]) = (0, 0);
( USERCLK2 *> DBGVECB[51]) = (0, 0);
( USERCLK2 *> DBGVECB[52]) = (0, 0);
( USERCLK2 *> DBGVECB[53]) = (0, 0);
( USERCLK2 *> DBGVECB[54]) = (0, 0);
( USERCLK2 *> DBGVECB[55]) = (0, 0);
( USERCLK2 *> DBGVECB[56]) = (0, 0);
( USERCLK2 *> DBGVECB[57]) = (0, 0);
( USERCLK2 *> DBGVECB[58]) = (0, 0);
( USERCLK2 *> DBGVECB[59]) = (0, 0);
( USERCLK2 *> DBGVECB[5]) = (0, 0);
( USERCLK2 *> DBGVECB[60]) = (0, 0);
( USERCLK2 *> DBGVECB[61]) = (0, 0);
( USERCLK2 *> DBGVECB[62]) = (0, 0);
( USERCLK2 *> DBGVECB[63]) = (0, 0);
( USERCLK2 *> DBGVECB[6]) = (0, 0);
( USERCLK2 *> DBGVECB[7]) = (0, 0);
( USERCLK2 *> DBGVECB[8]) = (0, 0);
( USERCLK2 *> DBGVECB[9]) = (0, 0);
( USERCLK2 *> DBGVECC[0]) = (0, 0);
( USERCLK2 *> DBGVECC[10]) = (0, 0);
( USERCLK2 *> DBGVECC[11]) = (0, 0);
( USERCLK2 *> DBGVECC[1]) = (0, 0);
( USERCLK2 *> DBGVECC[2]) = (0, 0);
( USERCLK2 *> DBGVECC[3]) = (0, 0);
( USERCLK2 *> DBGVECC[4]) = (0, 0);
( USERCLK2 *> DBGVECC[5]) = (0, 0);
( USERCLK2 *> DBGVECC[6]) = (0, 0);
( USERCLK2 *> DBGVECC[7]) = (0, 0);
( USERCLK2 *> DBGVECC[8]) = (0, 0);
( USERCLK2 *> DBGVECC[9]) = (0, 0);
( USERCLK2 *> LL2BADDLLPERR) = (0, 0);
( USERCLK2 *> LL2BADTLPERR) = (0, 0);
( USERCLK2 *> LL2LINKSTATUS[0]) = (0, 0);
( USERCLK2 *> LL2LINKSTATUS[1]) = (0, 0);
( USERCLK2 *> LL2LINKSTATUS[2]) = (0, 0);
( USERCLK2 *> LL2LINKSTATUS[3]) = (0, 0);
( USERCLK2 *> LL2LINKSTATUS[4]) = (0, 0);
( USERCLK2 *> LL2PROTOCOLERR) = (0, 0);
( USERCLK2 *> LL2RECEIVERERR) = (0, 0);
( USERCLK2 *> LL2REPLAYROERR) = (0, 0);
( USERCLK2 *> LL2REPLAYTOERR) = (0, 0);
( USERCLK2 *> LL2SUSPENDOK) = (0, 0);
( USERCLK2 *> LL2TFCINIT1SEQ) = (0, 0);
( USERCLK2 *> LL2TFCINIT2SEQ) = (0, 0);
( USERCLK2 *> LL2TXIDLE) = (0, 0);
( USERCLK2 *> PL2L0REQ) = (0, 0);
( USERCLK2 *> PL2LINKUP) = (0, 0);
( USERCLK2 *> PL2RECEIVERERR) = (0, 0);
( USERCLK2 *> PL2RECOVERY) = (0, 0);
( USERCLK2 *> PL2RXELECIDLE) = (0, 0);
( USERCLK2 *> PL2RXPMSTATE[0]) = (0, 0);
( USERCLK2 *> PL2RXPMSTATE[1]) = (0, 0);
( USERCLK2 *> PL2SUSPENDOK) = (0, 0);
( USERCLK2 *> RECEIVEDFUNCLVLRSTN) = (0, 0);
( USERCLK2 *> TL2ASPMSUSPENDCREDITCHECKOK) = (0, 0);
( USERCLK2 *> TL2ASPMSUSPENDREQ) = (0, 0);
( USERCLK2 *> TL2ERRFCPE) = (0, 0);
( USERCLK2 *> TL2ERRHDR[0]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[10]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[11]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[12]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[13]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[14]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[15]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[16]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[17]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[18]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[19]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[1]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[20]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[21]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[22]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[23]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[24]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[25]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[26]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[27]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[28]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[29]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[2]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[30]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[31]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[32]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[33]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[34]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[35]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[36]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[37]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[38]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[39]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[3]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[40]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[41]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[42]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[43]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[44]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[45]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[46]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[47]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[48]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[49]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[4]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[50]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[51]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[52]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[53]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[54]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[55]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[56]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[57]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[58]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[59]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[5]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[60]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[61]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[62]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[63]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[6]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[7]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[8]) = (0, 0);
( USERCLK2 *> TL2ERRHDR[9]) = (0, 0);
( USERCLK2 *> TL2ERRMALFORMED) = (0, 0);
( USERCLK2 *> TL2ERRRXOVERFLOW) = (0, 0);
( USERCLK2 *> TL2PPMSUSPENDOK) = (0, 0);
( USERCLK2 *> TRNFCCPLD[0]) = (0, 0);
( USERCLK2 *> TRNFCCPLD[10]) = (0, 0);
( USERCLK2 *> TRNFCCPLD[11]) = (0, 0);
( USERCLK2 *> TRNFCCPLD[1]) = (0, 0);
( USERCLK2 *> TRNFCCPLD[2]) = (0, 0);
( USERCLK2 *> TRNFCCPLD[3]) = (0, 0);
( USERCLK2 *> TRNFCCPLD[4]) = (0, 0);
( USERCLK2 *> TRNFCCPLD[5]) = (0, 0);
( USERCLK2 *> TRNFCCPLD[6]) = (0, 0);
( USERCLK2 *> TRNFCCPLD[7]) = (0, 0);
( USERCLK2 *> TRNFCCPLD[8]) = (0, 0);
( USERCLK2 *> TRNFCCPLD[9]) = (0, 0);
( USERCLK2 *> TRNFCCPLH[0]) = (0, 0);
( USERCLK2 *> TRNFCCPLH[1]) = (0, 0);
( USERCLK2 *> TRNFCCPLH[2]) = (0, 0);
( USERCLK2 *> TRNFCCPLH[3]) = (0, 0);
( USERCLK2 *> TRNFCCPLH[4]) = (0, 0);
( USERCLK2 *> TRNFCCPLH[5]) = (0, 0);
( USERCLK2 *> TRNFCCPLH[6]) = (0, 0);
( USERCLK2 *> TRNFCCPLH[7]) = (0, 0);
( USERCLK2 *> TRNFCNPD[0]) = (0, 0);
( USERCLK2 *> TRNFCNPD[10]) = (0, 0);
( USERCLK2 *> TRNFCNPD[11]) = (0, 0);
( USERCLK2 *> TRNFCNPD[1]) = (0, 0);
( USERCLK2 *> TRNFCNPD[2]) = (0, 0);
( USERCLK2 *> TRNFCNPD[3]) = (0, 0);
( USERCLK2 *> TRNFCNPD[4]) = (0, 0);
( USERCLK2 *> TRNFCNPD[5]) = (0, 0);
( USERCLK2 *> TRNFCNPD[6]) = (0, 0);
( USERCLK2 *> TRNFCNPD[7]) = (0, 0);
( USERCLK2 *> TRNFCNPD[8]) = (0, 0);
( USERCLK2 *> TRNFCNPD[9]) = (0, 0);
( USERCLK2 *> TRNFCNPH[0]) = (0, 0);
( USERCLK2 *> TRNFCNPH[1]) = (0, 0);
( USERCLK2 *> TRNFCNPH[2]) = (0, 0);
( USERCLK2 *> TRNFCNPH[3]) = (0, 0);
( USERCLK2 *> TRNFCNPH[4]) = (0, 0);
( USERCLK2 *> TRNFCNPH[5]) = (0, 0);
( USERCLK2 *> TRNFCNPH[6]) = (0, 0);
( USERCLK2 *> TRNFCNPH[7]) = (0, 0);
( USERCLK2 *> TRNFCPD[0]) = (0, 0);
( USERCLK2 *> TRNFCPD[10]) = (0, 0);
( USERCLK2 *> TRNFCPD[11]) = (0, 0);
( USERCLK2 *> TRNFCPD[1]) = (0, 0);
( USERCLK2 *> TRNFCPD[2]) = (0, 0);
( USERCLK2 *> TRNFCPD[3]) = (0, 0);
( USERCLK2 *> TRNFCPD[4]) = (0, 0);
( USERCLK2 *> TRNFCPD[5]) = (0, 0);
( USERCLK2 *> TRNFCPD[6]) = (0, 0);
( USERCLK2 *> TRNFCPD[7]) = (0, 0);
( USERCLK2 *> TRNFCPD[8]) = (0, 0);
( USERCLK2 *> TRNFCPD[9]) = (0, 0);
( USERCLK2 *> TRNFCPH[0]) = (0, 0);
( USERCLK2 *> TRNFCPH[1]) = (0, 0);
( USERCLK2 *> TRNFCPH[2]) = (0, 0);
( USERCLK2 *> TRNFCPH[3]) = (0, 0);
( USERCLK2 *> TRNFCPH[4]) = (0, 0);
( USERCLK2 *> TRNFCPH[5]) = (0, 0);
( USERCLK2 *> TRNFCPH[6]) = (0, 0);
( USERCLK2 *> TRNFCPH[7]) = (0, 0);
( USERCLK2 *> TRNLNKUP) = (0, 0);
( USERCLK2 *> TRNRBARHIT[0]) = (0, 0);
( USERCLK2 *> TRNRBARHIT[1]) = (0, 0);
( USERCLK2 *> TRNRBARHIT[2]) = (0, 0);
( USERCLK2 *> TRNRBARHIT[3]) = (0, 0);
( USERCLK2 *> TRNRBARHIT[4]) = (0, 0);
( USERCLK2 *> TRNRBARHIT[5]) = (0, 0);
( USERCLK2 *> TRNRBARHIT[6]) = (0, 0);
( USERCLK2 *> TRNRBARHIT[7]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[0]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[10]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[11]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[12]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[13]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[14]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[15]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[16]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[17]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[18]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[19]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[1]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[20]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[21]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[22]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[23]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[24]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[25]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[26]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[27]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[28]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[29]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[2]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[30]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[31]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[32]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[33]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[34]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[35]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[36]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[37]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[38]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[39]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[3]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[40]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[41]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[42]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[43]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[44]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[45]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[46]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[47]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[48]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[49]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[4]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[50]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[51]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[52]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[53]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[54]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[55]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[56]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[57]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[58]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[59]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[5]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[60]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[61]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[62]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[63]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[6]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[7]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[8]) = (0, 0);
( USERCLK2 *> TRNRDLLPDATA[9]) = (0, 0);
( USERCLK2 *> TRNRDLLPSRCRDY[0]) = (0, 0);
( USERCLK2 *> TRNRDLLPSRCRDY[1]) = (0, 0);
( USERCLK2 *> TRNRD[0]) = (0, 0);
( USERCLK2 *> TRNRD[100]) = (0, 0);
( USERCLK2 *> TRNRD[101]) = (0, 0);
( USERCLK2 *> TRNRD[102]) = (0, 0);
( USERCLK2 *> TRNRD[103]) = (0, 0);
( USERCLK2 *> TRNRD[104]) = (0, 0);
( USERCLK2 *> TRNRD[105]) = (0, 0);
( USERCLK2 *> TRNRD[106]) = (0, 0);
( USERCLK2 *> TRNRD[107]) = (0, 0);
( USERCLK2 *> TRNRD[108]) = (0, 0);
( USERCLK2 *> TRNRD[109]) = (0, 0);
( USERCLK2 *> TRNRD[10]) = (0, 0);
( USERCLK2 *> TRNRD[110]) = (0, 0);
( USERCLK2 *> TRNRD[111]) = (0, 0);
( USERCLK2 *> TRNRD[112]) = (0, 0);
( USERCLK2 *> TRNRD[113]) = (0, 0);
( USERCLK2 *> TRNRD[114]) = (0, 0);
( USERCLK2 *> TRNRD[115]) = (0, 0);
( USERCLK2 *> TRNRD[116]) = (0, 0);
( USERCLK2 *> TRNRD[117]) = (0, 0);
( USERCLK2 *> TRNRD[118]) = (0, 0);
( USERCLK2 *> TRNRD[119]) = (0, 0);
( USERCLK2 *> TRNRD[11]) = (0, 0);
( USERCLK2 *> TRNRD[120]) = (0, 0);
( USERCLK2 *> TRNRD[121]) = (0, 0);
( USERCLK2 *> TRNRD[122]) = (0, 0);
( USERCLK2 *> TRNRD[123]) = (0, 0);
( USERCLK2 *> TRNRD[124]) = (0, 0);
( USERCLK2 *> TRNRD[125]) = (0, 0);
( USERCLK2 *> TRNRD[126]) = (0, 0);
( USERCLK2 *> TRNRD[127]) = (0, 0);
( USERCLK2 *> TRNRD[12]) = (0, 0);
( USERCLK2 *> TRNRD[13]) = (0, 0);
( USERCLK2 *> TRNRD[14]) = (0, 0);
( USERCLK2 *> TRNRD[15]) = (0, 0);
( USERCLK2 *> TRNRD[16]) = (0, 0);
( USERCLK2 *> TRNRD[17]) = (0, 0);
( USERCLK2 *> TRNRD[18]) = (0, 0);
( USERCLK2 *> TRNRD[19]) = (0, 0);
( USERCLK2 *> TRNRD[1]) = (0, 0);
( USERCLK2 *> TRNRD[20]) = (0, 0);
( USERCLK2 *> TRNRD[21]) = (0, 0);
( USERCLK2 *> TRNRD[22]) = (0, 0);
( USERCLK2 *> TRNRD[23]) = (0, 0);
( USERCLK2 *> TRNRD[24]) = (0, 0);
( USERCLK2 *> TRNRD[25]) = (0, 0);
( USERCLK2 *> TRNRD[26]) = (0, 0);
( USERCLK2 *> TRNRD[27]) = (0, 0);
( USERCLK2 *> TRNRD[28]) = (0, 0);
( USERCLK2 *> TRNRD[29]) = (0, 0);
( USERCLK2 *> TRNRD[2]) = (0, 0);
( USERCLK2 *> TRNRD[30]) = (0, 0);
( USERCLK2 *> TRNRD[31]) = (0, 0);
( USERCLK2 *> TRNRD[32]) = (0, 0);
( USERCLK2 *> TRNRD[33]) = (0, 0);
( USERCLK2 *> TRNRD[34]) = (0, 0);
( USERCLK2 *> TRNRD[35]) = (0, 0);
( USERCLK2 *> TRNRD[36]) = (0, 0);
( USERCLK2 *> TRNRD[37]) = (0, 0);
( USERCLK2 *> TRNRD[38]) = (0, 0);
( USERCLK2 *> TRNRD[39]) = (0, 0);
( USERCLK2 *> TRNRD[3]) = (0, 0);
( USERCLK2 *> TRNRD[40]) = (0, 0);
( USERCLK2 *> TRNRD[41]) = (0, 0);
( USERCLK2 *> TRNRD[42]) = (0, 0);
( USERCLK2 *> TRNRD[43]) = (0, 0);
( USERCLK2 *> TRNRD[44]) = (0, 0);
( USERCLK2 *> TRNRD[45]) = (0, 0);
( USERCLK2 *> TRNRD[46]) = (0, 0);
( USERCLK2 *> TRNRD[47]) = (0, 0);
( USERCLK2 *> TRNRD[48]) = (0, 0);
( USERCLK2 *> TRNRD[49]) = (0, 0);
( USERCLK2 *> TRNRD[4]) = (0, 0);
( USERCLK2 *> TRNRD[50]) = (0, 0);
( USERCLK2 *> TRNRD[51]) = (0, 0);
( USERCLK2 *> TRNRD[52]) = (0, 0);
( USERCLK2 *> TRNRD[53]) = (0, 0);
( USERCLK2 *> TRNRD[54]) = (0, 0);
( USERCLK2 *> TRNRD[55]) = (0, 0);
( USERCLK2 *> TRNRD[56]) = (0, 0);
( USERCLK2 *> TRNRD[57]) = (0, 0);
( USERCLK2 *> TRNRD[58]) = (0, 0);
( USERCLK2 *> TRNRD[59]) = (0, 0);
( USERCLK2 *> TRNRD[5]) = (0, 0);
( USERCLK2 *> TRNRD[60]) = (0, 0);
( USERCLK2 *> TRNRD[61]) = (0, 0);
( USERCLK2 *> TRNRD[62]) = (0, 0);
( USERCLK2 *> TRNRD[63]) = (0, 0);
( USERCLK2 *> TRNRD[64]) = (0, 0);
( USERCLK2 *> TRNRD[65]) = (0, 0);
( USERCLK2 *> TRNRD[66]) = (0, 0);
( USERCLK2 *> TRNRD[67]) = (0, 0);
( USERCLK2 *> TRNRD[68]) = (0, 0);
( USERCLK2 *> TRNRD[69]) = (0, 0);
( USERCLK2 *> TRNRD[6]) = (0, 0);
( USERCLK2 *> TRNRD[70]) = (0, 0);
( USERCLK2 *> TRNRD[71]) = (0, 0);
( USERCLK2 *> TRNRD[72]) = (0, 0);
( USERCLK2 *> TRNRD[73]) = (0, 0);
( USERCLK2 *> TRNRD[74]) = (0, 0);
( USERCLK2 *> TRNRD[75]) = (0, 0);
( USERCLK2 *> TRNRD[76]) = (0, 0);
( USERCLK2 *> TRNRD[77]) = (0, 0);
( USERCLK2 *> TRNRD[78]) = (0, 0);
( USERCLK2 *> TRNRD[79]) = (0, 0);
( USERCLK2 *> TRNRD[7]) = (0, 0);
( USERCLK2 *> TRNRD[80]) = (0, 0);
( USERCLK2 *> TRNRD[81]) = (0, 0);
( USERCLK2 *> TRNRD[82]) = (0, 0);
( USERCLK2 *> TRNRD[83]) = (0, 0);
( USERCLK2 *> TRNRD[84]) = (0, 0);
( USERCLK2 *> TRNRD[85]) = (0, 0);
( USERCLK2 *> TRNRD[86]) = (0, 0);
( USERCLK2 *> TRNRD[87]) = (0, 0);
( USERCLK2 *> TRNRD[88]) = (0, 0);
( USERCLK2 *> TRNRD[89]) = (0, 0);
( USERCLK2 *> TRNRD[8]) = (0, 0);
( USERCLK2 *> TRNRD[90]) = (0, 0);
( USERCLK2 *> TRNRD[91]) = (0, 0);
( USERCLK2 *> TRNRD[92]) = (0, 0);
( USERCLK2 *> TRNRD[93]) = (0, 0);
( USERCLK2 *> TRNRD[94]) = (0, 0);
( USERCLK2 *> TRNRD[95]) = (0, 0);
( USERCLK2 *> TRNRD[96]) = (0, 0);
( USERCLK2 *> TRNRD[97]) = (0, 0);
( USERCLK2 *> TRNRD[98]) = (0, 0);
( USERCLK2 *> TRNRD[99]) = (0, 0);
( USERCLK2 *> TRNRD[9]) = (0, 0);
( USERCLK2 *> TRNRECRCERR) = (0, 0);
( USERCLK2 *> TRNREOF) = (0, 0);
( USERCLK2 *> TRNRERRFWD) = (0, 0);
( USERCLK2 *> TRNRREM[0]) = (0, 0);
( USERCLK2 *> TRNRREM[1]) = (0, 0);
( USERCLK2 *> TRNRSOF) = (0, 0);
( USERCLK2 *> TRNRSRCDSC) = (0, 0);
( USERCLK2 *> TRNRSRCRDY) = (0, 0);
( USERCLK2 *> TRNTBUFAV[0]) = (0, 0);
( USERCLK2 *> TRNTBUFAV[1]) = (0, 0);
( USERCLK2 *> TRNTBUFAV[2]) = (0, 0);
( USERCLK2 *> TRNTBUFAV[3]) = (0, 0);
( USERCLK2 *> TRNTBUFAV[4]) = (0, 0);
( USERCLK2 *> TRNTBUFAV[5]) = (0, 0);
( USERCLK2 *> TRNTCFGREQ) = (0, 0);
( USERCLK2 *> TRNTDLLPDSTRDY) = (0, 0);
( USERCLK2 *> TRNTDSTRDY[0]) = (0, 0);
( USERCLK2 *> TRNTDSTRDY[1]) = (0, 0);
( USERCLK2 *> TRNTDSTRDY[2]) = (0, 0);
( USERCLK2 *> TRNTDSTRDY[3]) = (0, 0);
( USERCLK2 *> TRNTERRDROP) = (0, 0);
( USERCLK2 *> USERRSTN) = (0, 0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:33:15 11/16/2015
// Design Name:
// Module Name: ControlUnit
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ControlUnit(
input [5:0] Special,
input [5:0] instructionCode,
output reg RegDst,
output reg Branch,
output reg BranchType,
output reg MemtoReg,
output reg [3:0]MemWrite,
output reg ALUSrc,
output reg ALUShiftImm,
output reg RegWrite,
output reg LoadImm,
output reg ZeroEx,
output reg EOP,
output reg [1:0] memReadWidth, // 0:Word 1:Halfword 2:Byte
output reg [3:0] aluOperation
);
always @* begin
case (Special)
'b100000:begin //LB
EOP <= 0;
RegDst <= 0;
Branch <= 0;
BranchType <= 0;
MemtoReg <= 1;
MemWrite <= 0;
ALUSrc <= 1;
ALUShiftImm <= 0;
RegWrite <= 1;
LoadImm <= 0;
ZeroEx <= 0;
aluOperation<= 3;
memReadWidth<= 2;
end
'b100001:begin //LH
EOP <= 0;
RegDst <= 0;
Branch <= 0;
BranchType <= 0;
MemtoReg <= 1;
MemWrite <= 0;
ALUSrc <= 1;
ALUShiftImm <= 0;
RegWrite <= 1;
LoadImm <= 0;
ZeroEx <= 0;
aluOperation<= 3;
memReadWidth<= 1;
end
'b100011:begin //LW
EOP <= 0;
RegDst <= 0;
Branch <= 0;
BranchType <= 0;
MemtoReg <= 1;
MemWrite <= 0;
ALUSrc <= 1;
ALUShiftImm <= 0;
RegWrite <= 1;
LoadImm <= 0;
ZeroEx <= 0;
aluOperation<= 3;
memReadWidth<= 0;
end
'b100111:begin //LWU
EOP <= 0;
RegDst <= 0;
Branch <= 0;
BranchType <= 0;
MemtoReg <= 1;
MemWrite <= 0;
ALUSrc <= 1;
ALUShiftImm <= 0;
RegWrite <= 1;
LoadImm <= 0;
ZeroEx <= 0;
aluOperation<= 3;
memReadWidth<= 0;
end
'b100100:begin //LBU
EOP <= 0;
RegDst <= 0;
Branch <= 0;
BranchType <= 0;
MemtoReg <= 1;
MemWrite <= 0;
ALUSrc <= 1;
ALUShiftImm <= 0;
RegWrite <= 1;
LoadImm <= 0;
ZeroEx <= 0;
aluOperation<= 3;
memReadWidth<= 2;
end
'b100101:begin //LHU
EOP <= 0;
RegDst <= 0;
Branch <= 0;
BranchType <= 0;
MemtoReg <= 1;
MemWrite <= 0;
ALUSrc <= 1;
ALUShiftImm <= 0;
RegWrite <= 1;
LoadImm <= 0;
ZeroEx <= 0;
aluOperation<= 3;
memReadWidth<= 1;
end
'b101000:begin //SB
EOP <= 0;
RegDst <= 0;
Branch <= 0;
BranchType <= 0;
MemtoReg <= 0;
MemWrite <= 4'd1;
ALUSrc <= 1;
ALUShiftImm <= 0;
RegWrite <= 0;
LoadImm <= 0;
ZeroEx <= 0;
aluOperation<= 3;
memReadWidth<= 0;
end
'b101001:begin //SH
EOP <= 0;
RegDst <= 0;
Branch <= 0;
BranchType <= 0;
MemtoReg <= 0;
MemWrite <= 4'b0011;
ALUSrc <= 1;
ALUShiftImm <= 0;
RegWrite <= 0;
LoadImm <= 0;
ZeroEx <= 0;
aluOperation<= 3;
memReadWidth<= 0;
end
'b101011:begin //SW
EOP <= 0;
RegDst <= 0;
Branch <= 0;
BranchType <= 0;
MemtoReg <= 0;
MemWrite <= 4'b1111;
ALUSrc <= 1;
ALUShiftImm <= 0;
RegWrite <= 0;
LoadImm <= 0;
ZeroEx <= 0;
aluOperation<= 3;
memReadWidth<= 0;
end
'b001000:begin //ADDI
EOP <= 0;
RegDst <= 0;
Branch <= 0;
BranchType <= 0;
MemtoReg <= 0;
MemWrite <= 0;
ALUSrc <= 1;
ALUShiftImm <= 0;
RegWrite <= 1;
LoadImm <= 0;
ZeroEx <= 0;
aluOperation<= 3;
memReadWidth<= 0;
end
'b001100:begin //ANDI
EOP <= 0;
RegDst <= 0;
Branch <= 0;
BranchType <= 0;
MemtoReg <= 0;
MemWrite <= 0;
ALUSrc <= 1;
ALUShiftImm <= 0;
RegWrite <= 1;
LoadImm <= 0;
ZeroEx <= 1;
aluOperation<= 5;
memReadWidth<= 0;
end
'b001101:begin //ORI
EOP <= 0;
RegDst <= 0;
Branch <= 0;
BranchType <= 0;
MemtoReg <= 0;
MemWrite <= 0;
ALUSrc <= 1;
ALUShiftImm <= 0;
RegWrite <= 1;
LoadImm <= 0;
ZeroEx <= 1;
aluOperation<= 6;
memReadWidth<= 0;
end
'b001110:begin //XORI
EOP <= 0;
RegDst <= 0;
Branch <= 0;
BranchType <= 0;
MemtoReg <= 0;
MemWrite <= 0;
ALUSrc <= 1;
ALUShiftImm <= 0;
RegWrite <= 1;
LoadImm <= 0;
ZeroEx <= 1;
aluOperation<= 7;
memReadWidth<= 0;
end
'b001010:begin //SLTI
EOP <= 0;
RegDst <= 0;
Branch <= 0;
BranchType <= 0;
MemtoReg <= 0;
MemWrite <= 0;
ALUSrc <= 1;
ALUShiftImm <= 0;
RegWrite <= 1;
LoadImm <= 0;
ZeroEx <= 0;
aluOperation<= 9;
memReadWidth<= 0;
end
'b001111:begin //LUI
EOP <= 0;
RegDst <= 0;
Branch <= 0;
BranchType <= 0;
MemtoReg <= 0;
MemWrite <= 0;
ALUSrc <= 1;
ALUShiftImm <= 0;
RegWrite <= 1;
LoadImm <= 1;
ZeroEx <= 0;
aluOperation<= 0;
memReadWidth<= 0;
end
'b000100:begin //BEQ
EOP <= 0;
RegDst <= 0;
Branch <= 1;
BranchType <= 0;
MemtoReg <= 0;
MemWrite <= 0;
ALUSrc <= 0;
ALUShiftImm <= 0;
RegWrite <= 0;
LoadImm <= 0;
ZeroEx <= 0;
aluOperation<= 4;
memReadWidth<= 0;
end
'b000101:begin //BNE
EOP <= 0;
RegDst <= 0;
Branch <= 1;
BranchType <= 1;
MemtoReg <= 0;
MemWrite <= 0;
ALUSrc <= 0;
ALUShiftImm <= 0;
RegWrite <= 0;
LoadImm <= 0;
ZeroEx <= 0;
aluOperation<= 4;
memReadWidth<= 0;
end
'b111111:begin // End of Program
EOP <= 1;
RegDst <= 0;
Branch <= 0;
BranchType <= 0;
MemtoReg <= 0;
MemWrite <= 0;
ALUSrc <= 1;
ALUShiftImm <= 0;
RegWrite <= 0;
LoadImm <= 0;
ZeroEx <= 1;
aluOperation<= 6;
memReadWidth<= 0;
end
default:begin //Tipo R
EOP <= 0;
RegDst <= 1;
Branch <= 0;
BranchType <= 0;
MemtoReg <= 0;
MemWrite <= 0;
ALUSrc <= 0;
ALUShiftImm <=((instructionCode==0) ||(instructionCode==2)||(instructionCode==3));
RegWrite <= 1;
LoadImm <= 0;
ZeroEx <= 0;
memReadWidth<= 0;
case(instructionCode)
6'b000000: aluOperation <= 0; //SLL
6'b000010: aluOperation <= 1; //SRL
6'b000011: aluOperation <= 2; //SRA
6'b000110: aluOperation <= 1; //SRLV
6'b000111: aluOperation <= 2; //SRAV
6'b000100: aluOperation <= 0; //SLLV
6'b100000: aluOperation <= 3; //ADD
6'b100010: aluOperation <= 4; //SUB
6'b100100: aluOperation <= 5; //AND
6'b100101: aluOperation <= 6; //OR
6'b100110: aluOperation <= 7; //XOR
6'b100111: aluOperation <= 8; //NOR
6'b101010: aluOperation <= 9; //SLT
default: aluOperation <= 'hF;
endcase
end
endcase;
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.7
// \ \ Application : MIG
// / / Filename : sim_tb_top.v
// /___/ /\ Date Last Modified : $Date: 2011/01/06 11:13:56 $
// \ \ / \ Date Created : Mon Jun 23 2008
// \___\/\___\
//
// Device : Virtex-6
// Design Name : DDR3 SDRAM
// Purpose :
// Top-level testbench for testing DDR3.
// Instantiates:
// 1. IP_TOP (top-level representing FPGA, contains core,
// clocking, built-in testbench/memory checker and other
// support structures)
// 2. DDR3 Memory
// 3. Miscellaneous clock generation and reset logic
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ps/100fs
module sim_tb_top;
parameter REFCLK_FREQ = 200;
// # = 200 when design frequency < 533 MHz,
// = 300 when design frequency >= 533 MHz.
parameter SIM_BYPASS_INIT_CAL = "FAST";
// # = "OFF" - Complete memory init &
// calibration sequence
// # = "SKIP" - Skip memory init &
// calibration sequence
// # = "FAST" - Skip memory init & use
// abbreviated calib sequence
parameter RST_ACT_LOW = 1;
// =1 for active low reset,
// =0 for active high.
parameter IODELAY_GRP = "IODELAY_MIG";
//to phy_top
parameter nCK_PER_CLK = 2;
// # of memory CKs per fabric clock.
// # = 2, 1.
parameter nCS_PER_RANK = 1;
// # of unique CS outputs per Rank for
// phy.
parameter DQS_CNT_WIDTH = 3;
// # = ceil(log2(DQS_WIDTH)).
parameter RANK_WIDTH = 1;
// # = ceil(log2(RANKS)).
parameter BANK_WIDTH = 3;
// # of memory Bank Address bits.
parameter CK_WIDTH = 1;
// # of CK/CK# outputs to memory.
parameter CKE_WIDTH = 1;
// # of CKE outputs to memory.
parameter COL_WIDTH = 10;
// # of memory Column Address bits.
parameter CS_WIDTH = 1;
// # of unique CS outputs to memory.
parameter DM_WIDTH = 8;
// # of Data Mask bits.
parameter DQ_WIDTH = 64;
// # of Data (DQ) bits.
parameter DQS_WIDTH = 8;
// # of DQS/DQS# bits.
parameter ROW_WIDTH = 13;
// # of memory Row Address bits.
parameter BURST_MODE = "8";
// Burst Length (Mode Register 0).
// # = "8", "4", "OTF".
parameter INPUT_CLK_TYPE = "DIFFERENTIAL";
// input clock type DIFFERENTIAL or SINGLE_ENDED
parameter BM_CNT_WIDTH = 2;
// # = ceil(log2(nBANK_MACHS)).
parameter ADDR_CMD_MODE = "1T" ;
// # = "2T", "1T".
parameter ORDERING = "STRICT";
// # = "NORM", "STRICT", "RELAXED".
parameter RTT_NOM = "60";
// RTT_NOM (ODT) (Mode Register 1).
// # = "DISABLED" - RTT_NOM disabled,
// = "120" - RZQ/2,
// = "60" - RZQ/4,
// = "40" - RZQ/6.
parameter RTT_WR = "OFF";
// RTT_WR (ODT) (Mode Register 2).
// # = "OFF" - Dynamic ODT off,
// = "120" - RZQ/2,
// = "60" - RZQ/4,
parameter OUTPUT_DRV = "HIGH";
// Output Driver Impedance Control (Mode Register 1).
// # = "HIGH" - RZQ/7,
// = "LOW" - RZQ/6.
parameter REG_CTRL = "OFF";
// # = "ON" - RDIMMs,
// = "OFF" - Components, SODIMMs, UDIMMs.
parameter CLKFBOUT_MULT_F = 6;
// write PLL VCO multiplier.
parameter DIVCLK_DIVIDE = 2;
// write PLL VCO divisor.
parameter CLKOUT_DIVIDE = 3;
// VCO output divisor for fast (memory) clocks.
parameter tCK = 2500;
// memory tCK paramter.
// # = Clock Period.
parameter DEBUG_PORT = "OFF";
// # = "ON" Enable debug signals/controls.
// = "OFF" Disable debug signals/controls.
parameter tPRDI = 1_000_000;
// memory tPRDI paramter.
parameter tREFI = 7800000;
// memory tREFI paramter.
parameter tZQI = 128_000_000;
// memory tZQI paramter.
parameter ADDR_WIDTH = 27;
// # = RANK_WIDTH + BANK_WIDTH
// + ROW_WIDTH + COL_WIDTH;
parameter STARVE_LIMIT = 2;
// # = 2,3,4.
parameter TCQ = 100;
parameter ECC_TEST = "OFF";
parameter DATA_WIDTH = 64;
parameter PAYLOAD_WIDTH = (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH;
//***********************************************************************//
// Traffic Gen related parameters
//***********************************************************************//
parameter EYE_TEST = "FALSE";
// set EYE_TEST = "TRUE" to probe memory
// signals. Traffic Generator will only
// write to one single location and no
// read transactions will be generated.
parameter DATA_PATTERN = "DGEN_ALL";
// "DGEN_HAMMER", "DGEN_WALKING1",
// "DGEN_WALKING0","DGEN_ADDR","
// "DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter CMD_PATTERN = "CGEN_ALL";
// "CGEN_RPBS","CGEN_FIXED","CGEN_BRAM",
// "CGEN_SEQUENTIAL", "CGEN_ALL"
parameter BEGIN_ADDRESS = 32'h00000000;
parameter PRBS_SADDR_MASK_POS = 32'h00000000;
parameter END_ADDRESS = 32'h000003ff;
parameter PRBS_EADDR_MASK_POS = 32'hfffffc00;
parameter SEL_VICTIM_LINE = 11;
//**************************************************************************//
// Local parameters Declarations
//**************************************************************************//
localparam real TPROP_DQS = 0.00; // Delay for DQS signal during Write Operation
localparam real TPROP_DQS_RD = 0.00; // Delay for DQS signal during Read Operation
localparam real TPROP_PCB_CTRL = 0.00; // Delay for Address and Ctrl signals
localparam real TPROP_PCB_DATA = 0.00; // Delay for data signal during Write operation
localparam real TPROP_PCB_DATA_RD = 0.00; // Delay for data signal during Read operation
localparam MEMORY_WIDTH = 16;
localparam NUM_COMP = DQ_WIDTH/MEMORY_WIDTH;
localparam real CLK_PERIOD = tCK;
localparam real REFCLK_PERIOD = (1000000.0/(2*REFCLK_FREQ));
localparam DRAM_DEVICE = "SODIMM";
// DRAM_TYPE: "UDIMM", "RDIMM", "COMPS"
// VT delay change options/settings
localparam VT_ENABLE = "OFF";
// Enable VT delay var's
localparam VT_RATE = CLK_PERIOD/500;
// Size of each VT step
localparam VT_UPDATE_INTERVAL = CLK_PERIOD*50;
// Update interval
localparam VT_MAX = CLK_PERIOD/40;
// Maximum VT shift
function integer STR_TO_INT;
input [7:0] in;
begin
if(in == "8")
STR_TO_INT = 8;
else if(in == "4")
STR_TO_INT = 4;
else
STR_TO_INT = 0;
end
endfunction
localparam APP_DATA_WIDTH = PAYLOAD_WIDTH * 4;
localparam APP_MASK_WIDTH = APP_DATA_WIDTH / 8;
localparam BURST_LENGTH = STR_TO_INT(BURST_MODE);
//**************************************************************************//
// Wire Declarations
//**************************************************************************//
reg sys_clk;
reg clk_ref;
reg sys_rst_n;
wire sys_clk_p;
wire sys_clk_n;
wire clk_ref_p;
wire clk_ref_n;
reg [DM_WIDTH-1:0] ddr3_dm_sdram_tmp;
wire sys_rst;
wire error;
wire phy_init_done;
wire ddr3_parity;
wire ddr3_reset_n;
wire sda;
wire scl;
wire [DQ_WIDTH-1:0] ddr3_dq_fpga;
wire [ROW_WIDTH-1:0] ddr3_addr_fpga;
wire [BANK_WIDTH-1:0] ddr3_ba_fpga;
wire ddr3_ras_n_fpga;
wire ddr3_cas_n_fpga;
wire ddr3_we_n_fpga;
wire [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_cs_n_fpga;
wire [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_odt_fpga;
wire [CKE_WIDTH-1:0] ddr3_cke_fpga;
wire [DM_WIDTH-1:0] ddr3_dm_fpga;
wire [DQS_WIDTH-1:0] ddr3_dqs_p_fpga;
wire [DQS_WIDTH-1:0] ddr3_dqs_n_fpga;
wire [CK_WIDTH-1:0] ddr3_ck_p_fpga;
wire [CK_WIDTH-1:0] ddr3_ck_n_fpga;
wire [DQ_WIDTH-1:0] ddr3_dq_sdram;
reg [ROW_WIDTH-1:0] ddr3_addr_sdram;
reg [BANK_WIDTH-1:0] ddr3_ba_sdram;
reg ddr3_ras_n_sdram;
reg ddr3_cas_n_sdram;
reg ddr3_we_n_sdram;
reg [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_cs_n_sdram;
reg [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_odt_sdram;
reg [CKE_WIDTH-1:0] ddr3_cke_sdram;
wire [DM_WIDTH-1:0] ddr3_dm_sdram;
wire [DQS_WIDTH-1:0] ddr3_dqs_p_sdram;
wire [DQS_WIDTH-1:0] ddr3_dqs_n_sdram;
reg [CK_WIDTH-1:0] ddr3_ck_p_sdram;
reg [CK_WIDTH-1:0] ddr3_ck_n_sdram;
reg [ROW_WIDTH-1:0] ddr3_addr_r;
reg [BANK_WIDTH-1:0] ddr3_ba_r;
reg ddr3_ras_n_r;
reg ddr3_cas_n_r;
reg ddr3_we_n_r;
reg [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_cs_n_r;
reg [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_odt_r;
reg [CKE_WIDTH-1:0] ddr3_cke_r;
wire clk;
wire rst;
wire app_en;
wire [2:0] app_cmd;
wire [ADDR_WIDTH-1:0] app_addr;
wire app_wdf_wren;
wire [APP_DATA_WIDTH-1:0] app_wdf_data;
wire [APP_MASK_WIDTH-1:0] app_wdf_mask;
wire app_wdf_end;
wire [6:0] tg_wr_fifo_counts;
wire [6:0] tg_rd_fifo_counts;
wire tg_rd_en;
wire [APP_DATA_WIDTH-1:0] app_rd_data;
wire [31:0] tpt_hdata;
wire t_gen_run_traffic;
wire [31:0] t_gen_start_addr;
wire [31:0] t_gen_end_addr;
wire [31:0] t_gen_cmd_seed;
wire [31:0] t_gen_data_seed;
wire t_gen_load_seed;
wire [2:0] t_gen_addr_mode;
wire [3:0] t_gen_instr_mode;
wire [1:0] t_gen_bl_mode;
wire [3:0] t_gen_data_mode;
wire t_gen_mode_load;
wire [5:0] t_gen_fixed_bl;
wire [2:0] t_gen_fixed_instr;
wire [31:0] t_gen_fixed_addr;
wire manual_clear_error;
wire modify_enable_sel;
wire [2:0] addr_mode_manual_sel;
wire [2:0] data_mode_manual_sel;
//**************************************************************************//
// Clock generation and reset
//**************************************************************************//
initial begin
sys_clk = 1'b0;
clk_ref = 1'b1;
sys_rst_n = 1'b0;
#120000
sys_rst_n = 1'b1;
end
assign sys_rst = RST_ACT_LOW ? sys_rst_n : ~sys_rst_n;
// Generate system clock = twice rate of CLK
always
sys_clk = #(CLK_PERIOD/2.0) ~sys_clk;
// Generate IDELAYCTRL reference clock (200MHz)
always
clk_ref = #REFCLK_PERIOD ~clk_ref;
assign sys_clk_p = sys_clk;
assign sys_clk_n = ~sys_clk;
assign clk_ref_p = clk_ref;
assign clk_ref_n = ~clk_ref;
//**************************************************************************//
always @( * ) begin
ddr3_ck_p_sdram <= #(TPROP_PCB_CTRL) ddr3_ck_p_fpga;
ddr3_ck_n_sdram <= #(TPROP_PCB_CTRL) ddr3_ck_n_fpga;
ddr3_addr_sdram <= #(TPROP_PCB_CTRL) ddr3_addr_fpga;
ddr3_ba_sdram <= #(TPROP_PCB_CTRL) ddr3_ba_fpga;
ddr3_ras_n_sdram <= #(TPROP_PCB_CTRL) ddr3_ras_n_fpga;
ddr3_cas_n_sdram <= #(TPROP_PCB_CTRL) ddr3_cas_n_fpga;
ddr3_we_n_sdram <= #(TPROP_PCB_CTRL) ddr3_we_n_fpga;
ddr3_cs_n_sdram <= #(TPROP_PCB_CTRL) ddr3_cs_n_fpga;
ddr3_cke_sdram <= #(TPROP_PCB_CTRL) ddr3_cke_fpga;
ddr3_odt_sdram <= #(TPROP_PCB_CTRL) ddr3_odt_fpga;
ddr3_dm_sdram_tmp <= #(TPROP_PCB_DATA) ddr3_dm_fpga;//DM signal generation
end
assign ddr3_dm_sdram = ddr3_dm_sdram_tmp;
// Controlling the bi-directional BUS
genvar dqwd;
generate
for (dqwd = 0;dqwd < DQ_WIDTH;dqwd = dqwd+1) begin : dq_delay
WireDelay #
(
.Delay_g (TPROP_PCB_DATA),
.Delay_rd (TPROP_PCB_DATA_RD)
)
u_delay_dq
(
.A (ddr3_dq_fpga[dqwd]),
.B (ddr3_dq_sdram[dqwd]),
.reset (sys_rst_n)
);
end
endgenerate
genvar dqswd;
generate
for (dqswd = 0;dqswd < DQS_WIDTH;dqswd = dqswd+1) begin : dqs_delay
WireDelay #
(
.Delay_g (TPROP_DQS),
.Delay_rd (TPROP_DQS_RD)
)
u_delay_dqs_p
(
.A (ddr3_dqs_p_fpga[dqswd]),
.B (ddr3_dqs_p_sdram[dqswd]),
.reset (sys_rst_n)
);
WireDelay #
(
.Delay_g (TPROP_DQS),
.Delay_rd (TPROP_DQS_RD)
)
u_delay_dqs_n
(
.A (ddr3_dqs_n_fpga[dqswd]),
.B (ddr3_dqs_n_sdram[dqswd]),
.reset (sys_rst_n)
);
end
endgenerate
assign sda = 1'b1;
assign scl = 1'b1;
mig_37 #
(
.nCK_PER_CLK (nCK_PER_CLK),
.tCK (tCK),
.RST_ACT_LOW (RST_ACT_LOW),
.REFCLK_FREQ (REFCLK_FREQ),
.IODELAY_GRP (IODELAY_GRP),
.INPUT_CLK_TYPE (INPUT_CLK_TYPE),
.BANK_WIDTH (BANK_WIDTH),
.CK_WIDTH (CK_WIDTH),
.CKE_WIDTH (CKE_WIDTH),
.COL_WIDTH (COL_WIDTH),
.nCS_PER_RANK (nCS_PER_RANK),
.DQ_WIDTH (DQ_WIDTH),
.DM_WIDTH (DM_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.CS_WIDTH (CS_WIDTH),
.BURST_MODE (BURST_MODE),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.CLKFBOUT_MULT_F (CLKFBOUT_MULT_F),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKOUT_DIVIDE (CLKOUT_DIVIDE),
.OUTPUT_DRV (OUTPUT_DRV),
.REG_CTRL (REG_CTRL),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
.DEBUG_PORT (DEBUG_PORT),
.tPRDI (tPRDI),
.tREFI (tREFI),
.tZQI (tZQI),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.ORDERING (ORDERING),
.STARVE_LIMIT (STARVE_LIMIT),
.ADDR_WIDTH (ADDR_WIDTH),
.ECC_TEST (ECC_TEST),
.TCQ (TCQ),
.DATA_WIDTH (DATA_WIDTH),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH)
)
u_ip_top
(
.sys_clk_p (sys_clk_p),
.sys_clk_n (sys_clk_n),
.clk_ref_p (clk_ref_p),
.clk_ref_n (clk_ref_n),
.sys_rst (sys_rst),
.ddr3_ck_p (ddr3_ck_p_fpga),
.ddr3_ck_n (ddr3_ck_n_fpga),
.ddr3_addr (ddr3_addr_fpga),
.ddr3_ba (ddr3_ba_fpga),
.ddr3_ras_n (ddr3_ras_n_fpga),
.ddr3_cas_n (ddr3_cas_n_fpga),
.ddr3_we_n (ddr3_we_n_fpga),
.ddr3_cs_n (ddr3_cs_n_fpga),
.ddr3_cke (ddr3_cke_fpga),
.ddr3_odt (ddr3_odt_fpga),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_dm (ddr3_dm_fpga),
.ddr3_dq (ddr3_dq_fpga),
.ddr3_dqs_p (ddr3_dqs_p_fpga),
.ddr3_dqs_n (ddr3_dqs_n_fpga),
.tb_clk (clk),
.tb_rst (rst),
.app_wdf_wren (app_wdf_wren),
.app_wdf_data (app_wdf_data),
.app_wdf_mask (app_wdf_mask),
.app_wdf_end (app_wdf_end),
.app_addr (app_addr),
.app_en (app_en),
.app_cmd (app_cmd),
.app_rdy (app_rdy),
.app_wdf_rdy (app_wdf_rdy),
.app_rd_data (app_rd_data),
.app_rd_data_valid (app_rd_data_valid),
.sda (sda),
.scl (scl),
.phy_init_done (phy_init_done)
);
// Extra one clock pipelining for RDIMM address and
// control signals is implemented here (Implemented external to memory model)
always @( posedge ddr3_ck_p_sdram[0] ) begin
if ( ddr3_reset_n == 1'b0 ) begin
ddr3_ras_n_r <= 1'b1;
ddr3_cas_n_r <= 1'b1;
ddr3_we_n_r <= 1'b1;
ddr3_cs_n_r <= {(CS_WIDTH*nCS_PER_RANK){1'b1}};
ddr3_odt_r <= 1'b0;
end
else begin
ddr3_addr_r <= #(CLK_PERIOD/2) ddr3_addr_sdram;
ddr3_ba_r <= #(CLK_PERIOD/2) ddr3_ba_sdram;
ddr3_ras_n_r <= #(CLK_PERIOD/2) ddr3_ras_n_sdram;
ddr3_cas_n_r <= #(CLK_PERIOD/2) ddr3_cas_n_sdram;
ddr3_we_n_r <= #(CLK_PERIOD/2) ddr3_we_n_sdram;
ddr3_cs_n_r <= #(CLK_PERIOD/2) ddr3_cs_n_sdram;
ddr3_odt_r <= #(CLK_PERIOD/2) ddr3_odt_sdram;
end
end
// to avoid tIS violations on CKE when reset is deasserted
always @( posedge ddr3_ck_n_sdram[0] )
if ( ddr3_reset_n == 1'b0 )
ddr3_cke_r <= 1'b0;
else
ddr3_cke_r <= #(CLK_PERIOD) ddr3_cke_sdram;
//***************************************************************************
// Instantiate memories
//***************************************************************************
genvar r,i,dqs_x;
generate
if(DRAM_DEVICE == "COMP") begin : comp_inst
for (r = 0; r < CS_WIDTH; r = r+1) begin: mem_rnk
if(MEMORY_WIDTH == 16) begin: mem_16
if(DQ_WIDTH/16) begin: gen_mem
for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem
ddr3_model u_comp_ddr3
(
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p_sdram),
.ck_n (ddr3_ck_n_sdram),
.cke (ddr3_cke_sdram[r]),
.cs_n (ddr3_cs_n_sdram[r]),
.ras_n (ddr3_ras_n_sdram),
.cas_n (ddr3_cas_n_sdram),
.we_n (ddr3_we_n_sdram),
.dm_tdqs (ddr3_dm_sdram[(2*(i+1)-1):(2*i)]),
.ba (ddr3_ba_sdram),
.addr (ddr3_addr_sdram),
.dq (ddr3_dq_sdram[16*(i+1)-1:16*(i)]),
.dqs (ddr3_dqs_p_sdram[(2*(i+1)-1):(2*i)]),
.dqs_n (ddr3_dqs_n_sdram[(2*(i+1)-1):(2*i)]),
.tdqs_n (),
.odt (ddr3_odt_sdram[r])
);
end
end
if (DQ_WIDTH%16) begin: gen_mem_extrabits
ddr3_model u_comp_ddr3
(
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p_sdram),
.ck_n (ddr3_ck_n_sdram),
.cke (ddr3_cke_sdram[r]),
.cs_n (ddr3_cs_n_sdram[r]),
.ras_n (ddr3_ras_n_sdram),
.cas_n (ddr3_cas_n_sdram),
.we_n (ddr3_we_n_sdram),
.dm_tdqs ({ddr3_dm_sdram[DM_WIDTH-1],ddr3_dm_sdram[DM_WIDTH-1]}),
.ba (ddr3_ba_sdram),
.addr (ddr3_addr_sdram),
.dq ({ddr3_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)],
ddr3_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)]}),
.dqs ({ddr3_dqs_p_sdram[DQS_WIDTH-1],
ddr3_dqs_p_sdram[DQS_WIDTH-1]}),
.dqs_n ({ddr3_dqs_n_sdram[DQS_WIDTH-1],
ddr3_dqs_n_sdram[DQS_WIDTH-1]}),
.tdqs_n (),
.odt (ddr3_odt_sdram[r])
);
end
end
else if((MEMORY_WIDTH == 8) || (MEMORY_WIDTH == 4)) begin: mem_8_4
for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem
ddr3_model u_comp_ddr3
(
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p_sdram),
.ck_n (ddr3_ck_n_sdram),
.cke (ddr3_cke_sdram[r]),
.cs_n (ddr3_cs_n_sdram[r]),
.ras_n (ddr3_ras_n_sdram),
.cas_n (ddr3_cas_n_sdram),
.we_n (ddr3_we_n_sdram),
.dm_tdqs (ddr3_dm_sdram[i]),
.ba (ddr3_ba_sdram),
.addr (ddr3_addr_sdram),
.dq (ddr3_dq_sdram[MEMORY_WIDTH*(i+1)-1:MEMORY_WIDTH*(i)]),
.dqs (ddr3_dqs_p_sdram[i]),
.dqs_n (ddr3_dqs_n_sdram[i]),
.tdqs_n (),
.odt (ddr3_odt_sdram[r])
);
end
end
end
end
else if(DRAM_DEVICE == "RDIMM") begin: rdimm_inst
for (r = 0; r < CS_WIDTH; r = r+1) begin: mem_rnk
if((MEMORY_WIDTH == 8) || (MEMORY_WIDTH == 4)) begin: mem_8_4
for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem
ddr3_model u_comp_ddr3
(
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p_sdram[(i*MEMORY_WIDTH)/72]),
.ck_n (ddr3_ck_n_sdram[(i*MEMORY_WIDTH)/72]),
.cke (ddr3_cke_r[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),
.cs_n (ddr3_cs_n_r[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),
.ras_n (ddr3_ras_n_r),
.cas_n (ddr3_cas_n_r),
.we_n (ddr3_we_n_r),
.dm_tdqs (ddr3_dm_sdram[i]),
.ba (ddr3_ba_r),
.addr (ddr3_addr_r),
.dq (ddr3_dq_sdram[MEMORY_WIDTH*(i+1)-1:MEMORY_WIDTH*(i)]),
.dqs (ddr3_dqs_p_sdram[i]),
.dqs_n (ddr3_dqs_n_sdram[i]),
.tdqs_n (),
.odt (ddr3_odt_r[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)])
);
end
end
end
end
else if(DRAM_DEVICE == "UDIMM") begin: udimm_inst
for (r = 0; r < CS_WIDTH; r = r+1) begin: mem_rnk
if(MEMORY_WIDTH == 16) begin: mem_16
if(DQ_WIDTH/16) begin: gen_mem
for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem
ddr3_model u_comp_ddr3
(
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p_sdram[(i*MEMORY_WIDTH)/72]),
.ck_n (ddr3_ck_n_sdram[(i*MEMORY_WIDTH)/72]),
.cke (ddr3_cke_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),
.cs_n (ddr3_cs_n_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),
.ras_n (ddr3_ras_n_sdram),
.cas_n (ddr3_cas_n_sdram),
.we_n (ddr3_we_n_sdram),
.dm_tdqs (ddr3_dm_sdram[(2*(i+1)-1):(2*i)]),
.ba (ddr3_ba_sdram),
.addr (ddr3_addr_sdram),
.dq (ddr3_dq_sdram[MEMORY_WIDTH*(i+1)-1:MEMORY_WIDTH*(i)]),
.dqs (ddr3_dqs_p_sdram[(2*(i+1)-1):(2*i)]),
.dqs_n (ddr3_dqs_n_sdram[(2*(i+1)-1):(2*i)]),
.tdqs_n (),
.odt (ddr3_odt_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)])
);
end
end
if (DQ_WIDTH%16) begin: gen_mem_extrabits
ddr3_model u_comp_ddr3
(
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p_sdram[(DQ_WIDTH-1)/72]),
.ck_n (ddr3_ck_n_sdram[(DQ_WIDTH-1)/72]),
.cke (ddr3_cke_sdram[((DQ_WIDTH-1)/72)+(nCS_PER_RANK*r)]),
.cs_n (ddr3_cs_n_sdram[((DQ_WIDTH-1)/72)+(nCS_PER_RANK*r)]),
.ras_n (ddr3_ras_n_sdram),
.cas_n (ddr3_cas_n_sdram),
.we_n (ddr3_we_n_sdram),
.dm_tdqs ({ddr3_dm_sdram[DM_WIDTH-1],ddr3_dm_sdram[DM_WIDTH-1]}),
.ba (ddr3_ba_sdram),
.addr (ddr3_addr_sdram),
.dq ({ddr3_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)],
ddr3_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)]}),
.dqs ({ddr3_dqs_p_sdram[DQS_WIDTH-1],
ddr3_dqs_p_sdram[DQS_WIDTH-1]}),
.dqs_n ({ddr3_dqs_n_sdram[DQS_WIDTH-1],
ddr3_dqs_n_sdram[DQS_WIDTH-1]}),
.tdqs_n (),
.odt (ddr3_odt_sdram[((DQ_WIDTH-1)/72)+(nCS_PER_RANK*r)])
);
end
end
else if((MEMORY_WIDTH == 8) || (MEMORY_WIDTH == 4)) begin: mem_8_4
for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem
ddr3_model u_comp_ddr3
(
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p_sdram[(i*MEMORY_WIDTH)/72]),
.ck_n (ddr3_ck_n_sdram[(i*MEMORY_WIDTH)/72]),
.cke (ddr3_cke_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),
.cs_n (ddr3_cs_n_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),
.ras_n (ddr3_ras_n_sdram),
.cas_n (ddr3_cas_n_sdram),
.we_n (ddr3_we_n_sdram),
.dm_tdqs (ddr3_dm_sdram[i]),
.ba (ddr3_ba_sdram),
.addr (ddr3_addr_sdram),
.dq (ddr3_dq_sdram[MEMORY_WIDTH*(i+1)-1:MEMORY_WIDTH*(i)]),
.dqs (ddr3_dqs_p_sdram[i]),
.dqs_n (ddr3_dqs_n_sdram[i]),
.tdqs_n (),
.odt (ddr3_odt_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)])
);
end
end
end
end
else if(DRAM_DEVICE == "SODIMM") begin: sodimm_inst
for (r = 0; r < CS_WIDTH; r = r+1) begin: mem_rnk
if(MEMORY_WIDTH == 16) begin: mem_16
if(DQ_WIDTH/16) begin: gen_mem
for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem
ddr3_model u_comp_ddr3
(
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p_sdram[(i*MEMORY_WIDTH)/72]),
.ck_n (ddr3_ck_n_sdram[(i*MEMORY_WIDTH)/72]),
.cke (ddr3_cke_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),
.cs_n (ddr3_cs_n_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),
.ras_n (ddr3_ras_n_sdram),
.cas_n (ddr3_cas_n_sdram),
.we_n (ddr3_we_n_sdram),
.dm_tdqs (ddr3_dm_sdram[(2*(i+1)-1):(2*i)]),
.ba (ddr3_ba_sdram),
.addr (ddr3_addr_sdram),
.dq (ddr3_dq_sdram[MEMORY_WIDTH*(i+1)-1:MEMORY_WIDTH*(i)]),
.dqs (ddr3_dqs_p_sdram[(2*(i+1)-1):(2*i)]),
.dqs_n (ddr3_dqs_n_sdram[(2*(i+1)-1):(2*i)]),
.tdqs_n (),
.odt (ddr3_odt_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)])
);
end
end
if (DQ_WIDTH%16) begin: gen_mem_extrabits
ddr3_model u_comp_ddr3
(
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p_sdram[(DQ_WIDTH-1)/72]),
.ck_n (ddr3_ck_n_sdram[(DQ_WIDTH-1)/72]),
.cke (ddr3_cke_sdram[((DQ_WIDTH-1)/72)+(nCS_PER_RANK*r)]),
.cs_n (ddr3_cs_n_sdram[((DQ_WIDTH-1)/72)+(nCS_PER_RANK*r)]),
.ras_n (ddr3_ras_n_sdram),
.cas_n (ddr3_cas_n_sdram),
.we_n (ddr3_we_n_sdram),
.dm_tdqs ({ddr3_dm_sdram[DM_WIDTH-1],ddr3_dm_sdram[DM_WIDTH-1]}),
.ba (ddr3_ba_sdram),
.addr (ddr3_addr_sdram),
.dq ({ddr3_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)],
ddr3_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)]}),
.dqs ({ddr3_dqs_p_sdram[DQS_WIDTH-1],
ddr3_dqs_p_sdram[DQS_WIDTH-1]}),
.dqs_n ({ddr3_dqs_n_sdram[DQS_WIDTH-1],
ddr3_dqs_n_sdram[DQS_WIDTH-1]}),
.tdqs_n (),
.odt (ddr3_odt_sdram[((DQ_WIDTH-1)/72)+(nCS_PER_RANK*r)])
);
end
end
if((MEMORY_WIDTH == 8) || (MEMORY_WIDTH == 4)) begin: mem_8_4
for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem
ddr3_model u_comp_ddr3
(
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p_sdram[(i*MEMORY_WIDTH)/72]),
.ck_n (ddr3_ck_n_sdram[(i*MEMORY_WIDTH)/72]),
.cke (ddr3_cke_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),
.cs_n (ddr3_cs_n_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),
.ras_n (ddr3_ras_n_sdram),
.cas_n (ddr3_cas_n_sdram),
.we_n (ddr3_we_n_sdram),
.dm_tdqs (ddr3_dm_sdram[i]),
.ba (ddr3_ba_sdram),
.addr (ddr3_addr_sdram),
.dq (ddr3_dq_sdram[MEMORY_WIDTH*(i+1)-1:MEMORY_WIDTH*(i)]),
.dqs (ddr3_dqs_p_sdram[i]),
.dqs_n (ddr3_dqs_n_sdram[i]),
.tdqs_n (),
.odt (ddr3_odt_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)])
);
end
end
end
end
endgenerate
// Traffic Gen Modules
init_mem_pattern_ctr #
(
.FAMILY ("VIRTEX6"),
.MEM_BURST_LEN (BURST_LENGTH),
.BEGIN_ADDRESS (BEGIN_ADDRESS),
.END_ADDRESS (END_ADDRESS),
.DWIDTH (APP_DATA_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
.EYE_TEST (EYE_TEST)
)
init_mem0
(
.clk_i (clk),
.rst_i (rst),
.mcb_cmd_en_i (app_en),
.mcb_cmd_instr_i (app_cmd[2:0]),
.mcb_cmd_addr_i (app_addr),
.mcb_cmd_bl_i (6'b001000),
.mcb_init_done_i (phy_init_done),
.cmp_error (error),
.run_traffic_o (t_gen_run_traffic),
.start_addr_o (t_gen_start_addr),
.end_addr_o (t_gen_end_addr),
.cmd_seed_o (t_gen_cmd_seed),
.data_seed_o (t_gen_data_seed),
.load_seed_o (t_gen_load_seed),
.addr_mode_o (t_gen_addr_mode),
.instr_mode_o (t_gen_instr_mode),
.bl_mode_o (t_gen_bl_mode),
.data_mode_o (t_gen_data_mode),
.mode_load_o (t_gen_mode_load),
.fixed_bl_o (t_gen_fixed_bl),
.fixed_instr_o (t_gen_fixed_instr),
.fixed_addr_o (t_gen_fixed_addr),
.mcb_wr_en_i (app_wdf_wren),
.vio_modify_enable (modify_enable_sel),
.vio_data_mode_value (data_mode_manual_sel),
.vio_addr_mode_value (addr_mode_manual_sel),
.vio_bl_mode_value (2'b01),
.vio_fixed_bl_value (6'b000010)
);
mcb_traffic_gen #
(
.FAMILY ("VIRTEX6"),
.MEM_BURST_LEN (BURST_LENGTH),
.PORT_MODE ("BI_MODE"),
.DATA_PATTERN (DATA_PATTERN),
.CMD_PATTERN (CMD_PATTERN),
.ADDR_WIDTH (ADDR_WIDTH),
.MEM_COL_WIDTH (COL_WIDTH),
.NUM_DQ_PINS (PAYLOAD_WIDTH),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.DWIDTH (APP_DATA_WIDTH),
.DQ_ERROR_WIDTH (PAYLOAD_WIDTH/8),
.PRBS_SADDR_MASK_POS (PRBS_SADDR_MASK_POS),
.PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS),
.PRBS_SADDR (BEGIN_ADDRESS),
.PRBS_EADDR (END_ADDRESS),
.EYE_TEST (EYE_TEST)
)
m_traffic_gen
(
.clk_i (clk),
.rst_i (rst),
.run_traffic_i (t_gen_run_traffic),
.manual_clear_error (manual_clear_error),
.start_addr_i (t_gen_start_addr),
.end_addr_i (t_gen_end_addr),
.cmd_seed_i (t_gen_cmd_seed),
.data_seed_i (t_gen_data_seed),
.load_seed_i (t_gen_load_seed),
.addr_mode_i (t_gen_addr_mode),
.instr_mode_i (t_gen_instr_mode),
.bl_mode_i (t_gen_bl_mode),
.data_mode_i (t_gen_data_mode),
.mode_load_i (t_gen_mode_load),
.fixed_bl_i (t_gen_fixed_bl),
.fixed_instr_i (t_gen_fixed_instr),
.fixed_addr_i (t_gen_fixed_addr),
.bram_cmd_i (39'b0),
.bram_valid_i (1'b0),
.bram_rdy_o (),
.mcb_cmd_en_o (app_en),
.mcb_cmd_instr_o (app_cmd[2:0]),
.mcb_cmd_addr_o (app_addr),
.mcb_cmd_bl_o (),
.mcb_cmd_full_i (~app_rdy),
.mcb_wr_en_o (app_wdf_wren),
.mcb_wr_data_o (app_wdf_data[APP_DATA_WIDTH-1:0]),
.mcb_wr_full_i (~app_wdf_rdy),
.mcb_wr_data_end_o (app_wdf_end),
.mcb_wr_fifo_counts (tg_wr_fifo_counts),
.mcb_wr_mask_o (),
.mcb_rd_en_o (tg_rd_en),
.mcb_rd_data_i (app_rd_data[APP_DATA_WIDTH-1:0]),
.mcb_rd_empty_i (~app_rd_data_valid),
.mcb_rd_fifo_counts (tg_rd_fifo_counts),
.counts_rst (rst),
.wr_data_counts (),
.rd_data_counts (),
.cmp_data (),
.cmp_error (),
.cmp_data_valid (),
.error (error),
.error_status (),
.mem_rd_data (),
.fixed_data_i ({APP_DATA_WIDTH{1'b0}}),
.dq_error_bytelane_cmp(),
.cumlative_dq_lane_error()
);
assign manual_clear_error = 1'b0;
assign modify_enable_sel = 1'b1;
assign data_mode_manual_sel = 3'b010; // ADDR_DATA
assign addr_mode_manual_sel = 3'b011; //SEQUENTIAL_ADDR
assign app_wdf_mask = {APP_MASK_WIDTH{1'b0}};
//***************************************************************************
// Reporting the test case status
//***************************************************************************
initial
begin : Logging
fork
begin : calibration_done
wait (phy_init_done);
$display("Calibration Done");
#50000000;
if (!error) begin
$display("TEST PASSED");
end
else begin
$display("TEST FAILED: DATA ERROR");
end
disable calib_not_done;
$finish;
end
begin : calib_not_done
#1000000000;
if (!phy_init_done) begin
$display("TEST FAILED: INITIALIZATION DID NOT COMPLETE");
end
disable calibration_done;
$finish;
end
join
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O221A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__O221A_FUNCTIONAL_PP_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__o221a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
and and0 (and0_out_X , or0_out, or1_out, C1 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O221A_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O31A_BLACKBOX_V
`define SKY130_FD_SC_LP__O31A_BLACKBOX_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o31a (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O31A_BLACKBOX_V
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : DLP Cache.
// File : dlp_top.v
// Author : Frank Bruno
// Created : 17-March-2012
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// The Display List Processor is used to automatically run commands
// to the Drawing engine, copy engine, or the DMA controller.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module dlp_cache
#(parameter BYTES = 4
)
(
input hb_clk, // clock input
input hb_rstn, // reset input
input dlp_flush, // Flush when end of list is reached.
input dlp_pop, // DLP read signal.
//
input mclock, // Memory controller clock
input mc_push, // memory controller push
input [(BYTES*8)-1:0] pd_in, // pixel data input
//**********************************************************************
// outputs to the Host Bus
//**********************************************************************
output dlp_data_avail, // DLP data Available.
output [(BYTES*8)-1:0] dlp_data, // DLP data.
output [6:0] rdusedw
);
/************************************************************************/
/* DLP FIFO. */
/************************************************************************/
wire rdempty;
wire flush_ff = (dlp_flush | ~hb_rstn);
assign dlp_data_avail = ~rdempty;
fifo_128x128a u_fifo_128_128a
(
.aclr (flush_ff),
.wrclk (mclock),
.wrreq (mc_push),
.data (pd_in),
.wrempty (),
.wrusedw (),
.rdclk (hb_clk),
.rdreq (dlp_pop),
.q (dlp_data),
.rdempty (rdempty),
.rdusedw (rdusedw)
);
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
//
// Author : Praveen Kumar Pendyala
// Create Date : 05/27/13
// Modify Date : 16/01/14
// Module Name : pdl_puf
// Project Name : PDL
// Target Devices : Xilinx Vertix 5, XUPV5 110T
// Tool versions : 13.2 ISE
//
// Description:
//
// This is probably what you are looking for.
//
// This module takes 2 signals and pdl configuration bits for 2 lines as inputs.
// Instantiates 64 pdl_switches and sends the received 2 signals along the switches
// Also assigns the configuration bits to switches.
// Final output signal is passed through arbiter and response is evaluated.
// The evaluated response will be sent back to higher modules.
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
`default_nettype none
module pdl_puf (s_tp, s_btm, s1, s2, reset, o);
// s: The challenge vector of size PUFlength
// q: The input trigger signal to the PUF (launch signal)
// reset: Resets the PUF output to zero and prepares it for the next round
// o: The output of the arbiters (response)
// s1: a sum bit from adder1;
// s2: a sum bit from adder2
parameter PUFlength = 63;
input [PUFlength:0] s_tp, s_btm;
input s1, s2, reset;
output o;
wire [PUFlength:0] i1,i2;
wire puf_out;
(* KEEP_HIERARCHY="TRUE" *)
pdl_switch sarray [PUFlength:0] (
.i1({s1,i1[PUFlength:1]}),
.i2({s2,i2[PUFlength:1]}),
.select_tp(s_tp[PUFlength:0]),
.select_btm(s_btm[PUFlength:0]),
.o1(i1[PUFlength:0]),
.o2(i2[PUFlength:0])
);
// Arbiter to decide which signal reached first.
FDC FDC1 (.Q (puf_out),
.C (i2[0]),
.CLR (reset),
.D (i1[0]));
(* BEL ="D6LUT" *) (* LOCK_PINS = "all" *)
LUT1 #(
.INIT(2'b10) // Specify LUT Contents
) LUT1_inst_2 (
.O(o), // LUT general output
.I0(puf_out) // LUT input
);
endmodule
|
`timescale 1ns / 1ps
module LCD_DISPLAY(LCD_ENABLE, LCD_RW, LCD_DI, LCD_CS1, LCD_CS2, LCD_RST, LCD_DATA, CLEAR, CALLFORPATTERN, PATTERN, reset, clk);
input clk;
input reset;
input [255:0] PATTERN;
output LCD_ENABLE;
output LCD_RW;
output LCD_DI;
output LCD_CS1;
output LCD_CS2;
output LCD_RST;
output [7:0] LCD_DATA;
output CALLFORPATTERN, CLEAR;
reg [7:0] LCD_DATA;
reg [1:0] LCD_SEL;
reg [2:0] STATE;
reg [2:0] X_PAGE;
reg [1:0] DELAY;
reg [7:0] INDEX;
reg [1:0] ENABLE;
reg CLEAR;
reg LCD_RW;
reg LCD_DI;
reg LCD_RST;
reg CALLFORPATTERN;
wire clk;
wire LCD_CS1;
wire LCD_CS2;
wire LCD_ENABLE;
always@(negedge clk or negedge reset) begin
if(!reset) begin
CLEAR = 1'b1;
STATE = 3'b0;
DELAY = 2'b00;
X_PAGE = 3'o0;
INDEX = 8'd0;
LCD_DATA = 8'd0;
LCD_RST= 1'b0;
ENABLE = 2'b00;
LCD_SEL= 2'b11;
LCD_DI = 1'b0;
LCD_RW = 1'b0;
CALLFORPATTERN = 0;
end else begin
if(ENABLE < 2'b10) begin
/*given en onepulse signal & delay 2 cycle*/
ENABLE = ENABLE + 2'b1;
DELAY[1]= 1'b1;
CALLFORPATTERN = 0;
end else if(DELAY != 2'b00)begin
/*given delay cycle by yourself, at most 2^18*/
DELAY = DELAY - 2'b1;
end else if(STATE == 3'o0) begin
LCD_RST = 1'b1;
LCD_DATA = 8'h3F;
ENABLE = 2'b00;
STATE = 3'o1;
end else if(STATE == 3'o1) begin
/*set up start line*/
LCD_DATA = {2'b11,6'b000000};
ENABLE = 2'b00;
STATE = 3'o2;
end else if(STATE == 3'o2) begin
/*set Y*/
LCD_DATA = 8'h40;
ENABLE = 2'b00;
STATE = 3'o3;
end else if(STATE == 3'o3) begin
/*set X*/
LCD_DI = 1'b0;
INDEX = 8'hFF;;
LCD_DATA = {5'b10111,X_PAGE};
STATE = 3'o4;
ENABLE = 2'b00;
if(CLEAR)CALLFORPATTERN = 0;
else CALLFORPATTERN = 1;
end else if(STATE == 3'o4) begin
if(CLEAR) begin
/*set all pixel to off*/
LCD_SEL = 2'b11;
if(INDEX < 8'd63 || INDEX==8'hFF) begin
LCD_DI = 1'b1;
INDEX = INDEX + 8'd1;
LCD_DATA = 8'h00;
ENABLE = 2'b00;
end else if(X_PAGE < 3'o7) begin
X_PAGE = X_PAGE + 3'o1;
STATE = 3'o3;
end else begin
X_PAGE = 3'o0;
STATE = 3'o3;
CLEAR = 1'b0;
end
end else begin
LCD_SEL = 2'b01;
if(INDEX < 8'd63 || INDEX==8'hFF) begin
LCD_DI = 1'b1;
INDEX = INDEX + 8'h1;
if(INDEX < 8'd32)begin
LCD_DATA[7:0] = PATTERN[ ((INDEX+1)*8-1)-:8 ];
end else begin
LCD_DATA[7:0] = PATTERN[ ((INDEX-8'd31)*8-1)-:8 ];
end
ENABLE= 2'b00;
end else if(X_PAGE<3'd7)begin
LCD_SEL = 2'b11;
X_PAGE = X_PAGE + 3'o1;
LCD_DI = 1'b0;
INDEX = 8'hFF;
LCD_DATA = {5'b10111,X_PAGE};
STATE = 3'o4;
ENABLE = 2'b00;
end else begin
X_PAGE = X_PAGE + 3'o1;
LCD_SEL = 2'b11;
LCD_DI = 1'b0;
INDEX = 8'hFF;
LCD_DATA = {5'b10111,X_PAGE};
STATE = 3'o5;
ENABLE = 2'b00;
end
if(INDEX==8'hFF || INDEX==8'd31)CALLFORPATTERN = 1;
else CALLFORPATTERN = 0;
end
end else if(STATE == 3'o5) begin
LCD_SEL = 2'b10;
if(INDEX < 8'd63 || INDEX==8'hFF) begin
LCD_DI = 1'b1;
INDEX = INDEX + 8'h1;
if(INDEX < 8'd32)begin
LCD_DATA[7:0] = PATTERN[ ((INDEX+1)*8-1)-:8 ];
end else begin
LCD_DATA[7:0] = PATTERN[ ((INDEX-8'd31)*8-1)-:8 ];
end
ENABLE= 2'b00;
end else if(X_PAGE<3'd7)begin
LCD_SEL = 2'b11;
X_PAGE = X_PAGE + 3'o1;
LCD_DI = 1'b0;
INDEX = 8'hFF;
LCD_DATA = {5'b10111,X_PAGE};
STATE = 3'o5;
ENABLE = 2'b00;
end else begin
LCD_SEL = 2'b11;
X_PAGE = 3'o0;
STATE = 3'o3;
end
if(INDEX==8'hFF || INDEX==8'd31)CALLFORPATTERN = 1;
else CALLFORPATTERN = 0;
end
end
end
assign LCD_ENABLE = ENABLE[0];
assign LCD_CS1 = LCD_SEL[0];
assign LCD_CS2 = LCD_SEL[1];
endmodule
|
//---------------------------------------------------------------------------
//-- Copyright 2015 - 2017 Systems Group, ETH Zurich
//--
//-- This hardware module is free software: you can redistribute it and/or
//-- modify it under the terms of the GNU General Public License as published
//-- by the Free Software Foundation, either version 3 of the License, or
//-- (at your option) any later version.
//--
//-- This program is distributed in the hope that it will be useful,
//-- but WITHOUT ANY WARRANTY; without even the implied warranty of
//-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
//-- GNU General Public License for more details.
//--
//-- You should have received a copy of the GNU General Public License
//-- along with this program. If not, see <http://www.gnu.org/licenses/>.
//---------------------------------------------------------------------------
module rem_halfrange #(parameter HIGH_HALF=0)
(
clk,
rst,
config_valid,
config_char,
config_chained,
config_range_en,
input_valid,
input_char,
prev_matched,
this_matched,
low_smaller,
this_smaller
);
input clk;
input rst;
input config_valid;
input [7:0] config_char;
input config_chained;
input config_range_en; // only relevant if LOW_PART=0
input input_valid;
input [7:0] input_char;
input prev_matched;
input low_smaller; // only relevant if LOW_PART=0
output this_matched;
output this_smaller; // only relevant if LOW_PART=1
reg char_match;
reg [7:0] char_data;
reg is_chained;
reg is_ranged;
assign this_matched = char_match;
assign this_smaller = (HIGH_HALF==0 && input_valid==1) ? input_char>char_data-1 : 0;
always @(posedge clk)
begin
if(rst) begin
char_data <= 0;
char_match <= 0;
end
else begin
if (input_valid==1) begin
if (char_data==input_char) begin
char_match <= is_chained ? prev_matched : 1;
end
else begin
if (HIGH_HALF==1 && is_ranged==1 && char_data>input_char && low_smaller==1) begin
char_match <= 1;
end
else begin
char_match <= 0;
end
end
end
if (config_valid==1) begin
char_data <= config_char;
is_chained <= config_chained;
is_ranged <= config_range_en;
char_match <= 0;
end
end
end
endmodule
|
/// date :2016/2/27
/// engineer
/// module name mem controler
/// module function : include direcotory ram and data ram
module memory_fsm(// global signals
clk,
rst,
//fsm state of rep paralle-serial port corresponding to mem
m_rep_fsm_state,
//fsm state of req paralle-serial port corresponding to mem
m_req_fsm_state,
// fsm state of req/rep regs to data cache
d_fsm_state,
// fsm state of input reg to inst cache
i_fsm_state,
// input from mem_ram
mem_state_out,
mem_data_in,
// input from local d cache
v_d_req,
v_d_rep,
local_d_head_in,
local_d_addr_in,
local_d_data_in,
// input from local i cache
v_i_rep,
// local_i_head, // no need for local i cache miss
local_i_addr_in,
// input form INfifos
v_INfifos,
infifos_head_in,
infifos_addr_in,
infifos_data_in,
//output to mem_ram
data_out_mem_ram,
state_out_mem_ram,
addr_out_mem_ram,
//output to mem_ram
state_we_out,
state_re_out,
data_we_out,
data_re_out,
// output to local d cache
v_req_d,
v_rep_d,
head_out_local_d,
addr_out_local_d,
data_out_local_d,
// output to local i cahce
v_rep_Icache,
data_out_local_i,
// output to OUT req fifo
en_inv_ids,
inv_ids_in,
flit_max_req,
en_flit_max_req,
v_req_out,
head_out_req_out,
addr_out_req_out,
// data_out_req_out,
// output to OUT rep fifo
flit_max_rep,
en_flit_max_rep,
v_rep_out,
head_out_rep_out,
addr_out_rep_out,
data_out_rep_out,
mem_access_done
);
// parameters of msg type used for temp reg
parameter shrep_type=4'b0001;
parameter wbreq_type=4'b0010;
parameter exrep_type=4'b0011;
parameter SHexrep_type=4'b0100;
parameter invreq_type=4'b0101;
parameter SCinvreq_type=4'b0110;
parameter flushreq_type=4'b0111;
parameter SCflurep_type=4'b1000;
parameter instrep_type=4'b1001;
parameter nackrep_type=4'b1010;
parameter local_id=2'b00;
/// parameter of msg cmd
/////// request cmd
parameter shreq_cmd=5'b00000;
parameter exreq_cmd=5'b00001;
parameter SCexreq_cmd=5'b00010;
parameter instreq_cmd=5'b00110;
parameter wbreq_cmd=5'b00011;
parameter invreq_cmd=5'b00100;
parameter flushreq_cmd=5'b00101;
parameter SCinvreq_cmd=5'b00110;
/////// reply cmd
parameter wbrep_cmd=5'b10000;
parameter C2Hinvrep_cmd=5'b10001;
parameter flushrep_cmd=5'b10010;
parameter ATflurep_cmd=5'b10011;
parameter shrep_cmd=5'b11000;
parameter exrep_cmd=5'b11001;
parameter SH_exrep_cmd=5'b11010;
parameter SCflurep_cmd=5'b11100;
parameter instrep_cmd=5'b10100;
parameter C2Cinvrep_cmd=5'b11011;
parameter nackrep_cmd=5'b10101;
parameter flushfail_rep_cmd=5'b10110;
parameter wbfail_rep_cmd=5'b10111;
///
parameter i_idle=2'b00;
parameter d_idle=1'b0;
parameter m_rep_idle=1'b0;
parameter m_req_idle=1'b0;
input clk;
input rst;
input [1:0] i_fsm_state;
input d_fsm_state;
input m_rep_fsm_state;
input m_req_fsm_state;
// input from mem_ram
input [5:0] mem_state_out;
input [127:0] mem_data_in;
// input from local d cache
input v_d_req;
input v_d_rep;
input [15:0] local_d_head_in;
input [31:0] local_d_addr_in;
input [127:0] local_d_data_in;
// input from local i cache
input v_i_rep;
// local_i_head, // no need for local i cache miss
input [31:0] local_i_addr_in;
// input form INfifos
input v_INfifos;
input [15:0] infifos_head_in;
input [31:0] infifos_addr_in;
input [127:0] infifos_data_in;
// output to mem_ram
output [127:0] data_out_mem_ram;
output [5:0] state_out_mem_ram;
output [31:0] addr_out_mem_ram;
//output to mem_ram
output state_we_out;
output state_re_out;
output data_we_out;
output data_re_out;
// output to local d cache
output v_req_d;
output v_rep_d;
output [15:0] head_out_local_d;
output [31:0] addr_out_local_d;
output [127:0] data_out_local_d;
// output to local i cahce
output v_rep_Icache;
output [127:0] data_out_local_i;
// output to OUT req fifo
output en_inv_ids;
output [3:0] inv_ids_in;
output [3:0] flit_max_req;
output en_flit_max_req;
output v_req_out;
output [15:0] head_out_req_out;
output [31:0] addr_out_req_out;
// output [127:0] data_out_req_out;
// output to OUT rep fifo
output [3:0] flit_max_rep;
output en_flit_max_rep;
output v_rep_out;
output [15:0] head_out_rep_out;
output [31:0] addr_out_rep_out;
output [127:0] data_out_rep_out;
output mem_access_done;
wire [5:0] m_state_out;
assign m_state_out=mem_state_out;
reg [15:0] temp_req_head_flit;
reg [15:0] temp_rep_head_flit;
wire [15:0] temp_req_head_flit_in1;
wire [15:0] temp_rep_head_flit_in1;
///////////////////////////////////////////////////////////////////////////
//////////////////////MEMORY FSM///////////////////////////////////////////
reg state_re_out;
reg mem_access_done;
reg data_re_out;
reg [1:0] addr_sel;
reg [1:0] data_sel;
reg req_done;
reg rep_done;
reg has_only_id;
reg [5:0] m_state_in;
reg en_rep_type;
reg [3:0] rep_type;
reg [3:0] rep_type_reg;
reg en_req_type;
reg [3:0] req_type;
reg [3:0] req_type_reg;
reg en_m_state_in;
reg oneORmore;
reg en_inv_ids;
reg [3:0] inv_ids_in;
reg [3:0] src_id_dir;
reg [3:0] requester_id_dir;
reg en_m_data_in;
reg [175:0] msg;
reg v_rep_d;
reg v_rep_out;
reg v_req_d;
reg v_req_out;
reg v_rep_Icache;
//reg [4:0] thead;
///////////// I have forget what function it is ,soI think I should take enough notes to some strange things
reg en_temp_rep_head_flit;
reg [15:0] temp_rep_head_flit_in;
reg en_temp_req_head_flit;
reg [15:0] temp_req_head_flit_in;
//reg [3:0] flit_max;
//reg en_flit_max;
reg [3:0] flit_max_rep;
reg en_flit_max_rep;
reg [3:0] flit_max_req;
reg en_flit_max_req;
reg t_req_head_sel;
reg t_rep_head_sel;
reg id_sel_out;
reg rep_local_remote;
reg req_local_remote;
reg [4:0] cmd_type;
reg set_req_done;
reg set_rep_done;
reg rst_rep_type;
reg rst_req_type;
////////fsm
parameter m_idle=2'b00;
parameter m_compare_tag=2'b01;
parameter m_gen_shrep=2'b10;
parameter m_gen_exrep=2'b11;
reg [1:0] nstate;
reg [1:0] rstate;
wire [15:0] seled_head;
wire [31:0] seled_addr;
wire [127:0] seled_data;
wire [127:0] data_read;
assign data_read=mem_data_in;
assign seled_head=addr_sel?infifos_head_in:local_d_head_in;
assign seled_addr=addr_sel?infifos_addr_in:local_d_addr_in;
assign addr_out_mem_ram=seled_addr;
always@(*)
begin
// default signal values
// en_temp_head_flit=1'b0;
mem_access_done=1'b0;
state_re_out=1'b0;
data_re_out=1'b0;
cmd_type=5'b00000;
rep_local_remote=1'b0;
req_local_remote=1'b0;
addr_sel=1'b0;
data_sel=1'b0;
nstate=rstate;
has_only_id=1'b0;
m_state_in=6'b000000;
en_rep_type=1'b0;
rep_type=4'b0000;
en_req_type=1'b0;
req_type=4'b0000;
en_m_state_in=1'b0;
oneORmore=1'b0;
en_inv_ids=1'b0;
inv_ids_in=4'b0000;
src_id_dir=4'b0000;
requester_id_dir=4'b0000;
en_m_data_in=1'b0;
msg=176'h0000;
v_rep_d=1'b0;
v_rep_out=1'b0;
v_req_d=1'b0;
v_req_out=1'b0;
v_rep_Icache=1'b0;
// thead=5'b00000;
t_req_head_sel=1'b0;
t_rep_head_sel=1'b0;
en_temp_rep_head_flit=1'b0;
temp_rep_head_flit_in =16'h0000;
en_temp_req_head_flit=1'b0;
temp_req_head_flit_in=16'h0000;
// flit_max=4'b0000;
// en_flit_max=1'b0;
flit_max_req=4'b0000;
en_flit_max_req=1'b0;
flit_max_rep=4'b0000;
en_flit_max_rep=1'b0;
id_sel_out=1'b0;
set_req_done=1'b0;
set_rep_done=1'b0;
rst_rep_type=1'b0;
rst_req_type=1'b0;
case(rstate)
m_idle:
begin
if(v_d_req==1'b1||v_d_rep==1'b1)
begin
addr_sel=1'b0;
data_sel=1'b0;
nstate=m_compare_tag;
// en_temp_head_flit=1'b1;
t_req_head_sel=1'b0;
t_rep_head_sel=1'b0;
en_temp_rep_head_flit=1'b1;
en_temp_req_head_flit=1'b1;
end
else if(v_INfifos==1'b1)
begin
addr_sel=1'b1;
data_sel=1'b1;
nstate=m_compare_tag;
// en_temp_head_flit=1'b1;
t_req_head_sel=1'b0;
t_rep_head_sel=1'b0;
en_temp_rep_head_flit=1'b1;
en_temp_req_head_flit=1'b1;
end
end
m_compare_tag:
begin
state_re_out=1'b1;
// has_only_id function
case(seled_head[12:11])
2'b00:has_only_id=m_state_out[3:0]==4'b0001;
2'b01:has_only_id=m_state_out[3:0]==4'b0010;
2'b10:has_only_id=m_state_out[3:0]==4'b0100;
2'b11:has_only_id=m_state_out[3:0]==4'b1000;
// default:has_only_id=m_state_out[3:0]==4'b0001;
endcase
//id_sel_out
case(seled_head[12:11])
2'b00:id_sel_out=m_state_out[0];
2'b01:id_sel_out=m_state_out[1];
2'b10:id_sel_out=m_state_out[2];
2'b11:id_sel_out=m_state_out[3];
endcase
// default:id_sel_out=m_state_out[0];
//////////////////////////////////
// check req /rep type////////////
//////////////////////////////////
//////////////////////////////////
// fsm will gen shreps
if((seled_head[9:5]==shreq_cmd||seled_head[9:5]==wbfail_rep_cmd)&&m_state_out[5:4]==2'b00&&id_sel_out==1'b0)
begin
if(seled_addr[12:11]==local_id)
rep_local_remote=1'b0;
else
rep_local_remote=1'b1;
en_m_state_in=1'b1;
case(seled_head[12:11])
2'b00:m_state_in={m_state_out[5:1],1'b0};
2'b01:m_state_in={m_state_out[5:2],1'b0,m_state_out[0]};
2'b10:m_state_in={m_state_out[5:3],1'b0,m_state_out[1:0]};
2'b11:m_state_in={m_state_out[5:4],1'b0,m_state_out[2:0]};
default:m_state_in=m_state_out;
endcase
rep_type=shrep_type;
en_rep_type=1'b1;
// oneORmore=1'b0;
nstate=m_gen_shrep;
// t_req_head_sel=1'b0;
t_rep_head_sel=1'b1;
en_temp_rep_head_flit=1'b1;
temp_rep_head_flit_in={temp_rep_head_flit[12:11],1'b0,temp_rep_head_flit[15:14],1'b1,shrep_cmd,5'b00000};
end
////////////////////////////////////
// fsm will gen NACKreply
if(seled_head[9:5]==shreq_cmd&&m_state_out[5]==1'b1)
begin
if(seled_addr[12:11]==local_id)
rep_local_remote=1'b0;
else
rep_local_remote=1'b1;
/// since the addr being accessed is busy doing other thing,home should just NACK this request ,
/// (via sending back a simple reply tell the requester the addr now is busy ,please retry again(here just for simplicity))
/// and no need to do something to m_state!
rep_type=nackrep_type;
en_rep_type=1'b1;
/* en_m_state_in=1'b1;
case(seled_head[12:11])
2'b00:m_state_in={m_state_out[5:1],1'b0};
2'b01:m_state_in={m_state_out[5:2],1'b0,m_state_out[0]};
2'b01:m_state_in={m_state_out[5:3],1'b0,m_state_out[1:0]};
2'b01:m_state_in={m_state_out[5:4],1'b0,m_state_out[2:0]};
default:m_state_in=m_state_out;
endcase */
// oneORmore=1'b0;
nstate=m_gen_shrep;
// t_req_head_sel=1'b0;
t_rep_head_sel=1'b1;
en_temp_rep_head_flit=1'b1;
temp_rep_head_flit_in={temp_rep_head_flit[12:11],1'b0,temp_rep_head_flit[15:14],1'b1,nackrep_cmd,5'b00000};
end
//////////////////////
// fsm will gen wbreq
if(seled_head[9:5]==shreq_cmd&&m_state_out[5:4]==2'b01&&id_sel_out==1'b0)
begin
if(seled_addr[12:11]==local_id)
req_local_remote=1'b0;
else
req_local_remote=1'b1;
en_m_state_in=1'b1;
m_state_in={2'b11,m_state_out[3:0]};
en_req_type=1'b1;
req_type=wbreq_type;
// oneORmore=1'b0;
t_req_head_sel=1'b1;
// t_rep_head_sel=1'b0;
nstate=m_gen_shrep;
en_temp_req_head_flit=1'b1;
temp_req_head_flit_in={2'b00,1'b0,temp_req_head_flit[15:14],1'b1,wbreq_cmd,temp_req_head_flit[12:11],3'b000};
end
////////////////////////
// fsm will gen exrep
if((seled_head[9:5]==exreq_cmd||seled_head[9:5]==flushfail_rep_cmd||seled_head[9:5]==SCexreq_cmd)&&m_state_out[5:4]==2'b00&&(|m_state_out[3:0]==1'b0||has_only_id))
begin
if(seled_addr[12:11]==local_id)
rep_local_remote=1'b0;
else
rep_local_remote=1'b1;
en_m_state_in=1'b1;
case(seled_head[12:11])
2'b00:m_state_in=6'b100001;
2'b01:m_state_in=6'b100010;
2'b10:m_state_in=6'b100100;
2'b11:m_state_in=6'b101000;
default:m_state_in=6'b100001;
endcase
rep_type=exrep_type;
en_rep_type=1'b1;
oneORmore=1'b0;
nstate=m_gen_exrep;
// t_req_head_sel=1'b0;
t_rep_head_sel=1'b1;
en_temp_rep_head_flit=1'b1;
temp_rep_head_flit_in={temp_rep_head_flit[12:11],1'b0,temp_rep_head_flit[15:14],1'b1,exrep_cmd,5'b00000};
end
////////////////////////
// fsm will gen NACKrep
if((seled_head[9:5]==exreq_cmd||seled_head[9:5]==SCexreq_cmd)&&m_state_out[5]==1'b1)
begin
if(seled_addr[12:11]==local_id)
rep_local_remote=1'b0;
else
rep_local_remote=1'b1;
/// since the addr being accessed is busy doing other thing,home should just NACK this request ,
/// (via sending back a simple reply tell the requester the addr now is busy ,please retry again(here just for simplicity))
/// and no need to do something to m_state!
rep_type=nackrep_type;
en_rep_type=1'b1;
oneORmore=1'b0;
/* en_m_state_in=1'b1;
case(seled_head[12:11])
2'b00:m_state_in=6'b100001;
2'b01:m_state_in=6'b100010;
2'b01:m_state_in=6'b100100;
2'b01:m_state_in=6'b101000;
default:m_state_in=6'b100001;
endcase */
nstate=m_gen_exrep;
// t_req_head_sel=1'b0;
t_rep_head_sel=1'b1;
en_temp_rep_head_flit=1'b1;
temp_rep_head_flit_in={temp_rep_head_flit[12:11],1'b0,temp_rep_head_flit[15:14],1'b1,nackrep_cmd,5'b00000};
end
//////////////////////////////////
//// fsm will gen invreq /SCinvreq
if((seled_head[9:5]==exreq_cmd||seled_head[9:5]==SCexreq_cmd)&&m_state_out[5:4]==2'b00&&!(|m_state_out[3:0]==1'b0||has_only_id))
begin
// check whether the original dir include src_id
if(id_sel_out==1'b1)
begin
case(seled_head[12:11])
2'b00:m_state_in={2'b10,m_state_out[3:1],1'b0};
2'b01:m_state_in={2'b10,m_state_out[3:2],1'b0,m_state_out[0]};
2'b10:m_state_in={2'b10,m_state_out[3],1'b0,m_state_out[1:0]};
2'b11:m_state_in={2'b10,1'b0,m_state_out[2:0]};
default:m_state_in={2'b10,m_state_out[3:1],1'b0};
endcase
end
else
begin
m_state_in={2'b10,m_state_out[3:0]};
end
//check whether invreq or SCinvreq
if(seled_head[9:5]==exreq_cmd)
begin
req_type=invreq_type;
cmd_type=invreq_cmd;
end
else
begin
req_type=SCinvreq_type;
cmd_type=SCinvreq_cmd;
end
if(seled_addr[12:11]==local_id)
req_local_remote=1'b0;
else
req_local_remote=1'b1;
// commen signals
en_m_state_in=1'b1;
en_req_type=1'b1;
oneORmore=1'b1;
rep_type=SHexrep_type;
en_rep_type=1'b1;
// reg the invreq vectors!
en_inv_ids=1'b1;
inv_ids_in=m_state_out[3:0];
nstate=m_gen_exrep;
t_req_head_sel=1'b1;
t_rep_head_sel=1'b1;
en_temp_rep_head_flit=1'b1;
temp_rep_head_flit_in={temp_rep_head_flit[12:11],1'b0,temp_rep_head_flit[15:14],1'b1,exrep_cmd,1'b0,m_state_out[3:0]};
en_temp_req_head_flit=1'b1;
temp_req_head_flit_in={2'b00,1'b0,temp_rep_head_flit[15:14],1'b1,cmd_type,temp_rep_head_flit[12:11],3'b000};
end
//////////////////
// gen flushreq
if(seled_head[9:5]==exreq_cmd&&m_state_out[5:4]==2'b10&&id_sel_out==1'b0)
begin
if(seled_addr[12:11]==local_id)
req_local_remote=1'b0;
else
req_local_remote=1'b1;
oneORmore=1'b0;
en_m_state_in=1'b1;
m_state_in={2'b11,m_state_out[3:0]};
en_req_type=1'b1;
req_type=flushreq_type;
nstate=m_gen_exrep;
t_req_head_sel=1'b1;
// t_rep_head_sel=1'b0;
en_temp_req_head_flit=1'b1;
temp_req_head_flit_in={2'b00,1'b0,temp_req_head_flit[15:14],1'b1,flushreq_cmd,temp_req_head_flit[12:11],3'b000};
end
/////////////////
// gen SCflushrep
if(seled_head[9:5]==SCexreq_cmd&&m_state_out[5:4]==2'b10&&id_sel_out==1'b0)
begin
if(seled_addr[12:11]==local_id)
rep_local_remote=1'b0;
else
rep_local_remote=1'b1;
oneORmore=1'b0;
en_rep_type=1'b1;
rep_type=SCflurep_type;
// t_req_head_sel=1'b0;
nstate=m_gen_exrep;
t_rep_head_sel=1'b1;
en_temp_rep_head_flit=1'b1;
temp_rep_head_flit_in={temp_rep_head_flit[12:11],1'b0,temp_rep_head_flit[15:14],1'b1,SCflurep_cmd,5'b00000};
end
/////////////////
/// gen instrep!
if(seled_head[9:5]==instreq_cmd)
begin
if(seled_addr[12:11]==local_id)
rep_local_remote=1'b0;
else
rep_local_remote=1'b1;
en_rep_type=1'b1;
rep_type=instrep_type;
// oneORmore=1'b0;
nstate=m_gen_shrep;
// t_req_head_sel=1'b0;
t_rep_head_sel=1'b1;
en_temp_rep_head_flit=1'b1;
temp_rep_head_flit_in={temp_rep_head_flit[12:11],1'b0,temp_rep_head_flit[15:14],1'b1,instrep_cmd,5'b00000};
end
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
///////////fsm will process the rep from network or local D$ or I$///////
//process invreps
if(seled_head[9:5]==C2Cinvrep_cmd&&(m_state_out[5:4]==2'b10))
begin
rst_rep_type=1'b1;
rst_req_type=1'b1;
nstate=m_idle;
mem_access_done=1'b1;
// some invreps haven't come
if(m_state_out[3:0]!=src_id_dir)
begin
en_m_state_in=1'b1;
case(seled_head[12:11])
2'b00:m_state_in={2'b10,m_state_out[3:1],1'b0};
2'b01:m_state_in={2'b10,m_state_out[3:2],1'b0,m_state_out[0]};
2'b10:m_state_in={2'b10,m_state_out[3],1'b0,m_state_out[1:0]};
2'b11:m_state_in={2'b10,1'b0,m_state_out[2:0]};
default:m_state_in={2'b10,m_state_out[3:1],1'b0};
endcase
end
// all the necessary invreps have come
else
begin
m_state_in={2'b01,requester_id_dir};
en_m_state_in=1'b1;
end
//src_id_dir :convert src_id to dir style
case(seled_head[12:11])
2'b00:src_id_dir=4'b0001;
2'b01:src_id_dir=4'b0010;
2'b10:src_id_dir=4'b0100;
2'b11:src_id_dir=4'b1000;
default:src_id_dir=4'b0001;
endcase
//requester_id_dir: convert requester id into dir stylr
case(seled_head[4:3])
2'b00:requester_id_dir=4'b0001;
2'b01:requester_id_dir=4'b0010;
2'b10:requester_id_dir=4'b0100;
2'b11:requester_id_dir=4'b1000;
default:requester_id_dir=4'b0001;
endcase
end
////////////////////////////////////
/// process (auto)invreps
if(seled_head[9:5]==C2Hinvrep_cmd&&(m_state_out[5:4]==2'b00))
begin
rst_rep_type=1'b1;
rst_req_type=1'b1;
nstate=m_idle;
mem_access_done=1'b1;
en_m_state_in=1'b1;
case(seled_head[12:11])
2'b00:m_state_in={2'b00,m_state_out[3:1],1'b0};
2'b01:m_state_in={2'b00,m_state_out[3:2],1'b0,m_state_out[0]};
2'b10:m_state_in={2'b00,m_state_out[3],1'b0,m_state_out[1:0]};
2'b11:m_state_in={2'b00,1'b0,m_state_out[2:0]};
default:m_state_in={2'b00,m_state_out[3:1],1'b0};
endcase
end
//////////////////////////////////////
/// process wbrep
if(seled_head[9:5]==wbrep_cmd&&(m_state_out[5:4]==2'b11))
begin
rst_rep_type=1'b1;
rst_req_type=1'b1;
nstate=m_idle;
mem_access_done=1'b1;
en_m_state_in=1'b1;
en_m_data_in=1'b1;
case(seled_head[12:11])
2'b00:m_state_in={2'b00,m_state_out[3:1],1'b1};
2'b01:m_state_in={2'b00,m_state_out[3:2],1'b1,m_state_out[0]};
2'b10:m_state_in={2'b00,m_state_out[3],1'b1,m_state_out[1:0]};
2'b11:m_state_in={2'b00,1'b1,m_state_out[2:0]};
default:m_state_in={2'b00,m_state_out[3:1],1'b1};
endcase
end
/////////////////////////////////////////
/// process AUTOflushrep
if(seled_head[9:5]==ATflurep_cmd&&(m_state_out[5:4]==2'b01))
begin
rst_rep_type=1'b1;
rst_req_type=1'b1;
nstate=m_idle;
mem_access_done=1'b1;
en_m_state_in=1'b1;
en_m_data_in=1'b1;
m_state_in=6'b000000;
end
/////////////////////////////////////////
/// process flushrep
if(seled_head[9:5]==flushrep_cmd&&(m_state_out[5:4]==2'b11))
begin
rst_rep_type=1'b1;
rst_req_type=1'b1;
nstate=m_idle;
mem_access_done=1'b1;
en_m_state_in=1'b1;
case(seled_head[4:3])
2'b00:m_state_in=6'b010001;
2'b01:m_state_in=6'b010010;
2'b10:m_state_in=6'b010100;
2'b11:m_state_in=6'b011000;
default:m_state_in=6'b010001;
endcase
end
end
m_gen_shrep:
begin
data_re_out=1'b1;
/////////////////////////////////////
/// gen shrep
if(rep_type_reg==shrep_type&&~rep_local_remote&&d_fsm_state==d_idle)
begin
v_rep_d=1'b1;
// flit_max_rep=4'b1000;
// en_flit_max_rep=1'b1;
msg={temp_rep_head_flit,data_read,32'h00000000};
nstate=m_idle;
mem_access_done=1'b1;
rst_rep_type=1'b1;
rst_req_type=1'b1;
end
if(rep_type_reg==shrep_type&&rep_local_remote&&m_rep_fsm_state==m_rep_idle)
begin
v_rep_out=1'b1;
flit_max_rep=4'b1000;
en_flit_max_rep=1'b1;
msg={temp_rep_head_flit,data_read,32'h00000000};
nstate=m_idle;
mem_access_done=1'b1;
rst_rep_type=1'b1;
rst_req_type=1'b1;
end
/////////////////////////////////////
/// gen nackrep
if(rep_type_reg==nackrep_type&&~rep_local_remote&&d_fsm_state==d_idle)
begin
v_rep_d=1'b1;
// flit_max_rep=4'b0000;
// en_flit_max_rep=1'b1;
msg={temp_rep_head_flit,data_read,32'h00000000};
nstate=m_idle;
mem_access_done=1'b1;
rst_rep_type=1'b1;
rst_req_type=1'b1;
end
if(rep_type_reg==nackrep_type&&rep_local_remote&&m_rep_fsm_state==m_rep_idle)
begin
v_rep_out=1'b1;
flit_max_rep=4'b0000;
en_flit_max_rep=1'b1;
msg={temp_rep_head_flit,data_read,32'h00000000};
nstate=m_idle;
mem_access_done=1'b1;
rst_rep_type=1'b1;
rst_req_type=1'b1;
end
//////////////////////////////////////
/// gen wbreq
if(req_type_reg==wbreq_type&&~req_local_remote&&d_fsm_state==d_idle)
begin
v_req_d=1'b1;
// flit_max_req=4'b0010;
// en_flit_max_req=1'b1;
msg={temp_rep_head_flit,seled_addr,128'h0000};
nstate=m_idle;
mem_access_done=1'b1;
rst_rep_type=1'b1;
rst_req_type=1'b1;
end
if(req_type_reg==wbreq_type&&req_local_remote&&m_req_fsm_state==m_req_idle)
begin
v_req_out=1'b1;
flit_max_req=4'b0010;
en_flit_max_req=1'b1;
msg={temp_req_head_flit,seled_addr,128'h0000};
nstate=m_idle;
mem_access_done=1'b1;
rst_rep_type=1'b1;
rst_req_type=1'b1;
end
///////////////////////////////////////
/// gen instrep
if(rep_type_reg==instrep_type&&~rep_local_remote&&i_fsm_state==i_idle)
begin
v_rep_Icache=1'b1;
// flit_max_rep=4'b1000;
// en_flit_max_rep=1'b1;
msg={temp_rep_head_flit,data_read,32'h00000000};
nstate=m_idle;
mem_access_done=1'b1;
rst_rep_type=1'b1;
rst_req_type=1'b1;
end
if(rep_type_reg==instrep_type&&rep_local_remote&&m_rep_fsm_state==m_rep_idle)
begin
v_rep_out=1'b1;
flit_max_rep=4'b1000;
en_flit_max_rep=1'b1;
msg={temp_rep_head_flit,data_read,32'h00000000};
nstate=m_idle;
mem_access_done=1'b1;
rst_rep_type=1'b1;
rst_req_type=1'b1;
end
end
m_gen_exrep:
begin
//////////////////////////////////////////
//// gen exrep
if(oneORmore==1'b0)
begin
if(rep_type_reg==exrep_type&&~rep_local_remote&&d_fsm_state==d_idle)
begin
v_rep_d=1'b1;
// flit_max_rep=4'b1000;
// en_flit_max_rep=1'b1;
msg={temp_rep_head_flit,data_read,32'h00000000};
nstate=m_idle;
mem_access_done=1'b1;
rst_rep_type=1'b1;
rst_req_type=1'b1;
end
if(rep_type_reg==exrep_type&&rep_local_remote&&m_rep_fsm_state==m_rep_idle)
begin
v_rep_out=1'b1;
flit_max_rep=4'b1000;
en_flit_max_rep=1'b1;
msg={temp_rep_head_flit,data_read,32'h00000000};
nstate=m_idle;
mem_access_done=1'b1;
rst_rep_type=1'b1;
rst_req_type=1'b1;
end
/////////////////////////////////////
/// gen nackrep
if(rep_type_reg==nackrep_type&&~rep_local_remote&&d_fsm_state==d_idle)
begin
v_rep_d=1'b1;
// flit_max_rep=4'b0000;
// en_flit_max_rep=1'b1;
msg={temp_rep_head_flit,data_read,32'h00000000};
nstate=m_idle;
mem_access_done=1'b1;
rst_rep_type=1'b1;
rst_req_type=1'b1;
end
if(rep_type_reg==nackrep_type&&rep_local_remote&&m_rep_fsm_state==m_rep_idle)
begin
v_rep_out=1'b1;
flit_max_rep=4'b0000;
en_flit_max_rep=1'b1;
msg={temp_rep_head_flit,data_read,32'h00000000};
nstate=m_idle;
mem_access_done=1'b1;
rst_rep_type=1'b1;
rst_req_type=1'b1;
end
////////////////////////////////////////////////
/// gen flushreq
if(req_type_reg==flushreq_type&&~req_local_remote&&d_fsm_state==d_idle)
begin
v_req_d=1'b1;
// flit_max_req=4'b0010;
// en_flit_max_req=1'b1;
msg={temp_req_head_flit,seled_addr,128'h0000};
nstate=m_idle;
mem_access_done=1'b1;
rst_rep_type=1'b1;
rst_req_type=1'b1;
end
if(req_type_reg==flushreq_type&&req_local_remote&&m_req_fsm_state==m_req_idle)
begin
v_req_out=1'b1;
flit_max_req=4'b0010;
en_flit_max_req=1'b1;
msg={temp_req_head_flit,seled_addr,128'h0000};
nstate=m_idle;
mem_access_done=1'b1;
rst_rep_type=1'b1;
rst_req_type=1'b1;
end
//////////////////////////////////////////////////
/// gen SCflushrep
if(rep_type_reg==SCflurep_type&&~rep_local_remote&&d_fsm_state==d_idle)
begin
v_rep_d=1'b1;
// flit_max_rep=4'b0000;
// en_flit_max_rep=1'b1;
msg={temp_rep_head_flit,data_read,32'h00000000};
nstate=m_idle;
mem_access_done=1'b1;
rst_rep_type=1'b1;
rst_req_type=1'b1;
end
if(rep_type_reg==SCflurep_type&&rep_local_remote&&m_rep_fsm_state==m_rep_idle)
begin
v_rep_out=1'b1;
flit_max_rep=4'b0000;
en_flit_max_rep=1'b1;
msg={temp_rep_head_flit,data_read,32'h00000000};
nstate=m_idle;
mem_access_done=1'b1;
rst_rep_type=1'b1;
rst_req_type=1'b1;
end
end
if(oneORmore==1'b1)
begin
//////////////////////////////////////////////////
/// gen SHexrep
if(rep_type_reg==SHexrep_type&&~rep_local_remote&&d_fsm_state==d_idle)
begin
v_rep_d=1'b1;
// flit_max_rep=4'b1000;
// en_flit_max_rep=1'b1;
msg={temp_rep_head_flit,data_read,32'h00000000};
set_rep_done=1'b1;
end
if(rep_type_reg==SHexrep_type&&rep_local_remote&&m_rep_fsm_state==m_rep_idle)
begin
v_rep_out=1'b1;
flit_max_rep=4'b1000;
en_flit_max_rep=1'b1;
msg={temp_rep_head_flit,data_read,32'h00000000};
set_rep_done=1'b1;
end
////////////////////////////////////////////////////
/// gen SCinvreq or invreq
if((req_type_reg==invreq_type||req_type_reg==SCinvreq_type)&&~req_local_remote&&d_fsm_state==d_idle)
begin
/* if(req_type==invreq_type)
thead[4:0]=invreq_cmd;
else
thead[4:0]=SCinvreq_cmd;
*/ ///
// flit_max=4'b0010;
// en_flit_max=1'b1;
v_req_d=1'b1;
msg={temp_req_head_flit,seled_addr,128'h0000};
set_req_done=1'b1;
end
if((req_type_reg==invreq_type||req_type_reg==SCinvreq_type)&&req_local_remote&&m_req_fsm_state==m_req_idle)
begin
/* if(req_type==invreq_type)
thead[4:0]=invreq_cmd;
else
thead[4:0]=SCinvreq_cmd;
*/ ///
flit_max_req=4'b0010;
en_flit_max_req=1'b1;
v_req_out=1'b1;
msg={temp_req_head_flit,seled_addr,128'h0000};
set_req_done=1'b1;
end
if(rep_done&&req_done||set_rep_done&&req_done||rep_done&&set_req_done)
begin
nstate=m_idle;
mem_access_done=1'b1;
rst_rep_type=1'b1;
rst_req_type=1'b1;
end
end
end
endcase
end
// fsm_memory_ctrl
always@(posedge clk)
begin
if(rst)
rstate<=m_idle;
else
rstate<=nstate;
end
always@(posedge clk)
begin
if(rst)
req_done<=1'b0;
else if(set_req_done)
req_done<=1'b1;
end
always@(posedge clk)
begin
if(rst)
rep_done<=1'b0;
else if(set_rep_done)
rep_done<=1'b1;
end
always@(posedge clk)
begin
if(rst||rst_rep_type)
rep_type_reg<=4'b0000;
else if(en_rep_type)
rep_type_reg<=rep_type;
end
always@(posedge clk)
begin
if(rst||rst_req_type)
req_type_reg<=4'b0000;
else if(en_req_type)
req_type_reg<=req_type;
end
assign temp_req_head_flit_in1=t_req_head_sel?temp_req_head_flit_in:seled_head;
assign temp_rep_head_flit_in1=t_rep_head_sel?temp_rep_head_flit_in:seled_head;
always@(posedge clk)
begin
if(rst)
temp_req_head_flit<=16'h0000;
else if(en_temp_req_head_flit)
temp_req_head_flit<=temp_req_head_flit_in1;
end
always@(posedge clk)
begin
if(rst)
temp_rep_head_flit<=16'h0000;
else if(en_temp_rep_head_flit)
temp_rep_head_flit<=temp_rep_head_flit_in1;
end
assign seled_data=data_sel?infifos_data_in:local_d_data_in;
wire [127:0] data_out_mem_ram;
wire [5:0] state_out_mem_ram;
assign state_we_out=en_m_state_in;
assign data_we_out=en_m_data_in;
assign state_out_mem_ram=m_state_in;
assign data_out_mem_ram=seled_data;
// assign output to local inst cache or local data cache or mem_rep_out fifo or mem_rep_out fifo
// output to local data cache
assign {head_out_local_d,addr_out_local_d,data_out_local_d}=msg;
// output to local inst cache
assign data_out_local_i=msg[159:32];
// output to mem_OUT rep fifo
assign {head_out_rep_out,addr_out_rep_out,data_out_rep_out}=msg;
// output to mem_OUT req fifo
assign {head_out_req_out,addr_out_req_out}=msg[175:128]; // msg[127:0] is useless for req msg
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFRTP_2_V
`define SKY130_FD_SC_LP__DFRTP_2_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog wrapper for dfrtp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfrtp_2 (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfrtp_2 (
Q ,
CLK ,
D ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFRTP_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O221A_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__O221A_PP_SYMBOL_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o221a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
input C1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O221A_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A41OI_1_V
`define SKY130_FD_SC_HS__A41OI_1_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog wrapper for a41oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a41oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a41oi_1 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a41oi_1 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A41OI_1_V
|
///////////////////////////////////////////////////////////////////
// File: video_input.v
// Author: B. Brown (all modules are from Terasic DE2-115 TV demo)
// About: Top-level module for the video decoding pipeline.
///////////////////////////////////////////////////////////////////
module video_input
(
input wire aresetn,
// TV Decoder
input wire TD_CLK27,
input wire [7:0] TD_DATA,
input wire TD_HS,
output wire TD_RESET_N,
input wire TD_VS,
// Output Position
output wire [9:0] pos_x,
output wire [9:0] pos_y,
// Output RGB
output wire [9:0] R_out,
output wire [9:0] B_out,
output wire [9:0] G_out,
output wire RGB_valid
);
// ITU-R 656 Decoder
wire [15:0] YCbCr;
wire YCbCr_valid_1;
wire [9:0] decoder_x;
// Down Sample
wire [3:0] Remain;
wire [9:0] Quotient;
// YUV 4:2:2 to YUV 4:4:4
wire [7:0] mY;
wire [7:0] mCb;
wire [7:0] mCr;
wire YCbCr_valid_2;
// TV Decoder Turned On
assign TD_RESET_N = 1'b1;
// Position Output
assign pos_x = decoder_x;
// ITU-R 656 to YUV 4:2:2
ITU_656_Decoder u4
(
.iCLK_27 (TD_CLK27),
.iRST_N (aresetn),
.iTD_DATA (TD_DATA),
.iSwap_CbCr (Quotient[0]),
.iSkip (Remain==4'h0),
.oTV_X (decoder_x),
.oTV_Y (pos_y),
.oYCbCr (YCbCr),
.oDVAL (YCbCr_valid_1)
);
// Divide Megafuncion (Used to Down Sample)
DIV u5
(
.clock (TD_CLK27),
.aclr (~aresetn),
.numer (decoder_x),
.denom (4'h9), // 720 - 640 = 80, 720/80 = 9. Skip a sample once every 9 pixels.
.quotient (Quotient),
.remain (Remain)
);
// YUV 4:2:2 to YUV 4:4:4
yuv422_to_yuv444 u7
(
.iCLK (TD_CLK27),
.iRST_N (aresetn),
.iYCbCr (YCbCr),
.iYCbCr_valid (YCbCr_valid_1),
.oY (mY),
.oCb (mCb),
.oCr (mCr),
.oYCbCr_valid (YCbCr_valid_2)
);
// YCbCr 8-bit to RGB-10 bit
YCbCr2RGB u8
(
.iCLK (TD_CLK27),
.iRESET (~aresetn),
.iY (mY),
.iCb (mCb),
.iCr (mCr),
.iDVAL (YCbCr_valid_2),
.Red (R_out),
.Green (G_out),
.Blue (B_out),
.oDVAL (RGB_valid)
);
endmodule
|
//
// scandoubler.v
//
// Copyright (c) 2015 Till Harbaum <[email protected]>
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
// TODO: Delay vsync one line
module mist_scandoubler (
// system interface
input clk, // 31.875 MHz
input clk_16, // from shifter
input clk_16_en,
input scanlines,
// shifter video interface
input hs_in,
input vs_in,
input r_in,
input g_in,
input b_in,
// output interface
output reg hs_out,
output reg vs_out,
output reg [1:0] r_out,
output reg [1:0] g_out,
output reg [1:0] b_out,
output is15k
);
// scan doubler output register
reg [2:0] sd_out;
// --------------------- create output signals -----------------
// latch everything once more to make it glitch free and apply scanline effect
reg scanline;
always @(posedge clk) begin
hs_out <= hs_sd;
vs_out <= vs_in;
// reset scanlines at every new screen
if(vs_out != vs_in)
scanline <= 1'b0;
// toggle scanlines at begin of every hsync
if(hs_out && !hs_sd)
scanline <= !scanline;
// if no scanlines or not a scanline
if(!scanlines || !scanline) begin
r_out <= { sd_out[2], sd_out[2] };
g_out <= { sd_out[1], sd_out[1] };
b_out <= { sd_out[0], sd_out[0] };
end else begin
r_out <= { 1'b0, sd_out[2] };
g_out <= { 1'b0, sd_out[1] };
b_out <= { 1'b0, sd_out[0] };
end
end
// ==================================================================
// ======================== the line buffers ========================
// ==================================================================
// 2 lines of 1024 pixels 3*4 bit RGB
reg [2:0] sd_buffer [2047:0];
// use alternating sd_buffers when storing/reading data
reg vsD;
reg line_toggle;
always @(negedge clk_16) begin
if (clk_16_en) begin
vsD <= vs_in;
if(vsD != vs_in)
line_toggle <= 1'b0;
// begin of incoming hsync
if(hsD && !hs_in)
line_toggle <= !line_toggle;
end
end
always @(negedge clk_16) begin
if (clk_16_en) begin
sd_buffer[{line_toggle, hcnt}] <= { r_in, g_in, b_in };
end
end
// ==================================================================
// =================== horizontal timing analysis ===================
// ==================================================================
// signal detection of 15khz if hsync frequency is less than 20KHz
assign is15k = hs_max > (16000000/20000);
// total hsync time (in 16MHz cycles), hs_total reaches 1024
reg [9:0] hs_max;
reg [9:0] hs_rise;
reg [9:0] hcnt;
reg hsD;
always @(negedge clk_16) begin
if (clk_16_en) begin
hsD <= hs_in;
// falling edge of hsync indicates start of line
if(hsD && !hs_in) begin
hs_max <= hcnt;
hcnt <= 10'd0;
end else
hcnt <= hcnt + 10'd1;
// save position of rising edge
if(!hsD && hs_in)
hs_rise <= hcnt;
end
end
// ==================================================================
// ==================== output timing generation ====================
// ==================================================================
reg [9:0] sd_hcnt;
reg hs_sd;
// timing generation runs 32 MHz (twice the input signal analysis speed)
always @(posedge clk) begin
// output counter synchronous to input and at twice the rate
sd_hcnt <= sd_hcnt + 10'd1;
if(hsD && !hs_in) sd_hcnt <= hs_max;
if(sd_hcnt == hs_max) sd_hcnt <= 10'd0;
// replicate horizontal sync at twice the speed
if(sd_hcnt == hs_max) hs_sd <= 1'b0;
if(sd_hcnt == hs_rise) hs_sd <= 1'b1;
// read data from line sd_buffer
sd_out <= sd_buffer[{~line_toggle, sd_hcnt}];
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module dmac_response_generator #(
parameter ID_WIDTH = 3)(
input clk,
input resetn,
input enable,
output reg enabled,
input [ID_WIDTH-1:0] request_id,
output reg [ID_WIDTH-1:0] response_id,
input eot,
output resp_valid,
input resp_ready,
output resp_eot,
output [1:0] resp_resp
);
`include "inc_id.vh"
`include "resp.vh"
assign resp_resp = RESP_OKAY;
assign resp_eot = eot;
assign resp_valid = request_id != response_id && enabled;
// We have to wait for all responses before we can disable the response handler
always @(posedge clk) begin
if (resetn == 1'b0) begin
enabled <= 1'b0;
end else if (enable == 1'b1) begin
enabled <= 1'b1;
end else if (request_id == response_id) begin
enabled <= 1'b0;
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
response_id <= 'h0;
end else if (resp_valid == 1'b1 && resp_ready == 1'b1) begin
response_id <= inc_id(response_id);
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O32A_M_V
`define SKY130_FD_SC_LP__O32A_M_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32a with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o32a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o32a_m (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o32a_m (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O32A_M_V
|
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
// On Tue Jan 22 07:33:07 EST 2013
//
//
// Ports:
// Name I/O size props
// wciS0_SResp O 2 reg
// wciS0_SData O 32 reg
// wciS0_SThreadBusy O 1
// wciS0_SFlag O 2
// wsiS0_SThreadBusy O 1
// wsiS0_SReset_n O 1
// wsiS1_SThreadBusy O 1
// wsiS1_SReset_n O 1
// wsiM0_MCmd O 3
// wsiM0_MReqLast O 1
// wsiM0_MBurstPrecise O 1
// wsiM0_MBurstLength O 12
// wsiM0_MData O 256 reg
// wsiM0_MByteEn O 32 reg
// wsiM0_MReqInfo O 8
// wsiM0_MReset_n O 1
// wsiM1_MCmd O 3
// wsiM1_MReqLast O 1
// wsiM1_MBurstPrecise O 1
// wsiM1_MBurstLength O 12
// wsiM1_MData O 256 reg
// wsiM1_MByteEn O 32 reg
// wsiM1_MReqInfo O 8
// wsiM1_MReset_n O 1
// wciS0_Clk I 1 clock
// wciS0_MReset_n I 1 reset
// wciS0_MCmd I 3
// wciS0_MAddrSpace I 1
// wciS0_MByteEn I 4
// wciS0_MAddr I 32
// wciS0_MData I 32
// wciS0_MFlag I 2 unused
// wsiS0_MCmd I 3
// wsiS0_MBurstLength I 12
// wsiS0_MData I 256
// wsiS0_MByteEn I 32
// wsiS0_MReqInfo I 8
// wsiS1_MCmd I 3
// wsiS1_MBurstLength I 12
// wsiS1_MData I 256
// wsiS1_MByteEn I 32
// wsiS1_MReqInfo I 8
// wsiS0_MReqLast I 1
// wsiS0_MBurstPrecise I 1
// wsiS0_MReset_n I 1 reg
// wsiS1_MReqLast I 1
// wsiS1_MBurstPrecise I 1
// wsiS1_MReset_n I 1 reg
// wsiM0_SThreadBusy I 1 reg
// wsiM0_SReset_n I 1 reg
// wsiM1_SThreadBusy I 1 reg
// wsiM1_SReset_n I 1 reg
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkWsiSplitter2x232B(wciS0_Clk,
wciS0_MReset_n,
wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData,
wciS0_SResp,
wciS0_SData,
wciS0_SThreadBusy,
wciS0_SFlag,
wciS0_MFlag,
wsiS0_MCmd,
wsiS0_MReqLast,
wsiS0_MBurstPrecise,
wsiS0_MBurstLength,
wsiS0_MData,
wsiS0_MByteEn,
wsiS0_MReqInfo,
wsiS0_SThreadBusy,
wsiS0_SReset_n,
wsiS0_MReset_n,
wsiS1_MCmd,
wsiS1_MReqLast,
wsiS1_MBurstPrecise,
wsiS1_MBurstLength,
wsiS1_MData,
wsiS1_MByteEn,
wsiS1_MReqInfo,
wsiS1_SThreadBusy,
wsiS1_SReset_n,
wsiS1_MReset_n,
wsiM0_MCmd,
wsiM0_MReqLast,
wsiM0_MBurstPrecise,
wsiM0_MBurstLength,
wsiM0_MData,
wsiM0_MByteEn,
wsiM0_MReqInfo,
wsiM0_SThreadBusy,
wsiM0_MReset_n,
wsiM0_SReset_n,
wsiM1_MCmd,
wsiM1_MReqLast,
wsiM1_MBurstPrecise,
wsiM1_MBurstLength,
wsiM1_MData,
wsiM1_MByteEn,
wsiM1_MReqInfo,
wsiM1_SThreadBusy,
wsiM1_MReset_n,
wsiM1_SReset_n);
parameter [31 : 0] ctrlInit = 32'b0;
parameter [0 : 0] hasDebugLogic = 1'b0;
input wciS0_Clk;
input wciS0_MReset_n;
// action method wciS0_mCmd
input [2 : 0] wciS0_MCmd;
// action method wciS0_mAddrSpace
input wciS0_MAddrSpace;
// action method wciS0_mByteEn
input [3 : 0] wciS0_MByteEn;
// action method wciS0_mAddr
input [31 : 0] wciS0_MAddr;
// action method wciS0_mData
input [31 : 0] wciS0_MData;
// value method wciS0_sResp
output [1 : 0] wciS0_SResp;
// value method wciS0_sData
output [31 : 0] wciS0_SData;
// value method wciS0_sThreadBusy
output wciS0_SThreadBusy;
// value method wciS0_sFlag
output [1 : 0] wciS0_SFlag;
// action method wciS0_mFlag
input [1 : 0] wciS0_MFlag;
// action method wsiS0_mCmd
input [2 : 0] wsiS0_MCmd;
// action method wsiS0_mReqLast
input wsiS0_MReqLast;
// action method wsiS0_mBurstPrecise
input wsiS0_MBurstPrecise;
// action method wsiS0_mBurstLength
input [11 : 0] wsiS0_MBurstLength;
// action method wsiS0_mData
input [255 : 0] wsiS0_MData;
// action method wsiS0_mByteEn
input [31 : 0] wsiS0_MByteEn;
// action method wsiS0_mReqInfo
input [7 : 0] wsiS0_MReqInfo;
// action method wsiS0_mDataInfo
// value method wsiS0_sThreadBusy
output wsiS0_SThreadBusy;
// value method wsiS0_sReset_n
output wsiS0_SReset_n;
// action method wsiS0_mReset_n
input wsiS0_MReset_n;
// action method wsiS1_mCmd
input [2 : 0] wsiS1_MCmd;
// action method wsiS1_mReqLast
input wsiS1_MReqLast;
// action method wsiS1_mBurstPrecise
input wsiS1_MBurstPrecise;
// action method wsiS1_mBurstLength
input [11 : 0] wsiS1_MBurstLength;
// action method wsiS1_mData
input [255 : 0] wsiS1_MData;
// action method wsiS1_mByteEn
input [31 : 0] wsiS1_MByteEn;
// action method wsiS1_mReqInfo
input [7 : 0] wsiS1_MReqInfo;
// action method wsiS1_mDataInfo
// value method wsiS1_sThreadBusy
output wsiS1_SThreadBusy;
// value method wsiS1_sReset_n
output wsiS1_SReset_n;
// action method wsiS1_mReset_n
input wsiS1_MReset_n;
// value method wsiM0_mCmd
output [2 : 0] wsiM0_MCmd;
// value method wsiM0_mReqLast
output wsiM0_MReqLast;
// value method wsiM0_mBurstPrecise
output wsiM0_MBurstPrecise;
// value method wsiM0_mBurstLength
output [11 : 0] wsiM0_MBurstLength;
// value method wsiM0_mData
output [255 : 0] wsiM0_MData;
// value method wsiM0_mByteEn
output [31 : 0] wsiM0_MByteEn;
// value method wsiM0_mReqInfo
output [7 : 0] wsiM0_MReqInfo;
// value method wsiM0_mDataInfo
// action method wsiM0_sThreadBusy
input wsiM0_SThreadBusy;
// value method wsiM0_mReset_n
output wsiM0_MReset_n;
// action method wsiM0_sReset_n
input wsiM0_SReset_n;
// value method wsiM1_mCmd
output [2 : 0] wsiM1_MCmd;
// value method wsiM1_mReqLast
output wsiM1_MReqLast;
// value method wsiM1_mBurstPrecise
output wsiM1_MBurstPrecise;
// value method wsiM1_mBurstLength
output [11 : 0] wsiM1_MBurstLength;
// value method wsiM1_mData
output [255 : 0] wsiM1_MData;
// value method wsiM1_mByteEn
output [31 : 0] wsiM1_MByteEn;
// value method wsiM1_mReqInfo
output [7 : 0] wsiM1_MReqInfo;
// value method wsiM1_mDataInfo
// action method wsiM1_sThreadBusy
input wsiM1_SThreadBusy;
// value method wsiM1_mReset_n
output wsiM1_MReset_n;
// action method wsiM1_sReset_n
input wsiM1_SReset_n;
// signals for module outputs
wire [255 : 0] wsiM0_MData, wsiM1_MData;
wire [31 : 0] wciS0_SData, wsiM0_MByteEn, wsiM1_MByteEn;
wire [11 : 0] wsiM0_MBurstLength, wsiM1_MBurstLength;
wire [7 : 0] wsiM0_MReqInfo, wsiM1_MReqInfo;
wire [2 : 0] wsiM0_MCmd, wsiM1_MCmd;
wire [1 : 0] wciS0_SFlag, wciS0_SResp;
wire wciS0_SThreadBusy,
wsiM0_MBurstPrecise,
wsiM0_MReqLast,
wsiM0_MReset_n,
wsiM1_MBurstPrecise,
wsiM1_MReqLast,
wsiM1_MReset_n,
wsiS0_SReset_n,
wsiS0_SThreadBusy,
wsiS1_SReset_n,
wsiS1_SThreadBusy;
// inlined wires
wire [312 : 0] wsi_M0_reqFifo_x_wire$wget,
wsi_M1_reqFifo_x_wire$wget,
wsi_S0_wsiReq$wget,
wsi_S1_wsiReq$wget;
wire [255 : 0] wsi_Es0_mData_w$wget, wsi_Es1_mData_w$wget;
wire [95 : 0] wsi_M0_extStatusW$wget,
wsi_M1_extStatusW$wget,
wsi_S0_extStatusW$wget,
wsi_S1_extStatusW$wget;
wire [71 : 0] wci_wciReq$wget;
wire [33 : 0] wci_respF_x_wire$wget;
wire [31 : 0] wci_Es_mAddr_w$wget,
wci_Es_mData_w$wget,
wsi_Es0_mByteEn_w$wget,
wsi_Es1_mByteEn_w$wget;
wire [11 : 0] wsi_Es0_mBurstLength_w$wget, wsi_Es1_mBurstLength_w$wget;
wire [7 : 0] wsi_Es0_mReqInfo_w$wget, wsi_Es1_mReqInfo_w$wget;
wire [3 : 0] wci_Es_mByteEn_w$wget;
wire [2 : 0] wci_Es_mCmd_w$wget,
wci_wEdge$wget,
wsi_Es0_mCmd_w$wget,
wsi_Es1_mCmd_w$wget;
wire wci_Es_mAddrSpace_w$wget,
wci_Es_mAddrSpace_w$whas,
wci_Es_mAddr_w$whas,
wci_Es_mByteEn_w$whas,
wci_Es_mCmd_w$whas,
wci_Es_mData_w$whas,
wci_ctlAckReg_1$wget,
wci_ctlAckReg_1$whas,
wci_reqF_r_clr$whas,
wci_reqF_r_deq$whas,
wci_reqF_r_enq$whas,
wci_respF_dequeueing$whas,
wci_respF_enqueueing$whas,
wci_respF_x_wire$whas,
wci_sFlagReg_1$wget,
wci_sFlagReg_1$whas,
wci_sThreadBusy_pw$whas,
wci_wEdge$whas,
wci_wciReq$whas,
wci_wci_cfrd_pw$whas,
wci_wci_cfwr_pw$whas,
wci_wci_ctrl_pw$whas,
wsi_Es0_mBurstLength_w$whas,
wsi_Es0_mBurstPrecise_w$whas,
wsi_Es0_mByteEn_w$whas,
wsi_Es0_mCmd_w$whas,
wsi_Es0_mDataInfo_w$whas,
wsi_Es0_mData_w$whas,
wsi_Es0_mReqInfo_w$whas,
wsi_Es0_mReqLast_w$whas,
wsi_Es1_mBurstLength_w$whas,
wsi_Es1_mBurstPrecise_w$whas,
wsi_Es1_mByteEn_w$whas,
wsi_Es1_mCmd_w$whas,
wsi_Es1_mDataInfo_w$whas,
wsi_Es1_mData_w$whas,
wsi_Es1_mReqInfo_w$whas,
wsi_Es1_mReqLast_w$whas,
wsi_M0_operateD_1$wget,
wsi_M0_operateD_1$whas,
wsi_M0_peerIsReady_1$wget,
wsi_M0_peerIsReady_1$whas,
wsi_M0_reqFifo_dequeueing$whas,
wsi_M0_reqFifo_enqueueing$whas,
wsi_M0_reqFifo_x_wire$whas,
wsi_M0_sThreadBusy_pw$whas,
wsi_M1_operateD_1$wget,
wsi_M1_operateD_1$whas,
wsi_M1_peerIsReady_1$wget,
wsi_M1_peerIsReady_1$whas,
wsi_M1_reqFifo_dequeueing$whas,
wsi_M1_reqFifo_enqueueing$whas,
wsi_M1_reqFifo_x_wire$whas,
wsi_M1_sThreadBusy_pw$whas,
wsi_S0_operateD_1$wget,
wsi_S0_operateD_1$whas,
wsi_S0_peerIsReady_1$wget,
wsi_S0_peerIsReady_1$whas,
wsi_S0_reqFifo_doResetClr$whas,
wsi_S0_reqFifo_doResetDeq$whas,
wsi_S0_reqFifo_doResetEnq$whas,
wsi_S0_reqFifo_r_clr$whas,
wsi_S0_reqFifo_r_deq$whas,
wsi_S0_reqFifo_r_enq$whas,
wsi_S0_sThreadBusy_dw$wget,
wsi_S0_sThreadBusy_dw$whas,
wsi_S0_wsiReq$whas,
wsi_S1_operateD_1$wget,
wsi_S1_operateD_1$whas,
wsi_S1_peerIsReady_1$wget,
wsi_S1_peerIsReady_1$whas,
wsi_S1_reqFifo_doResetClr$whas,
wsi_S1_reqFifo_doResetDeq$whas,
wsi_S1_reqFifo_doResetEnq$whas,
wsi_S1_reqFifo_r_clr$whas,
wsi_S1_reqFifo_r_deq$whas,
wsi_S1_reqFifo_r_enq$whas,
wsi_S1_sThreadBusy_dw$wget,
wsi_S1_sThreadBusy_dw$whas,
wsi_S1_wsiReq$whas;
// register splitCtrl
reg [31 : 0] splitCtrl;
wire [31 : 0] splitCtrl$D_IN;
wire splitCtrl$EN;
// register wci_cEdge
reg [2 : 0] wci_cEdge;
wire [2 : 0] wci_cEdge$D_IN;
wire wci_cEdge$EN;
// register wci_cState
reg [2 : 0] wci_cState;
wire [2 : 0] wci_cState$D_IN;
wire wci_cState$EN;
// register wci_ctlAckReg
reg wci_ctlAckReg;
wire wci_ctlAckReg$D_IN, wci_ctlAckReg$EN;
// register wci_ctlOpActive
reg wci_ctlOpActive;
wire wci_ctlOpActive$D_IN, wci_ctlOpActive$EN;
// register wci_illegalEdge
reg wci_illegalEdge;
wire wci_illegalEdge$D_IN, wci_illegalEdge$EN;
// register wci_isReset_isInReset
reg wci_isReset_isInReset;
wire wci_isReset_isInReset$D_IN, wci_isReset_isInReset$EN;
// register wci_nState
reg [2 : 0] wci_nState;
reg [2 : 0] wci_nState$D_IN;
wire wci_nState$EN;
// register wci_reqF_countReg
reg [1 : 0] wci_reqF_countReg;
wire [1 : 0] wci_reqF_countReg$D_IN;
wire wci_reqF_countReg$EN;
// register wci_respF_c_r
reg [1 : 0] wci_respF_c_r;
wire [1 : 0] wci_respF_c_r$D_IN;
wire wci_respF_c_r$EN;
// register wci_respF_q_0
reg [33 : 0] wci_respF_q_0;
reg [33 : 0] wci_respF_q_0$D_IN;
wire wci_respF_q_0$EN;
// register wci_respF_q_1
reg [33 : 0] wci_respF_q_1;
reg [33 : 0] wci_respF_q_1$D_IN;
wire wci_respF_q_1$EN;
// register wci_sFlagReg
reg wci_sFlagReg;
wire wci_sFlagReg$D_IN, wci_sFlagReg$EN;
// register wci_sThreadBusy_d
reg wci_sThreadBusy_d;
wire wci_sThreadBusy_d$D_IN, wci_sThreadBusy_d$EN;
// register wsi_M0_burstKind
reg [1 : 0] wsi_M0_burstKind;
wire [1 : 0] wsi_M0_burstKind$D_IN;
wire wsi_M0_burstKind$EN;
// register wsi_M0_errorSticky
reg wsi_M0_errorSticky;
wire wsi_M0_errorSticky$D_IN, wsi_M0_errorSticky$EN;
// register wsi_M0_iMesgCount
reg [31 : 0] wsi_M0_iMesgCount;
wire [31 : 0] wsi_M0_iMesgCount$D_IN;
wire wsi_M0_iMesgCount$EN;
// register wsi_M0_isReset_isInReset
reg wsi_M0_isReset_isInReset;
wire wsi_M0_isReset_isInReset$D_IN, wsi_M0_isReset_isInReset$EN;
// register wsi_M0_operateD
reg wsi_M0_operateD;
wire wsi_M0_operateD$D_IN, wsi_M0_operateD$EN;
// register wsi_M0_pMesgCount
reg [31 : 0] wsi_M0_pMesgCount;
wire [31 : 0] wsi_M0_pMesgCount$D_IN;
wire wsi_M0_pMesgCount$EN;
// register wsi_M0_peerIsReady
reg wsi_M0_peerIsReady;
wire wsi_M0_peerIsReady$D_IN, wsi_M0_peerIsReady$EN;
// register wsi_M0_reqFifo_c_r
reg [1 : 0] wsi_M0_reqFifo_c_r;
wire [1 : 0] wsi_M0_reqFifo_c_r$D_IN;
wire wsi_M0_reqFifo_c_r$EN;
// register wsi_M0_reqFifo_q_0
reg [312 : 0] wsi_M0_reqFifo_q_0;
reg [312 : 0] wsi_M0_reqFifo_q_0$D_IN;
wire wsi_M0_reqFifo_q_0$EN;
// register wsi_M0_reqFifo_q_1
reg [312 : 0] wsi_M0_reqFifo_q_1;
reg [312 : 0] wsi_M0_reqFifo_q_1$D_IN;
wire wsi_M0_reqFifo_q_1$EN;
// register wsi_M0_sThreadBusy_d
reg wsi_M0_sThreadBusy_d;
wire wsi_M0_sThreadBusy_d$D_IN, wsi_M0_sThreadBusy_d$EN;
// register wsi_M0_statusR
reg [7 : 0] wsi_M0_statusR;
wire [7 : 0] wsi_M0_statusR$D_IN;
wire wsi_M0_statusR$EN;
// register wsi_M0_tBusyCount
reg [31 : 0] wsi_M0_tBusyCount;
wire [31 : 0] wsi_M0_tBusyCount$D_IN;
wire wsi_M0_tBusyCount$EN;
// register wsi_M0_trafficSticky
reg wsi_M0_trafficSticky;
wire wsi_M0_trafficSticky$D_IN, wsi_M0_trafficSticky$EN;
// register wsi_M1_burstKind
reg [1 : 0] wsi_M1_burstKind;
wire [1 : 0] wsi_M1_burstKind$D_IN;
wire wsi_M1_burstKind$EN;
// register wsi_M1_errorSticky
reg wsi_M1_errorSticky;
wire wsi_M1_errorSticky$D_IN, wsi_M1_errorSticky$EN;
// register wsi_M1_iMesgCount
reg [31 : 0] wsi_M1_iMesgCount;
wire [31 : 0] wsi_M1_iMesgCount$D_IN;
wire wsi_M1_iMesgCount$EN;
// register wsi_M1_isReset_isInReset
reg wsi_M1_isReset_isInReset;
wire wsi_M1_isReset_isInReset$D_IN, wsi_M1_isReset_isInReset$EN;
// register wsi_M1_operateD
reg wsi_M1_operateD;
wire wsi_M1_operateD$D_IN, wsi_M1_operateD$EN;
// register wsi_M1_pMesgCount
reg [31 : 0] wsi_M1_pMesgCount;
wire [31 : 0] wsi_M1_pMesgCount$D_IN;
wire wsi_M1_pMesgCount$EN;
// register wsi_M1_peerIsReady
reg wsi_M1_peerIsReady;
wire wsi_M1_peerIsReady$D_IN, wsi_M1_peerIsReady$EN;
// register wsi_M1_reqFifo_c_r
reg [1 : 0] wsi_M1_reqFifo_c_r;
wire [1 : 0] wsi_M1_reqFifo_c_r$D_IN;
wire wsi_M1_reqFifo_c_r$EN;
// register wsi_M1_reqFifo_q_0
reg [312 : 0] wsi_M1_reqFifo_q_0;
reg [312 : 0] wsi_M1_reqFifo_q_0$D_IN;
wire wsi_M1_reqFifo_q_0$EN;
// register wsi_M1_reqFifo_q_1
reg [312 : 0] wsi_M1_reqFifo_q_1;
reg [312 : 0] wsi_M1_reqFifo_q_1$D_IN;
wire wsi_M1_reqFifo_q_1$EN;
// register wsi_M1_sThreadBusy_d
reg wsi_M1_sThreadBusy_d;
wire wsi_M1_sThreadBusy_d$D_IN, wsi_M1_sThreadBusy_d$EN;
// register wsi_M1_statusR
reg [7 : 0] wsi_M1_statusR;
wire [7 : 0] wsi_M1_statusR$D_IN;
wire wsi_M1_statusR$EN;
// register wsi_M1_tBusyCount
reg [31 : 0] wsi_M1_tBusyCount;
wire [31 : 0] wsi_M1_tBusyCount$D_IN;
wire wsi_M1_tBusyCount$EN;
// register wsi_M1_trafficSticky
reg wsi_M1_trafficSticky;
wire wsi_M1_trafficSticky$D_IN, wsi_M1_trafficSticky$EN;
// register wsi_S0_burstKind
reg [1 : 0] wsi_S0_burstKind;
wire [1 : 0] wsi_S0_burstKind$D_IN;
wire wsi_S0_burstKind$EN;
// register wsi_S0_errorSticky
reg wsi_S0_errorSticky;
wire wsi_S0_errorSticky$D_IN, wsi_S0_errorSticky$EN;
// register wsi_S0_iMesgCount
reg [31 : 0] wsi_S0_iMesgCount;
wire [31 : 0] wsi_S0_iMesgCount$D_IN;
wire wsi_S0_iMesgCount$EN;
// register wsi_S0_isReset_isInReset
reg wsi_S0_isReset_isInReset;
wire wsi_S0_isReset_isInReset$D_IN, wsi_S0_isReset_isInReset$EN;
// register wsi_S0_mesgWordLength
reg [11 : 0] wsi_S0_mesgWordLength;
wire [11 : 0] wsi_S0_mesgWordLength$D_IN;
wire wsi_S0_mesgWordLength$EN;
// register wsi_S0_operateD
reg wsi_S0_operateD;
wire wsi_S0_operateD$D_IN, wsi_S0_operateD$EN;
// register wsi_S0_pMesgCount
reg [31 : 0] wsi_S0_pMesgCount;
wire [31 : 0] wsi_S0_pMesgCount$D_IN;
wire wsi_S0_pMesgCount$EN;
// register wsi_S0_peerIsReady
reg wsi_S0_peerIsReady;
wire wsi_S0_peerIsReady$D_IN, wsi_S0_peerIsReady$EN;
// register wsi_S0_reqFifo_countReg
reg [1 : 0] wsi_S0_reqFifo_countReg;
wire [1 : 0] wsi_S0_reqFifo_countReg$D_IN;
wire wsi_S0_reqFifo_countReg$EN;
// register wsi_S0_reqFifo_levelsValid
reg wsi_S0_reqFifo_levelsValid;
wire wsi_S0_reqFifo_levelsValid$D_IN, wsi_S0_reqFifo_levelsValid$EN;
// register wsi_S0_statusR
reg [7 : 0] wsi_S0_statusR;
wire [7 : 0] wsi_S0_statusR$D_IN;
wire wsi_S0_statusR$EN;
// register wsi_S0_tBusyCount
reg [31 : 0] wsi_S0_tBusyCount;
wire [31 : 0] wsi_S0_tBusyCount$D_IN;
wire wsi_S0_tBusyCount$EN;
// register wsi_S0_trafficSticky
reg wsi_S0_trafficSticky;
wire wsi_S0_trafficSticky$D_IN, wsi_S0_trafficSticky$EN;
// register wsi_S0_wordCount
reg [11 : 0] wsi_S0_wordCount;
wire [11 : 0] wsi_S0_wordCount$D_IN;
wire wsi_S0_wordCount$EN;
// register wsi_S1_burstKind
reg [1 : 0] wsi_S1_burstKind;
wire [1 : 0] wsi_S1_burstKind$D_IN;
wire wsi_S1_burstKind$EN;
// register wsi_S1_errorSticky
reg wsi_S1_errorSticky;
wire wsi_S1_errorSticky$D_IN, wsi_S1_errorSticky$EN;
// register wsi_S1_iMesgCount
reg [31 : 0] wsi_S1_iMesgCount;
wire [31 : 0] wsi_S1_iMesgCount$D_IN;
wire wsi_S1_iMesgCount$EN;
// register wsi_S1_isReset_isInReset
reg wsi_S1_isReset_isInReset;
wire wsi_S1_isReset_isInReset$D_IN, wsi_S1_isReset_isInReset$EN;
// register wsi_S1_mesgWordLength
reg [11 : 0] wsi_S1_mesgWordLength;
wire [11 : 0] wsi_S1_mesgWordLength$D_IN;
wire wsi_S1_mesgWordLength$EN;
// register wsi_S1_operateD
reg wsi_S1_operateD;
wire wsi_S1_operateD$D_IN, wsi_S1_operateD$EN;
// register wsi_S1_pMesgCount
reg [31 : 0] wsi_S1_pMesgCount;
wire [31 : 0] wsi_S1_pMesgCount$D_IN;
wire wsi_S1_pMesgCount$EN;
// register wsi_S1_peerIsReady
reg wsi_S1_peerIsReady;
wire wsi_S1_peerIsReady$D_IN, wsi_S1_peerIsReady$EN;
// register wsi_S1_reqFifo_countReg
reg [1 : 0] wsi_S1_reqFifo_countReg;
wire [1 : 0] wsi_S1_reqFifo_countReg$D_IN;
wire wsi_S1_reqFifo_countReg$EN;
// register wsi_S1_reqFifo_levelsValid
reg wsi_S1_reqFifo_levelsValid;
wire wsi_S1_reqFifo_levelsValid$D_IN, wsi_S1_reqFifo_levelsValid$EN;
// register wsi_S1_statusR
reg [7 : 0] wsi_S1_statusR;
wire [7 : 0] wsi_S1_statusR$D_IN;
wire wsi_S1_statusR$EN;
// register wsi_S1_tBusyCount
reg [31 : 0] wsi_S1_tBusyCount;
wire [31 : 0] wsi_S1_tBusyCount$D_IN;
wire wsi_S1_tBusyCount$EN;
// register wsi_S1_trafficSticky
reg wsi_S1_trafficSticky;
wire wsi_S1_trafficSticky$D_IN, wsi_S1_trafficSticky$EN;
// register wsi_S1_wordCount
reg [11 : 0] wsi_S1_wordCount;
wire [11 : 0] wsi_S1_wordCount$D_IN;
wire wsi_S1_wordCount$EN;
// ports of submodule wci_reqF
wire [71 : 0] wci_reqF$D_IN, wci_reqF$D_OUT;
wire wci_reqF$CLR, wci_reqF$DEQ, wci_reqF$EMPTY_N, wci_reqF$ENQ;
// ports of submodule wsi_S0_reqFifo
wire [312 : 0] wsi_S0_reqFifo$D_IN, wsi_S0_reqFifo$D_OUT;
wire wsi_S0_reqFifo$CLR,
wsi_S0_reqFifo$DEQ,
wsi_S0_reqFifo$EMPTY_N,
wsi_S0_reqFifo$ENQ,
wsi_S0_reqFifo$FULL_N;
// ports of submodule wsi_S1_reqFifo
wire [312 : 0] wsi_S1_reqFifo$D_IN, wsi_S1_reqFifo$D_OUT;
wire wsi_S1_reqFifo$CLR,
wsi_S1_reqFifo$DEQ,
wsi_S1_reqFifo$EMPTY_N,
wsi_S1_reqFifo$ENQ,
wsi_S1_reqFifo$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_doMessageConsume_S1,
WILL_FIRE_RL_doMessageConsume_S0,
WILL_FIRE_RL_doMessageConsume_S1,
WILL_FIRE_RL_wci_cfrd,
WILL_FIRE_RL_wci_cfwr,
WILL_FIRE_RL_wci_ctl_op_complete,
WILL_FIRE_RL_wci_ctl_op_start,
WILL_FIRE_RL_wci_ctrl_EiI,
WILL_FIRE_RL_wci_ctrl_IsO,
WILL_FIRE_RL_wci_ctrl_OrE,
WILL_FIRE_RL_wci_respF_both,
WILL_FIRE_RL_wci_respF_decCtr,
WILL_FIRE_RL_wci_respF_incCtr,
WILL_FIRE_RL_wsi_M0_reqFifo_both,
WILL_FIRE_RL_wsi_M0_reqFifo_decCtr,
WILL_FIRE_RL_wsi_M0_reqFifo_deq,
WILL_FIRE_RL_wsi_M0_reqFifo_incCtr,
WILL_FIRE_RL_wsi_M1_reqFifo_both,
WILL_FIRE_RL_wsi_M1_reqFifo_decCtr,
WILL_FIRE_RL_wsi_M1_reqFifo_deq,
WILL_FIRE_RL_wsi_M1_reqFifo_incCtr,
WILL_FIRE_RL_wsi_S0_reqFifo_enq,
WILL_FIRE_RL_wsi_S0_reqFifo_reset,
WILL_FIRE_RL_wsi_S1_reqFifo_enq,
WILL_FIRE_RL_wsi_S1_reqFifo_reset;
// inputs to muxes for submodule ports
reg [33 : 0] MUX_wci_respF_q_0$write_1__VAL_2;
wire [312 : 0] MUX_wsi_M0_reqFifo_q_0$write_1__VAL_1,
MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2,
MUX_wsi_M0_reqFifo_q_1$write_1__VAL_1,
MUX_wsi_M1_reqFifo_q_0$write_1__VAL_1,
MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2,
MUX_wsi_M1_reqFifo_q_1$write_1__VAL_1;
wire [33 : 0] MUX_wci_respF_q_0$write_1__VAL_1,
MUX_wci_respF_q_1$write_1__VAL_1,
MUX_wci_respF_x_wire$wset_1__VAL_1,
MUX_wci_respF_x_wire$wset_1__VAL_2;
wire [1 : 0] MUX_wci_respF_c_r$write_1__VAL_1,
MUX_wci_respF_c_r$write_1__VAL_2,
MUX_wsi_M0_reqFifo_c_r$write_1__VAL_1,
MUX_wsi_M0_reqFifo_c_r$write_1__VAL_2,
MUX_wsi_M1_reqFifo_c_r$write_1__VAL_1,
MUX_wsi_M1_reqFifo_c_r$write_1__VAL_2;
wire MUX_wci_illegalEdge$write_1__SEL_1,
MUX_wci_illegalEdge$write_1__VAL_1,
MUX_wci_respF_q_0$write_1__SEL_2,
MUX_wci_respF_q_1$write_1__SEL_2,
MUX_wsi_M0_reqFifo_q_0$write_1__SEL_2,
MUX_wsi_M0_reqFifo_q_1$write_1__SEL_2,
MUX_wsi_M0_reqFifo_x_wire$wset_1__SEL_1,
MUX_wsi_M1_reqFifo_q_0$write_1__SEL_2,
MUX_wsi_M1_reqFifo_q_1$write_1__SEL_2,
MUX_wsi_M1_reqFifo_x_wire$wset_1__SEL_1;
// remaining internal signals
reg [63 : 0] v__h16289, v__h16444, v__h3698, v__h3873, v__h4017;
reg [31 : 0] _theResult____h16428;
wire [31 : 0] rdat__h16512,
rdat__h16701,
rdat__h16715,
rdat__h16723,
rdat__h16737,
rdat__h16745,
rdat__h16759,
rdat__h16767,
rdat__h16781;
// value method wciS0_sResp
assign wciS0_SResp = wci_respF_q_0[33:32] ;
// value method wciS0_sData
assign wciS0_SData = wci_respF_q_0[31:0] ;
// value method wciS0_sThreadBusy
assign wciS0_SThreadBusy =
wci_reqF_countReg > 2'd1 || wci_isReset_isInReset ;
// value method wciS0_sFlag
assign wciS0_SFlag = { 1'd1, wci_sFlagReg } ;
// value method wsiS0_sThreadBusy
assign wsiS0_SThreadBusy =
!wsi_S0_sThreadBusy_dw$whas || wsi_S0_sThreadBusy_dw$wget ;
// value method wsiS0_sReset_n
assign wsiS0_SReset_n = !wsi_S0_isReset_isInReset && wsi_S0_operateD ;
// value method wsiS1_sThreadBusy
assign wsiS1_SThreadBusy =
!wsi_S1_sThreadBusy_dw$whas || wsi_S1_sThreadBusy_dw$wget ;
// value method wsiS1_sReset_n
assign wsiS1_SReset_n = !wsi_S1_isReset_isInReset && wsi_S1_operateD ;
// value method wsiM0_mCmd
assign wsiM0_MCmd =
wsi_M0_sThreadBusy_d ? 3'd0 : wsi_M0_reqFifo_q_0[312:310] ;
// value method wsiM0_mReqLast
assign wsiM0_MReqLast = !wsi_M0_sThreadBusy_d && wsi_M0_reqFifo_q_0[309] ;
// value method wsiM0_mBurstPrecise
assign wsiM0_MBurstPrecise =
!wsi_M0_sThreadBusy_d && wsi_M0_reqFifo_q_0[308] ;
// value method wsiM0_mBurstLength
assign wsiM0_MBurstLength =
wsi_M0_sThreadBusy_d ? 12'd0 : wsi_M0_reqFifo_q_0[307:296] ;
// value method wsiM0_mData
assign wsiM0_MData = wsi_M0_reqFifo_q_0[295:40] ;
// value method wsiM0_mByteEn
assign wsiM0_MByteEn = wsi_M0_reqFifo_q_0[39:8] ;
// value method wsiM0_mReqInfo
assign wsiM0_MReqInfo =
wsi_M0_sThreadBusy_d ? 8'd0 : wsi_M0_reqFifo_q_0[7:0] ;
// value method wsiM0_mReset_n
assign wsiM0_MReset_n = !wsi_M0_isReset_isInReset && wsi_M0_operateD ;
// value method wsiM1_mCmd
assign wsiM1_MCmd =
wsi_M1_sThreadBusy_d ? 3'd0 : wsi_M1_reqFifo_q_0[312:310] ;
// value method wsiM1_mReqLast
assign wsiM1_MReqLast = !wsi_M1_sThreadBusy_d && wsi_M1_reqFifo_q_0[309] ;
// value method wsiM1_mBurstPrecise
assign wsiM1_MBurstPrecise =
!wsi_M1_sThreadBusy_d && wsi_M1_reqFifo_q_0[308] ;
// value method wsiM1_mBurstLength
assign wsiM1_MBurstLength =
wsi_M1_sThreadBusy_d ? 12'd0 : wsi_M1_reqFifo_q_0[307:296] ;
// value method wsiM1_mData
assign wsiM1_MData = wsi_M1_reqFifo_q_0[295:40] ;
// value method wsiM1_mByteEn
assign wsiM1_MByteEn = wsi_M1_reqFifo_q_0[39:8] ;
// value method wsiM1_mReqInfo
assign wsiM1_MReqInfo =
wsi_M1_sThreadBusy_d ? 8'd0 : wsi_M1_reqFifo_q_0[7:0] ;
// value method wsiM1_mReset_n
assign wsiM1_MReset_n = !wsi_M1_isReset_isInReset && wsi_M1_operateD ;
// submodule wci_reqF
SizedFIFO #(.p1width(32'd72),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wci_reqF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wci_reqF$D_IN),
.ENQ(wci_reqF$ENQ),
.DEQ(wci_reqF$DEQ),
.CLR(wci_reqF$CLR),
.D_OUT(wci_reqF$D_OUT),
.FULL_N(),
.EMPTY_N(wci_reqF$EMPTY_N));
// submodule wsi_S0_reqFifo
SizedFIFO #(.p1width(32'd313),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wsi_S0_reqFifo(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wsi_S0_reqFifo$D_IN),
.ENQ(wsi_S0_reqFifo$ENQ),
.DEQ(wsi_S0_reqFifo$DEQ),
.CLR(wsi_S0_reqFifo$CLR),
.D_OUT(wsi_S0_reqFifo$D_OUT),
.FULL_N(wsi_S0_reqFifo$FULL_N),
.EMPTY_N(wsi_S0_reqFifo$EMPTY_N));
// submodule wsi_S1_reqFifo
SizedFIFO #(.p1width(32'd313),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wsi_S1_reqFifo(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wsi_S1_reqFifo$D_IN),
.ENQ(wsi_S1_reqFifo$ENQ),
.DEQ(wsi_S1_reqFifo$DEQ),
.CLR(wsi_S1_reqFifo$CLR),
.D_OUT(wsi_S1_reqFifo$D_OUT),
.FULL_N(wsi_S1_reqFifo$FULL_N),
.EMPTY_N(wsi_S1_reqFifo$EMPTY_N));
// rule RL_wci_ctl_op_start
assign WILL_FIRE_RL_wci_ctl_op_start =
wci_reqF$EMPTY_N && wci_wci_ctrl_pw$whas &&
!WILL_FIRE_RL_wci_ctl_op_complete ;
// rule RL_wci_ctrl_EiI
assign WILL_FIRE_RL_wci_ctrl_EiI =
wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start &&
wci_cState == 3'd0 &&
wci_reqF$D_OUT[36:34] == 3'd0 ;
// rule RL_wci_ctrl_IsO
assign WILL_FIRE_RL_wci_ctrl_IsO =
wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start &&
wci_cState == 3'd1 &&
wci_reqF$D_OUT[36:34] == 3'd1 ;
// rule RL_wci_ctrl_OrE
assign WILL_FIRE_RL_wci_ctrl_OrE =
wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start &&
wci_cState == 3'd2 &&
wci_reqF$D_OUT[36:34] == 3'd3 ;
// rule RL_doMessageConsume_S0
assign WILL_FIRE_RL_doMessageConsume_S0 =
wsi_S0_reqFifo$EMPTY_N &&
(splitCtrl[0] || splitCtrl[7] || wsi_M0_reqFifo_c_r != 2'd2) &&
(splitCtrl[8] || splitCtrl[15] || wsi_M1_reqFifo_c_r != 2'd2) &&
wci_cState == 3'd2 ;
// rule RL_doMessageConsume_S1
assign CAN_FIRE_RL_doMessageConsume_S1 =
wsi_S1_reqFifo$EMPTY_N &&
(!splitCtrl[0] || splitCtrl[7] || wsi_M0_reqFifo_c_r != 2'd2) &&
(!splitCtrl[8] || splitCtrl[15] || wsi_M1_reqFifo_c_r != 2'd2) &&
wci_cState == 3'd2 ;
assign WILL_FIRE_RL_doMessageConsume_S1 =
CAN_FIRE_RL_doMessageConsume_S1 &&
!WILL_FIRE_RL_doMessageConsume_S0 ;
// rule RL_wci_cfwr
assign WILL_FIRE_RL_wci_cfwr =
wci_respF_c_r != 2'd2 && wci_reqF$EMPTY_N &&
wci_wci_cfwr_pw$whas &&
!WILL_FIRE_RL_wci_ctl_op_start &&
!WILL_FIRE_RL_wci_ctl_op_complete ;
// rule RL_wci_ctl_op_complete
assign WILL_FIRE_RL_wci_ctl_op_complete =
wci_respF_c_r != 2'd2 && wci_ctlOpActive && wci_ctlAckReg ;
// rule RL_wsi_M0_reqFifo_deq
assign WILL_FIRE_RL_wsi_M0_reqFifo_deq =
wsi_M0_reqFifo_c_r != 2'd0 && !wsi_M0_sThreadBusy_d ;
// rule RL_wsi_M0_reqFifo_incCtr
assign WILL_FIRE_RL_wsi_M0_reqFifo_incCtr =
((wsi_M0_reqFifo_c_r == 2'd0) ?
wsi_M0_reqFifo_enqueueing$whas :
wsi_M0_reqFifo_c_r != 2'd1 ||
wsi_M0_reqFifo_enqueueing$whas) &&
wsi_M0_reqFifo_enqueueing$whas &&
!WILL_FIRE_RL_wsi_M0_reqFifo_deq ;
// rule RL_wsi_M0_reqFifo_decCtr
assign WILL_FIRE_RL_wsi_M0_reqFifo_decCtr =
WILL_FIRE_RL_wsi_M0_reqFifo_deq &&
!wsi_M0_reqFifo_enqueueing$whas ;
// rule RL_wsi_M0_reqFifo_both
assign WILL_FIRE_RL_wsi_M0_reqFifo_both =
((wsi_M0_reqFifo_c_r == 2'd1) ?
wsi_M0_reqFifo_enqueueing$whas :
wsi_M0_reqFifo_c_r != 2'd2 ||
wsi_M0_reqFifo_enqueueing$whas) &&
WILL_FIRE_RL_wsi_M0_reqFifo_deq &&
wsi_M0_reqFifo_enqueueing$whas ;
// rule RL_wci_cfrd
assign WILL_FIRE_RL_wci_cfrd =
wci_respF_c_r != 2'd2 && wci_reqF$EMPTY_N &&
wci_wci_cfrd_pw$whas &&
!WILL_FIRE_RL_wci_ctl_op_start &&
!WILL_FIRE_RL_wci_ctl_op_complete ;
// rule RL_wci_respF_incCtr
assign WILL_FIRE_RL_wci_respF_incCtr =
((wci_respF_c_r == 2'd0) ?
wci_respF_enqueueing$whas :
wci_respF_c_r != 2'd1 || wci_respF_enqueueing$whas) &&
wci_respF_enqueueing$whas &&
!(wci_respF_c_r != 2'd0) ;
// rule RL_wci_respF_decCtr
assign WILL_FIRE_RL_wci_respF_decCtr =
wci_respF_c_r != 2'd0 && !wci_respF_enqueueing$whas ;
// rule RL_wci_respF_both
assign WILL_FIRE_RL_wci_respF_both =
((wci_respF_c_r == 2'd1) ?
wci_respF_enqueueing$whas :
wci_respF_c_r != 2'd2 || wci_respF_enqueueing$whas) &&
wci_respF_c_r != 2'd0 &&
wci_respF_enqueueing$whas ;
// rule RL_wsi_M1_reqFifo_deq
assign WILL_FIRE_RL_wsi_M1_reqFifo_deq =
wsi_M1_reqFifo_c_r != 2'd0 && !wsi_M1_sThreadBusy_d ;
// rule RL_wsi_M1_reqFifo_incCtr
assign WILL_FIRE_RL_wsi_M1_reqFifo_incCtr =
((wsi_M1_reqFifo_c_r == 2'd0) ?
wsi_M1_reqFifo_enqueueing$whas :
wsi_M1_reqFifo_c_r != 2'd1 ||
wsi_M1_reqFifo_enqueueing$whas) &&
wsi_M1_reqFifo_enqueueing$whas &&
!WILL_FIRE_RL_wsi_M1_reqFifo_deq ;
// rule RL_wsi_M1_reqFifo_decCtr
assign WILL_FIRE_RL_wsi_M1_reqFifo_decCtr =
WILL_FIRE_RL_wsi_M1_reqFifo_deq &&
!wsi_M1_reqFifo_enqueueing$whas ;
// rule RL_wsi_M1_reqFifo_both
assign WILL_FIRE_RL_wsi_M1_reqFifo_both =
((wsi_M1_reqFifo_c_r == 2'd1) ?
wsi_M1_reqFifo_enqueueing$whas :
wsi_M1_reqFifo_c_r != 2'd2 ||
wsi_M1_reqFifo_enqueueing$whas) &&
WILL_FIRE_RL_wsi_M1_reqFifo_deq &&
wsi_M1_reqFifo_enqueueing$whas ;
// rule RL_wsi_S0_reqFifo_enq
assign WILL_FIRE_RL_wsi_S0_reqFifo_enq =
wsi_S0_reqFifo$FULL_N && wsi_S0_operateD && wsi_S0_peerIsReady &&
wsi_S0_wsiReq$wget[312:310] == 3'd1 ;
// rule RL_wsi_S0_reqFifo_reset
assign WILL_FIRE_RL_wsi_S0_reqFifo_reset =
WILL_FIRE_RL_wsi_S0_reqFifo_enq ||
WILL_FIRE_RL_doMessageConsume_S0 ;
// rule RL_wsi_S1_reqFifo_enq
assign WILL_FIRE_RL_wsi_S1_reqFifo_enq =
wsi_S1_reqFifo$FULL_N && wsi_S1_operateD && wsi_S1_peerIsReady &&
wsi_S1_wsiReq$wget[312:310] == 3'd1 ;
// rule RL_wsi_S1_reqFifo_reset
assign WILL_FIRE_RL_wsi_S1_reqFifo_reset =
WILL_FIRE_RL_wsi_S1_reqFifo_enq ||
WILL_FIRE_RL_doMessageConsume_S1 ;
// inputs to muxes for submodule ports
assign MUX_wci_illegalEdge$write_1__SEL_1 =
WILL_FIRE_RL_wci_ctl_op_start &&
(wci_reqF$D_OUT[36:34] == 3'd0 && wci_cState != 3'd0 ||
wci_reqF$D_OUT[36:34] == 3'd1 && wci_cState != 3'd1 &&
wci_cState != 3'd3 ||
wci_reqF$D_OUT[36:34] == 3'd2 && wci_cState != 3'd2 ||
wci_reqF$D_OUT[36:34] == 3'd3 && wci_cState != 3'd3 &&
wci_cState != 3'd2 &&
wci_cState != 3'd1 ||
wci_reqF$D_OUT[36:34] == 3'd4 ||
wci_reqF$D_OUT[36:34] == 3'd5 ||
wci_reqF$D_OUT[36:34] == 3'd6 ||
wci_reqF$D_OUT[36:34] == 3'd7) ;
assign MUX_wci_respF_q_0$write_1__SEL_2 =
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 ;
assign MUX_wci_respF_q_1$write_1__SEL_2 =
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 ;
assign MUX_wsi_M0_reqFifo_q_0$write_1__SEL_2 =
WILL_FIRE_RL_wsi_M0_reqFifo_incCtr &&
wsi_M0_reqFifo_c_r == 2'd0 ;
assign MUX_wsi_M0_reqFifo_q_1$write_1__SEL_2 =
WILL_FIRE_RL_wsi_M0_reqFifo_incCtr &&
wsi_M0_reqFifo_c_r == 2'd1 ;
assign MUX_wsi_M0_reqFifo_x_wire$wset_1__SEL_1 =
WILL_FIRE_RL_doMessageConsume_S0 && !splitCtrl[0] &&
!splitCtrl[7] ;
assign MUX_wsi_M1_reqFifo_q_0$write_1__SEL_2 =
WILL_FIRE_RL_wsi_M1_reqFifo_incCtr &&
wsi_M1_reqFifo_c_r == 2'd0 ;
assign MUX_wsi_M1_reqFifo_q_1$write_1__SEL_2 =
WILL_FIRE_RL_wsi_M1_reqFifo_incCtr &&
wsi_M1_reqFifo_c_r == 2'd1 ;
assign MUX_wsi_M1_reqFifo_x_wire$wset_1__SEL_1 =
WILL_FIRE_RL_doMessageConsume_S0 && !splitCtrl[8] &&
!splitCtrl[15] ;
assign MUX_wci_illegalEdge$write_1__VAL_1 =
wci_reqF$D_OUT[36:34] != 3'd4 && wci_reqF$D_OUT[36:34] != 3'd5 &&
wci_reqF$D_OUT[36:34] != 3'd6 ;
assign MUX_wci_respF_c_r$write_1__VAL_1 = wci_respF_c_r + 2'd1 ;
assign MUX_wci_respF_c_r$write_1__VAL_2 = wci_respF_c_r - 2'd1 ;
assign MUX_wci_respF_q_0$write_1__VAL_1 =
(wci_respF_c_r == 2'd1) ?
MUX_wci_respF_q_0$write_1__VAL_2 :
wci_respF_q_1 ;
always@(WILL_FIRE_RL_wci_ctl_op_complete or
MUX_wci_respF_x_wire$wset_1__VAL_1 or
WILL_FIRE_RL_wci_cfrd or
MUX_wci_respF_x_wire$wset_1__VAL_2 or WILL_FIRE_RL_wci_cfwr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_ctl_op_complete:
MUX_wci_respF_q_0$write_1__VAL_2 =
MUX_wci_respF_x_wire$wset_1__VAL_1;
WILL_FIRE_RL_wci_cfrd:
MUX_wci_respF_q_0$write_1__VAL_2 =
MUX_wci_respF_x_wire$wset_1__VAL_2;
WILL_FIRE_RL_wci_cfwr: MUX_wci_respF_q_0$write_1__VAL_2 = 34'h1C0DE4201;
default: MUX_wci_respF_q_0$write_1__VAL_2 =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign MUX_wci_respF_q_1$write_1__VAL_1 =
(wci_respF_c_r == 2'd2) ?
MUX_wci_respF_q_0$write_1__VAL_2 :
34'h0AAAAAAAA ;
assign MUX_wci_respF_x_wire$wset_1__VAL_1 =
wci_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ;
assign MUX_wci_respF_x_wire$wset_1__VAL_2 = { 2'd1, _theResult____h16428 } ;
assign MUX_wsi_M0_reqFifo_c_r$write_1__VAL_1 = wsi_M0_reqFifo_c_r + 2'd1 ;
assign MUX_wsi_M0_reqFifo_c_r$write_1__VAL_2 = wsi_M0_reqFifo_c_r - 2'd1 ;
assign MUX_wsi_M0_reqFifo_q_0$write_1__VAL_1 =
(wsi_M0_reqFifo_c_r == 2'd1) ?
MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 :
wsi_M0_reqFifo_q_1 ;
assign MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 =
MUX_wsi_M0_reqFifo_x_wire$wset_1__SEL_1 ?
wsi_S0_reqFifo$D_OUT :
wsi_S1_reqFifo$D_OUT ;
assign MUX_wsi_M0_reqFifo_q_1$write_1__VAL_1 =
(wsi_M0_reqFifo_c_r == 2'd2) ?
MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 :
313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00 ;
assign MUX_wsi_M1_reqFifo_c_r$write_1__VAL_1 = wsi_M1_reqFifo_c_r + 2'd1 ;
assign MUX_wsi_M1_reqFifo_c_r$write_1__VAL_2 = wsi_M1_reqFifo_c_r - 2'd1 ;
assign MUX_wsi_M1_reqFifo_q_0$write_1__VAL_1 =
(wsi_M1_reqFifo_c_r == 2'd1) ?
MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 :
wsi_M1_reqFifo_q_1 ;
assign MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 =
MUX_wsi_M1_reqFifo_x_wire$wset_1__SEL_1 ?
wsi_S0_reqFifo$D_OUT :
wsi_S1_reqFifo$D_OUT ;
assign MUX_wsi_M1_reqFifo_q_1$write_1__VAL_1 =
(wsi_M1_reqFifo_c_r == 2'd2) ?
MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 :
313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00 ;
// inlined wires
assign wci_wciReq$wget =
{ wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData } ;
assign wci_wciReq$whas = 1'd1 ;
assign wci_respF_x_wire$wget = MUX_wci_respF_q_0$write_1__VAL_2 ;
assign wci_respF_x_wire$whas = wci_respF_enqueueing$whas ;
assign wci_wEdge$wget = wci_reqF$D_OUT[36:34] ;
assign wci_wEdge$whas = WILL_FIRE_RL_wci_ctl_op_start ;
assign wci_sFlagReg_1$wget = 1'b0 ;
assign wci_sFlagReg_1$whas = 1'b0 ;
assign wci_ctlAckReg_1$wget = 1'd1 ;
assign wci_ctlAckReg_1$whas =
WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO ||
WILL_FIRE_RL_wci_ctrl_EiI ;
assign wsi_S0_wsiReq$wget =
{ wsiS0_MCmd,
wsiS0_MReqLast,
wsiS0_MBurstPrecise,
wsiS0_MBurstLength,
wsiS0_MData,
wsiS0_MByteEn,
wsiS0_MReqInfo } ;
assign wsi_S0_wsiReq$whas = 1'd1 ;
assign wsi_S0_operateD_1$wget = 1'd1 ;
assign wsi_S0_operateD_1$whas = wci_cState == 3'd2 ;
assign wsi_S0_peerIsReady_1$wget = 1'd1 ;
assign wsi_S0_peerIsReady_1$whas = wsiS0_MReset_n ;
assign wsi_S0_sThreadBusy_dw$wget = wsi_S0_reqFifo_countReg > 2'd1 ;
assign wsi_S0_sThreadBusy_dw$whas =
wsi_S0_reqFifo_levelsValid && wsi_S0_operateD &&
wsi_S0_peerIsReady ;
assign wsi_S1_wsiReq$wget =
{ wsiS1_MCmd,
wsiS1_MReqLast,
wsiS1_MBurstPrecise,
wsiS1_MBurstLength,
wsiS1_MData,
wsiS1_MByteEn,
wsiS1_MReqInfo } ;
assign wsi_S1_wsiReq$whas = 1'd1 ;
assign wsi_S1_operateD_1$wget = 1'd1 ;
assign wsi_S1_operateD_1$whas = wci_cState == 3'd2 ;
assign wsi_S1_peerIsReady_1$wget = 1'd1 ;
assign wsi_S1_peerIsReady_1$whas = wsiS1_MReset_n ;
assign wsi_S1_sThreadBusy_dw$wget = wsi_S1_reqFifo_countReg > 2'd1 ;
assign wsi_S1_sThreadBusy_dw$whas =
wsi_S1_reqFifo_levelsValid && wsi_S1_operateD &&
wsi_S1_peerIsReady ;
assign wsi_M0_reqFifo_x_wire$wget = MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 ;
assign wsi_M0_reqFifo_x_wire$whas = wsi_M0_reqFifo_enqueueing$whas ;
assign wsi_M0_operateD_1$wget = 1'd1 ;
assign wsi_M0_operateD_1$whas = wci_cState == 3'd2 ;
assign wsi_M0_peerIsReady_1$wget = 1'd1 ;
assign wsi_M0_peerIsReady_1$whas = wsiM0_SReset_n ;
assign wsi_M1_reqFifo_x_wire$wget = MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 ;
assign wsi_M1_reqFifo_x_wire$whas = wsi_M1_reqFifo_enqueueing$whas ;
assign wsi_M1_operateD_1$wget = 1'd1 ;
assign wsi_M1_operateD_1$whas = wci_cState == 3'd2 ;
assign wsi_M1_peerIsReady_1$wget = 1'd1 ;
assign wsi_M1_peerIsReady_1$whas = wsiM1_SReset_n ;
assign wci_Es_mCmd_w$wget = wciS0_MCmd ;
assign wci_Es_mCmd_w$whas = 1'd1 ;
assign wci_Es_mAddrSpace_w$wget = wciS0_MAddrSpace ;
assign wci_Es_mAddrSpace_w$whas = 1'd1 ;
assign wci_Es_mByteEn_w$wget = wciS0_MByteEn ;
assign wci_Es_mByteEn_w$whas = 1'd1 ;
assign wci_Es_mAddr_w$wget = wciS0_MAddr ;
assign wci_Es_mAddr_w$whas = 1'd1 ;
assign wci_Es_mData_w$wget = wciS0_MData ;
assign wci_Es_mData_w$whas = 1'd1 ;
assign wsi_Es0_mCmd_w$wget = wsiS0_MCmd ;
assign wsi_Es0_mCmd_w$whas = 1'd1 ;
assign wsi_Es0_mBurstLength_w$wget = wsiS0_MBurstLength ;
assign wsi_Es0_mBurstLength_w$whas = 1'd1 ;
assign wsi_Es0_mData_w$wget = wsiS0_MData ;
assign wsi_Es0_mData_w$whas = 1'd1 ;
assign wsi_Es0_mByteEn_w$wget = wsiS0_MByteEn ;
assign wsi_Es0_mByteEn_w$whas = 1'd1 ;
assign wsi_Es0_mReqInfo_w$wget = wsiS0_MReqInfo ;
assign wsi_Es0_mReqInfo_w$whas = 1'd1 ;
assign wsi_Es1_mCmd_w$wget = wsiS1_MCmd ;
assign wsi_Es1_mCmd_w$whas = 1'd1 ;
assign wsi_Es1_mBurstLength_w$wget = wsiS1_MBurstLength ;
assign wsi_Es1_mBurstLength_w$whas = 1'd1 ;
assign wsi_Es1_mData_w$wget = wsiS1_MData ;
assign wsi_Es1_mData_w$whas = 1'd1 ;
assign wsi_Es1_mByteEn_w$wget = wsiS1_MByteEn ;
assign wsi_Es1_mByteEn_w$whas = 1'd1 ;
assign wsi_Es1_mReqInfo_w$wget = wsiS1_MReqInfo ;
assign wsi_Es1_mReqInfo_w$whas = 1'd1 ;
assign wci_reqF_r_enq$whas = wci_wciReq$wget[71:69] != 3'd0 ;
assign wci_reqF_r_deq$whas =
WILL_FIRE_RL_wci_ctl_op_start || WILL_FIRE_RL_wci_cfrd ||
WILL_FIRE_RL_wci_cfwr ;
assign wci_reqF_r_clr$whas = 1'b0 ;
assign wci_respF_enqueueing$whas =
WILL_FIRE_RL_wci_ctl_op_complete || WILL_FIRE_RL_wci_cfrd ||
WILL_FIRE_RL_wci_cfwr ;
assign wci_respF_dequeueing$whas = wci_respF_c_r != 2'd0 ;
assign wci_sThreadBusy_pw$whas = 1'b0 ;
assign wci_wci_cfwr_pw$whas =
wci_reqF$EMPTY_N && wci_reqF$D_OUT[68] &&
wci_reqF$D_OUT[71:69] == 3'd1 ;
assign wci_wci_cfrd_pw$whas =
wci_reqF$EMPTY_N && wci_reqF$D_OUT[68] &&
wci_reqF$D_OUT[71:69] == 3'd2 ;
assign wci_wci_ctrl_pw$whas =
wci_reqF$EMPTY_N && !wci_reqF$D_OUT[68] &&
wci_reqF$D_OUT[71:69] == 3'd2 ;
assign wsi_S0_reqFifo_r_enq$whas = WILL_FIRE_RL_wsi_S0_reqFifo_enq ;
assign wsi_S0_reqFifo_r_deq$whas = WILL_FIRE_RL_doMessageConsume_S0 ;
assign wsi_S0_reqFifo_r_clr$whas = 1'b0 ;
assign wsi_S0_reqFifo_doResetEnq$whas = WILL_FIRE_RL_wsi_S0_reqFifo_enq ;
assign wsi_S0_reqFifo_doResetDeq$whas = WILL_FIRE_RL_doMessageConsume_S0 ;
assign wsi_S0_reqFifo_doResetClr$whas = 1'b0 ;
assign wsi_S1_reqFifo_r_enq$whas = WILL_FIRE_RL_wsi_S1_reqFifo_enq ;
assign wsi_S1_reqFifo_r_deq$whas = WILL_FIRE_RL_doMessageConsume_S1 ;
assign wsi_S1_reqFifo_r_clr$whas = 1'b0 ;
assign wsi_S1_reqFifo_doResetEnq$whas = WILL_FIRE_RL_wsi_S1_reqFifo_enq ;
assign wsi_S1_reqFifo_doResetDeq$whas = WILL_FIRE_RL_doMessageConsume_S1 ;
assign wsi_S1_reqFifo_doResetClr$whas = 1'b0 ;
assign wsi_M0_reqFifo_enqueueing$whas =
WILL_FIRE_RL_doMessageConsume_S0 && !splitCtrl[0] &&
!splitCtrl[7] ||
WILL_FIRE_RL_doMessageConsume_S1 && splitCtrl[0] &&
!splitCtrl[7] ;
assign wsi_M0_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsi_M0_reqFifo_deq ;
assign wsi_M0_sThreadBusy_pw$whas = wsiM0_SThreadBusy ;
assign wsi_M1_reqFifo_enqueueing$whas =
WILL_FIRE_RL_doMessageConsume_S0 && !splitCtrl[8] &&
!splitCtrl[15] ||
WILL_FIRE_RL_doMessageConsume_S1 && splitCtrl[8] &&
!splitCtrl[15] ;
assign wsi_M1_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsi_M1_reqFifo_deq ;
assign wsi_M1_sThreadBusy_pw$whas = wsiM1_SThreadBusy ;
assign wsi_Es0_mReqLast_w$whas = wsiS0_MReqLast ;
assign wsi_Es0_mBurstPrecise_w$whas = wsiS0_MBurstPrecise ;
assign wsi_Es0_mDataInfo_w$whas = 1'd1 ;
assign wsi_Es1_mReqLast_w$whas = wsiS1_MReqLast ;
assign wsi_Es1_mBurstPrecise_w$whas = wsiS1_MBurstPrecise ;
assign wsi_Es1_mDataInfo_w$whas = 1'd1 ;
assign wsi_S0_extStatusW$wget =
{ wsi_S0_pMesgCount, wsi_S0_iMesgCount, wsi_S0_tBusyCount } ;
assign wsi_S1_extStatusW$wget =
{ wsi_S1_pMesgCount, wsi_S1_iMesgCount, wsi_S1_tBusyCount } ;
assign wsi_M0_extStatusW$wget =
{ wsi_M0_pMesgCount, wsi_M0_iMesgCount, wsi_M0_tBusyCount } ;
assign wsi_M1_extStatusW$wget =
{ wsi_M1_pMesgCount, wsi_M1_iMesgCount, wsi_M1_tBusyCount } ;
// register splitCtrl
assign splitCtrl$D_IN = wci_reqF$D_OUT[31:0] ;
assign splitCtrl$EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF$D_OUT[39:32] == 8'h04 ;
// register wci_cEdge
assign wci_cEdge$D_IN = wci_reqF$D_OUT[36:34] ;
assign wci_cEdge$EN = WILL_FIRE_RL_wci_ctl_op_start ;
// register wci_cState
assign wci_cState$D_IN = wci_nState ;
assign wci_cState$EN =
WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge ;
// register wci_ctlAckReg
assign wci_ctlAckReg$D_IN = wci_ctlAckReg_1$whas ;
assign wci_ctlAckReg$EN = 1'd1 ;
// register wci_ctlOpActive
assign wci_ctlOpActive$D_IN = !WILL_FIRE_RL_wci_ctl_op_complete ;
assign wci_ctlOpActive$EN =
WILL_FIRE_RL_wci_ctl_op_complete ||
WILL_FIRE_RL_wci_ctl_op_start ;
// register wci_illegalEdge
assign wci_illegalEdge$D_IN =
MUX_wci_illegalEdge$write_1__SEL_1 &&
MUX_wci_illegalEdge$write_1__VAL_1 ;
assign wci_illegalEdge$EN =
MUX_wci_illegalEdge$write_1__SEL_1 ||
WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge ;
// register wci_isReset_isInReset
assign wci_isReset_isInReset$D_IN = 1'd0 ;
assign wci_isReset_isInReset$EN = wci_isReset_isInReset ;
// register wci_nState
always@(wci_reqF$D_OUT)
begin
case (wci_reqF$D_OUT[36:34])
3'd0: wci_nState$D_IN = 3'd1;
3'd1: wci_nState$D_IN = 3'd2;
3'd2: wci_nState$D_IN = 3'd3;
default: wci_nState$D_IN = 3'd0;
endcase
end
assign wci_nState$EN =
WILL_FIRE_RL_wci_ctl_op_start &&
(wci_reqF$D_OUT[36:34] == 3'd0 && wci_cState == 3'd0 ||
wci_reqF$D_OUT[36:34] == 3'd1 &&
(wci_cState == 3'd1 || wci_cState == 3'd3) ||
wci_reqF$D_OUT[36:34] == 3'd2 && wci_cState == 3'd2 ||
wci_reqF$D_OUT[36:34] == 3'd3 &&
(wci_cState == 3'd3 || wci_cState == 3'd2 ||
wci_cState == 3'd1)) ;
// register wci_reqF_countReg
assign wci_reqF_countReg$D_IN =
(wci_wciReq$wget[71:69] != 3'd0) ?
wci_reqF_countReg + 2'd1 :
wci_reqF_countReg - 2'd1 ;
assign wci_reqF_countReg$EN =
(wci_wciReq$wget[71:69] != 3'd0) != wci_reqF_r_deq$whas ;
// register wci_respF_c_r
assign wci_respF_c_r$D_IN =
WILL_FIRE_RL_wci_respF_incCtr ?
MUX_wci_respF_c_r$write_1__VAL_1 :
MUX_wci_respF_c_r$write_1__VAL_2 ;
assign wci_respF_c_r$EN =
WILL_FIRE_RL_wci_respF_incCtr || WILL_FIRE_RL_wci_respF_decCtr ;
// register wci_respF_q_0
always@(WILL_FIRE_RL_wci_respF_both or
MUX_wci_respF_q_0$write_1__VAL_1 or
MUX_wci_respF_q_0$write_1__SEL_2 or
MUX_wci_respF_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wci_respF_decCtr or wci_respF_q_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_respF_both:
wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_1;
MUX_wci_respF_q_0$write_1__SEL_2:
wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_0$D_IN = wci_respF_q_1;
default: wci_respF_q_0$D_IN = 34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_respF_q_0$EN =
WILL_FIRE_RL_wci_respF_both ||
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 ||
WILL_FIRE_RL_wci_respF_decCtr ;
// register wci_respF_q_1
always@(WILL_FIRE_RL_wci_respF_both or
MUX_wci_respF_q_1$write_1__VAL_1 or
MUX_wci_respF_q_1$write_1__SEL_2 or
MUX_wci_respF_q_0$write_1__VAL_2 or WILL_FIRE_RL_wci_respF_decCtr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_respF_both:
wci_respF_q_1$D_IN = MUX_wci_respF_q_1$write_1__VAL_1;
MUX_wci_respF_q_1$write_1__SEL_2:
wci_respF_q_1$D_IN = MUX_wci_respF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_1$D_IN = 34'h0AAAAAAAA;
default: wci_respF_q_1$D_IN = 34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_respF_q_1$EN =
WILL_FIRE_RL_wci_respF_both ||
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 ||
WILL_FIRE_RL_wci_respF_decCtr ;
// register wci_sFlagReg
assign wci_sFlagReg$D_IN = 1'b0 ;
assign wci_sFlagReg$EN = 1'd1 ;
// register wci_sThreadBusy_d
assign wci_sThreadBusy_d$D_IN = 1'b0 ;
assign wci_sThreadBusy_d$EN = 1'd1 ;
// register wsi_M0_burstKind
assign wsi_M0_burstKind$D_IN =
(wsi_M0_burstKind == 2'd0) ?
(wsi_M0_reqFifo_q_0[308] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsi_M0_burstKind$EN =
WILL_FIRE_RL_wsi_M0_reqFifo_deq &&
wsi_M0_reqFifo_q_0[312:310] == 3'd1 &&
(wsi_M0_burstKind == 2'd0 ||
(wsi_M0_burstKind == 2'd1 || wsi_M0_burstKind == 2'd2) &&
wsi_M0_reqFifo_q_0[309]) ;
// register wsi_M0_errorSticky
assign wsi_M0_errorSticky$D_IN = 1'b0 ;
assign wsi_M0_errorSticky$EN = 1'b0 ;
// register wsi_M0_iMesgCount
assign wsi_M0_iMesgCount$D_IN = wsi_M0_iMesgCount + 32'd1 ;
assign wsi_M0_iMesgCount$EN =
WILL_FIRE_RL_wsi_M0_reqFifo_deq &&
wsi_M0_reqFifo_q_0[312:310] == 3'd1 &&
wsi_M0_burstKind == 2'd2 &&
wsi_M0_reqFifo_q_0[309] ;
// register wsi_M0_isReset_isInReset
assign wsi_M0_isReset_isInReset$D_IN = 1'd0 ;
assign wsi_M0_isReset_isInReset$EN = wsi_M0_isReset_isInReset ;
// register wsi_M0_operateD
assign wsi_M0_operateD$D_IN = wci_cState == 3'd2 ;
assign wsi_M0_operateD$EN = 1'd1 ;
// register wsi_M0_pMesgCount
assign wsi_M0_pMesgCount$D_IN = wsi_M0_pMesgCount + 32'd1 ;
assign wsi_M0_pMesgCount$EN =
WILL_FIRE_RL_wsi_M0_reqFifo_deq &&
wsi_M0_reqFifo_q_0[312:310] == 3'd1 &&
wsi_M0_burstKind == 2'd1 &&
wsi_M0_reqFifo_q_0[309] ;
// register wsi_M0_peerIsReady
assign wsi_M0_peerIsReady$D_IN = wsiM0_SReset_n ;
assign wsi_M0_peerIsReady$EN = 1'd1 ;
// register wsi_M0_reqFifo_c_r
assign wsi_M0_reqFifo_c_r$D_IN =
WILL_FIRE_RL_wsi_M0_reqFifo_incCtr ?
MUX_wsi_M0_reqFifo_c_r$write_1__VAL_1 :
MUX_wsi_M0_reqFifo_c_r$write_1__VAL_2 ;
assign wsi_M0_reqFifo_c_r$EN =
WILL_FIRE_RL_wsi_M0_reqFifo_incCtr ||
WILL_FIRE_RL_wsi_M0_reqFifo_decCtr ;
// register wsi_M0_reqFifo_q_0
always@(WILL_FIRE_RL_wsi_M0_reqFifo_both or
MUX_wsi_M0_reqFifo_q_0$write_1__VAL_1 or
MUX_wsi_M0_reqFifo_q_0$write_1__SEL_2 or
MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wsi_M0_reqFifo_decCtr or wsi_M0_reqFifo_q_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wsi_M0_reqFifo_both:
wsi_M0_reqFifo_q_0$D_IN = MUX_wsi_M0_reqFifo_q_0$write_1__VAL_1;
MUX_wsi_M0_reqFifo_q_0$write_1__SEL_2:
wsi_M0_reqFifo_q_0$D_IN = MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2;
WILL_FIRE_RL_wsi_M0_reqFifo_decCtr:
wsi_M0_reqFifo_q_0$D_IN = wsi_M0_reqFifo_q_1;
default: wsi_M0_reqFifo_q_0$D_IN =
313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsi_M0_reqFifo_q_0$EN =
WILL_FIRE_RL_wsi_M0_reqFifo_both ||
WILL_FIRE_RL_wsi_M0_reqFifo_incCtr &&
wsi_M0_reqFifo_c_r == 2'd0 ||
WILL_FIRE_RL_wsi_M0_reqFifo_decCtr ;
// register wsi_M0_reqFifo_q_1
always@(WILL_FIRE_RL_wsi_M0_reqFifo_both or
MUX_wsi_M0_reqFifo_q_1$write_1__VAL_1 or
MUX_wsi_M0_reqFifo_q_1$write_1__SEL_2 or
MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wsi_M0_reqFifo_decCtr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wsi_M0_reqFifo_both:
wsi_M0_reqFifo_q_1$D_IN = MUX_wsi_M0_reqFifo_q_1$write_1__VAL_1;
MUX_wsi_M0_reqFifo_q_1$write_1__SEL_2:
wsi_M0_reqFifo_q_1$D_IN = MUX_wsi_M0_reqFifo_q_0$write_1__VAL_2;
WILL_FIRE_RL_wsi_M0_reqFifo_decCtr:
wsi_M0_reqFifo_q_1$D_IN =
313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00;
default: wsi_M0_reqFifo_q_1$D_IN =
313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsi_M0_reqFifo_q_1$EN =
WILL_FIRE_RL_wsi_M0_reqFifo_both ||
WILL_FIRE_RL_wsi_M0_reqFifo_incCtr &&
wsi_M0_reqFifo_c_r == 2'd1 ||
WILL_FIRE_RL_wsi_M0_reqFifo_decCtr ;
// register wsi_M0_sThreadBusy_d
assign wsi_M0_sThreadBusy_d$D_IN = wsiM0_SThreadBusy ;
assign wsi_M0_sThreadBusy_d$EN = 1'd1 ;
// register wsi_M0_statusR
assign wsi_M0_statusR$D_IN =
{ wsi_M0_isReset_isInReset,
!wsi_M0_peerIsReady,
!wsi_M0_operateD,
wsi_M0_errorSticky,
wsi_M0_burstKind != 2'd0,
wsi_M0_sThreadBusy_d,
1'd0,
wsi_M0_trafficSticky } ;
assign wsi_M0_statusR$EN = 1'd1 ;
// register wsi_M0_tBusyCount
assign wsi_M0_tBusyCount$D_IN = wsi_M0_tBusyCount + 32'd1 ;
assign wsi_M0_tBusyCount$EN =
wsi_M0_operateD && wsi_M0_peerIsReady && wsi_M0_sThreadBusy_d ;
// register wsi_M0_trafficSticky
assign wsi_M0_trafficSticky$D_IN = 1'd1 ;
assign wsi_M0_trafficSticky$EN =
WILL_FIRE_RL_wsi_M0_reqFifo_deq &&
wsi_M0_reqFifo_q_0[312:310] == 3'd1 ;
// register wsi_M1_burstKind
assign wsi_M1_burstKind$D_IN =
(wsi_M1_burstKind == 2'd0) ?
(wsi_M1_reqFifo_q_0[308] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsi_M1_burstKind$EN =
WILL_FIRE_RL_wsi_M1_reqFifo_deq &&
wsi_M1_reqFifo_q_0[312:310] == 3'd1 &&
(wsi_M1_burstKind == 2'd0 ||
(wsi_M1_burstKind == 2'd1 || wsi_M1_burstKind == 2'd2) &&
wsi_M1_reqFifo_q_0[309]) ;
// register wsi_M1_errorSticky
assign wsi_M1_errorSticky$D_IN = 1'b0 ;
assign wsi_M1_errorSticky$EN = 1'b0 ;
// register wsi_M1_iMesgCount
assign wsi_M1_iMesgCount$D_IN = wsi_M1_iMesgCount + 32'd1 ;
assign wsi_M1_iMesgCount$EN =
WILL_FIRE_RL_wsi_M1_reqFifo_deq &&
wsi_M1_reqFifo_q_0[312:310] == 3'd1 &&
wsi_M1_burstKind == 2'd2 &&
wsi_M1_reqFifo_q_0[309] ;
// register wsi_M1_isReset_isInReset
assign wsi_M1_isReset_isInReset$D_IN = 1'd0 ;
assign wsi_M1_isReset_isInReset$EN = wsi_M1_isReset_isInReset ;
// register wsi_M1_operateD
assign wsi_M1_operateD$D_IN = wci_cState == 3'd2 ;
assign wsi_M1_operateD$EN = 1'd1 ;
// register wsi_M1_pMesgCount
assign wsi_M1_pMesgCount$D_IN = wsi_M1_pMesgCount + 32'd1 ;
assign wsi_M1_pMesgCount$EN =
WILL_FIRE_RL_wsi_M1_reqFifo_deq &&
wsi_M1_reqFifo_q_0[312:310] == 3'd1 &&
wsi_M1_burstKind == 2'd1 &&
wsi_M1_reqFifo_q_0[309] ;
// register wsi_M1_peerIsReady
assign wsi_M1_peerIsReady$D_IN = wsiM1_SReset_n ;
assign wsi_M1_peerIsReady$EN = 1'd1 ;
// register wsi_M1_reqFifo_c_r
assign wsi_M1_reqFifo_c_r$D_IN =
WILL_FIRE_RL_wsi_M1_reqFifo_incCtr ?
MUX_wsi_M1_reqFifo_c_r$write_1__VAL_1 :
MUX_wsi_M1_reqFifo_c_r$write_1__VAL_2 ;
assign wsi_M1_reqFifo_c_r$EN =
WILL_FIRE_RL_wsi_M1_reqFifo_incCtr ||
WILL_FIRE_RL_wsi_M1_reqFifo_decCtr ;
// register wsi_M1_reqFifo_q_0
always@(WILL_FIRE_RL_wsi_M1_reqFifo_both or
MUX_wsi_M1_reqFifo_q_0$write_1__VAL_1 or
MUX_wsi_M1_reqFifo_q_0$write_1__SEL_2 or
MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wsi_M1_reqFifo_decCtr or wsi_M1_reqFifo_q_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wsi_M1_reqFifo_both:
wsi_M1_reqFifo_q_0$D_IN = MUX_wsi_M1_reqFifo_q_0$write_1__VAL_1;
MUX_wsi_M1_reqFifo_q_0$write_1__SEL_2:
wsi_M1_reqFifo_q_0$D_IN = MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2;
WILL_FIRE_RL_wsi_M1_reqFifo_decCtr:
wsi_M1_reqFifo_q_0$D_IN = wsi_M1_reqFifo_q_1;
default: wsi_M1_reqFifo_q_0$D_IN =
313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsi_M1_reqFifo_q_0$EN =
WILL_FIRE_RL_wsi_M1_reqFifo_both ||
WILL_FIRE_RL_wsi_M1_reqFifo_incCtr &&
wsi_M1_reqFifo_c_r == 2'd0 ||
WILL_FIRE_RL_wsi_M1_reqFifo_decCtr ;
// register wsi_M1_reqFifo_q_1
always@(WILL_FIRE_RL_wsi_M1_reqFifo_both or
MUX_wsi_M1_reqFifo_q_1$write_1__VAL_1 or
MUX_wsi_M1_reqFifo_q_1$write_1__SEL_2 or
MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wsi_M1_reqFifo_decCtr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wsi_M1_reqFifo_both:
wsi_M1_reqFifo_q_1$D_IN = MUX_wsi_M1_reqFifo_q_1$write_1__VAL_1;
MUX_wsi_M1_reqFifo_q_1$write_1__SEL_2:
wsi_M1_reqFifo_q_1$D_IN = MUX_wsi_M1_reqFifo_q_0$write_1__VAL_2;
WILL_FIRE_RL_wsi_M1_reqFifo_decCtr:
wsi_M1_reqFifo_q_1$D_IN =
313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00;
default: wsi_M1_reqFifo_q_1$D_IN =
313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsi_M1_reqFifo_q_1$EN =
WILL_FIRE_RL_wsi_M1_reqFifo_both ||
WILL_FIRE_RL_wsi_M1_reqFifo_incCtr &&
wsi_M1_reqFifo_c_r == 2'd1 ||
WILL_FIRE_RL_wsi_M1_reqFifo_decCtr ;
// register wsi_M1_sThreadBusy_d
assign wsi_M1_sThreadBusy_d$D_IN = wsiM1_SThreadBusy ;
assign wsi_M1_sThreadBusy_d$EN = 1'd1 ;
// register wsi_M1_statusR
assign wsi_M1_statusR$D_IN =
{ wsi_M1_isReset_isInReset,
!wsi_M1_peerIsReady,
!wsi_M1_operateD,
wsi_M1_errorSticky,
wsi_M1_burstKind != 2'd0,
wsi_M1_sThreadBusy_d,
1'd0,
wsi_M1_trafficSticky } ;
assign wsi_M1_statusR$EN = 1'd1 ;
// register wsi_M1_tBusyCount
assign wsi_M1_tBusyCount$D_IN = wsi_M1_tBusyCount + 32'd1 ;
assign wsi_M1_tBusyCount$EN =
wsi_M1_operateD && wsi_M1_peerIsReady && wsi_M1_sThreadBusy_d ;
// register wsi_M1_trafficSticky
assign wsi_M1_trafficSticky$D_IN = 1'd1 ;
assign wsi_M1_trafficSticky$EN =
WILL_FIRE_RL_wsi_M1_reqFifo_deq &&
wsi_M1_reqFifo_q_0[312:310] == 3'd1 ;
// register wsi_S0_burstKind
assign wsi_S0_burstKind$D_IN =
(wsi_S0_burstKind == 2'd0) ?
(wsi_S0_wsiReq$wget[308] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsi_S0_burstKind$EN =
WILL_FIRE_RL_wsi_S0_reqFifo_enq &&
(wsi_S0_burstKind == 2'd0 ||
(wsi_S0_burstKind == 2'd1 || wsi_S0_burstKind == 2'd2) &&
wsi_S0_wsiReq$wget[309]) ;
// register wsi_S0_errorSticky
assign wsi_S0_errorSticky$D_IN = 1'b0 ;
assign wsi_S0_errorSticky$EN = 1'b0 ;
// register wsi_S0_iMesgCount
assign wsi_S0_iMesgCount$D_IN = wsi_S0_iMesgCount + 32'd1 ;
assign wsi_S0_iMesgCount$EN =
WILL_FIRE_RL_wsi_S0_reqFifo_enq && wsi_S0_burstKind == 2'd2 &&
wsi_S0_wsiReq$wget[309] ;
// register wsi_S0_isReset_isInReset
assign wsi_S0_isReset_isInReset$D_IN = 1'd0 ;
assign wsi_S0_isReset_isInReset$EN = wsi_S0_isReset_isInReset ;
// register wsi_S0_mesgWordLength
assign wsi_S0_mesgWordLength$D_IN = wsi_S0_wordCount ;
assign wsi_S0_mesgWordLength$EN =
WILL_FIRE_RL_wsi_S0_reqFifo_enq && wsi_S0_wsiReq$wget[309] ;
// register wsi_S0_operateD
assign wsi_S0_operateD$D_IN = wci_cState == 3'd2 ;
assign wsi_S0_operateD$EN = 1'd1 ;
// register wsi_S0_pMesgCount
assign wsi_S0_pMesgCount$D_IN = wsi_S0_pMesgCount + 32'd1 ;
assign wsi_S0_pMesgCount$EN =
WILL_FIRE_RL_wsi_S0_reqFifo_enq && wsi_S0_burstKind == 2'd1 &&
wsi_S0_wsiReq$wget[309] ;
// register wsi_S0_peerIsReady
assign wsi_S0_peerIsReady$D_IN = wsiS0_MReset_n ;
assign wsi_S0_peerIsReady$EN = 1'd1 ;
// register wsi_S0_reqFifo_countReg
assign wsi_S0_reqFifo_countReg$D_IN =
WILL_FIRE_RL_wsi_S0_reqFifo_enq ?
wsi_S0_reqFifo_countReg + 2'd1 :
wsi_S0_reqFifo_countReg - 2'd1 ;
assign wsi_S0_reqFifo_countReg$EN =
WILL_FIRE_RL_wsi_S0_reqFifo_enq !=
WILL_FIRE_RL_doMessageConsume_S0 ;
// register wsi_S0_reqFifo_levelsValid
assign wsi_S0_reqFifo_levelsValid$D_IN = WILL_FIRE_RL_wsi_S0_reqFifo_reset ;
assign wsi_S0_reqFifo_levelsValid$EN =
WILL_FIRE_RL_doMessageConsume_S0 ||
WILL_FIRE_RL_wsi_S0_reqFifo_enq ||
WILL_FIRE_RL_wsi_S0_reqFifo_reset ;
// register wsi_S0_statusR
assign wsi_S0_statusR$D_IN =
{ wsi_S0_isReset_isInReset,
!wsi_S0_peerIsReady,
!wsi_S0_operateD,
wsi_S0_errorSticky,
wsi_S0_burstKind != 2'd0,
!wsi_S0_sThreadBusy_dw$whas || wsi_S0_sThreadBusy_dw$wget,
1'd0,
wsi_S0_trafficSticky } ;
assign wsi_S0_statusR$EN = 1'd1 ;
// register wsi_S0_tBusyCount
assign wsi_S0_tBusyCount$D_IN = wsi_S0_tBusyCount + 32'd1 ;
assign wsi_S0_tBusyCount$EN =
wsi_S0_operateD && wsi_S0_peerIsReady &&
(!wsi_S0_sThreadBusy_dw$whas || wsi_S0_sThreadBusy_dw$wget) ;
// register wsi_S0_trafficSticky
assign wsi_S0_trafficSticky$D_IN = 1'd1 ;
assign wsi_S0_trafficSticky$EN = WILL_FIRE_RL_wsi_S0_reqFifo_enq ;
// register wsi_S0_wordCount
assign wsi_S0_wordCount$D_IN =
wsi_S0_wsiReq$wget[309] ? 12'd1 : wsi_S0_wordCount + 12'd1 ;
assign wsi_S0_wordCount$EN = WILL_FIRE_RL_wsi_S0_reqFifo_enq ;
// register wsi_S1_burstKind
assign wsi_S1_burstKind$D_IN =
(wsi_S1_burstKind == 2'd0) ?
(wsi_S1_wsiReq$wget[308] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsi_S1_burstKind$EN =
WILL_FIRE_RL_wsi_S1_reqFifo_enq &&
(wsi_S1_burstKind == 2'd0 ||
(wsi_S1_burstKind == 2'd1 || wsi_S1_burstKind == 2'd2) &&
wsi_S1_wsiReq$wget[309]) ;
// register wsi_S1_errorSticky
assign wsi_S1_errorSticky$D_IN = 1'b0 ;
assign wsi_S1_errorSticky$EN = 1'b0 ;
// register wsi_S1_iMesgCount
assign wsi_S1_iMesgCount$D_IN = wsi_S1_iMesgCount + 32'd1 ;
assign wsi_S1_iMesgCount$EN =
WILL_FIRE_RL_wsi_S1_reqFifo_enq && wsi_S1_burstKind == 2'd2 &&
wsi_S1_wsiReq$wget[309] ;
// register wsi_S1_isReset_isInReset
assign wsi_S1_isReset_isInReset$D_IN = 1'd0 ;
assign wsi_S1_isReset_isInReset$EN = wsi_S1_isReset_isInReset ;
// register wsi_S1_mesgWordLength
assign wsi_S1_mesgWordLength$D_IN = wsi_S1_wordCount ;
assign wsi_S1_mesgWordLength$EN =
WILL_FIRE_RL_wsi_S1_reqFifo_enq && wsi_S1_wsiReq$wget[309] ;
// register wsi_S1_operateD
assign wsi_S1_operateD$D_IN = wci_cState == 3'd2 ;
assign wsi_S1_operateD$EN = 1'd1 ;
// register wsi_S1_pMesgCount
assign wsi_S1_pMesgCount$D_IN = wsi_S1_pMesgCount + 32'd1 ;
assign wsi_S1_pMesgCount$EN =
WILL_FIRE_RL_wsi_S1_reqFifo_enq && wsi_S1_burstKind == 2'd1 &&
wsi_S1_wsiReq$wget[309] ;
// register wsi_S1_peerIsReady
assign wsi_S1_peerIsReady$D_IN = wsiS1_MReset_n ;
assign wsi_S1_peerIsReady$EN = 1'd1 ;
// register wsi_S1_reqFifo_countReg
assign wsi_S1_reqFifo_countReg$D_IN =
WILL_FIRE_RL_wsi_S1_reqFifo_enq ?
wsi_S1_reqFifo_countReg + 2'd1 :
wsi_S1_reqFifo_countReg - 2'd1 ;
assign wsi_S1_reqFifo_countReg$EN =
WILL_FIRE_RL_wsi_S1_reqFifo_enq !=
WILL_FIRE_RL_doMessageConsume_S1 ;
// register wsi_S1_reqFifo_levelsValid
assign wsi_S1_reqFifo_levelsValid$D_IN = WILL_FIRE_RL_wsi_S1_reqFifo_reset ;
assign wsi_S1_reqFifo_levelsValid$EN =
WILL_FIRE_RL_doMessageConsume_S1 ||
WILL_FIRE_RL_wsi_S1_reqFifo_enq ||
WILL_FIRE_RL_wsi_S1_reqFifo_reset ;
// register wsi_S1_statusR
assign wsi_S1_statusR$D_IN =
{ wsi_S1_isReset_isInReset,
!wsi_S1_peerIsReady,
!wsi_S1_operateD,
wsi_S1_errorSticky,
wsi_S1_burstKind != 2'd0,
!wsi_S1_sThreadBusy_dw$whas || wsi_S1_sThreadBusy_dw$wget,
1'd0,
wsi_S1_trafficSticky } ;
assign wsi_S1_statusR$EN = 1'd1 ;
// register wsi_S1_tBusyCount
assign wsi_S1_tBusyCount$D_IN = wsi_S1_tBusyCount + 32'd1 ;
assign wsi_S1_tBusyCount$EN =
wsi_S1_operateD && wsi_S1_peerIsReady &&
(!wsi_S1_sThreadBusy_dw$whas || wsi_S1_sThreadBusy_dw$wget) ;
// register wsi_S1_trafficSticky
assign wsi_S1_trafficSticky$D_IN = 1'd1 ;
assign wsi_S1_trafficSticky$EN = WILL_FIRE_RL_wsi_S1_reqFifo_enq ;
// register wsi_S1_wordCount
assign wsi_S1_wordCount$D_IN =
wsi_S1_wsiReq$wget[309] ? 12'd1 : wsi_S1_wordCount + 12'd1 ;
assign wsi_S1_wordCount$EN = WILL_FIRE_RL_wsi_S1_reqFifo_enq ;
// submodule wci_reqF
assign wci_reqF$D_IN = wci_wciReq$wget ;
assign wci_reqF$ENQ = wci_wciReq$wget[71:69] != 3'd0 ;
assign wci_reqF$DEQ = wci_reqF_r_deq$whas ;
assign wci_reqF$CLR = 1'b0 ;
// submodule wsi_S0_reqFifo
assign wsi_S0_reqFifo$D_IN = wsi_S0_wsiReq$wget ;
assign wsi_S0_reqFifo$ENQ = WILL_FIRE_RL_wsi_S0_reqFifo_enq ;
assign wsi_S0_reqFifo$DEQ = WILL_FIRE_RL_doMessageConsume_S0 ;
assign wsi_S0_reqFifo$CLR = 1'b0 ;
// submodule wsi_S1_reqFifo
assign wsi_S1_reqFifo$D_IN = wsi_S1_wsiReq$wget ;
assign wsi_S1_reqFifo$ENQ = WILL_FIRE_RL_wsi_S1_reqFifo_enq ;
assign wsi_S1_reqFifo$DEQ = WILL_FIRE_RL_doMessageConsume_S1 ;
assign wsi_S1_reqFifo$CLR = 1'b0 ;
// remaining internal signals
assign rdat__h16512 =
hasDebugLogic ?
{ wsi_S0_statusR,
wsi_S1_statusR,
wsi_M0_statusR,
wsi_M1_statusR } :
32'd0 ;
assign rdat__h16701 =
hasDebugLogic ? wsi_S0_extStatusW$wget[95:64] : 32'd0 ;
assign rdat__h16715 =
hasDebugLogic ? wsi_S0_extStatusW$wget[63:32] : 32'd0 ;
assign rdat__h16723 =
hasDebugLogic ? wsi_S1_extStatusW$wget[95:64] : 32'd0 ;
assign rdat__h16737 =
hasDebugLogic ? wsi_S1_extStatusW$wget[63:32] : 32'd0 ;
assign rdat__h16745 =
hasDebugLogic ? wsi_M0_extStatusW$wget[95:64] : 32'd0 ;
assign rdat__h16759 =
hasDebugLogic ? wsi_M0_extStatusW$wget[63:32] : 32'd0 ;
assign rdat__h16767 =
hasDebugLogic ? wsi_M1_extStatusW$wget[95:64] : 32'd0 ;
assign rdat__h16781 =
hasDebugLogic ? wsi_M1_extStatusW$wget[63:32] : 32'd0 ;
always@(wci_reqF$D_OUT or
splitCtrl or
rdat__h16512 or
rdat__h16701 or
rdat__h16715 or
rdat__h16723 or
rdat__h16737 or
rdat__h16745 or rdat__h16759 or rdat__h16767 or rdat__h16781)
begin
case (wci_reqF$D_OUT[39:32])
8'h04: _theResult____h16428 = splitCtrl;
8'h1C: _theResult____h16428 = rdat__h16512;
8'h20: _theResult____h16428 = rdat__h16701;
8'h24: _theResult____h16428 = rdat__h16715;
8'h28: _theResult____h16428 = rdat__h16723;
8'h2C: _theResult____h16428 = rdat__h16737;
8'h30: _theResult____h16428 = rdat__h16745;
8'h34: _theResult____h16428 = rdat__h16759;
8'h38: _theResult____h16428 = rdat__h16767;
8'h3C: _theResult____h16428 = rdat__h16781;
default: _theResult____h16428 = 32'd0;
endcase
end
// handling of inlined registers
always@(posedge wciS0_Clk)
begin
if (wciS0_MReset_n == `BSV_RESET_VALUE)
begin
splitCtrl <= `BSV_ASSIGNMENT_DELAY ctrlInit;
wci_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2;
wci_cState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_nState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsi_M0_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsi_M0_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_M0_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_M0_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_M0_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_M0_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_M0_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsi_M0_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY
313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00;
wsi_M0_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY
313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00;
wsi_M0_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsi_M0_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_M0_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_M1_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsi_M1_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_M1_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_M1_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_M1_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_M1_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_M1_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsi_M1_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY
313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00;
wsi_M1_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY
313'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00;
wsi_M1_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsi_M1_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_M1_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_S0_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsi_S0_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_S0_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_S0_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_S0_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_S0_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_S0_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsi_S0_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsi_S0_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_S0_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_S0_wordCount <= `BSV_ASSIGNMENT_DELAY 12'd1;
wsi_S1_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsi_S1_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_S1_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_S1_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_S1_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_S1_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_S1_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsi_S1_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsi_S1_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsi_S1_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsi_S1_wordCount <= `BSV_ASSIGNMENT_DELAY 12'd1;
end
else
begin
if (splitCtrl$EN) splitCtrl <= `BSV_ASSIGNMENT_DELAY splitCtrl$D_IN;
if (wci_cEdge$EN) wci_cEdge <= `BSV_ASSIGNMENT_DELAY wci_cEdge$D_IN;
if (wci_cState$EN)
wci_cState <= `BSV_ASSIGNMENT_DELAY wci_cState$D_IN;
if (wci_ctlAckReg$EN)
wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY wci_ctlAckReg$D_IN;
if (wci_ctlOpActive$EN)
wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY wci_ctlOpActive$D_IN;
if (wci_illegalEdge$EN)
wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY wci_illegalEdge$D_IN;
if (wci_nState$EN)
wci_nState <= `BSV_ASSIGNMENT_DELAY wci_nState$D_IN;
if (wci_reqF_countReg$EN)
wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY wci_reqF_countReg$D_IN;
if (wci_respF_c_r$EN)
wci_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_respF_c_r$D_IN;
if (wci_respF_q_0$EN)
wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_0$D_IN;
if (wci_respF_q_1$EN)
wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_1$D_IN;
if (wci_sFlagReg$EN)
wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY wci_sFlagReg$D_IN;
if (wci_sThreadBusy_d$EN)
wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wci_sThreadBusy_d$D_IN;
if (wsi_M0_burstKind$EN)
wsi_M0_burstKind <= `BSV_ASSIGNMENT_DELAY wsi_M0_burstKind$D_IN;
if (wsi_M0_errorSticky$EN)
wsi_M0_errorSticky <= `BSV_ASSIGNMENT_DELAY wsi_M0_errorSticky$D_IN;
if (wsi_M0_iMesgCount$EN)
wsi_M0_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_M0_iMesgCount$D_IN;
if (wsi_M0_operateD$EN)
wsi_M0_operateD <= `BSV_ASSIGNMENT_DELAY wsi_M0_operateD$D_IN;
if (wsi_M0_pMesgCount$EN)
wsi_M0_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_M0_pMesgCount$D_IN;
if (wsi_M0_peerIsReady$EN)
wsi_M0_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsi_M0_peerIsReady$D_IN;
if (wsi_M0_reqFifo_c_r$EN)
wsi_M0_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsi_M0_reqFifo_c_r$D_IN;
if (wsi_M0_reqFifo_q_0$EN)
wsi_M0_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsi_M0_reqFifo_q_0$D_IN;
if (wsi_M0_reqFifo_q_1$EN)
wsi_M0_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsi_M0_reqFifo_q_1$D_IN;
if (wsi_M0_sThreadBusy_d$EN)
wsi_M0_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY
wsi_M0_sThreadBusy_d$D_IN;
if (wsi_M0_tBusyCount$EN)
wsi_M0_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsi_M0_tBusyCount$D_IN;
if (wsi_M0_trafficSticky$EN)
wsi_M0_trafficSticky <= `BSV_ASSIGNMENT_DELAY
wsi_M0_trafficSticky$D_IN;
if (wsi_M1_burstKind$EN)
wsi_M1_burstKind <= `BSV_ASSIGNMENT_DELAY wsi_M1_burstKind$D_IN;
if (wsi_M1_errorSticky$EN)
wsi_M1_errorSticky <= `BSV_ASSIGNMENT_DELAY wsi_M1_errorSticky$D_IN;
if (wsi_M1_iMesgCount$EN)
wsi_M1_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_M1_iMesgCount$D_IN;
if (wsi_M1_operateD$EN)
wsi_M1_operateD <= `BSV_ASSIGNMENT_DELAY wsi_M1_operateD$D_IN;
if (wsi_M1_pMesgCount$EN)
wsi_M1_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_M1_pMesgCount$D_IN;
if (wsi_M1_peerIsReady$EN)
wsi_M1_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsi_M1_peerIsReady$D_IN;
if (wsi_M1_reqFifo_c_r$EN)
wsi_M1_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsi_M1_reqFifo_c_r$D_IN;
if (wsi_M1_reqFifo_q_0$EN)
wsi_M1_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsi_M1_reqFifo_q_0$D_IN;
if (wsi_M1_reqFifo_q_1$EN)
wsi_M1_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsi_M1_reqFifo_q_1$D_IN;
if (wsi_M1_sThreadBusy_d$EN)
wsi_M1_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY
wsi_M1_sThreadBusy_d$D_IN;
if (wsi_M1_tBusyCount$EN)
wsi_M1_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsi_M1_tBusyCount$D_IN;
if (wsi_M1_trafficSticky$EN)
wsi_M1_trafficSticky <= `BSV_ASSIGNMENT_DELAY
wsi_M1_trafficSticky$D_IN;
if (wsi_S0_burstKind$EN)
wsi_S0_burstKind <= `BSV_ASSIGNMENT_DELAY wsi_S0_burstKind$D_IN;
if (wsi_S0_errorSticky$EN)
wsi_S0_errorSticky <= `BSV_ASSIGNMENT_DELAY wsi_S0_errorSticky$D_IN;
if (wsi_S0_iMesgCount$EN)
wsi_S0_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_S0_iMesgCount$D_IN;
if (wsi_S0_operateD$EN)
wsi_S0_operateD <= `BSV_ASSIGNMENT_DELAY wsi_S0_operateD$D_IN;
if (wsi_S0_pMesgCount$EN)
wsi_S0_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_S0_pMesgCount$D_IN;
if (wsi_S0_peerIsReady$EN)
wsi_S0_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsi_S0_peerIsReady$D_IN;
if (wsi_S0_reqFifo_countReg$EN)
wsi_S0_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY
wsi_S0_reqFifo_countReg$D_IN;
if (wsi_S0_reqFifo_levelsValid$EN)
wsi_S0_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY
wsi_S0_reqFifo_levelsValid$D_IN;
if (wsi_S0_tBusyCount$EN)
wsi_S0_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsi_S0_tBusyCount$D_IN;
if (wsi_S0_trafficSticky$EN)
wsi_S0_trafficSticky <= `BSV_ASSIGNMENT_DELAY
wsi_S0_trafficSticky$D_IN;
if (wsi_S0_wordCount$EN)
wsi_S0_wordCount <= `BSV_ASSIGNMENT_DELAY wsi_S0_wordCount$D_IN;
if (wsi_S1_burstKind$EN)
wsi_S1_burstKind <= `BSV_ASSIGNMENT_DELAY wsi_S1_burstKind$D_IN;
if (wsi_S1_errorSticky$EN)
wsi_S1_errorSticky <= `BSV_ASSIGNMENT_DELAY wsi_S1_errorSticky$D_IN;
if (wsi_S1_iMesgCount$EN)
wsi_S1_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_S1_iMesgCount$D_IN;
if (wsi_S1_operateD$EN)
wsi_S1_operateD <= `BSV_ASSIGNMENT_DELAY wsi_S1_operateD$D_IN;
if (wsi_S1_pMesgCount$EN)
wsi_S1_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsi_S1_pMesgCount$D_IN;
if (wsi_S1_peerIsReady$EN)
wsi_S1_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsi_S1_peerIsReady$D_IN;
if (wsi_S1_reqFifo_countReg$EN)
wsi_S1_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY
wsi_S1_reqFifo_countReg$D_IN;
if (wsi_S1_reqFifo_levelsValid$EN)
wsi_S1_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY
wsi_S1_reqFifo_levelsValid$D_IN;
if (wsi_S1_tBusyCount$EN)
wsi_S1_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsi_S1_tBusyCount$D_IN;
if (wsi_S1_trafficSticky$EN)
wsi_S1_trafficSticky <= `BSV_ASSIGNMENT_DELAY
wsi_S1_trafficSticky$D_IN;
if (wsi_S1_wordCount$EN)
wsi_S1_wordCount <= `BSV_ASSIGNMENT_DELAY wsi_S1_wordCount$D_IN;
end
if (wsi_M0_statusR$EN)
wsi_M0_statusR <= `BSV_ASSIGNMENT_DELAY wsi_M0_statusR$D_IN;
if (wsi_M1_statusR$EN)
wsi_M1_statusR <= `BSV_ASSIGNMENT_DELAY wsi_M1_statusR$D_IN;
if (wsi_S0_mesgWordLength$EN)
wsi_S0_mesgWordLength <= `BSV_ASSIGNMENT_DELAY
wsi_S0_mesgWordLength$D_IN;
if (wsi_S0_statusR$EN)
wsi_S0_statusR <= `BSV_ASSIGNMENT_DELAY wsi_S0_statusR$D_IN;
if (wsi_S1_mesgWordLength$EN)
wsi_S1_mesgWordLength <= `BSV_ASSIGNMENT_DELAY
wsi_S1_mesgWordLength$D_IN;
if (wsi_S1_statusR$EN)
wsi_S1_statusR <= `BSV_ASSIGNMENT_DELAY wsi_S1_statusR$D_IN;
end
always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n)
if (wciS0_MReset_n == `BSV_RESET_VALUE)
begin
wci_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsi_M0_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsi_M1_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsi_S0_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsi_S1_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (wci_isReset_isInReset$EN)
wci_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wci_isReset_isInReset$D_IN;
if (wsi_M0_isReset_isInReset$EN)
wsi_M0_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wsi_M0_isReset_isInReset$D_IN;
if (wsi_M1_isReset_isInReset$EN)
wsi_M1_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wsi_M1_isReset_isInReset$D_IN;
if (wsi_S0_isReset_isInReset$EN)
wsi_S0_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wsi_S0_isReset_isInReset$D_IN;
if (wsi_S1_isReset_isInReset$EN)
wsi_S1_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wsi_S1_isReset_isInReset$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
splitCtrl = 32'hAAAAAAAA;
wci_cEdge = 3'h2;
wci_cState = 3'h2;
wci_ctlAckReg = 1'h0;
wci_ctlOpActive = 1'h0;
wci_illegalEdge = 1'h0;
wci_isReset_isInReset = 1'h0;
wci_nState = 3'h2;
wci_reqF_countReg = 2'h2;
wci_respF_c_r = 2'h2;
wci_respF_q_0 = 34'h2AAAAAAAA;
wci_respF_q_1 = 34'h2AAAAAAAA;
wci_sFlagReg = 1'h0;
wci_sThreadBusy_d = 1'h0;
wsi_M0_burstKind = 2'h2;
wsi_M0_errorSticky = 1'h0;
wsi_M0_iMesgCount = 32'hAAAAAAAA;
wsi_M0_isReset_isInReset = 1'h0;
wsi_M0_operateD = 1'h0;
wsi_M0_pMesgCount = 32'hAAAAAAAA;
wsi_M0_peerIsReady = 1'h0;
wsi_M0_reqFifo_c_r = 2'h2;
wsi_M0_reqFifo_q_0 =
313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wsi_M0_reqFifo_q_1 =
313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wsi_M0_sThreadBusy_d = 1'h0;
wsi_M0_statusR = 8'hAA;
wsi_M0_tBusyCount = 32'hAAAAAAAA;
wsi_M0_trafficSticky = 1'h0;
wsi_M1_burstKind = 2'h2;
wsi_M1_errorSticky = 1'h0;
wsi_M1_iMesgCount = 32'hAAAAAAAA;
wsi_M1_isReset_isInReset = 1'h0;
wsi_M1_operateD = 1'h0;
wsi_M1_pMesgCount = 32'hAAAAAAAA;
wsi_M1_peerIsReady = 1'h0;
wsi_M1_reqFifo_c_r = 2'h2;
wsi_M1_reqFifo_q_0 =
313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wsi_M1_reqFifo_q_1 =
313'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wsi_M1_sThreadBusy_d = 1'h0;
wsi_M1_statusR = 8'hAA;
wsi_M1_tBusyCount = 32'hAAAAAAAA;
wsi_M1_trafficSticky = 1'h0;
wsi_S0_burstKind = 2'h2;
wsi_S0_errorSticky = 1'h0;
wsi_S0_iMesgCount = 32'hAAAAAAAA;
wsi_S0_isReset_isInReset = 1'h0;
wsi_S0_mesgWordLength = 12'hAAA;
wsi_S0_operateD = 1'h0;
wsi_S0_pMesgCount = 32'hAAAAAAAA;
wsi_S0_peerIsReady = 1'h0;
wsi_S0_reqFifo_countReg = 2'h2;
wsi_S0_reqFifo_levelsValid = 1'h0;
wsi_S0_statusR = 8'hAA;
wsi_S0_tBusyCount = 32'hAAAAAAAA;
wsi_S0_trafficSticky = 1'h0;
wsi_S0_wordCount = 12'hAAA;
wsi_S1_burstKind = 2'h2;
wsi_S1_errorSticky = 1'h0;
wsi_S1_iMesgCount = 32'hAAAAAAAA;
wsi_S1_isReset_isInReset = 1'h0;
wsi_S1_mesgWordLength = 12'hAAA;
wsi_S1_operateD = 1'h0;
wsi_S1_pMesgCount = 32'hAAAAAAAA;
wsi_S1_peerIsReady = 1'h0;
wsi_S1_reqFifo_countReg = 2'h2;
wsi_S1_reqFifo_levelsValid = 1'h0;
wsi_S1_statusR = 8'hAA;
wsi_S1_tBusyCount = 32'hAAAAAAAA;
wsi_S1_trafficSticky = 1'h0;
wsi_S1_wordCount = 12'hAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge wciS0_Clk)
begin
#0;
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctl_op_start)
begin
v__h3698 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctl_op_start)
$display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x",
v__h3698,
wci_reqF$D_OUT[36:34],
wci_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 60: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr)
begin
v__h16289 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr)
$display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x",
v__h16289,
wci_reqF$D_OUT[63:32],
wci_reqF$D_OUT[67:64],
wci_reqF$D_OUT[31:0]);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge)
begin
v__h4017 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x",
v__h4017,
wci_cEdge,
wci_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge)
begin
v__h3873 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x",
v__h3873,
wci_cEdge,
wci_cState,
wci_nState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd)
begin
v__h16444 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd)
$display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x",
v__h16444,
wci_reqF$D_OUT[63:32],
wci_reqF$D_OUT[67:64],
_theResult____h16428);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd)
$display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/inf/WsiSplitter2x2.bsv\", line 48, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
end
// synopsys translate_on
endmodule // mkWsiSplitter2x232B
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_pcie_bram_7vx_rep_8k.v
// Version : 4.1
//----------------------------------------------------------------------------//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express //
// Filename : pcie3_7x_0_pcie_bram_7vx_rep_8k.v //
// Description : Implements 8 KB Single Ported Memory //
// - Output Regs are always enabled //
// - 2xRAMB36E1 Single Port Mode //
// //
//---------- PIPE Wrapper Hierarchy ------------------------------------------//
// pcie_bram_7vx_rep_8k.v //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie3_7x_0_pcie_bram_7vx_rep_8k #(
parameter IMPL_TARGET = "HARD", // the implementation target, HARD or SOFT
parameter NO_DECODE_LOGIC = "TRUE", // No decode logic, TRUE or FALSE
parameter INTERFACE_SPEED = "500 MHZ", // the memory interface speed, 500 MHz or 250 MHz.
parameter COMPLETION_SPACE = "16 KB" // the completion FIFO spec, 8KB or 16KB
) (
input clk_i, // user clock
input reset_i, // bram reset
input [8:0] addr_i, // address
input [127:0] wdata_i, // write data
input [15:0] wdip_i, // write parity
input [1:0] wen_i, // write enable
output [127:0] rdata_o, // read data
output [15:0] rdop_o // read parity
);
genvar i;
wire [1:0] wen = {wen_i[1], wen_i[0]};
generate
for (i = 0; i < 2; i = i + 1) begin : RAMB36E1
RAMB36E1 #(
.SIM_DEVICE ("7SERIES"),
.RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ),
.DOA_REG ( 1 ),
.DOB_REG ( 1 ),
.EN_ECC_READ ( "FALSE" ),
.EN_ECC_WRITE ( "FALSE" ),
.RAM_EXTENSION_A ( "NONE" ),
.RAM_EXTENSION_B ( "NONE" ),
.RAM_MODE ( "TDP" ),
.READ_WIDTH_A ( 36 ),
.READ_WIDTH_B ( 36 ),
.RSTREG_PRIORITY_A ( "REGCE" ),
.RSTREG_PRIORITY_B ( "REGCE" ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.WRITE_WIDTH_A ( 36 ),
.WRITE_WIDTH_B ( 36 )
)
u_buffer (
.CASCADEINA (),
.CASCADEINB (),
.CASCADEOUTA (),
.CASCADEOUTB (),
.CLKARDCLK (clk_i),
.CLKBWRCLK (clk_i),
.DBITERR (),
.ENARDEN (1'b1),
.ENBWREN (1'b1),
.INJECTDBITERR (1'b0),
.INJECTSBITERR (1'b0),
.REGCEAREGCE (1'b1 ),
.REGCEB (1'b1 ),
.RSTRAMARSTRAM (1'b0),
.RSTRAMB (1'b0),
.RSTREGARSTREG (1'b0),
.RSTREGB (1'b0),
.SBITERR (),
.ADDRARDADDR ({1'b1, addr_i[8:0], 6'b0}),
.ADDRBWRADDR ({1'b1, addr_i[8:0], 1'b1, 5'b0}),
.DIADI (wdata_i[(2*32*i)+31:(2*32*i)+0]),
.DIBDI (wdata_i[(2*32*i)+63:(2*32*i)+32]),
.DIPADIP (wdip_i[(2*4*i)+3:(2*4*i)+0]),
.DIPBDIP (wdip_i[(2*4*i)+7:(2*4*i)+4]),
.DOADO (rdata_o[(2*32*i)+31:(2*32*i)+0]),
.DOBDO (rdata_o[(2*32*i)+63:(2*32*i)+32]),
.DOPADOP (rdop_o[(2*4*i)+3:(2*4*i)+0]),
.DOPBDOP (rdop_o[(2*4*i)+7:(2*4*i)+4]),
.ECCPARITY (),
.RDADDRECC (),
.WEA ({4{wen[i]}}),
.WEBWE ({4'b0, {4{wen[i]}}})
);
end
endgenerate
endmodule // pcie_bram_7vx_rep_8k
|
/*
* Wrapper with proper reset handling for Xilinx FIFOE1 components
*
* Copyright (C) 2017 Olof Kindgren <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
//TODO: Add support for FIFO36 primitives
module xilinx_fifoe1
#(parameter ADDR_WIDTH = 0,
parameter DATA_WIDTH = 0)
(input wire rst_i,
input wire wr_clk_i,
input wire wr_en_i,
input wire [DATA_WIDTH-1:0] wr_data_i,
output wire full_o,
input wire rd_clk_i,
input wire rd_en_i,
output wire [DATA_WIDTH-1:0] rd_data_o,
output wire empty_o);
localparam FIFO_MODE = (DATA_WIDTH > 18) ? "FIFO18_36" : "FIFO18";
localparam DATA_WIDTH_INT = (DATA_WIDTH <= 4) ? 4 :
(DATA_WIDTH <= 9) ? 9 :
(DATA_WIDTH <= 18) ? 18 :
36;
localparam DP_LSB = DATA_WIDTH_INT/9*8;
localparam PAD = DATA_WIDTH_INT-DATA_WIDTH;
wire [35:0] wr_data;
wire [35:0] rd_data;
reg [6:0] wr_rst_done = 7'd0;
reg [2:0] wr_en_mask = 1'b0;
wire wr_en;
wire full;
reg [6:0] rd_rst_done = 7'd0;
reg [2:0] rd_en_mask = 1'b0;
wire rd_en;
wire rst;
assign wr_data = {{PAD{1'b0}},wr_data_i};
assign rd_data_o = rd_data[DATA_WIDTH-1:0];
FIFO18E1 # (
.ALMOST_EMPTY_OFFSET (13'h0080),
.ALMOST_FULL_OFFSET (13'h0080),
.DATA_WIDTH (DATA_WIDTH_INT),
.DO_REG (1),
.EN_SYN ("FALSE"),
.FIFO_MODE (FIFO_MODE),
.FIRST_WORD_FALL_THROUGH ("FALSE"),
.INIT (36'h000000000),
.SIM_DEVICE ("7SERIES"),
.SRVAL (36'h000000000)
) fifo (
.RST (rst),
//WRCLK domain
.WRCLK (wr_clk_i),
.ALMOSTFULL (),
.DI (wr_data[31:0]),
.DIP (wr_data[35:32]),
.FULL (full),
.WRCOUNT (),
.WREN (wr_en),
.WRERR (),
//RDCLK domain
.RDCLK (rd_clk_i),
.DO (rd_data[31:0]),
.DOP (rd_data[35:32]),
.ALMOSTEMPTY (),
.EMPTY (empty_o),
.RDCOUNT (),
.RDEN (rd_en),
.RDERR (),
.REGCE (1'b1),
.RSTREG (1'b0)
);
//Reset must be asserted for five wr_clk cycles
always @(posedge wr_clk_i or rst_i) begin
wr_rst_done <= {wr_rst_done[5:0],1'b0};
if (rst_i) begin
wr_rst_done <= 7'b1111111;
end
end
//Reset must be asserted for five rd_clk cycles
always @(posedge rd_clk_i or rst_i) begin
rd_rst_done <= {rd_rst_done[5:0],1'b0};
if (rst_i) begin
rd_rst_done <= 7'b1111111;
end
end
assign rst = wr_rst_done[6] | rd_rst_done[6];
//wr_en must be deasserted for two wr_clk cycles after reset is released
always @(posedge wr_clk_i or posedge rst_i) begin
wr_en_mask <= {wr_en_mask[1:0],~rst};
if (rst_i)
wr_en_mask <= 3'b000;
end
assign wr_en = wr_en_i & wr_en_mask[2];
//Pretend FIFO is full until it's ready to receive data
assign full_o = full | ~wr_en_mask[2];
//rd_en must be deasserted for two rd_clk cycles after reset is released
always @(posedge rd_clk_i or posedge rst_i) begin
rd_en_mask <= {rd_en_mask[1:0],~rst};
if (rst_i)
rd_en_mask <= 3'b000;
end
assign rd_en = rd_en_i & rd_en_mask[2];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_MUX_4TO2_TB_V
`define SKY130_FD_SC_LS__UDP_MUX_4TO2_TB_V
/**
* udp_mux_4to2: Four to one multiplexer with 2 select controls
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__udp_mux_4to2.v"
module top();
// Inputs are registered
reg A0;
reg A1;
reg A2;
reg A3;
reg S0;
reg S1;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A0 = 1'bX;
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
S0 = 1'bX;
S1 = 1'bX;
#20 A0 = 1'b0;
#40 A1 = 1'b0;
#60 A2 = 1'b0;
#80 A3 = 1'b0;
#100 S0 = 1'b0;
#120 S1 = 1'b0;
#140 A0 = 1'b1;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 A3 = 1'b1;
#220 S0 = 1'b1;
#240 S1 = 1'b1;
#260 A0 = 1'b0;
#280 A1 = 1'b0;
#300 A2 = 1'b0;
#320 A3 = 1'b0;
#340 S0 = 1'b0;
#360 S1 = 1'b0;
#380 S1 = 1'b1;
#400 S0 = 1'b1;
#420 A3 = 1'b1;
#440 A2 = 1'b1;
#460 A1 = 1'b1;
#480 A0 = 1'b1;
#500 S1 = 1'bx;
#520 S0 = 1'bx;
#540 A3 = 1'bx;
#560 A2 = 1'bx;
#580 A1 = 1'bx;
#600 A0 = 1'bx;
end
sky130_fd_sc_ls__udp_mux_4to2 dut (.A0(A0), .A1(A1), .A2(A2), .A3(A3), .S0(S0), .S1(S1), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_MUX_4TO2_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR4BB_FUNCTIONAL_V
`define SKY130_FD_SC_LP__NOR4BB_FUNCTIONAL_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__nor4bb (
Y ,
A ,
B ,
C_N,
D_N
);
// Module ports
output Y ;
input A ;
input B ;
input C_N;
input D_N;
// Local signals
wire nor0_out ;
wire and0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y, nor0_out, C_N, D_N);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR4BB_FUNCTIONAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02/01/2016 12:02:10 PM
// Design Name:
// Module Name: Problem3
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Problem3(
input [2:0] OpCode,
input [3:0] A,
input [3:0] B,
output reg [3:0] Final,
output reg Status
);
always @ (A or B or OpCode)
begin
Status = 0;
case (OpCode)
3'b000: begin
Final = ~A;
end
3'b001: begin
Final = ~(A&B);
end
3'b010: begin
Final = ~(A|B);
end
3'b011: begin
Final = A ^ B;
end
3'b100: begin
Final = A + B;
if (A[3] == B[3] && Final[3] != B[3])
Status = 1;
end
3'b101: begin
Final = A - B;
if (A[3] == (B[3] ^ 1) && Final[3] != A[3])
Status = 1;
end
3'b110: begin
Final = B + 4'b0001;
if (0 == B[3] && Final[3] != B[3])
Status = 1;
end
3'b111: begin
Final = B - 4'b0001;
//1 usually used for subtraction
if (1 == B[3] && Final[3] != 1 )
Status = 1;
end
endcase
end
endmodule
|
// file: testclk_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge dut.clknetwork.mmcm_adv_inst.LOCKED)
module testclk_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 3.906*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bits of the sampling counters
wire [4:1] COUNT;
reg COUNTER_RESET = 0;
wire [4:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
real period1;
real ref_period1;
localparam ref_period1_clkin1 = (3.906*2*8.000*1000/8.000);
time prev_rise1;
real period2;
real ref_period2;
localparam ref_period2_clkin1 = (3.906*2*8*1000/8.000);
time prev_rise2;
real period3;
real ref_period3;
localparam ref_period3_clkin1 = (3.906*2*8*1000/8.000);
time prev_rise3;
real period4;
real ref_period4;
localparam ref_period4_clkin1 = (3.906*2*4*1000/8.000);
time prev_rise4;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
COUNTER_RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*20)
COUNTER_RESET = 0;
test_phase = "counting";
#(PER1*COUNT_PHASE);
if ((period1 -ref_period1_clkin1) <= 100 && (period1 -ref_period1_clkin1) >= -100) begin
$display("Freq of CLK_OUT[1] ( in MHz ) : %0f\n", 1000000/period1);
end else
$display("ERROR: Freq of CLK_OUT[1] is not correct");
if ((period2 -ref_period2_clkin1) <= 100 && (period2 -ref_period2_clkin1) >= -100) begin
$display("Freq of CLK_OUT[2] ( in MHz ) : %0f\n", 1000000/period2);
end else
$display("ERROR: Freq of CLK_OUT[2] is not correct");
if ((period3 -ref_period3_clkin1) <= 100 && (period3 -ref_period3_clkin1) >= -100) begin
$display("Freq of CLK_OUT[3] ( in MHz ) : %0f\n", 1000000/period3);
end else
$display("ERROR: Freq of CLK_OUT[3] is not correct");
if ((period4 -ref_period4_clkin1) <= 100 && (period4 -ref_period4_clkin1) >= -100) begin
$display("Freq of CLK_OUT[4] ( in MHz ) : %0f\n", 1000000/period4);
end else
$display("ERROR: Freq of CLK_OUT[4] is not correct");
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
testclk_exdes
#(
.TCQ (TCQ)
) dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT));
// Freq Check
initial
prev_rise1 = 0;
always @(posedge CLK_OUT[1])
begin
if (prev_rise1 != 0)
period1 = $time - prev_rise1;
prev_rise1 = $time;
end
initial
prev_rise2 = 0;
always @(posedge CLK_OUT[2])
begin
if (prev_rise2 != 0)
period2 = $time - prev_rise2;
prev_rise2 = $time;
end
initial
prev_rise3 = 0;
always @(posedge CLK_OUT[3])
begin
if (prev_rise3 != 0)
period3 = $time - prev_rise3;
prev_rise3 = $time;
end
initial
prev_rise4 = 0;
always @(posedge CLK_OUT[4])
begin
if (prev_rise4 != 0)
period4 = $time - prev_rise4;
prev_rise4 = $time;
end
endmodule
|
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: mult_21_coeff_26561.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.3 Build 178 02/12/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module mult_21_coeff_26561 (
clken,
clock,
dataa,
result);
input clken;
input clock;
input [20:0] dataa;
output [41:0] result;
wire [41:0] sub_wire0;
wire [20:0] sub_wire1 = 21'd26561;
wire [41:0] result = sub_wire0[41:0];
lpm_mult lpm_mult_component (
.clock (clock),
.datab (sub_wire1),
.clken (clken),
.dataa (dataa),
.result (sub_wire0),
.aclr (1'b0),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=NO,INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=1",
lpm_mult_component.lpm_pipeline = 3,
lpm_mult_component.lpm_representation = "SIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 21,
lpm_mult_component.lpm_widthb = 21,
lpm_mult_component.lpm_widthp = 42;
endmodule
|
// MBT 7/25/2014
// async credit counter
//
// In this design, there are two clock domains. The first
// clock domain (w_) receives incoming credits. The second
// clock domain (r_) spends the credits. The first clock domain
// never needs to know how many credits are spent; it just
// accumulates how many have been received. This accumulated
// value is passed as a gray-coded pointer across to the _r clock domain.
// The _r clock domain records how many credits have been spent. It starts
// with a negative value. There will be lag from the w_ domain to
// the r_ domain because of the synchronizers. So imagine, after reset,
// we start sending packets, decrementing the credit counter, but no
// credits are received. The _r pointer will advance until it reaches the w_
// pointer, and then avail will go low, and transmits will stop. Then the
// credits start arriving and the w_ is advanced. After a few cycles delay,
// the _r side will observe this change and start spending credits again.
//
// label all signals in this module accordingly:
//
// w_: signals in "receive credits" clock domain
// r_: signals in "spend credits" clock domain
//
// TOKENS vs. CREDITS. We support a feature here, which is the idea of a token.
// A token is worth multiple credits. We pass tokens through the fifo (so that
// the gray-coded values are still consecutive). The number of credits must
// be a power-of-two multiple of the number of tokens. The log of this value is set
// by lg_credit_to_token_decimation_p. Using tokens can be used to reduce
// the toggle rate of the w_clk_i signal, for example, if it is being run
// over a pin exterior to the chip.
//
// RESET: both resets must be asserted and w_ clock most be posedge (negedge) toggled
// at least once; and the r_ clock posedge toggled at least four times after that.
// This will be a sufficient number of clocks to pass through the synchronizers.
// This will need to be done explicitly for the credit clock.
//
// ASYNC RESET PROCEDURE:
// Step 1: Assert r_ reset.
// Step 2: w_ reset must be posedge/negedge toggled (0->1->0) at least once.
// w_ clock cannot toggle during this step.
// Step 3: r_ clock posedge toggled at least four times after that.
// Step 4: Deassert r_ reset.
//
// MARGIN: when credit counters are used to count outgoing packets, it is sometimes
// helpful to include extra bits of precision in case the latency is longer than
// expected and the downstream module needs more buffer space than originally planned.
// The downstream module can give back tokens right after reset before anything is sent,
// increasing the amount of margin the upstream module thinks it have. Of course, you
// need to have the flexibility of being able to change the downstream's buffer space
// to take advantage of this feature, but this is the case if the downstream module
// is an FPGA. The parameter extra_margin_p is the number of additional bits in the
// credit counter that should be added to accomodate this behaviour. So for example,
// extra_margin_p of 2 increases the credit capacity by 2X.
// The parameter count_negedge_p determines whether we count
// on negedge edge or positive edge of the clock.
`include "bsg_defines.v"
module bsg_async_credit_counter #(parameter `BSG_INV_PARAM(max_tokens_p )
, parameter `BSG_INV_PARAM(lg_credit_to_token_decimation_p )
, parameter count_negedge_p = 0
, parameter extra_margin_p = 0
, parameter check_excess_credits_p = 1
, parameter start_full_p = 1
, parameter use_async_w_reset_p = 0)
(
input w_clk_i
, input w_inc_token_i
, input w_reset_i
, input r_clk_i
, input r_reset_i
, input r_dec_credit_i
, input r_infinite_credits_i // basically suppress this module
, output r_credits_avail_o
);
// $clog2(x) is how many bits are required to represent
// x unique values. we need to represent 0..max_credits_p = max_credits_p+1 values.
localparam r_counter_width_lp = extra_margin_p+$clog2(max_tokens_p+1) + lg_credit_to_token_decimation_p;
localparam w_counter_width_lp = extra_margin_p+$clog2(max_tokens_p+1);
logic [r_counter_width_lp-1:0] r_counter_r;
logic [w_counter_width_lp-1:0] w_counter_gray_r, w_counter_gray_r_rsync, w_counter_binary_r_rsync;
always @(posedge r_clk_i)
if (r_reset_i)
// fixme? not sure this constant will always do as expected
r_counter_r <= { -max_tokens_p * start_full_p, { lg_credit_to_token_decimation_p {1'b0} } };
else
r_counter_r <= r_counter_r + r_dec_credit_i;
// *********** this is basically an async_ptr: begin factor
bsg_async_ptr_gray #(.lg_size_p(w_counter_width_lp)
,.use_negedge_for_launch_p(count_negedge_p)
,.use_async_reset_p(use_async_w_reset_p)) bapg
(.w_clk_i(w_clk_i)
,.w_reset_i(w_reset_i)
,.w_inc_i(w_inc_token_i)
,.r_clk_i(r_clk_i)
,.w_ptr_binary_r_o() // we don't care about the binary version of the ptr on w side
,.w_ptr_gray_r_o(w_counter_gray_r) // synchronized with w clock domain
,.w_ptr_gray_r_rsync_o(w_counter_gray_r_rsync) // synchronized with r clock domain
);
/*
previously, we converted w_counter to binary, appended lg_credit_to_token_decimation 1'b0's and compared them
but instead, we convert the other way now.
assign r_credits_avail_o = r_infinite_credits_i | ~(w_counter_binary_r_rsync_padded == r_counter_r);
*/
wire [w_counter_width_lp-1:0] r_counter_r_hi_bits = r_counter_r[lg_credit_to_token_decimation_p+:w_counter_width_lp];
wire r_counter_r_lo_bits_nonzero;
if (lg_credit_to_token_decimation_p == 0)
assign r_counter_r_lo_bits_nonzero = 1'b0;
else
assign r_counter_r_lo_bits_nonzero = | r_counter_r[0+:lg_credit_to_token_decimation_p];
wire [w_counter_width_lp-1:0] r_counter_r_hi_bits_gray = (r_counter_r_hi_bits >> 1) ^ r_counter_r_hi_bits;
assign r_credits_avail_o = r_infinite_credits_i | r_counter_r_lo_bits_nonzero | (r_counter_r_hi_bits_gray != w_counter_gray_r_rsync);
// ***************************************
// for debug
//
//
// synopsys translate_off
bsg_gray_to_binary #(.width_p(w_counter_width_lp)) bsg_g2b
(.gray_i(w_counter_gray_r_rsync)
,.binary_o(w_counter_binary_r_rsync)
);
wire [r_counter_width_lp-1:0] w_counter_binary_r_rsync_padded = { w_counter_binary_r_rsync, { lg_credit_to_token_decimation_p {1'b0 } }};
wire [r_counter_width_lp-1:0] r_free_credits = w_counter_binary_r_rsync_padded - r_counter_r;
logic [r_counter_width_lp-1:0] r_free_credits_r;
always @(posedge r_clk_i)
r_free_credits_r <= r_free_credits;
if (check_excess_credits_p)
always @(r_free_credits_r)
assert(r_reset_i
| r_infinite_credits_i
| (r_free_credits_r <= (max_tokens_p << lg_credit_to_token_decimation_p)))
else $error("too many credits in credit counter %d (> %3d)"
, r_free_credits_r
, max_tokens_p << lg_credit_to_token_decimation_p
);
always @(negedge r_clk_i)
assert (!(r_dec_credit_i===1 && r_credits_avail_o===0))
else $error("decrementing empty credit counter");
// synopsys translate_on
//
// end debug
//
// ****************************************
endmodule
`BSG_ABSTRACT_MODULE(bsg_async_credit_counter)
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2018 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2018.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Fast Carry Logic with Look Ahead
// /___/ /\ Filename : CARRY4.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 04/11/05 - Initial version.
// 05/06/05 - Unused CYINT or CI pin need grounded instead of open (CR207752)
// 05/31/05 - Change pin order, remove connection check for CYINIT and CI.
// 12/21/05 - Add timing path.
// 04/13/06 - Add full timing path for DI to O (CR228786)
// 06/04/07 - Add wire definition.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 04/13/12 - CR655410 - add pulldown, CI, CYINIT, sync uni/sim/unp
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module CARRY4
`ifdef XIL_TIMING
#(
parameter LOC = "UNPLACED"
)
`endif
(
output [3:0] CO,
output [3:0] O,
input CI,
input CYINIT,
input [3:0] DI,
input [3:0] S
);
// define constants
localparam MODULE_NAME = "CARRY4";
`ifdef XIL_XECLIB
reg glblGSR = 1'b0;
`else
tri0 glblGSR = glbl.GSR;
`endif
wire CI_in;
wire CYINIT_in;
wire [3:0] DI_in;
wire [3:0] S_in;
assign CI_in = (CI !== 1'bz) && CI; // rv 0
assign CYINIT_in = (CYINIT !== 1'bz) && CYINIT; // rv 0
assign DI_in = DI;
assign S_in = S;
// begin behavioral model
wire [3:0] CO_fb;
assign CO_fb = {CO[2:0], CI_in || CYINIT_in};
assign O = S_in ^ CO_fb;
assign CO = (S_in & CO_fb) | (~S_in & DI_in);
// end behavioral model
`ifndef XIL_XECLIB
`ifdef XIL_TIMING
specify
(CI => CO[0]) = (0:0:0, 0:0:0);
(CI => CO[1]) = (0:0:0, 0:0:0);
(CI => CO[2]) = (0:0:0, 0:0:0);
(CI => CO[3]) = (0:0:0, 0:0:0);
(CI => O[0]) = (0:0:0, 0:0:0);
(CI => O[1]) = (0:0:0, 0:0:0);
(CI => O[2]) = (0:0:0, 0:0:0);
(CI => O[3]) = (0:0:0, 0:0:0);
(CYINIT => CO[0]) = (0:0:0, 0:0:0);
(CYINIT => CO[1]) = (0:0:0, 0:0:0);
(CYINIT => CO[2]) = (0:0:0, 0:0:0);
(CYINIT => CO[3]) = (0:0:0, 0:0:0);
(CYINIT => O[0]) = (0:0:0, 0:0:0);
(CYINIT => O[1]) = (0:0:0, 0:0:0);
(CYINIT => O[2]) = (0:0:0, 0:0:0);
(CYINIT => O[3]) = (0:0:0, 0:0:0);
(DI[0] => CO[0]) = (0:0:0, 0:0:0);
(DI[0] => CO[1]) = (0:0:0, 0:0:0);
(DI[0] => CO[2]) = (0:0:0, 0:0:0);
(DI[0] => CO[3]) = (0:0:0, 0:0:0);
(DI[0] => O[0]) = (0:0:0, 0:0:0);
(DI[0] => O[1]) = (0:0:0, 0:0:0);
(DI[0] => O[2]) = (0:0:0, 0:0:0);
(DI[0] => O[3]) = (0:0:0, 0:0:0);
(DI[1] => CO[0]) = (0:0:0, 0:0:0);
(DI[1] => CO[1]) = (0:0:0, 0:0:0);
(DI[1] => CO[2]) = (0:0:0, 0:0:0);
(DI[1] => CO[3]) = (0:0:0, 0:0:0);
(DI[1] => O[0]) = (0:0:0, 0:0:0);
(DI[1] => O[1]) = (0:0:0, 0:0:0);
(DI[1] => O[2]) = (0:0:0, 0:0:0);
(DI[1] => O[3]) = (0:0:0, 0:0:0);
(DI[2] => CO[0]) = (0:0:0, 0:0:0);
(DI[2] => CO[1]) = (0:0:0, 0:0:0);
(DI[2] => CO[2]) = (0:0:0, 0:0:0);
(DI[2] => CO[3]) = (0:0:0, 0:0:0);
(DI[2] => O[0]) = (0:0:0, 0:0:0);
(DI[2] => O[1]) = (0:0:0, 0:0:0);
(DI[2] => O[2]) = (0:0:0, 0:0:0);
(DI[2] => O[3]) = (0:0:0, 0:0:0);
(DI[3] => CO[0]) = (0:0:0, 0:0:0);
(DI[3] => CO[1]) = (0:0:0, 0:0:0);
(DI[3] => CO[2]) = (0:0:0, 0:0:0);
(DI[3] => CO[3]) = (0:0:0, 0:0:0);
(DI[3] => O[0]) = (0:0:0, 0:0:0);
(DI[3] => O[1]) = (0:0:0, 0:0:0);
(DI[3] => O[2]) = (0:0:0, 0:0:0);
(DI[3] => O[3]) = (0:0:0, 0:0:0);
(S[0] => CO[0]) = (0:0:0, 0:0:0);
(S[0] => CO[1]) = (0:0:0, 0:0:0);
(S[0] => CO[2]) = (0:0:0, 0:0:0);
(S[0] => CO[3]) = (0:0:0, 0:0:0);
(S[0] => O[0]) = (0:0:0, 0:0:0);
(S[0] => O[1]) = (0:0:0, 0:0:0);
(S[0] => O[2]) = (0:0:0, 0:0:0);
(S[0] => O[3]) = (0:0:0, 0:0:0);
(S[1] => CO[0]) = (0:0:0, 0:0:0);
(S[1] => CO[1]) = (0:0:0, 0:0:0);
(S[1] => CO[2]) = (0:0:0, 0:0:0);
(S[1] => CO[3]) = (0:0:0, 0:0:0);
(S[1] => O[0]) = (0:0:0, 0:0:0);
(S[1] => O[1]) = (0:0:0, 0:0:0);
(S[1] => O[2]) = (0:0:0, 0:0:0);
(S[1] => O[3]) = (0:0:0, 0:0:0);
(S[2] => CO[0]) = (0:0:0, 0:0:0);
(S[2] => CO[1]) = (0:0:0, 0:0:0);
(S[2] => CO[2]) = (0:0:0, 0:0:0);
(S[2] => CO[3]) = (0:0:0, 0:0:0);
(S[2] => O[0]) = (0:0:0, 0:0:0);
(S[2] => O[1]) = (0:0:0, 0:0:0);
(S[2] => O[2]) = (0:0:0, 0:0:0);
(S[2] => O[3]) = (0:0:0, 0:0:0);
(S[3] => CO[0]) = (0:0:0, 0:0:0);
(S[3] => CO[1]) = (0:0:0, 0:0:0);
(S[3] => CO[2]) = (0:0:0, 0:0:0);
(S[3] => CO[3]) = (0:0:0, 0:0:0);
(S[3] => O[0]) = (0:0:0, 0:0:0);
(S[3] => O[1]) = (0:0:0, 0:0:0);
(S[3] => O[2]) = (0:0:0, 0:0:0);
(S[3] => O[3]) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
`endif
endmodule
`endcelldefine
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 15:19:41 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ led_controller_design_rst_ps7_0_100M_0_sim_netlist.v
// Design : led_controller_design_rst_ps7_0_100M_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
(lpf_asr_reg,
scndry_out,
lpf_asr,
asr_lpf,
p_1_in,
p_2_in,
aux_reset_in,
slowest_sync_clk);
output lpf_asr_reg;
output scndry_out;
input lpf_asr;
input [0:0]asr_lpf;
input p_1_in;
input p_2_in;
input aux_reset_in;
input slowest_sync_clk;
wire asr_d1;
wire [0:0]asr_lpf;
wire aux_reset_in;
wire lpf_asr;
wire lpf_asr_reg;
wire p_1_in;
wire p_2_in;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scndry_out;
wire slowest_sync_clk;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(slowest_sync_clk),
.CE(1'b1),
.D(asr_d1),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1
(.I0(aux_reset_in),
.O(asr_d1));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(s_level_out_d2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d2),
.Q(s_level_out_d3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d3),
.Q(scndry_out),
.R(1'b0));
LUT5 #(
.INIT(32'hEAAAAAA8))
lpf_asr_i_1
(.I0(lpf_asr),
.I1(asr_lpf),
.I2(scndry_out),
.I3(p_1_in),
.I4(p_2_in),
.O(lpf_asr_reg));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0
(lpf_exr_reg,
scndry_out,
lpf_exr,
p_3_out,
mb_debug_sys_rst,
ext_reset_in,
slowest_sync_clk);
output lpf_exr_reg;
output scndry_out;
input lpf_exr;
input [2:0]p_3_out;
input mb_debug_sys_rst;
input ext_reset_in;
input slowest_sync_clk;
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ;
wire ext_reset_in;
wire lpf_exr;
wire lpf_exr_reg;
wire mb_debug_sys_rst;
wire [2:0]p_3_out;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scndry_out;
wire slowest_sync_clk;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
LUT2 #(
.INIT(4'hB))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0
(.I0(mb_debug_sys_rst),
.I1(ext_reset_in),
.O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(s_level_out_d2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d2),
.Q(s_level_out_d3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d3),
.Q(scndry_out),
.R(1'b0));
LUT5 #(
.INIT(32'hEAAAAAA8))
lpf_exr_i_1
(.I0(lpf_exr),
.I1(p_3_out[0]),
.I2(scndry_out),
.I3(p_3_out[1]),
.I4(p_3_out[2]),
.O(lpf_exr_reg));
endmodule
(* CHECK_LICENSE_TYPE = "led_controller_design_rst_ps7_0_100M_0,proc_sys_reset,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "proc_sys_reset,Vivado 2017.3" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN led_controller_design_processing_system7_0_0_FCLK_CLK0" *) input slowest_sync_clk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 ext_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW" *) input ext_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 aux_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW" *) input aux_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH" *) input mb_debug_sys_rst;
input dcm_locked;
(* x_interface_info = "xilinx.com:signal:reset:1.0 mb_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR" *) output mb_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 bus_struct_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT" *) output [0:0]bus_struct_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_high_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL" *) output [0:0]peripheral_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 interconnect_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT" *) output [0:0]interconnect_aresetn;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL" *) output [0:0]peripheral_aresetn;
wire aux_reset_in;
wire [0:0]bus_struct_reset;
wire dcm_locked;
wire ext_reset_in;
wire [0:0]interconnect_aresetn;
wire mb_debug_sys_rst;
wire mb_reset;
wire [0:0]peripheral_aresetn;
wire [0:0]peripheral_reset;
wire slowest_sync_clk;
(* C_AUX_RESET_HIGH = "1'b0" *)
(* C_AUX_RST_WIDTH = "4" *)
(* C_EXT_RESET_HIGH = "1'b0" *)
(* C_EXT_RST_WIDTH = "4" *)
(* C_FAMILY = "zynq" *)
(* C_NUM_BUS_RST = "1" *)
(* C_NUM_INTERCONNECT_ARESETN = "1" *)
(* C_NUM_PERP_ARESETN = "1" *)
(* C_NUM_PERP_RST = "1" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset U0
(.aux_reset_in(aux_reset_in),
.bus_struct_reset(bus_struct_reset),
.dcm_locked(dcm_locked),
.ext_reset_in(ext_reset_in),
.interconnect_aresetn(interconnect_aresetn),
.mb_debug_sys_rst(mb_debug_sys_rst),
.mb_reset(mb_reset),
.peripheral_aresetn(peripheral_aresetn),
.peripheral_reset(peripheral_reset),
.slowest_sync_clk(slowest_sync_clk));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf
(lpf_int,
slowest_sync_clk,
dcm_locked,
aux_reset_in,
mb_debug_sys_rst,
ext_reset_in);
output lpf_int;
input slowest_sync_clk;
input dcm_locked;
input aux_reset_in;
input mb_debug_sys_rst;
input ext_reset_in;
wire \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ;
wire \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ;
wire Q;
wire [0:0]asr_lpf;
wire aux_reset_in;
wire dcm_locked;
wire ext_reset_in;
wire lpf_asr;
wire lpf_exr;
wire lpf_int;
wire lpf_int0__0;
wire mb_debug_sys_rst;
wire p_1_in;
wire p_2_in;
wire p_3_in1_in;
wire [3:0]p_3_out;
wire slowest_sync_clk;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync \ACTIVE_LOW_AUX.ACT_LO_AUX
(.asr_lpf(asr_lpf),
.aux_reset_in(aux_reset_in),
.lpf_asr(lpf_asr),
.lpf_asr_reg(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
.p_1_in(p_1_in),
.p_2_in(p_2_in),
.scndry_out(p_3_in1_in),
.slowest_sync_clk(slowest_sync_clk));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 \ACTIVE_LOW_EXT.ACT_LO_EXT
(.ext_reset_in(ext_reset_in),
.lpf_exr(lpf_exr),
.lpf_exr_reg(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
.mb_debug_sys_rst(mb_debug_sys_rst),
.p_3_out(p_3_out[2:0]),
.scndry_out(p_3_out[3]),
.slowest_sync_clk(slowest_sync_clk));
FDRE #(
.INIT(1'b0))
\AUX_LPF[1].asr_lpf_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_in1_in),
.Q(p_2_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\AUX_LPF[2].asr_lpf_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_2_in),
.Q(p_1_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\AUX_LPF[3].asr_lpf_reg[3]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_1_in),
.Q(asr_lpf),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[1].exr_lpf_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[3]),
.Q(p_3_out[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[2].exr_lpf_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[2]),
.Q(p_3_out[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[3].exr_lpf_reg[3]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[1]),
.Q(p_3_out[0]),
.R(1'b0));
(* XILINX_LEGACY_PRIM = "SRL16" *)
(* box_type = "PRIMITIVE" *)
(* srl_name = "U0/\EXT_LPF/POR_SRL_I " *)
SRL16E #(
.INIT(16'hFFFF))
POR_SRL_I
(.A0(1'b1),
.A1(1'b1),
.A2(1'b1),
.A3(1'b1),
.CE(1'b1),
.CLK(slowest_sync_clk),
.D(1'b0),
.Q(Q));
FDRE #(
.INIT(1'b0))
lpf_asr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
.Q(lpf_asr),
.R(1'b0));
FDRE #(
.INIT(1'b0))
lpf_exr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
.Q(lpf_exr),
.R(1'b0));
LUT4 #(
.INIT(16'hFFEF))
lpf_int0
(.I0(Q),
.I1(lpf_asr),
.I2(dcm_locked),
.I3(lpf_exr),
.O(lpf_int0__0));
FDRE #(
.INIT(1'b0))
lpf_int_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(lpf_int0__0),
.Q(lpf_int),
.R(1'b0));
endmodule
(* C_AUX_RESET_HIGH = "1'b0" *) (* C_AUX_RST_WIDTH = "4" *) (* C_EXT_RESET_HIGH = "1'b0" *)
(* C_EXT_RST_WIDTH = "4" *) (* C_FAMILY = "zynq" *) (* C_NUM_BUS_RST = "1" *)
(* C_NUM_INTERCONNECT_ARESETN = "1" *) (* C_NUM_PERP_ARESETN = "1" *) (* C_NUM_PERP_RST = "1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset
(slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn);
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
(* equivalent_register_removal = "no" *) output [0:0]bus_struct_reset;
(* equivalent_register_removal = "no" *) output [0:0]peripheral_reset;
(* equivalent_register_removal = "no" *) output [0:0]interconnect_aresetn;
(* equivalent_register_removal = "no" *) output [0:0]peripheral_aresetn;
wire Bsr_out;
wire MB_out;
wire Pr_out;
wire SEQ_n_3;
wire SEQ_n_4;
wire aux_reset_in;
wire [0:0]bus_struct_reset;
wire dcm_locked;
wire ext_reset_in;
wire [0:0]interconnect_aresetn;
wire lpf_int;
wire mb_debug_sys_rst;
wire mb_reset;
wire [0:0]peripheral_aresetn;
wire [0:0]peripheral_reset;
wire slowest_sync_clk;
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N
(.C(slowest_sync_clk),
.CE(1'b1),
.D(SEQ_n_3),
.Q(interconnect_aresetn),
.R(1'b0));
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N
(.C(slowest_sync_clk),
.CE(1'b1),
.D(SEQ_n_4),
.Q(peripheral_aresetn),
.R(1'b0));
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\BSR_OUT_DFF[0].FDRE_BSR
(.C(slowest_sync_clk),
.CE(1'b1),
.D(Bsr_out),
.Q(bus_struct_reset),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf EXT_LPF
(.aux_reset_in(aux_reset_in),
.dcm_locked(dcm_locked),
.ext_reset_in(ext_reset_in),
.lpf_int(lpf_int),
.mb_debug_sys_rst(mb_debug_sys_rst),
.slowest_sync_clk(slowest_sync_clk));
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
FDRE_inst
(.C(slowest_sync_clk),
.CE(1'b1),
.D(MB_out),
.Q(mb_reset),
.R(1'b0));
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\PR_OUT_DFF[0].FDRE_PER
(.C(slowest_sync_clk),
.CE(1'b1),
.D(Pr_out),
.Q(peripheral_reset),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr SEQ
(.\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N (SEQ_n_3),
.\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N (SEQ_n_4),
.Bsr_out(Bsr_out),
.MB_out(MB_out),
.Pr_out(Pr_out),
.lpf_int(lpf_int),
.slowest_sync_clk(slowest_sync_clk));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr
(MB_out,
Bsr_out,
Pr_out,
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N ,
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N ,
lpf_int,
slowest_sync_clk);
output MB_out;
output Bsr_out;
output Pr_out;
output \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N ;
output \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N ;
input lpf_int;
input slowest_sync_clk;
wire \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N ;
wire \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N ;
wire Bsr_out;
wire Core_i_1_n_0;
wire MB_out;
wire Pr_out;
wire \bsr_dec_reg_n_0_[0] ;
wire \bsr_dec_reg_n_0_[2] ;
wire bsr_i_1_n_0;
wire \core_dec[0]_i_1_n_0 ;
wire \core_dec[2]_i_1_n_0 ;
wire \core_dec_reg_n_0_[0] ;
wire \core_dec_reg_n_0_[1] ;
wire from_sys_i_1_n_0;
wire lpf_int;
wire p_0_in;
wire [2:0]p_3_out;
wire [2:0]p_5_out;
wire pr_dec0__0;
wire \pr_dec_reg_n_0_[0] ;
wire \pr_dec_reg_n_0_[2] ;
wire pr_i_1_n_0;
wire seq_clr;
wire [5:0]seq_cnt;
wire seq_cnt_en;
wire slowest_sync_clk;
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT1 #(
.INIT(2'h1))
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1
(.I0(Bsr_out),
.O(\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT1 #(
.INIT(2'h1))
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1
(.I0(Pr_out),
.O(\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h2))
Core_i_1
(.I0(MB_out),
.I1(p_0_in),
.O(Core_i_1_n_0));
FDSE #(
.INIT(1'b1))
Core_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(Core_i_1_n_0),
.Q(MB_out),
.S(lpf_int));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n SEQ_COUNTER
(.Q(seq_cnt),
.seq_clr(seq_clr),
.seq_cnt_en(seq_cnt_en),
.slowest_sync_clk(slowest_sync_clk));
LUT4 #(
.INIT(16'h0804))
\bsr_dec[0]_i_1
(.I0(seq_cnt_en),
.I1(seq_cnt[3]),
.I2(seq_cnt[5]),
.I3(seq_cnt[4]),
.O(p_5_out[0]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h8))
\bsr_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\bsr_dec_reg_n_0_[0] ),
.O(p_5_out[2]));
FDRE #(
.INIT(1'b0))
\bsr_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_5_out[0]),
.Q(\bsr_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bsr_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_5_out[2]),
.Q(\bsr_dec_reg_n_0_[2] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h2))
bsr_i_1
(.I0(Bsr_out),
.I1(\bsr_dec_reg_n_0_[2] ),
.O(bsr_i_1_n_0));
FDSE #(
.INIT(1'b1))
bsr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(bsr_i_1_n_0),
.Q(Bsr_out),
.S(lpf_int));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h8040))
\core_dec[0]_i_1
(.I0(seq_cnt[4]),
.I1(seq_cnt[3]),
.I2(seq_cnt[5]),
.I3(seq_cnt_en),
.O(\core_dec[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h8))
\core_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\core_dec_reg_n_0_[0] ),
.O(\core_dec[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\core_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\core_dec[0]_i_1_n_0 ),
.Q(\core_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\core_dec_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(pr_dec0__0),
.Q(\core_dec_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\core_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\core_dec[2]_i_1_n_0 ),
.Q(p_0_in),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
from_sys_i_1
(.I0(MB_out),
.I1(seq_cnt_en),
.O(from_sys_i_1_n_0));
FDSE #(
.INIT(1'b0))
from_sys_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(from_sys_i_1_n_0),
.Q(seq_cnt_en),
.S(lpf_int));
LUT4 #(
.INIT(16'h0210))
pr_dec0
(.I0(seq_cnt[0]),
.I1(seq_cnt[1]),
.I2(seq_cnt[2]),
.I3(seq_cnt_en),
.O(pr_dec0__0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h1080))
\pr_dec[0]_i_1
(.I0(seq_cnt_en),
.I1(seq_cnt[5]),
.I2(seq_cnt[3]),
.I3(seq_cnt[4]),
.O(p_3_out[0]));
LUT2 #(
.INIT(4'h8))
\pr_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\pr_dec_reg_n_0_[0] ),
.O(p_3_out[2]));
FDRE #(
.INIT(1'b0))
\pr_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[0]),
.Q(\pr_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\pr_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[2]),
.Q(\pr_dec_reg_n_0_[2] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h2))
pr_i_1
(.I0(Pr_out),
.I1(\pr_dec_reg_n_0_[2] ),
.O(pr_i_1_n_0));
FDSE #(
.INIT(1'b1))
pr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(pr_i_1_n_0),
.Q(Pr_out),
.S(lpf_int));
FDRE #(
.INIT(1'b0))
seq_clr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(1'b1),
.Q(seq_clr),
.R(lpf_int));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n
(Q,
seq_clr,
seq_cnt_en,
slowest_sync_clk);
output [5:0]Q;
input seq_clr;
input seq_cnt_en;
input slowest_sync_clk;
wire [5:0]Q;
wire clear;
wire [5:0]q_int0;
wire seq_clr;
wire seq_cnt_en;
wire slowest_sync_clk;
LUT1 #(
.INIT(2'h1))
\q_int[0]_i_1
(.I0(Q[0]),
.O(q_int0[0]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\q_int[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(q_int0[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h78))
\q_int[2]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O(q_int0[2]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7F80))
\q_int[3]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(q_int0[3]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h7FFF8000))
\q_int[4]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O(q_int0[4]));
LUT1 #(
.INIT(2'h1))
\q_int[5]_i_1
(.I0(seq_clr),
.O(clear));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\q_int[5]_i_2
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[4]),
.I5(Q[5]),
.O(q_int0[5]));
FDRE #(
.INIT(1'b1))
\q_int_reg[0]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[0]),
.Q(Q[0]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[1]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[1]),
.Q(Q[1]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[2]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[2]),
.Q(Q[2]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[3]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[3]),
.Q(Q[3]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[4]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[4]),
.Q(Q[4]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[5]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[5]),
.Q(Q[5]),
.R(clear));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O31AI_PP_SYMBOL_V
`define SKY130_FD_SC_HS__O31AI_PP_SYMBOL_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o31ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O31AI_PP_SYMBOL_V
|
module clkgen(input wire clkin, input wire clk25m_on, output wire clkout, output wire [3:0] clk25m, output wire locked);
//reg cnt ;
wire clkout_div ;
//always @ ( posedge clkout )
// cnt <= ~cnt ;
//assign clk25m = cnt ;
//assign clk25m = clkout_div ;
ODDR2 ODDR2_inst0 (
.Q (clk25m[0]), // 1-bit DDR output data
.C0(clkout_div), // 1-bit clock input
.C1(~clkout_div), // 1-bit clock input
.CE(clk25m_on),//(1), // 1-bit clock enable input
.D0(0), // 1-bit data input (associated with C0)
.D1(1), // 1-bit data input (associated with C1)
.R (0), // 1-bit reset input
.S (0) // 1-bit set input
);
ODDR2 ODDR2_inst1 (
.Q (clk25m[1]), // 1-bit DDR output data
.C0(clkout_div), // 1-bit clock input
.C1(~clkout_div), // 1-bit clock input
.CE(clk25m_on),//(1), // 1-bit clock enable input
.D0(0), // 1-bit data input (associated with C0)
.D1(1), // 1-bit data input (associated with C1)
.R (0), // 1-bit reset input
.S (0) // 1-bit set input
);
ODDR2 ODDR2_inst2 (
.Q (clk25m[2]), // 1-bit DDR output data
.C0(clkout_div), // 1-bit clock input
.C1(~clkout_div), // 1-bit clock input
.CE(clk25m_on),//(1), // 1-bit clock enable input
.D0(0), // 1-bit data input (associated with C0)
.D1(1), // 1-bit data input (associated with C1)
.R (0), // 1-bit reset input
.S (0) // 1-bit set input
);
ODDR2 ODDR2_inst3 (
.Q (clk25m[3]), // 1-bit DDR output data
.C0(clkout_div), // 1-bit clock input
.C1(~clkout_div), // 1-bit clock input
.CE(clk25m_on),//(1), // 1-bit clock enable input
.D0(0), // 1-bit data input (associated with C0)
.D1(1), // 1-bit data input (associated with C1)
.R (0), // 1-bit reset input
.S (0) // 1-bit set input
);
DCM_CLKGEN #( // {{{
.CLKFXDV_DIVIDE(4), // CLKFXDV divide value (2, 4, 8, 16, 32)
.CLKFX_DIVIDE(1), // Divide value - D - (1-256)
.CLKFX_MD_MAX(0.0), // Specify maximum M/D ratio for timing anlysis
.CLKFX_MULTIPLY(4), // Multiply value - M - (2-256)
.CLKIN_PERIOD(40.0), // Input clock period specified in nS
.SPREAD_SPECTRUM("NONE"), // Spread Spectrum mode "NONE", "CENTER_LOW_SPREAD", "CENTER_HIGH_SPREAD",
// "VIDEO_LINK_M0", "VIDEO_LINK_M1" or "VIDEO_LINK_M2"
.STARTUP_WAIT("FALSE") // Delay config DONE until DCM_CLKGEN LOCKED (TRUE/FALSE)
) DCM (
.CLKFX(clkout), // 1-bit output: Generated clock output
.CLKFX180(), // 1-bit output: Generated clock output 180 degree out of phase from CLKFX.
.CLKFXDV(clkout_div), // 1-bit output: Divided clock output
.LOCKED(locked), // 1-bit output: Locked output
.PROGDONE(), // 1-bit output: Active high output to indicate the successful re-programming
.STATUS(), // 2-bit output: DCM_CLKGEN status
.CLKIN(clkin), // 1-bit input: Input clock
.FREEZEDCM(1'b0), // 1-bit input: Prevents frequency adjustments to input clock
.PROGCLK(1'b0), // 1-bit input: Clock input for M/D reconfiguration
.PROGDATA(1'b0), // 1-bit input: Serial data input for M/D reconfiguration
.PROGEN(1'b0), // 1-bit input: Active high program enable
.RST(1'b0) // 1-bit input: Reset input pin
); // }}}
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR3_4_V
`define SKY130_FD_SC_HD__OR3_4_V
/**
* or3: 3-input OR.
*
* Verilog wrapper for or3 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__or3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__or3_4 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__or3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR3_4_V
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module m26_rx
#(
parameter BASEADDR = 16'h0000,
parameter HIGHADDR = 16'h0000,
parameter ABUSWIDTH = 16,
parameter HEADER = 0,
parameter IDENTYFIER = 0
)(
input wire BUS_CLK,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RST,
input wire BUS_WR,
input wire BUS_RD,
input wire CLK_RX,
input wire MKD_RX,
input wire [1:0] DATA_RX,
input wire FIFO_READ,
output wire FIFO_EMPTY,
output wire [31:0] FIFO_DATA,
input wire [31:0] TIMESTAMP,
output wire LOST_ERROR
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
bus_to_ip #( .BASEADDR(BASEADDR), .HIGHADDR(HIGHADDR), .ABUSWIDTH(ABUSWIDTH) ) i_bus_to_ip
(
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
m26_rx_core
#(
.ABUSWIDTH(ABUSWIDTH),
.IDENTYFIER(IDENTYFIER),
.HEADER(HEADER)
) i_m26_rx_core
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.BUS_DATA_OUT(IP_DATA_OUT),
.CLK_RX(CLK_RX),
.MKD_RX(MKD_RX),
.DATA_RX(DATA_RX),
.FIFO_READ(FIFO_READ),
.FIFO_EMPTY(FIFO_EMPTY),
.FIFO_DATA(FIFO_DATA),
.TIMESTAMP(TIMESTAMP),
.LOST_ERROR(LOST_ERROR)
);
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 4
(* X_CORE_INFO = "axi_protocol_converter_v2_1_axi_protocol_converter,Vivado 2014.4" *)
(* CHECK_LICENSE_TYPE = "system_auto_pc_0,axi_protocol_converter_v2_1_axi_protocol_converter,{}" *)
(* CORE_GENERATION_INFO = "system_auto_pc_0,axi_protocol_converter_v2_1_axi_protocol_converter,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=1,C_IGNORE_ID=0,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module system_auto_pc_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
input wire [11 : 0] s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [3 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(1),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(12'H000),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(12'H000),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
// megafunction wizard: %RAM: 2-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: dpram_64_32x32_be.v
// Megafunction Name(s):
// altsyncram
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.2 Build 157 12/07/2004 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module dpram_64_32x32_be (
data,
wren,
wraddress,
rdaddress,
byteena_a,
wrclock,
rdclock,
q);
input [63:0] data;
input wren;
input [4:0] wraddress;
input [5:0] rdaddress;
input [7:0] byteena_a;
input wrclock;
input rdclock;
output [31:0] q;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "64"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "64"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "2048"
// Retrieval info: PRIVATE: Clock NUMERIC "1"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: UseLCs NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "64"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "6"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "64"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "8"
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL data[63..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
// Retrieval info: USED_PORT: wraddress 0 0 5 0 INPUT NODEFVAL wraddress[4..0]
// Retrieval info: USED_PORT: rdaddress 0 0 6 0 INPUT NODEFVAL rdaddress[5..0]
// Retrieval info: USED_PORT: byteena_a 0 0 8 0 INPUT VCC byteena_a[7..0]
// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT NODEFVAL wrclock
// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL rdclock
// Retrieval info: CONNECT: @data_a 0 0 64 0 data 0 0 64 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: CONNECT: @address_a 0 0 5 0 wraddress 0 0 5 0
// Retrieval info: CONNECT: @address_b 0 0 6 0 rdaddress 0 0 6 0
// Retrieval info: CONNECT: @byteena_a 0 0 8 0 byteena_a 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_64_32x32_be.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_64_32x32_be.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_64_32x32_be.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_64_32x32_be.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_64_32x32_be_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_64_32x32_be_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_64_32x32_be_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_64_32x32_be_wave*.jpg FALSE
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND2_BLACKBOX_V
`define SKY130_FD_SC_MS__AND2_BLACKBOX_V
/**
* and2: 2-input AND.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__and2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND2_BLACKBOX_V
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
// Behavioral model for the register file
module RegFileWW (rd1data,rd2data,wrdata,rd1addr,rd2addr,wraddr,
rd1en,rd2en,wren,wrbyteen,clk);
// Definitions for the constants the advanced register file
// parameter PARAM_NAME = VALUE;
// ===============================================================
// Output signals...
/**
* Output data that's read from the 2 ports of the advanced
* register file: data from Port 1 and Port 2
*
* Stay at high impedance state if no read operation is performed
*/
output [127:0] rd1data,rd2data;
// ===============================================================
// Input signals
// Input data coming into the write port of the register file
input [0:127] wrdata;
// Clock signal to facilitate state transitions
input clk;
// Write enable signal to facilitate writing signals; active-high
input wren;
// Read enable signals for two read ports; active-high
input rd1en, rd2en;
/**
* Addresses for write and read operations
*
* wraddr must have valid output data at positive edge of the
* clock when wren is set to logic HIGH
*
* rd?addr should contain valid value when rd?en = HIGH
*/
input [4:0] wraddr, rd1addr, rd2addr;
/**
* Byte-write enable signals: one for each byte of the data
*
* Asserted high when each byte of the address word needs to be
* updated during the write operation
*/
input [15:0] wrbyteen;
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg [127:0] rd1data,rd2data; // Output signals
/**
* (32 word) depth and (128 bits per word) width
*/
reg [127:0] reg_file [31:0]; // Store the data here
reg [127:0] ones; // 128-bit ones
reg [127:0] result; // ones & operand
reg [7:0] operand; // Write data to operate with
// ===============================================================
always @(posedge clk)
begin
ones=128'd0;
ones=ones-1'd1;
if(wren)
begin
if(wrbyteen==16'h1)
begin
operand=wrdata[0:7];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h3)
begin
operand=wrdata[8:15];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h7)
begin
operand=wrdata[16:23];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'hf)
begin
operand=wrdata[24:31];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h1f)
begin
operand=wrdata[32:39];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h3f)
begin
operand=wrdata[40:47];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h7f)
begin
operand=wrdata[48:55];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'hff)
begin
operand=wrdata[56:63];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h1ff)
begin
operand=wrdata[64:71];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h3ff)
begin
operand=wrdata[72:79];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h7ff)
begin
operand=wrdata[80:87];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'hfff)
begin
operand=wrdata[88:95];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h1fff)
begin
operand=wrdata[96:103];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h3fff)
begin
operand=wrdata[104:111];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h7fff)
begin
operand=wrdata[112:119];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'hffff)
begin
operand=wrdata[120:127];
result = ones & operand;
reg_file[wraddr] <= result;
end
end
//if(rd1en && !((rd1addr==5'bxxxxx) || (rd1addr==5'bzzzzz)))
/**
* Assume that no hardware errors will occur such that
* the values of the buses or signals will never be at the
* value X or Z.
*
* This can be ensured if the logic block is reset before
* usage.
*/
if(rd1en)
begin
rd1data<=reg_file[rd1addr];
end
else
begin
rd1data<=128'b0;
end
//if(rd2en && (rd2addr!=5'bx) && (rd2addr!=5'bz))
/**
* Assume that no hardware errors will occur such that
* the values of the buses or signals will never be at the
* value X or Z.
*
* This can be ensured if the logic block is reset before
* usage.
*/
if(rd2en)
begin
rd2data<=reg_file[rd2addr];
end
else
begin
rd2data<=128'b0;
end
end
endmodule
|
`timescale 1ns/1ps
module search_engine(
clk,
reset,
key_in_valid,
key_in,
bv_out_valid,
bv_out,
localbus_cs_n,
localbus_rd_wr,
localbus_data,
localbus_ale,
localbus_ack_n,
localbus_data_out
);
input clk;
input reset;
input key_in_valid;
input [71:0] key_in;
output wire bv_out_valid;
output wire [35:0] bv_out;
input localbus_cs_n;
input localbus_rd_wr;
input [31:0] localbus_data;
input localbus_ale;
output reg localbus_ack_n;
output reg [31:0] localbus_data_out;
reg set_valid[0:7];
reg read_valid[0:7];
reg [8:0] addr;
wire data_out_valid[0:7];
wire [35:0] data_out[0:7];
wire stage_enable[0:1];
wire bv_valid_temp[0:7];
wire [35:0] bv_temp[0:7];
//---state----//
reg [3:0] set_state;
parameter idle = 4'd0,
ram_set = 4'd1,
ram_read = 4'd2,
wait_read = 4'd3,
wait_back = 4'd4;
//--------------reg--------------//
//--set--//
reg [31:0] localbus_addr;
reg [35:0] set_data_temp;
wire[35:0] data_out_temp;
wire data_out_valid_temp;
reg [35:0] data_out_temp_reg;
assign data_out_valid_temp = (data_out_valid[0] == 1'b1)? 1'b1:
(data_out_valid[1] == 1'b1)? 1'b1:
(data_out_valid[2] == 1'b1)? 1'b1:
(data_out_valid[3] == 1'b1)? 1'b1:
(data_out_valid[4] == 1'b1)? 1'b1:
(data_out_valid[5] == 1'b1)? 1'b1:
(data_out_valid[6] == 1'b1)? 1'b1:
(data_out_valid[7] == 1'b1)? 1'b1:
1'b0;
assign data_out_temp = (data_out_valid[0] == 1'b1)? data_out[0]:
(data_out_valid[1] == 1'b1)? data_out[1]:
(data_out_valid[2] == 1'b1)? data_out[2]:
(data_out_valid[3] == 1'b1)? data_out[3]:
(data_out_valid[4] == 1'b1)? data_out[4]:
(data_out_valid[5] == 1'b1)? data_out[5]:
(data_out_valid[6] == 1'b1)? data_out[6]:
(data_out_valid[7] == 1'b1)? data_out[7]:
36'b0;
//-----------------------set_state---------------//
always @ (posedge clk or negedge reset)
begin
if(!reset)
begin
set_state <= idle;
set_valid[0] <= 1'b0;set_valid[1] <= 1'b0;set_valid[2] <= 1'b0;
set_valid[3] <= 1'b0;set_valid[4] <= 1'b0;set_valid[5] <= 1'b0;
set_valid[6] <= 1'b0;set_valid[7] <= 1'b0;
read_valid[0]<= 1'b0;read_valid[1]<= 1'b0;read_valid[2]<= 1'b0;
read_valid[3]<= 1'b0;read_valid[4]<= 1'b0;read_valid[5]<= 1'b0;
read_valid[6]<= 1'b0;read_valid[7]<= 1'b0;
set_data_temp <= 36'b0;
localbus_ack_n <= 1'b1;
localbus_data_out <= 32'b0;
end
else
begin
case(set_state)
idle:
begin
if(localbus_ale == 1'b1)
begin
localbus_addr <= localbus_data;
if(localbus_rd_wr == 1'b0)
begin
set_state <= ram_set;
end
else
begin
set_state <= ram_read;
end
end
end
ram_set:
begin
if(localbus_cs_n == 1'b0)
begin
case(localbus_addr[0])
1'd0: set_data_temp[35:32] <= localbus_data[3:0];
1'd1:
begin
set_data_temp[31:0] <= localbus_data;
addr <= localbus_addr[11:3];
case(localbus_addr[14:12])
3'd0: set_valid[0] <= 1'b1;
3'd1: set_valid[1] <= 1'b1;
3'd2: set_valid[2] <= 1'b1;
3'd3: set_valid[3] <= 1'b1;
3'd4: set_valid[4] <= 1'b1;
3'd5: set_valid[5] <= 1'b1;
3'd6: set_valid[6] <= 1'b1;
3'd7: set_valid[7] <= 1'b1;
endcase
end
endcase
set_state <= wait_back;
localbus_ack_n <= 1'b0;
end
end
ram_read:
begin
if(localbus_cs_n == 1'b0)
begin
case(localbus_addr[0])
1'b0:
begin
addr <= localbus_addr[11:3];
case(localbus_addr[14:12])
3'd0: read_valid[0] <= 1'b1;
3'd1: read_valid[1] <= 1'b1;
3'd2: read_valid[2] <= 1'b1;
3'd3: read_valid[3] <= 1'b1;
3'd4: read_valid[4] <= 1'b1;
3'd5: read_valid[5] <= 1'b1;
3'd6: read_valid[6] <= 1'b1;
3'd7: read_valid[7] <= 1'b1;
endcase
end
1'b1: localbus_data_out <= data_out_temp_reg[31:0];
endcase
if(localbus_addr[0] == 1'b0)
begin
set_state <= wait_read;
end
else
begin
set_state <= wait_back;
localbus_ack_n <= 1'b0;
end
end
end
wait_read:
begin
read_valid[0]<= 1'b0;read_valid[1]<= 1'b0;read_valid[2]<= 1'b0;
read_valid[3]<= 1'b0;read_valid[4]<= 1'b0;read_valid[5]<= 1'b0;
read_valid[6]<= 1'b0;read_valid[7]<= 1'b0;
if(data_out_valid_temp == 1'b1)begin
localbus_data_out <={28'b0,data_out_temp[35:32]};
data_out_temp_reg <= data_out_temp;
localbus_ack_n <= 1'b0;
set_state <= wait_back;
end
end
wait_back:
begin
set_valid[0] <= 1'b0;set_valid[1] <= 1'b0;set_valid[2] <= 1'b0;
set_valid[3] <= 1'b0;set_valid[4] <= 1'b0;set_valid[5] <= 1'b0;
set_valid[6] <= 1'b0;set_valid[7] <= 1'b0;
if(localbus_cs_n == 1'b1)
begin
localbus_ack_n <= 1'b1;
set_state <= idle;
end
end
default:
begin
set_state <= idle;
end
endcase
end
end
generate
genvar i;
for(i=0; i<8; i= i+1) begin : lookup_bit
lookup_bit lb(
.clk(clk),
.reset(reset),
.set_valid(set_valid[i]),
.set_data(set_data_temp[35:0]),
.read_valid(read_valid[i]),
.addr(addr),
.data_out_valid(data_out_valid[i]),
.data_out(data_out[i]),
.key_valid(key_in_valid),
.key(key_in[((i+1)*9-1):i*9]),
.bv_valid(bv_valid_temp[i]),
.bv(bv_temp[i])
);
end
endgenerate
bv_and_8 bv_and_8(
.clk(clk),
.reset(reset),
.bv_in_valid(bv_valid_temp[0]),
.bv_1(bv_temp[0]),
.bv_2(bv_temp[1]),
.bv_3(bv_temp[2]),
.bv_4(bv_temp[3]),
.bv_5(bv_temp[4]),
.bv_6(bv_temp[5]),
.bv_7(bv_temp[6]),
.bv_8(bv_temp[7]),
.bv_out_valid(bv_out_valid),
.bv_out(bv_out)
);
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sat Dec 24 01:08:44 2016
// Host : KLight-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// d:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/bg_tex/bg_tex_sim_netlist.v
// Design : bg_tex
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "bg_tex,blk_mem_gen_v8_3_5,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
(* NotValidForBitStream *)
module bg_tex
(clka,
wea,
addra,
dina,
douta);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [13:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [11:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [11:0]douta;
wire [13:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_rsta_busy_UNCONNECTED;
wire NLW_U0_rstb_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [11:0]NLW_U0_doutb_UNCONNECTED;
wire [13:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [13:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [11:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "14" *)
(* C_ADDRB_WIDTH = "14" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "4" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 6.22775 mW" *)
(* C_FAMILY = "artix7" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "bg_tex.mem" *)
(* C_INIT_FILE_NAME = "bg_tex.mif" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "11130" *)
(* C_READ_DEPTH_B = "11130" *)
(* C_READ_WIDTH_A = "12" *)
(* C_READ_WIDTH_B = "12" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "11130" *)
(* C_WRITE_DEPTH_B = "11130" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "12" *)
(* C_WRITE_WIDTH_B = "12" *)
(* C_XDEVICEFAMILY = "artix7" *)
(* downgradeipidentifiedwarnings = "yes" *)
bg_tex_blk_mem_gen_v8_3_5 U0
(.addra(addra),
.addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.clka(clka),
.clkb(1'b0),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(douta),
.doutb(NLW_U0_doutb_UNCONNECTED[11:0]),
.eccpipece(1'b0),
.ena(1'b0),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[13:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
.rstb(1'b0),
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[13:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[11:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "bindec" *)
module bg_tex_bindec
(ena_array,
addra);
output [0:0]ena_array;
input [1:0]addra;
wire [1:0]addra;
wire [0:0]ena_array;
LUT2 #(
.INIT(4'h1))
\/i_
(.I0(addra[1]),
.I1(addra[0]),
.O(ena_array));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module bg_tex_blk_mem_gen_generic_cstr
(douta,
addra,
clka,
dina,
wea);
output [11:0]douta;
input [13:0]addra;
input clka;
input [11:0]dina;
input [0:0]wea;
wire [13:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]ena_array;
wire \ramloop[2].ram.r_n_0 ;
wire \ramloop[2].ram.r_n_1 ;
wire \ramloop[2].ram.r_n_2 ;
wire \ramloop[2].ram.r_n_3 ;
wire \ramloop[2].ram.r_n_4 ;
wire \ramloop[2].ram.r_n_5 ;
wire \ramloop[2].ram.r_n_6 ;
wire \ramloop[2].ram.r_n_7 ;
wire \ramloop[2].ram.r_n_8 ;
wire \ramloop[3].ram.r_n_0 ;
wire \ramloop[3].ram.r_n_1 ;
wire \ramloop[3].ram.r_n_2 ;
wire \ramloop[3].ram.r_n_3 ;
wire \ramloop[3].ram.r_n_4 ;
wire \ramloop[3].ram.r_n_5 ;
wire \ramloop[3].ram.r_n_6 ;
wire \ramloop[3].ram.r_n_7 ;
wire \ramloop[3].ram.r_n_8 ;
wire \ramloop[4].ram.r_n_0 ;
wire \ramloop[4].ram.r_n_1 ;
wire \ramloop[4].ram.r_n_2 ;
wire \ramloop[4].ram.r_n_3 ;
wire \ramloop[4].ram.r_n_4 ;
wire \ramloop[4].ram.r_n_5 ;
wire \ramloop[4].ram.r_n_6 ;
wire \ramloop[4].ram.r_n_7 ;
wire \ramloop[4].ram.r_n_8 ;
wire [0:0]wea;
bg_tex_bindec \bindec_a.bindec_inst_a
(.addra(addra[13:12]),
.ena_array(ena_array));
bg_tex_blk_mem_gen_mux \has_mux_a.A
(.\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ({\ramloop[4].ram.r_n_0 ,\ramloop[4].ram.r_n_1 ,\ramloop[4].ram.r_n_2 ,\ramloop[4].ram.r_n_3 ,\ramloop[4].ram.r_n_4 ,\ramloop[4].ram.r_n_5 ,\ramloop[4].ram.r_n_6 ,\ramloop[4].ram.r_n_7 }),
.\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 ({\ramloop[2].ram.r_n_0 ,\ramloop[2].ram.r_n_1 ,\ramloop[2].ram.r_n_2 ,\ramloop[2].ram.r_n_3 ,\ramloop[2].ram.r_n_4 ,\ramloop[2].ram.r_n_5 ,\ramloop[2].ram.r_n_6 ,\ramloop[2].ram.r_n_7 }),
.\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1 (\ramloop[4].ram.r_n_8 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2 (\ramloop[2].ram.r_n_8 ),
.DOADO({\ramloop[3].ram.r_n_0 ,\ramloop[3].ram.r_n_1 ,\ramloop[3].ram.r_n_2 ,\ramloop[3].ram.r_n_3 ,\ramloop[3].ram.r_n_4 ,\ramloop[3].ram.r_n_5 ,\ramloop[3].ram.r_n_6 ,\ramloop[3].ram.r_n_7 }),
.DOPADOP(\ramloop[3].ram.r_n_8 ),
.addra(addra[13:12]),
.clka(clka),
.douta(douta[11:3]));
bg_tex_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.clka(clka),
.dina(dina[0]),
.douta(douta[0]),
.wea(wea));
bg_tex_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.addra(addra),
.clka(clka),
.dina(dina[2:1]),
.douta(douta[2:1]),
.wea(wea));
bg_tex_blk_mem_gen_prim_width__parameterized1 \ramloop[2].ram.r
(.addra(addra[11:0]),
.clka(clka),
.dina(dina[11:3]),
.\douta[10] ({\ramloop[2].ram.r_n_0 ,\ramloop[2].ram.r_n_1 ,\ramloop[2].ram.r_n_2 ,\ramloop[2].ram.r_n_3 ,\ramloop[2].ram.r_n_4 ,\ramloop[2].ram.r_n_5 ,\ramloop[2].ram.r_n_6 ,\ramloop[2].ram.r_n_7 }),
.\douta[11] (\ramloop[2].ram.r_n_8 ),
.ena_array(ena_array),
.wea(wea));
bg_tex_blk_mem_gen_prim_width__parameterized2 \ramloop[3].ram.r
(.DOADO({\ramloop[3].ram.r_n_0 ,\ramloop[3].ram.r_n_1 ,\ramloop[3].ram.r_n_2 ,\ramloop[3].ram.r_n_3 ,\ramloop[3].ram.r_n_4 ,\ramloop[3].ram.r_n_5 ,\ramloop[3].ram.r_n_6 ,\ramloop[3].ram.r_n_7 }),
.DOPADOP(\ramloop[3].ram.r_n_8 ),
.addra(addra),
.clka(clka),
.dina(dina[11:3]),
.wea(wea));
bg_tex_blk_mem_gen_prim_width__parameterized3 \ramloop[4].ram.r
(.addra(addra),
.clka(clka),
.dina(dina[11:3]),
.\douta[10] ({\ramloop[4].ram.r_n_0 ,\ramloop[4].ram.r_n_1 ,\ramloop[4].ram.r_n_2 ,\ramloop[4].ram.r_n_3 ,\ramloop[4].ram.r_n_4 ,\ramloop[4].ram.r_n_5 ,\ramloop[4].ram.r_n_6 ,\ramloop[4].ram.r_n_7 }),
.\douta[11] (\ramloop[4].ram.r_n_8 ),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_mux" *)
module bg_tex_blk_mem_gen_mux
(douta,
addra,
clka,
DOADO,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 ,
DOPADOP,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1 ,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2 );
output [8:0]douta;
input [1:0]addra;
input clka;
input [7:0]DOADO;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 ;
input [0:0]DOPADOP;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2 ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2 ;
wire [7:0]DOADO;
wire [0:0]DOPADOP;
wire [1:0]addra;
wire clka;
wire [8:0]douta;
wire [1:0]sel_pipe;
wire [1:0]sel_pipe_d1;
LUT5 #(
.INIT(32'h0A0ACFC0))
\douta[10]_INST_0
(.I0(DOADO[7]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram [7]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 [7]),
.I4(sel_pipe_d1[0]),
.O(douta[7]));
LUT5 #(
.INIT(32'h0A0ACFC0))
\douta[11]_INST_0
(.I0(DOPADOP),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1 ),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2 ),
.I4(sel_pipe_d1[0]),
.O(douta[8]));
LUT5 #(
.INIT(32'h0A0ACFC0))
\douta[3]_INST_0
(.I0(DOADO[0]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram [0]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 [0]),
.I4(sel_pipe_d1[0]),
.O(douta[0]));
LUT5 #(
.INIT(32'h0A0ACFC0))
\douta[4]_INST_0
(.I0(DOADO[1]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram [1]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 [1]),
.I4(sel_pipe_d1[0]),
.O(douta[1]));
LUT5 #(
.INIT(32'h0A0ACFC0))
\douta[5]_INST_0
(.I0(DOADO[2]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram [2]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 [2]),
.I4(sel_pipe_d1[0]),
.O(douta[2]));
LUT5 #(
.INIT(32'h0A0ACFC0))
\douta[6]_INST_0
(.I0(DOADO[3]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram [3]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 [3]),
.I4(sel_pipe_d1[0]),
.O(douta[3]));
LUT5 #(
.INIT(32'h0A0ACFC0))
\douta[7]_INST_0
(.I0(DOADO[4]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram [4]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 [4]),
.I4(sel_pipe_d1[0]),
.O(douta[4]));
LUT5 #(
.INIT(32'h0A0ACFC0))
\douta[8]_INST_0
(.I0(DOADO[5]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram [5]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 [5]),
.I4(sel_pipe_d1[0]),
.O(douta[5]));
LUT5 #(
.INIT(32'h0A0ACFC0))
\douta[9]_INST_0
(.I0(DOADO[6]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram [6]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 [6]),
.I4(sel_pipe_d1[0]),
.O(douta[6]));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]
(.C(clka),
.CE(1'b1),
.D(sel_pipe[0]),
.Q(sel_pipe_d1[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]
(.C(clka),
.CE(1'b1),
.D(sel_pipe[1]),
.Q(sel_pipe_d1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]
(.C(clka),
.CE(1'b1),
.D(addra[0]),
.Q(sel_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]
(.C(clka),
.CE(1'b1),
.D(addra[1]),
.Q(sel_pipe[1]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module bg_tex_blk_mem_gen_prim_width
(douta,
clka,
addra,
dina,
wea);
output [0:0]douta;
input clka;
input [13:0]addra;
input [0:0]dina;
input [0:0]wea;
wire [13:0]addra;
wire clka;
wire [0:0]dina;
wire [0:0]douta;
wire [0:0]wea;
bg_tex_blk_mem_gen_prim_wrapper_init \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module bg_tex_blk_mem_gen_prim_width__parameterized0
(douta,
clka,
addra,
dina,
wea);
output [1:0]douta;
input clka;
input [13:0]addra;
input [1:0]dina;
input [0:0]wea;
wire [13:0]addra;
wire clka;
wire [1:0]dina;
wire [1:0]douta;
wire [0:0]wea;
bg_tex_blk_mem_gen_prim_wrapper_init__parameterized0 \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module bg_tex_blk_mem_gen_prim_width__parameterized1
(\douta[10] ,
\douta[11] ,
clka,
ena_array,
addra,
dina,
wea);
output [7:0]\douta[10] ;
output [0:0]\douta[11] ;
input clka;
input [0:0]ena_array;
input [11:0]addra;
input [8:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [8:0]dina;
wire [7:0]\douta[10] ;
wire [0:0]\douta[11] ;
wire [0:0]ena_array;
wire [0:0]wea;
bg_tex_blk_mem_gen_prim_wrapper_init__parameterized1 \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.\douta[10] (\douta[10] ),
.\douta[11] (\douta[11] ),
.ena_array(ena_array),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module bg_tex_blk_mem_gen_prim_width__parameterized2
(DOADO,
DOPADOP,
clka,
addra,
dina,
wea);
output [7:0]DOADO;
output [0:0]DOPADOP;
input clka;
input [13:0]addra;
input [8:0]dina;
input [0:0]wea;
wire [7:0]DOADO;
wire [0:0]DOPADOP;
wire [13:0]addra;
wire clka;
wire [8:0]dina;
wire [0:0]wea;
bg_tex_blk_mem_gen_prim_wrapper_init__parameterized2 \prim_init.ram
(.DOADO(DOADO),
.DOPADOP(DOPADOP),
.addra(addra),
.clka(clka),
.dina(dina),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module bg_tex_blk_mem_gen_prim_width__parameterized3
(\douta[10] ,
\douta[11] ,
clka,
addra,
dina,
wea);
output [7:0]\douta[10] ;
output [0:0]\douta[11] ;
input clka;
input [13:0]addra;
input [8:0]dina;
input [0:0]wea;
wire [13:0]addra;
wire clka;
wire [8:0]dina;
wire [7:0]\douta[10] ;
wire [0:0]\douta[11] ;
wire [0:0]wea;
bg_tex_blk_mem_gen_prim_wrapper_init__parameterized3 \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.\douta[10] (\douta[10] ),
.\douta[11] (\douta[11] ),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module bg_tex_blk_mem_gen_prim_wrapper_init
(douta,
clka,
addra,
dina,
wea);
output [0:0]douta;
input clka;
input [13:0]addra;
input [0:0]dina;
input [0:0]wea;
wire [13:0]addra;
wire clka;
wire [0:0]dina;
wire [0:0]douta;
wire [0:0]wea;
wire [15:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ;
wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(1),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0200000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h1000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h000000000E000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h00000000000000000000300000000000000000000000001C0000000000000000),
.INIT_0E(256'h0C00000000000000000000000000000400000000000000000000000000000000),
.INIT_0F(256'h0000000000007000000000000000000000000038000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000040000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h8000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000028000000000000000000000008000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000004000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000040000),
.INIT_19(256'h0800000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0080200000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000040000000000020000000000000000000000000000000000000),
.INIT_1C(256'h00000000000080000000000000008004000000000000000000000A0000000000),
.INIT_1D(256'h0000000000000200000000000000000000000000000000001000000000000001),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000002000),
.INIT_1F(256'h0000000008000000010000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000004000040000000000000000000000000000000000000),
.INIT_21(256'h000000A000000000001000000000000000000000000000000000000000080000),
.INIT_22(256'h0000000000000000000000000000000000000000000000020000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000040000),
.INIT_24(256'h0000000000000000000400020000000000000000000000000000000000000000),
.INIT_25(256'h0000000001400000000000000000000000010000000000000000000004000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0080000000000000000000000000000000000000000000000000800000000000),
.INIT_28(256'h0000000000000800000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram
(.ADDRARDADDR(addra),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:1],douta}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:0]),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module bg_tex_blk_mem_gen_prim_wrapper_init__parameterized0
(douta,
clka,
addra,
dina,
wea);
output [1:0]douta;
input clka;
input [13:0]addra;
input [1:0]dina;
input [0:0]wea;
wire [13:0]addra;
wire clka;
wire [1:0]dina;
wire [1:0]douta;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h000000000000000C000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000C00000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000030000000000000000000000000000),
.INIT_0E(256'h0000000000000000000003000000000000000000000000300000000000000000),
.INIT_0F(256'h0000000300000000000000000000000000004000000000000000000000000000),
.INIT_10(256'h00000C0000000000000003000000000000000000000000C0000000000033C000),
.INIT_11(256'h0000000C0000000000000000000000C304000000000000000000000000300000),
.INIT_12(256'h000000000000000000000000000000000000000000C000000000000000000000),
.INIT_13(256'h000400000000000000000000000000000000000000000000000000C000000000),
.INIT_14(256'h00000000000003000000000000000000000000000000D0000000000000000000),
.INIT_15(256'h0E40000000000000000000000300000000000000000000000000000C40000000),
.INIT_16(256'h000000000003000C000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000003000C00000000000000000000000003000000000000000),
.INIT_18(256'h00000000C00000000000000000000000C00C0000000000000000000000000000),
.INIT_19(256'h000000000000000000CC00000000000000000000000003000000000000000000),
.INIT_1A(256'h0000030000000000000000000003016300000000000000000000000000000000),
.INIT_1B(256'h000000000000000003000000000000000000000C074C00000000000000000000),
.INIT_1C(256'h00C0000000000000000000000000000000000000000000000030003000000000),
.INIT_1D(256'h0160000000C00300000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000EC0000003C0F000000000000000000000000030000000000000),
.INIT_1F(256'h000000000000F0C00C0000002700000000FC3C00000000000000000000000030),
.INIT_20(256'h0000000000000000000000300000000000000030000000030000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000C00000000000000C00000000),
.INIT_22(256'h0000000000003000000000000000000000000000000000300000000000000000),
.INIT_23(256'h00000000003000003000000000C0000000000000000000000000000000000300),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h8000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h000000000300000000000000000000000000000000000C003000300000000030),
.INIT_27(256'h0000000000044003000000030000000000000000000000000003000030000000),
.INIT_28(256'h0000000000000000C0100000000030000000C000000000000000000000000000),
.INIT_29(256'h0000000000000000000003000000000000000000000000000000000000000000),
.INIT_2A(256'h00000000000000000000000000000000000800000000000000000000000C0000),
.INIT_2B(256'h0000000000000000000000000000000000000000000002000000040000000000),
.INIT_2C(256'h0000008000000000400000000000030000000000000000000000000000000003),
.INIT_2D(256'h0000000000000000001000000000300000000000000000000000000000000000),
.INIT_2E(256'h0C00000000000000000000000000000000C0000C000000000000000000000000),
.INIT_2F(256'h00000000000030000000000000000000000000000000000C0000000000000000),
.INIT_30(256'h0000000000000000000000003000000000000000000000000000001000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h00C0000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000300000000000003000000000000000000000000000000000000000000000),
.INIT_35(256'h0000400008000000000000000000000000000000000000000000000000000300),
.INIT_36(256'h0000000000000000000000000000000000000000300000000000000000000000),
.INIT_37(256'h0000000000000000000000000000100030000030000000000000CB0000000000),
.INIT_38(256'h0000000000003000000000000000000000000000004800000000000000000000),
.INIT_39(256'h0000C00000000000000000008000000000000000000000000000000080000023),
.INIT_3A(256'h0000000000000300000000C00000000002300000000000000000000000000001),
.INIT_3B(256'h00000000000000000000000000000000000000000C000000C000000000000000),
.INIT_3C(256'h03003000C00000000000000000000000000030C00000000C0000000008000000),
.INIT_3D(256'h08000C00000300CC00000000000000000000000000000000C000300000080003),
.INIT_3E(256'h00000000000300C00030000000C0000010000000000000000000000000000000),
.INIT_3F(256'h0000000000000000004300030000300000020030000000000000000000000000),
.INIT_40(256'h0008000000000000000000000000000000000030000000000000000000000000),
.INIT_41(256'h0000000000000C00000000000000000000000000000000000000200000000000),
.INIT_42(256'h3000000030000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000008830000000000000000000000E00000000000000000000000000),
.INIT_44(256'h0000000000000000000000000300000EF0000000000000000000000000000000),
.INIT_45(256'h000000000000000000000000000000000000000003003C000000000000C00000),
.INIT_46(256'hC000000000000000300400000000000000000000000000030000002000000000),
.INIT_47(256'h0000000000000000003000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000002003000000000000000000000000000000000000),
.INIT_49(256'h00000000000000000000000000000000000000C3000000080001000000000000),
.INIT_4A(256'h0000040200000000000000000000000000000000000000000020000000030300),
.INIT_4B(256'h0000003000000000000120000000000000000000000000000000000000020001),
.INIT_4C(256'h000000000000000C000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000003000000000000000000000000000000000000),
.INIT_4E(256'h000000000000000000000000000000000000000C100004000000000000000000),
.INIT_4F(256'h0000400000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000040000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000010000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000010000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module bg_tex_blk_mem_gen_prim_wrapper_init__parameterized1
(\douta[10] ,
\douta[11] ,
clka,
ena_array,
addra,
dina,
wea);
output [7:0]\douta[10] ;
output [0:0]\douta[11] ;
input clka;
input [0:0]ena_array;
input [11:0]addra;
input [8:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [8:0]dina;
wire [7:0]\douta[10] ;
wire [0:0]\douta[11] ;
wire [0:0]ena_array;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h00000000000000000000000C0000000000000000000000000200000000000000),
.INITP_05(256'h00000007E0000000000000000000000000F00000000000000000000000003800),
.INITP_06(256'h0000F0000000000001FF8000000000700000000000003FC00000000020000000),
.INITP_07(256'hFFFBF80000000003F8000001FFFFFFFE0000000001F00000000FFF07FF000000),
.INITP_08(256'h1FFE0000FFFFFFF9C0000000000FFE00003FFFFFF3F00000000007F8000007FF),
.INITP_09(256'hF800000000007FFF801FFFFFFFF800000000003FFF0007FFFFFFF90000000000),
.INITP_0A(256'hF0FFFFFFFFFFF00000000001FFFE03FFFFFFFFF80000000000FFFF807FFFFFFF),
.INITP_0B(256'h0000000007F87FFFFFFFFFFFE00000000007FF0FFFFFFFFFFFF00000000003FF),
.INITP_0C(256'hFFFFFFFFC40000000000021FFFFFFFFFFFF1800000000007C3FFFFFFFFFFFFC0),
.INITP_0D(256'h000000001FFFFFFFFFFE020000000000001FFFFFFFFFFF190000000000001FFF),
.INITP_0E(256'h81FFF8300000000000003FFFFFE1FFF8080000000000001FFFFFFFFFFC040000),
.INITP_0F(256'h000007FFBFFC23FFFFE00000000000074047FE11FFF8E00000000000040FC0FF),
.INIT_00(256'h1616161616161616161616161616161616161616161616161616161616161616),
.INIT_01(256'h1616161616161616161616161616161616161616161616161616161616161616),
.INIT_02(256'h1616161616161616161616161616161616161616161616161616161616161616),
.INIT_03(256'h1616161616161616161616161616161616161616161616161616161616161616),
.INIT_04(256'h1616161616161616161616161616161616161616161616161616161616161616),
.INIT_05(256'h1616161616161616161616161616161616161616161616161616161616161616),
.INIT_06(256'h1A161A161A161A161A161A161616161616161616161616161616161616161616),
.INIT_07(256'h1A161A161A161A161A161A161A161A161A161A161A161A161A161A161A161A16),
.INIT_08(256'h1A161A161A161A161A161A161A161A161A161A161A161A161A161A161A161A16),
.INIT_09(256'h1616161616161A161A161A161A161A161A161A161A161A161A161A161A161A16),
.INIT_0A(256'h1616161616161616161616161616161616161616161616161616161616161616),
.INIT_0B(256'h1616161616161616161616161616161616161616161616161616161616161616),
.INIT_0C(256'h1616161616161616161616161616161616161616161616161616161616161616),
.INIT_0D(256'h161616161616161616161616161616161616161616161616161A161616161616),
.INIT_0E(256'h1616161616161616161616161616161616161616161616161616161616161616),
.INIT_0F(256'h1616161616161616161616161616161616161616161616161616161616161616),
.INIT_10(256'h1A161A161A161A161A161A161A161A1616161616161616161616161616161616),
.INIT_11(256'h1A161A161A161A161A161A161A161A161A161A161A0020161A161A161A161A16),
.INIT_12(256'h1A161A161A161A161A161A161A161A161A161A161A161A161A161A161A161A16),
.INIT_13(256'h1616161616161616161616161A161A161A161A161A161A161A161A161A161A16),
.INIT_14(256'h1616161616161616161616060000161616161616161616161616161616161616),
.INIT_15(256'h1616161616161616161616161616161616161616161616161616161616161616),
.INIT_16(256'h1616161616161616161616161616161616161616161616161616161616161616),
.INIT_17(256'h16160000201616161616161616161616161616161616161616161616161A1616),
.INIT_18(256'h1616161616161616161616161616161616161616161616161616161616161616),
.INIT_19(256'h1616161616161616161616161616161616161616161616161616161616161616),
.INIT_1A(256'h1A161A161A161A161A161A161A161A161A161A1616161616161A161616161616),
.INIT_1B(256'h1A161A161A161A161A161A161A161A161A161A161A161A160000000016161A16),
.INIT_1C(256'h1A161A161A161A161A161A161A161A161A161A161A161A161A161A161A161A16),
.INIT_1D(256'h1616161616161616161616161A161616161616161A161A161A161A161A161A16),
.INIT_1E(256'h161616161616161616161616161600000000001A161616161616161616161616),
.INIT_1F(256'h1616161616161616161616161616161616161616161616161616161616161616),
.INIT_20(256'h1616161616161616161A16161616161616161616161616161616161616161616),
.INIT_21(256'h1616161600007600000016161616161616161616161616161616161616161616),
.INIT_22(256'h1616161616161616161616161616161616161616161616161616161616161616),
.INIT_23(256'h1616161616161616161616161616161616161616161616161616161616161616),
.INIT_24(256'h0016161A161A161A161A161A161A161A161A161A161A161A161616161616161A),
.INIT_25(256'h161A161A161A161A161A161A161A161A161A161A161A161A161A000076760000),
.INIT_26(256'h161A161A161A161A161A161A161A161A161A161A161A161A161A161A161A161A),
.INIT_27(256'h16161616161616161616161616161616161A161A16161616161A161A161A161A),
.INIT_28(256'h1616161616161616161616161616160000007676760000001616161616161616),
.INIT_29(256'h1616161616161616161616161616161616161616161616161616161616161616),
.INIT_2A(256'h1616161616161A161616161A1616161616161616161616161616161616161616),
.INIT_2B(256'h16161616000000EE7676BA76000020161A161616161616161616161616161616),
.INIT_2C(256'h1616161616161616161616161616161616161616161616161616161616161616),
.INIT_2D(256'h161616161A161A16161600001616161616161616161616161616161616161616),
.INIT_2E(256'h7676760000001616161A161A161A161A161A161A161A161A161A161616161616),
.INIT_2F(256'h161A161A161A161A161A161A161A161A161A161A161A161A161A0000EE767676),
.INIT_30(256'h16007600001A161A161A161A161A161A161A161A161A161A161A161A161A161A),
.INIT_31(256'h1616161616161616161616161616161616161A16161A1616161616161616161A),
.INIT_32(256'h1616161616161616161616161616161600007676BA76BA767676000016161616),
.INIT_33(256'h1616161616161616161616161616161616161616161616161616161616161616),
.INIT_34(256'h1616161616161616161616161616161616161616161616160076767600161616),
.INIT_35(256'h001616161600007676767676767676BA76000016161A16161616161616161616),
.INIT_36(256'h1616161616161616161616161616161616161616160000000000000000000000),
.INIT_37(256'h161A16161A161616161A161A1616160076BA7676001616161616161616161616),
.INIT_38(256'h76BA76767676767600001A1616161A161A161A161A161A161A161A161A161A16),
.INIT_39(256'h161A161A161A161A000000007676767676767676767676760000000000767676),
.INIT_3A(256'h16161616161A0076763276760002161A161A161A161A161A161A161A161A161A),
.INIT_3B(256'h1616161616161616161616161616161616161616161616161616161616161616),
.INIT_3C(256'h767676BA7676BA7676BA7676BA76767676767676BA76BA767676BA7676767600),
.INIT_3D(256'hBA76767676000016461A16161616161616161616161616161616161616160076),
.INIT_3E(256'h161616161616161616161616161A16161A16161616161A161616161A16007676),
.INIT_3F(256'h7676767676BA76BA76BA767676EE7676327676BA76EE0016161A161616161616),
.INIT_40(256'h1616161616161616161616161616161616161600007676767676767676767676),
.INIT_41(256'h1A161A16161616161A1616161616161A161616160076767676BA767676EE0202),
.INIT_42(256'h76767676AA003276767676760216161616161A161A161A161A161A161A161A16),
.INIT_43(256'h1A161A161A161A161A0076767676BA76BA7676BA7676BA7676BA767676767676),
.INIT_44(256'h161616161616161A1616160076BA7676767676BA7676760000161A161A161A16),
.INIT_45(256'hBA76461616161A1616161616161616161616161616161616161616161A161616),
.INIT_46(256'h767676BA7676767676767676767676767676BA76767676767676BA7676006676),
.INIT_47(256'h1A16007676767676BA7676763276760000161616161616161616161616160000),
.INIT_48(256'h1616161616161616161616161616161616161616161616161A16161A16161616),
.INIT_49(256'h7676BA7676BA7676767676BA76BA76BA767676767620AA766620161616161616),
.INIT_4A(256'h7676BA76BA76767600001616161616161616161600767676BA767676767676BA),
.INIT_4B(256'h161A161A161A161A16161A161A161616161616161616161616007676BA767676),
.INIT_4C(256'h767676767676767676BA76BA7622002016161A16161A161A161A161A161A161A),
.INIT_4D(256'hBA0000AA1A161A161A16007676BA76767676BA76BA767676767676767676BA76),
.INIT_4E(256'h161616161616161616161A16161A161600BA767676BA76767676767676BA7676),
.INIT_4F(256'h7676767632006606161616161616161616161616161616161616161616161616),
.INIT_50(256'h0076BA767676767676767676767676BA7676BA76767676BA7676767676767676),
.INIT_51(256'h161616161616160076767676767676BA7676767676767676764600AA16161600),
.INIT_52(256'h16161A16161616161616161616161616161616161616161A161616161A161616),
.INIT_53(256'h76767676BA7676767676767676767676BA76BA76BA76BA767676BA767600161A),
.INIT_54(256'h76BA7676BA76767676BA767676BA76EE64000000000076767676767676BA76BA),
.INIT_55(256'h161A161A161A161A161A161A16161616161A161616161616161A16161A160032),
.INIT_56(256'h76BA76BA76767676767676767676767676767676001616161616161A161A161A),
.INIT_57(256'h7676762A640000AA327676767676BA767676BA7676767676BA7676767676BA76),
.INIT_58(256'h161616161A1616161616161616161A16161616161600327676767676767676BA),
.INIT_59(256'h7676767676BA767676BA767600161A1616161616161616161616161616161616),
.INIT_5A(256'hBA7676BA767676BA767676767676767676BA76767676767676767676BA767676),
.INIT_5B(256'h161A1616161616161A1616160032BA7676BA7676BA767676A06600AA32BA7676),
.INIT_5C(256'h767632001616161A1616161616161616161616161616161616161616161A1616),
.INIT_5D(256'h76BA7676BA767676767676BA7676BA76767676767676BA76BA76BA767676BA76),
.INIT_5E(256'h16161A16007676767676767676600200EE767676767676767676767676767676),
.INIT_5F(256'h161A161A161A161A161A161A161A161A161A161616161A161616161616161616),
.INIT_60(256'hBA76767676767676BA7676BA76767676767676767676767676BA001616161616),
.INIT_61(256'h7632460022EE76BA7676BA7676BA7676BA767676BA7676767676767676BA7676),
.INIT_62(256'h16161616161616161616161616161616161616161A16161A16161600007676BA),
.INIT_63(256'h76767676767676767676BA32000000767600161A1616161A1616161616161616),
.INIT_64(256'h767676767676767676BA767676BA767676BA7676767676767676BA767676BA76),
.INIT_65(256'h1A161A1616161A16161616161616161616168E1600AA76460000007676BA7676),
.INIT_66(256'h76760000EE33EEEEEE0016161A16161616161616161616161616161616161616),
.INIT_67(256'h767676767676BA7676767676BA7676BA767676BA76767676BA7676BA76BA76BA),
.INIT_68(256'h161A16161A16161A161A16002000000000006676767676BA7676BA7676BA7676),
.INIT_69(256'h0016161616161616161A161A161A161A161A161A161A16161616161A16161616),
.INIT_6A(256'h76BA767676767676767676767676767676767676767676760000007777AA0076),
.INIT_6B(256'h16160000000000000000667676767676767676767676767676BA767676767676),
.INIT_6C(256'h1616161616161616161616161616161616161616161616161616161616161616),
.INIT_6D(256'h7676BA7676BA7676BA76767676767600000066EE460076001A16161A16161A16),
.INIT_6E(256'h00000076BA3276BA767676BA7676BA767676BA767676BA76767676BA767676BA),
.INIT_6F(256'h16161616161A161A1616161A16161616161A16161A1616161616000000000000),
.INIT_70(256'h76BA76BA76760000000000000076001616161616161616161616161616161616),
.INIT_71(256'hBA76767676767676767676BA7676767676767676BA7676767676767676767676),
.INIT_72(256'h1A1616161616161A16161616161A161A16161600000000000000007676767676),
.INIT_73(256'h00000000760016161A16161A16161A161A161A161A161A161A161A1616161616),
.INIT_74(256'h7676767676BA76BA767676000000007676BA767676BA767676767676BA000000),
.INIT_75(256'h161A1616161616161A1616000000000000007676BA7676767676BA7676BA7676),
.INIT_76(256'h1616161616161616161616161616161616161616161616161616161A16161616),
.INIT_77(256'h7600004666AA00767676BA767676767676767676760000000000767600161616),
.INIT_78(256'h161616000076AA00000000EE7676767676760000000000007676767676767676),
.INIT_79(256'h161616161616161616161A161A1616161A16161A161616161616161616161616),
.INIT_7A(256'h7676767676BA76BA76BA7676760000007676BAEE001A16161A16161A16161616),
.INIT_7B(256'hEE76000000000000007600EEEE767676BA76BA76767676000000EEBBEE000076),
.INIT_7C(256'h16161616161A161616161616161A161A16161A161A1616161A16161600767632),
.INIT_7D(256'h76767676767676767676760000161616161616161A161A161A161A161A161A16),
.INIT_7E(256'h76007676BA767676767676BA76BA000000AA77EE000076BA767676BA76767676),
.INIT_7F(256'h161616161616161616161616161A1616161A16160076BA767676767676767676),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],\douta[10] }),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],\douta[11] }),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module bg_tex_blk_mem_gen_prim_wrapper_init__parameterized2
(DOADO,
DOPADOP,
clka,
addra,
dina,
wea);
output [7:0]DOADO;
output [0:0]DOPADOP;
input clka;
input [13:0]addra;
input [8:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0 ;
wire [7:0]DOADO;
wire [0:0]DOPADOP;
wire [13:0]addra;
wire clka;
wire [8:0]dina;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'hE1F9E0000000000007FEFFF00FFFFC40000000000007FF7FF807FFFF00000000),
.INITP_01(256'h000FF7FFC1FF8FCFC0000000000007FBFFE07FC3E7E0000000000007FDFFE01F),
.INITP_02(256'h3E0000000000003FDFFFFFFFF99F0000000000001FEFFFFFFFFF9F8000000000),
.INITP_03(256'hF07C7C7F0F7F00000000000001FC7F1C7FE0BF38000000000000FF3FC07FFF07),
.INITP_04(256'h00000000001F81F3FDFFCDFF0000000000000FE0F9FEFFCEFFC0000000000007),
.INITP_05(256'hDFCFFFFFF00000000000002C01CFF7FFCFF80000000000001C01E7FBFF8BFE00),
.INITP_06(256'h000000007801C07FFFFFF00000000000003003CF1FFFFFD00000000000003801),
.INITP_07(256'hFFFFFFC0000000000000B81E7FFFFFFFE00000000000007C0CC3FFFFFFE00000),
.INITP_08(256'h00000FA1FFFFFFFFFF80000000000003D87FFFFFFFFFC0000000000001F81F3F),
.INITP_09(256'hFFFE0000000000007607FFFFFFFFFF0000000000003F83FFFFFFFFFF80000000),
.INITP_0A(256'h01603FFF7FFFEFFC000000000000F01FFFFFFFF7FE000000000000FC0FFFFFFF),
.INITP_0B(256'h60000000000003807FFEFFFFBFB0000000000003403FFEFFFFDFD80000000000),
.INITP_0C(256'hC0FFFDFFFDFB8000000000000782FFFDFFFEFEC0000000000007827FFDFFFF7E),
.INITP_0D(256'h00000000001F31FFFBFFEFEF8000000000000F90FFFBFFFBF780000000000002),
.INITP_0E(256'h1FF3FF1EFF8000000000001CFFFFE9FF3F7FC000000000001E7FFFF3FF9FBF80),
.INITP_0F(256'h0000000031FFCFCFFF07FE00000000000039FF9FE7FE2DFF00000000000018FE),
.INIT_00(256'h4600000000161A16161A161616161616161616161616161A1616161616161616),
.INIT_01(256'h76767676760000000000000000767676BA76767676767676BA76BA767676BA76),
.INIT_02(256'h16161616161616161616161A007676BA76BA76BA76BA76760076767676BA7676),
.INIT_03(256'h16161616161616161616161616161616161A1616161A1616161A161616161A16),
.INIT_04(256'h00000000767676767676767676BA7676767676BA767600206060600000161616),
.INIT_05(256'h1A161616003276767676767676BA760076BA7676767676BA7676767600000000),
.INIT_06(256'h161A161A16161A1616161A161616161616161A161616161A161A1616161A1616),
.INIT_07(256'h7676BAEE6600AA76767676763200A0606060600016161A16161A161A161A161A),
.INIT_08(256'h767676767676007676767676BA76767676BA76000000000000000076BA7676BA),
.INIT_09(256'h16161616161616161616161A1616161616161A16161616161616161600767676),
.INIT_0A(256'h767676EE00606060A06060001616161616161616161616161616161616161616),
.INIT_0B(256'hBA767676767676BA767676000000000000767676767676767676000000AABA76),
.INIT_0C(256'h161616161616161616161616161A16161A16161602BA76BA7676BA7676007676),
.INIT_0D(256'h60600016161A1616161616161616161616161A1616161A1616161A1616161A16),
.INIT_0E(256'h7676EE000000007676BA7676BA7676BA76AA4620767676BA7676AA0060A06060),
.INIT_0F(256'h16161A1616161616161A1600767676767676767600BA767676BA7676BA767676),
.INIT_10(256'h161A161A161A161A1616161A1616161A161616161616161A16161A161A161A16),
.INIT_11(256'h76767676767676767676BA76767632BA76EE0060606060A0600016161616161A),
.INIT_12(256'h161600767676BA7676BA7600767676767676767676767676BA76767676767676),
.INIT_13(256'h16161616161616161616161616161616161616161616161A161616161A161616),
.INIT_14(256'h767676BA7600AA76BA00206060206060001A16161A1616161616161616161616),
.INIT_15(256'h767600767676BA7676BA7676767632327676BA7676BA7676BA767676BA7676BA),
.INIT_16(256'h1616161A1616161A16161616161616161616161616161A16160076BA76767676),
.INIT_17(256'hAA2060A0606060001616161616161616161616161616161A1616161A1616161A),
.INIT_18(256'h7676AA2000200020EE7676767676767676BA7676767676760000000000767676),
.INIT_19(256'h1A161A161616161A161616161A161600767676767676BA76000076BA76767676),
.INIT_1A(256'h161A16161A161A161A161A161A1616161A1616161A161616161616161A161616),
.INIT_1B(256'h66BA3276BA7676767676760000000060600076767676767666006060A0001616),
.INIT_1C(256'h1A161616161600767676BA76767600160076767676BA3276000060606020A000),
.INIT_1D(256'h1616161616161616161616161616161616161616161616161616161A16161616),
.INIT_1E(256'hEE0000006060A02000767676BA76BA76AA000000000616161616161616161616),
.INIT_1F(256'h7676767600161616007676767676AA00E060A06060A0A6206676767676BA7676),
.INIT_20(256'h1A1616161A1616161A1616161A1616161616161A161616161A161616003276BA),
.INIT_21(256'h76BA3276767676BA7676001616161A16161A161616161616161616161A161616),
.INIT_22(256'h76BA7676BA6400A0606020606060200076BA7676767676BA7676000020606000),
.INIT_23(256'h161A1616161A161A161616161A161616161A1600BA76767676BA7600161A1600),
.INIT_24(256'hEE00161A1616161616161A161A161A161A161616161A1616161A161616161616),
.INIT_25(256'h60A06060606000327676767676BA767676760060606000767676767676767676),
.INIT_26(256'h1616161616161616161600767676763276001616161600767676767600A06060),
.INIT_27(256'h1616161616161616161A16161616161616161616161616161616161616161616),
.INIT_28(256'hBA76BA76767676BA76EE00A060007676BA76BA767676760016161616161A1616),
.INIT_29(256'h16160076BA32E82000161A1616160076BA767620606020606060A02020003276),
.INIT_2A(256'h16161616161A1616161A1616161A1616161A161616161A16161A16161A161616),
.INIT_2B(256'h7676000076BA767676763276BA00161A1616161616161A161616161616161616),
.INIT_2C(256'h1616161A1600EE7676764660A060A060606060200032767676767676767676BA),
.INIT_2D(256'h1616161616161A161616161A1616161616161616161A161A1600BAE820326000),
.INIT_2E(256'h76BA7676001616161A161A161616161A161A161A161A161A16161A1616161A16),
.INIT_2F(256'hBA7620602060606060A0E00076BA7676767676BA76767676BA76767676767676),
.INIT_30(256'h1A16161616161A16161A1616161616161600207660E00000161616161600EE76),
.INIT_31(256'h1616161616161616161616161616161616161616161616161616161616161616),
.INIT_32(256'h6420AA767676BA76BA767676767676767676BA7676BA76767676007600161616),
.INIT_33(256'h161616161616161600EE2032E8AA200016161A160A00767676BA206060A06060),
.INIT_34(256'h1616161616161A16161A1616161A161616161A16161616161616161A16161616),
.INIT_35(256'h7676BA7676BA7676767676767676BA767676763200161616161A161A16161616),
.INIT_36(256'h0032603260A622001616161A000000767676A0A0E020E0606076BA7676767676),
.INIT_37(256'h16161616161616161616161A16161A161A161616161A16161A161A161A161616),
.INIT_38(256'h76BA76767676767676BA760000161A1616161616161A161A161A161A16161616),
.INIT_39(256'h161616007676000076766000A0A076767676767676767676767676767676BA76),
.INIT_3A(256'h1616161616161616161616161616161616161616161A16120020326032202000),
.INIT_3B(256'h767676001616161616161A16161616161616161616161A16161A16161A161616),
.INIT_3C(256'h007676BA76BA3276BA7676BA76BA76BA7676BA76767676767676BA767676BA76),
.INIT_3D(256'h1A161A16161A1616161616161616160032AA203260EE001A1600EE76BA767600),
.INIT_3E(256'h16161616161616161616161A16161616161616161616161A1616161A16161616),
.INIT_3F(256'h76327676767676767676767676BA7676767676BA76767676BA76001616161A16),
.INIT_40(256'h1A1616161A1600206032203220A6001600EEEE7676BA76760000767676767676),
.INIT_41(256'h1A161616161A16161A161616161616161A161616161A16161616161616161A16),
.INIT_42(256'h76BA76767676BA767676767676BA76767676001A1616161A16161A161A161A16),
.INIT_43(256'h3220EE7620001600EE3276767676767676BA7676BA7676BA767676767676BA76),
.INIT_44(256'h1A1616161616161616161A1616161616161A161616161616161A161616003220),
.INIT_45(256'h76767676767676BA760016161616161616161616161616161616161616161616),
.INIT_46(256'h76767676BA76BA76767676767676767676BA76BA7676767676BA7676767676BA),
.INIT_47(256'h16161616161A161616161A1616161616161616003220322076E0200016160076),
.INIT_48(256'h7600161A1616161A1616161616161616161A16161A161616161616161A161616),
.INIT_49(256'hBA7676BA7676BA767676767676BA76767676BA7676767676BA76BA7676767676),
.INIT_4A(256'h161616161A161A161600322032603220324600161600767676BA767676767676),
.INIT_4B(256'h1A161A161A161A1616161616161616161A161616161A161A16161A1616161A16),
.INIT_4C(256'h7676767676767676767676BA76763276767676BA767676BA001616161A161616),
.INIT_4D(256'h00207620EE2032A00016161A0076BA7676767676767676767676767676767676),
.INIT_4E(256'h1A16161A161A16161616161616161616161616161616161616161A161616161A),
.INIT_4F(256'h76767676BA76327676767676BA76760016161616161616161616161616161616),
.INIT_50(256'h1616160076767676BA76BA76BA767676BA3276BA7676BA76BA767676BA7676BA),
.INIT_51(256'h161A161616161A16161A1616161A161A16161616161616003220322076600016),
.INIT_52(256'h76767676767676001A1616161A16161616161616161616161616161616161616),
.INIT_53(256'h7676767676BA7676767676767676767676BA7676767676767676767600BA76BA),
.INIT_54(256'h16161A16161616161616161A1616160032203220A016161A1616007676767676),
.INIT_55(256'h161A1616161A161A161A161A161A16161A161616161616161616161A16161616),
.INIT_56(256'h007676BA7676767676767676BA767676BA76320076767676BA76767676760016),
.INIT_57(256'h1A1616161A160060A66032001A16161616002ABA76BA7676767676767676BA76),
.INIT_58(256'h1616161616161616161A16161A1616161A16161616161A161616161616161616),
.INIT_59(256'h76BA767676BA7676763200767676767676760076BA0016161616161616161616),
.INIT_5A(256'hEE20001616161A0060AA76767676BA76BA7676767676320076767676BA767676),
.INIT_5B(256'h16161616161616161616161A1616161616161A161A1616161616161616163260),
.INIT_5C(256'h320076BA767676BA76002A76001616161A16161616161616161616161A161616),
.INIT_5D(256'h607676767676767676BA7676767676007676767676BA767676767676767676BA),
.INIT_5E(256'h1A161616161A161A16161616161A16161A1616161600322032A62016161620A0),
.INIT_5F(256'h20767600161A1616161A161A161A161A161A1616161A16161A161616161A1616),
.INIT_60(256'h7676BA76BA760032BA76767676BA767676BA76767676763200767676BA7632EE),
.INIT_61(256'h1616161616161616161A16160020326032E0201666602A666676BA7676767676),
.INIT_62(256'h1616161616161616161616161616161616161616161616161616161616161616),
.INIT_63(256'h76BA76767676BA767676BA76BA76320076767676767676007676001616161616),
.INIT_64(256'h161616160032203260EEA000006660202A767676BA76BA7676767676BA2A0076),
.INIT_65(256'h161A1616161A16161A1616161A1616161A161A16161616161A161A16161A1616),
.INIT_66(256'h7676767676320076BA767676BA0076762A201616161A16161616161616161616),
.INIT_67(256'hA03200004660A0667676BA76767676767676767676BA00767676767676767676),
.INIT_68(256'h16161616161A16161616161A161A16161616161616161616161A161600EE20A6),
.INIT_69(256'h76BA762A0076BA767600001616161A161A161A161A161A1616161A1616161616),
.INIT_6A(256'h7676767676BA76BA7676BA7676003276BA7676BA7676BA767676767676007676),
.INIT_6B(256'h1616161616161616161A16161A161A1616161600207632203260AA76AA0000AA),
.INIT_6C(256'h76000016161616161616161616161616161616161A161616161A161616161616),
.INIT_6D(256'h767676767600767676767676767676BA76BA7600767676767676760076767676),
.INIT_6E(256'h16161616161616161A160032206032200022BA76EE00003276BA767676767676),
.INIT_6F(256'h161616161616161A161616161616161616161616161A161A1616161616161A16),
.INIT_70(256'h7676BA767676767676000076BA76BA7676202A76BA7676BA76EE001A16161616),
.INIT_71(256'h161600203220762200767676767676767676BA76767676BA7676BA76000076BA),
.INIT_72(256'h1A16161A1616161616161A1616161616161A161A16161616161A161616161616),
.INIT_73(256'h00007676763276320076BA7676767676767600161A161A161A161A161A161616),
.INIT_74(256'h7676BA767676BA76767676BA76767676767676EE7600E8BA767676BA76767676),
.INIT_75(256'h161616161616161A1616161616161A1616161A161A1616161A16003220326020),
.INIT_76(256'h76767676BA7676BA760016161616161616161616161616161616161616161A16),
.INIT_77(256'h0000E8BA7676BA7676BA76762220767676767676BA7676760000EE7676767600),
.INIT_78(256'h16161A161616161616161616161A1616161200322060004676767676767676EE),
.INIT_79(256'h0246161616161616161616161A1616161A1616161616161A16161A161A161616),
.INIT_7A(256'h76BA7600007676BA7676767676BA76AA0000BA00767600BA7676767676767676),
.INIT_7B(256'h161616161616161A1600322032A000327676BA7676BA7676BA20003276767676),
.INIT_7C(256'h161A1616161A16161616161616161616161616161616161616161A1616161A16),
.INIT_7D(256'h76BA767676327632000000000076767676BA7676BA76760002020000161A161A),
.INIT_7E(256'h16003260A666607676767676767676767676000032BA76767676000076767676),
.INIT_7F(256'h161616161A16161A1616161A16161A161616161A161616161A161A1616161616),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra[11:0],1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],DOADO}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],DOPADOP}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0 ),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT2 #(
.INIT(4'h2))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0
(.I0(addra[12]),
.I1(addra[13]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0 ));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module bg_tex_blk_mem_gen_prim_wrapper_init__parameterized3
(\douta[10] ,
\douta[11] ,
clka,
addra,
dina,
wea);
output [7:0]\douta[10] ;
output [0:0]\douta[11] ;
input clka;
input [13:0]addra;
input [8:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0 ;
wire [13:0]addra;
wire clka;
wire [8:0]dina;
wire [7:0]\douta[10] ;
wire [0:0]\douta[11] ;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'hFFFFFFEF80000000000013FFC07FFFFFF88000000000000BFFE61FFFFFFC0000),
.INITP_01(256'h000000E7FFFFFFFFFFFC00000000000047FFCFFFFFFFFF80000000000003FFE1),
.INITP_02(256'hFFF000000000000001FFF87FFFFFF800000000000000FFFEFFFFFFFE00000000),
.INITP_03(256'h0001FF56FE0FFF0000000000000001FFA37FFFFFC000000000000001FFE53FFF),
.INITP_04(256'h0000000000000003FDFB0003F80000000000000003FEBDE007FE000000000000),
.INITP_05(256'h03EC000000400000000000000003F6000001E00000000000000003FBC00001F0),
.INITP_06(256'h00000000000001A0000000000000000000000003D80000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000003000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h76767676767676BA76767676767600000000000016161616161616161616161A),
.INIT_01(256'h7676BA7676BA767676767600EE7676EE0000AA76BA76767676767676BA763276),
.INIT_02(256'h16161616161616161616161616161A161616161A1616161A000000A020A03276),
.INIT_03(256'h76BA7676BA00E82076000000161616161A1616161A1616161616161616161616),
.INIT_04(256'h7676EE0000000000002A767676BA7676BA76767676BA767676BA76BA76767676),
.INIT_05(256'h1A16161A16161616161616161A16161600000032E00276BA76767676767676BA),
.INIT_06(256'h76AA0016161A1616161A161616161616161A16161A16161A16161A16161A1616),
.INIT_07(256'h76BA767676767676BA7676767676BA76767676BA767676767676760076BA7676),
.INIT_08(256'h1616161616161616160000A022A0767676BA7676BA76767676BA76000000EE32),
.INIT_09(256'h161616161A16161616161616161616161616161616161616161616161616161A),
.INIT_0A(256'h7676BA767676767676767676BA76BA7676767676767676BA76001A1616161616),
.INIT_0B(256'h0076AA2000767676767676767676BA767676AAAA32BA76BA76767676BA767676),
.INIT_0C(256'h1A1616161A16161A16161A16161A16161A1616161A1616161A1616161A161A16),
.INIT_0D(256'h76767676767676767676762ABA76000016161616161A1616161A161616161616),
.INIT_0E(256'hBA7676767676767676BA76767676767676BA767676767676BA7676767676BA76),
.INIT_0F(256'h1616161616161616161A161616161616161A16161616160032762A22AA767676),
.INIT_10(256'h6600200000001616161A161616161A161616161616161616161A161616161616),
.INIT_11(256'h7676BA767676BA76767676BA76BA76767676BA76767676BA7676767676BA76EE),
.INIT_12(256'h1616161A161616161616161616160000BA76BA7676BA767676BA7676BA76BAE8),
.INIT_13(256'h161A1616161616161A161616161A16161616161A1616161A16161A16161A1616),
.INIT_14(256'h76767676767676767676BA7676767676BA76BA7676EE000020200020161A1616),
.INIT_15(256'h161A161A16160032767676767676767676767676760020000076767676767676),
.INIT_16(256'h1616161616161616161616161A161616161616161616161616161616161A1616),
.INIT_17(256'h76767676BA767676767676326000202000001616161616161616161A16161616),
.INIT_18(256'h7676BA7676BA767676BA76000032007600EE76BA7676BA76BA7676767676BA76),
.INIT_19(256'h1A16161616161A16161A1616161A161A16161A1616161A161616161616160076),
.INIT_1A(256'h767600002060600016161A16161A1616161A16161A1616161A16161616161A16),
.INIT_1B(256'h76007600EE007676007676767676767676BA76BA767676767676BA7676767676),
.INIT_1C(256'h16161A1616161616161616161616161616161A161600EEBA767676767676BA76),
.INIT_1D(256'h1616161616161A1616161616161A161616161A16161616161616161616161616),
.INIT_1E(256'h7676BA76767676EEAAEEEEEE76BA76BA76767676BA76BA76EE00200020200016),
.INIT_1F(256'h161A1616161A161A1616161A1600EE767676BA7676767676007600320032BA00),
.INIT_20(256'h16161616161616161616161A1616161A161A1616161A16161616161616161A16),
.INIT_21(256'h000000606632767676767676767676200020202000161A16161A161616161616),
.INIT_22(256'h16161616160076BA7676767676BA7600BAE8BA7676760076767676EEA0000000),
.INIT_23(256'h161616161616161616161A1616161A161616161A1616161616161A1616161616),
.INIT_24(256'h76BA767676EE0060A02000661616161616161A16161A16161A161A1616161616),
.INIT_25(256'h7676BA7676760076BA7676767600BA76A0000000206020202060000000A02A76),
.INIT_26(256'h16161616161616161A16161616161A16161616161616161A16161A1616007676),
.INIT_27(256'h0016161A16161A161616161616161616161616161A161616161A16161A161616),
.INIT_28(256'h7632002000AA46002020202020002020202020200020AA767676BA7666002000),
.INIT_29(256'h1616161A1616161616161A161616161616161616160076BA7676767676007676),
.INIT_2A(256'h161A16161A161616161A161616161A1616161616161A161616161A1616161A16),
.INIT_2B(256'h2020202020202020202060200000002A76767660202000201616161616161616),
.INIT_2C(256'h1616161A16161A16161A16161600767676BA76760076BAE82000000000002060),
.INIT_2D(256'h16161616161616161A16161616161A161616161A161616161A161616161A161A),
.INIT_2E(256'h0000000000002066EE2A00200000161A16161A1616161A161616161616161A16),
.INIT_2F(256'h16161A161600767676BA76007676200020000000002020000060206000602020),
.INIT_30(256'h161A161616161A16161616161616161616161616161616161616161616161616),
.INIT_31(256'h00600000161616161616161A161616161A16161A161616161616161616161616),
.INIT_32(256'h767600BA32002020200000206000202020202020000000001616161616161600),
.INIT_33(256'h16161A16161A16161A161A16161616161A16161A16161A161616161A16007676),
.INIT_34(256'h16161616161616161616161616161A161616161A161A161616161A161616161A),
.INIT_35(256'h2020202020600020000000161616161616161A1616161616161616161616161A),
.INIT_36(256'h1616161A161A16161616161616161616161616161600EE76760076A000202020),
.INIT_37(256'h1A16161A16161616161616161616161616161616161616161616161616161616),
.INIT_38(256'h161616161A161A161616161A1616161A16161A161A16161616161A161A161616),
.INIT_39(256'h1616161A16161A1616161A16160076BA00460020202000000020602020000016),
.INIT_3A(256'h161616161A161A16161A16161A16161A16161A16161A1616161616161616161A),
.INIT_3B(256'h161616161A161616161616161616161A16161616161A161616161616161A1616),
.INIT_3C(256'h1616161A1600002200000020602000200000001616161616161A161616161A16),
.INIT_3D(256'h1616161616161616161616161616161A16161616161616161A1616161616161A),
.INIT_3E(256'h161616161A16161616161616161616161A16161616161616161A161616161616),
.INIT_3F(256'h20002020200000166616161616161A1616161616161616161A1616161616161A),
.INIT_40(256'h161A16161A1616161A161A161A1616161616161A161616161616161616000000),
.INIT_41(256'h161A1616161A1616161A16161616161616161616161A16161A16161A16161A16),
.INIT_42(256'h1A161A1616161616161A161616161A16161616161A1616161A1616161616161A),
.INIT_43(256'h16161616161616161A1616161616161A1616161616AA00006060200000161616),
.INIT_44(256'h16161A1616161A16161A16161616161616161616161616161616161616161616),
.INIT_45(256'h16161A16161616161A16161616161616161A16161A16161616161A1616161616),
.INIT_46(256'h16161A161A1616161A161A1616600000202000166A1A16161616161A16161A16),
.INIT_47(256'h16161A16161A16161A16161A16161A16161A16161A1616161616161A161A1616),
.INIT_48(256'h1A1616161A161616161616161616161616161616161A16161616161616161616),
.INIT_49(256'h1616161A160020600020161A16161616161616161616161616161A1616161616),
.INIT_4A(256'h16161616161616161616161616161A161A161616161616161616161616161616),
.INIT_4B(256'h1A1616161A161A1616161A1616161A1616161616161A16161616161616161616),
.INIT_4C(256'h16161616161A161A16161A1616161A16161616161A161616161A1616161A1616),
.INIT_4D(256'h1A16161A1616161616161616161A161A16161616161A16161616161616000046),
.INIT_4E(256'h161616161616161A1616161616161A16161A16161A16161A16161A16161A1616),
.INIT_4F(256'h1616161A1616161616161A16161616161616161616161616161A16161616161A),
.INIT_50(256'h1A161A16161616161A161A1616161A161616161616161616161A161616161616),
.INIT_51(256'h1616161616161616161616161616161616161616161616161616161616161616),
.INIT_52(256'h161616161A1616161A1616161A1616161616161616161616161A161616161616),
.INIT_53(256'h161616161616161A161A1616161616161616161616161A1616161616161A161A),
.INIT_54(256'h161A16161A16161A16161A16161A16161A16161A161A16161616161616161616),
.INIT_55(256'h161616161616161616161616161616161616161616161616161A1616161A1616),
.INIT_56(256'h1616161616161616161616161616161616161616161616161616161616161616),
.INIT_57(256'h1616161616161616161616161616161616161616161616161616161616161616),
.INIT_58(256'h1616161616161616161616161616161616161616161616161616161616161616),
.INIT_59(256'h1616161616161616161616161616161616161616161616161616161616161616),
.INIT_5A(256'h1616161616161616161616161616161616161616161616161616161616161616),
.INIT_5B(256'h0000000000001616161616161616161616161616161616161616161616161616),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra[11:0],1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],\douta[10] }),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],\douta[11] }),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0 ),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT2 #(
.INIT(4'h2))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1
(.I0(addra[13]),
.I1(addra[12]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0 ));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module bg_tex_blk_mem_gen_top
(douta,
addra,
clka,
dina,
wea);
output [11:0]douta;
input [13:0]addra;
input clka;
input [11:0]dina;
input [0:0]wea;
wire [13:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
bg_tex_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* C_ADDRA_WIDTH = "14" *) (* C_ADDRB_WIDTH = "14" *) (* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "4" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 6.22775 mW" *)
(* C_FAMILY = "artix7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "bg_tex.mem" *)
(* C_INIT_FILE_NAME = "bg_tex.mif" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "11130" *) (* C_READ_DEPTH_B = "11130" *) (* C_READ_WIDTH_A = "12" *)
(* C_READ_WIDTH_B = "12" *) (* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *) (* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *) (* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *) (* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "11130" *) (* C_WRITE_DEPTH_B = "11130" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *)
(* C_XDEVICEFAMILY = "artix7" *) (* ORIG_REF_NAME = "blk_mem_gen_v8_3_5" *) (* downgradeipidentifiedwarnings = "yes" *)
module bg_tex_blk_mem_gen_v8_3_5
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
rsta_busy,
rstb_busy,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [13:0]addra;
input [11:0]dina;
output [11:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [13:0]addrb;
input [11:0]dinb;
output [11:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [13:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
output rsta_busy;
output rstb_busy;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [11:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [13:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [13:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
assign dbiterr = \<const0> ;
assign doutb[11] = \<const0> ;
assign doutb[10] = \<const0> ;
assign doutb[9] = \<const0> ;
assign doutb[8] = \<const0> ;
assign doutb[7] = \<const0> ;
assign doutb[6] = \<const0> ;
assign doutb[5] = \<const0> ;
assign doutb[4] = \<const0> ;
assign doutb[3] = \<const0> ;
assign doutb[2] = \<const0> ;
assign doutb[1] = \<const0> ;
assign doutb[0] = \<const0> ;
assign rdaddrecc[13] = \<const0> ;
assign rdaddrecc[12] = \<const0> ;
assign rdaddrecc[11] = \<const0> ;
assign rdaddrecc[10] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign rsta_busy = \<const0> ;
assign rstb_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[13] = \<const0> ;
assign s_axi_rdaddrecc[12] = \<const0> ;
assign s_axi_rdaddrecc[11] = \<const0> ;
assign s_axi_rdaddrecc[10] = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
bg_tex_blk_mem_gen_v8_3_5_synth inst_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_5_synth" *)
module bg_tex_blk_mem_gen_v8_3_5_synth
(douta,
addra,
clka,
dina,
wea);
output [11:0]douta;
input [13:0]addra;
input clka;
input [11:0]dina;
input [0:0]wea;
wire [13:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
bg_tex_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// "and_tree_plusarg.v"
// This variant demonstrates using a plusarg to pass in the name of
// a HAC object file.
// @vcs-flags@ -P pli.tab -sverilog
// @haco@ and_tree.haco-c
// @plusargs@ +PRSIM_OBJ=and_tree.haco-c
`timescale 1ps / 1ps
// `include "standard.v"
`include "standard.v-wrap"
//-----------------------------------------------------------------------------
module _timeunit;
initial $timeformat(-9,1," ns",9);
endmodule
module TOP;
reg a, b, c, d;
wire z;
initial
begin
string prs_obj;
if (!$value$plusargs("PRSIM_OBJ=%s", prs_obj)) begin
prs_obj = "Missing +PRSIM_OBJ=objfile argument.";
end
$prsim(prs_obj);
$prsim_cmd("echo $start of simulation");
$prsim_cmd("watchall");
$to_prsim("TOP.a", "a");
$to_prsim("TOP.b", "b");
$to_prsim("TOP.c", "c");
$to_prsim("TOP.d", "d");
$from_prsim("z", "TOP.z");
end
// these could be automatically generated
// by finding all globally unique instances of processes
// along with their hierarchical names
// e.g. from hacobjdump of .haco-c file
HAC_AND2 and_0();
defparam and_0.prsim_name="mytree.and_0";
HAC_AND2 and_1();
defparam and_1.prsim_name="mytree.and_1";
HAC_AND2 and_2();
defparam and_2.prsim_name="mytree.and_2";
initial
begin
#10 a <= 1'b0;
b <= 1'b0;
c <= 1'b0;
d <= 1'b0;
#100 a <= 1'b1;
b <= 1'b1;
c <= 1'b1;
d <= 1'b1;
#100 a <= 1'b0;
#100 d <= 1'b0;
#100 a <= 1'b1;
#100 d <= 1'b1;
#50 $finish;
end
endmodule
|
// Simple 8-bit UART receiver
// Author: Ross MacArthur (https://github.com/rossmacarthur)
// Description:
// - Samples input line at 16 time the baudrate
// - Receives data in 8-bit chunks, LSB first
// - No parity
// - Single start and stop bit
module UART_RX (
input clk, // 16 * baudrate
input rst, // enable receiver
input RX, // UART receive line
output reg busy, // high when receiving
output reg [7:0] data // received data
);
reg RX_d;
reg [9:0] datafill;
reg [3:0] index;
reg [3:0] sampler;
always @(posedge clk) begin
RX_d <= RX;
if (rst) begin
busy <= 1'b0;
datafill <= 10'b0;
index <= 4'b0;
sampler <= 4'b0;
end else begin
if (~busy & ~RX_d) begin
busy <= 1'b1;
sampler <= 4'b0;
index <= 4'b0;
end
if (busy) begin
sampler <= sampler + 1'b1;
if (sampler == 4'd7) begin
if (RX_d & ~|index)
busy <= 1'b0;
else begin
index <= index + 1'b1;
datafill[index] <= RX_d;
if (index == 9) begin
data <= datafill[8:1];
index <= 4'b0;
busy <= 1'b0;
end
end
end
end
end
end
endmodule
|
/*
* Copyright 2012, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`timescale 1ns / 1ps
`define P 20 // clock period
module test_const;
// Inputs
reg clk;
reg [5:0] addr;
// Outputs
wire [1007:0] out;
wire effective;
reg [1007:0] w_out;
reg w_effective;
// Instantiate the Unit Under Test (UUT)
const_ uut (
.clk(clk),
.addr(addr),
.out(out),
.effective(effective)
);
initial begin
// Initialize Inputs
addr = 0; clk = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
@ (negedge clk);
addr = 1; w_out = 0; w_effective = 1;
#(`P); check;
addr = 2; w_out = 1;
#(`P); check;
addr = 4; w_out = {6'b000101, 1002'd0};
#(`P); check;
addr = 8; w_out = {6'b001001, 1002'd0};
#(`P); check;
addr = 16; w_out = {6'b010101, 1002'd0};
#(`P); check;
addr = 0; w_out = 0; w_effective = 0;
#(`P); check;
$display("Good");
$finish;
end
initial #100 forever #(`P/2) clk = ~clk;
task check;
begin
if (out !== w_out || effective !== w_effective)
$display("E %d %h %h", addr, out, w_out);
end
endtask
endmodule
|
module OSERDESE2 ( /*AUTOARG*/
// Outputs
OFB, OQ, SHIFTOUT1, SHIFTOUT2, TBYTEOUT, TFB, TQ,
// Inputs
CLK, CLKDIV, D1, D2, D3, D4, D5, D6, D7, D8, OCE, RST, SHIFTIN1,
SHIFTIN2, T1, T2, T3, T4, TBYTEIN, TCE
);
parameter DATA_RATE_OQ=0;
parameter DATA_RATE_TQ=0;
parameter DATA_WIDTH=0;
parameter INIT_OQ=0;
parameter INIT_TQ=0;
parameter SERDES_MODE=0;
parameter SRVAL_OQ=0;
parameter SRVAL_TQ=0;
parameter TBYTE_CTL=0;
parameter TBYTE_SRC=0;
parameter TRISTATE_WIDTH=0;
output OFB; // output feedback port
output OQ; // data output port, D1 appears first
output SHIFTOUT1; // connect to shift in of master, example?
output SHIFTOUT2; // connect to shift in of master, example?
output TBYTEOUT; // byte group tristate output to IOB
output TFB; // 3-state control output for ODELAYE2
output TQ; // 3-state control output
input CLK; // high speed clock
input CLKDIV; // low speed clock (/8 for example)
input D1; //
input D2; //
input D3; //
input D4; //
input D5; //
input D6; //
input D7; //
input D8; //
input OCE; // active high clock enable for datapath
input RST; // async reset, all output flops driven low
input SHIFTIN1; // connect to shift out of other
input SHIFTIN2; // connect to shift out of other
input T1; // parallel 3-state signals
input T2; // ??why 4??
input T3; //
input T4; //
input TBYTEIN; // byte group tristate input
input TCE; // active high clock enable for 3-state
//Statemachine
reg [2:0] state;
reg [7:0] buffer;
reg [1:0] clkdiv_sample;
reg [3:0] even;
reg [3:0] odd;
//parallel sample
always @ (posedge CLKDIV)
buffer[7:0]<={D8,D7,D6,D5,D4,D3,D2,D1};
//sample clkdiv
always @ (negedge CLK)
clkdiv_sample[1:0] <= {clkdiv_sample[0],CLKDIV};
//shift on second consective clk rising edge that clkdi_sample==0
wire load_parallel = (clkdiv_sample[1:0]==2'b00);
always @ (negedge CLK)
if(load_parallel)
even[3:0]<={buffer[6],buffer[4],buffer[2],buffer[0]};
else
even[3:0]<={1'b0,even[3:1]};
always @ (negedge CLK)
if(load_parallel)
odd[3:0]<={buffer[7],buffer[5],buffer[3],buffer[1]};
else
odd[3:0]<={1'b0,odd[3:1]};
assign OQ = CLK ? even[0] : odd[0];
//setting other outputs
assign OFB = 1'b0;
assign TQ = 1'b0;
assign TBYTEOUT = 1'b0;
assign SHIFTOUT1 = 1'b0;
assign SHIFTOUT2 = 1'b0;
assign TFB = 1'b0;
endmodule // OSERDESE2
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRSDFSTP_BEHAVIORAL_V
`define SKY130_FD_SC_LP__SRSDFSTP_BEHAVIORAL_V
/**
* srsdfstp: Scan flop with sleep mode, inverted set, non-inverted
* clock, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`include "../../models/udp_dff_ps_pp_pkg_sn/sky130_fd_sc_lp__udp_dff_ps_pp_pkg_sn.v"
`celldefine
module sky130_fd_sc_lp__srsdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B ,
SLEEP_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B ;
input SLEEP_B;
// Module supplies
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire SET ;
wire mux_out ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire SET_B_delayed ;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
wire pwrgood_pp0_out_Q;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out , D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_lp__udp_dff$PS_pp$PKG$sN dff0 (buf_Q , mux_out, CLK_delayed, SET, SLEEP_B, notifier, KAPWR, VGND, VPWR);
assign awake = ( ( SLEEP_B === 1'b1 ) && awake );
assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 && awake );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 && awake );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 && awake );
assign cond4 = ( ( SET_B === 1'b1 ) && awake );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Q, buf_Q, VPWR, VGND );
buf buf0 (Q , pwrgood_pp0_out_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRSDFSTP_BEHAVIORAL_V |
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_frame (clock, reset, enable, start_event, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter min_cks = 0;
parameter max_cks = 0;
parameter action_on_new_start = `OVL_ACTION_ON_NEW_START_DEFAULT;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input start_event;
input test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_FRAME";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_SYNTHESIS
`else
// Sanity Checks
initial begin
if (~((action_on_new_start == `OVL_IGNORE_NEW_START) ||
(action_on_new_start == `OVL_RESET_ON_NEW_START) ||
(action_on_new_start == `OVL_ERROR_ON_NEW_START)))
begin
ovl_error_t(`OVL_FIRE_2STATE,"Illegal value set for parameter action_on_new_start");
end
//
if ((max_cks > 0) && (min_cks > max_cks)) begin
ovl_error_t(`OVL_FIRE_2STATE,"Illegal parameter values set where min_cks > max_cks");
end
end
`endif
`ifdef OVL_VERILOG
`include "./vlog95/assert_frame_logic.v"
assign fire = {fire_cover, fire_xcheck, fire_2state};
`endif
`ifdef OVL_SVA
`include "./sva05/assert_frame_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_frame_psl_logic.v"
`else
`endmodule // ovl_frame
`endif
|
`timescale 1ns / 1ps
// @module
// top module
// @input
// clk_src: bind to E3(100Hz)
// power: electric power
// enable: enable switch(pause switch)
// reset: reset switch
// add_time/sub_time: add/sub time manually
// timing_clock_switch: switch for enabling to change timing clock
// timing_clock_disable: shutdown timing clock manually
// @output
// alarm: round time alarm
// timing_clock_alarm: timing clock arrive
// anodes/cnodes: displaye time
module clock
#(parameter WIDTH = 32, CLK_CH = 25, SEC_RANGE = 60, MIN_RANGE = 60, HOUR_RANGE = 24, LEN = 30, NUM = 5)
(
input clk_src,
input power,
input enable,
input reset,
input [2:0] add_time,
input [2:0] sub_time,
input timing_clock_switch,
input timing_clock_disable,
output alarm,
output [(NUM-1):0] timing_clock_alarm,
output [7:0] anodes,
output [7:0] cnodes
);
// record current time
wire [(WIDTH-1):0] sec, min, hour;
// record whole point signal
wire sig_sec, sig_min, sig_hour;
// divided clock source
wire clk_dst;
wire [(WIDTH-1):0] clk_group;
// segment light when power on
wire [7:0] inner_anodes, inner_cnodes;
// segment light of timing clock
wire [7:0] timing_anodes, timing_cnodes;
range_divider DRANGE_DIVIDER (
.clk_src(clk_src),
.clk_dst(clk_dst)
);
// for debug only
// assign clk_dst = clk_group[0];
tick_divider TICK_DIVIDER (
.clk_src(clk_src),
.clk_group(clk_group)
);
timer #(.WIDTH(WIDTH), .RANGE(SEC_RANGE)) SEC_TIMER (
.clk_normal(clk_dst),
// && !timing_clock_switch : when changing timing clock, lock manual changing of real clock
.clk_change_time(clk_group[CLK_CH] && !timing_clock_switch),
.power(power),
.enable(enable),
.reset(reset),
.add_time(add_time[0]),
.sub_time(sub_time[0]),
.count(sec),
.sig_end(sig_sec)
);
timer #(.WIDTH(WIDTH), .RANGE(MIN_RANGE)) MIN_TIMER (
.clk_normal(sig_sec),
.clk_change_time(clk_group[CLK_CH] && !timing_clock_switch),
.power(power),
.enable(enable),
.reset(reset),
.add_time(add_time[1]),
.sub_time(sub_time[1]),
.count(min),
.sig_end(sig_min)
);
timer #(.WIDTH(WIDTH), .RANGE(HOUR_RANGE)) HOUR_TIMER (
.clk_normal(sig_min),
.clk_change_time(clk_group[CLK_CH] && !timing_clock_switch),
.power(power),
.enable(enable),
.reset(reset),
.add_time(add_time[2]),
.sub_time(sub_time[2]),
.count(hour),
.sig_end(sig_hour)
);
time_displayer SEG_SEVEN (
.clk_src(clk_group[15]),
.sec_data(sec),
.min_data(min),
.hour_data(hour),
// when power off, light off
.anodes(inner_anodes),
.cnodes(inner_cnodes)
);
ring RING (
.power(power),
.sig_ring(sec == (SEC_RANGE-1) && min == (MIN_RANGE-1) && enable),
.sig_step(clk_dst),
.alarm(alarm)
);
timing_clock #(WIDTH, CLK_CH, SEC_RANGE, MIN_RANGE, HOUR_RANGE, LEN, NUM) TIMING_CLOCK (
.clk_dst(clk_dst),
.clk_group(clk_group),
.timing_clock_switch(timing_clock_switch),
.timing_clock_disable(timing_clock_disable),
.power(power),
.enable(enable),
.reset(reset),
.add_time(add_time),
.sub_time(sub_time),
.sec(sec),
.min(min),
.hour(hour),
.timing_anodes(timing_anodes),
.timing_cnodes(timing_cnodes),
.timing_clock_alarm(timing_clock_alarm)
);
assign anodes = !power ? 8'b11111111
: timing_clock_switch ? timing_anodes
: inner_anodes;
assign cnodes = !power ? 8'b11111111
: timing_clock_switch ? timing_cnodes
: inner_cnodes;
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Wed Oct 18 15:15:21 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode funcsim
// /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_processing_system7_0_0/ip_design_processing_system7_0_0_sim_netlist.v
// Design : ip_design_processing_system7_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "ip_design_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2017.3" *)
(* NotValidForBitStream *)
module ip_design_processing_system7_0_0
(I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
FCLK_CLK0,
FCLK_CLK1,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_I" *) input I2C0_SDA_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_O" *) output I2C0_SDA_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_T" *) output I2C0_SDA_T;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_I" *) input I2C0_SCL_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_O" *) output I2C0_SCL_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_T" *) output I2C0_SCL_T;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *) output [1:0]USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *) output USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *) input USB0_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *) output M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *) output M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *) output M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *) output M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *) output M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *) output M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *) output [11:0]M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *) output [11:0]M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *) output [11:0]M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *) output [1:0]M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *) output [1:0]M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *) output [2:0]M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *) output [1:0]M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *) output [1:0]M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *) output [2:0]M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *) output [2:0]M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *) output [2:0]M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *) output [31:0]M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *) output [31:0]M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *) output [31:0]M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *) output [3:0]M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *) output [3:0]M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *) output [3:0]M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *) output [3:0]M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *) output [3:0]M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *) output [3:0]M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *) output [3:0]M_AXI_GP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0" *) input M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *) input M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *) input M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *) input M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *) input M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *) input M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *) input M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *) input [11:0]M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *) input [11:0]M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *) input [1:0]M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *) input [1:0]M_AXI_GP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input [31:0]M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0" *) output FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK1 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK1, FREQ_HZ 10000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK1" *) output FCLK_CLK1;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW" *) output FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) inout [14:0]DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) inout DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11" *) inout [3:0]DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *) inout PS_PORB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire FCLK_CLK0;
wire FCLK_CLK1;
wire FCLK_RESET0_N;
wire I2C0_SCL_I;
wire I2C0_SCL_O;
wire I2C0_SCL_T;
wire I2C0_SDA_I;
wire I2C0_SDA_O;
wire I2C0_SDA_T;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]M_AXI_GP0_ARCACHE;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [2:0]M_AXI_GP0_ARSIZE;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]M_AXI_GP0_AWCACHE;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [2:0]M_AXI_GP0_AWSIZE;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire NLW_inst_CAN0_PHY_TX_UNCONNECTED;
wire NLW_inst_CAN1_PHY_TX_UNCONNECTED;
wire NLW_inst_DMA0_DAVALID_UNCONNECTED;
wire NLW_inst_DMA0_DRREADY_UNCONNECTED;
wire NLW_inst_DMA0_RSTN_UNCONNECTED;
wire NLW_inst_DMA1_DAVALID_UNCONNECTED;
wire NLW_inst_DMA1_DRREADY_UNCONNECTED;
wire NLW_inst_DMA1_RSTN_UNCONNECTED;
wire NLW_inst_DMA2_DAVALID_UNCONNECTED;
wire NLW_inst_DMA2_DRREADY_UNCONNECTED;
wire NLW_inst_DMA2_RSTN_UNCONNECTED;
wire NLW_inst_DMA3_DAVALID_UNCONNECTED;
wire NLW_inst_DMA3_DRREADY_UNCONNECTED;
wire NLW_inst_DMA3_RSTN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_TX_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_TX_UNCONNECTED;
wire NLW_inst_EVENT_EVENTO_UNCONNECTED;
wire NLW_inst_FCLK_CLK2_UNCONNECTED;
wire NLW_inst_FCLK_CLK3_UNCONNECTED;
wire NLW_inst_FCLK_RESET1_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET2_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET3_N_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED;
wire NLW_inst_I2C1_SCL_O_UNCONNECTED;
wire NLW_inst_I2C1_SCL_T_UNCONNECTED;
wire NLW_inst_I2C1_SDA_O_UNCONNECTED;
wire NLW_inst_I2C1_SDA_T_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED;
wire NLW_inst_PJTAG_TDO_UNCONNECTED;
wire NLW_inst_SDIO0_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO0_CLK_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO0_LED_UNCONNECTED;
wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO1_CLK_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO1_LED_UNCONNECTED;
wire NLW_inst_SPI0_MISO_O_UNCONNECTED;
wire NLW_inst_SPI0_MISO_T_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI0_SS1_O_UNCONNECTED;
wire NLW_inst_SPI0_SS2_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_T_UNCONNECTED;
wire NLW_inst_SPI1_MISO_O_UNCONNECTED;
wire NLW_inst_SPI1_MISO_T_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI1_SS1_O_UNCONNECTED;
wire NLW_inst_SPI1_SS2_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_T_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED;
wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED;
wire NLW_inst_TRACE_CTL_UNCONNECTED;
wire NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED;
wire NLW_inst_UART0_DTRN_UNCONNECTED;
wire NLW_inst_UART0_RTSN_UNCONNECTED;
wire NLW_inst_UART0_TX_UNCONNECTED;
wire NLW_inst_UART1_DTRN_UNCONNECTED;
wire NLW_inst_UART1_RTSN_UNCONNECTED;
wire NLW_inst_UART1_TX_UNCONNECTED;
wire NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED;
wire NLW_inst_WDT_RST_OUT_UNCONNECTED;
wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED;
wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED;
wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED;
wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_O_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_T_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_ARID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_AWID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_WID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED;
wire [2:0]NLW_inst_SDIO0_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED;
wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED;
wire [1:0]NLW_inst_USB1_PORT_INDCTL_UNCONNECTED;
(* C_DM_WIDTH = "4" *)
(* C_DQS_WIDTH = "4" *)
(* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *)
(* C_EN_EMIO_ENET0 = "0" *)
(* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *)
(* C_EN_EMIO_TRACE = "0" *)
(* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "TRUE" *)
(* C_FCLK_CLK2_BUF = "FALSE" *)
(* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "1" *)
(* C_GP1_EN_MODIFIABLE_TXN = "1" *)
(* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *)
(* C_IRQ_F2P_MODE = "DIRECT" *)
(* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP0_ID_WIDTH = "12" *)
(* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP1_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *)
(* C_PACKAGE_NAME = "clg484" *)
(* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *)
(* C_S_AXI_ACP_AWUSER_VAL = "31" *)
(* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *)
(* C_S_AXI_GP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *)
(* C_S_AXI_HP1_DATA_WIDTH = "64" *)
(* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *)
(* C_S_AXI_HP2_ID_WIDTH = "6" *)
(* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *)
(* C_TRACE_BUFFER_CLOCK_DELAY = "12" *)
(* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *)
(* C_TRACE_PIPELINE_WIDTH = "8" *)
(* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *)
(* C_USE_M_AXI_GP0 = "1" *)
(* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *)
(* C_USE_S_AXI_GP0 = "0" *)
(* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *)
(* C_USE_S_AXI_HP1 = "0" *)
(* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *)
(* HW_HANDOFF = "ip_design_processing_system7_0_0.hwdef" *)
(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={I2C} ioStandard={} bidis={1} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7 inst
(.CAN0_PHY_RX(1'b0),
.CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED),
.CAN1_PHY_RX(1'b0),
.CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED),
.Core0_nFIQ(1'b0),
.Core0_nIRQ(1'b0),
.Core1_nFIQ(1'b0),
.Core1_nIRQ(1'b0),
.DDR_ARB({1'b0,1'b0,1'b0,1'b0}),
.DDR_Addr(DDR_Addr),
.DDR_BankAddr(DDR_BankAddr),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_CS_n(DDR_CS_n),
.DDR_Clk(DDR_Clk),
.DDR_Clk_n(DDR_Clk_n),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS(DDR_DQS),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_WEB(DDR_WEB),
.DMA0_ACLK(1'b0),
.DMA0_DAREADY(1'b0),
.DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]),
.DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED),
.DMA0_DRLAST(1'b0),
.DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED),
.DMA0_DRTYPE({1'b0,1'b0}),
.DMA0_DRVALID(1'b0),
.DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED),
.DMA1_ACLK(1'b0),
.DMA1_DAREADY(1'b0),
.DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]),
.DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED),
.DMA1_DRLAST(1'b0),
.DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED),
.DMA1_DRTYPE({1'b0,1'b0}),
.DMA1_DRVALID(1'b0),
.DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED),
.DMA2_ACLK(1'b0),
.DMA2_DAREADY(1'b0),
.DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]),
.DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED),
.DMA2_DRLAST(1'b0),
.DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED),
.DMA2_DRTYPE({1'b0,1'b0}),
.DMA2_DRVALID(1'b0),
.DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED),
.DMA3_ACLK(1'b0),
.DMA3_DAREADY(1'b0),
.DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]),
.DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED),
.DMA3_DRLAST(1'b0),
.DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED),
.DMA3_DRTYPE({1'b0,1'b0}),
.DMA3_DRVALID(1'b0),
.DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED),
.ENET0_EXT_INTIN(1'b0),
.ENET0_GMII_COL(1'b0),
.ENET0_GMII_CRS(1'b0),
.ENET0_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET0_GMII_RX_CLK(1'b0),
.ENET0_GMII_RX_DV(1'b0),
.ENET0_GMII_RX_ER(1'b0),
.ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]),
.ENET0_GMII_TX_CLK(1'b0),
.ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED),
.ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED),
.ENET0_MDIO_I(1'b0),
.ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED),
.ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED),
.ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_RX(NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_TX(NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_RX(NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_TX(NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_RX(NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_TX(NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_RX(NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_TX(NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET0_SOF_RX(NLW_inst_ENET0_SOF_RX_UNCONNECTED),
.ENET0_SOF_TX(NLW_inst_ENET0_SOF_TX_UNCONNECTED),
.ENET1_EXT_INTIN(1'b0),
.ENET1_GMII_COL(1'b0),
.ENET1_GMII_CRS(1'b0),
.ENET1_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET1_GMII_RX_CLK(1'b0),
.ENET1_GMII_RX_DV(1'b0),
.ENET1_GMII_RX_ER(1'b0),
.ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]),
.ENET1_GMII_TX_CLK(1'b0),
.ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED),
.ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED),
.ENET1_MDIO_I(1'b0),
.ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED),
.ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED),
.ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED),
.ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED),
.EVENT_EVENTI(1'b0),
.EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED),
.EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]),
.EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(FCLK_CLK1),
.FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED),
.FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED),
.FCLK_CLKTRIG0_N(1'b0),
.FCLK_CLKTRIG1_N(1'b0),
.FCLK_CLKTRIG2_N(1'b0),
.FCLK_CLKTRIG3_N(1'b0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED),
.FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED),
.FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED),
.FPGA_IDLE_N(1'b0),
.FTMD_TRACEIN_ATID({1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_CLK(1'b0),
.FTMD_TRACEIN_DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_VALID(1'b0),
.FTMT_F2P_DEBUG({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMT_F2P_TRIGACK_0(NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED),
.FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED),
.FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED),
.FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED),
.FTMT_F2P_TRIG_0(1'b0),
.FTMT_F2P_TRIG_1(1'b0),
.FTMT_F2P_TRIG_2(1'b0),
.FTMT_F2P_TRIG_3(1'b0),
.FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]),
.FTMT_P2F_TRIGACK_0(1'b0),
.FTMT_P2F_TRIGACK_1(1'b0),
.FTMT_P2F_TRIGACK_2(1'b0),
.FTMT_P2F_TRIGACK_3(1'b0),
.FTMT_P2F_TRIG_0(NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED),
.FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED),
.FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED),
.FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED),
.GPIO_I({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.GPIO_O(NLW_inst_GPIO_O_UNCONNECTED[63:0]),
.GPIO_T(NLW_inst_GPIO_T_UNCONNECTED[63:0]),
.I2C0_SCL_I(I2C0_SCL_I),
.I2C0_SCL_O(I2C0_SCL_O),
.I2C0_SCL_T(I2C0_SCL_T),
.I2C0_SDA_I(I2C0_SDA_I),
.I2C0_SDA_O(I2C0_SDA_O),
.I2C0_SDA_T(I2C0_SDA_T),
.I2C1_SCL_I(1'b0),
.I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED),
.I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED),
.I2C1_SDA_I(1'b0),
.I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED),
.I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED),
.IRQ_F2P(1'b0),
.IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED),
.IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED),
.IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED),
.IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED),
.IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED),
.IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED),
.IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED),
.IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED),
.IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED),
.IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED),
.IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED),
.IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED),
.IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED),
.IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED),
.IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED),
.IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED),
.IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED),
.IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED),
.IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED),
.IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED),
.IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED),
.IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED),
.IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED),
.IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED),
.IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED),
.IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED),
.IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED),
.IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED),
.IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED),
.MIO(MIO),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP1_ACLK(1'b0),
.M_AXI_GP1_ARADDR(NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_ARBURST(NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_ARCACHE(NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED),
.M_AXI_GP1_ARID(NLW_inst_M_AXI_GP1_ARID_UNCONNECTED[11:0]),
.M_AXI_GP1_ARLEN(NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_ARLOCK(NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_ARPROT(NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_ARQOS(NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_ARREADY(1'b0),
.M_AXI_GP1_ARSIZE(NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_ARVALID(NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED),
.M_AXI_GP1_AWADDR(NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_AWBURST(NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_AWCACHE(NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_AWID(NLW_inst_M_AXI_GP1_AWID_UNCONNECTED[11:0]),
.M_AXI_GP1_AWLEN(NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_AWLOCK(NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_AWPROT(NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_AWQOS(NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_AWREADY(1'b0),
.M_AXI_GP1_AWSIZE(NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_AWVALID(NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED),
.M_AXI_GP1_BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_BREADY(NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED),
.M_AXI_GP1_BRESP({1'b0,1'b0}),
.M_AXI_GP1_BVALID(1'b0),
.M_AXI_GP1_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RLAST(1'b0),
.M_AXI_GP1_RREADY(NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED),
.M_AXI_GP1_RRESP({1'b0,1'b0}),
.M_AXI_GP1_RVALID(1'b0),
.M_AXI_GP1_WDATA(NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED[31:0]),
.M_AXI_GP1_WID(NLW_inst_M_AXI_GP1_WID_UNCONNECTED[11:0]),
.M_AXI_GP1_WLAST(NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED),
.M_AXI_GP1_WREADY(1'b0),
.M_AXI_GP1_WSTRB(NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED[3:0]),
.M_AXI_GP1_WVALID(NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED),
.PJTAG_TCK(1'b0),
.PJTAG_TDI(1'b0),
.PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED),
.PJTAG_TMS(1'b0),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB),
.PS_SRSTB(PS_SRSTB),
.SDIO0_BUSPOW(NLW_inst_SDIO0_BUSPOW_UNCONNECTED),
.SDIO0_BUSVOLT(NLW_inst_SDIO0_BUSVOLT_UNCONNECTED[2:0]),
.SDIO0_CDN(1'b0),
.SDIO0_CLK(NLW_inst_SDIO0_CLK_UNCONNECTED),
.SDIO0_CLK_FB(1'b0),
.SDIO0_CMD_I(1'b0),
.SDIO0_CMD_O(NLW_inst_SDIO0_CMD_O_UNCONNECTED),
.SDIO0_CMD_T(NLW_inst_SDIO0_CMD_T_UNCONNECTED),
.SDIO0_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO0_DATA_O(NLW_inst_SDIO0_DATA_O_UNCONNECTED[3:0]),
.SDIO0_DATA_T(NLW_inst_SDIO0_DATA_T_UNCONNECTED[3:0]),
.SDIO0_LED(NLW_inst_SDIO0_LED_UNCONNECTED),
.SDIO0_WP(1'b0),
.SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED),
.SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]),
.SDIO1_CDN(1'b0),
.SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED),
.SDIO1_CLK_FB(1'b0),
.SDIO1_CMD_I(1'b0),
.SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED),
.SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED),
.SDIO1_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]),
.SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]),
.SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED),
.SDIO1_WP(1'b0),
.SPI0_MISO_I(1'b0),
.SPI0_MISO_O(NLW_inst_SPI0_MISO_O_UNCONNECTED),
.SPI0_MISO_T(NLW_inst_SPI0_MISO_T_UNCONNECTED),
.SPI0_MOSI_I(1'b0),
.SPI0_MOSI_O(NLW_inst_SPI0_MOSI_O_UNCONNECTED),
.SPI0_MOSI_T(NLW_inst_SPI0_MOSI_T_UNCONNECTED),
.SPI0_SCLK_I(1'b0),
.SPI0_SCLK_O(NLW_inst_SPI0_SCLK_O_UNCONNECTED),
.SPI0_SCLK_T(NLW_inst_SPI0_SCLK_T_UNCONNECTED),
.SPI0_SS1_O(NLW_inst_SPI0_SS1_O_UNCONNECTED),
.SPI0_SS2_O(NLW_inst_SPI0_SS2_O_UNCONNECTED),
.SPI0_SS_I(1'b0),
.SPI0_SS_O(NLW_inst_SPI0_SS_O_UNCONNECTED),
.SPI0_SS_T(NLW_inst_SPI0_SS_T_UNCONNECTED),
.SPI1_MISO_I(1'b0),
.SPI1_MISO_O(NLW_inst_SPI1_MISO_O_UNCONNECTED),
.SPI1_MISO_T(NLW_inst_SPI1_MISO_T_UNCONNECTED),
.SPI1_MOSI_I(1'b0),
.SPI1_MOSI_O(NLW_inst_SPI1_MOSI_O_UNCONNECTED),
.SPI1_MOSI_T(NLW_inst_SPI1_MOSI_T_UNCONNECTED),
.SPI1_SCLK_I(1'b0),
.SPI1_SCLK_O(NLW_inst_SPI1_SCLK_O_UNCONNECTED),
.SPI1_SCLK_T(NLW_inst_SPI1_SCLK_T_UNCONNECTED),
.SPI1_SS1_O(NLW_inst_SPI1_SS1_O_UNCONNECTED),
.SPI1_SS2_O(NLW_inst_SPI1_SS2_O_UNCONNECTED),
.SPI1_SS_I(1'b0),
.SPI1_SS_O(NLW_inst_SPI1_SS_O_UNCONNECTED),
.SPI1_SS_T(NLW_inst_SPI1_SS_T_UNCONNECTED),
.SRAM_INTIN(1'b0),
.S_AXI_ACP_ACLK(1'b0),
.S_AXI_ACP_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARBURST({1'b0,1'b0}),
.S_AXI_ACP_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED),
.S_AXI_ACP_ARID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLOCK({1'b0,1'b0}),
.S_AXI_ACP_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED),
.S_AXI_ACP_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARVALID(1'b0),
.S_AXI_ACP_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWBURST({1'b0,1'b0}),
.S_AXI_ACP_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLOCK({1'b0,1'b0}),
.S_AXI_ACP_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED),
.S_AXI_ACP_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWVALID(1'b0),
.S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]),
.S_AXI_ACP_BREADY(1'b0),
.S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED),
.S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]),
.S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]),
.S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED),
.S_AXI_ACP_RREADY(1'b0),
.S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED),
.S_AXI_ACP_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_WLAST(1'b0),
.S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED),
.S_AXI_ACP_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WVALID(1'b0),
.S_AXI_GP0_ACLK(1'b0),
.S_AXI_GP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARBURST({1'b0,1'b0}),
.S_AXI_GP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED),
.S_AXI_GP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLOCK({1'b0,1'b0}),
.S_AXI_GP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED),
.S_AXI_GP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARVALID(1'b0),
.S_AXI_GP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWBURST({1'b0,1'b0}),
.S_AXI_GP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLOCK({1'b0,1'b0}),
.S_AXI_GP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED),
.S_AXI_GP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWVALID(1'b0),
.S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]),
.S_AXI_GP0_BREADY(1'b0),
.S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED),
.S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]),
.S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED),
.S_AXI_GP0_RREADY(1'b0),
.S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED),
.S_AXI_GP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WLAST(1'b0),
.S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED),
.S_AXI_GP0_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WVALID(1'b0),
.S_AXI_GP1_ACLK(1'b0),
.S_AXI_GP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARBURST({1'b0,1'b0}),
.S_AXI_GP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED),
.S_AXI_GP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLOCK({1'b0,1'b0}),
.S_AXI_GP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED),
.S_AXI_GP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARVALID(1'b0),
.S_AXI_GP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWBURST({1'b0,1'b0}),
.S_AXI_GP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLOCK({1'b0,1'b0}),
.S_AXI_GP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED),
.S_AXI_GP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWVALID(1'b0),
.S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]),
.S_AXI_GP1_BREADY(1'b0),
.S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED),
.S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]),
.S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED),
.S_AXI_GP1_RREADY(1'b0),
.S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED),
.S_AXI_GP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WLAST(1'b0),
.S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED),
.S_AXI_GP1_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WVALID(1'b0),
.S_AXI_HP0_ACLK(1'b0),
.S_AXI_HP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARBURST({1'b0,1'b0}),
.S_AXI_HP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED),
.S_AXI_HP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLOCK({1'b0,1'b0}),
.S_AXI_HP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARREADY(NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED),
.S_AXI_HP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARVALID(1'b0),
.S_AXI_HP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWBURST({1'b0,1'b0}),
.S_AXI_HP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLOCK({1'b0,1'b0}),
.S_AXI_HP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWREADY(NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED),
.S_AXI_HP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWVALID(1'b0),
.S_AXI_HP0_BID(NLW_inst_S_AXI_HP0_BID_UNCONNECTED[5:0]),
.S_AXI_HP0_BREADY(1'b0),
.S_AXI_HP0_BRESP(NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_BVALID(NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED),
.S_AXI_HP0_RACOUNT(NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP0_RCOUNT(NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_RDATA(NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP0_RDISSUECAP1_EN(1'b0),
.S_AXI_HP0_RID(NLW_inst_S_AXI_HP0_RID_UNCONNECTED[5:0]),
.S_AXI_HP0_RLAST(NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED),
.S_AXI_HP0_RREADY(1'b0),
.S_AXI_HP0_RRESP(NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_RVALID(NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED),
.S_AXI_HP0_WACOUNT(NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP0_WCOUNT(NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WLAST(1'b0),
.S_AXI_HP0_WREADY(NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED),
.S_AXI_HP0_WRISSUECAP1_EN(1'b0),
.S_AXI_HP0_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WVALID(1'b0),
.S_AXI_HP1_ACLK(1'b0),
.S_AXI_HP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARBURST({1'b0,1'b0}),
.S_AXI_HP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED),
.S_AXI_HP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLOCK({1'b0,1'b0}),
.S_AXI_HP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARREADY(NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED),
.S_AXI_HP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARVALID(1'b0),
.S_AXI_HP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWBURST({1'b0,1'b0}),
.S_AXI_HP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLOCK({1'b0,1'b0}),
.S_AXI_HP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWREADY(NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED),
.S_AXI_HP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWVALID(1'b0),
.S_AXI_HP1_BID(NLW_inst_S_AXI_HP1_BID_UNCONNECTED[5:0]),
.S_AXI_HP1_BREADY(1'b0),
.S_AXI_HP1_BRESP(NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_BVALID(NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED),
.S_AXI_HP1_RACOUNT(NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP1_RCOUNT(NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_RDATA(NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP1_RDISSUECAP1_EN(1'b0),
.S_AXI_HP1_RID(NLW_inst_S_AXI_HP1_RID_UNCONNECTED[5:0]),
.S_AXI_HP1_RLAST(NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED),
.S_AXI_HP1_RREADY(1'b0),
.S_AXI_HP1_RRESP(NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_RVALID(NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED),
.S_AXI_HP1_WACOUNT(NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP1_WCOUNT(NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WLAST(1'b0),
.S_AXI_HP1_WREADY(NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED),
.S_AXI_HP1_WRISSUECAP1_EN(1'b0),
.S_AXI_HP1_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WVALID(1'b0),
.S_AXI_HP2_ACLK(1'b0),
.S_AXI_HP2_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARBURST({1'b0,1'b0}),
.S_AXI_HP2_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED),
.S_AXI_HP2_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLOCK({1'b0,1'b0}),
.S_AXI_HP2_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED),
.S_AXI_HP2_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARVALID(1'b0),
.S_AXI_HP2_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWBURST({1'b0,1'b0}),
.S_AXI_HP2_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLOCK({1'b0,1'b0}),
.S_AXI_HP2_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED),
.S_AXI_HP2_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWVALID(1'b0),
.S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]),
.S_AXI_HP2_BREADY(1'b0),
.S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED),
.S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP2_RDISSUECAP1_EN(1'b0),
.S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]),
.S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED),
.S_AXI_HP2_RREADY(1'b0),
.S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED),
.S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WLAST(1'b0),
.S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED),
.S_AXI_HP2_WRISSUECAP1_EN(1'b0),
.S_AXI_HP2_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WVALID(1'b0),
.S_AXI_HP3_ACLK(1'b0),
.S_AXI_HP3_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARBURST({1'b0,1'b0}),
.S_AXI_HP3_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED),
.S_AXI_HP3_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLOCK({1'b0,1'b0}),
.S_AXI_HP3_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED),
.S_AXI_HP3_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARVALID(1'b0),
.S_AXI_HP3_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWBURST({1'b0,1'b0}),
.S_AXI_HP3_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLOCK({1'b0,1'b0}),
.S_AXI_HP3_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED),
.S_AXI_HP3_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWVALID(1'b0),
.S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]),
.S_AXI_HP3_BREADY(1'b0),
.S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED),
.S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP3_RDISSUECAP1_EN(1'b0),
.S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]),
.S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED),
.S_AXI_HP3_RREADY(1'b0),
.S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED),
.S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WLAST(1'b0),
.S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED),
.S_AXI_HP3_WRISSUECAP1_EN(1'b0),
.S_AXI_HP3_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WVALID(1'b0),
.TRACE_CLK(1'b0),
.TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED),
.TRACE_CTL(NLW_inst_TRACE_CTL_UNCONNECTED),
.TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]),
.TTC0_CLK0_IN(1'b0),
.TTC0_CLK1_IN(1'b0),
.TTC0_CLK2_IN(1'b0),
.TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
.TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
.TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
.TTC1_CLK0_IN(1'b0),
.TTC1_CLK1_IN(1'b0),
.TTC1_CLK2_IN(1'b0),
.TTC1_WAVE0_OUT(NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED),
.TTC1_WAVE1_OUT(NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED),
.TTC1_WAVE2_OUT(NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED),
.UART0_CTSN(1'b0),
.UART0_DCDN(1'b0),
.UART0_DSRN(1'b0),
.UART0_DTRN(NLW_inst_UART0_DTRN_UNCONNECTED),
.UART0_RIN(1'b0),
.UART0_RTSN(NLW_inst_UART0_RTSN_UNCONNECTED),
.UART0_RX(1'b1),
.UART0_TX(NLW_inst_UART0_TX_UNCONNECTED),
.UART1_CTSN(1'b0),
.UART1_DCDN(1'b0),
.UART1_DSRN(1'b0),
.UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED),
.UART1_RIN(1'b0),
.UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED),
.UART1_RX(1'b1),
.UART1_TX(NLW_inst_UART1_TX_UNCONNECTED),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB1_PORT_INDCTL(NLW_inst_USB1_PORT_INDCTL_UNCONNECTED[1:0]),
.USB1_VBUS_PWRFAULT(1'b0),
.USB1_VBUS_PWRSELECT(NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED),
.WDT_CLK_IN(1'b0),
.WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED));
endmodule
(* C_DM_WIDTH = "4" *) (* C_DQS_WIDTH = "4" *) (* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *) (* C_EN_EMIO_ENET0 = "0" *) (* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *) (* C_EN_EMIO_TRACE = "0" *) (* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "TRUE" *) (* C_FCLK_CLK2_BUF = "FALSE" *) (* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "1" *) (* C_GP1_EN_MODIFIABLE_TXN = "1" *) (* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *) (* C_IRQ_F2P_MODE = "DIRECT" *) (* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP0_ID_WIDTH = "12" *) (* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP1_ID_WIDTH = "12" *) (* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *) (* C_PACKAGE_NAME = "clg484" *) (* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *) (* C_S_AXI_ACP_AWUSER_VAL = "31" *) (* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *) (* C_S_AXI_GP1_ID_WIDTH = "6" *) (* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *) (* C_S_AXI_HP1_DATA_WIDTH = "64" *) (* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *) (* C_S_AXI_HP2_ID_WIDTH = "6" *) (* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *) (* C_TRACE_BUFFER_CLOCK_DELAY = "12" *) (* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *) (* C_TRACE_PIPELINE_WIDTH = "8" *) (* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *) (* C_USE_M_AXI_GP0 = "1" *) (* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *) (* C_USE_S_AXI_GP0 = "0" *) (* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *) (* C_USE_S_AXI_HP1 = "0" *) (* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *) (* HW_HANDOFF = "ip_design_processing_system7_0_0.hwdef" *) (* ORIG_REF_NAME = "processing_system7_v5_5_processing_system7" *)
(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={I2C} ioStandard={} bidis={1} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *) (* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
module ip_design_processing_system7_0_0_processing_system7_v5_5_processing_system7
(CAN0_PHY_TX,
CAN0_PHY_RX,
CAN1_PHY_TX,
CAN1_PHY_RX,
ENET0_GMII_TX_EN,
ENET0_GMII_TX_ER,
ENET0_MDIO_MDC,
ENET0_MDIO_O,
ENET0_MDIO_T,
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
ENET0_GMII_TXD,
ENET0_GMII_COL,
ENET0_GMII_CRS,
ENET0_GMII_RX_CLK,
ENET0_GMII_RX_DV,
ENET0_GMII_RX_ER,
ENET0_GMII_TX_CLK,
ENET0_MDIO_I,
ENET0_EXT_INTIN,
ENET0_GMII_RXD,
ENET1_GMII_TX_EN,
ENET1_GMII_TX_ER,
ENET1_MDIO_MDC,
ENET1_MDIO_O,
ENET1_MDIO_T,
ENET1_PTP_DELAY_REQ_RX,
ENET1_PTP_DELAY_REQ_TX,
ENET1_PTP_PDELAY_REQ_RX,
ENET1_PTP_PDELAY_REQ_TX,
ENET1_PTP_PDELAY_RESP_RX,
ENET1_PTP_PDELAY_RESP_TX,
ENET1_PTP_SYNC_FRAME_RX,
ENET1_PTP_SYNC_FRAME_TX,
ENET1_SOF_RX,
ENET1_SOF_TX,
ENET1_GMII_TXD,
ENET1_GMII_COL,
ENET1_GMII_CRS,
ENET1_GMII_RX_CLK,
ENET1_GMII_RX_DV,
ENET1_GMII_RX_ER,
ENET1_GMII_TX_CLK,
ENET1_MDIO_I,
ENET1_EXT_INTIN,
ENET1_GMII_RXD,
GPIO_I,
GPIO_O,
GPIO_T,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
I2C1_SDA_I,
I2C1_SDA_O,
I2C1_SDA_T,
I2C1_SCL_I,
I2C1_SCL_O,
I2C1_SCL_T,
PJTAG_TCK,
PJTAG_TMS,
PJTAG_TDI,
PJTAG_TDO,
SDIO0_CLK,
SDIO0_CLK_FB,
SDIO0_CMD_O,
SDIO0_CMD_I,
SDIO0_CMD_T,
SDIO0_DATA_I,
SDIO0_DATA_O,
SDIO0_DATA_T,
SDIO0_LED,
SDIO0_CDN,
SDIO0_WP,
SDIO0_BUSPOW,
SDIO0_BUSVOLT,
SDIO1_CLK,
SDIO1_CLK_FB,
SDIO1_CMD_O,
SDIO1_CMD_I,
SDIO1_CMD_T,
SDIO1_DATA_I,
SDIO1_DATA_O,
SDIO1_DATA_T,
SDIO1_LED,
SDIO1_CDN,
SDIO1_WP,
SDIO1_BUSPOW,
SDIO1_BUSVOLT,
SPI0_SCLK_I,
SPI0_SCLK_O,
SPI0_SCLK_T,
SPI0_MOSI_I,
SPI0_MOSI_O,
SPI0_MOSI_T,
SPI0_MISO_I,
SPI0_MISO_O,
SPI0_MISO_T,
SPI0_SS_I,
SPI0_SS_O,
SPI0_SS1_O,
SPI0_SS2_O,
SPI0_SS_T,
SPI1_SCLK_I,
SPI1_SCLK_O,
SPI1_SCLK_T,
SPI1_MOSI_I,
SPI1_MOSI_O,
SPI1_MOSI_T,
SPI1_MISO_I,
SPI1_MISO_O,
SPI1_MISO_T,
SPI1_SS_I,
SPI1_SS_O,
SPI1_SS1_O,
SPI1_SS2_O,
SPI1_SS_T,
UART0_DTRN,
UART0_RTSN,
UART0_TX,
UART0_CTSN,
UART0_DCDN,
UART0_DSRN,
UART0_RIN,
UART0_RX,
UART1_DTRN,
UART1_RTSN,
UART1_TX,
UART1_CTSN,
UART1_DCDN,
UART1_DSRN,
UART1_RIN,
UART1_RX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
TTC0_CLK0_IN,
TTC0_CLK1_IN,
TTC0_CLK2_IN,
TTC1_WAVE0_OUT,
TTC1_WAVE1_OUT,
TTC1_WAVE2_OUT,
TTC1_CLK0_IN,
TTC1_CLK1_IN,
TTC1_CLK2_IN,
WDT_CLK_IN,
WDT_RST_OUT,
TRACE_CLK,
TRACE_CTL,
TRACE_DATA,
TRACE_CLK_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
USB1_PORT_INDCTL,
USB1_VBUS_PWRSELECT,
USB1_VBUS_PWRFAULT,
SRAM_INTIN,
M_AXI_GP0_ARESETN,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
M_AXI_GP1_ARESETN,
M_AXI_GP1_ARVALID,
M_AXI_GP1_AWVALID,
M_AXI_GP1_BREADY,
M_AXI_GP1_RREADY,
M_AXI_GP1_WLAST,
M_AXI_GP1_WVALID,
M_AXI_GP1_ARID,
M_AXI_GP1_AWID,
M_AXI_GP1_WID,
M_AXI_GP1_ARBURST,
M_AXI_GP1_ARLOCK,
M_AXI_GP1_ARSIZE,
M_AXI_GP1_AWBURST,
M_AXI_GP1_AWLOCK,
M_AXI_GP1_AWSIZE,
M_AXI_GP1_ARPROT,
M_AXI_GP1_AWPROT,
M_AXI_GP1_ARADDR,
M_AXI_GP1_AWADDR,
M_AXI_GP1_WDATA,
M_AXI_GP1_ARCACHE,
M_AXI_GP1_ARLEN,
M_AXI_GP1_ARQOS,
M_AXI_GP1_AWCACHE,
M_AXI_GP1_AWLEN,
M_AXI_GP1_AWQOS,
M_AXI_GP1_WSTRB,
M_AXI_GP1_ACLK,
M_AXI_GP1_ARREADY,
M_AXI_GP1_AWREADY,
M_AXI_GP1_BVALID,
M_AXI_GP1_RLAST,
M_AXI_GP1_RVALID,
M_AXI_GP1_WREADY,
M_AXI_GP1_BID,
M_AXI_GP1_RID,
M_AXI_GP1_BRESP,
M_AXI_GP1_RRESP,
M_AXI_GP1_RDATA,
S_AXI_GP0_ARESETN,
S_AXI_GP0_ARREADY,
S_AXI_GP0_AWREADY,
S_AXI_GP0_BVALID,
S_AXI_GP0_RLAST,
S_AXI_GP0_RVALID,
S_AXI_GP0_WREADY,
S_AXI_GP0_BRESP,
S_AXI_GP0_RRESP,
S_AXI_GP0_RDATA,
S_AXI_GP0_BID,
S_AXI_GP0_RID,
S_AXI_GP0_ACLK,
S_AXI_GP0_ARVALID,
S_AXI_GP0_AWVALID,
S_AXI_GP0_BREADY,
S_AXI_GP0_RREADY,
S_AXI_GP0_WLAST,
S_AXI_GP0_WVALID,
S_AXI_GP0_ARBURST,
S_AXI_GP0_ARLOCK,
S_AXI_GP0_ARSIZE,
S_AXI_GP0_AWBURST,
S_AXI_GP0_AWLOCK,
S_AXI_GP0_AWSIZE,
S_AXI_GP0_ARPROT,
S_AXI_GP0_AWPROT,
S_AXI_GP0_ARADDR,
S_AXI_GP0_AWADDR,
S_AXI_GP0_WDATA,
S_AXI_GP0_ARCACHE,
S_AXI_GP0_ARLEN,
S_AXI_GP0_ARQOS,
S_AXI_GP0_AWCACHE,
S_AXI_GP0_AWLEN,
S_AXI_GP0_AWQOS,
S_AXI_GP0_WSTRB,
S_AXI_GP0_ARID,
S_AXI_GP0_AWID,
S_AXI_GP0_WID,
S_AXI_GP1_ARESETN,
S_AXI_GP1_ARREADY,
S_AXI_GP1_AWREADY,
S_AXI_GP1_BVALID,
S_AXI_GP1_RLAST,
S_AXI_GP1_RVALID,
S_AXI_GP1_WREADY,
S_AXI_GP1_BRESP,
S_AXI_GP1_RRESP,
S_AXI_GP1_RDATA,
S_AXI_GP1_BID,
S_AXI_GP1_RID,
S_AXI_GP1_ACLK,
S_AXI_GP1_ARVALID,
S_AXI_GP1_AWVALID,
S_AXI_GP1_BREADY,
S_AXI_GP1_RREADY,
S_AXI_GP1_WLAST,
S_AXI_GP1_WVALID,
S_AXI_GP1_ARBURST,
S_AXI_GP1_ARLOCK,
S_AXI_GP1_ARSIZE,
S_AXI_GP1_AWBURST,
S_AXI_GP1_AWLOCK,
S_AXI_GP1_AWSIZE,
S_AXI_GP1_ARPROT,
S_AXI_GP1_AWPROT,
S_AXI_GP1_ARADDR,
S_AXI_GP1_AWADDR,
S_AXI_GP1_WDATA,
S_AXI_GP1_ARCACHE,
S_AXI_GP1_ARLEN,
S_AXI_GP1_ARQOS,
S_AXI_GP1_AWCACHE,
S_AXI_GP1_AWLEN,
S_AXI_GP1_AWQOS,
S_AXI_GP1_WSTRB,
S_AXI_GP1_ARID,
S_AXI_GP1_AWID,
S_AXI_GP1_WID,
S_AXI_ACP_ARESETN,
S_AXI_ACP_ARREADY,
S_AXI_ACP_AWREADY,
S_AXI_ACP_BVALID,
S_AXI_ACP_RLAST,
S_AXI_ACP_RVALID,
S_AXI_ACP_WREADY,
S_AXI_ACP_BRESP,
S_AXI_ACP_RRESP,
S_AXI_ACP_BID,
S_AXI_ACP_RID,
S_AXI_ACP_RDATA,
S_AXI_ACP_ACLK,
S_AXI_ACP_ARVALID,
S_AXI_ACP_AWVALID,
S_AXI_ACP_BREADY,
S_AXI_ACP_RREADY,
S_AXI_ACP_WLAST,
S_AXI_ACP_WVALID,
S_AXI_ACP_ARID,
S_AXI_ACP_ARPROT,
S_AXI_ACP_AWID,
S_AXI_ACP_AWPROT,
S_AXI_ACP_WID,
S_AXI_ACP_ARADDR,
S_AXI_ACP_AWADDR,
S_AXI_ACP_ARCACHE,
S_AXI_ACP_ARLEN,
S_AXI_ACP_ARQOS,
S_AXI_ACP_AWCACHE,
S_AXI_ACP_AWLEN,
S_AXI_ACP_AWQOS,
S_AXI_ACP_ARBURST,
S_AXI_ACP_ARLOCK,
S_AXI_ACP_ARSIZE,
S_AXI_ACP_AWBURST,
S_AXI_ACP_AWLOCK,
S_AXI_ACP_AWSIZE,
S_AXI_ACP_ARUSER,
S_AXI_ACP_AWUSER,
S_AXI_ACP_WDATA,
S_AXI_ACP_WSTRB,
S_AXI_HP0_ARESETN,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
S_AXI_HP1_ARESETN,
S_AXI_HP1_ARREADY,
S_AXI_HP1_AWREADY,
S_AXI_HP1_BVALID,
S_AXI_HP1_RLAST,
S_AXI_HP1_RVALID,
S_AXI_HP1_WREADY,
S_AXI_HP1_BRESP,
S_AXI_HP1_RRESP,
S_AXI_HP1_BID,
S_AXI_HP1_RID,
S_AXI_HP1_RDATA,
S_AXI_HP1_RCOUNT,
S_AXI_HP1_WCOUNT,
S_AXI_HP1_RACOUNT,
S_AXI_HP1_WACOUNT,
S_AXI_HP1_ACLK,
S_AXI_HP1_ARVALID,
S_AXI_HP1_AWVALID,
S_AXI_HP1_BREADY,
S_AXI_HP1_RDISSUECAP1_EN,
S_AXI_HP1_RREADY,
S_AXI_HP1_WLAST,
S_AXI_HP1_WRISSUECAP1_EN,
S_AXI_HP1_WVALID,
S_AXI_HP1_ARBURST,
S_AXI_HP1_ARLOCK,
S_AXI_HP1_ARSIZE,
S_AXI_HP1_AWBURST,
S_AXI_HP1_AWLOCK,
S_AXI_HP1_AWSIZE,
S_AXI_HP1_ARPROT,
S_AXI_HP1_AWPROT,
S_AXI_HP1_ARADDR,
S_AXI_HP1_AWADDR,
S_AXI_HP1_ARCACHE,
S_AXI_HP1_ARLEN,
S_AXI_HP1_ARQOS,
S_AXI_HP1_AWCACHE,
S_AXI_HP1_AWLEN,
S_AXI_HP1_AWQOS,
S_AXI_HP1_ARID,
S_AXI_HP1_AWID,
S_AXI_HP1_WID,
S_AXI_HP1_WDATA,
S_AXI_HP1_WSTRB,
S_AXI_HP2_ARESETN,
S_AXI_HP2_ARREADY,
S_AXI_HP2_AWREADY,
S_AXI_HP2_BVALID,
S_AXI_HP2_RLAST,
S_AXI_HP2_RVALID,
S_AXI_HP2_WREADY,
S_AXI_HP2_BRESP,
S_AXI_HP2_RRESP,
S_AXI_HP2_BID,
S_AXI_HP2_RID,
S_AXI_HP2_RDATA,
S_AXI_HP2_RCOUNT,
S_AXI_HP2_WCOUNT,
S_AXI_HP2_RACOUNT,
S_AXI_HP2_WACOUNT,
S_AXI_HP2_ACLK,
S_AXI_HP2_ARVALID,
S_AXI_HP2_AWVALID,
S_AXI_HP2_BREADY,
S_AXI_HP2_RDISSUECAP1_EN,
S_AXI_HP2_RREADY,
S_AXI_HP2_WLAST,
S_AXI_HP2_WRISSUECAP1_EN,
S_AXI_HP2_WVALID,
S_AXI_HP2_ARBURST,
S_AXI_HP2_ARLOCK,
S_AXI_HP2_ARSIZE,
S_AXI_HP2_AWBURST,
S_AXI_HP2_AWLOCK,
S_AXI_HP2_AWSIZE,
S_AXI_HP2_ARPROT,
S_AXI_HP2_AWPROT,
S_AXI_HP2_ARADDR,
S_AXI_HP2_AWADDR,
S_AXI_HP2_ARCACHE,
S_AXI_HP2_ARLEN,
S_AXI_HP2_ARQOS,
S_AXI_HP2_AWCACHE,
S_AXI_HP2_AWLEN,
S_AXI_HP2_AWQOS,
S_AXI_HP2_ARID,
S_AXI_HP2_AWID,
S_AXI_HP2_WID,
S_AXI_HP2_WDATA,
S_AXI_HP2_WSTRB,
S_AXI_HP3_ARESETN,
S_AXI_HP3_ARREADY,
S_AXI_HP3_AWREADY,
S_AXI_HP3_BVALID,
S_AXI_HP3_RLAST,
S_AXI_HP3_RVALID,
S_AXI_HP3_WREADY,
S_AXI_HP3_BRESP,
S_AXI_HP3_RRESP,
S_AXI_HP3_BID,
S_AXI_HP3_RID,
S_AXI_HP3_RDATA,
S_AXI_HP3_RCOUNT,
S_AXI_HP3_WCOUNT,
S_AXI_HP3_RACOUNT,
S_AXI_HP3_WACOUNT,
S_AXI_HP3_ACLK,
S_AXI_HP3_ARVALID,
S_AXI_HP3_AWVALID,
S_AXI_HP3_BREADY,
S_AXI_HP3_RDISSUECAP1_EN,
S_AXI_HP3_RREADY,
S_AXI_HP3_WLAST,
S_AXI_HP3_WRISSUECAP1_EN,
S_AXI_HP3_WVALID,
S_AXI_HP3_ARBURST,
S_AXI_HP3_ARLOCK,
S_AXI_HP3_ARSIZE,
S_AXI_HP3_AWBURST,
S_AXI_HP3_AWLOCK,
S_AXI_HP3_AWSIZE,
S_AXI_HP3_ARPROT,
S_AXI_HP3_AWPROT,
S_AXI_HP3_ARADDR,
S_AXI_HP3_AWADDR,
S_AXI_HP3_ARCACHE,
S_AXI_HP3_ARLEN,
S_AXI_HP3_ARQOS,
S_AXI_HP3_AWCACHE,
S_AXI_HP3_AWLEN,
S_AXI_HP3_AWQOS,
S_AXI_HP3_ARID,
S_AXI_HP3_AWID,
S_AXI_HP3_WID,
S_AXI_HP3_WDATA,
S_AXI_HP3_WSTRB,
IRQ_P2F_DMAC_ABORT,
IRQ_P2F_DMAC0,
IRQ_P2F_DMAC1,
IRQ_P2F_DMAC2,
IRQ_P2F_DMAC3,
IRQ_P2F_DMAC4,
IRQ_P2F_DMAC5,
IRQ_P2F_DMAC6,
IRQ_P2F_DMAC7,
IRQ_P2F_SMC,
IRQ_P2F_QSPI,
IRQ_P2F_CTI,
IRQ_P2F_GPIO,
IRQ_P2F_USB0,
IRQ_P2F_ENET0,
IRQ_P2F_ENET_WAKE0,
IRQ_P2F_SDIO0,
IRQ_P2F_I2C0,
IRQ_P2F_SPI0,
IRQ_P2F_UART0,
IRQ_P2F_CAN0,
IRQ_P2F_USB1,
IRQ_P2F_ENET1,
IRQ_P2F_ENET_WAKE1,
IRQ_P2F_SDIO1,
IRQ_P2F_I2C1,
IRQ_P2F_SPI1,
IRQ_P2F_UART1,
IRQ_P2F_CAN1,
IRQ_F2P,
Core0_nFIQ,
Core0_nIRQ,
Core1_nFIQ,
Core1_nIRQ,
DMA0_DATYPE,
DMA0_DAVALID,
DMA0_DRREADY,
DMA0_RSTN,
DMA1_DATYPE,
DMA1_DAVALID,
DMA1_DRREADY,
DMA1_RSTN,
DMA2_DATYPE,
DMA2_DAVALID,
DMA2_DRREADY,
DMA2_RSTN,
DMA3_DATYPE,
DMA3_DAVALID,
DMA3_DRREADY,
DMA3_RSTN,
DMA0_ACLK,
DMA0_DAREADY,
DMA0_DRLAST,
DMA0_DRVALID,
DMA1_ACLK,
DMA1_DAREADY,
DMA1_DRLAST,
DMA1_DRVALID,
DMA2_ACLK,
DMA2_DAREADY,
DMA2_DRLAST,
DMA2_DRVALID,
DMA3_ACLK,
DMA3_DAREADY,
DMA3_DRLAST,
DMA3_DRVALID,
DMA0_DRTYPE,
DMA1_DRTYPE,
DMA2_DRTYPE,
DMA3_DRTYPE,
FCLK_CLK3,
FCLK_CLK2,
FCLK_CLK1,
FCLK_CLK0,
FCLK_CLKTRIG3_N,
FCLK_CLKTRIG2_N,
FCLK_CLKTRIG1_N,
FCLK_CLKTRIG0_N,
FCLK_RESET3_N,
FCLK_RESET2_N,
FCLK_RESET1_N,
FCLK_RESET0_N,
FTMD_TRACEIN_DATA,
FTMD_TRACEIN_VALID,
FTMD_TRACEIN_CLK,
FTMD_TRACEIN_ATID,
FTMT_F2P_TRIG_0,
FTMT_F2P_TRIGACK_0,
FTMT_F2P_TRIG_1,
FTMT_F2P_TRIGACK_1,
FTMT_F2P_TRIG_2,
FTMT_F2P_TRIGACK_2,
FTMT_F2P_TRIG_3,
FTMT_F2P_TRIGACK_3,
FTMT_F2P_DEBUG,
FTMT_P2F_TRIGACK_0,
FTMT_P2F_TRIG_0,
FTMT_P2F_TRIGACK_1,
FTMT_P2F_TRIG_1,
FTMT_P2F_TRIGACK_2,
FTMT_P2F_TRIG_2,
FTMT_P2F_TRIGACK_3,
FTMT_P2F_TRIG_3,
FTMT_P2F_DEBUG,
FPGA_IDLE_N,
EVENT_EVENTO,
EVENT_STANDBYWFE,
EVENT_STANDBYWFI,
EVENT_EVENTI,
DDR_ARB,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
output CAN0_PHY_TX;
input CAN0_PHY_RX;
output CAN1_PHY_TX;
input CAN1_PHY_RX;
output ENET0_GMII_TX_EN;
output ENET0_GMII_TX_ER;
output ENET0_MDIO_MDC;
output ENET0_MDIO_O;
output ENET0_MDIO_T;
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
output [7:0]ENET0_GMII_TXD;
input ENET0_GMII_COL;
input ENET0_GMII_CRS;
input ENET0_GMII_RX_CLK;
input ENET0_GMII_RX_DV;
input ENET0_GMII_RX_ER;
input ENET0_GMII_TX_CLK;
input ENET0_MDIO_I;
input ENET0_EXT_INTIN;
input [7:0]ENET0_GMII_RXD;
output ENET1_GMII_TX_EN;
output ENET1_GMII_TX_ER;
output ENET1_MDIO_MDC;
output ENET1_MDIO_O;
output ENET1_MDIO_T;
output ENET1_PTP_DELAY_REQ_RX;
output ENET1_PTP_DELAY_REQ_TX;
output ENET1_PTP_PDELAY_REQ_RX;
output ENET1_PTP_PDELAY_REQ_TX;
output ENET1_PTP_PDELAY_RESP_RX;
output ENET1_PTP_PDELAY_RESP_TX;
output ENET1_PTP_SYNC_FRAME_RX;
output ENET1_PTP_SYNC_FRAME_TX;
output ENET1_SOF_RX;
output ENET1_SOF_TX;
output [7:0]ENET1_GMII_TXD;
input ENET1_GMII_COL;
input ENET1_GMII_CRS;
input ENET1_GMII_RX_CLK;
input ENET1_GMII_RX_DV;
input ENET1_GMII_RX_ER;
input ENET1_GMII_TX_CLK;
input ENET1_MDIO_I;
input ENET1_EXT_INTIN;
input [7:0]ENET1_GMII_RXD;
input [63:0]GPIO_I;
output [63:0]GPIO_O;
output [63:0]GPIO_T;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input I2C1_SDA_I;
output I2C1_SDA_O;
output I2C1_SDA_T;
input I2C1_SCL_I;
output I2C1_SCL_O;
output I2C1_SCL_T;
input PJTAG_TCK;
input PJTAG_TMS;
input PJTAG_TDI;
output PJTAG_TDO;
output SDIO0_CLK;
input SDIO0_CLK_FB;
output SDIO0_CMD_O;
input SDIO0_CMD_I;
output SDIO0_CMD_T;
input [3:0]SDIO0_DATA_I;
output [3:0]SDIO0_DATA_O;
output [3:0]SDIO0_DATA_T;
output SDIO0_LED;
input SDIO0_CDN;
input SDIO0_WP;
output SDIO0_BUSPOW;
output [2:0]SDIO0_BUSVOLT;
output SDIO1_CLK;
input SDIO1_CLK_FB;
output SDIO1_CMD_O;
input SDIO1_CMD_I;
output SDIO1_CMD_T;
input [3:0]SDIO1_DATA_I;
output [3:0]SDIO1_DATA_O;
output [3:0]SDIO1_DATA_T;
output SDIO1_LED;
input SDIO1_CDN;
input SDIO1_WP;
output SDIO1_BUSPOW;
output [2:0]SDIO1_BUSVOLT;
input SPI0_SCLK_I;
output SPI0_SCLK_O;
output SPI0_SCLK_T;
input SPI0_MOSI_I;
output SPI0_MOSI_O;
output SPI0_MOSI_T;
input SPI0_MISO_I;
output SPI0_MISO_O;
output SPI0_MISO_T;
input SPI0_SS_I;
output SPI0_SS_O;
output SPI0_SS1_O;
output SPI0_SS2_O;
output SPI0_SS_T;
input SPI1_SCLK_I;
output SPI1_SCLK_O;
output SPI1_SCLK_T;
input SPI1_MOSI_I;
output SPI1_MOSI_O;
output SPI1_MOSI_T;
input SPI1_MISO_I;
output SPI1_MISO_O;
output SPI1_MISO_T;
input SPI1_SS_I;
output SPI1_SS_O;
output SPI1_SS1_O;
output SPI1_SS2_O;
output SPI1_SS_T;
output UART0_DTRN;
output UART0_RTSN;
output UART0_TX;
input UART0_CTSN;
input UART0_DCDN;
input UART0_DSRN;
input UART0_RIN;
input UART0_RX;
output UART1_DTRN;
output UART1_RTSN;
output UART1_TX;
input UART1_CTSN;
input UART1_DCDN;
input UART1_DSRN;
input UART1_RIN;
input UART1_RX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
input TTC0_CLK0_IN;
input TTC0_CLK1_IN;
input TTC0_CLK2_IN;
output TTC1_WAVE0_OUT;
output TTC1_WAVE1_OUT;
output TTC1_WAVE2_OUT;
input TTC1_CLK0_IN;
input TTC1_CLK1_IN;
input TTC1_CLK2_IN;
input WDT_CLK_IN;
output WDT_RST_OUT;
input TRACE_CLK;
output TRACE_CTL;
output [1:0]TRACE_DATA;
output TRACE_CLK_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output [1:0]USB1_PORT_INDCTL;
output USB1_VBUS_PWRSELECT;
input USB1_VBUS_PWRFAULT;
input SRAM_INTIN;
output M_AXI_GP0_ARESETN;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output M_AXI_GP1_ARESETN;
output M_AXI_GP1_ARVALID;
output M_AXI_GP1_AWVALID;
output M_AXI_GP1_BREADY;
output M_AXI_GP1_RREADY;
output M_AXI_GP1_WLAST;
output M_AXI_GP1_WVALID;
output [11:0]M_AXI_GP1_ARID;
output [11:0]M_AXI_GP1_AWID;
output [11:0]M_AXI_GP1_WID;
output [1:0]M_AXI_GP1_ARBURST;
output [1:0]M_AXI_GP1_ARLOCK;
output [2:0]M_AXI_GP1_ARSIZE;
output [1:0]M_AXI_GP1_AWBURST;
output [1:0]M_AXI_GP1_AWLOCK;
output [2:0]M_AXI_GP1_AWSIZE;
output [2:0]M_AXI_GP1_ARPROT;
output [2:0]M_AXI_GP1_AWPROT;
output [31:0]M_AXI_GP1_ARADDR;
output [31:0]M_AXI_GP1_AWADDR;
output [31:0]M_AXI_GP1_WDATA;
output [3:0]M_AXI_GP1_ARCACHE;
output [3:0]M_AXI_GP1_ARLEN;
output [3:0]M_AXI_GP1_ARQOS;
output [3:0]M_AXI_GP1_AWCACHE;
output [3:0]M_AXI_GP1_AWLEN;
output [3:0]M_AXI_GP1_AWQOS;
output [3:0]M_AXI_GP1_WSTRB;
input M_AXI_GP1_ACLK;
input M_AXI_GP1_ARREADY;
input M_AXI_GP1_AWREADY;
input M_AXI_GP1_BVALID;
input M_AXI_GP1_RLAST;
input M_AXI_GP1_RVALID;
input M_AXI_GP1_WREADY;
input [11:0]M_AXI_GP1_BID;
input [11:0]M_AXI_GP1_RID;
input [1:0]M_AXI_GP1_BRESP;
input [1:0]M_AXI_GP1_RRESP;
input [31:0]M_AXI_GP1_RDATA;
output S_AXI_GP0_ARESETN;
output S_AXI_GP0_ARREADY;
output S_AXI_GP0_AWREADY;
output S_AXI_GP0_BVALID;
output S_AXI_GP0_RLAST;
output S_AXI_GP0_RVALID;
output S_AXI_GP0_WREADY;
output [1:0]S_AXI_GP0_BRESP;
output [1:0]S_AXI_GP0_RRESP;
output [31:0]S_AXI_GP0_RDATA;
output [5:0]S_AXI_GP0_BID;
output [5:0]S_AXI_GP0_RID;
input S_AXI_GP0_ACLK;
input S_AXI_GP0_ARVALID;
input S_AXI_GP0_AWVALID;
input S_AXI_GP0_BREADY;
input S_AXI_GP0_RREADY;
input S_AXI_GP0_WLAST;
input S_AXI_GP0_WVALID;
input [1:0]S_AXI_GP0_ARBURST;
input [1:0]S_AXI_GP0_ARLOCK;
input [2:0]S_AXI_GP0_ARSIZE;
input [1:0]S_AXI_GP0_AWBURST;
input [1:0]S_AXI_GP0_AWLOCK;
input [2:0]S_AXI_GP0_AWSIZE;
input [2:0]S_AXI_GP0_ARPROT;
input [2:0]S_AXI_GP0_AWPROT;
input [31:0]S_AXI_GP0_ARADDR;
input [31:0]S_AXI_GP0_AWADDR;
input [31:0]S_AXI_GP0_WDATA;
input [3:0]S_AXI_GP0_ARCACHE;
input [3:0]S_AXI_GP0_ARLEN;
input [3:0]S_AXI_GP0_ARQOS;
input [3:0]S_AXI_GP0_AWCACHE;
input [3:0]S_AXI_GP0_AWLEN;
input [3:0]S_AXI_GP0_AWQOS;
input [3:0]S_AXI_GP0_WSTRB;
input [5:0]S_AXI_GP0_ARID;
input [5:0]S_AXI_GP0_AWID;
input [5:0]S_AXI_GP0_WID;
output S_AXI_GP1_ARESETN;
output S_AXI_GP1_ARREADY;
output S_AXI_GP1_AWREADY;
output S_AXI_GP1_BVALID;
output S_AXI_GP1_RLAST;
output S_AXI_GP1_RVALID;
output S_AXI_GP1_WREADY;
output [1:0]S_AXI_GP1_BRESP;
output [1:0]S_AXI_GP1_RRESP;
output [31:0]S_AXI_GP1_RDATA;
output [5:0]S_AXI_GP1_BID;
output [5:0]S_AXI_GP1_RID;
input S_AXI_GP1_ACLK;
input S_AXI_GP1_ARVALID;
input S_AXI_GP1_AWVALID;
input S_AXI_GP1_BREADY;
input S_AXI_GP1_RREADY;
input S_AXI_GP1_WLAST;
input S_AXI_GP1_WVALID;
input [1:0]S_AXI_GP1_ARBURST;
input [1:0]S_AXI_GP1_ARLOCK;
input [2:0]S_AXI_GP1_ARSIZE;
input [1:0]S_AXI_GP1_AWBURST;
input [1:0]S_AXI_GP1_AWLOCK;
input [2:0]S_AXI_GP1_AWSIZE;
input [2:0]S_AXI_GP1_ARPROT;
input [2:0]S_AXI_GP1_AWPROT;
input [31:0]S_AXI_GP1_ARADDR;
input [31:0]S_AXI_GP1_AWADDR;
input [31:0]S_AXI_GP1_WDATA;
input [3:0]S_AXI_GP1_ARCACHE;
input [3:0]S_AXI_GP1_ARLEN;
input [3:0]S_AXI_GP1_ARQOS;
input [3:0]S_AXI_GP1_AWCACHE;
input [3:0]S_AXI_GP1_AWLEN;
input [3:0]S_AXI_GP1_AWQOS;
input [3:0]S_AXI_GP1_WSTRB;
input [5:0]S_AXI_GP1_ARID;
input [5:0]S_AXI_GP1_AWID;
input [5:0]S_AXI_GP1_WID;
output S_AXI_ACP_ARESETN;
output S_AXI_ACP_ARREADY;
output S_AXI_ACP_AWREADY;
output S_AXI_ACP_BVALID;
output S_AXI_ACP_RLAST;
output S_AXI_ACP_RVALID;
output S_AXI_ACP_WREADY;
output [1:0]S_AXI_ACP_BRESP;
output [1:0]S_AXI_ACP_RRESP;
output [2:0]S_AXI_ACP_BID;
output [2:0]S_AXI_ACP_RID;
output [63:0]S_AXI_ACP_RDATA;
input S_AXI_ACP_ACLK;
input S_AXI_ACP_ARVALID;
input S_AXI_ACP_AWVALID;
input S_AXI_ACP_BREADY;
input S_AXI_ACP_RREADY;
input S_AXI_ACP_WLAST;
input S_AXI_ACP_WVALID;
input [2:0]S_AXI_ACP_ARID;
input [2:0]S_AXI_ACP_ARPROT;
input [2:0]S_AXI_ACP_AWID;
input [2:0]S_AXI_ACP_AWPROT;
input [2:0]S_AXI_ACP_WID;
input [31:0]S_AXI_ACP_ARADDR;
input [31:0]S_AXI_ACP_AWADDR;
input [3:0]S_AXI_ACP_ARCACHE;
input [3:0]S_AXI_ACP_ARLEN;
input [3:0]S_AXI_ACP_ARQOS;
input [3:0]S_AXI_ACP_AWCACHE;
input [3:0]S_AXI_ACP_AWLEN;
input [3:0]S_AXI_ACP_AWQOS;
input [1:0]S_AXI_ACP_ARBURST;
input [1:0]S_AXI_ACP_ARLOCK;
input [2:0]S_AXI_ACP_ARSIZE;
input [1:0]S_AXI_ACP_AWBURST;
input [1:0]S_AXI_ACP_AWLOCK;
input [2:0]S_AXI_ACP_AWSIZE;
input [4:0]S_AXI_ACP_ARUSER;
input [4:0]S_AXI_ACP_AWUSER;
input [63:0]S_AXI_ACP_WDATA;
input [7:0]S_AXI_ACP_WSTRB;
output S_AXI_HP0_ARESETN;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1:0]S_AXI_HP0_BRESP;
output [1:0]S_AXI_HP0_RRESP;
output [5:0]S_AXI_HP0_BID;
output [5:0]S_AXI_HP0_RID;
output [63:0]S_AXI_HP0_RDATA;
output [7:0]S_AXI_HP0_RCOUNT;
output [7:0]S_AXI_HP0_WCOUNT;
output [2:0]S_AXI_HP0_RACOUNT;
output [5:0]S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1:0]S_AXI_HP0_ARBURST;
input [1:0]S_AXI_HP0_ARLOCK;
input [2:0]S_AXI_HP0_ARSIZE;
input [1:0]S_AXI_HP0_AWBURST;
input [1:0]S_AXI_HP0_AWLOCK;
input [2:0]S_AXI_HP0_AWSIZE;
input [2:0]S_AXI_HP0_ARPROT;
input [2:0]S_AXI_HP0_AWPROT;
input [31:0]S_AXI_HP0_ARADDR;
input [31:0]S_AXI_HP0_AWADDR;
input [3:0]S_AXI_HP0_ARCACHE;
input [3:0]S_AXI_HP0_ARLEN;
input [3:0]S_AXI_HP0_ARQOS;
input [3:0]S_AXI_HP0_AWCACHE;
input [3:0]S_AXI_HP0_AWLEN;
input [3:0]S_AXI_HP0_AWQOS;
input [5:0]S_AXI_HP0_ARID;
input [5:0]S_AXI_HP0_AWID;
input [5:0]S_AXI_HP0_WID;
input [63:0]S_AXI_HP0_WDATA;
input [7:0]S_AXI_HP0_WSTRB;
output S_AXI_HP1_ARESETN;
output S_AXI_HP1_ARREADY;
output S_AXI_HP1_AWREADY;
output S_AXI_HP1_BVALID;
output S_AXI_HP1_RLAST;
output S_AXI_HP1_RVALID;
output S_AXI_HP1_WREADY;
output [1:0]S_AXI_HP1_BRESP;
output [1:0]S_AXI_HP1_RRESP;
output [5:0]S_AXI_HP1_BID;
output [5:0]S_AXI_HP1_RID;
output [63:0]S_AXI_HP1_RDATA;
output [7:0]S_AXI_HP1_RCOUNT;
output [7:0]S_AXI_HP1_WCOUNT;
output [2:0]S_AXI_HP1_RACOUNT;
output [5:0]S_AXI_HP1_WACOUNT;
input S_AXI_HP1_ACLK;
input S_AXI_HP1_ARVALID;
input S_AXI_HP1_AWVALID;
input S_AXI_HP1_BREADY;
input S_AXI_HP1_RDISSUECAP1_EN;
input S_AXI_HP1_RREADY;
input S_AXI_HP1_WLAST;
input S_AXI_HP1_WRISSUECAP1_EN;
input S_AXI_HP1_WVALID;
input [1:0]S_AXI_HP1_ARBURST;
input [1:0]S_AXI_HP1_ARLOCK;
input [2:0]S_AXI_HP1_ARSIZE;
input [1:0]S_AXI_HP1_AWBURST;
input [1:0]S_AXI_HP1_AWLOCK;
input [2:0]S_AXI_HP1_AWSIZE;
input [2:0]S_AXI_HP1_ARPROT;
input [2:0]S_AXI_HP1_AWPROT;
input [31:0]S_AXI_HP1_ARADDR;
input [31:0]S_AXI_HP1_AWADDR;
input [3:0]S_AXI_HP1_ARCACHE;
input [3:0]S_AXI_HP1_ARLEN;
input [3:0]S_AXI_HP1_ARQOS;
input [3:0]S_AXI_HP1_AWCACHE;
input [3:0]S_AXI_HP1_AWLEN;
input [3:0]S_AXI_HP1_AWQOS;
input [5:0]S_AXI_HP1_ARID;
input [5:0]S_AXI_HP1_AWID;
input [5:0]S_AXI_HP1_WID;
input [63:0]S_AXI_HP1_WDATA;
input [7:0]S_AXI_HP1_WSTRB;
output S_AXI_HP2_ARESETN;
output S_AXI_HP2_ARREADY;
output S_AXI_HP2_AWREADY;
output S_AXI_HP2_BVALID;
output S_AXI_HP2_RLAST;
output S_AXI_HP2_RVALID;
output S_AXI_HP2_WREADY;
output [1:0]S_AXI_HP2_BRESP;
output [1:0]S_AXI_HP2_RRESP;
output [5:0]S_AXI_HP2_BID;
output [5:0]S_AXI_HP2_RID;
output [63:0]S_AXI_HP2_RDATA;
output [7:0]S_AXI_HP2_RCOUNT;
output [7:0]S_AXI_HP2_WCOUNT;
output [2:0]S_AXI_HP2_RACOUNT;
output [5:0]S_AXI_HP2_WACOUNT;
input S_AXI_HP2_ACLK;
input S_AXI_HP2_ARVALID;
input S_AXI_HP2_AWVALID;
input S_AXI_HP2_BREADY;
input S_AXI_HP2_RDISSUECAP1_EN;
input S_AXI_HP2_RREADY;
input S_AXI_HP2_WLAST;
input S_AXI_HP2_WRISSUECAP1_EN;
input S_AXI_HP2_WVALID;
input [1:0]S_AXI_HP2_ARBURST;
input [1:0]S_AXI_HP2_ARLOCK;
input [2:0]S_AXI_HP2_ARSIZE;
input [1:0]S_AXI_HP2_AWBURST;
input [1:0]S_AXI_HP2_AWLOCK;
input [2:0]S_AXI_HP2_AWSIZE;
input [2:0]S_AXI_HP2_ARPROT;
input [2:0]S_AXI_HP2_AWPROT;
input [31:0]S_AXI_HP2_ARADDR;
input [31:0]S_AXI_HP2_AWADDR;
input [3:0]S_AXI_HP2_ARCACHE;
input [3:0]S_AXI_HP2_ARLEN;
input [3:0]S_AXI_HP2_ARQOS;
input [3:0]S_AXI_HP2_AWCACHE;
input [3:0]S_AXI_HP2_AWLEN;
input [3:0]S_AXI_HP2_AWQOS;
input [5:0]S_AXI_HP2_ARID;
input [5:0]S_AXI_HP2_AWID;
input [5:0]S_AXI_HP2_WID;
input [63:0]S_AXI_HP2_WDATA;
input [7:0]S_AXI_HP2_WSTRB;
output S_AXI_HP3_ARESETN;
output S_AXI_HP3_ARREADY;
output S_AXI_HP3_AWREADY;
output S_AXI_HP3_BVALID;
output S_AXI_HP3_RLAST;
output S_AXI_HP3_RVALID;
output S_AXI_HP3_WREADY;
output [1:0]S_AXI_HP3_BRESP;
output [1:0]S_AXI_HP3_RRESP;
output [5:0]S_AXI_HP3_BID;
output [5:0]S_AXI_HP3_RID;
output [63:0]S_AXI_HP3_RDATA;
output [7:0]S_AXI_HP3_RCOUNT;
output [7:0]S_AXI_HP3_WCOUNT;
output [2:0]S_AXI_HP3_RACOUNT;
output [5:0]S_AXI_HP3_WACOUNT;
input S_AXI_HP3_ACLK;
input S_AXI_HP3_ARVALID;
input S_AXI_HP3_AWVALID;
input S_AXI_HP3_BREADY;
input S_AXI_HP3_RDISSUECAP1_EN;
input S_AXI_HP3_RREADY;
input S_AXI_HP3_WLAST;
input S_AXI_HP3_WRISSUECAP1_EN;
input S_AXI_HP3_WVALID;
input [1:0]S_AXI_HP3_ARBURST;
input [1:0]S_AXI_HP3_ARLOCK;
input [2:0]S_AXI_HP3_ARSIZE;
input [1:0]S_AXI_HP3_AWBURST;
input [1:0]S_AXI_HP3_AWLOCK;
input [2:0]S_AXI_HP3_AWSIZE;
input [2:0]S_AXI_HP3_ARPROT;
input [2:0]S_AXI_HP3_AWPROT;
input [31:0]S_AXI_HP3_ARADDR;
input [31:0]S_AXI_HP3_AWADDR;
input [3:0]S_AXI_HP3_ARCACHE;
input [3:0]S_AXI_HP3_ARLEN;
input [3:0]S_AXI_HP3_ARQOS;
input [3:0]S_AXI_HP3_AWCACHE;
input [3:0]S_AXI_HP3_AWLEN;
input [3:0]S_AXI_HP3_AWQOS;
input [5:0]S_AXI_HP3_ARID;
input [5:0]S_AXI_HP3_AWID;
input [5:0]S_AXI_HP3_WID;
input [63:0]S_AXI_HP3_WDATA;
input [7:0]S_AXI_HP3_WSTRB;
output IRQ_P2F_DMAC_ABORT;
output IRQ_P2F_DMAC0;
output IRQ_P2F_DMAC1;
output IRQ_P2F_DMAC2;
output IRQ_P2F_DMAC3;
output IRQ_P2F_DMAC4;
output IRQ_P2F_DMAC5;
output IRQ_P2F_DMAC6;
output IRQ_P2F_DMAC7;
output IRQ_P2F_SMC;
output IRQ_P2F_QSPI;
output IRQ_P2F_CTI;
output IRQ_P2F_GPIO;
output IRQ_P2F_USB0;
output IRQ_P2F_ENET0;
output IRQ_P2F_ENET_WAKE0;
output IRQ_P2F_SDIO0;
output IRQ_P2F_I2C0;
output IRQ_P2F_SPI0;
output IRQ_P2F_UART0;
output IRQ_P2F_CAN0;
output IRQ_P2F_USB1;
output IRQ_P2F_ENET1;
output IRQ_P2F_ENET_WAKE1;
output IRQ_P2F_SDIO1;
output IRQ_P2F_I2C1;
output IRQ_P2F_SPI1;
output IRQ_P2F_UART1;
output IRQ_P2F_CAN1;
input [0:0]IRQ_F2P;
input Core0_nFIQ;
input Core0_nIRQ;
input Core1_nFIQ;
input Core1_nIRQ;
output [1:0]DMA0_DATYPE;
output DMA0_DAVALID;
output DMA0_DRREADY;
output DMA0_RSTN;
output [1:0]DMA1_DATYPE;
output DMA1_DAVALID;
output DMA1_DRREADY;
output DMA1_RSTN;
output [1:0]DMA2_DATYPE;
output DMA2_DAVALID;
output DMA2_DRREADY;
output DMA2_RSTN;
output [1:0]DMA3_DATYPE;
output DMA3_DAVALID;
output DMA3_DRREADY;
output DMA3_RSTN;
input DMA0_ACLK;
input DMA0_DAREADY;
input DMA0_DRLAST;
input DMA0_DRVALID;
input DMA1_ACLK;
input DMA1_DAREADY;
input DMA1_DRLAST;
input DMA1_DRVALID;
input DMA2_ACLK;
input DMA2_DAREADY;
input DMA2_DRLAST;
input DMA2_DRVALID;
input DMA3_ACLK;
input DMA3_DAREADY;
input DMA3_DRLAST;
input DMA3_DRVALID;
input [1:0]DMA0_DRTYPE;
input [1:0]DMA1_DRTYPE;
input [1:0]DMA2_DRTYPE;
input [1:0]DMA3_DRTYPE;
output FCLK_CLK3;
output FCLK_CLK2;
output FCLK_CLK1;
output FCLK_CLK0;
input FCLK_CLKTRIG3_N;
input FCLK_CLKTRIG2_N;
input FCLK_CLKTRIG1_N;
input FCLK_CLKTRIG0_N;
output FCLK_RESET3_N;
output FCLK_RESET2_N;
output FCLK_RESET1_N;
output FCLK_RESET0_N;
input [31:0]FTMD_TRACEIN_DATA;
input FTMD_TRACEIN_VALID;
input FTMD_TRACEIN_CLK;
input [3:0]FTMD_TRACEIN_ATID;
input FTMT_F2P_TRIG_0;
output FTMT_F2P_TRIGACK_0;
input FTMT_F2P_TRIG_1;
output FTMT_F2P_TRIGACK_1;
input FTMT_F2P_TRIG_2;
output FTMT_F2P_TRIGACK_2;
input FTMT_F2P_TRIG_3;
output FTMT_F2P_TRIGACK_3;
input [31:0]FTMT_F2P_DEBUG;
input FTMT_P2F_TRIGACK_0;
output FTMT_P2F_TRIG_0;
input FTMT_P2F_TRIGACK_1;
output FTMT_P2F_TRIG_1;
input FTMT_P2F_TRIGACK_2;
output FTMT_P2F_TRIG_2;
input FTMT_P2F_TRIGACK_3;
output FTMT_P2F_TRIG_3;
output [31:0]FTMT_P2F_DEBUG;
input FPGA_IDLE_N;
output EVENT_EVENTO;
output [1:0]EVENT_STANDBYWFE;
output [1:0]EVENT_STANDBYWFI;
input EVENT_EVENTI;
input [3:0]DDR_ARB;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
wire \<const0> ;
wire \<const1> ;
wire CAN0_PHY_RX;
wire CAN0_PHY_TX;
wire CAN1_PHY_RX;
wire CAN1_PHY_TX;
wire Core0_nFIQ;
wire Core0_nIRQ;
wire Core1_nFIQ;
wire Core1_nIRQ;
wire [3:0]DDR_ARB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire DMA0_ACLK;
wire DMA0_DAREADY;
wire [1:0]DMA0_DATYPE;
wire DMA0_DAVALID;
wire DMA0_DRLAST;
wire DMA0_DRREADY;
wire [1:0]DMA0_DRTYPE;
wire DMA0_DRVALID;
wire DMA0_RSTN;
wire DMA1_ACLK;
wire DMA1_DAREADY;
wire [1:0]DMA1_DATYPE;
wire DMA1_DAVALID;
wire DMA1_DRLAST;
wire DMA1_DRREADY;
wire [1:0]DMA1_DRTYPE;
wire DMA1_DRVALID;
wire DMA1_RSTN;
wire DMA2_ACLK;
wire DMA2_DAREADY;
wire [1:0]DMA2_DATYPE;
wire DMA2_DAVALID;
wire DMA2_DRLAST;
wire DMA2_DRREADY;
wire [1:0]DMA2_DRTYPE;
wire DMA2_DRVALID;
wire DMA2_RSTN;
wire DMA3_ACLK;
wire DMA3_DAREADY;
wire [1:0]DMA3_DATYPE;
wire DMA3_DAVALID;
wire DMA3_DRLAST;
wire DMA3_DRREADY;
wire [1:0]DMA3_DRTYPE;
wire DMA3_DRVALID;
wire DMA3_RSTN;
wire ENET0_EXT_INTIN;
wire ENET0_GMII_RX_CLK;
wire ENET0_GMII_TX_CLK;
wire ENET0_MDIO_I;
wire ENET0_MDIO_MDC;
wire ENET0_MDIO_O;
wire ENET0_MDIO_T;
wire ENET0_MDIO_T_n;
wire ENET0_PTP_DELAY_REQ_RX;
wire ENET0_PTP_DELAY_REQ_TX;
wire ENET0_PTP_PDELAY_REQ_RX;
wire ENET0_PTP_PDELAY_REQ_TX;
wire ENET0_PTP_PDELAY_RESP_RX;
wire ENET0_PTP_PDELAY_RESP_TX;
wire ENET0_PTP_SYNC_FRAME_RX;
wire ENET0_PTP_SYNC_FRAME_TX;
wire ENET0_SOF_RX;
wire ENET0_SOF_TX;
wire ENET1_EXT_INTIN;
wire ENET1_GMII_RX_CLK;
wire ENET1_GMII_TX_CLK;
wire ENET1_MDIO_I;
wire ENET1_MDIO_MDC;
wire ENET1_MDIO_O;
wire ENET1_MDIO_T;
wire ENET1_MDIO_T_n;
wire ENET1_PTP_DELAY_REQ_RX;
wire ENET1_PTP_DELAY_REQ_TX;
wire ENET1_PTP_PDELAY_REQ_RX;
wire ENET1_PTP_PDELAY_REQ_TX;
wire ENET1_PTP_PDELAY_RESP_RX;
wire ENET1_PTP_PDELAY_RESP_TX;
wire ENET1_PTP_SYNC_FRAME_RX;
wire ENET1_PTP_SYNC_FRAME_TX;
wire ENET1_SOF_RX;
wire ENET1_SOF_TX;
wire EVENT_EVENTI;
wire EVENT_EVENTO;
wire [1:0]EVENT_STANDBYWFE;
wire [1:0]EVENT_STANDBYWFI;
wire FCLK_CLK0;
wire FCLK_CLK1;
wire FCLK_CLK2;
wire FCLK_CLK3;
wire [1:0]FCLK_CLK_unbuffered;
wire FCLK_RESET0_N;
wire FCLK_RESET1_N;
wire FCLK_RESET2_N;
wire FCLK_RESET3_N;
wire FPGA_IDLE_N;
wire FTMD_TRACEIN_CLK;
wire [31:0]FTMT_F2P_DEBUG;
wire FTMT_F2P_TRIGACK_0;
wire FTMT_F2P_TRIGACK_1;
wire FTMT_F2P_TRIGACK_2;
wire FTMT_F2P_TRIGACK_3;
wire FTMT_F2P_TRIG_0;
wire FTMT_F2P_TRIG_1;
wire FTMT_F2P_TRIG_2;
wire FTMT_F2P_TRIG_3;
wire [31:0]FTMT_P2F_DEBUG;
wire FTMT_P2F_TRIGACK_0;
wire FTMT_P2F_TRIGACK_1;
wire FTMT_P2F_TRIGACK_2;
wire FTMT_P2F_TRIGACK_3;
wire FTMT_P2F_TRIG_0;
wire FTMT_P2F_TRIG_1;
wire FTMT_P2F_TRIG_2;
wire FTMT_P2F_TRIG_3;
wire [63:0]GPIO_I;
wire [63:0]GPIO_O;
wire [63:0]GPIO_T;
wire I2C0_SCL_I;
wire I2C0_SCL_O;
wire I2C0_SCL_T;
wire I2C0_SCL_T_n;
wire I2C0_SDA_I;
wire I2C0_SDA_O;
wire I2C0_SDA_T;
wire I2C0_SDA_T_n;
wire I2C1_SCL_I;
wire I2C1_SCL_O;
wire I2C1_SCL_T;
wire I2C1_SCL_T_n;
wire I2C1_SDA_I;
wire I2C1_SDA_O;
wire I2C1_SDA_T;
wire I2C1_SDA_T_n;
wire [0:0]IRQ_F2P;
wire IRQ_P2F_CAN0;
wire IRQ_P2F_CAN1;
wire IRQ_P2F_CTI;
wire IRQ_P2F_DMAC0;
wire IRQ_P2F_DMAC1;
wire IRQ_P2F_DMAC2;
wire IRQ_P2F_DMAC3;
wire IRQ_P2F_DMAC4;
wire IRQ_P2F_DMAC5;
wire IRQ_P2F_DMAC6;
wire IRQ_P2F_DMAC7;
wire IRQ_P2F_DMAC_ABORT;
wire IRQ_P2F_ENET0;
wire IRQ_P2F_ENET1;
wire IRQ_P2F_ENET_WAKE0;
wire IRQ_P2F_ENET_WAKE1;
wire IRQ_P2F_GPIO;
wire IRQ_P2F_I2C0;
wire IRQ_P2F_I2C1;
wire IRQ_P2F_QSPI;
wire IRQ_P2F_SDIO0;
wire IRQ_P2F_SDIO1;
wire IRQ_P2F_SMC;
wire IRQ_P2F_SPI0;
wire IRQ_P2F_SPI1;
wire IRQ_P2F_UART0;
wire IRQ_P2F_UART1;
wire IRQ_P2F_USB0;
wire IRQ_P2F_USB1;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]\^M_AXI_GP0_ARCACHE ;
wire M_AXI_GP0_ARESETN;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [1:0]\^M_AXI_GP0_ARSIZE ;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]\^M_AXI_GP0_AWCACHE ;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [1:0]\^M_AXI_GP0_AWSIZE ;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire M_AXI_GP1_ACLK;
wire [31:0]M_AXI_GP1_ARADDR;
wire [1:0]M_AXI_GP1_ARBURST;
wire [3:0]\^M_AXI_GP1_ARCACHE ;
wire M_AXI_GP1_ARESETN;
wire [11:0]M_AXI_GP1_ARID;
wire [3:0]M_AXI_GP1_ARLEN;
wire [1:0]M_AXI_GP1_ARLOCK;
wire [2:0]M_AXI_GP1_ARPROT;
wire [3:0]M_AXI_GP1_ARQOS;
wire M_AXI_GP1_ARREADY;
wire [1:0]\^M_AXI_GP1_ARSIZE ;
wire M_AXI_GP1_ARVALID;
wire [31:0]M_AXI_GP1_AWADDR;
wire [1:0]M_AXI_GP1_AWBURST;
wire [3:0]\^M_AXI_GP1_AWCACHE ;
wire [11:0]M_AXI_GP1_AWID;
wire [3:0]M_AXI_GP1_AWLEN;
wire [1:0]M_AXI_GP1_AWLOCK;
wire [2:0]M_AXI_GP1_AWPROT;
wire [3:0]M_AXI_GP1_AWQOS;
wire M_AXI_GP1_AWREADY;
wire [1:0]\^M_AXI_GP1_AWSIZE ;
wire M_AXI_GP1_AWVALID;
wire [11:0]M_AXI_GP1_BID;
wire M_AXI_GP1_BREADY;
wire [1:0]M_AXI_GP1_BRESP;
wire M_AXI_GP1_BVALID;
wire [31:0]M_AXI_GP1_RDATA;
wire [11:0]M_AXI_GP1_RID;
wire M_AXI_GP1_RLAST;
wire M_AXI_GP1_RREADY;
wire [1:0]M_AXI_GP1_RRESP;
wire M_AXI_GP1_RVALID;
wire [31:0]M_AXI_GP1_WDATA;
wire [11:0]M_AXI_GP1_WID;
wire M_AXI_GP1_WLAST;
wire M_AXI_GP1_WREADY;
wire [3:0]M_AXI_GP1_WSTRB;
wire M_AXI_GP1_WVALID;
wire PJTAG_TCK;
wire PJTAG_TDI;
wire PJTAG_TMS;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire SDIO0_BUSPOW;
wire [2:0]SDIO0_BUSVOLT;
wire SDIO0_CDN;
wire SDIO0_CLK;
wire SDIO0_CLK_FB;
wire SDIO0_CMD_I;
wire SDIO0_CMD_O;
wire SDIO0_CMD_T;
wire SDIO0_CMD_T_n;
wire [3:0]SDIO0_DATA_I;
wire [3:0]SDIO0_DATA_O;
wire [3:0]SDIO0_DATA_T;
wire [3:0]SDIO0_DATA_T_n;
wire SDIO0_LED;
wire SDIO0_WP;
wire SDIO1_BUSPOW;
wire [2:0]SDIO1_BUSVOLT;
wire SDIO1_CDN;
wire SDIO1_CLK;
wire SDIO1_CLK_FB;
wire SDIO1_CMD_I;
wire SDIO1_CMD_O;
wire SDIO1_CMD_T;
wire SDIO1_CMD_T_n;
wire [3:0]SDIO1_DATA_I;
wire [3:0]SDIO1_DATA_O;
wire [3:0]SDIO1_DATA_T;
wire [3:0]SDIO1_DATA_T_n;
wire SDIO1_LED;
wire SDIO1_WP;
wire SPI0_MISO_I;
wire SPI0_MISO_O;
wire SPI0_MISO_T;
wire SPI0_MISO_T_n;
wire SPI0_MOSI_I;
wire SPI0_MOSI_O;
wire SPI0_MOSI_T;
wire SPI0_MOSI_T_n;
wire SPI0_SCLK_I;
wire SPI0_SCLK_O;
wire SPI0_SCLK_T;
wire SPI0_SCLK_T_n;
wire SPI0_SS1_O;
wire SPI0_SS2_O;
wire SPI0_SS_I;
wire SPI0_SS_O;
wire SPI0_SS_T;
wire SPI0_SS_T_n;
wire SPI1_MISO_I;
wire SPI1_MISO_O;
wire SPI1_MISO_T;
wire SPI1_MISO_T_n;
wire SPI1_MOSI_I;
wire SPI1_MOSI_O;
wire SPI1_MOSI_T;
wire SPI1_MOSI_T_n;
wire SPI1_SCLK_I;
wire SPI1_SCLK_O;
wire SPI1_SCLK_T;
wire SPI1_SCLK_T_n;
wire SPI1_SS1_O;
wire SPI1_SS2_O;
wire SPI1_SS_I;
wire SPI1_SS_O;
wire SPI1_SS_T;
wire SPI1_SS_T_n;
wire SRAM_INTIN;
wire S_AXI_ACP_ACLK;
wire [31:0]S_AXI_ACP_ARADDR;
wire [1:0]S_AXI_ACP_ARBURST;
wire [3:0]S_AXI_ACP_ARCACHE;
wire S_AXI_ACP_ARESETN;
wire [2:0]S_AXI_ACP_ARID;
wire [3:0]S_AXI_ACP_ARLEN;
wire [1:0]S_AXI_ACP_ARLOCK;
wire [2:0]S_AXI_ACP_ARPROT;
wire [3:0]S_AXI_ACP_ARQOS;
wire S_AXI_ACP_ARREADY;
wire [2:0]S_AXI_ACP_ARSIZE;
wire [4:0]S_AXI_ACP_ARUSER;
wire S_AXI_ACP_ARVALID;
wire [31:0]S_AXI_ACP_AWADDR;
wire [1:0]S_AXI_ACP_AWBURST;
wire [3:0]S_AXI_ACP_AWCACHE;
wire [2:0]S_AXI_ACP_AWID;
wire [3:0]S_AXI_ACP_AWLEN;
wire [1:0]S_AXI_ACP_AWLOCK;
wire [2:0]S_AXI_ACP_AWPROT;
wire [3:0]S_AXI_ACP_AWQOS;
wire S_AXI_ACP_AWREADY;
wire [2:0]S_AXI_ACP_AWSIZE;
wire [4:0]S_AXI_ACP_AWUSER;
wire S_AXI_ACP_AWVALID;
wire [2:0]S_AXI_ACP_BID;
wire S_AXI_ACP_BREADY;
wire [1:0]S_AXI_ACP_BRESP;
wire S_AXI_ACP_BVALID;
wire [63:0]S_AXI_ACP_RDATA;
wire [2:0]S_AXI_ACP_RID;
wire S_AXI_ACP_RLAST;
wire S_AXI_ACP_RREADY;
wire [1:0]S_AXI_ACP_RRESP;
wire S_AXI_ACP_RVALID;
wire [63:0]S_AXI_ACP_WDATA;
wire [2:0]S_AXI_ACP_WID;
wire S_AXI_ACP_WLAST;
wire S_AXI_ACP_WREADY;
wire [7:0]S_AXI_ACP_WSTRB;
wire S_AXI_ACP_WVALID;
wire S_AXI_GP0_ACLK;
wire [31:0]S_AXI_GP0_ARADDR;
wire [1:0]S_AXI_GP0_ARBURST;
wire [3:0]S_AXI_GP0_ARCACHE;
wire S_AXI_GP0_ARESETN;
wire [5:0]S_AXI_GP0_ARID;
wire [3:0]S_AXI_GP0_ARLEN;
wire [1:0]S_AXI_GP0_ARLOCK;
wire [2:0]S_AXI_GP0_ARPROT;
wire [3:0]S_AXI_GP0_ARQOS;
wire S_AXI_GP0_ARREADY;
wire [2:0]S_AXI_GP0_ARSIZE;
wire S_AXI_GP0_ARVALID;
wire [31:0]S_AXI_GP0_AWADDR;
wire [1:0]S_AXI_GP0_AWBURST;
wire [3:0]S_AXI_GP0_AWCACHE;
wire [5:0]S_AXI_GP0_AWID;
wire [3:0]S_AXI_GP0_AWLEN;
wire [1:0]S_AXI_GP0_AWLOCK;
wire [2:0]S_AXI_GP0_AWPROT;
wire [3:0]S_AXI_GP0_AWQOS;
wire S_AXI_GP0_AWREADY;
wire [2:0]S_AXI_GP0_AWSIZE;
wire S_AXI_GP0_AWVALID;
wire [5:0]S_AXI_GP0_BID;
wire S_AXI_GP0_BREADY;
wire [1:0]S_AXI_GP0_BRESP;
wire S_AXI_GP0_BVALID;
wire [31:0]S_AXI_GP0_RDATA;
wire [5:0]S_AXI_GP0_RID;
wire S_AXI_GP0_RLAST;
wire S_AXI_GP0_RREADY;
wire [1:0]S_AXI_GP0_RRESP;
wire S_AXI_GP0_RVALID;
wire [31:0]S_AXI_GP0_WDATA;
wire [5:0]S_AXI_GP0_WID;
wire S_AXI_GP0_WLAST;
wire S_AXI_GP0_WREADY;
wire [3:0]S_AXI_GP0_WSTRB;
wire S_AXI_GP0_WVALID;
wire S_AXI_GP1_ACLK;
wire [31:0]S_AXI_GP1_ARADDR;
wire [1:0]S_AXI_GP1_ARBURST;
wire [3:0]S_AXI_GP1_ARCACHE;
wire S_AXI_GP1_ARESETN;
wire [5:0]S_AXI_GP1_ARID;
wire [3:0]S_AXI_GP1_ARLEN;
wire [1:0]S_AXI_GP1_ARLOCK;
wire [2:0]S_AXI_GP1_ARPROT;
wire [3:0]S_AXI_GP1_ARQOS;
wire S_AXI_GP1_ARREADY;
wire [2:0]S_AXI_GP1_ARSIZE;
wire S_AXI_GP1_ARVALID;
wire [31:0]S_AXI_GP1_AWADDR;
wire [1:0]S_AXI_GP1_AWBURST;
wire [3:0]S_AXI_GP1_AWCACHE;
wire [5:0]S_AXI_GP1_AWID;
wire [3:0]S_AXI_GP1_AWLEN;
wire [1:0]S_AXI_GP1_AWLOCK;
wire [2:0]S_AXI_GP1_AWPROT;
wire [3:0]S_AXI_GP1_AWQOS;
wire S_AXI_GP1_AWREADY;
wire [2:0]S_AXI_GP1_AWSIZE;
wire S_AXI_GP1_AWVALID;
wire [5:0]S_AXI_GP1_BID;
wire S_AXI_GP1_BREADY;
wire [1:0]S_AXI_GP1_BRESP;
wire S_AXI_GP1_BVALID;
wire [31:0]S_AXI_GP1_RDATA;
wire [5:0]S_AXI_GP1_RID;
wire S_AXI_GP1_RLAST;
wire S_AXI_GP1_RREADY;
wire [1:0]S_AXI_GP1_RRESP;
wire S_AXI_GP1_RVALID;
wire [31:0]S_AXI_GP1_WDATA;
wire [5:0]S_AXI_GP1_WID;
wire S_AXI_GP1_WLAST;
wire S_AXI_GP1_WREADY;
wire [3:0]S_AXI_GP1_WSTRB;
wire S_AXI_GP1_WVALID;
wire S_AXI_HP0_ACLK;
wire [31:0]S_AXI_HP0_ARADDR;
wire [1:0]S_AXI_HP0_ARBURST;
wire [3:0]S_AXI_HP0_ARCACHE;
wire S_AXI_HP0_ARESETN;
wire [5:0]S_AXI_HP0_ARID;
wire [3:0]S_AXI_HP0_ARLEN;
wire [1:0]S_AXI_HP0_ARLOCK;
wire [2:0]S_AXI_HP0_ARPROT;
wire [3:0]S_AXI_HP0_ARQOS;
wire S_AXI_HP0_ARREADY;
wire [2:0]S_AXI_HP0_ARSIZE;
wire S_AXI_HP0_ARVALID;
wire [31:0]S_AXI_HP0_AWADDR;
wire [1:0]S_AXI_HP0_AWBURST;
wire [3:0]S_AXI_HP0_AWCACHE;
wire [5:0]S_AXI_HP0_AWID;
wire [3:0]S_AXI_HP0_AWLEN;
wire [1:0]S_AXI_HP0_AWLOCK;
wire [2:0]S_AXI_HP0_AWPROT;
wire [3:0]S_AXI_HP0_AWQOS;
wire S_AXI_HP0_AWREADY;
wire [2:0]S_AXI_HP0_AWSIZE;
wire S_AXI_HP0_AWVALID;
wire [5:0]S_AXI_HP0_BID;
wire S_AXI_HP0_BREADY;
wire [1:0]S_AXI_HP0_BRESP;
wire S_AXI_HP0_BVALID;
wire [2:0]S_AXI_HP0_RACOUNT;
wire [7:0]S_AXI_HP0_RCOUNT;
wire [63:0]S_AXI_HP0_RDATA;
wire S_AXI_HP0_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP0_RID;
wire S_AXI_HP0_RLAST;
wire S_AXI_HP0_RREADY;
wire [1:0]S_AXI_HP0_RRESP;
wire S_AXI_HP0_RVALID;
wire [5:0]S_AXI_HP0_WACOUNT;
wire [7:0]S_AXI_HP0_WCOUNT;
wire [63:0]S_AXI_HP0_WDATA;
wire [5:0]S_AXI_HP0_WID;
wire S_AXI_HP0_WLAST;
wire S_AXI_HP0_WREADY;
wire S_AXI_HP0_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP0_WSTRB;
wire S_AXI_HP0_WVALID;
wire S_AXI_HP1_ACLK;
wire [31:0]S_AXI_HP1_ARADDR;
wire [1:0]S_AXI_HP1_ARBURST;
wire [3:0]S_AXI_HP1_ARCACHE;
wire S_AXI_HP1_ARESETN;
wire [5:0]S_AXI_HP1_ARID;
wire [3:0]S_AXI_HP1_ARLEN;
wire [1:0]S_AXI_HP1_ARLOCK;
wire [2:0]S_AXI_HP1_ARPROT;
wire [3:0]S_AXI_HP1_ARQOS;
wire S_AXI_HP1_ARREADY;
wire [2:0]S_AXI_HP1_ARSIZE;
wire S_AXI_HP1_ARVALID;
wire [31:0]S_AXI_HP1_AWADDR;
wire [1:0]S_AXI_HP1_AWBURST;
wire [3:0]S_AXI_HP1_AWCACHE;
wire [5:0]S_AXI_HP1_AWID;
wire [3:0]S_AXI_HP1_AWLEN;
wire [1:0]S_AXI_HP1_AWLOCK;
wire [2:0]S_AXI_HP1_AWPROT;
wire [3:0]S_AXI_HP1_AWQOS;
wire S_AXI_HP1_AWREADY;
wire [2:0]S_AXI_HP1_AWSIZE;
wire S_AXI_HP1_AWVALID;
wire [5:0]S_AXI_HP1_BID;
wire S_AXI_HP1_BREADY;
wire [1:0]S_AXI_HP1_BRESP;
wire S_AXI_HP1_BVALID;
wire [2:0]S_AXI_HP1_RACOUNT;
wire [7:0]S_AXI_HP1_RCOUNT;
wire [63:0]S_AXI_HP1_RDATA;
wire S_AXI_HP1_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP1_RID;
wire S_AXI_HP1_RLAST;
wire S_AXI_HP1_RREADY;
wire [1:0]S_AXI_HP1_RRESP;
wire S_AXI_HP1_RVALID;
wire [5:0]S_AXI_HP1_WACOUNT;
wire [7:0]S_AXI_HP1_WCOUNT;
wire [63:0]S_AXI_HP1_WDATA;
wire [5:0]S_AXI_HP1_WID;
wire S_AXI_HP1_WLAST;
wire S_AXI_HP1_WREADY;
wire S_AXI_HP1_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP1_WSTRB;
wire S_AXI_HP1_WVALID;
wire S_AXI_HP2_ACLK;
wire [31:0]S_AXI_HP2_ARADDR;
wire [1:0]S_AXI_HP2_ARBURST;
wire [3:0]S_AXI_HP2_ARCACHE;
wire S_AXI_HP2_ARESETN;
wire [5:0]S_AXI_HP2_ARID;
wire [3:0]S_AXI_HP2_ARLEN;
wire [1:0]S_AXI_HP2_ARLOCK;
wire [2:0]S_AXI_HP2_ARPROT;
wire [3:0]S_AXI_HP2_ARQOS;
wire S_AXI_HP2_ARREADY;
wire [2:0]S_AXI_HP2_ARSIZE;
wire S_AXI_HP2_ARVALID;
wire [31:0]S_AXI_HP2_AWADDR;
wire [1:0]S_AXI_HP2_AWBURST;
wire [3:0]S_AXI_HP2_AWCACHE;
wire [5:0]S_AXI_HP2_AWID;
wire [3:0]S_AXI_HP2_AWLEN;
wire [1:0]S_AXI_HP2_AWLOCK;
wire [2:0]S_AXI_HP2_AWPROT;
wire [3:0]S_AXI_HP2_AWQOS;
wire S_AXI_HP2_AWREADY;
wire [2:0]S_AXI_HP2_AWSIZE;
wire S_AXI_HP2_AWVALID;
wire [5:0]S_AXI_HP2_BID;
wire S_AXI_HP2_BREADY;
wire [1:0]S_AXI_HP2_BRESP;
wire S_AXI_HP2_BVALID;
wire [2:0]S_AXI_HP2_RACOUNT;
wire [7:0]S_AXI_HP2_RCOUNT;
wire [63:0]S_AXI_HP2_RDATA;
wire S_AXI_HP2_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP2_RID;
wire S_AXI_HP2_RLAST;
wire S_AXI_HP2_RREADY;
wire [1:0]S_AXI_HP2_RRESP;
wire S_AXI_HP2_RVALID;
wire [5:0]S_AXI_HP2_WACOUNT;
wire [7:0]S_AXI_HP2_WCOUNT;
wire [63:0]S_AXI_HP2_WDATA;
wire [5:0]S_AXI_HP2_WID;
wire S_AXI_HP2_WLAST;
wire S_AXI_HP2_WREADY;
wire S_AXI_HP2_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP2_WSTRB;
wire S_AXI_HP2_WVALID;
wire S_AXI_HP3_ACLK;
wire [31:0]S_AXI_HP3_ARADDR;
wire [1:0]S_AXI_HP3_ARBURST;
wire [3:0]S_AXI_HP3_ARCACHE;
wire S_AXI_HP3_ARESETN;
wire [5:0]S_AXI_HP3_ARID;
wire [3:0]S_AXI_HP3_ARLEN;
wire [1:0]S_AXI_HP3_ARLOCK;
wire [2:0]S_AXI_HP3_ARPROT;
wire [3:0]S_AXI_HP3_ARQOS;
wire S_AXI_HP3_ARREADY;
wire [2:0]S_AXI_HP3_ARSIZE;
wire S_AXI_HP3_ARVALID;
wire [31:0]S_AXI_HP3_AWADDR;
wire [1:0]S_AXI_HP3_AWBURST;
wire [3:0]S_AXI_HP3_AWCACHE;
wire [5:0]S_AXI_HP3_AWID;
wire [3:0]S_AXI_HP3_AWLEN;
wire [1:0]S_AXI_HP3_AWLOCK;
wire [2:0]S_AXI_HP3_AWPROT;
wire [3:0]S_AXI_HP3_AWQOS;
wire S_AXI_HP3_AWREADY;
wire [2:0]S_AXI_HP3_AWSIZE;
wire S_AXI_HP3_AWVALID;
wire [5:0]S_AXI_HP3_BID;
wire S_AXI_HP3_BREADY;
wire [1:0]S_AXI_HP3_BRESP;
wire S_AXI_HP3_BVALID;
wire [2:0]S_AXI_HP3_RACOUNT;
wire [7:0]S_AXI_HP3_RCOUNT;
wire [63:0]S_AXI_HP3_RDATA;
wire S_AXI_HP3_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP3_RID;
wire S_AXI_HP3_RLAST;
wire S_AXI_HP3_RREADY;
wire [1:0]S_AXI_HP3_RRESP;
wire S_AXI_HP3_RVALID;
wire [5:0]S_AXI_HP3_WACOUNT;
wire [7:0]S_AXI_HP3_WCOUNT;
wire [63:0]S_AXI_HP3_WDATA;
wire [5:0]S_AXI_HP3_WID;
wire S_AXI_HP3_WLAST;
wire S_AXI_HP3_WREADY;
wire S_AXI_HP3_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP3_WSTRB;
wire S_AXI_HP3_WVALID;
wire TRACE_CLK;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[0] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[1] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[2] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[3] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[4] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[5] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[6] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[7] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[0] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[1] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[2] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[3] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[4] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[5] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[6] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[7] ;
wire TTC0_CLK0_IN;
wire TTC0_CLK1_IN;
wire TTC0_CLK2_IN;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire TTC1_CLK0_IN;
wire TTC1_CLK1_IN;
wire TTC1_CLK2_IN;
wire TTC1_WAVE0_OUT;
wire TTC1_WAVE1_OUT;
wire TTC1_WAVE2_OUT;
wire UART0_CTSN;
wire UART0_DCDN;
wire UART0_DSRN;
wire UART0_DTRN;
wire UART0_RIN;
wire UART0_RTSN;
wire UART0_RX;
wire UART0_TX;
wire UART1_CTSN;
wire UART1_DCDN;
wire UART1_DSRN;
wire UART1_DTRN;
wire UART1_RIN;
wire UART1_RTSN;
wire UART1_RX;
wire UART1_TX;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire [1:0]USB1_PORT_INDCTL;
wire USB1_VBUS_PWRFAULT;
wire USB1_VBUS_PWRSELECT;
wire WDT_CLK_IN;
wire WDT_RST_OUT;
wire [14:0]buffered_DDR_Addr;
wire [2:0]buffered_DDR_BankAddr;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_CS_n;
wire buffered_DDR_Clk;
wire buffered_DDR_Clk_n;
wire [3:0]buffered_DDR_DM;
wire [31:0]buffered_DDR_DQ;
wire [3:0]buffered_DDR_DQS;
wire [3:0]buffered_DDR_DQS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire buffered_DDR_WEB;
wire [53:0]buffered_MIO;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire buffered_PS_SRSTB;
wire [63:0]gpio_out_t_n;
wire NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED;
wire NLW_PS7_i_EMIOTRACECTL_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED;
wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED;
assign ENET0_GMII_TXD[7] = \<const0> ;
assign ENET0_GMII_TXD[6] = \<const0> ;
assign ENET0_GMII_TXD[5] = \<const0> ;
assign ENET0_GMII_TXD[4] = \<const0> ;
assign ENET0_GMII_TXD[3] = \<const0> ;
assign ENET0_GMII_TXD[2] = \<const0> ;
assign ENET0_GMII_TXD[1] = \<const0> ;
assign ENET0_GMII_TXD[0] = \<const0> ;
assign ENET0_GMII_TX_EN = \<const0> ;
assign ENET0_GMII_TX_ER = \<const0> ;
assign ENET1_GMII_TXD[7] = \<const0> ;
assign ENET1_GMII_TXD[6] = \<const0> ;
assign ENET1_GMII_TXD[5] = \<const0> ;
assign ENET1_GMII_TXD[4] = \<const0> ;
assign ENET1_GMII_TXD[3] = \<const0> ;
assign ENET1_GMII_TXD[2] = \<const0> ;
assign ENET1_GMII_TXD[1] = \<const0> ;
assign ENET1_GMII_TXD[0] = \<const0> ;
assign ENET1_GMII_TX_EN = \<const0> ;
assign ENET1_GMII_TX_ER = \<const0> ;
assign M_AXI_GP0_ARCACHE[3:2] = \^M_AXI_GP0_ARCACHE [3:2];
assign M_AXI_GP0_ARCACHE[1] = \<const1> ;
assign M_AXI_GP0_ARCACHE[0] = \^M_AXI_GP0_ARCACHE [0];
assign M_AXI_GP0_ARSIZE[2] = \<const0> ;
assign M_AXI_GP0_ARSIZE[1:0] = \^M_AXI_GP0_ARSIZE [1:0];
assign M_AXI_GP0_AWCACHE[3:2] = \^M_AXI_GP0_AWCACHE [3:2];
assign M_AXI_GP0_AWCACHE[1] = \<const1> ;
assign M_AXI_GP0_AWCACHE[0] = \^M_AXI_GP0_AWCACHE [0];
assign M_AXI_GP0_AWSIZE[2] = \<const0> ;
assign M_AXI_GP0_AWSIZE[1:0] = \^M_AXI_GP0_AWSIZE [1:0];
assign M_AXI_GP1_ARCACHE[3:2] = \^M_AXI_GP1_ARCACHE [3:2];
assign M_AXI_GP1_ARCACHE[1] = \<const1> ;
assign M_AXI_GP1_ARCACHE[0] = \^M_AXI_GP1_ARCACHE [0];
assign M_AXI_GP1_ARSIZE[2] = \<const0> ;
assign M_AXI_GP1_ARSIZE[1:0] = \^M_AXI_GP1_ARSIZE [1:0];
assign M_AXI_GP1_AWCACHE[3:2] = \^M_AXI_GP1_AWCACHE [3:2];
assign M_AXI_GP1_AWCACHE[1] = \<const1> ;
assign M_AXI_GP1_AWCACHE[0] = \^M_AXI_GP1_AWCACHE [0];
assign M_AXI_GP1_AWSIZE[2] = \<const0> ;
assign M_AXI_GP1_AWSIZE[1:0] = \^M_AXI_GP1_AWSIZE [1:0];
assign PJTAG_TDO = \<const0> ;
assign TRACE_CLK_OUT = \<const0> ;
assign TRACE_CTL = \TRACE_CTL_PIPE[0] ;
assign TRACE_DATA[1:0] = \TRACE_DATA_PIPE[0] ;
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CAS_n_BIBUF
(.IO(buffered_DDR_CAS_n),
.PAD(DDR_CAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CKE_BIBUF
(.IO(buffered_DDR_CKE),
.PAD(DDR_CKE));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CS_n_BIBUF
(.IO(buffered_DDR_CS_n),
.PAD(DDR_CS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_BIBUF
(.IO(buffered_DDR_Clk),
.PAD(DDR_Clk));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_n_BIBUF
(.IO(buffered_DDR_Clk_n),
.PAD(DDR_Clk_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_DRSTB_BIBUF
(.IO(buffered_DDR_DRSTB),
.PAD(DDR_DRSTB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_ODT_BIBUF
(.IO(buffered_DDR_ODT),
.PAD(DDR_ODT));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_RAS_n_BIBUF
(.IO(buffered_DDR_RAS_n),
.PAD(DDR_RAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRN_BIBUF
(.IO(buffered_DDR_VRN),
.PAD(DDR_VRN));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRP_BIBUF
(.IO(buffered_DDR_VRP),
.PAD(DDR_VRP));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_WEB_BIBUF
(.IO(buffered_DDR_WEB),
.PAD(DDR_WEB));
LUT1 #(
.INIT(2'h1))
ENET0_MDIO_T_INST_0
(.I0(ENET0_MDIO_T_n),
.O(ENET0_MDIO_T));
LUT1 #(
.INIT(2'h1))
ENET1_MDIO_T_INST_0
(.I0(ENET1_MDIO_T_n),
.O(ENET1_MDIO_T));
GND GND
(.G(\<const0> ));
LUT1 #(
.INIT(2'h1))
\GPIO_T[0]_INST_0
(.I0(gpio_out_t_n[0]),
.O(GPIO_T[0]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[10]_INST_0
(.I0(gpio_out_t_n[10]),
.O(GPIO_T[10]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[11]_INST_0
(.I0(gpio_out_t_n[11]),
.O(GPIO_T[11]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[12]_INST_0
(.I0(gpio_out_t_n[12]),
.O(GPIO_T[12]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[13]_INST_0
(.I0(gpio_out_t_n[13]),
.O(GPIO_T[13]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[14]_INST_0
(.I0(gpio_out_t_n[14]),
.O(GPIO_T[14]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[15]_INST_0
(.I0(gpio_out_t_n[15]),
.O(GPIO_T[15]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[16]_INST_0
(.I0(gpio_out_t_n[16]),
.O(GPIO_T[16]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[17]_INST_0
(.I0(gpio_out_t_n[17]),
.O(GPIO_T[17]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[18]_INST_0
(.I0(gpio_out_t_n[18]),
.O(GPIO_T[18]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[19]_INST_0
(.I0(gpio_out_t_n[19]),
.O(GPIO_T[19]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[1]_INST_0
(.I0(gpio_out_t_n[1]),
.O(GPIO_T[1]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[20]_INST_0
(.I0(gpio_out_t_n[20]),
.O(GPIO_T[20]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[21]_INST_0
(.I0(gpio_out_t_n[21]),
.O(GPIO_T[21]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[22]_INST_0
(.I0(gpio_out_t_n[22]),
.O(GPIO_T[22]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[23]_INST_0
(.I0(gpio_out_t_n[23]),
.O(GPIO_T[23]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[24]_INST_0
(.I0(gpio_out_t_n[24]),
.O(GPIO_T[24]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[25]_INST_0
(.I0(gpio_out_t_n[25]),
.O(GPIO_T[25]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[26]_INST_0
(.I0(gpio_out_t_n[26]),
.O(GPIO_T[26]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[27]_INST_0
(.I0(gpio_out_t_n[27]),
.O(GPIO_T[27]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[28]_INST_0
(.I0(gpio_out_t_n[28]),
.O(GPIO_T[28]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[29]_INST_0
(.I0(gpio_out_t_n[29]),
.O(GPIO_T[29]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[2]_INST_0
(.I0(gpio_out_t_n[2]),
.O(GPIO_T[2]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[30]_INST_0
(.I0(gpio_out_t_n[30]),
.O(GPIO_T[30]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[31]_INST_0
(.I0(gpio_out_t_n[31]),
.O(GPIO_T[31]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[32]_INST_0
(.I0(gpio_out_t_n[32]),
.O(GPIO_T[32]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[33]_INST_0
(.I0(gpio_out_t_n[33]),
.O(GPIO_T[33]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[34]_INST_0
(.I0(gpio_out_t_n[34]),
.O(GPIO_T[34]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[35]_INST_0
(.I0(gpio_out_t_n[35]),
.O(GPIO_T[35]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[36]_INST_0
(.I0(gpio_out_t_n[36]),
.O(GPIO_T[36]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[37]_INST_0
(.I0(gpio_out_t_n[37]),
.O(GPIO_T[37]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[38]_INST_0
(.I0(gpio_out_t_n[38]),
.O(GPIO_T[38]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[39]_INST_0
(.I0(gpio_out_t_n[39]),
.O(GPIO_T[39]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[3]_INST_0
(.I0(gpio_out_t_n[3]),
.O(GPIO_T[3]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[40]_INST_0
(.I0(gpio_out_t_n[40]),
.O(GPIO_T[40]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[41]_INST_0
(.I0(gpio_out_t_n[41]),
.O(GPIO_T[41]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[42]_INST_0
(.I0(gpio_out_t_n[42]),
.O(GPIO_T[42]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[43]_INST_0
(.I0(gpio_out_t_n[43]),
.O(GPIO_T[43]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[44]_INST_0
(.I0(gpio_out_t_n[44]),
.O(GPIO_T[44]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[45]_INST_0
(.I0(gpio_out_t_n[45]),
.O(GPIO_T[45]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[46]_INST_0
(.I0(gpio_out_t_n[46]),
.O(GPIO_T[46]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[47]_INST_0
(.I0(gpio_out_t_n[47]),
.O(GPIO_T[47]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[48]_INST_0
(.I0(gpio_out_t_n[48]),
.O(GPIO_T[48]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[49]_INST_0
(.I0(gpio_out_t_n[49]),
.O(GPIO_T[49]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[4]_INST_0
(.I0(gpio_out_t_n[4]),
.O(GPIO_T[4]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[50]_INST_0
(.I0(gpio_out_t_n[50]),
.O(GPIO_T[50]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[51]_INST_0
(.I0(gpio_out_t_n[51]),
.O(GPIO_T[51]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[52]_INST_0
(.I0(gpio_out_t_n[52]),
.O(GPIO_T[52]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[53]_INST_0
(.I0(gpio_out_t_n[53]),
.O(GPIO_T[53]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[54]_INST_0
(.I0(gpio_out_t_n[54]),
.O(GPIO_T[54]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[55]_INST_0
(.I0(gpio_out_t_n[55]),
.O(GPIO_T[55]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[56]_INST_0
(.I0(gpio_out_t_n[56]),
.O(GPIO_T[56]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[57]_INST_0
(.I0(gpio_out_t_n[57]),
.O(GPIO_T[57]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[58]_INST_0
(.I0(gpio_out_t_n[58]),
.O(GPIO_T[58]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[59]_INST_0
(.I0(gpio_out_t_n[59]),
.O(GPIO_T[59]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[5]_INST_0
(.I0(gpio_out_t_n[5]),
.O(GPIO_T[5]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[60]_INST_0
(.I0(gpio_out_t_n[60]),
.O(GPIO_T[60]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[61]_INST_0
(.I0(gpio_out_t_n[61]),
.O(GPIO_T[61]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[62]_INST_0
(.I0(gpio_out_t_n[62]),
.O(GPIO_T[62]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[63]_INST_0
(.I0(gpio_out_t_n[63]),
.O(GPIO_T[63]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[6]_INST_0
(.I0(gpio_out_t_n[6]),
.O(GPIO_T[6]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[7]_INST_0
(.I0(gpio_out_t_n[7]),
.O(GPIO_T[7]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[8]_INST_0
(.I0(gpio_out_t_n[8]),
.O(GPIO_T[8]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[9]_INST_0
(.I0(gpio_out_t_n[9]),
.O(GPIO_T[9]));
LUT1 #(
.INIT(2'h1))
I2C0_SCL_T_INST_0
(.I0(I2C0_SCL_T_n),
.O(I2C0_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C0_SDA_T_INST_0
(.I0(I2C0_SDA_T_n),
.O(I2C0_SDA_T));
LUT1 #(
.INIT(2'h1))
I2C1_SCL_T_INST_0
(.I0(I2C1_SCL_T_n),
.O(I2C1_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C1_SDA_T_INST_0
(.I0(I2C1_SDA_T_n),
.O(I2C1_SDA_T));
(* BOX_TYPE = "PRIMITIVE" *)
PS7 PS7_i
(.DDRA(buffered_DDR_Addr),
.DDRARB(DDR_ARB),
.DDRBA(buffered_DDR_BankAddr),
.DDRCASB(buffered_DDR_CAS_n),
.DDRCKE(buffered_DDR_CKE),
.DDRCKN(buffered_DDR_Clk_n),
.DDRCKP(buffered_DDR_Clk),
.DDRCSB(buffered_DDR_CS_n),
.DDRDM(buffered_DDR_DM),
.DDRDQ(buffered_DDR_DQ),
.DDRDQSN(buffered_DDR_DQS_n),
.DDRDQSP(buffered_DDR_DQS),
.DDRDRSTB(buffered_DDR_DRSTB),
.DDRODT(buffered_DDR_ODT),
.DDRRASB(buffered_DDR_RAS_n),
.DDRVRN(buffered_DDR_VRN),
.DDRVRP(buffered_DDR_VRP),
.DDRWEB(buffered_DDR_WEB),
.DMA0ACLK(DMA0_ACLK),
.DMA0DAREADY(DMA0_DAREADY),
.DMA0DATYPE(DMA0_DATYPE),
.DMA0DAVALID(DMA0_DAVALID),
.DMA0DRLAST(DMA0_DRLAST),
.DMA0DRREADY(DMA0_DRREADY),
.DMA0DRTYPE(DMA0_DRTYPE),
.DMA0DRVALID(DMA0_DRVALID),
.DMA0RSTN(DMA0_RSTN),
.DMA1ACLK(DMA1_ACLK),
.DMA1DAREADY(DMA1_DAREADY),
.DMA1DATYPE(DMA1_DATYPE),
.DMA1DAVALID(DMA1_DAVALID),
.DMA1DRLAST(DMA1_DRLAST),
.DMA1DRREADY(DMA1_DRREADY),
.DMA1DRTYPE(DMA1_DRTYPE),
.DMA1DRVALID(DMA1_DRVALID),
.DMA1RSTN(DMA1_RSTN),
.DMA2ACLK(DMA2_ACLK),
.DMA2DAREADY(DMA2_DAREADY),
.DMA2DATYPE(DMA2_DATYPE),
.DMA2DAVALID(DMA2_DAVALID),
.DMA2DRLAST(DMA2_DRLAST),
.DMA2DRREADY(DMA2_DRREADY),
.DMA2DRTYPE(DMA2_DRTYPE),
.DMA2DRVALID(DMA2_DRVALID),
.DMA2RSTN(DMA2_RSTN),
.DMA3ACLK(DMA3_ACLK),
.DMA3DAREADY(DMA3_DAREADY),
.DMA3DATYPE(DMA3_DATYPE),
.DMA3DAVALID(DMA3_DAVALID),
.DMA3DRLAST(DMA3_DRLAST),
.DMA3DRREADY(DMA3_DRREADY),
.DMA3DRTYPE(DMA3_DRTYPE),
.DMA3DRVALID(DMA3_DRVALID),
.DMA3RSTN(DMA3_RSTN),
.EMIOCAN0PHYRX(CAN0_PHY_RX),
.EMIOCAN0PHYTX(CAN0_PHY_TX),
.EMIOCAN1PHYRX(CAN1_PHY_RX),
.EMIOCAN1PHYTX(CAN1_PHY_TX),
.EMIOENET0EXTINTIN(ENET0_EXT_INTIN),
.EMIOENET0GMIICOL(1'b0),
.EMIOENET0GMIICRS(1'b0),
.EMIOENET0GMIIRXCLK(ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET0GMIIRXDV(1'b0),
.EMIOENET0GMIIRXER(1'b0),
.EMIOENET0GMIITXCLK(ENET0_GMII_TX_CLK),
.EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]),
.EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED),
.EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED),
.EMIOENET0MDIOI(ENET0_MDIO_I),
.EMIOENET0MDIOMDC(ENET0_MDIO_MDC),
.EMIOENET0MDIOO(ENET0_MDIO_O),
.EMIOENET0MDIOTN(ENET0_MDIO_T_n),
.EMIOENET0PTPDELAYREQRX(ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX(ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX(ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX(ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX(ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX(ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX(ENET0_SOF_RX),
.EMIOENET0SOFTX(ENET0_SOF_TX),
.EMIOENET1EXTINTIN(ENET1_EXT_INTIN),
.EMIOENET1GMIICOL(1'b0),
.EMIOENET1GMIICRS(1'b0),
.EMIOENET1GMIIRXCLK(ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET1GMIIRXDV(1'b0),
.EMIOENET1GMIIRXER(1'b0),
.EMIOENET1GMIITXCLK(ENET1_GMII_TX_CLK),
.EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]),
.EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED),
.EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED),
.EMIOENET1MDIOI(ENET1_MDIO_I),
.EMIOENET1MDIOMDC(ENET1_MDIO_MDC),
.EMIOENET1MDIOO(ENET1_MDIO_O),
.EMIOENET1MDIOTN(ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX(ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX(ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX(ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX(ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX(ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX(ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX(ENET1_SOF_RX),
.EMIOENET1SOFTX(ENET1_SOF_TX),
.EMIOGPIOI(GPIO_I),
.EMIOGPIOO(GPIO_O),
.EMIOGPIOTN(gpio_out_t_n),
.EMIOI2C0SCLI(I2C0_SCL_I),
.EMIOI2C0SCLO(I2C0_SCL_O),
.EMIOI2C0SCLTN(I2C0_SCL_T_n),
.EMIOI2C0SDAI(I2C0_SDA_I),
.EMIOI2C0SDAO(I2C0_SDA_O),
.EMIOI2C0SDATN(I2C0_SDA_T_n),
.EMIOI2C1SCLI(I2C1_SCL_I),
.EMIOI2C1SCLO(I2C1_SCL_O),
.EMIOI2C1SCLTN(I2C1_SCL_T_n),
.EMIOI2C1SDAI(I2C1_SDA_I),
.EMIOI2C1SDAO(I2C1_SDA_O),
.EMIOI2C1SDATN(I2C1_SDA_T_n),
.EMIOPJTAGTCK(PJTAG_TCK),
.EMIOPJTAGTDI(PJTAG_TDI),
.EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED),
.EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED),
.EMIOPJTAGTMS(PJTAG_TMS),
.EMIOSDIO0BUSPOW(SDIO0_BUSPOW),
.EMIOSDIO0BUSVOLT(SDIO0_BUSVOLT),
.EMIOSDIO0CDN(SDIO0_CDN),
.EMIOSDIO0CLK(SDIO0_CLK),
.EMIOSDIO0CLKFB(SDIO0_CLK_FB),
.EMIOSDIO0CMDI(SDIO0_CMD_I),
.EMIOSDIO0CMDO(SDIO0_CMD_O),
.EMIOSDIO0CMDTN(SDIO0_CMD_T_n),
.EMIOSDIO0DATAI(SDIO0_DATA_I),
.EMIOSDIO0DATAO(SDIO0_DATA_O),
.EMIOSDIO0DATATN(SDIO0_DATA_T_n),
.EMIOSDIO0LED(SDIO0_LED),
.EMIOSDIO0WP(SDIO0_WP),
.EMIOSDIO1BUSPOW(SDIO1_BUSPOW),
.EMIOSDIO1BUSVOLT(SDIO1_BUSVOLT),
.EMIOSDIO1CDN(SDIO1_CDN),
.EMIOSDIO1CLK(SDIO1_CLK),
.EMIOSDIO1CLKFB(SDIO1_CLK_FB),
.EMIOSDIO1CMDI(SDIO1_CMD_I),
.EMIOSDIO1CMDO(SDIO1_CMD_O),
.EMIOSDIO1CMDTN(SDIO1_CMD_T_n),
.EMIOSDIO1DATAI(SDIO1_DATA_I),
.EMIOSDIO1DATAO(SDIO1_DATA_O),
.EMIOSDIO1DATATN(SDIO1_DATA_T_n),
.EMIOSDIO1LED(SDIO1_LED),
.EMIOSDIO1WP(SDIO1_WP),
.EMIOSPI0MI(SPI0_MISO_I),
.EMIOSPI0MO(SPI0_MOSI_O),
.EMIOSPI0MOTN(SPI0_MOSI_T_n),
.EMIOSPI0SCLKI(SPI0_SCLK_I),
.EMIOSPI0SCLKO(SPI0_SCLK_O),
.EMIOSPI0SCLKTN(SPI0_SCLK_T_n),
.EMIOSPI0SI(SPI0_MOSI_I),
.EMIOSPI0SO(SPI0_MISO_O),
.EMIOSPI0SSIN(SPI0_SS_I),
.EMIOSPI0SSNTN(SPI0_SS_T_n),
.EMIOSPI0SSON({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0STN(SPI0_MISO_T_n),
.EMIOSPI1MI(SPI1_MISO_I),
.EMIOSPI1MO(SPI1_MOSI_O),
.EMIOSPI1MOTN(SPI1_MOSI_T_n),
.EMIOSPI1SCLKI(SPI1_SCLK_I),
.EMIOSPI1SCLKO(SPI1_SCLK_O),
.EMIOSPI1SCLKTN(SPI1_SCLK_T_n),
.EMIOSPI1SI(SPI1_MOSI_I),
.EMIOSPI1SO(SPI1_MISO_O),
.EMIOSPI1SSIN(SPI1_SS_I),
.EMIOSPI1SSNTN(SPI1_SS_T_n),
.EMIOSPI1SSON({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1STN(SPI1_MISO_T_n),
.EMIOSRAMINTIN(SRAM_INTIN),
.EMIOTRACECLK(TRACE_CLK),
.EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED),
.EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]),
.EMIOTTC0CLKI({TTC0_CLK2_IN,TTC0_CLK1_IN,TTC0_CLK0_IN}),
.EMIOTTC0WAVEO({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1CLKI({TTC1_CLK2_IN,TTC1_CLK1_IN,TTC1_CLK0_IN}),
.EMIOTTC1WAVEO({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0CTSN(UART0_CTSN),
.EMIOUART0DCDN(UART0_DCDN),
.EMIOUART0DSRN(UART0_DSRN),
.EMIOUART0DTRN(UART0_DTRN),
.EMIOUART0RIN(UART0_RIN),
.EMIOUART0RTSN(UART0_RTSN),
.EMIOUART0RX(UART0_RX),
.EMIOUART0TX(UART0_TX),
.EMIOUART1CTSN(UART1_CTSN),
.EMIOUART1DCDN(UART1_DCDN),
.EMIOUART1DSRN(UART1_DSRN),
.EMIOUART1DTRN(UART1_DTRN),
.EMIOUART1RIN(UART1_RIN),
.EMIOUART1RTSN(UART1_RTSN),
.EMIOUART1RX(UART1_RX),
.EMIOUART1TX(UART1_TX),
.EMIOUSB0PORTINDCTL(USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRFAULT(USB0_VBUS_PWRFAULT),
.EMIOUSB0VBUSPWRSELECT(USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL(USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRFAULT(USB1_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRSELECT(USB1_VBUS_PWRSELECT),
.EMIOWDTCLKI(WDT_CLK_IN),
.EMIOWDTRSTO(WDT_RST_OUT),
.EVENTEVENTI(EVENT_EVENTI),
.EVENTEVENTO(EVENT_EVENTO),
.EVENTSTANDBYWFE(EVENT_STANDBYWFE),
.EVENTSTANDBYWFI(EVENT_STANDBYWFI),
.FCLKCLK({FCLK_CLK3,FCLK_CLK2,FCLK_CLK_unbuffered}),
.FCLKCLKTRIGN({1'b0,1'b0,1'b0,1'b0}),
.FCLKRESETN({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.FPGAIDLEN(FPGA_IDLE_N),
.FTMDTRACEINATID({1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINCLOCK(FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINVALID(1'b0),
.FTMTF2PDEBUG(FTMT_F2P_DEBUG),
.FTMTF2PTRIG({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTF2PTRIGACK({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG(FTMT_P2F_DEBUG),
.FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,IRQ_F2P}),
.IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}),
.MAXIGP0ACLK(M_AXI_GP0_ACLK),
.MAXIGP0ARADDR(M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST(M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE(\^M_AXI_GP0_ARCACHE ),
.MAXIGP0ARESETN(M_AXI_GP0_ARESETN),
.MAXIGP0ARID(M_AXI_GP0_ARID),
.MAXIGP0ARLEN(M_AXI_GP0_ARLEN),
.MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK),
.MAXIGP0ARPROT(M_AXI_GP0_ARPROT),
.MAXIGP0ARQOS(M_AXI_GP0_ARQOS),
.MAXIGP0ARREADY(M_AXI_GP0_ARREADY),
.MAXIGP0ARSIZE(\^M_AXI_GP0_ARSIZE ),
.MAXIGP0ARVALID(M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR(M_AXI_GP0_AWADDR),
.MAXIGP0AWBURST(M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE(\^M_AXI_GP0_AWCACHE ),
.MAXIGP0AWID(M_AXI_GP0_AWID),
.MAXIGP0AWLEN(M_AXI_GP0_AWLEN),
.MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK),
.MAXIGP0AWPROT(M_AXI_GP0_AWPROT),
.MAXIGP0AWQOS(M_AXI_GP0_AWQOS),
.MAXIGP0AWREADY(M_AXI_GP0_AWREADY),
.MAXIGP0AWSIZE(\^M_AXI_GP0_AWSIZE ),
.MAXIGP0AWVALID(M_AXI_GP0_AWVALID),
.MAXIGP0BID(M_AXI_GP0_BID),
.MAXIGP0BREADY(M_AXI_GP0_BREADY),
.MAXIGP0BRESP(M_AXI_GP0_BRESP),
.MAXIGP0BVALID(M_AXI_GP0_BVALID),
.MAXIGP0RDATA(M_AXI_GP0_RDATA),
.MAXIGP0RID(M_AXI_GP0_RID),
.MAXIGP0RLAST(M_AXI_GP0_RLAST),
.MAXIGP0RREADY(M_AXI_GP0_RREADY),
.MAXIGP0RRESP(M_AXI_GP0_RRESP),
.MAXIGP0RVALID(M_AXI_GP0_RVALID),
.MAXIGP0WDATA(M_AXI_GP0_WDATA),
.MAXIGP0WID(M_AXI_GP0_WID),
.MAXIGP0WLAST(M_AXI_GP0_WLAST),
.MAXIGP0WREADY(M_AXI_GP0_WREADY),
.MAXIGP0WSTRB(M_AXI_GP0_WSTRB),
.MAXIGP0WVALID(M_AXI_GP0_WVALID),
.MAXIGP1ACLK(M_AXI_GP1_ACLK),
.MAXIGP1ARADDR(M_AXI_GP1_ARADDR),
.MAXIGP1ARBURST(M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE(\^M_AXI_GP1_ARCACHE ),
.MAXIGP1ARESETN(M_AXI_GP1_ARESETN),
.MAXIGP1ARID(M_AXI_GP1_ARID),
.MAXIGP1ARLEN(M_AXI_GP1_ARLEN),
.MAXIGP1ARLOCK(M_AXI_GP1_ARLOCK),
.MAXIGP1ARPROT(M_AXI_GP1_ARPROT),
.MAXIGP1ARQOS(M_AXI_GP1_ARQOS),
.MAXIGP1ARREADY(M_AXI_GP1_ARREADY),
.MAXIGP1ARSIZE(\^M_AXI_GP1_ARSIZE ),
.MAXIGP1ARVALID(M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR(M_AXI_GP1_AWADDR),
.MAXIGP1AWBURST(M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE(\^M_AXI_GP1_AWCACHE ),
.MAXIGP1AWID(M_AXI_GP1_AWID),
.MAXIGP1AWLEN(M_AXI_GP1_AWLEN),
.MAXIGP1AWLOCK(M_AXI_GP1_AWLOCK),
.MAXIGP1AWPROT(M_AXI_GP1_AWPROT),
.MAXIGP1AWQOS(M_AXI_GP1_AWQOS),
.MAXIGP1AWREADY(M_AXI_GP1_AWREADY),
.MAXIGP1AWSIZE(\^M_AXI_GP1_AWSIZE ),
.MAXIGP1AWVALID(M_AXI_GP1_AWVALID),
.MAXIGP1BID(M_AXI_GP1_BID),
.MAXIGP1BREADY(M_AXI_GP1_BREADY),
.MAXIGP1BRESP(M_AXI_GP1_BRESP),
.MAXIGP1BVALID(M_AXI_GP1_BVALID),
.MAXIGP1RDATA(M_AXI_GP1_RDATA),
.MAXIGP1RID(M_AXI_GP1_RID),
.MAXIGP1RLAST(M_AXI_GP1_RLAST),
.MAXIGP1RREADY(M_AXI_GP1_RREADY),
.MAXIGP1RRESP(M_AXI_GP1_RRESP),
.MAXIGP1RVALID(M_AXI_GP1_RVALID),
.MAXIGP1WDATA(M_AXI_GP1_WDATA),
.MAXIGP1WID(M_AXI_GP1_WID),
.MAXIGP1WLAST(M_AXI_GP1_WLAST),
.MAXIGP1WREADY(M_AXI_GP1_WREADY),
.MAXIGP1WSTRB(M_AXI_GP1_WSTRB),
.MAXIGP1WVALID(M_AXI_GP1_WVALID),
.MIO(buffered_MIO),
.PSCLK(buffered_PS_CLK),
.PSPORB(buffered_PS_PORB),
.PSSRSTB(buffered_PS_SRSTB),
.SAXIACPACLK(S_AXI_ACP_ACLK),
.SAXIACPARADDR(S_AXI_ACP_ARADDR),
.SAXIACPARBURST(S_AXI_ACP_ARBURST),
.SAXIACPARCACHE(S_AXI_ACP_ARCACHE),
.SAXIACPARESETN(S_AXI_ACP_ARESETN),
.SAXIACPARID(S_AXI_ACP_ARID),
.SAXIACPARLEN(S_AXI_ACP_ARLEN),
.SAXIACPARLOCK(S_AXI_ACP_ARLOCK),
.SAXIACPARPROT(S_AXI_ACP_ARPROT),
.SAXIACPARQOS(S_AXI_ACP_ARQOS),
.SAXIACPARREADY(S_AXI_ACP_ARREADY),
.SAXIACPARSIZE(S_AXI_ACP_ARSIZE[1:0]),
.SAXIACPARUSER(S_AXI_ACP_ARUSER),
.SAXIACPARVALID(S_AXI_ACP_ARVALID),
.SAXIACPAWADDR(S_AXI_ACP_AWADDR),
.SAXIACPAWBURST(S_AXI_ACP_AWBURST),
.SAXIACPAWCACHE(S_AXI_ACP_AWCACHE),
.SAXIACPAWID(S_AXI_ACP_AWID),
.SAXIACPAWLEN(S_AXI_ACP_AWLEN),
.SAXIACPAWLOCK(S_AXI_ACP_AWLOCK),
.SAXIACPAWPROT(S_AXI_ACP_AWPROT),
.SAXIACPAWQOS(S_AXI_ACP_AWQOS),
.SAXIACPAWREADY(S_AXI_ACP_AWREADY),
.SAXIACPAWSIZE(S_AXI_ACP_AWSIZE[1:0]),
.SAXIACPAWUSER(S_AXI_ACP_AWUSER),
.SAXIACPAWVALID(S_AXI_ACP_AWVALID),
.SAXIACPBID(S_AXI_ACP_BID),
.SAXIACPBREADY(S_AXI_ACP_BREADY),
.SAXIACPBRESP(S_AXI_ACP_BRESP),
.SAXIACPBVALID(S_AXI_ACP_BVALID),
.SAXIACPRDATA(S_AXI_ACP_RDATA),
.SAXIACPRID(S_AXI_ACP_RID),
.SAXIACPRLAST(S_AXI_ACP_RLAST),
.SAXIACPRREADY(S_AXI_ACP_RREADY),
.SAXIACPRRESP(S_AXI_ACP_RRESP),
.SAXIACPRVALID(S_AXI_ACP_RVALID),
.SAXIACPWDATA(S_AXI_ACP_WDATA),
.SAXIACPWID(S_AXI_ACP_WID),
.SAXIACPWLAST(S_AXI_ACP_WLAST),
.SAXIACPWREADY(S_AXI_ACP_WREADY),
.SAXIACPWSTRB(S_AXI_ACP_WSTRB),
.SAXIACPWVALID(S_AXI_ACP_WVALID),
.SAXIGP0ACLK(S_AXI_GP0_ACLK),
.SAXIGP0ARADDR(S_AXI_GP0_ARADDR),
.SAXIGP0ARBURST(S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE(S_AXI_GP0_ARCACHE),
.SAXIGP0ARESETN(S_AXI_GP0_ARESETN),
.SAXIGP0ARID(S_AXI_GP0_ARID),
.SAXIGP0ARLEN(S_AXI_GP0_ARLEN),
.SAXIGP0ARLOCK(S_AXI_GP0_ARLOCK),
.SAXIGP0ARPROT(S_AXI_GP0_ARPROT),
.SAXIGP0ARQOS(S_AXI_GP0_ARQOS),
.SAXIGP0ARREADY(S_AXI_GP0_ARREADY),
.SAXIGP0ARSIZE(S_AXI_GP0_ARSIZE[1:0]),
.SAXIGP0ARVALID(S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR(S_AXI_GP0_AWADDR),
.SAXIGP0AWBURST(S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE(S_AXI_GP0_AWCACHE),
.SAXIGP0AWID(S_AXI_GP0_AWID),
.SAXIGP0AWLEN(S_AXI_GP0_AWLEN),
.SAXIGP0AWLOCK(S_AXI_GP0_AWLOCK),
.SAXIGP0AWPROT(S_AXI_GP0_AWPROT),
.SAXIGP0AWQOS(S_AXI_GP0_AWQOS),
.SAXIGP0AWREADY(S_AXI_GP0_AWREADY),
.SAXIGP0AWSIZE(S_AXI_GP0_AWSIZE[1:0]),
.SAXIGP0AWVALID(S_AXI_GP0_AWVALID),
.SAXIGP0BID(S_AXI_GP0_BID),
.SAXIGP0BREADY(S_AXI_GP0_BREADY),
.SAXIGP0BRESP(S_AXI_GP0_BRESP),
.SAXIGP0BVALID(S_AXI_GP0_BVALID),
.SAXIGP0RDATA(S_AXI_GP0_RDATA),
.SAXIGP0RID(S_AXI_GP0_RID),
.SAXIGP0RLAST(S_AXI_GP0_RLAST),
.SAXIGP0RREADY(S_AXI_GP0_RREADY),
.SAXIGP0RRESP(S_AXI_GP0_RRESP),
.SAXIGP0RVALID(S_AXI_GP0_RVALID),
.SAXIGP0WDATA(S_AXI_GP0_WDATA),
.SAXIGP0WID(S_AXI_GP0_WID),
.SAXIGP0WLAST(S_AXI_GP0_WLAST),
.SAXIGP0WREADY(S_AXI_GP0_WREADY),
.SAXIGP0WSTRB(S_AXI_GP0_WSTRB),
.SAXIGP0WVALID(S_AXI_GP0_WVALID),
.SAXIGP1ACLK(S_AXI_GP1_ACLK),
.SAXIGP1ARADDR(S_AXI_GP1_ARADDR),
.SAXIGP1ARBURST(S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE(S_AXI_GP1_ARCACHE),
.SAXIGP1ARESETN(S_AXI_GP1_ARESETN),
.SAXIGP1ARID(S_AXI_GP1_ARID),
.SAXIGP1ARLEN(S_AXI_GP1_ARLEN),
.SAXIGP1ARLOCK(S_AXI_GP1_ARLOCK),
.SAXIGP1ARPROT(S_AXI_GP1_ARPROT),
.SAXIGP1ARQOS(S_AXI_GP1_ARQOS),
.SAXIGP1ARREADY(S_AXI_GP1_ARREADY),
.SAXIGP1ARSIZE(S_AXI_GP1_ARSIZE[1:0]),
.SAXIGP1ARVALID(S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR(S_AXI_GP1_AWADDR),
.SAXIGP1AWBURST(S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE(S_AXI_GP1_AWCACHE),
.SAXIGP1AWID(S_AXI_GP1_AWID),
.SAXIGP1AWLEN(S_AXI_GP1_AWLEN),
.SAXIGP1AWLOCK(S_AXI_GP1_AWLOCK),
.SAXIGP1AWPROT(S_AXI_GP1_AWPROT),
.SAXIGP1AWQOS(S_AXI_GP1_AWQOS),
.SAXIGP1AWREADY(S_AXI_GP1_AWREADY),
.SAXIGP1AWSIZE(S_AXI_GP1_AWSIZE[1:0]),
.SAXIGP1AWVALID(S_AXI_GP1_AWVALID),
.SAXIGP1BID(S_AXI_GP1_BID),
.SAXIGP1BREADY(S_AXI_GP1_BREADY),
.SAXIGP1BRESP(S_AXI_GP1_BRESP),
.SAXIGP1BVALID(S_AXI_GP1_BVALID),
.SAXIGP1RDATA(S_AXI_GP1_RDATA),
.SAXIGP1RID(S_AXI_GP1_RID),
.SAXIGP1RLAST(S_AXI_GP1_RLAST),
.SAXIGP1RREADY(S_AXI_GP1_RREADY),
.SAXIGP1RRESP(S_AXI_GP1_RRESP),
.SAXIGP1RVALID(S_AXI_GP1_RVALID),
.SAXIGP1WDATA(S_AXI_GP1_WDATA),
.SAXIGP1WID(S_AXI_GP1_WID),
.SAXIGP1WLAST(S_AXI_GP1_WLAST),
.SAXIGP1WREADY(S_AXI_GP1_WREADY),
.SAXIGP1WSTRB(S_AXI_GP1_WSTRB),
.SAXIGP1WVALID(S_AXI_GP1_WVALID),
.SAXIHP0ACLK(S_AXI_HP0_ACLK),
.SAXIHP0ARADDR(S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST(S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE(S_AXI_HP0_ARCACHE),
.SAXIHP0ARESETN(S_AXI_HP0_ARESETN),
.SAXIHP0ARID(S_AXI_HP0_ARID),
.SAXIHP0ARLEN(S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK(S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT(S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS(S_AXI_HP0_ARQOS),
.SAXIHP0ARREADY(S_AXI_HP0_ARREADY),
.SAXIHP0ARSIZE(S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID(S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR(S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST(S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE(S_AXI_HP0_AWCACHE),
.SAXIHP0AWID(S_AXI_HP0_AWID),
.SAXIHP0AWLEN(S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK(S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT(S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS(S_AXI_HP0_AWQOS),
.SAXIHP0AWREADY(S_AXI_HP0_AWREADY),
.SAXIHP0AWSIZE(S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID(S_AXI_HP0_AWVALID),
.SAXIHP0BID(S_AXI_HP0_BID),
.SAXIHP0BREADY(S_AXI_HP0_BREADY),
.SAXIHP0BRESP(S_AXI_HP0_BRESP),
.SAXIHP0BVALID(S_AXI_HP0_BVALID),
.SAXIHP0RACOUNT(S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT(S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA(S_AXI_HP0_RDATA),
.SAXIHP0RDISSUECAP1EN(S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RID(S_AXI_HP0_RID),
.SAXIHP0RLAST(S_AXI_HP0_RLAST),
.SAXIHP0RREADY(S_AXI_HP0_RREADY),
.SAXIHP0RRESP(S_AXI_HP0_RRESP),
.SAXIHP0RVALID(S_AXI_HP0_RVALID),
.SAXIHP0WACOUNT(S_AXI_HP0_WACOUNT),
.SAXIHP0WCOUNT(S_AXI_HP0_WCOUNT),
.SAXIHP0WDATA(S_AXI_HP0_WDATA),
.SAXIHP0WID(S_AXI_HP0_WID),
.SAXIHP0WLAST(S_AXI_HP0_WLAST),
.SAXIHP0WREADY(S_AXI_HP0_WREADY),
.SAXIHP0WRISSUECAP1EN(S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB(S_AXI_HP0_WSTRB),
.SAXIHP0WVALID(S_AXI_HP0_WVALID),
.SAXIHP1ACLK(S_AXI_HP1_ACLK),
.SAXIHP1ARADDR(S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST(S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE(S_AXI_HP1_ARCACHE),
.SAXIHP1ARESETN(S_AXI_HP1_ARESETN),
.SAXIHP1ARID(S_AXI_HP1_ARID),
.SAXIHP1ARLEN(S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK(S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT(S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS(S_AXI_HP1_ARQOS),
.SAXIHP1ARREADY(S_AXI_HP1_ARREADY),
.SAXIHP1ARSIZE(S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID(S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR(S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST(S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE(S_AXI_HP1_AWCACHE),
.SAXIHP1AWID(S_AXI_HP1_AWID),
.SAXIHP1AWLEN(S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK(S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT(S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS(S_AXI_HP1_AWQOS),
.SAXIHP1AWREADY(S_AXI_HP1_AWREADY),
.SAXIHP1AWSIZE(S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID(S_AXI_HP1_AWVALID),
.SAXIHP1BID(S_AXI_HP1_BID),
.SAXIHP1BREADY(S_AXI_HP1_BREADY),
.SAXIHP1BRESP(S_AXI_HP1_BRESP),
.SAXIHP1BVALID(S_AXI_HP1_BVALID),
.SAXIHP1RACOUNT(S_AXI_HP1_RACOUNT),
.SAXIHP1RCOUNT(S_AXI_HP1_RCOUNT),
.SAXIHP1RDATA(S_AXI_HP1_RDATA),
.SAXIHP1RDISSUECAP1EN(S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RID(S_AXI_HP1_RID),
.SAXIHP1RLAST(S_AXI_HP1_RLAST),
.SAXIHP1RREADY(S_AXI_HP1_RREADY),
.SAXIHP1RRESP(S_AXI_HP1_RRESP),
.SAXIHP1RVALID(S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT(S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT(S_AXI_HP1_WCOUNT),
.SAXIHP1WDATA(S_AXI_HP1_WDATA),
.SAXIHP1WID(S_AXI_HP1_WID),
.SAXIHP1WLAST(S_AXI_HP1_WLAST),
.SAXIHP1WREADY(S_AXI_HP1_WREADY),
.SAXIHP1WRISSUECAP1EN(S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB(S_AXI_HP1_WSTRB),
.SAXIHP1WVALID(S_AXI_HP1_WVALID),
.SAXIHP2ACLK(S_AXI_HP2_ACLK),
.SAXIHP2ARADDR(S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST(S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE(S_AXI_HP2_ARCACHE),
.SAXIHP2ARESETN(S_AXI_HP2_ARESETN),
.SAXIHP2ARID(S_AXI_HP2_ARID),
.SAXIHP2ARLEN(S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK(S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT(S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS(S_AXI_HP2_ARQOS),
.SAXIHP2ARREADY(S_AXI_HP2_ARREADY),
.SAXIHP2ARSIZE(S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID(S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR(S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST(S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE(S_AXI_HP2_AWCACHE),
.SAXIHP2AWID(S_AXI_HP2_AWID),
.SAXIHP2AWLEN(S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK(S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT(S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS(S_AXI_HP2_AWQOS),
.SAXIHP2AWREADY(S_AXI_HP2_AWREADY),
.SAXIHP2AWSIZE(S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID(S_AXI_HP2_AWVALID),
.SAXIHP2BID(S_AXI_HP2_BID),
.SAXIHP2BREADY(S_AXI_HP2_BREADY),
.SAXIHP2BRESP(S_AXI_HP2_BRESP),
.SAXIHP2BVALID(S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT(S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT(S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA(S_AXI_HP2_RDATA),
.SAXIHP2RDISSUECAP1EN(S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RID(S_AXI_HP2_RID),
.SAXIHP2RLAST(S_AXI_HP2_RLAST),
.SAXIHP2RREADY(S_AXI_HP2_RREADY),
.SAXIHP2RRESP(S_AXI_HP2_RRESP),
.SAXIHP2RVALID(S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT(S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT(S_AXI_HP2_WCOUNT),
.SAXIHP2WDATA(S_AXI_HP2_WDATA),
.SAXIHP2WID(S_AXI_HP2_WID),
.SAXIHP2WLAST(S_AXI_HP2_WLAST),
.SAXIHP2WREADY(S_AXI_HP2_WREADY),
.SAXIHP2WRISSUECAP1EN(S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB(S_AXI_HP2_WSTRB),
.SAXIHP2WVALID(S_AXI_HP2_WVALID),
.SAXIHP3ACLK(S_AXI_HP3_ACLK),
.SAXIHP3ARADDR(S_AXI_HP3_ARADDR),
.SAXIHP3ARBURST(S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE(S_AXI_HP3_ARCACHE),
.SAXIHP3ARESETN(S_AXI_HP3_ARESETN),
.SAXIHP3ARID(S_AXI_HP3_ARID),
.SAXIHP3ARLEN(S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK(S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT(S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS(S_AXI_HP3_ARQOS),
.SAXIHP3ARREADY(S_AXI_HP3_ARREADY),
.SAXIHP3ARSIZE(S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID(S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR(S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST(S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE(S_AXI_HP3_AWCACHE),
.SAXIHP3AWID(S_AXI_HP3_AWID),
.SAXIHP3AWLEN(S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK(S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT(S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS(S_AXI_HP3_AWQOS),
.SAXIHP3AWREADY(S_AXI_HP3_AWREADY),
.SAXIHP3AWSIZE(S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID(S_AXI_HP3_AWVALID),
.SAXIHP3BID(S_AXI_HP3_BID),
.SAXIHP3BREADY(S_AXI_HP3_BREADY),
.SAXIHP3BRESP(S_AXI_HP3_BRESP),
.SAXIHP3BVALID(S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT(S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT(S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA(S_AXI_HP3_RDATA),
.SAXIHP3RDISSUECAP1EN(S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RID(S_AXI_HP3_RID),
.SAXIHP3RLAST(S_AXI_HP3_RLAST),
.SAXIHP3RREADY(S_AXI_HP3_RREADY),
.SAXIHP3RRESP(S_AXI_HP3_RRESP),
.SAXIHP3RVALID(S_AXI_HP3_RVALID),
.SAXIHP3WACOUNT(S_AXI_HP3_WACOUNT),
.SAXIHP3WCOUNT(S_AXI_HP3_WCOUNT),
.SAXIHP3WDATA(S_AXI_HP3_WDATA),
.SAXIHP3WID(S_AXI_HP3_WID),
.SAXIHP3WLAST(S_AXI_HP3_WLAST),
.SAXIHP3WREADY(S_AXI_HP3_WREADY),
.SAXIHP3WRISSUECAP1EN(S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB(S_AXI_HP3_WSTRB),
.SAXIHP3WVALID(S_AXI_HP3_WVALID));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_CLK_BIBUF
(.IO(buffered_PS_CLK),
.PAD(PS_CLK));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_PORB_BIBUF
(.IO(buffered_PS_PORB),
.PAD(PS_PORB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_SRSTB_BIBUF
(.IO(buffered_PS_SRSTB),
.PAD(PS_SRSTB));
LUT1 #(
.INIT(2'h1))
SDIO0_CMD_T_INST_0
(.I0(SDIO0_CMD_T_n),
.O(SDIO0_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[0]_INST_0
(.I0(SDIO0_DATA_T_n[0]),
.O(SDIO0_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[1]_INST_0
(.I0(SDIO0_DATA_T_n[1]),
.O(SDIO0_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[2]_INST_0
(.I0(SDIO0_DATA_T_n[2]),
.O(SDIO0_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[3]_INST_0
(.I0(SDIO0_DATA_T_n[3]),
.O(SDIO0_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SDIO1_CMD_T_INST_0
(.I0(SDIO1_CMD_T_n),
.O(SDIO1_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[0]_INST_0
(.I0(SDIO1_DATA_T_n[0]),
.O(SDIO1_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[1]_INST_0
(.I0(SDIO1_DATA_T_n[1]),
.O(SDIO1_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[2]_INST_0
(.I0(SDIO1_DATA_T_n[2]),
.O(SDIO1_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[3]_INST_0
(.I0(SDIO1_DATA_T_n[3]),
.O(SDIO1_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SPI0_MISO_T_INST_0
(.I0(SPI0_MISO_T_n),
.O(SPI0_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI0_MOSI_T_INST_0
(.I0(SPI0_MOSI_T_n),
.O(SPI0_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI0_SCLK_T_INST_0
(.I0(SPI0_SCLK_T_n),
.O(SPI0_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI0_SS_T_INST_0
(.I0(SPI0_SS_T_n),
.O(SPI0_SS_T));
LUT1 #(
.INIT(2'h1))
SPI1_MISO_T_INST_0
(.I0(SPI1_MISO_T_n),
.O(SPI1_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI1_MOSI_T_INST_0
(.I0(SPI1_MOSI_T_n),
.O(SPI1_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI1_SCLK_T_INST_0
(.I0(SPI1_SCLK_T_n),
.O(SPI1_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI1_SS_T_INST_0
(.I0(SPI1_SS_T_n),
.O(SPI1_SS_T));
VCC VCC
(.P(\<const1> ));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG \buffer_fclk_clk_0.FCLK_CLK_0_BUFG
(.I(FCLK_CLK_unbuffered[0]),
.O(FCLK_CLK0));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG \buffer_fclk_clk_1.FCLK_CLK_1_BUFG
(.I(FCLK_CLK_unbuffered[1]),
.O(FCLK_CLK1));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[0].MIO_BIBUF
(.IO(buffered_MIO[0]),
.PAD(MIO[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[10].MIO_BIBUF
(.IO(buffered_MIO[10]),
.PAD(MIO[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[11].MIO_BIBUF
(.IO(buffered_MIO[11]),
.PAD(MIO[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[12].MIO_BIBUF
(.IO(buffered_MIO[12]),
.PAD(MIO[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[13].MIO_BIBUF
(.IO(buffered_MIO[13]),
.PAD(MIO[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[14].MIO_BIBUF
(.IO(buffered_MIO[14]),
.PAD(MIO[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[15].MIO_BIBUF
(.IO(buffered_MIO[15]),
.PAD(MIO[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[16].MIO_BIBUF
(.IO(buffered_MIO[16]),
.PAD(MIO[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[17].MIO_BIBUF
(.IO(buffered_MIO[17]),
.PAD(MIO[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[18].MIO_BIBUF
(.IO(buffered_MIO[18]),
.PAD(MIO[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[19].MIO_BIBUF
(.IO(buffered_MIO[19]),
.PAD(MIO[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[1].MIO_BIBUF
(.IO(buffered_MIO[1]),
.PAD(MIO[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[20].MIO_BIBUF
(.IO(buffered_MIO[20]),
.PAD(MIO[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[21].MIO_BIBUF
(.IO(buffered_MIO[21]),
.PAD(MIO[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[22].MIO_BIBUF
(.IO(buffered_MIO[22]),
.PAD(MIO[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[23].MIO_BIBUF
(.IO(buffered_MIO[23]),
.PAD(MIO[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[24].MIO_BIBUF
(.IO(buffered_MIO[24]),
.PAD(MIO[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[25].MIO_BIBUF
(.IO(buffered_MIO[25]),
.PAD(MIO[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[26].MIO_BIBUF
(.IO(buffered_MIO[26]),
.PAD(MIO[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[27].MIO_BIBUF
(.IO(buffered_MIO[27]),
.PAD(MIO[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[28].MIO_BIBUF
(.IO(buffered_MIO[28]),
.PAD(MIO[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[29].MIO_BIBUF
(.IO(buffered_MIO[29]),
.PAD(MIO[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[2].MIO_BIBUF
(.IO(buffered_MIO[2]),
.PAD(MIO[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[30].MIO_BIBUF
(.IO(buffered_MIO[30]),
.PAD(MIO[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[31].MIO_BIBUF
(.IO(buffered_MIO[31]),
.PAD(MIO[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[32].MIO_BIBUF
(.IO(buffered_MIO[32]),
.PAD(MIO[32]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[33].MIO_BIBUF
(.IO(buffered_MIO[33]),
.PAD(MIO[33]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[34].MIO_BIBUF
(.IO(buffered_MIO[34]),
.PAD(MIO[34]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[35].MIO_BIBUF
(.IO(buffered_MIO[35]),
.PAD(MIO[35]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[36].MIO_BIBUF
(.IO(buffered_MIO[36]),
.PAD(MIO[36]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[37].MIO_BIBUF
(.IO(buffered_MIO[37]),
.PAD(MIO[37]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[38].MIO_BIBUF
(.IO(buffered_MIO[38]),
.PAD(MIO[38]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[39].MIO_BIBUF
(.IO(buffered_MIO[39]),
.PAD(MIO[39]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[3].MIO_BIBUF
(.IO(buffered_MIO[3]),
.PAD(MIO[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[40].MIO_BIBUF
(.IO(buffered_MIO[40]),
.PAD(MIO[40]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[41].MIO_BIBUF
(.IO(buffered_MIO[41]),
.PAD(MIO[41]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[42].MIO_BIBUF
(.IO(buffered_MIO[42]),
.PAD(MIO[42]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[43].MIO_BIBUF
(.IO(buffered_MIO[43]),
.PAD(MIO[43]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[44].MIO_BIBUF
(.IO(buffered_MIO[44]),
.PAD(MIO[44]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[45].MIO_BIBUF
(.IO(buffered_MIO[45]),
.PAD(MIO[45]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[46].MIO_BIBUF
(.IO(buffered_MIO[46]),
.PAD(MIO[46]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[47].MIO_BIBUF
(.IO(buffered_MIO[47]),
.PAD(MIO[47]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[48].MIO_BIBUF
(.IO(buffered_MIO[48]),
.PAD(MIO[48]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[49].MIO_BIBUF
(.IO(buffered_MIO[49]),
.PAD(MIO[49]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[4].MIO_BIBUF
(.IO(buffered_MIO[4]),
.PAD(MIO[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[50].MIO_BIBUF
(.IO(buffered_MIO[50]),
.PAD(MIO[50]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[51].MIO_BIBUF
(.IO(buffered_MIO[51]),
.PAD(MIO[51]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[52].MIO_BIBUF
(.IO(buffered_MIO[52]),
.PAD(MIO[52]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[53].MIO_BIBUF
(.IO(buffered_MIO[53]),
.PAD(MIO[53]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[5].MIO_BIBUF
(.IO(buffered_MIO[5]),
.PAD(MIO[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[6].MIO_BIBUF
(.IO(buffered_MIO[6]),
.PAD(MIO[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[7].MIO_BIBUF
(.IO(buffered_MIO[7]),
.PAD(MIO[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[8].MIO_BIBUF
(.IO(buffered_MIO[8]),
.PAD(MIO[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[9].MIO_BIBUF
(.IO(buffered_MIO[9]),
.PAD(MIO[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[0].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[0]),
.PAD(DDR_BankAddr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[1].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[1]),
.PAD(DDR_BankAddr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[2].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[2]),
.PAD(DDR_BankAddr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[0].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[0]),
.PAD(DDR_Addr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[10].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[10]),
.PAD(DDR_Addr[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[11].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[11]),
.PAD(DDR_Addr[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[12].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[12]),
.PAD(DDR_Addr[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[13].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[13]),
.PAD(DDR_Addr[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[14].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[14]),
.PAD(DDR_Addr[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[1].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[1]),
.PAD(DDR_Addr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[2].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[2]),
.PAD(DDR_Addr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[3].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[3]),
.PAD(DDR_Addr[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[4].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[4]),
.PAD(DDR_Addr[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[5].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[5]),
.PAD(DDR_Addr[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[6].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[6]),
.PAD(DDR_Addr[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[7].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[7]),
.PAD(DDR_Addr[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[8].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[8]),
.PAD(DDR_Addr[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[9].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[9]),
.PAD(DDR_Addr[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[0].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[0]),
.PAD(DDR_DM[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[1].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[1]),
.PAD(DDR_DM[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[2].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[2]),
.PAD(DDR_DM[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[3].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[3]),
.PAD(DDR_DM[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[0].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[0]),
.PAD(DDR_DQ[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[10].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[10]),
.PAD(DDR_DQ[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[11].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[11]),
.PAD(DDR_DQ[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[12].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[12]),
.PAD(DDR_DQ[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[13].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[13]),
.PAD(DDR_DQ[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[14].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[14]),
.PAD(DDR_DQ[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[15].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[15]),
.PAD(DDR_DQ[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[16].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[16]),
.PAD(DDR_DQ[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[17].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[17]),
.PAD(DDR_DQ[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[18].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[18]),
.PAD(DDR_DQ[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[19].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[19]),
.PAD(DDR_DQ[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[1].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[1]),
.PAD(DDR_DQ[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[20].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[20]),
.PAD(DDR_DQ[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[21].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[21]),
.PAD(DDR_DQ[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[22].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[22]),
.PAD(DDR_DQ[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[23].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[23]),
.PAD(DDR_DQ[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[24].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[24]),
.PAD(DDR_DQ[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[25].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[25]),
.PAD(DDR_DQ[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[26].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[26]),
.PAD(DDR_DQ[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[27].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[27]),
.PAD(DDR_DQ[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[28].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[28]),
.PAD(DDR_DQ[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[29].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[29]),
.PAD(DDR_DQ[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[2].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[2]),
.PAD(DDR_DQ[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[30].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[30]),
.PAD(DDR_DQ[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[31].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[31]),
.PAD(DDR_DQ[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[3].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[3]),
.PAD(DDR_DQ[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[4].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[4]),
.PAD(DDR_DQ[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[5].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[5]),
.PAD(DDR_DQ[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[6].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[6]),
.PAD(DDR_DQ[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[7].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[7]),
.PAD(DDR_DQ[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[8].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[8]),
.PAD(DDR_DQ[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[9].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[9]),
.PAD(DDR_DQ[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[0].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[0]),
.PAD(DDR_DQS_n[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[1].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[1]),
.PAD(DDR_DQS_n[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[2].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[2]),
.PAD(DDR_DQS_n[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[3].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[3]),
.PAD(DDR_DQS_n[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[0].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[0]),
.PAD(DDR_DQS[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[1].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[1]),
.PAD(DDR_DQS[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[2].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[2]),
.PAD(DDR_DQS[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[3].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[3]),
.PAD(DDR_DQS[3]));
LUT1 #(
.INIT(2'h2))
i_0
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[0] ));
LUT1 #(
.INIT(2'h2))
i_1
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [1]));
LUT1 #(
.INIT(2'h2))
i_10
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [1]));
LUT1 #(
.INIT(2'h2))
i_11
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [0]));
LUT1 #(
.INIT(2'h2))
i_12
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [1]));
LUT1 #(
.INIT(2'h2))
i_13
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [0]));
LUT1 #(
.INIT(2'h2))
i_14
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [1]));
LUT1 #(
.INIT(2'h2))
i_15
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [0]));
LUT1 #(
.INIT(2'h2))
i_16
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [1]));
LUT1 #(
.INIT(2'h2))
i_17
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [0]));
LUT1 #(
.INIT(2'h2))
i_18
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [1]));
LUT1 #(
.INIT(2'h2))
i_19
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [0]));
LUT1 #(
.INIT(2'h2))
i_2
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [0]));
LUT1 #(
.INIT(2'h2))
i_20
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [1]));
LUT1 #(
.INIT(2'h2))
i_21
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [0]));
LUT1 #(
.INIT(2'h2))
i_22
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [1]));
LUT1 #(
.INIT(2'h2))
i_23
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [0]));
LUT1 #(
.INIT(2'h2))
i_3
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[7] ));
LUT1 #(
.INIT(2'h2))
i_4
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[6] ));
LUT1 #(
.INIT(2'h2))
i_5
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[5] ));
LUT1 #(
.INIT(2'h2))
i_6
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[4] ));
LUT1 #(
.INIT(2'h2))
i_7
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[3] ));
LUT1 #(
.INIT(2'h2))
i_8
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[2] ));
LUT1 #(
.INIT(2'h2))
i_9
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[1] ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1 ns / 1 ps
module elink2_tb;
reg aclk;
reg aresetn;
reg start;
wire csysreq = 1'b0;
wire reset = ~aresetn;
wire [11:0] param_coreid = 12'h810;
wire [2:0] done;
wire [2:0] error;
// Create an instance of the example tb
elink_testbench dut
(.aclk (aclk),
.aresetn (aresetn),
.reset (reset),
.csysreq (csysreq),
.done0 (done[0]),
.done1 (done[1]),
.done2 (done[2]),
.error0 (error[0]),
.error1 (error[1]),
.error2 (error[2]),
.start (start),
.param_coreid (param_coreid));
// Reset Generator
initial begin
aresetn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge aclk);
aresetn = 1'b1;
end
// Clock Generator
initial aclk = 1'b0;
always #5 aclk = ~aclk;
// Drive the BFM
initial begin
start = 1'b0;
// Wait for end of reset
wait(aresetn === 0) @(posedge aclk);
wait(aresetn === 1) @(posedge aclk);
wait(aresetn === 1) @(posedge aclk);
wait(aresetn === 1) @(posedge aclk);
wait(aresetn === 1) @(posedge aclk);
#500 start = 1'b1;
$display("=== TB Started");
wait( done == 3'b111);
$display("=== TEST_FINISHED");
if ( error != 3'b000 ) begin
$display("===_TEST: FAILED!");
end else begin
$display("=== TEST: PASSED!");
end
end
always @ (posedge done[2])
$display("=== INIT Complete");
always @ (posedge done[0])
$display("=== GOLD->ELINK2 Complete");
always @ (posedge done[1])
$display("=== ELINK2->GOLD Complete");
always @ (posedge error[0])
if( error[0] == 1'b1 && done[0] == 1'b0)
$display("=== ERROR FLAG GOLD->ELINK2 @ %t", $time);
always @ (posedge error[1])
if( error[1] == 1'b1 && done[1] == 1'b0)
$display("=== ERROR FLAG ELINK2->GOLD @ %T", $time);
always @ (posedge error[2])
if( error[2] == 1'b1 && done[2] == 1'b0)
$display("=== ERROR FLAG INIT @ %T", $time);
endmodule
|
module multistage_interconnect_network(clk, push, d_in, valid, d_out, control);
parameter WIDTH = 64;
parameter IN_PORTS = 16;
parameter PIPELINE_STAGES = 5;
parameter OUT_PORTS = IN_PORTS;
parameter ADDR_WIDTH_PORTS = log2(OUT_PORTS-1); //TODO: max
input clk;
input [0:IN_PORTS-1] push;
input [IN_PORTS*WIDTH-1:0] d_in;
output [0:OUT_PORTS-1] valid;
output [OUT_PORTS*WIDTH-1:0] d_out;
input [ADDR_WIDTH_PORTS-1:0] control;
`include "log2.vh"
integer i, j;
genvar g, g2;
reg [WIDTH:0] input_stage[0:IN_PORTS-1];
wire [WIDTH:0] stage [0:ADDR_WIDTH_PORTS-1][0:IN_PORTS-1];
always @*
for(i = 0; i < IN_PORTS; i = i + 1) begin
input_stage[i][0] = push[i];
input_stage[i][WIDTH -:WIDTH] = d_in[(WIDTH)*(IN_PORTS-i)-1 -: WIDTH];
end
generate for(g = 0; g < IN_PORTS/2; g = g + 1) begin: generate_start
basic_switch #(WIDTH+1) sw(input_stage[g*2], input_stage[g*2+1], stage[0][g*2], stage[0][g*2+1], control[ADDR_WIDTH_PORTS-1]);
//basic_switch #(WIDTH+1) sw(input_stage[g*2], input_stage[g*2+1], stage[0][g*2], stage[0][g*2+1], control[ADDR_WIDTH_PORTS-1]);
end
for(g = 1; g < ADDR_WIDTH_PORTS; g = g + 1) begin: generate_stage
for(g2 = 0; g2 < IN_PORTS/2; g2 = g2 + 1) begin: generate_switch
basic_switch #(WIDTH+1) sw(stage[g-1][g2*2], stage[g-1][(g2^(1<<(ADDR_WIDTH_PORTS-2)))*2+1], stage[g][g2*2], stage[g][g2*2+1], control[ADDR_WIDTH_PORTS-g-1]);
end
end
endgenerate
reg [WIDTH:0] output_pipeline [0:PIPELINE_STAGES-1][0:OUT_PORTS-1];
always @(posedge clk)begin
for(i = 0; i < OUT_PORTS; i = i + 1)
output_pipeline[0][i] <= stage[ADDR_WIDTH_PORTS-1][i];
for(i = 1; i < PIPELINE_STAGES; i = i + 1) begin
for(j = 0; j < OUT_PORTS; j = j + 1) begin
output_pipeline[i][j] <= output_pipeline[i-1][j];
end
end
end
generate for(g=0; g < OUT_PORTS; g = g + 1) begin: generate_output
assign valid[g] = output_pipeline[PIPELINE_STAGES-1][g][0];
assign d_out[WIDTH*(OUT_PORTS-g)-1 -:WIDTH] = output_pipeline[PIPELINE_STAGES-1][g][WIDTH -: WIDTH];
end
endgenerate
//DEBUG
always @(posedge clk) begin
if(push)
for(i = 0; i < ADDR_WIDTH_PORTS; i = i + 1)
for(j = 0; j < OUT_PORTS; j = j + 1)
$display("stages: %d, %d, %b", i, j, stage[i][j]);
end
endmodule
|
/*
# ZUMA Open FPGA Overlay
# Alex Brant
# Email: [email protected]
# 2012
# LUTRAM wrapper
*/
/* These luts are used for building configurable muxes.*/
`include "define.v"
`include "def_generated.v"
`include "primitives.v"
module lut_custom #(
parameter used = 0,
parameter LUT_MASK={2**K{1'b0}}
) (
a,
d,
dpra,
clk,
we,
dpo);
input [ZUMA_LUT_SIZE-1 : 0] a;
input [0 : 0] d;
input [ZUMA_LUT_SIZE-1 : 0] dpra;
input clk;
input we;
output dpo;
wire lut_output;
//no plattform. just for a verificational build.
`ifdef ZUMA_VERIFICATION
generate
if( used == 0)
//nothing will be generated and connected
else
//we generate a lut
LUT_K #(
.K(ZUMA_LUT_SIZE),
.LUT_MASK(LUT_MASK)
) verification_lut (
.in(dpra),
.out(lut_output)
);
endgenerate
`elsif PLATFORM_XILINX
lut_xilinx LUT (
.a(a), // input [5 : 0] a
.d(d), // input [0 : 0] d
.dpra( dpra ), // input [5 : 0] dpra
.clk(clk), // input clk
.we(we), // input we
.dpo( lut_output ));
`elsif PLATFORM_ALTERA
SDPR LUT(
.clock(clk),
.data(d),
.rdaddress(dpra),
.wraddress(a),
.wren(we),
.q(lut_output));
`endif
`ifdef SIMULATION //X'd inputs will break the simulation
assign dpo = (lut_output === 1'bx) ? 0 : lut_output ;
`else
assign dpo = lut_output;
`endif
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Expert(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Wed Oct 19 14:29:42 2016
/////////////////////////////////////////////////////////////
module Mux_3x1_W1 ( ctrl, D0, D1, D2, S );
input [1:0] ctrl;
input [0:0] D0;
input [0:0] D1;
input [0:0] D2;
output [0:0] S;
wire n2, n3, n1;
AOI22X1TS U2 ( .A0(D0[0]), .A1(n2), .B0(ctrl[0]), .B1(D1[0]), .Y(n3) );
OAI2BB2XLTS U3 ( .B0(ctrl[1]), .B1(n3), .A0N(ctrl[1]), .A1N(n1), .Y(S[0]) );
AND2X2TS U4 ( .A(D2[0]), .B(n2), .Y(n1) );
INVX2TS U5 ( .A(ctrl[0]), .Y(n2) );
endmodule
module Multiplexer_AC_W8 ( ctrl, D0, D1, S );
input [7:0] D0;
input [7:0] D1;
output [7:0] S;
input ctrl;
wire n1, n2;
INVX2TS U1 ( .A(n2), .Y(n1) );
INVX2TS U2 ( .A(ctrl), .Y(n2) );
AO22X1TS U3 ( .A0(n1), .A1(D1[7]), .B0(D0[7]), .B1(n2), .Y(S[7]) );
AO22X1TS U4 ( .A0(D1[0]), .A1(n1), .B0(D0[0]), .B1(n2), .Y(S[0]) );
AO22X1TS U5 ( .A0(D1[1]), .A1(n1), .B0(D0[1]), .B1(n2), .Y(S[1]) );
AO22X1TS U6 ( .A0(D1[2]), .A1(n1), .B0(D0[2]), .B1(n2), .Y(S[2]) );
AO22X1TS U7 ( .A0(D1[3]), .A1(n1), .B0(D0[3]), .B1(n2), .Y(S[3]) );
AO22X1TS U8 ( .A0(D1[4]), .A1(n1), .B0(D0[4]), .B1(n2), .Y(S[4]) );
AO22X1TS U9 ( .A0(D1[5]), .A1(n1), .B0(D0[5]), .B1(n2), .Y(S[5]) );
AO22X1TS U10 ( .A0(D1[6]), .A1(n1), .B0(D0[6]), .B1(n2), .Y(S[6]) );
endmodule
module Multiplexer_AC_W23 ( ctrl, D0, D1, S );
input [22:0] D0;
input [22:0] D1;
output [22:0] S;
input ctrl;
wire n1, n2, n3, n4, n5;
INVX2TS U1 ( .A(n5), .Y(n2) );
CLKBUFX2TS U2 ( .A(n5), .Y(n3) );
CLKBUFX2TS U3 ( .A(n5), .Y(n4) );
INVX2TS U4 ( .A(n1), .Y(n5) );
CLKBUFX2TS U5 ( .A(ctrl), .Y(n1) );
AO22X1TS U6 ( .A0(D1[0]), .A1(ctrl), .B0(D0[0]), .B1(n5), .Y(S[0]) );
AO22X1TS U7 ( .A0(D1[1]), .A1(ctrl), .B0(D0[1]), .B1(n3), .Y(S[1]) );
AO22X1TS U8 ( .A0(D1[2]), .A1(n2), .B0(D0[2]), .B1(n3), .Y(S[2]) );
AO22X1TS U9 ( .A0(D1[3]), .A1(n2), .B0(D0[3]), .B1(n3), .Y(S[3]) );
AO22X1TS U10 ( .A0(D1[4]), .A1(n2), .B0(D0[4]), .B1(n3), .Y(S[4]) );
AO22X1TS U11 ( .A0(D1[5]), .A1(n2), .B0(D0[5]), .B1(n3), .Y(S[5]) );
AO22X1TS U12 ( .A0(D1[6]), .A1(n2), .B0(D0[6]), .B1(n3), .Y(S[6]) );
AO22X1TS U13 ( .A0(D1[7]), .A1(n2), .B0(D0[7]), .B1(n3), .Y(S[7]) );
AO22X1TS U14 ( .A0(D1[10]), .A1(ctrl), .B0(D0[10]), .B1(n4), .Y(S[10]) );
AO22X1TS U15 ( .A0(D1[11]), .A1(ctrl), .B0(D0[11]), .B1(n4), .Y(S[11]) );
AO22X1TS U16 ( .A0(D1[12]), .A1(ctrl), .B0(D0[12]), .B1(n4), .Y(S[12]) );
AO22X1TS U17 ( .A0(D1[13]), .A1(ctrl), .B0(D0[13]), .B1(n4), .Y(S[13]) );
AO22X1TS U18 ( .A0(D1[14]), .A1(ctrl), .B0(D0[14]), .B1(n5), .Y(S[14]) );
AO22X1TS U19 ( .A0(D1[15]), .A1(ctrl), .B0(D0[15]), .B1(n5), .Y(S[15]) );
AO22X1TS U20 ( .A0(D1[16]), .A1(n1), .B0(D0[16]), .B1(n4), .Y(S[16]) );
AO22X1TS U21 ( .A0(D1[17]), .A1(n1), .B0(D0[17]), .B1(n4), .Y(S[17]) );
AO22X1TS U22 ( .A0(D1[18]), .A1(n1), .B0(D0[18]), .B1(n4), .Y(S[18]) );
AO22X1TS U23 ( .A0(D1[19]), .A1(n1), .B0(D0[19]), .B1(n4), .Y(S[19]) );
AO22X1TS U24 ( .A0(D1[20]), .A1(n1), .B0(D0[20]), .B1(n3), .Y(S[20]) );
AO22X1TS U25 ( .A0(D1[21]), .A1(n2), .B0(D0[21]), .B1(n3), .Y(S[21]) );
AO22X1TS U26 ( .A0(D1[22]), .A1(n2), .B0(D0[22]), .B1(n3), .Y(S[22]) );
AO22X1TS U27 ( .A0(D1[8]), .A1(n2), .B0(D0[8]), .B1(n4), .Y(S[8]) );
AO22X1TS U28 ( .A0(n2), .A1(D1[9]), .B0(D0[9]), .B1(n4), .Y(S[9]) );
endmodule
module RegisterAdd_W32 ( clk, rst, load, D, Q );
input [31:0] D;
output [31:0] Q;
input clk, rst, load;
wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44,
n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58,
n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72,
n73, n74;
OAI2BB2XLTS U2 ( .B0(n1), .B1(n69), .A0N(n72), .A1N(D[0]), .Y(n33) );
OAI2BB2XLTS U3 ( .B0(n2), .B1(n69), .A0N(D[1]), .A1N(n72), .Y(n34) );
OAI2BB2XLTS U4 ( .B0(n3), .B1(n69), .A0N(D[2]), .A1N(n72), .Y(n35) );
OAI2BB2XLTS U5 ( .B0(n4), .B1(n69), .A0N(D[3]), .A1N(n72), .Y(n36) );
OAI2BB2XLTS U6 ( .B0(n5), .B1(n69), .A0N(D[4]), .A1N(n71), .Y(n37) );
OAI2BB2XLTS U7 ( .B0(n6), .B1(n69), .A0N(D[5]), .A1N(n71), .Y(n38) );
OAI2BB2XLTS U8 ( .B0(n7), .B1(n74), .A0N(D[6]), .A1N(n71), .Y(n39) );
OAI2BB2XLTS U9 ( .B0(n8), .B1(n69), .A0N(D[7]), .A1N(n71), .Y(n40) );
OAI2BB2XLTS U10 ( .B0(n9), .B1(n73), .A0N(D[8]), .A1N(n71), .Y(n41) );
OAI2BB2XLTS U11 ( .B0(n10), .B1(n74), .A0N(D[9]), .A1N(n71), .Y(n42) );
OAI2BB2XLTS U12 ( .B0(n11), .B1(n73), .A0N(D[10]), .A1N(n71), .Y(n43) );
OAI2BB2XLTS U13 ( .B0(n12), .B1(n74), .A0N(D[11]), .A1N(n71), .Y(n44) );
OAI2BB2XLTS U14 ( .B0(n13), .B1(n70), .A0N(D[12]), .A1N(n71), .Y(n45) );
OAI2BB2XLTS U15 ( .B0(n14), .B1(n73), .A0N(D[13]), .A1N(n71), .Y(n46) );
OAI2BB2XLTS U16 ( .B0(n15), .B1(n70), .A0N(D[14]), .A1N(n72), .Y(n47) );
OAI2BB2XLTS U17 ( .B0(n16), .B1(n70), .A0N(D[15]), .A1N(n72), .Y(n48) );
OAI2BB2XLTS U18 ( .B0(n17), .B1(n70), .A0N(D[16]), .A1N(n72), .Y(n49) );
OAI2BB2XLTS U19 ( .B0(n18), .B1(n70), .A0N(D[17]), .A1N(n72), .Y(n50) );
OAI2BB2XLTS U20 ( .B0(n19), .B1(n70), .A0N(D[18]), .A1N(n72), .Y(n51) );
OAI2BB2XLTS U21 ( .B0(n20), .B1(n70), .A0N(D[19]), .A1N(n72), .Y(n52) );
OAI2BB2XLTS U22 ( .B0(n21), .B1(load), .A0N(D[20]), .A1N(n73), .Y(n53) );
OAI2BB2XLTS U23 ( .B0(n22), .B1(n74), .A0N(D[21]), .A1N(n73), .Y(n54) );
OAI2BB2XLTS U24 ( .B0(n23), .B1(load), .A0N(D[22]), .A1N(n74), .Y(n55) );
OAI2BB2XLTS U25 ( .B0(n24), .B1(n70), .A0N(D[23]), .A1N(load), .Y(n56) );
OAI2BB2XLTS U26 ( .B0(n25), .B1(n70), .A0N(D[24]), .A1N(load), .Y(n57) );
OAI2BB2XLTS U27 ( .B0(n26), .B1(n70), .A0N(D[25]), .A1N(n73), .Y(n58) );
OAI2BB2XLTS U28 ( .B0(n27), .B1(n74), .A0N(D[26]), .A1N(load), .Y(n59) );
OAI2BB2XLTS U29 ( .B0(n28), .B1(n74), .A0N(D[27]), .A1N(load), .Y(n60) );
OAI2BB2XLTS U30 ( .B0(n29), .B1(n74), .A0N(D[28]), .A1N(load), .Y(n61) );
OAI2BB2XLTS U31 ( .B0(n30), .B1(n69), .A0N(D[29]), .A1N(n73), .Y(n62) );
OAI2BB2XLTS U32 ( .B0(n31), .B1(n69), .A0N(D[30]), .A1N(n74), .Y(n63) );
CLKINVX1TS U33 ( .A(rst), .Y(n64) );
OAI2BB2XLTS U34 ( .B0(n32), .B1(n69), .A0N(D[31]), .A1N(n73), .Y(n65) );
DFFRX2TS \Q_reg[31] ( .D(n65), .CK(clk), .RN(n67), .Q(Q[31]), .QN(n32) );
DFFRX2TS \Q_reg[30] ( .D(n63), .CK(clk), .RN(n68), .Q(Q[30]), .QN(n31) );
DFFRX2TS \Q_reg[29] ( .D(n62), .CK(clk), .RN(n68), .Q(Q[29]), .QN(n30) );
DFFRX2TS \Q_reg[28] ( .D(n61), .CK(clk), .RN(n67), .Q(Q[28]), .QN(n29) );
DFFRX2TS \Q_reg[27] ( .D(n60), .CK(clk), .RN(n67), .Q(Q[27]), .QN(n28) );
DFFRX2TS \Q_reg[26] ( .D(n59), .CK(clk), .RN(n67), .Q(Q[26]), .QN(n27) );
DFFRX2TS \Q_reg[25] ( .D(n58), .CK(clk), .RN(n67), .Q(Q[25]), .QN(n26) );
DFFRX2TS \Q_reg[24] ( .D(n57), .CK(clk), .RN(n67), .Q(Q[24]), .QN(n25) );
DFFRX2TS \Q_reg[23] ( .D(n56), .CK(clk), .RN(n67), .Q(Q[23]), .QN(n24) );
DFFRX2TS \Q_reg[22] ( .D(n55), .CK(clk), .RN(n67), .Q(Q[22]), .QN(n23) );
DFFRX2TS \Q_reg[21] ( .D(n54), .CK(clk), .RN(n67), .Q(Q[21]), .QN(n22) );
DFFRX2TS \Q_reg[20] ( .D(n53), .CK(clk), .RN(n67), .Q(Q[20]), .QN(n21) );
DFFRX2TS \Q_reg[19] ( .D(n52), .CK(clk), .RN(n64), .Q(Q[19]), .QN(n20) );
DFFRX2TS \Q_reg[18] ( .D(n51), .CK(clk), .RN(n64), .Q(Q[18]), .QN(n19) );
DFFRX2TS \Q_reg[17] ( .D(n50), .CK(clk), .RN(n64), .Q(Q[17]), .QN(n18) );
DFFRX2TS \Q_reg[16] ( .D(n49), .CK(clk), .RN(n64), .Q(Q[16]), .QN(n17) );
DFFRX2TS \Q_reg[15] ( .D(n48), .CK(clk), .RN(n64), .Q(Q[15]), .QN(n16) );
DFFRX2TS \Q_reg[14] ( .D(n47), .CK(clk), .RN(n64), .Q(Q[14]), .QN(n15) );
DFFRX2TS \Q_reg[13] ( .D(n46), .CK(clk), .RN(n64), .Q(Q[13]), .QN(n14) );
DFFRX2TS \Q_reg[12] ( .D(n45), .CK(clk), .RN(n64), .Q(Q[12]), .QN(n13) );
DFFRX2TS \Q_reg[11] ( .D(n44), .CK(clk), .RN(n68), .Q(Q[11]), .QN(n12) );
DFFRX2TS \Q_reg[10] ( .D(n43), .CK(clk), .RN(n68), .Q(Q[10]), .QN(n11) );
DFFRX2TS \Q_reg[9] ( .D(n42), .CK(clk), .RN(n66), .Q(Q[9]), .QN(n10) );
DFFRX2TS \Q_reg[8] ( .D(n41), .CK(clk), .RN(n66), .Q(Q[8]), .QN(n9) );
DFFRX2TS \Q_reg[7] ( .D(n40), .CK(clk), .RN(n66), .Q(Q[7]), .QN(n8) );
DFFRX2TS \Q_reg[6] ( .D(n39), .CK(clk), .RN(n66), .Q(Q[6]), .QN(n7) );
DFFRX2TS \Q_reg[5] ( .D(n38), .CK(clk), .RN(n66), .Q(Q[5]), .QN(n6) );
DFFRX2TS \Q_reg[4] ( .D(n37), .CK(clk), .RN(n66), .Q(Q[4]), .QN(n5) );
DFFRX2TS \Q_reg[3] ( .D(n36), .CK(clk), .RN(n66), .Q(Q[3]), .QN(n4) );
DFFRX2TS \Q_reg[2] ( .D(n35), .CK(clk), .RN(n66), .Q(Q[2]), .QN(n3) );
DFFRX2TS \Q_reg[1] ( .D(n34), .CK(clk), .RN(n66), .Q(Q[1]), .QN(n2) );
DFFRX2TS \Q_reg[0] ( .D(n33), .CK(clk), .RN(n66), .Q(Q[0]), .QN(n1) );
CLKBUFX2TS U35 ( .A(n68), .Y(n66) );
CLKBUFX2TS U36 ( .A(n74), .Y(n70) );
CLKBUFX2TS U37 ( .A(n73), .Y(n71) );
CLKBUFX2TS U38 ( .A(n73), .Y(n72) );
CLKBUFX2TS U39 ( .A(n64), .Y(n68) );
CLKBUFX2TS U40 ( .A(n64), .Y(n67) );
CLKBUFX2TS U41 ( .A(load), .Y(n73) );
CLKBUFX2TS U42 ( .A(load), .Y(n74) );
CLKBUFX2TS U43 ( .A(load), .Y(n69) );
endmodule
module Tenth_Phase ( clk, rst, load_i, sel_a_i, sel_b_i, sign_i, exp_ieee_i,
sgf_ieee_i, final_result_ieee_o );
input [7:0] exp_ieee_i;
input [22:0] sgf_ieee_i;
output [31:0] final_result_ieee_o;
input clk, rst, load_i, sel_a_i, sel_b_i, sign_i;
wire overunder, Sign_S_mux;
wire [7:0] Exp_S_mux;
wire [22:0] Sgf_S_mux;
Mux_3x1_W1 Sign_Mux ( .ctrl({sel_a_i, sel_b_i}), .D0(sign_i), .D1(1'b1),
.D2(1'b0), .S(Sign_S_mux) );
Multiplexer_AC_W8 Exp_Mux ( .ctrl(overunder), .D0(exp_ieee_i), .D1({1'b1,
1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), .S(Exp_S_mux) );
Multiplexer_AC_W23 Sgf_Mux ( .ctrl(overunder), .D0(sgf_ieee_i), .D1({1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}), .S(
Sgf_S_mux) );
RegisterAdd_W32 Final_Result_IEEE ( .clk(clk), .rst(rst), .load(load_i), .D(
{Sign_S_mux, Exp_S_mux, Sgf_S_mux}), .Q(final_result_ieee_o) );
OR2X2TS U4 ( .A(sel_a_i), .B(sel_b_i), .Y(overunder) );
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFXTP_TB_V
`define SKY130_FD_SC_HD__SDFXTP_TB_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__sdfxtp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SCD = 1'b0;
#60 SCE = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 SCD = 1'b1;
#200 SCE = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 SCD = 1'b0;
#340 SCE = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 SCE = 1'b1;
#540 SCD = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 SCE = 1'bx;
#680 SCD = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hd__sdfxtp dut (.D(D), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFXTP_TB_V
|
(** * RecordSub: Subtyping with Records *)
(** In this chapter, we combine two significant extensions of the pure
STLC -- records (from chapter [Records]) and subtyping (from
chapter [Sub]) -- and explore their interactions. Most of the
concepts have already been discussed in those chapters, so the
presentation here is somewhat terse. We just comment where things
are nonstandard. *)
Set Warnings "-notation-overridden,-parsing".
Require Import Maps.
Require Import Smallstep.
Require Import MoreStlc.
(* ################################################################# *)
(** * Core Definitions *)
(* ----------------------------------------------------------------- *)
(** *** Syntax *)
Inductive ty : Type :=
(* proper types *)
| TTop : ty
| TBase : id -> ty
| TArrow : ty -> ty -> ty
(* record types *)
| TRNil : ty
| TRCons : id -> ty -> ty -> ty.
Inductive tm : Type :=
(* proper terms *)
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
| tproj : tm -> id -> tm
(* record terms *)
| trnil : tm
| trcons : id -> tm -> tm -> tm.
(* ----------------------------------------------------------------- *)
(** *** Well-Formedness *)
(** The syntax of terms and types is a bit too loose, in the sense
that it admits things like a record type whose final "tail" is
[Top] or some arrow type rather than [Nil]. To avoid such cases,
it is useful to assume that all the record types and terms that we
see will obey some simple well-formedness conditions.
[An interesting technical question is whether the basic properties
of the system -- progress and preservation -- remain true if we
drop these conditions. I believe they do, and I would encourage
motivated readers to try to check this by dropping the conditions
from the definitions of typing and subtyping and adjusting the
proofs in the rest of the chapter accordingly. This is not a
trivial exercise (or I'd have done it!), but it should not involve
changing the basic structure of the proofs. If someone does do
it, please let me know. --BCP 5/16.] *)
Inductive record_ty : ty -> Prop :=
| RTnil :
record_ty TRNil
| RTcons : forall i T1 T2,
record_ty (TRCons i T1 T2).
Inductive record_tm : tm -> Prop :=
| rtnil :
record_tm trnil
| rtcons : forall i t1 t2,
record_tm (trcons i t1 t2).
Inductive well_formed_ty : ty -> Prop :=
| wfTTop :
well_formed_ty TTop
| wfTBase : forall i,
well_formed_ty (TBase i)
| wfTArrow : forall T1 T2,
well_formed_ty T1 ->
well_formed_ty T2 ->
well_formed_ty (TArrow T1 T2)
| wfTRNil :
well_formed_ty TRNil
| wfTRCons : forall i T1 T2,
well_formed_ty T1 ->
well_formed_ty T2 ->
record_ty T2 ->
well_formed_ty (TRCons i T1 T2).
Hint Constructors record_ty record_tm well_formed_ty.
(* ----------------------------------------------------------------- *)
(** *** Substitution *)
(** Substitution and reduction are as before. *)
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar y => if beq_id x y then s else t
| tabs y T t1 => tabs y T (if beq_id x y then t1
else (subst x s t1))
| tapp t1 t2 => tapp (subst x s t1) (subst x s t2)
| tproj t1 i => tproj (subst x s t1) i
| trnil => trnil
| trcons i t1 tr2 => trcons i (subst x s t1) (subst x s tr2)
end.
Notation "'[' x ':=' s ']' t" := (subst x s t) (at level 20).
(* ----------------------------------------------------------------- *)
(** *** Reduction *)
Inductive value : tm -> Prop :=
| v_abs : forall x T t,
value (tabs x T t)
| v_rnil : value trnil
| v_rcons : forall i v vr,
value v ->
value vr ->
value (trcons i v vr).
Hint Constructors value.
Fixpoint Tlookup (i:id) (Tr:ty) : option ty :=
match Tr with
| TRCons i' T Tr' =>
if beq_id i i' then Some T else Tlookup i Tr'
| _ => None
end.
Fixpoint tlookup (i:id) (tr:tm) : option tm :=
match tr with
| trcons i' t tr' =>
if beq_id i i' then Some t else tlookup i tr'
| _ => None
end.
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T t12 v2,
value v2 ->
(tapp (tabs x T t12) v2) ==> [x:=v2]t12
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
(tapp t1 t2) ==> (tapp t1' t2)
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tapp v1 t2) ==> (tapp v1 t2')
| ST_Proj1 : forall tr tr' i,
tr ==> tr' ->
(tproj tr i) ==> (tproj tr' i)
| ST_ProjRcd : forall tr i vi,
value tr ->
tlookup i tr = Some vi ->
(tproj tr i) ==> vi
| ST_Rcd_Head : forall i t1 t1' tr2,
t1 ==> t1' ->
(trcons i t1 tr2) ==> (trcons i t1' tr2)
| ST_Rcd_Tail : forall i v1 tr2 tr2',
value v1 ->
tr2 ==> tr2' ->
(trcons i v1 tr2) ==> (trcons i v1 tr2')
where "t1 '==>' t2" := (step t1 t2).
Hint Constructors step.
(* ################################################################# *)
(** * Subtyping *)
(** Now we come to the interesting part, where the features we've
added start to interact. We begin by defining the subtyping
relation and developing some of its important technical
properties. *)
(* ================================================================= *)
(** ** Definition *)
(** The definition of subtyping is essentially just what we sketched
in the discussion of record subtyping in chapter [Sub], but we
need to add well-formedness side conditions to some of the rules.
Also, we replace the "n-ary" width, depth, and permutation
subtyping rules by binary rules that deal with just the first
field. *)
Reserved Notation "T '<:' U" (at level 40).
Inductive subtype : ty -> ty -> Prop :=
(* Subtyping between proper types *)
| S_Refl : forall T,
well_formed_ty T ->
T <: T
| S_Trans : forall S U T,
S <: U ->
U <: T ->
S <: T
| S_Top : forall S,
well_formed_ty S ->
S <: TTop
| S_Arrow : forall S1 S2 T1 T2,
T1 <: S1 ->
S2 <: T2 ->
TArrow S1 S2 <: TArrow T1 T2
(* Subtyping between record types *)
| S_RcdWidth : forall i T1 T2,
well_formed_ty (TRCons i T1 T2) ->
TRCons i T1 T2 <: TRNil
| S_RcdDepth : forall i S1 T1 Sr2 Tr2,
S1 <: T1 ->
Sr2 <: Tr2 ->
record_ty Sr2 ->
record_ty Tr2 ->
TRCons i S1 Sr2 <: TRCons i T1 Tr2
| S_RcdPerm : forall i1 i2 T1 T2 Tr3,
well_formed_ty (TRCons i1 T1 (TRCons i2 T2 Tr3)) ->
i1 <> i2 ->
TRCons i1 T1 (TRCons i2 T2 Tr3)
<: TRCons i2 T2 (TRCons i1 T1 Tr3)
where "T '<:' U" := (subtype T U).
Hint Constructors subtype.
(* ================================================================= *)
(** ** Examples *)
Module Examples.
Notation x := (Id "x").
Notation y := (Id "y").
Notation z := (Id "z").
Notation j := (Id "j").
Notation k := (Id "k").
Notation i := (Id "i").
Notation A := (TBase (Id "A")).
Notation B := (TBase (Id "B")).
Notation C := (TBase (Id "C")).
Definition TRcd_j :=
(TRCons j (TArrow B B) TRNil). (* {j:B->B} *)
Definition TRcd_kj :=
TRCons k (TArrow A A) TRcd_j. (* {k:C->C,j:B->B} *)
Example subtyping_example_0 :
subtype (TArrow C TRcd_kj)
(TArrow C TRNil).
(* C->{k:A->A,j:B->B} <: C->{} *)
Proof.
apply S_Arrow.
apply S_Refl. auto.
unfold TRcd_kj, TRcd_j. apply S_RcdWidth; auto.
Qed.
(** The following facts are mostly easy to prove in Coq. To get full
benefit, make sure you also understand how to prove them on
paper! *)
(** **** Exercise: 2 stars (subtyping_example_1) *)
Example subtyping_example_1 :
subtype TRcd_kj TRcd_j.
(* {k:A->A,j:B->B} <: {j:B->B} *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star (subtyping_example_2) *)
Example subtyping_example_2 :
subtype (TArrow TTop TRcd_kj)
(TArrow (TArrow C C) TRcd_j).
(* Top->{k:A->A,j:B->B} <: (C->C)->{j:B->B} *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star (subtyping_example_3) *)
Example subtyping_example_3 :
subtype (TArrow TRNil (TRCons j A TRNil))
(TArrow (TRCons k B TRNil) TRNil).
(* {}->{j:A} <: {k:B}->{} *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (subtyping_example_4) *)
Example subtyping_example_4 :
subtype (TRCons x A (TRCons y B (TRCons z C TRNil)))
(TRCons z C (TRCons y B (TRCons x A TRNil))).
(* {x:A,y:B,z:C} <: {z:C,y:B,x:A} *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
End Examples.
(* ================================================================= *)
(** ** Properties of Subtyping *)
(* ----------------------------------------------------------------- *)
(** *** Well-Formedness *)
(** To get started proving things about subtyping, we need a couple of
technical lemmas that intuitively (1) allow us to extract the
well-formedness assumptions embedded in subtyping derivations
and (2) record the fact that fields of well-formed record types
are themselves well-formed types. *)
Lemma subtype__wf : forall S T,
subtype S T ->
well_formed_ty T /\ well_formed_ty S.
Proof with eauto.
intros S T Hsub.
induction Hsub;
intros; try (destruct IHHsub1; destruct IHHsub2)...
- (* S_RcdPerm *)
split... inversion H. subst. inversion H5... Qed.
Lemma wf_rcd_lookup : forall i T Ti,
well_formed_ty T ->
Tlookup i T = Some Ti ->
well_formed_ty Ti.
Proof with eauto.
intros i T.
induction T; intros; try solve_by_invert.
- (* TRCons *)
inversion H. subst. unfold Tlookup in H0.
destruct (beq_id i i0)... inversion H0; subst... Qed.
(* ----------------------------------------------------------------- *)
(** *** Field Lookup *)
(** The record matching lemmas get a little more complicated in the
presence of subtyping, for two reasons. First, record types no
longer necessarily describe the exact structure of the
corresponding terms. And second, reasoning by induction on typing
derivations becomes harder in general, because typing is no longer
syntax directed. *)
Lemma rcd_types_match : forall S T i Ti,
subtype S T ->
Tlookup i T = Some Ti ->
exists Si, Tlookup i S = Some Si /\ subtype Si Ti.
Proof with (eauto using wf_rcd_lookup).
intros S T i Ti Hsub Hget. generalize dependent Ti.
induction Hsub; intros Ti Hget;
try solve_by_invert.
- (* S_Refl *)
exists Ti...
- (* S_Trans *)
destruct (IHHsub2 Ti) as [Ui Hui]... destruct Hui.
destruct (IHHsub1 Ui) as [Si Hsi]... destruct Hsi.
exists Si...
- (* S_RcdDepth *)
rename i0 into k.
unfold Tlookup. unfold Tlookup in Hget.
destruct (beq_id i k)...
+ (* i = k -- we're looking up the first field *)
inversion Hget. subst. exists S1...
- (* S_RcdPerm *)
exists Ti. split.
+ (* lookup *)
unfold Tlookup. unfold Tlookup in Hget.
destruct (beq_idP i i1)...
* (* i = i1 -- we're looking up the first field *)
destruct (beq_idP i i2)...
(* i = i2 -- contradictory *)
destruct H0.
subst...
+ (* subtype *)
inversion H. subst. inversion H5. subst... Qed.
(** **** Exercise: 3 stars (rcd_types_match_informal) *)
(** Write a careful informal proof of the [rcd_types_match]
lemma. *)
(* FILL IN HERE *)
(** [] *)
(* ----------------------------------------------------------------- *)
(** *** Inversion Lemmas *)
(** **** Exercise: 3 stars, optional (sub_inversion_arrow) *)
Lemma sub_inversion_arrow : forall U V1 V2,
subtype U (TArrow V1 V2) ->
exists U1, exists U2,
(U=(TArrow U1 U2)) /\ (subtype V1 U1) /\ (subtype U2 V2).
Proof with eauto.
intros U V1 V2 Hs.
remember (TArrow V1 V2) as V.
generalize dependent V2. generalize dependent V1.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################################# *)
(** * Typing *)
Definition context := partial_map ty.
Reserved Notation "Gamma '|-' t '\in' T" (at level 40).
Inductive has_type : context -> tm -> ty -> Prop :=
| T_Var : forall Gamma x T,
Gamma x = Some T ->
well_formed_ty T ->
Gamma |- tvar x \in T
| T_Abs : forall Gamma x T11 T12 t12,
well_formed_ty T11 ->
update Gamma x T11 |- t12 \in T12 ->
Gamma |- tabs x T11 t12 \in TArrow T11 T12
| T_App : forall T1 T2 Gamma t1 t2,
Gamma |- t1 \in TArrow T1 T2 ->
Gamma |- t2 \in T1 ->
Gamma |- tapp t1 t2 \in T2
| T_Proj : forall Gamma i t T Ti,
Gamma |- t \in T ->
Tlookup i T = Some Ti ->
Gamma |- tproj t i \in Ti
(* Subsumption *)
| T_Sub : forall Gamma t S T,
Gamma |- t \in S ->
subtype S T ->
Gamma |- t \in T
(* Rules for record terms *)
| T_RNil : forall Gamma,
Gamma |- trnil \in TRNil
| T_RCons : forall Gamma i t T tr Tr,
Gamma |- t \in T ->
Gamma |- tr \in Tr ->
record_ty Tr ->
record_tm tr ->
Gamma |- trcons i t tr \in TRCons i T Tr
where "Gamma '|-' t '\in' T" := (has_type Gamma t T).
Hint Constructors has_type.
(* ================================================================= *)
(** ** Typing Examples *)
Module Examples2.
Import Examples.
(** **** Exercise: 1 star (typing_example_0) *)
Definition trcd_kj :=
(trcons k (tabs z A (tvar z))
(trcons j (tabs z B (tvar z))
trnil)).
Example typing_example_0 :
has_type empty
(trcons k (tabs z A (tvar z))
(trcons j (tabs z B (tvar z))
trnil))
TRcd_kj.
(* empty |- {k=(\z:A.z), j=(\z:B.z)} : {k:A->A,j:B->B} *)
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (typing_example_1) *)
Example typing_example_1 :
has_type empty
(tapp (tabs x TRcd_j (tproj (tvar x) j))
(trcd_kj))
(TArrow B B).
(* empty |- (\x:{k:A->A,j:B->B}. x.j)
{k=(\z:A.z), j=(\z:B.z)}
: B->B *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional (typing_example_2) *)
Example typing_example_2 :
has_type empty
(tapp (tabs z (TArrow (TArrow C C) TRcd_j)
(tproj (tapp (tvar z)
(tabs x C (tvar x)))
j))
(tabs z (TArrow C C) trcd_kj))
(TArrow B B).
(* empty |- (\z:(C->C)->{j:B->B}. (z (\x:C.x)).j)
(\z:C->C. {k=(\z:A.z), j=(\z:B.z)})
: B->B *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
End Examples2.
(* ================================================================= *)
(** ** Properties of Typing *)
(* ----------------------------------------------------------------- *)
(** *** Well-Formedness *)
Lemma has_type__wf : forall Gamma t T,
has_type Gamma t T -> well_formed_ty T.
Proof with eauto.
intros Gamma t T Htyp.
induction Htyp...
- (* T_App *)
inversion IHHtyp1...
- (* T_Proj *)
eapply wf_rcd_lookup...
- (* T_Sub *)
apply subtype__wf in H.
destruct H...
Qed.
Lemma step_preserves_record_tm : forall tr tr',
record_tm tr ->
tr ==> tr' ->
record_tm tr'.
Proof.
intros tr tr' Hrt Hstp.
inversion Hrt; subst; inversion Hstp; subst; eauto.
Qed.
(* ----------------------------------------------------------------- *)
(** *** Field Lookup *)
Lemma lookup_field_in_value : forall v T i Ti,
value v ->
has_type empty v T ->
Tlookup i T = Some Ti ->
exists vi, tlookup i v = Some vi /\ has_type empty vi Ti.
Proof with eauto.
remember empty as Gamma.
intros t T i Ti Hval Htyp. revert Ti HeqGamma Hval.
induction Htyp; intros; subst; try solve_by_invert.
- (* T_Sub *)
apply (rcd_types_match S) in H0...
destruct H0 as [Si [HgetSi Hsub]].
destruct (IHHtyp Si) as [vi [Hget Htyvi]]...
- (* T_RCons *)
simpl in H0. simpl. simpl in H1.
destruct (beq_id i i0).
+ (* i is first *)
inversion H1. subst. exists t...
+ (* i in tail *)
destruct (IHHtyp2 Ti) as [vi [get Htyvi]]...
inversion Hval... Qed.
(* ----------------------------------------------------------------- *)
(** *** Progress *)
(** **** Exercise: 3 stars (canonical_forms_of_arrow_types) *)
Lemma canonical_forms_of_arrow_types : forall Gamma s T1 T2,
has_type Gamma s (TArrow T1 T2) ->
value s ->
exists x, exists S1, exists s2,
s = tabs x S1 s2.
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
Theorem progress : forall t T,
has_type empty t T ->
value t \/ exists t', t ==> t'.
Proof with eauto.
intros t T Ht.
remember empty as Gamma.
revert HeqGamma.
induction Ht;
intros HeqGamma; subst...
- (* T_Var *)
inversion H.
- (* T_App *)
right.
destruct IHHt1; subst...
+ (* t1 is a value *)
destruct IHHt2; subst...
* (* t2 is a value *)
destruct (canonical_forms_of_arrow_types empty t1 T1 T2)
as [x [S1 [t12 Heqt1]]]...
subst. exists ([x:=t2]t12)...
* (* t2 steps *)
destruct H0 as [t2' Hstp]. exists (tapp t1 t2')...
+ (* t1 steps *)
destruct H as [t1' Hstp]. exists (tapp t1' t2)...
- (* T_Proj *)
right. destruct IHHt...
+ (* rcd is value *)
destruct (lookup_field_in_value t T i Ti)
as [t' [Hget Ht']]...
+ (* rcd_steps *)
destruct H0 as [t' Hstp]. exists (tproj t' i)...
- (* T_RCons *)
destruct IHHt1...
+ (* head is a value *)
destruct IHHt2...
* (* tail steps *)
right. destruct H2 as [tr' Hstp].
exists (trcons i t tr')...
+ (* head steps *)
right. destruct H1 as [t' Hstp].
exists (trcons i t' tr)... Qed.
(** _Theorem_ : For any term [t] and type [T], if [empty |- t : T]
then [t] is a value or [t ==> t'] for some term [t'].
_Proof_: Let [t] and [T] be given such that [empty |- t : T]. We
proceed by induction on the given typing derivation.
- The cases where the last step in the typing derivation is
[T_Abs] or [T_RNil] are immediate because abstractions and
[{}] are always values. The case for [T_Var] is vacuous
because variables cannot be typed in the empty context.
- If the last step in the typing derivation is by [T_App], then
there are terms [t1] [t2] and types [T1] [T2] such that [t =
t1 t2], [T = T2], [empty |- t1 : T1 -> T2] and [empty |- t2 :
T1].
The induction hypotheses for these typing derivations yield
that [t1] is a value or steps, and that [t2] is a value or
steps.
- Suppose [t1 ==> t1'] for some term [t1']. Then [t1 t2 ==>
t1' t2] by [ST_App1].
- Otherwise [t1] is a value.
- Suppose [t2 ==> t2'] for some term [t2']. Then [t1 t2 ==>
t1 t2'] by rule [ST_App2] because [t1] is a value.
- Otherwise, [t2] is a value. By Lemma
[canonical_forms_for_arrow_types], [t1 = \x:S1.s2] for
some [x], [S1], and [s2]. But then [(\x:S1.s2) t2 ==>
[x:=t2]s2] by [ST_AppAbs], since [t2] is a value.
- If the last step of the derivation is by [T_Proj], then there
are a term [tr], a type [Tr], and a label [i] such that [t =
tr.i], [empty |- tr : Tr], and [Tlookup i Tr = Some T].
By the IH, either [tr] is a value or it steps. If [tr ==>
tr'] for some term [tr'], then [tr.i ==> tr'.i] by rule
[ST_Proj1].
If [tr] is a value, then Lemma [lookup_field_in_value] yields
that there is a term [ti] such that [tlookup i tr = Some ti].
It follows that [tr.i ==> ti] by rule [ST_ProjRcd].
- If the final step of the derivation is by [T_Sub], then there
is a type [S] such that [S <: T] and [empty |- t : S]. The
desired result is exactly the induction hypothesis for the
typing subderivation.
- If the final step of the derivation is by [T_RCons], then
there exist some terms [t1] [tr], types [T1 Tr] and a label
[t] such that [t = {i=t1, tr}], [T = {i:T1, Tr}], [record_tm
tr], [record_tm Tr], [empty |- t1 : T1] and [empty |- tr :
Tr].
The induction hypotheses for these typing derivations yield
that [t1] is a value or steps, and that [tr] is a value or
steps. We consider each case:
- Suppose [t1 ==> t1'] for some term [t1']. Then [{i=t1, tr}
==> {i=t1', tr}] by rule [ST_Rcd_Head].
- Otherwise [t1] is a value.
- Suppose [tr ==> tr'] for some term [tr']. Then [{i=t1,
tr} ==> {i=t1, tr'}] by rule [ST_Rcd_Tail], since [t1] is
a value.
- Otherwise, [tr] is also a value. So, [{i=t1, tr}] is a
value by [v_rcons]. *)
(* ----------------------------------------------------------------- *)
(** *** Inversion Lemmas *)
Lemma typing_inversion_var : forall Gamma x T,
has_type Gamma (tvar x) T ->
exists S,
Gamma x = Some S /\ subtype S T.
Proof with eauto.
intros Gamma x T Hty.
remember (tvar x) as t.
induction Hty; intros;
inversion Heqt; subst; try solve_by_invert.
- (* T_Var *)
exists T...
- (* T_Sub *)
destruct IHHty as [U [Hctx HsubU]]... Qed.
Lemma typing_inversion_app : forall Gamma t1 t2 T2,
has_type Gamma (tapp t1 t2) T2 ->
exists T1,
has_type Gamma t1 (TArrow T1 T2) /\
has_type Gamma t2 T1.
Proof with eauto.
intros Gamma t1 t2 T2 Hty.
remember (tapp t1 t2) as t.
induction Hty; intros;
inversion Heqt; subst; try solve_by_invert.
- (* T_App *)
exists T1...
- (* T_Sub *)
destruct IHHty as [U1 [Hty1 Hty2]]...
assert (Hwf := has_type__wf _ _ _ Hty2).
exists U1... Qed.
Lemma typing_inversion_abs : forall Gamma x S1 t2 T,
has_type Gamma (tabs x S1 t2) T ->
(exists S2, subtype (TArrow S1 S2) T
/\ has_type (update Gamma x S1) t2 S2).
Proof with eauto.
intros Gamma x S1 t2 T H.
remember (tabs x S1 t2) as t.
induction H;
inversion Heqt; subst; intros; try solve_by_invert.
- (* T_Abs *)
assert (Hwf := has_type__wf _ _ _ H0).
exists T12...
- (* T_Sub *)
destruct IHhas_type as [S2 [Hsub Hty]]...
Qed.
Lemma typing_inversion_proj : forall Gamma i t1 Ti,
has_type Gamma (tproj t1 i) Ti ->
exists T, exists Si,
Tlookup i T = Some Si /\ subtype Si Ti /\ has_type Gamma t1 T.
Proof with eauto.
intros Gamma i t1 Ti H.
remember (tproj t1 i) as t.
induction H;
inversion Heqt; subst; intros; try solve_by_invert.
- (* T_Proj *)
assert (well_formed_ty Ti) as Hwf.
{ (* pf of assertion *)
apply (wf_rcd_lookup i T Ti)...
apply has_type__wf in H... }
exists T. exists Ti...
- (* T_Sub *)
destruct IHhas_type as [U [Ui [Hget [Hsub Hty]]]]...
exists U. exists Ui... Qed.
Lemma typing_inversion_rcons : forall Gamma i ti tr T,
has_type Gamma (trcons i ti tr) T ->
exists Si, exists Sr,
subtype (TRCons i Si Sr) T /\ has_type Gamma ti Si /\
record_tm tr /\ has_type Gamma tr Sr.
Proof with eauto.
intros Gamma i ti tr T Hty.
remember (trcons i ti tr) as t.
induction Hty;
inversion Heqt; subst...
- (* T_Sub *)
apply IHHty in H0.
destruct H0 as [Ri [Rr [HsubRS [HtypRi HtypRr]]]].
exists Ri. exists Rr...
- (* T_RCons *)
assert (well_formed_ty (TRCons i T Tr)) as Hwf.
{ (* pf of assertion *)
apply has_type__wf in Hty1.
apply has_type__wf in Hty2... }
exists T. exists Tr... Qed.
Lemma abs_arrow : forall x S1 s2 T1 T2,
has_type empty (tabs x S1 s2) (TArrow T1 T2) ->
subtype T1 S1
/\ has_type (update empty x S1) s2 T2.
Proof with eauto.
intros x S1 s2 T1 T2 Hty.
apply typing_inversion_abs in Hty.
destruct Hty as [S2 [Hsub Hty]].
apply sub_inversion_arrow in Hsub.
destruct Hsub as [U1 [U2 [Heq [Hsub1 Hsub2]]]].
inversion Heq; subst... Qed.
(* ----------------------------------------------------------------- *)
(** *** Context Invariance *)
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
| afi_proj : forall x t i,
appears_free_in x t ->
appears_free_in x (tproj t i)
| afi_rhead : forall x i t tr,
appears_free_in x t ->
appears_free_in x (trcons i t tr)
| afi_rtail : forall x i t tr,
appears_free_in x tr ->
appears_free_in x (trcons i t tr).
Hint Constructors appears_free_in.
Lemma context_invariance : forall Gamma Gamma' t S,
has_type Gamma t S ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
has_type Gamma' t S.
Proof with eauto.
intros. generalize dependent Gamma'.
induction H;
intros Gamma' Heqv...
- (* T_Var *)
apply T_Var... rewrite <- Heqv...
- (* T_Abs *)
apply T_Abs... apply IHhas_type. intros x0 Hafi.
unfold update, t_update. destruct (beq_idP x x0)...
- (* T_App *)
apply T_App with T1...
- (* T_RCons *)
apply T_RCons... Qed.
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
has_type Gamma t T ->
exists T', Gamma x = Some T'.
Proof with eauto.
intros x t T Gamma Hafi Htyp.
induction Htyp; subst; inversion Hafi; subst...
- (* T_Abs *)
destruct (IHHtyp H5) as [T Hctx]. exists T.
unfold update, t_update in Hctx.
rewrite false_beq_id in Hctx... Qed.
(* ----------------------------------------------------------------- *)
(** *** Preservation *)
Lemma substitution_preserves_typing : forall Gamma x U v t S,
has_type (update Gamma x U) t S ->
has_type empty v U ->
has_type Gamma ([x:=v]t) S.
Proof with eauto.
intros Gamma x U v t S Htypt Htypv.
generalize dependent S. generalize dependent Gamma.
induction t; intros; simpl.
- (* tvar *)
rename i into y.
destruct (typing_inversion_var _ _ _ Htypt) as [T [Hctx Hsub]].
unfold update, t_update in Hctx.
destruct (beq_idP x y)...
+ (* x=y *)
subst.
inversion Hctx; subst. clear Hctx.
apply context_invariance with empty...
intros x Hcontra.
destruct (free_in_context _ _ S empty Hcontra) as [T' HT']...
inversion HT'.
+ (* x<>y *)
destruct (subtype__wf _ _ Hsub)...
- (* tapp *)
destruct (typing_inversion_app _ _ _ _ Htypt)
as [T1 [Htypt1 Htypt2]].
eapply T_App...
- (* tabs *)
rename i into y. rename t into T1.
destruct (typing_inversion_abs _ _ _ _ _ Htypt)
as [T2 [Hsub Htypt2]].
destruct (subtype__wf _ _ Hsub) as [Hwf1 Hwf2].
inversion Hwf2. subst.
apply T_Sub with (TArrow T1 T2)... apply T_Abs...
destruct (beq_idP x y).
+ (* x=y *)
eapply context_invariance...
subst.
intros x Hafi. unfold update, t_update.
destruct (beq_id y x)...
+ (* x<>y *)
apply IHt. eapply context_invariance...
intros z Hafi. unfold update, t_update.
destruct (beq_idP y z)...
subst. rewrite false_beq_id...
- (* tproj *)
destruct (typing_inversion_proj _ _ _ _ Htypt)
as [T [Ti [Hget [Hsub Htypt1]]]]...
- (* trnil *)
eapply context_invariance...
intros y Hcontra. inversion Hcontra.
- (* trcons *)
destruct (typing_inversion_rcons _ _ _ _ _ Htypt) as
[Ti [Tr [Hsub [HtypTi [Hrcdt2 HtypTr]]]]].
apply T_Sub with (TRCons i Ti Tr)...
apply T_RCons...
+ (* record_ty Tr *)
apply subtype__wf in Hsub. destruct Hsub. inversion H0...
+ (* record_tm ([x:=v]t2) *)
inversion Hrcdt2; subst; simpl... Qed.
Theorem preservation : forall t t' T,
has_type empty t T ->
t ==> t' ->
has_type empty t' T.
Proof with eauto.
intros t t' T HT.
remember empty as Gamma. generalize dependent HeqGamma.
generalize dependent t'.
induction HT;
intros t' HeqGamma HE; subst; inversion HE; subst...
- (* T_App *)
inversion HE; subst...
+ (* ST_AppAbs *)
destruct (abs_arrow _ _ _ _ _ HT1) as [HA1 HA2].
apply substitution_preserves_typing with T...
- (* T_Proj *)
destruct (lookup_field_in_value _ _ _ _ H2 HT H)
as [vi [Hget Hty]].
rewrite H4 in Hget. inversion Hget. subst...
- (* T_RCons *)
eauto using step_preserves_record_tm. Qed.
(** _Theorem_: If [t], [t'] are terms and [T] is a type such that
[empty |- t : T] and [t ==> t'], then [empty |- t' : T].
_Proof_: Let [t] and [T] be given such that [empty |- t : T]. We go
by induction on the structure of this typing derivation, leaving
[t'] general. Cases [T_Abs] and [T_RNil] are vacuous because
abstractions and [{}] don't step. Case [T_Var] is vacuous as well,
since the context is empty.
- If the final step of the derivation is by [T_App], then there
are terms [t1] [t2] and types [T1] [T2] such that [t = t1 t2],
[T = T2], [empty |- t1 : T1 -> T2] and [empty |- t2 : T1].
By inspection of the definition of the step relation, there are
three ways [t1 t2] can step. Cases [ST_App1] and [ST_App2]
follow immediately by the induction hypotheses for the typing
subderivations and a use of [T_App].
Suppose instead [t1 t2] steps by [ST_AppAbs]. Then
[t1 = \x:S.t12] for some type [S] and term [t12], and
[t' = [x:=t2]t12].
By Lemma [abs_arrow], we have [T1 <: S] and [x:S1 |- s2 : T2].
It then follows by lemma [substitution_preserves_typing] that
[empty |- [x:=t2] t12 : T2] as desired.
- If the final step of the derivation is by [T_Proj], then there
is a term [tr], type [Tr] and label [i] such that [t = tr.i],
[empty |- tr : Tr], and [Tlookup i Tr = Some T].
The IH for the typing derivation gives us that, for any term
[tr'], if [tr ==> tr'] then [empty |- tr' Tr]. Inspection of
the definition of the step relation reveals that there are two
ways a projection can step. Case [ST_Proj1] follows
immediately by the IH.
Instead suppose [tr.i] steps by [ST_ProjRcd]. Then [tr] is a
value and there is some term [vi] such that
[tlookup i tr = Some vi] and [t' = vi]. But by lemma
[lookup_field_in_value], [empty |- vi : Ti] as desired.
- If the final step of the derivation is by [T_Sub], then there
is a type [S] such that [S <: T] and [empty |- t : S]. The
result is immediate by the induction hypothesis for the typing
subderivation and an application of [T_Sub].
- If the final step of the derivation is by [T_RCons], then there
exist some terms [t1] [tr], types [T1 Tr] and a label [t] such
that [t = {i=t1, tr}], [T = {i:T1, Tr}], [record_tm tr],
[record_tm Tr], [empty |- t1 : T1] and [empty |- tr : Tr].
By the definition of the step relation, [t] must have stepped
by [ST_Rcd_Head] or [ST_Rcd_Tail]. In the first case, the
result follows by the IH for [t1]'s typing derivation and
[T_RCons]. In the second case, the result follows by the IH
for [tr]'s typing derivation, [T_RCons], and a use of the
[step_preserves_record_tm] lemma. *)
(** $Date: 2017-05-17 16:11:21 -0400 (Wed, 17 May 2017) $ *)
|
/////////////////////////////////////////////////////////////////////
//// ////
//// JPEG Encoder Core - Verilog ////
//// ////
//// Author: David Lundgren ////
//// [email protected] ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 David Lundgren ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
/* This module converts the incoming Y data.
The incoming data is unsigned 8 bits, so the data is in the range of 0-255
Unlike a typical DCT, the data is not subtracted by 128 to center it around 0.
It is only required for the first row, and instead of subtracting 128 from each
pixel value, a total value can be subtracted at the end of the first row/column multiply,
involving the 8 pixel values and the 8 DCT matrix values.
For the other 7 rows of the DCT matrix, the values in each row add up to 0,
so it is not necessary to subtract 128 from each Y, Cb, and Cr pixel value.
Then the Discrete Cosine Transform is performed by multiplying the 8x8 pixel block values
by the 8x8 DCT matrix. */
`timescale 1ns / 100ps
module y_dct(clk, rst, enable, data_in,
Z11_final, Z12_final, Z13_final, Z14_final, Z15_final, Z16_final, Z17_final, Z18_final,
Z21_final, Z22_final, Z23_final, Z24_final, Z25_final, Z26_final, Z27_final, Z28_final,
Z31_final, Z32_final, Z33_final, Z34_final, Z35_final, Z36_final, Z37_final, Z38_final,
Z41_final, Z42_final, Z43_final, Z44_final, Z45_final, Z46_final, Z47_final, Z48_final,
Z51_final, Z52_final, Z53_final, Z54_final, Z55_final, Z56_final, Z57_final, Z58_final,
Z61_final, Z62_final, Z63_final, Z64_final, Z65_final, Z66_final, Z67_final, Z68_final,
Z71_final, Z72_final, Z73_final, Z74_final, Z75_final, Z76_final, Z77_final, Z78_final,
Z81_final, Z82_final, Z83_final, Z84_final, Z85_final, Z86_final, Z87_final, Z88_final,
output_enable);
input clk;
input rst;
input enable;
input [7:0] data_in;
output [10:0] Z11_final, Z12_final, Z13_final, Z14_final;
output [10:0] Z15_final, Z16_final, Z17_final, Z18_final;
output [10:0] Z21_final, Z22_final, Z23_final, Z24_final;
output [10:0] Z25_final, Z26_final, Z27_final, Z28_final;
output [10:0] Z31_final, Z32_final, Z33_final, Z34_final;
output [10:0] Z35_final, Z36_final, Z37_final, Z38_final;
output [10:0] Z41_final, Z42_final, Z43_final, Z44_final;
output [10:0] Z45_final, Z46_final, Z47_final, Z48_final;
output [10:0] Z51_final, Z52_final, Z53_final, Z54_final;
output [10:0] Z55_final, Z56_final, Z57_final, Z58_final;
output [10:0] Z61_final, Z62_final, Z63_final, Z64_final;
output [10:0] Z65_final, Z66_final, Z67_final, Z68_final;
output [10:0] Z71_final, Z72_final, Z73_final, Z74_final;
output [10:0] Z75_final, Z76_final, Z77_final, Z78_final;
output [10:0] Z81_final, Z82_final, Z83_final, Z84_final;
output [10:0] Z85_final, Z86_final, Z87_final, Z88_final;
output output_enable;
integer T1, T21, T22, T23, T24, T25, T26, T27, T28, T31, T32, T33, T34, T52;
integer Ti1, Ti21, Ti22, Ti23, Ti24, Ti25, Ti26, Ti27, Ti28, Ti31, Ti32, Ti33, Ti34, Ti52;
reg [24:0] Y_temp_11;
reg [24:0] Y11, Y21, Y31, Y41, Y51, Y61, Y71, Y81, Y11_final;
reg [31:0] Y_temp_21, Y_temp_31, Y_temp_41, Y_temp_51;
reg [31:0] Y_temp_61, Y_temp_71, Y_temp_81;
reg [31:0] Z_temp_11, Z_temp_12, Z_temp_13, Z_temp_14;
reg [31:0] Z_temp_15, Z_temp_16, Z_temp_17, Z_temp_18;
reg [31:0] Z_temp_21, Z_temp_22, Z_temp_23, Z_temp_24;
reg [31:0] Z_temp_25, Z_temp_26, Z_temp_27, Z_temp_28;
reg [31:0] Z_temp_31, Z_temp_32, Z_temp_33, Z_temp_34;
reg [31:0] Z_temp_35, Z_temp_36, Z_temp_37, Z_temp_38;
reg [31:0] Z_temp_41, Z_temp_42, Z_temp_43, Z_temp_44;
reg [31:0] Z_temp_45, Z_temp_46, Z_temp_47, Z_temp_48;
reg [31:0] Z_temp_51, Z_temp_52, Z_temp_53, Z_temp_54;
reg [31:0] Z_temp_55, Z_temp_56, Z_temp_57, Z_temp_58;
reg [31:0] Z_temp_61, Z_temp_62, Z_temp_63, Z_temp_64;
reg [31:0] Z_temp_65, Z_temp_66, Z_temp_67, Z_temp_68;
reg [31:0] Z_temp_71, Z_temp_72, Z_temp_73, Z_temp_74;
reg [31:0] Z_temp_75, Z_temp_76, Z_temp_77, Z_temp_78;
reg [31:0] Z_temp_81, Z_temp_82, Z_temp_83, Z_temp_84;
reg [31:0] Z_temp_85, Z_temp_86, Z_temp_87, Z_temp_88;
reg [26:0] Z11, Z12, Z13, Z14, Z15, Z16, Z17, Z18;
reg [26:0] Z21, Z22, Z23, Z24, Z25, Z26, Z27, Z28;
reg [26:0] Z31, Z32, Z33, Z34, Z35, Z36, Z37, Z38;
reg [26:0] Z41, Z42, Z43, Z44, Z45, Z46, Z47, Z48;
reg [26:0] Z51, Z52, Z53, Z54, Z55, Z56, Z57, Z58;
reg [26:0] Z61, Z62, Z63, Z64, Z65, Z66, Z67, Z68;
reg [26:0] Z71, Z72, Z73, Z74, Z75, Z76, Z77, Z78;
reg [26:0] Z81, Z82, Z83, Z84, Z85, Z86, Z87, Z88;
reg [31:0] Y11_final_2, Y21_final_2, Y11_final_3, Y11_final_4, Y31_final_2, Y41_final_2;
reg [31:0] Y51_final_2, Y61_final_2, Y71_final_2, Y81_final_2;
reg [12:0] Y11_final_1, Y21_final_1, Y31_final_1, Y41_final_1;
reg [12:0] Y51_final_1, Y61_final_1, Y71_final_1, Y81_final_1;
reg [24:0] Y21_final, Y31_final, Y41_final, Y51_final;
reg [24:0] Y61_final, Y71_final, Y81_final;
reg [24:0] Y21_final_prev, Y21_final_diff;
reg [24:0] Y31_final_prev, Y31_final_diff;
reg [24:0] Y41_final_prev, Y41_final_diff;
reg [24:0] Y51_final_prev, Y51_final_diff;
reg [24:0] Y61_final_prev, Y61_final_diff;
reg [24:0] Y71_final_prev, Y71_final_diff;
reg [24:0] Y81_final_prev, Y81_final_diff;
reg [10:0] Z11_final, Z12_final, Z13_final, Z14_final;
reg [10:0] Z15_final, Z16_final, Z17_final, Z18_final;
reg [10:0] Z21_final, Z22_final, Z23_final, Z24_final;
reg [10:0] Z25_final, Z26_final, Z27_final, Z28_final;
reg [10:0] Z31_final, Z32_final, Z33_final, Z34_final;
reg [10:0] Z35_final, Z36_final, Z37_final, Z38_final;
reg [10:0] Z41_final, Z42_final, Z43_final, Z44_final;
reg [10:0] Z45_final, Z46_final, Z47_final, Z48_final;
reg [10:0] Z51_final, Z52_final, Z53_final, Z54_final;
reg [10:0] Z55_final, Z56_final, Z57_final, Z58_final;
reg [10:0] Z61_final, Z62_final, Z63_final, Z64_final;
reg [10:0] Z65_final, Z66_final, Z67_final, Z68_final;
reg [10:0] Z71_final, Z72_final, Z73_final, Z74_final;
reg [10:0] Z75_final, Z76_final, Z77_final, Z78_final;
reg [10:0] Z81_final, Z82_final, Z83_final, Z84_final;
reg [10:0] Z85_final, Z86_final, Z87_final, Z88_final;
reg [2:0] count;
reg [2:0] count_of, count_of_copy;
reg count_1, count_3, count_4, count_5, count_6, count_7, count_8, enable_1, output_enable;
reg count_9, count_10;
reg [7:0] data_1;
integer Y2_mul_input, Y3_mul_input, Y4_mul_input, Y5_mul_input;
integer Y6_mul_input, Y7_mul_input, Y8_mul_input;
integer Ti2_mul_input, Ti3_mul_input, Ti4_mul_input, Ti5_mul_input;
integer Ti6_mul_input, Ti7_mul_input, Ti8_mul_input;
always @(posedge clk)
begin // DCT matrix entries
T1 = 5793; // .3536
T21 = 8035; // .4904
T22 = 6811; // .4157
T23 = 4551; // .2778
T24 = 1598; // .0975
T25 = -1598; // -.0975
T26 = -4551; // -.2778
T27 = -6811; // -.4157
T28 = -8035; // -.4904
T31 = 7568; // .4619
T32 = 3135; // .1913
T33 = -3135; // -.1913
T34 = -7568; // -.4619
T52 = -5793; // -.3536
end
always @(posedge clk)
begin // The inverse DCT matrix entries
Ti1 = 5793; // .3536
Ti21 = 8035; // .4904
Ti22 = 6811; // .4157
Ti23 = 4551; // .2778
Ti24 = 1598; // .0975
Ti25 = -1598; // -.0975
Ti26 = -4551; // -.2778
Ti27 = -6811; // -.4157
Ti28 = -8035; // -.4904
Ti31 = 7568; // .4619
Ti32 = 3135; // .1913
Ti33 = -3135; // -.1913
Ti34 = -7568; // -.4619
Ti52 = -5793; // -.3536
end
always @(posedge clk)
begin
if (rst) begin
Z_temp_11 <= 0; Z_temp_12 <= 0; Z_temp_13 <= 0; Z_temp_14 <= 0;
Z_temp_15 <= 0; Z_temp_16 <= 0; Z_temp_17 <= 0; Z_temp_18 <= 0;
Z_temp_21 <= 0; Z_temp_22 <= 0; Z_temp_23 <= 0; Z_temp_24 <= 0;
Z_temp_25 <= 0; Z_temp_26 <= 0; Z_temp_27 <= 0; Z_temp_28 <= 0;
Z_temp_31 <= 0; Z_temp_32 <= 0; Z_temp_33 <= 0; Z_temp_34 <= 0;
Z_temp_35 <= 0; Z_temp_36 <= 0; Z_temp_37 <= 0; Z_temp_38 <= 0;
Z_temp_41 <= 0; Z_temp_42 <= 0; Z_temp_43 <= 0; Z_temp_44 <= 0;
Z_temp_45 <= 0; Z_temp_46 <= 0; Z_temp_47 <= 0; Z_temp_48 <= 0;
Z_temp_51 <= 0; Z_temp_52 <= 0; Z_temp_53 <= 0; Z_temp_54 <= 0;
Z_temp_55 <= 0; Z_temp_56 <= 0; Z_temp_57 <= 0; Z_temp_58 <= 0;
Z_temp_61 <= 0; Z_temp_62 <= 0; Z_temp_63 <= 0; Z_temp_64 <= 0;
Z_temp_65 <= 0; Z_temp_66 <= 0; Z_temp_67 <= 0; Z_temp_68 <= 0;
Z_temp_71 <= 0; Z_temp_72 <= 0; Z_temp_73 <= 0; Z_temp_74 <= 0;
Z_temp_75 <= 0; Z_temp_76 <= 0; Z_temp_77 <= 0; Z_temp_78 <= 0;
Z_temp_81 <= 0; Z_temp_82 <= 0; Z_temp_83 <= 0; Z_temp_84 <= 0;
Z_temp_85 <= 0; Z_temp_86 <= 0; Z_temp_87 <= 0; Z_temp_88 <= 0;
end
else if (enable_1 & count_8) begin
Z_temp_11 <= Y11_final_4 * Ti1; Z_temp_12 <= Y11_final_4 * Ti2_mul_input;
Z_temp_13 <= Y11_final_4 * Ti3_mul_input; Z_temp_14 <= Y11_final_4 * Ti4_mul_input;
Z_temp_15 <= Y11_final_4 * Ti5_mul_input; Z_temp_16 <= Y11_final_4 * Ti6_mul_input;
Z_temp_17 <= Y11_final_4 * Ti7_mul_input; Z_temp_18 <= Y11_final_4 * Ti8_mul_input;
Z_temp_21 <= Y21_final_2 * Ti1; Z_temp_22 <= Y21_final_2 * Ti2_mul_input;
Z_temp_23 <= Y21_final_2 * Ti3_mul_input; Z_temp_24 <= Y21_final_2 * Ti4_mul_input;
Z_temp_25 <= Y21_final_2 * Ti5_mul_input; Z_temp_26 <= Y21_final_2 * Ti6_mul_input;
Z_temp_27 <= Y21_final_2 * Ti7_mul_input; Z_temp_28 <= Y21_final_2 * Ti8_mul_input;
Z_temp_31 <= Y31_final_2 * Ti1; Z_temp_32 <= Y31_final_2 * Ti2_mul_input;
Z_temp_33 <= Y31_final_2 * Ti3_mul_input; Z_temp_34 <= Y31_final_2 * Ti4_mul_input;
Z_temp_35 <= Y31_final_2 * Ti5_mul_input; Z_temp_36 <= Y31_final_2 * Ti6_mul_input;
Z_temp_37 <= Y31_final_2 * Ti7_mul_input; Z_temp_38 <= Y31_final_2 * Ti8_mul_input;
Z_temp_41 <= Y41_final_2 * Ti1; Z_temp_42 <= Y41_final_2 * Ti2_mul_input;
Z_temp_43 <= Y41_final_2 * Ti3_mul_input; Z_temp_44 <= Y41_final_2 * Ti4_mul_input;
Z_temp_45 <= Y41_final_2 * Ti5_mul_input; Z_temp_46 <= Y41_final_2 * Ti6_mul_input;
Z_temp_47 <= Y41_final_2 * Ti7_mul_input; Z_temp_48 <= Y41_final_2 * Ti8_mul_input;
Z_temp_51 <= Y51_final_2 * Ti1; Z_temp_52 <= Y51_final_2 * Ti2_mul_input;
Z_temp_53 <= Y51_final_2 * Ti3_mul_input; Z_temp_54 <= Y51_final_2 * Ti4_mul_input;
Z_temp_55 <= Y51_final_2 * Ti5_mul_input; Z_temp_56 <= Y51_final_2 * Ti6_mul_input;
Z_temp_57 <= Y51_final_2 * Ti7_mul_input; Z_temp_58 <= Y51_final_2 * Ti8_mul_input;
Z_temp_61 <= Y61_final_2 * Ti1; Z_temp_62 <= Y61_final_2 * Ti2_mul_input;
Z_temp_63 <= Y61_final_2 * Ti3_mul_input; Z_temp_64 <= Y61_final_2 * Ti4_mul_input;
Z_temp_65 <= Y61_final_2 * Ti5_mul_input; Z_temp_66 <= Y61_final_2 * Ti6_mul_input;
Z_temp_67 <= Y61_final_2 * Ti7_mul_input; Z_temp_68 <= Y61_final_2 * Ti8_mul_input;
Z_temp_71 <= Y71_final_2 * Ti1; Z_temp_72 <= Y71_final_2 * Ti2_mul_input;
Z_temp_73 <= Y71_final_2 * Ti3_mul_input; Z_temp_74 <= Y71_final_2 * Ti4_mul_input;
Z_temp_75 <= Y71_final_2 * Ti5_mul_input; Z_temp_76 <= Y71_final_2 * Ti6_mul_input;
Z_temp_77 <= Y71_final_2 * Ti7_mul_input; Z_temp_78 <= Y71_final_2 * Ti8_mul_input;
Z_temp_81 <= Y81_final_2 * Ti1; Z_temp_82 <= Y81_final_2 * Ti2_mul_input;
Z_temp_83 <= Y81_final_2 * Ti3_mul_input; Z_temp_84 <= Y81_final_2 * Ti4_mul_input;
Z_temp_85 <= Y81_final_2 * Ti5_mul_input; Z_temp_86 <= Y81_final_2 * Ti6_mul_input;
Z_temp_87 <= Y81_final_2 * Ti7_mul_input; Z_temp_88 <= Y81_final_2 * Ti8_mul_input;
end
end
always @(posedge clk)
begin
if (rst) begin
Z11 <= 0; Z12 <= 0; Z13 <= 0; Z14 <= 0; Z15 <= 0; Z16 <= 0; Z17 <= 0; Z18 <= 0;
Z21 <= 0; Z22 <= 0; Z23 <= 0; Z24 <= 0; Z25 <= 0; Z26 <= 0; Z27 <= 0; Z28 <= 0;
Z31 <= 0; Z32 <= 0; Z33 <= 0; Z34 <= 0; Z35 <= 0; Z36 <= 0; Z37 <= 0; Z38 <= 0;
Z41 <= 0; Z42 <= 0; Z43 <= 0; Z44 <= 0; Z45 <= 0; Z46 <= 0; Z47 <= 0; Z48 <= 0;
Z51 <= 0; Z52 <= 0; Z53 <= 0; Z54 <= 0; Z55 <= 0; Z56 <= 0; Z57 <= 0; Z58 <= 0;
Z61 <= 0; Z62 <= 0; Z63 <= 0; Z64 <= 0; Z65 <= 0; Z66 <= 0; Z67 <= 0; Z68 <= 0;
Z71 <= 0; Z72 <= 0; Z73 <= 0; Z74 <= 0; Z75 <= 0; Z76 <= 0; Z77 <= 0; Z78 <= 0;
Z81 <= 0; Z82 <= 0; Z83 <= 0; Z84 <= 0; Z85 <= 0; Z86 <= 0; Z87 <= 0; Z88 <= 0;
end
else if (count_8 & count_of == 1) begin
Z11 <= 0; Z12 <= 0; Z13 <= 0; Z14 <= 0;
Z15 <= 0; Z16 <= 0; Z17 <= 0; Z18 <= 0;
Z21 <= 0; Z22 <= 0; Z23 <= 0; Z24 <= 0;
Z25 <= 0; Z26 <= 0; Z27 <= 0; Z28 <= 0;
Z31 <= 0; Z32 <= 0; Z33 <= 0; Z34 <= 0;
Z35 <= 0; Z36 <= 0; Z37 <= 0; Z38 <= 0;
Z41 <= 0; Z42 <= 0; Z43 <= 0; Z44 <= 0;
Z45 <= 0; Z46 <= 0; Z47 <= 0; Z48 <= 0;
Z51 <= 0; Z52 <= 0; Z53 <= 0; Z54 <= 0;
Z55 <= 0; Z56 <= 0; Z57 <= 0; Z58 <= 0;
Z61 <= 0; Z62 <= 0; Z63 <= 0; Z64 <= 0;
Z65 <= 0; Z66 <= 0; Z67 <= 0; Z68 <= 0;
Z71 <= 0; Z72 <= 0; Z73 <= 0; Z74 <= 0;
Z75 <= 0; Z76 <= 0; Z77 <= 0; Z78 <= 0;
Z81 <= 0; Z82 <= 0; Z83 <= 0; Z84 <= 0;
Z85 <= 0; Z86 <= 0; Z87 <= 0; Z88 <= 0;
end
else if (enable & count_9) begin
Z11 <= Z_temp_11 + Z11; Z12 <= Z_temp_12 + Z12; Z13 <= Z_temp_13 + Z13; Z14 <= Z_temp_14 + Z14;
Z15 <= Z_temp_15 + Z15; Z16 <= Z_temp_16 + Z16; Z17 <= Z_temp_17 + Z17; Z18 <= Z_temp_18 + Z18;
Z21 <= Z_temp_21 + Z21; Z22 <= Z_temp_22 + Z22; Z23 <= Z_temp_23 + Z23; Z24 <= Z_temp_24 + Z24;
Z25 <= Z_temp_25 + Z25; Z26 <= Z_temp_26 + Z26; Z27 <= Z_temp_27 + Z27; Z28 <= Z_temp_28 + Z28;
Z31 <= Z_temp_31 + Z31; Z32 <= Z_temp_32 + Z32; Z33 <= Z_temp_33 + Z33; Z34 <= Z_temp_34 + Z34;
Z35 <= Z_temp_35 + Z35; Z36 <= Z_temp_36 + Z36; Z37 <= Z_temp_37 + Z37; Z38 <= Z_temp_38 + Z38;
Z41 <= Z_temp_41 + Z41; Z42 <= Z_temp_42 + Z42; Z43 <= Z_temp_43 + Z43; Z44 <= Z_temp_44 + Z44;
Z45 <= Z_temp_45 + Z45; Z46 <= Z_temp_46 + Z46; Z47 <= Z_temp_47 + Z47; Z48 <= Z_temp_48 + Z48;
Z51 <= Z_temp_51 + Z51; Z52 <= Z_temp_52 + Z52; Z53 <= Z_temp_53 + Z53; Z54 <= Z_temp_54 + Z54;
Z55 <= Z_temp_55 + Z55; Z56 <= Z_temp_56 + Z56; Z57 <= Z_temp_57 + Z57; Z58 <= Z_temp_58 + Z58;
Z61 <= Z_temp_61 + Z61; Z62 <= Z_temp_62 + Z62; Z63 <= Z_temp_63 + Z63; Z64 <= Z_temp_64 + Z64;
Z65 <= Z_temp_65 + Z65; Z66 <= Z_temp_66 + Z66; Z67 <= Z_temp_67 + Z67; Z68 <= Z_temp_68 + Z68;
Z71 <= Z_temp_71 + Z71; Z72 <= Z_temp_72 + Z72; Z73 <= Z_temp_73 + Z73; Z74 <= Z_temp_74 + Z74;
Z75 <= Z_temp_75 + Z75; Z76 <= Z_temp_76 + Z76; Z77 <= Z_temp_77 + Z77; Z78 <= Z_temp_78 + Z78;
Z81 <= Z_temp_81 + Z81; Z82 <= Z_temp_82 + Z82; Z83 <= Z_temp_83 + Z83; Z84 <= Z_temp_84 + Z84;
Z85 <= Z_temp_85 + Z85; Z86 <= Z_temp_86 + Z86; Z87 <= Z_temp_87 + Z87; Z88 <= Z_temp_88 + Z88;
end
end
always @(posedge clk)
begin
if (rst) begin
Z11_final <= 0; Z12_final <= 0; Z13_final <= 0; Z14_final <= 0;
Z15_final <= 0; Z16_final <= 0; Z17_final <= 0; Z18_final <= 0;
Z21_final <= 0; Z22_final <= 0; Z23_final <= 0; Z24_final <= 0;
Z25_final <= 0; Z26_final <= 0; Z27_final <= 0; Z28_final <= 0;
Z31_final <= 0; Z32_final <= 0; Z33_final <= 0; Z34_final <= 0;
Z35_final <= 0; Z36_final <= 0; Z37_final <= 0; Z38_final <= 0;
Z41_final <= 0; Z42_final <= 0; Z43_final <= 0; Z44_final <= 0;
Z45_final <= 0; Z46_final <= 0; Z47_final <= 0; Z48_final <= 0;
Z51_final <= 0; Z52_final <= 0; Z53_final <= 0; Z54_final <= 0;
Z55_final <= 0; Z56_final <= 0; Z57_final <= 0; Z58_final <= 0;
Z61_final <= 0; Z62_final <= 0; Z63_final <= 0; Z64_final <= 0;
Z65_final <= 0; Z66_final <= 0; Z67_final <= 0; Z68_final <= 0;
Z71_final <= 0; Z72_final <= 0; Z73_final <= 0; Z74_final <= 0;
Z75_final <= 0; Z76_final <= 0; Z77_final <= 0; Z78_final <= 0;
Z81_final <= 0; Z82_final <= 0; Z83_final <= 0; Z84_final <= 0;
Z85_final <= 0; Z86_final <= 0; Z87_final <= 0; Z88_final <= 0;
end
else if (count_10 & count_of == 0) begin
Z11_final <= Z11[15] ? Z11[26:16] + 1 : Z11[26:16];
Z12_final <= Z12[15] ? Z12[26:16] + 1 : Z12[26:16];
Z13_final <= Z13[15] ? Z13[26:16] + 1 : Z13[26:16];
Z14_final <= Z14[15] ? Z14[26:16] + 1 : Z14[26:16];
Z15_final <= Z15[15] ? Z15[26:16] + 1 : Z15[26:16];
Z16_final <= Z16[15] ? Z16[26:16] + 1 : Z16[26:16];
Z17_final <= Z17[15] ? Z17[26:16] + 1 : Z17[26:16];
Z18_final <= Z18[15] ? Z18[26:16] + 1 : Z18[26:16];
Z21_final <= Z21[15] ? Z21[26:16] + 1 : Z21[26:16];
Z22_final <= Z22[15] ? Z22[26:16] + 1 : Z22[26:16];
Z23_final <= Z23[15] ? Z23[26:16] + 1 : Z23[26:16];
Z24_final <= Z24[15] ? Z24[26:16] + 1 : Z24[26:16];
Z25_final <= Z25[15] ? Z25[26:16] + 1 : Z25[26:16];
Z26_final <= Z26[15] ? Z26[26:16] + 1 : Z26[26:16];
Z27_final <= Z27[15] ? Z27[26:16] + 1 : Z27[26:16];
Z28_final <= Z28[15] ? Z28[26:16] + 1 : Z28[26:16];
Z31_final <= Z31[15] ? Z31[26:16] + 1 : Z31[26:16];
Z32_final <= Z32[15] ? Z32[26:16] + 1 : Z32[26:16];
Z33_final <= Z33[15] ? Z33[26:16] + 1 : Z33[26:16];
Z34_final <= Z34[15] ? Z34[26:16] + 1 : Z34[26:16];
Z35_final <= Z35[15] ? Z35[26:16] + 1 : Z35[26:16];
Z36_final <= Z36[15] ? Z36[26:16] + 1 : Z36[26:16];
Z37_final <= Z37[15] ? Z37[26:16] + 1 : Z37[26:16];
Z38_final <= Z38[15] ? Z38[26:16] + 1 : Z38[26:16];
Z41_final <= Z41[15] ? Z41[26:16] + 1 : Z41[26:16];
Z42_final <= Z42[15] ? Z42[26:16] + 1 : Z42[26:16];
Z43_final <= Z43[15] ? Z43[26:16] + 1 : Z43[26:16];
Z44_final <= Z44[15] ? Z44[26:16] + 1 : Z44[26:16];
Z45_final <= Z45[15] ? Z45[26:16] + 1 : Z45[26:16];
Z46_final <= Z46[15] ? Z46[26:16] + 1 : Z46[26:16];
Z47_final <= Z47[15] ? Z47[26:16] + 1 : Z47[26:16];
Z48_final <= Z48[15] ? Z48[26:16] + 1 : Z48[26:16];
Z51_final <= Z51[15] ? Z51[26:16] + 1 : Z51[26:16];
Z52_final <= Z52[15] ? Z52[26:16] + 1 : Z52[26:16];
Z53_final <= Z53[15] ? Z53[26:16] + 1 : Z53[26:16];
Z54_final <= Z54[15] ? Z54[26:16] + 1 : Z54[26:16];
Z55_final <= Z55[15] ? Z55[26:16] + 1 : Z55[26:16];
Z56_final <= Z56[15] ? Z56[26:16] + 1 : Z56[26:16];
Z57_final <= Z57[15] ? Z57[26:16] + 1 : Z57[26:16];
Z58_final <= Z58[15] ? Z58[26:16] + 1 : Z58[26:16];
Z61_final <= Z61[15] ? Z61[26:16] + 1 : Z61[26:16];
Z62_final <= Z62[15] ? Z62[26:16] + 1 : Z62[26:16];
Z63_final <= Z63[15] ? Z63[26:16] + 1 : Z63[26:16];
Z64_final <= Z64[15] ? Z64[26:16] + 1 : Z64[26:16];
Z65_final <= Z65[15] ? Z65[26:16] + 1 : Z65[26:16];
Z66_final <= Z66[15] ? Z66[26:16] + 1 : Z66[26:16];
Z67_final <= Z67[15] ? Z67[26:16] + 1 : Z67[26:16];
Z68_final <= Z68[15] ? Z68[26:16] + 1 : Z68[26:16];
Z71_final <= Z71[15] ? Z71[26:16] + 1 : Z71[26:16];
Z72_final <= Z72[15] ? Z72[26:16] + 1 : Z72[26:16];
Z73_final <= Z73[15] ? Z73[26:16] + 1 : Z73[26:16];
Z74_final <= Z74[15] ? Z74[26:16] + 1 : Z74[26:16];
Z75_final <= Z75[15] ? Z75[26:16] + 1 : Z75[26:16];
Z76_final <= Z76[15] ? Z76[26:16] + 1 : Z76[26:16];
Z77_final <= Z77[15] ? Z77[26:16] + 1 : Z77[26:16];
Z78_final <= Z78[15] ? Z78[26:16] + 1 : Z78[26:16];
Z81_final <= Z81[15] ? Z81[26:16] + 1 : Z81[26:16];
Z82_final <= Z82[15] ? Z82[26:16] + 1 : Z82[26:16];
Z83_final <= Z83[15] ? Z83[26:16] + 1 : Z83[26:16];
Z84_final <= Z84[15] ? Z84[26:16] + 1 : Z84[26:16];
Z85_final <= Z85[15] ? Z85[26:16] + 1 : Z85[26:16];
Z86_final <= Z86[15] ? Z86[26:16] + 1 : Z86[26:16];
Z87_final <= Z87[15] ? Z87[26:16] + 1 : Z87[26:16];
Z88_final <= Z88[15] ? Z88[26:16] + 1 : Z88[26:16];
end
end
// output_enable signals the next block, the quantizer, that the input data is ready
always @(posedge clk)
begin
if (rst)
output_enable <= 0;
else if (!enable_1)
output_enable <= 0;
else if (count_10 == 0 | count_of)
output_enable <= 0;
else if (count_10 & count_of == 0)
output_enable <= 1;
end
always @(posedge clk)
begin
if (rst)
Y_temp_11 <= 0;
else if (enable)
Y_temp_11 <= data_in * T1;
end
always @(posedge clk)
begin
if (rst)
Y11 <= 0;
else if (count == 1 & enable == 1)
Y11 <= Y_temp_11;
else if (enable)
Y11 <= Y_temp_11 + Y11;
end
always @(posedge clk)
begin
if (rst) begin
Y_temp_21 <= 0;
Y_temp_31 <= 0;
Y_temp_41 <= 0;
Y_temp_51 <= 0;
Y_temp_61 <= 0;
Y_temp_71 <= 0;
Y_temp_81 <= 0;
end
else if (!enable_1) begin
Y_temp_21 <= 0;
Y_temp_31 <= 0;
Y_temp_41 <= 0;
Y_temp_51 <= 0;
Y_temp_61 <= 0;
Y_temp_71 <= 0;
Y_temp_81 <= 0;
end
else if (enable_1) begin
Y_temp_21 <= data_1 * Y2_mul_input;
Y_temp_31 <= data_1 * Y3_mul_input;
Y_temp_41 <= data_1 * Y4_mul_input;
Y_temp_51 <= data_1 * Y5_mul_input;
Y_temp_61 <= data_1 * Y6_mul_input;
Y_temp_71 <= data_1 * Y7_mul_input;
Y_temp_81 <= data_1 * Y8_mul_input;
end
end
always @(posedge clk)
begin
if (rst) begin
Y21 <= 0;
Y31 <= 0;
Y41 <= 0;
Y51 <= 0;
Y61 <= 0;
Y71 <= 0;
Y81 <= 0;
end
else if (!enable_1) begin
Y21 <= 0;
Y31 <= 0;
Y41 <= 0;
Y51 <= 0;
Y61 <= 0;
Y71 <= 0;
Y81 <= 0;
end
else if (enable_1) begin
Y21 <= Y_temp_21 + Y21;
Y31 <= Y_temp_31 + Y31;
Y41 <= Y_temp_41 + Y41;
Y51 <= Y_temp_51 + Y51;
Y61 <= Y_temp_61 + Y61;
Y71 <= Y_temp_71 + Y71;
Y81 <= Y_temp_81 + Y81;
end
end
always @(posedge clk)
begin
if (rst) begin
count <= 0; count_3 <= 0; count_4 <= 0; count_5 <= 0;
count_6 <= 0; count_7 <= 0; count_8 <= 0; count_9 <= 0;
count_10 <= 0;
end
else if (!enable) begin
count <= 0; count_3 <= 0; count_4 <= 0; count_5 <= 0;
count_6 <= 0; count_7 <= 0; count_8 <= 0; count_9 <= 0;
count_10 <= 0;
end
else if (enable) begin
count <= count + 1; count_3 <= count_1; count_4 <= count_3;
count_5 <= count_4; count_6 <= count_5; count_7 <= count_6;
count_8 <= count_7; count_9 <= count_8; count_10 <= count_9;
end
end
always @(posedge clk)
begin
if (rst) begin
count_1 <= 0;
end
else if (count != 7 | !enable) begin
count_1 <= 0;
end
else if (count == 7) begin
count_1 <= 1;
end
end
always @(posedge clk)
begin
if (rst) begin
count_of <= 0;
count_of_copy <= 0;
end
else if (!enable) begin
count_of <= 0;
count_of_copy <= 0;
end
else if (count_1 == 1) begin
count_of <= count_of + 1;
count_of_copy <= count_of_copy + 1;
end
end
always @(posedge clk)
begin
if (rst) begin
Y11_final <= 0;
end
else if (count_3 & enable_1) begin
Y11_final <= Y11 - 25'd5932032;
/* The Y values weren't centered on 0 before doing the DCT
128 needs to be subtracted from each Y value before, or in this
case, 362 is subtracted from the total, because this is the
total obtained by subtracting 128 from each element
and then multiplying by the weight
assigned by the DCT matrix : 128*8*5793 = 5932032
This is only needed for the first row, the values in the rest of
the rows add up to 0 */
end
end
always @(posedge clk)
begin
if (rst) begin
Y21_final <= 0; Y21_final_prev <= 0;
Y31_final <= 0; Y31_final_prev <= 0;
Y41_final <= 0; Y41_final_prev <= 0;
Y51_final <= 0; Y51_final_prev <= 0;
Y61_final <= 0; Y61_final_prev <= 0;
Y71_final <= 0; Y71_final_prev <= 0;
Y81_final <= 0; Y81_final_prev <= 0;
end
else if (!enable_1) begin
Y21_final <= 0; Y21_final_prev <= 0;
Y31_final <= 0; Y31_final_prev <= 0;
Y41_final <= 0; Y41_final_prev <= 0;
Y51_final <= 0; Y51_final_prev <= 0;
Y61_final <= 0; Y61_final_prev <= 0;
Y71_final <= 0; Y71_final_prev <= 0;
Y81_final <= 0; Y81_final_prev <= 0;
end
else if (count_4 & enable_1) begin
Y21_final <= Y21; Y21_final_prev <= Y21_final;
Y31_final <= Y31; Y31_final_prev <= Y31_final;
Y41_final <= Y41; Y41_final_prev <= Y41_final;
Y51_final <= Y51; Y51_final_prev <= Y51_final;
Y61_final <= Y61; Y61_final_prev <= Y61_final;
Y71_final <= Y71; Y71_final_prev <= Y71_final;
Y81_final <= Y81; Y81_final_prev <= Y81_final;
end
end
always @(posedge clk)
begin
if (rst) begin
Y21_final_diff <= 0; Y31_final_diff <= 0;
Y41_final_diff <= 0; Y51_final_diff <= 0;
Y61_final_diff <= 0; Y71_final_diff <= 0;
Y81_final_diff <= 0;
end
else if (count_5 & enable_1) begin
Y21_final_diff <= Y21_final - Y21_final_prev;
Y31_final_diff <= Y31_final - Y31_final_prev;
Y41_final_diff <= Y41_final - Y41_final_prev;
Y51_final_diff <= Y51_final - Y51_final_prev;
Y61_final_diff <= Y61_final - Y61_final_prev;
Y71_final_diff <= Y71_final - Y71_final_prev;
Y81_final_diff <= Y81_final - Y81_final_prev;
end
end
always @(posedge clk)
begin
case (count)
3'b000: Y2_mul_input <= T21;
3'b001: Y2_mul_input <= T22;
3'b010: Y2_mul_input <= T23;
3'b011: Y2_mul_input <= T24;
3'b100: Y2_mul_input <= T25;
3'b101: Y2_mul_input <= T26;
3'b110: Y2_mul_input <= T27;
3'b111: Y2_mul_input <= T28;
endcase
end
always @(posedge clk)
begin
case (count)
3'b000: Y3_mul_input <= T31;
3'b001: Y3_mul_input <= T32;
3'b010: Y3_mul_input <= T33;
3'b011: Y3_mul_input <= T34;
3'b100: Y3_mul_input <= T34;
3'b101: Y3_mul_input <= T33;
3'b110: Y3_mul_input <= T32;
3'b111: Y3_mul_input <= T31;
endcase
end
always @(posedge clk)
begin
case (count)
3'b000: Y4_mul_input <= T22;
3'b001: Y4_mul_input <= T25;
3'b010: Y4_mul_input <= T28;
3'b011: Y4_mul_input <= T26;
3'b100: Y4_mul_input <= T23;
3'b101: Y4_mul_input <= T21;
3'b110: Y4_mul_input <= T24;
3'b111: Y4_mul_input <= T27;
endcase
end
always @(posedge clk)
begin
case (count)
3'b000: Y5_mul_input <= T1;
3'b001: Y5_mul_input <= T52;
3'b010: Y5_mul_input <= T52;
3'b011: Y5_mul_input <= T1;
3'b100: Y5_mul_input <= T1;
3'b101: Y5_mul_input <= T52;
3'b110: Y5_mul_input <= T52;
3'b111: Y5_mul_input <= T1;
endcase
end
always @(posedge clk)
begin
case (count)
3'b000: Y6_mul_input <= T23;
3'b001: Y6_mul_input <= T28;
3'b010: Y6_mul_input <= T24;
3'b011: Y6_mul_input <= T22;
3'b100: Y6_mul_input <= T27;
3'b101: Y6_mul_input <= T25;
3'b110: Y6_mul_input <= T21;
3'b111: Y6_mul_input <= T26;
endcase
end
always @(posedge clk)
begin
case (count)
3'b000: Y7_mul_input <= T32;
3'b001: Y7_mul_input <= T34;
3'b010: Y7_mul_input <= T31;
3'b011: Y7_mul_input <= T33;
3'b100: Y7_mul_input <= T33;
3'b101: Y7_mul_input <= T31;
3'b110: Y7_mul_input <= T34;
3'b111: Y7_mul_input <= T32;
endcase
end
always @(posedge clk)
begin
case (count)
3'b000: Y8_mul_input <= T24;
3'b001: Y8_mul_input <= T26;
3'b010: Y8_mul_input <= T22;
3'b011: Y8_mul_input <= T28;
3'b100: Y8_mul_input <= T21;
3'b101: Y8_mul_input <= T27;
3'b110: Y8_mul_input <= T23;
3'b111: Y8_mul_input <= T25;
endcase
end
// Inverse DCT matrix entries
always @(posedge clk)
begin
case (count_of_copy)
3'b000: Ti2_mul_input <= Ti28;
3'b001: Ti2_mul_input <= Ti21;
3'b010: Ti2_mul_input <= Ti22;
3'b011: Ti2_mul_input <= Ti23;
3'b100: Ti2_mul_input <= Ti24;
3'b101: Ti2_mul_input <= Ti25;
3'b110: Ti2_mul_input <= Ti26;
3'b111: Ti2_mul_input <= Ti27;
endcase
end
always @(posedge clk)
begin
case (count_of_copy)
3'b000: Ti3_mul_input <= Ti31;
3'b001: Ti3_mul_input <= Ti31;
3'b010: Ti3_mul_input <= Ti32;
3'b011: Ti3_mul_input <= Ti33;
3'b100: Ti3_mul_input <= Ti34;
3'b101: Ti3_mul_input <= Ti34;
3'b110: Ti3_mul_input <= Ti33;
3'b111: Ti3_mul_input <= Ti32;
endcase
end
always @(posedge clk)
begin
case (count_of_copy)
3'b000: Ti4_mul_input <= Ti27;
3'b001: Ti4_mul_input <= Ti22;
3'b010: Ti4_mul_input <= Ti25;
3'b011: Ti4_mul_input <= Ti28;
3'b100: Ti4_mul_input <= Ti26;
3'b101: Ti4_mul_input <= Ti23;
3'b110: Ti4_mul_input <= Ti21;
3'b111: Ti4_mul_input <= Ti24;
endcase
end
always @(posedge clk)
begin
case (count_of_copy)
3'b000: Ti5_mul_input <= Ti1;
3'b001: Ti5_mul_input <= Ti1;
3'b010: Ti5_mul_input <= Ti52;
3'b011: Ti5_mul_input <= Ti52;
3'b100: Ti5_mul_input <= Ti1;
3'b101: Ti5_mul_input <= Ti1;
3'b110: Ti5_mul_input <= Ti52;
3'b111: Ti5_mul_input <= Ti52;
endcase
end
always @(posedge clk)
begin
case (count_of_copy)
3'b000: Ti6_mul_input <= Ti26;
3'b001: Ti6_mul_input <= Ti23;
3'b010: Ti6_mul_input <= Ti28;
3'b011: Ti6_mul_input <= Ti24;
3'b100: Ti6_mul_input <= Ti22;
3'b101: Ti6_mul_input <= Ti27;
3'b110: Ti6_mul_input <= Ti25;
3'b111: Ti6_mul_input <= Ti21;
endcase
end
always @(posedge clk)
begin
case (count_of_copy)
3'b000: Ti7_mul_input <= Ti32;
3'b001: Ti7_mul_input <= Ti32;
3'b010: Ti7_mul_input <= Ti34;
3'b011: Ti7_mul_input <= Ti31;
3'b100: Ti7_mul_input <= Ti33;
3'b101: Ti7_mul_input <= Ti33;
3'b110: Ti7_mul_input <= Ti31;
3'b111: Ti7_mul_input <= Ti34;
endcase
end
always @(posedge clk)
begin
case (count_of_copy)
3'b000: Ti8_mul_input <= Ti25;
3'b001: Ti8_mul_input <= Ti24;
3'b010: Ti8_mul_input <= Ti26;
3'b011: Ti8_mul_input <= Ti22;
3'b100: Ti8_mul_input <= Ti28;
3'b101: Ti8_mul_input <= Ti21;
3'b110: Ti8_mul_input <= Ti27;
3'b111: Ti8_mul_input <= Ti23;
endcase
end
// Rounding stage
always @(posedge clk)
begin
if (rst) begin
data_1 <= 0;
Y11_final_1 <= 0; Y21_final_1 <= 0; Y31_final_1 <= 0; Y41_final_1 <= 0;
Y51_final_1 <= 0; Y61_final_1 <= 0; Y71_final_1 <= 0; Y81_final_1 <= 0;
Y11_final_2 <= 0; Y21_final_2 <= 0; Y31_final_2 <= 0; Y41_final_2 <= 0;
Y51_final_2 <= 0; Y61_final_2 <= 0; Y71_final_2 <= 0; Y81_final_2 <= 0;
Y11_final_3 <= 0; Y11_final_4 <= 0;
end
else if (enable) begin
data_1 <= data_in;
Y11_final_1 <= Y11_final[11] ? Y11_final[24:12] + 1 : Y11_final[24:12];
Y11_final_2[31:13] <= Y11_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Y11_final_2[12:0] <= Y11_final_1;
// Need to sign extend Y11_final_1 and the other registers to store a negative
// number as a twos complement number. If you don't sign extend, then a negative number
// will be stored incorrectly as a positive number. For example, -215 would be stored
// as 1833 without sign extending
Y11_final_3 <= Y11_final_2;
Y11_final_4 <= Y11_final_3;
Y21_final_1 <= Y21_final_diff[11] ? Y21_final_diff[24:12] + 1 : Y21_final_diff[24:12];
Y21_final_2[31:13] <= Y21_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Y21_final_2[12:0] <= Y21_final_1;
Y31_final_1 <= Y31_final_diff[11] ? Y31_final_diff[24:12] + 1 : Y31_final_diff[24:12];
Y31_final_2[31:13] <= Y31_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Y31_final_2[12:0] <= Y31_final_1;
Y41_final_1 <= Y41_final_diff[11] ? Y41_final_diff[24:12] + 1 : Y41_final_diff[24:12];
Y41_final_2[31:13] <= Y41_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Y41_final_2[12:0] <= Y41_final_1;
Y51_final_1 <= Y51_final_diff[11] ? Y51_final_diff[24:12] + 1 : Y51_final_diff[24:12];
Y51_final_2[31:13] <= Y51_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Y51_final_2[12:0] <= Y51_final_1;
Y61_final_1 <= Y61_final_diff[11] ? Y61_final_diff[24:12] + 1 : Y61_final_diff[24:12];
Y61_final_2[31:13] <= Y61_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Y61_final_2[12:0] <= Y61_final_1;
Y71_final_1 <= Y71_final_diff[11] ? Y71_final_diff[24:12] + 1 : Y71_final_diff[24:12];
Y71_final_2[31:13] <= Y71_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Y71_final_2[12:0] <= Y71_final_1;
Y81_final_1 <= Y81_final_diff[11] ? Y81_final_diff[24:12] + 1 : Y81_final_diff[24:12];
Y81_final_2[31:13] <= Y81_final_1[12] ? 21'b111111111111111111111 : 21'b000000000000000000000;
Y81_final_2[12:0] <= Y81_final_1;
// The bit in place 11 is the fraction part, for rounding purposes
// if it is 1, then you need to add 1 to the bits in 24-12,
// if bit 11 is 0, then the bits in 24-12 won't change
end
end
always @(posedge clk)
begin
if (rst) begin
enable_1 <= 0;
end
else begin
enable_1 <= enable;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND4BB_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__AND4BB_BEHAVIORAL_PP_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__and4bb (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A_N, B_N );
and and0 (and0_out_X , nor0_out, C, D );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND4BB_BEHAVIORAL_PP_V |
`include "hrfp_defs.vh"
module hrfp_align
#(parameter PIPELINESTAGES=5)
(input wire clk,
input wire [2:0] expdiff_2,
input wire expdiff_saturated_2,
output reg expdiff_msb_3,
input wire [`MSBBIT:0] op2_a, op2_b,
output reg [`MSBBIT:0] op3_a, op3_b,
output reg [30:0] mantissa_3_align0, mantissa_3_align1
);
always @(posedge clk) begin
expdiff_msb_3 <= expdiff_2[2];
// We divide this 8-1 mux into two 4-1 muxes. The final 2-1 mux
// is in the next stage where it will be merged into the same
// LUTs used for the adder.
case(expdiff_2[1:0])
0: mantissa_3_align0 <= {1'b0, op2_b`MANTISSA, 3'b0};
1: mantissa_3_align0 <= {5'b0, op2_b[26:2] , |op2_b[1:0]};
2: mantissa_3_align0 <= {9'b0, op2_b[26:6] , |op2_b[5:0]};
3: mantissa_3_align0 <= {13'b0, op2_b[26:10], |op2_b[9:0]};
endcase // case (expdiff_2[1:0])
case(expdiff_2[1:0])
0: mantissa_3_align1 <= {17'b0, op2_b[26:14], |op2_b[13:0]};
1: mantissa_3_align1 <= {21'b0, op2_b[26:18], |op2_b[17:0]};
2: mantissa_3_align1 <= {25'b0, op2_b[26:22], |op2_b[21:0]};
3: mantissa_3_align1 <= {28'b0, op2_b[26], |op2_b[25:0]};
endcase // case (expdiff_2[1:0])
// Note: This may be a bit pessimistic, there may be other ways
// to solve this particular case.
if(expdiff_saturated_2) begin
mantissa_3_align1 <= |op2_b[26:0];
end
end
always @(posedge clk) begin
op3_a <= op2_a;
op3_b <= op2_b;
end // always @ (posedge clk)
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR4BB_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__NOR4BB_PP_BLACKBOX_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nor4bb (
Y ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR4BB_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O21AI_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__O21AI_PP_BLACKBOX_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o21ai (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O21AI_PP_BLACKBOX_V
|
(** * PE: Partial Evaluation *)
(* Chapter written and maintained by Chung-chieh Shan *)
(** The [Equiv] chapter introduced constant folding as an example of a
program transformation and proved that it preserves the meaning of
programs. Constant folding operates on manifest constants such as
[ANum] expressions. For example, it simplifies the command [Y :=
3 + 1] to the command [Y := 4]. However,
it does not propagate known constants along data flow. For
example, it does not simplify the sequence
X := 3; Y := X + 1
to
X := 3; Y := 4
because it forgets that [X] is [3] by the time it gets to [Y].
We might naturally want to enhance constant folding so that it
propagates known constants and uses them to simplify programs.
Doing so constitutes a rudimentary form of _partial evaluation_.
As we will see, partial evaluation is so called because it is like
running a program, except only part of the program can be
evaluated because only part of the input to the program is known.
For example, we can only simplify the program
X := 3; Y := (X + 1) - Y
to
X := 3; Y := 4 - Y
without knowing the initial value of [Y]. *)
From PLF Require Import Maps.
From Coq Require Import Bool.Bool.
From Coq Require Import Arith.Arith.
From Coq Require Import Arith.EqNat.
From Coq Require Import Arith.PeanoNat. Import Nat.
From Coq Require Import Lia.
From Coq Require Import Logic.FunctionalExtensionality.
From Coq Require Import Lists.List.
Import ListNotations.
From PLF Require Import Smallstep.
From PLF Require Import Imp.
(* ################################################################# *)
(** * Generalizing Constant Folding *)
(** The starting point of partial evaluation is to represent our
partial knowledge about the state. For example, between the two
assignments above, the partial evaluator may know only that [X] is
[3] and nothing about any other variable. *)
(* ================================================================= *)
(** ** Partial States *)
(** Conceptually speaking, we can think of such partial states as the
type [string -> option nat] (as opposed to the type [string -> nat] of
concrete, full states). However, in addition to looking up and
updating the values of individual variables in a partial state, we
may also want to compare two partial states to see if and where
they differ, to handle conditional control flow. It is not possible
to compare two arbitrary functions in this way, so we represent
partial states in a more concrete format: as a list of [string * nat]
pairs. *)
Definition pe_state := list (string * nat).
(** The idea is that a variable (of type [string]) appears in the list if and only
if we know its current [nat] value. The [pe_lookup] function thus
interprets this concrete representation. (If the same variable
appears multiple times in the list, the first occurrence
wins, but we will define our partial evaluator to never construct
such a [pe_state].) *)
Fixpoint pe_lookup (pe_st : pe_state) (V:string) : option nat :=
match pe_st with
| [] => None
| (V',n')::pe_st => if eqb_string V V' then Some n'
else pe_lookup pe_st V
end.
(** For example, [empty_pe_state] represents complete ignorance about
every variable -- the function that maps every identifier to [None]. *)
Definition empty_pe_state : pe_state := [].
(** More generally, if the [list] representing a [pe_state] does not
contain some identifier, then that [pe_state] must map that identifier to
[None]. Before we prove this fact, we first define a useful
tactic for reasoning with [string] equality. The tactic
compare V V'
means to reason by cases over [eqb_string V V'].
In the case where [V = V'], the tactic
substitutes [V] for [V'] throughout. *)
Tactic Notation "compare" ident(i) ident(j) :=
let H := fresh "Heq" i j in
destruct (eqb_stringP i j);
[ subst j | ].
Theorem pe_domain: forall pe_st V n,
pe_lookup pe_st V = Some n ->
In V (map (@fst _ _) pe_st).
Proof. intros pe_st V n H. induction pe_st as [| [V' n'] pe_st].
- (* [] *) inversion H.
- (* :: *) simpl in H. simpl. compare V V'; auto. Qed.
(** In what follows, we will make heavy use of the [In] property from
the standard library, also defined in [Logic.v]: *)
Print In.
(* ===> Fixpoint In {A:Type} (a: A) (l:list A) : Prop :=
match l with
| [] => False
| b :: m => b = a \/ In a m
end
: forall A : Type, A -> list A -> Prop *)
(** Besides the various lemmas about [In] that we've already come
across, the following one (taken from the standard library) will
also be useful: *)
Check filter_In.
(* ===> filter_In : forall (A : Type) (f : A -> bool) (x : A) (l : list A),
In x (filter f l) <-> In x l /\ f x = true *)
(** If a type [A] has an operator [eqb] for testing equality of its
elements, we can compute a boolean [inb eqb a l] for testing
whether [In a l] holds or not. *)
Fixpoint inb {A : Type} (eqb : A -> A -> bool) (a : A) (l : list A) :=
match l with
| [] => false
| a'::l' => eqb a a' || inb eqb a l'
end.
(** It is easy to relate [inb] to [In] with the [reflect] property: *)
Lemma inbP : forall A : Type, forall eqb : A->A->bool,
(forall a1 a2, reflect (a1 = a2) (eqb a1 a2)) ->
forall a l, reflect (In a l) (inb eqb a l).
Proof.
intros A eqb beqP a l.
induction l as [|a' l' IH].
- constructor. intros [].
- simpl. destruct (beqP a a').
+ subst. constructor. left. reflexivity.
+ simpl. destruct IH; constructor.
* right. trivial.
* intros [H1 | H2]; congruence.
Qed.
(* ================================================================= *)
(** ** Arithmetic Expressions *)
(** Partial evaluation of [aexp] is straightforward -- it is basically
the same as constant folding, [fold_constants_aexp], except that
sometimes the partial state tells us the current value of a
variable and we can replace it by a constant expression. *)
Fixpoint pe_aexp (pe_st : pe_state) (a : aexp) : aexp :=
match a with
| ANum n => ANum n
| AId i => match pe_lookup pe_st i with (* <----- NEW *)
| Some n => ANum n
| None => AId i
end
| <{ a1 + a2 }> =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 + n2)
| (a1', a2') => <{ a1' + a2' }>
end
| <{ a1 - a2 }> =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 - n2)
| (a1', a2') => <{ a1' - a2' }>
end
| <{ a1 * a2 }> =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 * n2)
| (a1', a2') => <{ a1' * a2' }>
end
end.
(** This partial evaluator folds constants but does not apply the
associativity of addition. *)
Example test_pe_aexp1:
pe_aexp [(X,3)] <{X + 1 + Y}>
= <{4 + Y}>.
Proof. reflexivity. Qed.
Example text_pe_aexp2:
pe_aexp [(Y,3)] <{X + 1 + Y}>
= <{X + 1 + 3}>.
Proof. reflexivity. Qed.
(** Now, in what sense is [pe_aexp] correct? It is reasonable to
define the correctness of [pe_aexp] as follows: whenever a full
state [st:state] is _consistent_ with a partial state
[pe_st:pe_state] (in other words, every variable to which [pe_st]
assigns a value is assigned the same value by [st]), evaluating
[a] and evaluating [pe_aexp pe_st a] in [st] yields the same
result. This statement is indeed true. *)
Definition pe_consistent (st:state) (pe_st:pe_state) :=
forall V n, Some n = pe_lookup pe_st V -> st V = n.
Theorem pe_aexp_correct_weak: forall st pe_st, pe_consistent st pe_st ->
forall a, aeval st a = aeval st (pe_aexp pe_st a).
Proof. unfold pe_consistent. intros st pe_st H a.
induction a; simpl;
try reflexivity;
try (destruct (pe_aexp pe_st a1);
destruct (pe_aexp pe_st a2);
rewrite IHa1; rewrite IHa2; reflexivity).
(* Compared to fold_constants_aexp_sound,
the only interesting case is AId *)
- (* AId *)
remember (pe_lookup pe_st x) as l. destruct l.
+ (* Some *) rewrite H with (n:=n) by apply Heql. reflexivity.
+ (* None *) reflexivity.
Qed.
(** However, we will soon want our partial evaluator to remove
assignments. For example, it will simplify
X := 3; Y := X - Y; X := 4
to just
Y := 3 - Y; X := 4
by delaying the assignment to [X] until the end. To accomplish
this simplification, we need the result of partial evaluating
pe_aexp [(X,3)] (X - Y)
to be equal to [3 - Y] and _not_ the original
expression [X - Y]. After all, it would be
incorrect, not just inefficient, to transform
X := 3; Y := X - Y; X := 4
to
Y := X - Y; X := 4
even though the output expressions [3 - Y] and
[X - Y] both satisfy the correctness criterion
that we just proved. Indeed, if we were to just define [pe_aexp
pe_st a = a] then the theorem [pe_aexp_correct_weak] would already
trivially hold.
Instead, we want to prove that the [pe_aexp] is correct in a
stronger sense: evaluating the expression produced by partial
evaluation ([aeval st (pe_aexp pe_st a)]) must not depend on those
parts of the full state [st] that are already specified in the
partial state [pe_st]. To be more precise, let us define a
function [pe_override], which updates [st] with the contents of
[pe_st]. In other words, [pe_override] carries out the
assignments listed in [pe_st] on top of [st]. *)
Fixpoint pe_update (st:state) (pe_st:pe_state) : state :=
match pe_st with
| [] => st
| (V,n)::pe_st => t_update (pe_update st pe_st) V n
end.
Example test_pe_update:
pe_update (Y !-> 1) [(X,3);(Z,2)]
= (X !-> 3 ; Z !-> 2 ; Y !-> 1).
Proof. reflexivity. Qed.
(** Although [pe_update] operates on a concrete [list] representing
a [pe_state], its behavior is defined entirely by the [pe_lookup]
interpretation of the [pe_state]. *)
Theorem pe_update_correct: forall st pe_st V0,
pe_update st pe_st V0 =
match pe_lookup pe_st V0 with
| Some n => n
| None => st V0
end.
Proof. intros. induction pe_st as [| [V n] pe_st]. reflexivity.
simpl in *. unfold t_update.
compare V0 V; auto. rewrite <- eqb_string_refl; auto. rewrite false_eqb_string; auto. Qed.
(** We can relate [pe_consistent] to [pe_update] in two ways.
First, overriding a state with a partial state always gives a
state that is consistent with the partial state. Second, if a
state is already consistent with a partial state, then overriding
the state with the partial state gives the same state. *)
Theorem pe_update_consistent: forall st pe_st,
pe_consistent (pe_update st pe_st) pe_st.
Proof. intros st pe_st V n H. rewrite pe_update_correct.
destruct (pe_lookup pe_st V); inversion H. reflexivity. Qed.
Theorem pe_consistent_update: forall st pe_st,
pe_consistent st pe_st -> forall V, st V = pe_update st pe_st V.
Proof. intros st pe_st H V. rewrite pe_update_correct.
remember (pe_lookup pe_st V) as l. destruct l; auto. Qed.
(** Now we can state and prove that [pe_aexp] is correct in the
stronger sense that will help us define the rest of the partial
evaluator.
Intuitively, running a program using partial evaluation is a
two-stage process. In the first, _static_ stage, we partially
evaluate the given program with respect to some partial state to
get a _residual_ program. In the second, _dynamic_ stage, we
evaluate the residual program with respect to the rest of the
state. This dynamic state provides values for those variables
that are unknown in the static (partial) state. Thus, the
residual program should be equivalent to _prepending_ the
assignments listed in the partial state to the original program. *)
Theorem pe_aexp_correct: forall (pe_st:pe_state) (a:aexp) (st:state),
aeval (pe_update st pe_st) a = aeval st (pe_aexp pe_st a).
Proof.
intros pe_st a st.
induction a; simpl;
try reflexivity;
try (destruct (pe_aexp pe_st a1);
destruct (pe_aexp pe_st a2);
rewrite IHa1; rewrite IHa2; reflexivity).
(* Compared to fold_constants_aexp_sound, the only
interesting case is AId. *)
rewrite pe_update_correct. destruct (pe_lookup pe_st x); reflexivity.
Qed.
(* ================================================================= *)
(** ** Boolean Expressions *)
(** The partial evaluation of boolean expressions is similar. In
fact, it is entirely analogous to the constant folding of boolean
expressions, because our language has no boolean variables. *)
Fixpoint pe_bexp (pe_st : pe_state) (b : bexp) : bexp :=
match b with
| <{ true }> => <{ true }>
| <{ false }> => <{ false }>
| <{ a1 = a2 }> =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => if n1 =? n2 then <{ true }> else <{ false }>
| (a1', a2') => <{ a1' = a2' }>
end
| <{ a1 <= a2 }> =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => if n1 <=? n2 then <{ true }> else <{ false }>
| (a1', a2') => <{ a1' <= a2' }>
end
| <{ ~ b1 }> =>
match (pe_bexp pe_st b1) with
| <{ true }> => <{ false }>
| <{ false }> => <{ true }>
| b1' => <{ ~ b1' }>
end
| <{ b1 && b2 }> =>
match (pe_bexp pe_st b1, pe_bexp pe_st b2) with
| (<{ true }>, <{ true }>) => <{ true }>
| (<{ true }>, <{ false }>) => <{ false }>
| (<{ false }>, <{ true }>) => <{ false }>
| (<{ false }>, <{ false }>) => <{ false }>
| (b1', b2') => <{ b1' && b2' }>
end
end.
Example test_pe_bexp1:
pe_bexp [(X,3)] <{~(X <= 3)}>
= <{ false }>.
Proof. reflexivity. Qed.
Example test_pe_bexp2: forall b:bexp,
b = <{ ~(X <= (X + 1)) }> ->
pe_bexp [] b = b.
Proof. intros b H. rewrite -> H. reflexivity. Qed.
(** The correctness of [pe_bexp] is analogous to the correctness of
[pe_aexp] above. *)
Theorem pe_bexp_correct: forall (pe_st:pe_state) (b:bexp) (st:state),
beval (pe_update st pe_st) b = beval st (pe_bexp pe_st b).
Proof.
intros pe_st b st.
induction b; simpl;
try reflexivity;
try (remember (pe_aexp pe_st a1) as a1';
remember (pe_aexp pe_st a2) as a2';
assert (H1: aeval (pe_update st pe_st) a1 = aeval st a1');
assert (H2: aeval (pe_update st pe_st) a2 = aeval st a2');
try (subst; apply pe_aexp_correct);
destruct a1'; destruct a2'; rewrite H1; rewrite H2;
simpl; try destruct (n =? n0);
try destruct (n <=? n0); reflexivity);
try (destruct (pe_bexp pe_st b); rewrite IHb; reflexivity);
try (destruct (pe_bexp pe_st b1);
destruct (pe_bexp pe_st b2);
rewrite IHb1; rewrite IHb2; reflexivity).
Qed.
(* ################################################################# *)
(** * Partial Evaluation of Commands, Without Loops *)
(** What about the partial evaluation of commands? The analogy
between partial evaluation and full evaluation continues: Just as
full evaluation of a command turns an initial state into a final
state, partial evaluation of a command turns an initial partial
state into a final partial state. The difference is that, because
the state is partial, some parts of the command may not be
executable at the static stage. Therefore, just as [pe_aexp]
returns a residual [aexp] and [pe_bexp] returns a residual [bexp]
above, partially evaluating a command yields a residual command.
Another way in which our partial evaluator is similar to a full
evaluator is that it does not terminate on all commands. It is
not hard to build a partial evaluator that terminates on all
commands; what is hard is building a partial evaluator that
terminates on all commands yet automatically performs desired
optimizations such as unrolling loops. Often a partial evaluator
can be coaxed into terminating more often and performing more
optimizations by writing the source program differently so that
the separation between static and dynamic information becomes more
apparent. Such coaxing is the art of _binding-time improvement_.
The binding time of a variable tells when its value is known --
either "static", or "dynamic."
Anyway, for now we will just live with the fact that our partial
evaluator is not a total function from the source command and the
initial partial state to the residual command and the final
partial state. To model this non-termination, just as with the
full evaluation of commands, we use an inductively defined
relation. We write
c1 / st ==> c1' / st'
to mean that partially evaluating the source command [c1] in the
initial partial state [st] yields the residual command [c1'] and
the final partial state [st']. For example, we want something like
[] / (X := 3 ; Y := Z * (X + X)) ==> (Y := Z * 6) / [(X,3)]
to hold. The assignment to [X] appears in the final partial state,
not the residual command.
(Writing something like [st =[ c1 ]=> c1' / st'] would be closer to
the notation used in [Imp]; perhaps this should be changed!)
*)
(* ================================================================= *)
(** ** Assignment *)
(** Let's start by considering how to partially evaluate an
assignment. The two assignments in the source program above needs
to be treated differently. The first assignment [X := 3],
is _static_: its right-hand-side is a constant (more generally,
simplifies to a constant), so we should update our partial state
at [X] to [3] and produce no residual code. (Actually, we produce
a residual [skip].) The second assignment [Y := Z * (X + X)]
is _dynamic_: its right-hand-side does
not simplify to a constant, so we should leave it in the residual
code and remove [Y], if present, from our partial state. To
implement these two cases, we define the functions [pe_add] and
[pe_remove]. Like [pe_update] above, these functions operate on
a concrete [list] representing a [pe_state], but the theorems
[pe_add_correct] and [pe_remove_correct] specify their behavior by
the [pe_lookup] interpretation of the [pe_state]. *)
Fixpoint pe_remove (pe_st:pe_state) (V:string) : pe_state :=
match pe_st with
| [] => []
| (V',n')::pe_st => if eqb_string V V' then pe_remove pe_st V
else (V',n') :: pe_remove pe_st V
end.
Theorem pe_remove_correct: forall pe_st V V0,
pe_lookup (pe_remove pe_st V) V0
= if eqb_string V V0 then None else pe_lookup pe_st V0.
Proof. intros pe_st V V0. induction pe_st as [| [V' n'] pe_st].
- (* [] *) destruct (eqb_string V V0); reflexivity.
- (* :: *) simpl. compare V V'.
+ (* equal *) rewrite IHpe_st.
destruct (eqb_stringP V V0). reflexivity.
rewrite false_eqb_string; auto.
+ (* not equal *) simpl. compare V0 V'.
* (* equal *) rewrite false_eqb_string; auto.
* (* not equal *) rewrite IHpe_st. reflexivity.
Qed.
Definition pe_add (pe_st:pe_state) (V:string) (n:nat) : pe_state :=
(V,n) :: pe_remove pe_st V.
Theorem pe_add_correct: forall pe_st V n V0,
pe_lookup (pe_add pe_st V n) V0
= if eqb_string V V0 then Some n else pe_lookup pe_st V0.
Proof. intros pe_st V n V0. unfold pe_add. simpl.
compare V V0.
- (* equal *) rewrite <- eqb_string_refl; auto.
- (* not equal *) rewrite pe_remove_correct.
repeat rewrite false_eqb_string; auto.
Qed.
(** We will use the two theorems below to show that our partial
evaluator correctly deals with dynamic assignments and static
assignments, respectively. *)
Theorem pe_update_update_remove: forall st pe_st V n,
t_update (pe_update st pe_st) V n =
pe_update (t_update st V n) (pe_remove pe_st V).
Proof. intros st pe_st V n. apply functional_extensionality.
intros V0. unfold t_update. rewrite !pe_update_correct.
rewrite pe_remove_correct. destruct (eqb_string V V0); reflexivity.
Qed.
Theorem pe_update_update_add: forall st pe_st V n,
t_update (pe_update st pe_st) V n =
pe_update st (pe_add pe_st V n).
Proof. intros st pe_st V n. apply functional_extensionality. intros V0.
unfold t_update. rewrite !pe_update_correct. rewrite pe_add_correct.
destruct (eqb_string V V0); reflexivity. Qed.
(* ================================================================= *)
(** ** Conditional *)
(** Trickier than assignments to partially evaluate is the
conditional, [if b1 then c1 else c2 end]. If [b1] simplifies to
[BTrue] or [BFalse] then it's easy: we know which branch will be
taken, so just take that branch. If [b1] does not simplify to a
constant, then we need to take both branches, and the final
partial state may differ between the two branches!
The following program illustrates the difficulty:
X := 3;
if Y <= 4 then
Y := 4;
if X <= Y then Y := 999 else skip end
else skip end
Suppose the initial partial state is empty. We don't know
statically how [Y] compares to [4], so we must partially evaluate
both branches of the (outer) conditional. On the [then] branch,
we know that [Y] is set to [4] and can even use that knowledge to
simplify the code somewhat. On the [else] branch, we still don't
know the exact value of [Y] at the end. What should the final
partial state and residual program be?
One way to handle such a dynamic conditional is to take the
intersection of the final partial states of the two branches. In
this example, we take the intersection of [(Y,4),(X,3)] and
[(X,3)], so the overall final partial state is [(X,3)]. To
compensate for forgetting that [Y] is [4], we need to add an
assignment [Y := 4] to the end of the [then] branch. So,
the residual program will be something like
skip;
if Y <= 4 then
skip;
skip;
Y := 4
else skip end
Programming this case in Coq calls for several auxiliary
functions: we need to compute the intersection of two [pe_state]s
and turn their difference into sequences of assignments.
First, we show how to compute whether two [pe_state]s to disagree
at a given variable. In the theorem [pe_disagree_domain], we
prove that two [pe_state]s can only disagree at variables that
appear in at least one of them. *)
Definition pe_disagree_at (pe_st1 pe_st2 : pe_state) (V:string) : bool :=
match pe_lookup pe_st1 V, pe_lookup pe_st2 V with
| Some x, Some y => negb (x =? y)
| None, None => false
| _, _ => true
end.
Theorem pe_disagree_domain: forall (pe_st1 pe_st2 : pe_state) (V:string),
true = pe_disagree_at pe_st1 pe_st2 V ->
In V (map (@fst _ _) pe_st1 ++ map (@fst _ _) pe_st2).
Proof. unfold pe_disagree_at. intros pe_st1 pe_st2 V H.
apply in_app_iff.
remember (pe_lookup pe_st1 V) as lookup1.
destruct lookup1 as [n1|]. left. apply pe_domain with n1. auto.
remember (pe_lookup pe_st2 V) as lookup2.
destruct lookup2 as [n2|]. right. apply pe_domain with n2. auto.
inversion H. Qed.
(** We define the [pe_compare] function to list the variables where
two given [pe_state]s disagree. This list is exact, according to
the theorem [pe_compare_correct]: a variable appears on the list
if and only if the two given [pe_state]s disagree at that
variable. Furthermore, we use the [pe_unique] function to
eliminate duplicates from the list. *)
Fixpoint pe_unique (l : list string) : list string :=
match l with
| [] => []
| x::l =>
x :: filter (fun y => if eqb_string x y then false else true) (pe_unique l)
end.
Theorem pe_unique_correct: forall l x,
In x l <-> In x (pe_unique l).
Proof. intros l x. induction l as [| h t]. reflexivity.
simpl in *. split.
- (* -> *)
intros. inversion H; clear H.
left. assumption.
destruct (eqb_stringP h x).
left. assumption.
right. apply filter_In. split.
apply IHt. assumption.
rewrite false_eqb_string; auto.
- (* <- *)
intros. inversion H; clear H.
left. assumption.
apply filter_In in H0. inversion H0. right. apply IHt. assumption.
Qed.
Definition pe_compare (pe_st1 pe_st2 : pe_state) : list string :=
pe_unique (filter (pe_disagree_at pe_st1 pe_st2)
(map (@fst _ _) pe_st1 ++ map (@fst _ _) pe_st2)).
Theorem pe_compare_correct: forall pe_st1 pe_st2 V,
pe_lookup pe_st1 V = pe_lookup pe_st2 V <->
~ In V (pe_compare pe_st1 pe_st2).
Proof. intros pe_st1 pe_st2 V.
unfold pe_compare. rewrite <- pe_unique_correct. rewrite filter_In.
split; intros Heq.
- (* -> *)
intro. destruct H. unfold pe_disagree_at in H0. rewrite Heq in H0.
destruct (pe_lookup pe_st2 V).
rewrite <- beq_nat_refl in H0. inversion H0.
inversion H0.
- (* <- *)
assert (Hagree: pe_disagree_at pe_st1 pe_st2 V = false).
{ (* Proof of assertion *)
remember (pe_disagree_at pe_st1 pe_st2 V) as disagree.
destruct disagree; [| reflexivity].
apply pe_disagree_domain in Heqdisagree.
exfalso. apply Heq. split. assumption. reflexivity. }
unfold pe_disagree_at in Hagree.
destruct (pe_lookup pe_st1 V) as [n1|];
destruct (pe_lookup pe_st2 V) as [n2|];
try reflexivity; try solve_by_invert.
rewrite negb_false_iff in Hagree.
apply eqb_eq in Hagree. subst. reflexivity. Qed.
(** The intersection of two partial states is the result of removing
from one of them all the variables where the two disagree. We
define the function [pe_removes], in terms of [pe_remove] above,
to perform such a removal of a whole list of variables at once.
The theorem [pe_compare_removes] testifies that the [pe_lookup]
interpretation of the result of this intersection operation is the
same no matter which of the two partial states we remove the
variables from. Because [pe_update] only depends on the
[pe_lookup] interpretation of partial states, [pe_update] also
does not care which of the two partial states we remove the
variables from; that theorem [pe_compare_update] is used in the
correctness proof shortly. *)
Fixpoint pe_removes (pe_st:pe_state) (ids : list string) : pe_state :=
match ids with
| [] => pe_st
| V::ids => pe_remove (pe_removes pe_st ids) V
end.
Theorem pe_removes_correct: forall pe_st ids V,
pe_lookup (pe_removes pe_st ids) V =
if inb eqb_string V ids then None else pe_lookup pe_st V.
Proof. intros pe_st ids V. induction ids as [| V' ids]. reflexivity.
simpl. rewrite pe_remove_correct. rewrite IHids.
compare V' V.
- rewrite <- eqb_string_refl. reflexivity.
- rewrite false_eqb_string; try congruence. reflexivity.
Qed.
Theorem pe_compare_removes: forall pe_st1 pe_st2 V,
pe_lookup (pe_removes pe_st1 (pe_compare pe_st1 pe_st2)) V =
pe_lookup (pe_removes pe_st2 (pe_compare pe_st1 pe_st2)) V.
Proof.
intros pe_st1 pe_st2 V. rewrite !pe_removes_correct.
destruct (inbP _ _ eqb_stringP V (pe_compare pe_st1 pe_st2)).
- reflexivity.
- apply pe_compare_correct. auto. Qed.
Theorem pe_compare_update: forall pe_st1 pe_st2 st,
pe_update st (pe_removes pe_st1 (pe_compare pe_st1 pe_st2)) =
pe_update st (pe_removes pe_st2 (pe_compare pe_st1 pe_st2)).
Proof. intros. apply functional_extensionality. intros V.
rewrite !pe_update_correct. rewrite pe_compare_removes. reflexivity.
Qed.
(** Finally, we define an [assign] function to turn the difference
between two partial states into a sequence of assignment commands.
More precisely, [assign pe_st ids] generates an assignment command
for each variable listed in [ids]. *)
Fixpoint assign (pe_st : pe_state) (ids : list string) : com :=
match ids with
| [] => <{ skip }>
| V::ids => match pe_lookup pe_st V with
| Some n => <{ assign pe_st ids; V := n }>
| None => assign pe_st ids
end
end.
(** The command generated by [assign] always terminates, because it is
just a sequence of assignments. The (total) function [assigned]
below computes the effect of the command on the (dynamic state).
The theorem [assign_removes] then confirms that the generated
assignments perfectly compensate for removing the variables from
the partial state. *)
Definition assigned (pe_st:pe_state) (ids : list string) (st:state) : state :=
fun V => if inb eqb_string V ids then
match pe_lookup pe_st V with
| Some n => n
| None => st V
end
else st V.
Theorem assign_removes: forall pe_st ids st,
pe_update st pe_st =
pe_update (assigned pe_st ids st) (pe_removes pe_st ids).
Proof. intros pe_st ids st. apply functional_extensionality. intros V.
rewrite !pe_update_correct. rewrite pe_removes_correct. unfold assigned.
destruct (inbP _ _ eqb_stringP V ids); destruct (pe_lookup pe_st V); reflexivity.
Qed.
Lemma ceval_extensionality: forall c st st1 st2,
st =[ c ]=> st1 -> (forall V, st1 V = st2 V) -> st =[ c ]=> st2.
Proof. intros c st st1 st2 H Heq.
apply functional_extensionality in Heq. rewrite <- Heq. apply H. Qed.
Theorem eval_assign: forall pe_st ids st,
st =[ assign pe_st ids ]=> assigned pe_st ids st.
Proof. intros pe_st ids st. induction ids as [| V ids]; simpl.
- (* [] *) eapply ceval_extensionality. apply E_Skip. reflexivity.
- (* V::ids *)
remember (pe_lookup pe_st V) as lookup. destruct lookup.
+ (* Some *) eapply E_Seq. apply IHids. unfold assigned. simpl.
eapply ceval_extensionality. apply E_Ass. simpl. reflexivity.
intros V0. unfold t_update. compare V V0.
* (* equal *) rewrite <- Heqlookup. rewrite <- eqb_string_refl. reflexivity.
* (* not equal *) rewrite false_eqb_string; simpl; congruence.
+ (* None *) eapply ceval_extensionality. apply IHids.
unfold assigned. intros V0. simpl. compare V V0.
* (* equal *) rewrite <- Heqlookup.
rewrite <- eqb_string_refl.
destruct (inbP _ _ eqb_stringP V ids); reflexivity.
* (* not equal *) rewrite false_eqb_string; simpl; congruence.
Qed.
(* ================================================================= *)
(** ** The Partial Evaluation Relation *)
(** At long last, we can define a partial evaluator for commands
without loops, as an inductive relation! The inequality
conditions in [PE_AssDynamic] and [PE_If] are just to keep the
partial evaluator deterministic; they are not required for
correctness. *)
Reserved Notation "c1 '/' st '==>' c1' '/' st'"
(at level 40, st at level 39, c1' at level 39).
Inductive pe_com : com -> pe_state -> com -> pe_state -> Prop :=
| PE_Skip : forall pe_st,
<{skip}> / pe_st ==> <{skip}> / pe_st
| PE_AssStatic : forall pe_st a1 (n1 : nat) l,
pe_aexp pe_st a1 = <{ n1 }> ->
<{l := a1}> / pe_st ==> <{skip}> / pe_add pe_st l n1
| PE_AssDynamic : forall pe_st a1 a1' l,
pe_aexp pe_st a1 = a1' ->
(forall n : nat , a1' <> <{ n }>) ->
<{l := a1}> / pe_st ==> <{l := a1'}> / pe_remove pe_st l
| PE_Seq : forall pe_st pe_st' pe_st'' c1 c2 c1' c2',
c1 / pe_st ==> c1' / pe_st' ->
c2 / pe_st' ==> c2' / pe_st'' ->
<{c1 ; c2}> / pe_st ==> <{c1' ; c2'}> / pe_st''
| PE_IfTrue : forall pe_st pe_st' b1 c1 c2 c1',
pe_bexp pe_st b1 = <{ true }> ->
c1 / pe_st ==> c1' / pe_st' ->
<{if b1 then c1 else c2 end}> / pe_st ==> c1' / pe_st'
| PE_IfFalse : forall pe_st pe_st' b1 c1 c2 c2',
pe_bexp pe_st b1 = BFalse ->
c2 / pe_st ==> c2' / pe_st' ->
<{if b1 then c1 else c2 end}> / pe_st ==> c2' / pe_st'
| PE_If : forall pe_st pe_st1 pe_st2 b1 c1 c2 c1' c2',
pe_bexp pe_st b1 <> <{ true }> ->
pe_bexp pe_st b1 <> <{ false }> ->
c1 / pe_st ==> c1' / pe_st1 ->
c2 / pe_st ==> c2' / pe_st2 ->
<{if b1 then c1 else c2 end}> / pe_st
==> <{if pe_bexp pe_st b1
then c1' ; assign pe_st1 (pe_compare pe_st1 pe_st2)
else c2' ; assign pe_st2 (pe_compare pe_st1 pe_st2) end}>
/ pe_removes pe_st1 (pe_compare pe_st1 pe_st2)
where "c1 '/' st '==>' c1' '/' st'" := (pe_com c1 st c1' st').
Hint Constructors pe_com : core.
Hint Constructors ceval : core.
(* ================================================================= *)
(** ** Examples *)
(** Below are some examples of using the partial evaluator. To make
the [pe_com] relation actually usable for automatic partial
evaluation, we would need to define more automation tactics in
Coq. That is not hard to do, but it is not needed here. *)
Example pe_example1:
<{X := 3 ; Y := Z * (X + X)}>
/ [] ==> <{skip; Y := Z * 6}> / [(X,3)].
Proof. eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_AssDynamic. reflexivity. intros n H. inversion H. Qed.
Example pe_example2:
<{X := 3 ; if X <= 4 then X := 4 else skip end}>
/ [] ==> <{skip; skip}> / [(X,4)].
Proof. eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_IfTrue. reflexivity.
eapply PE_AssStatic. reflexivity. Qed.
Example pe_example3:
<{X := 3;
if Y <= 4 then
Y := 4;
if X = Y then Y := 999 else skip end
else skip end}> / []
==> <{skip;
if Y <= 4 then
(skip; skip); (skip; Y := 4)
else skip; skip end}>
/ [(X,3)].
Proof. erewrite f_equal2 with (f := fun c st => _ / _ ==> c / st).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_If; intuition eauto; try solve_by_invert.
econstructor. eapply PE_AssStatic. reflexivity.
eapply PE_IfFalse. reflexivity. econstructor.
reflexivity. reflexivity. Qed.
(* ================================================================= *)
(** ** Correctness of Partial Evaluation *)
(** Finally let's prove that this partial evaluator is correct! *)
Reserved Notation "c' '/' pe_st' '/' st '==>' st''"
(at level 40, pe_st' at level 39, st at level 39).
Inductive pe_ceval
(c':com) (pe_st':pe_state) (st:state) (st'':state) : Prop :=
| pe_ceval_intro : forall st',
st =[ c' ]=> st' ->
pe_update st' pe_st' = st'' ->
c' / pe_st' / st ==> st''
where "c' '/' pe_st' '/' st '==>' st''" := (pe_ceval c' pe_st' st st'').
Hint Constructors pe_ceval : core.
(* NOTATION : IY -- The "If" case line spacing looks a little off---what are the line
break insert rules for Imp? *)
Theorem pe_com_complete:
forall c pe_st pe_st' c', c / pe_st ==> c' / pe_st' ->
forall st st'',
(pe_update st pe_st =[ c ]=> st'') ->
(c' / pe_st' / st ==> st'').
Proof. intros c pe_st pe_st' c' Hpe.
induction Hpe; intros st st'' Heval;
try (inversion Heval; subst;
try (rewrite -> pe_bexp_correct, -> H in *; solve_by_invert);
[]);
eauto.
- (* PE_AssStatic *) econstructor. econstructor.
rewrite -> pe_aexp_correct. rewrite <- pe_update_update_add.
rewrite -> H. reflexivity.
- (* PE_AssDynamic *) econstructor. econstructor. reflexivity.
rewrite -> pe_aexp_correct. rewrite <- pe_update_update_remove.
reflexivity.
- (* PE_Seq *)
edestruct IHHpe1. eassumption. subst.
edestruct IHHpe2. eassumption.
eauto.
- (* PE_If *) inversion Heval; subst.
+ (* E'IfTrue *) edestruct IHHpe1. eassumption.
econstructor. apply E_IfTrue. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite <- assign_removes. eassumption.
+ (* E_IfFalse *) edestruct IHHpe2. eassumption.
econstructor. apply E_IfFalse. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite -> pe_compare_update.
rewrite <- assign_removes. eassumption.
Qed.
(* NOTATION : IY -- Note : In the PE_AssDynamic/If cases, "=[ ]=>" breaks in a weird
way. *)
Theorem pe_com_sound:
forall c pe_st pe_st' c', c / pe_st ==> c' / pe_st' ->
forall st st'',
(c' / pe_st' / st ==> st'') ->
(pe_update st pe_st =[ c ]=> st'').
Proof. intros c pe_st pe_st' c' Hpe.
induction Hpe;
intros st st'' [st' Heval Heq];
try (inversion Heval; []; subst); auto.
- (* PE_AssStatic *) rewrite <- pe_update_update_add. apply E_Ass.
rewrite -> pe_aexp_correct. rewrite -> H. reflexivity.
- (* PE_AssDynamic *) rewrite <- pe_update_update_remove. apply E_Ass.
rewrite <- pe_aexp_correct. reflexivity.
- (* PE_Seq *) eapply E_Seq; eauto.
- (* PE_IfTrue *) apply E_IfTrue.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity. eauto.
- (* PE_IfFalse *) apply E_IfFalse.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity. eauto.
- (* PE_If *)
inversion Heval; subst; inversion H7;
(eapply ceval_deterministic in H8; [| apply eval_assign]); subst.
+ (* E_IfTrue *)
apply E_IfTrue. rewrite -> pe_bexp_correct. assumption.
rewrite <- assign_removes. eauto.
+ (* E_IfFalse *)
rewrite -> pe_compare_update.
apply E_IfFalse. rewrite -> pe_bexp_correct. assumption.
rewrite <- assign_removes. eauto.
Qed.
(** The main theorem. Thanks to David Menendez for this formulation! *)
Corollary pe_com_correct:
forall c pe_st pe_st' c', c / pe_st ==> c' / pe_st' ->
forall st st'',
(pe_update st pe_st =[ c ]=> st'') <->
(c' / pe_st' / st ==> st'').
Proof. intros c pe_st pe_st' c' H st st''. split.
- (* -> *) apply pe_com_complete. apply H.
- (* <- *) apply pe_com_sound. apply H.
Qed.
(* ################################################################# *)
(** * Partial Evaluation of Loops *)
(** It may seem straightforward at first glance to extend the partial
evaluation relation [pe_com] above to loops. Indeed, many loops
are easy to deal with. Considered this repeated-squaring loop,
for example:
while 1 <= X do
Y := Y * Y;
X := X - 1
end
If we know neither [X] nor [Y] statically, then the entire loop is
dynamic and the residual command should be the same. If we know
[X] but not [Y], then the loop can be unrolled all the way and the
residual command should be, for example,
Y := Y * Y;
Y := Y * Y;
Y := Y * Y
if [X] is initially [3] (and finally [0]). In general, a loop is
easy to partially evaluate if the final partial state of the loop
body is equal to the initial state, or if its guard condition is
static.
But there are other loops for which it is hard to express the
residual program we want in Imp. For example, take this program
for checking whether [Y] is even or odd:
X := 0;
while 1 <= Y do
Y := Y - 1 ;
X := 1 - X
end
The value of [X] alternates between [0] and [1] during the loop.
Ideally, we would like to unroll this loop, not all the way but
_two-fold_, into something like
while 1 <= Y do
Y := Y - 1;
if 1 <= Y then
Y := Y - 1
else
X := 1; EXIT
end
end;
X := 0
Unfortunately, there is no [EXIT] command in Imp. Without
extending the range of control structures available in our
language, the best we can do is to repeat loop-guard tests or add
flag variables. Neither option is terribly attractive.
Still, as a digression, below is an attempt at performing partial
evaluation on Imp commands. We add one more command argument
[c''] to the [pe_com] relation, which keeps track of a loop to
roll up. *)
Module Loop.
Reserved Notation "c1 '/' st '==>' c1' '/' st' '/' c''"
(at level 40, st at level 39, c1' at level 39, st' at level 39).
Inductive pe_com : com -> pe_state -> com -> pe_state -> com -> Prop :=
| PE_Skip : forall pe_st,
<{ skip }> / pe_st ==> <{ skip }> / pe_st / <{skip}>
| PE_AssStatic : forall pe_st a1 (n1 : nat) l,
pe_aexp pe_st a1 = <{ n1 }> ->
<{ l := a1 }> / pe_st ==> <{ skip }> / pe_add pe_st l n1 / <{skip}>
| PE_AssDynamic : forall pe_st a1 a1' l,
pe_aexp pe_st a1 = a1' ->
(forall n : nat, a1' <> <{ n }> ) ->
<{l := a1}> / pe_st ==> <{l := a1'}> / pe_remove pe_st l / <{skip}>
| PE_Seq : forall pe_st pe_st' pe_st'' c1 c2 c1' c2' c'',
c1 / pe_st ==> c1' / pe_st' / <{skip}> ->
c2 / pe_st' ==> c2' / pe_st'' / c'' ->
<{c1 ; c2}> / pe_st ==> <{c1' ; c2'}> / pe_st'' / c''
| PE_IfTrue : forall pe_st pe_st' b1 c1 c2 c1' c'',
pe_bexp pe_st b1 = <{ true }> ->
c1 / pe_st ==> c1' / pe_st' / c'' ->
<{if b1 then c1 else c2 end}> / pe_st ==> c1' / pe_st' / c''
| PE_IfFalse : forall pe_st pe_st' b1 c1 c2 c2' c'',
pe_bexp pe_st b1 = <{ false }> ->
c2 / pe_st ==> c2' / pe_st' / c'' ->
<{if b1 then c1 else c2 end}> / pe_st ==> c2' / pe_st' / c''
| PE_If : forall pe_st pe_st1 pe_st2 b1 c1 c2 c1' c2' c'',
pe_bexp pe_st b1 <> <{ true }> ->
pe_bexp pe_st b1 <> <{ false }> ->
c1 / pe_st ==> c1' / pe_st1 / c'' ->
c2 / pe_st ==> c2' / pe_st2 / c'' ->
<{if b1 then c1 else c2 end}> / pe_st
==> <{if pe_bexp pe_st b1
then c1' ; assign pe_st1 (pe_compare pe_st1 pe_st2)
else c2' ; assign pe_st2 (pe_compare pe_st1 pe_st2) end}>
/ pe_removes pe_st1 (pe_compare pe_st1 pe_st2)
/ c''
| PE_WhileFalse : forall pe_st b1 c1,
pe_bexp pe_st b1 = BFalse ->
<{while b1 do c1 end}> / pe_st ==> <{skip}> / pe_st / <{skip}>
| PE_WhileTrue : forall pe_st pe_st' pe_st'' b1 c1 c1' c2' c2'',
pe_bexp pe_st b1 = <{ true }> ->
c1 / pe_st ==> c1' / pe_st' / <{skip}> ->
<{while b1 do c1 end}> / pe_st' ==> c2' / pe_st'' / c2'' ->
pe_compare pe_st pe_st'' <> [] ->
<{while b1 do c1 end}> / pe_st ==> <{c1';c2'}> / pe_st'' / c2''
| PE_While : forall pe_st pe_st' pe_st'' b1 c1 c1' c2' c2'',
pe_bexp pe_st b1 <> <{ false }> ->
pe_bexp pe_st b1 <> <{ true }> ->
c1 / pe_st ==> c1' / pe_st' / <{skip}> ->
<{while b1 do c1 end}> / pe_st' ==> c2' / pe_st'' / c2'' ->
pe_compare pe_st pe_st'' <> [] ->
(c2'' = <{skip}> \/ c2'' = <{while b1 do c1 end}>) ->
<{while b1 do c1 end}> / pe_st
==> <{if pe_bexp pe_st b1
then c1'; c2'; assign pe_st'' (pe_compare pe_st pe_st'')
else assign pe_st (pe_compare pe_st pe_st'') end}>
/ pe_removes pe_st (pe_compare pe_st pe_st'')
/ c2''
| PE_WhileFixedEnd : forall pe_st b1 c1,
pe_bexp pe_st b1 <> <{ false }> ->
<{while b1 do c1 end}> / pe_st ==> <{skip}> / pe_st / <{while b1 do c1 end}>
| PE_WhileFixedLoop : forall pe_st pe_st' pe_st'' b1 c1 c1' c2',
pe_bexp pe_st b1 = <{ true }> ->
c1 / pe_st ==> c1' / pe_st' / <{skip}> ->
<{while b1 do c1 end}> / pe_st'
==> c2' / pe_st'' / <{while b1 do c1 end}>->
pe_compare pe_st pe_st'' = [] ->
<{while b1 do c1 end}> / pe_st
==> <{while true do skip end}> / pe_st / <{skip}>
(* Because we have an infinite loop, we should actually
start to throw away the rest of the program:
(while b1 do c1 end) / pe_st
==> skip / pe_st / (while BTrue do skip end) *)
| PE_WhileFixed : forall pe_st pe_st' pe_st'' b1 c1 c1' c2',
pe_bexp pe_st b1 <> <{ false }> ->
pe_bexp pe_st b1 <> <{ true }> ->
c1 / pe_st ==> c1' / pe_st' / <{skip}> ->
<{while b1 do c1 end}> / pe_st'
==> c2' / pe_st'' / <{while b1 do c1 end}> ->
pe_compare pe_st pe_st'' = [] ->
<{while b1 do c1 end}> / pe_st
==> <{while pe_bexp pe_st b1 do c1'; c2' end}> / pe_st / <{skip}>
where "c1 '/' st '==>' c1' '/' st' '/' c''" := (pe_com c1 st c1' st' c'').
Hint Constructors pe_com : core.
(* ================================================================= *)
(** ** Examples *)
Ltac step i :=
(eapply i; intuition eauto; try solve_by_invert);
repeat (try eapply PE_Seq;
try (eapply PE_AssStatic; simpl; reflexivity);
try (eapply PE_AssDynamic;
[ simpl; reflexivity
| intuition eauto; solve_by_invert])).
Definition square_loop: com :=
<{while 1 <= X do
Y := Y * Y;
X := X - 1
end}>.
Example pe_loop_example1:
square_loop / []
==> <{while 1 <= X do
(Y := Y * Y;
X := X - 1); skip
end}> / [] / <{skip}>.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ ==> c / st / <{skip}>).
step PE_WhileFixed. step PE_WhileFixedEnd. reflexivity.
reflexivity. reflexivity. Qed.
Example pe_loop_example2:
<{X := 3; square_loop}> / []
==> <{skip;
(Y := Y * Y; skip);
(Y := Y * Y; skip);
(Y := Y * Y; skip);
skip}> / [(X,0)] / <{skip}>.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ ==> c / st / <{skip}>).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_WhileTrue.
step PE_WhileTrue.
step PE_WhileTrue.
step PE_WhileFalse.
inversion H. inversion H. inversion H.
reflexivity. reflexivity. Qed.
Example pe_loop_example3:
<{Z := 3; subtract_slowly}> / []
==> <{skip;
if ~(X = 0) then
(skip; X := X - 1);
if ~(X = 0) then
(skip; X := X - 1);
if ~(X = 0) then
(skip; X := X - 1);
while ~(X = 0) do
(skip; X := X - 1); skip
end;
skip; Z := 0
else skip; Z := 1 end; skip
else skip; Z := 2 end; skip
else skip; Z := 3 end}> / [] / <{skip}>.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ ==> c / st / <{skip}>).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_While.
step PE_While.
step PE_While.
step PE_WhileFixed.
step PE_WhileFixedEnd.
reflexivity. inversion H. inversion H. inversion H.
reflexivity. reflexivity. Qed.
Example pe_loop_example4:
<{X := 0;
while X <= 2 do
X := 1 - X
end}> / [] ==> <{skip; while true do skip end}> / [(X,0)] / <{skip}>.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ ==> c / st / <{skip}>).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_WhileFixedLoop.
step PE_WhileTrue.
step PE_WhileFixedEnd.
inversion H. reflexivity. reflexivity. reflexivity. Qed.
(* ================================================================= *)
(** ** Correctness *)
(** Because this partial evaluator can unroll a loop n-fold where n is
a (finite) integer greater than one, in order to show it correct
we need to perform induction not structurally on dynamic
evaluation but on the number of times dynamic evaluation enters a
loop body. *)
Reserved Notation "c1 '/' st '==>' st' '#' n"
(at level 40, st at level 39, st' at level 39).
Inductive ceval_count : com -> state -> state -> nat -> Prop :=
| E'Skip : forall st,
<{skip}> / st ==> st # 0
| E'Ass : forall st a1 n l,
aeval st a1 = n ->
<{l := a1}> / st ==> (t_update st l n) # 0
| E'Seq : forall c1 c2 st st' st'' n1 n2,
c1 / st ==> st' # n1 ->
c2 / st' ==> st'' # n2 ->
<{c1 ; c2}> / st ==> st'' # (n1 + n2)
| E'IfTrue : forall st st' b1 c1 c2 n,
beval st b1 = true ->
c1 / st ==> st' # n ->
<{if b1 then c1 else c2 end}> / st ==> st' # n
| E'IfFalse : forall st st' b1 c1 c2 n,
beval st b1 = false ->
c2 / st ==> st' # n ->
<{if b1 then c1 else c2 end}> / st ==> st' # n
| E'WhileFalse : forall b1 st c1,
beval st b1 = false ->
<{while b1 do c1 end}> / st ==> st # 0
| E'WhileTrue : forall st st' st'' b1 c1 n1 n2,
beval st b1 = true ->
c1 / st ==> st' # n1 ->
<{while b1 do c1 end}> / st' ==> st'' # n2 ->
<{while b1 do c1 end}> / st ==> st'' # S (n1 + n2)
where "c1 '/' st '==>' st' # n" := (ceval_count c1 st st' n).
Hint Constructors ceval_count : core.
Theorem ceval_count_complete: forall c st st',
st =[ c ]=> st' -> exists n, c / st ==> st' # n.
Proof. intros c st st' Heval.
induction Heval;
try inversion IHHeval1;
try inversion IHHeval2;
try inversion IHHeval;
eauto. Qed.
Theorem ceval_count_sound: forall c st st' n,
c / st ==> st' # n -> st =[ c ]=> st'.
Proof. intros c st st' n Heval. induction Heval; eauto. Qed.
Theorem pe_compare_nil_lookup: forall pe_st1 pe_st2,
pe_compare pe_st1 pe_st2 = [] ->
forall V, pe_lookup pe_st1 V = pe_lookup pe_st2 V.
Proof. intros pe_st1 pe_st2 H V.
apply (pe_compare_correct pe_st1 pe_st2 V).
rewrite H. intro. inversion H0. Qed.
Theorem pe_compare_nil_update: forall pe_st1 pe_st2,
pe_compare pe_st1 pe_st2 = [] ->
forall st, pe_update st pe_st1 = pe_update st pe_st2.
Proof. intros pe_st1 pe_st2 H st.
apply functional_extensionality. intros V.
rewrite !pe_update_correct.
apply pe_compare_nil_lookup with (V:=V) in H.
rewrite H. reflexivity. Qed.
Reserved Notation "c' '/' pe_st' '/' c'' '/' st '==>' st'' '#' n"
(at level 40, pe_st' at level 39, c'' at level 39,
st at level 39, st'' at level 39).
Inductive pe_ceval_count (c':com) (pe_st':pe_state) (c'':com)
(st:state) (st'':state) (n:nat) : Prop :=
| pe_ceval_count_intro : forall st' n',
st =[ c' ]=> st' ->
c'' / pe_update st' pe_st' ==> st'' # n' ->
n' <= n ->
c' / pe_st' / c'' / st ==> st'' # n
where "c' '/' pe_st' '/' c'' '/' st '==>' st'' '#' n" :=
(pe_ceval_count c' pe_st' c'' st st'' n).
Hint Constructors pe_ceval_count : core.
Lemma pe_ceval_count_le: forall c' pe_st' c'' st st'' n n',
n' <= n ->
c' / pe_st' / c'' / st ==> st'' # n' ->
c' / pe_st' / c'' / st ==> st'' # n.
Proof. intros c' pe_st' c'' st st'' n n' Hle H. inversion H.
econstructor; try eassumption. lia. Qed.
Theorem pe_com_complete:
forall c pe_st pe_st' c' c'', c / pe_st ==> c' / pe_st' / c'' ->
forall st st'' n,
(c / pe_update st pe_st ==> st'' # n) ->
(c' / pe_st' / c'' / st ==> st'' # n).
Proof. intros c pe_st pe_st' c' c'' Hpe.
induction Hpe; intros st st'' n Heval;
try (inversion Heval; subst;
try (rewrite -> pe_bexp_correct, -> H in *; solve_by_invert);
[]);
eauto.
- (* PE_AssStatic *) econstructor. econstructor.
rewrite -> pe_aexp_correct. rewrite <- pe_update_update_add.
rewrite -> H. apply E'Skip. auto.
- (* PE_AssDynamic *) econstructor. econstructor. reflexivity.
rewrite -> pe_aexp_correct. rewrite <- pe_update_update_remove.
apply E'Skip. auto.
- (* PE_Seq *)
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor; eauto. lia.
- (* PE_If *) inversion Heval; subst.
+ (* E'IfTrue *) edestruct IHHpe1. eassumption.
econstructor. apply E_IfTrue. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite <- assign_removes. eassumption. eassumption.
+ (* E_IfFalse *) edestruct IHHpe2. eassumption.
econstructor. apply E_IfFalse. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite -> pe_compare_update.
rewrite <- assign_removes. eassumption. eassumption.
- (* PE_WhileTrue *)
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor; eauto. lia.
- (* PE_While *) inversion Heval; subst.
+ (* E_WhileFalse *) econstructor. apply E_IfFalse.
rewrite <- pe_bexp_correct. assumption.
apply eval_assign.
rewrite <- assign_removes. inversion H2; subst; auto.
auto.
+ (* E_WhileTrue *)
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor. apply E_IfTrue.
rewrite <- pe_bexp_correct. assumption.
repeat eapply E_Seq; eauto. apply eval_assign.
rewrite -> pe_compare_update, <- assign_removes. eassumption.
lia.
- (* PE_WhileFixedLoop *) exfalso.
generalize dependent (S (n1 + n2)). intros n.
clear - H H0 IHHpe1 IHHpe2. generalize dependent st.
induction n using lt_wf_ind; intros st Heval. inversion Heval; subst.
+ (* E'WhileFalse *) rewrite pe_bexp_correct, H in H7. inversion H7.
+ (* E'WhileTrue *)
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
rewrite <- (pe_compare_nil_update _ _ H0) in H7.
apply H1 in H7; [| lia]. inversion H7.
- (* PE_WhileFixed *) generalize dependent st.
induction n using lt_wf_ind; intros st Heval. inversion Heval; subst.
+ (* E'WhileFalse *) rewrite pe_bexp_correct in H8. eauto.
+ (* E'WhileTrue *) rewrite pe_bexp_correct in H5.
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
rewrite <- (pe_compare_nil_update _ _ H1) in H8.
apply H2 in H8; [| lia]. inversion H8.
econstructor; [ eapply E_WhileTrue; eauto | eassumption | lia].
Qed.
Theorem pe_com_sound:
forall c pe_st pe_st' c' c'', c / pe_st ==> c' / pe_st' / c'' ->
forall st st'' n,
(c' / pe_st' / c'' / st ==> st'' # n) ->
(pe_update st pe_st =[ c ]=> st'').
Proof. intros c pe_st pe_st' c' c'' Hpe.
induction Hpe;
intros st st'' n [st' n' Heval Heval' Hle];
try (inversion Heval; []; subst);
try (inversion Heval'; []; subst); eauto.
- (* PE_AssStatic *) rewrite <- pe_update_update_add. apply E_Ass.
rewrite -> pe_aexp_correct. rewrite -> H. reflexivity.
- (* PE_AssDynamic *) rewrite <- pe_update_update_remove. apply E_Ass.
rewrite <- pe_aexp_correct. reflexivity.
- (* PE_Seq *) eapply E_Seq; eauto.
- (* PE_IfTrue *) apply E_IfTrue.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe. eauto.
- (* PE_IfFalse *) apply E_IfFalse.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe. eauto.
- (* PE_If *) inversion Heval; subst; inversion H7; subst; clear H7.
+ (* E_IfTrue *)
eapply ceval_deterministic in H8; [| apply eval_assign]. subst.
rewrite <- assign_removes in Heval'.
apply E_IfTrue. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe1. eauto.
+ (* E_IfFalse *)
eapply ceval_deterministic in H8; [| apply eval_assign]. subst.
rewrite -> pe_compare_update in Heval'.
rewrite <- assign_removes in Heval'.
apply E_IfFalse. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe2. eauto.
- (* PE_WhileFalse *) apply E_WhileFalse.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
- (* PE_WhileTrue *) eapply E_WhileTrue.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe1. eauto. eapply IHHpe2. eauto.
- (* PE_While *) inversion Heval; subst.
+ (* E_IfTrue *)
inversion H9. subst. clear H9.
inversion H10. subst. clear H10.
eapply ceval_deterministic in H11; [| apply eval_assign]. subst.
rewrite -> pe_compare_update in Heval'.
rewrite <- assign_removes in Heval'.
eapply E_WhileTrue. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe1. eauto.
eapply IHHpe2. eauto.
+ (* E_IfFalse *) apply ceval_count_sound in Heval'.
eapply ceval_deterministic in H9; [| apply eval_assign]. subst.
rewrite <- assign_removes in Heval'.
inversion H2; subst.
* (* c2'' = skip *) inversion Heval'. subst. apply E_WhileFalse.
rewrite -> pe_bexp_correct. assumption.
* (* c2'' = while b1 do c1 end *) assumption.
- (* PE_WhileFixedEnd *) eapply ceval_count_sound. apply Heval'.
- (* PE_WhileFixedLoop *)
apply loop_never_stops in Heval. inversion Heval.
- (* PE_WhileFixed *)
clear - H1 IHHpe1 IHHpe2 Heval.
remember <{while pe_bexp pe_st b1 do c1'; c2' end}> as c'.
induction Heval;
inversion Heqc'; subst; clear Heqc'.
+ (* E_WhileFalse *) apply E_WhileFalse.
rewrite pe_bexp_correct. assumption.
+ (* E_WhileTrue *)
assert (IHHeval2' := IHHeval2 (refl_equal _)).
apply ceval_count_complete in IHHeval2'. inversion IHHeval2'.
clear IHHeval1 IHHeval2 IHHeval2'.
inversion Heval1. subst.
eapply E_WhileTrue. rewrite pe_bexp_correct. assumption. eauto.
eapply IHHpe2. econstructor. eassumption.
rewrite <- (pe_compare_nil_update _ _ H1). eassumption. apply le_n.
Qed.
Corollary pe_com_correct:
forall c pe_st pe_st' c', c / pe_st ==> c' / pe_st' / <{skip}> ->
forall st st'',
(pe_update st pe_st =[ c ]=> st'') <->
(exists st', st =[ c' ]=> st' /\ pe_update st' pe_st' = st'').
Proof. intros c pe_st pe_st' c' H st st''. split.
- (* -> *) intros Heval.
apply ceval_count_complete in Heval. inversion Heval as [n Heval'].
apply pe_com_complete with (st:=st) (st'':=st'') (n:=n) in H.
inversion H as [? ? ? Hskip ?]. inversion Hskip. subst. eauto.
assumption.
- (* <- *) intros [st' [Heval Heq] ]. subst st''.
eapply pe_com_sound in H. apply H.
econstructor. apply Heval. apply E'Skip. apply le_n.
Qed.
End Loop.
(* ################################################################# *)
(** * Partial Evaluation of Flowchart Programs *)
(** Instead of partially evaluating [while] loops directly, the
standard approach to partially evaluating imperative programs is
to convert them into _flowcharts_. In other words, it turns out
that adding labels and jumps to our language makes it much easier
to partially evaluate. The result of partially evaluating a
flowchart is a residual flowchart. If we are lucky, the jumps in
the residual flowchart can be converted back to [while] loops, but
that is not possible in general; we do not pursue it here. *)
(* ================================================================= *)
(** ** Basic blocks *)
(** A flowchart is made of _basic blocks_, which we represent with the
inductive type [block]. A basic block is a sequence of
assignments (the constructor [Assign]), concluding with a
conditional jump (the constructor [If]) or an unconditional jump
(the constructor [Goto]). The destinations of the jumps are
specified by _labels_, which can be of any type. Therefore, we
parameterize the [block] type by the type of labels. *)
Inductive block (Label:Type) : Type :=
| Goto : Label -> block Label
| If : bexp -> Label -> Label -> block Label
| Assign : string -> aexp -> block Label -> block Label.
Arguments Goto {Label} _.
Arguments If {Label} _ _ _.
Arguments Assign {Label} _ _ _.
(** We use the "even or odd" program, expressed above in Imp, as our
running example. Converting this program into a flowchart turns
out to require 4 labels, so we define the following type. *)
Inductive parity_label : Type :=
| entry : parity_label
| loop : parity_label
| body : parity_label
| done : parity_label.
(** The following [block] is the basic block found at the [body] label
of the example program. *)
Definition parity_body : block parity_label :=
Assign Y <{Y - 1}>
(Assign X <{1 - X}>
(Goto loop)).
(** To evaluate a basic block, given an initial state, is to compute
the final state and the label to jump to next. Because basic
blocks do not _contain_ loops or other control structures,
evaluation of basic blocks is a total function -- we don't need to
worry about non-termination. *)
Fixpoint keval {L:Type} (st:state) (k : block L) : state * L :=
match k with
| Goto l => (st, l)
| If b l1 l2 => (st, if beval st b then l1 else l2)
| Assign i a k => keval (t_update st i (aeval st a)) k
end.
Example keval_example:
keval empty_st parity_body
= ((X !-> 1 ; Y !-> 0), loop).
Proof. reflexivity. Qed.
(* ================================================================= *)
(** ** Flowchart programs *)
(** A flowchart program is simply a lookup function that maps labels
to basic blocks. Actually, some labels are _halting states_ and
do not map to any basic block. So, more precisely, a flowchart
[program] whose labels are of type [L] is a function from [L] to
[option (block L)]. *)
Definition program (L:Type) : Type := L -> option (block L).
Definition parity : program parity_label := fun l =>
match l with
| entry => Some (Assign X 0 (Goto loop))
| loop => Some (If <{1 <= Y}> body done)
| body => Some parity_body
| done => None (* halt *)
end.
(** Unlike a basic block, a program may not terminate, so we model the
evaluation of programs by an inductive relation [peval] rather
than a recursive function. *)
Inductive peval {L:Type} (p : program L)
: state -> L -> state -> L -> Prop :=
| E_None: forall st l,
p l = None ->
peval p st l st l
| E_Some: forall st l k st' l' st'' l'',
p l = Some k ->
keval st k = (st', l') ->
peval p st' l' st'' l'' ->
peval p st l st'' l''.
Example parity_eval: peval parity empty_st entry empty_st done.
Proof. erewrite f_equal with (f := fun st => peval _ _ _ st _).
eapply E_Some. reflexivity. reflexivity.
eapply E_Some. reflexivity. reflexivity.
apply E_None. reflexivity.
apply functional_extensionality. intros i. rewrite t_update_same; auto.
Qed.
(* ================================================================= *)
(** ** Partial Evaluation of Basic Blocks and Flowchart Programs *)
(** Partial evaluation changes the label type in a systematic way: if
the label type used to be [L], it becomes [pe_state * L]. So the
same label in the original program may be unfolded, or blown up,
into multiple labels by being paired with different partial
states. For example, the label [loop] in the [parity] program
will become two labels: [([(X,0)], loop)] and [([(X,1)], loop)].
This change of label type is reflected in the types of [pe_block]
and [pe_program] defined presently. *)
Fixpoint pe_block {L:Type} (pe_st:pe_state) (k : block L)
: block (pe_state * L) :=
match k with
| Goto l => Goto (pe_st, l)
| If b l1 l2 =>
match pe_bexp pe_st b with
| BTrue => Goto (pe_st, l1)
| BFalse => Goto (pe_st, l2)
| b' => If b' (pe_st, l1) (pe_st, l2)
end
| Assign i a k =>
match pe_aexp pe_st a with
| ANum n => pe_block (pe_add pe_st i n) k
| a' => Assign i a' (pe_block (pe_remove pe_st i) k)
end
end.
Example pe_block_example:
pe_block [(X,0)] parity_body
= Assign Y <{Y - 1}> (Goto ([(X,1)], loop)).
Proof. reflexivity. Qed.
Theorem pe_block_correct: forall (L:Type) st pe_st k st' pe_st' (l':L),
keval st (pe_block pe_st k) = (st', (pe_st', l')) ->
keval (pe_update st pe_st) k = (pe_update st' pe_st', l').
Proof. intros. generalize dependent pe_st. generalize dependent st.
induction k as [l | b l1 l2 | i a k];
intros st pe_st H.
- (* Goto *) inversion H; reflexivity.
- (* If *)
replace (keval st (pe_block pe_st (If b l1 l2)))
with (keval st (If (pe_bexp pe_st b) (pe_st, l1) (pe_st, l2)))
in H by (simpl; destruct (pe_bexp pe_st b); reflexivity).
simpl in *. rewrite pe_bexp_correct.
destruct (beval st (pe_bexp pe_st b)); inversion H; reflexivity.
- (* Assign *)
simpl in *. rewrite pe_aexp_correct.
destruct (pe_aexp pe_st a); simpl;
try solve [rewrite pe_update_update_add; apply IHk; apply H];
solve [rewrite pe_update_update_remove; apply IHk; apply H].
Qed.
Definition pe_program {L:Type} (p : program L)
: program (pe_state * L) :=
fun pe_l => match pe_l with | (pe_st, l) =>
option_map (pe_block pe_st) (p l)
end.
Inductive pe_peval {L:Type} (p : program L)
(st:state) (pe_st:pe_state) (l:L) (st'o:state) (l':L) : Prop :=
| pe_peval_intro : forall st' pe_st',
peval (pe_program p) st (pe_st, l) st' (pe_st', l') ->
pe_update st' pe_st' = st'o ->
pe_peval p st pe_st l st'o l'.
Theorem pe_program_correct:
forall (L:Type) (p : program L) st pe_st l st'o l',
peval p (pe_update st pe_st) l st'o l' <->
pe_peval p st pe_st l st'o l'.
Proof. intros.
split.
- (* -> *) intros Heval.
remember (pe_update st pe_st) as sto.
generalize dependent pe_st. generalize dependent st.
induction Heval as
[ sto l Hlookup | sto l k st'o l' st''o l'' Hlookup Hkeval Heval ];
intros st pe_st Heqsto; subst sto.
+ (* E_None *) eapply pe_peval_intro. apply E_None.
simpl. rewrite Hlookup. reflexivity. reflexivity.
+ (* E_Some *)
remember (keval st (pe_block pe_st k)) as x.
destruct x as [st' [pe_st' l'_] ].
symmetry in Heqx. erewrite pe_block_correct in Hkeval by apply Heqx.
inversion Hkeval. subst st'o l'_. clear Hkeval.
edestruct IHHeval. reflexivity. subst st''o. clear IHHeval.
eapply pe_peval_intro; [| reflexivity]. eapply E_Some; eauto.
simpl. rewrite Hlookup. reflexivity.
- (* <- *) intros [st' pe_st' Heval Heqst'o].
remember (pe_st, l) as pe_st_l.
remember (pe_st', l') as pe_st'_l'.
generalize dependent pe_st. generalize dependent l.
induction Heval as
[ st [pe_st_ l_] Hlookup
| st [pe_st_ l_] pe_k st' [pe_st'_ l'_] st'' [pe_st'' l'']
Hlookup Hkeval Heval ];
intros l pe_st Heqpe_st_l;
inversion Heqpe_st_l; inversion Heqpe_st'_l'; repeat subst.
+ (* E_None *) apply E_None. simpl in Hlookup.
destruct (p l'); [ solve [ inversion Hlookup ] | reflexivity ].
+ (* E_Some *)
simpl in Hlookup. remember (p l) as k.
destruct k as [k|]; inversion Hlookup; subst.
eapply E_Some; eauto. apply pe_block_correct. apply Hkeval.
Qed.
(* 2020-09-09 21:08 *)
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`timescale 1ns/1ps
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);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [14 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [7 : 0] douta;
blk_mem_gen_v8_2 #(
.C_FAMILY("zynq"),
.C_XDEVICEFAMILY("zynq"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(3),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("CHOPLIFTER.mif"),
.C_INIT_FILE("CHOPLIFTER.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_READ_WIDTH_A(8),
.C_WRITE_DEPTH_A(32768),
.C_READ_DEPTH_A(32768),
.C_ADDRA_WIDTH(15),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(8),
.C_READ_WIDTH_B(8),
.C_WRITE_DEPTH_B(32768),
.C_READ_DEPTH_B(32768),
.C_ADDRB_WIDTH(15),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("8"),
.C_COUNT_18K_BRAM("0"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 2.326399 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(1'B0),
.addra(addra),
.dina(8'B0),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(15'B0),
.dinb(8'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(8'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFXTP_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__SDFXTP_PP_SYMBOL_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__sdfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFXTP_PP_SYMBOL_V
|
`include "mio_constants.vh"
module mrx (/*AUTOARG*/
// Outputs
rx_empty, rx_full, rx_prog_full, rx_wait, access_out, packet_out,
// Inputs
clk, nreset, datasize, ddr_mode, lsbfirst, framepol, rx_clk,
rx_access, rx_packet, wait_in
);
//#####################################################################
//# INTERFACE
//#####################################################################
//parameters
parameter PW = 104; // data width (core)
parameter NMIO = 8; // IO data width
parameter FIFO_DEPTH = 32; // fifo depth
parameter TARGET = "GENERIC"; // GENERIC,XILINX,ALTERA,GENERIC,ASIC
//reset, clk, cfg
input clk; // main core clock
input nreset; // async active low reset
input [7:0] datasize; // size of data transmitted (in bytes, 0=1 byte)
input ddr_mode;
input lsbfirst;
input framepol;
//status
output rx_empty; // rx fifo is empty
output rx_full; // rx fifo is full (should never happen!)
output rx_prog_full;// rx is getting full (stop sending!)
//IO interface
input rx_clk; // clock from IO
input rx_access; // access signal for IO
input [NMIO-1:0] rx_packet; // packet from IO
output rx_wait; // pushback for IO
// data
output access_out; // fifo data valid
output [PW-1:0] packet_out; // fifo packet
input wait_in; // wait pushback for fifo
//#####################################################################
//# BODY
//#####################################################################
/*AUTOOUTPUT*/
/*AUTOINPUT*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire fifo_access; // From mrx_protocol of mrx_protocol.v
wire [PW-1:0] fifo_packet; // From mrx_protocol of mrx_protocol.v
wire io_access; // From mrx_io of mrx_io.v
wire [2*NMIO-1:0] io_packet; // From mrx_io of mrx_io.v
// End of automatics
//########################################
//# SYNCHRONIZATION FIFO
//########################################
/*oh_fifo_cdc AUTO_TEMPLATE (
// outputs
.prog_full (rx_prog_full),
.full (rx_full),
.empty (rx_empty),
.wait_out (rx_wait),
.access_out (access_out),
.packet_out (packet_out[PW-1:0]),
// inputs
.nreset (nreset),
.clk_in (rx_clk),
.access_in (fifo_access),
.packet_in (fifo_packet[PW-1:0]),
.clk_out (clk),
.wait_in (wait_in),
);
*/
oh_fifo_cdc #(.TARGET(TARGET),
.DW(PW),
.DEPTH(FIFO_DEPTH))
fifo (/*AUTOINST*/
// Outputs
.wait_out (rx_wait), // Templated
.access_out (access_out), // Templated
.packet_out (packet_out[PW-1:0]), // Templated
.prog_full (rx_prog_full), // Templated
.full (rx_full), // Templated
.empty (rx_empty), // Templated
// Inputs
.nreset (nreset), // Templated
.clk_in (rx_clk), // Templated
.access_in (fifo_access), // Templated
.packet_in (fifo_packet[PW-1:0]), // Templated
.clk_out (clk), // Templated
.wait_in (wait_in)); // Templated
//########################################
//# PROTOCOL
//########################################
mrx_protocol #(.PW(PW),
.NMIO(NMIO))
mrx_protocol (/*AUTOINST*/
// Outputs
.fifo_access (fifo_access),
.fifo_packet (fifo_packet[PW-1:0]),
// Inputs
.rx_clk (rx_clk),
.nreset (nreset),
.datasize (datasize[7:0]),
.lsbfirst (lsbfirst),
.io_access (io_access),
.io_packet (io_packet[2*NMIO-1:0]));
//########################################
//# FAST IO (DDR)
//########################################
mrx_io #(.NMIO(NMIO))
mrx_io (
/*AUTOINST*/
// Outputs
.io_access (io_access),
.io_packet (io_packet[2*NMIO-1:0]),
// Inputs
.nreset (nreset),
.rx_clk (rx_clk),
.ddr_mode (ddr_mode),
.lsbfirst (lsbfirst),
.framepol (framepol),
.rx_packet (rx_packet[NMIO-1:0]),
.rx_access (rx_access));
endmodule // ctx
// Local Variables:
// verilog-library-directories:("." "../../common/hdl" "../../../oh/emesh/hdl")
// End:
|
/**************************************
* Module: vc
* Date:2016-01-27
* Author: sara
*
* Description: virtual channel
***************************************/
`include "constants.v"
module vc( output reg [1:`FLIT_SIZE] flit_buff,
output reg credit,
output reg is_new,
input [1:`FLIT_SIZE] flit,
input next_router_credit,
input load,
input clock,
input reset);
//S0:wait for packet's flit
//S1:wait for receiving the credit of next router
//S2:credit delay state
parameter S0= 2'b00, S1= 2'b01, S2= 2'b10;
parameter CREDIT_DELAY=16;
reg [1:0]state, next_state;
reg [4:0]credit_delay_counter;
wire [1:`FLIT_SIZE]n_flit_buff;
wire n_credit;
wire n_is_new;
wire [4:0]n_credit_delay_counter;
//end_packet means tail_p=1 in the flit
//control unit
always @(posedge clock or posedge reset)begin
if(reset)
begin
state<= S0;
flit_buff <= {`FLIT_SIZE{1'b0}};
credit <= 1'b1;
credit_delay_counter <= 5'd0;
is_new <= 1'd0;
end
else
begin
state <= next_state;
flit_buff <= n_flit_buff;
credit <= n_credit;
credit_delay_counter <= n_credit_delay_counter;
is_new <= n_is_new;
end
end
always @(state or load or next_router_credit or credit_delay_counter)
begin
next_state<= S0;
case(state)
S0: next_state <= ((load) ? S1: S0);
S1: next_state <= ((next_router_credit == 1) ? S2: S1); // TODO FIXME maybe credit delay should be decrement
S2: next_state <= ((credit_delay_counter < CREDIT_DELAY) ? S2: S0);
endcase
end
assign n_credit = (reset == 1'b0 ? (state == S0 ? 1'd1: 1'd0): 1'd1);
assign n_flit_buff = (reset == 1'b0 ? ((state == S0 && load == 1'b1) ? flit : flit_buff) : {`FLIT_SIZE{1'b0}});
assign n_credit_delay_counter = (reset == 0 ?(state == S2 ? credit_delay_counter + 5'd1 : 5'd0): 5'd0);
assign n_is_new = (reset == 1'b0 ? (state == S1 ? 1'b1 : 1'b0) : 1'b0);
endmodule
|
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`timescale 1ns/1ps
`ifdef SYN
`include "/afs/eecs.umich.edu/kits/ARM/TSMC_cl018g/mosis_2009q1/sc-x_2004q3v1/aci/sc/verilog/tsmc18_neg.v"
`elsif APR
`include "/afs/eecs.umich.edu/kits/ARM/TSMC_cl018g/mosis_2009q1/sc-x_2004q3v1/aci/sc/verilog/tsmc18_neg.v"
`endif
`include "include/mbus_def.v"
module tb_mbus();
reg clk, resetn;
wire SCLK;
// n0 connections
reg [`ADDR_WIDTH-1:0] n0_tx_addr;
reg [`DATA_WIDTH-1:0] n0_tx_data;
reg n0_tx_req, n0_priority, n0_tx_pend, n0_tx_resp_ack;
wire n0_tx_ack, n0_tx_succ, n0_tx_fail;
wire [`ADDR_WIDTH-1:0] n0_rx_addr;
wire [`DATA_WIDTH-1:0] n0_rx_data;
wire n0_rx_req, n0_rx_fail, n0_rx_pend, n0_rx_broadcast;
reg n0_rx_ack;
// end of n0 connections
// n1 connections
reg [`ADDR_WIDTH-1:0] n1_tx_addr;
reg [`DATA_WIDTH-1:0] n1_tx_data;
reg n1_tx_req, n1_priority, n1_tx_pend, n1_tx_resp_ack;
wire n1_tx_ack, n1_tx_succ, n1_tx_fail;
wire [`ADDR_WIDTH-1:0] n1_rx_addr;
wire [`DATA_WIDTH-1:0] n1_rx_data;
wire n1_rx_req, n1_rx_fail, n1_rx_pend, n1_rx_broadcast;
reg n1_rx_ack;
// end of n1 connections
// n2 connections
reg [`ADDR_WIDTH-1:0] n2_tx_addr;
reg [`DATA_WIDTH-1:0] n2_tx_data;
reg n2_tx_req, n2_priority, n2_tx_pend, n2_tx_resp_ack;
wire n2_tx_ack, n2_tx_succ, n2_tx_fail;
wire [`ADDR_WIDTH-1:0] n2_rx_addr;
wire [`DATA_WIDTH-1:0] n2_rx_data;
wire n2_rx_req, n2_rx_fail, n2_rx_pend, n2_rx_broadcast;
reg n2_rx_ack;
// end of n2 connections
// n3 connections
reg [`ADDR_WIDTH-1:0] n3_tx_addr;
reg [`DATA_WIDTH-1:0] n3_tx_data;
reg n3_tx_req, n3_priority, n3_tx_pend, n3_tx_resp_ack;
wire n3_tx_ack, n3_tx_succ, n3_tx_fail;
wire [`ADDR_WIDTH-1:0] n3_rx_addr;
wire [`DATA_WIDTH-1:0] n3_rx_data;
wire n3_rx_req, n3_rx_fail, n3_rx_pend, n3_rx_broadcast;
reg n3_rx_ack;
// end of n3 connections
// c0 connections
reg [`ADDR_WIDTH-1:0] c0_tx_addr;
reg [`DATA_WIDTH-1:0] c0_tx_data;
reg c0_tx_req, c0_priority, c0_tx_pend, c0_tx_resp_ack;
wire c0_tx_ack, c0_tx_succ, c0_tx_fail;
wire [`ADDR_WIDTH-1:0] c0_rx_addr;
wire [`DATA_WIDTH-1:0] c0_rx_data;
wire c0_rx_req, c0_rx_fail, c0_rx_pend, c0_rx_broadcast;
reg c0_rx_ack;
// end of c0 connections
// connection between nodes
wire w_n0n1, w_n1n2, w_n2n3, w_n3c0, w_c0n0;
wire w_n0_clk_out, w_n1_clk_out, w_n2_clk_out, w_n3_clk_out;
// testbench variables
reg [31:0] rand_dat, rand_dat2;
reg [4:0] state;
reg [5:0] word_counter;
integer handle;
parameter TASK0=0;
parameter TASK1=1;
parameter TASK2=2;
parameter TASK3=3;
parameter TASK4=4;
parameter TASK5=5;
parameter TASK6=6;
parameter TASK7=7;
parameter TASK8=8;
parameter TASK9=9;
parameter TASK10=10;
parameter TASK11=11;
parameter TASK12=12;
parameter TASK13=13;
parameter TASK14=14;
parameter TASK15=15;
parameter TASK16=16;
parameter TASK17=17;
parameter TASK18=18;
parameter TASK19=19;
parameter TASK20=20;
parameter TASK21=21;
parameter TASK22=22;
parameter TASK23=23;
parameter TASK24=24;
parameter TASK25=25;
parameter TASK26=26;
parameter TASK27=27;
parameter TX_WAIT=31;
reg n0_auto_rx_ack, n1_auto_rx_ack, n2_auto_rx_ack, n3_auto_rx_ack, c0_auto_rx_ack;
mbus_layer_wrapper #(.ADDRESS(20'hbbbb0)) n0
(.CLKIN(SCLK), .CLKOUT(w_n0_clk_out), .RESETn(resetn), .DIN(w_c0n0), .DOUT(w_n0n1),
.TX_ADDR(n0_tx_addr), .TX_DATA(n0_tx_data), .TX_REQ(n0_tx_req), .TX_ACK(n0_tx_ack), .TX_PEND(n0_tx_pend), .TX_PRIORITY(n0_priority),
.RX_ADDR(n0_rx_addr), .RX_DATA(n0_rx_data), .RX_REQ(n0_rx_req), .RX_ACK(n0_rx_ack), .RX_FAIL(n0_rx_fail), .RX_PEND(n0_rx_pend),
.TX_SUCC(n0_tx_succ), .TX_FAIL(n0_tx_fail), .TX_RESP_ACK(n0_tx_resp_ack), .RX_BROADCAST(n0_rx_broadcast));
mbus_layer_wrapper #(.ADDRESS(20'hbbbb1)) n1
(.CLKIN(w_n0_clk_out), .CLKOUT(w_n1_clk_out), .RESETn(resetn), .DIN(w_n0n1), .DOUT(w_n1n2),
.TX_ADDR(n1_tx_addr), .TX_DATA(n1_tx_data), .TX_REQ(n1_tx_req), .TX_ACK(n1_tx_ack), .TX_PEND(n1_tx_pend), .TX_PRIORITY(n1_priority),
.RX_ADDR(n1_rx_addr), .RX_DATA(n1_rx_data), .RX_REQ(n1_rx_req), .RX_ACK(n1_rx_ack), .RX_FAIL(n1_rx_fail), .RX_PEND(n1_rx_pend),
.TX_SUCC(n1_tx_succ), .TX_FAIL(n1_tx_fail), .TX_RESP_ACK(n1_tx_resp_ack), .RX_BROADCAST(n1_rx_broadcast));
mbus_layer_wrapper #(.ADDRESS(20'hbbbb2)) n2
(.CLKIN(w_n1_clk_out), .CLKOUT(w_n2_clk_out), .RESETn(resetn), .DIN(w_n1n2), .DOUT(w_n2n3),
.TX_ADDR(n2_tx_addr), .TX_DATA(n2_tx_data), .TX_REQ(n2_tx_req), .TX_ACK(n2_tx_ack), .TX_PEND(n2_tx_pend), .TX_PRIORITY(n2_priority),
.RX_ADDR(n2_rx_addr), .RX_DATA(n2_rx_data), .RX_REQ(n2_rx_req), .RX_ACK(n2_rx_ack), .RX_FAIL(n2_rx_fail), .RX_PEND(n2_rx_pend),
.TX_SUCC(n2_tx_succ), .TX_FAIL(n2_tx_fail), .TX_RESP_ACK(n2_tx_resp_ack), .RX_BROADCAST(n2_rx_broadcast));
mbus_layer_wrapper #(.ADDRESS(20'hbbbb2)) n3
(.CLKIN(w_n2_clk_out), .CLKOUT(w_n3_clk_out), .RESETn(resetn), .DIN(w_n2n3), .DOUT(w_n3c0),
.TX_ADDR(n3_tx_addr), .TX_DATA(n3_tx_data), .TX_REQ(n3_tx_req), .TX_ACK(n3_tx_ack), .TX_PEND(n3_tx_pend), .TX_PRIORITY(n3_priority),
.RX_ADDR(n3_rx_addr), .RX_DATA(n3_rx_data), .RX_REQ(n3_rx_req), .RX_ACK(n3_rx_ack), .RX_FAIL(n3_rx_fail), .RX_PEND(n3_rx_pend),
.TX_SUCC(n3_tx_succ), .TX_FAIL(n3_tx_fail), .TX_RESP_ACK(n3_tx_resp_ack), .RX_BROADCAST(n3_rx_broadcast));
mbus_ctrl_layer_wrapper #(.ADDRESS(20'haaaa0)) c0
(.CLK_EXT(clk), .CLKIN(w_n3_clk_out), .CLKOUT(SCLK), .RESETn(resetn), .DIN(w_n3c0), .DOUT(w_c0n0),
.TX_ADDR(c0_tx_addr), .TX_DATA(c0_tx_data), .TX_REQ(c0_tx_req), .TX_ACK(c0_tx_ack), .TX_PEND(c0_tx_pend), .TX_PRIORITY(c0_priority),
.RX_ADDR(c0_rx_addr), .RX_DATA(c0_rx_data), .RX_REQ(c0_rx_req), .RX_ACK(c0_rx_ack), .RX_FAIL(c0_rx_fail), .RX_PEND(c0_rx_pend),
.TX_SUCC(c0_tx_succ), .TX_FAIL(c0_tx_fail), .TX_RESP_ACK(c0_tx_resp_ack), .RX_BROADCAST(c0_rx_broadcast));
initial begin
clk = 0;
resetn = 1;
state = 5'h1F;
@ (posedge clk);
@ (posedge clk);
@ (posedge clk);
`SD resetn = 0;
@ (posedge clk);
@ (posedge clk);
`SD resetn = 1;
@ (posedge clk);
@ (posedge clk);
//VCD DUMP SECTION
//`ifdef APR
/*
`ifdef TASK4
$dumpfile("task4.vcd");
`elsif TASK5
$dumpfile("task5.vcd");
`endif
$dumpvars(0, tb_ulpb_node32);
*/
//`endif
/*
//SDF ANNOTATION
`ifdef SYN
$sdf_annotate("../syn/ulpb_ctrl_wrapper.dc.sdf", c0);
$sdf_annotate("../syn/ulpb_node32_ab.dc.sdf", n0);
$sdf_annotate("../syn/ulpb_node32_cd.dc.sdf", n1);
$sdf_annotate("../syn/ulpb_node32_ef.dc.sdf", n2);
`elsif APR
$sdf_annotate("../apr/ulpb_ctrl_wrapper/ulpb_ctrl_wrapper.apr.sdf", c0);
$sdf_annotate("../apr/ulpb_node32_ab/ulpb_node32_ab.apr.sdf", n0);
$sdf_annotate("../apr/ulpb_node32_cd/ulpb_node32_cd.apr.sdf", n1);
$sdf_annotate("../apr/ulpb_node32_ef/ulpb_node32_ef.apr.sdf", n2);
`endif
*/
//************************
//TESTBENCH BEGINS
//Calls Tasks from tasks.v
//***********************
`ifdef TASK0
task0();
`elsif TASK1
task1();
`elsif TASK2
task2();
`else
$display("**************************************");
$display("************NO TASKS SUPPLIED*********");
$display("****************FAILURE***************");
$display("**************************************");
$finish;
`endif
end // initial begin
//Changed to 400K for primetime calculations
always #1250 clk = ~clk;
`ifdef TASK0
`include "task0.v"
`elsif TASK1
`include "task1.v"
`elsif TASK2
`include "task2.v"
`endif
always @ (posedge clk or negedge resetn)
begin
if (~resetn)
begin
n0_tx_addr <= 0;
n0_tx_data <= 0;
n0_tx_pend <= 0;
n0_tx_req <= 0;
n0_priority <= 0;
n0_auto_rx_ack <= 1;
n1_tx_addr <= 0;
n1_tx_data <= 0;
n1_tx_pend <= 0;
n1_tx_req <= 0;
n1_priority <= 0;
n1_auto_rx_ack <= 1;
n2_tx_addr <= 0;
n2_tx_data <= 0;
n2_tx_pend <= 0;
n2_tx_req <= 0;
n2_priority <= 0;
n2_auto_rx_ack <= 1;
n3_tx_addr <= 0;
n3_tx_data <= 0;
n3_tx_pend <= 0;
n3_tx_req <= 0;
n3_priority <= 0;
n3_auto_rx_ack <= 1;
c0_tx_addr <= 0;
c0_tx_data <= 0;
c0_tx_pend <= 0;
c0_tx_req <= 0;
c0_priority <= 0;
c0_auto_rx_ack <= 1;
word_counter <= 0;
end
else
begin
if (n0_tx_ack) n0_tx_req <= 0;
if (n1_tx_ack) n1_tx_req <= 0;
if (n2_tx_ack) n2_tx_req <= 0;
if (n3_tx_ack) n3_tx_req <= 0;
if (c0_tx_ack) c0_tx_req <= 0;
end
end
// n0 rx tx ack control
always @ (negedge resetn)
begin
n0_rx_ack <= 0;
n0_tx_resp_ack <= 0;
end
always @ (posedge n0_rx_fail)
$fdisplay(handle, "N0 RX Fail");
always @ (posedge n0_rx_req)
begin
$fdisplay(handle, "N0 RX Success");
$fdisplay(handle, "N0 Data out =\t32'h%h", n0_rx_data);
end
always @ (posedge clk)
begin
if ((n0_rx_req | n0_rx_fail) & n0_auto_rx_ack)
`SD n0_rx_ack <= 1;
if (n0_rx_ack & (~n0_rx_req))
`SD n0_rx_ack <= 0;
if (n0_rx_ack & (~n0_rx_fail))
`SD n0_rx_ack <= 0;
end
always @ (posedge n0_tx_succ)
$fdisplay(handle, "N0 TX Success\n");
always @ (posedge n0_tx_fail)
$fdisplay(handle, "N0 TX Fail\n");
always @ (posedge clk)
begin
if (n0_tx_succ | n0_tx_fail)
`SD n0_tx_resp_ack <= 1;
if (n0_tx_resp_ack & (~n0_tx_succ))
`SD n0_tx_resp_ack <= 0;
if (n0_tx_resp_ack & (~n0_tx_fail))
`SD n0_tx_resp_ack <= 0;
end
// end of n0 rx, tx ack control
// n1 rx tx ack control
always @ (negedge resetn)
begin
n1_rx_ack <= 0;
n1_tx_resp_ack <= 0;
end
always @ (posedge n1_rx_fail)
$fdisplay(handle, "N1 RX Fail");
always @ (posedge n1_rx_req)
begin
$fdisplay(handle, "N1 RX Success");
$fdisplay(handle, "N1 Data out =\t32'h%h", n1_rx_data);
end
always @ (posedge clk)
begin
if ((n1_rx_req | n1_rx_fail) & n1_auto_rx_ack)
`SD n1_rx_ack <= 1;
if (n1_rx_ack & (~n1_rx_req))
`SD n1_rx_ack <= 0;
if (n1_rx_ack & (~n1_rx_fail))
`SD n1_rx_ack <= 0;
end
always @ (posedge n1_tx_succ)
$fdisplay(handle, "N1 TX Success\n");
always @ (posedge n1_tx_fail)
$fdisplay(handle, "N1 TX Fail\n");
always @ (posedge clk)
begin
if (n1_tx_succ | n1_tx_fail)
`SD n1_tx_resp_ack <= 1;
if (n1_tx_resp_ack & (~n1_tx_succ))
`SD n1_tx_resp_ack <= 0;
if (n1_tx_resp_ack & (~n1_tx_fail))
`SD n1_tx_resp_ack <= 0;
end
// end of n1 rx, tx ack control
// n2 rx tx ack control
always @ (negedge resetn)
begin
n2_rx_ack <= 0;
n2_tx_resp_ack <= 0;
end
always @ (posedge n2_rx_fail)
$fdisplay(handle, "N2 RX Fail");
always @ (posedge n2_rx_req)
begin
$fdisplay(handle, "N2 RX Success");
$fdisplay(handle, "N2 Data out =\t32'h%h", n2_rx_data);
end
always @ (posedge clk)
begin
if ((n2_rx_req | n2_rx_fail) & n2_auto_rx_ack)
`SD n2_rx_ack <= 1;
if (n2_rx_ack & (~n2_rx_req))
`SD n2_rx_ack <= 0;
if (n2_rx_ack & (~n2_rx_fail))
`SD n2_rx_ack <= 0;
end
always @ (posedge n2_tx_succ)
$fdisplay(handle, "N2 TX Success\n");
always @ (posedge n2_tx_fail)
$fdisplay(handle, "N2 TX Fail\n");
always @ (posedge clk)
begin
if (n2_tx_succ | n2_tx_fail)
`SD n2_tx_resp_ack <= 1;
if (n2_tx_resp_ack & (~n2_tx_succ))
`SD n2_tx_resp_ack <= 0;
if (n2_tx_resp_ack & (~n2_tx_fail))
`SD n2_tx_resp_ack <= 0;
end
// end of n2 rx, tx ack control
// n3 rx tx ack control
always @ (negedge resetn)
begin
n3_rx_ack <= 0;
n3_tx_resp_ack <= 0;
end
always @ (posedge n3_rx_fail)
$fdisplay(handle, "N3 RX Fail");
always @ (posedge n3_rx_req)
begin
$fdisplay(handle, "N3 RX Success");
$fdisplay(handle, "N3 Data out =\t32'h%h", n3_rx_data);
end
always @ (posedge clk)
begin
if ((n3_rx_req | n3_rx_fail) & n3_auto_rx_ack)
`SD n3_rx_ack <= 1;
if (n3_rx_ack & (~n3_rx_req))
`SD n3_rx_ack <= 0;
if (n3_rx_ack & (~n3_rx_fail))
`SD n3_rx_ack <= 0;
end
always @ (posedge n3_tx_succ)
$fdisplay(handle, "N3 TX Success\n");
always @ (posedge n3_tx_fail)
$fdisplay(handle, "N3 TX Fail\n");
always @ (posedge clk)
begin
if (n3_tx_succ | n3_tx_fail)
`SD n3_tx_resp_ack <= 1;
if (n3_tx_resp_ack & (~n3_tx_succ))
`SD n3_tx_resp_ack <= 0;
if (n3_tx_resp_ack & (~n3_tx_fail))
`SD n3_tx_resp_ack <= 0;
end
// end of n3 rx, tx ack control
// c0 rx tx ack control
always @ (negedge resetn)
begin
c0_rx_ack <= 0;
c0_tx_resp_ack <= 0;
end
always @ (posedge c0_rx_fail)
$fdisplay(handle, "C0 RX Fail");
always @ (posedge c0_rx_req)
begin
$fdisplay(handle, "C0 RX Success");
$fdisplay(handle, "C0 Data out =\t32'h%h", c0_rx_data);
end
always @ (posedge clk)
begin
if ((c0_rx_req | c0_rx_fail) & c0_auto_rx_ack)
`SD c0_rx_ack <= 1;
if (c0_rx_ack & (~c0_rx_req))
`SD c0_rx_ack <= 0;
if (c0_rx_ack & (~c0_rx_fail))
`SD c0_rx_ack <= 0;
end
always @ (posedge c0_tx_succ)
$fdisplay(handle, "C0 TX Success\n");
always @ (posedge c0_tx_fail)
$fdisplay(handle, "C0 TX Fail\n");
always @ (posedge clk)
begin
if (c0_tx_succ | c0_tx_fail)
`SD c0_tx_resp_ack <= 1;
if (c0_tx_resp_ack & (~c0_tx_succ))
`SD c0_tx_resp_ack <= 0;
if (c0_tx_resp_ack & (~c0_tx_fail))
`SD c0_tx_resp_ack <= 0;
end
// end of c0 rx, tx ack control
always @ (posedge clk or negedge resetn) begin
if (~resetn) begin
rand_dat <= 0;
rand_dat2 <= 0;
end
else begin
rand_dat <= $random;
rand_dat2 <= $random;
end
end
`include "tasks.v"
endmodule // tb_ulpb_node32
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_DLATCH_P_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_HDLL__UDP_DLATCH_P_PP_PG_N_BLACKBOX_V
/**
* udp_dlatch$P_pp$PG$N: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__udp_dlatch$P_pp$PG$N (
Q ,
D ,
GATE ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input GATE ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_DLATCH_P_PP_PG_N_BLACKBOX_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dram_ecc_cor.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module dram_ecc_cor (/*AUTOARG*/
// Outputs
ecc_multi_err, ecc_single_err, cor_data, ecc_loc, syndrome,
// Inputs
clk, raw_ecc, raw_data, l2if_dram_fail_over_mode
);
// synopsys template
// Input Declarations
input clk;
input [15:0] raw_ecc;
input [127:0] raw_data;
input l2if_dram_fail_over_mode;
// Output Declarations
output ecc_multi_err;
output ecc_single_err;
output [127:0] cor_data;
output [35:0] ecc_loc;
output [15:0] syndrome;
// Wire Declarations
wire [127:0] fixed_data;
wire [3:0] outbyte0;
wire [3:0] outbyte1;
wire [3:0] outbyte2;
wire [3:0] outbyte3;
wire [3:0] outbyte4;
wire [3:0] outbyte5;
wire [3:0] outbyte6;
wire [3:0] outbyte7;
wire [3:0] outbyte8;
wire [3:0] outbyte9;
wire [3:0] outbyte10;
wire [3:0] outbyte11;
wire [3:0] outbyte12;
wire [3:0] outbyte13;
wire [3:0] outbyte14;
wire [3:0] outbyte15;
wire [3:0] outbyte16;
wire [3:0] outbyte17;
wire [3:0] outbyte18;
wire [3:0] outbyte19;
wire [3:0] outbyte20;
wire [3:0] outbyte21;
wire [3:0] outbyte22;
wire [3:0] outbyte23;
wire [3:0] outbyte24;
wire [3:0] outbyte25;
wire [3:0] outbyte26;
wire [3:0] outbyte27;
wire [3:0] outbyte28;
wire [3:0] outbyte29;
wire [3:0] outbyte30;
wire [3:0] outbyte31;
wire [3:0] eccresult0;
wire [3:0] eccresult1;
wire [3:0] eccresult2;
wire [3:0] eccresult3;
wire [3:0] eccresult0_d1;
wire [3:0] eccresult1_d1;
wire [3:0] eccresult2_d1;
wire [3:0] eccresult3_d1;
wire [3:0] diff_ecc0;
wire [3:0] diff_ecc1;
wire [3:0] diff_ecc2;
wire [3:0] diff_ecc3;
wire [3:0] diff_ecc0_d1;
wire [3:0] diff_ecc1_d1;
wire [3:0] diff_ecc2_d1;
wire [3:0] diff_ecc3_d1;
wire [111:0] cor_result;
wire [127:0] raw_data_d1;
wire [3:0] cor_result2_d1;
wire [3:0] cor_result3_d1;
wire [3:0] cor_result4_d1;
wire [3:0] cor_result5_d1;
wire [3:0] cor_result6_d1;
wire [3:0] cor_result7_d1;
wire [3:0] cor_result8_d1;
wire [3:0] cor_result9_d1;
wire [3:0] cor_result10_d1;
wire [3:0] cor_result11_d1;
wire [3:0] cor_result12_d1;
wire [3:0] cor_result13_d1;
wire [3:0] cor_result14_d1;
wire [3:0] cor_result15_d1;
//wire [3:0] cor_result16_d1;
wire [3:0] cor_result17_d1;
wire [3:0] cor_result18_d1;
wire [3:0] cor_result19_d1;
wire [3:0] cor_result20_d1;
wire [3:0] cor_result21_d1;
wire [3:0] cor_result22_d1;
wire [3:0] cor_result23_d1;
wire [3:0] cor_result24_d1;
wire [3:0] cor_result25_d1;
wire [3:0] cor_result26_d1;
wire [3:0] cor_result27_d1;
wire [3:0] cor_result28_d1;
wire [3:0] cor_result29_d1;
wire [3:0] cor_result30_d1;
wire [3:0] inbyte0_d2;
wire [3:0] inbyte1_d2;
wire [3:0] inbyte2_d2;
wire [3:0] inbyte3_d2;
wire [3:0] inbyte4_d2;
wire [3:0] inbyte5_d2;
wire [3:0] inbyte6_d2;
wire [3:0] inbyte7_d2;
wire [3:0] inbyte8_d2;
wire [3:0] inbyte9_d2;
wire [3:0] inbyte10_d2;
wire [3:0] inbyte11_d2;
wire [3:0] inbyte12_d2;
wire [3:0] inbyte13_d2;
wire [3:0] inbyte14_d2;
wire [3:0] inbyte15_d2;
wire [3:0] inbyte16_d2;
wire [3:0] inbyte17_d2;
wire [3:0] inbyte18_d2;
wire [3:0] inbyte19_d2;
wire [3:0] inbyte20_d2;
wire [3:0] inbyte21_d2;
wire [3:0] inbyte22_d2;
wire [3:0] inbyte23_d2;
wire [3:0] inbyte24_d2;
wire [3:0] inbyte25_d2;
wire [3:0] inbyte26_d2;
wire [3:0] inbyte27_d2;
wire [3:0] inbyte28_d2;
wire [3:0] inbyte29_d2;
wire [3:0] inbyte30_d2;
wire [3:0] inbyte31_d2;
wire [15:0] raw_ecc_d1;
///////////////////////////////
////// Code Begins Here ///////
///////////////////////////////
dram_ecc_gen ecc_gen(
// Outputs
.ecc({eccresult0, eccresult1, eccresult2, eccresult3}),
// Intputs
.data(raw_data));
// Find if ecc generated is different from the stored ecc
dff_ns #(16) ff_ecc_result(
.din({eccresult0, eccresult1, eccresult2, eccresult3}),
.q({eccresult0_d1, eccresult1_d1, eccresult2_d1, eccresult3_d1}),
.clk(clk));
dff_ns #(16) ff_raw_ecc(
.din(raw_ecc[15:0]),
.q(raw_ecc_d1[15:0]),
.clk(clk));
assign diff_ecc0 = eccresult0_d1 ^ raw_ecc_d1[15:12];
assign diff_ecc1 = eccresult1_d1 ^ raw_ecc_d1[11:8];
assign diff_ecc2 = eccresult2_d1 ^ raw_ecc_d1[7:4];
assign diff_ecc3 = eccresult3_d1 ^ raw_ecc_d1[3:0];
assign syndrome = {diff_ecc3, diff_ecc2, diff_ecc1, diff_ecc0};
/////////////////////////////////////////////////////////////////////////
// ECC correction logic
/////////////////////////////////////////////////////////////////////////
wire [3:0] err_nibble;
assign err_nibble = (diff_ecc2 != 4'h0) ? diff_ecc2 : diff_ecc1;
dram_ecc_gen ecc_cor(
// Outputs
.result(cor_result),
// Intputs
.data({32{err_nibble[3:0]}}));
// If 3 out of 4 syndrome nibbles are zero then its error in syndrome bits. So, we force the diff ecc to 0 in such case
// to not flip data bits.
wire [3:0] diff_ecc0_in;
wire [3:0] diff_ecc1_in;
wire [3:0] diff_ecc2_in;
wire [3:0] diff_ecc3_in;
wire [3:0] secc_err;
wire [3:0] secc_err_d1;
assign diff_ecc0_in = (diff_ecc1 == 4'h0) & (diff_ecc2 == 4'h0) & ((diff_ecc3 == 4'h0) & ~l2if_dram_fail_over_mode |
l2if_dram_fail_over_mode) ? 4'h0 : diff_ecc0;
assign diff_ecc1_in = (diff_ecc0 == 4'h0) & (diff_ecc2 == 4'h0) & ((diff_ecc3 == 4'h0) & ~l2if_dram_fail_over_mode |
l2if_dram_fail_over_mode) ? 4'h0 : diff_ecc1;
assign diff_ecc2_in = (diff_ecc0 == 4'h0) & (diff_ecc1 == 4'h0) & ((diff_ecc3 == 4'h0) & ~l2if_dram_fail_over_mode |
l2if_dram_fail_over_mode) ? 4'h0 : diff_ecc2;
assign diff_ecc3_in = (diff_ecc0 == 4'h0) & (diff_ecc1 == 4'h0) & (diff_ecc2 == 4'h0) ? 4'h0 : diff_ecc3;
assign secc_err[0] = (diff_ecc1 == 4'h0) & (diff_ecc2 == 4'h0) & ((diff_ecc3 == 4'h0) & ~l2if_dram_fail_over_mode |
l2if_dram_fail_over_mode) & (diff_ecc0 != 4'h0) ? 1'b1 : 1'b0;
assign secc_err[1] = (diff_ecc0 == 4'h0) & (diff_ecc2 == 4'h0) & ((diff_ecc3 == 4'h0) & ~l2if_dram_fail_over_mode |
l2if_dram_fail_over_mode) & (diff_ecc1 != 4'h0) ? 1'b1 : 1'b0;
assign secc_err[2] = (diff_ecc0 == 4'h0) & (diff_ecc1 == 4'h0) & ((diff_ecc3 == 4'h0) & ~l2if_dram_fail_over_mode |
l2if_dram_fail_over_mode) & (diff_ecc2 != 4'h0) ? 1'b1 : 1'b0;
assign secc_err[3] = (diff_ecc0 == 4'h0) & (diff_ecc1 == 4'h0) & (diff_ecc2 == 4'h0) & (diff_ecc3 != 4'h0) &
~l2if_dram_fail_over_mode ? 1'b1 : 1'b0;
// Need to flop to meet timing
dff_ns #(20) ff_diff_ecc(
.din({secc_err, diff_ecc0_in, diff_ecc1_in, diff_ecc2_in, diff_ecc3_in}),
.q({secc_err_d1, diff_ecc0_d1, diff_ecc1_d1, diff_ecc2_d1, diff_ecc3_d1}),
.clk(clk));
dff_ns #(112) ff_cor_res(
.din(cor_result),
.q({ cor_result30_d1, cor_result29_d1, cor_result28_d1, cor_result27_d1,
cor_result26_d1, cor_result25_d1, cor_result24_d1, cor_result23_d1,
cor_result22_d1, cor_result21_d1, cor_result20_d1,
cor_result19_d1, cor_result18_d1, cor_result17_d1,
cor_result15_d1, cor_result14_d1, cor_result13_d1,
cor_result12_d1, cor_result11_d1, cor_result10_d1, cor_result9_d1,
cor_result8_d1, cor_result7_d1, cor_result6_d1, cor_result5_d1,
cor_result4_d1, cor_result3_d1, cor_result2_d1}),
.clk(clk));
// Flop input data
dff_ns #(128) ff_raw_data(
.din(raw_data[127:0]),
.q(raw_data_d1[127:0]),
.clk(clk));
dff_ns #(128) ff_raw_data_d1(
.din(raw_data_d1[127:0]),
.q({inbyte31_d2, inbyte30_d2, inbyte29_d2, inbyte28_d2, inbyte27_d2, inbyte26_d2,
inbyte25_d2, inbyte24_d2, inbyte23_d2, inbyte22_d2, inbyte21_d2,
inbyte20_d2, inbyte19_d2, inbyte18_d2, inbyte17_d2, inbyte16_d2,
inbyte15_d2, inbyte14_d2, inbyte13_d2, inbyte12_d2, inbyte11_d2,
inbyte10_d2, inbyte9_d2, inbyte8_d2, inbyte7_d2, inbyte6_d2,
inbyte5_d2, inbyte4_d2, inbyte3_d2, inbyte2_d2, inbyte1_d2, inbyte0_d2 }),
.clk(clk));
// Correcting nibbles 0-14 - diff0/diff1
wire byte0_err = (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 == 4'h0) & (diff_ecc1_d1 == diff_ecc0_d1) ? 1'b1 : 1'b0;
assign outbyte0 = inbyte0_d2 ^ (byte0_err ? diff_ecc1_d1 : 4'h0);
wire byte1_err = (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 == 4'h0) & (cor_result2_d1 == diff_ecc0_d1) ? 1'b1 : 1'b0;
assign outbyte1 = inbyte1_d2 ^ (byte1_err ? diff_ecc1_d1 : 4'h0);
wire byte2_err = (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 == 4'h0) & (cor_result3_d1 == diff_ecc0_d1) ? 1'b1 : 1'b0;
assign outbyte2 = inbyte2_d2 ^ (byte2_err ? diff_ecc1_d1 : 4'h0);
wire byte3_err = (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 == 4'h0) & (cor_result4_d1 == diff_ecc0_d1) ? 1'b1 : 1'b0;
assign outbyte3 = inbyte3_d2 ^ (byte3_err ? diff_ecc1_d1 : 4'h0);
wire byte4_err = (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 == 4'h0) & (cor_result5_d1 == diff_ecc0_d1) ? 1'b1 : 1'b0;
assign outbyte4 = inbyte4_d2 ^ (byte4_err ? diff_ecc1_d1 : 4'h0);
wire byte5_err = (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 == 4'h0) & (cor_result6_d1 == diff_ecc0_d1) ? 1'b1 : 1'b0;
assign outbyte5 = inbyte5_d2 ^ (byte5_err ? diff_ecc1_d1 : 4'h0);
wire byte6_err = (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 == 4'h0) & (cor_result7_d1 == diff_ecc0_d1) ? 1'b1 : 1'b0;
assign outbyte6 = inbyte6_d2 ^ (byte6_err ? diff_ecc1_d1 : 4'h0);
wire byte7_err = (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 == 4'h0) & (cor_result8_d1 == diff_ecc0_d1) ? 1'b1 : 1'b0;
assign outbyte7 = inbyte7_d2 ^ (byte7_err ? diff_ecc1_d1 : 4'h0);
wire byte8_err = (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 == 4'h0) & (cor_result9_d1 == diff_ecc0_d1) ? 1'b1 : 1'b0;
assign outbyte8 = inbyte8_d2 ^ (byte8_err ? diff_ecc1_d1 : 4'h0);
wire byte9_err = (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 == 4'h0) & (cor_result10_d1 == diff_ecc0_d1) ? 1'b1 : 1'b0;
assign outbyte9 = inbyte9_d2 ^ (byte9_err ? diff_ecc1_d1 : 4'h0);
wire byte10_err = (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 == 4'h0) & (cor_result11_d1 == diff_ecc0_d1) ? 1'b1 : 1'b0;
assign outbyte10 = inbyte10_d2 ^ (byte10_err ? diff_ecc1_d1 : 4'h0);
wire byte11_err = (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 == 4'h0) & (cor_result12_d1 == diff_ecc0_d1) ? 1'b1 : 1'b0;
assign outbyte11 = inbyte11_d2 ^ (byte11_err ? diff_ecc1_d1 : 4'h0);
wire byte12_err = (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 == 4'h0) & (cor_result13_d1 == diff_ecc0_d1) ? 1'b1 : 1'b0;
assign outbyte12 = inbyte12_d2 ^ (byte12_err ? diff_ecc1_d1 : 4'h0);
wire byte13_err = (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 == 4'h0) & (cor_result14_d1 == diff_ecc0_d1) ? 1'b1 : 1'b0;
assign outbyte13 = inbyte13_d2 ^ (byte13_err ? diff_ecc1_d1 : 4'h0);
wire byte14_err = (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 == 4'h0) & (cor_result15_d1 == diff_ecc0_d1) ? 1'b1 : 1'b0;
assign outbyte14 = inbyte14_d2 ^ (byte14_err ? diff_ecc1_d1 : 4'h0);
// Logic used for MECC detection - diff3/diff1
wire byte0_err_mecc = (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 == 4'h0) & (diff_ecc1_d1 == diff_ecc3_d1) ? 1'b1 : 1'b0;
wire byte8_err_mecc = (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 == 4'h0) & (cor_result2_d1 == diff_ecc3_d1) ? 1'b1 : 1'b0;
wire byte13_err_mecc = (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 == 4'h0) & (cor_result3_d1 == diff_ecc3_d1) ? 1'b1 : 1'b0;
wire byte12_err_mecc = (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 == 4'h0) & (cor_result4_d1 == diff_ecc3_d1) ? 1'b1 : 1'b0;
wire byte10_err_mecc = (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 == 4'h0) & (cor_result5_d1 == diff_ecc3_d1) ? 1'b1 : 1'b0;
wire byte6_err_mecc = (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 == 4'h0) & (cor_result6_d1 == diff_ecc3_d1) ? 1'b1 : 1'b0;
wire byte5_err_mecc = (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 == 4'h0) & (cor_result7_d1 == diff_ecc3_d1) ? 1'b1 : 1'b0;
wire byte14_err_mecc = (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 == 4'h0) & (cor_result8_d1 == diff_ecc3_d1) ? 1'b1 : 1'b0;
wire byte1_err_mecc = (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 == 4'h0) & (cor_result9_d1 == diff_ecc3_d1) ? 1'b1 : 1'b0;
wire byte11_err_mecc = (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 == 4'h0) & (cor_result10_d1 == diff_ecc3_d1) ? 1'b1 : 1'b0;
wire byte4_err_mecc = (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 == 4'h0) & (cor_result11_d1 == diff_ecc3_d1) ? 1'b1 : 1'b0;
wire byte9_err_mecc = (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 == 4'h0) & (cor_result12_d1 == diff_ecc3_d1) ? 1'b1 : 1'b0;
wire byte3_err_mecc = (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 == 4'h0) & (cor_result13_d1 == diff_ecc3_d1) ? 1'b1 : 1'b0;
wire byte2_err_mecc = (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 == 4'h0) & (cor_result14_d1 == diff_ecc3_d1) ? 1'b1 : 1'b0;
wire byte7_err_mecc = (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 == 4'h0) & (cor_result15_d1 == diff_ecc3_d1) ? 1'b1 : 1'b0;
wire [14:0] err_byte_0_14_loc = {byte14_err_mecc, byte13_err_mecc, byte12_err_mecc, byte11_err_mecc,
byte10_err_mecc, byte9_err_mecc, byte8_err_mecc, byte7_err_mecc,
byte6_err_mecc, byte5_err_mecc, byte4_err_mecc, byte3_err_mecc,
byte2_err_mecc, byte1_err_mecc, byte0_err_mecc};
// Correcting nibbles 15-29 - diff0/diff2
wire byte15_err = (diff_ecc2_d1 != 4'h0) & (diff_ecc1_d1 == 4'h0) & (diff_ecc2_d1 == diff_ecc0_d1) ? 1'b1 : 1'b0;
assign outbyte15 = inbyte15_d2 ^ (byte15_err ? diff_ecc2_d1 : 4'h0);
wire byte16_err = (diff_ecc2_d1 != 4'h0) & (diff_ecc1_d1 == 4'h0) & (cor_result17_d1 == diff_ecc0_d1) ? 1'b1 : 1'b0;
assign outbyte16 = inbyte16_d2 ^ (byte16_err ? diff_ecc2_d1 : 4'h0);
wire byte17_err = (diff_ecc2_d1 != 4'h0) & (diff_ecc1_d1 == 4'h0) & (cor_result18_d1 == diff_ecc0_d1) ? 1'b1 : 1'b0;
assign outbyte17 = inbyte17_d2 ^ (byte17_err ? diff_ecc2_d1 : 4'h0);
wire byte18_err = (diff_ecc2_d1 != 4'h0) & (diff_ecc1_d1 == 4'h0) & (cor_result19_d1 == diff_ecc0_d1) ? 1'b1 : 1'b0;
assign outbyte18 = inbyte18_d2 ^ (byte18_err ? diff_ecc2_d1 : 4'h0);
wire byte19_err = (diff_ecc2_d1 != 4'h0) & (diff_ecc1_d1 == 4'h0) & (cor_result20_d1 == diff_ecc0_d1) ? 1'b1 : 1'b0;
assign outbyte19 = inbyte19_d2 ^ (byte19_err ? diff_ecc2_d1 : 4'h0);
wire byte20_err = (diff_ecc2_d1 != 4'h0) & (diff_ecc1_d1 == 4'h0) & (cor_result21_d1 == diff_ecc0_d1) ? 1'b1 : 1'b0;
assign outbyte20 = inbyte20_d2 ^ (byte20_err ? diff_ecc2_d1 : 4'h0);
wire byte21_err = (diff_ecc2_d1 != 4'h0) & (diff_ecc1_d1 == 4'h0) & (cor_result22_d1 == diff_ecc0_d1) ? 1'b1 : 1'b0;
assign outbyte21 = inbyte21_d2 ^ (byte21_err ? diff_ecc2_d1 : 4'h0);
wire byte22_err = (diff_ecc2_d1 != 4'h0) & (diff_ecc1_d1 == 4'h0) & (cor_result23_d1 == diff_ecc0_d1) ? 1'b1 : 1'b0;
assign outbyte22 = inbyte22_d2 ^ (byte22_err ? diff_ecc2_d1 : 4'h0);
wire byte23_err = (diff_ecc2_d1 != 4'h0) & (diff_ecc1_d1 == 4'h0) & (cor_result24_d1 == diff_ecc0_d1) ? 1'b1 : 1'b0;
assign outbyte23 = inbyte23_d2 ^ (byte23_err ? diff_ecc2_d1 : 4'h0);
wire byte24_err = (diff_ecc2_d1 != 4'h0) & (diff_ecc1_d1 == 4'h0) & (cor_result25_d1 == diff_ecc0_d1) ? 1'b1 : 1'b0;
assign outbyte24 = inbyte24_d2 ^ (byte24_err ? diff_ecc2_d1 : 4'h0);
wire byte25_err = (diff_ecc2_d1 != 4'h0) & (diff_ecc1_d1 == 4'h0) & (cor_result26_d1 == diff_ecc0_d1) ? 1'b1 : 1'b0;
assign outbyte25 = inbyte25_d2 ^ (byte25_err ? diff_ecc2_d1 : 4'h0);
wire byte26_err = (diff_ecc2_d1 != 4'h0) & (diff_ecc1_d1 == 4'h0) & (cor_result27_d1 == diff_ecc0_d1) ? 1'b1 : 1'b0;
assign outbyte26 = inbyte26_d2 ^ (byte26_err ? diff_ecc2_d1 : 4'h0);
wire byte27_err = (diff_ecc2_d1 != 4'h0) & (diff_ecc1_d1 == 4'h0) & (cor_result28_d1 == diff_ecc0_d1) ? 1'b1 : 1'b0;
assign outbyte27 = inbyte27_d2 ^ (byte27_err ? diff_ecc2_d1 : 4'h0);
wire byte28_err = (diff_ecc2_d1 != 4'h0) & (diff_ecc1_d1 == 4'h0) & (cor_result29_d1 == diff_ecc0_d1) ? 1'b1 : 1'b0;
assign outbyte28 = inbyte28_d2 ^ (byte28_err ? diff_ecc2_d1 : 4'h0);
wire byte29_err = (diff_ecc2_d1 != 4'h0) & (diff_ecc1_d1 == 4'h0) & (cor_result30_d1 == diff_ecc0_d1) ? 1'b1 : 1'b0;
assign outbyte29 = inbyte29_d2 ^ (byte29_err ? diff_ecc2_d1 : 4'h0);
// Logic used for MECC detection - diff3/diff2
wire byte15_err_mecc = (diff_ecc2_d1 != 4'h0) & (diff_ecc1_d1 == 4'h0) & (diff_ecc2_d1 == diff_ecc3_d1) ? 1'b1 : 1'b0;
wire byte23_err_mecc = (diff_ecc2_d1 != 4'h0) & (diff_ecc1_d1 == 4'h0) & (cor_result2_d1 == diff_ecc3_d1) ? 1'b1 : 1'b0;
wire byte28_err_mecc = (diff_ecc2_d1 != 4'h0) & (diff_ecc1_d1 == 4'h0) & (cor_result3_d1 == diff_ecc3_d1) ? 1'b1 : 1'b0;
wire byte27_err_mecc = (diff_ecc2_d1 != 4'h0) & (diff_ecc1_d1 == 4'h0) & (cor_result4_d1 == diff_ecc3_d1) ? 1'b1 : 1'b0;
wire byte25_err_mecc = (diff_ecc2_d1 != 4'h0) & (diff_ecc1_d1 == 4'h0) & (cor_result5_d1 == diff_ecc3_d1) ? 1'b1 : 1'b0;
wire byte21_err_mecc = (diff_ecc2_d1 != 4'h0) & (diff_ecc1_d1 == 4'h0) & (cor_result6_d1 == diff_ecc3_d1) ? 1'b1 : 1'b0;
wire byte20_err_mecc = (diff_ecc2_d1 != 4'h0) & (diff_ecc1_d1 == 4'h0) & (cor_result7_d1 == diff_ecc3_d1) ? 1'b1 : 1'b0;
wire byte29_err_mecc = (diff_ecc2_d1 != 4'h0) & (diff_ecc1_d1 == 4'h0) & (cor_result8_d1 == diff_ecc3_d1) ? 1'b1 : 1'b0;
wire byte16_err_mecc = (diff_ecc2_d1 != 4'h0) & (diff_ecc1_d1 == 4'h0) & (cor_result9_d1 == diff_ecc3_d1) ? 1'b1 : 1'b0;
wire byte26_err_mecc = (diff_ecc2_d1 != 4'h0) & (diff_ecc1_d1 == 4'h0) & (cor_result10_d1 == diff_ecc3_d1) ? 1'b1 : 1'b0;
wire byte19_err_mecc = (diff_ecc2_d1 != 4'h0) & (diff_ecc1_d1 == 4'h0) & (cor_result11_d1 == diff_ecc3_d1) ? 1'b1 : 1'b0;
wire byte24_err_mecc = (diff_ecc2_d1 != 4'h0) & (diff_ecc1_d1 == 4'h0) & (cor_result12_d1 == diff_ecc3_d1) ? 1'b1 : 1'b0;
wire byte18_err_mecc = (diff_ecc2_d1 != 4'h0) & (diff_ecc1_d1 == 4'h0) & (cor_result13_d1 == diff_ecc3_d1) ? 1'b1 : 1'b0;
wire byte17_err_mecc = (diff_ecc2_d1 != 4'h0) & (diff_ecc1_d1 == 4'h0) & (cor_result14_d1 == diff_ecc3_d1) ? 1'b1 : 1'b0;
wire byte22_err_mecc = (diff_ecc2_d1 != 4'h0) & (diff_ecc1_d1 == 4'h0) & (cor_result15_d1 == diff_ecc3_d1) ? 1'b1 : 1'b0;
wire [14:0] err_byte_15_29_loc = {byte29_err_mecc, byte28_err_mecc, byte27_err_mecc, byte26_err_mecc,
byte25_err_mecc, byte24_err_mecc, byte23_err_mecc, byte22_err_mecc,
byte21_err_mecc, byte20_err_mecc, byte19_err_mecc, byte18_err_mecc,
byte17_err_mecc, byte16_err_mecc, byte15_err_mecc};
// Correcting nibbles 30-31
wire byte30_err = (diff_ecc0_d1 == 4'h0) & (diff_ecc1_d1 == diff_ecc2_d1) & (diff_ecc1_d1 != 4'h0) ?
1'b1 : 1'b0;
assign outbyte30 = inbyte30_d2 ^ (byte30_err ? diff_ecc2_d1 : 4'h0);
wire byte31_err = (diff_ecc0_d1 == diff_ecc1_d1) & (diff_ecc1_d1 == diff_ecc2_d1) & (diff_ecc0_d1 != 4'h0) ?
1'b1 : 1'b0;
assign outbyte31 = inbyte31_d2 ^ (byte31_err ? diff_ecc2_d1 : 4'h0);
// ecc location
assign ecc_loc[35:0] = {secc_err_d1[3:0], byte31_err, byte30_err, byte29_err, byte28_err, byte27_err, byte26_err,
byte25_err, byte24_err,
byte23_err, byte22_err, byte21_err, byte20_err, byte19_err, byte18_err, byte17_err,
byte16_err, byte15_err, byte14_err, byte13_err, byte12_err, byte11_err, byte10_err,
byte9_err, byte8_err, byte7_err, byte6_err, byte5_err, byte4_err, byte3_err,
byte2_err, byte1_err, byte0_err};
// Generate multi ecc error signal.
assign ecc_multi_err = ~l2if_dram_fail_over_mode & (
((diff_ecc0_d1 == 4'h0) & (diff_ecc1_d1 == 4'h0) & (diff_ecc2_d1 != 4'h0) & (diff_ecc3_d1 != 4'h0)) |
((diff_ecc0_d1 != 4'h0) & (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 == 4'h0) & (diff_ecc3_d1 == 4'h0)) |
((diff_ecc0_d1 != 4'h0) & (diff_ecc1_d1 == 4'h0) & (diff_ecc2_d1 != 4'h0) & (diff_ecc3_d1 == 4'h0)) |
((diff_ecc0_d1 != 4'h0) & (diff_ecc1_d1 == 4'h0) & (diff_ecc2_d1 == 4'h0) & (diff_ecc3_d1 != 4'h0)) |
((diff_ecc0_d1 == 4'h0) & (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 == 4'h0) & (diff_ecc3_d1 != 4'h0)) |
((diff_ecc0_d1 == 4'h0) & (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 != 4'h0) & (diff_ecc3_d1 == 4'h0)) |
((diff_ecc0_d1 != 4'h0) & (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 != 4'h0) & (diff_ecc3_d1 != 4'h0)) |
((diff_ecc0_d1 != 4'h0) & (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 == 4'h0) & (diff_ecc3_d1 != 4'h0) &
(ecc_loc[14:0] != err_byte_0_14_loc[14:0]) ) |
((diff_ecc0_d1 != 4'h0) & (diff_ecc1_d1 == 4'h0) & (diff_ecc2_d1 != 4'h0) & (diff_ecc3_d1 != 4'h0) &
(ecc_loc[29:15] != err_byte_15_29_loc[14:0]) ) |
((diff_ecc0_d1 != 4'h0) & (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 != 4'h0) & (diff_ecc3_d1 == 4'h0) &
((diff_ecc0_d1 != diff_ecc1_d1) | (diff_ecc1_d1 != diff_ecc2_d1)) ) |
((diff_ecc0_d1 == 4'h0) & (diff_ecc1_d1 != 4'h0) & (diff_ecc2_d1 != 4'h0) & (diff_ecc3_d1 != 4'h0) &
((diff_ecc1_d1 != diff_ecc2_d1) | (diff_ecc2_d1 != diff_ecc3_d1)) ));
// Generate single ecc error signal.
wire secc_err31 = (diff_ecc0_d1 != 4'h0) & ( (diff_ecc2_d1 == diff_ecc1_d1) & (diff_ecc2_d1 == diff_ecc0_d1) );
wire secc_err30 = (diff_ecc1_d1 != 4'h0) & ( (diff_ecc1_d1 == diff_ecc2_d1) & (diff_ecc0_d1 == 4'h0) );
wire secc_err_lo = (diff_ecc1_d1 != 4'h0) & (diff_ecc0_d1 != 4'h0) & (diff_ecc2_d1 == 4'h0);
wire secc_err_hi = (diff_ecc2_d1 != 4'h0) & (diff_ecc0_d1 != 4'h0) & (diff_ecc1_d1 == 4'h0);
assign ecc_single_err = ~ecc_multi_err & ((secc_err31 | secc_err30 | secc_err_hi | secc_err_lo) | (|secc_err_d1));
// Corrected data
assign fixed_data[127:0] = {outbyte31, outbyte30, outbyte29, outbyte28, outbyte27, outbyte26,
outbyte25, outbyte24, outbyte23, outbyte22, outbyte21,
outbyte20, outbyte19, outbyte18, outbyte17, outbyte16,
outbyte15, outbyte14, outbyte13, outbyte12, outbyte11,
outbyte10, outbyte9, outbyte8, outbyte7, outbyte6,
outbyte5, outbyte4, outbyte3, outbyte2, outbyte1, outbyte0};
assign cor_data[127:0] = ecc_multi_err ?
({inbyte31_d2, inbyte30_d2, inbyte29_d2, inbyte28_d2, inbyte27_d2, inbyte26_d2,
inbyte25_d2, inbyte24_d2, inbyte23_d2, inbyte22_d2, inbyte21_d2,
inbyte20_d2, inbyte19_d2, inbyte18_d2, inbyte17_d2, inbyte16_d2,
inbyte15_d2, inbyte14_d2, inbyte13_d2, inbyte12_d2, inbyte11_d2,
inbyte10_d2, inbyte9_d2, inbyte8_d2, inbyte7_d2, inbyte6_d2,
inbyte5_d2, inbyte4_d2, inbyte3_d2, inbyte2_d2, inbyte1_d2, inbyte0_d2 }) : fixed_data;
endmodule // ecc
|
module ex_mem(clk,s7_idex, dmem_wen_idex, rf_wen_idex, branch2_idex,
mem2reg_idex,aluout, flag, extended_16_idex, rdata2_idex, rf_waddr, dmem_wen_exmem,
rf_wen_exmem, branch2_exmem, mem2reg_exmem, aluout_exmem, flag_exmem,
rdata2_exmem, rf_waddr_exmem, extended_exmem, s7_exmem, branch_target_final_muxout, branch_target_exmem,
nop_lw_idex,nop_sw_idex, nop_lw_exmem, nop_sw_exmem,
pc_added_idex, pc_added_exmem,
jal_idex, jal_exmem
);
input clk;
input s7_idex;
input dmem_wen_idex;
input rf_wen_idex;
input mem2reg_idex;
input branch2_idex;
input [15:0] aluout;
input [2:0] flag;
input [15:0] extended_16_idex;
input [15:0] rdata2_idex;
input [3:0] rf_waddr;
input [15:0] pc_added_idex;
input jal_idex;
input nop_lw_idex, nop_sw_idex;
output nop_lw_exmem, nop_sw_exmem;
input [15:0] branch_target_final_muxout;
output [15:0] branch_target_exmem;
output dmem_wen_exmem;
output rf_wen_exmem;
output branch2_exmem;
output mem2reg_exmem;
output s7_exmem;
output [15:0] extended_exmem;
output [15:0] pc_added_exmem;
output jal_exmem;
reg dmem_wen_exmem_temp;
reg rf_wen_exmem_temp;
reg branch2_exmem_temp;
reg mem2reg_exmem_temp;
reg s7_exmem_temp;
reg [15:0] extended_exmem_temp;
reg [15:0] pc_added_temp;
reg jal_temp;
output [15:0] aluout_exmem;
output [2:0] flag_exmem;
output [15:0] rdata2_exmem;
output [3:0] rf_waddr_exmem;
reg nop_lw_temp, nop_sw_temp;
//output reg control_lhb_llb_exmem;
reg [15:0] aluout_exmem_temp;
reg [2:0] flag_exmem_temp;
reg [15:0] rdata2_exmem_temp;
reg [3:0] rf_waddr_exmem_temp;
reg [15:0] branch_target_temp;
always @ (posedge clk)
begin
dmem_wen_exmem_temp <= dmem_wen_idex;
rf_wen_exmem_temp <= rf_wen_idex;
branch2_exmem_temp <= branch2_idex;
mem2reg_exmem_temp <= mem2reg_idex;
aluout_exmem_temp <=aluout;
flag_exmem_temp <= flag;
rdata2_exmem_temp <= rdata2_idex;
rf_waddr_exmem_temp <= rf_waddr;
s7_exmem_temp <= s7_idex;
extended_exmem_temp <= extended_16_idex;
branch_target_temp<= branch_target_final_muxout;
nop_lw_temp <= nop_lw_idex;
nop_sw_temp <= nop_sw_idex;
pc_added_temp <= pc_added_idex;
jal_temp <= jal_idex;
end
assign dmem_wen_exmem = dmem_wen_exmem_temp;
assign rf_wen_exmem = rf_wen_exmem_temp;
assign branch2_exmem = branch2_exmem_temp;
assign mem2reg_exmem = mem2reg_exmem_temp;
assign aluout_exmem = aluout_exmem_temp;
assign flag_exmem = flag_exmem_temp;
assign rdata2_exmem = rdata2_exmem_temp;
assign rf_waddr_exmem = rf_waddr_exmem_temp;
assign s7_exmem = s7_exmem_temp;
assign extended_exmem = extended_exmem_temp;
assign branch_target_exmem = branch_target_temp;
assign nop_lw_exmem = nop_lw_temp;
assign nop_sw_exmem = nop_sw_temp;
assign pc_added_exmem = pc_added_temp;
assign jal_exmem = jal_temp;
endmodule
|
/***************************************************************************************************
** fpga_nes/hw/src/cpu/apu/apu_pulse.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* APU noise channel.
***************************************************************************************************/
`timescale 1ps / 1ps
module apu_pulse
#(
parameter [0:0] CHANNEL = 1'b0 // Pulse channel 0 or 1
)
(
input wire clk_in, // system clock signal
input wire rst_in, // reset signal
input wire en_in, // enable (via $4015)
input wire cpu_cycle_pulse_in, // 1 clk pulse on every cpu cycle
input wire lc_pulse_in, // 1 clk pulse for every length counter decrement
input wire eg_pulse_in, // 1 clk pulse for every env gen update
input wire [1:0] a_in, // control register addr (i.e. $400C - $400F)
input wire [7:0] d_in, // control register write value
input wire wr_in, // enable control register write
output wire [3:0] pulse_out, // pulse channel output
output wire active_out // pulse channel active (length counter > 0)
);
//
// Envelope
//
wire envelope_generator_wr;
wire envelope_generator_restart;
wire [3:0] envelope_generator_out;
apu_envelope_generator envelope_generator(
.clk_in(clk_in),
.rst_in(rst_in),
.eg_pulse_in(eg_pulse_in),
.env_in(d_in[5:0]),
.env_wr_in(envelope_generator_wr),
.env_restart(envelope_generator_restart),
.env_out(envelope_generator_out)
);
assign envelope_generator_wr = wr_in && (a_in == 2'b00);
assign envelope_generator_restart = wr_in && (a_in == 2'b11);
//
// Timer
//
reg [10:0] q_timer_period, d_timer_period;
wire timer_pulse;
always @(posedge clk_in)
begin
if (rst_in)
q_timer_period <= 11'h000;
else
q_timer_period <= d_timer_period;
end
apu_div #(.PERIOD_BITS(12)) timer(
.clk_in(clk_in),
.rst_in(rst_in),
.pulse_in(cpu_cycle_pulse_in),
.reload_in(1'b0),
.period_in({ q_timer_period, 1'b0 }),
.pulse_out(timer_pulse)
);
//
// Sequencer
//
wire [3:0] sequencer_out;
reg [1:0] q_duty;
wire [1:0] d_duty;
reg [2:0] q_sequencer_cnt;
wire [2:0] d_sequencer_cnt;
wire seq_bit;
always @(posedge clk_in)
begin
if (rst_in)
begin
q_duty <= 2'h0;
q_sequencer_cnt <= 3'h0;
end
else
begin
q_duty <= d_duty;
q_sequencer_cnt <= d_sequencer_cnt;
end
end
assign d_duty = (wr_in && (a_in == 2'b00)) ? d_in[7:6] : q_duty;
assign d_sequencer_cnt = (timer_pulse) ? q_sequencer_cnt - 3'h1 : q_sequencer_cnt;
assign seq_bit = (q_duty == 2'h0) ? &q_sequencer_cnt[2:0] :
(q_duty == 2'h1) ? &q_sequencer_cnt[2:1] :
(q_duty == 2'h2) ? q_sequencer_cnt[2] : ~&q_sequencer_cnt[2:1];
assign sequencer_out = (seq_bit) ? envelope_generator_out : 4'h0;
//
// Sweep
//
reg q_sweep_reload;
wire d_sweep_reload;
reg [7:0] q_sweep_reg;
wire [7:0] d_sweep_reg;
always @(posedge clk_in)
begin
if (rst_in)
begin
q_sweep_reg <= 8'h00;
q_sweep_reload <= 1'b0;
end
else
begin
q_sweep_reg <= d_sweep_reg;
q_sweep_reload <= d_sweep_reload;
end
end
assign d_sweep_reg = (wr_in && (a_in == 2'b01)) ? d_in : q_sweep_reg;
assign d_sweep_reload = (wr_in && (a_in == 2'b01)) ? 1'b1 :
(lc_pulse_in) ? 1'b0 : q_sweep_reload;
wire sweep_divider_reload;
wire sweep_divider_pulse;
reg sweep_silence;
reg [11:0] sweep_target_period;
apu_div #(.PERIOD_BITS(3)) sweep_divider(
.clk_in(clk_in),
.rst_in(rst_in),
.pulse_in(lc_pulse_in),
.reload_in(sweep_divider_reload),
.period_in(q_sweep_reg[6:4]),
.pulse_out(sweep_divider_pulse)
);
assign sweep_divider_reload = lc_pulse_in & q_sweep_reload;
always @*
begin
sweep_target_period =
(!q_sweep_reg[3]) ? q_timer_period + (q_timer_period >> q_sweep_reg[2:0]) :
q_timer_period + ~(q_timer_period >> q_sweep_reg[2:0]) + CHANNEL;
sweep_silence = (q_timer_period[10:3] == 8'h00) || sweep_target_period[11];
if (wr_in && (a_in == 2'b10))
d_timer_period = { q_timer_period[10:8], d_in };
else if (wr_in && (a_in == 2'b11))
d_timer_period = { d_in[2:0], q_timer_period[7:0] };
else if (sweep_divider_pulse && q_sweep_reg[7] && !sweep_silence && (q_sweep_reg[2:0] != 3'h0))
d_timer_period = sweep_target_period[10:0];
else
d_timer_period = q_timer_period;
end
//
// Length Counter
//
reg q_length_counter_halt;
wire d_length_counter_halt;
always @(posedge clk_in)
begin
if (rst_in)
begin
q_length_counter_halt <= 1'b0;
end
else
begin
q_length_counter_halt <= d_length_counter_halt;
end
end
assign d_length_counter_halt = (wr_in && (a_in == 2'b00)) ? d_in[5] : q_length_counter_halt;
wire length_counter_wr;
wire length_counter_en;
apu_length_counter length_counter(
.clk_in(clk_in),
.rst_in(rst_in),
.en_in(en_in),
.halt_in(q_length_counter_halt),
.length_pulse_in(lc_pulse_in),
.length_in(d_in[7:3]),
.length_wr_in(length_counter_wr),
.en_out(length_counter_en)
);
assign length_counter_wr = wr_in && (a_in == 2'b11);
assign pulse_out = (length_counter_en && !sweep_silence) ? sequencer_out : 4'h0;
assign active_out = length_counter_en;
endmodule
|
//---------------------------------------------------------------------------
//-- (c) 2016 Alexey Spirkov
//-- I am happy for anyone to use this for non-commercial use.
//-- If my verilog/vhdl/c files are used commercially or otherwise sold,
//-- please contact me for explicit permission at me _at_ alsp.net.
//-- This applies for source and binary form and derived works.
//
//-- Audio and infoframe packet generation mechanizms based on Charlie Cole 2015
//-- design of HDMI output for Neo Geo MVS
module hdmidataencoder
#(parameter FREQ, FS, CTS, N)
(
input i_pixclk,
input i_hSync,
input i_vSync,
input i_blank,
input [15:0] i_audioL,
input [15:0] i_audioR,
output [3:0] o_d0,
output [3:0] o_d1,
output [3:0] o_d2,
output o_data
);
`define AUDIO_TIMER_ADDITION FS/1000
`define AUDIO_TIMER_LIMIT FREQ/1000
localparam [191:0] channelStatus = (FS == 48000)?192'hc202004004:(FS == 44100)?192'hc200004004:192'hc203004004;
localparam [55:0] audioRegenPacket = {N[7:0], N[15:8], 8'h00, CTS[7:0], CTS[15:8], 16'h0000};
reg [23:0] audioPacketHeader;
reg [55:0] audioSubPacket[3:0];
reg [7:0] channelStatusIdx;
reg [16:0] audioTimer;
reg [16:0] ctsTimer;
reg [1:0] samplesHead;
reg [3:0] dataChannel0;
reg [3:0] dataChannel1;
reg [3:0] dataChannel2;
reg [23:0] packetHeader;
reg [55:0] subpacket[3:0];
reg [7:0] bchHdr;
reg [7:0] bchCode [3:0];
reg [4:0] dataOffset;
reg tercData;
reg [25:0] audioRAvgSum;
reg [25:0] audioLAvgSum;
reg [15:0] audioRAvg;
reg [15:0] audioLAvg;
reg [10:0] audioAvgCnt;
reg [15:0] counterX;
reg firstHSyncChange;
reg oddLine;
reg prevHSync;
reg prevBlank;
reg allowGeneration;
initial
begin
audioPacketHeader=0;
audioSubPacket[0]=0;
audioSubPacket[1]=0;
audioSubPacket[2]=0;
audioSubPacket[3]=0;
channelStatusIdx=0;
audioTimer=0;
samplesHead=0;
ctsTimer = 0;
dataChannel0=0;
dataChannel1=0;
dataChannel2=0;
packetHeader=0;
subpacket[0]=0;
subpacket[1]=0;
subpacket[2]=0;
subpacket[3]=0;
bchHdr=0;
bchCode[0]=0;
bchCode[1]=0;
bchCode[2]=0;
bchCode[3]=0;
dataOffset=0;
tercData=0;
oddLine=0;
counterX=0;
prevHSync = 0;
prevBlank = 0;
firstHSyncChange = 0;
allowGeneration = 0;
audioRAvg = 0;
audioLAvg = 0;
audioRAvgSum = 0;
audioLAvgSum = 0;
audioAvgCnt = 1;
end
function [7:0] ECCcode; // Cycles the error code generator
input [7:0] code;
input bita;
input passthroughData;
begin
ECCcode = (code<<1) ^ (((code[7]^bita) && passthroughData)?(1+(1<<6)+(1<<7)):0);
end
endfunction
task ECCu;
output outbit;
inout [7:0] code;
input bita;
input passthroughData;
begin
outbit <= passthroughData?bita:code[7];
code <= ECCcode(code, bita, passthroughData);
end
endtask
task ECC2u;
output outbita;
output outbitb;
inout [7:0] code;
input bita;
input bitb;
input passthroughData;
begin
outbita <= passthroughData?bita:code[7];
outbitb <= passthroughData?bitb:(code[6]^(((code[7]^bita) && passthroughData)?1'b1:1'b0));
code <= ECCcode(ECCcode(code, bita, passthroughData), bitb, passthroughData);
end
endtask
task SendPacket;
inout [32:0] pckHeader;
inout [55:0] pckData0;
inout [55:0] pckData1;
inout [55:0] pckData2;
inout [55:0] pckData3;
input firstPacket;
begin
dataChannel0[0]=i_hSync;
dataChannel0[1]=i_vSync;
dataChannel0[3]=(!firstPacket || dataOffset)?1'b1:1'b0;
ECCu(dataChannel0[2], bchHdr, pckHeader[0], dataOffset<24?1'b1:1'b0);
ECC2u(dataChannel1[0], dataChannel2[0], bchCode[0], pckData0[0], pckData0[1], dataOffset<28?1'b1:1'b0);
ECC2u(dataChannel1[1], dataChannel2[1], bchCode[1], pckData1[0], pckData1[1], dataOffset<28?1'b1:1'b0);
ECC2u(dataChannel1[2], dataChannel2[2], bchCode[2], pckData2[0], pckData2[1], dataOffset<28?1'b1:1'b0);
ECC2u(dataChannel1[3], dataChannel2[3], bchCode[3], pckData3[0], pckData3[1], dataOffset<28?1'b1:1'b0);
pckHeader<=pckHeader[23:1];
pckData0<=pckData0[55:2];
pckData1<=pckData1[55:2];
pckData2<=pckData2[55:2];
pckData3<=pckData3[55:2];
dataOffset<=dataOffset+5'b1;
end
endtask
task InfoGen;
inout [16:0] _timer;
begin
if (_timer >= CTS) begin
packetHeader<=24'h000001; // audio clock regeneration packet
subpacket[0]<=audioRegenPacket;
subpacket[1]<=audioRegenPacket;
subpacket[2]<=audioRegenPacket;
subpacket[3]<=audioRegenPacket;
_timer <= _timer - CTS + 1;
end else begin
if (!oddLine) begin
packetHeader<=24'h0D0282; // infoframe AVI packet
// Byte0: Checksum (256-(S%256))%256
// Byte1: 10 = 0(Y1:Y0=0 RGB)(A0=1 active format valid)(B1:B0=00 No bar info)(S1:S0=00 No scan info)
// Byte2: 19 = (C1:C0=0 No colorimetry)(M1:M0=1 4:3)(R3:R0=9 4:3 center)
// Byte3: 00 = 0(SC1:SC0=0 No scaling)
// Byte4: 00 = 0(VIC6:VIC0=0 custom resolution)
// Byte5: 00 = 0(PR5:PR0=0 No repeation)
subpacket[0]<=56'h00000000191046;
subpacket[1]<=56'h00000000000000;
end else begin
packetHeader<=24'h0A0184; // infoframe audio packet
// Byte0: Checksum (256-(S%256))%256
// Byte1: 11 = (CT3:0=1 PCM)0(CC2:0=1 2ch)
// Byte2: 00 = 000(SF2:0=0 As stream)(SS1:0=0 As stream)
// Byte3: 00 = LPCM doesn't use this
// Byte4-5: 00 Multichannel only (>2ch)
subpacket[0]<=56'h00000000001160;
subpacket[1]<=56'h00000000000000;
end
subpacket[2]<=56'h00000000000000;
subpacket[3]<=56'h00000000000000;
end
end
endtask
task AproximateAudio;
begin
audioLAvgSum <= audioLAvgSum + i_audioL;
audioRAvgSum <= audioRAvgSum + i_audioR;
audioLAvg <= audioLAvgSum/audioAvgCnt;
audioRAvg <= audioRAvgSum/audioAvgCnt;
audioAvgCnt <= audioAvgCnt + 1;
end
endtask
task AudioGen;
begin
// Buffer up an audio sample
// Don't add to the audio output if we're currently sending that packet though
if (!( allowGeneration && counterX >= 32 && counterX < 64)) begin
if (audioTimer>=`AUDIO_TIMER_LIMIT) begin
audioTimer<=audioTimer-`AUDIO_TIMER_LIMIT+`AUDIO_TIMER_ADDITION;
audioPacketHeader<=audioPacketHeader|24'h000002|((channelStatusIdx==0?24'h100100:24'h000100)<<samplesHead);
audioSubPacket[samplesHead]<=((audioLAvg<<8)|(audioRAvg<<32)
|((^audioLAvg)?56'h08000000000000:56'h0) // parity bit for left channel
|((^audioRAvg)?56'h80000000000000:56'h0)) // parity bit for right channel
^(channelStatus[channelStatusIdx]?56'hCC000000000000:56'h0); // And channel status bit and adjust parity
if (channelStatusIdx<191)
channelStatusIdx<=channelStatusIdx+8'd1;
else
channelStatusIdx<=0;
samplesHead<=samplesHead+2'd1;
audioLAvgSum <= 0;
audioRAvgSum <= 0;
audioAvgCnt <= 1;
end else begin
audioTimer<=audioTimer+`AUDIO_TIMER_ADDITION;
AproximateAudio();
end
end else begin
audioTimer<=audioTimer+`AUDIO_TIMER_ADDITION;
AproximateAudio();
samplesHead<=0;
end
end
endtask
task SendPackets;
inout dataEnable;
begin
if (counterX<32) begin
// Send first data packet (Infoframe or audio clock regen)
dataEnable<=1;
SendPacket(packetHeader, subpacket[0], subpacket[1], subpacket[2], subpacket[3], 1);
end else if (counterX<64) begin
// Send second data packet (audio data)
SendPacket(audioPacketHeader, audioSubPacket[0], audioSubPacket[1], audioSubPacket[2], audioSubPacket[3], 0);
end else begin
dataEnable<=0;
end
end
endtask
always @(posedge i_pixclk)
begin
AudioGen();
// Send 2 packets each line
if(allowGeneration) begin
SendPackets(tercData);
end else begin
tercData<=0;
end
ctsTimer <= ctsTimer + 1;
if((prevBlank == 0) && (i_blank == 1))
firstHSyncChange <= 1;
if((prevBlank == 1) && (i_blank == 0))
allowGeneration <= 0;
if(prevHSync != i_hSync) begin
if(firstHSyncChange) begin
InfoGen(ctsTimer);
oddLine <= ! oddLine;
counterX <= 0;
allowGeneration <= 1;
end else begin
counterX <= counterX + 1;
end
firstHSyncChange <= !firstHSyncChange;
end else
counterX <= counterX + 1;
prevBlank <= i_blank;
prevHSync <= i_hSync;
end
assign o_d0 = dataChannel0;
assign o_d1 = dataChannel1;
assign o_d2 = dataChannel2;
assign o_data = tercData;
endmodule |
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2019 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
Require Import ZAxioms ZMulOrder ZSgnAbs NZDiv.
(** * Euclidean Division for integers (Trunc convention)
We use here the convention known as Trunc, or Round-Toward-Zero,
where [a/b] is the integer with the largest absolute value to
be between zero and the exact fraction. It can be summarized by:
[a = bq+r /\ 0 <= |r| < |b| /\ Sign(r) = Sign(a)]
This is the convention of Ocaml and many other systems (C, ASM, ...).
This convention is named "T" in the following paper:
R. Boute, "The Euclidean definition of the functions div and mod",
ACM Transactions on Programming Languages and Systems,
Vol. 14, No.2, pp. 127-144, April 1992.
See files [ZDivFloor] and [ZDivEucl] for others conventions.
*)
Module Type ZQuotProp
(Import A : ZAxiomsSig')
(Import B : ZMulOrderProp A)
(Import C : ZSgnAbsProp A B).
(** We benefit from what already exists for NZ *)
Module Import Private_Div.
Module Quot2Div <: NZDiv A.
Definition div := quot.
Definition modulo := A.rem.
Definition div_wd := quot_wd.
Definition mod_wd := rem_wd.
Definition div_mod := quot_rem.
Definition mod_bound_pos := rem_bound_pos.
End Quot2Div.
Module NZQuot := Nop <+ NZDivProp A Quot2Div B.
End Private_Div.
Ltac pos_or_neg a :=
let LT := fresh "LT" in
let LE := fresh "LE" in
destruct (le_gt_cases 0 a) as [LE|LT]; [|rewrite <- opp_pos_neg in LT].
(** Another formulation of the main equation *)
Lemma rem_eq :
forall a b, b~=0 -> a rem b == a - b*(a÷b).
Proof.
intros.
rewrite <- add_move_l.
symmetry. now apply quot_rem.
Qed.
(** A few sign rules (simple ones) *)
Lemma rem_opp_opp : forall a b, b ~= 0 -> (-a) rem (-b) == - (a rem b).
Proof. intros. now rewrite rem_opp_r, rem_opp_l. Qed.
Lemma quot_opp_l : forall a b, b ~= 0 -> (-a)÷b == -(a÷b).
Proof.
intros.
rewrite <- (mul_cancel_l _ _ b) by trivial.
rewrite <- (add_cancel_r _ _ ((-a) rem b)).
now rewrite <- quot_rem, rem_opp_l, mul_opp_r, <- opp_add_distr, <- quot_rem.
Qed.
Lemma quot_opp_r : forall a b, b ~= 0 -> a÷(-b) == -(a÷b).
Proof.
intros.
assert (-b ~= 0) by (now rewrite eq_opp_l, opp_0).
rewrite <- (mul_cancel_l _ _ (-b)) by trivial.
rewrite <- (add_cancel_r _ _ (a rem (-b))).
now rewrite <- quot_rem, rem_opp_r, mul_opp_opp, <- quot_rem.
Qed.
Lemma quot_opp_opp : forall a b, b ~= 0 -> (-a)÷(-b) == a÷b.
Proof. intros. now rewrite quot_opp_r, quot_opp_l, opp_involutive. Qed.
(** Uniqueness theorems *)
Theorem quot_rem_unique : forall b q1 q2 r1 r2 : t,
(0<=r1<b \/ b<r1<=0) -> (0<=r2<b \/ b<r2<=0) ->
b*q1+r1 == b*q2+r2 -> q1 == q2 /\ r1 == r2.
Proof.
intros b q1 q2 r1 r2 Hr1 Hr2 EQ.
destruct Hr1; destruct Hr2; try (intuition; order).
apply NZQuot.div_mod_unique with b; trivial.
rewrite <- (opp_inj_wd r1 r2).
apply NZQuot.div_mod_unique with (-b); trivial.
rewrite <- opp_lt_mono, opp_nonneg_nonpos; tauto.
rewrite <- opp_lt_mono, opp_nonneg_nonpos; tauto.
now rewrite 2 mul_opp_l, <- 2 opp_add_distr, opp_inj_wd.
Qed.
Theorem quot_unique:
forall a b q r, 0<=a -> 0<=r<b -> a == b*q + r -> q == a÷b.
Proof. intros; now apply NZQuot.div_unique with r. Qed.
Theorem rem_unique:
forall a b q r, 0<=a -> 0<=r<b -> a == b*q + r -> r == a rem b.
Proof. intros; now apply NZQuot.mod_unique with q. Qed.
(** A division by itself returns 1 *)
Lemma quot_same : forall a, a~=0 -> a÷a == 1.
Proof.
intros. pos_or_neg a. apply NZQuot.div_same; order.
rewrite <- quot_opp_opp by trivial. now apply NZQuot.div_same.
Qed.
Lemma rem_same : forall a, a~=0 -> a rem a == 0.
Proof.
intros. rewrite rem_eq, quot_same by trivial. nzsimpl. apply sub_diag.
Qed.
(** A division of a small number by a bigger one yields zero. *)
Theorem quot_small: forall a b, 0<=a<b -> a÷b == 0.
Proof. exact NZQuot.div_small. Qed.
(** Same situation, in term of remulo: *)
Theorem rem_small: forall a b, 0<=a<b -> a rem b == a.
Proof. exact NZQuot.mod_small. Qed.
(** * Basic values of divisions and modulo. *)
Lemma quot_0_l: forall a, a~=0 -> 0÷a == 0.
Proof.
intros. pos_or_neg a. apply NZQuot.div_0_l; order.
rewrite <- quot_opp_opp, opp_0 by trivial. now apply NZQuot.div_0_l.
Qed.
Lemma rem_0_l: forall a, a~=0 -> 0 rem a == 0.
Proof.
intros; rewrite rem_eq, quot_0_l; now nzsimpl.
Qed.
Lemma quot_1_r: forall a, a÷1 == a.
Proof.
intros. pos_or_neg a. now apply NZQuot.div_1_r.
apply opp_inj. rewrite <- quot_opp_l. apply NZQuot.div_1_r; order.
intro EQ; symmetry in EQ; revert EQ; apply lt_neq, lt_0_1.
Qed.
Lemma rem_1_r: forall a, a rem 1 == 0.
Proof.
intros. rewrite rem_eq, quot_1_r; nzsimpl; auto using sub_diag.
intro EQ; symmetry in EQ; revert EQ; apply lt_neq; apply lt_0_1.
Qed.
Lemma quot_1_l: forall a, 1<a -> 1÷a == 0.
Proof. exact NZQuot.div_1_l. Qed.
Lemma rem_1_l: forall a, 1<a -> 1 rem a == 1.
Proof. exact NZQuot.mod_1_l. Qed.
Lemma quot_mul : forall a b, b~=0 -> (a*b)÷b == a.
Proof.
intros. pos_or_neg a; pos_or_neg b. apply NZQuot.div_mul; order.
rewrite <- quot_opp_opp, <- mul_opp_r by order. apply NZQuot.div_mul; order.
rewrite <- opp_inj_wd, <- quot_opp_l, <- mul_opp_l by order.
apply NZQuot.div_mul; order.
rewrite <- opp_inj_wd, <- quot_opp_r, <- mul_opp_opp by order.
apply NZQuot.div_mul; order.
Qed.
Lemma rem_mul : forall a b, b~=0 -> (a*b) rem b == 0.
Proof.
intros. rewrite rem_eq, quot_mul by trivial. rewrite mul_comm; apply sub_diag.
Qed.
Theorem quot_unique_exact a b q: b~=0 -> a == b*q -> q == a÷b.
Proof.
intros Hb H. rewrite H, mul_comm. symmetry. now apply quot_mul.
Qed.
(** The sign of [a rem b] is the one of [a] (when it's not null) *)
Lemma rem_nonneg : forall a b, b~=0 -> 0 <= a -> 0 <= a rem b.
Proof.
intros. pos_or_neg b. destruct (rem_bound_pos a b); order.
rewrite <- rem_opp_r; trivial.
destruct (rem_bound_pos a (-b)); trivial.
Qed.
Lemma rem_nonpos : forall a b, b~=0 -> a <= 0 -> a rem b <= 0.
Proof.
intros a b Hb Ha.
apply opp_nonneg_nonpos. apply opp_nonneg_nonpos in Ha.
rewrite <- rem_opp_l by trivial. now apply rem_nonneg.
Qed.
Lemma rem_sign_mul : forall a b, b~=0 -> 0 <= (a rem b) * a.
Proof.
intros a b Hb. destruct (le_ge_cases 0 a).
apply mul_nonneg_nonneg; trivial. now apply rem_nonneg.
apply mul_nonpos_nonpos; trivial. now apply rem_nonpos.
Qed.
Lemma rem_sign_nz : forall a b, b~=0 -> a rem b ~= 0 ->
sgn (a rem b) == sgn a.
Proof.
intros a b Hb H. destruct (lt_trichotomy 0 a) as [LT|[EQ|LT]].
rewrite 2 sgn_pos; try easy.
generalize (rem_nonneg a b Hb (lt_le_incl _ _ LT)). order.
now rewrite <- EQ, rem_0_l, sgn_0.
rewrite 2 sgn_neg; try easy.
generalize (rem_nonpos a b Hb (lt_le_incl _ _ LT)). order.
Qed.
Lemma rem_sign : forall a b, a~=0 -> b~=0 -> sgn (a rem b) ~= -sgn a.
Proof.
intros a b Ha Hb H.
destruct (eq_decidable (a rem b) 0) as [EQ|NEQ].
apply Ha, sgn_null_iff, opp_inj. now rewrite <- H, opp_0, EQ, sgn_0.
apply Ha, sgn_null_iff. apply eq_mul_0_l with 2; try order'. nzsimpl'.
apply add_move_0_l. rewrite <- H. symmetry. now apply rem_sign_nz.
Qed.
(** Operations and absolute value *)
Lemma rem_abs_l : forall a b, b ~= 0 -> (abs a) rem b == abs (a rem b).
Proof.
intros a b Hb. destruct (le_ge_cases 0 a) as [LE|LE].
rewrite 2 abs_eq; try easy. now apply rem_nonneg.
rewrite 2 abs_neq, rem_opp_l; try easy. now apply rem_nonpos.
Qed.
Lemma rem_abs_r : forall a b, b ~= 0 -> a rem (abs b) == a rem b.
Proof.
intros a b Hb. destruct (le_ge_cases 0 b).
now rewrite abs_eq. now rewrite abs_neq, ?rem_opp_r.
Qed.
Lemma rem_abs : forall a b, b ~= 0 -> (abs a) rem (abs b) == abs (a rem b).
Proof.
intros. now rewrite rem_abs_r, rem_abs_l.
Qed.
Lemma quot_abs_l : forall a b, b ~= 0 -> (abs a)÷b == (sgn a)*(a÷b).
Proof.
intros a b Hb. destruct (lt_trichotomy 0 a) as [LT|[EQ|LT]].
rewrite abs_eq, sgn_pos by order. now nzsimpl.
rewrite <- EQ, abs_0, quot_0_l; trivial. now nzsimpl.
rewrite abs_neq, quot_opp_l, sgn_neg by order.
rewrite mul_opp_l. now nzsimpl.
Qed.
Lemma quot_abs_r : forall a b, b ~= 0 -> a÷(abs b) == (sgn b)*(a÷b).
Proof.
intros a b Hb. destruct (lt_trichotomy 0 b) as [LT|[EQ|LT]].
rewrite abs_eq, sgn_pos by order. now nzsimpl.
order.
rewrite abs_neq, quot_opp_r, sgn_neg by order.
rewrite mul_opp_l. now nzsimpl.
Qed.
Lemma quot_abs : forall a b, b ~= 0 -> (abs a)÷(abs b) == abs (a÷b).
Proof.
intros a b Hb.
pos_or_neg a; [rewrite (abs_eq a)|rewrite (abs_neq a)];
try apply opp_nonneg_nonpos; try order.
pos_or_neg b; [rewrite (abs_eq b)|rewrite (abs_neq b)];
try apply opp_nonneg_nonpos; try order.
rewrite abs_eq; try easy. apply NZQuot.div_pos; order.
rewrite <- abs_opp, <- quot_opp_r, abs_eq; try easy.
apply NZQuot.div_pos; order.
pos_or_neg b; [rewrite (abs_eq b)|rewrite (abs_neq b)];
try apply opp_nonneg_nonpos; try order.
rewrite <- (abs_opp (_÷_)), <- quot_opp_l, abs_eq; try easy.
apply NZQuot.div_pos; order.
rewrite <- (quot_opp_opp a b), abs_eq; try easy.
apply NZQuot.div_pos; order.
Qed.
(** We have a general bound for absolute values *)
Lemma rem_bound_abs :
forall a b, b~=0 -> abs (a rem b) < abs b.
Proof.
intros. rewrite <- rem_abs; trivial.
apply rem_bound_pos. apply abs_nonneg. now apply abs_pos.
Qed.
(** * Order results about rem and quot *)
(** A modulo cannot grow beyond its starting point. *)
Theorem rem_le: forall a b, 0<=a -> 0<b -> a rem b <= a.
Proof. exact NZQuot.mod_le. Qed.
Theorem quot_pos : forall a b, 0<=a -> 0<b -> 0<= a÷b.
Proof. exact NZQuot.div_pos. Qed.
Lemma quot_str_pos : forall a b, 0<b<=a -> 0 < a÷b.
Proof. exact NZQuot.div_str_pos. Qed.
Lemma quot_small_iff : forall a b, b~=0 -> (a÷b==0 <-> abs a < abs b).
Proof.
intros. pos_or_neg a; pos_or_neg b.
rewrite NZQuot.div_small_iff; try order. rewrite 2 abs_eq; intuition; order.
rewrite <- opp_inj_wd, opp_0, <- quot_opp_r, NZQuot.div_small_iff by order.
rewrite (abs_eq a), (abs_neq' b); intuition; order.
rewrite <- opp_inj_wd, opp_0, <- quot_opp_l, NZQuot.div_small_iff by order.
rewrite (abs_neq' a), (abs_eq b); intuition; order.
rewrite <- quot_opp_opp, NZQuot.div_small_iff by order.
rewrite (abs_neq' a), (abs_neq' b); intuition; order.
Qed.
Lemma rem_small_iff : forall a b, b~=0 -> (a rem b == a <-> abs a < abs b).
Proof.
intros. rewrite rem_eq, <- quot_small_iff by order.
rewrite sub_move_r, <- (add_0_r a) at 1. rewrite add_cancel_l.
rewrite eq_sym_iff, eq_mul_0. tauto.
Qed.
(** As soon as the divisor is strictly greater than 1,
the division is strictly decreasing. *)
Lemma quot_lt : forall a b, 0<a -> 1<b -> a÷b < a.
Proof. exact NZQuot.div_lt. Qed.
(** [le] is compatible with a positive division. *)
Lemma quot_le_mono : forall a b c, 0<c -> a<=b -> a÷c <= b÷c.
Proof.
intros. pos_or_neg a. apply NZQuot.div_le_mono; auto.
pos_or_neg b. apply le_trans with 0.
rewrite <- opp_nonneg_nonpos, <- quot_opp_l by order.
apply quot_pos; order.
apply quot_pos; order.
rewrite opp_le_mono in *. rewrite <- 2 quot_opp_l by order.
apply NZQuot.div_le_mono; intuition; order.
Qed.
(** With this choice of division,
rounding of quot is always done toward zero: *)
Lemma mul_quot_le : forall a b, 0<=a -> b~=0 -> 0 <= b*(a÷b) <= a.
Proof.
intros. pos_or_neg b.
split.
apply mul_nonneg_nonneg; [|apply quot_pos]; order.
apply NZQuot.mul_div_le; order.
rewrite <- mul_opp_opp, <- quot_opp_r by order.
split.
apply mul_nonneg_nonneg; [|apply quot_pos]; order.
apply NZQuot.mul_div_le; order.
Qed.
Lemma mul_quot_ge : forall a b, a<=0 -> b~=0 -> a <= b*(a÷b) <= 0.
Proof.
intros.
rewrite <- opp_nonneg_nonpos, opp_le_mono, <-mul_opp_r, <-quot_opp_l by order.
rewrite <- opp_nonneg_nonpos in *.
destruct (mul_quot_le (-a) b); tauto.
Qed.
(** For positive numbers, considering [S (a÷b)] leads to an upper bound for [a] *)
Lemma mul_succ_quot_gt: forall a b, 0<=a -> 0<b -> a < b*(S (a÷b)).
Proof. exact NZQuot.mul_succ_div_gt. Qed.
(** Similar results with negative numbers *)
Lemma mul_pred_quot_lt: forall a b, a<=0 -> 0<b -> b*(P (a÷b)) < a.
Proof.
intros.
rewrite opp_lt_mono, <- mul_opp_r, opp_pred, <- quot_opp_l by order.
rewrite <- opp_nonneg_nonpos in *.
now apply mul_succ_quot_gt.
Qed.
Lemma mul_pred_quot_gt: forall a b, 0<=a -> b<0 -> a < b*(P (a÷b)).
Proof.
intros.
rewrite <- mul_opp_opp, opp_pred, <- quot_opp_r by order.
rewrite <- opp_pos_neg in *.
now apply mul_succ_quot_gt.
Qed.
Lemma mul_succ_quot_lt: forall a b, a<=0 -> b<0 -> b*(S (a÷b)) < a.
Proof.
intros.
rewrite opp_lt_mono, <- mul_opp_l, <- quot_opp_opp by order.
rewrite <- opp_nonneg_nonpos, <- opp_pos_neg in *.
now apply mul_succ_quot_gt.
Qed.
(** Inequality [mul_quot_le] is exact iff the modulo is zero. *)
Lemma quot_exact : forall a b, b~=0 -> (a == b*(a÷b) <-> a rem b == 0).
Proof.
intros. rewrite rem_eq by order. rewrite sub_move_r; nzsimpl; tauto.
Qed.
(** Some additional inequalities about quot. *)
Theorem quot_lt_upper_bound:
forall a b q, 0<=a -> 0<b -> a < b*q -> a÷b < q.
Proof. exact NZQuot.div_lt_upper_bound. Qed.
Theorem quot_le_upper_bound:
forall a b q, 0<b -> a <= b*q -> a÷b <= q.
Proof.
intros.
rewrite <- (quot_mul q b) by order.
apply quot_le_mono; trivial. now rewrite mul_comm.
Qed.
Theorem quot_le_lower_bound:
forall a b q, 0<b -> b*q <= a -> q <= a÷b.
Proof.
intros.
rewrite <- (quot_mul q b) by order.
apply quot_le_mono; trivial. now rewrite mul_comm.
Qed.
(** A division respects opposite monotonicity for the divisor *)
Lemma quot_le_compat_l: forall p q r, 0<=p -> 0<q<=r -> p÷r <= p÷q.
Proof. exact NZQuot.div_le_compat_l. Qed.
(** * Relations between usual operations and rem and quot *)
(** Unlike with other division conventions, some results here aren't
always valid, and need to be restricted. For instance
[(a+b*c) rem c <> a rem c] for [a=9,b=-5,c=2] *)
Lemma rem_add : forall a b c, c~=0 -> 0 <= (a+b*c)*a ->
(a + b * c) rem c == a rem c.
Proof.
assert (forall a b c, c~=0 -> 0<=a -> 0<=a+b*c -> (a+b*c) rem c == a rem c).
intros. pos_or_neg c. apply NZQuot.mod_add; order.
rewrite <- (rem_opp_r a), <- (rem_opp_r (a+b*c)) by order.
rewrite <- mul_opp_opp in *.
apply NZQuot.mod_add; order.
intros a b c Hc Habc.
destruct (le_0_mul _ _ Habc) as [(Habc',Ha)|(Habc',Ha)]. auto.
apply opp_inj. revert Ha Habc'.
rewrite <- 2 opp_nonneg_nonpos.
rewrite <- 2 rem_opp_l, opp_add_distr, <- mul_opp_l by order. auto.
Qed.
Lemma quot_add : forall a b c, c~=0 -> 0 <= (a+b*c)*a ->
(a + b * c) ÷ c == a ÷ c + b.
Proof.
intros.
rewrite <- (mul_cancel_l _ _ c) by trivial.
rewrite <- (add_cancel_r _ _ ((a+b*c) rem c)).
rewrite <- quot_rem, rem_add by trivial.
now rewrite mul_add_distr_l, add_shuffle0, <-quot_rem, mul_comm.
Qed.
Lemma quot_add_l: forall a b c, b~=0 -> 0 <= (a*b+c)*c ->
(a * b + c) ÷ b == a + c ÷ b.
Proof.
intros a b c. rewrite add_comm, (add_comm a). now apply quot_add.
Qed.
(** Cancellations. *)
Lemma quot_mul_cancel_r : forall a b c, b~=0 -> c~=0 ->
(a*c)÷(b*c) == a÷b.
Proof.
assert (Aux1 : forall a b c, 0<=a -> 0<b -> c~=0 -> (a*c)÷(b*c) == a÷b).
intros. pos_or_neg c. apply NZQuot.div_mul_cancel_r; order.
rewrite <- quot_opp_opp, <- 2 mul_opp_r. apply NZQuot.div_mul_cancel_r; order.
rewrite <- neq_mul_0; intuition order.
assert (Aux2 : forall a b c, 0<=a -> b~=0 -> c~=0 -> (a*c)÷(b*c) == a÷b).
intros. pos_or_neg b. apply Aux1; order.
apply opp_inj. rewrite <- 2 quot_opp_r, <- mul_opp_l; try order. apply Aux1; order.
rewrite <- neq_mul_0; intuition order.
intros. pos_or_neg a. apply Aux2; order.
apply opp_inj. rewrite <- 2 quot_opp_l, <- mul_opp_l; try order. apply Aux2; order.
rewrite <- neq_mul_0; intuition order.
Qed.
Lemma quot_mul_cancel_l : forall a b c, b~=0 -> c~=0 ->
(c*a)÷(c*b) == a÷b.
Proof.
intros. rewrite !(mul_comm c); now apply quot_mul_cancel_r.
Qed.
Lemma mul_rem_distr_r: forall a b c, b~=0 -> c~=0 ->
(a*c) rem (b*c) == (a rem b) * c.
Proof.
intros.
assert (b*c ~= 0) by (rewrite <- neq_mul_0; tauto).
rewrite ! rem_eq by trivial.
rewrite quot_mul_cancel_r by order.
now rewrite mul_sub_distr_r, <- !mul_assoc, (mul_comm (a÷b) c).
Qed.
Lemma mul_rem_distr_l: forall a b c, b~=0 -> c~=0 ->
(c*a) rem (c*b) == c * (a rem b).
Proof.
intros; rewrite !(mul_comm c); now apply mul_rem_distr_r.
Qed.
(** Operations modulo. *)
Theorem rem_rem: forall a n, n~=0 ->
(a rem n) rem n == a rem n.
Proof.
intros. pos_or_neg a; pos_or_neg n. apply NZQuot.mod_mod; order.
rewrite <- ! (rem_opp_r _ n) by trivial. apply NZQuot.mod_mod; order.
apply opp_inj. rewrite <- !rem_opp_l by order. apply NZQuot.mod_mod; order.
apply opp_inj. rewrite <- !rem_opp_opp by order. apply NZQuot.mod_mod; order.
Qed.
Lemma mul_rem_idemp_l : forall a b n, n~=0 ->
((a rem n)*b) rem n == (a*b) rem n.
Proof.
assert (Aux1 : forall a b n, 0<=a -> 0<=b -> n~=0 ->
((a rem n)*b) rem n == (a*b) rem n).
intros. pos_or_neg n. apply NZQuot.mul_mod_idemp_l; order.
rewrite <- ! (rem_opp_r _ n) by order. apply NZQuot.mul_mod_idemp_l; order.
assert (Aux2 : forall a b n, 0<=a -> n~=0 ->
((a rem n)*b) rem n == (a*b) rem n).
intros. pos_or_neg b. now apply Aux1.
apply opp_inj. rewrite <-2 rem_opp_l, <-2 mul_opp_r by order.
apply Aux1; order.
intros a b n Hn. pos_or_neg a. now apply Aux2.
apply opp_inj. rewrite <-2 rem_opp_l, <-2 mul_opp_l, <-rem_opp_l by order.
apply Aux2; order.
Qed.
Lemma mul_rem_idemp_r : forall a b n, n~=0 ->
(a*(b rem n)) rem n == (a*b) rem n.
Proof.
intros. rewrite !(mul_comm a). now apply mul_rem_idemp_l.
Qed.
Theorem mul_rem: forall a b n, n~=0 ->
(a * b) rem n == ((a rem n) * (b rem n)) rem n.
Proof.
intros. now rewrite mul_rem_idemp_l, mul_rem_idemp_r.
Qed.
(** addition and modulo
Generally speaking, unlike with other conventions, we don't have
[(a+b) rem n = (a rem n + b rem n) rem n]
for any a and b.
For instance, take (8 + (-10)) rem 3 = -2 whereas
(8 rem 3 + (-10 rem 3)) rem 3 = 1.
*)
Lemma add_rem_idemp_l : forall a b n, n~=0 -> 0 <= a*b ->
((a rem n)+b) rem n == (a+b) rem n.
Proof.
assert (Aux : forall a b n, 0<=a -> 0<=b -> n~=0 ->
((a rem n)+b) rem n == (a+b) rem n).
intros. pos_or_neg n. apply NZQuot.add_mod_idemp_l; order.
rewrite <- ! (rem_opp_r _ n) by order. apply NZQuot.add_mod_idemp_l; order.
intros a b n Hn Hab. destruct (le_0_mul _ _ Hab) as [(Ha,Hb)|(Ha,Hb)].
now apply Aux.
apply opp_inj. rewrite <-2 rem_opp_l, 2 opp_add_distr, <-rem_opp_l by order.
rewrite <- opp_nonneg_nonpos in *.
now apply Aux.
Qed.
Lemma add_rem_idemp_r : forall a b n, n~=0 -> 0 <= a*b ->
(a+(b rem n)) rem n == (a+b) rem n.
Proof.
intros. rewrite !(add_comm a). apply add_rem_idemp_l; trivial.
now rewrite mul_comm.
Qed.
Theorem add_rem: forall a b n, n~=0 -> 0 <= a*b ->
(a+b) rem n == (a rem n + b rem n) rem n.
Proof.
intros a b n Hn Hab. rewrite add_rem_idemp_l, add_rem_idemp_r; trivial.
reflexivity.
destruct (le_0_mul _ _ Hab) as [(Ha,Hb)|(Ha,Hb)];
destruct (le_0_mul _ _ (rem_sign_mul b n Hn)) as [(Hb',Hm)|(Hb',Hm)];
auto using mul_nonneg_nonneg, mul_nonpos_nonpos.
setoid_replace b with 0 by order. rewrite rem_0_l by order. nzsimpl; order.
setoid_replace b with 0 by order. rewrite rem_0_l by order. nzsimpl; order.
Qed.
(** Conversely, the following results need less restrictions here. *)
Lemma quot_quot : forall a b c, b~=0 -> c~=0 ->
(a÷b)÷c == a÷(b*c).
Proof.
assert (Aux1 : forall a b c, 0<=a -> 0<b -> c~=0 -> (a÷b)÷c == a÷(b*c)).
intros. pos_or_neg c. apply NZQuot.div_div; order.
apply opp_inj. rewrite <- 2 quot_opp_r, <- mul_opp_r; trivial.
apply NZQuot.div_div; order.
rewrite <- neq_mul_0; intuition order.
assert (Aux2 : forall a b c, 0<=a -> b~=0 -> c~=0 -> (a÷b)÷c == a÷(b*c)).
intros. pos_or_neg b. apply Aux1; order.
apply opp_inj. rewrite <- quot_opp_l, <- 2 quot_opp_r, <- mul_opp_l; trivial.
apply Aux1; trivial.
rewrite <- neq_mul_0; intuition order.
intros. pos_or_neg a. apply Aux2; order.
apply opp_inj. rewrite <- 3 quot_opp_l; try order. apply Aux2; order.
rewrite <- neq_mul_0. tauto.
Qed.
Lemma mod_mul_r : forall a b c, b~=0 -> c~=0 ->
a rem (b*c) == a rem b + b*((a÷b) rem c).
Proof.
intros a b c Hb Hc.
apply add_cancel_l with (b*c*(a÷(b*c))).
rewrite <- quot_rem by (apply neq_mul_0; split; order).
rewrite <- quot_quot by trivial.
rewrite add_assoc, add_shuffle0, <- mul_assoc, <- mul_add_distr_l.
rewrite <- quot_rem by order.
apply quot_rem; order.
Qed.
Lemma rem_quot: forall a b, b~=0 ->
a rem b ÷ b == 0.
Proof.
intros a b Hb.
rewrite quot_small_iff by assumption.
auto using rem_bound_abs.
Qed.
(** A last inequality: *)
Theorem quot_mul_le:
forall a b c, 0<=a -> 0<b -> 0<=c -> c*(a÷b) <= (c*a)÷b.
Proof. exact NZQuot.div_mul_le. Qed.
End ZQuotProp.
|
/*
* The nice thing about defines that are not possible with parameters is that
* you can pull defines to an external file and have all the defines in one
* place. This can be accomplished with parameters and UCF files but that
* would be vendor specific
*/
`define FX3_READ_START_LATENCY 1
`define FX3_WRITE_FULL_LATENCY 4
`include "project_include.v"
module fx3_bus # (
parameter ADDRESS_WIDTH = 8 //128 coincides with the maximum DMA
//packet size for USB 2.0
//256 coincides with the maximum DMA
//packet size for USB 3.0 since the 512
//will work for both then the FIFOs will
//be sized for this
)(
input clk,
input rst,
//Phy Interface
inout [31:0] io_data,
output o_oe_n,
output o_we_n,
output o_re_n,
output o_pkt_end_n,
input i_in_ch0_rdy,
input i_in_ch1_rdy,
input i_out_ch0_rdy,
input i_out_ch1_rdy,
output [1:0] o_socket_addr,
//Master Interface
input i_master_ready,
output [7:0] o_command,
output [7:0] o_flag,
output [31:0] o_rw_count,
output [31:0] o_address,
output o_command_rdy_stb,
input [7:0] i_status,
input [31:0] i_read_size,
input i_status_rdy_stb,
input [31:0] i_address, //Calculated end address, this can be
//used to verify that the mem was
//calculated correctly
//Write side FIFO interface
output o_wpath_ready,
input i_wpath_activate,
output [23:0] o_wpath_packet_size,
output [31:0] o_wpath_data,
input i_wpath_strobe,
//Read side FIFO interface
output [1:0] o_rpath_ready,
input [1:0] i_rpath_activate,
output [23:0] o_rpath_size,
input [31:0] i_rpath_data,
input i_rpath_strobe
);
//Local Parameters
//Registers/Wires
wire w_output_enable;
wire w_read_enable;
wire w_write_enable;
wire w_packet_end;
wire [31:0] w_in_data;
wire [31:0] w_out_data;
wire w_data_valid;
wire [23:0] w_packet_size;
wire w_read_flow_cntrl;
//In Path Control
wire w_in_path_enable;
wire w_in_path_busy;
wire w_in_path_finished;
//In Command Path
wire w_in_path_cmd_enable;
wire w_in_path_cmd_busy;
wire w_in_path_cmd_finished;
//Out Path Control
wire w_out_path_ready;
wire w_out_path_enable;
wire w_out_path_busy;
wire w_out_path_finished;
//Submodules
//Data From FX3 to FPGA
fx3_bus_in_path in_path(
.clk (clk ),
.rst (rst ),
//Control Signals
.i_packet_size (w_packet_size ),
.i_read_flow_cntrl (w_read_flow_cntrl ),
//FX3 Interface
.o_output_enable (w_output_enable ),
.o_read_enable (w_read_enable ),
//When high w_in_data is valid
.o_data_valid (w_data_valid ),
.i_in_path_enable (w_in_path_enable ),
.o_in_path_busy (w_in_path_busy ),
.o_in_path_finished (w_in_path_finished )
);
//Data from in_path to command reader
fx3_bus_in_command in_cmd(
.clk (clk ),
.rst (rst ),
.o_read_flow_cntrl (w_read_flow_cntrl ),
//Control
.i_in_path_cmd_enable (w_in_path_cmd_enable ),
.o_in_path_cmd_busy (w_in_path_cmd_busy ),
.o_in_path_cmd_finished (w_in_path_cmd_finished ),
//Data
.i_data (w_in_data ),
//Data Valid Flag
.i_data_valid (w_data_valid ),
//Master Interface
.o_command (o_command ),
.o_flag (o_flag ),
.o_rw_count (o_rw_count ),
.o_address (o_address ),
.o_command_rdy_stb (o_command_rdy_stb ),
//Write side FIFO interface
.o_in_ready (o_wpath_ready ),
.i_in_activate (i_wpath_activate ),
.o_in_packet_size (o_wpath_packet_size ),
.o_in_data (o_wpath_data ),
.i_in_strobe (i_wpath_strobe )
);
//Data from Master to The host
fx3_bus_out_path out_path(
.clk (clk ),
.rst (rst ),
//Control
.o_out_path_ready (w_out_path_ready ),
.i_out_path_enable (w_out_path_enable ),
.o_out_path_busy (w_out_path_busy ),
.o_out_path_finished (w_out_path_finished ),
.i_dma_buf_ready (w_out_dma_buf_ready ),
.o_dma_buf_finished (w_out_dma_buf_finished ),
//Packet size
.i_packet_size (w_packet_size ),
.i_status_rdy_stb (i_status_rdy_stb ),
.i_read_size (i_read_size ),
//FX3 Interface
.o_write_enable (w_write_enable ),
.o_packet_end (w_packet_end ),
.o_data (w_out_data ),
//FIFO in path
.o_rpath_ready (o_rpath_ready ),
.i_rpath_activate (i_rpath_activate ),
.o_rpath_size (o_rpath_size ),
.i_rpath_data (i_rpath_data ),
.i_rpath_strobe (i_rpath_strobe )
);
fx3_bus_controller controller(
.clk (clk ),
.rst (rst ),
//FX3 Parallel Interface
.i_in_ch0_rdy (i_in_ch0_rdy ),
.i_in_ch1_rdy (i_in_ch1_rdy ),
.i_out_ch0_rdy (i_out_ch0_rdy ),
.i_out_ch1_rdy (i_out_ch1_rdy ),
.o_socket_addr (o_socket_addr ),
//Incomming Data
.i_master_rdy (i_master_ready ),
//Outgoing Flags/Feedback
.o_in_path_enable (w_in_path_enable ),
.i_in_path_busy (w_in_path_busy ),
.i_in_path_finished (w_in_path_finished ),
//Command Path
.o_in_path_cmd_enable (w_in_path_cmd_enable ),
.i_in_path_cmd_busy (w_in_path_cmd_busy ),
.i_in_path_cmd_finished (w_in_path_cmd_finished ),
//Master Interface
//Output Path
.i_out_path_ready (w_out_path_ready ),
.o_out_path_enable (w_out_path_enable ),
.i_out_path_busy (w_out_path_busy ),
.i_out_path_finished (w_out_path_finished ),
.o_out_dma_buf_ready (w_out_dma_buf_ready ),
.i_out_dma_buf_finished (w_out_dma_buf_finished )
);
//Asynchronous Logic
assign o_oe_n = !w_output_enable;
assign o_re_n = !w_read_enable;
assign o_we_n = !w_write_enable;
assign o_pkt_end_n = !w_packet_end;
assign io_data = (w_output_enable) ? 32'hZZZZZZZZ : w_out_data;
assign w_in_data = (w_data_valid) ? io_data : 32'h00000000;
//XXX: NOTE THIS SHOULD BE ADJUSTABLE FROM THE SPEED DETECT MODULE
assign w_packet_size = 24'h80;
//Synchronous Logic
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND3B_1_V
`define SKY130_FD_SC_HD__AND3B_1_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog wrapper for and3b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__and3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and3b_1 (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and3b_1 (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND3B_1_V
|
//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:47:07 MST 2014
//Date : Sun Apr 3 12:37:39 2016
//Host : ubuntu-desktop running 64-bit Ubuntu 14.04.4 LTS
//Command : generate_target design_1.bd
//Design : design_1
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module design_1
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire GND_1;
wire VCC_1;
wire [12:0]axi_bram_ctrl_0_BRAM_PORTA_ADDR;
wire axi_bram_ctrl_0_BRAM_PORTA_CLK;
wire [31:0]axi_bram_ctrl_0_BRAM_PORTA_DIN;
wire [31:0]axi_bram_ctrl_0_BRAM_PORTA_DOUT;
wire axi_bram_ctrl_0_BRAM_PORTA_EN;
wire axi_bram_ctrl_0_BRAM_PORTA_RST;
wire [3:0]axi_bram_ctrl_0_BRAM_PORTA_WE;
wire [12:0]axi_bram_ctrl_1_BRAM_PORTA_ADDR;
wire axi_bram_ctrl_1_BRAM_PORTA_CLK;
wire [31:0]axi_bram_ctrl_1_BRAM_PORTA_DIN;
wire [31:0]axi_bram_ctrl_1_BRAM_PORTA_DOUT;
wire axi_bram_ctrl_1_BRAM_PORTA_EN;
wire axi_bram_ctrl_1_BRAM_PORTA_RST;
wire [3:0]axi_bram_ctrl_1_BRAM_PORTA_WE;
wire [12:0]axi_mem_intercon_1_M00_AXI_ARADDR;
wire [1:0]axi_mem_intercon_1_M00_AXI_ARBURST;
wire [3:0]axi_mem_intercon_1_M00_AXI_ARCACHE;
wire [11:0]axi_mem_intercon_1_M00_AXI_ARID;
wire [7:0]axi_mem_intercon_1_M00_AXI_ARLEN;
wire [0:0]axi_mem_intercon_1_M00_AXI_ARLOCK;
wire [2:0]axi_mem_intercon_1_M00_AXI_ARPROT;
wire axi_mem_intercon_1_M00_AXI_ARREADY;
wire [2:0]axi_mem_intercon_1_M00_AXI_ARSIZE;
wire axi_mem_intercon_1_M00_AXI_ARVALID;
wire [12:0]axi_mem_intercon_1_M00_AXI_AWADDR;
wire [1:0]axi_mem_intercon_1_M00_AXI_AWBURST;
wire [3:0]axi_mem_intercon_1_M00_AXI_AWCACHE;
wire [11:0]axi_mem_intercon_1_M00_AXI_AWID;
wire [7:0]axi_mem_intercon_1_M00_AXI_AWLEN;
wire [0:0]axi_mem_intercon_1_M00_AXI_AWLOCK;
wire [2:0]axi_mem_intercon_1_M00_AXI_AWPROT;
wire axi_mem_intercon_1_M00_AXI_AWREADY;
wire [2:0]axi_mem_intercon_1_M00_AXI_AWSIZE;
wire axi_mem_intercon_1_M00_AXI_AWVALID;
wire [11:0]axi_mem_intercon_1_M00_AXI_BID;
wire axi_mem_intercon_1_M00_AXI_BREADY;
wire [1:0]axi_mem_intercon_1_M00_AXI_BRESP;
wire axi_mem_intercon_1_M00_AXI_BVALID;
wire [31:0]axi_mem_intercon_1_M00_AXI_RDATA;
wire [11:0]axi_mem_intercon_1_M00_AXI_RID;
wire axi_mem_intercon_1_M00_AXI_RLAST;
wire axi_mem_intercon_1_M00_AXI_RREADY;
wire [1:0]axi_mem_intercon_1_M00_AXI_RRESP;
wire axi_mem_intercon_1_M00_AXI_RVALID;
wire [31:0]axi_mem_intercon_1_M00_AXI_WDATA;
wire axi_mem_intercon_1_M00_AXI_WLAST;
wire axi_mem_intercon_1_M00_AXI_WREADY;
wire [3:0]axi_mem_intercon_1_M00_AXI_WSTRB;
wire axi_mem_intercon_1_M00_AXI_WVALID;
wire [12:0]axi_mem_intercon_M00_AXI_ARADDR;
wire [1:0]axi_mem_intercon_M00_AXI_ARBURST;
wire [3:0]axi_mem_intercon_M00_AXI_ARCACHE;
wire [11:0]axi_mem_intercon_M00_AXI_ARID;
wire [7:0]axi_mem_intercon_M00_AXI_ARLEN;
wire [0:0]axi_mem_intercon_M00_AXI_ARLOCK;
wire [2:0]axi_mem_intercon_M00_AXI_ARPROT;
wire axi_mem_intercon_M00_AXI_ARREADY;
wire [2:0]axi_mem_intercon_M00_AXI_ARSIZE;
wire axi_mem_intercon_M00_AXI_ARVALID;
wire [12:0]axi_mem_intercon_M00_AXI_AWADDR;
wire [1:0]axi_mem_intercon_M00_AXI_AWBURST;
wire [3:0]axi_mem_intercon_M00_AXI_AWCACHE;
wire [11:0]axi_mem_intercon_M00_AXI_AWID;
wire [7:0]axi_mem_intercon_M00_AXI_AWLEN;
wire [0:0]axi_mem_intercon_M00_AXI_AWLOCK;
wire [2:0]axi_mem_intercon_M00_AXI_AWPROT;
wire axi_mem_intercon_M00_AXI_AWREADY;
wire [2:0]axi_mem_intercon_M00_AXI_AWSIZE;
wire axi_mem_intercon_M00_AXI_AWVALID;
wire [11:0]axi_mem_intercon_M00_AXI_BID;
wire axi_mem_intercon_M00_AXI_BREADY;
wire [1:0]axi_mem_intercon_M00_AXI_BRESP;
wire axi_mem_intercon_M00_AXI_BVALID;
wire [31:0]axi_mem_intercon_M00_AXI_RDATA;
wire [11:0]axi_mem_intercon_M00_AXI_RID;
wire axi_mem_intercon_M00_AXI_RLAST;
wire axi_mem_intercon_M00_AXI_RREADY;
wire [1:0]axi_mem_intercon_M00_AXI_RRESP;
wire axi_mem_intercon_M00_AXI_RVALID;
wire [31:0]axi_mem_intercon_M00_AXI_WDATA;
wire axi_mem_intercon_M00_AXI_WLAST;
wire axi_mem_intercon_M00_AXI_WREADY;
wire [3:0]axi_mem_intercon_M00_AXI_WSTRB;
wire axi_mem_intercon_M00_AXI_WVALID;
wire [14:0]processing_system7_0_DDR_ADDR;
wire [2:0]processing_system7_0_DDR_BA;
wire processing_system7_0_DDR_CAS_N;
wire processing_system7_0_DDR_CKE;
wire processing_system7_0_DDR_CK_N;
wire processing_system7_0_DDR_CK_P;
wire processing_system7_0_DDR_CS_N;
wire [3:0]processing_system7_0_DDR_DM;
wire [31:0]processing_system7_0_DDR_DQ;
wire [3:0]processing_system7_0_DDR_DQS_N;
wire [3:0]processing_system7_0_DDR_DQS_P;
wire processing_system7_0_DDR_ODT;
wire processing_system7_0_DDR_RAS_N;
wire processing_system7_0_DDR_RESET_N;
wire processing_system7_0_DDR_WE_N;
wire processing_system7_0_FCLK_CLK0;
wire processing_system7_0_FCLK_RESET0_N;
wire processing_system7_0_FIXED_IO_DDR_VRN;
wire processing_system7_0_FIXED_IO_DDR_VRP;
wire [53:0]processing_system7_0_FIXED_IO_MIO;
wire processing_system7_0_FIXED_IO_PS_CLK;
wire processing_system7_0_FIXED_IO_PS_PORB;
wire processing_system7_0_FIXED_IO_PS_SRSTB;
wire [31:0]processing_system7_0_M_AXI_GP0_ARADDR;
wire [1:0]processing_system7_0_M_AXI_GP0_ARBURST;
wire [3:0]processing_system7_0_M_AXI_GP0_ARCACHE;
wire [11:0]processing_system7_0_M_AXI_GP0_ARID;
wire [3:0]processing_system7_0_M_AXI_GP0_ARLEN;
wire [1:0]processing_system7_0_M_AXI_GP0_ARLOCK;
wire [2:0]processing_system7_0_M_AXI_GP0_ARPROT;
wire [3:0]processing_system7_0_M_AXI_GP0_ARQOS;
wire processing_system7_0_M_AXI_GP0_ARREADY;
wire [2:0]processing_system7_0_M_AXI_GP0_ARSIZE;
wire processing_system7_0_M_AXI_GP0_ARVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_AWADDR;
wire [1:0]processing_system7_0_M_AXI_GP0_AWBURST;
wire [3:0]processing_system7_0_M_AXI_GP0_AWCACHE;
wire [11:0]processing_system7_0_M_AXI_GP0_AWID;
wire [3:0]processing_system7_0_M_AXI_GP0_AWLEN;
wire [1:0]processing_system7_0_M_AXI_GP0_AWLOCK;
wire [2:0]processing_system7_0_M_AXI_GP0_AWPROT;
wire [3:0]processing_system7_0_M_AXI_GP0_AWQOS;
wire processing_system7_0_M_AXI_GP0_AWREADY;
wire [2:0]processing_system7_0_M_AXI_GP0_AWSIZE;
wire processing_system7_0_M_AXI_GP0_AWVALID;
wire [11:0]processing_system7_0_M_AXI_GP0_BID;
wire processing_system7_0_M_AXI_GP0_BREADY;
wire [1:0]processing_system7_0_M_AXI_GP0_BRESP;
wire processing_system7_0_M_AXI_GP0_BVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_RDATA;
wire [11:0]processing_system7_0_M_AXI_GP0_RID;
wire processing_system7_0_M_AXI_GP0_RLAST;
wire processing_system7_0_M_AXI_GP0_RREADY;
wire [1:0]processing_system7_0_M_AXI_GP0_RRESP;
wire processing_system7_0_M_AXI_GP0_RVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_WDATA;
wire [11:0]processing_system7_0_M_AXI_GP0_WID;
wire processing_system7_0_M_AXI_GP0_WLAST;
wire processing_system7_0_M_AXI_GP0_WREADY;
wire [3:0]processing_system7_0_M_AXI_GP0_WSTRB;
wire processing_system7_0_M_AXI_GP0_WVALID;
wire [31:0]processing_system7_0_M_AXI_GP1_ARADDR;
wire [1:0]processing_system7_0_M_AXI_GP1_ARBURST;
wire [3:0]processing_system7_0_M_AXI_GP1_ARCACHE;
wire [11:0]processing_system7_0_M_AXI_GP1_ARID;
wire [3:0]processing_system7_0_M_AXI_GP1_ARLEN;
wire [1:0]processing_system7_0_M_AXI_GP1_ARLOCK;
wire [2:0]processing_system7_0_M_AXI_GP1_ARPROT;
wire [3:0]processing_system7_0_M_AXI_GP1_ARQOS;
wire processing_system7_0_M_AXI_GP1_ARREADY;
wire [2:0]processing_system7_0_M_AXI_GP1_ARSIZE;
wire processing_system7_0_M_AXI_GP1_ARVALID;
wire [31:0]processing_system7_0_M_AXI_GP1_AWADDR;
wire [1:0]processing_system7_0_M_AXI_GP1_AWBURST;
wire [3:0]processing_system7_0_M_AXI_GP1_AWCACHE;
wire [11:0]processing_system7_0_M_AXI_GP1_AWID;
wire [3:0]processing_system7_0_M_AXI_GP1_AWLEN;
wire [1:0]processing_system7_0_M_AXI_GP1_AWLOCK;
wire [2:0]processing_system7_0_M_AXI_GP1_AWPROT;
wire [3:0]processing_system7_0_M_AXI_GP1_AWQOS;
wire processing_system7_0_M_AXI_GP1_AWREADY;
wire [2:0]processing_system7_0_M_AXI_GP1_AWSIZE;
wire processing_system7_0_M_AXI_GP1_AWVALID;
wire [11:0]processing_system7_0_M_AXI_GP1_BID;
wire processing_system7_0_M_AXI_GP1_BREADY;
wire [1:0]processing_system7_0_M_AXI_GP1_BRESP;
wire processing_system7_0_M_AXI_GP1_BVALID;
wire [31:0]processing_system7_0_M_AXI_GP1_RDATA;
wire [11:0]processing_system7_0_M_AXI_GP1_RID;
wire processing_system7_0_M_AXI_GP1_RLAST;
wire processing_system7_0_M_AXI_GP1_RREADY;
wire [1:0]processing_system7_0_M_AXI_GP1_RRESP;
wire processing_system7_0_M_AXI_GP1_RVALID;
wire [31:0]processing_system7_0_M_AXI_GP1_WDATA;
wire [11:0]processing_system7_0_M_AXI_GP1_WID;
wire processing_system7_0_M_AXI_GP1_WLAST;
wire processing_system7_0_M_AXI_GP1_WREADY;
wire [3:0]processing_system7_0_M_AXI_GP1_WSTRB;
wire processing_system7_0_M_AXI_GP1_WVALID;
wire [0:0]rst_processing_system7_0_100M_interconnect_aresetn;
wire [0:0]rst_processing_system7_0_100M_peripheral_aresetn;
GND GND
(.G(GND_1));
VCC VCC
(.P(VCC_1));
(* BMM_INFO_ADDRESS_SPACE = "byte 0x40000000 32 > design_1 blk_mem_gen_0" *)
(* KEEP_HIERARCHY = "yes" *)
design_1_axi_bram_ctrl_0_0 axi_bram_ctrl_0
(.bram_addr_a(axi_bram_ctrl_0_BRAM_PORTA_ADDR),
.bram_clk_a(axi_bram_ctrl_0_BRAM_PORTA_CLK),
.bram_en_a(axi_bram_ctrl_0_BRAM_PORTA_EN),
.bram_rddata_a(axi_bram_ctrl_0_BRAM_PORTA_DOUT),
.bram_rst_a(axi_bram_ctrl_0_BRAM_PORTA_RST),
.bram_we_a(axi_bram_ctrl_0_BRAM_PORTA_WE),
.bram_wrdata_a(axi_bram_ctrl_0_BRAM_PORTA_DIN),
.s_axi_aclk(processing_system7_0_FCLK_CLK0),
.s_axi_araddr(axi_mem_intercon_M00_AXI_ARADDR),
.s_axi_arburst(axi_mem_intercon_M00_AXI_ARBURST),
.s_axi_arcache(axi_mem_intercon_M00_AXI_ARCACHE),
.s_axi_aresetn(rst_processing_system7_0_100M_peripheral_aresetn),
.s_axi_arid(axi_mem_intercon_M00_AXI_ARID),
.s_axi_arlen(axi_mem_intercon_M00_AXI_ARLEN),
.s_axi_arlock(axi_mem_intercon_M00_AXI_ARLOCK),
.s_axi_arprot(axi_mem_intercon_M00_AXI_ARPROT),
.s_axi_arready(axi_mem_intercon_M00_AXI_ARREADY),
.s_axi_arsize(axi_mem_intercon_M00_AXI_ARSIZE),
.s_axi_arvalid(axi_mem_intercon_M00_AXI_ARVALID),
.s_axi_awaddr(axi_mem_intercon_M00_AXI_AWADDR),
.s_axi_awburst(axi_mem_intercon_M00_AXI_AWBURST),
.s_axi_awcache(axi_mem_intercon_M00_AXI_AWCACHE),
.s_axi_awid(axi_mem_intercon_M00_AXI_AWID),
.s_axi_awlen(axi_mem_intercon_M00_AXI_AWLEN),
.s_axi_awlock(axi_mem_intercon_M00_AXI_AWLOCK),
.s_axi_awprot(axi_mem_intercon_M00_AXI_AWPROT),
.s_axi_awready(axi_mem_intercon_M00_AXI_AWREADY),
.s_axi_awsize(axi_mem_intercon_M00_AXI_AWSIZE),
.s_axi_awvalid(axi_mem_intercon_M00_AXI_AWVALID),
.s_axi_bid(axi_mem_intercon_M00_AXI_BID),
.s_axi_bready(axi_mem_intercon_M00_AXI_BREADY),
.s_axi_bresp(axi_mem_intercon_M00_AXI_BRESP),
.s_axi_bvalid(axi_mem_intercon_M00_AXI_BVALID),
.s_axi_rdata(axi_mem_intercon_M00_AXI_RDATA),
.s_axi_rid(axi_mem_intercon_M00_AXI_RID),
.s_axi_rlast(axi_mem_intercon_M00_AXI_RLAST),
.s_axi_rready(axi_mem_intercon_M00_AXI_RREADY),
.s_axi_rresp(axi_mem_intercon_M00_AXI_RRESP),
.s_axi_rvalid(axi_mem_intercon_M00_AXI_RVALID),
.s_axi_wdata(axi_mem_intercon_M00_AXI_WDATA),
.s_axi_wlast(axi_mem_intercon_M00_AXI_WLAST),
.s_axi_wready(axi_mem_intercon_M00_AXI_WREADY),
.s_axi_wstrb(axi_mem_intercon_M00_AXI_WSTRB),
.s_axi_wvalid(axi_mem_intercon_M00_AXI_WVALID));
design_1_axi_bram_ctrl_1_0 axi_bram_ctrl_1
(.bram_addr_a(axi_bram_ctrl_1_BRAM_PORTA_ADDR),
.bram_clk_a(axi_bram_ctrl_1_BRAM_PORTA_CLK),
.bram_en_a(axi_bram_ctrl_1_BRAM_PORTA_EN),
.bram_rddata_a(axi_bram_ctrl_1_BRAM_PORTA_DOUT),
.bram_rst_a(axi_bram_ctrl_1_BRAM_PORTA_RST),
.bram_we_a(axi_bram_ctrl_1_BRAM_PORTA_WE),
.bram_wrdata_a(axi_bram_ctrl_1_BRAM_PORTA_DIN),
.s_axi_aclk(processing_system7_0_FCLK_CLK0),
.s_axi_araddr(axi_mem_intercon_1_M00_AXI_ARADDR),
.s_axi_arburst(axi_mem_intercon_1_M00_AXI_ARBURST),
.s_axi_arcache(axi_mem_intercon_1_M00_AXI_ARCACHE),
.s_axi_aresetn(rst_processing_system7_0_100M_peripheral_aresetn),
.s_axi_arid(axi_mem_intercon_1_M00_AXI_ARID),
.s_axi_arlen(axi_mem_intercon_1_M00_AXI_ARLEN),
.s_axi_arlock(axi_mem_intercon_1_M00_AXI_ARLOCK),
.s_axi_arprot(axi_mem_intercon_1_M00_AXI_ARPROT),
.s_axi_arready(axi_mem_intercon_1_M00_AXI_ARREADY),
.s_axi_arsize(axi_mem_intercon_1_M00_AXI_ARSIZE),
.s_axi_arvalid(axi_mem_intercon_1_M00_AXI_ARVALID),
.s_axi_awaddr(axi_mem_intercon_1_M00_AXI_AWADDR),
.s_axi_awburst(axi_mem_intercon_1_M00_AXI_AWBURST),
.s_axi_awcache(axi_mem_intercon_1_M00_AXI_AWCACHE),
.s_axi_awid(axi_mem_intercon_1_M00_AXI_AWID),
.s_axi_awlen(axi_mem_intercon_1_M00_AXI_AWLEN),
.s_axi_awlock(axi_mem_intercon_1_M00_AXI_AWLOCK),
.s_axi_awprot(axi_mem_intercon_1_M00_AXI_AWPROT),
.s_axi_awready(axi_mem_intercon_1_M00_AXI_AWREADY),
.s_axi_awsize(axi_mem_intercon_1_M00_AXI_AWSIZE),
.s_axi_awvalid(axi_mem_intercon_1_M00_AXI_AWVALID),
.s_axi_bid(axi_mem_intercon_1_M00_AXI_BID),
.s_axi_bready(axi_mem_intercon_1_M00_AXI_BREADY),
.s_axi_bresp(axi_mem_intercon_1_M00_AXI_BRESP),
.s_axi_bvalid(axi_mem_intercon_1_M00_AXI_BVALID),
.s_axi_rdata(axi_mem_intercon_1_M00_AXI_RDATA),
.s_axi_rid(axi_mem_intercon_1_M00_AXI_RID),
.s_axi_rlast(axi_mem_intercon_1_M00_AXI_RLAST),
.s_axi_rready(axi_mem_intercon_1_M00_AXI_RREADY),
.s_axi_rresp(axi_mem_intercon_1_M00_AXI_RRESP),
.s_axi_rvalid(axi_mem_intercon_1_M00_AXI_RVALID),
.s_axi_wdata(axi_mem_intercon_1_M00_AXI_WDATA),
.s_axi_wlast(axi_mem_intercon_1_M00_AXI_WLAST),
.s_axi_wready(axi_mem_intercon_1_M00_AXI_WREADY),
.s_axi_wstrb(axi_mem_intercon_1_M00_AXI_WSTRB),
.s_axi_wvalid(axi_mem_intercon_1_M00_AXI_WVALID));
design_1_axi_mem_intercon_0 axi_mem_intercon
(.ACLK(processing_system7_0_FCLK_CLK0),
.ARESETN(rst_processing_system7_0_100M_interconnect_aresetn),
.M00_ACLK(processing_system7_0_FCLK_CLK0),
.M00_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M00_AXI_araddr(axi_mem_intercon_M00_AXI_ARADDR),
.M00_AXI_arburst(axi_mem_intercon_M00_AXI_ARBURST),
.M00_AXI_arcache(axi_mem_intercon_M00_AXI_ARCACHE),
.M00_AXI_arid(axi_mem_intercon_M00_AXI_ARID),
.M00_AXI_arlen(axi_mem_intercon_M00_AXI_ARLEN),
.M00_AXI_arlock(axi_mem_intercon_M00_AXI_ARLOCK),
.M00_AXI_arprot(axi_mem_intercon_M00_AXI_ARPROT),
.M00_AXI_arready(axi_mem_intercon_M00_AXI_ARREADY),
.M00_AXI_arsize(axi_mem_intercon_M00_AXI_ARSIZE),
.M00_AXI_arvalid(axi_mem_intercon_M00_AXI_ARVALID),
.M00_AXI_awaddr(axi_mem_intercon_M00_AXI_AWADDR),
.M00_AXI_awburst(axi_mem_intercon_M00_AXI_AWBURST),
.M00_AXI_awcache(axi_mem_intercon_M00_AXI_AWCACHE),
.M00_AXI_awid(axi_mem_intercon_M00_AXI_AWID),
.M00_AXI_awlen(axi_mem_intercon_M00_AXI_AWLEN),
.M00_AXI_awlock(axi_mem_intercon_M00_AXI_AWLOCK),
.M00_AXI_awprot(axi_mem_intercon_M00_AXI_AWPROT),
.M00_AXI_awready(axi_mem_intercon_M00_AXI_AWREADY),
.M00_AXI_awsize(axi_mem_intercon_M00_AXI_AWSIZE),
.M00_AXI_awvalid(axi_mem_intercon_M00_AXI_AWVALID),
.M00_AXI_bid(axi_mem_intercon_M00_AXI_BID),
.M00_AXI_bready(axi_mem_intercon_M00_AXI_BREADY),
.M00_AXI_bresp(axi_mem_intercon_M00_AXI_BRESP),
.M00_AXI_bvalid(axi_mem_intercon_M00_AXI_BVALID),
.M00_AXI_rdata(axi_mem_intercon_M00_AXI_RDATA),
.M00_AXI_rid(axi_mem_intercon_M00_AXI_RID),
.M00_AXI_rlast(axi_mem_intercon_M00_AXI_RLAST),
.M00_AXI_rready(axi_mem_intercon_M00_AXI_RREADY),
.M00_AXI_rresp(axi_mem_intercon_M00_AXI_RRESP),
.M00_AXI_rvalid(axi_mem_intercon_M00_AXI_RVALID),
.M00_AXI_wdata(axi_mem_intercon_M00_AXI_WDATA),
.M00_AXI_wlast(axi_mem_intercon_M00_AXI_WLAST),
.M00_AXI_wready(axi_mem_intercon_M00_AXI_WREADY),
.M00_AXI_wstrb(axi_mem_intercon_M00_AXI_WSTRB),
.M00_AXI_wvalid(axi_mem_intercon_M00_AXI_WVALID),
.S00_ACLK(processing_system7_0_FCLK_CLK0),
.S00_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.S00_AXI_araddr(processing_system7_0_M_AXI_GP0_ARADDR),
.S00_AXI_arburst(processing_system7_0_M_AXI_GP0_ARBURST),
.S00_AXI_arcache(processing_system7_0_M_AXI_GP0_ARCACHE),
.S00_AXI_arid(processing_system7_0_M_AXI_GP0_ARID),
.S00_AXI_arlen(processing_system7_0_M_AXI_GP0_ARLEN),
.S00_AXI_arlock(processing_system7_0_M_AXI_GP0_ARLOCK),
.S00_AXI_arprot(processing_system7_0_M_AXI_GP0_ARPROT),
.S00_AXI_arqos(processing_system7_0_M_AXI_GP0_ARQOS),
.S00_AXI_arready(processing_system7_0_M_AXI_GP0_ARREADY),
.S00_AXI_arsize(processing_system7_0_M_AXI_GP0_ARSIZE),
.S00_AXI_arvalid(processing_system7_0_M_AXI_GP0_ARVALID),
.S00_AXI_awaddr(processing_system7_0_M_AXI_GP0_AWADDR),
.S00_AXI_awburst(processing_system7_0_M_AXI_GP0_AWBURST),
.S00_AXI_awcache(processing_system7_0_M_AXI_GP0_AWCACHE),
.S00_AXI_awid(processing_system7_0_M_AXI_GP0_AWID),
.S00_AXI_awlen(processing_system7_0_M_AXI_GP0_AWLEN),
.S00_AXI_awlock(processing_system7_0_M_AXI_GP0_AWLOCK),
.S00_AXI_awprot(processing_system7_0_M_AXI_GP0_AWPROT),
.S00_AXI_awqos(processing_system7_0_M_AXI_GP0_AWQOS),
.S00_AXI_awready(processing_system7_0_M_AXI_GP0_AWREADY),
.S00_AXI_awsize(processing_system7_0_M_AXI_GP0_AWSIZE),
.S00_AXI_awvalid(processing_system7_0_M_AXI_GP0_AWVALID),
.S00_AXI_bid(processing_system7_0_M_AXI_GP0_BID),
.S00_AXI_bready(processing_system7_0_M_AXI_GP0_BREADY),
.S00_AXI_bresp(processing_system7_0_M_AXI_GP0_BRESP),
.S00_AXI_bvalid(processing_system7_0_M_AXI_GP0_BVALID),
.S00_AXI_rdata(processing_system7_0_M_AXI_GP0_RDATA),
.S00_AXI_rid(processing_system7_0_M_AXI_GP0_RID),
.S00_AXI_rlast(processing_system7_0_M_AXI_GP0_RLAST),
.S00_AXI_rready(processing_system7_0_M_AXI_GP0_RREADY),
.S00_AXI_rresp(processing_system7_0_M_AXI_GP0_RRESP),
.S00_AXI_rvalid(processing_system7_0_M_AXI_GP0_RVALID),
.S00_AXI_wdata(processing_system7_0_M_AXI_GP0_WDATA),
.S00_AXI_wid(processing_system7_0_M_AXI_GP0_WID),
.S00_AXI_wlast(processing_system7_0_M_AXI_GP0_WLAST),
.S00_AXI_wready(processing_system7_0_M_AXI_GP0_WREADY),
.S00_AXI_wstrb(processing_system7_0_M_AXI_GP0_WSTRB),
.S00_AXI_wvalid(processing_system7_0_M_AXI_GP0_WVALID));
design_1_axi_mem_intercon_1_0 axi_mem_intercon_1
(.ACLK(processing_system7_0_FCLK_CLK0),
.ARESETN(rst_processing_system7_0_100M_interconnect_aresetn),
.M00_ACLK(processing_system7_0_FCLK_CLK0),
.M00_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M00_AXI_araddr(axi_mem_intercon_1_M00_AXI_ARADDR),
.M00_AXI_arburst(axi_mem_intercon_1_M00_AXI_ARBURST),
.M00_AXI_arcache(axi_mem_intercon_1_M00_AXI_ARCACHE),
.M00_AXI_arid(axi_mem_intercon_1_M00_AXI_ARID),
.M00_AXI_arlen(axi_mem_intercon_1_M00_AXI_ARLEN),
.M00_AXI_arlock(axi_mem_intercon_1_M00_AXI_ARLOCK),
.M00_AXI_arprot(axi_mem_intercon_1_M00_AXI_ARPROT),
.M00_AXI_arready(axi_mem_intercon_1_M00_AXI_ARREADY),
.M00_AXI_arsize(axi_mem_intercon_1_M00_AXI_ARSIZE),
.M00_AXI_arvalid(axi_mem_intercon_1_M00_AXI_ARVALID),
.M00_AXI_awaddr(axi_mem_intercon_1_M00_AXI_AWADDR),
.M00_AXI_awburst(axi_mem_intercon_1_M00_AXI_AWBURST),
.M00_AXI_awcache(axi_mem_intercon_1_M00_AXI_AWCACHE),
.M00_AXI_awid(axi_mem_intercon_1_M00_AXI_AWID),
.M00_AXI_awlen(axi_mem_intercon_1_M00_AXI_AWLEN),
.M00_AXI_awlock(axi_mem_intercon_1_M00_AXI_AWLOCK),
.M00_AXI_awprot(axi_mem_intercon_1_M00_AXI_AWPROT),
.M00_AXI_awready(axi_mem_intercon_1_M00_AXI_AWREADY),
.M00_AXI_awsize(axi_mem_intercon_1_M00_AXI_AWSIZE),
.M00_AXI_awvalid(axi_mem_intercon_1_M00_AXI_AWVALID),
.M00_AXI_bid(axi_mem_intercon_1_M00_AXI_BID),
.M00_AXI_bready(axi_mem_intercon_1_M00_AXI_BREADY),
.M00_AXI_bresp(axi_mem_intercon_1_M00_AXI_BRESP),
.M00_AXI_bvalid(axi_mem_intercon_1_M00_AXI_BVALID),
.M00_AXI_rdata(axi_mem_intercon_1_M00_AXI_RDATA),
.M00_AXI_rid(axi_mem_intercon_1_M00_AXI_RID),
.M00_AXI_rlast(axi_mem_intercon_1_M00_AXI_RLAST),
.M00_AXI_rready(axi_mem_intercon_1_M00_AXI_RREADY),
.M00_AXI_rresp(axi_mem_intercon_1_M00_AXI_RRESP),
.M00_AXI_rvalid(axi_mem_intercon_1_M00_AXI_RVALID),
.M00_AXI_wdata(axi_mem_intercon_1_M00_AXI_WDATA),
.M00_AXI_wlast(axi_mem_intercon_1_M00_AXI_WLAST),
.M00_AXI_wready(axi_mem_intercon_1_M00_AXI_WREADY),
.M00_AXI_wstrb(axi_mem_intercon_1_M00_AXI_WSTRB),
.M00_AXI_wvalid(axi_mem_intercon_1_M00_AXI_WVALID),
.S00_ACLK(processing_system7_0_FCLK_CLK0),
.S00_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.S00_AXI_araddr(processing_system7_0_M_AXI_GP1_ARADDR),
.S00_AXI_arburst(processing_system7_0_M_AXI_GP1_ARBURST),
.S00_AXI_arcache(processing_system7_0_M_AXI_GP1_ARCACHE),
.S00_AXI_arid(processing_system7_0_M_AXI_GP1_ARID),
.S00_AXI_arlen(processing_system7_0_M_AXI_GP1_ARLEN),
.S00_AXI_arlock(processing_system7_0_M_AXI_GP1_ARLOCK),
.S00_AXI_arprot(processing_system7_0_M_AXI_GP1_ARPROT),
.S00_AXI_arqos(processing_system7_0_M_AXI_GP1_ARQOS),
.S00_AXI_arready(processing_system7_0_M_AXI_GP1_ARREADY),
.S00_AXI_arsize(processing_system7_0_M_AXI_GP1_ARSIZE),
.S00_AXI_arvalid(processing_system7_0_M_AXI_GP1_ARVALID),
.S00_AXI_awaddr(processing_system7_0_M_AXI_GP1_AWADDR),
.S00_AXI_awburst(processing_system7_0_M_AXI_GP1_AWBURST),
.S00_AXI_awcache(processing_system7_0_M_AXI_GP1_AWCACHE),
.S00_AXI_awid(processing_system7_0_M_AXI_GP1_AWID),
.S00_AXI_awlen(processing_system7_0_M_AXI_GP1_AWLEN),
.S00_AXI_awlock(processing_system7_0_M_AXI_GP1_AWLOCK),
.S00_AXI_awprot(processing_system7_0_M_AXI_GP1_AWPROT),
.S00_AXI_awqos(processing_system7_0_M_AXI_GP1_AWQOS),
.S00_AXI_awready(processing_system7_0_M_AXI_GP1_AWREADY),
.S00_AXI_awsize(processing_system7_0_M_AXI_GP1_AWSIZE),
.S00_AXI_awvalid(processing_system7_0_M_AXI_GP1_AWVALID),
.S00_AXI_bid(processing_system7_0_M_AXI_GP1_BID),
.S00_AXI_bready(processing_system7_0_M_AXI_GP1_BREADY),
.S00_AXI_bresp(processing_system7_0_M_AXI_GP1_BRESP),
.S00_AXI_bvalid(processing_system7_0_M_AXI_GP1_BVALID),
.S00_AXI_rdata(processing_system7_0_M_AXI_GP1_RDATA),
.S00_AXI_rid(processing_system7_0_M_AXI_GP1_RID),
.S00_AXI_rlast(processing_system7_0_M_AXI_GP1_RLAST),
.S00_AXI_rready(processing_system7_0_M_AXI_GP1_RREADY),
.S00_AXI_rresp(processing_system7_0_M_AXI_GP1_RRESP),
.S00_AXI_rvalid(processing_system7_0_M_AXI_GP1_RVALID),
.S00_AXI_wdata(processing_system7_0_M_AXI_GP1_WDATA),
.S00_AXI_wid(processing_system7_0_M_AXI_GP1_WID),
.S00_AXI_wlast(processing_system7_0_M_AXI_GP1_WLAST),
.S00_AXI_wready(processing_system7_0_M_AXI_GP1_WREADY),
.S00_AXI_wstrb(processing_system7_0_M_AXI_GP1_WSTRB),
.S00_AXI_wvalid(processing_system7_0_M_AXI_GP1_WVALID));
design_1_blk_mem_gen_0_0 blk_mem_gen_0
(.addra(axi_bram_ctrl_0_BRAM_PORTA_ADDR),
.addrb(axi_bram_ctrl_1_BRAM_PORTA_ADDR),
.clka(axi_bram_ctrl_0_BRAM_PORTA_CLK),
.clkb(axi_bram_ctrl_1_BRAM_PORTA_CLK),
.dina(axi_bram_ctrl_0_BRAM_PORTA_DIN),
.dinb(axi_bram_ctrl_1_BRAM_PORTA_DIN),
.douta(axi_bram_ctrl_0_BRAM_PORTA_DOUT),
.doutb(axi_bram_ctrl_1_BRAM_PORTA_DOUT),
.ena(axi_bram_ctrl_0_BRAM_PORTA_EN),
.enb(axi_bram_ctrl_1_BRAM_PORTA_EN),
.rsta(axi_bram_ctrl_0_BRAM_PORTA_RST),
.rstb(axi_bram_ctrl_1_BRAM_PORTA_RST),
.wea(axi_bram_ctrl_0_BRAM_PORTA_WE),
.web(axi_bram_ctrl_1_BRAM_PORTA_WE));
(* BMM_INFO_PROCESSOR = "ARM > design_1 axi_bram_ctrl_0" *)
(* KEEP_HIERARCHY = "yes" *)
design_1_processing_system7_0_0 processing_system7_0
(.DDR_Addr(DDR_addr[14:0]),
.DDR_BankAddr(DDR_ba[2:0]),
.DDR_CAS_n(DDR_cas_n),
.DDR_CKE(DDR_cke),
.DDR_CS_n(DDR_cs_n),
.DDR_Clk(DDR_ck_p),
.DDR_Clk_n(DDR_ck_n),
.DDR_DM(DDR_dm[3:0]),
.DDR_DQ(DDR_dq[31:0]),
.DDR_DQS(DDR_dqs_p[3:0]),
.DDR_DQS_n(DDR_dqs_n[3:0]),
.DDR_DRSTB(DDR_reset_n),
.DDR_ODT(DDR_odt),
.DDR_RAS_n(DDR_ras_n),
.DDR_VRN(FIXED_IO_ddr_vrn),
.DDR_VRP(FIXED_IO_ddr_vrp),
.DDR_WEB(DDR_we_n),
.FCLK_CLK0(processing_system7_0_FCLK_CLK0),
.FCLK_RESET0_N(processing_system7_0_FCLK_RESET0_N),
.MIO(FIXED_IO_mio[53:0]),
.M_AXI_GP0_ACLK(processing_system7_0_FCLK_CLK0),
.M_AXI_GP0_ARADDR(processing_system7_0_M_AXI_GP0_ARADDR),
.M_AXI_GP0_ARBURST(processing_system7_0_M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARCACHE(processing_system7_0_M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARID(processing_system7_0_M_AXI_GP0_ARID),
.M_AXI_GP0_ARLEN(processing_system7_0_M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARLOCK(processing_system7_0_M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARPROT(processing_system7_0_M_AXI_GP0_ARPROT),
.M_AXI_GP0_ARQOS(processing_system7_0_M_AXI_GP0_ARQOS),
.M_AXI_GP0_ARREADY(processing_system7_0_M_AXI_GP0_ARREADY),
.M_AXI_GP0_ARSIZE(processing_system7_0_M_AXI_GP0_ARSIZE),
.M_AXI_GP0_ARVALID(processing_system7_0_M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWADDR(processing_system7_0_M_AXI_GP0_AWADDR),
.M_AXI_GP0_AWBURST(processing_system7_0_M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWCACHE(processing_system7_0_M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWID(processing_system7_0_M_AXI_GP0_AWID),
.M_AXI_GP0_AWLEN(processing_system7_0_M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWLOCK(processing_system7_0_M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWPROT(processing_system7_0_M_AXI_GP0_AWPROT),
.M_AXI_GP0_AWQOS(processing_system7_0_M_AXI_GP0_AWQOS),
.M_AXI_GP0_AWREADY(processing_system7_0_M_AXI_GP0_AWREADY),
.M_AXI_GP0_AWSIZE(processing_system7_0_M_AXI_GP0_AWSIZE),
.M_AXI_GP0_AWVALID(processing_system7_0_M_AXI_GP0_AWVALID),
.M_AXI_GP0_BID(processing_system7_0_M_AXI_GP0_BID),
.M_AXI_GP0_BREADY(processing_system7_0_M_AXI_GP0_BREADY),
.M_AXI_GP0_BRESP(processing_system7_0_M_AXI_GP0_BRESP),
.M_AXI_GP0_BVALID(processing_system7_0_M_AXI_GP0_BVALID),
.M_AXI_GP0_RDATA(processing_system7_0_M_AXI_GP0_RDATA),
.M_AXI_GP0_RID(processing_system7_0_M_AXI_GP0_RID),
.M_AXI_GP0_RLAST(processing_system7_0_M_AXI_GP0_RLAST),
.M_AXI_GP0_RREADY(processing_system7_0_M_AXI_GP0_RREADY),
.M_AXI_GP0_RRESP(processing_system7_0_M_AXI_GP0_RRESP),
.M_AXI_GP0_RVALID(processing_system7_0_M_AXI_GP0_RVALID),
.M_AXI_GP0_WDATA(processing_system7_0_M_AXI_GP0_WDATA),
.M_AXI_GP0_WID(processing_system7_0_M_AXI_GP0_WID),
.M_AXI_GP0_WLAST(processing_system7_0_M_AXI_GP0_WLAST),
.M_AXI_GP0_WREADY(processing_system7_0_M_AXI_GP0_WREADY),
.M_AXI_GP0_WSTRB(processing_system7_0_M_AXI_GP0_WSTRB),
.M_AXI_GP0_WVALID(processing_system7_0_M_AXI_GP0_WVALID),
.M_AXI_GP1_ACLK(processing_system7_0_FCLK_CLK0),
.M_AXI_GP1_ARADDR(processing_system7_0_M_AXI_GP1_ARADDR),
.M_AXI_GP1_ARBURST(processing_system7_0_M_AXI_GP1_ARBURST),
.M_AXI_GP1_ARCACHE(processing_system7_0_M_AXI_GP1_ARCACHE),
.M_AXI_GP1_ARID(processing_system7_0_M_AXI_GP1_ARID),
.M_AXI_GP1_ARLEN(processing_system7_0_M_AXI_GP1_ARLEN),
.M_AXI_GP1_ARLOCK(processing_system7_0_M_AXI_GP1_ARLOCK),
.M_AXI_GP1_ARPROT(processing_system7_0_M_AXI_GP1_ARPROT),
.M_AXI_GP1_ARQOS(processing_system7_0_M_AXI_GP1_ARQOS),
.M_AXI_GP1_ARREADY(processing_system7_0_M_AXI_GP1_ARREADY),
.M_AXI_GP1_ARSIZE(processing_system7_0_M_AXI_GP1_ARSIZE),
.M_AXI_GP1_ARVALID(processing_system7_0_M_AXI_GP1_ARVALID),
.M_AXI_GP1_AWADDR(processing_system7_0_M_AXI_GP1_AWADDR),
.M_AXI_GP1_AWBURST(processing_system7_0_M_AXI_GP1_AWBURST),
.M_AXI_GP1_AWCACHE(processing_system7_0_M_AXI_GP1_AWCACHE),
.M_AXI_GP1_AWID(processing_system7_0_M_AXI_GP1_AWID),
.M_AXI_GP1_AWLEN(processing_system7_0_M_AXI_GP1_AWLEN),
.M_AXI_GP1_AWLOCK(processing_system7_0_M_AXI_GP1_AWLOCK),
.M_AXI_GP1_AWPROT(processing_system7_0_M_AXI_GP1_AWPROT),
.M_AXI_GP1_AWQOS(processing_system7_0_M_AXI_GP1_AWQOS),
.M_AXI_GP1_AWREADY(processing_system7_0_M_AXI_GP1_AWREADY),
.M_AXI_GP1_AWSIZE(processing_system7_0_M_AXI_GP1_AWSIZE),
.M_AXI_GP1_AWVALID(processing_system7_0_M_AXI_GP1_AWVALID),
.M_AXI_GP1_BID(processing_system7_0_M_AXI_GP1_BID),
.M_AXI_GP1_BREADY(processing_system7_0_M_AXI_GP1_BREADY),
.M_AXI_GP1_BRESP(processing_system7_0_M_AXI_GP1_BRESP),
.M_AXI_GP1_BVALID(processing_system7_0_M_AXI_GP1_BVALID),
.M_AXI_GP1_RDATA(processing_system7_0_M_AXI_GP1_RDATA),
.M_AXI_GP1_RID(processing_system7_0_M_AXI_GP1_RID),
.M_AXI_GP1_RLAST(processing_system7_0_M_AXI_GP1_RLAST),
.M_AXI_GP1_RREADY(processing_system7_0_M_AXI_GP1_RREADY),
.M_AXI_GP1_RRESP(processing_system7_0_M_AXI_GP1_RRESP),
.M_AXI_GP1_RVALID(processing_system7_0_M_AXI_GP1_RVALID),
.M_AXI_GP1_WDATA(processing_system7_0_M_AXI_GP1_WDATA),
.M_AXI_GP1_WID(processing_system7_0_M_AXI_GP1_WID),
.M_AXI_GP1_WLAST(processing_system7_0_M_AXI_GP1_WLAST),
.M_AXI_GP1_WREADY(processing_system7_0_M_AXI_GP1_WREADY),
.M_AXI_GP1_WSTRB(processing_system7_0_M_AXI_GP1_WSTRB),
.M_AXI_GP1_WVALID(processing_system7_0_M_AXI_GP1_WVALID),
.PS_CLK(FIXED_IO_ps_clk),
.PS_PORB(FIXED_IO_ps_porb),
.PS_SRSTB(FIXED_IO_ps_srstb),
.USB0_VBUS_PWRFAULT(GND_1));
design_1_rst_processing_system7_0_100M_0 rst_processing_system7_0_100M
(.aux_reset_in(VCC_1),
.dcm_locked(VCC_1),
.ext_reset_in(processing_system7_0_FCLK_RESET0_N),
.interconnect_aresetn(rst_processing_system7_0_100M_interconnect_aresetn),
.mb_debug_sys_rst(GND_1),
.peripheral_aresetn(rst_processing_system7_0_100M_peripheral_aresetn),
.slowest_sync_clk(processing_system7_0_FCLK_CLK0));
endmodule
module design_1_axi_mem_intercon_0
(ACLK,
ARESETN,
M00_ACLK,
M00_ARESETN,
M00_AXI_araddr,
M00_AXI_arburst,
M00_AXI_arcache,
M00_AXI_arid,
M00_AXI_arlen,
M00_AXI_arlock,
M00_AXI_arprot,
M00_AXI_arready,
M00_AXI_arsize,
M00_AXI_arvalid,
M00_AXI_awaddr,
M00_AXI_awburst,
M00_AXI_awcache,
M00_AXI_awid,
M00_AXI_awlen,
M00_AXI_awlock,
M00_AXI_awprot,
M00_AXI_awready,
M00_AXI_awsize,
M00_AXI_awvalid,
M00_AXI_bid,
M00_AXI_bready,
M00_AXI_bresp,
M00_AXI_bvalid,
M00_AXI_rdata,
M00_AXI_rid,
M00_AXI_rlast,
M00_AXI_rready,
M00_AXI_rresp,
M00_AXI_rvalid,
M00_AXI_wdata,
M00_AXI_wlast,
M00_AXI_wready,
M00_AXI_wstrb,
M00_AXI_wvalid,
S00_ACLK,
S00_ARESETN,
S00_AXI_araddr,
S00_AXI_arburst,
S00_AXI_arcache,
S00_AXI_arid,
S00_AXI_arlen,
S00_AXI_arlock,
S00_AXI_arprot,
S00_AXI_arqos,
S00_AXI_arready,
S00_AXI_arsize,
S00_AXI_arvalid,
S00_AXI_awaddr,
S00_AXI_awburst,
S00_AXI_awcache,
S00_AXI_awid,
S00_AXI_awlen,
S00_AXI_awlock,
S00_AXI_awprot,
S00_AXI_awqos,
S00_AXI_awready,
S00_AXI_awsize,
S00_AXI_awvalid,
S00_AXI_bid,
S00_AXI_bready,
S00_AXI_bresp,
S00_AXI_bvalid,
S00_AXI_rdata,
S00_AXI_rid,
S00_AXI_rlast,
S00_AXI_rready,
S00_AXI_rresp,
S00_AXI_rvalid,
S00_AXI_wdata,
S00_AXI_wid,
S00_AXI_wlast,
S00_AXI_wready,
S00_AXI_wstrb,
S00_AXI_wvalid);
input ACLK;
input [0:0]ARESETN;
input M00_ACLK;
input [0:0]M00_ARESETN;
output [12:0]M00_AXI_araddr;
output [1:0]M00_AXI_arburst;
output [3:0]M00_AXI_arcache;
output [11:0]M00_AXI_arid;
output [7:0]M00_AXI_arlen;
output [0:0]M00_AXI_arlock;
output [2:0]M00_AXI_arprot;
input M00_AXI_arready;
output [2:0]M00_AXI_arsize;
output M00_AXI_arvalid;
output [12:0]M00_AXI_awaddr;
output [1:0]M00_AXI_awburst;
output [3:0]M00_AXI_awcache;
output [11:0]M00_AXI_awid;
output [7:0]M00_AXI_awlen;
output [0:0]M00_AXI_awlock;
output [2:0]M00_AXI_awprot;
input M00_AXI_awready;
output [2:0]M00_AXI_awsize;
output M00_AXI_awvalid;
input [11:0]M00_AXI_bid;
output M00_AXI_bready;
input [1:0]M00_AXI_bresp;
input M00_AXI_bvalid;
input [31:0]M00_AXI_rdata;
input [11:0]M00_AXI_rid;
input M00_AXI_rlast;
output M00_AXI_rready;
input [1:0]M00_AXI_rresp;
input M00_AXI_rvalid;
output [31:0]M00_AXI_wdata;
output M00_AXI_wlast;
input M00_AXI_wready;
output [3:0]M00_AXI_wstrb;
output M00_AXI_wvalid;
input S00_ACLK;
input [0:0]S00_ARESETN;
input [31:0]S00_AXI_araddr;
input [1:0]S00_AXI_arburst;
input [3:0]S00_AXI_arcache;
input [11:0]S00_AXI_arid;
input [3:0]S00_AXI_arlen;
input [1:0]S00_AXI_arlock;
input [2:0]S00_AXI_arprot;
input [3:0]S00_AXI_arqos;
output S00_AXI_arready;
input [2:0]S00_AXI_arsize;
input S00_AXI_arvalid;
input [31:0]S00_AXI_awaddr;
input [1:0]S00_AXI_awburst;
input [3:0]S00_AXI_awcache;
input [11:0]S00_AXI_awid;
input [3:0]S00_AXI_awlen;
input [1:0]S00_AXI_awlock;
input [2:0]S00_AXI_awprot;
input [3:0]S00_AXI_awqos;
output S00_AXI_awready;
input [2:0]S00_AXI_awsize;
input S00_AXI_awvalid;
output [11:0]S00_AXI_bid;
input S00_AXI_bready;
output [1:0]S00_AXI_bresp;
output S00_AXI_bvalid;
output [31:0]S00_AXI_rdata;
output [11:0]S00_AXI_rid;
output S00_AXI_rlast;
input S00_AXI_rready;
output [1:0]S00_AXI_rresp;
output S00_AXI_rvalid;
input [31:0]S00_AXI_wdata;
input [11:0]S00_AXI_wid;
input S00_AXI_wlast;
output S00_AXI_wready;
input [3:0]S00_AXI_wstrb;
input S00_AXI_wvalid;
wire S00_ACLK_1;
wire [0:0]S00_ARESETN_1;
wire axi_mem_intercon_ACLK_net;
wire [0:0]axi_mem_intercon_ARESETN_net;
wire [31:0]axi_mem_intercon_to_s00_couplers_ARADDR;
wire [1:0]axi_mem_intercon_to_s00_couplers_ARBURST;
wire [3:0]axi_mem_intercon_to_s00_couplers_ARCACHE;
wire [11:0]axi_mem_intercon_to_s00_couplers_ARID;
wire [3:0]axi_mem_intercon_to_s00_couplers_ARLEN;
wire [1:0]axi_mem_intercon_to_s00_couplers_ARLOCK;
wire [2:0]axi_mem_intercon_to_s00_couplers_ARPROT;
wire [3:0]axi_mem_intercon_to_s00_couplers_ARQOS;
wire axi_mem_intercon_to_s00_couplers_ARREADY;
wire [2:0]axi_mem_intercon_to_s00_couplers_ARSIZE;
wire axi_mem_intercon_to_s00_couplers_ARVALID;
wire [31:0]axi_mem_intercon_to_s00_couplers_AWADDR;
wire [1:0]axi_mem_intercon_to_s00_couplers_AWBURST;
wire [3:0]axi_mem_intercon_to_s00_couplers_AWCACHE;
wire [11:0]axi_mem_intercon_to_s00_couplers_AWID;
wire [3:0]axi_mem_intercon_to_s00_couplers_AWLEN;
wire [1:0]axi_mem_intercon_to_s00_couplers_AWLOCK;
wire [2:0]axi_mem_intercon_to_s00_couplers_AWPROT;
wire [3:0]axi_mem_intercon_to_s00_couplers_AWQOS;
wire axi_mem_intercon_to_s00_couplers_AWREADY;
wire [2:0]axi_mem_intercon_to_s00_couplers_AWSIZE;
wire axi_mem_intercon_to_s00_couplers_AWVALID;
wire [11:0]axi_mem_intercon_to_s00_couplers_BID;
wire axi_mem_intercon_to_s00_couplers_BREADY;
wire [1:0]axi_mem_intercon_to_s00_couplers_BRESP;
wire axi_mem_intercon_to_s00_couplers_BVALID;
wire [31:0]axi_mem_intercon_to_s00_couplers_RDATA;
wire [11:0]axi_mem_intercon_to_s00_couplers_RID;
wire axi_mem_intercon_to_s00_couplers_RLAST;
wire axi_mem_intercon_to_s00_couplers_RREADY;
wire [1:0]axi_mem_intercon_to_s00_couplers_RRESP;
wire axi_mem_intercon_to_s00_couplers_RVALID;
wire [31:0]axi_mem_intercon_to_s00_couplers_WDATA;
wire [11:0]axi_mem_intercon_to_s00_couplers_WID;
wire axi_mem_intercon_to_s00_couplers_WLAST;
wire axi_mem_intercon_to_s00_couplers_WREADY;
wire [3:0]axi_mem_intercon_to_s00_couplers_WSTRB;
wire axi_mem_intercon_to_s00_couplers_WVALID;
wire [12:0]s00_couplers_to_axi_mem_intercon_ARADDR;
wire [1:0]s00_couplers_to_axi_mem_intercon_ARBURST;
wire [3:0]s00_couplers_to_axi_mem_intercon_ARCACHE;
wire [11:0]s00_couplers_to_axi_mem_intercon_ARID;
wire [7:0]s00_couplers_to_axi_mem_intercon_ARLEN;
wire [0:0]s00_couplers_to_axi_mem_intercon_ARLOCK;
wire [2:0]s00_couplers_to_axi_mem_intercon_ARPROT;
wire s00_couplers_to_axi_mem_intercon_ARREADY;
wire [2:0]s00_couplers_to_axi_mem_intercon_ARSIZE;
wire s00_couplers_to_axi_mem_intercon_ARVALID;
wire [12:0]s00_couplers_to_axi_mem_intercon_AWADDR;
wire [1:0]s00_couplers_to_axi_mem_intercon_AWBURST;
wire [3:0]s00_couplers_to_axi_mem_intercon_AWCACHE;
wire [11:0]s00_couplers_to_axi_mem_intercon_AWID;
wire [7:0]s00_couplers_to_axi_mem_intercon_AWLEN;
wire [0:0]s00_couplers_to_axi_mem_intercon_AWLOCK;
wire [2:0]s00_couplers_to_axi_mem_intercon_AWPROT;
wire s00_couplers_to_axi_mem_intercon_AWREADY;
wire [2:0]s00_couplers_to_axi_mem_intercon_AWSIZE;
wire s00_couplers_to_axi_mem_intercon_AWVALID;
wire [11:0]s00_couplers_to_axi_mem_intercon_BID;
wire s00_couplers_to_axi_mem_intercon_BREADY;
wire [1:0]s00_couplers_to_axi_mem_intercon_BRESP;
wire s00_couplers_to_axi_mem_intercon_BVALID;
wire [31:0]s00_couplers_to_axi_mem_intercon_RDATA;
wire [11:0]s00_couplers_to_axi_mem_intercon_RID;
wire s00_couplers_to_axi_mem_intercon_RLAST;
wire s00_couplers_to_axi_mem_intercon_RREADY;
wire [1:0]s00_couplers_to_axi_mem_intercon_RRESP;
wire s00_couplers_to_axi_mem_intercon_RVALID;
wire [31:0]s00_couplers_to_axi_mem_intercon_WDATA;
wire s00_couplers_to_axi_mem_intercon_WLAST;
wire s00_couplers_to_axi_mem_intercon_WREADY;
wire [3:0]s00_couplers_to_axi_mem_intercon_WSTRB;
wire s00_couplers_to_axi_mem_intercon_WVALID;
assign M00_AXI_araddr[12:0] = s00_couplers_to_axi_mem_intercon_ARADDR;
assign M00_AXI_arburst[1:0] = s00_couplers_to_axi_mem_intercon_ARBURST;
assign M00_AXI_arcache[3:0] = s00_couplers_to_axi_mem_intercon_ARCACHE;
assign M00_AXI_arid[11:0] = s00_couplers_to_axi_mem_intercon_ARID;
assign M00_AXI_arlen[7:0] = s00_couplers_to_axi_mem_intercon_ARLEN;
assign M00_AXI_arlock[0] = s00_couplers_to_axi_mem_intercon_ARLOCK;
assign M00_AXI_arprot[2:0] = s00_couplers_to_axi_mem_intercon_ARPROT;
assign M00_AXI_arsize[2:0] = s00_couplers_to_axi_mem_intercon_ARSIZE;
assign M00_AXI_arvalid = s00_couplers_to_axi_mem_intercon_ARVALID;
assign M00_AXI_awaddr[12:0] = s00_couplers_to_axi_mem_intercon_AWADDR;
assign M00_AXI_awburst[1:0] = s00_couplers_to_axi_mem_intercon_AWBURST;
assign M00_AXI_awcache[3:0] = s00_couplers_to_axi_mem_intercon_AWCACHE;
assign M00_AXI_awid[11:0] = s00_couplers_to_axi_mem_intercon_AWID;
assign M00_AXI_awlen[7:0] = s00_couplers_to_axi_mem_intercon_AWLEN;
assign M00_AXI_awlock[0] = s00_couplers_to_axi_mem_intercon_AWLOCK;
assign M00_AXI_awprot[2:0] = s00_couplers_to_axi_mem_intercon_AWPROT;
assign M00_AXI_awsize[2:0] = s00_couplers_to_axi_mem_intercon_AWSIZE;
assign M00_AXI_awvalid = s00_couplers_to_axi_mem_intercon_AWVALID;
assign M00_AXI_bready = s00_couplers_to_axi_mem_intercon_BREADY;
assign M00_AXI_rready = s00_couplers_to_axi_mem_intercon_RREADY;
assign M00_AXI_wdata[31:0] = s00_couplers_to_axi_mem_intercon_WDATA;
assign M00_AXI_wlast = s00_couplers_to_axi_mem_intercon_WLAST;
assign M00_AXI_wstrb[3:0] = s00_couplers_to_axi_mem_intercon_WSTRB;
assign M00_AXI_wvalid = s00_couplers_to_axi_mem_intercon_WVALID;
assign S00_ACLK_1 = S00_ACLK;
assign S00_ARESETN_1 = S00_ARESETN[0];
assign S00_AXI_arready = axi_mem_intercon_to_s00_couplers_ARREADY;
assign S00_AXI_awready = axi_mem_intercon_to_s00_couplers_AWREADY;
assign S00_AXI_bid[11:0] = axi_mem_intercon_to_s00_couplers_BID;
assign S00_AXI_bresp[1:0] = axi_mem_intercon_to_s00_couplers_BRESP;
assign S00_AXI_bvalid = axi_mem_intercon_to_s00_couplers_BVALID;
assign S00_AXI_rdata[31:0] = axi_mem_intercon_to_s00_couplers_RDATA;
assign S00_AXI_rid[11:0] = axi_mem_intercon_to_s00_couplers_RID;
assign S00_AXI_rlast = axi_mem_intercon_to_s00_couplers_RLAST;
assign S00_AXI_rresp[1:0] = axi_mem_intercon_to_s00_couplers_RRESP;
assign S00_AXI_rvalid = axi_mem_intercon_to_s00_couplers_RVALID;
assign S00_AXI_wready = axi_mem_intercon_to_s00_couplers_WREADY;
assign axi_mem_intercon_ACLK_net = M00_ACLK;
assign axi_mem_intercon_ARESETN_net = M00_ARESETN[0];
assign axi_mem_intercon_to_s00_couplers_ARADDR = S00_AXI_araddr[31:0];
assign axi_mem_intercon_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];
assign axi_mem_intercon_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];
assign axi_mem_intercon_to_s00_couplers_ARID = S00_AXI_arid[11:0];
assign axi_mem_intercon_to_s00_couplers_ARLEN = S00_AXI_arlen[3:0];
assign axi_mem_intercon_to_s00_couplers_ARLOCK = S00_AXI_arlock[1:0];
assign axi_mem_intercon_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];
assign axi_mem_intercon_to_s00_couplers_ARQOS = S00_AXI_arqos[3:0];
assign axi_mem_intercon_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];
assign axi_mem_intercon_to_s00_couplers_ARVALID = S00_AXI_arvalid;
assign axi_mem_intercon_to_s00_couplers_AWADDR = S00_AXI_awaddr[31:0];
assign axi_mem_intercon_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];
assign axi_mem_intercon_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];
assign axi_mem_intercon_to_s00_couplers_AWID = S00_AXI_awid[11:0];
assign axi_mem_intercon_to_s00_couplers_AWLEN = S00_AXI_awlen[3:0];
assign axi_mem_intercon_to_s00_couplers_AWLOCK = S00_AXI_awlock[1:0];
assign axi_mem_intercon_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];
assign axi_mem_intercon_to_s00_couplers_AWQOS = S00_AXI_awqos[3:0];
assign axi_mem_intercon_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];
assign axi_mem_intercon_to_s00_couplers_AWVALID = S00_AXI_awvalid;
assign axi_mem_intercon_to_s00_couplers_BREADY = S00_AXI_bready;
assign axi_mem_intercon_to_s00_couplers_RREADY = S00_AXI_rready;
assign axi_mem_intercon_to_s00_couplers_WDATA = S00_AXI_wdata[31:0];
assign axi_mem_intercon_to_s00_couplers_WID = S00_AXI_wid[11:0];
assign axi_mem_intercon_to_s00_couplers_WLAST = S00_AXI_wlast;
assign axi_mem_intercon_to_s00_couplers_WSTRB = S00_AXI_wstrb[3:0];
assign axi_mem_intercon_to_s00_couplers_WVALID = S00_AXI_wvalid;
assign s00_couplers_to_axi_mem_intercon_ARREADY = M00_AXI_arready;
assign s00_couplers_to_axi_mem_intercon_AWREADY = M00_AXI_awready;
assign s00_couplers_to_axi_mem_intercon_BID = M00_AXI_bid[11:0];
assign s00_couplers_to_axi_mem_intercon_BRESP = M00_AXI_bresp[1:0];
assign s00_couplers_to_axi_mem_intercon_BVALID = M00_AXI_bvalid;
assign s00_couplers_to_axi_mem_intercon_RDATA = M00_AXI_rdata[31:0];
assign s00_couplers_to_axi_mem_intercon_RID = M00_AXI_rid[11:0];
assign s00_couplers_to_axi_mem_intercon_RLAST = M00_AXI_rlast;
assign s00_couplers_to_axi_mem_intercon_RRESP = M00_AXI_rresp[1:0];
assign s00_couplers_to_axi_mem_intercon_RVALID = M00_AXI_rvalid;
assign s00_couplers_to_axi_mem_intercon_WREADY = M00_AXI_wready;
s00_couplers_imp_7HNO1D s00_couplers
(.M_ACLK(axi_mem_intercon_ACLK_net),
.M_ARESETN(axi_mem_intercon_ARESETN_net),
.M_AXI_araddr(s00_couplers_to_axi_mem_intercon_ARADDR),
.M_AXI_arburst(s00_couplers_to_axi_mem_intercon_ARBURST),
.M_AXI_arcache(s00_couplers_to_axi_mem_intercon_ARCACHE),
.M_AXI_arid(s00_couplers_to_axi_mem_intercon_ARID),
.M_AXI_arlen(s00_couplers_to_axi_mem_intercon_ARLEN),
.M_AXI_arlock(s00_couplers_to_axi_mem_intercon_ARLOCK),
.M_AXI_arprot(s00_couplers_to_axi_mem_intercon_ARPROT),
.M_AXI_arready(s00_couplers_to_axi_mem_intercon_ARREADY),
.M_AXI_arsize(s00_couplers_to_axi_mem_intercon_ARSIZE),
.M_AXI_arvalid(s00_couplers_to_axi_mem_intercon_ARVALID),
.M_AXI_awaddr(s00_couplers_to_axi_mem_intercon_AWADDR),
.M_AXI_awburst(s00_couplers_to_axi_mem_intercon_AWBURST),
.M_AXI_awcache(s00_couplers_to_axi_mem_intercon_AWCACHE),
.M_AXI_awid(s00_couplers_to_axi_mem_intercon_AWID),
.M_AXI_awlen(s00_couplers_to_axi_mem_intercon_AWLEN),
.M_AXI_awlock(s00_couplers_to_axi_mem_intercon_AWLOCK),
.M_AXI_awprot(s00_couplers_to_axi_mem_intercon_AWPROT),
.M_AXI_awready(s00_couplers_to_axi_mem_intercon_AWREADY),
.M_AXI_awsize(s00_couplers_to_axi_mem_intercon_AWSIZE),
.M_AXI_awvalid(s00_couplers_to_axi_mem_intercon_AWVALID),
.M_AXI_bid(s00_couplers_to_axi_mem_intercon_BID),
.M_AXI_bready(s00_couplers_to_axi_mem_intercon_BREADY),
.M_AXI_bresp(s00_couplers_to_axi_mem_intercon_BRESP),
.M_AXI_bvalid(s00_couplers_to_axi_mem_intercon_BVALID),
.M_AXI_rdata(s00_couplers_to_axi_mem_intercon_RDATA),
.M_AXI_rid(s00_couplers_to_axi_mem_intercon_RID),
.M_AXI_rlast(s00_couplers_to_axi_mem_intercon_RLAST),
.M_AXI_rready(s00_couplers_to_axi_mem_intercon_RREADY),
.M_AXI_rresp(s00_couplers_to_axi_mem_intercon_RRESP),
.M_AXI_rvalid(s00_couplers_to_axi_mem_intercon_RVALID),
.M_AXI_wdata(s00_couplers_to_axi_mem_intercon_WDATA),
.M_AXI_wlast(s00_couplers_to_axi_mem_intercon_WLAST),
.M_AXI_wready(s00_couplers_to_axi_mem_intercon_WREADY),
.M_AXI_wstrb(s00_couplers_to_axi_mem_intercon_WSTRB),
.M_AXI_wvalid(s00_couplers_to_axi_mem_intercon_WVALID),
.S_ACLK(S00_ACLK_1),
.S_ARESETN(S00_ARESETN_1),
.S_AXI_araddr(axi_mem_intercon_to_s00_couplers_ARADDR),
.S_AXI_arburst(axi_mem_intercon_to_s00_couplers_ARBURST),
.S_AXI_arcache(axi_mem_intercon_to_s00_couplers_ARCACHE),
.S_AXI_arid(axi_mem_intercon_to_s00_couplers_ARID),
.S_AXI_arlen(axi_mem_intercon_to_s00_couplers_ARLEN),
.S_AXI_arlock(axi_mem_intercon_to_s00_couplers_ARLOCK),
.S_AXI_arprot(axi_mem_intercon_to_s00_couplers_ARPROT),
.S_AXI_arqos(axi_mem_intercon_to_s00_couplers_ARQOS),
.S_AXI_arready(axi_mem_intercon_to_s00_couplers_ARREADY),
.S_AXI_arsize(axi_mem_intercon_to_s00_couplers_ARSIZE),
.S_AXI_arvalid(axi_mem_intercon_to_s00_couplers_ARVALID),
.S_AXI_awaddr(axi_mem_intercon_to_s00_couplers_AWADDR),
.S_AXI_awburst(axi_mem_intercon_to_s00_couplers_AWBURST),
.S_AXI_awcache(axi_mem_intercon_to_s00_couplers_AWCACHE),
.S_AXI_awid(axi_mem_intercon_to_s00_couplers_AWID),
.S_AXI_awlen(axi_mem_intercon_to_s00_couplers_AWLEN),
.S_AXI_awlock(axi_mem_intercon_to_s00_couplers_AWLOCK),
.S_AXI_awprot(axi_mem_intercon_to_s00_couplers_AWPROT),
.S_AXI_awqos(axi_mem_intercon_to_s00_couplers_AWQOS),
.S_AXI_awready(axi_mem_intercon_to_s00_couplers_AWREADY),
.S_AXI_awsize(axi_mem_intercon_to_s00_couplers_AWSIZE),
.S_AXI_awvalid(axi_mem_intercon_to_s00_couplers_AWVALID),
.S_AXI_bid(axi_mem_intercon_to_s00_couplers_BID),
.S_AXI_bready(axi_mem_intercon_to_s00_couplers_BREADY),
.S_AXI_bresp(axi_mem_intercon_to_s00_couplers_BRESP),
.S_AXI_bvalid(axi_mem_intercon_to_s00_couplers_BVALID),
.S_AXI_rdata(axi_mem_intercon_to_s00_couplers_RDATA),
.S_AXI_rid(axi_mem_intercon_to_s00_couplers_RID),
.S_AXI_rlast(axi_mem_intercon_to_s00_couplers_RLAST),
.S_AXI_rready(axi_mem_intercon_to_s00_couplers_RREADY),
.S_AXI_rresp(axi_mem_intercon_to_s00_couplers_RRESP),
.S_AXI_rvalid(axi_mem_intercon_to_s00_couplers_RVALID),
.S_AXI_wdata(axi_mem_intercon_to_s00_couplers_WDATA),
.S_AXI_wid(axi_mem_intercon_to_s00_couplers_WID),
.S_AXI_wlast(axi_mem_intercon_to_s00_couplers_WLAST),
.S_AXI_wready(axi_mem_intercon_to_s00_couplers_WREADY),
.S_AXI_wstrb(axi_mem_intercon_to_s00_couplers_WSTRB),
.S_AXI_wvalid(axi_mem_intercon_to_s00_couplers_WVALID));
endmodule
module design_1_axi_mem_intercon_1_0
(ACLK,
ARESETN,
M00_ACLK,
M00_ARESETN,
M00_AXI_araddr,
M00_AXI_arburst,
M00_AXI_arcache,
M00_AXI_arid,
M00_AXI_arlen,
M00_AXI_arlock,
M00_AXI_arprot,
M00_AXI_arready,
M00_AXI_arsize,
M00_AXI_arvalid,
M00_AXI_awaddr,
M00_AXI_awburst,
M00_AXI_awcache,
M00_AXI_awid,
M00_AXI_awlen,
M00_AXI_awlock,
M00_AXI_awprot,
M00_AXI_awready,
M00_AXI_awsize,
M00_AXI_awvalid,
M00_AXI_bid,
M00_AXI_bready,
M00_AXI_bresp,
M00_AXI_bvalid,
M00_AXI_rdata,
M00_AXI_rid,
M00_AXI_rlast,
M00_AXI_rready,
M00_AXI_rresp,
M00_AXI_rvalid,
M00_AXI_wdata,
M00_AXI_wlast,
M00_AXI_wready,
M00_AXI_wstrb,
M00_AXI_wvalid,
S00_ACLK,
S00_ARESETN,
S00_AXI_araddr,
S00_AXI_arburst,
S00_AXI_arcache,
S00_AXI_arid,
S00_AXI_arlen,
S00_AXI_arlock,
S00_AXI_arprot,
S00_AXI_arqos,
S00_AXI_arready,
S00_AXI_arsize,
S00_AXI_arvalid,
S00_AXI_awaddr,
S00_AXI_awburst,
S00_AXI_awcache,
S00_AXI_awid,
S00_AXI_awlen,
S00_AXI_awlock,
S00_AXI_awprot,
S00_AXI_awqos,
S00_AXI_awready,
S00_AXI_awsize,
S00_AXI_awvalid,
S00_AXI_bid,
S00_AXI_bready,
S00_AXI_bresp,
S00_AXI_bvalid,
S00_AXI_rdata,
S00_AXI_rid,
S00_AXI_rlast,
S00_AXI_rready,
S00_AXI_rresp,
S00_AXI_rvalid,
S00_AXI_wdata,
S00_AXI_wid,
S00_AXI_wlast,
S00_AXI_wready,
S00_AXI_wstrb,
S00_AXI_wvalid);
input ACLK;
input [0:0]ARESETN;
input M00_ACLK;
input [0:0]M00_ARESETN;
output [12:0]M00_AXI_araddr;
output [1:0]M00_AXI_arburst;
output [3:0]M00_AXI_arcache;
output [11:0]M00_AXI_arid;
output [7:0]M00_AXI_arlen;
output [0:0]M00_AXI_arlock;
output [2:0]M00_AXI_arprot;
input M00_AXI_arready;
output [2:0]M00_AXI_arsize;
output M00_AXI_arvalid;
output [12:0]M00_AXI_awaddr;
output [1:0]M00_AXI_awburst;
output [3:0]M00_AXI_awcache;
output [11:0]M00_AXI_awid;
output [7:0]M00_AXI_awlen;
output [0:0]M00_AXI_awlock;
output [2:0]M00_AXI_awprot;
input M00_AXI_awready;
output [2:0]M00_AXI_awsize;
output M00_AXI_awvalid;
input [11:0]M00_AXI_bid;
output M00_AXI_bready;
input [1:0]M00_AXI_bresp;
input M00_AXI_bvalid;
input [31:0]M00_AXI_rdata;
input [11:0]M00_AXI_rid;
input M00_AXI_rlast;
output M00_AXI_rready;
input [1:0]M00_AXI_rresp;
input M00_AXI_rvalid;
output [31:0]M00_AXI_wdata;
output M00_AXI_wlast;
input M00_AXI_wready;
output [3:0]M00_AXI_wstrb;
output M00_AXI_wvalid;
input S00_ACLK;
input [0:0]S00_ARESETN;
input [31:0]S00_AXI_araddr;
input [1:0]S00_AXI_arburst;
input [3:0]S00_AXI_arcache;
input [11:0]S00_AXI_arid;
input [3:0]S00_AXI_arlen;
input [1:0]S00_AXI_arlock;
input [2:0]S00_AXI_arprot;
input [3:0]S00_AXI_arqos;
output S00_AXI_arready;
input [2:0]S00_AXI_arsize;
input S00_AXI_arvalid;
input [31:0]S00_AXI_awaddr;
input [1:0]S00_AXI_awburst;
input [3:0]S00_AXI_awcache;
input [11:0]S00_AXI_awid;
input [3:0]S00_AXI_awlen;
input [1:0]S00_AXI_awlock;
input [2:0]S00_AXI_awprot;
input [3:0]S00_AXI_awqos;
output S00_AXI_awready;
input [2:0]S00_AXI_awsize;
input S00_AXI_awvalid;
output [11:0]S00_AXI_bid;
input S00_AXI_bready;
output [1:0]S00_AXI_bresp;
output S00_AXI_bvalid;
output [31:0]S00_AXI_rdata;
output [11:0]S00_AXI_rid;
output S00_AXI_rlast;
input S00_AXI_rready;
output [1:0]S00_AXI_rresp;
output S00_AXI_rvalid;
input [31:0]S00_AXI_wdata;
input [11:0]S00_AXI_wid;
input S00_AXI_wlast;
output S00_AXI_wready;
input [3:0]S00_AXI_wstrb;
input S00_AXI_wvalid;
wire S00_ACLK_1;
wire [0:0]S00_ARESETN_1;
wire axi_mem_intercon_1_ACLK_net;
wire [0:0]axi_mem_intercon_1_ARESETN_net;
wire [31:0]axi_mem_intercon_1_to_s00_couplers_ARADDR;
wire [1:0]axi_mem_intercon_1_to_s00_couplers_ARBURST;
wire [3:0]axi_mem_intercon_1_to_s00_couplers_ARCACHE;
wire [11:0]axi_mem_intercon_1_to_s00_couplers_ARID;
wire [3:0]axi_mem_intercon_1_to_s00_couplers_ARLEN;
wire [1:0]axi_mem_intercon_1_to_s00_couplers_ARLOCK;
wire [2:0]axi_mem_intercon_1_to_s00_couplers_ARPROT;
wire [3:0]axi_mem_intercon_1_to_s00_couplers_ARQOS;
wire axi_mem_intercon_1_to_s00_couplers_ARREADY;
wire [2:0]axi_mem_intercon_1_to_s00_couplers_ARSIZE;
wire axi_mem_intercon_1_to_s00_couplers_ARVALID;
wire [31:0]axi_mem_intercon_1_to_s00_couplers_AWADDR;
wire [1:0]axi_mem_intercon_1_to_s00_couplers_AWBURST;
wire [3:0]axi_mem_intercon_1_to_s00_couplers_AWCACHE;
wire [11:0]axi_mem_intercon_1_to_s00_couplers_AWID;
wire [3:0]axi_mem_intercon_1_to_s00_couplers_AWLEN;
wire [1:0]axi_mem_intercon_1_to_s00_couplers_AWLOCK;
wire [2:0]axi_mem_intercon_1_to_s00_couplers_AWPROT;
wire [3:0]axi_mem_intercon_1_to_s00_couplers_AWQOS;
wire axi_mem_intercon_1_to_s00_couplers_AWREADY;
wire [2:0]axi_mem_intercon_1_to_s00_couplers_AWSIZE;
wire axi_mem_intercon_1_to_s00_couplers_AWVALID;
wire [11:0]axi_mem_intercon_1_to_s00_couplers_BID;
wire axi_mem_intercon_1_to_s00_couplers_BREADY;
wire [1:0]axi_mem_intercon_1_to_s00_couplers_BRESP;
wire axi_mem_intercon_1_to_s00_couplers_BVALID;
wire [31:0]axi_mem_intercon_1_to_s00_couplers_RDATA;
wire [11:0]axi_mem_intercon_1_to_s00_couplers_RID;
wire axi_mem_intercon_1_to_s00_couplers_RLAST;
wire axi_mem_intercon_1_to_s00_couplers_RREADY;
wire [1:0]axi_mem_intercon_1_to_s00_couplers_RRESP;
wire axi_mem_intercon_1_to_s00_couplers_RVALID;
wire [31:0]axi_mem_intercon_1_to_s00_couplers_WDATA;
wire [11:0]axi_mem_intercon_1_to_s00_couplers_WID;
wire axi_mem_intercon_1_to_s00_couplers_WLAST;
wire axi_mem_intercon_1_to_s00_couplers_WREADY;
wire [3:0]axi_mem_intercon_1_to_s00_couplers_WSTRB;
wire axi_mem_intercon_1_to_s00_couplers_WVALID;
wire [12:0]s00_couplers_to_axi_mem_intercon_1_ARADDR;
wire [1:0]s00_couplers_to_axi_mem_intercon_1_ARBURST;
wire [3:0]s00_couplers_to_axi_mem_intercon_1_ARCACHE;
wire [11:0]s00_couplers_to_axi_mem_intercon_1_ARID;
wire [7:0]s00_couplers_to_axi_mem_intercon_1_ARLEN;
wire [0:0]s00_couplers_to_axi_mem_intercon_1_ARLOCK;
wire [2:0]s00_couplers_to_axi_mem_intercon_1_ARPROT;
wire s00_couplers_to_axi_mem_intercon_1_ARREADY;
wire [2:0]s00_couplers_to_axi_mem_intercon_1_ARSIZE;
wire s00_couplers_to_axi_mem_intercon_1_ARVALID;
wire [12:0]s00_couplers_to_axi_mem_intercon_1_AWADDR;
wire [1:0]s00_couplers_to_axi_mem_intercon_1_AWBURST;
wire [3:0]s00_couplers_to_axi_mem_intercon_1_AWCACHE;
wire [11:0]s00_couplers_to_axi_mem_intercon_1_AWID;
wire [7:0]s00_couplers_to_axi_mem_intercon_1_AWLEN;
wire [0:0]s00_couplers_to_axi_mem_intercon_1_AWLOCK;
wire [2:0]s00_couplers_to_axi_mem_intercon_1_AWPROT;
wire s00_couplers_to_axi_mem_intercon_1_AWREADY;
wire [2:0]s00_couplers_to_axi_mem_intercon_1_AWSIZE;
wire s00_couplers_to_axi_mem_intercon_1_AWVALID;
wire [11:0]s00_couplers_to_axi_mem_intercon_1_BID;
wire s00_couplers_to_axi_mem_intercon_1_BREADY;
wire [1:0]s00_couplers_to_axi_mem_intercon_1_BRESP;
wire s00_couplers_to_axi_mem_intercon_1_BVALID;
wire [31:0]s00_couplers_to_axi_mem_intercon_1_RDATA;
wire [11:0]s00_couplers_to_axi_mem_intercon_1_RID;
wire s00_couplers_to_axi_mem_intercon_1_RLAST;
wire s00_couplers_to_axi_mem_intercon_1_RREADY;
wire [1:0]s00_couplers_to_axi_mem_intercon_1_RRESP;
wire s00_couplers_to_axi_mem_intercon_1_RVALID;
wire [31:0]s00_couplers_to_axi_mem_intercon_1_WDATA;
wire s00_couplers_to_axi_mem_intercon_1_WLAST;
wire s00_couplers_to_axi_mem_intercon_1_WREADY;
wire [3:0]s00_couplers_to_axi_mem_intercon_1_WSTRB;
wire s00_couplers_to_axi_mem_intercon_1_WVALID;
assign M00_AXI_araddr[12:0] = s00_couplers_to_axi_mem_intercon_1_ARADDR;
assign M00_AXI_arburst[1:0] = s00_couplers_to_axi_mem_intercon_1_ARBURST;
assign M00_AXI_arcache[3:0] = s00_couplers_to_axi_mem_intercon_1_ARCACHE;
assign M00_AXI_arid[11:0] = s00_couplers_to_axi_mem_intercon_1_ARID;
assign M00_AXI_arlen[7:0] = s00_couplers_to_axi_mem_intercon_1_ARLEN;
assign M00_AXI_arlock[0] = s00_couplers_to_axi_mem_intercon_1_ARLOCK;
assign M00_AXI_arprot[2:0] = s00_couplers_to_axi_mem_intercon_1_ARPROT;
assign M00_AXI_arsize[2:0] = s00_couplers_to_axi_mem_intercon_1_ARSIZE;
assign M00_AXI_arvalid = s00_couplers_to_axi_mem_intercon_1_ARVALID;
assign M00_AXI_awaddr[12:0] = s00_couplers_to_axi_mem_intercon_1_AWADDR;
assign M00_AXI_awburst[1:0] = s00_couplers_to_axi_mem_intercon_1_AWBURST;
assign M00_AXI_awcache[3:0] = s00_couplers_to_axi_mem_intercon_1_AWCACHE;
assign M00_AXI_awid[11:0] = s00_couplers_to_axi_mem_intercon_1_AWID;
assign M00_AXI_awlen[7:0] = s00_couplers_to_axi_mem_intercon_1_AWLEN;
assign M00_AXI_awlock[0] = s00_couplers_to_axi_mem_intercon_1_AWLOCK;
assign M00_AXI_awprot[2:0] = s00_couplers_to_axi_mem_intercon_1_AWPROT;
assign M00_AXI_awsize[2:0] = s00_couplers_to_axi_mem_intercon_1_AWSIZE;
assign M00_AXI_awvalid = s00_couplers_to_axi_mem_intercon_1_AWVALID;
assign M00_AXI_bready = s00_couplers_to_axi_mem_intercon_1_BREADY;
assign M00_AXI_rready = s00_couplers_to_axi_mem_intercon_1_RREADY;
assign M00_AXI_wdata[31:0] = s00_couplers_to_axi_mem_intercon_1_WDATA;
assign M00_AXI_wlast = s00_couplers_to_axi_mem_intercon_1_WLAST;
assign M00_AXI_wstrb[3:0] = s00_couplers_to_axi_mem_intercon_1_WSTRB;
assign M00_AXI_wvalid = s00_couplers_to_axi_mem_intercon_1_WVALID;
assign S00_ACLK_1 = S00_ACLK;
assign S00_ARESETN_1 = S00_ARESETN[0];
assign S00_AXI_arready = axi_mem_intercon_1_to_s00_couplers_ARREADY;
assign S00_AXI_awready = axi_mem_intercon_1_to_s00_couplers_AWREADY;
assign S00_AXI_bid[11:0] = axi_mem_intercon_1_to_s00_couplers_BID;
assign S00_AXI_bresp[1:0] = axi_mem_intercon_1_to_s00_couplers_BRESP;
assign S00_AXI_bvalid = axi_mem_intercon_1_to_s00_couplers_BVALID;
assign S00_AXI_rdata[31:0] = axi_mem_intercon_1_to_s00_couplers_RDATA;
assign S00_AXI_rid[11:0] = axi_mem_intercon_1_to_s00_couplers_RID;
assign S00_AXI_rlast = axi_mem_intercon_1_to_s00_couplers_RLAST;
assign S00_AXI_rresp[1:0] = axi_mem_intercon_1_to_s00_couplers_RRESP;
assign S00_AXI_rvalid = axi_mem_intercon_1_to_s00_couplers_RVALID;
assign S00_AXI_wready = axi_mem_intercon_1_to_s00_couplers_WREADY;
assign axi_mem_intercon_1_ACLK_net = M00_ACLK;
assign axi_mem_intercon_1_ARESETN_net = M00_ARESETN[0];
assign axi_mem_intercon_1_to_s00_couplers_ARADDR = S00_AXI_araddr[31:0];
assign axi_mem_intercon_1_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];
assign axi_mem_intercon_1_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];
assign axi_mem_intercon_1_to_s00_couplers_ARID = S00_AXI_arid[11:0];
assign axi_mem_intercon_1_to_s00_couplers_ARLEN = S00_AXI_arlen[3:0];
assign axi_mem_intercon_1_to_s00_couplers_ARLOCK = S00_AXI_arlock[1:0];
assign axi_mem_intercon_1_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];
assign axi_mem_intercon_1_to_s00_couplers_ARQOS = S00_AXI_arqos[3:0];
assign axi_mem_intercon_1_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];
assign axi_mem_intercon_1_to_s00_couplers_ARVALID = S00_AXI_arvalid;
assign axi_mem_intercon_1_to_s00_couplers_AWADDR = S00_AXI_awaddr[31:0];
assign axi_mem_intercon_1_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];
assign axi_mem_intercon_1_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];
assign axi_mem_intercon_1_to_s00_couplers_AWID = S00_AXI_awid[11:0];
assign axi_mem_intercon_1_to_s00_couplers_AWLEN = S00_AXI_awlen[3:0];
assign axi_mem_intercon_1_to_s00_couplers_AWLOCK = S00_AXI_awlock[1:0];
assign axi_mem_intercon_1_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];
assign axi_mem_intercon_1_to_s00_couplers_AWQOS = S00_AXI_awqos[3:0];
assign axi_mem_intercon_1_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];
assign axi_mem_intercon_1_to_s00_couplers_AWVALID = S00_AXI_awvalid;
assign axi_mem_intercon_1_to_s00_couplers_BREADY = S00_AXI_bready;
assign axi_mem_intercon_1_to_s00_couplers_RREADY = S00_AXI_rready;
assign axi_mem_intercon_1_to_s00_couplers_WDATA = S00_AXI_wdata[31:0];
assign axi_mem_intercon_1_to_s00_couplers_WID = S00_AXI_wid[11:0];
assign axi_mem_intercon_1_to_s00_couplers_WLAST = S00_AXI_wlast;
assign axi_mem_intercon_1_to_s00_couplers_WSTRB = S00_AXI_wstrb[3:0];
assign axi_mem_intercon_1_to_s00_couplers_WVALID = S00_AXI_wvalid;
assign s00_couplers_to_axi_mem_intercon_1_ARREADY = M00_AXI_arready;
assign s00_couplers_to_axi_mem_intercon_1_AWREADY = M00_AXI_awready;
assign s00_couplers_to_axi_mem_intercon_1_BID = M00_AXI_bid[11:0];
assign s00_couplers_to_axi_mem_intercon_1_BRESP = M00_AXI_bresp[1:0];
assign s00_couplers_to_axi_mem_intercon_1_BVALID = M00_AXI_bvalid;
assign s00_couplers_to_axi_mem_intercon_1_RDATA = M00_AXI_rdata[31:0];
assign s00_couplers_to_axi_mem_intercon_1_RID = M00_AXI_rid[11:0];
assign s00_couplers_to_axi_mem_intercon_1_RLAST = M00_AXI_rlast;
assign s00_couplers_to_axi_mem_intercon_1_RRESP = M00_AXI_rresp[1:0];
assign s00_couplers_to_axi_mem_intercon_1_RVALID = M00_AXI_rvalid;
assign s00_couplers_to_axi_mem_intercon_1_WREADY = M00_AXI_wready;
s00_couplers_imp_1FI55ZU s00_couplers
(.M_ACLK(axi_mem_intercon_1_ACLK_net),
.M_ARESETN(axi_mem_intercon_1_ARESETN_net),
.M_AXI_araddr(s00_couplers_to_axi_mem_intercon_1_ARADDR),
.M_AXI_arburst(s00_couplers_to_axi_mem_intercon_1_ARBURST),
.M_AXI_arcache(s00_couplers_to_axi_mem_intercon_1_ARCACHE),
.M_AXI_arid(s00_couplers_to_axi_mem_intercon_1_ARID),
.M_AXI_arlen(s00_couplers_to_axi_mem_intercon_1_ARLEN),
.M_AXI_arlock(s00_couplers_to_axi_mem_intercon_1_ARLOCK),
.M_AXI_arprot(s00_couplers_to_axi_mem_intercon_1_ARPROT),
.M_AXI_arready(s00_couplers_to_axi_mem_intercon_1_ARREADY),
.M_AXI_arsize(s00_couplers_to_axi_mem_intercon_1_ARSIZE),
.M_AXI_arvalid(s00_couplers_to_axi_mem_intercon_1_ARVALID),
.M_AXI_awaddr(s00_couplers_to_axi_mem_intercon_1_AWADDR),
.M_AXI_awburst(s00_couplers_to_axi_mem_intercon_1_AWBURST),
.M_AXI_awcache(s00_couplers_to_axi_mem_intercon_1_AWCACHE),
.M_AXI_awid(s00_couplers_to_axi_mem_intercon_1_AWID),
.M_AXI_awlen(s00_couplers_to_axi_mem_intercon_1_AWLEN),
.M_AXI_awlock(s00_couplers_to_axi_mem_intercon_1_AWLOCK),
.M_AXI_awprot(s00_couplers_to_axi_mem_intercon_1_AWPROT),
.M_AXI_awready(s00_couplers_to_axi_mem_intercon_1_AWREADY),
.M_AXI_awsize(s00_couplers_to_axi_mem_intercon_1_AWSIZE),
.M_AXI_awvalid(s00_couplers_to_axi_mem_intercon_1_AWVALID),
.M_AXI_bid(s00_couplers_to_axi_mem_intercon_1_BID),
.M_AXI_bready(s00_couplers_to_axi_mem_intercon_1_BREADY),
.M_AXI_bresp(s00_couplers_to_axi_mem_intercon_1_BRESP),
.M_AXI_bvalid(s00_couplers_to_axi_mem_intercon_1_BVALID),
.M_AXI_rdata(s00_couplers_to_axi_mem_intercon_1_RDATA),
.M_AXI_rid(s00_couplers_to_axi_mem_intercon_1_RID),
.M_AXI_rlast(s00_couplers_to_axi_mem_intercon_1_RLAST),
.M_AXI_rready(s00_couplers_to_axi_mem_intercon_1_RREADY),
.M_AXI_rresp(s00_couplers_to_axi_mem_intercon_1_RRESP),
.M_AXI_rvalid(s00_couplers_to_axi_mem_intercon_1_RVALID),
.M_AXI_wdata(s00_couplers_to_axi_mem_intercon_1_WDATA),
.M_AXI_wlast(s00_couplers_to_axi_mem_intercon_1_WLAST),
.M_AXI_wready(s00_couplers_to_axi_mem_intercon_1_WREADY),
.M_AXI_wstrb(s00_couplers_to_axi_mem_intercon_1_WSTRB),
.M_AXI_wvalid(s00_couplers_to_axi_mem_intercon_1_WVALID),
.S_ACLK(S00_ACLK_1),
.S_ARESETN(S00_ARESETN_1),
.S_AXI_araddr(axi_mem_intercon_1_to_s00_couplers_ARADDR),
.S_AXI_arburst(axi_mem_intercon_1_to_s00_couplers_ARBURST),
.S_AXI_arcache(axi_mem_intercon_1_to_s00_couplers_ARCACHE),
.S_AXI_arid(axi_mem_intercon_1_to_s00_couplers_ARID),
.S_AXI_arlen(axi_mem_intercon_1_to_s00_couplers_ARLEN),
.S_AXI_arlock(axi_mem_intercon_1_to_s00_couplers_ARLOCK),
.S_AXI_arprot(axi_mem_intercon_1_to_s00_couplers_ARPROT),
.S_AXI_arqos(axi_mem_intercon_1_to_s00_couplers_ARQOS),
.S_AXI_arready(axi_mem_intercon_1_to_s00_couplers_ARREADY),
.S_AXI_arsize(axi_mem_intercon_1_to_s00_couplers_ARSIZE),
.S_AXI_arvalid(axi_mem_intercon_1_to_s00_couplers_ARVALID),
.S_AXI_awaddr(axi_mem_intercon_1_to_s00_couplers_AWADDR),
.S_AXI_awburst(axi_mem_intercon_1_to_s00_couplers_AWBURST),
.S_AXI_awcache(axi_mem_intercon_1_to_s00_couplers_AWCACHE),
.S_AXI_awid(axi_mem_intercon_1_to_s00_couplers_AWID),
.S_AXI_awlen(axi_mem_intercon_1_to_s00_couplers_AWLEN),
.S_AXI_awlock(axi_mem_intercon_1_to_s00_couplers_AWLOCK),
.S_AXI_awprot(axi_mem_intercon_1_to_s00_couplers_AWPROT),
.S_AXI_awqos(axi_mem_intercon_1_to_s00_couplers_AWQOS),
.S_AXI_awready(axi_mem_intercon_1_to_s00_couplers_AWREADY),
.S_AXI_awsize(axi_mem_intercon_1_to_s00_couplers_AWSIZE),
.S_AXI_awvalid(axi_mem_intercon_1_to_s00_couplers_AWVALID),
.S_AXI_bid(axi_mem_intercon_1_to_s00_couplers_BID),
.S_AXI_bready(axi_mem_intercon_1_to_s00_couplers_BREADY),
.S_AXI_bresp(axi_mem_intercon_1_to_s00_couplers_BRESP),
.S_AXI_bvalid(axi_mem_intercon_1_to_s00_couplers_BVALID),
.S_AXI_rdata(axi_mem_intercon_1_to_s00_couplers_RDATA),
.S_AXI_rid(axi_mem_intercon_1_to_s00_couplers_RID),
.S_AXI_rlast(axi_mem_intercon_1_to_s00_couplers_RLAST),
.S_AXI_rready(axi_mem_intercon_1_to_s00_couplers_RREADY),
.S_AXI_rresp(axi_mem_intercon_1_to_s00_couplers_RRESP),
.S_AXI_rvalid(axi_mem_intercon_1_to_s00_couplers_RVALID),
.S_AXI_wdata(axi_mem_intercon_1_to_s00_couplers_WDATA),
.S_AXI_wid(axi_mem_intercon_1_to_s00_couplers_WID),
.S_AXI_wlast(axi_mem_intercon_1_to_s00_couplers_WLAST),
.S_AXI_wready(axi_mem_intercon_1_to_s00_couplers_WREADY),
.S_AXI_wstrb(axi_mem_intercon_1_to_s00_couplers_WSTRB),
.S_AXI_wvalid(axi_mem_intercon_1_to_s00_couplers_WVALID));
endmodule
module s00_couplers_imp_1FI55ZU
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arburst,
M_AXI_arcache,
M_AXI_arid,
M_AXI_arlen,
M_AXI_arlock,
M_AXI_arprot,
M_AXI_arready,
M_AXI_arsize,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awburst,
M_AXI_awcache,
M_AXI_awid,
M_AXI_awlen,
M_AXI_awlock,
M_AXI_awprot,
M_AXI_awready,
M_AXI_awsize,
M_AXI_awvalid,
M_AXI_bid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rid,
M_AXI_rlast,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wlast,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arid,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awid,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rid,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wid,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [12:0]M_AXI_araddr;
output [1:0]M_AXI_arburst;
output [3:0]M_AXI_arcache;
output [11:0]M_AXI_arid;
output [7:0]M_AXI_arlen;
output [0:0]M_AXI_arlock;
output [2:0]M_AXI_arprot;
input M_AXI_arready;
output [2:0]M_AXI_arsize;
output M_AXI_arvalid;
output [12:0]M_AXI_awaddr;
output [1:0]M_AXI_awburst;
output [3:0]M_AXI_awcache;
output [11:0]M_AXI_awid;
output [7:0]M_AXI_awlen;
output [0:0]M_AXI_awlock;
output [2:0]M_AXI_awprot;
input M_AXI_awready;
output [2:0]M_AXI_awsize;
output M_AXI_awvalid;
input [11:0]M_AXI_bid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
input [11:0]M_AXI_rid;
input M_AXI_rlast;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
output M_AXI_wlast;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [11:0]S_AXI_arid;
input [3:0]S_AXI_arlen;
input [1:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [11:0]S_AXI_awid;
input [3:0]S_AXI_awlen;
input [1:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
output [11:0]S_AXI_bid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
output [11:0]S_AXI_rid;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
input [11:0]S_AXI_wid;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire [0:0]S_ARESETN_1;
wire [31:0]auto_pc_to_s00_couplers_ARADDR;
wire [1:0]auto_pc_to_s00_couplers_ARBURST;
wire [3:0]auto_pc_to_s00_couplers_ARCACHE;
wire [11:0]auto_pc_to_s00_couplers_ARID;
wire [7:0]auto_pc_to_s00_couplers_ARLEN;
wire [0:0]auto_pc_to_s00_couplers_ARLOCK;
wire [2:0]auto_pc_to_s00_couplers_ARPROT;
wire auto_pc_to_s00_couplers_ARREADY;
wire [2:0]auto_pc_to_s00_couplers_ARSIZE;
wire auto_pc_to_s00_couplers_ARVALID;
wire [31:0]auto_pc_to_s00_couplers_AWADDR;
wire [1:0]auto_pc_to_s00_couplers_AWBURST;
wire [3:0]auto_pc_to_s00_couplers_AWCACHE;
wire [11:0]auto_pc_to_s00_couplers_AWID;
wire [7:0]auto_pc_to_s00_couplers_AWLEN;
wire [0:0]auto_pc_to_s00_couplers_AWLOCK;
wire [2:0]auto_pc_to_s00_couplers_AWPROT;
wire auto_pc_to_s00_couplers_AWREADY;
wire [2:0]auto_pc_to_s00_couplers_AWSIZE;
wire auto_pc_to_s00_couplers_AWVALID;
wire [11:0]auto_pc_to_s00_couplers_BID;
wire auto_pc_to_s00_couplers_BREADY;
wire [1:0]auto_pc_to_s00_couplers_BRESP;
wire auto_pc_to_s00_couplers_BVALID;
wire [31:0]auto_pc_to_s00_couplers_RDATA;
wire [11:0]auto_pc_to_s00_couplers_RID;
wire auto_pc_to_s00_couplers_RLAST;
wire auto_pc_to_s00_couplers_RREADY;
wire [1:0]auto_pc_to_s00_couplers_RRESP;
wire auto_pc_to_s00_couplers_RVALID;
wire [31:0]auto_pc_to_s00_couplers_WDATA;
wire auto_pc_to_s00_couplers_WLAST;
wire auto_pc_to_s00_couplers_WREADY;
wire [3:0]auto_pc_to_s00_couplers_WSTRB;
wire auto_pc_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_auto_pc_ARADDR;
wire [1:0]s00_couplers_to_auto_pc_ARBURST;
wire [3:0]s00_couplers_to_auto_pc_ARCACHE;
wire [11:0]s00_couplers_to_auto_pc_ARID;
wire [3:0]s00_couplers_to_auto_pc_ARLEN;
wire [1:0]s00_couplers_to_auto_pc_ARLOCK;
wire [2:0]s00_couplers_to_auto_pc_ARPROT;
wire [3:0]s00_couplers_to_auto_pc_ARQOS;
wire s00_couplers_to_auto_pc_ARREADY;
wire [2:0]s00_couplers_to_auto_pc_ARSIZE;
wire s00_couplers_to_auto_pc_ARVALID;
wire [31:0]s00_couplers_to_auto_pc_AWADDR;
wire [1:0]s00_couplers_to_auto_pc_AWBURST;
wire [3:0]s00_couplers_to_auto_pc_AWCACHE;
wire [11:0]s00_couplers_to_auto_pc_AWID;
wire [3:0]s00_couplers_to_auto_pc_AWLEN;
wire [1:0]s00_couplers_to_auto_pc_AWLOCK;
wire [2:0]s00_couplers_to_auto_pc_AWPROT;
wire [3:0]s00_couplers_to_auto_pc_AWQOS;
wire s00_couplers_to_auto_pc_AWREADY;
wire [2:0]s00_couplers_to_auto_pc_AWSIZE;
wire s00_couplers_to_auto_pc_AWVALID;
wire [11:0]s00_couplers_to_auto_pc_BID;
wire s00_couplers_to_auto_pc_BREADY;
wire [1:0]s00_couplers_to_auto_pc_BRESP;
wire s00_couplers_to_auto_pc_BVALID;
wire [31:0]s00_couplers_to_auto_pc_RDATA;
wire [11:0]s00_couplers_to_auto_pc_RID;
wire s00_couplers_to_auto_pc_RLAST;
wire s00_couplers_to_auto_pc_RREADY;
wire [1:0]s00_couplers_to_auto_pc_RRESP;
wire s00_couplers_to_auto_pc_RVALID;
wire [31:0]s00_couplers_to_auto_pc_WDATA;
wire [11:0]s00_couplers_to_auto_pc_WID;
wire s00_couplers_to_auto_pc_WLAST;
wire s00_couplers_to_auto_pc_WREADY;
wire [3:0]s00_couplers_to_auto_pc_WSTRB;
wire s00_couplers_to_auto_pc_WVALID;
assign M_AXI_araddr[12:0] = auto_pc_to_s00_couplers_ARADDR[12:0];
assign M_AXI_arburst[1:0] = auto_pc_to_s00_couplers_ARBURST;
assign M_AXI_arcache[3:0] = auto_pc_to_s00_couplers_ARCACHE;
assign M_AXI_arid[11:0] = auto_pc_to_s00_couplers_ARID;
assign M_AXI_arlen[7:0] = auto_pc_to_s00_couplers_ARLEN;
assign M_AXI_arlock[0] = auto_pc_to_s00_couplers_ARLOCK;
assign M_AXI_arprot[2:0] = auto_pc_to_s00_couplers_ARPROT;
assign M_AXI_arsize[2:0] = auto_pc_to_s00_couplers_ARSIZE;
assign M_AXI_arvalid = auto_pc_to_s00_couplers_ARVALID;
assign M_AXI_awaddr[12:0] = auto_pc_to_s00_couplers_AWADDR[12:0];
assign M_AXI_awburst[1:0] = auto_pc_to_s00_couplers_AWBURST;
assign M_AXI_awcache[3:0] = auto_pc_to_s00_couplers_AWCACHE;
assign M_AXI_awid[11:0] = auto_pc_to_s00_couplers_AWID;
assign M_AXI_awlen[7:0] = auto_pc_to_s00_couplers_AWLEN;
assign M_AXI_awlock[0] = auto_pc_to_s00_couplers_AWLOCK;
assign M_AXI_awprot[2:0] = auto_pc_to_s00_couplers_AWPROT;
assign M_AXI_awsize[2:0] = auto_pc_to_s00_couplers_AWSIZE;
assign M_AXI_awvalid = auto_pc_to_s00_couplers_AWVALID;
assign M_AXI_bready = auto_pc_to_s00_couplers_BREADY;
assign M_AXI_rready = auto_pc_to_s00_couplers_RREADY;
assign M_AXI_wdata[31:0] = auto_pc_to_s00_couplers_WDATA;
assign M_AXI_wlast = auto_pc_to_s00_couplers_WLAST;
assign M_AXI_wstrb[3:0] = auto_pc_to_s00_couplers_WSTRB;
assign M_AXI_wvalid = auto_pc_to_s00_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN[0];
assign S_AXI_arready = s00_couplers_to_auto_pc_ARREADY;
assign S_AXI_awready = s00_couplers_to_auto_pc_AWREADY;
assign S_AXI_bid[11:0] = s00_couplers_to_auto_pc_BID;
assign S_AXI_bresp[1:0] = s00_couplers_to_auto_pc_BRESP;
assign S_AXI_bvalid = s00_couplers_to_auto_pc_BVALID;
assign S_AXI_rdata[31:0] = s00_couplers_to_auto_pc_RDATA;
assign S_AXI_rid[11:0] = s00_couplers_to_auto_pc_RID;
assign S_AXI_rlast = s00_couplers_to_auto_pc_RLAST;
assign S_AXI_rresp[1:0] = s00_couplers_to_auto_pc_RRESP;
assign S_AXI_rvalid = s00_couplers_to_auto_pc_RVALID;
assign S_AXI_wready = s00_couplers_to_auto_pc_WREADY;
assign auto_pc_to_s00_couplers_ARREADY = M_AXI_arready;
assign auto_pc_to_s00_couplers_AWREADY = M_AXI_awready;
assign auto_pc_to_s00_couplers_BID = M_AXI_bid[11:0];
assign auto_pc_to_s00_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_pc_to_s00_couplers_BVALID = M_AXI_bvalid;
assign auto_pc_to_s00_couplers_RDATA = M_AXI_rdata[31:0];
assign auto_pc_to_s00_couplers_RID = M_AXI_rid[11:0];
assign auto_pc_to_s00_couplers_RLAST = M_AXI_rlast;
assign auto_pc_to_s00_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_pc_to_s00_couplers_RVALID = M_AXI_rvalid;
assign auto_pc_to_s00_couplers_WREADY = M_AXI_wready;
assign s00_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
assign s00_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
assign s00_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
assign s00_couplers_to_auto_pc_ARID = S_AXI_arid[11:0];
assign s00_couplers_to_auto_pc_ARLEN = S_AXI_arlen[3:0];
assign s00_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[1:0];
assign s00_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
assign s00_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
assign s00_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
assign s00_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
assign s00_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
assign s00_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
assign s00_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
assign s00_couplers_to_auto_pc_AWID = S_AXI_awid[11:0];
assign s00_couplers_to_auto_pc_AWLEN = S_AXI_awlen[3:0];
assign s00_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[1:0];
assign s00_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
assign s00_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
assign s00_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
assign s00_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
assign s00_couplers_to_auto_pc_BREADY = S_AXI_bready;
assign s00_couplers_to_auto_pc_RREADY = S_AXI_rready;
assign s00_couplers_to_auto_pc_WDATA = S_AXI_wdata[31:0];
assign s00_couplers_to_auto_pc_WID = S_AXI_wid[11:0];
assign s00_couplers_to_auto_pc_WLAST = S_AXI_wlast;
assign s00_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[3:0];
assign s00_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
design_1_auto_pc_1 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(auto_pc_to_s00_couplers_ARADDR),
.m_axi_arburst(auto_pc_to_s00_couplers_ARBURST),
.m_axi_arcache(auto_pc_to_s00_couplers_ARCACHE),
.m_axi_arid(auto_pc_to_s00_couplers_ARID),
.m_axi_arlen(auto_pc_to_s00_couplers_ARLEN),
.m_axi_arlock(auto_pc_to_s00_couplers_ARLOCK),
.m_axi_arprot(auto_pc_to_s00_couplers_ARPROT),
.m_axi_arready(auto_pc_to_s00_couplers_ARREADY),
.m_axi_arsize(auto_pc_to_s00_couplers_ARSIZE),
.m_axi_arvalid(auto_pc_to_s00_couplers_ARVALID),
.m_axi_awaddr(auto_pc_to_s00_couplers_AWADDR),
.m_axi_awburst(auto_pc_to_s00_couplers_AWBURST),
.m_axi_awcache(auto_pc_to_s00_couplers_AWCACHE),
.m_axi_awid(auto_pc_to_s00_couplers_AWID),
.m_axi_awlen(auto_pc_to_s00_couplers_AWLEN),
.m_axi_awlock(auto_pc_to_s00_couplers_AWLOCK),
.m_axi_awprot(auto_pc_to_s00_couplers_AWPROT),
.m_axi_awready(auto_pc_to_s00_couplers_AWREADY),
.m_axi_awsize(auto_pc_to_s00_couplers_AWSIZE),
.m_axi_awvalid(auto_pc_to_s00_couplers_AWVALID),
.m_axi_bid(auto_pc_to_s00_couplers_BID),
.m_axi_bready(auto_pc_to_s00_couplers_BREADY),
.m_axi_bresp(auto_pc_to_s00_couplers_BRESP),
.m_axi_bvalid(auto_pc_to_s00_couplers_BVALID),
.m_axi_rdata(auto_pc_to_s00_couplers_RDATA),
.m_axi_rid(auto_pc_to_s00_couplers_RID),
.m_axi_rlast(auto_pc_to_s00_couplers_RLAST),
.m_axi_rready(auto_pc_to_s00_couplers_RREADY),
.m_axi_rresp(auto_pc_to_s00_couplers_RRESP),
.m_axi_rvalid(auto_pc_to_s00_couplers_RVALID),
.m_axi_wdata(auto_pc_to_s00_couplers_WDATA),
.m_axi_wlast(auto_pc_to_s00_couplers_WLAST),
.m_axi_wready(auto_pc_to_s00_couplers_WREADY),
.m_axi_wstrb(auto_pc_to_s00_couplers_WSTRB),
.m_axi_wvalid(auto_pc_to_s00_couplers_WVALID),
.s_axi_araddr(s00_couplers_to_auto_pc_ARADDR),
.s_axi_arburst(s00_couplers_to_auto_pc_ARBURST),
.s_axi_arcache(s00_couplers_to_auto_pc_ARCACHE),
.s_axi_arid(s00_couplers_to_auto_pc_ARID),
.s_axi_arlen(s00_couplers_to_auto_pc_ARLEN),
.s_axi_arlock(s00_couplers_to_auto_pc_ARLOCK),
.s_axi_arprot(s00_couplers_to_auto_pc_ARPROT),
.s_axi_arqos(s00_couplers_to_auto_pc_ARQOS),
.s_axi_arready(s00_couplers_to_auto_pc_ARREADY),
.s_axi_arsize(s00_couplers_to_auto_pc_ARSIZE),
.s_axi_arvalid(s00_couplers_to_auto_pc_ARVALID),
.s_axi_awaddr(s00_couplers_to_auto_pc_AWADDR),
.s_axi_awburst(s00_couplers_to_auto_pc_AWBURST),
.s_axi_awcache(s00_couplers_to_auto_pc_AWCACHE),
.s_axi_awid(s00_couplers_to_auto_pc_AWID),
.s_axi_awlen(s00_couplers_to_auto_pc_AWLEN),
.s_axi_awlock(s00_couplers_to_auto_pc_AWLOCK),
.s_axi_awprot(s00_couplers_to_auto_pc_AWPROT),
.s_axi_awqos(s00_couplers_to_auto_pc_AWQOS),
.s_axi_awready(s00_couplers_to_auto_pc_AWREADY),
.s_axi_awsize(s00_couplers_to_auto_pc_AWSIZE),
.s_axi_awvalid(s00_couplers_to_auto_pc_AWVALID),
.s_axi_bid(s00_couplers_to_auto_pc_BID),
.s_axi_bready(s00_couplers_to_auto_pc_BREADY),
.s_axi_bresp(s00_couplers_to_auto_pc_BRESP),
.s_axi_bvalid(s00_couplers_to_auto_pc_BVALID),
.s_axi_rdata(s00_couplers_to_auto_pc_RDATA),
.s_axi_rid(s00_couplers_to_auto_pc_RID),
.s_axi_rlast(s00_couplers_to_auto_pc_RLAST),
.s_axi_rready(s00_couplers_to_auto_pc_RREADY),
.s_axi_rresp(s00_couplers_to_auto_pc_RRESP),
.s_axi_rvalid(s00_couplers_to_auto_pc_RVALID),
.s_axi_wdata(s00_couplers_to_auto_pc_WDATA),
.s_axi_wid(s00_couplers_to_auto_pc_WID),
.s_axi_wlast(s00_couplers_to_auto_pc_WLAST),
.s_axi_wready(s00_couplers_to_auto_pc_WREADY),
.s_axi_wstrb(s00_couplers_to_auto_pc_WSTRB),
.s_axi_wvalid(s00_couplers_to_auto_pc_WVALID));
endmodule
module s00_couplers_imp_7HNO1D
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arburst,
M_AXI_arcache,
M_AXI_arid,
M_AXI_arlen,
M_AXI_arlock,
M_AXI_arprot,
M_AXI_arready,
M_AXI_arsize,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awburst,
M_AXI_awcache,
M_AXI_awid,
M_AXI_awlen,
M_AXI_awlock,
M_AXI_awprot,
M_AXI_awready,
M_AXI_awsize,
M_AXI_awvalid,
M_AXI_bid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rid,
M_AXI_rlast,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wlast,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arid,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awid,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rid,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wid,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [12:0]M_AXI_araddr;
output [1:0]M_AXI_arburst;
output [3:0]M_AXI_arcache;
output [11:0]M_AXI_arid;
output [7:0]M_AXI_arlen;
output [0:0]M_AXI_arlock;
output [2:0]M_AXI_arprot;
input M_AXI_arready;
output [2:0]M_AXI_arsize;
output M_AXI_arvalid;
output [12:0]M_AXI_awaddr;
output [1:0]M_AXI_awburst;
output [3:0]M_AXI_awcache;
output [11:0]M_AXI_awid;
output [7:0]M_AXI_awlen;
output [0:0]M_AXI_awlock;
output [2:0]M_AXI_awprot;
input M_AXI_awready;
output [2:0]M_AXI_awsize;
output M_AXI_awvalid;
input [11:0]M_AXI_bid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
input [11:0]M_AXI_rid;
input M_AXI_rlast;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
output M_AXI_wlast;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [11:0]S_AXI_arid;
input [3:0]S_AXI_arlen;
input [1:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [11:0]S_AXI_awid;
input [3:0]S_AXI_awlen;
input [1:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
output [11:0]S_AXI_bid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
output [11:0]S_AXI_rid;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
input [11:0]S_AXI_wid;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire [0:0]S_ARESETN_1;
wire [31:0]auto_pc_to_s00_couplers_ARADDR;
wire [1:0]auto_pc_to_s00_couplers_ARBURST;
wire [3:0]auto_pc_to_s00_couplers_ARCACHE;
wire [11:0]auto_pc_to_s00_couplers_ARID;
wire [7:0]auto_pc_to_s00_couplers_ARLEN;
wire [0:0]auto_pc_to_s00_couplers_ARLOCK;
wire [2:0]auto_pc_to_s00_couplers_ARPROT;
wire auto_pc_to_s00_couplers_ARREADY;
wire [2:0]auto_pc_to_s00_couplers_ARSIZE;
wire auto_pc_to_s00_couplers_ARVALID;
wire [31:0]auto_pc_to_s00_couplers_AWADDR;
wire [1:0]auto_pc_to_s00_couplers_AWBURST;
wire [3:0]auto_pc_to_s00_couplers_AWCACHE;
wire [11:0]auto_pc_to_s00_couplers_AWID;
wire [7:0]auto_pc_to_s00_couplers_AWLEN;
wire [0:0]auto_pc_to_s00_couplers_AWLOCK;
wire [2:0]auto_pc_to_s00_couplers_AWPROT;
wire auto_pc_to_s00_couplers_AWREADY;
wire [2:0]auto_pc_to_s00_couplers_AWSIZE;
wire auto_pc_to_s00_couplers_AWVALID;
wire [11:0]auto_pc_to_s00_couplers_BID;
wire auto_pc_to_s00_couplers_BREADY;
wire [1:0]auto_pc_to_s00_couplers_BRESP;
wire auto_pc_to_s00_couplers_BVALID;
wire [31:0]auto_pc_to_s00_couplers_RDATA;
wire [11:0]auto_pc_to_s00_couplers_RID;
wire auto_pc_to_s00_couplers_RLAST;
wire auto_pc_to_s00_couplers_RREADY;
wire [1:0]auto_pc_to_s00_couplers_RRESP;
wire auto_pc_to_s00_couplers_RVALID;
wire [31:0]auto_pc_to_s00_couplers_WDATA;
wire auto_pc_to_s00_couplers_WLAST;
wire auto_pc_to_s00_couplers_WREADY;
wire [3:0]auto_pc_to_s00_couplers_WSTRB;
wire auto_pc_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_auto_pc_ARADDR;
wire [1:0]s00_couplers_to_auto_pc_ARBURST;
wire [3:0]s00_couplers_to_auto_pc_ARCACHE;
wire [11:0]s00_couplers_to_auto_pc_ARID;
wire [3:0]s00_couplers_to_auto_pc_ARLEN;
wire [1:0]s00_couplers_to_auto_pc_ARLOCK;
wire [2:0]s00_couplers_to_auto_pc_ARPROT;
wire [3:0]s00_couplers_to_auto_pc_ARQOS;
wire s00_couplers_to_auto_pc_ARREADY;
wire [2:0]s00_couplers_to_auto_pc_ARSIZE;
wire s00_couplers_to_auto_pc_ARVALID;
wire [31:0]s00_couplers_to_auto_pc_AWADDR;
wire [1:0]s00_couplers_to_auto_pc_AWBURST;
wire [3:0]s00_couplers_to_auto_pc_AWCACHE;
wire [11:0]s00_couplers_to_auto_pc_AWID;
wire [3:0]s00_couplers_to_auto_pc_AWLEN;
wire [1:0]s00_couplers_to_auto_pc_AWLOCK;
wire [2:0]s00_couplers_to_auto_pc_AWPROT;
wire [3:0]s00_couplers_to_auto_pc_AWQOS;
wire s00_couplers_to_auto_pc_AWREADY;
wire [2:0]s00_couplers_to_auto_pc_AWSIZE;
wire s00_couplers_to_auto_pc_AWVALID;
wire [11:0]s00_couplers_to_auto_pc_BID;
wire s00_couplers_to_auto_pc_BREADY;
wire [1:0]s00_couplers_to_auto_pc_BRESP;
wire s00_couplers_to_auto_pc_BVALID;
wire [31:0]s00_couplers_to_auto_pc_RDATA;
wire [11:0]s00_couplers_to_auto_pc_RID;
wire s00_couplers_to_auto_pc_RLAST;
wire s00_couplers_to_auto_pc_RREADY;
wire [1:0]s00_couplers_to_auto_pc_RRESP;
wire s00_couplers_to_auto_pc_RVALID;
wire [31:0]s00_couplers_to_auto_pc_WDATA;
wire [11:0]s00_couplers_to_auto_pc_WID;
wire s00_couplers_to_auto_pc_WLAST;
wire s00_couplers_to_auto_pc_WREADY;
wire [3:0]s00_couplers_to_auto_pc_WSTRB;
wire s00_couplers_to_auto_pc_WVALID;
assign M_AXI_araddr[12:0] = auto_pc_to_s00_couplers_ARADDR[12:0];
assign M_AXI_arburst[1:0] = auto_pc_to_s00_couplers_ARBURST;
assign M_AXI_arcache[3:0] = auto_pc_to_s00_couplers_ARCACHE;
assign M_AXI_arid[11:0] = auto_pc_to_s00_couplers_ARID;
assign M_AXI_arlen[7:0] = auto_pc_to_s00_couplers_ARLEN;
assign M_AXI_arlock[0] = auto_pc_to_s00_couplers_ARLOCK;
assign M_AXI_arprot[2:0] = auto_pc_to_s00_couplers_ARPROT;
assign M_AXI_arsize[2:0] = auto_pc_to_s00_couplers_ARSIZE;
assign M_AXI_arvalid = auto_pc_to_s00_couplers_ARVALID;
assign M_AXI_awaddr[12:0] = auto_pc_to_s00_couplers_AWADDR[12:0];
assign M_AXI_awburst[1:0] = auto_pc_to_s00_couplers_AWBURST;
assign M_AXI_awcache[3:0] = auto_pc_to_s00_couplers_AWCACHE;
assign M_AXI_awid[11:0] = auto_pc_to_s00_couplers_AWID;
assign M_AXI_awlen[7:0] = auto_pc_to_s00_couplers_AWLEN;
assign M_AXI_awlock[0] = auto_pc_to_s00_couplers_AWLOCK;
assign M_AXI_awprot[2:0] = auto_pc_to_s00_couplers_AWPROT;
assign M_AXI_awsize[2:0] = auto_pc_to_s00_couplers_AWSIZE;
assign M_AXI_awvalid = auto_pc_to_s00_couplers_AWVALID;
assign M_AXI_bready = auto_pc_to_s00_couplers_BREADY;
assign M_AXI_rready = auto_pc_to_s00_couplers_RREADY;
assign M_AXI_wdata[31:0] = auto_pc_to_s00_couplers_WDATA;
assign M_AXI_wlast = auto_pc_to_s00_couplers_WLAST;
assign M_AXI_wstrb[3:0] = auto_pc_to_s00_couplers_WSTRB;
assign M_AXI_wvalid = auto_pc_to_s00_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN[0];
assign S_AXI_arready = s00_couplers_to_auto_pc_ARREADY;
assign S_AXI_awready = s00_couplers_to_auto_pc_AWREADY;
assign S_AXI_bid[11:0] = s00_couplers_to_auto_pc_BID;
assign S_AXI_bresp[1:0] = s00_couplers_to_auto_pc_BRESP;
assign S_AXI_bvalid = s00_couplers_to_auto_pc_BVALID;
assign S_AXI_rdata[31:0] = s00_couplers_to_auto_pc_RDATA;
assign S_AXI_rid[11:0] = s00_couplers_to_auto_pc_RID;
assign S_AXI_rlast = s00_couplers_to_auto_pc_RLAST;
assign S_AXI_rresp[1:0] = s00_couplers_to_auto_pc_RRESP;
assign S_AXI_rvalid = s00_couplers_to_auto_pc_RVALID;
assign S_AXI_wready = s00_couplers_to_auto_pc_WREADY;
assign auto_pc_to_s00_couplers_ARREADY = M_AXI_arready;
assign auto_pc_to_s00_couplers_AWREADY = M_AXI_awready;
assign auto_pc_to_s00_couplers_BID = M_AXI_bid[11:0];
assign auto_pc_to_s00_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_pc_to_s00_couplers_BVALID = M_AXI_bvalid;
assign auto_pc_to_s00_couplers_RDATA = M_AXI_rdata[31:0];
assign auto_pc_to_s00_couplers_RID = M_AXI_rid[11:0];
assign auto_pc_to_s00_couplers_RLAST = M_AXI_rlast;
assign auto_pc_to_s00_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_pc_to_s00_couplers_RVALID = M_AXI_rvalid;
assign auto_pc_to_s00_couplers_WREADY = M_AXI_wready;
assign s00_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
assign s00_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
assign s00_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
assign s00_couplers_to_auto_pc_ARID = S_AXI_arid[11:0];
assign s00_couplers_to_auto_pc_ARLEN = S_AXI_arlen[3:0];
assign s00_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[1:0];
assign s00_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
assign s00_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
assign s00_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
assign s00_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
assign s00_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
assign s00_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
assign s00_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
assign s00_couplers_to_auto_pc_AWID = S_AXI_awid[11:0];
assign s00_couplers_to_auto_pc_AWLEN = S_AXI_awlen[3:0];
assign s00_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[1:0];
assign s00_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
assign s00_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
assign s00_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
assign s00_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
assign s00_couplers_to_auto_pc_BREADY = S_AXI_bready;
assign s00_couplers_to_auto_pc_RREADY = S_AXI_rready;
assign s00_couplers_to_auto_pc_WDATA = S_AXI_wdata[31:0];
assign s00_couplers_to_auto_pc_WID = S_AXI_wid[11:0];
assign s00_couplers_to_auto_pc_WLAST = S_AXI_wlast;
assign s00_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[3:0];
assign s00_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
design_1_auto_pc_0 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(auto_pc_to_s00_couplers_ARADDR),
.m_axi_arburst(auto_pc_to_s00_couplers_ARBURST),
.m_axi_arcache(auto_pc_to_s00_couplers_ARCACHE),
.m_axi_arid(auto_pc_to_s00_couplers_ARID),
.m_axi_arlen(auto_pc_to_s00_couplers_ARLEN),
.m_axi_arlock(auto_pc_to_s00_couplers_ARLOCK),
.m_axi_arprot(auto_pc_to_s00_couplers_ARPROT),
.m_axi_arready(auto_pc_to_s00_couplers_ARREADY),
.m_axi_arsize(auto_pc_to_s00_couplers_ARSIZE),
.m_axi_arvalid(auto_pc_to_s00_couplers_ARVALID),
.m_axi_awaddr(auto_pc_to_s00_couplers_AWADDR),
.m_axi_awburst(auto_pc_to_s00_couplers_AWBURST),
.m_axi_awcache(auto_pc_to_s00_couplers_AWCACHE),
.m_axi_awid(auto_pc_to_s00_couplers_AWID),
.m_axi_awlen(auto_pc_to_s00_couplers_AWLEN),
.m_axi_awlock(auto_pc_to_s00_couplers_AWLOCK),
.m_axi_awprot(auto_pc_to_s00_couplers_AWPROT),
.m_axi_awready(auto_pc_to_s00_couplers_AWREADY),
.m_axi_awsize(auto_pc_to_s00_couplers_AWSIZE),
.m_axi_awvalid(auto_pc_to_s00_couplers_AWVALID),
.m_axi_bid(auto_pc_to_s00_couplers_BID),
.m_axi_bready(auto_pc_to_s00_couplers_BREADY),
.m_axi_bresp(auto_pc_to_s00_couplers_BRESP),
.m_axi_bvalid(auto_pc_to_s00_couplers_BVALID),
.m_axi_rdata(auto_pc_to_s00_couplers_RDATA),
.m_axi_rid(auto_pc_to_s00_couplers_RID),
.m_axi_rlast(auto_pc_to_s00_couplers_RLAST),
.m_axi_rready(auto_pc_to_s00_couplers_RREADY),
.m_axi_rresp(auto_pc_to_s00_couplers_RRESP),
.m_axi_rvalid(auto_pc_to_s00_couplers_RVALID),
.m_axi_wdata(auto_pc_to_s00_couplers_WDATA),
.m_axi_wlast(auto_pc_to_s00_couplers_WLAST),
.m_axi_wready(auto_pc_to_s00_couplers_WREADY),
.m_axi_wstrb(auto_pc_to_s00_couplers_WSTRB),
.m_axi_wvalid(auto_pc_to_s00_couplers_WVALID),
.s_axi_araddr(s00_couplers_to_auto_pc_ARADDR),
.s_axi_arburst(s00_couplers_to_auto_pc_ARBURST),
.s_axi_arcache(s00_couplers_to_auto_pc_ARCACHE),
.s_axi_arid(s00_couplers_to_auto_pc_ARID),
.s_axi_arlen(s00_couplers_to_auto_pc_ARLEN),
.s_axi_arlock(s00_couplers_to_auto_pc_ARLOCK),
.s_axi_arprot(s00_couplers_to_auto_pc_ARPROT),
.s_axi_arqos(s00_couplers_to_auto_pc_ARQOS),
.s_axi_arready(s00_couplers_to_auto_pc_ARREADY),
.s_axi_arsize(s00_couplers_to_auto_pc_ARSIZE),
.s_axi_arvalid(s00_couplers_to_auto_pc_ARVALID),
.s_axi_awaddr(s00_couplers_to_auto_pc_AWADDR),
.s_axi_awburst(s00_couplers_to_auto_pc_AWBURST),
.s_axi_awcache(s00_couplers_to_auto_pc_AWCACHE),
.s_axi_awid(s00_couplers_to_auto_pc_AWID),
.s_axi_awlen(s00_couplers_to_auto_pc_AWLEN),
.s_axi_awlock(s00_couplers_to_auto_pc_AWLOCK),
.s_axi_awprot(s00_couplers_to_auto_pc_AWPROT),
.s_axi_awqos(s00_couplers_to_auto_pc_AWQOS),
.s_axi_awready(s00_couplers_to_auto_pc_AWREADY),
.s_axi_awsize(s00_couplers_to_auto_pc_AWSIZE),
.s_axi_awvalid(s00_couplers_to_auto_pc_AWVALID),
.s_axi_bid(s00_couplers_to_auto_pc_BID),
.s_axi_bready(s00_couplers_to_auto_pc_BREADY),
.s_axi_bresp(s00_couplers_to_auto_pc_BRESP),
.s_axi_bvalid(s00_couplers_to_auto_pc_BVALID),
.s_axi_rdata(s00_couplers_to_auto_pc_RDATA),
.s_axi_rid(s00_couplers_to_auto_pc_RID),
.s_axi_rlast(s00_couplers_to_auto_pc_RLAST),
.s_axi_rready(s00_couplers_to_auto_pc_RREADY),
.s_axi_rresp(s00_couplers_to_auto_pc_RRESP),
.s_axi_rvalid(s00_couplers_to_auto_pc_RVALID),
.s_axi_wdata(s00_couplers_to_auto_pc_WDATA),
.s_axi_wid(s00_couplers_to_auto_pc_WID),
.s_axi_wlast(s00_couplers_to_auto_pc_WLAST),
.s_axi_wready(s00_couplers_to_auto_pc_WREADY),
.s_axi_wstrb(s00_couplers_to_auto_pc_WSTRB),
.s_axi_wvalid(s00_couplers_to_auto_pc_WVALID));
endmodule
|
/**************************************************************************************************/
/* Many-core processor project Arch Lab. TOKYO TECH */
/**************************************************************************************************/
`default_nettype none
/**************************************************************************************************/
`include "define.v"
/**************************************************************************************************/
`define SS_SER_WAIT 'd0 // do not modify this. RS232C deserializer, State WAIT
`define SS_SER_RCV0 'd1 // do not modify this. RS232C deserializer, State Receive0
`define SS_SER_DONE 'd9 // do not modify this. RS232C deserializer, State DONE
/**************************************************************************************************/
/*
module UartTx(CLK, RST_X, DATA, WE, TXD, READY);
input wire CLK, RST_X, WE;
input wire [15:0] DATA;
output reg TXD, READY;
reg [18:0] cmd;
reg [11:0] waitnum;
reg [4:0] cnt;
always @(posedge CLK or negedge RST_X) begin
if(~RST_X) begin
TXD <= 1'b1;
READY <= 1'b1;
cmd <= 19'h7ffff;
waitnum <= 0;
cnt <= 0;
end else if( READY ) begin
TXD <= 1'b1;
waitnum <= 0;
if( WE )begin
READY <= 1'b0;
//cmd <= {DATA[15:8], 2'b01, DATA[7:0], 1'b0};
cmd <= {DATA[15:8], 2'b01, 8'b11111111, 1'b1};
cnt <= 20; // 10
end
end else if( waitnum >= `SERIAL_WCNT ) begin
TXD <= cmd[0];
READY <= (cnt == 1);
cmd <= {1'b1, cmd[18:1]};
waitnum <= 1;
cnt <= cnt - 1;
end else begin
waitnum <= waitnum + 1;
end
end
endmodule
*/
module UartTx(CLK, RST_X, DATA, WE, TXD, READY);
input wire CLK, RST_X, WE;
input wire [7:0] DATA;
output reg TXD, READY;
reg [8:0] cmd;
reg [11:0] waitnum;
reg [3:0] cnt;
always @(posedge CLK or negedge RST_X) begin
if(~RST_X) begin
TXD <= 1'b1;
READY <= 1'b1;
cmd <= 9'h1ff;
waitnum <= 0;
cnt <= 0;
end else if( READY ) begin
TXD <= 1'b1;
waitnum <= 0;
if( WE )begin
READY <= 1'b0;
cmd <= {DATA, 1'b0};
cnt <= 10;
end
end else if( waitnum >= `SERIAL_WCNT ) begin
TXD <= cmd[0];
READY <= (cnt == 1);
cmd <= {1'b1, cmd[8:1]};
waitnum <= 1;
cnt <= cnt - 1;
end else begin
waitnum <= waitnum + 1;
end
end
endmodule
/**************************************************************************************************/
module TX_FIFO(CLK, RST_X, D_IN, WE, RE, D_OUT, D_EN, RDY, ERR);
input wire CLK, RST_X, WE, RE;
input wire [7:0] D_IN;
output reg [7:0] D_OUT;
output reg D_EN, ERR;
output wire RDY;
reg [7:0] mem [0:2048-1]; // FIFO memory
reg [10:0] head, tail; // regs for FIFO
assign RDY = (D_EN==0 && head!=tail);
always @(posedge CLK) begin
if(~RST_X) begin
{D_EN, ERR, head, tail, D_OUT} <= 0;
end
else begin
if(WE) begin ///// enqueue
mem[tail] <= D_IN;
tail <= tail + 1;
if(head == (tail + 1)) ERR <= 1; // buffer may full!
end
if(RE) begin ///// dequeue
D_OUT <= mem[head];
D_EN <= 1;
head <= head + 1;
end else begin
D_EN <= 0;
end
end
end
endmodule
/**************************************************************************************************/
/*
module MultiUartTx(CLK, RST_X, TXD, ERR,
DT01, WE01, DT02, WE02, DT03, WE03, DT04, WE04);
input wire CLK, RST_X;
input wire [7:0] DT01, DT02, DT03, DT04;
input wire WE01, WE02, WE03, WE04;
output wire TXD, ERR;
wire RE01, RE02, RE03, RE04;
wire [7:0] data01, data02, data03, data04;
wire en01, en02, en03, en04;
wire RDY01, RDY02, RDY03, RDY04;
wire ERR01, ERR02, ERR03, ERR04;
wire [15:0] data;
wire en;
wire TxRdy;
assign ERR = ERR01 | ERR02 | ERR03 | ERR04;
assign RE01 = (RDY01 & TxRdy);
assign RE02 = (RDY02 & TxRdy) & (~RDY01 & ~en01);
assign RE03 = (RDY03 & TxRdy) & (~RDY01 & ~en01) & (~RDY02 & ~en02);
assign RE04 = (RDY04 & TxRdy) & (~RDY01 & ~en01) & (~RDY02 & ~en02) & (~RDY03 & ~en03);
assign data = (en01) ? {data01, 8'h30} :
(en02) ? {data02, 8'h31} :
(en03) ? {data03, 8'h32} : {data04, 8'h33};
assign en = en01 | en02 | en03 | en04;
TX_FIFO fifo_01(CLK, RST_X, DT01, WE01, RE01, data01, en01, RDY01, ERR01);
TX_FIFO fifo_02(CLK, RST_X, DT02, WE02, RE02, data02, en02, RDY02, ERR02);
TX_FIFO fifo_03(CLK, RST_X, DT03, WE03, RE03, data03, en03, RDY03, ERR03);
TX_FIFO fifo_04(CLK, RST_X, DT04, WE04, RE04, data04, en04, RDY04, ERR04);
UartTx send(CLK, RST_X, data, en, TXD, TxRdy);
endmodule
*/
module SingleUartTx(CLK, RST_X, TXD, ERR, DT01, WE01);
input wire CLK, RST_X;
input wire [7:0] DT01;
input wire WE01;
output wire TXD, ERR;
wire RE01;
wire [7:0] data01;
wire en01;
wire RDY01;
wire ERR01;
wire TxRdy;
assign ERR = ERR01;
assign RE01 = (RDY01 & TxRdy);
TX_FIFO fifo_01(CLK, RST_X, DT01, WE01, RE01, data01, en01, RDY01, ERR01);
UartTx send(CLK, RST_X, data01, en01, TXD, TxRdy);
endmodule
/**************************************************************************************************/
module UartRx(CLK, RST_X, RXD, DATA, EN);
input wire CLK, RST_X, RXD; // clock, reset, RS232C input
output reg [7:0] DATA; // 8bit output data
output reg EN; // 8bit output data enable
reg [3:0] stage;
reg [12:0] cnt; // counter to latch D0, D1, ..., D7
reg [11:0] cnt_start; // counter to detect the Start Bit
wire [12:0] waitcnt;
assign waitcnt = `SERIAL_WCNT;
always @(posedge CLK or negedge RST_X)
if (~RST_X) cnt_start <= 0;
else cnt_start <= (RXD) ? 0 : cnt_start + 1;
always @(posedge CLK or negedge RST_X)
if(~RST_X) begin
EN <= 0;
stage <= `SS_SER_WAIT;
cnt <= 1;
DATA <= 0;
end else if (stage == `SS_SER_WAIT) begin // detect the Start Bit
EN <= 0;
stage <= (cnt_start == (waitcnt >> 1)) ? `SS_SER_RCV0 : stage;
end else begin
if (cnt != waitcnt) begin
cnt <= cnt + 1;
EN <= 0;
end else begin // receive 1bit data
stage <= (stage == `SS_SER_DONE) ? `SS_SER_WAIT : stage + 1;
EN <= (stage == 8) ? 1 : 0;
DATA <= {RXD, DATA[7:1]};
cnt <= 1;
end
end
endmodule
/**************************************************************************************************/
/*
module PLOADER(CLK, RST_X, RXD, ADDR, DATA, WE, DONE1, DONE2);
input wire CLK, RST_X, RXD;
output reg [31:0] ADDR;
output reg [31:0] DATA;
output reg WE;
output reg DONE1; // application program load is done
output reg DONE2; // scheduling program load is done
reg [31:0] waddr; // memory write address
wire SER_EN;
wire [7:0] SER_DATA;
UartRx recv(CLK, RST_X, RXD, SER_DATA, SER_EN);
always @(posedge CLK or negedge RST_X) begin
if(~RST_X) begin
{ADDR, DATA, WE, waddr, DONE1, DONE2} <= 0;
end else begin
if(DONE2==0 && SER_EN) begin
//ADDR <= (waddr<32'h40000) ? waddr : {8'h04, 6'd0, waddr[17:0]};
ADDR <= waddr;
DATA <= {SER_DATA, DATA[31:8]};
WE <= (waddr[1:0]==3);
waddr <= waddr + 1;
if(waddr>=`APP_SIZE) DONE1 <= 1;
end else begin
WE <= 0;
if(waddr>=`APP_SIZE) DONE1 <= 1;
if(waddr>=`IMG_SIZE) DONE2 <= 1;
end
end
end
endmodule
*/
module PLOADER(CLK, RST_X, RXD, ADDR, DATA, WE_32, WE_128, DONE);
input wire CLK, RST_X, RXD;
output reg [31:0] ADDR;
output reg [127:0] DATA;
output reg WE_32;
output reg WE_128;
output reg DONE;
reg [31:0] waddr; // memory write address
wire SER_EN;
wire [7:0] SER_DATA;
UartRx recv(CLK, RST_X, RXD, SER_DATA, SER_EN);
always @(posedge CLK or negedge RST_X) begin
if(~RST_X) begin
{ADDR, DATA, WE_32, WE_128, waddr, DONE} <= 0;
end else begin
if(DONE==0 && SER_EN) begin
ADDR <= waddr;
DATA <= {SER_DATA, DATA[127:8]};
WE_32 <= (waddr[1:0]==3) ? 1'b1 : 1'b0;
WE_128 <= (waddr[3:0]==15) ? 1'b1 : 1'b0;
waddr <= waddr + 1;
if(waddr>=`APP_SIZE) DONE <= 1;
end else begin
WE_32 <= 0;
WE_128 <= 0;
if(waddr>=`APP_SIZE) DONE <= 1;
end
end
end
endmodule
/**************************************************************************************************/
`default_nettype wire
/**************************************************************************************************/
|
// megafunction wizard: %ALTECC%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altecc_decoder
// ============================================================
// File Name: alt_mem_ddrx_ecc_decoder_64.v
// Megafunction Name(s):
// altecc_decoder
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altecc_decoder device_family="Stratix III" lpm_pipeline=0 width_codeword=72 width_dataword=64 data err_corrected err_detected err_fatal q
//VERSION_BEGIN 10.0SP1 cbx_altecc_decoder 2010:08:18:21:16:35:SJ cbx_cycloneii 2010:08:18:21:16:35:SJ cbx_lpm_add_sub 2010:08:18:21:16:35:SJ cbx_lpm_compare 2010:08:18:21:16:35:SJ cbx_lpm_decode 2010:08:18:21:16:35:SJ cbx_mgl 2010:08:18:21:20:44:SJ cbx_stratix 2010:08:18:21:16:35:SJ cbx_stratixii 2010:08:18:21:16:35:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//lpm_decode DEVICE_FAMILY="Stratix III" LPM_DECODES=128 LPM_WIDTH=7 data eq
//VERSION_BEGIN 10.0SP1 cbx_cycloneii 2010:08:18:21:16:35:SJ cbx_lpm_add_sub 2010:08:18:21:16:35:SJ cbx_lpm_compare 2010:08:18:21:16:35:SJ cbx_lpm_decode 2010:08:18:21:16:35:SJ cbx_mgl 2010:08:18:21:20:44:SJ cbx_stratix 2010:08:18:21:16:35:SJ cbx_stratixii 2010:08:18:21:16:35:SJ VERSION_END
//synthesis_resources = lut 144
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module alt_mem_ddrx_ecc_decoder_64_decode
(
data,
eq) /* synthesis synthesis_clearbox=1 */;
input [6:0] data;
output [127:0] eq;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [6:0] data;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [5:0] data_wire;
wire enable_wire1;
wire enable_wire2;
wire [127:0] eq_node;
wire [63:0] eq_wire1;
wire [63:0] eq_wire2;
wire [3:0] w_anode1006w;
wire [3:0] w_anode1018w;
wire [3:0] w_anode1029w;
wire [3:0] w_anode1040w;
wire [3:0] w_anode1050w;
wire [3:0] w_anode1060w;
wire [3:0] w_anode1070w;
wire [3:0] w_anode1080w;
wire [3:0] w_anode1090w;
wire [3:0] w_anode1100w;
wire [3:0] w_anode1111w;
wire [3:0] w_anode1122w;
wire [3:0] w_anode1133w;
wire [3:0] w_anode1143w;
wire [3:0] w_anode1153w;
wire [3:0] w_anode1163w;
wire [3:0] w_anode1173w;
wire [3:0] w_anode1183w;
wire [3:0] w_anode1193w;
wire [3:0] w_anode1204w;
wire [3:0] w_anode1215w;
wire [3:0] w_anode1226w;
wire [3:0] w_anode1236w;
wire [3:0] w_anode1246w;
wire [3:0] w_anode1256w;
wire [3:0] w_anode1266w;
wire [3:0] w_anode1276w;
wire [3:0] w_anode1286w;
wire [3:0] w_anode1297w;
wire [3:0] w_anode1308w;
wire [3:0] w_anode1319w;
wire [3:0] w_anode1329w;
wire [3:0] w_anode1339w;
wire [3:0] w_anode1349w;
wire [3:0] w_anode1359w;
wire [3:0] w_anode1369w;
wire [3:0] w_anode1379w;
wire [3:0] w_anode1390w;
wire [3:0] w_anode1401w;
wire [3:0] w_anode1412w;
wire [3:0] w_anode1422w;
wire [3:0] w_anode1432w;
wire [3:0] w_anode1442w;
wire [3:0] w_anode1452w;
wire [3:0] w_anode1462w;
wire [3:0] w_anode1472w;
wire [3:0] w_anode1483w;
wire [3:0] w_anode1494w;
wire [3:0] w_anode1505w;
wire [3:0] w_anode1515w;
wire [3:0] w_anode1525w;
wire [3:0] w_anode1535w;
wire [3:0] w_anode1545w;
wire [3:0] w_anode1555w;
wire [3:0] w_anode1565w;
wire [3:0] w_anode1576w;
wire [3:0] w_anode1587w;
wire [3:0] w_anode1598w;
wire [3:0] w_anode1608w;
wire [3:0] w_anode1618w;
wire [3:0] w_anode1628w;
wire [3:0] w_anode1638w;
wire [3:0] w_anode1648w;
wire [3:0] w_anode1658w;
wire [3:0] w_anode1670w;
wire [3:0] w_anode1681w;
wire [3:0] w_anode1698w;
wire [3:0] w_anode1708w;
wire [3:0] w_anode1718w;
wire [3:0] w_anode1728w;
wire [3:0] w_anode1738w;
wire [3:0] w_anode1748w;
wire [3:0] w_anode1758w;
wire [3:0] w_anode1770w;
wire [3:0] w_anode1781w;
wire [3:0] w_anode1792w;
wire [3:0] w_anode1802w;
wire [3:0] w_anode1812w;
wire [3:0] w_anode1822w;
wire [3:0] w_anode1832w;
wire [3:0] w_anode1842w;
wire [3:0] w_anode1852w;
wire [3:0] w_anode1863w;
wire [3:0] w_anode1874w;
wire [3:0] w_anode1885w;
wire [3:0] w_anode1895w;
wire [3:0] w_anode1905w;
wire [3:0] w_anode1915w;
wire [3:0] w_anode1925w;
wire [3:0] w_anode1935w;
wire [3:0] w_anode1945w;
wire [3:0] w_anode1956w;
wire [3:0] w_anode1967w;
wire [3:0] w_anode1978w;
wire [3:0] w_anode1988w;
wire [3:0] w_anode1998w;
wire [3:0] w_anode2008w;
wire [3:0] w_anode2018w;
wire [3:0] w_anode2028w;
wire [3:0] w_anode2038w;
wire [3:0] w_anode2049w;
wire [3:0] w_anode2060w;
wire [3:0] w_anode2071w;
wire [3:0] w_anode2081w;
wire [3:0] w_anode2091w;
wire [3:0] w_anode2101w;
wire [3:0] w_anode2111w;
wire [3:0] w_anode2121w;
wire [3:0] w_anode2131w;
wire [3:0] w_anode2142w;
wire [3:0] w_anode2153w;
wire [3:0] w_anode2164w;
wire [3:0] w_anode2174w;
wire [3:0] w_anode2184w;
wire [3:0] w_anode2194w;
wire [3:0] w_anode2204w;
wire [3:0] w_anode2214w;
wire [3:0] w_anode2224w;
wire [3:0] w_anode2235w;
wire [3:0] w_anode2246w;
wire [3:0] w_anode2257w;
wire [3:0] w_anode2267w;
wire [3:0] w_anode2277w;
wire [3:0] w_anode2287w;
wire [3:0] w_anode2297w;
wire [3:0] w_anode2307w;
wire [3:0] w_anode2317w;
wire [3:0] w_anode2328w;
wire [3:0] w_anode2339w;
wire [3:0] w_anode2350w;
wire [3:0] w_anode2360w;
wire [3:0] w_anode2370w;
wire [3:0] w_anode2380w;
wire [3:0] w_anode2390w;
wire [3:0] w_anode2400w;
wire [3:0] w_anode2410w;
wire [3:0] w_anode912w;
wire [3:0] w_anode929w;
wire [3:0] w_anode946w;
wire [3:0] w_anode956w;
wire [3:0] w_anode966w;
wire [3:0] w_anode976w;
wire [3:0] w_anode986w;
wire [3:0] w_anode996w;
wire [2:0] w_data1669w;
wire [2:0] w_data910w;
assign
data_wire = data[5:0],
enable_wire1 = (~ data[6]),
enable_wire2 = data[6],
eq = eq_node,
eq_node = {eq_wire2[63:0], eq_wire1},
eq_wire1 = {{w_anode1658w[3], w_anode1648w[3], w_anode1638w[3], w_anode1628w[3], w_anode1618w[3], w_anode1608w[3], w_anode1598w[3], w_anode1587w[3]}, {w_anode1565w[3], w_anode1555w[3], w_anode1545w[3], w_anode1535w[3], w_anode1525w[3], w_anode1515w[3], w_anode1505w[3], w_anode1494w[3]}, {w_anode1472w[3], w_anode1462w[3], w_anode1452w[3], w_anode1442w[3], w_anode1432w[3], w_anode1422w[3], w_anode1412w[3], w_anode1401w[3]}, {w_anode1379w[3], w_anode1369w[3], w_anode1359w[3], w_anode1349w[3], w_anode1339w[3], w_anode1329w[3], w_anode1319w[3], w_anode1308w[3]}, {w_anode1286w[3], w_anode1276w[3], w_anode1266w[3], w_anode1256w[3], w_anode1246w[3], w_anode1236w[3], w_anode1226w[3], w_anode1215w[3]}, {w_anode1193w[3], w_anode1183w[3], w_anode1173w[3], w_anode1163w[3], w_anode1153w[3], w_anode1143w[3], w_anode1133w[3], w_anode1122w[3]}, {w_anode1100w[3], w_anode1090w[3], w_anode1080w[3], w_anode1070w[3], w_anode1060w[3], w_anode1050w[3], w_anode1040w[3], w_anode1029w[3]}, {w_anode1006w[3], w_anode996w[3], w_anode986w[3], w_anode976w[3], w_anode966w[3], w_anode956w[3], w_anode946w[3], w_anode929w[3]}},
eq_wire2 = {{w_anode2410w[3], w_anode2400w[3], w_anode2390w[3], w_anode2380w[3], w_anode2370w[3], w_anode2360w[3], w_anode2350w[3], w_anode2339w[3]}, {w_anode2317w[3], w_anode2307w[3], w_anode2297w[3], w_anode2287w[3], w_anode2277w[3], w_anode2267w[3], w_anode2257w[3], w_anode2246w[3]}, {w_anode2224w[3], w_anode2214w[3], w_anode2204w[3], w_anode2194w[3], w_anode2184w[3], w_anode2174w[3], w_anode2164w[3], w_anode2153w[3]}, {w_anode2131w[3], w_anode2121w[3], w_anode2111w[3], w_anode2101w[3], w_anode2091w[3], w_anode2081w[3], w_anode2071w[3], w_anode2060w[3]}, {w_anode2038w[3], w_anode2028w[3], w_anode2018w[3], w_anode2008w[3], w_anode1998w[3], w_anode1988w[3], w_anode1978w[3], w_anode1967w[3]}, {w_anode1945w[3], w_anode1935w[3], w_anode1925w[3], w_anode1915w[3], w_anode1905w[3], w_anode1895w[3], w_anode1885w[3], w_anode1874w[3]}, {w_anode1852w[3], w_anode1842w[3], w_anode1832w[3], w_anode1822w[3], w_anode1812w[3], w_anode1802w[3], w_anode1792w[3], w_anode1781w[3]}, {w_anode1758w[3], w_anode1748w[3], w_anode1738w[3], w_anode1728w[3], w_anode1718w[3], w_anode1708w[3], w_anode1698w[3], w_anode1681w[3]}},
w_anode1006w = {(w_anode1006w[2] & w_data910w[2]), (w_anode1006w[1] & w_data910w[1]), (w_anode1006w[0] & w_data910w[0]), w_anode912w[3]},
w_anode1018w = {(w_anode1018w[2] & (~ data_wire[5])), (w_anode1018w[1] & (~ data_wire[4])), (w_anode1018w[0] & data_wire[3]), enable_wire1},
w_anode1029w = {(w_anode1029w[2] & (~ w_data910w[2])), (w_anode1029w[1] & (~ w_data910w[1])), (w_anode1029w[0] & (~ w_data910w[0])), w_anode1018w[3]},
w_anode1040w = {(w_anode1040w[2] & (~ w_data910w[2])), (w_anode1040w[1] & (~ w_data910w[1])), (w_anode1040w[0] & w_data910w[0]), w_anode1018w[3]},
w_anode1050w = {(w_anode1050w[2] & (~ w_data910w[2])), (w_anode1050w[1] & w_data910w[1]), (w_anode1050w[0] & (~ w_data910w[0])), w_anode1018w[3]},
w_anode1060w = {(w_anode1060w[2] & (~ w_data910w[2])), (w_anode1060w[1] & w_data910w[1]), (w_anode1060w[0] & w_data910w[0]), w_anode1018w[3]},
w_anode1070w = {(w_anode1070w[2] & w_data910w[2]), (w_anode1070w[1] & (~ w_data910w[1])), (w_anode1070w[0] & (~ w_data910w[0])), w_anode1018w[3]},
w_anode1080w = {(w_anode1080w[2] & w_data910w[2]), (w_anode1080w[1] & (~ w_data910w[1])), (w_anode1080w[0] & w_data910w[0]), w_anode1018w[3]},
w_anode1090w = {(w_anode1090w[2] & w_data910w[2]), (w_anode1090w[1] & w_data910w[1]), (w_anode1090w[0] & (~ w_data910w[0])), w_anode1018w[3]},
w_anode1100w = {(w_anode1100w[2] & w_data910w[2]), (w_anode1100w[1] & w_data910w[1]), (w_anode1100w[0] & w_data910w[0]), w_anode1018w[3]},
w_anode1111w = {(w_anode1111w[2] & (~ data_wire[5])), (w_anode1111w[1] & data_wire[4]), (w_anode1111w[0] & (~ data_wire[3])), enable_wire1},
w_anode1122w = {(w_anode1122w[2] & (~ w_data910w[2])), (w_anode1122w[1] & (~ w_data910w[1])), (w_anode1122w[0] & (~ w_data910w[0])), w_anode1111w[3]},
w_anode1133w = {(w_anode1133w[2] & (~ w_data910w[2])), (w_anode1133w[1] & (~ w_data910w[1])), (w_anode1133w[0] & w_data910w[0]), w_anode1111w[3]},
w_anode1143w = {(w_anode1143w[2] & (~ w_data910w[2])), (w_anode1143w[1] & w_data910w[1]), (w_anode1143w[0] & (~ w_data910w[0])), w_anode1111w[3]},
w_anode1153w = {(w_anode1153w[2] & (~ w_data910w[2])), (w_anode1153w[1] & w_data910w[1]), (w_anode1153w[0] & w_data910w[0]), w_anode1111w[3]},
w_anode1163w = {(w_anode1163w[2] & w_data910w[2]), (w_anode1163w[1] & (~ w_data910w[1])), (w_anode1163w[0] & (~ w_data910w[0])), w_anode1111w[3]},
w_anode1173w = {(w_anode1173w[2] & w_data910w[2]), (w_anode1173w[1] & (~ w_data910w[1])), (w_anode1173w[0] & w_data910w[0]), w_anode1111w[3]},
w_anode1183w = {(w_anode1183w[2] & w_data910w[2]), (w_anode1183w[1] & w_data910w[1]), (w_anode1183w[0] & (~ w_data910w[0])), w_anode1111w[3]},
w_anode1193w = {(w_anode1193w[2] & w_data910w[2]), (w_anode1193w[1] & w_data910w[1]), (w_anode1193w[0] & w_data910w[0]), w_anode1111w[3]},
w_anode1204w = {(w_anode1204w[2] & (~ data_wire[5])), (w_anode1204w[1] & data_wire[4]), (w_anode1204w[0] & data_wire[3]), enable_wire1},
w_anode1215w = {(w_anode1215w[2] & (~ w_data910w[2])), (w_anode1215w[1] & (~ w_data910w[1])), (w_anode1215w[0] & (~ w_data910w[0])), w_anode1204w[3]},
w_anode1226w = {(w_anode1226w[2] & (~ w_data910w[2])), (w_anode1226w[1] & (~ w_data910w[1])), (w_anode1226w[0] & w_data910w[0]), w_anode1204w[3]},
w_anode1236w = {(w_anode1236w[2] & (~ w_data910w[2])), (w_anode1236w[1] & w_data910w[1]), (w_anode1236w[0] & (~ w_data910w[0])), w_anode1204w[3]},
w_anode1246w = {(w_anode1246w[2] & (~ w_data910w[2])), (w_anode1246w[1] & w_data910w[1]), (w_anode1246w[0] & w_data910w[0]), w_anode1204w[3]},
w_anode1256w = {(w_anode1256w[2] & w_data910w[2]), (w_anode1256w[1] & (~ w_data910w[1])), (w_anode1256w[0] & (~ w_data910w[0])), w_anode1204w[3]},
w_anode1266w = {(w_anode1266w[2] & w_data910w[2]), (w_anode1266w[1] & (~ w_data910w[1])), (w_anode1266w[0] & w_data910w[0]), w_anode1204w[3]},
w_anode1276w = {(w_anode1276w[2] & w_data910w[2]), (w_anode1276w[1] & w_data910w[1]), (w_anode1276w[0] & (~ w_data910w[0])), w_anode1204w[3]},
w_anode1286w = {(w_anode1286w[2] & w_data910w[2]), (w_anode1286w[1] & w_data910w[1]), (w_anode1286w[0] & w_data910w[0]), w_anode1204w[3]},
w_anode1297w = {(w_anode1297w[2] & data_wire[5]), (w_anode1297w[1] & (~ data_wire[4])), (w_anode1297w[0] & (~ data_wire[3])), enable_wire1},
w_anode1308w = {(w_anode1308w[2] & (~ w_data910w[2])), (w_anode1308w[1] & (~ w_data910w[1])), (w_anode1308w[0] & (~ w_data910w[0])), w_anode1297w[3]},
w_anode1319w = {(w_anode1319w[2] & (~ w_data910w[2])), (w_anode1319w[1] & (~ w_data910w[1])), (w_anode1319w[0] & w_data910w[0]), w_anode1297w[3]},
w_anode1329w = {(w_anode1329w[2] & (~ w_data910w[2])), (w_anode1329w[1] & w_data910w[1]), (w_anode1329w[0] & (~ w_data910w[0])), w_anode1297w[3]},
w_anode1339w = {(w_anode1339w[2] & (~ w_data910w[2])), (w_anode1339w[1] & w_data910w[1]), (w_anode1339w[0] & w_data910w[0]), w_anode1297w[3]},
w_anode1349w = {(w_anode1349w[2] & w_data910w[2]), (w_anode1349w[1] & (~ w_data910w[1])), (w_anode1349w[0] & (~ w_data910w[0])), w_anode1297w[3]},
w_anode1359w = {(w_anode1359w[2] & w_data910w[2]), (w_anode1359w[1] & (~ w_data910w[1])), (w_anode1359w[0] & w_data910w[0]), w_anode1297w[3]},
w_anode1369w = {(w_anode1369w[2] & w_data910w[2]), (w_anode1369w[1] & w_data910w[1]), (w_anode1369w[0] & (~ w_data910w[0])), w_anode1297w[3]},
w_anode1379w = {(w_anode1379w[2] & w_data910w[2]), (w_anode1379w[1] & w_data910w[1]), (w_anode1379w[0] & w_data910w[0]), w_anode1297w[3]},
w_anode1390w = {(w_anode1390w[2] & data_wire[5]), (w_anode1390w[1] & (~ data_wire[4])), (w_anode1390w[0] & data_wire[3]), enable_wire1},
w_anode1401w = {(w_anode1401w[2] & (~ w_data910w[2])), (w_anode1401w[1] & (~ w_data910w[1])), (w_anode1401w[0] & (~ w_data910w[0])), w_anode1390w[3]},
w_anode1412w = {(w_anode1412w[2] & (~ w_data910w[2])), (w_anode1412w[1] & (~ w_data910w[1])), (w_anode1412w[0] & w_data910w[0]), w_anode1390w[3]},
w_anode1422w = {(w_anode1422w[2] & (~ w_data910w[2])), (w_anode1422w[1] & w_data910w[1]), (w_anode1422w[0] & (~ w_data910w[0])), w_anode1390w[3]},
w_anode1432w = {(w_anode1432w[2] & (~ w_data910w[2])), (w_anode1432w[1] & w_data910w[1]), (w_anode1432w[0] & w_data910w[0]), w_anode1390w[3]},
w_anode1442w = {(w_anode1442w[2] & w_data910w[2]), (w_anode1442w[1] & (~ w_data910w[1])), (w_anode1442w[0] & (~ w_data910w[0])), w_anode1390w[3]},
w_anode1452w = {(w_anode1452w[2] & w_data910w[2]), (w_anode1452w[1] & (~ w_data910w[1])), (w_anode1452w[0] & w_data910w[0]), w_anode1390w[3]},
w_anode1462w = {(w_anode1462w[2] & w_data910w[2]), (w_anode1462w[1] & w_data910w[1]), (w_anode1462w[0] & (~ w_data910w[0])), w_anode1390w[3]},
w_anode1472w = {(w_anode1472w[2] & w_data910w[2]), (w_anode1472w[1] & w_data910w[1]), (w_anode1472w[0] & w_data910w[0]), w_anode1390w[3]},
w_anode1483w = {(w_anode1483w[2] & data_wire[5]), (w_anode1483w[1] & data_wire[4]), (w_anode1483w[0] & (~ data_wire[3])), enable_wire1},
w_anode1494w = {(w_anode1494w[2] & (~ w_data910w[2])), (w_anode1494w[1] & (~ w_data910w[1])), (w_anode1494w[0] & (~ w_data910w[0])), w_anode1483w[3]},
w_anode1505w = {(w_anode1505w[2] & (~ w_data910w[2])), (w_anode1505w[1] & (~ w_data910w[1])), (w_anode1505w[0] & w_data910w[0]), w_anode1483w[3]},
w_anode1515w = {(w_anode1515w[2] & (~ w_data910w[2])), (w_anode1515w[1] & w_data910w[1]), (w_anode1515w[0] & (~ w_data910w[0])), w_anode1483w[3]},
w_anode1525w = {(w_anode1525w[2] & (~ w_data910w[2])), (w_anode1525w[1] & w_data910w[1]), (w_anode1525w[0] & w_data910w[0]), w_anode1483w[3]},
w_anode1535w = {(w_anode1535w[2] & w_data910w[2]), (w_anode1535w[1] & (~ w_data910w[1])), (w_anode1535w[0] & (~ w_data910w[0])), w_anode1483w[3]},
w_anode1545w = {(w_anode1545w[2] & w_data910w[2]), (w_anode1545w[1] & (~ w_data910w[1])), (w_anode1545w[0] & w_data910w[0]), w_anode1483w[3]},
w_anode1555w = {(w_anode1555w[2] & w_data910w[2]), (w_anode1555w[1] & w_data910w[1]), (w_anode1555w[0] & (~ w_data910w[0])), w_anode1483w[3]},
w_anode1565w = {(w_anode1565w[2] & w_data910w[2]), (w_anode1565w[1] & w_data910w[1]), (w_anode1565w[0] & w_data910w[0]), w_anode1483w[3]},
w_anode1576w = {(w_anode1576w[2] & data_wire[5]), (w_anode1576w[1] & data_wire[4]), (w_anode1576w[0] & data_wire[3]), enable_wire1},
w_anode1587w = {(w_anode1587w[2] & (~ w_data910w[2])), (w_anode1587w[1] & (~ w_data910w[1])), (w_anode1587w[0] & (~ w_data910w[0])), w_anode1576w[3]},
w_anode1598w = {(w_anode1598w[2] & (~ w_data910w[2])), (w_anode1598w[1] & (~ w_data910w[1])), (w_anode1598w[0] & w_data910w[0]), w_anode1576w[3]},
w_anode1608w = {(w_anode1608w[2] & (~ w_data910w[2])), (w_anode1608w[1] & w_data910w[1]), (w_anode1608w[0] & (~ w_data910w[0])), w_anode1576w[3]},
w_anode1618w = {(w_anode1618w[2] & (~ w_data910w[2])), (w_anode1618w[1] & w_data910w[1]), (w_anode1618w[0] & w_data910w[0]), w_anode1576w[3]},
w_anode1628w = {(w_anode1628w[2] & w_data910w[2]), (w_anode1628w[1] & (~ w_data910w[1])), (w_anode1628w[0] & (~ w_data910w[0])), w_anode1576w[3]},
w_anode1638w = {(w_anode1638w[2] & w_data910w[2]), (w_anode1638w[1] & (~ w_data910w[1])), (w_anode1638w[0] & w_data910w[0]), w_anode1576w[3]},
w_anode1648w = {(w_anode1648w[2] & w_data910w[2]), (w_anode1648w[1] & w_data910w[1]), (w_anode1648w[0] & (~ w_data910w[0])), w_anode1576w[3]},
w_anode1658w = {(w_anode1658w[2] & w_data910w[2]), (w_anode1658w[1] & w_data910w[1]), (w_anode1658w[0] & w_data910w[0]), w_anode1576w[3]},
w_anode1670w = {(w_anode1670w[2] & (~ data_wire[5])), (w_anode1670w[1] & (~ data_wire[4])), (w_anode1670w[0] & (~ data_wire[3])), enable_wire2},
w_anode1681w = {(w_anode1681w[2] & (~ w_data1669w[2])), (w_anode1681w[1] & (~ w_data1669w[1])), (w_anode1681w[0] & (~ w_data1669w[0])), w_anode1670w[3]},
w_anode1698w = {(w_anode1698w[2] & (~ w_data1669w[2])), (w_anode1698w[1] & (~ w_data1669w[1])), (w_anode1698w[0] & w_data1669w[0]), w_anode1670w[3]},
w_anode1708w = {(w_anode1708w[2] & (~ w_data1669w[2])), (w_anode1708w[1] & w_data1669w[1]), (w_anode1708w[0] & (~ w_data1669w[0])), w_anode1670w[3]},
w_anode1718w = {(w_anode1718w[2] & (~ w_data1669w[2])), (w_anode1718w[1] & w_data1669w[1]), (w_anode1718w[0] & w_data1669w[0]), w_anode1670w[3]},
w_anode1728w = {(w_anode1728w[2] & w_data1669w[2]), (w_anode1728w[1] & (~ w_data1669w[1])), (w_anode1728w[0] & (~ w_data1669w[0])), w_anode1670w[3]},
w_anode1738w = {(w_anode1738w[2] & w_data1669w[2]), (w_anode1738w[1] & (~ w_data1669w[1])), (w_anode1738w[0] & w_data1669w[0]), w_anode1670w[3]},
w_anode1748w = {(w_anode1748w[2] & w_data1669w[2]), (w_anode1748w[1] & w_data1669w[1]), (w_anode1748w[0] & (~ w_data1669w[0])), w_anode1670w[3]},
w_anode1758w = {(w_anode1758w[2] & w_data1669w[2]), (w_anode1758w[1] & w_data1669w[1]), (w_anode1758w[0] & w_data1669w[0]), w_anode1670w[3]},
w_anode1770w = {(w_anode1770w[2] & (~ data_wire[5])), (w_anode1770w[1] & (~ data_wire[4])), (w_anode1770w[0] & data_wire[3]), enable_wire2},
w_anode1781w = {(w_anode1781w[2] & (~ w_data1669w[2])), (w_anode1781w[1] & (~ w_data1669w[1])), (w_anode1781w[0] & (~ w_data1669w[0])), w_anode1770w[3]},
w_anode1792w = {(w_anode1792w[2] & (~ w_data1669w[2])), (w_anode1792w[1] & (~ w_data1669w[1])), (w_anode1792w[0] & w_data1669w[0]), w_anode1770w[3]},
w_anode1802w = {(w_anode1802w[2] & (~ w_data1669w[2])), (w_anode1802w[1] & w_data1669w[1]), (w_anode1802w[0] & (~ w_data1669w[0])), w_anode1770w[3]},
w_anode1812w = {(w_anode1812w[2] & (~ w_data1669w[2])), (w_anode1812w[1] & w_data1669w[1]), (w_anode1812w[0] & w_data1669w[0]), w_anode1770w[3]},
w_anode1822w = {(w_anode1822w[2] & w_data1669w[2]), (w_anode1822w[1] & (~ w_data1669w[1])), (w_anode1822w[0] & (~ w_data1669w[0])), w_anode1770w[3]},
w_anode1832w = {(w_anode1832w[2] & w_data1669w[2]), (w_anode1832w[1] & (~ w_data1669w[1])), (w_anode1832w[0] & w_data1669w[0]), w_anode1770w[3]},
w_anode1842w = {(w_anode1842w[2] & w_data1669w[2]), (w_anode1842w[1] & w_data1669w[1]), (w_anode1842w[0] & (~ w_data1669w[0])), w_anode1770w[3]},
w_anode1852w = {(w_anode1852w[2] & w_data1669w[2]), (w_anode1852w[1] & w_data1669w[1]), (w_anode1852w[0] & w_data1669w[0]), w_anode1770w[3]},
w_anode1863w = {(w_anode1863w[2] & (~ data_wire[5])), (w_anode1863w[1] & data_wire[4]), (w_anode1863w[0] & (~ data_wire[3])), enable_wire2},
w_anode1874w = {(w_anode1874w[2] & (~ w_data1669w[2])), (w_anode1874w[1] & (~ w_data1669w[1])), (w_anode1874w[0] & (~ w_data1669w[0])), w_anode1863w[3]},
w_anode1885w = {(w_anode1885w[2] & (~ w_data1669w[2])), (w_anode1885w[1] & (~ w_data1669w[1])), (w_anode1885w[0] & w_data1669w[0]), w_anode1863w[3]},
w_anode1895w = {(w_anode1895w[2] & (~ w_data1669w[2])), (w_anode1895w[1] & w_data1669w[1]), (w_anode1895w[0] & (~ w_data1669w[0])), w_anode1863w[3]},
w_anode1905w = {(w_anode1905w[2] & (~ w_data1669w[2])), (w_anode1905w[1] & w_data1669w[1]), (w_anode1905w[0] & w_data1669w[0]), w_anode1863w[3]},
w_anode1915w = {(w_anode1915w[2] & w_data1669w[2]), (w_anode1915w[1] & (~ w_data1669w[1])), (w_anode1915w[0] & (~ w_data1669w[0])), w_anode1863w[3]},
w_anode1925w = {(w_anode1925w[2] & w_data1669w[2]), (w_anode1925w[1] & (~ w_data1669w[1])), (w_anode1925w[0] & w_data1669w[0]), w_anode1863w[3]},
w_anode1935w = {(w_anode1935w[2] & w_data1669w[2]), (w_anode1935w[1] & w_data1669w[1]), (w_anode1935w[0] & (~ w_data1669w[0])), w_anode1863w[3]},
w_anode1945w = {(w_anode1945w[2] & w_data1669w[2]), (w_anode1945w[1] & w_data1669w[1]), (w_anode1945w[0] & w_data1669w[0]), w_anode1863w[3]},
w_anode1956w = {(w_anode1956w[2] & (~ data_wire[5])), (w_anode1956w[1] & data_wire[4]), (w_anode1956w[0] & data_wire[3]), enable_wire2},
w_anode1967w = {(w_anode1967w[2] & (~ w_data1669w[2])), (w_anode1967w[1] & (~ w_data1669w[1])), (w_anode1967w[0] & (~ w_data1669w[0])), w_anode1956w[3]},
w_anode1978w = {(w_anode1978w[2] & (~ w_data1669w[2])), (w_anode1978w[1] & (~ w_data1669w[1])), (w_anode1978w[0] & w_data1669w[0]), w_anode1956w[3]},
w_anode1988w = {(w_anode1988w[2] & (~ w_data1669w[2])), (w_anode1988w[1] & w_data1669w[1]), (w_anode1988w[0] & (~ w_data1669w[0])), w_anode1956w[3]},
w_anode1998w = {(w_anode1998w[2] & (~ w_data1669w[2])), (w_anode1998w[1] & w_data1669w[1]), (w_anode1998w[0] & w_data1669w[0]), w_anode1956w[3]},
w_anode2008w = {(w_anode2008w[2] & w_data1669w[2]), (w_anode2008w[1] & (~ w_data1669w[1])), (w_anode2008w[0] & (~ w_data1669w[0])), w_anode1956w[3]},
w_anode2018w = {(w_anode2018w[2] & w_data1669w[2]), (w_anode2018w[1] & (~ w_data1669w[1])), (w_anode2018w[0] & w_data1669w[0]), w_anode1956w[3]},
w_anode2028w = {(w_anode2028w[2] & w_data1669w[2]), (w_anode2028w[1] & w_data1669w[1]), (w_anode2028w[0] & (~ w_data1669w[0])), w_anode1956w[3]},
w_anode2038w = {(w_anode2038w[2] & w_data1669w[2]), (w_anode2038w[1] & w_data1669w[1]), (w_anode2038w[0] & w_data1669w[0]), w_anode1956w[3]},
w_anode2049w = {(w_anode2049w[2] & data_wire[5]), (w_anode2049w[1] & (~ data_wire[4])), (w_anode2049w[0] & (~ data_wire[3])), enable_wire2},
w_anode2060w = {(w_anode2060w[2] & (~ w_data1669w[2])), (w_anode2060w[1] & (~ w_data1669w[1])), (w_anode2060w[0] & (~ w_data1669w[0])), w_anode2049w[3]},
w_anode2071w = {(w_anode2071w[2] & (~ w_data1669w[2])), (w_anode2071w[1] & (~ w_data1669w[1])), (w_anode2071w[0] & w_data1669w[0]), w_anode2049w[3]},
w_anode2081w = {(w_anode2081w[2] & (~ w_data1669w[2])), (w_anode2081w[1] & w_data1669w[1]), (w_anode2081w[0] & (~ w_data1669w[0])), w_anode2049w[3]},
w_anode2091w = {(w_anode2091w[2] & (~ w_data1669w[2])), (w_anode2091w[1] & w_data1669w[1]), (w_anode2091w[0] & w_data1669w[0]), w_anode2049w[3]},
w_anode2101w = {(w_anode2101w[2] & w_data1669w[2]), (w_anode2101w[1] & (~ w_data1669w[1])), (w_anode2101w[0] & (~ w_data1669w[0])), w_anode2049w[3]},
w_anode2111w = {(w_anode2111w[2] & w_data1669w[2]), (w_anode2111w[1] & (~ w_data1669w[1])), (w_anode2111w[0] & w_data1669w[0]), w_anode2049w[3]},
w_anode2121w = {(w_anode2121w[2] & w_data1669w[2]), (w_anode2121w[1] & w_data1669w[1]), (w_anode2121w[0] & (~ w_data1669w[0])), w_anode2049w[3]},
w_anode2131w = {(w_anode2131w[2] & w_data1669w[2]), (w_anode2131w[1] & w_data1669w[1]), (w_anode2131w[0] & w_data1669w[0]), w_anode2049w[3]},
w_anode2142w = {(w_anode2142w[2] & data_wire[5]), (w_anode2142w[1] & (~ data_wire[4])), (w_anode2142w[0] & data_wire[3]), enable_wire2},
w_anode2153w = {(w_anode2153w[2] & (~ w_data1669w[2])), (w_anode2153w[1] & (~ w_data1669w[1])), (w_anode2153w[0] & (~ w_data1669w[0])), w_anode2142w[3]},
w_anode2164w = {(w_anode2164w[2] & (~ w_data1669w[2])), (w_anode2164w[1] & (~ w_data1669w[1])), (w_anode2164w[0] & w_data1669w[0]), w_anode2142w[3]},
w_anode2174w = {(w_anode2174w[2] & (~ w_data1669w[2])), (w_anode2174w[1] & w_data1669w[1]), (w_anode2174w[0] & (~ w_data1669w[0])), w_anode2142w[3]},
w_anode2184w = {(w_anode2184w[2] & (~ w_data1669w[2])), (w_anode2184w[1] & w_data1669w[1]), (w_anode2184w[0] & w_data1669w[0]), w_anode2142w[3]},
w_anode2194w = {(w_anode2194w[2] & w_data1669w[2]), (w_anode2194w[1] & (~ w_data1669w[1])), (w_anode2194w[0] & (~ w_data1669w[0])), w_anode2142w[3]},
w_anode2204w = {(w_anode2204w[2] & w_data1669w[2]), (w_anode2204w[1] & (~ w_data1669w[1])), (w_anode2204w[0] & w_data1669w[0]), w_anode2142w[3]},
w_anode2214w = {(w_anode2214w[2] & w_data1669w[2]), (w_anode2214w[1] & w_data1669w[1]), (w_anode2214w[0] & (~ w_data1669w[0])), w_anode2142w[3]},
w_anode2224w = {(w_anode2224w[2] & w_data1669w[2]), (w_anode2224w[1] & w_data1669w[1]), (w_anode2224w[0] & w_data1669w[0]), w_anode2142w[3]},
w_anode2235w = {(w_anode2235w[2] & data_wire[5]), (w_anode2235w[1] & data_wire[4]), (w_anode2235w[0] & (~ data_wire[3])), enable_wire2},
w_anode2246w = {(w_anode2246w[2] & (~ w_data1669w[2])), (w_anode2246w[1] & (~ w_data1669w[1])), (w_anode2246w[0] & (~ w_data1669w[0])), w_anode2235w[3]},
w_anode2257w = {(w_anode2257w[2] & (~ w_data1669w[2])), (w_anode2257w[1] & (~ w_data1669w[1])), (w_anode2257w[0] & w_data1669w[0]), w_anode2235w[3]},
w_anode2267w = {(w_anode2267w[2] & (~ w_data1669w[2])), (w_anode2267w[1] & w_data1669w[1]), (w_anode2267w[0] & (~ w_data1669w[0])), w_anode2235w[3]},
w_anode2277w = {(w_anode2277w[2] & (~ w_data1669w[2])), (w_anode2277w[1] & w_data1669w[1]), (w_anode2277w[0] & w_data1669w[0]), w_anode2235w[3]},
w_anode2287w = {(w_anode2287w[2] & w_data1669w[2]), (w_anode2287w[1] & (~ w_data1669w[1])), (w_anode2287w[0] & (~ w_data1669w[0])), w_anode2235w[3]},
w_anode2297w = {(w_anode2297w[2] & w_data1669w[2]), (w_anode2297w[1] & (~ w_data1669w[1])), (w_anode2297w[0] & w_data1669w[0]), w_anode2235w[3]},
w_anode2307w = {(w_anode2307w[2] & w_data1669w[2]), (w_anode2307w[1] & w_data1669w[1]), (w_anode2307w[0] & (~ w_data1669w[0])), w_anode2235w[3]},
w_anode2317w = {(w_anode2317w[2] & w_data1669w[2]), (w_anode2317w[1] & w_data1669w[1]), (w_anode2317w[0] & w_data1669w[0]), w_anode2235w[3]},
w_anode2328w = {(w_anode2328w[2] & data_wire[5]), (w_anode2328w[1] & data_wire[4]), (w_anode2328w[0] & data_wire[3]), enable_wire2},
w_anode2339w = {(w_anode2339w[2] & (~ w_data1669w[2])), (w_anode2339w[1] & (~ w_data1669w[1])), (w_anode2339w[0] & (~ w_data1669w[0])), w_anode2328w[3]},
w_anode2350w = {(w_anode2350w[2] & (~ w_data1669w[2])), (w_anode2350w[1] & (~ w_data1669w[1])), (w_anode2350w[0] & w_data1669w[0]), w_anode2328w[3]},
w_anode2360w = {(w_anode2360w[2] & (~ w_data1669w[2])), (w_anode2360w[1] & w_data1669w[1]), (w_anode2360w[0] & (~ w_data1669w[0])), w_anode2328w[3]},
w_anode2370w = {(w_anode2370w[2] & (~ w_data1669w[2])), (w_anode2370w[1] & w_data1669w[1]), (w_anode2370w[0] & w_data1669w[0]), w_anode2328w[3]},
w_anode2380w = {(w_anode2380w[2] & w_data1669w[2]), (w_anode2380w[1] & (~ w_data1669w[1])), (w_anode2380w[0] & (~ w_data1669w[0])), w_anode2328w[3]},
w_anode2390w = {(w_anode2390w[2] & w_data1669w[2]), (w_anode2390w[1] & (~ w_data1669w[1])), (w_anode2390w[0] & w_data1669w[0]), w_anode2328w[3]},
w_anode2400w = {(w_anode2400w[2] & w_data1669w[2]), (w_anode2400w[1] & w_data1669w[1]), (w_anode2400w[0] & (~ w_data1669w[0])), w_anode2328w[3]},
w_anode2410w = {(w_anode2410w[2] & w_data1669w[2]), (w_anode2410w[1] & w_data1669w[1]), (w_anode2410w[0] & w_data1669w[0]), w_anode2328w[3]},
w_anode912w = {(w_anode912w[2] & (~ data_wire[5])), (w_anode912w[1] & (~ data_wire[4])), (w_anode912w[0] & (~ data_wire[3])), enable_wire1},
w_anode929w = {(w_anode929w[2] & (~ w_data910w[2])), (w_anode929w[1] & (~ w_data910w[1])), (w_anode929w[0] & (~ w_data910w[0])), w_anode912w[3]},
w_anode946w = {(w_anode946w[2] & (~ w_data910w[2])), (w_anode946w[1] & (~ w_data910w[1])), (w_anode946w[0] & w_data910w[0]), w_anode912w[3]},
w_anode956w = {(w_anode956w[2] & (~ w_data910w[2])), (w_anode956w[1] & w_data910w[1]), (w_anode956w[0] & (~ w_data910w[0])), w_anode912w[3]},
w_anode966w = {(w_anode966w[2] & (~ w_data910w[2])), (w_anode966w[1] & w_data910w[1]), (w_anode966w[0] & w_data910w[0]), w_anode912w[3]},
w_anode976w = {(w_anode976w[2] & w_data910w[2]), (w_anode976w[1] & (~ w_data910w[1])), (w_anode976w[0] & (~ w_data910w[0])), w_anode912w[3]},
w_anode986w = {(w_anode986w[2] & w_data910w[2]), (w_anode986w[1] & (~ w_data910w[1])), (w_anode986w[0] & w_data910w[0]), w_anode912w[3]},
w_anode996w = {(w_anode996w[2] & w_data910w[2]), (w_anode996w[1] & w_data910w[1]), (w_anode996w[0] & (~ w_data910w[0])), w_anode912w[3]},
w_data1669w = data_wire[2:0],
w_data910w = data_wire[2:0];
endmodule //alt_mem_ddrx_ecc_decoder_64_decode
//synthesis_resources = lut 144 mux21 64
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module alt_mem_ddrx_ecc_decoder_64_altecc_decoder
(
data,
err_corrected,
err_detected,
err_fatal,
err_sbe,
q) /* synthesis synthesis_clearbox=1 */;
input [71:0] data;
output err_corrected;
output err_detected;
output err_fatal;
output err_sbe;
output [63:0] q;
wire [127:0] wire_error_bit_decoder_eq;
wire wire_mux21_0_dataout;
wire wire_mux21_1_dataout;
wire wire_mux21_10_dataout;
wire wire_mux21_11_dataout;
wire wire_mux21_12_dataout;
wire wire_mux21_13_dataout;
wire wire_mux21_14_dataout;
wire wire_mux21_15_dataout;
wire wire_mux21_16_dataout;
wire wire_mux21_17_dataout;
wire wire_mux21_18_dataout;
wire wire_mux21_19_dataout;
wire wire_mux21_2_dataout;
wire wire_mux21_20_dataout;
wire wire_mux21_21_dataout;
wire wire_mux21_22_dataout;
wire wire_mux21_23_dataout;
wire wire_mux21_24_dataout;
wire wire_mux21_25_dataout;
wire wire_mux21_26_dataout;
wire wire_mux21_27_dataout;
wire wire_mux21_28_dataout;
wire wire_mux21_29_dataout;
wire wire_mux21_3_dataout;
wire wire_mux21_30_dataout;
wire wire_mux21_31_dataout;
wire wire_mux21_32_dataout;
wire wire_mux21_33_dataout;
wire wire_mux21_34_dataout;
wire wire_mux21_35_dataout;
wire wire_mux21_36_dataout;
wire wire_mux21_37_dataout;
wire wire_mux21_38_dataout;
wire wire_mux21_39_dataout;
wire wire_mux21_4_dataout;
wire wire_mux21_40_dataout;
wire wire_mux21_41_dataout;
wire wire_mux21_42_dataout;
wire wire_mux21_43_dataout;
wire wire_mux21_44_dataout;
wire wire_mux21_45_dataout;
wire wire_mux21_46_dataout;
wire wire_mux21_47_dataout;
wire wire_mux21_48_dataout;
wire wire_mux21_49_dataout;
wire wire_mux21_5_dataout;
wire wire_mux21_50_dataout;
wire wire_mux21_51_dataout;
wire wire_mux21_52_dataout;
wire wire_mux21_53_dataout;
wire wire_mux21_54_dataout;
wire wire_mux21_55_dataout;
wire wire_mux21_56_dataout;
wire wire_mux21_57_dataout;
wire wire_mux21_58_dataout;
wire wire_mux21_59_dataout;
wire wire_mux21_6_dataout;
wire wire_mux21_60_dataout;
wire wire_mux21_61_dataout;
wire wire_mux21_62_dataout;
wire wire_mux21_63_dataout;
wire wire_mux21_7_dataout;
wire wire_mux21_8_dataout;
wire wire_mux21_9_dataout;
wire data_bit;
wire [63:0] data_t;
wire [71:0] data_wire;
wire [127:0] decode_output;
wire err_corrected_wire;
wire err_detected_wire;
wire err_fatal_wire;
wire [35:0] parity_01_wire;
wire [17:0] parity_02_wire;
wire [8:0] parity_03_wire;
wire [3:0] parity_04_wire;
wire [1:0] parity_05_wire;
wire [30:0] parity_06_wire;
wire [6:0] parity_07_wire;
wire parity_bit;
wire [70:0] parity_final_wire;
wire [6:0] parity_t;
wire [63:0] q_wire;
wire syn_bit;
wire syn_e;
wire [5:0] syn_t;
wire [7:0] syndrome;
alt_mem_ddrx_ecc_decoder_64_decode error_bit_decoder
(
.data(syndrome[6:0]),
.eq(wire_error_bit_decoder_eq));
assign wire_mux21_0_dataout = (syndrome[7] == 1'b1) ? (decode_output[3] ^ data_wire[0]) : data_wire[0];
assign wire_mux21_1_dataout = (syndrome[7] == 1'b1) ? (decode_output[5] ^ data_wire[1]) : data_wire[1];
assign wire_mux21_10_dataout = (syndrome[7] == 1'b1) ? (decode_output[15] ^ data_wire[10]) : data_wire[10];
assign wire_mux21_11_dataout = (syndrome[7] == 1'b1) ? (decode_output[17] ^ data_wire[11]) : data_wire[11];
assign wire_mux21_12_dataout = (syndrome[7] == 1'b1) ? (decode_output[18] ^ data_wire[12]) : data_wire[12];
assign wire_mux21_13_dataout = (syndrome[7] == 1'b1) ? (decode_output[19] ^ data_wire[13]) : data_wire[13];
assign wire_mux21_14_dataout = (syndrome[7] == 1'b1) ? (decode_output[20] ^ data_wire[14]) : data_wire[14];
assign wire_mux21_15_dataout = (syndrome[7] == 1'b1) ? (decode_output[21] ^ data_wire[15]) : data_wire[15];
assign wire_mux21_16_dataout = (syndrome[7] == 1'b1) ? (decode_output[22] ^ data_wire[16]) : data_wire[16];
assign wire_mux21_17_dataout = (syndrome[7] == 1'b1) ? (decode_output[23] ^ data_wire[17]) : data_wire[17];
assign wire_mux21_18_dataout = (syndrome[7] == 1'b1) ? (decode_output[24] ^ data_wire[18]) : data_wire[18];
assign wire_mux21_19_dataout = (syndrome[7] == 1'b1) ? (decode_output[25] ^ data_wire[19]) : data_wire[19];
assign wire_mux21_2_dataout = (syndrome[7] == 1'b1) ? (decode_output[6] ^ data_wire[2]) : data_wire[2];
assign wire_mux21_20_dataout = (syndrome[7] == 1'b1) ? (decode_output[26] ^ data_wire[20]) : data_wire[20];
assign wire_mux21_21_dataout = (syndrome[7] == 1'b1) ? (decode_output[27] ^ data_wire[21]) : data_wire[21];
assign wire_mux21_22_dataout = (syndrome[7] == 1'b1) ? (decode_output[28] ^ data_wire[22]) : data_wire[22];
assign wire_mux21_23_dataout = (syndrome[7] == 1'b1) ? (decode_output[29] ^ data_wire[23]) : data_wire[23];
assign wire_mux21_24_dataout = (syndrome[7] == 1'b1) ? (decode_output[30] ^ data_wire[24]) : data_wire[24];
assign wire_mux21_25_dataout = (syndrome[7] == 1'b1) ? (decode_output[31] ^ data_wire[25]) : data_wire[25];
assign wire_mux21_26_dataout = (syndrome[7] == 1'b1) ? (decode_output[33] ^ data_wire[26]) : data_wire[26];
assign wire_mux21_27_dataout = (syndrome[7] == 1'b1) ? (decode_output[34] ^ data_wire[27]) : data_wire[27];
assign wire_mux21_28_dataout = (syndrome[7] == 1'b1) ? (decode_output[35] ^ data_wire[28]) : data_wire[28];
assign wire_mux21_29_dataout = (syndrome[7] == 1'b1) ? (decode_output[36] ^ data_wire[29]) : data_wire[29];
assign wire_mux21_3_dataout = (syndrome[7] == 1'b1) ? (decode_output[7] ^ data_wire[3]) : data_wire[3];
assign wire_mux21_30_dataout = (syndrome[7] == 1'b1) ? (decode_output[37] ^ data_wire[30]) : data_wire[30];
assign wire_mux21_31_dataout = (syndrome[7] == 1'b1) ? (decode_output[38] ^ data_wire[31]) : data_wire[31];
assign wire_mux21_32_dataout = (syndrome[7] == 1'b1) ? (decode_output[39] ^ data_wire[32]) : data_wire[32];
assign wire_mux21_33_dataout = (syndrome[7] == 1'b1) ? (decode_output[40] ^ data_wire[33]) : data_wire[33];
assign wire_mux21_34_dataout = (syndrome[7] == 1'b1) ? (decode_output[41] ^ data_wire[34]) : data_wire[34];
assign wire_mux21_35_dataout = (syndrome[7] == 1'b1) ? (decode_output[42] ^ data_wire[35]) : data_wire[35];
assign wire_mux21_36_dataout = (syndrome[7] == 1'b1) ? (decode_output[43] ^ data_wire[36]) : data_wire[36];
assign wire_mux21_37_dataout = (syndrome[7] == 1'b1) ? (decode_output[44] ^ data_wire[37]) : data_wire[37];
assign wire_mux21_38_dataout = (syndrome[7] == 1'b1) ? (decode_output[45] ^ data_wire[38]) : data_wire[38];
assign wire_mux21_39_dataout = (syndrome[7] == 1'b1) ? (decode_output[46] ^ data_wire[39]) : data_wire[39];
assign wire_mux21_4_dataout = (syndrome[7] == 1'b1) ? (decode_output[9] ^ data_wire[4]) : data_wire[4];
assign wire_mux21_40_dataout = (syndrome[7] == 1'b1) ? (decode_output[47] ^ data_wire[40]) : data_wire[40];
assign wire_mux21_41_dataout = (syndrome[7] == 1'b1) ? (decode_output[48] ^ data_wire[41]) : data_wire[41];
assign wire_mux21_42_dataout = (syndrome[7] == 1'b1) ? (decode_output[49] ^ data_wire[42]) : data_wire[42];
assign wire_mux21_43_dataout = (syndrome[7] == 1'b1) ? (decode_output[50] ^ data_wire[43]) : data_wire[43];
assign wire_mux21_44_dataout = (syndrome[7] == 1'b1) ? (decode_output[51] ^ data_wire[44]) : data_wire[44];
assign wire_mux21_45_dataout = (syndrome[7] == 1'b1) ? (decode_output[52] ^ data_wire[45]) : data_wire[45];
assign wire_mux21_46_dataout = (syndrome[7] == 1'b1) ? (decode_output[53] ^ data_wire[46]) : data_wire[46];
assign wire_mux21_47_dataout = (syndrome[7] == 1'b1) ? (decode_output[54] ^ data_wire[47]) : data_wire[47];
assign wire_mux21_48_dataout = (syndrome[7] == 1'b1) ? (decode_output[55] ^ data_wire[48]) : data_wire[48];
assign wire_mux21_49_dataout = (syndrome[7] == 1'b1) ? (decode_output[56] ^ data_wire[49]) : data_wire[49];
assign wire_mux21_5_dataout = (syndrome[7] == 1'b1) ? (decode_output[10] ^ data_wire[5]) : data_wire[5];
assign wire_mux21_50_dataout = (syndrome[7] == 1'b1) ? (decode_output[57] ^ data_wire[50]) : data_wire[50];
assign wire_mux21_51_dataout = (syndrome[7] == 1'b1) ? (decode_output[58] ^ data_wire[51]) : data_wire[51];
assign wire_mux21_52_dataout = (syndrome[7] == 1'b1) ? (decode_output[59] ^ data_wire[52]) : data_wire[52];
assign wire_mux21_53_dataout = (syndrome[7] == 1'b1) ? (decode_output[60] ^ data_wire[53]) : data_wire[53];
assign wire_mux21_54_dataout = (syndrome[7] == 1'b1) ? (decode_output[61] ^ data_wire[54]) : data_wire[54];
assign wire_mux21_55_dataout = (syndrome[7] == 1'b1) ? (decode_output[62] ^ data_wire[55]) : data_wire[55];
assign wire_mux21_56_dataout = (syndrome[7] == 1'b1) ? (decode_output[63] ^ data_wire[56]) : data_wire[56];
assign wire_mux21_57_dataout = (syndrome[7] == 1'b1) ? (decode_output[65] ^ data_wire[57]) : data_wire[57];
assign wire_mux21_58_dataout = (syndrome[7] == 1'b1) ? (decode_output[66] ^ data_wire[58]) : data_wire[58];
assign wire_mux21_59_dataout = (syndrome[7] == 1'b1) ? (decode_output[67] ^ data_wire[59]) : data_wire[59];
assign wire_mux21_6_dataout = (syndrome[7] == 1'b1) ? (decode_output[11] ^ data_wire[6]) : data_wire[6];
assign wire_mux21_60_dataout = (syndrome[7] == 1'b1) ? (decode_output[68] ^ data_wire[60]) : data_wire[60];
assign wire_mux21_61_dataout = (syndrome[7] == 1'b1) ? (decode_output[69] ^ data_wire[61]) : data_wire[61];
assign wire_mux21_62_dataout = (syndrome[7] == 1'b1) ? (decode_output[70] ^ data_wire[62]) : data_wire[62];
assign wire_mux21_63_dataout = (syndrome[7] == 1'b1) ? (decode_output[71] ^ data_wire[63]) : data_wire[63];
assign wire_mux21_7_dataout = (syndrome[7] == 1'b1) ? (decode_output[12] ^ data_wire[7]) : data_wire[7];
assign wire_mux21_8_dataout = (syndrome[7] == 1'b1) ? (decode_output[13] ^ data_wire[8]) : data_wire[8];
assign wire_mux21_9_dataout = (syndrome[7] == 1'b1) ? (decode_output[14] ^ data_wire[9]) : data_wire[9];
assign
data_bit = data_t[63],
data_t = {(data_t[62] | decode_output[71]), (data_t[61] | decode_output[70]), (data_t[60] | decode_output[69]), (data_t[59] | decode_output[68]), (data_t[58] | decode_output[67]), (data_t[57] | decode_output[66]), (data_t[56] | decode_output[65]), (data_t[55] | decode_output[63]), (data_t[54] | decode_output[62]), (data_t[53] | decode_output[61]), (data_t[52] | decode_output[60]), (data_t[51] | decode_output[59]), (data_t[50] | decode_output[58]), (data_t[49] | decode_output[57]), (data_t[48] | decode_output[56]), (data_t[47] | decode_output[55]), (data_t[46] | decode_output[54]), (data_t[45] | decode_output[53]), (data_t[44] | decode_output[52]), (data_t[43] | decode_output[51]), (data_t[42] | decode_output[50]), (data_t[41] | decode_output[49]), (data_t[40] | decode_output[48]), (data_t[39] | decode_output[47]), (data_t[38] | decode_output[46]), (data_t[37] | decode_output[45]), (data_t[36] | decode_output[44]), (data_t[35] | decode_output[43]), (data_t[34] | decode_output[42]), (data_t[33] | decode_output[41]), (data_t[32] | decode_output[40]), (data_t[31] | decode_output[39]), (data_t[30] | decode_output[38]), (data_t[29] | decode_output[37]), (data_t[28] | decode_output[36]), (data_t[27] | decode_output[35]), (data_t[26] | decode_output[34]), (data_t[25] | decode_output[33]), (data_t[24] | decode_output[31]), (data_t[23] | decode_output[30]), (data_t[22] | decode_output[29]), (data_t[21] | decode_output[28]), (data_t[20] | decode_output[27]), (data_t[19] | decode_output[26]), (data_t[18] | decode_output[25]), (data_t[17] | decode_output[24]), (data_t[16] | decode_output[23]), (data_t[15] | decode_output[22]), (data_t[14] | decode_output[21]), (data_t[13] | decode_output[20]), (data_t[12] | decode_output[19]), (data_t[11] | decode_output[18]), (data_t[10] | decode_output[17]), (data_t[9] | decode_output[15]), (data_t[8] | decode_output[14]), (data_t[7] | decode_output[13]), (data_t[6] | decode_output[12]), (data_t[5] | decode_output[11]), (data_t[4] | decode_output[10]), (data_t[3] | decode_output[9]), (data_t[2]
| decode_output[7]), (data_t[1] | decode_output[6]), (data_t[0] | decode_output[5]), decode_output[3]},
data_wire = data,
decode_output = wire_error_bit_decoder_eq,
err_corrected = err_corrected_wire,
err_corrected_wire = ((syn_bit & syn_e) & data_bit),
err_detected = err_detected_wire,
err_detected_wire = (syn_bit & (~ (syn_e & parity_bit))),
err_fatal = err_fatal_wire,
err_sbe = syn_e,
err_fatal_wire = (err_detected_wire & (~ err_corrected_wire)),
parity_01_wire = {(data_wire[63] ^ parity_01_wire[34]), (data_wire[61] ^ parity_01_wire[33]), (data_wire[59] ^ parity_01_wire[32]), (data_wire[57] ^ parity_01_wire[31]), (data_wire[56] ^ parity_01_wire[30]), (data_wire[54] ^ parity_01_wire[29]), (data_wire[52] ^ parity_01_wire[28]), (data_wire[50] ^ parity_01_wire[27]), (data_wire[48] ^ parity_01_wire[26]), (data_wire[46] ^ parity_01_wire[25]), (data_wire[44] ^ parity_01_wire[24]), (data_wire[42] ^ parity_01_wire[23]), (data_wire[40] ^ parity_01_wire[22]), (data_wire[38] ^ parity_01_wire[21]), (data_wire[36] ^ parity_01_wire[20]), (data_wire[34] ^ parity_01_wire[19]), (data_wire[32] ^ parity_01_wire[18]), (data_wire[30] ^ parity_01_wire[17]), (data_wire[28] ^ parity_01_wire[16]), (data_wire[26] ^ parity_01_wire[15]), (data_wire[25] ^ parity_01_wire[14]), (data_wire[23] ^ parity_01_wire[13]), (data_wire[21] ^ parity_01_wire[12]), (data_wire[19] ^ parity_01_wire[11]), (data_wire[17] ^ parity_01_wire[10]), (data_wire[15] ^ parity_01_wire[9]), (data_wire[13] ^ parity_01_wire[8]), (data_wire[11] ^ parity_01_wire[7]), (data_wire[10] ^ parity_01_wire[6]), (data_wire[8] ^ parity_01_wire[5]), (data_wire[6] ^ parity_01_wire[4]), (data_wire[4] ^ parity_01_wire[3]), (data_wire[3] ^ parity_01_wire[2]), (data_wire[1] ^ parity_01_wire[1]), (data_wire[0] ^ parity_01_wire[0]), data_wire[64]},
parity_02_wire = {((data_wire[62] ^ data_wire[63]) ^ parity_02_wire[16]), ((data_wire[58] ^ data_wire[59]) ^ parity_02_wire[15]), ((data_wire[55] ^ data_wire[56]) ^ parity_02_wire[14]), ((data_wire[51] ^ data_wire[52]) ^ parity_02_wire[13]), ((data_wire[47] ^ data_wire[48]) ^ parity_02_wire[12]), ((data_wire[43] ^ data_wire[44]) ^ parity_02_wire[11]), ((data_wire[39] ^ data_wire[40]) ^ parity_02_wire[10]), ((data_wire[35] ^ data_wire[36]) ^ parity_02_wire[9]), ((data_wire[31] ^ data_wire[32]) ^ parity_02_wire[8]), ((data_wire[27] ^ data_wire[28]) ^ parity_02_wire[7]), ((data_wire[24] ^ data_wire[25]) ^ parity_02_wire[6]), ((data_wire[20] ^ data_wire[21]) ^ parity_02_wire[5]), ((data_wire[16] ^ data_wire[17]) ^ parity_02_wire[4]), ((data_wire[12] ^ data_wire[13]) ^ parity_02_wire[3]), ((data_wire[9] ^ data_wire[10]) ^ parity_02_wire[2]), ((data_wire[5] ^ data_wire[6]) ^ parity_02_wire[1]), ((data_wire[2] ^ data_wire[3]) ^ parity_02_wire[0]), (data_wire[65] ^ data_wire[0])},
parity_03_wire = {((((data_wire[60] ^ data_wire[61]) ^ data_wire[62]) ^ data_wire[63]) ^ parity_03_wire[7]), ((((data_wire[53] ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_03_wire[6]), ((((data_wire[45] ^ data_wire[46]) ^ data_wire[47]) ^ data_wire[48]) ^ parity_03_wire[5]), ((((data_wire[37] ^ data_wire[38]) ^ data_wire[39]) ^ data_wire[40]) ^ parity_03_wire[4]), ((((data_wire[29] ^ data_wire[30]) ^ data_wire[31]) ^ data_wire[32]) ^ parity_03_wire[3]), ((((data_wire[22] ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_03_wire[2]), ((((data_wire[14] ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ parity_03_wire[1]), ((((data_wire[7] ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10]) ^ parity_03_wire[0]), (((data_wire[66] ^ data_wire[1]) ^ data_wire[2]) ^ data_wire[3])},
parity_04_wire = {((((((((data_wire[49] ^ data_wire[50]) ^ data_wire[51]) ^ data_wire[52]) ^ data_wire[53]) ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_04_wire[2]), ((((((((data_wire[33] ^ data_wire[34]) ^ data_wire[35]) ^ data_wire[36]) ^ data_wire[37]) ^ data_wire[38]) ^ data_wire[39]) ^ data_wire[40]) ^ parity_04_wire[1]), ((((((((data_wire[18] ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_04_wire[0]), (((((((data_wire[67] ^ data_wire[4]) ^ data_wire[5]) ^ data_wire[6]) ^ data_wire[7]) ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10])},
parity_05_wire = {((((((((((((((((data_wire[41] ^ data_wire[42]) ^ data_wire[43]) ^ data_wire[44]) ^ data_wire[45]) ^ data_wire[46]) ^ data_wire[47]) ^ data_wire[48]) ^ data_wire[49]) ^ data_wire[50]) ^ data_wire[51]) ^ data_wire[52]) ^ data_wire[53]) ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_05_wire[0]), (((((((((((((((data_wire[68] ^ data_wire[11]) ^ data_wire[12]) ^ data_wire[13]) ^ data_wire[14]) ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ data_wire[18]) ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25])},
parity_06_wire = {(data_wire[56] ^ parity_06_wire[29]), (data_wire[55] ^ parity_06_wire[28]), (data_wire[54] ^ parity_06_wire[27]), (data_wire[53] ^ parity_06_wire[26]), (data_wire[52] ^ parity_06_wire[25]), (data_wire[51] ^ parity_06_wire[24]), (data_wire[50] ^ parity_06_wire[23]), (data_wire[49] ^ parity_06_wire[22]), (data_wire[48] ^ parity_06_wire[21]), (data_wire[47] ^ parity_06_wire[20]), (data_wire[46] ^ parity_06_wire[19]), (data_wire[45] ^ parity_06_wire[18]), (data_wire[44] ^ parity_06_wire[17]), (data_wire[43] ^ parity_06_wire[16]), (data_wire[42] ^ parity_06_wire[15]), (data_wire[41] ^ parity_06_wire[14]), (data_wire[40] ^ parity_06_wire[13]), (data_wire[39] ^ parity_06_wire[12]), (data_wire[38] ^ parity_06_wire[11]), (data_wire[37] ^ parity_06_wire[10]), (data_wire[36] ^ parity_06_wire[9]), (data_wire[35] ^ parity_06_wire[8]), (data_wire[34] ^ parity_06_wire[7]), (data_wire[33] ^ parity_06_wire[6]), (data_wire[32] ^ parity_06_wire[5]), (data_wire[31] ^ parity_06_wire[4]), (data_wire[30] ^ parity_06_wire[3]), (data_wire[29] ^ parity_06_wire[2]), (data_wire[28] ^ parity_06_wire[1]), (data_wire[27] ^ parity_06_wire[0]), (data_wire[69] ^ data_wire[26])},
parity_07_wire = {(data_wire[63] ^ parity_07_wire[5]), (data_wire[62] ^ parity_07_wire[4]), (data_wire[61] ^ parity_07_wire[3]), (data_wire[60] ^ parity_07_wire[2]), (data_wire[59] ^ parity_07_wire[1]), (data_wire[58] ^ parity_07_wire[0]), (data_wire[70] ^ data_wire[57])},
parity_bit = parity_t[6],
parity_final_wire = {(data_wire[70] ^ parity_final_wire[69]), (data_wire[69] ^ parity_final_wire[68]), (data_wire[68] ^ parity_final_wire[67]), (data_wire[67] ^ parity_final_wire[66]), (data_wire[66] ^ parity_final_wire[65]), (data_wire[65] ^ parity_final_wire[64]), (data_wire[64] ^ parity_final_wire[63]), (data_wire[63] ^ parity_final_wire[62]), (data_wire[62] ^ parity_final_wire[61]), (data_wire[61] ^ parity_final_wire[60]), (data_wire[60] ^ parity_final_wire[59]), (data_wire[59] ^ parity_final_wire[58]), (data_wire[58] ^ parity_final_wire[57]), (data_wire[57] ^ parity_final_wire[56]), (data_wire[56] ^ parity_final_wire[55]), (data_wire[55] ^ parity_final_wire[54]), (data_wire[54] ^ parity_final_wire[53]), (data_wire[53] ^ parity_final_wire[52]), (data_wire[52] ^ parity_final_wire[51]), (data_wire[51] ^ parity_final_wire[50]), (data_wire[50] ^ parity_final_wire[49]), (data_wire[49] ^ parity_final_wire[48]), (data_wire[48] ^ parity_final_wire[47]), (data_wire[47] ^ parity_final_wire[46]), (data_wire[46] ^ parity_final_wire[45]), (data_wire[45] ^ parity_final_wire[44]), (data_wire[44] ^ parity_final_wire[43]), (data_wire[43] ^ parity_final_wire[42]), (data_wire[42] ^ parity_final_wire[41]), (data_wire[41] ^ parity_final_wire[40]), (data_wire[40] ^ parity_final_wire[39]), (data_wire[39] ^ parity_final_wire[38]), (data_wire[38] ^ parity_final_wire[37]), (data_wire[37] ^ parity_final_wire[36]), (data_wire[36] ^ parity_final_wire[35]), (data_wire[35] ^ parity_final_wire[34]), (data_wire[34] ^ parity_final_wire[33]), (data_wire[33] ^ parity_final_wire[32]), (data_wire[32] ^ parity_final_wire[31]), (data_wire[31] ^ parity_final_wire[30]), (data_wire[30] ^ parity_final_wire[29]), (data_wire[29] ^ parity_final_wire[28]), (data_wire[28] ^ parity_final_wire[27]), (data_wire[27] ^ parity_final_wire[26]), (data_wire[26] ^ parity_final_wire[25]), (data_wire[25] ^ parity_final_wire[24]), (data_wire[24] ^ parity_final_wire[23]), (data_wire[23] ^ parity_final_wire[22]), (data_wire[22] ^ parity_final_wire[21]), (data_wire[21] ^
parity_final_wire[20]), (data_wire[20] ^ parity_final_wire[19]), (data_wire[19] ^ parity_final_wire[18]), (data_wire[18] ^ parity_final_wire[17]), (data_wire[17] ^ parity_final_wire[16]), (data_wire[16] ^ parity_final_wire[15]), (data_wire[15] ^ parity_final_wire[14]), (data_wire[14] ^ parity_final_wire[13]), (data_wire[13] ^ parity_final_wire[12]), (data_wire[12] ^ parity_final_wire[11]), (data_wire[11] ^ parity_final_wire[10]), (data_wire[10] ^ parity_final_wire[9]), (data_wire[9] ^ parity_final_wire[8]), (data_wire[8] ^ parity_final_wire[7]), (data_wire[7] ^ parity_final_wire[6]), (data_wire[6] ^ parity_final_wire[5]), (data_wire[5] ^ parity_final_wire[4]), (data_wire[4] ^ parity_final_wire[3]), (data_wire[3] ^ parity_final_wire[2]), (data_wire[2] ^ parity_final_wire[1]), (data_wire[1] ^ parity_final_wire[0]), (data_wire[71] ^ data_wire[0])},
parity_t = {(parity_t[5] | decode_output[64]), (parity_t[4] | decode_output[32]), (parity_t[3] | decode_output[16]), (parity_t[2] | decode_output[8]), (parity_t[1] | decode_output[4]), (parity_t[0] | decode_output[2]), decode_output[1]},
q = q_wire,
q_wire = {wire_mux21_63_dataout, wire_mux21_62_dataout, wire_mux21_61_dataout, wire_mux21_60_dataout, wire_mux21_59_dataout, wire_mux21_58_dataout, wire_mux21_57_dataout, wire_mux21_56_dataout, wire_mux21_55_dataout, wire_mux21_54_dataout, wire_mux21_53_dataout, wire_mux21_52_dataout, wire_mux21_51_dataout, wire_mux21_50_dataout, wire_mux21_49_dataout, wire_mux21_48_dataout, wire_mux21_47_dataout, wire_mux21_46_dataout, wire_mux21_45_dataout, wire_mux21_44_dataout, wire_mux21_43_dataout, wire_mux21_42_dataout, wire_mux21_41_dataout, wire_mux21_40_dataout, wire_mux21_39_dataout, wire_mux21_38_dataout, wire_mux21_37_dataout, wire_mux21_36_dataout, wire_mux21_35_dataout, wire_mux21_34_dataout, wire_mux21_33_dataout, wire_mux21_32_dataout, wire_mux21_31_dataout, wire_mux21_30_dataout, wire_mux21_29_dataout, wire_mux21_28_dataout, wire_mux21_27_dataout, wire_mux21_26_dataout, wire_mux21_25_dataout, wire_mux21_24_dataout, wire_mux21_23_dataout, wire_mux21_22_dataout, wire_mux21_21_dataout, wire_mux21_20_dataout, wire_mux21_19_dataout, wire_mux21_18_dataout, wire_mux21_17_dataout, wire_mux21_16_dataout, wire_mux21_15_dataout, wire_mux21_14_dataout, wire_mux21_13_dataout, wire_mux21_12_dataout, wire_mux21_11_dataout, wire_mux21_10_dataout, wire_mux21_9_dataout, wire_mux21_8_dataout, wire_mux21_7_dataout, wire_mux21_6_dataout, wire_mux21_5_dataout, wire_mux21_4_dataout, wire_mux21_3_dataout, wire_mux21_2_dataout, wire_mux21_1_dataout, wire_mux21_0_dataout},
syn_bit = syn_t[5],
syn_e = syndrome[7],
syn_t = {(syn_t[4] | syndrome[6]), (syn_t[3] | syndrome[5]), (syn_t[2] | syndrome[4]), (syn_t[1] | syndrome[3]), (syn_t[0] | syndrome[2]), (syndrome[0] | syndrome[1])},
syndrome = {parity_final_wire[70], parity_07_wire[6], parity_06_wire[30], parity_05_wire[1], parity_04_wire[3], parity_03_wire[8], parity_02_wire[17], parity_01_wire[35]};
endmodule //alt_mem_ddrx_ecc_decoder_64_altecc_decoder
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module alt_mem_ddrx_ecc_decoder_64 (
data,
err_corrected,
err_detected,
err_fatal,
err_sbe,
q)/* synthesis synthesis_clearbox = 1 */;
input [71:0] data;
output err_corrected;
output err_detected;
output err_fatal;
output err_sbe;
output [63:0] q;
wire sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire sub_wire4;
wire [63:0] sub_wire3;
wire err_detected = sub_wire0;
wire err_fatal = sub_wire1;
wire err_corrected = sub_wire2;
wire err_sbe = sub_wire4;
wire [63:0] q = sub_wire3[63:0];
alt_mem_ddrx_ecc_decoder_64_altecc_decoder alt_mem_ddrx_ecc_decoder_64_altecc_decoder_component (
.data (data),
.err_detected (sub_wire0),
.err_fatal (sub_wire1),
.err_corrected (sub_wire2),
.err_sbe (sub_wire4),
.q (sub_wire3));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: CONSTANT: lpm_pipeline NUMERIC "0"
// Retrieval info: CONSTANT: width_codeword NUMERIC "72"
// Retrieval info: CONSTANT: width_dataword NUMERIC "64"
// Retrieval info: USED_PORT: data 0 0 72 0 INPUT NODEFVAL "data[71..0]"
// Retrieval info: USED_PORT: err_corrected 0 0 0 0 OUTPUT NODEFVAL "err_corrected"
// Retrieval info: USED_PORT: err_detected 0 0 0 0 OUTPUT NODEFVAL "err_detected"
// Retrieval info: USED_PORT: err_fatal 0 0 0 0 OUTPUT NODEFVAL "err_fatal"
// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL "q[63..0]"
// Retrieval info: CONNECT: @data 0 0 72 0 data 0 0 72 0
// Retrieval info: CONNECT: err_corrected 0 0 0 0 @err_corrected 0 0 0 0
// Retrieval info: CONNECT: err_detected 0 0 0 0 @err_detected 0 0 0 0
// Retrieval info: CONNECT: err_fatal 0 0 0 0 @err_fatal 0 0 0 0
// Retrieval info: CONNECT: q 0 0 64 0 @q 0 0 64 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_32_syn.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_decoder_64_syn.v TRUE
// Retrieval info: LIB_FILE: lpm
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21BOI_PP_SYMBOL_V
`define SKY130_FD_SC_LS__A21BOI_PP_SYMBOL_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a21boi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21BOI_PP_SYMBOL_V
|
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