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//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcieCore_pcie_top.v
// Version : 1.11
// Description: Solution wrapper for Virtex7 Hard Block for PCI Express
//
//
//
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
module pcieCore_pcie_top # (
// PCIE_2_1 params
parameter PIPE_PIPELINE_STAGES = 0, // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
parameter [11:0] AER_BASE_PTR = 12'h140,
parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE",
parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE",
parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
parameter [15:0] AER_CAP_ID = 16'h0001,
parameter AER_CAP_MULTIHEADER = "FALSE",
parameter [11:0] AER_CAP_NEXTPTR = 12'h178,
parameter AER_CAP_ON = "FALSE",
parameter [23:0] AER_CAP_OPTIONAL_ERR_SUPPORT = 24'h000000,
parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE",
parameter [3:0] AER_CAP_VERSION = 4'h1,
parameter ALLOW_X8_GEN2 = "FALSE",
parameter [31:0] BAR0 = 32'hFFFFFF00,
parameter [31:0] BAR1 = 32'hFFFF0000,
parameter [31:0] BAR2 = 32'hFFFF000C,
parameter [31:0] BAR3 = 32'hFFFFFFFF,
parameter [31:0] BAR4 = 32'h00000000,
parameter [31:0] BAR5 = 32'h00000000,
parameter C_DATA_WIDTH = 64,
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1,
parameter KEEP_WIDTH = C_DATA_WIDTH / 8,
parameter [7:0] CAPABILITIES_PTR = 8'h40,
parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000,
parameter [23:0] CLASS_CODE = 24'h000000,
parameter CFG_ECRC_ERR_CPLSTAT = 0,
parameter CMD_INTX_IMPLEMENTED = "TRUE",
parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE",
parameter [3:0] CPL_TIMEOUT_RANGES_SUPPORTED = 4'h0,
parameter [6:0] CRM_MODULE_RSTS = 7'h00,
parameter DEV_CAP2_ARI_FORWARDING_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED = "FALSE",
parameter DEV_CAP2_CAS128_COMPLETER_SUPPORTED = "FALSE",
parameter DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED = "FALSE",
parameter DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED = "FALSE",
parameter DEV_CAP2_LTR_MECHANISM_SUPPORTED = "FALSE",
parameter [1:0] DEV_CAP2_MAX_ENDEND_TLP_PREFIXES = 2'h0,
parameter DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING = "FALSE",
parameter [1:0] DEV_CAP2_TPH_COMPLETER_SUPPORTED = 2'h0,
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE",
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE",
parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 0,
parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 0,
parameter DEV_CAP_EXT_TAG_SUPPORTED = "TRUE",
parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE",
parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2,
parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0,
parameter integer DEV_CAP_RSVD_14_12 = 0,
parameter integer DEV_CAP_RSVD_17_16 = 0,
parameter integer DEV_CAP_RSVD_31_29 = 0,
parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE",
parameter DEV_CONTROL_EXT_TAG_DEFAULT = "FALSE",
parameter DISABLE_ASPM_L1_TIMER = "FALSE",
parameter DISABLE_BAR_FILTERING = "FALSE",
parameter DISABLE_ERR_MSG = "FALSE",
parameter DISABLE_ID_CHECK = "FALSE",
parameter DISABLE_LANE_REVERSAL = "FALSE",
parameter DISABLE_LOCKED_FILTER = "FALSE",
parameter DISABLE_PPM_FILTER = "FALSE",
parameter DISABLE_RX_POISONED_RESP = "FALSE",
parameter DISABLE_RX_TC_FILTER = "FALSE",
parameter DISABLE_SCRAMBLING = "FALSE",
parameter [7:0] DNSTREAM_LINK_NUM = 8'h00,
parameter [11:0] DSN_BASE_PTR = 12'h100,
parameter [15:0] DSN_CAP_ID = 16'h0003,
parameter [11:0] DSN_CAP_NEXTPTR = 12'h10C,
parameter DSN_CAP_ON = "TRUE",
parameter [3:0] DSN_CAP_VERSION = 4'h1,
parameter [10:0] ENABLE_MSG_ROUTE = 11'h000,
parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE",
parameter ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED = "FALSE",
parameter ENTER_RVRY_EI_L0 = "TRUE",
parameter EXIT_LOOPBACK_ON_EI = "TRUE",
parameter [31:0] EXPANSION_ROM = 32'hFFFFF001,
parameter [5:0] EXT_CFG_CAP_PTR = 6'h3F,
parameter [9:0] EXT_CFG_XP_CAP_PTR = 10'h3FF,
parameter [7:0] HEADER_TYPE = 8'h00,
parameter [4:0] INFER_EI = 5'h00,
parameter [7:0] INTERRUPT_PIN = 8'h01,
parameter INTERRUPT_STAT_AUTO = "TRUE",
parameter IS_SWITCH = "FALSE",
parameter [9:0] LAST_CONFIG_DWORD = 10'h3FF,
parameter LINK_CAP_ASPM_OPTIONALITY = "TRUE",
parameter integer LINK_CAP_ASPM_SUPPORT = 1,
parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE",
parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE",
parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7,
parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7,
parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7,
parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7,
parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE",
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1,
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08,
parameter integer LINK_CAP_RSVD_23 = 0,
parameter integer LINK_CONTROL_RCB = 0,
parameter LINK_CTRL2_DEEMPHASIS = "FALSE",
parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE",
parameter [3:0] LINK_CTRL2_TARGET_LINK_SPEED = 4'h2,
parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE",
parameter [14:0] LL_ACK_TIMEOUT = 15'h0000,
parameter LL_ACK_TIMEOUT_EN = "FALSE",
parameter integer LL_ACK_TIMEOUT_FUNC = 0,
parameter [14:0] LL_REPLAY_TIMEOUT = 15'h0000,
parameter LL_REPLAY_TIMEOUT_EN = "FALSE",
parameter integer LL_REPLAY_TIMEOUT_FUNC = 0,
parameter [5:0] LTSSM_MAX_LINK_WIDTH = 6'h01,
parameter MPS_FORCE = "FALSE",
parameter [7:0] MSIX_BASE_PTR = 8'h9C,
parameter [7:0] MSIX_CAP_ID = 8'h11,
parameter [7:0] MSIX_CAP_NEXTPTR = 8'h00,
parameter MSIX_CAP_ON = "FALSE",
parameter integer MSIX_CAP_PBA_BIR = 0,
parameter [28:0] MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] MSIX_CAP_TABLE_SIZE = 11'h000,
parameter [7:0] MSI_BASE_PTR = 8'h48,
parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE",
parameter [7:0] MSI_CAP_ID = 8'h05,
parameter integer MSI_CAP_MULTIMSGCAP = 0,
parameter integer MSI_CAP_MULTIMSG_EXTENSION = 0,
parameter [7:0] MSI_CAP_NEXTPTR = 8'h60,
parameter MSI_CAP_ON = "FALSE",
parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "TRUE",
parameter integer N_FTS_COMCLK_GEN1 = 255,
parameter integer N_FTS_COMCLK_GEN2 = 255,
parameter integer N_FTS_GEN1 = 255,
parameter integer N_FTS_GEN2 = 255,
parameter [7:0] PCIE_BASE_PTR = 8'h60,
parameter [7:0] PCIE_CAP_CAPABILITY_ID = 8'h10,
parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h2,
parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0,
parameter [7:0] PCIE_CAP_NEXTPTR = 8'h9C,
parameter PCIE_CAP_ON = "TRUE",
parameter integer PCIE_CAP_RSVD_15_14 = 0,
parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE",
parameter integer PCIE_REVISION = 2,
parameter integer PL_AUTO_CONFIG = 0,
parameter PL_FAST_TRAIN = "FALSE",
parameter [14:0] PM_ASPML0S_TIMEOUT = 15'h0000,
parameter PM_ASPML0S_TIMEOUT_EN = "FALSE",
parameter integer PM_ASPML0S_TIMEOUT_FUNC = 0,
parameter PM_ASPM_FASTEXIT = "FALSE",
parameter [7:0] PM_BASE_PTR = 8'h40,
parameter integer PM_CAP_AUXCURRENT = 0,
parameter PM_CAP_D1SUPPORT = "TRUE",
parameter PM_CAP_D2SUPPORT = "TRUE",
parameter PM_CAP_DSI = "FALSE",
parameter [7:0] PM_CAP_ID = 8'h01,
parameter [7:0] PM_CAP_NEXTPTR = 8'h48,
parameter PM_CAP_ON = "TRUE",
parameter [4:0] PM_CAP_PMESUPPORT = 5'h0F,
parameter PM_CAP_PME_CLOCK = "FALSE",
parameter integer PM_CAP_RSVD_04 = 0,
parameter integer PM_CAP_VERSION = 3,
parameter PM_CSR_B2B3 = "FALSE",
parameter PM_CSR_BPCCEN = "FALSE",
parameter PM_CSR_NOSOFTRST = "TRUE",
parameter [7:0] PM_DATA0 = 8'h01,
parameter [7:0] PM_DATA1 = 8'h01,
parameter [7:0] PM_DATA2 = 8'h01,
parameter [7:0] PM_DATA3 = 8'h01,
parameter [7:0] PM_DATA4 = 8'h01,
parameter [7:0] PM_DATA5 = 8'h01,
parameter [7:0] PM_DATA6 = 8'h01,
parameter [7:0] PM_DATA7 = 8'h01,
parameter [1:0] PM_DATA_SCALE0 = 2'h1,
parameter [1:0] PM_DATA_SCALE1 = 2'h1,
parameter [1:0] PM_DATA_SCALE2 = 2'h1,
parameter [1:0] PM_DATA_SCALE3 = 2'h1,
parameter [1:0] PM_DATA_SCALE4 = 2'h1,
parameter [1:0] PM_DATA_SCALE5 = 2'h1,
parameter [1:0] PM_DATA_SCALE6 = 2'h1,
parameter [1:0] PM_DATA_SCALE7 = 2'h1,
parameter PM_MF = "FALSE",
parameter [11:0] RBAR_BASE_PTR = 12'h178,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR0 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR1 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR2 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR3 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR4 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR5 = 5'h00,
parameter [15:0] RBAR_CAP_ID = 16'h0015,
parameter [2:0] RBAR_CAP_INDEX0 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX1 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX2 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX3 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX4 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX5 = 3'h0,
parameter [11:0] RBAR_CAP_NEXTPTR = 12'h000,
parameter RBAR_CAP_ON = "FALSE",
parameter [31:0] RBAR_CAP_SUP0 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP1 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP2 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP3 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP4 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP5 = 32'h00000000,
parameter [3:0] RBAR_CAP_VERSION = 4'h1,
parameter [2:0] RBAR_NUM = 3'h1,
parameter integer RECRC_CHK = 0,
parameter RECRC_CHK_TRIM = "FALSE",
parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE",
parameter [1:0] RP_AUTO_SPD = 2'h1,
parameter [4:0] RP_AUTO_SPD_LOOPCNT = 5'h1f,
parameter SELECT_DLL_IF = "FALSE",
parameter SIM_VERSION = "1.0",
parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE",
parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE",
parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE",
parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE",
parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE",
parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE",
parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE",
parameter [12:0] SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000,
parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE",
parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE",
parameter integer SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0,
parameter [7:0] SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00,
parameter integer SPARE_BIT0 = 0,
parameter integer SPARE_BIT1 = 0,
parameter integer SPARE_BIT2 = 0,
parameter integer SPARE_BIT3 = 0,
parameter integer SPARE_BIT4 = 0,
parameter integer SPARE_BIT5 = 0,
parameter integer SPARE_BIT6 = 0,
parameter integer SPARE_BIT7 = 0,
parameter integer SPARE_BIT8 = 0,
parameter [7:0] SPARE_BYTE0 = 8'h00,
parameter [7:0] SPARE_BYTE1 = 8'h00,
parameter [7:0] SPARE_BYTE2 = 8'h00,
parameter [7:0] SPARE_BYTE3 = 8'h00,
parameter [31:0] SPARE_WORD0 = 32'h00000000,
parameter [31:0] SPARE_WORD1 = 32'h00000000,
parameter [31:0] SPARE_WORD2 = 32'h00000000,
parameter [31:0] SPARE_WORD3 = 32'h00000000,
parameter SSL_MESSAGE_AUTO = "FALSE",
parameter TECRC_EP_INV = "FALSE",
parameter TL_RBYPASS = "FALSE",
parameter integer TL_RX_RAM_RADDR_LATENCY = 0,
parameter integer TL_RX_RAM_RDATA_LATENCY = 2,
parameter integer TL_RX_RAM_WRITE_LATENCY = 0,
parameter TL_TFC_DISABLE = "FALSE",
parameter TL_TX_CHECKS_DISABLE = "FALSE",
parameter integer TL_TX_RAM_RADDR_LATENCY = 0,
parameter integer TL_TX_RAM_RDATA_LATENCY = 2,
parameter integer TL_TX_RAM_WRITE_LATENCY = 0,
parameter TRN_DW = "FALSE",
parameter TRN_NP_FC = "FALSE",
parameter UPCONFIG_CAPABLE = "TRUE",
parameter UPSTREAM_FACING = "TRUE",
parameter UR_ATOMIC = "TRUE",
parameter UR_CFG1 = "TRUE",
parameter UR_INV_REQ = "TRUE",
parameter UR_PRS_RESPONSE = "TRUE",
parameter USER_CLK2_DIV2 = "FALSE",
parameter integer USER_CLK_FREQ = 3,
parameter USE_RID_PINS = "FALSE",
parameter VC0_CPL_INFINITE = "TRUE",
parameter [12:0] VC0_RX_RAM_LIMIT = 13'h03FF,
parameter integer VC0_TOTAL_CREDITS_CD = 127,
parameter integer VC0_TOTAL_CREDITS_CH = 31,
parameter integer VC0_TOTAL_CREDITS_NPD = 24,
parameter integer VC0_TOTAL_CREDITS_NPH = 12,
parameter integer VC0_TOTAL_CREDITS_PD = 288,
parameter integer VC0_TOTAL_CREDITS_PH = 32,
parameter integer VC0_TX_LASTPACKET = 31,
parameter [11:0] VC_BASE_PTR = 12'h10C,
parameter [15:0] VC_CAP_ID = 16'h0002,
parameter [11:0] VC_CAP_NEXTPTR = 12'h000,
parameter VC_CAP_ON = "FALSE",
parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE",
parameter [3:0] VC_CAP_VERSION = 4'h1,
parameter [11:0] VSEC_BASE_PTR = 12'h128,
parameter [15:0] VSEC_CAP_HDR_ID = 16'h1234,
parameter [11:0] VSEC_CAP_HDR_LENGTH = 12'h018,
parameter [3:0] VSEC_CAP_HDR_REVISION = 4'h1,
parameter [15:0] VSEC_CAP_ID = 16'h000B,
parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE",
parameter [11:0] VSEC_CAP_NEXTPTR = 12'h140,
parameter VSEC_CAP_ON = "FALSE",
parameter [3:0] VSEC_CAP_VERSION = 4'h1
)
(
// wrapper input
// Common
output user_clk_out,
input user_reset,
input user_lnk_up,
output trn_lnk_up,
output user_rst_n,
// Tx
output [5:0] tx_buf_av,
output tx_err_drop,
output tx_cfg_req,
output s_axis_tx_tready,
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata,
input [KEEP_WIDTH-1:0] s_axis_tx_tkeep,
input [3:0] s_axis_tx_tuser,
input s_axis_tx_tlast,
input s_axis_tx_tvalid,
input tx_cfg_gnt,
// Rx
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata,
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep,
output m_axis_rx_tlast,
output m_axis_rx_tvalid,
input m_axis_rx_tready,
output [21:0] m_axis_rx_tuser,
input rx_np_ok,
input rx_np_req,
// Flow Control
output [11:0] fc_cpld,
output [7:0] fc_cplh,
output [11:0] fc_npd,
output [7:0] fc_nph,
output [11:0] fc_pd,
output [7:0] fc_ph,
input [2:0] fc_sel,
input wire [1:0] pl_directed_link_change,
input wire [1:0] pl_directed_link_width,
input wire pl_directed_link_speed,
input wire pl_directed_link_auton,
input wire pl_upstream_prefer_deemph,
input wire pl_downstream_deemph_source,
input wire pl_directed_ltssm_new_vld,
input wire [5:0] pl_directed_ltssm_new,
input wire pl_directed_ltssm_stall,
input wire cm_rst_n,
input wire func_lvl_rst_n,
input wire pl_transmit_hot_rst,
input wire [31:0] cfg_mgmt_di,
input wire [3:0] cfg_mgmt_byte_en_n,
input wire [9:0] cfg_mgmt_dwaddr,
input wire cfg_mgmt_wr_rw1c_as_rw_n,
input wire cfg_mgmt_wr_readonly_n,
input wire cfg_mgmt_wr_en_n,
input wire cfg_mgmt_rd_en_n,
input wire cfg_err_malformed_n,
input wire cfg_err_cor_n,
input wire cfg_err_ur_n,
input wire cfg_err_ecrc_n,
input wire cfg_err_cpl_timeout_n,
input wire cfg_err_cpl_abort_n,
input wire cfg_err_cpl_unexpect_n,
input wire cfg_err_poisoned_n,
input wire cfg_err_acs_n,
input wire cfg_err_atomic_egress_blocked_n,
input wire cfg_err_mc_blocked_n,
input wire cfg_err_internal_uncor_n,
input wire cfg_err_internal_cor_n,
input wire cfg_err_posted_n,
input wire cfg_err_locked_n,
input wire cfg_err_norecovery_n,
input wire [127:0] cfg_err_aer_headerlog,
input wire [47:0] cfg_err_tlp_cpl_header,
input wire cfg_interrupt_n,
input wire [7:0] cfg_interrupt_di,
input wire cfg_interrupt_assert_n,
input wire cfg_interrupt_stat_n,
input wire [7:0] cfg_ds_bus_number,
input wire [4:0] cfg_ds_device_number,
input wire [2:0] cfg_ds_function_number,
input wire [7:0] cfg_port_number,
input wire cfg_pm_halt_aspm_l0s_n,
input wire cfg_pm_halt_aspm_l1_n,
input wire cfg_pm_force_state_en_n,
input wire [1:0] cfg_pm_force_state,
input wire cfg_pm_wake_n,
input wire cfg_turnoff_ok,
input wire cfg_pm_send_pme_to_n,
input wire [4:0] cfg_pciecap_interrupt_msgnum,
input wire cfg_trn_pending,
input wire [2:0] cfg_force_mps,
input wire cfg_force_common_clock_off,
input wire cfg_force_extended_sync_on,
input wire [63:0] cfg_dsn,
input wire [4:0] cfg_aer_interrupt_msgnum,
input wire [15:0] cfg_dev_id,
input wire [15:0] cfg_vend_id,
input wire [7:0] cfg_rev_id,
input wire [15:0] cfg_subsys_id,
input wire [15:0] cfg_subsys_vend_id,
input wire drp_clk,
input wire drp_en,
input wire drp_we,
input wire [8:0] drp_addr,
input wire [15:0] drp_di,
output wire drp_rdy,
output wire [15:0] drp_do,
input wire [1:0] dbg_mode,
input wire dbg_sub_mode,
input wire [2:0] pl_dbg_mode ,
output wire pl_sel_lnk_rate,
output wire [1:0] pl_sel_lnk_width,
output wire [5:0] pl_ltssm_state,
output wire [1:0] pl_lane_reversal_mode,
output wire pl_phy_lnk_up,
output wire [2:0] pl_tx_pm_state,
output wire [1:0] pl_rx_pm_state,
output wire pl_link_upcfg_cap,
output wire pl_link_gen2_cap,
output wire pl_link_partner_gen2_supported,
output wire [2:0] pl_initial_link_width,
output wire pl_directed_change_done,
output wire pl_received_hot_rst,
output wire lnk_clk_en,
output wire [31:0] cfg_mgmt_do,
output wire cfg_mgmt_rd_wr_done,
output wire cfg_err_aer_headerlog_set,
output wire cfg_err_cpl_rdy,
output wire cfg_interrupt_rdy,
output wire [2:0] cfg_interrupt_mmenable,
output wire cfg_interrupt_msienable,
output wire [7:0] cfg_interrupt_do,
output wire cfg_interrupt_msixenable,
output wire cfg_interrupt_msixfm,
output wire [7:0] cfg_bus_number,
output wire [4:0] cfg_device_number,
output wire [2:0] cfg_function_number,
output wire [15:0] cfg_status,
output wire [15:0] cfg_command,
output wire [15:0] cfg_dstatus,
output wire [15:0] cfg_dcommand,
output wire [15:0] cfg_lstatus,
output wire [15:0] cfg_lcommand,
output wire [15:0] cfg_dcommand2,
output wire cfg_received_func_lvl_rst,
output wire cfg_msg_received,
output wire [15:0] cfg_msg_data,
output wire cfg_msg_received_err_cor,
output wire cfg_msg_received_err_non_fatal,
output wire cfg_msg_received_err_fatal,
output wire cfg_msg_received_assert_int_a,
output wire cfg_msg_received_deassert_int_a,
output wire cfg_msg_received_assert_int_b,
output wire cfg_msg_received_deassert_int_b,
output wire cfg_msg_received_assert_int_c,
output wire cfg_msg_received_deassert_int_c,
output wire cfg_msg_received_assert_int_d,
output wire cfg_msg_received_deassert_int_d,
output wire cfg_msg_received_pm_pme,
output wire cfg_msg_received_pme_to_ack,
output wire cfg_msg_received_pme_to,
output wire cfg_msg_received_setslotpowerlimit,
output wire cfg_msg_received_unlock,
output wire cfg_msg_received_pm_as_nak,
output wire cfg_to_turnoff,
output wire [2:0] cfg_pcie_link_state,
output wire cfg_pm_rcv_as_req_l1_n,
output wire cfg_pm_rcv_enter_l1_n,
output wire cfg_pm_rcv_enter_l23_n,
output wire cfg_pm_rcv_req_ack_n,
output wire [1:0] cfg_pmcsr_powerstate,
output wire cfg_pmcsr_pme_en,
output wire cfg_pmcsr_pme_status,
output wire cfg_transaction,
output wire cfg_transaction_type,
output wire [6:0] cfg_transaction_addr,
output wire cfg_command_io_enable,
output wire cfg_command_mem_enable,
output wire cfg_command_bus_master_enable,
output wire cfg_command_interrupt_disable,
output wire cfg_command_serr_en,
output wire cfg_bridge_serr_en,
output wire cfg_dev_status_corr_err_detected,
output wire cfg_dev_status_non_fatal_err_detected,
output wire cfg_dev_status_fatal_err_detected,
output wire cfg_dev_status_ur_detected,
output wire cfg_dev_control_corr_err_reporting_en,
output wire cfg_dev_control_non_fatal_reporting_en,
output wire cfg_dev_control_fatal_err_reporting_en,
output wire cfg_dev_control_ur_err_reporting_en,
output wire cfg_dev_control_enable_ro,
output wire [2:0] cfg_dev_control_max_payload,
output wire cfg_dev_control_ext_tag_en,
output wire cfg_dev_control_phantom_en,
output wire cfg_dev_control_aux_power_en,
output wire cfg_dev_control_no_snoop_en,
output wire [2:0] cfg_dev_control_max_read_req,
output wire [1:0] cfg_link_status_current_speed,
output wire [3:0] cfg_link_status_negotiated_width,
output wire cfg_link_status_link_training,
output wire cfg_link_status_dll_active,
output wire cfg_link_status_bandwidth_status,
output wire cfg_link_status_auto_bandwidth_status,
output wire [1:0] cfg_link_control_aspm_control,
output wire cfg_link_control_rcb,
output wire cfg_link_control_link_disable,
output wire cfg_link_control_retrain_link,
output wire cfg_link_control_common_clock,
output wire cfg_link_control_extended_sync,
output wire cfg_link_control_clock_pm_en,
output wire cfg_link_control_hw_auto_width_dis,
output wire cfg_link_control_bandwidth_int_en,
output wire cfg_link_control_auto_bandwidth_int_en,
output wire [3:0] cfg_dev_control2_cpl_timeout_val,
output wire cfg_dev_control2_cpl_timeout_dis,
output wire cfg_dev_control2_ari_forward_en,
output wire cfg_dev_control2_atomic_requester_en,
output wire cfg_dev_control2_atomic_egress_block,
output wire cfg_dev_control2_ido_req_en,
output wire cfg_dev_control2_ido_cpl_en,
output wire cfg_dev_control2_ltr_en,
output wire cfg_dev_control2_tlp_prefix_block,
output wire cfg_slot_control_electromech_il_ctl_pulse,
output wire cfg_root_control_syserr_corr_err_en,
output wire cfg_root_control_syserr_non_fatal_err_en,
output wire cfg_root_control_syserr_fatal_err_en,
output wire cfg_root_control_pme_int_en,
output wire cfg_aer_ecrc_check_en,
output wire cfg_aer_ecrc_gen_en,
output wire cfg_aer_rooterr_corr_err_reporting_en,
output wire cfg_aer_rooterr_non_fatal_err_reporting_en,
output wire cfg_aer_rooterr_fatal_err_reporting_en,
output wire cfg_aer_rooterr_corr_err_received,
output wire cfg_aer_rooterr_non_fatal_err_received,
output wire cfg_aer_rooterr_fatal_err_received,
output wire [6:0] cfg_vc_tcvc_map,
output wire [63:0] dbg_vec_a,
output wire [63:0] dbg_vec_b,
output wire [11:0] dbg_vec_c,
output wire dbg_sclr_a,
output wire dbg_sclr_b,
output wire dbg_sclr_c,
output wire dbg_sclr_d,
output wire dbg_sclr_e,
output wire dbg_sclr_f,
output wire dbg_sclr_g,
output wire dbg_sclr_h,
output wire dbg_sclr_i,
output wire dbg_sclr_j,
output wire dbg_sclr_k,
output wire [63:0] trn_rdllp_data,
output wire [1:0] trn_rdllp_src_rdy,
output wire [11:0] pl_dbg_vec,
input phy_rdy_n,
input pipe_clk,
input user_clk,
input user_clk2,
output wire pipe_rx0_polarity_gt,
output wire pipe_rx1_polarity_gt,
output wire pipe_rx2_polarity_gt,
output wire pipe_rx3_polarity_gt,
output wire pipe_rx4_polarity_gt,
output wire pipe_rx5_polarity_gt,
output wire pipe_rx6_polarity_gt,
output wire pipe_rx7_polarity_gt,
output wire pipe_tx_deemph_gt,
output wire [2:0] pipe_tx_margin_gt,
output wire pipe_tx_rate_gt,
output wire pipe_tx_rcvr_det_gt,
output wire [1:0] pipe_tx0_char_is_k_gt,
output wire pipe_tx0_compliance_gt,
output wire [15:0] pipe_tx0_data_gt,
output wire pipe_tx0_elec_idle_gt,
output wire [1:0] pipe_tx0_powerdown_gt,
output wire [1:0] pipe_tx1_char_is_k_gt,
output wire pipe_tx1_compliance_gt,
output wire [15:0] pipe_tx1_data_gt,
output wire pipe_tx1_elec_idle_gt,
output wire [1:0] pipe_tx1_powerdown_gt,
output wire [1:0] pipe_tx2_char_is_k_gt,
output wire pipe_tx2_compliance_gt,
output wire [15:0] pipe_tx2_data_gt,
output wire pipe_tx2_elec_idle_gt,
output wire [1:0] pipe_tx2_powerdown_gt,
output wire [1:0] pipe_tx3_char_is_k_gt,
output wire pipe_tx3_compliance_gt,
output wire [15:0] pipe_tx3_data_gt,
output wire pipe_tx3_elec_idle_gt,
output wire [1:0] pipe_tx3_powerdown_gt,
output wire [1:0] pipe_tx4_char_is_k_gt,
output wire pipe_tx4_compliance_gt,
output wire [15:0] pipe_tx4_data_gt,
output wire pipe_tx4_elec_idle_gt,
output wire [1:0] pipe_tx4_powerdown_gt,
output wire [1:0] pipe_tx5_char_is_k_gt,
output wire pipe_tx5_compliance_gt,
output wire [15:0] pipe_tx5_data_gt,
output wire pipe_tx5_elec_idle_gt,
output wire [1:0] pipe_tx5_powerdown_gt,
output wire [1:0] pipe_tx6_char_is_k_gt,
output wire pipe_tx6_compliance_gt,
output wire [15:0] pipe_tx6_data_gt,
output wire pipe_tx6_elec_idle_gt,
output wire [1:0] pipe_tx6_powerdown_gt,
output wire [1:0] pipe_tx7_char_is_k_gt,
output wire pipe_tx7_compliance_gt,
output wire [15:0] pipe_tx7_data_gt,
output wire pipe_tx7_elec_idle_gt,
output wire [1:0] pipe_tx7_powerdown_gt,
input wire pipe_rx0_chanisaligned_gt,
input wire [1:0] pipe_rx0_char_is_k_gt,
input wire [15:0] pipe_rx0_data_gt,
input wire pipe_rx0_elec_idle_gt,
input wire pipe_rx0_phy_status_gt,
input wire [2:0] pipe_rx0_status_gt,
input wire pipe_rx0_valid_gt,
input wire pipe_rx1_chanisaligned_gt,
input wire [1:0] pipe_rx1_char_is_k_gt,
input wire [15:0] pipe_rx1_data_gt,
input wire pipe_rx1_elec_idle_gt,
input wire pipe_rx1_phy_status_gt,
input wire [2:0] pipe_rx1_status_gt,
input wire pipe_rx1_valid_gt,
input wire pipe_rx2_chanisaligned_gt,
input wire [1:0] pipe_rx2_char_is_k_gt,
input wire [15:0] pipe_rx2_data_gt,
input wire pipe_rx2_elec_idle_gt,
input wire pipe_rx2_phy_status_gt,
input wire [2:0] pipe_rx2_status_gt,
input wire pipe_rx2_valid_gt,
input wire pipe_rx3_chanisaligned_gt,
input wire [1:0] pipe_rx3_char_is_k_gt,
input wire [15:0] pipe_rx3_data_gt,
input wire pipe_rx3_elec_idle_gt,
input wire pipe_rx3_phy_status_gt,
input wire [2:0] pipe_rx3_status_gt,
input wire pipe_rx3_valid_gt,
input wire pipe_rx4_chanisaligned_gt,
input wire [1:0] pipe_rx4_char_is_k_gt,
input wire [15:0] pipe_rx4_data_gt,
input wire pipe_rx4_elec_idle_gt,
input wire pipe_rx4_phy_status_gt,
input wire [2:0] pipe_rx4_status_gt,
input wire pipe_rx4_valid_gt,
input wire pipe_rx5_chanisaligned_gt,
input wire [1:0] pipe_rx5_char_is_k_gt,
input wire [15:0] pipe_rx5_data_gt,
input wire pipe_rx5_elec_idle_gt,
input wire pipe_rx5_phy_status_gt,
input wire [2:0] pipe_rx5_status_gt,
input wire pipe_rx5_valid_gt,
input wire pipe_rx6_chanisaligned_gt,
input wire [1:0] pipe_rx6_char_is_k_gt,
input wire [15:0] pipe_rx6_data_gt,
input wire pipe_rx6_elec_idle_gt,
input wire pipe_rx6_phy_status_gt,
input wire [2:0] pipe_rx6_status_gt,
input wire pipe_rx6_valid_gt,
input wire pipe_rx7_chanisaligned_gt,
input wire [1:0] pipe_rx7_char_is_k_gt,
input wire [15:0] pipe_rx7_data_gt,
input wire pipe_rx7_elec_idle_gt,
input wire pipe_rx7_phy_status_gt,
input wire [2:0] pipe_rx7_status_gt,
input wire pipe_rx7_valid_gt
);
//wire declaration
// TRN Interface
wire [C_DATA_WIDTH-1:0] trn_td;
wire [REM_WIDTH-1:0] trn_trem;
wire trn_tsof;
wire trn_teof;
wire trn_tsrc_rdy;
wire trn_tsrc_dsc;
wire trn_terrfwd;
wire trn_tecrc_gen;
wire trn_tstr;
wire trn_tcfg_gnt;
wire [C_DATA_WIDTH-1:0] trn_rd;
wire [REM_WIDTH-1:0] trn_rrem;
wire trn_rdst_rdy;
wire trn_rsof;
wire trn_reof;
wire trn_rsrc_rdy;
wire trn_rsrc_dsc;
wire trn_rerrfwd;
wire [7:0] trn_rbar_hit;
wire sys_reset_n_d;
wire [1:0] pipe_rx0_char_is_k;
wire [1:0] pipe_rx1_char_is_k;
wire [1:0] pipe_rx2_char_is_k;
wire [1:0] pipe_rx3_char_is_k;
wire [1:0] pipe_rx4_char_is_k;
wire [1:0] pipe_rx5_char_is_k;
wire [1:0] pipe_rx6_char_is_k;
wire [1:0] pipe_rx7_char_is_k;
wire pipe_rx0_valid;
wire pipe_rx1_valid;
wire pipe_rx2_valid;
wire pipe_rx3_valid;
wire pipe_rx4_valid;
wire pipe_rx5_valid;
wire pipe_rx6_valid;
wire pipe_rx7_valid;
wire [15:0] pipe_rx0_data;
wire [15:0] pipe_rx1_data;
wire [15:0] pipe_rx2_data;
wire [15:0] pipe_rx3_data;
wire [15:0] pipe_rx4_data;
wire [15:0] pipe_rx5_data;
wire [15:0] pipe_rx6_data;
wire [15:0] pipe_rx7_data;
wire pipe_rx0_chanisaligned;
wire pipe_rx1_chanisaligned;
wire pipe_rx2_chanisaligned;
wire pipe_rx3_chanisaligned;
wire pipe_rx4_chanisaligned;
wire pipe_rx5_chanisaligned;
wire pipe_rx6_chanisaligned;
wire pipe_rx7_chanisaligned;
wire [2:0] pipe_rx0_status;
wire [2:0] pipe_rx1_status;
wire [2:0] pipe_rx2_status;
wire [2:0] pipe_rx3_status;
wire [2:0] pipe_rx4_status;
wire [2:0] pipe_rx5_status;
wire [2:0] pipe_rx6_status;
wire [2:0] pipe_rx7_status;
wire pipe_rx0_phy_status;
wire pipe_rx1_phy_status;
wire pipe_rx2_phy_status;
wire pipe_rx3_phy_status;
wire pipe_rx4_phy_status;
wire pipe_rx5_phy_status;
wire pipe_rx6_phy_status;
wire pipe_rx7_phy_status;
wire pipe_rx0_elec_idle;
wire pipe_rx1_elec_idle;
wire pipe_rx2_elec_idle;
wire pipe_rx3_elec_idle;
wire pipe_rx4_elec_idle;
wire pipe_rx5_elec_idle;
wire pipe_rx6_elec_idle;
wire pipe_rx7_elec_idle;
wire pipe_tx_reset;
wire pipe_tx_rate;
wire pipe_tx_deemph;
wire [2:0] pipe_tx_margin;
wire pipe_rx0_polarity;
wire pipe_rx1_polarity;
wire pipe_rx2_polarity;
wire pipe_rx3_polarity;
wire pipe_rx4_polarity;
wire pipe_rx5_polarity;
wire pipe_rx6_polarity;
wire pipe_rx7_polarity;
wire pipe_tx0_compliance;
wire pipe_tx1_compliance;
wire pipe_tx2_compliance;
wire pipe_tx3_compliance;
wire pipe_tx4_compliance;
wire pipe_tx5_compliance;
wire pipe_tx6_compliance;
wire pipe_tx7_compliance;
wire [1:0] pipe_tx0_char_is_k;
wire [1:0] pipe_tx1_char_is_k;
wire [1:0] pipe_tx2_char_is_k;
wire [1:0] pipe_tx3_char_is_k;
wire [1:0] pipe_tx4_char_is_k;
wire [1:0] pipe_tx5_char_is_k;
wire [1:0] pipe_tx6_char_is_k;
wire [1:0] pipe_tx7_char_is_k;
wire [15:0] pipe_tx0_data;
wire [15:0] pipe_tx1_data;
wire [15:0] pipe_tx2_data;
wire [15:0] pipe_tx3_data;
wire [15:0] pipe_tx4_data;
wire [15:0] pipe_tx5_data;
wire [15:0] pipe_tx6_data;
wire [15:0] pipe_tx7_data;
wire pipe_tx0_elec_idle;
wire pipe_tx1_elec_idle;
wire pipe_tx2_elec_idle;
wire pipe_tx3_elec_idle;
wire pipe_tx4_elec_idle;
wire pipe_tx5_elec_idle;
wire pipe_tx6_elec_idle;
wire pipe_tx7_elec_idle;
wire [1:0] pipe_tx0_powerdown;
wire [1:0] pipe_tx1_powerdown;
wire [1:0] pipe_tx2_powerdown;
wire [1:0] pipe_tx3_powerdown;
wire [1:0] pipe_tx4_powerdown;
wire [1:0] pipe_tx5_powerdown;
wire [1:0] pipe_tx6_powerdown;
wire [1:0] pipe_tx7_powerdown;
wire cfg_received_func_lvl_rst_n;
wire cfg_err_cpl_rdy_n;
wire cfg_interrupt_rdy_n;
reg [7:0] cfg_bus_number_d;
reg [4:0] cfg_device_number_d;
reg [2:0] cfg_function_number_d;
wire cfg_mgmt_rd_wr_done_n;
wire pl_phy_lnk_up_n;
wire cfg_err_aer_headerlog_set_n;
assign cfg_received_func_lvl_rst = ~cfg_received_func_lvl_rst_n;
assign cfg_err_cpl_rdy = ~cfg_err_cpl_rdy_n;
assign cfg_interrupt_rdy = ~cfg_interrupt_rdy_n;
assign cfg_mgmt_rd_wr_done = ~cfg_mgmt_rd_wr_done_n;
assign pl_phy_lnk_up = ~pl_phy_lnk_up_n;
assign cfg_err_aer_headerlog_set = ~cfg_err_aer_headerlog_set_n;
assign cfg_to_turnoff = cfg_msg_received_pme_to;
assign cfg_status = {16'b0};
assign cfg_command = {5'b0,
cfg_command_interrupt_disable,
1'b0,
cfg_command_serr_en,
5'b0,
cfg_command_bus_master_enable,
cfg_command_mem_enable,
cfg_command_io_enable};
assign cfg_dstatus = {10'h0,
cfg_trn_pending,
1'b0,
cfg_dev_status_ur_detected,
cfg_dev_status_fatal_err_detected,
cfg_dev_status_non_fatal_err_detected,
cfg_dev_status_corr_err_detected};
assign cfg_dcommand = {1'b0,
cfg_dev_control_max_read_req,
cfg_dev_control_no_snoop_en,
cfg_dev_control_aux_power_en,
cfg_dev_control_phantom_en,
cfg_dev_control_ext_tag_en,
cfg_dev_control_max_payload,
cfg_dev_control_enable_ro,
cfg_dev_control_ur_err_reporting_en,
cfg_dev_control_fatal_err_reporting_en,
cfg_dev_control_non_fatal_reporting_en,
cfg_dev_control_corr_err_reporting_en };
assign cfg_lstatus = {cfg_link_status_auto_bandwidth_status,
cfg_link_status_bandwidth_status,
cfg_link_status_dll_active,
(LINK_STATUS_SLOT_CLOCK_CONFIG == "TRUE") ? 1'b1 : 1'b0,
cfg_link_status_link_training,
1'b0,
{2'b00, cfg_link_status_negotiated_width},
{2'b00, cfg_link_status_current_speed} };
assign cfg_lcommand = {4'b0,
cfg_link_control_auto_bandwidth_int_en,
cfg_link_control_bandwidth_int_en,
cfg_link_control_hw_auto_width_dis,
cfg_link_control_clock_pm_en,
cfg_link_control_extended_sync,
cfg_link_control_common_clock,
cfg_link_control_retrain_link,
cfg_link_control_link_disable,
cfg_link_control_rcb,
1'b0,
cfg_link_control_aspm_control};
assign cfg_bus_number = cfg_bus_number_d;
assign cfg_device_number = cfg_device_number_d;
assign cfg_function_number = cfg_function_number_d;
assign cfg_dcommand2 = {4'b0,
cfg_dev_control2_tlp_prefix_block,
cfg_dev_control2_ltr_en,
cfg_dev_control2_ido_cpl_en,
cfg_dev_control2_ido_req_en,
cfg_dev_control2_atomic_egress_block,
cfg_dev_control2_atomic_requester_en,
cfg_dev_control2_ari_forward_en,
cfg_dev_control2_cpl_timeout_dis,
cfg_dev_control2_cpl_timeout_val};
// Capture Bus/Device/Function number
always @(posedge user_clk_out) begin
if (~user_lnk_up)
begin
cfg_bus_number_d <= 8'b0;
end // if (~user_lnk_up)
else if (~cfg_msg_received)
begin
cfg_bus_number_d <= cfg_msg_data[15:8];
end // if (~cfg_msg_received)
end
always @(posedge user_clk_out) begin
if (~user_lnk_up)
begin
cfg_device_number_d <= 5'b0;
end // if (~user_lnk_up)
else if (~cfg_msg_received)
begin
cfg_device_number_d <= cfg_msg_data[7:3];
end // if (~cfg_msg_received)
end
always @(posedge user_clk_out) begin
if (~user_lnk_up)
begin
cfg_function_number_d <= 3'b0;
end // if (~user_lnk_up)
else if (~cfg_msg_received)
begin
cfg_function_number_d <= cfg_msg_data[2:0];
end // if (~cfg_msg_received)
end
pcieCore_axi_basic_top #(
.C_DATA_WIDTH (C_DATA_WIDTH), // RX/TX interface data width
.C_FAMILY ("X7"), // Targeted FPGA family
.C_ROOT_PORT ("FALSE"), // PCIe block is in root port mode
.C_PM_PRIORITY ("FALSE") // Disable TX packet boundary thrtl
) axi_basic_top (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
.s_axis_tx_tdata (s_axis_tx_tdata), // input
.s_axis_tx_tvalid (s_axis_tx_tvalid), // input
.s_axis_tx_tready (s_axis_tx_tready), // output
.s_axis_tx_tkeep (s_axis_tx_tkeep), // input
.s_axis_tx_tlast (s_axis_tx_tlast), // input
.s_axis_tx_tuser (s_axis_tx_tuser), // input
// AXI RX
//-----------
.m_axis_rx_tdata (m_axis_rx_tdata), // output
.m_axis_rx_tvalid (m_axis_rx_tvalid), // output
.m_axis_rx_tready (m_axis_rx_tready), // input
.m_axis_rx_tkeep (m_axis_rx_tkeep), // output
.m_axis_rx_tlast (m_axis_rx_tlast), // output
.m_axis_rx_tuser (m_axis_rx_tuser), // output
// User Misc.
//-----------
.user_turnoff_ok (cfg_turnoff_ok), // input
.user_tcfg_gnt (tx_cfg_gnt), // input
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
.trn_td (trn_td), // output
.trn_tsof (trn_tsof), // output
.trn_teof (trn_teof), // output
.trn_tsrc_rdy (trn_tsrc_rdy), // output
.trn_tdst_rdy (trn_tdst_rdy), // input
.trn_tsrc_dsc (trn_tsrc_dsc), // output
.trn_trem (trn_trem), // output
.trn_terrfwd (trn_terrfwd), // output
.trn_tstr (trn_tstr), // output
.trn_tbuf_av (tx_buf_av), // input
.trn_tecrc_gen (trn_tecrc_gen), // output
// TRN RX
//-----------
.trn_rd (trn_rd), // input
.trn_rsof (trn_rsof), // input
.trn_reof (trn_reof), // input
.trn_rsrc_rdy (trn_rsrc_rdy), // input
.trn_rdst_rdy (trn_rdst_rdy), // output
.trn_rsrc_dsc (trn_rsrc_dsc), // input
.trn_rrem (trn_rrem), // input
.trn_rerrfwd (trn_rerrfwd), // input
.trn_rbar_hit (trn_rbar_hit[6:0]), // input
.trn_recrc_err (trn_recrc_err), // input
// TRN Misc.
//-----------
.trn_tcfg_req ( tx_cfg_req ), // input
.trn_tcfg_gnt ( trn_tcfg_gnt), // output
.trn_lnk_up ( user_lnk_up), // input
// Fuji3/Virtex6 PM
//-----------
.cfg_pcie_link_state (cfg_pcie_link_state), // input
// Virtex6 PM
//-----------
.cfg_pm_send_pme_to (1'b0), // input NOT USED FOR EP
.cfg_pmcsr_powerstate (cfg_pmcsr_powerstate), // input
.trn_rdllp_data (32'b0), // input - Not used in 7-series
.trn_rdllp_src_rdy (1'b0), // input -- Not used in 7-series
// Power Mgmt for S6/V6
//-----------
.cfg_to_turnoff (cfg_to_turnoff), // input
.cfg_turnoff_ok (cfg_turnoff_ok_w), // output
// System
//-----------
.user_clk (user_clk_out), // input
.user_rst (user_reset), // input
.np_counter () // output
);
//-------------------------------------------------------
// PCI Express Pipe Wrapper
//-------------------------------------------------------
pcieCore_pcie_7x # (
.AER_BASE_PTR ( AER_BASE_PTR ),
.AER_CAP_ECRC_CHECK_CAPABLE ( AER_CAP_ECRC_CHECK_CAPABLE ),
.AER_CAP_ECRC_GEN_CAPABLE( AER_CAP_ECRC_GEN_CAPABLE ),
.AER_CAP_ID ( AER_CAP_ID ),
.AER_CAP_MULTIHEADER ( AER_CAP_MULTIHEADER ),
.AER_CAP_NEXTPTR ( AER_CAP_NEXTPTR ),
.AER_CAP_ON ( AER_CAP_ON ),
.AER_CAP_OPTIONAL_ERR_SUPPORT ( AER_CAP_OPTIONAL_ERR_SUPPORT ),
.AER_CAP_PERMIT_ROOTERR_UPDATE ( AER_CAP_PERMIT_ROOTERR_UPDATE ),
.AER_CAP_VERSION ( AER_CAP_VERSION ),
.ALLOW_X8_GEN2 (ALLOW_X8_GEN2),
.BAR0 ( BAR0 ),
.BAR1 ( BAR1 ),
.BAR2 ( BAR2 ),
.BAR3 ( BAR3 ),
.BAR4 ( BAR4 ),
.BAR5 ( BAR5 ),
.C_DATA_WIDTH ( C_DATA_WIDTH ),
.CAPABILITIES_PTR( CAPABILITIES_PTR ),
.CFG_ECRC_ERR_CPLSTAT ( CFG_ECRC_ERR_CPLSTAT ),
.CARDBUS_CIS_POINTER ( CARDBUS_CIS_POINTER ),
.CLASS_CODE ( CLASS_CODE ),
.CMD_INTX_IMPLEMENTED ( CMD_INTX_IMPLEMENTED ),
.CPL_TIMEOUT_DISABLE_SUPPORTED ( CPL_TIMEOUT_DISABLE_SUPPORTED ),
.CPL_TIMEOUT_RANGES_SUPPORTED ( CPL_TIMEOUT_RANGES_SUPPORTED ),
.CRM_MODULE_RSTS (CRM_MODULE_RSTS),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ),
.DEV_CAP_ENDPOINT_L0S_LATENCY ( DEV_CAP_ENDPOINT_L0S_LATENCY ),
.DEV_CAP_ENDPOINT_L1_LATENCY ( DEV_CAP_ENDPOINT_L1_LATENCY ),
.DEV_CAP_EXT_TAG_SUPPORTED ( DEV_CAP_EXT_TAG_SUPPORTED ),
.DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ( DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ),
.DEV_CAP_MAX_PAYLOAD_SUPPORTED ( DEV_CAP_MAX_PAYLOAD_SUPPORTED ),
.DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ( DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ),
.DEV_CAP_ROLE_BASED_ERROR( DEV_CAP_ROLE_BASED_ERROR ),
.DEV_CAP_RSVD_14_12 ( DEV_CAP_RSVD_14_12 ),
.DEV_CAP_RSVD_17_16 ( DEV_CAP_RSVD_17_16 ),
.DEV_CAP_RSVD_31_29 ( DEV_CAP_RSVD_31_29 ),
.DEV_CONTROL_AUX_POWER_SUPPORTED ( DEV_CONTROL_AUX_POWER_SUPPORTED ),
.DEV_CONTROL_EXT_TAG_DEFAULT ( DEV_CONTROL_EXT_TAG_DEFAULT ),
.DISABLE_ASPM_L1_TIMER ( DISABLE_ASPM_L1_TIMER ),
.DISABLE_BAR_FILTERING ( DISABLE_BAR_FILTERING ),
.DISABLE_ID_CHECK( DISABLE_ID_CHECK ),
.DISABLE_LANE_REVERSAL ( DISABLE_LANE_REVERSAL ),
.DISABLE_RX_POISONED_RESP (DISABLE_RX_POISONED_RESP),
.DISABLE_RX_TC_FILTER ( DISABLE_RX_TC_FILTER ),
.DISABLE_SCRAMBLING ( DISABLE_SCRAMBLING ),
.DNSTREAM_LINK_NUM ( DNSTREAM_LINK_NUM ),
.DSN_BASE_PTR ( DSN_BASE_PTR ),
.DSN_CAP_ID ( DSN_CAP_ID ),
.DSN_CAP_NEXTPTR ( DSN_CAP_NEXTPTR ),
.DSN_CAP_ON ( DSN_CAP_ON ),
.DSN_CAP_VERSION ( DSN_CAP_VERSION ),
.DEV_CAP2_ARI_FORWARDING_SUPPORTED(DEV_CAP2_ARI_FORWARDING_SUPPORTED),
.DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED (DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED),
.DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED (DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED),
.DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED (DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED),
.DEV_CAP2_CAS128_COMPLETER_SUPPORTED (DEV_CAP2_CAS128_COMPLETER_SUPPORTED),
.DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED (DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED),
.DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED (DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED),
.DEV_CAP2_LTR_MECHANISM_SUPPORTED (DEV_CAP2_LTR_MECHANISM_SUPPORTED),
.DEV_CAP2_MAX_ENDEND_TLP_PREFIXES (DEV_CAP2_MAX_ENDEND_TLP_PREFIXES),
.DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING (DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING),
.DEV_CAP2_TPH_COMPLETER_SUPPORTED (DEV_CAP2_TPH_COMPLETER_SUPPORTED),
.DISABLE_ERR_MSG (DISABLE_ERR_MSG),
.DISABLE_LOCKED_FILTER (DISABLE_LOCKED_FILTER),
.DISABLE_PPM_FILTER (DISABLE_PPM_FILTER),
.ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED (ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED),
.ENABLE_MSG_ROUTE( ENABLE_MSG_ROUTE ),
.ENABLE_RX_TD_ECRC_TRIM ( ENABLE_RX_TD_ECRC_TRIM ),
.ENTER_RVRY_EI_L0( ENTER_RVRY_EI_L0 ),
.EXIT_LOOPBACK_ON_EI (EXIT_LOOPBACK_ON_EI),
.EXPANSION_ROM ( EXPANSION_ROM ),
.EXT_CFG_CAP_PTR ( EXT_CFG_CAP_PTR ),
.EXT_CFG_XP_CAP_PTR ( EXT_CFG_XP_CAP_PTR ),
.HEADER_TYPE ( HEADER_TYPE ),
.INFER_EI( INFER_EI ),
.INTERRUPT_PIN ( INTERRUPT_PIN ),
.INTERRUPT_STAT_AUTO (INTERRUPT_STAT_AUTO),
.IS_SWITCH ( IS_SWITCH ),
.LAST_CONFIG_DWORD ( LAST_CONFIG_DWORD ),
.LINK_CAP_ASPM_OPTIONALITY ( LINK_CAP_ASPM_OPTIONALITY ),
.LINK_CAP_ASPM_SUPPORT ( LINK_CAP_ASPM_SUPPORT ),
.LINK_CAP_CLOCK_POWER_MANAGEMENT ( LINK_CAP_CLOCK_POWER_MANAGEMENT ),
.LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ( LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ),
.LINK_CAP_L0S_EXIT_LATENCY_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_GEN1 ),
.LINK_CAP_L0S_EXIT_LATENCY_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_GEN2 ),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ),
.LINK_CAP_L1_EXIT_LATENCY_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_GEN1 ),
.LINK_CAP_L1_EXIT_LATENCY_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_GEN2 ),
.LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP (LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP),
.LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ),
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.LINK_CAP_RSVD_23( LINK_CAP_RSVD_23 ),
.LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ( LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ),
.LINK_CONTROL_RCB( LINK_CONTROL_RCB ),
.LINK_CTRL2_DEEMPHASIS ( LINK_CTRL2_DEEMPHASIS ),
.LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ( LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ),
.LINK_CTRL2_TARGET_LINK_SPEED ( LINK_CTRL2_TARGET_LINK_SPEED ),
.LINK_STATUS_SLOT_CLOCK_CONFIG ( LINK_STATUS_SLOT_CLOCK_CONFIG ),
.LL_ACK_TIMEOUT ( LL_ACK_TIMEOUT ),
.LL_ACK_TIMEOUT_EN ( LL_ACK_TIMEOUT_EN ),
.LL_ACK_TIMEOUT_FUNC ( LL_ACK_TIMEOUT_FUNC ),
.LL_REPLAY_TIMEOUT ( LL_REPLAY_TIMEOUT ),
.LL_REPLAY_TIMEOUT_EN ( LL_REPLAY_TIMEOUT_EN ),
.LL_REPLAY_TIMEOUT_FUNC ( LL_REPLAY_TIMEOUT_FUNC ),
.LTSSM_MAX_LINK_WIDTH ( LTSSM_MAX_LINK_WIDTH ),
.MPS_FORCE (MPS_FORCE),
.MSI_BASE_PTR ( MSI_BASE_PTR ),
.MSI_CAP_ID ( MSI_CAP_ID ),
.MSI_CAP_MULTIMSGCAP ( MSI_CAP_MULTIMSGCAP ),
.MSI_CAP_MULTIMSG_EXTENSION ( MSI_CAP_MULTIMSG_EXTENSION ),
.MSI_CAP_NEXTPTR ( MSI_CAP_NEXTPTR ),
.MSI_CAP_ON ( MSI_CAP_ON ),
.MSI_CAP_PER_VECTOR_MASKING_CAPABLE ( MSI_CAP_PER_VECTOR_MASKING_CAPABLE ),
.MSI_CAP_64_BIT_ADDR_CAPABLE ( MSI_CAP_64_BIT_ADDR_CAPABLE ),
.MSIX_BASE_PTR ( MSIX_BASE_PTR ),
.MSIX_CAP_ID ( MSIX_CAP_ID ),
.MSIX_CAP_NEXTPTR( MSIX_CAP_NEXTPTR ),
.MSIX_CAP_ON ( MSIX_CAP_ON ),
.MSIX_CAP_PBA_BIR( MSIX_CAP_PBA_BIR ),
.MSIX_CAP_PBA_OFFSET ( MSIX_CAP_PBA_OFFSET ),
.MSIX_CAP_TABLE_BIR ( MSIX_CAP_TABLE_BIR ),
.MSIX_CAP_TABLE_OFFSET ( MSIX_CAP_TABLE_OFFSET ),
.MSIX_CAP_TABLE_SIZE ( MSIX_CAP_TABLE_SIZE ),
.N_FTS_COMCLK_GEN1 ( N_FTS_COMCLK_GEN1 ),
.N_FTS_COMCLK_GEN2 ( N_FTS_COMCLK_GEN2 ),
.N_FTS_GEN1 ( N_FTS_GEN1 ),
.N_FTS_GEN2 ( N_FTS_GEN2 ),
.PCIE_BASE_PTR ( PCIE_BASE_PTR ),
.PCIE_CAP_CAPABILITY_ID ( PCIE_CAP_CAPABILITY_ID ),
.PCIE_CAP_CAPABILITY_VERSION ( PCIE_CAP_CAPABILITY_VERSION ),
.PCIE_CAP_DEVICE_PORT_TYPE ( PCIE_CAP_DEVICE_PORT_TYPE ),
.PCIE_CAP_NEXTPTR( PCIE_CAP_NEXTPTR ),
.PCIE_CAP_ON ( PCIE_CAP_ON ),
.PCIE_CAP_RSVD_15_14 ( PCIE_CAP_RSVD_15_14 ),
.PCIE_CAP_SLOT_IMPLEMENTED ( PCIE_CAP_SLOT_IMPLEMENTED ),
.PCIE_REVISION ( PCIE_REVISION ),
.PL_AUTO_CONFIG ( PL_AUTO_CONFIG ),
.PL_FAST_TRAIN ( PL_FAST_TRAIN ),
.PM_ASPML0S_TIMEOUT ( PM_ASPML0S_TIMEOUT ),
.PM_ASPML0S_TIMEOUT_EN ( PM_ASPML0S_TIMEOUT_EN ),
.PM_ASPML0S_TIMEOUT_FUNC ( PM_ASPML0S_TIMEOUT_FUNC ),
.PM_ASPM_FASTEXIT ( PM_ASPM_FASTEXIT ),
.PM_BASE_PTR ( PM_BASE_PTR ),
.PM_CAP_AUXCURRENT ( PM_CAP_AUXCURRENT ),
.PM_CAP_D1SUPPORT( PM_CAP_D1SUPPORT ),
.PM_CAP_D2SUPPORT( PM_CAP_D2SUPPORT ),
.PM_CAP_DSI ( PM_CAP_DSI ),
.PM_CAP_ID ( PM_CAP_ID ),
.PM_CAP_NEXTPTR ( PM_CAP_NEXTPTR ),
.PM_CAP_ON ( PM_CAP_ON ),
.PM_CAP_PME_CLOCK( PM_CAP_PME_CLOCK ),
.PM_CAP_PMESUPPORT ( PM_CAP_PMESUPPORT ),
.PM_CAP_RSVD_04 ( PM_CAP_RSVD_04 ),
.PM_CAP_VERSION ( PM_CAP_VERSION ),
.PM_CSR_B2B3 ( PM_CSR_B2B3 ),
.PM_CSR_BPCCEN ( PM_CSR_BPCCEN ),
.PM_CSR_NOSOFTRST( PM_CSR_NOSOFTRST ),
.PM_DATA0( PM_DATA0 ),
.PM_DATA1( PM_DATA1 ),
.PM_DATA2( PM_DATA2 ),
.PM_DATA3( PM_DATA3 ),
.PM_DATA4( PM_DATA4 ),
.PM_DATA5( PM_DATA5 ),
.PM_DATA6( PM_DATA6 ),
.PM_DATA7( PM_DATA7 ),
.PM_DATA_SCALE0 ( PM_DATA_SCALE0 ),
.PM_DATA_SCALE1 ( PM_DATA_SCALE1 ),
.PM_DATA_SCALE2 ( PM_DATA_SCALE2 ),
.PM_DATA_SCALE3 ( PM_DATA_SCALE3 ),
.PM_DATA_SCALE4 ( PM_DATA_SCALE4 ),
.PM_DATA_SCALE5 ( PM_DATA_SCALE5 ),
.PM_DATA_SCALE6 ( PM_DATA_SCALE6 ),
.PM_DATA_SCALE7 ( PM_DATA_SCALE7 ),
.PM_MF (PM_MF),
.RBAR_BASE_PTR (RBAR_BASE_PTR),
.RBAR_CAP_CONTROL_ENCODEDBAR0 (RBAR_CAP_CONTROL_ENCODEDBAR0),
.RBAR_CAP_CONTROL_ENCODEDBAR1 (RBAR_CAP_CONTROL_ENCODEDBAR1),
.RBAR_CAP_CONTROL_ENCODEDBAR2 (RBAR_CAP_CONTROL_ENCODEDBAR2),
.RBAR_CAP_CONTROL_ENCODEDBAR3 (RBAR_CAP_CONTROL_ENCODEDBAR3),
.RBAR_CAP_CONTROL_ENCODEDBAR4 (RBAR_CAP_CONTROL_ENCODEDBAR4),
.RBAR_CAP_CONTROL_ENCODEDBAR5 (RBAR_CAP_CONTROL_ENCODEDBAR5),
.RBAR_CAP_ID (RBAR_CAP_ID),
.RBAR_CAP_INDEX0 (RBAR_CAP_INDEX0),
.RBAR_CAP_INDEX1 (RBAR_CAP_INDEX1),
.RBAR_CAP_INDEX2 (RBAR_CAP_INDEX2),
.RBAR_CAP_INDEX3 (RBAR_CAP_INDEX3),
.RBAR_CAP_INDEX4 (RBAR_CAP_INDEX4),
.RBAR_CAP_INDEX5 (RBAR_CAP_INDEX5),
.RBAR_CAP_NEXTPTR (RBAR_CAP_NEXTPTR),
.RBAR_CAP_ON (RBAR_CAP_ON),
.RBAR_CAP_SUP0 (RBAR_CAP_SUP0),
.RBAR_CAP_SUP1 (RBAR_CAP_SUP1),
.RBAR_CAP_SUP2 (RBAR_CAP_SUP2),
.RBAR_CAP_SUP3 (RBAR_CAP_SUP3),
.RBAR_CAP_SUP4 (RBAR_CAP_SUP4),
.RBAR_CAP_SUP5 (RBAR_CAP_SUP5),
.RBAR_CAP_VERSION (RBAR_CAP_VERSION),
.RBAR_NUM (RBAR_NUM),
.RECRC_CHK (RECRC_CHK),
.RECRC_CHK_TRIM (RECRC_CHK_TRIM),
.ROOT_CAP_CRS_SW_VISIBILITY ( ROOT_CAP_CRS_SW_VISIBILITY ),
.RP_AUTO_SPD ( RP_AUTO_SPD ),
.RP_AUTO_SPD_LOOPCNT ( RP_AUTO_SPD_LOOPCNT ),
.SELECT_DLL_IF ( SELECT_DLL_IF ),
.SLOT_CAP_ATT_BUTTON_PRESENT ( SLOT_CAP_ATT_BUTTON_PRESENT ),
.SLOT_CAP_ATT_INDICATOR_PRESENT ( SLOT_CAP_ATT_INDICATOR_PRESENT ),
.SLOT_CAP_ELEC_INTERLOCK_PRESENT ( SLOT_CAP_ELEC_INTERLOCK_PRESENT ),
.SLOT_CAP_HOTPLUG_CAPABLE( SLOT_CAP_HOTPLUG_CAPABLE ),
.SLOT_CAP_HOTPLUG_SURPRISE ( SLOT_CAP_HOTPLUG_SURPRISE ),
.SLOT_CAP_MRL_SENSOR_PRESENT ( SLOT_CAP_MRL_SENSOR_PRESENT ),
.SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ( SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ),
.SLOT_CAP_PHYSICAL_SLOT_NUM ( SLOT_CAP_PHYSICAL_SLOT_NUM ),
.SLOT_CAP_POWER_CONTROLLER_PRESENT ( SLOT_CAP_POWER_CONTROLLER_PRESENT ),
.SLOT_CAP_POWER_INDICATOR_PRESENT( SLOT_CAP_POWER_INDICATOR_PRESENT ),
.SLOT_CAP_SLOT_POWER_LIMIT_SCALE ( SLOT_CAP_SLOT_POWER_LIMIT_SCALE ),
.SLOT_CAP_SLOT_POWER_LIMIT_VALUE ( SLOT_CAP_SLOT_POWER_LIMIT_VALUE ),
.SPARE_BIT0 ( SPARE_BIT0 ),
.SPARE_BIT1 ( SPARE_BIT1 ),
.SPARE_BIT2 ( SPARE_BIT2 ),
.SPARE_BIT3 ( SPARE_BIT3 ),
.SPARE_BIT4 ( SPARE_BIT4 ),
.SPARE_BIT5 ( SPARE_BIT5 ),
.SPARE_BIT6 ( SPARE_BIT6 ),
.SPARE_BIT7 ( SPARE_BIT7 ),
.SPARE_BIT8 ( SPARE_BIT8 ),
.SPARE_BYTE0 ( SPARE_BYTE0 ),
.SPARE_BYTE1 ( SPARE_BYTE1 ),
.SPARE_BYTE2 ( SPARE_BYTE2 ),
.SPARE_BYTE3 ( SPARE_BYTE3 ),
.SPARE_WORD0 ( SPARE_WORD0 ),
.SPARE_WORD1 ( SPARE_WORD1 ),
.SPARE_WORD2 ( SPARE_WORD2 ),
.SPARE_WORD3 ( SPARE_WORD3 ),
.SSL_MESSAGE_AUTO (SSL_MESSAGE_AUTO),
.TECRC_EP_INV ( TECRC_EP_INV ),
.TL_RBYPASS(TL_RBYPASS),
.TL_RX_RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ),
.TL_RX_RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ),
.TL_RX_RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY ),
.TL_TFC_DISABLE ( TL_TFC_DISABLE ),
.TL_TX_CHECKS_DISABLE ( TL_TX_CHECKS_DISABLE ),
.TL_TX_RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ),
.TL_TX_RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ),
.TL_TX_RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY ),
.TRN_DW (TRN_DW),
.TRN_NP_FC (TRN_NP_FC),
.UPCONFIG_CAPABLE( UPCONFIG_CAPABLE ),
.UPSTREAM_FACING ( UPSTREAM_FACING ),
.UR_ATOMIC (UR_ATOMIC),
.UR_CFG1 (UR_CFG1),
.UR_INV_REQ(UR_INV_REQ),
.UR_PRS_RESPONSE (UR_PRS_RESPONSE),
.USER_CLK2_DIV2 (USER_CLK2_DIV2),
.USER_CLK_FREQ ( USER_CLK_FREQ ),
.USE_RID_PINS (USE_RID_PINS),
.VC0_CPL_INFINITE( VC0_CPL_INFINITE ),
.VC0_RX_RAM_LIMIT( VC0_RX_RAM_LIMIT ),
.VC0_TOTAL_CREDITS_CD ( VC0_TOTAL_CREDITS_CD ),
.VC0_TOTAL_CREDITS_CH ( VC0_TOTAL_CREDITS_CH ),
.VC0_TOTAL_CREDITS_NPD (VC0_TOTAL_CREDITS_NPD),
.VC0_TOTAL_CREDITS_NPH ( VC0_TOTAL_CREDITS_NPH ),
.VC0_TOTAL_CREDITS_PD ( VC0_TOTAL_CREDITS_PD ),
.VC0_TOTAL_CREDITS_PH ( VC0_TOTAL_CREDITS_PH ),
.VC0_TX_LASTPACKET ( VC0_TX_LASTPACKET ),
.VC_BASE_PTR ( VC_BASE_PTR ),
.VC_CAP_ID ( VC_CAP_ID ),
.VC_CAP_NEXTPTR ( VC_CAP_NEXTPTR ),
.VC_CAP_ON ( VC_CAP_ON ),
.VC_CAP_REJECT_SNOOP_TRANSACTIONS( VC_CAP_REJECT_SNOOP_TRANSACTIONS ),
.VC_CAP_VERSION ( VC_CAP_VERSION ),
.VSEC_BASE_PTR ( VSEC_BASE_PTR ),
.VSEC_CAP_HDR_ID ( VSEC_CAP_HDR_ID ),
.VSEC_CAP_HDR_LENGTH ( VSEC_CAP_HDR_LENGTH ),
.VSEC_CAP_HDR_REVISION ( VSEC_CAP_HDR_REVISION ),
.VSEC_CAP_ID ( VSEC_CAP_ID ),
.VSEC_CAP_IS_LINK_VISIBLE( VSEC_CAP_IS_LINK_VISIBLE ),
.VSEC_CAP_NEXTPTR( VSEC_CAP_NEXTPTR ),
.VSEC_CAP_ON ( VSEC_CAP_ON ),
.VSEC_CAP_VERSION( VSEC_CAP_VERSION )
) pcie_7x_i (
.trn_lnk_up ( trn_lnk_up ),
.trn_clk ( user_clk_out ),
.lnk_clk_en ( lnk_clk_en),
.user_rst_n ( user_rst_n ),
.received_func_lvl_rst_n ( cfg_received_func_lvl_rst_n ),
.sys_rst_n (~phy_rdy_n),
.pl_rst_n ( 1'b1 ),
.dl_rst_n ( 1'b1 ),
.tl_rst_n ( 1'b1 ),
.cm_sticky_rst_n ( 1'b1 ),
.func_lvl_rst_n ( func_lvl_rst_n ),
.cm_rst_n ( cm_rst_n ),
.trn_rbar_hit ( trn_rbar_hit ),
.trn_rd ( trn_rd ),
.trn_recrc_err ( trn_recrc_err ),
.trn_reof ( trn_reof ),
.trn_rerrfwd ( trn_rerrfwd ),
.trn_rrem ( trn_rrem ),
.trn_rsof ( trn_rsof ),
.trn_rsrc_dsc ( trn_rsrc_dsc ),
.trn_rsrc_rdy ( trn_rsrc_rdy ),
.trn_rdst_rdy ( trn_rdst_rdy ),
.trn_rnp_ok ( rx_np_ok ),
.trn_rnp_req ( rx_np_req ),
.trn_rfcp_ret ( 1'b1 ),
.trn_tbuf_av ( tx_buf_av ),
.trn_tcfg_req ( tx_cfg_req ),
.trn_tdllp_dst_rdy ( ),
.trn_tdst_rdy ( trn_tdst_rdy ),
.trn_terr_drop ( tx_err_drop ),
.trn_tcfg_gnt ( trn_tcfg_gnt ),
.trn_td ( trn_td ),
.trn_tdllp_data ( 32'b0 ),
.trn_tdllp_src_rdy ( 1'b0 ),
.trn_tecrc_gen ( trn_tecrc_gen ),
.trn_teof ( trn_teof ),
.trn_terrfwd ( trn_terrfwd ),
.trn_trem ( trn_trem),
.trn_tsof ( trn_tsof ),
.trn_tsrc_dsc ( trn_tsrc_dsc ),
.trn_tsrc_rdy ( trn_tsrc_rdy ),
.trn_tstr ( trn_tstr ),
.trn_fc_cpld ( fc_cpld ),
.trn_fc_cplh ( fc_cplh ),
.trn_fc_npd ( fc_npd ),
.trn_fc_nph ( fc_nph ),
.trn_fc_pd ( fc_pd ),
.trn_fc_ph ( fc_ph ),
.trn_fc_sel ( fc_sel ),
.cfg_dev_id (cfg_dev_id),
.cfg_vend_id (cfg_vend_id),
.cfg_rev_id (cfg_rev_id),
.cfg_subsys_id (cfg_subsys_id),
.cfg_subsys_vend_id (cfg_subsys_vend_id),
.cfg_pciecap_interrupt_msgnum (cfg_pciecap_interrupt_msgnum),
.cfg_bridge_serr_en (cfg_bridge_serr_en),
.cfg_command_bus_master_enable ( cfg_command_bus_master_enable ),
.cfg_command_interrupt_disable ( cfg_command_interrupt_disable ),
.cfg_command_io_enable ( cfg_command_io_enable ),
.cfg_command_mem_enable ( cfg_command_mem_enable ),
.cfg_command_serr_en ( cfg_command_serr_en ),
.cfg_dev_control_aux_power_en ( cfg_dev_control_aux_power_en ),
.cfg_dev_control_corr_err_reporting_en ( cfg_dev_control_corr_err_reporting_en ),
.cfg_dev_control_enable_ro ( cfg_dev_control_enable_ro ),
.cfg_dev_control_ext_tag_en ( cfg_dev_control_ext_tag_en ),
.cfg_dev_control_fatal_err_reporting_en ( cfg_dev_control_fatal_err_reporting_en ),
.cfg_dev_control_max_payload ( cfg_dev_control_max_payload ),
.cfg_dev_control_max_read_req ( cfg_dev_control_max_read_req ),
.cfg_dev_control_non_fatal_reporting_en ( cfg_dev_control_non_fatal_reporting_en ),
.cfg_dev_control_no_snoop_en ( cfg_dev_control_no_snoop_en ),
.cfg_dev_control_phantom_en ( cfg_dev_control_phantom_en ),
.cfg_dev_control_ur_err_reporting_en ( cfg_dev_control_ur_err_reporting_en ),
.cfg_dev_control2_cpl_timeout_dis ( cfg_dev_control2_cpl_timeout_dis ),
.cfg_dev_control2_cpl_timeout_val ( cfg_dev_control2_cpl_timeout_val ),
.cfg_dev_control2_ari_forward_en ( cfg_dev_control2_ari_forward_en),
.cfg_dev_control2_atomic_requester_en ( cfg_dev_control2_atomic_requester_en),
.cfg_dev_control2_atomic_egress_block ( cfg_dev_control2_atomic_egress_block),
.cfg_dev_control2_ido_req_en ( cfg_dev_control2_ido_req_en),
.cfg_dev_control2_ido_cpl_en ( cfg_dev_control2_ido_cpl_en),
.cfg_dev_control2_ltr_en ( cfg_dev_control2_ltr_en),
.cfg_dev_control2_tlp_prefix_block ( cfg_dev_control2_tlp_prefix_block),
.cfg_dev_status_corr_err_detected ( cfg_dev_status_corr_err_detected ),
.cfg_dev_status_fatal_err_detected ( cfg_dev_status_fatal_err_detected ),
.cfg_dev_status_non_fatal_err_detected ( cfg_dev_status_non_fatal_err_detected ),
.cfg_dev_status_ur_detected ( cfg_dev_status_ur_detected ),
.cfg_mgmt_do ( cfg_mgmt_do ),
.cfg_err_aer_headerlog_set_n ( cfg_err_aer_headerlog_set_n),
.cfg_err_aer_headerlog ( cfg_err_aer_headerlog),
.cfg_err_cpl_rdy_n ( cfg_err_cpl_rdy_n ),
.cfg_interrupt_do ( cfg_interrupt_do ),
.cfg_interrupt_mmenable ( cfg_interrupt_mmenable ),
.cfg_interrupt_msienable ( cfg_interrupt_msienable ),
.cfg_interrupt_msixenable ( cfg_interrupt_msixenable ),
.cfg_interrupt_msixfm ( cfg_interrupt_msixfm ),
.cfg_interrupt_rdy_n ( cfg_interrupt_rdy_n ),
.cfg_link_control_rcb ( cfg_link_control_rcb ),
.cfg_link_control_aspm_control ( cfg_link_control_aspm_control ),
.cfg_link_control_auto_bandwidth_int_en ( cfg_link_control_auto_bandwidth_int_en ),
.cfg_link_control_bandwidth_int_en ( cfg_link_control_bandwidth_int_en ),
.cfg_link_control_clock_pm_en ( cfg_link_control_clock_pm_en ),
.cfg_link_control_common_clock ( cfg_link_control_common_clock ),
.cfg_link_control_extended_sync ( cfg_link_control_extended_sync ),
.cfg_link_control_hw_auto_width_dis ( cfg_link_control_hw_auto_width_dis ),
.cfg_link_control_link_disable ( cfg_link_control_link_disable ),
.cfg_link_control_retrain_link ( cfg_link_control_retrain_link ),
.cfg_link_status_auto_bandwidth_status ( cfg_link_status_auto_bandwidth_status ),
.cfg_link_status_bandwidth_status ( cfg_link_status_bandwidth_status ),
.cfg_link_status_current_speed ( cfg_link_status_current_speed ),
.cfg_link_status_dll_active ( cfg_link_status_dll_active ),
.cfg_link_status_link_training ( cfg_link_status_link_training ),
.cfg_link_status_negotiated_width ( cfg_link_status_negotiated_width),
.cfg_msg_data ( cfg_msg_data ),
.cfg_msg_received ( cfg_msg_received ),
.cfg_msg_received_assert_int_a ( cfg_msg_received_assert_int_a),
.cfg_msg_received_assert_int_b ( cfg_msg_received_assert_int_b),
.cfg_msg_received_assert_int_c ( cfg_msg_received_assert_int_c),
.cfg_msg_received_assert_int_d ( cfg_msg_received_assert_int_d),
.cfg_msg_received_deassert_int_a ( cfg_msg_received_deassert_int_a),
.cfg_msg_received_deassert_int_b ( cfg_msg_received_deassert_int_b),
.cfg_msg_received_deassert_int_c ( cfg_msg_received_deassert_int_c),
.cfg_msg_received_deassert_int_d ( cfg_msg_received_deassert_int_d),
.cfg_msg_received_err_cor ( cfg_msg_received_err_cor),
.cfg_msg_received_err_fatal ( cfg_msg_received_err_fatal),
.cfg_msg_received_err_non_fatal ( cfg_msg_received_err_non_fatal),
.cfg_msg_received_pm_as_nak ( cfg_msg_received_pm_as_nak),
.cfg_msg_received_pme_to ( cfg_msg_received_pme_to ),
.cfg_msg_received_pme_to_ack ( cfg_msg_received_pme_to_ack),
.cfg_msg_received_pm_pme ( cfg_msg_received_pm_pme),
.cfg_msg_received_setslotpowerlimit ( cfg_msg_received_setslotpowerlimit),
.cfg_msg_received_unlock ( cfg_msg_received_unlock),
.cfg_pcie_link_state ( cfg_pcie_link_state ),
.cfg_pmcsr_pme_en ( cfg_pmcsr_pme_en),
.cfg_pmcsr_powerstate ( cfg_pmcsr_powerstate),
.cfg_pmcsr_pme_status ( cfg_pmcsr_pme_status),
.cfg_pm_rcv_as_req_l1_n ( cfg_pm_rcv_as_req_l1_n),
.cfg_pm_rcv_enter_l1_n ( cfg_pm_rcv_enter_l1_n),
.cfg_pm_rcv_enter_l23_n ( cfg_pm_rcv_enter_l23_n),
.cfg_pm_rcv_req_ack_n ( cfg_pm_rcv_req_ack_n),
.cfg_mgmt_rd_wr_done_n ( cfg_mgmt_rd_wr_done_n ),
.cfg_slot_control_electromech_il_ctl_pulse (cfg_slot_control_electromech_il_ctl_pulse),
.cfg_root_control_syserr_corr_err_en ( cfg_root_control_syserr_corr_err_en),
.cfg_root_control_syserr_non_fatal_err_en ( cfg_root_control_syserr_non_fatal_err_en),
.cfg_root_control_syserr_fatal_err_en ( cfg_root_control_syserr_fatal_err_en),
.cfg_root_control_pme_int_en ( cfg_root_control_pme_int_en ),
.cfg_aer_ecrc_check_en ( cfg_aer_ecrc_check_en ),
.cfg_aer_ecrc_gen_en ( cfg_aer_ecrc_gen_en ),
.cfg_aer_rooterr_corr_err_reporting_en ( cfg_aer_rooterr_corr_err_reporting_en),
.cfg_aer_rooterr_non_fatal_err_reporting_en( cfg_aer_rooterr_non_fatal_err_reporting_en),
.cfg_aer_rooterr_fatal_err_reporting_en ( cfg_aer_rooterr_fatal_err_reporting_en),
.cfg_aer_rooterr_corr_err_received ( cfg_aer_rooterr_corr_err_received),
.cfg_aer_rooterr_non_fatal_err_received ( cfg_aer_rooterr_non_fatal_err_received),
.cfg_aer_rooterr_fatal_err_received ( cfg_aer_rooterr_fatal_err_received),
.cfg_aer_interrupt_msgnum ( cfg_aer_interrupt_msgnum ),
.cfg_transaction ( cfg_transaction),
.cfg_transaction_addr ( cfg_transaction_addr),
.cfg_transaction_type ( cfg_transaction_type),
.cfg_vc_tcvc_map ( cfg_vc_tcvc_map),
.cfg_mgmt_byte_en_n ( cfg_mgmt_byte_en_n ),
.cfg_mgmt_di ( cfg_mgmt_di ),
.cfg_ds_bus_number ( cfg_ds_bus_number ),
.cfg_ds_device_number ( cfg_ds_device_number ),
.cfg_ds_function_number ( cfg_ds_function_number ),
.cfg_dsn ( cfg_dsn ),
.cfg_mgmt_dwaddr ( cfg_mgmt_dwaddr ),
.cfg_err_acs_n ( 1'b1 ),
.cfg_err_cor_n ( cfg_err_cor_n ),
.cfg_err_cpl_abort_n ( cfg_err_cpl_abort_n ),
.cfg_err_cpl_timeout_n ( cfg_err_cpl_timeout_n ),
.cfg_err_cpl_unexpect_n ( cfg_err_cpl_unexpect_n ),
.cfg_err_ecrc_n ( cfg_err_ecrc_n ),
.cfg_err_locked_n ( cfg_err_locked_n ),
.cfg_err_posted_n ( cfg_err_posted_n ),
.cfg_err_tlp_cpl_header ( cfg_err_tlp_cpl_header ),
.cfg_err_ur_n ( cfg_err_ur_n ),
.cfg_err_malformed_n ( cfg_err_malformed_n ),
.cfg_err_poisoned_n ( cfg_err_poisoned_n),
.cfg_err_atomic_egress_blocked_n ( cfg_err_atomic_egress_blocked_n ),
.cfg_err_mc_blocked_n ( cfg_err_mc_blocked_n ),
.cfg_err_internal_uncor_n ( cfg_err_internal_uncor_n ),
.cfg_err_internal_cor_n ( cfg_err_internal_cor_n ),
.cfg_err_norecovery_n ( cfg_err_norecovery_n ),
.cfg_interrupt_assert_n ( cfg_interrupt_assert_n ),
.cfg_interrupt_di ( cfg_interrupt_di ),
.cfg_interrupt_n ( cfg_interrupt_n ),
.cfg_interrupt_stat_n ( cfg_interrupt_stat_n),
.cfg_pm_send_pme_to_n ( cfg_pm_send_pme_to_n ),
.cfg_pm_turnoff_ok_n ( cfg_turnoff_ok_w ),
.cfg_pm_wake_n ( cfg_pm_wake_n ),
.cfg_pm_halt_aspm_l0s_n ( cfg_pm_halt_aspm_l0s_n ),
.cfg_pm_halt_aspm_l1_n ( cfg_pm_halt_aspm_l1_n ),
.cfg_pm_force_state_en_n ( cfg_pm_force_state_en_n ),
.cfg_pm_force_state ( cfg_pm_force_state ),
.cfg_force_mps ( cfg_force_mps ),
.cfg_force_common_clock_off ( cfg_force_common_clock_off ),
.cfg_force_extended_sync_on ( cfg_force_extended_sync_on ),
.cfg_port_number ( cfg_port_number ),
.cfg_mgmt_rd_en_n ( cfg_mgmt_rd_en_n ),
.cfg_trn_pending_n ( ~cfg_trn_pending ),
.cfg_mgmt_wr_en_n ( cfg_mgmt_wr_en_n ),
.cfg_mgmt_wr_readonly_n ( cfg_mgmt_wr_readonly_n ),
.cfg_mgmt_wr_rw1c_as_rw_n ( cfg_mgmt_wr_rw1c_as_rw_n ),
.pl_initial_link_width ( pl_initial_link_width ),
.pl_lane_reversal_mode ( pl_lane_reversal_mode ),
.pl_link_gen2_cap ( pl_link_gen2_cap ),
.pl_link_partner_gen2_supported ( pl_link_partner_gen2_supported ),
.pl_link_upcfg_cap ( pl_link_upcfg_cap ),
.pl_ltssm_state ( pl_ltssm_state ),
.pl_phy_lnk_up_n ( pl_phy_lnk_up_n ),
.pl_received_hot_rst ( pl_received_hot_rst ),
.pl_rx_pm_state ( pl_rx_pm_state ),
.pl_sel_lnk_rate ( pl_sel_lnk_rate),
.pl_sel_lnk_width ( pl_sel_lnk_width ),
.pl_tx_pm_state ( pl_tx_pm_state ),
.pl_directed_link_auton ( pl_directed_link_auton ),
.pl_directed_link_change ( pl_directed_link_change ),
.pl_directed_link_speed ( pl_directed_link_speed ),
.pl_directed_link_width ( pl_directed_link_width ),
.pl_downstream_deemph_source ( pl_downstream_deemph_source ),
.pl_upstream_prefer_deemph ( pl_upstream_prefer_deemph ),
.pl_transmit_hot_rst ( pl_transmit_hot_rst ),
.pl_directed_ltssm_new_vld ( pl_directed_ltssm_new_vld ),
.pl_directed_ltssm_new ( pl_directed_ltssm_new ),
.pl_directed_ltssm_stall ( pl_directed_ltssm_stall ),
.pl_directed_change_done ( pl_directed_change_done ),
.dbg_sclr_a ( dbg_sclr_a ),
.dbg_sclr_b ( dbg_sclr_b ),
.dbg_sclr_c ( dbg_sclr_c ),
.dbg_sclr_d ( dbg_sclr_d ),
.dbg_sclr_e ( dbg_sclr_e ),
.dbg_sclr_f ( dbg_sclr_f ),
.dbg_sclr_g ( dbg_sclr_g ),
.dbg_sclr_h ( dbg_sclr_h ),
.dbg_sclr_i ( dbg_sclr_i ),
.dbg_sclr_j ( dbg_sclr_j ),
.dbg_sclr_k ( dbg_sclr_k ),
.dbg_vec_a ( dbg_vec_a ),
.dbg_vec_b ( dbg_vec_b ),
.dbg_vec_c ( dbg_vec_c ),
.pl_dbg_vec ( pl_dbg_vec ),
.dbg_mode ( dbg_mode ),
.dbg_sub_mode ( dbg_sub_mode ),
.pl_dbg_mode ( pl_dbg_mode ),
.drp_do ( drp_do ),
.drp_rdy ( drp_rdy ),
.drp_clk ( drp_clk ),
.drp_addr ( drp_addr ),
.drp_en ( drp_en ),
.drp_di ( drp_di ),
.drp_we ( drp_we ),
.ll2_tlp_rcv ( 1'b0 ),
.ll2_send_enter_l1 ( 1'b0 ),
.ll2_send_enter_l23 ( 1'b0 ),
.ll2_send_as_req_l1 ( 1'b0 ),
.ll2_send_pm_ack ( 1'b0 ),
.ll2_suspend_now ( 1'b0 ),
.ll2_tfc_init1_seq ( ),
.ll2_tfc_init2_seq ( ),
.ll2_suspend_ok ( ),
.ll2_tx_idle ( ),
.ll2_link_status ( ),
.ll2_receiver_err ( ),
.ll2_protocol_err ( ),
.ll2_bad_tlp_err ( ),
.ll2_bad_dllp_err ( ),
.ll2_replay_ro_err ( ),
.ll2_replay_to_err ( ),
.tl2_ppm_suspend_req ( 1'b0 ),
.tl2_aspm_suspend_credit_check ( 1'b0 ),
.tl2_ppm_suspend_ok ( ),
.tl2_aspm_suspend_req ( ),
.tl2_aspm_suspend_credit_check_ok ( ),
.tl2_err_hdr ( ),
.tl2_err_malformed ( ),
.tl2_err_rxoverflow ( ),
.tl2_err_fcpe ( ),
.pl2_directed_lstate ( 5'b0 ),
.pl2_suspend_ok ( ),
.pl2_recovery ( ),
.pl2_rx_elec_idle ( ),
.pl2_rx_pm_state ( ),
.pl2_l0_req ( ),
.pl2_link_up ( ),
.pl2_receiver_err ( ),
.trn_rdllp_data (trn_rdllp_data ),
.trn_rdllp_src_rdy (trn_rdllp_src_rdy ),
.pipe_clk ( pipe_clk ),
.user_clk2 ( user_clk2 ),
.user_clk ( user_clk ),
.user_clk_prebuf ( 1'b0 ),
.user_clk_prebuf_en ( 1'b0 ),
.pipe_rx0_polarity ( pipe_rx0_polarity ),
.pipe_rx1_polarity ( pipe_rx1_polarity ),
.pipe_rx2_polarity ( pipe_rx2_polarity ),
.pipe_rx3_polarity ( pipe_rx3_polarity ),
.pipe_rx4_polarity ( pipe_rx4_polarity ),
.pipe_rx5_polarity ( pipe_rx5_polarity ),
.pipe_rx6_polarity ( pipe_rx6_polarity ),
.pipe_rx7_polarity ( pipe_rx7_polarity ),
.pipe_tx0_compliance ( pipe_tx0_compliance ),
.pipe_tx1_compliance ( pipe_tx1_compliance ),
.pipe_tx2_compliance ( pipe_tx2_compliance ),
.pipe_tx3_compliance ( pipe_tx3_compliance ),
.pipe_tx4_compliance ( pipe_tx4_compliance ),
.pipe_tx5_compliance ( pipe_tx5_compliance ),
.pipe_tx6_compliance ( pipe_tx6_compliance ),
.pipe_tx7_compliance ( pipe_tx7_compliance ),
.pipe_tx0_char_is_k ( pipe_tx0_char_is_k ),
.pipe_tx1_char_is_k ( pipe_tx1_char_is_k ),
.pipe_tx2_char_is_k ( pipe_tx2_char_is_k ),
.pipe_tx3_char_is_k ( pipe_tx3_char_is_k ),
.pipe_tx4_char_is_k ( pipe_tx4_char_is_k ),
.pipe_tx5_char_is_k ( pipe_tx5_char_is_k ),
.pipe_tx6_char_is_k ( pipe_tx6_char_is_k ),
.pipe_tx7_char_is_k ( pipe_tx7_char_is_k ),
.pipe_tx0_data ( pipe_tx0_data ),
.pipe_tx1_data ( pipe_tx1_data ),
.pipe_tx2_data ( pipe_tx2_data ),
.pipe_tx3_data ( pipe_tx3_data ),
.pipe_tx4_data ( pipe_tx4_data ),
.pipe_tx5_data ( pipe_tx5_data ),
.pipe_tx6_data ( pipe_tx6_data ),
.pipe_tx7_data ( pipe_tx7_data ),
.pipe_tx0_elec_idle ( pipe_tx0_elec_idle ),
.pipe_tx1_elec_idle ( pipe_tx1_elec_idle ),
.pipe_tx2_elec_idle ( pipe_tx2_elec_idle ),
.pipe_tx3_elec_idle ( pipe_tx3_elec_idle ),
.pipe_tx4_elec_idle ( pipe_tx4_elec_idle ),
.pipe_tx5_elec_idle ( pipe_tx5_elec_idle ),
.pipe_tx6_elec_idle ( pipe_tx6_elec_idle ),
.pipe_tx7_elec_idle ( pipe_tx7_elec_idle ),
.pipe_tx0_powerdown ( pipe_tx0_powerdown ),
.pipe_tx1_powerdown ( pipe_tx1_powerdown ),
.pipe_tx2_powerdown ( pipe_tx2_powerdown ),
.pipe_tx3_powerdown ( pipe_tx3_powerdown ),
.pipe_tx4_powerdown ( pipe_tx4_powerdown ),
.pipe_tx5_powerdown ( pipe_tx5_powerdown ),
.pipe_tx6_powerdown ( pipe_tx6_powerdown ),
.pipe_tx7_powerdown ( pipe_tx7_powerdown ),
.pipe_rx0_char_is_k ( pipe_rx0_char_is_k ),
.pipe_rx1_char_is_k ( pipe_rx1_char_is_k ),
.pipe_rx2_char_is_k ( pipe_rx2_char_is_k ),
.pipe_rx3_char_is_k ( pipe_rx3_char_is_k ),
.pipe_rx4_char_is_k ( pipe_rx4_char_is_k ),
.pipe_rx5_char_is_k ( pipe_rx5_char_is_k ),
.pipe_rx6_char_is_k ( pipe_rx6_char_is_k ),
.pipe_rx7_char_is_k ( pipe_rx7_char_is_k ),
.pipe_rx0_valid ( pipe_rx0_valid ),
.pipe_rx1_valid ( pipe_rx1_valid ),
.pipe_rx2_valid ( pipe_rx2_valid ),
.pipe_rx3_valid ( pipe_rx3_valid ),
.pipe_rx4_valid ( pipe_rx4_valid ),
.pipe_rx5_valid ( pipe_rx5_valid ),
.pipe_rx6_valid ( pipe_rx6_valid ),
.pipe_rx7_valid ( pipe_rx7_valid ),
.pipe_rx0_data ( pipe_rx0_data ),
.pipe_rx1_data ( pipe_rx1_data ),
.pipe_rx2_data ( pipe_rx2_data ),
.pipe_rx3_data ( pipe_rx3_data ),
.pipe_rx4_data ( pipe_rx4_data ),
.pipe_rx5_data ( pipe_rx5_data ),
.pipe_rx6_data ( pipe_rx6_data ),
.pipe_rx7_data ( pipe_rx7_data ),
.pipe_rx0_chanisaligned ( pipe_rx0_chanisaligned ),
.pipe_rx1_chanisaligned ( pipe_rx1_chanisaligned ),
.pipe_rx2_chanisaligned ( pipe_rx2_chanisaligned ),
.pipe_rx3_chanisaligned ( pipe_rx3_chanisaligned ),
.pipe_rx4_chanisaligned ( pipe_rx4_chanisaligned ),
.pipe_rx5_chanisaligned ( pipe_rx5_chanisaligned ),
.pipe_rx6_chanisaligned ( pipe_rx6_chanisaligned ),
.pipe_rx7_chanisaligned ( pipe_rx7_chanisaligned ),
.pipe_rx0_status ( pipe_rx0_status ),
.pipe_rx1_status ( pipe_rx1_status ),
.pipe_rx2_status ( pipe_rx2_status ),
.pipe_rx3_status ( pipe_rx3_status ),
.pipe_rx4_status ( pipe_rx4_status ),
.pipe_rx5_status ( pipe_rx5_status ),
.pipe_rx6_status ( pipe_rx6_status ),
.pipe_rx7_status ( pipe_rx7_status ),
.pipe_rx0_phy_status ( pipe_rx0_phy_status ),
.pipe_rx1_phy_status ( pipe_rx1_phy_status ),
.pipe_rx2_phy_status ( pipe_rx2_phy_status ),
.pipe_rx3_phy_status ( pipe_rx3_phy_status ),
.pipe_rx4_phy_status ( pipe_rx4_phy_status ),
.pipe_rx5_phy_status ( pipe_rx5_phy_status ),
.pipe_rx6_phy_status ( pipe_rx6_phy_status ),
.pipe_rx7_phy_status ( pipe_rx7_phy_status ),
.pipe_tx_deemph ( pipe_tx_deemph ),
.pipe_tx_margin ( pipe_tx_margin ),
.pipe_tx_reset ( pipe_tx_reset ),
.pipe_tx_rcvr_det ( pipe_tx_rcvr_det ),
.pipe_tx_rate ( pipe_tx_rate ),
.pipe_rx0_elec_idle ( pipe_rx0_elec_idle ),
.pipe_rx1_elec_idle ( pipe_rx1_elec_idle ),
.pipe_rx2_elec_idle ( pipe_rx2_elec_idle ),
.pipe_rx3_elec_idle ( pipe_rx3_elec_idle ),
.pipe_rx4_elec_idle ( pipe_rx4_elec_idle ),
.pipe_rx5_elec_idle ( pipe_rx5_elec_idle ),
.pipe_rx6_elec_idle ( pipe_rx6_elec_idle ),
.pipe_rx7_elec_idle ( pipe_rx7_elec_idle )
);
//------------------------------------------------------------------------------------------------------------------//
// PIPE Interface PIPELINE Module //
//------------------------------------------------------------------------------------------------------------------//
pcieCore_pcie_pipe_pipeline # (
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.PIPE_PIPELINE_STAGES ( PIPE_PIPELINE_STAGES )
)
pcie_pipe_pipeline_i (
// Pipe Per-Link Signals
.pipe_tx_rcvr_det_i (pipe_tx_rcvr_det),
.pipe_tx_reset_i (1'b0), //MV?
.pipe_tx_rate_i (pipe_tx_rate),
.pipe_tx_deemph_i (pipe_tx_deemph),
.pipe_tx_margin_i (pipe_tx_margin),
.pipe_tx_swing_i (1'b0),
.pipe_tx_rcvr_det_o (pipe_tx_rcvr_det_gt),
.pipe_tx_reset_o ( ),
.pipe_tx_rate_o (pipe_tx_rate_gt),
.pipe_tx_deemph_o (pipe_tx_deemph_gt),
.pipe_tx_margin_o (pipe_tx_margin_gt),
.pipe_tx_swing_o ( ),
// Pipe Per-Lane Signals - Lane 0
.pipe_rx0_char_is_k_o (pipe_rx0_char_is_k ),
.pipe_rx0_data_o (pipe_rx0_data ),
.pipe_rx0_valid_o (pipe_rx0_valid ),
.pipe_rx0_chanisaligned_o (pipe_rx0_chanisaligned ),
.pipe_rx0_status_o (pipe_rx0_status ),
.pipe_rx0_phy_status_o (pipe_rx0_phy_status ),
.pipe_rx0_elec_idle_i (pipe_rx0_elec_idle_gt ),
.pipe_rx0_polarity_i (pipe_rx0_polarity ),
.pipe_tx0_compliance_i (pipe_tx0_compliance ),
.pipe_tx0_char_is_k_i (pipe_tx0_char_is_k ),
.pipe_tx0_data_i (pipe_tx0_data ),
.pipe_tx0_elec_idle_i (pipe_tx0_elec_idle ),
.pipe_tx0_powerdown_i (pipe_tx0_powerdown ),
.pipe_rx0_char_is_k_i (pipe_rx0_char_is_k_gt ),
.pipe_rx0_data_i (pipe_rx0_data_gt ),
.pipe_rx0_valid_i (pipe_rx0_valid_gt ),
.pipe_rx0_chanisaligned_i (pipe_rx0_chanisaligned_gt),
.pipe_rx0_status_i (pipe_rx0_status_gt ),
.pipe_rx0_phy_status_i (pipe_rx0_phy_status_gt ),
.pipe_rx0_elec_idle_o (pipe_rx0_elec_idle ),
.pipe_rx0_polarity_o (pipe_rx0_polarity_gt ),
.pipe_tx0_compliance_o (pipe_tx0_compliance_gt ),
.pipe_tx0_char_is_k_o (pipe_tx0_char_is_k_gt ),
.pipe_tx0_data_o (pipe_tx0_data_gt ),
.pipe_tx0_elec_idle_o (pipe_tx0_elec_idle_gt ),
.pipe_tx0_powerdown_o (pipe_tx0_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 1
.pipe_rx1_char_is_k_o (pipe_rx1_char_is_k ),
.pipe_rx1_data_o (pipe_rx1_data ),
.pipe_rx1_valid_o (pipe_rx1_valid ),
.pipe_rx1_chanisaligned_o (pipe_rx1_chanisaligned ),
.pipe_rx1_status_o (pipe_rx1_status ),
.pipe_rx1_phy_status_o (pipe_rx1_phy_status ),
.pipe_rx1_elec_idle_i (pipe_rx1_elec_idle_gt ),
.pipe_rx1_polarity_i (pipe_rx1_polarity ),
.pipe_tx1_compliance_i (pipe_tx1_compliance ),
.pipe_tx1_char_is_k_i (pipe_tx1_char_is_k ),
.pipe_tx1_data_i (pipe_tx1_data ),
.pipe_tx1_elec_idle_i (pipe_tx1_elec_idle ),
.pipe_tx1_powerdown_i (pipe_tx1_powerdown ),
.pipe_rx1_char_is_k_i (pipe_rx1_char_is_k_gt ),
.pipe_rx1_data_i (pipe_rx1_data_gt ),
.pipe_rx1_valid_i (pipe_rx1_valid_gt ),
.pipe_rx1_chanisaligned_i (pipe_rx1_chanisaligned_gt),
.pipe_rx1_status_i (pipe_rx1_status_gt ),
.pipe_rx1_phy_status_i (pipe_rx1_phy_status_gt ),
.pipe_rx1_elec_idle_o (pipe_rx1_elec_idle ),
.pipe_rx1_polarity_o (pipe_rx1_polarity_gt ),
.pipe_tx1_compliance_o (pipe_tx1_compliance_gt ),
.pipe_tx1_char_is_k_o (pipe_tx1_char_is_k_gt ),
.pipe_tx1_data_o (pipe_tx1_data_gt ),
.pipe_tx1_elec_idle_o (pipe_tx1_elec_idle_gt ),
.pipe_tx1_powerdown_o (pipe_tx1_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 2
.pipe_rx2_char_is_k_o (pipe_rx2_char_is_k ),
.pipe_rx2_data_o (pipe_rx2_data ),
.pipe_rx2_valid_o (pipe_rx2_valid ),
.pipe_rx2_chanisaligned_o (pipe_rx2_chanisaligned ),
.pipe_rx2_status_o (pipe_rx2_status ),
.pipe_rx2_phy_status_o (pipe_rx2_phy_status ),
.pipe_rx2_elec_idle_i (pipe_rx2_elec_idle_gt ),
.pipe_rx2_polarity_i (pipe_rx2_polarity ),
.pipe_tx2_compliance_i (pipe_tx2_compliance ),
.pipe_tx2_char_is_k_i (pipe_tx2_char_is_k ),
.pipe_tx2_data_i (pipe_tx2_data ),
.pipe_tx2_elec_idle_i (pipe_tx2_elec_idle ),
.pipe_tx2_powerdown_i (pipe_tx2_powerdown ),
.pipe_rx2_char_is_k_i (pipe_rx2_char_is_k_gt ),
.pipe_rx2_data_i (pipe_rx2_data_gt ),
.pipe_rx2_valid_i (pipe_rx2_valid_gt ),
.pipe_rx2_chanisaligned_i (pipe_rx2_chanisaligned_gt),
.pipe_rx2_status_i (pipe_rx2_status_gt ),
.pipe_rx2_phy_status_i (pipe_rx2_phy_status_gt ),
.pipe_rx2_elec_idle_o (pipe_rx2_elec_idle ),
.pipe_rx2_polarity_o (pipe_rx2_polarity_gt ),
.pipe_tx2_compliance_o (pipe_tx2_compliance_gt ),
.pipe_tx2_char_is_k_o (pipe_tx2_char_is_k_gt ),
.pipe_tx2_data_o (pipe_tx2_data_gt ),
.pipe_tx2_elec_idle_o (pipe_tx2_elec_idle_gt ),
.pipe_tx2_powerdown_o (pipe_tx2_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 3
.pipe_rx3_char_is_k_o (pipe_rx3_char_is_k ),
.pipe_rx3_data_o (pipe_rx3_data ),
.pipe_rx3_valid_o (pipe_rx3_valid ),
.pipe_rx3_chanisaligned_o (pipe_rx3_chanisaligned ),
.pipe_rx3_status_o (pipe_rx3_status ),
.pipe_rx3_phy_status_o (pipe_rx3_phy_status ),
.pipe_rx3_elec_idle_i (pipe_rx3_elec_idle_gt ),
.pipe_rx3_polarity_i (pipe_rx3_polarity ),
.pipe_tx3_compliance_i (pipe_tx3_compliance ),
.pipe_tx3_char_is_k_i (pipe_tx3_char_is_k ),
.pipe_tx3_data_i (pipe_tx3_data ),
.pipe_tx3_elec_idle_i (pipe_tx3_elec_idle ),
.pipe_tx3_powerdown_i (pipe_tx3_powerdown ),
.pipe_rx3_char_is_k_i (pipe_rx3_char_is_k_gt ),
.pipe_rx3_data_i (pipe_rx3_data_gt ),
.pipe_rx3_valid_i (pipe_rx3_valid_gt ),
.pipe_rx3_chanisaligned_i (pipe_rx3_chanisaligned_gt),
.pipe_rx3_status_i (pipe_rx3_status_gt ),
.pipe_rx3_phy_status_i (pipe_rx3_phy_status_gt ),
.pipe_rx3_elec_idle_o (pipe_rx3_elec_idle ),
.pipe_rx3_polarity_o (pipe_rx3_polarity_gt ),
.pipe_tx3_compliance_o (pipe_tx3_compliance_gt ),
.pipe_tx3_char_is_k_o (pipe_tx3_char_is_k_gt ),
.pipe_tx3_data_o (pipe_tx3_data_gt ),
.pipe_tx3_elec_idle_o (pipe_tx3_elec_idle_gt ),
.pipe_tx3_powerdown_o (pipe_tx3_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 4
.pipe_rx4_char_is_k_o (pipe_rx4_char_is_k ),
.pipe_rx4_data_o (pipe_rx4_data ),
.pipe_rx4_valid_o (pipe_rx4_valid ),
.pipe_rx4_chanisaligned_o (pipe_rx4_chanisaligned ),
.pipe_rx4_status_o (pipe_rx4_status ),
.pipe_rx4_phy_status_o (pipe_rx4_phy_status ),
.pipe_rx4_elec_idle_i (pipe_rx4_elec_idle_gt ),
.pipe_rx4_polarity_i (pipe_rx4_polarity ),
.pipe_tx4_compliance_i (pipe_tx4_compliance ),
.pipe_tx4_char_is_k_i (pipe_tx4_char_is_k ),
.pipe_tx4_data_i (pipe_tx4_data ),
.pipe_tx4_elec_idle_i (pipe_tx4_elec_idle ),
.pipe_tx4_powerdown_i (pipe_tx4_powerdown ),
.pipe_rx4_char_is_k_i (pipe_rx4_char_is_k_gt ),
.pipe_rx4_data_i (pipe_rx4_data_gt ),
.pipe_rx4_valid_i (pipe_rx4_valid_gt ),
.pipe_rx4_chanisaligned_i (pipe_rx4_chanisaligned_gt),
.pipe_rx4_status_i (pipe_rx4_status_gt ),
.pipe_rx4_phy_status_i (pipe_rx4_phy_status_gt ),
.pipe_rx4_elec_idle_o (pipe_rx4_elec_idle ),
.pipe_rx4_polarity_o (pipe_rx4_polarity_gt ),
.pipe_tx4_compliance_o (pipe_tx4_compliance_gt ),
.pipe_tx4_char_is_k_o (pipe_tx4_char_is_k_gt ),
.pipe_tx4_data_o (pipe_tx4_data_gt ),
.pipe_tx4_elec_idle_o (pipe_tx4_elec_idle_gt ),
.pipe_tx4_powerdown_o (pipe_tx4_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 5
.pipe_rx5_char_is_k_o (pipe_rx5_char_is_k ),
.pipe_rx5_data_o (pipe_rx5_data ),
.pipe_rx5_valid_o (pipe_rx5_valid ),
.pipe_rx5_chanisaligned_o (pipe_rx5_chanisaligned ),
.pipe_rx5_status_o (pipe_rx5_status ),
.pipe_rx5_phy_status_o (pipe_rx5_phy_status ),
.pipe_rx5_elec_idle_i (pipe_rx5_elec_idle_gt ),
.pipe_rx5_polarity_i (pipe_rx5_polarity ),
.pipe_tx5_compliance_i (pipe_tx5_compliance ),
.pipe_tx5_char_is_k_i (pipe_tx5_char_is_k ),
.pipe_tx5_data_i (pipe_tx5_data ),
.pipe_tx5_elec_idle_i (pipe_tx5_elec_idle ),
.pipe_tx5_powerdown_i (pipe_tx5_powerdown ),
.pipe_rx5_char_is_k_i (pipe_rx5_char_is_k_gt ),
.pipe_rx5_data_i (pipe_rx5_data_gt ),
.pipe_rx5_valid_i (pipe_rx5_valid_gt ),
.pipe_rx5_chanisaligned_i (pipe_rx5_chanisaligned_gt),
.pipe_rx5_status_i (pipe_rx5_status_gt ),
.pipe_rx5_phy_status_i (pipe_rx5_phy_status_gt ),
.pipe_rx5_elec_idle_o (pipe_rx5_elec_idle ),
.pipe_rx5_polarity_o (pipe_rx5_polarity_gt ),
.pipe_tx5_compliance_o (pipe_tx5_compliance_gt ),
.pipe_tx5_char_is_k_o (pipe_tx5_char_is_k_gt ),
.pipe_tx5_data_o (pipe_tx5_data_gt ),
.pipe_tx5_elec_idle_o (pipe_tx5_elec_idle_gt ),
.pipe_tx5_powerdown_o (pipe_tx5_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 6
.pipe_rx6_char_is_k_o (pipe_rx6_char_is_k ),
.pipe_rx6_data_o (pipe_rx6_data ),
.pipe_rx6_valid_o (pipe_rx6_valid ),
.pipe_rx6_chanisaligned_o (pipe_rx6_chanisaligned ),
.pipe_rx6_status_o (pipe_rx6_status ),
.pipe_rx6_phy_status_o (pipe_rx6_phy_status ),
.pipe_rx6_elec_idle_i (pipe_rx6_elec_idle_gt ),
.pipe_rx6_polarity_i (pipe_rx6_polarity ),
.pipe_tx6_compliance_i (pipe_tx6_compliance ),
.pipe_tx6_char_is_k_i (pipe_tx6_char_is_k ),
.pipe_tx6_data_i (pipe_tx6_data ),
.pipe_tx6_elec_idle_i (pipe_tx6_elec_idle ),
.pipe_tx6_powerdown_i (pipe_tx6_powerdown ),
.pipe_rx6_char_is_k_i (pipe_rx6_char_is_k_gt ),
.pipe_rx6_data_i (pipe_rx6_data_gt ),
.pipe_rx6_valid_i (pipe_rx6_valid_gt ),
.pipe_rx6_chanisaligned_i (pipe_rx6_chanisaligned_gt),
.pipe_rx6_status_i (pipe_rx6_status_gt ),
.pipe_rx6_phy_status_i (pipe_rx6_phy_status_gt ),
.pipe_rx6_elec_idle_o (pipe_rx6_elec_idle ),
.pipe_rx6_polarity_o (pipe_rx6_polarity_gt ),
.pipe_tx6_compliance_o (pipe_tx6_compliance_gt ),
.pipe_tx6_char_is_k_o (pipe_tx6_char_is_k_gt ),
.pipe_tx6_data_o (pipe_tx6_data_gt ),
.pipe_tx6_elec_idle_o (pipe_tx6_elec_idle_gt ),
.pipe_tx6_powerdown_o (pipe_tx6_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 7
.pipe_rx7_char_is_k_o (pipe_rx7_char_is_k ),
.pipe_rx7_data_o (pipe_rx7_data ),
.pipe_rx7_valid_o (pipe_rx7_valid ),
.pipe_rx7_chanisaligned_o (pipe_rx7_chanisaligned ),
.pipe_rx7_status_o (pipe_rx7_status ),
.pipe_rx7_phy_status_o (pipe_rx7_phy_status ),
.pipe_rx7_elec_idle_i (pipe_rx7_elec_idle_gt ),
.pipe_rx7_polarity_i (pipe_rx7_polarity ),
.pipe_tx7_compliance_i (pipe_tx7_compliance ),
.pipe_tx7_char_is_k_i (pipe_tx7_char_is_k ),
.pipe_tx7_data_i (pipe_tx7_data ),
.pipe_tx7_elec_idle_i (pipe_tx7_elec_idle ),
.pipe_tx7_powerdown_i (pipe_tx7_powerdown ),
.pipe_rx7_char_is_k_i (pipe_rx7_char_is_k_gt ),
.pipe_rx7_data_i (pipe_rx7_data_gt ),
.pipe_rx7_valid_i (pipe_rx7_valid_gt ),
.pipe_rx7_chanisaligned_i (pipe_rx7_chanisaligned_gt),
.pipe_rx7_status_i (pipe_rx7_status_gt ),
.pipe_rx7_phy_status_i (pipe_rx7_phy_status_gt ),
.pipe_rx7_elec_idle_o (pipe_rx7_elec_idle ),
.pipe_rx7_polarity_o (pipe_rx7_polarity_gt ),
.pipe_tx7_compliance_o (pipe_tx7_compliance_gt ),
.pipe_tx7_char_is_k_o (pipe_tx7_char_is_k_gt ),
.pipe_tx7_data_o (pipe_tx7_data_gt ),
.pipe_tx7_elec_idle_o (pipe_tx7_elec_idle_gt ),
.pipe_tx7_powerdown_o (pipe_tx7_powerdown_gt ),
// Non PIPE signals
.pipe_clk (pipe_clk ),
.rst_n (phy_rdy_n )
);
endmodule
|
/**
* insn_out.v - Microcoded Accumulator CPU
* Copyright (C) 2015 Orlando Arias, David Mascenik
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
/* instruction output driver */
module insn_out(
input wire [15 : 0] insn,
input wire clk,
input wire res,
output wire [ 3 : 0] anode,
output wire [ 6 : 0] cathode
);
/* internal frequency scaler parameter */
parameter MSB = 16;
reg [MSB : 0] counter;
reg [ 3 : 0] nibble;
/* seven segment display driver instance */
sseg_driver ssgd0 (
.digit(nibble), /* digit to show */
.sel(counter[MSB:MSB - 1]), /* digit selection */
.anode(anode), /* decoded common anode enable */
.cathode(cathode) /* decoded seven segment cathode */
);
/* internal counter */
always @(posedge clk) begin
if(res) counter <= {(MSB+1){1'b0}};
else counter <= counter + 1'b1;
end
/* nibble multiplexing */
always @(counter[MSB:MSB - 1] or insn) begin
case(counter[MSB:MSB - 1])
2'b00: nibble = insn[ 3 : 0];
2'b01: nibble = insn[ 7 : 4];
2'b10: nibble = insn[11 : 8];
2'b11: nibble = insn[15 :12];
endcase
end
endmodule
/* vim: set ts=4 tw=79 syntax=verilog */
|
Require Import
FormTopC.FormTop
Algebra.SetsC
Algebra.OrderC.
Module JoinTop.
Section JoinTop.
(** We assume we have some type [S] equipped
with a partial order. *)
(** NO! This context gives us two (different) preorders on S.
Will need to fix this. *)
Context {S : PreSpace.t} {ops : JoinLat.Ops S} {JL : JoinLat.t S ops}.
Variable bot : S.
Local Open Scope FT.
Class t : Type :=
{ FT :> FormTop.t S
; bot_ok : @PreO.bottom _ JoinLat.le bot
; bot_Cov : forall U, bot <| U
; join_left : forall a b U, a <| U -> b <| U -> JoinLat.max a b <| U
}.
Hypothesis FTS : t.
(** Check properties we expect to hold *)
Definition singleton (s s' : S) : Prop := s = s'.
Lemma join_right : forall a b c, a <| (singleton b)
-> a <| singleton (JoinLat.max b c).
Proof.
intros. eapply FormTop.trans. apply X. clear X. clear a.
intros a sba. unfold singleton in sba. subst.
apply FormTop.le_left with (JoinLat.max a c).
apply JoinLat.max_ok.
apply FormTop.refl. unfold In in *. subst. reflexivity.
Qed.
End JoinTop.
(** Given a formal topology, we can always produce a join-closed formal
topology by taking "free join" elements (i.e., the free monoid, a list)
and interpreting the cover relation accordingly.
*)
Require Import Coq.Lists.List Types.List.
Section Joinify.
Context {S} {le : S -> Subset S} {PO : PreO.t le}.
Definition leL (xs ys : list S) := forall x,
member x xs -> { y : S & (le x y * member y ys)%type }.
Definition eqL (xs ys : list S) : Type := leL xs ys * leL ys xs.
Definition joinL (xs ys : list S) : list S := xs ++ ys.
Definition ops' : JoinLat.Ops (list S) :=
{| JoinLat.le := leL
; JoinLat.eq := eqL
; JoinLat.max := joinL
|}.
Instance ops : JoinLat.Ops (list S) := ops'.
Require Import CMorphisms.
Instance joinPreO : @PreO.t (list S) leL.
Proof.
constructor; intros.
- simpl. unfold leL. intros. exists x0.
split. apply PreO.le_refl. assumption.
- simpl in *. unfold leL in *. intros.
destruct (X x0 X1). destruct p.
destruct (X0 x1 m). destruct p.
exists x2. split. eapply PreO.le_trans; eassumption.
assumption.
Qed.
Instance joinPO : @PO.t (list S) leL JoinLat.eq.
Proof.
constructor.
- apply joinPreO.
- repeat intro.
destruct X, X0. split; intros.
transitivity x. assumption. transitivity x0; eassumption.
transitivity y; try assumption. transitivity y0; eassumption.
- intros. split; assumption.
Qed.
Lemma joinLE (xs ys xs' ys' : list S) : leL xs xs' -> leL ys ys'
-> leL (xs ++ ys) (xs' ++ ys').
Proof.
unfold leL in *.
intros H H0 x H1.
apply member_app in H1.
destruct H1 as [In1 | In2].
- destruct (H x In1). exists x0. destruct p.
split. assumption. apply member_app. left. assumption.
- destruct (H0 x In2). exists x0. destruct p.
split. assumption. apply member_app. right. assumption.
Qed.
Theorem JL : JoinLat.t (list S) ops.
Proof.
constructor.
- apply joinPO.
- repeat intro. simpl in *. unfold joinL.
unfold eqL in *. destruct X, X0.
auto using joinLE.
- intros. simpl. unfold joinL. constructor; unfold leL; intros.
+ exists x. split. apply PreO.le_refl. apply member_app. auto.
+ exists x. split. apply PreO.le_refl. apply member_app. auto.
+ apply member_app in X1. destruct X1; [apply X | apply X0]; assumption.
Qed.
Variable Cov : S -> (Subset S) -> Prop.
Definition LCov (a : list S) (U : Subset (list S)) :=
forall s : S, member s a -> Cov s (fun s' => { xs : list S & (member s' xs * U xs)%type }).
Instance joinify : FormTop.t le Cov -> t nil LCov.
Proof.
intros FTS.
constructor.
- constructor.
+ unfold LCov. intros. apply FormTop.refl.
exists a. split; assumption.
+ unfold LCov. intros. eapply FormTop.trans.
eapply H. assumption. simpl.
clear s X. intros.
destruct X as (xs & Inxs & Uxs).
eapply H0. eassumption. assumption.
+ simpl. unfold LCov. intros. unfold leL in *.
specialize (X s X0). destruct X as (y & sy & Inyb).
apply FormTop.le_left with y. assumption.
apply H. assumption.
+ unfold LCov. intros.
pose proof (fun (s' : S) (insa : member s' a) =>
@FormTop.le_right _ _ _ _ s' _ _ (H s' insa) (H0 s' insa)).
eapply FormTop.monotone. 2: apply (H1 s X). simpl.
unfold Included, pointwise_rel, arrow; intros.
destruct X0. destruct d, d0. unfold flip, SetsC.In in *.
destruct i as (xs & Inxs & Uxs).
destruct i0 as (ys & Inys & Vys).
exists (cons a0 nil). split. left.
constructor; (econstructor; [eassumption|]);
unfold flip, leL; intros x' inx; simpl in inx; inv inx; subst;
match goal with
| [ H: member ?z ?xs |- { y : _ & (_ * member y ?xs)%type } ] => exists z; split; auto
end.
inv X0. inv X0.
- unfold PreO.bottom. simpl. unfold leL. intros.
inv X.
- unfold LCov. intros. inv X.
- unfold LCov. simpl. unfold joinL. intros.
apply member_app in X. destruct X.
+ apply H; assumption.
+ apply H0; assumption.
Qed.
End Joinify.
End JoinTop.
|
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//
//
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module altpcie_rs_serdes (
input pld_clk,
input [39:0] test_in,
input [4:0] ltssm,
input npor,
input pll_locked,
input busy_altgxb_reconfig,
input [7:0] rx_pll_locked,
input [7:0] rx_freqlocked,
input [7:0] rx_signaldetect,
input use_c4gx_serdes,
input fifo_err,
input rc_inclk_eq_125mhz,
input detect_mask_rxdrst,
output txdigitalreset,
output rxanalogreset,
output rxdigitalreset
);
localparam [19:0] WS_SIM = 20'h00020;
localparam [19:0] WS_1MS_10000 = 20'h186a0;
localparam [19:0] WS_1MS_12500 = 20'h1e848;
localparam [19:0] WS_1MS_15625 = 20'h2625a;
localparam [19:0] WS_1MS_25000 = 20'h3d090;
localparam [1:0] STROBE_TXPLL_LOCKED_SD_CNT = 2'b00;
localparam [1:0] IDLE_ST_CNT = 2'b01;
localparam [1:0] STABLE_TX_PLL_ST_CNT = 2'b10;
localparam [1:0] WAIT_STATE_ST_CNT = 2'b11;
localparam [1:0] IDLE_ST_SD = 2'b00;
localparam [1:0] RSET_ST_SD = 2'b01;
localparam [1:0] DONE_ST_SD = 2'b10;
localparam [1:0] DFLT_ST_SD = 2'b11;
localparam [4:0] LTSSM_POL = 5'b00010;
localparam [4:0] LTSSM_DET = 5'b00000;
genvar i;
// Reset
wire arst;
reg [2:0] arst_r;
// Test
wire test_sim; // When 1 simulation mode
wire test_cbb_compliance; // When 1 DUT is under PCIe Compliance board test mode
(* syn_encoding = "user" *) reg [1:0] serdes_rst_state;
reg [19:0] waitstate_timer;
reg txdigitalreset_r;
reg rxanalogreset_r;
reg rxdigitalreset_r;
reg ws_tmr_eq_0;
reg ld_ws_tmr;
reg ld_ws_tmr_short;
wire rx_pll_freq_locked;
reg [7:0] rx_pll_locked_sync_r;
reg [2:0] rx_pll_freq_locked_cnt ;
reg rx_pll_freq_locked_sync_r ;
reg [1:0] busy_altgxb_reconfig_r;
wire pll_locked_sync;
reg [2:0] pll_locked_r;
reg [6:0] pll_locked_cnt;
reg pll_locked_stable;
wire rx_pll_freq_locked_sync;
reg [2:0] rx_pll_freq_locked_r;
wire [7:0] rx_pll_locked_sync;
reg [7:0] rx_pll_locked_r;
reg [7:0] rx_pll_locked_rr;
reg [7:0] rx_pll_locked_rrr;
wire [7:0] rx_signaldetect_sync;
reg [7:0] rx_signaldetect_r;
reg [7:0] rx_signaldetect_rr;
reg [7:0] rx_signaldetect_rrr;
reg ltssm_detect; // when 1 , the LTSSM is in detect state
reg [7:0] rx_sd_strb0;
reg [7:0] rx_sd_strb1;
wire stable_sd;
wire rst_rxpcs_sd;
(* syn_encoding = "user" *) reg [1:0] sd_state; //State machine for rx_signaldetect strobing;
reg [ 19: 0] rx_sd_idl_cnt;
assign test_sim =test_in[0];
assign test_cbb_compliance =test_in[32];
// SERDES reset outputs
assign txdigitalreset = txdigitalreset_r ;
assign rxanalogreset = (use_c4gx_serdes==1'b1)?arst:rxanalogreset_r ;
assign rxdigitalreset = (detect_mask_rxdrst==1'b0)?rxdigitalreset_r|rst_rxpcs_sd:(ltssm_detect==1'b1)?1'b0:rxdigitalreset_r | rst_rxpcs_sd;
//npor Reset Synchronizer on pld_clk
always @(posedge pld_clk or negedge npor) begin
if (npor == 1'b0) begin
arst_r[2:0] <= 3'b111;
end
else begin
arst_r[2:0] <= {arst_r[1],arst_r[0],1'b0};
end
end
assign arst = arst_r[2];
// Synchronize pll_lock,rx_pll_freq_locked to pld_clk
// using 3 level sync circuit
assign rx_pll_freq_locked = &(rx_pll_locked_sync_r[7:0] | rx_freqlocked[7:0] );
always @(posedge pld_clk or posedge arst) begin
if (arst == 1'b1) begin
pll_locked_r[2:0] <= 3'b000;
rx_pll_freq_locked_r[2:0] <= 3'b000;
end
else begin
pll_locked_r[2:0] <= {pll_locked_r[1],pll_locked_r[0],pll_locked};
rx_pll_freq_locked_r[2:0] <= {rx_pll_freq_locked_r[1],rx_pll_freq_locked_r[0],rx_pll_freq_locked};
end
end
assign pll_locked_sync = pll_locked_r[2];
assign rx_pll_freq_locked_sync = rx_pll_freq_locked_r[2];
// Synchronize rx_pll_locked[7:0],rx_signaldetect[7:0] to pld_clk
// using 3 level sync circuit
generate
for (i=0;i<8;i=i+1) begin : g_rx_pll_locked_sync
always @(posedge pld_clk or posedge arst) begin
if (arst == 1'b1) begin
rx_pll_locked_r[i] <= 1'b0;
rx_pll_locked_rr[i] <= 1'b0;
rx_pll_locked_rrr[i] <= 1'b0;
rx_signaldetect_r[i] <= 1'b0;
rx_signaldetect_rr[i] <= 1'b0;
rx_signaldetect_rrr[i] <= 1'b0;
end
else begin
rx_pll_locked_r[i] <= rx_pll_locked[i];
rx_pll_locked_rr[i] <= rx_pll_locked_r[i];
rx_pll_locked_rrr[i] <= rx_pll_locked_rr[i];
rx_signaldetect_r[i] <= rx_signaldetect[i];
rx_signaldetect_rr[i] <= rx_signaldetect_r[i];
rx_signaldetect_rrr[i] <= rx_signaldetect_rr[i];
end
end
assign rx_pll_locked_sync[i] = rx_pll_locked_rrr[i];
assign rx_signaldetect_sync[i] = rx_signaldetect_rrr[i];
end
endgenerate
always @(posedge pld_clk or posedge arst)
begin
if (arst == 1'b1) begin
txdigitalreset_r <= 1'b1 ;
rxanalogreset_r <= 1'b1 ;
rxdigitalreset_r <= 1'b1 ;
waitstate_timer <= 20'hFFFFF ;
serdes_rst_state <= STROBE_TXPLL_LOCKED_SD_CNT ;
ws_tmr_eq_0 <= 1'b0 ;
ld_ws_tmr <= 1'b1 ;
ld_ws_tmr_short <= 1'b0 ;
rx_pll_freq_locked_cnt <= 3'h0;
rx_pll_freq_locked_sync_r <= 1'b0;
rx_pll_locked_sync_r <= 8'h00;
busy_altgxb_reconfig_r[1:0] <= 2'b11;
pll_locked_cnt <= 7'h0;
pll_locked_stable <= 1'b0;
ltssm_detect <= 1'b1;
end
else begin
if ((ltssm==5'h0)||(ltssm==5'h1)) begin
ltssm_detect <= 1'b1;
end
else begin
ltssm_detect <= 1'b0;
end
if ( rx_pll_locked_sync[7:0]==8'hFF ) begin
rx_pll_locked_sync_r <= 8'hFF;
end
// add hysteresis for losing lock
if (rx_pll_freq_locked_sync == 1'b1) begin
rx_pll_freq_locked_cnt <= 3'h7;
end
else if (rx_pll_freq_locked_cnt == 3'h0) begin
rx_pll_freq_locked_cnt <= 3'h0;
end
else if (rx_pll_freq_locked_sync == 1'b0) begin
rx_pll_freq_locked_cnt <= rx_pll_freq_locked_cnt - 3'h1;
end
rx_pll_freq_locked_sync_r <= (rx_pll_freq_locked_cnt != 3'h0);
busy_altgxb_reconfig_r[1] <= busy_altgxb_reconfig_r[0];
busy_altgxb_reconfig_r[0] <= busy_altgxb_reconfig;
if (pll_locked_sync==1'b0) begin
pll_locked_cnt <= 7'h0;
end
else if (pll_locked_cnt < 7'h7F) begin
pll_locked_cnt <= pll_locked_cnt+7'h1;
end
pll_locked_stable <= (pll_locked_cnt==7'h7F)?1'b1:1'b0;
if (ld_ws_tmr == 1'b1) begin
if (test_sim == 1'b1) begin
waitstate_timer <= WS_SIM ;
end
else if (rc_inclk_eq_125mhz == 1'b1) begin
waitstate_timer <= WS_1MS_12500 ;
end
else begin
waitstate_timer <= WS_1MS_25000 ;
end
end
else if (ld_ws_tmr_short == 1'b1) begin
waitstate_timer <= WS_SIM ;
end
else if (waitstate_timer != 20'h00000) begin
waitstate_timer <= waitstate_timer - 20'h1 ;
end
if (ld_ws_tmr == 1'b1 | ld_ws_tmr_short) begin
ws_tmr_eq_0 <= 1'b0 ;
end
else if (waitstate_timer == 20'h00000) begin
ws_tmr_eq_0 <= 1'b1 ;
end
else begin
ws_tmr_eq_0 <= 1'b0 ;
end
case (serdes_rst_state)
STROBE_TXPLL_LOCKED_SD_CNT : begin
ld_ws_tmr <= 1'b0 ;
if ((pll_locked_sync == 1'b1) && (ws_tmr_eq_0 == 1'b1) && (pll_locked_stable==1'b1)) begin
serdes_rst_state <= (busy_altgxb_reconfig_r[1]==1'b1)?STROBE_TXPLL_LOCKED_SD_CNT:STABLE_TX_PLL_ST_CNT ;
txdigitalreset_r <= 1'b0 ;
rxanalogreset_r <= (busy_altgxb_reconfig_r[1]==1'b1)?1'b1:1'b0;
rxdigitalreset_r <= 1'b1 ;
end
else begin
serdes_rst_state <= STROBE_TXPLL_LOCKED_SD_CNT ;
txdigitalreset_r <= 1'b1 ;
rxanalogreset_r <= 1'b1 ;
rxdigitalreset_r <= 1'b1 ;
end
end
IDLE_ST_CNT : begin
if (rx_pll_freq_locked_sync_r == 1'b1) begin
if (fifo_err == 1'b1) begin
serdes_rst_state <= STABLE_TX_PLL_ST_CNT ;
end
else begin
serdes_rst_state <= IDLE_ST_CNT ;
end
end
else begin
serdes_rst_state <= STROBE_TXPLL_LOCKED_SD_CNT ;
ld_ws_tmr <= 1'b1 ;
end
end
STABLE_TX_PLL_ST_CNT : begin
if (rx_pll_freq_locked_sync_r == 1'b1) begin
serdes_rst_state <= WAIT_STATE_ST_CNT ;
txdigitalreset_r <= 1'b0 ;
rxanalogreset_r <= 1'b0 ;
rxdigitalreset_r <= 1'b1 ;
ld_ws_tmr_short <= 1'b1 ;
end
else begin
serdes_rst_state <= STABLE_TX_PLL_ST_CNT ;
txdigitalreset_r <= 1'b0 ;
rxanalogreset_r <= 1'b0 ;
rxdigitalreset_r <= 1'b1 ;
end
end
WAIT_STATE_ST_CNT : begin
if (rx_pll_freq_locked_sync_r == 1'b1) begin
ld_ws_tmr_short <= 1'b0 ;
if (ld_ws_tmr_short == 1'b0 & ws_tmr_eq_0 == 1'b1) begin
serdes_rst_state <= IDLE_ST_CNT ;
txdigitalreset_r <= 1'b0 ;
rxanalogreset_r <= 1'b0 ;
rxdigitalreset_r <= 1'b0 ;
end
else begin
serdes_rst_state <= WAIT_STATE_ST_CNT ;
txdigitalreset_r <= 1'b0 ;
rxanalogreset_r <= 1'b0 ;
rxdigitalreset_r <= 1'b1 ;
end
end
else begin
serdes_rst_state <= STABLE_TX_PLL_ST_CNT ;
txdigitalreset_r <= 1'b0 ;
rxanalogreset_r <= 1'b0 ;
rxdigitalreset_r <= 1'b1 ;
end
end
default : begin
serdes_rst_state <= STROBE_TXPLL_LOCKED_SD_CNT ;
waitstate_timer <= 20'hFFFFF ;
end
endcase
end
end
////////////////////////////////////////////////////////////////
//
// Signal detect logic use suffix/prefix _sd
//
// rx_signaldetect strobing (stable_sd)
assign rst_rxpcs_sd = ((test_cbb_compliance==1'b1)||(use_c4gx_serdes==1'b1))?1'b0:sd_state[0];
always @(posedge pld_clk or posedge arst) begin
if (arst == 1'b1) begin
rx_sd_strb0[7:0] <= 8'h00;
rx_sd_strb1[7:0] <= 8'h00;
end
else begin
rx_sd_strb0[7:0] <= rx_signaldetect_sync[7:0];
rx_sd_strb1[7:0] <= rx_sd_strb0[7:0];
end
end
assign stable_sd = (rx_sd_strb1[7:0] == rx_sd_strb0[7:0]) & (rx_sd_strb1[7:0] != 8'h00);
//signal detect based reset logic
always @(posedge pld_clk or posedge arst) begin
if (arst == 1'b1) begin
rx_sd_idl_cnt <= 20'h0;
sd_state <= IDLE_ST_SD;
end
else begin
case (sd_state)
IDLE_ST_SD: begin
//reset RXPCS on polling.active
if (ltssm == LTSSM_POL) begin
rx_sd_idl_cnt <= (rx_sd_idl_cnt > 20'd10) ? rx_sd_idl_cnt - 20'd10 : 20'h0;
sd_state <= RSET_ST_SD;
end
else begin //Incoming signal unstable, clear counter
if (stable_sd == 1'b0) begin
rx_sd_idl_cnt <= 20'h0;
end
else if ((stable_sd == 1'b1) & (rx_sd_idl_cnt < 20'd750000)) begin
rx_sd_idl_cnt <= rx_sd_idl_cnt + 20'h1;
end
end
end
RSET_ST_SD: begin
//Incoming data unstable, back to IDLE_ST_SD iff in detect
if (stable_sd == 1'b0) begin
rx_sd_idl_cnt <= 20'h0;
sd_state <= (ltssm == LTSSM_DET) ? IDLE_ST_SD : RSET_ST_SD;
end
else begin
if ((test_sim == 1'b1) & (rx_sd_idl_cnt >= 20'd32)) begin
rx_sd_idl_cnt <= 20'd32;
sd_state <= DONE_ST_SD;
end
else begin
if (rx_sd_idl_cnt == 20'd750000) begin
rx_sd_idl_cnt <= 20'd750000;
sd_state <= DONE_ST_SD;
end
else if (stable_sd == 1'b1) begin
rx_sd_idl_cnt <= rx_sd_idl_cnt + 20'h1;
end
end
end
end
DONE_ST_SD: begin
//Incoming data unstable, back to IDLE_ST_SD iff in detect
if (stable_sd == 1'b0) begin
rx_sd_idl_cnt <= 20'h0;
sd_state <= (ltssm == LTSSM_DET) ? IDLE_ST_SD : DONE_ST_SD;
end
end
default: begin
rx_sd_idl_cnt <= 20'h0;
sd_state <= IDLE_ST_SD;
end
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__XOR2_1_V
`define SKY130_FD_SC_MS__XOR2_1_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog wrapper for xor2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__xor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__xor2_1 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__xor2_1 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__xor2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__XOR2_1_V
|
`timescale 1ns / 1ps
/*
* Copyright 2015 Forest Crossman
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*/
`include "ipcore_dir/osdvu/uart.v"
module uart_demo(
input CLK_100MHz,
input Rx,
output Tx
);
wire reset;
reg transmit;
reg [7:0] tx_byte;
wire received;
wire [7:0] rx_byte;
wire is_receiving;
wire is_transmitting;
wire recv_error;
uart #(
.baud_rate(19200), // This must always be 19200
.sys_clk_freq(100000000) // The master clock frequency
)
uart0(
.clk(CLK_100MHz), // The master clock for this module
.rst(reset), // Synchronous reset
.rx(Rx), // Incoming serial line
.tx(Tx), // Outgoing serial line
.transmit(transmit), // Signal to transmit
.tx_byte(tx_byte), // Byte to transmit
.received(received), // Indicated that a byte has been received
.rx_byte(rx_byte), // Byte received
.is_receiving(is_receiving), // Low when receive line is idle
.is_transmitting(is_transmitting),// Low when transmit line is idle
.recv_error(recv_error) // Indicates error in receiving packet.
);
always @(posedge CLK_100MHz) begin
if (received) begin
tx_byte <= rx_byte;
transmit <= 1;
end
if (is_transmitting) begin
transmit <= 0;
end
end
endmodule
|
//
// Conformal-LEC Version 16.10-d005 ( 21-Apr-2016 ) ( 64 bit executable )
//
module top ( n0 , n1 , n2 , n3 , n4 , n5 , n6 , n7 , n8 , n9 , n10 , n11 , n12 , n13 , n14 , n15 , n16 , n17 , n18 , n19 , n20 , n21 , n22 , n23 , n24 , n25 , n26 , n27 , n28 , n29 , n30 , n31 , n32 , n33 , n34 , n35 , n36 , n37 , n38 , n39 , n40 , n41 , n42 , n43 , n44 , n45 , n46 , n47 , n48 , n49 , n50 , n51 , n52 , n53 , n54 , n55 , n56 , n57 , n58 , n59 , n60 , n61 , n62 , n63 , n64 , n65 , n66 , n67 , n68 , n69 , n70 , n71 , n72 , n73 , n74 , n75 , n76 , n77 , n78 , n79 , n80 , n81 , n82 , n83 , n84 , n85 , n86 , n87 , n88 , n89 , n90 , n91 , n92 , n93 , n94 , n95 , n96 , n97 , n98 , n99 , n100 , n101 , n102 , n103 , n104 , n105 , n106 , n107 , n108 , n109 , n110 , n111 , n112 , n113 , n114 , n115 , n116 , n117 , n118 , n119 , n120 , n121 , n122 , n123 , n124 , n125 , n126 , n127 , n128 , n129 , n130 , n131 , n132 , n133 , n134 , n135 , n136 , n137 , n138 , n139 , n140 , n141 , n142 , n143 , n144 , n145 , n146 , n147 , n148 , n149 , n150 , n151 , n152 , n153 , n154 , n155 , n156 , n157 , n158 , n159 , n160 , n161 , n162 , n163 , n164 , n165 , n166 , n167 , n168 , n169 , n170 , n171 , n172 , n173 , n174 , n175 , n176 , n177 , n178 , n179 , n180 , n181 , n182 , n183 , n184 , n185 , n186 , n187 , n188 , n189 , n190 , n191 , n192 , n193 , n194 , n195 , n196 , n197 , n198 , n199 , n200 , n201 , n202 , n203 , n204 , n205 , n206 , n207 , n208 , n209 , n210 , n211 , n212 , n213 , n214 , n215 , n216 , n217 , n218 , n219 , n220 , n221 , n222 , n223 , n224 , n225 , n226 , n227 , n228 , n229 , n230 , n231 , n232 , n233 , n234 , n235 , n236 , n237 , n238 , n239 , n240 , n241 , n242 , n243 , n244 , n245 , n246 , n247 , n248 , n249 , n250 , n251 , n252 , n253 , n254 , n255 , n256 , n257 , n258 , n259 , n260 , n261 , n262 , n263 , n264 , n265 , n266 , n267 , n268 , n269 , n270 , n271 , n272 , n273 , n274 , n275 , n276 , n277 , n278 , n279 , n280 , n281 , n282 , n283 , n284 , n285 , n286 , n287 , n288 , n289 , n290 , n291 , n292 , n293 , n294 , n295 , n296 , n297 , n298 , n299 , n300 , n301 , n302 , n303 , n304 , n305 , n306 , n307 , n308 , n309 , n310 , n311 , n312 , n313 , n314 , n315 , n316 , n317 , n318 , n319 , n320 , n321 , n322 , n323 , n324 , n325 , n326 , n327 , n328 , n329 , n330 , n331 , n332 , n333 , n334 , n335 , n336 , n337 , n338 , n339 , n340 , n341 , n342 , n343 , n344 , n345 , n346 , n347 , n348 , n349 , n350 , n351 , n352 , n353 , n354 , n355 , n356 , n357 , n358 , n359 , n360 , n361 , n362 , n363 , n364 , n365 , n366 , n367 , n368 , n369 , n370 , n371 , n372 , n373 , n374 , n375 , n376 , n377 , n378 , n379 , n380 , n381 , n382 , n383 , n384 , n385 , n386 , n387 , n388 , n389 , n390 , n391 , n392 , n393 , n394 , n395 , n396 , n397 , n398 , n399 , n400 , n401 , n402 , n403 , n404 , n405 , n406 , n407 , n408 , n409 , n410 , n411 , n412 , n413 , n414 , n415 , n416 , n417 , n418 , n419 , n420 , n421 , n422 , n423 , n424 , n425 , n426 , n427 , n428 , n429 , n430 , n431 , n432 , n433 , n434 , n435 , n436 , n437 , n438 , n439 , n440 , n441 , n442 , n443 , n444 , n445 , n446 , n447 , n448 , n449 , n450 , n451 , n452 , n453 , n454 , n455 , n456 , n457 , n458 , n459 , n460 , n461 , n462 , n463 , n464 , n465 , n466 , n467 , n468 , n469 , n470 , n471 , n472 , n473 , n474 , n475 , n476 , n477 , n478 , n479 , n480 , n481 , n482 , n483 , n484 , n485 , n486 , n487 , n488 , n489 , n490 , n491 , n492 , n493 , n494 , n495 , n496 , n497 , n498 , n499 , n500 , n501 , n502 , n503 , n504 , n505 , n506 , n507 , n508 , n509 , n510 , n511 , n512 , n513 , n514 , n515 , n516 );
input n0 , n1 , n2 , n3 , n4 , n5 , n6 , n7 , n8 , n9 , n10 , n11 , n12 , n13 , n14 , n15 , n16 , n17 , n18 , n19 , n20 , n21 , n22 , n23 , n24 , n25 , n26 , n27 , n28 , n29 , n30 , n31 , n32 , n33 , n34 , n35 , n36 , n37 , n38 , n39 , n40 , n41 , n42 , n43 , n44 , n45 , n46 , n47 , n48 , n49 , n50 , n51 , n52 , n53 , n54 , n55 , n56 , n57 , n58 , n59 , n60 , n61 , n62 , n63 , n64 , n65 , n66 , n67 , n68 , n69 , n70 , n71 , n72 , n73 , n74 , n75 , n76 , n77 , n78 , n79 , n80 , n81 , n82 , n83 , n84 , n85 , n86 , n87 , n88 , n89 , n90 , n91 , n92 , n93 , n94 , n95 , n96 , n97 , n98 , n99 , n100 , n101 , n102 , n103 , n104 , n105 , n106 , n107 , n108 , n109 , n110 , n111 , n112 , n113 , n114 , n115 , n116 , n117 , n118 , n119 , n120 , n121 , n122 , n123 , n124 , n125 , n126 , n127 , n128 , n129 , n130 , n131 , n132 , n133 , n134 , n135 , n136 , n137 , n138 , n139 , n140 , n141 , n142 , n143 , n144 , n145 , n146 , n147 , n148 , n149 , n150 , n151 , n152 , n153 , n154 , n155 , n156 , n157 , n158 , n159 , n160 , n161 , n162 , n163 , n164 , n165 , n166 , n167 , n168 , n169 , n170 , n171 , n172 , n173 , n174 , n175 , n176 , n177 , n178 , n179 , n180 , n181 , n182 , n183 , n184 , n185 , n186 , n187 , n188 , n189 , n190 , n191 , n192 , n193 , n194 , n195 , n196 , n197 , n198 , n199 , n200 , n201 , n202 , n203 , n204 , n205 , n206 , n207 , n208 , n209 , n210 , n211 , n212 , n213 , n214 , n215 , n216 , n217 , n218 , n219 , n220 , n221 , n222 , n223 , n224 , n225 , n226 , n227 , n228 , n229 , n230 , n231 , n232 , n233 , n234 , n235 , n236 , n237 , n238 , n239 , n240 , n241 , n242 , n243 , n244 , n245 , n246 , n247 , n248 , n249 , n250 , n251 , n252 , n253 , n254 , n255 , n256 , n257 , n258 , n259 , n260 , n261 , n262 , n263 , n264 , n265 , n266 , n267 , n268 , n269 , n270 , n271 , n272 , n273 , n274 , n275 , n276 , n277 , n278 , n279 , n280 , n281 , n282 , n283 , n284 , n285 , n286 , n287 , n288 , n289 , n290 , n291 , n292 , n293 , n294 , n295 , n296 , n297 , n298 , n299 , n300 , n301 , n302 , n303 , n304 , n305 , n306 , n307 , n308 , n309 , n310 , n311 , n312 , n313 , n314 , n315 , n316 , n317 , n318 , n319 , n320 , n321 , n322 , n323 , n324 , n325 , n326 , n327 , n328 , n329 , n330 , n331 , n332 , n333 , n334 , n335 , n336 , n337 , n338 , n339 , n340 , n341 , n342 , n343 , n344 , n345 , n346 , n347 , n348 , n349 , n350 , n351 , n352 , n353 , n354 , n355 , n356 , n357 , n358 , n359 , n360 , n361 , n362 , n363 , n364 , n365 , n366 , n367 , n368 , n369 , n370 , n371 , n372 , n373 , n374 , n375 , n376 , n377 , n378 , n379 , n380 , n381 , n382 , n383 , n384 , n385 , n386 , n387 , n388 , n389 , n390 , n391 , n392 , n393 , n394 , n395 , n396 , n397 , n398 , n399 , n400 , n401 , n402 , n403 , n404 , n405 , n406 , n407 , n408 , n409 , n410 , n411 , n412 , n413 , n414 , n415 , n416 , n417 , n418 , n419 , n420 , n421 , n422 , n423 , n424 , n425 , n426 , n427 , n428 , n429 , n430 , n431 , n432 , n433 , n434 , n435 , n436 , n437 , n438 , n439 , n440 , n441 , n442 , n443 , n444 , n445 , n446 , n447 , n448 , n449 , n450 , n451 , n452 , n453 , n454 , n455 , n456 , n457 , n458 , n459 , n460 , n461 , n462 , n463 , n464 , n465 , n466 , n467 , n468 , n469 , n470 , n471 , n472 , n473 , n474 , n475 , n476 , n477 , n478 , n479 , n480 , n481 , n482 , n483 , n484 , n485 , n486 , n487 , n488 , n489 , n490 , n491 , n492 , n493 , n494 , n495 , n496 , n497 , n498 , n499 , n500 , n501 , n502 , n503 , n504 , n505 , n506 , n507 , n508 , n509 , n510 , n511 ;
output n512 , n513 , n514 , n515 , n516 ;
wire n1034 , n1035 , n1036 , n1037 , n1038 , n1039 , n1040 , n1041 , n1042 ,
n1043 , n1044 , n1045 , n1046 , n1047 , n1048 , n1049 , n1050 , n1051 , n1052 ,
n1053 , n1054 , n1055 , n1056 , n1057 , n1058 , n1059 , n1060 , n1061 , n1062 ,
n1063 , n1064 , n1065 , n1066 , n1067 , n1068 , n1069 , n1070 , n1071 , n1072 ,
n1073 , n1074 , n1075 , n1076 , n1077 , n1078 , n1079 , n1080 , n1081 , n1082 ,
n1083 , n1084 , n1085 , n1086 , n1087 , n1088 , n1089 , n1090 , n1091 , n1092 ,
n1093 , n1094 , n1095 , n1096 , n1097 , n1098 , n1099 , n1100 , n1101 , n1102 ,
n1103 , n1104 , n1105 , n1106 , n1107 , n1108 , n1109 , n1110 , n1111 , n1112 ,
n1113 , n1114 , n1115 , n1116 , n1117 , n1118 , n1119 , n1120 , n1121 , n1122 ,
n1123 , n1124 , n1125 , n1126 , n1127 , n1128 , n1129 , n1130 , n1131 , n1132 ,
n1133 , n1134 , n1135 , n1136 , n1137 , n1138 , n1139 , n1140 , n1141 , n1142 ,
n1143 , n1144 , n1145 , n1146 , n1147 , n1148 , n1149 , n1150 , n1151 , n1152 ,
n1153 , n1154 , n1155 , n1156 , n1157 , n1158 , n1159 , n1160 , n1161 , n1162 ,
n1163 , n1164 , n1165 , n1166 , n1167 , n1168 , n1169 , n1170 , n1171 , n1172 ,
n1173 , n1174 , n1175 , n1176 , n1177 , n1178 , n1179 , n1180 , n1181 , n1182 ,
n1183 , n1184 , n1185 , n1186 , n1187 , n1188 , n1189 , n1190 , n1191 , n1192 ,
n1193 , n1194 , n1195 , n1196 , n1197 , n1198 , n1199 , n1200 , n1201 , n1202 ,
n1203 , n1204 , n1205 , n1206 , n1207 , n1208 , n1209 , n1210 , n1211 , n1212 ,
n1213 , n1214 , n1215 , n1216 , n1217 , n1218 , n1219 , n1220 , n1221 , n1222 ,
n1223 , n1224 , n1225 , n1226 , n1227 , n1228 , n1229 , n1230 , n1231 , n1232 ,
n1233 , n1234 , n1235 , n1236 , n1237 , n1238 , n1239 , n1240 , n1241 , n1242 ,
n1243 , n1244 , n1245 , n1246 , n1247 , n1248 , n1249 , n1250 , n1251 , n1252 ,
n1253 , n1254 , n1255 , n1256 , n1257 , n1258 , n1259 , n1260 , n1261 , n1262 ,
n1263 , n1264 , n1265 , n1266 , n1267 , n1268 , n1269 , n1270 , n1271 , n1272 ,
n1273 , n1274 , n1275 , n1276 , n1277 , n1278 , n1279 , n1280 , n1281 , n1282 ,
n1283 , n1284 , n1285 , n1286 , n1287 , n1288 , n1289 , n1290 , n1291 , n1292 ,
n1293 , n1294 , n1295 , n1296 , n1297 , n1298 , n1299 , n1300 , n1301 , n1302 ,
n1303 , n1304 , n1305 , n1306 , n1307 , n1308 , n1309 , n1310 , n1311 , n1312 ,
n1313 , n1314 , n1315 , n1316 , n1317 , n1318 , n1319 , n1320 , n1321 , n1322 ,
n1323 , n1324 , n1325 , n1326 , n1327 , n1328 , n1329 , n1330 , n1331 , n1332 ,
n1333 , n1334 , n1335 , n1336 , n1337 , n1338 , n1339 , n1340 , n1341 , n1342 ,
n1343 , n1344 , n1345 , n1346 , n1347 , n1348 , n1349 , n1350 , n1351 , n1352 ,
n1353 , n1354 , n1355 , n1356 , n1357 , n1358 , n1359 , n1360 , n1361 , n1362 ,
n1363 , n1364 , n1365 , n1366 , n1367 , n1368 , n1369 , n1370 , n1371 , n1372 ,
n1373 , n1374 , n1375 , n1376 , n1377 , n1378 , n1379 , n1380 , n1381 , n1382 ,
n1383 , n1384 , n1385 , n1386 , n1387 , n1388 , n1389 , n1390 , n1391 , n1392 ,
n1393 , n1394 , n1395 , n1396 , n1397 , n1398 , n1399 , n1400 , n1401 , n1402 ,
n1403 , n1404 , n1405 , n1406 , n1407 , n1408 , n1409 , n1410 , n1411 , n1412 ,
n1413 , n1414 , n1415 , n1416 , n1417 , n1418 , n1419 , n1420 , n1421 , n1422 ,
n1423 , n1424 , n1425 , n1426 , n1427 , n1428 , n1429 , n1430 , n1431 , n1432 ,
n1433 , n1434 , n1435 , n1436 , n1437 , n1438 , n1439 , n1440 , n1441 , n1442 ,
n1443 , n1444 , n1445 , n1446 , n1447 , n1448 , n1449 , n1450 , n1451 , n1452 ,
n1453 , n1454 , n1455 , n1456 , n1457 , n1458 , n1459 , n1460 , n1461 , n1462 ,
n1463 , n1464 , n1465 , n1466 , n1467 , n1468 , n1469 , n1470 , n1471 , n1472 ,
n1473 , n1474 , n1475 , n1476 , n1477 , n1478 , n1479 , n1480 , n1481 , n1482 ,
n1483 , n1484 , n1485 , n1486 , n1487 , n1488 , n1489 , n1490 , n1491 , n1492 ,
n1493 , n1494 , n1495 , n1496 , n1497 , n1498 , n1499 , n1500 , n1501 , n1502 ,
n1503 , n1504 , n1505 , n1506 , n1507 , n1508 , n1509 , n1510 , n1511 , n1512 ,
n1513 , n1514 , n1515 , n1516 , n1517 , n1518 , n1519 , n1520 , n1521 , n1522 ,
n1523 , n1524 , n1525 , n1526 , n1527 , n1528 , n1529 , n1530 , n1531 , n1532 ,
n1533 , n1534 , n1535 , n1536 , n1537 , n1538 , n1539 , n1540 , n1541 , n1542 ,
n1543 , n1544 , n1545 , n1546 , n1547 , n1548 , n1549 , n1550 , n1551 , n1552 ,
n1553 , n1554 , n1555 , n1556 , n1557 , n1558 , n1559 , n1560 , n1561 , n1562 ,
n1563 , n1564 , n1565 , n1566 , n1567 , n1568 , n1569 , n1570 , n1571 , n1572 ,
n1573 , n1574 , n1575 , n1576 , n1577 , n1578 , n1579 , n1580 , n1581 , n1582 ,
n1583 , n1584 , n1585 , n1586 , n1587 , n1588 , n1589 , n1590 , n1591 , n1592 ,
n1593 , n1594 , n1595 , n1596 , n1597 , n1598 , n1599 , n1600 , n1601 , n1602 ,
n1603 , n1604 , n1605 , n1606 , n1607 , n1608 , n1609 , n1610 , n1611 , n1612 ,
n1613 , n1614 , n1615 , n1616 , n1617 , n1618 , n1619 , n1620 , n1621 , n1622 ,
n1623 , n1624 , n1625 , n1626 , n1627 , n1628 , n1629 , n1630 , n1631 , n1632 ,
n1633 , n1634 , n1635 , n1636 , n1637 , n1638 , n1639 , n1640 , n1641 , n1642 ,
n1643 , n1644 , n1645 , n1646 , n1647 , n1648 , n1649 , n1650 , n1651 , n1652 ,
n1653 , n1654 , n1655 , n1656 , n1657 , n1658 , n1659 , n1660 , n1661 , n1662 ,
n1663 , n1664 , n1665 , n1666 , n1667 , n1668 , n1669 , n1670 , n1671 , n1672 ,
n1673 , n1674 , n1675 , n1676 , n1677 , n1678 , n1679 , n1680 , n1681 , n1682 ,
n1683 , n1684 , n1685 , n1686 , n1687 , n1688 , n1689 , n1690 , n1691 , n1692 ,
n1693 , n1694 , n1695 , n1696 , n1697 , n1698 , n1699 , n1700 , n1701 , n1702 ,
n1703 , n1704 , n1705 , n1706 , n1707 , n1708 , n1709 , n1710 , n1711 , n1712 ,
n1713 , n1714 , n1715 , n1716 , n1717 , n1718 , n1719 , n1720 , n1721 , n1722 ,
n1723 , n1724 , n1725 , n1726 , n1727 , n1728 , n1729 , n1730 , n1731 , n1732 ,
n1733 , n1734 , n1735 , n1736 , n1737 , n1738 , n1739 , n1740 , n1741 , n1742 ,
n1743 , n1744 , n1745 , n1746 , n1747 , n1748 , n1749 , n1750 , n1751 , n1752 ,
n1753 , n1754 , n1755 , n1756 , n1757 , n1758 , n1759 , n1760 , n1761 , n1762 ,
n1763 , n1764 , n1765 , n1766 , n1767 , n1768 , n1769 , n1770 , n1771 , n1772 ,
n1773 , n1774 , n1775 , n1776 , n1777 , n1778 , n1779 , n1780 , n1781 , n1782 ,
n1783 , n1784 , n1785 , n1786 , n1787 , n1788 , n1789 , n1790 , n1791 , n1792 ,
n1793 , n1794 , n1795 , n1796 , n1797 , n1798 , n1799 , n1800 , n1801 , n1802 ,
n1803 , n1804 , n1805 , n1806 , n1807 , n1808 , n1809 , n1810 , n1811 , n1812 ,
n1813 , n1814 , n1815 , n1816 , n1817 , n1818 , n1819 , n1820 , n1821 , n1822 ,
n1823 , n1824 , n1825 , n1826 , n1827 , n1828 , n1829 , n1830 , n1831 , n1832 ,
n1833 , n1834 , n1835 , n1836 , n1837 , n1838 , n1839 , n1840 , n1841 , n1842 ,
n1843 , n1844 , n1845 , n1846 , n1847 , n1848 , n1849 , n1850 , n1851 , n1852 ,
n1853 , n1854 , n1855 , n1856 , n1857 , n1858 , n1859 , n1860 , n1861 , n1862 ,
n1863 , n1864 , n1865 , n1866 , n1867 , n1868 , n1869 , n1870 , n1871 , n1872 ,
n1873 , n1874 , n1875 , n1876 , n1877 , n1878 , n1879 , n1880 , n1881 , n1882 ,
n1883 , n1884 , n1885 , n1886 , n1887 , n1888 , n1889 , n1890 , n1891 , n1892 ,
n1893 , n1894 , n1895 , n1896 , n1897 , n1898 , n1899 , n1900 , n1901 , n1902 ,
n1903 , n1904 , n1905 , n1906 , n1907 , n1908 , n1909 , n1910 , n1911 , n1912 ,
n1913 , n1914 , n1915 , n1916 , n1917 , n1918 , n1919 , n1920 , n1921 , n1922 ,
n1923 , n1924 , n1925 , n1926 , n1927 , n1928 , n1929 , n1930 , n1931 , n1932 ,
n1933 , n1934 , n1935 , n1936 , n1937 , n1938 , n1939 , n1940 , n1941 , n1942 ,
n1943 , n1944 , n1945 , n1946 , n1947 , n1948 , n1949 , n1950 , n1951 , n1952 ,
n1953 , n1954 , n1955 , n1956 , n1957 , n1958 , n1959 , n1960 , n1961 , n1962 ,
n1963 , n1964 , n1965 , n1966 , n1967 , n1968 , n1969 , n1970 , n1971 , n1972 ,
n1973 , n1974 , n1975 , n1976 , n1977 , n1978 , n1979 , n1980 , n1981 , n1982 ,
n1983 , n1984 , n1985 , n1986 , n1987 , n1988 , n1989 , n1990 , n1991 , n1992 ,
n1993 , n1994 , n1995 , n1996 , n1997 , n1998 , n1999 , n2000 , n2001 , n2002 ,
n2003 , n2004 , n2005 , n2006 , n2007 , n2008 , n2009 , n2010 , n2011 , n2012 ,
n2013 , n2014 , n2015 , n2016 , n2017 , n2018 , n2019 , n2020 , n2021 , n2022 ,
n2023 , n2024 , n2025 , n2026 , n2027 , n2028 , n2029 , n2030 , n2031 , n2032 ,
n2033 , n2034 , n2035 , n2036 , n2037 , n2038 , n2039 , n2040 , n2041 , n2042 ,
n2043 , n2044 , n2045 , n2046 , n2047 , n2048 , n2049 , n2050 , n2051 , n2052 ,
n2053 , n2054 , n2055 , n2056 , n2057 , n2058 , n2059 , n2060 , n2061 , n2062 ,
n2063 , n2064 , n2065 , n2066 , n2067 , n2068 , n2069 , n2070 , n2071 , n2072 ,
n2073 , n2074 , n2075 , n2076 , n2077 , n2078 , n2079 , n2080 , n2081 , n2082 ,
n2083 , n2084 , n2085 , n2086 , n2087 , n2088 , n2089 , n2090 , n2091 , n2092 ,
n2093 , n2094 , n2095 , n2096 , n2097 , n2098 , n2099 , n2100 , n2101 , n2102 ,
n2103 , n2104 , n2105 , n2106 , n2107 , n2108 , n2109 , n2110 , n2111 , n2112 ,
n2113 , n2114 , n2115 , n2116 , n2117 , n2118 , n2119 , n2120 , n2121 , n2122 ,
n2123 , n2124 , n2125 , n2126 , n2127 , n2128 , n2129 , n2130 , n2131 , n2132 ,
n2133 , n2134 , n2135 , n2136 , n2137 , n2138 , n2139 , n2140 , n2141 , n2142 ,
n2143 , n2144 , n2145 , n2146 , n2147 , n2148 , n2149 , n2150 , n2151 , n2152 ,
n2153 , n2154 , n2155 , n2156 , n2157 , n2158 , n2159 , n2160 , n2161 , n2162 ,
n2163 , n2164 , n2165 , n2166 , n2167 , n2168 , n2169 , n2170 , n2171 , n2172 ,
n2173 , n2174 , n2175 , n2176 , n2177 , n2178 , n2179 , n2180 , n2181 , n2182 ,
n2183 , n2184 , n2185 , n2186 , n2187 , n2188 , n2189 , n2190 , n2191 , n2192 ,
n2193 , n2194 , n2195 , n2196 , n2197 , n2198 , n2199 , n2200 , n2201 , n2202 ,
n2203 , n2204 , n2205 , n2206 , n2207 , n2208 , n2209 , n2210 , n2211 , n2212 ,
n2213 , n2214 , n2215 , n2216 , n2217 , n2218 , n2219 , n2220 , n2221 , n2222 ,
n2223 , n2224 , n2225 , n2226 , n2227 , n2228 , n2229 , n2230 , n2231 , n2232 ,
n2233 , n2234 , n2235 , n2236 , n2237 , n2238 , n2239 , n2240 , n2241 , n2242 ,
n2243 , n2244 , n2245 , n2246 , n2247 , n2248 , n2249 , n2250 , n2251 , n2252 ,
n2253 , n2254 , n2255 , n2256 , n2257 , n2258 , n2259 , n2260 , n2261 , n2262 ,
n2263 , n2264 , n2265 , n2266 , n2267 , n2268 , n2269 , n2270 , n2271 , n2272 ,
n2273 , n2274 , n2275 , n2276 , n2277 , n2278 , n2279 , n2280 , n2281 , n2282 ,
n2283 , n2284 , n2285 , n2286 , n2287 , n2288 , n2289 , n2290 , n2291 , n2292 ,
n2293 , n2294 , n2295 , n2296 , n2297 , n2298 , n2299 , n2300 , n2301 , n2302 ,
n2303 , n2304 , n2305 , n2306 , n2307 , n2308 , n2309 , n2310 , n2311 , n2312 ,
n2313 , n2314 , n2315 , n2316 , n2317 , n2318 , n2319 , n2320 , n2321 , n2322 ,
n2323 , n2324 , n2325 , n2326 , n2327 , n2328 , n2329 , n2330 , n2331 , n2332 ,
n2333 , n2334 , n2335 , n2336 , n2337 , n2338 , n2339 , n2340 , n2341 , n2342 ,
n2343 , n2344 , n2345 , n2346 , n2347 , n2348 , n2349 , n2350 , n2351 , n2352 ,
n2353 , n2354 , n2355 , n2356 , n2357 , n2358 , n2359 , n2360 , n2361 , n2362 ,
n2363 , n2364 , n2365 , n2366 , n2367 , n2368 , n2369 , n2370 , n2371 , n2372 ,
n2373 , n2374 , n2375 , n2376 , n2377 , n2378 , n2379 , n2380 , n2381 , n2382 ,
n2383 , n2384 , n2385 , n2386 , n2387 , n2388 , n2389 , n2390 , n2391 , n2392 ,
n2393 , n2394 , n2395 , n2396 , n2397 , n2398 , n2399 , n2400 , n2401 , n2402 ,
n2403 , n2404 , n2405 , n2406 , n2407 , n2408 , n2409 , n2410 , n2411 , n2412 ,
n2413 , n2414 , n2415 , n2416 , n2417 , n2418 , n2419 , n2420 , n2421 , n2422 ,
n2423 , n2424 , n2425 , n2426 , n2427 , n2428 , n2429 , n2430 , n2431 , n2432 ,
n2433 , n2434 , n2435 , n2436 , n2437 , n2438 , n2439 , n2440 , n2441 , n2442 ,
n2443 , n2444 , n2445 , n2446 , n2447 , n2448 , n2449 , n2450 , n2451 , n2452 ,
n2453 , n2454 , n2455 , n2456 , n2457 , n2458 , n2459 , n2460 , n2461 , n2462 ,
n2463 , n2464 , n2465 , n2466 , n2467 , n2468 , n2469 , n2470 , n2471 , n2472 ,
n2473 , n2474 , n2475 , n2476 , n2477 , n2478 , n2479 , n2480 , n2481 , n2482 ,
n2483 , n2484 , n2485 , n2486 , n2487 , n2488 , n2489 , n2490 , n2491 , n2492 ,
n2493 , n2494 , n2495 , n2496 , n2497 , n2498 , n2499 , n2500 , n2501 , n2502 ,
n2503 , n2504 , n2505 , n2506 , n2507 , n2508 , n2509 , n2510 , n2511 , n2512 ,
n2513 , n2514 , n2515 , n2516 , n2517 , n2518 , n2519 , n2520 , n2521 , n2522 ,
n2523 , n2524 , n2525 , n2526 , n2527 , n2528 , n2529 , n2530 , n2531 , n2532 ,
n2533 , n2534 , n2535 , n2536 , n2537 , n2538 , n2539 , n2540 , n2541 , n2542 ,
n2543 , n2544 , n2545 , n2546 , n2547 , n2548 , n2549 , n2550 , n2551 , n2552 ,
n2553 , n2554 , n2555 , n2556 , n2557 , n2558 , n2559 , n2560 , n2561 , n2562 ,
n2563 , n2564 , n2565 , n2566 , n2567 , n2568 , n2569 , n2570 , n2571 , n2572 ,
n2573 , n2574 , n2575 , n2576 , n2577 , n2578 , n2579 , n2580 , n2581 , n2582 ,
n2583 , n2584 , n2585 , n2586 , n2587 , n2588 , n2589 , n2590 , n2591 , n2592 ,
n2593 , n2594 , n2595 , n2596 , n2597 , n2598 , n2599 , n2600 , n2601 , n2602 ,
n2603 , n2604 , n2605 , n2606 , n2607 , n2608 , n2609 , n2610 , n2611 , n2612 ,
n2613 , n2614 , n2615 , n2616 , n2617 , n2618 , n2619 , n2620 , n2621 , n2622 ,
n2623 , n2624 , n2625 , n2626 , n2627 , n2628 , n2629 , n2630 , n2631 , n2632 ,
n2633 , n2634 , n2635 , n2636 , n2637 , n2638 , n2639 , n2640 , n2641 , n2642 ,
n2643 , n2644 , n2645 , n2646 , n2647 , n2648 , n2649 , n2650 , n2651 , n2652 ,
n2653 , n2654 , n2655 , n2656 , n2657 , n2658 , n2659 , n2660 , n2661 , n2662 ,
n2663 , n2664 , n2665 , n2666 , n2667 , n2668 , n2669 , n2670 , n2671 , n2672 ,
n2673 , n2674 , n2675 , n2676 , n2677 , n2678 , n2679 , n2680 , n2681 , n2682 ,
n2683 , n2684 , n2685 , n2686 , n2687 , n2688 , n2689 , n2690 , n2691 , n2692 ,
n2693 , n2694 , n2695 , n2696 , n2697 , n2698 , n2699 , n2700 , n2701 , n2702 ,
n2703 , n2704 , n2705 , n2706 , n2707 , n2708 , n2709 , n2710 , n2711 , n2712 ,
n2713 , n2714 , n2715 , n2716 , n2717 , n2718 , n2719 , n2720 , n2721 , n2722 ,
n2723 , n2724 , n2725 , n2726 , n2727 , n2728 , n2729 , n2730 , n2731 , n2732 ,
n2733 , n2734 , n2735 , n2736 , n2737 , n2738 , n2739 , n2740 , n2741 , n2742 ,
n2743 , n2744 , n2745 , n2746 , n2747 , n2748 , n2749 , n2750 , n2751 , n2752 ,
n2753 , n2754 , n2755 , n2756 , n2757 , n2758 , n2759 , n2760 , n2761 , n2762 ,
n2763 , n2764 , n2765 , n2766 , n2767 , n2768 , n2769 , n2770 , n2771 , n2772 ,
n2773 , n2774 , n2775 , n2776 , n2777 , n2778 , n2779 , n2780 , n2781 , n2782 ,
n2783 , n2784 , n2785 , n2786 , n2787 , n2788 , n2789 , n2790 , n2791 , n2792 ,
n2793 , n2794 , n2795 , n2796 , n2797 , n2798 , n2799 , n2800 , n2801 , n2802 ,
n2803 , n2804 , n2805 , n2806 , n2807 , n2808 , n2809 , n2810 , n2811 , n2812 ,
n2813 , n2814 , n2815 , n2816 , n2817 , n2818 , n2819 , n2820 , n2821 , n2822 ,
n2823 , n2824 , n2825 , n2826 , n2827 , n2828 , n2829 , n2830 , n2831 , n2832 ,
n2833 , n2834 , n2835 , n2836 , n2837 , n2838 , n2839 , n2840 , n2841 , n2842 ,
n2843 , n2844 , n2845 , n2846 , n2847 , n2848 , n2849 , n2850 , n2851 , n2852 ,
n2853 , n2854 , n2855 , n2856 , n2857 , n2858 , n2859 , n2860 , n2861 , n2862 ,
n2863 , n2864 , n2865 , n2866 , n2867 , n2868 , n2869 , n2870 , n2871 , n2872 ,
n2873 , n2874 , n2875 , n2876 , n2877 , n2878 , n2879 , n2880 , n2881 , n2882 ,
n2883 , n2884 , n2885 , n2886 , n2887 , n2888 , n2889 , n2890 , n2891 , n2892 ,
n2893 , n2894 , n2895 , n2896 , n2897 , n2898 , n2899 , n2900 , n2901 , n2902 ,
n2903 , n2904 , n2905 , n2906 , n2907 , n2908 , n2909 , n2910 , n2911 , n2912 ,
n2913 , n2914 , n2915 , n2916 , n2917 , n2918 , n2919 , n2920 , n2921 , n2922 ,
n2923 , n2924 , n2925 , n2926 , n2927 , n2928 , n2929 , n2930 , n2931 , n2932 ,
n2933 , n2934 , n2935 , n2936 , n2937 , n2938 , n2939 , n2940 , n2941 , n2942 ,
n2943 , n2944 , n2945 , n2946 , n2947 , n2948 , n2949 , n2950 , n2951 , n2952 ,
n2953 , n2954 , n2955 , n2956 , n2957 , n2958 , n2959 , n2960 , n2961 , n2962 ,
n2963 , n2964 , n2965 , n2966 , n2967 , n2968 , n2969 , n2970 , n2971 , n2972 ,
n2973 , n2974 , n2975 , n2976 , n2977 , n2978 , n2979 , n2980 , n2981 , n2982 ,
n2983 , n2984 , n2985 , n2986 , n2987 , n2988 , n2989 , n2990 , n2991 , n2992 ,
n2993 , n2994 , n2995 , n2996 , n2997 , n2998 , n2999 , n3000 , n3001 , n3002 ,
n3003 , n3004 , n3005 , n3006 , n3007 , n3008 , n3009 , n3010 , n3011 , n3012 ,
n3013 , n3014 , n3015 , n3016 , n3017 , n3018 , n3019 , n3020 , n3021 , n3022 ,
n3023 , n3024 , n3025 , n3026 , n3027 , n3028 , n3029 , n3030 , n3031 , n3032 ,
n3033 , n3034 , n3035 , n3036 , n3037 , n3038 , n3039 , n3040 , n3041 , n3042 ,
n3043 , n3044 , n3045 , n3046 , n3047 , n3048 , n3049 , n3050 , n3051 , n3052 ,
n3053 , n3054 , n3055 , n3056 , n3057 , n3058 , n3059 , n3060 , n3061 , n3062 ,
n3063 , n3064 , n3065 , n3066 , n3067 , n3068 , n3069 , n3070 , n3071 , n3072 ,
n3073 , n3074 , n3075 , n3076 , n3077 , n3078 , n3079 , n3080 , n3081 , n3082 ,
n3083 , n3084 , n3085 , n3086 , n3087 , n3088 , n3089 , n3090 , n3091 , n3092 ,
n3093 , n3094 , n3095 , n3096 , n3097 , n3098 , n3099 , n3100 , n3101 , n3102 ,
n3103 , n3104 , n3105 , n3106 , n3107 , n3108 , n3109 , n3110 , n3111 , n3112 ,
n3113 , n3114 , n3115 , n3116 , n3117 , n3118 , n3119 , n3120 , n3121 , n3122 ,
n3123 , n3124 , n3125 , n3126 , n3127 , n3128 , n3129 , n3130 , n3131 , n3132 ,
n3133 , n3134 , n3135 , n3136 , n3137 , n3138 , n3139 , n3140 , n3141 , n3142 ,
n3143 , n3144 , n3145 , n3146 , n3147 , n3148 , n3149 , n3150 , n3151 , n3152 ,
n3153 , n3154 , n3155 , n3156 , n3157 , n3158 , n3159 , n3160 , n3161 , n3162 ,
n3163 , n3164 , n3165 , n3166 , n3167 , n3168 , n3169 , n3170 , n3171 , n3172 ,
n3173 , n3174 , n3175 , n3176 , n3177 , n3178 , n3179 , n3180 , n3181 , n3182 ,
n3183 , n3184 , n3185 , n3186 , n3187 , n3188 , n3189 , n3190 , n3191 , n3192 ,
n3193 , n3194 , n3195 , n3196 , n3197 , n3198 , n3199 , n3200 , n3201 , n3202 ,
n3203 , n3204 , n3205 , n3206 , n3207 , n3208 , n3209 , n3210 , n3211 , n3212 ,
n3213 , n3214 , n3215 , n3216 , n3217 , n3218 , n3219 , n3220 , n3221 , n3222 ,
n3223 , n3224 , n3225 , n3226 , n3227 , n3228 , n3229 , n3230 , n3231 , n3232 ,
n3233 , n3234 , n3235 , n3236 , n3237 , n3238 , n3239 , n3240 , n3241 , n3242 ,
n3243 , n3244 , n3245 , n3246 , n3247 , n3248 , n3249 , n3250 , n3251 , n3252 ,
n3253 , n3254 , n3255 , n3256 , n3257 , n3258 , n3259 , n3260 , n3261 , n3262 ,
n3263 , n3264 , n3265 , n3266 , n3267 , n3268 , n3269 , n3270 , n3271 , n3272 ,
n3273 , n3274 , n3275 , n3276 , n3277 , n3278 , n3279 , n3280 , n3281 , n3282 ,
n3283 , n3284 , n3285 , n3286 , n3287 , n3288 , n3289 , n3290 , n3291 , n3292 ,
n3293 , n3294 , n3295 , n3296 , n3297 , n3298 , n3299 , n3300 , n3301 , n3302 ,
n3303 , n3304 , n3305 , n3306 , n3307 , n3308 , n3309 , n3310 , n3311 , n3312 ,
n3313 , n3314 , n3315 , n3316 , n3317 , n3318 , n3319 , n3320 , n3321 , n3322 ,
n3323 , n3324 , n3325 , n3326 , n3327 , n3328 , n3329 , n3330 , n3331 , n3332 ,
n3333 , n3334 , n3335 , n3336 , n3337 , n3338 , n3339 , n3340 , n3341 , n3342 ,
n3343 , n3344 , n3345 , n3346 , n3347 , n3348 , n3349 , n3350 , n3351 , n3352 ,
n3353 , n3354 , n3355 , n3356 , n3357 , n3358 , n3359 , n3360 , n3361 , n3362 ,
n3363 , n3364 , n3365 , n3366 , n3367 , n3368 , n3369 , n3370 , n3371 , n3372 ,
n3373 , n3374 , n3375 , n3376 , n3377 , n3378 , n3379 , n3380 , n3381 , n3382 ,
n3383 , n3384 , n3385 , n3386 , n3387 , n3388 , n3389 , n3390 , n3391 , n3392 ,
n3393 , n3394 , n3395 , n3396 , n3397 , n3398 , n3399 , n3400 , n3401 , n3402 ,
n3403 , n3404 , n3405 , n3406 , n3407 , n3408 , n3409 , n3410 , n3411 , n3412 ,
n3413 , n3414 , n3415 , n3416 , n3417 , n3418 , n3419 , n3420 , n3421 , n3422 ,
n3423 , n3424 , n3425 , n3426 , n3427 , n3428 , n3429 , n3430 , n3431 , n3432 ,
n3433 , n3434 , n3435 , n3436 , n3437 , n3438 , n3439 , n3440 , n3441 , n3442 ,
n3443 , n3444 , n3445 , n3446 , n3447 , n3448 , n3449 , n3450 , n3451 , n3452 ,
n3453 , n3454 , n3455 , n3456 , n3457 , n3458 , n3459 , n3460 , n3461 , n3462 ,
n3463 , n3464 , n3465 , n3466 , n3467 , n3468 , n3469 , n3470 , n3471 , n3472 ,
n3473 , n3474 , n3475 , n3476 , n3477 , n3478 , n3479 , n3480 , n3481 , n3482 ,
n3483 , n3484 , n3485 , n3486 , n3487 , n3488 , n3489 , n3490 , n3491 , n3492 ,
n3493 , n3494 , n3495 , n3496 , n3497 , n3498 , n3499 , n3500 , n3501 , n3502 ,
n3503 , n3504 , n3505 , n3506 , n3507 , n3508 , n3509 , n3510 , n3511 , n3512 ,
n3513 , n3514 , n3515 , n3516 , n3517 , n3518 , n3519 , n3520 , n3521 , n3522 ,
n3523 , n3524 , n3525 , n3526 , n3527 , n3528 , n3529 , n3530 , n3531 , n3532 ,
n3533 , n3534 , n3535 , n3536 , n3537 , n3538 , n3539 , n3540 , n3541 , n3542 ,
n3543 , n3544 , n3545 , n3546 , n3547 , n3548 , n3549 , n3550 , n3551 , n3552 ,
n3553 , n3554 , n3555 , n3556 , n3557 , n3558 , n3559 , n3560 , n3561 , n3562 ,
n3563 , n3564 , n3565 , n3566 , n3567 , n3568 , n3569 , n3570 , n3571 , n3572 ,
n3573 , n3574 , n3575 , n3576 , n3577 , n3578 , n3579 , n3580 , n3581 , n3582 ,
n3583 , n3584 , n3585 , n3586 , n3587 , n3588 , n3589 , n3590 , n3591 , n3592 ,
n3593 , n3594 , n3595 , n3596 ;
buf ( n513 , n3573 );
buf ( n515 , n3587 );
buf ( n512 , n3591 );
buf ( n516 , n3594 );
buf ( n514 , n3596 );
buf ( n1036 , n244 );
buf ( n1037 , n312 );
buf ( n1038 , n489 );
buf ( n1039 , n494 );
buf ( n1040 , n55 );
buf ( n1041 , n213 );
buf ( n1042 , n68 );
buf ( n1043 , n298 );
buf ( n1044 , n77 );
buf ( n1045 , n38 );
buf ( n1046 , n32 );
buf ( n1047 , n448 );
buf ( n1048 , n388 );
buf ( n1049 , n360 );
buf ( n1050 , n156 );
buf ( n1051 , n286 );
buf ( n1052 , n405 );
buf ( n1053 , n209 );
buf ( n1054 , n472 );
buf ( n1055 , n33 );
buf ( n1056 , n397 );
buf ( n1057 , n101 );
buf ( n1058 , n357 );
buf ( n1059 , n289 );
buf ( n1060 , n498 );
buf ( n1061 , n164 );
buf ( n1062 , n115 );
buf ( n1063 , n103 );
buf ( n1064 , n67 );
buf ( n1065 , n139 );
buf ( n1066 , n121 );
buf ( n1067 , n358 );
buf ( n1068 , n483 );
buf ( n1069 , n131 );
buf ( n1070 , n95 );
buf ( n1071 , n74 );
buf ( n1072 , n221 );
buf ( n1073 , n49 );
buf ( n1074 , n185 );
buf ( n1075 , n206 );
buf ( n1076 , n379 );
buf ( n1077 , n464 );
buf ( n1078 , n75 );
buf ( n1079 , n136 );
buf ( n1080 , n184 );
buf ( n1081 , n203 );
buf ( n1082 , n278 );
buf ( n1083 , n153 );
buf ( n1084 , n178 );
buf ( n1085 , n159 );
buf ( n1086 , n283 );
buf ( n1087 , n255 );
buf ( n1088 , n404 );
buf ( n1089 , n275 );
buf ( n1090 , n353 );
buf ( n1091 , n73 );
buf ( n1092 , n105 );
buf ( n1093 , n462 );
buf ( n1094 , n102 );
buf ( n1095 , n120 );
buf ( n1096 , n249 );
buf ( n1097 , n441 );
buf ( n1098 , n402 );
buf ( n1099 , n225 );
buf ( n1100 , n238 );
buf ( n1101 , n455 );
buf ( n1102 , n363 );
buf ( n1103 , n147 );
buf ( n1104 , n224 );
buf ( n1105 , n128 );
buf ( n1106 , n52 );
buf ( n1107 , n108 );
buf ( n1108 , n486 );
buf ( n1109 , n471 );
buf ( n1110 , n356 );
buf ( n1111 , n276 );
buf ( n1112 , n454 );
buf ( n1113 , n9 );
buf ( n1114 , n281 );
buf ( n1115 , n180 );
buf ( n1116 , n324 );
buf ( n1117 , n340 );
buf ( n1118 , n309 );
buf ( n1119 , n337 );
buf ( n1120 , n484 );
buf ( n1121 , n291 );
buf ( n1122 , n349 );
buf ( n1123 , n375 );
buf ( n1124 , n325 );
buf ( n1125 , n195 );
buf ( n1126 , n425 );
buf ( n1127 , n507 );
buf ( n1128 , n461 );
buf ( n1129 , n460 );
buf ( n1130 , n348 );
buf ( n1131 , n328 );
buf ( n1132 , n467 );
buf ( n1133 , n65 );
buf ( n1134 , n506 );
buf ( n1135 , n208 );
buf ( n1136 , n273 );
buf ( n1137 , n352 );
buf ( n1138 , n84 );
buf ( n1139 , n230 );
buf ( n1140 , n100 );
buf ( n1141 , n346 );
buf ( n1142 , n362 );
buf ( n1143 , n177 );
buf ( n1144 , n509 );
buf ( n1145 , n192 );
buf ( n1146 , n24 );
buf ( n1147 , n22 );
buf ( n1148 , n158 );
buf ( n1149 , n92 );
buf ( n1150 , n411 );
buf ( n1151 , n343 );
buf ( n1152 , n62 );
buf ( n1153 , n459 );
buf ( n1154 , n126 );
buf ( n1155 , n111 );
buf ( n1156 , n58 );
buf ( n1157 , n439 );
buf ( n1158 , n313 );
buf ( n1159 , n130 );
buf ( n1160 , n37 );
buf ( n1161 , n345 );
buf ( n1162 , n135 );
buf ( n1163 , n475 );
buf ( n1164 , n223 );
buf ( n1165 , n233 );
buf ( n1166 , n389 );
buf ( n1167 , n393 );
buf ( n1168 , n236 );
buf ( n1169 , n143 );
buf ( n1170 , n216 );
buf ( n1171 , n430 );
buf ( n1172 , n399 );
buf ( n1173 , n28 );
buf ( n1174 , n378 );
buf ( n1175 , n350 );
buf ( n1176 , n23 );
buf ( n1177 , n246 );
buf ( n1178 , n320 );
buf ( n1179 , n499 );
buf ( n1180 , n112 );
buf ( n1181 , n410 );
buf ( n1182 , n160 );
buf ( n1183 , n386 );
buf ( n1184 , n418 );
buf ( n1185 , n194 );
buf ( n1186 , n318 );
buf ( n1187 , n432 );
buf ( n1188 , n219 );
buf ( n1189 , n477 );
buf ( n1190 , n170 );
buf ( n1191 , n282 );
buf ( n1192 , n331 );
buf ( n1193 , n372 );
buf ( n1194 , n505 );
buf ( n1195 , n6 );
buf ( n1196 , n14 );
buf ( n1197 , n271 );
buf ( n1198 , n168 );
buf ( n1199 , n248 );
buf ( n1200 , n149 );
buf ( n1201 , n0 );
buf ( n1202 , n382 );
buf ( n1203 , n447 );
buf ( n1204 , n56 );
buf ( n1205 , n110 );
buf ( n1206 , n162 );
buf ( n1207 , n150 );
buf ( n1208 , n123 );
buf ( n1209 , n390 );
buf ( n1210 , n323 );
buf ( n1211 , n371 );
buf ( n1212 , n303 );
buf ( n1213 , n34 );
buf ( n1214 , n480 );
buf ( n1215 , n127 );
buf ( n1216 , n429 );
buf ( n1217 , n338 );
buf ( n1218 , n25 );
buf ( n1219 , n82 );
buf ( n1220 , n215 );
buf ( n1221 , n502 );
buf ( n1222 , n450 );
buf ( n1223 , n335 );
buf ( n1224 , n272 );
buf ( n1225 , n446 );
buf ( n1226 , n187 );
buf ( n1227 , n161 );
buf ( n1228 , n361 );
buf ( n1229 , n99 );
buf ( n1230 , n302 );
buf ( n1231 , n334 );
buf ( n1232 , n85 );
buf ( n1233 , n129 );
buf ( n1234 , n481 );
buf ( n1235 , n417 );
buf ( n1236 , n394 );
buf ( n1237 , n193 );
buf ( n1238 , n125 );
buf ( n1239 , n152 );
buf ( n1240 , n88 );
buf ( n1241 , n332 );
buf ( n1242 , n339 );
buf ( n1243 , n122 );
buf ( n1244 , n252 );
buf ( n1245 , n280 );
buf ( n1246 , n458 );
buf ( n1247 , n148 );
buf ( n1248 , n500 );
buf ( n1249 , n235 );
buf ( n1250 , n431 );
buf ( n1251 , n401 );
buf ( n1252 , n277 );
buf ( n1253 , n46 );
buf ( n1254 , n327 );
buf ( n1255 , n189 );
buf ( n1256 , n501 );
buf ( n1257 , n510 );
buf ( n1258 , n40 );
buf ( n1259 , n307 );
buf ( n1260 , n262 );
buf ( n1261 , n300 );
buf ( n1262 , n419 );
buf ( n1263 , n463 );
buf ( n1264 , n17 );
buf ( n1265 , n493 );
buf ( n1266 , n54 );
buf ( n1267 , n288 );
buf ( n1268 , n310 );
buf ( n1269 , n241 );
buf ( n1270 , n336 );
buf ( n1271 , n87 );
buf ( n1272 , n228 );
buf ( n1273 , n78 );
buf ( n1274 , n354 );
buf ( n1275 , n59 );
buf ( n1276 , n265 );
buf ( n1277 , n19 );
buf ( n1278 , n377 );
buf ( n1279 , n412 );
buf ( n1280 , n231 );
buf ( n1281 , n465 );
buf ( n1282 , n250 );
buf ( n1283 , n176 );
buf ( n1284 , n299 );
buf ( n1285 , n259 );
buf ( n1286 , n169 );
buf ( n1287 , n466 );
buf ( n1288 , n31 );
buf ( n1289 , n452 );
buf ( n1290 , n145 );
buf ( n1291 , n47 );
buf ( n1292 , n444 );
buf ( n1293 , n69 );
buf ( n1294 , n5 );
buf ( n1295 , n89 );
buf ( n1296 , n197 );
buf ( n1297 , n98 );
buf ( n1298 , n453 );
buf ( n1299 , n175 );
buf ( n1300 , n217 );
buf ( n1301 , n60 );
buf ( n1302 , n204 );
buf ( n1303 , n293 );
buf ( n1304 , n457 );
buf ( n1305 , n26 );
buf ( n1306 , n306 );
buf ( n1307 , n406 );
buf ( n1308 , n497 );
buf ( n1309 , n391 );
buf ( n1310 , n1 );
buf ( n1311 , n269 );
buf ( n1312 , n44 );
buf ( n1313 , n434 );
buf ( n1314 , n30 );
buf ( n1315 , n474 );
buf ( n1316 , n190 );
buf ( n1317 , n21 );
buf ( n1318 , n72 );
buf ( n1319 , n71 );
buf ( n1320 , n267 );
buf ( n1321 , n119 );
buf ( n1322 , n266 );
buf ( n1323 , n373 );
buf ( n1324 , n487 );
buf ( n1325 , n482 );
buf ( n1326 , n91 );
buf ( n1327 , n146 );
buf ( n1328 , n124 );
buf ( n1329 , n45 );
buf ( n1330 , n329 );
buf ( n1331 , n50 );
buf ( n1332 , n294 );
buf ( n1333 , n254 );
buf ( n1334 , n76 );
buf ( n1335 , n400 );
buf ( n1336 , n261 );
buf ( n1337 , n94 );
buf ( n1338 , n420 );
buf ( n1339 , n264 );
buf ( n1340 , n70 );
buf ( n1341 , n133 );
buf ( n1342 , n199 );
buf ( n1343 , n20 );
buf ( n1344 , n290 );
buf ( n1345 , n93 );
buf ( n1346 , n202 );
buf ( n1347 , n315 );
buf ( n1348 , n468 );
buf ( n1349 , n86 );
buf ( n1350 , n268 );
buf ( n1351 , n495 );
buf ( n1352 , n182 );
buf ( n1353 , n27 );
buf ( n1354 , n220 );
buf ( n1355 , n344 );
buf ( n1356 , n240 );
buf ( n1357 , n81 );
buf ( n1358 , n232 );
buf ( n1359 , n508 );
buf ( n1360 , n2 );
buf ( n1361 , n41 );
buf ( n1362 , n186 );
buf ( n1363 , n351 );
buf ( n1364 , n179 );
buf ( n1365 , n296 );
buf ( n1366 , n243 );
buf ( n1367 , n96 );
buf ( n1368 , n35 );
buf ( n1369 , n287 );
buf ( n1370 , n29 );
buf ( n1371 , n414 );
buf ( n1372 , n415 );
buf ( n1373 , n214 );
buf ( n1374 , n284 );
buf ( n1375 , n395 );
buf ( n1376 , n201 );
buf ( n1377 , n4 );
buf ( n1378 , n333 );
buf ( n1379 , n387 );
buf ( n1380 , n237 );
buf ( n1381 , n392 );
buf ( n1382 , n416 );
buf ( n1383 , n8 );
buf ( n1384 , n188 );
buf ( n1385 , n53 );
buf ( n1386 , n478 );
buf ( n1387 , n359 );
buf ( n1388 , n171 );
buf ( n1389 , n476 );
buf ( n1390 , n163 );
buf ( n1391 , n449 );
buf ( n1392 , n191 );
buf ( n1393 , n227 );
buf ( n1394 , n492 );
buf ( n1395 , n297 );
buf ( n1396 , n245 );
buf ( n1397 , n106 );
buf ( n1398 , n365 );
buf ( n1399 , n274 );
buf ( n1400 , n316 );
buf ( n1401 , n116 );
buf ( n1402 , n157 );
buf ( n1403 , n451 );
buf ( n1404 , n376 );
buf ( n1405 , n155 );
buf ( n1406 , n364 );
buf ( n1407 , n381 );
buf ( n1408 , n426 );
buf ( n1409 , n196 );
buf ( n1410 , n384 );
buf ( n1411 , n256 );
buf ( n1412 , n260 );
buf ( n1413 , n317 );
buf ( n1414 , n270 );
buf ( n1415 , n314 );
buf ( n1416 , n311 );
buf ( n1417 , n183 );
buf ( n1418 , n39 );
buf ( n1419 , n366 );
buf ( n1420 , n212 );
buf ( n1421 , n421 );
buf ( n1422 , n427 );
buf ( n1423 , n239 );
buf ( n1424 , n11 );
buf ( n1425 , n326 );
buf ( n1426 , n369 );
buf ( n1427 , n166 );
buf ( n1428 , n403 );
buf ( n1429 , n470 );
buf ( n1430 , n205 );
buf ( n1431 , n422 );
buf ( n1432 , n174 );
buf ( n1433 , n118 );
buf ( n1434 , n198 );
buf ( n1435 , n57 );
buf ( n1436 , n7 );
buf ( n1437 , n10 );
buf ( n1438 , n251 );
buf ( n1439 , n511 );
buf ( n1440 , n247 );
buf ( n1441 , n42 );
buf ( n1442 , n36 );
buf ( n1443 , n222 );
buf ( n1444 , n367 );
buf ( n1445 , n144 );
buf ( n1446 , n137 );
buf ( n1447 , n134 );
buf ( n1448 , n396 );
buf ( n1449 , n43 );
buf ( n1450 , n321 );
buf ( n1451 , n503 );
buf ( n1452 , n66 );
buf ( n1453 , n479 );
buf ( n1454 , n242 );
buf ( n1455 , n330 );
buf ( n1456 , n107 );
buf ( n1457 , n12 );
buf ( n1458 , n305 );
buf ( n1459 , n490 );
buf ( n1460 , n423 );
buf ( n1461 , n368 );
buf ( n1462 , n117 );
buf ( n1463 , n90 );
buf ( n1464 , n370 );
buf ( n1465 , n342 );
buf ( n1466 , n16 );
buf ( n1467 , n3 );
buf ( n1468 , n109 );
buf ( n1469 , n485 );
buf ( n1470 , n341 );
buf ( n1471 , n295 );
buf ( n1472 , n442 );
buf ( n1473 , n104 );
buf ( n1474 , n473 );
buf ( n1475 , n285 );
buf ( n1476 , n200 );
buf ( n1477 , n140 );
buf ( n1478 , n63 );
buf ( n1479 , n436 );
buf ( n1480 , n438 );
buf ( n1481 , n51 );
buf ( n1482 , n181 );
buf ( n1483 , n226 );
buf ( n1484 , n173 );
buf ( n1485 , n165 );
buf ( n1486 , n263 );
buf ( n1487 , n138 );
buf ( n1488 , n456 );
buf ( n1489 , n304 );
buf ( n1490 , n433 );
buf ( n1491 , n409 );
buf ( n1492 , n218 );
buf ( n1493 , n408 );
buf ( n1494 , n13 );
buf ( n1495 , n61 );
buf ( n1496 , n79 );
buf ( n1497 , n437 );
buf ( n1498 , n234 );
buf ( n1499 , n151 );
buf ( n1500 , n229 );
buf ( n1501 , n258 );
buf ( n1502 , n440 );
buf ( n1503 , n413 );
buf ( n1504 , n383 );
buf ( n1505 , n319 );
buf ( n1506 , n301 );
buf ( n1507 , n380 );
buf ( n1508 , n374 );
buf ( n1509 , n64 );
buf ( n1510 , n424 );
buf ( n1511 , n83 );
buf ( n1512 , n488 );
buf ( n1513 , n496 );
buf ( n1514 , n141 );
buf ( n1515 , n211 );
buf ( n1516 , n15 );
buf ( n1517 , n308 );
buf ( n1518 , n172 );
buf ( n1519 , n398 );
buf ( n1520 , n167 );
buf ( n1521 , n132 );
buf ( n1522 , n253 );
buf ( n1523 , n18 );
buf ( n1524 , n322 );
buf ( n1525 , n114 );
buf ( n1526 , n48 );
buf ( n1527 , n347 );
buf ( n1528 , n154 );
buf ( n1529 , n97 );
buf ( n1530 , n385 );
buf ( n1531 , n292 );
buf ( n1532 , n279 );
buf ( n1533 , n428 );
buf ( n1534 , n445 );
buf ( n1535 , n355 );
buf ( n1536 , n113 );
buf ( n1537 , n491 );
buf ( n1538 , n207 );
buf ( n1539 , n80 );
buf ( n1540 , n504 );
buf ( n1541 , n435 );
buf ( n1542 , n469 );
buf ( n1543 , n142 );
buf ( n1544 , n407 );
buf ( n1545 , n210 );
buf ( n1546 , n257 );
buf ( n1547 , n443 );
and ( n1548 , n1039 , n1167 );
not ( n1549 , n1039 );
not ( n1550 , n1167 );
and ( n1551 , n1549 , n1550 );
nor ( n1552 , n1548 , n1551 );
and ( n1553 , n1295 , n1423 );
not ( n1554 , n1295 );
not ( n1555 , n1423 );
and ( n1556 , n1554 , n1555 );
nor ( n1557 , n1553 , n1556 );
nand ( n1558 , n1552 , n1557 );
not ( n1559 , n1558 );
nor ( n1560 , n1557 , n1552 );
or ( n1561 , n1559 , n1560 );
and ( n1562 , n1038 , n1166 );
not ( n1563 , n1038 );
not ( n1564 , n1166 );
and ( n1565 , n1563 , n1564 );
nor ( n1566 , n1562 , n1565 );
xor ( n1567 , n1294 , n1422 );
not ( n1568 , n1567 );
and ( n1569 , n1566 , n1568 );
not ( n1570 , n1566 );
and ( n1571 , n1570 , n1567 );
nor ( n1572 , n1569 , n1571 );
nand ( n1573 , n1561 , n1572 );
and ( n1574 , n1165 , n1293 );
not ( n1575 , n1165 );
not ( n1576 , n1293 );
and ( n1577 , n1575 , n1576 );
nor ( n1578 , n1574 , n1577 );
and ( n1579 , n1037 , n1421 );
not ( n1580 , n1037 );
not ( n1581 , n1421 );
and ( n1582 , n1580 , n1581 );
nor ( n1583 , n1579 , n1582 );
nand ( n1584 , n1578 , n1583 );
not ( n1585 , n1584 );
nor ( n1586 , n1583 , n1578 );
or ( n1587 , n1585 , n1586 );
and ( n1588 , n1036 , n1164 );
not ( n1589 , n1036 );
not ( n1590 , n1164 );
and ( n1591 , n1589 , n1590 );
nor ( n1592 , n1588 , n1591 );
xor ( n1593 , n1292 , n1420 );
not ( n1594 , n1593 );
and ( n1595 , n1592 , n1594 );
not ( n1596 , n1592 );
and ( n1597 , n1596 , n1593 );
nor ( n1598 , n1595 , n1597 );
nand ( n1599 , n1587 , n1598 );
nor ( n1600 , n1573 , n1599 );
and ( n1601 , n1299 , n1427 );
not ( n1602 , n1299 );
not ( n1603 , n1427 );
and ( n1604 , n1602 , n1603 );
nor ( n1605 , n1601 , n1604 );
not ( n1606 , n1043 );
and ( n1607 , n1171 , n1606 );
not ( n1608 , n1171 );
and ( n1609 , n1608 , n1043 );
nor ( n1610 , n1607 , n1609 );
and ( n1611 , n1605 , n1610 );
not ( n1612 , n1605 );
not ( n1613 , n1610 );
and ( n1614 , n1612 , n1613 );
nor ( n1615 , n1611 , n1614 );
and ( n1616 , n1042 , n1170 );
not ( n1617 , n1042 );
not ( n1618 , n1170 );
and ( n1619 , n1617 , n1618 );
nor ( n1620 , n1616 , n1619 );
not ( n1621 , n1620 );
and ( n1622 , n1298 , n1426 );
not ( n1623 , n1298 );
not ( n1624 , n1426 );
and ( n1625 , n1623 , n1624 );
nor ( n1626 , n1622 , n1625 );
not ( n1627 , n1626 );
or ( n1628 , n1621 , n1627 );
or ( n1629 , n1620 , n1626 );
nand ( n1630 , n1628 , n1629 );
nand ( n1631 , n1615 , n1630 );
and ( n1632 , n1040 , n1168 );
not ( n1633 , n1040 );
not ( n1634 , n1168 );
and ( n1635 , n1633 , n1634 );
nor ( n1636 , n1632 , n1635 );
and ( n1637 , n1296 , n1424 );
not ( n1638 , n1296 );
not ( n1639 , n1424 );
and ( n1640 , n1638 , n1639 );
nor ( n1641 , n1637 , n1640 );
not ( n1642 , n1641 );
and ( n1643 , n1636 , n1642 );
not ( n1644 , n1636 );
and ( n1645 , n1644 , n1641 );
nor ( n1646 , n1643 , n1645 );
and ( n1647 , n1169 , n1297 );
not ( n1648 , n1169 );
not ( n1649 , n1297 );
and ( n1650 , n1648 , n1649 );
nor ( n1651 , n1647 , n1650 );
and ( n1652 , n1041 , n1425 );
not ( n1653 , n1041 );
not ( n1654 , n1425 );
and ( n1655 , n1653 , n1654 );
nor ( n1656 , n1652 , n1655 );
not ( n1657 , n1656 );
and ( n1658 , n1651 , n1657 );
not ( n1659 , n1651 );
and ( n1660 , n1659 , n1656 );
nor ( n1661 , n1658 , n1660 );
nand ( n1662 , n1646 , n1661 );
nor ( n1663 , n1631 , n1662 );
nand ( n1664 , n1600 , n1663 );
and ( n1665 , n1175 , n1303 );
not ( n1666 , n1175 );
not ( n1667 , n1303 );
and ( n1668 , n1666 , n1667 );
nor ( n1669 , n1665 , n1668 );
and ( n1670 , n1047 , n1431 );
not ( n1671 , n1047 );
not ( n1672 , n1431 );
and ( n1673 , n1671 , n1672 );
nor ( n1674 , n1670 , n1673 );
nand ( n1675 , n1669 , n1674 );
not ( n1676 , n1675 );
nor ( n1677 , n1674 , n1669 );
or ( n1678 , n1676 , n1677 );
and ( n1679 , n1046 , n1174 );
not ( n1680 , n1046 );
not ( n1681 , n1174 );
and ( n1682 , n1680 , n1681 );
nor ( n1683 , n1679 , n1682 );
xor ( n1684 , n1302 , n1430 );
not ( n1685 , n1684 );
and ( n1686 , n1683 , n1685 );
not ( n1687 , n1683 );
and ( n1688 , n1687 , n1684 );
nor ( n1689 , n1686 , n1688 );
nand ( n1690 , n1678 , n1689 );
and ( n1691 , n1045 , n1173 );
not ( n1692 , n1045 );
not ( n1693 , n1173 );
and ( n1694 , n1692 , n1693 );
nor ( n1695 , n1691 , n1694 );
and ( n1696 , n1301 , n1429 );
not ( n1697 , n1301 );
not ( n1698 , n1429 );
and ( n1699 , n1697 , n1698 );
nor ( n1700 , n1696 , n1699 );
nand ( n1701 , n1695 , n1700 );
not ( n1702 , n1701 );
not ( n1703 , n1700 );
and ( n1704 , n1045 , n1173 );
not ( n1705 , n1045 );
and ( n1706 , n1705 , n1693 );
nor ( n1707 , n1704 , n1706 );
not ( n1708 , n1707 );
nand ( n1709 , n1703 , n1708 );
not ( n1710 , n1709 );
or ( n1711 , n1702 , n1710 );
not ( n1712 , n1428 );
nand ( n1713 , n1712 , n1044 );
not ( n1714 , n1044 );
nand ( n1715 , n1714 , n1428 );
nand ( n1716 , n1713 , n1715 );
and ( n1717 , n1172 , n1300 );
not ( n1718 , n1172 );
not ( n1719 , n1300 );
and ( n1720 , n1718 , n1719 );
nor ( n1721 , n1717 , n1720 );
or ( n1722 , n1716 , n1721 );
nand ( n1723 , n1714 , n1428 );
not ( n1724 , n1723 );
not ( n1725 , n1713 );
or ( n1726 , n1724 , n1725 );
nand ( n1727 , n1726 , n1721 );
nand ( n1728 , n1722 , n1727 );
nand ( n1729 , n1711 , n1728 );
nor ( n1730 , n1690 , n1729 );
and ( n1731 , n1178 , n1306 );
not ( n1732 , n1178 );
not ( n1733 , n1306 );
and ( n1734 , n1732 , n1733 );
nor ( n1735 , n1731 , n1734 );
and ( n1736 , n1050 , n1434 );
not ( n1737 , n1050 );
not ( n1738 , n1434 );
and ( n1739 , n1737 , n1738 );
nor ( n1740 , n1736 , n1739 );
not ( n1741 , n1740 );
and ( n1742 , n1735 , n1741 );
not ( n1743 , n1735 );
and ( n1744 , n1743 , n1740 );
nor ( n1745 , n1742 , n1744 );
and ( n1746 , n1051 , n1179 );
not ( n1747 , n1051 );
not ( n1748 , n1179 );
and ( n1749 , n1747 , n1748 );
nor ( n1750 , n1746 , n1749 );
and ( n1751 , n1307 , n1435 );
not ( n1752 , n1307 );
not ( n1753 , n1435 );
and ( n1754 , n1752 , n1753 );
nor ( n1755 , n1751 , n1754 );
not ( n1756 , n1755 );
and ( n1757 , n1750 , n1756 );
not ( n1758 , n1750 );
and ( n1759 , n1758 , n1755 );
nor ( n1760 , n1757 , n1759 );
nand ( n1761 , n1745 , n1760 );
not ( n1762 , n1432 );
not ( n1763 , n1304 );
and ( n1764 , n1762 , n1763 );
and ( n1765 , n1304 , n1432 );
nor ( n1766 , n1764 , n1765 );
and ( n1767 , n1048 , n1176 );
not ( n1768 , n1048 );
not ( n1769 , n1176 );
and ( n1770 , n1768 , n1769 );
nor ( n1771 , n1767 , n1770 );
or ( n1772 , n1766 , n1771 );
and ( n1773 , n1304 , n1432 );
not ( n1774 , n1304 );
and ( n1775 , n1774 , n1762 );
nor ( n1776 , n1773 , n1775 );
nand ( n1777 , n1776 , n1771 );
nand ( n1778 , n1772 , n1777 );
and ( n1779 , n1305 , n1433 );
not ( n1780 , n1305 );
not ( n1781 , n1433 );
and ( n1782 , n1780 , n1781 );
nor ( n1783 , n1779 , n1782 );
and ( n1784 , n1049 , n1177 );
not ( n1785 , n1049 );
not ( n1786 , n1177 );
and ( n1787 , n1785 , n1786 );
nor ( n1788 , n1784 , n1787 );
not ( n1789 , n1788 );
and ( n1790 , n1783 , n1789 );
not ( n1791 , n1783 );
and ( n1792 , n1791 , n1788 );
nor ( n1793 , n1790 , n1792 );
nand ( n1794 , n1778 , n1793 );
nor ( n1795 , n1761 , n1794 );
nand ( n1796 , n1730 , n1795 );
nor ( n1797 , n1664 , n1796 );
and ( n1798 , n1311 , n1439 );
not ( n1799 , n1311 );
not ( n1800 , n1439 );
and ( n1801 , n1799 , n1800 );
nor ( n1802 , n1798 , n1801 );
not ( n1803 , n1802 );
and ( n1804 , n1055 , n1183 );
not ( n1805 , n1055 );
not ( n1806 , n1183 );
and ( n1807 , n1805 , n1806 );
nor ( n1808 , n1804 , n1807 );
not ( n1809 , n1808 );
or ( n1810 , n1803 , n1809 );
or ( n1811 , n1808 , n1802 );
nand ( n1812 , n1810 , n1811 );
not ( n1813 , n1054 );
and ( n1814 , n1438 , n1813 );
not ( n1815 , n1438 );
and ( n1816 , n1815 , n1054 );
nor ( n1817 , n1814 , n1816 );
and ( n1818 , n1182 , n1310 );
not ( n1819 , n1182 );
not ( n1820 , n1310 );
and ( n1821 , n1819 , n1820 );
nor ( n1822 , n1818 , n1821 );
and ( n1823 , n1817 , n1822 );
not ( n1824 , n1817 );
not ( n1825 , n1822 );
and ( n1826 , n1824 , n1825 );
nor ( n1827 , n1823 , n1826 );
nand ( n1828 , n1812 , n1827 );
and ( n1829 , n1181 , n1309 );
not ( n1830 , n1181 );
not ( n1831 , n1309 );
and ( n1832 , n1830 , n1831 );
nor ( n1833 , n1829 , n1832 );
and ( n1834 , n1053 , n1437 );
not ( n1835 , n1053 );
not ( n1836 , n1437 );
and ( n1837 , n1835 , n1836 );
nor ( n1838 , n1834 , n1837 );
not ( n1839 , n1838 );
and ( n1840 , n1833 , n1839 );
not ( n1841 , n1833 );
and ( n1842 , n1841 , n1838 );
nor ( n1843 , n1840 , n1842 );
and ( n1844 , n1052 , n1180 );
not ( n1845 , n1052 );
not ( n1846 , n1180 );
and ( n1847 , n1845 , n1846 );
nor ( n1848 , n1844 , n1847 );
xor ( n1849 , n1308 , n1436 );
not ( n1850 , n1849 );
and ( n1851 , n1848 , n1850 );
not ( n1852 , n1848 );
and ( n1853 , n1852 , n1849 );
nor ( n1854 , n1851 , n1853 );
nand ( n1855 , n1843 , n1854 );
nor ( n1856 , n1828 , n1855 );
and ( n1857 , n1313 , n1441 );
not ( n1858 , n1313 );
not ( n1859 , n1441 );
and ( n1860 , n1858 , n1859 );
nor ( n1861 , n1857 , n1860 );
and ( n1862 , n1057 , n1185 );
not ( n1863 , n1057 );
not ( n1864 , n1185 );
and ( n1865 , n1863 , n1864 );
nor ( n1866 , n1862 , n1865 );
nand ( n1867 , n1861 , n1866 );
not ( n1868 , n1867 );
nor ( n1869 , n1861 , n1866 );
or ( n1870 , n1868 , n1869 );
and ( n1871 , n1184 , n1312 );
not ( n1872 , n1184 );
not ( n1873 , n1312 );
and ( n1874 , n1872 , n1873 );
nor ( n1875 , n1871 , n1874 );
xor ( n1876 , n1056 , n1440 );
not ( n1877 , n1876 );
and ( n1878 , n1875 , n1877 );
not ( n1879 , n1875 );
and ( n1880 , n1879 , n1876 );
nor ( n1881 , n1878 , n1880 );
nand ( n1882 , n1870 , n1881 );
and ( n1883 , n1059 , n1187 );
not ( n1884 , n1059 );
not ( n1885 , n1187 );
and ( n1886 , n1884 , n1885 );
nor ( n1887 , n1883 , n1886 );
and ( n1888 , n1315 , n1443 );
not ( n1889 , n1315 );
not ( n1890 , n1443 );
and ( n1891 , n1889 , n1890 );
nor ( n1892 , n1888 , n1891 );
not ( n1893 , n1892 );
and ( n1894 , n1887 , n1893 );
not ( n1895 , n1887 );
and ( n1896 , n1895 , n1892 );
nor ( n1897 , n1894 , n1896 );
and ( n1898 , n1186 , n1314 );
not ( n1899 , n1186 );
not ( n1900 , n1314 );
and ( n1901 , n1899 , n1900 );
nor ( n1902 , n1898 , n1901 );
xor ( n1903 , n1058 , n1442 );
not ( n1904 , n1903 );
and ( n1905 , n1902 , n1904 );
not ( n1906 , n1902 );
and ( n1907 , n1906 , n1903 );
nor ( n1908 , n1905 , n1907 );
nand ( n1909 , n1897 , n1908 );
nor ( n1910 , n1882 , n1909 );
nand ( n1911 , n1856 , n1910 );
and ( n1912 , n1195 , n1323 );
not ( n1913 , n1195 );
not ( n1914 , n1323 );
and ( n1915 , n1913 , n1914 );
nor ( n1916 , n1912 , n1915 );
and ( n1917 , n1067 , n1451 );
not ( n1918 , n1067 );
not ( n1919 , n1451 );
and ( n1920 , n1918 , n1919 );
nor ( n1921 , n1917 , n1920 );
nand ( n1922 , n1916 , n1921 );
not ( n1923 , n1922 );
nor ( n1924 , n1921 , n1916 );
or ( n1925 , n1923 , n1924 );
and ( n1926 , n1066 , n1194 );
not ( n1927 , n1066 );
not ( n1928 , n1194 );
and ( n1929 , n1927 , n1928 );
nor ( n1930 , n1926 , n1929 );
xor ( n1931 , n1322 , n1450 );
not ( n1932 , n1931 );
and ( n1933 , n1930 , n1932 );
not ( n1934 , n1930 );
and ( n1935 , n1934 , n1931 );
nor ( n1936 , n1933 , n1935 );
nand ( n1937 , n1925 , n1936 );
and ( n1938 , n1193 , n1321 );
not ( n1939 , n1193 );
not ( n1940 , n1321 );
and ( n1941 , n1939 , n1940 );
nor ( n1942 , n1938 , n1941 );
and ( n1943 , n1065 , n1449 );
not ( n1944 , n1065 );
not ( n1945 , n1449 );
and ( n1946 , n1944 , n1945 );
nor ( n1947 , n1943 , n1946 );
nand ( n1948 , n1942 , n1947 );
not ( n1949 , n1948 );
not ( n1950 , n1947 );
and ( n1951 , n1193 , n1321 );
not ( n1952 , n1193 );
and ( n1953 , n1952 , n1940 );
nor ( n1954 , n1951 , n1953 );
not ( n1955 , n1954 );
nand ( n1956 , n1950 , n1955 );
not ( n1957 , n1956 );
or ( n1958 , n1949 , n1957 );
not ( n1959 , n1448 );
nand ( n1960 , n1959 , n1320 );
not ( n1961 , n1320 );
nand ( n1962 , n1961 , n1448 );
nand ( n1963 , n1960 , n1962 );
and ( n1964 , n1064 , n1192 );
not ( n1965 , n1064 );
not ( n1966 , n1192 );
and ( n1967 , n1965 , n1966 );
nor ( n1968 , n1964 , n1967 );
or ( n1969 , n1963 , n1968 );
nand ( n1970 , n1961 , n1448 );
not ( n1971 , n1970 );
not ( n1972 , n1960 );
or ( n1973 , n1971 , n1972 );
nand ( n1974 , n1973 , n1968 );
nand ( n1975 , n1969 , n1974 );
nand ( n1976 , n1958 , n1975 );
nor ( n1977 , n1937 , n1976 );
and ( n1978 , n1191 , n1319 );
not ( n1979 , n1191 );
not ( n1980 , n1319 );
and ( n1981 , n1979 , n1980 );
nor ( n1982 , n1978 , n1981 );
and ( n1983 , n1063 , n1447 );
not ( n1984 , n1063 );
not ( n1985 , n1447 );
and ( n1986 , n1984 , n1985 );
nor ( n1987 , n1983 , n1986 );
not ( n1988 , n1987 );
and ( n1989 , n1982 , n1988 );
not ( n1990 , n1982 );
and ( n1991 , n1990 , n1987 );
nor ( n1992 , n1989 , n1991 );
xor ( n1993 , n1062 , n1446 );
xnor ( n1994 , n1190 , n1318 );
and ( n1995 , n1993 , n1994 );
not ( n1996 , n1993 );
xor ( n1997 , n1190 , n1318 );
and ( n1998 , n1996 , n1997 );
nor ( n1999 , n1995 , n1998 );
nand ( n2000 , n1992 , n1999 );
and ( n2001 , n1189 , n1317 );
not ( n2002 , n1189 );
not ( n2003 , n1317 );
and ( n2004 , n2002 , n2003 );
nor ( n2005 , n2001 , n2004 );
not ( n2006 , n1061 );
not ( n2007 , n1445 );
not ( n2008 , n2007 );
or ( n2009 , n2006 , n2008 );
not ( n2010 , n1061 );
nand ( n2011 , n2010 , n1445 );
nand ( n2012 , n2009 , n2011 );
or ( n2013 , n2005 , n2012 );
nand ( n2014 , n2007 , n1061 );
not ( n2015 , n2014 );
not ( n2016 , n2011 );
or ( n2017 , n2015 , n2016 );
and ( n2018 , n1189 , n1317 );
not ( n2019 , n1189 );
and ( n2020 , n2019 , n2003 );
nor ( n2021 , n2018 , n2020 );
nand ( n2022 , n2017 , n2021 );
nand ( n2023 , n2013 , n2022 );
not ( n2024 , n1444 );
and ( n2025 , n1316 , n2024 );
not ( n2026 , n1316 );
and ( n2027 , n2026 , n1444 );
nor ( n2028 , n2025 , n2027 );
and ( n2029 , n1060 , n1188 );
not ( n2030 , n1060 );
not ( n2031 , n1188 );
and ( n2032 , n2030 , n2031 );
nor ( n2033 , n2029 , n2032 );
and ( n2034 , n2028 , n2033 );
not ( n2035 , n2028 );
not ( n2036 , n1060 );
nand ( n2037 , n2036 , n2031 );
nand ( n2038 , n1188 , n1060 );
nand ( n2039 , n2037 , n2038 );
and ( n2040 , n2035 , n2039 );
nor ( n2041 , n2034 , n2040 );
nand ( n2042 , n2023 , n2041 );
nor ( n2043 , n2000 , n2042 );
nand ( n2044 , n1977 , n2043 );
nor ( n2045 , n1911 , n2044 );
nand ( n2046 , n1797 , n2045 );
and ( n2047 , n1202 , n1330 );
not ( n2048 , n1202 );
not ( n2049 , n1330 );
and ( n2050 , n2048 , n2049 );
nor ( n2051 , n2047 , n2050 );
and ( n2052 , n1074 , n1458 );
not ( n2053 , n1074 );
not ( n2054 , n1458 );
and ( n2055 , n2053 , n2054 );
nor ( n2056 , n2052 , n2055 );
not ( n2057 , n2056 );
and ( n2058 , n2051 , n2057 );
not ( n2059 , n2051 );
and ( n2060 , n2059 , n2056 );
nor ( n2061 , n2058 , n2060 );
and ( n2062 , n1203 , n1331 );
not ( n2063 , n1203 );
not ( n2064 , n1331 );
and ( n2065 , n2063 , n2064 );
nor ( n2066 , n2062 , n2065 );
and ( n2067 , n1075 , n1459 );
not ( n2068 , n1075 );
not ( n2069 , n1459 );
and ( n2070 , n2068 , n2069 );
nor ( n2071 , n2067 , n2070 );
not ( n2072 , n2071 );
and ( n2073 , n2066 , n2072 );
not ( n2074 , n2066 );
and ( n2075 , n2074 , n2071 );
nor ( n2076 , n2073 , n2075 );
nand ( n2077 , n2061 , n2076 );
not ( n2078 , n1072 );
and ( n2079 , n1456 , n2078 );
not ( n2080 , n1456 );
and ( n2081 , n2080 , n1072 );
nor ( n2082 , n2079 , n2081 );
and ( n2083 , n1200 , n1328 );
not ( n2084 , n1200 );
not ( n2085 , n1328 );
and ( n2086 , n2084 , n2085 );
nor ( n2087 , n2083 , n2086 );
and ( n2088 , n2082 , n2087 );
not ( n2089 , n2082 );
not ( n2090 , n2087 );
and ( n2091 , n2089 , n2090 );
nor ( n2092 , n2088 , n2091 );
and ( n2093 , n1073 , n1457 );
not ( n2094 , n1073 );
not ( n2095 , n1457 );
and ( n2096 , n2094 , n2095 );
nor ( n2097 , n2093 , n2096 );
and ( n2098 , n1201 , n1329 );
not ( n2099 , n1201 );
not ( n2100 , n1329 );
and ( n2101 , n2099 , n2100 );
nor ( n2102 , n2098 , n2101 );
not ( n2103 , n2102 );
and ( n2104 , n2097 , n2103 );
not ( n2105 , n2097 );
and ( n2106 , n2105 , n2102 );
nor ( n2107 , n2104 , n2106 );
nand ( n2108 , n2092 , n2107 );
nor ( n2109 , n2077 , n2108 );
and ( n2110 , n1071 , n1455 );
not ( n2111 , n1071 );
not ( n2112 , n1455 );
and ( n2113 , n2111 , n2112 );
nor ( n2114 , n2110 , n2113 );
and ( n2115 , n1199 , n1327 );
not ( n2116 , n1199 );
not ( n2117 , n1327 );
and ( n2118 , n2116 , n2117 );
nor ( n2119 , n2115 , n2118 );
not ( n2120 , n2119 );
and ( n2121 , n2114 , n2120 );
not ( n2122 , n2114 );
and ( n2123 , n2122 , n2119 );
nor ( n2124 , n2121 , n2123 );
and ( n2125 , n1198 , n1326 );
not ( n2126 , n1198 );
not ( n2127 , n1326 );
and ( n2128 , n2126 , n2127 );
nor ( n2129 , n2125 , n2128 );
xor ( n2130 , n1070 , n1454 );
not ( n2131 , n2130 );
and ( n2132 , n2129 , n2131 );
not ( n2133 , n2129 );
and ( n2134 , n2133 , n2130 );
nor ( n2135 , n2132 , n2134 );
nand ( n2136 , n2124 , n2135 );
and ( n2137 , n1453 , n1325 );
not ( n2138 , n1453 );
not ( n2139 , n1325 );
and ( n2140 , n2138 , n2139 );
nor ( n2141 , n2137 , n2140 );
and ( n2142 , n1069 , n1197 );
not ( n2143 , n1069 );
not ( n2144 , n1197 );
and ( n2145 , n2143 , n2144 );
nor ( n2146 , n2142 , n2145 );
nand ( n2147 , n2141 , n2146 );
not ( n2148 , n2147 );
not ( n2149 , n2141 );
not ( n2150 , n2144 );
not ( n2151 , n1069 );
and ( n2152 , n2150 , n2151 );
and ( n2153 , n2144 , n1069 );
nor ( n2154 , n2152 , n2153 );
nand ( n2155 , n2149 , n2154 );
not ( n2156 , n2155 );
or ( n2157 , n2148 , n2156 );
not ( n2158 , n1324 );
not ( n2159 , n1452 );
not ( n2160 , n2159 );
or ( n2161 , n2158 , n2160 );
not ( n2162 , n1324 );
nand ( n2163 , n2162 , n1452 );
nand ( n2164 , n2161 , n2163 );
and ( n2165 , n1068 , n1196 );
not ( n2166 , n1068 );
not ( n2167 , n1196 );
and ( n2168 , n2166 , n2167 );
nor ( n2169 , n2165 , n2168 );
or ( n2170 , n2164 , n2169 );
not ( n2171 , n1324 );
not ( n2172 , n2159 );
or ( n2173 , n2171 , n2172 );
nand ( n2174 , n2173 , n2163 );
nand ( n2175 , n2174 , n2169 );
nand ( n2176 , n2170 , n2175 );
nand ( n2177 , n2157 , n2176 );
nor ( n2178 , n2136 , n2177 );
nand ( n2179 , n2109 , n2178 );
and ( n2180 , n1094 , n1222 );
not ( n2181 , n1094 );
not ( n2182 , n1222 );
and ( n2183 , n2181 , n2182 );
nor ( n2184 , n2180 , n2183 );
not ( n2185 , n1350 );
not ( n2186 , n2185 );
not ( n2187 , n1478 );
or ( n2188 , n2186 , n2187 );
not ( n2189 , n1478 );
nand ( n2190 , n2189 , n1350 );
nand ( n2191 , n2188 , n2190 );
or ( n2192 , n2184 , n2191 );
nand ( n2193 , n2185 , n1478 );
not ( n2194 , n2193 );
not ( n2195 , n2190 );
or ( n2196 , n2194 , n2195 );
and ( n2197 , n1094 , n1222 );
not ( n2198 , n1094 );
and ( n2199 , n2198 , n2182 );
nor ( n2200 , n2197 , n2199 );
nand ( n2201 , n2196 , n2200 );
nand ( n2202 , n2192 , n2201 );
and ( n2203 , n1095 , n1223 );
not ( n2204 , n1095 );
not ( n2205 , n1223 );
and ( n2206 , n2204 , n2205 );
nor ( n2207 , n2203 , n2206 );
not ( n2208 , n1479 );
and ( n2209 , n2208 , n1351 );
not ( n2210 , n1351 );
and ( n2211 , n2210 , n1479 );
nor ( n2212 , n2209 , n2211 );
and ( n2213 , n2207 , n2212 );
not ( n2214 , n2207 );
not ( n2215 , n1351 );
not ( n2216 , n2208 );
or ( n2217 , n2215 , n2216 );
nand ( n2218 , n2210 , n1479 );
nand ( n2219 , n2217 , n2218 );
and ( n2220 , n2214 , n2219 );
nor ( n2221 , n2213 , n2220 );
nand ( n2222 , n2202 , n2221 );
and ( n2223 , n1092 , n1220 );
not ( n2224 , n1092 );
not ( n2225 , n1220 );
and ( n2226 , n2224 , n2225 );
nor ( n2227 , n2223 , n2226 );
not ( n2228 , n1348 );
and ( n2229 , n2228 , n1476 );
not ( n2230 , n1476 );
and ( n2231 , n2230 , n1348 );
nor ( n2232 , n2229 , n2231 );
and ( n2233 , n2227 , n2232 );
not ( n2234 , n2227 );
not ( n2235 , n2228 );
not ( n2236 , n1476 );
or ( n2237 , n2235 , n2236 );
nand ( n2238 , n2230 , n1348 );
nand ( n2239 , n2237 , n2238 );
and ( n2240 , n2234 , n2239 );
nor ( n2241 , n2233 , n2240 );
and ( n2242 , n1349 , n1477 );
not ( n2243 , n1349 );
not ( n2244 , n1477 );
and ( n2245 , n2243 , n2244 );
nor ( n2246 , n2242 , n2245 );
xnor ( n2247 , n1221 , n1093 );
and ( n2248 , n2246 , n2247 );
not ( n2249 , n2246 );
xor ( n2250 , n1093 , n1221 );
and ( n2251 , n2249 , n2250 );
nor ( n2252 , n2248 , n2251 );
nand ( n2253 , n2241 , n2252 );
nor ( n2254 , n2222 , n2253 );
and ( n2255 , n1227 , n1355 );
not ( n2256 , n1227 );
not ( n2257 , n1355 );
and ( n2258 , n2256 , n2257 );
nor ( n2259 , n2255 , n2258 );
and ( n2260 , n1099 , n1483 );
not ( n2261 , n1099 );
not ( n2262 , n1483 );
and ( n2263 , n2261 , n2262 );
nor ( n2264 , n2260 , n2263 );
nand ( n2265 , n2259 , n2264 );
not ( n2266 , n2265 );
not ( n2267 , n2264 );
and ( n2268 , n1227 , n1355 );
not ( n2269 , n1227 );
and ( n2270 , n2269 , n2257 );
nor ( n2271 , n2268 , n2270 );
not ( n2272 , n2271 );
nand ( n2273 , n2267 , n2272 );
not ( n2274 , n2273 );
or ( n2275 , n2266 , n2274 );
not ( n2276 , n1354 );
not ( n2277 , n1482 );
not ( n2278 , n2277 );
or ( n2279 , n2276 , n2278 );
not ( n2280 , n1354 );
nand ( n2281 , n2280 , n1482 );
nand ( n2282 , n2279 , n2281 );
and ( n2283 , n1098 , n1226 );
not ( n2284 , n1098 );
not ( n2285 , n1226 );
and ( n2286 , n2284 , n2285 );
nor ( n2287 , n2283 , n2286 );
or ( n2288 , n2282 , n2287 );
not ( n2289 , n1354 );
not ( n2290 , n2277 );
or ( n2291 , n2289 , n2290 );
nand ( n2292 , n2291 , n2281 );
nand ( n2293 , n2292 , n2287 );
nand ( n2294 , n2288 , n2293 );
nand ( n2295 , n2275 , n2294 );
xor ( n2296 , n1481 , n1353 );
and ( n2297 , n1097 , n1225 );
not ( n2298 , n1097 );
not ( n2299 , n1225 );
and ( n2300 , n2298 , n2299 );
nor ( n2301 , n2297 , n2300 );
nand ( n2302 , n2296 , n2301 );
not ( n2303 , n2302 );
xnor ( n2304 , n1353 , n1481 );
not ( n2305 , n2299 );
not ( n2306 , n1097 );
and ( n2307 , n2305 , n2306 );
not ( n2308 , n1225 );
and ( n2309 , n2308 , n1097 );
nor ( n2310 , n2307 , n2309 );
nand ( n2311 , n2304 , n2310 );
not ( n2312 , n2311 );
or ( n2313 , n2303 , n2312 );
xor ( n2314 , n1096 , n1224 );
xor ( n2315 , n1352 , n1480 );
or ( n2316 , n2314 , n2315 );
xor ( n2317 , n1352 , n1480 );
xor ( n2318 , n1096 , n1224 );
nand ( n2319 , n2317 , n2318 );
nand ( n2320 , n2316 , n2319 );
nand ( n2321 , n2313 , n2320 );
nor ( n2322 , n2295 , n2321 );
nand ( n2323 , n2254 , n2322 );
nor ( n2324 , n2179 , n2323 );
and ( n2325 , n1344 , n1472 );
not ( n2326 , n1344 );
not ( n2327 , n1472 );
and ( n2328 , n2326 , n2327 );
nor ( n2329 , n2325 , n2328 );
not ( n2330 , n2329 );
and ( n2331 , n1088 , n1216 );
not ( n2332 , n1088 );
not ( n2333 , n1216 );
and ( n2334 , n2332 , n2333 );
nor ( n2335 , n2331 , n2334 );
not ( n2336 , n2335 );
or ( n2337 , n2330 , n2336 );
and ( n2338 , n1088 , n1216 );
not ( n2339 , n1088 );
and ( n2340 , n2339 , n2333 );
nor ( n2341 , n2338 , n2340 );
or ( n2342 , n2341 , n2329 );
nand ( n2343 , n2337 , n2342 );
not ( n2344 , n1089 );
and ( n2345 , n1217 , n2344 );
not ( n2346 , n1217 );
and ( n2347 , n2346 , n1089 );
nor ( n2348 , n2345 , n2347 );
and ( n2349 , n1345 , n1473 );
not ( n2350 , n1345 );
not ( n2351 , n1473 );
and ( n2352 , n2350 , n2351 );
nor ( n2353 , n2349 , n2352 );
and ( n2354 , n2348 , n2353 );
not ( n2355 , n2348 );
not ( n2356 , n2353 );
and ( n2357 , n2355 , n2356 );
nor ( n2358 , n2354 , n2357 );
nand ( n2359 , n2343 , n2358 );
not ( n2360 , n1347 );
and ( n2361 , n1475 , n2360 );
not ( n2362 , n1475 );
and ( n2363 , n2362 , n1347 );
nor ( n2364 , n2361 , n2363 );
and ( n2365 , n1091 , n1219 );
not ( n2366 , n1091 );
not ( n2367 , n1219 );
and ( n2368 , n2366 , n2367 );
nor ( n2369 , n2365 , n2368 );
and ( n2370 , n2364 , n2369 );
not ( n2371 , n2364 );
not ( n2372 , n2369 );
and ( n2373 , n2371 , n2372 );
nor ( n2374 , n2370 , n2373 );
and ( n2375 , n1218 , n1346 );
not ( n2376 , n1218 );
not ( n2377 , n1346 );
and ( n2378 , n2376 , n2377 );
nor ( n2379 , n2375 , n2378 );
xor ( n2380 , n1090 , n1474 );
not ( n2381 , n2380 );
and ( n2382 , n2379 , n2381 );
not ( n2383 , n2379 );
and ( n2384 , n2383 , n2380 );
nor ( n2385 , n2382 , n2384 );
nand ( n2386 , n2374 , n2385 );
nor ( n2387 , n2359 , n2386 );
and ( n2388 , n1087 , n1215 );
not ( n2389 , n1087 );
not ( n2390 , n1215 );
and ( n2391 , n2389 , n2390 );
nor ( n2392 , n2388 , n2391 );
not ( n2393 , n2392 );
xor ( n2394 , n1343 , n1471 );
not ( n2395 , n2394 );
or ( n2396 , n2393 , n2395 );
or ( n2397 , n2394 , n2392 );
nand ( n2398 , n2396 , n2397 );
xor ( n2399 , n1342 , n1470 );
xnor ( n2400 , n1086 , n1214 );
and ( n2401 , n2399 , n2400 );
not ( n2402 , n2399 );
xor ( n2403 , n1086 , n1214 );
and ( n2404 , n2402 , n2403 );
nor ( n2405 , n2401 , n2404 );
nand ( n2406 , n2398 , n2405 );
xor ( n2407 , n1212 , n1340 );
not ( n2408 , n1084 );
nand ( n2409 , n2408 , n1468 );
not ( n2410 , n1468 );
nand ( n2411 , n2410 , n1084 );
nand ( n2412 , n2409 , n2411 );
or ( n2413 , n2407 , n2412 );
not ( n2414 , n2411 );
not ( n2415 , n2409 );
or ( n2416 , n2414 , n2415 );
xor ( n2417 , n1212 , n1340 );
nand ( n2418 , n2416 , n2417 );
nand ( n2419 , n2413 , n2418 );
not ( n2420 , n1085 );
not ( n2421 , n1469 );
not ( n2422 , n2421 );
or ( n2423 , n2420 , n2422 );
not ( n2424 , n1085 );
nand ( n2425 , n2424 , n1469 );
nand ( n2426 , n2423 , n2425 );
not ( n2427 , n1213 );
or ( n2428 , n2427 , n1341 );
not ( n2429 , n1341 );
or ( n2430 , n2429 , n1213 );
nand ( n2431 , n2428 , n2430 );
or ( n2432 , n2426 , n2431 );
nand ( n2433 , n2421 , n1085 );
not ( n2434 , n2433 );
not ( n2435 , n2425 );
or ( n2436 , n2434 , n2435 );
xor ( n2437 , n1341 , n1213 );
nand ( n2438 , n2436 , n2437 );
nand ( n2439 , n2432 , n2438 );
nand ( n2440 , n2419 , n2439 );
nor ( n2441 , n2406 , n2440 );
nand ( n2442 , n2387 , n2441 );
xor ( n2443 , n1207 , n1079 );
and ( n2444 , n1335 , n1463 );
not ( n2445 , n1335 );
not ( n2446 , n1463 );
and ( n2447 , n2445 , n2446 );
nor ( n2448 , n2444 , n2447 );
nand ( n2449 , n2443 , n2448 );
not ( n2450 , n2449 );
not ( n2451 , n2448 );
xnor ( n2452 , n1079 , n1207 );
nand ( n2453 , n2451 , n2452 );
not ( n2454 , n2453 );
or ( n2455 , n2450 , n2454 );
not ( n2456 , n1078 );
not ( n2457 , n1462 );
not ( n2458 , n2457 );
or ( n2459 , n2456 , n2458 );
not ( n2460 , n1078 );
nand ( n2461 , n2460 , n1462 );
nand ( n2462 , n2459 , n2461 );
and ( n2463 , n1206 , n1334 );
not ( n2464 , n1206 );
not ( n2465 , n1334 );
and ( n2466 , n2464 , n2465 );
nor ( n2467 , n2463 , n2466 );
or ( n2468 , n2462 , n2467 );
not ( n2469 , n1078 );
not ( n2470 , n2457 );
or ( n2471 , n2469 , n2470 );
nand ( n2472 , n2471 , n2461 );
nand ( n2473 , n2472 , n2467 );
nand ( n2474 , n2468 , n2473 );
nand ( n2475 , n2455 , n2474 );
and ( n2476 , n1205 , n1333 );
not ( n2477 , n1205 );
not ( n2478 , n1333 );
and ( n2479 , n2477 , n2478 );
nor ( n2480 , n2476 , n2479 );
and ( n2481 , n1077 , n1461 );
not ( n2482 , n1077 );
not ( n2483 , n1461 );
and ( n2484 , n2482 , n2483 );
nor ( n2485 , n2481 , n2484 );
nand ( n2486 , n2480 , n2485 );
not ( n2487 , n2486 );
xnor ( n2488 , n1461 , n1077 );
and ( n2489 , n1333 , n1205 );
not ( n2490 , n1333 );
not ( n2491 , n1205 );
and ( n2492 , n2490 , n2491 );
nor ( n2493 , n2489 , n2492 );
not ( n2494 , n2493 );
nand ( n2495 , n2488 , n2494 );
not ( n2496 , n2495 );
or ( n2497 , n2487 , n2496 );
and ( n2498 , n1204 , n1332 );
not ( n2499 , n1204 );
not ( n2500 , n1332 );
and ( n2501 , n2499 , n2500 );
nor ( n2502 , n2498 , n2501 );
xnor ( n2503 , n1076 , n1460 );
and ( n2504 , n2502 , n2503 );
not ( n2505 , n2502 );
xor ( n2506 , n1076 , n1460 );
and ( n2507 , n2505 , n2506 );
nor ( n2508 , n2504 , n2507 );
nand ( n2509 , n2497 , n2508 );
nor ( n2510 , n2475 , n2509 );
xor ( n2511 , n1466 , n1338 );
and ( n2512 , n1082 , n1210 );
not ( n2513 , n1082 );
not ( n2514 , n1210 );
and ( n2515 , n2513 , n2514 );
nor ( n2516 , n2512 , n2515 );
or ( n2517 , n2511 , n2516 );
xor ( n2518 , n1338 , n1466 );
nand ( n2519 , n2518 , n2516 );
nand ( n2520 , n2517 , n2519 );
not ( n2521 , n1083 );
and ( n2522 , n1211 , n2521 );
not ( n2523 , n1211 );
and ( n2524 , n2523 , n1083 );
nor ( n2525 , n2522 , n2524 );
and ( n2526 , n1339 , n1467 );
not ( n2527 , n1339 );
not ( n2528 , n1467 );
and ( n2529 , n2527 , n2528 );
nor ( n2530 , n2526 , n2529 );
and ( n2531 , n2525 , n2530 );
not ( n2532 , n2525 );
and ( n2533 , n1339 , n1467 );
not ( n2534 , n1339 );
and ( n2535 , n2534 , n2528 );
nor ( n2536 , n2533 , n2535 );
not ( n2537 , n2536 );
and ( n2538 , n2532 , n2537 );
nor ( n2539 , n2531 , n2538 );
nand ( n2540 , n2520 , n2539 );
and ( n2541 , n1336 , n1464 );
not ( n2542 , n1336 );
not ( n2543 , n1464 );
and ( n2544 , n2542 , n2543 );
nor ( n2545 , n2541 , n2544 );
xnor ( n2546 , n1208 , n1080 );
and ( n2547 , n2545 , n2546 );
not ( n2548 , n2545 );
and ( n2549 , n1080 , n1208 );
not ( n2550 , n1080 );
not ( n2551 , n1208 );
and ( n2552 , n2550 , n2551 );
nor ( n2553 , n2549 , n2552 );
and ( n2554 , n2548 , n2553 );
nor ( n2555 , n2547 , n2554 );
and ( n2556 , n1081 , n1465 );
not ( n2557 , n1081 );
not ( n2558 , n1465 );
and ( n2559 , n2557 , n2558 );
nor ( n2560 , n2556 , n2559 );
xnor ( n2561 , n1337 , n1209 );
and ( n2562 , n2560 , n2561 );
not ( n2563 , n2560 );
and ( n2564 , n1209 , n1337 );
not ( n2565 , n1209 );
not ( n2566 , n1337 );
and ( n2567 , n2565 , n2566 );
nor ( n2568 , n2564 , n2567 );
and ( n2569 , n2563 , n2568 );
nor ( n2570 , n2562 , n2569 );
nand ( n2571 , n2555 , n2570 );
nor ( n2572 , n2540 , n2571 );
nand ( n2573 , n2510 , n2572 );
nor ( n2574 , n2442 , n2573 );
nand ( n2575 , n2324 , n2574 );
nor ( n2576 , n2046 , n2575 );
xor ( n2577 , n1103 , n1487 );
not ( n2578 , n2577 );
and ( n2579 , n1231 , n1359 );
not ( n2580 , n1231 );
not ( n2581 , n1359 );
and ( n2582 , n2580 , n2581 );
nor ( n2583 , n2579 , n2582 );
not ( n2584 , n2583 );
or ( n2585 , n2578 , n2584 );
or ( n2586 , n2583 , n2577 );
nand ( n2587 , n2585 , n2586 );
and ( n2588 , n1358 , n1486 );
not ( n2589 , n1358 );
not ( n2590 , n1486 );
and ( n2591 , n2589 , n2590 );
nor ( n2592 , n2588 , n2591 );
not ( n2593 , n2592 );
and ( n2594 , n1102 , n1230 );
not ( n2595 , n1102 );
not ( n2596 , n1230 );
and ( n2597 , n2595 , n2596 );
nor ( n2598 , n2594 , n2597 );
not ( n2599 , n2598 );
or ( n2600 , n2593 , n2599 );
or ( n2601 , n2592 , n2598 );
nand ( n2602 , n2600 , n2601 );
nand ( n2603 , n2587 , n2602 );
xor ( n2604 , n1100 , n1484 );
not ( n2605 , n2604 );
and ( n2606 , n1228 , n1356 );
not ( n2607 , n1228 );
not ( n2608 , n1356 );
and ( n2609 , n2607 , n2608 );
nor ( n2610 , n2606 , n2609 );
not ( n2611 , n2610 );
or ( n2612 , n2605 , n2611 );
or ( n2613 , n2604 , n2610 );
nand ( n2614 , n2612 , n2613 );
and ( n2615 , n1101 , n1229 );
not ( n2616 , n1101 );
not ( n2617 , n1229 );
and ( n2618 , n2616 , n2617 );
nor ( n2619 , n2615 , n2618 );
xor ( n2620 , n1357 , n1485 );
not ( n2621 , n2620 );
and ( n2622 , n2619 , n2621 );
not ( n2623 , n2619 );
and ( n2624 , n2623 , n2620 );
nor ( n2625 , n2622 , n2624 );
nand ( n2626 , n2614 , n2625 );
nor ( n2627 , n2603 , n2626 );
and ( n2628 , n1363 , n1491 );
not ( n2629 , n1363 );
not ( n2630 , n1491 );
and ( n2631 , n2629 , n2630 );
nor ( n2632 , n2628 , n2631 );
not ( n2633 , n2632 );
and ( n2634 , n1107 , n1235 );
not ( n2635 , n1107 );
not ( n2636 , n1235 );
and ( n2637 , n2635 , n2636 );
nor ( n2638 , n2634 , n2637 );
not ( n2639 , n2638 );
or ( n2640 , n2633 , n2639 );
or ( n2641 , n2638 , n2632 );
nand ( n2642 , n2640 , n2641 );
xor ( n2643 , n1106 , n1490 );
not ( n2644 , n2643 );
and ( n2645 , n1234 , n1362 );
not ( n2646 , n1234 );
not ( n2647 , n1362 );
and ( n2648 , n2646 , n2647 );
nor ( n2649 , n2645 , n2648 );
not ( n2650 , n2649 );
or ( n2651 , n2644 , n2650 );
or ( n2652 , n2649 , n2643 );
nand ( n2653 , n2651 , n2652 );
nand ( n2654 , n2642 , n2653 );
and ( n2655 , n1104 , n1488 );
not ( n2656 , n1104 );
not ( n2657 , n1488 );
and ( n2658 , n2656 , n2657 );
nor ( n2659 , n2655 , n2658 );
not ( n2660 , n2659 );
and ( n2661 , n1232 , n1360 );
not ( n2662 , n1232 );
not ( n2663 , n1360 );
and ( n2664 , n2662 , n2663 );
nor ( n2665 , n2661 , n2664 );
not ( n2666 , n2665 );
or ( n2667 , n2660 , n2666 );
or ( n2668 , n2659 , n2665 );
nand ( n2669 , n2667 , n2668 );
not ( n2670 , n1233 );
and ( n2671 , n1361 , n2670 );
not ( n2672 , n1361 );
and ( n2673 , n2672 , n1233 );
nor ( n2674 , n2671 , n2673 );
and ( n2675 , n1105 , n1489 );
not ( n2676 , n1105 );
not ( n2677 , n1489 );
and ( n2678 , n2676 , n2677 );
nor ( n2679 , n2675 , n2678 );
and ( n2680 , n2674 , n2679 );
not ( n2681 , n2674 );
not ( n2682 , n2679 );
and ( n2683 , n2681 , n2682 );
nor ( n2684 , n2680 , n2683 );
nand ( n2685 , n2669 , n2684 );
nor ( n2686 , n2654 , n2685 );
nand ( n2687 , n2627 , n2686 );
xor ( n2688 , n1108 , n1492 );
and ( n2689 , n1236 , n1364 );
not ( n2690 , n1236 );
not ( n2691 , n1364 );
and ( n2692 , n2690 , n2691 );
nor ( n2693 , n2689 , n2692 );
not ( n2694 , n2693 );
and ( n2695 , n2688 , n2694 );
not ( n2696 , n2688 );
and ( n2697 , n2696 , n2693 );
nor ( n2698 , n2695 , n2697 );
xor ( n2699 , n1365 , n1493 );
and ( n2700 , n1109 , n1237 );
not ( n2701 , n1109 );
not ( n2702 , n1237 );
and ( n2703 , n2701 , n2702 );
nor ( n2704 , n2700 , n2703 );
not ( n2705 , n2704 );
and ( n2706 , n2699 , n2705 );
not ( n2707 , n2699 );
and ( n2708 , n2707 , n2704 );
nor ( n2709 , n2706 , n2708 );
nand ( n2710 , n2698 , n2709 );
and ( n2711 , n1111 , n1239 );
not ( n2712 , n1111 );
not ( n2713 , n1239 );
and ( n2714 , n2712 , n2713 );
nor ( n2715 , n2711 , n2714 );
xor ( n2716 , n1367 , n1495 );
not ( n2717 , n2716 );
and ( n2718 , n2715 , n2717 );
not ( n2719 , n2715 );
and ( n2720 , n2719 , n2716 );
nor ( n2721 , n2718 , n2720 );
and ( n2722 , n1110 , n1238 );
not ( n2723 , n1110 );
not ( n2724 , n1238 );
and ( n2725 , n2723 , n2724 );
nor ( n2726 , n2722 , n2725 );
xor ( n2727 , n1366 , n1494 );
not ( n2728 , n2727 );
and ( n2729 , n2726 , n2728 );
not ( n2730 , n2726 );
and ( n2731 , n2730 , n2727 );
nor ( n2732 , n2729 , n2731 );
nand ( n2733 , n2721 , n2732 );
nor ( n2734 , n2710 , n2733 );
and ( n2735 , n1112 , n1240 );
not ( n2736 , n1112 );
not ( n2737 , n1240 );
and ( n2738 , n2736 , n2737 );
nor ( n2739 , n2735 , n2738 );
xor ( n2740 , n1368 , n1496 );
nand ( n2741 , n2739 , n2740 );
not ( n2742 , n2741 );
not ( n2743 , n2739 );
not ( n2744 , n2740 );
nand ( n2745 , n2743 , n2744 );
not ( n2746 , n2745 );
or ( n2747 , n2742 , n2746 );
not ( n2748 , n1113 );
and ( n2749 , n1241 , n2748 );
not ( n2750 , n1241 );
and ( n2751 , n2750 , n1113 );
nor ( n2752 , n2749 , n2751 );
and ( n2753 , n1369 , n1497 );
not ( n2754 , n1369 );
not ( n2755 , n1497 );
and ( n2756 , n2754 , n2755 );
nor ( n2757 , n2753 , n2756 );
and ( n2758 , n2752 , n2757 );
not ( n2759 , n2752 );
not ( n2760 , n2757 );
and ( n2761 , n2759 , n2760 );
nor ( n2762 , n2758 , n2761 );
nand ( n2763 , n2747 , n2762 );
and ( n2764 , n1114 , n1242 );
not ( n2765 , n1114 );
not ( n2766 , n1242 );
and ( n2767 , n2765 , n2766 );
nor ( n2768 , n2764 , n2767 );
xor ( n2769 , n1370 , n1498 );
not ( n2770 , n2769 );
and ( n2771 , n2768 , n2770 );
not ( n2772 , n2768 );
and ( n2773 , n2772 , n2769 );
nor ( n2774 , n2771 , n2773 );
and ( n2775 , n1371 , n1499 );
not ( n2776 , n1371 );
not ( n2777 , n1499 );
and ( n2778 , n2776 , n2777 );
nor ( n2779 , n2775 , n2778 );
and ( n2780 , n1115 , n1243 );
not ( n2781 , n1115 );
not ( n2782 , n1243 );
and ( n2783 , n2781 , n2782 );
nor ( n2784 , n2780 , n2783 );
not ( n2785 , n2784 );
and ( n2786 , n2779 , n2785 );
not ( n2787 , n2779 );
and ( n2788 , n2787 , n2784 );
nor ( n2789 , n2786 , n2788 );
nand ( n2790 , n2774 , n2789 );
nor ( n2791 , n2763 , n2790 );
nand ( n2792 , n2734 , n2791 );
nor ( n2793 , n2687 , n2792 );
and ( n2794 , n1379 , n1507 );
not ( n2795 , n1379 );
not ( n2796 , n1507 );
and ( n2797 , n2795 , n2796 );
nor ( n2798 , n2794 , n2797 );
not ( n2799 , n2798 );
and ( n2800 , n1123 , n1251 );
not ( n2801 , n1123 );
not ( n2802 , n1251 );
and ( n2803 , n2801 , n2802 );
nor ( n2804 , n2800 , n2803 );
not ( n2805 , n2804 );
or ( n2806 , n2799 , n2805 );
or ( n2807 , n2798 , n2804 );
nand ( n2808 , n2806 , n2807 );
and ( n2809 , n1378 , n1506 );
not ( n2810 , n1378 );
not ( n2811 , n1506 );
and ( n2812 , n2810 , n2811 );
nor ( n2813 , n2809 , n2812 );
not ( n2814 , n2813 );
and ( n2815 , n1122 , n1250 );
not ( n2816 , n1122 );
not ( n2817 , n1250 );
and ( n2818 , n2816 , n2817 );
nor ( n2819 , n2815 , n2818 );
not ( n2820 , n2819 );
or ( n2821 , n2814 , n2820 );
or ( n2822 , n2813 , n2819 );
nand ( n2823 , n2821 , n2822 );
nand ( n2824 , n2808 , n2823 );
xor ( n2825 , n1376 , n1504 );
not ( n2826 , n2825 );
and ( n2827 , n1120 , n1248 );
not ( n2828 , n1120 );
not ( n2829 , n1248 );
and ( n2830 , n2828 , n2829 );
nor ( n2831 , n2827 , n2830 );
not ( n2832 , n2831 );
or ( n2833 , n2826 , n2832 );
or ( n2834 , n2831 , n2825 );
nand ( n2835 , n2833 , n2834 );
and ( n2836 , n1121 , n1249 );
not ( n2837 , n1121 );
not ( n2838 , n1249 );
and ( n2839 , n2837 , n2838 );
nor ( n2840 , n2836 , n2839 );
xor ( n2841 , n1377 , n1505 );
not ( n2842 , n2841 );
and ( n2843 , n2840 , n2842 );
not ( n2844 , n2840 );
and ( n2845 , n2844 , n2841 );
nor ( n2846 , n2843 , n2845 );
nand ( n2847 , n2835 , n2846 );
nor ( n2848 , n2824 , n2847 );
and ( n2849 , n1117 , n1245 );
not ( n2850 , n1117 );
not ( n2851 , n1245 );
and ( n2852 , n2850 , n2851 );
nor ( n2853 , n2849 , n2852 );
and ( n2854 , n1373 , n1501 );
not ( n2855 , n1373 );
not ( n2856 , n1501 );
and ( n2857 , n2855 , n2856 );
nor ( n2858 , n2854 , n2857 );
not ( n2859 , n2858 );
and ( n2860 , n2853 , n2859 );
not ( n2861 , n2853 );
and ( n2862 , n2861 , n2858 );
nor ( n2863 , n2860 , n2862 );
xor ( n2864 , n1116 , n1500 );
and ( n2865 , n1244 , n1372 );
not ( n2866 , n1244 );
not ( n2867 , n1372 );
and ( n2868 , n2866 , n2867 );
nor ( n2869 , n2865 , n2868 );
not ( n2870 , n2869 );
and ( n2871 , n2864 , n2870 );
not ( n2872 , n2864 );
and ( n2873 , n2872 , n2869 );
nor ( n2874 , n2871 , n2873 );
nand ( n2875 , n2863 , n2874 );
and ( n2876 , n1118 , n1246 );
not ( n2877 , n1118 );
not ( n2878 , n1246 );
and ( n2879 , n2877 , n2878 );
nor ( n2880 , n2876 , n2879 );
and ( n2881 , n1374 , n1502 );
not ( n2882 , n1374 );
not ( n2883 , n1502 );
and ( n2884 , n2882 , n2883 );
nor ( n2885 , n2881 , n2884 );
nand ( n2886 , n2880 , n2885 );
not ( n2887 , n2886 );
nor ( n2888 , n2885 , n2880 );
or ( n2889 , n2887 , n2888 );
and ( n2890 , n1119 , n1247 );
not ( n2891 , n1119 );
not ( n2892 , n1247 );
and ( n2893 , n2891 , n2892 );
nor ( n2894 , n2890 , n2893 );
xor ( n2895 , n1375 , n1503 );
or ( n2896 , n2894 , n2895 );
and ( n2897 , n1119 , n1247 );
not ( n2898 , n1119 );
and ( n2899 , n2898 , n2892 );
nor ( n2900 , n2897 , n2899 );
nand ( n2901 , n2900 , n2895 );
nand ( n2902 , n2896 , n2901 );
nand ( n2903 , n2889 , n2902 );
nor ( n2904 , n2875 , n2903 );
nand ( n2905 , n2848 , n2904 );
and ( n2906 , n1387 , n1515 );
not ( n2907 , n1387 );
not ( n2908 , n1515 );
and ( n2909 , n2907 , n2908 );
nor ( n2910 , n2906 , n2909 );
not ( n2911 , n2910 );
and ( n2912 , n1131 , n1259 );
not ( n2913 , n1131 );
not ( n2914 , n1259 );
and ( n2915 , n2913 , n2914 );
nor ( n2916 , n2912 , n2915 );
not ( n2917 , n2916 );
or ( n2918 , n2911 , n2917 );
or ( n2919 , n2916 , n2910 );
nand ( n2920 , n2918 , n2919 );
and ( n2921 , n1130 , n1258 );
not ( n2922 , n1130 );
not ( n2923 , n1258 );
and ( n2924 , n2922 , n2923 );
nor ( n2925 , n2921 , n2924 );
not ( n2926 , n2925 );
xor ( n2927 , n1386 , n1514 );
not ( n2928 , n2927 );
or ( n2929 , n2926 , n2928 );
or ( n2930 , n2927 , n2925 );
nand ( n2931 , n2929 , n2930 );
nand ( n2932 , n2920 , n2931 );
xor ( n2933 , n1385 , n1513 );
and ( n2934 , n1129 , n1257 );
not ( n2935 , n1129 );
not ( n2936 , n1257 );
and ( n2937 , n2935 , n2936 );
nor ( n2938 , n2934 , n2937 );
not ( n2939 , n2938 );
and ( n2940 , n2933 , n2939 );
not ( n2941 , n2933 );
and ( n2942 , n2941 , n2938 );
nor ( n2943 , n2940 , n2942 );
xor ( n2944 , n1384 , n1512 );
and ( n2945 , n1128 , n1256 );
not ( n2946 , n1128 );
not ( n2947 , n1256 );
and ( n2948 , n2946 , n2947 );
nor ( n2949 , n2945 , n2948 );
not ( n2950 , n2949 );
and ( n2951 , n2944 , n2950 );
not ( n2952 , n2944 );
and ( n2953 , n2952 , n2949 );
nor ( n2954 , n2951 , n2953 );
nand ( n2955 , n2943 , n2954 );
nor ( n2956 , n2932 , n2955 );
and ( n2957 , n1509 , n1125 );
not ( n2958 , n1509 );
not ( n2959 , n1125 );
and ( n2960 , n2958 , n2959 );
nor ( n2961 , n2957 , n2960 );
and ( n2962 , n1253 , n1381 );
not ( n2963 , n1253 );
not ( n2964 , n1381 );
and ( n2965 , n2963 , n2964 );
nor ( n2966 , n2962 , n2965 );
nand ( n2967 , n2961 , n2966 );
not ( n2968 , n2967 );
not ( n2969 , n2966 );
and ( n2970 , n1509 , n1125 );
not ( n2971 , n1509 );
and ( n2972 , n2971 , n2959 );
nor ( n2973 , n2970 , n2972 );
not ( n2974 , n2973 );
nand ( n2975 , n2969 , n2974 );
not ( n2976 , n2975 );
or ( n2977 , n2968 , n2976 );
not ( n2978 , n1380 );
nand ( n2979 , n2978 , n1508 );
not ( n2980 , n1508 );
nand ( n2981 , n2980 , n1380 );
nand ( n2982 , n2979 , n2981 );
and ( n2983 , n1124 , n1252 );
not ( n2984 , n1124 );
not ( n2985 , n1252 );
and ( n2986 , n2984 , n2985 );
nor ( n2987 , n2983 , n2986 );
or ( n2988 , n2982 , n2987 );
nand ( n2989 , n2982 , n2987 );
nand ( n2990 , n2988 , n2989 );
nand ( n2991 , n2977 , n2990 );
and ( n2992 , n1255 , n1383 );
not ( n2993 , n1255 );
not ( n2994 , n1383 );
and ( n2995 , n2993 , n2994 );
nor ( n2996 , n2992 , n2995 );
xor ( n2997 , n1127 , n1511 );
not ( n2998 , n2997 );
and ( n2999 , n2996 , n2998 );
not ( n3000 , n2996 );
and ( n3001 , n3000 , n2997 );
nor ( n3002 , n2999 , n3001 );
and ( n3003 , n1126 , n1254 );
not ( n3004 , n1126 );
not ( n3005 , n1254 );
and ( n3006 , n3004 , n3005 );
nor ( n3007 , n3003 , n3006 );
xor ( n3008 , n1382 , n1510 );
not ( n3009 , n3008 );
and ( n3010 , n3007 , n3009 );
not ( n3011 , n3007 );
and ( n3012 , n3011 , n3008 );
nor ( n3013 , n3010 , n3012 );
nand ( n3014 , n3002 , n3013 );
nor ( n3015 , n2991 , n3014 );
nand ( n3016 , n2956 , n3015 );
nor ( n3017 , n2905 , n3016 );
nand ( n3018 , n2793 , n3017 );
not ( n3019 , n3018 );
not ( n3020 , n1139 );
and ( n3021 , n1267 , n3020 );
not ( n3022 , n1267 );
and ( n3023 , n3022 , n1139 );
nor ( n3024 , n3021 , n3023 );
and ( n3025 , n1395 , n1523 );
not ( n3026 , n1395 );
not ( n3027 , n1523 );
and ( n3028 , n3026 , n3027 );
nor ( n3029 , n3025 , n3028 );
and ( n3030 , n3024 , n3029 );
not ( n3031 , n3024 );
not ( n3032 , n3029 );
and ( n3033 , n3031 , n3032 );
nor ( n3034 , n3030 , n3033 );
and ( n3035 , n1138 , n1266 );
not ( n3036 , n1138 );
not ( n3037 , n1266 );
and ( n3038 , n3036 , n3037 );
nor ( n3039 , n3035 , n3038 );
and ( n3040 , n1394 , n1522 );
not ( n3041 , n1394 );
not ( n3042 , n1522 );
and ( n3043 , n3041 , n3042 );
nor ( n3044 , n3040 , n3043 );
not ( n3045 , n3044 );
and ( n3046 , n3039 , n3045 );
not ( n3047 , n3039 );
and ( n3048 , n3047 , n3044 );
nor ( n3049 , n3046 , n3048 );
nand ( n3050 , n3034 , n3049 );
and ( n3051 , n1136 , n1264 );
not ( n3052 , n1136 );
not ( n3053 , n1264 );
and ( n3054 , n3052 , n3053 );
nor ( n3055 , n3051 , n3054 );
xor ( n3056 , n1392 , n1520 );
nand ( n3057 , n3055 , n3056 );
not ( n3058 , n3057 );
and ( n3059 , n1136 , n1264 );
not ( n3060 , n1136 );
and ( n3061 , n3060 , n3053 );
or ( n3062 , n3059 , n3061 );
not ( n3063 , n3056 );
nand ( n3064 , n3062 , n3063 );
not ( n3065 , n3064 );
or ( n3066 , n3058 , n3065 );
not ( n3067 , n1265 );
and ( n3068 , n1393 , n3067 );
not ( n3069 , n1393 );
and ( n3070 , n3069 , n1265 );
nor ( n3071 , n3068 , n3070 );
and ( n3072 , n1137 , n1521 );
not ( n3073 , n1137 );
not ( n3074 , n1521 );
and ( n3075 , n3073 , n3074 );
nor ( n3076 , n3072 , n3075 );
and ( n3077 , n3071 , n3076 );
not ( n3078 , n3071 );
not ( n3079 , n3076 );
and ( n3080 , n3078 , n3079 );
nor ( n3081 , n3077 , n3080 );
nand ( n3082 , n3066 , n3081 );
nor ( n3083 , n3050 , n3082 );
and ( n3084 , n1263 , n1391 );
not ( n3085 , n1263 );
not ( n3086 , n1391 );
and ( n3087 , n3085 , n3086 );
nor ( n3088 , n3084 , n3087 );
not ( n3089 , n3088 );
xor ( n3090 , n1135 , n1519 );
not ( n3091 , n3090 );
or ( n3092 , n3089 , n3091 );
or ( n3093 , n3090 , n3088 );
nand ( n3094 , n3092 , n3093 );
and ( n3095 , n1390 , n1518 );
not ( n3096 , n1390 );
not ( n3097 , n1518 );
and ( n3098 , n3096 , n3097 );
nor ( n3099 , n3095 , n3098 );
not ( n3100 , n3099 );
and ( n3101 , n1134 , n1262 );
not ( n3102 , n1134 );
not ( n3103 , n1262 );
and ( n3104 , n3102 , n3103 );
nor ( n3105 , n3101 , n3104 );
not ( n3106 , n3105 );
or ( n3107 , n3100 , n3106 );
and ( n3108 , n1134 , n1262 );
not ( n3109 , n1134 );
and ( n3110 , n3109 , n3103 );
nor ( n3111 , n3108 , n3110 );
or ( n3112 , n3111 , n3099 );
nand ( n3113 , n3107 , n3112 );
nand ( n3114 , n3094 , n3113 );
xor ( n3115 , n1133 , n1517 );
and ( n3116 , n1261 , n1389 );
not ( n3117 , n1261 );
not ( n3118 , n1389 );
and ( n3119 , n3117 , n3118 );
nor ( n3120 , n3116 , n3119 );
not ( n3121 , n3120 );
and ( n3122 , n3115 , n3121 );
not ( n3123 , n3115 );
and ( n3124 , n3123 , n3120 );
nor ( n3125 , n3122 , n3124 );
xor ( n3126 , n1132 , n1516 );
and ( n3127 , n1260 , n1388 );
not ( n3128 , n1260 );
not ( n3129 , n1388 );
and ( n3130 , n3128 , n3129 );
nor ( n3131 , n3127 , n3130 );
not ( n3132 , n3131 );
and ( n3133 , n3126 , n3132 );
not ( n3134 , n3126 );
and ( n3135 , n3134 , n3131 );
nor ( n3136 , n3133 , n3135 );
nand ( n3137 , n3125 , n3136 );
nor ( n3138 , n3114 , n3137 );
nand ( n3139 , n3083 , n3138 );
not ( n3140 , n1402 );
nand ( n3141 , n3140 , n1530 );
not ( n3142 , n1530 );
nand ( n3143 , n3142 , n1402 );
nand ( n3144 , n3141 , n3143 );
and ( n3145 , n1146 , n1274 );
not ( n3146 , n1146 );
not ( n3147 , n1274 );
and ( n3148 , n3146 , n3147 );
nor ( n3149 , n3145 , n3148 );
or ( n3150 , n3144 , n3149 );
not ( n3151 , n3143 );
not ( n3152 , n3141 );
or ( n3153 , n3151 , n3152 );
nand ( n3154 , n3153 , n3149 );
nand ( n3155 , n3150 , n3154 );
and ( n3156 , n1403 , n1531 );
not ( n3157 , n1403 );
not ( n3158 , n1531 );
and ( n3159 , n3157 , n3158 );
nor ( n3160 , n3156 , n3159 );
and ( n3161 , n1147 , n1275 );
not ( n3162 , n1147 );
not ( n3163 , n1275 );
and ( n3164 , n3162 , n3163 );
nor ( n3165 , n3161 , n3164 );
not ( n3166 , n3165 );
and ( n3167 , n3160 , n3166 );
not ( n3168 , n3160 );
and ( n3169 , n3168 , n3165 );
nor ( n3170 , n3167 , n3169 );
nand ( n3171 , n3155 , n3170 );
and ( n3172 , n1529 , n1401 );
not ( n3173 , n1529 );
not ( n3174 , n1401 );
and ( n3175 , n3173 , n3174 );
nor ( n3176 , n3172 , n3175 );
not ( n3177 , n3176 );
and ( n3178 , n1273 , n1145 );
not ( n3179 , n1273 );
not ( n3180 , n1145 );
and ( n3181 , n3179 , n3180 );
nor ( n3182 , n3178 , n3181 );
not ( n3183 , n3182 );
or ( n3184 , n3177 , n3183 );
and ( n3185 , n1145 , n1273 );
not ( n3186 , n1145 );
not ( n3187 , n1273 );
and ( n3188 , n3186 , n3187 );
nor ( n3189 , n3185 , n3188 );
and ( n3190 , n1401 , n1529 );
not ( n3191 , n1401 );
not ( n3192 , n1529 );
and ( n3193 , n3191 , n3192 );
nor ( n3194 , n3190 , n3193 );
or ( n3195 , n3189 , n3194 );
nand ( n3196 , n3184 , n3195 );
not ( n3197 , n1400 );
not ( n3198 , n1528 );
not ( n3199 , n3198 );
or ( n3200 , n3197 , n3199 );
not ( n3201 , n1400 );
nand ( n3202 , n3201 , n1528 );
nand ( n3203 , n3200 , n3202 );
and ( n3204 , n1144 , n1272 );
not ( n3205 , n1144 );
not ( n3206 , n1272 );
and ( n3207 , n3205 , n3206 );
nor ( n3208 , n3204 , n3207 );
or ( n3209 , n3203 , n3208 );
not ( n3210 , n3202 );
nand ( n3211 , n3198 , n1400 );
not ( n3212 , n3211 );
or ( n3213 , n3210 , n3212 );
nand ( n3214 , n3213 , n3208 );
nand ( n3215 , n3209 , n3214 );
nand ( n3216 , n3196 , n3215 );
nor ( n3217 , n3171 , n3216 );
and ( n3218 , n1143 , n1271 );
not ( n3219 , n1143 );
not ( n3220 , n1271 );
and ( n3221 , n3219 , n3220 );
nor ( n3222 , n3218 , n3221 );
not ( n3223 , n1399 );
not ( n3224 , n1527 );
not ( n3225 , n3224 );
or ( n3226 , n3223 , n3225 );
not ( n3227 , n1399 );
nand ( n3228 , n3227 , n1527 );
nand ( n3229 , n3226 , n3228 );
or ( n3230 , n3222 , n3229 );
not ( n3231 , n3228 );
nand ( n3232 , n3224 , n1399 );
not ( n3233 , n3232 );
or ( n3234 , n3231 , n3233 );
nand ( n3235 , n3234 , n3222 );
nand ( n3236 , n3230 , n3235 );
not ( n3237 , n1526 );
and ( n3238 , n1142 , n3237 );
not ( n3239 , n1142 );
and ( n3240 , n3239 , n1526 );
nor ( n3241 , n3238 , n3240 );
and ( n3242 , n1270 , n1398 );
not ( n3243 , n1270 );
not ( n3244 , n1398 );
and ( n3245 , n3243 , n3244 );
nor ( n3246 , n3242 , n3245 );
and ( n3247 , n3241 , n3246 );
not ( n3248 , n3241 );
not ( n3249 , n3246 );
and ( n3250 , n3248 , n3249 );
nor ( n3251 , n3247 , n3250 );
nand ( n3252 , n3236 , n3251 );
not ( n3253 , n1525 );
nand ( n3254 , n3253 , n1141 );
not ( n3255 , n1141 );
nand ( n3256 , n3255 , n1525 );
nand ( n3257 , n3254 , n3256 );
and ( n3258 , n1269 , n1397 );
not ( n3259 , n1269 );
not ( n3260 , n1397 );
and ( n3261 , n3259 , n3260 );
nor ( n3262 , n3258 , n3261 );
or ( n3263 , n3257 , n3262 );
nand ( n3264 , n3255 , n1525 );
not ( n3265 , n3264 );
not ( n3266 , n3254 );
or ( n3267 , n3265 , n3266 );
nand ( n3268 , n3267 , n3262 );
nand ( n3269 , n3263 , n3268 );
not ( n3270 , n1396 );
not ( n3271 , n3270 );
not ( n3272 , n1524 );
or ( n3273 , n3271 , n3272 );
not ( n3274 , n1524 );
nand ( n3275 , n3274 , n1396 );
nand ( n3276 , n3273 , n3275 );
and ( n3277 , n1140 , n1268 );
not ( n3278 , n1140 );
not ( n3279 , n1268 );
and ( n3280 , n3278 , n3279 );
nor ( n3281 , n3277 , n3280 );
or ( n3282 , n3276 , n3281 );
nand ( n3283 , n3274 , n1396 );
not ( n3284 , n3283 );
nand ( n3285 , n3270 , n1524 );
not ( n3286 , n3285 );
or ( n3287 , n3284 , n3286 );
nand ( n3288 , n3287 , n3281 );
nand ( n3289 , n3282 , n3288 );
nand ( n3290 , n3269 , n3289 );
nor ( n3291 , n3252 , n3290 );
nand ( n3292 , n3217 , n3291 );
nor ( n3293 , n3139 , n3292 );
and ( n3294 , n1155 , n1283 );
not ( n3295 , n1155 );
not ( n3296 , n1283 );
and ( n3297 , n3295 , n3296 );
nor ( n3298 , n3294 , n3297 );
not ( n3299 , n3298 );
xor ( n3300 , n1411 , n1539 );
not ( n3301 , n3300 );
or ( n3302 , n3299 , n3301 );
or ( n3303 , n3298 , n3300 );
nand ( n3304 , n3302 , n3303 );
and ( n3305 , n1282 , n1410 );
not ( n3306 , n1282 );
not ( n3307 , n1410 );
and ( n3308 , n3306 , n3307 );
nor ( n3309 , n3305 , n3308 );
not ( n3310 , n3309 );
xor ( n3311 , n1154 , n1538 );
not ( n3312 , n3311 );
or ( n3313 , n3310 , n3312 );
or ( n3314 , n3309 , n3311 );
nand ( n3315 , n3313 , n3314 );
nand ( n3316 , n3304 , n3315 );
not ( n3317 , n1153 );
not ( n3318 , n1537 );
not ( n3319 , n3318 );
or ( n3320 , n3317 , n3319 );
not ( n3321 , n1153 );
nand ( n3322 , n3321 , n1537 );
nand ( n3323 , n3320 , n3322 );
not ( n3324 , n3323 );
and ( n3325 , n1281 , n1409 );
not ( n3326 , n1281 );
not ( n3327 , n1409 );
and ( n3328 , n3326 , n3327 );
nor ( n3329 , n3325 , n3328 );
not ( n3330 , n3329 );
or ( n3331 , n3324 , n3330 );
and ( n3332 , n1281 , n1409 );
not ( n3333 , n1281 );
and ( n3334 , n3333 , n3327 );
nor ( n3335 , n3332 , n3334 );
not ( n3336 , n1153 );
not ( n3337 , n3318 );
or ( n3338 , n3336 , n3337 );
nand ( n3339 , n3338 , n3322 );
or ( n3340 , n3335 , n3339 );
nand ( n3341 , n3331 , n3340 );
not ( n3342 , n1536 );
and ( n3343 , n1152 , n3342 );
not ( n3344 , n1152 );
and ( n3345 , n3344 , n1536 );
nor ( n3346 , n3343 , n3345 );
and ( n3347 , n1280 , n1408 );
not ( n3348 , n1280 );
not ( n3349 , n1408 );
and ( n3350 , n3348 , n3349 );
nor ( n3351 , n3347 , n3350 );
and ( n3352 , n3346 , n3351 );
not ( n3353 , n3346 );
not ( n3354 , n3351 );
and ( n3355 , n3353 , n3354 );
nor ( n3356 , n3352 , n3355 );
nand ( n3357 , n3341 , n3356 );
nor ( n3358 , n3316 , n3357 );
xor ( n3359 , n1532 , n1404 );
and ( n3360 , n1148 , n1276 );
not ( n3361 , n1148 );
not ( n3362 , n1276 );
and ( n3363 , n3361 , n3362 );
nor ( n3364 , n3360 , n3363 );
not ( n3365 , n3364 );
and ( n3366 , n3359 , n3365 );
not ( n3367 , n3359 );
and ( n3368 , n3367 , n3364 );
nor ( n3369 , n3366 , n3368 );
and ( n3370 , n1533 , n1405 );
not ( n3371 , n1533 );
not ( n3372 , n1405 );
and ( n3373 , n3371 , n3372 );
nor ( n3374 , n3370 , n3373 );
and ( n3375 , n1149 , n1277 );
not ( n3376 , n1149 );
not ( n3377 , n1277 );
and ( n3378 , n3376 , n3377 );
nor ( n3379 , n3375 , n3378 );
not ( n3380 , n3379 );
and ( n3381 , n3374 , n3380 );
not ( n3382 , n3374 );
and ( n3383 , n3382 , n3379 );
nor ( n3384 , n3381 , n3383 );
nand ( n3385 , n3369 , n3384 );
xor ( n3386 , n1407 , n1535 );
not ( n3387 , n3386 );
and ( n3388 , n1151 , n1279 );
not ( n3389 , n1151 );
not ( n3390 , n1279 );
and ( n3391 , n3389 , n3390 );
nor ( n3392 , n3388 , n3391 );
not ( n3393 , n3392 );
or ( n3394 , n3387 , n3393 );
and ( n3395 , n1151 , n1279 );
not ( n3396 , n1151 );
and ( n3397 , n3396 , n3390 );
nor ( n3398 , n3395 , n3397 );
or ( n3399 , n3398 , n3386 );
nand ( n3400 , n3394 , n3399 );
not ( n3401 , n1150 );
and ( n3402 , n1278 , n3401 );
not ( n3403 , n1278 );
and ( n3404 , n3403 , n1150 );
nor ( n3405 , n3402 , n3404 );
and ( n3406 , n1406 , n1534 );
not ( n3407 , n1406 );
not ( n3408 , n1534 );
and ( n3409 , n3407 , n3408 );
nor ( n3410 , n3406 , n3409 );
and ( n3411 , n3405 , n3410 );
not ( n3412 , n3405 );
not ( n3413 , n3410 );
and ( n3414 , n3412 , n3413 );
nor ( n3415 , n3411 , n3414 );
nand ( n3416 , n3400 , n3415 );
nor ( n3417 , n3385 , n3416 );
nand ( n3418 , n3358 , n3417 );
not ( n3419 , n1414 );
nand ( n3420 , n3419 , n1542 );
not ( n3421 , n1542 );
nand ( n3422 , n3421 , n1414 );
nand ( n3423 , n3420 , n3422 );
and ( n3424 , n1158 , n1286 );
not ( n3425 , n1158 );
not ( n3426 , n1286 );
and ( n3427 , n3425 , n3426 );
nor ( n3428 , n3424 , n3427 );
or ( n3429 , n3423 , n3428 );
not ( n3430 , n3422 );
not ( n3431 , n3420 );
or ( n3432 , n3430 , n3431 );
nand ( n3433 , n3432 , n3428 );
nand ( n3434 , n3429 , n3433 );
and ( n3435 , n1159 , n1287 );
not ( n3436 , n1159 );
not ( n3437 , n1287 );
and ( n3438 , n3436 , n3437 );
nor ( n3439 , n3435 , n3438 );
not ( n3440 , n3439 );
not ( n3441 , n1415 );
nand ( n3442 , n3441 , n1543 );
not ( n3443 , n1543 );
nand ( n3444 , n3443 , n1415 );
nand ( n3445 , n3442 , n3444 );
not ( n3446 , n3445 );
or ( n3447 , n3440 , n3446 );
and ( n3448 , n1159 , n1287 );
not ( n3449 , n1159 );
and ( n3450 , n3449 , n3437 );
nor ( n3451 , n3448 , n3450 );
nand ( n3452 , n3444 , n3442 );
or ( n3453 , n3451 , n3452 );
nand ( n3454 , n3447 , n3453 );
nand ( n3455 , n3434 , n3454 );
not ( n3456 , n1156 );
nand ( n3457 , n3456 , n1540 );
not ( n3458 , n1540 );
nand ( n3459 , n3458 , n1156 );
nand ( n3460 , n3457 , n3459 );
and ( n3461 , n1284 , n1412 );
not ( n3462 , n1284 );
not ( n3463 , n1412 );
and ( n3464 , n3462 , n3463 );
nor ( n3465 , n3461 , n3464 );
or ( n3466 , n3460 , n3465 );
not ( n3467 , n1156 );
not ( n3468 , n3458 );
or ( n3469 , n3467 , n3468 );
nand ( n3470 , n3469 , n3457 );
nand ( n3471 , n3470 , n3465 );
nand ( n3472 , n3466 , n3471 );
and ( n3473 , n1157 , n1285 );
not ( n3474 , n1157 );
not ( n3475 , n1285 );
and ( n3476 , n3474 , n3475 );
nor ( n3477 , n3473 , n3476 );
not ( n3478 , n3477 );
xor ( n3479 , n1413 , n1541 );
not ( n3480 , n3479 );
or ( n3481 , n3478 , n3480 );
and ( n3482 , n1157 , n1285 );
not ( n3483 , n1157 );
and ( n3484 , n3483 , n3475 );
nor ( n3485 , n3482 , n3484 );
xor ( n3486 , n1413 , n1541 );
or ( n3487 , n3485 , n3486 );
nand ( n3488 , n3481 , n3487 );
nand ( n3489 , n3472 , n3488 );
nor ( n3490 , n3455 , n3489 );
not ( n3491 , n1163 );
nand ( n3492 , n3491 , n1547 );
not ( n3493 , n1547 );
nand ( n3494 , n3493 , n1163 );
nand ( n3495 , n3492 , n3494 );
and ( n3496 , n1291 , n1419 );
not ( n3497 , n1291 );
not ( n3498 , n1419 );
and ( n3499 , n3497 , n3498 );
nor ( n3500 , n3496 , n3499 );
or ( n3501 , n3495 , n3500 );
not ( n3502 , n3494 );
not ( n3503 , n3492 );
or ( n3504 , n3502 , n3503 );
nand ( n3505 , n3504 , n3500 );
nand ( n3506 , n3501 , n3505 );
not ( n3507 , n1290 );
and ( n3508 , n1418 , n3507 );
not ( n3509 , n1418 );
and ( n3510 , n3509 , n1290 );
nor ( n3511 , n3508 , n3510 );
and ( n3512 , n1546 , n1162 );
not ( n3513 , n1546 );
not ( n3514 , n1162 );
and ( n3515 , n3513 , n3514 );
nor ( n3516 , n3512 , n3515 );
and ( n3517 , n3511 , n3516 );
not ( n3518 , n3511 );
not ( n3519 , n3516 );
and ( n3520 , n3518 , n3519 );
nor ( n3521 , n3517 , n3520 );
nand ( n3522 , n3506 , n3521 );
xor ( n3523 , n1289 , n1417 );
not ( n3524 , n1161 );
not ( n3525 , n1545 );
not ( n3526 , n3525 );
or ( n3527 , n3524 , n3526 );
not ( n3528 , n1161 );
nand ( n3529 , n3528 , n1545 );
nand ( n3530 , n3527 , n3529 );
or ( n3531 , n3523 , n3530 );
xor ( n3532 , n1417 , n1289 );
not ( n3533 , n1161 );
not ( n3534 , n3525 );
or ( n3535 , n3533 , n3534 );
nand ( n3536 , n3535 , n3529 );
nand ( n3537 , n3532 , n3536 );
nand ( n3538 , n3531 , n3537 );
and ( n3539 , n1288 , n1416 );
not ( n3540 , n1288 );
not ( n3541 , n1416 );
and ( n3542 , n3540 , n3541 );
nor ( n3543 , n3539 , n3542 );
not ( n3544 , n3543 );
and ( n3545 , n1160 , n1544 );
not ( n3546 , n1160 );
not ( n3547 , n1544 );
and ( n3548 , n3546 , n3547 );
nor ( n3549 , n3545 , n3548 );
not ( n3550 , n3549 );
or ( n3551 , n3544 , n3550 );
and ( n3552 , n1288 , n1416 );
not ( n3553 , n1288 );
and ( n3554 , n3553 , n3541 );
nor ( n3555 , n3552 , n3554 );
and ( n3556 , n1160 , n1544 );
not ( n3557 , n1160 );
and ( n3558 , n3557 , n3547 );
nor ( n3559 , n3556 , n3558 );
or ( n3560 , n3555 , n3559 );
nand ( n3561 , n3551 , n3560 );
nand ( n3562 , n3538 , n3561 );
nor ( n3563 , n3522 , n3562 );
nand ( n3564 , n3490 , n3563 );
nor ( n3565 , n3418 , n3564 );
nand ( n3566 , n3293 , n3565 );
not ( n3567 , n3566 );
and ( n3568 , n2576 , n3019 , n3567 );
not ( n3569 , n1406 );
nand ( n3570 , n3569 , n1269 );
nor ( n3571 , n3568 , n3570 );
buf ( n3572 , n3571 );
buf ( n3573 , n3572 );
not ( n3574 , n2442 );
not ( n3575 , n2323 );
or ( n3576 , n1160 , n1546 );
nand ( n3577 , n3574 , n3575 , n3576 );
not ( n3578 , n2179 );
not ( n3579 , n2573 );
nand ( n3580 , n3578 , n3579 );
nor ( n3581 , n3577 , n3580 );
nand ( n3582 , n3581 , n3019 );
not ( n3583 , n2046 );
nand ( n3584 , n3567 , n3583 );
nor ( n3585 , n3582 , n3584 );
buf ( n3586 , n3585 );
buf ( n3587 , n3586 );
nor ( n3588 , n3018 , n3566 );
nand ( n3589 , n3588 , n2576 );
buf ( n3590 , n3589 );
buf ( n3591 , n3590 );
not ( n3592 , n3589 );
buf ( n3593 , n3592 );
buf ( n3594 , n3593 );
buf ( n3595 , n3592 );
buf ( n3596 , n3595 );
endmodule
|
/**
\file "startup.v"
Chain a bunch of inverters between VPI/VCS and prsim, shoelacing.
$Id: inverters.v,v 1.3 2010/04/06 00:08:35 fang Exp $
Thanks to Ilya Ganusov for contributing this test.
*/
`timescale 1ps/1ps
`include "clkgen.v"
module timeunit;
initial $timeformat(-9,1," ns",9);
endmodule
module TOP;
reg in, in2;
reg in3 = 1'b1;
reg out, out2, out3;
// prsim stuff
initial
begin
// @haco@ startup.haco-c
$prsim("startup.haco-c");
$prsim_cmd("echo $start of simulation");
$prsim_cmd("getall .");
$prsim_cmd("watchall");
$prsim_cmd("watchall-queue");
$prsim_cmd("set out0 1");
in2 <= 1'b1;
#5
$prsim_cmd("echo -------------- connecting ---------------");
$prsim_cmd("time");
$to_prsim("TOP.in", "in0");
$to_prsim("TOP.in2", "in1");
$to_prsim("TOP.in3", "in2");
$from_prsim("out0","TOP.out");
$from_prsim("out1","TOP.out2");
$from_prsim("!Vdd","TOP.out3"); // aliased to Vdd
$prsim_cmd("time");
$prsim_cmd("getall .");
#5
$prsim_cmd("echo -----------------------------");
$prsim_cmd("time");
in <= 1'b1;
$prsim_cmd("set out1 1");
#10
$prsim_cmd("echo -----------------------------");
$prsim_cmd("time");
$prsim_cmd("getall .");
$finish;
end
always @(in)
begin
$display("at time %7.3f, observed in %b", $realtime,in);
end
always @(in2)
begin
$display("at time %7.3f, observed in2 %b", $realtime,in2);
end
always @(in3)
begin
$display("at time %7.3f, observed in3 %b", $realtime,in3);
end
always @(out)
begin
$display("at time %7.3f, observed out = %b", $realtime,out);
end
always @(out2)
begin
$display("at time %7.3f, observed out2 = %b", $realtime,out2);
end
always @(out3)
begin
$display("at time %7.3f, observed out3 = %b", $realtime,out3);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O211A_1_V
`define SKY130_FD_SC_MS__O211A_1_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o211a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o211a_1 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o211a_1 (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O211A_1_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon May 08 23:35:06 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_vga_test/zed_vga_test.srcs/sources_1/bd/system/ip/system_zed_vga_0_0/system_zed_vga_0_0_stub.v
// Design : system_zed_vga_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "zed_vga,Vivado 2016.4" *)
module system_zed_vga_0_0(clk, active, rgb565, vga_r, vga_g, vga_b)
/* synthesis syn_black_box black_box_pad_pin="clk,active,rgb565[15:0],vga_r[3:0],vga_g[3:0],vga_b[3:0]" */;
input clk;
input active;
input [15:0]rgb565;
output [3:0]vga_r;
output [3:0]vga_g;
output [3:0]vga_b;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EBUFN_FUNCTIONAL_V
`define SKY130_FD_SC_MS__EBUFN_FUNCTIONAL_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__ebufn (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Name Output Other arguments
bufif0 bufif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__EBUFN_FUNCTIONAL_V |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ba
//
// Generated
// by: wig
// on: Thu Apr 26 09:40:09 2007
// cmd: /home/wig/work/MIX/mix_0.pl -nodelta ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ba.v,v 1.2 2007/04/26 15:45:52 wig Exp $
// $Date: 2007/04/26 15:45:52 $
// $Log: ent_ba.v,v $
// Revision 1.2 2007/04/26 15:45:52 wig
// Updated testcase files
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.108 2007/04/26 06:35:17 wig Exp
//
// Generator: mix_0.pl Revision: 1.47 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_ba
//
// No user `defines in this module
module ent_ba
//
// Generated Module inst_ba
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of ent_ba
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRTP_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__DLRTP_PP_BLACKBOX_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlrtp (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRTP_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
module controler
#(parameter WIDTH = 32, CLK_CH = 25, TIME_SCORE = 1)
(
input power, input start_pause, input weight_ch, input mode_ch, input clk_src,
output start_pause_light,output [2:0]weight_ch_light, output power_light,
output water_in_light, output reg washing_light, output reg rinsing_light,
output reg dewatering_light, output water_out_light,
output [7:0]anodes, output [7:0]cnodes, output reg [2:0]state,
output alarm
);
reg [2:0]nextstate;
reg [2:0]water_level; //water level in machine
reg power_control; //power_control and power make up true_power
reg start_pause_light_two; // start_pause_light_two and start_pause make up start_pause_light
reg [1:0]washing_machine_running;// report washing machine's running state
reg [2:0]w_r_d_start, w_r_d; // w_r_d_start control submodules' start and reset, w_r_d report current mode
reg [31:0]mode_count, sum_count; // mode_count report current mode time, sum_count report totsl time
wire real_p_clk, real_s_clk, real_c_clk; // asynchronous change to synchronization
wire [2:0]weight_ch_light_mode; // report weight selector
wire true_power;
wire [7:0]ianodes, icnodes; // display water_level, sum_count, mode_count
wire [2:0]rinsing_state;
wire mode_ch_push, weight_ch_push; // report mode button or weight button push
wire water_in_light_wash, water_in_light_rinse; // make up water_in_light
wire water_out_light_rinse, water_out_light_dewater; // make up watre_out_light
wire dewatering_light_rinse, dewatering_light_dewater; // make up dewater_light
wire washing_light_wash, rinsing_light_rinse;
wire [2:0]w_r_d_end; // sign from sunmodule, control controller's state change
wire [2:0] w_r_d_change; // weight information from submodule selector_mode
wire [31:0]clk; // produce by tick_divider
wire [2:0]wash_water_level, rinse_water_level, dewater_water_level; // make up water_level
wire [31:0]wash_count, rinse_count, dewater_count; // report submodules' time
parameter mode_ch_state=0, wash_state=1, rinse_state=2, dewater_state=3, w_r_d_end_state=4;
integer count;
// choose mode when start_pause is pause
selector_mode #(0,5,CLK_CH) MODE_SEL (.clk(clk),
.switch_power(true_power),
.switch_en(start_pause), //start_pause control, not start_pause_light
.sig_change(mode_ch),
.push(mode_ch_push),
.washing_machine_running(washing_machine_running),
.sel_value(w_r_d_change)
);
//accept clock source, return clock array
tick_divider TICK_DEVIDER (.clk_src(clk_src),
.clk_group(clk)
);
//choose weight when start_pause is pause
selector_mode #(2,5,CLK_CH) WEIGHT_SEL (.clk(clk),
.switch_power(true_power),
.switch_en(start_pause),
.sig_change(weight_ch),
.push(weight_ch_push),
.washing_machine_running(washing_machine_running),
.sel_value(weight_ch_light_mode)
);
// wash mode run when start sign nd power are both true
wash_mode #(WIDTH, CLK_CH, TIME_SCORE) WASH_MODE (.power(true_power),
.start(start_pause_light),
.weight(weight_ch_light),
.clk(clk),
.wash_start(w_r_d_start[2]), // start sign
.water_in_light(water_in_light_wash),
.washing_light(washing_light_wash),
.wash_end_sign(w_r_d_end[2]),
.water_level(wash_water_level),
.wash_count(wash_count)
);
// rinse mode run when start sign nd power are both true
rinse_mode #(WIDTH, CLK_CH, TIME_SCORE) RINSE_MODE (.power(true_power),
.start(start_pause_light),
.clk(clk),
.weight(weight_ch_light),
.rinse_start(w_r_d_start[1]),
.rinsing_light(rinsing_light_rinse),
.rinse_end_sign(w_r_d_end[1]),
.water_in_light(water_in_light_rinse),
.water_out_light(water_out_light_rinse),
.dewatering_light(dewatering_light_rinse),
.water_level(rinse_water_level),
.rinse_count(rinse_count),
.state(rinsing_state)
);
// dewater mode run when start sign nd power are both true
dewater_mode #(WIDTH, CLK_CH, TIME_SCORE) DEWATER_MODE (.power(true_power),
.start(start_pause_light),
.clk(clk),
.weight(weight_ch_light),
.dewater_start(w_r_d_start[0]),
.dewatering_light(dewatering_light_dewater),
.dewater_end_sign(w_r_d_end[0]),
.water_out_light(water_out_light_dewater),
.water_level(dewater_water_level),
.dewater_count(dewater_count)
);
//display sum_count, mode_count, water_level
time_displayer TIME_DISPLAYER (.clk_src(clk[15]),
.sec_data({{29{1'b0}}, water_level}),
.min_data(mode_count),
.hour_data(sum_count),
.anodes(ianodes),
.cnodes(icnodes)
);
// ring when machine run over or each botton is pushed
ring RING (
.clk_src(clk),
.power(true_power),
.weight_ch(weight_ch),
.mode_ch(mode_ch),
.w_r_d_end(w_r_d_end),
.alarm(alarm)
);
initial begin
state <= mode_ch_state;
nextstate <= mode_ch_state;
start_pause_light_two <= 1'b1; //make start light on when start_pause on
w_r_d <= 3'b111; // initial mode
power_control <= 1'b1; // make true_power on when power on
water_level <= 3'b000; // initial water level
w_r_d_start <= {3{1'b0}}; // all mode off
washing_machine_running <= 2'b00; // initial machine's state
mode_count = 0;
sum_count = 0;
end
//water_in_light
assign water_in_light = (state == wash_state) ? water_in_light_wash : water_in_light_rinse;
assign water_out_light = (state == rinse_state) ? water_out_light_rinse : water_out_light_dewater;
assign true_power = power & power_control;
assign anodes = true_power ? ianodes : {8{1'b1}};
assign cnodes = true_power ? icnodes : {8{1'b1}};
assign start_pause_light = true_power ? (start_pause & start_pause_light_two) : 1'b0;
assign power_light = true_power;
assign weight_ch_light = true_power ? weight_ch_light_mode : 3'b000;
//change w_r_d_change which from selector mode to w_r_d
// problem : w_r_d auto change
always @(w_r_d_change or true_power) begin
if(true_power) begin
if(w_r_d_change == 0) begin w_r_d = 7; end
else if(w_r_d_change == 1) begin w_r_d = 4; end
else if(w_r_d_change == 2) begin w_r_d = 6; end
else if(w_r_d_change == 3) begin w_r_d = 2; end
else if(w_r_d_change == 4) begin w_r_d = 3; end
else if(w_r_d_change == 5) begin w_r_d = 1; end
end
else if(!true_power) begin
w_r_d = 3'b111;
end
end
//control water_level, all lights, sum_count, mode_count
always @(posedge clk[0])
if(true_power)
begin
case(state)
mode_ch_state: begin
water_level = 3'b0;
washing_light = w_r_d[2];
rinsing_light = w_r_d[1];
dewatering_light = w_r_d[0];
start_pause_light_two = 1'b1;
sum_count = w_r_d[2] * 4 * {{29{1'b0}},weight_ch_light} + w_r_d[1] * 5 * {{29{1'b0}},weight_ch_light} + w_r_d[0] * 2 * {{29{1'b0}},weight_ch_light};
if(w_r_d[2]) mode_count = w_r_d[2] * 4 * {{29{1'b0}},weight_ch_light};
else if(w_r_d[1]) mode_count = w_r_d[1] * 5 * {{29{1'b0}},weight_ch_light};
else if(w_r_d[0]) mode_count = w_r_d[0] * 2 * {{29{1'b0}},weight_ch_light};
else mode_count = 0;
end
wash_state: begin
water_level = wash_water_level;
rinsing_light = w_r_d[1];
dewatering_light = w_r_d[0];
washing_light = washing_light_wash;
sum_count = wash_count + w_r_d[1] * 5 * {{29{1'b0}},weight_ch_light} + w_r_d[0] * 2 * {{29{1'b0}},weight_ch_light};
mode_count = wash_count;
end
rinse_state: begin
water_level = rinse_water_level;
washing_light = 1'b0;
if(rinsing_state == 1) begin dewatering_light = dewatering_light_rinse; end
else begin dewatering_light = w_r_d[0]; end
rinsing_light = rinsing_light_rinse;
sum_count = rinse_count + w_r_d[0] * 2 * {{29{1'b0}},weight_ch_light};
mode_count = rinse_count;
end
dewater_state: begin
water_level = dewater_water_level;
washing_light = 1'b0;
rinsing_light = 1'b0;
dewatering_light = dewatering_light_dewater;
sum_count = dewater_count;
mode_count = dewater_count;
end
w_r_d_end_state: begin
sum_count = 0;
mode_count = 0;
water_level = 0;
washing_light = 1'b1;
rinsing_light = 1'b1;
dewatering_light = 1'b1;
start_pause_light_two = 1'b0;
end
endcase
end else begin
sum_count = 0;
mode_count = 0;
water_level = 0;
washing_light = 0;
rinsing_light = 0;
dewatering_light = 0;
start_pause_light_two = 1'b1;
end
// state change
always @(posedge clk[0])
if(true_power & start_pause_light) begin
state <= nextstate;
end
// change when mode or weight botton is pushed
else if(true_power && (mode_ch_push || weight_ch_push)) state = nextstate;
else if(!true_power) begin
state <= mode_ch_state;
end
//count ten seconds
assign real_p_clk = true_power ? clk[CLK_CH] : power;
always @(posedge real_p_clk)
begin
if(true_power) begin
if(state == 4) count = count + 1;
else count = 0;
if(count == 10) power_control = 0;
end
else if(power) begin count = 0; power_control = 1; end
end
// control submodules start
always @(state or true_power or start_pause_light) //moore
if(true_power & start_pause_light) begin
case(state)
mode_ch_state: begin w_r_d_start = 3'b000; end
wash_state: begin w_r_d_start = 3'b100; end
rinse_state: begin w_r_d_start = 3'b010; end
dewater_state: begin w_r_d_start = 3'b001; end
w_r_d_end_state: begin w_r_d_start = 3'b000; end
endcase
end
else if(!true_power) begin
w_r_d_start <= 3'b000;
end
//washing machine running flag
always @(state or true_power) //moore
if(true_power) begin
case(state)
mode_ch_state: begin washing_machine_running = 2'b00; end
wash_state: begin washing_machine_running = 2'b01; end
rinse_state: begin washing_machine_running = 2'b01; end
dewater_state: begin washing_machine_running = 2'b01; end
w_r_d_end_state: begin washing_machine_running = 2'b10; end
endcase
end
else if(!true_power) begin
washing_machine_running <= 2'b00;
end
// nextstate change
always @(w_r_d_end or w_r_d or true_power or mode_ch_push or weight_ch_push)
if(true_power) begin
case(state)
mode_ch_state: begin
if(mode_ch_push || weight_ch_push) nextstate = mode_ch_state;
else if(w_r_d[2]) begin //w_r_d contains wash
nextstate = wash_state;
end
else if(!w_r_d[2] & w_r_d[1]) begin
nextstate = rinse_state;
end
else if(w_r_d == 1) begin
nextstate = dewater_state;
end
else nextstate = mode_ch_state;
end
wash_state: begin
if(mode_ch_push || weight_ch_push) nextstate = mode_ch_state;
else if(w_r_d_end[2] & w_r_d[1]) begin
nextstate = rinse_state;
end
else if(w_r_d_end[2] & !w_r_d[1] & w_r_d[0]) begin
nextstate = dewater_state;
end
else if(w_r_d_end[2] & (w_r_d == 4)) nextstate = w_r_d_end_state;
else nextstate = wash_state;
end
rinse_state: begin
if(mode_ch_push || weight_ch_push) nextstate = mode_ch_state;
else if(w_r_d_end[1] & w_r_d[0]) begin
nextstate = dewater_state;
end
else if(w_r_d_end[1] & !w_r_d[0]) nextstate = w_r_d_end_state;
else nextstate = rinse_state;
end
dewater_state: begin
if(mode_ch_push || weight_ch_push) nextstate = mode_ch_state;
else if(w_r_d_end[0]) nextstate = w_r_d_end_state;
else nextstate = dewater_state;
end
w_r_d_end_state: begin
if(mode_ch_push || weight_ch_push) begin
nextstate = mode_ch_state;
end else begin
nextstate = w_r_d_end_state;
end
end
default : nextstate = mode_ch_state;
endcase
end
else nextstate = mode_ch_state;
endmodule
|
// -*- Mode: Verilog -*-
// Filename : test_00.v
// Description : Simple ADXL362 Test Case to bring environment to life
// Author : Philip Tracton
// Created On : Thu Jun 23 11:36:12 2016
// Last Modified By: Philip Tracton
// Last Modified On: Thu Jun 23 11:36:12 2016
// Update Count : 0
// Status : Unknown, Use with caution!
`include "simulation_includes.vh"
module test_case ();
//
// Test Configuration
// These parameters need to be set for each test case
//
parameter simulation_name = "fifo_00";
parameter number_of_tests = 32;
defparam `ADXL362_ACCELEROMETER.XDATA_FILE = "accelerometer_00_xdata.txt";
defparam `ADXL362_ACCELEROMETER.YDATA_FILE = "accelerometer_00_ydata.txt";
defparam `ADXL362_ACCELEROMETER.ZDATA_FILE = "accelerometer_00_zdata.txt";
defparam `ADXL362_ACCELEROMETER.TEMPERATURE_FILE = "accelerometer_00_temperature_data.txt";
reg err;
reg [31:0] data_out = 0;
integer i;
reg [(16*7):0] read_mem = 0;
initial begin
$display("FIFO 00 Case");
`TB.master_bfm.reset;
@(posedge `WB_RST);
@(negedge `WB_RST);
@(posedge `WB_CLK);
@(negedge `ADXL362_RESET);
`SIMPLE_SPI_INIT;
//
// Set FIFO Mode to Streaming
// Turn on Temperature FIFO
// Enable FIFO Streaming Mode
//
`ADXL362_WRITE_REGISTER(`ADXL362_FIFO_CONTROL, 8'h06);
`ADXL362_READ_REGISTER(`ADXL362_STATUS, data_out);
while (data_out[9] ==0) begin
repeat(100) @(posedge `WB_CLK);
`ADXL362_READ_REGISTER(`ADXL362_STATUS, data_out);
end
repeat(10) @(posedge `WB_CLK);
`ADXL362_READ_BURST_FIFO(read_mem, 8);
`TEST_COMPARE("FIFO 0", 8'h01, read_mem[7:0]);
`TEST_COMPARE("FIFO 1", 8'h00, read_mem[15:8]);
`TEST_COMPARE("FIFO 2", 8'h11, read_mem[23:16]);
`TEST_COMPARE("FIFO 3", 8'h40, read_mem[31:24]);
`TEST_COMPARE("FIFO 4", 8'hF1, read_mem[39:32]);
`TEST_COMPARE("FIFO 5", 8'h80, read_mem[47:40]);
`TEST_COMPARE("FIFO 6", 8'h47, read_mem[55:48]);
`TEST_COMPARE("FIFO 7", 8'hC0, read_mem[63:56]);
repeat(100) @(posedge `WB_CLK);
`ADXL362_READ_REGISTER(`ADXL362_STATUS, data_out);
while (data_out[9] ==0) begin
repeat(100) @(posedge `WB_CLK);
`ADXL362_READ_REGISTER(`ADXL362_STATUS, data_out);
end
repeat(10) @(posedge `WB_CLK);
`ADXL362_READ_BURST_FIFO(read_mem, 8);
`TEST_COMPARE("FIFO 0", 8'h02, read_mem[7:0]);
`TEST_COMPARE("FIFO 1", 8'h00, read_mem[15:8]);
`TEST_COMPARE("FIFO 2", 8'h12, read_mem[23:16]);
`TEST_COMPARE("FIFO 3", 8'h40, read_mem[31:24]);
`TEST_COMPARE("FIFO 4", 8'hF2, read_mem[39:32]);
`TEST_COMPARE("FIFO 5", 8'h80, read_mem[47:40]);
`TEST_COMPARE("FIFO 6", 8'h48, read_mem[55:48]);
`TEST_COMPARE("FIFO 7", 8'hC0, read_mem[63:56]);
repeat(100) @(posedge `WB_CLK);
`ADXL362_READ_REGISTER(`ADXL362_STATUS, data_out);
while (data_out[9] ==0) begin
repeat(100) @(posedge `WB_CLK);
`ADXL362_READ_REGISTER(`ADXL362_STATUS, data_out);
end
repeat(10) @(posedge `WB_CLK);
`ADXL362_READ_BURST_FIFO(read_mem, 8);
`TEST_COMPARE("FIFO 0", 8'h03, read_mem[7:0]);
`TEST_COMPARE("FIFO 1", 8'h00, read_mem[15:8]);
`TEST_COMPARE("FIFO 2", 8'h13, read_mem[23:16]);
`TEST_COMPARE("FIFO 3", 8'h40, read_mem[31:24]);
`TEST_COMPARE("FIFO 4", 8'hF3, read_mem[39:32]);
`TEST_COMPARE("FIFO 5", 8'h80, read_mem[47:40]);
`TEST_COMPARE("FIFO 6", 8'h49, read_mem[55:48]);
`TEST_COMPARE("FIFO 7", 8'hC0, read_mem[63:56]);
repeat(100) @(posedge `WB_CLK);
`ADXL362_READ_REGISTER(`ADXL362_STATUS, data_out);
while (data_out[9] ==0) begin
repeat(100) @(posedge `WB_CLK);
`ADXL362_READ_REGISTER(`ADXL362_STATUS, data_out);
end
repeat(10) @(posedge `WB_CLK);
`ADXL362_READ_BURST_FIFO(read_mem, 8);
`TEST_COMPARE("FIFO 0", 8'h04, read_mem[7:0]);
`TEST_COMPARE("FIFO 1", 8'h00, read_mem[15:8]);
`TEST_COMPARE("FIFO 2", 8'h14, read_mem[23:16]);
`TEST_COMPARE("FIFO 3", 8'h40, read_mem[31:24]);
`TEST_COMPARE("FIFO 4", 8'hF4, read_mem[39:32]);
`TEST_COMPARE("FIFO 5", 8'h80, read_mem[47:40]);
`TEST_COMPARE("FIFO 6", 8'h4A, read_mem[55:48]);
`TEST_COMPARE("FIFO 7", 8'hC0, read_mem[63:56]);
repeat(100) @(posedge `WB_CLK);
`TEST_COMPLETE;
end
endmodule // test_case
|
/*
* Milkymist VJ SoC fjmem flasher
* Copyright (C) 2010 Michael Walle
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module system(
input clk50,
/* flash */
output [23:0] flash_adr,
inout [15:0] flash_d,
output flash_oe_n,
output flash_we_n,
output flash_ce_n,
output flash_rst_n,
input flash_sts,
/* debug */
output led
);
/* clock and reset */
wire sys_rst;
wire sys_clk;
assign sys_clk = clk50;
assign sys_rst = 1'b0;
/* flash control pins */
assign flash_ce_n = 1'b0;
assign flash_rst_n = 1'b1;
/* debug */
wire fjmem_update;
reg [25:0] counter;
always @(posedge sys_clk)
counter <= counter + 1'd1;
assign led = counter[25] ^ fjmem_update;
fjmem #(
.adr_width(24)
) fjmem (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.flash_adr(flash_adr),
.flash_d(flash_d),
.flash_oe_n(flash_oe_n),
.flash_we_n(flash_we_n),
.fjmem_update(fjmem_update)
);
endmodule
|
`define WIDTH_P ? // unused for now...
module test_bsg;
import bsg_tag_pkg::bsg_tag_s;
// Enable VPD dump file
//
initial
begin
$vcdpluson;
$vcdplusmemon;
end
logic TCK,TDI,TMS;
localparam bsg_tag_els_lp = 4;
wire [bsg_tag_els_lp-1:0] bsg_recv_clocks;
genvar i;
for (i = 0; i < bsg_tag_els_lp; i=i+1)
begin: rof
bsg_nonsynth_clock_gen #(i+2) recv_clock(bsg_recv_clocks[i]);
end
// Config net configuration clock. We run it continuously
// but this is not necessary.
bsg_nonsynth_clock_gen #(100) cfg_clk_gen (TCK);
bsg_tag_s [bsg_tag_els_lp-1:0] clients_lo;
logic [bsg_tag_els_lp-1:0] clients_reset;
wire [bsg_tag_els_lp-1:0] clients_new;
wire [bsg_tag_els_lp-1:0][bsg_tag_els_lp*8+5-1:0] clients_data;
localparam payload_bits_lp = 7;
localparam max_payload_lp = (1 << payload_bits_lp)-1;
`declare_bsg_tag_header_s(bsg_tag_els_lp,payload_bits_lp)
// one master tag to connect to the clients
bsg_tag_master #(.els_p(bsg_tag_els_lp), .lg_width_p(payload_bits_lp)) btm
(.clk_i (TCK)
,.data_i (TDI)
,.en_i (TMS)
,.clients_r_o(clients_lo)
);
// stamp out a bunch of client tags
for (i = 0; i < bsg_tag_els_lp; i=i+1)
begin: rof2
bsg_tag_client #(.width_p(5+i*8)
,.default_p(i)
) btc
(.bsg_tag_i (clients_lo [i])
,.recv_clk_i (bsg_recv_clocks [i])
,.recv_reset_i (clients_reset [i])
,.recv_new_r_o (clients_new [i])
,.recv_data_r_o(clients_data [i][0+:5+i*8])
);
always @(clients_data[i])
begin
$display("## client %d data = %b new = %b",i,clients_data[i],clients_new[i]);
end
end
bsg_tag_header_s send_me;
wire [5+3*8-1:0] val = 29'b0_1111_1001_0110_0011_1100_1010_0101;
initial
begin
$display("## sim start");
send_me.nodeID = 3;
send_me.data_not_reset = 0;
send_me.len = max_payload_lp;
@(negedge TCK);
TDI = 1'b0;
TMS = 1'b1;
@(negedge TCK);
clients_reset[0] = 1;
// clear reset counter going
@(negedge TCK);
TDI = 1'b1;
clients_reset[0] = 0;
// start reset counter going
@(negedge TCK);
TDI = 1'b0;
// trigger bsg_tag_master reset
for (integer i = 0; i < `bsg_tag_reset_len(bsg_tag_els_lp,payload_bits_lp); i++)
@(posedge TCK);
// packet bit
@(negedge TCK);
TDI = 1'b1;
// transmit header
for (integer i = 0; i < $bits(send_me); i=i+1)
begin
@(negedge TCK);
TDI = send_me[i];
end
send_me.data_not_reset = 1;
send_me.len = 29;
// transmit reset payload
for (integer i = 0; i < max_payload_lp; i=i+1)
begin
@(negedge TCK);
TDI = 1'b1;
end
// packet bit
@(negedge TCK);
TDI = 1'b1;
// transmit header
for (integer i = 0; i < $bits(send_me); i=i+1)
begin
@(negedge TCK);
TDI = send_me[i];
end
// transmit payload
for (integer i = 0; i < 29; i=i+1)
begin
@(negedge TCK);
TDI = val[i];
end
// packet bit
@(negedge TCK);
TDI = 1'b1;
// transmit header
for (integer i = 0; i < $bits(send_me); i=i+1)
begin
@(negedge TCK);
TDI = send_me[i];
end
// transmit payload
for (integer i = 0; i < 29; i=i+1)
begin
@(negedge TCK);
TDI = val[i];
end
// packet bit
@(negedge TCK);
TDI = 1'b1;
send_me.nodeID = 1;
// transmit header
for (integer i = 0; i < $bits(send_me); i=i+1)
begin
@(negedge TCK);
TDI = send_me[i];
end
// transmit payload
for (integer i = 0; i < 29; i=i+1)
begin
@(negedge TCK);
TDI = val[i];
end
@(negedge TCK);
TDI = 1'b0;
@(negedge TCK);
TDI = 1'b0;
@(negedge TCK);
TDI = 1'b0;
@(negedge TCK);
TDI = 1'b0;
@(negedge TCK);
TDI = 1'b0;
$finish;
end
endmodule
|
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
// Date : Mon Sep 16 06:23:47 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top design_1_rst_ps7_0_50M_0 -prefix
// design_1_rst_ps7_0_50M_0_ design_1_rst_ps7_0_50M_0_stub.v
// Design : design_1_rst_ps7_0_50M_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "proc_sys_reset,Vivado 2018.2" *)
module design_1_rst_ps7_0_50M_0(slowest_sync_clk, ext_reset_in, aux_reset_in,
mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset,
interconnect_aresetn, peripheral_aresetn)
/* synthesis syn_black_box black_box_pad_pin="slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */;
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
output [0:0]bus_struct_reset;
output [0:0]peripheral_reset;
output [0:0]interconnect_aresetn;
output [0:0]peripheral_aresetn;
endmodule
|
//Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
//Date : Tue Feb 14 01:36:24 2017
//Host : TheMosass-PC running 64-bit major release (build 9200)
//Command : generate_target design_1_wrapper.bd
//Design : design_1_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module design_1_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
btns_4bits_tri_i,
leds_4bits_tri_io,
sws_4bits_tri_i);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
input [3:0]btns_4bits_tri_i;
inout [3:0]leds_4bits_tri_io;
input [3:0]sws_4bits_tri_i;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire [3:0]btns_4bits_tri_i;
wire [0:0]leds_4bits_tri_i_0;
wire [1:1]leds_4bits_tri_i_1;
wire [2:2]leds_4bits_tri_i_2;
wire [3:3]leds_4bits_tri_i_3;
wire [0:0]leds_4bits_tri_io_0;
wire [1:1]leds_4bits_tri_io_1;
wire [2:2]leds_4bits_tri_io_2;
wire [3:3]leds_4bits_tri_io_3;
wire [0:0]leds_4bits_tri_o_0;
wire [1:1]leds_4bits_tri_o_1;
wire [2:2]leds_4bits_tri_o_2;
wire [3:3]leds_4bits_tri_o_3;
wire [0:0]leds_4bits_tri_t_0;
wire [1:1]leds_4bits_tri_t_1;
wire [2:2]leds_4bits_tri_t_2;
wire [3:3]leds_4bits_tri_t_3;
wire [3:0]sws_4bits_tri_i;
design_1 design_1_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.btns_4bits_tri_i(btns_4bits_tri_i),
.leds_4bits_tri_i({leds_4bits_tri_i_3,leds_4bits_tri_i_2,leds_4bits_tri_i_1,leds_4bits_tri_i_0}),
.leds_4bits_tri_o({leds_4bits_tri_o_3,leds_4bits_tri_o_2,leds_4bits_tri_o_1,leds_4bits_tri_o_0}),
.leds_4bits_tri_t({leds_4bits_tri_t_3,leds_4bits_tri_t_2,leds_4bits_tri_t_1,leds_4bits_tri_t_0}),
.sws_4bits_tri_i(sws_4bits_tri_i));
IOBUF leds_4bits_tri_iobuf_0
(.I(leds_4bits_tri_o_0),
.IO(leds_4bits_tri_io[0]),
.O(leds_4bits_tri_i_0),
.T(leds_4bits_tri_t_0));
IOBUF leds_4bits_tri_iobuf_1
(.I(leds_4bits_tri_o_1),
.IO(leds_4bits_tri_io[1]),
.O(leds_4bits_tri_i_1),
.T(leds_4bits_tri_t_1));
IOBUF leds_4bits_tri_iobuf_2
(.I(leds_4bits_tri_o_2),
.IO(leds_4bits_tri_io[2]),
.O(leds_4bits_tri_i_2),
.T(leds_4bits_tri_t_2));
IOBUF leds_4bits_tri_iobuf_3
(.I(leds_4bits_tri_o_3),
.IO(leds_4bits_tri_io[3]),
.O(leds_4bits_tri_i_3),
.T(leds_4bits_tri_t_3));
endmodule
|
module BitonicSortX4 # (
parameter DSIZE = 18,
parameter OFFSET = 8
)(
input [DSIZE-1:0] a0,
input [DSIZE-1:0] a1,
input [DSIZE-1:0] a2,
input [DSIZE-1:0] a3,
output wire [DSIZE-1:0] sort0,
output wire [DSIZE-1:0] sort1,
output wire [DSIZE-1:0] sort2,
output wire [DSIZE-1:0] sort3
);
wire [DSIZE-1:0] sort0_0;
wire [DSIZE-1:0] sort0_1;
wire [DSIZE-1:0] sort1_0;
wire [DSIZE-1:0] sort1_1;
// half-clean
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst0 (
.a(a0),
.b(a2),
.sort0(sort0_0),
.sort1(sort0_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst1 (
.a(a1),
.b(a3),
.sort0(sort1_0),
.sort1(sort1_1)
);
// divide sort
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst2 (
.a(sort0_0),
.b(sort1_0),
.sort0(sort0),
.sort1(sort1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst3 (
.a(sort0_1),
.b(sort1_1),
.sort0(sort2),
.sort1(sort3)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A2BB2O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__A2BB2O_BEHAVIORAL_PP_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a2bb2o (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
or or0 (or0_out_X , nor0_out, and0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A2BB2O_BEHAVIORAL_PP_V |
/*
-- ============================================================================
-- FILE NAME : bus_master_mux.v
-- DESCRIPTION : oX}X^}`vNT
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito VKì¬
-- ============================================================================
*/
/********** ¤Êwb_t@C **********/
`include "nettype.h"
`include "stddef.h"
`include "global_config.h"
/********** ÂÊwb_t@C **********/
`include "bus.h"
/********** W
[ **********/
module bus_master_mux (
/********** oX}X^M **********/
// oX}X^0Ô
input wire [`WordAddrBus] m0_addr, // AhX
input wire m0_as_, // AhXXg[u
input wire m0_rw, // ÇÝ^«
input wire [`WordDataBus] m0_wr_data, // «Ýf[^
input wire m0_grnt_, // oXOg
// oX}X^1Ô
input wire [`WordAddrBus] m1_addr, // AhX
input wire m1_as_, // AhXXg[u
input wire m1_rw, // ÇÝ^«
input wire [`WordDataBus] m1_wr_data, // «Ýf[^
input wire m1_grnt_, // oXOg
// oX}X^2Ô
input wire [`WordAddrBus] m2_addr, // AhX
input wire m2_as_, // AhXXg[u
input wire m2_rw, // ÇÝ^«
input wire [`WordDataBus] m2_wr_data, // «Ýf[^
input wire m2_grnt_, // oXOg
// oX}X^3Ô
input wire [`WordAddrBus] m3_addr, // AhX
input wire m3_as_, // AhXXg[u
input wire m3_rw, // ÇÝ^«
input wire [`WordDataBus] m3_wr_data, // «Ýf[^
input wire m3_grnt_, // oXOg
/********** oXX[u¤ÊM **********/
output reg [`WordAddrBus] s_addr, // AhX
output reg s_as_, // AhXXg[u
output reg s_rw, // ÇÝ^«
output reg [`WordDataBus] s_wr_data // «Ýf[^
);
/********** oX}X^}`vNT **********/
always @(*) begin
/* oX ðÁÄ¢é}X^ÌIð */
if (m0_grnt_ == `ENABLE_) begin // oX}X^0Ô
s_addr = m0_addr;
s_as_ = m0_as_;
s_rw = m0_rw;
s_wr_data = m0_wr_data;
end else if (m1_grnt_ == `ENABLE_) begin // oX}X^0Ô
s_addr = m1_addr;
s_as_ = m1_as_;
s_rw = m1_rw;
s_wr_data = m1_wr_data;
end else if (m2_grnt_ == `ENABLE_) begin // oX}X^0Ô
s_addr = m2_addr;
s_as_ = m2_as_;
s_rw = m2_rw;
s_wr_data = m2_wr_data;
end else if (m3_grnt_ == `ENABLE_) begin // oX}X^0Ô
s_addr = m3_addr;
s_as_ = m3_as_;
s_rw = m3_rw;
s_wr_data = m3_wr_data;
end else begin // ftHgl
s_addr = `WORD_ADDR_W'h0;
s_as_ = `DISABLE_;
s_rw = `READ;
s_wr_data = `WORD_DATA_W'h0;
end
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information of Xilinx, Inc.
// and is protected under U.S. and international copyright and other
// intellectual property laws.
//
// DISCLAIMER
//
// This disclaimer is not a license and does not grant any rights to the
// materials distributed herewith. Except as otherwise provided in a valid
// license issued to you by Xilinx, and to the maximum extent permitted by
// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
// and (2) Xilinx shall not be liable (whether in contract or tort, including
// negligence, or under any other theory of liability) for any loss or damage
// of any kind or nature related to, arising under or in connection with these
// materials, including for any direct, or any indirect, special, incidental,
// or consequential loss or damage (including loss of data, profits, goodwill,
// or any type of loss or damage suffered as a result of any action brought by
// a third party) even if such damage or loss was reasonably foreseeable or
// Xilinx had been advised of the possibility of the same.
//
// CRITICAL APPLICATIONS
//
// Xilinx products are not designed or intended to be fail-safe, or for use in
// any application requiring fail-safe performance, such as life-support or
// safety devices or systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any other
// applications that could lead to death, personal injury, or severe property
// or environmental damage (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and liability of any use of
// Xilinx products in Critical Applications, subject only to applicable laws
// and regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
// AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : pcie_app_v6.v
//--
//-- Description: PCI Express Endpoint sample application
//-- design.
//--
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
`include "CM_HEAD.v"
`define PCI_EXP_EP_OUI 24'h000A35
`define PCI_EXP_EP_DSN_1 {{8'h1},`PCI_EXP_EP_OUI}
`define PCI_EXP_EP_DSN_2 32'h00000001
module pcie_app_v6
(
input trn_clk,
input trn_reset_n,
input trn_lnk_up_n,
// Tx
input [5:0] trn_tbuf_av,
input trn_tcfg_req_n,
input trn_terr_drop_n,
input trn_tdst_rdy_n,
output [127:0] trn_td,
output [1:0] trn_trem_n,
output trn_tsof_n,
output trn_teof_n,
output trn_tsrc_rdy_n,
output trn_tsrc_dsc_n,
output trn_terrfwd_n,
output trn_tcfg_gnt_n,
output trn_tstr_n,
// Rx
input [127:0] trn_rd,
input [1:0] trn_rrem_n,
input trn_rsof_n,
input trn_reof_n,
input trn_rsrc_rdy_n,
input trn_rsrc_dsc_n,
input trn_rerrfwd_n,
input [6:0] trn_rbar_hit_n,
output trn_rdst_rdy_n,
output trn_rnp_ok_n,
// Flow Control
input [11:0] trn_fc_cpld,
input [7:0] trn_fc_cplh,
input [11:0] trn_fc_npd,
input [7:0] trn_fc_nph,
input [11:0] trn_fc_pd,
input [7:0] trn_fc_ph,
output [2:0] trn_fc_sel,
input CMGFTL_cmd_fifo_full_i,
input CMGFTL_cmd_fifo_almost_full_i,
output CMGFTL_cmd_fifo_wr_en_o,
output [127:0] CMGFTL_cmd_fifo_data_o,
input FTLCMG_cmd_fifo_empty_i,
input FTLCMG_cmd_fifo_almost_empty_i,
output FTLCMG_cmd_fifo_rd_en_o,
input [127:0] FTLCMG_cmd_fifo_data_i,
input RX_data_fifo_full_i,
input RX_data_fifo_almost_full_i,
output RX_data_fifo_wr_en_o,
output [127:0] RX_data_fifo_data_o,
input RX_data_fifo_av_i,
input TX_data_fifo_empty_i,
input TX_data_fifo_almost_empty_i,
output TX_data_fifo_rd_en_o,
input [127:0] TX_data_fifo_data_i,
input [31:0] cfg_do,
input cfg_rd_wr_done_n,
output [31:0] cfg_di,
output [3:0] cfg_byte_en_n,
output [9:0] cfg_dwaddr,
output cfg_wr_en_n,
output cfg_rd_en_n,
output cfg_err_cor_n,
output cfg_err_ur_n,
output cfg_err_ecrc_n,
output cfg_err_cpl_timeout_n,
output cfg_err_cpl_abort_n,
output cfg_err_cpl_unexpect_n,
output cfg_err_posted_n,
output cfg_err_locked_n,
output [47:0] cfg_err_tlp_cpl_header,
input cfg_err_cpl_rdy_n,
output cfg_interrupt_n,
input cfg_interrupt_rdy_n,
output cfg_interrupt_assert_n,
output [7:0] cfg_interrupt_di,
input [7:0] cfg_interrupt_do,
input [2:0] cfg_interrupt_mmenable,
input cfg_interrupt_msienable,
input cfg_interrupt_msixenable,
input cfg_interrupt_msixfm,
output cfg_turnoff_ok_n,
input cfg_to_turnoff_n,
output cfg_trn_pending_n,
output cfg_pm_wake_n,
input [7:0] cfg_bus_number,
input [4:0] cfg_device_number,
input [2:0] cfg_function_number,
input [15:0] cfg_status,
input [15:0] cfg_command,
input [15:0] cfg_dstatus,
input [15:0] cfg_dcommand,
input [15:0] cfg_lstatus,
input [15:0] cfg_lcommand,
input [15:0] cfg_dcommand2,
input [2:0] cfg_pcie_link_state_n,
output [1:0] pl_directed_link_change,
input [5:0] pl_ltssm_state,
output [1:0] pl_directed_link_width,
output pl_directed_link_speed,
output pl_directed_link_auton,
output pl_upstream_prefer_deemph,
input [1:0] pl_sel_link_width,
input pl_sel_link_rate,
input pl_link_gen2_capable,
input pl_link_partner_gen2_supported,
input [2:0] pl_initial_link_width,
input pl_link_upcfg_capable,
input [1:0] pl_lane_reversal_mode,
input pl_received_hot_rst,
output [63:0] cfg_dsn
);
/*************ouyang***************/
//response queue interface
wire response_queue_empty;
wire [31:0] response_queue_data;
wire response_queue_rd_en ;//read enable signal for response queue
//msix interface
wire [31:0] msg_lower_addr;
wire [31:0] msg_upper_addr;
wire [31:0] msg_data;
// the base addr for response queue
wire [31:0] response_queue_addr;
//count enable for response queue offset
wire response_queue_addr_offset_cnt_en;
wire interrupt_block;
wire [31:0] response_queue_cur_offset_reg;
wire [10:0] response_queue_addr_offset;
/**********************************/
wire [1:0] trn_trem;
wire [1:0] trn_rrem;
//
// Core input tie-offs
//
assign trn_fc_sel = 3'b0;
assign trn_rnp_ok_n = 1'b0;
assign trn_terrfwd_n = 1'b1;
assign trn_tcfg_gnt_n = 1'b0;
assign trn_tecrc_gen_n = 1'b1;
assign cfg_err_cor_n = 1'b1;
assign cfg_err_ur_n = 1'b1;
assign cfg_err_ecrc_n = 1'b1;
assign cfg_err_cpl_timeout_n = 1'b1;
assign cfg_err_cpl_abort_n = 1'b1;
assign cfg_err_cpl_unexpect_n = 1'b1;
assign cfg_err_posted_n = 1'b0;
assign cfg_err_locked_n = 1'b1;
assign cfg_pm_wake_n = 1'b1;
assign cfg_trn_pending_n = 1'b1;
assign trn_tstr_n = 1'b0;
assign cfg_err_tlp_cpl_header = 47'h0;
assign cfg_di = 0;
assign cfg_byte_en_n = 4'hf;
assign cfg_wr_en_n = 1;
assign cfg_dsn = {`PCI_EXP_EP_DSN_2, `PCI_EXP_EP_DSN_1};
`ifndef PCIE2_0
assign pl_directed_link_change = 0;
assign pl_directed_link_width = 0;
assign pl_directed_link_speed = 0;
assign pl_directed_link_auton = 0;
assign pl_upstream_prefer_deemph = 1'b1;
`endif
//
//BMD
//
wire cfg_ext_tag_en = cfg_dcommand[8];
wire [5:0] cfg_neg_max_lnk_width = cfg_lstatus[9:4];
wire [3:0] cfg_neg_max_lnk_speed = cfg_lstatus[3:0];
wire [2:0] cfg_prg_max_payload_size = cfg_dcommand[7:5];
wire [2:0] cfg_max_rd_req_size = cfg_dcommand[14:12];
wire cfg_rd_comp_bound = cfg_lcommand[3];
wire [15:0] cfg_completer_id = { cfg_bus_number, cfg_device_number, cfg_function_number };
wire cfg_bus_mstr_enable = cfg_command[2];
wire trn_tdst_dsc_n = 1'b1;
wire en;
wire [6:0] bar0_addr;
wire bar0_wr_en;
wire [7:0] bar0_wr_be;
wire bar0_busy;
wire [31:0] bar0_rd_d;
wire [3:0] bar0_rd_be;
wire [31:0] bar0_wr_d;
wire bar1_wr_en1;
wire [6:0] bar1_addr1;
wire [3:0] bar1_be1;
wire [31:0] bar1_wr_d1;
wire bar1_wr_ack1_n;
wire bar1_wr_en2;
wire [6:0] bar1_addr2;
wire [3:0] bar1_be2;
wire [31:0] bar1_wr_d2;
wire bar1_wr_ack2_n;
wire bar1_wr_en3;
wire [6:0] bar1_addr3;
wire [3:0] bar1_be3;
wire [31:0] bar1_wr_d3;
wire bar1_wr_ack3_n;
wire bar1_arbiter_busy;
wire bar1_wr_busy;
wire [127:0] rdata;
wire rdata_rd_en;
wire rdata_fifo_empty;
//wire [127:0] tdata;
wire tdata_wr_en;
wire tdata_fifo_full;
wire mwr_start;
wire mwr_done;
wire mrd_start;
wire mrd_done;
wire req_compl;
wire compl_done;
wire cpld_malformed;
wire dma_rd_req_flag;
wire rdata_wr_en;
wire req_queue_full;
wire [63:0] dma_rd_q_rd_data;
wire dma_rd_q_empty;
reg dma_rd_q_rd_en;
reg dma_rd_q_sw_delay;
reg [15:0] dma_rd_xfer_cnt;
reg dma_rd_xfer_done;
wire dma_rd_xfer_done_ack;
reg [63:0] dma_rd_done_entry;
reg dma_rd_xfer_done_ack_q;
reg [31:0] cpld_rcv_data_size;
always @ ( posedge trn_clk ) begin
if( !trn_reset_n || trn_lnk_up_n || !en ) begin
dma_rd_q_rd_en <= 1'b0;
dma_rd_q_sw_delay <= 1'b0;
dma_rd_xfer_cnt <= 16'b0;
dma_rd_xfer_done <= 1'b0;
dma_rd_done_entry <= 64'b0;
cpld_rcv_data_size <= 32'b0;
dma_rd_xfer_done_ack_q <= 1'b0;
end else begin
dma_rd_q_rd_en <= 1'b0;
dma_rd_xfer_done_ack_q <= dma_rd_xfer_done_ack;
if( dma_rd_xfer_done ) begin
if( dma_rd_xfer_done_ack_q && !dma_rd_xfer_done_ack ) begin
dma_rd_q_sw_delay <= 1'b0;
dma_rd_xfer_done <= 1'b0;
end
end else
dma_rd_q_sw_delay <= 1'b0;
if( rdata_rd_en ) begin
dma_rd_xfer_cnt <= dma_rd_xfer_cnt + 1'b1;
cpld_rcv_data_size <= cpld_rcv_data_size + 4;
if( ( ( dma_rd_q_rd_data[63:62] == 2'b01 ) && ( dma_rd_xfer_cnt + 1'b1 == ( dma_rd_q_rd_data[15:0] >> 4 ) ) )
|| ( ( dma_rd_q_rd_data[63] == 1'b1 ) && ( dma_rd_xfer_cnt + 1'b1 == ( `PAGE_SIZE >> 4 ) ) ) ) begin
dma_rd_q_rd_en <= 1'b1;
dma_rd_q_sw_delay <= 1'b1;
dma_rd_xfer_cnt <= 16'b0;
dma_rd_xfer_done <= dma_rd_q_rd_data[63];
dma_rd_done_entry <= dma_rd_q_rd_data;
end
end
end
end
assign rdata_wr_en = ( !dma_rd_q_empty && ( dma_rd_q_rd_data[63:62] == 2'b01 ) && !dma_rd_q_sw_delay )?( (!rdata_fifo_empty && !req_queue_full) ? 1'b1 : 1'b0) : 1'b0;
assign RX_data_fifo_wr_en_o = ( !dma_rd_q_empty && ( dma_rd_q_rd_data[63] == 1'b1 ) && !dma_rd_q_sw_delay )?( (!rdata_fifo_empty && !RX_data_fifo_full_i) ? 1'b1 : 1'b0) : 1'b0;
assign rdata_rd_en = rdata_wr_en | RX_data_fifo_wr_en_o;
assign tdata_wr_en = ( !TX_data_fifo_empty_i && !tdata_fifo_full ) ? 1'b1 : 1'b0;
assign TX_data_fifo_rd_en_o = tdata_wr_en;
assign RX_data_fifo_data_o = rdata;
parameter INTERFACE_WIDTH = 128;
parameter INTERFACE_TYPE = 4'b0011;
parameter FPGA_FAMILY = 8'h14;
BMD#
(
.INTERFACE_WIDTH(INTERFACE_WIDTH),
.INTERFACE_TYPE(INTERFACE_TYPE),
.FPGA_FAMILY(FPGA_FAMILY)
)
BMD (
.trn_clk ( trn_clk ), // I
.trn_reset_n ( trn_reset_n ), // I
.trn_lnk_up_n ( trn_lnk_up_n ), // I
.en(en),
.bar0_addr_o(bar0_addr),
.bar0_wr_en_o(bar0_wr_en),
.bar0_wr_be_o(bar0_wr_be),
.bar0_busy_i(bar0_busy),
.bar0_rd_d_i(bar0_rd_d),
.bar0_rd_be_o(bar0_rd_be),
.bar0_wr_d_o(bar0_wr_d),
.bar1_wr_en1_i(bar1_wr_en1),
.bar1_addr1_i(bar1_addr1),
.bar1_be1_i(bar1_be1),
.bar1_wr_d1_i(bar1_wr_d1),
.bar1_wr_ack1_n_o(bar1_wr_ack1_n),
.bar1_wr_en2_i(bar1_wr_en2),
.bar1_addr2_i(bar1_addr2),
.bar1_be2_i(bar1_be2),
.bar1_wr_d2_i(bar1_wr_d2),
.bar1_wr_ack2_n_o(bar1_wr_ack2_n),
.bar1_wr_en3_i(bar1_wr_en3),
.bar1_addr3_i(bar1_addr3),
.bar1_be3_i(bar1_be3),
.bar1_wr_d3_i(bar1_wr_d3),
.bar1_wr_ack3_n_o(bar1_wr_ack3_n),
.bar1_arbiter_busy_o(bar1_arbiter_busy),
.bar1_wr_busy_o(bar1_wr_busy),
.rdata_o(rdata),
.rdata_rd_en_i(rdata_rd_en),
.rdata_fifo_empty_o(rdata_fifo_empty),
.tdata_i(TX_data_fifo_data_i),
.tdata_wr_en_i(tdata_wr_en),
.tdata_fifo_full_o(tdata_fifo_full),
.mwr_start_o(mwr_start),
.mwr_done_o(mwr_done),
.mrd_start_o(mrd_start),
.mrd_done_o(mrd_done),
.req_compl_o(req_compl),
.compl_done_o(compl_done),
.cpld_malformed_o(cpld_malformed),
.cpld_rcv_data_size_i(cpld_rcv_data_size),
.trn_td ( trn_td ), // O [63:0]
.trn_trem_n ( trn_trem_n ), // O [7:0]
.trn_tsof_n ( trn_tsof_n ), // O
.trn_teof_n ( trn_teof_n ), // O
.trn_tsrc_rdy_n ( trn_tsrc_rdy_n ), // O
.trn_tsrc_dsc_n ( trn_tsrc_dsc_n ), // O
.trn_tdst_rdy_n ( trn_tdst_rdy_n ), // I
.trn_tdst_dsc_n ( trn_tdst_dsc_n ), // I
.trn_tbuf_av ( trn_tbuf_av ), // I [5:0]
.trn_rd ( trn_rd ), // I [63:0]
.trn_rrem_n ( trn_rrem_n ), // I [7:0]
.trn_rsof_n ( trn_rsof_n ), // I
.trn_reof_n ( trn_reof_n ), // I
.trn_rsrc_rdy_n ( trn_rsrc_rdy_n ), // I
.trn_rsrc_dsc_n ( trn_rsrc_dsc_n ), // I
.trn_rbar_hit_n ( trn_rbar_hit_n ), // I [6:0]
.trn_rdst_rdy_n ( trn_rdst_rdy_n ), // O
.cfg_to_turnoff_n ( cfg_to_turnoff_n ), // I
.cfg_turnoff_ok_n ( cfg_turnoff_ok_n ), // O
.cfg_do(cfg_do), // I [31:0]
.cfg_dwaddr(cfg_dwaddr), // O [11:0]
.cfg_rd_en_n(cfg_rd_en_n), // O
.cfg_interrupt_n(), // O
.cfg_interrupt_rdy_n(), // I
.cfg_interrupt_assert_n(), // O
.cfg_interrupt_di(cfg_interrupt_di), // O
.cfg_interrupt_do(cfg_interrupt_do), // I
.cfg_interrupt_mmenable(cfg_interrupt_mmenable), // I
.cfg_interrupt_msienable(cfg_interrupt_msienable), // I
.cfg_ext_tag_en( cfg_ext_tag_en ), // I
.cfg_max_rd_req_size(cfg_max_rd_req_size), // I [2:0]
.cfg_prg_max_payload_size(cfg_prg_max_payload_size), // I [5:0]
.cfg_neg_max_lnk_width(cfg_neg_max_lnk_width), // I [5:0]
.cfg_neg_max_lnk_speed(cfg_neg_max_lnk_speed),
.cfg_rd_comp_bound(cfg_rd_comp_bound), // I
.cfg_rd_wr_done_n(cfg_rd_wr_done_n), // I
`ifdef PCIE2_0
.pl_directed_link_change( pl_directed_link_change ),
.pl_ltssm_state( pl_ltssm_state ),
.pl_directed_link_width( pl_directed_link_width ),
.pl_directed_link_speed( pl_directed_link_speed ),
.pl_directed_link_auton( pl_directed_link_auton ),
.pl_sel_link_width( pl_sel_link_width ),
.pl_sel_link_rate( pl_sel_link_rate ),
.pl_link_gen2_capable( pl_link_gen2_capable ),
.pl_link_partner_gen2_supported( pl_link_partner_gen2_supported ),
.pl_initial_link_width( pl_initial_link_width ),
.pl_link_upcfg_capable( pl_link_upcfg_capable ),
.pl_lane_reversal_mode( pl_lane_reversal_mode ),
.pl_upstream_preemph_src( pl_upstream_prefer_deemph ),
`endif
.cfg_completer_id ( cfg_completer_id ), // I [15:0]
.cfg_bus_mstr_enable (cfg_bus_mstr_enable ), // I
/*************ouyang***************/
//response queue interface
.response_queue_empty_i(response_queue_empty),
.response_queue_data_i(response_queue_data),
.response_queue_rd_en_o(response_queue_rd_en) ,//read enable signal for response queue
//msix interface
.msg_lower_addr_i(msg_lower_addr),
.msg_upper_addr_i(msg_upper_addr),
.msg_data_i(msg_data),
// the base addr for response queue
.response_queue_addr_i(response_queue_addr),
//count enable for response queue offset
.response_queue_addr_offset_cnt_en_o(response_queue_addr_offset_cnt_en),
.interrupt_block_i(interrupt_block),
.response_queue_cur_offset_reg_i(response_queue_cur_offset_reg),
.response_queue_addr_offset_i(response_queue_addr_offset)
/**********************************/
);
REQ_MANAGER REQ_MANAGER(
.clk(trn_clk),
.rst_n(trn_reset_n & ~trn_lnk_up_n),
.en(en),
// REQ_QUEUE_WRAPPER
.rdata_i(rdata),
.rdata_wr_en_i(rdata_wr_en),
.req_queue_full_o(req_queue_full),
//CPM
.CMGFTL_cmd_fifo_full_i(CMGFTL_cmd_fifo_full_i),
.CMGFTL_cmd_fifo_almost_full_i(CMGFTL_cmd_fifo_almost_full_i),
.CMGFTL_cmd_fifo_wr_en_o(CMGFTL_cmd_fifo_wr_en_o),
.CMGFTL_cmd_fifo_data_o(CMGFTL_cmd_fifo_data_o),
.FTLCMG_cmd_fifo_empty_i(FTLCMG_cmd_fifo_empty_i),
.FTLCMG_cmd_fifo_almost_empty_i(FTLCMG_cmd_fifo_almost_empty_i),
.FTLCMG_cmd_fifo_rd_en_o(FTLCMG_cmd_fifo_rd_en_o),
.FTLCMG_cmd_fifo_data_i(FTLCMG_cmd_fifo_data_i),
.bar1_wr_en2_o(bar1_wr_en2),
.bar1_addr2_o(bar1_addr2),
.bar1_wr_be2_o(bar1_be2),
.bar1_wr_d2_o(bar1_wr_d2),
.bar1_wr_ack2_n_i(bar1_wr_ack2_n),
.bar1_wr_en3_o(bar1_wr_en3),
.bar1_addr3_o(bar1_addr3),
.bar1_wr_be3_o(bar1_be3),
.bar1_wr_d3_o(bar1_wr_d3),
.bar1_wr_ack3_n_i(bar1_wr_ack3_n),
.bar1_arbiter_busy_i(bar1_arbiter_busy),
.bar1_wr_busy_i(bar1_wr_busy),
.mrd_start_i(mrd_start),
.mrd_done_i(mrd_done),
.mwr_start_i(mwr_start),
.mwr_done_i(mwr_done),
.req_compl_i(req_compl),
.recv_fifo_av_i(RX_data_fifo_av_i),
//BAR0_WRAPPER
.a_i(bar0_addr),
.wr_en_i(bar0_wr_en),
.wr_be_i(bar0_wr_be),
.wr_busy_o(bar0_busy),
.rd_d_o(bar0_rd_d),
.rd_be_i(bar0_rd_be),
.wr_d_i(bar0_wr_d),
.bar1_wr_en1_o(bar1_wr_en1),
.bar1_addr1_o(bar1_addr1),
.bar1_wr_be1_o(bar1_be1),
.bar1_wr_d1_o(bar1_wr_d1),
.bar1_wr_ack1_n_i(bar1_wr_ack1_n),
.compl_done_i(compl_done),
.dma_rd_req_flag_o(dma_rd_req_flag),
.cpld_malformed_i(cpld_malformed),
//INT_MANAGER
.msi_on(cfg_interrupt_msienable),
.cfg_interrupt_assert_n_o(cfg_interrupt_assert_n),
.cfg_interrupt_rdy_n_i(cfg_interrupt_rdy_n),
.cfg_interrupt_n_o(cfg_interrupt_n),
.cfg_interrupt_legacyclr(),
.dma_rd_q_rd_en_i(dma_rd_q_rd_en),
.dma_rd_q_rd_data_o(dma_rd_q_rd_data),
.dma_rd_q_empty_o(dma_rd_q_empty),
.dma_rd_xfer_done_i(dma_rd_xfer_done),
.dma_rd_done_entry_i(dma_rd_done_entry),
.dma_rd_xfer_done_ack_o(dma_rd_xfer_done_ack),
/*************ouyang***************/
//response queue interface
.response_queue_empty_o(response_queue_empty),
.response_queue_data_o(response_queue_data),
.response_queue_rd_en_i(response_queue_rd_en) ,//read enable signal for response queue
//msix interface
.msg_lower_addr_o(msg_lower_addr),
.msg_upper_addr_o(msg_upper_addr),
.msg_data_o(msg_data),
// the base addr for response queue
.response_queue_addr_o(response_queue_addr),
//count enable for response queue offset
.response_queue_addr_offset_cnt_en_i(response_queue_addr_offset_cnt_en),
.interrupt_block_o(interrupt_block),
.response_queue_cur_offset_reg_o(response_queue_cur_offset_reg),
.response_queue_addr_offset_o(response_queue_addr_offset)
/**********************************/
);
endmodule // pcie_app
|
`timescale 1ns / 1ns
module eth_crc32
(input c, // clock
input r, // reset
input dv, // data-valid
input [7:0] d, // data
output [31:0] crc);
// buffer everything here to help it make timing.
wire dv_d1;
r #(1) dv_d1_r(.c(c), .d(dv), .rst(1'b0), .en(1'b1), .q(dv_d1));
wire [7:0] A; // latched input data
r #(8) din_r(.c(c), .d(d), .rst(1'b0), .en(1'b1), .q(A));
wire [31:0] crc_int;
wire [31:0] new_crc;
wire crc_reg_en = dv_d1;
r #(32, 32'hffffffff) crc_reg(.c(c), .rst(r), .en(crc_reg_en),
.d(new_crc), .q(crc_int));
// flip the bytes around
genvar i, j;
generate
for (j = 0; j < 4; j = j + 1) begin: bytes
for (i = 0; i < 8; i = i + 1) begin: bits
//assign crc[j*8+i] = ~crc_int[(j+1)*8-1-i];
assign crc[j*8+i] = ~new_crc[(j+1)*8-1-i];
end
end
endgenerate
// hooray for CRC auto-generators.
wire [31:0] C = crc_int;
assign new_crc[0] = C[24]^C[30]^A[1]^A[7];
assign new_crc[1] = C[25]^C[31]^A[0]^A[6]^C[24]^C[30]^A[1]^A[7];
assign new_crc[2] = C[26]^A[5]^C[25]^C[31]^A[0]^A[6]^C[24]^C[30]^A[1]^A[7];
assign new_crc[3] = C[27]^A[4]^C[26]^A[5]^C[25]^C[31]^A[0]^A[6];
assign new_crc[4] = C[28]^A[3]^C[27]^A[4]^C[26]^A[5]^C[24]^C[30]^A[1]^A[7];
assign new_crc[5] = C[29]^A[2]^C[28]^A[3]^C[27]^A[4]^C[25]^C[31]^A[0]^A[6]^C[24]^C[30]^A[1]^A[7];
assign new_crc[6] = C[30]^A[1]^C[29]^A[2]^C[28]^A[3]^C[26]^A[5]^C[25]^C[31]^A[0]^A[6];
assign new_crc[7] = C[31]^A[0]^C[29]^A[2]^C[27]^A[4]^C[26]^A[5]^C[24]^A[7];
assign new_crc[8] = C[0]^C[28]^A[3]^C[27]^A[4]^C[25]^A[6]^C[24]^A[7];
assign new_crc[9] = C[1]^C[29]^A[2]^C[28]^A[3]^C[26]^A[5]^C[25]^A[6];
assign new_crc[10] = C[2]^C[29]^A[2]^C[27]^A[4]^C[26]^A[5]^C[24]^A[7];
assign new_crc[11] = C[3]^C[28]^A[3]^C[27]^A[4]^C[25]^A[6]^C[24]^A[7];
assign new_crc[12] = C[4]^C[29]^A[2]^C[28]^A[3]^C[26]^A[5]^C[25]^A[6]^C[24]^C[30]^A[1]^A[7];
assign new_crc[13] = C[5]^C[30]^A[1]^C[29]^A[2]^C[27]^A[4]^C[26]^A[5]^C[25]^C[31]^A[0]^A[6];
assign new_crc[14] = C[6]^C[31]^A[0]^C[30]^A[1]^C[28]^A[3]^C[27]^A[4]^C[26]^A[5];
assign new_crc[15] = C[7]^C[31]^A[0]^C[29]^A[2]^C[28]^A[3]^C[27]^A[4];
assign new_crc[16] = C[8]^C[29]^A[2]^C[28]^A[3]^C[24]^A[7];
assign new_crc[17] = C[9]^C[30]^A[1]^C[29]^A[2]^C[25]^A[6];
assign new_crc[18] = C[10]^C[31]^A[0]^C[30]^A[1]^C[26]^A[5];
assign new_crc[19] = C[11]^C[31]^A[0]^C[27]^A[4];
assign new_crc[20] = C[12]^C[28]^A[3];
assign new_crc[21] = C[13]^C[29]^A[2];
assign new_crc[22] = C[14]^C[24]^A[7];
assign new_crc[23] = C[15]^C[25]^A[6]^C[24]^C[30]^A[1]^A[7];
assign new_crc[24] = C[16]^C[26]^A[5]^C[25]^C[31]^A[0]^A[6];
assign new_crc[25] = C[17]^C[27]^A[4]^C[26]^A[5];
assign new_crc[26] = C[18]^C[28]^A[3]^C[27]^A[4]^C[24]^C[30]^A[1]^A[7];
assign new_crc[27] = C[19]^C[29]^A[2]^C[28]^A[3]^C[25]^C[31]^A[0]^A[6];
assign new_crc[28] = C[20]^C[30]^A[1]^C[29]^A[2]^C[26]^A[5];
assign new_crc[29] = C[21]^C[31]^A[0]^C[30]^A[1]^C[27]^A[4];
assign new_crc[30] = C[22]^C[31]^A[0]^C[28]^A[3];
assign new_crc[31] = C[23]^C[29]^A[2];
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Grig Barbulescu
//
// Create Date: 01/17/2016 04:48:20 PM
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
// This small sketch demonstrates the division operation on Zybo board.
// This was implemented to use only the PL, but no PS nor ARM.
// The usage is simple:
// - on swithes 3:0 select the upper four bits of dividend, then press&release button 3
// - on swithes 3:0 select the lower four bits of dividend, then press&release button 2
// - on swithes 3:0 select the four bits of divisor, then press&release button 1
// - on LEDs 3:0 will be visible the four bits of the quotient
// - if you push the button 0, on the LEDs will appear the four bits of the remainder
//////////////////////////////////////////////////////////////////////////////////
module top( input clk,
output reg [3:0] led,
input [3:0] btn,
input [3:0] sw );
reg [7:0] A;
reg [3:0] B;
wire [3:0] Q;
wire [3:0] R;
div inst( .clk(clk),
.A(A),
.B(B),
.Q(Q),
.R(R)
);
always @(posedge clk)
begin
if(btn[3]) A[7:4] <= sw[3:0];
if(btn[2]) A[3:0] <= sw[3:0];
if(btn[1]) B[3:0] <= sw[3:0];
if(btn[0]) led[3:0] <= R[3:0];
else led[3:0] <= Q[3:0];
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A311OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__A311OI_FUNCTIONAL_PP_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a311oi (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
// Local signals
wire B1 and0_out ;
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y , and0_out, B1, C1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A311OI_FUNCTIONAL_PP_V |
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// See Xilinx UG953 and UG474 for a description of the cell types below.
// http://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf
// http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug953-vivado-7series-libraries.pdf
module VCC(output P);
assign P = 1;
endmodule
module GND(output G);
assign G = 0;
endmodule
module IBUF(
output O,
(* iopad_external_pin *)
input I);
parameter IOSTANDARD = "default";
parameter IBUF_LOW_PWR = 0;
assign O = I;
specify
(I => O) = 0;
endspecify
endmodule
module IBUFG(
output O,
(* iopad_external_pin *)
input I);
parameter CAPACITANCE = "DONT_CARE";
parameter IBUF_DELAY_VALUE = "0";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
assign O = I;
endmodule
module OBUF(
(* iopad_external_pin *)
output O,
input I);
parameter IOSTANDARD = "default";
parameter DRIVE = 12;
parameter SLEW = "SLOW";
assign O = I;
specify
(I => O) = 0;
endspecify
endmodule
module IOBUF (
(* iopad_external_pin *)
inout IO,
output O,
input I,
input T
);
parameter integer DRIVE = 12;
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter SLEW = "SLOW";
assign IO = T ? 1'bz : I;
assign O = IO;
specify
(I => IO) = 0;
(IO => O) = 0;
endspecify
endmodule
module OBUFT (
(* iopad_external_pin *)
output O,
input I,
input T
);
parameter CAPACITANCE = "DONT_CARE";
parameter integer DRIVE = 12;
parameter IOSTANDARD = "DEFAULT";
parameter SLEW = "SLOW";
assign O = T ? 1'bz : I;
specify
(I => O) = 0;
endspecify
endmodule
module BUFG(
(* clkbuf_driver *)
output O,
input I);
assign O = I;
specify
// https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/CLK_BUFG_TOP_R.sdf#L11
(I => O) = 96;
endspecify
endmodule
module BUFGCTRL(
(* clkbuf_driver *)
output O,
input I0, input I1,
(* invertible_pin = "IS_S0_INVERTED" *)
input S0,
(* invertible_pin = "IS_S1_INVERTED" *)
input S1,
(* invertible_pin = "IS_CE0_INVERTED" *)
input CE0,
(* invertible_pin = "IS_CE1_INVERTED" *)
input CE1,
(* invertible_pin = "IS_IGNORE0_INVERTED" *)
input IGNORE0,
(* invertible_pin = "IS_IGNORE1_INVERTED" *)
input IGNORE1);
parameter [0:0] INIT_OUT = 1'b0;
parameter PRESELECT_I0 = "FALSE";
parameter PRESELECT_I1 = "FALSE";
parameter [0:0] IS_CE0_INVERTED = 1'b0;
parameter [0:0] IS_CE1_INVERTED = 1'b0;
parameter [0:0] IS_S0_INVERTED = 1'b0;
parameter [0:0] IS_S1_INVERTED = 1'b0;
parameter [0:0] IS_IGNORE0_INVERTED = 1'b0;
parameter [0:0] IS_IGNORE1_INVERTED = 1'b0;
wire I0_internal = ((CE0 ^ IS_CE0_INVERTED) ? I0 : INIT_OUT);
wire I1_internal = ((CE1 ^ IS_CE1_INVERTED) ? I1 : INIT_OUT);
wire S0_true = (S0 ^ IS_S0_INVERTED);
wire S1_true = (S1 ^ IS_S1_INVERTED);
assign O = S0_true ? I0_internal : (S1_true ? I1_internal : INIT_OUT);
endmodule
module BUFHCE(
(* clkbuf_driver *)
output O,
input I,
(* invertible_pin = "IS_CE_INVERTED" *)
input CE);
parameter [0:0] INIT_OUT = 1'b0;
parameter CE_TYPE = "SYNC";
parameter [0:0] IS_CE_INVERTED = 1'b0;
assign O = ((CE ^ IS_CE_INVERTED) ? I : INIT_OUT);
endmodule
// module OBUFT(output O, input I, T);
// assign O = T ? 1'bz : I;
// endmodule
// module IOBUF(inout IO, output O, input I, T);
// assign O = IO, IO = T ? 1'bz : I;
// endmodule
module INV(
(* clkbuf_inv = "I" *)
output O,
input I
);
assign O = !I;
specify
(I => O) = 127;
endspecify
endmodule
(* abc9_lut=1 *)
module LUT1(output O, input I0);
parameter [1:0] INIT = 0;
assign O = I0 ? INIT[1] : INIT[0];
specify
(I0 => O) = 127;
endspecify
endmodule
(* abc9_lut=2 *)
module LUT2(output O, input I0, I1);
parameter [3:0] INIT = 0;
wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
assign O = I0 ? s1[1] : s1[0];
specify
(I0 => O) = 238;
(I1 => O) = 127;
endspecify
endmodule
(* abc9_lut=3 *)
module LUT3(output O, input I0, I1, I2);
parameter [7:0] INIT = 0;
wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign O = I0 ? s1[1] : s1[0];
specify
(I0 => O) = 407;
(I1 => O) = 238;
(I2 => O) = 127;
endspecify
endmodule
(* abc9_lut=3 *)
module LUT4(output O, input I0, I1, I2, I3);
parameter [15:0] INIT = 0;
wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign O = I0 ? s1[1] : s1[0];
specify
(I0 => O) = 472;
(I1 => O) = 407;
(I2 => O) = 238;
(I3 => O) = 127;
endspecify
endmodule
(* abc9_lut=3 *)
module LUT5(output O, input I0, I1, I2, I3, I4);
parameter [31:0] INIT = 0;
wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0];
wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0];
wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign O = I0 ? s1[1] : s1[0];
specify
(I0 => O) = 631;
(I1 => O) = 472;
(I2 => O) = 407;
(I3 => O) = 238;
(I4 => O) = 127;
endspecify
endmodule
// This is a placeholder for ABC9 to extract the area/delay
// cost of 3-input LUTs and is not intended to be instantiated
(* abc9_lut=5 *)
module LUT6(output O, input I0, I1, I2, I3, I4, I5);
parameter [63:0] INIT = 0;
wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
wire [15: 0] s4 = I4 ? s5[31:16] : s5[15: 0];
wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0];
wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign O = I0 ? s1[1] : s1[0];
specify
(I0 => O) = 642;
(I1 => O) = 631;
(I2 => O) = 472;
(I3 => O) = 407;
(I4 => O) = 238;
(I5 => O) = 127;
endspecify
endmodule
module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5);
parameter [63:0] INIT = 0;
wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
wire [15: 0] s4 = I4 ? s5[31:16] : s5[15: 0];
wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0];
wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
assign O6 = I0 ? s1[1] : s1[0];
wire [15: 0] s5_4 = I4 ? INIT[31:16] : INIT[15: 0];
wire [ 7: 0] s5_3 = I3 ? s5_4[15: 8] : s5_4[ 7: 0];
wire [ 3: 0] s5_2 = I2 ? s5_3[ 7: 4] : s5_3[ 3: 0];
wire [ 1: 0] s5_1 = I1 ? s5_2[ 3: 2] : s5_2[ 1: 0];
assign O5 = I0 ? s5_1[1] : s5_1[0];
endmodule
// This is a placeholder for ABC9 to extract the area/delay
// cost of 3-input LUTs and is not intended to be instantiated
(* abc9_lut=10 *)
module \$__ABC9_LUT7 (output O, input I0, I1, I2, I3, I4, I5, I6);
`ifndef __ICARUS__
specify
// https://github.com/SymbiFlow/prjxray-db/blob/1c85daf1b115da4d27ca83c6b89f53a94de39748/artix7/timings/slicel.sdf#L867
(I0 => O) = 642 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
(I1 => O) = 631 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
(I2 => O) = 472 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
(I3 => O) = 407 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
(I4 => O) = 238 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
(I5 => O) = 127 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
(I6 => O) = 0 + 296 /* to select F7BMUX */ + 174 /* CMUX */;
endspecify
`endif
endmodule
// This is a placeholder for ABC9 to extract the area/delay
// cost of 3-input LUTs and is not intended to be instantiated
(* abc9_lut=20 *)
module \$__ABC9_LUT8 (output O, input I0, I1, I2, I3, I4, I5, I6, I7);
`ifndef __ICARUS__
specify
// https://github.com/SymbiFlow/prjxray-db/blob/1c85daf1b115da4d27ca83c6b89f53a94de39748/artix7/timings/slicel.sdf#L716
(I0 => O) = 642 + 223 /* to cross F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */;
(I1 => O) = 631 + 223 /* to cross F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */;
(I2 => O) = 472 + 223 /* to cross F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */;
(I3 => O) = 407 + 223 /* to cross F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */;
(I4 => O) = 238 + 223 /* to cross F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */;
(I5 => O) = 127 + 223 /* to cross F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */;
(I6 => O) = 0 + 296 /* to select F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */;
(I7 => O) = 0 + 0 + 273 /* to select F8MUX */ + 192 /* BMUX */;
endspecify
`endif
endmodule
module MUXCY(output O, input CI, DI, S);
assign O = S ? CI : DI;
endmodule
module MUXF5(output O, input I0, I1, S);
assign O = S ? I1 : I0;
endmodule
module MUXF6(output O, input I0, I1, S);
assign O = S ? I1 : I0;
endmodule
(* abc9_box, lib_whitebox *)
module MUXF7(output O, input I0, I1, S);
assign O = S ? I1 : I0;
specify
// https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L451-L453
(I0 => O) = 217;
(I1 => O) = 223;
(S => O) = 296;
endspecify
endmodule
(* abc9_box, lib_whitebox *)
module MUXF8(output O, input I0, I1, S);
assign O = S ? I1 : I0;
specify
// Max delays from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L462-L464
(I0 => O) = 104;
(I1 => O) = 94;
(S => O) = 273;
endspecify
endmodule
module MUXF9(output O, input I0, I1, S);
assign O = S ? I1 : I0;
endmodule
module XORCY(output O, input CI, LI);
assign O = CI ^ LI;
endmodule
(* abc9_box, lib_whitebox *)
module CARRY4(
(* abc9_carry *)
output [3:0] CO,
output [3:0] O,
(* abc9_carry *)
input CI,
input CYINIT,
input [3:0] DI, S
);
assign O = S ^ {CO[2:0], CI | CYINIT};
assign CO[0] = S[0] ? CI | CYINIT : DI[0];
assign CO[1] = S[1] ? CO[0] : DI[1];
assign CO[2] = S[2] ? CO[1] : DI[2];
assign CO[3] = S[3] ? CO[2] : DI[3];
specify
// https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L11-L46
(CYINIT => O[0]) = 482;
(S[0] => O[0]) = 223;
(CI => O[0]) = 222;
(CYINIT => O[1]) = 598;
(DI[0] => O[1]) = 407;
(S[0] => O[1]) = 400;
(S[1] => O[1]) = 205;
(CI => O[1]) = 334;
(CYINIT => O[2]) = 584;
(DI[0] => O[2]) = 556;
(DI[1] => O[2]) = 537;
(S[0] => O[2]) = 523;
(S[1] => O[2]) = 558;
(S[2] => O[2]) = 226;
(CI => O[2]) = 239;
(CYINIT => O[3]) = 642;
(DI[0] => O[3]) = 615;
(DI[1] => O[3]) = 596;
(DI[2] => O[3]) = 438;
(S[0] => O[3]) = 582;
(S[1] => O[3]) = 618;
(S[2] => O[3]) = 330;
(S[3] => O[3]) = 227;
(CI => O[3]) = 313;
(CYINIT => CO[0]) = 536;
(DI[0] => CO[0]) = 379;
(S[0] => CO[0]) = 340;
(CI => CO[0]) = 271;
(CYINIT => CO[1]) = 494;
(DI[0] => CO[1]) = 465;
(DI[1] => CO[1]) = 445;
(S[0] => CO[1]) = 433;
(S[1] => CO[1]) = 469;
(CI => CO[1]) = 157;
(CYINIT => CO[2]) = 592;
(DI[0] => CO[2]) = 540;
(DI[1] => CO[2]) = 520;
(DI[2] => CO[2]) = 356;
(S[0] => CO[2]) = 512;
(S[1] => CO[2]) = 548;
(S[2] => CO[2]) = 292;
(CI => CO[2]) = 228;
(CYINIT => CO[3]) = 580;
(DI[0] => CO[3]) = 526;
(DI[1] => CO[3]) = 507;
(DI[2] => CO[3]) = 398;
(DI[3] => CO[3]) = 385;
(S[0] => CO[3]) = 508;
(S[1] => CO[3]) = 528;
(S[2] => CO[3]) = 378;
(S[3] => CO[3]) = 380;
(CI => CO[3]) = 114;
endspecify
endmodule
module CARRY8(
output [7:0] CO,
output [7:0] O,
input CI,
input CI_TOP,
input [7:0] DI, S
);
parameter CARRY_TYPE = "SINGLE_CY8";
wire CI4 = (CARRY_TYPE == "DUAL_CY4" ? CI_TOP : CO[3]);
assign O = S ^ {CO[6:4], CI4, CO[2:0], CI};
assign CO[0] = S[0] ? CI : DI[0];
assign CO[1] = S[1] ? CO[0] : DI[1];
assign CO[2] = S[2] ? CO[1] : DI[2];
assign CO[3] = S[3] ? CO[2] : DI[3];
assign CO[4] = S[4] ? CI4 : DI[4];
assign CO[5] = S[5] ? CO[4] : DI[5];
assign CO[6] = S[6] ? CO[5] : DI[6];
assign CO[7] = S[7] ? CO[6] : DI[7];
endmodule
module ORCY (output O, input CI, I);
assign O = CI | I;
endmodule
module MULT_AND (output LO, input I0, I1);
assign LO = I0 & I1;
endmodule
// Flip-flops and latches.
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L238-L250
(* abc9_flop, lib_whitebox *)
module FDRE (
output reg Q,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C,
input CE,
(* invertible_pin = "IS_D_INVERTED" *)
input D,
(* invertible_pin = "IS_R_INVERTED" *)
input R
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_R_INVERTED = 1'b0;
initial Q <= INIT;
generate
case (|IS_C_INVERTED)
1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
endcase
endgenerate
specify
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249
$setup(D , posedge C &&& CE && !IS_C_INVERTED , /*-46*/ 0); // Negative times not currently supported
$setup(D , negedge C &&& CE && IS_C_INVERTED , /*-46*/ 0); // Negative times not currently supported
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
$setup(CE, posedge C &&& !IS_C_INVERTED, 109);
$setup(CE, negedge C &&& IS_C_INVERTED, 109);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274
$setup(R , posedge C &&& !IS_C_INVERTED, 404);
$setup(R , negedge C &&& IS_C_INVERTED, 404);
// https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L243
if (!IS_C_INVERTED && R != IS_R_INVERTED) (posedge C => (Q : 1'b0)) = 303;
if ( IS_C_INVERTED && R != IS_R_INVERTED) (negedge C => (Q : 1'b0)) = 303;
if (!IS_C_INVERTED && R == IS_R_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
if ( IS_C_INVERTED && R == IS_R_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
endspecify
endmodule
(* abc9_flop, lib_whitebox *)
module FDRE_1 (
output reg Q,
(* clkbuf_sink *)
input C,
input CE,
input D,
input R
);
parameter [0:0] INIT = 1'b0;
initial Q <= INIT;
always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D;
specify
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249
$setup(D , negedge C &&& CE, /*-46*/ 0); // Negative times not currently supported
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
$setup(CE, negedge C, 109);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274
$setup(R , negedge C, 404); // https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L243
if (R) (negedge C => (Q : 1'b0)) = 303;
if (!R && CE) (negedge C => (Q : D)) = 303;
endspecify
endmodule
(* abc9_flop, lib_whitebox *)
module FDSE (
output reg Q,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C,
input CE,
(* invertible_pin = "IS_D_INVERTED" *)
input D,
(* invertible_pin = "IS_S_INVERTED" *)
input S
);
parameter [0:0] INIT = 1'b1;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_S_INVERTED = 1'b0;
initial Q <= INIT;
generate
case (|IS_C_INVERTED)
1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
endcase
endgenerate
specify
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249
$setup(D , posedge C &&& !IS_C_INVERTED && CE, /*-46*/ 0); // Negative times not currently supported
$setup(D , negedge C &&& IS_C_INVERTED && CE, /*-46*/ 0); // Negative times not currently supported
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
$setup(CE, posedge C &&& !IS_C_INVERTED, 109);
$setup(CE, negedge C &&& IS_C_INVERTED, 109);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274
$setup(S , posedge C &&& !IS_C_INVERTED, 404);
$setup(S , negedge C &&& IS_C_INVERTED, 404);
// https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L243
if (!IS_C_INVERTED && S != IS_S_INVERTED) (posedge C => (Q : 1'b1)) = 303;
if ( IS_C_INVERTED && S != IS_S_INVERTED) (negedge C => (Q : 1'b1)) = 303;
if (!IS_C_INVERTED && S == IS_S_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
if ( IS_C_INVERTED && S == IS_S_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
endspecify
endmodule
(* abc9_flop, lib_whitebox *)
module FDSE_1 (
output reg Q,
(* clkbuf_sink *)
input C,
input CE,
input D,
input S
);
parameter [0:0] INIT = 1'b1;
initial Q <= INIT;
always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D;
specify
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249
$setup(D , negedge C &&& CE, /*-46*/ 0); // Negative times not currently supported
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
$setup(CE, negedge C, 109);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274
$setup(S , negedge C, 404);
// https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L243
if (S) (negedge C => (Q : 1'b1)) = 303;
if (!S && CE) (negedge C => (Q : D)) = 303;
endspecify
endmodule
module FDRSE (
output reg Q,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C,
(* invertible_pin = "IS_CE_INVERTED" *)
input CE,
(* invertible_pin = "IS_D_INVERTED" *)
input D,
(* invertible_pin = "IS_R_INVERTED" *)
input R,
(* invertible_pin = "IS_S_INVERTED" *)
input S
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_CE_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_R_INVERTED = 1'b0;
parameter [0:0] IS_S_INVERTED = 1'b0;
initial Q <= INIT;
wire c = C ^ IS_C_INVERTED;
wire ce = CE ^ IS_CE_INVERTED;
wire d = D ^ IS_D_INVERTED;
wire r = R ^ IS_R_INVERTED;
wire s = S ^ IS_S_INVERTED;
always @(posedge c)
if (r)
Q <= 0;
else if (s)
Q <= 1;
else if (ce)
Q <= d;
endmodule
(* abc9_box, lib_whitebox *)
module FDCE (
output reg Q,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C,
input CE,
(* invertible_pin = "IS_CLR_INVERTED" *)
input CLR,
(* invertible_pin = "IS_D_INVERTED" *)
input D
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_CLR_INVERTED = 1'b0;
initial Q <= INIT;
generate
case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
endcase
endgenerate
specify
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249
$setup(D , posedge C &&& !IS_C_INVERTED && CE, /*-46*/ 0); // Negative times not currently supported
$setup(D , negedge C &&& IS_C_INVERTED && CE, /*-46*/ 0); // Negative times not currently supported
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
$setup(CE , posedge C &&& !IS_C_INVERTED, 109);
$setup(CE , negedge C &&& IS_C_INVERTED, 109);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274
$setup(CLR, posedge C &&& !IS_C_INVERTED, 404);
$setup(CLR, negedge C &&& IS_C_INVERTED, 404);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
`ifndef YOSYS
if (!IS_CLR_INVERTED) (posedge CLR => (Q : 1'b0)) = 764;
if ( IS_CLR_INVERTED) (negedge CLR => (Q : 1'b0)) = 764;
`else
if (IS_CLR_INVERTED != CLR) (CLR => Q) = 764; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
`endif
if (!IS_C_INVERTED && CLR == IS_CLR_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
if ( IS_C_INVERTED && CLR == IS_CLR_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
endspecify
endmodule
(* abc9_box, lib_whitebox *)
module FDCE_1 (
output reg Q,
(* clkbuf_sink *)
input C,
input CE,
input CLR,
input D
);
parameter [0:0] INIT = 1'b0;
initial Q <= INIT;
always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
specify
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249
$setup(D , negedge C &&& CE, /*-46*/ 0); // Negative times not currently supported
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
$setup(CE , negedge C, 109);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274
$setup(CLR, negedge C, 404);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
`ifndef YOSYS
(posedge CLR => (Q : 1'b0)) = 764;
`else
if (CLR) (CLR => Q) = 764; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
`endif
if (!CLR && CE) (negedge C => (Q : D)) = 303;
endspecify
endmodule
(* abc9_box, lib_whitebox *)
module FDPE (
output reg Q,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C,
input CE,
(* invertible_pin = "IS_D_INVERTED" *)
input D,
(* invertible_pin = "IS_PRE_INVERTED" *)
input PRE
);
parameter [0:0] INIT = 1'b1;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_PRE_INVERTED = 1'b0;
initial Q <= INIT;
generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
endcase
endgenerate
specify
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249
$setup(D , posedge C &&& !IS_C_INVERTED && CE, /*-46*/ 0); // Negative times not currently supported
$setup(D , negedge C &&& IS_C_INVERTED && CE, /*-46*/ 0); // Negative times not currently supported
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
$setup(CE , posedge C &&& !IS_C_INVERTED, 109);
$setup(CE , negedge C &&& IS_C_INVERTED, 109);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274
$setup(PRE, posedge C &&& !IS_C_INVERTED, 404);
$setup(PRE, negedge C &&& IS_C_INVERTED, 404);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
`ifndef YOSYS
if (!IS_PRE_INVERTED) (posedge PRE => (Q : 1'b1)) = 764;
if ( IS_PRE_INVERTED) (negedge PRE => (Q : 1'b1)) = 764;
`else
if (IS_PRE_INVERTED != PRE) (PRE => Q) = 764; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
`endif
if (!IS_C_INVERTED && PRE == IS_PRE_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
if ( IS_C_INVERTED && PRE == IS_PRE_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
endspecify
endmodule
(* abc9_box, lib_whitebox *)
module FDPE_1 (
output reg Q,
(* clkbuf_sink *)
input C,
input CE,
input D,
input PRE
);
parameter [0:0] INIT = 1'b1;
initial Q <= INIT;
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
specify
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249
$setup(D , negedge C &&& CE, /*-46*/ 0); // Negative times not currently supported
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
$setup(CE , negedge C, 109);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274
$setup(PRE, negedge C, 404);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
`ifndef YOSYS
(posedge PRE => (Q : 1'b1)) = 764;
`else
if (PRE) (PRE => Q) = 764; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
`endif
if (!PRE && CE) (negedge C => (Q : D)) = 303;
endspecify
endmodule
module FDCPE (
output wire Q,
(* clkbuf_sink *)
(* invertible_pin = "IS_C_INVERTED" *)
input C,
input CE,
(* invertible_pin = "IS_CLR_INVERTED" *)
input CLR,
input D,
(* invertible_pin = "IS_PRE_INVERTED" *)
input PRE
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_CLR_INVERTED = 1'b0;
parameter [0:0] IS_PRE_INVERTED = 1'b0;
wire c = C ^ IS_C_INVERTED;
wire clr = CLR ^ IS_CLR_INVERTED;
wire pre = PRE ^ IS_PRE_INVERTED;
// Hacky model to avoid simulation-synthesis mismatches.
reg qc, qp, qs;
initial qc = INIT;
initial qp = INIT;
initial qs = 0;
always @(posedge c, posedge clr) begin
if (clr)
qc <= 0;
else if (CE)
qc <= D;
end
always @(posedge c, posedge pre) begin
if (pre)
qp <= 1;
else if (CE)
qp <= D;
end
always @* begin
if (clr)
qs <= 0;
else if (pre)
qs <= 1;
end
assign Q = qs ? qp : qc;
endmodule
module LDCE (
output reg Q,
(* invertible_pin = "IS_CLR_INVERTED" *)
input CLR,
input D,
(* invertible_pin = "IS_G_INVERTED" *)
input G,
input GE
);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_CLR_INVERTED = 1'b0;
parameter [0:0] IS_G_INVERTED = 1'b0;
parameter MSGON = "TRUE";
parameter XON = "TRUE";
initial Q = INIT;
wire clr = CLR ^ IS_CLR_INVERTED;
wire g = G ^ IS_G_INVERTED;
always @*
if (clr) Q <= 1'b0;
else if (GE && g) Q <= D;
endmodule
module LDPE (
output reg Q,
input D,
(* invertible_pin = "IS_G_INVERTED" *)
input G,
input GE,
(* invertible_pin = "IS_PRE_INVERTED" *)
input PRE
);
parameter [0:0] INIT = 1'b1;
parameter [0:0] IS_G_INVERTED = 1'b0;
parameter [0:0] IS_PRE_INVERTED = 1'b0;
parameter MSGON = "TRUE";
parameter XON = "TRUE";
initial Q = INIT;
wire g = G ^ IS_G_INVERTED;
wire pre = PRE ^ IS_PRE_INVERTED;
always @*
if (pre) Q <= 1'b1;
else if (GE && g) Q <= D;
endmodule
module LDCPE (
output reg Q,
(* invertible_pin = "IS_CLR_INVERTED" *)
input CLR,
(* invertible_pin = "IS_D_INVERTED" *)
input D,
(* invertible_pin = "IS_G_INVERTED" *)
input G,
(* invertible_pin = "IS_GE_INVERTED" *)
input GE,
(* invertible_pin = "IS_PRE_INVERTED" *)
input PRE
);
parameter [0:0] INIT = 1'b1;
parameter [0:0] IS_CLR_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_G_INVERTED = 1'b0;
parameter [0:0] IS_GE_INVERTED = 1'b0;
parameter [0:0] IS_PRE_INVERTED = 1'b0;
initial Q = INIT;
wire d = D ^ IS_D_INVERTED;
wire g = G ^ IS_G_INVERTED;
wire ge = GE ^ IS_GE_INVERTED;
wire clr = CLR ^ IS_CLR_INVERTED;
wire pre = PRE ^ IS_PRE_INVERTED;
always @*
if (clr) Q <= 1'b0;
else if (pre) Q <= 1'b1;
else if (ge && g) Q <= d;
endmodule
module AND2B1L (
output O,
input DI,
(* invertible_pin = "IS_SRI_INVERTED" *)
input SRI
);
parameter [0:0] IS_SRI_INVERTED = 1'b0;
assign O = DI & ~(SRI ^ IS_SRI_INVERTED);
endmodule
module OR2L (
output O,
input DI,
(* invertible_pin = "IS_SRI_INVERTED" *)
input SRI
);
parameter [0:0] IS_SRI_INVERTED = 1'b0;
assign O = DI | (SRI ^ IS_SRI_INVERTED);
endmodule
// LUTRAM.
// Single port.
module RAM16X1S (
output O,
input A0, A1, A2, A3,
input D,
(* clkbuf_sink *)
(* invertible_pin = "IS_WCLK_INVERTED" *)
input WCLK,
input WE
);
parameter [15:0] INIT = 16'h0000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
wire [3:0] a = {A3, A2, A1, A0};
reg [15:0] mem = INIT;
assign O = mem[a];
wire clk = WCLK ^ IS_WCLK_INVERTED;
always @(posedge clk) if (WE) mem[a] <= D;
endmodule
module RAM16X1S_1 (
output O,
input A0, A1, A2, A3,
input D,
(* clkbuf_sink *)
(* invertible_pin = "IS_WCLK_INVERTED" *)
input WCLK,
input WE
);
parameter [15:0] INIT = 16'h0000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
wire [3:0] a = {A3, A2, A1, A0};
reg [15:0] mem = INIT;
assign O = mem[a];
wire clk = WCLK ^ IS_WCLK_INVERTED;
always @(negedge clk) if (WE) mem[a] <= D;
endmodule
module RAM32X1S (
output O,
input A0, A1, A2, A3, A4,
input D,
(* clkbuf_sink *)
(* invertible_pin = "IS_WCLK_INVERTED" *)
input WCLK,
input WE
);
parameter [31:0] INIT = 32'h00000000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
wire [4:0] a = {A4, A3, A2, A1, A0};
reg [31:0] mem = INIT;
assign O = mem[a];
wire clk = WCLK ^ IS_WCLK_INVERTED;
always @(posedge clk) if (WE) mem[a] <= D;
endmodule
module RAM32X1S_1 (
output O,
input A0, A1, A2, A3, A4,
input D,
(* clkbuf_sink *)
(* invertible_pin = "IS_WCLK_INVERTED" *)
input WCLK,
input WE
);
parameter [31:0] INIT = 32'h00000000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
wire [4:0] a = {A4, A3, A2, A1, A0};
reg [31:0] mem = INIT;
assign O = mem[a];
wire clk = WCLK ^ IS_WCLK_INVERTED;
always @(negedge clk) if (WE) mem[a] <= D;
endmodule
module RAM64X1S (
output O,
input A0, A1, A2, A3, A4, A5,
input D,
(* clkbuf_sink *)
(* invertible_pin = "IS_WCLK_INVERTED" *)
input WCLK,
input WE
);
parameter [63:0] INIT = 64'h0000000000000000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
wire [5:0] a = {A5, A4, A3, A2, A1, A0};
reg [63:0] mem = INIT;
assign O = mem[a];
wire clk = WCLK ^ IS_WCLK_INVERTED;
always @(posedge clk) if (WE) mem[a] <= D;
endmodule
module RAM64X1S_1 (
output O,
input A0, A1, A2, A3, A4, A5,
input D,
(* clkbuf_sink *)
(* invertible_pin = "IS_WCLK_INVERTED" *)
input WCLK,
input WE
);
parameter [63:0] INIT = 64'h0000000000000000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
wire [5:0] a = {A5, A4, A3, A2, A1, A0};
reg [63:0] mem = INIT;
assign O = mem[a];
wire clk = WCLK ^ IS_WCLK_INVERTED;
always @(negedge clk) if (WE) mem[a] <= D;
endmodule
module RAM128X1S (
output O,
input A0, A1, A2, A3, A4, A5, A6,
input D,
(* clkbuf_sink *)
(* invertible_pin = "IS_WCLK_INVERTED" *)
input WCLK,
input WE
);
parameter [127:0] INIT = 128'h00000000000000000000000000000000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
wire [6:0] a = {A6, A5, A4, A3, A2, A1, A0};
reg [127:0] mem = INIT;
assign O = mem[a];
wire clk = WCLK ^ IS_WCLK_INVERTED;
always @(posedge clk) if (WE) mem[a] <= D;
endmodule
module RAM128X1S_1 (
output O,
input A0, A1, A2, A3, A4, A5, A6,
input D,
(* clkbuf_sink *)
(* invertible_pin = "IS_WCLK_INVERTED" *)
input WCLK,
input WE
);
parameter [127:0] INIT = 128'h00000000000000000000000000000000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
wire [6:0] a = {A6, A5, A4, A3, A2, A1, A0};
reg [127:0] mem = INIT;
assign O = mem[a];
wire clk = WCLK ^ IS_WCLK_INVERTED;
always @(negedge clk) if (WE) mem[a] <= D;
endmodule
module RAM256X1S (
output O,
input [7:0] A,
input D,
(* clkbuf_sink *)
(* invertible_pin = "IS_WCLK_INVERTED" *)
input WCLK,
input WE
);
parameter [255:0] INIT = 256'h0;
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
reg [255:0] mem = INIT;
assign O = mem[A];
wire clk = WCLK ^ IS_WCLK_INVERTED;
always @(posedge clk) if (WE) mem[A] <= D;
endmodule
module RAM512X1S (
output O,
input [8:0] A,
input D,
(* clkbuf_sink *)
(* invertible_pin = "IS_WCLK_INVERTED" *)
input WCLK,
input WE
);
parameter [511:0] INIT = 512'h0;
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
reg [511:0] mem = INIT;
assign O = mem[A];
wire clk = WCLK ^ IS_WCLK_INVERTED;
always @(posedge clk) if (WE) mem[A] <= D;
endmodule
// Single port, wide.
module RAM16X2S (
output O0, O1,
input A0, A1, A2, A3,
input D0, D1,
(* clkbuf_sink *)
(* invertible_pin = "IS_WCLK_INVERTED" *)
input WCLK,
input WE
);
parameter [15:0] INIT_00 = 16'h0000;
parameter [15:0] INIT_01 = 16'h0000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
wire [3:0] a = {A3, A2, A1, A0};
wire clk = WCLK ^ IS_WCLK_INVERTED;
reg [15:0] mem0 = INIT_00;
reg [15:0] mem1 = INIT_01;
assign O0 = mem0[a];
assign O1 = mem1[a];
always @(posedge clk)
if (WE) begin
mem0[a] <= D0;
mem1[a] <= D1;
end
endmodule
module RAM32X2S (
output O0, O1,
input A0, A1, A2, A3, A4,
input D0, D1,
(* clkbuf_sink *)
(* invertible_pin = "IS_WCLK_INVERTED" *)
input WCLK,
input WE
);
parameter [31:0] INIT_00 = 32'h00000000;
parameter [31:0] INIT_01 = 32'h00000000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
wire [4:0] a = {A4, A3, A2, A1, A0};
wire clk = WCLK ^ IS_WCLK_INVERTED;
reg [31:0] mem0 = INIT_00;
reg [31:0] mem1 = INIT_01;
assign O0 = mem0[a];
assign O1 = mem1[a];
always @(posedge clk)
if (WE) begin
mem0[a] <= D0;
mem1[a] <= D1;
end
endmodule
module RAM64X2S (
output O0, O1,
input A0, A1, A2, A3, A4, A5,
input D0, D1,
(* clkbuf_sink *)
(* invertible_pin = "IS_WCLK_INVERTED" *)
input WCLK,
input WE
);
parameter [63:0] INIT_00 = 64'h0000000000000000;
parameter [63:0] INIT_01 = 64'h0000000000000000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
wire [5:0] a = {A5, A3, A2, A1, A0};
wire clk = WCLK ^ IS_WCLK_INVERTED;
reg [63:0] mem0 = INIT_00;
reg [63:0] mem1 = INIT_01;
assign O0 = mem0[a];
assign O1 = mem1[a];
always @(posedge clk)
if (WE) begin
mem0[a] <= D0;
mem1[a] <= D1;
end
endmodule
module RAM16X4S (
output O0, O1, O2, O3,
input A0, A1, A2, A3,
input D0, D1, D2, D3,
(* clkbuf_sink *)
(* invertible_pin = "IS_WCLK_INVERTED" *)
input WCLK,
input WE
);
parameter [15:0] INIT_00 = 16'h0000;
parameter [15:0] INIT_01 = 16'h0000;
parameter [15:0] INIT_02 = 16'h0000;
parameter [15:0] INIT_03 = 16'h0000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
wire [3:0] a = {A3, A2, A1, A0};
wire clk = WCLK ^ IS_WCLK_INVERTED;
reg [15:0] mem0 = INIT_00;
reg [15:0] mem1 = INIT_01;
reg [15:0] mem2 = INIT_02;
reg [15:0] mem3 = INIT_03;
assign O0 = mem0[a];
assign O1 = mem1[a];
assign O2 = mem2[a];
assign O3 = mem3[a];
always @(posedge clk)
if (WE) begin
mem0[a] <= D0;
mem1[a] <= D1;
mem2[a] <= D2;
mem3[a] <= D3;
end
endmodule
module RAM32X4S (
output O0, O1, O2, O3,
input A0, A1, A2, A3, A4,
input D0, D1, D2, D3,
(* clkbuf_sink *)
(* invertible_pin = "IS_WCLK_INVERTED" *)
input WCLK,
input WE
);
parameter [31:0] INIT_00 = 32'h00000000;
parameter [31:0] INIT_01 = 32'h00000000;
parameter [31:0] INIT_02 = 32'h00000000;
parameter [31:0] INIT_03 = 32'h00000000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
wire [4:0] a = {A4, A3, A2, A1, A0};
wire clk = WCLK ^ IS_WCLK_INVERTED;
reg [31:0] mem0 = INIT_00;
reg [31:0] mem1 = INIT_01;
reg [31:0] mem2 = INIT_02;
reg [31:0] mem3 = INIT_03;
assign O0 = mem0[a];
assign O1 = mem1[a];
assign O2 = mem2[a];
assign O3 = mem3[a];
always @(posedge clk)
if (WE) begin
mem0[a] <= D0;
mem1[a] <= D1;
mem2[a] <= D2;
mem3[a] <= D3;
end
endmodule
module RAM16X8S (
output [7:0] O,
input A0, A1, A2, A3,
input [7:0] D,
(* clkbuf_sink *)
(* invertible_pin = "IS_WCLK_INVERTED" *)
input WCLK,
input WE
);
parameter [15:0] INIT_00 = 16'h0000;
parameter [15:0] INIT_01 = 16'h0000;
parameter [15:0] INIT_02 = 16'h0000;
parameter [15:0] INIT_03 = 16'h0000;
parameter [15:0] INIT_04 = 16'h0000;
parameter [15:0] INIT_05 = 16'h0000;
parameter [15:0] INIT_06 = 16'h0000;
parameter [15:0] INIT_07 = 16'h0000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
wire [3:0] a = {A3, A2, A1, A0};
wire clk = WCLK ^ IS_WCLK_INVERTED;
reg [15:0] mem0 = INIT_00;
reg [15:0] mem1 = INIT_01;
reg [15:0] mem2 = INIT_02;
reg [15:0] mem3 = INIT_03;
reg [15:0] mem4 = INIT_04;
reg [15:0] mem5 = INIT_05;
reg [15:0] mem6 = INIT_06;
reg [15:0] mem7 = INIT_07;
assign O[0] = mem0[a];
assign O[1] = mem1[a];
assign O[2] = mem2[a];
assign O[3] = mem3[a];
assign O[4] = mem4[a];
assign O[5] = mem5[a];
assign O[6] = mem6[a];
assign O[7] = mem7[a];
always @(posedge clk)
if (WE) begin
mem0[a] <= D[0];
mem1[a] <= D[1];
mem2[a] <= D[2];
mem3[a] <= D[3];
mem4[a] <= D[4];
mem5[a] <= D[5];
mem6[a] <= D[6];
mem7[a] <= D[7];
end
endmodule
module RAM32X8S (
output [7:0] O,
input A0, A1, A2, A3, A4,
input [7:0] D,
(* clkbuf_sink *)
(* invertible_pin = "IS_WCLK_INVERTED" *)
input WCLK,
input WE
);
parameter [31:0] INIT_00 = 32'h00000000;
parameter [31:0] INIT_01 = 32'h00000000;
parameter [31:0] INIT_02 = 32'h00000000;
parameter [31:0] INIT_03 = 32'h00000000;
parameter [31:0] INIT_04 = 32'h00000000;
parameter [31:0] INIT_05 = 32'h00000000;
parameter [31:0] INIT_06 = 32'h00000000;
parameter [31:0] INIT_07 = 32'h00000000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
wire [4:0] a = {A4, A3, A2, A1, A0};
wire clk = WCLK ^ IS_WCLK_INVERTED;
reg [31:0] mem0 = INIT_00;
reg [31:0] mem1 = INIT_01;
reg [31:0] mem2 = INIT_02;
reg [31:0] mem3 = INIT_03;
reg [31:0] mem4 = INIT_04;
reg [31:0] mem5 = INIT_05;
reg [31:0] mem6 = INIT_06;
reg [31:0] mem7 = INIT_07;
assign O[0] = mem0[a];
assign O[1] = mem1[a];
assign O[2] = mem2[a];
assign O[3] = mem3[a];
assign O[4] = mem4[a];
assign O[5] = mem5[a];
assign O[6] = mem6[a];
assign O[7] = mem7[a];
always @(posedge clk)
if (WE) begin
mem0[a] <= D[0];
mem1[a] <= D[1];
mem2[a] <= D[2];
mem3[a] <= D[3];
mem4[a] <= D[4];
mem5[a] <= D[5];
mem6[a] <= D[6];
mem7[a] <= D[7];
end
endmodule
// Dual port.
module RAM16X1D (
output DPO, SPO,
input D,
(* clkbuf_sink *)
(* invertible_pin = "IS_WCLK_INVERTED" *)
input WCLK,
input WE,
input A0, A1, A2, A3,
input DPRA0, DPRA1, DPRA2, DPRA3
);
parameter INIT = 16'h0;
parameter IS_WCLK_INVERTED = 1'b0;
wire [3:0] a = {A3, A2, A1, A0};
wire [3:0] dpra = {DPRA3, DPRA2, DPRA1, DPRA0};
reg [15:0] mem = INIT;
assign SPO = mem[a];
assign DPO = mem[dpra];
wire clk = WCLK ^ IS_WCLK_INVERTED;
always @(posedge clk) if (WE) mem[a] <= D;
endmodule
module RAM16X1D_1 (
output DPO, SPO,
input D,
(* clkbuf_sink *)
(* invertible_pin = "IS_WCLK_INVERTED" *)
input WCLK,
input WE,
input A0, A1, A2, A3,
input DPRA0, DPRA1, DPRA2, DPRA3
);
parameter INIT = 16'h0;
parameter IS_WCLK_INVERTED = 1'b0;
wire [3:0] a = {A3, A2, A1, A0};
wire [3:0] dpra = {DPRA3, DPRA2, DPRA1, DPRA0};
reg [15:0] mem = INIT;
assign SPO = mem[a];
assign DPO = mem[dpra];
wire clk = WCLK ^ IS_WCLK_INVERTED;
always @(negedge clk) if (WE) mem[a] <= D;
endmodule
(* abc9_box, lib_whitebox *)
module RAM32X1D (
output DPO, SPO,
input D,
(* clkbuf_sink *)
(* invertible_pin = "IS_WCLK_INVERTED" *)
input WCLK,
input WE,
input A0, A1, A2, A3, A4,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
);
parameter INIT = 32'h0;
parameter IS_WCLK_INVERTED = 1'b0;
wire [4:0] a = {A4, A3, A2, A1, A0};
wire [4:0] dpra = {DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
reg [31:0] mem = INIT;
assign SPO = mem[a];
assign DPO = mem[dpra];
wire clk = WCLK ^ IS_WCLK_INVERTED;
always @(posedge clk) if (WE) mem[a] <= D;
specify
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
$setup(D , posedge WCLK &&& !IS_WCLK_INVERTED && WE, 453);
$setup(D , negedge WCLK &&& IS_WCLK_INVERTED && WE, 453);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
$setup(WE, posedge WCLK &&& !IS_WCLK_INVERTED, 654);
$setup(WE, negedge WCLK &&& IS_WCLK_INVERTED, 654);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L800
$setup(A0, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 245);
$setup(A0, negedge WCLK &&& IS_WCLK_INVERTED && WE, 245);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L798
$setup(A1, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 208);
$setup(A1, negedge WCLK &&& IS_WCLK_INVERTED && WE, 208);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L796
$setup(A2, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 147);
$setup(A2, negedge WCLK &&& IS_WCLK_INVERTED && WE, 147);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L794
$setup(A3, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 68);
$setup(A3, negedge WCLK &&& IS_WCLK_INVERTED && WE, 68);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792
$setup(A4, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 66);
$setup(A4, posedge WCLK &&& IS_WCLK_INVERTED && WE, 66);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
if (!IS_WCLK_INVERTED) (posedge WCLK => (SPO : D)) = 1153;
if (!IS_WCLK_INVERTED) (posedge WCLK => (DPO : 1'bx)) = 1153;
if ( IS_WCLK_INVERTED) (posedge WCLK => (SPO : D)) = 1153;
if ( IS_WCLK_INVERTED) (negedge WCLK => (DPO : 1'bx)) = 1153;
(A0 => SPO) = 642; (DPRA0 => DPO) = 642;
(A1 => SPO) = 632; (DPRA1 => DPO) = 631;
(A2 => SPO) = 472; (DPRA2 => DPO) = 472;
(A3 => SPO) = 407; (DPRA3 => DPO) = 407;
(A4 => SPO) = 238; (DPRA4 => DPO) = 238;
endspecify
endmodule
(* abc9_box, lib_whitebox *)
module RAM32X1D_1 (
output DPO, SPO,
input D,
(* clkbuf_sink *)
(* invertible_pin = "IS_WCLK_INVERTED" *)
input WCLK,
input WE,
input A0,
input A1,
input A2,
input A3,
input A4,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
);
parameter INIT = 32'h0;
parameter IS_WCLK_INVERTED = 1'b0;
wire [4:0] a = {A4, A3, A2, A1, A0};
wire [4:0] dpra = {DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
reg [31:0] mem = INIT;
assign SPO = mem[a];
assign DPO = mem[dpra];
wire clk = WCLK ^ IS_WCLK_INVERTED;
always @(negedge clk) if (WE) mem[a] <= D;
specify
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
$setup(D , negedge WCLK &&& WE, 453);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
$setup(WE, negedge WCLK, 654);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L800
$setup(A0, negedge WCLK &&& WE, 245);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L798
$setup(A1, negedge WCLK &&& WE, 208);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L796
$setup(A2, negedge WCLK &&& WE, 147);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L794
$setup(A3, negedge WCLK &&& WE, 68);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792
$setup(A4, negedge WCLK &&& WE, 66);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
if (WE) (negedge WCLK => (SPO : D)) = 1153;
if (WE) (negedge WCLK => (DPO : 1'bx)) = 1153;
(A0 => SPO) = 642; (DPRA0 => DPO) = 642;
(A1 => SPO) = 632; (DPRA1 => DPO) = 631;
(A2 => SPO) = 472; (DPRA2 => DPO) = 472;
(A3 => SPO) = 407; (DPRA3 => DPO) = 407;
(A4 => SPO) = 238; (DPRA4 => DPO) = 238;
endspecify
endmodule
(* abc9_box, lib_whitebox *)
module RAM64X1D (
output DPO, SPO,
input D,
(* clkbuf_sink *)
(* invertible_pin = "IS_WCLK_INVERTED" *)
input WCLK,
input WE,
input A0, A1, A2, A3, A4, A5,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
);
parameter INIT = 64'h0;
parameter IS_WCLK_INVERTED = 1'b0;
wire [5:0] a = {A5, A4, A3, A2, A1, A0};
wire [5:0] dpra = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
reg [63:0] mem = INIT;
assign SPO = mem[a];
assign DPO = mem[dpra];
wire clk = WCLK ^ IS_WCLK_INVERTED;
always @(posedge clk) if (WE) mem[a] <= D;
specify
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
$setup(D , posedge WCLK &&& !IS_WCLK_INVERTED && WE, 453);
$setup(D , negedge WCLK &&& IS_WCLK_INVERTED && WE, 453);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
$setup(WE, posedge WCLK &&& !IS_WCLK_INVERTED, 654);
$setup(WE, negedge WCLK &&& IS_WCLK_INVERTED, 654);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L828
$setup(A0, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 362);
$setup(A0, negedge WCLK &&& IS_WCLK_INVERTED && WE, 362);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L826
$setup(A1, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 245);
$setup(A1, negedge WCLK &&& IS_WCLK_INVERTED && WE, 245);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L824
$setup(A2, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 208);
$setup(A2, negedge WCLK &&& IS_WCLK_INVERTED && WE, 208);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L822
$setup(A3, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 147);
$setup(A3, negedge WCLK &&& IS_WCLK_INVERTED && WE, 147);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L820
$setup(A4, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 68);
$setup(A4, negedge WCLK &&& IS_WCLK_INVERTED && WE, 68);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818
$setup(A5, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 66);
$setup(A5, negedge WCLK &&& IS_WCLK_INVERTED && WE, 66);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (SPO : D)) = 1153;
if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DPO : 1'bx)) = 1153;
if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (SPO : D)) = 1153;
if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DPO : 1'bx)) = 1153;
(A0 => SPO) = 642; (DPRA0 => DPO) = 642;
(A1 => SPO) = 632; (DPRA1 => DPO) = 631;
(A2 => SPO) = 472; (DPRA2 => DPO) = 472;
(A3 => SPO) = 407; (DPRA3 => DPO) = 407;
(A4 => SPO) = 238; (DPRA4 => DPO) = 238;
(A5 => SPO) = 127; (DPRA5 => DPO) = 127;
endspecify
endmodule
module RAM64X1D_1 (
output DPO, SPO,
input D,
(* clkbuf_sink *)
(* invertible_pin = "IS_WCLK_INVERTED" *)
input WCLK,
input WE,
input A0, A1, A2, A3, A4, A5,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
);
parameter INIT = 64'h0;
parameter IS_WCLK_INVERTED = 1'b0;
wire [5:0] a = {A5, A4, A3, A2, A1, A0};
wire [5:0] dpra = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
reg [63:0] mem = INIT;
assign SPO = mem[a];
assign DPO = mem[dpra];
wire clk = WCLK ^ IS_WCLK_INVERTED;
always @(negedge clk) if (WE) mem[a] <= D;
specify
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
$setup(D , negedge WCLK &&& WE, 453);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
$setup(WE, negedge WCLK, 654);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L828
$setup(A0, negedge WCLK &&& WE, 362);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L826
$setup(A1, negedge WCLK &&& WE, 245);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L824
$setup(A2, negedge WCLK &&& WE, 208);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L822
$setup(A3, negedge WCLK &&& WE, 147);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L820
$setup(A4, negedge WCLK &&& WE, 68);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818
$setup(A5, negedge WCLK &&& WE, 66);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
if (WE) (negedge WCLK => (SPO : D)) = 1153;
if (WE) (negedge WCLK => (DPO : 1'bx)) = 1153;
(A0 => SPO) = 642; (DPRA0 => DPO) = 642;
(A1 => SPO) = 632; (DPRA1 => DPO) = 631;
(A2 => SPO) = 472; (DPRA2 => DPO) = 472;
(A3 => SPO) = 407; (DPRA3 => DPO) = 407;
(A4 => SPO) = 238; (DPRA4 => DPO) = 238;
(A5 => SPO) = 127; (DPRA5 => DPO) = 127;
endspecify
endmodule
(* abc9_box, lib_whitebox *)
module RAM128X1D (
output DPO, SPO,
input D,
(* clkbuf_sink *)
(* invertible_pin = "IS_WCLK_INVERTED" *)
input WCLK,
input WE,
input [6:0] A,
input [6:0] DPRA
);
parameter INIT = 128'h0;
parameter IS_WCLK_INVERTED = 1'b0;
reg [127:0] mem = INIT;
assign SPO = mem[A];
assign DPO = mem[DPRA];
wire clk = WCLK ^ IS_WCLK_INVERTED;
always @(posedge clk) if (WE) mem[A] <= D;
specify
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
$setup(D , posedge WCLK &&& !IS_WCLK_INVERTED && WE, 453);
$setup(D , negedge WCLK &&& IS_WCLK_INVERTED && WE, 453);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
$setup(WE, posedge WCLK &&& !IS_WCLK_INVERTED, 654);
$setup(WE, negedge WCLK &&& IS_WCLK_INVERTED, 654);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-830
$setup(A[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 616);
$setup(A[0], negedge WCLK &&& IS_WCLK_INVERTED && WE, 616);
$setup(A[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 362);
$setup(A[1], negedge WCLK &&& IS_WCLK_INVERTED && WE, 362);
$setup(A[2], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 245);
$setup(A[2], negedge WCLK &&& IS_WCLK_INVERTED && WE, 245);
$setup(A[3], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 208);
$setup(A[3], negedge WCLK &&& IS_WCLK_INVERTED && WE, 208);
$setup(A[4], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 147);
$setup(A[4], negedge WCLK &&& IS_WCLK_INVERTED && WE, 147);
$setup(A[5], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 68);
$setup(A[5], negedge WCLK &&& IS_WCLK_INVERTED && WE, 68);
$setup(A[6], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 66);
$setup(A[6], negedge WCLK &&& IS_WCLK_INVERTED && WE, 66);
`ifndef __ICARUS__
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (SPO : D)) = 1153 + 217 /* to cross F7AMUX */ + 175 /* AMUX */;
if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DPO : 1'bx)) = 1153 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
(A[0] => SPO) = 642 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
(A[1] => SPO) = 631 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
(A[2] => SPO) = 472 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
(A[3] => SPO) = 407 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
(A[4] => SPO) = 238 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
(A[5] => SPO) = 127 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
(A[6] => SPO) = 0 + 276 /* to select F7AMUX */ + 175 /* AMUX */;
(DPRA[0] => DPO) = 642 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
(DPRA[1] => DPO) = 631 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
(DPRA[2] => DPO) = 472 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
(DPRA[3] => DPO) = 407 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
(DPRA[4] => DPO) = 238 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
(DPRA[5] => DPO) = 127 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
(DPRA[6] => DPO) = 0 + 296 /* to select MUXF7 */ + 174 /* CMUX */;
`endif
endspecify
endmodule
module RAM256X1D (
output DPO, SPO,
input D,
(* clkbuf_sink *)
(* invertible_pin = "IS_WCLK_INVERTED" *)
input WCLK,
input WE,
input [7:0] A, DPRA
);
parameter INIT = 256'h0;
parameter IS_WCLK_INVERTED = 1'b0;
reg [255:0] mem = INIT;
assign SPO = mem[A];
assign DPO = mem[DPRA];
wire clk = WCLK ^ IS_WCLK_INVERTED;
always @(posedge clk) if (WE) mem[A] <= D;
endmodule
// Multi port.
(* abc9_box, lib_whitebox *)
module RAM32M (
output [1:0] DOA,
output [1:0] DOB,
output [1:0] DOC,
output [1:0] DOD,
input [4:0] ADDRA, ADDRB, ADDRC,
input [4:0] ADDRD,
input [1:0] DIA,
input [1:0] DIB,
input [1:0] DIC,
input [1:0] DID,
(* clkbuf_sink *)
(* invertible_pin = "IS_WCLK_INVERTED" *)
input WCLK,
input WE
);
parameter [63:0] INIT_A = 64'h0000000000000000;
parameter [63:0] INIT_B = 64'h0000000000000000;
parameter [63:0] INIT_C = 64'h0000000000000000;
parameter [63:0] INIT_D = 64'h0000000000000000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
reg [63:0] mem_a = INIT_A;
reg [63:0] mem_b = INIT_B;
reg [63:0] mem_c = INIT_C;
reg [63:0] mem_d = INIT_D;
assign DOA = mem_a[2*ADDRA+:2];
assign DOB = mem_b[2*ADDRB+:2];
assign DOC = mem_c[2*ADDRC+:2];
assign DOD = mem_d[2*ADDRD+:2];
wire clk = WCLK ^ IS_WCLK_INVERTED;
always @(posedge clk)
if (WE) begin
mem_a[2*ADDRD+:2] <= DIA;
mem_b[2*ADDRD+:2] <= DIB;
mem_c[2*ADDRD+:2] <= DIC;
mem_d[2*ADDRD+:2] <= DID;
end
specify
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
$setup(ADDRD[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 245);
$setup(ADDRD[0], negedge WCLK &&& IS_WCLK_INVERTED && WE, 245);
$setup(ADDRD[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 208);
$setup(ADDRD[1], negedge WCLK &&& IS_WCLK_INVERTED && WE, 208);
$setup(ADDRD[2], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 147);
$setup(ADDRD[2], negedge WCLK &&& IS_WCLK_INVERTED && WE, 147);
$setup(ADDRD[3], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 68);
$setup(ADDRD[3], negedge WCLK &&& IS_WCLK_INVERTED && WE, 68);
$setup(ADDRD[4], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 66);
$setup(ADDRD[4], negedge WCLK &&& IS_WCLK_INVERTED && WE, 66);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988
$setup(DIA[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 453);
$setup(DIA[0], negedge WCLK &&& IS_WCLK_INVERTED && WE, 453);
$setup(DIA[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 384);
$setup(DIA[1], negedge WCLK &&& IS_WCLK_INVERTED && WE, 384);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056
$setup(DIB[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 461);
$setup(DIB[0], negedge WCLK &&& IS_WCLK_INVERTED && WE, 461);
$setup(DIB[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 354);
$setup(DIB[1], negedge WCLK &&& IS_WCLK_INVERTED && WE, 354);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124
$setup(DIC[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 457);
$setup(DIC[0], negedge WCLK &&& IS_WCLK_INVERTED && WE, 457);
$setup(DIC[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 375);
$setup(DIC[1], negedge WCLK &&& IS_WCLK_INVERTED && WE, 375);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192
$setup(DID[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 310);
$setup(DID[0], negedge WCLK &&& IS_WCLK_INVERTED && WE, 310);
$setup(DID[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 334);
$setup(DID[1], negedge WCLK &&& IS_WCLK_INVERTED && WE, 334);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
$setup(WE, posedge WCLK &&& !IS_WCLK_INVERTED, 654);
$setup(WE, negedge WCLK &&& IS_WCLK_INVERTED, 654);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOA[0] : DIA[0])) = 1153;
if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOA[0] : DIA[0])) = 1153;
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L857
if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOA[1] : DIA[1])) = 1188;
if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOA[1] : DIA[1])) = 1188;
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOB[0] : DIB[0])) = 1161;
if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOB[0] : DIB[0])) = 1161;
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L925
if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOB[1] : DIB[1])) = 1187;
if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOB[1] : DIB[1])) = 1187;
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L993
if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOC[0] : DIC[0])) = 1158;
if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOC[0] : DIC[0])) = 1158;
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOC[1] : DIC[1])) = 1180;
if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOC[1] : DIC[1])) = 1180;
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOD[0] : DID[0])) = 1163;
if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOD[0] : DID[0])) = 1163;
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1061
if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOD[1] : DID[1])) = 1190;
if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOD[1] : DID[1])) = 1190;
(ADDRA[0] *> DOA) = 642; (ADDRB[0] *> DOB) = 642; (ADDRC[0] *> DOC) = 642; (ADDRD[0] *> DOD) = 642;
(ADDRA[1] *> DOA) = 631; (ADDRB[1] *> DOB) = 631; (ADDRC[1] *> DOC) = 631; (ADDRD[1] *> DOD) = 631;
(ADDRA[2] *> DOA) = 472; (ADDRB[2] *> DOB) = 472; (ADDRC[2] *> DOC) = 472; (ADDRD[2] *> DOD) = 472;
(ADDRA[3] *> DOA) = 407; (ADDRB[3] *> DOB) = 407; (ADDRC[3] *> DOC) = 407; (ADDRD[3] *> DOD) = 407;
(ADDRA[4] *> DOA) = 238; (ADDRB[4] *> DOB) = 238; (ADDRC[4] *> DOC) = 238; (ADDRD[4] *> DOD) = 238;
endspecify
endmodule
module RAM32M16 (
output [1:0] DOA,
output [1:0] DOB,
output [1:0] DOC,
output [1:0] DOD,
output [1:0] DOE,
output [1:0] DOF,
output [1:0] DOG,
output [1:0] DOH,
input [4:0] ADDRA,
input [4:0] ADDRB,
input [4:0] ADDRC,
input [4:0] ADDRD,
input [4:0] ADDRE,
input [4:0] ADDRF,
input [4:0] ADDRG,
input [4:0] ADDRH,
input [1:0] DIA,
input [1:0] DIB,
input [1:0] DIC,
input [1:0] DID,
input [1:0] DIE,
input [1:0] DIF,
input [1:0] DIG,
input [1:0] DIH,
(* clkbuf_sink *)
(* invertible_pin = "IS_WCLK_INVERTED" *)
input WCLK,
input WE
);
parameter [63:0] INIT_A = 64'h0000000000000000;
parameter [63:0] INIT_B = 64'h0000000000000000;
parameter [63:0] INIT_C = 64'h0000000000000000;
parameter [63:0] INIT_D = 64'h0000000000000000;
parameter [63:0] INIT_E = 64'h0000000000000000;
parameter [63:0] INIT_F = 64'h0000000000000000;
parameter [63:0] INIT_G = 64'h0000000000000000;
parameter [63:0] INIT_H = 64'h0000000000000000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
reg [63:0] mem_a = INIT_A;
reg [63:0] mem_b = INIT_B;
reg [63:0] mem_c = INIT_C;
reg [63:0] mem_d = INIT_D;
reg [63:0] mem_e = INIT_E;
reg [63:0] mem_f = INIT_F;
reg [63:0] mem_g = INIT_G;
reg [63:0] mem_h = INIT_H;
assign DOA = mem_a[2*ADDRA+:2];
assign DOB = mem_b[2*ADDRB+:2];
assign DOC = mem_c[2*ADDRC+:2];
assign DOD = mem_d[2*ADDRD+:2];
assign DOE = mem_e[2*ADDRE+:2];
assign DOF = mem_f[2*ADDRF+:2];
assign DOG = mem_g[2*ADDRG+:2];
assign DOH = mem_h[2*ADDRH+:2];
wire clk = WCLK ^ IS_WCLK_INVERTED;
always @(posedge clk)
if (WE) begin
mem_a[2*ADDRH+:2] <= DIA;
mem_b[2*ADDRH+:2] <= DIB;
mem_c[2*ADDRH+:2] <= DIC;
mem_d[2*ADDRH+:2] <= DID;
mem_e[2*ADDRH+:2] <= DIE;
mem_f[2*ADDRH+:2] <= DIF;
mem_g[2*ADDRH+:2] <= DIG;
mem_h[2*ADDRH+:2] <= DIH;
end
endmodule
(* abc9_box, lib_whitebox *)
module RAM64M (
output DOA,
output DOB,
output DOC,
output DOD,
input [5:0] ADDRA, ADDRB, ADDRC,
input [5:0] ADDRD,
input DIA,
input DIB,
input DIC,
input DID,
(* clkbuf_sink *)
(* invertible_pin = "IS_WCLK_INVERTED" *)
input WCLK,
input WE
);
parameter [63:0] INIT_A = 64'h0000000000000000;
parameter [63:0] INIT_B = 64'h0000000000000000;
parameter [63:0] INIT_C = 64'h0000000000000000;
parameter [63:0] INIT_D = 64'h0000000000000000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
reg [63:0] mem_a = INIT_A;
reg [63:0] mem_b = INIT_B;
reg [63:0] mem_c = INIT_C;
reg [63:0] mem_d = INIT_D;
assign DOA = mem_a[ADDRA];
assign DOB = mem_b[ADDRB];
assign DOC = mem_c[ADDRC];
assign DOD = mem_d[ADDRD];
wire clk = WCLK ^ IS_WCLK_INVERTED;
always @(posedge clk)
if (WE) begin
mem_a[ADDRD] <= DIA;
mem_b[ADDRD] <= DIB;
mem_c[ADDRD] <= DIC;
mem_d[ADDRD] <= DID;
end
specify
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-L830
$setup(ADDRD[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 362);
$setup(ADDRD[0], negedge WCLK &&& IS_WCLK_INVERTED && WE, 362);
$setup(ADDRD[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 245);
$setup(ADDRD[1], negedge WCLK &&& IS_WCLK_INVERTED && WE, 245);
$setup(ADDRD[2], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 208);
$setup(ADDRD[2], negedge WCLK &&& IS_WCLK_INVERTED && WE, 208);
$setup(ADDRD[3], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 147);
$setup(ADDRD[3], negedge WCLK &&& IS_WCLK_INVERTED && WE, 147);
$setup(ADDRD[4], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 68);
$setup(ADDRD[4], negedge WCLK &&& IS_WCLK_INVERTED && WE, 68);
$setup(ADDRD[5], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 66);
$setup(ADDRD[5], negedge WCLK &&& IS_WCLK_INVERTED && WE, 66);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988
$setup(DIA, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 384);
$setup(DIA, negedge WCLK &&& IS_WCLK_INVERTED && WE, 384);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056
$setup(DIB, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 354);
$setup(DIB, negedge WCLK &&& IS_WCLK_INVERTED && WE, 354);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124
$setup(DIC, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 375);
$setup(DIC, negedge WCLK &&& IS_WCLK_INVERTED && WE, 375);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192
$setup(DID, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 310);
$setup(DID, negedge WCLK &&& IS_WCLK_INVERTED && WE, 310);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
$setup(WE, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 654);
$setup(WE, negedge WCLK &&& IS_WCLK_INVERTED && WE, 654);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOA : DIA)) = 1153;
if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOA : DIA)) = 1153;
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOB : DIB)) = 1161;
if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOB : DIB)) = 1161;
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOC : DIC)) = 1158;
if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOC : DIC)) = 1158;
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOD : DID)) = 1163;
if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOD : DID)) = 1163;
(ADDRA[0] => DOA) = 642; (ADDRB[0] => DOB) = 642; (ADDRC[0] => DOC) = 642; (ADDRD[0] => DOD) = 642;
(ADDRA[1] => DOA) = 631; (ADDRB[1] => DOB) = 631; (ADDRC[1] => DOC) = 631; (ADDRD[1] => DOD) = 631;
(ADDRA[2] => DOA) = 472; (ADDRB[2] => DOB) = 472; (ADDRC[2] => DOC) = 472; (ADDRD[2] => DOD) = 472;
(ADDRA[3] => DOA) = 407; (ADDRB[3] => DOB) = 407; (ADDRC[3] => DOC) = 407; (ADDRD[3] => DOD) = 407;
(ADDRA[4] => DOA) = 238; (ADDRB[4] => DOB) = 238; (ADDRC[4] => DOC) = 238; (ADDRD[4] => DOD) = 238;
endspecify
endmodule
module RAM64M8 (
output DOA,
output DOB,
output DOC,
output DOD,
output DOE,
output DOF,
output DOG,
output DOH,
input [5:0] ADDRA,
input [5:0] ADDRB,
input [5:0] ADDRC,
input [5:0] ADDRD,
input [5:0] ADDRE,
input [5:0] ADDRF,
input [5:0] ADDRG,
input [5:0] ADDRH,
input DIA,
input DIB,
input DIC,
input DID,
input DIE,
input DIF,
input DIG,
input DIH,
(* clkbuf_sink *)
(* invertible_pin = "IS_WCLK_INVERTED" *)
input WCLK,
input WE
);
parameter [63:0] INIT_A = 64'h0000000000000000;
parameter [63:0] INIT_B = 64'h0000000000000000;
parameter [63:0] INIT_C = 64'h0000000000000000;
parameter [63:0] INIT_D = 64'h0000000000000000;
parameter [63:0] INIT_E = 64'h0000000000000000;
parameter [63:0] INIT_F = 64'h0000000000000000;
parameter [63:0] INIT_G = 64'h0000000000000000;
parameter [63:0] INIT_H = 64'h0000000000000000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
reg [63:0] mem_a = INIT_A;
reg [63:0] mem_b = INIT_B;
reg [63:0] mem_c = INIT_C;
reg [63:0] mem_d = INIT_D;
reg [63:0] mem_e = INIT_E;
reg [63:0] mem_f = INIT_F;
reg [63:0] mem_g = INIT_G;
reg [63:0] mem_h = INIT_H;
assign DOA = mem_a[ADDRA];
assign DOB = mem_b[ADDRB];
assign DOC = mem_c[ADDRC];
assign DOD = mem_d[ADDRD];
assign DOE = mem_e[ADDRE];
assign DOF = mem_f[ADDRF];
assign DOG = mem_g[ADDRG];
assign DOH = mem_h[ADDRH];
wire clk = WCLK ^ IS_WCLK_INVERTED;
always @(posedge clk)
if (WE) begin
mem_a[ADDRH] <= DIA;
mem_b[ADDRH] <= DIB;
mem_c[ADDRH] <= DIC;
mem_d[ADDRH] <= DID;
mem_e[ADDRH] <= DIE;
mem_f[ADDRH] <= DIF;
mem_g[ADDRH] <= DIG;
mem_h[ADDRH] <= DIH;
end
endmodule
// ROM.
module ROM16X1 (
output O,
input A0, A1, A2, A3
);
parameter [15:0] INIT = 16'h0;
assign O = INIT[{A3, A2, A1, A0}];
endmodule
module ROM32X1 (
output O,
input A0, A1, A2, A3, A4
);
parameter [31:0] INIT = 32'h0;
assign O = INIT[{A4, A3, A2, A1, A0}];
endmodule
module ROM64X1 (
output O,
input A0, A1, A2, A3, A4, A5
);
parameter [63:0] INIT = 64'h0;
assign O = INIT[{A5, A4, A3, A2, A1, A0}];
endmodule
module ROM128X1 (
output O,
input A0, A1, A2, A3, A4, A5, A6
);
parameter [127:0] INIT = 128'h0;
assign O = INIT[{A6, A5, A4, A3, A2, A1, A0}];
endmodule
module ROM256X1 (
output O,
input A0, A1, A2, A3, A4, A5, A6, A7
);
parameter [255:0] INIT = 256'h0;
assign O = INIT[{A7, A6, A5, A4, A3, A2, A1, A0}];
endmodule
// Shift registers.
(* abc9_box, lib_whitebox *)
module SRL16 (
output Q,
input A0, A1, A2, A3,
(* clkbuf_sink *)
input CLK,
input D
);
parameter [15:0] INIT = 16'h0000;
reg [15:0] r = INIT;
assign Q = r[{A3,A2,A1,A0}];
always @(posedge CLK) r <= { r[14:0], D };
specify
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
(posedge CLK => (Q : 1'bx)) = 1472;
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912
$setup(D , posedge CLK, 173);
(A0 => Q) = 631;
(A1 => Q) = 472;
(A2 => Q) = 407;
(A3 => Q) = 238;
endspecify
endmodule
(* abc9_box, lib_whitebox *)
module SRL16E (
output Q,
input A0, A1, A2, A3, CE,
(* clkbuf_sink *)
(* invertible_pin = "IS_CLK_INVERTED" *)
input CLK,
input D
);
parameter [15:0] INIT = 16'h0000;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
reg [15:0] r = INIT;
assign Q = r[{A3,A2,A1,A0}];
generate
if (IS_CLK_INVERTED) begin
always @(negedge CLK) if (CE) r <= { r[14:0], D };
end
else
always @(posedge CLK) if (CE) r <= { r[14:0], D };
endgenerate
specify
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912
$setup(D , posedge CLK &&& !IS_CLK_INVERTED, 173);
$setup(D , negedge CLK &&& IS_CLK_INVERTED, 173);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : D)) = 1472;
if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : D)) = 1472;
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : 1'bx)) = 1472;
if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : 1'bx)) = 1472;
(A0 => Q) = 631;
(A1 => Q) = 472;
(A2 => Q) = 407;
(A3 => Q) = 238;
endspecify
endmodule
(* abc9_box, lib_whitebox *)
module SRLC16 (
output Q,
output Q15,
input A0, A1, A2, A3,
(* clkbuf_sink *)
input CLK,
input D
);
parameter [15:0] INIT = 16'h0000;
reg [15:0] r = INIT;
assign Q15 = r[15];
assign Q = r[{A3,A2,A1,A0}];
always @(posedge CLK) r <= { r[14:0], D };
specify
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912
$setup(D , posedge CLK, 173);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
(posedge CLK => (Q : 1'bx)) = 1472;
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904
(posedge CLK => (Q15 : 1'bx)) = 1114;
(A0 => Q) = 631;
(A1 => Q) = 472;
(A2 => Q) = 407;
(A3 => Q) = 238;
endspecify
endmodule
(* abc9_box, lib_whitebox *)
module SRLC16E (
output Q,
output Q15,
input A0, A1, A2, A3, CE,
(* clkbuf_sink *)
(* invertible_pin = "IS_CLK_INVERTED" *)
input CLK,
input D
);
parameter [15:0] INIT = 16'h0000;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
reg [15:0] r = INIT;
assign Q15 = r[15];
assign Q = r[{A3,A2,A1,A0}];
generate
if (IS_CLK_INVERTED) begin
always @(negedge CLK) if (CE) r <= { r[14:0], D };
end
else
always @(posedge CLK) if (CE) r <= { r[14:0], D };
endgenerate
specify
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912
$setup(D , posedge CLK &&& !IS_CLK_INVERTED, 173);
$setup(D , negedge CLK &&& IS_CLK_INVERTED, 173);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
$setup(CE, posedge CLK &&& !IS_CLK_INVERTED, 109);
$setup(CE, negedge CLK &&& IS_CLK_INVERTED, 109);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : D)) = 1472;
if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : D)) = 1472;
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904
if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q15 : 1'bx)) = 1114;
if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q15 : 1'bx)) = 1114;
(A0 => Q) = 631;
(A1 => Q) = 472;
(A2 => Q) = 407;
(A3 => Q) = 238;
endspecify
endmodule
(* abc9_box, lib_whitebox *)
module SRLC32E (
output Q,
output Q31,
input [4:0] A,
input CE,
(* clkbuf_sink *)
(* invertible_pin = "IS_CLK_INVERTED" *)
input CLK,
input D
);
parameter [31:0] INIT = 32'h00000000;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
reg [31:0] r = INIT;
assign Q31 = r[31];
assign Q = r[A];
generate
if (IS_CLK_INVERTED) begin
always @(negedge CLK) if (CE) r <= { r[30:0], D };
end
else
always @(posedge CLK) if (CE) r <= { r[30:0], D };
endgenerate
specify
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912
$setup(D , posedge CLK &&& !IS_CLK_INVERTED, 173);
$setup(D , negedge CLK &&& IS_CLK_INVERTED, 173);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
$setup(CE, posedge CLK &&& !IS_CLK_INVERTED, 109);
$setup(CE, negedge CLK &&& IS_CLK_INVERTED, 109);
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : 1'bx)) = 1472;
if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : 1'bx)) = 1472;
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904
if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q31 : 1'bx)) = 1114;
if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q31 : 1'bx)) = 1114;
(A[0] => Q) = 642;
(A[1] => Q) = 631;
(A[2] => Q) = 472;
(A[3] => Q) = 407;
(A[4] => Q) = 238;
endspecify
endmodule
module CFGLUT5 (
output CDO,
output O5,
output O6,
input I4,
input I3,
input I2,
input I1,
input I0,
input CDI,
input CE,
(* clkbuf_sink *)
(* invertible_pin = "IS_CLK_INVERTED" *)
input CLK
);
parameter [31:0] INIT = 32'h00000000;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
wire clk = CLK ^ IS_CLK_INVERTED;
reg [31:0] r = INIT;
assign CDO = r[31];
assign O5 = r[{1'b0, I3, I2, I1, I0}];
assign O6 = r[{I4, I3, I2, I1, I0}];
always @(posedge clk) if (CE) r <= {r[30:0], CDI};
endmodule
// DSP
// Virtex 2, Virtex 2 Pro, Spartan 3.
// Asynchronous mode.
module MULT18X18 (
input signed [17:0] A,
input signed [17:0] B,
output signed [35:0] P
);
assign P = A * B;
endmodule
// Synchronous mode.
module MULT18X18S (
input signed [17:0] A,
input signed [17:0] B,
output reg signed [35:0] P,
(* clkbuf_sink *)
input C,
input CE,
input R
);
always @(posedge C)
if (R)
P <= 0;
else if (CE)
P <= A * B;
endmodule
// Spartan 3E, Spartan 3A.
module MULT18X18SIO (
input signed [17:0] A,
input signed [17:0] B,
output signed [35:0] P,
(* clkbuf_sink *)
input CLK,
input CEA,
input CEB,
input CEP,
input RSTA,
input RSTB,
input RSTP,
input signed [17:0] BCIN,
output signed [17:0] BCOUT
);
parameter integer AREG = 1;
parameter integer BREG = 1;
parameter B_INPUT = "DIRECT";
parameter integer PREG = 1;
// The multiplier.
wire signed [35:0] P_MULT;
wire signed [17:0] A_MULT;
wire signed [17:0] B_MULT;
assign P_MULT = A_MULT * B_MULT;
// The cascade output.
assign BCOUT = B_MULT;
// The B input multiplexer.
wire signed [17:0] B_MUX;
assign B_MUX = (B_INPUT == "DIRECT") ? B : BCIN;
// The registers.
reg signed [17:0] A_REG;
reg signed [17:0] B_REG;
reg signed [35:0] P_REG;
initial begin
A_REG = 0;
B_REG = 0;
P_REG = 0;
end
always @(posedge CLK) begin
if (RSTA)
A_REG <= 0;
else if (CEA)
A_REG <= A;
if (RSTB)
B_REG <= 0;
else if (CEB)
B_REG <= B_MUX;
if (RSTP)
P_REG <= 0;
else if (CEP)
P_REG <= P_MULT;
end
// The register enables.
assign A_MULT = (AREG == 1) ? A_REG : A;
assign B_MULT = (BREG == 1) ? B_REG : B_MUX;
assign P = (PREG == 1) ? P_REG : P_MULT;
endmodule
// Spartan 3A DSP.
module DSP48A (
input signed [17:0] A,
input signed [17:0] B,
input signed [47:0] C,
input signed [17:0] D,
input signed [47:0] PCIN,
input CARRYIN,
input [7:0] OPMODE,
output signed [47:0] P,
output signed [17:0] BCOUT,
output signed [47:0] PCOUT,
output CARRYOUT,
(* clkbuf_sink *)
input CLK,
input CEA,
input CEB,
input CEC,
input CED,
input CEM,
input CECARRYIN,
input CEOPMODE,
input CEP,
input RSTA,
input RSTB,
input RSTC,
input RSTD,
input RSTM,
input RSTCARRYIN,
input RSTOPMODE,
input RSTP
);
parameter integer A0REG = 0;
parameter integer A1REG = 1;
parameter integer B0REG = 0;
parameter integer B1REG = 1;
parameter integer CREG = 1;
parameter integer DREG = 1;
parameter integer MREG = 1;
parameter integer CARRYINREG = 1;
parameter integer OPMODEREG = 1;
parameter integer PREG = 1;
parameter CARRYINSEL = "CARRYIN";
parameter RSTTYPE = "SYNC";
// This is a strict subset of Spartan 6 -- reuse its model.
/* verilator lint_off PINMISSING */
DSP48A1 #(
.A0REG(A0REG),
.A1REG(A1REG),
.B0REG(B0REG),
.B1REG(B1REG),
.CREG(CREG),
.DREG(DREG),
.MREG(MREG),
.CARRYINREG(CARRYINREG),
.CARRYOUTREG(0),
.OPMODEREG(OPMODEREG),
.PREG(PREG),
.CARRYINSEL(CARRYINSEL),
.RSTTYPE(RSTTYPE)
) upgrade (
.A(A),
.B(B),
.C(C),
.D(D),
.PCIN(PCIN),
.CARRYIN(CARRYIN),
.OPMODE(OPMODE),
// M unconnected
.P(P),
.BCOUT(BCOUT),
.PCOUT(PCOUT),
.CARRYOUT(CARRYOUT),
// CARRYOUTF unconnected
.CLK(CLK),
.CEA(CEA),
.CEB(CEB),
.CEC(CEC),
.CED(CED),
.CEM(CEM),
.CECARRYIN(CECARRYIN),
.CEOPMODE(CEOPMODE),
.CEP(CEP),
.RSTA(RSTA),
.RSTB(RSTB),
.RSTC(RSTC),
.RSTD(RSTD),
.RSTM(RSTM),
.RSTCARRYIN(RSTCARRYIN),
.RSTOPMODE(RSTOPMODE),
.RSTP(RSTP)
);
/* verilator lint_on PINMISSING */
endmodule
// Spartan 6.
module DSP48A1 (
input signed [17:0] A,
input signed [17:0] B,
input signed [47:0] C,
input signed [17:0] D,
input signed [47:0] PCIN,
input CARRYIN,
input [7:0] OPMODE,
output signed [35:0] M,
output signed [47:0] P,
output signed [17:0] BCOUT,
output signed [47:0] PCOUT,
output CARRYOUT,
output CARRYOUTF,
(* clkbuf_sink *)
input CLK,
input CEA,
input CEB,
input CEC,
input CED,
input CEM,
input CECARRYIN,
input CEOPMODE,
input CEP,
input RSTA,
input RSTB,
input RSTC,
input RSTD,
input RSTM,
input RSTCARRYIN,
input RSTOPMODE,
input RSTP
);
parameter integer A0REG = 0;
parameter integer A1REG = 1;
parameter integer B0REG = 0;
parameter integer B1REG = 1;
parameter integer CREG = 1;
parameter integer DREG = 1;
parameter integer MREG = 1;
parameter integer CARRYINREG = 1;
parameter integer CARRYOUTREG = 1;
parameter integer OPMODEREG = 1;
parameter integer PREG = 1;
parameter CARRYINSEL = "OPMODE5";
parameter RSTTYPE = "SYNC";
wire signed [35:0] M_MULT;
wire signed [47:0] P_IN;
wire signed [17:0] A0_OUT;
wire signed [17:0] B0_OUT;
wire signed [17:0] A1_OUT;
wire signed [17:0] B1_OUT;
wire signed [17:0] B1_IN;
wire signed [47:0] C_OUT;
wire signed [17:0] D_OUT;
wire signed [7:0] OPMODE_OUT;
wire CARRYIN_OUT;
wire CARRYOUT_IN;
wire CARRYIN_IN;
reg signed [47:0] XMUX;
reg signed [47:0] ZMUX;
// The registers.
reg signed [17:0] A0_REG;
reg signed [17:0] A1_REG;
reg signed [17:0] B0_REG;
reg signed [17:0] B1_REG;
reg signed [47:0] C_REG;
reg signed [17:0] D_REG;
reg signed [35:0] M_REG;
reg signed [47:0] P_REG;
reg [7:0] OPMODE_REG;
reg CARRYIN_REG;
reg CARRYOUT_REG;
initial begin
A0_REG = 0;
A1_REG = 0;
B0_REG = 0;
B1_REG = 0;
C_REG = 0;
D_REG = 0;
M_REG = 0;
P_REG = 0;
OPMODE_REG = 0;
CARRYIN_REG = 0;
CARRYOUT_REG = 0;
end
generate
if (RSTTYPE == "SYNC") begin
always @(posedge CLK) begin
if (RSTA) begin
A0_REG <= 0;
A1_REG <= 0;
end else if (CEA) begin
A0_REG <= A;
A1_REG <= A0_OUT;
end
end
always @(posedge CLK) begin
if (RSTB) begin
B0_REG <= 0;
B1_REG <= 0;
end else if (CEB) begin
B0_REG <= B;
B1_REG <= B1_IN;
end
end
always @(posedge CLK) begin
if (RSTC) begin
C_REG <= 0;
end else if (CEC) begin
C_REG <= C;
end
end
always @(posedge CLK) begin
if (RSTD) begin
D_REG <= 0;
end else if (CED) begin
D_REG <= D;
end
end
always @(posedge CLK) begin
if (RSTM) begin
M_REG <= 0;
end else if (CEM) begin
M_REG <= M_MULT;
end
end
always @(posedge CLK) begin
if (RSTP) begin
P_REG <= 0;
end else if (CEP) begin
P_REG <= P_IN;
end
end
always @(posedge CLK) begin
if (RSTOPMODE) begin
OPMODE_REG <= 0;
end else if (CEOPMODE) begin
OPMODE_REG <= OPMODE;
end
end
always @(posedge CLK) begin
if (RSTCARRYIN) begin
CARRYIN_REG <= 0;
CARRYOUT_REG <= 0;
end else if (CECARRYIN) begin
CARRYIN_REG <= CARRYIN_IN;
CARRYOUT_REG <= CARRYOUT_IN;
end
end
end else begin
always @(posedge CLK, posedge RSTA) begin
if (RSTA) begin
A0_REG <= 0;
A1_REG <= 0;
end else if (CEA) begin
A0_REG <= A;
A1_REG <= A0_OUT;
end
end
always @(posedge CLK, posedge RSTB) begin
if (RSTB) begin
B0_REG <= 0;
B1_REG <= 0;
end else if (CEB) begin
B0_REG <= B;
B1_REG <= B1_IN;
end
end
always @(posedge CLK, posedge RSTC) begin
if (RSTC) begin
C_REG <= 0;
end else if (CEC) begin
C_REG <= C;
end
end
always @(posedge CLK, posedge RSTD) begin
if (RSTD) begin
D_REG <= 0;
end else if (CED) begin
D_REG <= D;
end
end
always @(posedge CLK, posedge RSTM) begin
if (RSTM) begin
M_REG <= 0;
end else if (CEM) begin
M_REG <= M_MULT;
end
end
always @(posedge CLK, posedge RSTP) begin
if (RSTP) begin
P_REG <= 0;
end else if (CEP) begin
P_REG <= P_IN;
end
end
always @(posedge CLK, posedge RSTOPMODE) begin
if (RSTOPMODE) begin
OPMODE_REG <= 0;
end else if (CEOPMODE) begin
OPMODE_REG <= OPMODE;
end
end
always @(posedge CLK, posedge RSTCARRYIN) begin
if (RSTCARRYIN) begin
CARRYIN_REG <= 0;
CARRYOUT_REG <= 0;
end else if (CECARRYIN) begin
CARRYIN_REG <= CARRYIN_IN;
CARRYOUT_REG <= CARRYOUT_IN;
end
end
end
endgenerate
// The register enables.
assign A0_OUT = (A0REG == 1) ? A0_REG : A;
assign A1_OUT = (A1REG == 1) ? A1_REG : A0_OUT;
assign B0_OUT = (B0REG == 1) ? B0_REG : B;
assign B1_OUT = (B1REG == 1) ? B1_REG : B1_IN;
assign C_OUT = (CREG == 1) ? C_REG : C;
assign D_OUT = (DREG == 1) ? D_REG : D;
assign M = (MREG == 1) ? M_REG : M_MULT;
assign P = (PREG == 1) ? P_REG : P_IN;
assign OPMODE_OUT = (OPMODEREG == 1) ? OPMODE_REG : OPMODE;
assign CARRYIN_OUT = (CARRYINREG == 1) ? CARRYIN_REG : CARRYIN_IN;
assign CARRYOUT = (CARRYOUTREG == 1) ? CARRYOUT_REG : CARRYOUT_IN;
assign CARRYOUTF = CARRYOUT;
// The pre-adder.
wire signed [17:0] PREADDER;
assign B1_IN = OPMODE_OUT[4] ? PREADDER : B0_OUT;
assign PREADDER = OPMODE_OUT[6] ? D_OUT - B0_OUT : D_OUT + B0_OUT;
// The multiplier.
assign M_MULT = A1_OUT * B1_OUT;
// The carry in selection.
assign CARRYIN_IN = (CARRYINSEL == "OPMODE5") ? OPMODE_OUT[5] : CARRYIN;
// The post-adder inputs.
always @* begin
case (OPMODE_OUT[1:0])
2'b00: XMUX <= 0;
2'b01: XMUX <= M;
2'b10: XMUX <= P;
2'b11: XMUX <= {D_OUT[11:0], A1_OUT, B1_OUT};
default: XMUX <= 48'hxxxxxxxxxxxx;
endcase
end
always @* begin
case (OPMODE_OUT[3:2])
2'b00: ZMUX <= 0;
2'b01: ZMUX <= PCIN;
2'b10: ZMUX <= P;
2'b11: ZMUX <= C_OUT;
default: ZMUX <= 48'hxxxxxxxxxxxx;
endcase
end
// The post-adder.
wire signed [48:0] X_EXT;
wire signed [48:0] Z_EXT;
assign X_EXT = {1'b0, XMUX};
assign Z_EXT = {1'b0, ZMUX};
assign {CARRYOUT_IN, P_IN} = OPMODE_OUT[7] ? (Z_EXT - (X_EXT + CARRYIN_OUT)) : (Z_EXT + X_EXT + CARRYIN_OUT);
// Cascade outputs.
assign BCOUT = B1_OUT;
assign PCOUT = P;
endmodule
module DSP48 (
input signed [17:0] A,
input signed [17:0] B,
input signed [47:0] C,
input signed [17:0] BCIN,
input signed [47:0] PCIN,
input CARRYIN,
input [6:0] OPMODE,
input SUBTRACT,
input [1:0] CARRYINSEL,
output signed [47:0] P,
output signed [17:0] BCOUT,
output signed [47:0] PCOUT,
(* clkbuf_sink *)
input CLK,
input CEA,
input CEB,
input CEC,
input CEM,
input CECARRYIN,
input CECINSUB,
input CECTRL,
input CEP,
input RSTA,
input RSTB,
input RSTC,
input RSTM,
input RSTCARRYIN,
input RSTCTRL,
input RSTP
);
parameter integer AREG = 1;
parameter integer BREG = 1;
parameter integer CREG = 1;
parameter integer MREG = 1;
parameter integer PREG = 1;
parameter integer CARRYINREG = 1;
parameter integer CARRYINSELREG = 1;
parameter integer OPMODEREG = 1;
parameter integer SUBTRACTREG = 1;
parameter B_INPUT = "DIRECT";
parameter LEGACY_MODE = "MULT18X18S";
wire signed [17:0] A_OUT;
wire signed [17:0] B_OUT;
wire signed [47:0] C_OUT;
wire signed [35:0] M_MULT;
wire signed [35:0] M_OUT;
wire signed [47:0] P_IN;
wire [6:0] OPMODE_OUT;
wire [1:0] CARRYINSEL_OUT;
wire CARRYIN_OUT;
wire SUBTRACT_OUT;
reg INT_CARRYIN_XY;
reg INT_CARRYIN_Z;
reg signed [47:0] XMUX;
reg signed [47:0] YMUX;
wire signed [47:0] XYMUX;
reg signed [47:0] ZMUX;
reg CIN;
// The B input multiplexer.
wire signed [17:0] B_MUX;
assign B_MUX = (B_INPUT == "DIRECT") ? B : BCIN;
// The cascade output.
assign BCOUT = B_OUT;
assign PCOUT = P;
// The registers.
reg signed [17:0] A0_REG;
reg signed [17:0] A1_REG;
reg signed [17:0] B0_REG;
reg signed [17:0] B1_REG;
reg signed [47:0] C_REG;
reg signed [35:0] M_REG;
reg signed [47:0] P_REG;
reg [6:0] OPMODE_REG;
reg [1:0] CARRYINSEL_REG;
reg SUBTRACT_REG;
reg CARRYIN_REG;
reg INT_CARRYIN_XY_REG;
initial begin
A0_REG = 0;
A1_REG = 0;
B0_REG = 0;
B1_REG = 0;
C_REG = 0;
M_REG = 0;
P_REG = 0;
OPMODE_REG = 0;
CARRYINSEL_REG = 0;
SUBTRACT_REG = 0;
CARRYIN_REG = 0;
INT_CARRYIN_XY_REG = 0;
end
always @(posedge CLK) begin
if (RSTA) begin
A0_REG <= 0;
A1_REG <= 0;
end else if (CEA) begin
A0_REG <= A;
A1_REG <= A0_REG;
end
if (RSTB) begin
B0_REG <= 0;
B1_REG <= 0;
end else if (CEB) begin
B0_REG <= B_MUX;
B1_REG <= B0_REG;
end
if (RSTC) begin
C_REG <= 0;
end else if (CEC) begin
C_REG <= C;
end
if (RSTM) begin
M_REG <= 0;
end else if (CEM) begin
M_REG <= M_MULT;
end
if (RSTP) begin
P_REG <= 0;
end else if (CEP) begin
P_REG <= P_IN;
end
if (RSTCTRL) begin
OPMODE_REG <= 0;
CARRYINSEL_REG <= 0;
SUBTRACT_REG <= 0;
end else begin
if (CECTRL) begin
OPMODE_REG <= OPMODE;
CARRYINSEL_REG <= CARRYINSEL;
end
if (CECINSUB)
SUBTRACT_REG <= SUBTRACT;
end
if (RSTCARRYIN) begin
CARRYIN_REG <= 0;
INT_CARRYIN_XY_REG <= 0;
end else begin
if (CECINSUB)
CARRYIN_REG <= CARRYIN;
if (CECARRYIN)
INT_CARRYIN_XY_REG <= INT_CARRYIN_XY;
end
end
// The register enables.
assign A_OUT = (AREG == 2) ? A1_REG : (AREG == 1) ? A0_REG : A;
assign B_OUT = (BREG == 2) ? B1_REG : (BREG == 1) ? B0_REG : B_MUX;
assign C_OUT = (CREG == 1) ? C_REG : C;
assign M_OUT = (MREG == 1) ? M_REG : M_MULT;
assign P = (PREG == 1) ? P_REG : P_IN;
assign OPMODE_OUT = (OPMODEREG == 1) ? OPMODE_REG : OPMODE;
assign SUBTRACT_OUT = (SUBTRACTREG == 1) ? SUBTRACT_REG : SUBTRACT;
assign CARRYINSEL_OUT = (CARRYINSELREG == 1) ? CARRYINSEL_REG : CARRYINSEL;
assign CARRYIN_OUT = (CARRYINREG == 1) ? CARRYIN_REG : CARRYIN;
// The multiplier.
assign M_MULT = A_OUT * B_OUT;
// The post-adder inputs.
always @* begin
case (OPMODE_OUT[1:0])
2'b00: XMUX <= 0;
2'b10: XMUX <= P;
2'b11: XMUX <= {{12{A_OUT[17]}}, A_OUT, B_OUT};
default: XMUX <= 48'hxxxxxxxxxxxx;
endcase
case (OPMODE_OUT[1:0])
2'b01: INT_CARRYIN_XY <= A_OUT[17] ~^ B_OUT[17];
2'b11: INT_CARRYIN_XY <= ~A_OUT[17];
// TODO: not tested in hardware.
default: INT_CARRYIN_XY <= A_OUT[17] ~^ B_OUT[17];
endcase
end
always @* begin
case (OPMODE_OUT[3:2])
2'b00: YMUX <= 0;
2'b11: YMUX <= C_OUT;
default: YMUX <= 48'hxxxxxxxxxxxx;
endcase
end
assign XYMUX = (OPMODE_OUT[3:0] == 4'b0101) ? M_OUT : (XMUX + YMUX);
always @* begin
case (OPMODE_OUT[6:4])
3'b000: ZMUX <= 0;
3'b001: ZMUX <= PCIN;
3'b010: ZMUX <= P;
3'b011: ZMUX <= C_OUT;
3'b101: ZMUX <= {{17{PCIN[47]}}, PCIN[47:17]};
3'b110: ZMUX <= {{17{P[47]}}, P[47:17]};
default: ZMUX <= 48'hxxxxxxxxxxxx;
endcase
// TODO: check how all this works on actual hw.
if (OPMODE_OUT[1:0] == 2'b10)
INT_CARRYIN_Z <= ~P[47];
else
case (OPMODE_OUT[6:4])
3'b001: INT_CARRYIN_Z <= ~PCIN[47];
3'b010: INT_CARRYIN_Z <= ~P[47];
3'b101: INT_CARRYIN_Z <= ~PCIN[47];
3'b110: INT_CARRYIN_Z <= ~P[47];
default: INT_CARRYIN_Z <= 1'bx;
endcase
end
always @* begin
case (CARRYINSEL_OUT)
2'b00: CIN <= CARRYIN_OUT;
2'b01: CIN <= INT_CARRYIN_Z;
2'b10: CIN <= INT_CARRYIN_XY;
2'b11: CIN <= INT_CARRYIN_XY_REG;
default: CIN <= 1'bx;
endcase
end
// The post-adder.
assign P_IN = SUBTRACT_OUT ? (ZMUX - (XYMUX + CIN)) : (ZMUX + XYMUX + CIN);
endmodule
// TODO: DSP48E (Virtex 5).
// Virtex 6, Series 7.
`ifdef YOSYS
(* abc9_box=!(PREG || AREG || ADREG || BREG || CREG || DREG || MREG)
`ifdef ALLOW_WHITEBOX_DSP48E1
// Do not make DSP48E1 a whitebox for ABC9 even if fully combinatorial, since it is a big complex block
, lib_whitebox=!(PREG || AREG || ADREG || BREG || CREG || DREG || MREG || INMODEREG || OPMODEREG || ALUMODEREG || CARRYINREG || CARRYINSELREG)
`endif
*)
`endif
module DSP48E1 (
output [29:0] ACOUT,
output [17:0] BCOUT,
output reg CARRYCASCOUT,
output reg [3:0] CARRYOUT,
output reg MULTSIGNOUT,
output OVERFLOW,
output reg signed [47:0] P,
output reg PATTERNBDETECT,
output reg PATTERNDETECT,
output [47:0] PCOUT,
output UNDERFLOW,
input signed [29:0] A,
input [29:0] ACIN,
input [3:0] ALUMODE,
input signed [17:0] B,
input [17:0] BCIN,
input [47:0] C,
input CARRYCASCIN,
input CARRYIN,
input [2:0] CARRYINSEL,
input CEA1,
input CEA2,
input CEAD,
input CEALUMODE,
input CEB1,
input CEB2,
input CEC,
input CECARRYIN,
input CECTRL,
input CED,
input CEINMODE,
input CEM,
input CEP,
(* clkbuf_sink *) input CLK,
input [24:0] D,
input [4:0] INMODE,
input MULTSIGNIN,
input [6:0] OPMODE,
input [47:0] PCIN,
input RSTA,
input RSTALLCARRYIN,
input RSTALUMODE,
input RSTB,
input RSTC,
input RSTCTRL,
input RSTD,
input RSTINMODE,
input RSTM,
input RSTP
);
parameter integer ACASCREG = 1;
parameter integer ADREG = 1;
parameter integer ALUMODEREG = 1;
parameter integer AREG = 1;
parameter AUTORESET_PATDET = "NO_RESET";
parameter A_INPUT = "DIRECT";
parameter integer BCASCREG = 1;
parameter integer BREG = 1;
parameter B_INPUT = "DIRECT";
parameter integer CARRYINREG = 1;
parameter integer CARRYINSELREG = 1;
parameter integer CREG = 1;
parameter integer DREG = 1;
parameter integer INMODEREG = 1;
parameter integer MREG = 1;
parameter integer OPMODEREG = 1;
parameter integer PREG = 1;
parameter SEL_MASK = "MASK";
parameter SEL_PATTERN = "PATTERN";
parameter USE_DPORT = "FALSE";
parameter USE_MULT = "MULTIPLY";
parameter USE_PATTERN_DETECT = "NO_PATDET";
parameter USE_SIMD = "ONE48";
parameter [47:0] MASK = 48'h3FFFFFFFFFFF;
parameter [47:0] PATTERN = 48'h000000000000;
parameter [3:0] IS_ALUMODE_INVERTED = 4'b0;
parameter [0:0] IS_CARRYIN_INVERTED = 1'b0;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
parameter [4:0] IS_INMODE_INVERTED = 5'b0;
parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
`ifdef YOSYS
function integer \A.required ;
begin
if (AREG != 0) \A.required = 254;
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
if (MREG != 0) \A.required = 1416;
else if (PREG != 0) \A.required = (USE_PATTERN_DETECT != "NO_PATDET" ? 3030 : 2739) ;
end
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin
// Worst-case from ADREG and MREG
if (MREG != 0) \A.required = 2400;
else if (ADREG != 0) \A.required = 1283;
else if (PREG != 0) \A.required = 3723;
else if (PREG != 0) \A.required = (USE_PATTERN_DETECT != "NO_PATDET" ? 4014 : 3723) ;
end
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin
if (PREG != 0) \A.required = (USE_PATTERN_DETECT != "NO_PATDET" ? 1730 : 1441) ;
end
end
endfunction
function integer \B.required ;
begin
if (BREG != 0) \B.required = 324;
else if (MREG != 0) \B.required = 1285;
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
if (PREG != 0) \B.required = (USE_PATTERN_DETECT != "NO_PATDET" ? 2898 : 2608) ;
end
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin
if (PREG != 0) \B.required = (USE_PATTERN_DETECT != "NO_PATDET" ? 2898 : 2608) ;
end
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin
if (PREG != 0) \B.required = (USE_PATTERN_DETECT != "NO_PATDET" ? 1718 : 1428) ;
end
end
endfunction
function integer \C.required ;
begin
if (CREG != 0) \C.required = 168;
else if (PREG != 0) \C.required = (USE_PATTERN_DETECT != "NO_PATDET" ? 1534 : 1244) ;
end
endfunction
function integer \D.required ;
begin
if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
end
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin
if (DREG != 0) \D.required = 248;
else if (ADREG != 0) \D.required = 1195;
else if (MREG != 0) \D.required = 2310;
else if (PREG != 0) \D.required = (USE_PATTERN_DETECT != "NO_PATDET" ? 3925 : 3635) ;
end
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin
end
end
endfunction
function integer \P.arrival ;
begin
if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
if (PREG != 0) \P.arrival = 329;
// Worst-case from CREG and MREG
else if (CREG != 0) \P.arrival = 1687;
else if (MREG != 0) \P.arrival = 1671;
// Worst-case from AREG and BREG
else if (AREG != 0) \P.arrival = 2952;
else if (BREG != 0) \P.arrival = 2813;
end
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin
if (PREG != 0) \P.arrival = 329;
// Worst-case from CREG and MREG
else if (CREG != 0) \P.arrival = 1687;
else if (MREG != 0) \P.arrival = 1671;
// Worst-case from AREG, ADREG, BREG, DREG
else if (AREG != 0) \P.arrival = 3935;
else if (DREG != 0) \P.arrival = 3908;
else if (ADREG != 0) \P.arrival = 2958;
else if (BREG != 0) \P.arrival = 2813;
end
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin
if (PREG != 0) \P.arrival = 329;
// Worst-case from AREG, BREG, CREG
else if (CREG != 0) \P.arrival = 1687;
else if (AREG != 0) \P.arrival = 1632;
else if (BREG != 0) \P.arrival = 1616;
end
end
endfunction
function integer \PCOUT.arrival ;
begin
if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
if (PREG != 0) \PCOUT.arrival = 435;
// Worst-case from CREG and MREG
else if (CREG != 0) \PCOUT.arrival = 1835;
else if (MREG != 0) \PCOUT.arrival = 1819;
// Worst-case from AREG and BREG
else if (AREG != 0) \PCOUT.arrival = 3098;
else if (BREG != 0) \PCOUT.arrival = 2960;
end
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin
if (PREG != 0) \PCOUT.arrival = 435;
// Worst-case from CREG and MREG
else if (CREG != 0) \PCOUT.arrival = 1835;
else if (MREG != 0) \PCOUT.arrival = 1819;
// Worst-case from AREG, ADREG, BREG, DREG
else if (AREG != 0) \PCOUT.arrival = 4083;
else if (DREG != 0) \PCOUT.arrival = 4056;
else if (BREG != 0) \PCOUT.arrival = 2960;
else if (ADREG != 0) \PCOUT.arrival = 2859;
end
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin
if (PREG != 0) \PCOUT.arrival = 435;
// Worst-case from AREG, BREG, CREG
else if (CREG != 0) \PCOUT.arrival = 1835;
else if (AREG != 0) \PCOUT.arrival = 1780;
else if (BREG != 0) \PCOUT.arrival = 1765;
end
end
endfunction
function integer \A.P.comb ;
begin
if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \A.P.comb = 2823;
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \A.P.comb = 3806;
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \A.P.comb = 1523;
end
endfunction
function integer \A.PCOUT.comb ;
begin
if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \A.PCOUT.comb = 2970;
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \A.PCOUT.comb = 3954;
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \A.PCOUT.comb = 1671;
end
endfunction
function integer \B.P.comb ;
begin
if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \B.P.comb = 2690;
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \B.P.comb = 2690;
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \B.P.comb = 1509;
end
endfunction
function integer \B.PCOUT.comb ;
begin
if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \B.PCOUT.comb = 2838;
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \B.PCOUT.comb = 2838;
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \B.PCOUT.comb = 1658;
end
endfunction
function integer \C.P.comb ;
begin
if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \C.P.comb = 1325;
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \C.P.comb = 1325;
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \C.P.comb = 1325;
end
endfunction
function integer \C.PCOUT.comb ;
begin
if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \C.PCOUT.comb = 1474;
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \C.PCOUT.comb = 1474;
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \C.PCOUT.comb = 1474;
end
endfunction
function integer \D.P.comb ;
begin
if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \D.P.comb = 3717;
end
endfunction
function integer \D.PCOUT.comb ;
begin
if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \D.PCOUT.comb = 3700;
end
endfunction
generate
if (PREG == 0 && MREG == 0 && AREG == 0 && ADREG == 0)
specify
(A *> P) = \A.P.comb ();
(A *> PCOUT) = \A.PCOUT.comb ();
endspecify
else
specify
$setup(A, posedge CLK &&& !IS_CLK_INVERTED, \A.required () );
$setup(A, negedge CLK &&& IS_CLK_INVERTED, \A.required () );
endspecify
if (PREG == 0 && MREG == 0 && BREG == 0)
specify
(B *> P) = \B.P.comb ();
(B *> PCOUT) = \B.PCOUT.comb ();
endspecify
else
specify
$setup(B, posedge CLK &&& !IS_CLK_INVERTED, \B.required () );
$setup(B, negedge CLK &&& IS_CLK_INVERTED, \B.required () );
endspecify
if (PREG == 0 && CREG == 0)
specify
(C *> P) = \C.P.comb ();
(C *> PCOUT) = \C.PCOUT.comb ();
endspecify
else
specify
$setup(C, posedge CLK &&& !IS_CLK_INVERTED, \C.required () );
$setup(C, negedge CLK &&& IS_CLK_INVERTED, \C.required () );
endspecify
if (PREG == 0 && MREG == 0 && ADREG == 0 && DREG == 0)
specify
(D *> P) = \D.P.comb ();
(D *> PCOUT) = \D.PCOUT.comb ();
endspecify
else
specify
$setup(D, posedge CLK &&& !IS_CLK_INVERTED, \D.required () );
$setup(D, negedge CLK &&& IS_CLK_INVERTED, \D.required () );
endspecify
if (PREG == 0)
specify
(PCIN *> P) = 1107;
(PCIN *> PCOUT) = 1255;
endspecify
else
specify
$setup(PCIN, posedge CLK &&& !IS_CLK_INVERTED, USE_PATTERN_DETECT != "NO_PATDET" ? 1315 : 1025);
$setup(PCIN, negedge CLK &&& IS_CLK_INVERTED, USE_PATTERN_DETECT != "NO_PATDET" ? 1315 : 1025);
endspecify
if (PREG || AREG || ADREG || BREG || CREG || DREG || MREG)
specify
if (!IS_CLK_INVERTED && CEP) (posedge CLK => (P : 48'bx)) = \P.arrival () ;
if ( IS_CLK_INVERTED && CEP) (negedge CLK => (P : 48'bx)) = \P.arrival () ;
if (!IS_CLK_INVERTED && CEP) (posedge CLK => (PCOUT : 48'bx)) = \PCOUT.arrival () ;
if ( IS_CLK_INVERTED && CEP) (negedge CLK => (PCOUT : 48'bx)) = \PCOUT.arrival () ;
endspecify
endgenerate
`endif
initial begin
`ifndef YOSYS
if (AUTORESET_PATDET != "NO_RESET") $fatal(1, "Unsupported AUTORESET_PATDET value");
if (SEL_MASK != "MASK") $fatal(1, "Unsupported SEL_MASK value");
if (SEL_PATTERN != "PATTERN") $fatal(1, "Unsupported SEL_PATTERN value");
if (USE_SIMD != "ONE48" && USE_SIMD != "TWO24" && USE_SIMD != "FOUR12") $fatal(1, "Unsupported USE_SIMD value");
if (IS_ALUMODE_INVERTED != 4'b0) $fatal(1, "Unsupported IS_ALUMODE_INVERTED value");
if (IS_CARRYIN_INVERTED != 1'b0) $fatal(1, "Unsupported IS_CARRYIN_INVERTED value");
if (IS_CLK_INVERTED != 1'b0) $fatal(1, "Unsupported IS_CLK_INVERTED value");
if (IS_INMODE_INVERTED != 5'b0) $fatal(1, "Unsupported IS_INMODE_INVERTED value");
if (IS_OPMODE_INVERTED != 7'b0) $fatal(1, "Unsupported IS_OPMODE_INVERTED value");
`endif
end
wire signed [29:0] A_muxed;
wire signed [17:0] B_muxed;
generate
if (A_INPUT == "CASCADE") assign A_muxed = ACIN;
else assign A_muxed = A;
if (B_INPUT == "CASCADE") assign B_muxed = BCIN;
else assign B_muxed = B;
endgenerate
reg signed [29:0] Ar1, Ar2;
reg signed [24:0] Dr;
reg signed [17:0] Br1, Br2;
reg signed [47:0] Cr;
reg [4:0] INMODEr;
reg [6:0] OPMODEr;
reg [3:0] ALUMODEr;
reg [2:0] CARRYINSELr;
generate
// Configurable A register
if (AREG == 2) begin
initial Ar1 = 30'b0;
initial Ar2 = 30'b0;
always @(posedge CLK)
if (RSTA) begin
Ar1 <= 30'b0;
Ar2 <= 30'b0;
end else begin
if (CEA1) Ar1 <= A_muxed;
if (CEA2) Ar2 <= Ar1;
end
end else if (AREG == 1) begin
//initial Ar1 = 30'b0;
initial Ar2 = 30'b0;
always @(posedge CLK)
if (RSTA) begin
Ar1 <= 30'b0;
Ar2 <= 30'b0;
end else begin
if (CEA1) Ar1 <= A_muxed;
if (CEA2) Ar2 <= A_muxed;
end
end else begin
always @* Ar1 <= A_muxed;
always @* Ar2 <= A_muxed;
end
// Configurable B register
if (BREG == 2) begin
initial Br1 = 25'b0;
initial Br2 = 25'b0;
always @(posedge CLK)
if (RSTB) begin
Br1 <= 18'b0;
Br2 <= 18'b0;
end else begin
if (CEB1) Br1 <= B_muxed;
if (CEB2) Br2 <= Br1;
end
end else if (BREG == 1) begin
//initial Br1 = 18'b0;
initial Br2 = 18'b0;
always @(posedge CLK)
if (RSTB) begin
Br1 <= 18'b0;
Br2 <= 18'b0;
end else begin
if (CEB1) Br1 <= B_muxed;
if (CEB2) Br2 <= B_muxed;
end
end else begin
always @* Br1 <= B_muxed;
always @* Br2 <= B_muxed;
end
// C and D registers
if (CREG == 1) initial Cr = 48'b0;
if (CREG == 1) begin always @(posedge CLK) if (RSTC) Cr <= 48'b0; else if (CEC) Cr <= C; end
else always @* Cr <= C;
if (CREG == 1) initial Dr = 25'b0;
if (DREG == 1) begin always @(posedge CLK) if (RSTD) Dr <= 25'b0; else if (CED) Dr <= D; end
else always @* Dr <= D;
// Control registers
if (INMODEREG == 1) initial INMODEr = 5'b0;
if (INMODEREG == 1) begin always @(posedge CLK) if (RSTINMODE) INMODEr <= 5'b0; else if (CEINMODE) INMODEr <= INMODE; end
else always @* INMODEr <= INMODE;
if (OPMODEREG == 1) initial OPMODEr = 7'b0;
if (OPMODEREG == 1) begin always @(posedge CLK) if (RSTCTRL) OPMODEr <= 7'b0; else if (CECTRL) OPMODEr <= OPMODE; end
else always @* OPMODEr <= OPMODE;
if (ALUMODEREG == 1) initial ALUMODEr = 4'b0;
if (ALUMODEREG == 1) begin always @(posedge CLK) if (RSTALUMODE) ALUMODEr <= 4'b0; else if (CEALUMODE) ALUMODEr <= ALUMODE; end
else always @* ALUMODEr <= ALUMODE;
if (CARRYINSELREG == 1) initial CARRYINSELr = 3'b0;
if (CARRYINSELREG == 1) begin always @(posedge CLK) if (RSTCTRL) CARRYINSELr <= 3'b0; else if (CECTRL) CARRYINSELr <= CARRYINSEL; end
else always @* CARRYINSELr <= CARRYINSEL;
endgenerate
// A and B cascade
generate
if (ACASCREG == 1 && AREG == 2) assign ACOUT = Ar1;
else assign ACOUT = Ar2;
if (BCASCREG == 1 && BREG == 2) assign BCOUT = Br1;
else assign BCOUT = Br2;
endgenerate
// A/D input selection and pre-adder
wire signed [24:0] Ar12_muxed = INMODEr[0] ? Ar1 : Ar2;
wire signed [24:0] Ar12_gated = INMODEr[1] ? 25'b0 : Ar12_muxed;
wire signed [24:0] Dr_gated = INMODEr[2] ? Dr : 25'b0;
wire signed [24:0] AD_result = INMODEr[3] ? (Dr_gated - Ar12_gated) : (Dr_gated + Ar12_gated);
reg signed [24:0] ADr;
generate
if (ADREG == 1) initial ADr = 25'b0;
if (ADREG == 1) begin always @(posedge CLK) if (RSTD) ADr <= 25'b0; else if (CEAD) ADr <= AD_result; end
else always @* ADr <= AD_result;
endgenerate
// 25x18 multiplier
wire signed [24:0] A_MULT;
wire signed [17:0] B_MULT = INMODEr[4] ? Br1 : Br2;
generate
if (USE_DPORT == "TRUE") assign A_MULT = ADr;
else assign A_MULT = Ar12_gated;
endgenerate
wire signed [42:0] M = A_MULT * B_MULT;
wire signed [42:0] Mx = (CARRYINSEL == 3'b010) ? 43'bx : M;
reg signed [42:0] Mr = 43'b0;
// Multiplier result register
generate
if (MREG == 1) begin always @(posedge CLK) if (RSTM) Mr <= 43'b0; else if (CEM) Mr <= Mx; end
else always @* Mr <= Mx;
endgenerate
wire signed [42:0] Mrx = (CARRYINSELr == 3'b010) ? 43'bx : Mr;
// X, Y and Z ALU inputs
reg signed [47:0] X, Y, Z;
always @* begin
// X multiplexer
case (OPMODEr[1:0])
2'b00: X = 48'b0;
2'b01: begin X = $signed(Mrx);
`ifndef YOSYS
if (OPMODEr[3:2] != 2'b01) $fatal(1, "OPMODEr[3:2] must be 2'b01 when OPMODEr[1:0] is 2'b01");
`endif
end
2'b10:
if (PREG == 1)
X = P;
else begin
X = 48'bx;
`ifndef YOSYS
$fatal(1, "PREG must be 1 when OPMODEr[1:0] is 2'b10");
`endif
end
2'b11: X = $signed({Ar2, Br2});
default: X = 48'bx;
endcase
// Y multiplexer
case (OPMODEr[3:2])
2'b00: Y = 48'b0;
2'b01: begin Y = 48'b0; // FIXME: more accurate partial product modelling?
`ifndef YOSYS
if (OPMODEr[1:0] != 2'b01) $fatal(1, "OPMODEr[1:0] must be 2'b01 when OPMODEr[3:2] is 2'b01");
`endif
end
2'b10: Y = {48{1'b1}};
2'b11: Y = Cr;
default: Y = 48'bx;
endcase
// Z multiplexer
case (OPMODEr[6:4])
3'b000: Z = 48'b0;
3'b001: Z = PCIN;
3'b010:
if (PREG == 1)
Z = P;
else begin
Z = 48'bx;
`ifndef YOSYS
$fatal(1, "PREG must be 1 when OPMODEr[6:4] is 3'b010");
`endif
end
3'b011: Z = Cr;
3'b100:
if (PREG == 1 && OPMODEr[3:0] === 4'b1000)
Z = P;
else begin
Z = 48'bx;
`ifndef YOSYS
if (PREG != 1) $fatal(1, "PREG must be 1 when OPMODEr[6:4] is 3'b100");
if (OPMODEr[3:0] != 4'b1000) $fatal(1, "OPMODEr[3:0] must be 4'b1000 when OPMODEr[6:4] i0s 3'b100");
`endif
end
3'b101: Z = $signed(PCIN[47:17]);
3'b110:
if (PREG == 1)
Z = $signed(P[47:17]);
else begin
Z = 48'bx;
`ifndef YOSYS
$fatal(1, "PREG must be 1 when OPMODEr[6:4] is 3'b110");
`endif
end
default: Z = 48'bx;
endcase
end
// Carry in
wire A24_xnor_B17d = A_MULT[24] ~^ B_MULT[17];
reg CARRYINr, A24_xnor_B17;
generate
if (CARRYINREG == 1) initial CARRYINr = 1'b0;
if (CARRYINREG == 1) begin always @(posedge CLK) if (RSTALLCARRYIN) CARRYINr <= 1'b0; else if (CECARRYIN) CARRYINr <= CARRYIN; end
else always @* CARRYINr = CARRYIN;
if (MREG == 1) initial A24_xnor_B17 = 1'b0;
if (MREG == 1) begin always @(posedge CLK) if (RSTALLCARRYIN) A24_xnor_B17 <= 1'b0; else if (CEM) A24_xnor_B17 <= A24_xnor_B17d; end
else always @* A24_xnor_B17 = A24_xnor_B17d;
endgenerate
reg cin_muxed;
always @(*) begin
case (CARRYINSELr)
3'b000: cin_muxed = CARRYINr;
3'b001: cin_muxed = ~PCIN[47];
3'b010: cin_muxed = CARRYCASCIN;
3'b011: cin_muxed = PCIN[47];
3'b100:
if (PREG == 1)
cin_muxed = CARRYCASCOUT;
else begin
cin_muxed = 1'bx;
`ifndef YOSYS
$fatal(1, "PREG must be 1 when CARRYINSEL is 3'b100");
`endif
end
3'b101:
if (PREG == 1)
cin_muxed = ~P[47];
else begin
cin_muxed = 1'bx;
`ifndef YOSYS
$fatal(1, "PREG must be 1 when CARRYINSEL is 3'b101");
`endif
end
3'b110: cin_muxed = A24_xnor_B17;
3'b111:
if (PREG == 1)
cin_muxed = P[47];
else begin
cin_muxed = 1'bx;
`ifndef YOSYS
$fatal(1, "PREG must be 1 when CARRYINSEL is 3'b111");
`endif
end
default: cin_muxed = 1'bx;
endcase
end
wire alu_cin = (ALUMODEr[3] || ALUMODEr[2]) ? 1'b0 : cin_muxed;
// ALU core
wire [47:0] Z_muxinv = ALUMODEr[0] ? ~Z : Z;
wire [47:0] xor_xyz = X ^ Y ^ Z_muxinv;
wire [47:0] maj_xyz = (X & Y) | (X & Z_muxinv) | (Y & Z_muxinv);
wire [47:0] xor_xyz_muxed = ALUMODEr[3] ? maj_xyz : xor_xyz;
wire [47:0] maj_xyz_gated = ALUMODEr[2] ? 48'b0 : maj_xyz;
wire [48:0] maj_xyz_simd_gated;
wire [3:0] int_carry_in, int_carry_out, ext_carry_out;
wire [47:0] alu_sum;
assign int_carry_in[0] = 1'b0;
wire [3:0] carryout_reset;
generate
if (USE_SIMD == "FOUR12") begin
assign maj_xyz_simd_gated = {
maj_xyz_gated[47:36],
1'b0, maj_xyz_gated[34:24],
1'b0, maj_xyz_gated[22:12],
1'b0, maj_xyz_gated[10:0],
alu_cin
};
assign int_carry_in[3:1] = 3'b000;
assign ext_carry_out = {
int_carry_out[3],
maj_xyz_gated[35] ^ int_carry_out[2],
maj_xyz_gated[23] ^ int_carry_out[1],
maj_xyz_gated[11] ^ int_carry_out[0]
};
assign carryout_reset = 4'b0000;
end else if (USE_SIMD == "TWO24") begin
assign maj_xyz_simd_gated = {
maj_xyz_gated[47:24],
1'b0, maj_xyz_gated[22:0],
alu_cin
};
assign int_carry_in[3:1] = {int_carry_out[2], 1'b0, int_carry_out[0]};
assign ext_carry_out = {
int_carry_out[3],
1'bx,
maj_xyz_gated[23] ^ int_carry_out[1],
1'bx
};
assign carryout_reset = 4'b0x0x;
end else begin
assign maj_xyz_simd_gated = {maj_xyz_gated, alu_cin};
assign int_carry_in[3:1] = int_carry_out[2:0];
assign ext_carry_out = {
int_carry_out[3],
3'bxxx
};
assign carryout_reset = 4'b0xxx;
end
genvar i;
for (i = 0; i < 4; i = i + 1)
assign {int_carry_out[i], alu_sum[i*12 +: 12]} = {1'b0, maj_xyz_simd_gated[i*12 +: ((i == 3) ? 13 : 12)]}
+ xor_xyz_muxed[i*12 +: 12] + int_carry_in[i];
endgenerate
wire signed [47:0] Pd = ALUMODEr[1] ? ~alu_sum : alu_sum;
wire [3:0] CARRYOUTd = (OPMODEr[3:0] == 4'b0101 || ALUMODEr[3:2] != 2'b00) ? 4'bxxxx :
((ALUMODEr[0] & ALUMODEr[1]) ? ~ext_carry_out : ext_carry_out);
wire CARRYCASCOUTd = ext_carry_out[3];
wire MULTSIGNOUTd = Mrx[42];
generate
if (PREG == 1) begin
initial P = 48'b0;
initial CARRYOUT = carryout_reset;
initial CARRYCASCOUT = 1'b0;
initial MULTSIGNOUT = 1'b0;
always @(posedge CLK)
if (RSTP) begin
P <= 48'b0;
CARRYOUT <= carryout_reset;
CARRYCASCOUT <= 1'b0;
MULTSIGNOUT <= 1'b0;
end else if (CEP) begin
P <= Pd;
CARRYOUT <= CARRYOUTd;
CARRYCASCOUT <= CARRYCASCOUTd;
MULTSIGNOUT <= MULTSIGNOUTd;
end
end else begin
always @* begin
P = Pd;
CARRYOUT = CARRYOUTd;
CARRYCASCOUT = CARRYCASCOUTd;
MULTSIGNOUT = MULTSIGNOUTd;
end
end
endgenerate
assign PCOUT = P;
generate
wire PATTERNDETECTd, PATTERNBDETECTd;
if (USE_PATTERN_DETECT == "PATDET") begin
// TODO: Support SEL_PATTERN != "PATTERN" and SEL_MASK != "MASK
assign PATTERNDETECTd = &(~(Pd ^ PATTERN) | MASK);
assign PATTERNBDETECTd = &((Pd ^ PATTERN) | MASK);
end else begin
assign PATTERNDETECTd = 1'b1;
assign PATTERNBDETECTd = 1'b1;
end
if (PREG == 1) begin
reg PATTERNDETECTPAST, PATTERNBDETECTPAST;
initial PATTERNDETECT = 1'b0;
initial PATTERNBDETECT = 1'b0;
initial PATTERNDETECTPAST = 1'b0;
initial PATTERNBDETECTPAST = 1'b0;
always @(posedge CLK)
if (RSTP) begin
PATTERNDETECT <= 1'b0;
PATTERNBDETECT <= 1'b0;
PATTERNDETECTPAST <= 1'b0;
PATTERNBDETECTPAST <= 1'b0;
end else if (CEP) begin
PATTERNDETECT <= PATTERNDETECTd;
PATTERNBDETECT <= PATTERNBDETECTd;
PATTERNDETECTPAST <= PATTERNDETECT;
PATTERNBDETECTPAST <= PATTERNBDETECT;
end
assign OVERFLOW = &{PATTERNDETECTPAST, ~PATTERNBDETECT, ~PATTERNDETECT};
assign UNDERFLOW = &{PATTERNBDETECTPAST, ~PATTERNBDETECT, ~PATTERNDETECT};
end else begin
always @* begin
PATTERNDETECT = PATTERNDETECTd;
PATTERNBDETECT = PATTERNBDETECTd;
end
assign OVERFLOW = 1'bx, UNDERFLOW = 1'bx;
end
endgenerate
endmodule
// TODO: DSP48E2 (Ultrascale).
// Block RAM
module RAMB18E1 (
(* clkbuf_sink *)
(* invertible_pin = "IS_CLKARDCLK_INVERTED" *)
input CLKARDCLK,
(* clkbuf_sink *)
(* invertible_pin = "IS_CLKBWRCLK_INVERTED" *)
input CLKBWRCLK,
(* invertible_pin = "IS_ENARDEN_INVERTED" *)
input ENARDEN,
(* invertible_pin = "IS_ENBWREN_INVERTED" *)
input ENBWREN,
input REGCEAREGCE,
input REGCEB,
(* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *)
input RSTRAMARSTRAM,
(* invertible_pin = "IS_RSTRAMB_INVERTED" *)
input RSTRAMB,
(* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *)
input RSTREGARSTREG,
(* invertible_pin = "IS_RSTREGB_INVERTED" *)
input RSTREGB,
input [13:0] ADDRARDADDR,
input [13:0] ADDRBWRADDR,
input [15:0] DIADI,
input [15:0] DIBDI,
input [1:0] DIPADIP,
input [1:0] DIPBDIP,
input [1:0] WEA,
input [3:0] WEBWE,
output [15:0] DOADO,
output [15:0] DOBDO,
output [1:0] DOPADOP,
output [1:0] DOPBDOP
);
parameter integer DOA_REG = 0;
parameter integer DOB_REG = 0;
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_A = 18'h0;
parameter INIT_B = 18'h0;
parameter INIT_FILE = "NONE";
parameter RAM_MODE = "TDP";
parameter RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE";
parameter integer READ_WIDTH_A = 0;
parameter integer READ_WIDTH_B = 0;
parameter RSTREG_PRIORITY_A = "RSTREG";
parameter RSTREG_PRIORITY_B = "RSTREG";
parameter SIM_COLLISION_CHECK = "ALL";
parameter SIM_DEVICE = "VIRTEX6";
parameter SRVAL_A = 18'h0;
parameter SRVAL_B = 18'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter integer WRITE_WIDTH_A = 0;
parameter integer WRITE_WIDTH_B = 0;
parameter IS_CLKARDCLK_INVERTED = 1'b0;
parameter IS_CLKBWRCLK_INVERTED = 1'b0;
parameter IS_ENARDEN_INVERTED = 1'b0;
parameter IS_ENBWREN_INVERTED = 1'b0;
parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
parameter IS_RSTRAMB_INVERTED = 1'b0;
parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
parameter IS_RSTREGB_INVERTED = 1'b0;
specify
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L13
$setup(ADDRARDADDR, posedge CLKARDCLK, 566);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L17
$setup(ADDRBWRADDR, posedge CLKBWRCLK, 566);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L19
$setup(WEA, posedge CLKARDCLK, 532);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L21
$setup(WEBWE, posedge CLKBWRCLK, 532);
// https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L29
$setup(REGCEAREGCE, posedge CLKARDCLK, 360);
// https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L31
$setup(RSTREGARSTREG, posedge CLKARDCLK, 342);
// https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L49
$setup(REGCEB, posedge CLKBWRCLK, 360);
// https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L59
$setup(RSTREGB, posedge CLKBWRCLK, 342);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L123
$setup(DIADI, posedge CLKARDCLK, 737);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L133
$setup(DIBDI, posedge CLKBWRCLK, 737);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L125
$setup(DIPADIP, posedge CLKARDCLK, 737);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L135
$setup(DIPBDIP, posedge CLKBWRCLK, 737);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L143
if (&DOA_REG) (posedge CLKARDCLK => (DOADO : 16'bx)) = 2454;
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L144
if (&DOA_REG) (posedge CLKARDCLK => (DOPADOP : 2'bx)) = 2454;
// https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L153
if (|DOA_REG) (posedge CLKARDCLK => (DOADO : 16'bx)) = 882;
// https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L154
if (|DOA_REG) (posedge CLKARDCLK => (DOPADOP : 2'bx)) = 882;
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L163
if (&DOB_REG) (posedge CLKBWRCLK => (DOBDO : 16'bx)) = 2454;
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L164
if (&DOB_REG) (posedge CLKBWRCLK => (DOPBDOP : 2'bx)) = 2454;
// https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L173
if (|DOB_REG) (posedge CLKBWRCLK => (DOBDO : 16'bx)) = 882;
// https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L174
if (|DOB_REG) (posedge CLKBWRCLK => (DOPBDOP : 2'bx)) = 882;
endspecify
endmodule
module RAMB36E1 (
output CASCADEOUTA,
output CASCADEOUTB,
output [31:0] DOADO,
output [31:0] DOBDO,
output [3:0] DOPADOP,
output [3:0] DOPBDOP,
output [7:0] ECCPARITY,
output [8:0] RDADDRECC,
output SBITERR,
output DBITERR,
(* invertible_pin = "IS_ENARDEN_INVERTED" *)
input ENARDEN,
(* clkbuf_sink *)
(* invertible_pin = "IS_CLKARDCLK_INVERTED" *)
input CLKARDCLK,
(* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *)
input RSTRAMARSTRAM,
(* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *)
input RSTREGARSTREG,
input CASCADEINA,
input REGCEAREGCE,
(* invertible_pin = "IS_ENBWREN_INVERTED" *)
input ENBWREN,
(* clkbuf_sink *)
(* invertible_pin = "IS_CLKBWRCLK_INVERTED" *)
input CLKBWRCLK,
(* invertible_pin = "IS_RSTRAMB_INVERTED" *)
input RSTRAMB,
(* invertible_pin = "IS_RSTREGB_INVERTED" *)
input RSTREGB,
input CASCADEINB,
input REGCEB,
input INJECTDBITERR,
input INJECTSBITERR,
input [15:0] ADDRARDADDR,
input [15:0] ADDRBWRADDR,
input [31:0] DIADI,
input [31:0] DIBDI,
input [3:0] DIPADIP,
input [3:0] DIPBDIP,
input [3:0] WEA,
input [7:0] WEBWE
);
parameter integer DOA_REG = 0;
parameter integer DOB_REG = 0;
parameter EN_ECC_READ = "FALSE";
parameter EN_ECC_WRITE = "FALSE";
parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_A = 36'h0;
parameter INIT_B = 36'h0;
parameter INIT_FILE = "NONE";
parameter RAM_EXTENSION_A = "NONE";
parameter RAM_EXTENSION_B = "NONE";
parameter RAM_MODE = "TDP";
parameter RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE";
parameter integer READ_WIDTH_A = 0;
parameter integer READ_WIDTH_B = 0;
parameter RSTREG_PRIORITY_A = "RSTREG";
parameter RSTREG_PRIORITY_B = "RSTREG";
parameter SIM_COLLISION_CHECK = "ALL";
parameter SIM_DEVICE = "VIRTEX6";
parameter SRVAL_A = 36'h0;
parameter SRVAL_B = 36'h0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
parameter integer WRITE_WIDTH_A = 0;
parameter integer WRITE_WIDTH_B = 0;
parameter IS_CLKARDCLK_INVERTED = 1'b0;
parameter IS_CLKBWRCLK_INVERTED = 1'b0;
parameter IS_ENARDEN_INVERTED = 1'b0;
parameter IS_ENBWREN_INVERTED = 1'b0;
parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
parameter IS_RSTRAMB_INVERTED = 1'b0;
parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
parameter IS_RSTREGB_INVERTED = 1'b0;
specify
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L13
$setup(ADDRARDADDR, posedge CLKARDCLK, 566);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L17
$setup(ADDRBWRADDR, posedge CLKBWRCLK, 566);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L19
$setup(WEA, posedge CLKARDCLK, 532);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L21
$setup(WEBWE, posedge CLKBWRCLK, 532);
// https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L29
$setup(REGCEAREGCE, posedge CLKARDCLK, 360);
// https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L31
$setup(RSTREGARSTREG, posedge CLKARDCLK, 342);
// https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L49
$setup(REGCEB, posedge CLKBWRCLK, 360);
// https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L59
$setup(RSTREGB, posedge CLKBWRCLK, 342);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L123
$setup(DIADI, posedge CLKARDCLK, 737);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L133
$setup(DIBDI, posedge CLKBWRCLK, 737);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L125
$setup(DIPADIP, posedge CLKARDCLK, 737);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L135
$setup(DIPBDIP, posedge CLKBWRCLK, 737);
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L143
if (&DOA_REG) (posedge CLKARDCLK => (DOADO : 32'bx)) = 2454;
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L144
if (&DOA_REG) (posedge CLKARDCLK => (DOPADOP : 4'bx)) = 2454;
// https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L153
if (|DOA_REG) (posedge CLKARDCLK => (DOADO : 32'bx)) = 882;
// https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L154
if (|DOA_REG) (posedge CLKARDCLK => (DOPADOP : 4'bx)) = 882;
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L163
if (&DOB_REG) (posedge CLKBWRCLK => (DOBDO : 32'bx)) = 2454;
// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L164
if (&DOB_REG) (posedge CLKBWRCLK => (DOPBDOP : 4'bx)) = 2454;
// https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L173
if (|DOB_REG) (posedge CLKBWRCLK => (DOBDO : 32'bx)) = 882;
// https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L174
if (|DOB_REG) (posedge CLKBWRCLK => (DOPBDOP : 4'bx)) = 882;
endspecify
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O311A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__O311A_BEHAVIORAL_PP_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o311a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X , or0_out, B1, C1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O311A_BEHAVIORAL_PP_V |
module nios_tester (
audio_in_data,
audio_in_valid,
audio_in_ready,
audio_out_data,
audio_out_valid,
audio_out_ready,
dummy_export,
io_ack,
io_rdata,
io_read,
io_wdata,
io_write,
io_address,
io_irq,
io_u2p_ack,
io_u2p_rdata,
io_u2p_read,
io_u2p_wdata,
io_u2p_write,
io_u2p_address,
io_u2p_irq,
jtag0_jtag_tck,
jtag0_jtag_tms,
jtag0_jtag_tdi,
jtag0_jtag_tdo,
jtag1_jtag_tck,
jtag1_jtag_tms,
jtag1_jtag_tdi,
jtag1_jtag_tdo,
jtag_in_data,
jtag_in_valid,
jtag_in_ready,
mem_mem_req_address,
mem_mem_req_byte_en,
mem_mem_req_read_writen,
mem_mem_req_request,
mem_mem_req_tag,
mem_mem_req_wdata,
mem_mem_resp_dack_tag,
mem_mem_resp_data,
mem_mem_resp_rack_tag,
pio_in_port,
pio_out_port,
spi_MISO,
spi_MOSI,
spi_SCLK,
spi_SS_n,
sys_clock_clk,
sys_reset_reset_n);
input [31:0] audio_in_data;
input audio_in_valid;
output audio_in_ready;
output [31:0] audio_out_data;
output audio_out_valid;
input audio_out_ready;
input dummy_export;
input io_ack;
input [7:0] io_rdata;
output io_read;
output [7:0] io_wdata;
output io_write;
output [19:0] io_address;
input io_irq;
input io_u2p_ack;
input [7:0] io_u2p_rdata;
output io_u2p_read;
output [7:0] io_u2p_wdata;
output io_u2p_write;
output [19:0] io_u2p_address;
input io_u2p_irq;
output jtag0_jtag_tck;
output jtag0_jtag_tms;
output jtag0_jtag_tdi;
input jtag0_jtag_tdo;
output jtag1_jtag_tck;
output jtag1_jtag_tms;
output jtag1_jtag_tdi;
input jtag1_jtag_tdo;
input [7:0] jtag_in_data;
input jtag_in_valid;
output jtag_in_ready;
output [25:0] mem_mem_req_address;
output [3:0] mem_mem_req_byte_en;
output mem_mem_req_read_writen;
output mem_mem_req_request;
output [7:0] mem_mem_req_tag;
output [31:0] mem_mem_req_wdata;
input [7:0] mem_mem_resp_dack_tag;
input [31:0] mem_mem_resp_data;
input [7:0] mem_mem_resp_rack_tag;
input [31:0] pio_in_port;
output [31:0] pio_out_port;
input spi_MISO;
output spi_MOSI;
output spi_SCLK;
output spi_SS_n;
input sys_clock_clk;
input sys_reset_reset_n;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Silicon Spectrum Corporation - All Rights Reserved
// Copyright (C) 2009 - All rights reserved
//
// This File is copyright Silicon Spectrum Corporation and is licensed for
// use by Conexant Systems, Inc., hereafter the "licensee", as defined by the NDA and the
// license agreement.
//
// This code may not be used as a basis for new development without a written
// agreement between Silicon Spectrum and the licensee.
//
// New development includes, but is not limited to new designs based on this
// code, using this code to aid verification or using this code to test code
// developed independently by the licensee.
//
// This copyright notice must be maintained as written, modifying or removing
// this copyright header will be considered a breach of the license agreement.
//
// The licensee may modify the code for the licensed project.
// Silicon Spectrum does not give up the copyright to the original
// file or encumber in any way.
//
// Use of this file is restricted by the license agreement between the
// licensee and Silicon Spectrum, Inc.
//
// Title : Drawing Engine Top Level
// File : de_top.v
// Author : Jim MacLeod
// Created : 30-Dec-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module Corresponds to the top level of Silverhammer. It will
// Contain only 2D functionality.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module de_top
#(parameter BYTES = 16)
(
// Inputs
input de_clk, // drawing engine clock input. */
input sys_locked, // drawing engine clock input. */
// Host inputs
input hb_clk, // host bus clock input
input hb_rstn, // reset input
input [8:2] dlp_adr, // host bus address through DLP
input [13:2] hb_adr_bp1, // " " bypass DLP for DED
input [8:2] hb_adr_bp2, // " " bypass DLP for DER readback
input hb_wstrb, // host bus write strobe for DED
input [3:0] hb_ben, // host bus byte enables
input [31:0] hb_din, // host bus data, not swizzled
input hb_csn_de, // chip select for de registers
input hb_xyw_csn, // chip select for XY window.
// Input from MC
input mclock, // Memory controller clock.
input mc_popen, // Memory controller pop enable.
input mc_push, // push data into the fifo.
mc_eop, // end of page indicator.
mc_eop4, // end of page indicator.(high last 4 pages)
input [53:0] dl_rdback, // DLP readback data.
input mw_de_fip, // Memory window flush in progress.
input hb_write, // Host write enable.
input de_pc_pop, // Pop from the pixcache
input mc_busy, // Memory Controller busy.
input busy_dlp, // Busy Feed Back from the DLP
// Output
output [31:0] hb_dout, // host bus read back data.
output [31:0] dr_hbdout, // Drawing engine registers to HB
output busy_hb, // drawing pipeline busy.
output interrupt, // Host interrupt.
// ded_ca_top ram interface
`ifdef BYTE16 output [3:0] ca_enable,
`elsif BYTE8 output [1:0] ca_enable,
`else output ca_enable, `endif
output [4:0] hb_ram_addr,
output [4:0] ca_ram_addr0,
output [4:0] ca_ram_addr1,
input [(BYTES*8)-1:0] hb_dout_ram,
input [(BYTES<<3)-1:0] ca_dout0,
input [(BYTES<<3)-1:0] ca_dout1,
// Output MC
output [BYTES-1:0] dd_pixel_msk, // pixel dr_mask bits
output [(BYTES<<3)-1:0] dd_fb_out, // data output to the frame buffer
output [(BYTES<<2)-1:0] dd_fb_a, // data output to the frame buffer
output de_pc_empty, // FIFO flag to MC
output [2:0] hdf_1, // host data format to HBI module.
output [1:0] ps_4, // Output the pixel size for the MC.
output [31:0] de_mc_address, // Line/ Blt linear address
output de_mc_read,
output de_mc_rmw,
output [3:0] de_mc_wcnt,
output line_actv_4,
output [3:0] bsrcr_4, // Source blending function.
output [2:0] bdstr_4, // Destination blending function.
output blend_en_4, // Blending enable.
output [1:0] blend_reg_en_4,// Blending enable.
output [7:0] bsrc_alpha_4, // Source alpha data.
output [7:0] bdst_alpha_4, // Destination alpha data.
output [3:0] rop_4, // Raster operation.
output [31:0] kcol_4, // Key Color.
output [2:0] key_ctrl_4, // Key control.
output dr_org_md_2,
output [6:0] mem_offset,
output [3:0] sorg_upper,
output ca_busy,
output de_ddint_tog, // drawing done pulse.
output de_clint_tog, // clipping interrupt pulse.
output dx_clp, // last command was clipped.
output dx_deb, // drawing engine busy.
output [4:0] z_ctrl_4,
output [31:0] z_address_4,
output [(BYTES*8)-1:0] z_out,
//
// Outputs to PCI bus
output pipe_pending, // pipeline has data in it
// TC Signals To/from the Memory controller.
input mc_tc_push,
input [(BYTES<<3)-1:0] mc_tc_data,
input mc_tc_ack,
input mc_pal_ack,
input mc_pal_push,
// Outputs.
output mc_tc_req,
output [5:0] mc_tc_page,
output [31:0] mc_tc_address,
output mc_pal_req,
output mc_pal_half,
output [31:0] mc_pal_address
);
// Internal Signals
wire [20:0] tporg_2; // palette origin
wire cmd_done_3d; // Last pixel done for current command.
wire [1:0] ps_15; // DSIZE bits
wire [3:0] opc_1;
wire [3:0] opc_15;
wire [3:0] rop_1;
wire [1:0] dr_apat_2;
wire [1:0] stpl_2;
wire [2:0] dr_clp_2;
wire [31:0] dr_fore_2;
wire [31:0] dr_back_2;
wire [31:0] dr_lpat_1;
wire [15:0] dr_pctrl_1;
wire [31:0] dr_clptl_1;
wire [31:0] dr_clpbr_1;
wire [159:0] dr_xydat_1;
wire [15:0] dx_xalu;
wire [15:0] dx_srcx,
dx_srcy,
dx_dstx,
dx_dsty;
wire [15:0] dx_lpat_state;
wire [31:0] dx_clpx_bus_2; // clipping X values.
wire [3:0] fx_1;
wire [15:0] real_dstx;
wire [15:0] real_dsty;
wire [31:0] de_dorg_2;
wire [31:0] de_sorg_2;
wire [1:0] chng_stat_1;
wire [27:0] dr_sorg_2;
wire [27:0] dr_dorg_2;
wire [11:0] dr_sptch_2;
wire [11:0] dr_dptch_2;
wire load_actvn;
wire [2:0] frst8;
wire pc_mc_busy;
// wire [1:0] pss_2;
// wire [1:0] ps_2;
// wire [1:0] nc2_0;
/* this renaming stuff stays */
wire tc_xyw_sel_1;
wire force8_2;
wire [11:0] dr_buf_ctrl_2;
wire dr_sen_2;
wire [31:0] kcol_2;
wire [2:0] key_ctrl_2;
assign {
dr_sen_2, // [11]
// pss_2, // [10:9]
// ps_2, // [8:7]
// nc2_0, // [6:5]
dr_org_md_2, // [4]
force8_2, // [3]
key_ctrl_2 // [2:0]
} = {dr_buf_ctrl_2[11], dr_buf_ctrl_2[4:0]};
wire dr_sfd_2;
assign dr_sfd_2 = dr_sen_2;
wire solid_2; /* solid bit*/
wire [4:0] dr_style_2;
assign solid_2 = dr_style_2[0]; /* solid bit */
wire de_edi_2; /* edge inclusion mode bit */
assign de_edi_2 = dr_style_2[4]; /* edge inclusion mode bit */
wire [1:0] bc_lvl_2;
reg [4:0] flow;
reg [4:0] flow_d;
always @(posedge hb_clk) begin
flow <= flow_d;
flow_d <= {
pipe_pending,
ca_busy,
dx_clp,
(mc_busy | pc_mc_busy | ca_busy),
dx_deb
};
end
/******************************************************************************/
/* syncronize the drawing done signal. */
wire [4:0] xpat_ofs;
wire [4:0] ypat_ofs;
// New Inputs
wire [1:0] dither_op; /* Dither Control Bits */
wire [17:0] acntrl_2;
wire [15:0] alpha_2;
wire [23:0] de_key_2;
wire cmdcpyclr;
wire de_rstn;
wire solid_1;
wire dr_prst_1;
wire dr_nlst_2;
wire dr_apat_1;
wire der_stpl_1;
wire ca_rdy;
wire ps16s_2;
wire cmd_trig_comb;
wire de_trnsp_2;
wire pc_mc_rdy;
wire pcbusy;
wire ps8_2, ps16_2, ps32_2;
wire pc_dirty;
wire de_pad8_2;
wire mw_fip;
wire deb;
wire bound;
wire dx_pc_ld;
wire rmw;
wire dx_ld_wcnt;
wire line_actv_2;
wire dx_blt_actv_2;
wire dx_fg_bgn;
wire dx_rstn_wad;
wire dx_ld_rad, dx_ld_rad_e;
wire dx_sol_2, eol_2;
wire dx_ld_msk;
wire clip;
wire y_clip_2;
wire src_lte_dst;
wire dx_ld_initial;
wire pc_msk_last;
wire frst_pix;
wire last_pixel;
wire wb_clip_ind;
wire stpl_pk_4;
wire dx_mem_req;
wire line_actv_1;
wire blt_actv_1;
wire [3:0] de_pln_msk_2;
wire dx_mem_rd;
wire [3:0] rop_2;
wire pc_empty;
wire valid_3d;
wire fg_bgn_3d;
wire [15:0] x_out_3d;
wire [15:0] y_out_3d;
wire last_3d;
wire [31:0] pixel_3d;
wire [31:0] z_3d;
wire [4:0] z_ctrl;
wire [7:0] alpha_3d;
wire [31:0] hb_dout_2d;
wire sup_done;
wire abort_cmd;
wire go_sup;
wire dex_busy;
wire goline;
wire goblt;
wire pal_load;
wire tc_inv_cmd;
wire load_actv_3d;
wire line_actv_3d;
wire pc_last;
wire [27:0] zorg_2;
wire [11:0] zptch_2;
wire active_3d_2;
wire [31:0] clptl_2;
wire [31:0] clpbr_2;
wire load_15;
wire pc_busy_3d;
wire msk_last_3d;
wire l3_incpat;
// Drawing Engine Registers
der_top u_der_top
(
.de_clk (de_clk),
.de_rstn (de_rstn),
.hb_clk (hb_clk),
.hb_rstn (hb_rstn),
.hb_din (hb_din),
.dlp_adr (dlp_adr[8:2]),
.hb_adr_r (hb_adr_bp2[8:2]),
.hb_wstrb (hb_wstrb),
.hb_ben (hb_ben),
.hb_csn (hb_csn_de),
.lpat_state (dx_lpat_state),
.dl_rdback (dl_rdback),
.flow (flow),
.busy_dlp (busy_dlp),
.de_clint_tog (de_clint_tog),
.de_ddint_tog (de_ddint_tog),
.sup_done (sup_done),
.abort_cmd (abort_cmd),
.dex_busy (dex_busy),
.pc_last (pc_last),
.cmd_done_3d (cmd_done_3d),
.pal_busy (pal_busy),
.goline (goline),
.goblt (goblt),
.pal_load (pal_load),
.tc_inv_cmd (tc_inv_cmd),
.go_sup (go_sup),
.load_actv_3d (load_actv_3d),
.cmdcpyclr (cmdcpyclr),
.load_actvn (load_actvn),
.tc_xyw_sel (tc_xyw_sel_1),
.buf_ctrl_2 (dr_buf_ctrl_2),
.ps_1 (ps_15),
.sorg_2 (dr_sorg_2),
.dorg_2 (dr_dorg_2),
.de_sorg_2 (de_sorg_2),
.de_dorg_2 (de_dorg_2),
.sptch_2 (dr_sptch_2),
.dptch_2 (dr_dptch_2),
.opc_1 (opc_1),
.opc_15 (opc_15),
.rop_1 (rop_1),
.rop_2 (rop_2),
.style_2 (dr_style_2),
.solid_1 (solid_1),
.prst_1 (dr_prst_1),
.nlst_2 (dr_nlst_2),
.or_apat_1 (dr_apat_1),
.apat_2 (dr_apat_2),
.hdf_1 (hdf_1),
.clp_2 (dr_clp_2),
.fore_2 (dr_fore_2),
.back_2 (dr_back_2),
.mask_2 (de_pln_msk_2),
.lpat_1 (dr_lpat_1),
.pctrl_1 (dr_pctrl_1),
.clptl_1 (dr_clptl_1),
.clpbr_1 (dr_clpbr_1),
.de_key_2 (de_key_2),
.xydat_1 (dr_xydat_1),
.alpha_2 (alpha_2),
.acntrl_2 (acntrl_2),
.hb_dout (hb_dout_2d),
.busy_hb (busy_hb),
.stpl_1 (der_stpl_1),
.de_ca_rdy (ca_rdy),
.ps16s_2 (ps16s_2),
.cmd_trig_comb (cmd_trig_comb),
.bc_lvl_2 (bc_lvl_2),
.interrupt (interrupt),
.mem_offset (mem_offset),
.sorg_upper (sorg_upper),
.load_15 (load_15),
.busy_3d (busy_3d)
);
/***************************************************************************/
/* Drawing Execution Module */
/***************************************************************************/
dex_top u_dex_top
(
.de_clk (de_clk),
.mclock (mclock),
.rstn (de_rstn),
.de_sorg_2 (de_sorg_2),
.de_dorg_2 (de_dorg_2),
.opc_1 (opc_1),
.opc_15 (opc_15),
.rop_1 (rop_1),
.rop_2 (rop_2),
.solid_1 (solid_1),
.solid_2 (solid_2),
.trnsp_2 (de_trnsp_2),
.stpl_1 (der_stpl_1),
.stpl_2 (stpl_2),
.apat_1 (dr_apat_1),
.apat_2 (dr_apat_2),
.sfd_2 (dr_sfd_2),
.edi_2 (de_edi_2),
.prst (dr_prst_1),
.nlst_2 (dr_nlst_2),
.clp_2 (dr_clp_2),
.lpat_1 (dr_lpat_1),
.pctrl_1 (dr_pctrl_1),
.clptl_1 (dr_clptl_1),
.clpbr_1 (dr_clpbr_1),
.xydat_1 (dr_xydat_1),
.pc_mcrdy (pc_mc_rdy),
.pcbusy (pc_busy_3d),
.ps_1 (ps_15),
.ps8_2 (ps8_2),
.ps16_2 (ps16_2),
.ps32_2 (ps32_2),
.pc_dirty (pc_dirty),
.ca_rdy (ca_rdy),
.pad8_2 (de_pad8_2),
.force8 (force8_2),
.mw_fip (mw_fip),
.load_actvn (load_actvn),
.load_actv_3d (load_actv_3d),
.cmdcpyclr (cmdcpyclr),
.goline (goline),
.goblt (goblt),
.l3_incpat (l3_incpat),
.busy_3d (busy_3d),
.busy (deb),
.bound (bound),
.pc_ld (dx_pc_ld),
.mem_req (dx_mem_req),
.mem_rd (dx_mem_rd),
.mem_rmw (rmw),
.ld_wcnt (dx_ld_wcnt),
.fx (dx_xalu),
.srcx (dx_srcx),
.srcy (dx_srcy),
.dstx (dx_dstx),
.dsty (dx_dsty),
.line_actv_2 (line_actv_2),
.blt_actv_2 (dx_blt_actv_2),
.fg_bgn (dx_fg_bgn),
.lpat_state (dx_lpat_state),
.clpx_bus_2 (dx_clpx_bus_2),
.rstn_wad (dx_rstn_wad),
.ld_rad (dx_ld_rad),
.ld_rad_e (dx_ld_rad_e),
.sol_2 (dx_sol_2),
.eol_2 (eol_2),
.ld_msk (dx_ld_msk),
.fx_1 (fx_1),
.clip (clip),
.y_clip_2 (y_clip_2),
.src_lte_dst (src_lte_dst),
.xpat_ofs (xpat_ofs),
.ypat_ofs (ypat_ofs),
.real_dstx (real_dstx),
.real_dsty (real_dsty),
.xchng (),
.ychng (),
.ld_initial (dx_ld_initial),
.next_x (), // remove_me
.next_y (), // remove_me
.pc_msk_last (pc_msk_last),
.frst_pix (), // remove_me
.last_pixel (last_pixel),
.line_actv_1 (line_actv_1),
.blt_actv_1 (blt_actv_1),
.frst8 (frst8),
.dex_busy (dex_busy),
.clptl_2 (clptl_2),
.clpbr_2 (clpbr_2)
);
/*********************************************************************** ***/
/* Drawing Data Path Module */
/***************************************************************************/
ded_top #
(
.BYTES (BYTES)
) D_DED
(
.de_clk (de_clk),
.de_rstn (de_rstn),
.hb_clk (hb_clk),
.hb_rstn (hb_rstn),
.hb_adr (hb_adr_bp1[12:2]),
.hb_we (hb_wstrb),
.hb_xyw_csn (hb_xyw_csn),
.dx_mem_req (dx_mem_req),
.dx_mem_rd (dx_mem_rd),
.dx_line_actv_2 (line_actv_2),
.dx_blt_actv_2 (dx_blt_actv_2),
.dx_pc_ld (dx_pc_ld),
.dx_clpx_bus_2 (dx_clpx_bus_2),
.dx_rstn_wad (dx_rstn_wad),
.dx_ld_rad (dx_ld_rad),
.dx_ld_rad_e (dx_ld_rad_e),
.dx_sol_2 (dx_sol_2),
.dx_eol_2 (eol_2),
.dx_ld_msk (dx_ld_msk),
.dx_xalu (dx_xalu[9:0]),
.srcx (dx_srcx),
.srcy (dx_srcy),
.dsty (dx_dsty),
.dx_dstx (dx_dstx),
.dx_fg_bgn (dx_fg_bgn),
.sorg_2 (dr_sorg_2),
.dorg_2 (dr_dorg_2),
.z_org (zorg_2),
.sptch_2 (dr_sptch_2),
.dptch_2 (dr_dptch_2),
.z_ptch (zptch_2),
.ps_2 (dr_buf_ctrl_2[8:7]),
.bsrcr_2 (acntrl_2[3:0]),
.bdstr_2 (acntrl_2[6:4]),
.blend_en_2 (acntrl_2[10]),
.blend_reg_en_2 (acntrl_2[9:8]),
.bsrc_alpha_2 (alpha_2[7:0]),
.bdst_alpha_2 (alpha_2[15:8]),
.rop_2 (rop_2),
.kcol_2 (kcol_2),
.key_ctrl_2 (key_ctrl_2),
.frst8_2 (frst8),
.clip (clip),
.xpat_ofs (xpat_ofs),
.ypat_ofs (ypat_ofs),
.real_dstx (real_dstx),
.real_dsty (real_dsty),
.ld_initial (dx_ld_initial),
.pc_msk_last (pc_msk_last),
.last_pixel (last_pixel),
.mclock (mclock),
.mc_popen (mc_popen),
.mc_push (mc_push),
.mc_eop (mc_eop),
.mc_eop4 (mc_eop4),
.de_pc_pop (de_pc_pop),
.ld_wcnt (dx_ld_wcnt),
.fx_1 (fx_1),
.rmw (rmw),
.de_pln_msk_2 (de_pln_msk_2),
.dr_solid_2 (solid_2),
.dr_trnsp_2 (de_trnsp_2),
.stpl_2 (stpl_2),
.dr_apat_2 (dr_apat_2),
.dr_clp_2 (dr_clp_2[1:0]),
.fore_2 (dr_fore_2),
.back_2 (dr_back_2),
.dr_sen_2 (dr_sen_2),
.y_clip_2 (y_clip_2),
.ps8_2 (ps8_2),
.ps16_2 (ps16_2),
.ps32_2 (ps32_2),
.bc_lvl_2 (bc_lvl_2),
.hb_write (hb_write),
.mc_pixel_msk (dd_pixel_msk),
.mc_fb_out (dd_fb_out),
.mc_fb_a (dd_fb_a),
.pc_mc_busy (pc_mc_busy),
.de_pc_empty (de_pc_empty),
.pc_empty (pc_empty),
.de_mc_address (de_mc_address),
.de_mc_read (de_mc_read),
.de_mc_rmw (de_mc_rmw),
.de_mc_wcnt (de_mc_wcnt),
.hb_dout (hb_dout),
.pc_dirty (pc_dirty),
.clip_ind (wb_clip_ind),
.stpl_pk_4 (stpl_pk_4),
.pc_mc_rdy (pc_mc_rdy),
.pipe_pending (pipe_pending),
.line_actv_4 (line_actv_4),
.ps_4 (ps_4),
.bsrcr_4 (bsrcr_4),
.bdstr_4 (bdstr_4),
.blend_en_4 (blend_en_4),
.blend_reg_en_4 (blend_reg_en_4),
.bsrc_alpha_4 (bsrc_alpha_4),
.bdst_alpha_4 (bdst_alpha_4),
.rop_4 (rop_4),
.kcol_4 (kcol_4),
.key_ctrl_4 (key_ctrl_4),
.ca_enable (ca_enable),
.hb_ram_addr (hb_ram_addr),
.ca_ram_addr0 (ca_ram_addr0),
.ca_ram_addr1 (ca_ram_addr1),
.hb_dout_ram (hb_dout_ram),
.ca_dout0 (ca_dout0),
.ca_dout1 (ca_dout1),
// 3D Interface.
.pc_busy_3d (pc_busy_3d),
.valid_3d (valid_3d),
.fg_bgn_3d (fg_bgn_3d),
.msk_last_3d (msk_last_3d),
.x_out_3d (x_out_3d),
.y_out_3d (y_out_3d),
.last_3d (last_3d),
.pixel_3d (pixel_3d),
.z_3d (z_3d),
.z_ctrl (z_ctrl),
.active_3d_2 (active_3d_2),
.alpha_3d (alpha_3d),
.pc_last (pc_last),
.z_ctrl_4 (z_ctrl_4),
.z_address_4 (z_address_4),
.z_out (z_out)
);
/***************************************************************************/
/* All the random stuff that used to be inferred at this level */
/***************************************************************************/
de_top_misc D_MISC
(
.de_clk (de_clk),
.sys_locked (sys_locked),
.hb_clk (hb_clk),
.hb_rstn (hb_rstn),
.ps_2 (dr_buf_ctrl_2[8:7]),
.pc_mc_rdy (pc_mc_rdy),
.busy_hb (busy_hb),
.mw_de_fip (mw_de_fip),
.dr_style_2 (dr_style_2),
.dx_blt_actv_2 (dx_blt_actv_2),
.load_actvn (load_actvn),
.line_actv_2 (line_actv_2),
.wb_clip_ind (wb_clip_ind),
.clip (clip),
.cmd_trig_comb (cmd_trig_comb),
.line_actv_1 (line_actv_1),
.blt_actv_1 (blt_actv_1),
.de_key_2 (de_key_2),
.deb (deb),
.cmdcpyclr (cmdcpyclr),
.pc_empty (pc_empty),
.pal_busy (pal_busy),
// outputs
.mw_fip (mw_fip),
.ca_busy (ca_busy),
.ps8_2 (ps8_2),
.ps16_2 (ps16_2),
.ps32_2 (ps32_2),
.de_pad8_2 (de_pad8_2),
.stpl_2 (stpl_2),
.de_rstn (de_rstn),
.dx_clp (dx_clp),
.dx_deb (dx_deb),
.de_trnsp_2 (de_trnsp_2),
.kcol_2 (kcol_2),
.de_clint_tog (de_clint_tog),
.de_ddint_tog (de_ddint_tog)
);
// assign dx_mem_rmw = 1'b0;
`ifdef CORE_3D
/***************************************************************************/
/* 3D Core if included. */
/***************************************************************************/
wire [31:0] hb_dout_3d;
de3d_top
#(.fract (9),
.BYTES (BYTES)
)
u_de3d_top
(
.hb_clk (hb_clk),
.hb_rstn (hb_rstn),
.hb_din (hb_din),
.dlp_adr (dlp_adr[8:2]),
.hb_adr_r (hb_adr_bp2[8:2]),
.hb_wstrb (hb_wstrb),
.hb_ben (hb_ben),
.hb_cp_csn (hb_csn_de),
.cp_hb_dout (hb_dout_3d),
.de_clk (de_clk),
.de_rstn (de_rstn),
// 2D Engine Interface.
.back_2 (dr_back_2),
.fore_2 (dr_fore_2),
.solid_2 (solid_2),
.ps_15 (ps_15),
.ps_2 (dr_buf_ctrl_2[8:7]),
.trnsp_2 (de_trnsp_2),
.mcrdy (1'b0),
.stpl_2 (stpl_2),
.stpl_pk_1 (1'b0),
.apat32_2 (1'b0),
.nlst_2 (dr_nlst_2),
.mw_fip (mw_fip),
.pal_load (pal_load),
.tc_inv_cmd (tc_inv_cmd),
.clp_2 (dr_clp_2),
.clptl_2 (clptl_2),
.clpbr_2 (clpbr_2),
.load_15 (load_15),
.load_actvn (load_actvn),
.l3_fg_bgn (dx_fg_bgn),
// Setup engine control..
.go_sup (go_sup),
.load_actv_3d (load_actv_3d),
.sup_done (sup_done),
.abort_cmd (abort_cmd),
// Pixel Cache Interface.
// .pc_busy (~pc_mc_rdy),
.pc_busy (pc_busy_3d),
.pc_valid (valid_3d),
.pc_fg_bgn (fg_bgn_3d),
.pc_x_out (x_out_3d),
.pc_y_out (y_out_3d),
.pc_last (last_3d),
.pc_msk_last (msk_last_3d),
.pc_formatted_pixel (pixel_3d),
.pc_formatted_z (z_3d),
.pc_z_ctrl (z_ctrl),
.pc_active_3d_2 (active_3d_2),
.pc_current_alpha (alpha_3d),
.pc_zorg_2 (zorg_2),
.pc_zptch_2 (zptch_2),
.tporg_2 (tporg_2),
// TC MC Signals.
.mclock (mclock),
.mc_tc_push (mc_tc_push),
.mc_tc_data (mc_tc_data),
.mc_tc_ack (mc_tc_ack),
.mc_pal_ack (mc_pal_ack),
.mc_pal_push (mc_pal_push),
// Outputs.
.mc_tc_req (mc_tc_req),
.mc_tc_page (mc_tc_page),
.mc_tc_address (mc_tc_address),
.mc_pal_req (mc_pal_req),
.mc_pal_half (mc_pal_half),
//
.last_pixel_g0 (cmd_done_3d),
.l3_incpat (l3_incpat),
.pal_busy (pal_busy)
);
assign mc_pal_address = {11'b0, tporg_2};
assign dr_hbdout = hb_dout_3d | hb_dout_2d;
`else
assign dr_hbdout = hb_dout_2d;
`endif
endmodule
|
//********************************************************************
//
// clock_gen.v
//
// This file is part of the DLX3 project
// http://
//
// Description : A simple clock generator for DLX3 testbench
//
//
// Author : [email protected]
// Date : Mon Jan 31 23:15:45 2011
//
//********************************************************************
//
// Copyright (C) 2010 Ronan Barzic
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//********************************************************************
module clock_gen (/*AUTOARG*/
// Outputs
clk
);
parameter period = 20;
output clk;
reg clk;
always #(period/2) clk = !clk;
initial begin
clk = 1'b0;
end
endmodule // clock_gen
/*
Local Variables:
verilog-library-directories:(
"."
)
End:
*/
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O32AI_4_V
`define SKY130_FD_SC_LP__O32AI_4_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o32ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o32ai_4 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o32ai_4 (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O32AI_4_V
|
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29441 $
// $Date: 2012-08-27 21:58:03 +0000 (Mon, 27 Aug 2012) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module RegN(CLK, RST, Q_OUT, D_IN, EN);
parameter width = 1;
parameter init = { width {1'b0} } ;
input CLK;
input RST;
input EN;
input [width - 1 : 0] D_IN;
output [width - 1 : 0] Q_OUT;
reg [width - 1 : 0] Q_OUT;
always@(posedge CLK)
begin
if (RST == `BSV_RESET_VALUE)
Q_OUT <= `BSV_ASSIGNMENT_DELAY init;
else
begin
if (EN)
Q_OUT <= `BSV_ASSIGNMENT_DELAY D_IN;
end // else: !if(RST == `BSV_RESET_VALUE)
end
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial begin
Q_OUT = {((width + 1)/2){2'b10}} ;
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule
|
//
// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_reset O 1
// RDY_set_verbosity O 1 const
// v_from_masters_0_awready O 1 reg
// v_from_masters_0_wready O 1 reg
// v_from_masters_0_bvalid O 1 reg
// v_from_masters_0_bid O 4 reg
// v_from_masters_0_bresp O 2 reg
// v_from_masters_0_arready O 1 reg
// v_from_masters_0_rvalid O 1 reg
// v_from_masters_0_rid O 4 reg
// v_from_masters_0_rdata O 64 reg
// v_from_masters_0_rresp O 2 reg
// v_from_masters_0_rlast O 1 reg
// v_from_masters_1_awready O 1 reg
// v_from_masters_1_wready O 1 reg
// v_from_masters_1_bvalid O 1 reg
// v_from_masters_1_bid O 4 reg
// v_from_masters_1_bresp O 2 reg
// v_from_masters_1_arready O 1 reg
// v_from_masters_1_rvalid O 1 reg
// v_from_masters_1_rid O 4 reg
// v_from_masters_1_rdata O 64 reg
// v_from_masters_1_rresp O 2 reg
// v_from_masters_1_rlast O 1 reg
// v_to_slaves_0_awvalid O 1 reg
// v_to_slaves_0_awid O 4 reg
// v_to_slaves_0_awaddr O 64 reg
// v_to_slaves_0_awlen O 8 reg
// v_to_slaves_0_awsize O 3 reg
// v_to_slaves_0_awburst O 2 reg
// v_to_slaves_0_awlock O 1 reg
// v_to_slaves_0_awcache O 4 reg
// v_to_slaves_0_awprot O 3 reg
// v_to_slaves_0_awqos O 4 reg
// v_to_slaves_0_awregion O 4 reg
// v_to_slaves_0_wvalid O 1 reg
// v_to_slaves_0_wdata O 64 reg
// v_to_slaves_0_wstrb O 8 reg
// v_to_slaves_0_wlast O 1 reg
// v_to_slaves_0_bready O 1 reg
// v_to_slaves_0_arvalid O 1 reg
// v_to_slaves_0_arid O 4 reg
// v_to_slaves_0_araddr O 64 reg
// v_to_slaves_0_arlen O 8 reg
// v_to_slaves_0_arsize O 3 reg
// v_to_slaves_0_arburst O 2 reg
// v_to_slaves_0_arlock O 1 reg
// v_to_slaves_0_arcache O 4 reg
// v_to_slaves_0_arprot O 3 reg
// v_to_slaves_0_arqos O 4 reg
// v_to_slaves_0_arregion O 4 reg
// v_to_slaves_0_rready O 1 reg
// v_to_slaves_1_awvalid O 1 reg
// v_to_slaves_1_awid O 4 reg
// v_to_slaves_1_awaddr O 64 reg
// v_to_slaves_1_awlen O 8 reg
// v_to_slaves_1_awsize O 3 reg
// v_to_slaves_1_awburst O 2 reg
// v_to_slaves_1_awlock O 1 reg
// v_to_slaves_1_awcache O 4 reg
// v_to_slaves_1_awprot O 3 reg
// v_to_slaves_1_awqos O 4 reg
// v_to_slaves_1_awregion O 4 reg
// v_to_slaves_1_wvalid O 1 reg
// v_to_slaves_1_wdata O 64 reg
// v_to_slaves_1_wstrb O 8 reg
// v_to_slaves_1_wlast O 1 reg
// v_to_slaves_1_bready O 1 reg
// v_to_slaves_1_arvalid O 1 reg
// v_to_slaves_1_arid O 4 reg
// v_to_slaves_1_araddr O 64 reg
// v_to_slaves_1_arlen O 8 reg
// v_to_slaves_1_arsize O 3 reg
// v_to_slaves_1_arburst O 2 reg
// v_to_slaves_1_arlock O 1 reg
// v_to_slaves_1_arcache O 4 reg
// v_to_slaves_1_arprot O 3 reg
// v_to_slaves_1_arqos O 4 reg
// v_to_slaves_1_arregion O 4 reg
// v_to_slaves_1_rready O 1 reg
// v_to_slaves_2_awvalid O 1 reg
// v_to_slaves_2_awid O 4 reg
// v_to_slaves_2_awaddr O 64 reg
// v_to_slaves_2_awlen O 8 reg
// v_to_slaves_2_awsize O 3 reg
// v_to_slaves_2_awburst O 2 reg
// v_to_slaves_2_awlock O 1 reg
// v_to_slaves_2_awcache O 4 reg
// v_to_slaves_2_awprot O 3 reg
// v_to_slaves_2_awqos O 4 reg
// v_to_slaves_2_awregion O 4 reg
// v_to_slaves_2_wvalid O 1 reg
// v_to_slaves_2_wdata O 64 reg
// v_to_slaves_2_wstrb O 8 reg
// v_to_slaves_2_wlast O 1 reg
// v_to_slaves_2_bready O 1 reg
// v_to_slaves_2_arvalid O 1 reg
// v_to_slaves_2_arid O 4 reg
// v_to_slaves_2_araddr O 64 reg
// v_to_slaves_2_arlen O 8 reg
// v_to_slaves_2_arsize O 3 reg
// v_to_slaves_2_arburst O 2 reg
// v_to_slaves_2_arlock O 1 reg
// v_to_slaves_2_arcache O 4 reg
// v_to_slaves_2_arprot O 3 reg
// v_to_slaves_2_arqos O 4 reg
// v_to_slaves_2_arregion O 4 reg
// v_to_slaves_2_rready O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// set_verbosity_verbosity I 4 reg
// v_from_masters_0_awvalid I 1
// v_from_masters_0_awid I 4 reg
// v_from_masters_0_awaddr I 64 reg
// v_from_masters_0_awlen I 8 reg
// v_from_masters_0_awsize I 3 reg
// v_from_masters_0_awburst I 2 reg
// v_from_masters_0_awlock I 1 reg
// v_from_masters_0_awcache I 4 reg
// v_from_masters_0_awprot I 3 reg
// v_from_masters_0_awqos I 4 reg
// v_from_masters_0_awregion I 4 reg
// v_from_masters_0_wvalid I 1
// v_from_masters_0_wdata I 64 reg
// v_from_masters_0_wstrb I 8 reg
// v_from_masters_0_wlast I 1 reg
// v_from_masters_0_bready I 1
// v_from_masters_0_arvalid I 1
// v_from_masters_0_arid I 4 reg
// v_from_masters_0_araddr I 64 reg
// v_from_masters_0_arlen I 8 reg
// v_from_masters_0_arsize I 3 reg
// v_from_masters_0_arburst I 2 reg
// v_from_masters_0_arlock I 1 reg
// v_from_masters_0_arcache I 4 reg
// v_from_masters_0_arprot I 3 reg
// v_from_masters_0_arqos I 4 reg
// v_from_masters_0_arregion I 4 reg
// v_from_masters_0_rready I 1
// v_from_masters_1_awvalid I 1
// v_from_masters_1_awid I 4 reg
// v_from_masters_1_awaddr I 64 reg
// v_from_masters_1_awlen I 8 reg
// v_from_masters_1_awsize I 3 reg
// v_from_masters_1_awburst I 2 reg
// v_from_masters_1_awlock I 1 reg
// v_from_masters_1_awcache I 4 reg
// v_from_masters_1_awprot I 3 reg
// v_from_masters_1_awqos I 4 reg
// v_from_masters_1_awregion I 4 reg
// v_from_masters_1_wvalid I 1
// v_from_masters_1_wdata I 64 reg
// v_from_masters_1_wstrb I 8 reg
// v_from_masters_1_wlast I 1 reg
// v_from_masters_1_bready I 1
// v_from_masters_1_arvalid I 1
// v_from_masters_1_arid I 4 reg
// v_from_masters_1_araddr I 64 reg
// v_from_masters_1_arlen I 8 reg
// v_from_masters_1_arsize I 3 reg
// v_from_masters_1_arburst I 2 reg
// v_from_masters_1_arlock I 1 reg
// v_from_masters_1_arcache I 4 reg
// v_from_masters_1_arprot I 3 reg
// v_from_masters_1_arqos I 4 reg
// v_from_masters_1_arregion I 4 reg
// v_from_masters_1_rready I 1
// v_to_slaves_0_awready I 1
// v_to_slaves_0_wready I 1
// v_to_slaves_0_bvalid I 1
// v_to_slaves_0_bid I 4 reg
// v_to_slaves_0_bresp I 2 reg
// v_to_slaves_0_arready I 1
// v_to_slaves_0_rvalid I 1
// v_to_slaves_0_rid I 4 reg
// v_to_slaves_0_rdata I 64 reg
// v_to_slaves_0_rresp I 2 reg
// v_to_slaves_0_rlast I 1 reg
// v_to_slaves_1_awready I 1
// v_to_slaves_1_wready I 1
// v_to_slaves_1_bvalid I 1
// v_to_slaves_1_bid I 4 reg
// v_to_slaves_1_bresp I 2 reg
// v_to_slaves_1_arready I 1
// v_to_slaves_1_rvalid I 1
// v_to_slaves_1_rid I 4 reg
// v_to_slaves_1_rdata I 64 reg
// v_to_slaves_1_rresp I 2 reg
// v_to_slaves_1_rlast I 1 reg
// v_to_slaves_2_awready I 1
// v_to_slaves_2_wready I 1
// v_to_slaves_2_bvalid I 1
// v_to_slaves_2_bid I 4 reg
// v_to_slaves_2_bresp I 2 reg
// v_to_slaves_2_arready I 1
// v_to_slaves_2_rvalid I 1
// v_to_slaves_2_rid I 4 reg
// v_to_slaves_2_rdata I 64 reg
// v_to_slaves_2_rresp I 2 reg
// v_to_slaves_2_rlast I 1 reg
// EN_reset I 1
// EN_set_verbosity I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkFabric_AXI4(CLK,
RST_N,
EN_reset,
RDY_reset,
set_verbosity_verbosity,
EN_set_verbosity,
RDY_set_verbosity,
v_from_masters_0_awvalid,
v_from_masters_0_awid,
v_from_masters_0_awaddr,
v_from_masters_0_awlen,
v_from_masters_0_awsize,
v_from_masters_0_awburst,
v_from_masters_0_awlock,
v_from_masters_0_awcache,
v_from_masters_0_awprot,
v_from_masters_0_awqos,
v_from_masters_0_awregion,
v_from_masters_0_awready,
v_from_masters_0_wvalid,
v_from_masters_0_wdata,
v_from_masters_0_wstrb,
v_from_masters_0_wlast,
v_from_masters_0_wready,
v_from_masters_0_bvalid,
v_from_masters_0_bid,
v_from_masters_0_bresp,
v_from_masters_0_bready,
v_from_masters_0_arvalid,
v_from_masters_0_arid,
v_from_masters_0_araddr,
v_from_masters_0_arlen,
v_from_masters_0_arsize,
v_from_masters_0_arburst,
v_from_masters_0_arlock,
v_from_masters_0_arcache,
v_from_masters_0_arprot,
v_from_masters_0_arqos,
v_from_masters_0_arregion,
v_from_masters_0_arready,
v_from_masters_0_rvalid,
v_from_masters_0_rid,
v_from_masters_0_rdata,
v_from_masters_0_rresp,
v_from_masters_0_rlast,
v_from_masters_0_rready,
v_from_masters_1_awvalid,
v_from_masters_1_awid,
v_from_masters_1_awaddr,
v_from_masters_1_awlen,
v_from_masters_1_awsize,
v_from_masters_1_awburst,
v_from_masters_1_awlock,
v_from_masters_1_awcache,
v_from_masters_1_awprot,
v_from_masters_1_awqos,
v_from_masters_1_awregion,
v_from_masters_1_awready,
v_from_masters_1_wvalid,
v_from_masters_1_wdata,
v_from_masters_1_wstrb,
v_from_masters_1_wlast,
v_from_masters_1_wready,
v_from_masters_1_bvalid,
v_from_masters_1_bid,
v_from_masters_1_bresp,
v_from_masters_1_bready,
v_from_masters_1_arvalid,
v_from_masters_1_arid,
v_from_masters_1_araddr,
v_from_masters_1_arlen,
v_from_masters_1_arsize,
v_from_masters_1_arburst,
v_from_masters_1_arlock,
v_from_masters_1_arcache,
v_from_masters_1_arprot,
v_from_masters_1_arqos,
v_from_masters_1_arregion,
v_from_masters_1_arready,
v_from_masters_1_rvalid,
v_from_masters_1_rid,
v_from_masters_1_rdata,
v_from_masters_1_rresp,
v_from_masters_1_rlast,
v_from_masters_1_rready,
v_to_slaves_0_awvalid,
v_to_slaves_0_awid,
v_to_slaves_0_awaddr,
v_to_slaves_0_awlen,
v_to_slaves_0_awsize,
v_to_slaves_0_awburst,
v_to_slaves_0_awlock,
v_to_slaves_0_awcache,
v_to_slaves_0_awprot,
v_to_slaves_0_awqos,
v_to_slaves_0_awregion,
v_to_slaves_0_awready,
v_to_slaves_0_wvalid,
v_to_slaves_0_wdata,
v_to_slaves_0_wstrb,
v_to_slaves_0_wlast,
v_to_slaves_0_wready,
v_to_slaves_0_bvalid,
v_to_slaves_0_bid,
v_to_slaves_0_bresp,
v_to_slaves_0_bready,
v_to_slaves_0_arvalid,
v_to_slaves_0_arid,
v_to_slaves_0_araddr,
v_to_slaves_0_arlen,
v_to_slaves_0_arsize,
v_to_slaves_0_arburst,
v_to_slaves_0_arlock,
v_to_slaves_0_arcache,
v_to_slaves_0_arprot,
v_to_slaves_0_arqos,
v_to_slaves_0_arregion,
v_to_slaves_0_arready,
v_to_slaves_0_rvalid,
v_to_slaves_0_rid,
v_to_slaves_0_rdata,
v_to_slaves_0_rresp,
v_to_slaves_0_rlast,
v_to_slaves_0_rready,
v_to_slaves_1_awvalid,
v_to_slaves_1_awid,
v_to_slaves_1_awaddr,
v_to_slaves_1_awlen,
v_to_slaves_1_awsize,
v_to_slaves_1_awburst,
v_to_slaves_1_awlock,
v_to_slaves_1_awcache,
v_to_slaves_1_awprot,
v_to_slaves_1_awqos,
v_to_slaves_1_awregion,
v_to_slaves_1_awready,
v_to_slaves_1_wvalid,
v_to_slaves_1_wdata,
v_to_slaves_1_wstrb,
v_to_slaves_1_wlast,
v_to_slaves_1_wready,
v_to_slaves_1_bvalid,
v_to_slaves_1_bid,
v_to_slaves_1_bresp,
v_to_slaves_1_bready,
v_to_slaves_1_arvalid,
v_to_slaves_1_arid,
v_to_slaves_1_araddr,
v_to_slaves_1_arlen,
v_to_slaves_1_arsize,
v_to_slaves_1_arburst,
v_to_slaves_1_arlock,
v_to_slaves_1_arcache,
v_to_slaves_1_arprot,
v_to_slaves_1_arqos,
v_to_slaves_1_arregion,
v_to_slaves_1_arready,
v_to_slaves_1_rvalid,
v_to_slaves_1_rid,
v_to_slaves_1_rdata,
v_to_slaves_1_rresp,
v_to_slaves_1_rlast,
v_to_slaves_1_rready,
v_to_slaves_2_awvalid,
v_to_slaves_2_awid,
v_to_slaves_2_awaddr,
v_to_slaves_2_awlen,
v_to_slaves_2_awsize,
v_to_slaves_2_awburst,
v_to_slaves_2_awlock,
v_to_slaves_2_awcache,
v_to_slaves_2_awprot,
v_to_slaves_2_awqos,
v_to_slaves_2_awregion,
v_to_slaves_2_awready,
v_to_slaves_2_wvalid,
v_to_slaves_2_wdata,
v_to_slaves_2_wstrb,
v_to_slaves_2_wlast,
v_to_slaves_2_wready,
v_to_slaves_2_bvalid,
v_to_slaves_2_bid,
v_to_slaves_2_bresp,
v_to_slaves_2_bready,
v_to_slaves_2_arvalid,
v_to_slaves_2_arid,
v_to_slaves_2_araddr,
v_to_slaves_2_arlen,
v_to_slaves_2_arsize,
v_to_slaves_2_arburst,
v_to_slaves_2_arlock,
v_to_slaves_2_arcache,
v_to_slaves_2_arprot,
v_to_slaves_2_arqos,
v_to_slaves_2_arregion,
v_to_slaves_2_arready,
v_to_slaves_2_rvalid,
v_to_slaves_2_rid,
v_to_slaves_2_rdata,
v_to_slaves_2_rresp,
v_to_slaves_2_rlast,
v_to_slaves_2_rready);
input CLK;
input RST_N;
// action method reset
input EN_reset;
output RDY_reset;
// action method set_verbosity
input [3 : 0] set_verbosity_verbosity;
input EN_set_verbosity;
output RDY_set_verbosity;
// action method v_from_masters_0_m_awvalid
input v_from_masters_0_awvalid;
input [3 : 0] v_from_masters_0_awid;
input [63 : 0] v_from_masters_0_awaddr;
input [7 : 0] v_from_masters_0_awlen;
input [2 : 0] v_from_masters_0_awsize;
input [1 : 0] v_from_masters_0_awburst;
input v_from_masters_0_awlock;
input [3 : 0] v_from_masters_0_awcache;
input [2 : 0] v_from_masters_0_awprot;
input [3 : 0] v_from_masters_0_awqos;
input [3 : 0] v_from_masters_0_awregion;
// value method v_from_masters_0_m_awready
output v_from_masters_0_awready;
// action method v_from_masters_0_m_wvalid
input v_from_masters_0_wvalid;
input [63 : 0] v_from_masters_0_wdata;
input [7 : 0] v_from_masters_0_wstrb;
input v_from_masters_0_wlast;
// value method v_from_masters_0_m_wready
output v_from_masters_0_wready;
// value method v_from_masters_0_m_bvalid
output v_from_masters_0_bvalid;
// value method v_from_masters_0_m_bid
output [3 : 0] v_from_masters_0_bid;
// value method v_from_masters_0_m_bresp
output [1 : 0] v_from_masters_0_bresp;
// value method v_from_masters_0_m_buser
// action method v_from_masters_0_m_bready
input v_from_masters_0_bready;
// action method v_from_masters_0_m_arvalid
input v_from_masters_0_arvalid;
input [3 : 0] v_from_masters_0_arid;
input [63 : 0] v_from_masters_0_araddr;
input [7 : 0] v_from_masters_0_arlen;
input [2 : 0] v_from_masters_0_arsize;
input [1 : 0] v_from_masters_0_arburst;
input v_from_masters_0_arlock;
input [3 : 0] v_from_masters_0_arcache;
input [2 : 0] v_from_masters_0_arprot;
input [3 : 0] v_from_masters_0_arqos;
input [3 : 0] v_from_masters_0_arregion;
// value method v_from_masters_0_m_arready
output v_from_masters_0_arready;
// value method v_from_masters_0_m_rvalid
output v_from_masters_0_rvalid;
// value method v_from_masters_0_m_rid
output [3 : 0] v_from_masters_0_rid;
// value method v_from_masters_0_m_rdata
output [63 : 0] v_from_masters_0_rdata;
// value method v_from_masters_0_m_rresp
output [1 : 0] v_from_masters_0_rresp;
// value method v_from_masters_0_m_rlast
output v_from_masters_0_rlast;
// value method v_from_masters_0_m_ruser
// action method v_from_masters_0_m_rready
input v_from_masters_0_rready;
// action method v_from_masters_1_m_awvalid
input v_from_masters_1_awvalid;
input [3 : 0] v_from_masters_1_awid;
input [63 : 0] v_from_masters_1_awaddr;
input [7 : 0] v_from_masters_1_awlen;
input [2 : 0] v_from_masters_1_awsize;
input [1 : 0] v_from_masters_1_awburst;
input v_from_masters_1_awlock;
input [3 : 0] v_from_masters_1_awcache;
input [2 : 0] v_from_masters_1_awprot;
input [3 : 0] v_from_masters_1_awqos;
input [3 : 0] v_from_masters_1_awregion;
// value method v_from_masters_1_m_awready
output v_from_masters_1_awready;
// action method v_from_masters_1_m_wvalid
input v_from_masters_1_wvalid;
input [63 : 0] v_from_masters_1_wdata;
input [7 : 0] v_from_masters_1_wstrb;
input v_from_masters_1_wlast;
// value method v_from_masters_1_m_wready
output v_from_masters_1_wready;
// value method v_from_masters_1_m_bvalid
output v_from_masters_1_bvalid;
// value method v_from_masters_1_m_bid
output [3 : 0] v_from_masters_1_bid;
// value method v_from_masters_1_m_bresp
output [1 : 0] v_from_masters_1_bresp;
// value method v_from_masters_1_m_buser
// action method v_from_masters_1_m_bready
input v_from_masters_1_bready;
// action method v_from_masters_1_m_arvalid
input v_from_masters_1_arvalid;
input [3 : 0] v_from_masters_1_arid;
input [63 : 0] v_from_masters_1_araddr;
input [7 : 0] v_from_masters_1_arlen;
input [2 : 0] v_from_masters_1_arsize;
input [1 : 0] v_from_masters_1_arburst;
input v_from_masters_1_arlock;
input [3 : 0] v_from_masters_1_arcache;
input [2 : 0] v_from_masters_1_arprot;
input [3 : 0] v_from_masters_1_arqos;
input [3 : 0] v_from_masters_1_arregion;
// value method v_from_masters_1_m_arready
output v_from_masters_1_arready;
// value method v_from_masters_1_m_rvalid
output v_from_masters_1_rvalid;
// value method v_from_masters_1_m_rid
output [3 : 0] v_from_masters_1_rid;
// value method v_from_masters_1_m_rdata
output [63 : 0] v_from_masters_1_rdata;
// value method v_from_masters_1_m_rresp
output [1 : 0] v_from_masters_1_rresp;
// value method v_from_masters_1_m_rlast
output v_from_masters_1_rlast;
// value method v_from_masters_1_m_ruser
// action method v_from_masters_1_m_rready
input v_from_masters_1_rready;
// value method v_to_slaves_0_m_awvalid
output v_to_slaves_0_awvalid;
// value method v_to_slaves_0_m_awid
output [3 : 0] v_to_slaves_0_awid;
// value method v_to_slaves_0_m_awaddr
output [63 : 0] v_to_slaves_0_awaddr;
// value method v_to_slaves_0_m_awlen
output [7 : 0] v_to_slaves_0_awlen;
// value method v_to_slaves_0_m_awsize
output [2 : 0] v_to_slaves_0_awsize;
// value method v_to_slaves_0_m_awburst
output [1 : 0] v_to_slaves_0_awburst;
// value method v_to_slaves_0_m_awlock
output v_to_slaves_0_awlock;
// value method v_to_slaves_0_m_awcache
output [3 : 0] v_to_slaves_0_awcache;
// value method v_to_slaves_0_m_awprot
output [2 : 0] v_to_slaves_0_awprot;
// value method v_to_slaves_0_m_awqos
output [3 : 0] v_to_slaves_0_awqos;
// value method v_to_slaves_0_m_awregion
output [3 : 0] v_to_slaves_0_awregion;
// value method v_to_slaves_0_m_awuser
// action method v_to_slaves_0_m_awready
input v_to_slaves_0_awready;
// value method v_to_slaves_0_m_wvalid
output v_to_slaves_0_wvalid;
// value method v_to_slaves_0_m_wdata
output [63 : 0] v_to_slaves_0_wdata;
// value method v_to_slaves_0_m_wstrb
output [7 : 0] v_to_slaves_0_wstrb;
// value method v_to_slaves_0_m_wlast
output v_to_slaves_0_wlast;
// value method v_to_slaves_0_m_wuser
// action method v_to_slaves_0_m_wready
input v_to_slaves_0_wready;
// action method v_to_slaves_0_m_bvalid
input v_to_slaves_0_bvalid;
input [3 : 0] v_to_slaves_0_bid;
input [1 : 0] v_to_slaves_0_bresp;
// value method v_to_slaves_0_m_bready
output v_to_slaves_0_bready;
// value method v_to_slaves_0_m_arvalid
output v_to_slaves_0_arvalid;
// value method v_to_slaves_0_m_arid
output [3 : 0] v_to_slaves_0_arid;
// value method v_to_slaves_0_m_araddr
output [63 : 0] v_to_slaves_0_araddr;
// value method v_to_slaves_0_m_arlen
output [7 : 0] v_to_slaves_0_arlen;
// value method v_to_slaves_0_m_arsize
output [2 : 0] v_to_slaves_0_arsize;
// value method v_to_slaves_0_m_arburst
output [1 : 0] v_to_slaves_0_arburst;
// value method v_to_slaves_0_m_arlock
output v_to_slaves_0_arlock;
// value method v_to_slaves_0_m_arcache
output [3 : 0] v_to_slaves_0_arcache;
// value method v_to_slaves_0_m_arprot
output [2 : 0] v_to_slaves_0_arprot;
// value method v_to_slaves_0_m_arqos
output [3 : 0] v_to_slaves_0_arqos;
// value method v_to_slaves_0_m_arregion
output [3 : 0] v_to_slaves_0_arregion;
// value method v_to_slaves_0_m_aruser
// action method v_to_slaves_0_m_arready
input v_to_slaves_0_arready;
// action method v_to_slaves_0_m_rvalid
input v_to_slaves_0_rvalid;
input [3 : 0] v_to_slaves_0_rid;
input [63 : 0] v_to_slaves_0_rdata;
input [1 : 0] v_to_slaves_0_rresp;
input v_to_slaves_0_rlast;
// value method v_to_slaves_0_m_rready
output v_to_slaves_0_rready;
// value method v_to_slaves_1_m_awvalid
output v_to_slaves_1_awvalid;
// value method v_to_slaves_1_m_awid
output [3 : 0] v_to_slaves_1_awid;
// value method v_to_slaves_1_m_awaddr
output [63 : 0] v_to_slaves_1_awaddr;
// value method v_to_slaves_1_m_awlen
output [7 : 0] v_to_slaves_1_awlen;
// value method v_to_slaves_1_m_awsize
output [2 : 0] v_to_slaves_1_awsize;
// value method v_to_slaves_1_m_awburst
output [1 : 0] v_to_slaves_1_awburst;
// value method v_to_slaves_1_m_awlock
output v_to_slaves_1_awlock;
// value method v_to_slaves_1_m_awcache
output [3 : 0] v_to_slaves_1_awcache;
// value method v_to_slaves_1_m_awprot
output [2 : 0] v_to_slaves_1_awprot;
// value method v_to_slaves_1_m_awqos
output [3 : 0] v_to_slaves_1_awqos;
// value method v_to_slaves_1_m_awregion
output [3 : 0] v_to_slaves_1_awregion;
// value method v_to_slaves_1_m_awuser
// action method v_to_slaves_1_m_awready
input v_to_slaves_1_awready;
// value method v_to_slaves_1_m_wvalid
output v_to_slaves_1_wvalid;
// value method v_to_slaves_1_m_wdata
output [63 : 0] v_to_slaves_1_wdata;
// value method v_to_slaves_1_m_wstrb
output [7 : 0] v_to_slaves_1_wstrb;
// value method v_to_slaves_1_m_wlast
output v_to_slaves_1_wlast;
// value method v_to_slaves_1_m_wuser
// action method v_to_slaves_1_m_wready
input v_to_slaves_1_wready;
// action method v_to_slaves_1_m_bvalid
input v_to_slaves_1_bvalid;
input [3 : 0] v_to_slaves_1_bid;
input [1 : 0] v_to_slaves_1_bresp;
// value method v_to_slaves_1_m_bready
output v_to_slaves_1_bready;
// value method v_to_slaves_1_m_arvalid
output v_to_slaves_1_arvalid;
// value method v_to_slaves_1_m_arid
output [3 : 0] v_to_slaves_1_arid;
// value method v_to_slaves_1_m_araddr
output [63 : 0] v_to_slaves_1_araddr;
// value method v_to_slaves_1_m_arlen
output [7 : 0] v_to_slaves_1_arlen;
// value method v_to_slaves_1_m_arsize
output [2 : 0] v_to_slaves_1_arsize;
// value method v_to_slaves_1_m_arburst
output [1 : 0] v_to_slaves_1_arburst;
// value method v_to_slaves_1_m_arlock
output v_to_slaves_1_arlock;
// value method v_to_slaves_1_m_arcache
output [3 : 0] v_to_slaves_1_arcache;
// value method v_to_slaves_1_m_arprot
output [2 : 0] v_to_slaves_1_arprot;
// value method v_to_slaves_1_m_arqos
output [3 : 0] v_to_slaves_1_arqos;
// value method v_to_slaves_1_m_arregion
output [3 : 0] v_to_slaves_1_arregion;
// value method v_to_slaves_1_m_aruser
// action method v_to_slaves_1_m_arready
input v_to_slaves_1_arready;
// action method v_to_slaves_1_m_rvalid
input v_to_slaves_1_rvalid;
input [3 : 0] v_to_slaves_1_rid;
input [63 : 0] v_to_slaves_1_rdata;
input [1 : 0] v_to_slaves_1_rresp;
input v_to_slaves_1_rlast;
// value method v_to_slaves_1_m_rready
output v_to_slaves_1_rready;
// value method v_to_slaves_2_m_awvalid
output v_to_slaves_2_awvalid;
// value method v_to_slaves_2_m_awid
output [3 : 0] v_to_slaves_2_awid;
// value method v_to_slaves_2_m_awaddr
output [63 : 0] v_to_slaves_2_awaddr;
// value method v_to_slaves_2_m_awlen
output [7 : 0] v_to_slaves_2_awlen;
// value method v_to_slaves_2_m_awsize
output [2 : 0] v_to_slaves_2_awsize;
// value method v_to_slaves_2_m_awburst
output [1 : 0] v_to_slaves_2_awburst;
// value method v_to_slaves_2_m_awlock
output v_to_slaves_2_awlock;
// value method v_to_slaves_2_m_awcache
output [3 : 0] v_to_slaves_2_awcache;
// value method v_to_slaves_2_m_awprot
output [2 : 0] v_to_slaves_2_awprot;
// value method v_to_slaves_2_m_awqos
output [3 : 0] v_to_slaves_2_awqos;
// value method v_to_slaves_2_m_awregion
output [3 : 0] v_to_slaves_2_awregion;
// value method v_to_slaves_2_m_awuser
// action method v_to_slaves_2_m_awready
input v_to_slaves_2_awready;
// value method v_to_slaves_2_m_wvalid
output v_to_slaves_2_wvalid;
// value method v_to_slaves_2_m_wdata
output [63 : 0] v_to_slaves_2_wdata;
// value method v_to_slaves_2_m_wstrb
output [7 : 0] v_to_slaves_2_wstrb;
// value method v_to_slaves_2_m_wlast
output v_to_slaves_2_wlast;
// value method v_to_slaves_2_m_wuser
// action method v_to_slaves_2_m_wready
input v_to_slaves_2_wready;
// action method v_to_slaves_2_m_bvalid
input v_to_slaves_2_bvalid;
input [3 : 0] v_to_slaves_2_bid;
input [1 : 0] v_to_slaves_2_bresp;
// value method v_to_slaves_2_m_bready
output v_to_slaves_2_bready;
// value method v_to_slaves_2_m_arvalid
output v_to_slaves_2_arvalid;
// value method v_to_slaves_2_m_arid
output [3 : 0] v_to_slaves_2_arid;
// value method v_to_slaves_2_m_araddr
output [63 : 0] v_to_slaves_2_araddr;
// value method v_to_slaves_2_m_arlen
output [7 : 0] v_to_slaves_2_arlen;
// value method v_to_slaves_2_m_arsize
output [2 : 0] v_to_slaves_2_arsize;
// value method v_to_slaves_2_m_arburst
output [1 : 0] v_to_slaves_2_arburst;
// value method v_to_slaves_2_m_arlock
output v_to_slaves_2_arlock;
// value method v_to_slaves_2_m_arcache
output [3 : 0] v_to_slaves_2_arcache;
// value method v_to_slaves_2_m_arprot
output [2 : 0] v_to_slaves_2_arprot;
// value method v_to_slaves_2_m_arqos
output [3 : 0] v_to_slaves_2_arqos;
// value method v_to_slaves_2_m_arregion
output [3 : 0] v_to_slaves_2_arregion;
// value method v_to_slaves_2_m_aruser
// action method v_to_slaves_2_m_arready
input v_to_slaves_2_arready;
// action method v_to_slaves_2_m_rvalid
input v_to_slaves_2_rvalid;
input [3 : 0] v_to_slaves_2_rid;
input [63 : 0] v_to_slaves_2_rdata;
input [1 : 0] v_to_slaves_2_rresp;
input v_to_slaves_2_rlast;
// value method v_to_slaves_2_m_rready
output v_to_slaves_2_rready;
// signals for module outputs
wire [63 : 0] v_from_masters_0_rdata,
v_from_masters_1_rdata,
v_to_slaves_0_araddr,
v_to_slaves_0_awaddr,
v_to_slaves_0_wdata,
v_to_slaves_1_araddr,
v_to_slaves_1_awaddr,
v_to_slaves_1_wdata,
v_to_slaves_2_araddr,
v_to_slaves_2_awaddr,
v_to_slaves_2_wdata;
wire [7 : 0] v_to_slaves_0_arlen,
v_to_slaves_0_awlen,
v_to_slaves_0_wstrb,
v_to_slaves_1_arlen,
v_to_slaves_1_awlen,
v_to_slaves_1_wstrb,
v_to_slaves_2_arlen,
v_to_slaves_2_awlen,
v_to_slaves_2_wstrb;
wire [3 : 0] v_from_masters_0_bid,
v_from_masters_0_rid,
v_from_masters_1_bid,
v_from_masters_1_rid,
v_to_slaves_0_arcache,
v_to_slaves_0_arid,
v_to_slaves_0_arqos,
v_to_slaves_0_arregion,
v_to_slaves_0_awcache,
v_to_slaves_0_awid,
v_to_slaves_0_awqos,
v_to_slaves_0_awregion,
v_to_slaves_1_arcache,
v_to_slaves_1_arid,
v_to_slaves_1_arqos,
v_to_slaves_1_arregion,
v_to_slaves_1_awcache,
v_to_slaves_1_awid,
v_to_slaves_1_awqos,
v_to_slaves_1_awregion,
v_to_slaves_2_arcache,
v_to_slaves_2_arid,
v_to_slaves_2_arqos,
v_to_slaves_2_arregion,
v_to_slaves_2_awcache,
v_to_slaves_2_awid,
v_to_slaves_2_awqos,
v_to_slaves_2_awregion;
wire [2 : 0] v_to_slaves_0_arprot,
v_to_slaves_0_arsize,
v_to_slaves_0_awprot,
v_to_slaves_0_awsize,
v_to_slaves_1_arprot,
v_to_slaves_1_arsize,
v_to_slaves_1_awprot,
v_to_slaves_1_awsize,
v_to_slaves_2_arprot,
v_to_slaves_2_arsize,
v_to_slaves_2_awprot,
v_to_slaves_2_awsize;
wire [1 : 0] v_from_masters_0_bresp,
v_from_masters_0_rresp,
v_from_masters_1_bresp,
v_from_masters_1_rresp,
v_to_slaves_0_arburst,
v_to_slaves_0_awburst,
v_to_slaves_1_arburst,
v_to_slaves_1_awburst,
v_to_slaves_2_arburst,
v_to_slaves_2_awburst;
wire RDY_reset,
RDY_set_verbosity,
v_from_masters_0_arready,
v_from_masters_0_awready,
v_from_masters_0_bvalid,
v_from_masters_0_rlast,
v_from_masters_0_rvalid,
v_from_masters_0_wready,
v_from_masters_1_arready,
v_from_masters_1_awready,
v_from_masters_1_bvalid,
v_from_masters_1_rlast,
v_from_masters_1_rvalid,
v_from_masters_1_wready,
v_to_slaves_0_arlock,
v_to_slaves_0_arvalid,
v_to_slaves_0_awlock,
v_to_slaves_0_awvalid,
v_to_slaves_0_bready,
v_to_slaves_0_rready,
v_to_slaves_0_wlast,
v_to_slaves_0_wvalid,
v_to_slaves_1_arlock,
v_to_slaves_1_arvalid,
v_to_slaves_1_awlock,
v_to_slaves_1_awvalid,
v_to_slaves_1_bready,
v_to_slaves_1_rready,
v_to_slaves_1_wlast,
v_to_slaves_1_wvalid,
v_to_slaves_2_arlock,
v_to_slaves_2_arvalid,
v_to_slaves_2_awlock,
v_to_slaves_2_awvalid,
v_to_slaves_2_bready,
v_to_slaves_2_rready,
v_to_slaves_2_wlast,
v_to_slaves_2_wvalid;
// register fabric_cfg_verbosity
reg [3 : 0] fabric_cfg_verbosity;
wire [3 : 0] fabric_cfg_verbosity$D_IN;
wire fabric_cfg_verbosity$EN;
// register fabric_rg_reset
reg fabric_rg_reset;
wire fabric_rg_reset$D_IN, fabric_rg_reset$EN;
// register fabric_v_rg_r_beat_count_0
reg [7 : 0] fabric_v_rg_r_beat_count_0;
reg [7 : 0] fabric_v_rg_r_beat_count_0$D_IN;
wire fabric_v_rg_r_beat_count_0$EN;
// register fabric_v_rg_r_beat_count_1
reg [7 : 0] fabric_v_rg_r_beat_count_1;
reg [7 : 0] fabric_v_rg_r_beat_count_1$D_IN;
wire fabric_v_rg_r_beat_count_1$EN;
// register fabric_v_rg_r_beat_count_2
reg [7 : 0] fabric_v_rg_r_beat_count_2;
reg [7 : 0] fabric_v_rg_r_beat_count_2$D_IN;
wire fabric_v_rg_r_beat_count_2$EN;
// register fabric_v_rg_r_err_beat_count_0
reg [7 : 0] fabric_v_rg_r_err_beat_count_0;
wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN;
wire fabric_v_rg_r_err_beat_count_0$EN;
// register fabric_v_rg_r_err_beat_count_1
reg [7 : 0] fabric_v_rg_r_err_beat_count_1;
wire [7 : 0] fabric_v_rg_r_err_beat_count_1$D_IN;
wire fabric_v_rg_r_err_beat_count_1$EN;
// register fabric_v_rg_wd_beat_count_0
reg [7 : 0] fabric_v_rg_wd_beat_count_0;
wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN;
wire fabric_v_rg_wd_beat_count_0$EN;
// register fabric_v_rg_wd_beat_count_1
reg [7 : 0] fabric_v_rg_wd_beat_count_1;
wire [7 : 0] fabric_v_rg_wd_beat_count_1$D_IN;
wire fabric_v_rg_wd_beat_count_1$EN;
// ports of submodule fabric_v_f_rd_err_info_0
wire [11 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT;
wire fabric_v_f_rd_err_info_0$CLR,
fabric_v_f_rd_err_info_0$DEQ,
fabric_v_f_rd_err_info_0$EMPTY_N,
fabric_v_f_rd_err_info_0$ENQ,
fabric_v_f_rd_err_info_0$FULL_N;
// ports of submodule fabric_v_f_rd_err_info_1
wire [11 : 0] fabric_v_f_rd_err_info_1$D_IN, fabric_v_f_rd_err_info_1$D_OUT;
wire fabric_v_f_rd_err_info_1$CLR,
fabric_v_f_rd_err_info_1$DEQ,
fabric_v_f_rd_err_info_1$EMPTY_N,
fabric_v_f_rd_err_info_1$ENQ,
fabric_v_f_rd_err_info_1$FULL_N;
// ports of submodule fabric_v_f_rd_mis_0
wire [9 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT;
wire fabric_v_f_rd_mis_0$CLR,
fabric_v_f_rd_mis_0$DEQ,
fabric_v_f_rd_mis_0$EMPTY_N,
fabric_v_f_rd_mis_0$ENQ,
fabric_v_f_rd_mis_0$FULL_N;
// ports of submodule fabric_v_f_rd_mis_1
wire [9 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT;
wire fabric_v_f_rd_mis_1$CLR,
fabric_v_f_rd_mis_1$DEQ,
fabric_v_f_rd_mis_1$EMPTY_N,
fabric_v_f_rd_mis_1$ENQ,
fabric_v_f_rd_mis_1$FULL_N;
// ports of submodule fabric_v_f_rd_mis_2
wire [9 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT;
wire fabric_v_f_rd_mis_2$CLR,
fabric_v_f_rd_mis_2$DEQ,
fabric_v_f_rd_mis_2$EMPTY_N,
fabric_v_f_rd_mis_2$ENQ,
fabric_v_f_rd_mis_2$FULL_N;
// ports of submodule fabric_v_f_rd_sjs_0
reg [1 : 0] fabric_v_f_rd_sjs_0$D_IN;
wire [1 : 0] fabric_v_f_rd_sjs_0$D_OUT;
wire fabric_v_f_rd_sjs_0$CLR,
fabric_v_f_rd_sjs_0$DEQ,
fabric_v_f_rd_sjs_0$EMPTY_N,
fabric_v_f_rd_sjs_0$ENQ,
fabric_v_f_rd_sjs_0$FULL_N;
// ports of submodule fabric_v_f_rd_sjs_1
reg [1 : 0] fabric_v_f_rd_sjs_1$D_IN;
wire [1 : 0] fabric_v_f_rd_sjs_1$D_OUT;
wire fabric_v_f_rd_sjs_1$CLR,
fabric_v_f_rd_sjs_1$DEQ,
fabric_v_f_rd_sjs_1$EMPTY_N,
fabric_v_f_rd_sjs_1$ENQ,
fabric_v_f_rd_sjs_1$FULL_N;
// ports of submodule fabric_v_f_wd_tasks_0
reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN;
wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT;
wire fabric_v_f_wd_tasks_0$CLR,
fabric_v_f_wd_tasks_0$DEQ,
fabric_v_f_wd_tasks_0$EMPTY_N,
fabric_v_f_wd_tasks_0$ENQ,
fabric_v_f_wd_tasks_0$FULL_N;
// ports of submodule fabric_v_f_wd_tasks_1
reg [9 : 0] fabric_v_f_wd_tasks_1$D_IN;
wire [9 : 0] fabric_v_f_wd_tasks_1$D_OUT;
wire fabric_v_f_wd_tasks_1$CLR,
fabric_v_f_wd_tasks_1$DEQ,
fabric_v_f_wd_tasks_1$EMPTY_N,
fabric_v_f_wd_tasks_1$ENQ,
fabric_v_f_wd_tasks_1$FULL_N;
// ports of submodule fabric_v_f_wr_err_info_0
wire [3 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT;
wire fabric_v_f_wr_err_info_0$CLR,
fabric_v_f_wr_err_info_0$DEQ,
fabric_v_f_wr_err_info_0$EMPTY_N,
fabric_v_f_wr_err_info_0$ENQ,
fabric_v_f_wr_err_info_0$FULL_N;
// ports of submodule fabric_v_f_wr_err_info_1
wire [3 : 0] fabric_v_f_wr_err_info_1$D_IN, fabric_v_f_wr_err_info_1$D_OUT;
wire fabric_v_f_wr_err_info_1$CLR,
fabric_v_f_wr_err_info_1$DEQ,
fabric_v_f_wr_err_info_1$EMPTY_N,
fabric_v_f_wr_err_info_1$ENQ,
fabric_v_f_wr_err_info_1$FULL_N;
// ports of submodule fabric_v_f_wr_mis_0
wire [1 : 0] fabric_v_f_wr_mis_0$D_IN, fabric_v_f_wr_mis_0$D_OUT;
wire fabric_v_f_wr_mis_0$CLR,
fabric_v_f_wr_mis_0$DEQ,
fabric_v_f_wr_mis_0$EMPTY_N,
fabric_v_f_wr_mis_0$ENQ,
fabric_v_f_wr_mis_0$FULL_N;
// ports of submodule fabric_v_f_wr_mis_1
wire [1 : 0] fabric_v_f_wr_mis_1$D_IN, fabric_v_f_wr_mis_1$D_OUT;
wire fabric_v_f_wr_mis_1$CLR,
fabric_v_f_wr_mis_1$DEQ,
fabric_v_f_wr_mis_1$EMPTY_N,
fabric_v_f_wr_mis_1$ENQ,
fabric_v_f_wr_mis_1$FULL_N;
// ports of submodule fabric_v_f_wr_mis_2
wire [1 : 0] fabric_v_f_wr_mis_2$D_IN, fabric_v_f_wr_mis_2$D_OUT;
wire fabric_v_f_wr_mis_2$CLR,
fabric_v_f_wr_mis_2$DEQ,
fabric_v_f_wr_mis_2$EMPTY_N,
fabric_v_f_wr_mis_2$ENQ,
fabric_v_f_wr_mis_2$FULL_N;
// ports of submodule fabric_v_f_wr_sjs_0
reg [1 : 0] fabric_v_f_wr_sjs_0$D_IN;
wire [1 : 0] fabric_v_f_wr_sjs_0$D_OUT;
wire fabric_v_f_wr_sjs_0$CLR,
fabric_v_f_wr_sjs_0$DEQ,
fabric_v_f_wr_sjs_0$EMPTY_N,
fabric_v_f_wr_sjs_0$ENQ,
fabric_v_f_wr_sjs_0$FULL_N;
// ports of submodule fabric_v_f_wr_sjs_1
reg [1 : 0] fabric_v_f_wr_sjs_1$D_IN;
wire [1 : 0] fabric_v_f_wr_sjs_1$D_OUT;
wire fabric_v_f_wr_sjs_1$CLR,
fabric_v_f_wr_sjs_1$DEQ,
fabric_v_f_wr_sjs_1$EMPTY_N,
fabric_v_f_wr_sjs_1$ENQ,
fabric_v_f_wr_sjs_1$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_rd_addr
wire [96 : 0] fabric_xactors_from_masters_0_f_rd_addr$D_IN,
fabric_xactors_from_masters_0_f_rd_addr$D_OUT;
wire fabric_xactors_from_masters_0_f_rd_addr$CLR,
fabric_xactors_from_masters_0_f_rd_addr$DEQ,
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N,
fabric_xactors_from_masters_0_f_rd_addr$ENQ,
fabric_xactors_from_masters_0_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_rd_data
reg [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_IN;
wire [70 : 0] fabric_xactors_from_masters_0_f_rd_data$D_OUT;
wire fabric_xactors_from_masters_0_f_rd_data$CLR,
fabric_xactors_from_masters_0_f_rd_data$DEQ,
fabric_xactors_from_masters_0_f_rd_data$EMPTY_N,
fabric_xactors_from_masters_0_f_rd_data$ENQ,
fabric_xactors_from_masters_0_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_wr_addr
wire [96 : 0] fabric_xactors_from_masters_0_f_wr_addr$D_IN,
fabric_xactors_from_masters_0_f_wr_addr$D_OUT;
wire fabric_xactors_from_masters_0_f_wr_addr$CLR,
fabric_xactors_from_masters_0_f_wr_addr$DEQ,
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N,
fabric_xactors_from_masters_0_f_wr_addr$ENQ,
fabric_xactors_from_masters_0_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_wr_data
wire [72 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN,
fabric_xactors_from_masters_0_f_wr_data$D_OUT;
wire fabric_xactors_from_masters_0_f_wr_data$CLR,
fabric_xactors_from_masters_0_f_wr_data$DEQ,
fabric_xactors_from_masters_0_f_wr_data$EMPTY_N,
fabric_xactors_from_masters_0_f_wr_data$ENQ,
fabric_xactors_from_masters_0_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_wr_resp
reg [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_IN;
wire [5 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_OUT;
wire fabric_xactors_from_masters_0_f_wr_resp$CLR,
fabric_xactors_from_masters_0_f_wr_resp$DEQ,
fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N,
fabric_xactors_from_masters_0_f_wr_resp$ENQ,
fabric_xactors_from_masters_0_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_from_masters_1_f_rd_addr
wire [96 : 0] fabric_xactors_from_masters_1_f_rd_addr$D_IN,
fabric_xactors_from_masters_1_f_rd_addr$D_OUT;
wire fabric_xactors_from_masters_1_f_rd_addr$CLR,
fabric_xactors_from_masters_1_f_rd_addr$DEQ,
fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N,
fabric_xactors_from_masters_1_f_rd_addr$ENQ,
fabric_xactors_from_masters_1_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_from_masters_1_f_rd_data
reg [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_IN;
wire [70 : 0] fabric_xactors_from_masters_1_f_rd_data$D_OUT;
wire fabric_xactors_from_masters_1_f_rd_data$CLR,
fabric_xactors_from_masters_1_f_rd_data$DEQ,
fabric_xactors_from_masters_1_f_rd_data$EMPTY_N,
fabric_xactors_from_masters_1_f_rd_data$ENQ,
fabric_xactors_from_masters_1_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_from_masters_1_f_wr_addr
wire [96 : 0] fabric_xactors_from_masters_1_f_wr_addr$D_IN,
fabric_xactors_from_masters_1_f_wr_addr$D_OUT;
wire fabric_xactors_from_masters_1_f_wr_addr$CLR,
fabric_xactors_from_masters_1_f_wr_addr$DEQ,
fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N,
fabric_xactors_from_masters_1_f_wr_addr$ENQ,
fabric_xactors_from_masters_1_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_from_masters_1_f_wr_data
wire [72 : 0] fabric_xactors_from_masters_1_f_wr_data$D_IN,
fabric_xactors_from_masters_1_f_wr_data$D_OUT;
wire fabric_xactors_from_masters_1_f_wr_data$CLR,
fabric_xactors_from_masters_1_f_wr_data$DEQ,
fabric_xactors_from_masters_1_f_wr_data$EMPTY_N,
fabric_xactors_from_masters_1_f_wr_data$ENQ,
fabric_xactors_from_masters_1_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_from_masters_1_f_wr_resp
reg [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_IN;
wire [5 : 0] fabric_xactors_from_masters_1_f_wr_resp$D_OUT;
wire fabric_xactors_from_masters_1_f_wr_resp$CLR,
fabric_xactors_from_masters_1_f_wr_resp$DEQ,
fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N,
fabric_xactors_from_masters_1_f_wr_resp$ENQ,
fabric_xactors_from_masters_1_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_rd_addr
wire [96 : 0] fabric_xactors_to_slaves_0_f_rd_addr$D_IN,
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT;
wire fabric_xactors_to_slaves_0_f_rd_addr$CLR,
fabric_xactors_to_slaves_0_f_rd_addr$DEQ,
fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N,
fabric_xactors_to_slaves_0_f_rd_addr$ENQ,
fabric_xactors_to_slaves_0_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_rd_data
wire [70 : 0] fabric_xactors_to_slaves_0_f_rd_data$D_IN,
fabric_xactors_to_slaves_0_f_rd_data$D_OUT;
wire fabric_xactors_to_slaves_0_f_rd_data$CLR,
fabric_xactors_to_slaves_0_f_rd_data$DEQ,
fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N,
fabric_xactors_to_slaves_0_f_rd_data$ENQ,
fabric_xactors_to_slaves_0_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_wr_addr
wire [96 : 0] fabric_xactors_to_slaves_0_f_wr_addr$D_IN,
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT;
wire fabric_xactors_to_slaves_0_f_wr_addr$CLR,
fabric_xactors_to_slaves_0_f_wr_addr$DEQ,
fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N,
fabric_xactors_to_slaves_0_f_wr_addr$ENQ,
fabric_xactors_to_slaves_0_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_wr_data
wire [72 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN,
fabric_xactors_to_slaves_0_f_wr_data$D_OUT;
wire fabric_xactors_to_slaves_0_f_wr_data$CLR,
fabric_xactors_to_slaves_0_f_wr_data$DEQ,
fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N,
fabric_xactors_to_slaves_0_f_wr_data$ENQ,
fabric_xactors_to_slaves_0_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_wr_resp
wire [5 : 0] fabric_xactors_to_slaves_0_f_wr_resp$D_IN,
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT;
wire fabric_xactors_to_slaves_0_f_wr_resp$CLR,
fabric_xactors_to_slaves_0_f_wr_resp$DEQ,
fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N,
fabric_xactors_to_slaves_0_f_wr_resp$ENQ,
fabric_xactors_to_slaves_0_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_rd_addr
wire [96 : 0] fabric_xactors_to_slaves_1_f_rd_addr$D_IN,
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT;
wire fabric_xactors_to_slaves_1_f_rd_addr$CLR,
fabric_xactors_to_slaves_1_f_rd_addr$DEQ,
fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N,
fabric_xactors_to_slaves_1_f_rd_addr$ENQ,
fabric_xactors_to_slaves_1_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_rd_data
wire [70 : 0] fabric_xactors_to_slaves_1_f_rd_data$D_IN,
fabric_xactors_to_slaves_1_f_rd_data$D_OUT;
wire fabric_xactors_to_slaves_1_f_rd_data$CLR,
fabric_xactors_to_slaves_1_f_rd_data$DEQ,
fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N,
fabric_xactors_to_slaves_1_f_rd_data$ENQ,
fabric_xactors_to_slaves_1_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_wr_addr
wire [96 : 0] fabric_xactors_to_slaves_1_f_wr_addr$D_IN,
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT;
wire fabric_xactors_to_slaves_1_f_wr_addr$CLR,
fabric_xactors_to_slaves_1_f_wr_addr$DEQ,
fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N,
fabric_xactors_to_slaves_1_f_wr_addr$ENQ,
fabric_xactors_to_slaves_1_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_wr_data
wire [72 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN,
fabric_xactors_to_slaves_1_f_wr_data$D_OUT;
wire fabric_xactors_to_slaves_1_f_wr_data$CLR,
fabric_xactors_to_slaves_1_f_wr_data$DEQ,
fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N,
fabric_xactors_to_slaves_1_f_wr_data$ENQ,
fabric_xactors_to_slaves_1_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_wr_resp
wire [5 : 0] fabric_xactors_to_slaves_1_f_wr_resp$D_IN,
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT;
wire fabric_xactors_to_slaves_1_f_wr_resp$CLR,
fabric_xactors_to_slaves_1_f_wr_resp$DEQ,
fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N,
fabric_xactors_to_slaves_1_f_wr_resp$ENQ,
fabric_xactors_to_slaves_1_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_rd_addr
wire [96 : 0] fabric_xactors_to_slaves_2_f_rd_addr$D_IN,
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT;
wire fabric_xactors_to_slaves_2_f_rd_addr$CLR,
fabric_xactors_to_slaves_2_f_rd_addr$DEQ,
fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N,
fabric_xactors_to_slaves_2_f_rd_addr$ENQ,
fabric_xactors_to_slaves_2_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_rd_data
wire [70 : 0] fabric_xactors_to_slaves_2_f_rd_data$D_IN,
fabric_xactors_to_slaves_2_f_rd_data$D_OUT;
wire fabric_xactors_to_slaves_2_f_rd_data$CLR,
fabric_xactors_to_slaves_2_f_rd_data$DEQ,
fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N,
fabric_xactors_to_slaves_2_f_rd_data$ENQ,
fabric_xactors_to_slaves_2_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_wr_addr
wire [96 : 0] fabric_xactors_to_slaves_2_f_wr_addr$D_IN,
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT;
wire fabric_xactors_to_slaves_2_f_wr_addr$CLR,
fabric_xactors_to_slaves_2_f_wr_addr$DEQ,
fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N,
fabric_xactors_to_slaves_2_f_wr_addr$ENQ,
fabric_xactors_to_slaves_2_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_wr_data
wire [72 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN,
fabric_xactors_to_slaves_2_f_wr_data$D_OUT;
wire fabric_xactors_to_slaves_2_f_wr_data$CLR,
fabric_xactors_to_slaves_2_f_wr_data$DEQ,
fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N,
fabric_xactors_to_slaves_2_f_wr_data$ENQ,
fabric_xactors_to_slaves_2_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_wr_resp
wire [5 : 0] fabric_xactors_to_slaves_2_f_wr_resp$D_IN,
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT;
wire fabric_xactors_to_slaves_2_f_wr_resp$CLR,
fabric_xactors_to_slaves_2_f_wr_resp$DEQ,
fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N,
fabric_xactors_to_slaves_2_f_wr_resp$ENQ,
fabric_xactors_to_slaves_2_f_wr_resp$FULL_N;
// ports of submodule soc_map
wire [63 : 0] soc_map$m_boot_rom_addr_base,
soc_map$m_boot_rom_addr_lim,
soc_map$m_is_IO_addr_addr,
soc_map$m_is_mem_addr_addr,
soc_map$m_is_near_mem_IO_addr_addr,
soc_map$m_mem0_controller_addr_base,
soc_map$m_mem0_controller_addr_lim,
soc_map$m_uart0_addr_base,
soc_map$m_uart0_addr_lim;
// rule scheduling signals
wire CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master,
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5,
CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave,
CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1,
CAN_FIRE_RL_fabric_rl_reset,
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master,
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1,
CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave,
CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1,
CAN_FIRE_reset,
CAN_FIRE_set_verbosity,
CAN_FIRE_v_from_masters_0_m_arvalid,
CAN_FIRE_v_from_masters_0_m_awvalid,
CAN_FIRE_v_from_masters_0_m_bready,
CAN_FIRE_v_from_masters_0_m_rready,
CAN_FIRE_v_from_masters_0_m_wvalid,
CAN_FIRE_v_from_masters_1_m_arvalid,
CAN_FIRE_v_from_masters_1_m_awvalid,
CAN_FIRE_v_from_masters_1_m_bready,
CAN_FIRE_v_from_masters_1_m_rready,
CAN_FIRE_v_from_masters_1_m_wvalid,
CAN_FIRE_v_to_slaves_0_m_arready,
CAN_FIRE_v_to_slaves_0_m_awready,
CAN_FIRE_v_to_slaves_0_m_bvalid,
CAN_FIRE_v_to_slaves_0_m_rvalid,
CAN_FIRE_v_to_slaves_0_m_wready,
CAN_FIRE_v_to_slaves_1_m_arready,
CAN_FIRE_v_to_slaves_1_m_awready,
CAN_FIRE_v_to_slaves_1_m_bvalid,
CAN_FIRE_v_to_slaves_1_m_rvalid,
CAN_FIRE_v_to_slaves_1_m_wready,
CAN_FIRE_v_to_slaves_2_m_arready,
CAN_FIRE_v_to_slaves_2_m_awready,
CAN_FIRE_v_to_slaves_2_m_bvalid,
CAN_FIRE_v_to_slaves_2_m_rvalid,
CAN_FIRE_v_to_slaves_2_m_wready,
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master,
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5,
WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave,
WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1,
WILL_FIRE_RL_fabric_rl_reset,
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master,
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1,
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave,
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1,
WILL_FIRE_reset,
WILL_FIRE_set_verbosity,
WILL_FIRE_v_from_masters_0_m_arvalid,
WILL_FIRE_v_from_masters_0_m_awvalid,
WILL_FIRE_v_from_masters_0_m_bready,
WILL_FIRE_v_from_masters_0_m_rready,
WILL_FIRE_v_from_masters_0_m_wvalid,
WILL_FIRE_v_from_masters_1_m_arvalid,
WILL_FIRE_v_from_masters_1_m_awvalid,
WILL_FIRE_v_from_masters_1_m_bready,
WILL_FIRE_v_from_masters_1_m_rready,
WILL_FIRE_v_from_masters_1_m_wvalid,
WILL_FIRE_v_to_slaves_0_m_arready,
WILL_FIRE_v_to_slaves_0_m_awready,
WILL_FIRE_v_to_slaves_0_m_bvalid,
WILL_FIRE_v_to_slaves_0_m_rvalid,
WILL_FIRE_v_to_slaves_0_m_wready,
WILL_FIRE_v_to_slaves_1_m_arready,
WILL_FIRE_v_to_slaves_1_m_awready,
WILL_FIRE_v_to_slaves_1_m_bvalid,
WILL_FIRE_v_to_slaves_1_m_rvalid,
WILL_FIRE_v_to_slaves_1_m_wready,
WILL_FIRE_v_to_slaves_2_m_arready,
WILL_FIRE_v_to_slaves_2_m_awready,
WILL_FIRE_v_to_slaves_2_m_bvalid,
WILL_FIRE_v_to_slaves_2_m_rvalid,
WILL_FIRE_v_to_slaves_2_m_wready;
// inputs to muxes for submodule ports
wire [70 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1,
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2,
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3,
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4,
MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4;
wire [9 : 0] MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1,
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2,
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1,
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2,
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3,
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4,
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1,
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2,
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3,
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4;
wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2,
MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2,
MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2,
MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2,
MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2;
wire [5 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4,
MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4;
wire MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1,
MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1,
MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h8720;
reg [31 : 0] v__h9120;
reg [31 : 0] v__h9520;
reg [31 : 0] v__h9990;
reg [31 : 0] v__h10384;
reg [31 : 0] v__h10778;
reg [31 : 0] v__h11160;
reg [31 : 0] v__h11498;
reg [31 : 0] v__h11898;
reg [31 : 0] v__h12144;
reg [31 : 0] v__h12524;
reg [31 : 0] v__h12770;
reg [31 : 0] v__h13147;
reg [31 : 0] v__h13439;
reg [31 : 0] v__h13731;
reg [31 : 0] v__h14034;
reg [31 : 0] v__h14300;
reg [31 : 0] v__h14566;
reg [31 : 0] v__h14830;
reg [31 : 0] v__h15056;
reg [31 : 0] v__h15510;
reg [31 : 0] v__h15891;
reg [31 : 0] v__h16272;
reg [31 : 0] v__h16714;
reg [31 : 0] v__h17071;
reg [31 : 0] v__h17428;
reg [31 : 0] v__h17779;
reg [31 : 0] v__h18080;
reg [31 : 0] v__h18488;
reg [31 : 0] v__h18739;
reg [31 : 0] v__h19114;
reg [31 : 0] v__h19355;
reg [31 : 0] v__h19730;
reg [31 : 0] v__h19971;
reg [31 : 0] v__h20333;
reg [31 : 0] v__h20584;
reg [31 : 0] v__h20914;
reg [31 : 0] v__h21155;
reg [31 : 0] v__h21485;
reg [31 : 0] v__h21726;
reg [31 : 0] v__h22239;
reg [31 : 0] v__h22640;
reg [31 : 0] v__h5716;
reg [31 : 0] v__h5710;
reg [31 : 0] v__h8714;
reg [31 : 0] v__h9114;
reg [31 : 0] v__h9514;
reg [31 : 0] v__h9984;
reg [31 : 0] v__h10378;
reg [31 : 0] v__h10772;
reg [31 : 0] v__h11154;
reg [31 : 0] v__h11492;
reg [31 : 0] v__h11892;
reg [31 : 0] v__h12138;
reg [31 : 0] v__h12518;
reg [31 : 0] v__h12764;
reg [31 : 0] v__h13141;
reg [31 : 0] v__h13433;
reg [31 : 0] v__h13725;
reg [31 : 0] v__h14028;
reg [31 : 0] v__h14294;
reg [31 : 0] v__h14560;
reg [31 : 0] v__h14824;
reg [31 : 0] v__h15050;
reg [31 : 0] v__h15504;
reg [31 : 0] v__h15885;
reg [31 : 0] v__h16266;
reg [31 : 0] v__h16708;
reg [31 : 0] v__h17065;
reg [31 : 0] v__h17422;
reg [31 : 0] v__h17773;
reg [31 : 0] v__h18074;
reg [31 : 0] v__h18482;
reg [31 : 0] v__h18733;
reg [31 : 0] v__h19108;
reg [31 : 0] v__h19349;
reg [31 : 0] v__h19724;
reg [31 : 0] v__h19965;
reg [31 : 0] v__h20327;
reg [31 : 0] v__h20578;
reg [31 : 0] v__h20908;
reg [31 : 0] v__h21149;
reg [31 : 0] v__h21479;
reg [31 : 0] v__h21720;
reg [31 : 0] v__h22233;
reg [31 : 0] v__h22634;
// synopsys translate_on
// remaining internal signals
reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1,
CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2;
wire [7 : 0] x__h12049,
x__h12675,
x__h18625,
x__h19251,
x__h19867,
x__h22171,
x__h22572;
wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_ETC___d503,
IF_fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_ETC___d538,
IF_fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_ETC___d573,
IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d102,
IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d349,
IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d37,
IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d405,
x1_avValue_rresp__h18603,
x1_avValue_rresp__h19229,
x1_avValue_rresp__h19845;
wire NOT_soc_map_m_mem0_controller_addr_base__6_ULE_ETC___d148,
NOT_soc_map_m_mem0_controller_addr_base__6_ULE_ETC___d167,
NOT_soc_map_m_mem0_controller_addr_base__6_ULE_ETC___d448,
NOT_soc_map_m_mem0_controller_addr_base__6_ULE_ETC___d466,
_dor1fabric_v_f_rd_mis_0$EN_deq,
_dor1fabric_v_f_rd_mis_1$EN_deq,
_dor1fabric_v_f_rd_mis_2$EN_deq,
fabric_v_f_wd_tasks_0_i_notEmpty__73_AND_fabri_ETC___d182,
fabric_v_f_wd_tasks_1_i_notEmpty__05_AND_fabri_ETC___d211,
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d487,
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d522,
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d557,
fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d622,
fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d640,
fabric_v_rg_wd_beat_count_0_90_EQ_fabric_v_f_w_ETC___d198,
fabric_v_rg_wd_beat_count_1_19_EQ_fabric_v_f_w_ETC___d227,
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d337,
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d340,
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d343,
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d21,
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26,
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d31,
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d393,
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d396,
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d399,
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90,
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93,
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96,
soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d24,
soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d339,
soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d395,
soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d92,
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d19,
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d336,
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d34,
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d346,
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d392,
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d402,
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d89,
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d99,
soc_map_m_uart0_addr_base__8_ULE_fabric_xactor_ETC___d29,
soc_map_m_uart0_addr_base__8_ULE_fabric_xactor_ETC___d342,
soc_map_m_uart0_addr_base__8_ULE_fabric_xactor_ETC___d398,
soc_map_m_uart0_addr_base__8_ULE_fabric_xactor_ETC___d95;
// action method reset
assign RDY_reset = !fabric_rg_reset ;
assign CAN_FIRE_reset = !fabric_rg_reset ;
assign WILL_FIRE_reset = EN_reset ;
// action method set_verbosity
assign RDY_set_verbosity = 1'd1 ;
assign CAN_FIRE_set_verbosity = 1'd1 ;
assign WILL_FIRE_set_verbosity = EN_set_verbosity ;
// action method v_from_masters_0_m_awvalid
assign CAN_FIRE_v_from_masters_0_m_awvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_awvalid = 1'd1 ;
// value method v_from_masters_0_m_awready
assign v_from_masters_0_awready =
fabric_xactors_from_masters_0_f_wr_addr$FULL_N ;
// action method v_from_masters_0_m_wvalid
assign CAN_FIRE_v_from_masters_0_m_wvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_wvalid = 1'd1 ;
// value method v_from_masters_0_m_wready
assign v_from_masters_0_wready =
fabric_xactors_from_masters_0_f_wr_data$FULL_N ;
// value method v_from_masters_0_m_bvalid
assign v_from_masters_0_bvalid =
fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ;
// value method v_from_masters_0_m_bid
assign v_from_masters_0_bid =
fabric_xactors_from_masters_0_f_wr_resp$D_OUT[5:2] ;
// value method v_from_masters_0_m_bresp
assign v_from_masters_0_bresp =
fabric_xactors_from_masters_0_f_wr_resp$D_OUT[1:0] ;
// action method v_from_masters_0_m_bready
assign CAN_FIRE_v_from_masters_0_m_bready = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_bready = 1'd1 ;
// action method v_from_masters_0_m_arvalid
assign CAN_FIRE_v_from_masters_0_m_arvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_arvalid = 1'd1 ;
// value method v_from_masters_0_m_arready
assign v_from_masters_0_arready =
fabric_xactors_from_masters_0_f_rd_addr$FULL_N ;
// value method v_from_masters_0_m_rvalid
assign v_from_masters_0_rvalid =
fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ;
// value method v_from_masters_0_m_rid
assign v_from_masters_0_rid =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[70:67] ;
// value method v_from_masters_0_m_rdata
assign v_from_masters_0_rdata =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[66:3] ;
// value method v_from_masters_0_m_rresp
assign v_from_masters_0_rresp =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[2:1] ;
// value method v_from_masters_0_m_rlast
assign v_from_masters_0_rlast =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[0] ;
// action method v_from_masters_0_m_rready
assign CAN_FIRE_v_from_masters_0_m_rready = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_rready = 1'd1 ;
// action method v_from_masters_1_m_awvalid
assign CAN_FIRE_v_from_masters_1_m_awvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_1_m_awvalid = 1'd1 ;
// value method v_from_masters_1_m_awready
assign v_from_masters_1_awready =
fabric_xactors_from_masters_1_f_wr_addr$FULL_N ;
// action method v_from_masters_1_m_wvalid
assign CAN_FIRE_v_from_masters_1_m_wvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_1_m_wvalid = 1'd1 ;
// value method v_from_masters_1_m_wready
assign v_from_masters_1_wready =
fabric_xactors_from_masters_1_f_wr_data$FULL_N ;
// value method v_from_masters_1_m_bvalid
assign v_from_masters_1_bvalid =
fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ;
// value method v_from_masters_1_m_bid
assign v_from_masters_1_bid =
fabric_xactors_from_masters_1_f_wr_resp$D_OUT[5:2] ;
// value method v_from_masters_1_m_bresp
assign v_from_masters_1_bresp =
fabric_xactors_from_masters_1_f_wr_resp$D_OUT[1:0] ;
// action method v_from_masters_1_m_bready
assign CAN_FIRE_v_from_masters_1_m_bready = 1'd1 ;
assign WILL_FIRE_v_from_masters_1_m_bready = 1'd1 ;
// action method v_from_masters_1_m_arvalid
assign CAN_FIRE_v_from_masters_1_m_arvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_1_m_arvalid = 1'd1 ;
// value method v_from_masters_1_m_arready
assign v_from_masters_1_arready =
fabric_xactors_from_masters_1_f_rd_addr$FULL_N ;
// value method v_from_masters_1_m_rvalid
assign v_from_masters_1_rvalid =
fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ;
// value method v_from_masters_1_m_rid
assign v_from_masters_1_rid =
fabric_xactors_from_masters_1_f_rd_data$D_OUT[70:67] ;
// value method v_from_masters_1_m_rdata
assign v_from_masters_1_rdata =
fabric_xactors_from_masters_1_f_rd_data$D_OUT[66:3] ;
// value method v_from_masters_1_m_rresp
assign v_from_masters_1_rresp =
fabric_xactors_from_masters_1_f_rd_data$D_OUT[2:1] ;
// value method v_from_masters_1_m_rlast
assign v_from_masters_1_rlast =
fabric_xactors_from_masters_1_f_rd_data$D_OUT[0] ;
// action method v_from_masters_1_m_rready
assign CAN_FIRE_v_from_masters_1_m_rready = 1'd1 ;
assign WILL_FIRE_v_from_masters_1_m_rready = 1'd1 ;
// value method v_to_slaves_0_m_awvalid
assign v_to_slaves_0_awvalid =
fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N ;
// value method v_to_slaves_0_m_awid
assign v_to_slaves_0_awid =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[96:93] ;
// value method v_to_slaves_0_m_awaddr
assign v_to_slaves_0_awaddr =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[92:29] ;
// value method v_to_slaves_0_m_awlen
assign v_to_slaves_0_awlen =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[28:21] ;
// value method v_to_slaves_0_m_awsize
assign v_to_slaves_0_awsize =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[20:18] ;
// value method v_to_slaves_0_m_awburst
assign v_to_slaves_0_awburst =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[17:16] ;
// value method v_to_slaves_0_m_awlock
assign v_to_slaves_0_awlock =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[15] ;
// value method v_to_slaves_0_m_awcache
assign v_to_slaves_0_awcache =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[14:11] ;
// value method v_to_slaves_0_m_awprot
assign v_to_slaves_0_awprot =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[10:8] ;
// value method v_to_slaves_0_m_awqos
assign v_to_slaves_0_awqos =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[7:4] ;
// value method v_to_slaves_0_m_awregion
assign v_to_slaves_0_awregion =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[3:0] ;
// action method v_to_slaves_0_m_awready
assign CAN_FIRE_v_to_slaves_0_m_awready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_awready = 1'd1 ;
// value method v_to_slaves_0_m_wvalid
assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ;
// value method v_to_slaves_0_m_wdata
assign v_to_slaves_0_wdata =
fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ;
// value method v_to_slaves_0_m_wstrb
assign v_to_slaves_0_wstrb =
fabric_xactors_to_slaves_0_f_wr_data$D_OUT[8:1] ;
// value method v_to_slaves_0_m_wlast
assign v_to_slaves_0_wlast = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[0] ;
// action method v_to_slaves_0_m_wready
assign CAN_FIRE_v_to_slaves_0_m_wready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_wready = 1'd1 ;
// action method v_to_slaves_0_m_bvalid
assign CAN_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ;
// value method v_to_slaves_0_m_bready
assign v_to_slaves_0_bready = fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ;
// value method v_to_slaves_0_m_arvalid
assign v_to_slaves_0_arvalid =
fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N ;
// value method v_to_slaves_0_m_arid
assign v_to_slaves_0_arid =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[96:93] ;
// value method v_to_slaves_0_m_araddr
assign v_to_slaves_0_araddr =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[92:29] ;
// value method v_to_slaves_0_m_arlen
assign v_to_slaves_0_arlen =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[28:21] ;
// value method v_to_slaves_0_m_arsize
assign v_to_slaves_0_arsize =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[20:18] ;
// value method v_to_slaves_0_m_arburst
assign v_to_slaves_0_arburst =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[17:16] ;
// value method v_to_slaves_0_m_arlock
assign v_to_slaves_0_arlock =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[15] ;
// value method v_to_slaves_0_m_arcache
assign v_to_slaves_0_arcache =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[14:11] ;
// value method v_to_slaves_0_m_arprot
assign v_to_slaves_0_arprot =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[10:8] ;
// value method v_to_slaves_0_m_arqos
assign v_to_slaves_0_arqos =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[7:4] ;
// value method v_to_slaves_0_m_arregion
assign v_to_slaves_0_arregion =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[3:0] ;
// action method v_to_slaves_0_m_arready
assign CAN_FIRE_v_to_slaves_0_m_arready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_arready = 1'd1 ;
// action method v_to_slaves_0_m_rvalid
assign CAN_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ;
// value method v_to_slaves_0_m_rready
assign v_to_slaves_0_rready = fabric_xactors_to_slaves_0_f_rd_data$FULL_N ;
// value method v_to_slaves_1_m_awvalid
assign v_to_slaves_1_awvalid =
fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N ;
// value method v_to_slaves_1_m_awid
assign v_to_slaves_1_awid =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[96:93] ;
// value method v_to_slaves_1_m_awaddr
assign v_to_slaves_1_awaddr =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[92:29] ;
// value method v_to_slaves_1_m_awlen
assign v_to_slaves_1_awlen =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[28:21] ;
// value method v_to_slaves_1_m_awsize
assign v_to_slaves_1_awsize =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[20:18] ;
// value method v_to_slaves_1_m_awburst
assign v_to_slaves_1_awburst =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[17:16] ;
// value method v_to_slaves_1_m_awlock
assign v_to_slaves_1_awlock =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[15] ;
// value method v_to_slaves_1_m_awcache
assign v_to_slaves_1_awcache =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[14:11] ;
// value method v_to_slaves_1_m_awprot
assign v_to_slaves_1_awprot =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[10:8] ;
// value method v_to_slaves_1_m_awqos
assign v_to_slaves_1_awqos =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[7:4] ;
// value method v_to_slaves_1_m_awregion
assign v_to_slaves_1_awregion =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[3:0] ;
// action method v_to_slaves_1_m_awready
assign CAN_FIRE_v_to_slaves_1_m_awready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_awready = 1'd1 ;
// value method v_to_slaves_1_m_wvalid
assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ;
// value method v_to_slaves_1_m_wdata
assign v_to_slaves_1_wdata =
fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ;
// value method v_to_slaves_1_m_wstrb
assign v_to_slaves_1_wstrb =
fabric_xactors_to_slaves_1_f_wr_data$D_OUT[8:1] ;
// value method v_to_slaves_1_m_wlast
assign v_to_slaves_1_wlast = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[0] ;
// action method v_to_slaves_1_m_wready
assign CAN_FIRE_v_to_slaves_1_m_wready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_wready = 1'd1 ;
// action method v_to_slaves_1_m_bvalid
assign CAN_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ;
// value method v_to_slaves_1_m_bready
assign v_to_slaves_1_bready = fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ;
// value method v_to_slaves_1_m_arvalid
assign v_to_slaves_1_arvalid =
fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N ;
// value method v_to_slaves_1_m_arid
assign v_to_slaves_1_arid =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[96:93] ;
// value method v_to_slaves_1_m_araddr
assign v_to_slaves_1_araddr =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[92:29] ;
// value method v_to_slaves_1_m_arlen
assign v_to_slaves_1_arlen =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[28:21] ;
// value method v_to_slaves_1_m_arsize
assign v_to_slaves_1_arsize =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[20:18] ;
// value method v_to_slaves_1_m_arburst
assign v_to_slaves_1_arburst =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[17:16] ;
// value method v_to_slaves_1_m_arlock
assign v_to_slaves_1_arlock =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[15] ;
// value method v_to_slaves_1_m_arcache
assign v_to_slaves_1_arcache =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[14:11] ;
// value method v_to_slaves_1_m_arprot
assign v_to_slaves_1_arprot =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[10:8] ;
// value method v_to_slaves_1_m_arqos
assign v_to_slaves_1_arqos =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[7:4] ;
// value method v_to_slaves_1_m_arregion
assign v_to_slaves_1_arregion =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[3:0] ;
// action method v_to_slaves_1_m_arready
assign CAN_FIRE_v_to_slaves_1_m_arready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_arready = 1'd1 ;
// action method v_to_slaves_1_m_rvalid
assign CAN_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ;
// value method v_to_slaves_1_m_rready
assign v_to_slaves_1_rready = fabric_xactors_to_slaves_1_f_rd_data$FULL_N ;
// value method v_to_slaves_2_m_awvalid
assign v_to_slaves_2_awvalid =
fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N ;
// value method v_to_slaves_2_m_awid
assign v_to_slaves_2_awid =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[96:93] ;
// value method v_to_slaves_2_m_awaddr
assign v_to_slaves_2_awaddr =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[92:29] ;
// value method v_to_slaves_2_m_awlen
assign v_to_slaves_2_awlen =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[28:21] ;
// value method v_to_slaves_2_m_awsize
assign v_to_slaves_2_awsize =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[20:18] ;
// value method v_to_slaves_2_m_awburst
assign v_to_slaves_2_awburst =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[17:16] ;
// value method v_to_slaves_2_m_awlock
assign v_to_slaves_2_awlock =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[15] ;
// value method v_to_slaves_2_m_awcache
assign v_to_slaves_2_awcache =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[14:11] ;
// value method v_to_slaves_2_m_awprot
assign v_to_slaves_2_awprot =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[10:8] ;
// value method v_to_slaves_2_m_awqos
assign v_to_slaves_2_awqos =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[7:4] ;
// value method v_to_slaves_2_m_awregion
assign v_to_slaves_2_awregion =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[3:0] ;
// action method v_to_slaves_2_m_awready
assign CAN_FIRE_v_to_slaves_2_m_awready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_awready = 1'd1 ;
// value method v_to_slaves_2_m_wvalid
assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ;
// value method v_to_slaves_2_m_wdata
assign v_to_slaves_2_wdata =
fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ;
// value method v_to_slaves_2_m_wstrb
assign v_to_slaves_2_wstrb =
fabric_xactors_to_slaves_2_f_wr_data$D_OUT[8:1] ;
// value method v_to_slaves_2_m_wlast
assign v_to_slaves_2_wlast = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[0] ;
// action method v_to_slaves_2_m_wready
assign CAN_FIRE_v_to_slaves_2_m_wready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_wready = 1'd1 ;
// action method v_to_slaves_2_m_bvalid
assign CAN_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ;
// value method v_to_slaves_2_m_bready
assign v_to_slaves_2_bready = fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ;
// value method v_to_slaves_2_m_arvalid
assign v_to_slaves_2_arvalid =
fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N ;
// value method v_to_slaves_2_m_arid
assign v_to_slaves_2_arid =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[96:93] ;
// value method v_to_slaves_2_m_araddr
assign v_to_slaves_2_araddr =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[92:29] ;
// value method v_to_slaves_2_m_arlen
assign v_to_slaves_2_arlen =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[28:21] ;
// value method v_to_slaves_2_m_arsize
assign v_to_slaves_2_arsize =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[20:18] ;
// value method v_to_slaves_2_m_arburst
assign v_to_slaves_2_arburst =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[17:16] ;
// value method v_to_slaves_2_m_arlock
assign v_to_slaves_2_arlock =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[15] ;
// value method v_to_slaves_2_m_arcache
assign v_to_slaves_2_arcache =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[14:11] ;
// value method v_to_slaves_2_m_arprot
assign v_to_slaves_2_arprot =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[10:8] ;
// value method v_to_slaves_2_m_arqos
assign v_to_slaves_2_arqos =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[7:4] ;
// value method v_to_slaves_2_m_arregion
assign v_to_slaves_2_arregion =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[3:0] ;
// action method v_to_slaves_2_m_arready
assign CAN_FIRE_v_to_slaves_2_m_arready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_arready = 1'd1 ;
// action method v_to_slaves_2_m_rvalid
assign CAN_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ;
// value method v_to_slaves_2_m_rready
assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ;
// submodule fabric_v_f_rd_err_info_0
SizedFIFO #(.p1width(32'd12),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_err_info_0$D_IN),
.ENQ(fabric_v_f_rd_err_info_0$ENQ),
.DEQ(fabric_v_f_rd_err_info_0$DEQ),
.CLR(fabric_v_f_rd_err_info_0$CLR),
.D_OUT(fabric_v_f_rd_err_info_0$D_OUT),
.FULL_N(fabric_v_f_rd_err_info_0$FULL_N),
.EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N));
// submodule fabric_v_f_rd_err_info_1
SizedFIFO #(.p1width(32'd12),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_rd_err_info_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_err_info_1$D_IN),
.ENQ(fabric_v_f_rd_err_info_1$ENQ),
.DEQ(fabric_v_f_rd_err_info_1$DEQ),
.CLR(fabric_v_f_rd_err_info_1$CLR),
.D_OUT(fabric_v_f_rd_err_info_1$D_OUT),
.FULL_N(fabric_v_f_rd_err_info_1$FULL_N),
.EMPTY_N(fabric_v_f_rd_err_info_1$EMPTY_N));
// submodule fabric_v_f_rd_mis_0
SizedFIFO #(.p1width(32'd10),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_rd_mis_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_mis_0$D_IN),
.ENQ(fabric_v_f_rd_mis_0$ENQ),
.DEQ(fabric_v_f_rd_mis_0$DEQ),
.CLR(fabric_v_f_rd_mis_0$CLR),
.D_OUT(fabric_v_f_rd_mis_0$D_OUT),
.FULL_N(fabric_v_f_rd_mis_0$FULL_N),
.EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N));
// submodule fabric_v_f_rd_mis_1
SizedFIFO #(.p1width(32'd10),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_rd_mis_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_mis_1$D_IN),
.ENQ(fabric_v_f_rd_mis_1$ENQ),
.DEQ(fabric_v_f_rd_mis_1$DEQ),
.CLR(fabric_v_f_rd_mis_1$CLR),
.D_OUT(fabric_v_f_rd_mis_1$D_OUT),
.FULL_N(fabric_v_f_rd_mis_1$FULL_N),
.EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N));
// submodule fabric_v_f_rd_mis_2
SizedFIFO #(.p1width(32'd10),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_rd_mis_2(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_mis_2$D_IN),
.ENQ(fabric_v_f_rd_mis_2$ENQ),
.DEQ(fabric_v_f_rd_mis_2$DEQ),
.CLR(fabric_v_f_rd_mis_2$CLR),
.D_OUT(fabric_v_f_rd_mis_2$D_OUT),
.FULL_N(fabric_v_f_rd_mis_2$FULL_N),
.EMPTY_N(fabric_v_f_rd_mis_2$EMPTY_N));
// submodule fabric_v_f_rd_sjs_0
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_rd_sjs_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_sjs_0$D_IN),
.ENQ(fabric_v_f_rd_sjs_0$ENQ),
.DEQ(fabric_v_f_rd_sjs_0$DEQ),
.CLR(fabric_v_f_rd_sjs_0$CLR),
.D_OUT(fabric_v_f_rd_sjs_0$D_OUT),
.FULL_N(fabric_v_f_rd_sjs_0$FULL_N),
.EMPTY_N(fabric_v_f_rd_sjs_0$EMPTY_N));
// submodule fabric_v_f_rd_sjs_1
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_rd_sjs_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_sjs_1$D_IN),
.ENQ(fabric_v_f_rd_sjs_1$ENQ),
.DEQ(fabric_v_f_rd_sjs_1$DEQ),
.CLR(fabric_v_f_rd_sjs_1$CLR),
.D_OUT(fabric_v_f_rd_sjs_1$D_OUT),
.FULL_N(fabric_v_f_rd_sjs_1$FULL_N),
.EMPTY_N(fabric_v_f_rd_sjs_1$EMPTY_N));
// submodule fabric_v_f_wd_tasks_0
FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wd_tasks_0$D_IN),
.ENQ(fabric_v_f_wd_tasks_0$ENQ),
.DEQ(fabric_v_f_wd_tasks_0$DEQ),
.CLR(fabric_v_f_wd_tasks_0$CLR),
.D_OUT(fabric_v_f_wd_tasks_0$D_OUT),
.FULL_N(fabric_v_f_wd_tasks_0$FULL_N),
.EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N));
// submodule fabric_v_f_wd_tasks_1
FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wd_tasks_1$D_IN),
.ENQ(fabric_v_f_wd_tasks_1$ENQ),
.DEQ(fabric_v_f_wd_tasks_1$DEQ),
.CLR(fabric_v_f_wd_tasks_1$CLR),
.D_OUT(fabric_v_f_wd_tasks_1$D_OUT),
.FULL_N(fabric_v_f_wd_tasks_1$FULL_N),
.EMPTY_N(fabric_v_f_wd_tasks_1$EMPTY_N));
// submodule fabric_v_f_wr_err_info_0
SizedFIFO #(.p1width(32'd4),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_err_info_0$D_IN),
.ENQ(fabric_v_f_wr_err_info_0$ENQ),
.DEQ(fabric_v_f_wr_err_info_0$DEQ),
.CLR(fabric_v_f_wr_err_info_0$CLR),
.D_OUT(fabric_v_f_wr_err_info_0$D_OUT),
.FULL_N(fabric_v_f_wr_err_info_0$FULL_N),
.EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N));
// submodule fabric_v_f_wr_err_info_1
SizedFIFO #(.p1width(32'd4),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_wr_err_info_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_err_info_1$D_IN),
.ENQ(fabric_v_f_wr_err_info_1$ENQ),
.DEQ(fabric_v_f_wr_err_info_1$DEQ),
.CLR(fabric_v_f_wr_err_info_1$CLR),
.D_OUT(fabric_v_f_wr_err_info_1$D_OUT),
.FULL_N(fabric_v_f_wr_err_info_1$FULL_N),
.EMPTY_N(fabric_v_f_wr_err_info_1$EMPTY_N));
// submodule fabric_v_f_wr_mis_0
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_wr_mis_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_mis_0$D_IN),
.ENQ(fabric_v_f_wr_mis_0$ENQ),
.DEQ(fabric_v_f_wr_mis_0$DEQ),
.CLR(fabric_v_f_wr_mis_0$CLR),
.D_OUT(fabric_v_f_wr_mis_0$D_OUT),
.FULL_N(fabric_v_f_wr_mis_0$FULL_N),
.EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N));
// submodule fabric_v_f_wr_mis_1
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_wr_mis_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_mis_1$D_IN),
.ENQ(fabric_v_f_wr_mis_1$ENQ),
.DEQ(fabric_v_f_wr_mis_1$DEQ),
.CLR(fabric_v_f_wr_mis_1$CLR),
.D_OUT(fabric_v_f_wr_mis_1$D_OUT),
.FULL_N(fabric_v_f_wr_mis_1$FULL_N),
.EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N));
// submodule fabric_v_f_wr_mis_2
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_wr_mis_2(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_mis_2$D_IN),
.ENQ(fabric_v_f_wr_mis_2$ENQ),
.DEQ(fabric_v_f_wr_mis_2$DEQ),
.CLR(fabric_v_f_wr_mis_2$CLR),
.D_OUT(fabric_v_f_wr_mis_2$D_OUT),
.FULL_N(fabric_v_f_wr_mis_2$FULL_N),
.EMPTY_N(fabric_v_f_wr_mis_2$EMPTY_N));
// submodule fabric_v_f_wr_sjs_0
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_wr_sjs_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_sjs_0$D_IN),
.ENQ(fabric_v_f_wr_sjs_0$ENQ),
.DEQ(fabric_v_f_wr_sjs_0$DEQ),
.CLR(fabric_v_f_wr_sjs_0$CLR),
.D_OUT(fabric_v_f_wr_sjs_0$D_OUT),
.FULL_N(fabric_v_f_wr_sjs_0$FULL_N),
.EMPTY_N(fabric_v_f_wr_sjs_0$EMPTY_N));
// submodule fabric_v_f_wr_sjs_1
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_wr_sjs_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_sjs_1$D_IN),
.ENQ(fabric_v_f_wr_sjs_1$ENQ),
.DEQ(fabric_v_f_wr_sjs_1$DEQ),
.CLR(fabric_v_f_wr_sjs_1$CLR),
.D_OUT(fabric_v_f_wr_sjs_1$D_OUT),
.FULL_N(fabric_v_f_wr_sjs_1$FULL_N),
.EMPTY_N(fabric_v_f_wr_sjs_1$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_rd_addr$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_rd_addr$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_rd_addr$DEQ),
.CLR(fabric_xactors_from_masters_0_f_rd_addr$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_rd_data$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_rd_data$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_rd_data$DEQ),
.CLR(fabric_xactors_from_masters_0_f_rd_data$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_rd_data$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_wr_addr$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_wr_addr$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_wr_addr$DEQ),
.CLR(fabric_xactors_from_masters_0_f_wr_addr$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_wr_data$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_wr_data$DEQ),
.CLR(fabric_xactors_from_masters_0_f_wr_data$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_wr_data$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_wr_resp
FIFO2 #(.width(32'd6),
.guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_wr_resp$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_wr_resp$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_wr_resp$DEQ),
.CLR(fabric_xactors_from_masters_0_f_wr_resp$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_from_masters_1_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_1_f_rd_addr$D_IN),
.ENQ(fabric_xactors_from_masters_1_f_rd_addr$ENQ),
.DEQ(fabric_xactors_from_masters_1_f_rd_addr$DEQ),
.CLR(fabric_xactors_from_masters_1_f_rd_addr$CLR),
.D_OUT(fabric_xactors_from_masters_1_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_from_masters_1_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_from_masters_1_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(32'd1)) fabric_xactors_from_masters_1_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_1_f_rd_data$D_IN),
.ENQ(fabric_xactors_from_masters_1_f_rd_data$ENQ),
.DEQ(fabric_xactors_from_masters_1_f_rd_data$DEQ),
.CLR(fabric_xactors_from_masters_1_f_rd_data$CLR),
.D_OUT(fabric_xactors_from_masters_1_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_from_masters_1_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_1_f_rd_data$EMPTY_N));
// submodule fabric_xactors_from_masters_1_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_1_f_wr_addr$D_IN),
.ENQ(fabric_xactors_from_masters_1_f_wr_addr$ENQ),
.DEQ(fabric_xactors_from_masters_1_f_wr_addr$DEQ),
.CLR(fabric_xactors_from_masters_1_f_wr_addr$CLR),
.D_OUT(fabric_xactors_from_masters_1_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_from_masters_1_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_from_masters_1_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_1_f_wr_data$D_IN),
.ENQ(fabric_xactors_from_masters_1_f_wr_data$ENQ),
.DEQ(fabric_xactors_from_masters_1_f_wr_data$DEQ),
.CLR(fabric_xactors_from_masters_1_f_wr_data$CLR),
.D_OUT(fabric_xactors_from_masters_1_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_from_masters_1_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_1_f_wr_data$EMPTY_N));
// submodule fabric_xactors_from_masters_1_f_wr_resp
FIFO2 #(.width(32'd6),
.guarded(32'd1)) fabric_xactors_from_masters_1_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_1_f_wr_resp$D_IN),
.ENQ(fabric_xactors_from_masters_1_f_wr_resp$ENQ),
.DEQ(fabric_xactors_from_masters_1_f_wr_resp$DEQ),
.CLR(fabric_xactors_from_masters_1_f_wr_resp$CLR),
.D_OUT(fabric_xactors_from_masters_1_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_from_masters_1_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_rd_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_rd_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_rd_addr$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_rd_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_rd_data$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_rd_data$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_rd_data$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_rd_data$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_wr_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_wr_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_wr_addr$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_wr_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_wr_data$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_wr_data$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_wr_data$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_wr_resp
FIFO2 #(.width(32'd6),
.guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_wr_resp$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_wr_resp$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_wr_resp$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_wr_resp$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_rd_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_rd_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_rd_addr$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_rd_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_rd_data$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_rd_data$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_rd_data$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_rd_data$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_wr_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_wr_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_wr_addr$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_wr_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_wr_data$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_wr_data$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_wr_data$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_wr_resp
FIFO2 #(.width(32'd6),
.guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_wr_resp$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_wr_resp$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_wr_resp$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_wr_resp$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_rd_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_rd_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_rd_addr$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_rd_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_rd_data$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_rd_data$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_rd_data$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_rd_data$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_wr_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_wr_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_wr_addr$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_wr_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_wr_data$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_wr_data$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_wr_data$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_wr_resp
FIFO2 #(.width(32'd6),
.guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_wr_resp$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_wr_resp$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_wr_resp$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_wr_resp$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N));
// submodule soc_map
mkSoC_Map soc_map(.CLK(CLK),
.RST_N(RST_N),
.m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
.m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
.m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
.m_near_mem_io_addr_base(),
.m_near_mem_io_addr_size(),
.m_near_mem_io_addr_lim(),
.m_plic_addr_base(),
.m_plic_addr_size(),
.m_plic_addr_lim(),
.m_uart0_addr_base(soc_map$m_uart0_addr_base),
.m_uart0_addr_size(),
.m_uart0_addr_lim(soc_map$m_uart0_addr_lim),
.m_boot_rom_addr_base(soc_map$m_boot_rom_addr_base),
.m_boot_rom_addr_size(),
.m_boot_rom_addr_lim(soc_map$m_boot_rom_addr_lim),
.m_mem0_controller_addr_base(soc_map$m_mem0_controller_addr_base),
.m_mem0_controller_addr_size(),
.m_mem0_controller_addr_lim(soc_map$m_mem0_controller_addr_lim),
.m_tcm_addr_base(),
.m_tcm_addr_size(),
.m_tcm_addr_lim(),
.m_is_mem_addr(),
.m_is_IO_addr(),
.m_is_near_mem_IO_addr(),
.m_pc_reset_value(),
.m_mtvec_reset_value(),
.m_nmivec_reset_value());
// rule RL_fabric_rl_wr_xaction_master_to_slave
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave =
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N &&
fabric_xactors_to_slaves_0_f_wr_addr$FULL_N &&
fabric_v_f_wd_tasks_0$FULL_N &&
fabric_v_f_wr_mis_0$FULL_N &&
fabric_v_f_wr_sjs_0$FULL_N &&
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d34 &&
IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d37 ==
2'd0 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_1
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 =
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_0$FULL_N &&
fabric_v_f_wr_sjs_0$FULL_N &&
fabric_xactors_to_slaves_1_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_1$FULL_N &&
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d34 &&
IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d37 ==
2'd1 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_2
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 =
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_0$FULL_N &&
fabric_v_f_wr_sjs_0$FULL_N &&
fabric_xactors_to_slaves_2_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_2$FULL_N &&
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d34 &&
IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d37 ==
2'd2 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_3
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 =
fabric_xactors_to_slaves_0_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_0$FULL_N &&
fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_1$FULL_N &&
fabric_v_f_wr_sjs_1$FULL_N &&
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d99 &&
IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d102 ==
2'd0 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
!WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_4
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 =
fabric_xactors_to_slaves_1_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_1$FULL_N &&
fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_1$FULL_N &&
fabric_v_f_wr_sjs_1$FULL_N &&
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d99 &&
IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d102 ==
2'd1 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
!WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_5
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 =
fabric_xactors_to_slaves_2_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_2$FULL_N &&
fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_1$FULL_N &&
fabric_v_f_wr_sjs_1$FULL_N &&
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d99 &&
IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d102 ==
2'd2 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
!WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
// rule RL_fabric_rl_wr_xaction_no_such_slave
assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave =
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_0$FULL_N &&
fabric_v_f_wr_sjs_0$FULL_N &&
fabric_v_f_wr_err_info_0$FULL_N &&
NOT_soc_map_m_mem0_controller_addr_base__6_ULE_ETC___d148 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave =
CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ;
// rule RL_fabric_rl_wr_xaction_no_such_slave_1
assign CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 =
fabric_xactors_from_masters_1_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_1$FULL_N &&
fabric_v_f_wr_sjs_1$FULL_N &&
fabric_v_f_wr_err_info_1$FULL_N &&
NOT_soc_map_m_mem0_controller_addr_base__6_ULE_ETC___d167 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 =
CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_data
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data =
fabric_xactors_from_masters_0_f_wr_data$EMPTY_N &&
fabric_v_f_wd_tasks_0_i_notEmpty__73_AND_fabri_ETC___d182 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_data_1
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 =
fabric_xactors_from_masters_1_f_wr_data$EMPTY_N &&
fabric_v_f_wd_tasks_1_i_notEmpty__05_AND_fabri_ETC___d211 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
!WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ;
// rule RL_fabric_rl_wr_resp_slave_to_master
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master =
fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_0$D_OUT == 2'd0 &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
// rule RL_fabric_rl_wr_resp_slave_to_master_1
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 =
fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_1$EMPTY_N &&
fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N &&
fabric_v_f_wr_mis_1$D_OUT == 2'd0 &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ;
// rule RL_fabric_rl_wr_resp_slave_to_master_2
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 =
fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_2$EMPTY_N &&
fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N &&
fabric_v_f_wr_mis_2$D_OUT == 2'd0 &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ;
// rule RL_fabric_rl_wr_resp_slave_to_master_3
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 =
fabric_v_f_wr_mis_0$EMPTY_N &&
fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N &&
fabric_v_f_wr_sjs_1$EMPTY_N &&
fabric_xactors_from_masters_1_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_0$D_OUT == 2'd1 &&
fabric_v_f_wr_sjs_1$D_OUT == 2'd0 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ;
// rule RL_fabric_rl_wr_resp_slave_to_master_4
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 =
fabric_v_f_wr_mis_1$EMPTY_N &&
fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N &&
fabric_v_f_wr_sjs_1$EMPTY_N &&
fabric_xactors_from_masters_1_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_1$D_OUT == 2'd1 &&
fabric_v_f_wr_sjs_1$D_OUT == 2'd1 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ;
// rule RL_fabric_rl_wr_resp_slave_to_master_5
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 =
fabric_v_f_wr_mis_2$EMPTY_N &&
fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N &&
fabric_v_f_wr_sjs_1$EMPTY_N &&
fabric_xactors_from_masters_1_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_2$D_OUT == 2'd1 &&
fabric_v_f_wr_sjs_1$D_OUT == 2'd2 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ;
// rule RL_fabric_rl_wr_resp_err_to_master
assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master =
fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
fabric_v_f_wr_err_info_0$EMPTY_N &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master =
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ;
// rule RL_fabric_rl_wr_resp_err_to_master_1
assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 =
fabric_v_f_wr_sjs_1$EMPTY_N &&
fabric_xactors_from_masters_1_f_wr_resp$FULL_N &&
fabric_v_f_wr_err_info_1$EMPTY_N &&
fabric_v_f_wr_sjs_1$D_OUT == 2'd3 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 =
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ;
// rule RL_fabric_rl_rd_xaction_master_to_slave
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave =
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N &&
fabric_xactors_to_slaves_0_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_0$FULL_N &&
fabric_v_f_rd_sjs_0$FULL_N &&
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d346 &&
IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d349 ==
2'd0 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_1
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 =
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_0$FULL_N &&
fabric_xactors_to_slaves_1_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_1$FULL_N &&
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d346 &&
IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d349 ==
2'd1 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_2
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 =
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_0$FULL_N &&
fabric_xactors_to_slaves_2_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_2$FULL_N &&
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d346 &&
IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d349 ==
2'd2 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_3
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 =
fabric_xactors_to_slaves_0_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_0$FULL_N &&
fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_1$FULL_N &&
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d402 &&
IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d405 ==
2'd0 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
!WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_4
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 =
fabric_xactors_to_slaves_1_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_1$FULL_N &&
fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_1$FULL_N &&
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d402 &&
IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d405 ==
2'd1 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
!WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_5
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 =
fabric_xactors_to_slaves_2_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_2$FULL_N &&
fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_1$FULL_N &&
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d402 &&
IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d405 ==
2'd2 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
!WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ;
// rule RL_fabric_rl_rd_xaction_no_such_slave
assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave =
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_0$FULL_N &&
fabric_v_f_rd_err_info_0$FULL_N &&
NOT_soc_map_m_mem0_controller_addr_base__6_ULE_ETC___d448 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave =
CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ;
// rule RL_fabric_rl_rd_xaction_no_such_slave_1
assign CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 =
fabric_xactors_from_masters_1_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_1$FULL_N &&
fabric_v_f_rd_err_info_1$FULL_N &&
NOT_soc_map_m_mem0_controller_addr_base__6_ULE_ETC___d466 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 =
CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ;
// rule RL_fabric_rl_rd_resp_slave_to_master
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master =
fabric_v_f_rd_mis_0$EMPTY_N &&
fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N &&
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
fabric_v_f_rd_sjs_0$EMPTY_N &&
fabric_v_f_rd_mis_0$D_OUT[9:8] == 2'd0 &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ;
// rule RL_fabric_rl_rd_resp_slave_to_master_1
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 =
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
fabric_v_f_rd_mis_1$EMPTY_N &&
fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N &&
fabric_v_f_rd_sjs_0$EMPTY_N &&
fabric_v_f_rd_mis_1$D_OUT[9:8] == 2'd0 &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ;
// rule RL_fabric_rl_rd_resp_slave_to_master_2
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 =
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
fabric_v_f_rd_mis_2$EMPTY_N &&
fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N &&
fabric_v_f_rd_sjs_0$EMPTY_N &&
fabric_v_f_rd_mis_2$D_OUT[9:8] == 2'd0 &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ;
// rule RL_fabric_rl_rd_resp_slave_to_master_3
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 =
fabric_v_f_rd_mis_0$EMPTY_N &&
fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N &&
fabric_xactors_from_masters_1_f_rd_data$FULL_N &&
fabric_v_f_rd_sjs_1$EMPTY_N &&
fabric_v_f_rd_mis_0$D_OUT[9:8] == 2'd1 &&
fabric_v_f_rd_sjs_1$D_OUT == 2'd0 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ;
// rule RL_fabric_rl_rd_resp_slave_to_master_4
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 =
fabric_v_f_rd_mis_1$EMPTY_N &&
fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N &&
fabric_xactors_from_masters_1_f_rd_data$FULL_N &&
fabric_v_f_rd_sjs_1$EMPTY_N &&
fabric_v_f_rd_mis_1$D_OUT[9:8] == 2'd1 &&
fabric_v_f_rd_sjs_1$D_OUT == 2'd1 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ;
// rule RL_fabric_rl_rd_resp_slave_to_master_5
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 =
fabric_v_f_rd_mis_2$EMPTY_N &&
fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N &&
fabric_xactors_from_masters_1_f_rd_data$FULL_N &&
fabric_v_f_rd_sjs_1$EMPTY_N &&
fabric_v_f_rd_mis_2$D_OUT[9:8] == 2'd1 &&
fabric_v_f_rd_sjs_1$D_OUT == 2'd2 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ;
// rule RL_fabric_rl_rd_resp_err_to_master
assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master =
fabric_v_f_rd_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
fabric_v_f_rd_err_info_0$EMPTY_N &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master =
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ;
// rule RL_fabric_rl_rd_resp_err_to_master_1
assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 =
fabric_v_f_rd_sjs_1$EMPTY_N &&
fabric_xactors_from_masters_1_f_rd_data$FULL_N &&
fabric_v_f_rd_err_info_1$EMPTY_N &&
fabric_v_f_rd_sjs_1$D_OUT == 2'd3 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 =
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ;
// rule RL_fabric_rl_reset
assign CAN_FIRE_RL_fabric_rl_reset = fabric_rg_reset ;
assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ;
// inputs to muxes for submodule ports
assign MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ;
assign MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ;
assign MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ;
assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 =
{ 2'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 =
{ 2'd1, fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 =
{ 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 =
{ 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 =
{ 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4 =
{ 2'd3, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 =
{ 2'd0, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 =
{ 2'd1, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 =
{ 2'd2, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4 =
{ 2'd3, fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 =
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d487 ?
8'd0 :
x__h18625 ;
assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 =
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d522 ?
8'd0 :
x__h19251 ;
assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 =
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d557 ?
8'd0 :
x__h19867 ;
assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 =
fabric_v_rg_wd_beat_count_0_90_EQ_fabric_v_f_w_ETC___d198 ?
8'd0 :
x__h12049 ;
assign MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 =
fabric_v_rg_wd_beat_count_1_19_EQ_fabric_v_f_w_ETC___d227 ?
8'd0 :
x__h12675 ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 =
{ fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:3],
IF_fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_ETC___d503,
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 =
{ fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:3],
IF_fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_ETC___d538,
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 =
{ fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:3],
IF_fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_ETC___d573,
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 =
{ fabric_v_f_rd_err_info_0$D_OUT[3:0],
66'd3,
fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d622 } ;
assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 =
{ fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ;
assign MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4 =
{ fabric_v_f_rd_err_info_1$D_OUT[3:0],
66'd3,
fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d640 } ;
assign MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4 =
{ fabric_v_f_wr_err_info_1$D_OUT, 2'd3 } ;
// register fabric_cfg_verbosity
assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ;
assign fabric_cfg_verbosity$EN = EN_set_verbosity ;
// register fabric_rg_reset
assign fabric_rg_reset$D_IN = !fabric_rg_reset ;
assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ;
// register fabric_v_rg_r_beat_count_0
always@(fabric_rg_reset or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or
MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master)
case (1'b1)
fabric_rg_reset: fabric_v_rg_r_beat_count_0$D_IN = 8'd0;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3:
fabric_v_rg_r_beat_count_0$D_IN =
MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master:
fabric_v_rg_r_beat_count_0$D_IN =
MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2;
default: fabric_v_rg_r_beat_count_0$D_IN =
8'b10101010 /* unspecified value */ ;
endcase
assign fabric_v_rg_r_beat_count_0$EN =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ||
fabric_rg_reset ;
// register fabric_v_rg_r_beat_count_1
always@(fabric_rg_reset or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or
MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1)
case (1'b1)
fabric_rg_reset: fabric_v_rg_r_beat_count_1$D_IN = 8'd0;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4:
fabric_v_rg_r_beat_count_1$D_IN =
MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1:
fabric_v_rg_r_beat_count_1$D_IN =
MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2;
default: fabric_v_rg_r_beat_count_1$D_IN =
8'b10101010 /* unspecified value */ ;
endcase
assign fabric_v_rg_r_beat_count_1$EN =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ||
fabric_rg_reset ;
// register fabric_v_rg_r_beat_count_2
always@(fabric_rg_reset or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or
MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2)
case (1'b1)
fabric_rg_reset: fabric_v_rg_r_beat_count_2$D_IN = 8'd0;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5:
fabric_v_rg_r_beat_count_2$D_IN =
MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2:
fabric_v_rg_r_beat_count_2$D_IN =
MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2;
default: fabric_v_rg_r_beat_count_2$D_IN =
8'b10101010 /* unspecified value */ ;
endcase
assign fabric_v_rg_r_beat_count_2$EN =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ||
fabric_rg_reset ;
// register fabric_v_rg_r_err_beat_count_0
assign fabric_v_rg_r_err_beat_count_0$D_IN =
fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d622 ?
8'd0 :
x__h22171 ;
assign fabric_v_rg_r_err_beat_count_0$EN =
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ;
// register fabric_v_rg_r_err_beat_count_1
assign fabric_v_rg_r_err_beat_count_1$D_IN =
fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d640 ?
8'd0 :
x__h22572 ;
assign fabric_v_rg_r_err_beat_count_1$EN =
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ;
// register fabric_v_rg_wd_beat_count_0
assign fabric_v_rg_wd_beat_count_0$D_IN =
fabric_rg_reset ?
8'd0 :
MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ;
assign fabric_v_rg_wd_beat_count_0$EN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ||
fabric_rg_reset ;
// register fabric_v_rg_wd_beat_count_1
assign fabric_v_rg_wd_beat_count_1$D_IN =
fabric_rg_reset ?
8'd0 :
MUX_fabric_v_rg_wd_beat_count_1$write_1__VAL_2 ;
assign fabric_v_rg_wd_beat_count_1$EN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 ||
fabric_rg_reset ;
// submodule fabric_v_f_rd_err_info_0
assign fabric_v_f_rd_err_info_0$D_IN =
{ fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21],
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93] } ;
assign fabric_v_f_rd_err_info_0$ENQ =
CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ;
assign fabric_v_f_rd_err_info_0$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d622 ;
assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_err_info_1
assign fabric_v_f_rd_err_info_1$D_IN =
{ fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21],
fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93] } ;
assign fabric_v_f_rd_err_info_1$ENQ =
CAN_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ;
assign fabric_v_f_rd_err_info_1$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d640 ;
assign fabric_v_f_rd_err_info_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_mis_0
assign fabric_v_f_rd_mis_0$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ?
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 :
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ;
assign fabric_v_f_rd_mis_0$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ;
assign fabric_v_f_rd_mis_0$DEQ =
_dor1fabric_v_f_rd_mis_0$EN_deq &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d487 ;
assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_mis_1
assign fabric_v_f_rd_mis_1$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ?
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 :
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ;
assign fabric_v_f_rd_mis_1$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ;
assign fabric_v_f_rd_mis_1$DEQ =
_dor1fabric_v_f_rd_mis_1$EN_deq &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d522 ;
assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_mis_2
assign fabric_v_f_rd_mis_2$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ?
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_1 :
MUX_fabric_v_f_rd_mis_0$enq_1__VAL_2 ;
assign fabric_v_f_rd_mis_2$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ;
assign fabric_v_f_rd_mis_2$DEQ =
_dor1fabric_v_f_rd_mis_2$EN_deq &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d557 ;
assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_sjs_0
always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave or
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 or
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 or
WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave:
fabric_v_f_rd_sjs_0$D_IN = 2'd0;
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1:
fabric_v_f_rd_sjs_0$D_IN = 2'd1;
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2:
fabric_v_f_rd_sjs_0$D_IN = 2'd2;
WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave:
fabric_v_f_rd_sjs_0$D_IN = 2'd3;
default: fabric_v_f_rd_sjs_0$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign fabric_v_f_rd_sjs_0$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ;
assign fabric_v_f_rd_sjs_0$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d487 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d522 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d557 ||
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d622 ;
assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_sjs_1
always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 or
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 or
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 or
WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3:
fabric_v_f_rd_sjs_1$D_IN = 2'd0;
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4:
fabric_v_f_rd_sjs_1$D_IN = 2'd1;
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5:
fabric_v_f_rd_sjs_1$D_IN = 2'd2;
WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1:
fabric_v_f_rd_sjs_1$D_IN = 2'd3;
default: fabric_v_f_rd_sjs_1$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign fabric_v_f_rd_sjs_1$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ;
assign fabric_v_f_rd_sjs_1$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d487 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d522 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d557 ||
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d640 ;
assign fabric_v_f_rd_sjs_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wd_tasks_0
always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 or
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave or
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave:
fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1:
fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2:
fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3;
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave:
fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_4;
default: fabric_v_f_wd_tasks_0$D_IN =
10'b1010101010 /* unspecified value */ ;
endcase
end
assign fabric_v_f_wd_tasks_0$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ;
assign fabric_v_f_wd_tasks_0$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_90_EQ_fabric_v_f_w_ETC___d198 ;
assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wd_tasks_1
always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3 or
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 or
MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3:
fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_1;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4:
fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_2;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5:
fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_3;
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1:
fabric_v_f_wd_tasks_1$D_IN = MUX_fabric_v_f_wd_tasks_1$enq_1__VAL_4;
default: fabric_v_f_wd_tasks_1$D_IN =
10'b1010101010 /* unspecified value */ ;
endcase
end
assign fabric_v_f_wd_tasks_1$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ;
assign fabric_v_f_wd_tasks_1$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_19_EQ_fabric_v_f_w_ETC___d227 ;
assign fabric_v_f_wd_tasks_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_err_info_0
assign fabric_v_f_wr_err_info_0$D_IN =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93] ;
assign fabric_v_f_wr_err_info_0$ENQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ;
assign fabric_v_f_wr_err_info_0$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ;
assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_err_info_1
assign fabric_v_f_wr_err_info_1$D_IN =
fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93] ;
assign fabric_v_f_wr_err_info_1$ENQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ;
assign fabric_v_f_wr_err_info_1$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ;
assign fabric_v_f_wr_err_info_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_mis_0
assign fabric_v_f_wr_mis_0$D_IN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ? 2'd0 : 2'd1 ;
assign fabric_v_f_wr_mis_0$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ;
assign fabric_v_f_wr_mis_0$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
assign fabric_v_f_wr_mis_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_mis_1
assign fabric_v_f_wr_mis_1$D_IN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ?
2'd0 :
2'd1 ;
assign fabric_v_f_wr_mis_1$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ;
assign fabric_v_f_wr_mis_1$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ;
assign fabric_v_f_wr_mis_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_mis_2
assign fabric_v_f_wr_mis_2$D_IN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ?
2'd0 :
2'd1 ;
assign fabric_v_f_wr_mis_2$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ;
assign fabric_v_f_wr_mis_2$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ;
assign fabric_v_f_wr_mis_2$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_sjs_0
always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave:
fabric_v_f_wr_sjs_0$D_IN = 2'd0;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1:
fabric_v_f_wr_sjs_0$D_IN = 2'd1;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2:
fabric_v_f_wr_sjs_0$D_IN = 2'd2;
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave:
fabric_v_f_wr_sjs_0$D_IN = 2'd3;
default: fabric_v_f_wr_sjs_0$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign fabric_v_f_wr_sjs_0$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ;
assign fabric_v_f_wr_sjs_0$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
assign fabric_v_f_wr_sjs_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_sjs_1
always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 or
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3:
fabric_v_f_wr_sjs_1$D_IN = 2'd0;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4:
fabric_v_f_wr_sjs_1$D_IN = 2'd1;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5:
fabric_v_f_wr_sjs_1$D_IN = 2'd2;
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1:
fabric_v_f_wr_sjs_1$D_IN = 2'd3;
default: fabric_v_f_wr_sjs_1$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign fabric_v_f_wr_sjs_1$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ;
assign fabric_v_f_wr_sjs_1$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ;
assign fabric_v_f_wr_sjs_1$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_rd_addr
assign fabric_xactors_from_masters_0_f_rd_addr$D_IN =
{ v_from_masters_0_arid,
v_from_masters_0_araddr,
v_from_masters_0_arlen,
v_from_masters_0_arsize,
v_from_masters_0_arburst,
v_from_masters_0_arlock,
v_from_masters_0_arcache,
v_from_masters_0_arprot,
v_from_masters_0_arqos,
v_from_masters_0_arregion } ;
assign fabric_xactors_from_masters_0_f_rd_addr$ENQ =
v_from_masters_0_arvalid &&
fabric_xactors_from_masters_0_f_rd_addr$FULL_N ;
assign fabric_xactors_from_masters_0_f_rd_addr$DEQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ;
assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_rd_data
always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3;
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4;
default: fabric_xactors_from_masters_0_f_rd_data$D_IN =
71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign fabric_xactors_from_masters_0_f_rd_data$ENQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ||
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ;
assign fabric_xactors_from_masters_0_f_rd_data$DEQ =
v_from_masters_0_rready &&
fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ;
assign fabric_xactors_from_masters_0_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_wr_addr
assign fabric_xactors_from_masters_0_f_wr_addr$D_IN =
{ v_from_masters_0_awid,
v_from_masters_0_awaddr,
v_from_masters_0_awlen,
v_from_masters_0_awsize,
v_from_masters_0_awburst,
v_from_masters_0_awlock,
v_from_masters_0_awcache,
v_from_masters_0_awprot,
v_from_masters_0_awqos,
v_from_masters_0_awregion } ;
assign fabric_xactors_from_masters_0_f_wr_addr$ENQ =
v_from_masters_0_awvalid &&
fabric_xactors_from_masters_0_f_wr_addr$FULL_N ;
assign fabric_xactors_from_masters_0_f_wr_addr$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
assign fabric_xactors_from_masters_0_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_wr_data
assign fabric_xactors_from_masters_0_f_wr_data$D_IN =
{ v_from_masters_0_wdata,
v_from_masters_0_wstrb,
v_from_masters_0_wlast } ;
assign fabric_xactors_from_masters_0_f_wr_data$ENQ =
v_from_masters_0_wvalid &&
fabric_xactors_from_masters_0_f_wr_data$FULL_N ;
assign fabric_xactors_from_masters_0_f_wr_data$DEQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ;
assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_wr_resp
always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 or
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master or
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 or
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master or
MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4;
default: fabric_xactors_from_masters_0_f_wr_resp$D_IN =
6'b101010 /* unspecified value */ ;
endcase
end
assign fabric_xactors_from_masters_0_f_wr_resp$ENQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ||
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ;
assign fabric_xactors_from_masters_0_f_wr_resp$DEQ =
v_from_masters_0_bready &&
fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ;
assign fabric_xactors_from_masters_0_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_1_f_rd_addr
assign fabric_xactors_from_masters_1_f_rd_addr$D_IN =
{ v_from_masters_1_arid,
v_from_masters_1_araddr,
v_from_masters_1_arlen,
v_from_masters_1_arsize,
v_from_masters_1_arburst,
v_from_masters_1_arlock,
v_from_masters_1_arcache,
v_from_masters_1_arprot,
v_from_masters_1_arqos,
v_from_masters_1_arregion } ;
assign fabric_xactors_from_masters_1_f_rd_addr$ENQ =
v_from_masters_1_arvalid &&
fabric_xactors_from_masters_1_f_rd_addr$FULL_N ;
assign fabric_xactors_from_masters_1_f_rd_addr$DEQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ;
assign fabric_xactors_from_masters_1_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_1_f_rd_data
always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 or
MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3:
fabric_xactors_from_masters_1_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4:
fabric_xactors_from_masters_1_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5:
fabric_xactors_from_masters_1_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3;
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1:
fabric_xactors_from_masters_1_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_1_f_rd_data$enq_1__VAL_4;
default: fabric_xactors_from_masters_1_f_rd_data$D_IN =
71'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign fabric_xactors_from_masters_1_f_rd_data$ENQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 ;
assign fabric_xactors_from_masters_1_f_rd_data$DEQ =
v_from_masters_1_rready &&
fabric_xactors_from_masters_1_f_rd_data$EMPTY_N ;
assign fabric_xactors_from_masters_1_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_1_f_wr_addr
assign fabric_xactors_from_masters_1_f_wr_addr$D_IN =
{ v_from_masters_1_awid,
v_from_masters_1_awaddr,
v_from_masters_1_awlen,
v_from_masters_1_awsize,
v_from_masters_1_awburst,
v_from_masters_1_awlock,
v_from_masters_1_awcache,
v_from_masters_1_awprot,
v_from_masters_1_awqos,
v_from_masters_1_awregion } ;
assign fabric_xactors_from_masters_1_f_wr_addr$ENQ =
v_from_masters_1_awvalid &&
fabric_xactors_from_masters_1_f_wr_addr$FULL_N ;
assign fabric_xactors_from_masters_1_f_wr_addr$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ;
assign fabric_xactors_from_masters_1_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_1_f_wr_data
assign fabric_xactors_from_masters_1_f_wr_data$D_IN =
{ v_from_masters_1_wdata,
v_from_masters_1_wstrb,
v_from_masters_1_wlast } ;
assign fabric_xactors_from_masters_1_f_wr_data$ENQ =
v_from_masters_1_wvalid &&
fabric_xactors_from_masters_1_f_wr_data$FULL_N ;
assign fabric_xactors_from_masters_1_f_wr_data$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 ;
assign fabric_xactors_from_masters_1_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_1_f_wr_resp
always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 or
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 or
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 or
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 or
MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4:
fabric_xactors_from_masters_1_f_wr_resp$D_IN =
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3:
fabric_xactors_from_masters_1_f_wr_resp$D_IN =
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5:
fabric_xactors_from_masters_1_f_wr_resp$D_IN =
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1:
fabric_xactors_from_masters_1_f_wr_resp$D_IN =
MUX_fabric_xactors_from_masters_1_f_wr_resp$enq_1__VAL_4;
default: fabric_xactors_from_masters_1_f_wr_resp$D_IN =
6'b101010 /* unspecified value */ ;
endcase
end
assign fabric_xactors_from_masters_1_f_wr_resp$ENQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 ;
assign fabric_xactors_from_masters_1_f_wr_resp$DEQ =
v_from_masters_1_bready &&
fabric_xactors_from_masters_1_f_wr_resp$EMPTY_N ;
assign fabric_xactors_from_masters_1_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_rd_addr
assign fabric_xactors_to_slaves_0_f_rd_addr$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ?
fabric_xactors_from_masters_0_f_rd_addr$D_OUT :
fabric_xactors_from_masters_1_f_rd_addr$D_OUT ;
assign fabric_xactors_to_slaves_0_f_rd_addr$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 ;
assign fabric_xactors_to_slaves_0_f_rd_addr$DEQ =
fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N &&
v_to_slaves_0_arready ;
assign fabric_xactors_to_slaves_0_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_rd_data
assign fabric_xactors_to_slaves_0_f_rd_data$D_IN =
{ v_to_slaves_0_rid,
v_to_slaves_0_rdata,
v_to_slaves_0_rresp,
v_to_slaves_0_rlast } ;
assign fabric_xactors_to_slaves_0_f_rd_data$ENQ =
v_to_slaves_0_rvalid &&
fabric_xactors_to_slaves_0_f_rd_data$FULL_N ;
assign fabric_xactors_to_slaves_0_f_rd_data$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ;
assign fabric_xactors_to_slaves_0_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_wr_addr
assign fabric_xactors_to_slaves_0_f_wr_addr$D_IN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ?
fabric_xactors_from_masters_0_f_wr_addr$D_OUT :
fabric_xactors_from_masters_1_f_wr_addr$D_OUT ;
assign fabric_xactors_to_slaves_0_f_wr_addr$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 ;
assign fabric_xactors_to_slaves_0_f_wr_addr$DEQ =
fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N &&
v_to_slaves_0_awready ;
assign fabric_xactors_to_slaves_0_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_wr_data
assign fabric_xactors_to_slaves_0_f_wr_data$D_IN =
MUX_fabric_xactors_to_slaves_0_f_wr_data$enq_1__SEL_1 ?
fabric_xactors_from_masters_0_f_wr_data$D_OUT :
fabric_xactors_from_masters_1_f_wr_data$D_OUT ;
assign fabric_xactors_to_slaves_0_f_wr_data$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd0 ;
assign fabric_xactors_to_slaves_0_f_wr_data$DEQ =
fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N &&
v_to_slaves_0_wready ;
assign fabric_xactors_to_slaves_0_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_wr_resp
assign fabric_xactors_to_slaves_0_f_wr_resp$D_IN =
{ v_to_slaves_0_bid, v_to_slaves_0_bresp } ;
assign fabric_xactors_to_slaves_0_f_wr_resp$ENQ =
v_to_slaves_0_bvalid &&
fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ;
assign fabric_xactors_to_slaves_0_f_wr_resp$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
assign fabric_xactors_to_slaves_0_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_rd_addr
assign fabric_xactors_to_slaves_1_f_rd_addr$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ?
fabric_xactors_from_masters_0_f_rd_addr$D_OUT :
fabric_xactors_from_masters_1_f_rd_addr$D_OUT ;
assign fabric_xactors_to_slaves_1_f_rd_addr$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 ;
assign fabric_xactors_to_slaves_1_f_rd_addr$DEQ =
fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N &&
v_to_slaves_1_arready ;
assign fabric_xactors_to_slaves_1_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_rd_data
assign fabric_xactors_to_slaves_1_f_rd_data$D_IN =
{ v_to_slaves_1_rid,
v_to_slaves_1_rdata,
v_to_slaves_1_rresp,
v_to_slaves_1_rlast } ;
assign fabric_xactors_to_slaves_1_f_rd_data$ENQ =
v_to_slaves_1_rvalid &&
fabric_xactors_to_slaves_1_f_rd_data$FULL_N ;
assign fabric_xactors_to_slaves_1_f_rd_data$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ;
assign fabric_xactors_to_slaves_1_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_wr_addr
assign fabric_xactors_to_slaves_1_f_wr_addr$D_IN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ?
fabric_xactors_from_masters_0_f_wr_addr$D_OUT :
fabric_xactors_from_masters_1_f_wr_addr$D_OUT ;
assign fabric_xactors_to_slaves_1_f_wr_addr$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 ;
assign fabric_xactors_to_slaves_1_f_wr_addr$DEQ =
fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N &&
v_to_slaves_1_awready ;
assign fabric_xactors_to_slaves_1_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_wr_data
assign fabric_xactors_to_slaves_1_f_wr_data$D_IN =
MUX_fabric_xactors_to_slaves_1_f_wr_data$enq_1__SEL_1 ?
fabric_xactors_from_masters_0_f_wr_data$D_OUT :
fabric_xactors_from_masters_1_f_wr_data$D_OUT ;
assign fabric_xactors_to_slaves_1_f_wr_data$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd1 ;
assign fabric_xactors_to_slaves_1_f_wr_data$DEQ =
fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N &&
v_to_slaves_1_wready ;
assign fabric_xactors_to_slaves_1_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_wr_resp
assign fabric_xactors_to_slaves_1_f_wr_resp$D_IN =
{ v_to_slaves_1_bid, v_to_slaves_1_bresp } ;
assign fabric_xactors_to_slaves_1_f_wr_resp$ENQ =
v_to_slaves_1_bvalid &&
fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ;
assign fabric_xactors_to_slaves_1_f_wr_resp$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ;
assign fabric_xactors_to_slaves_1_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_rd_addr
assign fabric_xactors_to_slaves_2_f_rd_addr$D_IN =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ?
fabric_xactors_from_masters_0_f_rd_addr$D_OUT :
fabric_xactors_from_masters_1_f_rd_addr$D_OUT ;
assign fabric_xactors_to_slaves_2_f_rd_addr$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 ;
assign fabric_xactors_to_slaves_2_f_rd_addr$DEQ =
fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N &&
v_to_slaves_2_arready ;
assign fabric_xactors_to_slaves_2_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_rd_data
assign fabric_xactors_to_slaves_2_f_rd_data$D_IN =
{ v_to_slaves_2_rid,
v_to_slaves_2_rdata,
v_to_slaves_2_rresp,
v_to_slaves_2_rlast } ;
assign fabric_xactors_to_slaves_2_f_rd_data$ENQ =
v_to_slaves_2_rvalid &&
fabric_xactors_to_slaves_2_f_rd_data$FULL_N ;
assign fabric_xactors_to_slaves_2_f_rd_data$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ;
assign fabric_xactors_to_slaves_2_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_wr_addr
assign fabric_xactors_to_slaves_2_f_wr_addr$D_IN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ?
fabric_xactors_from_masters_0_f_wr_addr$D_OUT :
fabric_xactors_from_masters_1_f_wr_addr$D_OUT ;
assign fabric_xactors_to_slaves_2_f_wr_addr$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 ;
assign fabric_xactors_to_slaves_2_f_wr_addr$DEQ =
fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N &&
v_to_slaves_2_awready ;
assign fabric_xactors_to_slaves_2_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_wr_data
assign fabric_xactors_to_slaves_2_f_wr_data$D_IN =
MUX_fabric_xactors_to_slaves_2_f_wr_data$enq_1__SEL_1 ?
fabric_xactors_from_masters_0_f_wr_data$D_OUT :
fabric_xactors_from_masters_1_f_wr_data$D_OUT ;
assign fabric_xactors_to_slaves_2_f_wr_data$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_f_wd_tasks_1$D_OUT[9:8] == 2'd2 ;
assign fabric_xactors_to_slaves_2_f_wr_data$DEQ =
fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N &&
v_to_slaves_2_wready ;
assign fabric_xactors_to_slaves_2_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_wr_resp
assign fabric_xactors_to_slaves_2_f_wr_resp$D_IN =
{ v_to_slaves_2_bid, v_to_slaves_2_bresp } ;
assign fabric_xactors_to_slaves_2_f_wr_resp$ENQ =
v_to_slaves_2_bvalid &&
fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ;
assign fabric_xactors_to_slaves_2_f_wr_resp$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ;
assign fabric_xactors_to_slaves_2_f_wr_resp$CLR = fabric_rg_reset ;
// submodule soc_map
assign soc_map$m_is_IO_addr_addr = 64'h0 ;
assign soc_map$m_is_mem_addr_addr = 64'h0 ;
assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;
// remaining internal signals
assign IF_fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_ETC___d503 =
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d487 ?
x1_avValue_rresp__h18603 :
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ;
assign IF_fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_ETC___d538 =
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d522 ?
x1_avValue_rresp__h19229 :
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ;
assign IF_fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_ETC___d573 =
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d557 ?
x1_avValue_rresp__h19845 :
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ;
assign IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d102 =
(soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d89 &&
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) ?
2'd1 :
((soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d92 &&
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) ?
2'd0 :
2'd2) ;
assign IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d349 =
(soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d336 &&
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d337) ?
2'd1 :
((soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d339 &&
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d340) ?
2'd0 :
2'd2) ;
assign IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d37 =
(soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d19 &&
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d21) ?
2'd1 :
((soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d24 &&
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26) ?
2'd0 :
2'd2) ;
assign IF_soc_map_m_mem0_controller_addr_base__6_ULE__ETC___d405 =
(soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d392 &&
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d393) ?
2'd1 :
((soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d395 &&
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d396) ?
2'd0 :
2'd2) ;
assign NOT_soc_map_m_mem0_controller_addr_base__6_ULE_ETC___d148 =
(!soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d19 ||
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d21) &&
(!soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d24 ||
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26) &&
(!soc_map_m_uart0_addr_base__8_ULE_fabric_xactor_ETC___d29 ||
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d31) ;
assign NOT_soc_map_m_mem0_controller_addr_base__6_ULE_ETC___d167 =
(!soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d89 ||
!fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90) &&
(!soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d92 ||
!fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93) &&
(!soc_map_m_uart0_addr_base__8_ULE_fabric_xactor_ETC___d95 ||
!fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96) ;
assign NOT_soc_map_m_mem0_controller_addr_base__6_ULE_ETC___d448 =
(!soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d336 ||
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d337) &&
(!soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d339 ||
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d340) &&
(!soc_map_m_uart0_addr_base__8_ULE_fabric_xactor_ETC___d342 ||
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d343) ;
assign NOT_soc_map_m_mem0_controller_addr_base__6_ULE_ETC___d466 =
(!soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d392 ||
!fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d393) &&
(!soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d395 ||
!fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d396) &&
(!soc_map_m_uart0_addr_base__8_ULE_fabric_xactor_ETC___d398 ||
!fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d399) ;
assign _dor1fabric_v_f_rd_mis_0$EN_deq =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ;
assign _dor1fabric_v_f_rd_mis_1$EN_deq =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ;
assign _dor1fabric_v_f_rd_mis_2$EN_deq =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ;
assign fabric_v_f_wd_tasks_0_i_notEmpty__73_AND_fabri_ETC___d182 =
fabric_v_f_wd_tasks_0$EMPTY_N &&
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ;
assign fabric_v_f_wd_tasks_1_i_notEmpty__05_AND_fabri_ETC___d211 =
fabric_v_f_wd_tasks_1$EMPTY_N &&
CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 ;
assign fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d487 =
fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ;
assign fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d522 =
fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ;
assign fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d557 =
fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ;
assign fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d622 =
fabric_v_rg_r_err_beat_count_0 ==
fabric_v_f_rd_err_info_0$D_OUT[11:4] ;
assign fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d640 =
fabric_v_rg_r_err_beat_count_1 ==
fabric_v_f_rd_err_info_1$D_OUT[11:4] ;
assign fabric_v_rg_wd_beat_count_0_90_EQ_fabric_v_f_w_ETC___d198 =
fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ;
assign fabric_v_rg_wd_beat_count_1_19_EQ_fabric_v_f_w_ETC___d227 =
fabric_v_rg_wd_beat_count_1 == fabric_v_f_wd_tasks_1$D_OUT[7:0] ;
assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d337 =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] <
soc_map$m_mem0_controller_addr_lim ;
assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d340 =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] <
soc_map$m_boot_rom_addr_lim ;
assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d343 =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] <
soc_map$m_uart0_addr_lim ;
assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d21 =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] <
soc_map$m_mem0_controller_addr_lim ;
assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26 =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] <
soc_map$m_boot_rom_addr_lim ;
assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d31 =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] <
soc_map$m_uart0_addr_lim ;
assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d393 =
fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] <
soc_map$m_mem0_controller_addr_lim ;
assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d396 =
fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] <
soc_map$m_boot_rom_addr_lim ;
assign fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d399 =
fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] <
soc_map$m_uart0_addr_lim ;
assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 =
fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] <
soc_map$m_mem0_controller_addr_lim ;
assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 =
fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] <
soc_map$m_boot_rom_addr_lim ;
assign fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 =
fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] <
soc_map$m_uart0_addr_lim ;
assign soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d24 =
soc_map$m_boot_rom_addr_base <=
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ;
assign soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d339 =
soc_map$m_boot_rom_addr_base <=
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ;
assign soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d395 =
soc_map$m_boot_rom_addr_base <=
fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ;
assign soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d92 =
soc_map$m_boot_rom_addr_base <=
fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ;
assign soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d19 =
soc_map$m_mem0_controller_addr_base <=
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ;
assign soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d336 =
soc_map$m_mem0_controller_addr_base <=
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ;
assign soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d34 =
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d19 &&
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d21 ||
soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d24 &&
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d26 ||
soc_map_m_uart0_addr_base__8_ULE_fabric_xactor_ETC___d29 &&
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d31 ;
assign soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d346 =
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d336 &&
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d337 ||
soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d339 &&
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d340 ||
soc_map_m_uart0_addr_base__8_ULE_fabric_xactor_ETC___d342 &&
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d343 ;
assign soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d392 =
soc_map$m_mem0_controller_addr_base <=
fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ;
assign soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d402 =
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d392 &&
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d393 ||
soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d395 &&
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d396 ||
soc_map_m_uart0_addr_base__8_ULE_fabric_xactor_ETC___d398 &&
fabric_xactors_from_masters_1_f_rd_addr_first__ETC___d399 ;
assign soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d89 =
soc_map$m_mem0_controller_addr_base <=
fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ;
assign soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d99 =
soc_map_m_mem0_controller_addr_base__6_ULE_fab_ETC___d89 &&
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d90 ||
soc_map_m_boot_rom_addr_base__3_ULE_fabric_xac_ETC___d92 &&
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d93 ||
soc_map_m_uart0_addr_base__8_ULE_fabric_xactor_ETC___d95 &&
fabric_xactors_from_masters_1_f_wr_addr_first__ETC___d96 ;
assign soc_map_m_uart0_addr_base__8_ULE_fabric_xactor_ETC___d29 =
soc_map$m_uart0_addr_base <=
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ;
assign soc_map_m_uart0_addr_base__8_ULE_fabric_xactor_ETC___d342 =
soc_map$m_uart0_addr_base <=
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ;
assign soc_map_m_uart0_addr_base__8_ULE_fabric_xactor_ETC___d398 =
soc_map$m_uart0_addr_base <=
fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29] ;
assign soc_map_m_uart0_addr_base__8_ULE_fabric_xactor_ETC___d95 =
soc_map$m_uart0_addr_base <=
fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29] ;
assign x1_avValue_rresp__h18603 =
(fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ?
2'b10 :
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ;
assign x1_avValue_rresp__h19229 =
(fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ?
2'b10 :
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ;
assign x1_avValue_rresp__h19845 =
(fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ?
2'b10 :
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ;
assign x__h12049 = fabric_v_rg_wd_beat_count_0 + 8'd1 ;
assign x__h12675 = fabric_v_rg_wd_beat_count_1 + 8'd1 ;
assign x__h18625 = fabric_v_rg_r_beat_count_0 + 8'd1 ;
assign x__h19251 = fabric_v_rg_r_beat_count_1 + 8'd1 ;
assign x__h19867 = fabric_v_rg_r_beat_count_2 + 8'd1 ;
assign x__h22171 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ;
assign x__h22572 = fabric_v_rg_r_err_beat_count_1 + 8'd1 ;
always@(fabric_v_f_wd_tasks_0$D_OUT or
fabric_xactors_to_slaves_0_f_wr_data$FULL_N or
fabric_xactors_to_slaves_1_f_wr_data$FULL_N or
fabric_xactors_to_slaves_2_f_wr_data$FULL_N)
begin
case (fabric_v_f_wd_tasks_0$D_OUT[9:8])
2'd0:
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 =
fabric_xactors_to_slaves_0_f_wr_data$FULL_N;
2'd1:
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 =
fabric_xactors_to_slaves_1_f_wr_data$FULL_N;
2'd2:
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 =
fabric_xactors_to_slaves_2_f_wr_data$FULL_N;
2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1;
endcase
end
always@(fabric_v_f_wd_tasks_1$D_OUT or
fabric_xactors_to_slaves_0_f_wr_data$FULL_N or
fabric_xactors_to_slaves_1_f_wr_data$FULL_N or
fabric_xactors_to_slaves_2_f_wr_data$FULL_N)
begin
case (fabric_v_f_wd_tasks_1$D_OUT[9:8])
2'd0:
CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 =
fabric_xactors_to_slaves_0_f_wr_data$FULL_N;
2'd1:
CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 =
fabric_xactors_to_slaves_1_f_wr_data$FULL_N;
2'd2:
CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 =
fabric_xactors_to_slaves_2_f_wr_data$FULL_N;
2'd3: CASE_fabric_v_f_wd_tasks_1D_OUT_BITS_9_TO_8_0_ETC__q2 = 1'd1;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1;
fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0;
end
else
begin
if (fabric_cfg_verbosity$EN)
fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY
fabric_cfg_verbosity$D_IN;
if (fabric_rg_reset$EN)
fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN;
if (fabric_v_rg_r_beat_count_0$EN)
fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_beat_count_0$D_IN;
if (fabric_v_rg_r_beat_count_1$EN)
fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_beat_count_1$D_IN;
if (fabric_v_rg_r_beat_count_2$EN)
fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_beat_count_2$D_IN;
if (fabric_v_rg_r_err_beat_count_0$EN)
fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_err_beat_count_0$D_IN;
if (fabric_v_rg_r_err_beat_count_1$EN)
fabric_v_rg_r_err_beat_count_1 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_err_beat_count_1$D_IN;
if (fabric_v_rg_wd_beat_count_0$EN)
fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_wd_beat_count_0$D_IN;
if (fabric_v_rg_wd_beat_count_1$EN)
fabric_v_rg_wd_beat_count_1 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_wd_beat_count_1$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
fabric_cfg_verbosity = 4'hA;
fabric_rg_reset = 1'h0;
fabric_v_rg_r_beat_count_0 = 8'hAA;
fabric_v_rg_r_beat_count_1 = 8'hAA;
fabric_v_rg_r_beat_count_2 = 8'hAA;
fabric_v_rg_r_err_beat_count_0 = 8'hAA;
fabric_v_rg_r_err_beat_count_1 = 8'hAA;
fabric_v_rg_wd_beat_count_0 = 8'hAA;
fabric_v_rg_wd_beat_count_1 = 8'hAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
begin
v__h8720 = $stime;
#0;
end
v__h8714 = v__h8720 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h8714,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h9120 = $stime;
#0;
end
v__h9114 = v__h9120 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h9114,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h9520 = $stime;
#0;
end
v__h9514 = v__h9520 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h9514,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h9990 = $stime;
#0;
end
v__h9984 = v__h9990 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h9984,
$signed(32'd1),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h10384 = $stime;
#0;
end
v__h10378 = v__h10384 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h10378,
$signed(32'd1),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h10778 = $stime;
#0;
end
v__h10772 = v__h10778 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h10772,
$signed(32'd1),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
begin
v__h11160 = $stime;
#0;
end
v__h11154 = v__h11160 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_no_such_slave: m%0d -> ?",
v__h11154,
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h11498 = $stime;
#0;
end
v__h11492 = v__h11498 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_no_such_slave: m%0d -> ?",
v__h11492,
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
begin
v__h11898 = $stime;
#0;
end
v__h11892 = v__h11898 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave_data: m%0d -> s%0d, beat %0d/%0d",
v__h11892,
$signed(32'd0),
fabric_v_f_wd_tasks_0$D_OUT[9:8],
fabric_v_rg_wd_beat_count_0,
fabric_v_f_wd_tasks_0$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_90_EQ_fabric_v_f_w_ETC___d198 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
begin
v__h12144 = $stime;
#0;
end
v__h12138 = v__h12144 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_90_EQ_fabric_v_f_w_ETC___d198 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d",
v__h12138,
$signed(32'd0),
fabric_v_f_wd_tasks_0$D_OUT[9:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_90_EQ_fabric_v_f_w_ETC___d198 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$display(" WLAST not set on final data beat (awlen = %0d)",
fabric_v_f_wd_tasks_0$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_90_EQ_fabric_v_f_w_ETC___d198 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_90_EQ_fabric_v_f_w_ETC___d198 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_90_EQ_fabric_v_f_w_ETC___d198 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_90_EQ_fabric_v_f_w_ETC___d198 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_90_EQ_fabric_v_f_w_ETC___d198 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_90_EQ_fabric_v_f_w_ETC___d198 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_90_EQ_fabric_v_f_w_ETC___d198 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_90_EQ_fabric_v_f_w_ETC___d198 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_90_EQ_fabric_v_f_w_ETC___d198 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_90_EQ_fabric_v_f_w_ETC___d198 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h12524 = $stime;
#0;
end
v__h12518 = v__h12524 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave_data: m%0d -> s%0d, beat %0d/%0d",
v__h12518,
$signed(32'd1),
fabric_v_f_wd_tasks_1$D_OUT[9:8],
fabric_v_rg_wd_beat_count_1,
fabric_v_f_wd_tasks_1$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_19_EQ_fabric_v_f_w_ETC___d227 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
begin
v__h12770 = $stime;
#0;
end
v__h12764 = v__h12770 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_19_EQ_fabric_v_f_w_ETC___d227 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d",
v__h12764,
$signed(32'd1),
fabric_v_f_wd_tasks_1$D_OUT[9:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_19_EQ_fabric_v_f_w_ETC___d227 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$display(" WLAST not set on final data beat (awlen = %0d)",
fabric_v_f_wd_tasks_1$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_19_EQ_fabric_v_f_w_ETC___d227 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_19_EQ_fabric_v_f_w_ETC___d227 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_19_EQ_fabric_v_f_w_ETC___d227 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_19_EQ_fabric_v_f_w_ETC___d227 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_19_EQ_fabric_v_f_w_ETC___d227 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("'h%h", fabric_xactors_from_masters_1_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_19_EQ_fabric_v_f_w_ETC___d227 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_19_EQ_fabric_v_f_w_ETC___d227 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_19_EQ_fabric_v_f_w_ETC___d227 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_19_EQ_fabric_v_f_w_ETC___d227 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data_1 &&
fabric_v_rg_wd_beat_count_1_19_EQ_fabric_v_f_w_ETC___d227 &&
!fabric_xactors_from_masters_1_f_wr_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h13147 = $stime;
#0;
end
v__h13141 = v__h13147 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h13141,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h13439 = $stime;
#0;
end
v__h13433 = v__h13439 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h13433,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h13731 = $stime;
#0;
end
v__h13725 = v__h13731 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h13725,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h14034 = $stime;
#0;
end
v__h14028 = v__h14034 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h14028,
$signed(32'd1),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h14300 = $stime;
#0;
end
v__h14294 = v__h14300 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h14294,
$signed(32'd1),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h14566 = $stime;
#0;
end
v__h14560 = v__h14566 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h14560,
$signed(32'd1),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h14830 = $stime;
#0;
end
v__h14824 = v__h14830 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err",
v__h14824,
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_v_f_wr_err_info_0$D_OUT);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h15056 = $stime;
#0;
end
v__h15050 = v__h15056 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err",
v__h15050,
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_v_f_wr_err_info_1$D_OUT);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
begin
v__h15510 = $stime;
#0;
end
v__h15504 = v__h15510 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h15504,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h15891 = $stime;
#0;
end
v__h15885 = v__h15891 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h15885,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h16272 = $stime;
#0;
end
v__h16266 = v__h16272 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h16266,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h16714 = $stime;
#0;
end
v__h16708 = v__h16714 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h16708,
$signed(32'd1),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_3 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h17071 = $stime;
#0;
end
v__h17065 = v__h17071 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h17065,
$signed(32'd1),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_4 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h17428 = $stime;
#0;
end
v__h17422 = v__h17428 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h17422,
$signed(32'd1),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_5 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
begin
v__h17779 = $stime;
#0;
end
v__h17773 = v__h17779 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_no_such_slave: m%0d -> ?",
v__h17773,
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h18080 = $stime;
#0;
end
v__h18074 = v__h18080 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_no_such_slave: m%0d -> ?",
v__h18074,
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_1_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_no_such_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d487 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
begin
v__h18488 = $stime;
#0;
end
v__h18482 = v__h18488 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d487 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h18482,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d487 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_0$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d487 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d487 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d487 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d487 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d487 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d487 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d487 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d487 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d487 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d487 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d487 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d487 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h18739 = $stime;
#0;
end
v__h18733 = v__h18739 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h18733,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_ETC___d503);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d522 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
begin
v__h19114 = $stime;
#0;
end
v__h19108 = v__h19114 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d522 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h19108,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d522 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_1$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d522 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d522 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d522 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d522 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d522 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d522 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d522 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d522 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d522 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d522 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d522 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d522 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h19355 = $stime;
#0;
end
v__h19349 = v__h19355 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h19349,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_ETC___d538);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d557 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
begin
v__h19730 = $stime;
#0;
end
v__h19724 = v__h19730 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d557 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h19724,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d557 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_2$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d557 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d557 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d557 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d557 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d557 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d557 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d557 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d557 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d557 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d557 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d557 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d557 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h19971 = $stime;
#0;
end
v__h19965 = v__h19971 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h19965,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_ETC___d573);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d487 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
begin
v__h20333 = $stime;
#0;
end
v__h20327 = v__h20333 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d487 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h20327,
$signed(32'd1),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d487 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_0$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d487 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d487 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d487 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d487 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d487 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d487 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d487 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d487 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d487 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d487 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d487 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_rd_ETC___d487 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h20584 = $stime;
#0;
end
v__h20578 = v__h20584 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h20578,
$signed(32'd1),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_0_85_EQ_fabric_v_f_ETC___d503);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_3 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d522 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
begin
v__h20914 = $stime;
#0;
end
v__h20908 = v__h20914 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d522 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h20908,
$signed(32'd1),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d522 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_1$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d522 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d522 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d522 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d522 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d522 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d522 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d522 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d522 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d522 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d522 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d522 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_rd_ETC___d522 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h21155 = $stime;
#0;
end
v__h21149 = v__h21155 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h21149,
$signed(32'd1),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_1_20_EQ_fabric_v_f_ETC___d538);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_4 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d557 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
begin
v__h21485 = $stime;
#0;
end
v__h21479 = v__h21485 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d557 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h21479,
$signed(32'd1),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d557 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_2$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d557 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d557 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d557 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d557 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d557 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d557 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d557 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d557 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d557 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d557 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d557 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_rd_ETC___d557 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h21726 = $stime;
#0;
end
v__h21720 = v__h21726 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h21720,
$signed(32'd1),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_2_55_EQ_fabric_v_f_ETC___d573);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_5 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h22239 = $stime;
#0;
end
v__h22233 = v__h22239 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err",
v__h22233,
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 64'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0 &&
fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d622)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_v_rg_r_err_beat_count_0_20_EQ_fabric_v__ETC___d622)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h22640 = $stime;
#0;
end
v__h22634 = v__h22640 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err",
v__h22634,
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_v_f_rd_err_info_1$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 64'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d640)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_v_rg_r_err_beat_count_1_38_EQ_fabric_v__ETC___d640)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (fabric_rg_reset && fabric_cfg_verbosity != 4'd0)
begin
v__h5716 = $stime;
#0;
end
v__h5710 = v__h5716 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (fabric_rg_reset && fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_reset", v__h5710);
end
// synopsys translate_on
endmodule // mkFabric_AXI4
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21BOI_0_V
`define SKY130_FD_SC_HD__A21BOI_0_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21boi with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a21boi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a21boi_0 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a21boi_0 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21BOI_0_V
|
//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module SD_CLK (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg data_out;
wire out_port;
wire read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata;
end
assign readdata = {{{32- 1}{1'b0}},read_mux_out};
assign out_port = data_out;
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// sm_fifoRTL.v ////
//// ////
//// This file is part of the spiMaster opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// parameterized dual clock domain fifo.
//// fifo depth is restricted to 2^ADDR_WIDTH
//// No protection against over runs and under runs.
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
module sm_fifoDMA(fifoClk, reset, dataIn,
dataOut, fifoWEn, fifoREn,
forceEmptyWr, forceEmptyRd,
do_peri, di_peri, addr_peri, mem_clk, mem_access, store_access, addr_high);
//FIFO_DEPTH = ADDR_WIDTH^2. Min = 2, Max = 66536
parameter FIFO_DEPTH = 64;
parameter ADDR_WIDTH = 6;
parameter DMA_ADR = 18'h19c00; //1024 addresses below IO ports
parameter FIFO_WIDTH = 8;
// Two clock domains within this module, DMA and fifo clocks
input fifoClk;
input reset;
input [FIFO_WIDTH-1:0] dataIn;
input fifoWEn;
input forceEmptyWr;
output [FIFO_WIDTH-1:0] dataOut;
input fifoREn;
input forceEmptyRd;
//*** Connections to SpartanMC Core (do not change) ***
input [17:0] do_peri; //Data Bus from MC
output [17:0] di_peri; //Data Bus to MC
input [9:0] addr_peri; //Address Bus from MC
// BlockRAM interface
input mem_clk; //BRAM clk
input mem_access;
input store_access;
input [7:0] addr_high;
wire fifoClk;
wire reset;
wire [FIFO_WIDTH-1:0] dataIn;
reg [FIFO_WIDTH-1:0] dataOut;
wire fifoWEn;
wire fifoREn;
wire forceEmpty;
reg [15:0]numElementsInFifo;
// local registers
reg [ADDR_WIDTH:0]bufferInIndex;
reg [ADDR_WIDTH:0]bufferOutIndex;
reg [ADDR_WIDTH-1:0]bufferIndexToMem;
reg fifoREnDelayed;
wire [FIFO_WIDTH-1:0] dataFromMem;
always @(posedge fifoClk)
begin
if (reset == 1'b1 || forceEmptyWr == 1'b1)
begin
bufferInIndex <= 0;
end
else
begin
if (fifoWEn == 1'b1) begin
bufferInIndex <= bufferInIndex + 1'b1;
end
end
end
always @(posedge fifoClk)
begin
if (reset == 1'b1 || forceEmptyRd == 1'b1)
begin
bufferOutIndex <= 0;
fifoREnDelayed <= 1'b0;
end
else
begin
fifoREnDelayed <= fifoREn;
if (fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
dataOut <= dataFromMem;
bufferOutIndex <= bufferOutIndex + 1'b1;
end
end
end
always @(bufferInIndex or bufferOutIndex or fifoWEn) begin
if (fifoWEn) begin
bufferIndexToMem <= bufferInIndex[ADDR_WIDTH-1:0];
end else begin
bufferIndexToMem <= bufferOutIndex[ADDR_WIDTH-1:0];
end
end
wire activ_dma0;
pselect #(
.ADDR_WIDTH (8 ),
.BASE_WIDTH (8 ),
.BASE_ADDR (DMA_ADR >> 10 ) // using upper 8 bit of address
)
dmasel0 (
.addr (addr_high[7:0] ),
.activ_peri (mem_access ),
.select (activ_dma0 )
);
RAMB16_S9_S9 fifo_mem (
// Port A, access from SD card module
.DIA (dataIn[7:0] ),
.DIPA (1'd0 ),
.ADDRA ({2'b0, bufferIndexToMem} ),
.ENA (1'b1 ),
.WEA (fifoWEn ),
.SSRA (1'b0 ),
.CLKA (fifoClk ),
.DOA (dataFromMem[7:0] ),
// .DOPA (dataFromMem[8] ),
// Port B, access from SpartanMC
.DIB (do_peri[7:0] ),
.DIPB (do_peri[8] ),
.ADDRB ({1'b0, addr_peri[9:0]} ),
.ENB (1'b1 ),
.WEB (store_access & activ_dma0 ),
.SSRB (! activ_dma0 ),
.CLKB (mem_clk ),
.DOB (di_peri[7:0] ),
.DOPB (di_peri[8] )
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A31OI_SYMBOL_V
`define SKY130_FD_SC_HS__A31OI_SYMBOL_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a31oi (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A31OI_SYMBOL_V
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_leds_pio_0 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 7: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 7: 0] data_out;
wire [ 7: 0] out_port;
wire [ 7: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 255;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[7 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
/**
* bsg_wormhole_router_adapter_in.v
*
* packet = {payload, length, cord}
*/
`include "bsg_defines.v"
`include "bsg_noc_links.vh"
`include "bsg_wormhole_router.vh"
module bsg_wormhole_router_adapter_in
#(parameter `BSG_INV_PARAM(max_payload_width_p )
, parameter `BSG_INV_PARAM(len_width_p )
, parameter `BSG_INV_PARAM(cord_width_p )
, parameter `BSG_INV_PARAM(flit_width_p )
, localparam bsg_ready_and_link_sif_width_lp =
`bsg_ready_and_link_sif_width(flit_width_p)
, localparam bsg_wormhole_packet_width_lp =
`bsg_wormhole_router_packet_width(cord_width_p, len_width_p, max_payload_width_p)
)
(input clk_i
, input reset_i
, input [bsg_wormhole_packet_width_lp-1:0] packet_i
, input v_i
, output ready_o
, output [bsg_ready_and_link_sif_width_lp-1:0] link_o
, input [bsg_ready_and_link_sif_width_lp-1:0] link_i
);
// Casting ports
`declare_bsg_ready_and_link_sif_s(flit_width_p, bsg_ready_and_link_sif_s);
bsg_ready_and_link_sif_s link_cast_i, link_cast_o;
`declare_bsg_wormhole_router_packet_s(cord_width_p, len_width_p, max_payload_width_p, bsg_wormhole_packet_s);
bsg_wormhole_packet_s packet_cast_i;
assign packet_cast_i = packet_i;
localparam max_num_flits_lp = `BSG_CDIV($bits(bsg_wormhole_packet_s), flit_width_p);
localparam protocol_len_lp = `BSG_SAFE_CLOG2(max_num_flits_lp);
wire [max_num_flits_lp*flit_width_p-1:0] packet_padded_li = packet_i;
assign link_cast_i = link_i;
assign link_o = link_cast_o;
bsg_parallel_in_serial_out_dynamic
#(.width_p(flit_width_p)
,.max_els_p(max_num_flits_lp)
)
piso
(.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(v_i)
,.len_i(protocol_len_lp'(packet_cast_i.len))
,.data_i(packet_padded_li)
,.ready_o(ready_o)
,.v_o(link_cast_o.v)
,.len_v_o(/* unused */)
,.data_o(link_cast_o.data)
,.yumi_i(link_cast_i.ready_and_rev & link_cast_o.v)
);
// Stub the input ready, since this is an input adapter
assign link_cast_o.ready_and_rev = 1'b0;
`ifndef SYNTHESIS
always_ff @(negedge clk_i)
assert(reset_i || ~v_i || (packet_cast_i.len <= max_num_flits_lp))
else
$error("Packet received with len: %x > max_num_flits: %x", packet_cast_i.len, max_num_flits_lp);
`endif
endmodule
`BSG_ABSTRACT_MODULE(bsg_wormhole_router_adapter_in)
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ADC channel-
`timescale 1ns/100ps
module axi_ad6676_channel (
// adc interface
adc_clk,
adc_rst,
adc_data,
adc_or,
// channel interface
adc_dfmt_data,
adc_enable,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter IQSEL = 0;
parameter CHID = 0;
// adc interface
input adc_clk;
input adc_rst;
input [31:0] adc_data;
input adc_or;
// channel interface
output [31:0] adc_dfmt_data;
output adc_enable;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal signals
wire adc_pn_oos_s;
wire adc_pn_err_s;
wire [ 3:0] adc_pnseq_sel_s;
// instantiations
axi_ad6676_pnmon i_pnmon (
.adc_clk (adc_clk),
.adc_data (adc_data),
.adc_pn_oos (adc_pn_oos_s),
.adc_pn_err (adc_pn_err_s),
.adc_pnseq_sel (adc_pnseq_sel_s));
assign adc_dfmt_data = adc_data;
up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
.adc_iqcor_enb (),
.adc_dcfilt_enb (),
.adc_dfmt_se (),
.adc_dfmt_type (),
.adc_dfmt_enable (),
.adc_dcfilt_offset (),
.adc_dcfilt_coeff (),
.adc_iqcor_coeff_1 (),
.adc_iqcor_coeff_2 (),
.adc_pnseq_sel (adc_pnseq_sel_s),
.adc_data_sel (),
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_or (adc_or),
.up_adc_pn_err (up_adc_pn_err),
.up_adc_pn_oos (up_adc_pn_oos),
.up_adc_or (up_adc_or),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd16),
.adc_usr_datatype_bits (8'd16),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Fri Mar 31 18:24:55 2017
// Host : LAPTOP-IQ9G3D1I running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top mig_wrap_proc_sys_reset_1_0 -prefix
// mig_wrap_proc_sys_reset_1_0_ mig_wrap_proc_sys_reset_0_0_stub.v
// Design : mig_wrap_proc_sys_reset_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7vx485tffg1761-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "proc_sys_reset,Vivado 2016.4" *)
module mig_wrap_proc_sys_reset_1_0(slowest_sync_clk, ext_reset_in, aux_reset_in,
mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset,
interconnect_aresetn, peripheral_aresetn)
/* synthesis syn_black_box black_box_pad_pin="slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */;
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
output [0:0]bus_struct_reset;
output [0:0]peripheral_reset;
output [0:0]interconnect_aresetn;
output [0:0]peripheral_aresetn;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: flop_rptrs_xc6.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module flop_rptrs_xc6(/*AUTOARG*/
// Outputs
sparc_out, so, jbussync2_out, jbussync1_out, grst_out,
gdbginit_out, ddrsync2_out, ddrsync1_out, cken_out,
// Inputs
spare_in, se, sd, jbussync2_in, jbussync1_in, grst_in,
gdbginit_in, gclk, ddrsync2_in, ddrsync1_in, cken_in, agrst_l,
adbginit_l
);
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [25:0] cken_out; // From cken_ff_25_ of bw_u1_soffasr_2x.v, ...
output ddrsync1_out; // From ddrsync1_ff of bw_u1_soffasr_2x.v
output ddrsync2_out; // From ddrsync2_ff of bw_u1_soffasr_2x.v
output gdbginit_out; // From gdbginit_ff of bw_u1_soffasr_2x.v
output grst_out; // From gclk_ff of bw_u1_soffasr_2x.v
output jbussync1_out; // From jbussync1_ff of bw_u1_soffasr_2x.v
output jbussync2_out; // From jbussync2_ff of bw_u1_soffasr_2x.v
output so; // From scanout_latch of bw_u1_scanlg_2x.v
output [5:0] sparc_out; // From spare_ff_5_ of bw_u1_soffasr_2x.v, ...
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input adbginit_l; // To gdbginit_ff of bw_u1_soffasr_2x.v
input agrst_l; // To spare_ff_5_ of bw_u1_soffasr_2x.v, ...
input [25:0] cken_in; // To cken_ff_25_ of bw_u1_soffasr_2x.v, ...
input ddrsync1_in; // To ddrsync1_ff of bw_u1_soffasr_2x.v
input ddrsync2_in; // To ddrsync2_ff of bw_u1_soffasr_2x.v
input gclk; // To I73 of bw_u1_ckbuf_33x.v
input gdbginit_in; // To gdbginit_ff of bw_u1_soffasr_2x.v
input grst_in; // To gclk_ff of bw_u1_soffasr_2x.v
input jbussync1_in; // To jbussync1_ff of bw_u1_soffasr_2x.v
input jbussync2_in; // To jbussync2_ff of bw_u1_soffasr_2x.v
input sd; // To spare_ff_5_ of bw_u1_soffasr_2x.v
input se; // To spare_ff_5_ of bw_u1_soffasr_2x.v, ...
input [5:0] spare_in; // To spare_ff_5_ of bw_u1_soffasr_2x.v, ...
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire clk; // From I73 of bw_u1_ckbuf_33x.v
wire scan_data_0; // From spare_ff_5_ of bw_u1_soffasr_2x.v
wire scan_data_1; // From spare_ff_4_ of bw_u1_soffasr_2x.v
wire scan_data_10; // From gdbginit_ff of bw_u1_soffasr_2x.v
wire scan_data_11; // From gclk_ff of bw_u1_soffasr_2x.v
wire scan_data_2; // From spare_ff_3_ of bw_u1_soffasr_2x.v
wire scan_data_3; // From spare_ff_2_ of bw_u1_soffasr_2x.v
wire scan_data_4; // From spare_ff_1_ of bw_u1_soffasr_2x.v
wire scan_data_5; // From spare_ff_0_ of bw_u1_soffasr_2x.v
wire scan_data_6; // From jbussync2_ff of bw_u1_soffasr_2x.v
wire scan_data_7; // From jbussync1_ff of bw_u1_soffasr_2x.v
wire scan_data_8; // From ddrsync2_ff of bw_u1_soffasr_2x.v
wire scan_data_9; // From ddrsync1_ff of bw_u1_soffasr_2x.v
// End of automatics
/* bw_u1_ckbuf_33x AUTO_TEMPLATE (
.clk (clk ),
.rclk (gclk ) ); */
bw_u1_ckbuf_33x I73
(/*AUTOINST*/
// Outputs
.clk (clk ), // Templated
// Inputs
.rclk (gclk )); // Templated
/* bw_u1_soffasr_2x AUTO_TEMPLATE (
.q (sparc_out[@]),
.d (spare_in[@]),
.ck (clk ),
.r_l (agrst_l ),
.s_l (1'b1),
.sd (scan_data_@"(- 4 @)" ),
.so (scan_data_@"(- 5 @)" ),
); */
bw_u1_soffasr_2x spare_ff_5_
(
// Inputs
.sd (sd ),
/*AUTOINST*/
// Outputs
.q (sparc_out[5]), // Templated
.so (scan_data_0 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[5]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se));
bw_u1_soffasr_2x spare_ff_4_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[4]), // Templated
.so (scan_data_1 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[4]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_0 )); // Templated
bw_u1_soffasr_2x spare_ff_3_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[3]), // Templated
.so (scan_data_2 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[3]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_1 )); // Templated
bw_u1_soffasr_2x spare_ff_2_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[2]), // Templated
.so (scan_data_3 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[2]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_2 )); // Templated
bw_u1_soffasr_2x spare_ff_1_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[1]), // Templated
.so (scan_data_4 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[1]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_3 )); // Templated
bw_u1_soffasr_2x spare_ff_0_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[0]), // Templated
.so (scan_data_5 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[0]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_4 )); // Templated
/* bw_u1_soffasr_2x AUTO_TEMPLATE (
.q (cken_out[@] ),
.d (cken_in[@] ),
.ck (clk ),
.r_l (agrst_l ),
.s_l (1'b1),
.se (1'b0),
.sd (1'b0),
.so (),
); */
bw_u1_soffasr_2x cken_ff_25_
( /*AUTOINST*/
// Outputs
.q (cken_out[25] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[25] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_24_
( /*AUTOINST*/
// Outputs
.q (cken_out[24] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[24] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_23_
( /*AUTOINST*/
// Outputs
.q (cken_out[23] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[23] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_22_
( /*AUTOINST*/
// Outputs
.q (cken_out[22] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[22] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_21_
( /*AUTOINST*/
// Outputs
.q (cken_out[21] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[21] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_20_
( /*AUTOINST*/
// Outputs
.q (cken_out[20] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[20] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_19_
( /*AUTOINST*/
// Outputs
.q (cken_out[19] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[19] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_18_
( /*AUTOINST*/
// Outputs
.q (cken_out[18] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[18] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_17_
( /*AUTOINST*/
// Outputs
.q (cken_out[17] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[17] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_16_
( /*AUTOINST*/
// Outputs
.q (cken_out[16] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[16] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_15_
( /*AUTOINST*/
// Outputs
.q (cken_out[15] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[15] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_14_
( /*AUTOINST*/
// Outputs
.q (cken_out[14] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[14] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_13_
( /*AUTOINST*/
// Outputs
.q (cken_out[13] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[13] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_12_
( /*AUTOINST*/
// Outputs
.q (cken_out[12] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[12] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_11_
( /*AUTOINST*/
// Outputs
.q (cken_out[11] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[11] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_10_
( /*AUTOINST*/
// Outputs
.q (cken_out[10] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[10] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_9_
( /*AUTOINST*/
// Outputs
.q (cken_out[9] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[9] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_8_
( /*AUTOINST*/
// Outputs
.q (cken_out[8] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[8] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_7_
( /*AUTOINST*/
// Outputs
.q (cken_out[7] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[7] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_6_
( /*AUTOINST*/
// Outputs
.q (cken_out[6] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[6] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_5_
( /*AUTOINST*/
// Outputs
.q (cken_out[5] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[5] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_4_
( /*AUTOINST*/
// Outputs
.q (cken_out[4] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[4] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_3_
( /*AUTOINST*/
// Outputs
.q (cken_out[3] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[3] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_2_
( /*AUTOINST*/
// Outputs
.q (cken_out[2] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[2] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_1_
( /*AUTOINST*/
// Outputs
.q (cken_out[1] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[1] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_0_
( /*AUTOINST*/
// Outputs
.q (cken_out[0] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[0] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
/* bw_u1_soffasr_2x AUTO_TEMPLATE (
.ck (clk ),
.r_l (agrst_l ),
.s_l (1'b1),
.se (se ),
); */
bw_u1_soffasr_2x ddrsync1_ff
(
// Outputs
.q (ddrsync1_out ),
.so (scan_data_9 ),
// Inputs
.d (ddrsync1_in ),
.sd (scan_data_8 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x ddrsync2_ff
(
// Outputs
.q (ddrsync2_out ),
.so (scan_data_8 ),
// Inputs
.d (ddrsync2_in ),
.sd (scan_data_7 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x jbussync1_ff
(
// Outputs
.q (jbussync1_out ),
.so (scan_data_7 ),
// Inputs
.d (jbussync1_in ),
.sd (scan_data_6 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x jbussync2_ff
(
// Outputs
.q (jbussync2_out ),
.so (scan_data_6 ),
// Inputs
.d (jbussync2_in ),
.sd (scan_data_5 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x gdbginit_ff
(
// Outputs
.q (gdbginit_out ),
.so (scan_data_10 ),
// Inputs
.d (gdbginit_in ),
.sd (scan_data_9 ),
.r_l (adbginit_l),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x gclk_ff
(
// Outputs
.q (grst_out ),
.so (scan_data_11 ),
// Inputs
.d (grst_in ),
.sd (scan_data_10 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
/* bw_u1_scanlg_2x AUTO_TEMPLATE (
.sd (scan_data_11 ),
.ck (clk ),
); */
bw_u1_scanlg_2x scanout_latch
( /*AUTOINST*/
// Outputs
.so (so),
// Inputs
.sd (scan_data_11 ), // Templated
.ck (clk ), // Templated
.se (1'b1));
endmodule
// Local Variables:
// verilog-library-files:("../../../common/rtl/u1.behV" )
// End:
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (win64) Build 2018833 Wed Oct 4 19:58:22 MDT 2017
// Date : Fri Nov 17 14:49:55 2017
// Host : egk-pc running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top DemoInterconnect_axi_spi_master_1_0 -prefix
// DemoInterconnect_axi_spi_master_1_0_ DemoInterconnect_axi_spi_master_0_0_stub.v
// Design : DemoInterconnect_axi_spi_master_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a15tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_spi_master_v1_0,Vivado 2017.3" *)
module DemoInterconnect_axi_spi_master_1_0(m_spi_mosi, m_spi_miso, m_spi_ss, m_spi_sclk,
s00_axi_awaddr, s00_axi_awprot, s00_axi_awvalid, s00_axi_awready, s00_axi_wdata,
s00_axi_wstrb, s00_axi_wvalid, s00_axi_wready, s00_axi_bresp, s00_axi_bvalid,
s00_axi_bready, s00_axi_araddr, s00_axi_arprot, s00_axi_arvalid, s00_axi_arready,
s00_axi_rdata, s00_axi_rresp, s00_axi_rvalid, s00_axi_rready, s00_axi_aclk,
s00_axi_aresetn)
/* synthesis syn_black_box black_box_pad_pin="m_spi_mosi,m_spi_miso,m_spi_ss,m_spi_sclk,s00_axi_awaddr[3:0],s00_axi_awprot[2:0],s00_axi_awvalid,s00_axi_awready,s00_axi_wdata[31:0],s00_axi_wstrb[3:0],s00_axi_wvalid,s00_axi_wready,s00_axi_bresp[1:0],s00_axi_bvalid,s00_axi_bready,s00_axi_araddr[3:0],s00_axi_arprot[2:0],s00_axi_arvalid,s00_axi_arready,s00_axi_rdata[31:0],s00_axi_rresp[1:0],s00_axi_rvalid,s00_axi_rready,s00_axi_aclk,s00_axi_aresetn" */;
output m_spi_mosi;
input m_spi_miso;
output m_spi_ss;
output m_spi_sclk;
input [3:0]s00_axi_awaddr;
input [2:0]s00_axi_awprot;
input s00_axi_awvalid;
output s00_axi_awready;
input [31:0]s00_axi_wdata;
input [3:0]s00_axi_wstrb;
input s00_axi_wvalid;
output s00_axi_wready;
output [1:0]s00_axi_bresp;
output s00_axi_bvalid;
input s00_axi_bready;
input [3:0]s00_axi_araddr;
input [2:0]s00_axi_arprot;
input s00_axi_arvalid;
output s00_axi_arready;
output [31:0]s00_axi_rdata;
output [1:0]s00_axi_rresp;
output s00_axi_rvalid;
input s00_axi_rready;
input s00_axi_aclk;
input s00_axi_aresetn;
endmodule
|
//
// Generated by Bluespec Compiler, version 2021.07 (build 4cac6eb)
//
//
// Ports:
// Name I/O size props
// RDY_set_addr_map O 1 const
// slave_awready O 1 reg
// slave_wready O 1 reg
// slave_bvalid O 1 reg
// slave_bid O 16 reg
// slave_bresp O 2 reg
// slave_arready O 1 reg
// slave_rvalid O 1 reg
// slave_rid O 16 reg
// slave_rdata O 64 reg
// slave_rresp O 2 reg
// slave_rlast O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// set_addr_map_addr_base I 64 reg
// set_addr_map_addr_lim I 64 reg
// slave_awvalid I 1
// slave_awid I 16 reg
// slave_awaddr I 64 reg
// slave_awlen I 8 reg
// slave_awsize I 3 reg
// slave_awburst I 2 reg
// slave_awlock I 1 reg
// slave_awcache I 4 reg
// slave_awprot I 3 reg
// slave_awqos I 4 reg
// slave_awregion I 4 reg
// slave_wvalid I 1
// slave_wdata I 64 reg
// slave_wstrb I 8 reg
// slave_wlast I 1 reg
// slave_bready I 1
// slave_arvalid I 1
// slave_arid I 16 reg
// slave_araddr I 64 reg
// slave_arlen I 8 reg
// slave_arsize I 3 reg
// slave_arburst I 2 reg
// slave_arlock I 1 reg
// slave_arcache I 4 reg
// slave_arprot I 3 reg
// slave_arqos I 4 reg
// slave_arregion I 4 reg
// slave_rready I 1
// EN_set_addr_map I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkBoot_ROM(CLK,
RST_N,
set_addr_map_addr_base,
set_addr_map_addr_lim,
EN_set_addr_map,
RDY_set_addr_map,
slave_awvalid,
slave_awid,
slave_awaddr,
slave_awlen,
slave_awsize,
slave_awburst,
slave_awlock,
slave_awcache,
slave_awprot,
slave_awqos,
slave_awregion,
slave_awready,
slave_wvalid,
slave_wdata,
slave_wstrb,
slave_wlast,
slave_wready,
slave_bvalid,
slave_bid,
slave_bresp,
slave_bready,
slave_arvalid,
slave_arid,
slave_araddr,
slave_arlen,
slave_arsize,
slave_arburst,
slave_arlock,
slave_arcache,
slave_arprot,
slave_arqos,
slave_arregion,
slave_arready,
slave_rvalid,
slave_rid,
slave_rdata,
slave_rresp,
slave_rlast,
slave_rready);
input CLK;
input RST_N;
// action method set_addr_map
input [63 : 0] set_addr_map_addr_base;
input [63 : 0] set_addr_map_addr_lim;
input EN_set_addr_map;
output RDY_set_addr_map;
// action method slave_m_awvalid
input slave_awvalid;
input [15 : 0] slave_awid;
input [63 : 0] slave_awaddr;
input [7 : 0] slave_awlen;
input [2 : 0] slave_awsize;
input [1 : 0] slave_awburst;
input slave_awlock;
input [3 : 0] slave_awcache;
input [2 : 0] slave_awprot;
input [3 : 0] slave_awqos;
input [3 : 0] slave_awregion;
// value method slave_m_awready
output slave_awready;
// action method slave_m_wvalid
input slave_wvalid;
input [63 : 0] slave_wdata;
input [7 : 0] slave_wstrb;
input slave_wlast;
// value method slave_m_wready
output slave_wready;
// value method slave_m_bvalid
output slave_bvalid;
// value method slave_m_bid
output [15 : 0] slave_bid;
// value method slave_m_bresp
output [1 : 0] slave_bresp;
// value method slave_m_buser
// action method slave_m_bready
input slave_bready;
// action method slave_m_arvalid
input slave_arvalid;
input [15 : 0] slave_arid;
input [63 : 0] slave_araddr;
input [7 : 0] slave_arlen;
input [2 : 0] slave_arsize;
input [1 : 0] slave_arburst;
input slave_arlock;
input [3 : 0] slave_arcache;
input [2 : 0] slave_arprot;
input [3 : 0] slave_arqos;
input [3 : 0] slave_arregion;
// value method slave_m_arready
output slave_arready;
// value method slave_m_rvalid
output slave_rvalid;
// value method slave_m_rid
output [15 : 0] slave_rid;
// value method slave_m_rdata
output [63 : 0] slave_rdata;
// value method slave_m_rresp
output [1 : 0] slave_rresp;
// value method slave_m_rlast
output slave_rlast;
// value method slave_m_ruser
// action method slave_m_rready
input slave_rready;
// signals for module outputs
wire [63 : 0] slave_rdata;
wire [15 : 0] slave_bid, slave_rid;
wire [1 : 0] slave_bresp, slave_rresp;
wire RDY_set_addr_map,
slave_arready,
slave_awready,
slave_bvalid,
slave_rlast,
slave_rvalid,
slave_wready;
// register rg_addr_base
reg [63 : 0] rg_addr_base;
wire [63 : 0] rg_addr_base$D_IN;
wire rg_addr_base$EN;
// register rg_addr_lim
reg [63 : 0] rg_addr_lim;
wire [63 : 0] rg_addr_lim$D_IN;
wire rg_addr_lim$EN;
// register rg_module_ready
reg rg_module_ready;
wire rg_module_ready$D_IN, rg_module_ready$EN;
// ports of submodule slave_xactor_f_rd_addr
wire [108 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT;
wire slave_xactor_f_rd_addr$CLR,
slave_xactor_f_rd_addr$DEQ,
slave_xactor_f_rd_addr$EMPTY_N,
slave_xactor_f_rd_addr$ENQ,
slave_xactor_f_rd_addr$FULL_N;
// ports of submodule slave_xactor_f_rd_data
wire [82 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT;
wire slave_xactor_f_rd_data$CLR,
slave_xactor_f_rd_data$DEQ,
slave_xactor_f_rd_data$EMPTY_N,
slave_xactor_f_rd_data$ENQ,
slave_xactor_f_rd_data$FULL_N;
// ports of submodule slave_xactor_f_wr_addr
wire [108 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT;
wire slave_xactor_f_wr_addr$CLR,
slave_xactor_f_wr_addr$DEQ,
slave_xactor_f_wr_addr$EMPTY_N,
slave_xactor_f_wr_addr$ENQ,
slave_xactor_f_wr_addr$FULL_N;
// ports of submodule slave_xactor_f_wr_data
wire [72 : 0] slave_xactor_f_wr_data$D_IN;
wire slave_xactor_f_wr_data$CLR,
slave_xactor_f_wr_data$DEQ,
slave_xactor_f_wr_data$EMPTY_N,
slave_xactor_f_wr_data$ENQ,
slave_xactor_f_wr_data$FULL_N;
// ports of submodule slave_xactor_f_wr_resp
wire [17 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT;
wire slave_xactor_f_wr_resp$CLR,
slave_xactor_f_wr_resp$DEQ,
slave_xactor_f_wr_resp$EMPTY_N,
slave_xactor_f_wr_resp$ENQ,
slave_xactor_f_wr_resp$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_rl_process_rd_req,
CAN_FIRE_RL_rl_process_wr_req,
CAN_FIRE_set_addr_map,
CAN_FIRE_slave_m_arvalid,
CAN_FIRE_slave_m_awvalid,
CAN_FIRE_slave_m_bready,
CAN_FIRE_slave_m_rready,
CAN_FIRE_slave_m_wvalid,
WILL_FIRE_RL_rl_process_rd_req,
WILL_FIRE_RL_rl_process_wr_req,
WILL_FIRE_set_addr_map,
WILL_FIRE_slave_m_arvalid,
WILL_FIRE_slave_m_awvalid,
WILL_FIRE_slave_m_bready,
WILL_FIRE_slave_m_rready,
WILL_FIRE_slave_m_wvalid;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h889;
reg [31 : 0] v__h6517;
reg [31 : 0] v__h6810;
reg [31 : 0] v__h6916;
reg [31 : 0] v__h883;
reg [31 : 0] v__h6511;
reg [31 : 0] v__h6804;
reg [31 : 0] v__h6910;
// synopsys translate_on
// remaining internal signals
reg [63 : 0] data64__h1057;
reg [31 : 0] CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2,
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3;
reg CASE_slave_xactor_f_rd_addrD_OUT_BITS_20_TO_1_ETC__q4,
CASE_slave_xactor_f_wr_addrD_OUT_BITS_20_TO_1_ETC__q5;
wire [63 : 0] rdata__h1019,
slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_MIN_ETC__q1;
wire [1 : 0] rdr_rresp__h1046;
wire NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33,
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248;
// action method set_addr_map
assign RDY_set_addr_map = 1'd1 ;
assign CAN_FIRE_set_addr_map = 1'd1 ;
assign WILL_FIRE_set_addr_map = EN_set_addr_map ;
// action method slave_m_awvalid
assign CAN_FIRE_slave_m_awvalid = 1'd1 ;
assign WILL_FIRE_slave_m_awvalid = 1'd1 ;
// value method slave_m_awready
assign slave_awready = slave_xactor_f_wr_addr$FULL_N ;
// action method slave_m_wvalid
assign CAN_FIRE_slave_m_wvalid = 1'd1 ;
assign WILL_FIRE_slave_m_wvalid = 1'd1 ;
// value method slave_m_wready
assign slave_wready = slave_xactor_f_wr_data$FULL_N ;
// value method slave_m_bvalid
assign slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ;
// value method slave_m_bid
assign slave_bid = slave_xactor_f_wr_resp$D_OUT[17:2] ;
// value method slave_m_bresp
assign slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ;
// action method slave_m_bready
assign CAN_FIRE_slave_m_bready = 1'd1 ;
assign WILL_FIRE_slave_m_bready = 1'd1 ;
// action method slave_m_arvalid
assign CAN_FIRE_slave_m_arvalid = 1'd1 ;
assign WILL_FIRE_slave_m_arvalid = 1'd1 ;
// value method slave_m_arready
assign slave_arready = slave_xactor_f_rd_addr$FULL_N ;
// value method slave_m_rvalid
assign slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ;
// value method slave_m_rid
assign slave_rid = slave_xactor_f_rd_data$D_OUT[82:67] ;
// value method slave_m_rdata
assign slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ;
// value method slave_m_rresp
assign slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ;
// value method slave_m_rlast
assign slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ;
// action method slave_m_rready
assign CAN_FIRE_slave_m_rready = 1'd1 ;
assign WILL_FIRE_slave_m_rready = 1'd1 ;
// submodule slave_xactor_f_rd_addr
FIFO2 #(.width(32'd109), .guarded(1'd1)) slave_xactor_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(slave_xactor_f_rd_addr$D_IN),
.ENQ(slave_xactor_f_rd_addr$ENQ),
.DEQ(slave_xactor_f_rd_addr$DEQ),
.CLR(slave_xactor_f_rd_addr$CLR),
.D_OUT(slave_xactor_f_rd_addr$D_OUT),
.FULL_N(slave_xactor_f_rd_addr$FULL_N),
.EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N));
// submodule slave_xactor_f_rd_data
FIFO2 #(.width(32'd83), .guarded(1'd1)) slave_xactor_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(slave_xactor_f_rd_data$D_IN),
.ENQ(slave_xactor_f_rd_data$ENQ),
.DEQ(slave_xactor_f_rd_data$DEQ),
.CLR(slave_xactor_f_rd_data$CLR),
.D_OUT(slave_xactor_f_rd_data$D_OUT),
.FULL_N(slave_xactor_f_rd_data$FULL_N),
.EMPTY_N(slave_xactor_f_rd_data$EMPTY_N));
// submodule slave_xactor_f_wr_addr
FIFO2 #(.width(32'd109), .guarded(1'd1)) slave_xactor_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(slave_xactor_f_wr_addr$D_IN),
.ENQ(slave_xactor_f_wr_addr$ENQ),
.DEQ(slave_xactor_f_wr_addr$DEQ),
.CLR(slave_xactor_f_wr_addr$CLR),
.D_OUT(slave_xactor_f_wr_addr$D_OUT),
.FULL_N(slave_xactor_f_wr_addr$FULL_N),
.EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N));
// submodule slave_xactor_f_wr_data
FIFO2 #(.width(32'd73), .guarded(1'd1)) slave_xactor_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(slave_xactor_f_wr_data$D_IN),
.ENQ(slave_xactor_f_wr_data$ENQ),
.DEQ(slave_xactor_f_wr_data$DEQ),
.CLR(slave_xactor_f_wr_data$CLR),
.D_OUT(),
.FULL_N(slave_xactor_f_wr_data$FULL_N),
.EMPTY_N(slave_xactor_f_wr_data$EMPTY_N));
// submodule slave_xactor_f_wr_resp
FIFO2 #(.width(32'd18), .guarded(1'd1)) slave_xactor_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(slave_xactor_f_wr_resp$D_IN),
.ENQ(slave_xactor_f_wr_resp$ENQ),
.DEQ(slave_xactor_f_wr_resp$DEQ),
.CLR(slave_xactor_f_wr_resp$CLR),
.D_OUT(slave_xactor_f_wr_resp$D_OUT),
.FULL_N(slave_xactor_f_wr_resp$FULL_N),
.EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N));
// rule RL_rl_process_rd_req
assign CAN_FIRE_RL_rl_process_rd_req =
slave_xactor_f_rd_addr$EMPTY_N &&
slave_xactor_f_rd_data$FULL_N &&
rg_module_ready ;
assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ;
// rule RL_rl_process_wr_req
assign CAN_FIRE_RL_rl_process_wr_req =
slave_xactor_f_wr_addr$EMPTY_N &&
slave_xactor_f_wr_data$EMPTY_N &&
slave_xactor_f_wr_resp$FULL_N &&
rg_module_ready ;
assign WILL_FIRE_RL_rl_process_wr_req = CAN_FIRE_RL_rl_process_wr_req ;
// register rg_addr_base
assign rg_addr_base$D_IN = set_addr_map_addr_base ;
assign rg_addr_base$EN = EN_set_addr_map ;
// register rg_addr_lim
assign rg_addr_lim$D_IN = set_addr_map_addr_lim ;
assign rg_addr_lim$EN = EN_set_addr_map ;
// register rg_module_ready
assign rg_module_ready$D_IN = 1'd1 ;
assign rg_module_ready$EN = EN_set_addr_map ;
// submodule slave_xactor_f_rd_addr
assign slave_xactor_f_rd_addr$D_IN =
{ slave_arid,
slave_araddr,
slave_arlen,
slave_arsize,
slave_arburst,
slave_arlock,
slave_arcache,
slave_arprot,
slave_arqos,
slave_arregion } ;
assign slave_xactor_f_rd_addr$ENQ =
slave_arvalid && slave_xactor_f_rd_addr$FULL_N ;
assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_process_rd_req ;
assign slave_xactor_f_rd_addr$CLR = 1'b0 ;
// submodule slave_xactor_f_rd_data
assign slave_xactor_f_rd_data$D_IN =
{ slave_xactor_f_rd_addr$D_OUT[108:93],
rdata__h1019,
rdr_rresp__h1046,
1'd1 } ;
assign slave_xactor_f_rd_data$ENQ = CAN_FIRE_RL_rl_process_rd_req ;
assign slave_xactor_f_rd_data$DEQ =
slave_rready && slave_xactor_f_rd_data$EMPTY_N ;
assign slave_xactor_f_rd_data$CLR = 1'b0 ;
// submodule slave_xactor_f_wr_addr
assign slave_xactor_f_wr_addr$D_IN =
{ slave_awid,
slave_awaddr,
slave_awlen,
slave_awsize,
slave_awburst,
slave_awlock,
slave_awcache,
slave_awprot,
slave_awqos,
slave_awregion } ;
assign slave_xactor_f_wr_addr$ENQ =
slave_awvalid && slave_xactor_f_wr_addr$FULL_N ;
assign slave_xactor_f_wr_addr$DEQ = CAN_FIRE_RL_rl_process_wr_req ;
assign slave_xactor_f_wr_addr$CLR = 1'b0 ;
// submodule slave_xactor_f_wr_data
assign slave_xactor_f_wr_data$D_IN =
{ slave_wdata, slave_wstrb, slave_wlast } ;
assign slave_xactor_f_wr_data$ENQ =
slave_wvalid && slave_xactor_f_wr_data$FULL_N ;
assign slave_xactor_f_wr_data$DEQ = CAN_FIRE_RL_rl_process_wr_req ;
assign slave_xactor_f_wr_data$CLR = 1'b0 ;
// submodule slave_xactor_f_wr_resp
assign slave_xactor_f_wr_resp$D_IN =
{ slave_xactor_f_wr_addr$D_OUT[108:93],
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248 ?
2'b10 :
2'b0 } ;
assign slave_xactor_f_wr_resp$ENQ = CAN_FIRE_RL_rl_process_wr_req ;
assign slave_xactor_f_wr_resp$DEQ =
slave_bready && slave_xactor_f_wr_resp$EMPTY_N ;
assign slave_xactor_f_wr_resp$CLR = 1'b0 ;
// remaining internal signals
assign NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33 =
slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b0 &&
CASE_slave_xactor_f_rd_addrD_OUT_BITS_20_TO_1_ETC__q4 ||
rg_addr_base > slave_xactor_f_rd_addr$D_OUT[92:29] ||
slave_xactor_f_rd_addr$D_OUT[92:29] >= rg_addr_lim ;
assign NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248 =
slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b0 &&
CASE_slave_xactor_f_wr_addrD_OUT_BITS_20_TO_1_ETC__q5 ||
rg_addr_base > slave_xactor_f_wr_addr$D_OUT[92:29] ||
slave_xactor_f_wr_addr$D_OUT[92:29] >= rg_addr_lim ;
assign rdata__h1019 =
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33 ?
64'd0 :
data64__h1057 ;
assign rdr_rresp__h1046 =
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33 ?
2'b10 :
2'b0 ;
assign slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_MIN_ETC__q1 =
slave_xactor_f_rd_addr$D_OUT[92:29] - rg_addr_base ;
always@(slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_MIN_ETC__q1)
begin
case (slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_MIN_ETC__q1[63:3])
61'd2,
61'd3,
61'd7,
61'd9,
61'd10,
61'd11,
61'd25,
61'd29,
61'd39,
61'd53,
61'd56,
61'd75,
61'd91,
61'd142,
61'd143,
61'd144,
61'd145,
61'd146,
61'd147,
61'd148,
61'd149,
61'd150,
61'd151,
61'd152,
61'd153,
61'd154,
61'd155,
61'd156,
61'd157,
61'd158,
61'd159,
61'd160,
61'd161,
61'd162,
61'd163,
61'd164,
61'd165,
61'd166,
61'd167,
61'd168,
61'd169,
61'd170,
61'd171,
61'd172,
61'd173,
61'd174,
61'd175,
61'd176,
61'd177,
61'd178,
61'd179,
61'd180,
61'd181,
61'd182,
61'd183,
61'd184,
61'd185,
61'd186,
61'd187,
61'd188,
61'd189,
61'd190,
61'd191,
61'd192,
61'd193,
61'd194,
61'd195,
61'd196,
61'd197,
61'd198,
61'd199,
61'd200,
61'd201,
61'd202,
61'd203,
61'd204,
61'd205,
61'd206,
61'd207,
61'd208,
61'd209,
61'd210,
61'd211,
61'd212,
61'd213,
61'd214,
61'd215,
61'd216,
61'd217,
61'd218,
61'd219,
61'd220,
61'd221,
61'd222,
61'd223,
61'd224,
61'd225,
61'd226,
61'd227,
61'd228,
61'd229,
61'd230,
61'd231,
61'd232,
61'd233,
61'd234,
61'd235,
61'd236,
61'd237,
61'd238,
61'd239,
61'd240,
61'd241,
61'd242,
61'd243,
61'd244,
61'd245,
61'd246,
61'd247,
61'd248,
61'd249,
61'd250,
61'd251,
61'd252,
61'd253,
61'd254,
61'd255,
61'd256,
61'd257,
61'd258,
61'd259,
61'd260,
61'd261,
61'd262,
61'd263,
61'd264,
61'd265,
61'd266,
61'd267,
61'd268,
61'd269,
61'd270,
61'd271,
61'd272,
61'd273,
61'd274,
61'd275,
61'd276,
61'd277,
61'd278,
61'd279,
61'd280,
61'd281,
61'd282,
61'd283,
61'd284,
61'd285,
61'd286,
61'd287,
61'd288,
61'd289,
61'd290,
61'd291,
61'd292,
61'd293,
61'd294,
61'd295,
61'd296,
61'd297,
61'd298,
61'd299,
61'd300,
61'd301,
61'd302,
61'd303,
61'd304,
61'd305,
61'd306,
61'd307,
61'd308,
61'd309,
61'd310,
61'd311,
61'd312,
61'd313,
61'd314,
61'd315,
61'd316,
61'd317,
61'd318,
61'd319,
61'd320,
61'd321,
61'd322,
61'd323,
61'd324,
61'd325,
61'd326,
61'd327,
61'd328,
61'd329,
61'd330,
61'd331,
61'd332,
61'd333,
61'd334,
61'd335,
61'd336,
61'd337,
61'd338,
61'd339,
61'd340,
61'd341,
61'd342,
61'd343,
61'd344,
61'd345,
61'd346,
61'd347,
61'd348,
61'd349,
61'd350,
61'd351,
61'd352,
61'd353,
61'd354,
61'd355,
61'd356,
61'd357,
61'd358,
61'd359,
61'd360,
61'd361,
61'd362,
61'd363,
61'd364,
61'd365,
61'd366,
61'd367,
61'd368,
61'd369,
61'd370,
61'd371,
61'd372,
61'd373,
61'd374,
61'd375,
61'd376,
61'd377,
61'd378,
61'd379,
61'd380,
61'd381,
61'd382,
61'd383,
61'd384,
61'd385,
61'd386,
61'd387,
61'd388,
61'd389,
61'd390,
61'd391,
61'd392,
61'd393,
61'd394,
61'd395,
61'd396,
61'd397,
61'd398,
61'd399,
61'd400,
61'd401,
61'd402,
61'd403,
61'd404,
61'd405,
61'd406,
61'd407,
61'd408,
61'd409,
61'd410,
61'd411,
61'd412,
61'd413,
61'd414,
61'd415,
61'd416,
61'd417,
61'd418,
61'd419,
61'd420,
61'd421,
61'd422,
61'd423,
61'd424,
61'd425,
61'd426,
61'd427,
61'd428,
61'd429,
61'd430,
61'd431,
61'd432,
61'd433,
61'd434,
61'd435,
61'd436,
61'd437,
61'd438,
61'd439,
61'd440,
61'd441,
61'd442,
61'd443,
61'd444,
61'd445,
61'd446,
61'd447,
61'd448,
61'd449,
61'd450,
61'd451,
61'd452,
61'd453,
61'd454,
61'd455,
61'd456,
61'd457,
61'd458,
61'd459,
61'd460,
61'd461,
61'd462,
61'd463,
61'd464,
61'd465,
61'd466,
61'd467,
61'd468,
61'd469,
61'd470,
61'd471,
61'd472,
61'd473,
61'd474,
61'd475,
61'd476,
61'd477,
61'd478,
61'd479,
61'd480,
61'd481,
61'd482,
61'd483,
61'd484,
61'd485,
61'd486,
61'd487,
61'd488,
61'd489,
61'd490,
61'd491,
61'd492,
61'd493,
61'd494,
61'd495,
61'd496,
61'd497,
61'd498,
61'd499,
61'd500,
61'd501,
61'd502,
61'd503,
61'd504,
61'd505,
61'd506,
61'd507,
61'd508,
61'd509,
61'd510,
61'd511:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 = 32'h0;
61'd4:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h54040000;
61'd5:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h88030000;
61'd6:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h11000000;
61'd8:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h50030000;
61'd12,
61'd14,
61'd26,
61'd28,
61'd30,
61'd54,
61'd61,
61'd109,
61'd111:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h04000000;
61'd13, 61'd15, 61'd63, 61'd99, 61'd115:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h02000000;
61'd16:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h16000000;
61'd17:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h62626375;
61'd18:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h656B6970;
61'd19:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h65642D65;
61'd20,
61'd33,
61'd35,
61'd37,
61'd42,
61'd45,
61'd48,
61'd57,
61'd69,
61'd74,
61'd76,
61'd78,
61'd84,
61'd88,
61'd95,
61'd102,
61'd105,
61'd110:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h03000000;
61'd21:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h26000000;
61'd22, 61'd80:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h732C7261;
61'd23, 61'd81:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h7261622D;
61'd24,
61'd27,
61'd50,
61'd55,
61'd62,
61'd64,
61'd73,
61'd93,
61'd94,
61'd114:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h01000000;
61'd31, 61'd112:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h80969800;
61'd32:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h40757063;
61'd34:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h3F000000;
61'd36, 61'd70, 61'd96, 61'd106:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h4B000000;
61'd38:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h4F000000;
61'd40:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h06000000;
61'd41:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h63736972;
61'd43:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h56000000;
61'd44:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h75616D69;
61'd46:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h60000000;
61'd47:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h76732C76;
61'd49:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h69000000;
61'd51:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h70757272;
61'd52:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h6F72746E;
61'd58, 61'd79, 61'd89, 61'd103:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h1B000000;
61'd59:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h70632C76;
61'd60:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h00006374;
61'd65:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h38407972;
61'd66:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h00303030;
61'd67:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h07000000;
61'd68:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h6F6D656D;
61'd71:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h00000080;
61'd72:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h00000010;
61'd77:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h0F000000;
61'd82:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h69730063;
61'd83:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h7375622D;
61'd85:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'hA7000000;
61'd86:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h6E696C63;
61'd87, 61'd101:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h30303030;
61'd90:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h6C632C76;
61'd92:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h10000000;
61'd97:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h00000002;
61'd98:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h00000C00;
61'd100:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h74726175;
61'd104:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h61303535;
61'd107:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h000000C0;
61'd108:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h40000000;
61'd113:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h08000000;
61'd116:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h09000000;
61'd117:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h73736572;
61'd118:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h2300736C;
61'd119:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h6C65632D;
61'd120:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h61706D6F;
61'd121:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h6F6D0065;
61'd122:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h656D6974;
61'd123:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h6572662D;
61'd124:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h64007963;
61'd125:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h79745F65;
61'd126:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h73006765;
61'd127:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h69720073;
61'd128:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h00617369;
61'd129:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h65707974;
61'd130:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h662D6B63;
61'd131:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h79636E65;
61'd132, 61'd134:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h72726574;
61'd133:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h6C6C6563;
61'd135:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h746E6F63;
61'd136:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h70007265;
61'd137:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h7200656C;
61'd138:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h6E690073;
61'd139:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h73747075;
61'd140:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h65646E65;
61'd141:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'h68732D67;
default: CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 =
32'hAAAAAAAA;
endcase
end
always@(slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_MIN_ETC__q1)
begin
case (slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_MIN_ETC__q1[63:3])
61'd2:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h00028067;
61'd3:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h80000000;
61'd4:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'hEDFE0DD0;
61'd5:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h38000000;
61'd6:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h28000000;
61'd7, 61'd70, 61'd96, 61'd106:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h10000000;
61'd8:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'hCC000000;
61'd9,
61'd10,
61'd13,
61'd27,
61'd37,
61'd71,
61'd72,
61'd84,
61'd85,
61'd97,
61'd98,
61'd105,
61'd107,
61'd108,
61'd143,
61'd144,
61'd145,
61'd146,
61'd147,
61'd148,
61'd149,
61'd150,
61'd151,
61'd152,
61'd153,
61'd154,
61'd155,
61'd156,
61'd157,
61'd158,
61'd159,
61'd160,
61'd161,
61'd162,
61'd163,
61'd164,
61'd165,
61'd166,
61'd167,
61'd168,
61'd169,
61'd170,
61'd171,
61'd172,
61'd173,
61'd174,
61'd175,
61'd176,
61'd177,
61'd178,
61'd179,
61'd180,
61'd181,
61'd182,
61'd183,
61'd184,
61'd185,
61'd186,
61'd187,
61'd188,
61'd189,
61'd190,
61'd191,
61'd192,
61'd193,
61'd194,
61'd195,
61'd196,
61'd197,
61'd198,
61'd199,
61'd200,
61'd201,
61'd202,
61'd203,
61'd204,
61'd205,
61'd206,
61'd207,
61'd208,
61'd209,
61'd210,
61'd211,
61'd212,
61'd213,
61'd214,
61'd215,
61'd216,
61'd217,
61'd218,
61'd219,
61'd220,
61'd221,
61'd222,
61'd223,
61'd224,
61'd225,
61'd226,
61'd227,
61'd228,
61'd229,
61'd230,
61'd231,
61'd232,
61'd233,
61'd234,
61'd235,
61'd236,
61'd237,
61'd238,
61'd239,
61'd240,
61'd241,
61'd242,
61'd243,
61'd244,
61'd245,
61'd246,
61'd247,
61'd248,
61'd249,
61'd250,
61'd251,
61'd252,
61'd253,
61'd254,
61'd255,
61'd256,
61'd257,
61'd258,
61'd259,
61'd260,
61'd261,
61'd262,
61'd263,
61'd264,
61'd265,
61'd266,
61'd267,
61'd268,
61'd269,
61'd270,
61'd271,
61'd272,
61'd273,
61'd274,
61'd275,
61'd276,
61'd277,
61'd278,
61'd279,
61'd280,
61'd281,
61'd282,
61'd283,
61'd284,
61'd285,
61'd286,
61'd287,
61'd288,
61'd289,
61'd290,
61'd291,
61'd292,
61'd293,
61'd294,
61'd295,
61'd296,
61'd297,
61'd298,
61'd299,
61'd300,
61'd301,
61'd302,
61'd303,
61'd304,
61'd305,
61'd306,
61'd307,
61'd308,
61'd309,
61'd310,
61'd311,
61'd312,
61'd313,
61'd314,
61'd315,
61'd316,
61'd317,
61'd318,
61'd319,
61'd320,
61'd321,
61'd322,
61'd323,
61'd324,
61'd325,
61'd326,
61'd327,
61'd328,
61'd329,
61'd330,
61'd331,
61'd332,
61'd333,
61'd334,
61'd335,
61'd336,
61'd337,
61'd338,
61'd339,
61'd340,
61'd341,
61'd342,
61'd343,
61'd344,
61'd345,
61'd346,
61'd347,
61'd348,
61'd349,
61'd350,
61'd351,
61'd352,
61'd353,
61'd354,
61'd355,
61'd356,
61'd357,
61'd358,
61'd359,
61'd360,
61'd361,
61'd362,
61'd363,
61'd364,
61'd365,
61'd366,
61'd367,
61'd368,
61'd369,
61'd370,
61'd371,
61'd372,
61'd373,
61'd374,
61'd375,
61'd376,
61'd377,
61'd378,
61'd379,
61'd380,
61'd381,
61'd382,
61'd383,
61'd384,
61'd385,
61'd386,
61'd387,
61'd388,
61'd389,
61'd390,
61'd391,
61'd392,
61'd393,
61'd394,
61'd395,
61'd396,
61'd397,
61'd398,
61'd399,
61'd400,
61'd401,
61'd402,
61'd403,
61'd404,
61'd405,
61'd406,
61'd407,
61'd408,
61'd409,
61'd410,
61'd411,
61'd412,
61'd413,
61'd414,
61'd415,
61'd416,
61'd417,
61'd418,
61'd419,
61'd420,
61'd421,
61'd422,
61'd423,
61'd424,
61'd425,
61'd426,
61'd427,
61'd428,
61'd429,
61'd430,
61'd431,
61'd432,
61'd433,
61'd434,
61'd435,
61'd436,
61'd437,
61'd438,
61'd439,
61'd440,
61'd441,
61'd442,
61'd443,
61'd444,
61'd445,
61'd446,
61'd447,
61'd448,
61'd449,
61'd450,
61'd451,
61'd452,
61'd453,
61'd454,
61'd455,
61'd456,
61'd457,
61'd458,
61'd459,
61'd460,
61'd461,
61'd462,
61'd463,
61'd464,
61'd465,
61'd466,
61'd467,
61'd468,
61'd469,
61'd470,
61'd471,
61'd472,
61'd473,
61'd474,
61'd475,
61'd476,
61'd477,
61'd478,
61'd479,
61'd480,
61'd481,
61'd482,
61'd483,
61'd484,
61'd485,
61'd486,
61'd487,
61'd488,
61'd489,
61'd490,
61'd491,
61'd492,
61'd493,
61'd494,
61'd495,
61'd496,
61'd497,
61'd498,
61'd499,
61'd500,
61'd501,
61'd502,
61'd503,
61'd504,
61'd505,
61'd506,
61'd507,
61'd508,
61'd509,
61'd510,
61'd511:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 = 32'h0;
61'd11, 61'd32, 61'd86, 61'd100:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h01000000;
61'd12,
61'd14,
61'd16,
61'd26,
61'd28,
61'd30,
61'd40,
61'd54,
61'd56,
61'd61,
61'd67,
61'd92,
61'd94,
61'd109,
61'd111,
61'd113:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h03000000;
61'd15, 61'd29, 61'd58:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h0F000000;
61'd17, 61'd41:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h1B000000;
61'd18:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h732C7261;
61'd19:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h7261622D;
61'd20, 61'd42:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h00000076;
61'd21:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h12000000;
61'd22, 61'd80:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h62626375;
61'd23, 61'd81:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h656B6970;
61'd24:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h00000065;
61'd25:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h73757063;
61'd31:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h2C000000;
61'd33, 61'd88, 61'd102:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h00000030;
61'd34, 61'd36, 61'd49, 61'd75, 61'd77:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h04000000;
61'd35:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h00757063;
61'd38:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h05000000;
61'd39:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h79616B6F;
61'd43:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h0A000000;
61'd44:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h34367672;
61'd45:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h00000073;
61'd46, 61'd115:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h0B000000;
61'd47, 61'd59, 61'd90:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h63736972;
61'd48:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h00003933;
61'd50:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h80969800;
61'd51:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h65746E69;
61'd52:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h6F632D74;
61'd53:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h72656C6C;
61'd55:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h79000000;
61'd57:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h8A000000;
61'd60:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h6E692D75;
61'd62:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h9F000000;
61'd63, 61'd64, 61'd73, 61'd76, 61'd78, 61'd99, 61'd116:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h02000000;
61'd65:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h6F6D656D;
61'd66:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h30303030;
61'd68:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h3F000000;
61'd69:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h00007972;
61'd74:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h00636F73;
61'd79:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h21000000;
61'd82:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h6F732D65;
61'd83:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h656C706D;
61'd87:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h30324074;
61'd89:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h0D000000;
61'd91:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h30746E69;
61'd93, 61'd114:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'hAE000000;
61'd95:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h07000000;
61'd101:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h30306340;
61'd103:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h09000000;
61'd104:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h3631736E;
61'd110:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'hC2000000;
61'd112:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h69000000;
61'd117:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h64646123;
61'd118:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h6C65632D;
61'd119:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h657A6973;
61'd120:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h6300736C;
61'd121:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h6C626974;
61'd122:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h006C6564;
61'd123:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h65736162;
61'd124:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h6E657571;
61'd125:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h63697665;
61'd126:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h72006570;
61'd127:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h75746174;
61'd128:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h2C766373;
61'd129:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h2D756D6D;
61'd130:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h6F6C6300;
61'd131:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h75716572;
61'd132:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h6E692300;
61'd133, 61'd135:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h2D747075;
61'd134:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h6E690073;
61'd136:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h6C6C6F72;
61'd137:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h646E6168;
61'd138:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h65676E61;
61'd139:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h72726574;
61'd140:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h7478652D;
61'd141:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h65720064;
61'd142:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'h00746669;
default: CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 =
32'hAAAAAAAA;
endcase
end
always@(slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_MIN_ETC__q1 or
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2 or
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3)
begin
case (slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_MIN_ETC__q1[63:3])
61'd0: data64__h1057 = 64'h0202859300000297;
61'd1: data64__h1057 = 64'h0182B283F1402573;
default: data64__h1057 =
{ CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q2,
CASE_slave_xactor_f_rd_addrD_OUT_BITS_92_TO_29_ETC__q3 };
endcase
end
always@(slave_xactor_f_rd_addr$D_OUT)
begin
case (slave_xactor_f_rd_addr$D_OUT[20:18])
3'b001:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_20_TO_1_ETC__q4 =
slave_xactor_f_rd_addr$D_OUT[29];
3'b010:
CASE_slave_xactor_f_rd_addrD_OUT_BITS_20_TO_1_ETC__q4 =
slave_xactor_f_rd_addr$D_OUT[30:29] != 2'b0;
default: CASE_slave_xactor_f_rd_addrD_OUT_BITS_20_TO_1_ETC__q4 =
slave_xactor_f_rd_addr$D_OUT[20:18] != 3'b011 ||
slave_xactor_f_rd_addr$D_OUT[31:29] != 3'b0;
endcase
end
always@(slave_xactor_f_wr_addr$D_OUT)
begin
case (slave_xactor_f_wr_addr$D_OUT[20:18])
3'b001:
CASE_slave_xactor_f_wr_addrD_OUT_BITS_20_TO_1_ETC__q5 =
slave_xactor_f_wr_addr$D_OUT[29];
3'b010:
CASE_slave_xactor_f_wr_addrD_OUT_BITS_20_TO_1_ETC__q5 =
slave_xactor_f_wr_addr$D_OUT[30:29] != 2'b0;
default: CASE_slave_xactor_f_wr_addrD_OUT_BITS_20_TO_1_ETC__q5 =
slave_xactor_f_wr_addr$D_OUT[20:18] != 3'b011 ||
slave_xactor_f_wr_addr$D_OUT[31:29] != 3'b0;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
rg_module_ready <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (rg_module_ready$EN)
rg_module_ready <= `BSV_ASSIGNMENT_DELAY rg_module_ready$D_IN;
end
if (rg_addr_base$EN)
rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN;
if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
rg_addr_base = 64'hAAAAAAAAAAAAAAAA;
rg_addr_lim = 64'hAAAAAAAAAAAAAAAA;
rg_module_ready = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
begin
v__h889 = $stime;
#0;
end
v__h883 = v__h889 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$display("%0d: ERROR: Boot_ROM.rl_process_rd_req: unrecognized or misaligned addr",
v__h883);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req &&
NOT_slave_xactor_f_rd_addr_first_BITS_20_TO_18_ETC___d33)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
begin
v__h6517 = $stime;
#0;
end
v__h6511 = v__h6517 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$display("%0d: ERROR: Boot_ROM.rl_process_wr_req: unrecognized or misaligned addr",
v__h6511);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
NOT_slave_xactor_f_wr_addr_first__223_BITS_20__ETC___d1248)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0)
begin
v__h6810 = $stime;
#0;
end
v__h6804 = v__h6810 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (EN_set_addr_map && set_addr_map_addr_base[2:0] != 3'd0)
$display("%0d: WARNING: Boot_ROM.set_addr_map: addr_base 0x%0h is not 4-Byte-aligned",
v__h6804,
set_addr_map_addr_base);
if (RST_N != `BSV_RESET_VALUE)
if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0)
begin
v__h6916 = $stime;
#0;
end
v__h6910 = v__h6916 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (EN_set_addr_map && set_addr_map_addr_lim[2:0] != 3'd0)
$display("%0d: WARNING: Boot_ROM.set_addr_map: addr_lim 0x%0h is not 4-Byte-aligned",
v__h6910,
set_addr_map_addr_lim);
end
// synopsys translate_on
endmodule // mkBoot_ROM
|
(************************************************************************)
(* Copyright (c) 2010, Martijn Vermaat <[email protected]> *)
(* *)
(* Licensed under the MIT license, see the LICENSE file or *)
(* http://en.wikipedia.org/wiki/Mit_license *)
(************************************************************************)
(** This library defines substition of terms for variables in terms. *)
Require Export List.
Require Export FiniteTerm.
Require Export Term.
Require Import TermEquality.
Require Import Equality.
Set Implicit Arguments.
Section Substitution.
Variable F : signature.
Variable X : variables.
Notation term := (term F X).
Notation fterm := (finite_term F X).
(** A substitution is a function from variables to terms. *)
Definition substitution := X -> term.
(** Equality of substitutions on a list of variables. *)
Fixpoint substitution_eq (vars : list X) (sigma sigma' : substitution) :=
match vars with
| nil => True
| x :: xs => (substitution_eq xs sigma sigma') /\ (sigma x = sigma' x)
end.
(** Equality of substitutions on a list of variables is invariant under
list inclusion.
We have not yet proven this lemma. This taints the lemma [step_eq__target]
in [Rewriting]. *)
Lemma substitution_eq_incl :
forall sigma theta l l',
incl l' l ->
substitution_eq l sigma theta ->
substitution_eq l' sigma theta.
Proof.
intros sigma theta l l' H1 H2.
revert l' H1.
induction l as [| x l IH]; intros l' H1; simpl.
destruct l' as [| y l'].
exact I.
elim (H1 y).
left; reflexivity.
induction l' as [| y l' IH']; simpl.
exact I.
split.
apply IH'.
intros z H.
apply H1.
right.
assumption.
destruct (H1 y).
left; reflexivity.
rewrite H in H2.
apply H2.
simpl in H2.
(** This should not be too hard. (Problem is whether [x] is in [l']. *)
Admitted.
Lemma substitution_eq_app_left :
forall sigma theta l l',
substitution_eq (l ++ l') sigma theta ->
substitution_eq l sigma theta.
Proof.
intros sigma theta l l' H.
induction l as [| x l IH]; simpl.
exact I.
split.
apply IH.
apply H.
apply H.
Qed.
Lemma substitution_eq_app_right :
forall sigma theta l l',
substitution_eq (l ++ l') sigma theta ->
substitution_eq l' sigma theta.
Proof.
intros sigma theta l l' H.
induction l as [| x l IH]; simpl.
assumption.
apply IH.
apply H.
Qed.
Implicit Arguments substitution_eq_app_left [l l'].
Implicit Arguments substitution_eq_app_right [l l'].
(** We show [substitution_eq] is an equivalence. *)
Lemma substitution_eq_refl :
forall vars sigma, substitution_eq vars sigma sigma.
Proof.
induction vars; [simpl | split]; trivial.
Qed.
Lemma substitution_eq_symm :
forall vars sigma theta,
substitution_eq vars sigma theta ->
substitution_eq vars theta sigma.
Proof.
intros vars sigma theta H.
induction vars as [| x vars IH]; simpl.
exact I.
split.
apply IH.
apply H.
symmetry.
apply H.
Qed.
Lemma substitution_eq_trans :
forall vars sigma theta upsilon,
substitution_eq vars sigma theta ->
substitution_eq vars theta upsilon ->
substitution_eq vars sigma upsilon.
Proof.
intros vars sigma theta upsilon H1 H2.
induction vars as [| x vars IH]; simpl.
exact I.
split.
apply IH.
apply H1.
apply H2.
apply eq_trans with (theta x).
apply H1.
apply H2.
Qed.
(** The identity substitution. *)
Definition empty_substitution (x : X) : term := Var x.
(** We define two substitution functions. The first, [substitute], defines
substitution on finite terms. The second, [substitute'], defines
substitution on infinite terms.
In principle, [substitute'] works fine and is a generalisation of
[substitute]. However, it yields a (potentially) infinite term (of type
[term] instead of [finite_term]) and this makes it somewhat painful to
work with (corecursive definitions have to be manually unfolded in Coq).
Since we almost always apply substitutions on finite terms, we define
this seperately and provide the more general [substitute'] for
completeness. *)
(** Apply a substitution to a finite term. *)
Fixpoint substitute (sigma : substitution) (t : fterm) {struct t} : term :=
match t with
| FVar x => sigma x
| FFun f args => Fun f (vmap (substitute sigma) args)
end.
(** Applying the empty substitution to a finite term gives the trivial
infinite term image. The only reason we cannot prove coq-equality here
is equality on vectors. *)
Lemma empty_substitution_is_id :
forall (t : fterm), substitute empty_substitution t [~] t.
Proof.
induction t.
apply term_bis_refl.
constructor.
assumption.
Qed.
(** Applying equal substitutions yields equal terms.
We have not yet proven this lemma. This taints the lemmas
[step_eq_source] and [step_eq_target] in [Rewriting]. *)
Lemma substitution_eq_substitute :
forall sigma theta t,
substitution_eq (vars t) sigma theta ->
substitute sigma t [~] substitute theta t.
Proof.
intros sigma theta t H.
induction t as [x | f args IH]; simpl.
rewrite (proj2 H).
apply term_bis_refl.
constructor.
intro i.
apply IH; clear IH.
simpl in H.
unfold vmap in H.
induction (arity f) as [| n IH]; clear f.
inversion i.
dependent destruction i.
simpl in H.
unfold vhead in H.
unfold vtail in H.
apply (substitution_eq_app_left sigma theta H).
specialize IH with (vtail args) i.
apply IH.
unfold vtail.
(** Here we are stuck, need some more lemmas on [vector], for example:
[[
Lemma a :
forall x n v,
In x (vfold nil app (fun i0 : Fin n => vars (v (Next i0)))) ->
In x (vfold nil app (fun i : Fin (S n) => vars (v i))).
]]
*)
Admitted.
(** Apply a substitution to an infinite term. Note that this definition is
not in guarded form if we were to use the inductive vector type from the
standard library. It is in guarded form here, because we use [vector]
from the [Vector] library, where [vmap] is just an abstraction (which
ensures the corecursive call to [substitute'] to be guarded). *)
CoFixpoint substitute' (sigma : substitution) (t : term) : term :=
match t with
| Var x => sigma x
| Fun f args => Fun f (vmap (substitute' sigma) args)
end.
(** Applying the empty substitution to a term gives the same term. *)
Lemma empty_substitution_is_id' :
forall (t : term), substitute' empty_substitution t [~] t.
Proof.
cofix IH.
destruct t.
rewrite (peek_eq (substitute' empty_substitution (Var v))).
apply term_bis_refl.
rewrite (peek_eq (substitute' empty_substitution (Fun f v))).
simpl.
constructor.
intro i.
unfold vmap.
apply IH.
Qed.
(** We prove that both substitution functions do the same thing (on finite
terms). We can almost prove this for coq-equality, but we cannot equate
[vmap finite_term_as_term v] and [v]. *)
Lemma substitutions_related :
forall (s : substitution) (t : fterm), substitute s t [~] substitute' s t.
Proof.
induction t.
simpl.
rewrite (peek_eq (substitute' s (Var v))).
simpl.
destruct (s v); apply term_bis_refl.
simpl.
rewrite (peek_eq (substitute' s (Fun f (vmap (@finite_term_as_term F X) v)))).
simpl.
constructor.
intro i.
unfold vmap.
apply H.
Qed.
End Substitution.
|
`define STATE_BYTE_START 3'h0
`define STATE_BYTE_WAIT_FOR_BUSY 3'h1
`define STATE_BYTE_WAIT_FOR_NOT_BUSY 3'h2
`define STATE_STOPPED 3'h3
`define MESSAGE "Hello, everyweeks!\r\n"
`define MESSAGE_LEN 20
`define MESSAGE_LEN_BITS `MESSAGE_LEN * 8
module hello(
input clk_50,
input reset_n,
output tx);
reg [7:0] data;
reg dataReady;
wire busy;
reg [0:`MESSAGE_LEN_BITS - 1] message;
reg [1:0] state;
always @(posedge clk_50 or negedge reset_n)
if (reset_n == 1'b0) begin
data <= 0;
dataReady <= 0;
message <= `MESSAGE;
state <= `STATE_BYTE_START;
end else begin
case (state)
`STATE_BYTE_START:
if (message[0:7] != 0) begin
data <= message[0:7];
message <= {message[8:`MESSAGE_LEN_BITS - 1], 8'd0};
dataReady <= 1;
state <= `STATE_BYTE_WAIT_FOR_BUSY;
end else
state <= `STATE_STOPPED;
`STATE_BYTE_WAIT_FOR_BUSY:
if (busy) begin
dataReady <= 0;
state <= `STATE_BYTE_WAIT_FOR_NOT_BUSY;
end
`STATE_BYTE_WAIT_FOR_NOT_BUSY:
if (!busy)
state <= `STATE_BYTE_START;
default: state <= `STATE_STOPPED;
endcase
end
uart yuart(
.clk(clk_50),
.reset(!reset_n),
.data(data),
.dataReady(dataReady),
.busy(busy),
.tx(tx)
);
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:02:53 05/24/2016
// Design Name: escritor_lector_rtc
// Module Name: D:/TEC/I 2016/Lab Digitales/Proyecto III/Proyecto Xillinx/Proyecto_3/testbench_escitor_lector_rtc.v
// Project Name: Proyecto_3
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: escritor_lector_rtc
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testbench_escitor_lector_rtc;
// Inputs
reg clk;
reg reset;
reg [7:0] port_id;
reg [7:0] in_dato;
reg write_strobe;
reg read_strobe;
// Outputs
wire reg_a_d;
wire reg_cs;
wire reg_rd;
wire reg_wr;
wire [7:0] out_dato;
wire [7:0] fin_lectura_escritura;
// Bidirs
wire [7:0] dato;
// Instantiate the Unit Under Test (UUT)
escritor_lector_rtc uut (
.clk(clk),
.reset(reset),
.port_id(port_id),
.in_dato(in_dato),
.write_strobe(write_strobe),
.read_strobe(read_strobe),
.reg_a_d(reg_a_d),
.reg_cs(reg_cs),
.reg_rd(reg_rd),
.reg_wr(reg_wr),
.out_dato(out_dato),
.fin_lectura_escritura(fin_lectura_escritura),
.dato(dato)
);
always #10 clk = ~clk;
/*
reg count;
always @ (posedge clk) begin
count = count + 1'b1;
end
always @(negedge count) begin
end
*/
initial begin
// Initialize Inputs
clk = 0;
reset = 1;
port_id = 0;
in_dato = 0;
write_strobe = 0;
read_strobe = 0;
#10 reset = 0;
#20 port_id = 8'h10;
in_dato = 8'h01;
#20 port_id = 8'h00;
in_dato = 8'h21;
#20 port_id = 8'h01;
in_dato = 8'h01;
#100000 $stop;
// Wait 100 ns for global reset to finish
// Add stimulus here
end
endmodule
|
module Board(clkin, /*reset,*/ rgb, led, segments, buttons, enable_segments, hsync, vsync);
input clkin /*verilator clocker*/;
reg reset;
initial reset = 1;
output [5:0] rgb;
output hsync, vsync;
input [4:0] buttons;
wire halt;
wire [15:0] data_bus;
wire [15:0] address_bus;
wire [7:0] interrupts;
wire clk;
wire write, read;
//buttons
wire cs_buttons; assign cs_buttons = read && address_bus[15:12] == 4'hB;
Buttons module_buttons(data_bus, cs_buttons, interrupts[7], buttons);
//diodes
output [15:0] led;
wire cs_diodes; assign cs_diodes = address_bus[15:12] == 4'h9;
Diodes diodes(data_bus, led, cs_diodes, write);
//led counter
output [3:0] enable_segments;
output [7:0] segments;
wire cs_led_counter; assign cs_led_counter = address_bus[15:12] == 4'hA;
LedCounter led_counter(
.clk(clk),
.data_bus(data_bus),
.enable(cs_led_counter),
.write(write),
.segments(segments),
.enable_segments(enable_segments));
//clock
//Dcm dcm(
// .CLKIN_IN(clkin),
// .RST_IN(reset),
// .CLKFX_OUT(clk),
// .CLKIN_IBUFG_OUT());
//assign clk = clkin;
reg [3:0] clk_counter;
initial clk_counter = 0;
assign clk = clk_counter[3];
always @ (posedge clkin) begin
clk_counter = clk_counter + 1;
end
reg [3:0] counter;
initial counter = 0;
//initial led_counter = 0;
always @ (posedge clk) begin
counter = counter + 1;
if (&counter) begin
reset = 0;
//led_counter <= led_counter + 1;
end
end
//assign led = led_counter;
//gpu
wire cs_gpu; assign cs_gpu = address_bus[15:12] == 4'b1111;
Gpu gpu(
.clk(clk),
.reset(reset),
.data_bus(data_bus),
.address_bus(address_bus[7:0]),
.w(cs_gpu & write),
.r(cs_gpu & read),
.hs(hsync),
.vs(vsync),
.color(rgb));
//ram
wire cs_ram; assign cs_ram = !address_bus[15];
Ram ram(
.clk(clk),
.data_bus(data_bus),
.address_bus(address_bus[10:0]),
.enable(cs_ram),
.write(write),
.read(read));
//cpu
Cpu cpu(
.clk(clk),
.reset(reset),
.data_bus(data_bus),
.address_bus(address_bus),
.r(read),
.w(write),
.interrupts(interrupts),
.halt(halt));
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_regc.v
*
* Date : 2012-11
*
* Description : Controller for Register Map Memory
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_regc(
rstn,
sw_clk,
/* Goes to port 0 of REG */
reg_rd_req_port0,
reg_rd_dv_port0,
reg_rd_addr_port0,
reg_rd_data_port0,
reg_rd_bytes_port0,
reg_rd_qos_port0,
/* Goes to port 1 of REG */
reg_rd_req_port1,
reg_rd_dv_port1,
reg_rd_addr_port1,
reg_rd_data_port1,
reg_rd_bytes_port1,
reg_rd_qos_port1
);
input rstn;
input sw_clk;
input reg_rd_req_port0;
output reg_rd_dv_port0;
input[31:0] reg_rd_addr_port0;
output[1023:0] reg_rd_data_port0;
input[7:0] reg_rd_bytes_port0;
input [3:0] reg_rd_qos_port0;
input reg_rd_req_port1;
output reg_rd_dv_port1;
input[31:0] reg_rd_addr_port1;
output[1023:0] reg_rd_data_port1;
input[7:0] reg_rd_bytes_port1;
input[3:0] reg_rd_qos_port1;
wire [3:0] rd_qos;
reg [1023:0] rd_data;
wire [31:0] rd_addr;
wire [7:0] rd_bytes;
reg rd_dv;
wire rd_req;
processing_system7_bfm_v2_0_arb_rd reg_read_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(reg_rd_qos_port0),
.qos2(reg_rd_qos_port1),
.prt_req1(reg_rd_req_port0),
.prt_req2(reg_rd_req_port1),
.prt_data1(reg_rd_data_port0),
.prt_data2(reg_rd_data_port1),
.prt_addr1(reg_rd_addr_port0),
.prt_addr2(reg_rd_addr_port1),
.prt_bytes1(reg_rd_bytes_port0),
.prt_bytes2(reg_rd_bytes_port1),
.prt_dv1(reg_rd_dv_port0),
.prt_dv2(reg_rd_dv_port1),
.prt_qos(rd_qos),
.prt_req(rd_req),
.prt_data(rd_data),
.prt_addr(rd_addr),
.prt_bytes(rd_bytes),
.prt_dv(rd_dv)
);
processing_system7_bfm_v2_0_reg_map regm();
reg state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
rd_dv <= 0;
state <= 0;
end else begin
case(state)
0:begin
state <= 0;
rd_dv <= 0;
if(rd_req) begin
regm.read_reg_mem(rd_data,rd_addr, rd_bytes);
rd_dv <= 1;
state <= 1;
end
end
1:begin
rd_dv <= 0;
state <= 0;
end
endcase
end /// if
end// always
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIEBus_pcie_bram_7x.v
// Version : 1.11
// Description : single bram wrapper for the mb pcie block
// The bram A port is the write port
// the B port is the read port
//
//
//-----------------------------------------------------------------------------//
`timescale 1ps/1ps
module PCIEBus_pcie_bram_7x
#(
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1, // PCIe Link Speed : 1 - 2.5 GT/s; 2 - 5.0 GT/s
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08, // PCIe Link Width : 1 / 2 / 4 / 8
parameter IMPL_TARGET = "HARD", // the implementation target : HARD, SOFT
parameter DOB_REG = 0, // 1 - use the output register;
// 0 - don't use the output register
parameter WIDTH = 0 // supported WIDTH's : 4, 9, 18, 36 - uses RAMB36
// 72 - uses RAMB36SDP
)
(
input user_clk_i,// user clock
input reset_i, // bram reset
input wen_i, // write enable
input [12:0] waddr_i, // write address
input [WIDTH - 1:0] wdata_i, // write data
input ren_i, // read enable
input rce_i, // output register clock enable
input [12:0] raddr_i, // read address
output [WIDTH - 1:0] rdata_o // read data
);
// map the address bits
localparam ADDR_MSB = ((WIDTH == 4) ? 12 :
(WIDTH == 9) ? 11 :
(WIDTH == 18) ? 10 :
(WIDTH == 36) ? 9 :
8
);
// set the width of the tied off low address bits
localparam ADDR_LO_BITS = ((WIDTH == 4) ? 2 :
(WIDTH == 9) ? 3 :
(WIDTH == 18) ? 4 :
(WIDTH == 36) ? 5 :
0 // for WIDTH 72 use RAMB36SDP
);
// map the data bits
localparam D_MSB = ((WIDTH == 4) ? 3 :
(WIDTH == 9) ? 7 :
(WIDTH == 18) ? 15 :
(WIDTH == 36) ? 31 :
63
);
// map the data parity bits
localparam DP_LSB = D_MSB + 1;
localparam DP_MSB = ((WIDTH == 4) ? 4 :
(WIDTH == 9) ? 8 :
(WIDTH == 18) ? 17 :
(WIDTH == 36) ? 35 :
71
);
localparam DPW = DP_MSB - DP_LSB + 1;
localparam WRITE_MODE = ((WIDTH == 72) && (!((LINK_CAP_MAX_LINK_SPEED == 4'h2) && (LINK_CAP_MAX_LINK_WIDTH == 6'h08)))) ? "WRITE_FIRST" :
((LINK_CAP_MAX_LINK_SPEED == 4'h2) && (LINK_CAP_MAX_LINK_WIDTH == 6'h08)) ? "WRITE_FIRST" : "NO_CHANGE";
localparam DEVICE = (IMPL_TARGET == "HARD") ? "7SERIES" : "VIRTEX6";
localparam BRAM_SIZE = "36Kb";
localparam WE_WIDTH =(DEVICE == "VIRTEX5" || DEVICE == "VIRTEX6" || DEVICE == "7SERIES") ?
((WIDTH <= 9) ? 1 :
(WIDTH > 9 && WIDTH <= 18) ? 2 :
(WIDTH > 18 && WIDTH <= 36) ? 4 :
(WIDTH > 36 && WIDTH <= 72) ? 8 :
(BRAM_SIZE == "18Kb") ? 4 : 8 ) : 8;
//synthesis translate_off
initial begin
//$display("[%t] %m DOB_REG %0d WIDTH %0d ADDR_MSB %0d ADDR_LO_BITS %0d DP_MSB %0d DP_LSB %0d D_MSB %0d",
// $time, DOB_REG, WIDTH, ADDR_MSB, ADDR_LO_BITS, DP_MSB, DP_LSB, D_MSB);
case (WIDTH)
4,9,18,36,72:;
default:
begin
$display("[%t] %m Error WIDTH %0d not supported", $time, WIDTH);
$finish;
end
endcase // case (WIDTH)
end
//synthesis translate_on
generate
if ((LINK_CAP_MAX_LINK_WIDTH == 6'h08 && LINK_CAP_MAX_LINK_SPEED == 4'h2) || (WIDTH == 72)) begin : use_sdp
BRAM_SDP_MACRO #(
.DEVICE (DEVICE),
.BRAM_SIZE (BRAM_SIZE),
.DO_REG (DOB_REG),
.READ_WIDTH (WIDTH),
.WRITE_WIDTH (WIDTH),
.WRITE_MODE (WRITE_MODE)
)
ramb36sdp(
.DO (rdata_o[WIDTH-1:0]),
.DI (wdata_i[WIDTH-1:0]),
.RDADDR (raddr_i[ADDR_MSB:0]),
.RDCLK (user_clk_i),
.RDEN (ren_i),
.REGCE (rce_i),
.RST (reset_i),
.WE ({WE_WIDTH{1'b1}}),
.WRADDR (waddr_i[ADDR_MSB:0]),
.WRCLK (user_clk_i),
.WREN (wen_i)
);
end // block: use_sdp
else if (WIDTH <= 36) begin : use_tdp
// use RAMB36's if the width is 4, 9, 18, or 36
BRAM_TDP_MACRO #(
.DEVICE (DEVICE),
.BRAM_SIZE (BRAM_SIZE),
.DOA_REG (0),
.DOB_REG (DOB_REG),
.READ_WIDTH_A (WIDTH),
.READ_WIDTH_B (WIDTH),
.WRITE_WIDTH_A (WIDTH),
.WRITE_WIDTH_B (WIDTH),
.WRITE_MODE_A (WRITE_MODE)
)
ramb36(
.DOA (),
.DOB (rdata_o[WIDTH-1:0]),
.ADDRA (waddr_i[ADDR_MSB:0]),
.ADDRB (raddr_i[ADDR_MSB:0]),
.CLKA (user_clk_i),
.CLKB (user_clk_i),
.DIA (wdata_i[WIDTH-1:0]),
.DIB ({WIDTH{1'b0}}),
.ENA (wen_i),
.ENB (ren_i),
.REGCEA (1'b0),
.REGCEB (rce_i),
.RSTA (reset_i),
.RSTB (reset_i),
.WEA ({WE_WIDTH{1'b1}}),
.WEB ({WE_WIDTH{1'b0}})
);
end // block: use_tdp
endgenerate
endmodule // pcie_bram_7x
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Thu Sep 28 11:37:19 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_rx_inst_stub.v
// Design : fifo_generator_rx_inst
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v13_1_2,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, rst, din, wr_en, rd_en, dout, full, empty)
/* synthesis syn_black_box black_box_pad_pin="clk,rst,din[63:0],wr_en,rd_en,dout[63:0],full,empty" */;
input clk;
input rst;
input [63:0]din;
input wr_en;
input rd_en;
output [63:0]dout;
output full;
output empty;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O211AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__O211AI_BEHAVIORAL_PP_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o211ai (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , C1, or0_out, B1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O211AI_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A22OI_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__A22OI_PP_BLACKBOX_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a22oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A22OI_PP_BLACKBOX_V
|
/*
* Copyright (c) 2015-2018 The Ultiparc Project. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* Memory access pipeline stage
*/
`include "uparc_cpu_config.vh"
`include "uparc_cpu_common.vh"
`include "uparc_cpu_const.vh"
/* Memory access stage */
module uparc_memory_access(
clk,
nrst,
/* CU signals */
i_exec_stall,
o_mem_stall,
i_fetch_stall,
i_wait_stall,
o_bus_error,
o_addr_error,
i_nullify,
/* LSU interface */
lsu_addr,
lsu_wdata,
lsu_rdata,
lsu_cmd,
lsu_rnw,
lsu_busy,
lsu_err_align,
lsu_err_bus,
/* Result of execute stage */
i_rd_no,
i_alu_result,
i_lsu_op,
i_lsu_lns,
i_lsu_ext,
i_mem_data,
/* Data for writeback */
o_rd_no,
o_rd_val
);
`include "uparc_reg_names.vh"
/* Destination result */
localparam [3:0] MUX_RD_ALU = 4'b0000; /* ALU result */
localparam [3:0] MUX_RD_BYTE_SE = 4'b1000; /* Sign-extended byte */
localparam [3:0] MUX_RD_BYTE_ZE = 4'b1001; /* Zero-extended byte */
localparam [3:0] MUX_RD_HWORD_SE = 4'b1010; /* Sign-extended halfword */
localparam [3:0] MUX_RD_HWORD_ZE = 4'b1011; /* Zero-extended halfword */
localparam [3:0] MUX_RD_WORD = 4'b1100; /* Word */
/* Inputs */
input wire clk;
input wire nrst;
/* CU signals */
input wire i_exec_stall;
output wire o_mem_stall;
input wire i_fetch_stall;
input wire i_wait_stall;
output wire o_bus_error;
output wire o_addr_error;
input wire i_nullify;
/* LSU interface */
output reg [`UPARC_ADDR_WIDTH-1:0] lsu_addr;
output reg [`UPARC_DATA_WIDTH-1:0] lsu_wdata;
input wire [`UPARC_DATA_WIDTH-1:0] lsu_rdata;
output reg [1:0] lsu_cmd;
output reg lsu_rnw;
input wire lsu_busy;
input wire lsu_err_align;
input wire lsu_err_bus;
/* Input from execute stage */
input wire [`UPARC_REGNO_WIDTH-1:0] i_rd_no;
input wire [`UPARC_REG_WIDTH-1:0] i_alu_result;
input wire [`UPARC_LSUOP_WIDTH-1:0] i_lsu_op;
input wire i_lsu_lns;
input wire i_lsu_ext;
input wire [`UPARC_DATA_WIDTH-1:0] i_mem_data;
/* Output for writeback */
output reg [`UPARC_REGNO_WIDTH-1:0] o_rd_no;
output reg [`UPARC_REG_WIDTH-1:0] o_rd_val;
wire core_stall = i_exec_stall || o_mem_stall || i_fetch_stall || i_wait_stall;
assign o_mem_stall = lsu_busy;
assign o_bus_error = lsu_err_bus | lsu_err_bus_r;
assign o_addr_error = lsu_err_align | lsu_err_align_r;
/** Local wires and registers **/
reg lsu_err_bus_r;
reg lsu_err_align_r;
reg [3:0] lsu_mux; /* Destination result MUX */
reg [`UPARC_REG_WIDTH-1:0] alu_result;
/* LSU operation */
always @(posedge clk or negedge nrst)
begin
if(!nrst)
begin
lsu_addr <= {(`UPARC_ADDR_WIDTH){1'b0}};
lsu_wdata <= {(`UPARC_DATA_WIDTH){1'b0}};
lsu_cmd <= `UPARC_LSU_IDLE;
lsu_rnw <= 1'b0;
lsu_mux <= MUX_RD_ALU;
alu_result <= {(`UPARC_REG_WIDTH){1'b0}};
o_rd_no <= {(`UPARC_REGNO_WIDTH){1'b0}};
lsu_err_align_r <= 1'b0;
lsu_err_bus_r <= 1'b0;
end
else
begin
lsu_cmd <= `UPARC_LSU_IDLE;
lsu_err_bus_r <= lsu_err_bus_r | lsu_err_bus;
lsu_err_align_r <= lsu_err_align_r | lsu_err_align;
if(!core_stall)
begin
o_rd_no <= !i_nullify ? i_rd_no : {(`UPARC_REGNO_WIDTH){1'b0}};
lsu_err_bus_r <= 1'b0;
lsu_err_align_r <= 1'b0;
alu_result <= i_alu_result;
lsu_addr <= i_alu_result;
lsu_wdata <= i_mem_data;
lsu_cmd <= !i_nullify ? i_lsu_op : `UPARC_LSU_IDLE;
lsu_rnw <= i_lsu_lns;
if(i_lsu_op == `UPARC_LSU_BYTE && i_lsu_ext == 1'b1)
lsu_mux <= MUX_RD_BYTE_SE;
else if(i_lsu_op == `UPARC_LSU_BYTE && i_lsu_ext == 1'b0)
lsu_mux <= MUX_RD_BYTE_ZE;
else if(i_lsu_op == `UPARC_LSU_HWORD && i_lsu_ext == 1'b1)
lsu_mux <= MUX_RD_HWORD_SE;
else if(i_lsu_op == `UPARC_LSU_HWORD && i_lsu_ext == 1'b0)
lsu_mux <= MUX_RD_HWORD_ZE;
else if(i_lsu_op == `UPARC_LSU_WORD)
lsu_mux <= MUX_RD_WORD;
else
lsu_mux <= MUX_RD_ALU;
end
end
end
/* Set outputs */
always @(*)
begin
case(lsu_mux)
MUX_RD_BYTE_SE: o_rd_val = { {24{lsu_rdata[7]}}, lsu_rdata[7:0] };
MUX_RD_BYTE_ZE: o_rd_val = { 24'b0, lsu_rdata[7:0] };
MUX_RD_HWORD_SE: o_rd_val = { {16{lsu_rdata[15]}}, lsu_rdata[15:0] };
MUX_RD_HWORD_ZE: o_rd_val = { 16'b0, lsu_rdata[15:0] };
MUX_RD_WORD: o_rd_val = lsu_rdata;
default: o_rd_val = alu_result;
endcase
end
endmodule /* uparc_memory_access */
|
// system1.v
// Generated using ACDS version 16.1 196
`timescale 1 ps / 1 ps
module system1 (
input wire clk_clk, // clk.clk
input wire [31:0] input0_extern_con_export, // input0_extern_con.export
input wire [31:0] input1_extern_con_export, // input1_extern_con.export
input wire [31:0] input2_extern_con_export, // input2_extern_con.export
input wire [31:0] input3_extern_con_export, // input3_extern_con.export
output wire [31:0] output0_extern_con_export, // output0_extern_con.export
output wire [31:0] output1_extern_con_export, // output1_extern_con.export
output wire [31:0] output2_extern_con_export, // output2_extern_con.export
output wire [31:0] output3_extern_con_export, // output3_extern_con.export
input wire reset_reset_n // reset.reset_n
);
wire [31:0] nios2_gen2_0_data_master_readdata; // mm_interconnect_0:nios2_gen2_0_data_master_readdata -> nios2_gen2_0:d_readdata
wire nios2_gen2_0_data_master_waitrequest; // mm_interconnect_0:nios2_gen2_0_data_master_waitrequest -> nios2_gen2_0:d_waitrequest
wire nios2_gen2_0_data_master_debugaccess; // nios2_gen2_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_gen2_0_data_master_debugaccess
wire [20:0] nios2_gen2_0_data_master_address; // nios2_gen2_0:d_address -> mm_interconnect_0:nios2_gen2_0_data_master_address
wire [3:0] nios2_gen2_0_data_master_byteenable; // nios2_gen2_0:d_byteenable -> mm_interconnect_0:nios2_gen2_0_data_master_byteenable
wire nios2_gen2_0_data_master_read; // nios2_gen2_0:d_read -> mm_interconnect_0:nios2_gen2_0_data_master_read
wire nios2_gen2_0_data_master_write; // nios2_gen2_0:d_write -> mm_interconnect_0:nios2_gen2_0_data_master_write
wire [31:0] nios2_gen2_0_data_master_writedata; // nios2_gen2_0:d_writedata -> mm_interconnect_0:nios2_gen2_0_data_master_writedata
wire [31:0] nios2_gen2_0_instruction_master_readdata; // mm_interconnect_0:nios2_gen2_0_instruction_master_readdata -> nios2_gen2_0:i_readdata
wire nios2_gen2_0_instruction_master_waitrequest; // mm_interconnect_0:nios2_gen2_0_instruction_master_waitrequest -> nios2_gen2_0:i_waitrequest
wire [20:0] nios2_gen2_0_instruction_master_address; // nios2_gen2_0:i_address -> mm_interconnect_0:nios2_gen2_0_instruction_master_address
wire nios2_gen2_0_instruction_master_read; // nios2_gen2_0:i_read -> mm_interconnect_0:nios2_gen2_0_instruction_master_read
wire mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_chipselect -> jtag_uart_0:av_chipselect
wire [31:0] mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata; // jtag_uart_0:av_readdata -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_readdata
wire mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest; // jtag_uart_0:av_waitrequest -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_waitrequest
wire [0:0] mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_address -> jtag_uart_0:av_address
wire mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_read -> jtag_uart_0:av_read_n
wire mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_write -> jtag_uart_0:av_write_n
wire [31:0] mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_writedata -> jtag_uart_0:av_writedata
wire [31:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata; // nios2_gen2_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_readdata
wire mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest; // nios2_gen2_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_waitrequest
wire mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_debugaccess -> nios2_gen2_0:debug_mem_slave_debugaccess
wire [8:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_address -> nios2_gen2_0:debug_mem_slave_address
wire mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_read -> nios2_gen2_0:debug_mem_slave_read
wire [3:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_byteenable -> nios2_gen2_0:debug_mem_slave_byteenable
wire mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_write -> nios2_gen2_0:debug_mem_slave_write
wire [31:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_writedata -> nios2_gen2_0:debug_mem_slave_writedata
wire mm_interconnect_0_output3_s1_chipselect; // mm_interconnect_0:output3_s1_chipselect -> output3:chipselect
wire [31:0] mm_interconnect_0_output3_s1_readdata; // output3:readdata -> mm_interconnect_0:output3_s1_readdata
wire [1:0] mm_interconnect_0_output3_s1_address; // mm_interconnect_0:output3_s1_address -> output3:address
wire mm_interconnect_0_output3_s1_write; // mm_interconnect_0:output3_s1_write -> output3:write_n
wire [31:0] mm_interconnect_0_output3_s1_writedata; // mm_interconnect_0:output3_s1_writedata -> output3:writedata
wire mm_interconnect_0_output2_s1_chipselect; // mm_interconnect_0:output2_s1_chipselect -> output2:chipselect
wire [31:0] mm_interconnect_0_output2_s1_readdata; // output2:readdata -> mm_interconnect_0:output2_s1_readdata
wire [1:0] mm_interconnect_0_output2_s1_address; // mm_interconnect_0:output2_s1_address -> output2:address
wire mm_interconnect_0_output2_s1_write; // mm_interconnect_0:output2_s1_write -> output2:write_n
wire [31:0] mm_interconnect_0_output2_s1_writedata; // mm_interconnect_0:output2_s1_writedata -> output2:writedata
wire mm_interconnect_0_output1_s1_chipselect; // mm_interconnect_0:output1_s1_chipselect -> output1:chipselect
wire [31:0] mm_interconnect_0_output1_s1_readdata; // output1:readdata -> mm_interconnect_0:output1_s1_readdata
wire [1:0] mm_interconnect_0_output1_s1_address; // mm_interconnect_0:output1_s1_address -> output1:address
wire mm_interconnect_0_output1_s1_write; // mm_interconnect_0:output1_s1_write -> output1:write_n
wire [31:0] mm_interconnect_0_output1_s1_writedata; // mm_interconnect_0:output1_s1_writedata -> output1:writedata
wire mm_interconnect_0_output0_s1_chipselect; // mm_interconnect_0:output0_s1_chipselect -> output0:chipselect
wire [31:0] mm_interconnect_0_output0_s1_readdata; // output0:readdata -> mm_interconnect_0:output0_s1_readdata
wire [1:0] mm_interconnect_0_output0_s1_address; // mm_interconnect_0:output0_s1_address -> output0:address
wire mm_interconnect_0_output0_s1_write; // mm_interconnect_0:output0_s1_write -> output0:write_n
wire [31:0] mm_interconnect_0_output0_s1_writedata; // mm_interconnect_0:output0_s1_writedata -> output0:writedata
wire [31:0] mm_interconnect_0_input3_s1_readdata; // input3:readdata -> mm_interconnect_0:input3_s1_readdata
wire [1:0] mm_interconnect_0_input3_s1_address; // mm_interconnect_0:input3_s1_address -> input3:address
wire [31:0] mm_interconnect_0_input2_s1_readdata; // input2:readdata -> mm_interconnect_0:input2_s1_readdata
wire [1:0] mm_interconnect_0_input2_s1_address; // mm_interconnect_0:input2_s1_address -> input2:address
wire [31:0] mm_interconnect_0_input1_s1_readdata; // input1:readdata -> mm_interconnect_0:input1_s1_readdata
wire [1:0] mm_interconnect_0_input1_s1_address; // mm_interconnect_0:input1_s1_address -> input1:address
wire [31:0] mm_interconnect_0_input0_s1_readdata; // input0:readdata -> mm_interconnect_0:input0_s1_readdata
wire [1:0] mm_interconnect_0_input0_s1_address; // mm_interconnect_0:input0_s1_address -> input0:address
wire mm_interconnect_0_onchip_memory2_0_s1_chipselect; // mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect
wire [31:0] mm_interconnect_0_onchip_memory2_0_s1_readdata; // onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata
wire [15:0] mm_interconnect_0_onchip_memory2_0_s1_address; // mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address
wire [3:0] mm_interconnect_0_onchip_memory2_0_s1_byteenable; // mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable
wire mm_interconnect_0_onchip_memory2_0_s1_write; // mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write
wire [31:0] mm_interconnect_0_onchip_memory2_0_s1_writedata; // mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata
wire mm_interconnect_0_onchip_memory2_0_s1_clken; // mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken
wire irq_mapper_receiver0_irq; // jtag_uart_0:av_irq -> irq_mapper:receiver0_irq
wire [31:0] nios2_gen2_0_irq_irq; // irq_mapper:sender_irq -> nios2_gen2_0:irq
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [input0:reset_n, input1:reset_n, input2:reset_n, input3:reset_n, irq_mapper:reset, jtag_uart_0:rst_n, mm_interconnect_0:nios2_gen2_0_reset_reset_bridge_in_reset_reset, nios2_gen2_0:reset_n, onchip_memory2_0:reset, output0:reset_n, output1:reset_n, output2:reset_n, output3:reset_n, rst_translator:in_reset]
wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> [nios2_gen2_0:reset_req, onchip_memory2_0:reset_req, rst_translator:reset_req_in]
system1_input0 input0 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_input0_s1_address), // s1.address
.readdata (mm_interconnect_0_input0_s1_readdata), // .readdata
.in_port (input0_extern_con_export) // external_connection.export
);
system1_input0 input1 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_input1_s1_address), // s1.address
.readdata (mm_interconnect_0_input1_s1_readdata), // .readdata
.in_port (input1_extern_con_export) // external_connection.export
);
system1_input0 input2 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_input2_s1_address), // s1.address
.readdata (mm_interconnect_0_input2_s1_readdata), // .readdata
.in_port (input2_extern_con_export) // external_connection.export
);
system1_input0 input3 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_input3_s1_address), // s1.address
.readdata (mm_interconnect_0_input3_s1_readdata), // .readdata
.in_port (input3_extern_con_export) // external_connection.export
);
system1_jtag_uart_0 jtag_uart_0 (
.clk (clk_clk), // clk.clk
.rst_n (~rst_controller_reset_out_reset), // reset.reset_n
.av_chipselect (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect), // avalon_jtag_slave.chipselect
.av_address (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address), // .address
.av_read_n (~mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read), // .read_n
.av_readdata (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata), // .readdata
.av_write_n (~mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write), // .write_n
.av_writedata (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest), // .waitrequest
.av_irq (irq_mapper_receiver0_irq) // irq.irq
);
system1_nios2_gen2_0 nios2_gen2_0 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.d_address (nios2_gen2_0_data_master_address), // data_master.address
.d_byteenable (nios2_gen2_0_data_master_byteenable), // .byteenable
.d_read (nios2_gen2_0_data_master_read), // .read
.d_readdata (nios2_gen2_0_data_master_readdata), // .readdata
.d_waitrequest (nios2_gen2_0_data_master_waitrequest), // .waitrequest
.d_write (nios2_gen2_0_data_master_write), // .write
.d_writedata (nios2_gen2_0_data_master_writedata), // .writedata
.debug_mem_slave_debugaccess_to_roms (nios2_gen2_0_data_master_debugaccess), // .debugaccess
.i_address (nios2_gen2_0_instruction_master_address), // instruction_master.address
.i_read (nios2_gen2_0_instruction_master_read), // .read
.i_readdata (nios2_gen2_0_instruction_master_readdata), // .readdata
.i_waitrequest (nios2_gen2_0_instruction_master_waitrequest), // .waitrequest
.irq (nios2_gen2_0_irq_irq), // irq.irq
.debug_reset_request (), // debug_reset_request.reset
.debug_mem_slave_address (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read), // .read
.debug_mem_slave_readdata (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write), // .write
.debug_mem_slave_writedata (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata), // .writedata
.dummy_ci_port () // custom_instruction_master.readra
);
system1_onchip_memory2_0 onchip_memory2_0 (
.clk (clk_clk), // clk1.clk
.address (mm_interconnect_0_onchip_memory2_0_s1_address), // s1.address
.clken (mm_interconnect_0_onchip_memory2_0_s1_clken), // .clken
.chipselect (mm_interconnect_0_onchip_memory2_0_s1_chipselect), // .chipselect
.write (mm_interconnect_0_onchip_memory2_0_s1_write), // .write
.readdata (mm_interconnect_0_onchip_memory2_0_s1_readdata), // .readdata
.writedata (mm_interconnect_0_onchip_memory2_0_s1_writedata), // .writedata
.byteenable (mm_interconnect_0_onchip_memory2_0_s1_byteenable), // .byteenable
.reset (rst_controller_reset_out_reset), // reset1.reset
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.freeze (1'b0) // (terminated)
);
system1_output0 output0 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_output0_s1_address), // s1.address
.write_n (~mm_interconnect_0_output0_s1_write), // .write_n
.writedata (mm_interconnect_0_output0_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_output0_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_output0_s1_readdata), // .readdata
.out_port (output0_extern_con_export) // external_connection.export
);
system1_output0 output1 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_output1_s1_address), // s1.address
.write_n (~mm_interconnect_0_output1_s1_write), // .write_n
.writedata (mm_interconnect_0_output1_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_output1_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_output1_s1_readdata), // .readdata
.out_port (output1_extern_con_export) // external_connection.export
);
system1_output0 output2 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_output2_s1_address), // s1.address
.write_n (~mm_interconnect_0_output2_s1_write), // .write_n
.writedata (mm_interconnect_0_output2_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_output2_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_output2_s1_readdata), // .readdata
.out_port (output2_extern_con_export) // external_connection.export
);
system1_output0 output3 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_output3_s1_address), // s1.address
.write_n (~mm_interconnect_0_output3_s1_write), // .write_n
.writedata (mm_interconnect_0_output3_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_output3_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_output3_s1_readdata), // .readdata
.out_port (output3_extern_con_export) // external_connection.export
);
system1_mm_interconnect_0 mm_interconnect_0 (
.clk_0_clk_clk (clk_clk), // clk_0_clk.clk
.nios2_gen2_0_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // nios2_gen2_0_reset_reset_bridge_in_reset.reset
.nios2_gen2_0_data_master_address (nios2_gen2_0_data_master_address), // nios2_gen2_0_data_master.address
.nios2_gen2_0_data_master_waitrequest (nios2_gen2_0_data_master_waitrequest), // .waitrequest
.nios2_gen2_0_data_master_byteenable (nios2_gen2_0_data_master_byteenable), // .byteenable
.nios2_gen2_0_data_master_read (nios2_gen2_0_data_master_read), // .read
.nios2_gen2_0_data_master_readdata (nios2_gen2_0_data_master_readdata), // .readdata
.nios2_gen2_0_data_master_write (nios2_gen2_0_data_master_write), // .write
.nios2_gen2_0_data_master_writedata (nios2_gen2_0_data_master_writedata), // .writedata
.nios2_gen2_0_data_master_debugaccess (nios2_gen2_0_data_master_debugaccess), // .debugaccess
.nios2_gen2_0_instruction_master_address (nios2_gen2_0_instruction_master_address), // nios2_gen2_0_instruction_master.address
.nios2_gen2_0_instruction_master_waitrequest (nios2_gen2_0_instruction_master_waitrequest), // .waitrequest
.nios2_gen2_0_instruction_master_read (nios2_gen2_0_instruction_master_read), // .read
.nios2_gen2_0_instruction_master_readdata (nios2_gen2_0_instruction_master_readdata), // .readdata
.input0_s1_address (mm_interconnect_0_input0_s1_address), // input0_s1.address
.input0_s1_readdata (mm_interconnect_0_input0_s1_readdata), // .readdata
.input1_s1_address (mm_interconnect_0_input1_s1_address), // input1_s1.address
.input1_s1_readdata (mm_interconnect_0_input1_s1_readdata), // .readdata
.input2_s1_address (mm_interconnect_0_input2_s1_address), // input2_s1.address
.input2_s1_readdata (mm_interconnect_0_input2_s1_readdata), // .readdata
.input3_s1_address (mm_interconnect_0_input3_s1_address), // input3_s1.address
.input3_s1_readdata (mm_interconnect_0_input3_s1_readdata), // .readdata
.jtag_uart_0_avalon_jtag_slave_address (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address), // jtag_uart_0_avalon_jtag_slave.address
.jtag_uart_0_avalon_jtag_slave_write (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write), // .write
.jtag_uart_0_avalon_jtag_slave_read (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read), // .read
.jtag_uart_0_avalon_jtag_slave_readdata (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata), // .readdata
.jtag_uart_0_avalon_jtag_slave_writedata (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata), // .writedata
.jtag_uart_0_avalon_jtag_slave_waitrequest (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest), // .waitrequest
.jtag_uart_0_avalon_jtag_slave_chipselect (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect), // .chipselect
.nios2_gen2_0_debug_mem_slave_address (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address), // nios2_gen2_0_debug_mem_slave.address
.nios2_gen2_0_debug_mem_slave_write (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write), // .write
.nios2_gen2_0_debug_mem_slave_read (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read), // .read
.nios2_gen2_0_debug_mem_slave_readdata (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata), // .readdata
.nios2_gen2_0_debug_mem_slave_writedata (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata), // .writedata
.nios2_gen2_0_debug_mem_slave_byteenable (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable), // .byteenable
.nios2_gen2_0_debug_mem_slave_waitrequest (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest), // .waitrequest
.nios2_gen2_0_debug_mem_slave_debugaccess (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess), // .debugaccess
.onchip_memory2_0_s1_address (mm_interconnect_0_onchip_memory2_0_s1_address), // onchip_memory2_0_s1.address
.onchip_memory2_0_s1_write (mm_interconnect_0_onchip_memory2_0_s1_write), // .write
.onchip_memory2_0_s1_readdata (mm_interconnect_0_onchip_memory2_0_s1_readdata), // .readdata
.onchip_memory2_0_s1_writedata (mm_interconnect_0_onchip_memory2_0_s1_writedata), // .writedata
.onchip_memory2_0_s1_byteenable (mm_interconnect_0_onchip_memory2_0_s1_byteenable), // .byteenable
.onchip_memory2_0_s1_chipselect (mm_interconnect_0_onchip_memory2_0_s1_chipselect), // .chipselect
.onchip_memory2_0_s1_clken (mm_interconnect_0_onchip_memory2_0_s1_clken), // .clken
.output0_s1_address (mm_interconnect_0_output0_s1_address), // output0_s1.address
.output0_s1_write (mm_interconnect_0_output0_s1_write), // .write
.output0_s1_readdata (mm_interconnect_0_output0_s1_readdata), // .readdata
.output0_s1_writedata (mm_interconnect_0_output0_s1_writedata), // .writedata
.output0_s1_chipselect (mm_interconnect_0_output0_s1_chipselect), // .chipselect
.output1_s1_address (mm_interconnect_0_output1_s1_address), // output1_s1.address
.output1_s1_write (mm_interconnect_0_output1_s1_write), // .write
.output1_s1_readdata (mm_interconnect_0_output1_s1_readdata), // .readdata
.output1_s1_writedata (mm_interconnect_0_output1_s1_writedata), // .writedata
.output1_s1_chipselect (mm_interconnect_0_output1_s1_chipselect), // .chipselect
.output2_s1_address (mm_interconnect_0_output2_s1_address), // output2_s1.address
.output2_s1_write (mm_interconnect_0_output2_s1_write), // .write
.output2_s1_readdata (mm_interconnect_0_output2_s1_readdata), // .readdata
.output2_s1_writedata (mm_interconnect_0_output2_s1_writedata), // .writedata
.output2_s1_chipselect (mm_interconnect_0_output2_s1_chipselect), // .chipselect
.output3_s1_address (mm_interconnect_0_output3_s1_address), // output3_s1.address
.output3_s1_write (mm_interconnect_0_output3_s1_write), // .write
.output3_s1_readdata (mm_interconnect_0_output3_s1_readdata), // .readdata
.output3_s1_writedata (mm_interconnect_0_output3_s1_writedata), // .writedata
.output3_s1_chipselect (mm_interconnect_0_output3_s1_chipselect) // .chipselect
);
system1_irq_mapper irq_mapper (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.sender_irq (nios2_gen2_0_irq_irq) // sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2BB2AI_BEHAVIORAL_V
`define SKY130_FD_SC_HS__O2BB2AI_BEHAVIORAL_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o2bb2ai (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
// Local signals
wire B2 nand0_out ;
wire B2 or0_out ;
wire nand1_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
nand nand1 (nand1_out_Y , nand0_out, or0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand1_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2BB2AI_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD1_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__CLKDLYINV3SD1_FUNCTIONAL_PP_V
/**
* clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__clkdlyinv3sd1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV3SD1_FUNCTIONAL_PP_V |
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.2 (win64) Build 928826 Thu Jun 5 18:21:07 MDT 2014
// Date : Wed Sep 10 03:38:08 2014
// Host : Dtysky running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// d:/spira_heaven/0-myworks/ld3320_axi/ld3320_axi_1.0/src/LIST/LIST_funcsim.v
// Design : LIST
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-2
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_2,Vivado 2014.2" *) (* CHECK_LICENSE_TYPE = "LIST,blk_mem_gen_v8_2,{}" *)
(* core_generation_info = "LIST,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=1,x_ipLanguage=VERILOG,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=LIST.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=256,C_READ_DEPTH_A=256,C_ADDRA_WIDTH=8,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=256,C_READ_DEPTH_B=256,C_ADDRB_WIDTH=8,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=0,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.68455 mW}" *)
(* NotValidForBitStream *)
module LIST
(clka,
wea,
addra,
dina,
clkb,
addrb,
doutb);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
input [0:0]wea;
input [7:0]addra;
input [7:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *) input clkb;
input [7:0]addrb;
output [7:0]doutb;
wire [7:0]addra;
wire [7:0]addrb;
wire clka;
wire clkb;
wire [7:0]dina;
wire [7:0]doutb;
wire [0:0]wea;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [7:0]NLW_U0_douta_UNCONNECTED;
wire [7:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [7:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [7:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "8" *)
(* C_ADDRB_WIDTH = "8" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "0" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.68455 mW" *)
(* C_FAMILY = "zynq" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "LIST.mem" *)
(* C_INIT_FILE_NAME = "no_coe_file_loaded" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "0" *)
(* C_MEM_TYPE = "1" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "256" *)
(* C_READ_DEPTH_B = "256" *)
(* C_READ_WIDTH_A = "8" *)
(* C_READ_WIDTH_B = "8" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "256" *)
(* C_WRITE_DEPTH_B = "256" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "8" *)
(* C_WRITE_WIDTH_B = "8" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* DONT_TOUCH *)
(* downgradeipidentifiedwarnings = "yes" *)
LIST_blk_mem_gen_v8_2__parameterized0 U0
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.dina(dina),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(NLW_U0_douta_UNCONNECTED[7:0]),
.doutb(doutb),
.eccpipece(1'b0),
.ena(1'b0),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[7:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rstb(1'b0),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[7:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[7:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.sleep(1'b0),
.wea(wea),
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module LIST_blk_mem_gen_generic_cstr
(doutb,
clkb,
clka,
wea,
addrb,
addra,
dina);
output [7:0]doutb;
input clkb;
input clka;
input [0:0]wea;
input [7:0]addrb;
input [7:0]addra;
input [7:0]dina;
wire [7:0]addra;
wire [7:0]addrb;
wire clka;
wire clkb;
wire [7:0]dina;
wire [7:0]doutb;
wire [0:0]wea;
LIST_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.doutb(doutb),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module LIST_blk_mem_gen_prim_width
(doutb,
clkb,
clka,
wea,
addrb,
addra,
dina);
output [7:0]doutb;
input clkb;
input clka;
input [0:0]wea;
input [7:0]addrb;
input [7:0]addra;
input [7:0]dina;
wire [7:0]addra;
wire [7:0]addrb;
wire clka;
wire clkb;
wire [7:0]dina;
wire [7:0]doutb;
wire [0:0]wea;
LIST_blk_mem_gen_prim_wrapper \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.doutb(doutb),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module LIST_blk_mem_gen_prim_wrapper
(doutb,
clkb,
clka,
wea,
addrb,
addra,
dina);
output [7:0]doutb;
input clkb;
input clka;
input [0:0]wea;
input [7:0]addrb;
input [7:0]addra;
input [7:0]dina;
wire [7:0]addra;
wire [7:0]addrb;
wire clka;
wire clkb;
wire [7:0]dina;
wire [7:0]doutb;
wire \n_0_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire \n_10_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire \n_11_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire \n_12_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire \n_13_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire \n_16_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire \n_17_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire \n_18_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire \n_19_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire \n_1_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire \n_20_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire \n_21_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire \n_24_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire \n_25_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire \n_26_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire \n_27_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire \n_28_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire \n_29_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire \n_2_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire \n_32_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire \n_33_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire \n_34_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire \n_35_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire \n_3_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire \n_4_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire \n_5_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire \n_8_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire \n_9_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ;
wire [0:0]wea;
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(0),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("SDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(0),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram
(.ADDRARDADDR({1'b0,addrb,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b0,addra,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CLKARDCLK(clkb),
.CLKBWRCLK(clka),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[3:2],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[1:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:6],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[5:4]}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO({\n_0_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_1_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_2_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_3_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_4_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_5_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,doutb[3:2],\n_8_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_9_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_10_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_11_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_12_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_13_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,doutb[1:0]}),
.DOBDO({\n_16_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_17_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_18_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_19_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_20_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_21_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,doutb[7:6],\n_24_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_25_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_26_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_27_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_28_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_29_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,doutb[5:4]}),
.DOPADOP({\n_32_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_33_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram }),
.DOPBDOP({\n_34_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram ,\n_35_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram }),
.ENARDEN(1'b1),
.ENBWREN(wea),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({1'b0,1'b0}),
.WEBWE({1'b1,1'b1,1'b1,1'b1}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module LIST_blk_mem_gen_top
(doutb,
clkb,
clka,
wea,
addrb,
addra,
dina);
output [7:0]doutb;
input clkb;
input clka;
input [0:0]wea;
input [7:0]addrb;
input [7:0]addra;
input [7:0]dina;
wire [7:0]addra;
wire [7:0]addrb;
wire clka;
wire clkb;
wire [7:0]dina;
wire [7:0]doutb;
wire [0:0]wea;
LIST_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.doutb(doutb),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_2" *) (* C_FAMILY = "zynq" *) (* C_XDEVICEFAMILY = "zynq" *)
(* C_ELABORATION_DIR = "./" *) (* C_INTERFACE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_AXI_SLAVE_TYPE = "0" *) (* C_USE_BRAM_BLOCK = "0" *) (* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_CTRL_ECC_ALGO = "NONE" *) (* C_HAS_AXI_ID = "0" *) (* C_AXI_ID_WIDTH = "4" *)
(* C_MEM_TYPE = "1" *) (* C_BYTE_SIZE = "9" *) (* C_ALGORITHM = "1" *)
(* C_PRIM_TYPE = "1" *) (* C_LOAD_INIT_FILE = "0" *) (* C_INIT_FILE_NAME = "no_coe_file_loaded" *)
(* C_INIT_FILE = "LIST.mem" *) (* C_USE_DEFAULT_DATA = "0" *) (* C_DEFAULT_DATA = "0" *)
(* C_HAS_RSTA = "0" *) (* C_RST_PRIORITY_A = "CE" *) (* C_RSTRAM_A = "0" *)
(* C_INITA_VAL = "0" *) (* C_HAS_ENA = "0" *) (* C_HAS_REGCEA = "0" *)
(* C_USE_BYTE_WEA = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "8" *) (* C_READ_WIDTH_A = "8" *) (* C_WRITE_DEPTH_A = "256" *)
(* C_READ_DEPTH_A = "256" *) (* C_ADDRA_WIDTH = "8" *) (* C_HAS_RSTB = "0" *)
(* C_RST_PRIORITY_B = "CE" *) (* C_RSTRAM_B = "0" *) (* C_INITB_VAL = "0" *)
(* C_HAS_ENB = "0" *) (* C_HAS_REGCEB = "0" *) (* C_USE_BYTE_WEB = "0" *)
(* C_WEB_WIDTH = "1" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_B = "8" *)
(* C_READ_WIDTH_B = "8" *) (* C_WRITE_DEPTH_B = "256" *) (* C_READ_DEPTH_B = "256" *)
(* C_ADDRB_WIDTH = "8" *) (* C_HAS_MEM_OUTPUT_REGS_A = "0" *) (* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *) (* C_MUX_PIPELINE_STAGES = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) (* C_USE_SOFTECC = "0" *)
(* C_USE_ECC = "0" *) (* C_EN_ECC_PIPE = "0" *) (* C_HAS_INJECTERR = "0" *)
(* C_SIM_COLLISION_CHECK = "ALL" *) (* C_COMMON_CLK = "0" *) (* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_EN_SLEEP_PIN = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_COUNT_36K_BRAM = "0" *)
(* C_COUNT_18K_BRAM = "1" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.68455 mW" *) (* downgradeipidentifiedwarnings = "yes" *)
module LIST_blk_mem_gen_v8_2__parameterized0
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [7:0]addra;
input [7:0]dina;
output [7:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [7:0]addrb;
input [7:0]dinb;
output [7:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [7:0]rdaddrecc;
input sleep;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [7:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [7:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [7:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [7:0]addra;
wire [7:0]addrb;
wire clka;
wire clkb;
wire [7:0]dina;
wire [7:0]dinb;
wire [7:0]doutb;
wire eccpipece;
wire ena;
wire enb;
wire injectdbiterr;
wire injectsbiterr;
wire regcea;
wire regceb;
wire rsta;
wire rstb;
wire s_aclk;
wire s_aresetn;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_injectdbiterr;
wire s_axi_injectsbiterr;
wire s_axi_rready;
wire [7:0]s_axi_wdata;
wire s_axi_wlast;
wire [0:0]s_axi_wstrb;
wire s_axi_wvalid;
wire sleep;
wire [0:0]wea;
wire [0:0]web;
assign dbiterr = \<const0> ;
assign douta[7] = \<const0> ;
assign douta[6] = \<const0> ;
assign douta[5] = \<const0> ;
assign douta[4] = \<const0> ;
assign douta[3] = \<const0> ;
assign douta[2] = \<const0> ;
assign douta[1] = \<const0> ;
assign douta[0] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
LIST_blk_mem_gen_v8_2_synth inst_blk_mem_gen
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.doutb(doutb),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_2_synth" *)
module LIST_blk_mem_gen_v8_2_synth
(doutb,
clkb,
clka,
wea,
addrb,
addra,
dina);
output [7:0]doutb;
input clkb;
input clka;
input [0:0]wea;
input [7:0]addrb;
input [7:0]addra;
input [7:0]dina;
wire [7:0]addra;
wire [7:0]addrb;
wire clka;
wire clkb;
wire [7:0]dina;
wire [7:0]doutb;
wire [0:0]wea;
LIST_blk_mem_gen_top \gnativebmg.native_blk_mem_gen
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.doutb(doutb),
.wea(wea));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// Copyright 2021 The CFU-Playground Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
module Cfu (
input cmd_valid,
output cmd_ready,
input [9:0] cmd_payload_function_id,
input [31:0] cmd_payload_inputs_0,
input [31:0] cmd_payload_inputs_1,
output rsp_valid,
input rsp_ready,
output [31:0] rsp_payload_outputs_0,
input clk,
input reset
);
assign rsp_valid = cmd_valid;
assign cmd_ready = rsp_ready;
// byte sum (unsigned)
wire [31:0] cfu0;
assign cfu0[31:0] = cmd_payload_inputs_0[7:0] + cmd_payload_inputs_1[7:0] +
cmd_payload_inputs_0[15:8] + cmd_payload_inputs_1[15:8] +
cmd_payload_inputs_0[23:16] + cmd_payload_inputs_1[23:16] +
cmd_payload_inputs_0[31:24] + cmd_payload_inputs_1[31:24];
// byte swap
wire [31:0] cfu1;
assign cfu1[31:24] = cmd_payload_inputs_0[7:0];
assign cfu1[23:16] = cmd_payload_inputs_0[15:8];
assign cfu1[15:8] = cmd_payload_inputs_0[23:16];
assign cfu1[7:0] = cmd_payload_inputs_0[31:24];
// bit reverse
wire [31:0] cfu2;
genvar n;
generate
for (n=0; n<32; n=n+1) begin
assign cfu2[n] = cmd_payload_inputs_0[31-n];
end
endgenerate
//
// select output -- note that we're not fully decoding the 3 function_id bits
//
assign rsp_payload_outputs_0 = cmd_payload_function_id[1] ? cfu2 :
( cmd_payload_function_id[0] ? cfu1 : cfu0);
endmodule
|
// megafunction wizard: %RAM: 2-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: dpram_32_128x16.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.1 Build 201 11/27/2006 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module dpram_32_128x16 (
byteena_a,
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [3:0] byteena_a;
input [31:0] data;
input [1:0] rdaddress;
input rdclock;
input [3:0] wraddress;
input wrclock;
input wren;
output [127:0] q;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "1"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "512"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "128"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "128"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "4"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "2"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "128"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4"
// Retrieval info: USED_PORT: byteena_a 0 0 4 0 INPUT VCC byteena_a[3..0]
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
// Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL q[127..0]
// Retrieval info: USED_PORT: rdaddress 0 0 2 0 INPUT NODEFVAL rdaddress[1..0]
// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL rdclock
// Retrieval info: USED_PORT: wraddress 0 0 4 0 INPUT NODEFVAL wraddress[3..0]
// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT NODEFVAL wrclock
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 128 0 @q_b 0 0 128 0
// Retrieval info: CONNECT: @address_a 0 0 4 0 wraddress 0 0 4 0
// Retrieval info: CONNECT: @address_b 0 0 2 0 rdaddress 0 0 2 0
// Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena_a 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_128x16.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_128x16.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_128x16.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_128x16.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_128x16_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_128x16_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_128x16_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_32_128x16_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
//////////////////////////////////////////////////////////////////////////
// Department of Computer Science
// National Tsing Hua University
// Project : FIFO for CS4125 Digital System Design
// Module : fifo.v
// Author : Chih-Tsun Huang
// E-mail : [email protected]
// Revision : 4
// Date : 2014/04/28
// Abstract :
// The top module of FIFO consists of FIFO controller and the RAM module.
// Note :
// 1. The purpose of this version is to provide a design style. It is
// not a complete module. Please fix any *unexpected feature* by
// yourself if any.
// 2. Feel free to rewrite this file header to your own.
//
module fifo (
input clk,
input rst_n,
input push,
input pop,
input [7:0] datain,
output empty,
output almost_empty,
output full,
output almost_full,
output error,
output [7:0] dataout
);
wire [4:0] addr;
wire cen;
wire oen;
wire wen;
wire [7:0] data_to_ram;
fifo_ctr controller (
.clk(clk),
.rst_n(rst_n),
.push(push),
.pop(pop),
.empty(empty),
.almost_empty(almost_empty),
.full(full),
.almost_full(almost_full),
.error(error),
.cen(cen),
.wen(wen),
.oen(oen),
.addr(addr)
);
// LAB NOTE:
// You should include the memory simulation model by your own
RAM32x8 ram (
.Q(dataout),
.CLK(clk),
.CEN(cen),
.WEN(wen),
.A(addr),
.D(datain),
.OEN(oen)
);
endmodule
|
`include "constants.vh"
`include "alu_ops.vh"
`default_nettype none
module rs_mul_ent
(
//Memory
input wire clk,
input wire reset,
input wire busy,
input wire [`DATA_LEN-1:0] wsrc1,
input wire [`DATA_LEN-1:0] wsrc2,
input wire wvalid1,
input wire wvalid2,
input wire [`RRF_SEL-1:0] wrrftag,
input wire wdstval,
input wire [`SPECTAG_LEN-1:0] wspectag,
input wire wsrc1_signed,
input wire wsrc2_signed,
input wire wsel_lohi,
input wire we,
output wire [`DATA_LEN-1:0] ex_src1,
output wire [`DATA_LEN-1:0] ex_src2,
output wire ready,
output reg [`RRF_SEL-1:0] rrftag,
output reg dstval,
output reg [`SPECTAG_LEN-1:0] spectag,
output reg src1_signed,
output reg src2_signed,
output reg sel_lohi,
//EXRSLT
input wire [`DATA_LEN-1:0] exrslt1,
input wire [`RRF_SEL-1:0] exdst1,
input wire kill_spec1,
input wire [`DATA_LEN-1:0] exrslt2,
input wire [`RRF_SEL-1:0] exdst2,
input wire kill_spec2,
input wire [`DATA_LEN-1:0] exrslt3,
input wire [`RRF_SEL-1:0] exdst3,
input wire kill_spec3,
input wire [`DATA_LEN-1:0] exrslt4,
input wire [`RRF_SEL-1:0] exdst4,
input wire kill_spec4,
input wire [`DATA_LEN-1:0] exrslt5,
input wire [`RRF_SEL-1:0] exdst5,
input wire kill_spec5
);
reg [`DATA_LEN-1:0] src1;
reg [`DATA_LEN-1:0] src2;
reg valid1;
reg valid2;
wire [`DATA_LEN-1:0] nextsrc1;
wire [`DATA_LEN-1:0] nextsrc2;
wire nextvalid1;
wire nextvalid2;
assign ready = busy & valid1 & valid2;
assign ex_src1 = ~valid1 & nextvalid1 ?
nextsrc1 : src1;
assign ex_src2 = ~valid2 & nextvalid2 ?
nextsrc2 : src2;
always @ (posedge clk) begin
if (reset) begin
rrftag <= 0;
dstval <= 0;
spectag <= 0;
src1_signed <= 0;
src2_signed <= 0;
sel_lohi <= 0;
src1 <= 0;
src2 <= 0;
valid1 <= 0;
valid2 <= 0;
end else if (we) begin
rrftag <= wrrftag;
dstval <= wdstval;
spectag <= wspectag;
src1_signed <= wsrc1_signed;
src2_signed <= wsrc2_signed;
sel_lohi <= wsel_lohi;
src1 <= wsrc1;
src2 <= wsrc2;
valid1 <= wvalid1;
valid2 <= wvalid2;
end else begin // if (we)
src1 <= nextsrc1;
src2 <= nextsrc2;
valid1 <= nextvalid1;
valid2 <= nextvalid2;
end
end
src_manager srcmng1(
.opr(src1),
.opr_rdy(valid1),
.exrslt1(exrslt1),
.exdst1(exdst1),
.kill_spec1(kill_spec1),
.exrslt2(exrslt2),
.exdst2(exdst2),
.kill_spec2(kill_spec2),
.exrslt3(exrslt3),
.exdst3(exdst3),
.kill_spec3(kill_spec3),
.exrslt4(exrslt4),
.exdst4(exdst4),
.kill_spec4(kill_spec4),
.exrslt5(exrslt5),
.exdst5(exdst5),
.kill_spec5(kill_spec5),
.src(nextsrc1),
.resolved(nextvalid1)
);
src_manager srcmng2(
.opr(src2),
.opr_rdy(valid2),
.exrslt1(exrslt1),
.exdst1(exdst1),
.kill_spec1(kill_spec1),
.exrslt2(exrslt2),
.exdst2(exdst2),
.kill_spec2(kill_spec2),
.exrslt3(exrslt3),
.exdst3(exdst3),
.kill_spec3(kill_spec3),
.exrslt4(exrslt4),
.exdst4(exdst4),
.kill_spec4(kill_spec4),
.exrslt5(exrslt5),
.exdst5(exdst5),
.kill_spec5(kill_spec5),
.src(nextsrc2),
.resolved(nextvalid2)
);
endmodule // rs_mul
module rs_mul
(
//System
input wire clk,
input wire reset,
output reg [`MUL_ENT_NUM-1:0] busyvec,
input wire prmiss,
input wire prsuccess,
input wire [`SPECTAG_LEN-1:0] prtag,
input wire [`SPECTAG_LEN-1:0] specfixtag,
//WriteSignal
input wire clearbusy, //Issue
input wire [`MUL_ENT_SEL-1:0] issueaddr, //= raddr, clsbsyadr
input wire we1, //alloc1
input wire we2, //alloc2
input wire [`MUL_ENT_SEL-1:0] waddr1, //allocent1
input wire [`MUL_ENT_SEL-1:0] waddr2, //allocent2
//WriteSignal1
input wire [`DATA_LEN-1:0] wsrc1_1,
input wire [`DATA_LEN-1:0] wsrc2_1,
input wire wvalid1_1,
input wire wvalid2_1,
input wire [`RRF_SEL-1:0] wrrftag_1,
input wire wdstval_1,
input wire [`SPECTAG_LEN-1:0] wspectag_1,
input wire wspecbit_1,
input wire wsrc1_signed_1,
input wire wsrc2_signed_1,
input wire wsel_lohi_1,
//WriteSignal2
input wire [`DATA_LEN-1:0] wsrc1_2,
input wire [`DATA_LEN-1:0] wsrc2_2,
input wire wvalid1_2,
input wire wvalid2_2,
input wire [`RRF_SEL-1:0] wrrftag_2,
input wire wdstval_2,
input wire [`SPECTAG_LEN-1:0] wspectag_2,
input wire wspecbit_2,
input wire wsrc1_signed_2,
input wire wsrc2_signed_2,
input wire wsel_lohi_2,
//ReadSignal
output wire [`DATA_LEN-1:0] ex_src1,
output wire [`DATA_LEN-1:0] ex_src2,
output wire [`MUL_ENT_NUM-1:0] ready,
output wire [`RRF_SEL-1:0] rrftag,
output wire dstval,
output wire [`SPECTAG_LEN-1:0] spectag,
output wire specbit,
output wire src1_signed,
output wire src2_signed,
output wire sel_lohi,
//EXRSLT
input wire [`DATA_LEN-1:0] exrslt1,
input wire [`RRF_SEL-1:0] exdst1,
input wire kill_spec1,
input wire [`DATA_LEN-1:0] exrslt2,
input wire [`RRF_SEL-1:0] exdst2,
input wire kill_spec2,
input wire [`DATA_LEN-1:0] exrslt3,
input wire [`RRF_SEL-1:0] exdst3,
input wire kill_spec3,
input wire [`DATA_LEN-1:0] exrslt4,
input wire [`RRF_SEL-1:0] exdst4,
input wire kill_spec4,
input wire [`DATA_LEN-1:0] exrslt5,
input wire [`RRF_SEL-1:0] exdst5,
input wire kill_spec5
);
//_0
wire [`DATA_LEN-1:0] ex_src1_0;
wire [`DATA_LEN-1:0] ex_src2_0;
wire ready_0;
wire [`RRF_SEL-1:0] rrftag_0;
wire dstval_0;
wire [`SPECTAG_LEN-1:0] spectag_0;
wire src1_signed_0;
wire src2_signed_0;
wire sel_lohi_0;
//_1
wire [`DATA_LEN-1:0] ex_src1_1;
wire [`DATA_LEN-1:0] ex_src2_1;
wire ready_1;
wire [`RRF_SEL-1:0] rrftag_1;
wire dstval_1;
wire [`SPECTAG_LEN-1:0] spectag_1;
wire src1_signed_1;
wire src2_signed_1;
wire sel_lohi_1;
reg [`MUL_ENT_NUM-1:0] specbitvec;
wire [`MUL_ENT_NUM-1:0] inv_vector =
{(spectag_1 & specfixtag) == 0 ? 1'b1 : 1'b0,
(spectag_0 & specfixtag) == 0 ? 1'b1 : 1'b0};
wire [`MUL_ENT_NUM-1:0] inv_vector_spec =
{(spectag_1 == prtag) ? 1'b0 : 1'b1,
(spectag_0 == prtag) ? 1'b0 : 1'b1};
wire [`MUL_ENT_NUM-1:0] specbitvec_next =
(inv_vector_spec & specbitvec);
/* |
(we1 & wspecbit_1 ? (`MUL_ENT_SEL'b1 << waddr1) : 0) |
(we2 & wspecbit_2 ? (`MUL_ENT_SEL'b1 << waddr2) : 0);
*/
assign specbit = prsuccess ?
specbitvec_next[issueaddr] : specbitvec[issueaddr];
assign ready = {ready_1, ready_0};
always @ (posedge clk) begin
if (reset) begin
busyvec <= 0;
specbitvec <= 0;
end else begin
if (prmiss) begin
busyvec <= inv_vector & busyvec;
specbitvec <= 0;
end else if (prsuccess) begin
specbitvec <= specbitvec_next;
/*
if (we1) begin
busyvec[waddr1] <= 1'b1;
end
if (we2) begin
busyvec[waddr2] <= 1'b1;
end
*/
if (clearbusy) begin
busyvec[issueaddr] <= 1'b0;
end
end else begin
if (we1) begin
busyvec[waddr1] <= 1'b1;
specbitvec[waddr1] <= wspecbit_1;
end
if (we2) begin
busyvec[waddr2] <= 1'b1;
specbitvec[waddr2] <= wspecbit_2;
end
if (clearbusy) begin
busyvec[issueaddr] <= 1'b0;
end
end
end
end
rs_mul_ent ent0(
.clk(clk),
.reset(reset),
.busy(busyvec[0]),
.wsrc1((we1 && (waddr1 == 0)) ? wsrc1_1 : wsrc1_2),
.wsrc2((we1 && (waddr1 == 0)) ? wsrc2_1 : wsrc2_2),
.wvalid1((we1 && (waddr1 == 0)) ? wvalid1_1 : wvalid1_2),
.wvalid2((we1 && (waddr1 == 0)) ? wvalid2_1 : wvalid2_2),
.wrrftag((we1 && (waddr1 == 0)) ? wrrftag_1 : wrrftag_2),
.wdstval((we1 && (waddr1 == 0)) ? wdstval_1 : wdstval_2),
.wspectag((we1 && (waddr1 == 0)) ? wspectag_1 : wspectag_2),
.wsrc1_signed((we1 && (waddr1 == 0)) ? wsrc1_signed_1 : wsrc1_signed_2),
.wsrc2_signed((we1 && (waddr1 == 0)) ? wsrc2_signed_1 : wsrc2_signed_2),
.wsel_lohi((we1 && (waddr1 == 0)) ? wsel_lohi_1 : wsel_lohi_2),
.we((we1 && (waddr1 == 0)) || (we2 && (waddr2 == 0))),
.ex_src1(ex_src1_0),
.ex_src2(ex_src2_0),
.ready(ready_0),
.rrftag(rrftag_0),
.dstval(dstval_0),
.spectag(spectag_0),
.src1_signed(src1_signed_0),
.src2_signed(src2_signed_0),
.sel_lohi(sel_lohi_0),
.exrslt1(exrslt1),
.exdst1(exdst1),
.kill_spec1(kill_spec1),
.exrslt2(exrslt2),
.exdst2(exdst2),
.kill_spec2(kill_spec2),
.exrslt3(exrslt3),
.exdst3(exdst3),
.kill_spec3(kill_spec3),
.exrslt4(exrslt4),
.exdst4(exdst4),
.kill_spec4(kill_spec4),
.exrslt5(exrslt5),
.exdst5(exdst5),
.kill_spec5(kill_spec5)
);
rs_mul_ent ent1(
.clk(clk),
.reset(reset),
.busy(busyvec[1]),
.wsrc1((we1 && (waddr1 == 1)) ? wsrc1_1 : wsrc1_2),
.wsrc2((we1 && (waddr1 == 1)) ? wsrc2_1 : wsrc2_2),
.wvalid1((we1 && (waddr1 == 1)) ? wvalid1_1 : wvalid1_2),
.wvalid2((we1 && (waddr1 == 1)) ? wvalid2_1 : wvalid2_2),
.wrrftag((we1 && (waddr1 == 1)) ? wrrftag_1 : wrrftag_2),
.wdstval((we1 && (waddr1 == 1)) ? wdstval_1 : wdstval_2),
.wspectag((we1 && (waddr1 == 1)) ? wspectag_1 : wspectag_2),
.wsrc1_signed((we1 && (waddr1 == 1)) ? wsrc1_signed_1 : wsrc1_signed_2),
.wsrc2_signed((we1 && (waddr1 == 1)) ? wsrc2_signed_1 : wsrc2_signed_2),
.wsel_lohi((we1 && (waddr1 == 1)) ? wsel_lohi_1 : wsel_lohi_2),
.we((we1 && (waddr1 == 1)) || (we2 && (waddr2 == 1))),
.ex_src1(ex_src1_1),
.ex_src2(ex_src2_1),
.ready(ready_1),
.rrftag(rrftag_1),
.dstval(dstval_1),
.spectag(spectag_1),
.src1_signed(src1_signed_1),
.src2_signed(src2_signed_1),
.sel_lohi(sel_lohi_1),
.exrslt1(exrslt1),
.exdst1(exdst1),
.kill_spec1(kill_spec1),
.exrslt2(exrslt2),
.exdst2(exdst2),
.kill_spec2(kill_spec2),
.exrslt3(exrslt3),
.exdst3(exdst3),
.kill_spec3(kill_spec3),
.exrslt4(exrslt4),
.exdst4(exdst4),
.kill_spec4(kill_spec4),
.exrslt5(exrslt5),
.exdst5(exdst5),
.kill_spec5(kill_spec5)
);
assign ex_src1 = (issueaddr == 0) ? ex_src1_0 : ex_src1_1;
assign ex_src2 = (issueaddr == 0) ? ex_src2_0 : ex_src2_1;
assign rrftag = (issueaddr == 0) ? rrftag_0 : rrftag_1;
assign dstval = (issueaddr == 0) ? dstval_0 : dstval_1;
assign spectag = (issueaddr == 0) ? spectag_0 : spectag_1;
assign src1_signed = (issueaddr == 0) ? src1_signed_0 : src1_signed_1;
assign src2_signed = (issueaddr == 0) ? src2_signed_0 : src2_signed_1;
assign sel_lohi = (issueaddr == 0) ? sel_lohi_0 : sel_lohi_1;
endmodule // rs_mul
`default_nettype wire
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: STARTUP.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module STARTUP (
address,
clock,
q);
input [8:0] address;
input clock;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./startup/startup.hex"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "512"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "9"
// Retrieval info: PRIVATE: WidthData NUMERIC "32"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./startup/startup.hex"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 9 0 INPUT NODEFVAL "address[8..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: CONNECT: @address_a 0 0 9 0 address 0 0 9 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL STARTUP.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL STARTUP.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL STARTUP.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL STARTUP.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL STARTUP_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL STARTUP_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
`include "../../../rtl/verilog/gfx/gfx_rasterizer.v"
`include "../../../rtl/verilog/gfx/gfx_line.v"
`include "../../../rtl/verilog/gfx/gfx_triangle.v"
`include "../../../rtl/verilog/gfx/div_uu.v"
module raster_bench();
parameter point_width = 16;
parameter subpixel_width = 16;
reg clk_i;
reg rst_i;
reg clip_ack_i;
reg interp_ack_i;
wire ack_o;
reg rect_write_i;
reg line_write_i;
reg triangle_write_i;
reg interpolate_i;
reg texture_enable_i;
reg clipping_enable_i;
reg [point_width-1:0] src_pixel0_x_i;
reg [point_width-1:0] src_pixel0_y_i;
reg [point_width-1:0] src_pixel1_x_i;
reg [point_width-1:0] src_pixel1_y_i;
reg signed [point_width-1:-subpixel_width] dest_pixel0_x_i;
reg signed [point_width-1:-subpixel_width] dest_pixel0_y_i;
reg signed [point_width-1:-subpixel_width] dest_pixel1_x_i;
reg signed [point_width-1:-subpixel_width] dest_pixel1_y_i;
reg signed [point_width-1:-subpixel_width] dest_pixel2_x_i;
reg signed [point_width-1:-subpixel_width] dest_pixel2_y_i;
reg [point_width-1:0] clip_pixel0_x_i;
reg [point_width-1:0] clip_pixel0_y_i;
reg [point_width-1:0] clip_pixel1_x_i;
reg [point_width-1:0] clip_pixel1_y_i;
reg [point_width-1:0] target_size_x_i;
reg [point_width-1:0] target_size_y_i;
wire [point_width-1:0] x_counter_o;
wire [point_width-1:0] y_counter_o;
wire [point_width-1:0] u_o;
wire [point_width-1:0] v_o;
wire clip_write_o;
wire interp_write_o;
parameter FIXEDW = 2**subpixel_width;
initial begin
$dumpfile("raster.vcd");
$dumpvars(0,raster_bench);
// init values
clk_i = 0;
rst_i = 1;
clip_ack_i = 0;
interp_ack_i = 0;
rect_write_i = 0;
line_write_i = 0;
triangle_write_i = 0;
interpolate_i = 0;
dest_pixel0_x_i = -5 * FIXEDW;
dest_pixel0_y_i = 5 * FIXEDW;
dest_pixel1_x_i = 10 * FIXEDW;
dest_pixel1_y_i = 10 * FIXEDW;
dest_pixel2_x_i = 5 * FIXEDW;
dest_pixel2_y_i = 10 * FIXEDW;
src_pixel0_x_i = 5;
src_pixel0_y_i = 5;
src_pixel1_x_i = 10;
src_pixel1_y_i = 10;
clip_pixel0_x_i = 0;
clip_pixel0_y_i = 0;
clip_pixel1_x_i = 10;
clip_pixel1_y_i = 10;
target_size_x_i = 640;
target_size_y_i = 480;
texture_enable_i = 0;
clipping_enable_i = 0;
//timing
#4 rst_i = 0;
#2 rect_write_i = 1;
#2 rect_write_i = 0;
#100 line_write_i = 1;
#2 line_write_i = 0;
#100 triangle_write_i = 1;
#2 triangle_write_i = 0;
// end sim
#1000 $finish;
end
always begin
#1 clk_i = ~clk_i;
end
always @(posedge clk_i)
begin
clip_ack_i <= #1 clip_write_o;
interp_ack_i <= #1 interp_write_o;
end
gfx_rasterizer #(point_width, subpixel_width) raster(
.clk_i (clk_i),
.rst_i (rst_i),
.clip_ack_i (clip_ack_i),
.interp_ack_i (interp_ack_i),
.ack_o (ack_o),
.rect_write_i (rect_write_i),
.line_write_i (line_write_i),
.triangle_write_i (triangle_write_i),
.interpolate_i (interpolate_i),
.texture_enable_i (texture_enable_i),
.src_pixel0_x_i (src_pixel0_x_i),
.src_pixel0_y_i (src_pixel0_y_i),
.src_pixel1_x_i (src_pixel1_x_i),
.src_pixel1_y_i (src_pixel1_y_i),
.dest_pixel0_x_i (dest_pixel0_x_i),
.dest_pixel0_y_i (dest_pixel0_y_i),
.dest_pixel1_x_i (dest_pixel1_x_i),
.dest_pixel1_y_i (dest_pixel1_y_i),
.dest_pixel2_x_i (dest_pixel2_x_i),
.dest_pixel2_y_i (dest_pixel2_y_i),
.clipping_enable_i(clipping_enable_i),
.clip_pixel0_x_i (clip_pixel0_x_i),
.clip_pixel0_y_i (clip_pixel0_y_i),
.clip_pixel1_x_i (clip_pixel1_x_i),
.clip_pixel1_y_i (clip_pixel1_y_i),
.target_size_x_i (target_size_x_i),
.target_size_y_i (target_size_y_i),
.x_counter_o (x_counter_o),
.y_counter_o (y_counter_o),
.u_o (u_o),
.v_o (v_o),
.clip_write_o (clip_write_o),
.interp_write_o (interp_write_o)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O221AI_M_V
`define SKY130_FD_SC_LP__O221AI_M_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog wrapper for o221ai with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o221ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o221ai_m (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o221ai_m (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O221AI_M_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR3B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__OR3B_BEHAVIORAL_PP_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__or3b (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , C_N );
or or0 (or0_out_X , B, A, not0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR3B_BEHAVIORAL_PP_V |
// cic_dec_2.v: CIC Decimator - single
// 2016-07-17 E. Brombaugh
module cic_dec_2 #(
parameter NUM_STAGES = 4, // Stages of int / comb
STG_GSZ = 8, // Bit growth per stage
ISZ = 10, // Input word size
OSZ = (ISZ + (NUM_STAGES * STG_GSZ)) // Output word size
)
(
input clk, // System clock
input reset, // System POR
input ena_out, // Decimated output rate (2 clks wide)
input signed [ISZ-1:0] x, // Input data
output signed [OSZ-1:0] y, // Output data
output valid // Output Valid
);
// sign-extend input
wire signed [OSZ-1:0] x_sx = {{OSZ-ISZ{x[ISZ-1]}},x};
// Integrators
reg signed [OSZ-1:0] integrator[0:NUM_STAGES-1];
always @(posedge clk)
begin
if(reset == 1'b1)
begin
integrator[0] <= {OSZ{1'b0}};
end
else
begin
integrator[0] <= integrator[0] + x_sx;
end
end
generate
genvar i;
for(i=1;i<NUM_STAGES;i=i+1)
begin
always @(posedge clk)
begin
if(reset == 1'b1)
begin
integrator[i] <= {OSZ{1'b0}};
end
else
begin
integrator[i] <= integrator[i] + integrator[i-1];
end
end
end
endgenerate
// Combs
reg [NUM_STAGES:0] comb_ena;
reg signed [OSZ-1:0] comb_diff[0:NUM_STAGES];
reg signed [OSZ-1:0] comb_dly[0:NUM_STAGES];
always @(posedge clk)
begin
if(reset == 1'b1)
begin
comb_ena <= {NUM_STAGES+2{1'b0}};
comb_diff[0] <= {OSZ{1'b0}};
comb_dly[0] <= {OSZ{1'b0}};
end
else
begin
if(ena_out == 1'b1)
begin
comb_diff[0] <= integrator[NUM_STAGES-1];
comb_dly[0] <= comb_diff[0];
end
comb_ena <= {comb_ena[NUM_STAGES:0],ena_out};
end
end
generate
genvar j;
for(j=1;j<=NUM_STAGES;j=j+1)
begin
always @(posedge clk)
begin
if(reset == 1'b1)
begin
comb_diff[j] <= {OSZ{1'b0}};
comb_dly[j] <= {OSZ{1'b0}};
end
else if(comb_ena[j-1] == 1'b1)
begin
comb_diff[j] <= comb_diff[j-1] - comb_dly[j-1];
comb_dly[j] <= comb_diff[j];
end
end
end
endgenerate
// assign output
assign y = comb_diff[NUM_STAGES];
assign valid = comb_ena[NUM_STAGES];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX2I_BLACKBOX_V
`define SKY130_FD_SC_HS__MUX2I_BLACKBOX_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__mux2i (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX2I_BLACKBOX_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// Color Space Conversion, multiplier. This is a simple partial product adder
// that generates the product of the two inputs.
`timescale 1ps/1ps
module ad_csc_1_mul (
// data_a is signed
clk,
data_a,
data_b,
data_p,
// delay match
ddata_in,
ddata_out);
// parameters
parameter DELAY_DATA_WIDTH = 16;
localparam DW = DELAY_DATA_WIDTH - 1;
// data_a is signed
input clk;
input [16:0] data_a;
input [ 7:0] data_b;
output [24:0] data_p;
// delay match
input [DW:0] ddata_in;
output [DW:0] ddata_out;
// internal registers
reg p1_sign = 'd0;
reg [DW:0] p1_ddata = 'd0;
reg [23:0] p1_data_p_0 = 'd0;
reg [23:0] p1_data_p_1 = 'd0;
reg [23:0] p1_data_p_2 = 'd0;
reg [23:0] p1_data_p_3 = 'd0;
reg [23:0] p1_data_p_4 = 'd0;
reg p2_sign = 'd0;
reg [DW:0] p2_ddata = 'd0;
reg [23:0] p2_data_p_0 = 'd0;
reg [23:0] p2_data_p_1 = 'd0;
reg p3_sign = 'd0;
reg [DW:0] p3_ddata = 'd0;
reg [23:0] p3_data_p_0 = 'd0;
reg [DW:0] ddata_out = 'd0;
reg [24:0] data_p = 'd0;
// internal wires
wire [16:0] p1_data_a_1p_17_s;
wire [16:0] p1_data_a_1n_17_s;
wire [23:0] p1_data_a_1p_s;
wire [23:0] p1_data_a_1n_s;
wire [23:0] p1_data_a_2p_s;
wire [23:0] p1_data_a_2n_s;
// pipe line stage 1, get the two's complement versions
assign p1_data_a_1p_17_s = {1'b0, data_a[15:0]};
assign p1_data_a_1n_17_s = ~p1_data_a_1p_17_s + 1'b1;
assign p1_data_a_1p_s = {{7{p1_data_a_1p_17_s[16]}}, p1_data_a_1p_17_s};
assign p1_data_a_1n_s = {{7{p1_data_a_1n_17_s[16]}}, p1_data_a_1n_17_s};
assign p1_data_a_2p_s = {{6{p1_data_a_1p_17_s[16]}}, p1_data_a_1p_17_s, 1'b0};
assign p1_data_a_2n_s = {{6{p1_data_a_1n_17_s[16]}}, p1_data_a_1n_17_s, 1'b0};
// pipe line stage 1, get the partial products
always @(posedge clk) begin
p1_sign <= data_a[16];
p1_ddata <= ddata_in;
case (data_b[1:0])
2'b11: p1_data_p_0 <= p1_data_a_1n_s;
2'b10: p1_data_p_0 <= p1_data_a_2n_s;
2'b01: p1_data_p_0 <= p1_data_a_1p_s;
default: p1_data_p_0 <= 24'd0;
endcase
case (data_b[3:1])
3'b011: p1_data_p_1 <= {p1_data_a_2p_s[21:0], 2'd0};
3'b100: p1_data_p_1 <= {p1_data_a_2n_s[21:0], 2'd0};
3'b001: p1_data_p_1 <= {p1_data_a_1p_s[21:0], 2'd0};
3'b010: p1_data_p_1 <= {p1_data_a_1p_s[21:0], 2'd0};
3'b101: p1_data_p_1 <= {p1_data_a_1n_s[21:0], 2'd0};
3'b110: p1_data_p_1 <= {p1_data_a_1n_s[21:0], 2'd0};
default: p1_data_p_1 <= 24'd0;
endcase
case (data_b[5:3])
3'b011: p1_data_p_2 <= {p1_data_a_2p_s[19:0], 4'd0};
3'b100: p1_data_p_2 <= {p1_data_a_2n_s[19:0], 4'd0};
3'b001: p1_data_p_2 <= {p1_data_a_1p_s[19:0], 4'd0};
3'b010: p1_data_p_2 <= {p1_data_a_1p_s[19:0], 4'd0};
3'b101: p1_data_p_2 <= {p1_data_a_1n_s[19:0], 4'd0};
3'b110: p1_data_p_2 <= {p1_data_a_1n_s[19:0], 4'd0};
default: p1_data_p_2 <= 24'd0;
endcase
case (data_b[7:5])
3'b011: p1_data_p_3 <= {p1_data_a_2p_s[17:0], 6'd0};
3'b100: p1_data_p_3 <= {p1_data_a_2n_s[17:0], 6'd0};
3'b001: p1_data_p_3 <= {p1_data_a_1p_s[17:0], 6'd0};
3'b010: p1_data_p_3 <= {p1_data_a_1p_s[17:0], 6'd0};
3'b101: p1_data_p_3 <= {p1_data_a_1n_s[17:0], 6'd0};
3'b110: p1_data_p_3 <= {p1_data_a_1n_s[17:0], 6'd0};
default: p1_data_p_3 <= 24'd0;
endcase
case (data_b[7])
1'b1: p1_data_p_4 <= {p1_data_a_1p_s[15:0], 8'd0};
default: p1_data_p_4 <= 24'd0;
endcase
end
// pipe line stage 2, get the sum (intermediate 5 -> 2)
always @(posedge clk) begin
p2_sign <= p1_sign;
p2_ddata <= p1_ddata;
p2_data_p_0 <= p1_data_p_0 + p1_data_p_1 + p1_data_p_4;
p2_data_p_1 <= p1_data_p_2 + p1_data_p_3;
end
// pipe line stage 2, get the sum (final 2 -> 1)
always @(posedge clk) begin
p3_sign <= p2_sign;
p3_ddata <= p2_ddata;
p3_data_p_0 <= p2_data_p_0 + p2_data_p_1;
end
// output registers (truncation occurs after addition, see ad_csc_1_add.v)
always @(posedge clk) begin
ddata_out <= p3_ddata;
data_p <= {p3_sign, p3_data_p_0};
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
module ram0(
// Read port
input rdclk,
input [8:0] rdaddr,
output reg [63:0] do);
(* ram_style = "block" *) reg [63:0] ram[0:511];
genvar i;
generate
for (i=0; i<512; i=i+1)
begin
initial begin
ram[i] <= i | i << 16 | i << 32 | i << 48;
end
end
endgenerate
always @ (posedge rdclk) begin
do <= ram[rdaddr];
end
endmodule
module top (
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
reg nrst = 0;
wire tx_baud_edge;
wire rx_baud_edge;
// Data in.
wire [7:0] rx_data_wire;
wire rx_data_ready_wire;
// Data out.
wire tx_data_ready;
wire tx_data_accepted;
wire [7:0] tx_data;
assign led[14:0] = sw[14:0];
assign led[15] = rx_data_ready_wire ^ sw[15];
UART #(
.COUNTER(25),
.OVERSAMPLE(8)
) uart (
.clk(clk),
.rst(!nrst),
.rx(rx),
.tx(tx),
.tx_data_ready(tx_data_ready),
.tx_data(tx_data),
.tx_data_accepted(tx_data_accepted),
.rx_data(rx_data_wire),
.rx_data_ready(rx_data_ready_wire)
);
wire [8:0] read_address;
wire [63:0] read_data;
wire [8:0] rom_read_address;
reg [63:0] rom_read_data;
always @(posedge clk) rom_read_data <= {4{7'd0, rom_read_address}};
wire loop_complete;
wire error_detected;
wire [7:0] error_state;
wire [8:0] error_address;
wire [63:0] expected_data;
wire [63:0] actual_data;
ROM_TEST #(
.ADDR_WIDTH(9),
.DATA_WIDTH(64),
.ADDRESS_STEP(1),
.MAX_ADDRESS(511)
) dram_test (
.rst(!nrst),
.clk(clk),
// Memory connection
.read_data(read_data),
.read_address(read_address),
// INIT ROM connection
.rom_read_data(rom_read_data),
.rom_read_address(rom_read_address),
// Reporting
.loop_complete(loop_complete),
.error(error_detected),
.error_state(error_state),
.error_address(error_address),
.expected_data(expected_data),
.actual_data(actual_data)
);
ram0 #(
) bram (
// Read port
.rdclk(clk),
.rdaddr(read_address),
.do(read_data)
);
ERROR_OUTPUT_LOGIC #(
.DATA_WIDTH(64),
.ADDR_WIDTH(9)
) output_logic (
.clk(clk),
.rst(!nrst),
.loop_complete(loop_complete),
.error_detected(error_detected),
.error_state(error_state),
.error_address(error_address),
.expected_data(expected_data),
.actual_data(actual_data),
.tx_data(tx_data),
.tx_data_ready(tx_data_ready),
.tx_data_accepted(tx_data_accepted)
);
always @(posedge clk) begin
nrst <= 1;
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Apr 09 07:03:52 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_ov7670_controller_1_0_1/system_ov7670_controller_1_0_sim_netlist.v
// Design : system_ov7670_controller_1_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_ov7670_controller_1_0,ov7670_controller,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "ov7670_controller,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_ov7670_controller_1_0
(clk,
resend,
config_finished,
sioc,
siod,
reset,
pwdn,
xclk);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
input resend;
output config_finished;
output sioc;
inout siod;
(* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) output reset;
output pwdn;
output xclk;
wire \<const0> ;
wire \<const1> ;
wire clk;
wire config_finished;
wire resend;
wire sioc;
wire siod;
wire xclk;
assign pwdn = \<const0> ;
assign reset = \<const1> ;
GND GND
(.G(\<const0> ));
system_ov7670_controller_1_0_ov7670_controller U0
(.clk(clk),
.config_finished(config_finished),
.resend(resend),
.sioc(sioc),
.siod(siod),
.xclk(xclk));
VCC VCC
(.P(\<const1> ));
endmodule
(* ORIG_REF_NAME = "i2c_sender" *)
module system_ov7670_controller_1_0_i2c_sender
(E,
sioc,
p_0_in,
\busy_sr_reg[1]_0 ,
siod,
\busy_sr_reg[31]_0 ,
clk,
p_1_in,
DOADO,
\busy_sr_reg[31]_1 );
output [0:0]E;
output sioc;
output p_0_in;
output \busy_sr_reg[1]_0 ;
output siod;
input \busy_sr_reg[31]_0 ;
input clk;
input [0:0]p_1_in;
input [15:0]DOADO;
input [0:0]\busy_sr_reg[31]_1 ;
wire [15:0]DOADO;
wire [0:0]E;
wire busy_sr0;
wire \busy_sr[0]_i_3_n_0 ;
wire \busy_sr[0]_i_5_n_0 ;
wire \busy_sr[10]_i_1_n_0 ;
wire \busy_sr[11]_i_1_n_0 ;
wire \busy_sr[12]_i_1_n_0 ;
wire \busy_sr[13]_i_1_n_0 ;
wire \busy_sr[14]_i_1_n_0 ;
wire \busy_sr[15]_i_1_n_0 ;
wire \busy_sr[16]_i_1_n_0 ;
wire \busy_sr[17]_i_1_n_0 ;
wire \busy_sr[18]_i_1_n_0 ;
wire \busy_sr[19]_i_1_n_0 ;
wire \busy_sr[1]_i_1_n_0 ;
wire \busy_sr[20]_i_1_n_0 ;
wire \busy_sr[21]_i_1_n_0 ;
wire \busy_sr[22]_i_1_n_0 ;
wire \busy_sr[23]_i_1_n_0 ;
wire \busy_sr[24]_i_1_n_0 ;
wire \busy_sr[25]_i_1_n_0 ;
wire \busy_sr[26]_i_1_n_0 ;
wire \busy_sr[27]_i_1_n_0 ;
wire \busy_sr[28]_i_1_n_0 ;
wire \busy_sr[29]_i_1_n_0 ;
wire \busy_sr[2]_i_1_n_0 ;
wire \busy_sr[30]_i_1_n_0 ;
wire \busy_sr[31]_i_1_n_0 ;
wire \busy_sr[31]_i_2_n_0 ;
wire \busy_sr[3]_i_1_n_0 ;
wire \busy_sr[4]_i_1_n_0 ;
wire \busy_sr[5]_i_1_n_0 ;
wire \busy_sr[6]_i_1_n_0 ;
wire \busy_sr[7]_i_1_n_0 ;
wire \busy_sr[8]_i_1_n_0 ;
wire \busy_sr[9]_i_1_n_0 ;
wire \busy_sr_reg[1]_0 ;
wire \busy_sr_reg[31]_0 ;
wire [0:0]\busy_sr_reg[31]_1 ;
wire \busy_sr_reg_n_0_[0] ;
wire \busy_sr_reg_n_0_[10] ;
wire \busy_sr_reg_n_0_[11] ;
wire \busy_sr_reg_n_0_[12] ;
wire \busy_sr_reg_n_0_[13] ;
wire \busy_sr_reg_n_0_[14] ;
wire \busy_sr_reg_n_0_[15] ;
wire \busy_sr_reg_n_0_[16] ;
wire \busy_sr_reg_n_0_[17] ;
wire \busy_sr_reg_n_0_[18] ;
wire \busy_sr_reg_n_0_[1] ;
wire \busy_sr_reg_n_0_[21] ;
wire \busy_sr_reg_n_0_[22] ;
wire \busy_sr_reg_n_0_[23] ;
wire \busy_sr_reg_n_0_[24] ;
wire \busy_sr_reg_n_0_[25] ;
wire \busy_sr_reg_n_0_[26] ;
wire \busy_sr_reg_n_0_[27] ;
wire \busy_sr_reg_n_0_[28] ;
wire \busy_sr_reg_n_0_[29] ;
wire \busy_sr_reg_n_0_[2] ;
wire \busy_sr_reg_n_0_[30] ;
wire \busy_sr_reg_n_0_[3] ;
wire \busy_sr_reg_n_0_[4] ;
wire \busy_sr_reg_n_0_[5] ;
wire \busy_sr_reg_n_0_[6] ;
wire \busy_sr_reg_n_0_[7] ;
wire \busy_sr_reg_n_0_[8] ;
wire \busy_sr_reg_n_0_[9] ;
wire clk;
wire \data_sr[10]_i_1_n_0 ;
wire \data_sr[12]_i_1_n_0 ;
wire \data_sr[13]_i_1_n_0 ;
wire \data_sr[14]_i_1_n_0 ;
wire \data_sr[15]_i_1_n_0 ;
wire \data_sr[16]_i_1_n_0 ;
wire \data_sr[17]_i_1_n_0 ;
wire \data_sr[18]_i_1_n_0 ;
wire \data_sr[19]_i_1_n_0 ;
wire \data_sr[22]_i_1_n_0 ;
wire \data_sr[27]_i_1_n_0 ;
wire \data_sr[30]_i_1_n_0 ;
wire \data_sr[31]_i_1_n_0 ;
wire \data_sr[31]_i_2_n_0 ;
wire \data_sr[3]_i_1_n_0 ;
wire \data_sr[4]_i_1_n_0 ;
wire \data_sr[5]_i_1_n_0 ;
wire \data_sr[6]_i_1_n_0 ;
wire \data_sr[7]_i_1_n_0 ;
wire \data_sr[8]_i_1_n_0 ;
wire \data_sr[9]_i_1_n_0 ;
wire \data_sr_reg_n_0_[10] ;
wire \data_sr_reg_n_0_[11] ;
wire \data_sr_reg_n_0_[12] ;
wire \data_sr_reg_n_0_[13] ;
wire \data_sr_reg_n_0_[14] ;
wire \data_sr_reg_n_0_[15] ;
wire \data_sr_reg_n_0_[16] ;
wire \data_sr_reg_n_0_[17] ;
wire \data_sr_reg_n_0_[18] ;
wire \data_sr_reg_n_0_[19] ;
wire \data_sr_reg_n_0_[1] ;
wire \data_sr_reg_n_0_[20] ;
wire \data_sr_reg_n_0_[21] ;
wire \data_sr_reg_n_0_[22] ;
wire \data_sr_reg_n_0_[23] ;
wire \data_sr_reg_n_0_[24] ;
wire \data_sr_reg_n_0_[25] ;
wire \data_sr_reg_n_0_[26] ;
wire \data_sr_reg_n_0_[27] ;
wire \data_sr_reg_n_0_[28] ;
wire \data_sr_reg_n_0_[29] ;
wire \data_sr_reg_n_0_[2] ;
wire \data_sr_reg_n_0_[30] ;
wire \data_sr_reg_n_0_[31] ;
wire \data_sr_reg_n_0_[3] ;
wire \data_sr_reg_n_0_[4] ;
wire \data_sr_reg_n_0_[5] ;
wire \data_sr_reg_n_0_[6] ;
wire \data_sr_reg_n_0_[7] ;
wire \data_sr_reg_n_0_[8] ;
wire \data_sr_reg_n_0_[9] ;
wire [7:6]divider_reg__0;
wire [5:0]divider_reg__1;
wire p_0_in;
wire [7:0]p_0_in__0;
wire [0:0]p_1_in;
wire [1:0]p_1_in_0;
wire sioc;
wire sioc_i_1_n_0;
wire sioc_i_2_n_0;
wire sioc_i_3_n_0;
wire sioc_i_4_n_0;
wire sioc_i_5_n_0;
wire siod;
wire siod_INST_0_i_1_n_0;
LUT6 #(
.INIT(64'h4000FFFF40004000))
\busy_sr[0]_i_1
(.I0(\busy_sr[0]_i_3_n_0 ),
.I1(divider_reg__0[6]),
.I2(divider_reg__0[7]),
.I3(p_0_in),
.I4(\busy_sr_reg[1]_0 ),
.I5(p_1_in),
.O(busy_sr0));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\busy_sr[0]_i_3
(.I0(divider_reg__1[4]),
.I1(divider_reg__1[2]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[1]),
.I4(divider_reg__1[3]),
.I5(divider_reg__1[5]),
.O(\busy_sr[0]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\busy_sr[0]_i_4
(.I0(divider_reg__1[2]),
.I1(divider_reg__1[3]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[1]),
.I4(\busy_sr[0]_i_5_n_0 ),
.O(\busy_sr_reg[1]_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'hFFFE))
\busy_sr[0]_i_5
(.I0(divider_reg__1[5]),
.I1(divider_reg__1[4]),
.I2(divider_reg__0[7]),
.I3(divider_reg__0[6]),
.O(\busy_sr[0]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[10]_i_1
(.I0(\busy_sr_reg_n_0_[9] ),
.I1(p_0_in),
.O(\busy_sr[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[11]_i_1
(.I0(\busy_sr_reg_n_0_[10] ),
.I1(p_0_in),
.O(\busy_sr[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[12]_i_1
(.I0(\busy_sr_reg_n_0_[11] ),
.I1(p_0_in),
.O(\busy_sr[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[13]_i_1
(.I0(\busy_sr_reg_n_0_[12] ),
.I1(p_0_in),
.O(\busy_sr[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[14]_i_1
(.I0(\busy_sr_reg_n_0_[13] ),
.I1(p_0_in),
.O(\busy_sr[14]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[15]_i_1
(.I0(\busy_sr_reg_n_0_[14] ),
.I1(p_0_in),
.O(\busy_sr[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[16]_i_1
(.I0(\busy_sr_reg_n_0_[15] ),
.I1(p_0_in),
.O(\busy_sr[16]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[17]_i_1
(.I0(\busy_sr_reg_n_0_[16] ),
.I1(p_0_in),
.O(\busy_sr[17]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[18]_i_1
(.I0(\busy_sr_reg_n_0_[17] ),
.I1(p_0_in),
.O(\busy_sr[18]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[19]_i_1
(.I0(\busy_sr_reg_n_0_[18] ),
.I1(p_0_in),
.O(\busy_sr[19]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[1]_i_1
(.I0(\busy_sr_reg_n_0_[0] ),
.I1(p_0_in),
.O(\busy_sr[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[20]_i_1
(.I0(p_1_in_0[0]),
.I1(p_0_in),
.O(\busy_sr[20]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[21]_i_1
(.I0(p_1_in_0[1]),
.I1(p_0_in),
.O(\busy_sr[21]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[22]_i_1
(.I0(\busy_sr_reg_n_0_[21] ),
.I1(p_0_in),
.O(\busy_sr[22]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[23]_i_1
(.I0(\busy_sr_reg_n_0_[22] ),
.I1(p_0_in),
.O(\busy_sr[23]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[24]_i_1
(.I0(\busy_sr_reg_n_0_[23] ),
.I1(p_0_in),
.O(\busy_sr[24]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[25]_i_1
(.I0(\busy_sr_reg_n_0_[24] ),
.I1(p_0_in),
.O(\busy_sr[25]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[26]_i_1
(.I0(\busy_sr_reg_n_0_[25] ),
.I1(p_0_in),
.O(\busy_sr[26]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[27]_i_1
(.I0(\busy_sr_reg_n_0_[26] ),
.I1(p_0_in),
.O(\busy_sr[27]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[28]_i_1
(.I0(\busy_sr_reg_n_0_[27] ),
.I1(p_0_in),
.O(\busy_sr[28]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[29]_i_1
(.I0(\busy_sr_reg_n_0_[28] ),
.I1(p_0_in),
.O(\busy_sr[29]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[2]_i_1
(.I0(\busy_sr_reg_n_0_[1] ),
.I1(p_0_in),
.O(\busy_sr[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[30]_i_1
(.I0(\busy_sr_reg_n_0_[29] ),
.I1(p_0_in),
.O(\busy_sr[30]_i_1_n_0 ));
LUT6 #(
.INIT(64'h22222222A2222222))
\busy_sr[31]_i_1
(.I0(p_1_in),
.I1(\busy_sr_reg[1]_0 ),
.I2(p_0_in),
.I3(divider_reg__0[7]),
.I4(divider_reg__0[6]),
.I5(\busy_sr[0]_i_3_n_0 ),
.O(\busy_sr[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[31]_i_2
(.I0(p_0_in),
.I1(\busy_sr_reg_n_0_[30] ),
.O(\busy_sr[31]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[3]_i_1
(.I0(\busy_sr_reg_n_0_[2] ),
.I1(p_0_in),
.O(\busy_sr[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[4]_i_1
(.I0(\busy_sr_reg_n_0_[3] ),
.I1(p_0_in),
.O(\busy_sr[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[5]_i_1
(.I0(\busy_sr_reg_n_0_[4] ),
.I1(p_0_in),
.O(\busy_sr[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[6]_i_1
(.I0(\busy_sr_reg_n_0_[5] ),
.I1(p_0_in),
.O(\busy_sr[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[7]_i_1
(.I0(\busy_sr_reg_n_0_[6] ),
.I1(p_0_in),
.O(\busy_sr[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[8]_i_1
(.I0(\busy_sr_reg_n_0_[7] ),
.I1(p_0_in),
.O(\busy_sr[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[9]_i_1
(.I0(\busy_sr_reg_n_0_[8] ),
.I1(p_0_in),
.O(\busy_sr[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\busy_sr_reg[0]
(.C(clk),
.CE(busy_sr0),
.D(p_1_in),
.Q(\busy_sr_reg_n_0_[0] ),
.R(1'b0));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[10]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[10]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[10] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[11]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[11]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[11] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[12]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[12]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[12] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[13]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[13]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[13] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[14]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[14]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[14] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[15]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[15]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[15] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[16]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[16]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[16] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[17]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[17]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[17] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[18]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[18]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[18] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[19]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[19]_i_1_n_0 ),
.Q(p_1_in_0[0]),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[1]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[1]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[1] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[20]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[20]_i_1_n_0 ),
.Q(p_1_in_0[1]),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[21]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[21]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[21] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[22]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[22]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[22] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[23]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[23]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[23] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[24]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[24]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[24] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[25]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[25]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[25] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[26]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[26]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[26] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[27]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[27]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[27] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[28]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[28]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[28] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[29]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[29]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[29] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[2]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[2]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[2] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[30]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[30]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[30] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[31]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[31]_i_2_n_0 ),
.Q(p_0_in),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[3]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[3]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[3] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[4]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[4]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[4] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[5]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[5]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[5] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[6]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[6]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[6] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[7]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[7]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[7] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[8]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[8]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[8] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[9]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[9]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[9] ),
.S(\busy_sr[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[10]_i_1
(.I0(\data_sr_reg_n_0_[9] ),
.I1(p_0_in),
.I2(DOADO[7]),
.O(\data_sr[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[12]_i_1
(.I0(\data_sr_reg_n_0_[11] ),
.I1(p_0_in),
.I2(DOADO[8]),
.O(\data_sr[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[13]_i_1
(.I0(\data_sr_reg_n_0_[12] ),
.I1(p_0_in),
.I2(DOADO[9]),
.O(\data_sr[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[14]_i_1
(.I0(\data_sr_reg_n_0_[13] ),
.I1(p_0_in),
.I2(DOADO[10]),
.O(\data_sr[14]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[15]_i_1
(.I0(\data_sr_reg_n_0_[14] ),
.I1(p_0_in),
.I2(DOADO[11]),
.O(\data_sr[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[16]_i_1
(.I0(\data_sr_reg_n_0_[15] ),
.I1(p_0_in),
.I2(DOADO[12]),
.O(\data_sr[16]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[17]_i_1
(.I0(\data_sr_reg_n_0_[16] ),
.I1(p_0_in),
.I2(DOADO[13]),
.O(\data_sr[17]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[18]_i_1
(.I0(\data_sr_reg_n_0_[17] ),
.I1(p_0_in),
.I2(DOADO[14]),
.O(\data_sr[18]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[19]_i_1
(.I0(\data_sr_reg_n_0_[18] ),
.I1(p_0_in),
.I2(DOADO[15]),
.O(\data_sr[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFCFCFCFAACAAAAA))
\data_sr[22]_i_1
(.I0(\data_sr_reg_n_0_[22] ),
.I1(\data_sr_reg_n_0_[21] ),
.I2(p_0_in),
.I3(\data_sr[31]_i_2_n_0 ),
.I4(divider_reg__0[7]),
.I5(\busy_sr_reg[31]_0 ),
.O(\data_sr[22]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFCFCFCFAACAAAAA))
\data_sr[27]_i_1
(.I0(\data_sr_reg_n_0_[27] ),
.I1(\data_sr_reg_n_0_[26] ),
.I2(p_0_in),
.I3(\data_sr[31]_i_2_n_0 ),
.I4(divider_reg__0[7]),
.I5(\busy_sr_reg[31]_0 ),
.O(\data_sr[27]_i_1_n_0 ));
LUT3 #(
.INIT(8'h02))
\data_sr[30]_i_1
(.I0(p_1_in),
.I1(\busy_sr_reg[1]_0 ),
.I2(p_0_in),
.O(\data_sr[30]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFCFCFCFAACAAAAA))
\data_sr[31]_i_1
(.I0(\data_sr_reg_n_0_[31] ),
.I1(\data_sr_reg_n_0_[30] ),
.I2(p_0_in),
.I3(\data_sr[31]_i_2_n_0 ),
.I4(divider_reg__0[7]),
.I5(\busy_sr_reg[31]_0 ),
.O(\data_sr[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'hB))
\data_sr[31]_i_2
(.I0(\busy_sr[0]_i_3_n_0 ),
.I1(divider_reg__0[6]),
.O(\data_sr[31]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[3]_i_1
(.I0(\data_sr_reg_n_0_[2] ),
.I1(p_0_in),
.I2(DOADO[0]),
.O(\data_sr[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[4]_i_1
(.I0(\data_sr_reg_n_0_[3] ),
.I1(p_0_in),
.I2(DOADO[1]),
.O(\data_sr[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[5]_i_1
(.I0(\data_sr_reg_n_0_[4] ),
.I1(p_0_in),
.I2(DOADO[2]),
.O(\data_sr[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[6]_i_1
(.I0(\data_sr_reg_n_0_[5] ),
.I1(p_0_in),
.I2(DOADO[3]),
.O(\data_sr[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[7]_i_1
(.I0(\data_sr_reg_n_0_[6] ),
.I1(p_0_in),
.I2(DOADO[4]),
.O(\data_sr[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[8]_i_1
(.I0(\data_sr_reg_n_0_[7] ),
.I1(p_0_in),
.I2(DOADO[5]),
.O(\data_sr[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[9]_i_1
(.I0(\data_sr_reg_n_0_[8] ),
.I1(p_0_in),
.I2(DOADO[6]),
.O(\data_sr[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[10]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[10]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[11]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[10] ),
.Q(\data_sr_reg_n_0_[11] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[12]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[12]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[13]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[13]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[14]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[14]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[15]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[15]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[16]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[16]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[16] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[17]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[17]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[17] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[18]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[18]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[18] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[19]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[19]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[19] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[1]
(.C(clk),
.CE(busy_sr0),
.D(p_0_in),
.Q(\data_sr_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[20]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[19] ),
.Q(\data_sr_reg_n_0_[20] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[21]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[20] ),
.Q(\data_sr_reg_n_0_[21] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[22]
(.C(clk),
.CE(1'b1),
.D(\data_sr[22]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[22] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[23]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[22] ),
.Q(\data_sr_reg_n_0_[23] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[24]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[23] ),
.Q(\data_sr_reg_n_0_[24] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[25]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[24] ),
.Q(\data_sr_reg_n_0_[25] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[26]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[25] ),
.Q(\data_sr_reg_n_0_[26] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[27]
(.C(clk),
.CE(1'b1),
.D(\data_sr[27]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[27] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[28]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[27] ),
.Q(\data_sr_reg_n_0_[28] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[29]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[28] ),
.Q(\data_sr_reg_n_0_[29] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[2]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[1] ),
.Q(\data_sr_reg_n_0_[2] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[30]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[29] ),
.Q(\data_sr_reg_n_0_[30] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[31]
(.C(clk),
.CE(1'b1),
.D(\data_sr[31]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[31] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[3]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[3]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[4]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[4]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[5]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[5]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[6]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[6]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[7]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[7]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[8]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[8]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[9]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[9]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[9] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT1 #(
.INIT(2'h1))
\divider[0]_i_1
(.I0(divider_reg__1[0]),
.O(p_0_in__0[0]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'h6))
\divider[1]_i_1
(.I0(divider_reg__1[0]),
.I1(divider_reg__1[1]),
.O(p_0_in__0[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h78))
\divider[2]_i_1
(.I0(divider_reg__1[1]),
.I1(divider_reg__1[0]),
.I2(divider_reg__1[2]),
.O(p_0_in__0[2]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7F80))
\divider[3]_i_1
(.I0(divider_reg__1[2]),
.I1(divider_reg__1[0]),
.I2(divider_reg__1[1]),
.I3(divider_reg__1[3]),
.O(p_0_in__0[3]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h7FFF8000))
\divider[4]_i_1
(.I0(divider_reg__1[3]),
.I1(divider_reg__1[1]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[2]),
.I4(divider_reg__1[4]),
.O(p_0_in__0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\divider[5]_i_1
(.I0(divider_reg__1[4]),
.I1(divider_reg__1[2]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[1]),
.I4(divider_reg__1[3]),
.I5(divider_reg__1[5]),
.O(p_0_in__0[5]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'h9))
\divider[6]_i_1
(.I0(\busy_sr[0]_i_3_n_0 ),
.I1(divider_reg__0[6]),
.O(p_0_in__0[6]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hD2))
\divider[7]_i_2
(.I0(divider_reg__0[6]),
.I1(\busy_sr[0]_i_3_n_0 ),
.I2(divider_reg__0[7]),
.O(p_0_in__0[7]));
FDRE #(
.INIT(1'b1))
\divider_reg[0]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[0]),
.Q(divider_reg__1[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[1]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[1]),
.Q(divider_reg__1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[2]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[2]),
.Q(divider_reg__1[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[3]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[3]),
.Q(divider_reg__1[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[4]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[4]),
.Q(divider_reg__1[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[5]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[5]),
.Q(divider_reg__1[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[6]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[6]),
.Q(divider_reg__0[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[7]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[7]),
.Q(divider_reg__0[7]),
.R(1'b0));
LUT6 #(
.INIT(64'hFCFCFFF8FFFFFFFF))
sioc_i_1
(.I0(\busy_sr_reg_n_0_[0] ),
.I1(sioc_i_2_n_0),
.I2(sioc_i_3_n_0),
.I3(\busy_sr_reg_n_0_[1] ),
.I4(sioc_i_4_n_0),
.I5(p_0_in),
.O(sioc_i_1_n_0));
LUT2 #(
.INIT(4'h6))
sioc_i_2
(.I0(divider_reg__0[6]),
.I1(divider_reg__0[7]),
.O(sioc_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hA222))
sioc_i_3
(.I0(sioc_i_5_n_0),
.I1(\busy_sr_reg_n_0_[30] ),
.I2(divider_reg__0[6]),
.I3(p_0_in),
.O(sioc_i_3_n_0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h7FFF))
sioc_i_4
(.I0(\busy_sr_reg_n_0_[29] ),
.I1(\busy_sr_reg_n_0_[2] ),
.I2(p_0_in),
.I3(\busy_sr_reg_n_0_[30] ),
.O(sioc_i_4_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0001))
sioc_i_5
(.I0(\busy_sr_reg_n_0_[0] ),
.I1(\busy_sr_reg_n_0_[1] ),
.I2(\busy_sr_reg_n_0_[29] ),
.I3(\busy_sr_reg_n_0_[2] ),
.O(sioc_i_5_n_0));
FDRE sioc_reg
(.C(clk),
.CE(1'b1),
.D(sioc_i_1_n_0),
.Q(sioc),
.R(1'b0));
LUT2 #(
.INIT(4'h8))
siod_INST_0
(.I0(\data_sr_reg_n_0_[31] ),
.I1(siod_INST_0_i_1_n_0),
.O(siod));
LUT6 #(
.INIT(64'hB0BBB0BB0000B0BB))
siod_INST_0_i_1
(.I0(\busy_sr_reg_n_0_[28] ),
.I1(\busy_sr_reg_n_0_[29] ),
.I2(p_1_in_0[0]),
.I3(p_1_in_0[1]),
.I4(\busy_sr_reg_n_0_[11] ),
.I5(\busy_sr_reg_n_0_[10] ),
.O(siod_INST_0_i_1_n_0));
FDRE taken_reg
(.C(clk),
.CE(1'b1),
.D(\busy_sr_reg[31]_0 ),
.Q(E),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "ov7670_controller" *)
module system_ov7670_controller_1_0_ov7670_controller
(config_finished,
siod,
xclk,
sioc,
resend,
clk);
output config_finished;
output siod;
output xclk;
output sioc;
input resend;
input clk;
wire Inst_i2c_sender_n_3;
wire Inst_ov7670_registers_n_16;
wire Inst_ov7670_registers_n_18;
wire clk;
wire config_finished;
wire p_0_in;
wire [0:0]p_1_in;
wire resend;
wire sioc;
wire siod;
wire [15:0]sreg_reg;
wire sys_clk_i_1_n_0;
wire taken;
wire xclk;
system_ov7670_controller_1_0_i2c_sender Inst_i2c_sender
(.DOADO(sreg_reg),
.E(taken),
.\busy_sr_reg[1]_0 (Inst_i2c_sender_n_3),
.\busy_sr_reg[31]_0 (Inst_ov7670_registers_n_18),
.\busy_sr_reg[31]_1 (Inst_ov7670_registers_n_16),
.clk(clk),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.sioc(sioc),
.siod(siod));
system_ov7670_controller_1_0_ov7670_registers Inst_ov7670_registers
(.DOADO(sreg_reg),
.E(taken),
.clk(clk),
.config_finished(config_finished),
.\divider_reg[2] (Inst_i2c_sender_n_3),
.\divider_reg[7] (Inst_ov7670_registers_n_16),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.resend(resend),
.taken_reg(Inst_ov7670_registers_n_18));
LUT1 #(
.INIT(2'h1))
sys_clk_i_1
(.I0(xclk),
.O(sys_clk_i_1_n_0));
FDRE #(
.INIT(1'b0))
sys_clk_reg
(.C(clk),
.CE(1'b1),
.D(sys_clk_i_1_n_0),
.Q(xclk),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "ov7670_registers" *)
module system_ov7670_controller_1_0_ov7670_registers
(DOADO,
\divider_reg[7] ,
config_finished,
taken_reg,
p_1_in,
clk,
\divider_reg[2] ,
p_0_in,
resend,
E);
output [15:0]DOADO;
output [0:0]\divider_reg[7] ;
output config_finished;
output taken_reg;
output [0:0]p_1_in;
input clk;
input \divider_reg[2] ;
input p_0_in;
input resend;
input [0:0]E;
wire [15:0]DOADO;
wire [0:0]E;
wire [7:0]address;
wire [7:0]address_reg__0;
wire \address_rep[0]_i_1_n_0 ;
wire \address_rep[1]_i_1_n_0 ;
wire \address_rep[2]_i_1_n_0 ;
wire \address_rep[3]_i_1_n_0 ;
wire \address_rep[4]_i_1_n_0 ;
wire \address_rep[5]_i_1_n_0 ;
wire \address_rep[6]_i_1_n_0 ;
wire \address_rep[7]_i_1_n_0 ;
wire \address_rep[7]_i_2_n_0 ;
wire clk;
wire config_finished;
wire config_finished_INST_0_i_1_n_0;
wire config_finished_INST_0_i_2_n_0;
wire config_finished_INST_0_i_3_n_0;
wire config_finished_INST_0_i_4_n_0;
wire \divider_reg[2] ;
wire [0:0]\divider_reg[7] ;
wire p_0_in;
wire [0:0]p_1_in;
wire resend;
wire taken_reg;
wire [15:0]NLW_sreg_reg_DOBDO_UNCONNECTED;
wire [1:0]NLW_sreg_reg_DOPADOP_UNCONNECTED;
wire [1:0]NLW_sreg_reg_DOPBDOP_UNCONNECTED;
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[0]
(.C(clk),
.CE(E),
.D(\address_rep[0]_i_1_n_0 ),
.Q(address_reg__0[0]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[1]
(.C(clk),
.CE(E),
.D(\address_rep[1]_i_1_n_0 ),
.Q(address_reg__0[1]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[2]
(.C(clk),
.CE(E),
.D(\address_rep[2]_i_1_n_0 ),
.Q(address_reg__0[2]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[3]
(.C(clk),
.CE(E),
.D(\address_rep[3]_i_1_n_0 ),
.Q(address_reg__0[3]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[4]
(.C(clk),
.CE(E),
.D(\address_rep[4]_i_1_n_0 ),
.Q(address_reg__0[4]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[5]
(.C(clk),
.CE(E),
.D(\address_rep[5]_i_1_n_0 ),
.Q(address_reg__0[5]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[6]
(.C(clk),
.CE(E),
.D(\address_rep[6]_i_1_n_0 ),
.Q(address_reg__0[6]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[7]
(.C(clk),
.CE(E),
.D(\address_rep[7]_i_1_n_0 ),
.Q(address_reg__0[7]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[0]
(.C(clk),
.CE(E),
.D(\address_rep[0]_i_1_n_0 ),
.Q(address[0]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[1]
(.C(clk),
.CE(E),
.D(\address_rep[1]_i_1_n_0 ),
.Q(address[1]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[2]
(.C(clk),
.CE(E),
.D(\address_rep[2]_i_1_n_0 ),
.Q(address[2]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[3]
(.C(clk),
.CE(E),
.D(\address_rep[3]_i_1_n_0 ),
.Q(address[3]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[4]
(.C(clk),
.CE(E),
.D(\address_rep[4]_i_1_n_0 ),
.Q(address[4]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[5]
(.C(clk),
.CE(E),
.D(\address_rep[5]_i_1_n_0 ),
.Q(address[5]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[6]
(.C(clk),
.CE(E),
.D(\address_rep[6]_i_1_n_0 ),
.Q(address[6]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[7]
(.C(clk),
.CE(E),
.D(\address_rep[7]_i_1_n_0 ),
.Q(address[7]),
.R(resend));
LUT1 #(
.INIT(2'h1))
\address_rep[0]_i_1
(.I0(address_reg__0[0]),
.O(\address_rep[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT2 #(
.INIT(4'h6))
\address_rep[1]_i_1
(.I0(address_reg__0[0]),
.I1(address_reg__0[1]),
.O(\address_rep[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'h78))
\address_rep[2]_i_1
(.I0(address_reg__0[1]),
.I1(address_reg__0[0]),
.I2(address_reg__0[2]),
.O(\address_rep[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT4 #(
.INIT(16'h7F80))
\address_rep[3]_i_1
(.I0(address_reg__0[2]),
.I1(address_reg__0[0]),
.I2(address_reg__0[1]),
.I3(address_reg__0[3]),
.O(\address_rep[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT5 #(
.INIT(32'h7FFF8000))
\address_rep[4]_i_1
(.I0(address_reg__0[3]),
.I1(address_reg__0[1]),
.I2(address_reg__0[0]),
.I3(address_reg__0[2]),
.I4(address_reg__0[4]),
.O(\address_rep[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\address_rep[5]_i_1
(.I0(address_reg__0[4]),
.I1(address_reg__0[2]),
.I2(address_reg__0[0]),
.I3(address_reg__0[1]),
.I4(address_reg__0[3]),
.I5(address_reg__0[5]),
.O(\address_rep[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT2 #(
.INIT(4'h9))
\address_rep[6]_i_1
(.I0(\address_rep[7]_i_2_n_0 ),
.I1(address_reg__0[6]),
.O(\address_rep[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hD2))
\address_rep[7]_i_1
(.I0(address_reg__0[6]),
.I1(\address_rep[7]_i_2_n_0 ),
.I2(address_reg__0[7]),
.O(\address_rep[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\address_rep[7]_i_2
(.I0(address_reg__0[4]),
.I1(address_reg__0[2]),
.I2(address_reg__0[0]),
.I3(address_reg__0[1]),
.I4(address_reg__0[3]),
.I5(address_reg__0[5]),
.O(\address_rep[7]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT5 #(
.INIT(32'h0000FFFE))
\busy_sr[0]_i_2
(.I0(config_finished_INST_0_i_4_n_0),
.I1(config_finished_INST_0_i_3_n_0),
.I2(config_finished_INST_0_i_2_n_0),
.I3(config_finished_INST_0_i_1_n_0),
.I4(p_0_in),
.O(p_1_in));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT4 #(
.INIT(16'h0001))
config_finished_INST_0
(.I0(config_finished_INST_0_i_1_n_0),
.I1(config_finished_INST_0_i_2_n_0),
.I2(config_finished_INST_0_i_3_n_0),
.I3(config_finished_INST_0_i_4_n_0),
.O(config_finished));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_1
(.I0(DOADO[5]),
.I1(DOADO[4]),
.I2(DOADO[7]),
.I3(DOADO[6]),
.O(config_finished_INST_0_i_1_n_0));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_2
(.I0(DOADO[1]),
.I1(DOADO[0]),
.I2(DOADO[3]),
.I3(DOADO[2]),
.O(config_finished_INST_0_i_2_n_0));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_3
(.I0(DOADO[13]),
.I1(DOADO[12]),
.I2(DOADO[15]),
.I3(DOADO[14]),
.O(config_finished_INST_0_i_3_n_0));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_4
(.I0(DOADO[9]),
.I1(DOADO[8]),
.I2(DOADO[11]),
.I3(DOADO[10]),
.O(config_finished_INST_0_i_4_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFE0000))
\divider[7]_i_1
(.I0(config_finished_INST_0_i_1_n_0),
.I1(config_finished_INST_0_i_2_n_0),
.I2(config_finished_INST_0_i_3_n_0),
.I3(config_finished_INST_0_i_4_n_0),
.I4(\divider_reg[2] ),
.I5(p_0_in),
.O(\divider_reg[7] ));
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d16" *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* RTL_RAM_BITS = "4096" *)
(* RTL_RAM_NAME = "U0/Inst_ov7670_registers/sreg" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "1023" *)
(* bram_slice_begin = "0" *)
(* bram_slice_end = "15" *)
RAMB18E1 #(
.DOA_REG(0),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h53295217510C50344F4014383A04401004008C003E000C001100120412801280),
.INIT_01(256'h229121021E3716020F4B0E61030A1A7B190332A41861171111003DC0581E5440),
.INIT_02(256'h90008F008E008D4F74106B4A69004E204D403C78392A3871371D350B330B2907),
.INIT_03(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB80AB382B20EB10CB0849A0096009100),
.INIT_04(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_05(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_06(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_07(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_08(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_09(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(0))
sreg_reg
(.ADDRARDADDR({1'b0,1'b0,address,1'b0,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CLKARDCLK(clk),
.CLKBWRCLK(1'b0),
.DIADI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1}),
.DOADO(DOADO),
.DOBDO(NLW_sreg_reg_DOBDO_UNCONNECTED[15:0]),
.DOPADOP(NLW_sreg_reg_DOPADOP_UNCONNECTED[1:0]),
.DOPBDOP(NLW_sreg_reg_DOPBDOP_UNCONNECTED[1:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
LUT6 #(
.INIT(64'h0000000055555554))
taken_i_1
(.I0(p_0_in),
.I1(config_finished_INST_0_i_1_n_0),
.I2(config_finished_INST_0_i_2_n_0),
.I3(config_finished_INST_0_i_3_n_0),
.I4(config_finished_INST_0_i_4_n_0),
.I5(\divider_reg[2] ),
.O(taken_reg));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*******************************************************************************
*
* NetFPGA-10G http://www.netfpga.org
*
* File:
* stats_to_axi.v
*
* Library:
*
* Author:
* Michaela Blott
*
* Description:
* AXI4-Lite for registers
*
* Copyright notice:
* Copyright (C) 2010, 2011 Xilinx, Inc.
*
* Licence:
* This file is part of the NetFPGA 10G development base package.
*
* This file is free code: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 2.1 as
* published by the Free Software Foundation.
*
* This package is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with the NetFPGA source package. If not, see
* http://www.gnu.org/licenses/.
*
*/
module stats_to_axi
#(
// Master AXI Stream Data Width
parameter DATA_WIDTH=32,
parameter ADDR_WIDTH=32,
parameter STATS_WIDTH=32,
parameter REVISION=32'h1
)
(
//clock and reset
input ACLK,
input ARESETN,
//address write
input [ADDR_WIDTH-1: 0] AWADDR,
input AWVALID,
output reg AWREADY,
//data write
input [DATA_WIDTH-1: 0] WDATA,
input [DATA_WIDTH/8-1: 0] WSTRB,
input WVALID,
output reg WREADY,
//write response (handhake)
output reg [1:0] BRESP,
output reg BVALID,
input BREADY,
//address read
input [ADDR_WIDTH-1: 0] ARADDR,
input ARVALID,
output reg ARREADY,
//data read
output reg [DATA_WIDTH-1: 0] RDATA,
output reg [1:0] RRESP,
output reg RVALID,
input RREADY,
//incoming data from the stats modules. must be in pcie clock domain
input [STATS_WIDTH-1:0] stats0_in,//stats 0
input [STATS_WIDTH-1:0] stats1_in,//stats1, connected to a different stats module instance
input [STATS_WIDTH-1:0] stats2_in,
input [STATS_WIDTH-1:0] stats3_in,
//interface to memory allocation unit. for every value store we have 3 queues of free addresses
//one queue for small, medium and large sized values each.
//'small'
output reg [31:0] free1,
output reg free1_wr,
input free1_full,
output reg [31:0] free2,
output reg free2_wr,
input free2_full,
output reg [31:0] free3,
output reg free3_wr,
input free3_full,
output reg [31:0] free4,
output reg free4_wr,
input free4_full,
//'medium'
output reg [31:0] free1M,
output reg free1M_wr,
input free1M_full,
output reg [31:0] free2M,
output reg free2M_wr,
input free2M_full,
output reg [31:0] free3M,
output reg free3M_wr,
input free3M_full,
output reg [31:0] free4M,
output reg free4M_wr,
input free4M_full,
//'large'
output reg [31:0] free1L,
output reg free1L_wr,
input free1L_full,
output reg [31:0] free2L,
output reg free2L_wr,
input free2L_full,
output reg [31:0] free3L,
output reg free3L_wr,
input free3L_full,
output reg [31:0] free4L,
output reg free4L_wr,
input free4L_full,
//fifo for icap
output reg [31:0] icap,
output reg icap_wr,
input icap_full,
//address return fifo
input [31:0] del1,
output reg del1_rd,
input del1_ety,
//software initiated reset
output reg SC_reset,
//flush protocol
input flushreq,
output reg flushack,
input flushdone
);
localparam AXI_RESP_OK = 2'b00;
localparam AXI_RESP_SLVERR = 2'b10;
localparam WRITE_IDLE = 0;
localparam WRITE_RESPONSE = 1;
localparam WRITE_DATA = 2;
localparam READ_IDLE = 0;
localparam READ_RESPONSE = 1;
localparam READ_WAIT = 2;
//for now all addresses are of the form C000XXXX because of the axi crossbar that does some unnecessary address translation
// -- register interface of the CAPI2 corresponding address (hex):
// stats1 : in std_logic_vector(31 downto 0); 0
// stats2 : in std_logic_vector(31 downto 0); 4
// stats3 : in std_logic_vector(31 downto 0); 8
// stats4 : in std_logic_vector(31 downto 0); c
// del1 : in std_logic_vector(31 downto 0); 20
// del1_rd : out std_logic;
// del1_ety : in std_logic;
// free1 : out std_logic_vector(31 downto 0); 30
// free1_wr : out std_logic;
// free1_full : in std_logic; in topmost bit when read
// free2 : out std_logic_vector(31 downto 0); 34
// free2_wr : out std_logic;
// free2_full : in std_logic; in topmost bit when read
// free3 : out std_logic_vector(31 downto 0); 38
// free3_wr : out std_logic;
// free3_full : in std_logic; in topmost bit when read
// free4 : out std_logic_vector(31 downto 0); 3c
// free4_wr : out std_logic;
// free4_full : in std_logic; in topmost bit when read
//
// same for free 1M...free4M at addresses 40-4c. Share the same rw registers for debug as free1-free4
// same for free1L...free4L
//
// icap : out std_logic_vector(31 downto 0); f4
// icap_wr : out std_logic;
// icap_full : in std_logic; in topmost bit when read
//the starting C is from the settings of pcie2axilite core
localparam STATS0_ADDR = 32'h00000000;
localparam STATS1_ADDR = 32'h00000004;
localparam STATS2_ADDR = 32'h00000008;
localparam STATS3_ADDR = 32'h0000000C;
localparam RESET_ADDR = 32'h00000010;
localparam DEL1_ADDR = 32'h00000020;
localparam FREE1_ADDR = 32'h00000030;
localparam FREE2_ADDR = 32'h00000034;
localparam FREE3_ADDR = 32'h00000038;
localparam FREE4_ADDR = 32'h0000003c;
localparam FREE1M_ADDR = 32'h00000040;
localparam FREE2M_ADDR = 32'h00000044;
localparam FREE3M_ADDR = 32'h00000048;
localparam FREE4M_ADDR = 32'h0000004c;
localparam FREE1L_ADDR = 32'h00000050;
localparam FREE2L_ADDR = 32'h00000054;
localparam FREE3L_ADDR = 32'h00000058;
localparam FREE4L_ADDR = 32'h0000005c;
localparam FLUSHREQ = 32'h000000e0;
localparam FLUSHACK = 32'h000000e4;
localparam FLUSHDONE = 32'h000000e8;
localparam REVISION_ADDR = 32'h000000f0;
localparam ICAP_ADDR = 32'h000000f4;
//localparam REVISION=32'h1;
reg [1:0] write_state, write_state_next;
reg [1:0] read_state, read_state_next;
reg [ADDR_WIDTH-1:0] read_addr, read_addr_next;
reg [ADDR_WIDTH-1:0] write_addr, write_addr_next;
reg [2:0] counter, counter_next;
reg [1:0] BRESP_next;
reg [31:0] free1_next,free2_next,free3_next,free4_next,icap_next;
reg [31:0] free1M_next,free2M_next,free3M_next,free4M_next;
reg [31:0] free1L_next,free2L_next,free3L_next,free4L_next;
reg free1_wr_next,free2_wr_next,free3_wr_next,free4_wr_next,icap_wr_next;
reg free1M_wr_next,free2M_wr_next,free3M_wr_next,free4M_wr_next;
reg free1L_wr_next,free2L_wr_next,free3L_wr_next,free4L_wr_next;
reg flushack_next;
reg SC_reset_next;
//4 read-write registers, attached to the lower 31 bits of the "free" regs. Mostly for driver testing
reg[31:0] rw_0,rw_1,rw_2,rw_3;
reg[31:0] rw_0_next,rw_1_next,rw_2_next,rw_3_next;
reg del1_rd_next;//control of the read enable signal for del1
localparam WAIT_COUNT = 2;
always @(*) begin
read_state_next = read_state;
ARREADY = 1'b1;
read_addr_next = read_addr;
counter_next = counter;
RDATA = 0;
RRESP = AXI_RESP_OK;
RVALID = 1'b0;
del1_rd_next=1'b0;
case(read_state)
READ_IDLE: begin
counter_next = 0;
if(ARVALID) begin
read_addr_next = ARADDR;
read_state_next = READ_WAIT;
end
end
READ_WAIT: begin
counter_next = counter + 1;
ARREADY = 1'b0;
if(counter == WAIT_COUNT)
read_state_next = READ_RESPONSE;
end
READ_RESPONSE: begin
RVALID = 1'b1;
ARREADY = 1'b0;
//master tries to read one of the regs
// address decode. valid address of this transaction in read_addr
case(read_addr)
STATS0_ADDR: RDATA=stats0_in[DATA_WIDTH-1:0];
STATS1_ADDR: RDATA=stats1_in[DATA_WIDTH-1:0];
STATS2_ADDR: RDATA=stats2_in[DATA_WIDTH-1:0];
STATS3_ADDR: RDATA=stats3_in[DATA_WIDTH-1:0];
DEL1_ADDR:begin
del1_rd_next=!del1_ety;//if del1 not empty, consume an element
RDATA[31]=del1_ety;
RDATA[30:0]=del1[30:0];
end
FREE1_ADDR: RDATA={free1_full,rw_0[30:0]};
FREE1M_ADDR: RDATA={free1M_full,rw_0[30:0]};
FREE1L_ADDR: RDATA={free1L_full,rw_0[30:0]};
FREE2_ADDR: RDATA={free2_full,rw_1[30:0]};
FREE2M_ADDR: RDATA={free2M_full,rw_1[30:0]};
FREE2L_ADDR: RDATA={free2L_full,rw_1[30:0]};
FREE3_ADDR: RDATA={free3_full,rw_2[30:0]};
FREE3M_ADDR: RDATA={free3M_full,rw_2[30:0]};
FREE3L_ADDR: RDATA={free3L_full,rw_2[30:0]};
FREE4_ADDR: RDATA={free4_full,rw_3[30:0]};
FREE4M_ADDR: RDATA={free4M_full,rw_3[30:0]};
FREE4L_ADDR: RDATA={free4L_full,rw_3[30:0]};
FLUSHREQ: RDATA={31'h0,flushreq};
FLUSHDONE: RDATA={31'h0,flushdone};
REVISION_ADDR: RDATA=REVISION;
ICAP_ADDR : RDATA={icap_full,31'h0};
default: RDATA=32'hffffffff;
endcase
//no error response. If ever needed, do:
//RRESP=AXI_RESP_SLVERR;
if(RREADY) begin// danger: may be multiple cycles in this state!
read_state_next = READ_IDLE;
end
end
endcase
end
always @(*) begin
write_state_next = write_state;
write_addr_next = write_addr;
// count_reset_control_next = count_reset_control;
AWREADY = 1'b1;
WREADY = 1'b0;
BVALID = 1'b0;
BRESP_next = BRESP;
rw_0_next=rw_0;
rw_1_next=rw_1;
rw_2_next=rw_2;
rw_3_next=rw_3;
//defaults: no fresh data
free1_wr_next=1'b0;
free2_wr_next=1'b0;
free3_wr_next=1'b0;
free4_wr_next=1'b0;
icap_wr_next=1'b0;
free1_next=free1;
free2_next=free2;
free3_next=free3;
free4_next=free4;
free1M_next=free1;
free2M_next=free2;
free3M_next=free3;
free4M_next=free4;
free1L_next=free1;
free2L_next=free2;
free3L_next=free3;
free4L_next=free4;
icap_next=icap;
// if(flushdone) begin
// flushack_next=1'b0;
// end else begin
// flushack_next=flushack;
// end
flushack_next=1'b0; //only needs to go high at least 1 cycle
SC_reset_next=1'b0;//high 1 cycle. bridge top makes sure software defined reset is held a few cycles
case(write_state)
WRITE_IDLE: begin
write_addr_next = AWADDR;
if(AWVALID) begin
write_state_next = WRITE_DATA;
end
end
WRITE_DATA: begin
AWREADY = 1'b0;
WREADY = 1'b1;
if(WVALID) begin
//I am being written to.
//address in write_addr, data in WDATA
// address decode
case(write_addr)
STATS0_ADDR:;
STATS1_ADDR:;
STATS2_ADDR:;
STATS3_ADDR:;
RESET_ADDR: SC_reset_next=1'b1;
DEL1_ADDR:;
FREE1_ADDR: begin
rw_0_next=WDATA;//this register can be read out later
free1_next=WDATA;//push the data out
free1_wr_next=1'b1;//notify recipient FIFO of the new data
end
FREE2_ADDR: begin
rw_1_next=WDATA;
free2_next=WDATA;
free2_wr_next=1'b1;
end
FREE3_ADDR: begin
rw_2_next=WDATA;
free3_next=WDATA;
free3_wr_next=1'b1;
end
FREE4_ADDR: begin
rw_3_next=WDATA;
free4_next=WDATA;
free4_wr_next=1'b1;
end
FREE1M_ADDR: begin
rw_0_next=WDATA;//this register can be read out later
free1M_next=WDATA;//push the data out
free1M_wr_next=1'b1;//notify recipient FIFO of the new data
end
FREE2M_ADDR: begin
rw_1_next=WDATA;
free2M_next=WDATA;
free2M_wr_next=1'b1;
end
FREE3M_ADDR: begin
rw_2_next=WDATA;
free3M_next=WDATA;
free3M_wr_next=1'b1;
end
FREE4M_ADDR: begin
rw_3_next=WDATA;
free4M_next=WDATA;
free4M_wr_next=1'b1;
end
FREE1L_ADDR: begin
rw_0_next=WDATA;//this register can be read out later
free1L_next=WDATA;//push the data out
free1L_wr_next=1'b1;//notify recipient FIFO of the new data
end
FREE2L_ADDR: begin
rw_1_next=WDATA;
free2L_next=WDATA;
free2L_wr_next=1'b1;
end
FREE3L_ADDR: begin
rw_2_next=WDATA;
free3L_next=WDATA;
free3L_wr_next=1'b1;
end
FREE4L_ADDR: begin
rw_3_next=WDATA;
free4L_next=WDATA;
free4L_wr_next=1'b1;
end
ICAP_ADDR: begin
icap_next=WDATA;
icap_wr_next=1'b1;
end
FLUSHACK: flushack_next=1'b1;
default:;
endcase
//no error ever if needed, set
//BRESP_next=AXI_RESP_SLVERR;
write_state_next = WRITE_RESPONSE;
end
end
WRITE_RESPONSE: begin
AWREADY = 1'b0;
BVALID = 1'b1;
if(BREADY) begin
write_state_next = WRITE_IDLE;
end
end
endcase
end
always @(posedge ACLK) begin
if(~ARESETN) begin
write_state <= WRITE_IDLE;
read_state <= READ_IDLE;
read_addr <= 0;
write_addr <= 0;
BRESP <= AXI_RESP_OK;
rw_0<=32'h0;
rw_1<=32'h0;
rw_2<=32'h0;
rw_3<=32'h0;
free1<=32'h0;
free2<=32'h0;
free3<=32'h0;
icap<=32'h0;
free1_wr<=1'b0;
free2_wr<=1'b0;
free3_wr<=1'b0;
icap_wr<=1'b0;
del1_rd=1'b0;
SC_reset=1'b0;
flushack=1'b0;
end
else begin
write_state <= write_state_next;
read_state <= read_state_next;
read_addr <= read_addr_next;
write_addr <= write_addr_next;
BRESP <= BRESP_next;
rw_0<=rw_0_next;
rw_1<=rw_1_next;
rw_2<=rw_2_next;
rw_3<=rw_3_next;
free1<=free1_next;
free2<=free2_next;
free3<=free3_next;
free4<=free4_next;
icap<=icap_next;
free1_wr<=free1_wr_next;
free2_wr<=free2_wr_next;
free3_wr<=free3_wr_next;
free4_wr<=free4_wr_next;
icap_wr<=icap_wr_next;
del1_rd=del1_rd_next;
flushack=flushack_next;
SC_reset=SC_reset_next;
end
counter <= counter_next;
end
endmodule
|
`include "assert.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 4;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("i64.ne1.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
reg reset = 0;
wire [63:0] result;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("i64.ne1_tb.vcd");
$dumpvars(0, cpu_tb);
#24
`assert(result, 0);
`assert(result_empty, 0);
$finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A222O_BEHAVIORAL_V
`define SKY130_FD_SC_MS__A222O_BEHAVIORAL_V
/**
* a222o: 2-input AND into all inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a222o (
X ,
A1,
A2,
B1,
B2,
C1,
C2
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire and2_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
and and2 (and2_out , C1, C2 );
or or0 (or0_out_X, and1_out, and0_out, and2_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A222O_BEHAVIORAL_V |
/* This file is part of JT12.
JT12 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 21-03-2019
*/
module jt12_pcm_interpol
#(parameter dw=9, stepw=5)
(
input rst_n,
input clk,
input cen, // 8MHz cen
input cen55, // clk & cen55 = 55 kHz
input pcm_wr, // advance to next sample
input signed [dw-1:0] pcmin,
output reg signed [dw-1:0] pcmout
);
reg [stepw-1:0] dn, pre_dn={stepw{1'b1}};
wire posedge_pcmwr = pcm_wr && !last_pcm_wr;
wire negedge_pcmwr = !pcm_wr && last_pcm_wr;
reg start_div = 0;
wire working;
reg signed [dw-1:0] pcmnew, dx, pcmlast, pcminter;
wire signed [dw:0] dx_ext = { pcmin[dw-1], pcmin } - { pcmnew[dw-1], pcmnew };
reg sign, last_pcm_wr;
// latch new data and compute the two deltas : dx and dn, slope = dx/dn
always @(posedge clk) begin
last_pcm_wr <= pcm_wr;
start_div <= posedge_pcmwr;
if( posedge_pcmwr ) begin
pre_dn <= 1;
pcmnew <= pcmin;
pcmlast <= pcmnew;
dn <= pre_dn;
dx <= dx_ext[dw] ? ~dx_ext[dw-1:0] + 'd1 : dx_ext[dw-1:0];
sign <= dx_ext[dw];
start_div <= 1;
end
if( !pcm_wr && cen55 ) begin
if( pre_dn != {stepw{1'b1}} ) pre_dn <= pre_dn + 'd1;
end
end
// interpolate samples
wire [dw-1:0] step;
wire signed [dw-1:0] next_up = pcminter + step;
wire signed [dw-1:0] next_down = pcminter - step;
wire overflow_up = 0;//next_up[dw-1] != pcmnew[dw-1];
wire overflow_down = 0;//next_down[dw-1] != pcmnew[dw-1];
always @(posedge clk) begin
if( negedge_pcmwr ) begin
pcminter <= pcmlast;
end else if(cen55 && !working && !pcm_wr) begin // only advance if the divider has finished
if( sign ) begin // subtract
if( next_down > pcmnew && !overflow_down )
pcminter <= next_down;
else
pcminter <= pcmnew; // done
end
else begin // add
if( next_up < pcmnew && !overflow_up )
pcminter <= next_up;
else
pcminter <= pcmnew; // done
end
end
end
// output only at cen55
always @(posedge clk) if(cen55) pcmout <= pcminter;
jt10_adpcm_div #(.dw(dw)) u_div(
.rst_n ( rst_n ),
.clk ( clk ),
.cen ( 1'b1 ),
.start ( start_div ),
.a ( dx ),
.b ( { {dw-stepw{1'b0}}, dn } ),
.d ( step ),
.r ( ),
.working( working )
);
endmodule // jt10_adpcmb_interpol |
`timescale 1ns / 1ps
// ***************** ALIGN_MONITOR ******************************************
//
// Only operates when align_en is high
//
// On the 40MHz domain the main_count counts out 127 sets of samples. In each
// sampling routine, sample_trig is taken high and synched onto the 357 domain.
// The 357 domain then samples the data ready on consec. rising, falling, rising edges.
// These 3 samples are then synched back to the 40MHz logic, and added to a running count.
// If all of sample 1 are the same, all of sample 3 are opposite to sample 1, and
// approx. 50% of sample 2 are set, then the 357 phase wrt data ready (and hence adc data)
// is correct. If not, the delay_modifier is changed. This modification is applied
// to the IDELAY on the adc data/data ready inputs.
//
// One complication is that the overall phase of data ready is not known. In order
// that the sampling is consistant over successive sample_trigs, we must force samples 1
// and 3 to always be on given data ready values. This is done by taking a zeroth sample
// on the first 357 rising edge after sample_trig. If this is 0, then continue, else
// delay all by a cycle of 357 to get into the correct phase
//
// When the delay modifier charnges, a strobe is sent for 1 40MHz cycle
//
// *Following commented out for now*
// Additional complication. When the clock phase is set perfectly badly, then the
// sample 0 value depends on the jitter. This leads to random samping in all
// sample 1, 2 & 3! Hence additional check is implemented if sample 2 is within
// threshold. If sample3 count !=0 or sample2 count != 127 then prang the delay mod
//
//
// IODELAY ar 64 tap, or 6-bit. The delay_modifier is a 7-bit 2's comp. number which
// is comined in the delay_calc module with some nominal delay
// i.e is from -64 upto +63
//
//
//////////////////////////////////////////////////////////////////////////////////
module align_monitor(
input clk357,
input clk40,
input rst,
input align_en,
input Q1,
input Q2,
//output reg align_end,
output reg [6:0] delay_modifier,
output reg delay_mod_strb,
output reg [6:0] count1, //Monitoring
output reg [6:0] count2, //Monitoring
output reg [6:0] count3, //Monitoring
output reg monitor_strb
);
//Internal registers
//Taking sample_trig high initiates the sampling on 357 domain
reg sample_trig;
reg sample_trig_a;
reg sample_trig_b;
//reg delay_mod_strb;
reg [1:0] sample_state = 2'b00;
// For samples
reg samp0;
reg samp1;
reg samp2;
reg samp3;
//reg monitor_strb;
reg samples_rdy; //(added by GBC) handshaking signal on sampling clk domain to tell
//the slow domain that samples are ready to synchronise
reg samples_rdy_slow_a; // (added by GBC) synchroniser on slow domain
reg samples_rdy_slow_b; // (added by GBC) guards against metastability
//(* equivalent_register_removal = "no" *) reg align_en_a, align_en_b;
(* equivalent_register_removal = "no", shreg_extract = "no" *) reg align_en_slow_a, align_en_slow_b;
//sythesis attribute equivalent_register_removal of align_en_a is "no"
//sythesis attribute equivalent_register_removal of align_en_b is "no"
//sythesis attribute equivalent_register_removal of align_en_slow_a is "no"
//sythesis attribute equivalent_register_removal of align_en_slow_b is "no"
always @(posedge clk357) begin
//align_en_a <= align_en;
//align_en_b <= align_en_a;
//if (align_en_b) begin
//Synchronise sample_trig
sample_trig_a <= sample_trig;
sample_trig_b <= sample_trig_a;
//Take the samples if sample trig is high
if (sample_trig_b) begin
case (sample_state)
2'd0: begin
//Take zeroth sample
samp0 <= Q1;
samp1 <= samp1;
samp2 <= samp2;
samp3 <= samp3;
sample_state <= 2'd1;
samples_rdy <= samples_rdy;
end
2'd1: begin
samp0 <= (samp0) ? samp0 : Q1;
samp1 <= (samp0) ? Q1 : samp1;
samp2 <= (samp0) ? Q2 : samp2;
samp3 <= samp3;
sample_state <= (samp0) ? 2'd2 : sample_state; //Increment state
samples_rdy <= samples_rdy;
/*
//if (~samp0) begin
if (samp0==1'b1) begin // Modified by GBC 23/11/16 - init value of DDR is zero, therefore check for "1"
//We are on the correct phase, so continue
samp0 <= samp0;
samp1 <= Q1;
samp2 <= Q2;
sample_state <= 2'd2; //Increment state
end else begin //Incorrect phase, so ignore this cycle and wait until next
//samp0 <= 0;
samp0 <= Q1; // Modified by GBC 23/11/16
samp1 <= samp1;
samp2 <= samp2;
sample_state <= sample_state;
end
*/
end
2'd2: begin
samp0 <= samp0;
samp1 <= samp1;
samp2 <= samp2;
//Take third sample
samp3 <= Q1;
//Increment state
sample_state <= 2'd3;
samples_rdy <= 1'b1;
end
2'd3: begin // hold (wait) state
samp0 <= samp0;
samp1 <= samp1;
samp2 <= samp2;
samp3 <= samp3;
sample_state <= sample_state;
samples_rdy <= samples_rdy;
end
endcase
end else begin
samp0 <= samp0;
samp1 <= samp1;
samp2 <= samp2;
samp3 <= samp3;
//When sample_trig goes low, reset state
sample_state <= 2'd0;
samples_rdy <= 1'b0;
end //else (if ~sample_trig_b)
//end //if (align_en)
//end //else (if ~rst)
end //always
//This logic runs on 40MHz domain
//Assert sample_trig then synchronise the three samples to 40MHz
//Add the samples to three counters to track how many of each are set
//Do so n_samp times
//Secondly, increment or decrement the delay_modifier depending on whether
//or not sample 2's count falls within a threshold range. The sample1 and 3 counts
//determine which way to move (delay_modifier is twos comp)
//reg [6:0] delay_modifier;
reg samp1_a;
reg samp2_a;
reg samp3_a;
reg samp1_b;
reg samp2_b;
reg samp3_b;
//parameter counter_bits = 7;
//parameter n_samp = 127;
//parameter threshold_min = 20;
//parameter threshold_max = 107;
parameter counter_bits = 7;
parameter n_samp = 7'd31;
parameter threshold_min = 7'd5;
parameter threshold_max = 7'd26;
reg [counter_bits-1:0] main_count;
reg [counter_bits-1:0] samp1_count;
reg [counter_bits-1:0] samp2_count;
reg [counter_bits-1:0] samp3_count;
//To store the final sample counter values for monitoring purposes
//reg [counter_bits-1:0] count1_mon;
//reg [counter_bits-1:0] count2_mon;
//reg [counter_bits-1:0] count3_mon;
reg [1:0] state40 = 2'b00;
//reg [5:0] iteration_counter; // GBC added for testbenching
//wire align_en_end = align_en_slow_b & ~align_en_slow_a;
always @(posedge clk40) begin
align_en_slow_a <= align_en;
align_en_slow_b <= align_en_slow_a;
//align_end <= align_en_end;
if (rst) begin
sample_trig <= 0;
delay_modifier <= 0;
samp1_a <= 0;
samp2_a <= 0;
samp3_a <= 0;
samp1_b <= 0;
samp2_b <= 0;
samp3_b <= 0;
main_count <= 0;
samp1_count <= 0;
samp2_count <= 0;
samp3_count <= 0;
state40 <= 0;
delay_mod_strb <= 0;
monitor_strb <= 0;
samples_rdy_slow_a <= 1'b0;
samples_rdy_slow_b <= 1'b0;
count1 <= 7'd0;
count2 <= 7'd0;
count3 <= 7'd0;
//iteration_counter <= 6'b0;
end else begin
//align_en_slow_c <= align_en_slow_b;
if (align_en_slow_b) begin
//synchronise samples_rdy
samples_rdy_slow_a <= samples_rdy;
samples_rdy_slow_b <= samples_rdy_slow_a;
if (main_count < n_samp) begin
case (state40)
2'b00: begin
sample_trig <= 1; //Tell 357MHz logic to take some samples
delay_modifier <= delay_modifier;
samp1_a <= samp1_a;
samp2_a <= samp2_a;
samp3_a <= samp3_a;
samp1_b <= samp1_b;
samp2_b <= samp2_b;
samp3_b <= samp3_b;
main_count <= main_count;
samp1_count <= samp1_count;
samp2_count <= samp2_count;
samp3_count <= samp3_count;
state40 <= 2'b01;
//Turn off the strobe
delay_mod_strb <= 0;
monitor_strb <= 0;
count1 <= count1;
count2 <= count2;
count3 <= count3;
end
2'b01: begin
if (samples_rdy_slow_b) begin
//Start synchronsing samples onto the 40MHz domain
samp1_a <= samp1;
samp2_a <= samp2;
samp3_a <= samp3;
sample_trig <= 0;
state40 <= 2'b10;
delay_modifier <= delay_modifier;
samp1_b <= samp1_b;
samp2_b <= samp2_b;
samp3_b <= samp3_b;
main_count <= main_count;
samp1_count <= samp1_count;
samp2_count <= samp2_count;
samp3_count <= samp3_count;
delay_mod_strb <= delay_mod_strb;
monitor_strb <= monitor_strb;
count1 <= count1;
count2 <= count2;
count3 <= count3;
end else begin // hold
samp1_a <= samp1_a;
samp2_a <= samp2_a;
samp3_a <= samp3_a;
sample_trig <= sample_trig;
state40 <= state40;
delay_modifier <= delay_modifier;
samp1_b <= samp1_b;
samp2_b <= samp2_b;
samp3_b <= samp3_b;
main_count <= main_count;
samp1_count <= samp1_count;
samp2_count <= samp2_count;
samp3_count <= samp3_count;
delay_mod_strb <= delay_mod_strb;
monitor_strb <= monitor_strb;
count1 <= count1;
count2 <= count2;
count3 <= count3;
end //else (if ~samples_rdy_slow_b)
end
2'b10: begin
//Finish synching
samp1_b <= samp1_a;
samp2_b <= samp2_a;
samp3_b <= samp3_a;
state40 <= 2'b11;
samp1_a <= samp1_a;
samp2_a <= samp2_a;
samp3_a <= samp3_a;
sample_trig <= sample_trig;
delay_modifier <= delay_modifier;
main_count <= main_count;
samp1_count <= samp1_count;
samp2_count <= samp2_count;
samp3_count <= samp3_count;
delay_mod_strb <= delay_mod_strb;
monitor_strb <= monitor_strb;
count1 <= count1;
count2 <= count2;
count3 <= count3;
end
2'b11: begin
//Add to running totals
samp1_count <= samp1_count + samp1_b;
samp2_count <= samp2_count + samp2_b;
samp3_count <= samp3_count + samp3_b;
//Increment main counter and reset state
main_count <= main_count + 1'b1;
state40 <= 2'b00;
sample_trig <= sample_trig;
delay_modifier <= delay_modifier;
samp1_a <= samp1_a;
samp2_a <= samp2_a;
samp3_a <= samp3_a;
samp1_b <= samp1_b;
samp2_b <= samp2_b;
samp3_b <= samp3_b;
delay_mod_strb <= delay_mod_strb;
monitor_strb <= monitor_strb;
count1 <= count1;
count2 <= count2;
count3 <= count3;
end
endcase
end else begin
//Finished counting the samples
//Must modify the delay if samp2_count is outside the threshold
//Generally, unless the sampling point is well off, then all of sample 1
//should be set or unset, and all of sample 3 the opposite
//Just in case though, will take a majority decision for the possible case of the
//sample point being well off the optimum position, allowing for correction
// if (samp1_count >= samp2_count) begin
// if (samp2_count < threshold_min) delay_modifier = delay_modifier + (7'b1);
// if (samp2_count > threshold_max) delay_modifier = delay_modifier + (-7'b1);
// end
// if (samp1_count < samp2_count) begin
// if (samp2_count < threshold_min) delay_modifier = delay_modifier + (-7'b1);
// if (samp2_count > threshold_max) delay_modifier = delay_modifier + (7'b1);
// end
//First check for 'perfect misphasing'
//This was removed after tests at ATF showed occasional jumps by 20 saturating
//the delays
/* if ( (samp1_count < threshold_max) || (samp3_count > threshold_min) ) begin
//Hmmm. Move delay_mod by half a 357 in which ever direction takes i closer
//to zero to help avoid saturation
if (delay_modifier[6]) begin
//Negative
delay_modifier <= delay_modifier + 7'd20;
delay_mod_strb <= 1;
end else begin
delay_modifier <= delay_modifier + (-7'd20);
delay_mod_strb <= 1;
end
end else begin */
//Things see okay, so check whether samp2 is within threshold
if ( (samp2_count < threshold_min) || (samp2_count > threshold_max) ) begin
//Outside of threshold so modify but prevent wrap-around
if (samp2_count > 16) begin
if (delay_modifier != 7'b1000000) begin
//delay_modifier <= delay_modifier + (-7'b1);
delay_modifier <= delay_modifier + 7'd001;
delay_mod_strb <= 1;
end
end else begin
if (delay_modifier != 7'b0111111) begin
//delay_modifier <= delay_modifier + (7'b1);
delay_modifier <= delay_modifier - 7'd001;
delay_mod_strb <= 1;
end
end //else (if ~(samp2_count) > 64))
end
// end
//rewrite GBC 29/11/16 - superfluous condition (comparing to 16) + condsider useful size of delay_mod
// delay_mod (6 bits) + 1 to catch overflow
/*if ((samp2_count > threshold min) && (samp2_count < 16)) begin //decrease the delay, provided it is not saturated (eg +/- half the range)
if (delay_modifier[6]) begin
delay_modifier <= delay_modifier;
delay_*/
//Store values for monitoring and output strobe
//count1 <= {2'b00, samp1_count};
//count2 <= {2'b00, samp2_count};
//count3 <= {2'b00, samp3_count};
count1 <= samp1_count;
count2 <= samp2_count;
count3 <= samp3_count;
monitor_strb <= 1;
samp1_a <= samp1_a;
samp2_a <= samp2_a;
samp3_a <= samp3_a;
sample_trig <= sample_trig;
state40 <= state40;
samp1_b <= samp1_b;
samp2_b <= samp2_b;
samp3_b <= samp3_b;
//iteration_counter <= iteration_counter + 1'b1;
//Additional check for 'perfect' misphasing
// if ( (samp2_count < threshold_max) && (samp2_count > threshold_min) &&
// ( (samp1_count < 127) || (samp3_count > 0) ) ) begin
// //Something ain't right. Prang the delay by half a period in which
// //ever direction takes it closer to zero
// if (delay_modifier[6])
// delay_modifier <= delay_modifier + 7'd20;
// else
// delay_modifier <= delay_modifier + (-7'd20);
// end
main_count <= 5'd0;
samp1_count <= 5'd0;
samp2_count <= 5'd0;
samp3_count <= 5'd0;
end //else (if ~(main_cnt < n_samp))
end else begin // if (~align_en)
count1 <= count1;
count2 <= count2;
count3 <= count3;
sample_trig <= 1'b0;
delay_modifier <= delay_modifier;
samp1_a <= 1'b0;
samp2_a <= 1'b0;
samp3_a <= 1'b0;
samp1_b <= 1'b0;
samp2_b <= 1'b0;
samp3_b <= 1'b0;
main_count <= 5'd0;
samp1_count <= 5'd0;
samp2_count <= 5'd0;
samp3_count <= 5'd0;
state40 <= 2'b00;
delay_mod_strb <= 1'b0;
monitor_strb <= 1'b0;
samples_rdy_slow_a <= 1'b0;
samples_rdy_slow_b <= 1'b0;
end // else if (~align_en)
end //else (if ~rst)
end //always
//assign align_en_slow = align_en_slow_b &
// Output the temp monitored counters
//assign count1 = count1_mon;
//assign count2 = count2_mon;
//assign count3 = count3_mon;
endmodule |
//////////////////////////////////////////////////////////////////
// //
// Decompiler for Amber 2 Core //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Decompiler for debugging core - not synthesizable //
// Shows instruction in Execute Stage at last clock of //
// the instruction //
// //
// Author(s): //
// - Conor Santifort, [email protected] //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
`include "global_timescale.vh"
`include "global_defines.vh"
`include "a23_config_defines.vh"
module a23_decompile
(
input i_clk,
input i_fetch_stall,
input [31:0] i_instruction,
input i_instruction_valid,
input i_instruction_undefined,
input i_instruction_execute,
input [2:0] i_interrupt, // non-zero value means interrupt triggered
input i_interrupt_state,
input [31:0] i_instruction_address,
input [1:0] i_pc_sel,
input i_pc_wen
);
`include "a23_localparams.vh"
`ifdef A23_DECOMPILE
integer i;
wire [31:0] imm32;
wire [7:0] imm8;
wire [11:0] offset12;
wire [7:0] offset8;
wire [3:0] reg_n, reg_d, reg_m, reg_s;
wire [4:0] shift_imm;
wire [3:0] opcode;
wire [3:0] condition;
wire [3:0] itype;
wire opcode_compare;
wire opcode_move;
wire no_shift;
wire shift_op_imm;
wire [1:0] mtrans_itype;
wire s_bit;
reg [(5*8)-1:0] xINSTRUCTION_EXECUTE;
reg [(5*8)-1:0] xINSTRUCTION_EXECUTE_R = "--- ";
wire [(8*8)-1:0] TYPE_NAME;
reg [3:0] fchars;
reg [31:0] execute_address = 'd0;
reg [2:0] interrupt_d1;
reg [31:0] execute_instruction = 'd0;
reg execute_now = 'd0;
reg execute_valid = 'd0;
reg execute_undefined = 'd0;
// ========================================================
// Delay instruction to Execute stage
// ========================================================
always @( posedge i_clk )
if ( !i_fetch_stall && i_instruction_valid )
begin
execute_instruction <= i_instruction;
execute_address <= i_instruction_address;
execute_undefined <= i_instruction_undefined;
execute_now <= 1'd1;
end
else
execute_now <= 1'd0;
always @ ( posedge i_clk )
if ( !i_fetch_stall )
execute_valid <= i_instruction_valid;
// ========================================================
// Open File
// ========================================================
integer decompile_file;
initial
#1 decompile_file = $fopen(`A23_DECOMPILE_FILE, "w");
// ========================================================
// Fields within the instruction
// ========================================================
assign opcode = execute_instruction[24:21];
assign condition = execute_instruction[31:28];
assign s_bit = execute_instruction[20];
assign reg_n = execute_instruction[19:16];
assign reg_d = execute_instruction[15:12];
assign reg_m = execute_instruction[3:0];
assign reg_s = execute_instruction[11:8];
assign shift_imm = execute_instruction[11:7];
assign offset12 = execute_instruction[11:0];
assign offset8 = {execute_instruction[11:8], execute_instruction[3:0]};
assign imm8 = execute_instruction[7:0];
assign no_shift = execute_instruction[11:4] == 8'h0;
assign mtrans_itype = execute_instruction[24:23];
assign opcode_compare =
opcode == CMP ||
opcode == CMN ||
opcode == TEQ ||
opcode == TST ;
assign opcode_move =
opcode == MOV ||
opcode == MVN ;
assign shift_op_imm = itype == REGOP && execute_instruction[25] == 1'd1;
assign imm32 = execute_instruction[11:8] == 4'h0 ? { 24'h0, imm8[7:0] } :
execute_instruction[11:8] == 4'h1 ? { imm8[1:0], 24'h0, imm8[7:2] } :
execute_instruction[11:8] == 4'h2 ? { imm8[3:0], 24'h0, imm8[7:4] } :
execute_instruction[11:8] == 4'h3 ? { imm8[5:0], 24'h0, imm8[7:6] } :
execute_instruction[11:8] == 4'h4 ? { imm8[7:0], 24'h0 } :
execute_instruction[11:8] == 4'h5 ? { 2'h0, imm8[7:0], 22'h0 } :
execute_instruction[11:8] == 4'h6 ? { 4'h0, imm8[7:0], 20'h0 } :
execute_instruction[11:8] == 4'h7 ? { 6'h0, imm8[7:0], 18'h0 } :
execute_instruction[11:8] == 4'h8 ? { 8'h0, imm8[7:0], 16'h0 } :
execute_instruction[11:8] == 4'h9 ? { 10'h0, imm8[7:0], 14'h0 } :
execute_instruction[11:8] == 4'ha ? { 12'h0, imm8[7:0], 12'h0 } :
execute_instruction[11:8] == 4'hb ? { 14'h0, imm8[7:0], 10'h0 } :
execute_instruction[11:8] == 4'hc ? { 16'h0, imm8[7:0], 8'h0 } :
execute_instruction[11:8] == 4'hd ? { 18'h0, imm8[7:0], 6'h0 } :
execute_instruction[11:8] == 4'he ? { 20'h0, imm8[7:0], 4'h0 } :
{ 22'h0, imm8[7:0], 2'h0 } ;
// ========================================================
// Instruction decode
// ========================================================
// the order of these matters
assign itype =
{execute_instruction[27:23], execute_instruction[21:20], execute_instruction[11:4] } == { 5'b00010, 2'b00, 8'b00001001 } ? SWAP : // Before REGOP
{execute_instruction[27:22], execute_instruction[7:4] } == { 6'b000000, 4'b1001 } ? MULT : // Before REGOP
{execute_instruction[27:26] } == { 2'b00 } ? REGOP :
{execute_instruction[27:26] } == { 2'b01 } ? TRANS :
{execute_instruction[27:25] } == { 3'b100 } ? MTRANS :
{execute_instruction[27:25] } == { 3'b101 } ? BRANCH :
{execute_instruction[27:25] } == { 3'b110 } ? CODTRANS :
{execute_instruction[27:24], execute_instruction[4] } == { 4'b1110, 1'b0 } ? COREGOP :
{execute_instruction[27:24], execute_instruction[4] } == { 4'b1110, 1'b1 } ? CORTRANS :
SWI ;
//
// Convert some important signals to ASCII
// so their values can easily be displayed on a waveform viewer
//
assign TYPE_NAME = itype == REGOP ? "REGOP " :
itype == MULT ? "MULT " :
itype == SWAP ? "SWAP " :
itype == TRANS ? "TRANS " :
itype == MTRANS ? "MTRANS " :
itype == BRANCH ? "BRANCH " :
itype == CODTRANS ? "CODTRANS" :
itype == COREGOP ? "COREGOP " :
itype == CORTRANS ? "CORTRANS" :
itype == SWI ? "SWI " :
"UNKNOWN " ;
always @*
begin
if ( !execute_now )
begin
xINSTRUCTION_EXECUTE = xINSTRUCTION_EXECUTE_R;
end // stalled
else if ( itype == REGOP && opcode == ADC ) xINSTRUCTION_EXECUTE = "adc ";
else if ( itype == REGOP && opcode == ADD ) xINSTRUCTION_EXECUTE = "add ";
else if ( itype == REGOP && opcode == AND ) xINSTRUCTION_EXECUTE = "and ";
else if ( itype == BRANCH && execute_instruction[24] == 1'b0 ) xINSTRUCTION_EXECUTE = "b ";
else if ( itype == REGOP && opcode == BIC ) xINSTRUCTION_EXECUTE = "bic ";
else if ( itype == BRANCH && execute_instruction[24] == 1'b1 ) xINSTRUCTION_EXECUTE = "bl ";
else if ( itype == COREGOP ) xINSTRUCTION_EXECUTE = "cdp ";
else if ( itype == REGOP && opcode == CMN ) xINSTRUCTION_EXECUTE = "cmn ";
else if ( itype == REGOP && opcode == CMP ) xINSTRUCTION_EXECUTE = "cmp ";
else if ( itype == REGOP && opcode == EOR ) xINSTRUCTION_EXECUTE = "eor ";
else if ( itype == CODTRANS && execute_instruction[20] == 1'b1 ) xINSTRUCTION_EXECUTE = "ldc ";
else if ( itype == MTRANS && execute_instruction[20] == 1'b1 ) xINSTRUCTION_EXECUTE = "ldm ";
else if ( itype == TRANS && {execute_instruction[22],execute_instruction[20]} == {1'b0, 1'b1} ) xINSTRUCTION_EXECUTE = "ldr ";
else if ( itype == TRANS && {execute_instruction[22],execute_instruction[20]} == {1'b1, 1'b1} ) xINSTRUCTION_EXECUTE = "ldrb ";
else if ( itype == CORTRANS && execute_instruction[20] == 1'b0 ) xINSTRUCTION_EXECUTE = "mcr ";
else if ( itype == MULT && execute_instruction[21] == 1'b1 ) xINSTRUCTION_EXECUTE = "mla ";
else if ( itype == REGOP && opcode == MOV ) xINSTRUCTION_EXECUTE = "mov ";
else if ( itype == CORTRANS && execute_instruction[20] == 1'b1 ) xINSTRUCTION_EXECUTE = "mrc ";
else if ( itype == MULT && execute_instruction[21] == 1'b0 ) xINSTRUCTION_EXECUTE = "mul ";
else if ( itype == REGOP && opcode == MVN ) xINSTRUCTION_EXECUTE = "mvn ";
else if ( itype == REGOP && opcode == ORR ) xINSTRUCTION_EXECUTE = "orr ";
else if ( itype == REGOP && opcode == RSB ) xINSTRUCTION_EXECUTE = "rsb ";
else if ( itype == REGOP && opcode == RSC ) xINSTRUCTION_EXECUTE = "rsc ";
else if ( itype == REGOP && opcode == SBC ) xINSTRUCTION_EXECUTE = "sbc ";
else if ( itype == CODTRANS && execute_instruction[20] == 1'b0 ) xINSTRUCTION_EXECUTE = "stc ";
else if ( itype == MTRANS && execute_instruction[20] == 1'b0 ) xINSTRUCTION_EXECUTE = "stm ";
else if ( itype == TRANS && {execute_instruction[22],execute_instruction[20]} == {1'b0, 1'b0} ) xINSTRUCTION_EXECUTE = "str ";
else if ( itype == TRANS && {execute_instruction[22],execute_instruction[20]} == {1'b1, 1'b0} ) xINSTRUCTION_EXECUTE = "strb ";
else if ( itype == REGOP && opcode == SUB ) xINSTRUCTION_EXECUTE = "sub ";
else if ( itype == SWI ) xINSTRUCTION_EXECUTE = "swi ";
else if ( itype == SWAP && execute_instruction[22] == 1'b0 ) xINSTRUCTION_EXECUTE = "swp ";
else if ( itype == SWAP && execute_instruction[22] == 1'b1 ) xINSTRUCTION_EXECUTE = "swpb ";
else if ( itype == REGOP && opcode == TEQ ) xINSTRUCTION_EXECUTE = "teq ";
else if ( itype == REGOP && opcode == TST ) xINSTRUCTION_EXECUTE = "tst ";
else xINSTRUCTION_EXECUTE = "unkow";
end
always @ ( posedge i_clk )
xINSTRUCTION_EXECUTE_R <= xINSTRUCTION_EXECUTE;
always @( posedge i_clk )
if ( execute_now )
begin
// Interrupts override instructions that are just starting
if ( interrupt_d1 == 3'd0 || interrupt_d1 == 3'd7 )
begin
$fwrite(decompile_file,"%09d ", `U_TB.clk_count);
// Right justify the address
if ( execute_address < 32'h10) $fwrite(decompile_file," %01x: ", {execute_address[ 3:1], 1'd0});
else if ( execute_address < 32'h100) $fwrite(decompile_file," %02x: ", {execute_address[ 7:1], 1'd0});
else if ( execute_address < 32'h1000) $fwrite(decompile_file," %03x: ", {execute_address[11:1], 1'd0});
else if ( execute_address < 32'h10000) $fwrite(decompile_file," %04x: ", {execute_address[15:1], 1'd0});
else if ( execute_address < 32'h100000) $fwrite(decompile_file," %05x: ", {execute_address[19:1], 1'd0});
else if ( execute_address < 32'h1000000) $fwrite(decompile_file," %06x: ", {execute_address[23:1], 1'd0});
else if ( execute_address < 32'h10000000) $fwrite(decompile_file," %07x: ", {execute_address[27:1], 1'd0});
else $fwrite(decompile_file,"%8x: ", {execute_address[31:1], 1'd0});
// Mark that the instruction is not being executed
// condition field in execute stage allows instruction to execute ?
if (!i_instruction_execute)
begin
$fwrite(decompile_file,"-");
if ( itype == SWI )
$display ("Cycle %09d SWI not taken *************", `U_TB.clk_count);
end
else
$fwrite(decompile_file," ");
// ========================================
// print the instruction name
// ========================================
case (numchars( xINSTRUCTION_EXECUTE ))
4'd1: $fwrite(decompile_file,"%s", xINSTRUCTION_EXECUTE[39:32] );
4'd2: $fwrite(decompile_file,"%s", xINSTRUCTION_EXECUTE[39:24] );
4'd3: $fwrite(decompile_file,"%s", xINSTRUCTION_EXECUTE[39:16] );
4'd4: $fwrite(decompile_file,"%s", xINSTRUCTION_EXECUTE[39: 8] );
default: $fwrite(decompile_file,"%s", xINSTRUCTION_EXECUTE[39: 0] );
endcase
fchars = 8 - numchars(xINSTRUCTION_EXECUTE);
// Print the Multiple transfer itype
if (itype == MTRANS )
begin
w_mtrans_type;
fchars = fchars - 2;
end
// Print the s bit
if ( ((itype == REGOP && !opcode_compare) || itype == MULT ) && s_bit == 1'b1 )
begin
$fwrite(decompile_file,"s");
fchars = fchars - 1;
end
// Print the p bit
if ( itype == REGOP && opcode_compare && s_bit == 1'b1 && reg_d == 4'd15 )
begin
$fwrite(decompile_file,"p");
fchars = fchars - 1;
end
// Print the condition code
if ( condition != AL )
begin
wcond;
fchars = fchars - 2;
end
// Align spaces after instruction
case ( fchars )
4'd0: $fwrite(decompile_file,"");
4'd1: $fwrite(decompile_file," ");
4'd2: $fwrite(decompile_file," ");
4'd3: $fwrite(decompile_file," ");
4'd4: $fwrite(decompile_file," ");
4'd5: $fwrite(decompile_file," ");
4'd6: $fwrite(decompile_file," ");
4'd7: $fwrite(decompile_file," ");
4'd8: $fwrite(decompile_file," ");
default: $fwrite(decompile_file," ");
endcase
// ========================================
// print the arguments for the instruction
// ========================================
case ( itype )
REGOP: regop_args;
TRANS: trans_args;
MTRANS: mtrans_args;
BRANCH: branch_args;
MULT: mult_args;
SWAP: swap_args;
CODTRANS: codtrans_args;
COREGOP: begin
// `TB_ERROR_MESSAGE
$write("Coregop not implemented in decompiler yet\n");
end
CORTRANS: cortrans_args;
SWI: $fwrite(decompile_file,"#0x%06h", execute_instruction[23:0]);
default: begin
`TB_ERROR_MESSAGE
$write("Unknown Instruction Type ERROR\n");
end
endcase
$fwrite( decompile_file,"\n" );
end
// Undefined Instruction Interrupts
if ( i_instruction_execute && execute_undefined )
begin
$fwrite( decompile_file,"%09d interrupt undefined instruction", `U_TB.clk_count );
$fwrite( decompile_file,", return addr " );
$fwrite( decompile_file,"%08x\n", pcf(get_reg_val(5'd21)-4'd4) );
end
// Software Interrupt
if ( i_instruction_execute && itype == SWI )
begin
$fwrite( decompile_file,"%09d interrupt swi", `U_TB.clk_count );
$fwrite( decompile_file,", return addr " );
$fwrite( decompile_file,"%08x\n", pcf(get_reg_val(5'd21)-4'd4) );
end
end
always @( posedge i_clk )
if ( !i_fetch_stall )
begin
interrupt_d1 <= i_interrupt;
// Asynchronous Interrupts
if ( interrupt_d1 != 3'd0 && i_interrupt_state )
begin
$fwrite( decompile_file,"%09d interrupt ", `U_TB.clk_count );
case ( interrupt_d1 )
3'd1: $fwrite( decompile_file,"data abort" );
3'd2: $fwrite( decompile_file,"firq" );
3'd3: $fwrite( decompile_file,"irq" );
3'd4: $fwrite( decompile_file,"address exception" );
3'd5: $fwrite( decompile_file,"instruction abort" );
default: $fwrite( decompile_file,"unknown itype" );
endcase
$fwrite( decompile_file,", return addr " );
case ( interrupt_d1 )
3'd1: $fwrite(decompile_file,"%08h\n", pcf(get_reg_val(5'd16)));
3'd2: $fwrite(decompile_file,"%08h\n", pcf(get_reg_val(5'd17)));
3'd3: $fwrite(decompile_file,"%08h\n", pcf(get_reg_val(5'd18)));
3'd4: $fwrite(decompile_file,"%08h\n", pcf(get_reg_val(5'd19)));
3'd5: $fwrite(decompile_file,"%08h\n", pcf(get_reg_val(5'd19)));
3'd7: $fwrite(decompile_file,"%08h\n", pcf(get_reg_val(5'd20)));
default: ;
endcase
end
end
// jump
// Dont print a jump message for interrupts
always @( posedge i_clk )
if (
i_pc_sel != 2'd0 &&
i_pc_wen &&
!i_fetch_stall &&
i_instruction_execute &&
i_interrupt == 3'd0 &&
!execute_undefined &&
itype != SWI &&
execute_address != get_32bit_signal(0) // Don't print jump to same address
)
begin
$fwrite(decompile_file,"%09d jump from ", `U_TB.clk_count);
fwrite_hex_drop_zeros(decompile_file, pcf(execute_address));
$fwrite(decompile_file," to ");
fwrite_hex_drop_zeros(decompile_file, pcf(get_32bit_signal(0)) ); // u_execute.pc_nxt
$fwrite(decompile_file,", r0 %08h, ", get_reg_val ( 5'd0 ));
$fwrite(decompile_file,"r1 %08h\n", get_reg_val ( 5'd1 ));
end
// =================================================================================
// Memory Writes - Peek into fetch module
// =================================================================================
reg [31:0] tmp_address;
// Data access
always @( posedge i_clk )
// Data Write
if ( get_1bit_signal(0) && !get_1bit_signal(1) )
begin
$fwrite(decompile_file, "%09d write addr ", `U_TB.clk_count);
tmp_address = get_32bit_signal(2);
fwrite_hex_drop_zeros(decompile_file, {tmp_address [31:2], 2'd0} );
$fwrite(decompile_file, ", data %08h, be %h",
get_32bit_signal(3), // u_cache.i_write_data
get_4bit_signal (0)); // u_cache.i_byte_enable
if ( get_1bit_signal(2) ) // Abort! address translation failed
$fwrite(decompile_file, " aborted!\n");
else
$fwrite(decompile_file, "\n");
end
// Data Read
else if (get_1bit_signal(3) && !get_1bit_signal(0) && !get_1bit_signal(1))
begin
$fwrite(decompile_file, "%09d read addr ", `U_TB.clk_count);
tmp_address = get_32bit_signal(2);
fwrite_hex_drop_zeros(decompile_file, {tmp_address[31:2], 2'd0} );
$fwrite(decompile_file, ", data %08h", get_32bit_signal(4)); // u_decode.i_read_data
if ( get_1bit_signal(2) ) // Abort! address translation failed
$fwrite(decompile_file, " aborted!\n");
else
$fwrite(decompile_file, "\n");
end
// =================================================================================
// Tasks
// =================================================================================
// Write Condition field
task wcond;
begin
case( condition)
4'h0: $fwrite(decompile_file,"eq");
4'h1: $fwrite(decompile_file,"ne");
4'h2: $fwrite(decompile_file,"cs");
4'h3: $fwrite(decompile_file,"cc");
4'h4: $fwrite(decompile_file,"mi");
4'h5: $fwrite(decompile_file,"pl");
4'h6: $fwrite(decompile_file,"vs");
4'h7: $fwrite(decompile_file,"vc");
4'h8: $fwrite(decompile_file,"hi");
4'h9: $fwrite(decompile_file,"ls");
4'ha: $fwrite(decompile_file,"ge");
4'hb: $fwrite(decompile_file,"lt");
4'hc: $fwrite(decompile_file,"gt");
4'hd: $fwrite(decompile_file,"le");
4'he: $fwrite(decompile_file," "); // Always
default: $fwrite(decompile_file,"nv"); // Never
endcase
end
endtask
// ldm and stm types
task w_mtrans_type;
begin
case( mtrans_itype )
4'h0: $fwrite(decompile_file,"da");
4'h1: $fwrite(decompile_file,"ia");
4'h2: $fwrite(decompile_file,"db");
4'h3: $fwrite(decompile_file,"ib");
default: $fwrite(decompile_file,"xx");
endcase
end
endtask
// e.g. mrc 15, 0, r9, cr0, cr0, {0}
task cortrans_args;
begin
// Co-Processor Number
$fwrite(decompile_file,"%1d, ", execute_instruction[11:8]);
// opcode1
$fwrite(decompile_file,"%1d, ", execute_instruction[23:21]);
// Rd [15:12]
warmreg(reg_d);
// CRn [19:16]
$fwrite(decompile_file,", cr%1d", execute_instruction[19:16]);
// CRm [3:0]
$fwrite(decompile_file,", cr%1d", execute_instruction[3:0]);
// Opcode2 [7:5]
$fwrite(decompile_file,", {%1d}", execute_instruction[7:5]);
end
endtask
// ldc 15, 0, r9, cr0, cr0, {0}
task codtrans_args;
begin
// Co-Processor Number
$fwrite(decompile_file,"%1d, ", execute_instruction[11:8]);
// CRd [15:12]
$fwrite(decompile_file,"cr%1d, ", execute_instruction[15:12]);
// Rd [19:16]
warmreg(reg_n);
end
endtask
task branch_args;
reg [31:0] shift_amount;
begin
if (execute_instruction[23]) // negative
shift_amount = {~execute_instruction[23:0] + 24'd1, 2'd0};
else
shift_amount = {execute_instruction[23:0], 2'd0};
if (execute_instruction[23]) // negative
fwrite_hex_drop_zeros ( decompile_file, get_reg_val( 5'd21 ) - shift_amount );
else
fwrite_hex_drop_zeros ( decompile_file, get_reg_val( 5'd21 ) + shift_amount );
end
endtask
task mult_args;
begin
warmreg(reg_n); // Rd is in the Rn position for MULT instructions
$fwrite(decompile_file,", ");
warmreg(reg_m);
$fwrite(decompile_file,", ");
warmreg(reg_s);
if (execute_instruction[21]) // MLA
begin
$fwrite(decompile_file,", ");
warmreg(reg_d);
end
end
endtask
task swap_args;
begin
warmreg(reg_d);
$fwrite(decompile_file,", ");
warmreg(reg_m);
$fwrite(decompile_file,", [");
warmreg(reg_n);
$fwrite(decompile_file,"]");
end
endtask
task regop_args;
begin
if (!opcode_compare)
warmreg(reg_d);
if (!opcode_move )
begin
if (!opcode_compare)
begin
$fwrite(decompile_file,", ");
if (reg_d < 4'd10 || reg_d > 4'd12)
$fwrite(decompile_file," ");
end
warmreg(reg_n);
$fwrite(decompile_file,", ");
if (reg_n < 4'd10 || reg_n > 4'd12)
$fwrite(decompile_file," ");
end
else
begin
$fwrite(decompile_file,", ");
if (reg_d < 4'd10 || reg_d > 4'd12)
$fwrite(decompile_file," ");
end
if (shift_op_imm)
begin
if (|imm32[31:15])
$fwrite(decompile_file,"#0x%08h", imm32);
else
$fwrite(decompile_file,"#%1d", imm32);
end
else // Rm
begin
warmreg(reg_m);
if (execute_instruction[4])
// Register Shifts
wshiftreg;
else
// Immediate shifts
wshift;
end
end
endtask
task trans_args;
begin
warmreg(reg_d); // Destination register
casez ({execute_instruction[25:23], execute_instruction[21], no_shift, offset12==12'd0})
6'b0100?0 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", #-%1d]" , offset12); end
6'b0110?0 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", #%1d]" , offset12); end
6'b0100?1 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"]"); end
6'b0110?1 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"]"); end
6'b0101?? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", #-%1d]!", offset12); end
6'b0111?? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", #%1d]!" , offset12); end
6'b0000?0 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], #-%1d", offset12); end
6'b0010?0 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], #%1d" , offset12); end
6'b0001?0 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], #-%1d", offset12); end
6'b0011?0 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], #%1d" , offset12); end
6'b0000?1 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"]"); end
6'b0010?1 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"]"); end
6'b0001?1 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"]"); end
6'b0011?1 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"]"); end
6'b11001? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", -"); warmreg(reg_m); $fwrite(decompile_file,"]"); end
6'b11101? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", "); warmreg(reg_m); $fwrite(decompile_file,"]"); end
6'b11011? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", -"); warmreg(reg_m); $fwrite(decompile_file,"]!"); end
6'b11111? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", "); warmreg(reg_m); $fwrite(decompile_file,"]!"); end
6'b10001? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], -"); warmreg(reg_m); end
6'b10101? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], "); warmreg(reg_m); end
6'b10011? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], -"); warmreg(reg_m); end
6'b10111? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], "); warmreg(reg_m); end
6'b11000? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", -"); warmreg(reg_m); wshift; $fwrite(decompile_file,"]"); end
6'b11100? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", "); warmreg(reg_m); wshift; $fwrite(decompile_file,"]"); end
6'b11010? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", -"); warmreg(reg_m); wshift; $fwrite(decompile_file,"]!");end
6'b11110? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", "); warmreg(reg_m); wshift; $fwrite(decompile_file,"]!");end
6'b10000? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], -"); warmreg(reg_m); wshift; end
6'b10100? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], "); warmreg(reg_m); wshift; end
6'b10010? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], -"); warmreg(reg_m); wshift; end
6'b10110? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], "); warmreg(reg_m); wshift; end
endcase
end
endtask
task mtrans_args;
begin
warmreg(reg_n);
if (execute_instruction[21]) $fwrite(decompile_file,"!");
$fwrite(decompile_file,", {");
for (i=0;i<16;i=i+1)
if (execute_instruction[i])
begin
warmreg(i);
if (more_to_come(execute_instruction[15:0], i))
$fwrite(decompile_file,", ");
end
$fwrite(decompile_file,"}");
// SDM: store the user mode registers, when in priviledged mode
if (execute_instruction[22:20] == 3'b100)
$fwrite(decompile_file,"^");
end
endtask
task wshift;
begin
// Check that its a valid shift operation. LSL by #0 is the null operator
if (execute_instruction[6:5] != LSL || shift_imm != 5'd0)
begin
case(execute_instruction[6:5])
2'd0: $fwrite(decompile_file,", lsl");
2'd1: $fwrite(decompile_file,", lsr");
2'd2: $fwrite(decompile_file,", asr");
2'd3: if (shift_imm == 5'd0) $fwrite(decompile_file,", rrx"); else $fwrite(decompile_file,", ror");
endcase
if (execute_instruction[6:5] != 2'd3 || shift_imm != 5'd0)
$fwrite(decompile_file," #%1d", shift_imm);
end
end
endtask
task wshiftreg;
begin
case(execute_instruction[6:5])
2'd0: $fwrite(decompile_file,", lsl ");
2'd1: $fwrite(decompile_file,", lsr ");
2'd2: $fwrite(decompile_file,", asr ");
2'd3: $fwrite(decompile_file,", ror ");
endcase
warmreg(reg_s);
end
endtask
task warmreg;
input [3:0] regnum;
begin
if (regnum < 4'd12)
$fwrite(decompile_file,"r%1d", regnum);
else
case (regnum)
4'd12 : $fwrite(decompile_file,"ip");
4'd13 : $fwrite(decompile_file,"sp");
4'd14 : $fwrite(decompile_file,"lr");
4'd15 : $fwrite(decompile_file,"pc");
endcase
end
endtask
task fwrite_hex_drop_zeros;
input [31:0] file;
input [31:0] num;
begin
if (num[31:28] != 4'd0)
$fwrite(file, "%x", num);
else if (num[27:24] != 4'd0)
$fwrite(file, "%x", num[27:0]);
else if (num[23:20] != 4'd0)
$fwrite(file, "%x", num[23:0]);
else if (num[19:16] != 4'd0)
$fwrite(file, "%x", num[19:0]);
else if (num[15:12] != 4'd0)
$fwrite(file, "%x", num[15:0]);
else if (num[11:8] != 4'd0)
$fwrite(file, "%x", num[11:0]);
else if (num[7:4] != 4'd0)
$fwrite(file, "%x", num[7:0]);
else
$fwrite(file, "%x", num[3:0]);
end
endtask
// =================================================================================
// Functions
// =================================================================================
// Get current value of register
function [31:0] get_reg_val;
input [4:0] regnum;
begin
case (regnum)
5'd0 : get_reg_val = `U_REGISTER_BANK.r0_out;
5'd1 : get_reg_val = `U_REGISTER_BANK.r1_out;
5'd2 : get_reg_val = `U_REGISTER_BANK.r2_out;
5'd3 : get_reg_val = `U_REGISTER_BANK.r3_out;
5'd4 : get_reg_val = `U_REGISTER_BANK.r4_out;
5'd5 : get_reg_val = `U_REGISTER_BANK.r5_out;
5'd6 : get_reg_val = `U_REGISTER_BANK.r6_out;
5'd7 : get_reg_val = `U_REGISTER_BANK.r7_out;
5'd8 : get_reg_val = `U_REGISTER_BANK.r8_out;
5'd9 : get_reg_val = `U_REGISTER_BANK.r9_out;
5'd10 : get_reg_val = `U_REGISTER_BANK.r10_out;
5'd11 : get_reg_val = `U_REGISTER_BANK.r11_out;
5'd12 : get_reg_val = `U_REGISTER_BANK.r12_out;
5'd13 : get_reg_val = `U_REGISTER_BANK.r13_out;
5'd14 : get_reg_val = `U_REGISTER_BANK.r14_out;
5'd15 : get_reg_val = `U_REGISTER_BANK.r15_out_rm; // the version of pc with status bits
5'd16 : get_reg_val = `U_REGISTER_BANK.r14_svc;
5'd17 : get_reg_val = `U_REGISTER_BANK.r14_firq;
5'd18 : get_reg_val = `U_REGISTER_BANK.r14_irq;
5'd19 : get_reg_val = `U_REGISTER_BANK.r14_svc;
5'd20 : get_reg_val = `U_REGISTER_BANK.r14_svc;
5'd21 : get_reg_val = `U_REGISTER_BANK.r15_out_rn; // the version of pc without status bits
endcase
end
endfunction
function [31:0] get_32bit_signal;
input [2:0] num;
begin
case (num)
3'd0: get_32bit_signal = `U_EXECUTE.pc_nxt;
3'd1: get_32bit_signal = `U_FETCH.i_address;
3'd2: get_32bit_signal = `U_FETCH.i_address;
3'd3: get_32bit_signal = `U_CACHE.i_write_data;
3'd4: get_32bit_signal = `U_DECODE.i_read_data;
endcase
end
endfunction
function get_1bit_signal;
input [2:0] num;
begin
case (num)
3'd0: get_1bit_signal = `U_FETCH.i_write_enable;
3'd1: get_1bit_signal = `U_AMBER.fetch_stall;
3'd2: get_1bit_signal = 1'd0;
3'd3: get_1bit_signal = `U_FETCH.i_data_access;
endcase
end
endfunction
function [3:0] get_4bit_signal;
input [2:0] num;
begin
case (num)
3'd0: get_4bit_signal = `U_CACHE.i_byte_enable;
endcase
end
endfunction
function [3:0] numchars;
input [(5*8)-1:0] xINSTRUCTION_EXECUTE;
begin
if (xINSTRUCTION_EXECUTE[31:0] == " ")
numchars = 4'd1;
else if (xINSTRUCTION_EXECUTE[23:0] == " ")
numchars = 4'd2;
else if (xINSTRUCTION_EXECUTE[15:0] == " ")
numchars = 4'd3;
else if (xINSTRUCTION_EXECUTE[7:0] == " ")
numchars = 4'd4;
else
numchars = 4'd5;
end
endfunction
function more_to_come;
input [15:0] regs;
input [31:0] i;
begin
case (i)
15 : more_to_come = 1'd0;
14 : more_to_come = regs[15] ? 1'd1 : 1'd0;
13 : more_to_come = |regs[15:14] ? 1'd1 : 1'd0;
12 : more_to_come = |regs[15:13] ? 1'd1 : 1'd0;
11 : more_to_come = |regs[15:12] ? 1'd1 : 1'd0;
10 : more_to_come = |regs[15:11] ? 1'd1 : 1'd0;
9 : more_to_come = |regs[15:10] ? 1'd1 : 1'd0;
8 : more_to_come = |regs[15: 9] ? 1'd1 : 1'd0;
7 : more_to_come = |regs[15: 8] ? 1'd1 : 1'd0;
6 : more_to_come = |regs[15: 7] ? 1'd1 : 1'd0;
5 : more_to_come = |regs[15: 6] ? 1'd1 : 1'd0;
4 : more_to_come = |regs[15: 5] ? 1'd1 : 1'd0;
3 : more_to_come = |regs[15: 4] ? 1'd1 : 1'd0;
2 : more_to_come = |regs[15: 3] ? 1'd1 : 1'd0;
1 : more_to_come = |regs[15: 2] ? 1'd1 : 1'd0;
0 : more_to_come = |regs[15: 1] ? 1'd1 : 1'd0;
endcase
end
endfunction
`endif
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 14:32:02 2016
/////////////////////////////////////////////////////////////
module SNPS_CLOCK_GATE_HIGH_Up_counter_COUNTER_WIDTH4 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_FSM_Mult_Function ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_ShiftRegister_W7 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W13 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterMult_W9 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W48 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterMult_W24 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W24 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterMult_W32_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_3 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_3 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_4 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_6 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_9 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_FPU_Interface2_W32_EW8_SW23_SWR26_EWR5_1 ( CLK, EN,
ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
module FPU_Interface2_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, begin_operation,
ack_operation, operation, region_flag, Data_1, Data_2, r_mode,
overflow_flag, underflow_flag, NaN_flag, operation_ready, op_result,
busy );
input [2:0] operation;
input [1:0] region_flag;
input [31:0] Data_1;
input [31:0] Data_2;
input [1:0] r_mode;
output [31:0] op_result;
input clk, rst, begin_operation, ack_operation;
output overflow_flag, underflow_flag, NaN_flag, operation_ready, busy;
wire NaN_reg, ready_add_subt, underflow_flag_mult, overflow_flag_addsubt,
underflow_flag_addsubt, FPSENCOS_fmtted_Result_31_,
FPSENCOS_enab_d_ff4_Xn, FPSENCOS_enab_d_ff4_Yn,
FPSENCOS_d_ff3_sign_out, FPSENCOS_d_ff1_shift_region_flag_out_0_,
FPSENCOS_d_ff1_operation_out, FPSENCOS_enab_d_ff5_data_out,
FPSENCOS_enab_RB3, FPSENCOS_enab_d_ff_RB1, FPSENCOS_enab_d_ff4_Zn,
FPMULT_FSM_selector_C, FPMULT_FSM_selector_A,
FPMULT_FSM_exp_operation_A_S, FPMULT_FSM_barrel_shifter_load,
FPMULT_FSM_final_result_load, FPMULT_FSM_adder_round_norm_load,
FPMULT_FSM_load_second_step, FPMULT_FSM_exp_operation_load_result,
FPMULT_FSM_first_phase_load, FPMULT_FSM_add_overflow_flag,
FPADDSUB_N60, FPADDSUB_N59, FPADDSUB_SIGN_FLAG_SFG, FPADDSUB__19_net_,
FPADDSUB_SIGN_FLAG_NRM, FPADDSUB_SIGN_FLAG_SHT1SHT2,
FPADDSUB_ADD_OVRFLW_NRM2, FPADDSUB_OP_FLAG_SHT2,
FPADDSUB_SIGN_FLAG_SHT2, FPADDSUB_bit_shift_SHT2,
FPADDSUB_left_right_SHT2, FPADDSUB__6_net_, FPADDSUB_ADD_OVRFLW_NRM,
FPADDSUB_OP_FLAG_SHT1, FPADDSUB_SIGN_FLAG_SHT1, FPADDSUB_OP_FLAG_EXP,
FPADDSUB_SIGN_FLAG_EXP, FPADDSUB_Shift_reg_FLAGS_7_5,
FPADDSUB_Shift_reg_FLAGS_7_6, FPADDSUB_enable_Pipeline_input,
FPSENCOS_ITER_CONT_net8160953, FPSENCOS_ITER_CONT_N5,
FPSENCOS_ITER_CONT_N4, FPSENCOS_ITER_CONT_N3,
FPMULT_FS_Module_net8160899, FPMULT_Exp_module_Overflow_flag_A,
FPMULT_Exp_module_Overflow_A,
FPMULT_final_result_ieee_Module_Sign_S_mux,
FPADDSUB_inst_ShiftRegister_net8160791,
FPADDSUB_SFT2FRMT_STAGE_VARS_net8160701,
FPSENCOS_d_ff5_data_out_net8160917,
FPADDSUB_FRMT_STAGE_DATAOUT_net8160629,
FPADDSUB_SGF_STAGE_DMP_net8160683,
FPADDSUB_NRM_STAGE_Raw_mant_net8160665, FPSENCOS_reg_Z0_net8160917,
FPSENCOS_reg_val_muxZ_2stage_net8160917,
FPSENCOS_reg_shift_y_net8160917, FPSENCOS_d_ff4_Xn_net8160917,
FPSENCOS_d_ff4_Yn_net8160917, FPSENCOS_d_ff4_Zn_net8160917,
FPADDSUB_INPUT_STAGE_OPERANDY_net8160629,
FPADDSUB_EXP_STAGE_DMP_net8160683, FPADDSUB_SHT1_STAGE_DMP_net8160683,
FPADDSUB_SHT2_STAGE_DMP_net8160683,
FPADDSUB_SHT2_SHIFT_DATA_net8160665,
FPMULT_Exp_module_exp_result_m_net8160863,
FPMULT_Sgf_operation_EVEN1_finalreg_net8160845,
FPMULT_Barrel_Shifter_module_Output_Reg_net8160827,
FPMULT_Adder_M_Add_Subt_Result_net8160809,
FPMULT_Operands_load_reg_XMRegister_net8160881,
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8160629, n30,
n106, n107, n810, n813, n816, n819, n829, n830, n834, n842, n843,
n844, n846, n848, n849, n850, n851, n852, n853, n854, n855, n856,
n857, n859, n860, n861, n862, n863, n864, n865, n874, n875,
DP_OP_496J314_122_3540_n414, DP_OP_496J314_122_3540_n413,
DP_OP_496J314_122_3540_n412, DP_OP_496J314_122_3540_n407,
DP_OP_496J314_122_3540_n406, DP_OP_496J314_122_3540_n405,
DP_OP_496J314_122_3540_n404, DP_OP_496J314_122_3540_n403,
DP_OP_496J314_122_3540_n400, DP_OP_496J314_122_3540_n399,
DP_OP_496J314_122_3540_n398, DP_OP_496J314_122_3540_n397,
DP_OP_496J314_122_3540_n396, DP_OP_496J314_122_3540_n394,
DP_OP_496J314_122_3540_n393, DP_OP_496J314_122_3540_n392,
DP_OP_496J314_122_3540_n380, DP_OP_496J314_122_3540_n377,
DP_OP_496J314_122_3540_n376, DP_OP_496J314_122_3540_n375,
DP_OP_496J314_122_3540_n374, DP_OP_496J314_122_3540_n373,
DP_OP_496J314_122_3540_n372, DP_OP_496J314_122_3540_n371,
DP_OP_496J314_122_3540_n370, DP_OP_496J314_122_3540_n369,
DP_OP_496J314_122_3540_n368, DP_OP_496J314_122_3540_n367,
DP_OP_496J314_122_3540_n366, DP_OP_496J314_122_3540_n365,
DP_OP_496J314_122_3540_n364, DP_OP_496J314_122_3540_n363,
DP_OP_496J314_122_3540_n362, DP_OP_496J314_122_3540_n361,
DP_OP_496J314_122_3540_n360, DP_OP_496J314_122_3540_n359,
DP_OP_496J314_122_3540_n311, DP_OP_496J314_122_3540_n306,
DP_OP_496J314_122_3540_n305, DP_OP_496J314_122_3540_n296,
DP_OP_496J314_122_3540_n293, DP_OP_496J314_122_3540_n292,
DP_OP_496J314_122_3540_n290, DP_OP_496J314_122_3540_n289,
DP_OP_496J314_122_3540_n288, DP_OP_496J314_122_3540_n287,
DP_OP_496J314_122_3540_n282, DP_OP_496J314_122_3540_n274,
DP_OP_496J314_122_3540_n273, DP_OP_496J314_122_3540_n271,
DP_OP_496J314_122_3540_n270, DP_OP_496J314_122_3540_n269,
DP_OP_496J314_122_3540_n268, DP_OP_496J314_122_3540_n266,
DP_OP_496J314_122_3540_n265, DP_OP_496J314_122_3540_n264,
DP_OP_496J314_122_3540_n263, DP_OP_496J314_122_3540_n262,
DP_OP_496J314_122_3540_n261, DP_OP_496J314_122_3540_n259,
DP_OP_496J314_122_3540_n258, DP_OP_496J314_122_3540_n257,
DP_OP_496J314_122_3540_n256, DP_OP_496J314_122_3540_n255,
DP_OP_496J314_122_3540_n254, DP_OP_496J314_122_3540_n253,
DP_OP_496J314_122_3540_n252, DP_OP_496J314_122_3540_n251,
DP_OP_496J314_122_3540_n250, DP_OP_496J314_122_3540_n249,
DP_OP_496J314_122_3540_n248, DP_OP_496J314_122_3540_n247,
DP_OP_496J314_122_3540_n234, DP_OP_496J314_122_3540_n229,
DP_OP_496J314_122_3540_n228, DP_OP_496J314_122_3540_n227,
DP_OP_496J314_122_3540_n224, DP_OP_496J314_122_3540_n205,
DP_OP_496J314_122_3540_n204, DP_OP_496J314_122_3540_n203,
DP_OP_496J314_122_3540_n202, DP_OP_496J314_122_3540_n201,
DP_OP_496J314_122_3540_n200, DP_OP_496J314_122_3540_n196,
DP_OP_496J314_122_3540_n195, DP_OP_496J314_122_3540_n194,
DP_OP_496J314_122_3540_n193, DP_OP_496J314_122_3540_n192,
DP_OP_496J314_122_3540_n191, DP_OP_496J314_122_3540_n187,
DP_OP_496J314_122_3540_n186, DP_OP_496J314_122_3540_n185,
DP_OP_496J314_122_3540_n184, DP_OP_496J314_122_3540_n183,
DP_OP_496J314_122_3540_n182, DP_OP_496J314_122_3540_n177,
DP_OP_496J314_122_3540_n176, DP_OP_496J314_122_3540_n175,
DP_OP_496J314_122_3540_n174, DP_OP_496J314_122_3540_n173,
DP_OP_496J314_122_3540_n169, DP_OP_496J314_122_3540_n167,
DP_OP_496J314_122_3540_n166, DP_OP_496J314_122_3540_n165,
DP_OP_496J314_122_3540_n162, DP_OP_496J314_122_3540_n161,
DP_OP_496J314_122_3540_n159, DP_OP_496J314_122_3540_n158,
DP_OP_496J314_122_3540_n157, DP_OP_496J314_122_3540_n156,
DP_OP_496J314_122_3540_n155, DP_OP_496J314_122_3540_n154,
DP_OP_496J314_122_3540_n151, DP_OP_496J314_122_3540_n150,
DP_OP_496J314_122_3540_n149, DP_OP_496J314_122_3540_n148,
DP_OP_496J314_122_3540_n145, DP_OP_496J314_122_3540_n133,
DP_OP_496J314_122_3540_n128, DP_OP_496J314_122_3540_n127,
DP_OP_496J314_122_3540_n125, DP_OP_496J314_122_3540_n124,
DP_OP_496J314_122_3540_n123, DP_OP_496J314_122_3540_n122,
DP_OP_496J314_122_3540_n121, DP_OP_496J314_122_3540_n120,
DP_OP_496J314_122_3540_n119, DP_OP_496J314_122_3540_n118,
DP_OP_496J314_122_3540_n117, DP_OP_496J314_122_3540_n116,
DP_OP_496J314_122_3540_n115, DP_OP_496J314_122_3540_n113,
DP_OP_496J314_122_3540_n112, DP_OP_496J314_122_3540_n111,
DP_OP_496J314_122_3540_n110, DP_OP_496J314_122_3540_n109,
DP_OP_496J314_122_3540_n108, DP_OP_496J314_122_3540_n107,
DP_OP_496J314_122_3540_n106, DP_OP_496J314_122_3540_n105,
DP_OP_496J314_122_3540_n104, DP_OP_496J314_122_3540_n103,
DP_OP_496J314_122_3540_n102, DP_OP_496J314_122_3540_n101,
DP_OP_496J314_122_3540_n100, DP_OP_496J314_122_3540_n99,
DP_OP_496J314_122_3540_n98, DP_OP_496J314_122_3540_n97,
DP_OP_496J314_122_3540_n95, DP_OP_496J314_122_3540_n94,
DP_OP_496J314_122_3540_n93, DP_OP_496J314_122_3540_n92,
DP_OP_496J314_122_3540_n91, DP_OP_496J314_122_3540_n90,
DP_OP_496J314_122_3540_n89, DP_OP_496J314_122_3540_n88,
DP_OP_496J314_122_3540_n87, DP_OP_496J314_122_3540_n84,
DP_OP_496J314_122_3540_n83, DP_OP_496J314_122_3540_n82,
DP_OP_496J314_122_3540_n81, DP_OP_496J314_122_3540_n80,
DP_OP_496J314_122_3540_n79, DP_OP_496J314_122_3540_n78,
DP_OP_496J314_122_3540_n77, DP_OP_496J314_122_3540_n76,
DP_OP_496J314_122_3540_n75, DP_OP_496J314_122_3540_n74,
DP_OP_496J314_122_3540_n73, DP_OP_496J314_122_3540_n72,
DP_OP_496J314_122_3540_n71, DP_OP_496J314_122_3540_n70,
DP_OP_496J314_122_3540_n69, DP_OP_496J314_122_3540_n68,
DP_OP_496J314_122_3540_n67, DP_OP_496J314_122_3540_n66,
DP_OP_496J314_122_3540_n65, DP_OP_496J314_122_3540_n64,
DP_OP_496J314_122_3540_n63, DP_OP_496J314_122_3540_n62,
DP_OP_496J314_122_3540_n61, DP_OP_496J314_122_3540_n60,
DP_OP_496J314_122_3540_n59, DP_OP_496J314_122_3540_n58,
DP_OP_496J314_122_3540_n57, DP_OP_496J314_122_3540_n56,
DP_OP_496J314_122_3540_n55, DP_OP_496J314_122_3540_n54,
DP_OP_496J314_122_3540_n53, DP_OP_496J314_122_3540_n52,
DP_OP_496J314_122_3540_n51, DP_OP_496J314_122_3540_n50,
DP_OP_496J314_122_3540_n49, DP_OP_496J314_122_3540_n48,
DP_OP_496J314_122_3540_n47, DP_OP_496J314_122_3540_n46,
DP_OP_496J314_122_3540_n45, DP_OP_496J314_122_3540_n44,
DP_OP_496J314_122_3540_n43, DP_OP_496J314_122_3540_n42,
DP_OP_496J314_122_3540_n41, DP_OP_496J314_122_3540_n40,
DP_OP_496J314_122_3540_n38, DP_OP_496J314_122_3540_n37,
DP_OP_496J314_122_3540_n36, DP_OP_496J314_122_3540_n35,
DP_OP_496J314_122_3540_n34, DP_OP_496J314_122_3540_n33,
DP_OP_496J314_122_3540_n32, DP_OP_496J314_122_3540_n31,
DP_OP_496J314_122_3540_n30, DP_OP_496J314_122_3540_n29,
DP_OP_496J314_122_3540_n28, DP_OP_496J314_122_3540_n27,
DP_OP_496J314_122_3540_n26, DP_OP_496J314_122_3540_n25,
DP_OP_496J314_122_3540_n23, DP_OP_496J314_122_3540_n22,
DP_OP_496J314_122_3540_n21, DP_OP_26J314_126_1325_n18,
DP_OP_26J314_126_1325_n17, DP_OP_26J314_126_1325_n16,
DP_OP_26J314_126_1325_n15, DP_OP_26J314_126_1325_n14,
DP_OP_26J314_126_1325_n8, DP_OP_26J314_126_1325_n7,
DP_OP_26J314_126_1325_n6, DP_OP_26J314_126_1325_n5,
DP_OP_26J314_126_1325_n4, DP_OP_26J314_126_1325_n3,
DP_OP_26J314_126_1325_n2, DP_OP_26J314_126_1325_n1,
DP_OP_234J314_129_4955_n22, DP_OP_234J314_129_4955_n21,
DP_OP_234J314_129_4955_n20, DP_OP_234J314_129_4955_n19,
DP_OP_234J314_129_4955_n18, DP_OP_234J314_129_4955_n17,
DP_OP_234J314_129_4955_n16, DP_OP_234J314_129_4955_n15,
DP_OP_234J314_129_4955_n9, DP_OP_234J314_129_4955_n8,
DP_OP_234J314_129_4955_n7, DP_OP_234J314_129_4955_n6,
DP_OP_234J314_129_4955_n5, DP_OP_234J314_129_4955_n4,
DP_OP_234J314_129_4955_n3, DP_OP_234J314_129_4955_n2,
DP_OP_234J314_129_4955_n1, intadd_1057_CI, intadd_1057_SUM_9_,
intadd_1057_SUM_8_, intadd_1057_SUM_7_, intadd_1057_SUM_6_,
intadd_1057_SUM_5_, intadd_1057_SUM_4_, intadd_1057_SUM_3_,
intadd_1057_SUM_2_, intadd_1057_SUM_1_, intadd_1057_SUM_0_,
intadd_1057_n10, intadd_1057_n9, intadd_1057_n8, intadd_1057_n7,
intadd_1057_n6, intadd_1057_n5, intadd_1057_n4, intadd_1057_n3,
intadd_1057_n2, intadd_1057_n1, intadd_1058_A_8_, intadd_1058_A_1_,
intadd_1058_A_0_, intadd_1058_B_8_, intadd_1058_B_7_,
intadd_1058_B_2_, intadd_1058_B_1_, intadd_1058_B_0_, intadd_1058_CI,
intadd_1058_n9, intadd_1058_n8, intadd_1058_n7, intadd_1058_n6,
intadd_1058_n5, intadd_1058_n4, intadd_1058_n3, intadd_1058_n2,
intadd_1058_n1, intadd_1059_A_4_, intadd_1059_A_3_, intadd_1059_A_2_,
intadd_1059_A_1_, intadd_1059_A_0_, intadd_1059_B_4_,
intadd_1059_B_3_, intadd_1059_B_2_, intadd_1059_B_1_,
intadd_1059_B_0_, intadd_1059_CI, intadd_1059_SUM_4_,
intadd_1059_SUM_3_, intadd_1059_SUM_2_, intadd_1059_SUM_1_,
intadd_1059_SUM_0_, intadd_1059_n5, intadd_1059_n4, intadd_1059_n3,
intadd_1059_n2, intadd_1059_n1, intadd_1060_B_4_, intadd_1060_B_3_,
intadd_1060_B_0_, intadd_1060_SUM_4_, intadd_1060_SUM_3_,
intadd_1060_SUM_2_, intadd_1060_SUM_1_, intadd_1060_SUM_0_,
intadd_1060_n5, intadd_1060_n4, intadd_1060_n3, intadd_1060_n2,
intadd_1060_n1, intadd_1061_CI, intadd_1061_n3, intadd_1061_n2,
intadd_1061_n1, intadd_1062_CI, intadd_1062_n3, intadd_1062_n2,
intadd_1062_n1, intadd_1063_CI, intadd_1063_SUM_2_,
intadd_1063_SUM_1_, intadd_1063_SUM_0_, intadd_1063_n3,
intadd_1063_n2, intadd_1063_n1, intadd_1054_A_13_, intadd_1054_A_12_,
intadd_1054_A_11_, intadd_1054_A_10_, intadd_1054_A_9_,
intadd_1054_A_8_, intadd_1054_A_7_, intadd_1054_A_6_,
intadd_1054_A_5_, intadd_1054_A_4_, intadd_1054_A_3_,
intadd_1054_A_2_, intadd_1054_A_1_, intadd_1054_B_13_,
intadd_1054_B_12_, intadd_1054_B_11_, intadd_1054_B_10_,
intadd_1054_B_7_, intadd_1054_B_6_, intadd_1054_B_5_,
intadd_1054_B_0_, intadd_1054_CI, intadd_1054_SUM_13_,
intadd_1054_SUM_12_, intadd_1054_SUM_11_, intadd_1054_SUM_10_,
intadd_1054_SUM_9_, intadd_1054_SUM_8_, intadd_1054_SUM_7_,
intadd_1054_SUM_6_, intadd_1054_SUM_5_, intadd_1054_SUM_4_,
intadd_1054_SUM_3_, intadd_1054_SUM_2_, intadd_1054_SUM_1_,
intadd_1054_SUM_0_, intadd_1054_n14, intadd_1054_n13, intadd_1054_n12,
intadd_1054_n11, intadd_1054_n10, intadd_1054_n9, intadd_1054_n8,
intadd_1054_n7, intadd_1054_n6, intadd_1054_n5, intadd_1054_n4,
intadd_1054_n3, intadd_1054_n2, intadd_1054_n1, intadd_1055_A_9_,
intadd_1055_A_2_, intadd_1055_A_1_, intadd_1055_A_0_,
intadd_1055_B_9_, intadd_1055_B_8_, intadd_1055_B_3_,
intadd_1055_B_2_, intadd_1055_B_1_, intadd_1055_B_0_, intadd_1055_CI,
intadd_1055_n10, intadd_1055_n9, intadd_1055_n8, intadd_1055_n7,
intadd_1055_n6, intadd_1055_n5, intadd_1055_n4, intadd_1055_n3,
intadd_1055_n2, intadd_1055_n1, intadd_1056_CI, intadd_1056_SUM_6_,
intadd_1056_SUM_5_, intadd_1056_n10, intadd_1056_n9, intadd_1056_n8,
intadd_1056_n7, intadd_1056_n6, intadd_1056_n5, intadd_1056_n4,
intadd_1056_n3, intadd_1056_n2, intadd_1056_n1,
DP_OP_499J314_125_1651_n133, DP_OP_499J314_125_1651_n132,
DP_OP_499J314_125_1651_n131, DP_OP_499J314_125_1651_n130,
DP_OP_499J314_125_1651_n129, DP_OP_499J314_125_1651_n128,
DP_OP_499J314_125_1651_n127, DP_OP_499J314_125_1651_n126,
DP_OP_499J314_125_1651_n125, DP_OP_499J314_125_1651_n124,
DP_OP_499J314_125_1651_n123, DP_OP_499J314_125_1651_n122,
DP_OP_499J314_125_1651_n121, DP_OP_499J314_125_1651_n120,
DP_OP_499J314_125_1651_n119, DP_OP_499J314_125_1651_n118,
DP_OP_499J314_125_1651_n110, DP_OP_499J314_125_1651_n109,
DP_OP_499J314_125_1651_n108, DP_OP_499J314_125_1651_n107,
DP_OP_499J314_125_1651_n106, DP_OP_499J314_125_1651_n105,
DP_OP_499J314_125_1651_n104, DP_OP_499J314_125_1651_n103,
DP_OP_499J314_125_1651_n102, DP_OP_499J314_125_1651_n101,
DP_OP_499J314_125_1651_n100, DP_OP_499J314_125_1651_n99,
DP_OP_499J314_125_1651_n98, DP_OP_499J314_125_1651_n97,
DP_OP_499J314_125_1651_n96, DP_OP_499J314_125_1651_n95,
DP_OP_499J314_125_1651_n81, DP_OP_499J314_125_1651_n78,
DP_OP_499J314_125_1651_n77, DP_OP_499J314_125_1651_n76,
DP_OP_499J314_125_1651_n75, DP_OP_499J314_125_1651_n74,
DP_OP_499J314_125_1651_n73, DP_OP_499J314_125_1651_n72,
DP_OP_499J314_125_1651_n71, DP_OP_499J314_125_1651_n70,
DP_OP_499J314_125_1651_n69, DP_OP_499J314_125_1651_n68,
DP_OP_499J314_125_1651_n67, DP_OP_499J314_125_1651_n66,
DP_OP_499J314_125_1651_n65, DP_OP_499J314_125_1651_n64,
DP_OP_499J314_125_1651_n63, DP_OP_499J314_125_1651_n62,
DP_OP_499J314_125_1651_n61, DP_OP_499J314_125_1651_n60,
DP_OP_499J314_125_1651_n59, DP_OP_499J314_125_1651_n58,
DP_OP_499J314_125_1651_n57, DP_OP_499J314_125_1651_n56,
DP_OP_499J314_125_1651_n55, DP_OP_499J314_125_1651_n54,
DP_OP_499J314_125_1651_n53, DP_OP_499J314_125_1651_n52,
DP_OP_499J314_125_1651_n51, DP_OP_499J314_125_1651_n50,
DP_OP_499J314_125_1651_n49, DP_OP_499J314_125_1651_n48,
DP_OP_499J314_125_1651_n47, DP_OP_499J314_125_1651_n46,
DP_OP_499J314_125_1651_n45, DP_OP_499J314_125_1651_n44,
DP_OP_499J314_125_1651_n43, DP_OP_499J314_125_1651_n42,
DP_OP_499J314_125_1651_n41, DP_OP_499J314_125_1651_n40,
DP_OP_499J314_125_1651_n39, DP_OP_499J314_125_1651_n38,
DP_OP_499J314_125_1651_n37, DP_OP_499J314_125_1651_n36,
DP_OP_499J314_125_1651_n35, DP_OP_499J314_125_1651_n34,
DP_OP_499J314_125_1651_n33, DP_OP_499J314_125_1651_n32,
DP_OP_499J314_125_1651_n31, DP_OP_498J314_124_1725_n370,
DP_OP_498J314_124_1725_n365, DP_OP_498J314_124_1725_n364,
DP_OP_498J314_124_1725_n360, DP_OP_498J314_124_1725_n352,
DP_OP_498J314_124_1725_n351, DP_OP_498J314_124_1725_n346,
DP_OP_498J314_124_1725_n341, DP_OP_498J314_124_1725_n335,
DP_OP_498J314_124_1725_n332, DP_OP_498J314_124_1725_n331,
DP_OP_498J314_124_1725_n330, DP_OP_498J314_124_1725_n329,
DP_OP_498J314_124_1725_n328, DP_OP_498J314_124_1725_n327,
DP_OP_498J314_124_1725_n326, DP_OP_498J314_124_1725_n325,
DP_OP_498J314_124_1725_n324, DP_OP_498J314_124_1725_n323,
DP_OP_498J314_124_1725_n322, DP_OP_498J314_124_1725_n321,
DP_OP_498J314_124_1725_n320, DP_OP_498J314_124_1725_n319,
DP_OP_498J314_124_1725_n318, DP_OP_498J314_124_1725_n317,
DP_OP_498J314_124_1725_n316, DP_OP_498J314_124_1725_n315,
DP_OP_498J314_124_1725_n314, DP_OP_498J314_124_1725_n313,
DP_OP_498J314_124_1725_n312, DP_OP_498J314_124_1725_n311,
DP_OP_498J314_124_1725_n310, DP_OP_498J314_124_1725_n309,
DP_OP_498J314_124_1725_n308, DP_OP_498J314_124_1725_n307,
DP_OP_498J314_124_1725_n306, DP_OP_498J314_124_1725_n279,
DP_OP_498J314_124_1725_n274, DP_OP_498J314_124_1725_n273,
DP_OP_498J314_124_1725_n269, DP_OP_498J314_124_1725_n261,
DP_OP_498J314_124_1725_n260, DP_OP_498J314_124_1725_n255,
DP_OP_498J314_124_1725_n250, DP_OP_498J314_124_1725_n244,
DP_OP_498J314_124_1725_n241, DP_OP_498J314_124_1725_n240,
DP_OP_498J314_124_1725_n239, DP_OP_498J314_124_1725_n238,
DP_OP_498J314_124_1725_n237, DP_OP_498J314_124_1725_n236,
DP_OP_498J314_124_1725_n235, DP_OP_498J314_124_1725_n234,
DP_OP_498J314_124_1725_n233, DP_OP_498J314_124_1725_n232,
DP_OP_498J314_124_1725_n231, DP_OP_498J314_124_1725_n230,
DP_OP_498J314_124_1725_n229, DP_OP_498J314_124_1725_n228,
DP_OP_498J314_124_1725_n227, DP_OP_498J314_124_1725_n226,
DP_OP_498J314_124_1725_n225, DP_OP_498J314_124_1725_n224,
DP_OP_498J314_124_1725_n223, DP_OP_498J314_124_1725_n222,
DP_OP_498J314_124_1725_n221, DP_OP_498J314_124_1725_n220,
DP_OP_498J314_124_1725_n219, DP_OP_498J314_124_1725_n218,
DP_OP_498J314_124_1725_n217, DP_OP_498J314_124_1725_n216,
DP_OP_498J314_124_1725_n215, DP_OP_498J314_124_1725_n202,
DP_OP_498J314_124_1725_n201, DP_OP_498J314_124_1725_n197,
DP_OP_498J314_124_1725_n196, DP_OP_498J314_124_1725_n195,
DP_OP_498J314_124_1725_n194, DP_OP_498J314_124_1725_n193,
DP_OP_498J314_124_1725_n192, DP_OP_498J314_124_1725_n125,
DP_OP_498J314_124_1725_n124, DP_OP_498J314_124_1725_n123,
DP_OP_498J314_124_1725_n122, DP_OP_498J314_124_1725_n121,
DP_OP_498J314_124_1725_n120, DP_OP_498J314_124_1725_n119,
DP_OP_498J314_124_1725_n118, DP_OP_498J314_124_1725_n117,
DP_OP_498J314_124_1725_n116, DP_OP_498J314_124_1725_n114,
DP_OP_498J314_124_1725_n113, DP_OP_498J314_124_1725_n112,
DP_OP_498J314_124_1725_n111, DP_OP_498J314_124_1725_n110,
DP_OP_498J314_124_1725_n109, DP_OP_498J314_124_1725_n108,
DP_OP_498J314_124_1725_n107, DP_OP_498J314_124_1725_n106,
DP_OP_498J314_124_1725_n105, DP_OP_498J314_124_1725_n104,
DP_OP_498J314_124_1725_n103, DP_OP_498J314_124_1725_n101,
DP_OP_498J314_124_1725_n100, DP_OP_498J314_124_1725_n99,
DP_OP_498J314_124_1725_n98, DP_OP_498J314_124_1725_n97,
DP_OP_498J314_124_1725_n96, DP_OP_498J314_124_1725_n94,
DP_OP_498J314_124_1725_n91, DP_OP_498J314_124_1725_n90,
DP_OP_498J314_124_1725_n83, DP_OP_498J314_124_1725_n82,
DP_OP_498J314_124_1725_n81, DP_OP_498J314_124_1725_n80,
DP_OP_498J314_124_1725_n79, DP_OP_498J314_124_1725_n78,
DP_OP_498J314_124_1725_n75, DP_OP_498J314_124_1725_n74,
DP_OP_498J314_124_1725_n73, DP_OP_498J314_124_1725_n72,
DP_OP_498J314_124_1725_n70, DP_OP_498J314_124_1725_n69,
DP_OP_498J314_124_1725_n68, DP_OP_498J314_124_1725_n67,
DP_OP_498J314_124_1725_n65, DP_OP_498J314_124_1725_n64,
DP_OP_498J314_124_1725_n63, DP_OP_498J314_124_1725_n62,
DP_OP_498J314_124_1725_n61, DP_OP_498J314_124_1725_n60,
DP_OP_498J314_124_1725_n59, DP_OP_498J314_124_1725_n58,
DP_OP_498J314_124_1725_n57, DP_OP_498J314_124_1725_n56,
DP_OP_498J314_124_1725_n55, DP_OP_498J314_124_1725_n54,
DP_OP_498J314_124_1725_n53, DP_OP_498J314_124_1725_n52,
DP_OP_498J314_124_1725_n51, DP_OP_498J314_124_1725_n50,
DP_OP_498J314_124_1725_n49, DP_OP_498J314_124_1725_n48,
DP_OP_498J314_124_1725_n47, DP_OP_498J314_124_1725_n46,
DP_OP_498J314_124_1725_n45, DP_OP_498J314_124_1725_n44,
DP_OP_498J314_124_1725_n43, DP_OP_498J314_124_1725_n42,
DP_OP_498J314_124_1725_n41, DP_OP_498J314_124_1725_n40,
DP_OP_498J314_124_1725_n39, DP_OP_498J314_124_1725_n38,
DP_OP_498J314_124_1725_n37, DP_OP_498J314_124_1725_n36,
DP_OP_498J314_124_1725_n35, DP_OP_498J314_124_1725_n34,
DP_OP_498J314_124_1725_n33, DP_OP_498J314_124_1725_n32,
DP_OP_498J314_124_1725_n31, DP_OP_498J314_124_1725_n30,
DP_OP_498J314_124_1725_n29, DP_OP_498J314_124_1725_n28,
DP_OP_498J314_124_1725_n27, DP_OP_498J314_124_1725_n26,
DP_OP_498J314_124_1725_n25, DP_OP_498J314_124_1725_n24,
DP_OP_498J314_124_1725_n23, DP_OP_498J314_124_1725_n22,
DP_OP_498J314_124_1725_n21, DP_OP_498J314_124_1725_n20,
DP_OP_498J314_124_1725_n19, DP_OP_498J314_124_1725_n18,
DP_OP_497J314_123_1725_n369, DP_OP_497J314_123_1725_n364,
DP_OP_497J314_123_1725_n359, DP_OP_497J314_123_1725_n358,
DP_OP_497J314_123_1725_n351, DP_OP_497J314_123_1725_n345,
DP_OP_497J314_123_1725_n335, DP_OP_497J314_123_1725_n332,
DP_OP_497J314_123_1725_n331, DP_OP_497J314_123_1725_n330,
DP_OP_497J314_123_1725_n329, DP_OP_497J314_123_1725_n328,
DP_OP_497J314_123_1725_n327, DP_OP_497J314_123_1725_n326,
DP_OP_497J314_123_1725_n325, DP_OP_497J314_123_1725_n324,
DP_OP_497J314_123_1725_n323, DP_OP_497J314_123_1725_n322,
DP_OP_497J314_123_1725_n321, DP_OP_497J314_123_1725_n320,
DP_OP_497J314_123_1725_n319, DP_OP_497J314_123_1725_n318,
DP_OP_497J314_123_1725_n317, DP_OP_497J314_123_1725_n316,
DP_OP_497J314_123_1725_n315, DP_OP_497J314_123_1725_n314,
DP_OP_497J314_123_1725_n313, DP_OP_497J314_123_1725_n312,
DP_OP_497J314_123_1725_n311, DP_OP_497J314_123_1725_n310,
DP_OP_497J314_123_1725_n309, DP_OP_497J314_123_1725_n308,
DP_OP_497J314_123_1725_n307, DP_OP_497J314_123_1725_n306,
DP_OP_497J314_123_1725_n279, DP_OP_497J314_123_1725_n274,
DP_OP_497J314_123_1725_n273, DP_OP_497J314_123_1725_n269,
DP_OP_497J314_123_1725_n261, DP_OP_497J314_123_1725_n260,
DP_OP_497J314_123_1725_n255, DP_OP_497J314_123_1725_n250,
DP_OP_497J314_123_1725_n244, DP_OP_497J314_123_1725_n241,
DP_OP_497J314_123_1725_n240, DP_OP_497J314_123_1725_n239,
DP_OP_497J314_123_1725_n238, DP_OP_497J314_123_1725_n237,
DP_OP_497J314_123_1725_n236, DP_OP_497J314_123_1725_n235,
DP_OP_497J314_123_1725_n234, DP_OP_497J314_123_1725_n233,
DP_OP_497J314_123_1725_n232, DP_OP_497J314_123_1725_n231,
DP_OP_497J314_123_1725_n230, DP_OP_497J314_123_1725_n229,
DP_OP_497J314_123_1725_n228, DP_OP_497J314_123_1725_n227,
DP_OP_497J314_123_1725_n226, DP_OP_497J314_123_1725_n225,
DP_OP_497J314_123_1725_n224, DP_OP_497J314_123_1725_n223,
DP_OP_497J314_123_1725_n222, DP_OP_497J314_123_1725_n221,
DP_OP_497J314_123_1725_n220, DP_OP_497J314_123_1725_n219,
DP_OP_497J314_123_1725_n218, DP_OP_497J314_123_1725_n217,
DP_OP_497J314_123_1725_n216, DP_OP_497J314_123_1725_n215,
DP_OP_497J314_123_1725_n202, DP_OP_497J314_123_1725_n201,
DP_OP_497J314_123_1725_n197, DP_OP_497J314_123_1725_n196,
DP_OP_497J314_123_1725_n195, DP_OP_497J314_123_1725_n194,
DP_OP_497J314_123_1725_n193, DP_OP_497J314_123_1725_n192,
DP_OP_497J314_123_1725_n125, DP_OP_497J314_123_1725_n124,
DP_OP_497J314_123_1725_n123, DP_OP_497J314_123_1725_n122,
DP_OP_497J314_123_1725_n121, DP_OP_497J314_123_1725_n120,
DP_OP_497J314_123_1725_n119, DP_OP_497J314_123_1725_n118,
DP_OP_497J314_123_1725_n117, DP_OP_497J314_123_1725_n116,
DP_OP_497J314_123_1725_n114, DP_OP_497J314_123_1725_n113,
DP_OP_497J314_123_1725_n112, DP_OP_497J314_123_1725_n111,
DP_OP_497J314_123_1725_n110, DP_OP_497J314_123_1725_n109,
DP_OP_497J314_123_1725_n108, DP_OP_497J314_123_1725_n107,
DP_OP_497J314_123_1725_n106, DP_OP_497J314_123_1725_n105,
DP_OP_497J314_123_1725_n104, DP_OP_497J314_123_1725_n103,
DP_OP_497J314_123_1725_n101, DP_OP_497J314_123_1725_n100,
DP_OP_497J314_123_1725_n99, DP_OP_497J314_123_1725_n98,
DP_OP_497J314_123_1725_n97, DP_OP_497J314_123_1725_n96,
DP_OP_497J314_123_1725_n94, DP_OP_497J314_123_1725_n91,
DP_OP_497J314_123_1725_n87, DP_OP_497J314_123_1725_n83,
DP_OP_497J314_123_1725_n82, DP_OP_497J314_123_1725_n81,
DP_OP_497J314_123_1725_n80, DP_OP_497J314_123_1725_n79,
DP_OP_497J314_123_1725_n78, DP_OP_497J314_123_1725_n75,
DP_OP_497J314_123_1725_n74, DP_OP_497J314_123_1725_n73,
DP_OP_497J314_123_1725_n72, DP_OP_497J314_123_1725_n70,
DP_OP_497J314_123_1725_n69, DP_OP_497J314_123_1725_n68,
DP_OP_497J314_123_1725_n67, DP_OP_497J314_123_1725_n65,
DP_OP_497J314_123_1725_n64, DP_OP_497J314_123_1725_n63,
DP_OP_497J314_123_1725_n62, DP_OP_497J314_123_1725_n61,
DP_OP_497J314_123_1725_n60, DP_OP_497J314_123_1725_n59,
DP_OP_497J314_123_1725_n58, DP_OP_497J314_123_1725_n57,
DP_OP_497J314_123_1725_n56, DP_OP_497J314_123_1725_n55,
DP_OP_497J314_123_1725_n54, DP_OP_497J314_123_1725_n53,
DP_OP_497J314_123_1725_n52, DP_OP_497J314_123_1725_n51,
DP_OP_497J314_123_1725_n50, DP_OP_497J314_123_1725_n49,
DP_OP_497J314_123_1725_n48, DP_OP_497J314_123_1725_n47,
DP_OP_497J314_123_1725_n46, DP_OP_497J314_123_1725_n45,
DP_OP_497J314_123_1725_n44, DP_OP_497J314_123_1725_n43,
DP_OP_497J314_123_1725_n42, DP_OP_497J314_123_1725_n41,
DP_OP_497J314_123_1725_n40, DP_OP_497J314_123_1725_n39,
DP_OP_497J314_123_1725_n38, DP_OP_497J314_123_1725_n37,
DP_OP_497J314_123_1725_n36, DP_OP_497J314_123_1725_n35,
DP_OP_497J314_123_1725_n34, DP_OP_497J314_123_1725_n33,
DP_OP_497J314_123_1725_n32, DP_OP_497J314_123_1725_n31,
DP_OP_497J314_123_1725_n30, DP_OP_497J314_123_1725_n29,
DP_OP_497J314_123_1725_n28, DP_OP_497J314_123_1725_n27,
DP_OP_497J314_123_1725_n26, DP_OP_497J314_123_1725_n25,
DP_OP_497J314_123_1725_n24, DP_OP_497J314_123_1725_n23,
DP_OP_497J314_123_1725_n22, DP_OP_497J314_123_1725_n21,
DP_OP_497J314_123_1725_n20, DP_OP_497J314_123_1725_n19,
DP_OP_497J314_123_1725_n18, n911, n912, n913, n914, n915, n916, n917,
n918, n919, n920, n921, n922, n923, n924, n925, n926, n927, n928,
n929, n930, n931, n932, n933, n934, n935, n936, n937, n938, n939,
n940, n941, n942, n943, n944, n945, n946, n947, n948, n949, n950,
n951, n952, n953, n954, n955, n956, n957, n958, n959, n960, n961,
n962, n963, n964, n965, n966, n967, n968, n969, n970, n971, n972,
n973, n974, n975, n976, n977, n978, n979, n981, n982, n983, n984,
n985, n986, n987, n988, n989, n992, n993, n994, n995, n996, n997,
n998, n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007,
n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017,
n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027,
n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037,
n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047,
n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057,
n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067,
n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077,
n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087,
n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097,
n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107,
n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117,
n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127,
n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137,
n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147,
n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157,
n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167,
n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177,
n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187,
n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197,
n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207,
n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217,
n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227,
n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237,
n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247,
n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257,
n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267,
n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277,
n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287,
n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297,
n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307,
n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317,
n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327,
n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337,
n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347,
n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357,
n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367,
n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377,
n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387,
n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397,
n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407,
n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417,
n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426, n1427,
n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1437,
n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447,
n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456, n1457,
n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466, n1467,
n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477,
n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487,
n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497,
n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507,
n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517,
n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527,
n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537,
n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547,
n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557,
n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567,
n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577,
n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587,
n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597,
n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607,
n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617,
n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627,
n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636, n1637,
n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646, n1647,
n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656, n1657,
n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666, n1667,
n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676, n1677,
n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686, n1687,
n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696, n1697,
n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706, n1707,
n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716, n1717,
n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726, n1727,
n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737,
n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747,
n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755, n1756, n1757,
n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766, n1767,
n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776, n1777,
n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1786, n1787,
n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795, n1796, n1797,
n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805, n1806, n1807,
n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815, n1816, n1817,
n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825, n1826, n1827,
n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835, n1836, n1837,
n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845, n1846, n1847,
n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855, n1856, n1857,
n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865, n1866, n1867,
n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875, n1876, n1877,
n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885, n1886, n1887,
n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895, n1896, n1897,
n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905, n1906, n1907,
n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915, n1916, n1917,
n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925, n1926, n1927,
n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935, n1936, n1937,
n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945, n1946, n1947,
n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955, n1956, n1957,
n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965, n1966, n1967,
n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975, n1976, n1977,
n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985, n1986, n1987,
n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995, n1996, n1997,
n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005, n2006, n2007,
n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015, n2016, n2017,
n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025, n2026, n2027,
n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035, n2036, n2037,
n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045, n2046, n2047,
n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055, n2056, n2057,
n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065, n2066, n2067,
n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075, n2076, n2077,
n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085, n2086, n2087,
n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095, n2096, n2097,
n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105, n2106, n2107,
n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115, n2116, n2117,
n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125, n2126, n2127,
n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135, n2136, n2137,
n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145, n2146, n2147,
n2148, n2149, n2150, n2151, n2152, n2153, n2154, n2155, n2156, n2157,
n2158, n2159, n2160, n2161, n2162, n2163, n2164, n2165, n2166, n2167,
n2168, n2169, n2170, n2171, n2172, n2173, n2174, n2175, n2176, n2177,
n2178, n2179, n2180, n2181, n2182, n2183, n2184, n2185, n2186, n2187,
n2188, n2189, n2190, n2191, n2192, n2193, n2194, n2195, n2196, n2197,
n2198, n2199, n2200, n2201, n2202, n2203, n2204, n2205, n2206, n2207,
n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215, n2216, n2217,
n2218, n2219, n2220, n2221, n2222, n2223, n2224, n2225, n2226, n2227,
n2228, n2229, n2230, n2231, n2232, n2233, n2234, n2235, n2236, n2237,
n2238, n2239, n2240, n2241, n2242, n2243, n2244, n2245, n2246, n2247,
n2248, n2249, n2250, n2251, n2252, n2253, n2254, n2255, n2256, n2257,
n2258, n2259, n2260, n2261, n2262, n2263, n2264, n2265, n2266, n2267,
n2268, n2269, n2270, n2271, n2272, n2273, n2274, n2275, n2276, n2277,
n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285, n2286, n2287,
n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295, n2296, n2297,
n2298, n2299, n2300, n2301, n2302, n2303, n2304, n2305, n2306, n2307,
n2308, n2309, n2310, n2311, n2312, n2313, n2314, n2315, n2316, n2317,
n2318, n2319, n2320, n2321, n2322, n2323, n2324, n2325, n2326, n2327,
n2328, n2329, n2330, n2331, n2332, n2333, n2334, n2335, n2336, n2337,
n2338, n2339, n2340, n2341, n2342, n2343, n2344, n2345, n2346, n2347,
n2348, n2349, n2350, n2351, n2352, n2353, n2354, n2355, n2356, n2357,
n2358, n2359, n2360, n2361, n2362, n2363, n2364, n2365, n2366, n2367,
n2368, n2369, n2370, n2371, n2372, n2373, n2374, n2375, n2376, n2377,
n2378, n2379, n2380, n2381, n2382, n2383, n2384, n2385, n2386, n2387,
n2388, n2389, n2390, n2391, n2392, n2393, n2394, n2395, n2396, n2397,
n2398, n2399, n2400, n2401, n2402, n2403, n2404, n2405, n2406, n2407,
n2408, n2409, n2410, n2411, n2412, n2413, n2414, n2415, n2416, n2417,
n2418, n2419, n2420, n2421, n2422, n2423, n2424, n2425, n2426, n2427,
n2428, n2429, n2430, n2431, n2432, n2433, n2434, n2435, n2436, n2437,
n2438, n2439, n2440, n2441, n2442, n2443, n2444, n2445, n2446, n2447,
n2448, n2449, n2450, n2451, n2452, n2453, n2454, n2455, n2456, n2457,
n2458, n2459, n2460, n2461, n2462, n2463, n2464, n2465, n2466, n2467,
n2468, n2469, n2470, n2471, n2472, n2473, n2474, n2475, n2476, n2477,
n2478, n2479, n2480, n2481, n2482, n2483, n2484, n2485, n2486, n2487,
n2488, n2489, n2490, n2491, n2492, n2493, n2494, n2495, n2496, n2497,
n2498, n2499, n2500, n2501, n2502, n2503, n2504, n2505, n2506, n2507,
n2508, n2509, n2510, n2511, n2512, n2513, n2514, n2515, n2516, n2517,
n2518, n2519, n2520, n2521, n2522, n2523, n2524, n2525, n2526, n2527,
n2528, n2529, n2530, n2531, n2532, n2533, n2534, n2535, n2536, n2537,
n2538, n2539, n2540, n2541, n2542, n2543, n2544, n2545, n2546, n2547,
n2548, n2549, n2550, n2551, n2552, n2553, n2554, n2555, n2556, n2557,
n2558, n2559, n2560, n2561, n2562, n2563, n2564, n2565, n2566, n2567,
n2568, n2569, n2570, n2571, n2572, n2573, n2574, n2575, n2576, n2577,
n2578, n2579, n2580, n2581, n2582, n2583, n2584, n2585, n2586, n2587,
n2588, n2589, n2590, n2591, n2592, n2593, n2594, n2595, n2596, n2597,
n2598, n2599, n2600, n2601, n2602, n2603, n2604, n2605, n2606, n2607,
n2608, n2609, n2610, n2611, n2612, n2613, n2614, n2615, n2616, n2617,
n2618, n2619, n2620, n2621, n2622, n2623, n2624, n2625, n2626, n2627,
n2628, n2629, n2630, n2631, n2632, n2633, n2634, n2635, n2636, n2637,
n2638, n2639, n2640, n2641, n2642, n2643, n2644, n2645, n2646, n2647,
n2648, n2649, n2650, n2651, n2652, n2653, n2654, n2655, n2656, n2657,
n2658, n2659, n2660, n2661, n2662, n2663, n2664, n2665, n2666, n2667,
n2668, n2669, n2670, n2671, n2672, n2673, n2674, n2675, n2676, n2677,
n2678, n2679, n2680, n2681, n2682, n2683, n2684, n2685, n2686, n2687,
n2688, n2689, n2690, n2691, n2692, n2693, n2694, n2695, n2696, n2697,
n2698, n2699, n2700, n2701, n2702, n2703, n2704, n2705, n2706, n2707,
n2708, n2709, n2710, n2711, n2712, n2713, n2714, n2715, n2716, n2717,
n2718, n2719, n2720, n2721, n2722, n2723, n2724, n2725, n2726, n2727,
n2728, n2729, n2730, n2731, n2732, n2733, n2734, n2735, n2736, n2737,
n2738, n2739, n2740, n2741, n2742, n2743, n2744, n2745, n2746, n2747,
n2748, n2749, n2750, n2751, n2752, n2753, n2754, n2755, n2756, n2757,
n2758, n2759, n2760, n2761, n2762, n2763, n2764, n2765, n2766, n2767,
n2768, n2769, n2770, n2771, n2772, n2773, n2774, n2775, n2776, n2777,
n2778, n2779, n2780, n2781, n2782, n2783, n2784, n2785, n2786, n2787,
n2788, n2789, n2790, n2791, n2792, n2793, n2794, n2795, n2796, n2797,
n2798, n2799, n2800, n2801, n2802, n2803, n2804, n2805, n2806, n2807,
n2808, n2809, n2810, n2811, n2812, n2813, n2814, n2815, n2816, n2817,
n2818, n2819, n2820, n2821, n2822, n2823, n2824, n2825, n2826, n2827,
n2828, n2829, n2830, n2831, n2832, n2833, n2834, n2835, n2836, n2837,
n2838, n2839, n2840, n2841, n2842, n2843, n2844, n2845, n2846, n2847,
n2848, n2849, n2850, n2851, n2852, n2853, n2854, n2855, n2856, n2857,
n2858, n2859, n2860, n2861, n2862, n2863, n2864, n2865, n2866, n2867,
n2868, n2869, n2870, n2871, n2872, n2873, n2874, n2875, n2876, n2877,
n2878, n2879, n2880, n2881, n2882, n2883, n2884, n2885, n2886, n2887,
n2888, n2889, n2890, n2891, n2892, n2893, n2894, n2895, n2896, n2897,
n2898, n2900, n2901, n2902, n2903, n2904, n2905, n2906, n2907, n2908,
n2909, n2910, n2911, n2912, n2913, n2914, n2915, n2916, n2917, n2918,
n2919, n2920, n2921, n2922, n2923, n2924, n2925, n2926, n2927, n2928,
n2929, n2930, n2931, n2932, n2933, n2934, n2935, n2936, n2937, n2938,
n2939, n2940, n2941, n2942, n2943, n2944, n2945, n2946, n2947, n2948,
n2949, n2950, n2951, n2952, n2953, n2954, n2955, n2956, n2957, n2958,
n2959, n2960, n2962, n2963, n2965, n2966, n2967, n2968, n2969, n2970,
n2971, n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980,
n2981, n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989, n2990;
wire [1:0] operation_reg;
wire [31:23] dataA;
wire [31:23] dataB;
wire [31:0] add_subt_data1;
wire [30:0] add_subt_data2;
wire [31:0] cordic_result;
wire [31:0] result_add_subt;
wire [31:0] mult_result;
wire [30:0] FPSENCOS_mux_sal;
wire [27:0] FPSENCOS_d_ff3_LUT_out;
wire [31:0] FPSENCOS_d_ff3_sh_y_out;
wire [31:0] FPSENCOS_d_ff3_sh_x_out;
wire [25:4] FPSENCOS_data_out_LUT;
wire [7:0] FPSENCOS_sh_exp_y;
wire [7:0] FPSENCOS_sh_exp_x;
wire [31:0] FPSENCOS_d_ff2_Z;
wire [31:0] FPSENCOS_d_ff2_Y;
wire [31:0] FPSENCOS_d_ff2_X;
wire [31:0] FPSENCOS_first_mux_Z;
wire [31:0] FPSENCOS_d_ff_Zn;
wire [31:0] FPSENCOS_first_mux_Y;
wire [31:0] FPSENCOS_d_ff_Yn;
wire [31:0] FPSENCOS_first_mux_X;
wire [31:0] FPSENCOS_d_ff_Xn;
wire [31:0] FPSENCOS_d_ff1_Z;
wire [1:0] FPSENCOS_cont_var_out;
wire [3:0] FPSENCOS_cont_iter_out;
wire [23:0] FPMULT_Sgf_normalized_result;
wire [23:0] FPMULT_Add_result;
wire [8:0] FPMULT_S_Oper_A_exp;
wire [8:0] FPMULT_exp_oper_result;
wire [30:0] FPMULT_Op_MY;
wire [30:0] FPMULT_Op_MX;
wire [1:0] FPMULT_FSM_selector_B;
wire [47:23] FPMULT_P_Sgf;
wire [31:0] FPADDSUB_formatted_number_W;
wire [25:1] FPADDSUB_Raw_mant_SGF;
wire [24:2] FPADDSUB_DmP_mant_SFG_SWR;
wire [30:0] FPADDSUB_DMP_SFG;
wire [7:0] FPADDSUB_exp_rslt_NRM2_EW1;
wire [4:0] FPADDSUB_LZD_output_NRM2_EW;
wire [25:0] FPADDSUB_sftr_odat_SHT2_SWR;
wire [7:0] FPADDSUB_DMP_exp_NRM_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM2_EW;
wire [4:2] FPADDSUB_shift_value_SHT2_EWR;
wire [30:0] FPADDSUB_DMP_SHT2_EWSW;
wire [51:0] FPADDSUB_Data_array_SWR;
wire [25:0] FPADDSUB_Raw_mant_NRM_SWR;
wire [4:2] FPADDSUB_shft_value_mux_o_EWR;
wire [4:0] FPADDSUB_LZD_raw_out_EWR;
wire [4:0] FPADDSUB_Shift_amount_SHT1_EWR;
wire [22:0] FPADDSUB_DmP_mant_SHT1_SW;
wire [30:0] FPADDSUB_DMP_SHT1_EWSW;
wire [4:0] FPADDSUB_Shift_amount_EXP_EW;
wire [27:0] FPADDSUB_DmP_EXP_EWSW;
wire [30:0] FPADDSUB_DMP_EXP_EWSW;
wire [27:0] FPADDSUB_DmP_INIT_EWSW;
wire [30:0] FPADDSUB_DMP_INIT_EWSW;
wire [28:0] FPADDSUB_intDY_EWSW;
wire [31:0] FPADDSUB_intDX_EWSW;
wire [3:0] FPADDSUB_Shift_reg_FLAGS_7;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_next;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_reg;
wire [3:0] FPMULT_FS_Module_state_next;
wire [3:0] FPMULT_FS_Module_state_reg;
wire [8:0] FPMULT_Exp_module_Data_S;
wire [47:23] FPMULT_Sgf_operation_Result;
wire [24:1] FPMULT_Adder_M_result_A_adder;
wire [22:0] FPMULT_final_result_ieee_Module_Sgf_S_mux;
wire [7:0] FPMULT_final_result_ieee_Module_Exp_S_mux;
wire [2:0] FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg;
wire [11:8] FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left;
wire [16:1] FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B;
wire [13:3] FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right;
wire [10:0] FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left;
wire [11:8] FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left;
SNPS_CLOCK_GATE_HIGH_Up_counter_COUNTER_WIDTH4 FPSENCOS_ITER_CONT_clk_gate_temp_reg (
.CLK(clk), .EN(n967), .ENCLK(FPSENCOS_ITER_CONT_net8160953), .TE(1'b0)
);
SNPS_CLOCK_GATE_HIGH_FSM_Mult_Function FPMULT_FS_Module_clk_gate_state_reg_reg (
.CLK(clk), .EN(n846), .ENCLK(FPMULT_FS_Module_net8160899), .TE(1'b0)
);
SNPS_CLOCK_GATE_HIGH_ShiftRegister_W7 FPADDSUB_inst_ShiftRegister_clk_gate_Q_reg (
.CLK(clk), .EN(n875), .ENCLK(FPADDSUB_inst_ShiftRegister_net8160791),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W13 FPADDSUB_SFT2FRMT_STAGE_VARS_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7[1]), .ENCLK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8160701), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_0 FPSENCOS_d_ff5_data_out_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_d_ff5_data_out), .ENCLK(
FPSENCOS_d_ff5_data_out_net8160917), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_0 FPADDSUB_FRMT_STAGE_DATAOUT_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7[0]), .ENCLK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8160629), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_0 FPADDSUB_SGF_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB__19_net_), .ENCLK(
FPADDSUB_SGF_STAGE_DMP_net8160683), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_0 FPADDSUB_NRM_STAGE_Raw_mant_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7[2]), .ENCLK(
FPADDSUB_NRM_STAGE_Raw_mant_net8160665), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_9 FPSENCOS_reg_Z0_clk_gate_Q_reg ( .CLK(
clk), .EN(FPSENCOS_enab_d_ff_RB1), .ENCLK(FPSENCOS_reg_Z0_net8160917),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_6 FPSENCOS_reg_val_muxZ_2stage_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]), .ENCLK(
FPSENCOS_reg_val_muxZ_2stage_net8160917), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_4 FPSENCOS_reg_shift_y_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_RB3), .ENCLK(
FPSENCOS_reg_shift_y_net8160917), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_3 FPSENCOS_d_ff4_Xn_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_d_ff4_Xn), .ENCLK(
FPSENCOS_d_ff4_Xn_net8160917), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_2 FPSENCOS_d_ff4_Yn_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_d_ff4_Yn), .ENCLK(
FPSENCOS_d_ff4_Yn_net8160917), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_1 FPSENCOS_d_ff4_Zn_clk_gate_Q_reg (
.CLK(clk), .EN(FPSENCOS_enab_d_ff4_Zn), .ENCLK(
FPSENCOS_d_ff4_Zn_net8160917), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_2 FPADDSUB_INPUT_STAGE_OPERANDY_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_enable_Pipeline_input), .ENCLK(
FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_3 FPADDSUB_EXP_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7_6), .ENCLK(
FPADDSUB_EXP_STAGE_DMP_net8160683), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_2 FPADDSUB_SHT1_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB_Shift_reg_FLAGS_7_5), .ENCLK(
FPADDSUB_SHT1_STAGE_DMP_net8160683), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_1 FPADDSUB_SHT2_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(busy), .ENCLK(FPADDSUB_SHT2_STAGE_DMP_net8160683), .TE(
1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_2 FPADDSUB_SHT2_SHIFT_DATA_clk_gate_Q_reg (
.CLK(clk), .EN(FPADDSUB__6_net_), .ENCLK(
FPADDSUB_SHT2_SHIFT_DATA_net8160665), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterMult_W9 FPMULT_Exp_module_exp_result_m_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_exp_operation_load_result), .ENCLK(
FPMULT_Exp_module_exp_result_m_net8160863), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W48 FPMULT_Sgf_operation_EVEN1_finalreg_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_load_second_step), .ENCLK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8160845), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterMult_W24 FPMULT_Barrel_Shifter_module_Output_Reg_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_barrel_shifter_load), .ENCLK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8160827), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W24 FPMULT_Adder_M_Add_Subt_Result_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_adder_round_norm_load), .ENCLK(
FPMULT_Adder_M_Add_Subt_Result_net8160809), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterMult_W32_0_1 FPMULT_Operands_load_reg_XMRegister_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_first_phase_load), .ENCLK(
FPMULT_Operands_load_reg_XMRegister_net8160881), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_1 FPMULT_final_result_ieee_Module_Final_Result_IEEE_clk_gate_Q_reg (
.CLK(clk), .EN(FPMULT_FSM_final_result_load), .ENCLK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8160629), .TE(
1'b0) );
DFFRXLTS reg_dataA_Q_reg_24_ ( .D(Data_1[24]), .CK(clk), .RN(n918), .QN(n947) );
DFFRXLTS reg_dataA_Q_reg_25_ ( .D(Data_1[25]), .CK(clk), .RN(n2936), .Q(
dataA[25]) );
DFFRXLTS reg_dataA_Q_reg_26_ ( .D(Data_1[26]), .CK(clk), .RN(n2943), .Q(
dataA[26]) );
DFFRXLTS reg_dataA_Q_reg_27_ ( .D(Data_1[27]), .CK(clk), .RN(n2925), .Q(
dataA[27]) );
DFFRXLTS reg_dataA_Q_reg_31_ ( .D(Data_1[31]), .CK(clk), .RN(n2934), .Q(
dataA[31]) );
DFFRXLTS reg_dataB_Q_reg_25_ ( .D(Data_2[25]), .CK(clk), .RN(n918), .Q(
dataB[25]) );
DFFRXLTS reg_dataB_Q_reg_26_ ( .D(Data_2[26]), .CK(clk), .RN(n918), .Q(
dataB[26]) );
DFFRXLTS reg_dataB_Q_reg_29_ ( .D(Data_2[29]), .CK(clk), .RN(n2934), .Q(
dataB[29]) );
DFFRXLTS reg_dataB_Q_reg_31_ ( .D(Data_2[31]), .CK(clk), .RN(n2944), .Q(
dataB[31]) );
DFFRXLTS NaN_dff_Q_reg_0_ ( .D(NaN_reg), .CK(clk), .RN(n2945), .Q(NaN_flag)
);
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_6_ ( .D(n2966), .CK(
FPADDSUB_inst_ShiftRegister_net8160791), .RN(n2910), .Q(
FPADDSUB_Shift_reg_FLAGS_7_6) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_5_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7_6), .CK(
FPADDSUB_inst_ShiftRegister_net8160791), .RN(n2909), .Q(
FPADDSUB_Shift_reg_FLAGS_7_5) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_3_ ( .D(busy), .CK(
FPADDSUB_inst_ShiftRegister_net8160791), .RN(n2902), .Q(
FPADDSUB_Shift_reg_FLAGS_7[3]) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_2_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7[3]), .CK(
FPADDSUB_inst_ShiftRegister_net8160791), .RN(n2893), .Q(
FPADDSUB_Shift_reg_FLAGS_7[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[4]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n2903), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[3]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n2898), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[2]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n913), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[1]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n912), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[0]), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n2901), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[0]) );
DFFRXLTS FPSENCOS_reg_region_flag_Q_reg_0_ ( .D(region_flag[0]), .CK(
FPSENCOS_reg_Z0_net8160917), .RN(n2944), .Q(
FPSENCOS_d_ff1_shift_region_flag_out_0_), .QN(n994) );
DFFRXLTS FPSENCOS_reg_region_flag_Q_reg_1_ ( .D(region_flag[1]), .CK(
FPSENCOS_reg_Z0_net8160917), .RN(n917), .QN(n946) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_0_ ( .D(n852), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n1729), .Q(
FPSENCOS_d_ff3_LUT_out[0]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_1_ ( .D(n862), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n917), .Q(
FPSENCOS_d_ff3_LUT_out[1]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_2_ ( .D(n856), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n918), .Q(
FPSENCOS_d_ff3_LUT_out[2]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_3_ ( .D(n864), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2936), .Q(
FPSENCOS_d_ff3_LUT_out[3]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_4_ ( .D(FPSENCOS_data_out_LUT[4]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2943), .Q(
FPSENCOS_d_ff3_LUT_out[4]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_5_ ( .D(n853), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n917), .Q(
FPSENCOS_d_ff3_LUT_out[5]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_6_ ( .D(n855), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n917), .Q(
FPSENCOS_d_ff3_LUT_out[6]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_7_ ( .D(n859), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n918), .Q(
FPSENCOS_d_ff3_LUT_out[7]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_8_ ( .D(n2747), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2936), .Q(
FPSENCOS_d_ff3_LUT_out[8]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_9_ ( .D(n861), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2943), .Q(
FPSENCOS_d_ff3_LUT_out[9]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_10_ ( .D(n854), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n1733), .Q(
FPSENCOS_d_ff3_LUT_out[10]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_12_ ( .D(n860), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2942), .Q(
FPSENCOS_d_ff3_LUT_out[12]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_13_ ( .D(n851), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2928), .Q(
FPSENCOS_d_ff3_LUT_out[13]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_15_ ( .D(n863), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2942), .Q(
FPSENCOS_d_ff3_LUT_out[15]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_19_ ( .D(n865), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2928), .Q(
FPSENCOS_d_ff3_LUT_out[19]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_21_ ( .D(n850), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2942), .Q(
FPSENCOS_d_ff3_LUT_out[21]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_23_ ( .D(n849), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2928), .Q(
FPSENCOS_d_ff3_LUT_out[23]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_24_ ( .D(n848), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2942), .Q(
FPSENCOS_d_ff3_LUT_out[24]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_25_ ( .D(FPSENCOS_data_out_LUT[25]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2928), .Q(
FPSENCOS_d_ff3_LUT_out[25]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_26_ ( .D(n857), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n918), .Q(
FPSENCOS_d_ff3_LUT_out[26]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_0_ ( .D(Data_1[0]), .CK(
FPSENCOS_reg_Z0_net8160917), .RN(n2945), .Q(FPSENCOS_d_ff1_Z[0]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_1_ ( .D(Data_1[1]), .CK(
FPSENCOS_reg_Z0_net8160917), .RN(n2934), .Q(FPSENCOS_d_ff1_Z[1]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_2_ ( .D(Data_1[2]), .CK(
FPSENCOS_reg_Z0_net8160917), .RN(n2944), .Q(FPSENCOS_d_ff1_Z[2]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_3_ ( .D(Data_1[3]), .CK(
FPSENCOS_reg_Z0_net8160917), .RN(n918), .Q(FPSENCOS_d_ff1_Z[3]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_4_ ( .D(Data_1[4]), .CK(
FPSENCOS_reg_Z0_net8160917), .RN(n2934), .Q(FPSENCOS_d_ff1_Z[4]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_5_ ( .D(Data_1[5]), .CK(
FPSENCOS_reg_Z0_net8160917), .RN(n918), .Q(FPSENCOS_d_ff1_Z[5]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_6_ ( .D(Data_1[6]), .CK(
FPSENCOS_reg_Z0_net8160917), .RN(n2944), .Q(FPSENCOS_d_ff1_Z[6]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_7_ ( .D(Data_1[7]), .CK(
FPSENCOS_reg_Z0_net8160917), .RN(n2945), .Q(FPSENCOS_d_ff1_Z[7]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_8_ ( .D(Data_1[8]), .CK(
FPSENCOS_reg_Z0_net8160917), .RN(n918), .Q(FPSENCOS_d_ff1_Z[8]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_9_ ( .D(Data_1[9]), .CK(
FPSENCOS_reg_Z0_net8160917), .RN(n918), .Q(FPSENCOS_d_ff1_Z[9]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_10_ ( .D(Data_1[10]), .CK(
FPSENCOS_reg_Z0_net8160917), .RN(n2934), .Q(FPSENCOS_d_ff1_Z[10]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_11_ ( .D(Data_1[11]), .CK(
FPSENCOS_reg_Z0_net8160917), .RN(n2944), .Q(FPSENCOS_d_ff1_Z[11]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_12_ ( .D(Data_1[12]), .CK(
FPSENCOS_reg_Z0_net8160917), .RN(n2944), .Q(FPSENCOS_d_ff1_Z[12]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_13_ ( .D(Data_1[13]), .CK(
FPSENCOS_reg_Z0_net8160917), .RN(n2945), .Q(FPSENCOS_d_ff1_Z[13]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_14_ ( .D(Data_1[14]), .CK(
FPSENCOS_reg_Z0_net8160917), .RN(n2933), .Q(FPSENCOS_d_ff1_Z[14]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_15_ ( .D(Data_1[15]), .CK(
FPSENCOS_reg_Z0_net8160917), .RN(n2941), .Q(FPSENCOS_d_ff1_Z[15]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_16_ ( .D(Data_1[16]), .CK(
FPSENCOS_reg_Z0_net8160917), .RN(n2933), .Q(FPSENCOS_d_ff1_Z[16]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_17_ ( .D(Data_1[17]), .CK(
FPSENCOS_reg_Z0_net8160917), .RN(n2938), .Q(FPSENCOS_d_ff1_Z[17]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_18_ ( .D(Data_1[18]), .CK(
FPSENCOS_reg_Z0_net8160917), .RN(n2937), .Q(FPSENCOS_d_ff1_Z[18]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_19_ ( .D(Data_1[19]), .CK(
FPSENCOS_reg_Z0_net8160917), .RN(n2943), .Q(FPSENCOS_d_ff1_Z[19]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_20_ ( .D(Data_1[20]), .CK(
FPSENCOS_reg_Z0_net8160917), .RN(n2935), .Q(FPSENCOS_d_ff1_Z[20]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_21_ ( .D(Data_1[21]), .CK(
FPSENCOS_reg_Z0_net8160917), .RN(n2941), .Q(FPSENCOS_d_ff1_Z[21]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_22_ ( .D(Data_1[22]), .CK(
FPSENCOS_reg_Z0_net8160917), .RN(n2938), .Q(FPSENCOS_d_ff1_Z[22]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_23_ ( .D(Data_1[23]), .CK(
FPSENCOS_reg_Z0_net8160917), .RN(n2935), .Q(FPSENCOS_d_ff1_Z[23]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_24_ ( .D(Data_1[24]), .CK(
FPSENCOS_reg_Z0_net8160917), .RN(n2935), .Q(FPSENCOS_d_ff1_Z[24]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_25_ ( .D(Data_1[25]), .CK(
FPSENCOS_reg_Z0_net8160917), .RN(n2939), .Q(FPSENCOS_d_ff1_Z[25]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_26_ ( .D(Data_1[26]), .CK(
FPSENCOS_reg_Z0_net8160917), .RN(n2940), .Q(FPSENCOS_d_ff1_Z[26]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_27_ ( .D(Data_1[27]), .CK(
FPSENCOS_reg_Z0_net8160917), .RN(n2940), .Q(FPSENCOS_d_ff1_Z[27]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_28_ ( .D(Data_1[28]), .CK(
FPSENCOS_reg_Z0_net8160917), .RN(n2940), .Q(FPSENCOS_d_ff1_Z[28]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_29_ ( .D(Data_1[29]), .CK(
FPSENCOS_reg_Z0_net8160917), .RN(n2940), .Q(FPSENCOS_d_ff1_Z[29]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_30_ ( .D(Data_1[30]), .CK(
FPSENCOS_reg_Z0_net8160917), .RN(n2940), .Q(FPSENCOS_d_ff1_Z[30]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_31_ ( .D(Data_1[31]), .CK(
FPSENCOS_reg_Z0_net8160917), .RN(n2940), .Q(FPSENCOS_d_ff1_Z[31]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_23_ ( .D(FPSENCOS_sh_exp_x[0]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2940), .Q(
FPSENCOS_d_ff3_sh_x_out[23]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_24_ ( .D(FPSENCOS_sh_exp_x[1]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2940), .Q(
FPSENCOS_d_ff3_sh_x_out[24]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_25_ ( .D(FPSENCOS_sh_exp_x[2]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2940), .Q(
FPSENCOS_d_ff3_sh_x_out[25]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_26_ ( .D(FPSENCOS_sh_exp_x[3]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2940), .Q(
FPSENCOS_d_ff3_sh_x_out[26]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_27_ ( .D(FPSENCOS_sh_exp_x[4]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2940), .Q(
FPSENCOS_d_ff3_sh_x_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_28_ ( .D(FPSENCOS_sh_exp_x[5]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2940), .Q(
FPSENCOS_d_ff3_sh_x_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_29_ ( .D(FPSENCOS_sh_exp_x[6]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2939), .Q(
FPSENCOS_d_ff3_sh_x_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_30_ ( .D(FPSENCOS_sh_exp_x[7]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2934), .Q(
FPSENCOS_d_ff3_sh_x_out[30]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_23_ ( .D(FPSENCOS_sh_exp_y[0]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2933), .Q(
FPSENCOS_d_ff3_sh_y_out[23]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_24_ ( .D(FPSENCOS_sh_exp_y[1]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2939), .Q(
FPSENCOS_d_ff3_sh_y_out[24]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_25_ ( .D(FPSENCOS_sh_exp_y[2]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2941), .Q(
FPSENCOS_d_ff3_sh_y_out[25]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_26_ ( .D(FPSENCOS_sh_exp_y[3]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2938), .Q(
FPSENCOS_d_ff3_sh_y_out[26]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_27_ ( .D(FPSENCOS_sh_exp_y[4]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2938), .Q(
FPSENCOS_d_ff3_sh_y_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_28_ ( .D(FPSENCOS_sh_exp_y[5]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2938), .Q(
FPSENCOS_d_ff3_sh_y_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_29_ ( .D(FPSENCOS_sh_exp_y[6]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2945), .Q(
FPSENCOS_d_ff3_sh_y_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_30_ ( .D(FPSENCOS_sh_exp_y[7]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2941), .Q(
FPSENCOS_d_ff3_sh_y_out[30]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
FPSENCOS_d_ff4_Xn_net8160917), .RN(n2937), .Q(FPSENCOS_d_ff_Xn[23]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
FPSENCOS_d_ff4_Xn_net8160917), .RN(n2941), .Q(FPSENCOS_d_ff_Xn[24]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
FPSENCOS_d_ff4_Xn_net8160917), .RN(n2929), .Q(FPSENCOS_d_ff_Xn[25]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
FPSENCOS_d_ff4_Xn_net8160917), .RN(n2938), .Q(FPSENCOS_d_ff_Xn[26]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
FPSENCOS_d_ff4_Xn_net8160917), .RN(n2935), .Q(FPSENCOS_d_ff_Xn[27]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_27_ ( .D(
FPSENCOS_first_mux_X[27]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2926), .QN(n953) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
FPSENCOS_d_ff4_Xn_net8160917), .RN(n2938), .Q(FPSENCOS_d_ff_Xn[28]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
FPSENCOS_d_ff4_Xn_net8160917), .RN(n2941), .Q(FPSENCOS_d_ff_Xn[29]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
FPSENCOS_d_ff4_Xn_net8160917), .RN(n916), .Q(FPSENCOS_d_ff_Xn[30]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_30_ ( .D(
FPSENCOS_first_mux_X[30]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2935), .Q(FPSENCOS_d_ff2_X[30]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
FPSENCOS_d_ff4_Yn_net8160917), .RN(n2937), .Q(FPSENCOS_d_ff_Yn[23]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_23_ ( .D(FPSENCOS_mux_sal[23]), .CK(
FPSENCOS_d_ff5_data_out_net8160917), .RN(n2937), .Q(cordic_result[23])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
FPSENCOS_d_ff4_Yn_net8160917), .RN(n2937), .Q(FPSENCOS_d_ff_Yn[24]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_24_ ( .D(FPSENCOS_mux_sal[24]), .CK(
FPSENCOS_d_ff5_data_out_net8160917), .RN(n2935), .Q(cordic_result[24])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
FPSENCOS_d_ff4_Yn_net8160917), .RN(n2933), .Q(FPSENCOS_d_ff_Yn[25]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_25_ ( .D(FPSENCOS_mux_sal[25]), .CK(
FPSENCOS_d_ff5_data_out_net8160917), .RN(n2939), .Q(cordic_result[25])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
FPSENCOS_d_ff4_Yn_net8160917), .RN(n2939), .Q(FPSENCOS_d_ff_Yn[26]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_26_ ( .D(FPSENCOS_mux_sal[26]), .CK(
FPSENCOS_d_ff5_data_out_net8160917), .RN(n2937), .Q(cordic_result[26])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
FPSENCOS_d_ff4_Yn_net8160917), .RN(n2935), .Q(FPSENCOS_d_ff_Yn[27]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_27_ ( .D(
FPSENCOS_first_mux_Y[27]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2935), .QN(n954) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_27_ ( .D(FPSENCOS_mux_sal[27]), .CK(
FPSENCOS_d_ff5_data_out_net8160917), .RN(n2935), .Q(cordic_result[27])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
FPSENCOS_d_ff4_Yn_net8160917), .RN(n916), .Q(FPSENCOS_d_ff_Yn[28]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_28_ ( .D(FPSENCOS_mux_sal[28]), .CK(
FPSENCOS_d_ff5_data_out_net8160917), .RN(n2933), .Q(cordic_result[28])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
FPSENCOS_d_ff4_Yn_net8160917), .RN(n2941), .Q(FPSENCOS_d_ff_Yn[29]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_29_ ( .D(
FPSENCOS_first_mux_Y[29]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2939), .QN(n955) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_29_ ( .D(FPSENCOS_mux_sal[29]), .CK(
FPSENCOS_d_ff5_data_out_net8160917), .RN(n2933), .Q(cordic_result[29])
);
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
FPSENCOS_d_ff4_Yn_net8160917), .RN(n2933), .Q(FPSENCOS_d_ff_Yn[30]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_30_ ( .D(
FPSENCOS_first_mux_Y[30]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2925), .Q(FPSENCOS_d_ff2_Y[30]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_30_ ( .D(FPSENCOS_mux_sal[30]), .CK(
FPSENCOS_d_ff5_data_out_net8160917), .RN(n2933), .Q(cordic_result[30])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
FPSENCOS_d_ff4_Zn_net8160917), .RN(n2943), .Q(FPSENCOS_d_ff_Zn[23]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_23_ ( .D(
FPSENCOS_first_mux_Z[23]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n1733), .Q(FPSENCOS_d_ff2_Z[23]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
FPSENCOS_d_ff4_Zn_net8160917), .RN(n2931), .Q(FPSENCOS_d_ff_Zn[24]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_24_ ( .D(
FPSENCOS_first_mux_Z[24]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2925), .Q(FPSENCOS_d_ff2_Z[24]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
FPSENCOS_d_ff4_Zn_net8160917), .RN(n2925), .Q(FPSENCOS_d_ff_Zn[25]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_25_ ( .D(
FPSENCOS_first_mux_Z[25]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2935), .Q(FPSENCOS_d_ff2_Z[25]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
FPSENCOS_d_ff4_Zn_net8160917), .RN(n2932), .Q(FPSENCOS_d_ff_Zn[26]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_26_ ( .D(
FPSENCOS_first_mux_Z[26]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n1733), .Q(FPSENCOS_d_ff2_Z[26]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
FPSENCOS_d_ff4_Zn_net8160917), .RN(n2931), .Q(FPSENCOS_d_ff_Zn[27]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_27_ ( .D(
FPSENCOS_first_mux_Z[27]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2925), .Q(FPSENCOS_d_ff2_Z[27]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
FPSENCOS_d_ff4_Zn_net8160917), .RN(n917), .Q(FPSENCOS_d_ff_Zn[28]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_28_ ( .D(
FPSENCOS_first_mux_Z[28]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2936), .Q(FPSENCOS_d_ff2_Z[28]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
FPSENCOS_d_ff4_Zn_net8160917), .RN(n918), .Q(FPSENCOS_d_ff_Zn[29]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_29_ ( .D(
FPSENCOS_first_mux_Z[29]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2943), .Q(FPSENCOS_d_ff2_Z[29]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
FPSENCOS_d_ff4_Zn_net8160917), .RN(n2925), .Q(FPSENCOS_d_ff_Zn[30]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_30_ ( .D(
FPSENCOS_first_mux_Z[30]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n917), .Q(FPSENCOS_d_ff2_Z[30]) );
DFFRXLTS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(add_subt_data1[24]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2893), .QN(n945)
);
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_23_ ( .D(FPADDSUB_DmP_INIT_EWSW[23]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n914), .Q(
FPADDSUB_DmP_EXP_EWSW[23]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_24_ ( .D(FPADDSUB_DmP_INIT_EWSW[24]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2892), .Q(
FPADDSUB_DmP_EXP_EWSW[24]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_25_ ( .D(FPADDSUB_DmP_INIT_EWSW[25]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2895), .Q(
FPADDSUB_DmP_EXP_EWSW[25]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_26_ ( .D(FPADDSUB_DmP_INIT_EWSW[26]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2902), .Q(
FPADDSUB_DmP_EXP_EWSW[26]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_27_ ( .D(FPADDSUB_DmP_INIT_EWSW[27]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n1734), .Q(
FPADDSUB_DmP_EXP_EWSW[27]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_23_ ( .D(FPADDSUB_DMP_INIT_EWSW[23]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2894), .Q(
FPADDSUB_DMP_EXP_EWSW[23]), .QN(n992) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_27_ ( .D(FPADDSUB_DMP_INIT_EWSW[27]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2900), .Q(
FPADDSUB_DMP_EXP_EWSW[27]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_28_ ( .D(FPADDSUB_DMP_INIT_EWSW[28]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2897), .Q(
FPADDSUB_DMP_EXP_EWSW[28]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_29_ ( .D(FPADDSUB_DMP_INIT_EWSW[29]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n1734), .Q(
FPADDSUB_DMP_EXP_EWSW[29]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_30_ ( .D(FPADDSUB_DMP_INIT_EWSW[30]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2891), .Q(
FPADDSUB_DMP_EXP_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_23_ ( .D(FPADDSUB_DMP_EXP_EWSW[23]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n1831), .Q(
FPADDSUB_DMP_SHT1_EWSW[23]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_24_ ( .D(FPADDSUB_DMP_EXP_EWSW[24]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n2907), .Q(
FPADDSUB_DMP_SHT1_EWSW[24]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_25_ ( .D(FPADDSUB_DMP_EXP_EWSW[25]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n914), .Q(
FPADDSUB_DMP_SHT1_EWSW[25]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_26_ ( .D(FPADDSUB_DMP_EXP_EWSW[26]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n2900), .Q(
FPADDSUB_DMP_SHT1_EWSW[26]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_27_ ( .D(FPADDSUB_DMP_EXP_EWSW[27]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n2895), .Q(
FPADDSUB_DMP_SHT1_EWSW[27]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_28_ ( .D(FPADDSUB_DMP_EXP_EWSW[28]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n2897), .Q(
FPADDSUB_DMP_SHT1_EWSW[28]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_29_ ( .D(FPADDSUB_DMP_EXP_EWSW[29]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n2894), .Q(
FPADDSUB_DMP_SHT1_EWSW[29]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_30_ ( .D(FPADDSUB_DMP_EXP_EWSW[30]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n2901), .Q(
FPADDSUB_DMP_SHT1_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_23_ ( .D(FPADDSUB_DMP_SHT1_EWSW[23]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8160683), .RN(n2905), .Q(
FPADDSUB_DMP_SHT2_EWSW[23]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_23_ ( .D(FPADDSUB_DMP_SHT2_EWSW[23]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n913), .Q(
FPADDSUB_DMP_SFG[23]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(FPADDSUB_DMP_SFG[23]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8160665), .RN(n913), .Q(
FPADDSUB_DMP_exp_NRM_EW[0]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[0]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8160701), .RN(n913), .Q(
FPADDSUB_DMP_exp_NRM2_EW[0]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_24_ ( .D(FPADDSUB_DMP_SHT1_EWSW[24]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8160683), .RN(n2904), .Q(
FPADDSUB_DMP_SHT2_EWSW[24]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_24_ ( .D(FPADDSUB_DMP_SHT2_EWSW[24]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2894), .Q(
FPADDSUB_DMP_SFG[24]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(FPADDSUB_DMP_SFG[24]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8160665), .RN(n912), .Q(
FPADDSUB_DMP_exp_NRM_EW[1]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[1]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8160701), .RN(n2901), .Q(
FPADDSUB_DMP_exp_NRM2_EW[1]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_25_ ( .D(FPADDSUB_DMP_SHT1_EWSW[25]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8160683), .RN(n914), .Q(
FPADDSUB_DMP_SHT2_EWSW[25]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_25_ ( .D(FPADDSUB_DMP_SHT2_EWSW[25]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2898), .Q(
FPADDSUB_DMP_SFG[25]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(FPADDSUB_DMP_SFG[25]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8160665), .RN(n2903), .Q(
FPADDSUB_DMP_exp_NRM_EW[2]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[2]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8160701), .RN(n2894), .Q(
FPADDSUB_DMP_exp_NRM2_EW[2]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_26_ ( .D(FPADDSUB_DMP_SHT1_EWSW[26]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8160683), .RN(n2892), .Q(
FPADDSUB_DMP_SHT2_EWSW[26]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_26_ ( .D(FPADDSUB_DMP_SHT2_EWSW[26]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2902), .Q(
FPADDSUB_DMP_SFG[26]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(FPADDSUB_DMP_SFG[26]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8160665), .RN(n2909), .Q(
FPADDSUB_DMP_exp_NRM_EW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[3]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8160701), .RN(n2910), .Q(
FPADDSUB_DMP_exp_NRM2_EW[3]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_27_ ( .D(FPADDSUB_DMP_SHT1_EWSW[27]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8160683), .RN(n1734), .Q(
FPADDSUB_DMP_SHT2_EWSW[27]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_27_ ( .D(FPADDSUB_DMP_SHT2_EWSW[27]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n912), .Q(
FPADDSUB_DMP_SFG[27]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(FPADDSUB_DMP_SFG[27]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8160665), .RN(n913), .Q(
FPADDSUB_DMP_exp_NRM_EW[4]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[4]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8160701), .RN(n2893), .Q(
FPADDSUB_DMP_exp_NRM2_EW[4]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_28_ ( .D(FPADDSUB_DMP_SHT1_EWSW[28]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8160683), .RN(n2897), .Q(
FPADDSUB_DMP_SHT2_EWSW[28]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_28_ ( .D(FPADDSUB_DMP_SHT2_EWSW[28]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n912), .Q(
FPADDSUB_DMP_SFG[28]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(FPADDSUB_DMP_SFG[28]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8160665), .RN(n913), .Q(
FPADDSUB_DMP_exp_NRM_EW[5]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[5]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8160701), .RN(n912), .Q(
FPADDSUB_DMP_exp_NRM2_EW[5]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_29_ ( .D(FPADDSUB_DMP_SHT1_EWSW[29]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8160683), .RN(n1734), .Q(
FPADDSUB_DMP_SHT2_EWSW[29]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_29_ ( .D(FPADDSUB_DMP_SHT2_EWSW[29]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n914), .Q(
FPADDSUB_DMP_SFG[29]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(FPADDSUB_DMP_SFG[29]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8160665), .RN(n914), .Q(
FPADDSUB_DMP_exp_NRM_EW[6]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[6]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8160701), .RN(n912), .Q(
FPADDSUB_DMP_exp_NRM2_EW[6]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_30_ ( .D(FPADDSUB_DMP_SHT1_EWSW[30]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8160683), .RN(n1734), .Q(
FPADDSUB_DMP_SHT2_EWSW[30]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_30_ ( .D(FPADDSUB_DMP_SHT2_EWSW[30]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n1734), .Q(
FPADDSUB_DMP_SFG[30]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(FPADDSUB_DMP_SFG[30]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8160665), .RN(n914), .Q(
FPADDSUB_DMP_exp_NRM_EW[7]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[7]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8160701), .RN(n914), .Q(
FPADDSUB_DMP_exp_NRM2_EW[7]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_25_ ( .D(FPADDSUB_Data_array_SWR[25]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8160665), .RN(n2901), .Q(
FPADDSUB_Data_array_SWR[51]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
FPSENCOS_d_ff4_Xn_net8160917), .RN(n1729), .Q(FPSENCOS_d_ff_Xn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_22_ ( .D(
FPSENCOS_first_mux_X[22]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n917), .Q(FPSENCOS_d_ff2_X[22]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_22_ ( .D(FPSENCOS_d_ff2_X[22]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2936), .Q(
FPSENCOS_d_ff3_sh_x_out[22]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
FPSENCOS_d_ff4_Yn_net8160917), .RN(n918), .Q(FPSENCOS_d_ff_Yn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_22_ ( .D(
FPSENCOS_first_mux_Y[22]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2943), .Q(FPSENCOS_d_ff2_Y[22]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_22_ ( .D(FPSENCOS_d_ff2_Y[22]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2925), .Q(
FPSENCOS_d_ff3_sh_y_out[22]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_22_ ( .D(FPSENCOS_mux_sal[22]), .CK(
FPSENCOS_d_ff5_data_out_net8160917), .RN(n2941), .Q(cordic_result[22])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
FPSENCOS_d_ff4_Zn_net8160917), .RN(n2929), .Q(FPSENCOS_d_ff_Zn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_22_ ( .D(
FPSENCOS_first_mux_Z[22]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2937), .Q(FPSENCOS_d_ff2_Z[22]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_22_ ( .D(FPADDSUB_DmP_INIT_EWSW[22]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2898), .Q(
FPADDSUB_DmP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(
FPADDSUB_DmP_EXP_EWSW[22]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8160683),
.RN(n2903), .Q(FPADDSUB_DmP_mant_SHT1_SW[22]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
FPSENCOS_d_ff4_Xn_net8160917), .RN(n2937), .Q(FPSENCOS_d_ff_Xn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_19_ ( .D(
FPSENCOS_first_mux_X[19]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2938), .Q(FPSENCOS_d_ff2_X[19]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_19_ ( .D(FPSENCOS_d_ff2_X[19]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2941), .Q(
FPSENCOS_d_ff3_sh_x_out[19]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
FPSENCOS_d_ff4_Yn_net8160917), .RN(n2941), .Q(FPSENCOS_d_ff_Yn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_19_ ( .D(
FPSENCOS_first_mux_Y[19]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2933), .Q(FPSENCOS_d_ff2_Y[19]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_19_ ( .D(FPSENCOS_d_ff2_Y[19]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2929), .Q(
FPSENCOS_d_ff3_sh_y_out[19]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_19_ ( .D(FPSENCOS_mux_sal[19]), .CK(
FPSENCOS_d_ff5_data_out_net8160917), .RN(n2939), .Q(cordic_result[19])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
FPSENCOS_d_ff4_Zn_net8160917), .RN(n2939), .Q(FPSENCOS_d_ff_Zn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_19_ ( .D(
FPSENCOS_first_mux_Z[19]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2935), .Q(FPSENCOS_d_ff2_Z[19]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_19_ ( .D(FPADDSUB_DmP_INIT_EWSW[19]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n912), .Q(
FPADDSUB_DmP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(
FPADDSUB_DmP_EXP_EWSW[19]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8160683),
.RN(n2894), .Q(FPADDSUB_DmP_mant_SHT1_SW[19]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_2_ ( .D(FPADDSUB_Data_array_SWR[2]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8160665), .RN(n2897), .Q(
FPADDSUB_Data_array_SWR[28]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
FPSENCOS_d_ff4_Xn_net8160917), .RN(n917), .Q(FPSENCOS_d_ff_Xn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_21_ ( .D(
FPSENCOS_first_mux_X[21]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n917), .Q(FPSENCOS_d_ff2_X[21]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_21_ ( .D(FPSENCOS_d_ff2_X[21]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n918), .Q(
FPSENCOS_d_ff3_sh_x_out[21]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
FPSENCOS_d_ff4_Yn_net8160917), .RN(n2936), .Q(FPSENCOS_d_ff_Yn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_21_ ( .D(
FPSENCOS_first_mux_Y[21]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2943), .Q(FPSENCOS_d_ff2_Y[21]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_21_ ( .D(FPSENCOS_d_ff2_Y[21]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2925), .Q(
FPSENCOS_d_ff3_sh_y_out[21]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_21_ ( .D(FPSENCOS_mux_sal[21]), .CK(
FPSENCOS_d_ff5_data_out_net8160917), .RN(n917), .Q(cordic_result[21])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
FPSENCOS_d_ff4_Zn_net8160917), .RN(n1729), .Q(FPSENCOS_d_ff_Zn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_21_ ( .D(
FPSENCOS_first_mux_Z[21]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n917), .Q(FPSENCOS_d_ff2_Z[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_21_ ( .D(FPADDSUB_DmP_INIT_EWSW[21]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2907), .Q(
FPADDSUB_DmP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(
FPADDSUB_DmP_EXP_EWSW[21]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8160683),
.RN(n2891), .Q(FPADDSUB_DmP_mant_SHT1_SW[21]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(
FPSENCOS_d_ff4_Xn_net8160917), .RN(n918), .Q(FPSENCOS_d_ff_Xn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_2_ ( .D(FPSENCOS_first_mux_X[2]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2936), .Q(
FPSENCOS_d_ff2_X[2]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_2_ ( .D(FPSENCOS_d_ff2_X[2]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2943), .Q(
FPSENCOS_d_ff3_sh_x_out[2]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(
FPSENCOS_d_ff4_Yn_net8160917), .RN(n2934), .Q(FPSENCOS_d_ff_Yn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_2_ ( .D(FPSENCOS_first_mux_Y[2]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2945), .Q(
FPSENCOS_d_ff2_Y[2]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_2_ ( .D(FPSENCOS_d_ff2_Y[2]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2946), .Q(
FPSENCOS_d_ff3_sh_y_out[2]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_2_ ( .D(FPSENCOS_mux_sal[2]), .CK(
FPSENCOS_d_ff5_data_out_net8160917), .RN(n2934), .Q(cordic_result[2])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(
FPSENCOS_d_ff4_Zn_net8160917), .RN(n2945), .Q(FPSENCOS_d_ff_Zn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_2_ ( .D(FPSENCOS_first_mux_Z[2]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2946), .Q(
FPSENCOS_d_ff2_Z[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_2_ ( .D(FPADDSUB_DmP_INIT_EWSW[2]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n914), .Q(
FPADDSUB_DmP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(FPADDSUB_DmP_EXP_EWSW[2]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n1831), .Q(
FPADDSUB_DmP_mant_SHT1_SW[2]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
FPSENCOS_d_ff4_Xn_net8160917), .RN(n2934), .Q(FPSENCOS_d_ff_Xn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_16_ ( .D(
FPSENCOS_first_mux_X[16]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2945), .Q(FPSENCOS_d_ff2_X[16]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_16_ ( .D(FPSENCOS_d_ff2_X[16]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2946), .Q(
FPSENCOS_d_ff3_sh_x_out[16]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
FPSENCOS_d_ff4_Yn_net8160917), .RN(n2934), .Q(FPSENCOS_d_ff_Yn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_16_ ( .D(
FPSENCOS_first_mux_Y[16]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2945), .Q(FPSENCOS_d_ff2_Y[16]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_16_ ( .D(FPSENCOS_d_ff2_Y[16]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2946), .Q(
FPSENCOS_d_ff3_sh_y_out[16]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_16_ ( .D(FPSENCOS_mux_sal[16]), .CK(
FPSENCOS_d_ff5_data_out_net8160917), .RN(n2937), .Q(cordic_result[16])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
FPSENCOS_d_ff4_Zn_net8160917), .RN(n2941), .Q(FPSENCOS_d_ff_Zn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_16_ ( .D(
FPSENCOS_first_mux_Z[16]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2933), .Q(FPSENCOS_d_ff2_Z[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_16_ ( .D(FPADDSUB_DmP_INIT_EWSW[16]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n912), .Q(
FPADDSUB_DmP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(
FPADDSUB_DmP_EXP_EWSW[16]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8160683),
.RN(n2901), .Q(FPADDSUB_DmP_mant_SHT1_SW[16]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
FPSENCOS_d_ff4_Xn_net8160917), .RN(n2929), .Q(FPSENCOS_d_ff_Xn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_18_ ( .D(
FPSENCOS_first_mux_X[18]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2941), .Q(FPSENCOS_d_ff2_X[18]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_18_ ( .D(FPSENCOS_d_ff2_X[18]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2935), .Q(
FPSENCOS_d_ff3_sh_x_out[18]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
FPSENCOS_d_ff4_Yn_net8160917), .RN(n2933), .Q(FPSENCOS_d_ff_Yn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_18_ ( .D(
FPSENCOS_first_mux_Y[18]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2939), .Q(FPSENCOS_d_ff2_Y[18]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_18_ ( .D(FPSENCOS_d_ff2_Y[18]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2933), .Q(
FPSENCOS_d_ff3_sh_y_out[18]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_18_ ( .D(FPSENCOS_mux_sal[18]), .CK(
FPSENCOS_d_ff5_data_out_net8160917), .RN(n2941), .Q(cordic_result[18])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
FPSENCOS_d_ff4_Zn_net8160917), .RN(n918), .Q(FPSENCOS_d_ff_Zn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_18_ ( .D(
FPSENCOS_first_mux_Z[18]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2938), .Q(FPSENCOS_d_ff2_Z[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_18_ ( .D(FPADDSUB_DmP_INIT_EWSW[18]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2909), .Q(
FPADDSUB_DmP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(
FPADDSUB_DmP_EXP_EWSW[18]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8160683),
.RN(n2902), .Q(FPADDSUB_DmP_mant_SHT1_SW[18]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_3_ ( .D(FPADDSUB_Data_array_SWR[3]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8160665), .RN(n2900), .Q(
FPADDSUB_Data_array_SWR[29]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
FPSENCOS_d_ff4_Xn_net8160917), .RN(n2932), .Q(FPSENCOS_d_ff_Xn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_20_ ( .D(
FPSENCOS_first_mux_X[20]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2932), .Q(FPSENCOS_d_ff2_X[20]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_20_ ( .D(FPSENCOS_d_ff2_X[20]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2932), .Q(
FPSENCOS_d_ff3_sh_x_out[20]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
FPSENCOS_d_ff4_Yn_net8160917), .RN(n2932), .Q(FPSENCOS_d_ff_Yn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_20_ ( .D(
FPSENCOS_first_mux_Y[20]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2932), .Q(FPSENCOS_d_ff2_Y[20]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_20_ ( .D(FPSENCOS_d_ff2_Y[20]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2932), .Q(
FPSENCOS_d_ff3_sh_y_out[20]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_20_ ( .D(FPSENCOS_mux_sal[20]), .CK(
FPSENCOS_d_ff5_data_out_net8160917), .RN(n2932), .Q(cordic_result[20])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
FPSENCOS_d_ff4_Zn_net8160917), .RN(n2932), .Q(FPSENCOS_d_ff_Zn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_20_ ( .D(
FPSENCOS_first_mux_Z[20]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2932), .Q(FPSENCOS_d_ff2_Z[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_20_ ( .D(FPADDSUB_DmP_INIT_EWSW[20]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n1734), .Q(
FPADDSUB_DmP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(
FPADDSUB_DmP_EXP_EWSW[20]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8160683),
.RN(n2894), .Q(FPADDSUB_DmP_mant_SHT1_SW[20]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
FPSENCOS_d_ff4_Xn_net8160917), .RN(n2932), .Q(FPSENCOS_d_ff_Xn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_17_ ( .D(
FPSENCOS_first_mux_X[17]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2932), .Q(FPSENCOS_d_ff2_X[17]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_17_ ( .D(FPSENCOS_d_ff2_X[17]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2932), .Q(
FPSENCOS_d_ff3_sh_x_out[17]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
FPSENCOS_d_ff4_Yn_net8160917), .RN(n1733), .Q(FPSENCOS_d_ff_Yn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_17_ ( .D(
FPSENCOS_first_mux_Y[17]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2931), .Q(FPSENCOS_d_ff2_Y[17]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_17_ ( .D(FPSENCOS_d_ff2_Y[17]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2925), .Q(
FPSENCOS_d_ff3_sh_y_out[17]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_17_ ( .D(FPSENCOS_mux_sal[17]), .CK(
FPSENCOS_d_ff5_data_out_net8160917), .RN(n2943), .Q(cordic_result[17])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
FPSENCOS_d_ff4_Zn_net8160917), .RN(n2945), .Q(FPSENCOS_d_ff_Zn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_17_ ( .D(
FPSENCOS_first_mux_Z[17]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2940), .Q(FPSENCOS_d_ff2_Z[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_17_ ( .D(FPADDSUB_DmP_INIT_EWSW[17]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2901), .Q(
FPADDSUB_DmP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(
FPADDSUB_DmP_EXP_EWSW[17]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8160683),
.RN(n2908), .Q(FPADDSUB_DmP_mant_SHT1_SW[17]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(
FPSENCOS_d_ff4_Xn_net8160917), .RN(n2939), .Q(FPSENCOS_d_ff_Xn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_4_ ( .D(FPSENCOS_first_mux_X[4]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n1733), .Q(
FPSENCOS_d_ff2_X[4]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_4_ ( .D(FPSENCOS_d_ff2_X[4]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2931), .Q(
FPSENCOS_d_ff3_sh_x_out[4]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(
FPSENCOS_d_ff4_Yn_net8160917), .RN(n2925), .Q(FPSENCOS_d_ff_Yn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_4_ ( .D(FPSENCOS_first_mux_Y[4]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2944), .Q(
FPSENCOS_d_ff2_Y[4]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_4_ ( .D(FPSENCOS_d_ff2_Y[4]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2943), .Q(
FPSENCOS_d_ff3_sh_y_out[4]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_4_ ( .D(FPSENCOS_mux_sal[4]), .CK(
FPSENCOS_d_ff5_data_out_net8160917), .RN(n2935), .Q(cordic_result[4])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(
FPSENCOS_d_ff4_Zn_net8160917), .RN(n1733), .Q(FPSENCOS_d_ff_Zn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_4_ ( .D(FPSENCOS_first_mux_Z[4]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n1733), .Q(
FPSENCOS_d_ff2_Z[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_4_ ( .D(FPADDSUB_DmP_INIT_EWSW[4]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2909), .Q(
FPADDSUB_DmP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(FPADDSUB_DmP_EXP_EWSW[4]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n2902), .Q(
FPADDSUB_DmP_mant_SHT1_SW[4]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
FPSENCOS_d_ff4_Xn_net8160917), .RN(n2931), .Q(FPSENCOS_d_ff_Xn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_15_ ( .D(
FPSENCOS_first_mux_X[15]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2925), .Q(FPSENCOS_d_ff2_X[15]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_15_ ( .D(FPSENCOS_d_ff2_X[15]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2938), .Q(
FPSENCOS_d_ff3_sh_x_out[15]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
FPSENCOS_d_ff4_Yn_net8160917), .RN(n2938), .Q(FPSENCOS_d_ff_Yn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_15_ ( .D(
FPSENCOS_first_mux_Y[15]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2930), .Q(FPSENCOS_d_ff2_Y[15]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_15_ ( .D(FPSENCOS_d_ff2_Y[15]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2937), .Q(
FPSENCOS_d_ff3_sh_y_out[15]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_15_ ( .D(FPSENCOS_mux_sal[15]), .CK(
FPSENCOS_d_ff5_data_out_net8160917), .RN(n1733), .Q(cordic_result[15])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
FPSENCOS_d_ff4_Zn_net8160917), .RN(n2931), .Q(FPSENCOS_d_ff_Zn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_15_ ( .D(
FPSENCOS_first_mux_Z[15]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2925), .Q(FPSENCOS_d_ff2_Z[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_15_ ( .D(FPADDSUB_DmP_INIT_EWSW[15]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2893), .Q(
FPADDSUB_DmP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(
FPADDSUB_DmP_EXP_EWSW[15]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8160683),
.RN(n913), .Q(FPADDSUB_DmP_mant_SHT1_SW[15]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(
FPSENCOS_d_ff4_Xn_net8160917), .RN(n2930), .Q(FPSENCOS_d_ff_Xn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_5_ ( .D(FPSENCOS_first_mux_X[5]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2930), .Q(
FPSENCOS_d_ff2_X[5]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_5_ ( .D(FPSENCOS_d_ff2_X[5]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2930), .Q(
FPSENCOS_d_ff3_sh_x_out[5]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(
FPSENCOS_d_ff4_Yn_net8160917), .RN(n2930), .Q(FPSENCOS_d_ff_Yn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_5_ ( .D(FPSENCOS_first_mux_Y[5]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2930), .Q(
FPSENCOS_d_ff2_Y[5]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_5_ ( .D(FPSENCOS_d_ff2_Y[5]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2930), .Q(
FPSENCOS_d_ff3_sh_y_out[5]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_5_ ( .D(FPSENCOS_mux_sal[5]), .CK(
FPSENCOS_d_ff5_data_out_net8160917), .RN(n2930), .Q(cordic_result[5])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(
FPSENCOS_d_ff4_Zn_net8160917), .RN(n2930), .Q(FPSENCOS_d_ff_Zn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_5_ ( .D(FPSENCOS_first_mux_Z[5]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2930), .Q(
FPSENCOS_d_ff2_Z[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_5_ ( .D(FPADDSUB_DmP_INIT_EWSW[5]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n914), .Q(
FPADDSUB_DmP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(FPADDSUB_DmP_EXP_EWSW[5]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n2892), .Q(
FPADDSUB_DmP_mant_SHT1_SW[5]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
FPSENCOS_d_ff4_Xn_net8160917), .RN(n2930), .Q(FPSENCOS_d_ff_Xn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_13_ ( .D(
FPSENCOS_first_mux_X[13]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2930), .Q(FPSENCOS_d_ff2_X[13]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_13_ ( .D(FPSENCOS_d_ff2_X[13]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2930), .Q(
FPSENCOS_d_ff3_sh_x_out[13]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
FPSENCOS_d_ff4_Yn_net8160917), .RN(n916), .Q(FPSENCOS_d_ff_Yn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_13_ ( .D(
FPSENCOS_first_mux_Y[13]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2937), .Q(FPSENCOS_d_ff2_Y[13]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_13_ ( .D(FPSENCOS_d_ff2_Y[13]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n1733), .Q(
FPSENCOS_d_ff3_sh_y_out[13]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_13_ ( .D(FPSENCOS_mux_sal[13]), .CK(
FPSENCOS_d_ff5_data_out_net8160917), .RN(n2943), .Q(cordic_result[13])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
FPSENCOS_d_ff4_Zn_net8160917), .RN(n2942), .Q(FPSENCOS_d_ff_Zn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_13_ ( .D(
FPSENCOS_first_mux_Z[13]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n1733), .Q(FPSENCOS_d_ff2_Z[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_13_ ( .D(FPADDSUB_DmP_INIT_EWSW[13]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2895), .Q(
FPADDSUB_DmP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(
FPADDSUB_DmP_EXP_EWSW[13]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8160683),
.RN(n2908), .Q(FPADDSUB_DmP_mant_SHT1_SW[13]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
FPSENCOS_d_ff4_Xn_net8160917), .RN(n2931), .Q(FPSENCOS_d_ff_Xn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_14_ ( .D(
FPSENCOS_first_mux_X[14]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2925), .Q(FPSENCOS_d_ff2_X[14]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_14_ ( .D(FPSENCOS_d_ff2_X[14]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2925), .Q(
FPSENCOS_d_ff3_sh_x_out[14]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
FPSENCOS_d_ff4_Yn_net8160917), .RN(n2934), .Q(FPSENCOS_d_ff_Yn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_14_ ( .D(
FPSENCOS_first_mux_Y[14]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2938), .Q(FPSENCOS_d_ff2_Y[14]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_14_ ( .D(FPSENCOS_d_ff2_Y[14]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2943), .Q(
FPSENCOS_d_ff3_sh_y_out[14]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_14_ ( .D(FPSENCOS_mux_sal[14]), .CK(
FPSENCOS_d_ff5_data_out_net8160917), .RN(n2933), .Q(cordic_result[14])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
FPSENCOS_d_ff4_Zn_net8160917), .RN(n916), .Q(FPSENCOS_d_ff_Zn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_14_ ( .D(
FPSENCOS_first_mux_Z[14]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2932), .Q(FPSENCOS_d_ff2_Z[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_14_ ( .D(FPADDSUB_DmP_INIT_EWSW[14]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2904), .Q(
FPADDSUB_DmP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(
FPADDSUB_DmP_EXP_EWSW[14]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8160683),
.RN(n914), .Q(FPADDSUB_DmP_mant_SHT1_SW[14]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
FPSENCOS_d_ff4_Xn_net8160917), .RN(n2939), .Q(FPSENCOS_d_ff_Xn[11]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_11_ ( .D(
FPSENCOS_first_mux_X[11]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2931), .Q(FPSENCOS_d_ff2_X[11]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_11_ ( .D(FPSENCOS_d_ff2_X[11]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2925), .Q(
FPSENCOS_d_ff3_sh_x_out[11]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
FPSENCOS_d_ff4_Yn_net8160917), .RN(n2932), .Q(FPSENCOS_d_ff_Yn[11]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_11_ ( .D(
FPSENCOS_first_mux_Y[11]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2940), .Q(FPSENCOS_d_ff2_Y[11]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_11_ ( .D(FPSENCOS_d_ff2_Y[11]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2940), .Q(
FPSENCOS_d_ff3_sh_y_out[11]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_11_ ( .D(FPSENCOS_mux_sal[11]), .CK(
FPSENCOS_d_ff5_data_out_net8160917), .RN(n1733), .Q(cordic_result[11])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
FPSENCOS_d_ff4_Zn_net8160917), .RN(n2931), .Q(FPSENCOS_d_ff_Zn[11]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_11_ ( .D(
FPSENCOS_first_mux_Z[11]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2925), .Q(FPSENCOS_d_ff2_Z[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_11_ ( .D(FPADDSUB_DmP_INIT_EWSW[11]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2901), .Q(
FPADDSUB_DmP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(
FPADDSUB_DmP_EXP_EWSW[11]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8160683),
.RN(n2892), .Q(FPADDSUB_DmP_mant_SHT1_SW[11]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(
FPSENCOS_d_ff4_Xn_net8160917), .RN(n2929), .Q(FPSENCOS_d_ff_Xn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_8_ ( .D(FPSENCOS_first_mux_X[8]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2929), .Q(
FPSENCOS_d_ff2_X[8]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_8_ ( .D(FPSENCOS_d_ff2_X[8]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2929), .Q(
FPSENCOS_d_ff3_sh_x_out[8]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(
FPSENCOS_d_ff4_Yn_net8160917), .RN(n2929), .Q(FPSENCOS_d_ff_Yn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_8_ ( .D(FPSENCOS_first_mux_Y[8]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2929), .Q(
FPSENCOS_d_ff2_Y[8]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_8_ ( .D(FPSENCOS_d_ff2_Y[8]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2929), .Q(
FPSENCOS_d_ff3_sh_y_out[8]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_8_ ( .D(FPSENCOS_mux_sal[8]), .CK(
FPSENCOS_d_ff5_data_out_net8160917), .RN(n2929), .Q(cordic_result[8])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(
FPSENCOS_d_ff4_Zn_net8160917), .RN(n2929), .Q(FPSENCOS_d_ff_Zn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_8_ ( .D(FPSENCOS_first_mux_Z[8]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2929), .Q(
FPSENCOS_d_ff2_Z[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_8_ ( .D(FPADDSUB_DmP_INIT_EWSW[8]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2894), .Q(
FPADDSUB_DmP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(FPADDSUB_DmP_EXP_EWSW[8]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n2892), .Q(
FPADDSUB_DmP_mant_SHT1_SW[8]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
FPSENCOS_d_ff4_Xn_net8160917), .RN(n2929), .Q(FPSENCOS_d_ff_Xn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_10_ ( .D(
FPSENCOS_first_mux_X[10]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2929), .Q(FPSENCOS_d_ff2_X[10]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_10_ ( .D(FPSENCOS_d_ff2_X[10]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2929), .Q(
FPSENCOS_d_ff3_sh_x_out[10]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
FPSENCOS_d_ff4_Yn_net8160917), .RN(n2928), .Q(FPSENCOS_d_ff_Yn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_10_ ( .D(
FPSENCOS_first_mux_Y[10]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2942), .Q(FPSENCOS_d_ff2_Y[10]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_10_ ( .D(FPSENCOS_d_ff2_Y[10]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2928), .Q(
FPSENCOS_d_ff3_sh_y_out[10]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_10_ ( .D(FPSENCOS_mux_sal[10]), .CK(
FPSENCOS_d_ff5_data_out_net8160917), .RN(n2942), .Q(cordic_result[10])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
FPSENCOS_d_ff4_Zn_net8160917), .RN(n2928), .Q(FPSENCOS_d_ff_Zn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_10_ ( .D(
FPSENCOS_first_mux_Z[10]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2942), .Q(FPSENCOS_d_ff2_Z[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_10_ ( .D(FPADDSUB_DmP_INIT_EWSW[10]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2903), .Q(
FPADDSUB_DmP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(
FPADDSUB_DmP_EXP_EWSW[10]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8160683),
.RN(n2898), .Q(FPADDSUB_DmP_mant_SHT1_SW[10]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
FPSENCOS_d_ff4_Xn_net8160917), .RN(n2928), .Q(FPSENCOS_d_ff_Xn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_12_ ( .D(
FPSENCOS_first_mux_X[12]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2942), .Q(FPSENCOS_d_ff2_X[12]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_12_ ( .D(FPSENCOS_d_ff2_X[12]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2928), .Q(
FPSENCOS_d_ff3_sh_x_out[12]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
FPSENCOS_d_ff4_Yn_net8160917), .RN(n2942), .Q(FPSENCOS_d_ff_Yn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_12_ ( .D(
FPSENCOS_first_mux_Y[12]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2928), .Q(FPSENCOS_d_ff2_Y[12]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_12_ ( .D(FPSENCOS_d_ff2_Y[12]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2942), .Q(
FPSENCOS_d_ff3_sh_y_out[12]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_12_ ( .D(FPSENCOS_mux_sal[12]), .CK(
FPSENCOS_d_ff5_data_out_net8160917), .RN(n2927), .Q(cordic_result[12])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
FPSENCOS_d_ff4_Zn_net8160917), .RN(n2927), .Q(FPSENCOS_d_ff_Zn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_12_ ( .D(
FPSENCOS_first_mux_Z[12]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2927), .Q(FPSENCOS_d_ff2_Z[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_12_ ( .D(FPADDSUB_DmP_INIT_EWSW[12]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2901), .Q(
FPADDSUB_DmP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(
FPADDSUB_DmP_EXP_EWSW[12]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8160683),
.RN(n912), .Q(FPADDSUB_DmP_mant_SHT1_SW[12]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(
FPSENCOS_d_ff4_Xn_net8160917), .RN(n2927), .Q(FPSENCOS_d_ff_Xn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_9_ ( .D(FPSENCOS_first_mux_X[9]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2927), .Q(
FPSENCOS_d_ff2_X[9]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_9_ ( .D(FPSENCOS_d_ff2_X[9]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2927), .Q(
FPSENCOS_d_ff3_sh_x_out[9]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(
FPSENCOS_d_ff4_Yn_net8160917), .RN(n2927), .Q(FPSENCOS_d_ff_Yn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_9_ ( .D(FPSENCOS_first_mux_Y[9]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2927), .Q(
FPSENCOS_d_ff2_Y[9]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_9_ ( .D(FPSENCOS_d_ff2_Y[9]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2927), .Q(
FPSENCOS_d_ff3_sh_y_out[9]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_9_ ( .D(FPSENCOS_mux_sal[9]), .CK(
FPSENCOS_d_ff5_data_out_net8160917), .RN(n2927), .Q(cordic_result[9])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(
FPSENCOS_d_ff4_Zn_net8160917), .RN(n2927), .Q(FPSENCOS_d_ff_Zn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_9_ ( .D(FPSENCOS_first_mux_Z[9]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2944), .Q(
FPSENCOS_d_ff2_Z[9]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
FPSENCOS_d_ff4_Xn_net8160917), .RN(n2926), .Q(FPSENCOS_d_ff_Xn[31]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_31_ ( .D(
FPSENCOS_first_mux_X[31]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2926), .Q(FPSENCOS_d_ff2_X[31]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_31_ ( .D(FPSENCOS_d_ff2_X[31]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2926), .Q(
FPSENCOS_d_ff3_sh_x_out[31]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
FPSENCOS_d_ff4_Yn_net8160917), .RN(n2926), .Q(FPSENCOS_d_ff_Yn[31]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_31_ ( .D(FPSENCOS_fmtted_Result_31_),
.CK(FPSENCOS_d_ff5_data_out_net8160917), .RN(n2926), .Q(
cordic_result[31]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_31_ ( .D(
FPSENCOS_first_mux_Y[31]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2926), .Q(FPSENCOS_d_ff2_Y[31]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_31_ ( .D(FPSENCOS_d_ff2_Y[31]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2926), .Q(
FPSENCOS_d_ff3_sh_y_out[31]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
FPSENCOS_d_ff4_Zn_net8160917), .RN(n2926), .Q(FPSENCOS_d_ff_Zn[31]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_31_ ( .D(
FPSENCOS_first_mux_Z[31]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2926), .Q(FPSENCOS_d_ff2_Z[31]) );
DFFRXLTS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(add_subt_data1[31]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n1734), .Q(
FPADDSUB_intDX_EWSW[31]) );
DFFRXLTS FPSENCOS_reg_sign_Q_reg_0_ ( .D(FPSENCOS_d_ff2_Z[31]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2926), .Q(
FPSENCOS_d_ff3_sign_out) );
DFFRXLTS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n2921), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8160665), .RN(n2905), .Q(
FPADDSUB_left_right_SHT2) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(
FPADDSUB_LZD_raw_out_EWR[3]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8160701), .RN(n913), .Q(
FPADDSUB_LZD_output_NRM2_EW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(
FPADDSUB_LZD_raw_out_EWR[0]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8160701), .RN(n913), .Q(
FPADDSUB_LZD_output_NRM2_EW[0]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(
FPADDSUB_LZD_raw_out_EWR[2]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8160701), .RN(n913), .Q(
FPADDSUB_LZD_output_NRM2_EW[2]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(
FPADDSUB_LZD_raw_out_EWR[1]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8160701), .RN(n913), .Q(
FPADDSUB_LZD_output_NRM2_EW[1]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(
FPADDSUB_LZD_raw_out_EWR[4]), .CK(
FPADDSUB_SFT2FRMT_STAGE_VARS_net8160701), .RN(n913), .Q(
FPADDSUB_LZD_output_NRM2_EW[4]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(
FPSENCOS_d_ff4_Xn_net8160917), .RN(n2934), .Q(FPSENCOS_d_ff_Xn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_0_ ( .D(FPSENCOS_first_mux_X[0]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2945), .Q(
FPSENCOS_d_ff2_X[0]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_0_ ( .D(FPSENCOS_d_ff2_X[0]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n916), .Q(
FPSENCOS_d_ff3_sh_x_out[0]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(
FPSENCOS_d_ff4_Yn_net8160917), .RN(n916), .Q(FPSENCOS_d_ff_Yn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_0_ ( .D(FPSENCOS_first_mux_Y[0]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n916), .Q(
FPSENCOS_d_ff2_Y[0]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_0_ ( .D(FPSENCOS_d_ff2_Y[0]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n916), .Q(
FPSENCOS_d_ff3_sh_y_out[0]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_0_ ( .D(FPSENCOS_mux_sal[0]), .CK(
FPSENCOS_d_ff5_data_out_net8160917), .RN(n916), .Q(cordic_result[0])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(
FPSENCOS_d_ff4_Zn_net8160917), .RN(n916), .Q(FPSENCOS_d_ff_Zn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_0_ ( .D(FPSENCOS_first_mux_Z[0]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n916), .Q(
FPSENCOS_d_ff2_Z[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_0_ ( .D(FPADDSUB_DmP_INIT_EWSW[0]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2901), .Q(
FPADDSUB_DmP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(FPADDSUB_DmP_EXP_EWSW[0]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n2898), .Q(
FPADDSUB_DmP_mant_SHT1_SW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_0_ ( .D(FPADDSUB_DMP_INIT_EWSW[0]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2903), .Q(
FPADDSUB_DMP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_0_ ( .D(FPADDSUB_DMP_EXP_EWSW[0]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n2910), .Q(
FPADDSUB_DMP_SHT1_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_0_ ( .D(FPADDSUB_DMP_SHT1_EWSW[0]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8160683), .RN(n2909), .Q(
FPADDSUB_DMP_SHT2_EWSW[0]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(
FPSENCOS_d_ff4_Xn_net8160917), .RN(n916), .Q(FPSENCOS_d_ff_Xn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_1_ ( .D(FPSENCOS_first_mux_X[1]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n916), .Q(
FPSENCOS_d_ff2_X[1]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_1_ ( .D(FPSENCOS_d_ff2_X[1]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n916), .Q(
FPSENCOS_d_ff3_sh_x_out[1]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(
FPSENCOS_d_ff4_Yn_net8160917), .RN(n916), .Q(FPSENCOS_d_ff_Yn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_1_ ( .D(FPSENCOS_first_mux_Y[1]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n916), .Q(
FPSENCOS_d_ff2_Y[1]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_1_ ( .D(FPSENCOS_d_ff2_Y[1]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n1728), .Q(
FPSENCOS_d_ff3_sh_y_out[1]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_1_ ( .D(FPSENCOS_mux_sal[1]), .CK(
FPSENCOS_d_ff5_data_out_net8160917), .RN(n1731), .Q(cordic_result[1])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(
FPSENCOS_d_ff4_Zn_net8160917), .RN(n1728), .Q(FPSENCOS_d_ff_Zn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_1_ ( .D(FPSENCOS_first_mux_Z[1]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n1731), .Q(
FPSENCOS_d_ff2_Z[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_1_ ( .D(FPADDSUB_DmP_INIT_EWSW[1]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2895), .Q(
FPADDSUB_DmP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(FPADDSUB_DmP_EXP_EWSW[1]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n2905), .Q(
FPADDSUB_DmP_mant_SHT1_SW[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_1_ ( .D(FPADDSUB_DMP_INIT_EWSW[1]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2897), .Q(
FPADDSUB_DMP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_1_ ( .D(FPADDSUB_DMP_EXP_EWSW[1]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n1734), .Q(
FPADDSUB_DMP_SHT1_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_1_ ( .D(FPADDSUB_DMP_SHT1_EWSW[1]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8160683), .RN(n2907), .Q(
FPADDSUB_DMP_SHT2_EWSW[1]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(
FPSENCOS_d_ff4_Xn_net8160917), .RN(n1728), .Q(FPSENCOS_d_ff_Xn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_3_ ( .D(FPSENCOS_first_mux_X[3]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n1731), .Q(
FPSENCOS_d_ff2_X[3]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_3_ ( .D(FPSENCOS_d_ff2_X[3]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n1728), .Q(
FPSENCOS_d_ff3_sh_x_out[3]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(
FPSENCOS_d_ff4_Yn_net8160917), .RN(n1728), .Q(FPSENCOS_d_ff_Yn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_3_ ( .D(FPSENCOS_first_mux_Y[3]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n1731), .Q(
FPSENCOS_d_ff2_Y[3]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_3_ ( .D(FPSENCOS_d_ff2_Y[3]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2925), .Q(
FPSENCOS_d_ff3_sh_y_out[3]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_3_ ( .D(FPSENCOS_mux_sal[3]), .CK(
FPSENCOS_d_ff5_data_out_net8160917), .RN(n918), .Q(cordic_result[3])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(
FPSENCOS_d_ff4_Zn_net8160917), .RN(n917), .Q(FPSENCOS_d_ff_Zn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_3_ ( .D(FPSENCOS_first_mux_Z[3]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2936), .Q(
FPSENCOS_d_ff2_Z[3]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_3_ ( .D(FPADDSUB_DmP_INIT_EWSW[3]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n914), .Q(
FPADDSUB_DmP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(FPADDSUB_DmP_EXP_EWSW[3]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n1831), .Q(
FPADDSUB_DmP_mant_SHT1_SW[3]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_3_ ( .D(FPADDSUB_DMP_INIT_EWSW[3]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2891), .Q(
FPADDSUB_DMP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_3_ ( .D(FPADDSUB_DMP_EXP_EWSW[3]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n914), .Q(
FPADDSUB_DMP_SHT1_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_3_ ( .D(FPADDSUB_DMP_SHT1_EWSW[3]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8160683), .RN(n2892), .Q(
FPADDSUB_DMP_SHT2_EWSW[3]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(
FPSENCOS_d_ff4_Xn_net8160917), .RN(n2936), .Q(FPSENCOS_d_ff_Xn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_6_ ( .D(FPSENCOS_first_mux_X[6]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2936), .Q(
FPSENCOS_d_ff2_X[6]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_6_ ( .D(FPSENCOS_d_ff2_X[6]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2936), .Q(
FPSENCOS_d_ff3_sh_x_out[6]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(
FPSENCOS_d_ff4_Yn_net8160917), .RN(n2936), .Q(FPSENCOS_d_ff_Yn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_6_ ( .D(FPSENCOS_first_mux_Y[6]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n918), .Q(
FPSENCOS_d_ff2_Y[6]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_6_ ( .D(FPSENCOS_d_ff2_Y[6]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n918), .Q(
FPSENCOS_d_ff3_sh_y_out[6]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_6_ ( .D(FPSENCOS_mux_sal[6]), .CK(
FPSENCOS_d_ff5_data_out_net8160917), .RN(n2936), .Q(cordic_result[6])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(
FPSENCOS_d_ff4_Zn_net8160917), .RN(n2936), .Q(FPSENCOS_d_ff_Zn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_6_ ( .D(FPSENCOS_first_mux_Z[6]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2936), .Q(
FPSENCOS_d_ff2_Z[6]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_6_ ( .D(FPADDSUB_DmP_INIT_EWSW[6]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2893), .Q(
FPADDSUB_DmP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(FPADDSUB_DmP_EXP_EWSW[6]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n2895), .Q(
FPADDSUB_DmP_mant_SHT1_SW[6]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_6_ ( .D(FPADDSUB_DMP_INIT_EWSW[6]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n1734), .Q(
FPADDSUB_DMP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_6_ ( .D(FPADDSUB_DMP_EXP_EWSW[6]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n2907), .Q(
FPADDSUB_DMP_SHT1_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_6_ ( .D(FPADDSUB_DMP_SHT1_EWSW[6]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8160683), .RN(n2891), .Q(
FPADDSUB_DMP_SHT2_EWSW[6]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(
FPSENCOS_d_ff4_Xn_net8160917), .RN(n2936), .Q(FPSENCOS_d_ff_Xn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_7_ ( .D(FPSENCOS_first_mux_X[7]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2936), .Q(
FPSENCOS_d_ff2_X[7]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_7_ ( .D(FPSENCOS_d_ff2_X[7]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2930), .Q(
FPSENCOS_d_ff3_sh_x_out[7]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(
FPSENCOS_d_ff4_Yn_net8160917), .RN(n2940), .Q(FPSENCOS_d_ff_Yn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_7_ ( .D(FPSENCOS_first_mux_Y[7]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n1733), .Q(
FPSENCOS_d_ff2_Y[7]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_7_ ( .D(FPSENCOS_d_ff2_Y[7]), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2931), .Q(
FPSENCOS_d_ff3_sh_y_out[7]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_7_ ( .D(FPSENCOS_mux_sal[7]), .CK(
FPSENCOS_d_ff5_data_out_net8160917), .RN(n2925), .Q(cordic_result[7])
);
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(
FPSENCOS_d_ff4_Zn_net8160917), .RN(n2930), .Q(FPSENCOS_d_ff_Zn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_7_ ( .D(FPSENCOS_first_mux_Z[7]),
.CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2941), .Q(
FPSENCOS_d_ff2_Z[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_7_ ( .D(FPADDSUB_DmP_INIT_EWSW[7]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2900), .Q(
FPADDSUB_DmP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(FPADDSUB_DmP_EXP_EWSW[7]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n1734), .Q(
FPADDSUB_DmP_mant_SHT1_SW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_7_ ( .D(FPADDSUB_DMP_INIT_EWSW[7]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2897), .Q(
FPADDSUB_DMP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_7_ ( .D(FPADDSUB_DMP_EXP_EWSW[7]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n2894), .Q(
FPADDSUB_DMP_SHT1_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_7_ ( .D(FPADDSUB_DMP_SHT1_EWSW[7]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8160683), .RN(n2901), .Q(
FPADDSUB_DMP_SHT2_EWSW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_9_ ( .D(FPADDSUB_DmP_INIT_EWSW[9]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2908), .Q(
FPADDSUB_DmP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(FPADDSUB_DmP_EXP_EWSW[9]), .CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n2904), .Q(
FPADDSUB_DmP_mant_SHT1_SW[9]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_9_ ( .D(FPADDSUB_DMP_INIT_EWSW[9]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2902), .Q(
FPADDSUB_DMP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_9_ ( .D(FPADDSUB_DMP_EXP_EWSW[9]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n2893), .Q(
FPADDSUB_DMP_SHT1_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_9_ ( .D(FPADDSUB_DMP_SHT1_EWSW[9]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8160683), .RN(n912), .Q(
FPADDSUB_DMP_SHT2_EWSW[9]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_12_ ( .D(FPADDSUB_DMP_INIT_EWSW[12]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2894), .Q(
FPADDSUB_DMP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_12_ ( .D(FPADDSUB_DMP_EXP_EWSW[12]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n2901), .Q(
FPADDSUB_DMP_SHT1_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_12_ ( .D(FPADDSUB_DMP_SHT1_EWSW[12]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8160683), .RN(n2898), .Q(
FPADDSUB_DMP_SHT2_EWSW[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_10_ ( .D(FPADDSUB_DMP_INIT_EWSW[10]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2903), .Q(
FPADDSUB_DMP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_10_ ( .D(FPADDSUB_DMP_EXP_EWSW[10]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n2910), .Q(
FPADDSUB_DMP_SHT1_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_10_ ( .D(FPADDSUB_DMP_SHT1_EWSW[10]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8160683), .RN(n2909), .Q(
FPADDSUB_DMP_SHT2_EWSW[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_8_ ( .D(FPADDSUB_DMP_INIT_EWSW[8]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2902), .Q(
FPADDSUB_DMP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_8_ ( .D(FPADDSUB_DMP_EXP_EWSW[8]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n2893), .Q(
FPADDSUB_DMP_SHT1_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_8_ ( .D(FPADDSUB_DMP_SHT1_EWSW[8]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8160683), .RN(n913), .Q(
FPADDSUB_DMP_SHT2_EWSW[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_11_ ( .D(FPADDSUB_DMP_INIT_EWSW[11]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n912), .Q(
FPADDSUB_DMP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_11_ ( .D(FPADDSUB_DMP_EXP_EWSW[11]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n2901), .Q(
FPADDSUB_DMP_SHT1_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_11_ ( .D(FPADDSUB_DMP_SHT1_EWSW[11]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8160683), .RN(n2903), .Q(
FPADDSUB_DMP_SHT2_EWSW[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_14_ ( .D(FPADDSUB_DMP_INIT_EWSW[14]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2898), .Q(
FPADDSUB_DMP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_14_ ( .D(FPADDSUB_DMP_EXP_EWSW[14]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n2910), .Q(
FPADDSUB_DMP_SHT1_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_14_ ( .D(FPADDSUB_DMP_SHT1_EWSW[14]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8160683), .RN(n2909), .Q(
FPADDSUB_DMP_SHT2_EWSW[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_13_ ( .D(FPADDSUB_DMP_INIT_EWSW[13]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2910), .Q(
FPADDSUB_DMP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_13_ ( .D(FPADDSUB_DMP_EXP_EWSW[13]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n2909), .Q(
FPADDSUB_DMP_SHT1_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_13_ ( .D(FPADDSUB_DMP_SHT1_EWSW[13]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8160683), .RN(n2902), .Q(
FPADDSUB_DMP_SHT2_EWSW[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_5_ ( .D(FPADDSUB_DMP_INIT_EWSW[5]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2893), .Q(
FPADDSUB_DMP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_5_ ( .D(FPADDSUB_DMP_EXP_EWSW[5]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n913), .Q(
FPADDSUB_DMP_SHT1_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_5_ ( .D(FPADDSUB_DMP_SHT1_EWSW[5]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8160683), .RN(n912), .Q(
FPADDSUB_DMP_SHT2_EWSW[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_15_ ( .D(FPADDSUB_DMP_INIT_EWSW[15]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2901), .Q(
FPADDSUB_DMP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_15_ ( .D(FPADDSUB_DMP_EXP_EWSW[15]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n912), .Q(
FPADDSUB_DMP_SHT1_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_15_ ( .D(FPADDSUB_DMP_SHT1_EWSW[15]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8160683), .RN(n2894), .Q(
FPADDSUB_DMP_SHT2_EWSW[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_4_ ( .D(FPADDSUB_DMP_INIT_EWSW[4]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2904), .Q(
FPADDSUB_DMP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_4_ ( .D(FPADDSUB_DMP_EXP_EWSW[4]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n2904), .Q(
FPADDSUB_DMP_SHT1_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_4_ ( .D(FPADDSUB_DMP_SHT1_EWSW[4]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8160683), .RN(n2904), .Q(
FPADDSUB_DMP_SHT2_EWSW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_17_ ( .D(FPADDSUB_DMP_INIT_EWSW[17]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2904), .Q(
FPADDSUB_DMP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_17_ ( .D(FPADDSUB_DMP_EXP_EWSW[17]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n2904), .Q(
FPADDSUB_DMP_SHT1_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_17_ ( .D(FPADDSUB_DMP_SHT1_EWSW[17]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8160683), .RN(n2904), .Q(
FPADDSUB_DMP_SHT2_EWSW[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_20_ ( .D(FPADDSUB_DMP_INIT_EWSW[20]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2904), .Q(
FPADDSUB_DMP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_20_ ( .D(FPADDSUB_DMP_EXP_EWSW[20]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n2904), .Q(
FPADDSUB_DMP_SHT1_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_20_ ( .D(FPADDSUB_DMP_SHT1_EWSW[20]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8160683), .RN(n2904), .Q(
FPADDSUB_DMP_SHT2_EWSW[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_18_ ( .D(FPADDSUB_DMP_INIT_EWSW[18]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n914), .Q(
FPADDSUB_DMP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_18_ ( .D(FPADDSUB_DMP_EXP_EWSW[18]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n1831), .Q(
FPADDSUB_DMP_SHT1_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_18_ ( .D(FPADDSUB_DMP_SHT1_EWSW[18]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8160683), .RN(n2900), .Q(
FPADDSUB_DMP_SHT2_EWSW[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_16_ ( .D(FPADDSUB_DMP_INIT_EWSW[16]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n1734), .Q(
FPADDSUB_DMP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_16_ ( .D(FPADDSUB_DMP_EXP_EWSW[16]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n2894), .Q(
FPADDSUB_DMP_SHT1_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_16_ ( .D(FPADDSUB_DMP_SHT1_EWSW[16]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8160683), .RN(n2901), .Q(
FPADDSUB_DMP_SHT2_EWSW[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_2_ ( .D(FPADDSUB_DMP_INIT_EWSW[2]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2905), .Q(
FPADDSUB_DMP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_2_ ( .D(FPADDSUB_DMP_EXP_EWSW[2]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n2904), .Q(
FPADDSUB_DMP_SHT1_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_2_ ( .D(FPADDSUB_DMP_SHT1_EWSW[2]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8160683), .RN(n2905), .Q(
FPADDSUB_DMP_SHT2_EWSW[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_21_ ( .D(FPADDSUB_DMP_INIT_EWSW[21]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2905), .Q(
FPADDSUB_DMP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_21_ ( .D(FPADDSUB_DMP_EXP_EWSW[21]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n2905), .Q(
FPADDSUB_DMP_SHT1_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_21_ ( .D(FPADDSUB_DMP_SHT1_EWSW[21]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8160683), .RN(n2905), .Q(
FPADDSUB_DMP_SHT2_EWSW[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_19_ ( .D(FPADDSUB_DMP_INIT_EWSW[19]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2905), .Q(
FPADDSUB_DMP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_19_ ( .D(FPADDSUB_DMP_EXP_EWSW[19]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n2905), .Q(
FPADDSUB_DMP_SHT1_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_19_ ( .D(FPADDSUB_DMP_SHT1_EWSW[19]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8160683), .RN(n2905), .Q(
FPADDSUB_DMP_SHT2_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_1_ ( .D(FPADDSUB_Data_array_SWR[1]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8160665), .RN(n2905), .Q(
FPADDSUB_Data_array_SWR[27]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_0_ ( .D(FPADDSUB_Data_array_SWR[0]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8160665), .RN(n2905), .Q(
FPADDSUB_Data_array_SWR[26]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_22_ ( .D(FPADDSUB_DMP_INIT_EWSW[22]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2902), .Q(
FPADDSUB_DMP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_22_ ( .D(FPADDSUB_DMP_EXP_EWSW[22]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n2893), .Q(
FPADDSUB_DMP_SHT1_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_22_ ( .D(FPADDSUB_DMP_SHT1_EWSW[22]),
.CK(FPADDSUB_SHT2_STAGE_DMP_net8160683), .RN(n913), .Q(
FPADDSUB_DMP_SHT2_EWSW[22]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[1]), .CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n912), .Q(FPADDSUB_N60) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[25]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2908), .QN(n957) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_47_ ( .D(
FPMULT_Sgf_operation_Result[47]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8160845), .RN(n2935), .Q(
FPMULT_P_Sgf[47]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_30_ ( .D(Data_2[30]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2917), .Q(
FPMULT_Op_MY[30]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_29_ ( .D(Data_2[29]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2918), .Q(
FPMULT_Op_MY[29]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_28_ ( .D(Data_2[28]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2914), .Q(
FPMULT_Op_MY[28]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_27_ ( .D(Data_2[27]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n915), .Q(
FPMULT_Op_MY[27]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_26_ ( .D(Data_2[26]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2912), .Q(
FPMULT_Op_MY[26]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_25_ ( .D(Data_2[25]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2914), .Q(
FPMULT_Op_MY[25]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_24_ ( .D(Data_2[24]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2912), .Q(
FPMULT_Op_MY[24]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_23_ ( .D(Data_2[23]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2913), .Q(
FPMULT_Op_MY[23]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_16_ ( .D(Data_2[16]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n915), .QN(
n936) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_14_ ( .D(Data_2[14]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2917), .QN(
n932) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_10_ ( .D(Data_2[10]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2918), .QN(
n935) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_9_ ( .D(Data_2[9]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n961), .QN(n933)
);
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_7_ ( .D(Data_2[7]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2913), .QN(n920)
);
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_6_ ( .D(Data_2[6]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2916), .QN(n931)
);
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_27_ ( .D(Data_1[27]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2917), .Q(
FPMULT_Op_MX[27]) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_26_ ( .D(Data_1[26]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n961), .Q(
FPMULT_Op_MX[26]) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_22_ ( .D(Data_1[22]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2918), .QN(
n941) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_20_ ( .D(Data_1[20]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2915), .QN(
n937) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_14_ ( .D(Data_1[14]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2917), .Q(
FPMULT_Op_MX[14]), .QN(n940) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_9_ ( .D(Data_1[9]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2912), .QN(n921)
);
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_5_ ( .D(Data_1[5]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2913), .QN(n934)
);
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_4_ ( .D(Data_1[4]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2918), .QN(n922)
);
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_3_ ( .D(Data_1[3]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2914), .QN(n919)
);
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_2_ ( .D(Data_1[2]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2912), .QN(n930)
);
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_1_ ( .D(Data_1[1]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2913), .QN(n929)
);
DFFRXLTS FPMULT_Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n106), .CK(
n2963), .RN(n2915), .QN(n997) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n2775), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8160809), .RN(n2913), .Q(
FPMULT_Add_result[0]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_25_ ( .D(
FPMULT_Sgf_operation_Result[25]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8160845), .RN(n918), .QN(n956)
);
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_23_ ( .D(
FPMULT_Sgf_operation_Result[23]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8160845), .RN(n2943), .Q(
FPMULT_P_Sgf[23]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_8_ ( .D(
FPMULT_Exp_module_Data_S[8]), .CK(
FPMULT_Exp_module_exp_result_m_net8160863), .RN(n2914), .Q(
FPMULT_exp_oper_result[8]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_7_ ( .D(
FPMULT_Exp_module_Data_S[7]), .CK(
FPMULT_Exp_module_exp_result_m_net8160863), .RN(n2912), .Q(
FPMULT_exp_oper_result[7]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_6_ ( .D(
FPMULT_Exp_module_Data_S[6]), .CK(
FPMULT_Exp_module_exp_result_m_net8160863), .RN(n2913), .Q(
FPMULT_exp_oper_result[6]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_5_ ( .D(
FPMULT_Exp_module_Data_S[5]), .CK(
FPMULT_Exp_module_exp_result_m_net8160863), .RN(n2916), .Q(
FPMULT_exp_oper_result[5]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_4_ ( .D(
FPMULT_Exp_module_Data_S[4]), .CK(
FPMULT_Exp_module_exp_result_m_net8160863), .RN(n915), .Q(
FPMULT_exp_oper_result[4]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_3_ ( .D(
FPMULT_Exp_module_Data_S[3]), .CK(
FPMULT_Exp_module_exp_result_m_net8160863), .RN(n2911), .Q(
FPMULT_exp_oper_result[3]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_2_ ( .D(
FPMULT_Exp_module_Data_S[2]), .CK(
FPMULT_Exp_module_exp_result_m_net8160863), .RN(n961), .Q(
FPMULT_exp_oper_result[2]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_1_ ( .D(
FPMULT_Exp_module_Data_S[1]), .CK(
FPMULT_Exp_module_exp_result_m_net8160863), .RN(n2919), .Q(
FPMULT_exp_oper_result[1]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_0_ ( .D(
FPMULT_Exp_module_Data_S[0]), .CK(
FPMULT_Exp_module_exp_result_m_net8160863), .RN(n915), .Q(
FPMULT_exp_oper_result[0]) );
DFFRXLTS FPMULT_Exp_module_Oflow_A_m_Q_reg_0_ ( .D(
FPMULT_Exp_module_Overflow_A), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8160845), .RN(n2915), .Q(
FPMULT_Exp_module_Overflow_flag_A) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n2990), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8160827), .RN(n2918), .Q(
FPMULT_Sgf_normalized_result[23]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n2988), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8160827), .RN(n2916), .Q(
FPMULT_Sgf_normalized_result[21]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n2986), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8160827), .RN(n915), .Q(
FPMULT_Sgf_normalized_result[19]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n2984), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8160827), .RN(n2911), .Q(
FPMULT_Sgf_normalized_result[17]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n2982), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8160827), .RN(n2915), .Q(
FPMULT_Sgf_normalized_result[15]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n2980), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8160827), .RN(n2917), .Q(
FPMULT_Sgf_normalized_result[13]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n2978), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8160827), .RN(n961), .Q(
FPMULT_Sgf_normalized_result[11]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n2976), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8160827), .RN(n2919), .Q(
FPMULT_Sgf_normalized_result[9]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n2974), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8160827), .RN(n915), .Q(
FPMULT_Sgf_normalized_result[7]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n2972), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8160827), .RN(n2918), .Q(
FPMULT_Sgf_normalized_result[5]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n2970), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8160827), .RN(n2915), .Q(
FPMULT_Sgf_normalized_result[3]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[0]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8160629), .RN(
n2917), .Q(mult_result[0]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[1]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8160629), .RN(
n2917), .Q(mult_result[1]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[2]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8160629), .RN(
n2914), .Q(mult_result[2]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[3]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8160629), .RN(
n2912), .Q(mult_result[3]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[4]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8160629), .RN(
n2913), .Q(mult_result[4]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[5]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8160629), .RN(
n2916), .Q(mult_result[5]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[6]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8160629), .RN(
n915), .Q(mult_result[6]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[7]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8160629), .RN(
n2911), .Q(mult_result[7]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[8]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8160629), .RN(
n2915), .Q(mult_result[8]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[9]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8160629), .RN(
n2917), .Q(mult_result[9]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[10]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8160629), .RN(
n961), .Q(mult_result[10]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[11]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8160629), .RN(
n2919), .Q(mult_result[11]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[12]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8160629), .RN(
n915), .Q(mult_result[12]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[13]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8160629), .RN(
n2923), .Q(mult_result[13]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[14]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8160629), .RN(
n2923), .Q(mult_result[14]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[15]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8160629), .RN(
n2923), .Q(mult_result[15]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[16]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8160629), .RN(
n2923), .Q(mult_result[16]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[17]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8160629), .RN(
n2923), .Q(mult_result[17]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[18]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8160629), .RN(
n2923), .Q(mult_result[18]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[19]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8160629), .RN(
n2923), .Q(mult_result[19]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[20]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8160629), .RN(
n2923), .Q(mult_result[20]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[21]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8160629), .RN(
n961), .Q(mult_result[21]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[22]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8160629), .RN(
n2915), .Q(mult_result[22]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[0]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8160629), .RN(
n2917), .Q(mult_result[23]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[1]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8160629), .RN(
n2918), .Q(mult_result[24]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[2]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8160629), .RN(
n2916), .Q(mult_result[25]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[3]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8160629), .RN(
n915), .Q(mult_result[26]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[4]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8160629), .RN(
n2911), .Q(mult_result[27]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[5]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8160629), .RN(
n961), .Q(mult_result[28]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[6]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8160629), .RN(
n2919), .Q(mult_result[29]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[7]), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8160629), .RN(
n915), .Q(mult_result[30]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(
FPMULT_final_result_ieee_Module_Sign_S_mux), .CK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net8160629), .RN(
n2915), .Q(mult_result[31]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n2958), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8160629), .RN(n913), .Q(
underflow_flag_addsubt) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n2959), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8160629), .RN(n913), .Q(
overflow_flag_addsubt) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n2957), .CK(
FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2908), .Q(
FPADDSUB_SIGN_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(FPADDSUB_SIGN_FLAG_EXP),
.CK(FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n2908), .Q(
FPADDSUB_SIGN_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n819), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8160665), .RN(n2908), .Q(
FPADDSUB_SIGN_FLAG_SHT2) );
DFFRXLTS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_2_ ( .D(FPADDSUB_SIGN_FLAG_SHT2),
.CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2908), .Q(
FPADDSUB_SIGN_FLAG_SFG) );
DFFRXLTS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_1_ ( .D(FPADDSUB_SIGN_FLAG_SFG),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8160665), .RN(n2908), .Q(
FPADDSUB_SIGN_FLAG_NRM) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n816), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8160665), .RN(n912), .Q(
FPADDSUB_SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n30), .CK(
FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2908), .Q(
FPADDSUB_OP_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(FPADDSUB_OP_FLAG_EXP), .CK(
FPADDSUB_SHT1_STAGE_DMP_net8160683), .RN(n2902), .Q(
FPADDSUB_OP_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n813), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8160665), .RN(n2893), .Q(
FPADDSUB_OP_FLAG_SHT2) );
SNPS_CLOCK_GATE_HIGH_FPU_Interface2_W32_EW8_SW23_SWR26_EWR5_1 clk_gate_FPMULT_Exp_module_Underflow_m_Q_reg (
.CLK(clk), .EN(n107), .ENCLK(n2963), .TE(1'b0) );
CMPR42X1TS DP_OP_496J314_122_3540_U283 ( .A(DP_OP_496J314_122_3540_n394),
.B(DP_OP_496J314_122_3540_n414), .C(DP_OP_496J314_122_3540_n407), .D(
DP_OP_496J314_122_3540_n400), .ICI(DP_OP_496J314_122_3540_n380), .S(
DP_OP_496J314_122_3540_n377), .ICO(DP_OP_496J314_122_3540_n375), .CO(
DP_OP_496J314_122_3540_n376) );
CMPR42X1TS DP_OP_496J314_122_3540_U282 ( .A(DP_OP_496J314_122_3540_n413),
.B(DP_OP_496J314_122_3540_n393), .C(DP_OP_496J314_122_3540_n399), .D(
DP_OP_496J314_122_3540_n406), .ICI(DP_OP_496J314_122_3540_n375), .S(
DP_OP_496J314_122_3540_n374), .ICO(DP_OP_496J314_122_3540_n372), .CO(
DP_OP_496J314_122_3540_n373) );
CMPR42X1TS DP_OP_496J314_122_3540_U280 ( .A(DP_OP_496J314_122_3540_n405),
.B(DP_OP_496J314_122_3540_n398), .C(DP_OP_496J314_122_3540_n412), .D(
DP_OP_496J314_122_3540_n371), .ICI(DP_OP_496J314_122_3540_n372), .S(
DP_OP_496J314_122_3540_n369), .ICO(DP_OP_496J314_122_3540_n367), .CO(
DP_OP_496J314_122_3540_n368) );
CMPR42X1TS DP_OP_496J314_122_3540_U278 ( .A(DP_OP_496J314_122_3540_n404),
.B(DP_OP_496J314_122_3540_n370), .C(DP_OP_496J314_122_3540_n397), .D(
DP_OP_496J314_122_3540_n366), .ICI(DP_OP_496J314_122_3540_n367), .S(
DP_OP_496J314_122_3540_n364), .ICO(DP_OP_496J314_122_3540_n362), .CO(
DP_OP_496J314_122_3540_n363) );
CMPR42X1TS DP_OP_496J314_122_3540_U277 ( .A(DP_OP_496J314_122_3540_n365),
.B(DP_OP_496J314_122_3540_n396), .C(DP_OP_496J314_122_3540_n392), .D(
DP_OP_496J314_122_3540_n403), .ICI(DP_OP_496J314_122_3540_n362), .S(
DP_OP_496J314_122_3540_n361), .ICO(DP_OP_496J314_122_3540_n359), .CO(
DP_OP_496J314_122_3540_n360) );
CMPR42X1TS DP_OP_496J314_122_3540_U192 ( .A(DP_OP_496J314_122_3540_n306),
.B(DP_OP_496J314_122_3540_n296), .C(DP_OP_496J314_122_3540_n274), .D(
DP_OP_496J314_122_3540_n273), .ICI(DP_OP_496J314_122_3540_n311), .S(
DP_OP_496J314_122_3540_n271), .ICO(DP_OP_496J314_122_3540_n269), .CO(
DP_OP_496J314_122_3540_n270) );
CMPR42X1TS DP_OP_496J314_122_3540_U189 ( .A(DP_OP_496J314_122_3540_n268),
.B(DP_OP_496J314_122_3540_n305), .C(DP_OP_496J314_122_3540_n290), .D(
DP_OP_496J314_122_3540_n266), .ICI(DP_OP_496J314_122_3540_n269), .S(
DP_OP_496J314_122_3540_n264), .ICO(DP_OP_496J314_122_3540_n262), .CO(
DP_OP_496J314_122_3540_n263) );
CMPR42X1TS DP_OP_496J314_122_3540_U186 ( .A(DP_OP_496J314_122_3540_n289),
.B(DP_OP_496J314_122_3540_n265), .C(DP_OP_496J314_122_3540_n261), .D(
DP_OP_496J314_122_3540_n262), .ICI(DP_OP_496J314_122_3540_n259), .S(
DP_OP_496J314_122_3540_n257), .ICO(DP_OP_496J314_122_3540_n255), .CO(
DP_OP_496J314_122_3540_n256) );
CMPR42X1TS DP_OP_496J314_122_3540_U184 ( .A(DP_OP_496J314_122_3540_n293),
.B(DP_OP_496J314_122_3540_n288), .C(DP_OP_496J314_122_3540_n254), .D(
DP_OP_496J314_122_3540_n258), .ICI(DP_OP_496J314_122_3540_n255), .S(
DP_OP_496J314_122_3540_n252), .ICO(DP_OP_496J314_122_3540_n250), .CO(
DP_OP_496J314_122_3540_n251) );
CMPR42X1TS DP_OP_496J314_122_3540_U183 ( .A(DP_OP_496J314_122_3540_n292),
.B(DP_OP_496J314_122_3540_n282), .C(DP_OP_496J314_122_3540_n287), .D(
DP_OP_496J314_122_3540_n253), .ICI(DP_OP_496J314_122_3540_n250), .S(
DP_OP_496J314_122_3540_n249), .ICO(DP_OP_496J314_122_3540_n247), .CO(
DP_OP_496J314_122_3540_n248) );
CMPR42X1TS DP_OP_496J314_122_3540_U63 ( .A(DP_OP_496J314_122_3540_n234), .B(
DP_OP_496J314_122_3540_n205), .C(DP_OP_496J314_122_3540_n191), .D(
DP_OP_496J314_122_3540_n128), .ICI(DP_OP_496J314_122_3540_n127), .S(
DP_OP_496J314_122_3540_n125), .ICO(DP_OP_496J314_122_3540_n123), .CO(
DP_OP_496J314_122_3540_n124) );
CMPR42X1TS DP_OP_496J314_122_3540_U60 ( .A(DP_OP_496J314_122_3540_n204), .B(
DP_OP_496J314_122_3540_n183), .C(DP_OP_496J314_122_3540_n122), .D(
DP_OP_496J314_122_3540_n120), .ICI(DP_OP_496J314_122_3540_n124), .S(
DP_OP_496J314_122_3540_n118), .ICO(DP_OP_496J314_122_3540_n116), .CO(
DP_OP_496J314_122_3540_n117) );
CMPR42X1TS DP_OP_496J314_122_3540_U58 ( .A(DP_OP_496J314_122_3540_n121), .B(
DP_OP_496J314_122_3540_n182), .C(DP_OP_496J314_122_3540_n196), .D(
DP_OP_496J314_122_3540_n115), .ICI(DP_OP_496J314_122_3540_n116), .S(
DP_OP_496J314_122_3540_n113), .ICO(DP_OP_496J314_122_3540_n111), .CO(
DP_OP_496J314_122_3540_n112) );
CMPR42X1TS DP_OP_496J314_122_3540_U57 ( .A(DP_OP_496J314_122_3540_n119), .B(
DP_OP_496J314_122_3540_n175), .C(DP_OP_496J314_122_3540_n203), .D(
DP_OP_496J314_122_3540_n113), .ICI(DP_OP_496J314_122_3540_n117), .S(
DP_OP_496J314_122_3540_n110), .ICO(DP_OP_496J314_122_3540_n108), .CO(
DP_OP_496J314_122_3540_n109) );
CMPR42X1TS DP_OP_496J314_122_3540_U54 ( .A(DP_OP_496J314_122_3540_n107), .B(
DP_OP_496J314_122_3540_n195), .C(DP_OP_496J314_122_3540_n174), .D(
DP_OP_496J314_122_3540_n105), .ICI(DP_OP_496J314_122_3540_n202), .S(
DP_OP_496J314_122_3540_n103), .ICO(DP_OP_496J314_122_3540_n101), .CO(
DP_OP_496J314_122_3540_n102) );
CMPR42X1TS DP_OP_496J314_122_3540_U53 ( .A(DP_OP_496J314_122_3540_n112), .B(
DP_OP_496J314_122_3540_n108), .C(DP_OP_496J314_122_3540_n167), .D(
DP_OP_496J314_122_3540_n103), .ICI(DP_OP_496J314_122_3540_n109), .S(
DP_OP_496J314_122_3540_n100), .ICO(DP_OP_496J314_122_3540_n98), .CO(
DP_OP_496J314_122_3540_n99) );
CMPR42X1TS DP_OP_496J314_122_3540_U51 ( .A(DP_OP_496J314_122_3540_n106), .B(
DP_OP_496J314_122_3540_n97), .C(DP_OP_496J314_122_3540_n173), .D(
DP_OP_496J314_122_3540_n187), .ICI(DP_OP_496J314_122_3540_n104), .S(
DP_OP_496J314_122_3540_n95), .ICO(DP_OP_496J314_122_3540_n93), .CO(
DP_OP_496J314_122_3540_n94) );
CMPR42X1TS DP_OP_496J314_122_3540_U50 ( .A(DP_OP_496J314_122_3540_n101), .B(
DP_OP_496J314_122_3540_n166), .C(DP_OP_496J314_122_3540_n194), .D(
DP_OP_496J314_122_3540_n98), .ICI(DP_OP_496J314_122_3540_n95), .S(
DP_OP_496J314_122_3540_n92), .ICO(DP_OP_496J314_122_3540_n90), .CO(
DP_OP_496J314_122_3540_n91) );
CMPR42X1TS DP_OP_496J314_122_3540_U49 ( .A(DP_OP_496J314_122_3540_n201), .B(
DP_OP_496J314_122_3540_n159), .C(DP_OP_496J314_122_3540_n102), .D(
DP_OP_496J314_122_3540_n229), .ICI(DP_OP_496J314_122_3540_n92), .S(
DP_OP_496J314_122_3540_n89), .ICO(DP_OP_496J314_122_3540_n87), .CO(
DP_OP_496J314_122_3540_n88) );
CMPR42X1TS DP_OP_496J314_122_3540_U46 ( .A(DP_OP_496J314_122_3540_n93), .B(
DP_OP_496J314_122_3540_n165), .C(DP_OP_496J314_122_3540_n186), .D(
DP_OP_496J314_122_3540_n151), .ICI(DP_OP_496J314_122_3540_n158), .S(
DP_OP_496J314_122_3540_n82), .ICO(DP_OP_496J314_122_3540_n80), .CO(
DP_OP_496J314_122_3540_n81) );
CMPR42X1TS DP_OP_496J314_122_3540_U45 ( .A(DP_OP_496J314_122_3540_n200), .B(
DP_OP_496J314_122_3540_n90), .C(DP_OP_496J314_122_3540_n94), .D(
DP_OP_496J314_122_3540_n193), .ICI(DP_OP_496J314_122_3540_n87), .S(
DP_OP_496J314_122_3540_n79), .ICO(DP_OP_496J314_122_3540_n77), .CO(
DP_OP_496J314_122_3540_n78) );
CMPR42X1TS DP_OP_496J314_122_3540_U44 ( .A(DP_OP_496J314_122_3540_n84), .B(
DP_OP_496J314_122_3540_n91), .C(DP_OP_496J314_122_3540_n82), .D(
DP_OP_496J314_122_3540_n79), .ICI(DP_OP_496J314_122_3540_n228), .S(
DP_OP_496J314_122_3540_n76), .ICO(DP_OP_496J314_122_3540_n74), .CO(
DP_OP_496J314_122_3540_n75) );
CMPR42X1TS DP_OP_496J314_122_3540_U41 ( .A(DP_OP_496J314_122_3540_n73), .B(
DP_OP_496J314_122_3540_n83), .C(DP_OP_496J314_122_3540_n192), .D(
DP_OP_496J314_122_3540_n150), .ICI(DP_OP_496J314_122_3540_n71), .S(
DP_OP_496J314_122_3540_n69), .ICO(DP_OP_496J314_122_3540_n67), .CO(
DP_OP_496J314_122_3540_n68) );
CMPR42X1TS DP_OP_496J314_122_3540_U40 ( .A(DP_OP_496J314_122_3540_n80), .B(
DP_OP_496J314_122_3540_n185), .C(DP_OP_496J314_122_3540_n157), .D(
DP_OP_496J314_122_3540_n77), .ICI(DP_OP_496J314_122_3540_n81), .S(
DP_OP_496J314_122_3540_n66), .ICO(DP_OP_496J314_122_3540_n64), .CO(
DP_OP_496J314_122_3540_n65) );
CMPR42X1TS DP_OP_496J314_122_3540_U39 ( .A(DP_OP_496J314_122_3540_n78), .B(
DP_OP_496J314_122_3540_n69), .C(DP_OP_496J314_122_3540_n74), .D(
DP_OP_496J314_122_3540_n66), .ICI(DP_OP_496J314_122_3540_n227), .S(
DP_OP_496J314_122_3540_n63), .ICO(DP_OP_496J314_122_3540_n61), .CO(
DP_OP_496J314_122_3540_n62) );
CMPR42X1TS DP_OP_496J314_122_3540_U37 ( .A(DP_OP_496J314_122_3540_n72), .B(
DP_OP_496J314_122_3540_n149), .C(DP_OP_496J314_122_3540_n184), .D(
DP_OP_496J314_122_3540_n156), .ICI(DP_OP_496J314_122_3540_n60), .S(
DP_OP_496J314_122_3540_n58), .ICO(DP_OP_496J314_122_3540_n56), .CO(
DP_OP_496J314_122_3540_n57) );
CMPR42X1TS DP_OP_496J314_122_3540_U36 ( .A(DP_OP_496J314_122_3540_n177), .B(
DP_OP_496J314_122_3540_n70), .C(DP_OP_496J314_122_3540_n67), .D(
DP_OP_496J314_122_3540_n64), .ICI(DP_OP_496J314_122_3540_n68), .S(
DP_OP_496J314_122_3540_n55), .ICO(DP_OP_496J314_122_3540_n53), .CO(
DP_OP_496J314_122_3540_n54) );
CMPR42X1TS DP_OP_496J314_122_3540_U35 ( .A(DP_OP_496J314_122_3540_n58), .B(
DP_OP_496J314_122_3540_n65), .C(DP_OP_496J314_122_3540_n55), .D(
DP_OP_496J314_122_3540_n61), .ICI(DP_OP_496J314_122_3540_n62), .S(
DP_OP_496J314_122_3540_n52), .ICO(DP_OP_496J314_122_3540_n50), .CO(
DP_OP_496J314_122_3540_n51) );
CMPR42X1TS DP_OP_496J314_122_3540_U34 ( .A(DP_OP_496J314_122_3540_n133), .B(
DP_OP_496J314_122_3540_n162), .C(DP_OP_496J314_122_3540_n148), .D(
DP_OP_496J314_122_3540_n176), .ICI(DP_OP_496J314_122_3540_n155), .S(
DP_OP_496J314_122_3540_n49), .ICO(DP_OP_496J314_122_3540_n47), .CO(
DP_OP_496J314_122_3540_n48) );
CMPR42X1TS DP_OP_496J314_122_3540_U33 ( .A(DP_OP_496J314_122_3540_n169), .B(
DP_OP_496J314_122_3540_n59), .C(DP_OP_496J314_122_3540_n56), .D(
DP_OP_496J314_122_3540_n53), .ICI(DP_OP_496J314_122_3540_n57), .S(
DP_OP_496J314_122_3540_n46), .ICO(DP_OP_496J314_122_3540_n44), .CO(
DP_OP_496J314_122_3540_n45) );
CMPR42X1TS DP_OP_496J314_122_3540_U32 ( .A(DP_OP_496J314_122_3540_n49), .B(
DP_OP_496J314_122_3540_n54), .C(DP_OP_496J314_122_3540_n46), .D(
DP_OP_496J314_122_3540_n50), .ICI(DP_OP_496J314_122_3540_n51), .S(
DP_OP_496J314_122_3540_n43), .ICO(DP_OP_496J314_122_3540_n41), .CO(
DP_OP_496J314_122_3540_n42) );
CMPR42X1TS DP_OP_496J314_122_3540_U30 ( .A(DP_OP_496J314_122_3540_n161), .B(
DP_OP_496J314_122_3540_n154), .C(DP_OP_496J314_122_3540_n47), .D(
DP_OP_496J314_122_3540_n40), .ICI(DP_OP_496J314_122_3540_n44), .S(
DP_OP_496J314_122_3540_n38), .ICO(DP_OP_496J314_122_3540_n36), .CO(
DP_OP_496J314_122_3540_n37) );
CMPR42X1TS DP_OP_496J314_122_3540_U29 ( .A(DP_OP_496J314_122_3540_n48), .B(
DP_OP_496J314_122_3540_n38), .C(DP_OP_496J314_122_3540_n45), .D(
DP_OP_496J314_122_3540_n41), .ICI(DP_OP_496J314_122_3540_n224), .S(
DP_OP_496J314_122_3540_n35), .ICO(DP_OP_496J314_122_3540_n33), .CO(
DP_OP_496J314_122_3540_n34) );
CMPR42X1TS DP_OP_496J314_122_3540_U25 ( .A(DP_OP_496J314_122_3540_n36), .B(
DP_OP_496J314_122_3540_n32), .C(DP_OP_496J314_122_3540_n30), .D(
DP_OP_496J314_122_3540_n37), .ICI(DP_OP_496J314_122_3540_n33), .S(
DP_OP_496J314_122_3540_n28), .ICO(DP_OP_496J314_122_3540_n26), .CO(
DP_OP_496J314_122_3540_n27) );
CMPR42X1TS DP_OP_496J314_122_3540_U22 ( .A(DP_OP_496J314_122_3540_n145), .B(
DP_OP_496J314_122_3540_n31), .C(DP_OP_496J314_122_3540_n29), .D(
DP_OP_496J314_122_3540_n25), .ICI(DP_OP_496J314_122_3540_n26), .S(
DP_OP_496J314_122_3540_n23), .ICO(DP_OP_496J314_122_3540_n21), .CO(
DP_OP_496J314_122_3540_n22) );
CMPR32X2TS DP_OP_26J314_126_1325_U9 ( .A(FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
n962), .C(DP_OP_26J314_126_1325_n18), .CO(DP_OP_26J314_126_1325_n8),
.S(FPADDSUB_exp_rslt_NRM2_EW1[0]) );
CMPR32X2TS DP_OP_26J314_126_1325_U8 ( .A(DP_OP_26J314_126_1325_n17), .B(
FPADDSUB_DMP_exp_NRM2_EW[1]), .C(DP_OP_26J314_126_1325_n8), .CO(
DP_OP_26J314_126_1325_n7), .S(FPADDSUB_exp_rslt_NRM2_EW1[1]) );
CMPR32X2TS DP_OP_26J314_126_1325_U7 ( .A(DP_OP_26J314_126_1325_n16), .B(
FPADDSUB_DMP_exp_NRM2_EW[2]), .C(DP_OP_26J314_126_1325_n7), .CO(
DP_OP_26J314_126_1325_n6), .S(FPADDSUB_exp_rslt_NRM2_EW1[2]) );
CMPR32X2TS DP_OP_26J314_126_1325_U6 ( .A(DP_OP_26J314_126_1325_n15), .B(
FPADDSUB_DMP_exp_NRM2_EW[3]), .C(DP_OP_26J314_126_1325_n6), .CO(
DP_OP_26J314_126_1325_n5), .S(FPADDSUB_exp_rslt_NRM2_EW1[3]) );
CMPR32X2TS intadd_1058_U8 ( .A(DP_OP_496J314_122_3540_n271), .B(
intadd_1058_B_2_), .C(intadd_1058_n8), .CO(intadd_1058_n7), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]) );
CMPR32X2TS intadd_1058_U7 ( .A(DP_OP_496J314_122_3540_n270), .B(
DP_OP_496J314_122_3540_n264), .C(intadd_1058_n7), .CO(intadd_1058_n6),
.S(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]) );
CMPR32X2TS intadd_1058_U6 ( .A(DP_OP_496J314_122_3540_n263), .B(
DP_OP_496J314_122_3540_n257), .C(intadd_1058_n6), .CO(intadd_1058_n5),
.S(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]) );
CMPR32X2TS intadd_1058_U5 ( .A(DP_OP_496J314_122_3540_n256), .B(
DP_OP_496J314_122_3540_n252), .C(intadd_1058_n5), .CO(intadd_1058_n4),
.S(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]) );
CMPR32X2TS intadd_1058_U4 ( .A(DP_OP_496J314_122_3540_n251), .B(
DP_OP_496J314_122_3540_n249), .C(intadd_1058_n4), .CO(intadd_1058_n3),
.S(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]) );
CMPR32X2TS intadd_1058_U3 ( .A(DP_OP_496J314_122_3540_n248), .B(
intadd_1058_B_7_), .C(intadd_1058_n3), .CO(intadd_1058_n2), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]) );
CMPR32X2TS intadd_1058_U2 ( .A(intadd_1058_A_8_), .B(intadd_1058_B_8_), .C(
intadd_1058_n2), .CO(intadd_1058_n1), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[10]) );
CMPR32X2TS intadd_1059_U6 ( .A(intadd_1059_A_0_), .B(intadd_1059_B_0_), .C(
intadd_1059_CI), .CO(intadd_1059_n5), .S(intadd_1059_SUM_0_) );
CMPR32X2TS intadd_1059_U5 ( .A(intadd_1059_A_1_), .B(intadd_1059_B_1_), .C(
intadd_1059_n5), .CO(intadd_1059_n4), .S(intadd_1059_SUM_1_) );
CMPR32X2TS intadd_1059_U4 ( .A(intadd_1059_A_2_), .B(intadd_1059_B_2_), .C(
intadd_1059_n4), .CO(intadd_1059_n3), .S(intadd_1059_SUM_2_) );
CMPR32X2TS intadd_1059_U3 ( .A(intadd_1059_A_3_), .B(intadd_1059_B_3_), .C(
intadd_1059_n3), .CO(intadd_1059_n2), .S(intadd_1059_SUM_3_) );
CMPR32X2TS intadd_1059_U2 ( .A(intadd_1059_A_4_), .B(intadd_1059_B_4_), .C(
intadd_1059_n2), .CO(intadd_1059_n1), .S(intadd_1059_SUM_4_) );
CMPR32X2TS intadd_1060_U6 ( .A(intadd_1057_SUM_0_), .B(intadd_1060_B_0_),
.C(intadd_1057_SUM_7_), .CO(intadd_1060_n5), .S(intadd_1060_SUM_0_) );
CMPR32X2TS intadd_1060_U5 ( .A(intadd_1057_SUM_1_), .B(intadd_1057_SUM_8_),
.C(intadd_1060_n5), .CO(intadd_1060_n4), .S(intadd_1060_SUM_1_) );
CMPR32X2TS intadd_1060_U4 ( .A(intadd_1057_SUM_2_), .B(intadd_1057_SUM_9_),
.C(intadd_1060_n4), .CO(intadd_1060_n3), .S(intadd_1060_SUM_2_) );
CMPR32X2TS intadd_1060_U3 ( .A(intadd_1057_SUM_3_), .B(intadd_1060_B_3_),
.C(intadd_1060_n3), .CO(intadd_1060_n2), .S(intadd_1060_SUM_3_) );
CMPR32X2TS intadd_1062_U4 ( .A(n2800), .B(FPSENCOS_d_ff2_Y[24]), .C(
intadd_1062_CI), .CO(intadd_1062_n3), .S(FPSENCOS_sh_exp_y[1]) );
CMPR32X2TS intadd_1063_U4 ( .A(FPADDSUB_DmP_EXP_EWSW[24]), .B(n2861), .C(
intadd_1063_CI), .CO(intadd_1063_n3), .S(intadd_1063_SUM_0_) );
CMPR32X2TS intadd_1063_U3 ( .A(FPADDSUB_DmP_EXP_EWSW[25]), .B(n2860), .C(
intadd_1063_n3), .CO(intadd_1063_n2), .S(intadd_1063_SUM_1_) );
CMPR32X2TS intadd_1063_U2 ( .A(FPADDSUB_DmP_EXP_EWSW[26]), .B(n2876), .C(
intadd_1063_n2), .CO(intadd_1063_n1), .S(intadd_1063_SUM_2_) );
CMPR32X2TS intadd_1054_U15 ( .A(DP_OP_496J314_122_3540_n234), .B(
intadd_1054_B_0_), .C(intadd_1054_CI), .CO(intadd_1054_n14), .S(
intadd_1054_SUM_0_) );
CMPR32X2TS intadd_1054_U14 ( .A(intadd_1054_A_1_), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]), .C(
intadd_1054_n14), .CO(intadd_1054_n13), .S(intadd_1054_SUM_1_) );
CMPR32X2TS intadd_1054_U13 ( .A(intadd_1054_A_2_), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]), .C(
intadd_1054_n13), .CO(intadd_1054_n12), .S(intadd_1054_SUM_2_) );
CMPR32X2TS intadd_1054_U12 ( .A(intadd_1054_A_3_), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]), .C(
intadd_1054_n12), .CO(intadd_1054_n11), .S(intadd_1054_SUM_3_) );
CMPR32X2TS intadd_1054_U11 ( .A(intadd_1054_A_4_), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]), .C(
intadd_1054_n11), .CO(intadd_1054_n10), .S(intadd_1054_SUM_4_) );
CMPR32X2TS intadd_1054_U10 ( .A(intadd_1054_A_5_), .B(intadd_1054_B_5_), .C(
intadd_1054_n10), .CO(intadd_1054_n9), .S(intadd_1054_SUM_5_) );
CMPR32X2TS intadd_1054_U9 ( .A(intadd_1054_A_6_), .B(intadd_1054_B_6_), .C(
intadd_1054_n9), .CO(intadd_1054_n8), .S(intadd_1054_SUM_6_) );
CMPR32X2TS intadd_1054_U8 ( .A(intadd_1054_A_7_), .B(intadd_1054_B_7_), .C(
intadd_1054_n8), .CO(intadd_1054_n7), .S(intadd_1054_SUM_7_) );
CMPR32X2TS intadd_1054_U7 ( .A(intadd_1054_A_8_), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]), .C(
intadd_1054_n7), .CO(intadd_1054_n6), .S(intadd_1054_SUM_8_) );
CMPR32X2TS intadd_1054_U6 ( .A(intadd_1054_A_9_), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[10]), .C(
intadd_1054_n6), .CO(intadd_1054_n5), .S(intadd_1054_SUM_9_) );
CMPR32X2TS intadd_1054_U5 ( .A(intadd_1054_A_10_), .B(intadd_1054_B_10_),
.C(intadd_1054_n5), .CO(intadd_1054_n4), .S(intadd_1054_SUM_10_) );
CMPR32X2TS intadd_1054_U4 ( .A(intadd_1054_A_11_), .B(intadd_1054_B_11_),
.C(intadd_1054_n4), .CO(intadd_1054_n3), .S(intadd_1054_SUM_11_) );
CMPR32X2TS intadd_1054_U3 ( .A(intadd_1054_A_12_), .B(intadd_1054_B_12_),
.C(intadd_1054_n3), .CO(intadd_1054_n2), .S(intadd_1054_SUM_12_) );
CMPR32X2TS intadd_1054_U2 ( .A(intadd_1054_A_13_), .B(intadd_1054_B_13_),
.C(intadd_1054_n2), .CO(intadd_1054_n1), .S(intadd_1054_SUM_13_) );
CMPR32X2TS intadd_1055_U11 ( .A(intadd_1055_A_0_), .B(intadd_1055_B_0_), .C(
intadd_1055_CI), .CO(intadd_1055_n10), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[3]) );
CMPR32X2TS intadd_1055_U10 ( .A(intadd_1055_A_1_), .B(intadd_1055_B_1_), .C(
intadd_1055_n10), .CO(intadd_1055_n9), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[4]) );
CMPR32X2TS intadd_1055_U9 ( .A(intadd_1055_A_2_), .B(intadd_1055_B_2_), .C(
intadd_1055_n9), .CO(intadd_1055_n8), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[5]) );
CMPR32X2TS intadd_1055_U8 ( .A(DP_OP_496J314_122_3540_n377), .B(
intadd_1055_B_3_), .C(intadd_1055_n8), .CO(intadd_1055_n7), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[6]) );
CMPR32X2TS intadd_1055_U7 ( .A(DP_OP_496J314_122_3540_n376), .B(
DP_OP_496J314_122_3540_n374), .C(intadd_1055_n7), .CO(intadd_1055_n6),
.S(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[7]) );
CMPR32X2TS intadd_1055_U6 ( .A(DP_OP_496J314_122_3540_n373), .B(
DP_OP_496J314_122_3540_n369), .C(intadd_1055_n6), .CO(intadd_1055_n5),
.S(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]) );
CMPR32X2TS intadd_1055_U5 ( .A(DP_OP_496J314_122_3540_n368), .B(
DP_OP_496J314_122_3540_n364), .C(intadd_1055_n5), .CO(intadd_1055_n4),
.S(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[9]) );
CMPR32X2TS intadd_1055_U4 ( .A(DP_OP_496J314_122_3540_n363), .B(
DP_OP_496J314_122_3540_n361), .C(intadd_1055_n4), .CO(intadd_1055_n3),
.S(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[10]) );
DFFSX2TS R_7 ( .D(n2885), .CK(clk), .SN(n1731), .Q(n2952) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_27_ ( .D(1'b1), .CK(
FPSENCOS_reg_shift_y_net8160917), .RN(n2936), .Q(
FPSENCOS_d_ff3_LUT_out[27]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_28_ ( .D(
FPSENCOS_first_mux_X[28]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2941), .Q(FPSENCOS_d_ff2_X[28]), .QN(n2875) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_28_ ( .D(
FPSENCOS_first_mux_Y[28]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2938), .Q(FPSENCOS_d_ff2_Y[28]), .QN(n2874) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(add_subt_data2[0]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2893), .Q(
FPADDSUB_intDY_EWSW[0]), .QN(n2873) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(add_subt_data2[26]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2897), .Q(
FPADDSUB_intDY_EWSW[26]), .QN(n2871) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(add_subt_data2[1]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2892), .Q(
FPADDSUB_intDY_EWSW[1]), .QN(n2870) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(add_subt_data2[18]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2906), .Q(
FPADDSUB_intDY_EWSW[18]), .QN(n2869) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(add_subt_data2[8]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2893), .Q(
FPADDSUB_intDY_EWSW[8]), .QN(n2868) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(add_subt_data2[25]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2900), .Q(
FPADDSUB_intDY_EWSW[25]), .QN(n2867) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(add_subt_data2[17]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2895), .Q(
FPADDSUB_intDY_EWSW[17]), .QN(n2866) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(add_subt_data2[11]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2894), .Q(
FPADDSUB_intDY_EWSW[11]), .QN(n2864) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n2968), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8160827), .RN(n2916), .Q(
FPMULT_Sgf_normalized_result[1]), .QN(n2863) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(add_subt_data2[20]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n1734), .Q(
FPADDSUB_intDY_EWSW[20]), .QN(n2858) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(add_subt_data2[21]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n1734), .Q(
FPADDSUB_intDY_EWSW[21]), .QN(n2857) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(add_subt_data2[27]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n914), .Q(
FPADDSUB_intDY_EWSW[27]), .QN(n2856) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(add_subt_data2[9]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n912), .Q(
FPADDSUB_intDY_EWSW[9]), .QN(n2855) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(add_subt_data2[24]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2891), .Q(
FPADDSUB_intDY_EWSW[24]), .QN(n2854) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(add_subt_data2[2]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2894), .Q(
FPADDSUB_intDY_EWSW[2]), .QN(n2853) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(add_subt_data2[13]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2897), .Q(
FPADDSUB_intDY_EWSW[13]), .QN(n2852) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(add_subt_data2[4]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2892), .Q(
FPADDSUB_intDY_EWSW[4]), .QN(n2851) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(add_subt_data2[16]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2892), .Q(
FPADDSUB_intDY_EWSW[16]), .QN(n2850) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(add_subt_data2[6]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n914), .Q(
FPADDSUB_intDY_EWSW[6]), .QN(n2849) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(add_subt_data2[10]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2892), .Q(
FPADDSUB_intDY_EWSW[10]), .QN(n2848) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(add_subt_data1[12]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2894), .Q(
FPADDSUB_intDX_EWSW[12]), .QN(n2847) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_22_ ( .D(FPADDSUB_DMP_SHT2_EWSW[22]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n912), .Q(
FPADDSUB_DMP_SFG[22]), .QN(n2843) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_20_ ( .D(FPADDSUB_Data_array_SWR[20]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8160665), .RN(n2901), .Q(
FPADDSUB_Data_array_SWR[46]), .QN(n2842) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(add_subt_data1[14]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2901), .Q(
FPADDSUB_intDX_EWSW[14]), .QN(n2840) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(n2966), .CK(
clk), .RN(n2910), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]),
.QN(n2838) );
DFFRX1TS FPMULT_Sel_C_Q_reg_0_ ( .D(n834), .CK(FPMULT_FS_Module_net8160899),
.RN(n915), .Q(FPMULT_FSM_selector_C), .QN(n2837) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(add_subt_data1[5]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n914), .QN(n2836)
);
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_23_ ( .D(FPADDSUB_Data_array_SWR[23]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8160665), .RN(n1734), .Q(
FPADDSUB_Data_array_SWR[49]), .QN(n2832) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_22_ ( .D(FPADDSUB_Data_array_SWR[22]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8160665), .RN(n1734), .Q(
FPADDSUB_Data_array_SWR[48]), .QN(n2831) );
DFFRX1TS FPMULT_FS_Module_state_reg_reg_3_ ( .D(
FPMULT_FS_Module_state_next[3]), .CK(FPMULT_FS_Module_net8160899),
.RN(n2931), .Q(FPMULT_FS_Module_state_reg[3]), .QN(n2830) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(add_subt_data2[28]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n1831), .Q(
FPADDSUB_intDY_EWSW[28]), .QN(n2829) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_20_ ( .D(FPADDSUB_DMP_SHT2_EWSW[20]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n1734), .Q(
FPADDSUB_DMP_SFG[20]), .QN(n2828) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(add_subt_data1[3]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2907), .Q(
FPADDSUB_intDX_EWSW[3]), .QN(n2827) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(add_subt_data1[20]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2898), .Q(
FPADDSUB_intDX_EWSW[20]), .QN(n2826) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(add_subt_data1[18]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2896), .Q(
FPADDSUB_intDX_EWSW[18]), .QN(n2825) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(add_subt_data1[8]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2906), .Q(
FPADDSUB_intDX_EWSW[8]), .QN(n2823) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(add_subt_data1[17]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2907), .Q(
FPADDSUB_intDX_EWSW[17]), .QN(n2821) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(add_subt_data1[1]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2909), .Q(
FPADDSUB_intDX_EWSW[1]), .QN(n2820) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(add_subt_data1[15]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2906), .Q(
FPADDSUB_intDX_EWSW[15]), .QN(n2819) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(add_subt_data1[11]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n1734), .Q(
FPADDSUB_intDX_EWSW[11]), .QN(n2816) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(
FPADDSUB_shft_value_mux_o_EWR[2]), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8160665), .RN(n912), .Q(
FPADDSUB_shift_value_SHT2_EWR[2]), .QN(n2815) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_18_ ( .D(FPADDSUB_DMP_SHT2_EWSW[18]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2907), .Q(
FPADDSUB_DMP_SFG[18]), .QN(n2814) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_21_ ( .D(FPADDSUB_DMP_SHT2_EWSW[21]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2905), .Q(
FPADDSUB_DMP_SFG[21]), .QN(n2813) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(
FPADDSUB_Raw_mant_SGF[12]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8160665), .RN(n2903), .Q(FPADDSUB_Raw_mant_NRM_SWR[12]), .QN(n2810) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_16_ ( .D(FPADDSUB_DMP_SHT2_EWSW[16]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2897), .Q(
FPADDSUB_DMP_SFG[16]), .QN(n2809) );
DFFRX1TS FPMULT_Sel_B_Q_reg_0_ ( .D(n830), .CK(FPMULT_FS_Module_net8160899),
.RN(n2919), .Q(FPMULT_FSM_selector_B[0]), .QN(n2807) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]), .CK(clk), .RN(n2934), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .QN(n2806) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(
FPADDSUB_Raw_mant_SGF[20]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8160665), .RN(n2897), .Q(FPADDSUB_Raw_mant_NRM_SWR[20]), .QN(n2805) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(
FPADDSUB_Raw_mant_SGF[18]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8160665), .RN(n2910), .Q(FPADDSUB_Raw_mant_NRM_SWR[18]), .QN(n2804) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(
FPADDSUB_Raw_mant_SGF[25]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8160665), .RN(n2894), .Q(FPADDSUB_Raw_mant_NRM_SWR[25]), .QN(n2803) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(
FPADDSUB_Raw_mant_SGF[14]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8160665), .RN(n2902), .Q(FPADDSUB_Raw_mant_NRM_SWR[14]), .QN(n2802) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_14_ ( .D(FPADDSUB_DMP_SHT2_EWSW[14]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2893), .Q(
FPADDSUB_DMP_SFG[14]), .QN(n2799) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(
FPADDSUB_Raw_mant_SGF[17]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8160665), .RN(n2909), .Q(FPADDSUB_Raw_mant_NRM_SWR[17]), .QN(n2798) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_12_ ( .D(FPADDSUB_DMP_SHT2_EWSW[12]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2892), .Q(
FPADDSUB_DMP_SFG[12]), .QN(n2796) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_19_ ( .D(FPADDSUB_DMP_SHT2_EWSW[19]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2905), .Q(
FPADDSUB_DMP_SFG[19]), .QN(n2795) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[19]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n914), .Q(
FPADDSUB_DmP_mant_SFG_SWR[19]), .QN(n2791) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_10_ ( .D(FPADDSUB_DMP_SHT2_EWSW[10]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2894), .Q(
FPADDSUB_DMP_SFG[10]), .QN(n2790) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[17]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2891), .Q(
FPADDSUB_DmP_mant_SFG_SWR[17]), .QN(n2789) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_8_ ( .D(FPADDSUB_DMP_SHT2_EWSW[8]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2903), .Q(
FPADDSUB_DMP_SFG[8]), .QN(n2788) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_6_ ( .D(FPADDSUB_DMP_SHT2_EWSW[6]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n1831), .Q(
FPADDSUB_DMP_SFG[6]), .QN(n2787) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_4_ ( .D(FPADDSUB_DMP_SHT2_EWSW[4]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2904), .Q(
FPADDSUB_DMP_SFG[4]), .QN(n2786) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[15]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n1734), .Q(
FPADDSUB_DmP_mant_SFG_SWR[15]), .QN(n2785) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_2_ ( .D(FPADDSUB_DMP_SHT2_EWSW[2]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2905), .Q(
FPADDSUB_DMP_SFG[2]), .QN(n2784) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_0_ ( .D(FPADDSUB_DMP_SHT2_EWSW[0]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2894), .Q(
FPADDSUB_DMP_SFG[0]), .QN(n2783) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[13]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n1831), .Q(
FPADDSUB_DmP_mant_SFG_SWR[13]), .QN(n2782) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[11]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2900), .Q(
FPADDSUB_DmP_mant_SFG_SWR[11]), .QN(n2781) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[9]), .CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2897), .Q(FPADDSUB_DmP_mant_SFG_SWR[9]), .QN(n2780) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[7]), .CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n913), .Q(FPADDSUB_DmP_mant_SFG_SWR[7]), .QN(n2779) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_3_ ( .D(FPADDSUB_DMP_SHT2_EWSW[3]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2892), .Q(
FPADDSUB_DMP_SFG[3]), .QN(n2778) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[3]), .CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2898), .Q(FPADDSUB_DmP_mant_SFG_SWR[3]), .QN(n2777) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n2967), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8160827), .RN(n2913), .Q(
FPMULT_Sgf_normalized_result[0]), .QN(n2775) );
DFFRX1TS FPMULT_Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(
FPMULT_Adder_M_result_A_adder[24]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8160809), .RN(n2911), .Q(
FPMULT_FSM_add_overflow_flag), .QN(n2774) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(add_subt_data2[19]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2903), .Q(
FPADDSUB_intDY_EWSW[19]), .QN(n2773) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_24_ ( .D(FPADDSUB_Data_array_SWR[24]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8160665), .RN(n2901), .Q(
FPADDSUB_Data_array_SWR[50]), .QN(n2772) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(add_subt_data2[14]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2894), .Q(
FPADDSUB_intDY_EWSW[14]), .QN(n2771) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(add_subt_data1[0]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2910), .Q(
FPADDSUB_intDX_EWSW[0]), .QN(n2770) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(add_subt_data1[21]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2901), .Q(
FPADDSUB_intDX_EWSW[21]), .QN(n2768) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(add_subt_data1[7]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2908), .QN(n2767)
);
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(add_subt_data1[13]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2900), .Q(
FPADDSUB_intDX_EWSW[13]), .QN(n2766) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(add_subt_data1[9]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2894), .Q(
FPADDSUB_intDX_EWSW[9]), .QN(n2765) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(add_subt_data1[2]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2897), .Q(
FPADDSUB_intDX_EWSW[2]), .QN(n2764) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[23]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2908), .Q(
FPADDSUB_DmP_mant_SFG_SWR[23]), .QN(n2763) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(
FPADDSUB_Raw_mant_SGF[22]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8160665), .RN(n2897), .Q(FPADDSUB_Raw_mant_NRM_SWR[22]), .QN(n2762) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[21]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2908), .Q(
FPADDSUB_DmP_mant_SFG_SWR[21]), .QN(n2760) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_17_ ( .D(FPADDSUB_DMP_SHT2_EWSW[17]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2904), .Q(
FPADDSUB_DMP_SFG[17]), .QN(n2759) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_15_ ( .D(FPADDSUB_DMP_SHT2_EWSW[15]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2904), .Q(
FPADDSUB_DMP_SFG[15]), .QN(n2758) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_13_ ( .D(FPADDSUB_DMP_SHT2_EWSW[13]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2898), .Q(
FPADDSUB_DMP_SFG[13]), .QN(n2757) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_11_ ( .D(FPADDSUB_DMP_SHT2_EWSW[11]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2898), .Q(
FPADDSUB_DMP_SFG[11]), .QN(n2756) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_9_ ( .D(FPADDSUB_DMP_SHT2_EWSW[9]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n912), .Q(
FPADDSUB_DMP_SFG[9]), .QN(n2755) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_7_ ( .D(FPADDSUB_DMP_SHT2_EWSW[7]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2891), .Q(
FPADDSUB_DMP_SFG[7]), .QN(n2754) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_5_ ( .D(FPADDSUB_DMP_SHT2_EWSW[5]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2903), .Q(
FPADDSUB_DMP_SFG[5]), .QN(n2753) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[5]), .CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2893), .Q(FPADDSUB_DmP_mant_SFG_SWR[5]), .QN(n2752) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_1_ ( .D(FPADDSUB_DMP_SHT2_EWSW[1]),
.CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2903), .Q(
FPADDSUB_DMP_SFG[1]), .QN(n2751) );
CMPR32X2TS intadd_1055_U3 ( .A(DP_OP_496J314_122_3540_n360), .B(
intadd_1055_B_8_), .C(intadd_1055_n3), .CO(intadd_1055_n2), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[11]) );
CMPR32X2TS intadd_1055_U2 ( .A(intadd_1055_A_9_), .B(intadd_1055_B_9_), .C(
intadd_1055_n2), .CO(intadd_1055_n1), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]) );
CMPR32X2TS intadd_1056_U10 ( .A(n973), .B(n979), .C(intadd_1056_n10), .CO(
intadd_1056_n9), .S(intadd_1059_A_1_) );
CMPR32X2TS intadd_1056_U3 ( .A(FPMULT_Op_MX[21]), .B(n981), .C(
intadd_1056_n3), .CO(intadd_1056_n2), .S(intadd_1059_B_1_) );
CMPR32X2TS intadd_1056_U2 ( .A(n984), .B(FPMULT_Op_MX[10]), .C(
intadd_1056_n2), .CO(intadd_1056_n1), .S(intadd_1059_B_2_) );
CMPR32X2TS intadd_1057_U3 ( .A(FPMULT_Op_MY[21]), .B(n977), .C(
intadd_1057_n3), .CO(intadd_1057_n2), .S(intadd_1057_SUM_8_) );
CMPR32X2TS intadd_1057_U2 ( .A(FPMULT_Op_MY[22]), .B(n975), .C(
intadd_1057_n2), .CO(intadd_1057_n1), .S(intadd_1057_SUM_9_) );
CMPR32X2TS DP_OP_234J314_129_4955_U2 ( .A(FPMULT_FSM_exp_operation_A_S), .B(
FPMULT_S_Oper_A_exp[8]), .C(DP_OP_234J314_129_4955_n2), .CO(
DP_OP_234J314_129_4955_n1), .S(FPMULT_Exp_module_Data_S[8]) );
CMPR32X2TS intadd_1057_U5 ( .A(FPMULT_Op_MY[19]), .B(n976), .C(
intadd_1057_n5), .CO(intadd_1057_n4), .S(intadd_1057_SUM_6_) );
CMPR32X2TS intadd_1058_U9 ( .A(intadd_1058_A_1_), .B(intadd_1058_B_1_), .C(
intadd_1058_n9), .CO(intadd_1058_n8), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]) );
CMPR32X2TS DP_OP_234J314_129_4955_U10 ( .A(FPMULT_S_Oper_A_exp[0]), .B(
FPMULT_FSM_exp_operation_A_S), .C(DP_OP_234J314_129_4955_n22), .CO(
DP_OP_234J314_129_4955_n9), .S(FPMULT_Exp_module_Data_S[0]) );
CMPR32X2TS DP_OP_234J314_129_4955_U9 ( .A(DP_OP_234J314_129_4955_n21), .B(
FPMULT_S_Oper_A_exp[1]), .C(DP_OP_234J314_129_4955_n9), .CO(
DP_OP_234J314_129_4955_n8), .S(FPMULT_Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_234J314_129_4955_U8 ( .A(DP_OP_234J314_129_4955_n20), .B(
FPMULT_S_Oper_A_exp[2]), .C(DP_OP_234J314_129_4955_n8), .CO(
DP_OP_234J314_129_4955_n7), .S(FPMULT_Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_234J314_129_4955_U7 ( .A(DP_OP_234J314_129_4955_n19), .B(
FPMULT_S_Oper_A_exp[3]), .C(DP_OP_234J314_129_4955_n7), .CO(
DP_OP_234J314_129_4955_n6), .S(FPMULT_Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_234J314_129_4955_U6 ( .A(DP_OP_234J314_129_4955_n18), .B(
FPMULT_S_Oper_A_exp[4]), .C(DP_OP_234J314_129_4955_n6), .CO(
DP_OP_234J314_129_4955_n5), .S(FPMULT_Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_234J314_129_4955_U5 ( .A(DP_OP_234J314_129_4955_n17), .B(
FPMULT_S_Oper_A_exp[5]), .C(DP_OP_234J314_129_4955_n5), .CO(
DP_OP_234J314_129_4955_n4), .S(FPMULT_Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_234J314_129_4955_U4 ( .A(DP_OP_234J314_129_4955_n16), .B(
FPMULT_S_Oper_A_exp[6]), .C(DP_OP_234J314_129_4955_n4), .CO(
DP_OP_234J314_129_4955_n3), .S(FPMULT_Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_234J314_129_4955_U3 ( .A(DP_OP_234J314_129_4955_n15), .B(
FPMULT_S_Oper_A_exp[7]), .C(DP_OP_234J314_129_4955_n3), .CO(
DP_OP_234J314_129_4955_n2), .S(FPMULT_Exp_module_Data_S[7]) );
CMPR32X2TS DP_OP_26J314_126_1325_U5 ( .A(DP_OP_26J314_126_1325_n14), .B(
FPADDSUB_DMP_exp_NRM2_EW[4]), .C(DP_OP_26J314_126_1325_n5), .CO(
DP_OP_26J314_126_1325_n4), .S(FPADDSUB_exp_rslt_NRM2_EW1[4]) );
CMPR32X2TS DP_OP_26J314_126_1325_U4 ( .A(n962), .B(
FPADDSUB_DMP_exp_NRM2_EW[5]), .C(DP_OP_26J314_126_1325_n4), .CO(
DP_OP_26J314_126_1325_n3), .S(FPADDSUB_exp_rslt_NRM2_EW1[5]) );
CMPR32X2TS DP_OP_26J314_126_1325_U3 ( .A(n962), .B(
FPADDSUB_DMP_exp_NRM2_EW[6]), .C(DP_OP_26J314_126_1325_n3), .CO(
DP_OP_26J314_126_1325_n2), .S(FPADDSUB_exp_rslt_NRM2_EW1[6]) );
CMPR32X2TS intadd_1056_U6 ( .A(FPMULT_Op_MX[18]), .B(FPMULT_Op_MX[6]), .C(
intadd_1056_n6), .CO(intadd_1056_n5), .S(intadd_1056_SUM_5_) );
CMPR32X2TS intadd_1056_U4 ( .A(n985), .B(FPMULT_Op_MX[8]), .C(intadd_1056_n4), .CO(intadd_1056_n3), .S(intadd_1059_CI) );
CMPR32X2TS DP_OP_26J314_126_1325_U2 ( .A(n962), .B(
FPADDSUB_DMP_exp_NRM2_EW[7]), .C(DP_OP_26J314_126_1325_n2), .CO(
DP_OP_26J314_126_1325_n1), .S(FPADDSUB_exp_rslt_NRM2_EW1[7]) );
CMPR32X2TS intadd_1057_U4 ( .A(FPMULT_Op_MY[20]), .B(FPMULT_Op_MY[8]), .C(
intadd_1057_n4), .CO(intadd_1057_n3), .S(intadd_1057_SUM_7_) );
CMPR32X2TS intadd_1056_U8 ( .A(FPMULT_Op_MX[16]), .B(n982), .C(
intadd_1056_n8), .CO(intadd_1056_n7), .S(intadd_1059_A_3_) );
CMPR42X1TS DP_OP_499J314_125_1651_U46 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[1]), .C(
DP_OP_499J314_125_1651_n110), .D(DP_OP_499J314_125_1651_n133), .ICI(
DP_OP_499J314_125_1651_n81), .S(DP_OP_499J314_125_1651_n78), .ICO(
DP_OP_499J314_125_1651_n76), .CO(DP_OP_499J314_125_1651_n77) );
CMPR42X1TS DP_OP_499J314_125_1651_U45 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[9]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[2]), .C(
DP_OP_499J314_125_1651_n109), .D(DP_OP_499J314_125_1651_n132), .ICI(
DP_OP_499J314_125_1651_n76), .S(DP_OP_499J314_125_1651_n75), .ICO(
DP_OP_499J314_125_1651_n73), .CO(DP_OP_499J314_125_1651_n74) );
CMPR42X1TS DP_OP_499J314_125_1651_U44 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[10]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[3]), .C(
DP_OP_499J314_125_1651_n108), .D(DP_OP_499J314_125_1651_n131), .ICI(
DP_OP_499J314_125_1651_n73), .S(DP_OP_499J314_125_1651_n72), .ICO(
DP_OP_499J314_125_1651_n70), .CO(DP_OP_499J314_125_1651_n71) );
CMPR42X1TS DP_OP_499J314_125_1651_U43 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[11]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[4]), .C(
DP_OP_499J314_125_1651_n107), .D(DP_OP_499J314_125_1651_n130), .ICI(
DP_OP_499J314_125_1651_n70), .S(DP_OP_499J314_125_1651_n69), .ICO(
DP_OP_499J314_125_1651_n67), .CO(DP_OP_499J314_125_1651_n68) );
CMPR42X1TS DP_OP_499J314_125_1651_U42 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[5]), .C(
DP_OP_499J314_125_1651_n106), .D(DP_OP_499J314_125_1651_n129), .ICI(
DP_OP_499J314_125_1651_n67), .S(DP_OP_499J314_125_1651_n66), .ICO(
DP_OP_499J314_125_1651_n64), .CO(DP_OP_499J314_125_1651_n65) );
CMPR42X1TS DP_OP_499J314_125_1651_U41 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[6]), .C(
DP_OP_499J314_125_1651_n105), .D(DP_OP_499J314_125_1651_n128), .ICI(
DP_OP_499J314_125_1651_n64), .S(DP_OP_499J314_125_1651_n63), .ICO(
DP_OP_499J314_125_1651_n61), .CO(DP_OP_499J314_125_1651_n62) );
CMPR42X1TS DP_OP_499J314_125_1651_U40 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[7]), .C(
DP_OP_499J314_125_1651_n104), .D(DP_OP_499J314_125_1651_n127), .ICI(
DP_OP_499J314_125_1651_n61), .S(DP_OP_499J314_125_1651_n60), .ICO(
DP_OP_499J314_125_1651_n58), .CO(DP_OP_499J314_125_1651_n59) );
CMPR42X1TS DP_OP_499J314_125_1651_U39 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[8]), .C(
DP_OP_499J314_125_1651_n103), .D(DP_OP_499J314_125_1651_n126), .ICI(
DP_OP_499J314_125_1651_n58), .S(DP_OP_499J314_125_1651_n57), .ICO(
DP_OP_499J314_125_1651_n55), .CO(DP_OP_499J314_125_1651_n56) );
CMPR42X1TS DP_OP_499J314_125_1651_U38 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[9]), .C(
DP_OP_499J314_125_1651_n102), .D(DP_OP_499J314_125_1651_n125), .ICI(
DP_OP_499J314_125_1651_n55), .S(DP_OP_499J314_125_1651_n54), .ICO(
DP_OP_499J314_125_1651_n52), .CO(DP_OP_499J314_125_1651_n53) );
CMPR42X1TS DP_OP_499J314_125_1651_U37 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[10]), .C(
DP_OP_499J314_125_1651_n101), .D(DP_OP_499J314_125_1651_n124), .ICI(
DP_OP_499J314_125_1651_n52), .S(DP_OP_499J314_125_1651_n51), .ICO(
DP_OP_499J314_125_1651_n49), .CO(DP_OP_499J314_125_1651_n50) );
CMPR42X1TS DP_OP_499J314_125_1651_U36 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[11]), .C(
DP_OP_499J314_125_1651_n100), .D(DP_OP_499J314_125_1651_n123), .ICI(
DP_OP_499J314_125_1651_n49), .S(DP_OP_499J314_125_1651_n48), .ICO(
DP_OP_499J314_125_1651_n46), .CO(DP_OP_499J314_125_1651_n47) );
CMPR42X1TS DP_OP_499J314_125_1651_U35 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[12]), .C(
DP_OP_499J314_125_1651_n99), .D(DP_OP_499J314_125_1651_n122), .ICI(
DP_OP_499J314_125_1651_n46), .S(DP_OP_499J314_125_1651_n45), .ICO(
DP_OP_499J314_125_1651_n43), .CO(DP_OP_499J314_125_1651_n44) );
CMPR42X1TS DP_OP_499J314_125_1651_U34 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[13]), .C(
DP_OP_499J314_125_1651_n98), .D(DP_OP_499J314_125_1651_n121), .ICI(
DP_OP_499J314_125_1651_n43), .S(DP_OP_499J314_125_1651_n42), .ICO(
DP_OP_499J314_125_1651_n40), .CO(DP_OP_499J314_125_1651_n41) );
CMPR42X1TS DP_OP_499J314_125_1651_U33 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[14]), .C(
DP_OP_499J314_125_1651_n97), .D(DP_OP_499J314_125_1651_n120), .ICI(
DP_OP_499J314_125_1651_n40), .S(DP_OP_499J314_125_1651_n39), .ICO(
DP_OP_499J314_125_1651_n37), .CO(DP_OP_499J314_125_1651_n38) );
CMPR42X1TS DP_OP_499J314_125_1651_U32 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[15]), .C(
DP_OP_499J314_125_1651_n96), .D(DP_OP_499J314_125_1651_n119), .ICI(
DP_OP_499J314_125_1651_n37), .S(DP_OP_499J314_125_1651_n36), .ICO(
DP_OP_499J314_125_1651_n34), .CO(DP_OP_499J314_125_1651_n35) );
CMPR42X1TS DP_OP_499J314_125_1651_U31 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[16]), .C(
DP_OP_499J314_125_1651_n95), .D(DP_OP_499J314_125_1651_n118), .ICI(
DP_OP_499J314_125_1651_n34), .S(DP_OP_499J314_125_1651_n33), .ICO(
DP_OP_499J314_125_1651_n31), .CO(DP_OP_499J314_125_1651_n32) );
CMPR42X1TS DP_OP_498J314_124_1725_U253 ( .A(DP_OP_498J314_124_1725_n370),
.B(DP_OP_498J314_124_1725_n360), .C(DP_OP_498J314_124_1725_n365), .D(
DP_OP_498J314_124_1725_n335), .ICI(DP_OP_498J314_124_1725_n332), .S(
DP_OP_498J314_124_1725_n330), .ICO(DP_OP_498J314_124_1725_n328), .CO(
DP_OP_498J314_124_1725_n329) );
CMPR42X1TS DP_OP_498J314_124_1725_U250 ( .A(DP_OP_498J314_124_1725_n364),
.B(DP_OP_498J314_124_1725_n331), .C(DP_OP_498J314_124_1725_n328), .D(
DP_OP_498J314_124_1725_n327), .ICI(DP_OP_498J314_124_1725_n325), .S(
DP_OP_498J314_124_1725_n323), .ICO(DP_OP_498J314_124_1725_n321), .CO(
DP_OP_498J314_124_1725_n322) );
CMPR42X1TS DP_OP_498J314_124_1725_U247 ( .A(DP_OP_498J314_124_1725_n326),
.B(DP_OP_498J314_124_1725_n324), .C(DP_OP_498J314_124_1725_n320), .D(
DP_OP_498J314_124_1725_n318), .ICI(DP_OP_498J314_124_1725_n321), .S(
DP_OP_498J314_124_1725_n316), .ICO(DP_OP_498J314_124_1725_n314), .CO(
DP_OP_498J314_124_1725_n315) );
CMPR42X1TS DP_OP_498J314_124_1725_U245 ( .A(DP_OP_498J314_124_1725_n352),
.B(DP_OP_498J314_124_1725_n319), .C(DP_OP_498J314_124_1725_n317), .D(
DP_OP_498J314_124_1725_n313), .ICI(DP_OP_498J314_124_1725_n314), .S(
DP_OP_498J314_124_1725_n311), .ICO(DP_OP_498J314_124_1725_n309), .CO(
DP_OP_498J314_124_1725_n310) );
CMPR42X1TS DP_OP_498J314_124_1725_U244 ( .A(DP_OP_498J314_124_1725_n351),
.B(DP_OP_498J314_124_1725_n341), .C(DP_OP_498J314_124_1725_n346), .D(
DP_OP_498J314_124_1725_n312), .ICI(DP_OP_498J314_124_1725_n309), .S(
DP_OP_498J314_124_1725_n308), .ICO(DP_OP_498J314_124_1725_n306), .CO(
DP_OP_498J314_124_1725_n307) );
CMPR42X1TS DP_OP_498J314_124_1725_U180 ( .A(DP_OP_498J314_124_1725_n279),
.B(DP_OP_498J314_124_1725_n269), .C(DP_OP_498J314_124_1725_n274), .D(
DP_OP_498J314_124_1725_n244), .ICI(DP_OP_498J314_124_1725_n241), .S(
DP_OP_498J314_124_1725_n239), .ICO(DP_OP_498J314_124_1725_n237), .CO(
DP_OP_498J314_124_1725_n238) );
CMPR42X1TS DP_OP_498J314_124_1725_U177 ( .A(DP_OP_498J314_124_1725_n273),
.B(DP_OP_498J314_124_1725_n240), .C(DP_OP_498J314_124_1725_n237), .D(
DP_OP_498J314_124_1725_n236), .ICI(DP_OP_498J314_124_1725_n234), .S(
DP_OP_498J314_124_1725_n232), .ICO(DP_OP_498J314_124_1725_n230), .CO(
DP_OP_498J314_124_1725_n231) );
CMPR42X1TS DP_OP_498J314_124_1725_U174 ( .A(DP_OP_498J314_124_1725_n235),
.B(DP_OP_498J314_124_1725_n233), .C(DP_OP_498J314_124_1725_n229), .D(
DP_OP_498J314_124_1725_n227), .ICI(DP_OP_498J314_124_1725_n230), .S(
DP_OP_498J314_124_1725_n225), .ICO(DP_OP_498J314_124_1725_n223), .CO(
DP_OP_498J314_124_1725_n224) );
CMPR42X1TS DP_OP_498J314_124_1725_U172 ( .A(DP_OP_498J314_124_1725_n261),
.B(DP_OP_498J314_124_1725_n228), .C(DP_OP_498J314_124_1725_n226), .D(
DP_OP_498J314_124_1725_n222), .ICI(DP_OP_498J314_124_1725_n223), .S(
DP_OP_498J314_124_1725_n220), .ICO(DP_OP_498J314_124_1725_n218), .CO(
DP_OP_498J314_124_1725_n219) );
CMPR42X1TS DP_OP_498J314_124_1725_U171 ( .A(DP_OP_498J314_124_1725_n260),
.B(DP_OP_498J314_124_1725_n250), .C(DP_OP_498J314_124_1725_n255), .D(
DP_OP_498J314_124_1725_n221), .ICI(DP_OP_498J314_124_1725_n218), .S(
DP_OP_498J314_124_1725_n217), .ICO(DP_OP_498J314_124_1725_n215), .CO(
DP_OP_498J314_124_1725_n216) );
CMPR42X1TS DP_OP_498J314_124_1725_U39 ( .A(DP_OP_498J314_124_1725_n202), .B(
n1080), .C(DP_OP_498J314_124_1725_n201), .D(
DP_OP_498J314_124_1725_n118), .ICI(DP_OP_498J314_124_1725_n125), .S(
DP_OP_498J314_124_1725_n75), .ICO(DP_OP_498J314_124_1725_n73), .CO(
DP_OP_498J314_124_1725_n74) );
CMPR42X1TS DP_OP_498J314_124_1725_U37 ( .A(n1070), .B(
DP_OP_498J314_124_1725_n124), .C(DP_OP_498J314_124_1725_n72), .D(
DP_OP_498J314_124_1725_n117), .ICI(DP_OP_498J314_124_1725_n91), .S(
DP_OP_498J314_124_1725_n70), .ICO(DP_OP_498J314_124_1725_n68), .CO(
DP_OP_498J314_124_1725_n69) );
CMPR42X1TS DP_OP_498J314_124_1725_U35 ( .A(DP_OP_498J314_124_1725_n116), .B(
DP_OP_498J314_124_1725_n109), .C(DP_OP_498J314_124_1725_n123), .D(
DP_OP_498J314_124_1725_n68), .ICI(DP_OP_498J314_124_1725_n67), .S(
DP_OP_498J314_124_1725_n65), .ICO(DP_OP_498J314_124_1725_n63), .CO(
DP_OP_498J314_124_1725_n64) );
CMPR42X1TS DP_OP_498J314_124_1725_U32 ( .A(DP_OP_498J314_124_1725_n122), .B(
DP_OP_498J314_124_1725_n62), .C(DP_OP_498J314_124_1725_n108), .D(
DP_OP_498J314_124_1725_n90), .ICI(DP_OP_498J314_124_1725_n60), .S(
DP_OP_498J314_124_1725_n58), .ICO(DP_OP_498J314_124_1725_n56), .CO(
DP_OP_498J314_124_1725_n57) );
CMPR42X1TS DP_OP_498J314_124_1725_U31 ( .A(DP_OP_498J314_124_1725_n114), .B(
DP_OP_498J314_124_1725_n61), .C(DP_OP_498J314_124_1725_n83), .D(
DP_OP_498J314_124_1725_n197), .ICI(DP_OP_498J314_124_1725_n100), .S(
DP_OP_498J314_124_1725_n55), .ICO(DP_OP_498J314_124_1725_n53), .CO(
DP_OP_498J314_124_1725_n54) );
CMPR42X1TS DP_OP_498J314_124_1725_U30 ( .A(DP_OP_498J314_124_1725_n121), .B(
DP_OP_498J314_124_1725_n107), .C(DP_OP_498J314_124_1725_n59), .D(
DP_OP_498J314_124_1725_n56), .ICI(DP_OP_498J314_124_1725_n55), .S(
DP_OP_498J314_124_1725_n52), .ICO(DP_OP_498J314_124_1725_n50), .CO(
DP_OP_498J314_124_1725_n51) );
CMPR42X1TS DP_OP_498J314_124_1725_U29 ( .A(DP_OP_498J314_124_1725_n120), .B(
DP_OP_498J314_124_1725_n113), .C(DP_OP_498J314_124_1725_n106), .D(
DP_OP_498J314_124_1725_n99), .ICI(DP_OP_498J314_124_1725_n82), .S(
DP_OP_498J314_124_1725_n49), .ICO(DP_OP_498J314_124_1725_n47), .CO(
DP_OP_498J314_124_1725_n48) );
CMPR42X1TS DP_OP_498J314_124_1725_U28 ( .A(DP_OP_498J314_124_1725_n53), .B(
DP_OP_498J314_124_1725_n196), .C(DP_OP_498J314_124_1725_n50), .D(
DP_OP_498J314_124_1725_n54), .ICI(DP_OP_498J314_124_1725_n49), .S(
DP_OP_498J314_124_1725_n46), .ICO(DP_OP_498J314_124_1725_n44), .CO(
DP_OP_498J314_124_1725_n45) );
CMPR42X1TS DP_OP_498J314_124_1725_U27 ( .A(DP_OP_498J314_124_1725_n119), .B(
DP_OP_498J314_124_1725_n112), .C(DP_OP_498J314_124_1725_n105), .D(
DP_OP_498J314_124_1725_n98), .ICI(DP_OP_498J314_124_1725_n47), .S(
DP_OP_498J314_124_1725_n43), .ICO(DP_OP_498J314_124_1725_n41), .CO(
DP_OP_498J314_124_1725_n42) );
CMPR42X1TS DP_OP_498J314_124_1725_U26 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]), .B(
DP_OP_498J314_124_1725_n81), .C(DP_OP_498J314_124_1725_n48), .D(
DP_OP_498J314_124_1725_n44), .ICI(DP_OP_498J314_124_1725_n43), .S(
DP_OP_498J314_124_1725_n40), .ICO(DP_OP_498J314_124_1725_n38), .CO(
DP_OP_498J314_124_1725_n39) );
CMPR42X1TS DP_OP_498J314_124_1725_U25 ( .A(DP_OP_498J314_124_1725_n111), .B(
DP_OP_498J314_124_1725_n104), .C(DP_OP_498J314_124_1725_n97), .D(
DP_OP_498J314_124_1725_n41), .ICI(DP_OP_498J314_124_1725_n195), .S(
DP_OP_498J314_124_1725_n37), .ICO(DP_OP_498J314_124_1725_n35), .CO(
DP_OP_498J314_124_1725_n36) );
CMPR42X1TS DP_OP_498J314_124_1725_U24 ( .A(DP_OP_498J314_124_1725_n42), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]), .C(
DP_OP_498J314_124_1725_n80), .D(DP_OP_498J314_124_1725_n38), .ICI(
DP_OP_498J314_124_1725_n37), .S(DP_OP_498J314_124_1725_n34), .ICO(
DP_OP_498J314_124_1725_n32), .CO(DP_OP_498J314_124_1725_n33) );
CMPR42X1TS DP_OP_498J314_124_1725_U23 ( .A(DP_OP_498J314_124_1725_n110), .B(
DP_OP_498J314_124_1725_n103), .C(DP_OP_498J314_124_1725_n96), .D(
DP_OP_498J314_124_1725_n35), .ICI(DP_OP_498J314_124_1725_n194), .S(
DP_OP_498J314_124_1725_n31), .ICO(DP_OP_498J314_124_1725_n29), .CO(
DP_OP_498J314_124_1725_n30) );
CMPR42X1TS DP_OP_498J314_124_1725_U22 ( .A(DP_OP_498J314_124_1725_n36), .B(
DP_OP_498J314_124_1725_n32), .C(DP_OP_498J314_124_1725_n193), .D(
DP_OP_498J314_124_1725_n79), .ICI(DP_OP_498J314_124_1725_n31), .S(
DP_OP_498J314_124_1725_n28), .ICO(DP_OP_498J314_124_1725_n26), .CO(
DP_OP_498J314_124_1725_n27) );
CMPR42X1TS DP_OP_498J314_124_1725_U20 ( .A(DP_OP_498J314_124_1725_n25), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[11]), .C(
DP_OP_498J314_124_1725_n30), .D(DP_OP_498J314_124_1725_n78), .ICI(
DP_OP_498J314_124_1725_n26), .S(DP_OP_498J314_124_1725_n23), .ICO(
DP_OP_498J314_124_1725_n21), .CO(DP_OP_498J314_124_1725_n22) );
CMPR42X1TS DP_OP_498J314_124_1725_U19 ( .A(DP_OP_498J314_124_1725_n94), .B(
DP_OP_498J314_124_1725_n101), .C(DP_OP_498J314_124_1725_n24), .D(
DP_OP_498J314_124_1725_n192), .ICI(DP_OP_498J314_124_1725_n21), .S(
DP_OP_498J314_124_1725_n20), .ICO(DP_OP_498J314_124_1725_n18), .CO(
DP_OP_498J314_124_1725_n19) );
CMPR42X1TS DP_OP_497J314_123_1725_U254 ( .A(DP_OP_497J314_123_1725_n369),
.B(DP_OP_497J314_123_1725_n359), .C(DP_OP_497J314_123_1725_n364), .D(
DP_OP_497J314_123_1725_n335), .ICI(DP_OP_497J314_123_1725_n332), .S(
DP_OP_497J314_123_1725_n330), .ICO(DP_OP_497J314_123_1725_n328), .CO(
DP_OP_497J314_123_1725_n329) );
CMPR42X1TS DP_OP_497J314_123_1725_U251 ( .A(DP_OP_497J314_123_1725_n358),
.B(DP_OP_497J314_123_1725_n331), .C(DP_OP_497J314_123_1725_n328), .D(
DP_OP_497J314_123_1725_n327), .ICI(DP_OP_497J314_123_1725_n325), .S(
DP_OP_497J314_123_1725_n323), .ICO(DP_OP_497J314_123_1725_n321), .CO(
DP_OP_497J314_123_1725_n322) );
CMPR42X1TS DP_OP_497J314_123_1725_U248 ( .A(DP_OP_497J314_123_1725_n326),
.B(DP_OP_497J314_123_1725_n320), .C(DP_OP_497J314_123_1725_n324), .D(
DP_OP_497J314_123_1725_n318), .ICI(DP_OP_497J314_123_1725_n321), .S(
DP_OP_497J314_123_1725_n316), .ICO(DP_OP_497J314_123_1725_n314), .CO(
DP_OP_497J314_123_1725_n315) );
CMPR42X1TS DP_OP_497J314_123_1725_U246 ( .A(DP_OP_497J314_123_1725_n351),
.B(DP_OP_497J314_123_1725_n319), .C(DP_OP_497J314_123_1725_n313), .D(
DP_OP_497J314_123_1725_n317), .ICI(DP_OP_497J314_123_1725_n314), .S(
DP_OP_497J314_123_1725_n311), .ICO(DP_OP_497J314_123_1725_n309), .CO(
DP_OP_497J314_123_1725_n310) );
CMPR42X1TS DP_OP_497J314_123_1725_U245 ( .A(FPMULT_Op_MX[21]), .B(
FPMULT_Op_MY[21]), .C(DP_OP_497J314_123_1725_n345), .D(
DP_OP_497J314_123_1725_n312), .ICI(DP_OP_497J314_123_1725_n309), .S(
DP_OP_497J314_123_1725_n308), .ICO(DP_OP_497J314_123_1725_n306), .CO(
DP_OP_497J314_123_1725_n307) );
CMPR42X1TS DP_OP_497J314_123_1725_U180 ( .A(DP_OP_497J314_123_1725_n279),
.B(DP_OP_497J314_123_1725_n269), .C(DP_OP_497J314_123_1725_n274), .D(
DP_OP_497J314_123_1725_n244), .ICI(DP_OP_497J314_123_1725_n241), .S(
DP_OP_497J314_123_1725_n239), .ICO(DP_OP_497J314_123_1725_n237), .CO(
DP_OP_497J314_123_1725_n238) );
CMPR42X1TS DP_OP_497J314_123_1725_U177 ( .A(DP_OP_497J314_123_1725_n273),
.B(DP_OP_497J314_123_1725_n240), .C(DP_OP_497J314_123_1725_n237), .D(
DP_OP_497J314_123_1725_n236), .ICI(DP_OP_497J314_123_1725_n234), .S(
DP_OP_497J314_123_1725_n232), .ICO(DP_OP_497J314_123_1725_n230), .CO(
DP_OP_497J314_123_1725_n231) );
CMPR42X1TS DP_OP_497J314_123_1725_U174 ( .A(DP_OP_497J314_123_1725_n235),
.B(DP_OP_497J314_123_1725_n233), .C(DP_OP_497J314_123_1725_n229), .D(
DP_OP_497J314_123_1725_n227), .ICI(DP_OP_497J314_123_1725_n230), .S(
DP_OP_497J314_123_1725_n225), .ICO(DP_OP_497J314_123_1725_n223), .CO(
DP_OP_497J314_123_1725_n224) );
CMPR42X1TS DP_OP_497J314_123_1725_U172 ( .A(DP_OP_497J314_123_1725_n261),
.B(DP_OP_497J314_123_1725_n228), .C(DP_OP_497J314_123_1725_n226), .D(
DP_OP_497J314_123_1725_n222), .ICI(DP_OP_497J314_123_1725_n223), .S(
DP_OP_497J314_123_1725_n220), .ICO(DP_OP_497J314_123_1725_n218), .CO(
DP_OP_497J314_123_1725_n219) );
CMPR42X1TS DP_OP_497J314_123_1725_U171 ( .A(DP_OP_497J314_123_1725_n260),
.B(DP_OP_497J314_123_1725_n250), .C(DP_OP_497J314_123_1725_n255), .D(
DP_OP_497J314_123_1725_n221), .ICI(DP_OP_497J314_123_1725_n218), .S(
DP_OP_497J314_123_1725_n217), .ICO(DP_OP_497J314_123_1725_n215), .CO(
DP_OP_497J314_123_1725_n216) );
CMPR42X1TS DP_OP_497J314_123_1725_U39 ( .A(DP_OP_497J314_123_1725_n202), .B(
DP_OP_497J314_123_1725_n87), .C(DP_OP_497J314_123_1725_n201), .D(
DP_OP_497J314_123_1725_n118), .ICI(DP_OP_497J314_123_1725_n125), .S(
DP_OP_497J314_123_1725_n75), .ICO(DP_OP_497J314_123_1725_n73), .CO(
DP_OP_497J314_123_1725_n74) );
CMPR42X1TS DP_OP_497J314_123_1725_U37 ( .A(n1071), .B(
DP_OP_497J314_123_1725_n124), .C(DP_OP_497J314_123_1725_n72), .D(
DP_OP_497J314_123_1725_n117), .ICI(DP_OP_497J314_123_1725_n91), .S(
DP_OP_497J314_123_1725_n70), .ICO(DP_OP_497J314_123_1725_n68), .CO(
DP_OP_497J314_123_1725_n69) );
CMPR42X1TS DP_OP_497J314_123_1725_U35 ( .A(DP_OP_497J314_123_1725_n116), .B(
DP_OP_497J314_123_1725_n109), .C(DP_OP_497J314_123_1725_n123), .D(
DP_OP_497J314_123_1725_n68), .ICI(DP_OP_497J314_123_1725_n67), .S(
DP_OP_497J314_123_1725_n65), .ICO(DP_OP_497J314_123_1725_n63), .CO(
DP_OP_497J314_123_1725_n64) );
CMPR42X1TS DP_OP_497J314_123_1725_U32 ( .A(DP_OP_497J314_123_1725_n62), .B(
DP_OP_497J314_123_1725_n122), .C(DP_OP_497J314_123_1725_n60), .D(
DP_OP_497J314_123_1725_n64), .ICI(DP_OP_497J314_123_1725_n108), .S(
DP_OP_497J314_123_1725_n58), .ICO(DP_OP_497J314_123_1725_n56), .CO(
DP_OP_497J314_123_1725_n57) );
CMPR42X1TS DP_OP_497J314_123_1725_U31 ( .A(DP_OP_497J314_123_1725_n114), .B(
DP_OP_497J314_123_1725_n61), .C(DP_OP_497J314_123_1725_n83), .D(
DP_OP_497J314_123_1725_n197), .ICI(DP_OP_497J314_123_1725_n100), .S(
DP_OP_497J314_123_1725_n55), .ICO(DP_OP_497J314_123_1725_n53), .CO(
DP_OP_497J314_123_1725_n54) );
CMPR42X1TS DP_OP_497J314_123_1725_U30 ( .A(DP_OP_497J314_123_1725_n121), .B(
DP_OP_497J314_123_1725_n59), .C(DP_OP_497J314_123_1725_n107), .D(
DP_OP_497J314_123_1725_n56), .ICI(DP_OP_497J314_123_1725_n55), .S(
DP_OP_497J314_123_1725_n52), .ICO(DP_OP_497J314_123_1725_n50), .CO(
DP_OP_497J314_123_1725_n51) );
CMPR42X1TS DP_OP_497J314_123_1725_U29 ( .A(DP_OP_497J314_123_1725_n120), .B(
DP_OP_497J314_123_1725_n113), .C(DP_OP_497J314_123_1725_n53), .D(
DP_OP_497J314_123_1725_n196), .ICI(DP_OP_497J314_123_1725_n82), .S(
DP_OP_497J314_123_1725_n49), .ICO(DP_OP_497J314_123_1725_n47), .CO(
DP_OP_497J314_123_1725_n48) );
CMPR42X1TS DP_OP_497J314_123_1725_U28 ( .A(DP_OP_497J314_123_1725_n99), .B(
DP_OP_497J314_123_1725_n106), .C(DP_OP_497J314_123_1725_n54), .D(
DP_OP_497J314_123_1725_n50), .ICI(DP_OP_497J314_123_1725_n49), .S(
DP_OP_497J314_123_1725_n46), .ICO(DP_OP_497J314_123_1725_n44), .CO(
DP_OP_497J314_123_1725_n45) );
CMPR42X1TS DP_OP_497J314_123_1725_U27 ( .A(DP_OP_497J314_123_1725_n119), .B(
DP_OP_497J314_123_1725_n112), .C(DP_OP_497J314_123_1725_n98), .D(
DP_OP_497J314_123_1725_n105), .ICI(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .S(
DP_OP_497J314_123_1725_n43), .ICO(DP_OP_497J314_123_1725_n41), .CO(
DP_OP_497J314_123_1725_n42) );
CMPR42X1TS DP_OP_497J314_123_1725_U26 ( .A(DP_OP_497J314_123_1725_n47), .B(
DP_OP_497J314_123_1725_n81), .C(DP_OP_497J314_123_1725_n44), .D(
DP_OP_497J314_123_1725_n48), .ICI(DP_OP_497J314_123_1725_n43), .S(
DP_OP_497J314_123_1725_n40), .ICO(DP_OP_497J314_123_1725_n38), .CO(
DP_OP_497J314_123_1725_n39) );
CMPR42X1TS DP_OP_497J314_123_1725_U25 ( .A(DP_OP_497J314_123_1725_n111), .B(
DP_OP_497J314_123_1725_n97), .C(DP_OP_497J314_123_1725_n104), .D(
DP_OP_497J314_123_1725_n195), .ICI(DP_OP_497J314_123_1725_n41), .S(
DP_OP_497J314_123_1725_n37), .ICO(DP_OP_497J314_123_1725_n35), .CO(
DP_OP_497J314_123_1725_n36) );
CMPR42X1TS DP_OP_497J314_123_1725_U24 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]), .B(
DP_OP_497J314_123_1725_n80), .C(DP_OP_497J314_123_1725_n42), .D(
DP_OP_497J314_123_1725_n38), .ICI(DP_OP_497J314_123_1725_n37), .S(
DP_OP_497J314_123_1725_n34), .ICO(DP_OP_497J314_123_1725_n32), .CO(
DP_OP_497J314_123_1725_n33) );
CMPR42X1TS DP_OP_497J314_123_1725_U23 ( .A(DP_OP_497J314_123_1725_n110), .B(
DP_OP_497J314_123_1725_n96), .C(DP_OP_497J314_123_1725_n103), .D(
DP_OP_497J314_123_1725_n35), .ICI(DP_OP_497J314_123_1725_n194), .S(
DP_OP_497J314_123_1725_n31), .ICO(DP_OP_497J314_123_1725_n29), .CO(
DP_OP_497J314_123_1725_n30) );
CMPR42X1TS DP_OP_497J314_123_1725_U22 ( .A(DP_OP_497J314_123_1725_n36), .B(
DP_OP_497J314_123_1725_n79), .C(DP_OP_497J314_123_1725_n32), .D(
DP_OP_497J314_123_1725_n31), .ICI(DP_OP_497J314_123_1725_n193), .S(
DP_OP_497J314_123_1725_n28), .ICO(DP_OP_497J314_123_1725_n26), .CO(
DP_OP_497J314_123_1725_n27) );
CMPR42X1TS DP_OP_497J314_123_1725_U20 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[11]), .B(
DP_OP_497J314_123_1725_n25), .C(DP_OP_497J314_123_1725_n78), .D(
DP_OP_497J314_123_1725_n30), .ICI(DP_OP_497J314_123_1725_n26), .S(
DP_OP_497J314_123_1725_n23), .ICO(DP_OP_497J314_123_1725_n21), .CO(
DP_OP_497J314_123_1725_n22) );
CMPR42X1TS DP_OP_497J314_123_1725_U19 ( .A(DP_OP_497J314_123_1725_n94), .B(
DP_OP_497J314_123_1725_n101), .C(DP_OP_497J314_123_1725_n24), .D(
DP_OP_497J314_123_1725_n192), .ICI(DP_OP_497J314_123_1725_n21), .S(
DP_OP_497J314_123_1725_n20), .ICO(DP_OP_497J314_123_1725_n18), .CO(
DP_OP_497J314_123_1725_n19) );
DFFSXLTS R_16 ( .D(n2882), .CK(
FPMULT_Operands_load_reg_XMRegister_net8160881), .SN(n2915), .Q(n2955),
.QN(n2859) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_0_ ( .D(n2761), .CK(
FPSENCOS_ITER_CONT_net8160953), .RN(n2944), .Q(
FPSENCOS_cont_iter_out[0]), .QN(n2761) );
DFFRX2TS FPADDSUB_inst_ShiftRegister_Q_reg_4_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7_5), .CK(
FPADDSUB_inst_ShiftRegister_net8160791), .RN(n2896), .Q(busy), .QN(
n2844) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_2_ ( .D(
FPMULT_FS_Module_state_next[2]), .CK(FPMULT_FS_Module_net8160899),
.RN(n2932), .Q(FPMULT_FS_Module_state_reg[2]), .QN(n2748) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_2_ ( .D(FPSENCOS_ITER_CONT_N4), .CK(
FPSENCOS_ITER_CONT_net8160953), .RN(n2934), .Q(
FPSENCOS_cont_iter_out[2]), .QN(n2747) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_3_ ( .D(FPSENCOS_ITER_CONT_N5), .CK(
FPSENCOS_ITER_CONT_net8160953), .RN(n918), .Q(
FPSENCOS_cont_iter_out[3]), .QN(n2749) );
DFFRX2TS FPMULT_Sel_B_Q_reg_1_ ( .D(n829), .CK(FPMULT_FS_Module_net8160899),
.RN(n2920), .Q(FPMULT_FSM_selector_B[1]), .QN(n2801) );
DFFRX2TS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n810), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8160665), .RN(n913), .Q(
FPADDSUB_ADD_OVRFLW_NRM2) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(FPADDSUB_Raw_mant_SGF[5]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8160665), .RN(n2894), .Q(
FPADDSUB_Raw_mant_NRM_SWR[5]), .QN(n2841) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_0_ ( .D(n843), .CK(clk), .RN(n2944), .Q(
FPSENCOS_cont_var_out[0]), .QN(n2808) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_1_ ( .D(
FPMULT_FS_Module_state_next[1]), .CK(FPMULT_FS_Module_net8160899),
.RN(n2941), .Q(FPMULT_FS_Module_state_reg[1]), .QN(n2750) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(add_subt_data2[12]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2892), .Q(
FPADDSUB_intDY_EWSW[12]), .QN(n2818) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(add_subt_data1[4]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2906), .Q(
FPADDSUB_intDX_EWSW[4]), .QN(n2769) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(add_subt_data2[7]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2894), .Q(
FPADDSUB_intDY_EWSW[7]), .QN(n2845) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(add_subt_data2[5]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n1831), .Q(
FPADDSUB_intDY_EWSW[5]), .QN(n2846) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(add_subt_data2[3]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2895), .Q(
FPADDSUB_intDY_EWSW[3]), .QN(n2872) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(add_subt_data1[16]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2906), .Q(
FPADDSUB_intDX_EWSW[16]), .QN(n2824) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(add_subt_data1[10]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2896), .Q(
FPADDSUB_intDX_EWSW[10]), .QN(n2817) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(add_subt_data1[6]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2892), .Q(
FPADDSUB_intDX_EWSW[6]), .QN(n2822) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(add_subt_data2[15]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2896), .Q(
FPADDSUB_intDY_EWSW[15]), .QN(n2865) );
DFFRX2TS FPADDSUB_inst_ShiftRegister_Q_reg_1_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7[2]), .CK(
FPADDSUB_inst_ShiftRegister_net8160791), .RN(n913), .Q(
FPADDSUB_Shift_reg_FLAGS_7[1]), .QN(n2793) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_0_ ( .D(
FPMULT_FS_Module_state_next[0]), .CK(FPMULT_FS_Module_net8160899),
.RN(n2925), .Q(FPMULT_FS_Module_state_reg[0]), .QN(n996) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(add_subt_data2[23]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n912), .Q(
FPADDSUB_intDY_EWSW[23]), .QN(n2890) );
DFFSX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]), .CK(clk), .SN(n916), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]) );
DFFSX1TS R_19 ( .D(n2880), .CK(clk), .SN(n916), .Q(n2950) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_21_ ( .D(FPADDSUB_Data_array_SWR[21]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8160665), .RN(n2898), .Q(
FPADDSUB_Data_array_SWR[47]), .QN(n2835) );
DFFSX1TS R_6 ( .D(n2886), .CK(clk), .SN(n2945), .Q(n2951) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_0_ ( .D(Data_2[0]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2920), .Q(
FPMULT_Op_MY[0]) );
DFFRX4TS FPMULT_Sel_A_Q_reg_0_ ( .D(1'b1), .CK(n2963), .RN(n2920), .Q(
FPMULT_FSM_selector_A) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_21_ ( .D(Data_2[21]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2920), .Q(
FPMULT_Op_MY[21]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_20_ ( .D(Data_2[20]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2913), .Q(
FPMULT_Op_MY[20]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_8_ ( .D(Data_1[8]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n915), .Q(
FPMULT_Op_MX[8]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_3_ ( .D(Data_2[3]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n915), .Q(
FPMULT_Op_MY[3]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_4_ ( .D(Data_2[4]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2919), .Q(
FPMULT_Op_MY[4]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_7_ ( .D(Data_1[7]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2916), .Q(
FPMULT_Op_MX[7]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_10_ ( .D(Data_1[10]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2913), .Q(
FPMULT_Op_MX[10]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_1_ ( .D(Data_2[1]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2920), .Q(
FPMULT_Op_MY[1]) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_1_ ( .D(n842), .CK(clk), .RN(n2934), .Q(
FPSENCOS_cont_var_out[1]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_17_ ( .D(Data_1[17]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n915), .Q(
FPMULT_Op_MX[17]), .QN(n942) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(
FPADDSUB_Raw_mant_SGF[23]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8160665), .RN(n2901), .Q(FPADDSUB_Raw_mant_NRM_SWR[23]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(
FPADDSUB_Raw_mant_SGF[13]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8160665), .RN(n2906), .Q(FPADDSUB_Raw_mant_NRM_SWR[13]) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]), .CK(clk), .RN(n2944), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[24]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2908), .Q(
FPADDSUB_DmP_mant_SFG_SWR[24]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[20]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2908), .Q(
FPADDSUB_DmP_mant_SFG_SWR[20]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[18]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n1831), .Q(
FPADDSUB_DmP_mant_SFG_SWR[18]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(
FPADDSUB_Raw_mant_SGF[24]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8160665), .RN(n912), .Q(FPADDSUB_Raw_mant_NRM_SWR[24]) );
DFFRX2TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n844), .CK(clk), .RN(n2906), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[22]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2908), .Q(
FPADDSUB_DmP_mant_SFG_SWR[22]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[16]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2891), .Q(
FPADDSUB_DmP_mant_SFG_SWR[16]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[14]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n914), .Q(
FPADDSUB_DmP_mant_SFG_SWR[14]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[12]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2900), .Q(
FPADDSUB_DmP_mant_SFG_SWR[12]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[10]), .CK(
FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n1734), .Q(
FPADDSUB_DmP_mant_SFG_SWR[10]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[8]), .CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2897), .Q(FPADDSUB_DmP_mant_SFG_SWR[8]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[6]), .CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2892), .Q(FPADDSUB_DmP_mant_SFG_SWR[6]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[4]), .CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2896), .Q(FPADDSUB_DmP_mant_SFG_SWR[4]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(
FPADDSUB_Raw_mant_SGF[21]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8160665), .RN(n2897), .Q(FPADDSUB_Raw_mant_NRM_SWR[21]) );
DFFRX2TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(
FPADDSUB_shft_value_mux_o_EWR[3]), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8160665), .RN(n914), .Q(
FPADDSUB_shift_value_SHT2_EWR[3]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(
FPADDSUB_Raw_mant_SGF[16]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8160665), .RN(n2892), .Q(FPADDSUB_Raw_mant_NRM_SWR[16]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(
FPADDSUB_Raw_mant_SGF[10]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8160665), .RN(n2896), .Q(FPADDSUB_Raw_mant_NRM_SWR[10]) );
DFFRX4TS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_1_ ( .D(FPADDSUB_OP_FLAG_SHT2), .CK(
FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2892), .Q(n995), .QN(n2922)
);
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_16_ ( .D(Data_1[16]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2912), .Q(
FPMULT_Op_MX[16]), .QN(n943) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_17_ ( .D(FPADDSUB_Data_array_SWR[17]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8160665), .RN(n2910), .Q(
FPADDSUB_Data_array_SWR[43]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_16_ ( .D(FPADDSUB_Data_array_SWR[16]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8160665), .RN(n2896), .Q(
FPADDSUB_Data_array_SWR[42]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(
FPADDSUB_Raw_mant_SGF[19]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8160665), .RN(n2898), .Q(FPADDSUB_Raw_mant_NRM_SWR[19]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[2]), .CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2906), .Q(FPADDSUB_DmP_mant_SFG_SWR[2]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_18_ ( .D(FPADDSUB_Data_array_SWR[18]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8160665), .RN(n2896), .Q(
FPADDSUB_Data_array_SWR[44]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_19_ ( .D(FPADDSUB_Data_array_SWR[19]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8160665), .RN(n2891), .Q(
FPADDSUB_Data_array_SWR[45]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(FPADDSUB_Raw_mant_SGF[8]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8160665), .RN(n2893), .Q(
FPADDSUB_Raw_mant_NRM_SWR[8]) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]), .CK(clk), .RN(n918), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(add_subt_data1[29]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2910), .Q(
FPADDSUB_intDX_EWSW[29]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_12_ ( .D(Data_1[12]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2914), .Q(
FPMULT_Op_MX[12]), .QN(n938) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(
FPADDSUB_formatted_number_W[7]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8160629), .RN(n2900), .Q(
result_add_subt[7]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(
FPADDSUB_formatted_number_W[6]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8160629), .RN(n2895), .Q(
result_add_subt[6]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(
FPADDSUB_formatted_number_W[3]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8160629), .RN(n914), .Q(
result_add_subt[3]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(
FPADDSUB_formatted_number_W[1]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8160629), .RN(n2902), .Q(
result_add_subt[1]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(
FPADDSUB_formatted_number_W[0]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8160629), .RN(n2903), .Q(
result_add_subt[0]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(
FPADDSUB_formatted_number_W[31]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8160629), .RN(n2910), .Q(
result_add_subt[31]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(
FPADDSUB_formatted_number_W[9]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8160629), .RN(n2909), .Q(
result_add_subt[9]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(
FPADDSUB_formatted_number_W[12]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8160629), .RN(n2902), .Q(
result_add_subt[12]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(
FPADDSUB_formatted_number_W[10]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8160629), .RN(n2896), .Q(
result_add_subt[10]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(
FPADDSUB_formatted_number_W[8]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8160629), .RN(n2892), .Q(
result_add_subt[8]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(
FPADDSUB_formatted_number_W[11]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8160629), .RN(n2897), .Q(
result_add_subt[11]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(
FPADDSUB_formatted_number_W[14]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8160629), .RN(n914), .Q(
result_add_subt[14]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(
FPADDSUB_formatted_number_W[13]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8160629), .RN(n1734), .Q(
result_add_subt[13]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(
FPADDSUB_formatted_number_W[5]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8160629), .RN(n2895), .Q(
result_add_subt[5]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(
FPADDSUB_formatted_number_W[15]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8160629), .RN(n2892), .Q(
result_add_subt[15]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(
FPADDSUB_formatted_number_W[4]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8160629), .RN(n2906), .Q(
result_add_subt[4]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(
FPADDSUB_formatted_number_W[17]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8160629), .RN(n914), .Q(
result_add_subt[17]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(
FPADDSUB_formatted_number_W[20]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8160629), .RN(n1831), .Q(
result_add_subt[20]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(
FPADDSUB_formatted_number_W[18]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8160629), .RN(n2892), .Q(
result_add_subt[18]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(
FPADDSUB_formatted_number_W[16]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8160629), .RN(n2896), .Q(
result_add_subt[16]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(
FPADDSUB_formatted_number_W[2]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8160629), .RN(n914), .Q(
result_add_subt[2]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(
FPADDSUB_formatted_number_W[21]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8160629), .RN(n2892), .Q(
result_add_subt[21]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(
FPADDSUB_formatted_number_W[19]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8160629), .RN(n2893), .Q(
result_add_subt[19]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(
FPADDSUB_formatted_number_W[22]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8160629), .RN(n913), .Q(
result_add_subt[22]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(
FPADDSUB_formatted_number_W[30]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8160629), .RN(n913), .Q(
result_add_subt[30]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(
FPADDSUB_formatted_number_W[29]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8160629), .RN(n2901), .Q(
result_add_subt[29]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(
FPADDSUB_formatted_number_W[28]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8160629), .RN(n912), .Q(
result_add_subt[28]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(
FPADDSUB_formatted_number_W[27]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8160629), .RN(n2901), .Q(
result_add_subt[27]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(
FPADDSUB_formatted_number_W[26]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8160629), .RN(n2894), .Q(
result_add_subt[26]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(
FPADDSUB_formatted_number_W[25]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8160629), .RN(n2910), .Q(
result_add_subt[25]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(
FPADDSUB_formatted_number_W[24]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8160629), .RN(n2909), .Q(
result_add_subt[24]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(
FPADDSUB_formatted_number_W[23]), .CK(
FPADDSUB_FRMT_STAGE_DATAOUT_net8160629), .RN(n2902), .Q(
result_add_subt[23]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_0_ ( .D(Data_1[0]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2920), .Q(
FPMULT_Op_MX[0]) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_11_ ( .D(Data_2[11]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2911), .Q(
FPMULT_Op_MY[11]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(add_subt_data1[25]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2909), .Q(
FPADDSUB_intDX_EWSW[25]), .QN(n951) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(add_subt_data1[26]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2902), .Q(
FPADDSUB_intDX_EWSW[26]), .QN(n952) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_9_ ( .D(FPADDSUB_Data_array_SWR[9]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8160665), .RN(n2892), .Q(
FPADDSUB_Data_array_SWR[35]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(add_subt_data1[19]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n912), .Q(
FPADDSUB_intDX_EWSW[19]), .QN(n949) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_8_ ( .D(FPADDSUB_Data_array_SWR[8]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8160665), .RN(n912), .Q(
FPADDSUB_Data_array_SWR[34]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_11_ ( .D(FPADDSUB_Data_array_SWR[11]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8160665), .RN(n2903), .Q(
FPADDSUB_Data_array_SWR[37]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_10_ ( .D(FPADDSUB_Data_array_SWR[10]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8160665), .RN(n2906), .Q(
FPADDSUB_Data_array_SWR[36]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n1604), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8160665), .RN(n2897), .Q(
FPADDSUB_bit_shift_SHT2) );
DFFRX1TS FPSENCOS_reg_operation_Q_reg_0_ ( .D(n2965), .CK(
FPSENCOS_reg_Z0_net8160917), .RN(n2928), .Q(
FPSENCOS_d_ff1_operation_out) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_29_ ( .D(
FPSENCOS_first_mux_X[29]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2935), .Q(FPSENCOS_d_ff2_X[29]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(add_subt_data1[27]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2903), .Q(
FPADDSUB_intDX_EWSW[27]), .QN(n928) );
DFFRX1TS operation_dff_Q_reg_0_ ( .D(operation[1]), .CK(clk), .RN(n916), .Q(
operation_reg[0]) );
DFFRX1TS operation_dff_Q_reg_1_ ( .D(operation[2]), .CK(clk), .RN(n916), .Q(
operation_reg[1]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n2969), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8160827), .RN(n2912), .Q(
FPMULT_Sgf_normalized_result[2]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(add_subt_data1[22]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2901), .Q(
FPADDSUB_intDX_EWSW[22]), .QN(n911) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n2971), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8160827), .RN(n2914), .Q(
FPMULT_Sgf_normalized_result[4]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n2973), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8160827), .RN(n2917), .Q(
FPMULT_Sgf_normalized_result[6]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n2975), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8160827), .RN(n2915), .Q(
FPMULT_Sgf_normalized_result[8]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n2977), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8160827), .RN(n2918), .Q(
FPMULT_Sgf_normalized_result[10]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n2979), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8160827), .RN(n961), .Q(
FPMULT_Sgf_normalized_result[12]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n2981), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8160827), .RN(n915), .Q(
FPMULT_Sgf_normalized_result[14]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n2983), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8160827), .RN(n2919), .Q(
FPMULT_Sgf_normalized_result[16]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n2985), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8160827), .RN(n2917), .Q(
FPMULT_Sgf_normalized_result[18]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n2987), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8160827), .RN(n2915), .Q(
FPMULT_Sgf_normalized_result[20]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n2989), .CK(
FPMULT_Barrel_Shifter_module_Output_Reg_net8160827), .RN(n2911), .Q(
FPMULT_Sgf_normalized_result[22]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[0]), .CK(FPADDSUB_SGF_STAGE_DMP_net8160683), .RN(n2901), .Q(FPADDSUB_N59) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(FPADDSUB_N59), .CK(
FPADDSUB_NRM_STAGE_Raw_mant_net8160665), .RN(n1734), .Q(
FPADDSUB_Raw_mant_NRM_SWR[0]), .QN(n2877) );
DFFRX1TS FPADDSUB_inst_ShiftRegister_Q_reg_0_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7[1]), .CK(
FPADDSUB_inst_ShiftRegister_net8160791), .RN(n2902), .Q(
FPADDSUB_Shift_reg_FLAGS_7[0]) );
DFFRX1TS FPADDSUB_Ready_reg_Q_reg_0_ ( .D(FPADDSUB_Shift_reg_FLAGS_7[0]),
.CK(clk), .RN(n2909), .Q(ready_add_subt), .QN(n950) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(FPADDSUB_Raw_mant_SGF[4]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8160665), .RN(n2907), .Q(
FPADDSUB_Raw_mant_NRM_SWR[4]) );
DFFRX4TS FPSENCOS_ITER_CONT_temp_reg_1_ ( .D(FPSENCOS_ITER_CONT_N3), .CK(
FPSENCOS_ITER_CONT_net8160953), .RN(n2944), .Q(
FPSENCOS_cont_iter_out[1]), .QN(n2800) );
DFFRX1TS reg_dataB_Q_reg_28_ ( .D(Data_2[28]), .CK(clk), .RN(n2944), .Q(
dataB[28]) );
DFFRX1TS reg_dataB_Q_reg_27_ ( .D(Data_2[27]), .CK(clk), .RN(n2945), .Q(
dataB[27]) );
DFFRX1TS reg_dataB_Q_reg_24_ ( .D(Data_2[24]), .CK(clk), .RN(n918), .Q(
dataB[24]) );
DFFRX1TS reg_dataB_Q_reg_23_ ( .D(Data_2[23]), .CK(clk), .RN(n918), .Q(
dataB[23]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_23_ ( .D(Data_1[23]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n915), .Q(
FPMULT_Op_MX[23]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_26_ ( .D(
FPSENCOS_first_mux_Y[26]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2938), .Q(FPSENCOS_d_ff2_Y[26]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_26_ ( .D(
FPSENCOS_first_mux_X[26]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2933), .Q(FPSENCOS_d_ff2_X[26]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_25_ ( .D(
FPSENCOS_first_mux_X[25]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2935), .Q(FPSENCOS_d_ff2_X[25]) );
DFFSX1TS R_9 ( .D(n2883), .CK(clk), .SN(n2934), .Q(n2948) );
DFFSX1TS R_8 ( .D(n2884), .CK(clk), .SN(n2946), .Q(n2947) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]), .CK(clk), .RN(n2945), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]) );
DFFRX1TS reg_dataA_Q_reg_29_ ( .D(Data_1[29]), .CK(clk), .RN(n917), .Q(
dataA[29]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(add_subt_data1[30]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2898), .Q(
FPADDSUB_intDX_EWSW[30]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_21_ ( .D(Data_1[21]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2919), .Q(
FPMULT_Op_MX[21]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_22_ ( .D(Data_2[22]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2920), .Q(
FPMULT_Op_MY[22]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_19_ ( .D(Data_1[19]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2915), .Q(
FPMULT_Op_MX[19]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_8_ ( .D(Data_2[8]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2920), .Q(
FPMULT_Op_MY[8]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_18_ ( .D(Data_1[18]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n961), .Q(
FPMULT_Op_MX[18]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_2_ ( .D(Data_2[2]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2920), .Q(
FPMULT_Op_MY[2]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_5_ ( .D(Data_2[5]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2920), .Q(
FPMULT_Op_MY[5]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_6_ ( .D(Data_1[6]), .CK(
FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2918), .Q(
FPMULT_Op_MX[6]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_18_ ( .D(Data_2[18]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2912), .Q(
FPMULT_Op_MY[18]) );
ADDFX2TS intadd_1057_U6 ( .A(FPMULT_Op_MY[18]), .B(n986), .CI(intadd_1057_n6), .CO(intadd_1057_n5), .S(intadd_1057_SUM_5_) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(
FPADDSUB_Raw_mant_SGF[11]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8160665), .RN(n2906), .Q(FPADDSUB_Raw_mant_NRM_SWR[11]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_12_ ( .D(Data_2[12]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2914), .Q(
FPMULT_Op_MY[12]), .QN(n923) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(FPADDSUB_Raw_mant_SGF[2]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8160665), .RN(n914), .Q(
FPADDSUB_Raw_mant_NRM_SWR[2]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_17_ ( .D(Data_2[17]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n915), .Q(
FPMULT_Op_MY[17]), .QN(n925) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_13_ ( .D(Data_2[13]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2916), .Q(
FPMULT_Op_MY[13]), .QN(n924) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_13_ ( .D(Data_1[13]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2923), .Q(
FPMULT_Op_MX[13]), .QN(n939) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_15_ ( .D(Data_1[15]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n961), .Q(
FPMULT_Op_MX[15]), .QN(n944) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_15_ ( .D(Data_2[15]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2915), .Q(
FPMULT_Op_MY[15]), .QN(n926) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_13_ ( .D(FPADDSUB_Data_array_SWR[13]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8160665), .RN(n2895), .Q(
FPADDSUB_Data_array_SWR[39]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_12_ ( .D(FPADDSUB_Data_array_SWR[12]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8160665), .RN(n2896), .Q(
FPADDSUB_Data_array_SWR[38]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_14_ ( .D(FPADDSUB_Data_array_SWR[14]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8160665), .RN(n2898), .Q(
FPADDSUB_Data_array_SWR[40]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_15_ ( .D(FPADDSUB_Data_array_SWR[15]), .CK(FPADDSUB_SHT2_SHIFT_DATA_net8160665), .RN(n2909), .Q(
FPADDSUB_Data_array_SWR[41]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(
FPADDSUB_Raw_mant_SGF[15]), .CK(FPADDSUB_NRM_STAGE_Raw_mant_net8160665), .RN(n913), .Q(FPADDSUB_Raw_mant_NRM_SWR[15]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(FPADDSUB_Raw_mant_SGF[9]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8160665), .RN(n912), .Q(
FPADDSUB_Raw_mant_NRM_SWR[9]) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]), .CK(clk), .RN(n2944), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]) );
DFFRX4TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(
FPADDSUB_shft_value_mux_o_EWR[4]), .CK(
FPADDSUB_SHT2_SHIFT_DATA_net8160665), .RN(n2907), .Q(
FPADDSUB_shift_value_SHT2_EWR[4]), .QN(n2811) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n874), .CK(clk), .RN(n2894), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(FPADDSUB_Raw_mant_SGF[7]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8160665), .RN(n2892), .Q(
FPADDSUB_Raw_mant_NRM_SWR[7]) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]), .CK(clk), .RN(n2945), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .QN(n993) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]), .CK(clk), .RN(n2944), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_46_ ( .D(
FPMULT_Sgf_operation_Result[46]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8160845), .RN(n2930), .Q(
FPMULT_P_Sgf[46]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_45_ ( .D(
FPMULT_Sgf_operation_Result[45]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8160845), .RN(n2924), .Q(
FPMULT_P_Sgf[45]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_44_ ( .D(
FPMULT_Sgf_operation_Result[44]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8160845), .RN(n2924), .Q(
FPMULT_P_Sgf[44]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_43_ ( .D(
FPMULT_Sgf_operation_Result[43]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8160845), .RN(n2924), .Q(
FPMULT_P_Sgf[43]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_42_ ( .D(
FPMULT_Sgf_operation_Result[42]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8160845), .RN(n2924), .Q(
FPMULT_P_Sgf[42]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_41_ ( .D(
FPMULT_Sgf_operation_Result[41]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8160845), .RN(n2924), .Q(
FPMULT_P_Sgf[41]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_40_ ( .D(
FPMULT_Sgf_operation_Result[40]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8160845), .RN(n2924), .Q(
FPMULT_P_Sgf[40]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_39_ ( .D(
FPMULT_Sgf_operation_Result[39]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8160845), .RN(n2924), .Q(
FPMULT_P_Sgf[39]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_38_ ( .D(
FPMULT_Sgf_operation_Result[38]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8160845), .RN(n2924), .Q(
FPMULT_P_Sgf[38]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_37_ ( .D(
FPMULT_Sgf_operation_Result[37]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8160845), .RN(n2924), .Q(
FPMULT_P_Sgf[37]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_36_ ( .D(
FPMULT_Sgf_operation_Result[36]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8160845), .RN(n2924), .Q(
FPMULT_P_Sgf[36]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_35_ ( .D(
FPMULT_Sgf_operation_Result[35]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8160845), .RN(n2924), .Q(
FPMULT_P_Sgf[35]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_29_ ( .D(
FPMULT_Sgf_operation_Result[29]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8160845), .RN(n917), .Q(
FPMULT_P_Sgf[29]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_30_ ( .D(
FPMULT_Sgf_operation_Result[30]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8160845), .RN(n1729), .Q(
FPMULT_P_Sgf[30]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_31_ ( .D(
FPMULT_Sgf_operation_Result[31]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8160845), .RN(n917), .Q(
FPMULT_P_Sgf[31]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_32_ ( .D(
FPMULT_Sgf_operation_Result[32]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8160845), .RN(n2936), .Q(
FPMULT_P_Sgf[32]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_33_ ( .D(
FPMULT_Sgf_operation_Result[33]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8160845), .RN(n2943), .Q(
FPMULT_P_Sgf[33]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_34_ ( .D(
FPMULT_Sgf_operation_Result[34]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8160845), .RN(n1733), .Q(
FPMULT_P_Sgf[34]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_24_ ( .D(
FPSENCOS_first_mux_Y[24]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n1733), .Q(FPSENCOS_d_ff2_Y[24]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_24_ ( .D(
FPSENCOS_first_mux_X[24]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2938), .Q(FPSENCOS_d_ff2_X[24]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_25_ ( .D(
FPSENCOS_first_mux_Y[25]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2933), .Q(FPSENCOS_d_ff2_Y[25]) );
DFFRX1TS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_2_ ( .D(n2960), .CK(
FPADDSUB_NRM_STAGE_Raw_mant_net8160665), .RN(n913), .Q(
FPADDSUB_ADD_OVRFLW_NRM) );
DFFRX1TS reg_dataB_Q_reg_30_ ( .D(Data_2[30]), .CK(clk), .RN(n2944), .Q(
dataB[30]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_6_ ( .D(FPADDSUB_Data_array_SWR[6]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8160665), .RN(n2910), .Q(
FPADDSUB_Data_array_SWR[32]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(
FPMULT_Adder_M_result_A_adder[22]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8160809), .RN(n915), .Q(
FPMULT_Add_result[22]) );
DFFRX1TS reg_dataA_Q_reg_30_ ( .D(Data_1[30]), .CK(clk), .RN(n1729), .Q(
dataA[30]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_5_ ( .D(FPADDSUB_Data_array_SWR[5]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8160665), .RN(n2910), .Q(
FPADDSUB_Data_array_SWR[31]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_7_ ( .D(FPADDSUB_Data_array_SWR[7]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8160665), .RN(n2897), .Q(
FPADDSUB_Data_array_SWR[33]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_4_ ( .D(FPADDSUB_Data_array_SWR[4]),
.CK(FPADDSUB_SHT2_SHIFT_DATA_net8160665), .RN(n2897), .Q(
FPADDSUB_Data_array_SWR[30]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(
FPMULT_Adder_M_result_A_adder[23]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8160809), .RN(n2916), .Q(
FPMULT_Add_result[23]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(
FPMULT_Adder_M_result_A_adder[21]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8160809), .RN(n2923), .Q(
FPMULT_Add_result[21]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(
FPMULT_Adder_M_result_A_adder[20]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8160809), .RN(n2916), .Q(
FPMULT_Add_result[20]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(
FPMULT_Adder_M_result_A_adder[19]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8160809), .RN(n915), .Q(
FPMULT_Add_result[19]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(
FPMULT_Adder_M_result_A_adder[18]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8160809), .RN(n2911), .Q(
FPMULT_Add_result[18]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(
FPMULT_Adder_M_result_A_adder[17]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8160809), .RN(n2915), .Q(
FPMULT_Add_result[17]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(
FPMULT_Adder_M_result_A_adder[16]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8160809), .RN(n2923), .Q(
FPMULT_Add_result[16]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(
FPMULT_Adder_M_result_A_adder[15]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8160809), .RN(n2918), .Q(
FPMULT_Add_result[15]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(
FPMULT_Adder_M_result_A_adder[14]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8160809), .RN(n2914), .Q(
FPMULT_Add_result[14]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(
FPMULT_Adder_M_result_A_adder[13]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8160809), .RN(n2912), .Q(
FPMULT_Add_result[13]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(
FPMULT_Adder_M_result_A_adder[12]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8160809), .RN(n2913), .Q(
FPMULT_Add_result[12]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(
FPMULT_Adder_M_result_A_adder[11]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8160809), .RN(n2916), .Q(
FPMULT_Add_result[11]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(
FPMULT_Adder_M_result_A_adder[10]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8160809), .RN(n915), .Q(
FPMULT_Add_result[10]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(
FPMULT_Adder_M_result_A_adder[9]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8160809), .RN(n2911), .Q(
FPMULT_Add_result[9]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(
FPMULT_Adder_M_result_A_adder[8]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8160809), .RN(n2911), .Q(
FPMULT_Add_result[8]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(
FPMULT_Adder_M_result_A_adder[7]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8160809), .RN(n961), .Q(
FPMULT_Add_result[7]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(
FPMULT_Adder_M_result_A_adder[6]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8160809), .RN(n2919), .Q(
FPMULT_Add_result[6]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(
FPMULT_Adder_M_result_A_adder[5]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8160809), .RN(n2918), .Q(
FPMULT_Add_result[5]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(
FPMULT_Adder_M_result_A_adder[4]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8160809), .RN(n2915), .Q(
FPMULT_Add_result[4]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(
FPMULT_Adder_M_result_A_adder[3]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8160809), .RN(n2923), .Q(
FPMULT_Add_result[3]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(
FPMULT_Adder_M_result_A_adder[2]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8160809), .RN(n2914), .Q(
FPMULT_Add_result[2]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(
FPMULT_Adder_M_result_A_adder[1]), .CK(
FPMULT_Adder_M_Add_Subt_Result_net8160809), .RN(n2912), .Q(
FPMULT_Add_result[1]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_28_ ( .D(
FPMULT_Sgf_operation_Result[28]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8160845), .RN(n917), .Q(
FPMULT_P_Sgf[28]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_27_ ( .D(
FPMULT_Sgf_operation_Result[27]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8160845), .RN(n1729), .Q(
FPMULT_P_Sgf[27]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_26_ ( .D(
FPMULT_Sgf_operation_Result[26]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8160845), .RN(n917), .Q(
FPMULT_P_Sgf[26]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_24_ ( .D(
FPMULT_Sgf_operation_Result[24]), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8160845), .RN(n2936), .Q(
FPMULT_P_Sgf[24]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_30_ ( .D(Data_1[30]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n915), .Q(
FPMULT_Op_MX[30]) );
DFFRX1TS reg_dataA_Q_reg_28_ ( .D(Data_1[28]), .CK(clk), .RN(n917), .Q(
dataA[28]) );
DFFRX1TS reg_dataA_Q_reg_23_ ( .D(Data_1[23]), .CK(clk), .RN(n917), .Q(
dataA[23]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_28_ ( .D(Data_1[28]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2915), .Q(
FPMULT_Op_MX[28]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_24_ ( .D(Data_1[24]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n915), .Q(
FPMULT_Op_MX[24]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_29_ ( .D(Data_1[29]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2911), .Q(
FPMULT_Op_MX[29]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_25_ ( .D(Data_1[25]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2919), .Q(
FPMULT_Op_MX[25]) );
DFFSXLTS R_4 ( .D(n2887), .CK(FPMULT_Sgf_operation_EVEN1_finalreg_net8160845), .SN(n916), .Q(n2954) );
DFFRX1TS R_20 ( .D(n2879), .CK(clk), .RN(n916), .Q(n2949) );
DFFSXLTS R_21 ( .D(n2878), .CK(
FPMULT_Sgf_operation_EVEN1_finalreg_net8160845), .SN(n916), .Q(n2953)
);
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_23_ ( .D(
FPSENCOS_first_mux_X[23]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2938), .Q(FPSENCOS_d_ff2_X[23]), .QN(n2834) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_23_ ( .D(
FPSENCOS_first_mux_Y[23]), .CK(FPSENCOS_reg_val_muxZ_2stage_net8160917), .RN(n2933), .Q(FPSENCOS_d_ff2_Y[23]), .QN(n2833) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(FPADDSUB_Raw_mant_SGF[3]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8160665), .RN(n2901), .Q(
FPADDSUB_Raw_mant_NRM_SWR[3]), .QN(n2794) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(FPADDSUB_Raw_mant_SGF[1]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8160665), .RN(n2894), .Q(
FPADDSUB_Raw_mant_NRM_SWR[1]), .QN(n2797) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(FPADDSUB_Raw_mant_SGF[6]),
.CK(FPADDSUB_NRM_STAGE_Raw_mant_net8160665), .RN(n2897), .Q(
FPADDSUB_Raw_mant_NRM_SWR[6]), .QN(n2792) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_26_ ( .D(FPADDSUB_DMP_INIT_EWSW[26]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2897), .Q(
FPADDSUB_DMP_EXP_EWSW[26]), .QN(n2876) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_25_ ( .D(FPADDSUB_DMP_INIT_EWSW[25]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n1734), .Q(
FPADDSUB_DMP_EXP_EWSW[25]), .QN(n2860) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_24_ ( .D(FPADDSUB_DMP_INIT_EWSW[24]),
.CK(FPADDSUB_EXP_STAGE_DMP_net8160683), .RN(n2907), .Q(
FPADDSUB_DMP_EXP_EWSW[24]), .QN(n2861) );
DFFRXLTS FPMULT_Exp_module_Underflow_m_Q_reg_0_ ( .D(n2962), .CK(n2963),
.RN(n2920), .Q(underflow_flag_mult), .QN(n2862) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(add_subt_data2[30]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n1734), .QN(n2889)
);
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(add_subt_data2[22]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2892), .Q(
FPADDSUB_intDY_EWSW[22]), .QN(n2776) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(add_subt_data2[29]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2891), .QN(n2888)
);
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(add_subt_data1[28]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2901), .Q(
FPADDSUB_intDX_EWSW[28]), .QN(n2812) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(add_subt_data1[23]),
.CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629), .RN(n2894), .Q(
FPADDSUB_intDX_EWSW[23]), .QN(n2839) );
ADDFX1TS intadd_1061_U4 ( .A(n2800), .B(FPSENCOS_d_ff2_X[24]), .CI(
intadd_1061_CI), .CO(intadd_1061_n3), .S(FPSENCOS_sh_exp_x[1]) );
ADDFX1TS intadd_1061_U3 ( .A(FPSENCOS_d_ff2_X[25]), .B(n2747), .CI(
intadd_1061_n3), .CO(intadd_1061_n2), .S(FPSENCOS_sh_exp_x[2]) );
ADDFX1TS intadd_1062_U3 ( .A(FPSENCOS_d_ff2_Y[25]), .B(n2747), .CI(
intadd_1062_n3), .CO(intadd_1062_n2), .S(FPSENCOS_sh_exp_y[2]) );
ADDFX1TS intadd_1062_U2 ( .A(FPSENCOS_d_ff2_Y[26]), .B(n2749), .CI(
intadd_1062_n2), .CO(intadd_1062_n1), .S(FPSENCOS_sh_exp_y[3]) );
ADDFX1TS intadd_1061_U2 ( .A(FPSENCOS_d_ff2_X[26]), .B(n2749), .CI(
intadd_1061_n2), .CO(intadd_1061_n1), .S(FPSENCOS_sh_exp_x[3]) );
ADDFX1TS intadd_1060_U2 ( .A(intadd_1057_SUM_4_), .B(intadd_1060_B_4_), .CI(
intadd_1060_n2), .CO(intadd_1060_n1), .S(intadd_1060_SUM_4_) );
DFFSXLTS R_17 ( .D(n2881), .CK(FPADDSUB_INPUT_STAGE_OPERANDY_net8160629),
.SN(n2897), .Q(n2956) );
CMPR32X2TS intadd_1057_U11 ( .A(FPMULT_Op_MY[13]), .B(FPMULT_Op_MY[1]), .C(
intadd_1057_CI), .CO(intadd_1057_n10), .S(intadd_1057_SUM_0_) );
CMPR32X2TS intadd_1056_U11 ( .A(FPMULT_Op_MX[13]), .B(n978), .C(
intadd_1056_CI), .CO(intadd_1056_n10), .S(intadd_1059_A_0_) );
CMPR32X2TS intadd_1057_U10 ( .A(n970), .B(FPMULT_Op_MY[2]), .C(
intadd_1057_n10), .CO(intadd_1057_n9), .S(intadd_1057_SUM_1_) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_11_ ( .D(Data_1[11]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2914), .Q(
FPMULT_Op_MX[11]) );
CMPR32X2TS intadd_1057_U9 ( .A(FPMULT_Op_MY[15]), .B(FPMULT_Op_MY[3]), .C(
intadd_1057_n9), .CO(intadd_1057_n8), .S(intadd_1057_SUM_2_) );
CMPR32X2TS intadd_1057_U8 ( .A(n971), .B(FPMULT_Op_MY[4]), .C(intadd_1057_n8), .CO(intadd_1057_n7), .S(intadd_1057_SUM_3_) );
CMPR32X2TS intadd_1057_U7 ( .A(FPMULT_Op_MY[17]), .B(FPMULT_Op_MY[5]), .C(
intadd_1057_n7), .CO(intadd_1057_n6), .S(intadd_1057_SUM_4_) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_19_ ( .D(Data_2[19]),
.CK(FPMULT_Operands_load_reg_XMRegister_net8160881), .RN(n2919), .Q(
FPMULT_Op_MY[19]) );
CMPR32X2TS intadd_1056_U5 ( .A(FPMULT_Op_MX[19]), .B(FPMULT_Op_MX[7]), .C(
intadd_1056_n5), .CO(intadd_1056_n4), .S(intadd_1056_SUM_6_) );
CMPR32X2TS intadd_1058_U10 ( .A(intadd_1058_A_0_), .B(intadd_1058_B_0_), .C(
intadd_1058_CI), .CO(intadd_1058_n9), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]) );
INVX8TS U1399 ( .A(n1732), .Y(n1831) );
CMPR32X2TS U1400 ( .A(n1235), .B(n1489), .C(n1234), .CO(n1230), .S(n1692) );
CMPR32X2TS U1401 ( .A(n2070), .B(n2188), .C(n2069), .CO(
DP_OP_496J314_122_3540_n274), .S(intadd_1058_A_1_) );
CMPR32X2TS U1402 ( .A(DP_OP_497J314_123_1725_n87), .B(n2231), .C(n1080),
.CO(n1223), .S(n1229) );
CMPR32X2TS U1403 ( .A(n1239), .B(n1727), .C(n1084), .CO(n1233), .S(n2030) );
OAI32X4TS U1404 ( .A0(n1083), .A1(n1727), .A2(DP_OP_496J314_122_3540_n412),
.B0(n1082), .B1(n1083), .Y(n2234) );
CMPR32X2TS U1405 ( .A(n971), .B(FPMULT_Op_MY[22]), .C(n1348), .CO(n1347),
.S(n1369) );
CMPR32X2TS U1406 ( .A(FPMULT_Op_MY[15]), .B(FPMULT_Op_MY[21]), .C(n1350),
.CO(n1348), .S(n1371) );
CMPR32X2TS U1407 ( .A(n970), .B(FPMULT_Op_MY[20]), .C(n1352), .CO(n1350),
.S(n1380) );
CMPR32X2TS U1408 ( .A(FPMULT_Op_MY[13]), .B(FPMULT_Op_MY[19]), .C(n1244),
.CO(n1352), .S(n1382) );
CMPR32X2TS U1409 ( .A(FPMULT_Op_MY[5]), .B(FPMULT_Op_MY[11]), .C(n1447),
.CO(n1465), .S(n1467) );
CMPR32X2TS U1410 ( .A(FPMULT_Op_MY[2]), .B(FPMULT_Op_MY[8]), .C(n1452), .CO(
n1450), .S(n1485) );
NOR2XLTS U1411 ( .A(n2207), .B(n2214), .Y(n2205) );
NOR2XLTS U1412 ( .A(n2251), .B(n2239), .Y(n2237) );
NOR2XLTS U1413 ( .A(n2248), .B(n2239), .Y(intadd_1058_B_0_) );
AOI222X2TS U1414 ( .A0(FPADDSUB_DMP_SFG[8]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[10]), .B0(FPADDSUB_DMP_SFG[8]), .B1(n1937),
.C0(FPADDSUB_DmP_mant_SFG_SWR[10]), .C1(n1937), .Y(n2488) );
AOI222X2TS U1415 ( .A0(FPADDSUB_DMP_SFG[20]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[22]), .B0(FPADDSUB_DMP_SFG[20]), .B1(n2134),
.C0(FPADDSUB_DmP_mant_SFG_SWR[22]), .C1(n2134), .Y(n2519) );
ADDFX1TS U1416 ( .A(n1297), .B(n1330), .CI(n1296), .CO(n1298), .S(
FPMULT_Sgf_operation_Result[28]) );
ADDFX1TS U1417 ( .A(n1303), .B(n1394), .CI(n1302), .CO(n1296), .S(
FPMULT_Sgf_operation_Result[27]) );
ADDFX1TS U1418 ( .A(n1301), .B(n1386), .CI(n1300), .CO(n1302), .S(
FPMULT_Sgf_operation_Result[26]) );
ADDFX1TS U1419 ( .A(n1320), .B(n1319), .CI(n1318), .CO(n1300), .S(
FPMULT_Sgf_operation_Result[25]) );
ADDFX1TS U1420 ( .A(n1292), .B(n1291), .CI(n1290), .CO(n1318), .S(
FPMULT_Sgf_operation_Result[24]) );
CLKBUFX3TS U1421 ( .A(n2065), .Y(n2200) );
CLKINVX6TS U1422 ( .A(n2021), .Y(n1932) );
INVX4TS U1423 ( .A(n1987), .Y(n1941) );
ADDFX1TS U1424 ( .A(n2244), .B(n2255), .CI(n2243), .CO(
DP_OP_496J314_122_3540_n258), .S(DP_OP_496J314_122_3540_n259) );
OR2X2TS U1425 ( .A(n988), .B(n989), .Y(n987) );
ADDFX1TS U1426 ( .A(n2245), .B(n2237), .CI(n2236), .CO(
DP_OP_496J314_122_3540_n253), .S(DP_OP_496J314_122_3540_n254) );
NOR3X1TS U1427 ( .A(n2223), .B(n2225), .C(n2231), .Y(n2229) );
OAI22X1TS U1428 ( .A0(n2267), .A1(n2260), .B0(n2261), .B1(n2258), .Y(
DP_OP_496J314_122_3540_n370) );
CLKINVX6TS U1429 ( .A(n2357), .Y(n2539) );
CLKBUFX3TS U1430 ( .A(n1620), .Y(n2273) );
CLKBUFX3TS U1431 ( .A(n1097), .Y(n1407) );
CLKBUFX3TS U1432 ( .A(n1445), .Y(n1503) );
ADDFX1TS U1433 ( .A(n1151), .B(n1489), .CI(n1150), .CO(n1189), .S(n1147) );
BUFX6TS U1434 ( .A(n2897), .Y(n912) );
CLKBUFX3TS U1435 ( .A(n1458), .Y(n1518) );
CLKBUFX3TS U1436 ( .A(n1358), .Y(n1433) );
BUFX6TS U1437 ( .A(n1831), .Y(n2901) );
BUFX6TS U1438 ( .A(n1831), .Y(n2892) );
BUFX6TS U1439 ( .A(n1831), .Y(n2894) );
BUFX6TS U1440 ( .A(n1734), .Y(n913) );
INVX3TS U1441 ( .A(intadd_1059_A_2_), .Y(n2276) );
BUFX6TS U1442 ( .A(n1831), .Y(n914) );
INVX3TS U1443 ( .A(n1496), .Y(n1500) );
ADDFX1TS U1444 ( .A(n982), .B(FPMULT_Op_MX[10]), .CI(n1444), .CO(n1154), .S(
n1446) );
INVX3TS U1445 ( .A(n1400), .Y(n1404) );
BUFX6TS U1446 ( .A(n2923), .Y(n915) );
ADDFX1TS U1447 ( .A(n979), .B(FPMULT_Op_MX[8]), .CI(n1457), .CO(n1443), .S(
n1459) );
NOR2X4TS U1448 ( .A(n1898), .B(n1762), .Y(n1753) );
NAND2X4TS U1449 ( .A(n1898), .B(n2811), .Y(n1738) );
CLKINVX6TS U1450 ( .A(n2143), .Y(n1604) );
OR2X6TS U1451 ( .A(FPSENCOS_cont_iter_out[2]), .B(n2453), .Y(n2552) );
NAND2X4TS U1452 ( .A(n2862), .B(n2452), .Y(n1833) );
NAND2X4TS U1453 ( .A(n1894), .B(n2811), .Y(n1749) );
OR2X2TS U1454 ( .A(FPADDSUB_ADD_OVRFLW_NRM), .B(n1963), .Y(n1943) );
NOR2X4TS U1455 ( .A(n1894), .B(n1762), .Y(n1746) );
ADDHX2TS U1456 ( .A(n986), .B(FPMULT_Op_MY[0]), .CO(n1155), .S(n1504) );
NOR2X6TS U1457 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n1781), .Y(n1740)
);
CLKINVX3TS U1458 ( .A(n1793), .Y(n1742) );
NOR2X6TS U1459 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n1757), .Y(n1743)
);
BUFX4TS U1460 ( .A(n2946), .Y(n1733) );
INVX2TS U1461 ( .A(n931), .Y(n986) );
NOR2X4TS U1462 ( .A(n2659), .B(n2569), .Y(n1814) );
ADDHX2TS U1463 ( .A(FPMULT_Op_MY[12]), .B(FPMULT_Op_MY[18]), .CO(n1244), .S(
n1403) );
ADDHX2TS U1464 ( .A(FPMULT_Op_MX[12]), .B(FPMULT_Op_MX[18]), .CO(n1093), .S(
n1383) );
ADDHX2TS U1465 ( .A(FPMULT_Op_MX[0]), .B(FPMULT_Op_MX[6]), .CO(n1153), .S(
n1488) );
INVX4TS U1466 ( .A(n2711), .Y(n1672) );
NOR2X2TS U1467 ( .A(n2659), .B(operation[2]), .Y(n1669) );
BUFX6TS U1468 ( .A(n1728), .Y(n2936) );
BUFX6TS U1469 ( .A(n2943), .Y(n916) );
NOR2X1TS U1470 ( .A(operation[1]), .B(operation[2]), .Y(n1670) );
BUFX6TS U1471 ( .A(n1728), .Y(n917) );
BUFX6TS U1472 ( .A(n1731), .Y(n918) );
NOR2XLTS U1473 ( .A(n2218), .B(n2220), .Y(n1664) );
NOR2XLTS U1474 ( .A(n2218), .B(n2208), .Y(n2209) );
NOR2XLTS U1475 ( .A(n2213), .B(n2208), .Y(n2204) );
AO22XLTS U1476 ( .A0(n2273), .A1(n2269), .B0(n2271), .B1(n2272), .Y(
DP_OP_496J314_122_3540_n399) );
AOI2BB2XLTS U1477 ( .B0(intadd_1057_SUM_5_), .B1(n2090), .A0N(n2087), .A1N(
intadd_1057_SUM_5_), .Y(n2064) );
AO22XLTS U1478 ( .A0(n2273), .A1(n2272), .B0(n2271), .B1(n2270), .Y(
DP_OP_496J314_122_3540_n400) );
INVX2TS U1479 ( .A(n987), .Y(intadd_1060_B_3_) );
NOR2XLTS U1480 ( .A(n2218), .B(n2222), .Y(n2219) );
NOR2XLTS U1481 ( .A(n2071), .B(n2201), .Y(DP_OP_496J314_122_3540_n151) );
NOR2XLTS U1482 ( .A(n2225), .B(n2200), .Y(DP_OP_496J314_122_3540_n158) );
NOR2XLTS U1483 ( .A(n2218), .B(n2214), .Y(n2215) );
NOR2XLTS U1484 ( .A(n2225), .B(n2201), .Y(DP_OP_496J314_122_3540_n150) );
NOR2XLTS U1485 ( .A(n2251), .B(n2250), .Y(n2252) );
NOR2XLTS U1486 ( .A(n2249), .B(n2248), .Y(n2253) );
NOR2XLTS U1487 ( .A(n2200), .B(n2214), .Y(DP_OP_496J314_122_3540_n155) );
NOR2XLTS U1488 ( .A(n2218), .B(n2140), .Y(DP_OP_496J314_122_3540_n176) );
NOR2XLTS U1489 ( .A(n2251), .B(n2242), .Y(n2243) );
CLKAND2X2TS U1490 ( .A(n976), .B(n981), .Y(n1538) );
CLKAND2X2TS U1491 ( .A(n986), .B(FPMULT_Op_MX[10]), .Y(n1537) );
CLKAND2X2TS U1492 ( .A(n976), .B(FPMULT_Op_MX[10]), .Y(n1548) );
CLKAND2X2TS U1493 ( .A(FPMULT_Op_MX[11]), .B(n986), .Y(n1547) );
CLKAND2X2TS U1494 ( .A(FPMULT_Op_MY[11]), .B(FPMULT_Op_MX[6]), .Y(n1525) );
CLKAND2X2TS U1495 ( .A(n977), .B(FPMULT_Op_MX[8]), .Y(n1524) );
CLKAND2X2TS U1496 ( .A(FPMULT_Op_MY[8]), .B(n981), .Y(n1526) );
CLKAND2X2TS U1497 ( .A(FPMULT_Op_MY[8]), .B(FPMULT_Op_MX[10]), .Y(n1546) );
CLKAND2X2TS U1498 ( .A(FPMULT_Op_MX[11]), .B(n976), .Y(n1545) );
CLKAND2X2TS U1499 ( .A(FPMULT_Op_MY[11]), .B(FPMULT_Op_MX[7]), .Y(n1528) );
CLKAND2X2TS U1500 ( .A(n975), .B(FPMULT_Op_MX[8]), .Y(n1527) );
CLKAND2X2TS U1501 ( .A(n977), .B(n981), .Y(n1529) );
CLKAND2X2TS U1502 ( .A(n976), .B(FPMULT_Op_MX[8]), .Y(n1533) );
CLKAND2X2TS U1503 ( .A(n986), .B(n981), .Y(n1532) );
CLKAND2X2TS U1504 ( .A(FPMULT_Op_MY[8]), .B(FPMULT_Op_MX[7]), .Y(n1001) );
CLKAND2X2TS U1505 ( .A(n977), .B(FPMULT_Op_MX[6]), .Y(n1000) );
CLKAND2X2TS U1506 ( .A(FPMULT_Op_MY[8]), .B(FPMULT_Op_MX[8]), .Y(
DP_OP_498J314_124_1725_n360) );
CLKAND2X2TS U1507 ( .A(n977), .B(FPMULT_Op_MX[7]), .Y(
DP_OP_498J314_124_1725_n365) );
CLKAND2X2TS U1508 ( .A(n975), .B(FPMULT_Op_MX[6]), .Y(
DP_OP_498J314_124_1725_n370) );
INVX2TS U1509 ( .A(n1580), .Y(intadd_1056_CI) );
NOR2XLTS U1510 ( .A(n1523), .B(n1522), .Y(DP_OP_498J314_124_1725_n100) );
NOR2XLTS U1511 ( .A(n2223), .B(n2222), .Y(n2227) );
CLKAND2X2TS U1512 ( .A(FPMULT_Op_MY[11]), .B(FPMULT_Op_MX[8]), .Y(n1510) );
CLKAND2X2TS U1513 ( .A(n977), .B(FPMULT_Op_MX[10]), .Y(n1509) );
CLKAND2X2TS U1514 ( .A(FPMULT_Op_MX[11]), .B(FPMULT_Op_MY[8]), .Y(n1511) );
AO22XLTS U1515 ( .A0(n2273), .A1(n2266), .B0(n2271), .B1(n2269), .Y(
DP_OP_496J314_122_3540_n398) );
NOR2XLTS U1516 ( .A(n2072), .B(n2208), .Y(DP_OP_496J314_122_3540_n202) );
OAI21XLTS U1517 ( .A0(intadd_1056_SUM_5_), .A1(intadd_1059_n1), .B0(n2201),
.Y(n2065) );
NOR2XLTS U1518 ( .A(n1384), .B(n1433), .Y(DP_OP_497J314_123_1725_n118) );
NOR2XLTS U1519 ( .A(n926), .B(n943), .Y(n1335) );
NOR2XLTS U1520 ( .A(n942), .B(n1397), .Y(n1337) );
NOR2XLTS U1521 ( .A(n1397), .B(n943), .Y(n1399) );
NOR2XLTS U1522 ( .A(n926), .B(n944), .Y(n1340) );
NOR2XLTS U1523 ( .A(n1420), .B(n972), .Y(n1338) );
NOR2XLTS U1524 ( .A(n2250), .B(n2241), .Y(n2070) );
NOR2XLTS U1525 ( .A(n2248), .B(n2240), .Y(n2069) );
NOR2XLTS U1526 ( .A(n2249), .B(n2238), .Y(n2236) );
NOR2XLTS U1527 ( .A(n1412), .B(n1384), .Y(DP_OP_497J314_123_1725_n100) );
CLKAND2X2TS U1528 ( .A(n984), .B(FPMULT_Op_MY[18]), .Y(n1428) );
CLKAND2X2TS U1529 ( .A(FPMULT_Op_MY[19]), .B(FPMULT_Op_MX[21]), .Y(n1429) );
CLKAND2X2TS U1530 ( .A(FPMULT_Op_MY[20]), .B(FPMULT_Op_MX[21]), .Y(n1417) );
CLKAND2X2TS U1531 ( .A(FPMULT_Op_MY[22]), .B(FPMULT_Op_MX[19]), .Y(n1418) );
CLKAND2X2TS U1532 ( .A(n984), .B(FPMULT_Op_MY[19]), .Y(n1419) );
CLKAND2X2TS U1533 ( .A(FPMULT_Op_MY[21]), .B(FPMULT_Op_MX[21]), .Y(n1423) );
CLKAND2X2TS U1534 ( .A(FPMULT_Op_MY[22]), .B(n985), .Y(n1421) );
CLKAND2X2TS U1535 ( .A(n984), .B(FPMULT_Op_MY[20]), .Y(n1422) );
CLKAND2X2TS U1536 ( .A(n984), .B(FPMULT_Op_MY[21]), .Y(n1346) );
CLKAND2X2TS U1537 ( .A(n975), .B(n981), .Y(DP_OP_498J314_124_1725_n352) );
CLKAND2X2TS U1538 ( .A(n975), .B(FPMULT_Op_MX[7]), .Y(
DP_OP_498J314_124_1725_n364) );
CLKAND2X2TS U1539 ( .A(FPMULT_Op_MY[3]), .B(n982), .Y(n1512) );
CLKAND2X2TS U1540 ( .A(n974), .B(FPMULT_Op_MY[2]), .Y(n1514) );
CLKAND2X2TS U1541 ( .A(FPMULT_Op_MY[5]), .B(n979), .Y(n1513) );
CLKAND2X2TS U1542 ( .A(n974), .B(FPMULT_Op_MY[1]), .Y(n1539) );
CLKAND2X2TS U1543 ( .A(FPMULT_Op_MY[2]), .B(n982), .Y(n1540) );
CLKAND2X2TS U1544 ( .A(FPMULT_Op_MY[4]), .B(n979), .Y(n1506) );
CLKAND2X2TS U1545 ( .A(FPMULT_Op_MY[3]), .B(n983), .Y(n1508) );
CLKAND2X2TS U1546 ( .A(FPMULT_Op_MY[5]), .B(n978), .Y(n1507) );
INVX2TS U1547 ( .A(n2187), .Y(intadd_1057_CI) );
CLKAND2X2TS U1548 ( .A(FPMULT_Op_MY[8]), .B(FPMULT_Op_MX[6]), .Y(n1003) );
CLKAND2X2TS U1549 ( .A(n976), .B(FPMULT_Op_MX[7]), .Y(n1002) );
AO22XLTS U1550 ( .A0(n2273), .A1(n2264), .B0(n2271), .B1(n2266), .Y(
DP_OP_496J314_122_3540_n397) );
AO22XLTS U1551 ( .A0(n2273), .A1(n2262), .B0(n2271), .B1(n2264), .Y(
DP_OP_496J314_122_3540_n396) );
CLKAND2X2TS U1552 ( .A(n975), .B(FPMULT_Op_MX[10]), .Y(
DP_OP_498J314_124_1725_n346) );
CLKAND2X2TS U1553 ( .A(FPMULT_Op_MY[11]), .B(n981), .Y(
DP_OP_498J314_124_1725_n351) );
CLKAND2X2TS U1554 ( .A(FPMULT_Op_MX[11]), .B(n977), .Y(
DP_OP_498J314_124_1725_n341) );
CLKAND2X2TS U1555 ( .A(n976), .B(FPMULT_Op_MX[6]), .Y(n1018) );
CLKAND2X2TS U1556 ( .A(n986), .B(FPMULT_Op_MX[7]), .Y(n1019) );
NOR2XLTS U1557 ( .A(n2191), .B(n2248), .Y(intadd_1058_B_2_) );
NOR2XLTS U1558 ( .A(n923), .B(n943), .Y(n1415) );
NOR2XLTS U1559 ( .A(n924), .B(n944), .Y(n1416) );
NOR2XLTS U1560 ( .A(n1397), .B(n944), .Y(n1343) );
NOR2XLTS U1561 ( .A(n942), .B(n923), .Y(n1344) );
NOR2XLTS U1562 ( .A(n924), .B(n943), .Y(n1345) );
AOI2BB2XLTS U1563 ( .B0(n1245), .B1(FPMULT_Op_MX[17]), .A0N(FPMULT_Op_MX[17]), .A1N(n1245), .Y(n1094) );
NOR2XLTS U1564 ( .A(n942), .B(n1420), .Y(n1104) );
CLKAND2X2TS U1565 ( .A(FPMULT_Op_MY[20]), .B(FPMULT_Op_MX[18]), .Y(n1013) );
CLKAND2X2TS U1566 ( .A(FPMULT_Op_MY[19]), .B(FPMULT_Op_MX[19]), .Y(n1012) );
CLKAND2X2TS U1567 ( .A(FPMULT_Op_MY[18]), .B(FPMULT_Op_MX[21]), .Y(n1424) );
CLKAND2X2TS U1568 ( .A(FPMULT_Op_MY[19]), .B(n985), .Y(n1425) );
CLKAND2X2TS U1569 ( .A(FPMULT_Op_MY[20]), .B(FPMULT_Op_MX[19]), .Y(n1011) );
CLKAND2X2TS U1570 ( .A(FPMULT_Op_MY[21]), .B(FPMULT_Op_MX[18]), .Y(n1010) );
CLKAND2X2TS U1571 ( .A(FPMULT_Op_MY[21]), .B(FPMULT_Op_MX[19]), .Y(
DP_OP_497J314_123_1725_n364) );
CLKAND2X2TS U1572 ( .A(FPMULT_Op_MY[22]), .B(FPMULT_Op_MX[18]), .Y(
DP_OP_497J314_123_1725_n369) );
CLKAND2X2TS U1573 ( .A(FPMULT_Op_MY[20]), .B(n985), .Y(
DP_OP_497J314_123_1725_n359) );
CLKAND2X2TS U1574 ( .A(FPMULT_Op_MY[21]), .B(n985), .Y(
DP_OP_497J314_123_1725_n358) );
CLKAND2X2TS U1575 ( .A(FPMULT_Op_MY[22]), .B(FPMULT_Op_MX[21]), .Y(
DP_OP_497J314_123_1725_n351) );
CLKAND2X2TS U1576 ( .A(FPMULT_Op_MY[22]), .B(n984), .Y(
DP_OP_497J314_123_1725_n345) );
CLKAND2X2TS U1577 ( .A(FPMULT_Op_MY[5]), .B(FPMULT_Op_MX[0]), .Y(n1535) );
CLKAND2X2TS U1578 ( .A(FPMULT_Op_MY[3]), .B(n979), .Y(n1534) );
CLKAND2X2TS U1579 ( .A(FPMULT_Op_MY[2]), .B(n983), .Y(n1536) );
CLKAND2X2TS U1580 ( .A(n974), .B(FPMULT_Op_MY[0]), .Y(n1543) );
CLKAND2X2TS U1581 ( .A(FPMULT_Op_MY[1]), .B(n982), .Y(n1544) );
CLKAND2X2TS U1582 ( .A(FPMULT_Op_MY[0]), .B(n982), .Y(n1541) );
CLKAND2X2TS U1583 ( .A(FPMULT_Op_MY[1]), .B(n983), .Y(n1542) );
CLKAND2X2TS U1584 ( .A(FPMULT_Op_MY[4]), .B(n982), .Y(
DP_OP_498J314_124_1725_n255) );
CLKAND2X2TS U1585 ( .A(n974), .B(FPMULT_Op_MY[3]), .Y(
DP_OP_498J314_124_1725_n250) );
CLKAND2X2TS U1586 ( .A(FPMULT_Op_MY[5]), .B(n983), .Y(
DP_OP_498J314_124_1725_n260) );
CLKAND2X2TS U1587 ( .A(FPMULT_Op_MY[4]), .B(n983), .Y(
DP_OP_498J314_124_1725_n261) );
CLKAND2X2TS U1588 ( .A(n974), .B(FPMULT_Op_MY[4]), .Y(n1180) );
CLKAND2X2TS U1589 ( .A(FPMULT_Op_MY[5]), .B(n982), .Y(n1179) );
CLKAND2X2TS U1590 ( .A(n986), .B(FPMULT_Op_MX[8]), .Y(n1173) );
NAND2BXLTS U1591 ( .AN(FPADDSUB_intDX_EWSW[19]), .B(FPADDSUB_intDY_EWSW[19]),
.Y(n2340) );
NAND2BXLTS U1592 ( .AN(FPADDSUB_intDX_EWSW[27]), .B(FPADDSUB_intDY_EWSW[27]),
.Y(n2294) );
CLKAND2X2TS U1593 ( .A(FPMULT_Op_MY[11]), .B(FPMULT_Op_MX[10]), .Y(n1005) );
CLKAND2X2TS U1594 ( .A(FPMULT_Op_MX[11]), .B(n975), .Y(n1006) );
OAI21XLTS U1595 ( .A0(n2274), .A1(n2258), .B0(n2075), .Y(n2074) );
NOR2XLTS U1596 ( .A(n924), .B(n939), .Y(n1041) );
NOR2XLTS U1597 ( .A(n1397), .B(n938), .Y(n1042) );
NOR2XLTS U1598 ( .A(n923), .B(n944), .Y(n1426) );
NOR2XLTS U1599 ( .A(n924), .B(n940), .Y(n1427) );
NOR2XLTS U1600 ( .A(n926), .B(n938), .Y(n1037) );
NOR2XLTS U1601 ( .A(n1397), .B(n939), .Y(n1038) );
NOR2XLTS U1602 ( .A(n1384), .B(n1031), .Y(n1044) );
NOR2XLTS U1603 ( .A(n942), .B(n925), .Y(n1108) );
CLKAND2X2TS U1604 ( .A(FPMULT_Op_MY[18]), .B(FPMULT_Op_MX[19]), .Y(n1033) );
CLKAND2X2TS U1605 ( .A(FPMULT_Op_MY[19]), .B(FPMULT_Op_MX[18]), .Y(n1032) );
NOR2XLTS U1606 ( .A(n2251), .B(n2191), .Y(n2193) );
CLKAND2X2TS U1607 ( .A(FPMULT_Op_MY[18]), .B(n985), .Y(n1263) );
CLKAND2X2TS U1608 ( .A(FPMULT_Op_MY[1]), .B(n979), .Y(n1531) );
CLKAND2X2TS U1609 ( .A(FPMULT_Op_MY[0]), .B(n983), .Y(n1530) );
CLKAND2X2TS U1610 ( .A(FPMULT_Op_MY[4]), .B(n978), .Y(
DP_OP_498J314_124_1725_n273) );
CLKAND2X2TS U1611 ( .A(FPMULT_Op_MY[4]), .B(FPMULT_Op_MX[0]), .Y(
DP_OP_498J314_124_1725_n279) );
CLKAND2X2TS U1612 ( .A(FPMULT_Op_MY[3]), .B(n978), .Y(
DP_OP_498J314_124_1725_n274) );
CLKAND2X2TS U1613 ( .A(FPMULT_Op_MY[2]), .B(n979), .Y(
DP_OP_498J314_124_1725_n269) );
CLKAND2X2TS U1614 ( .A(FPMULT_Op_MY[3]), .B(FPMULT_Op_MX[0]), .Y(n1023) );
CLKAND2X2TS U1615 ( .A(FPMULT_Op_MY[2]), .B(n978), .Y(n1024) );
NOR2XLTS U1616 ( .A(n1523), .B(n1017), .Y(n1030) );
CLKAND2X2TS U1617 ( .A(FPMULT_Op_MY[2]), .B(FPMULT_Op_MX[0]), .Y(n1028) );
CLKAND2X2TS U1618 ( .A(FPMULT_Op_MY[1]), .B(n978), .Y(n1027) );
NAND2BXLTS U1619 ( .AN(n2234), .B(n1319), .Y(n1228) );
NAND2BXLTS U1620 ( .AN(n965), .B(FPADDSUB_intDY_EWSW[24]), .Y(n2349) );
CLKAND2X2TS U1621 ( .A(FPMULT_Op_MY[11]), .B(FPMULT_Op_MX[11]), .Y(n1145) );
NOR2XLTS U1622 ( .A(n923), .B(n972), .Y(n1073) );
AOI222X4TS U1623 ( .A0(FPADDSUB_DMP_SFG[2]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[4]), .B0(FPADDSUB_DMP_SFG[2]), .B1(n1854),
.C0(FPADDSUB_DmP_mant_SFG_SWR[4]), .C1(n1854), .Y(n1868) );
OAI211X1TS U1624 ( .A0(n2811), .A1(n960), .B0(n1760), .C0(n1759), .Y(n1787)
);
AOI211X1TS U1625 ( .A0(n1743), .A1(FPADDSUB_Data_array_SWR[45]), .B0(n1795),
.C0(n1768), .Y(n1807) );
AOI211X1TS U1626 ( .A0(FPADDSUB_Data_array_SWR[44]), .A1(n1743), .B0(n1795),
.C0(n1764), .Y(n1802) );
CLKAND2X2TS U1627 ( .A(FPMULT_Op_MY[1]), .B(FPMULT_Op_MX[0]), .Y(n1025) );
CLKAND2X2TS U1628 ( .A(FPMULT_Op_MY[0]), .B(n978), .Y(n1026) );
CLKAND2X2TS U1629 ( .A(FPMULT_Op_MY[0]), .B(n979), .Y(n1078) );
AO21XLTS U1630 ( .A0(n1783), .A1(FPADDSUB_Data_array_SWR[51]), .B0(n1779),
.Y(n948) );
NAND2BXLTS U1631 ( .AN(FPADDSUB_Raw_mant_NRM_SWR[23]), .B(n2762), .Y(n1609)
);
AOI222X4TS U1632 ( .A0(n1963), .A1(FPADDSUB_DmP_mant_SHT1_SW[1]), .B0(n1959),
.B1(FPADDSUB_Raw_mant_NRM_SWR[22]), .C0(FPADDSUB_Raw_mant_NRM_SWR[3]),
.C1(n1604), .Y(n1979) );
AOI222X4TS U1633 ( .A0(n1963), .A1(FPADDSUB_DmP_mant_SHT1_SW[0]), .B0(n1959),
.B1(FPADDSUB_Raw_mant_NRM_SWR[23]), .C0(FPADDSUB_Raw_mant_NRM_SWR[2]),
.C1(n1604), .Y(n1989) );
OAI211XLTS U1634 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(
n2838), .B0(n2716), .C0(n2451), .Y(n875) );
ADDHXLTS U1635 ( .A(n1570), .B(n1295), .CO(n1322), .S(
FPMULT_Sgf_operation_Result[38]) );
AO22XLTS U1636 ( .A0(n2921), .A1(FPADDSUB_LZD_raw_out_EWR[4]), .B0(
FPADDSUB_Shift_amount_SHT1_EWR[4]), .B1(n1963), .Y(
FPADDSUB_shft_value_mux_o_EWR[4]) );
AO22XLTS U1637 ( .A0(n2921), .A1(FPADDSUB_LZD_raw_out_EWR[3]), .B0(
FPADDSUB_Shift_amount_SHT1_EWR[3]), .B1(n1963), .Y(
FPADDSUB_shft_value_mux_o_EWR[3]) );
OAI31X1TS U1638 ( .A0(n2719), .A1(FPSENCOS_cont_var_out[1]), .A2(n2808),
.B0(n2144), .Y(n842) );
AO22XLTS U1639 ( .A0(n2921), .A1(FPADDSUB_LZD_raw_out_EWR[2]), .B0(
FPADDSUB_Shift_amount_SHT1_EWR[2]), .B1(n1963), .Y(
FPADDSUB_shft_value_mux_o_EWR[2]) );
XOR2XLTS U1640 ( .A(n1286), .B(n1553), .Y(FPMULT_Sgf_operation_Result[47])
);
NAND2BXLTS U1641 ( .AN(FPADDSUB_intDX_EWSW[30]), .B(n2889), .Y(
FPADDSUB_DMP_INIT_EWSW[30]) );
OR4X2TS U1642 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .C(n1730), .D(n2806), .Y(
n927) );
OAI221X1TS U1643 ( .A0(n2820), .A1(FPADDSUB_intDY_EWSW[1]), .B0(n2770), .B1(
FPADDSUB_intDY_EWSW[0]), .C0(n2360), .Y(n2363) );
OAI221X1TS U1644 ( .A0(n2821), .A1(FPADDSUB_intDY_EWSW[17]), .B0(n2824),
.B1(FPADDSUB_intDY_EWSW[16]), .C0(n2368), .Y(n2371) );
INVX2TS U1645 ( .A(n947), .Y(n958) );
OAI21X1TS U1646 ( .A0(n1781), .A1(n2831), .B0(n1780), .Y(n1750) );
OAI21X1TS U1647 ( .A0(n1781), .A1(n2832), .B0(n1780), .Y(n1782) );
ADDHX1TS U1648 ( .A(n1521), .B(n1520), .CO(DP_OP_498J314_124_1725_n61), .S(
DP_OP_498J314_124_1725_n62) );
ADDHX1TS U1649 ( .A(FPMULT_Op_MY[19]), .B(FPMULT_Op_MX[19]), .CO(
DP_OP_497J314_123_1725_n319), .S(DP_OP_497J314_123_1725_n320) );
INVX2TS U1650 ( .A(n956), .Y(n959) );
AOI221X4TS U1651 ( .A0(FPADDSUB_intDX_EWSW[30]), .A1(n2889), .B0(
FPADDSUB_intDX_EWSW[29]), .B1(n2888), .C0(n2299), .Y(n2301) );
NOR4X2TS U1652 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .Y(n1811) );
NOR2X2TS U1653 ( .A(n1780), .B(n2815), .Y(n1765) );
INVX2TS U1654 ( .A(n948), .Y(n960) );
NOR2X2TS U1655 ( .A(n2802), .B(n1612), .Y(n2116) );
NOR2X2TS U1656 ( .A(n2181), .B(n2185), .Y(n2180) );
NOR2X2TS U1657 ( .A(n2178), .B(n2179), .Y(n2177) );
NOR2X2TS U1658 ( .A(n2175), .B(n2176), .Y(n2174) );
NOR2X2TS U1659 ( .A(n2172), .B(n2173), .Y(n2171) );
NOR2X2TS U1660 ( .A(n2169), .B(n2170), .Y(n2168) );
NOR2X2TS U1661 ( .A(n2166), .B(n2167), .Y(n2165) );
NOR2X2TS U1662 ( .A(n2163), .B(n2164), .Y(n2162) );
NOR2X2TS U1663 ( .A(n2160), .B(n2161), .Y(n2159) );
NOR2X2TS U1664 ( .A(n2157), .B(n2158), .Y(n2156) );
NAND3X2TS U1665 ( .A(n2749), .B(n2761), .C(n2800), .Y(n2453) );
BUFX4TS U1666 ( .A(n1731), .Y(n2943) );
BUFX4TS U1667 ( .A(n916), .Y(n2932) );
BUFX4TS U1668 ( .A(n916), .Y(n2940) );
BUFX4TS U1669 ( .A(n2936), .Y(n2929) );
BUFX4TS U1670 ( .A(n917), .Y(n2934) );
BUFX4TS U1671 ( .A(n2945), .Y(n2930) );
NOR4X1TS U1672 ( .A(n986), .B(FPMULT_Op_MY[19]), .C(n976), .D(
FPMULT_Op_MY[20]), .Y(n2721) );
NOR4X1TS U1673 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MX[19]), .C(
FPMULT_Op_MX[7]), .D(n985), .Y(n2729) );
NOR4X1TS U1674 ( .A(FPMULT_Op_MX[8]), .B(FPMULT_Op_MX[21]), .C(n981), .D(
n984), .Y(n2730) );
NOR4X1TS U1675 ( .A(FPMULT_Op_MY[8]), .B(FPMULT_Op_MY[21]), .C(n977), .D(
FPMULT_Op_MY[22]), .Y(n2722) );
BUFX6TS U1676 ( .A(n1733), .Y(n2925) );
BUFX4TS U1677 ( .A(n2898), .Y(n2905) );
BUFX4TS U1678 ( .A(n2895), .Y(n2904) );
NOR2XLTS U1679 ( .A(FPMULT_FSM_selector_C), .B(n2399), .Y(n2400) );
NOR2XLTS U1680 ( .A(n2837), .B(n2399), .Y(n2396) );
OAI21X2TS U1681 ( .A0(FPMULT_FS_Module_state_reg[2]), .A1(
FPMULT_FSM_add_overflow_flag), .B0(n996), .Y(n2399) );
BUFX4TS U1682 ( .A(n2925), .Y(n2933) );
BUFX4TS U1683 ( .A(n2925), .Y(n2935) );
BUFX4TS U1684 ( .A(n2925), .Y(n2938) );
BUFX4TS U1685 ( .A(n2925), .Y(n2941) );
NOR4X1TS U1686 ( .A(n982), .B(FPMULT_Op_MX[17]), .C(n974), .D(
FPMULT_Op_MX[18]), .Y(n2732) );
OAI211X1TS U1687 ( .A0(n2811), .A1(n1865), .B0(n1772), .C0(n1771), .Y(n1804)
);
AOI21X2TS U1688 ( .A0(n1783), .A1(FPADDSUB_Data_array_SWR[50]), .B0(n1779),
.Y(n1865) );
NOR4X2TS U1689 ( .A(n2250), .B(n2248), .C(n2235), .D(n2242), .Y(
intadd_1058_CI) );
NOR4X2TS U1690 ( .A(n2240), .B(n2241), .C(n2235), .D(n2249), .Y(n2245) );
NOR4X2TS U1691 ( .A(n2241), .B(n2240), .C(n2239), .D(n2238), .Y(n2255) );
NAND2X4TS U1692 ( .A(intadd_1059_A_4_), .B(intadd_1056_SUM_5_), .Y(n2258) );
BUFX4TS U1693 ( .A(n2909), .Y(n2908) );
OAI211X1TS U1694 ( .A0(n2811), .A1(n1879), .B0(n1878), .C0(n1877), .Y(n1897)
);
AOI21X2TS U1695 ( .A0(n1783), .A1(FPADDSUB_Data_array_SWR[49]), .B0(n1779),
.Y(n1879) );
NOR2X2TS U1696 ( .A(n2282), .B(n2259), .Y(n1727) );
NOR2X2TS U1697 ( .A(n2182), .B(n2183), .Y(n2186) );
AOI21X2TS U1698 ( .A0(FPADDSUB_Data_array_SWR[48]), .A1(n1783), .B0(n1779),
.Y(n1891) );
BUFX3TS U1699 ( .A(n1737), .Y(n1783) );
AOI21X2TS U1700 ( .A0(n1783), .A1(FPADDSUB_Data_array_SWR[46]), .B0(n1774),
.Y(n1883) );
OAI21X1TS U1701 ( .A0(n1781), .A1(n2772), .B0(n1780), .Y(n1774) );
AOI21X2TS U1702 ( .A0(n1783), .A1(FPADDSUB_Data_array_SWR[47]), .B0(n1775),
.Y(n1887) );
OAI21X1TS U1703 ( .A0(n1781), .A1(n1790), .B0(n1780), .Y(n1775) );
BUFX3TS U1704 ( .A(n2923), .Y(n961) );
BUFX4TS U1705 ( .A(n2923), .Y(n2915) );
BUFX4TS U1706 ( .A(n2923), .Y(n2917) );
BUFX4TS U1707 ( .A(n2936), .Y(n2944) );
NOR2X4TS U1708 ( .A(n2747), .B(n2749), .Y(n2704) );
AOI211XLTS U1709 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n2824), .B0(n2343),
.C0(n2344), .Y(n2335) );
OAI211X2TS U1710 ( .A0(FPADDSUB_intDX_EWSW[20]), .A1(n2858), .B0(n2367),
.C0(n2334), .Y(n2343) );
NOR2X4TS U1711 ( .A(intadd_1059_A_0_), .B(n2282), .Y(n2090) );
OAI2BB2X4TS U1712 ( .B0(n925), .B1(n1347), .A0N(n1347), .A1N(n925), .Y(n1410) );
CLKINVX3TS U1713 ( .A(FPADDSUB_ADD_OVRFLW_NRM2), .Y(n962) );
CLKINVX6TS U1714 ( .A(n1894), .Y(n1898) );
BUFX6TS U1715 ( .A(FPADDSUB_left_right_SHT2), .Y(n1894) );
NOR3X2TS U1716 ( .A(n2750), .B(n996), .C(n1832), .Y(n107) );
ADDHX1TS U1717 ( .A(n1284), .B(n1283), .CO(n1285), .S(n1551) );
ADDHX1TS U1718 ( .A(n1026), .B(n1025), .CO(n1079), .S(n1718) );
BUFX6TS U1719 ( .A(n1926), .Y(n2546) );
AOI222X4TS U1720 ( .A0(n2751), .A1(n2479), .B0(n2751), .B1(n2777), .C0(n2479), .C1(n2777), .Y(n1854) );
NAND2X1TS U1721 ( .A(FPADDSUB_DMP_SFG[0]), .B(FPADDSUB_DmP_mant_SFG_SWR[2]),
.Y(n2479) );
AOI222X4TS U1722 ( .A0(FPADDSUB_DMP_SFG[18]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[20]), .B0(FPADDSUB_DMP_SFG[18]), .B1(n2060),
.C0(FPADDSUB_DmP_mant_SFG_SWR[20]), .C1(n2060), .Y(n2514) );
AOI222X4TS U1723 ( .A0(n2509), .A1(n2759), .B0(n2509), .B1(n2791), .C0(n2759), .C1(n2791), .Y(n2060) );
AOI222X4TS U1724 ( .A0(n2514), .A1(n2795), .B0(n2514), .B1(n2760), .C0(n2795), .C1(n2760), .Y(n2134) );
BUFX6TS U1725 ( .A(n1831), .Y(n2897) );
BUFX6TS U1726 ( .A(n1831), .Y(n1734) );
NAND2BX1TS U1727 ( .AN(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .Y(n2451) );
NAND2X1TS U1728 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n2838),
.Y(n2716) );
OAI22X2TS U1729 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(
FPADDSUB_Shift_amount_SHT1_EWR[0]), .B0(FPADDSUB_LZD_raw_out_EWR[0]),
.B1(n1943), .Y(n1933) );
INVX2TS U1730 ( .A(n946), .Y(n963) );
AOI211X2TS U1731 ( .A0(n1045), .A1(intadd_1057_SUM_0_), .B0(n2196), .C0(
DP_OP_496J314_122_3540_n412), .Y(n1083) );
BUFX6TS U1732 ( .A(n2649), .Y(n2656) );
INVX2TS U1733 ( .A(n955), .Y(n964) );
INVX2TS U1734 ( .A(n945), .Y(n965) );
OAI21X2TS U1735 ( .A0(n2792), .A1(n2143), .B0(n1952), .Y(n1997) );
OAI21X2TS U1736 ( .A0(n2804), .A1(n2143), .B0(n1955), .Y(n2015) );
INVX4TS U1737 ( .A(n2552), .Y(n2551) );
INVX4TS U1738 ( .A(n2552), .Y(n2550) );
BUFX6TS U1739 ( .A(n1748), .Y(n2548) );
BUFX4TS U1740 ( .A(n1741), .Y(n1888) );
CLKINVX6TS U1741 ( .A(n2539), .Y(n2542) );
CLKINVX6TS U1742 ( .A(n2539), .Y(n2537) );
CLKINVX6TS U1743 ( .A(n2539), .Y(n2538) );
BUFX6TS U1744 ( .A(n2793), .Y(n1963) );
ADDHX1TS U1745 ( .A(n1019), .B(n1018), .CO(n1174), .S(n1489) );
CLKINVX6TS U1746 ( .A(n2552), .Y(n966) );
INVX2TS U1747 ( .A(n2552), .Y(n2554) );
INVX3TS U1748 ( .A(n1943), .Y(n1959) );
INVX3TS U1749 ( .A(n2525), .Y(n2490) );
BUFX6TS U1750 ( .A(n2396), .Y(n2445) );
BUFX6TS U1751 ( .A(n2400), .Y(n2447) );
INVX2TS U1752 ( .A(n927), .Y(n967) );
NOR2X1TS U1753 ( .A(FPADDSUB_Raw_mant_NRM_SWR[9]), .B(
FPADDSUB_Raw_mant_NRM_SWR[8]), .Y(n2125) );
NOR4X1TS U1754 ( .A(FPADDSUB_Raw_mant_NRM_SWR[9]), .B(
FPADDSUB_Raw_mant_NRM_SWR[13]), .C(FPADDSUB_Raw_mant_NRM_SWR[11]), .D(
n2121), .Y(n1649) );
INVX2TS U1755 ( .A(n953), .Y(n968) );
INVX2TS U1756 ( .A(n954), .Y(n969) );
NOR3X1TS U1757 ( .A(FPADDSUB_Raw_mant_NRM_SWR[15]), .B(
FPADDSUB_Raw_mant_NRM_SWR[16]), .C(FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(
n2115) );
ADDHX1TS U1758 ( .A(n1040), .B(n1039), .CO(n1074), .S(n1319) );
NOR4X1TS U1759 ( .A(FPMULT_Op_MY[3]), .B(FPMULT_Op_MY[2]), .C(
FPMULT_Op_MY[15]), .D(n971), .Y(n2723) );
NOR4X1TS U1760 ( .A(n983), .B(n979), .C(FPMULT_Op_MX[15]), .D(
FPMULT_Op_MX[16]), .Y(n2731) );
CMPR32X4TS U1761 ( .A(FPMULT_Op_MX[15]), .B(FPMULT_Op_MX[21]), .C(n1095),
.CO(n1096), .S(n1400) );
NOR4X1TS U1762 ( .A(FPMULT_Op_MX[11]), .B(FPMULT_Op_MX[13]), .C(n978), .D(
n973), .Y(n2734) );
NOR4X1TS U1763 ( .A(FPMULT_Op_MY[11]), .B(FPMULT_Op_MY[13]), .C(
FPMULT_Op_MY[1]), .D(n970), .Y(n2726) );
INVX2TS U1764 ( .A(n932), .Y(n970) );
INVX2TS U1765 ( .A(n936), .Y(n971) );
INVX2TS U1766 ( .A(FPMULT_Op_MX[14]), .Y(n972) );
INVX2TS U1767 ( .A(n972), .Y(n973) );
NOR4X1TS U1768 ( .A(FPMULT_Op_MY[4]), .B(FPMULT_Op_MY[17]), .C(
FPMULT_Op_MY[5]), .D(FPMULT_Op_MY[18]), .Y(n2724) );
NOR3XLTS U1769 ( .A(FPMULT_Op_MY[0]), .B(FPMULT_Op_MY[12]), .C(n975), .Y(
n2727) );
NOR3X1TS U1770 ( .A(FPADDSUB_Raw_mant_NRM_SWR[12]), .B(
FPADDSUB_Raw_mant_NRM_SWR[13]), .C(FPADDSUB_Raw_mant_NRM_SWR[11]), .Y(
n2122) );
INVX2TS U1771 ( .A(n934), .Y(n974) );
INVX2TS U1772 ( .A(n935), .Y(n975) );
INVX2TS U1773 ( .A(n920), .Y(n976) );
INVX2TS U1774 ( .A(n933), .Y(n977) );
INVX2TS U1775 ( .A(n929), .Y(n978) );
INVX2TS U1776 ( .A(n930), .Y(n979) );
INVX2TS U1777 ( .A(n921), .Y(n981) );
INVX2TS U1778 ( .A(n922), .Y(n982) );
INVX2TS U1779 ( .A(n919), .Y(n983) );
ADDFX2TS U1780 ( .A(FPMULT_Op_MX[13]), .B(FPMULT_Op_MX[19]), .CI(n1093),
.CO(n1357), .S(n1379) );
INVX2TS U1781 ( .A(n941), .Y(n984) );
INVX2TS U1782 ( .A(n937), .Y(n985) );
OAI221X1TS U1783 ( .A0(n2889), .A1(FPADDSUB_intDX_EWSW[30]), .B0(n2826),
.B1(FPADDSUB_intDY_EWSW[20]), .C0(n2374), .Y(n2389) );
OAI221X1TS U1784 ( .A0(n2836), .A1(FPADDSUB_intDY_EWSW[5]), .B0(n2769), .B1(
FPADDSUB_intDY_EWSW[4]), .C0(n2366), .Y(n2373) );
NOR2X1TS U1785 ( .A(n2071), .B(n2224), .Y(DP_OP_496J314_122_3540_n191) );
CLKINVX3TS U1786 ( .A(intadd_1059_SUM_1_), .Y(n2224) );
OAI2BB2X1TS U1787 ( .B0(n2281), .B1(n2278), .A0N(n2095), .A1N(n2096), .Y(
DP_OP_496J314_122_3540_n407) );
NOR4X2TS U1788 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .Y(n1666) );
NOR4X1TS U1789 ( .A(Data_2[2]), .B(Data_2[10]), .C(Data_2[12]), .D(
Data_2[14]), .Y(n2884) );
NOR4X1TS U1790 ( .A(Data_2[4]), .B(Data_2[18]), .C(Data_2[20]), .D(Data_2[1]), .Y(n2886) );
NOR4X1TS U1791 ( .A(Data_2[15]), .B(Data_2[19]), .C(Data_2[13]), .D(
Data_2[21]), .Y(n2885) );
NOR4X1TS U1792 ( .A(Data_2[7]), .B(Data_2[9]), .C(Data_2[11]), .D(Data_2[6]),
.Y(n2883) );
NOR4X1TS U1793 ( .A(Data_2[17]), .B(Data_2[16]), .C(Data_2[8]), .D(n1581),
.Y(n2880) );
NOR3X6TS U1794 ( .A(n1658), .B(FPADDSUB_exp_rslt_NRM2_EW1[7]), .C(n1623),
.Y(n2958) );
XNOR2X2TS U1795 ( .A(DP_OP_26J314_126_1325_n1), .B(FPADDSUB_ADD_OVRFLW_NRM2),
.Y(n1658) );
NOR4X1TS U1796 ( .A(FPMULT_Op_MX[23]), .B(FPMULT_Op_MX[25]), .C(
FPMULT_Op_MX[24]), .D(FPMULT_Op_MX[26]), .Y(n2733) );
BUFX4TS U1797 ( .A(n917), .Y(n2945) );
NOR4X2TS U1798 ( .A(n2250), .B(n2235), .C(n2242), .D(n2238), .Y(n2188) );
NOR2X4TS U1799 ( .A(n2761), .B(n2800), .Y(n2666) );
NOR2X2TS U1800 ( .A(n2830), .B(FPMULT_FS_Module_state_reg[2]), .Y(n1834) );
OAI211X2TS U1801 ( .A0(FPADDSUB_intDX_EWSW[12]), .A1(n2818), .B0(n2329),
.C0(n2315), .Y(n2331) );
AOI21X2TS U1802 ( .A0(n1076), .A1(n1075), .B0(intadd_1055_CI), .Y(n2231) );
NOR3X2TS U1803 ( .A(FPADDSUB_Raw_mant_NRM_SWR[5]), .B(
FPADDSUB_Raw_mant_NRM_SWR[4]), .C(n2114), .Y(n2111) );
NOR3X2TS U1804 ( .A(FPMULT_FS_Module_state_reg[1]), .B(
FPMULT_FS_Module_state_reg[0]), .C(n1671), .Y(n2714) );
NOR2X2TS U1805 ( .A(FPMULT_Sgf_normalized_result[4]), .B(n2186), .Y(n2185)
);
NOR3X2TS U1806 ( .A(FPMULT_Sgf_normalized_result[2]), .B(
FPMULT_Sgf_normalized_result[1]), .C(FPMULT_Sgf_normalized_result[0]),
.Y(n2183) );
BUFX6TS U1807 ( .A(n2633), .Y(n2660) );
OAI32X4TS U1808 ( .A0(n994), .A1(FPSENCOS_d_ff1_operation_out), .A2(n963),
.B0(FPSENCOS_d_ff1_shift_region_flag_out_0_), .B1(n2532), .Y(n2533) );
NAND2X4TS U1809 ( .A(intadd_1057_SUM_5_), .B(intadd_1060_n1), .Y(n2140) );
AOI21X2TS U1810 ( .A0(FPSENCOS_cont_iter_out[2]), .A1(n2749), .B0(n1736),
.Y(n1851) );
OAI21X2TS U1811 ( .A0(n1943), .A1(n2794), .B0(n1942), .Y(n2020) );
OAI21X2TS U1812 ( .A0(n2802), .A1(n2143), .B0(n1958), .Y(n2009) );
BUFX4TS U1813 ( .A(n2907), .Y(n2893) );
BUFX4TS U1814 ( .A(n914), .Y(n2910) );
BUFX4TS U1815 ( .A(n1831), .Y(n2909) );
BUFX4TS U1816 ( .A(n2891), .Y(n2898) );
BUFX4TS U1817 ( .A(n2900), .Y(n2902) );
BUFX4TS U1818 ( .A(n2897), .Y(n2903) );
OAI21XLTS U1819 ( .A0(n1373), .A1(n1409), .B0(n1247), .Y(n1246) );
NOR2X4TS U1820 ( .A(FPMULT_Op_MY[17]), .B(n1347), .Y(n1373) );
NOR2XLTS U1821 ( .A(FPMULT_Op_MY[11]), .B(n2251), .Y(n988) );
NOR2XLTS U1822 ( .A(intadd_1057_n1), .B(n2251), .Y(n989) );
NOR2XLTS U1823 ( .A(n2249), .B(n987), .Y(n2192) );
NOR2XLTS U1824 ( .A(n987), .B(n2239), .Y(n2244) );
NOR2XLTS U1825 ( .A(n987), .B(n2250), .Y(DP_OP_496J314_122_3540_n311) );
BUFX4TS U1826 ( .A(n1669), .Y(n2698) );
OAI21X4TS U1827 ( .A0(FPMULT_Op_MX[0]), .A1(FPMULT_Op_MX[12]), .B0(n1580),
.Y(n2282) );
NOR2X4TS U1828 ( .A(n1933), .B(n1945), .Y(n1987) );
NOR2X4TS U1829 ( .A(n1945), .B(n1944), .Y(n2021) );
AOI22X2TS U1830 ( .A0(n1959), .A1(FPADDSUB_LZD_raw_out_EWR[1]), .B0(
FPADDSUB_Shift_amount_SHT1_EWR[1]), .B1(n1963), .Y(n1945) );
OAI221X1TS U1831 ( .A0(n2888), .A1(FPADDSUB_intDX_EWSW[29]), .B0(n2825),
.B1(FPADDSUB_intDY_EWSW[18]), .C0(n2358), .Y(n2365) );
CLKAND2X4TS U1832 ( .A(n1835), .B(n1812), .Y(FPMULT_FSM_exp_operation_A_S)
);
NOR2X2TS U1833 ( .A(n2748), .B(FPMULT_FS_Module_state_reg[3]), .Y(n1835) );
AOI21X2TS U1834 ( .A0(n1783), .A1(FPADDSUB_Data_array_SWR[45]), .B0(n1782),
.Y(n1896) );
AOI21X2TS U1835 ( .A0(n1783), .A1(FPADDSUB_Data_array_SWR[44]), .B0(n1750),
.Y(n1900) );
NOR3BX2TS U1836 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .B(n1665),
.C(n1809), .Y(FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]) );
NOR4BX2TS U1837 ( .AN(n1666), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]),
.C(n1665), .D(n993), .Y(FPSENCOS_enab_RB3) );
AOI222X4TS U1838 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[2]), .A1(n2783), .B0(
FPADDSUB_DmP_mant_SFG_SWR[2]), .B1(n2480), .C0(n2783), .C1(n2480), .Y(
n1847) );
NOR3X1TS U1839 ( .A(FPADDSUB_Raw_mant_NRM_SWR[19]), .B(
FPADDSUB_Raw_mant_NRM_SWR[20]), .C(FPADDSUB_Raw_mant_NRM_SWR[21]), .Y(
n2109) );
NOR2X2TS U1840 ( .A(FPADDSUB_Raw_mant_NRM_SWR[7]), .B(n1606), .Y(n2128) );
AOI211X4TS U1841 ( .A0(FPADDSUB_Data_array_SWR[42]), .A1(n1783), .B0(n1765),
.C0(n1758), .Y(n1859) );
AOI211X4TS U1842 ( .A0(FPADDSUB_Data_array_SWR[43]), .A1(n1783), .B0(n1765),
.C0(n1739), .Y(n1806) );
INVX3TS U1843 ( .A(n2531), .Y(n2556) );
INVX6TS U1844 ( .A(n2552), .Y(n2555) );
BUFX6TS U1845 ( .A(n2395), .Y(n2446) );
BUFX6TS U1846 ( .A(n2398), .Y(n2448) );
INVX6TS U1847 ( .A(n2713), .Y(n2923) );
OAI2BB1X1TS U1848 ( .A0N(FPADDSUB_Raw_mant_NRM_SWR[10]), .A1N(n1604), .B0(
n1949), .Y(n2003) );
NAND2X2TS U1849 ( .A(FPADDSUB_bit_shift_SHT2), .B(
FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n1780) );
NAND3X2TS U1850 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_shift_value_SHT2_EWR[2]), .C(n2811), .Y(n1793) );
OAI32X1TS U1851 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[23]), .A1(
FPADDSUB_Raw_mant_NRM_SWR[21]), .A2(n2805), .B0(n2762), .B1(
FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n1650) );
AOI222X4TS U1852 ( .A0(FPADDSUB_DMP_SFG[4]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[6]), .B0(FPADDSUB_DMP_SFG[4]), .B1(n1874),
.C0(FPADDSUB_DmP_mant_SFG_SWR[6]), .C1(n1874), .Y(n1905) );
AOI222X4TS U1853 ( .A0(FPADDSUB_DMP_SFG[6]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[8]), .B0(FPADDSUB_DMP_SFG[6]), .B1(n1922),
.C0(FPADDSUB_DmP_mant_SFG_SWR[8]), .C1(n1922), .Y(n2483) );
AOI222X4TS U1854 ( .A0(FPADDSUB_DMP_SFG[10]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[12]), .B0(FPADDSUB_DMP_SFG[10]), .B1(n2026),
.C0(FPADDSUB_DmP_mant_SFG_SWR[12]), .C1(n2026), .Y(n2494) );
AOI222X4TS U1855 ( .A0(FPADDSUB_DMP_SFG[12]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[14]), .B0(FPADDSUB_DMP_SFG[12]), .B1(n2041),
.C0(FPADDSUB_DmP_mant_SFG_SWR[14]), .C1(n2041), .Y(n2499) );
AOI222X4TS U1856 ( .A0(FPADDSUB_DMP_SFG[14]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[16]), .B0(FPADDSUB_DMP_SFG[14]), .B1(n2047),
.C0(FPADDSUB_DmP_mant_SFG_SWR[16]), .C1(n2047), .Y(n2504) );
NOR4X2TS U1857 ( .A(FPADDSUB_Raw_mant_NRM_SWR[24]), .B(
FPADDSUB_Raw_mant_NRM_SWR[25]), .C(FPADDSUB_Raw_mant_NRM_SWR[22]), .D(
FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n2106) );
AOI222X4TS U1858 ( .A0(FPADDSUB_DMP_SFG[16]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[18]), .B0(FPADDSUB_DMP_SFG[16]), .B1(n2053),
.C0(FPADDSUB_DmP_mant_SFG_SWR[18]), .C1(n2053), .Y(n2509) );
AOI222X4TS U1859 ( .A0(FPADDSUB_DMP_SFG[22]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[24]), .B0(FPADDSUB_DMP_SFG[22]), .B1(n2526),
.C0(FPADDSUB_DmP_mant_SFG_SWR[24]), .C1(n2526), .Y(n2287) );
NAND2X2TS U1860 ( .A(n1245), .B(FPMULT_Op_MX[17]), .Y(n1409) );
NOR3BX2TS U1861 ( .AN(FPSENCOS_cont_var_out[1]), .B(n950), .C(
FPSENCOS_cont_var_out[0]), .Y(FPSENCOS_enab_d_ff4_Zn) );
ADDFX2TS U1862 ( .A(n978), .B(FPMULT_Op_MX[7]), .CI(n1153), .CO(n1457), .S(
n1484) );
CMPR32X4TS U1863 ( .A(n974), .B(FPMULT_Op_MX[11]), .C(n1154), .CO(n1473),
.S(n1498) );
AOI21X4TS U1864 ( .A0(intadd_1056_n1), .A1(FPMULT_Op_MX[11]), .B0(n2249),
.Y(n2191) );
INVX2TS U1865 ( .A(rst), .Y(n1728) );
NOR2XLTS U1866 ( .A(n2225), .B(n2224), .Y(n2226) );
NOR2XLTS U1867 ( .A(n2223), .B(n2199), .Y(DP_OP_496J314_122_3540_n193) );
NOR2XLTS U1868 ( .A(n2200), .B(n2220), .Y(DP_OP_496J314_122_3540_n156) );
OAI21XLTS U1869 ( .A0(n1477), .A1(n1474), .B0(n1157), .Y(n1156) );
NOR2XLTS U1870 ( .A(intadd_1057_SUM_0_), .B(n2087), .Y(n1081) );
NOR2XLTS U1871 ( .A(n2338), .B(FPADDSUB_intDY_EWSW[16]), .Y(n2339) );
NOR2XLTS U1872 ( .A(n1523), .B(n1518), .Y(DP_OP_498J314_124_1725_n118) );
OAI21XLTS U1873 ( .A0(DP_OP_496J314_122_3540_n412), .A1(n2057), .B0(
intadd_1059_A_2_), .Y(DP_OP_496J314_122_3540_n403) );
NOR2XLTS U1874 ( .A(n942), .B(n924), .Y(n1398) );
OAI21XLTS U1875 ( .A0(FPADDSUB_intDX_EWSW[23]), .A1(n2890), .B0(
FPADDSUB_intDX_EWSW[22]), .Y(n2345) );
NOR2XLTS U1876 ( .A(n926), .B(n972), .Y(n1341) );
INVX2TS U1877 ( .A(rst), .Y(n1731) );
OAI21XLTS U1878 ( .A0(n1793), .A1(n2772), .B0(n1792), .Y(n1794) );
NOR2XLTS U1879 ( .A(FPADDSUB_Raw_mant_NRM_SWR[20]), .B(
FPADDSUB_Raw_mant_NRM_SWR[21]), .Y(n1611) );
OAI21XLTS U1880 ( .A0(n2063), .A1(n2133), .B0(n2062), .Y(n2061) );
OAI21XLTS U1881 ( .A0(n2029), .A1(n2040), .B0(n2028), .Y(n2027) );
INVX2TS U1882 ( .A(FPMULT_Sgf_normalized_result[3]), .Y(n2182) );
OAI21XLTS U1883 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[24]), .A1(n1650), .B0(n2803),
.Y(n1651) );
OAI21XLTS U1884 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[19]), .A1(n2759), .B0(n2511),
.Y(n2512) );
OR2X1TS U1885 ( .A(n107), .B(FPMULT_FSM_load_second_step), .Y(
FPMULT_FSM_exp_operation_load_result) );
NOR3XLTS U1886 ( .A(FPMULT_Exp_module_Data_S[8]), .B(
FPMULT_Exp_module_Data_S[7]), .C(n1912), .Y(n2962) );
OAI31X1TS U1887 ( .A0(FPMULT_FS_Module_state_reg[0]), .A1(
FPMULT_FS_Module_state_reg[2]), .A2(n2750), .B0(n1662), .Y(
FPMULT_FS_Module_state_next[1]) );
OAI211XLTS U1888 ( .A0(n2145), .A1(n997), .B0(n1837), .C0(n2560), .Y(
FPMULT_FS_Module_state_next[3]) );
OAI21XLTS U1889 ( .A0(n2023), .A1(n2546), .B0(n2022), .Y(
FPADDSUB_Data_array_SWR[20]) );
OR2X1TS U1890 ( .A(FPSENCOS_d_ff_Xn[28]), .B(n2550), .Y(
FPSENCOS_first_mux_X[28]) );
NOR2XLTS U1891 ( .A(n2166), .B(n2549), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[15]) );
OR2X1TS U1892 ( .A(FPSENCOS_d_ff_Xn[3]), .B(n1845), .Y(
FPSENCOS_first_mux_X[3]) );
OAI21XLTS U1893 ( .A0(n2011), .A1(n2546), .B0(n2010), .Y(
FPADDSUB_Data_array_SWR[12]) );
OAI21XLTS U1894 ( .A0(n1979), .A1(n2546), .B0(n1978), .Y(
FPADDSUB_Data_array_SWR[3]) );
OAI21XLTS U1895 ( .A0(n2743), .A1(n2874), .B0(n2742), .Y(
FPSENCOS_sh_exp_y[5]) );
OAI21XLTS U1896 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n2834), .B0(
intadd_1061_CI), .Y(FPSENCOS_sh_exp_x[0]) );
OR2X1TS U1897 ( .A(n2958), .B(FPADDSUB_exp_rslt_NRM2_EW1[5]), .Y(
FPADDSUB_formatted_number_W[28]) );
OAI21XLTS U1898 ( .A0(FPADDSUB_DmP_EXP_EWSW[23]), .A1(n992), .B0(n1842), .Y(
FPADDSUB_Shift_amount_EXP_EW[0]) );
INVX4TS U1899 ( .A(n1484), .Y(DP_OP_498J314_124_1725_n119) );
INVX4TS U1900 ( .A(n1379), .Y(DP_OP_497J314_123_1725_n119) );
INVX2TS U1901 ( .A(intadd_1059_A_0_), .Y(DP_OP_496J314_122_3540_n412) );
NAND2X1TS U1902 ( .A(FPMULT_Op_MX[0]), .B(FPMULT_Op_MX[12]), .Y(n1580) );
INVX2TS U1903 ( .A(n2282), .Y(n1045) );
NAND2X2TS U1904 ( .A(intadd_1059_A_0_), .B(n1045), .Y(n2087) );
NAND2X2TS U1905 ( .A(intadd_1059_A_0_), .B(n2282), .Y(n2088) );
OAI22X1TS U1906 ( .A0(intadd_1057_SUM_1_), .A1(n2087), .B0(
intadd_1057_SUM_0_), .B1(n2088), .Y(n998) );
AOI21X1TS U1907 ( .A0(n2090), .A1(intadd_1057_SUM_1_), .B0(n998), .Y(n1075)
);
NAND2X1TS U1908 ( .A(FPMULT_Op_MY[0]), .B(FPMULT_Op_MY[12]), .Y(n2187) );
OAI21X4TS U1909 ( .A0(FPMULT_Op_MY[0]), .A1(FPMULT_Op_MY[12]), .B0(n2187),
.Y(n2259) );
INVX2TS U1910 ( .A(n2259), .Y(n2196) );
INVX2TS U1911 ( .A(intadd_1059_A_1_), .Y(n2057) );
OAI22X4TS U1912 ( .A0(DP_OP_496J314_122_3540_n412), .A1(n2057), .B0(
intadd_1059_A_1_), .B1(intadd_1059_A_0_), .Y(n2281) );
INVX2TS U1913 ( .A(n2281), .Y(n2097) );
AOI21X1TS U1914 ( .A0(n2196), .A1(n2097), .B0(n1083), .Y(n1076) );
NOR2X1TS U1915 ( .A(n1075), .B(n1076), .Y(intadd_1055_CI) );
CMPR32X2TS U1916 ( .A(n1001), .B(n1000), .C(n999), .CO(n1166), .S(n1170) );
ADDHXLTS U1917 ( .A(n1003), .B(n1002), .CO(n999), .S(n1172) );
CMPR32X2TS U1918 ( .A(DP_OP_498J314_124_1725_n308), .B(
DP_OP_498J314_124_1725_n310), .C(n1004), .CO(n1007), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]) );
CMPR32X2TS U1919 ( .A(n1006), .B(n1005), .C(DP_OP_498J314_124_1725_n306),
.CO(n1146), .S(n1008) );
CMPR32X2TS U1920 ( .A(DP_OP_498J314_124_1725_n307), .B(n1008), .C(n1007),
.CO(n1144), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]) );
CMPR32X2TS U1921 ( .A(FPMULT_Op_MY[22]), .B(n984), .C(
DP_OP_497J314_123_1725_n306), .CO(n1241), .S(n1015) );
CMPR32X2TS U1922 ( .A(n1011), .B(n1010), .C(n1009), .CO(n1256), .S(n1260) );
ADDHXLTS U1923 ( .A(n1013), .B(n1012), .CO(n1009), .S(n1262) );
XOR2X1TS U1924 ( .A(n1241), .B(n1240), .Y(DP_OP_497J314_123_1725_n193) );
CMPR32X2TS U1925 ( .A(DP_OP_497J314_123_1725_n307), .B(n1015), .C(n1014),
.CO(n1240), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]) );
CMPR32X2TS U1926 ( .A(DP_OP_497J314_123_1725_n308), .B(
DP_OP_497J314_123_1725_n310), .C(n1016), .CO(n1014), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]) );
AOI21X1TS U1927 ( .A0(n1504), .A1(n1488), .B0(DP_OP_498J314_124_1725_n119),
.Y(n1149) );
NAND2X1TS U1928 ( .A(n986), .B(FPMULT_Op_MX[6]), .Y(n1177) );
NAND2X1TS U1929 ( .A(FPMULT_Op_MY[0]), .B(FPMULT_Op_MX[0]), .Y(n1084) );
INVX2TS U1930 ( .A(n1504), .Y(n1523) );
INVX2TS U1931 ( .A(n1488), .Y(n1017) );
INVX2TS U1932 ( .A(n1718), .Y(n1151) );
NAND2X1TS U1933 ( .A(n1484), .B(n1017), .Y(n1021) );
INVX2TS U1934 ( .A(n1487), .Y(n1476) );
AOI22X1TS U1935 ( .A0(n1487), .A1(DP_OP_498J314_124_1725_n119), .B0(n1484),
.B1(n1476), .Y(n1020) );
OAI22X1TS U1936 ( .A0(n1504), .A1(n1021), .B0(n1020), .B1(n1017), .Y(n1150)
);
CMPR32X2TS U1937 ( .A(n1024), .B(n1023), .C(n1022), .CO(n1062), .S(n1069) );
ADDHXLTS U1938 ( .A(n1028), .B(n1027), .CO(n1022), .S(n1077) );
CMPR32X2TS U1939 ( .A(DP_OP_498J314_124_1725_n225), .B(
DP_OP_498J314_124_1725_n231), .C(n1029), .CO(n1181), .S(n1490) );
CMPR32X2TS U1940 ( .A(n1177), .B(n1084), .C(n1030), .CO(n1148), .S(n1052) );
INVX2TS U1941 ( .A(n1678), .Y(n1050) );
AOI21X1TS U1942 ( .A0(n1403), .A1(n1383), .B0(DP_OP_497J314_123_1725_n119),
.Y(n1090) );
NAND2X1TS U1943 ( .A(FPMULT_Op_MY[18]), .B(FPMULT_Op_MX[18]), .Y(n1100) );
NOR2X1TS U1944 ( .A(n923), .B(n938), .Y(n1291) );
INVX2TS U1945 ( .A(n1403), .Y(n1384) );
INVX2TS U1946 ( .A(n1383), .Y(n1031) );
NOR2X1TS U1947 ( .A(n923), .B(n939), .Y(n1040) );
NOR2X1TS U1948 ( .A(n924), .B(n938), .Y(n1039) );
INVX2TS U1949 ( .A(n1319), .Y(n1092) );
ADDHX1TS U1950 ( .A(n1033), .B(n1032), .CO(n1264), .S(n1385) );
NAND2X1TS U1951 ( .A(n1379), .B(n1031), .Y(n1035) );
INVX2TS U1952 ( .A(n1382), .Y(n1375) );
AOI22X1TS U1953 ( .A0(n1382), .A1(DP_OP_497J314_123_1725_n119), .B0(n1379),
.B1(n1375), .Y(n1034) );
OAI22X1TS U1954 ( .A0(n1403), .A1(n1035), .B0(n1034), .B1(n1031), .Y(n1091)
);
INVX2TS U1955 ( .A(n970), .Y(n1397) );
CMPR32X2TS U1956 ( .A(n1038), .B(n1037), .C(n1036), .CO(n1060), .S(n1066) );
ADDHXLTS U1957 ( .A(n1042), .B(n1041), .CO(n1036), .S(n1072) );
CMPR32X2TS U1958 ( .A(DP_OP_497J314_123_1725_n225), .B(
DP_OP_497J314_123_1725_n231), .C(n1043), .CO(n1105), .S(n1388) );
CMPR32X2TS U1959 ( .A(n1100), .B(n1239), .C(n1044), .CO(n1089), .S(n1051) );
INVX2TS U1960 ( .A(n1314), .Y(n1049) );
NAND2X1TS U1961 ( .A(intadd_1056_SUM_6_), .B(n2196), .Y(n1047) );
NAND2X1TS U1962 ( .A(intadd_1057_SUM_6_), .B(n1045), .Y(n1046) );
XOR2X1TS U1963 ( .A(n1047), .B(n1046), .Y(n1578) );
CMPR32X2TS U1964 ( .A(n1050), .B(n1049), .C(n1048), .CO(n1200), .S(n1204) );
ADDHX1TS U1965 ( .A(n1388), .B(n1051), .CO(n1116), .S(n1311) );
INVX2TS U1966 ( .A(n1311), .Y(n1054) );
ADDHX1TS U1967 ( .A(n1490), .B(n1052), .CO(n1192), .S(n1675) );
INVX2TS U1968 ( .A(n1675), .Y(n1053) );
CMPR32X2TS U1969 ( .A(n1054), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[6]), .C(n1053), .CO(n1203), .S(n1209) );
CMPR32X2TS U1970 ( .A(DP_OP_497J314_123_1725_n232), .B(
DP_OP_497J314_123_1725_n238), .C(n1055), .CO(n1043), .S(n1331) );
INVX2TS U1971 ( .A(n1331), .Y(n1058) );
CMPR32X2TS U1972 ( .A(DP_OP_498J314_124_1725_n232), .B(
DP_OP_498J314_124_1725_n238), .C(n1056), .CO(n1029), .S(n1710) );
INVX2TS U1973 ( .A(n1710), .Y(n1057) );
CMPR32X2TS U1974 ( .A(n1058), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[5]), .C(n1057), .CO(n1208), .S(n1214) );
CMPR32X2TS U1975 ( .A(DP_OP_497J314_123_1725_n239), .B(n1060), .C(n1059),
.CO(n1055), .S(n1330) );
INVX2TS U1976 ( .A(n1330), .Y(n1063) );
CMPR32X2TS U1977 ( .A(DP_OP_498J314_124_1725_n239), .B(n1062), .C(n1061),
.CO(n1056), .S(n1721) );
CMPR32X2TS U1978 ( .A(n1063), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[4]), .C(n1440), .CO(n1213), .S(n1219) );
CMPR32X2TS U1979 ( .A(n1066), .B(n1065), .C(n1064), .CO(n1059), .S(n1394) );
INVX2TS U1980 ( .A(n1394), .Y(n1071) );
CMPR32X2TS U1981 ( .A(n1069), .B(n1068), .C(n1067), .CO(n1061), .S(n1711) );
INVX2TS U1982 ( .A(n1711), .Y(n1070) );
CMPR32X2TS U1983 ( .A(n1071), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[3]), .C(n1070), .CO(n1218), .S(n1224) );
CMPR32X2TS U1984 ( .A(n1074), .B(n1073), .C(n1072), .CO(n1064), .S(n1386) );
CMPR32X2TS U1985 ( .A(n1079), .B(n1078), .C(n1077), .CO(n1067), .S(n2038) );
INVX2TS U1986 ( .A(n2038), .Y(n1080) );
AOI21X1TS U1987 ( .A0(n2090), .A1(intadd_1057_SUM_0_), .B0(n1081), .Y(n1082)
);
INVX2TS U1988 ( .A(n1291), .Y(n1239) );
INVX2TS U1989 ( .A(n1084), .Y(n1708) );
XOR2X1TS U1990 ( .A(n2234), .B(n1319), .Y(n1232) );
ADDHXLTS U1991 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[10]), .B(
DP_OP_499J314_125_1651_n31), .CO(n1085), .S(n1119) );
XNOR2X1TS U1992 ( .A(n1086), .B(n1085), .Y(n1087) );
XOR2X1TS U1993 ( .A(intadd_1058_n1), .B(n1087), .Y(n1282) );
CMPR32X2TS U1994 ( .A(n1090), .B(n1089), .C(n1088), .CO(n1114), .S(n1117) );
CMPR32X2TS U1995 ( .A(n1092), .B(n1385), .C(n1091), .CO(n1113), .S(n1088) );
BUFX3TS U1996 ( .A(n1094), .Y(n1408) );
CMPR32X2TS U1997 ( .A(FPMULT_Op_MX[16]), .B(n984), .C(n1096), .CO(n1245),
.S(n1098) );
INVX2TS U1998 ( .A(n1098), .Y(n1377) );
AOI22X1TS U1999 ( .A0(n1400), .A1(n1377), .B0(n1098), .B1(n1404), .Y(n1097)
);
INVX2TS U2000 ( .A(n1408), .Y(n1376) );
OAI221X4TS U2001 ( .A0(n1098), .A1(n1376), .B0(n1377), .B1(n1408), .C0(n1407), .Y(n1405) );
OAI32X1TS U2002 ( .A0(n1408), .A1(n1403), .A2(n1407), .B0(n1405), .B1(n1408),
.Y(n1101) );
CMPR32X2TS U2003 ( .A(DP_OP_497J314_123_1725_n52), .B(
DP_OP_497J314_123_1725_n57), .C(n1099), .CO(n1242), .S(n1122) );
INVX2TS U2004 ( .A(n1100), .Y(n1121) );
CMPR32X2TS U2005 ( .A(n1102), .B(n1101), .C(DP_OP_497J314_123_1725_n58),
.CO(n1099), .S(n1125) );
INVX2TS U2006 ( .A(n971), .Y(n1420) );
NOR2X1TS U2007 ( .A(n925), .B(n943), .Y(n1103) );
CMPR32X2TS U2008 ( .A(n1104), .B(n1103), .C(DP_OP_497J314_123_1725_n215),
.CO(n1109), .S(n1112) );
CMPR32X2TS U2009 ( .A(DP_OP_497J314_123_1725_n220), .B(
DP_OP_497J314_123_1725_n224), .C(n1105), .CO(n1115), .S(n1395) );
CMPR32X2TS U2010 ( .A(DP_OP_497J314_123_1725_n65), .B(
DP_OP_497J314_123_1725_n69), .C(n1106), .CO(n1102), .S(n1128) );
CMPR32X2TS U2011 ( .A(n1109), .B(n1108), .C(n1107), .CO(n1396), .S(n1393) );
CMPR32X2TS U2012 ( .A(n1110), .B(DP_OP_497J314_123_1725_n74), .C(
DP_OP_497J314_123_1725_n70), .CO(n1106), .S(n1131) );
CMPR32X2TS U2013 ( .A(DP_OP_497J314_123_1725_n216), .B(n1112), .C(n1111),
.CO(n1107), .S(n1392) );
CMPR32X2TS U2014 ( .A(n1114), .B(n1113), .C(DP_OP_497J314_123_1725_n75),
.CO(n1110), .S(n1134) );
CMPR32X2TS U2015 ( .A(DP_OP_497J314_123_1725_n217), .B(
DP_OP_497J314_123_1725_n219), .C(n1115), .CO(n1111), .S(n1391) );
CMPR32X2TS U2016 ( .A(n1117), .B(n1395), .C(n1116), .CO(n1133), .S(n1314) );
CMPR32X2TS U2017 ( .A(n1119), .B(DP_OP_499J314_125_1651_n32), .C(n1118),
.CO(n1086), .S(n1324) );
CMPR32X2TS U2018 ( .A(n1122), .B(n1121), .C(n1120), .CO(n1265), .S(n1565) );
CMPR32X2TS U2019 ( .A(DP_OP_499J314_125_1651_n33), .B(
DP_OP_499J314_125_1651_n35), .C(n1123), .CO(n1118), .S(n1317) );
CMPR32X2TS U2020 ( .A(n1125), .B(n1396), .C(n1124), .CO(n1120), .S(n1564) );
CMPR32X2TS U2021 ( .A(DP_OP_499J314_125_1651_n36), .B(
DP_OP_499J314_125_1651_n38), .C(n1126), .CO(n1123), .S(n1309) );
CMPR32X2TS U2022 ( .A(n1128), .B(n1393), .C(n1127), .CO(n1124), .S(n1573) );
CMPR32X2TS U2023 ( .A(DP_OP_499J314_125_1651_n39), .B(
DP_OP_499J314_125_1651_n41), .C(n1129), .CO(n1126), .S(n1307) );
CMPR32X2TS U2024 ( .A(n1131), .B(n1392), .C(n1130), .CO(n1127), .S(n1572) );
CMPR32X2TS U2025 ( .A(DP_OP_499J314_125_1651_n42), .B(
DP_OP_499J314_125_1651_n44), .C(n1132), .CO(n1129), .S(n1305) );
CMPR32X2TS U2026 ( .A(n1134), .B(n1391), .C(n1133), .CO(n1130), .S(n1577) );
CMPR32X2TS U2027 ( .A(DP_OP_499J314_125_1651_n45), .B(
DP_OP_499J314_125_1651_n47), .C(n1135), .CO(n1132), .S(n1315) );
CMPR32X2TS U2028 ( .A(DP_OP_499J314_125_1651_n48), .B(
DP_OP_499J314_125_1651_n50), .C(n1136), .CO(n1135), .S(n1312) );
CMPR32X2TS U2029 ( .A(DP_OP_499J314_125_1651_n51), .B(
DP_OP_499J314_125_1651_n53), .C(n1137), .CO(n1136), .S(n1299) );
CMPR32X2TS U2030 ( .A(DP_OP_499J314_125_1651_n54), .B(
DP_OP_499J314_125_1651_n56), .C(n1138), .CO(n1137), .S(n1297) );
CMPR32X2TS U2031 ( .A(DP_OP_499J314_125_1651_n57), .B(
DP_OP_499J314_125_1651_n59), .C(n1139), .CO(n1138), .S(n1303) );
CMPR32X2TS U2032 ( .A(DP_OP_499J314_125_1651_n60), .B(
DP_OP_499J314_125_1651_n62), .C(n1140), .CO(n1139), .S(n1301) );
CMPR32X2TS U2033 ( .A(DP_OP_499J314_125_1651_n63), .B(
DP_OP_499J314_125_1651_n65), .C(n1141), .CO(n1140), .S(n1320) );
CMPR32X2TS U2034 ( .A(DP_OP_499J314_125_1651_n66), .B(
DP_OP_499J314_125_1651_n68), .C(n1142), .CO(n1141), .S(n1292) );
CMPR32X2TS U2035 ( .A(DP_OP_499J314_125_1651_n69), .B(
DP_OP_499J314_125_1651_n71), .C(n1143), .CO(n1142), .S(n1288) );
CMPR32X2TS U2036 ( .A(n1146), .B(n1145), .C(n1144), .CO(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[11]), .S(n1495) );
CMPR32X2TS U2037 ( .A(n1149), .B(n1148), .C(n1147), .CO(n1190), .S(n1193) );
XOR2X1TS U2038 ( .A(n1152), .B(DP_OP_498J314_124_1725_n19), .Y(n1157) );
NAND2X2TS U2039 ( .A(n1498), .B(n1473), .Y(n1477) );
CMPR32X2TS U2040 ( .A(FPMULT_Op_MY[1]), .B(n976), .C(n1155), .CO(n1452), .S(
n1487) );
INVX2TS U2041 ( .A(n1465), .Y(n1474) );
OAI31X1TS U2042 ( .A0(n1157), .A1(n1477), .A2(n1474), .B0(n1156), .Y(n1158)
);
XOR2X1TS U2043 ( .A(DP_OP_498J314_124_1725_n18), .B(n1158), .Y(n1206) );
CMPR32X2TS U2044 ( .A(DP_OP_498J314_124_1725_n311), .B(
DP_OP_498J314_124_1725_n315), .C(n1159), .CO(n1004), .S(n1494) );
CMPR32X2TS U2045 ( .A(DP_OP_498J314_124_1725_n20), .B(
DP_OP_498J314_124_1725_n22), .C(n1160), .CO(n1152), .S(n1211) );
CMPR32X2TS U2046 ( .A(DP_OP_498J314_124_1725_n316), .B(
DP_OP_498J314_124_1725_n322), .C(n1161), .CO(n1159), .S(n1492) );
CMPR32X2TS U2047 ( .A(DP_OP_498J314_124_1725_n23), .B(
DP_OP_498J314_124_1725_n27), .C(n1162), .CO(n1160), .S(n1216) );
CMPR32X2TS U2048 ( .A(DP_OP_498J314_124_1725_n323), .B(
DP_OP_498J314_124_1725_n329), .C(n1163), .CO(n1161), .S(n1519) );
CMPR32X2TS U2049 ( .A(DP_OP_498J314_124_1725_n28), .B(
DP_OP_498J314_124_1725_n33), .C(n1164), .CO(n1162), .S(n1221) );
CMPR32X2TS U2050 ( .A(DP_OP_498J314_124_1725_n330), .B(n1166), .C(n1165),
.CO(n1163), .S(n1437) );
CMPR32X2TS U2051 ( .A(DP_OP_498J314_124_1725_n34), .B(
DP_OP_498J314_124_1725_n39), .C(n1167), .CO(n1164), .S(n1226) );
CMPR32X2TS U2052 ( .A(n1170), .B(n1169), .C(n1168), .CO(n1165), .S(n1438) );
CMPR32X2TS U2053 ( .A(DP_OP_498J314_124_1725_n40), .B(
DP_OP_498J314_124_1725_n45), .C(n1171), .CO(n1167), .S(n1231) );
CMPR32X2TS U2054 ( .A(n1174), .B(n1173), .C(n1172), .CO(n1168), .S(n1491) );
CMPR32X2TS U2055 ( .A(DP_OP_498J314_124_1725_n46), .B(
DP_OP_498J314_124_1725_n51), .C(n1175), .CO(n1171), .S(n1235) );
CMPR32X2TS U2056 ( .A(DP_OP_498J314_124_1725_n52), .B(
DP_OP_498J314_124_1725_n57), .C(n1176), .CO(n1175), .S(n1238) );
INVX2TS U2057 ( .A(n1177), .Y(n1237) );
CMPR32X2TS U2058 ( .A(n1178), .B(DP_OP_498J314_124_1725_n64), .C(
DP_OP_498J314_124_1725_n58), .CO(n1176), .S(n1557) );
CLKAND2X2TS U2059 ( .A(FPMULT_Op_MY[5]), .B(n974), .Y(n1184) );
CMPR32X2TS U2060 ( .A(n1180), .B(n1179), .C(DP_OP_498J314_124_1725_n215),
.CO(n1185), .S(n1188) );
CMPR32X2TS U2061 ( .A(DP_OP_498J314_124_1725_n220), .B(
DP_OP_498J314_124_1725_n224), .C(n1181), .CO(n1191), .S(n1493) );
CMPR32X2TS U2062 ( .A(DP_OP_498J314_124_1725_n65), .B(
DP_OP_498J314_124_1725_n69), .C(n1182), .CO(n1178), .S(n1563) );
CMPR32X2TS U2063 ( .A(n1185), .B(n1184), .C(n1183), .CO(n1556), .S(n1562) );
CMPR32X2TS U2064 ( .A(n1186), .B(DP_OP_498J314_124_1725_n74), .C(
DP_OP_498J314_124_1725_n70), .CO(n1182), .S(n1560) );
CMPR32X2TS U2065 ( .A(DP_OP_498J314_124_1725_n216), .B(n1188), .C(n1187),
.CO(n1183), .S(n1559) );
CMPR32X2TS U2066 ( .A(n1190), .B(n1189), .C(DP_OP_498J314_124_1725_n75),
.CO(n1186), .S(n1576) );
CMPR32X2TS U2067 ( .A(DP_OP_498J314_124_1725_n217), .B(
DP_OP_498J314_124_1725_n219), .C(n1191), .CO(n1187), .S(n1575) );
CMPR32X2TS U2068 ( .A(n1193), .B(n1493), .C(n1192), .CO(n1574), .S(n1678) );
XOR2X1TS U2069 ( .A(n1194), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[11]), .Y(n1552) );
CMPR32X2TS U2070 ( .A(DP_OP_499J314_125_1651_n72), .B(
DP_OP_499J314_125_1651_n74), .C(n1195), .CO(n1143), .S(n1696) );
ADDHX1TS U2071 ( .A(n1495), .B(n1196), .CO(n1194), .S(n1695) );
CMPR32X2TS U2072 ( .A(DP_OP_499J314_125_1651_n75), .B(
DP_OP_499J314_125_1651_n77), .C(n1197), .CO(n1195), .S(n1707) );
ADDHX1TS U2073 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]), .B(n1198),
.CO(n1196), .S(n1706) );
CMPR32X2TS U2074 ( .A(DP_OP_499J314_125_1651_n78), .B(n1200), .C(n1199),
.CO(n1197), .S(n1717) );
ADDHX1TS U2075 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]), .B(n1201),
.CO(n1198), .S(n1716) );
CMPR32X2TS U2076 ( .A(n1204), .B(n1203), .C(n1202), .CO(n1199), .S(n1690) );
CMPR32X2TS U2077 ( .A(n1206), .B(n1494), .C(n1205), .CO(n1201), .S(n1689) );
CMPR32X2TS U2078 ( .A(n1209), .B(n1208), .C(n1207), .CO(n1202), .S(n1714) );
CMPR32X2TS U2079 ( .A(n1211), .B(n1492), .C(n1210), .CO(n1205), .S(n1713) );
CMPR32X2TS U2080 ( .A(n1214), .B(n1213), .C(n1212), .CO(n1207), .S(n1681) );
CMPR32X2TS U2081 ( .A(n1216), .B(n1519), .C(n1215), .CO(n1210), .S(n1680) );
CMPR32X2TS U2082 ( .A(n1219), .B(n1218), .C(n1217), .CO(n1212), .S(n1684) );
CMPR32X2TS U2083 ( .A(n1221), .B(n1437), .C(n1220), .CO(n1215), .S(n1683) );
CMPR32X2TS U2084 ( .A(n1224), .B(n1223), .C(n1222), .CO(n1217), .S(n1687) );
CMPR32X2TS U2085 ( .A(n1226), .B(n1438), .C(n1225), .CO(n1220), .S(n1686) );
CMPR32X2TS U2086 ( .A(n1229), .B(n1228), .C(n1227), .CO(n1222), .S(n2034) );
CMPR32X2TS U2087 ( .A(n1231), .B(n1491), .C(n1230), .CO(n1225), .S(n2033) );
CMPR32X2TS U2088 ( .A(n1233), .B(n1151), .C(n1232), .CO(n1227), .S(n1693) );
CMPR32X2TS U2089 ( .A(n1238), .B(n1237), .C(n1236), .CO(n1234), .S(n2031) );
NOR2X1TS U2090 ( .A(n1241), .B(n1240), .Y(DP_OP_497J314_123_1725_n192) );
INVX2TS U2091 ( .A(DP_OP_497J314_123_1725_n192), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[11]) );
INVX2TS U2092 ( .A(DP_OP_497J314_123_1725_n193), .Y(n1284) );
CMPR32X2TS U2093 ( .A(DP_OP_497J314_123_1725_n46), .B(
DP_OP_497J314_123_1725_n51), .C(n1242), .CO(n1261), .S(n1266) );
XOR2X1TS U2094 ( .A(n1243), .B(DP_OP_497J314_123_1725_n19), .Y(n1247) );
OAI31X1TS U2095 ( .A0(n1247), .A1(n1373), .A2(n1409), .B0(n1246), .Y(n1248)
);
XOR2X1TS U2096 ( .A(DP_OP_497J314_123_1725_n18), .B(n1248), .Y(n1270) );
CMPR32X2TS U2097 ( .A(DP_OP_497J314_123_1725_n311), .B(
DP_OP_497J314_123_1725_n315), .C(n1249), .CO(n1016), .S(n1389) );
CMPR32X2TS U2098 ( .A(DP_OP_497J314_123_1725_n22), .B(
DP_OP_497J314_123_1725_n20), .C(n1250), .CO(n1243), .S(n1272) );
CMPR32X2TS U2099 ( .A(DP_OP_497J314_123_1725_n316), .B(
DP_OP_497J314_123_1725_n322), .C(n1251), .CO(n1249), .S(n1390) );
CMPR32X2TS U2100 ( .A(DP_OP_497J314_123_1725_n23), .B(
DP_OP_497J314_123_1725_n27), .C(n1252), .CO(n1250), .S(n1274) );
CMPR32X2TS U2101 ( .A(DP_OP_497J314_123_1725_n323), .B(
DP_OP_497J314_123_1725_n329), .C(n1253), .CO(n1251), .S(n1434) );
CMPR32X2TS U2102 ( .A(DP_OP_497J314_123_1725_n28), .B(
DP_OP_497J314_123_1725_n33), .C(n1254), .CO(n1252), .S(n1276) );
CMPR32X2TS U2103 ( .A(DP_OP_497J314_123_1725_n330), .B(n1256), .C(n1255),
.CO(n1253), .S(n1328) );
CMPR32X2TS U2104 ( .A(DP_OP_497J314_123_1725_n34), .B(
DP_OP_497J314_123_1725_n39), .C(n1257), .CO(n1254), .S(n1278) );
CMPR32X2TS U2105 ( .A(n1260), .B(n1259), .C(n1258), .CO(n1255), .S(n1329) );
CMPR32X2TS U2106 ( .A(DP_OP_497J314_123_1725_n40), .B(
DP_OP_497J314_123_1725_n45), .C(n1261), .CO(n1257), .S(n1280) );
CMPR32X2TS U2107 ( .A(n1264), .B(n1263), .C(n1262), .CO(n1258), .S(n1387) );
CMPR32X2TS U2108 ( .A(n1266), .B(n1385), .C(n1265), .CO(n1279), .S(n1566) );
ADDHX1TS U2109 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]), .B(n1267),
.CO(n1283), .S(n1550) );
ADDHX1TS U2110 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .B(n1268),
.CO(n1267), .S(n1549) );
CMPR32X2TS U2111 ( .A(n1270), .B(n1389), .C(n1269), .CO(n1268), .S(n1554) );
CMPR32X2TS U2112 ( .A(n1272), .B(n1390), .C(n1271), .CO(n1269), .S(n1569) );
CMPR32X2TS U2113 ( .A(n1274), .B(n1434), .C(n1273), .CO(n1271), .S(n1567) );
CMPR32X2TS U2114 ( .A(n1276), .B(n1328), .C(n1275), .CO(n1273), .S(n1568) );
CMPR32X2TS U2115 ( .A(n1278), .B(n1329), .C(n1277), .CO(n1275), .S(n1571) );
CMPR32X2TS U2116 ( .A(n1280), .B(n1387), .C(n1279), .CO(n1277), .S(n1570) );
CMPR32X2TS U2117 ( .A(n1282), .B(n1566), .C(n1281), .CO(n1295), .S(
FPMULT_Sgf_operation_Result[37]) );
XOR2X1TS U2118 ( .A(n1285), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[11]), .Y(n1553)
);
CMPR32X2TS U2119 ( .A(n1288), .B(n1552), .C(n1287), .CO(n1290), .S(
FPMULT_Sgf_operation_Result[23]) );
ADDHXLTS U2120 ( .A(n1549), .B(n1289), .CO(n1293), .S(
FPMULT_Sgf_operation_Result[44]) );
ADDHXLTS U2121 ( .A(n1550), .B(n1293), .CO(n1294), .S(
FPMULT_Sgf_operation_Result[45]) );
ADDHXLTS U2122 ( .A(n1551), .B(n1294), .CO(n1286), .S(
FPMULT_Sgf_operation_Result[46]) );
CMPR32X2TS U2123 ( .A(n1299), .B(n1331), .C(n1298), .CO(n1310), .S(
FPMULT_Sgf_operation_Result[29]) );
CMPR32X2TS U2124 ( .A(n1305), .B(n1577), .C(n1304), .CO(n1306), .S(
FPMULT_Sgf_operation_Result[32]) );
CMPR32X2TS U2125 ( .A(n1307), .B(n1572), .C(n1306), .CO(n1308), .S(
FPMULT_Sgf_operation_Result[33]) );
CMPR32X2TS U2126 ( .A(n1309), .B(n1573), .C(n1308), .CO(n1316), .S(
FPMULT_Sgf_operation_Result[34]) );
CMPR32X2TS U2127 ( .A(n1312), .B(n1311), .C(n1310), .CO(n1313), .S(
FPMULT_Sgf_operation_Result[30]) );
CMPR32X2TS U2128 ( .A(n1315), .B(n1314), .C(n1313), .CO(n1304), .S(
FPMULT_Sgf_operation_Result[31]) );
CMPR32X2TS U2129 ( .A(n1317), .B(n1564), .C(n1316), .CO(n1323), .S(
FPMULT_Sgf_operation_Result[35]) );
ADDHXLTS U2130 ( .A(n1554), .B(n1321), .CO(n1289), .S(
FPMULT_Sgf_operation_Result[43]) );
ADDHXLTS U2131 ( .A(n1571), .B(n1322), .CO(n1327), .S(
FPMULT_Sgf_operation_Result[39]) );
CMPR32X2TS U2132 ( .A(n1324), .B(n1565), .C(n1323), .CO(n1281), .S(
FPMULT_Sgf_operation_Result[36]) );
ADDHXLTS U2133 ( .A(n1569), .B(n1325), .CO(n1321), .S(
FPMULT_Sgf_operation_Result[42]) );
ADDHXLTS U2134 ( .A(n1567), .B(n1326), .CO(n1325), .S(
FPMULT_Sgf_operation_Result[41]) );
ADDHXLTS U2135 ( .A(n1568), .B(n1327), .CO(n1326), .S(
FPMULT_Sgf_operation_Result[40]) );
INVX2TS U2136 ( .A(n1328), .Y(n1334) );
INVX2TS U2137 ( .A(n1329), .Y(n1402) );
CMPR32X2TS U2138 ( .A(n1332), .B(n1058), .C(DP_OP_497J314_123_1725_n63),
.CO(DP_OP_497J314_123_1725_n59), .S(DP_OP_497J314_123_1725_n60) );
CMPR32X2TS U2139 ( .A(n1334), .B(n1333), .C(n1063), .CO(n1332), .S(
DP_OP_497J314_123_1725_n67) );
NOR2X1TS U2140 ( .A(n925), .B(n972), .Y(n1336) );
CMPR32X2TS U2141 ( .A(n1337), .B(n1336), .C(n1335), .CO(
DP_OP_497J314_123_1725_n221), .S(DP_OP_497J314_123_1725_n222) );
NOR2X1TS U2142 ( .A(n925), .B(n939), .Y(n1339) );
CMPR32X2TS U2143 ( .A(n1340), .B(n1339), .C(n1338), .CO(
DP_OP_497J314_123_1725_n226), .S(DP_OP_497J314_123_1725_n227) );
NOR2X1TS U2144 ( .A(n925), .B(n938), .Y(n1342) );
CMPR32X2TS U2145 ( .A(n1343), .B(n1342), .C(n1341), .CO(
DP_OP_497J314_123_1725_n233), .S(DP_OP_497J314_123_1725_n234) );
ADDHXLTS U2146 ( .A(n1345), .B(n1344), .CO(DP_OP_497J314_123_1725_n235), .S(
DP_OP_497J314_123_1725_n236) );
CMPR32X2TS U2147 ( .A(FPMULT_Op_MY[20]), .B(n985), .C(n1346), .CO(
DP_OP_497J314_123_1725_n312), .S(DP_OP_497J314_123_1725_n313) );
ADDHXLTS U2148 ( .A(FPMULT_Op_MY[18]), .B(FPMULT_Op_MX[18]), .CO(
DP_OP_497J314_123_1725_n326), .S(DP_OP_497J314_123_1725_n327) );
INVX2TS U2149 ( .A(n1373), .Y(n1365) );
AOI22X1TS U2150 ( .A0(n1408), .A1(n1365), .B0(n1373), .B1(n1376), .Y(n1406)
);
INVX2TS U2151 ( .A(n1410), .Y(n1367) );
AOI22X1TS U2152 ( .A0(n1408), .A1(n1367), .B0(n1410), .B1(n1376), .Y(n1349)
);
OAI22X1TS U2153 ( .A0(n1407), .A1(n1406), .B0(n1405), .B1(n1349), .Y(
DP_OP_497J314_123_1725_n103) );
INVX2TS U2154 ( .A(n1369), .Y(n1411) );
AOI22X1TS U2155 ( .A0(n1408), .A1(n1369), .B0(n1411), .B1(n1376), .Y(n1351)
);
OAI22X1TS U2156 ( .A0(n1351), .A1(n1405), .B0(n1407), .B1(n1349), .Y(
DP_OP_497J314_123_1725_n104) );
INVX2TS U2157 ( .A(n1371), .Y(n1374) );
AOI22X1TS U2158 ( .A0(n1408), .A1(n1371), .B0(n1374), .B1(n1376), .Y(n1353)
);
OAI22X1TS U2159 ( .A0(n1351), .A1(n1407), .B0(n1353), .B1(n1405), .Y(
DP_OP_497J314_123_1725_n105) );
INVX2TS U2160 ( .A(n1380), .Y(n1378) );
AOI22X1TS U2161 ( .A0(n1408), .A1(n1380), .B0(n1378), .B1(n1376), .Y(n1354)
);
OAI22X1TS U2162 ( .A0(n1353), .A1(n1407), .B0(n1354), .B1(n1405), .Y(
DP_OP_497J314_123_1725_n106) );
AOI22X1TS U2163 ( .A0(n1408), .A1(n1382), .B0(n1375), .B1(n1376), .Y(n1356)
);
OAI22X1TS U2164 ( .A0(n1354), .A1(n1407), .B0(n1356), .B1(n1405), .Y(
DP_OP_497J314_123_1725_n107) );
AOI22X1TS U2165 ( .A0(n1408), .A1(n1403), .B0(n1384), .B1(n1376), .Y(n1355)
);
OAI22X1TS U2166 ( .A0(n1356), .A1(n1407), .B0(n1405), .B1(n1355), .Y(
DP_OP_497J314_123_1725_n108) );
AOI22X1TS U2167 ( .A0(n1400), .A1(n1373), .B0(n1365), .B1(n1404), .Y(n1360)
);
CMPR32X2TS U2168 ( .A(n973), .B(n985), .C(n1357), .CO(n1095), .S(n1359) );
INVX2TS U2169 ( .A(n1359), .Y(n1401) );
AOI22X1TS U2170 ( .A0(n1379), .A1(n1401), .B0(n1359), .B1(
DP_OP_497J314_123_1725_n119), .Y(n1358) );
OAI221X4TS U2171 ( .A0(n1359), .A1(n1400), .B0(n1401), .B1(n1404), .C0(n1433), .Y(n1431) );
OAI22X1TS U2172 ( .A0(n1360), .A1(n1431), .B0(n1404), .B1(n1433), .Y(
DP_OP_497J314_123_1725_n111) );
AOI22X1TS U2173 ( .A0(n1400), .A1(n1410), .B0(n1367), .B1(n1404), .Y(n1361)
);
OAI22X1TS U2174 ( .A0(n1360), .A1(n1433), .B0(n1361), .B1(n1431), .Y(
DP_OP_497J314_123_1725_n112) );
AOI22X1TS U2175 ( .A0(n1400), .A1(n1411), .B0(n1369), .B1(n1404), .Y(n1362)
);
OAI22X1TS U2176 ( .A0(n1361), .A1(n1433), .B0(n1431), .B1(n1362), .Y(
DP_OP_497J314_123_1725_n113) );
AOI22X1TS U2177 ( .A0(n1400), .A1(n1374), .B0(n1371), .B1(n1404), .Y(n1432)
);
OAI22X1TS U2178 ( .A0(n1433), .A1(n1362), .B0(n1431), .B1(n1432), .Y(
DP_OP_497J314_123_1725_n114) );
AOI22X1TS U2179 ( .A0(n1400), .A1(n1378), .B0(n1380), .B1(n1404), .Y(n1430)
);
AOI22X1TS U2180 ( .A0(n1400), .A1(n1375), .B0(n1382), .B1(n1404), .Y(n1364)
);
OAI22X1TS U2181 ( .A0(n1433), .A1(n1430), .B0(n1431), .B1(n1364), .Y(
DP_OP_497J314_123_1725_n116) );
AOI22X1TS U2182 ( .A0(n1400), .A1(n1384), .B0(n1403), .B1(n1404), .Y(n1363)
);
OAI22X1TS U2183 ( .A0(n1433), .A1(n1364), .B0(n1431), .B1(n1363), .Y(
DP_OP_497J314_123_1725_n117) );
AOI21X1TS U2184 ( .A0(n1365), .A1(n1031), .B0(DP_OP_497J314_123_1725_n119),
.Y(DP_OP_497J314_123_1725_n120) );
AOI22X1TS U2185 ( .A0(n1373), .A1(n1379), .B0(DP_OP_497J314_123_1725_n119),
.B1(n1365), .Y(n1366) );
OAI32X1TS U2186 ( .A0(n1383), .A1(n1367), .A2(DP_OP_497J314_123_1725_n119),
.B0(n1366), .B1(n1031), .Y(DP_OP_497J314_123_1725_n121) );
AOI22X1TS U2187 ( .A0(n1410), .A1(n1379), .B0(DP_OP_497J314_123_1725_n119),
.B1(n1367), .Y(n1368) );
OAI32X1TS U2188 ( .A0(n1383), .A1(n1369), .A2(DP_OP_497J314_123_1725_n119),
.B0(n1368), .B1(n1031), .Y(DP_OP_497J314_123_1725_n122) );
AOI22X1TS U2189 ( .A0(n1369), .A1(DP_OP_497J314_123_1725_n119), .B0(n1379),
.B1(n1411), .Y(n1370) );
OAI32X1TS U2190 ( .A0(n1383), .A1(n1371), .A2(DP_OP_497J314_123_1725_n119),
.B0(n1370), .B1(n1031), .Y(DP_OP_497J314_123_1725_n123) );
AOI22X1TS U2191 ( .A0(n1371), .A1(DP_OP_497J314_123_1725_n119), .B0(n1379),
.B1(n1374), .Y(n1372) );
OAI32X1TS U2192 ( .A0(n1383), .A1(n1380), .A2(DP_OP_497J314_123_1725_n119),
.B0(n1372), .B1(n1031), .Y(DP_OP_497J314_123_1725_n124) );
INVX2TS U2193 ( .A(n1409), .Y(n1412) );
AOI22X1TS U2194 ( .A0(n1412), .A1(n1410), .B0(n1373), .B1(n1409), .Y(
DP_OP_497J314_123_1725_n94) );
AOI22X1TS U2195 ( .A0(n1412), .A1(n1374), .B0(n1411), .B1(n1409), .Y(
DP_OP_497J314_123_1725_n96) );
AOI22X1TS U2196 ( .A0(n1412), .A1(n1378), .B0(n1374), .B1(n1409), .Y(
DP_OP_497J314_123_1725_n97) );
AOI22X1TS U2197 ( .A0(n1412), .A1(n1375), .B0(n1378), .B1(n1409), .Y(
DP_OP_497J314_123_1725_n98) );
AOI22X1TS U2198 ( .A0(n1412), .A1(n1384), .B0(n1375), .B1(n1409), .Y(
DP_OP_497J314_123_1725_n99) );
OAI21X1TS U2199 ( .A0(n1404), .A1(n1377), .B0(n1376), .Y(
DP_OP_497J314_123_1725_n101) );
NOR2X1TS U2200 ( .A(n1407), .B(n1384), .Y(DP_OP_497J314_123_1725_n109) );
AOI22X1TS U2201 ( .A0(n1380), .A1(DP_OP_497J314_123_1725_n119), .B0(n1379),
.B1(n1378), .Y(n1381) );
OAI32X1TS U2202 ( .A0(n1383), .A1(n1382), .A2(DP_OP_497J314_123_1725_n119),
.B0(n1381), .B1(n1031), .Y(DP_OP_497J314_123_1725_n125) );
INVX2TS U2203 ( .A(n1385), .Y(DP_OP_497J314_123_1725_n202) );
INVX2TS U2204 ( .A(n1386), .Y(DP_OP_497J314_123_1725_n87) );
INVX2TS U2205 ( .A(n1387), .Y(DP_OP_497J314_123_1725_n201) );
INVX2TS U2206 ( .A(n1388), .Y(DP_OP_497J314_123_1725_n83) );
INVX2TS U2207 ( .A(n1389), .Y(DP_OP_497J314_123_1725_n196) );
INVX2TS U2208 ( .A(n1390), .Y(DP_OP_497J314_123_1725_n197) );
INVX2TS U2209 ( .A(n1391), .Y(DP_OP_497J314_123_1725_n81) );
INVX2TS U2210 ( .A(n1392), .Y(DP_OP_497J314_123_1725_n80) );
INVX2TS U2211 ( .A(n1393), .Y(DP_OP_497J314_123_1725_n79) );
INVX2TS U2212 ( .A(n1395), .Y(DP_OP_497J314_123_1725_n82) );
INVX2TS U2213 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .Y(DP_OP_497J314_123_1725_n195) );
INVX2TS U2214 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]), .Y(DP_OP_497J314_123_1725_n194) );
NOR2X1TS U2215 ( .A(n1397), .B(n940), .Y(DP_OP_497J314_123_1725_n269) );
INVX2TS U2216 ( .A(n1396), .Y(DP_OP_497J314_123_1725_n78) );
ADDHXLTS U2217 ( .A(n1399), .B(n1398), .CO(DP_OP_497J314_123_1725_n228), .S(
DP_OP_497J314_123_1725_n229) );
NOR2X1TS U2218 ( .A(n942), .B(n926), .Y(DP_OP_497J314_123_1725_n250) );
OAI21X1TS U2219 ( .A0(DP_OP_497J314_123_1725_n119), .A1(n1401), .B0(n1400),
.Y(DP_OP_497J314_123_1725_n110) );
NOR2X1TS U2220 ( .A(n1420), .B(n944), .Y(DP_OP_497J314_123_1725_n261) );
NOR2X1TS U2221 ( .A(n1420), .B(n943), .Y(DP_OP_497J314_123_1725_n255) );
ADDHXLTS U2222 ( .A(DP_OP_497J314_123_1725_n73), .B(n1402), .CO(n1333), .S(
DP_OP_497J314_123_1725_n72) );
OAI32X1TS U2223 ( .A0(n1404), .A1(n1403), .A2(n1433), .B0(n1431), .B1(n1404),
.Y(DP_OP_497J314_123_1725_n91) );
OAI22X1TS U2224 ( .A0(n1408), .A1(n1407), .B0(n1406), .B1(n1405), .Y(n1414)
);
AOI22X1TS U2225 ( .A0(n1412), .A1(n1411), .B0(n1410), .B1(n1409), .Y(n1413)
);
CMPR32X2TS U2226 ( .A(n1414), .B(n1413), .C(DP_OP_497J314_123_1725_n29),
.CO(DP_OP_497J314_123_1725_n24), .S(DP_OP_497J314_123_1725_n25) );
ADDHXLTS U2227 ( .A(n1416), .B(n1415), .CO(DP_OP_497J314_123_1725_n240), .S(
DP_OP_497J314_123_1725_n241) );
NOR2X1TS U2228 ( .A(n1420), .B(n938), .Y(DP_OP_497J314_123_1725_n279) );
NOR2X1TS U2229 ( .A(n926), .B(n939), .Y(DP_OP_497J314_123_1725_n274) );
CMPR32X2TS U2230 ( .A(n1419), .B(n1418), .C(n1417), .CO(
DP_OP_497J314_123_1725_n324), .S(DP_OP_497J314_123_1725_n325) );
NOR2X1TS U2231 ( .A(n1420), .B(n939), .Y(DP_OP_497J314_123_1725_n273) );
CMPR32X2TS U2232 ( .A(n1423), .B(n1422), .C(n1421), .CO(
DP_OP_497J314_123_1725_n317), .S(DP_OP_497J314_123_1725_n318) );
ADDHXLTS U2233 ( .A(n1425), .B(n1424), .CO(DP_OP_497J314_123_1725_n335), .S(
n1259) );
ADDHXLTS U2234 ( .A(n1427), .B(n1426), .CO(DP_OP_497J314_123_1725_n244), .S(
n1065) );
NOR2X1TS U2235 ( .A(n925), .B(n944), .Y(DP_OP_497J314_123_1725_n260) );
ADDHXLTS U2236 ( .A(n1429), .B(n1428), .CO(DP_OP_497J314_123_1725_n331), .S(
DP_OP_497J314_123_1725_n332) );
OAI22X1TS U2237 ( .A0(n1433), .A1(n1432), .B0(n1431), .B1(n1430), .Y(n1436)
);
INVX2TS U2238 ( .A(n1434), .Y(n1435) );
ADDHXLTS U2239 ( .A(n1436), .B(n1435), .CO(DP_OP_497J314_123_1725_n61), .S(
DP_OP_497J314_123_1725_n62) );
INVX2TS U2240 ( .A(n1437), .Y(n1442) );
INVX2TS U2241 ( .A(n1438), .Y(n1501) );
INVX2TS U2242 ( .A(n1721), .Y(n1440) );
CMPR32X2TS U2243 ( .A(n1439), .B(n1057), .C(DP_OP_498J314_124_1725_n63),
.CO(DP_OP_498J314_124_1725_n59), .S(DP_OP_498J314_124_1725_n60) );
CMPR32X2TS U2244 ( .A(n1442), .B(n1441), .C(n1440), .CO(n1439), .S(
DP_OP_498J314_124_1725_n67) );
CMPR32X4TS U2245 ( .A(n983), .B(n981), .C(n1443), .CO(n1444), .S(n1496) );
INVX2TS U2246 ( .A(n1446), .Y(n1499) );
AOI22X1TS U2247 ( .A0(n1496), .A1(n1499), .B0(n1446), .B1(n1500), .Y(n1445)
);
INVX4TS U2248 ( .A(n1498), .Y(n1505) );
AOI22X1TS U2249 ( .A0(n1498), .A1(n1474), .B0(n1465), .B1(n1505), .Y(n1480)
);
OAI221X4TS U2250 ( .A0(n1446), .A1(n1498), .B0(n1499), .B1(n1505), .C0(n1503), .Y(n1502) );
INVX2TS U2251 ( .A(n1467), .Y(n1479) );
AOI22X1TS U2252 ( .A0(n1498), .A1(n1479), .B0(n1467), .B1(n1505), .Y(n1449)
);
OAI22X1TS U2253 ( .A0(n1503), .A1(n1480), .B0(n1502), .B1(n1449), .Y(
DP_OP_498J314_124_1725_n103) );
CMPR32X2TS U2254 ( .A(FPMULT_Op_MY[4]), .B(n975), .C(n1448), .CO(n1447), .S(
n1469) );
INVX2TS U2255 ( .A(n1469), .Y(n1478) );
AOI22X1TS U2256 ( .A0(n1498), .A1(n1478), .B0(n1469), .B1(n1505), .Y(n1451)
);
OAI22X1TS U2257 ( .A0(n1503), .A1(n1449), .B0(n1502), .B1(n1451), .Y(
DP_OP_498J314_124_1725_n104) );
CMPR32X2TS U2258 ( .A(FPMULT_Op_MY[3]), .B(n977), .C(n1450), .CO(n1448), .S(
n1471) );
INVX2TS U2259 ( .A(n1471), .Y(n1475) );
AOI22X1TS U2260 ( .A0(n1498), .A1(n1475), .B0(n1471), .B1(n1505), .Y(n1453)
);
OAI22X1TS U2261 ( .A0(n1503), .A1(n1451), .B0(n1502), .B1(n1453), .Y(
DP_OP_498J314_124_1725_n105) );
INVX2TS U2262 ( .A(n1485), .Y(n1483) );
AOI22X1TS U2263 ( .A0(n1498), .A1(n1483), .B0(n1485), .B1(n1505), .Y(n1454)
);
OAI22X1TS U2264 ( .A0(n1503), .A1(n1453), .B0(n1502), .B1(n1454), .Y(
DP_OP_498J314_124_1725_n106) );
AOI22X1TS U2265 ( .A0(n1498), .A1(n1476), .B0(n1487), .B1(n1505), .Y(n1456)
);
OAI22X1TS U2266 ( .A0(n1503), .A1(n1454), .B0(n1502), .B1(n1456), .Y(
DP_OP_498J314_124_1725_n107) );
AOI22X1TS U2267 ( .A0(n1498), .A1(n1523), .B0(n1504), .B1(n1505), .Y(n1455)
);
OAI22X1TS U2268 ( .A0(n1503), .A1(n1456), .B0(n1502), .B1(n1455), .Y(
DP_OP_498J314_124_1725_n108) );
INVX2TS U2269 ( .A(n1459), .Y(n1497) );
AOI22X1TS U2270 ( .A0(n1484), .A1(n1497), .B0(n1459), .B1(
DP_OP_498J314_124_1725_n119), .Y(n1458) );
OAI221X4TS U2271 ( .A0(n1459), .A1(n1496), .B0(n1497), .B1(n1500), .C0(n1518), .Y(n1516) );
AOI22X1TS U2272 ( .A0(n1496), .A1(n1474), .B0(n1465), .B1(n1500), .Y(n1460)
);
OAI22X1TS U2273 ( .A0(n1500), .A1(n1518), .B0(n1516), .B1(n1460), .Y(
DP_OP_498J314_124_1725_n111) );
AOI22X1TS U2274 ( .A0(n1496), .A1(n1479), .B0(n1467), .B1(n1500), .Y(n1461)
);
OAI22X1TS U2275 ( .A0(n1518), .A1(n1460), .B0(n1516), .B1(n1461), .Y(
DP_OP_498J314_124_1725_n112) );
AOI22X1TS U2276 ( .A0(n1496), .A1(n1478), .B0(n1469), .B1(n1500), .Y(n1462)
);
OAI22X1TS U2277 ( .A0(n1518), .A1(n1461), .B0(n1516), .B1(n1462), .Y(
DP_OP_498J314_124_1725_n113) );
AOI22X1TS U2278 ( .A0(n1496), .A1(n1475), .B0(n1471), .B1(n1500), .Y(n1517)
);
OAI22X1TS U2279 ( .A0(n1518), .A1(n1462), .B0(n1516), .B1(n1517), .Y(
DP_OP_498J314_124_1725_n114) );
AOI22X1TS U2280 ( .A0(n1496), .A1(n1483), .B0(n1485), .B1(n1500), .Y(n1515)
);
AOI22X1TS U2281 ( .A0(n1496), .A1(n1476), .B0(n1487), .B1(n1500), .Y(n1464)
);
OAI22X1TS U2282 ( .A0(n1518), .A1(n1515), .B0(n1516), .B1(n1464), .Y(
DP_OP_498J314_124_1725_n116) );
AOI22X1TS U2283 ( .A0(n1496), .A1(n1523), .B0(n1504), .B1(n1500), .Y(n1463)
);
OAI22X1TS U2284 ( .A0(n1518), .A1(n1464), .B0(n1516), .B1(n1463), .Y(
DP_OP_498J314_124_1725_n117) );
AOI21X1TS U2285 ( .A0(n1465), .A1(n1017), .B0(DP_OP_498J314_124_1725_n119),
.Y(DP_OP_498J314_124_1725_n120) );
AOI22X1TS U2286 ( .A0(n1465), .A1(DP_OP_498J314_124_1725_n119), .B0(n1484),
.B1(n1474), .Y(n1466) );
OAI32X1TS U2287 ( .A0(n1488), .A1(n1467), .A2(DP_OP_498J314_124_1725_n119),
.B0(n1466), .B1(n1017), .Y(DP_OP_498J314_124_1725_n121) );
AOI22X1TS U2288 ( .A0(n1467), .A1(DP_OP_498J314_124_1725_n119), .B0(n1484),
.B1(n1479), .Y(n1468) );
OAI32X1TS U2289 ( .A0(n1488), .A1(n1469), .A2(DP_OP_498J314_124_1725_n119),
.B0(n1468), .B1(n1017), .Y(DP_OP_498J314_124_1725_n122) );
AOI22X1TS U2290 ( .A0(n1469), .A1(DP_OP_498J314_124_1725_n119), .B0(n1484),
.B1(n1478), .Y(n1470) );
OAI32X1TS U2291 ( .A0(n1488), .A1(n1471), .A2(DP_OP_498J314_124_1725_n119),
.B0(n1470), .B1(n1017), .Y(DP_OP_498J314_124_1725_n123) );
AOI22X1TS U2292 ( .A0(n1471), .A1(DP_OP_498J314_124_1725_n119), .B0(n1484),
.B1(n1475), .Y(n1472) );
OAI32X1TS U2293 ( .A0(n1488), .A1(n1485), .A2(DP_OP_498J314_124_1725_n119),
.B0(n1472), .B1(n1017), .Y(DP_OP_498J314_124_1725_n124) );
AOI2BB2X4TS U2294 ( .B0(n1473), .B1(n1505), .A0N(n1505), .A1N(n1473), .Y(
n1522) );
OAI22X1TS U2295 ( .A0(n1474), .A1(n1522), .B0(n1479), .B1(n1477), .Y(
DP_OP_498J314_124_1725_n94) );
OAI22X1TS U2296 ( .A0(n1478), .A1(n1522), .B0(n1475), .B1(n1477), .Y(
DP_OP_498J314_124_1725_n96) );
OAI22X1TS U2297 ( .A0(n1475), .A1(n1522), .B0(n1483), .B1(n1477), .Y(
DP_OP_498J314_124_1725_n97) );
OAI22X1TS U2298 ( .A0(n1483), .A1(n1522), .B0(n1476), .B1(n1477), .Y(
DP_OP_498J314_124_1725_n98) );
OAI22X1TS U2299 ( .A0(n1476), .A1(n1522), .B0(n1523), .B1(n1477), .Y(
DP_OP_498J314_124_1725_n99) );
OAI22X1TS U2300 ( .A0(n1479), .A1(n1522), .B0(n1478), .B1(n1477), .Y(n1482)
);
OAI22X1TS U2301 ( .A0(n1505), .A1(n1503), .B0(n1502), .B1(n1480), .Y(n1481)
);
CMPR32X2TS U2302 ( .A(n1482), .B(n1481), .C(DP_OP_498J314_124_1725_n29),
.CO(DP_OP_498J314_124_1725_n24), .S(DP_OP_498J314_124_1725_n25) );
NOR2X1TS U2303 ( .A(n1503), .B(n1523), .Y(DP_OP_498J314_124_1725_n109) );
AOI22X1TS U2304 ( .A0(n1485), .A1(DP_OP_498J314_124_1725_n119), .B0(n1484),
.B1(n1483), .Y(n1486) );
OAI32X1TS U2305 ( .A0(n1488), .A1(n1487), .A2(DP_OP_498J314_124_1725_n119),
.B0(n1486), .B1(n1017), .Y(DP_OP_498J314_124_1725_n125) );
INVX2TS U2306 ( .A(n1489), .Y(DP_OP_498J314_124_1725_n202) );
INVX2TS U2307 ( .A(n1490), .Y(DP_OP_498J314_124_1725_n83) );
INVX2TS U2308 ( .A(n1491), .Y(DP_OP_498J314_124_1725_n201) );
INVX2TS U2309 ( .A(n1575), .Y(DP_OP_498J314_124_1725_n81) );
INVX2TS U2310 ( .A(n1492), .Y(DP_OP_498J314_124_1725_n197) );
INVX2TS U2311 ( .A(n1559), .Y(DP_OP_498J314_124_1725_n80) );
INVX2TS U2312 ( .A(n1493), .Y(DP_OP_498J314_124_1725_n82) );
INVX2TS U2313 ( .A(n1562), .Y(DP_OP_498J314_124_1725_n79) );
INVX2TS U2314 ( .A(n1494), .Y(DP_OP_498J314_124_1725_n196) );
INVX2TS U2315 ( .A(n1495), .Y(DP_OP_498J314_124_1725_n193) );
INVX2TS U2316 ( .A(n1556), .Y(DP_OP_498J314_124_1725_n78) );
INVX2TS U2317 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]), .Y(
DP_OP_498J314_124_1725_n195) );
INVX2TS U2318 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]), .Y(
DP_OP_498J314_124_1725_n194) );
INVX2TS U2319 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[11]), .Y(
DP_OP_498J314_124_1725_n192) );
OAI21X1TS U2320 ( .A0(DP_OP_498J314_124_1725_n119), .A1(n1497), .B0(n1496),
.Y(DP_OP_498J314_124_1725_n110) );
OAI21X1TS U2321 ( .A0(n1500), .A1(n1499), .B0(n1498), .Y(
DP_OP_498J314_124_1725_n101) );
OAI32X1TS U2322 ( .A0(n1500), .A1(n1504), .A2(n1518), .B0(n1516), .B1(n1500),
.Y(DP_OP_498J314_124_1725_n91) );
ADDHXLTS U2323 ( .A(DP_OP_498J314_124_1725_n73), .B(n1501), .CO(n1441), .S(
DP_OP_498J314_124_1725_n72) );
OAI32X1TS U2324 ( .A0(n1505), .A1(n1504), .A2(n1503), .B0(n1502), .B1(n1505),
.Y(DP_OP_498J314_124_1725_n90) );
CMPR32X2TS U2325 ( .A(n1508), .B(n1507), .C(n1506), .CO(
DP_OP_498J314_124_1725_n226), .S(DP_OP_498J314_124_1725_n227) );
CMPR32X2TS U2326 ( .A(n1511), .B(n1510), .C(n1509), .CO(
DP_OP_498J314_124_1725_n312), .S(DP_OP_498J314_124_1725_n313) );
CMPR32X2TS U2327 ( .A(n1514), .B(n1513), .C(n1512), .CO(
DP_OP_498J314_124_1725_n221), .S(DP_OP_498J314_124_1725_n222) );
OAI22X1TS U2328 ( .A0(n1518), .A1(n1517), .B0(n1516), .B1(n1515), .Y(n1521)
);
INVX2TS U2329 ( .A(n1519), .Y(n1520) );
CMPR32X2TS U2330 ( .A(n1526), .B(n1525), .C(n1524), .CO(
DP_OP_498J314_124_1725_n324), .S(DP_OP_498J314_124_1725_n325) );
CMPR32X2TS U2331 ( .A(n1529), .B(n1528), .C(n1527), .CO(
DP_OP_498J314_124_1725_n317), .S(DP_OP_498J314_124_1725_n318) );
ADDHXLTS U2332 ( .A(n1531), .B(n1530), .CO(DP_OP_498J314_124_1725_n244), .S(
n1068) );
ADDHXLTS U2333 ( .A(n1533), .B(n1532), .CO(DP_OP_498J314_124_1725_n335), .S(
n1169) );
CMPR32X2TS U2334 ( .A(n1536), .B(n1535), .C(n1534), .CO(
DP_OP_498J314_124_1725_n233), .S(DP_OP_498J314_124_1725_n234) );
ADDHXLTS U2335 ( .A(n1538), .B(n1537), .CO(DP_OP_498J314_124_1725_n331), .S(
DP_OP_498J314_124_1725_n332) );
ADDHXLTS U2336 ( .A(n1540), .B(n1539), .CO(DP_OP_498J314_124_1725_n228), .S(
DP_OP_498J314_124_1725_n229) );
ADDHXLTS U2337 ( .A(n1542), .B(n1541), .CO(DP_OP_498J314_124_1725_n240), .S(
DP_OP_498J314_124_1725_n241) );
ADDHXLTS U2338 ( .A(n1544), .B(n1543), .CO(DP_OP_498J314_124_1725_n235), .S(
DP_OP_498J314_124_1725_n236) );
ADDHXLTS U2339 ( .A(n1546), .B(n1545), .CO(DP_OP_498J314_124_1725_n319), .S(
DP_OP_498J314_124_1725_n320) );
ADDHXLTS U2340 ( .A(n1548), .B(n1547), .CO(DP_OP_498J314_124_1725_n326), .S(
DP_OP_498J314_124_1725_n327) );
INVX2TS U2341 ( .A(n1716), .Y(DP_OP_499J314_125_1651_n98) );
INVX2TS U2342 ( .A(n1706), .Y(DP_OP_499J314_125_1651_n97) );
INVX2TS U2343 ( .A(n1695), .Y(DP_OP_499J314_125_1651_n96) );
INVX2TS U2344 ( .A(n1549), .Y(DP_OP_499J314_125_1651_n121) );
INVX2TS U2345 ( .A(n1550), .Y(DP_OP_499J314_125_1651_n120) );
INVX2TS U2346 ( .A(n1551), .Y(DP_OP_499J314_125_1651_n119) );
INVX2TS U2347 ( .A(n1552), .Y(DP_OP_499J314_125_1651_n95) );
INVX2TS U2348 ( .A(n1689), .Y(DP_OP_499J314_125_1651_n99) );
INVX2TS U2349 ( .A(n1553), .Y(DP_OP_499J314_125_1651_n118) );
INVX2TS U2350 ( .A(n1554), .Y(DP_OP_499J314_125_1651_n122) );
CMPR32X2TS U2351 ( .A(n1557), .B(n1556), .C(n1555), .CO(n1236), .S(n1676) );
INVX2TS U2352 ( .A(n1676), .Y(DP_OP_499J314_125_1651_n107) );
INVX2TS U2353 ( .A(n1713), .Y(DP_OP_499J314_125_1651_n100) );
INVX2TS U2354 ( .A(n1680), .Y(DP_OP_499J314_125_1651_n101) );
INVX2TS U2355 ( .A(n1686), .Y(DP_OP_499J314_125_1651_n103) );
INVX2TS U2356 ( .A(n2033), .Y(DP_OP_499J314_125_1651_n104) );
INVX2TS U2357 ( .A(n1683), .Y(DP_OP_499J314_125_1651_n102) );
INVX2TS U2358 ( .A(n1692), .Y(DP_OP_499J314_125_1651_n105) );
INVX2TS U2359 ( .A(n2031), .Y(DP_OP_499J314_125_1651_n106) );
CMPR32X2TS U2360 ( .A(n1560), .B(n1559), .C(n1558), .CO(n1561), .S(n1677) );
INVX2TS U2361 ( .A(n1677), .Y(DP_OP_499J314_125_1651_n109) );
CMPR32X2TS U2362 ( .A(n1563), .B(n1562), .C(n1561), .CO(n1555), .S(n2037) );
INVX2TS U2363 ( .A(n2037), .Y(DP_OP_499J314_125_1651_n108) );
INVX2TS U2364 ( .A(n1564), .Y(DP_OP_499J314_125_1651_n130) );
INVX2TS U2365 ( .A(n1565), .Y(DP_OP_499J314_125_1651_n129) );
INVX2TS U2366 ( .A(n1566), .Y(DP_OP_499J314_125_1651_n128) );
INVX2TS U2367 ( .A(n1567), .Y(DP_OP_499J314_125_1651_n124) );
INVX2TS U2368 ( .A(n1568), .Y(DP_OP_499J314_125_1651_n125) );
INVX2TS U2369 ( .A(n1569), .Y(DP_OP_499J314_125_1651_n123) );
INVX2TS U2370 ( .A(n1570), .Y(DP_OP_499J314_125_1651_n127) );
INVX2TS U2371 ( .A(n1571), .Y(DP_OP_499J314_125_1651_n126) );
INVX2TS U2372 ( .A(n1572), .Y(DP_OP_499J314_125_1651_n132) );
INVX2TS U2373 ( .A(n1573), .Y(DP_OP_499J314_125_1651_n131) );
CMPR32X2TS U2374 ( .A(n1576), .B(n1575), .C(n1574), .CO(n1558), .S(n1704) );
INVX2TS U2375 ( .A(n1704), .Y(DP_OP_499J314_125_1651_n110) );
INVX2TS U2376 ( .A(n1577), .Y(DP_OP_499J314_125_1651_n133) );
ADDHXLTS U2377 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[7]), .B(n1578), .CO(DP_OP_499J314_125_1651_n81), .S(n1048) );
NOR2X1TS U2378 ( .A(FPMULT_FS_Module_state_reg[1]), .B(
FPMULT_FS_Module_state_reg[0]), .Y(n1812) );
NAND2X1TS U2379 ( .A(n2750), .B(FPMULT_FS_Module_state_reg[0]), .Y(n1836) );
INVX2TS U2380 ( .A(n1836), .Y(n1660) );
NAND2X1TS U2381 ( .A(n1660), .B(n1835), .Y(n1838) );
AOI2BB2XLTS U2382 ( .B0(n997), .B1(FPMULT_FSM_exp_operation_A_S), .A0N(
FPMULT_P_Sgf[47]), .A1N(n1838), .Y(n1579) );
OAI21XLTS U2383 ( .A0(FPMULT_FS_Module_state_reg[0]), .A1(
FPMULT_FS_Module_state_reg[2]), .B0(n1579), .Y(
FPMULT_FS_Module_state_next[0]) );
NOR2X4TS U2384 ( .A(FPMULT_Op_MY[11]), .B(intadd_1057_n1), .Y(n2251) );
INVX2TS U2385 ( .A(intadd_1059_B_2_), .Y(n2240) );
NOR2X1TS U2386 ( .A(n2251), .B(n2240), .Y(DP_OP_496J314_122_3540_n292) );
INVX2TS U2387 ( .A(n2251), .Y(intadd_1060_B_4_) );
NOR2X4TS U2388 ( .A(FPMULT_Op_MX[11]), .B(intadd_1056_n1), .Y(n2249) );
NOR2XLTS U2389 ( .A(n2249), .B(n2251), .Y(intadd_1058_A_8_) );
OR4X2TS U2390 ( .A(Data_2[3]), .B(Data_2[5]), .C(Data_2[22]), .D(Data_2[0]),
.Y(n1581) );
INVX2TS U2391 ( .A(Data_2[14]), .Y(n1584) );
INVX2TS U2392 ( .A(operation[1]), .Y(n2586) );
BUFX6TS U2393 ( .A(n2586), .Y(n2659) );
NOR3X1TS U2394 ( .A(FPSENCOS_cont_var_out[1]), .B(n2659), .C(n2808), .Y(
n1589) );
BUFX4TS U2395 ( .A(n1589), .Y(n2649) );
NAND2X1TS U2396 ( .A(FPSENCOS_cont_var_out[1]), .B(n2808), .Y(n1582) );
NOR2X1TS U2397 ( .A(n2659), .B(n1582), .Y(n1601) );
BUFX3TS U2398 ( .A(n1601), .Y(n2289) );
AOI22X1TS U2399 ( .A0(n2649), .A1(FPSENCOS_d_ff3_sh_y_out[14]), .B0(n2289),
.B1(FPSENCOS_d_ff3_sh_x_out[14]), .Y(n1583) );
NAND2X1TS U2400 ( .A(FPSENCOS_cont_var_out[1]), .B(FPSENCOS_cont_var_out[0]),
.Y(n2569) );
BUFX4TS U2401 ( .A(n1814), .Y(n2626) );
NAND2X1TS U2402 ( .A(n2626), .B(FPSENCOS_d_ff3_LUT_out[5]), .Y(n1598) );
OAI211XLTS U2403 ( .A0(operation[1]), .A1(n1584), .B0(n1583), .C0(n1598),
.Y(add_subt_data2[14]) );
INVX2TS U2404 ( .A(Data_2[13]), .Y(n1586) );
AOI22X1TS U2405 ( .A0(n2649), .A1(FPSENCOS_d_ff3_sh_y_out[13]), .B0(n2289),
.B1(FPSENCOS_d_ff3_sh_x_out[13]), .Y(n1585) );
NAND2X1TS U2406 ( .A(n2626), .B(FPSENCOS_d_ff3_LUT_out[13]), .Y(n1627) );
OAI211XLTS U2407 ( .A0(operation[1]), .A1(n1586), .B0(n1585), .C0(n1627),
.Y(add_subt_data2[13]) );
INVX2TS U2408 ( .A(Data_2[16]), .Y(n1588) );
AOI22X1TS U2409 ( .A0(n2649), .A1(FPSENCOS_d_ff3_sh_y_out[16]), .B0(n2289),
.B1(FPSENCOS_d_ff3_sh_x_out[16]), .Y(n1587) );
NAND2X1TS U2410 ( .A(n2626), .B(FPSENCOS_d_ff3_LUT_out[3]), .Y(n1592) );
OAI211XLTS U2411 ( .A0(operation[1]), .A1(n1588), .B0(n1587), .C0(n1592),
.Y(add_subt_data2[16]) );
INVX2TS U2412 ( .A(Data_2[11]), .Y(n1591) );
BUFX3TS U2413 ( .A(n1589), .Y(n2587) );
AOI22X1TS U2414 ( .A0(n2587), .A1(FPSENCOS_d_ff3_sh_y_out[11]), .B0(n2289),
.B1(FPSENCOS_d_ff3_sh_x_out[11]), .Y(n1590) );
NAND2X1TS U2415 ( .A(n2626), .B(FPSENCOS_d_ff3_LUT_out[7]), .Y(n1595) );
OAI211XLTS U2416 ( .A0(operation[1]), .A1(n1591), .B0(n1590), .C0(n1595),
.Y(add_subt_data2[11]) );
INVX2TS U2417 ( .A(Data_2[3]), .Y(n1594) );
AOI22X1TS U2418 ( .A0(n2587), .A1(FPSENCOS_d_ff3_sh_y_out[3]), .B0(n2289),
.B1(FPSENCOS_d_ff3_sh_x_out[3]), .Y(n1593) );
OAI211XLTS U2419 ( .A0(operation[1]), .A1(n1594), .B0(n1593), .C0(n1592),
.Y(add_subt_data2[3]) );
INVX2TS U2420 ( .A(Data_2[7]), .Y(n1597) );
AOI22X1TS U2421 ( .A0(n2649), .A1(FPSENCOS_d_ff3_sh_y_out[7]), .B0(n2289),
.B1(FPSENCOS_d_ff3_sh_x_out[7]), .Y(n1596) );
OAI211XLTS U2422 ( .A0(operation[1]), .A1(n1597), .B0(n1596), .C0(n1595),
.Y(add_subt_data2[7]) );
INVX2TS U2423 ( .A(Data_2[5]), .Y(n1600) );
AOI22X1TS U2424 ( .A0(n2587), .A1(FPSENCOS_d_ff3_sh_y_out[5]), .B0(n2289),
.B1(FPSENCOS_d_ff3_sh_x_out[5]), .Y(n1599) );
OAI211XLTS U2425 ( .A0(operation[1]), .A1(n1600), .B0(n1599), .C0(n1598),
.Y(add_subt_data2[5]) );
INVX2TS U2426 ( .A(Data_2[19]), .Y(n1603) );
BUFX4TS U2427 ( .A(n2649), .Y(n2662) );
BUFX4TS U2428 ( .A(n1601), .Y(n2633) );
AOI22X1TS U2429 ( .A0(n2662), .A1(FPSENCOS_d_ff3_sh_y_out[19]), .B0(n2633),
.B1(FPSENCOS_d_ff3_sh_x_out[19]), .Y(n1602) );
NAND2X1TS U2430 ( .A(n2626), .B(FPSENCOS_d_ff3_LUT_out[19]), .Y(n1624) );
OAI211XLTS U2431 ( .A0(operation[1]), .A1(n1603), .B0(n1602), .C0(n1624),
.Y(add_subt_data2[19]) );
NAND2X2TS U2432 ( .A(FPADDSUB_Shift_reg_FLAGS_7[1]), .B(
FPADDSUB_ADD_OVRFLW_NRM), .Y(n2143) );
NAND2X1TS U2433 ( .A(n2109), .B(n2106), .Y(n1615) );
NOR2X1TS U2434 ( .A(FPADDSUB_Raw_mant_NRM_SWR[18]), .B(n1615), .Y(n2118) );
NAND2X1TS U2435 ( .A(n2118), .B(n2115), .Y(n1612) );
NOR2X1TS U2436 ( .A(FPADDSUB_Raw_mant_NRM_SWR[14]), .B(n1612), .Y(n1614) );
NAND2X1TS U2437 ( .A(n2122), .B(n1614), .Y(n2124) );
NOR2XLTS U2438 ( .A(FPADDSUB_Raw_mant_NRM_SWR[10]), .B(n2124), .Y(n1605) );
NAND2X1TS U2439 ( .A(n2125), .B(n1605), .Y(n1606) );
NAND2X1TS U2440 ( .A(n2128), .B(n2792), .Y(n2114) );
OA21XLTS U2441 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[3]), .A1(
FPADDSUB_Raw_mant_NRM_SWR[2]), .B0(n2111), .Y(n1608) );
INVX2TS U2442 ( .A(n1606), .Y(n1607) );
OAI31X1TS U2443 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[7]), .A1(n1608), .A2(
FPADDSUB_Raw_mant_NRM_SWR[6]), .B0(n1607), .Y(n2130) );
NOR2X1TS U2444 ( .A(FPADDSUB_Raw_mant_NRM_SWR[24]), .B(
FPADDSUB_Raw_mant_NRM_SWR[25]), .Y(n1610) );
AOI32X1TS U2445 ( .A0(n1611), .A1(n1610), .A2(FPADDSUB_Raw_mant_NRM_SWR[19]),
.B0(n1609), .B1(n1610), .Y(n1618) );
INVX2TS U2446 ( .A(n1615), .Y(n1648) );
NOR2XLTS U2447 ( .A(FPADDSUB_Raw_mant_NRM_SWR[16]), .B(
FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n1613) );
AOI31XLTS U2448 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[15]), .A1(n1648), .A2(n1613),
.B0(n2116), .Y(n1617) );
INVX2TS U2449 ( .A(n1614), .Y(n2121) );
NOR2X1TS U2450 ( .A(FPADDSUB_Raw_mant_NRM_SWR[13]), .B(n2121), .Y(n1647) );
NAND2BXLTS U2451 ( .AN(n2124), .B(FPADDSUB_Raw_mant_NRM_SWR[10]), .Y(n2119)
);
OAI21X1TS U2452 ( .A0(n1615), .A1(n2804), .B0(n2119), .Y(n1646) );
AOI31XLTS U2453 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[11]), .A1(n1647), .A2(n2810),
.B0(n1646), .Y(n1616) );
NAND4XLTS U2454 ( .A(n2130), .B(n1618), .C(n1617), .D(n1616), .Y(
FPADDSUB_LZD_raw_out_EWR[1]) );
OAI22X1TS U2455 ( .A0(intadd_1057_SUM_4_), .A1(n2087), .B0(
intadd_1057_SUM_3_), .B1(n2088), .Y(n1619) );
AOI21X1TS U2456 ( .A0(n2090), .A1(intadd_1057_SUM_4_), .B0(n1619), .Y(n2198)
);
INVX2TS U2457 ( .A(intadd_1059_A_3_), .Y(n1621) );
AOI22X1TS U2458 ( .A0(intadd_1059_A_2_), .A1(intadd_1059_A_3_), .B0(n1621),
.B1(n2276), .Y(n1620) );
INVX2TS U2459 ( .A(intadd_1059_A_4_), .Y(n2268) );
OAI33X4TS U2460 ( .A0(intadd_1059_A_4_), .A1(n2276), .A2(n1621), .B0(n2268),
.B1(intadd_1059_A_2_), .B2(intadd_1059_A_3_), .Y(n2271) );
AOI32X1TS U2461 ( .A0(n2273), .A1(intadd_1059_A_4_), .A2(n2259), .B0(n2271),
.B1(intadd_1059_A_4_), .Y(n2197) );
NOR2X1TS U2462 ( .A(n2198), .B(n2197), .Y(DP_OP_496J314_122_3540_n380) );
INVX2TS U2463 ( .A(intadd_1056_SUM_6_), .Y(n2250) );
NOR2X1TS U2464 ( .A(n2282), .B(n2250), .Y(intadd_1059_B_0_) );
INVX2TS U2465 ( .A(intadd_1057_SUM_6_), .Y(n2248) );
NOR2X1TS U2466 ( .A(n2259), .B(n2248), .Y(intadd_1060_B_0_) );
INVX2TS U2467 ( .A(intadd_1057_SUM_7_), .Y(n2235) );
INVX2TS U2468 ( .A(intadd_1059_CI), .Y(n2242) );
OR4X2TS U2469 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[2]), .C(FPADDSUB_exp_rslt_NRM2_EW1[1]), .D(
FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(n1622) );
OR4X2TS U2470 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[5]), .C(FPADDSUB_exp_rslt_NRM2_EW1[4]), .D(
n1622), .Y(n1623) );
INVX2TS U2471 ( .A(Data_2[22]), .Y(n1626) );
AOI22X1TS U2472 ( .A0(n2649), .A1(FPSENCOS_d_ff3_sh_y_out[22]), .B0(n2633),
.B1(FPSENCOS_d_ff3_sh_x_out[22]), .Y(n1625) );
OAI211XLTS U2473 ( .A0(operation[1]), .A1(n1626), .B0(n1625), .C0(n1624),
.Y(add_subt_data2[22]) );
INVX2TS U2474 ( .A(Data_2[18]), .Y(n1629) );
AOI22X1TS U2475 ( .A0(n2649), .A1(FPSENCOS_d_ff3_sh_y_out[18]), .B0(n2633),
.B1(FPSENCOS_d_ff3_sh_x_out[18]), .Y(n1628) );
OAI211XLTS U2476 ( .A0(operation[1]), .A1(n1629), .B0(n1628), .C0(n1627),
.Y(add_subt_data2[18]) );
INVX2TS U2477 ( .A(Data_2[17]), .Y(n1631) );
AOI22X1TS U2478 ( .A0(n2649), .A1(FPSENCOS_d_ff3_sh_y_out[17]), .B0(n2289),
.B1(FPSENCOS_d_ff3_sh_x_out[17]), .Y(n1630) );
NAND2X1TS U2479 ( .A(n2626), .B(FPSENCOS_d_ff3_LUT_out[15]), .Y(n1634) );
OAI211XLTS U2480 ( .A0(operation[1]), .A1(n1631), .B0(n1630), .C0(n1634),
.Y(add_subt_data2[17]) );
INVX2TS U2481 ( .A(Data_2[20]), .Y(n1633) );
AOI22X1TS U2482 ( .A0(n2649), .A1(FPSENCOS_d_ff3_sh_y_out[20]), .B0(n2633),
.B1(FPSENCOS_d_ff3_sh_x_out[20]), .Y(n1632) );
OAI211XLTS U2483 ( .A0(operation[1]), .A1(n1633), .B0(n1632), .C0(n1634),
.Y(add_subt_data2[20]) );
INVX2TS U2484 ( .A(Data_2[15]), .Y(n1636) );
AOI22X1TS U2485 ( .A0(n2649), .A1(FPSENCOS_d_ff3_sh_y_out[15]), .B0(n2289),
.B1(FPSENCOS_d_ff3_sh_x_out[15]), .Y(n1635) );
OAI211XLTS U2486 ( .A0(operation[1]), .A1(n1636), .B0(n1635), .C0(n1634),
.Y(add_subt_data2[15]) );
INVX2TS U2487 ( .A(Data_2[29]), .Y(n1638) );
AOI22X1TS U2488 ( .A0(n2662), .A1(FPSENCOS_d_ff3_sh_y_out[29]), .B0(n2289),
.B1(FPSENCOS_d_ff3_sh_x_out[29]), .Y(n1637) );
NAND2X1TS U2489 ( .A(n2626), .B(FPSENCOS_d_ff3_LUT_out[27]), .Y(n1641) );
OAI211XLTS U2490 ( .A0(operation[1]), .A1(n1638), .B0(n1637), .C0(n1641),
.Y(add_subt_data2[29]) );
INVX2TS U2491 ( .A(Data_2[28]), .Y(n1640) );
AOI22X1TS U2492 ( .A0(n2662), .A1(FPSENCOS_d_ff3_sh_y_out[28]), .B0(n2633),
.B1(FPSENCOS_d_ff3_sh_x_out[28]), .Y(n1639) );
OAI211XLTS U2493 ( .A0(operation[1]), .A1(n1640), .B0(n1639), .C0(n1641),
.Y(add_subt_data2[28]) );
INVX2TS U2494 ( .A(Data_2[27]), .Y(n1643) );
AOI22X1TS U2495 ( .A0(n2662), .A1(FPSENCOS_d_ff3_sh_y_out[27]), .B0(n2633),
.B1(FPSENCOS_d_ff3_sh_x_out[27]), .Y(n1642) );
OAI211XLTS U2496 ( .A0(operation[1]), .A1(n1643), .B0(n1642), .C0(n1641),
.Y(add_subt_data2[27]) );
NAND2BXLTS U2497 ( .AN(n2114), .B(FPADDSUB_Raw_mant_NRM_SWR[4]), .Y(n2123)
);
AOI21X1TS U2498 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[0]), .A1(n2797), .B0(
FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n1644) );
NAND2X1TS U2499 ( .A(n2111), .B(n2794), .Y(n2131) );
OAI22X1TS U2500 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[5]), .A1(n2123), .B0(n1644),
.B1(n2131), .Y(n1645) );
AOI211X1TS U2501 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[12]), .A1(n1647), .B0(n1646), .C0(n1645), .Y(n2113) );
AOI31XLTS U2502 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[16]), .A1(n1648), .A2(n2798),
.B0(n2116), .Y(n1653) );
AOI22X1TS U2503 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[8]), .A1(n1649), .B0(
FPADDSUB_Raw_mant_NRM_SWR[6]), .B1(n2128), .Y(n1652) );
NAND4XLTS U2504 ( .A(n2113), .B(n1653), .C(n1652), .D(n1651), .Y(
FPADDSUB_LZD_raw_out_EWR[0]) );
NAND2X1TS U2505 ( .A(intadd_1057_SUM_6_), .B(intadd_1059_CI), .Y(n1655) );
NAND2X1TS U2506 ( .A(intadd_1056_SUM_6_), .B(intadd_1057_SUM_7_), .Y(n1654)
);
AOI21X1TS U2507 ( .A0(n1655), .A1(n1654), .B0(intadd_1058_CI), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]) );
AND4X1TS U2508 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[2]), .C(FPADDSUB_exp_rslt_NRM2_EW1[1]), .D(
FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(n1656) );
AND4X1TS U2509 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[5]), .C(FPADDSUB_exp_rslt_NRM2_EW1[4]), .D(
n1656), .Y(n1657) );
AND3X1TS U2510 ( .A(n1658), .B(FPADDSUB_exp_rslt_NRM2_EW1[7]), .C(n1657),
.Y(n2959) );
NAND3XLTS U2511 ( .A(n2750), .B(n996), .C(n1834), .Y(n1667) );
INVX2TS U2512 ( .A(n1667), .Y(n1661) );
AOI22X1TS U2513 ( .A0(n2954), .A1(n2953), .B0(r_mode[0]), .B1(r_mode[1]),
.Y(n1659) );
OAI221X1TS U2514 ( .A0(n2859), .A1(r_mode[1]), .B0(n2955), .B1(r_mode[0]),
.C0(n1659), .Y(n1668) );
NAND2X1TS U2515 ( .A(FPMULT_FS_Module_state_reg[3]), .B(
FPMULT_FS_Module_state_reg[2]), .Y(n1671) );
AOI22X1TS U2516 ( .A0(n1661), .A1(n1668), .B0(n1660), .B1(n1671), .Y(n1662)
);
INVX2TS U2517 ( .A(intadd_1057_SUM_3_), .Y(n2263) );
AOI22X1TS U2518 ( .A0(intadd_1057_SUM_3_), .A1(n2276), .B0(intadd_1059_A_2_),
.B1(n2263), .Y(n2278) );
OAI221X4TS U2519 ( .A0(n2057), .A1(n2276), .B0(intadd_1059_A_1_), .B1(
intadd_1059_A_2_), .C0(n2281), .Y(n2279) );
INVX2TS U2520 ( .A(n2279), .Y(n2095) );
INVX2TS U2521 ( .A(intadd_1057_SUM_2_), .Y(n2265) );
AOI22X1TS U2522 ( .A0(intadd_1059_A_2_), .A1(intadd_1057_SUM_2_), .B0(n2265),
.B1(n2276), .Y(n2096) );
INVX2TS U2523 ( .A(n2249), .Y(intadd_1059_B_4_) );
INVX2TS U2524 ( .A(intadd_1059_SUM_2_), .Y(n2218) );
INVX2TS U2525 ( .A(intadd_1060_SUM_2_), .Y(n2220) );
INVX2TS U2526 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[6]), .Y(n1663) );
NAND3X1TS U2527 ( .A(intadd_1060_SUM_2_), .B(intadd_1059_SUM_2_), .C(n1663),
.Y(n2212) );
OA21XLTS U2528 ( .A0(n1664), .A1(n1663), .B0(n2212), .Y(
DP_OP_496J314_122_3540_n97) );
NAND2X1TS U2529 ( .A(n2830), .B(n2748), .Y(n1832) );
NAND2X1TS U2530 ( .A(n2666), .B(n2747), .Y(n1839) );
OAI31X1TS U2531 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(
FPSENCOS_cont_iter_out[1]), .A2(n2747), .B0(n1839), .Y(n856) );
INVX2TS U2532 ( .A(n2704), .Y(n865) );
OAI31X4TS U2533 ( .A0(FPSENCOS_cont_iter_out[2]), .A1(
FPSENCOS_cont_iter_out[3]), .A2(n2761), .B0(n865), .Y(n2706) );
OAI21XLTS U2534 ( .A0(n2704), .A1(n2800), .B0(n2706), .Y(n859) );
NAND2X1TS U2535 ( .A(n2747), .B(FPSENCOS_cont_iter_out[3]), .Y(n1840) );
OAI21XLTS U2536 ( .A0(n2800), .A1(n2706), .B0(n1840), .Y(n860) );
INVX2TS U2537 ( .A(n1840), .Y(n1736) );
NAND2X1TS U2538 ( .A(n865), .B(FPSENCOS_cont_iter_out[0]), .Y(n2709) );
INVX2TS U2539 ( .A(n2709), .Y(n2708) );
NOR2X1TS U2540 ( .A(n1736), .B(n2708), .Y(n2705) );
OAI211X1TS U2541 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(n2761), .B0(n2747),
.C0(n2800), .Y(n2707) );
OAI21XLTS U2542 ( .A0(n2705), .A1(n2800), .B0(n2707), .Y(n854) );
OR2X1TS U2543 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .Y(n1665) );
NAND2X1TS U2544 ( .A(n1666), .B(n993), .Y(n1809) );
OAI21XLTS U2545 ( .A0(n1668), .A1(n1667), .B0(n2837), .Y(n834) );
NAND2BXLTS U2546 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .B(n1811),
.Y(n1730) );
NOR2X1TS U2547 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .B(n1730),
.Y(n1927) );
NAND3BX1TS U2548 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .C(n1927), .Y(n2562) );
INVX2TS U2549 ( .A(n2562), .Y(n1674) );
BUFX3TS U2550 ( .A(n1670), .Y(n2703) );
NAND2X1TS U2551 ( .A(n2586), .B(operation[2]), .Y(n2711) );
BUFX4TS U2552 ( .A(n1672), .Y(n2700) );
AOI22X1TS U2553 ( .A0(n2703), .A1(ready_add_subt), .B0(n2714), .B1(n2700),
.Y(n1673) );
OAI2BB1X1TS U2554 ( .A0N(n1674), .A1N(n1669), .B0(n1673), .Y(operation_ready) );
NOR4X1TS U2555 ( .A(n1678), .B(n1677), .C(n1676), .D(n1675), .Y(n1725) );
CMPR32X2TS U2556 ( .A(n1681), .B(n1680), .C(n1679), .CO(n1712), .S(n1703) );
CMPR32X2TS U2557 ( .A(n1684), .B(n1683), .C(n1682), .CO(n1679), .S(n1702) );
CMPR32X2TS U2558 ( .A(n1687), .B(n1686), .C(n1685), .CO(n1682), .S(n1700) );
CMPR32X2TS U2559 ( .A(n1690), .B(n1689), .C(n1688), .CO(n1715), .S(n1699) );
CMPR32X2TS U2560 ( .A(n1693), .B(n1692), .C(n1691), .CO(n2032), .S(n1698) );
CMPR32X2TS U2561 ( .A(n1696), .B(n1695), .C(n1694), .CO(n1287), .S(n1697) );
OR4X2TS U2562 ( .A(n1700), .B(n1699), .C(n1698), .D(n1697), .Y(n1701) );
NOR4X1TS U2563 ( .A(n1704), .B(n1703), .C(n1702), .D(n1701), .Y(n1724) );
CMPR32X2TS U2564 ( .A(n1707), .B(n1706), .C(n1705), .CO(n1694), .S(n1709) );
NOR4X1TS U2565 ( .A(n1711), .B(n1710), .C(n1709), .D(n1708), .Y(n1723) );
CMPR32X2TS U2566 ( .A(n1714), .B(n1713), .C(n1712), .CO(n1688), .S(n1720) );
CMPR32X2TS U2567 ( .A(n1717), .B(n1716), .C(n1715), .CO(n1705), .S(n1719) );
NOR4X1TS U2568 ( .A(n1721), .B(n1720), .C(n1719), .D(n1718), .Y(n1722) );
AND4X1TS U2569 ( .A(n1725), .B(n1724), .C(n1723), .D(n1722), .Y(n2878) );
INVX2TS U2570 ( .A(intadd_1057_SUM_5_), .Y(n2274) );
AOI22X1TS U2571 ( .A0(intadd_1059_A_4_), .A1(intadd_1057_SUM_5_), .B0(n2274),
.B1(n2268), .Y(n2262) );
AOI22X1TS U2572 ( .A0(intadd_1059_A_4_), .A1(n2273), .B0(n2271), .B1(n2262),
.Y(n2082) );
INVX2TS U2573 ( .A(intadd_1057_SUM_4_), .Y(n2275) );
OAI21X4TS U2574 ( .A0(intadd_1059_A_4_), .A1(intadd_1056_SUM_5_), .B0(n2258),
.Y(n2260) );
OAI22X1TS U2575 ( .A0(n2275), .A1(n2260), .B0(n2263), .B1(n2258), .Y(n1726)
);
CMPR32X2TS U2576 ( .A(DP_OP_496J314_122_3540_n359), .B(n2082), .C(n1726),
.CO(intadd_1055_B_9_), .S(intadd_1055_B_8_) );
NOR2X1TS U2577 ( .A(n2250), .B(n2248), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]) );
AOI21X1TS U2578 ( .A0(n2259), .A1(n2248), .B0(intadd_1060_B_0_), .Y(n2067)
);
INVX2TS U2579 ( .A(n2067), .Y(n2071) );
AOI21X1TS U2580 ( .A0(n2282), .A1(n2250), .B0(intadd_1059_B_0_), .Y(n2066)
);
INVX2TS U2581 ( .A(n2066), .Y(n2072) );
OA22X1TS U2582 ( .A0(n2071), .A1(n2072), .B0(n1727), .B1(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]), .Y(
intadd_1054_B_0_) );
CLKBUFX2TS U2583 ( .A(n1731), .Y(n1729) );
BUFX3TS U2584 ( .A(n917), .Y(n2926) );
BUFX3TS U2585 ( .A(n2945), .Y(n2927) );
BUFX3TS U2586 ( .A(n918), .Y(n2928) );
BUFX3TS U2587 ( .A(n2936), .Y(n2924) );
BUFX3TS U2588 ( .A(n918), .Y(n2942) );
CLKBUFX2TS U2589 ( .A(n917), .Y(n2946) );
BUFX3TS U2590 ( .A(n1733), .Y(n2931) );
NAND2BXLTS U2591 ( .AN(n967), .B(n1728), .Y(n1732) );
BUFX3TS U2592 ( .A(n2925), .Y(n2937) );
BUFX3TS U2593 ( .A(n2925), .Y(n2939) );
BUFX3TS U2594 ( .A(n1831), .Y(n2906) );
BUFX3TS U2595 ( .A(n2903), .Y(n2896) );
INVX2TS U2596 ( .A(n1835), .Y(n1735) );
OAI32X1TS U2597 ( .A0(n2750), .A1(FPMULT_FS_Module_state_reg[2]), .A2(n996),
.B0(FPMULT_FS_Module_state_reg[1]), .B1(n1735), .Y(
FPMULT_FS_Module_state_next[2]) );
NOR2X1TS U2598 ( .A(FPMULT_Exp_module_Overflow_flag_A), .B(
FPMULT_exp_oper_result[8]), .Y(n2452) );
OR2X1TS U2599 ( .A(n1833), .B(FPMULT_exp_oper_result[6]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[6]) );
OR2X1TS U2600 ( .A(n1833), .B(FPMULT_exp_oper_result[7]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[7]) );
OR2X1TS U2601 ( .A(n1833), .B(FPMULT_exp_oper_result[0]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[0]) );
OR2X1TS U2602 ( .A(n1833), .B(FPMULT_exp_oper_result[2]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[2]) );
OR2X1TS U2603 ( .A(n1833), .B(FPMULT_exp_oper_result[1]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[1]) );
OR2X1TS U2604 ( .A(n1833), .B(FPMULT_exp_oper_result[3]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[3]) );
OR2X1TS U2605 ( .A(n1833), .B(FPMULT_exp_oper_result[5]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[5]) );
OR2X1TS U2606 ( .A(n1833), .B(FPMULT_exp_oper_result[4]), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[4]) );
NAND3XLTS U2607 ( .A(FPMULT_FS_Module_state_reg[1]), .B(n1834), .C(n996),
.Y(n2561) );
OAI22X1TS U2608 ( .A0(FPMULT_FS_Module_state_reg[0]), .A1(n1735), .B0(n2561),
.B1(n2774), .Y(FPMULT_FSM_load_second_step) );
NAND2X1TS U2609 ( .A(n1851), .B(n2709), .Y(n851) );
NOR2XLTS U2610 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n1737) );
NOR2BX2TS U2611 ( .AN(FPADDSUB_bit_shift_SHT2), .B(n1783), .Y(n1779) );
NAND2BX2TS U2612 ( .AN(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n1781) );
NAND2X1TS U2613 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(n2815), .Y(n1757)
);
INVX1TS U2614 ( .A(FPADDSUB_Data_array_SWR[51]), .Y(n1790) );
OAI22X1TS U2615 ( .A0(n1781), .A1(n2835), .B0(n1757), .B1(n1790), .Y(n1739)
);
NOR2BX1TS U2616 ( .AN(n1783), .B(FPADDSUB_shift_value_SHT2_EWR[4]), .Y(n1741) );
AOI22X1TS U2617 ( .A0(n1740), .A1(FPADDSUB_Data_array_SWR[31]), .B0(n1888),
.B1(FPADDSUB_Data_array_SWR[27]), .Y(n1745) );
AOI22X1TS U2618 ( .A0(n1742), .A1(FPADDSUB_Data_array_SWR[39]), .B0(n1743),
.B1(FPADDSUB_Data_array_SWR[35]), .Y(n1744) );
OAI211X1TS U2619 ( .A0(n1806), .A1(n2811), .B0(n1745), .C0(n1744), .Y(n1863)
);
NAND2X1TS U2620 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(
FPADDSUB_bit_shift_SHT2), .Y(n1762) );
AOI21X1TS U2621 ( .A0(n1894), .A1(n1863), .B0(n1746), .Y(n1747) );
OAI21X1TS U2622 ( .A0(n1865), .A1(n1738), .B0(n1747), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[24]) );
NOR2XLTS U2623 ( .A(n2958), .B(n2959), .Y(n1748) );
CLKAND2X2TS U2624 ( .A(n2548), .B(FPADDSUB_sftr_odat_SHT2_SWR[24]), .Y(
FPADDSUB_formatted_number_W[22]) );
AOI22X1TS U2625 ( .A0(n1742), .A1(FPADDSUB_Data_array_SWR[40]), .B0(n1743),
.B1(FPADDSUB_Data_array_SWR[36]), .Y(n1752) );
AOI22X1TS U2626 ( .A0(n1740), .A1(FPADDSUB_Data_array_SWR[32]), .B0(n1888),
.B1(FPADDSUB_Data_array_SWR[28]), .Y(n1751) );
OAI211X1TS U2627 ( .A0(n1900), .A1(n2811), .B0(n1752), .C0(n1751), .Y(n1755)
);
AOI21X1TS U2628 ( .A0(n1898), .A1(n1755), .B0(n1753), .Y(n1754) );
OAI21X1TS U2629 ( .A0(n1879), .A1(n1749), .B0(n1754), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[2]) );
CLKAND2X2TS U2630 ( .A(n2548), .B(FPADDSUB_sftr_odat_SHT2_SWR[2]), .Y(
FPADDSUB_formatted_number_W[0]) );
AOI21X1TS U2631 ( .A0(n1894), .A1(n1755), .B0(n1746), .Y(n1756) );
OAI21X1TS U2632 ( .A0(n1879), .A1(n1738), .B0(n1756), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[23]) );
CLKAND2X2TS U2633 ( .A(n2548), .B(FPADDSUB_sftr_odat_SHT2_SWR[23]), .Y(
FPADDSUB_formatted_number_W[21]) );
OAI22X1TS U2634 ( .A0(n1781), .A1(n2842), .B0(n1757), .B1(n2772), .Y(n1758)
);
AOI22X1TS U2635 ( .A0(n1740), .A1(FPADDSUB_Data_array_SWR[39]), .B0(n1743),
.B1(FPADDSUB_Data_array_SWR[43]), .Y(n1760) );
AOI22X1TS U2636 ( .A0(n1888), .A1(FPADDSUB_Data_array_SWR[35]), .B0(n1742),
.B1(FPADDSUB_Data_array_SWR[47]), .Y(n1759) );
AOI21X1TS U2637 ( .A0(n1894), .A1(n1787), .B0(n1746), .Y(n1761) );
OAI21X1TS U2638 ( .A0(n1859), .A1(n1738), .B0(n1761), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[16]) );
CLKAND2X2TS U2639 ( .A(n2548), .B(FPADDSUB_sftr_odat_SHT2_SWR[16]), .Y(
FPADDSUB_formatted_number_W[14]) );
INVX2TS U2640 ( .A(n1762), .Y(n1795) );
AOI22X1TS U2641 ( .A0(n1740), .A1(FPADDSUB_Data_array_SWR[40]), .B0(n1888),
.B1(FPADDSUB_Data_array_SWR[36]), .Y(n1763) );
OAI21XLTS U2642 ( .A0(n2831), .A1(n1793), .B0(n1763), .Y(n1764) );
OR2X1TS U2643 ( .A(n1765), .B(n1795), .Y(n1770) );
AO22XLTS U2644 ( .A0(n1740), .A1(FPADDSUB_Data_array_SWR[45]), .B0(n1888),
.B1(FPADDSUB_Data_array_SWR[41]), .Y(n1766) );
AOI211X1TS U2645 ( .A0(n1743), .A1(FPADDSUB_Data_array_SWR[49]), .B0(n1770),
.C0(n1766), .Y(n1803) );
AOI22X1TS U2646 ( .A0(n1894), .A1(n1802), .B0(n1803), .B1(n1898), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[15]) );
CLKAND2X2TS U2647 ( .A(n2548), .B(FPADDSUB_sftr_odat_SHT2_SWR[15]), .Y(
FPADDSUB_formatted_number_W[13]) );
AOI22X1TS U2648 ( .A0(n1740), .A1(FPADDSUB_Data_array_SWR[41]), .B0(n1888),
.B1(FPADDSUB_Data_array_SWR[37]), .Y(n1767) );
OAI21XLTS U2649 ( .A0(n1793), .A1(n2832), .B0(n1767), .Y(n1768) );
AO22XLTS U2650 ( .A0(FPADDSUB_Data_array_SWR[44]), .A1(n1740), .B0(n1888),
.B1(FPADDSUB_Data_array_SWR[40]), .Y(n1769) );
AOI211X1TS U2651 ( .A0(FPADDSUB_Data_array_SWR[48]), .A1(n1743), .B0(n1770),
.C0(n1769), .Y(n1808) );
AOI22X1TS U2652 ( .A0(n1894), .A1(n1807), .B0(n1808), .B1(n1898), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[14]) );
CLKAND2X2TS U2653 ( .A(n2548), .B(FPADDSUB_sftr_odat_SHT2_SWR[14]), .Y(
FPADDSUB_formatted_number_W[12]) );
AOI22X1TS U2654 ( .A0(n1742), .A1(FPADDSUB_Data_array_SWR[46]), .B0(n1743),
.B1(FPADDSUB_Data_array_SWR[42]), .Y(n1772) );
AOI22X1TS U2655 ( .A0(n1740), .A1(FPADDSUB_Data_array_SWR[38]), .B0(n1888),
.B1(FPADDSUB_Data_array_SWR[34]), .Y(n1771) );
AOI21X1TS U2656 ( .A0(n1898), .A1(n1804), .B0(n1753), .Y(n1773) );
OAI21X1TS U2657 ( .A0(n1806), .A1(n1749), .B0(n1773), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[8]) );
CLKAND2X2TS U2658 ( .A(n2548), .B(FPADDSUB_sftr_odat_SHT2_SWR[8]), .Y(
FPADDSUB_formatted_number_W[6]) );
AOI22X1TS U2659 ( .A0(n1742), .A1(FPADDSUB_Data_array_SWR[43]), .B0(n1743),
.B1(FPADDSUB_Data_array_SWR[39]), .Y(n1777) );
AOI22X1TS U2660 ( .A0(n1740), .A1(FPADDSUB_Data_array_SWR[35]), .B0(n1888),
.B1(FPADDSUB_Data_array_SWR[31]), .Y(n1776) );
OAI211X1TS U2661 ( .A0(n1887), .A1(n2811), .B0(n1777), .C0(n1776), .Y(n1798)
);
AOI21X1TS U2662 ( .A0(n1898), .A1(n1798), .B0(n1753), .Y(n1778) );
OAI21X1TS U2663 ( .A0(n1883), .A1(n1749), .B0(n1778), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[5]) );
CLKAND2X2TS U2664 ( .A(n2548), .B(FPADDSUB_sftr_odat_SHT2_SWR[5]), .Y(
FPADDSUB_formatted_number_W[3]) );
AOI22X1TS U2665 ( .A0(n1742), .A1(FPADDSUB_Data_array_SWR[41]), .B0(n1743),
.B1(FPADDSUB_Data_array_SWR[37]), .Y(n1785) );
AOI22X1TS U2666 ( .A0(n1740), .A1(FPADDSUB_Data_array_SWR[33]), .B0(n1888),
.B1(FPADDSUB_Data_array_SWR[29]), .Y(n1784) );
OAI211X1TS U2667 ( .A0(n1896), .A1(n2811), .B0(n1785), .C0(n1784), .Y(n1800)
);
AOI21X1TS U2668 ( .A0(n1898), .A1(n1800), .B0(n1753), .Y(n1786) );
OAI21X1TS U2669 ( .A0(n1749), .A1(n1891), .B0(n1786), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[3]) );
CLKAND2X2TS U2670 ( .A(n2548), .B(FPADDSUB_sftr_odat_SHT2_SWR[3]), .Y(
FPADDSUB_formatted_number_W[1]) );
AOI21X1TS U2671 ( .A0(n1898), .A1(n1787), .B0(n1753), .Y(n1788) );
OAI21X1TS U2672 ( .A0(n1859), .A1(n1749), .B0(n1788), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[9]) );
CLKAND2X2TS U2673 ( .A(n2548), .B(FPADDSUB_sftr_odat_SHT2_SWR[9]), .Y(
FPADDSUB_formatted_number_W[7]) );
AOI22X1TS U2674 ( .A0(n1740), .A1(FPADDSUB_Data_array_SWR[43]), .B0(n1888),
.B1(FPADDSUB_Data_array_SWR[39]), .Y(n1789) );
OAI21XLTS U2675 ( .A0(n1793), .A1(n1790), .B0(n1789), .Y(n1791) );
AOI211X1TS U2676 ( .A0(n1743), .A1(FPADDSUB_Data_array_SWR[47]), .B0(n1795),
.C0(n1791), .Y(n1796) );
AOI22X1TS U2677 ( .A0(n1740), .A1(FPADDSUB_Data_array_SWR[42]), .B0(n1888),
.B1(FPADDSUB_Data_array_SWR[38]), .Y(n1792) );
AOI211X1TS U2678 ( .A0(n1743), .A1(FPADDSUB_Data_array_SWR[46]), .B0(n1795),
.C0(n1794), .Y(n1797) );
AOI22X1TS U2679 ( .A0(n1894), .A1(n1796), .B0(n1797), .B1(n1898), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[12]) );
CLKAND2X2TS U2680 ( .A(n2548), .B(FPADDSUB_sftr_odat_SHT2_SWR[12]), .Y(
FPADDSUB_formatted_number_W[10]) );
AOI22X1TS U2681 ( .A0(n1894), .A1(n1797), .B0(n1796), .B1(n1898), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[13]) );
CLKAND2X2TS U2682 ( .A(n2548), .B(FPADDSUB_sftr_odat_SHT2_SWR[13]), .Y(
FPADDSUB_formatted_number_W[11]) );
AOI21X1TS U2683 ( .A0(n1894), .A1(n1798), .B0(n1746), .Y(n1799) );
OAI21X1TS U2684 ( .A0(n1883), .A1(n1738), .B0(n1799), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[20]) );
CLKAND2X2TS U2685 ( .A(n2548), .B(FPADDSUB_sftr_odat_SHT2_SWR[20]), .Y(
FPADDSUB_formatted_number_W[18]) );
AOI21X1TS U2686 ( .A0(n1894), .A1(n1800), .B0(n1746), .Y(n1801) );
OAI21X1TS U2687 ( .A0(n1891), .A1(n1738), .B0(n1801), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[22]) );
CLKAND2X2TS U2688 ( .A(n2548), .B(FPADDSUB_sftr_odat_SHT2_SWR[22]), .Y(
FPADDSUB_formatted_number_W[20]) );
AOI22X1TS U2689 ( .A0(n1894), .A1(n1803), .B0(n1802), .B1(n1898), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[10]) );
CLKAND2X2TS U2690 ( .A(n2548), .B(FPADDSUB_sftr_odat_SHT2_SWR[10]), .Y(
FPADDSUB_formatted_number_W[8]) );
AOI21X1TS U2691 ( .A0(n1894), .A1(n1804), .B0(n1746), .Y(n1805) );
OAI21X1TS U2692 ( .A0(n1806), .A1(n1738), .B0(n1805), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[17]) );
CLKAND2X2TS U2693 ( .A(n2548), .B(FPADDSUB_sftr_odat_SHT2_SWR[17]), .Y(
FPADDSUB_formatted_number_W[15]) );
AOI22X1TS U2694 ( .A0(n1894), .A1(n1808), .B0(n1807), .B1(n1898), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[11]) );
CLKAND2X2TS U2695 ( .A(n2548), .B(FPADDSUB_sftr_odat_SHT2_SWR[11]), .Y(
FPADDSUB_formatted_number_W[9]) );
NOR2X1TS U2696 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .B(n1809),
.Y(n1928) );
NAND3BXLTS U2697 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .C(n1928), .Y(n1909) );
NOR2XLTS U2698 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .Y(n1810) );
NAND4X1TS U2699 ( .A(n1811), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]),
.C(n1810), .D(n2806), .Y(n2566) );
NAND2X1TS U2700 ( .A(n1909), .B(n2566), .Y(FPSENCOS_enab_d_ff_RB1) );
INVX2TS U2701 ( .A(n1812), .Y(n1813) );
NOR2X1TS U2702 ( .A(n1813), .B(n1832), .Y(n2713) );
BUFX6TS U2703 ( .A(n2659), .Y(n2642) );
AOI22X1TS U2704 ( .A0(FPSENCOS_d_ff2_Y[10]), .A1(n2660), .B0(Data_1[10]),
.B1(n2642), .Y(n1816) );
AOI22X1TS U2705 ( .A0(n2656), .A1(FPSENCOS_d_ff2_X[10]), .B0(n1814), .B1(
FPSENCOS_d_ff2_Z[10]), .Y(n1815) );
NAND2X1TS U2706 ( .A(n1816), .B(n1815), .Y(add_subt_data1[10]) );
BUFX4TS U2707 ( .A(n2633), .Y(n2654) );
AOI22X1TS U2708 ( .A0(FPSENCOS_d_ff2_Y[19]), .A1(n2654), .B0(Data_1[19]),
.B1(n2642), .Y(n1818) );
BUFX3TS U2709 ( .A(n2626), .Y(n2655) );
AOI22X1TS U2710 ( .A0(n2656), .A1(FPSENCOS_d_ff2_X[19]), .B0(n2655), .B1(
FPSENCOS_d_ff2_Z[19]), .Y(n1817) );
NAND2X1TS U2711 ( .A(n1818), .B(n1817), .Y(add_subt_data1[19]) );
AOI22X1TS U2712 ( .A0(FPSENCOS_d_ff2_Y[23]), .A1(n2654), .B0(Data_1[23]),
.B1(n2659), .Y(n1820) );
AOI22X1TS U2713 ( .A0(n2656), .A1(FPSENCOS_d_ff2_X[23]), .B0(n2655), .B1(
FPSENCOS_d_ff2_Z[23]), .Y(n1819) );
NAND2X1TS U2714 ( .A(n1820), .B(n1819), .Y(add_subt_data1[23]) );
AOI22X1TS U2715 ( .A0(FPSENCOS_d_ff2_Y[22]), .A1(n2654), .B0(Data_1[22]),
.B1(n2659), .Y(n1822) );
AOI22X1TS U2716 ( .A0(n2656), .A1(FPSENCOS_d_ff2_X[22]), .B0(n2655), .B1(
FPSENCOS_d_ff2_Z[22]), .Y(n1821) );
NAND2X1TS U2717 ( .A(n1822), .B(n1821), .Y(add_subt_data1[22]) );
AOI22X1TS U2718 ( .A0(FPSENCOS_d_ff2_Y[30]), .A1(n2654), .B0(Data_1[30]),
.B1(n2659), .Y(n1824) );
AOI22X1TS U2719 ( .A0(n2656), .A1(FPSENCOS_d_ff2_X[30]), .B0(n2655), .B1(
FPSENCOS_d_ff2_Z[30]), .Y(n1823) );
NAND2X1TS U2720 ( .A(n1824), .B(n1823), .Y(add_subt_data1[30]) );
AOI22X1TS U2721 ( .A0(FPSENCOS_d_ff2_Y[28]), .A1(n2654), .B0(Data_1[28]),
.B1(n2659), .Y(n1826) );
AOI22X1TS U2722 ( .A0(n2662), .A1(FPSENCOS_d_ff2_X[28]), .B0(n2655), .B1(
FPSENCOS_d_ff2_Z[28]), .Y(n1825) );
NAND2X1TS U2723 ( .A(n1826), .B(n1825), .Y(add_subt_data1[28]) );
AOI22X1TS U2724 ( .A0(FPSENCOS_d_ff2_Y[21]), .A1(n2654), .B0(Data_1[21]),
.B1(n2642), .Y(n1828) );
AOI22X1TS U2725 ( .A0(n2662), .A1(FPSENCOS_d_ff2_X[21]), .B0(n2655), .B1(
FPSENCOS_d_ff2_Z[21]), .Y(n1827) );
NAND2X1TS U2726 ( .A(n1828), .B(n1827), .Y(add_subt_data1[21]) );
AOI22X1TS U2727 ( .A0(FPSENCOS_d_ff3_sh_x_out[0]), .A1(n2654), .B0(Data_2[0]), .B1(n2586), .Y(n1830) );
AOI22X1TS U2728 ( .A0(n2662), .A1(FPSENCOS_d_ff3_sh_y_out[0]), .B0(n2655),
.B1(FPSENCOS_d_ff3_LUT_out[0]), .Y(n1829) );
NAND2X1TS U2729 ( .A(n1830), .B(n1829), .Y(add_subt_data2[0]) );
INVX4TS U2730 ( .A(n1943), .Y(n2921) );
NOR2X1TS U2731 ( .A(n2259), .B(n2260), .Y(DP_OP_496J314_122_3540_n394) );
INVX2TS U2732 ( .A(intadd_1059_SUM_0_), .Y(n2223) );
INVX2TS U2733 ( .A(intadd_1060_SUM_0_), .Y(n2225) );
INVX2TS U2734 ( .A(n2229), .Y(n2228) );
NOR2X1TS U2735 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[3]), .B(n2228), .Y(DP_OP_496J314_122_3540_n121) );
INVX2TS U2736 ( .A(intadd_1059_B_1_), .Y(n2239) );
BUFX3TS U2737 ( .A(n2923), .Y(n2918) );
BUFX3TS U2738 ( .A(n2923), .Y(n2919) );
BUFX3TS U2739 ( .A(n2923), .Y(n2920) );
BUFX3TS U2740 ( .A(n1831), .Y(n2891) );
BUFX3TS U2741 ( .A(n2923), .Y(n2911) );
BUFX3TS U2742 ( .A(n2923), .Y(n2914) );
BUFX3TS U2743 ( .A(n1831), .Y(n2907) );
BUFX3TS U2744 ( .A(n2923), .Y(n2916) );
BUFX3TS U2745 ( .A(n1831), .Y(n2895) );
BUFX3TS U2746 ( .A(n2923), .Y(n2912) );
BUFX3TS U2747 ( .A(n1831), .Y(n2900) );
BUFX3TS U2748 ( .A(n2923), .Y(n2913) );
NAND2X1TS U2749 ( .A(n2833), .B(FPSENCOS_cont_iter_out[0]), .Y(
intadd_1062_CI) );
OAI21XLTS U2750 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n2833), .B0(
intadd_1062_CI), .Y(FPSENCOS_sh_exp_y[0]) );
NAND2X1TS U2751 ( .A(n2834), .B(FPSENCOS_cont_iter_out[0]), .Y(
intadd_1061_CI) );
NAND2X1TS U2752 ( .A(n2863), .B(n2775), .Y(n2184) );
OAI21XLTS U2753 ( .A0(n2775), .A1(n2863), .B0(n2184), .Y(
FPMULT_Adder_M_result_A_adder[1]) );
NAND2X1TS U2754 ( .A(FPADDSUB_DmP_EXP_EWSW[23]), .B(n992), .Y(n1842) );
NOR2XLTS U2755 ( .A(n1836), .B(n1832), .Y(FPMULT_FSM_first_phase_load) );
NOR2XLTS U2756 ( .A(n2863), .B(n1833), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[1]) );
INVX2TS U2757 ( .A(FPMULT_Sgf_normalized_result[7]), .Y(n2178) );
NOR2XLTS U2758 ( .A(n2178), .B(n1833), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[7]) );
INVX2TS U2759 ( .A(FPMULT_Sgf_normalized_result[21]), .Y(n2157) );
NOR2XLTS U2760 ( .A(n2157), .B(n1833), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[21]) );
INVX2TS U2761 ( .A(FPMULT_Sgf_normalized_result[5]), .Y(n2181) );
NOR2XLTS U2762 ( .A(n2181), .B(n1833), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[5]) );
NOR2XLTS U2763 ( .A(n2182), .B(n1833), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[3]) );
NOR2XLTS U2764 ( .A(n2775), .B(n1833), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[0]) );
INVX2TS U2765 ( .A(FPMULT_Sgf_normalized_result[17]), .Y(n2163) );
BUFX4TS U2766 ( .A(n1833), .Y(n2549) );
NOR2XLTS U2767 ( .A(n2163), .B(n2549), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[17]) );
INVX2TS U2768 ( .A(FPMULT_Sgf_normalized_result[11]), .Y(n2172) );
NOR2XLTS U2769 ( .A(n2172), .B(n2549), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[11]) );
INVX2TS U2770 ( .A(FPMULT_Sgf_normalized_result[15]), .Y(n2166) );
INVX2TS U2771 ( .A(FPMULT_Sgf_normalized_result[19]), .Y(n2160) );
NOR2XLTS U2772 ( .A(n2160), .B(n2549), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[19]) );
INVX2TS U2773 ( .A(FPMULT_Sgf_normalized_result[13]), .Y(n2169) );
NOR2XLTS U2774 ( .A(n2169), .B(n2549), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[13]) );
INVX2TS U2775 ( .A(FPMULT_Sgf_normalized_result[9]), .Y(n2175) );
NOR2XLTS U2776 ( .A(n2175), .B(n2549), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[9]) );
INVX2TS U2777 ( .A(n1834), .Y(n1837) );
NOR3XLTS U2778 ( .A(n2750), .B(n996), .C(n1837), .Y(
FPMULT_FSM_final_result_load) );
INVX2TS U2779 ( .A(intadd_1063_SUM_0_), .Y(FPADDSUB_Shift_amount_EXP_EW[1])
);
NOR2X1TS U2780 ( .A(FPSENCOS_cont_iter_out[0]), .B(FPSENCOS_cont_iter_out[1]), .Y(n1841) );
NOR2XLTS U2781 ( .A(n2666), .B(n1841), .Y(FPSENCOS_ITER_CONT_N3) );
INVX2TS U2782 ( .A(FPMULT_FSM_exp_operation_A_S), .Y(n2145) );
NAND2X1TS U2783 ( .A(FPMULT_FS_Module_state_reg[1]), .B(n1835), .Y(n2560) );
OAI21XLTS U2784 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(
n2716), .B0(n2451), .Y(n874) );
OAI21XLTS U2785 ( .A0(n2704), .A1(FPSENCOS_cont_iter_out[1]), .B0(n1851),
.Y(n864) );
INVX2TS U2786 ( .A(intadd_1063_SUM_1_), .Y(FPADDSUB_Shift_amount_EXP_EW[2])
);
NOR2X1TS U2787 ( .A(n1837), .B(n1836), .Y(FPMULT_FSM_adder_round_norm_load)
);
NOR2BX1TS U2788 ( .AN(FPMULT_P_Sgf[47]), .B(n1838), .Y(n2152) );
NOR2X1TS U2789 ( .A(n107), .B(FPMULT_FSM_adder_round_norm_load), .Y(n2153)
);
OAI21XLTS U2790 ( .A0(n2152), .A1(n2807), .B0(n2153), .Y(n830) );
OAI211XLTS U2791 ( .A0(n1841), .A1(n1840), .B0(n1839), .C0(n2453), .Y(n855)
);
INVX2TS U2792 ( .A(intadd_1063_SUM_2_), .Y(FPADDSUB_Shift_amount_EXP_EW[3])
);
NOR2X1TS U2793 ( .A(n969), .B(intadd_1062_n1), .Y(n2743) );
OR3X1TS U2794 ( .A(n969), .B(FPSENCOS_d_ff2_Y[28]), .C(intadd_1062_n1), .Y(
n2742) );
NOR2X1TS U2795 ( .A(n968), .B(intadd_1061_n1), .Y(n2746) );
OR3X1TS U2796 ( .A(n968), .B(FPSENCOS_d_ff2_X[28]), .C(intadd_1061_n1), .Y(
n2745) );
OAI21XLTS U2797 ( .A0(n2746), .A1(n2875), .B0(n2745), .Y(
FPSENCOS_sh_exp_x[5]) );
INVX2TS U2798 ( .A(n1842), .Y(intadd_1063_CI) );
OR2X1TS U2799 ( .A(FPSENCOS_d_ff_Xn[26]), .B(n966), .Y(
FPSENCOS_first_mux_X[26]) );
OR2X1TS U2800 ( .A(FPSENCOS_d_ff_Xn[13]), .B(n966), .Y(
FPSENCOS_first_mux_X[13]) );
OR2X1TS U2801 ( .A(FPSENCOS_d_ff_Xn[16]), .B(n966), .Y(
FPSENCOS_first_mux_X[16]) );
OR2X1TS U2802 ( .A(FPSENCOS_d_ff_Xn[20]), .B(n966), .Y(
FPSENCOS_first_mux_X[20]) );
CLKBUFX2TS U2803 ( .A(n2922), .Y(n2525) );
OR2X1TS U2804 ( .A(FPADDSUB_N60), .B(FPADDSUB_N59), .Y(n2480) );
AOI22X1TS U2805 ( .A0(n2490), .A1(n1847), .B0(n2479), .B1(n2525), .Y(n1844)
);
NAND2X1TS U2806 ( .A(FPADDSUB_DmP_mant_SFG_SWR[3]), .B(n2751), .Y(n1846) );
OAI21XLTS U2807 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[3]), .A1(n2751), .B0(n1846),
.Y(n1843) );
XOR2XLTS U2808 ( .A(n1844), .B(n1843), .Y(FPADDSUB_Raw_mant_SGF[3]) );
OR2X1TS U2809 ( .A(FPSENCOS_d_ff_Xn[19]), .B(n2554), .Y(
FPSENCOS_first_mux_X[19]) );
OR2X1TS U2810 ( .A(FPSENCOS_d_ff_Xn[25]), .B(n2551), .Y(
FPSENCOS_first_mux_X[25]) );
OR2X1TS U2811 ( .A(FPSENCOS_d_ff_Xn[14]), .B(n2550), .Y(
FPSENCOS_first_mux_X[14]) );
NAND2X1TS U2812 ( .A(FPSENCOS_cont_iter_out[2]), .B(n2666), .Y(n2665) );
CLKAND2X2TS U2813 ( .A(n2665), .B(n2749), .Y(n857) );
NOR2X1TS U2814 ( .A(n2749), .B(n2665), .Y(n1910) );
NOR2XLTS U2815 ( .A(n1910), .B(n857), .Y(FPSENCOS_ITER_CONT_N5) );
OAI21XLTS U2816 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n865), .B0(n2709), .Y(
n849) );
BUFX4TS U2817 ( .A(n2552), .Y(n2553) );
INVX2TS U2818 ( .A(n2552), .Y(n1845) );
OR2X1TS U2819 ( .A(FPSENCOS_d_ff_Xn[6]), .B(n1845), .Y(
FPSENCOS_first_mux_X[6]) );
OR2X1TS U2820 ( .A(FPSENCOS_d_ff_Xn[10]), .B(n1845), .Y(
FPSENCOS_first_mux_X[10]) );
OR2X1TS U2821 ( .A(FPSENCOS_d_ff_Xn[2]), .B(n1845), .Y(
FPSENCOS_first_mux_X[2]) );
OR2X1TS U2822 ( .A(FPSENCOS_d_ff_Xn[12]), .B(n1845), .Y(
FPSENCOS_first_mux_X[12]) );
OR2X1TS U2823 ( .A(FPSENCOS_d_ff_Xn[7]), .B(n1845), .Y(
FPSENCOS_first_mux_X[7]) );
OR2X1TS U2824 ( .A(FPSENCOS_d_ff_Xn[17]), .B(n1845), .Y(
FPSENCOS_first_mux_X[17]) );
OR2X1TS U2825 ( .A(FPSENCOS_d_ff_Xn[5]), .B(n1845), .Y(
FPSENCOS_first_mux_X[5]) );
OR2X1TS U2826 ( .A(FPSENCOS_d_ff_Xn[1]), .B(n1845), .Y(
FPSENCOS_first_mux_X[1]) );
OR2X1TS U2827 ( .A(FPSENCOS_d_ff_Xn[29]), .B(n1845), .Y(
FPSENCOS_first_mux_X[29]) );
OAI21XLTS U2828 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n2706), .B0(n1851),
.Y(n862) );
NOR2X1TS U2829 ( .A(FPADDSUB_DmP_mant_SFG_SWR[4]), .B(n2784), .Y(n1850) );
AOI22X1TS U2830 ( .A0(FPADDSUB_DMP_SFG[1]), .A1(n2777), .B0(n1847), .B1(
n1846), .Y(n1852) );
AOI22X1TS U2831 ( .A0(n2490), .A1(n1852), .B0(n1854), .B1(n2922), .Y(n1849)
);
CLKAND2X2TS U2832 ( .A(FPADDSUB_DmP_mant_SFG_SWR[4]), .B(n2784), .Y(n1853)
);
OAI21XLTS U2833 ( .A0(n1850), .A1(n1853), .B0(n1849), .Y(n1848) );
OAI31X1TS U2834 ( .A0(n1850), .A1(n1849), .A2(n1853), .B0(n1848), .Y(
FPADDSUB_Raw_mant_SGF[4]) );
OAI21X1TS U2835 ( .A0(n2704), .A1(n2800), .B0(n1851), .Y(n863) );
OR2X1TS U2836 ( .A(n863), .B(n2708), .Y(n850) );
OAI22X1TS U2837 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[4]), .A1(n2784), .B0(n1853),
.B1(n1852), .Y(n1866) );
AOI22X1TS U2838 ( .A0(n2490), .A1(n1866), .B0(n1868), .B1(n2922), .Y(n1856)
);
NAND2X1TS U2839 ( .A(FPADDSUB_DmP_mant_SFG_SWR[5]), .B(n2778), .Y(n1867) );
OAI21XLTS U2840 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[5]), .A1(n2778), .B0(n1867),
.Y(n1855) );
XOR2XLTS U2841 ( .A(n1856), .B(n1855), .Y(FPADDSUB_Raw_mant_SGF[5]) );
AOI22X1TS U2842 ( .A0(n1740), .A1(FPADDSUB_Data_array_SWR[30]), .B0(n1743),
.B1(FPADDSUB_Data_array_SWR[34]), .Y(n1858) );
AOI22X1TS U2843 ( .A0(n1888), .A1(FPADDSUB_Data_array_SWR[26]), .B0(n1742),
.B1(FPADDSUB_Data_array_SWR[38]), .Y(n1857) );
OAI211X1TS U2844 ( .A0(n1859), .A1(n2811), .B0(n1858), .C0(n1857), .Y(n1861)
);
AOI21X1TS U2845 ( .A0(n1894), .A1(n1861), .B0(n1746), .Y(n1860) );
OAI21XLTS U2846 ( .A0(n960), .A1(n1738), .B0(n1860), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[25]) );
AOI21X1TS U2847 ( .A0(n1898), .A1(n1861), .B0(n1753), .Y(n1862) );
OAI21XLTS U2848 ( .A0(n1749), .A1(n960), .B0(n1862), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[0]) );
AOI21X1TS U2849 ( .A0(n1898), .A1(n1863), .B0(n1753), .Y(n1864) );
OAI21XLTS U2850 ( .A0(n1749), .A1(n1865), .B0(n1864), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[1]) );
NOR2X1TS U2851 ( .A(FPADDSUB_DmP_mant_SFG_SWR[6]), .B(n2786), .Y(n1871) );
AOI22X1TS U2852 ( .A0(FPADDSUB_DMP_SFG[3]), .A1(n2752), .B0(n1867), .B1(
n1866), .Y(n1872) );
AOI222X4TS U2853 ( .A0(n1868), .A1(n2778), .B0(n1868), .B1(n2752), .C0(n2778), .C1(n2752), .Y(n1874) );
AOI22X1TS U2854 ( .A0(n2490), .A1(n1872), .B0(n1874), .B1(n2922), .Y(n1870)
);
CLKAND2X2TS U2855 ( .A(FPADDSUB_DmP_mant_SFG_SWR[6]), .B(n2786), .Y(n1873)
);
OAI21XLTS U2856 ( .A0(n1871), .A1(n1873), .B0(n1870), .Y(n1869) );
OAI31X1TS U2857 ( .A0(n1871), .A1(n1870), .A2(n1873), .B0(n1869), .Y(
FPADDSUB_Raw_mant_SGF[6]) );
OAI22X1TS U2858 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[6]), .A1(n2786), .B0(n1873),
.B1(n1872), .Y(n1903) );
AOI22X1TS U2859 ( .A0(n2490), .A1(n1903), .B0(n1905), .B1(n2922), .Y(n1876)
);
NAND2X1TS U2860 ( .A(FPADDSUB_DmP_mant_SFG_SWR[7]), .B(n2753), .Y(n1904) );
OAI21XLTS U2861 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[7]), .A1(n2753), .B0(n1904),
.Y(n1875) );
XOR2XLTS U2862 ( .A(n1876), .B(n1875), .Y(FPADDSUB_Raw_mant_SGF[7]) );
OR2X1TS U2863 ( .A(n2958), .B(FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(
FPADDSUB_formatted_number_W[23]) );
OR2X1TS U2864 ( .A(n2958), .B(FPADDSUB_exp_rslt_NRM2_EW1[2]), .Y(
FPADDSUB_formatted_number_W[25]) );
OR2X1TS U2865 ( .A(n2958), .B(FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(
FPADDSUB_formatted_number_W[24]) );
OR2X1TS U2866 ( .A(n2958), .B(FPADDSUB_exp_rslt_NRM2_EW1[3]), .Y(
FPADDSUB_formatted_number_W[26]) );
OR2X1TS U2867 ( .A(n2958), .B(FPADDSUB_exp_rslt_NRM2_EW1[4]), .Y(
FPADDSUB_formatted_number_W[27]) );
OR2X1TS U2868 ( .A(n2958), .B(FPADDSUB_exp_rslt_NRM2_EW1[6]), .Y(
FPADDSUB_formatted_number_W[29]) );
AOI22X1TS U2869 ( .A0(n1742), .A1(FPADDSUB_Data_array_SWR[45]), .B0(n1743),
.B1(FPADDSUB_Data_array_SWR[41]), .Y(n1878) );
AOI22X1TS U2870 ( .A0(n1740), .A1(FPADDSUB_Data_array_SWR[37]), .B0(n1888),
.B1(FPADDSUB_Data_array_SWR[33]), .Y(n1877) );
AOI21X1TS U2871 ( .A0(n1894), .A1(n1897), .B0(n1746), .Y(n1880) );
OAI21X1TS U2872 ( .A0(n1900), .A1(n1738), .B0(n1880), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[18]) );
AOI22X1TS U2873 ( .A0(n1742), .A1(FPADDSUB_Data_array_SWR[42]), .B0(n1743),
.B1(FPADDSUB_Data_array_SWR[38]), .Y(n1882) );
AOI22X1TS U2874 ( .A0(n1740), .A1(FPADDSUB_Data_array_SWR[34]), .B0(n1888),
.B1(FPADDSUB_Data_array_SWR[30]), .Y(n1881) );
OAI211X1TS U2875 ( .A0(n1883), .A1(n2811), .B0(n1882), .C0(n1881), .Y(n1885)
);
AOI21X1TS U2876 ( .A0(n1894), .A1(n1885), .B0(n1746), .Y(n1884) );
OAI21X1TS U2877 ( .A0(n1887), .A1(n1738), .B0(n1884), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[21]) );
AOI21X1TS U2878 ( .A0(n1898), .A1(n1885), .B0(n1753), .Y(n1886) );
OAI21X1TS U2879 ( .A0(n1887), .A1(n1749), .B0(n1886), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[4]) );
AOI22X1TS U2880 ( .A0(FPADDSUB_Data_array_SWR[44]), .A1(n1742), .B0(
FPADDSUB_Data_array_SWR[40]), .B1(n1743), .Y(n1890) );
AOI22X1TS U2881 ( .A0(n1740), .A1(FPADDSUB_Data_array_SWR[36]), .B0(
FPADDSUB_Data_array_SWR[32]), .B1(n1888), .Y(n1889) );
OAI211X1TS U2882 ( .A0(n2811), .A1(n1891), .B0(n1890), .C0(n1889), .Y(n1893)
);
AOI21X1TS U2883 ( .A0(n1898), .A1(n1893), .B0(n1753), .Y(n1892) );
OAI21X1TS U2884 ( .A0(n1896), .A1(n1749), .B0(n1892), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[6]) );
AOI21X1TS U2885 ( .A0(n1894), .A1(n1893), .B0(n1746), .Y(n1895) );
OAI21X1TS U2886 ( .A0(n1896), .A1(n1738), .B0(n1895), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[19]) );
AOI21X1TS U2887 ( .A0(n1898), .A1(n1897), .B0(n1753), .Y(n1899) );
OAI21X1TS U2888 ( .A0(n1900), .A1(n1749), .B0(n1899), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[7]) );
NOR2BX1TS U2889 ( .AN(FPADDSUB_LZD_output_NRM2_EW[3]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n1901) );
XOR2X1TS U2890 ( .A(n962), .B(n1901), .Y(DP_OP_26J314_126_1325_n15) );
NOR2BX1TS U2891 ( .AN(FPADDSUB_LZD_output_NRM2_EW[4]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n1902) );
XOR2X1TS U2892 ( .A(n962), .B(n1902), .Y(DP_OP_26J314_126_1325_n14) );
NOR2X1TS U2893 ( .A(FPADDSUB_DmP_mant_SFG_SWR[8]), .B(n2787), .Y(n1908) );
AOI22X1TS U2894 ( .A0(FPADDSUB_DMP_SFG[5]), .A1(n2779), .B0(n1904), .B1(
n1903), .Y(n1920) );
AOI222X4TS U2895 ( .A0(n1905), .A1(n2753), .B0(n1905), .B1(n2779), .C0(n2753), .C1(n2779), .Y(n1922) );
AOI22X1TS U2896 ( .A0(n2490), .A1(n1920), .B0(n1922), .B1(n2922), .Y(n1907)
);
CLKAND2X2TS U2897 ( .A(FPADDSUB_DmP_mant_SFG_SWR[8]), .B(n2787), .Y(n1921)
);
OAI21XLTS U2898 ( .A0(n1908), .A1(n1921), .B0(n1907), .Y(n1906) );
OAI31X1TS U2899 ( .A0(n1908), .A1(n1907), .A2(n1921), .B0(n1906), .Y(
FPADDSUB_Raw_mant_SGF[8]) );
OAI21XLTS U2900 ( .A0(n1910), .A1(n927), .B0(n1909), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]) );
AND4X1TS U2901 ( .A(FPMULT_Exp_module_Data_S[3]), .B(
FPMULT_Exp_module_Data_S[2]), .C(FPMULT_Exp_module_Data_S[0]), .D(
FPMULT_Exp_module_Data_S[1]), .Y(n1911) );
AND4X1TS U2902 ( .A(FPMULT_Exp_module_Data_S[6]), .B(
FPMULT_Exp_module_Data_S[5]), .C(FPMULT_Exp_module_Data_S[4]), .D(
n1911), .Y(n1912) );
MX2X1TS U2903 ( .A(FPMULT_Op_MX[23]), .B(FPMULT_exp_oper_result[0]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[0]) );
MX2X1TS U2904 ( .A(FPMULT_Op_MX[24]), .B(FPMULT_exp_oper_result[1]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[1]) );
OR2X2TS U2905 ( .A(FPMULT_FSM_selector_B[1]), .B(n2807), .Y(n2146) );
OAI2BB1X1TS U2906 ( .A0N(FPMULT_Op_MY[24]), .A1N(n2801), .B0(n2146), .Y(
n1913) );
XOR2X1TS U2907 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n1913), .Y(
DP_OP_234J314_129_4955_n21) );
MX2X1TS U2908 ( .A(FPMULT_Op_MX[25]), .B(FPMULT_exp_oper_result[2]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[2]) );
OAI2BB1X1TS U2909 ( .A0N(FPMULT_Op_MY[25]), .A1N(n2801), .B0(n2146), .Y(
n1914) );
XOR2X1TS U2910 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n1914), .Y(
DP_OP_234J314_129_4955_n20) );
MX2X1TS U2911 ( .A(FPMULT_Op_MX[26]), .B(FPMULT_exp_oper_result[3]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[3]) );
OAI2BB1X1TS U2912 ( .A0N(FPMULT_Op_MY[26]), .A1N(n2801), .B0(n2146), .Y(
n1915) );
XOR2X1TS U2913 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n1915), .Y(
DP_OP_234J314_129_4955_n19) );
MX2X1TS U2914 ( .A(FPMULT_Op_MX[27]), .B(FPMULT_exp_oper_result[4]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[4]) );
OAI2BB1X1TS U2915 ( .A0N(FPMULT_Op_MY[27]), .A1N(n2801), .B0(n2146), .Y(
n1916) );
XOR2X1TS U2916 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n1916), .Y(
DP_OP_234J314_129_4955_n18) );
MX2X1TS U2917 ( .A(FPMULT_Op_MX[28]), .B(FPMULT_exp_oper_result[5]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[5]) );
OAI2BB1X1TS U2918 ( .A0N(FPMULT_Op_MY[28]), .A1N(n2801), .B0(n2146), .Y(
n1917) );
XOR2X1TS U2919 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n1917), .Y(
DP_OP_234J314_129_4955_n17) );
MX2X1TS U2920 ( .A(FPMULT_Op_MX[29]), .B(FPMULT_exp_oper_result[6]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[6]) );
OAI2BB1X1TS U2921 ( .A0N(FPMULT_Op_MY[29]), .A1N(n2801), .B0(n2146), .Y(
n1918) );
XOR2X1TS U2922 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n1918), .Y(
DP_OP_234J314_129_4955_n16) );
MX2X1TS U2923 ( .A(FPMULT_Op_MX[30]), .B(FPMULT_exp_oper_result[7]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[7]) );
NOR3BX1TS U2924 ( .AN(FPMULT_Op_MY[30]), .B(FPMULT_FSM_selector_B[0]), .C(
FPMULT_FSM_selector_B[1]), .Y(n1919) );
XOR2X1TS U2925 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n1919), .Y(
DP_OP_234J314_129_4955_n15) );
CLKAND2X2TS U2926 ( .A(FPMULT_FSM_selector_A), .B(FPMULT_exp_oper_result[8]),
.Y(FPMULT_S_Oper_A_exp[8]) );
NOR2X1TS U2927 ( .A(FPADDSUB_DmP_mant_SFG_SWR[10]), .B(n2788), .Y(n1925) );
NAND2X1TS U2928 ( .A(FPADDSUB_DmP_mant_SFG_SWR[9]), .B(n2754), .Y(n2485) );
OAI22X1TS U2929 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[8]), .A1(n2787), .B0(n1921),
.B1(n1920), .Y(n2484) );
AOI22X1TS U2930 ( .A0(FPADDSUB_DMP_SFG[7]), .A1(n2780), .B0(n2485), .B1(
n2484), .Y(n1935) );
AOI222X4TS U2931 ( .A0(n2483), .A1(n2754), .B0(n2483), .B1(n2780), .C0(n2754), .C1(n2780), .Y(n1937) );
AOI22X1TS U2932 ( .A0(n2490), .A1(n1935), .B0(n1937), .B1(n2922), .Y(n1924)
);
CLKAND2X2TS U2933 ( .A(FPADDSUB_DmP_mant_SFG_SWR[10]), .B(n2788), .Y(n1936)
);
OAI21XLTS U2934 ( .A0(n1925), .A1(n1936), .B0(n1924), .Y(n1923) );
OAI31X1TS U2935 ( .A0(n1925), .A1(n1924), .A2(n1936), .B0(n1923), .Y(
FPADDSUB_Raw_mant_SGF[10]) );
AOI221X4TS U2936 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[0]), .A1(n1959), .B0(
FPADDSUB_Raw_mant_NRM_SWR[25]), .B1(n1943), .C0(n1963), .Y(n2547) );
NAND2X1TS U2937 ( .A(n1945), .B(n1933), .Y(n1926) );
OAI21XLTS U2938 ( .A0(n2547), .A1(n2546), .B0(n2143), .Y(
FPADDSUB_Data_array_SWR[25]) );
INVX2TS U2939 ( .A(n2451), .Y(n2718) );
NAND3BX1TS U2940 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .C(n1927), .Y(n2571) );
NAND3BX1TS U2941 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(n1928),
.C(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .Y(n2570) );
NAND2X1TS U2942 ( .A(n2571), .B(n2570), .Y(n1929) );
AOI22X1TS U2943 ( .A0(operation[1]), .A1(n1929), .B0(begin_operation), .B1(
n2703), .Y(n2715) );
INVX2TS U2944 ( .A(n2716), .Y(n1930) );
AOI211XLTS U2945 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
n2718), .B0(n2715), .C0(n1930), .Y(FPADDSUB_enable_Pipeline_input) );
AOI222X1TS U2946 ( .A0(n2659), .A1(Data_2[30]), .B0(n2289), .B1(
FPSENCOS_d_ff3_sh_x_out[30]), .C0(FPSENCOS_d_ff3_sh_y_out[30]), .C1(
n2587), .Y(n1931) );
INVX2TS U2947 ( .A(n1931), .Y(add_subt_data2[30]) );
INVX2TS U2948 ( .A(n1933), .Y(n1944) );
AOI22X1TS U2949 ( .A0(n1959), .A1(FPADDSUB_Raw_mant_NRM_SWR[24]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[1]), .B1(n1604), .Y(n1993) );
INVX2TS U2950 ( .A(n1979), .Y(n1991) );
AOI22X1TS U2951 ( .A0(n1959), .A1(FPADDSUB_Raw_mant_NRM_SWR[25]), .B0(n1987),
.B1(n1991), .Y(n1934) );
OAI211XLTS U2952 ( .A0(n1989), .A1(n1932), .B0(n1993), .C0(n1934), .Y(
FPADDSUB_Data_array_SWR[0]) );
NOR2X1TS U2953 ( .A(FPADDSUB_DmP_mant_SFG_SWR[12]), .B(n2790), .Y(n1940) );
NAND2X1TS U2954 ( .A(FPADDSUB_DmP_mant_SFG_SWR[11]), .B(n2755), .Y(n2491) );
OAI22X1TS U2955 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[10]), .A1(n2788), .B0(n1936),
.B1(n1935), .Y(n2489) );
AOI22X1TS U2956 ( .A0(FPADDSUB_DMP_SFG[9]), .A1(n2781), .B0(n2491), .B1(
n2489), .Y(n2024) );
AOI222X4TS U2957 ( .A0(n2488), .A1(n2755), .B0(n2488), .B1(n2781), .C0(n2755), .C1(n2781), .Y(n2026) );
AOI22X1TS U2958 ( .A0(n995), .A1(n2024), .B0(n2026), .B1(n2922), .Y(n1939)
);
CLKAND2X2TS U2959 ( .A(FPADDSUB_DmP_mant_SFG_SWR[12]), .B(n2790), .Y(n2025)
);
OAI21XLTS U2960 ( .A0(n1940), .A1(n2025), .B0(n1939), .Y(n1938) );
OAI31X1TS U2961 ( .A0(n1940), .A1(n1939), .A2(n2025), .B0(n1938), .Y(
FPADDSUB_Raw_mant_SGF[12]) );
INVX2TS U2962 ( .A(n2546), .Y(n1961) );
AOI22X1TS U2963 ( .A0(n1604), .A1(FPADDSUB_Raw_mant_NRM_SWR[22]), .B0(
FPADDSUB_DmP_mant_SHT1_SW[20]), .B1(n1963), .Y(n1942) );
AOI222X4TS U2964 ( .A0(n1963), .A1(FPADDSUB_DmP_mant_SHT1_SW[22]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[24]), .B1(n1604), .C0(
FPADDSUB_Raw_mant_NRM_SWR[1]), .C1(n2921), .Y(n2543) );
AOI222X4TS U2965 ( .A0(n1963), .A1(FPADDSUB_DmP_mant_SHT1_SW[21]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[23]), .B1(n1604), .C0(
FPADDSUB_Raw_mant_NRM_SWR[2]), .C1(n2921), .Y(n2545) );
NAND2X1TS U2966 ( .A(n1945), .B(n1944), .Y(n1946) );
BUFX4TS U2967 ( .A(n1946), .Y(n2544) );
OAI22X1TS U2968 ( .A0(n2543), .A1(n1932), .B0(n2545), .B1(n2544), .Y(n1947)
);
AOI21X1TS U2969 ( .A0(n1961), .A1(n2020), .B0(n1947), .Y(n1948) );
OAI21XLTS U2970 ( .A0(n2547), .A1(n1941), .B0(n1948), .Y(
FPADDSUB_Data_array_SWR[22]) );
AOI222X4TS U2971 ( .A0(n2793), .A1(FPADDSUB_DmP_mant_SHT1_SW[9]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[11]), .B1(n1604), .C0(
FPADDSUB_Raw_mant_NRM_SWR[14]), .C1(n2921), .Y(n2001) );
AOI22X1TS U2972 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[15]), .A1(n1959), .B0(
FPADDSUB_DmP_mant_SHT1_SW[8]), .B1(n1963), .Y(n1949) );
AOI222X4TS U2973 ( .A0(n2793), .A1(FPADDSUB_DmP_mant_SHT1_SW[11]), .B0(n2921), .B1(FPADDSUB_Raw_mant_NRM_SWR[12]), .C0(FPADDSUB_Raw_mant_NRM_SWR[13]), .C1(
n1604), .Y(n2006) );
AOI222X4TS U2974 ( .A0(n1963), .A1(FPADDSUB_DmP_mant_SHT1_SW[10]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[12]), .B1(n1604), .C0(
FPADDSUB_Raw_mant_NRM_SWR[13]), .C1(n2921), .Y(n2011) );
OAI22X1TS U2975 ( .A0(n2006), .A1(n1941), .B0(n2011), .B1(n1932), .Y(n1950)
);
AOI21X1TS U2976 ( .A0(n1961), .A1(n2003), .B0(n1950), .Y(n1951) );
OAI21XLTS U2977 ( .A0(n2001), .A1(n2544), .B0(n1951), .Y(
FPADDSUB_Data_array_SWR[10]) );
AOI222X4TS U2978 ( .A0(n1963), .A1(FPADDSUB_DmP_mant_SHT1_SW[5]), .B0(n2921),
.B1(FPADDSUB_Raw_mant_NRM_SWR[18]), .C0(FPADDSUB_Raw_mant_NRM_SWR[7]),
.C1(n1604), .Y(n1995) );
AOI22X1TS U2979 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[19]), .A1(n1959), .B0(
FPADDSUB_DmP_mant_SHT1_SW[4]), .B1(n1963), .Y(n1952) );
AOI222X4TS U2980 ( .A0(n1963), .A1(FPADDSUB_DmP_mant_SHT1_SW[7]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[9]), .B1(n1604), .C0(
FPADDSUB_Raw_mant_NRM_SWR[16]), .C1(n2921), .Y(n2000) );
AOI222X4TS U2981 ( .A0(n2793), .A1(FPADDSUB_DmP_mant_SHT1_SW[6]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[8]), .B1(n1604), .C0(
FPADDSUB_Raw_mant_NRM_SWR[17]), .C1(n2921), .Y(n2005) );
OAI22X1TS U2982 ( .A0(n2000), .A1(n1941), .B0(n2005), .B1(n1932), .Y(n1953)
);
AOI21X1TS U2983 ( .A0(n1961), .A1(n1997), .B0(n1953), .Y(n1954) );
OAI21XLTS U2984 ( .A0(n1995), .A1(n2544), .B0(n1954), .Y(
FPADDSUB_Data_array_SWR[6]) );
AOI222X4TS U2985 ( .A0(n2793), .A1(FPADDSUB_DmP_mant_SHT1_SW[17]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[19]), .B1(n1604), .C0(
FPADDSUB_Raw_mant_NRM_SWR[6]), .C1(n2921), .Y(n2013) );
AOI22X1TS U2986 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[7]), .A1(n1959), .B0(
FPADDSUB_DmP_mant_SHT1_SW[16]), .B1(n1963), .Y(n1955) );
AOI222X4TS U2987 ( .A0(n2793), .A1(FPADDSUB_DmP_mant_SHT1_SW[19]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[21]), .B1(n1604), .C0(
FPADDSUB_Raw_mant_NRM_SWR[4]), .C1(n2921), .Y(n2018) );
AOI222X4TS U2988 ( .A0(n2793), .A1(FPADDSUB_DmP_mant_SHT1_SW[18]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[20]), .B1(n1604), .C0(
FPADDSUB_Raw_mant_NRM_SWR[5]), .C1(n2921), .Y(n2023) );
OAI22X1TS U2989 ( .A0(n2018), .A1(n1941), .B0(n2023), .B1(n1932), .Y(n1956)
);
AOI21X1TS U2990 ( .A0(n1961), .A1(n2015), .B0(n1956), .Y(n1957) );
OAI21XLTS U2991 ( .A0(n2013), .A1(n2544), .B0(n1957), .Y(
FPADDSUB_Data_array_SWR[18]) );
AOI222X4TS U2992 ( .A0(n2793), .A1(FPADDSUB_DmP_mant_SHT1_SW[13]), .B0(n1959), .B1(FPADDSUB_Raw_mant_NRM_SWR[10]), .C0(FPADDSUB_Raw_mant_NRM_SWR[15]), .C1(
n1604), .Y(n2007) );
AOI22X1TS U2993 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[11]), .A1(n1959), .B0(
FPADDSUB_DmP_mant_SHT1_SW[12]), .B1(n1963), .Y(n1958) );
AOI222X4TS U2994 ( .A0(n2793), .A1(FPADDSUB_DmP_mant_SHT1_SW[15]), .B0(n1959), .B1(FPADDSUB_Raw_mant_NRM_SWR[8]), .C0(FPADDSUB_Raw_mant_NRM_SWR[17]), .C1(
n1604), .Y(n2012) );
AOI222X4TS U2995 ( .A0(n1963), .A1(FPADDSUB_DmP_mant_SHT1_SW[14]), .B0(n1959), .B1(FPADDSUB_Raw_mant_NRM_SWR[9]), .C0(FPADDSUB_Raw_mant_NRM_SWR[16]), .C1(
n1604), .Y(n2017) );
OAI22X1TS U2996 ( .A0(n2012), .A1(n1941), .B0(n2017), .B1(n1932), .Y(n1960)
);
AOI21X1TS U2997 ( .A0(n1961), .A1(n2009), .B0(n1960), .Y(n1962) );
OAI21XLTS U2998 ( .A0(n2007), .A1(n2544), .B0(n1962), .Y(
FPADDSUB_Data_array_SWR[14]) );
INVX2TS U2999 ( .A(n2544), .Y(n1975) );
AOI222X4TS U3000 ( .A0(n1963), .A1(FPADDSUB_DmP_mant_SHT1_SW[3]), .B0(n2921),
.B1(FPADDSUB_Raw_mant_NRM_SWR[20]), .C0(FPADDSUB_Raw_mant_NRM_SWR[5]),
.C1(n1604), .Y(n1994) );
AOI222X4TS U3001 ( .A0(n1963), .A1(FPADDSUB_DmP_mant_SHT1_SW[2]), .B0(n2921),
.B1(FPADDSUB_Raw_mant_NRM_SWR[21]), .C0(FPADDSUB_Raw_mant_NRM_SWR[4]),
.C1(n1604), .Y(n1999) );
OAI22X1TS U3002 ( .A0(n1994), .A1(n1941), .B0(n1999), .B1(n1932), .Y(n1964)
);
AOI21X1TS U3003 ( .A0(n1975), .A1(n1991), .B0(n1964), .Y(n1965) );
OAI21XLTS U3004 ( .A0(n1989), .A1(n2546), .B0(n1965), .Y(
FPADDSUB_Data_array_SWR[2]) );
OAI22X1TS U3005 ( .A0(n2017), .A1(n1941), .B0(n2007), .B1(n1932), .Y(n1966)
);
AOI21X1TS U3006 ( .A0(n1975), .A1(n2009), .B0(n1966), .Y(n1967) );
OAI21XLTS U3007 ( .A0(n2006), .A1(n2546), .B0(n1967), .Y(
FPADDSUB_Data_array_SWR[13]) );
OAI22X1TS U3008 ( .A0(n2005), .A1(n1941), .B0(n1995), .B1(n1932), .Y(n1968)
);
AOI21X1TS U3009 ( .A0(n1975), .A1(n1997), .B0(n1968), .Y(n1969) );
OAI21XLTS U3010 ( .A0(n1994), .A1(n2546), .B0(n1969), .Y(
FPADDSUB_Data_array_SWR[5]) );
OAI22X1TS U3011 ( .A0(n2543), .A1(n1941), .B0(n2545), .B1(n1932), .Y(n1970)
);
AOI21X1TS U3012 ( .A0(n1975), .A1(n2020), .B0(n1970), .Y(n1971) );
OAI21XLTS U3013 ( .A0(n2018), .A1(n2546), .B0(n1971), .Y(
FPADDSUB_Data_array_SWR[21]) );
OAI22X1TS U3014 ( .A0(n2011), .A1(n1941), .B0(n2001), .B1(n1932), .Y(n1972)
);
AOI21X1TS U3015 ( .A0(n1975), .A1(n2003), .B0(n1972), .Y(n1973) );
OAI21XLTS U3016 ( .A0(n2000), .A1(n2546), .B0(n1973), .Y(
FPADDSUB_Data_array_SWR[9]) );
OAI22X1TS U3017 ( .A0(n2023), .A1(n1941), .B0(n2013), .B1(n1932), .Y(n1974)
);
AOI21X1TS U3018 ( .A0(n1975), .A1(n2015), .B0(n1974), .Y(n1976) );
OAI21XLTS U3019 ( .A0(n2012), .A1(n2546), .B0(n1976), .Y(
FPADDSUB_Data_array_SWR[17]) );
OAI22X1TS U3020 ( .A0(n1994), .A1(n1932), .B0(n1999), .B1(n2544), .Y(n1977)
);
AOI21X1TS U3021 ( .A0(n1987), .A1(n1997), .B0(n1977), .Y(n1978) );
OAI22X1TS U3022 ( .A0(n2006), .A1(n1932), .B0(n2011), .B1(n2544), .Y(n1980)
);
AOI21X1TS U3023 ( .A0(n1987), .A1(n2009), .B0(n1980), .Y(n1981) );
OAI21XLTS U3024 ( .A0(n2001), .A1(n2546), .B0(n1981), .Y(
FPADDSUB_Data_array_SWR[11]) );
OAI22X1TS U3025 ( .A0(n2000), .A1(n1932), .B0(n2005), .B1(n2544), .Y(n1982)
);
AOI21X1TS U3026 ( .A0(n1987), .A1(n2003), .B0(n1982), .Y(n1983) );
OAI21XLTS U3027 ( .A0(n1995), .A1(n2546), .B0(n1983), .Y(
FPADDSUB_Data_array_SWR[7]) );
OAI22X1TS U3028 ( .A0(n2012), .A1(n1932), .B0(n2017), .B1(n2544), .Y(n1984)
);
AOI21X1TS U3029 ( .A0(n1987), .A1(n2015), .B0(n1984), .Y(n1985) );
OAI21XLTS U3030 ( .A0(n2007), .A1(n2546), .B0(n1985), .Y(
FPADDSUB_Data_array_SWR[15]) );
OAI22X1TS U3031 ( .A0(n2018), .A1(n1932), .B0(n2023), .B1(n2544), .Y(n1986)
);
AOI21X1TS U3032 ( .A0(n1987), .A1(n2020), .B0(n1986), .Y(n1988) );
OAI21XLTS U3033 ( .A0(n2013), .A1(n2546), .B0(n1988), .Y(
FPADDSUB_Data_array_SWR[19]) );
OAI22X1TS U3034 ( .A0(n1999), .A1(n1941), .B0(n1989), .B1(n2544), .Y(n1990)
);
AOI21X1TS U3035 ( .A0(n2021), .A1(n1991), .B0(n1990), .Y(n1992) );
OAI21XLTS U3036 ( .A0(n1993), .A1(n2546), .B0(n1992), .Y(
FPADDSUB_Data_array_SWR[1]) );
OAI22X1TS U3037 ( .A0(n1995), .A1(n1941), .B0(n1994), .B1(n2544), .Y(n1996)
);
AOI21X1TS U3038 ( .A0(n2021), .A1(n1997), .B0(n1996), .Y(n1998) );
OAI21XLTS U3039 ( .A0(n1999), .A1(n2546), .B0(n1998), .Y(
FPADDSUB_Data_array_SWR[4]) );
OAI22X1TS U3040 ( .A0(n2001), .A1(n1941), .B0(n2000), .B1(n2544), .Y(n2002)
);
AOI21X1TS U3041 ( .A0(n2021), .A1(n2003), .B0(n2002), .Y(n2004) );
OAI21XLTS U3042 ( .A0(n2005), .A1(n2546), .B0(n2004), .Y(
FPADDSUB_Data_array_SWR[8]) );
OAI22X1TS U3043 ( .A0(n2007), .A1(n1941), .B0(n2006), .B1(n2544), .Y(n2008)
);
AOI21X1TS U3044 ( .A0(n2021), .A1(n2009), .B0(n2008), .Y(n2010) );
OAI22X1TS U3045 ( .A0(n2013), .A1(n1941), .B0(n2012), .B1(n2544), .Y(n2014)
);
AOI21X1TS U3046 ( .A0(n2021), .A1(n2015), .B0(n2014), .Y(n2016) );
OAI21XLTS U3047 ( .A0(n2017), .A1(n2546), .B0(n2016), .Y(
FPADDSUB_Data_array_SWR[16]) );
OAI22X1TS U3048 ( .A0(n2545), .A1(n1941), .B0(n2018), .B1(n2544), .Y(n2019)
);
AOI21X1TS U3049 ( .A0(n2021), .A1(n2020), .B0(n2019), .Y(n2022) );
INVX2TS U3050 ( .A(FPMULT_Sgf_normalized_result[23]), .Y(n2154) );
NAND2X1TS U3051 ( .A(FPMULT_Sgf_normalized_result[6]), .B(n2180), .Y(n2179)
);
NAND2X1TS U3052 ( .A(FPMULT_Sgf_normalized_result[8]), .B(n2177), .Y(n2176)
);
NAND2X1TS U3053 ( .A(FPMULT_Sgf_normalized_result[10]), .B(n2174), .Y(n2173)
);
NAND2X1TS U3054 ( .A(FPMULT_Sgf_normalized_result[12]), .B(n2171), .Y(n2170)
);
NAND2X1TS U3055 ( .A(FPMULT_Sgf_normalized_result[14]), .B(n2168), .Y(n2167)
);
NAND2X1TS U3056 ( .A(FPMULT_Sgf_normalized_result[16]), .B(n2165), .Y(n2164)
);
NAND2X1TS U3057 ( .A(FPMULT_Sgf_normalized_result[18]), .B(n2162), .Y(n2161)
);
NAND2X1TS U3058 ( .A(FPMULT_Sgf_normalized_result[20]), .B(n2159), .Y(n2158)
);
NAND2X1TS U3059 ( .A(FPMULT_Sgf_normalized_result[22]), .B(n2156), .Y(n2155)
);
NOR2X1TS U3060 ( .A(n2154), .B(n2155), .Y(FPMULT_Adder_M_result_A_adder[24])
);
NOR2X1TS U3061 ( .A(FPADDSUB_DmP_mant_SFG_SWR[14]), .B(n2796), .Y(n2029) );
NAND2X1TS U3062 ( .A(FPADDSUB_DmP_mant_SFG_SWR[13]), .B(n2756), .Y(n2496) );
OAI22X1TS U3063 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[12]), .A1(n2790), .B0(n2025),
.B1(n2024), .Y(n2495) );
AOI22X1TS U3064 ( .A0(FPADDSUB_DMP_SFG[11]), .A1(n2782), .B0(n2496), .B1(
n2495), .Y(n2039) );
AOI222X4TS U3065 ( .A0(n2494), .A1(n2756), .B0(n2494), .B1(n2782), .C0(n2756), .C1(n2782), .Y(n2041) );
AOI22X1TS U3066 ( .A0(n995), .A1(n2039), .B0(n2041), .B1(n2922), .Y(n2028)
);
CLKAND2X2TS U3067 ( .A(FPADDSUB_DmP_mant_SFG_SWR[14]), .B(n2796), .Y(n2040)
);
OAI31X1TS U3068 ( .A0(n2029), .A1(n2028), .A2(n2040), .B0(n2027), .Y(
FPADDSUB_Raw_mant_SGF[14]) );
ADDHXLTS U3069 ( .A(n2031), .B(n2030), .CO(n1691), .S(n2036) );
CMPR32X2TS U3070 ( .A(n2034), .B(n2033), .C(n2032), .CO(n1685), .S(n2035) );
NOR4X1TS U3071 ( .A(n2038), .B(n2037), .C(n2036), .D(n2035), .Y(n2887) );
NOR2X1TS U3072 ( .A(FPADDSUB_DmP_mant_SFG_SWR[16]), .B(n2799), .Y(n2044) );
NAND2X1TS U3073 ( .A(FPADDSUB_DmP_mant_SFG_SWR[15]), .B(n2757), .Y(n2501) );
OAI22X1TS U3074 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[14]), .A1(n2796), .B0(n2040),
.B1(n2039), .Y(n2500) );
AOI22X1TS U3075 ( .A0(FPADDSUB_DMP_SFG[13]), .A1(n2785), .B0(n2501), .B1(
n2500), .Y(n2045) );
AOI222X4TS U3076 ( .A0(n2499), .A1(n2757), .B0(n2499), .B1(n2785), .C0(n2757), .C1(n2785), .Y(n2047) );
AOI22X1TS U3077 ( .A0(n995), .A1(n2045), .B0(n2047), .B1(n2922), .Y(n2043)
);
CLKAND2X2TS U3078 ( .A(FPADDSUB_DmP_mant_SFG_SWR[16]), .B(n2799), .Y(n2046)
);
OAI21XLTS U3079 ( .A0(n2044), .A1(n2046), .B0(n2043), .Y(n2042) );
OAI31X1TS U3080 ( .A0(n2044), .A1(n2043), .A2(n2046), .B0(n2042), .Y(
FPADDSUB_Raw_mant_SGF[16]) );
NOR2X1TS U3081 ( .A(FPADDSUB_DmP_mant_SFG_SWR[18]), .B(n2809), .Y(n2050) );
NAND2X1TS U3082 ( .A(FPADDSUB_DmP_mant_SFG_SWR[17]), .B(n2758), .Y(n2506) );
OAI22X1TS U3083 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[16]), .A1(n2799), .B0(n2046),
.B1(n2045), .Y(n2505) );
AOI22X1TS U3084 ( .A0(FPADDSUB_DMP_SFG[15]), .A1(n2789), .B0(n2506), .B1(
n2505), .Y(n2051) );
AOI222X4TS U3085 ( .A0(n2504), .A1(n2758), .B0(n2504), .B1(n2789), .C0(n2758), .C1(n2789), .Y(n2053) );
AOI22X1TS U3086 ( .A0(n995), .A1(n2051), .B0(n2053), .B1(n2922), .Y(n2049)
);
CLKAND2X2TS U3087 ( .A(FPADDSUB_DmP_mant_SFG_SWR[18]), .B(n2809), .Y(n2052)
);
OAI21XLTS U3088 ( .A0(n2050), .A1(n2052), .B0(n2049), .Y(n2048) );
OAI31X1TS U3089 ( .A0(n2050), .A1(n2049), .A2(n2052), .B0(n2048), .Y(
FPADDSUB_Raw_mant_SGF[18]) );
NOR2X1TS U3090 ( .A(FPADDSUB_DmP_mant_SFG_SWR[20]), .B(n2814), .Y(n2056) );
NAND2X1TS U3091 ( .A(FPADDSUB_DmP_mant_SFG_SWR[19]), .B(n2759), .Y(n2511) );
OAI22X1TS U3092 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[18]), .A1(n2809), .B0(n2052),
.B1(n2051), .Y(n2510) );
AOI22X1TS U3093 ( .A0(FPADDSUB_DMP_SFG[17]), .A1(n2791), .B0(n2511), .B1(
n2510), .Y(n2058) );
AOI22X1TS U3094 ( .A0(n995), .A1(n2058), .B0(n2060), .B1(n2922), .Y(n2055)
);
CLKAND2X2TS U3095 ( .A(FPADDSUB_DmP_mant_SFG_SWR[20]), .B(n2814), .Y(n2059)
);
OAI21XLTS U3096 ( .A0(n2056), .A1(n2059), .B0(n2055), .Y(n2054) );
OAI31X1TS U3097 ( .A0(n2056), .A1(n2055), .A2(n2059), .B0(n2054), .Y(
FPADDSUB_Raw_mant_SGF[20]) );
INVX2TS U3098 ( .A(intadd_1057_SUM_9_), .Y(n2241) );
NOR2X1TS U3099 ( .A(n2249), .B(n2241), .Y(DP_OP_496J314_122_3540_n282) );
NOR2X1TS U3100 ( .A(FPADDSUB_DmP_mant_SFG_SWR[22]), .B(n2828), .Y(n2063) );
NAND2X1TS U3101 ( .A(FPADDSUB_DmP_mant_SFG_SWR[21]), .B(n2795), .Y(n2516) );
OAI22X1TS U3102 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[20]), .A1(n2814), .B0(n2059),
.B1(n2058), .Y(n2515) );
AOI22X1TS U3103 ( .A0(FPADDSUB_DMP_SFG[19]), .A1(n2760), .B0(n2516), .B1(
n2515), .Y(n2132) );
AOI22X1TS U3104 ( .A0(n995), .A1(n2132), .B0(n2134), .B1(n2525), .Y(n2062)
);
CLKAND2X2TS U3105 ( .A(FPADDSUB_DmP_mant_SFG_SWR[22]), .B(n2828), .Y(n2133)
);
OAI31X1TS U3106 ( .A0(n2063), .A1(n2062), .A2(n2133), .B0(n2061), .Y(
FPADDSUB_Raw_mant_SGF[22]) );
NOR2X1TS U3107 ( .A(n987), .B(n2191), .Y(DP_OP_496J314_122_3540_n287) );
NAND2X2TS U3108 ( .A(intadd_1056_SUM_5_), .B(intadd_1059_n1), .Y(n2201) );
OAI21X4TS U3109 ( .A0(intadd_1057_SUM_5_), .A1(intadd_1060_n1), .B0(n2140),
.Y(n2199) );
NOR2X1TS U3110 ( .A(n2201), .B(n2199), .Y(DP_OP_496J314_122_3540_n145) );
INVX2TS U3111 ( .A(intadd_1057_SUM_1_), .Y(n2267) );
OAI22X1TS U3112 ( .A0(n2267), .A1(n2258), .B0(n2265), .B1(n2260), .Y(
DP_OP_496J314_122_3540_n365) );
INVX2TS U3113 ( .A(DP_OP_496J314_122_3540_n365), .Y(
DP_OP_496J314_122_3540_n366) );
NOR2X1TS U3114 ( .A(n2201), .B(n2220), .Y(DP_OP_496J314_122_3540_n148) );
NOR2X1TS U3115 ( .A(n2191), .B(n2241), .Y(DP_OP_496J314_122_3540_n288) );
OAI21X1TS U3116 ( .A0(intadd_1057_SUM_4_), .A1(n2088), .B0(n2064), .Y(
DP_OP_496J314_122_3540_n414) );
NOR2X1TS U3117 ( .A(n987), .B(n2240), .Y(DP_OP_496J314_122_3540_n293) );
INVX2TS U3118 ( .A(intadd_1054_SUM_0_), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[1]) );
INVX2TS U3119 ( .A(intadd_1059_SUM_4_), .Y(n2207) );
INVX2TS U3120 ( .A(intadd_1060_SUM_4_), .Y(n2208) );
NOR2X1TS U3121 ( .A(n2207), .B(n2208), .Y(DP_OP_496J314_122_3540_n162) );
NOR2X1TS U3122 ( .A(n2240), .B(n2235), .Y(DP_OP_496J314_122_3540_n296) );
INVX2TS U3123 ( .A(intadd_1060_SUM_3_), .Y(n2214) );
NOR2X1TS U3124 ( .A(n2241), .B(n2242), .Y(DP_OP_496J314_122_3540_n306) );
NOR2X1TS U3125 ( .A(n2200), .B(n2208), .Y(DP_OP_496J314_122_3540_n154) );
NAND2X1TS U3126 ( .A(intadd_1060_SUM_0_), .B(n2066), .Y(n2233) );
NAND2X1TS U3127 ( .A(intadd_1059_SUM_0_), .B(n2067), .Y(n2232) );
INVX2TS U3128 ( .A(n2068), .Y(DP_OP_496J314_122_3540_n128) );
INVX2TS U3129 ( .A(intadd_1060_SUM_1_), .Y(n2222) );
NOR2X1TS U3130 ( .A(n2201), .B(n2222), .Y(DP_OP_496J314_122_3540_n149) );
NOR2X1TS U3131 ( .A(n2224), .B(n2140), .Y(DP_OP_496J314_122_3540_n184) );
INVX2TS U3132 ( .A(intadd_1057_SUM_8_), .Y(n2238) );
NOR2X1TS U3133 ( .A(n2191), .B(n2238), .Y(DP_OP_496J314_122_3540_n289) );
NOR2X1TS U3134 ( .A(n2072), .B(n2220), .Y(DP_OP_496J314_122_3540_n204) );
NOR2X1TS U3135 ( .A(n2223), .B(n2140), .Y(DP_OP_496J314_122_3540_n192) );
INVX2TS U3136 ( .A(intadd_1057_SUM_0_), .Y(n2261) );
INVX2TS U3137 ( .A(DP_OP_496J314_122_3540_n370), .Y(
DP_OP_496J314_122_3540_n371) );
NOR2X1TS U3138 ( .A(n2191), .B(n2235), .Y(DP_OP_496J314_122_3540_n290) );
INVX2TS U3139 ( .A(intadd_1054_SUM_1_), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[2]) );
NOR2X1TS U3140 ( .A(n2072), .B(n2222), .Y(DP_OP_496J314_122_3540_n205) );
NOR2X1TS U3141 ( .A(n987), .B(n2242), .Y(DP_OP_496J314_122_3540_n305) );
NOR2X1TS U3142 ( .A(n2207), .B(n2222), .Y(DP_OP_496J314_122_3540_n165) );
NOR2X1TS U3143 ( .A(n2224), .B(n2208), .Y(DP_OP_496J314_122_3540_n186) );
NOR2X1TS U3144 ( .A(n2072), .B(n2140), .Y(DP_OP_496J314_122_3540_n200) );
NOR2X1TS U3145 ( .A(n2200), .B(n2222), .Y(DP_OP_496J314_122_3540_n157) );
NOR2X1TS U3146 ( .A(n2223), .B(n2220), .Y(DP_OP_496J314_122_3540_n196) );
NOR2X1TS U3147 ( .A(n2071), .B(n2207), .Y(DP_OP_496J314_122_3540_n167) );
INVX2TS U3148 ( .A(intadd_1058_n1), .Y(DP_OP_496J314_122_3540_n224) );
NOR2X1TS U3149 ( .A(n2207), .B(n2199), .Y(DP_OP_496J314_122_3540_n161) );
NOR2X1TS U3150 ( .A(n2225), .B(n2207), .Y(DP_OP_496J314_122_3540_n166) );
NOR2X1TS U3151 ( .A(n2223), .B(n2208), .Y(DP_OP_496J314_122_3540_n194) );
NOR2X1TS U3152 ( .A(n2071), .B(n2200), .Y(DP_OP_496J314_122_3540_n159) );
NOR2X1TS U3153 ( .A(n2071), .B(n2218), .Y(DP_OP_496J314_122_3540_n183) );
INVX2TS U3154 ( .A(intadd_1059_SUM_3_), .Y(n2213) );
NOR2X1TS U3155 ( .A(n2213), .B(n2199), .Y(DP_OP_496J314_122_3540_n169) );
INVX2TS U3156 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]), .Y(
DP_OP_496J314_122_3540_n228) );
INVX2TS U3157 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]), .Y(
DP_OP_496J314_122_3540_n227) );
NOR2X1TS U3158 ( .A(n2218), .B(n2199), .Y(DP_OP_496J314_122_3540_n177) );
INVX2TS U3159 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]), .Y(
DP_OP_496J314_122_3540_n229) );
NOR4X2TS U3160 ( .A(n2235), .B(n2239), .C(n2242), .D(n2238), .Y(n2254) );
NOR3X1TS U3161 ( .A(n2254), .B(n2238), .C(n2239), .Y(
DP_OP_496J314_122_3540_n273) );
NOR2X1TS U3162 ( .A(n2225), .B(n2218), .Y(DP_OP_496J314_122_3540_n182) );
INVX2TS U3163 ( .A(intadd_1054_SUM_2_), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[3]) );
NOR2X1TS U3164 ( .A(n2071), .B(n2213), .Y(DP_OP_496J314_122_3540_n175) );
NOR2X1TS U3165 ( .A(n2072), .B(n2214), .Y(DP_OP_496J314_122_3540_n203) );
NOR2X1TS U3166 ( .A(n2225), .B(n2213), .Y(DP_OP_496J314_122_3540_n174) );
NOR2X1TS U3167 ( .A(n2224), .B(n2214), .Y(DP_OP_496J314_122_3540_n187) );
NOR2X1TS U3168 ( .A(n2224), .B(n2199), .Y(DP_OP_496J314_122_3540_n185) );
NOR2X1TS U3169 ( .A(n2213), .B(n2222), .Y(DP_OP_496J314_122_3540_n173) );
NOR2X1TS U3170 ( .A(n2223), .B(n2214), .Y(DP_OP_496J314_122_3540_n195) );
NOR2X1TS U3171 ( .A(n2072), .B(n2199), .Y(DP_OP_496J314_122_3540_n201) );
OAI21X1TS U3172 ( .A0(n2207), .A1(n2140), .B0(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]), .Y(
DP_OP_496J314_122_3540_n31) );
INVX2TS U3173 ( .A(intadd_1054_SUM_3_), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[4]) );
INVX2TS U3174 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[10]), .Y(
DP_OP_496J314_122_3540_n133) );
INVX2TS U3175 ( .A(n2201), .Y(n2078) );
NAND2X1TS U3176 ( .A(n2078), .B(intadd_1060_SUM_3_), .Y(n2138) );
INVX2TS U3177 ( .A(n2140), .Y(n2077) );
NAND2X1TS U3178 ( .A(intadd_1059_SUM_3_), .B(n2077), .Y(n2137) );
INVX2TS U3179 ( .A(n2073), .Y(DP_OP_496J314_122_3540_n40) );
OA22X1TS U3180 ( .A0(n2275), .A1(n2258), .B0(n2274), .B1(n2260), .Y(n2083)
);
AOI21X1TS U3181 ( .A0(intadd_1059_A_2_), .A1(intadd_1059_A_3_), .B0(n2268),
.Y(n2081) );
OAI31X1TS U3182 ( .A0(n2274), .A1(n2075), .A2(n2258), .B0(n2074), .Y(n2076)
);
CLKXOR2X2TS U3183 ( .A(intadd_1055_n1), .B(n2076), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]) );
INVX2TS U3184 ( .A(DP_OP_496J314_122_3540_n21), .Y(n2285) );
OAI21X1TS U3185 ( .A0(n2200), .A1(n2140), .B0(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]), .Y(
n2139) );
INVX2TS U3186 ( .A(n2139), .Y(n2284) );
NAND2X1TS U3187 ( .A(n2078), .B(n2077), .Y(n2283) );
NAND2X1TS U3188 ( .A(intadd_1054_n1), .B(n2080), .Y(n2079) );
INVX2TS U3189 ( .A(n2079), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[16]) );
INVX2TS U3190 ( .A(intadd_1054_SUM_5_), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[6]) );
INVX2TS U3191 ( .A(intadd_1054_SUM_4_), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[5]) );
NOR3X2TS U3192 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[5]), .B(n2220), .C(n2224), .Y(DP_OP_496J314_122_3540_n106) );
OAI21X1TS U3193 ( .A0(intadd_1054_n1), .A1(n2080), .B0(n2079), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[15]) );
INVX2TS U3194 ( .A(intadd_1054_SUM_10_), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[11]) );
INVX2TS U3195 ( .A(intadd_1054_SUM_9_), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[10]) );
INVX2TS U3196 ( .A(intadd_1054_SUM_12_), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[13]) );
INVX2TS U3197 ( .A(intadd_1054_SUM_13_), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[14]) );
INVX2TS U3198 ( .A(DP_OP_496J314_122_3540_n27), .Y(intadd_1054_B_12_) );
INVX2TS U3199 ( .A(DP_OP_496J314_122_3540_n23), .Y(intadd_1054_A_12_) );
CMPR32X2TS U3200 ( .A(n2083), .B(n2082), .C(n2081), .CO(n2075), .S(n2084) );
INVX2TS U3201 ( .A(n2084), .Y(intadd_1055_A_9_) );
INVX2TS U3202 ( .A(DP_OP_496J314_122_3540_n22), .Y(intadd_1054_A_13_) );
INVX2TS U3203 ( .A(intadd_1054_SUM_11_), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[12]) );
INVX2TS U3204 ( .A(DP_OP_496J314_122_3540_n43), .Y(intadd_1054_A_9_) );
INVX2TS U3205 ( .A(DP_OP_496J314_122_3540_n35), .Y(intadd_1054_B_10_) );
INVX2TS U3206 ( .A(DP_OP_496J314_122_3540_n42), .Y(intadd_1054_A_10_) );
INVX2TS U3207 ( .A(DP_OP_496J314_122_3540_n34), .Y(intadd_1054_B_11_) );
INVX2TS U3208 ( .A(DP_OP_496J314_122_3540_n28), .Y(intadd_1054_A_11_) );
NOR3X2TS U3209 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]), .B(n2214), .C(n2213), .Y(DP_OP_496J314_122_3540_n72) );
INVX2TS U3210 ( .A(n2191), .Y(intadd_1059_B_3_) );
INVX2TS U3211 ( .A(intadd_1054_SUM_8_), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[9]) );
INVX2TS U3212 ( .A(DP_OP_496J314_122_3540_n52), .Y(intadd_1054_A_8_) );
INVX2TS U3213 ( .A(intadd_1054_SUM_7_), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[8]) );
INVX2TS U3214 ( .A(DP_OP_496J314_122_3540_n63), .Y(intadd_1054_B_7_) );
INVX2TS U3215 ( .A(DP_OP_496J314_122_3540_n75), .Y(intadd_1054_A_7_) );
OAI22X1TS U3216 ( .A0(intadd_1057_SUM_3_), .A1(n2087), .B0(
intadd_1057_SUM_2_), .B1(n2088), .Y(n2085) );
AOI21X1TS U3217 ( .A0(n2090), .A1(intadd_1057_SUM_3_), .B0(n2085), .Y(n2100)
);
AOI22X1TS U3218 ( .A0(intadd_1057_SUM_1_), .A1(intadd_1059_A_2_), .B0(n2276),
.B1(n2267), .Y(n2094) );
AOI22X1TS U3219 ( .A0(intadd_1057_SUM_0_), .A1(intadd_1059_A_2_), .B0(n2276),
.B1(n2261), .Y(n2092) );
AOI22X1TS U3220 ( .A0(n2097), .A1(n2094), .B0(n2095), .B1(n2092), .Y(n2099)
);
NAND2X1TS U3221 ( .A(n2196), .B(n2273), .Y(n2098) );
INVX2TS U3222 ( .A(n2086), .Y(intadd_1055_B_1_) );
OAI22X1TS U3223 ( .A0(intadd_1057_SUM_1_), .A1(n2088), .B0(
intadd_1057_SUM_2_), .B1(n2087), .Y(n2089) );
AOI21X1TS U3224 ( .A0(n2090), .A1(intadd_1057_SUM_2_), .B0(n2089), .Y(n2194)
);
AOI22X1TS U3225 ( .A0(n2196), .A1(intadd_1059_A_2_), .B0(n2276), .B1(n2259),
.Y(n2091) );
AOI22X1TS U3226 ( .A0(n2097), .A1(n2092), .B0(n2095), .B1(n2091), .Y(n2195)
);
NOR2X1TS U3227 ( .A(n2194), .B(n2195), .Y(intadd_1055_A_1_) );
AOI22X1TS U3228 ( .A0(intadd_1057_SUM_0_), .A1(intadd_1059_A_4_), .B0(n2268),
.B1(n2261), .Y(n2270) );
AOI22X1TS U3229 ( .A0(n2196), .A1(intadd_1059_A_4_), .B0(n2268), .B1(n2259),
.Y(n2093) );
AOI22X1TS U3230 ( .A0(n2273), .A1(n2270), .B0(n2271), .B1(n2093), .Y(n2104)
);
AOI22X1TS U3231 ( .A0(n2097), .A1(n2096), .B0(n2095), .B1(n2094), .Y(n2103)
);
CMPR32X2TS U3232 ( .A(n2100), .B(n2099), .C(n2098), .CO(n2102), .S(n2086) );
INVX2TS U3233 ( .A(n2101), .Y(intadd_1055_A_2_) );
CMPR32X2TS U3234 ( .A(n2104), .B(n2103), .C(n2102), .CO(n2105), .S(n2101) );
INVX2TS U3235 ( .A(n2105), .Y(intadd_1055_B_3_) );
INVX2TS U3236 ( .A(intadd_1054_SUM_6_), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[7]) );
INVX2TS U3237 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]), .Y(
DP_OP_496J314_122_3540_n234) );
INVX2TS U3238 ( .A(DP_OP_496J314_122_3540_n125), .Y(intadd_1054_A_1_) );
INVX2TS U3239 ( .A(DP_OP_496J314_122_3540_n118), .Y(intadd_1054_A_2_) );
INVX2TS U3240 ( .A(DP_OP_496J314_122_3540_n110), .Y(intadd_1054_A_3_) );
INVX2TS U3241 ( .A(DP_OP_496J314_122_3540_n100), .Y(intadd_1054_A_4_) );
INVX2TS U3242 ( .A(DP_OP_496J314_122_3540_n99), .Y(intadd_1054_B_5_) );
INVX2TS U3243 ( .A(DP_OP_496J314_122_3540_n89), .Y(intadd_1054_A_5_) );
INVX2TS U3244 ( .A(DP_OP_496J314_122_3540_n76), .Y(intadd_1054_B_6_) );
INVX2TS U3245 ( .A(DP_OP_496J314_122_3540_n88), .Y(intadd_1054_A_6_) );
OR2X1TS U3246 ( .A(FPSENCOS_d_ff_Xn[24]), .B(n2555), .Y(
FPSENCOS_first_mux_X[24]) );
OR2X1TS U3247 ( .A(FPSENCOS_d_ff_Xn[27]), .B(n2555), .Y(
FPSENCOS_first_mux_X[27]) );
INVX2TS U3248 ( .A(n2106), .Y(n2108) );
NOR2XLTS U3249 ( .A(FPADDSUB_Raw_mant_NRM_SWR[13]), .B(
FPADDSUB_Raw_mant_NRM_SWR[11]), .Y(n2107) );
OAI22X1TS U3250 ( .A0(n2109), .A1(n2108), .B0(n2107), .B1(n2121), .Y(n2110)
);
AOI21X1TS U3251 ( .A0(n2111), .A1(FPADDSUB_Raw_mant_NRM_SWR[3]), .B0(n2110),
.Y(n2112) );
OAI211X1TS U3252 ( .A0(n2114), .A1(n2841), .B0(n2113), .C0(n2112), .Y(
FPADDSUB_LZD_raw_out_EWR[2]) );
INVX2TS U3253 ( .A(n2115), .Y(n2117) );
NOR3X1TS U3254 ( .A(FPADDSUB_Raw_mant_NRM_SWR[2]), .B(n2131), .C(n2797), .Y(
n2127) );
AOI211X1TS U3255 ( .A0(n2118), .A1(n2117), .B0(n2116), .C0(n2127), .Y(n2120)
);
OAI211X1TS U3256 ( .A0(n2122), .A1(n2121), .B0(n2120), .C0(n2119), .Y(
FPADDSUB_LZD_raw_out_EWR[3]) );
OAI31X1TS U3257 ( .A0(n2125), .A1(FPADDSUB_Raw_mant_NRM_SWR[10]), .A2(n2124),
.B0(n2123), .Y(n2126) );
AOI211X1TS U3258 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[5]), .A1(n2128), .B0(n2127),
.C0(n2126), .Y(n2129) );
OAI211X1TS U3259 ( .A0(n2877), .A1(n2131), .B0(n2130), .C0(n2129), .Y(
FPADDSUB_LZD_raw_out_EWR[4]) );
NOR2X1TS U3260 ( .A(FPADDSUB_DmP_mant_SFG_SWR[24]), .B(n2843), .Y(n2524) );
NAND2X1TS U3261 ( .A(FPADDSUB_DmP_mant_SFG_SWR[23]), .B(n2813), .Y(n2521) );
OAI22X1TS U3262 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[22]), .A1(n2828), .B0(n2133),
.B1(n2132), .Y(n2520) );
AOI22X1TS U3263 ( .A0(FPADDSUB_DMP_SFG[21]), .A1(n2763), .B0(n2521), .B1(
n2520), .Y(n2527) );
AOI21X1TS U3264 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[24]), .A1(n2843), .B0(n2527),
.Y(n2135) );
AOI222X4TS U3265 ( .A0(n2519), .A1(n2813), .B0(n2519), .B1(n2763), .C0(n2813), .C1(n2763), .Y(n2526) );
OAI32X1TS U3266 ( .A0(n2525), .A1(n2524), .A2(n2135), .B0(n2287), .B1(n2490),
.Y(n2136) );
XOR2XLTS U3267 ( .A(n957), .B(n2136), .Y(FPADDSUB_Raw_mant_SGF[25]) );
CMPR32X2TS U3268 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[11]), .B(
n2138), .C(n2137), .CO(n2203), .S(n2073) );
NOR3X1TS U3269 ( .A(n2203), .B(n2208), .C(n2201), .Y(
DP_OP_496J314_122_3540_n29) );
OAI31X1TS U3270 ( .A0(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]), .A1(
n2140), .A2(n2207), .B0(DP_OP_496J314_122_3540_n31), .Y(
DP_OP_496J314_122_3540_n32) );
OAI31X1TS U3271 ( .A0(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]), .A1(
n2140), .A2(n2200), .B0(n2139), .Y(DP_OP_496J314_122_3540_n25) );
NAND2X1TS U3272 ( .A(intadd_1057_SUM_7_), .B(intadd_1059_B_1_), .Y(n2142) );
NAND2X1TS U3273 ( .A(intadd_1059_CI), .B(intadd_1057_SUM_8_), .Y(n2141) );
AOI21X1TS U3274 ( .A0(n2142), .A1(n2141), .B0(n2254), .Y(intadd_1058_B_1_)
);
NOR3XLTS U3275 ( .A(FPSENCOS_cont_var_out[1]), .B(FPSENCOS_cont_var_out[0]),
.C(n950), .Y(FPSENCOS_enab_d_ff4_Xn) );
NOR3XLTS U3276 ( .A(FPSENCOS_cont_var_out[1]), .B(n2808), .C(n950), .Y(
FPSENCOS_enab_d_ff4_Yn) );
OAI21XLTS U3277 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(n962), .B0(n2143),
.Y(n810) );
INVX2TS U3278 ( .A(n2570), .Y(n2568) );
NOR2X1TS U3279 ( .A(n967), .B(n2568), .Y(n2564) );
NAND2X1TS U3280 ( .A(n2564), .B(n950), .Y(n2720) );
INVX2TS U3281 ( .A(n2720), .Y(n2719) );
OAI21XLTS U3282 ( .A0(n2719), .A1(n2808), .B0(FPSENCOS_cont_var_out[1]), .Y(
n2144) );
XNOR2X1TS U3283 ( .A(DP_OP_234J314_129_4955_n1), .B(n2145), .Y(
FPMULT_Exp_module_Overflow_A) );
NOR2XLTS U3284 ( .A(FPMULT_FSM_selector_B[1]), .B(FPMULT_Op_MY[23]), .Y(
n2147) );
OAI21XLTS U3285 ( .A0(FPMULT_FSM_selector_B[0]), .A1(n2147), .B0(n2146), .Y(
n2148) );
XOR2X1TS U3286 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n2148), .Y(
DP_OP_234J314_129_4955_n22) );
NOR2BX1TS U3287 ( .AN(FPADDSUB_LZD_output_NRM2_EW[2]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n2149) );
XOR2X1TS U3288 ( .A(n962), .B(n2149), .Y(DP_OP_26J314_126_1325_n16) );
NOR2BX1TS U3289 ( .AN(FPADDSUB_LZD_output_NRM2_EW[1]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n2150) );
XOR2X1TS U3290 ( .A(n962), .B(n2150), .Y(DP_OP_26J314_126_1325_n17) );
OR2X1TS U3291 ( .A(FPADDSUB_ADD_OVRFLW_NRM2), .B(
FPADDSUB_LZD_output_NRM2_EW[0]), .Y(n2151) );
XOR2X1TS U3292 ( .A(n962), .B(n2151), .Y(DP_OP_26J314_126_1325_n18) );
AO21XLTS U3293 ( .A0(n2153), .A1(FPMULT_FSM_selector_B[1]), .B0(n2152), .Y(
n829) );
NOR2BX1TS U3294 ( .AN(FPADDSUB_exp_rslt_NRM2_EW1[7]), .B(n2959), .Y(
FPADDSUB_formatted_number_W[30]) );
AOI2BB1XLTS U3295 ( .A0N(n2958), .A1N(FPADDSUB_SIGN_FLAG_SHT1SHT2), .B0(
n2959), .Y(FPADDSUB_formatted_number_W[31]) );
AOI21X1TS U3296 ( .A0(n2155), .A1(n2154), .B0(
FPMULT_Adder_M_result_A_adder[24]), .Y(
FPMULT_Adder_M_result_A_adder[23]) );
OA21XLTS U3297 ( .A0(FPMULT_Sgf_normalized_result[22]), .A1(n2156), .B0(
n2155), .Y(FPMULT_Adder_M_result_A_adder[22]) );
AOI21X1TS U3298 ( .A0(n2157), .A1(n2158), .B0(n2156), .Y(
FPMULT_Adder_M_result_A_adder[21]) );
OA21XLTS U3299 ( .A0(FPMULT_Sgf_normalized_result[20]), .A1(n2159), .B0(
n2158), .Y(FPMULT_Adder_M_result_A_adder[20]) );
AOI21X1TS U3300 ( .A0(n2160), .A1(n2161), .B0(n2159), .Y(
FPMULT_Adder_M_result_A_adder[19]) );
OA21XLTS U3301 ( .A0(FPMULT_Sgf_normalized_result[18]), .A1(n2162), .B0(
n2161), .Y(FPMULT_Adder_M_result_A_adder[18]) );
AOI21X1TS U3302 ( .A0(n2163), .A1(n2164), .B0(n2162), .Y(
FPMULT_Adder_M_result_A_adder[17]) );
OA21XLTS U3303 ( .A0(FPMULT_Sgf_normalized_result[16]), .A1(n2165), .B0(
n2164), .Y(FPMULT_Adder_M_result_A_adder[16]) );
AOI21X1TS U3304 ( .A0(n2166), .A1(n2167), .B0(n2165), .Y(
FPMULT_Adder_M_result_A_adder[15]) );
OA21XLTS U3305 ( .A0(FPMULT_Sgf_normalized_result[14]), .A1(n2168), .B0(
n2167), .Y(FPMULT_Adder_M_result_A_adder[14]) );
AOI21X1TS U3306 ( .A0(n2169), .A1(n2170), .B0(n2168), .Y(
FPMULT_Adder_M_result_A_adder[13]) );
OA21XLTS U3307 ( .A0(FPMULT_Sgf_normalized_result[12]), .A1(n2171), .B0(
n2170), .Y(FPMULT_Adder_M_result_A_adder[12]) );
AOI21X1TS U3308 ( .A0(n2172), .A1(n2173), .B0(n2171), .Y(
FPMULT_Adder_M_result_A_adder[11]) );
OA21XLTS U3309 ( .A0(FPMULT_Sgf_normalized_result[10]), .A1(n2174), .B0(
n2173), .Y(FPMULT_Adder_M_result_A_adder[10]) );
AOI21X1TS U3310 ( .A0(n2175), .A1(n2176), .B0(n2174), .Y(
FPMULT_Adder_M_result_A_adder[9]) );
OA21XLTS U3311 ( .A0(FPMULT_Sgf_normalized_result[8]), .A1(n2177), .B0(n2176), .Y(FPMULT_Adder_M_result_A_adder[8]) );
AOI21X1TS U3312 ( .A0(n2178), .A1(n2179), .B0(n2177), .Y(
FPMULT_Adder_M_result_A_adder[7]) );
OA21XLTS U3313 ( .A0(FPMULT_Sgf_normalized_result[6]), .A1(n2180), .B0(n2179), .Y(FPMULT_Adder_M_result_A_adder[6]) );
AOI21X1TS U3314 ( .A0(n2185), .A1(n2181), .B0(n2180), .Y(
FPMULT_Adder_M_result_A_adder[5]) );
AOI21X1TS U3315 ( .A0(n2183), .A1(n2182), .B0(n2186), .Y(
FPMULT_Adder_M_result_A_adder[3]) );
AO21XLTS U3316 ( .A0(FPMULT_Sgf_normalized_result[2]), .A1(n2184), .B0(n2183), .Y(FPMULT_Adder_M_result_A_adder[2]) );
AO21XLTS U3317 ( .A0(n2186), .A1(FPMULT_Sgf_normalized_result[4]), .B0(n2185), .Y(FPMULT_Adder_M_result_A_adder[4]) );
NAND2X1TS U3318 ( .A(intadd_1057_SUM_7_), .B(intadd_1059_CI), .Y(n2190) );
NAND2X1TS U3319 ( .A(intadd_1056_SUM_6_), .B(intadd_1057_SUM_8_), .Y(n2189)
);
AOI21X1TS U3320 ( .A0(n2190), .A1(n2189), .B0(n2188), .Y(intadd_1058_A_0_)
);
CMPR32X2TS U3321 ( .A(DP_OP_496J314_122_3540_n247), .B(n2193), .C(n2192),
.CO(intadd_1058_B_8_), .S(intadd_1058_B_7_) );
AOI21X1TS U3322 ( .A0(n2195), .A1(n2194), .B0(intadd_1055_A_1_), .Y(
intadd_1055_A_0_) );
OAI32X1TS U3323 ( .A0(n2276), .A1(n2196), .A2(n2281), .B0(n2279), .B1(n2276),
.Y(intadd_1055_B_0_) );
AOI21X1TS U3324 ( .A0(n2198), .A1(n2197), .B0(DP_OP_496J314_122_3540_n380),
.Y(intadd_1055_B_2_) );
OAI22X1TS U3325 ( .A0(n2201), .A1(n2208), .B0(n2200), .B1(n2199), .Y(n2202)
);
XNOR2X1TS U3326 ( .A(n2203), .B(n2202), .Y(DP_OP_496J314_122_3540_n30) );
INVX2TS U3327 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[9]), .Y(n2206) );
CMPR32X2TS U3328 ( .A(n2206), .B(n2205), .C(n2204), .CO(
DP_OP_496J314_122_3540_n59), .S(DP_OP_496J314_122_3540_n60) );
NOR2X1TS U3329 ( .A(n2207), .B(n2220), .Y(n2210) );
NOR2X1TS U3330 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[7]), .B(n2212), .Y(n2211) );
CMPR32X2TS U3331 ( .A(n2210), .B(n2209), .C(n2211), .CO(
DP_OP_496J314_122_3540_n70), .S(DP_OP_496J314_122_3540_n71) );
OAI32X1TS U3332 ( .A0(DP_OP_496J314_122_3540_n72), .A1(n2214), .A2(n2213),
.B0(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]), .B1(
DP_OP_496J314_122_3540_n72), .Y(DP_OP_496J314_122_3540_n73) );
AOI21X1TS U3333 ( .A0(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[7]), .A1(
n2212), .B0(n2211), .Y(n2217) );
NOR2X1TS U3334 ( .A(n2213), .B(n2220), .Y(n2216) );
CMPR32X2TS U3335 ( .A(n2217), .B(n2216), .C(n2215), .CO(
DP_OP_496J314_122_3540_n83), .S(DP_OP_496J314_122_3540_n84) );
NOR3X2TS U3336 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[4]), .B(n2222), .C(n2224), .Y(n2221) );
CMPR32X2TS U3337 ( .A(DP_OP_496J314_122_3540_n111), .B(n2219), .C(n2221),
.CO(DP_OP_496J314_122_3540_n104), .S(DP_OP_496J314_122_3540_n105) );
OAI32X1TS U3338 ( .A0(DP_OP_496J314_122_3540_n106), .A1(n2220), .A2(n2224),
.B0(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[5]), .B1(
DP_OP_496J314_122_3540_n106), .Y(DP_OP_496J314_122_3540_n107) );
OAI32X1TS U3339 ( .A0(n2221), .A1(n2222), .A2(n2224), .B0(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[4]), .B1(
n2221), .Y(DP_OP_496J314_122_3540_n115) );
CMPR32X2TS U3340 ( .A(DP_OP_496J314_122_3540_n123), .B(n2227), .C(n2226),
.CO(DP_OP_496J314_122_3540_n119), .S(DP_OP_496J314_122_3540_n120) );
AOI21X1TS U3341 ( .A0(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[3]), .A1(
n2228), .B0(DP_OP_496J314_122_3540_n121), .Y(
DP_OP_496J314_122_3540_n122) );
NAND2X1TS U3342 ( .A(intadd_1059_SUM_0_), .B(intadd_1060_SUM_0_), .Y(n2230)
);
AOI21X1TS U3343 ( .A0(n2231), .A1(n2230), .B0(n2229), .Y(
DP_OP_496J314_122_3540_n127) );
CMPR32X2TS U3344 ( .A(n2234), .B(n2233), .C(n2232), .CO(n2068), .S(
intadd_1054_CI) );
NAND2X1TS U3345 ( .A(intadd_1057_SUM_9_), .B(intadd_1059_B_2_), .Y(n2247) );
NAND2X1TS U3346 ( .A(intadd_1057_SUM_7_), .B(intadd_1059_B_4_), .Y(n2246) );
AOI21X1TS U3347 ( .A0(n2247), .A1(n2246), .B0(n2245), .Y(
DP_OP_496J314_122_3540_n261) );
CMPR32X2TS U3348 ( .A(n2254), .B(n2253), .C(n2252), .CO(
DP_OP_496J314_122_3540_n265), .S(DP_OP_496J314_122_3540_n266) );
NAND2X1TS U3349 ( .A(intadd_1059_B_2_), .B(intadd_1057_SUM_8_), .Y(n2257) );
NAND2X1TS U3350 ( .A(intadd_1057_SUM_9_), .B(intadd_1059_B_1_), .Y(n2256) );
AOI21X1TS U3351 ( .A0(n2257), .A1(n2256), .B0(n2255), .Y(
DP_OP_496J314_122_3540_n268) );
OAI22X1TS U3352 ( .A0(n2263), .A1(n2260), .B0(n2265), .B1(n2258), .Y(
DP_OP_496J314_122_3540_n392) );
OAI22X1TS U3353 ( .A0(n2261), .A1(n2260), .B0(n2259), .B1(n2258), .Y(
DP_OP_496J314_122_3540_n393) );
AOI22X1TS U3354 ( .A0(intadd_1057_SUM_4_), .A1(intadd_1059_A_4_), .B0(n2268),
.B1(n2275), .Y(n2264) );
AOI22X1TS U3355 ( .A0(intadd_1057_SUM_3_), .A1(intadd_1059_A_4_), .B0(n2268),
.B1(n2263), .Y(n2266) );
AOI22X1TS U3356 ( .A0(intadd_1059_A_4_), .A1(intadd_1057_SUM_2_), .B0(n2265),
.B1(n2268), .Y(n2269) );
AOI22X1TS U3357 ( .A0(intadd_1057_SUM_1_), .A1(intadd_1059_A_4_), .B0(n2268),
.B1(n2267), .Y(n2272) );
AOI22X1TS U3358 ( .A0(intadd_1059_A_2_), .A1(n2274), .B0(intadd_1057_SUM_5_),
.B1(n2276), .Y(n2277) );
OAI22X1TS U3359 ( .A0(n2281), .A1(n2276), .B0(n2279), .B1(n2277), .Y(
DP_OP_496J314_122_3540_n404) );
AOI22X1TS U3360 ( .A0(intadd_1057_SUM_4_), .A1(n2276), .B0(intadd_1059_A_2_),
.B1(n2275), .Y(n2280) );
OAI22X1TS U3361 ( .A0(n2281), .A1(n2277), .B0(n2279), .B1(n2280), .Y(
DP_OP_496J314_122_3540_n405) );
OAI22X1TS U3362 ( .A0(n2281), .A1(n2280), .B0(n2279), .B1(n2278), .Y(
DP_OP_496J314_122_3540_n406) );
AOI21X1TS U3363 ( .A0(intadd_1057_SUM_5_), .A1(n2282), .B0(
DP_OP_496J314_122_3540_n412), .Y(DP_OP_496J314_122_3540_n413) );
CMPR32X2TS U3364 ( .A(n2285), .B(n2284), .C(n2283), .CO(n2080), .S(
intadd_1054_B_13_) );
XOR2XLTS U3365 ( .A(FPADDSUB_DMP_EXP_EWSW[27]), .B(FPADDSUB_DmP_EXP_EWSW[27]), .Y(n2286) );
XOR2XLTS U3366 ( .A(intadd_1063_n1), .B(n2286), .Y(
FPADDSUB_Shift_amount_EXP_EW[4]) );
AOI21X1TS U3367 ( .A0(n2287), .A1(n957), .B0(n2490), .Y(n2960) );
NOR2BX1TS U3368 ( .AN(operation[0]), .B(n2586), .Y(n2965) );
AOI2BB2XLTS U3369 ( .B0(FPSENCOS_cont_var_out[0]), .B1(
FPSENCOS_d_ff3_sign_out), .A0N(FPSENCOS_d_ff3_sign_out), .A1N(
FPSENCOS_cont_var_out[0]), .Y(n2288) );
AO22XLTS U3370 ( .A0(operation[1]), .A1(n2288), .B0(n2586), .B1(operation[0]), .Y(n2292) );
AOI222X1TS U3371 ( .A0(n2659), .A1(Data_2[31]), .B0(n2289), .B1(
FPSENCOS_d_ff3_sh_x_out[31]), .C0(FPSENCOS_d_ff3_sh_y_out[31]), .C1(
n2587), .Y(n2290) );
INVX2TS U3372 ( .A(n2290), .Y(n2291) );
XNOR2X1TS U3373 ( .A(n2292), .B(n2291), .Y(n2881) );
NOR2X1TS U3374 ( .A(n2867), .B(FPADDSUB_intDX_EWSW[25]), .Y(n2351) );
NOR2XLTS U3375 ( .A(n2351), .B(FPADDSUB_intDY_EWSW[24]), .Y(n2293) );
AOI22X1TS U3376 ( .A0(FPADDSUB_intDX_EWSW[25]), .A1(n2867), .B0(n965), .B1(
n2293), .Y(n2297) );
OAI21X1TS U3377 ( .A0(FPADDSUB_intDX_EWSW[26]), .A1(n2871), .B0(n2294), .Y(
n2352) );
NAND3XLTS U3378 ( .A(n2871), .B(n2294), .C(FPADDSUB_intDX_EWSW[26]), .Y(
n2296) );
NAND2BXLTS U3379 ( .AN(FPADDSUB_intDY_EWSW[27]), .B(FPADDSUB_intDX_EWSW[27]),
.Y(n2295) );
OAI211XLTS U3380 ( .A0(n2297), .A1(n2352), .B0(n2296), .C0(n2295), .Y(n2302)
);
NOR2X1TS U3381 ( .A(n2889), .B(FPADDSUB_intDX_EWSW[30]), .Y(n2300) );
NOR2X1TS U3382 ( .A(n2888), .B(FPADDSUB_intDX_EWSW[29]), .Y(n2298) );
AOI211X1TS U3383 ( .A0(FPADDSUB_intDY_EWSW[28]), .A1(n2812), .B0(n2300),
.C0(n2298), .Y(n2350) );
NOR3XLTS U3384 ( .A(n2812), .B(n2298), .C(FPADDSUB_intDY_EWSW[28]), .Y(n2299) );
AOI2BB2X1TS U3385 ( .B0(n2302), .B1(n2350), .A0N(n2301), .A1N(n2300), .Y(
n2356) );
NOR2X1TS U3386 ( .A(n2866), .B(FPADDSUB_intDX_EWSW[17]), .Y(n2338) );
NAND2BXLTS U3387 ( .AN(FPADDSUB_intDX_EWSW[9]), .B(FPADDSUB_intDY_EWSW[9]),
.Y(n2319) );
NOR2X1TS U3388 ( .A(n2864), .B(FPADDSUB_intDX_EWSW[11]), .Y(n2317) );
AOI21X1TS U3389 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n2817), .B0(n2317), .Y(
n2322) );
OAI211XLTS U3390 ( .A0(FPADDSUB_intDX_EWSW[8]), .A1(n2868), .B0(n2319), .C0(
n2322), .Y(n2333) );
OAI2BB1X1TS U3391 ( .A0N(n2836), .A1N(FPADDSUB_intDY_EWSW[5]), .B0(
FPADDSUB_intDX_EWSW[4]), .Y(n2303) );
OAI22X1TS U3392 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n2303), .B0(n2836), .B1(
FPADDSUB_intDY_EWSW[5]), .Y(n2314) );
OAI2BB1X1TS U3393 ( .A0N(n2767), .A1N(FPADDSUB_intDY_EWSW[7]), .B0(
FPADDSUB_intDX_EWSW[6]), .Y(n2304) );
OAI22X1TS U3394 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n2304), .B0(n2767), .B1(
FPADDSUB_intDY_EWSW[7]), .Y(n2313) );
OAI21XLTS U3395 ( .A0(FPADDSUB_intDX_EWSW[1]), .A1(n2870), .B0(
FPADDSUB_intDX_EWSW[0]), .Y(n2305) );
OAI2BB2XLTS U3396 ( .B0(FPADDSUB_intDY_EWSW[0]), .B1(n2305), .A0N(
FPADDSUB_intDX_EWSW[1]), .A1N(n2870), .Y(n2307) );
NAND2BXLTS U3397 ( .AN(FPADDSUB_intDX_EWSW[2]), .B(FPADDSUB_intDY_EWSW[2]),
.Y(n2306) );
OAI211XLTS U3398 ( .A0(n2872), .A1(FPADDSUB_intDX_EWSW[3]), .B0(n2307), .C0(
n2306), .Y(n2310) );
OAI21XLTS U3399 ( .A0(FPADDSUB_intDX_EWSW[3]), .A1(n2872), .B0(
FPADDSUB_intDX_EWSW[2]), .Y(n2308) );
AOI2BB2XLTS U3400 ( .B0(FPADDSUB_intDX_EWSW[3]), .B1(n2872), .A0N(
FPADDSUB_intDY_EWSW[2]), .A1N(n2308), .Y(n2309) );
AOI222X1TS U3401 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n2769), .B0(n2310), .B1(
n2309), .C0(FPADDSUB_intDY_EWSW[5]), .C1(n2836), .Y(n2312) );
AOI22X1TS U3402 ( .A0(FPADDSUB_intDY_EWSW[7]), .A1(n2767), .B0(
FPADDSUB_intDY_EWSW[6]), .B1(n2822), .Y(n2311) );
OAI32X1TS U3403 ( .A0(n2314), .A1(n2313), .A2(n2312), .B0(n2311), .B1(n2313),
.Y(n2332) );
OA22X1TS U3404 ( .A0(n2771), .A1(FPADDSUB_intDX_EWSW[14]), .B0(n2865), .B1(
FPADDSUB_intDX_EWSW[15]), .Y(n2329) );
NAND2BXLTS U3405 ( .AN(FPADDSUB_intDX_EWSW[13]), .B(FPADDSUB_intDY_EWSW[13]),
.Y(n2315) );
OAI21XLTS U3406 ( .A0(FPADDSUB_intDX_EWSW[13]), .A1(n2852), .B0(
FPADDSUB_intDX_EWSW[12]), .Y(n2316) );
OAI2BB2XLTS U3407 ( .B0(FPADDSUB_intDY_EWSW[12]), .B1(n2316), .A0N(
FPADDSUB_intDX_EWSW[13]), .A1N(n2852), .Y(n2328) );
NOR2XLTS U3408 ( .A(n2317), .B(FPADDSUB_intDY_EWSW[10]), .Y(n2318) );
AOI22X1TS U3409 ( .A0(FPADDSUB_intDX_EWSW[11]), .A1(n2864), .B0(
FPADDSUB_intDX_EWSW[10]), .B1(n2318), .Y(n2324) );
NAND2BXLTS U3410 ( .AN(FPADDSUB_intDY_EWSW[9]), .B(FPADDSUB_intDX_EWSW[9]),
.Y(n2321) );
NAND3XLTS U3411 ( .A(n2868), .B(n2319), .C(FPADDSUB_intDX_EWSW[8]), .Y(n2320) );
AOI21X1TS U3412 ( .A0(n2321), .A1(n2320), .B0(n2331), .Y(n2323) );
OAI2BB2XLTS U3413 ( .B0(n2324), .B1(n2331), .A0N(n2323), .A1N(n2322), .Y(
n2327) );
OAI21XLTS U3414 ( .A0(FPADDSUB_intDX_EWSW[15]), .A1(n2865), .B0(
FPADDSUB_intDX_EWSW[14]), .Y(n2325) );
OAI2BB2XLTS U3415 ( .B0(FPADDSUB_intDY_EWSW[14]), .B1(n2325), .A0N(
FPADDSUB_intDX_EWSW[15]), .A1N(n2865), .Y(n2326) );
AOI211X1TS U3416 ( .A0(n2329), .A1(n2328), .B0(n2327), .C0(n2326), .Y(n2330)
);
OAI31X1TS U3417 ( .A0(n2333), .A1(n2332), .A2(n2331), .B0(n2330), .Y(n2336)
);
OA22X1TS U3418 ( .A0(n2776), .A1(FPADDSUB_intDX_EWSW[22]), .B0(n2890), .B1(
FPADDSUB_intDX_EWSW[23]), .Y(n2367) );
NAND2BXLTS U3419 ( .AN(FPADDSUB_intDX_EWSW[21]), .B(FPADDSUB_intDY_EWSW[21]),
.Y(n2334) );
OAI21X1TS U3420 ( .A0(FPADDSUB_intDX_EWSW[18]), .A1(n2869), .B0(n2340), .Y(
n2344) );
NAND3BXLTS U3421 ( .AN(n2338), .B(n2336), .C(n2335), .Y(n2355) );
OAI21XLTS U3422 ( .A0(FPADDSUB_intDX_EWSW[21]), .A1(n2857), .B0(
FPADDSUB_intDX_EWSW[20]), .Y(n2337) );
OAI2BB2XLTS U3423 ( .B0(FPADDSUB_intDY_EWSW[20]), .B1(n2337), .A0N(
FPADDSUB_intDX_EWSW[21]), .A1N(n2857), .Y(n2348) );
AOI22X1TS U3424 ( .A0(FPADDSUB_intDX_EWSW[17]), .A1(n2866), .B0(
FPADDSUB_intDX_EWSW[16]), .B1(n2339), .Y(n2342) );
AOI32X1TS U3425 ( .A0(n2869), .A1(n2340), .A2(FPADDSUB_intDX_EWSW[18]), .B0(
FPADDSUB_intDX_EWSW[19]), .B1(n2773), .Y(n2341) );
OAI32X1TS U3426 ( .A0(n2344), .A1(n2343), .A2(n2342), .B0(n2341), .B1(n2343),
.Y(n2347) );
OAI2BB2XLTS U3427 ( .B0(FPADDSUB_intDY_EWSW[22]), .B1(n2345), .A0N(
FPADDSUB_intDX_EWSW[23]), .A1N(n2890), .Y(n2346) );
AOI211X1TS U3428 ( .A0(n2367), .A1(n2348), .B0(n2347), .C0(n2346), .Y(n2354)
);
NAND4BBX1TS U3429 ( .AN(n2352), .BN(n2351), .C(n2350), .D(n2349), .Y(n2353)
);
AOI32X1TS U3430 ( .A0(n2356), .A1(n2355), .A2(n2354), .B0(n2353), .B1(n2356),
.Y(n2357) );
NAND2X1TS U3431 ( .A(FPADDSUB_intDY_EWSW[18]), .B(n2825), .Y(n2358) );
AOI22X1TS U3432 ( .A0(n2829), .A1(FPADDSUB_intDX_EWSW[28]), .B0(n2822), .B1(
FPADDSUB_intDY_EWSW[6]), .Y(n2359) );
OAI221XLTS U3433 ( .A0(n2829), .A1(FPADDSUB_intDX_EWSW[28]), .B0(n2822),
.B1(FPADDSUB_intDY_EWSW[6]), .C0(n2359), .Y(n2364) );
AOI22X1TS U3434 ( .A0(n2820), .A1(FPADDSUB_intDY_EWSW[1]), .B0(n2770), .B1(
FPADDSUB_intDY_EWSW[0]), .Y(n2360) );
AOI22X1TS U3435 ( .A0(n952), .A1(FPADDSUB_intDY_EWSW[26]), .B0(n2827), .B1(
FPADDSUB_intDY_EWSW[3]), .Y(n2361) );
OAI221XLTS U3436 ( .A0(n952), .A1(FPADDSUB_intDY_EWSW[26]), .B0(n2827), .B1(
FPADDSUB_intDY_EWSW[3]), .C0(n2361), .Y(n2362) );
NOR4X1TS U3437 ( .A(n2365), .B(n2364), .C(n2363), .D(n2362), .Y(n2392) );
AOI22X1TS U3438 ( .A0(n2836), .A1(FPADDSUB_intDY_EWSW[5]), .B0(n2769), .B1(
FPADDSUB_intDY_EWSW[4]), .Y(n2366) );
OAI221XLTS U3439 ( .A0(n2839), .A1(FPADDSUB_intDY_EWSW[23]), .B0(n911), .B1(
FPADDSUB_intDY_EWSW[22]), .C0(n2367), .Y(n2372) );
AOI22X1TS U3440 ( .A0(n2821), .A1(FPADDSUB_intDY_EWSW[17]), .B0(n2824), .B1(
FPADDSUB_intDY_EWSW[16]), .Y(n2368) );
AOI22X1TS U3441 ( .A0(n2768), .A1(FPADDSUB_intDY_EWSW[21]), .B0(n2823), .B1(
FPADDSUB_intDY_EWSW[8]), .Y(n2369) );
OAI221XLTS U3442 ( .A0(n2768), .A1(FPADDSUB_intDY_EWSW[21]), .B0(n2823),
.B1(FPADDSUB_intDY_EWSW[8]), .C0(n2369), .Y(n2370) );
NOR4X1TS U3443 ( .A(n2373), .B(n2372), .C(n2371), .D(n2370), .Y(n2391) );
NAND2X1TS U3444 ( .A(FPADDSUB_intDY_EWSW[20]), .B(n2826), .Y(n2374) );
INVX2TS U3445 ( .A(n965), .Y(n2540) );
AOI22X1TS U3446 ( .A0(n951), .A1(FPADDSUB_intDY_EWSW[25]), .B0(n2540), .B1(
FPADDSUB_intDY_EWSW[24]), .Y(n2375) );
OAI221XLTS U3447 ( .A0(n951), .A1(FPADDSUB_intDY_EWSW[25]), .B0(n2540), .B1(
FPADDSUB_intDY_EWSW[24]), .C0(n2375), .Y(n2388) );
OAI22X1TS U3448 ( .A0(n949), .A1(FPADDSUB_intDY_EWSW[19]), .B0(n928), .B1(
FPADDSUB_intDY_EWSW[27]), .Y(n2376) );
AOI221X1TS U3449 ( .A0(n949), .A1(FPADDSUB_intDY_EWSW[19]), .B0(
FPADDSUB_intDY_EWSW[27]), .B1(n928), .C0(n2376), .Y(n2377) );
OAI221XLTS U3450 ( .A0(FPADDSUB_intDX_EWSW[14]), .A1(n2771), .B0(n2840),
.B1(FPADDSUB_intDY_EWSW[14]), .C0(n2377), .Y(n2387) );
OAI22X1TS U3451 ( .A0(n2818), .A1(FPADDSUB_intDX_EWSW[12]), .B0(n2764), .B1(
FPADDSUB_intDY_EWSW[2]), .Y(n2378) );
AOI221X1TS U3452 ( .A0(n2818), .A1(FPADDSUB_intDX_EWSW[12]), .B0(
FPADDSUB_intDY_EWSW[2]), .B1(n2764), .C0(n2378), .Y(n2385) );
OAI22X1TS U3453 ( .A0(n2767), .A1(FPADDSUB_intDY_EWSW[7]), .B0(n2765), .B1(
FPADDSUB_intDY_EWSW[9]), .Y(n2379) );
AOI221X1TS U3454 ( .A0(n2767), .A1(FPADDSUB_intDY_EWSW[7]), .B0(
FPADDSUB_intDY_EWSW[9]), .B1(n2765), .C0(n2379), .Y(n2384) );
OAI22X1TS U3455 ( .A0(n2817), .A1(FPADDSUB_intDY_EWSW[10]), .B0(n2816), .B1(
FPADDSUB_intDY_EWSW[11]), .Y(n2380) );
AOI221X1TS U3456 ( .A0(n2817), .A1(FPADDSUB_intDY_EWSW[10]), .B0(
FPADDSUB_intDY_EWSW[11]), .B1(n2816), .C0(n2380), .Y(n2383) );
OAI22X1TS U3457 ( .A0(n2819), .A1(FPADDSUB_intDY_EWSW[15]), .B0(n2766), .B1(
FPADDSUB_intDY_EWSW[13]), .Y(n2381) );
AOI221X1TS U3458 ( .A0(n2819), .A1(FPADDSUB_intDY_EWSW[15]), .B0(
FPADDSUB_intDY_EWSW[13]), .B1(n2766), .C0(n2381), .Y(n2382) );
NAND4XLTS U3459 ( .A(n2385), .B(n2384), .C(n2383), .D(n2382), .Y(n2386) );
NOR4X1TS U3460 ( .A(n2389), .B(n2388), .C(n2386), .D(n2387), .Y(n2390) );
AOI31XLTS U3461 ( .A0(n2392), .A1(n2391), .A2(n2390), .B0(n2357), .Y(n2393)
);
AOI2BB2XLTS U3462 ( .B0(n2539), .B1(n2956), .A0N(FPADDSUB_intDX_EWSW[31]),
.A1N(n2393), .Y(n2957) );
AOI22X1TS U3465 ( .A0(FPMULT_FSM_selector_C), .A1(FPMULT_Add_result[23]),
.B0(FPMULT_P_Sgf[46]), .B1(n2837), .Y(n2394) );
AOI22X1TS U3466 ( .A0(n2748), .A1(FPMULT_FS_Module_state_reg[0]), .B0(n2399),
.B1(n2394), .Y(n2990) );
AOI32X1TS U3467 ( .A0(n996), .A1(n2748), .A2(n2774), .B0(
FPMULT_FS_Module_state_reg[0]), .B1(FPMULT_FS_Module_state_reg[2]),
.Y(n2397) );
NOR2XLTS U3468 ( .A(n2397), .B(n2837), .Y(n2395) );
AOI22X1TS U3469 ( .A0(n2446), .A1(FPMULT_Add_result[22]), .B0(n2445), .B1(
FPMULT_Add_result[23]), .Y(n2402) );
NOR2XLTS U3470 ( .A(FPMULT_FSM_selector_C), .B(n2397), .Y(n2398) );
AOI22X1TS U3471 ( .A0(n2448), .A1(FPMULT_P_Sgf[45]), .B0(n2447), .B1(
FPMULT_P_Sgf[46]), .Y(n2401) );
NAND2X1TS U3472 ( .A(n2402), .B(n2401), .Y(n2989) );
AOI22X1TS U3473 ( .A0(n2446), .A1(FPMULT_Add_result[21]), .B0(
FPMULT_Add_result[22]), .B1(n2445), .Y(n2404) );
AOI22X1TS U3474 ( .A0(n2448), .A1(FPMULT_P_Sgf[44]), .B0(FPMULT_P_Sgf[45]),
.B1(n2447), .Y(n2403) );
NAND2X1TS U3475 ( .A(n2404), .B(n2403), .Y(n2988) );
AOI22X1TS U3476 ( .A0(n2446), .A1(FPMULT_Add_result[20]), .B0(n2445), .B1(
FPMULT_Add_result[21]), .Y(n2406) );
AOI22X1TS U3477 ( .A0(n2448), .A1(FPMULT_P_Sgf[43]), .B0(n2447), .B1(
FPMULT_P_Sgf[44]), .Y(n2405) );
NAND2X1TS U3478 ( .A(n2406), .B(n2405), .Y(n2987) );
AOI22X1TS U3479 ( .A0(n2446), .A1(FPMULT_Add_result[19]), .B0(n2445), .B1(
FPMULT_Add_result[20]), .Y(n2408) );
AOI22X1TS U3480 ( .A0(n2448), .A1(FPMULT_P_Sgf[42]), .B0(n2447), .B1(
FPMULT_P_Sgf[43]), .Y(n2407) );
NAND2X1TS U3481 ( .A(n2408), .B(n2407), .Y(n2986) );
AOI22X1TS U3482 ( .A0(n2446), .A1(FPMULT_Add_result[18]), .B0(n2445), .B1(
FPMULT_Add_result[19]), .Y(n2410) );
AOI22X1TS U3483 ( .A0(n2448), .A1(FPMULT_P_Sgf[41]), .B0(n2447), .B1(
FPMULT_P_Sgf[42]), .Y(n2409) );
NAND2X1TS U3484 ( .A(n2410), .B(n2409), .Y(n2985) );
AOI22X1TS U3485 ( .A0(n2446), .A1(FPMULT_Add_result[17]), .B0(n2445), .B1(
FPMULT_Add_result[18]), .Y(n2412) );
AOI22X1TS U3486 ( .A0(n2448), .A1(FPMULT_P_Sgf[40]), .B0(n2447), .B1(
FPMULT_P_Sgf[41]), .Y(n2411) );
NAND2X1TS U3487 ( .A(n2412), .B(n2411), .Y(n2984) );
AOI22X1TS U3488 ( .A0(n2446), .A1(FPMULT_Add_result[16]), .B0(n2445), .B1(
FPMULT_Add_result[17]), .Y(n2414) );
AOI22X1TS U3489 ( .A0(n2448), .A1(FPMULT_P_Sgf[39]), .B0(n2447), .B1(
FPMULT_P_Sgf[40]), .Y(n2413) );
NAND2X1TS U3490 ( .A(n2414), .B(n2413), .Y(n2983) );
AOI22X1TS U3491 ( .A0(n2446), .A1(FPMULT_Add_result[15]), .B0(n2445), .B1(
FPMULT_Add_result[16]), .Y(n2416) );
AOI22X1TS U3492 ( .A0(n2448), .A1(FPMULT_P_Sgf[38]), .B0(n2447), .B1(
FPMULT_P_Sgf[39]), .Y(n2415) );
NAND2X1TS U3493 ( .A(n2416), .B(n2415), .Y(n2982) );
AOI22X1TS U3494 ( .A0(n2446), .A1(FPMULT_Add_result[14]), .B0(n2445), .B1(
FPMULT_Add_result[15]), .Y(n2418) );
AOI22X1TS U3495 ( .A0(n2448), .A1(FPMULT_P_Sgf[37]), .B0(n2447), .B1(
FPMULT_P_Sgf[38]), .Y(n2417) );
NAND2X1TS U3496 ( .A(n2418), .B(n2417), .Y(n2981) );
AOI22X1TS U3497 ( .A0(n2446), .A1(FPMULT_Add_result[13]), .B0(n2445), .B1(
FPMULT_Add_result[14]), .Y(n2420) );
AOI22X1TS U3498 ( .A0(n2448), .A1(FPMULT_P_Sgf[36]), .B0(n2447), .B1(
FPMULT_P_Sgf[37]), .Y(n2419) );
NAND2X1TS U3499 ( .A(n2420), .B(n2419), .Y(n2980) );
AOI22X1TS U3500 ( .A0(n2446), .A1(FPMULT_Add_result[12]), .B0(n2445), .B1(
FPMULT_Add_result[13]), .Y(n2422) );
AOI22X1TS U3501 ( .A0(n2448), .A1(FPMULT_P_Sgf[35]), .B0(n2447), .B1(
FPMULT_P_Sgf[36]), .Y(n2421) );
NAND2X1TS U3502 ( .A(n2422), .B(n2421), .Y(n2979) );
AOI22X1TS U3503 ( .A0(n2446), .A1(FPMULT_Add_result[11]), .B0(n2445), .B1(
FPMULT_Add_result[12]), .Y(n2424) );
AOI22X1TS U3504 ( .A0(n2448), .A1(FPMULT_P_Sgf[34]), .B0(n2447), .B1(
FPMULT_P_Sgf[35]), .Y(n2423) );
NAND2X1TS U3505 ( .A(n2424), .B(n2423), .Y(n2978) );
AOI22X1TS U3506 ( .A0(n2446), .A1(FPMULT_Add_result[10]), .B0(n2445), .B1(
FPMULT_Add_result[11]), .Y(n2426) );
AOI22X1TS U3507 ( .A0(n2448), .A1(FPMULT_P_Sgf[33]), .B0(n2447), .B1(
FPMULT_P_Sgf[34]), .Y(n2425) );
NAND2X1TS U3508 ( .A(n2426), .B(n2425), .Y(n2977) );
AOI22X1TS U3509 ( .A0(n2446), .A1(FPMULT_Add_result[9]), .B0(n2445), .B1(
FPMULT_Add_result[10]), .Y(n2428) );
AOI22X1TS U3510 ( .A0(n2448), .A1(FPMULT_P_Sgf[32]), .B0(n2447), .B1(
FPMULT_P_Sgf[33]), .Y(n2427) );
NAND2X1TS U3511 ( .A(n2428), .B(n2427), .Y(n2976) );
AOI22X1TS U3512 ( .A0(n2446), .A1(FPMULT_Add_result[8]), .B0(n2445), .B1(
FPMULT_Add_result[9]), .Y(n2430) );
AOI22X1TS U3513 ( .A0(n2448), .A1(FPMULT_P_Sgf[31]), .B0(n2447), .B1(
FPMULT_P_Sgf[32]), .Y(n2429) );
NAND2X1TS U3514 ( .A(n2430), .B(n2429), .Y(n2975) );
AOI22X1TS U3515 ( .A0(n2446), .A1(FPMULT_Add_result[7]), .B0(n2445), .B1(
FPMULT_Add_result[8]), .Y(n2432) );
AOI22X1TS U3516 ( .A0(n2448), .A1(FPMULT_P_Sgf[30]), .B0(n2447), .B1(
FPMULT_P_Sgf[31]), .Y(n2431) );
NAND2X1TS U3517 ( .A(n2432), .B(n2431), .Y(n2974) );
AOI22X1TS U3518 ( .A0(n2446), .A1(FPMULT_Add_result[6]), .B0(n2445), .B1(
FPMULT_Add_result[7]), .Y(n2434) );
AOI22X1TS U3519 ( .A0(n2448), .A1(FPMULT_P_Sgf[29]), .B0(n2447), .B1(
FPMULT_P_Sgf[30]), .Y(n2433) );
NAND2X1TS U3520 ( .A(n2434), .B(n2433), .Y(n2973) );
AOI22X1TS U3521 ( .A0(n2446), .A1(FPMULT_Add_result[5]), .B0(n2445), .B1(
FPMULT_Add_result[6]), .Y(n2436) );
AOI22X1TS U3522 ( .A0(n2448), .A1(FPMULT_P_Sgf[28]), .B0(n2447), .B1(
FPMULT_P_Sgf[29]), .Y(n2435) );
NAND2X1TS U3523 ( .A(n2436), .B(n2435), .Y(n2972) );
AOI22X1TS U3524 ( .A0(n2446), .A1(FPMULT_Add_result[4]), .B0(n2445), .B1(
FPMULT_Add_result[5]), .Y(n2438) );
AOI22X1TS U3525 ( .A0(n2448), .A1(FPMULT_P_Sgf[27]), .B0(n2447), .B1(
FPMULT_P_Sgf[28]), .Y(n2437) );
NAND2X1TS U3526 ( .A(n2438), .B(n2437), .Y(n2971) );
AOI22X1TS U3527 ( .A0(n2446), .A1(FPMULT_Add_result[3]), .B0(n2445), .B1(
FPMULT_Add_result[4]), .Y(n2440) );
AOI22X1TS U3528 ( .A0(n2448), .A1(FPMULT_P_Sgf[26]), .B0(n2447), .B1(
FPMULT_P_Sgf[27]), .Y(n2439) );
NAND2X1TS U3529 ( .A(n2440), .B(n2439), .Y(n2970) );
AOI22X1TS U3530 ( .A0(n2446), .A1(FPMULT_Add_result[2]), .B0(n2445), .B1(
FPMULT_Add_result[3]), .Y(n2442) );
AOI22X1TS U3531 ( .A0(n2448), .A1(n959), .B0(n2447), .B1(FPMULT_P_Sgf[26]),
.Y(n2441) );
NAND2X1TS U3532 ( .A(n2442), .B(n2441), .Y(n2969) );
AOI22X1TS U3533 ( .A0(n2446), .A1(FPMULT_Add_result[1]), .B0(n2445), .B1(
FPMULT_Add_result[2]), .Y(n2444) );
AOI22X1TS U3534 ( .A0(n2448), .A1(FPMULT_P_Sgf[24]), .B0(n2447), .B1(n959),
.Y(n2443) );
NAND2X1TS U3535 ( .A(n2444), .B(n2443), .Y(n2968) );
AOI22X1TS U3536 ( .A0(n2446), .A1(FPMULT_Add_result[0]), .B0(n2445), .B1(
FPMULT_Add_result[1]), .Y(n2450) );
AOI22X1TS U3537 ( .A0(n2448), .A1(FPMULT_P_Sgf[23]), .B0(n2447), .B1(
FPMULT_P_Sgf[24]), .Y(n2449) );
NAND2X1TS U3538 ( .A(n2450), .B(n2449), .Y(n2967) );
AOI22X1TS U3539 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n2451), .B1(n2838),
.Y(n2966) );
XNOR2X1TS U3540 ( .A(Data_2[31]), .B(Data_1[31]), .Y(n2882) );
INVX2TS U3541 ( .A(n2452), .Y(n2602) );
AOI2BB1XLTS U3542 ( .A0N(n2859), .A1N(underflow_flag_mult), .B0(n2602), .Y(
FPMULT_final_result_ieee_Module_Sign_S_mux) );
AOI32X1TS U3543 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(n2453), .A2(n2800),
.B0(FPSENCOS_cont_iter_out[2]), .B1(n2453), .Y(
FPSENCOS_data_out_LUT[4]) );
OAI22X1TS U3544 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(n2665), .B0(
FPSENCOS_cont_iter_out[2]), .B1(n2666), .Y(FPSENCOS_data_out_LUT[25])
);
NOR4X1TS U3545 ( .A(Data_1[12]), .B(Data_1[11]), .C(Data_1[10]), .D(
Data_1[9]), .Y(n2460) );
NOR4X1TS U3546 ( .A(Data_1[8]), .B(Data_1[7]), .C(Data_1[6]), .D(Data_1[0]),
.Y(n2459) );
NOR4X1TS U3547 ( .A(Data_1[3]), .B(Data_1[16]), .C(Data_1[1]), .D(Data_1[22]), .Y(n2457) );
NOR3XLTS U3548 ( .A(Data_1[2]), .B(Data_1[5]), .C(Data_1[4]), .Y(n2456) );
NOR4X1TS U3549 ( .A(Data_1[21]), .B(Data_1[19]), .C(Data_1[14]), .D(
Data_1[20]), .Y(n2455) );
NOR4X1TS U3550 ( .A(Data_1[13]), .B(Data_1[15]), .C(Data_1[17]), .D(
Data_1[18]), .Y(n2454) );
AND4X1TS U3551 ( .A(n2457), .B(n2456), .C(n2455), .D(n2454), .Y(n2458) );
NAND3XLTS U3552 ( .A(n2460), .B(n2459), .C(n2458), .Y(n2879) );
NAND4XLTS U3553 ( .A(dataA[30]), .B(dataA[27]), .C(dataA[28]), .D(dataA[26]),
.Y(n2462) );
NAND4XLTS U3554 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(n958), .Y(
n2461) );
NOR3X1TS U3555 ( .A(n2949), .B(n2462), .C(n2461), .Y(n2467) );
NOR4X1TS U3556 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[28]), .D(dataB[23]),
.Y(n2464) );
NOR3XLTS U3557 ( .A(dataB[26]), .B(dataB[29]), .C(dataB[25]), .Y(n2463) );
NAND4XLTS U3558 ( .A(n2467), .B(operation_reg[1]), .C(n2464), .D(n2463), .Y(
n2465) );
NOR3XLTS U3559 ( .A(operation_reg[0]), .B(dataB[31]), .C(n2465), .Y(n2466)
);
OAI211XLTS U3560 ( .A0(dataB[27]), .A1(n2466), .B0(n2948), .C0(n2947), .Y(
n2477) );
NOR4X1TS U3561 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[28]), .D(dataA[26]),
.Y(n2470) );
NOR4BX1TS U3562 ( .AN(operation_reg[1]), .B(dataA[31]), .C(n958), .D(
dataA[25]), .Y(n2469) );
NOR4X1TS U3563 ( .A(n2949), .B(dataA[30]), .C(operation_reg[0]), .D(
dataA[27]), .Y(n2468) );
NOR2BX1TS U3564 ( .AN(n2467), .B(operation_reg[1]), .Y(n2475) );
AOI31XLTS U3565 ( .A0(n2470), .A1(n2469), .A2(n2468), .B0(n2475), .Y(n2473)
);
NAND3XLTS U3566 ( .A(dataB[28]), .B(dataB[23]), .C(dataB[25]), .Y(n2472) );
NAND4XLTS U3567 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[26]), .D(dataB[29]),
.Y(n2471) );
OAI31X1TS U3568 ( .A0(n2473), .A1(n2472), .A2(n2471), .B0(dataB[27]), .Y(
n2474) );
NAND4XLTS U3569 ( .A(n2952), .B(n2951), .C(n2950), .D(n2474), .Y(n2476) );
OAI2BB2XLTS U3570 ( .B0(n2477), .B1(n2476), .A0N(n2475), .A1N(
operation_reg[0]), .Y(NaN_reg) );
NAND2X1TS U3571 ( .A(FPADDSUB_N59), .B(n2490), .Y(n2478) );
XNOR2X1TS U3572 ( .A(n2478), .B(FPADDSUB_N60), .Y(FPADDSUB_Raw_mant_SGF[1])
);
OAI21XLTS U3573 ( .A0(FPADDSUB_DMP_SFG[0]), .A1(FPADDSUB_DmP_mant_SFG_SWR[2]), .B0(n2479), .Y(n2482) );
NAND2X1TS U3574 ( .A(n2480), .B(n2490), .Y(n2481) );
XOR2XLTS U3575 ( .A(n2482), .B(n2481), .Y(FPADDSUB_Raw_mant_SGF[2]) );
AOI22X1TS U3576 ( .A0(n2490), .A1(n2484), .B0(n2483), .B1(n2922), .Y(n2487)
);
OAI21XLTS U3577 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[9]), .A1(n2754), .B0(n2485),
.Y(n2486) );
XOR2XLTS U3578 ( .A(n2487), .B(n2486), .Y(FPADDSUB_Raw_mant_SGF[9]) );
AOI22X1TS U3579 ( .A0(n2490), .A1(n2489), .B0(n2488), .B1(n2922), .Y(n2493)
);
OAI21XLTS U3580 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[11]), .A1(n2755), .B0(n2491),
.Y(n2492) );
XOR2XLTS U3581 ( .A(n2493), .B(n2492), .Y(FPADDSUB_Raw_mant_SGF[11]) );
AOI22X1TS U3582 ( .A0(n995), .A1(n2495), .B0(n2494), .B1(n2922), .Y(n2498)
);
OAI21XLTS U3583 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[13]), .A1(n2756), .B0(n2496),
.Y(n2497) );
XOR2XLTS U3584 ( .A(n2498), .B(n2497), .Y(FPADDSUB_Raw_mant_SGF[13]) );
AOI22X1TS U3585 ( .A0(n995), .A1(n2500), .B0(n2499), .B1(n2525), .Y(n2503)
);
OAI21XLTS U3586 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[15]), .A1(n2757), .B0(n2501),
.Y(n2502) );
XOR2XLTS U3587 ( .A(n2503), .B(n2502), .Y(FPADDSUB_Raw_mant_SGF[15]) );
AOI22X1TS U3588 ( .A0(n995), .A1(n2505), .B0(n2504), .B1(n2922), .Y(n2508)
);
OAI21XLTS U3589 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[17]), .A1(n2758), .B0(n2506),
.Y(n2507) );
XOR2XLTS U3590 ( .A(n2508), .B(n2507), .Y(FPADDSUB_Raw_mant_SGF[17]) );
AOI22X1TS U3591 ( .A0(n995), .A1(n2510), .B0(n2509), .B1(n2922), .Y(n2513)
);
XOR2XLTS U3592 ( .A(n2513), .B(n2512), .Y(FPADDSUB_Raw_mant_SGF[19]) );
AOI22X1TS U3593 ( .A0(n995), .A1(n2515), .B0(n2514), .B1(n2922), .Y(n2518)
);
OAI21XLTS U3594 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[21]), .A1(n2795), .B0(n2516),
.Y(n2517) );
XOR2XLTS U3595 ( .A(n2518), .B(n2517), .Y(FPADDSUB_Raw_mant_SGF[21]) );
AOI22X1TS U3596 ( .A0(n995), .A1(n2520), .B0(n2519), .B1(n2922), .Y(n2523)
);
OAI21XLTS U3597 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[23]), .A1(n2813), .B0(n2521),
.Y(n2522) );
XOR2XLTS U3598 ( .A(n2523), .B(n2522), .Y(FPADDSUB_Raw_mant_SGF[23]) );
AOI21X1TS U3599 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[24]), .A1(n2843), .B0(n2524),
.Y(n2529) );
AOI22X1TS U3600 ( .A0(n995), .A1(n2527), .B0(n2526), .B1(n2525), .Y(n2528)
);
XOR2XLTS U3601 ( .A(n2529), .B(n2528), .Y(FPADDSUB_Raw_mant_SGF[24]) );
NAND2X1TS U3602 ( .A(FPSENCOS_d_ff1_operation_out), .B(n963), .Y(n2532) );
OAI21XLTS U3603 ( .A0(FPSENCOS_d_ff1_operation_out), .A1(n963), .B0(n2532),
.Y(n2530) );
XNOR2X1TS U3604 ( .A(n994), .B(n2530), .Y(n2531) );
BUFX3TS U3605 ( .A(n2531), .Y(n2557) );
AOI22X1TS U3606 ( .A0(n2556), .A1(FPSENCOS_d_ff_Yn[31]), .B0(
FPSENCOS_d_ff_Xn[31]), .B1(n2557), .Y(n2534) );
XNOR2X1TS U3607 ( .A(n2534), .B(n2533), .Y(FPSENCOS_fmtted_Result_31_) );
AOI22X1TS U3608 ( .A0(n2542), .A1(n2873), .B0(n2770), .B1(n2539), .Y(
FPADDSUB_DmP_INIT_EWSW[0]) );
AOI22X1TS U3609 ( .A0(n2542), .A1(n2870), .B0(n2820), .B1(n2539), .Y(
FPADDSUB_DmP_INIT_EWSW[1]) );
AOI22X1TS U3610 ( .A0(n2537), .A1(n2853), .B0(n2764), .B1(n2539), .Y(
FPADDSUB_DmP_INIT_EWSW[2]) );
BUFX4TS U3611 ( .A(n2539), .Y(n2541) );
AOI22X1TS U3612 ( .A0(n2542), .A1(n2872), .B0(n2827), .B1(n2541), .Y(
FPADDSUB_DmP_INIT_EWSW[3]) );
BUFX3TS U3613 ( .A(n2539), .Y(n2535) );
AOI22X1TS U3614 ( .A0(n2542), .A1(n2851), .B0(n2769), .B1(n2535), .Y(
FPADDSUB_DmP_INIT_EWSW[4]) );
AOI22X1TS U3615 ( .A0(n2542), .A1(n2846), .B0(n2836), .B1(n2535), .Y(
FPADDSUB_DmP_INIT_EWSW[5]) );
BUFX3TS U3616 ( .A(n2539), .Y(n2536) );
AOI22X1TS U3617 ( .A0(n2537), .A1(n2849), .B0(n2822), .B1(n2536), .Y(
FPADDSUB_DmP_INIT_EWSW[6]) );
AOI22X1TS U3618 ( .A0(n2542), .A1(n2845), .B0(n2767), .B1(n2536), .Y(
FPADDSUB_DmP_INIT_EWSW[7]) );
AOI22X1TS U3619 ( .A0(n2542), .A1(n2868), .B0(n2823), .B1(n2541), .Y(
FPADDSUB_DmP_INIT_EWSW[8]) );
AOI22X1TS U3620 ( .A0(n2538), .A1(n2855), .B0(n2765), .B1(n2541), .Y(
FPADDSUB_DmP_INIT_EWSW[9]) );
AOI22X1TS U3621 ( .A0(n2537), .A1(n2848), .B0(n2817), .B1(n2535), .Y(
FPADDSUB_DmP_INIT_EWSW[10]) );
AOI22X1TS U3622 ( .A0(n2542), .A1(n2864), .B0(n2816), .B1(n2536), .Y(
FPADDSUB_DmP_INIT_EWSW[11]) );
AOI22X1TS U3623 ( .A0(n2538), .A1(n2818), .B0(n2847), .B1(n2541), .Y(
FPADDSUB_DmP_INIT_EWSW[12]) );
AOI22X1TS U3624 ( .A0(n2542), .A1(n2852), .B0(n2766), .B1(n2535), .Y(
FPADDSUB_DmP_INIT_EWSW[13]) );
AOI22X1TS U3625 ( .A0(n2537), .A1(n2771), .B0(n2840), .B1(n2535), .Y(
FPADDSUB_DmP_INIT_EWSW[14]) );
AOI22X1TS U3626 ( .A0(n2542), .A1(n2865), .B0(n2819), .B1(n2535), .Y(
FPADDSUB_DmP_INIT_EWSW[15]) );
AOI22X1TS U3627 ( .A0(n2538), .A1(n2850), .B0(n2824), .B1(n2535), .Y(
FPADDSUB_DmP_INIT_EWSW[16]) );
AOI22X1TS U3628 ( .A0(n2537), .A1(n2866), .B0(n2821), .B1(n2535), .Y(
FPADDSUB_DmP_INIT_EWSW[17]) );
AOI22X1TS U3629 ( .A0(n2538), .A1(n2869), .B0(n2825), .B1(n2535), .Y(
FPADDSUB_DmP_INIT_EWSW[18]) );
AOI22X1TS U3630 ( .A0(n2537), .A1(n2773), .B0(n949), .B1(n2535), .Y(
FPADDSUB_DmP_INIT_EWSW[19]) );
AOI22X1TS U3631 ( .A0(n2538), .A1(n2858), .B0(n2826), .B1(n2535), .Y(
FPADDSUB_DmP_INIT_EWSW[20]) );
AOI22X1TS U3632 ( .A0(n2537), .A1(n2857), .B0(n2768), .B1(n2535), .Y(
FPADDSUB_DmP_INIT_EWSW[21]) );
AOI22X1TS U3633 ( .A0(n2538), .A1(n2776), .B0(n911), .B1(n2535), .Y(
FPADDSUB_DmP_INIT_EWSW[22]) );
AOI22X1TS U3634 ( .A0(n2537), .A1(n2890), .B0(n2839), .B1(n2536), .Y(
FPADDSUB_DmP_INIT_EWSW[23]) );
AOI22X1TS U3635 ( .A0(n2538), .A1(n2854), .B0(n2540), .B1(n2536), .Y(
FPADDSUB_DmP_INIT_EWSW[24]) );
AOI22X1TS U3636 ( .A0(n2537), .A1(n2867), .B0(n951), .B1(n2536), .Y(
FPADDSUB_DmP_INIT_EWSW[25]) );
AOI22X1TS U3637 ( .A0(n2538), .A1(n2871), .B0(n952), .B1(n2536), .Y(
FPADDSUB_DmP_INIT_EWSW[26]) );
AOI22X1TS U3638 ( .A0(n2537), .A1(n2856), .B0(n928), .B1(n2536), .Y(
FPADDSUB_DmP_INIT_EWSW[27]) );
AOI22X1TS U3639 ( .A0(n2538), .A1(n2770), .B0(n2873), .B1(n2536), .Y(
FPADDSUB_DMP_INIT_EWSW[0]) );
AOI22X1TS U3640 ( .A0(n2538), .A1(n2820), .B0(n2870), .B1(n2536), .Y(
FPADDSUB_DMP_INIT_EWSW[1]) );
AOI22X1TS U3641 ( .A0(n2538), .A1(n2764), .B0(n2853), .B1(n2536), .Y(
FPADDSUB_DMP_INIT_EWSW[2]) );
AOI22X1TS U3642 ( .A0(n2537), .A1(n2827), .B0(n2872), .B1(n2536), .Y(
FPADDSUB_DMP_INIT_EWSW[3]) );
AOI22X1TS U3643 ( .A0(n2537), .A1(n2769), .B0(n2851), .B1(n2536), .Y(
FPADDSUB_DMP_INIT_EWSW[4]) );
AOI22X1TS U3644 ( .A0(n2538), .A1(n2836), .B0(n2846), .B1(n2541), .Y(
FPADDSUB_DMP_INIT_EWSW[5]) );
AOI22X1TS U3645 ( .A0(n2537), .A1(n2822), .B0(n2849), .B1(n2541), .Y(
FPADDSUB_DMP_INIT_EWSW[6]) );
AOI22X1TS U3646 ( .A0(n2538), .A1(n2767), .B0(n2845), .B1(n2541), .Y(
FPADDSUB_DMP_INIT_EWSW[7]) );
AOI22X1TS U3647 ( .A0(n2538), .A1(n2823), .B0(n2868), .B1(n2541), .Y(
FPADDSUB_DMP_INIT_EWSW[8]) );
AOI22X1TS U3648 ( .A0(n2537), .A1(n2765), .B0(n2855), .B1(n2541), .Y(
FPADDSUB_DMP_INIT_EWSW[9]) );
AOI22X1TS U3649 ( .A0(n2537), .A1(n2817), .B0(n2848), .B1(n2541), .Y(
FPADDSUB_DMP_INIT_EWSW[10]) );
AOI22X1TS U3650 ( .A0(n2538), .A1(n2816), .B0(n2864), .B1(n2541), .Y(
FPADDSUB_DMP_INIT_EWSW[11]) );
AOI22X1TS U3651 ( .A0(n2538), .A1(n2847), .B0(n2818), .B1(n2541), .Y(
FPADDSUB_DMP_INIT_EWSW[12]) );
AOI22X1TS U3652 ( .A0(n2537), .A1(n2766), .B0(n2852), .B1(n2541), .Y(
FPADDSUB_DMP_INIT_EWSW[13]) );
AOI22X1TS U3653 ( .A0(n2542), .A1(n2840), .B0(n2771), .B1(n2541), .Y(
FPADDSUB_DMP_INIT_EWSW[14]) );
AOI22X1TS U3654 ( .A0(n2542), .A1(n2819), .B0(n2865), .B1(n2541), .Y(
FPADDSUB_DMP_INIT_EWSW[15]) );
AOI22X1TS U3655 ( .A0(n2542), .A1(n2824), .B0(n2850), .B1(n2539), .Y(
FPADDSUB_DMP_INIT_EWSW[16]) );
AOI22X1TS U3656 ( .A0(n2542), .A1(n2821), .B0(n2866), .B1(n2539), .Y(
FPADDSUB_DMP_INIT_EWSW[17]) );
AOI22X1TS U3657 ( .A0(n2542), .A1(n2825), .B0(n2869), .B1(n2539), .Y(
FPADDSUB_DMP_INIT_EWSW[18]) );
AOI22X1TS U3658 ( .A0(n2537), .A1(n949), .B0(n2773), .B1(n2539), .Y(
FPADDSUB_DMP_INIT_EWSW[19]) );
AOI22X1TS U3659 ( .A0(n2542), .A1(n2826), .B0(n2858), .B1(n2539), .Y(
FPADDSUB_DMP_INIT_EWSW[20]) );
AOI22X1TS U3660 ( .A0(n2542), .A1(n2768), .B0(n2857), .B1(n2539), .Y(
FPADDSUB_DMP_INIT_EWSW[21]) );
AOI22X1TS U3661 ( .A0(n2542), .A1(n911), .B0(n2776), .B1(n2539), .Y(
FPADDSUB_DMP_INIT_EWSW[22]) );
AOI22X1TS U3662 ( .A0(n2537), .A1(n2839), .B0(n2890), .B1(n2539), .Y(
FPADDSUB_DMP_INIT_EWSW[23]) );
AOI22X1TS U3663 ( .A0(n2542), .A1(n2540), .B0(n2854), .B1(n2539), .Y(
FPADDSUB_DMP_INIT_EWSW[24]) );
AOI22X1TS U3664 ( .A0(n2542), .A1(n951), .B0(n2867), .B1(n2541), .Y(
FPADDSUB_DMP_INIT_EWSW[25]) );
AOI22X1TS U3665 ( .A0(n2542), .A1(n952), .B0(n2871), .B1(n2541), .Y(
FPADDSUB_DMP_INIT_EWSW[26]) );
AOI22X1TS U3666 ( .A0(n2538), .A1(n928), .B0(n2856), .B1(n2541), .Y(
FPADDSUB_DMP_INIT_EWSW[27]) );
OAI2BB2XLTS U3667 ( .B0(n2537), .B1(n2829), .A0N(n2537), .A1N(
FPADDSUB_intDX_EWSW[28]), .Y(FPADDSUB_DMP_INIT_EWSW[28]) );
OAI2BB2XLTS U3668 ( .B0(n2538), .B1(n2888), .A0N(n2538), .A1N(
FPADDSUB_intDX_EWSW[29]), .Y(FPADDSUB_DMP_INIT_EWSW[29]) );
OAI22X1TS U3669 ( .A0(n2543), .A1(n2546), .B0(n2547), .B1(n2544), .Y(
FPADDSUB_Data_array_SWR[24]) );
OAI222X1TS U3670 ( .A0(n1932), .A1(n2547), .B0(n2546), .B1(n2545), .C0(n2544), .C1(n2543), .Y(FPADDSUB_Data_array_SWR[23]) );
NAND3XLTS U3671 ( .A(n967), .B(n2704), .C(n2666), .Y(n2572) );
NAND2X1TS U3672 ( .A(n2562), .B(n2572), .Y(FPSENCOS_enab_d_ff5_data_out) );
CLKAND2X2TS U3673 ( .A(n2548), .B(FPADDSUB_sftr_odat_SHT2_SWR[4]), .Y(
FPADDSUB_formatted_number_W[2]) );
CLKAND2X2TS U3674 ( .A(n2548), .B(FPADDSUB_sftr_odat_SHT2_SWR[6]), .Y(
FPADDSUB_formatted_number_W[4]) );
CLKAND2X2TS U3675 ( .A(n2548), .B(FPADDSUB_sftr_odat_SHT2_SWR[7]), .Y(
FPADDSUB_formatted_number_W[5]) );
CLKAND2X2TS U3676 ( .A(n2548), .B(FPADDSUB_sftr_odat_SHT2_SWR[18]), .Y(
FPADDSUB_formatted_number_W[16]) );
CLKAND2X2TS U3677 ( .A(n2548), .B(FPADDSUB_sftr_odat_SHT2_SWR[19]), .Y(
FPADDSUB_formatted_number_W[17]) );
CLKAND2X2TS U3678 ( .A(n2548), .B(FPADDSUB_sftr_odat_SHT2_SWR[21]), .Y(
FPADDSUB_formatted_number_W[19]) );
NOR2BX1TS U3679 ( .AN(FPMULT_Sgf_normalized_result[2]), .B(n2549), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[2]) );
NOR2BX1TS U3680 ( .AN(FPMULT_Sgf_normalized_result[4]), .B(n2549), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[4]) );
NOR2BX1TS U3681 ( .AN(FPMULT_Sgf_normalized_result[6]), .B(n2549), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[6]) );
NOR2BX1TS U3682 ( .AN(FPMULT_Sgf_normalized_result[8]), .B(n2549), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[8]) );
NOR2BX1TS U3683 ( .AN(FPMULT_Sgf_normalized_result[10]), .B(n2549), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[10]) );
NOR2BX1TS U3684 ( .AN(FPMULT_Sgf_normalized_result[12]), .B(n2549), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[12]) );
NOR2BX1TS U3685 ( .AN(FPMULT_Sgf_normalized_result[14]), .B(n2549), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[14]) );
NOR2BX1TS U3686 ( .AN(FPMULT_Sgf_normalized_result[16]), .B(n2549), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[16]) );
NOR2BX1TS U3687 ( .AN(FPMULT_Sgf_normalized_result[18]), .B(n2549), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[18]) );
NOR2BX1TS U3688 ( .AN(FPMULT_Sgf_normalized_result[20]), .B(n2549), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[20]) );
NOR2BX1TS U3689 ( .AN(FPMULT_Sgf_normalized_result[22]), .B(n2549), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[22]) );
NOR2BX1TS U3690 ( .AN(FPSENCOS_d_ff_Xn[0]), .B(n2551), .Y(
FPSENCOS_first_mux_X[0]) );
NOR2BX1TS U3691 ( .AN(FPSENCOS_d_ff_Xn[4]), .B(n2551), .Y(
FPSENCOS_first_mux_X[4]) );
NOR2BX1TS U3692 ( .AN(FPSENCOS_d_ff_Xn[8]), .B(n2551), .Y(
FPSENCOS_first_mux_X[8]) );
NOR2BX1TS U3693 ( .AN(FPSENCOS_d_ff_Xn[9]), .B(n2551), .Y(
FPSENCOS_first_mux_X[9]) );
NOR2BX1TS U3694 ( .AN(FPSENCOS_d_ff_Xn[11]), .B(n2551), .Y(
FPSENCOS_first_mux_X[11]) );
NOR2BX1TS U3695 ( .AN(FPSENCOS_d_ff_Xn[15]), .B(n2550), .Y(
FPSENCOS_first_mux_X[15]) );
NOR2BX1TS U3696 ( .AN(FPSENCOS_d_ff_Xn[18]), .B(n2551), .Y(
FPSENCOS_first_mux_X[18]) );
NOR2BX1TS U3697 ( .AN(FPSENCOS_d_ff_Xn[21]), .B(n2550), .Y(
FPSENCOS_first_mux_X[21]) );
NOR2BX1TS U3698 ( .AN(FPSENCOS_d_ff_Xn[22]), .B(n2551), .Y(
FPSENCOS_first_mux_X[22]) );
NOR2BX1TS U3699 ( .AN(FPSENCOS_d_ff_Xn[23]), .B(n2551), .Y(
FPSENCOS_first_mux_X[23]) );
NOR2BX1TS U3700 ( .AN(FPSENCOS_d_ff_Xn[30]), .B(n2551), .Y(
FPSENCOS_first_mux_X[30]) );
NOR2BX1TS U3701 ( .AN(FPSENCOS_d_ff_Xn[31]), .B(n2550), .Y(
FPSENCOS_first_mux_X[31]) );
NOR2BX1TS U3702 ( .AN(FPSENCOS_d_ff_Yn[0]), .B(n2550), .Y(
FPSENCOS_first_mux_Y[0]) );
NOR2BX1TS U3703 ( .AN(FPSENCOS_d_ff_Yn[1]), .B(n2550), .Y(
FPSENCOS_first_mux_Y[1]) );
NOR2BX1TS U3704 ( .AN(FPSENCOS_d_ff_Yn[2]), .B(n2550), .Y(
FPSENCOS_first_mux_Y[2]) );
NOR2BX1TS U3705 ( .AN(FPSENCOS_d_ff_Yn[3]), .B(n966), .Y(
FPSENCOS_first_mux_Y[3]) );
NOR2BX1TS U3706 ( .AN(FPSENCOS_d_ff_Yn[4]), .B(n2550), .Y(
FPSENCOS_first_mux_Y[4]) );
NOR2BX1TS U3707 ( .AN(FPSENCOS_d_ff_Yn[5]), .B(n966), .Y(
FPSENCOS_first_mux_Y[5]) );
NOR2BX1TS U3708 ( .AN(FPSENCOS_d_ff_Yn[6]), .B(n2551), .Y(
FPSENCOS_first_mux_Y[6]) );
NOR2BX1TS U3709 ( .AN(FPSENCOS_d_ff_Yn[7]), .B(n966), .Y(
FPSENCOS_first_mux_Y[7]) );
NOR2BX1TS U3710 ( .AN(FPSENCOS_d_ff_Yn[8]), .B(n2550), .Y(
FPSENCOS_first_mux_Y[8]) );
NOR2BX1TS U3711 ( .AN(FPSENCOS_d_ff_Yn[9]), .B(n2555), .Y(
FPSENCOS_first_mux_Y[9]) );
NOR2BX1TS U3712 ( .AN(FPSENCOS_d_ff_Yn[10]), .B(n2550), .Y(
FPSENCOS_first_mux_Y[10]) );
NOR2BX1TS U3713 ( .AN(FPSENCOS_d_ff_Yn[11]), .B(n966), .Y(
FPSENCOS_first_mux_Y[11]) );
NOR2BX1TS U3714 ( .AN(FPSENCOS_d_ff_Yn[12]), .B(n2550), .Y(
FPSENCOS_first_mux_Y[12]) );
NOR2BX1TS U3715 ( .AN(FPSENCOS_d_ff_Yn[13]), .B(n2555), .Y(
FPSENCOS_first_mux_Y[13]) );
NOR2BX1TS U3716 ( .AN(FPSENCOS_d_ff_Yn[14]), .B(n2550), .Y(
FPSENCOS_first_mux_Y[14]) );
NOR2BX1TS U3717 ( .AN(FPSENCOS_d_ff_Yn[15]), .B(n2555), .Y(
FPSENCOS_first_mux_Y[15]) );
NOR2BX1TS U3718 ( .AN(FPSENCOS_d_ff_Yn[16]), .B(n2550), .Y(
FPSENCOS_first_mux_Y[16]) );
NOR2BX1TS U3719 ( .AN(FPSENCOS_d_ff_Yn[17]), .B(n2555), .Y(
FPSENCOS_first_mux_Y[17]) );
NOR2BX1TS U3720 ( .AN(FPSENCOS_d_ff_Yn[18]), .B(n2555), .Y(
FPSENCOS_first_mux_Y[18]) );
NOR2BX1TS U3721 ( .AN(FPSENCOS_d_ff_Yn[19]), .B(n2555), .Y(
FPSENCOS_first_mux_Y[19]) );
NOR2BX1TS U3722 ( .AN(FPSENCOS_d_ff_Yn[20]), .B(n2555), .Y(
FPSENCOS_first_mux_Y[20]) );
NOR2BX1TS U3723 ( .AN(FPSENCOS_d_ff_Yn[21]), .B(n2555), .Y(
FPSENCOS_first_mux_Y[21]) );
NOR2BX1TS U3724 ( .AN(FPSENCOS_d_ff_Yn[22]), .B(n2555), .Y(
FPSENCOS_first_mux_Y[22]) );
NOR2BX1TS U3725 ( .AN(FPSENCOS_d_ff_Yn[23]), .B(n2551), .Y(
FPSENCOS_first_mux_Y[23]) );
NOR2BX1TS U3726 ( .AN(FPSENCOS_d_ff_Yn[24]), .B(n2555), .Y(
FPSENCOS_first_mux_Y[24]) );
NOR2BX1TS U3727 ( .AN(FPSENCOS_d_ff_Yn[25]), .B(n2555), .Y(
FPSENCOS_first_mux_Y[25]) );
NOR2BX1TS U3728 ( .AN(FPSENCOS_d_ff_Yn[26]), .B(n2551), .Y(
FPSENCOS_first_mux_Y[26]) );
NOR2BX1TS U3729 ( .AN(FPSENCOS_d_ff_Yn[27]), .B(n2555), .Y(
FPSENCOS_first_mux_Y[27]) );
NOR2BX1TS U3730 ( .AN(FPSENCOS_d_ff_Yn[28]), .B(n2551), .Y(
FPSENCOS_first_mux_Y[28]) );
NOR2BX1TS U3731 ( .AN(FPSENCOS_d_ff_Yn[29]), .B(n2555), .Y(
FPSENCOS_first_mux_Y[29]) );
NOR2BX1TS U3732 ( .AN(FPSENCOS_d_ff_Yn[30]), .B(n2555), .Y(
FPSENCOS_first_mux_Y[30]) );
NOR2BX1TS U3733 ( .AN(FPSENCOS_d_ff_Yn[31]), .B(n2555), .Y(
FPSENCOS_first_mux_Y[31]) );
AO22XLTS U3734 ( .A0(n966), .A1(FPSENCOS_d_ff1_Z[0]), .B0(n2553), .B1(
FPSENCOS_d_ff_Zn[0]), .Y(FPSENCOS_first_mux_Z[0]) );
AO22XLTS U3735 ( .A0(n2555), .A1(FPSENCOS_d_ff1_Z[1]), .B0(n2552), .B1(
FPSENCOS_d_ff_Zn[1]), .Y(FPSENCOS_first_mux_Z[1]) );
AO22XLTS U3736 ( .A0(n2555), .A1(FPSENCOS_d_ff1_Z[2]), .B0(n2552), .B1(
FPSENCOS_d_ff_Zn[2]), .Y(FPSENCOS_first_mux_Z[2]) );
AO22XLTS U3737 ( .A0(n2555), .A1(FPSENCOS_d_ff1_Z[3]), .B0(n2552), .B1(
FPSENCOS_d_ff_Zn[3]), .Y(FPSENCOS_first_mux_Z[3]) );
AO22XLTS U3738 ( .A0(n2554), .A1(FPSENCOS_d_ff1_Z[4]), .B0(n2552), .B1(
FPSENCOS_d_ff_Zn[4]), .Y(FPSENCOS_first_mux_Z[4]) );
AO22XLTS U3739 ( .A0(n2554), .A1(FPSENCOS_d_ff1_Z[5]), .B0(n2552), .B1(
FPSENCOS_d_ff_Zn[5]), .Y(FPSENCOS_first_mux_Z[5]) );
AO22XLTS U3740 ( .A0(n2554), .A1(FPSENCOS_d_ff1_Z[6]), .B0(n2552), .B1(
FPSENCOS_d_ff_Zn[6]), .Y(FPSENCOS_first_mux_Z[6]) );
AO22XLTS U3741 ( .A0(n2554), .A1(FPSENCOS_d_ff1_Z[7]), .B0(n2553), .B1(
FPSENCOS_d_ff_Zn[7]), .Y(FPSENCOS_first_mux_Z[7]) );
AO22XLTS U3742 ( .A0(n2554), .A1(FPSENCOS_d_ff1_Z[8]), .B0(n2553), .B1(
FPSENCOS_d_ff_Zn[8]), .Y(FPSENCOS_first_mux_Z[8]) );
AO22XLTS U3743 ( .A0(n2554), .A1(FPSENCOS_d_ff1_Z[9]), .B0(n2553), .B1(
FPSENCOS_d_ff_Zn[9]), .Y(FPSENCOS_first_mux_Z[9]) );
AO22XLTS U3744 ( .A0(n2554), .A1(FPSENCOS_d_ff1_Z[10]), .B0(n2552), .B1(
FPSENCOS_d_ff_Zn[10]), .Y(FPSENCOS_first_mux_Z[10]) );
AO22XLTS U3745 ( .A0(n966), .A1(FPSENCOS_d_ff1_Z[11]), .B0(n2553), .B1(
FPSENCOS_d_ff_Zn[11]), .Y(FPSENCOS_first_mux_Z[11]) );
AO22XLTS U3746 ( .A0(n2554), .A1(FPSENCOS_d_ff1_Z[12]), .B0(n2553), .B1(
FPSENCOS_d_ff_Zn[12]), .Y(FPSENCOS_first_mux_Z[12]) );
AO22XLTS U3747 ( .A0(n966), .A1(FPSENCOS_d_ff1_Z[13]), .B0(n2553), .B1(
FPSENCOS_d_ff_Zn[13]), .Y(FPSENCOS_first_mux_Z[13]) );
AO22XLTS U3748 ( .A0(n966), .A1(FPSENCOS_d_ff1_Z[14]), .B0(n2552), .B1(
FPSENCOS_d_ff_Zn[14]), .Y(FPSENCOS_first_mux_Z[14]) );
AO22XLTS U3749 ( .A0(n966), .A1(FPSENCOS_d_ff1_Z[15]), .B0(n2552), .B1(
FPSENCOS_d_ff_Zn[15]), .Y(FPSENCOS_first_mux_Z[15]) );
AO22XLTS U3750 ( .A0(n966), .A1(FPSENCOS_d_ff1_Z[16]), .B0(n2553), .B1(
FPSENCOS_d_ff_Zn[16]), .Y(FPSENCOS_first_mux_Z[16]) );
AO22XLTS U3751 ( .A0(n966), .A1(FPSENCOS_d_ff1_Z[17]), .B0(n2553), .B1(
FPSENCOS_d_ff_Zn[17]), .Y(FPSENCOS_first_mux_Z[17]) );
AO22XLTS U3752 ( .A0(n2555), .A1(FPSENCOS_d_ff1_Z[18]), .B0(n2553), .B1(
FPSENCOS_d_ff_Zn[18]), .Y(FPSENCOS_first_mux_Z[18]) );
AO22XLTS U3753 ( .A0(n2555), .A1(FPSENCOS_d_ff1_Z[19]), .B0(n2553), .B1(
FPSENCOS_d_ff_Zn[19]), .Y(FPSENCOS_first_mux_Z[19]) );
AO22XLTS U3754 ( .A0(n966), .A1(FPSENCOS_d_ff1_Z[20]), .B0(n2553), .B1(
FPSENCOS_d_ff_Zn[20]), .Y(FPSENCOS_first_mux_Z[20]) );
AO22XLTS U3755 ( .A0(n966), .A1(FPSENCOS_d_ff1_Z[21]), .B0(n2553), .B1(
FPSENCOS_d_ff_Zn[21]), .Y(FPSENCOS_first_mux_Z[21]) );
AO22XLTS U3756 ( .A0(n2551), .A1(FPSENCOS_d_ff1_Z[22]), .B0(n2553), .B1(
FPSENCOS_d_ff_Zn[22]), .Y(FPSENCOS_first_mux_Z[22]) );
AO22XLTS U3757 ( .A0(n966), .A1(FPSENCOS_d_ff1_Z[23]), .B0(n2553), .B1(
FPSENCOS_d_ff_Zn[23]), .Y(FPSENCOS_first_mux_Z[23]) );
AO22XLTS U3758 ( .A0(n966), .A1(FPSENCOS_d_ff1_Z[24]), .B0(n2553), .B1(
FPSENCOS_d_ff_Zn[24]), .Y(FPSENCOS_first_mux_Z[24]) );
AO22XLTS U3759 ( .A0(n2555), .A1(FPSENCOS_d_ff1_Z[25]), .B0(n2553), .B1(
FPSENCOS_d_ff_Zn[25]), .Y(FPSENCOS_first_mux_Z[25]) );
AO22XLTS U3760 ( .A0(n966), .A1(FPSENCOS_d_ff1_Z[26]), .B0(n2553), .B1(
FPSENCOS_d_ff_Zn[26]), .Y(FPSENCOS_first_mux_Z[26]) );
AO22XLTS U3761 ( .A0(n2555), .A1(FPSENCOS_d_ff1_Z[27]), .B0(n2553), .B1(
FPSENCOS_d_ff_Zn[27]), .Y(FPSENCOS_first_mux_Z[27]) );
AO22XLTS U3762 ( .A0(n966), .A1(FPSENCOS_d_ff1_Z[28]), .B0(n2552), .B1(
FPSENCOS_d_ff_Zn[28]), .Y(FPSENCOS_first_mux_Z[28]) );
AO22XLTS U3763 ( .A0(n966), .A1(FPSENCOS_d_ff1_Z[29]), .B0(n2552), .B1(
FPSENCOS_d_ff_Zn[29]), .Y(FPSENCOS_first_mux_Z[29]) );
AO22XLTS U3764 ( .A0(n2555), .A1(FPSENCOS_d_ff1_Z[30]), .B0(n2553), .B1(
FPSENCOS_d_ff_Zn[30]), .Y(FPSENCOS_first_mux_Z[30]) );
AO22XLTS U3765 ( .A0(n2550), .A1(FPSENCOS_d_ff1_Z[31]), .B0(n2552), .B1(
FPSENCOS_d_ff_Zn[31]), .Y(FPSENCOS_first_mux_Z[31]) );
AO22XLTS U3766 ( .A0(n2556), .A1(FPSENCOS_d_ff_Yn[0]), .B0(n2557), .B1(
FPSENCOS_d_ff_Xn[0]), .Y(FPSENCOS_mux_sal[0]) );
AO22XLTS U3767 ( .A0(n2556), .A1(FPSENCOS_d_ff_Yn[1]), .B0(n2557), .B1(
FPSENCOS_d_ff_Xn[1]), .Y(FPSENCOS_mux_sal[1]) );
AO22XLTS U3768 ( .A0(n2556), .A1(FPSENCOS_d_ff_Yn[2]), .B0(n2557), .B1(
FPSENCOS_d_ff_Xn[2]), .Y(FPSENCOS_mux_sal[2]) );
AO22XLTS U3769 ( .A0(n2556), .A1(FPSENCOS_d_ff_Yn[3]), .B0(n2557), .B1(
FPSENCOS_d_ff_Xn[3]), .Y(FPSENCOS_mux_sal[3]) );
AO22XLTS U3770 ( .A0(n2556), .A1(FPSENCOS_d_ff_Yn[4]), .B0(n2557), .B1(
FPSENCOS_d_ff_Xn[4]), .Y(FPSENCOS_mux_sal[4]) );
AO22XLTS U3771 ( .A0(n2556), .A1(FPSENCOS_d_ff_Yn[5]), .B0(n2557), .B1(
FPSENCOS_d_ff_Xn[5]), .Y(FPSENCOS_mux_sal[5]) );
AO22XLTS U3772 ( .A0(n2556), .A1(FPSENCOS_d_ff_Yn[6]), .B0(n2557), .B1(
FPSENCOS_d_ff_Xn[6]), .Y(FPSENCOS_mux_sal[6]) );
AO22XLTS U3773 ( .A0(n2556), .A1(FPSENCOS_d_ff_Yn[7]), .B0(n2557), .B1(
FPSENCOS_d_ff_Xn[7]), .Y(FPSENCOS_mux_sal[7]) );
AO22XLTS U3774 ( .A0(n2556), .A1(FPSENCOS_d_ff_Yn[8]), .B0(n2557), .B1(
FPSENCOS_d_ff_Xn[8]), .Y(FPSENCOS_mux_sal[8]) );
AO22XLTS U3775 ( .A0(n2556), .A1(FPSENCOS_d_ff_Yn[9]), .B0(n2557), .B1(
FPSENCOS_d_ff_Xn[9]), .Y(FPSENCOS_mux_sal[9]) );
AO22XLTS U3776 ( .A0(n2556), .A1(FPSENCOS_d_ff_Yn[10]), .B0(n2557), .B1(
FPSENCOS_d_ff_Xn[10]), .Y(FPSENCOS_mux_sal[10]) );
BUFX4TS U3777 ( .A(n2557), .Y(n2558) );
AO22XLTS U3778 ( .A0(n2556), .A1(FPSENCOS_d_ff_Yn[11]), .B0(n2558), .B1(
FPSENCOS_d_ff_Xn[11]), .Y(FPSENCOS_mux_sal[11]) );
AO22XLTS U3779 ( .A0(n2556), .A1(FPSENCOS_d_ff_Yn[12]), .B0(n2558), .B1(
FPSENCOS_d_ff_Xn[12]), .Y(FPSENCOS_mux_sal[12]) );
INVX4TS U3780 ( .A(n2558), .Y(n2559) );
AO22XLTS U3781 ( .A0(n2559), .A1(FPSENCOS_d_ff_Yn[13]), .B0(n2558), .B1(
FPSENCOS_d_ff_Xn[13]), .Y(FPSENCOS_mux_sal[13]) );
AO22XLTS U3782 ( .A0(n2559), .A1(FPSENCOS_d_ff_Yn[14]), .B0(n2558), .B1(
FPSENCOS_d_ff_Xn[14]), .Y(FPSENCOS_mux_sal[14]) );
AO22XLTS U3783 ( .A0(n2559), .A1(FPSENCOS_d_ff_Yn[15]), .B0(n2558), .B1(
FPSENCOS_d_ff_Xn[15]), .Y(FPSENCOS_mux_sal[15]) );
AO22XLTS U3784 ( .A0(n2559), .A1(FPSENCOS_d_ff_Yn[16]), .B0(n2558), .B1(
FPSENCOS_d_ff_Xn[16]), .Y(FPSENCOS_mux_sal[16]) );
AO22XLTS U3785 ( .A0(n2559), .A1(FPSENCOS_d_ff_Yn[17]), .B0(n2558), .B1(
FPSENCOS_d_ff_Xn[17]), .Y(FPSENCOS_mux_sal[17]) );
AO22XLTS U3786 ( .A0(n2559), .A1(FPSENCOS_d_ff_Yn[18]), .B0(n2558), .B1(
FPSENCOS_d_ff_Xn[18]), .Y(FPSENCOS_mux_sal[18]) );
AO22XLTS U3787 ( .A0(n2559), .A1(FPSENCOS_d_ff_Yn[19]), .B0(n2558), .B1(
FPSENCOS_d_ff_Xn[19]), .Y(FPSENCOS_mux_sal[19]) );
AO22XLTS U3788 ( .A0(n2559), .A1(FPSENCOS_d_ff_Yn[20]), .B0(n2558), .B1(
FPSENCOS_d_ff_Xn[20]), .Y(FPSENCOS_mux_sal[20]) );
AO22XLTS U3789 ( .A0(n2559), .A1(FPSENCOS_d_ff_Yn[21]), .B0(n2558), .B1(
FPSENCOS_d_ff_Xn[21]), .Y(FPSENCOS_mux_sal[21]) );
AO22XLTS U3790 ( .A0(n2559), .A1(FPSENCOS_d_ff_Yn[22]), .B0(n2558), .B1(
FPSENCOS_d_ff_Xn[22]), .Y(FPSENCOS_mux_sal[22]) );
AO22XLTS U3791 ( .A0(n2559), .A1(FPSENCOS_d_ff_Yn[23]), .B0(n2558), .B1(
FPSENCOS_d_ff_Xn[23]), .Y(FPSENCOS_mux_sal[23]) );
AO22XLTS U3792 ( .A0(n2559), .A1(FPSENCOS_d_ff_Yn[24]), .B0(n2558), .B1(
FPSENCOS_d_ff_Xn[24]), .Y(FPSENCOS_mux_sal[24]) );
AO22XLTS U3793 ( .A0(n2559), .A1(FPSENCOS_d_ff_Yn[25]), .B0(n2558), .B1(
FPSENCOS_d_ff_Xn[25]), .Y(FPSENCOS_mux_sal[25]) );
AO22XLTS U3794 ( .A0(n2559), .A1(FPSENCOS_d_ff_Yn[26]), .B0(n2558), .B1(
FPSENCOS_d_ff_Xn[26]), .Y(FPSENCOS_mux_sal[26]) );
AO22XLTS U3795 ( .A0(n2559), .A1(FPSENCOS_d_ff_Yn[27]), .B0(n2558), .B1(
FPSENCOS_d_ff_Xn[27]), .Y(FPSENCOS_mux_sal[27]) );
AO22XLTS U3796 ( .A0(n2559), .A1(FPSENCOS_d_ff_Yn[28]), .B0(n2558), .B1(
FPSENCOS_d_ff_Xn[28]), .Y(FPSENCOS_mux_sal[28]) );
AO22XLTS U3797 ( .A0(n2559), .A1(FPSENCOS_d_ff_Yn[29]), .B0(n2557), .B1(
FPSENCOS_d_ff_Xn[29]), .Y(FPSENCOS_mux_sal[29]) );
AO22XLTS U3798 ( .A0(n2559), .A1(FPSENCOS_d_ff_Yn[30]), .B0(n2558), .B1(
FPSENCOS_d_ff_Xn[30]), .Y(FPSENCOS_mux_sal[30]) );
NAND2X1TS U3799 ( .A(n2561), .B(n2560), .Y(FPMULT_FSM_barrel_shifter_load)
);
AOI21X1TS U3800 ( .A0(operation[1]), .A1(ack_operation), .B0(n2562), .Y(
n2573) );
NOR3XLTS U3801 ( .A(FPSENCOS_enab_RB3), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]), .C(FPSENCOS_enab_d_ff_RB1),
.Y(n2563) );
NAND3XLTS U3802 ( .A(n2564), .B(n2571), .C(n2563), .Y(n2565) );
NOR2BX1TS U3803 ( .AN(begin_operation), .B(n2586), .Y(n2567) );
OAI22X1TS U3804 ( .A0(n2573), .A1(n2565), .B0(n2567), .B1(n2566), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]) );
NOR2BX1TS U3805 ( .AN(n2567), .B(n2566), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]) );
AO21XLTS U3806 ( .A0(n2568), .A1(n2569), .B0(FPSENCOS_enab_RB3), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]) );
OAI22X1TS U3807 ( .A0(FPSENCOS_enab_d_ff4_Zn), .A1(n2571), .B0(n2570), .B1(
n2569), .Y(FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]) );
NOR2BX1TS U3808 ( .AN(FPSENCOS_enab_d_ff4_Zn), .B(n2571), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]) );
NAND2BXLTS U3809 ( .AN(n2573), .B(n2572), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]) );
AOI22X1TS U3810 ( .A0(FPSENCOS_d_ff3_sh_x_out[1]), .A1(n2660), .B0(Data_2[1]), .B1(n2659), .Y(n2575) );
AOI22X1TS U3811 ( .A0(n2587), .A1(FPSENCOS_d_ff3_sh_y_out[1]), .B0(n2626),
.B1(FPSENCOS_d_ff3_LUT_out[1]), .Y(n2574) );
NAND2X1TS U3812 ( .A(n2575), .B(n2574), .Y(add_subt_data2[1]) );
AOI22X1TS U3813 ( .A0(FPSENCOS_d_ff3_sh_x_out[2]), .A1(n2633), .B0(Data_2[2]), .B1(n2659), .Y(n2577) );
AOI22X1TS U3814 ( .A0(n2587), .A1(FPSENCOS_d_ff3_sh_y_out[2]), .B0(n2626),
.B1(FPSENCOS_d_ff3_LUT_out[2]), .Y(n2576) );
NAND2X1TS U3815 ( .A(n2577), .B(n2576), .Y(add_subt_data2[2]) );
AOI22X1TS U3816 ( .A0(FPSENCOS_d_ff3_sh_x_out[4]), .A1(n2633), .B0(Data_2[4]), .B1(n2659), .Y(n2579) );
AOI22X1TS U3817 ( .A0(n2587), .A1(FPSENCOS_d_ff3_sh_y_out[4]), .B0(n2626),
.B1(FPSENCOS_d_ff3_LUT_out[4]), .Y(n2578) );
NAND2X1TS U3818 ( .A(n2579), .B(n2578), .Y(add_subt_data2[4]) );
AOI22X1TS U3819 ( .A0(FPSENCOS_d_ff3_sh_x_out[6]), .A1(n2633), .B0(Data_2[6]), .B1(n2659), .Y(n2581) );
AOI22X1TS U3820 ( .A0(n2587), .A1(FPSENCOS_d_ff3_sh_y_out[6]), .B0(n2626),
.B1(FPSENCOS_d_ff3_LUT_out[6]), .Y(n2580) );
NAND2X1TS U3821 ( .A(n2581), .B(n2580), .Y(add_subt_data2[6]) );
AOI22X1TS U3822 ( .A0(FPSENCOS_d_ff3_sh_x_out[8]), .A1(n2633), .B0(Data_2[8]), .B1(n2586), .Y(n2583) );
AOI22X1TS U3823 ( .A0(n2587), .A1(FPSENCOS_d_ff3_sh_y_out[8]), .B0(n2626),
.B1(FPSENCOS_d_ff3_LUT_out[8]), .Y(n2582) );
NAND2X1TS U3824 ( .A(n2583), .B(n2582), .Y(add_subt_data2[8]) );
AOI22X1TS U3825 ( .A0(FPSENCOS_d_ff3_sh_x_out[9]), .A1(n2633), .B0(Data_2[9]), .B1(n2659), .Y(n2585) );
AOI22X1TS U3826 ( .A0(n2587), .A1(FPSENCOS_d_ff3_sh_y_out[9]), .B0(n2626),
.B1(FPSENCOS_d_ff3_LUT_out[9]), .Y(n2584) );
NAND2X1TS U3827 ( .A(n2585), .B(n2584), .Y(add_subt_data2[9]) );
AOI22X1TS U3828 ( .A0(FPSENCOS_d_ff3_sh_x_out[10]), .A1(n2633), .B0(
Data_2[10]), .B1(n2586), .Y(n2589) );
AOI22X1TS U3829 ( .A0(n2587), .A1(FPSENCOS_d_ff3_sh_y_out[10]), .B0(n2626),
.B1(FPSENCOS_d_ff3_LUT_out[10]), .Y(n2588) );
NAND2X1TS U3830 ( .A(n2589), .B(n2588), .Y(add_subt_data2[10]) );
AOI22X1TS U3831 ( .A0(FPSENCOS_d_ff3_sh_x_out[12]), .A1(n2633), .B0(
Data_2[12]), .B1(n2659), .Y(n2591) );
BUFX4TS U3832 ( .A(n1814), .Y(n2661) );
AOI22X1TS U3833 ( .A0(n2649), .A1(FPSENCOS_d_ff3_sh_y_out[12]), .B0(n2661),
.B1(FPSENCOS_d_ff3_LUT_out[12]), .Y(n2590) );
NAND2X1TS U3834 ( .A(n2591), .B(n2590), .Y(add_subt_data2[12]) );
AOI22X1TS U3835 ( .A0(FPSENCOS_d_ff3_sh_x_out[21]), .A1(n2660), .B0(
Data_2[21]), .B1(n2642), .Y(n2593) );
AOI22X1TS U3836 ( .A0(n2649), .A1(FPSENCOS_d_ff3_sh_y_out[21]), .B0(n2661),
.B1(FPSENCOS_d_ff3_LUT_out[21]), .Y(n2592) );
NAND2X1TS U3837 ( .A(n2593), .B(n2592), .Y(add_subt_data2[21]) );
AOI22X1TS U3838 ( .A0(FPSENCOS_d_ff3_sh_x_out[23]), .A1(n2660), .B0(
Data_2[23]), .B1(n2659), .Y(n2595) );
AOI22X1TS U3839 ( .A0(n2649), .A1(FPSENCOS_d_ff3_sh_y_out[23]), .B0(n2661),
.B1(FPSENCOS_d_ff3_LUT_out[23]), .Y(n2594) );
NAND2X1TS U3840 ( .A(n2595), .B(n2594), .Y(add_subt_data2[23]) );
AOI22X1TS U3841 ( .A0(FPSENCOS_d_ff3_sh_x_out[24]), .A1(n2660), .B0(
Data_2[24]), .B1(n2659), .Y(n2597) );
AOI22X1TS U3842 ( .A0(n2649), .A1(FPSENCOS_d_ff3_sh_y_out[24]), .B0(n2661),
.B1(FPSENCOS_d_ff3_LUT_out[24]), .Y(n2596) );
NAND2X1TS U3843 ( .A(n2597), .B(n2596), .Y(add_subt_data2[24]) );
AOI22X1TS U3844 ( .A0(FPSENCOS_d_ff3_sh_x_out[25]), .A1(n2660), .B0(
Data_2[25]), .B1(n2642), .Y(n2599) );
AOI22X1TS U3845 ( .A0(n2662), .A1(FPSENCOS_d_ff3_sh_y_out[25]), .B0(n2661),
.B1(FPSENCOS_d_ff3_LUT_out[25]), .Y(n2598) );
NAND2X1TS U3846 ( .A(n2599), .B(n2598), .Y(add_subt_data2[25]) );
AOI22X1TS U3847 ( .A0(FPSENCOS_d_ff3_sh_x_out[26]), .A1(n2660), .B0(
Data_2[26]), .B1(n2642), .Y(n2601) );
AOI22X1TS U3848 ( .A0(n2662), .A1(FPSENCOS_d_ff3_sh_y_out[26]), .B0(n2661),
.B1(FPSENCOS_d_ff3_LUT_out[26]), .Y(n2600) );
NAND2X1TS U3849 ( .A(n2601), .B(n2600), .Y(add_subt_data2[26]) );
INVX2TS U3850 ( .A(operation[2]), .Y(n2603) );
AO22XLTS U3851 ( .A0(operation[2]), .A1(n2602), .B0(n2603), .B1(
overflow_flag_addsubt), .Y(overflow_flag) );
AO22XLTS U3852 ( .A0(operation[2]), .A1(underflow_flag_mult), .B0(n2603),
.B1(underflow_flag_addsubt), .Y(underflow_flag) );
AOI22X1TS U3853 ( .A0(FPSENCOS_d_ff2_Y[0]), .A1(n2660), .B0(Data_1[0]), .B1(
n2642), .Y(n2605) );
AOI22X1TS U3854 ( .A0(n2662), .A1(FPSENCOS_d_ff2_X[0]), .B0(n2661), .B1(
FPSENCOS_d_ff2_Z[0]), .Y(n2604) );
NAND2X1TS U3855 ( .A(n2605), .B(n2604), .Y(add_subt_data1[0]) );
AOI22X1TS U3856 ( .A0(FPSENCOS_d_ff2_Y[1]), .A1(n2660), .B0(Data_1[1]), .B1(
n2642), .Y(n2607) );
AOI22X1TS U3857 ( .A0(n2662), .A1(FPSENCOS_d_ff2_X[1]), .B0(n2661), .B1(
FPSENCOS_d_ff2_Z[1]), .Y(n2606) );
NAND2X1TS U3858 ( .A(n2607), .B(n2606), .Y(add_subt_data1[1]) );
AOI22X1TS U3859 ( .A0(FPSENCOS_d_ff2_Y[2]), .A1(n2660), .B0(Data_1[2]), .B1(
n2642), .Y(n2609) );
AOI22X1TS U3860 ( .A0(n2662), .A1(FPSENCOS_d_ff2_X[2]), .B0(n2661), .B1(
FPSENCOS_d_ff2_Z[2]), .Y(n2608) );
NAND2X1TS U3861 ( .A(n2609), .B(n2608), .Y(add_subt_data1[2]) );
AOI22X1TS U3862 ( .A0(FPSENCOS_d_ff2_Y[3]), .A1(n2660), .B0(Data_1[3]), .B1(
n2642), .Y(n2611) );
AOI22X1TS U3863 ( .A0(n2662), .A1(FPSENCOS_d_ff2_X[3]), .B0(n2661), .B1(
FPSENCOS_d_ff2_Z[3]), .Y(n2610) );
NAND2X1TS U3864 ( .A(n2611), .B(n2610), .Y(add_subt_data1[3]) );
AOI22X1TS U3865 ( .A0(FPSENCOS_d_ff2_Y[4]), .A1(n2660), .B0(Data_1[4]), .B1(
n2642), .Y(n2613) );
AOI22X1TS U3866 ( .A0(n2662), .A1(FPSENCOS_d_ff2_X[4]), .B0(n2661), .B1(
FPSENCOS_d_ff2_Z[4]), .Y(n2612) );
NAND2X1TS U3867 ( .A(n2613), .B(n2612), .Y(add_subt_data1[4]) );
AOI22X1TS U3868 ( .A0(FPSENCOS_d_ff2_Y[5]), .A1(n2660), .B0(Data_1[5]), .B1(
n2642), .Y(n2615) );
AOI22X1TS U3869 ( .A0(n2662), .A1(FPSENCOS_d_ff2_X[5]), .B0(n2661), .B1(
FPSENCOS_d_ff2_Z[5]), .Y(n2614) );
NAND2X1TS U3870 ( .A(n2615), .B(n2614), .Y(add_subt_data1[5]) );
AOI22X1TS U3871 ( .A0(FPSENCOS_d_ff2_Y[6]), .A1(n2660), .B0(Data_1[6]), .B1(
n2642), .Y(n2617) );
AOI22X1TS U3872 ( .A0(n2656), .A1(FPSENCOS_d_ff2_X[6]), .B0(n2661), .B1(
FPSENCOS_d_ff2_Z[6]), .Y(n2616) );
NAND2X1TS U3873 ( .A(n2617), .B(n2616), .Y(add_subt_data1[6]) );
AOI22X1TS U3874 ( .A0(FPSENCOS_d_ff2_Y[7]), .A1(n2660), .B0(Data_1[7]), .B1(
n2642), .Y(n2619) );
AOI22X1TS U3875 ( .A0(n2656), .A1(FPSENCOS_d_ff2_X[7]), .B0(n2661), .B1(
FPSENCOS_d_ff2_Z[7]), .Y(n2618) );
NAND2X1TS U3876 ( .A(n2619), .B(n2618), .Y(add_subt_data1[7]) );
AOI22X1TS U3877 ( .A0(FPSENCOS_d_ff2_Y[8]), .A1(n2633), .B0(Data_1[8]), .B1(
n2642), .Y(n2621) );
AOI22X1TS U3878 ( .A0(n2656), .A1(FPSENCOS_d_ff2_X[8]), .B0(n2626), .B1(
FPSENCOS_d_ff2_Z[8]), .Y(n2620) );
NAND2X1TS U3879 ( .A(n2621), .B(n2620), .Y(add_subt_data1[8]) );
AOI22X1TS U3880 ( .A0(FPSENCOS_d_ff2_Y[9]), .A1(n2654), .B0(Data_1[9]), .B1(
n2642), .Y(n2623) );
AOI22X1TS U3881 ( .A0(n2656), .A1(FPSENCOS_d_ff2_X[9]), .B0(n1814), .B1(
FPSENCOS_d_ff2_Z[9]), .Y(n2622) );
NAND2X1TS U3882 ( .A(n2623), .B(n2622), .Y(add_subt_data1[9]) );
AOI22X1TS U3883 ( .A0(FPSENCOS_d_ff2_Y[11]), .A1(n2660), .B0(Data_1[11]),
.B1(n2642), .Y(n2625) );
AOI22X1TS U3884 ( .A0(n2656), .A1(FPSENCOS_d_ff2_X[11]), .B0(n2626), .B1(
FPSENCOS_d_ff2_Z[11]), .Y(n2624) );
NAND2X1TS U3885 ( .A(n2625), .B(n2624), .Y(add_subt_data1[11]) );
AOI22X1TS U3886 ( .A0(FPSENCOS_d_ff2_Y[12]), .A1(n2654), .B0(Data_1[12]),
.B1(n2642), .Y(n2628) );
AOI22X1TS U3887 ( .A0(n2656), .A1(FPSENCOS_d_ff2_X[12]), .B0(n2626), .B1(
FPSENCOS_d_ff2_Z[12]), .Y(n2627) );
NAND2X1TS U3888 ( .A(n2628), .B(n2627), .Y(add_subt_data1[12]) );
AOI22X1TS U3889 ( .A0(FPSENCOS_d_ff2_Y[13]), .A1(n2660), .B0(Data_1[13]),
.B1(n2642), .Y(n2630) );
AOI22X1TS U3890 ( .A0(n2656), .A1(FPSENCOS_d_ff2_X[13]), .B0(n2661), .B1(
FPSENCOS_d_ff2_Z[13]), .Y(n2629) );
NAND2X1TS U3891 ( .A(n2630), .B(n2629), .Y(add_subt_data1[13]) );
AOI22X1TS U3892 ( .A0(FPSENCOS_d_ff2_Y[14]), .A1(n2654), .B0(Data_1[14]),
.B1(n2642), .Y(n2632) );
AOI22X1TS U3893 ( .A0(n2656), .A1(FPSENCOS_d_ff2_X[14]), .B0(n2661), .B1(
FPSENCOS_d_ff2_Z[14]), .Y(n2631) );
NAND2X1TS U3894 ( .A(n2632), .B(n2631), .Y(add_subt_data1[14]) );
AOI22X1TS U3895 ( .A0(FPSENCOS_d_ff2_Y[15]), .A1(n2633), .B0(Data_1[15]),
.B1(n2642), .Y(n2635) );
AOI22X1TS U3896 ( .A0(n2656), .A1(FPSENCOS_d_ff2_X[15]), .B0(n2661), .B1(
FPSENCOS_d_ff2_Z[15]), .Y(n2634) );
NAND2X1TS U3897 ( .A(n2635), .B(n2634), .Y(add_subt_data1[15]) );
AOI22X1TS U3898 ( .A0(FPSENCOS_d_ff2_Y[16]), .A1(n2660), .B0(Data_1[16]),
.B1(n2642), .Y(n2637) );
AOI22X1TS U3899 ( .A0(n2656), .A1(FPSENCOS_d_ff2_X[16]), .B0(n1814), .B1(
FPSENCOS_d_ff2_Z[16]), .Y(n2636) );
NAND2X1TS U3900 ( .A(n2637), .B(n2636), .Y(add_subt_data1[16]) );
AOI22X1TS U3901 ( .A0(FPSENCOS_d_ff2_Y[17]), .A1(n2660), .B0(Data_1[17]),
.B1(n2642), .Y(n2639) );
AOI22X1TS U3902 ( .A0(n2656), .A1(FPSENCOS_d_ff2_X[17]), .B0(n1814), .B1(
FPSENCOS_d_ff2_Z[17]), .Y(n2638) );
NAND2X1TS U3903 ( .A(n2639), .B(n2638), .Y(add_subt_data1[17]) );
AOI22X1TS U3904 ( .A0(FPSENCOS_d_ff2_Y[18]), .A1(n2654), .B0(Data_1[18]),
.B1(n2642), .Y(n2641) );
AOI22X1TS U3905 ( .A0(n2656), .A1(FPSENCOS_d_ff2_X[18]), .B0(n1814), .B1(
FPSENCOS_d_ff2_Z[18]), .Y(n2640) );
NAND2X1TS U3906 ( .A(n2641), .B(n2640), .Y(add_subt_data1[18]) );
AOI22X1TS U3907 ( .A0(FPSENCOS_d_ff2_Y[20]), .A1(n2654), .B0(Data_1[20]),
.B1(n2642), .Y(n2644) );
AOI22X1TS U3908 ( .A0(n2649), .A1(FPSENCOS_d_ff2_X[20]), .B0(n2655), .B1(
FPSENCOS_d_ff2_Z[20]), .Y(n2643) );
NAND2X1TS U3909 ( .A(n2644), .B(n2643), .Y(add_subt_data1[20]) );
AOI22X1TS U3910 ( .A0(FPSENCOS_d_ff2_Y[24]), .A1(n2654), .B0(Data_1[24]),
.B1(n2659), .Y(n2646) );
AOI22X1TS U3911 ( .A0(n2656), .A1(FPSENCOS_d_ff2_X[24]), .B0(n2655), .B1(
FPSENCOS_d_ff2_Z[24]), .Y(n2645) );
NAND2X1TS U3912 ( .A(n2646), .B(n2645), .Y(add_subt_data1[24]) );
AOI22X1TS U3913 ( .A0(FPSENCOS_d_ff2_Y[25]), .A1(n2654), .B0(Data_1[25]),
.B1(n2659), .Y(n2648) );
AOI22X1TS U3914 ( .A0(n2662), .A1(FPSENCOS_d_ff2_X[25]), .B0(n2655), .B1(
FPSENCOS_d_ff2_Z[25]), .Y(n2647) );
NAND2X1TS U3915 ( .A(n2648), .B(n2647), .Y(add_subt_data1[25]) );
AOI22X1TS U3916 ( .A0(FPSENCOS_d_ff2_Y[26]), .A1(n2654), .B0(Data_1[26]),
.B1(n2659), .Y(n2651) );
AOI22X1TS U3917 ( .A0(n2649), .A1(FPSENCOS_d_ff2_X[26]), .B0(n2655), .B1(
FPSENCOS_d_ff2_Z[26]), .Y(n2650) );
NAND2X1TS U3918 ( .A(n2651), .B(n2650), .Y(add_subt_data1[26]) );
AOI22X1TS U3919 ( .A0(n969), .A1(n2654), .B0(Data_1[27]), .B1(n2659), .Y(
n2653) );
AOI22X1TS U3920 ( .A0(n2656), .A1(n968), .B0(n2655), .B1(
FPSENCOS_d_ff2_Z[27]), .Y(n2652) );
NAND2X1TS U3921 ( .A(n2653), .B(n2652), .Y(add_subt_data1[27]) );
AOI22X1TS U3922 ( .A0(n964), .A1(n2654), .B0(Data_1[29]), .B1(n2659), .Y(
n2658) );
AOI22X1TS U3923 ( .A0(n2656), .A1(FPSENCOS_d_ff2_X[29]), .B0(n2655), .B1(
FPSENCOS_d_ff2_Z[29]), .Y(n2657) );
NAND2X1TS U3924 ( .A(n2658), .B(n2657), .Y(add_subt_data1[29]) );
AOI22X1TS U3925 ( .A0(FPSENCOS_d_ff2_Y[31]), .A1(n2660), .B0(Data_1[31]),
.B1(n2659), .Y(n2664) );
AOI22X1TS U3926 ( .A0(n2662), .A1(FPSENCOS_d_ff2_X[31]), .B0(n2661), .B1(
FPSENCOS_d_ff2_Z[31]), .Y(n2663) );
NAND2X1TS U3927 ( .A(n2664), .B(n2663), .Y(add_subt_data1[31]) );
OA21XLTS U3928 ( .A0(FPSENCOS_cont_iter_out[2]), .A1(n2666), .B0(n2665), .Y(
FPSENCOS_ITER_CONT_N4) );
BUFX3TS U3929 ( .A(n1669), .Y(n2701) );
AOI22X1TS U3930 ( .A0(n2701), .A1(cordic_result[31]), .B0(n1672), .B1(
mult_result[31]), .Y(n2667) );
OAI2BB1X1TS U3931 ( .A0N(n2703), .A1N(result_add_subt[31]), .B0(n2667), .Y(
op_result[31]) );
BUFX4TS U3932 ( .A(n1670), .Y(n2693) );
AOI22X1TS U3933 ( .A0(n2701), .A1(cordic_result[30]), .B0(n1672), .B1(
mult_result[30]), .Y(n2668) );
OAI2BB1X1TS U3934 ( .A0N(n2693), .A1N(result_add_subt[30]), .B0(n2668), .Y(
op_result[30]) );
AOI22X1TS U3935 ( .A0(n2701), .A1(cordic_result[29]), .B0(n1672), .B1(
mult_result[29]), .Y(n2669) );
OAI2BB1X1TS U3936 ( .A0N(n2693), .A1N(result_add_subt[29]), .B0(n2669), .Y(
op_result[29]) );
AOI22X1TS U3937 ( .A0(n2701), .A1(cordic_result[28]), .B0(n1672), .B1(
mult_result[28]), .Y(n2670) );
OAI2BB1X1TS U3938 ( .A0N(n2693), .A1N(result_add_subt[28]), .B0(n2670), .Y(
op_result[28]) );
AOI22X1TS U3939 ( .A0(n2701), .A1(cordic_result[27]), .B0(n1672), .B1(
mult_result[27]), .Y(n2671) );
OAI2BB1X1TS U3940 ( .A0N(n2693), .A1N(result_add_subt[27]), .B0(n2671), .Y(
op_result[27]) );
AOI22X1TS U3941 ( .A0(n2701), .A1(cordic_result[26]), .B0(n1672), .B1(
mult_result[26]), .Y(n2672) );
OAI2BB1X1TS U3942 ( .A0N(n2693), .A1N(result_add_subt[26]), .B0(n2672), .Y(
op_result[26]) );
AOI22X1TS U3943 ( .A0(n2701), .A1(cordic_result[25]), .B0(n1672), .B1(
mult_result[25]), .Y(n2673) );
OAI2BB1X1TS U3944 ( .A0N(n2693), .A1N(result_add_subt[25]), .B0(n2673), .Y(
op_result[25]) );
AOI22X1TS U3945 ( .A0(n2701), .A1(cordic_result[24]), .B0(n1672), .B1(
mult_result[24]), .Y(n2674) );
OAI2BB1X1TS U3946 ( .A0N(n2693), .A1N(result_add_subt[24]), .B0(n2674), .Y(
op_result[24]) );
AOI22X1TS U3947 ( .A0(n2701), .A1(cordic_result[23]), .B0(n1672), .B1(
mult_result[23]), .Y(n2675) );
OAI2BB1X1TS U3948 ( .A0N(n2693), .A1N(result_add_subt[23]), .B0(n2675), .Y(
op_result[23]) );
AOI22X1TS U3949 ( .A0(n2701), .A1(cordic_result[22]), .B0(n1672), .B1(
mult_result[22]), .Y(n2676) );
OAI2BB1X1TS U3950 ( .A0N(n2693), .A1N(result_add_subt[22]), .B0(n2676), .Y(
op_result[22]) );
AOI22X1TS U3951 ( .A0(n2701), .A1(cordic_result[21]), .B0(n1672), .B1(
mult_result[21]), .Y(n2677) );
OAI2BB1X1TS U3952 ( .A0N(n2693), .A1N(result_add_subt[21]), .B0(n2677), .Y(
op_result[21]) );
AOI22X1TS U3953 ( .A0(n2701), .A1(cordic_result[20]), .B0(n1672), .B1(
mult_result[20]), .Y(n2678) );
OAI2BB1X1TS U3954 ( .A0N(n2693), .A1N(result_add_subt[20]), .B0(n2678), .Y(
op_result[20]) );
AOI22X1TS U3955 ( .A0(n2698), .A1(cordic_result[19]), .B0(n1672), .B1(
mult_result[19]), .Y(n2679) );
OAI2BB1X1TS U3956 ( .A0N(n2693), .A1N(result_add_subt[19]), .B0(n2679), .Y(
op_result[19]) );
AOI22X1TS U3957 ( .A0(n2698), .A1(cordic_result[18]), .B0(n2700), .B1(
mult_result[18]), .Y(n2680) );
OAI2BB1X1TS U3958 ( .A0N(n2693), .A1N(result_add_subt[18]), .B0(n2680), .Y(
op_result[18]) );
AOI22X1TS U3959 ( .A0(n2698), .A1(cordic_result[17]), .B0(n2700), .B1(
mult_result[17]), .Y(n2681) );
OAI2BB1X1TS U3960 ( .A0N(n2693), .A1N(result_add_subt[17]), .B0(n2681), .Y(
op_result[17]) );
AOI22X1TS U3961 ( .A0(n2698), .A1(cordic_result[16]), .B0(n2700), .B1(
mult_result[16]), .Y(n2682) );
OAI2BB1X1TS U3962 ( .A0N(n2693), .A1N(result_add_subt[16]), .B0(n2682), .Y(
op_result[16]) );
AOI22X1TS U3963 ( .A0(n2698), .A1(cordic_result[15]), .B0(n2700), .B1(
mult_result[15]), .Y(n2683) );
OAI2BB1X1TS U3964 ( .A0N(n2693), .A1N(result_add_subt[15]), .B0(n2683), .Y(
op_result[15]) );
AOI22X1TS U3965 ( .A0(n2698), .A1(cordic_result[14]), .B0(n2700), .B1(
mult_result[14]), .Y(n2684) );
OAI2BB1X1TS U3966 ( .A0N(n2693), .A1N(result_add_subt[14]), .B0(n2684), .Y(
op_result[14]) );
AOI22X1TS U3967 ( .A0(n2698), .A1(cordic_result[13]), .B0(n2700), .B1(
mult_result[13]), .Y(n2685) );
OAI2BB1X1TS U3968 ( .A0N(n2693), .A1N(result_add_subt[13]), .B0(n2685), .Y(
op_result[13]) );
AOI22X1TS U3969 ( .A0(n2698), .A1(cordic_result[12]), .B0(n2700), .B1(
mult_result[12]), .Y(n2686) );
OAI2BB1X1TS U3970 ( .A0N(n2693), .A1N(result_add_subt[12]), .B0(n2686), .Y(
op_result[12]) );
AOI22X1TS U3971 ( .A0(n2698), .A1(cordic_result[11]), .B0(n2700), .B1(
mult_result[11]), .Y(n2687) );
OAI2BB1X1TS U3972 ( .A0N(n2703), .A1N(result_add_subt[11]), .B0(n2687), .Y(
op_result[11]) );
AOI22X1TS U3973 ( .A0(n2698), .A1(cordic_result[10]), .B0(n2700), .B1(
mult_result[10]), .Y(n2688) );
OAI2BB1X1TS U3974 ( .A0N(n2703), .A1N(result_add_subt[10]), .B0(n2688), .Y(
op_result[10]) );
AOI22X1TS U3975 ( .A0(n2698), .A1(cordic_result[9]), .B0(n2700), .B1(
mult_result[9]), .Y(n2689) );
OAI2BB1X1TS U3976 ( .A0N(n2703), .A1N(result_add_subt[9]), .B0(n2689), .Y(
op_result[9]) );
AOI22X1TS U3977 ( .A0(n2698), .A1(cordic_result[8]), .B0(n2700), .B1(
mult_result[8]), .Y(n2690) );
OAI2BB1X1TS U3978 ( .A0N(n2703), .A1N(result_add_subt[8]), .B0(n2690), .Y(
op_result[8]) );
AOI22X1TS U3979 ( .A0(n2698), .A1(cordic_result[7]), .B0(n2700), .B1(
mult_result[7]), .Y(n2691) );
OAI2BB1X1TS U3980 ( .A0N(n2703), .A1N(result_add_subt[7]), .B0(n2691), .Y(
op_result[7]) );
AOI22X1TS U3981 ( .A0(n2698), .A1(cordic_result[6]), .B0(n2700), .B1(
mult_result[6]), .Y(n2692) );
OAI2BB1X1TS U3982 ( .A0N(n2693), .A1N(result_add_subt[6]), .B0(n2692), .Y(
op_result[6]) );
AOI22X1TS U3983 ( .A0(n1669), .A1(cordic_result[5]), .B0(n1672), .B1(
mult_result[5]), .Y(n2694) );
OAI2BB1X1TS U3984 ( .A0N(n2703), .A1N(result_add_subt[5]), .B0(n2694), .Y(
op_result[5]) );
AOI22X1TS U3985 ( .A0(n1669), .A1(cordic_result[4]), .B0(n1672), .B1(
mult_result[4]), .Y(n2695) );
OAI2BB1X1TS U3986 ( .A0N(n2703), .A1N(result_add_subt[4]), .B0(n2695), .Y(
op_result[4]) );
AOI22X1TS U3987 ( .A0(n2698), .A1(cordic_result[3]), .B0(n1672), .B1(
mult_result[3]), .Y(n2696) );
OAI2BB1X1TS U3988 ( .A0N(n2703), .A1N(result_add_subt[3]), .B0(n2696), .Y(
op_result[3]) );
AOI22X1TS U3989 ( .A0(n2698), .A1(cordic_result[2]), .B0(n2700), .B1(
mult_result[2]), .Y(n2697) );
OAI2BB1X1TS U3990 ( .A0N(n2703), .A1N(result_add_subt[2]), .B0(n2697), .Y(
op_result[2]) );
AOI22X1TS U3991 ( .A0(n2698), .A1(cordic_result[1]), .B0(n2700), .B1(
mult_result[1]), .Y(n2699) );
OAI2BB1X1TS U3992 ( .A0N(n2703), .A1N(result_add_subt[1]), .B0(n2699), .Y(
op_result[1]) );
AOI22X1TS U3993 ( .A0(n2698), .A1(cordic_result[0]), .B0(n2700), .B1(
mult_result[0]), .Y(n2702) );
OAI2BB1X1TS U3994 ( .A0N(n2703), .A1N(result_add_subt[0]), .B0(n2702), .Y(
op_result[0]) );
AOI22X1TS U3995 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n2706), .B0(n2704),
.B1(n2800), .Y(n861) );
AOI22X1TS U3996 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n2706), .B0(n2705),
.B1(n2800), .Y(n853) );
OAI2BB1X1TS U3997 ( .A0N(FPSENCOS_cont_iter_out[1]), .A1N(n851), .B0(n2707),
.Y(n852) );
AOI22X1TS U3998 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n2709), .B0(n2708),
.B1(n2800), .Y(n848) );
INVX2TS U3999 ( .A(n2714), .Y(n2710) );
AOI22X1TS U4000 ( .A0(ack_operation), .A1(n2917), .B0(begin_operation), .B1(
n2710), .Y(n2712) );
OAI22X1TS U4001 ( .A0(n2714), .A1(n2713), .B0(n2712), .B1(n2711), .Y(n846)
);
AO22XLTS U4002 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n2838), .B1(n2715),
.Y(n2717) );
OAI22X1TS U4003 ( .A0(n2718), .A1(n2717), .B0(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B1(n2716), .Y(n844) );
AOI22X1TS U4004 ( .A0(FPSENCOS_cont_var_out[0]), .A1(n2720), .B0(n2719),
.B1(n2808), .Y(n843) );
NAND2X1TS U4005 ( .A(n1963), .B(n2844), .Y(FPADDSUB__6_net_) );
NAND4XLTS U4006 ( .A(n2724), .B(n2723), .C(n2722), .D(n2721), .Y(n2740) );
NOR4X1TS U4007 ( .A(FPMULT_Op_MY[29]), .B(FPMULT_Op_MY[28]), .C(
FPMULT_Op_MY[27]), .D(FPMULT_Op_MY[26]), .Y(n2728) );
NOR4X1TS U4008 ( .A(FPMULT_Op_MY[25]), .B(FPMULT_Op_MY[24]), .C(
FPMULT_Op_MY[23]), .D(FPMULT_Op_MY[30]), .Y(n2725) );
NAND4XLTS U4009 ( .A(n2728), .B(n2727), .C(n2726), .D(n2725), .Y(n2739) );
NAND4XLTS U4010 ( .A(n2732), .B(n2731), .C(n2730), .D(n2729), .Y(n2738) );
NOR4X1TS U4011 ( .A(FPMULT_Op_MX[30]), .B(FPMULT_Op_MX[29]), .C(
FPMULT_Op_MX[28]), .D(FPMULT_Op_MX[27]), .Y(n2736) );
NOR3XLTS U4012 ( .A(FPMULT_Op_MX[0]), .B(FPMULT_Op_MX[12]), .C(
FPMULT_Op_MX[10]), .Y(n2735) );
NAND4XLTS U4013 ( .A(n2736), .B(n2735), .C(n2734), .D(n2733), .Y(n2737) );
OAI22X1TS U4014 ( .A0(n2740), .A1(n2739), .B0(n2738), .B1(n2737), .Y(n106)
);
AO22XLTS U4015 ( .A0(busy), .A1(FPADDSUB_SIGN_FLAG_SHT1), .B0(n2844), .B1(
FPADDSUB_SIGN_FLAG_SHT2), .Y(n819) );
AO22XLTS U4016 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(
FPADDSUB_SIGN_FLAG_NRM), .B0(n1963), .B1(FPADDSUB_SIGN_FLAG_SHT1SHT2),
.Y(n816) );
XNOR2X1TS U4017 ( .A(FPADDSUB_intDX_EWSW[31]), .B(n2956), .Y(n30) );
AO22XLTS U4018 ( .A0(busy), .A1(FPADDSUB_OP_FLAG_SHT1), .B0(n2844), .B1(
FPADDSUB_OP_FLAG_SHT2), .Y(n813) );
NOR2BX1TS U4019 ( .AN(FPADDSUB_Shift_reg_FLAGS_7[3]), .B(
FPADDSUB_Shift_reg_FLAGS_7[0]), .Y(FPADDSUB__19_net_) );
NOR2XLTS U4020 ( .A(n964), .B(n2742), .Y(n2741) );
XOR2XLTS U4021 ( .A(n2741), .B(FPSENCOS_d_ff2_Y[30]), .Y(
FPSENCOS_sh_exp_y[7]) );
XNOR2X1TS U4022 ( .A(n964), .B(n2742), .Y(FPSENCOS_sh_exp_y[6]) );
AO21XLTS U4023 ( .A0(intadd_1062_n1), .A1(n969), .B0(n2743), .Y(
FPSENCOS_sh_exp_y[4]) );
NOR2XLTS U4024 ( .A(FPSENCOS_d_ff2_X[29]), .B(n2745), .Y(n2744) );
XOR2XLTS U4025 ( .A(n2744), .B(FPSENCOS_d_ff2_X[30]), .Y(
FPSENCOS_sh_exp_x[7]) );
XNOR2X1TS U4026 ( .A(FPSENCOS_d_ff2_X[29]), .B(n2745), .Y(
FPSENCOS_sh_exp_x[6]) );
AO21XLTS U4027 ( .A0(intadd_1061_n1), .A1(n968), .B0(n2746), .Y(
FPSENCOS_sh_exp_x[4]) );
CMPR32X4TS U4028 ( .A(FPMULT_Op_MX[17]), .B(n974), .C(intadd_1056_n7), .CO(
intadd_1056_n6), .S(intadd_1059_A_4_) );
CMPR32X4TS U4029 ( .A(FPMULT_Op_MX[15]), .B(n983), .C(intadd_1056_n9), .CO(
intadd_1056_n8), .S(intadd_1059_A_2_) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_GATED_RKOA_1STAGE_syn.sdf");
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Wilson Snyder.
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
`define checkg(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%g' exp='%g'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
string s;
integer cyc=0;
// Check constification
initial begin
s="1234"; `checkh(s.len(),4);
`ifndef VERILATOR
s="1234"; s.putc(2, "z"); `checks(s, "12z4");
s="1234"; `checkh(s.getc(2), "3");
s="abCD"; `checks(s.toupper(), "ABCD");
s="abCD"; `checks(s.tolower(), "abcd");
s="b"; if (s.compare("a") <= 0) $stop;
s="b"; if (s.compare("b") != 0) $stop;
s="b"; if (s.compare("c") >= 0) $stop;
s="b"; if (s.icompare("A") < 0) $stop;
s="b"; if (s.icompare("B") != 0) $stop;
s="b"; if (s.icompare("C") >= 0) $stop;
s="101"; `checkh(s.atoi(), 'd101);
s="101"; `checkh(s.atohex(), 'h101);
s="101"; `checkh(s.atooct(), 'o101);
s="101"; `checkh(s.atobin(), 'b101);
s="1.23"; `checkg(s.atoreal(), 1.23);
`endif
s.itoa(123); `checks(s, "123");
s.hextoa(123); `checks(s, "7b");
s.octtoa(123); `checks(s, "173");
s.bintoa(123); `checks(s, "1111011");
s.realtoa(1.23); `checks(s, "1.23");
end
// Check runtime
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
s = "1234";
end
else if (cyc==1) begin
`checkh(s.len(),4);
end
`ifndef VERILATOR
else if (cyc==2) begin
s.putc(2, "z");
end
else if (cyc==3) begin
`checks(s, "12z4");
`checkh(s.getc(2), "z");
s="abCD";
end
else if (cyc==4) begin
`checks(s.toupper(), "ABCD");
`checks(s.tolower(), "abcd");
s="b";
end
else if (cyc==5) begin
if (s.compare("a") <= 0) $stop;
if (s.compare("b") != 0) $stop;
if (s.compare("c") >= 0) $stop;
if (s.icompare("A") < 0) $stop;
if (s.icompare("B") != 0) $stop;
if (s.icompare("C") >= 0) $stop;
s="101";
end
else if (cyc==7) begin
`checkh(s.atoi(), 'd101);
`checkh(s.atohex(), 'h101);
`checkh(s.atooct(), 'o101);
`checkh(s.atobin(), 'b101);
s="1.23";
end
else if (cyc==8) begin
`checkg(s.atoreal(), 1.23);
end
`endif
else if (cyc==9) begin
s.itoa(123);
end
else if (cyc==10) begin
`checks(s, "123");
s.hextoa(123);
end
else if (cyc==11) begin
`checks(s, "7b");
s.octtoa(123);
end
else if (cyc==12) begin
`checks(s, "173");
s.bintoa(123);
end
else if (cyc==13) begin
`checks(s, "1111011");
s.realtoa(1.23);
end
else if (cyc==14) begin
`checks(s, "1.23");
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sat Nov 19 19:22:53 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire Shift_reg_FLAGS_7_6, intAS, SIGN_FLAG_EXP, OP_FLAG_EXP, ZERO_FLAG_EXP,
SIGN_FLAG_SHT1, OP_FLAG_SHT1, ZERO_FLAG_SHT1, left_right_SHT2,
SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2, SIGN_FLAG_SHT1SHT2,
ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM, ZERO_FLAG_NRM, SIGN_FLAG_SFG,
ZERO_FLAG_SFG, inst_FSM_INPUT_ENABLE_state_next_1_, n463, n464, n465,
n466, n467, n468, n469, n470, n471, n472, n473, n474, n475, n476,
n477, n478, n479, n480, n481, n482, n483, n484, n485, n486, n487,
n488, n489, n490, n491, n492, n493, n494, n495, n496, n497, n498,
n499, n500, n501, n502, n503, n504, n505, n506, n507, n508, n509,
n510, n511, n512, n513, n514, n515, n516, n517, n518, n519, n520,
n521, n522, n523, n524, n525, n526, n527, n528, n529, n530, n531,
n532, n533, n534, n535, n536, n537, n538, n539, n540, n541, n542,
n543, n544, n545, n546, n547, n548, n549, n551, n552, n553, n554,
n555, n556, n557, n558, n559, n560, n561, n562, n563, n564, n565,
n566, n567, n568, n569, n570, n571, n572, n573, n574, n575, n576,
n577, n578, n579, n580, n581, n582, n583, n584, n585, n586, n587,
n588, n589, n590, n591, n592, n593, n594, n595, n596, n597, n598,
n599, n600, n601, n602, n603, n604, n605, n606, n607, n608, n609,
n610, n611, n612, n613, n614, n615, n616, n617, n618, n619, n620,
n621, n622, n623, n624, n625, n626, n627, n628, n629, n630, n631,
n632, n633, n634, n635, n636, n637, n638, n639, n640, n641, n642,
n643, n644, n645, n646, n647, n648, n649, n650, n651, n652, n653,
n654, n655, n656, n657, n658, n659, n660, n661, n662, n663, n664,
n665, n666, n667, n668, n669, n670, n671, n672, n673, n674, n675,
n676, n677, n678, n679, n680, n681, n682, n683, n684, n685, n686,
n687, n688, n689, n690, n691, n692, n693, n694, n695, n696, n697,
n698, n699, n700, n701, n702, n703, n704, n705, n706, n707, n708,
n709, n710, n711, n712, n713, n714, n715, n716, n717, n718, n719,
n720, n721, n722, n723, n724, n725, n726, n727, n728, n729, n730,
n731, n732, n733, n734, n735, n736, n737, n738, n739, n740, n741,
n742, n743, n744, n745, n746, n747, n748, n749, n750, n751, n752,
n753, n754, n755, n756, n757, n758, n759, n760, n761, n762, n763,
n764, n765, n766, n767, n769, n770, n771, n772, n773, n774, n775,
n776, n777, n778, n779, n780, n781, n782, n783, n784, n785, n786,
n787, n788, n789, n790, n791, n792, n793, n794, n795, n796, n797,
n798, n799, n800, n801, n802, n803, n804, n805, n806, n807, n808,
n809, n810, n811, n812, n813, n814, n815, n816, n817, n818, n819,
n820, n821, n822, n823, n824, n825, n826, n827, n828, n829, n830,
n831, n832, n833, n834, n835, n836, n837, n838, n839, n840, n841,
n842, n843, n844, n845, n846, n847, n848, n849, n850, n851, n852,
n853, n854, n855, n856, n857, n858, n859, n860, n861, n862, n863,
n864, n865, n866, n867, n868, n869, n870, n871,
DP_OP_15J28_123_3372_n8, DP_OP_15J28_123_3372_n7,
DP_OP_15J28_123_3372_n6, DP_OP_15J28_123_3372_n5,
DP_OP_15J28_123_3372_n4, intadd_21_B_2_, intadd_21_B_1_,
intadd_21_B_0_, intadd_21_CI, intadd_21_SUM_2_, intadd_21_SUM_1_,
intadd_21_SUM_0_, intadd_21_n3, intadd_21_n2, intadd_21_n1,
DP_OP_285J28_122_2126_n74, DP_OP_285J28_122_2126_n73,
DP_OP_285J28_122_2126_n72, DP_OP_285J28_122_2126_n71,
DP_OP_285J28_122_2126_n70, n873, n874, n875, n876, n877, n878, n879,
n880, n881, n882, n883, n884, n885, n886, n887, n888, n889, n890,
n891, n892, n893, n894, n895, n896, n897, n898, n899, n900, n901,
n902, n903, n904, n905, n906, n907, n908, n909, n910, n911, n912,
n913, n914, n915, n916, n917, n918, n919, n920, n921, n922, n923,
n924, n925, n926, n927, n928, n929, n930, n931, n932, n933, n934,
n935, n936, n937, n938, n939, n940, n941, n942, n943, n944, n945,
n946, n947, n948, n949, n950, n951, n952, n953, n954, n955, n956,
n957, n958, n959, n960, n961, n962, n963, n964, n965, n966, n967,
n968, n969, n970, n971, n972, n973, n974, n975, n976, n977, n978,
n979, n980, n981, n982, n983, n984, n985, n986, n987, n988, n989,
n990, n991, n992, n993, n994, n995, n996, n997, n998, n999, n1000,
n1001, n1002, n1003, n1004, n1005, n1006, n1007, n1008, n1009, n1010,
n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019, n1020,
n1021, n1022, n1023, n1024, n1025, n1026, n1027, n1028, n1029, n1030,
n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039, n1040,
n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050,
n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1060,
n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070,
n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080,
n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090,
n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099, n1100,
n1101, n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110,
n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120,
n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130,
n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140,
n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150,
n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160,
n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170,
n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180,
n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190,
n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200,
n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210,
n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220,
n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230,
n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240,
n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250,
n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260,
n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270,
n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280,
n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290,
n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300,
n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310,
n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320,
n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330,
n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340,
n1341, n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350,
n1351, n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360,
n1361, n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370,
n1371, n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380,
n1381, n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390,
n1391, n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400,
n1401, n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410,
n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420,
n1421, n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430,
n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440,
n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450,
n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460,
n1461, n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470,
n1471, n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480,
n1481, n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490,
n1491, n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500,
n1501, n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510,
n1511, n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520,
n1521, n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530,
n1531, n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540,
n1541, n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550,
n1551, n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560,
n1561, n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570,
n1571, n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580,
n1581, n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590,
n1591, n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600,
n1601, n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610,
n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620,
n1621, n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630,
n1631, n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640,
n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650,
n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660,
n1661, n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670,
n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680,
n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690,
n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700,
n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710,
n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720,
n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730,
n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740,
n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750,
n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760,
n1761, n1762, n1763, n1764, n1765;
wire [3:0] Shift_reg_FLAGS_7;
wire [31:0] intDX_EWSW;
wire [31:0] intDY_EWSW;
wire [30:0] DMP_EXP_EWSW;
wire [27:0] DmP_EXP_EWSW;
wire [30:0] DMP_SHT1_EWSW;
wire [22:0] DmP_mant_SHT1_SW;
wire [4:0] Shift_amount_SHT1_EWR;
wire [25:0] Raw_mant_NRM_SWR;
wire [25:0] Data_array_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [4:2] shift_value_SHT2_EWR;
wire [7:0] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [4:0] LZD_output_NRM2_EW;
wire [4:1] exp_rslt_NRM2_EW1;
wire [30:0] DMP_SFG;
wire [25:0] DmP_mant_SFG_SWR;
wire [11:10] DmP_mant_SFG_SWR_signed;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_ShiftRegister_Q_reg_6_ ( .D(n869), .CK(clk), .RN(n1724), .Q(
Shift_reg_FLAGS_7_6), .QN(n928) );
DFFRXLTS inst_ShiftRegister_Q_reg_3_ ( .D(n866), .CK(clk), .RN(n1724), .Q(
Shift_reg_FLAGS_7[3]) );
DFFRXLTS inst_ShiftRegister_Q_reg_2_ ( .D(n865), .CK(clk), .RN(n1763), .Q(
Shift_reg_FLAGS_7[2]), .QN(n1717) );
DFFRXLTS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n830), .CK(clk), .RN(n1728), .Q(
intAS) );
DFFRXLTS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n829), .CK(clk), .RN(n1728), .Q(
left_right_SHT2), .QN(n888) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n764), .CK(clk), .RN(n1734),
.Q(Shift_amount_SHT1_EWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n763), .CK(clk), .RN(n1734),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n762), .CK(clk), .RN(n1734),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n753), .CK(clk), .RN(n1738), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n752), .CK(clk), .RN(n1135), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n751), .CK(clk), .RN(n1739), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n750), .CK(clk), .RN(n1136), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n749), .CK(clk), .RN(n1134), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n748), .CK(clk), .RN(n1139), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n747), .CK(clk), .RN(n1138), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n746), .CK(clk), .RN(n1735), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n745), .CK(clk), .RN(n1134), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n744), .CK(clk), .RN(n1735), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n743), .CK(clk), .RN(n1738), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n742), .CK(clk), .RN(n1135), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n741), .CK(clk), .RN(n1739), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n740), .CK(clk), .RN(n1136), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n739), .CK(clk), .RN(n1134), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n738), .CK(clk), .RN(n1139), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n737), .CK(clk), .RN(n1138), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n736), .CK(clk), .RN(n1735), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n735), .CK(clk), .RN(n1138), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n734), .CK(clk), .RN(n1736), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n733), .CK(clk), .RN(n1139), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n732), .CK(clk), .RN(n1134), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n731), .CK(clk), .RN(n1735), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n725), .CK(clk), .RN(n1138), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n724), .CK(clk), .RN(n1736), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n723), .CK(clk), .RN(n1737), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n722), .CK(clk), .RN(n1737), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n721), .CK(clk), .RN(n1737), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n720), .CK(clk), .RN(n1737), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n719), .CK(clk), .RN(n1737), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n718), .CK(clk), .RN(n1737), .Q(
DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n716), .CK(clk), .RN(n1737), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n715), .CK(clk), .RN(n1737), .Q(
DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n713), .CK(clk), .RN(n1735), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n712), .CK(clk), .RN(n1736), .Q(
DMP_SHT2_EWSW[2]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_2_ ( .D(n711), .CK(clk), .RN(n1738), .Q(
DMP_SFG[2]), .QN(n1700) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n710), .CK(clk), .RN(n1138), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n709), .CK(clk), .RN(n1135), .Q(
DMP_SHT2_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n707), .CK(clk), .RN(n1739), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n706), .CK(clk), .RN(n1136), .Q(
DMP_SHT2_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n704), .CK(clk), .RN(n1134), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n703), .CK(clk), .RN(n1736), .Q(
DMP_SHT2_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n701), .CK(clk), .RN(n1738), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n700), .CK(clk), .RN(n1138), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n698), .CK(clk), .RN(n1135), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n697), .CK(clk), .RN(n1739), .Q(
DMP_SHT2_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n695), .CK(clk), .RN(n1136), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n694), .CK(clk), .RN(n1134), .Q(
DMP_SHT2_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n692), .CK(clk), .RN(n1139), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n691), .CK(clk), .RN(n1138), .Q(
DMP_SHT2_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n689), .CK(clk), .RN(n1740), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n688), .CK(clk), .RN(n1740), .Q(
DMP_SHT2_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n686), .CK(clk), .RN(n1740), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n685), .CK(clk), .RN(n1740), .Q(
DMP_SHT2_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n683), .CK(clk), .RN(n1740), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n682), .CK(clk), .RN(n1740), .Q(
DMP_SHT2_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n680), .CK(clk), .RN(n1740), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n679), .CK(clk), .RN(n1740), .Q(
DMP_SHT2_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n677), .CK(clk), .RN(n1740), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n676), .CK(clk), .RN(n1740), .Q(
DMP_SHT2_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n674), .CK(clk), .RN(n1741), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n673), .CK(clk), .RN(n1741), .Q(
DMP_SHT2_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n671), .CK(clk), .RN(n1741), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n670), .CK(clk), .RN(n1741), .Q(
DMP_SHT2_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n668), .CK(clk), .RN(n1741), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n667), .CK(clk), .RN(n1741), .Q(
DMP_SHT2_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n665), .CK(clk), .RN(n1741), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n664), .CK(clk), .RN(n1741), .Q(
DMP_SHT2_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n662), .CK(clk), .RN(n1741), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n661), .CK(clk), .RN(n1741), .Q(
DMP_SHT2_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n659), .CK(clk), .RN(n1742), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n658), .CK(clk), .RN(n1742), .Q(
DMP_SHT2_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n656), .CK(clk), .RN(n1742), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n655), .CK(clk), .RN(n1742), .Q(
DMP_SHT2_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n653), .CK(clk), .RN(n1742), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n652), .CK(clk), .RN(n1742), .Q(
DMP_SHT2_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n650), .CK(clk), .RN(n1742), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n649), .CK(clk), .RN(n1742), .Q(
DMP_SHT2_EWSW[23]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_23_ ( .D(n648), .CK(clk), .RN(n1742), .Q(
DMP_SFG[23]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n647), .CK(clk), .RN(n1742), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n645), .CK(clk), .RN(n1743), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n644), .CK(clk), .RN(n1743), .Q(
DMP_SHT2_EWSW[24]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_24_ ( .D(n643), .CK(clk), .RN(n1743), .Q(
DMP_SFG[24]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n642), .CK(clk), .RN(n1743), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n640), .CK(clk), .RN(n1743), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n639), .CK(clk), .RN(n1743), .Q(
DMP_SHT2_EWSW[25]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_25_ ( .D(n638), .CK(clk), .RN(n1743), .Q(
DMP_SFG[25]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n637), .CK(clk), .RN(n1743), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n635), .CK(clk), .RN(n1743), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n634), .CK(clk), .RN(n1743), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_26_ ( .D(n633), .CK(clk), .RN(n1744), .Q(
DMP_SFG[26]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n632), .CK(clk), .RN(n1744), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n630), .CK(clk), .RN(n1744), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n629), .CK(clk), .RN(n1744), .Q(
DMP_SHT2_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_27_ ( .D(n628), .CK(clk), .RN(n1744), .Q(
DMP_SFG[27]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n627), .CK(clk), .RN(n1744), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n625), .CK(clk), .RN(n1744), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n624), .CK(clk), .RN(n1744), .Q(
DMP_SHT2_EWSW[28]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_28_ ( .D(n623), .CK(clk), .RN(n1744), .Q(
DMP_SFG[28]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n622), .CK(clk), .RN(n1744), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n620), .CK(clk), .RN(n1745), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n619), .CK(clk), .RN(n1745), .Q(
DMP_SHT2_EWSW[29]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_29_ ( .D(n618), .CK(clk), .RN(n1745), .Q(
DMP_SFG[29]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n617), .CK(clk), .RN(n1745), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n615), .CK(clk), .RN(n1745), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n614), .CK(clk), .RN(n1745), .Q(
DMP_SHT2_EWSW[30]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_30_ ( .D(n613), .CK(clk), .RN(n1745), .Q(
DMP_SFG[30]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n612), .CK(clk), .RN(n1745), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n610), .CK(clk), .RN(n1745), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n609), .CK(clk), .RN(n1745), .Q(
DmP_mant_SHT1_SW[0]), .QN(n1715) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n608), .CK(clk), .RN(n1746), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n606), .CK(clk), .RN(n1746), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n604), .CK(clk), .RN(n1746), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n602), .CK(clk), .RN(n1746), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n600), .CK(clk), .RN(n1746), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n598), .CK(clk), .RN(n1747), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n596), .CK(clk), .RN(n1747), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n594), .CK(clk), .RN(n1747), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n592), .CK(clk), .RN(n1747), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n590), .CK(clk), .RN(n1747), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n588), .CK(clk), .RN(n1748), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n586), .CK(clk), .RN(n1748), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n584), .CK(clk), .RN(n1748), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n582), .CK(clk), .RN(n1748), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n580), .CK(clk), .RN(n1748), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n578), .CK(clk), .RN(n1749), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n576), .CK(clk), .RN(n1749), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n574), .CK(clk), .RN(n1749), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n572), .CK(clk), .RN(n1749), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n570), .CK(clk), .RN(n1749), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n568), .CK(clk), .RN(n1750), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n566), .CK(clk), .RN(n1750), .Q(
DmP_EXP_EWSW[22]) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n557), .CK(clk), .RN(n1751), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n556), .CK(clk), .RN(n1751), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n555), .CK(clk), .RN(n1751), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n554), .CK(clk), .RN(n1751), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n553), .CK(clk), .RN(n1751), .Q(
ZERO_FLAG_SHT1SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n551), .CK(clk), .RN(n1751), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n1716), .CK(clk), .RN(n1763), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n548), .CK(clk), .RN(n1751), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n547), .CK(clk), .RN(n1751), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n546), .CK(clk), .RN(n1751), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n545), .CK(clk), .RN(n1752), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n544), .CK(clk), .RN(n1752), .Q(
SIGN_FLAG_SHT1SHT2) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n527), .CK(clk), .RN(n1759), .Q(
Raw_mant_NRM_SWR[15]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n526), .CK(clk), .RN(n1759), .Q(
Raw_mant_NRM_SWR[16]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n524), .CK(clk), .RN(n1759), .Q(
Raw_mant_NRM_SWR[18]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n516), .CK(clk), .RN(n1757), .Q(
LZD_output_NRM2_EW[3]), .QN(n1663) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n514), .CK(clk), .RN(n1757), .Q(
LZD_output_NRM2_EW[2]), .QN(n1665) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n513), .CK(clk), .RN(n1757), .Q(
LZD_output_NRM2_EW[1]), .QN(n1664) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n512), .CK(clk), .RN(n1757), .Q(
LZD_output_NRM2_EW[4]), .QN(n1671) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n488), .CK(clk), .RN(n1755), .Q(
DmP_mant_SFG_SWR[0]), .QN(n922) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n487), .CK(clk), .RN(n1755), .Q(
DmP_mant_SFG_SWR[1]), .QN(n923) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n484), .CK(clk), .RN(n1755), .Q(
DmP_mant_SFG_SWR[4]), .QN(n1673) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n483), .CK(clk), .RN(n1755), .Q(
DmP_mant_SFG_SWR[5]), .QN(n1666) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n482), .CK(clk), .RN(n1755), .Q(
DmP_mant_SFG_SWR[6]), .QN(n1672) );
CMPR32X2TS intadd_21_U4 ( .A(n1700), .B(intadd_21_B_0_), .C(intadd_21_CI),
.CO(intadd_21_n3), .S(intadd_21_SUM_0_) );
CMPR32X2TS intadd_21_U3 ( .A(n1710), .B(intadd_21_B_1_), .C(intadd_21_n3),
.CO(intadd_21_n2), .S(intadd_21_SUM_1_) );
CMPR32X2TS intadd_21_U2 ( .A(n1711), .B(intadd_21_B_2_), .C(intadd_21_n2),
.CO(intadd_21_n1), .S(intadd_21_SUM_2_) );
AFCSIHCONX2TS DP_OP_285J28_122_2126_U78 ( .A(DMP_SFG[8]), .B(
DmP_mant_SFG_SWR_signed[10]), .CS(DP_OP_285J28_122_2126_n74), .CO0N(
DP_OP_285J28_122_2126_n73), .CO1N(DP_OP_285J28_122_2126_n72) );
AFCSHCINX2TS DP_OP_285J28_122_2126_U77 ( .CI1N(DP_OP_285J28_122_2126_n72),
.B(DmP_mant_SFG_SWR_signed[11]), .A(DMP_SFG[9]), .CI0N(
DP_OP_285J28_122_2126_n73), .CS(DP_OP_285J28_122_2126_n74), .CO1(
DP_OP_285J28_122_2126_n70), .CO0(DP_OP_285J28_122_2126_n71) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n1728),
.Q(ready) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n559), .CK(clk), .RN(n1750), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n552), .CK(clk), .RN(n1751), .Q(
zero_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n505), .CK(clk), .RN(n1753), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n503), .CK(clk), .RN(n1753), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n558), .CK(clk), .RN(n1755), .Q(
overflow_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n754), .CK(clk), .RN(n1756), .Q(
final_result_ieee[30]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n543), .CK(clk), .RN(n1756), .Q(
final_result_ieee[31]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n761), .CK(clk), .RN(n1756), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n760), .CK(clk), .RN(n1756), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n759), .CK(clk), .RN(n1756), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n758), .CK(clk), .RN(n1756), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n757), .CK(clk), .RN(n1756), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n756), .CK(clk), .RN(n1756), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n755), .CK(clk), .RN(n1756), .Q(
final_result_ieee[29]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n530), .CK(clk), .RN(n1758), .Q(
Raw_mant_NRM_SWR[12]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n528), .CK(clk), .RN(n1759), .Q(
Raw_mant_NRM_SWR[14]), .QN(n1659) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n827), .CK(clk), .RN(n1728), .Q(
intDY_EWSW[1]), .QN(n1765) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n539), .CK(clk), .RN(n1752), .Q(
Raw_mant_NRM_SWR[3]), .QN(n1647) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n1724), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n1640) );
DFFRX2TS inst_ShiftRegister_Q_reg_5_ ( .D(n868), .CK(clk), .RN(n1724), .Q(
n1636), .QN(n1714) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n858), .CK(clk), .RN(n1725), .Q(
intDX_EWSW[4]), .QN(n1637) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n536), .CK(clk), .RN(n1752), .Q(
Raw_mant_NRM_SWR[6]), .QN(n1702) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n838), .CK(clk), .RN(n1727),
.Q(intDX_EWSW[24]), .QN(n1707) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n837), .CK(clk), .RN(n1727),
.Q(intDX_EWSW[25]), .QN(n1649) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n808), .CK(clk), .RN(n1730),
.Q(intDY_EWSW[20]), .QN(n1688) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n814), .CK(clk), .RN(n1729),
.Q(intDY_EWSW[14]), .QN(n1686) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n815), .CK(clk), .RN(n1729),
.Q(intDY_EWSW[13]), .QN(n1680) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n816), .CK(clk), .RN(n1729),
.Q(intDY_EWSW[12]), .QN(n1685) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n810), .CK(clk), .RN(n1730),
.Q(intDY_EWSW[18]), .QN(n1694) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n811), .CK(clk), .RN(n1730),
.Q(intDY_EWSW[17]), .QN(n1678) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n813), .CK(clk), .RN(n1729),
.Q(intDY_EWSW[15]), .QN(n1643) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n817), .CK(clk), .RN(n1729),
.Q(intDY_EWSW[11]), .QN(n1660) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n820), .CK(clk), .RN(n1729), .Q(
intDY_EWSW[8]), .QN(n1682) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n825), .CK(clk), .RN(n1728), .Q(
intDY_EWSW[3]), .QN(n1677) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n805), .CK(clk), .RN(n1730),
.Q(intDY_EWSW[23]), .QN(n1691) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n806), .CK(clk), .RN(n1730),
.Q(intDY_EWSW[22]), .QN(n1644) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n807), .CK(clk), .RN(n1730),
.Q(intDY_EWSW[21]), .QN(n1681) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n798), .CK(clk), .RN(n1731),
.Q(intDY_EWSW[30]), .QN(n1692) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n799), .CK(clk), .RN(n1731),
.Q(intDY_EWSW[29]), .QN(n1645) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n802), .CK(clk), .RN(n1731),
.Q(intDY_EWSW[26]), .QN(n1689) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n803), .CK(clk), .RN(n1730),
.Q(intDY_EWSW[25]), .QN(n1676) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n846), .CK(clk), .RN(n1726),
.Q(intDX_EWSW[16]), .QN(n1656) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n855), .CK(clk), .RN(n1725), .Q(
intDX_EWSW[7]), .QN(n1638) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n856), .CK(clk), .RN(n1725), .Q(
intDX_EWSW[6]), .QN(n1657) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n857), .CK(clk), .RN(n1725), .Q(
intDX_EWSW[5]), .QN(n1651) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n525), .CK(clk), .RN(n1759), .Q(
Raw_mant_NRM_SWR[17]), .QN(n1674) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n796), .CK(clk), .RN(n1731), .Q(
Data_array_SWR[25]), .QN(n1720) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n795), .CK(clk), .RN(n1731), .Q(
Data_array_SWR[24]), .QN(n1721) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n509), .CK(clk), .RN(n1753), .Q(
final_result_ieee[9]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n520), .CK(clk), .RN(n1759), .Q(
Raw_mant_NRM_SWR[22]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n517), .CK(clk), .RN(n1759), .Q(
Raw_mant_NRM_SWR[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n497), .CK(clk), .RN(n1754), .Q(
final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n506), .CK(clk), .RN(n1753), .Q(
final_result_ieee[13]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n542), .CK(clk), .RN(n1758), .Q(
Raw_mant_NRM_SWR[0]), .QN(n1639) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n826), .CK(clk), .RN(n1728), .Q(
intDY_EWSW[2]), .QN(n1683) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n788), .CK(clk), .RN(n1732), .Q(
Data_array_SWR[17]), .QN(n1719) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n859), .CK(clk), .RN(n1725), .Q(
intDX_EWSW[3]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n839), .CK(clk), .RN(n1727),
.Q(intDX_EWSW[23]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n847), .CK(clk), .RN(n1726),
.Q(intDX_EWSW[15]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n841), .CK(clk), .RN(n1727),
.Q(intDX_EWSW[21]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n849), .CK(clk), .RN(n1726),
.Q(intDX_EWSW[13]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n767), .CK(clk), .RN(n1734), .Q(
shift_value_SHT2_EWR[4]), .QN(n882) );
DFFRX2TS inst_ShiftRegister_Q_reg_0_ ( .D(n863), .CK(clk), .RN(n1724), .Q(
Shift_reg_FLAGS_7[0]), .QN(n1701) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n845), .CK(clk), .RN(n1726),
.Q(intDX_EWSW[17]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n793), .CK(clk), .RN(n1732), .Q(
Data_array_SWR[22]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n533), .CK(clk), .RN(n1758), .Q(
Raw_mant_NRM_SWR[9]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n854), .CK(clk), .RN(n1725), .Q(
intDX_EWSW[8]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n851), .CK(clk), .RN(n1726),
.Q(intDX_EWSW[11]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n532), .CK(clk), .RN(n1758), .Q(
Raw_mant_NRM_SWR[10]), .QN(n881) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n861), .CK(clk), .RN(n1725), .Q(
intDX_EWSW[1]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n853), .CK(clk), .RN(n1725), .Q(
intDX_EWSW[9]) );
DFFRX4TS inst_ShiftRegister_Q_reg_4_ ( .D(n867), .CK(clk), .RN(n1724), .Q(
busy), .QN(n1764) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n770), .CK(clk), .RN(n1731), .Q(
shift_value_SHT2_EWR[2]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n844), .CK(clk), .RN(n1726),
.Q(intDX_EWSW[18]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n794), .CK(clk), .RN(n1732), .Q(
Data_array_SWR[23]), .QN(n1703) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n786), .CK(clk), .RN(n1732), .Q(
Data_array_SWR[15]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n833), .CK(clk), .RN(n1727),
.Q(intDX_EWSW[29]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n871), .CK(clk), .RN(
n1724), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n843), .CK(clk), .RN(n1726),
.Q(intDX_EWSW[19]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n835), .CK(clk), .RN(n1727),
.Q(intDX_EWSW[27]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n785), .CK(clk), .RN(n1732), .Q(
Data_array_SWR[14]), .QN(n1706) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n783), .CK(clk), .RN(n1733), .Q(
Data_array_SWR[12]), .QN(n1705) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n538), .CK(clk), .RN(n1752), .Q(
Raw_mant_NRM_SWR[4]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n780), .CK(clk), .RN(n1733), .Q(
Data_array_SWR[9]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_7_ ( .D(n696), .CK(clk), .RN(n1763), .Q(
DMP_SFG[7]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n777), .CK(clk), .RN(n1733), .Q(
Data_array_SWR[6]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n778), .CK(clk), .RN(n1733), .Q(
Data_array_SWR[7]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n775), .CK(clk), .RN(n1733), .Q(
Data_array_SWR[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n776), .CK(clk), .RN(n1733), .Q(
Data_array_SWR[5]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n831), .CK(clk), .RN(n1728),
.Q(intDX_EWSW[31]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_5_ ( .D(n702), .CK(clk), .RN(n1135), .Q(
DMP_SFG[5]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n714), .CK(clk), .RN(n1737), .Q(
DMP_SFG[1]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_8_ ( .D(n693), .CK(clk), .RN(n1763), .Q(
DMP_SFG[8]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_11_ ( .D(n684), .CK(clk), .RN(n1763), .Q(
DMP_SFG[11]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_18_ ( .D(n663), .CK(clk), .RN(n1761), .Q(
DMP_SFG[18]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_16_ ( .D(n669), .CK(clk), .RN(n1761), .Q(
DMP_SFG[16]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_9_ ( .D(n690), .CK(clk), .RN(n1763), .Q(
DMP_SFG[9]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_6_ ( .D(n699), .CK(clk), .RN(n1763), .Q(
DMP_SFG[6]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_14_ ( .D(n675), .CK(clk), .RN(n1761), .Q(
DMP_SFG[14]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n575), .CK(clk), .RN(n1749), .Q(
DmP_mant_SHT1_SW[17]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_17_ ( .D(n666), .CK(clk), .RN(n1761), .Q(
DMP_SFG[17]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_15_ ( .D(n672), .CK(clk), .RN(n1761), .Q(
DMP_SFG[15]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n765), .CK(clk), .RN(n1734),
.Q(Shift_amount_SHT1_EWR[1]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_21_ ( .D(n654), .CK(clk), .RN(n1761), .Q(
DMP_SFG[21]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_13_ ( .D(n678), .CK(clk), .RN(n1763), .Q(
DMP_SFG[13]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n626), .CK(clk), .RN(n1757), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n631), .CK(clk), .RN(n1757), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n636), .CK(clk), .RN(n1757), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n641), .CK(clk), .RN(n1757), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_12_ ( .D(n681), .CK(clk), .RN(n1763), .Q(
DMP_SFG[12]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_10_ ( .D(n687), .CK(clk), .RN(n1763), .Q(
DMP_SFG[10]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_22_ ( .D(n651), .CK(clk), .RN(n1762), .Q(
DMP_SFG[22]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_20_ ( .D(n657), .CK(clk), .RN(n1761), .Q(
DMP_SFG[20]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_19_ ( .D(n660), .CK(clk), .RN(n1761), .Q(
DMP_SFG[19]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_26_ ( .D(n561), .CK(clk), .RN(n1750), .Q(
DmP_EXP_EWSW[26]), .QN(n889) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n478), .CK(clk), .RN(n1762), .Q(
DmP_mant_SFG_SWR[10]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n468), .CK(clk), .RN(n1760), .Q(
DmP_mant_SFG_SWR[20]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n470), .CK(clk), .RN(n1760), .Q(
DmP_mant_SFG_SWR[18]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n479), .CK(clk), .RN(n1762), .Q(
DmP_mant_SFG_SWR[9]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n480), .CK(clk), .RN(n1762), .Q(
DmP_mant_SFG_SWR[8]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n717), .CK(clk), .RN(n1737), .Q(
DMP_SFG[0]), .QN(n886) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n797), .CK(clk), .RN(n1731),
.Q(intDY_EWSW[31]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n473), .CK(clk), .RN(n1762), .Q(
DmP_mant_SFG_SWR[15]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n474), .CK(clk), .RN(n1762), .Q(
DmP_mant_SFG_SWR[14]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n475), .CK(clk), .RN(n1762), .Q(
DmP_mant_SFG_SWR[13]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n476), .CK(clk), .RN(n1762), .Q(
DmP_mant_SFG_SWR[12]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n477), .CK(clk), .RN(n1762), .Q(
DmP_mant_SFG_SWR[11]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n463), .CK(clk), .RN(n1761), .Q(
DmP_mant_SFG_SWR[25]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n464), .CK(clk), .RN(n1761), .Q(
DmP_mant_SFG_SWR[24]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n465), .CK(clk), .RN(n1760), .Q(
DmP_mant_SFG_SWR[23]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n466), .CK(clk), .RN(n1760), .Q(
DmP_mant_SFG_SWR[22]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n467), .CK(clk), .RN(n1760), .Q(
DmP_mant_SFG_SWR[21]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n469), .CK(clk), .RN(n1760), .Q(
DmP_mant_SFG_SWR[19]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n471), .CK(clk), .RN(n1760), .Q(
DmP_mant_SFG_SWR[17]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n472), .CK(clk), .RN(n1760), .Q(
DmP_mant_SFG_SWR[16]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n850), .CK(clk), .RN(n1726),
.Q(intDX_EWSW[12]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n842), .CK(clk), .RN(n1726),
.Q(intDX_EWSW[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n848), .CK(clk), .RN(n1726),
.Q(intDX_EWSW[14]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n840), .CK(clk), .RN(n1727),
.Q(intDX_EWSW[22]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n860), .CK(clk), .RN(n1725), .Q(
intDX_EWSW[2]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n784), .CK(clk), .RN(n1733), .Q(
Data_array_SWR[13]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n832), .CK(clk), .RN(n1727),
.Q(intDX_EWSW[30]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n852), .CK(clk), .RN(n1725),
.Q(intDX_EWSW[10]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n862), .CK(clk), .RN(n1724), .Q(
intDX_EWSW[0]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n782), .CK(clk), .RN(n1733), .Q(
Data_array_SWR[11]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n790), .CK(clk), .RN(n1732), .Q(
Data_array_SWR[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n789), .CK(clk), .RN(n1732), .Q(
Data_array_SWR[18]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n779), .CK(clk), .RN(n1733), .Q(
Data_array_SWR[8]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n781), .CK(clk), .RN(n1733), .Q(
Data_array_SWR[10]), .QN(n1713) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n603), .CK(clk), .RN(n1746), .Q(
DmP_mant_SHT1_SW[3]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n593), .CK(clk), .RN(n1747), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n589), .CK(clk), .RN(n1747), .Q(
DmP_mant_SHT1_SW[10]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n585), .CK(clk), .RN(n1748), .Q(
DmP_mant_SHT1_SW[12]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n565), .CK(clk), .RN(n1750), .Q(
DmP_mant_SHT1_SW[22]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n579), .CK(clk), .RN(n1748), .Q(
DmP_mant_SHT1_SW[15]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_27_ ( .D(n726), .CK(clk), .RN(n1739), .Q(
DMP_EXP_EWSW[27]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_25_ ( .D(n728), .CK(clk), .RN(n1136), .Q(
DMP_EXP_EWSW[25]), .QN(n924) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n607), .CK(clk), .RN(n1746), .Q(
DmP_mant_SHT1_SW[1]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n599), .CK(clk), .RN(n1746), .Q(
DmP_mant_SHT1_SW[5]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_24_ ( .D(n729), .CK(clk), .RN(n1134), .Q(
DMP_EXP_EWSW[24]), .QN(n1648) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_26_ ( .D(n727), .CK(clk), .RN(n1139), .Q(
DMP_EXP_EWSW[26]), .QN(n1650) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n567), .CK(clk), .RN(n1750), .Q(
DmP_mant_SHT1_SW[21]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n605), .CK(clk), .RN(n1746), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n597), .CK(clk), .RN(n1747), .Q(
DmP_mant_SHT1_SW[6]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n591), .CK(clk), .RN(n1747), .Q(
DmP_mant_SHT1_SW[9]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n587), .CK(clk), .RN(n1748), .Q(
DmP_mant_SHT1_SW[11]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n571), .CK(clk), .RN(n1749), .Q(
DmP_mant_SHT1_SW[19]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n581), .CK(clk), .RN(n1748), .Q(
DmP_mant_SHT1_SW[14]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n601), .CK(clk), .RN(n1746), .Q(
DmP_mant_SHT1_SW[4]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n583), .CK(clk), .RN(n1748), .Q(
DmP_mant_SHT1_SW[13]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n573), .CK(clk), .RN(n1749), .Q(
DmP_mant_SHT1_SW[18]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n595), .CK(clk), .RN(n1747), .Q(
DmP_mant_SHT1_SW[7]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n577), .CK(clk), .RN(n1749), .Q(
DmP_mant_SHT1_SW[16]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n569), .CK(clk), .RN(n1749), .Q(
DmP_mant_SHT1_SW[20]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n766), .CK(clk), .RN(n1734),
.Q(Shift_amount_SHT1_EWR[0]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_23_ ( .D(n564), .CK(clk), .RN(n1750), .Q(
DmP_EXP_EWSW[23]), .QN(n925) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_24_ ( .D(n563), .CK(clk), .RN(n1750), .Q(
DmP_EXP_EWSW[24]), .QN(n887) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n774), .CK(clk), .RN(n1734), .Q(
Data_array_SWR[3]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n773), .CK(clk), .RN(n1734), .Q(
Data_array_SWR[2]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n772), .CK(clk), .RN(n1734), .Q(
Data_array_SWR[1]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_27_ ( .D(n560), .CK(clk), .RN(n1750), .Q(
DmP_EXP_EWSW[27]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_25_ ( .D(n562), .CK(clk), .RN(n1750), .Q(
DmP_EXP_EWSW[25]), .QN(n1708) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n771), .CK(clk), .RN(n1734), .Q(
Data_array_SWR[0]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n515), .CK(clk), .RN(n1756), .Q(
LZD_output_NRM2_EW[0]), .QN(n878) );
DFFRX1TS inst_ShiftRegister_Q_reg_1_ ( .D(n864), .CK(clk), .RN(n1724), .Q(
Shift_reg_FLAGS_7[1]), .QN(n877) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n523), .CK(clk), .RN(n1760), .Q(
Raw_mant_NRM_SWR[19]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n522), .CK(clk), .RN(n1759), .Q(
Raw_mant_NRM_SWR[20]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n521), .CK(clk), .RN(n1760), .Q(
Raw_mant_NRM_SWR[21]), .QN(n1675) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n519), .CK(clk), .RN(n1759), .Q(
Raw_mant_NRM_SWR[23]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n529), .CK(clk), .RN(n1758), .Q(
Raw_mant_NRM_SWR[13]), .QN(n1704) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n531), .CK(clk), .RN(n1758), .Q(
Raw_mant_NRM_SWR[11]), .QN(n1633) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n504), .CK(clk), .RN(n1753), .Q(
final_result_ieee[14]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n502), .CK(clk), .RN(n1753), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n501), .CK(clk), .RN(n1753), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n500), .CK(clk), .RN(n1753), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n499), .CK(clk), .RN(n1754), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n498), .CK(clk), .RN(n1754), .Q(
final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n496), .CK(clk), .RN(n1754), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n495), .CK(clk), .RN(n1754), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n494), .CK(clk), .RN(n1754), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n493), .CK(clk), .RN(n1754), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n492), .CK(clk), .RN(n1754), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n491), .CK(clk), .RN(n1754), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n490), .CK(clk), .RN(n1754), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n489), .CK(clk), .RN(n1755), .Q(
final_result_ieee[22]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n510), .CK(clk), .RN(n1752), .Q(
final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n508), .CK(clk), .RN(n1753), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n507), .CK(clk), .RN(n1753), .Q(
final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n511), .CK(clk), .RN(n1752), .Q(
final_result_ieee[10]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n611), .CK(clk), .RN(n1758), .Q(
DMP_exp_NRM2_EW[7]), .QN(n1699) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n616), .CK(clk), .RN(n1758), .Q(
DMP_exp_NRM2_EW[6]), .QN(n1698) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n621), .CK(clk), .RN(n1757), .Q(
DMP_exp_NRM2_EW[5]), .QN(n1670) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n646), .CK(clk), .RN(n1757), .Q(
DMP_exp_NRM2_EW[0]), .QN(n1662) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n541), .CK(clk), .RN(n1758), .Q(
Raw_mant_NRM_SWR[1]), .QN(n1709) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n870), .CK(clk), .RN(
n1724), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n1669) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n540), .CK(clk), .RN(n1752), .Q(
Raw_mant_NRM_SWR[2]), .QN(n1634) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n537), .CK(clk), .RN(n1752), .Q(
Raw_mant_NRM_SWR[5]), .QN(n1654) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_4_ ( .D(n705), .CK(clk), .RN(n1138), .Q(
DMP_SFG[4]), .QN(n1711) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_3_ ( .D(n708), .CK(clk), .RN(n1736), .Q(
DMP_SFG[3]), .QN(n1710) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n769), .CK(clk), .RN(n1731), .Q(
shift_value_SHT2_EWR[3]), .QN(n1652) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n821), .CK(clk), .RN(n1729), .Q(
intDY_EWSW[7]), .QN(n1668) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n836), .CK(clk), .RN(n1727),
.Q(intDX_EWSW[26]), .QN(n1712) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n809), .CK(clk), .RN(n1730),
.Q(intDY_EWSW[19]), .QN(n1646) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n818), .CK(clk), .RN(n1729),
.Q(intDY_EWSW[10]), .QN(n1653) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n828), .CK(clk), .RN(n1728), .Q(
intDY_EWSW[0]), .QN(n1642) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n819), .CK(clk), .RN(n1729), .Q(
intDY_EWSW[9]), .QN(n1679) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n812), .CK(clk), .RN(n1730),
.Q(intDY_EWSW[16]), .QN(n1687) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n822), .CK(clk), .RN(n1729), .Q(
intDY_EWSW[6]), .QN(n1667) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n824), .CK(clk), .RN(n1728), .Q(
intDY_EWSW[4]), .QN(n1684) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n823), .CK(clk), .RN(n1728), .Q(
intDY_EWSW[5]), .QN(n1641) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n834), .CK(clk), .RN(n1727),
.Q(intDX_EWSW[28]), .QN(n1658) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n801), .CK(clk), .RN(n1731),
.Q(intDY_EWSW[27]), .QN(n1693) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n804), .CK(clk), .RN(n1730),
.Q(intDY_EWSW[24]), .QN(n1635) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n800), .CK(clk), .RN(n1731),
.Q(intDY_EWSW[28]), .QN(n1690) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n535), .CK(clk), .RN(n1752), .Q(
Raw_mant_NRM_SWR[7]), .QN(n1655) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n486), .CK(clk), .RN(n1755), .Q(
DmP_mant_SFG_SWR[2]), .QN(n1696) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n485), .CK(clk), .RN(n1755), .Q(
DmP_mant_SFG_SWR[3]), .QN(n1697) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n481), .CK(clk), .RN(n1755), .Q(
DmP_mant_SFG_SWR[7]), .QN(n1695) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n787), .CK(clk), .RN(n1732), .Q(
Data_array_SWR[16]), .QN(n1723) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n791), .CK(clk), .RN(n1732), .Q(
Data_array_SWR[20]), .QN(n1722) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n534), .CK(clk), .RN(n1758), .Q(
Raw_mant_NRM_SWR[8]), .QN(n1632) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n792), .CK(clk), .RN(n1732), .Q(
Data_array_SWR[21]), .QN(n1718) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_23_ ( .D(n730), .CK(clk), .RN(n1738), .Q(
DMP_EXP_EWSW[23]) );
DFFRX2TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n549), .CK(clk), .RN(n1762), .Q(n873),
.QN(n1661) );
ADDFX1TS DP_OP_15J28_123_3372_U7 ( .A(n1665), .B(DMP_exp_NRM2_EW[2]), .CI(
DP_OP_15J28_123_3372_n7), .CO(DP_OP_15J28_123_3372_n6), .S(
exp_rslt_NRM2_EW1[2]) );
ADDFX1TS DP_OP_15J28_123_3372_U6 ( .A(n1663), .B(DMP_exp_NRM2_EW[3]), .CI(
DP_OP_15J28_123_3372_n6), .CO(DP_OP_15J28_123_3372_n5), .S(
exp_rslt_NRM2_EW1[3]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n518), .CK(clk), .RN(n1759), .Q(
Raw_mant_NRM_SWR[24]) );
CMPR32X2TS DP_OP_15J28_123_3372_U8 ( .A(n1664), .B(DMP_exp_NRM2_EW[1]), .C(
DP_OP_15J28_123_3372_n8), .CO(DP_OP_15J28_123_3372_n7), .S(
exp_rslt_NRM2_EW1[1]) );
CMPR32X2TS DP_OP_15J28_123_3372_U5 ( .A(n1671), .B(DMP_exp_NRM2_EW[4]), .C(
DP_OP_15J28_123_3372_n5), .CO(DP_OP_15J28_123_3372_n4), .S(
exp_rslt_NRM2_EW1[4]) );
OAI221X1TS U897 ( .A0(n906), .A1(n1394), .B0(n905), .B1(n1393), .C0(n1392),
.Y(n1589) );
AOI222X1TS U898 ( .A0(n1601), .A1(n888), .B0(Data_array_SWR[6]), .B1(n904),
.C0(n1600), .C1(n1604), .Y(n1628) );
OAI2BB2XLTS U899 ( .B0(n1339), .B1(n909), .A0N(Raw_mant_NRM_SWR[16]), .A1N(
n1353), .Y(n966) );
CMPR32X2TS U900 ( .A(DMP_SFG[8]), .B(DmP_mant_SFG_SWR_signed[10]), .C(n1477),
.CO(n1471), .S(n1478) );
AOI222X4TS U901 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n897), .B0(n918), .B1(
DmP_mant_SHT1_SW[19]), .C0(n1313), .C1(DmP_mant_SHT1_SW[20]), .Y(n1376) );
AOI222X4TS U902 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n897), .B0(n917), .B1(
DmP_mant_SHT1_SW[20]), .C0(n1360), .C1(DmP_mant_SHT1_SW[21]), .Y(n1379) );
AOI222X4TS U903 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n897), .B0(n918), .B1(
DmP_mant_SHT1_SW[16]), .C0(n1313), .C1(DmP_mant_SHT1_SW[17]), .Y(n1306) );
AND2X2TS U904 ( .A(beg_OP), .B(n1509), .Y(n1514) );
AOI211X1TS U905 ( .A0(DmP_mant_SHT1_SW[22]), .A1(n914), .B0(n1527), .C0(
n1114), .Y(n1380) );
CMPR32X2TS U906 ( .A(DMP_SFG[7]), .B(n1483), .C(n1482), .CO(n1477), .S(n1484) );
INVX2TS U907 ( .A(n896), .Y(n897) );
INVX2TS U908 ( .A(n883), .Y(n874) );
CMPR32X2TS U909 ( .A(DMP_SFG[6]), .B(n1480), .C(n1479), .CO(n1482), .S(n1481) );
INVX2TS U910 ( .A(n1567), .Y(n1243) );
AOI32X1TS U911 ( .A0(n1057), .A1(n1056), .A2(n1055), .B0(n1054), .B1(n1057),
.Y(n1058) );
NAND3X1TS U912 ( .A(shift_value_SHT2_EWR[2]), .B(n882), .C(
shift_value_SHT2_EWR[3]), .Y(n883) );
BUFX3TS U913 ( .A(Shift_reg_FLAGS_7_6), .Y(n1567) );
NAND2X1TS U914 ( .A(n1698), .B(n1066), .Y(n1092) );
INVX2TS U915 ( .A(n905), .Y(n906) );
INVX2TS U916 ( .A(n1401), .Y(n905) );
NAND2X1TS U917 ( .A(n1670), .B(n1061), .Y(n1065) );
INVX2TS U918 ( .A(n914), .Y(n915) );
NAND2X2TS U919 ( .A(n914), .B(n894), .Y(n1540) );
CMPR32X2TS U920 ( .A(n1462), .B(DMP_SFG[11]), .C(n1461), .CO(n1458), .S(
n1463) );
NAND2X2TS U921 ( .A(n1490), .B(n1218), .Y(n1222) );
CMPR32X2TS U922 ( .A(n1475), .B(DMP_SFG[10]), .C(n1474), .CO(n1461), .S(
n1476) );
BUFX3TS U923 ( .A(Shift_reg_FLAGS_7[1]), .Y(n1576) );
CMPR32X2TS U924 ( .A(n1483), .B(DMP_SFG[7]), .C(n977), .CO(
DP_OP_285J28_122_2126_n74) );
NOR3X1TS U925 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[15]), .C(
Raw_mant_NRM_SWR[16]), .Y(n1118) );
OAI211XLTS U926 ( .A0(n1677), .A1(intDX_EWSW[3]), .B0(n1024), .C0(n1023),
.Y(n1027) );
OAI21XLTS U927 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n935), .B0(n934), .Y(n936)
);
AOI31XLTS U928 ( .A0(n941), .A1(Raw_mant_NRM_SWR[16]), .A2(n1674), .B0(n936),
.Y(n937) );
OAI21XLTS U929 ( .A0(intDX_EWSW[23]), .A1(n1691), .B0(intDX_EWSW[22]), .Y(
n1046) );
OAI211XLTS U930 ( .A0(DMP_SFG[3]), .A1(n1466), .B0(n1464), .C0(DMP_SFG[2]),
.Y(n1465) );
NOR2XLTS U931 ( .A(n1063), .B(n1089), .Y(n1064) );
NOR2XLTS U932 ( .A(DMP_SFG[5]), .B(n1585), .Y(n1469) );
NOR2XLTS U933 ( .A(n1673), .B(n873), .Y(n1198) );
OR2X1TS U934 ( .A(n906), .B(n1127), .Y(n885) );
OAI21XLTS U935 ( .A0(n1654), .A1(n1533), .B0(n968), .Y(n969) );
CLKINVX3TS U936 ( .A(n1555), .Y(n1237) );
NOR2X2TS U937 ( .A(n970), .B(n875), .Y(n1368) );
INVX2TS U938 ( .A(n1090), .Y(n1077) );
CLKINVX3TS U939 ( .A(n1245), .Y(n1568) );
CLKINVX3TS U940 ( .A(n1576), .Y(n914) );
OAI21XLTS U941 ( .A0(n1526), .A1(n908), .B0(n1378), .Y(n792) );
OAI21XLTS U942 ( .A0(n1530), .A1(n910), .B0(n976), .Y(n787) );
OAI21XLTS U943 ( .A0(n1504), .A1(n1060), .B0(n1502), .Y(n870) );
OAI21XLTS U944 ( .A0(n1693), .A1(n1265), .B0(n1252), .Y(n560) );
OAI211XLTS U945 ( .A0(n1343), .A1(n907), .B0(n1342), .C0(n1341), .Y(n773) );
OAI21XLTS U946 ( .A0(n1693), .A1(n1312), .B0(n1285), .Y(n726) );
OAI21XLTS U947 ( .A0(n1537), .A1(n907), .B0(n967), .Y(n779) );
OAI21XLTS U948 ( .A0(n1214), .A1(n1402), .B0(n1213), .Y(n466) );
OAI21XLTS U949 ( .A0(n1596), .A1(n1402), .B0(n1194), .Y(n479) );
OAI211XLTS U950 ( .A0(n1347), .A1(n910), .B0(n1335), .C0(n1334), .Y(n776) );
OAI21XLTS U951 ( .A0(n1634), .A1(n1383), .B0(n1382), .Y(n793) );
OAI211XLTS U952 ( .A0(n1540), .A1(n882), .B0(n1488), .C0(n1226), .Y(n767) );
OAI211XLTS U953 ( .A0(n1069), .A1(n1187), .B0(n1569), .C0(n1068), .Y(n757)
);
OAI21XLTS U954 ( .A0(n1679), .A1(n1261), .B0(n1260), .Y(n592) );
OAI21XLTS U955 ( .A0(n1688), .A1(n1312), .B0(n1305), .Y(n733) );
INVX4TS U956 ( .A(n1661), .Y(n1387) );
OAI21X1TS U957 ( .A0(n1309), .A1(n908), .B0(n1308), .Y(n789) );
OAI211X1TS U958 ( .A0(n1363), .A1(n911), .B0(n1362), .C0(n1361), .Y(n782) );
AOI2BB1X1TS U959 ( .A0N(n1576), .A1N(LZD_output_NRM2_EW[3]), .B0(n1542), .Y(
n516) );
OAI21X1TS U960 ( .A0(n1659), .A1(n875), .B0(n950), .Y(n951) );
OAI21X1TS U961 ( .A0(n1709), .A1(n875), .B0(n1374), .Y(n1375) );
CLKMX2X2TS U962 ( .A(Raw_mant_NRM_SWR[24]), .B(n1432), .S0(n1451), .Y(n518)
);
AO22X1TS U963 ( .A0(n1500), .A1(n1499), .B0(final_result_ieee[30]), .B1(
n1507), .Y(n754) );
AO22X1TS U964 ( .A0(final_result_ieee[10]), .A1(n1610), .B0(n1595), .B1(
n1589), .Y(n511) );
AND2X2TS U965 ( .A(n1499), .B(n1091), .Y(n927) );
INVX4TS U966 ( .A(n1319), .Y(n1566) );
NAND2X4TS U967 ( .A(n1126), .B(n881), .Y(n1219) );
AND2X2TS U968 ( .A(n1699), .B(n1093), .Y(n1094) );
INVX1TS U969 ( .A(n1089), .Y(n1073) );
OAI21X1TS U970 ( .A0(busy), .A1(n1617), .B0(n914), .Y(n829) );
INVX4TS U971 ( .A(n906), .Y(n1617) );
INVX4TS U972 ( .A(n1555), .Y(n1402) );
NOR2X1TS U973 ( .A(n1002), .B(intDY_EWSW[10]), .Y(n1003) );
NOR2X1TS U974 ( .A(n1672), .B(n873), .Y(n1078) );
OAI21X1TS U975 ( .A0(intDX_EWSW[15]), .A1(n1643), .B0(intDX_EWSW[14]), .Y(
n1009) );
OAI21X1TS U976 ( .A0(intDX_EWSW[21]), .A1(n1681), .B0(intDX_EWSW[20]), .Y(
n1039) );
NOR2X1TS U977 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n1385) );
OAI21X1TS U978 ( .A0(n1309), .A1(n911), .B0(n972), .Y(n791) );
OAI211X1TS U979 ( .A0(n1318), .A1(n911), .B0(n1317), .C0(n1316), .Y(n772) );
OAI211X1TS U980 ( .A0(n1339), .A1(n908), .B0(n1338), .C0(n1337), .Y(n777) );
AOI222X1TS U981 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n898), .B0(n918), .B1(
DmP_mant_SHT1_SW[7]), .C0(n1360), .C1(DmP_mant_SHT1_SW[8]), .Y(n1356)
);
OAI21X1TS U982 ( .A0(n1704), .A1(n1533), .B0(n1532), .Y(n1534) );
AND2X2TS U983 ( .A(n965), .B(n1540), .Y(n879) );
OAI21X1TS U984 ( .A0(n1639), .A1(n1222), .B0(n1221), .Y(n1223) );
INVX4TS U985 ( .A(n1531), .Y(n875) );
OAI211X1TS U986 ( .A0(n1495), .A1(n1494), .B0(n1493), .C0(n1492), .Y(n1496)
);
NAND4X1TS U987 ( .A(n1124), .B(n1123), .C(n1221), .D(n1492), .Y(n1125) );
AO22X1TS U988 ( .A0(n1595), .A1(n1590), .B0(final_result_ieee[11]), .B1(
n1701), .Y(n510) );
AO22X1TS U989 ( .A0(n1595), .A1(n1593), .B0(final_result_ieee[8]), .B1(n1610), .Y(n507) );
AO22X1TS U990 ( .A0(n1595), .A1(n1592), .B0(final_result_ieee[12]), .B1(
n1701), .Y(n508) );
AO22X1TS U991 ( .A0(n1595), .A1(n1591), .B0(final_result_ieee[9]), .B1(n1701), .Y(n509) );
AO22X1TS U992 ( .A0(n1595), .A1(n1594), .B0(final_result_ieee[13]), .B1(
n1701), .Y(n506) );
OAI211X1TS U993 ( .A0(n1077), .A1(n1187), .B0(n1569), .C0(n1076), .Y(n755)
);
OAI211X1TS U994 ( .A0(n1073), .A1(n1187), .B0(n1569), .C0(n1072), .Y(n756)
);
OAI211X1TS U995 ( .A0(n1191), .A1(n1610), .B0(n1569), .C0(n1190), .Y(n760)
);
OAI211X1TS U996 ( .A0(n1075), .A1(n1187), .B0(n1569), .C0(n1074), .Y(n758)
);
OAI211X1TS U997 ( .A0(n1071), .A1(n1187), .B0(n1569), .C0(n1070), .Y(n759)
);
OAI211X1TS U998 ( .A0(n1189), .A1(n1610), .B0(n1569), .C0(n1188), .Y(n761)
);
INVX1TS U999 ( .A(n1501), .Y(n1500) );
OAI21X1TS U1000 ( .A0(n1645), .A1(n1568), .B0(n1280), .Y(n724) );
OAI21X1TS U1001 ( .A0(n1644), .A1(n1566), .B0(n1322), .Y(n566) );
OAI21X1TS U1002 ( .A0(n1765), .A1(n1568), .B0(n1273), .Y(n752) );
OAI21X1TS U1003 ( .A0(n1641), .A1(n1279), .B0(n1276), .Y(n748) );
NOR2X6TS U1004 ( .A(n1219), .B(n930), .Y(n957) );
OAI21X1TS U1005 ( .A0(n1690), .A1(n1568), .B0(n1272), .Y(n725) );
OAI21X1TS U1006 ( .A0(n1677), .A1(n1279), .B0(n1059), .Y(n750) );
OAI21X1TS U1007 ( .A0(n1643), .A1(n1301), .B0(n1293), .Y(n738) );
OAI21X1TS U1008 ( .A0(n1668), .A1(n1301), .B0(n1295), .Y(n746) );
OAI21X1TS U1009 ( .A0(n1688), .A1(n1566), .B0(n1320), .Y(n570) );
OAI21X1TS U1010 ( .A0(n1667), .A1(n1261), .B0(n1247), .Y(n598) );
OAI21X1TS U1011 ( .A0(n1678), .A1(n1312), .B0(n1289), .Y(n736) );
OAI21X1TS U1012 ( .A0(n1686), .A1(n1301), .B0(n1288), .Y(n739) );
OAI21X1TS U1013 ( .A0(n1765), .A1(n1261), .B0(n1250), .Y(n608) );
OAI21X1TS U1014 ( .A0(n1646), .A1(n1566), .B0(n1323), .Y(n572) );
OAI21X1TS U1015 ( .A0(n1684), .A1(n1279), .B0(n1275), .Y(n749) );
OAI21X1TS U1016 ( .A0(n1687), .A1(n1265), .B0(n1244), .Y(n578) );
OAI21X1TS U1017 ( .A0(n1646), .A1(n1312), .B0(n1303), .Y(n734) );
OAI21X1TS U1018 ( .A0(n1683), .A1(n1279), .B0(n1278), .Y(n751) );
OAI21X1TS U1019 ( .A0(n1685), .A1(n1265), .B0(n1259), .Y(n586) );
OAI21X1TS U1020 ( .A0(n1694), .A1(n1312), .B0(n1281), .Y(n735) );
OAI21X1TS U1021 ( .A0(n1660), .A1(n1301), .B0(n1292), .Y(n742) );
OAI21X1TS U1022 ( .A0(n1641), .A1(n1261), .B0(n1248), .Y(n600) );
OAI21X1TS U1023 ( .A0(n1679), .A1(n1301), .B0(n1296), .Y(n744) );
OAI21X1TS U1024 ( .A0(n1667), .A1(n1279), .B0(n1277), .Y(n747) );
OAI21X1TS U1025 ( .A0(n1681), .A1(n1566), .B0(n1321), .Y(n568) );
OAI21X1TS U1026 ( .A0(n1660), .A1(n1265), .B0(n1257), .Y(n588) );
OAI21X1TS U1027 ( .A0(n1270), .A1(n1554), .B0(n1267), .Y(n1268) );
OAI21X1TS U1028 ( .A0(n1678), .A1(n1265), .B0(n1241), .Y(n576) );
OAI21X1TS U1029 ( .A0(n1642), .A1(n1261), .B0(n1242), .Y(n610) );
NOR2X6TS U1030 ( .A(Raw_mant_NRM_SWR[12]), .B(n938), .Y(n1126) );
INVX1TS U1031 ( .A(n1284), .Y(n1267) );
OAI21X1TS U1032 ( .A0(n1597), .A1(n1240), .B0(n1197), .Y(n480) );
NAND2BX1TS U1033 ( .AN(n1090), .B(n1064), .Y(n1067) );
OAI21X1TS U1034 ( .A0(n1206), .A1(n1240), .B0(n1205), .Y(n463) );
AOI222X1TS U1035 ( .A0(n1599), .A1(n906), .B0(Data_array_SWR[7]), .B1(n900),
.C0(n1598), .C1(n1112), .Y(n1236) );
AOI222X1TS U1036 ( .A0(n1599), .A1(n905), .B0(Data_array_SWR[7]), .B1(n904),
.C0(n1598), .C1(n1604), .Y(n1630) );
AOI222X1TS U1037 ( .A0(n1603), .A1(n905), .B0(n904), .B1(Data_array_SWR[5]),
.C0(n1602), .C1(n1604), .Y(n1626) );
NOR2X6TS U1038 ( .A(Raw_mant_NRM_SWR[13]), .B(n1122), .Y(n959) );
AOI222X1TS U1039 ( .A0(n1606), .A1(n905), .B0(n904), .B1(Data_array_SWR[4]),
.C0(n1605), .C1(n1604), .Y(n1623) );
OAI21X1TS U1040 ( .A0(n1415), .A1(n1418), .B0(n1419), .Y(n985) );
OAI21X1TS U1041 ( .A0(n1612), .A1(n1402), .B0(n1212), .Y(n464) );
OR2X2TS U1042 ( .A(n1617), .B(n1127), .Y(n884) );
OAI21X1TS U1043 ( .A0(n1216), .A1(n1402), .B0(n1215), .Y(n465) );
NOR2X1TS U1044 ( .A(n1414), .B(n1418), .Y(n986) );
OAI21X1TS U1045 ( .A0(n1038), .A1(n1037), .B0(n1036), .Y(n1056) );
NAND4BX1TS U1046 ( .AN(exp_rslt_NRM2_EW1[4]), .B(n1062), .C(n1075), .D(n1071), .Y(n1063) );
AO22XLTS U1047 ( .A0(n1517), .A1(add_subt), .B0(n1515), .B1(intAS), .Y(n830)
);
BUFX3TS U1048 ( .A(n1527), .Y(n1313) );
AOI32X1TS U1049 ( .A0(Shift_amount_SHT1_EWR[2]), .A1(n1540), .A2(n914), .B0(
shift_value_SHT2_EWR[2]), .B1(n1113), .Y(n1539) );
OAI211X1TS U1050 ( .A0(n995), .A1(n1148), .B0(n994), .C0(n993), .Y(n1000) );
NOR2BX4TS U1051 ( .AN(Shift_amount_SHT1_EWR[0]), .B(n915), .Y(n1527) );
INVX3TS U1052 ( .A(n1620), .Y(n1629) );
OR2X2TS U1053 ( .A(n915), .B(Shift_amount_SHT1_EWR[0]), .Y(n949) );
INVX2TS U1054 ( .A(n1555), .Y(n1240) );
CLKBUFX3TS U1055 ( .A(n1085), .Y(n902) );
OAI211X1TS U1056 ( .A0(intDX_EWSW[8]), .A1(n1682), .B0(n1017), .C0(n1016),
.Y(n1018) );
INVX3TS U1057 ( .A(n989), .Y(n1588) );
NAND2BX1TS U1058 ( .AN(n954), .B(n953), .Y(n956) );
AOI211X1TS U1059 ( .A0(intDY_EWSW[16]), .A1(n1656), .B0(n1045), .C0(n1155),
.Y(n1035) );
CLKBUFX3TS U1060 ( .A(n1390), .Y(n901) );
NOR2X1TS U1061 ( .A(n1186), .B(exp_rslt_NRM2_EW1[1]), .Y(n1062) );
INVX1TS U1062 ( .A(n1118), .Y(n1120) );
OAI211X2TS U1063 ( .A0(intDX_EWSW[12]), .A1(n1685), .B0(n1013), .C0(n1004),
.Y(n1015) );
OAI211X2TS U1064 ( .A0(intDX_EWSW[20]), .A1(n1688), .B0(n1050), .C0(n1034),
.Y(n1045) );
NOR2X1TS U1065 ( .A(n1053), .B(intDY_EWSW[24]), .Y(n991) );
NAND3X1TS U1066 ( .A(n1689), .B(n992), .C(intDX_EWSW[26]), .Y(n994) );
NOR2X4TS U1067 ( .A(shift_value_SHT2_EWR[4]), .B(n1108), .Y(n1085) );
NOR2X1TS U1068 ( .A(n1666), .B(n873), .Y(n1116) );
NAND3X1TS U1069 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1640), .C(
n1669), .Y(n1502) );
INVX2TS U1070 ( .A(n883), .Y(n876) );
INVX4TS U1071 ( .A(Shift_reg_FLAGS_7[2]), .Y(n989) );
CLKINVX2TS U1072 ( .A(Shift_reg_FLAGS_7[3]), .Y(n1386) );
NAND2BX1TS U1073 ( .AN(intDX_EWSW[27]), .B(intDY_EWSW[27]), .Y(n992) );
NOR2X1TS U1074 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[20]), .Y(n953) );
NAND2BX1TS U1075 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n993) );
NAND2BX1TS U1076 ( .AN(intDX_EWSW[21]), .B(intDY_EWSW[21]), .Y(n1034) );
INVX1TS U1077 ( .A(DmP_mant_SFG_SWR[6]), .Y(n1627) );
NAND2BX1TS U1078 ( .AN(intDX_EWSW[19]), .B(intDY_EWSW[19]), .Y(n1042) );
NAND2BX1TS U1079 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n1051) );
INVX1TS U1080 ( .A(DmP_mant_SFG_SWR[4]), .Y(n1622) );
OR2X2TS U1081 ( .A(Raw_mant_NRM_SWR[25]), .B(Raw_mant_NRM_SWR[24]), .Y(n880)
);
NAND2BX1TS U1082 ( .AN(intDX_EWSW[13]), .B(intDY_EWSW[13]), .Y(n1004) );
NAND2BX1TS U1083 ( .AN(Raw_mant_NRM_SWR[9]), .B(n1632), .Y(n930) );
NAND2BX1TS U1084 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n1017) );
NOR2X8TS U1085 ( .A(n948), .B(n1575), .Y(n1531) );
AOI222X4TS U1086 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n897), .B0(n917), .B1(
DmP_mant_SHT1_SW[6]), .C0(n1360), .C1(DmP_mant_SHT1_SW[7]), .Y(n1339)
);
ADDFHX2TS U1087 ( .A(n1450), .B(DMP_SFG[13]), .CI(n1449), .CO(n1456), .S(
n1452) );
ADDFHX2TS U1088 ( .A(n1459), .B(DMP_SFG[12]), .CI(n1458), .CO(n1449), .S(
n1460) );
NAND2BXLTS U1089 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n1006) );
NAND3XLTS U1090 ( .A(n1682), .B(n1017), .C(intDX_EWSW[8]), .Y(n1005) );
AOI21X1TS U1091 ( .A0(n940), .A1(Raw_mant_NRM_SWR[6]), .B0(n939), .Y(n946)
);
NAND2BXLTS U1092 ( .AN(intDX_EWSW[2]), .B(intDY_EWSW[2]), .Y(n1023) );
NAND2BX1TS U1093 ( .AN(n942), .B(n960), .Y(n945) );
INVX2TS U1094 ( .A(n1123), .Y(n942) );
NOR2X4TS U1095 ( .A(n929), .B(n880), .Y(n1489) );
NAND2X1TS U1096 ( .A(Raw_mant_NRM_SWR[12]), .B(n959), .Y(n1123) );
NAND3X1TS U1097 ( .A(n1121), .B(n1491), .C(Raw_mant_NRM_SWR[1]), .Y(n1221)
);
AO21XLTS U1098 ( .A0(n1633), .A1(n1704), .B0(n1122), .Y(n1492) );
INVX4TS U1099 ( .A(n1661), .Y(n1200) );
AOI21X1TS U1100 ( .A0(n1407), .A1(n1410), .B0(n983), .Y(n1415) );
NAND2X1TS U1101 ( .A(n1408), .B(n1410), .Y(n1414) );
NAND2X1TS U1102 ( .A(n1454), .B(n1445), .Y(n1433) );
CLKBUFX2TS U1103 ( .A(n1245), .Y(n1287) );
AOI222X1TS U1104 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n898), .B0(n917), .B1(
DmP_mant_SHT1_SW[3]), .C0(n1360), .C1(DmP_mant_SHT1_SW[4]), .Y(n1347)
);
AOI222X1TS U1105 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n898), .B0(n917), .B1(
DmP_mant_SHT1_SW[2]), .C0(n1360), .C1(DmP_mant_SHT1_SW[3]), .Y(n1343)
);
INVX2TS U1106 ( .A(n1383), .Y(n1353) );
NAND2X2TS U1107 ( .A(n970), .B(n1531), .Y(n1383) );
NOR2X4TS U1108 ( .A(n926), .B(n1501), .Y(n1595) );
AOI222X1TS U1109 ( .A0(n1603), .A1(n1401), .B0(Data_array_SWR[5]), .B1(n900),
.C0(n1602), .C1(n1112), .Y(n1232) );
AO22XLTS U1110 ( .A0(n903), .A1(Data_array_SWR[8]), .B0(n1195), .B1(n905),
.Y(n1196) );
AO22XLTS U1111 ( .A0(n903), .A1(Data_array_SWR[9]), .B0(n1192), .B1(n1617),
.Y(n1193) );
INVX2TS U1112 ( .A(n1415), .Y(n1416) );
INVX2TS U1113 ( .A(n1418), .Y(n1420) );
OAI21X1TS U1114 ( .A0(n1434), .A1(n1437), .B0(n1438), .Y(n1407) );
NOR2X1TS U1115 ( .A(n1433), .B(n1437), .Y(n1408) );
INVX2TS U1116 ( .A(n1434), .Y(n1435) );
INVX2TS U1117 ( .A(n1437), .Y(n1439) );
INVX2TS U1118 ( .A(n1284), .Y(n1265) );
BUFX3TS U1119 ( .A(n1245), .Y(n1263) );
INVX2TS U1120 ( .A(n1284), .Y(n1261) );
NAND4XLTS U1121 ( .A(n1169), .B(n1168), .C(n1167), .D(n1166), .Y(n1179) );
NAND4XLTS U1122 ( .A(n1153), .B(n1152), .C(n1151), .D(n1150), .Y(n1181) );
NAND4XLTS U1123 ( .A(n1177), .B(n1176), .C(n1175), .D(n1174), .Y(n1178) );
INVX2TS U1124 ( .A(n1287), .Y(n1301) );
BUFX3TS U1125 ( .A(n1284), .Y(n1302) );
INVX2TS U1126 ( .A(n1287), .Y(n1312) );
AO22XLTS U1127 ( .A0(n1512), .A1(Data_X[10]), .B0(n1511), .B1(intDX_EWSW[10]), .Y(n852) );
AO22XLTS U1128 ( .A0(n1513), .A1(Data_X[30]), .B0(n1515), .B1(intDX_EWSW[30]), .Y(n832) );
AO22XLTS U1129 ( .A0(n1512), .A1(Data_X[22]), .B0(n1523), .B1(intDX_EWSW[22]), .Y(n840) );
AO22XLTS U1130 ( .A0(n1514), .A1(Data_X[14]), .B0(n1511), .B1(intDX_EWSW[14]), .Y(n848) );
AO22XLTS U1131 ( .A0(n1513), .A1(Data_X[20]), .B0(n1523), .B1(intDX_EWSW[20]), .Y(n842) );
AO22XLTS U1132 ( .A0(n1512), .A1(Data_X[12]), .B0(n1511), .B1(intDX_EWSW[12]), .Y(n850) );
AO22XLTS U1133 ( .A0(n1513), .A1(Data_X[31]), .B0(n1515), .B1(intDX_EWSW[31]), .Y(n831) );
AO22XLTS U1134 ( .A0(n1512), .A1(Data_X[19]), .B0(n1523), .B1(intDX_EWSW[19]), .Y(n843) );
AO22XLTS U1135 ( .A0(n1513), .A1(Data_X[29]), .B0(n1515), .B1(intDX_EWSW[29]), .Y(n833) );
AO22XLTS U1136 ( .A0(n1524), .A1(Data_X[18]), .B0(n1523), .B1(intDX_EWSW[18]), .Y(n844) );
AO22XLTS U1137 ( .A0(n1513), .A1(Data_X[9]), .B0(n1511), .B1(intDX_EWSW[9]),
.Y(n853) );
AO22XLTS U1138 ( .A0(n1512), .A1(Data_X[11]), .B0(n1511), .B1(intDX_EWSW[11]), .Y(n851) );
AO22XLTS U1139 ( .A0(n1513), .A1(Data_X[8]), .B0(n1511), .B1(intDX_EWSW[8]),
.Y(n854) );
AO22XLTS U1140 ( .A0(n1512), .A1(Data_X[17]), .B0(n1523), .B1(intDX_EWSW[17]), .Y(n845) );
AO22XLTS U1141 ( .A0(n1512), .A1(Data_X[13]), .B0(n1511), .B1(intDX_EWSW[13]), .Y(n849) );
AO22XLTS U1142 ( .A0(n1513), .A1(Data_X[21]), .B0(n1523), .B1(intDX_EWSW[21]), .Y(n841) );
AO22XLTS U1143 ( .A0(n1512), .A1(Data_X[15]), .B0(n1523), .B1(intDX_EWSW[15]), .Y(n847) );
AO22XLTS U1144 ( .A0(n1516), .A1(intDY_EWSW[2]), .B0(n1519), .B1(Data_Y[2]),
.Y(n826) );
AO22XLTS U1145 ( .A0(n1520), .A1(Data_X[5]), .B0(n1511), .B1(intDX_EWSW[5]),
.Y(n857) );
AO22XLTS U1146 ( .A0(n1520), .A1(Data_X[6]), .B0(n1511), .B1(intDX_EWSW[6]),
.Y(n856) );
AO22XLTS U1147 ( .A0(n1513), .A1(Data_X[7]), .B0(n1511), .B1(intDX_EWSW[7]),
.Y(n855) );
AO22XLTS U1148 ( .A0(n1512), .A1(Data_X[16]), .B0(n1523), .B1(intDX_EWSW[16]), .Y(n846) );
AO22XLTS U1149 ( .A0(n1522), .A1(intDY_EWSW[29]), .B0(n1521), .B1(Data_Y[29]), .Y(n799) );
AO22XLTS U1150 ( .A0(n1522), .A1(intDY_EWSW[30]), .B0(n1521), .B1(Data_Y[30]), .Y(n798) );
AO22XLTS U1151 ( .A0(n1522), .A1(intDY_EWSW[21]), .B0(n1519), .B1(Data_Y[21]), .Y(n807) );
AO22XLTS U1152 ( .A0(n1522), .A1(intDY_EWSW[22]), .B0(n1520), .B1(Data_Y[22]), .Y(n806) );
AO22XLTS U1153 ( .A0(n1516), .A1(intDY_EWSW[3]), .B0(n1519), .B1(Data_Y[3]),
.Y(n825) );
AO22XLTS U1154 ( .A0(n1516), .A1(intDY_EWSW[8]), .B0(n1520), .B1(Data_Y[8]),
.Y(n820) );
AO22XLTS U1155 ( .A0(n1518), .A1(intDY_EWSW[11]), .B0(n1520), .B1(Data_Y[11]), .Y(n817) );
AO22XLTS U1156 ( .A0(n1518), .A1(intDY_EWSW[15]), .B0(n1521), .B1(Data_Y[15]), .Y(n813) );
AO22XLTS U1157 ( .A0(n1518), .A1(intDY_EWSW[17]), .B0(n1521), .B1(Data_Y[17]), .Y(n811) );
AO22XLTS U1158 ( .A0(n1518), .A1(intDY_EWSW[18]), .B0(n1521), .B1(Data_Y[18]), .Y(n810) );
AO22XLTS U1159 ( .A0(n1518), .A1(intDY_EWSW[12]), .B0(n1519), .B1(Data_Y[12]), .Y(n816) );
AO22XLTS U1160 ( .A0(n1518), .A1(intDY_EWSW[13]), .B0(n1521), .B1(Data_Y[13]), .Y(n815) );
AO22XLTS U1161 ( .A0(n1518), .A1(intDY_EWSW[14]), .B0(n1521), .B1(Data_Y[14]), .Y(n814) );
AO22XLTS U1162 ( .A0(n1518), .A1(intDY_EWSW[20]), .B0(n1519), .B1(Data_Y[20]), .Y(n808) );
AO22XLTS U1163 ( .A0(n1522), .A1(intDY_EWSW[28]), .B0(n1517), .B1(Data_Y[28]), .Y(n800) );
AO22XLTS U1164 ( .A0(n1512), .A1(Data_X[28]), .B0(n1515), .B1(intDX_EWSW[28]), .Y(n834) );
AO22XLTS U1165 ( .A0(n1516), .A1(intDY_EWSW[5]), .B0(n1519), .B1(Data_Y[5]),
.Y(n823) );
AO22XLTS U1166 ( .A0(n1516), .A1(intDY_EWSW[4]), .B0(n1519), .B1(Data_Y[4]),
.Y(n824) );
AO22XLTS U1167 ( .A0(n1516), .A1(intDY_EWSW[6]), .B0(n1519), .B1(Data_Y[6]),
.Y(n822) );
AO22XLTS U1168 ( .A0(n1518), .A1(intDY_EWSW[16]), .B0(n1521), .B1(Data_Y[16]), .Y(n812) );
AO22XLTS U1169 ( .A0(n1516), .A1(intDY_EWSW[9]), .B0(n1520), .B1(Data_Y[9]),
.Y(n819) );
AO22XLTS U1170 ( .A0(n1516), .A1(intDY_EWSW[0]), .B0(n1520), .B1(Data_Y[0]),
.Y(n828) );
AO22XLTS U1171 ( .A0(n1516), .A1(intDY_EWSW[1]), .B0(n1519), .B1(Data_Y[1]),
.Y(n827) );
AO22XLTS U1172 ( .A0(n1516), .A1(intDY_EWSW[10]), .B0(n1520), .B1(Data_Y[10]), .Y(n818) );
AO22XLTS U1173 ( .A0(n1518), .A1(intDY_EWSW[19]), .B0(n1521), .B1(Data_Y[19]), .Y(n809) );
AO22XLTS U1174 ( .A0(n1515), .A1(intDY_EWSW[7]), .B0(n1519), .B1(Data_Y[7]),
.Y(n821) );
AOI222X1TS U1175 ( .A0(intDY_EWSW[4]), .A1(n1637), .B0(n1027), .B1(n1026),
.C0(intDY_EWSW[5]), .C1(n1651), .Y(n1029) );
AOI2BB2XLTS U1176 ( .B0(intDX_EWSW[3]), .B1(n1677), .A0N(intDY_EWSW[2]),
.A1N(n1025), .Y(n1026) );
AOI2BB1XLTS U1177 ( .A0N(n932), .A1N(Raw_mant_NRM_SWR[23]), .B0(
Raw_mant_NRM_SWR[24]), .Y(n935) );
OAI2BB2XLTS U1178 ( .B0(n1008), .B1(n1015), .A0N(n1007), .A1N(n1016), .Y(
n1011) );
NOR2BX1TS U1179 ( .AN(n1019), .B(n1018), .Y(n1033) );
INVX2TS U1180 ( .A(n1015), .Y(n1019) );
INVX2TS U1181 ( .A(n947), .Y(n912) );
CLKAND2X2TS U1182 ( .A(n1101), .B(shift_value_SHT2_EWR[4]), .Y(n1103) );
NAND2X1TS U1183 ( .A(n1101), .B(n882), .Y(n1127) );
NOR2XLTS U1184 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[16]), .Y(n952) );
NOR2XLTS U1185 ( .A(n1040), .B(intDY_EWSW[16]), .Y(n1041) );
AOI211X1TS U1186 ( .A0(intDY_EWSW[28]), .A1(n1658), .B0(n998), .C0(n996),
.Y(n1052) );
NOR2BX1TS U1187 ( .AN(n1035), .B(n1040), .Y(n1036) );
NOR2BX1TS U1188 ( .AN(n1033), .B(n1032), .Y(n1037) );
INVX2TS U1189 ( .A(n1014), .Y(n1038) );
INVX2TS U1190 ( .A(n947), .Y(n896) );
INVX4TS U1191 ( .A(n912), .Y(n913) );
NOR2X1TS U1192 ( .A(n1117), .B(n1116), .Y(intadd_21_B_1_) );
NOR2XLTS U1193 ( .A(n1661), .B(n1115), .Y(n1117) );
NAND4XLTS U1194 ( .A(n1161), .B(n1160), .C(n1159), .D(n1158), .Y(n1180) );
BUFX3TS U1195 ( .A(n1631), .Y(n1555) );
AO21XLTS U1196 ( .A0(n1580), .A1(DMP_SFG[1]), .B0(n1579), .Y(n1185) );
OAI21XLTS U1197 ( .A0(n1633), .A1(n1533), .B0(n1528), .Y(n1529) );
INVX2TS U1198 ( .A(n1504), .Y(n1503) );
CLKMX2X2TS U1199 ( .A(DP_OP_285J28_122_2126_n71), .B(
DP_OP_285J28_122_2126_n70), .S0(DP_OP_285J28_122_2126_n74), .Y(n1474)
);
NAND2X1TS U1200 ( .A(n1662), .B(LZD_output_NRM2_EW[0]), .Y(
DP_OP_15J28_123_3372_n8) );
AOI222X1TS U1201 ( .A0(n1606), .A1(n1401), .B0(Data_array_SWR[4]), .B1(n900),
.C0(n1605), .C1(n1112), .Y(n1234) );
AOI222X1TS U1202 ( .A0(n1195), .A1(n906), .B0(Data_array_SWR[8]), .B1(n900),
.C0(n1207), .C1(n1112), .Y(n1239) );
AOI222X1TS U1203 ( .A0(n1192), .A1(n1401), .B0(Data_array_SWR[9]), .B1(n900),
.C0(n1201), .C1(n1112), .Y(n1228) );
INVX2TS U1204 ( .A(n1489), .Y(n1494) );
AOI21X1TS U1205 ( .A0(n1456), .A1(n986), .B0(n985), .Y(n1404) );
CLKBUFX2TS U1206 ( .A(n1631), .Y(n1620) );
MX2X1TS U1207 ( .A(n1387), .B(OP_FLAG_SHT2), .S0(n1403), .Y(n549) );
AO21XLTS U1208 ( .A0(LZD_output_NRM2_EW[0]), .A1(n914), .B0(n890), .Y(n515)
);
AOI2BB2XLTS U1209 ( .B0(n1572), .B1(n1543), .A0N(Shift_amount_SHT1_EWR[0]),
.A1N(n1552), .Y(n766) );
AO22XLTS U1210 ( .A0(n1572), .A1(DmP_EXP_EWSW[20]), .B0(n1570), .B1(
DmP_mant_SHT1_SW[20]), .Y(n569) );
AO22XLTS U1211 ( .A0(n1572), .A1(DmP_EXP_EWSW[16]), .B0(n1565), .B1(
DmP_mant_SHT1_SW[16]), .Y(n577) );
AO22XLTS U1212 ( .A0(n921), .A1(DmP_EXP_EWSW[7]), .B0(n1564), .B1(
DmP_mant_SHT1_SW[7]), .Y(n595) );
AO22XLTS U1213 ( .A0(n1572), .A1(DmP_EXP_EWSW[18]), .B0(n1565), .B1(
DmP_mant_SHT1_SW[18]), .Y(n573) );
AO22XLTS U1214 ( .A0(n921), .A1(DmP_EXP_EWSW[13]), .B0(n1565), .B1(
DmP_mant_SHT1_SW[13]), .Y(n583) );
AO22XLTS U1215 ( .A0(n1563), .A1(DmP_EXP_EWSW[4]), .B0(n1564), .B1(
DmP_mant_SHT1_SW[4]), .Y(n601) );
AO22XLTS U1216 ( .A0(n921), .A1(DmP_EXP_EWSW[14]), .B0(n1565), .B1(
DmP_mant_SHT1_SW[14]), .Y(n581) );
AO22XLTS U1217 ( .A0(n1572), .A1(DmP_EXP_EWSW[19]), .B0(n1570), .B1(
DmP_mant_SHT1_SW[19]), .Y(n571) );
AO22XLTS U1218 ( .A0(n921), .A1(DmP_EXP_EWSW[11]), .B0(n1565), .B1(
DmP_mant_SHT1_SW[11]), .Y(n587) );
AO22XLTS U1219 ( .A0(n921), .A1(DmP_EXP_EWSW[9]), .B0(n1565), .B1(
DmP_mant_SHT1_SW[9]), .Y(n591) );
AO22XLTS U1220 ( .A0(n1636), .A1(DmP_EXP_EWSW[6]), .B0(n1564), .B1(
DmP_mant_SHT1_SW[6]), .Y(n597) );
AO22XLTS U1221 ( .A0(n1563), .A1(DmP_EXP_EWSW[2]), .B0(n1564), .B1(
DmP_mant_SHT1_SW[2]), .Y(n605) );
AO22XLTS U1222 ( .A0(n1572), .A1(DmP_EXP_EWSW[21]), .B0(n1570), .B1(
DmP_mant_SHT1_SW[21]), .Y(n567) );
AO22XLTS U1223 ( .A0(n1563), .A1(DmP_EXP_EWSW[5]), .B0(n1564), .B1(
DmP_mant_SHT1_SW[5]), .Y(n599) );
AO22XLTS U1224 ( .A0(n1563), .A1(DmP_EXP_EWSW[1]), .B0(n1564), .B1(
DmP_mant_SHT1_SW[1]), .Y(n607) );
AO22XLTS U1225 ( .A0(n921), .A1(DmP_EXP_EWSW[15]), .B0(n1565), .B1(
DmP_mant_SHT1_SW[15]), .Y(n579) );
AO22XLTS U1226 ( .A0(n1572), .A1(DmP_EXP_EWSW[22]), .B0(n1570), .B1(
DmP_mant_SHT1_SW[22]), .Y(n565) );
AO22XLTS U1227 ( .A0(n921), .A1(DmP_EXP_EWSW[12]), .B0(n1565), .B1(
DmP_mant_SHT1_SW[12]), .Y(n585) );
AO22XLTS U1228 ( .A0(n921), .A1(DmP_EXP_EWSW[10]), .B0(n1565), .B1(
DmP_mant_SHT1_SW[10]), .Y(n589) );
AO22XLTS U1229 ( .A0(n921), .A1(DmP_EXP_EWSW[8]), .B0(n1564), .B1(
DmP_mant_SHT1_SW[8]), .Y(n593) );
AO22XLTS U1230 ( .A0(n1563), .A1(DmP_EXP_EWSW[3]), .B0(n1564), .B1(
DmP_mant_SHT1_SW[3]), .Y(n603) );
OAI222X1TS U1231 ( .A0(n1713), .A1(n1540), .B0(n910), .B1(n1537), .C0(n907),
.C1(n1536), .Y(n781) );
AO22XLTS U1232 ( .A0(n1524), .A1(Data_X[0]), .B0(n1510), .B1(intDX_EWSW[0]),
.Y(n862) );
AO22XLTS U1233 ( .A0(n1524), .A1(Data_X[2]), .B0(n1510), .B1(intDX_EWSW[2]),
.Y(n860) );
MX2X1TS U1234 ( .A(n1591), .B(DmP_mant_SFG_SWR[11]), .S0(n1402), .Y(n477) );
MX2X1TS U1235 ( .A(n1589), .B(DmP_mant_SFG_SWR[12]), .S0(n1402), .Y(n476) );
MX2X1TS U1236 ( .A(n1590), .B(DmP_mant_SFG_SWR[13]), .S0(n1402), .Y(n475) );
MX2X1TS U1237 ( .A(n1592), .B(DmP_mant_SFG_SWR[14]), .S0(n1402), .Y(n474) );
MX2X1TS U1238 ( .A(n1594), .B(DmP_mant_SFG_SWR[15]), .S0(n1402), .Y(n473) );
AO22XLTS U1239 ( .A0(n1524), .A1(Data_Y[31]), .B0(n1523), .B1(intDY_EWSW[31]), .Y(n797) );
AO22XLTS U1240 ( .A0(n1555), .A1(DMP_SHT2_EWSW[0]), .B0(n1562), .B1(
DMP_SFG[0]), .Y(n717) );
OAI21XLTS U1241 ( .A0(n1240), .A1(n1236), .B0(n1235), .Y(n470) );
OAI21XLTS U1242 ( .A0(n1240), .A1(n1232), .B0(n1231), .Y(n468) );
MX2X1TS U1243 ( .A(n1593), .B(DmP_mant_SFG_SWR[10]), .S0(n1402), .Y(n478) );
MX2X1TS U1244 ( .A(DMP_SFG[19]), .B(DMP_SHT2_EWSW[19]), .S0(n1555), .Y(n660)
);
MX2X1TS U1245 ( .A(DMP_SFG[20]), .B(DMP_SHT2_EWSW[20]), .S0(n1555), .Y(n657)
);
MX2X1TS U1246 ( .A(DMP_SFG[22]), .B(DMP_SHT2_EWSW[22]), .S0(n1403), .Y(n651)
);
MX2X1TS U1247 ( .A(DMP_SFG[10]), .B(DMP_SHT2_EWSW[10]), .S0(n1555), .Y(n687)
);
MX2X1TS U1248 ( .A(DMP_SFG[12]), .B(DMP_SHT2_EWSW[12]), .S0(n1403), .Y(n681)
);
MX2X1TS U1249 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(n1576),
.Y(n641) );
MX2X1TS U1250 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(n915),
.Y(n636) );
MX2X1TS U1251 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(n1576),
.Y(n631) );
MX2X1TS U1252 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(n915),
.Y(n626) );
MX2X1TS U1253 ( .A(DMP_SFG[13]), .B(DMP_SHT2_EWSW[13]), .S0(n1555), .Y(n678)
);
MX2X1TS U1254 ( .A(DMP_SFG[21]), .B(DMP_SHT2_EWSW[21]), .S0(n1403), .Y(n654)
);
OAI21XLTS U1255 ( .A0(n1691), .A1(n1312), .B0(n1286), .Y(n730) );
AO22XLTS U1256 ( .A0(n1552), .A1(n1547), .B0(n1571), .B1(
Shift_amount_SHT1_EWR[1]), .Y(n765) );
MX2X1TS U1257 ( .A(DMP_SFG[15]), .B(DMP_SHT2_EWSW[15]), .S0(n1624), .Y(n672)
);
MX2X1TS U1258 ( .A(DMP_SFG[17]), .B(DMP_SHT2_EWSW[17]), .S0(n1631), .Y(n666)
);
AO22XLTS U1259 ( .A0(n1572), .A1(DmP_EXP_EWSW[17]), .B0(n1565), .B1(
DmP_mant_SHT1_SW[17]), .Y(n575) );
MX2X1TS U1260 ( .A(DMP_SFG[14]), .B(DMP_SHT2_EWSW[14]), .S0(n1555), .Y(n675)
);
MX2X1TS U1261 ( .A(DMP_SFG[6]), .B(DMP_SHT2_EWSW[6]), .S0(n1403), .Y(n699)
);
MX2X1TS U1262 ( .A(DMP_SFG[9]), .B(DMP_SHT2_EWSW[9]), .S0(n1403), .Y(n690)
);
MX2X1TS U1263 ( .A(DMP_SFG[16]), .B(DMP_SHT2_EWSW[16]), .S0(n1403), .Y(n669)
);
MX2X1TS U1264 ( .A(DMP_SFG[18]), .B(DMP_SHT2_EWSW[18]), .S0(n1403), .Y(n663)
);
MX2X1TS U1265 ( .A(DMP_SFG[11]), .B(DMP_SHT2_EWSW[11]), .S0(n1555), .Y(n684)
);
MX2X1TS U1266 ( .A(DMP_SFG[8]), .B(DMP_SHT2_EWSW[8]), .S0(n1403), .Y(n693)
);
AO22XLTS U1267 ( .A0(n1624), .A1(DMP_SHT2_EWSW[1]), .B0(n1562), .B1(
DMP_SFG[1]), .Y(n714) );
AO22XLTS U1268 ( .A0(n1615), .A1(DMP_SHT2_EWSW[5]), .B0(n1574), .B1(
DMP_SFG[5]), .Y(n702) );
OAI211XLTS U1269 ( .A0(n1343), .A1(n911), .B0(n1330), .C0(n1329), .Y(n775)
);
OAI211XLTS U1270 ( .A0(n1356), .A1(n907), .B0(n1350), .C0(n1349), .Y(n778)
);
MX2X1TS U1271 ( .A(DMP_SFG[7]), .B(DMP_SHT2_EWSW[7]), .S0(n1403), .Y(n696)
);
AOI2BB2XLTS U1272 ( .B0(n1588), .B1(intadd_21_SUM_0_), .A0N(
Raw_mant_NRM_SWR[4]), .A1N(n1584), .Y(n538) );
OAI222X1TS U1273 ( .A0(n1705), .A1(n1540), .B0(n910), .B1(n1536), .C0(n908),
.C1(n1535), .Y(n783) );
OAI222X1TS U1274 ( .A0(n1540), .A1(n1706), .B0(n911), .B1(n1535), .C0(n907),
.C1(n1530), .Y(n785) );
AO22XLTS U1275 ( .A0(n1513), .A1(Data_X[27]), .B0(n1515), .B1(intDX_EWSW[27]), .Y(n835) );
AO22XLTS U1276 ( .A0(n1524), .A1(Data_X[1]), .B0(n1510), .B1(intDX_EWSW[1]),
.Y(n861) );
MX2X1TS U1277 ( .A(Raw_mant_NRM_SWR[10]), .B(n1478), .S0(n1486), .Y(n532) );
MX2X1TS U1278 ( .A(Raw_mant_NRM_SWR[9]), .B(n1484), .S0(n1486), .Y(n533) );
NAND3XLTS U1279 ( .A(busy), .B(Shift_amount_SHT1_EWR[4]), .C(n877), .Y(n1226) );
AO22XLTS U1280 ( .A0(n1513), .A1(Data_X[23]), .B0(n1523), .B1(intDX_EWSW[23]), .Y(n839) );
AO22XLTS U1281 ( .A0(n1524), .A1(Data_X[3]), .B0(n1510), .B1(intDX_EWSW[3]),
.Y(n859) );
CLKMX2X2TS U1282 ( .A(Raw_mant_NRM_SWR[25]), .B(n990), .S0(n1451), .Y(n517)
);
MX2X1TS U1283 ( .A(Raw_mant_NRM_SWR[22]), .B(n1426), .S0(n1451), .Y(n520) );
MX2X1TS U1284 ( .A(Raw_mant_NRM_SWR[17]), .B(n1448), .S0(n1451), .Y(n525) );
AO22XLTS U1285 ( .A0(n1522), .A1(intDY_EWSW[25]), .B0(n1517), .B1(Data_Y[25]), .Y(n803) );
AO22XLTS U1286 ( .A0(n1522), .A1(intDY_EWSW[26]), .B0(n1517), .B1(Data_Y[26]), .Y(n802) );
AO22XLTS U1287 ( .A0(n1522), .A1(intDY_EWSW[23]), .B0(n1517), .B1(Data_Y[23]), .Y(n805) );
AO22XLTS U1288 ( .A0(n1515), .A1(intDX_EWSW[25]), .B0(n1520), .B1(Data_X[25]), .Y(n837) );
AO22XLTS U1289 ( .A0(n1515), .A1(intDX_EWSW[24]), .B0(n1521), .B1(Data_X[24]), .Y(n838) );
MX2X1TS U1290 ( .A(Raw_mant_NRM_SWR[8]), .B(n1481), .S0(n1486), .Y(n534) );
AO22XLTS U1291 ( .A0(n1524), .A1(Data_X[4]), .B0(n1510), .B1(intDX_EWSW[4]),
.Y(n858) );
AO22XLTS U1292 ( .A0(n1522), .A1(intDY_EWSW[24]), .B0(n1517), .B1(Data_Y[24]), .Y(n804) );
AO22XLTS U1293 ( .A0(n1522), .A1(intDY_EWSW[27]), .B0(n1514), .B1(Data_Y[27]), .Y(n801) );
AO22XLTS U1294 ( .A0(n1515), .A1(intDX_EWSW[26]), .B0(n1520), .B1(Data_X[26]), .Y(n836) );
AO22XLTS U1295 ( .A0(n1562), .A1(DMP_SFG[3]), .B0(n1624), .B1(
DMP_SHT2_EWSW[3]), .Y(n708) );
AO22XLTS U1296 ( .A0(n1629), .A1(DMP_SFG[4]), .B0(n1624), .B1(
DMP_SHT2_EWSW[4]), .Y(n705) );
MX2X1TS U1297 ( .A(Raw_mant_NRM_SWR[14]), .B(n1460), .S0(n1486), .Y(n528) );
AO21XLTS U1298 ( .A0(n1577), .A1(n886), .B0(n1580), .Y(n1578) );
AOI2BB2XLTS U1299 ( .B0(beg_OP), .B1(n1640), .A0N(n1640), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n1060) );
MX2X1TS U1300 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(n1576),
.Y(n646) );
MX2X1TS U1301 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(n915),
.Y(n621) );
MX2X1TS U1302 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(n1576),
.Y(n616) );
MX2X1TS U1303 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(n915),
.Y(n611) );
MX2X1TS U1304 ( .A(Raw_mant_NRM_SWR[12]), .B(n1476), .S0(n1486), .Y(n530) );
AO22XLTS U1305 ( .A0(Shift_reg_FLAGS_7[0]), .A1(ZERO_FLAG_SHT1SHT2), .B0(
n1610), .B1(zero_flag), .Y(n552) );
MX2X1TS U1306 ( .A(Raw_mant_NRM_SWR[11]), .B(n1473), .S0(n1486), .Y(n531) );
MX2X1TS U1307 ( .A(Raw_mant_NRM_SWR[13]), .B(n1463), .S0(n1486), .Y(n529) );
AO21XLTS U1308 ( .A0(LZD_output_NRM2_EW[1]), .A1(n1575), .B0(n1498), .Y(n513) );
MX2X1TS U1309 ( .A(Raw_mant_NRM_SWR[23]), .B(n1429), .S0(n1451), .Y(n519) );
MX2X1TS U1310 ( .A(Raw_mant_NRM_SWR[21]), .B(n1406), .S0(n1451), .Y(n521) );
MX2X1TS U1311 ( .A(Raw_mant_NRM_SWR[20]), .B(n1423), .S0(n1451), .Y(n522) );
MX2X1TS U1312 ( .A(Raw_mant_NRM_SWR[19]), .B(n1413), .S0(n1451), .Y(n523) );
MX2X1TS U1313 ( .A(Raw_mant_NRM_SWR[18]), .B(n1442), .S0(n1451), .Y(n524) );
MX2X1TS U1314 ( .A(Raw_mant_NRM_SWR[16]), .B(n1457), .S0(n1486), .Y(n526) );
MX2X1TS U1315 ( .A(Raw_mant_NRM_SWR[15]), .B(n1452), .S0(n1451), .Y(n527) );
AO22XLTS U1316 ( .A0(Shift_reg_FLAGS_7[1]), .A1(SIGN_FLAG_NRM), .B0(n914),
.B1(SIGN_FLAG_SHT1SHT2), .Y(n544) );
AO22XLTS U1317 ( .A0(n1584), .A1(SIGN_FLAG_SFG), .B0(n1582), .B1(
SIGN_FLAG_NRM), .Y(n545) );
AO22XLTS U1318 ( .A0(n1620), .A1(SIGN_FLAG_SHT2), .B0(n1574), .B1(
SIGN_FLAG_SFG), .Y(n546) );
AO22XLTS U1319 ( .A0(n920), .A1(SIGN_FLAG_SHT1), .B0(n1764), .B1(
SIGN_FLAG_SHT2), .Y(n547) );
AO22XLTS U1320 ( .A0(n921), .A1(SIGN_FLAG_EXP), .B0(n1573), .B1(
SIGN_FLAG_SHT1), .Y(n548) );
AO22XLTS U1321 ( .A0(busy), .A1(OP_FLAG_SHT1), .B0(OP_FLAG_SHT2), .B1(n895),
.Y(n1716) );
AO22XLTS U1322 ( .A0(n1572), .A1(OP_FLAG_EXP), .B0(n1571), .B1(OP_FLAG_SHT1),
.Y(n551) );
AO22XLTS U1323 ( .A0(n915), .A1(ZERO_FLAG_NRM), .B0(n877), .B1(
ZERO_FLAG_SHT1SHT2), .Y(n553) );
AO22XLTS U1324 ( .A0(n1584), .A1(ZERO_FLAG_SFG), .B0(n1717), .B1(
ZERO_FLAG_NRM), .Y(n554) );
AO22XLTS U1325 ( .A0(n1624), .A1(ZERO_FLAG_SHT2), .B0(n1574), .B1(
ZERO_FLAG_SFG), .Y(n555) );
AO22XLTS U1326 ( .A0(n920), .A1(ZERO_FLAG_SHT1), .B0(n1764), .B1(
ZERO_FLAG_SHT2), .Y(n556) );
AO22XLTS U1327 ( .A0(n1572), .A1(ZERO_FLAG_EXP), .B0(n1570), .B1(
ZERO_FLAG_SHT1), .Y(n557) );
OAI21XLTS U1328 ( .A0(n1694), .A1(n1265), .B0(n1254), .Y(n574) );
OAI21XLTS U1329 ( .A0(n1643), .A1(n1265), .B0(n1264), .Y(n580) );
OAI21XLTS U1330 ( .A0(n1686), .A1(n1265), .B0(n1256), .Y(n582) );
OAI21XLTS U1331 ( .A0(n1680), .A1(n1265), .B0(n1262), .Y(n584) );
OAI21XLTS U1332 ( .A0(n1653), .A1(n1265), .B0(n1255), .Y(n590) );
OAI21XLTS U1333 ( .A0(n1682), .A1(n1261), .B0(n1258), .Y(n594) );
OAI21XLTS U1334 ( .A0(n1668), .A1(n1261), .B0(n1253), .Y(n596) );
OAI21XLTS U1335 ( .A0(n1684), .A1(n1261), .B0(n1246), .Y(n602) );
OAI21XLTS U1336 ( .A0(n1677), .A1(n1261), .B0(n1251), .Y(n604) );
OAI21XLTS U1337 ( .A0(n1683), .A1(n1261), .B0(n1249), .Y(n606) );
AO22XLTS U1338 ( .A0(n1563), .A1(DmP_EXP_EWSW[0]), .B0(n1564), .B1(
DmP_mant_SHT1_SW[0]), .Y(n609) );
AO22XLTS U1339 ( .A0(n1588), .A1(DMP_SFG[30]), .B0(n1582), .B1(
DMP_exp_NRM_EW[7]), .Y(n612) );
AO22XLTS U1340 ( .A0(n1615), .A1(DMP_SHT2_EWSW[30]), .B0(n1562), .B1(
DMP_SFG[30]), .Y(n613) );
AO22XLTS U1341 ( .A0(n920), .A1(DMP_SHT1_EWSW[30]), .B0(n1764), .B1(
DMP_SHT2_EWSW[30]), .Y(n614) );
AO22XLTS U1342 ( .A0(n1563), .A1(DMP_EXP_EWSW[30]), .B0(n1564), .B1(
DMP_SHT1_EWSW[30]), .Y(n615) );
AO22XLTS U1343 ( .A0(n1584), .A1(DMP_SFG[29]), .B0(n1582), .B1(
DMP_exp_NRM_EW[6]), .Y(n617) );
AO22XLTS U1344 ( .A0(n1615), .A1(DMP_SHT2_EWSW[29]), .B0(n1562), .B1(
DMP_SFG[29]), .Y(n618) );
AO22XLTS U1345 ( .A0(n920), .A1(DMP_SHT1_EWSW[29]), .B0(n1764), .B1(
DMP_SHT2_EWSW[29]), .Y(n619) );
AO22XLTS U1346 ( .A0(n1563), .A1(DMP_EXP_EWSW[29]), .B0(n1573), .B1(
DMP_SHT1_EWSW[29]), .Y(n620) );
AO22XLTS U1347 ( .A0(n1584), .A1(DMP_SFG[28]), .B0(n1582), .B1(
DMP_exp_NRM_EW[5]), .Y(n622) );
AO22XLTS U1348 ( .A0(n1615), .A1(DMP_SHT2_EWSW[28]), .B0(n1574), .B1(
DMP_SFG[28]), .Y(n623) );
AO22XLTS U1349 ( .A0(n920), .A1(DMP_SHT1_EWSW[28]), .B0(n1764), .B1(
DMP_SHT2_EWSW[28]), .Y(n624) );
AO22XLTS U1350 ( .A0(n1563), .A1(DMP_EXP_EWSW[28]), .B0(n1573), .B1(
DMP_SHT1_EWSW[28]), .Y(n625) );
AO22XLTS U1351 ( .A0(n1584), .A1(DMP_SFG[27]), .B0(n1582), .B1(
DMP_exp_NRM_EW[4]), .Y(n627) );
AO22XLTS U1352 ( .A0(n1615), .A1(DMP_SHT2_EWSW[27]), .B0(n1562), .B1(
DMP_SFG[27]), .Y(n628) );
AO22XLTS U1353 ( .A0(busy), .A1(DMP_SHT1_EWSW[27]), .B0(n1764), .B1(
DMP_SHT2_EWSW[27]), .Y(n629) );
AO22XLTS U1354 ( .A0(n1563), .A1(DMP_EXP_EWSW[27]), .B0(n1573), .B1(
DMP_SHT1_EWSW[27]), .Y(n630) );
AO22XLTS U1355 ( .A0(n1588), .A1(DMP_SFG[26]), .B0(n1582), .B1(
DMP_exp_NRM_EW[3]), .Y(n632) );
AO22XLTS U1356 ( .A0(n1615), .A1(DMP_SHT2_EWSW[26]), .B0(n1562), .B1(
DMP_SFG[26]), .Y(n633) );
AO22XLTS U1357 ( .A0(n1561), .A1(DMP_SHT1_EWSW[26]), .B0(n1764), .B1(
DMP_SHT2_EWSW[26]), .Y(n634) );
AO22XLTS U1358 ( .A0(n1552), .A1(DMP_EXP_EWSW[26]), .B0(n1573), .B1(
DMP_SHT1_EWSW[26]), .Y(n635) );
AO22XLTS U1359 ( .A0(n1588), .A1(DMP_SFG[25]), .B0(n1582), .B1(
DMP_exp_NRM_EW[2]), .Y(n637) );
AO22XLTS U1360 ( .A0(n1615), .A1(DMP_SHT2_EWSW[25]), .B0(n1562), .B1(
DMP_SFG[25]), .Y(n638) );
AO22XLTS U1361 ( .A0(n893), .A1(DMP_SHT1_EWSW[25]), .B0(n894), .B1(
DMP_SHT2_EWSW[25]), .Y(n639) );
AO22XLTS U1362 ( .A0(n1636), .A1(DMP_EXP_EWSW[25]), .B0(n1573), .B1(
DMP_SHT1_EWSW[25]), .Y(n640) );
AO22XLTS U1363 ( .A0(n1584), .A1(DMP_SFG[24]), .B0(n1582), .B1(
DMP_exp_NRM_EW[1]), .Y(n642) );
AO22XLTS U1364 ( .A0(n1615), .A1(DMP_SHT2_EWSW[24]), .B0(n1562), .B1(
DMP_SFG[24]), .Y(n643) );
AO22XLTS U1365 ( .A0(n1561), .A1(DMP_SHT1_EWSW[24]), .B0(n1764), .B1(
DMP_SHT2_EWSW[24]), .Y(n644) );
AO22XLTS U1366 ( .A0(n1636), .A1(DMP_EXP_EWSW[24]), .B0(n1573), .B1(
DMP_SHT1_EWSW[24]), .Y(n645) );
AO22XLTS U1367 ( .A0(n1588), .A1(DMP_SFG[23]), .B0(n1717), .B1(
DMP_exp_NRM_EW[0]), .Y(n647) );
AO22XLTS U1368 ( .A0(n1615), .A1(DMP_SHT2_EWSW[23]), .B0(n1562), .B1(
DMP_SFG[23]), .Y(n648) );
AO22XLTS U1369 ( .A0(n1561), .A1(DMP_SHT1_EWSW[23]), .B0(n894), .B1(
DMP_SHT2_EWSW[23]), .Y(n649) );
AO22XLTS U1370 ( .A0(n1636), .A1(DMP_EXP_EWSW[23]), .B0(n1573), .B1(
DMP_SHT1_EWSW[23]), .Y(n650) );
AO22XLTS U1371 ( .A0(n1561), .A1(DMP_SHT1_EWSW[22]), .B0(n894), .B1(
DMP_SHT2_EWSW[22]), .Y(n652) );
AO22XLTS U1372 ( .A0(n1636), .A1(DMP_EXP_EWSW[22]), .B0(n1573), .B1(
DMP_SHT1_EWSW[22]), .Y(n653) );
AO22XLTS U1373 ( .A0(n1561), .A1(DMP_SHT1_EWSW[21]), .B0(n894), .B1(
DMP_SHT2_EWSW[21]), .Y(n655) );
AO22XLTS U1374 ( .A0(n1636), .A1(DMP_EXP_EWSW[21]), .B0(n1573), .B1(
DMP_SHT1_EWSW[21]), .Y(n656) );
AO22XLTS U1375 ( .A0(n1561), .A1(DMP_SHT1_EWSW[20]), .B0(n894), .B1(
DMP_SHT2_EWSW[20]), .Y(n658) );
AO22XLTS U1376 ( .A0(n1636), .A1(DMP_EXP_EWSW[20]), .B0(n1560), .B1(
DMP_SHT1_EWSW[20]), .Y(n659) );
AO22XLTS U1377 ( .A0(n1561), .A1(DMP_SHT1_EWSW[19]), .B0(n894), .B1(
DMP_SHT2_EWSW[19]), .Y(n661) );
AO22XLTS U1378 ( .A0(n1636), .A1(DMP_EXP_EWSW[19]), .B0(n1560), .B1(
DMP_SHT1_EWSW[19]), .Y(n662) );
AO22XLTS U1379 ( .A0(n1561), .A1(DMP_SHT1_EWSW[18]), .B0(n894), .B1(
DMP_SHT2_EWSW[18]), .Y(n664) );
AO22XLTS U1380 ( .A0(n1636), .A1(DMP_EXP_EWSW[18]), .B0(n1560), .B1(
DMP_SHT1_EWSW[18]), .Y(n665) );
AO22XLTS U1381 ( .A0(n1561), .A1(DMP_SHT1_EWSW[17]), .B0(n894), .B1(
DMP_SHT2_EWSW[17]), .Y(n667) );
AO22XLTS U1382 ( .A0(n1559), .A1(DMP_EXP_EWSW[17]), .B0(n1560), .B1(
DMP_SHT1_EWSW[17]), .Y(n668) );
AO22XLTS U1383 ( .A0(n1561), .A1(DMP_SHT1_EWSW[16]), .B0(n894), .B1(
DMP_SHT2_EWSW[16]), .Y(n670) );
AO22XLTS U1384 ( .A0(n1559), .A1(DMP_EXP_EWSW[16]), .B0(n1560), .B1(
DMP_SHT1_EWSW[16]), .Y(n671) );
AO22XLTS U1385 ( .A0(n893), .A1(DMP_SHT1_EWSW[15]), .B0(n895), .B1(
DMP_SHT2_EWSW[15]), .Y(n673) );
AO22XLTS U1386 ( .A0(n1559), .A1(DMP_EXP_EWSW[15]), .B0(n1560), .B1(
DMP_SHT1_EWSW[15]), .Y(n674) );
AO22XLTS U1387 ( .A0(n893), .A1(DMP_SHT1_EWSW[14]), .B0(n895), .B1(
DMP_SHT2_EWSW[14]), .Y(n676) );
AO22XLTS U1388 ( .A0(n1559), .A1(DMP_EXP_EWSW[14]), .B0(n1560), .B1(
DMP_SHT1_EWSW[14]), .Y(n677) );
AO22XLTS U1389 ( .A0(n893), .A1(DMP_SHT1_EWSW[13]), .B0(n1558), .B1(
DMP_SHT2_EWSW[13]), .Y(n679) );
AO22XLTS U1390 ( .A0(n1559), .A1(DMP_EXP_EWSW[13]), .B0(n1560), .B1(
DMP_SHT1_EWSW[13]), .Y(n680) );
AO22XLTS U1391 ( .A0(n893), .A1(DMP_SHT1_EWSW[12]), .B0(n1558), .B1(
DMP_SHT2_EWSW[12]), .Y(n682) );
AO22XLTS U1392 ( .A0(n1559), .A1(DMP_EXP_EWSW[12]), .B0(n1560), .B1(
DMP_SHT1_EWSW[12]), .Y(n683) );
AO22XLTS U1393 ( .A0(n893), .A1(DMP_SHT1_EWSW[11]), .B0(n1558), .B1(
DMP_SHT2_EWSW[11]), .Y(n685) );
AO22XLTS U1394 ( .A0(n1559), .A1(DMP_EXP_EWSW[11]), .B0(n1560), .B1(
DMP_SHT1_EWSW[11]), .Y(n686) );
AO22XLTS U1395 ( .A0(n893), .A1(DMP_SHT1_EWSW[10]), .B0(n1558), .B1(
DMP_SHT2_EWSW[10]), .Y(n688) );
AO22XLTS U1396 ( .A0(n1559), .A1(DMP_EXP_EWSW[10]), .B0(n1557), .B1(
DMP_SHT1_EWSW[10]), .Y(n689) );
AO22XLTS U1397 ( .A0(n893), .A1(DMP_SHT1_EWSW[9]), .B0(n1558), .B1(
DMP_SHT2_EWSW[9]), .Y(n691) );
AO22XLTS U1398 ( .A0(n1559), .A1(DMP_EXP_EWSW[9]), .B0(n1557), .B1(
DMP_SHT1_EWSW[9]), .Y(n692) );
AO22XLTS U1399 ( .A0(n920), .A1(DMP_SHT1_EWSW[8]), .B0(n1558), .B1(
DMP_SHT2_EWSW[8]), .Y(n694) );
AO22XLTS U1400 ( .A0(n1559), .A1(DMP_EXP_EWSW[8]), .B0(n1557), .B1(
DMP_SHT1_EWSW[8]), .Y(n695) );
AO22XLTS U1401 ( .A0(n920), .A1(DMP_SHT1_EWSW[7]), .B0(n1558), .B1(
DMP_SHT2_EWSW[7]), .Y(n697) );
AO22XLTS U1402 ( .A0(n1556), .A1(DMP_EXP_EWSW[7]), .B0(n1557), .B1(
DMP_SHT1_EWSW[7]), .Y(n698) );
AO22XLTS U1403 ( .A0(busy), .A1(DMP_SHT1_EWSW[6]), .B0(n1558), .B1(
DMP_SHT2_EWSW[6]), .Y(n700) );
AO22XLTS U1404 ( .A0(n1556), .A1(DMP_EXP_EWSW[6]), .B0(n1557), .B1(
DMP_SHT1_EWSW[6]), .Y(n701) );
AO22XLTS U1405 ( .A0(busy), .A1(DMP_SHT1_EWSW[5]), .B0(n1558), .B1(
DMP_SHT2_EWSW[5]), .Y(n703) );
AO22XLTS U1406 ( .A0(n1556), .A1(DMP_EXP_EWSW[5]), .B0(n1557), .B1(
DMP_SHT1_EWSW[5]), .Y(n704) );
AO22XLTS U1407 ( .A0(n920), .A1(DMP_SHT1_EWSW[4]), .B0(n1558), .B1(
DMP_SHT2_EWSW[4]), .Y(n706) );
AO22XLTS U1408 ( .A0(n1556), .A1(DMP_EXP_EWSW[4]), .B0(n1557), .B1(
DMP_SHT1_EWSW[4]), .Y(n707) );
AO22XLTS U1409 ( .A0(n920), .A1(DMP_SHT1_EWSW[3]), .B0(n895), .B1(
DMP_SHT2_EWSW[3]), .Y(n709) );
AO22XLTS U1410 ( .A0(n1556), .A1(DMP_EXP_EWSW[3]), .B0(n1557), .B1(
DMP_SHT1_EWSW[3]), .Y(n710) );
AO22XLTS U1411 ( .A0(n1629), .A1(DMP_SFG[2]), .B0(n1624), .B1(
DMP_SHT2_EWSW[2]), .Y(n711) );
AO22XLTS U1412 ( .A0(n920), .A1(DMP_SHT1_EWSW[2]), .B0(n895), .B1(
DMP_SHT2_EWSW[2]), .Y(n712) );
AO22XLTS U1413 ( .A0(n1556), .A1(DMP_EXP_EWSW[2]), .B0(n1557), .B1(
DMP_SHT1_EWSW[2]), .Y(n713) );
AO22XLTS U1414 ( .A0(busy), .A1(DMP_SHT1_EWSW[1]), .B0(n895), .B1(
DMP_SHT2_EWSW[1]), .Y(n715) );
AO22XLTS U1415 ( .A0(n1556), .A1(DMP_EXP_EWSW[1]), .B0(n1557), .B1(
DMP_SHT1_EWSW[1]), .Y(n716) );
AO22XLTS U1416 ( .A0(busy), .A1(DMP_SHT1_EWSW[0]), .B0(n895), .B1(
DMP_SHT2_EWSW[0]), .Y(n718) );
AO22XLTS U1417 ( .A0(n1556), .A1(DMP_EXP_EWSW[0]), .B0(n1714), .B1(
DMP_SHT1_EWSW[0]), .Y(n719) );
AO22XLTS U1418 ( .A0(n1271), .A1(n1553), .B0(ZERO_FLAG_EXP), .B1(n1554), .Y(
n721) );
AO21XLTS U1419 ( .A0(OP_FLAG_EXP), .A1(n1554), .B0(n1553), .Y(n722) );
OAI21XLTS U1420 ( .A0(n1692), .A1(n1312), .B0(n1283), .Y(n723) );
OAI21XLTS U1421 ( .A0(n1644), .A1(n1312), .B0(n1304), .Y(n731) );
OAI21XLTS U1422 ( .A0(n1681), .A1(n1312), .B0(n1311), .Y(n732) );
OAI21XLTS U1423 ( .A0(n1687), .A1(n1301), .B0(n1300), .Y(n737) );
OAI21XLTS U1424 ( .A0(n1680), .A1(n1301), .B0(n1294), .Y(n740) );
OAI21XLTS U1425 ( .A0(n1685), .A1(n1301), .B0(n1290), .Y(n741) );
OAI21XLTS U1426 ( .A0(n1653), .A1(n1301), .B0(n1298), .Y(n743) );
OAI21XLTS U1427 ( .A0(n1682), .A1(n1301), .B0(n1291), .Y(n745) );
OAI21XLTS U1428 ( .A0(n1642), .A1(n1312), .B0(n1299), .Y(n753) );
AO22XLTS U1429 ( .A0(n1556), .A1(n1146), .B0(n1714), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n762) );
AO22XLTS U1430 ( .A0(n1556), .A1(n1141), .B0(n1714), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n763) );
AO22XLTS U1431 ( .A0(n1552), .A1(n1551), .B0(n1714), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n764) );
AO22XLTS U1432 ( .A0(n1508), .A1(busy), .B0(n1506), .B1(Shift_reg_FLAGS_7[3]), .Y(n866) );
AO22XLTS U1433 ( .A0(n1506), .A1(n1567), .B0(n1508), .B1(n1509), .Y(n869) );
INVX2TS U1434 ( .A(n915), .Y(n1575) );
BUFX3TS U1435 ( .A(left_right_SHT2), .Y(n1401) );
INVX2TS U1436 ( .A(n1368), .Y(n891) );
AND2X4TS U1437 ( .A(n1567), .B(n1058), .Y(n1284) );
BUFX3TS U1438 ( .A(n1284), .Y(n1319) );
BUFX3TS U1439 ( .A(n1084), .Y(n1390) );
CLKINVX3TS U1440 ( .A(rst), .Y(n1137) );
INVX2TS U1441 ( .A(n875), .Y(n890) );
INVX2TS U1442 ( .A(n891), .Y(n892) );
INVX2TS U1443 ( .A(n1764), .Y(n893) );
INVX2TS U1444 ( .A(n893), .Y(n894) );
INVX2TS U1445 ( .A(n893), .Y(n895) );
INVX2TS U1446 ( .A(n896), .Y(n898) );
INVX2TS U1447 ( .A(n884), .Y(n899) );
INVX2TS U1448 ( .A(n884), .Y(n900) );
INVX2TS U1449 ( .A(n885), .Y(n903) );
INVX2TS U1450 ( .A(n885), .Y(n904) );
INVX4TS U1451 ( .A(n1333), .Y(n907) );
INVX4TS U1452 ( .A(n1333), .Y(n908) );
INVX2TS U1453 ( .A(n879), .Y(n909) );
INVX2TS U1454 ( .A(n879), .Y(n910) );
INVX2TS U1455 ( .A(n879), .Y(n911) );
NAND2X1TS U1456 ( .A(n1083), .B(n1082), .Y(n771) );
BUFX3TS U1457 ( .A(n1137), .Y(n1138) );
BUFX3TS U1458 ( .A(n1137), .Y(n1134) );
CLKBUFX3TS U1459 ( .A(n1137), .Y(n1136) );
NOR2X4TS U1460 ( .A(shift_value_SHT2_EWR[4]), .B(n1401), .Y(n1112) );
AOI222X1TS U1461 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n913), .B0(n918), .B1(
DmP_mant_SHT1_SW[15]), .C0(n1360), .C1(DmP_mant_SHT1_SW[16]), .Y(n1373) );
AOI222X1TS U1462 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n913), .B0(n919), .B1(
DmP_mant_SHT1_SW[17]), .C0(n1313), .C1(DmP_mant_SHT1_SW[18]), .Y(n1370) );
AOI222X1TS U1463 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n913), .B0(
DmP_mant_SHT1_SW[14]), .B1(n1313), .C0(n918), .C1(DmP_mant_SHT1_SW[13]), .Y(n1364) );
AOI222X1TS U1464 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n913), .B0(n918), .B1(
DmP_mant_SHT1_SW[11]), .C0(n1360), .C1(DmP_mant_SHT1_SW[12]), .Y(n1367) );
AOI222X1TS U1465 ( .A0(Raw_mant_NRM_SWR[14]), .A1(n913), .B0(n919), .B1(
DmP_mant_SHT1_SW[9]), .C0(n1360), .C1(DmP_mant_SHT1_SW[10]), .Y(n1363)
);
AOI222X4TS U1466 ( .A0(Data_array_SWR[14]), .A1(n902), .B0(
Data_array_SWR[22]), .B1(n876), .C0(Data_array_SWR[18]), .C1(n901),
.Y(n1400) );
AOI222X4TS U1467 ( .A0(Data_array_SWR[23]), .A1(n874), .B0(
Data_array_SWR[19]), .B1(n901), .C0(Data_array_SWR[15]), .C1(n902),
.Y(n1397) );
AOI221X1TS U1468 ( .A0(n1653), .A1(intDX_EWSW[10]), .B0(intDX_EWSW[11]),
.B1(n1660), .C0(n1163), .Y(n1168) );
AOI221X1TS U1469 ( .A0(intDX_EWSW[30]), .A1(n1692), .B0(intDX_EWSW[29]),
.B1(n1645), .C0(n997), .Y(n999) );
AOI221X1TS U1470 ( .A0(n1692), .A1(intDX_EWSW[30]), .B0(intDX_EWSW[17]),
.B1(n1678), .C0(n1154), .Y(n1161) );
NOR2X1TS U1471 ( .A(n1692), .B(intDX_EWSW[30]), .Y(n998) );
OAI211XLTS U1472 ( .A0(n1367), .A1(n910), .B0(n1366), .C0(n1365), .Y(n784)
);
AOI221X1TS U1473 ( .A0(n1683), .A1(intDX_EWSW[2]), .B0(intDX_EWSW[3]), .B1(
n1677), .C0(n1171), .Y(n1176) );
AOI221X1TS U1474 ( .A0(n1644), .A1(intDX_EWSW[22]), .B0(intDX_EWSW[23]),
.B1(n1691), .C0(n1157), .Y(n1158) );
AOI221X1TS U1475 ( .A0(n1686), .A1(intDX_EWSW[14]), .B0(intDX_EWSW[15]),
.B1(n1643), .C0(n1165), .Y(n1166) );
AOI221X1TS U1476 ( .A0(n1688), .A1(intDX_EWSW[20]), .B0(intDX_EWSW[21]),
.B1(n1681), .C0(n1156), .Y(n1159) );
AOI221X1TS U1477 ( .A0(n1685), .A1(intDX_EWSW[12]), .B0(intDX_EWSW[13]),
.B1(n1680), .C0(n1164), .Y(n1167) );
INVX2TS U1478 ( .A(n1595), .Y(n916) );
INVX2TS U1479 ( .A(n1595), .Y(n1611) );
OAI21XLTS U1480 ( .A0(n1240), .A1(n1239), .B0(n1238), .Y(n471) );
OAI21XLTS U1481 ( .A0(n1240), .A1(n1230), .B0(n1229), .Y(n469) );
OAI21XLTS U1482 ( .A0(n1240), .A1(n1234), .B0(n1233), .Y(n467) );
CLKXOR2X2TS U1483 ( .A(n1387), .B(DmP_mant_SFG_SWR[11]), .Y(
DmP_mant_SFG_SWR_signed[11]) );
XOR2X1TS U1484 ( .A(n1387), .B(DmP_mant_SFG_SWR[8]), .Y(n1480) );
XOR2X1TS U1485 ( .A(n1387), .B(DmP_mant_SFG_SWR[9]), .Y(n1483) );
XOR2X1TS U1486 ( .A(n1200), .B(DmP_mant_SFG_SWR[18]), .Y(n981) );
XOR2X1TS U1487 ( .A(n1200), .B(DmP_mant_SFG_SWR[20]), .Y(n984) );
NOR4X4TS U1488 ( .A(n964), .B(n963), .C(n1224), .D(n962), .Y(n970) );
NOR4X2TS U1489 ( .A(n1181), .B(n1180), .C(n1179), .D(n1178), .Y(n1271) );
AFHCINX2TS U1490 ( .CIN(n1427), .B(n1428), .A(DMP_SFG[21]), .S(n1429), .CO(
n1430) );
NOR2X2TS U1491 ( .A(n925), .B(DMP_EXP_EWSW[23]), .Y(n1546) );
AOI21X2TS U1492 ( .A0(Shift_amount_SHT1_EWR[1]), .A1(n877), .B0(n1498), .Y(
n965) );
XNOR2X2TS U1493 ( .A(DMP_exp_NRM2_EW[0]), .B(n878), .Y(n1186) );
BUFX3TS U1494 ( .A(n1137), .Y(n1139) );
OR2X1TS U1495 ( .A(n978), .B(DMP_SFG[14]), .Y(n1454) );
AND2X2TS U1496 ( .A(DMP_SFG[6]), .B(n1480), .Y(n977) );
OAI2BB2XLTS U1497 ( .B0(n1470), .B1(n1469), .A0N(DMP_SFG[5]), .A1N(n1585),
.Y(n1479) );
OAI21XLTS U1498 ( .A0(n1266), .A1(intDX_EWSW[31]), .B0(n1567), .Y(n1182) );
AOI222X4TS U1499 ( .A0(n1601), .A1(left_right_SHT2), .B0(Data_array_SWR[6]),
.B1(n900), .C0(n1600), .C1(n1112), .Y(n1230) );
INVX2TS U1500 ( .A(n949), .Y(n917) );
INVX2TS U1501 ( .A(n949), .Y(n918) );
INVX2TS U1502 ( .A(n949), .Y(n919) );
AOI221X1TS U1503 ( .A0(n1694), .A1(intDX_EWSW[18]), .B0(intDX_EWSW[19]),
.B1(n1646), .C0(n1155), .Y(n1160) );
AOI32X1TS U1504 ( .A0(n1694), .A1(n1042), .A2(intDX_EWSW[18]), .B0(
intDX_EWSW[19]), .B1(n1646), .Y(n1043) );
AOI221X1TS U1505 ( .A0(n1690), .A1(intDX_EWSW[28]), .B0(intDX_EWSW[29]),
.B1(n1645), .C0(n1149), .Y(n1151) );
NOR2X1TS U1506 ( .A(n1645), .B(intDX_EWSW[29]), .Y(n996) );
OAI211XLTS U1507 ( .A0(n1364), .A1(n911), .B0(n1352), .C0(n1351), .Y(n786)
);
NOR3X1TS U1508 ( .A(shift_value_SHT2_EWR[4]), .B(shift_value_SHT2_EWR[2]),
.C(n1652), .Y(n1084) );
INVX2TS U1509 ( .A(n1764), .Y(n920) );
OAI2BB2XLTS U1510 ( .B0(intDY_EWSW[0]), .B1(n1022), .A0N(intDX_EWSW[1]),
.A1N(n1765), .Y(n1024) );
AOI22X1TS U1511 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n941), .B0(n1126), .B1(
Raw_mant_NRM_SWR[10]), .Y(n960) );
NOR2XLTS U1512 ( .A(n1660), .B(intDX_EWSW[11]), .Y(n1002) );
NOR2XLTS U1513 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .Y(n1220)
);
NOR2X1TS U1514 ( .A(n1678), .B(intDX_EWSW[17]), .Y(n1040) );
BUFX3TS U1515 ( .A(n1636), .Y(n921) );
NOR2X4TS U1516 ( .A(shift_value_SHT2_EWR[4]), .B(n1617), .Y(n1604) );
OAI21XLTS U1517 ( .A0(intDX_EWSW[13]), .A1(n1680), .B0(intDX_EWSW[12]), .Y(
n1001) );
OA22X1TS U1518 ( .A0(n1686), .A1(intDX_EWSW[14]), .B0(n1643), .B1(
intDX_EWSW[15]), .Y(n1013) );
OA22X1TS U1519 ( .A0(n1644), .A1(intDX_EWSW[22]), .B0(n1691), .B1(
intDX_EWSW[23]), .Y(n1050) );
OAI21XLTS U1520 ( .A0(intDX_EWSW[3]), .A1(n1677), .B0(intDX_EWSW[2]), .Y(
n1025) );
NOR2X2TS U1521 ( .A(n1067), .B(n1499), .Y(n926) );
OAI21XLTS U1522 ( .A0(intDX_EWSW[1]), .A1(n1765), .B0(intDX_EWSW[0]), .Y(
n1022) );
AND4X1TS U1523 ( .A(n1090), .B(n1089), .C(exp_rslt_NRM2_EW1[4]), .D(n1088),
.Y(n1091) );
AOI2BB2X1TS U1524 ( .B0(n1000), .B1(n1052), .A0N(n999), .A1N(n998), .Y(n1057) );
OR2X1TS U1525 ( .A(n979), .B(DMP_SFG[15]), .Y(n1445) );
INVX2TS U1526 ( .A(n1101), .Y(n1107) );
OR2X1TS U1527 ( .A(n982), .B(DMP_SFG[17]), .Y(n1410) );
NAND2X2TS U1528 ( .A(n1576), .B(n948), .Y(n1533) );
NOR2X1TS U1529 ( .A(n1079), .B(n1078), .Y(intadd_21_B_2_) );
OAI21XLTS U1530 ( .A0(DmP_EXP_EWSW[25]), .A1(n924), .B0(n1548), .Y(n1549) );
NOR2XLTS U1531 ( .A(n926), .B(SIGN_FLAG_SHT1SHT2), .Y(n1384) );
XOR2X1TS U1532 ( .A(n988), .B(n987), .Y(n990) );
BUFX3TS U1533 ( .A(n1514), .Y(n1524) );
OAI211XLTS U1534 ( .A0(n1373), .A1(n910), .B0(n1372), .C0(n1371), .Y(n788)
);
OAI21XLTS U1535 ( .A0(n1240), .A1(n1228), .B0(n1227), .Y(n472) );
OAI211XLTS U1536 ( .A0(n1347), .A1(n908), .B0(n1346), .C0(n1345), .Y(n774)
);
OAI211XLTS U1537 ( .A0(n1370), .A1(n910), .B0(n1358), .C0(n1357), .Y(n790)
);
NOR2X2TS U1538 ( .A(Raw_mant_NRM_SWR[22]), .B(Raw_mant_NRM_SWR[23]), .Y(n955) );
INVX2TS U1539 ( .A(n955), .Y(n929) );
NOR3X2TS U1540 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[19]), .C(
Raw_mant_NRM_SWR[20]), .Y(n1495) );
NAND2X2TS U1541 ( .A(n1489), .B(n1495), .Y(n931) );
NOR2X2TS U1542 ( .A(Raw_mant_NRM_SWR[18]), .B(n931), .Y(n1119) );
NAND2X2TS U1543 ( .A(n1119), .B(n1118), .Y(n933) );
OR2X4TS U1544 ( .A(n933), .B(Raw_mant_NRM_SWR[14]), .Y(n1122) );
NAND2X2TS U1545 ( .A(n959), .B(n1633), .Y(n938) );
NAND2X4TS U1546 ( .A(n957), .B(n1655), .Y(n1217) );
INVX2TS U1547 ( .A(n1217), .Y(n940) );
INVX2TS U1548 ( .A(n931), .Y(n941) );
AOI21X1TS U1549 ( .A0(n1675), .A1(Raw_mant_NRM_SWR[20]), .B0(
Raw_mant_NRM_SWR[22]), .Y(n932) );
NOR2X2TS U1550 ( .A(n1659), .B(n933), .Y(n964) );
INVX2TS U1551 ( .A(n964), .Y(n934) );
OAI31X1TS U1552 ( .A0(Raw_mant_NRM_SWR[9]), .A1(n938), .A2(n1632), .B0(n937),
.Y(n939) );
OAI32X1TS U1553 ( .A0(Raw_mant_NRM_SWR[3]), .A1(Raw_mant_NRM_SWR[1]), .A2(
n1639), .B0(n1634), .B1(Raw_mant_NRM_SWR[3]), .Y(n943) );
NOR2X6TS U1554 ( .A(Raw_mant_NRM_SWR[6]), .B(n1217), .Y(n1490) );
OAI211X1TS U1555 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n943), .B0(n1490), .C0(
n1654), .Y(n944) );
NAND2BX4TS U1556 ( .AN(n945), .B(n944), .Y(n1497) );
NOR2BX4TS U1557 ( .AN(n946), .B(n1497), .Y(n948) );
INVX2TS U1558 ( .A(n1533), .Y(n947) );
AOI22X1TS U1559 ( .A0(n919), .A1(DmP_mant_SHT1_SW[8]), .B0(n1313), .B1(
DmP_mant_SHT1_SW[9]), .Y(n950) );
AOI21X1TS U1560 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n897), .B0(n951), .Y(n1537)
);
INVX2TS U1561 ( .A(n1540), .Y(n1359) );
CLKBUFX2TS U1562 ( .A(n1359), .Y(n1113) );
BUFX3TS U1563 ( .A(n1113), .Y(n1369) );
AOI21X1TS U1564 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n952), .B0(
Raw_mant_NRM_SWR[19]), .Y(n954) );
AOI21X1TS U1565 ( .A0(n956), .A1(n955), .B0(n880), .Y(n963) );
NOR2X1TS U1566 ( .A(Raw_mant_NRM_SWR[3]), .B(Raw_mant_NRM_SWR[2]), .Y(n1121)
);
NOR2X1TS U1567 ( .A(Raw_mant_NRM_SWR[4]), .B(Raw_mant_NRM_SWR[5]), .Y(n1218)
);
OAI21X1TS U1568 ( .A0(Raw_mant_NRM_SWR[6]), .A1(Raw_mant_NRM_SWR[7]), .B0(
n957), .Y(n958) );
OAI21X2TS U1569 ( .A0(n1121), .A1(n1222), .B0(n958), .Y(n1224) );
INVX2TS U1570 ( .A(n959), .Y(n961) );
OAI31X1TS U1571 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1633), .A2(n961), .B0(n960), .Y(n962) );
NOR2X4TS U1572 ( .A(n970), .B(n1575), .Y(n1498) );
NOR2X4TS U1573 ( .A(n1369), .B(n965), .Y(n1333) );
BUFX3TS U1574 ( .A(n1313), .Y(n1360) );
AOI21X1TS U1575 ( .A0(n1369), .A1(Data_array_SWR[8]), .B0(n966), .Y(n967) );
AOI22X1TS U1576 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n890), .B0(n1527), .B1(
DmP_mant_SHT1_SW[19]), .Y(n968) );
AOI21X1TS U1577 ( .A0(n919), .A1(DmP_mant_SHT1_SW[18]), .B0(n969), .Y(n1309)
);
OAI22X1TS U1578 ( .A0(n1379), .A1(n907), .B0(n1634), .B1(n891), .Y(n971) );
AOI21X1TS U1579 ( .A0(n1369), .A1(Data_array_SWR[20]), .B0(n971), .Y(n972)
);
AOI22X1TS U1580 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n1531), .B0(
DmP_mant_SHT1_SW[15]), .B1(n1360), .Y(n973) );
OAI2BB1X1TS U1581 ( .A0N(Raw_mant_NRM_SWR[9]), .A1N(n913), .B0(n973), .Y(
n974) );
AOI21X1TS U1582 ( .A0(DmP_mant_SHT1_SW[14]), .A1(n917), .B0(n974), .Y(n1530)
);
OAI22X1TS U1583 ( .A0(n1306), .A1(n907), .B0(n1702), .B1(n891), .Y(n975) );
AOI21X1TS U1584 ( .A0(n1369), .A1(Data_array_SWR[16]), .B0(n975), .Y(n976)
);
XOR2X1TS U1585 ( .A(n1200), .B(DmP_mant_SFG_SWR[24]), .Y(n1431) );
XOR2X1TS U1586 ( .A(n1200), .B(DmP_mant_SFG_SWR[23]), .Y(n1428) );
XOR2X1TS U1587 ( .A(n1200), .B(DmP_mant_SFG_SWR[22]), .Y(n1425) );
XOR2X1TS U1588 ( .A(n1200), .B(DmP_mant_SFG_SWR[21]), .Y(n1405) );
XOR2X1TS U1589 ( .A(n1387), .B(DmP_mant_SFG_SWR[15]), .Y(n1450) );
XOR2X1TS U1590 ( .A(n1387), .B(DmP_mant_SFG_SWR[14]), .Y(n1459) );
XOR2X1TS U1591 ( .A(n1387), .B(DmP_mant_SFG_SWR[13]), .Y(n1462) );
XOR2X1TS U1592 ( .A(n1387), .B(DmP_mant_SFG_SWR[12]), .Y(n1475) );
XOR2X1TS U1593 ( .A(n1200), .B(DmP_mant_SFG_SWR[16]), .Y(n978) );
XOR2X1TS U1594 ( .A(n1200), .B(DmP_mant_SFG_SWR[17]), .Y(n979) );
NOR2X2TS U1595 ( .A(n981), .B(DMP_SFG[16]), .Y(n1437) );
XOR2X1TS U1596 ( .A(n1200), .B(DmP_mant_SFG_SWR[19]), .Y(n982) );
NOR2X2TS U1597 ( .A(n984), .B(DMP_SFG[18]), .Y(n1418) );
NAND2X1TS U1598 ( .A(n978), .B(DMP_SFG[14]), .Y(n1453) );
INVX2TS U1599 ( .A(n1453), .Y(n1443) );
NAND2X1TS U1600 ( .A(n979), .B(DMP_SFG[15]), .Y(n1444) );
INVX2TS U1601 ( .A(n1444), .Y(n980) );
AOI21X1TS U1602 ( .A0(n1445), .A1(n1443), .B0(n980), .Y(n1434) );
NAND2X1TS U1603 ( .A(n981), .B(DMP_SFG[16]), .Y(n1438) );
NAND2X1TS U1604 ( .A(n982), .B(DMP_SFG[17]), .Y(n1409) );
INVX2TS U1605 ( .A(n1409), .Y(n983) );
NAND2X1TS U1606 ( .A(n984), .B(DMP_SFG[18]), .Y(n1419) );
XOR2X1TS U1607 ( .A(n1387), .B(DmP_mant_SFG_SWR[25]), .Y(n987) );
INVX4TS U1608 ( .A(n989), .Y(n1451) );
NOR2X1TS U1609 ( .A(n1676), .B(intDX_EWSW[25]), .Y(n1053) );
AOI22X1TS U1610 ( .A0(intDX_EWSW[25]), .A1(n1676), .B0(intDX_EWSW[24]), .B1(
n991), .Y(n995) );
OAI21X2TS U1611 ( .A0(intDX_EWSW[26]), .A1(n1689), .B0(n992), .Y(n1148) );
NOR3X1TS U1612 ( .A(n1658), .B(n996), .C(intDY_EWSW[28]), .Y(n997) );
OAI2BB2XLTS U1613 ( .B0(intDY_EWSW[12]), .B1(n1001), .A0N(intDX_EWSW[13]),
.A1N(n1680), .Y(n1012) );
AOI22X1TS U1614 ( .A0(intDX_EWSW[11]), .A1(n1660), .B0(intDX_EWSW[10]), .B1(
n1003), .Y(n1008) );
AOI21X1TS U1615 ( .A0(n1006), .A1(n1005), .B0(n1015), .Y(n1007) );
OAI22X1TS U1616 ( .A0(n1653), .A1(intDX_EWSW[10]), .B0(n1660), .B1(
intDX_EWSW[11]), .Y(n1163) );
INVX2TS U1617 ( .A(n1163), .Y(n1016) );
OAI2BB2XLTS U1618 ( .B0(intDY_EWSW[14]), .B1(n1009), .A0N(intDX_EWSW[15]),
.A1N(n1643), .Y(n1010) );
AOI211X1TS U1619 ( .A0(n1013), .A1(n1012), .B0(n1011), .C0(n1010), .Y(n1014)
);
OAI2BB1X1TS U1620 ( .A0N(n1651), .A1N(intDY_EWSW[5]), .B0(intDX_EWSW[4]),
.Y(n1020) );
OAI22X1TS U1621 ( .A0(intDY_EWSW[4]), .A1(n1020), .B0(n1651), .B1(
intDY_EWSW[5]), .Y(n1031) );
OAI2BB1X1TS U1622 ( .A0N(n1638), .A1N(intDY_EWSW[7]), .B0(intDX_EWSW[6]),
.Y(n1021) );
OAI22X1TS U1623 ( .A0(intDY_EWSW[6]), .A1(n1021), .B0(n1638), .B1(
intDY_EWSW[7]), .Y(n1030) );
AOI22X1TS U1624 ( .A0(intDY_EWSW[7]), .A1(n1638), .B0(intDY_EWSW[6]), .B1(
n1657), .Y(n1028) );
OAI32X1TS U1625 ( .A0(n1031), .A1(n1030), .A2(n1029), .B0(n1028), .B1(n1030),
.Y(n1032) );
OAI21X2TS U1626 ( .A0(intDX_EWSW[18]), .A1(n1694), .B0(n1042), .Y(n1155) );
OAI2BB2XLTS U1627 ( .B0(intDY_EWSW[20]), .B1(n1039), .A0N(intDX_EWSW[21]),
.A1N(n1681), .Y(n1049) );
AOI22X1TS U1628 ( .A0(intDX_EWSW[17]), .A1(n1678), .B0(intDX_EWSW[16]), .B1(
n1041), .Y(n1044) );
OAI32X1TS U1629 ( .A0(n1155), .A1(n1045), .A2(n1044), .B0(n1043), .B1(n1045),
.Y(n1048) );
OAI2BB2XLTS U1630 ( .B0(intDY_EWSW[22]), .B1(n1046), .A0N(intDX_EWSW[23]),
.A1N(n1691), .Y(n1047) );
AOI211X1TS U1631 ( .A0(n1050), .A1(n1049), .B0(n1048), .C0(n1047), .Y(n1055)
);
NAND4BBX1TS U1632 ( .AN(n1148), .BN(n1053), .C(n1052), .D(n1051), .Y(n1054)
);
BUFX3TS U1633 ( .A(n1243), .Y(n1554) );
NOR2X4TS U1634 ( .A(n1058), .B(n1554), .Y(n1245) );
INVX2TS U1635 ( .A(n1287), .Y(n1279) );
AOI22X1TS U1636 ( .A0(intDX_EWSW[3]), .A1(n1319), .B0(DMP_EXP_EWSW[3]), .B1(
n1554), .Y(n1059) );
NOR2X2TS U1637 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1669), .Y(n1504) );
INVX2TS U1638 ( .A(exp_rslt_NRM2_EW1[4]), .Y(n1069) );
INVX2TS U1639 ( .A(Shift_reg_FLAGS_7[0]), .Y(n1187) );
INVX2TS U1640 ( .A(DP_OP_15J28_123_3372_n4), .Y(n1061) );
XNOR2X2TS U1641 ( .A(DMP_exp_NRM2_EW[6]), .B(n1065), .Y(n1090) );
INVX2TS U1642 ( .A(exp_rslt_NRM2_EW1[3]), .Y(n1075) );
INVX2TS U1643 ( .A(exp_rslt_NRM2_EW1[2]), .Y(n1071) );
XNOR2X2TS U1644 ( .A(DMP_exp_NRM2_EW[5]), .B(DP_OP_15J28_123_3372_n4), .Y(
n1089) );
INVX2TS U1645 ( .A(n1065), .Y(n1066) );
XNOR2X2TS U1646 ( .A(DMP_exp_NRM2_EW[7]), .B(n1092), .Y(n1499) );
NAND2X2TS U1647 ( .A(n926), .B(Shift_reg_FLAGS_7[0]), .Y(n1569) );
BUFX3TS U1648 ( .A(n1187), .Y(n1507) );
NAND2X1TS U1649 ( .A(n1507), .B(final_result_ieee[27]), .Y(n1068) );
NAND2X1TS U1650 ( .A(n1507), .B(final_result_ieee[25]), .Y(n1070) );
NAND2X1TS U1651 ( .A(n1507), .B(final_result_ieee[28]), .Y(n1072) );
NAND2X1TS U1652 ( .A(n1507), .B(final_result_ieee[26]), .Y(n1074) );
NAND2X1TS U1653 ( .A(n1507), .B(final_result_ieee[29]), .Y(n1076) );
NOR2XLTS U1654 ( .A(n1661), .B(DmP_mant_SFG_SWR[6]), .Y(n1079) );
AOI22X1TS U1655 ( .A0(n1353), .A1(Raw_mant_NRM_SWR[24]), .B0(n1359), .B1(
Data_array_SWR[0]), .Y(n1083) );
NAND2X1TS U1656 ( .A(n913), .B(Raw_mant_NRM_SWR[23]), .Y(n1081) );
AOI22X1TS U1657 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n890), .B0(n1360), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1080) );
OAI211X1TS U1658 ( .A0(n1715), .A1(n949), .B0(n1081), .C0(n1080), .Y(n1340)
);
AOI22X1TS U1659 ( .A0(n1333), .A1(n1340), .B0(n898), .B1(
Raw_mant_NRM_SWR[25]), .Y(n1082) );
NAND2X2TS U1660 ( .A(shift_value_SHT2_EWR[2]), .B(n1652), .Y(n1108) );
AOI22X1TS U1661 ( .A0(Data_array_SWR[14]), .A1(n901), .B0(Data_array_SWR[10]), .B1(n902), .Y(n1087) );
NOR2X4TS U1662 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n1101) );
AOI22X1TS U1663 ( .A0(Data_array_SWR[22]), .A1(n1103), .B0(
Data_array_SWR[18]), .B1(n876), .Y(n1086) );
NAND2X1TS U1664 ( .A(n1087), .B(n1086), .Y(n1601) );
INVX2TS U1665 ( .A(n1108), .Y(n1102) );
AOI22X1TS U1666 ( .A0(Data_array_SWR[23]), .A1(n1102), .B0(
Data_array_SWR[19]), .B1(n1101), .Y(n1133) );
INVX2TS U1667 ( .A(n1133), .Y(n1600) );
AND4X1TS U1668 ( .A(exp_rslt_NRM2_EW1[3]), .B(exp_rslt_NRM2_EW1[2]), .C(
n1186), .D(exp_rslt_NRM2_EW1[1]), .Y(n1088) );
INVX2TS U1669 ( .A(n1092), .Y(n1093) );
OAI2BB1X2TS U1670 ( .A0N(n927), .A1N(n1094), .B0(Shift_reg_FLAGS_7[0]), .Y(
n1501) );
BUFX3TS U1671 ( .A(n1187), .Y(n1607) );
OAI2BB2XLTS U1672 ( .B0(n1230), .B1(n1611), .A0N(final_result_ieee[17]),
.A1N(n1607), .Y(n498) );
AOI22X1TS U1673 ( .A0(Data_array_SWR[15]), .A1(n901), .B0(Data_array_SWR[11]), .B1(n902), .Y(n1096) );
AOI22X1TS U1674 ( .A0(Data_array_SWR[23]), .A1(n1103), .B0(
Data_array_SWR[19]), .B1(n874), .Y(n1095) );
NAND2X1TS U1675 ( .A(n1096), .B(n1095), .Y(n1599) );
AOI22X1TS U1676 ( .A0(Data_array_SWR[22]), .A1(n1102), .B0(
Data_array_SWR[18]), .B1(n1101), .Y(n1130) );
INVX2TS U1677 ( .A(n1130), .Y(n1598) );
OAI2BB2XLTS U1678 ( .B0(n1236), .B1(n1611), .A0N(final_result_ieee[16]),
.A1N(n1607), .Y(n500) );
AOI22X1TS U1679 ( .A0(Data_array_SWR[17]), .A1(n1390), .B0(
Data_array_SWR[13]), .B1(n1085), .Y(n1098) );
AOI22X1TS U1680 ( .A0(Data_array_SWR[21]), .A1(n876), .B0(Data_array_SWR[25]), .B1(n1103), .Y(n1097) );
NAND2X1TS U1681 ( .A(n1098), .B(n1097), .Y(n1192) );
OR2X1TS U1682 ( .A(shift_value_SHT2_EWR[2]), .B(n1652), .Y(n1106) );
OAI222X4TS U1683 ( .A0(n1721), .A1(n1106), .B0(n1722), .B1(n1108), .C0(n1723), .C1(n1107), .Y(n1201) );
OAI2BB2XLTS U1684 ( .B0(n1228), .B1(n1611), .A0N(final_result_ieee[14]),
.A1N(n1607), .Y(n504) );
AOI22X1TS U1685 ( .A0(Data_array_SWR[21]), .A1(n1101), .B0(
Data_array_SWR[25]), .B1(n1102), .Y(n1111) );
AOI22X1TS U1686 ( .A0(Data_array_SWR[13]), .A1(n901), .B0(Data_array_SWR[9]),
.B1(n1085), .Y(n1100) );
NAND2X1TS U1687 ( .A(Data_array_SWR[17]), .B(n874), .Y(n1099) );
OAI211X1TS U1688 ( .A0(n1111), .A1(n882), .B0(n1100), .C0(n1099), .Y(n1603)
);
AO22X1TS U1689 ( .A0(Data_array_SWR[24]), .A1(n1102), .B0(Data_array_SWR[20]), .B1(n1101), .Y(n1602) );
OAI2BB2XLTS U1690 ( .B0(n1232), .B1(n1611), .A0N(final_result_ieee[18]),
.A1N(n1607), .Y(n496) );
AOI22X1TS U1691 ( .A0(Data_array_SWR[12]), .A1(n1085), .B0(
Data_array_SWR[16]), .B1(n1390), .Y(n1105) );
AOI22X1TS U1692 ( .A0(Data_array_SWR[24]), .A1(n1103), .B0(
Data_array_SWR[20]), .B1(n876), .Y(n1104) );
NAND2X1TS U1693 ( .A(n1105), .B(n1104), .Y(n1195) );
OAI222X4TS U1694 ( .A0(n1718), .A1(n1108), .B0(n1719), .B1(n1107), .C0(n1720), .C1(n1106), .Y(n1207) );
OAI2BB2XLTS U1695 ( .B0(n1239), .B1(n1611), .A0N(final_result_ieee[15]),
.A1N(n1607), .Y(n502) );
AOI22X1TS U1696 ( .A0(Data_array_SWR[12]), .A1(n901), .B0(Data_array_SWR[8]),
.B1(n902), .Y(n1110) );
AOI22X1TS U1697 ( .A0(Data_array_SWR[16]), .A1(n874), .B0(
shift_value_SHT2_EWR[4]), .B1(n1602), .Y(n1109) );
NAND2X1TS U1698 ( .A(n1110), .B(n1109), .Y(n1606) );
INVX2TS U1699 ( .A(n1111), .Y(n1605) );
OAI2BB2XLTS U1700 ( .B0(n1234), .B1(n1611), .A0N(final_result_ieee[19]),
.A1N(n1607), .Y(n494) );
AOI21X1TS U1701 ( .A0(n898), .A1(Raw_mant_NRM_SWR[0]), .B0(n918), .Y(n1525)
);
OAI2BB2XLTS U1702 ( .B0(n1525), .B1(n911), .A0N(n1113), .A1N(
Data_array_SWR[25]), .Y(n796) );
OAI22X1TS U1703 ( .A0(n1709), .A1(n1533), .B0(n1639), .B1(n875), .Y(n1114)
);
OAI2BB2XLTS U1704 ( .B0(n1380), .B1(n910), .A0N(n1113), .A1N(
Data_array_SWR[24]), .Y(n795) );
INVX2TS U1705 ( .A(DmP_mant_SFG_SWR[5]), .Y(n1625) );
INVX2TS U1706 ( .A(n1625), .Y(n1115) );
OAI32X1TS U1707 ( .A0(n877), .A1(Raw_mant_NRM_SWR[14]), .A2(n1120), .B0(
n1119), .B1(n914), .Y(n1124) );
INVX2TS U1708 ( .A(n1222), .Y(n1491) );
AOI21X1TS U1709 ( .A0(n1126), .A1(Raw_mant_NRM_SWR[10]), .B0(n1125), .Y(
n1542) );
AOI22X1TS U1710 ( .A0(Data_array_SWR[14]), .A1(n876), .B0(Data_array_SWR[10]), .B1(n1390), .Y(n1129) );
INVX2TS U1711 ( .A(n1127), .Y(n1208) );
AOI22X1TS U1712 ( .A0(Data_array_SWR[6]), .A1(n1085), .B0(Data_array_SWR[2]),
.B1(n1208), .Y(n1128) );
OAI211X1TS U1713 ( .A0(n1130), .A1(n882), .B0(n1129), .C0(n1128), .Y(n1609)
);
AOI22X1TS U1714 ( .A0(Data_array_SWR[23]), .A1(n904), .B0(n1401), .B1(n1609),
.Y(n1216) );
OAI2BB2XLTS U1715 ( .B0(n1216), .B1(n1611), .A0N(final_result_ieee[21]),
.A1N(n1701), .Y(n490) );
AOI22X1TS U1716 ( .A0(Data_array_SWR[15]), .A1(n874), .B0(Data_array_SWR[11]), .B1(n1390), .Y(n1132) );
AOI22X1TS U1717 ( .A0(Data_array_SWR[7]), .A1(n1085), .B0(Data_array_SWR[3]),
.B1(n1208), .Y(n1131) );
OAI211X1TS U1718 ( .A0(n1133), .A1(n882), .B0(n1132), .C0(n1131), .Y(n1608)
);
AOI22X1TS U1719 ( .A0(Data_array_SWR[22]), .A1(n904), .B0(n906), .B1(n1608),
.Y(n1214) );
OAI2BB2XLTS U1720 ( .B0(n1214), .B1(n1611), .A0N(final_result_ieee[20]),
.A1N(n1701), .Y(n491) );
BUFX3TS U1721 ( .A(n1736), .Y(n1741) );
BUFX3TS U1722 ( .A(n1735), .Y(n1759) );
BUFX3TS U1723 ( .A(n1735), .Y(n1740) );
BUFX3TS U1724 ( .A(n1137), .Y(n1739) );
BUFX3TS U1725 ( .A(n1138), .Y(n1760) );
CLKBUFX2TS U1726 ( .A(n1137), .Y(n1135) );
BUFX3TS U1727 ( .A(n1134), .Y(n1746) );
BUFX3TS U1728 ( .A(n1139), .Y(n1747) );
BUFX3TS U1729 ( .A(n1137), .Y(n1744) );
BUFX3TS U1730 ( .A(n1739), .Y(n1748) );
BUFX3TS U1731 ( .A(n1139), .Y(n1743) );
BUFX3TS U1732 ( .A(n1738), .Y(n1749) );
BUFX3TS U1733 ( .A(n1139), .Y(n1762) );
BUFX3TS U1734 ( .A(n1739), .Y(n1761) );
BUFX3TS U1735 ( .A(n1739), .Y(n1742) );
BUFX3TS U1736 ( .A(n1738), .Y(n1745) );
BUFX3TS U1737 ( .A(n1738), .Y(n1733) );
BUFX3TS U1738 ( .A(n1736), .Y(n1750) );
BUFX3TS U1739 ( .A(n1134), .Y(n1751) );
BUFX3TS U1740 ( .A(n1735), .Y(n1754) );
BUFX3TS U1741 ( .A(n1136), .Y(n1753) );
BUFX3TS U1742 ( .A(n1736), .Y(n1763) );
BUFX3TS U1743 ( .A(n1139), .Y(n1756) );
BUFX3TS U1744 ( .A(n1736), .Y(n1732) );
BUFX3TS U1745 ( .A(n1137), .Y(n1738) );
BUFX3TS U1746 ( .A(n1134), .Y(n1755) );
BUFX3TS U1747 ( .A(n1137), .Y(n1736) );
BUFX3TS U1748 ( .A(n1136), .Y(n1731) );
BUFX3TS U1749 ( .A(n1138), .Y(n1737) );
BUFX3TS U1750 ( .A(n1738), .Y(n1728) );
BUFX3TS U1751 ( .A(n1736), .Y(n1727) );
BUFX3TS U1752 ( .A(n1137), .Y(n1735) );
BUFX3TS U1753 ( .A(n1735), .Y(n1730) );
BUFX3TS U1754 ( .A(n1136), .Y(n1757) );
BUFX3TS U1755 ( .A(n1735), .Y(n1758) );
BUFX3TS U1756 ( .A(n1136), .Y(n1729) );
BUFX3TS U1757 ( .A(n1739), .Y(n1752) );
BUFX3TS U1758 ( .A(n1139), .Y(n1726) );
BUFX3TS U1759 ( .A(n1135), .Y(n1734) );
BUFX3TS U1760 ( .A(n1739), .Y(n1725) );
BUFX3TS U1761 ( .A(n1738), .Y(n1724) );
CLKBUFX2TS U1762 ( .A(n1714), .Y(n1571) );
INVX2TS U1763 ( .A(n1571), .Y(n1556) );
NAND2X1TS U1764 ( .A(DmP_EXP_EWSW[25]), .B(n924), .Y(n1548) );
NOR2X1TS U1765 ( .A(n887), .B(DMP_EXP_EWSW[24]), .Y(n1544) );
OAI22X1TS U1766 ( .A0(n1546), .A1(n1544), .B0(DmP_EXP_EWSW[24]), .B1(n1648),
.Y(n1550) );
AOI22X1TS U1767 ( .A0(DMP_EXP_EWSW[25]), .A1(n1708), .B0(n1548), .B1(n1550),
.Y(n1142) );
NOR2X1TS U1768 ( .A(n889), .B(DMP_EXP_EWSW[26]), .Y(n1143) );
AOI21X1TS U1769 ( .A0(DMP_EXP_EWSW[26]), .A1(n889), .B0(n1143), .Y(n1140) );
XNOR2X1TS U1770 ( .A(n1142), .B(n1140), .Y(n1141) );
OAI22X1TS U1771 ( .A0(n1143), .A1(n1142), .B0(DmP_EXP_EWSW[26]), .B1(n1650),
.Y(n1145) );
XNOR2X1TS U1772 ( .A(DmP_EXP_EWSW[27]), .B(DMP_EXP_EWSW[27]), .Y(n1144) );
XOR2X1TS U1773 ( .A(n1145), .B(n1144), .Y(n1146) );
OAI22X1TS U1774 ( .A0(n1765), .A1(intDX_EWSW[1]), .B0(n1676), .B1(
intDX_EWSW[25]), .Y(n1147) );
AOI221X1TS U1775 ( .A0(n1765), .A1(intDX_EWSW[1]), .B0(intDX_EWSW[25]), .B1(
n1676), .C0(n1147), .Y(n1153) );
AOI221X1TS U1776 ( .A0(n1689), .A1(intDX_EWSW[26]), .B0(intDX_EWSW[27]),
.B1(n1693), .C0(n1148), .Y(n1152) );
OAI22X1TS U1777 ( .A0(n1690), .A1(intDX_EWSW[28]), .B0(n1645), .B1(
intDX_EWSW[29]), .Y(n1149) );
AOI2BB2XLTS U1778 ( .B0(intDX_EWSW[7]), .B1(n1668), .A0N(n1668), .A1N(
intDX_EWSW[7]), .Y(n1150) );
OAI22X1TS U1779 ( .A0(n1692), .A1(intDX_EWSW[30]), .B0(n1678), .B1(
intDX_EWSW[17]), .Y(n1154) );
OAI22X1TS U1780 ( .A0(n1688), .A1(intDX_EWSW[20]), .B0(n1681), .B1(
intDX_EWSW[21]), .Y(n1156) );
OAI22X1TS U1781 ( .A0(n1644), .A1(intDX_EWSW[22]), .B0(n1691), .B1(
intDX_EWSW[23]), .Y(n1157) );
OAI22X1TS U1782 ( .A0(n1635), .A1(intDX_EWSW[24]), .B0(n1679), .B1(
intDX_EWSW[9]), .Y(n1162) );
AOI221X1TS U1783 ( .A0(n1635), .A1(intDX_EWSW[24]), .B0(intDX_EWSW[9]), .B1(
n1679), .C0(n1162), .Y(n1169) );
OAI22X1TS U1784 ( .A0(n1685), .A1(intDX_EWSW[12]), .B0(n1680), .B1(
intDX_EWSW[13]), .Y(n1164) );
OAI22X1TS U1785 ( .A0(n1686), .A1(intDX_EWSW[14]), .B0(n1643), .B1(
intDX_EWSW[15]), .Y(n1165) );
OAI22X1TS U1786 ( .A0(n1687), .A1(intDX_EWSW[16]), .B0(n1642), .B1(
intDX_EWSW[0]), .Y(n1170) );
AOI221X1TS U1787 ( .A0(n1687), .A1(intDX_EWSW[16]), .B0(intDX_EWSW[0]), .B1(
n1642), .C0(n1170), .Y(n1177) );
OAI22X1TS U1788 ( .A0(n1683), .A1(intDX_EWSW[2]), .B0(n1677), .B1(
intDX_EWSW[3]), .Y(n1171) );
OAI22X1TS U1789 ( .A0(n1684), .A1(intDX_EWSW[4]), .B0(n1641), .B1(
intDX_EWSW[5]), .Y(n1172) );
AOI221X1TS U1790 ( .A0(n1684), .A1(intDX_EWSW[4]), .B0(intDX_EWSW[5]), .B1(
n1641), .C0(n1172), .Y(n1175) );
OAI22X1TS U1791 ( .A0(n1682), .A1(intDX_EWSW[8]), .B0(n1667), .B1(
intDX_EWSW[6]), .Y(n1173) );
AOI221X1TS U1792 ( .A0(n1682), .A1(intDX_EWSW[8]), .B0(intDX_EWSW[6]), .B1(
n1667), .C0(n1173), .Y(n1174) );
CLKXOR2X2TS U1793 ( .A(intDY_EWSW[31]), .B(intAS), .Y(n1266) );
AOI21X1TS U1794 ( .A0(n1266), .A1(intDX_EWSW[31]), .B0(n1182), .Y(n1553) );
NAND2X1TS U1795 ( .A(n873), .B(DmP_mant_SFG_SWR[2]), .Y(n1183) );
OAI21X1TS U1796 ( .A0(n873), .A1(DmP_mant_SFG_SWR[2]), .B0(n1183), .Y(n1577)
);
NOR2X2TS U1797 ( .A(n1577), .B(n886), .Y(n1580) );
NOR2BX1TS U1798 ( .AN(n1697), .B(n873), .Y(n1184) );
AOI21X1TS U1799 ( .A0(n873), .A1(DmP_mant_SFG_SWR[3]), .B0(n1184), .Y(n1579)
);
OAI21X1TS U1800 ( .A0(n1580), .A1(DMP_SFG[1]), .B0(n1185), .Y(intadd_21_B_0_) );
INVX2TS U1801 ( .A(n1186), .Y(n1189) );
CLKBUFX2TS U1802 ( .A(n1187), .Y(n1610) );
NAND2X1TS U1803 ( .A(n1507), .B(final_result_ieee[23]), .Y(n1188) );
INVX2TS U1804 ( .A(exp_rslt_NRM2_EW1[1]), .Y(n1191) );
NAND2X1TS U1805 ( .A(n1507), .B(final_result_ieee[24]), .Y(n1190) );
AOI21X1TS U1806 ( .A0(n1201), .A1(n1604), .B0(n1193), .Y(n1596) );
NOR2X4TS U1807 ( .A(n1386), .B(Shift_reg_FLAGS_7[0]), .Y(n1631) );
NAND2X1TS U1808 ( .A(n1240), .B(DmP_mant_SFG_SWR[9]), .Y(n1194) );
AOI21X1TS U1809 ( .A0(n1207), .A1(n1604), .B0(n1196), .Y(n1597) );
NAND2X1TS U1810 ( .A(n1240), .B(DmP_mant_SFG_SWR[8]), .Y(n1197) );
NOR2XLTS U1811 ( .A(n1661), .B(DmP_mant_SFG_SWR[4]), .Y(n1199) );
NOR2X1TS U1812 ( .A(n1199), .B(n1198), .Y(intadd_21_CI) );
CLKXOR2X2TS U1813 ( .A(n1200), .B(DmP_mant_SFG_SWR[10]), .Y(
DmP_mant_SFG_SWR_signed[10]) );
INVX2TS U1814 ( .A(n1201), .Y(n1204) );
AOI22X1TS U1815 ( .A0(Data_array_SWR[12]), .A1(n874), .B0(Data_array_SWR[8]),
.B1(n1390), .Y(n1203) );
AOI22X1TS U1816 ( .A0(Data_array_SWR[4]), .A1(n902), .B0(Data_array_SWR[0]),
.B1(n1208), .Y(n1202) );
OAI211X1TS U1817 ( .A0(n1204), .A1(n882), .B0(n1203), .C0(n1202), .Y(n1613)
);
AOI22X1TS U1818 ( .A0(Data_array_SWR[25]), .A1(n904), .B0(n1401), .B1(n1613),
.Y(n1206) );
NAND2X1TS U1819 ( .A(n1237), .B(DmP_mant_SFG_SWR[25]), .Y(n1205) );
INVX2TS U1820 ( .A(n1207), .Y(n1211) );
AOI22X1TS U1821 ( .A0(Data_array_SWR[13]), .A1(n874), .B0(Data_array_SWR[9]),
.B1(n1390), .Y(n1210) );
AOI22X1TS U1822 ( .A0(Data_array_SWR[5]), .A1(n1085), .B0(Data_array_SWR[1]),
.B1(n1208), .Y(n1209) );
OAI211X1TS U1823 ( .A0(n1211), .A1(n882), .B0(n1210), .C0(n1209), .Y(n1616)
);
AOI22X1TS U1824 ( .A0(Data_array_SWR[24]), .A1(n904), .B0(n1401), .B1(n1616),
.Y(n1612) );
NAND2X1TS U1825 ( .A(n1237), .B(DmP_mant_SFG_SWR[24]), .Y(n1212) );
NAND2X1TS U1826 ( .A(n1237), .B(DmP_mant_SFG_SWR[22]), .Y(n1213) );
NAND2X1TS U1827 ( .A(n1237), .B(DmP_mant_SFG_SWR[23]), .Y(n1215) );
OAI22X1TS U1828 ( .A0(n1220), .A1(n1219), .B0(n1218), .B1(n1217), .Y(n1225)
);
OAI31X1TS U1829 ( .A0(n1225), .A1(n1224), .A2(n1223), .B0(n1576), .Y(n1488)
);
NAND2X1TS U1830 ( .A(n1237), .B(DmP_mant_SFG_SWR[16]), .Y(n1227) );
NAND2X1TS U1831 ( .A(n1237), .B(DmP_mant_SFG_SWR[19]), .Y(n1229) );
NAND2X1TS U1832 ( .A(n1237), .B(DmP_mant_SFG_SWR[20]), .Y(n1231) );
NAND2X1TS U1833 ( .A(n1237), .B(DmP_mant_SFG_SWR[21]), .Y(n1233) );
NAND2X1TS U1834 ( .A(n1237), .B(DmP_mant_SFG_SWR[18]), .Y(n1235) );
NAND2X1TS U1835 ( .A(n1237), .B(DmP_mant_SFG_SWR[17]), .Y(n1238) );
CLKBUFX2TS U1836 ( .A(n1243), .Y(n1274) );
BUFX3TS U1837 ( .A(n1274), .Y(n1505) );
AOI22X1TS U1838 ( .A0(intDX_EWSW[17]), .A1(n1245), .B0(DmP_EXP_EWSW[17]),
.B1(n1505), .Y(n1241) );
BUFX3TS U1839 ( .A(n1554), .Y(n1282) );
AOI22X1TS U1840 ( .A0(intDX_EWSW[0]), .A1(n1245), .B0(DmP_EXP_EWSW[0]), .B1(
n1282), .Y(n1242) );
AOI22X1TS U1841 ( .A0(intDX_EWSW[16]), .A1(n1325), .B0(DmP_EXP_EWSW[16]),
.B1(n1243), .Y(n1244) );
BUFX3TS U1842 ( .A(n1245), .Y(n1325) );
AOI22X1TS U1843 ( .A0(intDX_EWSW[4]), .A1(n1325), .B0(DmP_EXP_EWSW[4]), .B1(
n1282), .Y(n1246) );
AOI22X1TS U1844 ( .A0(intDX_EWSW[6]), .A1(n1325), .B0(DmP_EXP_EWSW[6]), .B1(
n1282), .Y(n1247) );
AOI22X1TS U1845 ( .A0(intDX_EWSW[5]), .A1(n1325), .B0(DmP_EXP_EWSW[5]), .B1(
n1243), .Y(n1248) );
AOI22X1TS U1846 ( .A0(intDX_EWSW[2]), .A1(n1325), .B0(DmP_EXP_EWSW[2]), .B1(
n1282), .Y(n1249) );
AOI22X1TS U1847 ( .A0(intDX_EWSW[1]), .A1(n1325), .B0(DmP_EXP_EWSW[1]), .B1(
n1282), .Y(n1250) );
AOI22X1TS U1848 ( .A0(intDX_EWSW[3]), .A1(n1325), .B0(DmP_EXP_EWSW[3]), .B1(
n1282), .Y(n1251) );
AOI22X1TS U1849 ( .A0(DmP_EXP_EWSW[27]), .A1(n1505), .B0(intDX_EWSW[27]),
.B1(n1325), .Y(n1252) );
AOI22X1TS U1850 ( .A0(intDX_EWSW[7]), .A1(n1263), .B0(DmP_EXP_EWSW[7]), .B1(
n1243), .Y(n1253) );
AOI22X1TS U1851 ( .A0(intDX_EWSW[18]), .A1(n1263), .B0(DmP_EXP_EWSW[18]),
.B1(n1243), .Y(n1254) );
AOI22X1TS U1852 ( .A0(intDX_EWSW[10]), .A1(n1263), .B0(DmP_EXP_EWSW[10]),
.B1(n1282), .Y(n1255) );
AOI22X1TS U1853 ( .A0(intDX_EWSW[14]), .A1(n1263), .B0(DmP_EXP_EWSW[14]),
.B1(n1274), .Y(n1256) );
AOI22X1TS U1854 ( .A0(intDX_EWSW[11]), .A1(n1263), .B0(DmP_EXP_EWSW[11]),
.B1(n1274), .Y(n1257) );
AOI22X1TS U1855 ( .A0(intDX_EWSW[8]), .A1(n1263), .B0(DmP_EXP_EWSW[8]), .B1(
n928), .Y(n1258) );
AOI22X1TS U1856 ( .A0(intDX_EWSW[12]), .A1(n1263), .B0(DmP_EXP_EWSW[12]),
.B1(n1274), .Y(n1259) );
AOI22X1TS U1857 ( .A0(intDX_EWSW[9]), .A1(n1263), .B0(DmP_EXP_EWSW[9]), .B1(
n1243), .Y(n1260) );
AOI22X1TS U1858 ( .A0(intDX_EWSW[13]), .A1(n1263), .B0(DmP_EXP_EWSW[13]),
.B1(n928), .Y(n1262) );
AOI22X1TS U1859 ( .A0(intDX_EWSW[15]), .A1(n1263), .B0(DmP_EXP_EWSW[15]),
.B1(n1505), .Y(n1264) );
INVX2TS U1860 ( .A(n1266), .Y(n1270) );
AOI22X1TS U1861 ( .A0(intDX_EWSW[31]), .A1(n1268), .B0(SIGN_FLAG_EXP), .B1(
n1282), .Y(n1269) );
OAI31X1TS U1862 ( .A0(n1271), .A1(n1270), .A2(n1568), .B0(n1269), .Y(n720)
);
BUFX3TS U1863 ( .A(n1274), .Y(n1310) );
AOI22X1TS U1864 ( .A0(intDX_EWSW[28]), .A1(n1319), .B0(DMP_EXP_EWSW[28]),
.B1(n1310), .Y(n1272) );
AOI22X1TS U1865 ( .A0(intDX_EWSW[1]), .A1(n1324), .B0(DMP_EXP_EWSW[1]), .B1(
n1554), .Y(n1273) );
BUFX3TS U1866 ( .A(n1274), .Y(n1297) );
AOI22X1TS U1867 ( .A0(intDX_EWSW[4]), .A1(n1302), .B0(DMP_EXP_EWSW[4]), .B1(
n1297), .Y(n1275) );
AOI22X1TS U1868 ( .A0(intDX_EWSW[5]), .A1(n1324), .B0(DMP_EXP_EWSW[5]), .B1(
n1297), .Y(n1276) );
AOI22X1TS U1869 ( .A0(intDX_EWSW[6]), .A1(n1324), .B0(DMP_EXP_EWSW[6]), .B1(
n1297), .Y(n1277) );
AOI22X1TS U1870 ( .A0(intDX_EWSW[2]), .A1(n1324), .B0(DMP_EXP_EWSW[2]), .B1(
n1554), .Y(n1278) );
AOI22X1TS U1871 ( .A0(intDX_EWSW[29]), .A1(n1319), .B0(DMP_EXP_EWSW[29]),
.B1(n1282), .Y(n1280) );
AOI22X1TS U1872 ( .A0(intDX_EWSW[18]), .A1(n1302), .B0(DMP_EXP_EWSW[18]),
.B1(n1310), .Y(n1281) );
AOI22X1TS U1873 ( .A0(intDX_EWSW[30]), .A1(n1319), .B0(DMP_EXP_EWSW[30]),
.B1(n1282), .Y(n1283) );
CLKBUFX2TS U1874 ( .A(n1284), .Y(n1324) );
AOI22X1TS U1875 ( .A0(DMP_EXP_EWSW[27]), .A1(n1505), .B0(intDX_EWSW[27]),
.B1(n1324), .Y(n1285) );
AOI22X1TS U1876 ( .A0(DMP_EXP_EWSW[23]), .A1(n1505), .B0(intDX_EWSW[23]),
.B1(n1319), .Y(n1286) );
AOI22X1TS U1877 ( .A0(intDX_EWSW[14]), .A1(n1302), .B0(DMP_EXP_EWSW[14]),
.B1(n1310), .Y(n1288) );
AOI22X1TS U1878 ( .A0(intDX_EWSW[17]), .A1(n1302), .B0(DMP_EXP_EWSW[17]),
.B1(n1310), .Y(n1289) );
AOI22X1TS U1879 ( .A0(intDX_EWSW[12]), .A1(n1302), .B0(DMP_EXP_EWSW[12]),
.B1(n1297), .Y(n1290) );
AOI22X1TS U1880 ( .A0(intDX_EWSW[8]), .A1(n1284), .B0(DMP_EXP_EWSW[8]), .B1(
n1297), .Y(n1291) );
AOI22X1TS U1881 ( .A0(intDX_EWSW[11]), .A1(n1302), .B0(DMP_EXP_EWSW[11]),
.B1(n1310), .Y(n1292) );
AOI22X1TS U1882 ( .A0(intDX_EWSW[15]), .A1(n1302), .B0(DMP_EXP_EWSW[15]),
.B1(n1297), .Y(n1293) );
AOI22X1TS U1883 ( .A0(intDX_EWSW[13]), .A1(n1302), .B0(DMP_EXP_EWSW[13]),
.B1(n1297), .Y(n1294) );
AOI22X1TS U1884 ( .A0(intDX_EWSW[7]), .A1(n1284), .B0(DMP_EXP_EWSW[7]), .B1(
n1297), .Y(n1295) );
AOI22X1TS U1885 ( .A0(intDX_EWSW[9]), .A1(n1284), .B0(DMP_EXP_EWSW[9]), .B1(
n1297), .Y(n1296) );
AOI22X1TS U1886 ( .A0(intDX_EWSW[10]), .A1(n1284), .B0(DMP_EXP_EWSW[10]),
.B1(n1297), .Y(n1298) );
AOI22X1TS U1887 ( .A0(intDX_EWSW[0]), .A1(n1319), .B0(DMP_EXP_EWSW[0]), .B1(
n1554), .Y(n1299) );
AOI22X1TS U1888 ( .A0(intDX_EWSW[16]), .A1(n1302), .B0(DMP_EXP_EWSW[16]),
.B1(n1310), .Y(n1300) );
AOI22X1TS U1889 ( .A0(intDX_EWSW[19]), .A1(n1302), .B0(DMP_EXP_EWSW[19]),
.B1(n1310), .Y(n1303) );
AOI22X1TS U1890 ( .A0(intDX_EWSW[22]), .A1(n1319), .B0(DMP_EXP_EWSW[22]),
.B1(n1310), .Y(n1304) );
AOI22X1TS U1891 ( .A0(intDX_EWSW[20]), .A1(n1319), .B0(DMP_EXP_EWSW[20]),
.B1(n1310), .Y(n1305) );
OAI22X1TS U1892 ( .A0(n1306), .A1(n909), .B0(n1702), .B1(n1383), .Y(n1307)
);
AOI21X1TS U1893 ( .A0(n1369), .A1(Data_array_SWR[18]), .B0(n1307), .Y(n1308)
);
AOI22X1TS U1894 ( .A0(intDX_EWSW[21]), .A1(n1319), .B0(DMP_EXP_EWSW[21]),
.B1(n1310), .Y(n1311) );
AOI22X1TS U1895 ( .A0(n898), .A1(Raw_mant_NRM_SWR[24]), .B0(
DmP_mant_SHT1_SW[0]), .B1(n1313), .Y(n1318) );
AOI22X1TS U1896 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n890), .B0(n1527), .B1(
DmP_mant_SHT1_SW[2]), .Y(n1315) );
AOI22X1TS U1897 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n913), .B0(n917), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1314) );
NAND2X1TS U1898 ( .A(n1315), .B(n1314), .Y(n1344) );
AOI22X1TS U1899 ( .A0(n1359), .A1(Data_array_SWR[1]), .B0(n1333), .B1(n1344),
.Y(n1317) );
NAND2X1TS U1900 ( .A(n1353), .B(Raw_mant_NRM_SWR[23]), .Y(n1316) );
AOI22X1TS U1901 ( .A0(intDX_EWSW[20]), .A1(n1245), .B0(DmP_EXP_EWSW[20]),
.B1(n1505), .Y(n1320) );
AOI22X1TS U1902 ( .A0(intDX_EWSW[21]), .A1(n1245), .B0(DmP_EXP_EWSW[21]),
.B1(n1505), .Y(n1321) );
AOI22X1TS U1903 ( .A0(intDX_EWSW[22]), .A1(n1245), .B0(DmP_EXP_EWSW[22]),
.B1(n1505), .Y(n1322) );
AOI22X1TS U1904 ( .A0(intDX_EWSW[19]), .A1(n1245), .B0(DmP_EXP_EWSW[19]),
.B1(n1505), .Y(n1323) );
AOI222X1TS U1905 ( .A0(n1325), .A1(intDX_EWSW[23]), .B0(DmP_EXP_EWSW[23]),
.B1(n1554), .C0(intDY_EWSW[23]), .C1(n1324), .Y(n1326) );
INVX2TS U1906 ( .A(n1326), .Y(n564) );
AOI22X1TS U1907 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n890), .B0(n1527), .B1(
DmP_mant_SHT1_SW[5]), .Y(n1328) );
AOI22X1TS U1908 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n913), .B0(n919), .B1(
DmP_mant_SHT1_SW[4]), .Y(n1327) );
NAND2X1TS U1909 ( .A(n1328), .B(n1327), .Y(n1336) );
AOI22X1TS U1910 ( .A0(n1359), .A1(Data_array_SWR[4]), .B0(n1333), .B1(n1336),
.Y(n1330) );
NAND2X1TS U1911 ( .A(Raw_mant_NRM_SWR[20]), .B(n1353), .Y(n1329) );
AOI22X1TS U1912 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n890), .B0(n1527), .B1(
DmP_mant_SHT1_SW[6]), .Y(n1332) );
AOI22X1TS U1913 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n913), .B0(n917), .B1(
DmP_mant_SHT1_SW[5]), .Y(n1331) );
NAND2X1TS U1914 ( .A(n1332), .B(n1331), .Y(n1348) );
AOI22X1TS U1915 ( .A0(n1359), .A1(Data_array_SWR[5]), .B0(n1333), .B1(n1348),
.Y(n1335) );
NAND2X1TS U1916 ( .A(Raw_mant_NRM_SWR[19]), .B(n1353), .Y(n1334) );
AOI22X1TS U1917 ( .A0(n1369), .A1(Data_array_SWR[6]), .B0(n879), .B1(n1336),
.Y(n1338) );
NAND2X1TS U1918 ( .A(Raw_mant_NRM_SWR[16]), .B(n892), .Y(n1337) );
AOI22X1TS U1919 ( .A0(n1359), .A1(Data_array_SWR[2]), .B0(n879), .B1(n1340),
.Y(n1342) );
NAND2X1TS U1920 ( .A(Raw_mant_NRM_SWR[20]), .B(n892), .Y(n1341) );
AOI22X1TS U1921 ( .A0(n1359), .A1(Data_array_SWR[3]), .B0(n879), .B1(n1344),
.Y(n1346) );
NAND2X1TS U1922 ( .A(Raw_mant_NRM_SWR[19]), .B(n892), .Y(n1345) );
AOI22X1TS U1923 ( .A0(n1359), .A1(Data_array_SWR[7]), .B0(n879), .B1(n1348),
.Y(n1350) );
NAND2X1TS U1924 ( .A(Raw_mant_NRM_SWR[15]), .B(n892), .Y(n1349) );
AOI22X1TS U1925 ( .A0(n1369), .A1(Data_array_SWR[15]), .B0(
Raw_mant_NRM_SWR[7]), .B1(n1368), .Y(n1352) );
AOI2BB2X1TS U1926 ( .B0(Raw_mant_NRM_SWR[9]), .B1(n1353), .A0N(n1373), .A1N(
n907), .Y(n1351) );
AOI22X1TS U1927 ( .A0(n1113), .A1(Data_array_SWR[9]), .B0(
Raw_mant_NRM_SWR[13]), .B1(n892), .Y(n1355) );
AOI2BB2X1TS U1928 ( .B0(Raw_mant_NRM_SWR[15]), .B1(n1353), .A0N(n1363),
.A1N(n907), .Y(n1354) );
OAI211X1TS U1929 ( .A0(n1356), .A1(n910), .B0(n1355), .C0(n1354), .Y(n780)
);
AOI22X1TS U1930 ( .A0(n1369), .A1(Data_array_SWR[19]), .B0(
Raw_mant_NRM_SWR[3]), .B1(n1368), .Y(n1358) );
OA22X1TS U1931 ( .A0(n1654), .A1(n1383), .B0(n1376), .B1(n907), .Y(n1357) );
AOI22X1TS U1932 ( .A0(n1359), .A1(Data_array_SWR[11]), .B0(
Raw_mant_NRM_SWR[11]), .B1(n1368), .Y(n1362) );
OA22X1TS U1933 ( .A0(n1704), .A1(n1383), .B0(n1367), .B1(n908), .Y(n1361) );
AOI22X1TS U1934 ( .A0(n1369), .A1(Data_array_SWR[13]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n1368), .Y(n1366) );
OA22X1TS U1935 ( .A0(n1633), .A1(n1383), .B0(n1364), .B1(n908), .Y(n1365) );
AOI22X1TS U1936 ( .A0(n1369), .A1(Data_array_SWR[17]), .B0(
Raw_mant_NRM_SWR[5]), .B1(n892), .Y(n1372) );
OA22X1TS U1937 ( .A0(n1655), .A1(n1383), .B0(n1370), .B1(n908), .Y(n1371) );
AOI22X1TS U1938 ( .A0(n919), .A1(DmP_mant_SHT1_SW[21]), .B0(n1527), .B1(
DmP_mant_SHT1_SW[22]), .Y(n1374) );
AOI21X1TS U1939 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n898), .B0(n1375), .Y(n1526)
);
OAI22X1TS U1940 ( .A0(n1376), .A1(n909), .B0(n1647), .B1(n1383), .Y(n1377)
);
AOI21X1TS U1941 ( .A0(n1113), .A1(Data_array_SWR[21]), .B0(n1377), .Y(n1378)
);
OAI22X1TS U1942 ( .A0(n1380), .A1(n908), .B0(n1379), .B1(n909), .Y(n1381) );
AOI21X1TS U1943 ( .A0(n1113), .A1(Data_array_SWR[22]), .B0(n1381), .Y(n1382)
);
OAI2BB2XLTS U1944 ( .B0(n1384), .B1(n1501), .A0N(final_result_ieee[31]),
.A1N(n1507), .Y(n543) );
AOI32X4TS U1945 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n1385), .B1(n1669), .Y(n1508)
);
MXI2X1TS U1946 ( .A(n989), .B(n1386), .S0(n1508), .Y(n865) );
BUFX3TS U1947 ( .A(n1631), .Y(n1403) );
AOI22X1TS U1948 ( .A0(Data_array_SWR[23]), .A1(n901), .B0(Data_array_SWR[19]), .B1(n902), .Y(n1399) );
AOI22X1TS U1949 ( .A0(Data_array_SWR[10]), .A1(n899), .B0(Data_array_SWR[15]), .B1(n903), .Y(n1388) );
OAI221X1TS U1950 ( .A0(n906), .A1(n1399), .B0(n1617), .B1(n1400), .C0(n1388),
.Y(n1594) );
AOI22X1TS U1951 ( .A0(Data_array_SWR[22]), .A1(n901), .B0(Data_array_SWR[18]), .B1(n902), .Y(n1396) );
AOI22X1TS U1952 ( .A0(Data_array_SWR[14]), .A1(n903), .B0(Data_array_SWR[11]), .B1(n899), .Y(n1389) );
OAI221X1TS U1953 ( .A0(n1401), .A1(n1396), .B0(n1617), .B1(n1397), .C0(n1389), .Y(n1592) );
AOI222X1TS U1954 ( .A0(Data_array_SWR[21]), .A1(n901), .B0(
Data_array_SWR[17]), .B1(n902), .C0(Data_array_SWR[25]), .C1(n876),
.Y(n1393) );
AOI222X1TS U1955 ( .A0(Data_array_SWR[24]), .A1(n874), .B0(
Data_array_SWR[20]), .B1(n1390), .C0(Data_array_SWR[16]), .C1(n1085),
.Y(n1394) );
AOI22X1TS U1956 ( .A0(Data_array_SWR[12]), .A1(n899), .B0(Data_array_SWR[13]), .B1(n903), .Y(n1391) );
OAI221X1TS U1957 ( .A0(n906), .A1(n1393), .B0(n1617), .B1(n1394), .C0(n1391),
.Y(n1590) );
AOI22X1TS U1958 ( .A0(Data_array_SWR[12]), .A1(n903), .B0(Data_array_SWR[13]), .B1(n899), .Y(n1392) );
AOI22X1TS U1959 ( .A0(Data_array_SWR[14]), .A1(n899), .B0(Data_array_SWR[11]), .B1(n903), .Y(n1395) );
OAI221X1TS U1960 ( .A0(n1401), .A1(n1397), .B0(n905), .B1(n1396), .C0(n1395),
.Y(n1591) );
AOI22X1TS U1961 ( .A0(Data_array_SWR[10]), .A1(n903), .B0(Data_array_SWR[15]), .B1(n899), .Y(n1398) );
OAI221X1TS U1962 ( .A0(n906), .A1(n1400), .B0(n1617), .B1(n1399), .C0(n1398),
.Y(n1593) );
CLKBUFX2TS U1963 ( .A(n1631), .Y(n1624) );
AFHCINX2TS U1964 ( .CIN(n1404), .B(n1405), .A(DMP_SFG[19]), .S(n1406), .CO(
n1424) );
AOI21X1TS U1965 ( .A0(n1456), .A1(n1408), .B0(n1407), .Y(n1412) );
NAND2X1TS U1966 ( .A(n1410), .B(n1409), .Y(n1411) );
XOR2X1TS U1967 ( .A(n1412), .B(n1411), .Y(n1413) );
INVX2TS U1968 ( .A(n1414), .Y(n1417) );
AOI21X1TS U1969 ( .A0(n1456), .A1(n1417), .B0(n1416), .Y(n1422) );
NAND2X1TS U1970 ( .A(n1420), .B(n1419), .Y(n1421) );
XOR2X1TS U1971 ( .A(n1422), .B(n1421), .Y(n1423) );
AFHCONX2TS U1972 ( .A(DMP_SFG[20]), .B(n1425), .CI(n1424), .CON(n1427), .S(
n1426) );
AFHCONX2TS U1973 ( .A(DMP_SFG[22]), .B(n1431), .CI(n1430), .CON(n988), .S(
n1432) );
INVX2TS U1974 ( .A(n1433), .Y(n1436) );
AOI21X1TS U1975 ( .A0(n1456), .A1(n1436), .B0(n1435), .Y(n1441) );
NAND2X1TS U1976 ( .A(n1439), .B(n1438), .Y(n1440) );
XOR2X1TS U1977 ( .A(n1441), .B(n1440), .Y(n1442) );
AOI21X1TS U1978 ( .A0(n1456), .A1(n1454), .B0(n1443), .Y(n1447) );
NAND2X1TS U1979 ( .A(n1445), .B(n1444), .Y(n1446) );
XOR2X1TS U1980 ( .A(n1447), .B(n1446), .Y(n1448) );
NAND2X1TS U1981 ( .A(n1454), .B(n1453), .Y(n1455) );
XNOR2X1TS U1982 ( .A(n1456), .B(n1455), .Y(n1457) );
INVX4TS U1983 ( .A(n989), .Y(n1486) );
INVX2TS U1984 ( .A(intadd_21_B_2_), .Y(n1468) );
INVX2TS U1985 ( .A(intadd_21_B_1_), .Y(n1466) );
INVX2TS U1986 ( .A(intadd_21_CI), .Y(n1464) );
OAI2BB1X1TS U1987 ( .A0N(n1466), .A1N(DMP_SFG[3]), .B0(n1465), .Y(n1467) );
AOI222X1TS U1988 ( .A0(n1468), .A1(DMP_SFG[4]), .B0(n1468), .B1(n1467), .C0(
DMP_SFG[4]), .C1(n1467), .Y(n1470) );
MXI2X2TS U1989 ( .A(n1695), .B(DmP_mant_SFG_SWR[7]), .S0(n873), .Y(n1585) );
XOR2X1TS U1990 ( .A(DMP_SFG[9]), .B(n1471), .Y(n1472) );
XOR2X1TS U1991 ( .A(DmP_mant_SFG_SWR_signed[11]), .B(n1472), .Y(n1473) );
MXI2X1TS U1992 ( .A(DmP_mant_SFG_SWR[1]), .B(n923), .S0(n873), .Y(n1485) );
MXI2X1TS U1993 ( .A(n1709), .B(n1485), .S0(n1486), .Y(n541) );
MXI2X1TS U1994 ( .A(DmP_mant_SFG_SWR[0]), .B(n922), .S0(n1387), .Y(n1487) );
MXI2X1TS U1995 ( .A(n1639), .B(n1487), .S0(n1486), .Y(n542) );
OAI2BB1X1TS U1996 ( .A0N(LZD_output_NRM2_EW[4]), .A1N(n1575), .B0(n1488),
.Y(n512) );
AOI22X1TS U1997 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n1491), .B0(n1490), .B1(
Raw_mant_NRM_SWR[5]), .Y(n1493) );
OAI21X1TS U1998 ( .A0(n1497), .A1(n1496), .B0(n1576), .Y(n1538) );
OAI2BB1X1TS U1999 ( .A0N(LZD_output_NRM2_EW[2]), .A1N(n1575), .B0(n1538),
.Y(n514) );
OA21XLTS U2000 ( .A0(Shift_reg_FLAGS_7[0]), .A1(overflow_flag), .B0(n1501),
.Y(n558) );
AOI22X1TS U2001 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n1503), .B1(n1640), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U2002 ( .A(n1503), .B(n1502), .Y(n871) );
INVX2TS U2003 ( .A(n1508), .Y(n1506) );
AOI22X1TS U2004 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n1504), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n1640), .Y(n1509) );
BUFX3TS U2005 ( .A(n1714), .Y(n1570) );
AOI22X1TS U2006 ( .A0(n1508), .A1(n1505), .B0(n1570), .B1(n1506), .Y(n868)
);
AOI22X1TS U2007 ( .A0(n1508), .A1(n1570), .B0(n895), .B1(n1506), .Y(n867) );
AOI22X1TS U2008 ( .A0(n1508), .A1(n989), .B0(n914), .B1(n1506), .Y(n864) );
AOI22X1TS U2009 ( .A0(n1508), .A1(n914), .B0(n1507), .B1(n1506), .Y(n863) );
INVX2TS U2010 ( .A(n1514), .Y(n1510) );
BUFX3TS U2011 ( .A(n1514), .Y(n1520) );
INVX2TS U2012 ( .A(n1524), .Y(n1511) );
BUFX3TS U2013 ( .A(n1514), .Y(n1513) );
BUFX3TS U2014 ( .A(n1514), .Y(n1517) );
BUFX3TS U2015 ( .A(n1517), .Y(n1512) );
INVX2TS U2016 ( .A(n1524), .Y(n1523) );
INVX2TS U2017 ( .A(n1517), .Y(n1515) );
BUFX3TS U2018 ( .A(n1514), .Y(n1521) );
INVX2TS U2019 ( .A(n1517), .Y(n1516) );
BUFX3TS U2020 ( .A(n1514), .Y(n1519) );
INVX2TS U2021 ( .A(n1517), .Y(n1518) );
INVX2TS U2022 ( .A(n1524), .Y(n1522) );
OAI222X1TS U2023 ( .A0(n1703), .A1(n1540), .B0(n911), .B1(n1526), .C0(n908),
.C1(n1525), .Y(n794) );
AOI22X1TS U2024 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n890), .B0(n1527), .B1(
DmP_mant_SHT1_SW[13]), .Y(n1528) );
AOI21X1TS U2025 ( .A0(n918), .A1(DmP_mant_SHT1_SW[12]), .B0(n1529), .Y(n1535) );
AOI22X1TS U2026 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1531), .B0(n1313), .B1(
DmP_mant_SHT1_SW[11]), .Y(n1532) );
AOI21X1TS U2027 ( .A0(n919), .A1(DmP_mant_SHT1_SW[10]), .B0(n1534), .Y(n1536) );
NAND2X1TS U2028 ( .A(n1539), .B(n1538), .Y(n770) );
AOI21X1TS U2029 ( .A0(busy), .A1(Shift_amount_SHT1_EWR[3]), .B0(n1576), .Y(
n1541) );
OAI22X1TS U2030 ( .A0(n1542), .A1(n1541), .B0(n1540), .B1(n1652), .Y(n769)
);
INVX2TS U2031 ( .A(n1570), .Y(n1572) );
AOI21X1TS U2032 ( .A0(DMP_EXP_EWSW[23]), .A1(n925), .B0(n1546), .Y(n1543) );
INVX2TS U2033 ( .A(n1571), .Y(n1552) );
AOI21X1TS U2034 ( .A0(DMP_EXP_EWSW[24]), .A1(n887), .B0(n1544), .Y(n1545) );
XNOR2X1TS U2035 ( .A(n1546), .B(n1545), .Y(n1547) );
XNOR2X1TS U2036 ( .A(n1550), .B(n1549), .Y(n1551) );
OAI222X1TS U2037 ( .A0(n1566), .A1(n1707), .B0(n1648), .B1(n1567), .C0(n1635), .C1(n1568), .Y(n729) );
OAI222X1TS U2038 ( .A0(n1566), .A1(n1649), .B0(n924), .B1(n1567), .C0(n1676),
.C1(n1568), .Y(n728) );
OAI222X1TS U2039 ( .A0(n1566), .A1(n1712), .B0(n1650), .B1(n1567), .C0(n1689), .C1(n1568), .Y(n727) );
INVX2TS U2040 ( .A(n1620), .Y(n1562) );
BUFX3TS U2041 ( .A(n1714), .Y(n1557) );
BUFX3TS U2042 ( .A(n895), .Y(n1558) );
BUFX3TS U2043 ( .A(n1631), .Y(n1615) );
INVX2TS U2044 ( .A(n1620), .Y(n1574) );
INVX2TS U2045 ( .A(n1571), .Y(n1559) );
BUFX3TS U2046 ( .A(n1714), .Y(n1560) );
INVX2TS U2047 ( .A(n895), .Y(n1561) );
BUFX3TS U2048 ( .A(n1714), .Y(n1573) );
INVX2TS U2049 ( .A(n989), .Y(n1584) );
BUFX3TS U2050 ( .A(n989), .Y(n1582) );
INVX2TS U2051 ( .A(n1570), .Y(n1563) );
BUFX3TS U2052 ( .A(n1571), .Y(n1564) );
BUFX3TS U2053 ( .A(n1570), .Y(n1565) );
OAI222X1TS U2054 ( .A0(n1568), .A1(n1707), .B0(n887), .B1(n1567), .C0(n1635),
.C1(n1566), .Y(n563) );
OAI222X1TS U2055 ( .A0(n1568), .A1(n1649), .B0(n1708), .B1(n1567), .C0(n1676), .C1(n1566), .Y(n562) );
OAI222X1TS U2056 ( .A0(n1568), .A1(n1712), .B0(n889), .B1(n1567), .C0(n1689),
.C1(n1566), .Y(n561) );
OAI2BB1X1TS U2057 ( .A0N(underflow_flag), .A1N(n1610), .B0(n1569), .Y(n559)
);
AOI22X1TS U2058 ( .A0(n1588), .A1(n1578), .B0(n1634), .B1(n1582), .Y(n540)
);
XOR2X1TS U2059 ( .A(n1579), .B(DMP_SFG[1]), .Y(n1581) );
XNOR2X1TS U2060 ( .A(n1581), .B(n1580), .Y(n1583) );
AOI22X1TS U2061 ( .A0(n1588), .A1(n1583), .B0(n1647), .B1(n1582), .Y(n539)
);
AOI22X1TS U2062 ( .A0(n1588), .A1(intadd_21_SUM_1_), .B0(n1654), .B1(n989),
.Y(n537) );
AOI22X1TS U2063 ( .A0(n1588), .A1(intadd_21_SUM_2_), .B0(n1702), .B1(n989),
.Y(n536) );
XOR2X1TS U2064 ( .A(n1585), .B(DMP_SFG[5]), .Y(n1586) );
XOR2X1TS U2065 ( .A(intadd_21_n1), .B(n1586), .Y(n1587) );
AOI22X1TS U2066 ( .A0(n1588), .A1(n1587), .B0(n1655), .B1(n989), .Y(n535) );
OAI2BB2XLTS U2067 ( .B0(n1596), .B1(n916), .A0N(final_result_ieee[7]), .A1N(
n1701), .Y(n505) );
OAI2BB2XLTS U2068 ( .B0(n1597), .B1(n916), .A0N(final_result_ieee[6]), .A1N(
n1701), .Y(n503) );
OAI2BB2XLTS U2069 ( .B0(n1630), .B1(n1611), .A0N(final_result_ieee[5]),
.A1N(n1607), .Y(n501) );
OAI2BB2XLTS U2070 ( .B0(n1628), .B1(n916), .A0N(final_result_ieee[4]), .A1N(
n1607), .Y(n499) );
OAI2BB2XLTS U2071 ( .B0(n1626), .B1(n916), .A0N(final_result_ieee[3]), .A1N(
n1607), .Y(n497) );
OAI2BB2XLTS U2072 ( .B0(n1623), .B1(n916), .A0N(final_result_ieee[2]), .A1N(
n1607), .Y(n495) );
AOI22X1TS U2073 ( .A0(Data_array_SWR[22]), .A1(n899), .B0(n888), .B1(n1608),
.Y(n1621) );
OAI2BB2XLTS U2074 ( .B0(n1621), .B1(n916), .A0N(final_result_ieee[1]), .A1N(
n1701), .Y(n493) );
AOI22X1TS U2075 ( .A0(Data_array_SWR[23]), .A1(n900), .B0(n905), .B1(n1609),
.Y(n1619) );
OAI2BB2XLTS U2076 ( .B0(n1619), .B1(n916), .A0N(final_result_ieee[0]), .A1N(
n1701), .Y(n492) );
OAI2BB2XLTS U2077 ( .B0(n1612), .B1(n916), .A0N(final_result_ieee[22]),
.A1N(n1610), .Y(n489) );
AOI22X1TS U2078 ( .A0(Data_array_SWR[25]), .A1(n900), .B0(n1617), .B1(n1613),
.Y(n1614) );
AOI22X1TS U2079 ( .A0(n1615), .A1(n1614), .B0(n922), .B1(n1629), .Y(n488) );
AOI22X1TS U2080 ( .A0(Data_array_SWR[24]), .A1(n900), .B0(n1617), .B1(n1616),
.Y(n1618) );
AOI22X1TS U2081 ( .A0(n1620), .A1(n1618), .B0(n923), .B1(n1629), .Y(n487) );
AOI22X1TS U2082 ( .A0(n1620), .A1(n1619), .B0(n1696), .B1(n1629), .Y(n486)
);
AOI22X1TS U2083 ( .A0(n1631), .A1(n1621), .B0(n1697), .B1(n1629), .Y(n485)
);
AOI22X1TS U2084 ( .A0(n1624), .A1(n1623), .B0(n1622), .B1(n1629), .Y(n484)
);
AOI22X1TS U2085 ( .A0(n1631), .A1(n1626), .B0(n1625), .B1(n1629), .Y(n483)
);
AOI22X1TS U2086 ( .A0(n1631), .A1(n1628), .B0(n1627), .B1(n1629), .Y(n482)
);
AOI22X1TS U2087 ( .A0(n1631), .A1(n1630), .B0(n1695), .B1(n1629), .Y(n481)
);
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk10.tcl_ACAIIN16Q8_syn.sdf");
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_4_e
//
// Generated
// by: wig
// on: Mon Jun 26 08:25:04 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../generic.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_4_e.v,v 1.3 2006/06/26 08:39:43 wig Exp $
// $Date: 2006/06/26 08:39:43 $
// $Log: inst_4_e.v,v $
// Revision 1.3 2006/06/26 08:39:43 wig
// Update more testcases (up to generic)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_4_e
//
// No `defines in this module
module inst_4_e
//
// Generated Module inst_4
//
(
);
// Module parameters:
parameter FOO = 10;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of inst_4_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
// megafunction wizard: %Altera PLL v15.1%
// GENERATION: XML
// pll.v
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module pll (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0, // outclk0.clk
output wire outclk_1 // outclk1.clk
);
pll_0002 pll_inst (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.reset
.outclk_0 (outclk_0), // outclk0.clk
.outclk_1 (outclk_1), // outclk1.clk
.locked () // (terminated)
);
endmodule
// Retrieval info: <?xml version="1.0"?>
//<!--
// Generated by Altera MegaWizard Launcher Utility version 1.0
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2016 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_pll" version="15.1" >
// Retrieval info: <generic name="debug_print_output" value="false" />
// Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
// Retrieval info: <generic name="device_family" value="Cyclone V" />
// Retrieval info: <generic name="device" value="5CEBA2F17A7" />
// Retrieval info: <generic name="gui_device_speed_grade" value="1" />
// Retrieval info: <generic name="gui_pll_mode" value="Integer-N PLL" />
// Retrieval info: <generic name="gui_reference_clock_frequency" value="50.0" />
// Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
// Retrieval info: <generic name="gui_operation_mode" value="direct" />
// Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
// Retrieval info: <generic name="gui_fractional_cout" value="32" />
// Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
// Retrieval info: <generic name="gui_use_locked" value="false" />
// Retrieval info: <generic name="gui_en_adv_params" value="false" />
// Retrieval info: <generic name="gui_number_of_clocks" value="2" />
// Retrieval info: <generic name="gui_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_divide_factor_n" value="1" />
// Retrieval info: <generic name="gui_cascade_counter0" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency0" value="25.0" />
// Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units0" value="ps" />
// Retrieval info: <generic name="gui_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg0" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_duty_cycle0" value="50" />
// Retrieval info: <generic name="gui_cascade_counter1" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency1" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units1" value="ps" />
// Retrieval info: <generic name="gui_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg1" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_duty_cycle1" value="50" />
// Retrieval info: <generic name="gui_cascade_counter2" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency2" value="25.0" />
// Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units2" value="ps" />
// Retrieval info: <generic name="gui_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_duty_cycle2" value="50" />
// Retrieval info: <generic name="gui_cascade_counter3" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency3" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units3" value="ps" />
// Retrieval info: <generic name="gui_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_duty_cycle3" value="50" />
// Retrieval info: <generic name="gui_cascade_counter4" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units4" value="ps" />
// Retrieval info: <generic name="gui_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_duty_cycle4" value="50" />
// Retrieval info: <generic name="gui_cascade_counter5" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c5" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units5" value="ps" />
// Retrieval info: <generic name="gui_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_duty_cycle5" value="50" />
// Retrieval info: <generic name="gui_cascade_counter6" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c6" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units6" value="ps" />
// Retrieval info: <generic name="gui_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_duty_cycle6" value="50" />
// Retrieval info: <generic name="gui_cascade_counter7" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c7" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units7" value="ps" />
// Retrieval info: <generic name="gui_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_duty_cycle7" value="50" />
// Retrieval info: <generic name="gui_cascade_counter8" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c8" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units8" value="ps" />
// Retrieval info: <generic name="gui_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_duty_cycle8" value="50" />
// Retrieval info: <generic name="gui_cascade_counter9" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c9" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units9" value="ps" />
// Retrieval info: <generic name="gui_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_duty_cycle9" value="50" />
// Retrieval info: <generic name="gui_cascade_counter10" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units10" value="ps" />
// Retrieval info: <generic name="gui_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_duty_cycle10" value="50" />
// Retrieval info: <generic name="gui_cascade_counter11" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c11" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units11" value="ps" />
// Retrieval info: <generic name="gui_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_duty_cycle11" value="50" />
// Retrieval info: <generic name="gui_cascade_counter12" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c12" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units12" value="ps" />
// Retrieval info: <generic name="gui_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_duty_cycle12" value="50" />
// Retrieval info: <generic name="gui_cascade_counter13" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c13" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units13" value="ps" />
// Retrieval info: <generic name="gui_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_duty_cycle13" value="50" />
// Retrieval info: <generic name="gui_cascade_counter14" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c14" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units14" value="ps" />
// Retrieval info: <generic name="gui_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_duty_cycle14" value="50" />
// Retrieval info: <generic name="gui_cascade_counter15" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c15" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units15" value="ps" />
// Retrieval info: <generic name="gui_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_duty_cycle15" value="50" />
// Retrieval info: <generic name="gui_cascade_counter16" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c16" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units16" value="ps" />
// Retrieval info: <generic name="gui_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_duty_cycle16" value="50" />
// Retrieval info: <generic name="gui_cascade_counter17" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c17" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units17" value="ps" />
// Retrieval info: <generic name="gui_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_duty_cycle17" value="50" />
// Retrieval info: <generic name="gui_pll_auto_reset" value="Off" />
// Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
// Retrieval info: <generic name="gui_en_reconf" value="false" />
// Retrieval info: <generic name="gui_en_dps_ports" value="false" />
// Retrieval info: <generic name="gui_en_phout_ports" value="false" />
// Retrieval info: <generic name="gui_phout_division" value="1" />
// Retrieval info: <generic name="gui_mif_generate" value="false" />
// Retrieval info: <generic name="gui_enable_mif_dps" value="false" />
// Retrieval info: <generic name="gui_dps_cntr" value="C0" />
// Retrieval info: <generic name="gui_dps_num" value="1" />
// Retrieval info: <generic name="gui_dps_dir" value="Positive" />
// Retrieval info: <generic name="gui_refclk_switch" value="false" />
// Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
// Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
// Retrieval info: <generic name="gui_switchover_delay" value="0" />
// Retrieval info: <generic name="gui_active_clk" value="false" />
// Retrieval info: <generic name="gui_clk_bad" value="false" />
// Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
// Retrieval info: <generic name="gui_cascade_outclk_index" value="0" />
// Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
// Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
// Retrieval info: </instance>
// IPFS_FILES : pll.vo
// RELATED_FILES: pll.v, pll_0002.v
|
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: sync_spram_40W_256D.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sync_spram_40W_256D (
address,
clock,
data,
wren,
q);
input [7:0] address;
input clock;
input [39:0] data;
input wren;
output [39:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [39:0] sub_wire0;
wire [39:0] q = sub_wire0[39:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M10K",
altsyncram_component.read_during_write_mode_port_a = "DONT_CARE",
altsyncram_component.widthad_a = 8,
altsyncram_component.width_a = 40,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "2"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
// Retrieval info: PRIVATE: WidthData NUMERIC "40"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M10K"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "40"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 40 0 INPUT NODEFVAL "data[39..0]"
// Retrieval info: USED_PORT: q 0 0 40 0 OUTPUT NODEFVAL "q[39..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 40 0 data 0 0 40 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 40 0 @q_a 0 0 40 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sync_spram_40W_256D.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sync_spram_40W_256D.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sync_spram_40W_256D.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sync_spram_40W_256D.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sync_spram_40W_256D_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sync_spram_40W_256D_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_DFF_P_PP_PG_N_TB_V
`define SKY130_FD_SC_HVL__UDP_DFF_P_PP_PG_N_TB_V
/**
* udp_dff$P_pp$PG$N: Positive edge triggered D flip-flop
* (Q output UDP).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__udp_dff_p_pp_pg_n.v"
module top();
// Inputs are registered
reg D;
reg NOTIFIER;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
NOTIFIER = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 NOTIFIER = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 D = 1'b1;
#120 NOTIFIER = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 D = 1'b0;
#200 NOTIFIER = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 NOTIFIER = 1'b1;
#320 D = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 NOTIFIER = 1'bx;
#400 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N dut (.D(D), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_DFF_P_PP_PG_N_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EINVP_8_V
`define SKY130_FD_SC_LS__EINVP_8_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog wrapper for einvp with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__einvp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__einvp_8 (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__einvp base (
.Z(Z),
.A(A),
.TE(TE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__einvp_8 (
Z ,
A ,
TE
);
output Z ;
input A ;
input TE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__einvp base (
.Z(Z),
.A(A),
.TE(TE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__EINVP_8_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR3B_TB_V
`define SKY130_FD_SC_HDLL__NOR3B_TB_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor3b.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C_N = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C_N = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C_N = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C_N = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C_N = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_hdll__nor3b dut (.A(A), .B(B), .C_N(C_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR3B_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR4B_TB_V
`define SKY130_FD_SC_HDLL__OR4B_TB_V
/**
* or4b: 4-input OR, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__or4b.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D_N = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D_N = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D_N = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D_N = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D_N = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_hdll__or4b dut (.A(A), .B(B), .C(C), .D_N(D_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR4B_TB_V
|
module servo_fsm #(parameter PWM_CYCLES_PER_ITER = 1)(
input wire clk,
input wire rst_n,
// to servo_driver
input wire servo_cycle_done,
output reg[7:0] servo_angle = 8'h80,
// to control unit
input wire move_en, // Enable signal for prevent movements during sonar work
input wire[7:0] start_angle, // [-90 .. 90] in degrees projected to
input wire[7:0] end_angle // [8'h00 .. 8'hFF] angle reg's value
);
// INTERNAL REGISTERS
reg[1:0] state = 0; // FSM current state
reg[1:0] next_state = 0; // FSM next state
parameter WAIT_SERVO = 2'b00;
parameter DIVIDE = 2'b01;
parameter ANGLE_UPD = 2'b10;
parameter DIR_UPD = 2'b11;
reg[8:0] divider = PWM_CYCLES_PER_ITER - 1;
reg servo_dir = 0; // 0 - increasing angle. 1 - decreasing.
/********* Angle control process ************
* Just changes servo angle
* from start angle value to end angle value
* and after this returns angle value to
* it's start value.
* Example: start_val = 1, end_value = 3
* Angle sequence: 1 2 3 2 1 2 3 2 1 ...
*******************************************/
// Assign new state logic
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state = WAIT_SERVO;
end else begin
state = next_state;
end
end
// Next state logic
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
next_state = WAIT_SERVO;
end else begin
case (state)
WAIT_SERVO: begin
if (servo_cycle_done) begin
next_state = DIVIDE;
end
end
DIVIDE: begin
if (divider == 0 && move_en == 1) begin
next_state = ANGLE_UPD;
end else begin
next_state = WAIT_SERVO;
end
end
ANGLE_UPD: begin
next_state = DIR_UPD;
end
DIR_UPD: begin
next_state = WAIT_SERVO;
end
endcase
end
end
// Outputs logic
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
divider = PWM_CYCLES_PER_ITER;
servo_dir = 0;
servo_angle = 8'h80;
end else begin
case (state)
WAIT_SERVO: begin
end
DIVIDE: begin
if (divider == 0) begin
divider = PWM_CYCLES_PER_ITER - 1;
end else begin
divider = divider - 1;
end
end
ANGLE_UPD: begin
if (servo_dir) begin
servo_angle = servo_angle + 1;
end else begin
servo_angle = servo_angle - 1;
end
end
DIR_UPD: begin
if (servo_angle <= start_angle) begin
servo_dir = 1;
end else if (servo_angle >= end_angle) begin
servo_dir = 0;
end
end
endcase
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SEDFXBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__SEDFXBP_BEHAVIORAL_PP_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hdll__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__sedfxbp (
Q ,
Q_N ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire mux_out ;
wire de_d ;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD_delayed, SCE_delayed );
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_hdll__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( awake && ( SCE_delayed === 1'b0 ) && ( DE_delayed === 1'b1 ) );
assign cond2 = ( awake && ( SCE_delayed === 1'b1 ) );
assign cond3 = ( awake && ( DE_delayed === 1'b1 ) && ( D_delayed !== SCD_delayed ) );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SEDFXBP_BEHAVIORAL_PP_V |
module Queue_2(input clk, input reset,
output io_enq_ready,
input io_enq_valid,
input [7:0] io_enq_bits,
input io_deq_ready,
output io_deq_valid,
output[7:0] io_deq_bits,
output[5:0] io_count
);
wire[5:0] T0;
wire[4:0] ptr_diff;
reg [4:0] R1;
wire[4:0] T15;
wire[4:0] T2;
wire[4:0] T3;
wire do_deq;
reg [4:0] R4;
wire[4:0] T16;
wire[4:0] T5;
wire[4:0] T6;
wire do_enq;
wire T7;
wire ptr_match;
reg maybe_full;
wire T17;
wire T8;
wire T9;
wire[7:0] T10;
reg [7:0] ram [31:0];
wire[7:0] T11;
wire T12;
wire empty;
wire T13;
wire T14;
wire full;
`ifndef SYNTHESIS
// synthesis translate_off
integer initvar;
initial begin
#0.002;
R1 = {1{$random}};
R4 = {1{$random}};
maybe_full = {1{$random}};
for (initvar = 0; initvar < 32; initvar = initvar+1)
ram[initvar] = {1{$random}};
end
// synthesis translate_on
`endif
assign io_count = T0;
assign T0 = {T7, ptr_diff};
assign ptr_diff = R4 - R1;
assign T15 = reset ? 5'h0 : T2;
assign T2 = do_deq ? T3 : R1;
assign T3 = R1 + 5'h1;
assign do_deq = io_deq_ready & io_deq_valid;
assign T16 = reset ? 5'h0 : T5;
assign T5 = do_enq ? T6 : R4;
assign T6 = R4 + 5'h1;
assign do_enq = io_enq_ready & io_enq_valid;
assign T7 = maybe_full & ptr_match;
assign ptr_match = R4 == R1;
assign T17 = reset ? 1'h0 : T8;
assign T8 = T9 ? do_enq : maybe_full;
assign T9 = do_enq != do_deq;
assign io_deq_bits = T10;
assign T10 = ram[R1];
assign io_deq_valid = T12;
assign T12 = empty ^ 1'h1;
assign empty = ptr_match & T13;
assign T13 = maybe_full ^ 1'h1;
assign io_enq_ready = T14;
assign T14 = full ^ 1'h1;
assign full = ptr_match & maybe_full;
always @(posedge clk) begin
if(reset) begin
R1 <= 5'h0;
end else if(do_deq) begin
R1 <= T3;
end
if(reset) begin
R4 <= 5'h0;
end else if(do_enq) begin
R4 <= T6;
end
if(reset) begin
maybe_full <= 1'h0;
end else if(T9) begin
maybe_full <= do_enq;
end
if (do_enq)
ram[R4] <= io_enq_bits;
end
endmodule
module SimpleAdderSuite_SimpleAdder_1(input clk, input reset,
output io_dataIn_ready,
input io_dataIn_valid,
input [7:0] io_dataIn_bits_7,
input [7:0] io_dataIn_bits_6,
input [7:0] io_dataIn_bits_5,
input [7:0] io_dataIn_bits_4,
input [7:0] io_dataIn_bits_3,
input [7:0] io_dataIn_bits_2,
input [7:0] io_dataIn_bits_1,
input [7:0] io_dataIn_bits_0,
input [31:0] io_regIn_14,
input [31:0] io_regIn_13,
input [31:0] io_regIn_12,
input [31:0] io_regIn_11,
input [31:0] io_regIn_10,
input [31:0] io_regIn_9,
input [31:0] io_regIn_8,
input [31:0] io_regIn_7,
input [31:0] io_regIn_6,
input [31:0] io_regIn_5,
input [31:0] io_regIn_4,
input [31:0] io_regIn_3,
input [31:0] io_regIn_2,
input [31:0] io_regIn_1,
input [31:0] io_regIn_0,
output[31:0] io_regOut_14,
output[31:0] io_regOut_13,
output[31:0] io_regOut_12,
output[31:0] io_regOut_11,
output[31:0] io_regOut_10,
output[31:0] io_regOut_9,
output[31:0] io_regOut_8,
output[31:0] io_regOut_7,
output[31:0] io_regOut_6,
output[31:0] io_regOut_5,
output[31:0] io_regOut_4,
output[31:0] io_regOut_3,
output[31:0] io_regOut_2,
output[31:0] io_regOut_1,
output[31:0] io_regOut_0,
output io_regOutEn,
output[18:0] io_memAddr,
input [127:0] io_memData,
output io_error,
input io_dataOut_ready,
output io_dataOut_valid,
output[7:0] io_dataOut_bits
);
reg [7:0] R0;
wire[7:0] T1_1;
reg [7:0] addLayer2_1;
wire[7:0] T2_1;
reg [7:0] addLayer1_3;
wire[7:0] T3_1;
reg [7:0] addLayer1_2;
wire[7:0] T4_1;
reg [7:0] addLayer2_0;
wire[7:0] T5_1;
reg [7:0] addLayer1_1;
wire[7:0] T6_1;
reg [7:0] addLayer1_0;
wire[7:0] T7;
reg R8;
reg R9;
reg R10;
wire T11;
wire T12;
wire T13;
wire[31:0] T14;
wire[31:0] T15;
wire[31:0] T16;
wire[31:0] T17;
wire[31:0] T18;
wire[31:0] T19;
wire[31:0] T20;
wire[31:0] T21;
wire[31:0] T22;
wire fifo_io_enq_ready;
wire fifo_io_deq_valid;
wire[7:0] fifo_io_deq_bits;
wire[5:0] fifo_io_count;
`ifndef SYNTHESIS
// synthesis translate_off
integer initvar;
initial begin
#0.002;
R0 = {1{$random}};
addLayer2_1 = {1{$random}};
addLayer1_3 = {1{$random}};
addLayer1_2 = {1{$random}};
addLayer2_0 = {1{$random}};
addLayer1_1 = {1{$random}};
addLayer1_0 = {1{$random}};
R8 = {1{$random}};
R9 = {1{$random}};
R10 = {1{$random}};
end
// synthesis translate_on
`endif
assign T1_1 = addLayer2_0 + addLayer2_1;
assign T2_1 = addLayer1_2 + addLayer1_3;
assign T3_1 = io_dataIn_bits_6 + io_dataIn_bits_7;
assign T4_1 = io_dataIn_bits_4 + io_dataIn_bits_5;
assign T5_1 = addLayer1_0 + addLayer1_1;
assign T6_1 = io_dataIn_bits_2 + io_dataIn_bits_3;
assign T7 = io_dataIn_bits_0 + io_dataIn_bits_1;
assign io_dataOut_bits = fifo_io_deq_bits;
assign io_dataOut_valid = fifo_io_deq_valid;
assign io_error = T11;
assign T11 = T13 | T12;
assign T12 = io_dataOut_ready ^ 1'h1;
assign T13 = fifo_io_enq_ready ^ 1'h1;
assign io_memAddr = 19'h0;
assign io_regOutEn = fifo_io_deq_valid;
assign io_regOut_0 = T14;
assign T14 = {26'h0, fifo_io_count};
assign io_regOut_1 = T15;
assign T15 = {24'h0, io_dataIn_bits_0};
assign io_regOut_2 = T16;
assign T16 = {24'h0, io_dataIn_bits_1};
assign io_regOut_3 = T17;
assign T17 = {24'h0, io_dataIn_bits_2};
assign io_regOut_4 = T18;
assign T18 = {24'h0, io_dataIn_bits_3};
assign io_regOut_5 = T19;
assign T19 = {24'h0, io_dataIn_bits_4};
assign io_regOut_6 = T20;
assign T20 = {24'h0, io_dataIn_bits_5};
assign io_regOut_7 = T21;
assign T21 = {24'h0, io_dataIn_bits_6};
assign io_regOut_8 = T22;
assign T22 = {24'h0, io_dataIn_bits_7};
assign io_regOut_9 = 32'h0;
assign io_regOut_10 = 32'h0;
assign io_regOut_11 = 32'h0;
assign io_regOut_12 = 32'h0;
assign io_regOut_13 = 32'h0;
assign io_regOut_14 = 32'h0;
assign io_dataIn_ready = 1'h1;
Queue_2 fifo(.clk(clk), .reset(reset),
.io_enq_ready( fifo_io_enq_ready ),
.io_enq_valid( R8 ),
.io_enq_bits( R0 ),
.io_deq_ready( io_dataOut_ready ),
.io_deq_valid( fifo_io_deq_valid ),
.io_deq_bits( fifo_io_deq_bits ),
.io_count( fifo_io_count )
);
always @(posedge clk) begin
R0 <= T1_1;
addLayer2_1 <= T2_1;
addLayer1_3 <= T3_1;
addLayer1_2 <= T4_1;
addLayer2_0 <= T5_1;
addLayer1_1 <= T6_1;
addLayer1_0 <= T7;
R8 <= R9;
R9 <= R10;
R10 <= io_dataIn_valid;
end
endmodule
module StripCrc(input clk, input reset,
input [63:0] io_in_data,
input io_in_sof,
input io_in_eof,
input [2:0] io_in_len,
input io_in_vld,
output[63:0] io_out_data,
output io_out_sof,
output io_out_eof,
output[2:0] io_out_len,
output io_out_vld
);
wire T0;
wire T1;
wire T2;
wire T3;
reg [2:0] frame_len;
wire[2:0] initVal_len;
wire[2:0] T43;
wire[2:0] T4;
wire T5;
reg frame_eof;
wire initVal_eof;
wire T44;
wire T6;
wire T7;
wire T8;
wire T9;
reg frame_vld;
wire initVal_vld;
wire T45;
wire T10;
wire T11;
wire T12;
wire T13;
wire[2:0] T14;
wire[2:0] T15;
wire[2:0] T16;
wire T17;
wire T18;
wire T19;
wire T20;
wire[2:0] T21;
wire T22;
wire T23;
wire T24;
wire T25;
wire T26;
wire T27;
wire T28;
wire T29;
wire T30;
wire T31;
wire T32;
wire T33;
wire T34;
wire T35;
wire T36;
wire T37;
wire T38;
wire T39;
wire T40;
reg frame_sof;
wire initVal_sof;
wire T46;
wire T41;
reg [63:0] frame_data;
wire[63:0] initVal_data;
wire[63:0] T47;
wire[63:0] T42;
`ifndef SYNTHESIS
// synthesis translate_off
integer initvar;
initial begin
#0.002;
frame_len = {1{$random}};
frame_eof = {1{$random}};
frame_vld = {1{$random}};
frame_sof = {1{$random}};
frame_data = {2{$random}};
end
// synthesis translate_on
`endif
assign io_out_vld = T0;
assign T0 = T11 | T1;
assign T1 = T9 & T2;
assign T2 = T8 | T3;
assign T3 = 3'h4 < frame_len;
assign initVal_len = 3'h0;
assign T43 = reset ? initVal_len : T4;
assign T4 = T5 ? io_in_len : frame_len;
assign T5 = T7 | frame_eof;
assign initVal_eof = 1'h0;
assign T44 = reset ? initVal_eof : T6;
assign T6 = T5 ? io_in_eof : frame_eof;
assign T7 = io_in_vld | io_in_eof;
assign T8 = frame_len == 3'h0;
assign T9 = frame_eof & frame_vld;
assign initVal_vld = 1'h0;
assign T45 = reset ? initVal_vld : T10;
assign T10 = T5 ? io_in_vld : frame_vld;
assign T11 = T13 | T12;
assign T12 = frame_vld & io_in_eof;
assign T13 = frame_vld & io_in_vld;
assign io_out_len = T14;
assign T14 = T22 ? T21 : T15;
assign T15 = T17 ? T16 : 3'h0;
assign T16 = io_in_len - 3'h4;
assign T17 = T19 & T18;
assign T18 = io_in_len != 3'h0;
assign T19 = io_in_eof & T20;
assign T20 = io_in_len < 3'h5;
assign T21 = frame_len - 3'h4;
assign T22 = frame_eof & T23;
assign T23 = T25 | T24;
assign T24 = frame_len == 3'h0;
assign T25 = 3'h4 < frame_len;
assign io_out_eof = T26;
assign T26 = T32 | T27;
assign T27 = T29 & T28;
assign T28 = io_in_len != 3'h0;
assign T29 = T31 & T30;
assign T30 = io_in_len < 3'h5;
assign T31 = io_in_eof & io_in_vld;
assign T32 = T38 | T33;
assign T33 = T37 & T34;
assign T34 = T36 | T35;
assign T35 = 3'h4 < frame_len;
assign T36 = frame_len == 3'h0;
assign T37 = frame_eof & frame_vld;
assign T38 = frame_vld & T39;
assign T39 = T40 & io_in_eof;
assign T40 = io_in_vld ^ 1'h1;
assign io_out_sof = frame_sof;
assign initVal_sof = 1'h0;
assign T46 = reset ? initVal_sof : T41;
assign T41 = T5 ? io_in_sof : frame_sof;
assign io_out_data = frame_data;
assign initVal_data = 64'h0;
assign T47 = reset ? initVal_data : T42;
assign T42 = T5 ? io_in_data : frame_data;
always @(posedge clk) begin
if(reset) begin
frame_len <= initVal_len;
end else if(T5) begin
frame_len <= io_in_len;
end
if(reset) begin
frame_eof <= initVal_eof;
end else if(T5) begin
frame_eof <= io_in_eof;
end
if(reset) begin
frame_vld <= initVal_vld;
end else if(T5) begin
frame_vld <= io_in_vld;
end
if(reset) begin
frame_sof <= initVal_sof;
end else if(T5) begin
frame_sof <= io_in_sof;
end
if(reset) begin
frame_data <= initVal_data;
end else if(T5) begin
frame_data <= io_in_data;
end
end
endmodule
module DataCombiner(input clk, input reset,
input [7:0] io_dataIn_7,
input [7:0] io_dataIn_6,
input [7:0] io_dataIn_5,
input [7:0] io_dataIn_4,
input [7:0] io_dataIn_3,
input [7:0] io_dataIn_2,
input [7:0] io_dataIn_1,
input [7:0] io_dataIn_0,
input io_vld,
input [2:0] io_len,
output[7:0] io_dataOut_7,
output[7:0] io_dataOut_6,
output[7:0] io_dataOut_5,
output[7:0] io_dataOut_4,
output[7:0] io_dataOut_3,
output[7:0] io_dataOut_2,
output[7:0] io_dataOut_1,
output[7:0] io_dataOut_0,
output io_vldOut
);
wire T0;
wire[2:0] T1;
wire[63:0] T2;
wire T3;
wire[2:0] T4;
reg [2:0] count;
wire[2:0] T452;
wire[3:0] T453;
wire[3:0] T5;
wire[3:0] T6;
wire[3:0] T454;
wire[3:0] total;
wire[3:0] T7;
wire[3:0] T8;
wire[3:0] T9;
wire[3:0] T455;
wire[3:0] T10;
wire[3:0] T456;
wire[2:0] T11;
wire T12;
wire[79:0] T13;
wire T14;
wire[3:0] T15;
wire[87:0] T16;
wire T17;
wire T18;
wire T19;
wire T20;
wire[7:0] T21;
reg [7:0] store_0;
wire[7:0] T22;
wire[7:0] T23;
wire[7:0] T24;
wire[7:0] T25;
wire[7:0] T26;
wire T27;
wire[2:0] T28;
wire[2:0] T29;
wire[7:0] T30;
wire T31;
wire T32;
wire[7:0] T33;
wire[7:0] T34;
wire T35;
wire[7:0] T36;
wire T37;
wire T38;
wire T39;
wire T40;
wire T41;
wire T42;
wire[2:0] T43;
wire T44;
wire[7:0] T45;
wire[7:0] T46;
wire[7:0] T47;
wire T48;
wire[2:0] T49;
wire[2:0] T457;
wire[3:0] T50;
wire[3:0] T51;
wire[3:0] T458;
wire[7:0] T52;
wire T53;
wire T54;
wire[7:0] T55;
wire[7:0] T56;
wire T57;
wire[7:0] T58;
wire T59;
wire T60;
wire T61;
wire T62;
wire[7:0] T63;
wire[7:0] T64;
wire[7:0] T65;
wire T66;
wire[2:0] T67;
wire[2:0] T459;
wire[3:0] T68;
wire[3:0] T460;
wire[7:0] T69;
wire T70;
wire T71;
wire[7:0] T72;
wire[7:0] T73;
wire T74;
wire[7:0] T75;
wire T76;
wire T77;
wire T78;
wire T79;
wire[7:0] T80;
reg [7:0] store_1;
wire[7:0] T81;
wire[7:0] T82;
wire[7:0] T83;
wire[7:0] T84;
wire[7:0] T85;
wire T86;
wire[2:0] T87;
wire[2:0] T88;
wire[7:0] T89;
wire T90;
wire T91;
wire[7:0] T92;
wire[7:0] T93;
wire T94;
wire[7:0] T95;
wire T96;
wire T97;
wire T98;
wire T99;
wire T100;
wire T101;
wire[2:0] T102;
wire T103;
wire[7:0] T104;
wire[7:0] T105;
wire[7:0] T106;
wire T107;
wire[2:0] T108;
wire[2:0] T461;
wire[3:0] T109;
wire[3:0] T110;
wire[3:0] T462;
wire[7:0] T111;
wire T112;
wire T113;
wire[7:0] T114;
wire[7:0] T115;
wire T116;
wire[7:0] T117;
wire T118;
wire T119;
wire T120;
wire T121;
wire[7:0] T122;
wire[7:0] T123;
wire[7:0] T124;
wire T125;
wire[2:0] T126;
wire[2:0] T463;
wire[3:0] T127;
wire[3:0] T464;
wire[7:0] T128;
wire T129;
wire T130;
wire[7:0] T131;
wire[7:0] T132;
wire T133;
wire[7:0] T134;
wire T135;
wire T136;
wire T137;
wire T138;
wire[7:0] T139;
reg [7:0] store_2;
wire[7:0] T140;
wire[7:0] T141;
wire[7:0] T142;
wire[7:0] T143;
wire[7:0] T144;
wire T145;
wire[2:0] T146;
wire[2:0] T147;
wire[7:0] T148;
wire T149;
wire T150;
wire[7:0] T151;
wire[7:0] T152;
wire T153;
wire[7:0] T154;
wire T155;
wire T156;
wire T157;
wire T158;
wire T159;
wire T160;
wire[2:0] T161;
wire T162;
wire[7:0] T163;
wire[7:0] T164;
wire[7:0] T165;
wire T166;
wire[2:0] T167;
wire[2:0] T465;
wire[3:0] T168;
wire[3:0] T169;
wire[3:0] T466;
wire[7:0] T170;
wire T171;
wire T172;
wire[7:0] T173;
wire[7:0] T174;
wire T175;
wire[7:0] T176;
wire T177;
wire T178;
wire T179;
wire T180;
wire[7:0] T181;
wire[7:0] T182;
wire[7:0] T183;
wire T184;
wire[2:0] T185;
wire[2:0] T467;
wire[3:0] T186;
wire[3:0] T468;
wire[7:0] T187;
wire T188;
wire T189;
wire[7:0] T190;
wire[7:0] T191;
wire T192;
wire[7:0] T193;
wire T194;
wire T195;
wire T196;
wire T197;
wire[7:0] T198;
reg [7:0] store_3;
wire[7:0] T199;
wire[7:0] T200;
wire[7:0] T201;
wire[7:0] T202;
wire[7:0] T203;
wire T204;
wire[2:0] T205;
wire[2:0] T206;
wire[7:0] T207;
wire T208;
wire T209;
wire[7:0] T210;
wire[7:0] T211;
wire T212;
wire[7:0] T213;
wire T214;
wire T215;
wire T216;
wire T217;
wire T218;
wire T219;
wire[2:0] T220;
wire T221;
wire[7:0] T222;
wire[7:0] T223;
wire[7:0] T224;
wire T225;
wire[2:0] T226;
wire[2:0] T469;
wire[3:0] T227;
wire[3:0] T228;
wire[3:0] T470;
wire[7:0] T229;
wire T230;
wire T231;
wire[7:0] T232;
wire[7:0] T233;
wire T234;
wire[7:0] T235;
wire T236;
wire T237;
wire T238;
wire T239;
wire[7:0] T240;
wire[7:0] T241;
wire[7:0] T242;
wire T243;
wire[2:0] T244;
wire[2:0] T471;
wire[3:0] T245;
wire[3:0] T472;
wire[7:0] T246;
wire T247;
wire T248;
wire[7:0] T249;
wire[7:0] T250;
wire T251;
wire[7:0] T252;
wire T253;
wire T254;
wire T255;
wire T256;
wire[7:0] T257;
reg [7:0] store_4;
wire[7:0] T258;
wire[7:0] T259;
wire[7:0] T260;
wire[7:0] T261;
wire[7:0] T262;
wire T263;
wire[2:0] T264;
wire[2:0] T265;
wire[7:0] T266;
wire T267;
wire T268;
wire[7:0] T269;
wire[7:0] T270;
wire T271;
wire[7:0] T272;
wire T273;
wire T274;
wire T275;
wire T276;
wire T277;
wire T278;
wire[2:0] T279;
wire T280;
wire[7:0] T281;
wire[7:0] T282;
wire[7:0] T283;
wire T284;
wire[2:0] T285;
wire[2:0] T473;
wire[3:0] T286;
wire[3:0] T287;
wire[3:0] T474;
wire[7:0] T288;
wire T289;
wire T290;
wire[7:0] T291;
wire[7:0] T292;
wire T293;
wire[7:0] T294;
wire T295;
wire T296;
wire T297;
wire T298;
wire[7:0] T299;
wire[7:0] T300;
wire[7:0] T301;
wire T302;
wire[2:0] T303;
wire[2:0] T475;
wire[3:0] T304;
wire[3:0] T476;
wire[7:0] T305;
wire T306;
wire T307;
wire[7:0] T308;
wire[7:0] T309;
wire T310;
wire[7:0] T311;
wire T312;
wire T313;
wire T314;
wire T315;
wire[7:0] T316;
reg [7:0] store_5;
wire[7:0] T317;
wire[7:0] T318;
wire[7:0] T319;
wire[7:0] T320;
wire[7:0] T321;
wire T322;
wire[2:0] T323;
wire[2:0] T324;
wire[7:0] T325;
wire T326;
wire T327;
wire[7:0] T328;
wire[7:0] T329;
wire T330;
wire[7:0] T331;
wire T332;
wire T333;
wire T334;
wire T335;
wire T336;
wire T337;
wire[2:0] T338;
wire T339;
wire[7:0] T340;
wire[7:0] T341;
wire[7:0] T342;
wire T343;
wire[2:0] T344;
wire[2:0] T477;
wire[3:0] T345;
wire[3:0] T346;
wire[3:0] T478;
wire[7:0] T347;
wire T348;
wire T349;
wire[7:0] T350;
wire[7:0] T351;
wire T352;
wire[7:0] T353;
wire T354;
wire T355;
wire T356;
wire T357;
wire[7:0] T358;
wire[7:0] T359;
wire[7:0] T360;
wire T361;
wire[2:0] T362;
wire[2:0] T479;
wire[3:0] T363;
wire[3:0] T480;
wire[7:0] T364;
wire T365;
wire T366;
wire[7:0] T367;
wire[7:0] T368;
wire T369;
wire[7:0] T370;
wire T371;
wire T372;
wire T373;
wire T374;
wire[7:0] T375;
reg [7:0] store_6;
wire[7:0] T376;
wire[7:0] T377;
wire[7:0] T378;
wire[7:0] T379;
wire[7:0] T380;
wire T381;
wire[2:0] T382;
wire[2:0] T383;
wire[7:0] T384;
wire T385;
wire T386;
wire[7:0] T387;
wire[7:0] T388;
wire T389;
wire[7:0] T390;
wire T391;
wire T392;
wire T393;
wire T394;
wire T395;
wire T396;
wire[2:0] T397;
wire T398;
wire[7:0] T399;
wire[7:0] T400;
wire[7:0] T401;
wire T402;
wire[2:0] T403;
wire[2:0] T481;
wire[3:0] T404;
wire[3:0] T405;
wire[3:0] T482;
wire[7:0] T406;
wire T407;
wire T408;
wire[7:0] T409;
wire[7:0] T410;
wire T411;
wire[7:0] T412;
wire T413;
wire T414;
wire T415;
wire T416;
wire[7:0] T417;
wire[7:0] T418;
wire[7:0] T419;
wire T420;
wire[2:0] T421;
wire[2:0] T483;
wire[3:0] T422;
wire[3:0] T484;
wire[7:0] T423;
wire T424;
wire T425;
wire[7:0] T426;
wire[7:0] T427;
wire T428;
wire[7:0] T429;
wire T430;
wire T431;
wire T432;
wire T433;
wire[7:0] T434;
wire[7:0] T435;
wire[7:0] T436;
wire[7:0] T437;
wire T438;
wire[2:0] T439;
wire[2:0] T485;
wire[3:0] T440;
wire[3:0] T486;
wire[7:0] T441;
wire T442;
wire T443;
wire[7:0] T444;
wire[7:0] T445;
wire T446;
wire[7:0] T447;
wire T448;
wire T449;
wire T450;
wire T451;
`ifndef SYNTHESIS
// synthesis translate_off
integer initvar;
initial begin
#0.002;
count = {1{$random}};
store_0 = {1{$random}};
store_1 = {1{$random}};
store_2 = {1{$random}};
store_3 = {1{$random}};
store_4 = {1{$random}};
store_5 = {1{$random}};
store_6 = {1{$random}};
end
// synthesis translate_on
`endif
assign T0 = reset ^ 1'h1;
assign T1 = io_len;
assign T3 = reset ^ 1'h1;
assign T4 = count;
assign T452 = T453[2:0];
assign T453 = reset ? 4'h0 : T5;
assign T5 = T12 ? T456 : T6;
assign T6 = io_vld ? total : T454;
assign T454 = {1'h0, count};
assign total = T7;
assign T7 = io_vld ? T9 : T8;
assign T8 = {1'h0, count};
assign T9 = T10 + T455;
assign T455 = {1'h0, io_len};
assign T10 = {1'h0, count};
assign T456 = {1'h0, T11};
assign T11 = count + io_len;
assign T12 = io_vld & io_vldOut;
assign T14 = reset ^ 1'h1;
assign T15 = total;
assign io_vldOut = T17;
assign T17 = T20 | T18;
assign T18 = io_vld & T19;
assign T19 = io_len == 3'h0;
assign T20 = 4'h7 < total;
assign io_dataOut_0 = T21;
assign T21 = T79 ? T63 : store_0;
assign T22 = T62 ? T45 : T23;
assign T23 = T40 ? T24 : store_0;
assign T24 = T39 ? T33 : T25;
assign T25 = T32 ? T30 : T26;
assign T26 = T27 ? io_dataIn_1 : io_dataIn_0;
assign T27 = T28[0];
assign T28 = T29;
assign T29 = 3'h0 - count;
assign T30 = T31 ? io_dataIn_3 : io_dataIn_2;
assign T31 = T28[0];
assign T32 = T28[1];
assign T33 = T38 ? T36 : T34;
assign T34 = T35 ? io_dataIn_5 : io_dataIn_4;
assign T35 = T28[0];
assign T36 = T37 ? io_dataIn_7 : io_dataIn_6;
assign T37 = T28[0];
assign T38 = T28[1];
assign T39 = T28[2];
assign T40 = io_vld & T41;
assign T41 = T44 & T42;
assign T42 = 3'h0 <= T43;
assign T43 = count + io_len;
assign T44 = count <= 3'h0;
assign T45 = T61 ? T55 : T46;
assign T46 = T54 ? T52 : T47;
assign T47 = T48 ? io_dataIn_1 : io_dataIn_0;
assign T48 = T49[0];
assign T49 = T457;
assign T457 = T50[2:0];
assign T50 = T51 + 4'h0;
assign T51 = 4'h8 - T458;
assign T458 = {1'h0, count};
assign T52 = T53 ? io_dataIn_3 : io_dataIn_2;
assign T53 = T49[0];
assign T54 = T49[1];
assign T55 = T60 ? T58 : T56;
assign T56 = T57 ? io_dataIn_5 : io_dataIn_4;
assign T57 = T49[0];
assign T58 = T59 ? io_dataIn_7 : io_dataIn_6;
assign T59 = T49[0];
assign T60 = T49[1];
assign T61 = T49[2];
assign T62 = io_vld & io_vldOut;
assign T63 = T78 ? T72 : T64;
assign T64 = T71 ? T69 : T65;
assign T65 = T66 ? io_dataIn_1 : io_dataIn_0;
assign T66 = T67[0];
assign T67 = T459;
assign T459 = T68[2:0];
assign T68 = 4'h0 - T460;
assign T460 = {1'h0, count};
assign T69 = T70 ? io_dataIn_3 : io_dataIn_2;
assign T70 = T67[0];
assign T71 = T67[1];
assign T72 = T77 ? T75 : T73;
assign T73 = T74 ? io_dataIn_5 : io_dataIn_4;
assign T74 = T67[0];
assign T75 = T76 ? io_dataIn_7 : io_dataIn_6;
assign T76 = T67[0];
assign T77 = T67[1];
assign T78 = T67[2];
assign T79 = count <= 3'h0;
assign io_dataOut_1 = T80;
assign T80 = T138 ? T122 : store_1;
assign T81 = T121 ? T104 : T82;
assign T82 = T99 ? T83 : store_1;
assign T83 = T98 ? T92 : T84;
assign T84 = T91 ? T89 : T85;
assign T85 = T86 ? io_dataIn_1 : io_dataIn_0;
assign T86 = T87[0];
assign T87 = T88;
assign T88 = 3'h1 - count;
assign T89 = T90 ? io_dataIn_3 : io_dataIn_2;
assign T90 = T87[0];
assign T91 = T87[1];
assign T92 = T97 ? T95 : T93;
assign T93 = T94 ? io_dataIn_5 : io_dataIn_4;
assign T94 = T87[0];
assign T95 = T96 ? io_dataIn_7 : io_dataIn_6;
assign T96 = T87[0];
assign T97 = T87[1];
assign T98 = T87[2];
assign T99 = io_vld & T100;
assign T100 = T103 & T101;
assign T101 = 3'h1 <= T102;
assign T102 = count + io_len;
assign T103 = count <= 3'h1;
assign T104 = T120 ? T114 : T105;
assign T105 = T113 ? T111 : T106;
assign T106 = T107 ? io_dataIn_1 : io_dataIn_0;
assign T107 = T108[0];
assign T108 = T461;
assign T461 = T109[2:0];
assign T109 = T110 + 4'h1;
assign T110 = 4'h8 - T462;
assign T462 = {1'h0, count};
assign T111 = T112 ? io_dataIn_3 : io_dataIn_2;
assign T112 = T108[0];
assign T113 = T108[1];
assign T114 = T119 ? T117 : T115;
assign T115 = T116 ? io_dataIn_5 : io_dataIn_4;
assign T116 = T108[0];
assign T117 = T118 ? io_dataIn_7 : io_dataIn_6;
assign T118 = T108[0];
assign T119 = T108[1];
assign T120 = T108[2];
assign T121 = io_vld & io_vldOut;
assign T122 = T137 ? T131 : T123;
assign T123 = T130 ? T128 : T124;
assign T124 = T125 ? io_dataIn_1 : io_dataIn_0;
assign T125 = T126[0];
assign T126 = T463;
assign T463 = T127[2:0];
assign T127 = 4'h1 - T464;
assign T464 = {1'h0, count};
assign T128 = T129 ? io_dataIn_3 : io_dataIn_2;
assign T129 = T126[0];
assign T130 = T126[1];
assign T131 = T136 ? T134 : T132;
assign T132 = T133 ? io_dataIn_5 : io_dataIn_4;
assign T133 = T126[0];
assign T134 = T135 ? io_dataIn_7 : io_dataIn_6;
assign T135 = T126[0];
assign T136 = T126[1];
assign T137 = T126[2];
assign T138 = count <= 3'h1;
assign io_dataOut_2 = T139;
assign T139 = T197 ? T181 : store_2;
assign T140 = T180 ? T163 : T141;
assign T141 = T158 ? T142 : store_2;
assign T142 = T157 ? T151 : T143;
assign T143 = T150 ? T148 : T144;
assign T144 = T145 ? io_dataIn_1 : io_dataIn_0;
assign T145 = T146[0];
assign T146 = T147;
assign T147 = 3'h2 - count;
assign T148 = T149 ? io_dataIn_3 : io_dataIn_2;
assign T149 = T146[0];
assign T150 = T146[1];
assign T151 = T156 ? T154 : T152;
assign T152 = T153 ? io_dataIn_5 : io_dataIn_4;
assign T153 = T146[0];
assign T154 = T155 ? io_dataIn_7 : io_dataIn_6;
assign T155 = T146[0];
assign T156 = T146[1];
assign T157 = T146[2];
assign T158 = io_vld & T159;
assign T159 = T162 & T160;
assign T160 = 3'h2 <= T161;
assign T161 = count + io_len;
assign T162 = count <= 3'h2;
assign T163 = T179 ? T173 : T164;
assign T164 = T172 ? T170 : T165;
assign T165 = T166 ? io_dataIn_1 : io_dataIn_0;
assign T166 = T167[0];
assign T167 = T465;
assign T465 = T168[2:0];
assign T168 = T169 + 4'h2;
assign T169 = 4'h8 - T466;
assign T466 = {1'h0, count};
assign T170 = T171 ? io_dataIn_3 : io_dataIn_2;
assign T171 = T167[0];
assign T172 = T167[1];
assign T173 = T178 ? T176 : T174;
assign T174 = T175 ? io_dataIn_5 : io_dataIn_4;
assign T175 = T167[0];
assign T176 = T177 ? io_dataIn_7 : io_dataIn_6;
assign T177 = T167[0];
assign T178 = T167[1];
assign T179 = T167[2];
assign T180 = io_vld & io_vldOut;
assign T181 = T196 ? T190 : T182;
assign T182 = T189 ? T187 : T183;
assign T183 = T184 ? io_dataIn_1 : io_dataIn_0;
assign T184 = T185[0];
assign T185 = T467;
assign T467 = T186[2:0];
assign T186 = 4'h2 - T468;
assign T468 = {1'h0, count};
assign T187 = T188 ? io_dataIn_3 : io_dataIn_2;
assign T188 = T185[0];
assign T189 = T185[1];
assign T190 = T195 ? T193 : T191;
assign T191 = T192 ? io_dataIn_5 : io_dataIn_4;
assign T192 = T185[0];
assign T193 = T194 ? io_dataIn_7 : io_dataIn_6;
assign T194 = T185[0];
assign T195 = T185[1];
assign T196 = T185[2];
assign T197 = count <= 3'h2;
assign io_dataOut_3 = T198;
assign T198 = T256 ? T240 : store_3;
assign T199 = T239 ? T222 : T200;
assign T200 = T217 ? T201 : store_3;
assign T201 = T216 ? T210 : T202;
assign T202 = T209 ? T207 : T203;
assign T203 = T204 ? io_dataIn_1 : io_dataIn_0;
assign T204 = T205[0];
assign T205 = T206;
assign T206 = 3'h3 - count;
assign T207 = T208 ? io_dataIn_3 : io_dataIn_2;
assign T208 = T205[0];
assign T209 = T205[1];
assign T210 = T215 ? T213 : T211;
assign T211 = T212 ? io_dataIn_5 : io_dataIn_4;
assign T212 = T205[0];
assign T213 = T214 ? io_dataIn_7 : io_dataIn_6;
assign T214 = T205[0];
assign T215 = T205[1];
assign T216 = T205[2];
assign T217 = io_vld & T218;
assign T218 = T221 & T219;
assign T219 = 3'h3 <= T220;
assign T220 = count + io_len;
assign T221 = count <= 3'h3;
assign T222 = T238 ? T232 : T223;
assign T223 = T231 ? T229 : T224;
assign T224 = T225 ? io_dataIn_1 : io_dataIn_0;
assign T225 = T226[0];
assign T226 = T469;
assign T469 = T227[2:0];
assign T227 = T228 + 4'h3;
assign T228 = 4'h8 - T470;
assign T470 = {1'h0, count};
assign T229 = T230 ? io_dataIn_3 : io_dataIn_2;
assign T230 = T226[0];
assign T231 = T226[1];
assign T232 = T237 ? T235 : T233;
assign T233 = T234 ? io_dataIn_5 : io_dataIn_4;
assign T234 = T226[0];
assign T235 = T236 ? io_dataIn_7 : io_dataIn_6;
assign T236 = T226[0];
assign T237 = T226[1];
assign T238 = T226[2];
assign T239 = io_vld & io_vldOut;
assign T240 = T255 ? T249 : T241;
assign T241 = T248 ? T246 : T242;
assign T242 = T243 ? io_dataIn_1 : io_dataIn_0;
assign T243 = T244[0];
assign T244 = T471;
assign T471 = T245[2:0];
assign T245 = 4'h3 - T472;
assign T472 = {1'h0, count};
assign T246 = T247 ? io_dataIn_3 : io_dataIn_2;
assign T247 = T244[0];
assign T248 = T244[1];
assign T249 = T254 ? T252 : T250;
assign T250 = T251 ? io_dataIn_5 : io_dataIn_4;
assign T251 = T244[0];
assign T252 = T253 ? io_dataIn_7 : io_dataIn_6;
assign T253 = T244[0];
assign T254 = T244[1];
assign T255 = T244[2];
assign T256 = count <= 3'h3;
assign io_dataOut_4 = T257;
assign T257 = T315 ? T299 : store_4;
assign T258 = T298 ? T281 : T259;
assign T259 = T276 ? T260 : store_4;
assign T260 = T275 ? T269 : T261;
assign T261 = T268 ? T266 : T262;
assign T262 = T263 ? io_dataIn_1 : io_dataIn_0;
assign T263 = T264[0];
assign T264 = T265;
assign T265 = 3'h4 - count;
assign T266 = T267 ? io_dataIn_3 : io_dataIn_2;
assign T267 = T264[0];
assign T268 = T264[1];
assign T269 = T274 ? T272 : T270;
assign T270 = T271 ? io_dataIn_5 : io_dataIn_4;
assign T271 = T264[0];
assign T272 = T273 ? io_dataIn_7 : io_dataIn_6;
assign T273 = T264[0];
assign T274 = T264[1];
assign T275 = T264[2];
assign T276 = io_vld & T277;
assign T277 = T280 & T278;
assign T278 = 3'h4 <= T279;
assign T279 = count + io_len;
assign T280 = count <= 3'h4;
assign T281 = T297 ? T291 : T282;
assign T282 = T290 ? T288 : T283;
assign T283 = T284 ? io_dataIn_1 : io_dataIn_0;
assign T284 = T285[0];
assign T285 = T473;
assign T473 = T286[2:0];
assign T286 = T287 + 4'h4;
assign T287 = 4'h8 - T474;
assign T474 = {1'h0, count};
assign T288 = T289 ? io_dataIn_3 : io_dataIn_2;
assign T289 = T285[0];
assign T290 = T285[1];
assign T291 = T296 ? T294 : T292;
assign T292 = T293 ? io_dataIn_5 : io_dataIn_4;
assign T293 = T285[0];
assign T294 = T295 ? io_dataIn_7 : io_dataIn_6;
assign T295 = T285[0];
assign T296 = T285[1];
assign T297 = T285[2];
assign T298 = io_vld & io_vldOut;
assign T299 = T314 ? T308 : T300;
assign T300 = T307 ? T305 : T301;
assign T301 = T302 ? io_dataIn_1 : io_dataIn_0;
assign T302 = T303[0];
assign T303 = T475;
assign T475 = T304[2:0];
assign T304 = 4'h4 - T476;
assign T476 = {1'h0, count};
assign T305 = T306 ? io_dataIn_3 : io_dataIn_2;
assign T306 = T303[0];
assign T307 = T303[1];
assign T308 = T313 ? T311 : T309;
assign T309 = T310 ? io_dataIn_5 : io_dataIn_4;
assign T310 = T303[0];
assign T311 = T312 ? io_dataIn_7 : io_dataIn_6;
assign T312 = T303[0];
assign T313 = T303[1];
assign T314 = T303[2];
assign T315 = count <= 3'h4;
assign io_dataOut_5 = T316;
assign T316 = T374 ? T358 : store_5;
assign T317 = T357 ? T340 : T318;
assign T318 = T335 ? T319 : store_5;
assign T319 = T334 ? T328 : T320;
assign T320 = T327 ? T325 : T321;
assign T321 = T322 ? io_dataIn_1 : io_dataIn_0;
assign T322 = T323[0];
assign T323 = T324;
assign T324 = 3'h5 - count;
assign T325 = T326 ? io_dataIn_3 : io_dataIn_2;
assign T326 = T323[0];
assign T327 = T323[1];
assign T328 = T333 ? T331 : T329;
assign T329 = T330 ? io_dataIn_5 : io_dataIn_4;
assign T330 = T323[0];
assign T331 = T332 ? io_dataIn_7 : io_dataIn_6;
assign T332 = T323[0];
assign T333 = T323[1];
assign T334 = T323[2];
assign T335 = io_vld & T336;
assign T336 = T339 & T337;
assign T337 = 3'h5 <= T338;
assign T338 = count + io_len;
assign T339 = count <= 3'h5;
assign T340 = T356 ? T350 : T341;
assign T341 = T349 ? T347 : T342;
assign T342 = T343 ? io_dataIn_1 : io_dataIn_0;
assign T343 = T344[0];
assign T344 = T477;
assign T477 = T345[2:0];
assign T345 = T346 + 4'h5;
assign T346 = 4'h8 - T478;
assign T478 = {1'h0, count};
assign T347 = T348 ? io_dataIn_3 : io_dataIn_2;
assign T348 = T344[0];
assign T349 = T344[1];
assign T350 = T355 ? T353 : T351;
assign T351 = T352 ? io_dataIn_5 : io_dataIn_4;
assign T352 = T344[0];
assign T353 = T354 ? io_dataIn_7 : io_dataIn_6;
assign T354 = T344[0];
assign T355 = T344[1];
assign T356 = T344[2];
assign T357 = io_vld & io_vldOut;
assign T358 = T373 ? T367 : T359;
assign T359 = T366 ? T364 : T360;
assign T360 = T361 ? io_dataIn_1 : io_dataIn_0;
assign T361 = T362[0];
assign T362 = T479;
assign T479 = T363[2:0];
assign T363 = 4'h5 - T480;
assign T480 = {1'h0, count};
assign T364 = T365 ? io_dataIn_3 : io_dataIn_2;
assign T365 = T362[0];
assign T366 = T362[1];
assign T367 = T372 ? T370 : T368;
assign T368 = T369 ? io_dataIn_5 : io_dataIn_4;
assign T369 = T362[0];
assign T370 = T371 ? io_dataIn_7 : io_dataIn_6;
assign T371 = T362[0];
assign T372 = T362[1];
assign T373 = T362[2];
assign T374 = count <= 3'h5;
assign io_dataOut_6 = T375;
assign T375 = T433 ? T417 : store_6;
assign T376 = T416 ? T399 : T377;
assign T377 = T394 ? T378 : store_6;
assign T378 = T393 ? T387 : T379;
assign T379 = T386 ? T384 : T380;
assign T380 = T381 ? io_dataIn_1 : io_dataIn_0;
assign T381 = T382[0];
assign T382 = T383;
assign T383 = 3'h6 - count;
assign T384 = T385 ? io_dataIn_3 : io_dataIn_2;
assign T385 = T382[0];
assign T386 = T382[1];
assign T387 = T392 ? T390 : T388;
assign T388 = T389 ? io_dataIn_5 : io_dataIn_4;
assign T389 = T382[0];
assign T390 = T391 ? io_dataIn_7 : io_dataIn_6;
assign T391 = T382[0];
assign T392 = T382[1];
assign T393 = T382[2];
assign T394 = io_vld & T395;
assign T395 = T398 & T396;
assign T396 = 3'h6 <= T397;
assign T397 = count + io_len;
assign T398 = count <= 3'h6;
assign T399 = T415 ? T409 : T400;
assign T400 = T408 ? T406 : T401;
assign T401 = T402 ? io_dataIn_1 : io_dataIn_0;
assign T402 = T403[0];
assign T403 = T481;
assign T481 = T404[2:0];
assign T404 = T405 + 4'h6;
assign T405 = 4'h8 - T482;
assign T482 = {1'h0, count};
assign T406 = T407 ? io_dataIn_3 : io_dataIn_2;
assign T407 = T403[0];
assign T408 = T403[1];
assign T409 = T414 ? T412 : T410;
assign T410 = T411 ? io_dataIn_5 : io_dataIn_4;
assign T411 = T403[0];
assign T412 = T413 ? io_dataIn_7 : io_dataIn_6;
assign T413 = T403[0];
assign T414 = T403[1];
assign T415 = T403[2];
assign T416 = io_vld & io_vldOut;
assign T417 = T432 ? T426 : T418;
assign T418 = T425 ? T423 : T419;
assign T419 = T420 ? io_dataIn_1 : io_dataIn_0;
assign T420 = T421[0];
assign T421 = T483;
assign T483 = T422[2:0];
assign T422 = 4'h6 - T484;
assign T484 = {1'h0, count};
assign T423 = T424 ? io_dataIn_3 : io_dataIn_2;
assign T424 = T421[0];
assign T425 = T421[1];
assign T426 = T431 ? T429 : T427;
assign T427 = T428 ? io_dataIn_5 : io_dataIn_4;
assign T428 = T421[0];
assign T429 = T430 ? io_dataIn_7 : io_dataIn_6;
assign T430 = T421[0];
assign T431 = T421[1];
assign T432 = T421[2];
assign T433 = count <= 3'h6;
assign io_dataOut_7 = T434;
assign T434 = T451 ? T435 : 8'h0;
assign T435 = T450 ? T444 : T436;
assign T436 = T443 ? T441 : T437;
assign T437 = T438 ? io_dataIn_1 : io_dataIn_0;
assign T438 = T439[0];
assign T439 = T485;
assign T485 = T440[2:0];
assign T440 = 4'h7 - T486;
assign T486 = {1'h0, count};
assign T441 = T442 ? io_dataIn_3 : io_dataIn_2;
assign T442 = T439[0];
assign T443 = T439[1];
assign T444 = T449 ? T447 : T445;
assign T445 = T446 ? io_dataIn_5 : io_dataIn_4;
assign T446 = T439[0];
assign T447 = T448 ? io_dataIn_7 : io_dataIn_6;
assign T448 = T439[0];
assign T449 = T439[1];
assign T450 = T439[2];
assign T451 = count <= 3'h7;
always @(posedge clk) begin
count <= T452;
if(T62) begin
store_0 <= T45;
end else if(T40) begin
store_0 <= T24;
end
if(T121) begin
store_1 <= T104;
end else if(T99) begin
store_1 <= T83;
end
if(T180) begin
store_2 <= T163;
end else if(T158) begin
store_2 <= T142;
end
if(T239) begin
store_3 <= T222;
end else if(T217) begin
store_3 <= T201;
end
if(T298) begin
store_4 <= T281;
end else if(T276) begin
store_4 <= T260;
end
if(T357) begin
store_5 <= T340;
end else if(T335) begin
store_5 <= T319;
end
if(T416) begin
store_6 <= T399;
end else if(T394) begin
store_6 <= T378;
end
`ifndef SYNTHESIS
// synthesis translate_off
`ifdef PRINTF_COND
if (`PRINTF_COND)
`endif
if (T14)
$fwrite(32'h80000002, "total = %d\n", T15);
// synthesis translate_on
`endif
`ifndef SYNTHESIS
// synthesis translate_off
`ifdef PRINTF_COND
if (`PRINTF_COND)
`endif
if (T3)
$fwrite(32'h80000002, "count = %d\n", T4);
// synthesis translate_on
`endif
`ifndef SYNTHESIS
// synthesis translate_off
`ifdef PRINTF_COND
if (`PRINTF_COND)
`endif
if (T0)
$fwrite(32'h80000002, "len = %d\n", T1);
// synthesis translate_on
`endif
end
endmodule
module Queue_0(input clk, input reset,
output io_enq_ready,
input io_enq_valid,
input [7:0] io_enq_bits_7,
input [7:0] io_enq_bits_6,
input [7:0] io_enq_bits_5,
input [7:0] io_enq_bits_4,
input [7:0] io_enq_bits_3,
input [7:0] io_enq_bits_2,
input [7:0] io_enq_bits_1,
input [7:0] io_enq_bits_0,
input io_deq_ready,
output io_deq_valid,
output[7:0] io_deq_bits_7,
output[7:0] io_deq_bits_6,
output[7:0] io_deq_bits_5,
output[7:0] io_deq_bits_4,
output[7:0] io_deq_bits_3,
output[7:0] io_deq_bits_2,
output[7:0] io_deq_bits_1,
output[7:0] io_deq_bits_0,
output[5:0] io_count
);
wire[5:0] T0;
wire[4:0] ptr_diff;
reg [4:0] R1;
wire[4:0] T31;
wire[4:0] T2;
wire[4:0] T3;
wire do_deq;
reg [4:0] R4;
wire[4:0] T32;
wire[4:0] T5;
wire[4:0] T6;
wire do_enq;
wire T7;
wire ptr_match;
reg maybe_full;
wire T33;
wire T8;
wire T9;
wire[7:0] T10;
wire[63:0] T11;
reg [63:0] ram [31:0];
wire[63:0] T12;
wire[63:0] T13;
wire[63:0] T14;
wire[31:0] T15;
wire[15:0] T16;
wire[15:0] T17;
wire[31:0] T18;
wire[15:0] T19;
wire[15:0] T20;
wire[7:0] T21;
wire[7:0] T22;
wire[7:0] T23;
wire[7:0] T24;
wire[7:0] T25;
wire[7:0] T26;
wire[7:0] T27;
wire T28;
wire empty;
wire T29;
wire T30;
wire full;
`ifndef SYNTHESIS
// synthesis translate_off
integer initvar;
initial begin
#0.002;
R1 = {1{$random}};
R4 = {1{$random}};
maybe_full = {1{$random}};
for (initvar = 0; initvar < 32; initvar = initvar+1)
ram[initvar] = {2{$random}};
end
// synthesis translate_on
`endif
assign io_count = T0;
assign T0 = {T7, ptr_diff};
assign ptr_diff = R4 - R1;
assign T31 = reset ? 5'h0 : T2;
assign T2 = do_deq ? T3 : R1;
assign T3 = R1 + 5'h1;
assign do_deq = io_deq_ready & io_deq_valid;
assign T32 = reset ? 5'h0 : T5;
assign T5 = do_enq ? T6 : R4;
assign T6 = R4 + 5'h1;
assign do_enq = io_enq_ready & io_enq_valid;
assign T7 = maybe_full & ptr_match;
assign ptr_match = R4 == R1;
assign T33 = reset ? 1'h0 : T8;
assign T8 = T9 ? do_enq : maybe_full;
assign T9 = do_enq != do_deq;
assign io_deq_bits_0 = T10;
assign T10 = T11[7:0];
assign T11 = ram[R1];
assign T13 = T14;
assign T14 = {T18, T15};
assign T15 = {T17, T16};
assign T16 = {io_enq_bits_1, io_enq_bits_0};
assign T17 = {io_enq_bits_3, io_enq_bits_2};
assign T18 = {T20, T19};
assign T19 = {io_enq_bits_5, io_enq_bits_4};
assign T20 = {io_enq_bits_7, io_enq_bits_6};
assign io_deq_bits_1 = T21;
assign T21 = T11[15:8];
assign io_deq_bits_2 = T22;
assign T22 = T11[23:16];
assign io_deq_bits_3 = T23;
assign T23 = T11[31:24];
assign io_deq_bits_4 = T24;
assign T24 = T11[39:32];
assign io_deq_bits_5 = T25;
assign T25 = T11[47:40];
assign io_deq_bits_6 = T26;
assign T26 = T11[55:48];
assign io_deq_bits_7 = T27;
assign T27 = T11[63:56];
assign io_deq_valid = T28;
assign T28 = empty ^ 1'h1;
assign empty = ptr_match & T29;
assign T29 = maybe_full ^ 1'h1;
assign io_enq_ready = T30;
assign T30 = full ^ 1'h1;
assign full = ptr_match & maybe_full;
always @(posedge clk) begin
if(reset) begin
R1 <= 5'h0;
end else if(do_deq) begin
R1 <= T3;
end
if(reset) begin
R4 <= 5'h0;
end else if(do_enq) begin
R4 <= T6;
end
if(reset) begin
maybe_full <= 1'h0;
end else if(T9) begin
maybe_full <= do_enq;
end
if (do_enq)
ram[R4] <= T13;
end
endmodule
module Queue_1(input clk, input reset,
output io_enq_ready,
input io_enq_valid,
input io_enq_bits_7,
input io_enq_bits_6,
input io_enq_bits_5,
input io_enq_bits_4,
input io_enq_bits_3,
input io_enq_bits_2,
input io_enq_bits_1,
input io_enq_bits_0,
input io_deq_ready,
output io_deq_valid,
output io_deq_bits_7,
output io_deq_bits_6,
output io_deq_bits_5,
output io_deq_bits_4,
output io_deq_bits_3,
output io_deq_bits_2,
output io_deq_bits_1,
output io_deq_bits_0,
output[5:0] io_count
);
wire[5:0] T0;
wire[4:0] ptr_diff;
reg [4:0] R1;
wire[4:0] T31;
wire[4:0] T2;
wire[4:0] T3;
wire do_deq;
reg [4:0] R4;
wire[4:0] T32;
wire[4:0] T5;
wire[4:0] T6;
wire do_enq;
wire T7;
wire ptr_match;
reg maybe_full;
wire T33;
wire T8;
wire T9;
wire T10;
wire[7:0] T11;
reg [7:0] ram [31:0];
wire[7:0] T12;
wire[7:0] T13;
wire[7:0] T14;
wire[3:0] T15;
wire[1:0] T16;
wire[1:0] T17;
wire[3:0] T18;
wire[1:0] T19;
wire[1:0] T20;
wire T21;
wire T22;
wire T23;
wire T24;
wire T25;
wire T26;
wire T27;
wire T28;
wire empty;
wire T29;
wire T30;
wire full;
`ifndef SYNTHESIS
// synthesis translate_off
integer initvar;
initial begin
#0.002;
R1 = {1{$random}};
R4 = {1{$random}};
maybe_full = {1{$random}};
for (initvar = 0; initvar < 32; initvar = initvar+1)
ram[initvar] = {1{$random}};
end
// synthesis translate_on
`endif
assign io_count = T0;
assign T0 = {T7, ptr_diff};
assign ptr_diff = R4 - R1;
assign T31 = reset ? 5'h0 : T2;
assign T2 = do_deq ? T3 : R1;
assign T3 = R1 + 5'h1;
assign do_deq = io_deq_ready & io_deq_valid;
assign T32 = reset ? 5'h0 : T5;
assign T5 = do_enq ? T6 : R4;
assign T6 = R4 + 5'h1;
assign do_enq = io_enq_ready & io_enq_valid;
assign T7 = maybe_full & ptr_match;
assign ptr_match = R4 == R1;
assign T33 = reset ? 1'h0 : T8;
assign T8 = T9 ? do_enq : maybe_full;
assign T9 = do_enq != do_deq;
assign io_deq_bits_0 = T10;
assign T10 = T11[0];
assign T11 = ram[R1];
assign T13 = T14;
assign T14 = {T18, T15};
assign T15 = {T17, T16};
assign T16 = {io_enq_bits_1, io_enq_bits_0};
assign T17 = {io_enq_bits_3, io_enq_bits_2};
assign T18 = {T20, T19};
assign T19 = {io_enq_bits_5, io_enq_bits_4};
assign T20 = {io_enq_bits_7, io_enq_bits_6};
assign io_deq_bits_1 = T21;
assign T21 = T11[1];
assign io_deq_bits_2 = T22;
assign T22 = T11[2];
assign io_deq_bits_3 = T23;
assign T23 = T11[3];
assign io_deq_bits_4 = T24;
assign T24 = T11[4];
assign io_deq_bits_5 = T25;
assign T25 = T11[5];
assign io_deq_bits_6 = T26;
assign T26 = T11[6];
assign io_deq_bits_7 = T27;
assign T27 = T11[7];
assign io_deq_valid = T28;
assign T28 = empty ^ 1'h1;
assign empty = ptr_match & T29;
assign T29 = maybe_full ^ 1'h1;
assign io_enq_ready = T30;
assign T30 = full ^ 1'h1;
assign full = ptr_match & maybe_full;
always @(posedge clk) begin
if(reset) begin
R1 <= 5'h0;
end else if(do_deq) begin
R1 <= T3;
end
if(reset) begin
R4 <= 5'h0;
end else if(do_enq) begin
R4 <= T6;
end
if(reset) begin
maybe_full <= 1'h0;
end else if(T9) begin
maybe_full <= do_enq;
end
if (do_enq)
ram[R4] <= T13;
end
endmodule
module Serializer(input clk, input reset,
output io_dataIn_ready,
input io_dataIn_valid,
input io_dataIn_bits_7,
input io_dataIn_bits_6,
input io_dataIn_bits_5,
input io_dataIn_bits_4,
input io_dataIn_bits_3,
input io_dataIn_bits_2,
input io_dataIn_bits_1,
input io_dataIn_bits_0,
input io_flush,
output io_dataOut_valid,
output io_dataOut_bits_63,
output io_dataOut_bits_62,
output io_dataOut_bits_61,
output io_dataOut_bits_60,
output io_dataOut_bits_59,
output io_dataOut_bits_58,
output io_dataOut_bits_57,
output io_dataOut_bits_56,
output io_dataOut_bits_55,
output io_dataOut_bits_54,
output io_dataOut_bits_53,
output io_dataOut_bits_52,
output io_dataOut_bits_51,
output io_dataOut_bits_50,
output io_dataOut_bits_49,
output io_dataOut_bits_48,
output io_dataOut_bits_47,
output io_dataOut_bits_46,
output io_dataOut_bits_45,
output io_dataOut_bits_44,
output io_dataOut_bits_43,
output io_dataOut_bits_42,
output io_dataOut_bits_41,
output io_dataOut_bits_40,
output io_dataOut_bits_39,
output io_dataOut_bits_38,
output io_dataOut_bits_37,
output io_dataOut_bits_36,
output io_dataOut_bits_35,
output io_dataOut_bits_34,
output io_dataOut_bits_33,
output io_dataOut_bits_32,
output io_dataOut_bits_31,
output io_dataOut_bits_30,
output io_dataOut_bits_29,
output io_dataOut_bits_28,
output io_dataOut_bits_27,
output io_dataOut_bits_26,
output io_dataOut_bits_25,
output io_dataOut_bits_24,
output io_dataOut_bits_23,
output io_dataOut_bits_22,
output io_dataOut_bits_21,
output io_dataOut_bits_20,
output io_dataOut_bits_19,
output io_dataOut_bits_18,
output io_dataOut_bits_17,
output io_dataOut_bits_16,
output io_dataOut_bits_15,
output io_dataOut_bits_14,
output io_dataOut_bits_13,
output io_dataOut_bits_12,
output io_dataOut_bits_11,
output io_dataOut_bits_10,
output io_dataOut_bits_9,
output io_dataOut_bits_8,
output io_dataOut_bits_7,
output io_dataOut_bits_6,
output io_dataOut_bits_5,
output io_dataOut_bits_4,
output io_dataOut_bits_3,
output io_dataOut_bits_2,
output io_dataOut_bits_1,
output io_dataOut_bits_0,
output io_flushed
);
wire T0;
reg R1;
wire T2;
wire T3;
wire T4;
wire T5;
reg [2:0] R6;
wire[2:0] T346;
wire[3:0] T347;
wire[3:0] T7;
wire[3:0] T8;
wire[3:0] T9;
wire[3:0] T348;
wire[3:0] T10;
wire[3:0] T349;
wire[3:0] T350;
wire[2:0] T11;
wire T12;
wire T13;
wire T14;
wire T15;
wire T16;
wire T17;
wire[7:0] vecOutComb_0;
wire[7:0] T18;
wire[7:0] T19;
wire[7:0] T20;
wire[7:0] T21;
wire[7:0] T22;
wire[7:0] T23;
wire[7:0] T24;
wire[7:0] T25;
wire[7:0] T26;
wire T34;
wire T35;
wire[7:0] T36;
wire[2:0] T37;
wire T38;
wire T39;
wire T40;
wire[2:0] T41;
wire[2:0] T42;
wire T43;
wire[2:0] T44;
wire[2:0] T351;
wire[3:0] T45;
wire[3:0] T46;
wire[3:0] T352;
wire[2:0] T47;
wire T48;
wire T49;
wire T50;
wire T51;
wire T52;
wire T53;
wire[7:0] T54;
wire[2:0] T55;
wire T56;
wire T57;
wire T58;
wire T59;
wire T60;
wire T61;
wire[7:0] T62;
wire[2:0] T63;
wire T64;
wire T65;
wire T66;
wire T67;
wire T68;
wire T69;
wire[7:0] T70;
wire[2:0] T71;
wire T72;
wire T73;
wire T74;
wire T75;
wire T76;
wire T77;
wire[7:0] T78;
wire[2:0] T79;
wire T80;
wire T81;
wire T82;
wire T83;
wire T84;
wire T85;
wire[7:0] T86;
wire[2:0] T87;
wire T88;
wire T89;
wire T90;
wire T91;
wire[7:0] vecInComb_0;
wire[7:0] T27;
wire[6:0] T28;
wire[5:0] T29;
wire[4:0] T30;
wire[3:0] T31;
wire[2:0] T32;
wire[1:0] T33;
wire T92;
wire T93;
wire[7:0] T94;
wire[2:0] T95;
wire T96;
wire T97;
wire T98;
wire T99;
reg [7:0] R100;
wire T101;
wire T102;
wire T103;
wire T104;
wire T105;
wire T106;
wire T107;
wire T108;
wire[7:0] vecOutComb_1;
wire[7:0] T109;
wire[7:0] T110;
wire[7:0] T111;
wire[7:0] T112;
wire[7:0] T113;
wire[7:0] T114;
wire[7:0] T115;
wire[7:0] T116;
wire[7:0] T117;
wire T118;
wire T119;
wire T120;
wire T121;
wire T122;
wire T123;
wire T124;
wire T125;
wire T126;
wire T127;
wire T128;
wire T129;
wire T130;
wire T131;
reg [7:0] R132;
wire T133;
wire T134;
wire T135;
wire T136;
wire T137;
wire T138;
wire T139;
wire T140;
wire[7:0] vecOutComb_2;
wire[7:0] T141;
wire[7:0] T142;
wire[7:0] T143;
wire[7:0] T144;
wire[7:0] T145;
wire[7:0] T146;
wire[7:0] T147;
wire[7:0] T148;
wire[7:0] T149;
wire T150;
wire T151;
wire T152;
wire T153;
wire T154;
wire T155;
wire T156;
wire T157;
wire T158;
wire T159;
wire T160;
wire T161;
wire T162;
wire T163;
reg [7:0] R164;
wire T165;
wire T166;
wire T167;
wire T168;
wire T169;
wire T170;
wire T171;
wire T172;
wire[7:0] vecOutComb_3;
wire[7:0] T173;
wire[7:0] T174;
wire[7:0] T175;
wire[7:0] T176;
wire[7:0] T177;
wire[7:0] T178;
wire[7:0] T179;
wire[7:0] T180;
wire[7:0] T181;
wire T182;
wire T183;
wire T184;
wire T185;
wire T186;
wire T187;
wire T188;
wire T189;
wire T190;
wire T191;
wire T192;
wire T193;
wire T194;
wire T195;
reg [7:0] R196;
wire T197;
wire T198;
wire T199;
wire T200;
wire T201;
wire T202;
wire T203;
wire T204;
wire[7:0] vecOutComb_4;
wire[7:0] T205;
wire[7:0] T206;
wire[7:0] T207;
wire[7:0] T208;
wire[7:0] T209;
wire[7:0] T210;
wire[7:0] T211;
wire[7:0] T212;
wire[7:0] T213;
wire T214;
wire T215;
wire T216;
wire T217;
wire T218;
wire T219;
wire T220;
wire T221;
wire T222;
wire T223;
wire T224;
wire T225;
wire T226;
wire T227;
reg [7:0] R228;
wire T229;
wire T230;
wire T231;
wire T232;
wire T233;
wire T234;
wire T235;
wire T236;
wire[7:0] vecOutComb_5;
wire[7:0] T237;
wire[7:0] T238;
wire[7:0] T239;
wire[7:0] T240;
wire[7:0] T241;
wire[7:0] T242;
wire[7:0] T243;
wire[7:0] T244;
wire[7:0] T245;
wire T246;
wire T247;
wire T248;
wire T249;
wire T250;
wire T251;
wire T252;
wire T253;
wire T254;
wire T255;
wire T256;
wire T257;
wire T258;
wire T259;
reg [7:0] R260;
wire T261;
wire T262;
wire T263;
wire T264;
wire T265;
wire T266;
wire T267;
wire T268;
wire[7:0] vecOutComb_6;
wire[7:0] T269;
wire[7:0] T270;
wire[7:0] T271;
wire[7:0] T272;
wire[7:0] T273;
wire[7:0] T274;
wire[7:0] T275;
wire[7:0] T276;
wire[7:0] T277;
wire T278;
wire T279;
wire T280;
wire T281;
wire T282;
wire T283;
wire T284;
wire T285;
wire T286;
wire T287;
wire T288;
wire T289;
wire T290;
wire T291;
reg [7:0] R292;
wire T293;
wire T294;
wire T295;
wire T296;
wire T297;
wire T298;
wire T299;
wire T300;
wire[7:0] vecOutComb_7;
wire[7:0] T301;
wire[7:0] T302;
wire[7:0] T303;
wire[7:0] T304;
wire[7:0] T305;
wire[7:0] T306;
wire T307;
wire[2:0] T308;
wire[7:0] T309;
wire T310;
wire T311;
wire[7:0] T312;
wire[7:0] T313;
wire T314;
wire T315;
wire T316;
wire T317;
wire[7:0] T318;
wire[7:0] T319;
wire[7:0] T320;
wire T321;
wire[2:0] T322;
wire[7:0] T323;
wire T324;
wire T325;
wire[7:0] T326;
wire[7:0] T327;
wire T328;
wire T329;
wire T330;
wire T331;
wire T332;
wire T333;
wire T334;
wire T335;
wire T336;
wire T337;
wire T338;
wire T339;
wire T340;
wire T341;
wire T342;
wire T343;
wire T344;
wire T345;
`ifndef SYNTHESIS
// synthesis translate_off
integer initvar;
initial begin
#0.002;
R1 = {1{$random}};
R6 = {1{$random}};
R100 = {1{$random}};
R132 = {1{$random}};
R164 = {1{$random}};
R196 = {1{$random}};
R228 = {1{$random}};
R260 = {1{$random}};
R292 = {1{$random}};
end
// synthesis translate_on
`endif
assign io_flushed = T0;
assign T0 = T15 | R1;
assign T2 = io_flushed ? 1'h0 : T3;
assign T3 = T4 & io_flush;
assign T4 = T5 & io_dataIn_valid;
assign T5 = 3'h7 < R6;
assign T346 = T347[2:0];
assign T347 = reset ? 4'h0 : T7;
assign T7 = io_flushed ? 4'h0 : T8;
assign T8 = T12 ? T350 : T9;
assign T9 = io_dataIn_valid ? T10 : T348;
assign T348 = {1'h0, R6};
assign T10 = T349 + 4'h1;
assign T349 = {1'h0, R6};
assign T350 = {1'h0, T11};
assign T11 = R6 - 3'h7;
assign T12 = io_dataIn_valid & T13;
assign T13 = T14 & io_dataIn_valid;
assign T14 = 3'h7 <= R6;
assign T15 = T16 & io_flush;
assign T16 = T4 ^ 1'h1;
assign io_dataOut_bits_0 = T17;
assign T17 = vecOutComb_0[0];
assign vecOutComb_0 = T18;
assign T18 = T13 ? R100 : T19;
assign T19 = T20;
assign T20 = T92 ? vecInComb_0 : T21;
assign T21 = T84 ? vecInComb_0 : T22;
assign T22 = T76 ? vecInComb_0 : T23;
assign T23 = T68 ? vecInComb_0 : T24;
assign T24 = T60 ? vecInComb_0 : T25;
assign T25 = T52 ? vecInComb_0 : T26;
assign T26 = T34 ? vecInComb_0 : R100;
assign T34 = T38 & T35;
assign T35 = T36[0];
assign T36 = 1'h1 << T37;
assign T37 = 3'h0;
assign T38 = T48 & T39;
assign T39 = T43 & T40;
assign T40 = T41 <= 3'h0;
assign T41 = T42;
assign T42 = T13 ? 3'h0 : R6;
assign T43 = 3'h0 <= T44;
assign T44 = T351;
assign T351 = T45[2:0];
assign T45 = T13 ? T352 : T46;
assign T46 = T10 - 4'h1;
assign T352 = {1'h0, T47};
assign T47 = T11 - 3'h1;
assign T48 = io_dataIn_valid & T49;
assign T49 = T50 ^ 1'h1;
assign T50 = T13 & T51;
assign T51 = T11 == 3'h0;
assign T52 = T56 & T53;
assign T53 = T54[0];
assign T54 = 1'h1 << T55;
assign T55 = 3'h1;
assign T56 = T48 & T57;
assign T57 = T59 & T58;
assign T58 = T41 <= 3'h1;
assign T59 = 3'h1 <= T44;
assign T60 = T64 & T61;
assign T61 = T62[0];
assign T62 = 1'h1 << T63;
assign T63 = 3'h2;
assign T64 = T48 & T65;
assign T65 = T67 & T66;
assign T66 = T41 <= 3'h2;
assign T67 = 3'h2 <= T44;
assign T68 = T72 & T69;
assign T69 = T70[0];
assign T70 = 1'h1 << T71;
assign T71 = 3'h3;
assign T72 = T48 & T73;
assign T73 = T75 & T74;
assign T74 = T41 <= 3'h3;
assign T75 = 3'h3 <= T44;
assign T76 = T80 & T77;
assign T77 = T78[0];
assign T78 = 1'h1 << T79;
assign T79 = 3'h4;
assign T80 = T48 & T81;
assign T81 = T83 & T82;
assign T82 = T41 <= 3'h4;
assign T83 = 3'h4 <= T44;
assign T84 = T88 & T85;
assign T85 = T86[0];
assign T86 = 1'h1 << T87;
assign T87 = 3'h5;
assign T88 = T48 & T89;
assign T89 = T91 & T90;
assign T90 = T41 <= 3'h5;
assign T91 = 3'h5 <= T44;
assign vecInComb_0 = T27;
assign T27 = {T28, io_dataIn_bits_0};
assign T28 = {T29, io_dataIn_bits_1};
assign T29 = {T30, io_dataIn_bits_2};
assign T30 = {T31, io_dataIn_bits_3};
assign T31 = {T32, io_dataIn_bits_4};
assign T32 = {T33, io_dataIn_bits_5};
assign T33 = {io_dataIn_bits_7, io_dataIn_bits_6};
assign T92 = T96 & T93;
assign T93 = T94[0];
assign T94 = 1'h1 << T95;
assign T95 = 3'h6;
assign T96 = T48 & T97;
assign T97 = T99 & T98;
assign T98 = T41 <= 3'h6;
assign T99 = 3'h6 <= T44;
assign io_dataOut_bits_1 = T101;
assign T101 = vecOutComb_0[1];
assign io_dataOut_bits_2 = T102;
assign T102 = vecOutComb_0[2];
assign io_dataOut_bits_3 = T103;
assign T103 = vecOutComb_0[3];
assign io_dataOut_bits_4 = T104;
assign T104 = vecOutComb_0[4];
assign io_dataOut_bits_5 = T105;
assign T105 = vecOutComb_0[5];
assign io_dataOut_bits_6 = T106;
assign T106 = vecOutComb_0[6];
assign io_dataOut_bits_7 = T107;
assign T107 = vecOutComb_0[7];
assign io_dataOut_bits_8 = T108;
assign T108 = vecOutComb_1[0];
assign vecOutComb_1 = T109;
assign T109 = T13 ? R132 : T110;
assign T110 = T111;
assign T111 = T130 ? vecInComb_0 : T112;
assign T112 = T128 ? vecInComb_0 : T113;
assign T113 = T126 ? vecInComb_0 : T114;
assign T114 = T124 ? vecInComb_0 : T115;
assign T115 = T122 ? vecInComb_0 : T116;
assign T116 = T120 ? vecInComb_0 : T117;
assign T117 = T118 ? vecInComb_0 : R132;
assign T118 = T38 & T119;
assign T119 = T36[1];
assign T120 = T56 & T121;
assign T121 = T54[1];
assign T122 = T64 & T123;
assign T123 = T62[1];
assign T124 = T72 & T125;
assign T125 = T70[1];
assign T126 = T80 & T127;
assign T127 = T78[1];
assign T128 = T88 & T129;
assign T129 = T86[1];
assign T130 = T96 & T131;
assign T131 = T94[1];
assign io_dataOut_bits_9 = T133;
assign T133 = vecOutComb_1[1];
assign io_dataOut_bits_10 = T134;
assign T134 = vecOutComb_1[2];
assign io_dataOut_bits_11 = T135;
assign T135 = vecOutComb_1[3];
assign io_dataOut_bits_12 = T136;
assign T136 = vecOutComb_1[4];
assign io_dataOut_bits_13 = T137;
assign T137 = vecOutComb_1[5];
assign io_dataOut_bits_14 = T138;
assign T138 = vecOutComb_1[6];
assign io_dataOut_bits_15 = T139;
assign T139 = vecOutComb_1[7];
assign io_dataOut_bits_16 = T140;
assign T140 = vecOutComb_2[0];
assign vecOutComb_2 = T141;
assign T141 = T13 ? R164 : T142;
assign T142 = T143;
assign T143 = T162 ? vecInComb_0 : T144;
assign T144 = T160 ? vecInComb_0 : T145;
assign T145 = T158 ? vecInComb_0 : T146;
assign T146 = T156 ? vecInComb_0 : T147;
assign T147 = T154 ? vecInComb_0 : T148;
assign T148 = T152 ? vecInComb_0 : T149;
assign T149 = T150 ? vecInComb_0 : R164;
assign T150 = T38 & T151;
assign T151 = T36[2];
assign T152 = T56 & T153;
assign T153 = T54[2];
assign T154 = T64 & T155;
assign T155 = T62[2];
assign T156 = T72 & T157;
assign T157 = T70[2];
assign T158 = T80 & T159;
assign T159 = T78[2];
assign T160 = T88 & T161;
assign T161 = T86[2];
assign T162 = T96 & T163;
assign T163 = T94[2];
assign io_dataOut_bits_17 = T165;
assign T165 = vecOutComb_2[1];
assign io_dataOut_bits_18 = T166;
assign T166 = vecOutComb_2[2];
assign io_dataOut_bits_19 = T167;
assign T167 = vecOutComb_2[3];
assign io_dataOut_bits_20 = T168;
assign T168 = vecOutComb_2[4];
assign io_dataOut_bits_21 = T169;
assign T169 = vecOutComb_2[5];
assign io_dataOut_bits_22 = T170;
assign T170 = vecOutComb_2[6];
assign io_dataOut_bits_23 = T171;
assign T171 = vecOutComb_2[7];
assign io_dataOut_bits_24 = T172;
assign T172 = vecOutComb_3[0];
assign vecOutComb_3 = T173;
assign T173 = T13 ? R196 : T174;
assign T174 = T175;
assign T175 = T194 ? vecInComb_0 : T176;
assign T176 = T192 ? vecInComb_0 : T177;
assign T177 = T190 ? vecInComb_0 : T178;
assign T178 = T188 ? vecInComb_0 : T179;
assign T179 = T186 ? vecInComb_0 : T180;
assign T180 = T184 ? vecInComb_0 : T181;
assign T181 = T182 ? vecInComb_0 : R196;
assign T182 = T38 & T183;
assign T183 = T36[3];
assign T184 = T56 & T185;
assign T185 = T54[3];
assign T186 = T64 & T187;
assign T187 = T62[3];
assign T188 = T72 & T189;
assign T189 = T70[3];
assign T190 = T80 & T191;
assign T191 = T78[3];
assign T192 = T88 & T193;
assign T193 = T86[3];
assign T194 = T96 & T195;
assign T195 = T94[3];
assign io_dataOut_bits_25 = T197;
assign T197 = vecOutComb_3[1];
assign io_dataOut_bits_26 = T198;
assign T198 = vecOutComb_3[2];
assign io_dataOut_bits_27 = T199;
assign T199 = vecOutComb_3[3];
assign io_dataOut_bits_28 = T200;
assign T200 = vecOutComb_3[4];
assign io_dataOut_bits_29 = T201;
assign T201 = vecOutComb_3[5];
assign io_dataOut_bits_30 = T202;
assign T202 = vecOutComb_3[6];
assign io_dataOut_bits_31 = T203;
assign T203 = vecOutComb_3[7];
assign io_dataOut_bits_32 = T204;
assign T204 = vecOutComb_4[0];
assign vecOutComb_4 = T205;
assign T205 = T13 ? R228 : T206;
assign T206 = T207;
assign T207 = T226 ? vecInComb_0 : T208;
assign T208 = T224 ? vecInComb_0 : T209;
assign T209 = T222 ? vecInComb_0 : T210;
assign T210 = T220 ? vecInComb_0 : T211;
assign T211 = T218 ? vecInComb_0 : T212;
assign T212 = T216 ? vecInComb_0 : T213;
assign T213 = T214 ? vecInComb_0 : R228;
assign T214 = T38 & T215;
assign T215 = T36[4];
assign T216 = T56 & T217;
assign T217 = T54[4];
assign T218 = T64 & T219;
assign T219 = T62[4];
assign T220 = T72 & T221;
assign T221 = T70[4];
assign T222 = T80 & T223;
assign T223 = T78[4];
assign T224 = T88 & T225;
assign T225 = T86[4];
assign T226 = T96 & T227;
assign T227 = T94[4];
assign io_dataOut_bits_33 = T229;
assign T229 = vecOutComb_4[1];
assign io_dataOut_bits_34 = T230;
assign T230 = vecOutComb_4[2];
assign io_dataOut_bits_35 = T231;
assign T231 = vecOutComb_4[3];
assign io_dataOut_bits_36 = T232;
assign T232 = vecOutComb_4[4];
assign io_dataOut_bits_37 = T233;
assign T233 = vecOutComb_4[5];
assign io_dataOut_bits_38 = T234;
assign T234 = vecOutComb_4[6];
assign io_dataOut_bits_39 = T235;
assign T235 = vecOutComb_4[7];
assign io_dataOut_bits_40 = T236;
assign T236 = vecOutComb_5[0];
assign vecOutComb_5 = T237;
assign T237 = T13 ? R260 : T238;
assign T238 = T239;
assign T239 = T258 ? vecInComb_0 : T240;
assign T240 = T256 ? vecInComb_0 : T241;
assign T241 = T254 ? vecInComb_0 : T242;
assign T242 = T252 ? vecInComb_0 : T243;
assign T243 = T250 ? vecInComb_0 : T244;
assign T244 = T248 ? vecInComb_0 : T245;
assign T245 = T246 ? vecInComb_0 : R260;
assign T246 = T38 & T247;
assign T247 = T36[5];
assign T248 = T56 & T249;
assign T249 = T54[5];
assign T250 = T64 & T251;
assign T251 = T62[5];
assign T252 = T72 & T253;
assign T253 = T70[5];
assign T254 = T80 & T255;
assign T255 = T78[5];
assign T256 = T88 & T257;
assign T257 = T86[5];
assign T258 = T96 & T259;
assign T259 = T94[5];
assign io_dataOut_bits_41 = T261;
assign T261 = vecOutComb_5[1];
assign io_dataOut_bits_42 = T262;
assign T262 = vecOutComb_5[2];
assign io_dataOut_bits_43 = T263;
assign T263 = vecOutComb_5[3];
assign io_dataOut_bits_44 = T264;
assign T264 = vecOutComb_5[4];
assign io_dataOut_bits_45 = T265;
assign T265 = vecOutComb_5[5];
assign io_dataOut_bits_46 = T266;
assign T266 = vecOutComb_5[6];
assign io_dataOut_bits_47 = T267;
assign T267 = vecOutComb_5[7];
assign io_dataOut_bits_48 = T268;
assign T268 = vecOutComb_6[0];
assign vecOutComb_6 = T269;
assign T269 = T13 ? R292 : T270;
assign T270 = T271;
assign T271 = T290 ? vecInComb_0 : T272;
assign T272 = T288 ? vecInComb_0 : T273;
assign T273 = T286 ? vecInComb_0 : T274;
assign T274 = T284 ? vecInComb_0 : T275;
assign T275 = T282 ? vecInComb_0 : T276;
assign T276 = T280 ? vecInComb_0 : T277;
assign T277 = T278 ? vecInComb_0 : R292;
assign T278 = T38 & T279;
assign T279 = T36[6];
assign T280 = T56 & T281;
assign T281 = T54[6];
assign T282 = T64 & T283;
assign T283 = T62[6];
assign T284 = T72 & T285;
assign T285 = T70[6];
assign T286 = T80 & T287;
assign T287 = T78[6];
assign T288 = T88 & T289;
assign T289 = T86[6];
assign T290 = T96 & T291;
assign T291 = T94[6];
assign io_dataOut_bits_49 = T293;
assign T293 = vecOutComb_6[1];
assign io_dataOut_bits_50 = T294;
assign T294 = vecOutComb_6[2];
assign io_dataOut_bits_51 = T295;
assign T295 = vecOutComb_6[3];
assign io_dataOut_bits_52 = T296;
assign T296 = vecOutComb_6[4];
assign io_dataOut_bits_53 = T297;
assign T297 = vecOutComb_6[5];
assign io_dataOut_bits_54 = T298;
assign T298 = vecOutComb_6[6];
assign io_dataOut_bits_55 = T299;
assign T299 = vecOutComb_6[7];
assign io_dataOut_bits_56 = T300;
assign T300 = vecOutComb_7[0];
assign vecOutComb_7 = T301;
assign T301 = T302;
assign T302 = T331 ? T318 : T303;
assign T303 = T317 ? T304 : vecInComb_0;
assign T304 = T316 ? T312 : T305;
assign T305 = T311 ? T309 : T306;
assign T306 = T307 ? T110 : T19;
assign T307 = T308[0];
assign T308 = 3'h7;
assign T309 = T310 ? T174 : T142;
assign T310 = T308[0];
assign T311 = T308[1];
assign T312 = T315 ? T270 : T313;
assign T313 = T314 ? T238 : T206;
assign T314 = T308[0];
assign T315 = T308[1];
assign T316 = T308[2];
assign T317 = 3'h0 < T11;
assign T318 = T330 ? T326 : T319;
assign T319 = T325 ? T323 : T320;
assign T320 = T321 ? R132 : R100;
assign T321 = T322[0];
assign T322 = 3'h7;
assign T323 = T324 ? R196 : R164;
assign T324 = T322[0];
assign T325 = T322[1];
assign T326 = T329 ? R292 : T327;
assign T327 = T328 ? R260 : R228;
assign T328 = T322[0];
assign T329 = T322[1];
assign T330 = T322[2];
assign T331 = T317 & T13;
assign io_dataOut_bits_57 = T332;
assign T332 = vecOutComb_7[1];
assign io_dataOut_bits_58 = T333;
assign T333 = vecOutComb_7[2];
assign io_dataOut_bits_59 = T334;
assign T334 = vecOutComb_7[3];
assign io_dataOut_bits_60 = T335;
assign T335 = vecOutComb_7[4];
assign io_dataOut_bits_61 = T336;
assign T336 = vecOutComb_7[5];
assign io_dataOut_bits_62 = T337;
assign T337 = vecOutComb_7[6];
assign io_dataOut_bits_63 = T338;
assign T338 = vecOutComb_7[7];
assign io_dataOut_valid = T339;
assign T339 = T13 | T340;
assign T340 = io_flushed & T341;
assign T341 = io_dataIn_valid | T342;
assign T342 = R6 != 3'h0;
assign io_dataIn_ready = T343;
assign T343 = T344 | io_flushed;
assign T344 = T345 ^ 1'h1;
assign T345 = T4 & io_flush;
always @(posedge clk) begin
if(io_flushed) begin
R1 <= 1'h0;
end else begin
R1 <= T3;
end
R6 <= T346;
R100 <= T19;
R132 <= T110;
R164 <= T142;
R196 <= T174;
R228 <= T206;
R260 <= T238;
R292 <= T270;
end
endmodule
module user_application(input clk, input rst,
input [31:0] devkit_version,
input [31:0] hw_time,
input [2:0] hw_rev,
input reg_w_en,
input [10:0] reg_w_addr,
input [31:0] reg_w_data,
input [10:0] reg_r_addr,
output[31:0] reg_r_data,
input [15:0] mem_w_en,
input [18:0] mem_w_addr,
input [127:0] mem_w_data,
input trx0_link_up,
output[63:0] tx0_data_usr,
output tx0_sof_usr,
output tx0_eof_usr,
output[2:0] tx0_len_usr,
output tx0_vld_usr,
input tx0_ack_usr,
input [63:0] tx0_data_host,
input tx0_sof_host,
input tx0_eof_host,
input [2:0] tx0_len_host,
input tx0_vld_host,
output tx0_ack_host,
input [63:0] rx0_data_usr,
input rx0_sof_usr,
input rx0_eof_usr,
input [2:0] rx0_len_usr,
input rx0_vld_usr,
input rx0_err_usr,
input rx0_pkt_drop_usr,
input rx0_crc_fail_usr,
input [31:0] rx0_timestamp_usr,
input rx0_is_vlan_usr,
input [11:0] rx0_vlan_usr,
output[63:0] rx0_data_host,
output rx0_sof_host,
output rx0_eof_host,
output[2:0] rx0_len_host,
output rx0_vld_host,
output rx0_err_host,
output rx0_pkt_drop_host,
output rx0_crc_fail_host,
output[31:0] rx0_timestamp_host,
output[7:0] rx0_match_host,
output[5:0] rx0_buffer_host,
input trx1_link_up,
output[63:0] tx1_data_usr,
output tx1_sof_usr,
output tx1_eof_usr,
output[2:0] tx1_len_usr,
output tx1_vld_usr,
input tx1_ack_usr,
input [63:0] tx1_data_host,
input tx1_sof_host,
input tx1_eof_host,
input [2:0] tx1_len_host,
input tx1_vld_host,
output tx1_ack_host,
input [63:0] rx1_data_usr,
input rx1_sof_usr,
input rx1_eof_usr,
input [2:0] rx1_len_usr,
input rx1_vld_usr,
input rx1_err_usr,
input rx1_pkt_drop_usr,
input rx1_crc_fail_usr,
input [31:0] rx1_timestamp_usr,
input rx1_is_vlan_usr,
input [11:0] rx1_vlan_usr,
output[63:0] rx1_data_host,
output rx1_sof_host,
output rx1_eof_host,
output[2:0] rx1_len_host,
output rx1_vld_host,
output rx1_err_host,
output rx1_pkt_drop_host,
output rx1_crc_fail_host,
output[31:0] rx1_timestamp_host,
output[7:0] rx1_match_host,
output[5:0] rx1_buffer_host,
input trx2_link_up,
output[63:0] tx2_data_usr,
output tx2_sof_usr,
output tx2_eof_usr,
output[2:0] tx2_len_usr,
output tx2_vld_usr,
input tx2_ack_usr,
input [63:0] tx2_data_host,
input tx2_sof_host,
input tx2_eof_host,
input [2:0] tx2_len_host,
input tx2_vld_host,
output tx2_ack_host,
input [63:0] rx2_data_usr,
input rx2_sof_usr,
input rx2_eof_usr,
input [2:0] rx2_len_usr,
input rx2_vld_usr,
input rx2_err_usr,
input rx2_pkt_drop_usr,
input rx2_crc_fail_usr,
input [31:0] rx2_timestamp_usr,
input rx2_is_vlan_usr,
input [11:0] rx2_vlan_usr,
output[63:0] rx2_data_host,
output rx2_sof_host,
output rx2_eof_host,
output[2:0] rx2_len_host,
output rx2_vld_host,
output rx2_err_host,
output rx2_pkt_drop_host,
output rx2_crc_fail_host,
output[31:0] rx2_timestamp_host,
output[7:0] rx2_match_host,
output[5:0] rx2_buffer_host,
input trx3_link_up,
output[63:0] tx3_data_usr,
output tx3_sof_usr,
output tx3_eof_usr,
output[2:0] tx3_len_usr,
output tx3_vld_usr,
input tx3_ack_usr,
input [63:0] tx3_data_host,
input tx3_sof_host,
input tx3_eof_host,
input [2:0] tx3_len_host,
input tx3_vld_host,
output tx3_ack_host,
input [63:0] rx3_data_usr,
input rx3_sof_usr,
input rx3_eof_usr,
input [2:0] rx3_len_usr,
input rx3_vld_usr,
input rx3_err_usr,
input rx3_pkt_drop_usr,
input rx3_crc_fail_usr,
input [31:0] rx3_timestamp_usr,
input rx3_is_vlan_usr,
input [11:0] rx3_vlan_usr,
output[63:0] rx3_data_host,
output rx3_sof_host,
output rx3_eof_host,
output[2:0] rx3_len_host,
output rx3_vld_host,
output rx3_err_host,
output rx3_pkt_drop_host,
output rx3_crc_fail_host,
output[31:0] rx3_timestamp_host,
output[7:0] rx3_match_host,
output[5:0] rx3_buffer_host
);
wire T836;
wire T837;
reg [31:0] controlReg;
wire[31:0] T1;
wire[31:0] T838;
wire[31:0] T2;
wire T3;
wire T4;
wire[15:0] T5;
wire[3:0] T6;
wire[3:0] T839;
wire T0;
wire fifoDrain;
wire T7;
reg sending;
wire T840;
wire T8;
wire T9;
wire T10;
wire T11;
wire T12;
wire T13;
wire eof;
reg [3:0] segmentCounter;
wire[3:0] T841;
wire[3:0] T14;
wire[3:0] T15;
wire[3:0] T16;
wire[3:0] T17;
wire T18;
wire T19;
wire[7:0] bufferByte_0;
wire[7:0] T842;
wire[8:0] T20;
wire[8:0] T21;
wire[8:0] T22;
wire[8:0] T843;
wire T23;
wire T24;
reg buffer_7;
wire[8:0] T25;
wire[8:0] T26;
wire[8:0] T844;
wire[7:0] T27;
wire[7:0] T28;
wire[7:0] T29;
wire[7:0] T845;
wire T30;
wire T31;
reg buffer_6;
wire[7:0] T32;
wire[7:0] T33;
wire[7:0] T34;
wire[7:0] T846;
wire[6:0] T35;
wire[6:0] T36;
wire[6:0] T847;
wire T37;
wire T38;
reg buffer_5;
wire T848;
wire[7:0] T39;
wire[7:0] T849;
wire[6:0] T40;
wire T850;
wire[7:0] T41;
wire[7:0] T851;
wire[5:0] T42;
wire[5:0] T43;
wire[5:0] T852;
wire T44;
wire T45;
reg buffer_4;
wire[1:0] T853;
wire T854;
wire[7:0] T46;
wire[7:0] T855;
wire[5:0] T47;
wire[1:0] T856;
wire T857;
wire[7:0] T48;
wire[7:0] T858;
wire[4:0] T49;
wire[4:0] T50;
wire[4:0] T859;
wire T51;
wire T52;
reg buffer_3;
wire[2:0] T860;
wire T861;
wire[7:0] T53;
wire[7:0] T862;
wire[4:0] T54;
wire[2:0] T863;
wire T864;
wire[7:0] T55;
wire[7:0] T865;
wire[3:0] T56;
wire[3:0] T57;
wire[3:0] T866;
wire T58;
wire T59;
reg buffer_2;
wire[3:0] T867;
wire T868;
wire[7:0] T60;
wire[7:0] T869;
wire[3:0] T61;
wire[3:0] T870;
wire T871;
wire[7:0] T62;
wire[7:0] T872;
wire[2:0] T63;
wire[2:0] T64;
wire[2:0] T873;
wire T65;
wire T66;
reg buffer_1;
wire[4:0] T874;
wire T875;
wire[7:0] T67;
wire[7:0] T876;
wire[2:0] T68;
wire[4:0] T877;
wire T878;
wire[7:0] T69;
wire[7:0] T879;
wire[1:0] T70;
wire[1:0] T71;
wire[1:0] T880;
wire T72;
wire T73;
reg buffer_0;
wire[5:0] T881;
wire T882;
wire[7:0] T74;
wire[7:0] T883;
wire[1:0] T75;
wire[5:0] T884;
wire T885;
wire[7:0] bufferByte_1;
wire[7:0] T886;
wire[8:0] T76;
wire[8:0] T77;
wire[8:0] T78;
wire[8:0] T887;
wire T79;
wire T80;
reg buffer_15;
wire[8:0] T81;
wire[8:0] T82;
wire[8:0] T888;
wire[7:0] T83;
wire[7:0] T84;
wire[7:0] T85;
wire[7:0] T889;
wire T86;
wire T87;
reg buffer_14;
wire[7:0] T88;
wire[7:0] T89;
wire[7:0] T90;
wire[7:0] T890;
wire[6:0] T91;
wire[6:0] T92;
wire[6:0] T891;
wire T93;
wire T94;
reg buffer_13;
wire T892;
wire[7:0] T95;
wire[7:0] T893;
wire[6:0] T96;
wire T894;
wire[7:0] T97;
wire[7:0] T895;
wire[5:0] T98;
wire[5:0] T99;
wire[5:0] T896;
wire T100;
wire T101;
reg buffer_12;
wire[1:0] T897;
wire T898;
wire[7:0] T102;
wire[7:0] T899;
wire[5:0] T103;
wire[1:0] T900;
wire T901;
wire[7:0] T104;
wire[7:0] T902;
wire[4:0] T105;
wire[4:0] T106;
wire[4:0] T903;
wire T107;
wire T108;
reg buffer_11;
wire[2:0] T904;
wire T905;
wire[7:0] T109;
wire[7:0] T906;
wire[4:0] T110;
wire[2:0] T907;
wire T908;
wire[7:0] T111;
wire[7:0] T909;
wire[3:0] T112;
wire[3:0] T113;
wire[3:0] T910;
wire T114;
wire T115;
reg buffer_10;
wire[3:0] T911;
wire T912;
wire[7:0] T116;
wire[7:0] T913;
wire[3:0] T117;
wire[3:0] T914;
wire T915;
wire[7:0] T118;
wire[7:0] T916;
wire[2:0] T119;
wire[2:0] T120;
wire[2:0] T917;
wire T121;
wire T122;
reg buffer_9;
wire[4:0] T918;
wire T919;
wire[7:0] T123;
wire[7:0] T920;
wire[2:0] T124;
wire[4:0] T921;
wire T922;
wire[7:0] T125;
wire[7:0] T923;
wire[1:0] T126;
wire[1:0] T127;
wire[1:0] T924;
wire T128;
wire T129;
reg buffer_8;
wire[5:0] T925;
wire T926;
wire[7:0] T130;
wire[7:0] T927;
wire[1:0] T131;
wire[5:0] T928;
wire T929;
wire[7:0] bufferByte_2;
wire[7:0] T930;
wire[8:0] T132;
wire[8:0] T133;
wire[8:0] T134;
wire[8:0] T931;
wire T135;
wire T136;
reg buffer_23;
wire[8:0] T137;
wire[8:0] T138;
wire[8:0] T932;
wire[7:0] T139;
wire[7:0] T140;
wire[7:0] T141;
wire[7:0] T933;
wire T142;
wire T143;
reg buffer_22;
wire[7:0] T144;
wire[7:0] T145;
wire[7:0] T146;
wire[7:0] T934;
wire[6:0] T147;
wire[6:0] T148;
wire[6:0] T935;
wire T149;
wire T150;
reg buffer_21;
wire T936;
wire[7:0] T151;
wire[7:0] T937;
wire[6:0] T152;
wire T938;
wire[7:0] T153;
wire[7:0] T939;
wire[5:0] T154;
wire[5:0] T155;
wire[5:0] T940;
wire T156;
wire T157;
reg buffer_20;
wire[1:0] T941;
wire T942;
wire[7:0] T158;
wire[7:0] T943;
wire[5:0] T159;
wire[1:0] T944;
wire T945;
wire[7:0] T160;
wire[7:0] T946;
wire[4:0] T161;
wire[4:0] T162;
wire[4:0] T947;
wire T163;
wire T164;
reg buffer_19;
wire[2:0] T948;
wire T949;
wire[7:0] T165;
wire[7:0] T950;
wire[4:0] T166;
wire[2:0] T951;
wire T952;
wire[7:0] T167;
wire[7:0] T953;
wire[3:0] T168;
wire[3:0] T169;
wire[3:0] T954;
wire T170;
wire T171;
reg buffer_18;
wire[3:0] T955;
wire T956;
wire[7:0] T172;
wire[7:0] T957;
wire[3:0] T173;
wire[3:0] T958;
wire T959;
wire[7:0] T174;
wire[7:0] T960;
wire[2:0] T175;
wire[2:0] T176;
wire[2:0] T961;
wire T177;
wire T178;
reg buffer_17;
wire[4:0] T962;
wire T963;
wire[7:0] T179;
wire[7:0] T964;
wire[2:0] T180;
wire[4:0] T965;
wire T966;
wire[7:0] T181;
wire[7:0] T967;
wire[1:0] T182;
wire[1:0] T183;
wire[1:0] T968;
wire T184;
wire T185;
reg buffer_16;
wire[5:0] T969;
wire T970;
wire[7:0] T186;
wire[7:0] T971;
wire[1:0] T187;
wire[5:0] T972;
wire T973;
wire[7:0] bufferByte_3;
wire[7:0] T974;
wire[8:0] T188;
wire[8:0] T189;
wire[8:0] T190;
wire[8:0] T975;
wire T191;
wire T192;
reg buffer_31;
wire[8:0] T193;
wire[8:0] T194;
wire[8:0] T976;
wire[7:0] T195;
wire[7:0] T196;
wire[7:0] T197;
wire[7:0] T977;
wire T198;
wire T199;
reg buffer_30;
wire[7:0] T200;
wire[7:0] T201;
wire[7:0] T202;
wire[7:0] T978;
wire[6:0] T203;
wire[6:0] T204;
wire[6:0] T979;
wire T205;
wire T206;
reg buffer_29;
wire T980;
wire[7:0] T207;
wire[7:0] T981;
wire[6:0] T208;
wire T982;
wire[7:0] T209;
wire[7:0] T983;
wire[5:0] T210;
wire[5:0] T211;
wire[5:0] T984;
wire T212;
wire T213;
reg buffer_28;
wire[1:0] T985;
wire T986;
wire[7:0] T214;
wire[7:0] T987;
wire[5:0] T215;
wire[1:0] T988;
wire T989;
wire[7:0] T216;
wire[7:0] T990;
wire[4:0] T217;
wire[4:0] T218;
wire[4:0] T991;
wire T219;
wire T220;
reg buffer_27;
wire[2:0] T992;
wire T993;
wire[7:0] T221;
wire[7:0] T994;
wire[4:0] T222;
wire[2:0] T995;
wire T996;
wire[7:0] T223;
wire[7:0] T997;
wire[3:0] T224;
wire[3:0] T225;
wire[3:0] T998;
wire T226;
wire T227;
reg buffer_26;
wire[3:0] T999;
wire T1000;
wire[7:0] T228;
wire[7:0] T1001;
wire[3:0] T229;
wire[3:0] T1002;
wire T1003;
wire[7:0] T230;
wire[7:0] T1004;
wire[2:0] T231;
wire[2:0] T232;
wire[2:0] T1005;
wire T233;
wire T234;
reg buffer_25;
wire[4:0] T1006;
wire T1007;
wire[7:0] T235;
wire[7:0] T1008;
wire[2:0] T236;
wire[4:0] T1009;
wire T1010;
wire[7:0] T237;
wire[7:0] T1011;
wire[1:0] T238;
wire[1:0] T239;
wire[1:0] T1012;
wire T240;
wire T241;
reg buffer_24;
wire[5:0] T1013;
wire T1014;
wire[7:0] T242;
wire[7:0] T1015;
wire[1:0] T243;
wire[5:0] T1016;
wire T1017;
wire[7:0] bufferByte_4;
wire[7:0] T1018;
wire[8:0] T244;
wire[8:0] T245;
wire[8:0] T246;
wire[8:0] T1019;
wire T247;
wire T248;
reg buffer_39;
wire[8:0] T249;
wire[8:0] T250;
wire[8:0] T1020;
wire[7:0] T251;
wire[7:0] T252;
wire[7:0] T253;
wire[7:0] T1021;
wire T254;
wire T255;
reg buffer_38;
wire[7:0] T256;
wire[7:0] T257;
wire[7:0] T258;
wire[7:0] T1022;
wire[6:0] T259;
wire[6:0] T260;
wire[6:0] T1023;
wire T261;
wire T262;
reg buffer_37;
wire T1024;
wire[7:0] T263;
wire[7:0] T1025;
wire[6:0] T264;
wire T1026;
wire[7:0] T265;
wire[7:0] T1027;
wire[5:0] T266;
wire[5:0] T267;
wire[5:0] T1028;
wire T268;
wire T269;
reg buffer_36;
wire[1:0] T1029;
wire T1030;
wire[7:0] T270;
wire[7:0] T1031;
wire[5:0] T271;
wire[1:0] T1032;
wire T1033;
wire[7:0] T272;
wire[7:0] T1034;
wire[4:0] T273;
wire[4:0] T274;
wire[4:0] T1035;
wire T275;
wire T276;
reg buffer_35;
wire[2:0] T1036;
wire T1037;
wire[7:0] T277;
wire[7:0] T1038;
wire[4:0] T278;
wire[2:0] T1039;
wire T1040;
wire[7:0] T279;
wire[7:0] T1041;
wire[3:0] T280;
wire[3:0] T281;
wire[3:0] T1042;
wire T282;
wire T283;
reg buffer_34;
wire[3:0] T1043;
wire T1044;
wire[7:0] T284;
wire[7:0] T1045;
wire[3:0] T285;
wire[3:0] T1046;
wire T1047;
wire[7:0] T286;
wire[7:0] T1048;
wire[2:0] T287;
wire[2:0] T288;
wire[2:0] T1049;
wire T289;
wire T290;
reg buffer_33;
wire[4:0] T1050;
wire T1051;
wire[7:0] T291;
wire[7:0] T1052;
wire[2:0] T292;
wire[4:0] T1053;
wire T1054;
wire[7:0] T293;
wire[7:0] T1055;
wire[1:0] T294;
wire[1:0] T295;
wire[1:0] T1056;
wire T296;
wire T297;
reg buffer_32;
wire[5:0] T1057;
wire T1058;
wire[7:0] T298;
wire[7:0] T1059;
wire[1:0] T299;
wire[5:0] T1060;
wire T1061;
wire[7:0] bufferByte_5;
wire[7:0] T1062;
wire[8:0] T300;
wire[8:0] T301;
wire[8:0] T302;
wire[8:0] T1063;
wire T303;
wire T304;
reg buffer_47;
wire[8:0] T305;
wire[8:0] T306;
wire[8:0] T1064;
wire[7:0] T307;
wire[7:0] T308;
wire[7:0] T309;
wire[7:0] T1065;
wire T310;
wire T311;
reg buffer_46;
wire[7:0] T312;
wire[7:0] T313;
wire[7:0] T314;
wire[7:0] T1066;
wire[6:0] T315;
wire[6:0] T316;
wire[6:0] T1067;
wire T317;
wire T318;
reg buffer_45;
wire T1068;
wire[7:0] T319;
wire[7:0] T1069;
wire[6:0] T320;
wire T1070;
wire[7:0] T321;
wire[7:0] T1071;
wire[5:0] T322;
wire[5:0] T323;
wire[5:0] T1072;
wire T324;
wire T325;
reg buffer_44;
wire[1:0] T1073;
wire T1074;
wire[7:0] T326;
wire[7:0] T1075;
wire[5:0] T327;
wire[1:0] T1076;
wire T1077;
wire[7:0] T328;
wire[7:0] T1078;
wire[4:0] T329;
wire[4:0] T330;
wire[4:0] T1079;
wire T331;
wire T332;
reg buffer_43;
wire[2:0] T1080;
wire T1081;
wire[7:0] T333;
wire[7:0] T1082;
wire[4:0] T334;
wire[2:0] T1083;
wire T1084;
wire[7:0] T335;
wire[7:0] T1085;
wire[3:0] T336;
wire[3:0] T337;
wire[3:0] T1086;
wire T338;
wire T339;
reg buffer_42;
wire[3:0] T1087;
wire T1088;
wire[7:0] T340;
wire[7:0] T1089;
wire[3:0] T341;
wire[3:0] T1090;
wire T1091;
wire[7:0] T342;
wire[7:0] T1092;
wire[2:0] T343;
wire[2:0] T344;
wire[2:0] T1093;
wire T345;
wire T346;
reg buffer_41;
wire[4:0] T1094;
wire T1095;
wire[7:0] T347;
wire[7:0] T1096;
wire[2:0] T348;
wire[4:0] T1097;
wire T1098;
wire[7:0] T349;
wire[7:0] T1099;
wire[1:0] T350;
wire[1:0] T351;
wire[1:0] T1100;
wire T352;
wire T353;
reg buffer_40;
wire[5:0] T1101;
wire T1102;
wire[7:0] T354;
wire[7:0] T1103;
wire[1:0] T355;
wire[5:0] T1104;
wire T1105;
wire[7:0] bufferByte_6;
wire[7:0] T1106;
wire[8:0] T356;
wire[8:0] T357;
wire[8:0] T358;
wire[8:0] T1107;
wire T359;
wire T360;
reg buffer_55;
wire[8:0] T361;
wire[8:0] T362;
wire[8:0] T1108;
wire[7:0] T363;
wire[7:0] T364;
wire[7:0] T365;
wire[7:0] T1109;
wire T366;
wire T367;
reg buffer_54;
wire[7:0] T368;
wire[7:0] T369;
wire[7:0] T370;
wire[7:0] T1110;
wire[6:0] T371;
wire[6:0] T372;
wire[6:0] T1111;
wire T373;
wire T374;
reg buffer_53;
wire T1112;
wire[7:0] T375;
wire[7:0] T1113;
wire[6:0] T376;
wire T1114;
wire[7:0] T377;
wire[7:0] T1115;
wire[5:0] T378;
wire[5:0] T379;
wire[5:0] T1116;
wire T380;
wire T381;
reg buffer_52;
wire[1:0] T1117;
wire T1118;
wire[7:0] T382;
wire[7:0] T1119;
wire[5:0] T383;
wire[1:0] T1120;
wire T1121;
wire[7:0] T384;
wire[7:0] T1122;
wire[4:0] T385;
wire[4:0] T386;
wire[4:0] T1123;
wire T387;
wire T388;
reg buffer_51;
wire[2:0] T1124;
wire T1125;
wire[7:0] T389;
wire[7:0] T1126;
wire[4:0] T390;
wire[2:0] T1127;
wire T1128;
wire[7:0] T391;
wire[7:0] T1129;
wire[3:0] T392;
wire[3:0] T393;
wire[3:0] T1130;
wire T394;
wire T395;
reg buffer_50;
wire[3:0] T1131;
wire T1132;
wire[7:0] T396;
wire[7:0] T1133;
wire[3:0] T397;
wire[3:0] T1134;
wire T1135;
wire[7:0] T398;
wire[7:0] T1136;
wire[2:0] T399;
wire[2:0] T400;
wire[2:0] T1137;
wire T401;
wire T402;
reg buffer_49;
wire[4:0] T1138;
wire T1139;
wire[7:0] T403;
wire[7:0] T1140;
wire[2:0] T404;
wire[4:0] T1141;
wire T1142;
wire[7:0] T405;
wire[7:0] T1143;
wire[1:0] T406;
wire[1:0] T407;
wire[1:0] T1144;
wire T408;
wire T409;
reg buffer_48;
wire[5:0] T1145;
wire T1146;
wire[7:0] T410;
wire[7:0] T1147;
wire[1:0] T411;
wire[5:0] T1148;
wire T1149;
wire[7:0] bufferByte_7;
wire[7:0] T1150;
wire[8:0] T412;
wire[8:0] T413;
wire[8:0] T414;
wire[8:0] T1151;
wire T415;
wire T416;
reg buffer_63;
wire[8:0] T417;
wire[8:0] T418;
wire[8:0] T1152;
wire[7:0] T419;
wire[7:0] T420;
wire[7:0] T421;
wire[7:0] T1153;
wire T422;
wire T423;
reg buffer_62;
wire[7:0] T424;
wire[7:0] T425;
wire[7:0] T426;
wire[7:0] T1154;
wire[6:0] T427;
wire[6:0] T428;
wire[6:0] T1155;
wire T429;
wire T430;
reg buffer_61;
wire T1156;
wire[7:0] T431;
wire[7:0] T1157;
wire[6:0] T432;
wire T1158;
wire[7:0] T433;
wire[7:0] T1159;
wire[5:0] T434;
wire[5:0] T435;
wire[5:0] T1160;
wire T436;
wire T437;
reg buffer_60;
wire[1:0] T1161;
wire T1162;
wire[7:0] T438;
wire[7:0] T1163;
wire[5:0] T439;
wire[1:0] T1164;
wire T1165;
wire[7:0] T440;
wire[7:0] T1166;
wire[4:0] T441;
wire[4:0] T442;
wire[4:0] T1167;
wire T443;
wire T444;
reg buffer_59;
wire[2:0] T1168;
wire T1169;
wire[7:0] T445;
wire[7:0] T1170;
wire[4:0] T446;
wire[2:0] T1171;
wire T1172;
wire[7:0] T447;
wire[7:0] T1173;
wire[3:0] T448;
wire[3:0] T449;
wire[3:0] T1174;
wire T450;
wire T451;
reg buffer_58;
wire[3:0] T1175;
wire T1176;
wire[7:0] T452;
wire[7:0] T1177;
wire[3:0] T453;
wire[3:0] T1178;
wire T1179;
wire[7:0] T454;
wire[7:0] T1180;
wire[2:0] T455;
wire[2:0] T456;
wire[2:0] T1181;
wire T457;
wire T458;
reg buffer_57;
wire[4:0] T1182;
wire T1183;
wire[7:0] T459;
wire[7:0] T1184;
wire[2:0] T460;
wire[4:0] T1185;
wire T1186;
wire[7:0] T461;
wire[7:0] T1187;
wire[1:0] T462;
wire[1:0] T463;
wire[1:0] T1188;
wire T464;
wire T465;
reg buffer_56;
wire[5:0] T1189;
wire T1190;
wire[7:0] T466;
wire[7:0] T1191;
wire[1:0] T467;
wire[5:0] T1192;
wire T1193;
reg bufferVld;
wire flush;
wire T468;
wire T469;
reg [6:0] buffCount;
wire[6:0] T1194;
wire[6:0] T470;
wire[6:0] T471;
wire[6:0] T472;
wire T473;
wire vecDataOut_0;
wire T474;
wire vecDataOut_1;
wire T475;
wire vecDataOut_2;
wire T476;
wire vecDataOut_3;
wire T477;
wire vecDataOut_4;
wire T478;
wire vecDataOut_5;
wire T479;
wire vecDataOut_6;
wire T480;
wire vecDataOut_7;
wire T481;
wire[7:0] T482;
wire[7:0] T483;
wire[7:0] T484;
wire[7:0] T485;
wire[7:0] T486;
wire[7:0] T487;
wire[7:0] T488;
wire[7:0] T489;
wire[127:0] T1195;
wire[128:0] T490;
wire[128:0] T1196;
wire[127:0] T491;
wire[7:0] T492;
wire[7:0] T493;
wire[127:0] T494;
reg [127:0] userMem [127:0];
wire[127:0] T495;
wire[127:0] T1197;
wire[127:0] T1198;
wire[127:0] T1199;
wire[127:0] T1200;
wire[15:0] T1201;
wire[127:0] T1202;
wire[127:0] T1203;
wire[63:0] T1204;
wire[31:0] T1205;
wire[15:0] T1206;
wire[7:0] T1207;
wire[127:0] T1208;
wire[6:0] T1209;
wire[7:0] T1210;
wire[15:0] T1211;
wire[7:0] T1212;
wire[7:0] T1213;
wire[31:0] T1214;
wire[15:0] T1215;
wire[7:0] T1216;
wire[7:0] T1217;
wire[15:0] T1218;
wire[7:0] T1219;
wire[7:0] T1220;
wire[63:0] T1221;
wire[31:0] T1222;
wire[15:0] T1223;
wire[7:0] T1224;
wire[7:0] T1225;
wire[15:0] T1226;
wire[7:0] T1227;
wire[7:0] T1228;
wire[31:0] T1229;
wire[15:0] T1230;
wire[7:0] T1231;
wire[7:0] T1232;
wire[15:0] T1233;
wire[7:0] T1234;
wire[7:0] T1235;
wire[127:0] T1236;
wire[127:0] T1237;
wire[127:0] T496;
wire[127:0] T497;
wire[63:0] T498;
wire[31:0] T499;
wire[15:0] T500;
wire[7:0] memWData_0;
wire[7:0] T501;
wire[7:0] memWData_1;
wire[7:0] T502;
wire[15:0] T503;
wire[7:0] memWData_2;
wire[7:0] T504;
wire[7:0] memWData_3;
wire[7:0] T505;
wire[31:0] T506;
wire[15:0] T507;
wire[7:0] memWData_4;
wire[7:0] T508;
wire[7:0] memWData_5;
wire[7:0] T509;
wire[15:0] T510;
wire[7:0] memWData_6;
wire[7:0] T511;
wire[7:0] memWData_7;
wire[7:0] T512;
wire[63:0] T513;
wire[31:0] T514;
wire[15:0] T515;
wire[7:0] memWData_8;
wire[7:0] T516;
wire[7:0] memWData_9;
wire[7:0] T517;
wire[15:0] T518;
wire[7:0] memWData_10;
wire[7:0] T519;
wire[7:0] memWData_11;
wire[7:0] T520;
wire[31:0] T521;
wire[15:0] T522;
wire[7:0] memWData_12;
wire[7:0] T523;
wire[7:0] memWData_13;
wire[7:0] T524;
wire[15:0] T525;
wire[7:0] memWData_14;
wire[7:0] T526;
wire[7:0] memWData_15;
wire[7:0] T527;
wire[6:0] T1238;
wire[6:0] T1239;
wire[128:0] T528;
wire[128:0] T529;
wire[128:0] T530;
wire[128:0] T1240;
wire[127:0] T531;
wire[127:0] T1241;
wire[119:0] T532;
wire[7:0] T533;
wire[7:0] T534;
wire[127:0] T535;
wire[127:0] T1242;
wire[120:0] T536;
wire[120:0] T537;
wire[6:0] T1243;
wire T1244;
wire[127:0] T538;
wire[127:0] T1245;
wire[111:0] T539;
wire[7:0] T540;
wire[7:0] T541;
wire[127:0] T542;
wire[127:0] T1246;
wire[112:0] T543;
wire[112:0] T544;
wire[14:0] T1247;
wire T1248;
wire[127:0] T545;
wire[127:0] T1249;
wire[103:0] T546;
wire[7:0] T547;
wire[7:0] T548;
wire[127:0] T549;
wire[127:0] T1250;
wire[104:0] T550;
wire[104:0] T551;
wire[22:0] T1251;
wire T1252;
wire[127:0] T552;
wire[127:0] T1253;
wire[95:0] T553;
wire[7:0] T554;
wire[7:0] T555;
wire[127:0] T556;
wire[127:0] T1254;
wire[96:0] T557;
wire[96:0] T558;
wire[30:0] T1255;
wire T1256;
wire[127:0] T559;
wire[127:0] T1257;
wire[87:0] T560;
wire[7:0] T561;
wire[7:0] T562;
wire[127:0] T563;
wire[127:0] T1258;
wire[88:0] T564;
wire[88:0] T565;
wire[38:0] T1259;
wire T1260;
wire[127:0] T566;
wire[127:0] T1261;
wire[79:0] T567;
wire[7:0] T568;
wire[7:0] T569;
wire[127:0] T570;
wire[127:0] T1262;
wire[80:0] T571;
wire[80:0] T572;
wire[46:0] T1263;
wire T1264;
wire[127:0] T573;
wire[127:0] T1265;
wire[71:0] T574;
wire[7:0] T575;
wire[7:0] T576;
wire[127:0] T577;
wire[127:0] T1266;
wire[72:0] T578;
wire[72:0] T579;
wire[54:0] T1267;
wire T1268;
wire[127:0] T580;
wire[127:0] T1269;
wire[63:0] T581;
wire[7:0] T582;
wire[7:0] T583;
wire[127:0] T584;
wire[127:0] T1270;
wire[64:0] T585;
wire[64:0] T586;
wire[62:0] T1271;
wire T1272;
wire[127:0] T587;
wire[127:0] T1273;
wire[55:0] T588;
wire[7:0] T589;
wire[7:0] T590;
wire[127:0] T591;
wire[127:0] T1274;
wire[56:0] T592;
wire[56:0] T593;
wire[70:0] T1275;
wire T1276;
wire[127:0] T594;
wire[127:0] T1277;
wire[47:0] T595;
wire[7:0] T596;
wire[7:0] T597;
wire[127:0] T598;
wire[127:0] T1278;
wire[48:0] T599;
wire[48:0] T600;
wire[78:0] T1279;
wire T1280;
wire[127:0] T601;
wire[127:0] T1281;
wire[39:0] T602;
wire[7:0] T603;
wire[7:0] T604;
wire[127:0] T605;
wire[127:0] T1282;
wire[40:0] T606;
wire[40:0] T607;
wire[86:0] T1283;
wire T1284;
wire[127:0] T608;
wire[127:0] T1285;
wire[31:0] T609;
wire[7:0] T610;
wire[7:0] T611;
wire[127:0] T612;
wire[127:0] T1286;
wire[32:0] T613;
wire[32:0] T614;
wire[94:0] T1287;
wire T1288;
wire[127:0] T615;
wire[127:0] T1289;
wire[23:0] T616;
wire[7:0] T617;
wire[7:0] T618;
wire[127:0] T619;
wire[127:0] T1290;
wire[24:0] T620;
wire[24:0] T621;
wire[102:0] T1291;
wire T1292;
wire[127:0] T622;
wire[127:0] T1293;
wire[15:0] T623;
wire[7:0] T624;
wire[7:0] T625;
wire[127:0] T626;
wire[127:0] T1294;
wire[16:0] T627;
wire[16:0] T628;
wire[110:0] T1295;
wire T1296;
wire[127:0] T629;
wire[127:0] T1297;
wire[7:0] T630;
wire[7:0] T631;
wire[7:0] T632;
wire[127:0] T633;
wire[127:0] T1298;
wire[8:0] T634;
wire[8:0] T635;
wire[118:0] T1299;
wire T1300;
reg [31:0] regIntR_0;
wire[31:0] T636;
wire[31:0] T1301;
wire[31:0] T637;
wire T638;
wire T639;
reg [31:0] regIntR_1;
wire[31:0] T640;
wire[31:0] T1302;
wire[31:0] T641;
wire T642;
wire T643;
reg [31:0] regIntR_2;
wire[31:0] T644;
wire[31:0] T1303;
wire[31:0] T645;
wire T646;
wire T647;
reg [31:0] regIntR_3;
wire[31:0] T648;
wire[31:0] T1304;
wire[31:0] T649;
wire T650;
wire T651;
reg [31:0] regIntR_4;
wire[31:0] T652;
wire[31:0] T1305;
wire[31:0] T653;
wire T654;
wire T655;
reg [31:0] regIntR_5;
wire[31:0] T656;
wire[31:0] T1306;
wire[31:0] T657;
wire T658;
wire T659;
reg [31:0] regIntR_6;
wire[31:0] T660;
wire[31:0] T1307;
wire[31:0] T661;
wire T662;
wire T663;
reg [31:0] regIntR_7;
wire[31:0] T664;
wire[31:0] T1308;
wire[31:0] T665;
wire T666;
wire T667;
reg [31:0] regIntR_8;
wire[31:0] T668;
wire[31:0] T1309;
wire[31:0] T669;
wire T670;
wire T671;
reg [31:0] regIntR_9;
wire[31:0] T672;
wire[31:0] T1310;
wire[31:0] T673;
wire T674;
wire T675;
reg [31:0] regIntR_10;
wire[31:0] T676;
wire[31:0] T1311;
wire[31:0] T677;
wire T678;
wire T679;
reg [31:0] regIntR_11;
wire[31:0] T680;
wire[31:0] T1312;
wire[31:0] T681;
wire T682;
wire T683;
reg [31:0] regIntR_12;
wire[31:0] T684;
wire[31:0] T1313;
wire[31:0] T685;
wire T686;
wire T687;
reg [31:0] regIntR_13;
wire[31:0] T688;
wire[31:0] T1314;
wire[31:0] T689;
wire T690;
wire T691;
reg [31:0] regIntR_14;
wire[31:0] T692;
wire[31:0] T1315;
wire[31:0] T693;
wire T694;
wire T695;
wire T696;
wire[2:0] len;
wire[2:0] T697;
wire T698;
wire T699;
wire sof;
wire[63:0] tx1Output;
wire[63:0] T1316;
wire[64:0] T700;
wire[64:0] T1317;
wire[63:0] T701;
wire[7:0] T702;
wire[64:0] T703;
wire[64:0] T704;
wire[64:0] T705;
wire[64:0] T1318;
wire[63:0] T706;
wire[63:0] T1319;
wire[55:0] T707;
wire[7:0] T708;
wire[63:0] T709;
wire[63:0] T1320;
wire[56:0] T710;
wire[56:0] T711;
wire[6:0] T1321;
wire T1322;
wire[63:0] T712;
wire[63:0] T1323;
wire[47:0] T713;
wire[7:0] T714;
wire[63:0] T715;
wire[63:0] T1324;
wire[48:0] T716;
wire[48:0] T717;
wire[14:0] T1325;
wire T1326;
wire[63:0] T718;
wire[63:0] T1327;
wire[39:0] T719;
wire[7:0] T720;
wire[63:0] T721;
wire[63:0] T1328;
wire[40:0] T722;
wire[40:0] T723;
wire[22:0] T1329;
wire T1330;
wire[63:0] T724;
wire[63:0] T1331;
wire[31:0] T725;
wire[7:0] T726;
wire[63:0] T727;
wire[63:0] T1332;
wire[32:0] T728;
wire[32:0] T729;
wire[30:0] T1333;
wire T1334;
wire[63:0] T730;
wire[63:0] T1335;
wire[23:0] T731;
wire[7:0] T732;
wire[63:0] T733;
wire[63:0] T1336;
wire[24:0] T734;
wire[24:0] T735;
wire[38:0] T1337;
wire T1338;
wire[63:0] T736;
wire[63:0] T1339;
wire[15:0] T737;
wire[7:0] T738;
wire[63:0] T739;
wire[63:0] T1340;
wire[16:0] T740;
wire[16:0] T741;
wire[46:0] T1341;
wire T1342;
wire[63:0] T742;
wire[63:0] T1343;
wire[7:0] T743;
wire[7:0] T744;
wire[63:0] T745;
wire[63:0] T1344;
wire[8:0] T746;
wire[8:0] T747;
wire[54:0] T1345;
wire T1346;
wire[31:0] T748;
wire[31:0] T749;
wire[31:0] T750;
wire[31:0] T751;
reg [31:0] regIntW_0;
wire[31:0] T752;
wire[31:0] T1347;
wire[31:0] T753;
reg [31:0] regIntW_1;
wire[31:0] T754;
wire[31:0] T1348;
wire[31:0] T755;
wire T756;
wire[3:0] T757;
wire[3:0] T1349;
wire[31:0] T758;
reg [31:0] regIntW_2;
wire[31:0] T759;
wire[31:0] T1350;
wire[31:0] T760;
reg [31:0] regIntW_3;
wire[31:0] T761;
wire[31:0] T1351;
wire[31:0] T762;
wire T763;
wire T764;
wire[31:0] T765;
wire[31:0] T766;
reg [31:0] regIntW_4;
wire[31:0] T767;
wire[31:0] T1352;
wire[31:0] T768;
reg [31:0] regIntW_5;
wire[31:0] T769;
wire[31:0] T1353;
wire[31:0] T770;
wire T771;
wire[31:0] T772;
reg [31:0] regIntW_6;
wire[31:0] T773;
wire[31:0] T1354;
wire[31:0] T774;
reg [31:0] regIntW_7;
wire[31:0] T775;
wire[31:0] T1355;
wire[31:0] T776;
wire T777;
wire T778;
wire T779;
wire[31:0] T780;
wire[31:0] T781;
wire[31:0] T782;
reg [31:0] regIntW_8;
wire[31:0] T783;
wire[31:0] T1356;
wire[31:0] T784;
reg [31:0] regIntW_9;
wire[31:0] T785;
wire[31:0] T1357;
wire[31:0] T786;
wire T787;
wire[31:0] T788;
reg [31:0] regIntW_10;
wire[31:0] T789;
wire[31:0] T1358;
wire[31:0] T790;
reg [31:0] regIntW_11;
wire[31:0] T791;
wire[31:0] T1359;
wire[31:0] T792;
wire T793;
wire T794;
wire[31:0] T795;
wire[31:0] T796;
reg [31:0] regIntW_12;
wire[31:0] T797;
wire[31:0] T1360;
wire[31:0] T798;
reg [31:0] regIntW_13;
wire[31:0] T799;
wire[31:0] T1361;
wire[31:0] T800;
wire T801;
wire[31:0] T802;
reg [31:0] regIntW_14;
wire[31:0] T803;
wire[31:0] T1362;
wire[31:0] T804;
reg [31:0] regIntW_15;
wire[31:0] T805;
wire[31:0] T1363;
wire[31:0] T1364;
wire[22:0] T806;
wire[6:0] error;
wire[6:0] T807;
reg userErr;
wire T1365;
wire T808;
wire T809;
wire errRst;
wire[5:0] T810;
reg dirOutFull;
wire T1366;
wire T811;
wire T812;
wire T813;
wire[4:0] T814;
reg txFifoFull;
wire T1367;
wire T815;
wire T816;
wire T817;
wire[3:0] T818;
reg fifoFull;
wire T1368;
wire T819;
wire T820;
wire T821;
wire[2:0] T822;
reg crcFail;
wire T1369;
wire T823;
wire T824;
wire[1:0] T825;
reg pktDrop;
wire T1370;
wire T826;
wire T827;
reg rx1Err;
wire T1371;
wire T828;
wire T829;
wire[15:0] T830;
wire[11:0] T831;
wire T832;
wire T833;
wire T834;
wire T835;
wire[63:0] stripper_io_out_data;
wire[2:0] stripper_io_out_len;
wire stripper_io_out_vld;
wire[7:0] combiner_io_dataOut_7;
wire[7:0] combiner_io_dataOut_6;
wire[7:0] combiner_io_dataOut_5;
wire[7:0] combiner_io_dataOut_4;
wire[7:0] combiner_io_dataOut_3;
wire[7:0] combiner_io_dataOut_2;
wire[7:0] combiner_io_dataOut_1;
wire[7:0] combiner_io_dataOut_0;
wire combiner_io_vldOut;
wire fifo_io_enq_ready;
wire fifo_io_deq_valid;
wire[7:0] fifo_io_deq_bits_7;
wire[7:0] fifo_io_deq_bits_6;
wire[7:0] fifo_io_deq_bits_5;
wire[7:0] fifo_io_deq_bits_4;
wire[7:0] fifo_io_deq_bits_3;
wire[7:0] fifo_io_deq_bits_2;
wire[7:0] fifo_io_deq_bits_1;
wire[7:0] fifo_io_deq_bits_0;
wire directOutputFifo_io_enq_ready;
wire directOutputFifo_io_deq_valid;
wire directOutputFifo_io_deq_bits_7;
wire directOutputFifo_io_deq_bits_6;
wire directOutputFifo_io_deq_bits_5;
wire directOutputFifo_io_deq_bits_4;
wire directOutputFifo_io_deq_bits_3;
wire directOutputFifo_io_deq_bits_2;
wire directOutputFifo_io_deq_bits_1;
wire directOutputFifo_io_deq_bits_0;
wire[5:0] directOutputFifo_io_count;
wire outToBuffer_io_dataIn_ready;
wire outToBuffer_io_dataOut_valid;
wire outToBuffer_io_dataOut_bits_63;
wire outToBuffer_io_dataOut_bits_62;
wire outToBuffer_io_dataOut_bits_61;
wire outToBuffer_io_dataOut_bits_60;
wire outToBuffer_io_dataOut_bits_59;
wire outToBuffer_io_dataOut_bits_58;
wire outToBuffer_io_dataOut_bits_57;
wire outToBuffer_io_dataOut_bits_56;
wire outToBuffer_io_dataOut_bits_55;
wire outToBuffer_io_dataOut_bits_54;
wire outToBuffer_io_dataOut_bits_53;
wire outToBuffer_io_dataOut_bits_52;
wire outToBuffer_io_dataOut_bits_51;
wire outToBuffer_io_dataOut_bits_50;
wire outToBuffer_io_dataOut_bits_49;
wire outToBuffer_io_dataOut_bits_48;
wire outToBuffer_io_dataOut_bits_47;
wire outToBuffer_io_dataOut_bits_46;
wire outToBuffer_io_dataOut_bits_45;
wire outToBuffer_io_dataOut_bits_44;
wire outToBuffer_io_dataOut_bits_43;
wire outToBuffer_io_dataOut_bits_42;
wire outToBuffer_io_dataOut_bits_41;
wire outToBuffer_io_dataOut_bits_40;
wire outToBuffer_io_dataOut_bits_39;
wire outToBuffer_io_dataOut_bits_38;
wire outToBuffer_io_dataOut_bits_37;
wire outToBuffer_io_dataOut_bits_36;
wire outToBuffer_io_dataOut_bits_35;
wire outToBuffer_io_dataOut_bits_34;
wire outToBuffer_io_dataOut_bits_33;
wire outToBuffer_io_dataOut_bits_32;
wire outToBuffer_io_dataOut_bits_31;
wire outToBuffer_io_dataOut_bits_30;
wire outToBuffer_io_dataOut_bits_29;
wire outToBuffer_io_dataOut_bits_28;
wire outToBuffer_io_dataOut_bits_27;
wire outToBuffer_io_dataOut_bits_26;
wire outToBuffer_io_dataOut_bits_25;
wire outToBuffer_io_dataOut_bits_24;
wire outToBuffer_io_dataOut_bits_23;
wire outToBuffer_io_dataOut_bits_22;
wire outToBuffer_io_dataOut_bits_21;
wire outToBuffer_io_dataOut_bits_20;
wire outToBuffer_io_dataOut_bits_19;
wire outToBuffer_io_dataOut_bits_18;
wire outToBuffer_io_dataOut_bits_17;
wire outToBuffer_io_dataOut_bits_16;
wire outToBuffer_io_dataOut_bits_15;
wire outToBuffer_io_dataOut_bits_14;
wire outToBuffer_io_dataOut_bits_13;
wire outToBuffer_io_dataOut_bits_12;
wire outToBuffer_io_dataOut_bits_11;
wire outToBuffer_io_dataOut_bits_10;
wire outToBuffer_io_dataOut_bits_9;
wire outToBuffer_io_dataOut_bits_8;
wire outToBuffer_io_dataOut_bits_7;
wire outToBuffer_io_dataOut_bits_6;
wire outToBuffer_io_dataOut_bits_5;
wire outToBuffer_io_dataOut_bits_4;
wire outToBuffer_io_dataOut_bits_3;
wire outToBuffer_io_dataOut_bits_2;
wire outToBuffer_io_dataOut_bits_1;
wire outToBuffer_io_dataOut_bits_0;
wire fifoTxOut_io_enq_ready;
wire fifoTxOut_io_deq_valid;
wire[7:0] fifoTxOut_io_deq_bits_7;
wire[7:0] fifoTxOut_io_deq_bits_6;
wire[7:0] fifoTxOut_io_deq_bits_5;
wire[7:0] fifoTxOut_io_deq_bits_4;
wire[7:0] fifoTxOut_io_deq_bits_3;
wire[7:0] fifoTxOut_io_deq_bits_2;
wire[7:0] fifoTxOut_io_deq_bits_1;
wire[7:0] fifoTxOut_io_deq_bits_0;
wire[5:0] fifoTxOut_io_count;
wire userMod_io_dataIn_ready;
wire[31:0] userMod_io_regOut_14;
wire[31:0] userMod_io_regOut_13;
wire[31:0] userMod_io_regOut_12;
wire[31:0] userMod_io_regOut_11;
wire[31:0] userMod_io_regOut_10;
wire[31:0] userMod_io_regOut_9;
wire[31:0] userMod_io_regOut_8;
wire[31:0] userMod_io_regOut_7;
wire[31:0] userMod_io_regOut_6;
wire[31:0] userMod_io_regOut_5;
wire[31:0] userMod_io_regOut_4;
wire[31:0] userMod_io_regOut_3;
wire[31:0] userMod_io_regOut_2;
wire[31:0] userMod_io_regOut_1;
wire[31:0] userMod_io_regOut_0;
wire userMod_io_regOutEn;
wire[18:0] userMod_io_memAddr;
wire userMod_io_error;
wire userMod_io_dataOut_valid;
wire[7:0] userMod_io_dataOut_bits;
`ifndef SYNTHESIS
// synthesis translate_off
integer initvar;
initial begin
#0.002;
controlReg = {1{$random}};
sending = {1{$random}};
segmentCounter = {1{$random}};
buffer_7 = {1{$random}};
buffer_6 = {1{$random}};
buffer_5 = {1{$random}};
buffer_4 = {1{$random}};
buffer_3 = {1{$random}};
buffer_2 = {1{$random}};
buffer_1 = {1{$random}};
buffer_0 = {1{$random}};
buffer_15 = {1{$random}};
buffer_14 = {1{$random}};
buffer_13 = {1{$random}};
buffer_12 = {1{$random}};
buffer_11 = {1{$random}};
buffer_10 = {1{$random}};
buffer_9 = {1{$random}};
buffer_8 = {1{$random}};
buffer_23 = {1{$random}};
buffer_22 = {1{$random}};
buffer_21 = {1{$random}};
buffer_20 = {1{$random}};
buffer_19 = {1{$random}};
buffer_18 = {1{$random}};
buffer_17 = {1{$random}};
buffer_16 = {1{$random}};
buffer_31 = {1{$random}};
buffer_30 = {1{$random}};
buffer_29 = {1{$random}};
buffer_28 = {1{$random}};
buffer_27 = {1{$random}};
buffer_26 = {1{$random}};
buffer_25 = {1{$random}};
buffer_24 = {1{$random}};
buffer_39 = {1{$random}};
buffer_38 = {1{$random}};
buffer_37 = {1{$random}};
buffer_36 = {1{$random}};
buffer_35 = {1{$random}};
buffer_34 = {1{$random}};
buffer_33 = {1{$random}};
buffer_32 = {1{$random}};
buffer_47 = {1{$random}};
buffer_46 = {1{$random}};
buffer_45 = {1{$random}};
buffer_44 = {1{$random}};
buffer_43 = {1{$random}};
buffer_42 = {1{$random}};
buffer_41 = {1{$random}};
buffer_40 = {1{$random}};
buffer_55 = {1{$random}};
buffer_54 = {1{$random}};
buffer_53 = {1{$random}};
buffer_52 = {1{$random}};
buffer_51 = {1{$random}};
buffer_50 = {1{$random}};
buffer_49 = {1{$random}};
buffer_48 = {1{$random}};
buffer_63 = {1{$random}};
buffer_62 = {1{$random}};
buffer_61 = {1{$random}};
buffer_60 = {1{$random}};
buffer_59 = {1{$random}};
buffer_58 = {1{$random}};
buffer_57 = {1{$random}};
buffer_56 = {1{$random}};
bufferVld = {1{$random}};
buffCount = {1{$random}};
for (initvar = 0; initvar < 128; initvar = initvar+1)
userMem[initvar] = {4{$random}};
regIntR_0 = {1{$random}};
regIntR_1 = {1{$random}};
regIntR_2 = {1{$random}};
regIntR_3 = {1{$random}};
regIntR_4 = {1{$random}};
regIntR_5 = {1{$random}};
regIntR_6 = {1{$random}};
regIntR_7 = {1{$random}};
regIntR_8 = {1{$random}};
regIntR_9 = {1{$random}};
regIntR_10 = {1{$random}};
regIntR_11 = {1{$random}};
regIntR_12 = {1{$random}};
regIntR_13 = {1{$random}};
regIntR_14 = {1{$random}};
regIntW_0 = {1{$random}};
regIntW_1 = {1{$random}};
regIntW_2 = {1{$random}};
regIntW_3 = {1{$random}};
regIntW_4 = {1{$random}};
regIntW_5 = {1{$random}};
regIntW_6 = {1{$random}};
regIntW_7 = {1{$random}};
regIntW_8 = {1{$random}};
regIntW_9 = {1{$random}};
regIntW_10 = {1{$random}};
regIntW_11 = {1{$random}};
regIntW_12 = {1{$random}};
regIntW_13 = {1{$random}};
regIntW_14 = {1{$random}};
regIntW_15 = {1{$random}};
userErr = {1{$random}};
dirOutFull = {1{$random}};
txFifoFull = {1{$random}};
fifoFull = {1{$random}};
crcFail = {1{$random}};
pktDrop = {1{$random}};
rx1Err = {1{$random}};
end
// synthesis translate_on
`endif
`ifndef SYNTHESIS
// synthesis translate_off
assign T1 = {1{$random}};
assign T636 = {1{$random}};
assign T640 = {1{$random}};
assign T644 = {1{$random}};
assign T648 = {1{$random}};
assign T652 = {1{$random}};
assign T656 = {1{$random}};
assign T660 = {1{$random}};
assign T664 = {1{$random}};
assign T668 = {1{$random}};
assign T672 = {1{$random}};
assign T676 = {1{$random}};
assign T680 = {1{$random}};
assign T684 = {1{$random}};
assign T688 = {1{$random}};
assign T692 = {1{$random}};
assign T752 = {1{$random}};
assign T754 = {1{$random}};
assign T759 = {1{$random}};
assign T761 = {1{$random}};
assign T767 = {1{$random}};
assign T769 = {1{$random}};
assign T773 = {1{$random}};
assign T775 = {1{$random}};
assign T783 = {1{$random}};
assign T785 = {1{$random}};
assign T789 = {1{$random}};
assign T791 = {1{$random}};
assign T797 = {1{$random}};
assign T799 = {1{$random}};
assign T803 = {1{$random}};
assign T805 = {1{$random}};
// synthesis translate_on
`endif
assign T836 = T837 | rst;
assign T837 = controlReg[1];
assign T838 = rst ? T1 : T2;
assign T2 = T3 ? reg_w_data : controlReg;
assign T3 = reg_w_en & T4;
assign T4 = T5[15];
assign T5 = 1'h1 << T6;
assign T6 = T839;
assign T839 = reg_w_addr[3:0];
assign T0 = T7 | fifoDrain;
assign fifoDrain = controlReg[2];
assign T7 = tx1_ack_usr & sending;
assign T840 = rst ? 1'h0 : T8;
assign T8 = T11 ? 1'h0 : T9;
assign T9 = sending | T10;
assign T10 = 6'hc <= fifoTxOut_io_count;
assign T11 = T12 | fifoDrain;
assign T12 = T13 & tx1_ack_usr;
assign T13 = eof & tx1_vld_usr;
assign eof = 4'hc <= segmentCounter;
assign T841 = rst ? 4'h0 : T14;
assign T14 = fifoDrain ? 4'h0 : T15;
assign T15 = T19 ? 4'h0 : T16;
assign T16 = T18 ? T17 : segmentCounter;
assign T17 = segmentCounter + 4'h1;
assign T18 = fifoTxOut_io_deq_valid & T0;
assign T19 = T18 & eof;
assign bufferByte_0 = T842;
assign T842 = T20[7:0];
assign T20 = T25 | T21;
assign T21 = T843 & T22;
assign T22 = 9'h80;
assign T843 = T23 ? 9'h1ff : 9'h0;
assign T23 = T24;
assign T24 = buffer_7;
assign T25 = T844 & T26;
assign T26 = ~ T22;
assign T844 = {1'h0, T27};
assign T27 = T32 | T28;
assign T28 = T845 & T29;
assign T29 = 8'h40;
assign T845 = T30 ? 8'hff : 8'h0;
assign T30 = T31;
assign T31 = buffer_6;
assign T32 = T34 & T33;
assign T33 = ~ T29;
assign T34 = T39 | T846;
assign T846 = {T848, T35};
assign T35 = T847 & T36;
assign T36 = 7'h20;
assign T847 = T37 ? 7'h7f : 7'h0;
assign T37 = T38;
assign T38 = buffer_5;
assign T848 = T35[6];
assign T39 = T41 & T849;
assign T849 = {T850, T40};
assign T40 = ~ T36;
assign T850 = T40[6];
assign T41 = T46 | T851;
assign T851 = {T853, T42};
assign T42 = T852 & T43;
assign T43 = 6'h10;
assign T852 = T44 ? 6'h3f : 6'h0;
assign T44 = T45;
assign T45 = buffer_4;
assign T853 = T854 ? 2'h3 : 2'h0;
assign T854 = T42[5];
assign T46 = T48 & T855;
assign T855 = {T856, T47};
assign T47 = ~ T43;
assign T856 = T857 ? 2'h3 : 2'h0;
assign T857 = T47[5];
assign T48 = T53 | T858;
assign T858 = {T860, T49};
assign T49 = T859 & T50;
assign T50 = 5'h8;
assign T859 = T51 ? 5'h1f : 5'h0;
assign T51 = T52;
assign T52 = buffer_3;
assign T860 = T861 ? 3'h7 : 3'h0;
assign T861 = T49[4];
assign T53 = T55 & T862;
assign T862 = {T863, T54};
assign T54 = ~ T50;
assign T863 = T864 ? 3'h7 : 3'h0;
assign T864 = T54[4];
assign T55 = T60 | T865;
assign T865 = {T867, T56};
assign T56 = T866 & T57;
assign T57 = 4'h4;
assign T866 = T58 ? 4'hf : 4'h0;
assign T58 = T59;
assign T59 = buffer_2;
assign T867 = T868 ? 4'hf : 4'h0;
assign T868 = T56[3];
assign T60 = T62 & T869;
assign T869 = {T870, T61};
assign T61 = ~ T57;
assign T870 = T871 ? 4'hf : 4'h0;
assign T871 = T61[3];
assign T62 = T67 | T872;
assign T872 = {T874, T63};
assign T63 = T873 & T64;
assign T64 = 3'h2;
assign T873 = T65 ? 3'h7 : 3'h0;
assign T65 = T66;
assign T66 = buffer_1;
assign T874 = T875 ? 5'h1f : 5'h0;
assign T875 = T63[2];
assign T67 = T69 & T876;
assign T876 = {T877, T68};
assign T68 = ~ T64;
assign T877 = T878 ? 5'h1f : 5'h0;
assign T878 = T68[2];
assign T69 = T74 | T879;
assign T879 = {T881, T70};
assign T70 = T880 & T71;
assign T71 = 2'h1;
assign T880 = T72 ? 2'h3 : 2'h0;
assign T72 = T73;
assign T73 = buffer_0;
assign T881 = T882 ? 6'h3f : 6'h0;
assign T882 = T70[1];
assign T74 = 8'h0 & T883;
assign T883 = {T884, T75};
assign T75 = ~ T71;
assign T884 = T885 ? 6'h3f : 6'h0;
assign T885 = T75[1];
assign bufferByte_1 = T886;
assign T886 = T76[7:0];
assign T76 = T81 | T77;
assign T77 = T887 & T78;
assign T78 = 9'h80;
assign T887 = T79 ? 9'h1ff : 9'h0;
assign T79 = T80;
assign T80 = buffer_15;
assign T81 = T888 & T82;
assign T82 = ~ T78;
assign T888 = {1'h0, T83};
assign T83 = T88 | T84;
assign T84 = T889 & T85;
assign T85 = 8'h40;
assign T889 = T86 ? 8'hff : 8'h0;
assign T86 = T87;
assign T87 = buffer_14;
assign T88 = T90 & T89;
assign T89 = ~ T85;
assign T90 = T95 | T890;
assign T890 = {T892, T91};
assign T91 = T891 & T92;
assign T92 = 7'h20;
assign T891 = T93 ? 7'h7f : 7'h0;
assign T93 = T94;
assign T94 = buffer_13;
assign T892 = T91[6];
assign T95 = T97 & T893;
assign T893 = {T894, T96};
assign T96 = ~ T92;
assign T894 = T96[6];
assign T97 = T102 | T895;
assign T895 = {T897, T98};
assign T98 = T896 & T99;
assign T99 = 6'h10;
assign T896 = T100 ? 6'h3f : 6'h0;
assign T100 = T101;
assign T101 = buffer_12;
assign T897 = T898 ? 2'h3 : 2'h0;
assign T898 = T98[5];
assign T102 = T104 & T899;
assign T899 = {T900, T103};
assign T103 = ~ T99;
assign T900 = T901 ? 2'h3 : 2'h0;
assign T901 = T103[5];
assign T104 = T109 | T902;
assign T902 = {T904, T105};
assign T105 = T903 & T106;
assign T106 = 5'h8;
assign T903 = T107 ? 5'h1f : 5'h0;
assign T107 = T108;
assign T108 = buffer_11;
assign T904 = T905 ? 3'h7 : 3'h0;
assign T905 = T105[4];
assign T109 = T111 & T906;
assign T906 = {T907, T110};
assign T110 = ~ T106;
assign T907 = T908 ? 3'h7 : 3'h0;
assign T908 = T110[4];
assign T111 = T116 | T909;
assign T909 = {T911, T112};
assign T112 = T910 & T113;
assign T113 = 4'h4;
assign T910 = T114 ? 4'hf : 4'h0;
assign T114 = T115;
assign T115 = buffer_10;
assign T911 = T912 ? 4'hf : 4'h0;
assign T912 = T112[3];
assign T116 = T118 & T913;
assign T913 = {T914, T117};
assign T117 = ~ T113;
assign T914 = T915 ? 4'hf : 4'h0;
assign T915 = T117[3];
assign T118 = T123 | T916;
assign T916 = {T918, T119};
assign T119 = T917 & T120;
assign T120 = 3'h2;
assign T917 = T121 ? 3'h7 : 3'h0;
assign T121 = T122;
assign T122 = buffer_9;
assign T918 = T919 ? 5'h1f : 5'h0;
assign T919 = T119[2];
assign T123 = T125 & T920;
assign T920 = {T921, T124};
assign T124 = ~ T120;
assign T921 = T922 ? 5'h1f : 5'h0;
assign T922 = T124[2];
assign T125 = T130 | T923;
assign T923 = {T925, T126};
assign T126 = T924 & T127;
assign T127 = 2'h1;
assign T924 = T128 ? 2'h3 : 2'h0;
assign T128 = T129;
assign T129 = buffer_8;
assign T925 = T926 ? 6'h3f : 6'h0;
assign T926 = T126[1];
assign T130 = 8'h0 & T927;
assign T927 = {T928, T131};
assign T131 = ~ T127;
assign T928 = T929 ? 6'h3f : 6'h0;
assign T929 = T131[1];
assign bufferByte_2 = T930;
assign T930 = T132[7:0];
assign T132 = T137 | T133;
assign T133 = T931 & T134;
assign T134 = 9'h80;
assign T931 = T135 ? 9'h1ff : 9'h0;
assign T135 = T136;
assign T136 = buffer_23;
assign T137 = T932 & T138;
assign T138 = ~ T134;
assign T932 = {1'h0, T139};
assign T139 = T144 | T140;
assign T140 = T933 & T141;
assign T141 = 8'h40;
assign T933 = T142 ? 8'hff : 8'h0;
assign T142 = T143;
assign T143 = buffer_22;
assign T144 = T146 & T145;
assign T145 = ~ T141;
assign T146 = T151 | T934;
assign T934 = {T936, T147};
assign T147 = T935 & T148;
assign T148 = 7'h20;
assign T935 = T149 ? 7'h7f : 7'h0;
assign T149 = T150;
assign T150 = buffer_21;
assign T936 = T147[6];
assign T151 = T153 & T937;
assign T937 = {T938, T152};
assign T152 = ~ T148;
assign T938 = T152[6];
assign T153 = T158 | T939;
assign T939 = {T941, T154};
assign T154 = T940 & T155;
assign T155 = 6'h10;
assign T940 = T156 ? 6'h3f : 6'h0;
assign T156 = T157;
assign T157 = buffer_20;
assign T941 = T942 ? 2'h3 : 2'h0;
assign T942 = T154[5];
assign T158 = T160 & T943;
assign T943 = {T944, T159};
assign T159 = ~ T155;
assign T944 = T945 ? 2'h3 : 2'h0;
assign T945 = T159[5];
assign T160 = T165 | T946;
assign T946 = {T948, T161};
assign T161 = T947 & T162;
assign T162 = 5'h8;
assign T947 = T163 ? 5'h1f : 5'h0;
assign T163 = T164;
assign T164 = buffer_19;
assign T948 = T949 ? 3'h7 : 3'h0;
assign T949 = T161[4];
assign T165 = T167 & T950;
assign T950 = {T951, T166};
assign T166 = ~ T162;
assign T951 = T952 ? 3'h7 : 3'h0;
assign T952 = T166[4];
assign T167 = T172 | T953;
assign T953 = {T955, T168};
assign T168 = T954 & T169;
assign T169 = 4'h4;
assign T954 = T170 ? 4'hf : 4'h0;
assign T170 = T171;
assign T171 = buffer_18;
assign T955 = T956 ? 4'hf : 4'h0;
assign T956 = T168[3];
assign T172 = T174 & T957;
assign T957 = {T958, T173};
assign T173 = ~ T169;
assign T958 = T959 ? 4'hf : 4'h0;
assign T959 = T173[3];
assign T174 = T179 | T960;
assign T960 = {T962, T175};
assign T175 = T961 & T176;
assign T176 = 3'h2;
assign T961 = T177 ? 3'h7 : 3'h0;
assign T177 = T178;
assign T178 = buffer_17;
assign T962 = T963 ? 5'h1f : 5'h0;
assign T963 = T175[2];
assign T179 = T181 & T964;
assign T964 = {T965, T180};
assign T180 = ~ T176;
assign T965 = T966 ? 5'h1f : 5'h0;
assign T966 = T180[2];
assign T181 = T186 | T967;
assign T967 = {T969, T182};
assign T182 = T968 & T183;
assign T183 = 2'h1;
assign T968 = T184 ? 2'h3 : 2'h0;
assign T184 = T185;
assign T185 = buffer_16;
assign T969 = T970 ? 6'h3f : 6'h0;
assign T970 = T182[1];
assign T186 = 8'h0 & T971;
assign T971 = {T972, T187};
assign T187 = ~ T183;
assign T972 = T973 ? 6'h3f : 6'h0;
assign T973 = T187[1];
assign bufferByte_3 = T974;
assign T974 = T188[7:0];
assign T188 = T193 | T189;
assign T189 = T975 & T190;
assign T190 = 9'h80;
assign T975 = T191 ? 9'h1ff : 9'h0;
assign T191 = T192;
assign T192 = buffer_31;
assign T193 = T976 & T194;
assign T194 = ~ T190;
assign T976 = {1'h0, T195};
assign T195 = T200 | T196;
assign T196 = T977 & T197;
assign T197 = 8'h40;
assign T977 = T198 ? 8'hff : 8'h0;
assign T198 = T199;
assign T199 = buffer_30;
assign T200 = T202 & T201;
assign T201 = ~ T197;
assign T202 = T207 | T978;
assign T978 = {T980, T203};
assign T203 = T979 & T204;
assign T204 = 7'h20;
assign T979 = T205 ? 7'h7f : 7'h0;
assign T205 = T206;
assign T206 = buffer_29;
assign T980 = T203[6];
assign T207 = T209 & T981;
assign T981 = {T982, T208};
assign T208 = ~ T204;
assign T982 = T208[6];
assign T209 = T214 | T983;
assign T983 = {T985, T210};
assign T210 = T984 & T211;
assign T211 = 6'h10;
assign T984 = T212 ? 6'h3f : 6'h0;
assign T212 = T213;
assign T213 = buffer_28;
assign T985 = T986 ? 2'h3 : 2'h0;
assign T986 = T210[5];
assign T214 = T216 & T987;
assign T987 = {T988, T215};
assign T215 = ~ T211;
assign T988 = T989 ? 2'h3 : 2'h0;
assign T989 = T215[5];
assign T216 = T221 | T990;
assign T990 = {T992, T217};
assign T217 = T991 & T218;
assign T218 = 5'h8;
assign T991 = T219 ? 5'h1f : 5'h0;
assign T219 = T220;
assign T220 = buffer_27;
assign T992 = T993 ? 3'h7 : 3'h0;
assign T993 = T217[4];
assign T221 = T223 & T994;
assign T994 = {T995, T222};
assign T222 = ~ T218;
assign T995 = T996 ? 3'h7 : 3'h0;
assign T996 = T222[4];
assign T223 = T228 | T997;
assign T997 = {T999, T224};
assign T224 = T998 & T225;
assign T225 = 4'h4;
assign T998 = T226 ? 4'hf : 4'h0;
assign T226 = T227;
assign T227 = buffer_26;
assign T999 = T1000 ? 4'hf : 4'h0;
assign T1000 = T224[3];
assign T228 = T230 & T1001;
assign T1001 = {T1002, T229};
assign T229 = ~ T225;
assign T1002 = T1003 ? 4'hf : 4'h0;
assign T1003 = T229[3];
assign T230 = T235 | T1004;
assign T1004 = {T1006, T231};
assign T231 = T1005 & T232;
assign T232 = 3'h2;
assign T1005 = T233 ? 3'h7 : 3'h0;
assign T233 = T234;
assign T234 = buffer_25;
assign T1006 = T1007 ? 5'h1f : 5'h0;
assign T1007 = T231[2];
assign T235 = T237 & T1008;
assign T1008 = {T1009, T236};
assign T236 = ~ T232;
assign T1009 = T1010 ? 5'h1f : 5'h0;
assign T1010 = T236[2];
assign T237 = T242 | T1011;
assign T1011 = {T1013, T238};
assign T238 = T1012 & T239;
assign T239 = 2'h1;
assign T1012 = T240 ? 2'h3 : 2'h0;
assign T240 = T241;
assign T241 = buffer_24;
assign T1013 = T1014 ? 6'h3f : 6'h0;
assign T1014 = T238[1];
assign T242 = 8'h0 & T1015;
assign T1015 = {T1016, T243};
assign T243 = ~ T239;
assign T1016 = T1017 ? 6'h3f : 6'h0;
assign T1017 = T243[1];
assign bufferByte_4 = T1018;
assign T1018 = T244[7:0];
assign T244 = T249 | T245;
assign T245 = T1019 & T246;
assign T246 = 9'h80;
assign T1019 = T247 ? 9'h1ff : 9'h0;
assign T247 = T248;
assign T248 = buffer_39;
assign T249 = T1020 & T250;
assign T250 = ~ T246;
assign T1020 = {1'h0, T251};
assign T251 = T256 | T252;
assign T252 = T1021 & T253;
assign T253 = 8'h40;
assign T1021 = T254 ? 8'hff : 8'h0;
assign T254 = T255;
assign T255 = buffer_38;
assign T256 = T258 & T257;
assign T257 = ~ T253;
assign T258 = T263 | T1022;
assign T1022 = {T1024, T259};
assign T259 = T1023 & T260;
assign T260 = 7'h20;
assign T1023 = T261 ? 7'h7f : 7'h0;
assign T261 = T262;
assign T262 = buffer_37;
assign T1024 = T259[6];
assign T263 = T265 & T1025;
assign T1025 = {T1026, T264};
assign T264 = ~ T260;
assign T1026 = T264[6];
assign T265 = T270 | T1027;
assign T1027 = {T1029, T266};
assign T266 = T1028 & T267;
assign T267 = 6'h10;
assign T1028 = T268 ? 6'h3f : 6'h0;
assign T268 = T269;
assign T269 = buffer_36;
assign T1029 = T1030 ? 2'h3 : 2'h0;
assign T1030 = T266[5];
assign T270 = T272 & T1031;
assign T1031 = {T1032, T271};
assign T271 = ~ T267;
assign T1032 = T1033 ? 2'h3 : 2'h0;
assign T1033 = T271[5];
assign T272 = T277 | T1034;
assign T1034 = {T1036, T273};
assign T273 = T1035 & T274;
assign T274 = 5'h8;
assign T1035 = T275 ? 5'h1f : 5'h0;
assign T275 = T276;
assign T276 = buffer_35;
assign T1036 = T1037 ? 3'h7 : 3'h0;
assign T1037 = T273[4];
assign T277 = T279 & T1038;
assign T1038 = {T1039, T278};
assign T278 = ~ T274;
assign T1039 = T1040 ? 3'h7 : 3'h0;
assign T1040 = T278[4];
assign T279 = T284 | T1041;
assign T1041 = {T1043, T280};
assign T280 = T1042 & T281;
assign T281 = 4'h4;
assign T1042 = T282 ? 4'hf : 4'h0;
assign T282 = T283;
assign T283 = buffer_34;
assign T1043 = T1044 ? 4'hf : 4'h0;
assign T1044 = T280[3];
assign T284 = T286 & T1045;
assign T1045 = {T1046, T285};
assign T285 = ~ T281;
assign T1046 = T1047 ? 4'hf : 4'h0;
assign T1047 = T285[3];
assign T286 = T291 | T1048;
assign T1048 = {T1050, T287};
assign T287 = T1049 & T288;
assign T288 = 3'h2;
assign T1049 = T289 ? 3'h7 : 3'h0;
assign T289 = T290;
assign T290 = buffer_33;
assign T1050 = T1051 ? 5'h1f : 5'h0;
assign T1051 = T287[2];
assign T291 = T293 & T1052;
assign T1052 = {T1053, T292};
assign T292 = ~ T288;
assign T1053 = T1054 ? 5'h1f : 5'h0;
assign T1054 = T292[2];
assign T293 = T298 | T1055;
assign T1055 = {T1057, T294};
assign T294 = T1056 & T295;
assign T295 = 2'h1;
assign T1056 = T296 ? 2'h3 : 2'h0;
assign T296 = T297;
assign T297 = buffer_32;
assign T1057 = T1058 ? 6'h3f : 6'h0;
assign T1058 = T294[1];
assign T298 = 8'h0 & T1059;
assign T1059 = {T1060, T299};
assign T299 = ~ T295;
assign T1060 = T1061 ? 6'h3f : 6'h0;
assign T1061 = T299[1];
assign bufferByte_5 = T1062;
assign T1062 = T300[7:0];
assign T300 = T305 | T301;
assign T301 = T1063 & T302;
assign T302 = 9'h80;
assign T1063 = T303 ? 9'h1ff : 9'h0;
assign T303 = T304;
assign T304 = buffer_47;
assign T305 = T1064 & T306;
assign T306 = ~ T302;
assign T1064 = {1'h0, T307};
assign T307 = T312 | T308;
assign T308 = T1065 & T309;
assign T309 = 8'h40;
assign T1065 = T310 ? 8'hff : 8'h0;
assign T310 = T311;
assign T311 = buffer_46;
assign T312 = T314 & T313;
assign T313 = ~ T309;
assign T314 = T319 | T1066;
assign T1066 = {T1068, T315};
assign T315 = T1067 & T316;
assign T316 = 7'h20;
assign T1067 = T317 ? 7'h7f : 7'h0;
assign T317 = T318;
assign T318 = buffer_45;
assign T1068 = T315[6];
assign T319 = T321 & T1069;
assign T1069 = {T1070, T320};
assign T320 = ~ T316;
assign T1070 = T320[6];
assign T321 = T326 | T1071;
assign T1071 = {T1073, T322};
assign T322 = T1072 & T323;
assign T323 = 6'h10;
assign T1072 = T324 ? 6'h3f : 6'h0;
assign T324 = T325;
assign T325 = buffer_44;
assign T1073 = T1074 ? 2'h3 : 2'h0;
assign T1074 = T322[5];
assign T326 = T328 & T1075;
assign T1075 = {T1076, T327};
assign T327 = ~ T323;
assign T1076 = T1077 ? 2'h3 : 2'h0;
assign T1077 = T327[5];
assign T328 = T333 | T1078;
assign T1078 = {T1080, T329};
assign T329 = T1079 & T330;
assign T330 = 5'h8;
assign T1079 = T331 ? 5'h1f : 5'h0;
assign T331 = T332;
assign T332 = buffer_43;
assign T1080 = T1081 ? 3'h7 : 3'h0;
assign T1081 = T329[4];
assign T333 = T335 & T1082;
assign T1082 = {T1083, T334};
assign T334 = ~ T330;
assign T1083 = T1084 ? 3'h7 : 3'h0;
assign T1084 = T334[4];
assign T335 = T340 | T1085;
assign T1085 = {T1087, T336};
assign T336 = T1086 & T337;
assign T337 = 4'h4;
assign T1086 = T338 ? 4'hf : 4'h0;
assign T338 = T339;
assign T339 = buffer_42;
assign T1087 = T1088 ? 4'hf : 4'h0;
assign T1088 = T336[3];
assign T340 = T342 & T1089;
assign T1089 = {T1090, T341};
assign T341 = ~ T337;
assign T1090 = T1091 ? 4'hf : 4'h0;
assign T1091 = T341[3];
assign T342 = T347 | T1092;
assign T1092 = {T1094, T343};
assign T343 = T1093 & T344;
assign T344 = 3'h2;
assign T1093 = T345 ? 3'h7 : 3'h0;
assign T345 = T346;
assign T346 = buffer_41;
assign T1094 = T1095 ? 5'h1f : 5'h0;
assign T1095 = T343[2];
assign T347 = T349 & T1096;
assign T1096 = {T1097, T348};
assign T348 = ~ T344;
assign T1097 = T1098 ? 5'h1f : 5'h0;
assign T1098 = T348[2];
assign T349 = T354 | T1099;
assign T1099 = {T1101, T350};
assign T350 = T1100 & T351;
assign T351 = 2'h1;
assign T1100 = T352 ? 2'h3 : 2'h0;
assign T352 = T353;
assign T353 = buffer_40;
assign T1101 = T1102 ? 6'h3f : 6'h0;
assign T1102 = T350[1];
assign T354 = 8'h0 & T1103;
assign T1103 = {T1104, T355};
assign T355 = ~ T351;
assign T1104 = T1105 ? 6'h3f : 6'h0;
assign T1105 = T355[1];
assign bufferByte_6 = T1106;
assign T1106 = T356[7:0];
assign T356 = T361 | T357;
assign T357 = T1107 & T358;
assign T358 = 9'h80;
assign T1107 = T359 ? 9'h1ff : 9'h0;
assign T359 = T360;
assign T360 = buffer_55;
assign T361 = T1108 & T362;
assign T362 = ~ T358;
assign T1108 = {1'h0, T363};
assign T363 = T368 | T364;
assign T364 = T1109 & T365;
assign T365 = 8'h40;
assign T1109 = T366 ? 8'hff : 8'h0;
assign T366 = T367;
assign T367 = buffer_54;
assign T368 = T370 & T369;
assign T369 = ~ T365;
assign T370 = T375 | T1110;
assign T1110 = {T1112, T371};
assign T371 = T1111 & T372;
assign T372 = 7'h20;
assign T1111 = T373 ? 7'h7f : 7'h0;
assign T373 = T374;
assign T374 = buffer_53;
assign T1112 = T371[6];
assign T375 = T377 & T1113;
assign T1113 = {T1114, T376};
assign T376 = ~ T372;
assign T1114 = T376[6];
assign T377 = T382 | T1115;
assign T1115 = {T1117, T378};
assign T378 = T1116 & T379;
assign T379 = 6'h10;
assign T1116 = T380 ? 6'h3f : 6'h0;
assign T380 = T381;
assign T381 = buffer_52;
assign T1117 = T1118 ? 2'h3 : 2'h0;
assign T1118 = T378[5];
assign T382 = T384 & T1119;
assign T1119 = {T1120, T383};
assign T383 = ~ T379;
assign T1120 = T1121 ? 2'h3 : 2'h0;
assign T1121 = T383[5];
assign T384 = T389 | T1122;
assign T1122 = {T1124, T385};
assign T385 = T1123 & T386;
assign T386 = 5'h8;
assign T1123 = T387 ? 5'h1f : 5'h0;
assign T387 = T388;
assign T388 = buffer_51;
assign T1124 = T1125 ? 3'h7 : 3'h0;
assign T1125 = T385[4];
assign T389 = T391 & T1126;
assign T1126 = {T1127, T390};
assign T390 = ~ T386;
assign T1127 = T1128 ? 3'h7 : 3'h0;
assign T1128 = T390[4];
assign T391 = T396 | T1129;
assign T1129 = {T1131, T392};
assign T392 = T1130 & T393;
assign T393 = 4'h4;
assign T1130 = T394 ? 4'hf : 4'h0;
assign T394 = T395;
assign T395 = buffer_50;
assign T1131 = T1132 ? 4'hf : 4'h0;
assign T1132 = T392[3];
assign T396 = T398 & T1133;
assign T1133 = {T1134, T397};
assign T397 = ~ T393;
assign T1134 = T1135 ? 4'hf : 4'h0;
assign T1135 = T397[3];
assign T398 = T403 | T1136;
assign T1136 = {T1138, T399};
assign T399 = T1137 & T400;
assign T400 = 3'h2;
assign T1137 = T401 ? 3'h7 : 3'h0;
assign T401 = T402;
assign T402 = buffer_49;
assign T1138 = T1139 ? 5'h1f : 5'h0;
assign T1139 = T399[2];
assign T403 = T405 & T1140;
assign T1140 = {T1141, T404};
assign T404 = ~ T400;
assign T1141 = T1142 ? 5'h1f : 5'h0;
assign T1142 = T404[2];
assign T405 = T410 | T1143;
assign T1143 = {T1145, T406};
assign T406 = T1144 & T407;
assign T407 = 2'h1;
assign T1144 = T408 ? 2'h3 : 2'h0;
assign T408 = T409;
assign T409 = buffer_48;
assign T1145 = T1146 ? 6'h3f : 6'h0;
assign T1146 = T406[1];
assign T410 = 8'h0 & T1147;
assign T1147 = {T1148, T411};
assign T411 = ~ T407;
assign T1148 = T1149 ? 6'h3f : 6'h0;
assign T1149 = T411[1];
assign bufferByte_7 = T1150;
assign T1150 = T412[7:0];
assign T412 = T417 | T413;
assign T413 = T1151 & T414;
assign T414 = 9'h80;
assign T1151 = T415 ? 9'h1ff : 9'h0;
assign T415 = T416;
assign T416 = buffer_63;
assign T417 = T1152 & T418;
assign T418 = ~ T414;
assign T1152 = {1'h0, T419};
assign T419 = T424 | T420;
assign T420 = T1153 & T421;
assign T421 = 8'h40;
assign T1153 = T422 ? 8'hff : 8'h0;
assign T422 = T423;
assign T423 = buffer_62;
assign T424 = T426 & T425;
assign T425 = ~ T421;
assign T426 = T431 | T1154;
assign T1154 = {T1156, T427};
assign T427 = T1155 & T428;
assign T428 = 7'h20;
assign T1155 = T429 ? 7'h7f : 7'h0;
assign T429 = T430;
assign T430 = buffer_61;
assign T1156 = T427[6];
assign T431 = T433 & T1157;
assign T1157 = {T1158, T432};
assign T432 = ~ T428;
assign T1158 = T432[6];
assign T433 = T438 | T1159;
assign T1159 = {T1161, T434};
assign T434 = T1160 & T435;
assign T435 = 6'h10;
assign T1160 = T436 ? 6'h3f : 6'h0;
assign T436 = T437;
assign T437 = buffer_60;
assign T1161 = T1162 ? 2'h3 : 2'h0;
assign T1162 = T434[5];
assign T438 = T440 & T1163;
assign T1163 = {T1164, T439};
assign T439 = ~ T435;
assign T1164 = T1165 ? 2'h3 : 2'h0;
assign T1165 = T439[5];
assign T440 = T445 | T1166;
assign T1166 = {T1168, T441};
assign T441 = T1167 & T442;
assign T442 = 5'h8;
assign T1167 = T443 ? 5'h1f : 5'h0;
assign T443 = T444;
assign T444 = buffer_59;
assign T1168 = T1169 ? 3'h7 : 3'h0;
assign T1169 = T441[4];
assign T445 = T447 & T1170;
assign T1170 = {T1171, T446};
assign T446 = ~ T442;
assign T1171 = T1172 ? 3'h7 : 3'h0;
assign T1172 = T446[4];
assign T447 = T452 | T1173;
assign T1173 = {T1175, T448};
assign T448 = T1174 & T449;
assign T449 = 4'h4;
assign T1174 = T450 ? 4'hf : 4'h0;
assign T450 = T451;
assign T451 = buffer_58;
assign T1175 = T1176 ? 4'hf : 4'h0;
assign T1176 = T448[3];
assign T452 = T454 & T1177;
assign T1177 = {T1178, T453};
assign T453 = ~ T449;
assign T1178 = T1179 ? 4'hf : 4'h0;
assign T1179 = T453[3];
assign T454 = T459 | T1180;
assign T1180 = {T1182, T455};
assign T455 = T1181 & T456;
assign T456 = 3'h2;
assign T1181 = T457 ? 3'h7 : 3'h0;
assign T457 = T458;
assign T458 = buffer_57;
assign T1182 = T1183 ? 5'h1f : 5'h0;
assign T1183 = T455[2];
assign T459 = T461 & T1184;
assign T1184 = {T1185, T460};
assign T460 = ~ T456;
assign T1185 = T1186 ? 5'h1f : 5'h0;
assign T1186 = T460[2];
assign T461 = T466 | T1187;
assign T1187 = {T1189, T462};
assign T462 = T1188 & T463;
assign T463 = 2'h1;
assign T1188 = T464 ? 2'h3 : 2'h0;
assign T464 = T465;
assign T465 = buffer_56;
assign T1189 = T1190 ? 6'h3f : 6'h0;
assign T1190 = T462[1];
assign T466 = 8'h0 & T1191;
assign T1191 = {T1192, T467};
assign T467 = ~ T463;
assign T1192 = T1193 ? 6'h3f : 6'h0;
assign T1193 = T467[1];
assign flush = T468 | fifoDrain;
assign T468 = T469 & directOutputFifo_io_deq_valid;
assign T469 = 7'h63 <= buffCount;
assign T1194 = rst ? 7'h0 : T470;
assign T470 = flush ? 7'h0 : T471;
assign T471 = T473 ? T472 : buffCount;
assign T472 = buffCount + 7'h1;
assign T473 = outToBuffer_io_dataIn_ready & directOutputFifo_io_deq_valid;
assign vecDataOut_0 = T474;
assign T474 = userMod_io_dataOut_bits[0];
assign vecDataOut_1 = T475;
assign T475 = userMod_io_dataOut_bits[1];
assign vecDataOut_2 = T476;
assign T476 = userMod_io_dataOut_bits[2];
assign vecDataOut_3 = T477;
assign T477 = userMod_io_dataOut_bits[3];
assign vecDataOut_4 = T478;
assign T478 = userMod_io_dataOut_bits[4];
assign vecDataOut_5 = T479;
assign T479 = userMod_io_dataOut_bits[5];
assign vecDataOut_6 = T480;
assign T480 = userMod_io_dataOut_bits[6];
assign vecDataOut_7 = T481;
assign T481 = userMod_io_dataOut_bits[7];
assign T482 = stripper_io_out_data[7:0];
assign T483 = stripper_io_out_data[15:8];
assign T484 = stripper_io_out_data[23:16];
assign T485 = stripper_io_out_data[31:24];
assign T486 = stripper_io_out_data[39:32];
assign T487 = stripper_io_out_data[47:40];
assign T488 = stripper_io_out_data[55:48];
assign T489 = stripper_io_out_data[63:56];
assign T1195 = T490[127:0];
assign T490 = T528 | T1196;
assign T1196 = {1'h0, T491};
assign T491 = T492 << 7'h78;
assign T492 = T493 & 8'hff;
assign T493 = T494[127:120];
assign T494 = userMem[T1239];
assign T1197 = {112'h0, mem_w_en};
assign T1198 = T1236 | T1199;
assign T1199 = T1202 & T1200;
assign T1200 = {112'h0, T1201};
assign T1201 = ~ mem_w_en;
assign T1202 = T1203;
assign T1203 = {T1221, T1204};
assign T1204 = {T1214, T1205};
assign T1205 = {T1211, T1206};
assign T1206 = {T1210, T1207};
assign T1207 = T1208[7:0];
assign T1208 = userMem[T1209];
assign T1209 = mem_w_addr[6:0];
assign T1210 = T1208[15:8];
assign T1211 = {T1213, T1212};
assign T1212 = T1208[23:16];
assign T1213 = T1208[31:24];
assign T1214 = {T1218, T1215};
assign T1215 = {T1217, T1216};
assign T1216 = T1208[39:32];
assign T1217 = T1208[47:40];
assign T1218 = {T1220, T1219};
assign T1219 = T1208[55:48];
assign T1220 = T1208[63:56];
assign T1221 = {T1229, T1222};
assign T1222 = {T1226, T1223};
assign T1223 = {T1225, T1224};
assign T1224 = T1208[71:64];
assign T1225 = T1208[79:72];
assign T1226 = {T1228, T1227};
assign T1227 = T1208[87:80];
assign T1228 = T1208[95:88];
assign T1229 = {T1233, T1230};
assign T1230 = {T1232, T1231};
assign T1231 = T1208[103:96];
assign T1232 = T1208[111:104];
assign T1233 = {T1235, T1234};
assign T1234 = T1208[119:112];
assign T1235 = T1208[127:120];
assign T1236 = T496 & T1237;
assign T1237 = {112'h0, mem_w_en};
assign T496 = T497;
assign T497 = {T513, T498};
assign T498 = {T506, T499};
assign T499 = {T503, T500};
assign T500 = {memWData_1, memWData_0};
assign memWData_0 = T501;
assign T501 = mem_w_data[7:0];
assign memWData_1 = T502;
assign T502 = mem_w_data[15:8];
assign T503 = {memWData_3, memWData_2};
assign memWData_2 = T504;
assign T504 = mem_w_data[23:16];
assign memWData_3 = T505;
assign T505 = mem_w_data[31:24];
assign T506 = {T510, T507};
assign T507 = {memWData_5, memWData_4};
assign memWData_4 = T508;
assign T508 = mem_w_data[39:32];
assign memWData_5 = T509;
assign T509 = mem_w_data[47:40];
assign T510 = {memWData_7, memWData_6};
assign memWData_6 = T511;
assign T511 = mem_w_data[55:48];
assign memWData_7 = T512;
assign T512 = mem_w_data[63:56];
assign T513 = {T521, T514};
assign T514 = {T518, T515};
assign T515 = {memWData_9, memWData_8};
assign memWData_8 = T516;
assign T516 = mem_w_data[71:64];
assign memWData_9 = T517;
assign T517 = mem_w_data[79:72];
assign T518 = {memWData_11, memWData_10};
assign memWData_10 = T519;
assign T519 = mem_w_data[87:80];
assign memWData_11 = T520;
assign T520 = mem_w_data[95:88];
assign T521 = {T525, T522};
assign T522 = {memWData_13, memWData_12};
assign memWData_12 = T523;
assign T523 = mem_w_data[103:96];
assign memWData_13 = T524;
assign T524 = mem_w_data[111:104];
assign T525 = {memWData_15, memWData_14};
assign memWData_14 = T526;
assign T526 = mem_w_data[119:112];
assign memWData_15 = T527;
assign T527 = mem_w_data[127:120];
assign T1238 = mem_w_addr[6:0];
assign T1239 = userMod_io_memAddr[6:0];
assign T528 = T1240 & T529;
assign T529 = ~ T530;
assign T530 = 129'hff000000000000000000000000000000;
assign T1240 = {1'h0, T531};
assign T531 = T535 | T1241;
assign T1241 = {8'h0, T532};
assign T532 = T533 << 7'h70;
assign T533 = T534 & 8'hff;
assign T534 = T494[119:112];
assign T535 = T538 & T1242;
assign T1242 = {T1243, T536};
assign T536 = ~ T537;
assign T537 = 121'hff0000000000000000000000000000;
assign T1243 = T1244 ? 7'h7f : 7'h0;
assign T1244 = T536[120];
assign T538 = T542 | T1245;
assign T1245 = {16'h0, T539};
assign T539 = T540 << 7'h68;
assign T540 = T541 & 8'hff;
assign T541 = T494[111:104];
assign T542 = T545 & T1246;
assign T1246 = {T1247, T543};
assign T543 = ~ T544;
assign T544 = 113'hff00000000000000000000000000;
assign T1247 = T1248 ? 15'h7fff : 15'h0;
assign T1248 = T543[112];
assign T545 = T549 | T1249;
assign T1249 = {24'h0, T546};
assign T546 = T547 << 7'h60;
assign T547 = T548 & 8'hff;
assign T548 = T494[103:96];
assign T549 = T552 & T1250;
assign T1250 = {T1251, T550};
assign T550 = ~ T551;
assign T551 = 105'hff000000000000000000000000;
assign T1251 = T1252 ? 23'h7fffff : 23'h0;
assign T1252 = T550[104];
assign T552 = T556 | T1253;
assign T1253 = {32'h0, T553};
assign T553 = T554 << 7'h58;
assign T554 = T555 & 8'hff;
assign T555 = T494[95:88];
assign T556 = T559 & T1254;
assign T1254 = {T1255, T557};
assign T557 = ~ T558;
assign T558 = 97'hff0000000000000000000000;
assign T1255 = T1256 ? 31'h7fffffff : 31'h0;
assign T1256 = T557[96];
assign T559 = T563 | T1257;
assign T1257 = {40'h0, T560};
assign T560 = T561 << 7'h50;
assign T561 = T562 & 8'hff;
assign T562 = T494[87:80];
assign T563 = T566 & T1258;
assign T1258 = {T1259, T564};
assign T564 = ~ T565;
assign T565 = 89'hff00000000000000000000;
assign T1259 = T1260 ? 39'h7fffffffff : 39'h0;
assign T1260 = T564[88];
assign T566 = T570 | T1261;
assign T1261 = {48'h0, T567};
assign T567 = T568 << 7'h48;
assign T568 = T569 & 8'hff;
assign T569 = T494[79:72];
assign T570 = T573 & T1262;
assign T1262 = {T1263, T571};
assign T571 = ~ T572;
assign T572 = 81'hff000000000000000000;
assign T1263 = T1264 ? 47'h7fffffffffff : 47'h0;
assign T1264 = T571[80];
assign T573 = T577 | T1265;
assign T1265 = {56'h0, T574};
assign T574 = T575 << 7'h40;
assign T575 = T576 & 8'hff;
assign T576 = T494[71:64];
assign T577 = T580 & T1266;
assign T1266 = {T1267, T578};
assign T578 = ~ T579;
assign T579 = 73'hff0000000000000000;
assign T1267 = T1268 ? 55'h7fffffffffffff : 55'h0;
assign T1268 = T578[72];
assign T580 = T584 | T1269;
assign T1269 = {64'h0, T581};
assign T581 = T582 << 6'h38;
assign T582 = T583 & 8'hff;
assign T583 = T494[63:56];
assign T584 = T587 & T1270;
assign T1270 = {T1271, T585};
assign T585 = ~ T586;
assign T586 = 65'hff00000000000000;
assign T1271 = T1272 ? 63'h7fffffffffffffff : 63'h0;
assign T1272 = T585[64];
assign T587 = T591 | T1273;
assign T1273 = {72'h0, T588};
assign T588 = T589 << 6'h30;
assign T589 = T590 & 8'hff;
assign T590 = T494[55:48];
assign T591 = T594 & T1274;
assign T1274 = {T1275, T592};
assign T592 = ~ T593;
assign T593 = 57'hff000000000000;
assign T1275 = T1276 ? 71'h7fffffffffffffffff : 71'h0;
assign T1276 = T592[56];
assign T594 = T598 | T1277;
assign T1277 = {80'h0, T595};
assign T595 = T596 << 6'h28;
assign T596 = T597 & 8'hff;
assign T597 = T494[47:40];
assign T598 = T601 & T1278;
assign T1278 = {T1279, T599};
assign T599 = ~ T600;
assign T600 = 49'hff0000000000;
assign T1279 = T1280 ? 79'h7fffffffffffffffffff : 79'h0;
assign T1280 = T599[48];
assign T601 = T605 | T1281;
assign T1281 = {88'h0, T602};
assign T602 = T603 << 6'h20;
assign T603 = T604 & 8'hff;
assign T604 = T494[39:32];
assign T605 = T608 & T1282;
assign T1282 = {T1283, T606};
assign T606 = ~ T607;
assign T607 = 41'hff00000000;
assign T1283 = T1284 ? 87'h7fffffffffffffffffffff : 87'h0;
assign T1284 = T606[40];
assign T608 = T612 | T1285;
assign T1285 = {96'h0, T609};
assign T609 = T610 << 5'h18;
assign T610 = T611 & 8'hff;
assign T611 = T494[31:24];
assign T612 = T615 & T1286;
assign T1286 = {T1287, T613};
assign T613 = ~ T614;
assign T614 = 33'hff000000;
assign T1287 = T1288 ? 95'h7fffffffffffffffffffffff : 95'h0;
assign T1288 = T613[32];
assign T615 = T619 | T1289;
assign T1289 = {104'h0, T616};
assign T616 = T617 << 5'h10;
assign T617 = T618 & 8'hff;
assign T618 = T494[23:16];
assign T619 = T622 & T1290;
assign T1290 = {T1291, T620};
assign T620 = ~ T621;
assign T621 = 25'hff0000;
assign T1291 = T1292 ? 103'h7fffffffffffffffffffffffff : 103'h0;
assign T1292 = T620[24];
assign T622 = T626 | T1293;
assign T1293 = {112'h0, T623};
assign T623 = T624 << 4'h8;
assign T624 = T625 & 8'hff;
assign T625 = T494[15:8];
assign T626 = T629 & T1294;
assign T1294 = {T1295, T627};
assign T627 = ~ T628;
assign T628 = 17'hff00;
assign T1295 = T1296 ? 111'h7fffffffffffffffffffffffffff : 111'h0;
assign T1296 = T627[16];
assign T629 = T633 | T1297;
assign T1297 = {120'h0, T630};
assign T630 = T631 << 1'h0;
assign T631 = T632 & 8'hff;
assign T632 = T494[7:0];
assign T633 = 128'h0 & T1298;
assign T1298 = {T1299, T634};
assign T634 = ~ T635;
assign T635 = 9'hff;
assign T1299 = T1300 ? 119'h7fffffffffffffffffffffffffffff : 119'h0;
assign T1300 = T634[8];
assign T1301 = rst ? T636 : T637;
assign T637 = T638 ? reg_w_data : regIntR_0;
assign T638 = reg_w_en & T639;
assign T639 = T5[0];
assign T1302 = rst ? T640 : T641;
assign T641 = T642 ? reg_w_data : regIntR_1;
assign T642 = reg_w_en & T643;
assign T643 = T5[1];
assign T1303 = rst ? T644 : T645;
assign T645 = T646 ? reg_w_data : regIntR_2;
assign T646 = reg_w_en & T647;
assign T647 = T5[2];
assign T1304 = rst ? T648 : T649;
assign T649 = T650 ? reg_w_data : regIntR_3;
assign T650 = reg_w_en & T651;
assign T651 = T5[3];
assign T1305 = rst ? T652 : T653;
assign T653 = T654 ? reg_w_data : regIntR_4;
assign T654 = reg_w_en & T655;
assign T655 = T5[4];
assign T1306 = rst ? T656 : T657;
assign T657 = T658 ? reg_w_data : regIntR_5;
assign T658 = reg_w_en & T659;
assign T659 = T5[5];
assign T1307 = rst ? T660 : T661;
assign T661 = T662 ? reg_w_data : regIntR_6;
assign T662 = reg_w_en & T663;
assign T663 = T5[6];
assign T1308 = rst ? T664 : T665;
assign T665 = T666 ? reg_w_data : regIntR_7;
assign T666 = reg_w_en & T667;
assign T667 = T5[7];
assign T1309 = rst ? T668 : T669;
assign T669 = T670 ? reg_w_data : regIntR_8;
assign T670 = reg_w_en & T671;
assign T671 = T5[8];
assign T1310 = rst ? T672 : T673;
assign T673 = T674 ? reg_w_data : regIntR_9;
assign T674 = reg_w_en & T675;
assign T675 = T5[9];
assign T1311 = rst ? T676 : T677;
assign T677 = T678 ? reg_w_data : regIntR_10;
assign T678 = reg_w_en & T679;
assign T679 = T5[10];
assign T1312 = rst ? T680 : T681;
assign T681 = T682 ? reg_w_data : regIntR_11;
assign T682 = reg_w_en & T683;
assign T683 = T5[11];
assign T1313 = rst ? T684 : T685;
assign T685 = T686 ? reg_w_data : regIntR_12;
assign T686 = reg_w_en & T687;
assign T687 = T5[12];
assign T1314 = rst ? T688 : T689;
assign T689 = T690 ? reg_w_data : regIntR_13;
assign T690 = reg_w_en & T691;
assign T691 = T5[13];
assign T1315 = rst ? T692 : T693;
assign T693 = T694 ? reg_w_data : regIntR_14;
assign T694 = reg_w_en & T695;
assign T695 = T5[14];
assign rx3_buffer_host = 6'h0;
assign rx3_match_host = 8'h0;
assign rx3_timestamp_host = rx3_timestamp_usr;
assign rx3_crc_fail_host = rx3_crc_fail_usr;
assign rx3_pkt_drop_host = rx3_pkt_drop_usr;
assign rx3_err_host = rx3_err_usr;
assign rx3_vld_host = rx3_vld_usr;
assign rx3_len_host = rx3_len_usr;
assign rx3_eof_host = rx3_eof_usr;
assign rx3_sof_host = rx3_sof_usr;
assign rx3_data_host = rx3_data_usr;
assign tx3_ack_host = tx3_ack_usr;
assign tx3_vld_usr = tx3_vld_host;
assign tx3_len_usr = tx3_len_host;
assign tx3_eof_usr = tx3_eof_host;
assign tx3_sof_usr = tx3_sof_host;
assign tx3_data_usr = tx3_data_host;
assign rx2_buffer_host = 6'h0;
assign rx2_match_host = 8'h0;
assign rx2_timestamp_host = rx2_timestamp_usr;
assign rx2_crc_fail_host = rx2_crc_fail_usr;
assign rx2_pkt_drop_host = rx2_pkt_drop_usr;
assign rx2_err_host = rx2_err_usr;
assign rx2_vld_host = rx2_vld_usr;
assign rx2_len_host = rx2_len_usr;
assign rx2_eof_host = rx2_eof_usr;
assign rx2_sof_host = rx2_sof_usr;
assign rx2_data_host = rx2_data_usr;
assign tx2_ack_host = tx2_ack_usr;
assign tx2_vld_usr = tx2_vld_host;
assign tx2_len_usr = tx2_len_host;
assign tx2_eof_usr = tx2_eof_host;
assign tx2_sof_usr = tx2_sof_host;
assign tx2_data_usr = tx2_data_host;
assign rx1_buffer_host = 6'h0;
assign rx1_match_host = 8'h0;
assign rx1_timestamp_host = rx1_timestamp_usr;
assign rx1_crc_fail_host = rx1_crc_fail_usr;
assign rx1_pkt_drop_host = rx1_pkt_drop_usr;
assign rx1_err_host = rx1_err_usr;
assign rx1_vld_host = rx1_vld_usr;
assign rx1_len_host = rx1_len_usr;
assign rx1_eof_host = rx1_eof_usr;
assign rx1_sof_host = rx1_sof_usr;
assign rx1_data_host = rx1_data_usr;
assign tx1_ack_host = tx1_ack_usr;
assign tx1_vld_usr = T696;
assign T696 = fifoTxOut_io_deq_valid & sending;
assign tx1_len_usr = len;
assign len = T697;
assign T697 = eof ? 3'h4 : 3'h0;
assign tx1_eof_usr = T698;
assign T698 = eof & tx1_vld_usr;
assign tx1_sof_usr = T699;
assign T699 = sof & tx1_vld_usr;
assign sof = segmentCounter == 4'h0;
assign tx1_data_usr = tx1Output;
assign tx1Output = T1316;
assign T1316 = T700[63:0];
assign T700 = T703 | T1317;
assign T1317 = {1'h0, T701};
assign T701 = T702 << 6'h38;
assign T702 = fifoTxOut_io_deq_bits_7 & 8'hff;
assign T703 = T1318 & T704;
assign T704 = ~ T705;
assign T705 = 65'hff00000000000000;
assign T1318 = {1'h0, T706};
assign T706 = T709 | T1319;
assign T1319 = {8'h0, T707};
assign T707 = T708 << 6'h30;
assign T708 = fifoTxOut_io_deq_bits_6 & 8'hff;
assign T709 = T712 & T1320;
assign T1320 = {T1321, T710};
assign T710 = ~ T711;
assign T711 = 57'hff000000000000;
assign T1321 = T1322 ? 7'h7f : 7'h0;
assign T1322 = T710[56];
assign T712 = T715 | T1323;
assign T1323 = {16'h0, T713};
assign T713 = T714 << 6'h28;
assign T714 = fifoTxOut_io_deq_bits_5 & 8'hff;
assign T715 = T718 & T1324;
assign T1324 = {T1325, T716};
assign T716 = ~ T717;
assign T717 = 49'hff0000000000;
assign T1325 = T1326 ? 15'h7fff : 15'h0;
assign T1326 = T716[48];
assign T718 = T721 | T1327;
assign T1327 = {24'h0, T719};
assign T719 = T720 << 6'h20;
assign T720 = fifoTxOut_io_deq_bits_4 & 8'hff;
assign T721 = T724 & T1328;
assign T1328 = {T1329, T722};
assign T722 = ~ T723;
assign T723 = 41'hff00000000;
assign T1329 = T1330 ? 23'h7fffff : 23'h0;
assign T1330 = T722[40];
assign T724 = T727 | T1331;
assign T1331 = {32'h0, T725};
assign T725 = T726 << 5'h18;
assign T726 = fifoTxOut_io_deq_bits_3 & 8'hff;
assign T727 = T730 & T1332;
assign T1332 = {T1333, T728};
assign T728 = ~ T729;
assign T729 = 33'hff000000;
assign T1333 = T1334 ? 31'h7fffffff : 31'h0;
assign T1334 = T728[32];
assign T730 = T733 | T1335;
assign T1335 = {40'h0, T731};
assign T731 = T732 << 5'h10;
assign T732 = fifoTxOut_io_deq_bits_2 & 8'hff;
assign T733 = T736 & T1336;
assign T1336 = {T1337, T734};
assign T734 = ~ T735;
assign T735 = 25'hff0000;
assign T1337 = T1338 ? 39'h7fffffffff : 39'h0;
assign T1338 = T734[24];
assign T736 = T739 | T1339;
assign T1339 = {48'h0, T737};
assign T737 = T738 << 4'h8;
assign T738 = fifoTxOut_io_deq_bits_1 & 8'hff;
assign T739 = T742 & T1340;
assign T1340 = {T1341, T740};
assign T740 = ~ T741;
assign T741 = 17'hff00;
assign T1341 = T1342 ? 47'h7fffffffffff : 47'h0;
assign T1342 = T740[16];
assign T742 = T745 | T1343;
assign T1343 = {56'h0, T743};
assign T743 = T744 << 1'h0;
assign T744 = fifoTxOut_io_deq_bits_0 & 8'hff;
assign T745 = 64'h0 & T1344;
assign T1344 = {T1345, T746};
assign T746 = ~ T747;
assign T747 = 9'hff;
assign T1345 = T1346 ? 55'h7fffffffffffff : 55'h0;
assign T1346 = T746[8];
assign rx0_buffer_host = 6'h0;
assign rx0_match_host = 8'h0;
assign rx0_timestamp_host = rx0_timestamp_usr;
assign rx0_crc_fail_host = rx0_crc_fail_usr;
assign rx0_pkt_drop_host = rx0_pkt_drop_usr;
assign rx0_err_host = rx0_err_usr;
assign rx0_vld_host = rx0_vld_usr;
assign rx0_len_host = rx0_len_usr;
assign rx0_eof_host = rx0_eof_usr;
assign rx0_sof_host = rx0_sof_usr;
assign rx0_data_host = rx0_data_usr;
assign tx0_ack_host = tx0_ack_usr;
assign tx0_vld_usr = tx0_vld_host;
assign tx0_len_usr = tx0_len_host;
assign tx0_eof_usr = tx0_eof_host;
assign tx0_sof_usr = tx0_sof_host;
assign tx0_data_usr = tx0_data_host;
assign reg_r_data = T748;
assign T748 = T835 ? T780 : T749;
assign T749 = T779 ? T765 : T750;
assign T750 = T764 ? T758 : T751;
assign T751 = T756 ? regIntW_1 : regIntW_0;
assign T1347 = rst ? T752 : T753;
assign T753 = userMod_io_regOutEn ? userMod_io_regOut_0 : regIntW_0;
assign T1348 = rst ? T754 : T755;
assign T755 = userMod_io_regOutEn ? userMod_io_regOut_1 : regIntW_1;
assign T756 = T757[0];
assign T757 = T1349;
assign T1349 = reg_r_addr[3:0];
assign T758 = T763 ? regIntW_3 : regIntW_2;
assign T1350 = rst ? T759 : T760;
assign T760 = userMod_io_regOutEn ? userMod_io_regOut_2 : regIntW_2;
assign T1351 = rst ? T761 : T762;
assign T762 = userMod_io_regOutEn ? userMod_io_regOut_3 : regIntW_3;
assign T763 = T757[0];
assign T764 = T757[1];
assign T765 = T778 ? T772 : T766;
assign T766 = T771 ? regIntW_5 : regIntW_4;
assign T1352 = rst ? T767 : T768;
assign T768 = userMod_io_regOutEn ? userMod_io_regOut_4 : regIntW_4;
assign T1353 = rst ? T769 : T770;
assign T770 = userMod_io_regOutEn ? userMod_io_regOut_5 : regIntW_5;
assign T771 = T757[0];
assign T772 = T777 ? regIntW_7 : regIntW_6;
assign T1354 = rst ? T773 : T774;
assign T774 = userMod_io_regOutEn ? userMod_io_regOut_6 : regIntW_6;
assign T1355 = rst ? T775 : T776;
assign T776 = userMod_io_regOutEn ? userMod_io_regOut_7 : regIntW_7;
assign T777 = T757[0];
assign T778 = T757[1];
assign T779 = T757[2];
assign T780 = T834 ? T795 : T781;
assign T781 = T794 ? T788 : T782;
assign T782 = T787 ? regIntW_9 : regIntW_8;
assign T1356 = rst ? T783 : T784;
assign T784 = userMod_io_regOutEn ? userMod_io_regOut_8 : regIntW_8;
assign T1357 = rst ? T785 : T786;
assign T786 = userMod_io_regOutEn ? userMod_io_regOut_9 : regIntW_9;
assign T787 = T757[0];
assign T788 = T793 ? regIntW_11 : regIntW_10;
assign T1358 = rst ? T789 : T790;
assign T790 = userMod_io_regOutEn ? userMod_io_regOut_10 : regIntW_10;
assign T1359 = rst ? T791 : T792;
assign T792 = userMod_io_regOutEn ? userMod_io_regOut_11 : regIntW_11;
assign T793 = T757[0];
assign T794 = T757[1];
assign T795 = T833 ? T802 : T796;
assign T796 = T801 ? regIntW_13 : regIntW_12;
assign T1360 = rst ? T797 : T798;
assign T798 = userMod_io_regOutEn ? userMod_io_regOut_12 : regIntW_12;
assign T1361 = rst ? T799 : T800;
assign T800 = userMod_io_regOutEn ? userMod_io_regOut_13 : regIntW_13;
assign T801 = T757[0];
assign T802 = T832 ? regIntW_15 : regIntW_14;
assign T1362 = rst ? T803 : T804;
assign T804 = userMod_io_regOutEn ? userMod_io_regOut_14 : regIntW_14;
assign T1363 = rst ? T805 : T1364;
assign T1364 = {9'h0, T806};
assign T806 = {T830, error};
assign error = T807;
assign T807 = {T810, userErr};
assign T1365 = rst ? 1'h0 : T808;
assign T808 = errRst ? 1'h0 : T809;
assign T809 = userErr | userMod_io_error;
assign errRst = controlReg[0];
assign T810 = {T814, dirOutFull};
assign T1366 = rst ? 1'h0 : T811;
assign T811 = errRst ? 1'h0 : T812;
assign T812 = dirOutFull | T813;
assign T813 = directOutputFifo_io_enq_ready ^ 1'h1;
assign T814 = {T818, txFifoFull};
assign T1367 = rst ? 1'h0 : T815;
assign T815 = errRst ? 1'h0 : T816;
assign T816 = txFifoFull | T817;
assign T817 = fifoTxOut_io_enq_ready ^ 1'h1;
assign T818 = {T822, fifoFull};
assign T1368 = rst ? 1'h0 : T819;
assign T819 = errRst ? 1'h0 : T820;
assign T820 = fifoFull | T821;
assign T821 = fifo_io_enq_ready ^ 1'h1;
assign T822 = {T825, crcFail};
assign T1369 = rst ? 1'h0 : T823;
assign T823 = errRst ? 1'h0 : T824;
assign T824 = crcFail | rx1_crc_fail_usr;
assign T825 = {rx1Err, pktDrop};
assign T1370 = rst ? 1'h0 : T826;
assign T826 = errRst ? 1'h0 : T827;
assign T827 = pktDrop | rx1_pkt_drop_usr;
assign T1371 = rst ? 1'h0 : T828;
assign T828 = errRst ? 1'h0 : T829;
assign T829 = rx1Err | rx1_err_usr;
assign T830 = {T831, segmentCounter};
assign T831 = {directOutputFifo_io_count, fifoTxOut_io_count};
assign T832 = T757[0];
assign T833 = T757[1];
assign T834 = T757[2];
assign T835 = T757[3];
SimpleAdderSuite_SimpleAdder_1 userMod(.clk(clk), .reset(T836),
.io_dataIn_ready( userMod_io_dataIn_ready ),
.io_dataIn_valid( fifo_io_deq_valid ),
.io_dataIn_bits_7( fifo_io_deq_bits_7 ),
.io_dataIn_bits_6( fifo_io_deq_bits_6 ),
.io_dataIn_bits_5( fifo_io_deq_bits_5 ),
.io_dataIn_bits_4( fifo_io_deq_bits_4 ),
.io_dataIn_bits_3( fifo_io_deq_bits_3 ),
.io_dataIn_bits_2( fifo_io_deq_bits_2 ),
.io_dataIn_bits_1( fifo_io_deq_bits_1 ),
.io_dataIn_bits_0( fifo_io_deq_bits_0 ),
.io_regIn_14( regIntR_14 ),
.io_regIn_13( regIntR_13 ),
.io_regIn_12( regIntR_12 ),
.io_regIn_11( regIntR_11 ),
.io_regIn_10( regIntR_10 ),
.io_regIn_9( regIntR_9 ),
.io_regIn_8( regIntR_8 ),
.io_regIn_7( regIntR_7 ),
.io_regIn_6( regIntR_6 ),
.io_regIn_5( regIntR_5 ),
.io_regIn_4( regIntR_4 ),
.io_regIn_3( regIntR_3 ),
.io_regIn_2( regIntR_2 ),
.io_regIn_1( regIntR_1 ),
.io_regIn_0( regIntR_0 ),
.io_regOut_14( userMod_io_regOut_14 ),
.io_regOut_13( userMod_io_regOut_13 ),
.io_regOut_12( userMod_io_regOut_12 ),
.io_regOut_11( userMod_io_regOut_11 ),
.io_regOut_10( userMod_io_regOut_10 ),
.io_regOut_9( userMod_io_regOut_9 ),
.io_regOut_8( userMod_io_regOut_8 ),
.io_regOut_7( userMod_io_regOut_7 ),
.io_regOut_6( userMod_io_regOut_6 ),
.io_regOut_5( userMod_io_regOut_5 ),
.io_regOut_4( userMod_io_regOut_4 ),
.io_regOut_3( userMod_io_regOut_3 ),
.io_regOut_2( userMod_io_regOut_2 ),
.io_regOut_1( userMod_io_regOut_1 ),
.io_regOut_0( userMod_io_regOut_0 ),
.io_regOutEn( userMod_io_regOutEn ),
.io_memAddr( userMod_io_memAddr ),
.io_memData( T1195 ),
.io_error( userMod_io_error ),
.io_dataOut_ready( directOutputFifo_io_enq_ready ),
.io_dataOut_valid( userMod_io_dataOut_valid ),
.io_dataOut_bits( userMod_io_dataOut_bits )
);
StripCrc stripper(.clk(clk), .reset(rst),
.io_in_data( rx1_data_usr ),
.io_in_sof( rx1_sof_usr ),
.io_in_eof( rx1_eof_usr ),
.io_in_len( rx1_len_usr ),
.io_in_vld( rx1_vld_usr ),
.io_out_data( stripper_io_out_data ),
//.io_out_sof( )
//.io_out_eof( )
.io_out_len( stripper_io_out_len ),
.io_out_vld( stripper_io_out_vld )
);
DataCombiner combiner(.clk(clk), .reset(rst),
.io_dataIn_7( T489 ),
.io_dataIn_6( T488 ),
.io_dataIn_5( T487 ),
.io_dataIn_4( T486 ),
.io_dataIn_3( T485 ),
.io_dataIn_2( T484 ),
.io_dataIn_1( T483 ),
.io_dataIn_0( T482 ),
.io_vld( stripper_io_out_vld ),
.io_len( stripper_io_out_len ),
.io_dataOut_7( combiner_io_dataOut_7 ),
.io_dataOut_6( combiner_io_dataOut_6 ),
.io_dataOut_5( combiner_io_dataOut_5 ),
.io_dataOut_4( combiner_io_dataOut_4 ),
.io_dataOut_3( combiner_io_dataOut_3 ),
.io_dataOut_2( combiner_io_dataOut_2 ),
.io_dataOut_1( combiner_io_dataOut_1 ),
.io_dataOut_0( combiner_io_dataOut_0 ),
.io_vldOut( combiner_io_vldOut )
);
Queue_0 fifo(.clk(clk), .reset(rst),
.io_enq_ready( fifo_io_enq_ready ),
.io_enq_valid( combiner_io_vldOut ),
.io_enq_bits_7( combiner_io_dataOut_7 ),
.io_enq_bits_6( combiner_io_dataOut_6 ),
.io_enq_bits_5( combiner_io_dataOut_5 ),
.io_enq_bits_4( combiner_io_dataOut_4 ),
.io_enq_bits_3( combiner_io_dataOut_3 ),
.io_enq_bits_2( combiner_io_dataOut_2 ),
.io_enq_bits_1( combiner_io_dataOut_1 ),
.io_enq_bits_0( combiner_io_dataOut_0 ),
.io_deq_ready( userMod_io_dataIn_ready ),
.io_deq_valid( fifo_io_deq_valid ),
.io_deq_bits_7( fifo_io_deq_bits_7 ),
.io_deq_bits_6( fifo_io_deq_bits_6 ),
.io_deq_bits_5( fifo_io_deq_bits_5 ),
.io_deq_bits_4( fifo_io_deq_bits_4 ),
.io_deq_bits_3( fifo_io_deq_bits_3 ),
.io_deq_bits_2( fifo_io_deq_bits_2 ),
.io_deq_bits_1( fifo_io_deq_bits_1 ),
.io_deq_bits_0( fifo_io_deq_bits_0 )
//.io_count( )
);
Queue_1 directOutputFifo(.clk(clk), .reset(rst),
.io_enq_ready( directOutputFifo_io_enq_ready ),
.io_enq_valid( userMod_io_dataOut_valid ),
.io_enq_bits_7( vecDataOut_7 ),
.io_enq_bits_6( vecDataOut_6 ),
.io_enq_bits_5( vecDataOut_5 ),
.io_enq_bits_4( vecDataOut_4 ),
.io_enq_bits_3( vecDataOut_3 ),
.io_enq_bits_2( vecDataOut_2 ),
.io_enq_bits_1( vecDataOut_1 ),
.io_enq_bits_0( vecDataOut_0 ),
.io_deq_ready( outToBuffer_io_dataIn_ready ),
.io_deq_valid( directOutputFifo_io_deq_valid ),
.io_deq_bits_7( directOutputFifo_io_deq_bits_7 ),
.io_deq_bits_6( directOutputFifo_io_deq_bits_6 ),
.io_deq_bits_5( directOutputFifo_io_deq_bits_5 ),
.io_deq_bits_4( directOutputFifo_io_deq_bits_4 ),
.io_deq_bits_3( directOutputFifo_io_deq_bits_3 ),
.io_deq_bits_2( directOutputFifo_io_deq_bits_2 ),
.io_deq_bits_1( directOutputFifo_io_deq_bits_1 ),
.io_deq_bits_0( directOutputFifo_io_deq_bits_0 ),
.io_count( directOutputFifo_io_count )
);
Serializer outToBuffer(.clk(clk), .reset(rst),
.io_dataIn_ready( outToBuffer_io_dataIn_ready ),
.io_dataIn_valid( directOutputFifo_io_deq_valid ),
.io_dataIn_bits_7( directOutputFifo_io_deq_bits_7 ),
.io_dataIn_bits_6( directOutputFifo_io_deq_bits_6 ),
.io_dataIn_bits_5( directOutputFifo_io_deq_bits_5 ),
.io_dataIn_bits_4( directOutputFifo_io_deq_bits_4 ),
.io_dataIn_bits_3( directOutputFifo_io_deq_bits_3 ),
.io_dataIn_bits_2( directOutputFifo_io_deq_bits_2 ),
.io_dataIn_bits_1( directOutputFifo_io_deq_bits_1 ),
.io_dataIn_bits_0( directOutputFifo_io_deq_bits_0 ),
.io_flush( flush ),
.io_dataOut_valid( outToBuffer_io_dataOut_valid ),
.io_dataOut_bits_63( outToBuffer_io_dataOut_bits_63 ),
.io_dataOut_bits_62( outToBuffer_io_dataOut_bits_62 ),
.io_dataOut_bits_61( outToBuffer_io_dataOut_bits_61 ),
.io_dataOut_bits_60( outToBuffer_io_dataOut_bits_60 ),
.io_dataOut_bits_59( outToBuffer_io_dataOut_bits_59 ),
.io_dataOut_bits_58( outToBuffer_io_dataOut_bits_58 ),
.io_dataOut_bits_57( outToBuffer_io_dataOut_bits_57 ),
.io_dataOut_bits_56( outToBuffer_io_dataOut_bits_56 ),
.io_dataOut_bits_55( outToBuffer_io_dataOut_bits_55 ),
.io_dataOut_bits_54( outToBuffer_io_dataOut_bits_54 ),
.io_dataOut_bits_53( outToBuffer_io_dataOut_bits_53 ),
.io_dataOut_bits_52( outToBuffer_io_dataOut_bits_52 ),
.io_dataOut_bits_51( outToBuffer_io_dataOut_bits_51 ),
.io_dataOut_bits_50( outToBuffer_io_dataOut_bits_50 ),
.io_dataOut_bits_49( outToBuffer_io_dataOut_bits_49 ),
.io_dataOut_bits_48( outToBuffer_io_dataOut_bits_48 ),
.io_dataOut_bits_47( outToBuffer_io_dataOut_bits_47 ),
.io_dataOut_bits_46( outToBuffer_io_dataOut_bits_46 ),
.io_dataOut_bits_45( outToBuffer_io_dataOut_bits_45 ),
.io_dataOut_bits_44( outToBuffer_io_dataOut_bits_44 ),
.io_dataOut_bits_43( outToBuffer_io_dataOut_bits_43 ),
.io_dataOut_bits_42( outToBuffer_io_dataOut_bits_42 ),
.io_dataOut_bits_41( outToBuffer_io_dataOut_bits_41 ),
.io_dataOut_bits_40( outToBuffer_io_dataOut_bits_40 ),
.io_dataOut_bits_39( outToBuffer_io_dataOut_bits_39 ),
.io_dataOut_bits_38( outToBuffer_io_dataOut_bits_38 ),
.io_dataOut_bits_37( outToBuffer_io_dataOut_bits_37 ),
.io_dataOut_bits_36( outToBuffer_io_dataOut_bits_36 ),
.io_dataOut_bits_35( outToBuffer_io_dataOut_bits_35 ),
.io_dataOut_bits_34( outToBuffer_io_dataOut_bits_34 ),
.io_dataOut_bits_33( outToBuffer_io_dataOut_bits_33 ),
.io_dataOut_bits_32( outToBuffer_io_dataOut_bits_32 ),
.io_dataOut_bits_31( outToBuffer_io_dataOut_bits_31 ),
.io_dataOut_bits_30( outToBuffer_io_dataOut_bits_30 ),
.io_dataOut_bits_29( outToBuffer_io_dataOut_bits_29 ),
.io_dataOut_bits_28( outToBuffer_io_dataOut_bits_28 ),
.io_dataOut_bits_27( outToBuffer_io_dataOut_bits_27 ),
.io_dataOut_bits_26( outToBuffer_io_dataOut_bits_26 ),
.io_dataOut_bits_25( outToBuffer_io_dataOut_bits_25 ),
.io_dataOut_bits_24( outToBuffer_io_dataOut_bits_24 ),
.io_dataOut_bits_23( outToBuffer_io_dataOut_bits_23 ),
.io_dataOut_bits_22( outToBuffer_io_dataOut_bits_22 ),
.io_dataOut_bits_21( outToBuffer_io_dataOut_bits_21 ),
.io_dataOut_bits_20( outToBuffer_io_dataOut_bits_20 ),
.io_dataOut_bits_19( outToBuffer_io_dataOut_bits_19 ),
.io_dataOut_bits_18( outToBuffer_io_dataOut_bits_18 ),
.io_dataOut_bits_17( outToBuffer_io_dataOut_bits_17 ),
.io_dataOut_bits_16( outToBuffer_io_dataOut_bits_16 ),
.io_dataOut_bits_15( outToBuffer_io_dataOut_bits_15 ),
.io_dataOut_bits_14( outToBuffer_io_dataOut_bits_14 ),
.io_dataOut_bits_13( outToBuffer_io_dataOut_bits_13 ),
.io_dataOut_bits_12( outToBuffer_io_dataOut_bits_12 ),
.io_dataOut_bits_11( outToBuffer_io_dataOut_bits_11 ),
.io_dataOut_bits_10( outToBuffer_io_dataOut_bits_10 ),
.io_dataOut_bits_9( outToBuffer_io_dataOut_bits_9 ),
.io_dataOut_bits_8( outToBuffer_io_dataOut_bits_8 ),
.io_dataOut_bits_7( outToBuffer_io_dataOut_bits_7 ),
.io_dataOut_bits_6( outToBuffer_io_dataOut_bits_6 ),
.io_dataOut_bits_5( outToBuffer_io_dataOut_bits_5 ),
.io_dataOut_bits_4( outToBuffer_io_dataOut_bits_4 ),
.io_dataOut_bits_3( outToBuffer_io_dataOut_bits_3 ),
.io_dataOut_bits_2( outToBuffer_io_dataOut_bits_2 ),
.io_dataOut_bits_1( outToBuffer_io_dataOut_bits_1 ),
.io_dataOut_bits_0( outToBuffer_io_dataOut_bits_0 )
//.io_flushed( )
);
Queue_0 fifoTxOut(.clk(clk), .reset(rst),
.io_enq_ready( fifoTxOut_io_enq_ready ),
.io_enq_valid( bufferVld ),
.io_enq_bits_7( bufferByte_7 ),
.io_enq_bits_6( bufferByte_6 ),
.io_enq_bits_5( bufferByte_5 ),
.io_enq_bits_4( bufferByte_4 ),
.io_enq_bits_3( bufferByte_3 ),
.io_enq_bits_2( bufferByte_2 ),
.io_enq_bits_1( bufferByte_1 ),
.io_enq_bits_0( bufferByte_0 ),
.io_deq_ready( T0 ),
.io_deq_valid( fifoTxOut_io_deq_valid ),
.io_deq_bits_7( fifoTxOut_io_deq_bits_7 ),
.io_deq_bits_6( fifoTxOut_io_deq_bits_6 ),
.io_deq_bits_5( fifoTxOut_io_deq_bits_5 ),
.io_deq_bits_4( fifoTxOut_io_deq_bits_4 ),
.io_deq_bits_3( fifoTxOut_io_deq_bits_3 ),
.io_deq_bits_2( fifoTxOut_io_deq_bits_2 ),
.io_deq_bits_1( fifoTxOut_io_deq_bits_1 ),
.io_deq_bits_0( fifoTxOut_io_deq_bits_0 ),
.io_count( fifoTxOut_io_count )
);
always @(posedge clk) begin
if(rst) begin
controlReg <= T1;
end else if(T3) begin
controlReg <= reg_w_data;
end
if(rst) begin
sending <= 1'h0;
end else if(T11) begin
sending <= 1'h0;
end else begin
sending <= T9;
end
if(rst) begin
segmentCounter <= 4'h0;
end else if(fifoDrain) begin
segmentCounter <= 4'h0;
end else if(T19) begin
segmentCounter <= 4'h0;
end else if(T18) begin
segmentCounter <= T17;
end
buffer_7 <= outToBuffer_io_dataOut_bits_7;
buffer_6 <= outToBuffer_io_dataOut_bits_6;
buffer_5 <= outToBuffer_io_dataOut_bits_5;
buffer_4 <= outToBuffer_io_dataOut_bits_4;
buffer_3 <= outToBuffer_io_dataOut_bits_3;
buffer_2 <= outToBuffer_io_dataOut_bits_2;
buffer_1 <= outToBuffer_io_dataOut_bits_1;
buffer_0 <= outToBuffer_io_dataOut_bits_0;
buffer_15 <= outToBuffer_io_dataOut_bits_15;
buffer_14 <= outToBuffer_io_dataOut_bits_14;
buffer_13 <= outToBuffer_io_dataOut_bits_13;
buffer_12 <= outToBuffer_io_dataOut_bits_12;
buffer_11 <= outToBuffer_io_dataOut_bits_11;
buffer_10 <= outToBuffer_io_dataOut_bits_10;
buffer_9 <= outToBuffer_io_dataOut_bits_9;
buffer_8 <= outToBuffer_io_dataOut_bits_8;
buffer_23 <= outToBuffer_io_dataOut_bits_23;
buffer_22 <= outToBuffer_io_dataOut_bits_22;
buffer_21 <= outToBuffer_io_dataOut_bits_21;
buffer_20 <= outToBuffer_io_dataOut_bits_20;
buffer_19 <= outToBuffer_io_dataOut_bits_19;
buffer_18 <= outToBuffer_io_dataOut_bits_18;
buffer_17 <= outToBuffer_io_dataOut_bits_17;
buffer_16 <= outToBuffer_io_dataOut_bits_16;
buffer_31 <= outToBuffer_io_dataOut_bits_31;
buffer_30 <= outToBuffer_io_dataOut_bits_30;
buffer_29 <= outToBuffer_io_dataOut_bits_29;
buffer_28 <= outToBuffer_io_dataOut_bits_28;
buffer_27 <= outToBuffer_io_dataOut_bits_27;
buffer_26 <= outToBuffer_io_dataOut_bits_26;
buffer_25 <= outToBuffer_io_dataOut_bits_25;
buffer_24 <= outToBuffer_io_dataOut_bits_24;
buffer_39 <= outToBuffer_io_dataOut_bits_39;
buffer_38 <= outToBuffer_io_dataOut_bits_38;
buffer_37 <= outToBuffer_io_dataOut_bits_37;
buffer_36 <= outToBuffer_io_dataOut_bits_36;
buffer_35 <= outToBuffer_io_dataOut_bits_35;
buffer_34 <= outToBuffer_io_dataOut_bits_34;
buffer_33 <= outToBuffer_io_dataOut_bits_33;
buffer_32 <= outToBuffer_io_dataOut_bits_32;
buffer_47 <= outToBuffer_io_dataOut_bits_47;
buffer_46 <= outToBuffer_io_dataOut_bits_46;
buffer_45 <= outToBuffer_io_dataOut_bits_45;
buffer_44 <= outToBuffer_io_dataOut_bits_44;
buffer_43 <= outToBuffer_io_dataOut_bits_43;
buffer_42 <= outToBuffer_io_dataOut_bits_42;
buffer_41 <= outToBuffer_io_dataOut_bits_41;
buffer_40 <= outToBuffer_io_dataOut_bits_40;
buffer_55 <= outToBuffer_io_dataOut_bits_55;
buffer_54 <= outToBuffer_io_dataOut_bits_54;
buffer_53 <= outToBuffer_io_dataOut_bits_53;
buffer_52 <= outToBuffer_io_dataOut_bits_52;
buffer_51 <= outToBuffer_io_dataOut_bits_51;
buffer_50 <= outToBuffer_io_dataOut_bits_50;
buffer_49 <= outToBuffer_io_dataOut_bits_49;
buffer_48 <= outToBuffer_io_dataOut_bits_48;
buffer_63 <= outToBuffer_io_dataOut_bits_63;
buffer_62 <= outToBuffer_io_dataOut_bits_62;
buffer_61 <= outToBuffer_io_dataOut_bits_61;
buffer_60 <= outToBuffer_io_dataOut_bits_60;
buffer_59 <= outToBuffer_io_dataOut_bits_59;
buffer_58 <= outToBuffer_io_dataOut_bits_58;
buffer_57 <= outToBuffer_io_dataOut_bits_57;
buffer_56 <= outToBuffer_io_dataOut_bits_56;
bufferVld <= outToBuffer_io_dataOut_valid;
if(rst) begin
buffCount <= 7'h0;
end else if(flush) begin
buffCount <= 7'h0;
end else if(T473) begin
buffCount <= T472;
end
if (1'h1)
userMem[T1238] <= T1198;
if(rst) begin
regIntR_0 <= T636;
end else if(T638) begin
regIntR_0 <= reg_w_data;
end
if(rst) begin
regIntR_1 <= T640;
end else if(T642) begin
regIntR_1 <= reg_w_data;
end
if(rst) begin
regIntR_2 <= T644;
end else if(T646) begin
regIntR_2 <= reg_w_data;
end
if(rst) begin
regIntR_3 <= T648;
end else if(T650) begin
regIntR_3 <= reg_w_data;
end
if(rst) begin
regIntR_4 <= T652;
end else if(T654) begin
regIntR_4 <= reg_w_data;
end
if(rst) begin
regIntR_5 <= T656;
end else if(T658) begin
regIntR_5 <= reg_w_data;
end
if(rst) begin
regIntR_6 <= T660;
end else if(T662) begin
regIntR_6 <= reg_w_data;
end
if(rst) begin
regIntR_7 <= T664;
end else if(T666) begin
regIntR_7 <= reg_w_data;
end
if(rst) begin
regIntR_8 <= T668;
end else if(T670) begin
regIntR_8 <= reg_w_data;
end
if(rst) begin
regIntR_9 <= T672;
end else if(T674) begin
regIntR_9 <= reg_w_data;
end
if(rst) begin
regIntR_10 <= T676;
end else if(T678) begin
regIntR_10 <= reg_w_data;
end
if(rst) begin
regIntR_11 <= T680;
end else if(T682) begin
regIntR_11 <= reg_w_data;
end
if(rst) begin
regIntR_12 <= T684;
end else if(T686) begin
regIntR_12 <= reg_w_data;
end
if(rst) begin
regIntR_13 <= T688;
end else if(T690) begin
regIntR_13 <= reg_w_data;
end
if(rst) begin
regIntR_14 <= T692;
end else if(T694) begin
regIntR_14 <= reg_w_data;
end
if(rst) begin
regIntW_0 <= T752;
end else if(userMod_io_regOutEn) begin
regIntW_0 <= userMod_io_regOut_0;
end
if(rst) begin
regIntW_1 <= T754;
end else if(userMod_io_regOutEn) begin
regIntW_1 <= userMod_io_regOut_1;
end
if(rst) begin
regIntW_2 <= T759;
end else if(userMod_io_regOutEn) begin
regIntW_2 <= userMod_io_regOut_2;
end
if(rst) begin
regIntW_3 <= T761;
end else if(userMod_io_regOutEn) begin
regIntW_3 <= userMod_io_regOut_3;
end
if(rst) begin
regIntW_4 <= T767;
end else if(userMod_io_regOutEn) begin
regIntW_4 <= userMod_io_regOut_4;
end
if(rst) begin
regIntW_5 <= T769;
end else if(userMod_io_regOutEn) begin
regIntW_5 <= userMod_io_regOut_5;
end
if(rst) begin
regIntW_6 <= T773;
end else if(userMod_io_regOutEn) begin
regIntW_6 <= userMod_io_regOut_6;
end
if(rst) begin
regIntW_7 <= T775;
end else if(userMod_io_regOutEn) begin
regIntW_7 <= userMod_io_regOut_7;
end
if(rst) begin
regIntW_8 <= T783;
end else if(userMod_io_regOutEn) begin
regIntW_8 <= userMod_io_regOut_8;
end
if(rst) begin
regIntW_9 <= T785;
end else if(userMod_io_regOutEn) begin
regIntW_9 <= userMod_io_regOut_9;
end
if(rst) begin
regIntW_10 <= T789;
end else if(userMod_io_regOutEn) begin
regIntW_10 <= userMod_io_regOut_10;
end
if(rst) begin
regIntW_11 <= T791;
end else if(userMod_io_regOutEn) begin
regIntW_11 <= userMod_io_regOut_11;
end
if(rst) begin
regIntW_12 <= T797;
end else if(userMod_io_regOutEn) begin
regIntW_12 <= userMod_io_regOut_12;
end
if(rst) begin
regIntW_13 <= T799;
end else if(userMod_io_regOutEn) begin
regIntW_13 <= userMod_io_regOut_13;
end
if(rst) begin
regIntW_14 <= T803;
end else if(userMod_io_regOutEn) begin
regIntW_14 <= userMod_io_regOut_14;
end
if(rst) begin
regIntW_15 <= T805;
end else begin
regIntW_15 <= T1364;
end
if(rst) begin
userErr <= 1'h0;
end else if(errRst) begin
userErr <= 1'h0;
end else begin
userErr <= T809;
end
if(rst) begin
dirOutFull <= 1'h0;
end else if(errRst) begin
dirOutFull <= 1'h0;
end else begin
dirOutFull <= T812;
end
if(rst) begin
txFifoFull <= 1'h0;
end else if(errRst) begin
txFifoFull <= 1'h0;
end else begin
txFifoFull <= T816;
end
if(rst) begin
fifoFull <= 1'h0;
end else if(errRst) begin
fifoFull <= 1'h0;
end else begin
fifoFull <= T820;
end
if(rst) begin
crcFail <= 1'h0;
end else if(errRst) begin
crcFail <= 1'h0;
end else begin
crcFail <= T824;
end
if(rst) begin
pktDrop <= 1'h0;
end else if(errRst) begin
pktDrop <= 1'h0;
end else begin
pktDrop <= T827;
end
if(rst) begin
rx1Err <= 1'h0;
end else if(errRst) begin
rx1Err <= 1'h0;
end else begin
rx1Err <= T829;
end
end
endmodule
|
// system_acl_iface_acl_kernel_interface.v
// Generated using ACDS version 14.0 200 at 2015.05.05.08:40:28
`timescale 1 ps / 1 ps
module system_acl_iface_acl_kernel_interface (
input wire clk_clk, // clk.clk
input wire reset_reset_n, // reset.reset_n
output wire kernel_cntrl_waitrequest, // kernel_cntrl.waitrequest
output wire [31:0] kernel_cntrl_readdata, // .readdata
output wire kernel_cntrl_readdatavalid, // .readdatavalid
input wire [0:0] kernel_cntrl_burstcount, // .burstcount
input wire [31:0] kernel_cntrl_writedata, // .writedata
input wire [13:0] kernel_cntrl_address, // .address
input wire kernel_cntrl_write, // .write
input wire kernel_cntrl_read, // .read
input wire [3:0] kernel_cntrl_byteenable, // .byteenable
input wire kernel_cntrl_debugaccess, // .debugaccess
input wire kernel_cra_waitrequest, // kernel_cra.waitrequest
input wire [63:0] kernel_cra_readdata, // .readdata
input wire kernel_cra_readdatavalid, // .readdatavalid
output wire [0:0] kernel_cra_burstcount, // .burstcount
output wire [63:0] kernel_cra_writedata, // .writedata
output wire [29:0] kernel_cra_address, // .address
output wire kernel_cra_write, // .write
output wire kernel_cra_read, // .read
output wire [7:0] kernel_cra_byteenable, // .byteenable
output wire kernel_cra_debugaccess, // .debugaccess
input wire [0:0] kernel_irq_from_kernel_irq, // kernel_irq_from_kernel.irq
output wire [1:0] acl_bsp_memorg_kernel_mode, // acl_bsp_memorg_kernel.mode
output wire [1:0] acl_bsp_memorg_host_mode, // acl_bsp_memorg_host.mode
input wire sw_reset_in_reset, // sw_reset_in.reset
input wire kernel_clk_clk, // kernel_clk.clk
output wire sw_reset_export_reset_n, // sw_reset_export.reset_n
output wire kernel_reset_reset_n, // kernel_reset.reset_n
output wire kernel_irq_to_host_irq // kernel_irq_to_host.irq
);
wire reset_controller_sw_reset_out_reset; // reset_controller_sw:reset_out -> [irq_bridge_0:reset, kernel_cra:reset, mm_interconnect_0:kernel_cra_reset_reset_bridge_in_reset_reset, reset_controller_sw_reset_out_reset:in]
wire [0:0] address_span_extender_0_expanded_master_burstcount; // address_span_extender_0:avm_m0_burstcount -> mm_interconnect_0:address_span_extender_0_expanded_master_burstcount
wire address_span_extender_0_expanded_master_waitrequest; // mm_interconnect_0:address_span_extender_0_expanded_master_waitrequest -> address_span_extender_0:avm_m0_waitrequest
wire [31:0] address_span_extender_0_expanded_master_writedata; // address_span_extender_0:avm_m0_writedata -> mm_interconnect_0:address_span_extender_0_expanded_master_writedata
wire [29:0] address_span_extender_0_expanded_master_address; // address_span_extender_0:avm_m0_address -> mm_interconnect_0:address_span_extender_0_expanded_master_address
wire address_span_extender_0_expanded_master_write; // address_span_extender_0:avm_m0_write -> mm_interconnect_0:address_span_extender_0_expanded_master_write
wire address_span_extender_0_expanded_master_read; // address_span_extender_0:avm_m0_read -> mm_interconnect_0:address_span_extender_0_expanded_master_read
wire [31:0] address_span_extender_0_expanded_master_readdata; // mm_interconnect_0:address_span_extender_0_expanded_master_readdata -> address_span_extender_0:avm_m0_readdata
wire [3:0] address_span_extender_0_expanded_master_byteenable; // address_span_extender_0:avm_m0_byteenable -> mm_interconnect_0:address_span_extender_0_expanded_master_byteenable
wire address_span_extender_0_expanded_master_readdatavalid; // mm_interconnect_0:address_span_extender_0_expanded_master_readdatavalid -> address_span_extender_0:avm_m0_readdatavalid
wire mm_interconnect_0_kernel_cra_s0_waitrequest; // kernel_cra:s0_waitrequest -> mm_interconnect_0:kernel_cra_s0_waitrequest
wire [0:0] mm_interconnect_0_kernel_cra_s0_burstcount; // mm_interconnect_0:kernel_cra_s0_burstcount -> kernel_cra:s0_burstcount
wire [63:0] mm_interconnect_0_kernel_cra_s0_writedata; // mm_interconnect_0:kernel_cra_s0_writedata -> kernel_cra:s0_writedata
wire [29:0] mm_interconnect_0_kernel_cra_s0_address; // mm_interconnect_0:kernel_cra_s0_address -> kernel_cra:s0_address
wire mm_interconnect_0_kernel_cra_s0_write; // mm_interconnect_0:kernel_cra_s0_write -> kernel_cra:s0_write
wire mm_interconnect_0_kernel_cra_s0_read; // mm_interconnect_0:kernel_cra_s0_read -> kernel_cra:s0_read
wire [63:0] mm_interconnect_0_kernel_cra_s0_readdata; // kernel_cra:s0_readdata -> mm_interconnect_0:kernel_cra_s0_readdata
wire mm_interconnect_0_kernel_cra_s0_debugaccess; // mm_interconnect_0:kernel_cra_s0_debugaccess -> kernel_cra:s0_debugaccess
wire mm_interconnect_0_kernel_cra_s0_readdatavalid; // kernel_cra:s0_readdatavalid -> mm_interconnect_0:kernel_cra_s0_readdatavalid
wire [7:0] mm_interconnect_0_kernel_cra_s0_byteenable; // mm_interconnect_0:kernel_cra_s0_byteenable -> kernel_cra:s0_byteenable
wire [0:0] kernel_cntrl_m0_burstcount; // kernel_cntrl:m0_burstcount -> mm_interconnect_1:kernel_cntrl_m0_burstcount
wire kernel_cntrl_m0_waitrequest; // mm_interconnect_1:kernel_cntrl_m0_waitrequest -> kernel_cntrl:m0_waitrequest
wire [13:0] kernel_cntrl_m0_address; // kernel_cntrl:m0_address -> mm_interconnect_1:kernel_cntrl_m0_address
wire [31:0] kernel_cntrl_m0_writedata; // kernel_cntrl:m0_writedata -> mm_interconnect_1:kernel_cntrl_m0_writedata
wire kernel_cntrl_m0_write; // kernel_cntrl:m0_write -> mm_interconnect_1:kernel_cntrl_m0_write
wire kernel_cntrl_m0_read; // kernel_cntrl:m0_read -> mm_interconnect_1:kernel_cntrl_m0_read
wire [31:0] kernel_cntrl_m0_readdata; // mm_interconnect_1:kernel_cntrl_m0_readdata -> kernel_cntrl:m0_readdata
wire kernel_cntrl_m0_debugaccess; // kernel_cntrl:m0_debugaccess -> mm_interconnect_1:kernel_cntrl_m0_debugaccess
wire [3:0] kernel_cntrl_m0_byteenable; // kernel_cntrl:m0_byteenable -> mm_interconnect_1:kernel_cntrl_m0_byteenable
wire kernel_cntrl_m0_readdatavalid; // mm_interconnect_1:kernel_cntrl_m0_readdatavalid -> kernel_cntrl:m0_readdatavalid
wire mm_interconnect_1_address_span_extender_0_windowed_slave_waitrequest; // address_span_extender_0:avs_s0_waitrequest -> mm_interconnect_1:address_span_extender_0_windowed_slave_waitrequest
wire [0:0] mm_interconnect_1_address_span_extender_0_windowed_slave_burstcount; // mm_interconnect_1:address_span_extender_0_windowed_slave_burstcount -> address_span_extender_0:avs_s0_burstcount
wire [31:0] mm_interconnect_1_address_span_extender_0_windowed_slave_writedata; // mm_interconnect_1:address_span_extender_0_windowed_slave_writedata -> address_span_extender_0:avs_s0_writedata
wire [9:0] mm_interconnect_1_address_span_extender_0_windowed_slave_address; // mm_interconnect_1:address_span_extender_0_windowed_slave_address -> address_span_extender_0:avs_s0_address
wire mm_interconnect_1_address_span_extender_0_windowed_slave_write; // mm_interconnect_1:address_span_extender_0_windowed_slave_write -> address_span_extender_0:avs_s0_write
wire mm_interconnect_1_address_span_extender_0_windowed_slave_read; // mm_interconnect_1:address_span_extender_0_windowed_slave_read -> address_span_extender_0:avs_s0_read
wire [31:0] mm_interconnect_1_address_span_extender_0_windowed_slave_readdata; // address_span_extender_0:avs_s0_readdata -> mm_interconnect_1:address_span_extender_0_windowed_slave_readdata
wire mm_interconnect_1_address_span_extender_0_windowed_slave_readdatavalid; // address_span_extender_0:avs_s0_readdatavalid -> mm_interconnect_1:address_span_extender_0_windowed_slave_readdatavalid
wire [3:0] mm_interconnect_1_address_span_extender_0_windowed_slave_byteenable; // mm_interconnect_1:address_span_extender_0_windowed_slave_byteenable -> address_span_extender_0:avs_s0_byteenable
wire [63:0] mm_interconnect_1_address_span_extender_0_cntl_writedata; // mm_interconnect_1:address_span_extender_0_cntl_writedata -> address_span_extender_0:avs_cntl_writedata
wire mm_interconnect_1_address_span_extender_0_cntl_write; // mm_interconnect_1:address_span_extender_0_cntl_write -> address_span_extender_0:avs_cntl_write
wire mm_interconnect_1_address_span_extender_0_cntl_read; // mm_interconnect_1:address_span_extender_0_cntl_read -> address_span_extender_0:avs_cntl_read
wire [63:0] mm_interconnect_1_address_span_extender_0_cntl_readdata; // address_span_extender_0:avs_cntl_readdata -> mm_interconnect_1:address_span_extender_0_cntl_readdata
wire [7:0] mm_interconnect_1_address_span_extender_0_cntl_byteenable; // mm_interconnect_1:address_span_extender_0_cntl_byteenable -> address_span_extender_0:avs_cntl_byteenable
wire [63:0] mm_interconnect_1_sys_description_rom_s1_writedata; // mm_interconnect_1:sys_description_rom_s1_writedata -> sys_description_rom:writedata
wire [8:0] mm_interconnect_1_sys_description_rom_s1_address; // mm_interconnect_1:sys_description_rom_s1_address -> sys_description_rom:address
wire mm_interconnect_1_sys_description_rom_s1_chipselect; // mm_interconnect_1:sys_description_rom_s1_chipselect -> sys_description_rom:chipselect
wire mm_interconnect_1_sys_description_rom_s1_clken; // mm_interconnect_1:sys_description_rom_s1_clken -> sys_description_rom:clken
wire mm_interconnect_1_sys_description_rom_s1_write; // mm_interconnect_1:sys_description_rom_s1_write -> sys_description_rom:write
wire [63:0] mm_interconnect_1_sys_description_rom_s1_readdata; // sys_description_rom:readdata -> mm_interconnect_1:sys_description_rom_s1_readdata
wire mm_interconnect_1_sys_description_rom_s1_debugaccess; // mm_interconnect_1:sys_description_rom_s1_debugaccess -> sys_description_rom:debugaccess
wire [7:0] mm_interconnect_1_sys_description_rom_s1_byteenable; // mm_interconnect_1:sys_description_rom_s1_byteenable -> sys_description_rom:byteenable
wire mm_interconnect_1_sw_reset_s_waitrequest; // sw_reset:slave_waitrequest -> mm_interconnect_1:sw_reset_s_waitrequest
wire [63:0] mm_interconnect_1_sw_reset_s_writedata; // mm_interconnect_1:sw_reset_s_writedata -> sw_reset:slave_writedata
wire mm_interconnect_1_sw_reset_s_write; // mm_interconnect_1:sw_reset_s_write -> sw_reset:slave_write
wire mm_interconnect_1_sw_reset_s_read; // mm_interconnect_1:sw_reset_s_read -> sw_reset:slave_read
wire [63:0] mm_interconnect_1_sw_reset_s_readdata; // sw_reset:slave_readdata -> mm_interconnect_1:sw_reset_s_readdata
wire [7:0] mm_interconnect_1_sw_reset_s_byteenable; // mm_interconnect_1:sw_reset_s_byteenable -> sw_reset:slave_byteenable
wire mm_interconnect_1_mem_org_mode_s_waitrequest; // mem_org_mode:slave_waitrequest -> mm_interconnect_1:mem_org_mode_s_waitrequest
wire [31:0] mm_interconnect_1_mem_org_mode_s_writedata; // mm_interconnect_1:mem_org_mode_s_writedata -> mem_org_mode:slave_writedata
wire mm_interconnect_1_mem_org_mode_s_write; // mm_interconnect_1:mem_org_mode_s_write -> mem_org_mode:slave_write
wire mm_interconnect_1_mem_org_mode_s_read; // mm_interconnect_1:mem_org_mode_s_read -> mem_org_mode:slave_read
wire [31:0] mm_interconnect_1_mem_org_mode_s_readdata; // mem_org_mode:slave_readdata -> mm_interconnect_1:mem_org_mode_s_readdata
wire mm_interconnect_1_version_id_0_s_read; // mm_interconnect_1:version_id_0_s_read -> version_id_0:slave_read
wire [31:0] mm_interconnect_1_version_id_0_s_readdata; // version_id_0:slave_readdata -> mm_interconnect_1:version_id_0_s_readdata
wire mm_interconnect_1_irq_ena_0_s_waitrequest; // irq_ena_0:slave_waitrequest -> mm_interconnect_1:irq_ena_0_s_waitrequest
wire [31:0] mm_interconnect_1_irq_ena_0_s_writedata; // mm_interconnect_1:irq_ena_0_s_writedata -> irq_ena_0:slave_writedata
wire mm_interconnect_1_irq_ena_0_s_write; // mm_interconnect_1:irq_ena_0_s_write -> irq_ena_0:slave_write
wire mm_interconnect_1_irq_ena_0_s_read; // mm_interconnect_1:irq_ena_0_s_read -> irq_ena_0:slave_read
wire [31:0] mm_interconnect_1_irq_ena_0_s_readdata; // irq_ena_0:slave_readdata -> mm_interconnect_1:irq_ena_0_s_readdata
wire [3:0] mm_interconnect_1_irq_ena_0_s_byteenable; // mm_interconnect_1:irq_ena_0_s_byteenable -> irq_ena_0:slave_byteenable
wire irq_mapper_receiver0_irq; // irq_bridge_0:sender0_irq -> irq_mapper:receiver0_irq
wire irq_ena_0_my_irq_in_irq; // irq_mapper:sender_irq -> irq_ena_0:irq
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [irq_ena_0:resetn, kernel_cntrl:reset, mem_org_mode:resetn, mm_interconnect_1:kernel_cntrl_reset_reset_bridge_in_reset_reset, rst_translator:in_reset, sys_description_rom:reset, version_id_0:resetn]
wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> [rst_translator:reset_req_in, sys_description_rom:reset_req]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [address_span_extender_0:reset, mm_interconnect_0:address_span_extender_0_reset_reset_bridge_in_reset_reset, mm_interconnect_1:address_span_extender_0_reset_reset_bridge_in_reset_reset]
wire rst_controller_002_reset_out_reset; // rst_controller_002:reset_out -> [mm_interconnect_1:sw_reset_clk_reset_reset_bridge_in_reset_reset, sw_reset:resetn]
system_acl_iface_acl_kernel_interface_sys_description_rom sys_description_rom (
.clk (clk_clk), // clk1.clk
.address (mm_interconnect_1_sys_description_rom_s1_address), // s1.address
.debugaccess (mm_interconnect_1_sys_description_rom_s1_debugaccess), // .debugaccess
.clken (mm_interconnect_1_sys_description_rom_s1_clken), // .clken
.chipselect (mm_interconnect_1_sys_description_rom_s1_chipselect), // .chipselect
.write (mm_interconnect_1_sys_description_rom_s1_write), // .write
.readdata (mm_interconnect_1_sys_description_rom_s1_readdata), // .readdata
.writedata (mm_interconnect_1_sys_description_rom_s1_writedata), // .writedata
.byteenable (mm_interconnect_1_sys_description_rom_s1_byteenable), // .byteenable
.reset (rst_controller_reset_out_reset), // reset1.reset
.reset_req (rst_controller_reset_out_reset_req) // .reset_req
);
altera_avalon_mm_bridge #(
.DATA_WIDTH (64),
.SYMBOL_WIDTH (8),
.HDL_ADDR_WIDTH (30),
.BURSTCOUNT_WIDTH (1),
.PIPELINE_COMMAND (1),
.PIPELINE_RESPONSE (1)
) kernel_cra (
.clk (kernel_clk_clk), // clk.clk
.reset (reset_controller_sw_reset_out_reset), // reset.reset
.s0_waitrequest (mm_interconnect_0_kernel_cra_s0_waitrequest), // s0.waitrequest
.s0_readdata (mm_interconnect_0_kernel_cra_s0_readdata), // .readdata
.s0_readdatavalid (mm_interconnect_0_kernel_cra_s0_readdatavalid), // .readdatavalid
.s0_burstcount (mm_interconnect_0_kernel_cra_s0_burstcount), // .burstcount
.s0_writedata (mm_interconnect_0_kernel_cra_s0_writedata), // .writedata
.s0_address (mm_interconnect_0_kernel_cra_s0_address), // .address
.s0_write (mm_interconnect_0_kernel_cra_s0_write), // .write
.s0_read (mm_interconnect_0_kernel_cra_s0_read), // .read
.s0_byteenable (mm_interconnect_0_kernel_cra_s0_byteenable), // .byteenable
.s0_debugaccess (mm_interconnect_0_kernel_cra_s0_debugaccess), // .debugaccess
.m0_waitrequest (kernel_cra_waitrequest), // m0.waitrequest
.m0_readdata (kernel_cra_readdata), // .readdata
.m0_readdatavalid (kernel_cra_readdatavalid), // .readdatavalid
.m0_burstcount (kernel_cra_burstcount), // .burstcount
.m0_writedata (kernel_cra_writedata), // .writedata
.m0_address (kernel_cra_address), // .address
.m0_write (kernel_cra_write), // .write
.m0_read (kernel_cra_read), // .read
.m0_byteenable (kernel_cra_byteenable), // .byteenable
.m0_debugaccess (kernel_cra_debugaccess) // .debugaccess
);
altera_address_span_extender #(
.DATA_WIDTH (32),
.BYTEENABLE_WIDTH (4),
.MASTER_ADDRESS_WIDTH (30),
.SLAVE_ADDRESS_WIDTH (10),
.SLAVE_ADDRESS_SHIFT (2),
.BURSTCOUNT_WIDTH (1),
.CNTL_ADDRESS_WIDTH (1),
.SUB_WINDOW_COUNT (1),
.MASTER_ADDRESS_DEF (64'b0000000000000000000000000000000000000000000000000000000000000000)
) address_span_extender_0 (
.clk (kernel_clk_clk), // clock.clk
.reset (rst_controller_001_reset_out_reset), // reset.reset
.avs_s0_address (mm_interconnect_1_address_span_extender_0_windowed_slave_address), // windowed_slave.address
.avs_s0_read (mm_interconnect_1_address_span_extender_0_windowed_slave_read), // .read
.avs_s0_readdata (mm_interconnect_1_address_span_extender_0_windowed_slave_readdata), // .readdata
.avs_s0_write (mm_interconnect_1_address_span_extender_0_windowed_slave_write), // .write
.avs_s0_writedata (mm_interconnect_1_address_span_extender_0_windowed_slave_writedata), // .writedata
.avs_s0_readdatavalid (mm_interconnect_1_address_span_extender_0_windowed_slave_readdatavalid), // .readdatavalid
.avs_s0_waitrequest (mm_interconnect_1_address_span_extender_0_windowed_slave_waitrequest), // .waitrequest
.avs_s0_byteenable (mm_interconnect_1_address_span_extender_0_windowed_slave_byteenable), // .byteenable
.avs_s0_burstcount (mm_interconnect_1_address_span_extender_0_windowed_slave_burstcount), // .burstcount
.avm_m0_address (address_span_extender_0_expanded_master_address), // expanded_master.address
.avm_m0_read (address_span_extender_0_expanded_master_read), // .read
.avm_m0_waitrequest (address_span_extender_0_expanded_master_waitrequest), // .waitrequest
.avm_m0_readdata (address_span_extender_0_expanded_master_readdata), // .readdata
.avm_m0_write (address_span_extender_0_expanded_master_write), // .write
.avm_m0_writedata (address_span_extender_0_expanded_master_writedata), // .writedata
.avm_m0_readdatavalid (address_span_extender_0_expanded_master_readdatavalid), // .readdatavalid
.avm_m0_byteenable (address_span_extender_0_expanded_master_byteenable), // .byteenable
.avm_m0_burstcount (address_span_extender_0_expanded_master_burstcount), // .burstcount
.avs_cntl_read (mm_interconnect_1_address_span_extender_0_cntl_read), // cntl.read
.avs_cntl_readdata (mm_interconnect_1_address_span_extender_0_cntl_readdata), // .readdata
.avs_cntl_write (mm_interconnect_1_address_span_extender_0_cntl_write), // .write
.avs_cntl_writedata (mm_interconnect_1_address_span_extender_0_cntl_writedata), // .writedata
.avs_cntl_byteenable (mm_interconnect_1_address_span_extender_0_cntl_byteenable), // .byteenable
.avs_cntl_address (1'b0) // (terminated)
);
sw_reset #(
.WIDTH (64),
.LOG2_RESET_CYCLES (10)
) sw_reset (
.clk (clk_clk), // clk.clk
.resetn (~rst_controller_002_reset_out_reset), // clk_reset.reset_n
.slave_write (mm_interconnect_1_sw_reset_s_write), // s.write
.slave_writedata (mm_interconnect_1_sw_reset_s_writedata), // .writedata
.slave_byteenable (mm_interconnect_1_sw_reset_s_byteenable), // .byteenable
.slave_read (mm_interconnect_1_sw_reset_s_read), // .read
.slave_readdata (mm_interconnect_1_sw_reset_s_readdata), // .readdata
.slave_waitrequest (mm_interconnect_1_sw_reset_s_waitrequest), // .waitrequest
.sw_reset_n_out (sw_reset_export_reset_n) // sw_reset.reset_n
);
altera_avalon_mm_bridge #(
.DATA_WIDTH (32),
.SYMBOL_WIDTH (8),
.HDL_ADDR_WIDTH (14),
.BURSTCOUNT_WIDTH (1),
.PIPELINE_COMMAND (1),
.PIPELINE_RESPONSE (1)
) kernel_cntrl (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.s0_waitrequest (kernel_cntrl_waitrequest), // s0.waitrequest
.s0_readdata (kernel_cntrl_readdata), // .readdata
.s0_readdatavalid (kernel_cntrl_readdatavalid), // .readdatavalid
.s0_burstcount (kernel_cntrl_burstcount), // .burstcount
.s0_writedata (kernel_cntrl_writedata), // .writedata
.s0_address (kernel_cntrl_address), // .address
.s0_write (kernel_cntrl_write), // .write
.s0_read (kernel_cntrl_read), // .read
.s0_byteenable (kernel_cntrl_byteenable), // .byteenable
.s0_debugaccess (kernel_cntrl_debugaccess), // .debugaccess
.m0_waitrequest (kernel_cntrl_m0_waitrequest), // m0.waitrequest
.m0_readdata (kernel_cntrl_m0_readdata), // .readdata
.m0_readdatavalid (kernel_cntrl_m0_readdatavalid), // .readdatavalid
.m0_burstcount (kernel_cntrl_m0_burstcount), // .burstcount
.m0_writedata (kernel_cntrl_m0_writedata), // .writedata
.m0_address (kernel_cntrl_m0_address), // .address
.m0_write (kernel_cntrl_m0_write), // .write
.m0_read (kernel_cntrl_m0_read), // .read
.m0_byteenable (kernel_cntrl_m0_byteenable), // .byteenable
.m0_debugaccess (kernel_cntrl_m0_debugaccess) // .debugaccess
);
mem_org_mode #(
.WIDTH (32)
) mem_org_mode (
.clk (clk_clk), // clk.clk
.resetn (~rst_controller_reset_out_reset), // clk_reset.reset_n
.slave_write (mm_interconnect_1_mem_org_mode_s_write), // s.write
.slave_writedata (mm_interconnect_1_mem_org_mode_s_writedata), // .writedata
.slave_read (mm_interconnect_1_mem_org_mode_s_read), // .read
.slave_readdata (mm_interconnect_1_mem_org_mode_s_readdata), // .readdata
.slave_waitrequest (mm_interconnect_1_mem_org_mode_s_waitrequest), // .waitrequest
.mem_organization_kernel (acl_bsp_memorg_kernel_mode), // mem_organization_kernel.mode
.mem_organization_host (acl_bsp_memorg_host_mode) // mem_organization_host.mode
);
altera_irq_bridge #(
.IRQ_WIDTH (1)
) irq_bridge_0 (
.clk (kernel_clk_clk), // clk.clk
.receiver_irq (kernel_irq_from_kernel_irq), // receiver_irq.irq
.reset (reset_controller_sw_reset_out_reset), // clk_reset.reset
.sender0_irq (irq_mapper_receiver0_irq), // sender0_irq.irq
.sender1_irq (), // (terminated)
.sender2_irq (), // (terminated)
.sender3_irq (), // (terminated)
.sender4_irq (), // (terminated)
.sender5_irq (), // (terminated)
.sender6_irq (), // (terminated)
.sender7_irq (), // (terminated)
.sender8_irq (), // (terminated)
.sender9_irq (), // (terminated)
.sender10_irq (), // (terminated)
.sender11_irq (), // (terminated)
.sender12_irq (), // (terminated)
.sender13_irq (), // (terminated)
.sender14_irq (), // (terminated)
.sender15_irq (), // (terminated)
.sender16_irq (), // (terminated)
.sender17_irq (), // (terminated)
.sender18_irq (), // (terminated)
.sender19_irq (), // (terminated)
.sender20_irq (), // (terminated)
.sender21_irq (), // (terminated)
.sender22_irq (), // (terminated)
.sender23_irq (), // (terminated)
.sender24_irq (), // (terminated)
.sender25_irq (), // (terminated)
.sender26_irq (), // (terminated)
.sender27_irq (), // (terminated)
.sender28_irq (), // (terminated)
.sender29_irq (), // (terminated)
.sender30_irq (), // (terminated)
.sender31_irq () // (terminated)
);
version_id #(
.WIDTH (32),
.VERSION_ID (-1598029823)
) version_id_0 (
.clk (clk_clk), // clk.clk
.resetn (~rst_controller_reset_out_reset), // clk_reset.reset_n
.slave_read (mm_interconnect_1_version_id_0_s_read), // s.read
.slave_readdata (mm_interconnect_1_version_id_0_s_readdata) // .readdata
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) reset_controller_sw (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.reset_in1 (~sw_reset_export_reset_n), // reset_in1.reset
.clk (kernel_clk_clk), // clk.clk
.reset_out (reset_controller_sw_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
irq_ena irq_ena_0 (
.clk (clk_clk), // clk.clk
.resetn (~rst_controller_reset_out_reset), // clk_reset.reset_n
.slave_write (mm_interconnect_1_irq_ena_0_s_write), // s.write
.slave_writedata (mm_interconnect_1_irq_ena_0_s_writedata), // .writedata
.slave_byteenable (mm_interconnect_1_irq_ena_0_s_byteenable), // .byteenable
.slave_read (mm_interconnect_1_irq_ena_0_s_read), // .read
.slave_readdata (mm_interconnect_1_irq_ena_0_s_readdata), // .readdata
.slave_waitrequest (mm_interconnect_1_irq_ena_0_s_waitrequest), // .waitrequest
.irq (irq_ena_0_my_irq_in_irq), // my_irq_in.irq
.irq_out (kernel_irq_to_host_irq) // my_irq_out.irq
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0 mm_interconnect_0 (
.kernel_clk_out_clk_clk (kernel_clk_clk), // kernel_clk_out_clk.clk
.address_span_extender_0_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // address_span_extender_0_reset_reset_bridge_in_reset.reset
.kernel_cra_reset_reset_bridge_in_reset_reset (reset_controller_sw_reset_out_reset), // kernel_cra_reset_reset_bridge_in_reset.reset
.address_span_extender_0_expanded_master_address (address_span_extender_0_expanded_master_address), // address_span_extender_0_expanded_master.address
.address_span_extender_0_expanded_master_waitrequest (address_span_extender_0_expanded_master_waitrequest), // .waitrequest
.address_span_extender_0_expanded_master_burstcount (address_span_extender_0_expanded_master_burstcount), // .burstcount
.address_span_extender_0_expanded_master_byteenable (address_span_extender_0_expanded_master_byteenable), // .byteenable
.address_span_extender_0_expanded_master_read (address_span_extender_0_expanded_master_read), // .read
.address_span_extender_0_expanded_master_readdata (address_span_extender_0_expanded_master_readdata), // .readdata
.address_span_extender_0_expanded_master_readdatavalid (address_span_extender_0_expanded_master_readdatavalid), // .readdatavalid
.address_span_extender_0_expanded_master_write (address_span_extender_0_expanded_master_write), // .write
.address_span_extender_0_expanded_master_writedata (address_span_extender_0_expanded_master_writedata), // .writedata
.kernel_cra_s0_address (mm_interconnect_0_kernel_cra_s0_address), // kernel_cra_s0.address
.kernel_cra_s0_write (mm_interconnect_0_kernel_cra_s0_write), // .write
.kernel_cra_s0_read (mm_interconnect_0_kernel_cra_s0_read), // .read
.kernel_cra_s0_readdata (mm_interconnect_0_kernel_cra_s0_readdata), // .readdata
.kernel_cra_s0_writedata (mm_interconnect_0_kernel_cra_s0_writedata), // .writedata
.kernel_cra_s0_burstcount (mm_interconnect_0_kernel_cra_s0_burstcount), // .burstcount
.kernel_cra_s0_byteenable (mm_interconnect_0_kernel_cra_s0_byteenable), // .byteenable
.kernel_cra_s0_readdatavalid (mm_interconnect_0_kernel_cra_s0_readdatavalid), // .readdatavalid
.kernel_cra_s0_waitrequest (mm_interconnect_0_kernel_cra_s0_waitrequest), // .waitrequest
.kernel_cra_s0_debugaccess (mm_interconnect_0_kernel_cra_s0_debugaccess) // .debugaccess
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1 mm_interconnect_1 (
.clk_reset_clk_clk (clk_clk), // clk_reset_clk.clk
.kernel_clk_out_clk_clk (kernel_clk_clk), // kernel_clk_out_clk.clk
.address_span_extender_0_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // address_span_extender_0_reset_reset_bridge_in_reset.reset
.kernel_cntrl_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // kernel_cntrl_reset_reset_bridge_in_reset.reset
.sw_reset_clk_reset_reset_bridge_in_reset_reset (rst_controller_002_reset_out_reset), // sw_reset_clk_reset_reset_bridge_in_reset.reset
.kernel_cntrl_m0_address (kernel_cntrl_m0_address), // kernel_cntrl_m0.address
.kernel_cntrl_m0_waitrequest (kernel_cntrl_m0_waitrequest), // .waitrequest
.kernel_cntrl_m0_burstcount (kernel_cntrl_m0_burstcount), // .burstcount
.kernel_cntrl_m0_byteenable (kernel_cntrl_m0_byteenable), // .byteenable
.kernel_cntrl_m0_read (kernel_cntrl_m0_read), // .read
.kernel_cntrl_m0_readdata (kernel_cntrl_m0_readdata), // .readdata
.kernel_cntrl_m0_readdatavalid (kernel_cntrl_m0_readdatavalid), // .readdatavalid
.kernel_cntrl_m0_write (kernel_cntrl_m0_write), // .write
.kernel_cntrl_m0_writedata (kernel_cntrl_m0_writedata), // .writedata
.kernel_cntrl_m0_debugaccess (kernel_cntrl_m0_debugaccess), // .debugaccess
.address_span_extender_0_cntl_write (mm_interconnect_1_address_span_extender_0_cntl_write), // address_span_extender_0_cntl.write
.address_span_extender_0_cntl_read (mm_interconnect_1_address_span_extender_0_cntl_read), // .read
.address_span_extender_0_cntl_readdata (mm_interconnect_1_address_span_extender_0_cntl_readdata), // .readdata
.address_span_extender_0_cntl_writedata (mm_interconnect_1_address_span_extender_0_cntl_writedata), // .writedata
.address_span_extender_0_cntl_byteenable (mm_interconnect_1_address_span_extender_0_cntl_byteenable), // .byteenable
.address_span_extender_0_windowed_slave_address (mm_interconnect_1_address_span_extender_0_windowed_slave_address), // address_span_extender_0_windowed_slave.address
.address_span_extender_0_windowed_slave_write (mm_interconnect_1_address_span_extender_0_windowed_slave_write), // .write
.address_span_extender_0_windowed_slave_read (mm_interconnect_1_address_span_extender_0_windowed_slave_read), // .read
.address_span_extender_0_windowed_slave_readdata (mm_interconnect_1_address_span_extender_0_windowed_slave_readdata), // .readdata
.address_span_extender_0_windowed_slave_writedata (mm_interconnect_1_address_span_extender_0_windowed_slave_writedata), // .writedata
.address_span_extender_0_windowed_slave_burstcount (mm_interconnect_1_address_span_extender_0_windowed_slave_burstcount), // .burstcount
.address_span_extender_0_windowed_slave_byteenable (mm_interconnect_1_address_span_extender_0_windowed_slave_byteenable), // .byteenable
.address_span_extender_0_windowed_slave_readdatavalid (mm_interconnect_1_address_span_extender_0_windowed_slave_readdatavalid), // .readdatavalid
.address_span_extender_0_windowed_slave_waitrequest (mm_interconnect_1_address_span_extender_0_windowed_slave_waitrequest), // .waitrequest
.irq_ena_0_s_write (mm_interconnect_1_irq_ena_0_s_write), // irq_ena_0_s.write
.irq_ena_0_s_read (mm_interconnect_1_irq_ena_0_s_read), // .read
.irq_ena_0_s_readdata (mm_interconnect_1_irq_ena_0_s_readdata), // .readdata
.irq_ena_0_s_writedata (mm_interconnect_1_irq_ena_0_s_writedata), // .writedata
.irq_ena_0_s_byteenable (mm_interconnect_1_irq_ena_0_s_byteenable), // .byteenable
.irq_ena_0_s_waitrequest (mm_interconnect_1_irq_ena_0_s_waitrequest), // .waitrequest
.mem_org_mode_s_write (mm_interconnect_1_mem_org_mode_s_write), // mem_org_mode_s.write
.mem_org_mode_s_read (mm_interconnect_1_mem_org_mode_s_read), // .read
.mem_org_mode_s_readdata (mm_interconnect_1_mem_org_mode_s_readdata), // .readdata
.mem_org_mode_s_writedata (mm_interconnect_1_mem_org_mode_s_writedata), // .writedata
.mem_org_mode_s_waitrequest (mm_interconnect_1_mem_org_mode_s_waitrequest), // .waitrequest
.sw_reset_s_write (mm_interconnect_1_sw_reset_s_write), // sw_reset_s.write
.sw_reset_s_read (mm_interconnect_1_sw_reset_s_read), // .read
.sw_reset_s_readdata (mm_interconnect_1_sw_reset_s_readdata), // .readdata
.sw_reset_s_writedata (mm_interconnect_1_sw_reset_s_writedata), // .writedata
.sw_reset_s_byteenable (mm_interconnect_1_sw_reset_s_byteenable), // .byteenable
.sw_reset_s_waitrequest (mm_interconnect_1_sw_reset_s_waitrequest), // .waitrequest
.sys_description_rom_s1_address (mm_interconnect_1_sys_description_rom_s1_address), // sys_description_rom_s1.address
.sys_description_rom_s1_write (mm_interconnect_1_sys_description_rom_s1_write), // .write
.sys_description_rom_s1_readdata (mm_interconnect_1_sys_description_rom_s1_readdata), // .readdata
.sys_description_rom_s1_writedata (mm_interconnect_1_sys_description_rom_s1_writedata), // .writedata
.sys_description_rom_s1_byteenable (mm_interconnect_1_sys_description_rom_s1_byteenable), // .byteenable
.sys_description_rom_s1_chipselect (mm_interconnect_1_sys_description_rom_s1_chipselect), // .chipselect
.sys_description_rom_s1_clken (mm_interconnect_1_sys_description_rom_s1_clken), // .clken
.sys_description_rom_s1_debugaccess (mm_interconnect_1_sys_description_rom_s1_debugaccess), // .debugaccess
.version_id_0_s_read (mm_interconnect_1_version_id_0_s_read), // version_id_0_s.read
.version_id_0_s_readdata (mm_interconnect_1_version_id_0_s_readdata) // .readdata
);
system_irq_mapper irq_mapper (
.clk (), // clk.clk
.reset (), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.sender_irq (irq_ena_0_my_irq_in_irq) // sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (kernel_clk_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_002 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.reset_in1 (sw_reset_in_reset), // reset_in1.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_002_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
assign kernel_reset_reset_n = ~reset_controller_sw_reset_out_reset;
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_oclkdelay_cal.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Center write DQS in write DQ valid window using Phaser_Out Stage3
// delay
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v1_8_ddr_phy_oclkdelay_cal #
(
parameter TCQ = 100,
parameter tCK = 2500,
parameter nCK_PER_CLK = 4,
parameter DRAM_TYPE = "DDR3",
parameter DRAM_WIDTH = 8,
parameter DQS_CNT_WIDTH = 3,
parameter DQS_WIDTH = 8,
parameter DQ_WIDTH = 64,
parameter SIM_CAL_OPTION = "NONE",
parameter OCAL_EN = "ON"
)
(
input clk,
input rst,
// Start only after PO and PI FINE delay decremented
input oclk_init_delay_start,
input oclkdelay_calib_start,
input [5:0] oclkdelay_init_val,
// Detect write valid data edge during OCLKDELAY calib
input phy_rddata_en,
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data,
// Precharge done status from ddr_phy_init
input prech_done,
// Write Level signals during OCLKDELAY calibration
input [6*DQS_WIDTH-1:0] wl_po_fine_cnt,
output reg wrlvl_final,
// Inc/dec Phaser_Out fine delay line
output reg po_stg3_incdec,
output reg po_en_stg3,
output reg po_stg23_sel,
output reg po_stg23_incdec,
output reg po_en_stg23,
// Completed initial delay increment
output oclk_init_delay_done,
output [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt,
output reg oclk_prech_req,
output reg oclk_calib_resume,
output reg ocal_if_rst,
output oclkdelay_calib_done,
output [255:0] dbg_phy_oclkdelay_cal,
output [16*DRAM_WIDTH-1:0] dbg_oclkdelay_rd_data
);
// Start with an initial delay of 0 on OCLKDELAY. This is required to
// detect two valid data edges when possible. Two edges cannot be
// detected if write DQ and DQS are exactly edge aligned at stage3 tap0.
localparam TAP_CNT = 0;
//(tCK <= 938) ? 13 :
//(tCK <= 1072) ? 14 :
//(tCK <= 1250) ? 15 :
//(tCK <= 1500) ? 16 : 17;
localparam WAIT_CNT = 15;
// Default set to TRUE because there can be a case where the ocal_rise_right_edge
// may not be detected if WRLVL stage2 tap value is large upto 63 and the initial
// DQS position is more than 225 degrees
localparam MINUS_32 = "TRUE";
localparam [4:0] OCAL_IDLE = 5'h00;
localparam [4:0] OCAL_NEW_DQS_WAIT = 5'h01;
localparam [4:0] OCAL_STG3_SEL = 5'h02;
localparam [4:0] OCAL_STG3_SEL_WAIT = 5'h03;
localparam [4:0] OCAL_STG3_EN_WAIT = 5'h04;
localparam [4:0] OCAL_STG3_DEC = 5'h05;
localparam [4:0] OCAL_STG3_WAIT = 5'h06;
localparam [4:0] OCAL_STG3_CALC = 5'h07;
localparam [4:0] OCAL_STG3_INC = 5'h08;
localparam [4:0] OCAL_STG3_INC_WAIT = 5'h09;
localparam [4:0] OCAL_STG2_SEL = 5'h0A;
localparam [4:0] OCAL_STG2_WAIT = 5'h0B;
localparam [4:0] OCAL_STG2_INC = 5'h0C;
localparam [4:0] OCAL_STG2_DEC = 5'h0D;
localparam [4:0] OCAL_STG2_DEC_WAIT = 5'h0E;
localparam [4:0] OCAL_NEXT_DQS = 5'h0F;
localparam [4:0] OCAL_NEW_DQS_READ = 5'h10;
localparam [4:0] OCAL_INC_DONE_WAIT = 5'h11;
localparam [4:0] OCAL_STG3_DEC_WAIT = 5'h12;
localparam [4:0] OCAL_DEC_DONE_WAIT = 5'h13;
localparam [4:0] OCAL_DONE = 5'h14;
integer i;
reg oclk_init_delay_start_r;
reg [3:0] count;
reg delay_done;
reg delay_done_r1;
reg delay_done_r2;
reg delay_done_r3;
reg delay_done_r4;
reg [5:0] delay_cnt_r;
reg po_stg3_dec;
wire [DQ_WIDTH-1:0] rd_data_rise0;
wire [DQ_WIDTH-1:0] rd_data_fall0;
wire [DQ_WIDTH-1:0] rd_data_rise1;
wire [DQ_WIDTH-1:0] rd_data_fall1;
wire [DQ_WIDTH-1:0] rd_data_rise2;
wire [DQ_WIDTH-1:0] rd_data_fall2;
wire [DQ_WIDTH-1:0] rd_data_rise3;
wire [DQ_WIDTH-1:0] rd_data_fall3;
reg [DQS_CNT_WIDTH:0] cnt_dqs_r;
wire [DQS_CNT_WIDTH+2:0] cnt_dqs_w;
reg [DQS_CNT_WIDTH:0] mux_sel_r;
reg [DRAM_WIDTH-1:0] sel_rd_rise0_r;
reg [DRAM_WIDTH-1:0] sel_rd_fall0_r;
reg [DRAM_WIDTH-1:0] sel_rd_rise1_r;
reg [DRAM_WIDTH-1:0] sel_rd_fall1_r;
reg [DRAM_WIDTH-1:0] sel_rd_rise2_r;
reg [DRAM_WIDTH-1:0] sel_rd_fall2_r;
reg [DRAM_WIDTH-1:0] sel_rd_rise3_r;
reg [DRAM_WIDTH-1:0] sel_rd_fall3_r;
reg [DRAM_WIDTH-1:0] prev_rd_rise0_r;
reg [DRAM_WIDTH-1:0] prev_rd_fall0_r;
reg [DRAM_WIDTH-1:0] prev_rd_rise1_r;
reg [DRAM_WIDTH-1:0] prev_rd_fall1_r;
reg [DRAM_WIDTH-1:0] prev_rd_rise2_r;
reg [DRAM_WIDTH-1:0] prev_rd_fall2_r;
reg [DRAM_WIDTH-1:0] prev_rd_rise3_r;
reg [DRAM_WIDTH-1:0] prev_rd_fall3_r;
reg rd_active_r;
reg rd_active_r1;
reg rd_active_r2;
reg rd_active_r3;
reg rd_active_r4;
reg [DRAM_WIDTH-1:0] pat_match_fall0_r;
reg pat_match_fall0_and_r;
reg [DRAM_WIDTH-1:0] pat_match_fall1_r;
reg pat_match_fall1_and_r;
reg [DRAM_WIDTH-1:0] pat_match_fall2_r;
reg pat_match_fall2_and_r;
reg [DRAM_WIDTH-1:0] pat_match_fall3_r;
reg pat_match_fall3_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise0_r;
reg pat_match_rise0_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise1_r;
reg pat_match_rise1_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise2_r;
reg pat_match_rise2_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise3_r;
reg pat_match_rise3_and_r;
reg pat_data_match_r;
reg pat_data_match_valid_r;
reg pat_data_match_valid_r1;
//reg [3:0] stable_stg3_cnt;
//reg stable_eye_r;
reg [3:0] stable_rise_stg3_cnt;
reg stable_rise_eye_r;
reg [3:0] stable_fall_stg3_cnt;
reg stable_fall_eye_r;
reg wait_cnt_en_r;
reg [3:0] wait_cnt_r;
reg cnt_next_state;
reg oclkdelay_calib_start_r;
reg [5:0] stg3_tap_cnt;
reg [5:0] stg3_incdec_limit;
reg stg3_dec2inc;
reg [5:0] stg2_tap_cnt;
reg [1:0] stg2_inc2_cnt;
reg [1:0] stg2_dec2_cnt;
reg [5:0] stg2_dec_cnt;
reg stg3_dec;
reg stg3_dec_r;
reg [4:0] ocal_state_r;
reg [5:0] ocal_final_cnt_r;
reg [5:0] ocal_inc_cnt;
reg [5:0] ocal_dec_cnt;
reg ocal_stg3_inc_en;
reg ocal_rise_edge1_found;
reg ocal_rise_edge2_found;
reg [5:0] ocal_rise_edge1_taps;
reg [5:0] ocal_rise_edge2_taps;
reg [5:0] ocal_rise_right_edge;
reg ocal_fall_edge1_found;
reg ocal_fall_edge2_found;
reg [5:0] ocal_fall_edge1_taps;
reg [5:0] ocal_fall_edge2_taps;
reg ocal_byte_done;
reg ocal_wrlvl_done;
reg ocal_wrlvl_done_r;
(* keep = "true", max_fanout = 10 *) reg ocal_done_r /* synthesis syn_maxfan = 10 */;
reg [5:0] ocal_tap_cnt_r[0:DQS_WIDTH-1];
reg prech_done_r;
reg rise_win;
reg fall_win;
// timing registers
reg stg3_tap_cnt_eq_oclkdelay_init_val;
reg stg3_tap_cnt_eq_0;
//reg stg3_tap_cnt_gt_20;
reg stg3_tap_cnt_eq_63;
reg stg3_tap_cnt_less_oclkdelay_init_val;
reg stg3_limit;
//**************************************************************************
// Debug signals
//**************************************************************************
genvar dqs_i;
generate
for (dqs_i=0; dqs_i < DQS_WIDTH; dqs_i = dqs_i + 1) begin: oclkdelay_tap_cnt
assign dbg_phy_oclkdelay_cal[6*dqs_i+:6] = ocal_tap_cnt_r[dqs_i][5:0];
end
endgenerate
assign dbg_phy_oclkdelay_cal[57:54] = cnt_dqs_r;
assign dbg_phy_oclkdelay_cal[58] = ocal_rise_edge1_found;
assign dbg_phy_oclkdelay_cal[59] = ocal_rise_edge2_found;
assign dbg_phy_oclkdelay_cal[65:60] = ocal_rise_edge1_taps;
assign dbg_phy_oclkdelay_cal[71:66] = ocal_rise_edge2_taps;
assign dbg_phy_oclkdelay_cal[76:72] = ocal_state_r;
assign dbg_phy_oclkdelay_cal[77] = pat_data_match_valid_r;
assign dbg_phy_oclkdelay_cal[78] = pat_data_match_r;
assign dbg_phy_oclkdelay_cal[84:79] = stg3_tap_cnt;
assign dbg_phy_oclkdelay_cal[88:85] = stable_rise_stg3_cnt;
assign dbg_phy_oclkdelay_cal[89] = stable_rise_eye_r;
assign dbg_phy_oclkdelay_cal[97:90] = prev_rd_rise0_r;
assign dbg_phy_oclkdelay_cal[105:98] = prev_rd_fall0_r;
assign dbg_phy_oclkdelay_cal[113:106] = prev_rd_rise1_r;
assign dbg_phy_oclkdelay_cal[121:114] = prev_rd_fall1_r;
assign dbg_phy_oclkdelay_cal[129:122] = prev_rd_rise2_r;
assign dbg_phy_oclkdelay_cal[137:130] = prev_rd_fall2_r;
assign dbg_phy_oclkdelay_cal[145:138] = prev_rd_rise3_r;
assign dbg_phy_oclkdelay_cal[153:146] = prev_rd_fall3_r;
assign dbg_phy_oclkdelay_cal[154] = rd_active_r;
assign dbg_phy_oclkdelay_cal[162:155] = sel_rd_rise0_r;
assign dbg_phy_oclkdelay_cal[170:163] = sel_rd_fall0_r;
assign dbg_phy_oclkdelay_cal[178:171] = sel_rd_rise1_r;
assign dbg_phy_oclkdelay_cal[186:179] = sel_rd_fall1_r;
assign dbg_phy_oclkdelay_cal[194:187] = sel_rd_rise2_r;
assign dbg_phy_oclkdelay_cal[202:195] = sel_rd_fall2_r;
assign dbg_phy_oclkdelay_cal[210:203] = sel_rd_rise3_r;
assign dbg_phy_oclkdelay_cal[218:211] = sel_rd_fall3_r;
assign dbg_phy_oclkdelay_cal[219+:6] = stg2_tap_cnt;
assign dbg_phy_oclkdelay_cal[225] = ocal_fall_edge1_found;
assign dbg_phy_oclkdelay_cal[226] = ocal_fall_edge2_found;
assign dbg_phy_oclkdelay_cal[232:227] = ocal_fall_edge1_taps;
assign dbg_phy_oclkdelay_cal[238:233] = ocal_fall_edge2_taps;
assign dbg_phy_oclkdelay_cal[244:239] = ocal_rise_right_edge;
assign dbg_phy_oclkdelay_cal[250:245] = 'd0;
assign dbg_phy_oclkdelay_cal[251] = stable_fall_eye_r;
assign dbg_phy_oclkdelay_cal[252] = rise_win;
assign dbg_phy_oclkdelay_cal[253] = fall_win;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*1 -1:0] = prev_rd_rise0_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*2 -1:DRAM_WIDTH*1] = prev_rd_fall0_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*3 -1:DRAM_WIDTH*2] = prev_rd_rise1_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*4 -1:DRAM_WIDTH*3] = prev_rd_fall1_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*5 -1:DRAM_WIDTH*4] = prev_rd_rise2_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*6 -1:DRAM_WIDTH*5] = prev_rd_fall2_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*7 -1:DRAM_WIDTH*6] = prev_rd_rise3_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*8 -1:DRAM_WIDTH*7] = prev_rd_fall3_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*9 -1:DRAM_WIDTH*8] = sel_rd_rise0_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*10 -1:DRAM_WIDTH*9] = sel_rd_fall0_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*11 -1:DRAM_WIDTH*10] = sel_rd_rise1_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*12 -1:DRAM_WIDTH*11] = sel_rd_fall1_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*13 -1:DRAM_WIDTH*12] = sel_rd_rise2_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*14 -1:DRAM_WIDTH*13] = sel_rd_fall2_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*15 -1:DRAM_WIDTH*14] = sel_rd_rise3_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*16 -1:DRAM_WIDTH*15] = sel_rd_fall3_r;
assign oclk_init_delay_done = ((SIM_CAL_OPTION == "FAST_CAL") || (DRAM_TYPE!="DDR3")) ? 1'b1 : delay_done_r4; //(SIM_CAL_OPTION != "NONE")
assign oclkdelay_calib_cnt = cnt_dqs_r;
assign oclkdelay_calib_done = (OCAL_EN == "ON") ? ocal_done_r : 1'b1;
assign cnt_dqs_w = {2'b00, cnt_dqs_r};
always @(posedge clk)
oclk_init_delay_start_r <= #TCQ oclk_init_delay_start;
always @(posedge clk) begin
if (rst || po_stg3_dec)
count <= #TCQ WAIT_CNT;
else if (oclk_init_delay_start && (count > 'd0))
count <= #TCQ count - 1;
end
always @(posedge clk) begin
if (rst || (delay_cnt_r == 'd0))
po_stg3_dec <= #TCQ 1'b0;
else if (count == 'd1)
po_stg3_dec <= #TCQ 1'b1;
else
po_stg3_dec <= #TCQ 1'b0;
end
//po_stg3_incdec and po_en_stg3 asserted for all data byte lanes
always @(posedge clk) begin
if (rst) begin
po_stg3_incdec <= #TCQ 1'b0;
po_en_stg3 <= #TCQ 1'b0;
end else if (po_stg3_dec) begin
po_stg3_incdec <= #TCQ 1'b0;
po_en_stg3 <= #TCQ 1'b1;
end else begin
po_stg3_incdec <= #TCQ 1'b0;
po_en_stg3 <= #TCQ 1'b0;
end
end
// delay counter to count TAP_CNT cycles
always @(posedge clk) begin
// load delay counter with init value of TAP_CNT
if (rst)
delay_cnt_r <= #TCQ TAP_CNT;
else if (po_stg3_dec && (delay_cnt_r > 6'd0))
delay_cnt_r <= #TCQ delay_cnt_r - 1;
end
// when all the ctl_lanes have their output phase shifted by 1/4 cycle, delay shifting is done.
always @(posedge clk) begin
if (rst) begin
delay_done <= #TCQ 1'b0;
end else if ((TAP_CNT == 6'd0) || ((delay_cnt_r == 6'd1) &&
(count == 'd1))) begin
delay_done <= #TCQ 1'b1;
end
end
always @(posedge clk) begin
delay_done_r1 <= #TCQ delay_done;
delay_done_r2 <= #TCQ delay_done_r1;
delay_done_r3 <= #TCQ delay_done_r2;
delay_done_r4 <= #TCQ delay_done_r3;
end
//**************************************************************************
// OCLKDELAY Calibration
//**************************************************************************
generate
if (nCK_PER_CLK == 4) begin: gen_rd_data_div4
assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];
assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH];
assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH];
assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH];
assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH];
end else if (nCK_PER_CLK == 2) begin: gen_rd_data_div2
assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];
assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
end
endgenerate
always @(posedge clk) begin
mux_sel_r <= #TCQ cnt_dqs_r;
oclkdelay_calib_start_r <= #TCQ oclkdelay_calib_start;
ocal_wrlvl_done_r <= #TCQ ocal_wrlvl_done;
rd_active_r <= #TCQ phy_rddata_en;
rd_active_r1 <= #TCQ rd_active_r;
rd_active_r2 <= #TCQ rd_active_r1;
rd_active_r3 <= #TCQ rd_active_r2;
rd_active_r4 <= #TCQ rd_active_r3;
stg3_dec_r <= #TCQ stg3_dec;
end
// Register outputs for improved timing.
// All bits in selected DQS group are checked in aggregate
generate
genvar mux_j;
for (mux_j = 0; mux_j < DRAM_WIDTH; mux_j = mux_j + 1) begin: gen_mux_rd
always @(posedge clk) begin
if (phy_rddata_en) begin
sel_rd_rise0_r[mux_j] <= #TCQ rd_data_rise0[DRAM_WIDTH*mux_sel_r +
mux_j];
sel_rd_fall0_r[mux_j] <= #TCQ rd_data_fall0[DRAM_WIDTH*mux_sel_r +
mux_j];
sel_rd_rise1_r[mux_j] <= #TCQ rd_data_rise1[DRAM_WIDTH*mux_sel_r +
mux_j];
sel_rd_fall1_r[mux_j] <= #TCQ rd_data_fall1[DRAM_WIDTH*mux_sel_r +
mux_j];
sel_rd_rise2_r[mux_j] <= #TCQ rd_data_rise2[DRAM_WIDTH*mux_sel_r +
mux_j];
sel_rd_fall2_r[mux_j] <= #TCQ rd_data_fall2[DRAM_WIDTH*mux_sel_r +
mux_j];
sel_rd_rise3_r[mux_j] <= #TCQ rd_data_rise3[DRAM_WIDTH*mux_sel_r +
mux_j];
sel_rd_fall3_r[mux_j] <= #TCQ rd_data_fall3[DRAM_WIDTH*mux_sel_r +
mux_j];
end
end
end
endgenerate
always @(posedge clk)
if (((stg3_tap_cnt_eq_oclkdelay_init_val) && rd_active_r) |
rd_active_r4) begin
prev_rd_rise0_r <= #TCQ sel_rd_rise0_r;
prev_rd_fall0_r <= #TCQ sel_rd_fall0_r;
prev_rd_rise1_r <= #TCQ sel_rd_rise1_r;
prev_rd_fall1_r <= #TCQ sel_rd_fall1_r;
prev_rd_rise2_r <= #TCQ sel_rd_rise2_r;
prev_rd_fall2_r <= #TCQ sel_rd_fall2_r;
prev_rd_rise3_r <= #TCQ sel_rd_rise3_r;
prev_rd_fall3_r <= #TCQ sel_rd_fall3_r;
end
// Each bit of each byte is compared with previous data to
// detect an edge
generate
genvar pt_j;
if (nCK_PER_CLK == 4) begin: gen_pat_match_div4
always @(posedge clk) begin
if (rd_active_r) begin
rise_win <= #TCQ (|sel_rd_rise0_r | |sel_rd_rise1_r | |sel_rd_rise2_r | |sel_rd_rise3_r);
fall_win <= #TCQ (&sel_rd_rise0_r & &sel_rd_rise1_r & &sel_rd_rise2_r & &sel_rd_rise3_r);
end
end
for (pt_j = 0; pt_j < DRAM_WIDTH; pt_j = pt_j + 1) begin: gen_pat_match
always @(posedge clk) begin
if (sel_rd_rise0_r[pt_j] == prev_rd_rise0_r[pt_j])
pat_match_rise0_r[pt_j] <= #TCQ 1'b1;
else
pat_match_rise0_r[pt_j] <= #TCQ 1'b0;
if (sel_rd_fall0_r[pt_j] == prev_rd_fall0_r[pt_j])
pat_match_fall0_r[pt_j] <= #TCQ 1'b1;
else
pat_match_fall0_r[pt_j] <= #TCQ 1'b0;
if (sel_rd_rise1_r[pt_j] == prev_rd_rise1_r[pt_j])
pat_match_rise1_r[pt_j] <= #TCQ 1'b1;
else
pat_match_rise1_r[pt_j] <= #TCQ 1'b0;
if (sel_rd_fall1_r[pt_j] == prev_rd_fall1_r[pt_j])
pat_match_fall1_r[pt_j] <= #TCQ 1'b1;
else
pat_match_fall1_r[pt_j] <= #TCQ 1'b0;
if (sel_rd_rise2_r[pt_j] == prev_rd_rise2_r[pt_j])
pat_match_rise2_r[pt_j] <= #TCQ 1'b1;
else
pat_match_rise2_r[pt_j] <= #TCQ 1'b0;
if (sel_rd_fall2_r[pt_j] == prev_rd_fall2_r[pt_j])
pat_match_fall2_r[pt_j] <= #TCQ 1'b1;
else
pat_match_fall2_r[pt_j] <= #TCQ 1'b0;
if (sel_rd_rise3_r[pt_j] == prev_rd_rise3_r[pt_j])
pat_match_rise3_r[pt_j] <= #TCQ 1'b1;
else
pat_match_rise3_r[pt_j] <= #TCQ 1'b0;
if (sel_rd_fall3_r[pt_j] == prev_rd_fall3_r[pt_j])
pat_match_fall3_r[pt_j] <= #TCQ 1'b1;
else
pat_match_fall3_r[pt_j] <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
pat_match_rise0_and_r <= #TCQ &pat_match_rise0_r;
pat_match_fall0_and_r <= #TCQ &pat_match_fall0_r;
pat_match_rise1_and_r <= #TCQ &pat_match_rise1_r;
pat_match_fall1_and_r <= #TCQ &pat_match_fall1_r;
pat_match_rise2_and_r <= #TCQ &pat_match_rise2_r;
pat_match_fall2_and_r <= #TCQ &pat_match_fall2_r;
pat_match_rise3_and_r <= #TCQ &pat_match_rise3_r;
pat_match_fall3_and_r <= #TCQ &pat_match_fall3_r;
pat_data_match_r <= #TCQ (//pat_match_rise0_and_r &&
//pat_match_fall0_and_r &&
pat_match_rise1_and_r &&
pat_match_fall1_and_r &&
pat_match_rise2_and_r &&
pat_match_fall2_and_r &&
pat_match_rise3_and_r &&
pat_match_fall3_and_r);
pat_data_match_valid_r <= #TCQ rd_active_r2;
end
always @(posedge clk) begin
pat_data_match_valid_r1 <= #TCQ pat_data_match_valid_r;
end
end else if (nCK_PER_CLK == 2) begin: gen_pat_match_div2
always @(posedge clk) begin
if (rd_active_r) begin
rise_win <= #TCQ (|sel_rd_rise0_r | |sel_rd_rise1_r);
fall_win <= #TCQ (&sel_rd_rise0_r & &sel_rd_rise1_r);
end
end
for (pt_j = 0; pt_j < DRAM_WIDTH; pt_j = pt_j + 1) begin: gen_pat_match
always @(posedge clk) begin
if (sel_rd_rise0_r[pt_j] == prev_rd_rise0_r[pt_j])
pat_match_rise0_r[pt_j] <= #TCQ 1'b1;
else
pat_match_rise0_r[pt_j] <= #TCQ 1'b0;
if (sel_rd_fall0_r[pt_j] == prev_rd_fall0_r[pt_j])
pat_match_fall0_r[pt_j] <= #TCQ 1'b1;
else
pat_match_fall0_r[pt_j] <= #TCQ 1'b0;
if (sel_rd_rise1_r[pt_j] == prev_rd_rise1_r[pt_j])
pat_match_rise1_r[pt_j] <= #TCQ 1'b1;
else
pat_match_rise1_r[pt_j] <= #TCQ 1'b0;
if (sel_rd_fall1_r[pt_j] == prev_rd_fall1_r[pt_j])
pat_match_fall1_r[pt_j] <= #TCQ 1'b1;
else
pat_match_fall1_r[pt_j] <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
pat_match_rise0_and_r <= #TCQ &pat_match_rise0_r;
pat_match_fall0_and_r <= #TCQ &pat_match_fall0_r;
pat_match_rise1_and_r <= #TCQ &pat_match_rise1_r;
pat_match_fall1_and_r <= #TCQ &pat_match_fall1_r;
pat_data_match_r <= #TCQ (//pat_match_rise0_and_r &&
//pat_match_fall0_and_r &&
pat_match_rise1_and_r &&
pat_match_fall1_and_r);
pat_data_match_valid_r <= #TCQ rd_active_r2;
end
always @(posedge clk) begin
pat_data_match_valid_r1 <= #TCQ pat_data_match_valid_r;
end
end
endgenerate
// Stable count of 16 PO Stage3 taps at 2x the resolution of stage2 taps
// Required to inhibit false edge detection due to clock jitter
always @(posedge clk)begin
if (rst | (pat_data_match_valid_r & ~pat_data_match_r &
(ocal_state_r == OCAL_NEW_DQS_WAIT)) |
(ocal_state_r == OCAL_STG3_CALC))
stable_rise_stg3_cnt <= #TCQ 'd0;
else if ((!stg3_tap_cnt_eq_oclkdelay_init_val) &
pat_data_match_valid_r & pat_data_match_r &
(ocal_state_r == OCAL_NEW_DQS_WAIT) &
(stable_rise_stg3_cnt < 'd8) & ~rise_win)
stable_rise_stg3_cnt <= #TCQ stable_rise_stg3_cnt + 1;
end
always @(posedge clk) begin
if (rst | (stable_rise_stg3_cnt != 'd8))
stable_rise_eye_r <= #TCQ 1'b0;
else if (stable_rise_stg3_cnt == 'd8)
stable_rise_eye_r <= #TCQ 1'b1;
end
always @(posedge clk)begin
if (rst | (pat_data_match_valid_r & ~pat_data_match_r &
(ocal_state_r == OCAL_NEW_DQS_WAIT)) |
(ocal_state_r == OCAL_STG3_CALC))
stable_fall_stg3_cnt <= #TCQ 'd0;
else if ((!stg3_tap_cnt_eq_oclkdelay_init_val) &
pat_data_match_valid_r & pat_data_match_r &
(ocal_state_r == OCAL_NEW_DQS_WAIT) &
(stable_fall_stg3_cnt < 'd8) & fall_win)
stable_fall_stg3_cnt <= #TCQ stable_fall_stg3_cnt + 1;
end
always @(posedge clk) begin
if (rst | (stable_fall_stg3_cnt != 'd8))
stable_fall_eye_r <= #TCQ 1'b0;
else if (stable_fall_stg3_cnt == 'd8)
stable_fall_eye_r <= #TCQ 1'b1;
end
always @(posedge clk)
if ((ocal_state_r == OCAL_STG3_SEL_WAIT) ||
(ocal_state_r == OCAL_STG3_EN_WAIT) ||
(ocal_state_r == OCAL_STG3_WAIT) ||
(ocal_state_r == OCAL_STG3_INC_WAIT) ||
(ocal_state_r == OCAL_STG3_DEC_WAIT) ||
(ocal_state_r == OCAL_STG2_WAIT) ||
(ocal_state_r == OCAL_STG2_DEC_WAIT) ||
(ocal_state_r == OCAL_INC_DONE_WAIT) ||
(ocal_state_r == OCAL_DEC_DONE_WAIT))
wait_cnt_en_r <= #TCQ 1'b1;
else
wait_cnt_en_r <= #TCQ 1'b0;
always @(posedge clk)
if (!wait_cnt_en_r) begin
wait_cnt_r <= #TCQ 'b0;
cnt_next_state <= #TCQ 1'b0;
end else begin
if (wait_cnt_r != WAIT_CNT - 1) begin
wait_cnt_r <= #TCQ wait_cnt_r + 1;
cnt_next_state <= #TCQ 1'b0;
end else begin
// Need to reset to 0 to handle the case when there are two
// different WAIT states back-to-back
wait_cnt_r <= #TCQ 'b0;
cnt_next_state <= #TCQ 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
for (i=0; i < DQS_WIDTH; i = i + 1) begin: rst_ocal_tap_cnt
ocal_tap_cnt_r[i] <= #TCQ 'b0;
end
end else if (stg3_dec_r && ~stg3_dec)
ocal_tap_cnt_r[cnt_dqs_r][5:0] <= #TCQ stg3_tap_cnt;
end
always @(posedge clk) begin
if (rst || (ocal_state_r == OCAL_NEW_DQS_READ) ||
(ocal_state_r == OCAL_STG3_CALC) ||
(ocal_state_r == OCAL_DONE))
prech_done_r <= #TCQ 1'b0;
else if (prech_done)
prech_done_r <= #TCQ 1'b1;
end
// setting stg3_tap_cnt == oclkdelay_int_val
always @(posedge clk) begin
if (rst || (ocal_state_r == OCAL_NEXT_DQS)) begin
stg3_tap_cnt_eq_oclkdelay_init_val <= #TCQ 1'b1;
end else begin
if (ocal_state_r == OCAL_DONE)
stg3_tap_cnt_eq_oclkdelay_init_val <= #TCQ 1'b0;
else if (ocal_state_r == OCAL_STG3_DEC)
stg3_tap_cnt_eq_oclkdelay_init_val <= #TCQ (stg3_tap_cnt == oclkdelay_init_val+1);
else if (ocal_state_r == OCAL_STG3_INC)
stg3_tap_cnt_eq_oclkdelay_init_val <= #TCQ (stg3_tap_cnt == oclkdelay_init_val-1);
end // else: !if((rst || (ocal_state_r == OCAL_IDLE)) begin...
end // always @ (posedge clk)
// setting sg3_tap_cng > 20
// always @(posedge clk) begin
// if ((rst)|| (ocal_state_r == OCAL_NEXT_DQS)) begin
// stg3_tap_cnt_gt_20 <= #TCQ 1'b0;
// end else begin // if (rst)
// if (ocal_state_r == OCAL_STG3_DEC)
// stg3_tap_cnt_gt_20 <= #TCQ (stg3_tap_cnt >= 'd22);
// else if (ocal_state_r == OCAL_STG3_INC)
// stg3_tap_cnt_gt_20 <= #TCQ (stg3_tap_cnt >= 'd20);
// end // else: !if((rst || (ocal_state_r == OCAL_IDLE)) begin...
// end // always @ (posedge clk)
// setting sg3_tap_cnt == 0
always @(posedge clk) begin
if ((rst)|| (ocal_state_r == OCAL_NEXT_DQS) || (ocal_state_r == OCAL_STG3_INC) ) begin
stg3_tap_cnt_eq_0 <= #TCQ 1'b0;
end else begin // if (rst)
if (ocal_state_r == OCAL_STG3_DEC)
stg3_tap_cnt_eq_0 <= #TCQ (stg3_tap_cnt == 'd1);
end // else: !if((rst || (ocal_state_r == OCAL_IDLE)) begin...
end // always @ (posedge clk)
// setting sg3_tap_cnt == 63
always @(posedge clk) begin
if ((rst)|| (ocal_state_r == OCAL_NEXT_DQS)) begin
stg3_tap_cnt_eq_63 <= #TCQ 1'b0;
end else begin // if (rst)
if (ocal_state_r == OCAL_STG3_INC)
stg3_tap_cnt_eq_63 <= #TCQ (stg3_tap_cnt >= 'd62);
else if (ocal_state_r == OCAL_STG3_DEC)
stg3_tap_cnt_eq_63 <= #TCQ 1'b0;
end // else: !if((rst || (ocal_state_r == OCAL_IDLE)) begin...
end // always @ (posedge clk)
// setting sg3_tap_cnt < ocaldelay_init_val
always @(posedge clk) begin
if ((rst)|| (ocal_state_r == OCAL_NEXT_DQS)) begin
stg3_tap_cnt_less_oclkdelay_init_val <= #TCQ 1'b0;
end else begin // if (rst)
if (ocal_state_r == OCAL_STG3_DEC)
stg3_tap_cnt_less_oclkdelay_init_val <= #TCQ (stg3_tap_cnt <= oclkdelay_init_val);
else if (ocal_state_r == OCAL_STG3_INC)
stg3_tap_cnt_less_oclkdelay_init_val <= #TCQ (stg3_tap_cnt <= oclkdelay_init_val-2);
end // else: !if((rst || (ocal_state_r == OCAL_IDLE)) begin...
end // always @ (posedge clk)
// setting stg3_incdec_limit == 15
always @(posedge clk) begin
if (rst || (ocal_state_r == OCAL_NEXT_DQS) || (ocal_state_r == OCAL_DONE)) begin
stg3_limit <= #TCQ 1'b0;
end else if ((ocal_state_r == OCAL_STG3_WAIT) || (ocal_state_r == OCAL_STG2_WAIT)) begin
stg3_limit <= #TCQ (stg3_incdec_limit == 'd14);
end
end
// State Machine
always @(posedge clk) begin
if (rst) begin
ocal_state_r <= #TCQ OCAL_IDLE;
cnt_dqs_r <= #TCQ 'd0;
stg3_tap_cnt <= #TCQ oclkdelay_init_val;
stg3_incdec_limit <= #TCQ 'd0;
stg3_dec2inc <= #TCQ 1'b0;
stg2_tap_cnt <= #TCQ 'd0;
stg2_inc2_cnt <= #TCQ 2'b00;
stg2_dec2_cnt <= #TCQ 2'b00;
stg2_dec_cnt <= #TCQ 'd0;
stg3_dec <= #TCQ 1'b0;
wrlvl_final <= #TCQ 1'b0;
oclk_calib_resume <= #TCQ 1'b0;
oclk_prech_req <= #TCQ 1'b0;
ocal_final_cnt_r <= #TCQ 'd0;
ocal_inc_cnt <= #TCQ 'd0;
ocal_dec_cnt <= #TCQ 'd0;
ocal_stg3_inc_en <= #TCQ 1'b0;
ocal_rise_edge1_found <= #TCQ 1'b0;
ocal_rise_edge2_found <= #TCQ 1'b0;
ocal_rise_right_edge <= #TCQ 'd0;
ocal_rise_edge1_taps <= #TCQ 'd0;
ocal_rise_edge2_taps <= #TCQ 'd0;
ocal_fall_edge1_found <= #TCQ 1'b0;
ocal_fall_edge2_found <= #TCQ 1'b0;
ocal_fall_edge1_taps <= #TCQ 'd0;
ocal_fall_edge2_taps <= #TCQ 'd0;
ocal_byte_done <= #TCQ 1'b0;
ocal_wrlvl_done <= #TCQ 1'b0;
ocal_if_rst <= #TCQ 1'b0;
ocal_done_r <= #TCQ 1'b0;
po_stg23_sel <= #TCQ 1'b0;
po_en_stg23 <= #TCQ 1'b0;
po_stg23_incdec <= #TCQ 1'b0;
end else begin
case (ocal_state_r)
OCAL_IDLE: begin
if (oclkdelay_calib_start && ~oclkdelay_calib_start_r) begin
ocal_state_r <= #TCQ OCAL_NEW_DQS_WAIT;
stg3_tap_cnt <= #TCQ oclkdelay_init_val;
stg2_tap_cnt <= #TCQ wl_po_fine_cnt[((cnt_dqs_w << 2) +
(cnt_dqs_w << 1))+:6];
end
end
OCAL_NEW_DQS_READ: begin
oclk_prech_req <= #TCQ 1'b0;
oclk_calib_resume <= #TCQ 1'b0;
if (pat_data_match_valid_r)
ocal_state_r <= #TCQ OCAL_NEW_DQS_WAIT;
end
OCAL_NEW_DQS_WAIT: begin
oclk_calib_resume <= #TCQ 1'b0;
oclk_prech_req <= #TCQ 1'b0;
po_en_stg23 <= #TCQ 1'b0;
po_stg23_incdec <= #TCQ 1'b0;
if (pat_data_match_valid_r && !stg3_tap_cnt_eq_oclkdelay_init_val) begin
if ((stg3_limit && ~ocal_stg3_inc_en) ||
stg3_tap_cnt == 'd0) begin
// No write levling performed to avoid stage 2 coarse dec.
// Therefore stage 3 taps can only be decremented by an
// additional 15 taps after stage 2 taps reach 63.
ocal_state_r <= #TCQ OCAL_STG3_SEL;
ocal_stg3_inc_en <= #TCQ 1'b1;
stg3_incdec_limit <= #TCQ 'd0;
// An edge was detected
end else if (~pat_data_match_r) begin
// Sticky bit - asserted after we encounter an edge, although
// the current edge may not be considered the "first edge" this
// just means we found at least one edge
if (~ocal_stg3_inc_en) begin
if (|stable_fall_stg3_cnt && ~ocal_fall_edge1_found) begin
ocal_fall_edge1_found <= #TCQ 1'b1;
ocal_fall_edge1_taps <= #TCQ stg3_tap_cnt + 1;
end else
ocal_rise_edge1_found <= #TCQ 1'b1;
end
// Sarting point was in the jitter region close to the right edge
if (~stable_rise_eye_r && ~ocal_stg3_inc_en) begin
ocal_rise_right_edge <= #TCQ stg3_tap_cnt;
ocal_state_r <= #TCQ OCAL_STG3_SEL;
// Starting point was in the valid window close to the right edge
// Or away from the right edge hence no stable_eye_r condition
// Or starting point was in the right jitter region and ocal_rise_right_edge
// is detected
end else if (ocal_stg3_inc_en) begin
// Both edges found
if (stable_fall_eye_r) begin
ocal_state_r <= #TCQ OCAL_STG3_CALC;
ocal_fall_edge2_found <= #TCQ 1'b1;
ocal_fall_edge2_taps <= #TCQ stg3_tap_cnt - 1;
end else begin
ocal_state_r <= #TCQ OCAL_STG3_CALC;
ocal_rise_edge2_found <= #TCQ 1'b1;
ocal_rise_edge2_taps <= #TCQ stg3_tap_cnt - 1;
end
// Starting point in the valid window away from left edge
// Assuming starting point will not be in valid window close to
// left edge
end else if (stable_rise_eye_r) begin
ocal_rise_edge1_taps <= #TCQ stg3_tap_cnt + 1;
ocal_state_r <= #TCQ OCAL_STG3_SEL;
ocal_stg3_inc_en <= #TCQ 1'b1;
stg3_incdec_limit <= #TCQ 'd0;
end else
ocal_state_r <= #TCQ OCAL_STG3_SEL;
end else
ocal_state_r <= #TCQ OCAL_STG3_SEL;
end else if (stg3_tap_cnt_eq_oclkdelay_init_val)
ocal_state_r <= #TCQ OCAL_STG3_SEL;
else if ((stg3_limit && ocal_stg3_inc_en) ||
(stg3_tap_cnt_eq_63)) begin
ocal_state_r <= #TCQ OCAL_STG3_CALC;
stg3_incdec_limit <= #TCQ 'd0;
end
end
OCAL_STG3_SEL: begin
po_stg23_sel <= #TCQ 1'b1;
ocal_wrlvl_done <= #TCQ 1'b0;
ocal_state_r <= #TCQ OCAL_STG3_SEL_WAIT;
end
OCAL_STG3_SEL_WAIT: begin
if (cnt_next_state) begin
ocal_state_r <= #TCQ OCAL_STG3_EN_WAIT;
if (ocal_stg3_inc_en) begin
po_stg23_incdec <= #TCQ 1'b1;
if (stg3_tap_cnt_less_oclkdelay_init_val) begin
ocal_inc_cnt <= #TCQ oclkdelay_init_val - stg3_tap_cnt;
stg3_dec2inc <= #TCQ 1'b1;
oclk_prech_req <= #TCQ 1'b1;
end
end else begin
po_stg23_incdec <= #TCQ 1'b0;
if (stg3_dec)
ocal_dec_cnt <= #TCQ ocal_final_cnt_r;
end
end
end
OCAL_STG3_EN_WAIT: begin
if (cnt_next_state) begin
if (ocal_stg3_inc_en)
ocal_state_r <= #TCQ OCAL_STG3_INC;
else
ocal_state_r <= #TCQ OCAL_STG3_DEC;
end
end
OCAL_STG3_DEC: begin
po_en_stg23 <= #TCQ 1'b1;
stg3_tap_cnt <= #TCQ stg3_tap_cnt - 1;
if (ocal_dec_cnt == 1) begin
ocal_byte_done <= #TCQ 1'b1;
ocal_state_r <= #TCQ OCAL_DEC_DONE_WAIT;
ocal_dec_cnt <= #TCQ ocal_dec_cnt - 1;
end else if (ocal_dec_cnt > 'd0) begin
ocal_state_r <= #TCQ OCAL_STG3_DEC_WAIT;
ocal_dec_cnt <= #TCQ ocal_dec_cnt - 1;
end else
ocal_state_r <= #TCQ OCAL_STG3_WAIT;
end
OCAL_STG3_DEC_WAIT: begin
po_en_stg23 <= #TCQ 1'b0;
if (cnt_next_state) begin
if (ocal_dec_cnt > 'd0)
ocal_state_r <= #TCQ OCAL_STG3_DEC;
else
ocal_state_r <= #TCQ OCAL_DEC_DONE_WAIT;
end
end
OCAL_DEC_DONE_WAIT: begin
// Required to make sure that po_stg23_incdec
// de-asserts some time after de-assertion of
// po_en_stg23
po_en_stg23 <= #TCQ 1'b0;
if (cnt_next_state) begin
// Final stage 3 decrement completed, proceed
// to stage 2 tap decrement
ocal_state_r <= #TCQ OCAL_STG2_SEL;
po_stg23_incdec <= #TCQ 1'b0;
stg3_dec <= #TCQ 1'b0;
end
end
OCAL_STG3_WAIT: begin
po_en_stg23 <= #TCQ 1'b0;
if (cnt_next_state) begin
po_stg23_incdec <= #TCQ 1'b0;
if ((stg2_tap_cnt != 6'd63) || (stg2_tap_cnt != 6'd0))
ocal_state_r <= #TCQ OCAL_STG2_SEL;
else begin
oclk_calib_resume <= #TCQ 1'b1;
ocal_state_r <= #TCQ OCAL_NEW_DQS_WAIT;
stg3_incdec_limit <= #TCQ stg3_incdec_limit + 1;
end
end
end
OCAL_STG2_SEL: begin
po_stg23_sel <= #TCQ 1'b0;
po_en_stg23 <= #TCQ 1'b0;
po_stg23_incdec <= #TCQ 1'b0;
ocal_state_r <= #TCQ OCAL_STG2_WAIT;
stg2_inc2_cnt <= #TCQ 2'b01;
stg2_dec2_cnt <= #TCQ 2'b01;
end
OCAL_STG2_WAIT: begin
po_en_stg23 <= #TCQ 1'b0;
po_stg23_incdec <= #TCQ 1'b0;
if (cnt_next_state) begin
if (ocal_byte_done) begin
if (stg2_tap_cnt > 'd0) begin
// Decrement stage 2 taps to '0' before
// final write level is performed
ocal_state_r <= #TCQ OCAL_STG2_DEC;
stg2_dec_cnt <= #TCQ stg2_tap_cnt;
end else begin
ocal_state_r <= #TCQ OCAL_NEXT_DQS;
ocal_byte_done <= #TCQ 1'b0;
end
end else if (stg3_dec2inc && (stg2_tap_cnt > 'd0)) begin
// Decrement stage 2 tap to initial value before
// edge 2 detection begins
ocal_state_r <= #TCQ OCAL_STG2_DEC;
stg2_dec_cnt <= #TCQ stg2_tap_cnt -
wl_po_fine_cnt[((cnt_dqs_w << 2) +
(cnt_dqs_w << 1))+:6];
end else if (~ocal_stg3_inc_en && (stg2_tap_cnt < 6'd63)) begin
// Increment stage 2 taps by 2 for every stage 3 tap decrement
// as part of edge 1 detection to avoid tDQSS violation between
// write DQS and CK
ocal_state_r <= #TCQ OCAL_STG2_INC;
end else if (ocal_stg3_inc_en && (stg2_tap_cnt > 6'd0)) begin
// Decrement stage 2 taps by 2 for every stage 3 tap increment
// as part of edge 2 detection to avoid tDQSS violation between
// write DQS and CK
ocal_state_r <= #TCQ OCAL_STG2_DEC;
end else begin
oclk_calib_resume <= #TCQ 1'b1;
ocal_state_r <= #TCQ OCAL_NEW_DQS_WAIT;
stg3_incdec_limit <= #TCQ stg3_incdec_limit + 1;
end
end
end
OCAL_STG2_INC: begin
po_en_stg23 <= #TCQ 1'b1;
po_stg23_incdec <= #TCQ 1'b1;
stg2_tap_cnt <= #TCQ stg2_tap_cnt + 1;
if (stg2_inc2_cnt > 2'b00) begin
stg2_inc2_cnt <= stg2_inc2_cnt - 1;
ocal_state_r <= #TCQ OCAL_STG2_WAIT;
end else if (stg2_tap_cnt == 6'd62) begin
ocal_state_r <= #TCQ OCAL_STG2_WAIT;
end else begin
oclk_calib_resume <= #TCQ 1'b1;
ocal_state_r <= #TCQ OCAL_NEW_DQS_WAIT;
end
end
OCAL_STG2_DEC: begin
po_en_stg23 <= #TCQ 1'b1;
po_stg23_incdec <= #TCQ 1'b0;
stg2_tap_cnt <= #TCQ stg2_tap_cnt - 1;
if (stg2_dec_cnt > 6'd0) begin
stg2_dec_cnt <= #TCQ stg2_dec_cnt - 1;
ocal_state_r <= #TCQ OCAL_STG2_DEC_WAIT;
end else if (stg2_dec2_cnt > 2'b00) begin
stg2_dec2_cnt <= stg2_dec2_cnt - 1;
ocal_state_r <= #TCQ OCAL_STG2_WAIT;
end else if (stg2_tap_cnt == 6'd1)
ocal_state_r <= #TCQ OCAL_STG2_WAIT;
else begin
oclk_calib_resume <= #TCQ 1'b1;
ocal_state_r <= #TCQ OCAL_NEW_DQS_WAIT;
end
end
OCAL_STG2_DEC_WAIT: begin
po_en_stg23 <= #TCQ 1'b0;
po_stg23_incdec <= #TCQ 1'b0;
if (cnt_next_state) begin
if (stg2_dec_cnt > 6'd0) begin
ocal_state_r <= #TCQ OCAL_STG2_DEC;
end else if (ocal_byte_done) begin
ocal_state_r <= #TCQ OCAL_NEXT_DQS;
ocal_byte_done <= #TCQ 1'b0;
end else if (prech_done_r && stg3_dec2inc) begin
stg3_dec2inc <= #TCQ 1'b0;
if (stg3_tap_cnt_eq_63)
ocal_state_r <= #TCQ OCAL_STG3_CALC;
else begin
ocal_state_r <= #TCQ OCAL_NEW_DQS_READ;
oclk_calib_resume <= #TCQ 1'b1;
end
end
end
end
OCAL_STG3_CALC: begin
// ocal_rise_right_edge is asserted when an edge is detected
// with both stable_rise_eye_r and stabe_fall_eye_r de-asserted
if (|ocal_rise_right_edge) begin
if (ocal_fall_edge2_found && ocal_fall_edge1_found) begin
if (MINUS_32 == "TRUE")
ocal_final_cnt_r <= #TCQ ((ocal_fall_edge2_taps - ocal_fall_edge1_taps)>>1) + 1 + 32;
else
ocal_final_cnt_r <= #TCQ ((ocal_fall_edge2_taps - ocal_fall_edge1_taps)>>1) +
(stg3_tap_cnt - ocal_rise_right_edge);
end else
ocal_final_cnt_r
<= #TCQ ((ocal_rise_right_edge - ocal_rise_edge1_taps)>>1) +
(stg3_tap_cnt - ocal_rise_right_edge);
// Both rise window edges found. The left edge is the first
// edge since taps are decremented first from initial tap value
// and then incremented until second edge or 63 taps
end else if (ocal_rise_edge2_found && ocal_rise_edge1_found)
ocal_final_cnt_r
<= #TCQ ((ocal_rise_edge2_taps -
ocal_rise_edge1_taps)>>1) + 1;
else if (ocal_rise_edge2_found && ~ocal_rise_edge1_found)
// This case is possible if either write level stg2
// tap values are very large resulting in minimal
// stage3 tap decrements
// Or if initial DQS is very close to the right edge
ocal_final_cnt_r
<= #TCQ (ocal_rise_edge2_taps>>1) + 1;
else if (~ocal_rise_edge2_found && ocal_rise_edge1_found)
// This case is possible if write level stg2
// tap values are very small resulting in minimal
// stage3 tap increments
ocal_final_cnt_r
<= #TCQ ((stg3_tap_cnt - ocal_rise_edge1_taps)>>1);
else if (ocal_fall_edge2_found && ocal_fall_edge1_found)
ocal_final_cnt_r <= #TCQ ((ocal_fall_edge2_taps - ocal_fall_edge1_taps)>>1) + 1 + 32;
ocal_state_r <= #TCQ OCAL_STG3_SEL;
stg3_dec <= #TCQ 1'b1;
//end
ocal_stg3_inc_en <= #TCQ 1'b0;
end
OCAL_STG3_INC: begin
po_en_stg23 <= #TCQ 1'b1;
stg3_tap_cnt <= #TCQ stg3_tap_cnt + 1;
if (ocal_inc_cnt > 'd0)
ocal_inc_cnt <= #TCQ ocal_inc_cnt - 1;
if (ocal_inc_cnt == 1)
ocal_state_r <= #TCQ OCAL_INC_DONE_WAIT;
else
ocal_state_r <= #TCQ OCAL_STG3_INC_WAIT;
end
OCAL_STG3_INC_WAIT: begin
po_en_stg23 <= #TCQ 1'b0;
po_stg23_incdec <= #TCQ 1'b1;
if (cnt_next_state) begin
if (ocal_inc_cnt > 'd0)
ocal_state_r <= #TCQ OCAL_STG3_INC;
else begin
ocal_state_r <= #TCQ OCAL_STG2_SEL;
po_stg23_incdec <= #TCQ 1'b0;
end
end
end
OCAL_INC_DONE_WAIT: begin
// Required to make sure that po_stg23_incdec
// de-asserts some time after de-assertion of
// po_en_stg23
po_en_stg23 <= #TCQ 1'b0;
oclk_prech_req <= #TCQ 1'b0;
if (cnt_next_state) begin
ocal_state_r <= #TCQ OCAL_STG2_SEL;
po_stg23_incdec <= #TCQ 1'b0;
end
end
OCAL_NEXT_DQS: begin
po_en_stg23 <= #TCQ 1'b0;
po_stg23_incdec <= #TCQ 1'b0;
stg3_tap_cnt <= #TCQ 6'd0;
ocal_rise_edge1_found <= #TCQ 1'b0;
ocal_rise_edge2_found <= #TCQ 1'b0;
ocal_rise_edge1_taps <= #TCQ 'd0;
ocal_rise_edge2_taps <= #TCQ 'd0;
ocal_rise_right_edge <= #TCQ 'd0;
ocal_fall_edge1_found <= #TCQ 1'b0;
ocal_fall_edge2_found <= #TCQ 1'b0;
ocal_fall_edge1_taps <= #TCQ 'd0;
ocal_fall_edge2_taps <= #TCQ 'd0;
ocal_final_cnt_r <= #TCQ 'd0;
stg3_incdec_limit <= #TCQ 'd0;
oclk_prech_req <= #TCQ 1'b1;
if (cnt_dqs_r == DQS_WIDTH-1)
wrlvl_final <= #TCQ 1'b1;
if (prech_done) begin
if (cnt_dqs_r == DQS_WIDTH-1)
// If the last DQS group was just finished,
// then end of calibration
ocal_state_r <= #TCQ OCAL_DONE;
else begin
// Continue to next DQS group
cnt_dqs_r <= #TCQ cnt_dqs_r + 1;
ocal_state_r <= #TCQ OCAL_NEW_DQS_READ;
stg3_tap_cnt <= #TCQ oclkdelay_init_val;
stg2_tap_cnt <= #TCQ wl_po_fine_cnt[(((cnt_dqs_w+1) << 2) +
((cnt_dqs_w+1) << 1))+:6];
end
end
end
OCAL_DONE: begin
oclk_prech_req <= #TCQ 1'b0;
po_stg23_sel <= #TCQ 1'b0;
ocal_done_r <= #TCQ 1'b1;
end
endcase
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYGATE4SD3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__DLYGATE4SD3_BEHAVIORAL_PP_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__dlygate4sd3 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYGATE4SD3_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPVGND_1_V
`define SKY130_FD_SC_MS__TAPVGND_1_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection
* 1 row down.
*
* Verilog wrapper for tapvgnd with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__tapvgnd.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__tapvgnd_1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__tapvgnd base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__tapvgnd_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__tapvgnd base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPVGND_1_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sat Nov 19 19:18:37 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire Shift_reg_FLAGS_7_6, intAS, SIGN_FLAG_EXP, OP_FLAG_EXP, ZERO_FLAG_EXP,
SIGN_FLAG_SHT1, OP_FLAG_SHT1, ZERO_FLAG_SHT1, left_right_SHT2,
SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2, SIGN_FLAG_SHT1SHT2,
ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM, ZERO_FLAG_NRM, SIGN_FLAG_SFG,
OP_FLAG_SFG, ZERO_FLAG_SFG, inst_FSM_INPUT_ENABLE_state_next_1_, n514,
n515, n516, n517, n518, n519, n520, n521, n522, n523, n524, n525,
n526, n527, n528, n529, n530, n531, n532, n533, n534, n535, n536,
n537, n538, n539, n540, n541, n542, n543, n544, n545, n546, n547,
n548, n549, n550, n551, n552, n553, n554, n555, n556, n557, n558,
n559, n560, n561, n562, n563, n564, n565, n566, n567, n568, n569,
n570, n571, n572, n573, n574, n575, n576, n577, n578, n579, n580,
n581, n582, n583, n584, n585, n586, n587, n588, n589, n590, n591,
n592, n593, n594, n595, n596, n597, n598, n599, n600, n601, n602,
n603, n604, n605, n606, n607, n608, n609, n610, n611, n612, n613,
n614, n615, n616, n617, n618, n619, n620, n621, n622, n623, n624,
n625, n626, n627, n628, n629, n630, n631, n632, n633, n634, n635,
n636, n637, n638, n639, n640, n641, n642, n643, n644, n645, n646,
n647, n648, n649, n650, n651, n652, n653, n654, n655, n656, n657,
n658, n659, n660, n661, n662, n663, n664, n665, n666, n667, n668,
n669, n670, n671, n672, n673, n674, n675, n676, n677, n678, n679,
n680, n681, n682, n683, n684, n685, n686, n687, n688, n689, n690,
n691, n692, n693, n694, n695, n696, n697, n698, n699, n700, n701,
n702, n703, n704, n705, n706, n707, n708, n709, n710, n711, n712,
n713, n714, n715, n716, n717, n718, n719, n720, n721, n722, n723,
n724, n725, n726, n727, n728, n729, n730, n731, n732, n733, n734,
n735, n736, n737, n738, n739, n740, n741, n742, n743, n744, n745,
n746, n747, n748, n749, n750, n751, n752, n753, n754, n755, n756,
n757, n758, n759, n760, n761, n762, n763, n764, n765, n766, n767,
n768, n769, n770, n771, n772, n773, n774, n775, n776, n777, n778,
n779, n780, n781, n782, n783, n784, n785, n786, n787, n788, n789,
n790, n791, n792, n793, n794, n795, n796, n797, n798, n799, n800,
n801, n802, n803, n804, n805, n806, n807, n808, n809, n810, n811,
n812, n813, n814, n815, n816, n817, n818, n820, n821, n822, n823,
n824, n825, n826, n827, n828, n829, n830, n831, n832, n833, n834,
n835, n836, n837, n838, n839, n840, n841, n842, n843, n844, n845,
n846, n847, n848, n849, n850, n851, n852, n853, n854, n855, n856,
n857, n858, n859, n860, n861, n862, n863, n864, n865, n866, n867,
n868, n869, n870, n871, n872, n873, n874, n875, n876, n877, n878,
n879, n880, n881, n882, n883, n884, n885, n886, n887, n888, n889,
n890, n891, n892, n893, n894, n895, n896, n897, n898, n899, n900,
n901, n902, n903, n904, n905, n906, n907, n908, n909, n910, n911,
n912, n913, n914, n915, n916, n917, n918, n919, n920, n921, n922,
DP_OP_15J23_123_2314_n8, DP_OP_15J23_123_2314_n7,
DP_OP_15J23_123_2314_n6, DP_OP_15J23_123_2314_n5,
DP_OP_15J23_123_2314_n4, n923, n924, n925, n926, n927, n928, n929,
n930, n931, n932, n933, n934, n935, n936, n937, n938, n939, n940,
n941, n942, n943, n944, n945, n946, n947, n948, n949, n950, n951,
n952, n953, n954, n955, n956, n957, n958, n959, n960, n961, n962,
n963, n964, n965, n966, n967, n968, n969, n970, n971, n972, n973,
n974, n975, n976, n977, n978, n979, n980, n981, n982, n983, n984,
n985, n986, n987, n988, n989, n990, n991, n992, n993, n994, n995,
n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004, n1005,
n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015,
n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025,
n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035,
n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045,
n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055,
n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065,
n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075,
n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085,
n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095,
n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105,
n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115,
n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125,
n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135,
n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145,
n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155,
n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165,
n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175,
n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185,
n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195,
n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205,
n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215,
n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225,
n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235,
n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245,
n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255,
n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265,
n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275,
n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285,
n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295,
n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305,
n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315,
n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325,
n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335,
n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345,
n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355,
n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365,
n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375,
n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385,
n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395,
n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405,
n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415,
n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425,
n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435,
n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445,
n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455,
n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465,
n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475,
n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485,
n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495,
n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1506,
n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1516, n1517,
n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527,
n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537,
n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1548,
n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557, n1558,
n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567, n1568,
n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577, n1578,
n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587, n1588,
n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597, n1598,
n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607, n1608,
n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618,
n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627, n1629,
n1630, n1631, n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639,
n1640, n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649,
n1650, n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659,
n1660, n1661, n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669,
n1670, n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679,
n1680, n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689,
n1690, n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699,
n1700, n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709,
n1710, n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719,
n1720, n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729,
n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739,
n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749,
n1750, n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759,
n1760, n1761, n1762, n1763, n1764, n1765, n1766, n1767, n1768;
wire [3:0] Shift_reg_FLAGS_7;
wire [31:0] intDX_EWSW;
wire [31:0] intDY_EWSW;
wire [30:0] DMP_EXP_EWSW;
wire [27:0] DmP_EXP_EWSW;
wire [30:0] DMP_SHT1_EWSW;
wire [22:0] DmP_mant_SHT1_SW;
wire [4:0] Shift_amount_SHT1_EWR;
wire [25:0] Raw_mant_NRM_SWR;
wire [24:0] Data_array_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [4:2] shift_value_SHT2_EWR;
wire [7:0] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [4:0] LZD_output_NRM2_EW;
wire [4:1] exp_rslt_NRM2_EW1;
wire [30:0] DMP_SFG;
wire [25:0] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_ShiftRegister_Q_reg_6_ ( .D(n920), .CK(clk), .RN(n1727), .Q(
Shift_reg_FLAGS_7_6), .QN(n969) );
DFFRXLTS inst_ShiftRegister_Q_reg_1_ ( .D(n915), .CK(clk), .RN(n1727), .Q(
Shift_reg_FLAGS_7[1]), .QN(n925) );
DFFRXLTS inst_ShiftRegister_Q_reg_0_ ( .D(n914), .CK(clk), .RN(n1727), .Q(
Shift_reg_FLAGS_7[0]), .QN(n1635) );
DFFRXLTS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n881), .CK(clk), .RN(n1731), .Q(
intAS) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n815), .CK(clk), .RN(n1737),
.Q(Shift_amount_SHT1_EWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n814), .CK(clk), .RN(n1737),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n813), .CK(clk), .RN(n1740),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n804), .CK(clk), .RN(n1123), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n803), .CK(clk), .RN(n1742), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n802), .CK(clk), .RN(n1739), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n801), .CK(clk), .RN(n1738), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n800), .CK(clk), .RN(n1125), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n799), .CK(clk), .RN(n1122), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n798), .CK(clk), .RN(n1123), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n797), .CK(clk), .RN(n1126), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n796), .CK(clk), .RN(n1743), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n795), .CK(clk), .RN(n1740), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n794), .CK(clk), .RN(n1124), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n793), .CK(clk), .RN(n1742), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n792), .CK(clk), .RN(n1739), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n791), .CK(clk), .RN(n1738), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n790), .CK(clk), .RN(n1125), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n789), .CK(clk), .RN(n1122), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n788), .CK(clk), .RN(n1123), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n787), .CK(clk), .RN(n1126), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n786), .CK(clk), .RN(n1743), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n785), .CK(clk), .RN(n1123), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n784), .CK(clk), .RN(n1126), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n783), .CK(clk), .RN(n1743), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n782), .CK(clk), .RN(n1740), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n776), .CK(clk), .RN(n1742), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n775), .CK(clk), .RN(n1741), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n774), .CK(clk), .RN(n1741), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n773), .CK(clk), .RN(n1741), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n772), .CK(clk), .RN(n1741), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n771), .CK(clk), .RN(n1741), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n770), .CK(clk), .RN(n1741), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n769), .CK(clk), .RN(n1741), .Q(
DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n767), .CK(clk), .RN(n1741), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n766), .CK(clk), .RN(n1741), .Q(
DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n764), .CK(clk), .RN(n1740), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n763), .CK(clk), .RN(n1122), .Q(
DMP_SHT2_EWSW[2]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_2_ ( .D(n762), .CK(clk), .RN(n1122), .Q(
DMP_SFG[2]), .QN(n1724) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n761), .CK(clk), .RN(n1742), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n760), .CK(clk), .RN(n1739), .Q(
DMP_SHT2_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n758), .CK(clk), .RN(n1738), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n757), .CK(clk), .RN(n1125), .Q(
DMP_SHT2_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n755), .CK(clk), .RN(n1739), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n754), .CK(clk), .RN(n1738), .Q(
DMP_SHT2_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n752), .CK(clk), .RN(n1125), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n751), .CK(clk), .RN(n1122), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n749), .CK(clk), .RN(n1123), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n748), .CK(clk), .RN(n1126), .Q(
DMP_SHT2_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n746), .CK(clk), .RN(n1743), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n745), .CK(clk), .RN(n1744), .Q(
DMP_SHT2_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n743), .CK(clk), .RN(n1744), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n742), .CK(clk), .RN(n1744), .Q(
DMP_SHT2_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n740), .CK(clk), .RN(n1744), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n739), .CK(clk), .RN(n1744), .Q(
DMP_SHT2_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n737), .CK(clk), .RN(n1744), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n736), .CK(clk), .RN(n1744), .Q(
DMP_SHT2_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n734), .CK(clk), .RN(n1745), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n733), .CK(clk), .RN(n1745), .Q(
DMP_SHT2_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n731), .CK(clk), .RN(n1745), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n730), .CK(clk), .RN(n1745), .Q(
DMP_SHT2_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n728), .CK(clk), .RN(n1745), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n727), .CK(clk), .RN(n1745), .Q(
DMP_SHT2_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n725), .CK(clk), .RN(n1746), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n724), .CK(clk), .RN(n1746), .Q(
DMP_SHT2_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n722), .CK(clk), .RN(n1746), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n721), .CK(clk), .RN(n1746), .Q(
DMP_SHT2_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n719), .CK(clk), .RN(n1746), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n718), .CK(clk), .RN(n1746), .Q(
DMP_SHT2_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n716), .CK(clk), .RN(n1746), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n715), .CK(clk), .RN(n1747), .Q(
DMP_SHT2_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n713), .CK(clk), .RN(n1747), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n712), .CK(clk), .RN(n1747), .Q(
DMP_SHT2_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n710), .CK(clk), .RN(n1747), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n709), .CK(clk), .RN(n1747), .Q(
DMP_SHT2_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n707), .CK(clk), .RN(n1747), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n706), .CK(clk), .RN(n1747), .Q(
DMP_SHT2_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n704), .CK(clk), .RN(n1748), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n703), .CK(clk), .RN(n1748), .Q(
DMP_SHT2_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n701), .CK(clk), .RN(n1748), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n700), .CK(clk), .RN(n1748), .Q(
DMP_SHT2_EWSW[23]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_23_ ( .D(n699), .CK(clk), .RN(n1748), .Q(
DMP_SFG[23]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n698), .CK(clk), .RN(n1748), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n696), .CK(clk), .RN(n1748), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n695), .CK(clk), .RN(n1748), .Q(
DMP_SHT2_EWSW[24]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_24_ ( .D(n694), .CK(clk), .RN(n1749), .Q(
DMP_SFG[24]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n693), .CK(clk), .RN(n1749), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n691), .CK(clk), .RN(n1749), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n690), .CK(clk), .RN(n1749), .Q(
DMP_SHT2_EWSW[25]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_25_ ( .D(n689), .CK(clk), .RN(n1749), .Q(
DMP_SFG[25]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n688), .CK(clk), .RN(n1749), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n686), .CK(clk), .RN(n1749), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n685), .CK(clk), .RN(n1749), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_26_ ( .D(n684), .CK(clk), .RN(n1749), .Q(
DMP_SFG[26]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n683), .CK(clk), .RN(n1749), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n681), .CK(clk), .RN(n1750), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n680), .CK(clk), .RN(n1750), .Q(
DMP_SHT2_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_27_ ( .D(n679), .CK(clk), .RN(n1750), .Q(
DMP_SFG[27]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n678), .CK(clk), .RN(n1750), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n676), .CK(clk), .RN(n1750), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n675), .CK(clk), .RN(n1750), .Q(
DMP_SHT2_EWSW[28]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_28_ ( .D(n674), .CK(clk), .RN(n1750), .Q(
DMP_SFG[28]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n673), .CK(clk), .RN(n1750), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n671), .CK(clk), .RN(n1750), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n670), .CK(clk), .RN(n1750), .Q(
DMP_SHT2_EWSW[29]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_29_ ( .D(n669), .CK(clk), .RN(n1751), .Q(
DMP_SFG[29]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n668), .CK(clk), .RN(n1751), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n666), .CK(clk), .RN(n1751), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n665), .CK(clk), .RN(n1751), .Q(
DMP_SHT2_EWSW[30]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_30_ ( .D(n664), .CK(clk), .RN(n1751), .Q(
DMP_SFG[30]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n663), .CK(clk), .RN(n1751), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n661), .CK(clk), .RN(n1751), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n659), .CK(clk), .RN(n1751), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n657), .CK(clk), .RN(n1752), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n655), .CK(clk), .RN(n1752), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n653), .CK(clk), .RN(n1752), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n651), .CK(clk), .RN(n1752), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n649), .CK(clk), .RN(n1752), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n647), .CK(clk), .RN(n1753), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n645), .CK(clk), .RN(n1753), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n643), .CK(clk), .RN(n1753), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n641), .CK(clk), .RN(n1753), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n639), .CK(clk), .RN(n1753), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n637), .CK(clk), .RN(n1754), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n635), .CK(clk), .RN(n1754), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n633), .CK(clk), .RN(n1754), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n631), .CK(clk), .RN(n1754), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n629), .CK(clk), .RN(n1754), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n627), .CK(clk), .RN(n1755), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n625), .CK(clk), .RN(n1755), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n623), .CK(clk), .RN(n1755), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n621), .CK(clk), .RN(n1755), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n619), .CK(clk), .RN(n1755), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n617), .CK(clk), .RN(n1756), .Q(
DmP_EXP_EWSW[22]) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n608), .CK(clk), .RN(n1756), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n607), .CK(clk), .RN(n1756), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n606), .CK(clk), .RN(n1757), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n605), .CK(clk), .RN(n1757), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n604), .CK(clk), .RN(n1757), .Q(
ZERO_FLAG_SHT1SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n602), .CK(clk), .RN(n1757), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n601), .CK(clk), .RN(n1757), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n599), .CK(clk), .RN(n1757), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n598), .CK(clk), .RN(n1757), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n597), .CK(clk), .RN(n1757), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n596), .CK(clk), .RN(n1758), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n595), .CK(clk), .RN(n1758), .Q(
SIGN_FLAG_SHT1SHT2) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n589), .CK(clk), .RN(n1758), .Q(
Raw_mant_NRM_SWR[18]) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n585), .CK(clk), .RN(n1759), .Q(
Raw_mant_NRM_SWR[22]) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n584), .CK(clk), .RN(n1759), .Q(
Raw_mant_NRM_SWR[23]), .QN(n1651) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n583), .CK(clk), .RN(n1759), .Q(
Raw_mant_NRM_SWR[24]), .QN(n1705) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n582), .CK(clk), .RN(n1759), .Q(
Raw_mant_NRM_SWR[25]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n580), .CK(clk), .RN(n1759), .Q(
Raw_mant_NRM_SWR[13]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n579), .CK(clk), .RN(n1767), .Q(
LZD_output_NRM2_EW[4]), .QN(n1677) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n578), .CK(clk), .RN(n1759), .Q(
DmP_mant_SFG_SWR[1]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n576), .CK(clk), .RN(n1766), .Q(
LZD_output_NRM2_EW[2]), .QN(n1679) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n575), .CK(clk), .RN(n1759), .Q(
DmP_mant_SFG_SWR[8]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n573), .CK(clk), .RN(n1766), .Q(
LZD_output_NRM2_EW[1]), .QN(n1665) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n572), .CK(clk), .RN(n1760), .Q(
DmP_mant_SFG_SWR[0]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n567), .CK(clk), .RN(n1767), .Q(
LZD_output_NRM2_EW[3]), .QN(n1678) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n559), .CK(clk), .RN(n1761), .Q(
DmP_mant_SFG_SWR[4]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n553), .CK(clk), .RN(n1761), .Q(
DmP_mant_SFG_SWR[11]), .QN(n926) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n551), .CK(clk), .RN(n1761), .Q(
DmP_mant_SFG_SWR[10]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n550), .CK(clk), .RN(n1762), .Q(
Raw_mant_NRM_SWR[10]), .QN(n1673) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n519), .CK(clk), .RN(n1765), .Q(
DmP_mant_SFG_SWR[20]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n518), .CK(clk), .RN(n1765), .Q(
DmP_mant_SFG_SWR[21]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n515), .CK(clk), .RN(n1765), .Q(
DmP_mant_SFG_SWR[24]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n514), .CK(clk), .RN(n1765), .Q(
DmP_mant_SFG_SWR[25]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n831), .CK(clk), .RN(n1735), .Q(
Data_array_SWR[9]), .QN(n1719) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n829), .CK(clk), .RN(n1735), .Q(
Data_array_SWR[7]), .QN(n1717) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n828), .CK(clk), .RN(n1736), .Q(
Data_array_SWR[6]), .QN(n1716) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n832), .CK(clk), .RN(n1736), .Q(
Data_array_SWR[10]), .QN(n1714) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n662), .CK(clk), .RN(n1767), .Q(
DMP_exp_NRM2_EW[7]), .QN(n1713) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_3_ ( .D(n759), .CK(clk), .RN(n1123), .Q(
DMP_SFG[3]), .QN(n1712) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n834), .CK(clk), .RN(n1737), .Q(
Data_array_SWR[12]), .QN(n1709) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n884), .CK(clk), .RN(n1730),
.Q(intDX_EWSW[29]), .QN(n1701) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n852), .CK(clk), .RN(n1734),
.Q(intDY_EWSW[27]), .QN(n1700) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n863), .CK(clk), .RN(n1733),
.Q(intDY_EWSW[16]), .QN(n1698) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n875), .CK(clk), .RN(n1731), .Q(
intDY_EWSW[4]), .QN(n1695) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n877), .CK(clk), .RN(n1731), .Q(
intDY_EWSW[2]), .QN(n1694) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n878), .CK(clk), .RN(n1731), .Q(
intDY_EWSW[1]), .QN(n1692) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n870), .CK(clk), .RN(n1732), .Q(
intDY_EWSW[9]), .QN(n1689) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n672), .CK(clk), .RN(n1767), .Q(
DMP_exp_NRM2_EW[5]), .QN(n1684) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n667), .CK(clk), .RN(n1767), .Q(
DMP_exp_NRM2_EW[6]), .QN(n1683) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n921), .CK(clk), .RN(
n1727), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n1682) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n872), .CK(clk), .RN(n1732), .Q(
intDY_EWSW[7]), .QN(n1681) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n873), .CK(clk), .RN(n1732), .Q(
intDY_EWSW[6]), .QN(n1680) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n850), .CK(clk), .RN(n1734),
.Q(intDY_EWSW[29]), .QN(n1675) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n869), .CK(clk), .RN(n1732),
.Q(intDY_EWSW[10]), .QN(n1666) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_24_ ( .D(n780), .CK(clk), .RN(n1738), .Q(
DMP_EXP_EWSW[24]), .QN(n1653) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_24_ ( .D(n614), .CK(clk), .RN(n1756), .Q(
DmP_EXP_EWSW[24]), .QN(n1652) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n860), .CK(clk), .RN(n1733),
.Q(intDY_EWSW[19]), .QN(n1650) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n883), .CK(clk), .RN(n1731),
.Q(intDX_EWSW[30]), .QN(n1649) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n879), .CK(clk), .RN(n1731), .Q(
intDY_EWSW[0]), .QN(n1646) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n874), .CK(clk), .RN(n1732), .Q(
intDY_EWSW[5]), .QN(n1645) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n849), .CK(clk), .RN(n1734),
.Q(intDY_EWSW[30]), .QN(n1643) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n855), .CK(clk), .RN(n1733),
.Q(intDY_EWSW[24]), .QN(n1634) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n1731),
.Q(ready) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n610), .CK(clk), .RN(n1756), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n805), .CK(clk), .RN(n1765), .Q(
final_result_ieee[30]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n603), .CK(clk), .RN(n1757), .Q(
zero_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n547), .CK(clk), .RN(n1762), .Q(
final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n546), .CK(clk), .RN(n1762), .Q(
final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n545), .CK(clk), .RN(n1762), .Q(
final_result_ieee[13]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n544), .CK(clk), .RN(n1762), .Q(
final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n543), .CK(clk), .RN(n1762), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n538), .CK(clk), .RN(n1763), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n537), .CK(clk), .RN(n1763), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n534), .CK(clk), .RN(n1763), .Q(
final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n533), .CK(clk), .RN(n1763), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n530), .CK(clk), .RN(n1764), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n529), .CK(clk), .RN(n1764), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n526), .CK(clk), .RN(n1764), .Q(
final_result_ieee[22]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n609), .CK(clk), .RN(n1765), .Q(
overflow_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n548), .CK(clk), .RN(n1762), .Q(
final_result_ieee[10]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n542), .CK(clk), .RN(n1762), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n541), .CK(clk), .RN(n1762), .Q(
final_result_ieee[14]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n540), .CK(clk), .RN(n1763), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n539), .CK(clk), .RN(n1763), .Q(
final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n536), .CK(clk), .RN(n1763), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n535), .CK(clk), .RN(n1763), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n532), .CK(clk), .RN(n1763), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n531), .CK(clk), .RN(n1763), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n528), .CK(clk), .RN(n1764), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n527), .CK(clk), .RN(n1764), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n812), .CK(clk), .RN(n1766), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n811), .CK(clk), .RN(n1766), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n810), .CK(clk), .RN(n1766), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n809), .CK(clk), .RN(n1766), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n808), .CK(clk), .RN(n1766), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n807), .CK(clk), .RN(n1766), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n806), .CK(clk), .RN(n1766), .Q(
final_result_ieee[29]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n594), .CK(clk), .RN(n1765), .Q(
final_result_ieee[31]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n563), .CK(clk), .RN(n1760), .Q(
Raw_mant_NRM_SWR[7]), .QN(n1659) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n697), .CK(clk), .RN(n1767), .Q(
DMP_exp_NRM2_EW[0]), .QN(n1664) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n910), .CK(clk), .RN(n1728), .Q(
intDX_EWSW[3]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n561), .CK(clk), .RN(n1761), .Q(
Raw_mant_NRM_SWR[8]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n1727), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n1644) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n568), .CK(clk), .RN(n1760), .Q(
Raw_mant_NRM_SWR[3]), .QN(n1708) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n558), .CK(clk), .RN(n1761), .Q(
Raw_mant_NRM_SWR[4]), .QN(n1641) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n556), .CK(clk), .RN(n1761), .Q(
Raw_mant_NRM_SWR[6]), .QN(n1667) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n554), .CK(clk), .RN(n1761), .Q(
Raw_mant_NRM_SWR[11]), .QN(n1660) );
DFFRX2TS inst_ShiftRegister_Q_reg_5_ ( .D(n919), .CK(clk), .RN(n1727), .Q(
n1638), .QN(n1725) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n821), .CK(clk), .RN(n1734), .Q(
shift_value_SHT2_EWR[2]), .QN(n1661) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n820), .CK(clk), .RN(n1735), .Q(
shift_value_SHT2_EWR[3]), .QN(n1671) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n885), .CK(clk), .RN(n1730),
.Q(intDX_EWSW[28]), .QN(n1703) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n889), .CK(clk), .RN(n1730),
.Q(intDX_EWSW[24]), .QN(n1718) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n887), .CK(clk), .RN(n1730),
.Q(intDX_EWSW[26]), .QN(n1656) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n888), .CK(clk), .RN(n1730),
.Q(intDX_EWSW[25]), .QN(n1655) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n865), .CK(clk), .RN(n1732),
.Q(intDY_EWSW[14]), .QN(n1697) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n866), .CK(clk), .RN(n1732),
.Q(intDY_EWSW[13]), .QN(n1690) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n867), .CK(clk), .RN(n1732),
.Q(intDY_EWSW[12]), .QN(n1696) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n862), .CK(clk), .RN(n1733),
.Q(intDY_EWSW[17]), .QN(n1688) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n864), .CK(clk), .RN(n1733),
.Q(intDY_EWSW[15]), .QN(n1647) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n868), .CK(clk), .RN(n1732),
.Q(intDY_EWSW[11]), .QN(n1676) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n871), .CK(clk), .RN(n1732), .Q(
intDY_EWSW[8]), .QN(n1693) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n876), .CK(clk), .RN(n1731), .Q(
intDY_EWSW[3]), .QN(n1687) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n856), .CK(clk), .RN(n1733),
.Q(intDY_EWSW[23]), .QN(n1702) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n857), .CK(clk), .RN(n1733),
.Q(intDY_EWSW[22]), .QN(n1648) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n858), .CK(clk), .RN(n1733),
.Q(intDY_EWSW[21]), .QN(n1691) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n859), .CK(clk), .RN(n1733),
.Q(intDY_EWSW[20]), .QN(n1699) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n853), .CK(clk), .RN(n1734),
.Q(intDY_EWSW[26]), .QN(n1685) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n854), .CK(clk), .RN(n1734),
.Q(intDY_EWSW[25]), .QN(n1686) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n861), .CK(clk), .RN(n1733),
.Q(intDY_EWSW[18]), .QN(n1704) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n897), .CK(clk), .RN(n1729),
.Q(intDX_EWSW[16]), .QN(n1669) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n906), .CK(clk), .RN(n1728), .Q(
intDX_EWSW[7]), .QN(n1663) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n907), .CK(clk), .RN(n1728), .Q(
intDX_EWSW[6]), .QN(n1642) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n908), .CK(clk), .RN(n1728), .Q(
intDX_EWSW[5]), .QN(n1662) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n909), .CK(clk), .RN(n1728), .Q(
intDX_EWSW[4]), .QN(n1639) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n836), .CK(clk), .RN(n1737), .QN(
n1654) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n898), .CK(clk), .RN(n1729),
.Q(intDX_EWSW[15]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n890), .CK(clk), .RN(n1730),
.Q(intDX_EWSW[23]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n900), .CK(clk), .RN(n1729),
.Q(intDX_EWSW[13]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n892), .CK(clk), .RN(n1730),
.Q(intDX_EWSW[21]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n896), .CK(clk), .RN(n1729),
.Q(intDX_EWSW[17]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n847), .CK(clk), .RN(n1735), .Q(
Data_array_SWR[24]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n905), .CK(clk), .RN(n1728), .Q(
intDX_EWSW[8]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n902), .CK(clk), .RN(n1729),
.Q(intDX_EWSW[11]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n846), .CK(clk), .RN(n1735), .Q(
Data_array_SWR[23]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n904), .CK(clk), .RN(n1728), .Q(
intDX_EWSW[9]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n886), .CK(clk), .RN(n1730),
.Q(intDX_EWSW[27]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n911), .CK(clk), .RN(n1728), .Q(
intDX_EWSW[2]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n565), .CK(clk), .RN(n1760), .Q(
Raw_mant_NRM_SWR[5]) );
DFFRX4TS inst_ShiftRegister_Q_reg_4_ ( .D(n918), .CK(clk), .RN(n1727), .Q(
busy), .QN(n1768) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n922), .CK(clk), .RN(
n1727), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n835), .CK(clk), .RN(n1737), .Q(
Data_array_SWR[13]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n895), .CK(clk), .RN(n1729),
.Q(intDX_EWSW[18]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n577), .CK(clk), .RN(n1759), .Q(
Raw_mant_NRM_SWR[1]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n913), .CK(clk), .RN(n1728), .Q(
intDX_EWSW[0]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n894), .CK(clk), .RN(n1729),
.Q(intDX_EWSW[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n830), .CK(clk), .RN(n1735), .Q(
Data_array_SWR[8]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n845), .CK(clk), .RN(n1735), .Q(
Data_array_SWR[22]), .QN(n1637) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_10_ ( .D(n738), .CK(clk), .RN(n1744), .Q(
DMP_SFG[10]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n838), .CK(clk), .RN(n1736), .Q(
Data_array_SWR[15]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n826), .CK(clk), .RN(n1736), .Q(
Data_array_SWR[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n827), .CK(clk), .RN(n1736), .Q(
Data_array_SWR[5]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_9_ ( .D(n741), .CK(clk), .RN(n1744), .Q(
DMP_SFG[9]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n765), .CK(clk), .RN(n1742), .Q(
DMP_SFG[1]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_11_ ( .D(n735), .CK(clk), .RN(n1745), .Q(
DMP_SFG[11]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n882), .CK(clk), .RN(n1731),
.Q(intDX_EWSW[31]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_7_ ( .D(n747), .CK(clk), .RN(n1126), .Q(
DMP_SFG[7]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_5_ ( .D(n753), .CK(clk), .RN(n1123), .Q(
DMP_SFG[5]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_21_ ( .D(n705), .CK(clk), .RN(n1748), .Q(
DMP_SFG[21]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_19_ ( .D(n711), .CK(clk), .RN(n1747), .Q(
DMP_SFG[19]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_17_ ( .D(n717), .CK(clk), .RN(n1746), .Q(
DMP_SFG[17]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_15_ ( .D(n723), .CK(clk), .RN(n1746), .Q(
DMP_SFG[15]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n549), .CK(clk), .RN(n1762), .Q(
DmP_mant_SFG_SWR[12]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_6_ ( .D(n750), .CK(clk), .RN(n1743), .Q(
DMP_SFG[6]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_4_ ( .D(n756), .CK(clk), .RN(n1739), .Q(
DMP_SFG[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n833), .CK(clk), .RN(n1736), .Q(
Data_array_SWR[11]), .QN(n1715) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n840), .CK(clk), .RN(n1736), .Q(
Data_array_SWR[17]), .QN(n1711) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_8_ ( .D(n744), .CK(clk), .RN(n1744), .Q(
DMP_SFG[8]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n616), .CK(clk), .RN(n1756), .Q(
DmP_mant_SHT1_SW[22]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n516), .CK(clk), .RN(n1765), .Q(
DmP_mant_SFG_SWR[23]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n517), .CK(clk), .RN(n1765), .Q(
DmP_mant_SFG_SWR[22]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n520), .CK(clk), .RN(n1765), .Q(
DmP_mant_SFG_SWR[19]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n521), .CK(clk), .RN(n1764), .Q(
DmP_mant_SFG_SWR[18]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n523), .CK(clk), .RN(n1764), .Q(
DmP_mant_SFG_SWR[16]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n555), .CK(clk), .RN(n1761), .Q(
DmP_mant_SFG_SWR[9]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n557), .CK(clk), .RN(n1761), .Q(
DmP_mant_SFG_SWR[6]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n562), .CK(clk), .RN(n1760), .Q(
DmP_mant_SFG_SWR[7]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n566), .CK(clk), .RN(n1760), .Q(
DmP_mant_SFG_SWR[3]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n570), .CK(clk), .RN(n1760), .Q(
DmP_mant_SFG_SWR[2]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n768), .CK(clk), .RN(n1741), .Q(
DMP_SFG[0]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_13_ ( .D(n729), .CK(clk), .RN(n1745), .Q(
DMP_SFG[13]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n560), .CK(clk), .RN(n1766), .Q(
LZD_output_NRM2_EW[0]), .QN(n968) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n816), .CK(clk), .RN(n1737),
.Q(Shift_amount_SHT1_EWR[1]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n677), .CK(clk), .RN(n1767), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n682), .CK(clk), .RN(n1767), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n687), .CK(clk), .RN(n1767), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n692), .CK(clk), .RN(n1767), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_26_ ( .D(n612), .CK(clk), .RN(n1756), .Q(
DmP_EXP_EWSW[26]), .QN(n932) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n851), .CK(clk), .RN(n1734),
.Q(intDY_EWSW[28]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n824), .CK(clk), .RN(n1737), .Q(
Data_array_SWR[2]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n825), .CK(clk), .RN(n1737), .Q(
Data_array_SWR[3]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_22_ ( .D(n702), .CK(clk), .RN(n1748), .Q(
DMP_SFG[22]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_20_ ( .D(n708), .CK(clk), .RN(n1747), .Q(
DMP_SFG[20]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_18_ ( .D(n714), .CK(clk), .RN(n1747), .Q(
DMP_SFG[18]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_16_ ( .D(n720), .CK(clk), .RN(n1746), .Q(
DMP_SFG[16]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_14_ ( .D(n726), .CK(clk), .RN(n1745), .Q(
DMP_SFG[14]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_12_ ( .D(n732), .CK(clk), .RN(n1745), .Q(
DMP_SFG[12]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n848), .CK(clk), .RN(n1734),
.Q(intDY_EWSW[31]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_25_ ( .D(n613), .CK(clk), .RN(n1756), .Q(
DmP_EXP_EWSW[25]), .QN(n1721) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n912), .CK(clk), .RN(n1728), .Q(
intDX_EWSW[1]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n901), .CK(clk), .RN(n1729),
.Q(intDX_EWSW[12]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n893), .CK(clk), .RN(n1730),
.Q(intDX_EWSW[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n899), .CK(clk), .RN(n1729),
.Q(intDX_EWSW[14]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n891), .CK(clk), .RN(n1730),
.Q(intDX_EWSW[22]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n903), .CK(clk), .RN(n1729),
.Q(intDX_EWSW[10]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n837), .CK(clk), .RN(n1735), .Q(
Data_array_SWR[14]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n843), .CK(clk), .RN(n1736), .Q(
Data_array_SWR[20]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n571), .CK(clk), .RN(n1760), .Q(
Raw_mant_NRM_SWR[0]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n842), .CK(clk), .RN(n1736), .Q(
Data_array_SWR[19]), .QN(n1722) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n841), .CK(clk), .RN(n1736), .Q(
Data_array_SWR[18]), .QN(n1710) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n654), .CK(clk), .RN(n1752), .Q(
DmP_mant_SHT1_SW[3]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n644), .CK(clk), .RN(n1753), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n640), .CK(clk), .RN(n1753), .Q(
DmP_mant_SHT1_SW[10]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n636), .CK(clk), .RN(n1754), .Q(
DmP_mant_SHT1_SW[12]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n624), .CK(clk), .RN(n1755), .Q(
DmP_mant_SHT1_SW[18]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n632), .CK(clk), .RN(n1754), .Q(
DmP_mant_SHT1_SW[14]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_27_ ( .D(n777), .CK(clk), .RN(n1125), .Q(
DMP_EXP_EWSW[27]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n630), .CK(clk), .RN(n1754), .Q(
DmP_mant_SHT1_SW[15]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_25_ ( .D(n779), .CK(clk), .RN(n1122), .Q(
DMP_EXP_EWSW[25]), .QN(n967) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n660), .CK(clk), .RN(n1751), .Q(
DmP_mant_SHT1_SW[0]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n658), .CK(clk), .RN(n1751), .Q(
DmP_mant_SHT1_SW[1]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n650), .CK(clk), .RN(n1752), .Q(
DmP_mant_SHT1_SW[5]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_26_ ( .D(n778), .CK(clk), .RN(n1123), .Q(
DMP_EXP_EWSW[26]), .QN(n1720) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n618), .CK(clk), .RN(n1755), .Q(
DmP_mant_SHT1_SW[21]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n656), .CK(clk), .RN(n1752), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n648), .CK(clk), .RN(n1752), .Q(
DmP_mant_SHT1_SW[6]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n642), .CK(clk), .RN(n1753), .Q(
DmP_mant_SHT1_SW[9]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n638), .CK(clk), .RN(n1753), .Q(
DmP_mant_SHT1_SW[11]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n634), .CK(clk), .RN(n1754), .Q(
DmP_mant_SHT1_SW[13]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n620), .CK(clk), .RN(n1755), .Q(
DmP_mant_SHT1_SW[20]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n652), .CK(clk), .RN(n1752), .Q(
DmP_mant_SHT1_SW[4]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n622), .CK(clk), .RN(n1755), .Q(
DmP_mant_SHT1_SW[19]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n646), .CK(clk), .RN(n1753), .Q(
DmP_mant_SHT1_SW[7]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n628), .CK(clk), .RN(n1754), .Q(
DmP_mant_SHT1_SW[16]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n626), .CK(clk), .RN(n1755), .Q(
DmP_mant_SHT1_SW[17]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n817), .CK(clk), .RN(n1737),
.Q(Shift_amount_SHT1_EWR[0]) );
DFFRX1TS inst_ShiftRegister_Q_reg_3_ ( .D(n917), .CK(clk), .RN(n1727), .Q(
Shift_reg_FLAGS_7[3]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n844), .CK(clk), .RN(n1735), .Q(
Data_array_SWR[21]), .QN(n1636) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n839), .CK(clk), .RN(n1735), .Q(
Data_array_SWR[16]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n574), .CK(clk), .RN(n1759), .Q(
Raw_mant_NRM_SWR[9]), .QN(n1668) );
DFFRX4TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n818), .CK(clk), .RN(n1734), .Q(
shift_value_SHT2_EWR[4]), .QN(n1640) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n552), .CK(clk), .RN(n1761), .Q(
Raw_mant_NRM_SWR[12]), .QN(n1658) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n569), .CK(clk), .RN(n1760), .Q(
Raw_mant_NRM_SWR[2]), .QN(n1672) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_23_ ( .D(n615), .CK(clk), .RN(n1756), .Q(
DmP_EXP_EWSW[23]), .QN(n966) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n564), .CK(clk), .RN(n1760), .Q(
DmP_mant_SFG_SWR[5]), .QN(n931) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n822), .CK(clk), .RN(n1734), .Q(
Data_array_SWR[0]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n823), .CK(clk), .RN(n1737), .Q(
Data_array_SWR[1]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_27_ ( .D(n611), .CK(clk), .RN(n1756), .Q(
DmP_EXP_EWSW[27]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n525), .CK(clk), .RN(n1764), .Q(
DmP_mant_SFG_SWR[14]), .QN(n963) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n524), .CK(clk), .RN(n1764), .Q(
DmP_mant_SFG_SWR[15]), .QN(n964) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n522), .CK(clk), .RN(n1764), .Q(
DmP_mant_SFG_SWR[17]), .QN(n965) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n593), .CK(clk), .RN(n1758), .Q(
Raw_mant_NRM_SWR[14]), .QN(n1657) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n592), .CK(clk), .RN(n1758), .Q(
Raw_mant_NRM_SWR[15]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n591), .CK(clk), .RN(n1758), .Q(
Raw_mant_NRM_SWR[16]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n590), .CK(clk), .RN(n1758), .Q(
Raw_mant_NRM_SWR[17]), .QN(n1706) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n588), .CK(clk), .RN(n1758), .Q(
Raw_mant_NRM_SWR[19]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n587), .CK(clk), .RN(n1758), .Q(
Raw_mant_NRM_SWR[20]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n586), .CK(clk), .RN(n1758), .Q(
Raw_mant_NRM_SWR[21]), .QN(n1707) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n581), .CK(clk), .RN(n1759), .Q(
DmP_mant_SFG_SWR[13]), .QN(n1674) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_23_ ( .D(n781), .CK(clk), .RN(n1740), .Q(
DMP_EXP_EWSW[23]) );
DFFRX4TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n600), .CK(clk), .RN(n1757), .Q(
OP_FLAG_SFG), .QN(n1670) );
CMPR32X2TS DP_OP_15J23_123_2314_U8 ( .A(n1665), .B(DMP_exp_NRM2_EW[1]), .C(
DP_OP_15J23_123_2314_n8), .CO(DP_OP_15J23_123_2314_n7), .S(
exp_rslt_NRM2_EW1[1]) );
CMPR32X2TS DP_OP_15J23_123_2314_U7 ( .A(n1679), .B(DMP_exp_NRM2_EW[2]), .C(
DP_OP_15J23_123_2314_n7), .CO(DP_OP_15J23_123_2314_n6), .S(
exp_rslt_NRM2_EW1[2]) );
CMPR32X2TS DP_OP_15J23_123_2314_U6 ( .A(n1678), .B(DMP_exp_NRM2_EW[3]), .C(
DP_OP_15J23_123_2314_n6), .CO(DP_OP_15J23_123_2314_n5), .S(
exp_rslt_NRM2_EW1[3]) );
CMPR32X2TS DP_OP_15J23_123_2314_U5 ( .A(n1677), .B(DMP_exp_NRM2_EW[4]), .C(
DP_OP_15J23_123_2314_n5), .CO(DP_OP_15J23_123_2314_n4), .S(
exp_rslt_NRM2_EW1[4]) );
DFFRX2TS inst_ShiftRegister_Q_reg_2_ ( .D(n916), .CK(clk), .RN(n1727), .Q(
n970), .QN(n1723) );
DFFRX2TS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n880), .CK(clk), .RN(n1731), .Q(
left_right_SHT2), .QN(n924) );
AO22X1TS U930 ( .A0(n1575), .A1(Raw_mant_NRM_SWR[24]), .B0(n1584), .B1(n1080), .Y(n583) );
INVX2TS U931 ( .A(n957), .Y(n936) );
CMPR32X2TS U932 ( .A(DMP_SFG[8]), .B(n1582), .C(n1581), .CO(n1569), .S(n1583) );
CMPR32X2TS U933 ( .A(DMP_SFG[4]), .B(n1562), .C(n1561), .CO(n1543), .S(n1563) );
CMPR32X2TS U934 ( .A(DMP_SFG[6]), .B(n1565), .C(n1546), .CO(n1508), .S(n1548) );
BUFX3TS U935 ( .A(n1338), .Y(n1293) );
CLKBUFX2TS U936 ( .A(n1604), .Y(n957) );
ADDFHX2TS U937 ( .A(n1203), .B(DMP_SFG[22]), .CI(n1202), .CO(n1204), .S(
n1080) );
AOI222X4TS U938 ( .A0(Data_array_SWR[20]), .A1(n1536), .B0(
Data_array_SWR[16]), .B1(n1537), .C0(Data_array_SWR[24]), .C1(n1494),
.Y(n1503) );
BUFX3TS U939 ( .A(n1180), .Y(n1538) );
AND2X2TS U940 ( .A(beg_OP), .B(n1390), .Y(n1393) );
ADDFHX2TS U941 ( .A(n1481), .B(DMP_SFG[21]), .CI(n1480), .CO(n1202), .S(
n1482) );
CMPR32X2TS U942 ( .A(n1079), .B(DMP_SFG[20]), .C(n1078), .CO(n1480), .S(
n1046) );
CMPR32X2TS U943 ( .A(n1478), .B(DMP_SFG[19]), .C(n1477), .CO(n1078), .S(
n1479) );
BUFX3TS U944 ( .A(n1253), .Y(n1443) );
INVX2TS U945 ( .A(n1181), .Y(n1612) );
AOI21X1TS U946 ( .A0(Shift_amount_SHT1_EWR[1]), .A1(n942), .B0(n1376), .Y(
n1210) );
CMPR32X2TS U947 ( .A(n1082), .B(DMP_SFG[18]), .C(n1081), .CO(n1477), .S(
n1083) );
INVX2TS U948 ( .A(n1458), .Y(n1253) );
NAND2X1TS U949 ( .A(n925), .B(n938), .Y(n1429) );
NAND2X2TS U950 ( .A(n1026), .B(n1025), .Y(n1041) );
CMPR32X2TS U951 ( .A(n1116), .B(DMP_SFG[17]), .C(n1115), .CO(n1081), .S(
n1117) );
BUFX3TS U952 ( .A(Shift_reg_FLAGS_7_6), .Y(n1458) );
INVX2TS U953 ( .A(n942), .Y(n923) );
NAND2X2TS U954 ( .A(n1022), .B(n1021), .Y(n1026) );
CMPR32X2TS U955 ( .A(n1113), .B(DMP_SFG[16]), .C(n1112), .CO(n1115), .S(
n1114) );
INVX2TS U956 ( .A(n1768), .Y(n937) );
OAI21X1TS U957 ( .A0(n1008), .A1(n1007), .B0(n1006), .Y(n1022) );
CMPR32X2TS U958 ( .A(n1474), .B(DMP_SFG[15]), .C(n1473), .CO(n1112), .S(
n1475) );
BUFX3TS U959 ( .A(Shift_reg_FLAGS_7[1]), .Y(n1372) );
NAND2X1TS U960 ( .A(n1684), .B(n1084), .Y(n1090) );
CMPR32X2TS U961 ( .A(n1471), .B(DMP_SFG[14]), .C(n1470), .CO(n1473), .S(
n1472) );
AO21XLTS U962 ( .A0(n1063), .A1(Raw_mant_NRM_SWR[18]), .B0(n1365), .Y(n1064)
);
CMPR32X2TS U963 ( .A(DMP_SFG[12]), .B(n1468), .C(n1467), .CO(n1127), .S(
n1469) );
AOI22X2TS U964 ( .A0(n1523), .A1(DmP_mant_SFG_SWR[13]), .B0(n1674), .B1(
n1529), .Y(n1491) );
BUFX8TS U965 ( .A(n1670), .Y(n1529) );
NAND2X4TS U966 ( .A(n1066), .B(n1660), .Y(n1050) );
OAI211XLTS U967 ( .A0(n1687), .A1(intDX_EWSW[3]), .B0(n994), .C0(n993), .Y(
n997) );
NOR2XLTS U968 ( .A(n1010), .B(intDY_EWSW[16]), .Y(n1011) );
OAI21XLTS U969 ( .A0(intDX_EWSW[23]), .A1(n1702), .B0(intDX_EWSW[22]), .Y(
n1016) );
NOR2XLTS U970 ( .A(n1377), .B(exp_rslt_NRM2_EW1[1]), .Y(n1087) );
NOR3X1TS U971 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[15]), .C(
Raw_mant_NRM_SWR[16]), .Y(n1360) );
OAI21XLTS U972 ( .A0(n1641), .A1(n1420), .B0(n1285), .Y(n1286) );
NAND2X1TS U973 ( .A(n1683), .B(n1091), .Y(n1096) );
AOI31XLTS U974 ( .A0(busy), .A1(Shift_amount_SHT1_EWR[4]), .A2(n943), .B0(
n1357), .Y(n1201) );
BUFX3TS U975 ( .A(n1393), .Y(n1405) );
CLKINVX3TS U976 ( .A(n1315), .Y(n1211) );
CLKINVX3TS U977 ( .A(n1483), .Y(n1633) );
NAND2X1TS U978 ( .A(Shift_reg_FLAGS_7[3]), .B(n1612), .Y(n1180) );
CLKINVX3TS U979 ( .A(n1259), .Y(n1459) );
OAI21XLTS U980 ( .A0(n1700), .A1(n1280), .B0(n1261), .Y(n611) );
OAI21XLTS U981 ( .A0(n1700), .A1(n1459), .B0(n1343), .Y(n777) );
OAI211XLTS U982 ( .A0(n1281), .A1(n950), .B0(n1236), .C0(n1235), .Y(n843) );
OAI211XLTS U983 ( .A0(n1310), .A1(n948), .B0(n1309), .C0(n1308), .Y(n825) );
OAI21XLTS U984 ( .A0(n1413), .A1(n1211), .B0(n1290), .Y(n840) );
OAI21XLTS U985 ( .A0(n1417), .A1(n951), .B0(n1214), .Y(n838) );
OAI21XLTS U986 ( .A0(n1385), .A1(n1077), .B0(n1382), .Y(n921) );
OAI21XLTS U987 ( .A0(n1691), .A1(n1457), .B0(n1218), .Y(n619) );
OAI21XLTS U988 ( .A0(n1693), .A1(n1277), .B0(n1274), .Y(n645) );
OAI21XLTS U989 ( .A0(n1648), .A1(n1459), .B0(n1340), .Y(n782) );
AO22X1TS U990 ( .A0(n1184), .A1(n1183), .B0(n1612), .B1(
final_result_ieee[30]), .Y(n805) );
BUFX4TS U991 ( .A(n1338), .Y(n1259) );
AO22X1TS U992 ( .A0(n1549), .A1(n1117), .B0(n1564), .B1(Raw_mant_NRM_SWR[19]), .Y(n588) );
INVX4TS U993 ( .A(n928), .Y(n1457) );
AO22X1TS U994 ( .A0(n1549), .A1(n1114), .B0(n1564), .B1(Raw_mant_NRM_SWR[18]), .Y(n589) );
AND2X2TS U995 ( .A(n1183), .B(n1094), .Y(n1095) );
AND2X2TS U996 ( .A(n1713), .B(n1097), .Y(n1098) );
NAND2X4TS U997 ( .A(n1041), .B(n1040), .Y(n1042) );
AO22X1TS U998 ( .A0(n1549), .A1(n1548), .B0(n1723), .B1(Raw_mant_NRM_SWR[8]),
.Y(n561) );
AO22X1TS U999 ( .A0(n1392), .A1(Data_X[10]), .B0(n1391), .B1(intDX_EWSW[10]),
.Y(n903) );
AO22X1TS U1000 ( .A0(n1392), .A1(Data_X[22]), .B0(n1394), .B1(intDX_EWSW[22]), .Y(n891) );
AO22X1TS U1001 ( .A0(n1392), .A1(Data_X[12]), .B0(n1404), .B1(intDX_EWSW[12]), .Y(n901) );
AO22X1TS U1002 ( .A0(n1392), .A1(Data_X[27]), .B0(n1394), .B1(intDX_EWSW[27]), .Y(n886) );
AO22X1TS U1003 ( .A0(n1392), .A1(Data_X[11]), .B0(n1391), .B1(intDX_EWSW[11]), .Y(n902) );
AO22X1TS U1004 ( .A0(n1392), .A1(Data_X[19]), .B0(n1404), .B1(intDX_EWSW[19]), .Y(n894) );
AO22X1TS U1005 ( .A0(n1392), .A1(Data_X[16]), .B0(n1404), .B1(intDX_EWSW[16]), .Y(n897) );
OAI21X1TS U1006 ( .A0(n955), .A1(n1102), .B0(n1107), .Y(n1108) );
OAI21X1TS U1007 ( .A0(n1654), .A1(n1102), .B0(n1109), .Y(n1110) );
AND2X4TS U1008 ( .A(n1359), .B(n1360), .Y(n1358) );
OAI211X1TS U1009 ( .A0(DMP_SFG[5]), .A1(n1541), .B0(DMP_SFG[4]), .C0(n1561),
.Y(n1506) );
OAI211X1TS U1010 ( .A0(DMP_SFG[7]), .A1(n1567), .B0(DMP_SFG[6]), .C0(n1565),
.Y(n1566) );
NOR2BX4TS U1011 ( .AN(Shift_amount_SHT1_EWR[0]), .B(n923), .Y(n1072) );
OR2X2TS U1012 ( .A(n923), .B(Shift_amount_SHT1_EWR[0]), .Y(n929) );
AOI2BB2X1TS U1013 ( .B0(OP_FLAG_SFG), .B1(DmP_mant_SFG_SWR[22]), .A0N(
DmP_mant_SFG_SWR[22]), .A1N(n1522), .Y(n1079) );
AOI2BB2X1TS U1014 ( .B0(OP_FLAG_SFG), .B1(DmP_mant_SFG_SWR[18]), .A0N(
DmP_mant_SFG_SWR[18]), .A1N(n1522), .Y(n1113) );
AOI2BB2X1TS U1015 ( .B0(OP_FLAG_SFG), .B1(DmP_mant_SFG_SWR[19]), .A0N(
DmP_mant_SFG_SWR[19]), .A1N(n1522), .Y(n1116) );
NOR2X1TS U1016 ( .A(n1027), .B(intDY_EWSW[24]), .Y(n1028) );
NOR2X1TS U1017 ( .A(n972), .B(intDY_EWSW[10]), .Y(n973) );
AOI211X1TS U1018 ( .A0(intDY_EWSW[28]), .A1(n1703), .B0(n1036), .C0(n1034),
.Y(n1038) );
INVX3TS U1019 ( .A(n1578), .Y(n1101) );
INVX1TS U1020 ( .A(n1366), .Y(n1368) );
NAND2X2TS U1021 ( .A(n1640), .B(n1494), .Y(n1102) );
OAI21X1TS U1022 ( .A0(intDX_EWSW[21]), .A1(n1691), .B0(intDX_EWSW[20]), .Y(
n1009) );
OAI21X1TS U1023 ( .A0(intDX_EWSW[15]), .A1(n1647), .B0(intDX_EWSW[14]), .Y(
n979) );
INVX4TS U1024 ( .A(n1670), .Y(n1530) );
OAI21X1TS U1025 ( .A0(n1406), .A1(n1211), .B0(n1270), .Y(n845) );
OAI211X1TS U1026 ( .A0(n1324), .A1(n1211), .B0(n1227), .C0(n1226), .Y(n828)
);
OAI211X1TS U1027 ( .A0(n1251), .A1(n950), .B0(n1250), .C0(n1249), .Y(n823)
);
OAI211X1TS U1028 ( .A0(n1318), .A1(n948), .B0(n1313), .C0(n1312), .Y(n824)
);
OAI211X1TS U1029 ( .A0(n1284), .A1(n951), .B0(n1283), .C0(n1282), .Y(n841)
);
OAI211X1TS U1030 ( .A0(n1303), .A1(n951), .B0(n1302), .C0(n1301), .Y(n831)
);
AOI222X1TS U1031 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n1323), .B0(n960), .B1(
DmP_mant_SHT1_SW[3]), .C0(n1240), .C1(DmP_mant_SHT1_SW[4]), .Y(n1310)
);
OAI21X1TS U1032 ( .A0(n1668), .A1(n1208), .B0(n1207), .Y(n1209) );
AOI222X1TS U1033 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n1407), .B0(n959), .B1(
DmP_mant_SHT1_SW[17]), .C0(n1240), .C1(DmP_mant_SHT1_SW[18]), .Y(n1284) );
AOI222X1TS U1034 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n1323), .B0(n958), .B1(
DmP_mant_SHT1_SW[15]), .C0(n1240), .C1(DmP_mant_SHT1_SW[16]), .Y(n1243) );
AOI222X1TS U1035 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n1323), .B0(n958), .B1(
DmP_mant_SHT1_SW[2]), .C0(n1240), .C1(DmP_mant_SHT1_SW[3]), .Y(n1318)
);
OAI21X1TS U1036 ( .A0(n1708), .A1(n1208), .B0(n1410), .Y(n1411) );
INVX4TS U1037 ( .A(n1287), .Y(n941) );
AOI222X1TS U1038 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n1323), .B0(n959), .B1(
DmP_mant_SHT1_SW[7]), .C0(n1240), .C1(DmP_mant_SHT1_SW[8]), .Y(n1303)
);
OAI21X1TS U1039 ( .A0(n1658), .A1(n1420), .B0(n1419), .Y(n1421) );
OAI21X1TS U1040 ( .A0(n1657), .A1(n1420), .B0(n1321), .Y(n1322) );
CLKINVX6TS U1041 ( .A(n1420), .Y(n1409) );
OAI21X1TS U1042 ( .A0(n1673), .A1(n1420), .B0(n1415), .Y(n1416) );
NAND2X4TS U1043 ( .A(n1212), .B(n1372), .Y(n1420) );
OAI21X1TS U1044 ( .A0(n956), .A1(n1640), .B0(n1201), .Y(n818) );
AO22X1TS U1045 ( .A0(n1585), .A1(Raw_mant_NRM_SWR[23]), .B0(n1584), .B1(
n1482), .Y(n584) );
AO22X1TS U1046 ( .A0(n957), .A1(n1519), .B0(final_result_ieee[0]), .B1(n935),
.Y(n531) );
OAI211X2TS U1047 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n1199), .B0(n1067), .C0(
n1363), .Y(n1374) );
AO22X1TS U1048 ( .A0(n957), .A1(n1545), .B0(final_result_ieee[5]), .B1(n1610), .Y(n536) );
AO22X1TS U1049 ( .A0(n957), .A1(n1603), .B0(final_result_ieee[1]), .B1(n935),
.Y(n532) );
AO22X1TS U1050 ( .A0(n1604), .A1(n1141), .B0(final_result_ieee[17]), .B1(
n1610), .Y(n539) );
AO22X1TS U1051 ( .A0(n1604), .A1(n1179), .B0(final_result_ieee[10]), .B1(
n935), .Y(n548) );
AO22X1TS U1052 ( .A0(n1604), .A1(n1560), .B0(final_result_ieee[4]), .B1(n935), .Y(n540) );
AO22X1TS U1053 ( .A0(n1604), .A1(n1142), .B0(final_result_ieee[16]), .B1(
n935), .Y(n535) );
AO22X1TS U1054 ( .A0(n1604), .A1(n1185), .B0(final_result_ieee[7]), .B1(
n1610), .Y(n542) );
AO22X1TS U1055 ( .A0(n1604), .A1(n1622), .B0(final_result_ieee[20]), .B1(
n935), .Y(n528) );
AO22X1TS U1056 ( .A0(n1604), .A1(n1137), .B0(final_result_ieee[21]), .B1(
n935), .Y(n527) );
AO22X1TS U1057 ( .A0(n1604), .A1(n1139), .B0(final_result_ieee[14]), .B1(
n935), .Y(n541) );
OAI21X1TS U1058 ( .A0(n1703), .A1(n1457), .B0(n1221), .Y(n776) );
OAI21X1TS U1059 ( .A0(n1694), .A1(n1217), .B0(n1215), .Y(n802) );
OAI21X1TS U1060 ( .A0(n1648), .A1(n1457), .B0(n1222), .Y(n617) );
OAI21X1TS U1061 ( .A0(n1265), .A1(n1217), .B0(n1216), .Y(n803) );
OAI21X1TS U1062 ( .A0(n1699), .A1(n1457), .B0(n1219), .Y(n621) );
OAI21X1TS U1063 ( .A0(n1646), .A1(n1459), .B0(n1229), .Y(n804) );
OAI21X1TS U1064 ( .A0(n1650), .A1(n1348), .B0(n1336), .Y(n785) );
OAI21X1TS U1065 ( .A0(n1689), .A1(n1335), .B0(n1328), .Y(n795) );
OAI21X1TS U1066 ( .A0(n1704), .A1(n1348), .B0(n1337), .Y(n786) );
OAI21X1TS U1067 ( .A0(n1701), .A1(n1350), .B0(n1294), .Y(n775) );
OAI21X1TS U1068 ( .A0(n1666), .A1(n1335), .B0(n1327), .Y(n794) );
OAI21X1TS U1069 ( .A0(n1676), .A1(n1335), .B0(n1330), .Y(n793) );
OAI21X1TS U1070 ( .A0(n1696), .A1(n1335), .B0(n1334), .Y(n792) );
OAI21X1TS U1071 ( .A0(n1693), .A1(n1335), .B0(n1331), .Y(n796) );
OAI21X1TS U1072 ( .A0(n1688), .A1(n1348), .B0(n1341), .Y(n787) );
OAI21X1TS U1073 ( .A0(n1647), .A1(n1348), .B0(n1044), .Y(n789) );
OAI21X1TS U1074 ( .A0(n1699), .A1(n1348), .B0(n1342), .Y(n784) );
OAI21X1TS U1075 ( .A0(n1696), .A1(n1280), .B0(n1275), .Y(n637) );
OAI21X1TS U1076 ( .A0(n1676), .A1(n1280), .B0(n1273), .Y(n639) );
OAI21X1TS U1077 ( .A0(n1687), .A1(n1277), .B0(n1256), .Y(n655) );
OAI21X1TS U1078 ( .A0(n1697), .A1(n1280), .B0(n1272), .Y(n633) );
OAI21X1TS U1079 ( .A0(n1695), .A1(n1277), .B0(n1262), .Y(n653) );
OAI21X1TS U1080 ( .A0(n1690), .A1(n1280), .B0(n1278), .Y(n635) );
OAI21X1TS U1081 ( .A0(n1645), .A1(n1277), .B0(n1263), .Y(n651) );
OAI21X1TS U1082 ( .A0(n1265), .A1(n1277), .B0(n1264), .Y(n659) );
AO22X1TS U1083 ( .A0(n1585), .A1(Raw_mant_NRM_SWR[21]), .B0(n1584), .B1(
n1479), .Y(n586) );
INVX2TS U1084 ( .A(n1293), .Y(n1335) );
INVX2TS U1085 ( .A(n1293), .Y(n1348) );
OAI21X1TS U1086 ( .A0(n1646), .A1(n1350), .B0(n1295), .Y(n661) );
INVX1TS U1087 ( .A(n1381), .Y(n1184) );
INVX2TS U1088 ( .A(n1255), .Y(n1280) );
OAI21X1TS U1089 ( .A0(n1649), .A1(n1350), .B0(n1292), .Y(n774) );
OAI21X1TS U1090 ( .A0(n1354), .A1(n1443), .B0(n1350), .Y(n1352) );
INVX2TS U1091 ( .A(n1255), .Y(n1277) );
NOR2X1TS U1092 ( .A(n1460), .B(SIGN_FLAG_SHT1SHT2), .Y(n1356) );
BUFX4TS U1093 ( .A(n1291), .Y(n1338) );
OR2X2TS U1094 ( .A(n1092), .B(n1183), .Y(n1182) );
AOI31X1TS U1095 ( .A0(n1658), .A1(Raw_mant_NRM_SWR[11]), .A2(n1066), .B0(
n1064), .Y(n1059) );
NOR3X6TS U1096 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .C(n1193),
.Y(n1051) );
NAND2BX1TS U1097 ( .AN(n1379), .B(n1089), .Y(n1092) );
NAND2X6TS U1098 ( .A(n1068), .B(n1658), .Y(n1193) );
AOI222X1TS U1099 ( .A0(n1602), .A1(n947), .B0(n1629), .B1(Data_array_SWR[5]),
.C0(n1601), .C1(n1555), .Y(n1600) );
AOI222X1TS U1100 ( .A0(n1609), .A1(n1595), .B0(n1629), .B1(Data_array_SWR[8]), .C0(n1607), .C1(n1555), .Y(n1605) );
AOI222X1TS U1101 ( .A0(n1599), .A1(n947), .B0(n1629), .B1(Data_array_SWR[4]),
.C0(n1598), .C1(n1555), .Y(n1597) );
AOI31X1TS U1102 ( .A0(n1063), .A1(Raw_mant_NRM_SWR[16]), .A2(n1706), .B0(
n1062), .Y(n1070) );
AOI222X1TS U1103 ( .A0(n1599), .A1(n954), .B0(Data_array_SWR[4]), .B1(n1608),
.C0(n1598), .C1(n1606), .Y(n1621) );
AOI222X1TS U1104 ( .A0(n1609), .A1(left_right_SHT2), .B0(Data_array_SWR[8]),
.B1(n1608), .C0(n1607), .C1(n1606), .Y(n1616) );
AOI222X1TS U1105 ( .A0(n1602), .A1(left_right_SHT2), .B0(Data_array_SWR[5]),
.B1(n1608), .C0(n1601), .C1(n1606), .Y(n1618) );
NOR2X1TS U1106 ( .A(n1088), .B(n1378), .Y(n1089) );
AO22XLTS U1107 ( .A0(n1401), .A1(add_subt), .B0(n1394), .B1(intAS), .Y(n881)
);
NOR2X6TS U1108 ( .A(Raw_mant_NRM_SWR[13]), .B(n1048), .Y(n1066) );
AOI31X1TS U1109 ( .A0(n1705), .A1(n1061), .A2(n1060), .B0(
Raw_mant_NRM_SWR[25]), .Y(n1062) );
BUFX3TS U1110 ( .A(n1072), .Y(n1240) );
NAND4BX1TS U1111 ( .AN(exp_rslt_NRM2_EW1[4]), .B(n1087), .C(n1086), .D(n1085), .Y(n1088) );
AOI2BB2X1TS U1112 ( .B0(n1039), .B1(n1038), .A0N(n1037), .A1N(n1036), .Y(
n1040) );
AOI222X1TS U1113 ( .A0(Data_array_SWR[19]), .A1(n1551), .B0(
Data_array_SWR[23]), .B1(n1101), .C0(Data_array_SWR[15]), .C1(n1550),
.Y(n1484) );
NAND2X4TS U1114 ( .A(n946), .B(n1510), .Y(n1105) );
NAND2X2TS U1115 ( .A(n1358), .B(n1657), .Y(n1048) );
NAND4XLTS U1116 ( .A(n1157), .B(n1156), .C(n1155), .D(n1154), .Y(n1176) );
NAND2BX1TS U1117 ( .AN(n1558), .B(DMP_SFG[2]), .Y(n1539) );
INVX3TS U1118 ( .A(n1577), .Y(n1550) );
NAND4XLTS U1119 ( .A(n1173), .B(n1172), .C(n1171), .D(n1170), .Y(n1174) );
OAI211X1TS U1120 ( .A0(intDX_EWSW[8]), .A1(n1693), .B0(n987), .C0(n986), .Y(
n988) );
NAND4XLTS U1121 ( .A(n1149), .B(n1148), .C(n1147), .D(n1146), .Y(n1177) );
OAI211X2TS U1122 ( .A0(intDX_EWSW[12]), .A1(n1696), .B0(n983), .C0(n974),
.Y(n985) );
NAND2X2TS U1123 ( .A(n1366), .B(n1369), .Y(n1049) );
NAND3X1TS U1124 ( .A(n1685), .B(n1029), .C(intDX_EWSW[26]), .Y(n1031) );
OAI211X2TS U1125 ( .A0(intDX_EWSW[20]), .A1(n1699), .B0(n1020), .C0(n1004),
.Y(n1015) );
NOR2X1TS U1126 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n1384) );
INVX1TS U1127 ( .A(DmP_mant_SFG_SWR[20]), .Y(n1617) );
NAND2BX1TS U1128 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n1030) );
INVX1TS U1129 ( .A(DmP_mant_SFG_SWR[21]), .Y(n1620) );
NOR2X1TS U1130 ( .A(Raw_mant_NRM_SWR[23]), .B(Raw_mant_NRM_SWR[22]), .Y(
n1057) );
NAND2BX1TS U1131 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n1023) );
NAND2BX1TS U1132 ( .AN(intDX_EWSW[19]), .B(intDY_EWSW[19]), .Y(n1012) );
OAI21X1TS U1133 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n1672), .B0(n1641), .Y(n1065) );
INVX1TS U1134 ( .A(DmP_mant_SFG_SWR[10]), .Y(n1580) );
NAND3X1TS U1135 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1644), .C(
n1682), .Y(n1382) );
NAND2BX1TS U1136 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n987) );
NAND2BX1TS U1137 ( .AN(intDX_EWSW[27]), .B(intDY_EWSW[27]), .Y(n1029) );
NOR4X2TS U1138 ( .A(Raw_mant_NRM_SWR[25]), .B(Raw_mant_NRM_SWR[24]), .C(
Raw_mant_NRM_SWR[23]), .D(Raw_mant_NRM_SWR[22]), .Y(n1366) );
NAND2BX1TS U1139 ( .AN(intDX_EWSW[21]), .B(intDY_EWSW[21]), .Y(n1004) );
NAND2BX1TS U1140 ( .AN(intDX_EWSW[13]), .B(intDY_EWSW[13]), .Y(n974) );
AO22X2TS U1141 ( .A0(n1549), .A1(n1206), .B0(n1723), .B1(
Raw_mant_NRM_SWR[25]), .Y(n582) );
XNOR2X4TS U1142 ( .A(n1205), .B(n1204), .Y(n1206) );
OAI211X1TS U1143 ( .A0(DMP_SFG[11]), .A1(n1491), .B0(DMP_SFG[10]), .C0(n1573), .Y(n1045) );
OAI211X1TS U1144 ( .A0(n1243), .A1(n951), .B0(n1242), .C0(n1241), .Y(n839)
);
NOR2X6TS U1145 ( .A(Raw_mant_NRM_SWR[10]), .B(n1050), .Y(n1068) );
NAND2X4TS U1146 ( .A(n1051), .B(n1659), .Y(n1192) );
AND4X1TS U1147 ( .A(n1379), .B(n1378), .C(exp_rslt_NRM2_EW1[4]), .D(n1093),
.Y(n1094) );
NOR3X1TS U1148 ( .A(Raw_mant_NRM_SWR[12]), .B(n1673), .C(n1050), .Y(n1365)
);
NAND2BXLTS U1149 ( .AN(intDX_EWSW[2]), .B(intDY_EWSW[2]), .Y(n993) );
OAI2BB2XLTS U1150 ( .B0(n978), .B1(n985), .A0N(n977), .A1N(n986), .Y(n981)
);
NOR4BBX2TS U1151 ( .AN(n1060), .BN(n1059), .C(n1196), .D(n1058), .Y(n1071)
);
CLKAND2X2TS U1152 ( .A(n1581), .B(DMP_SFG[8]), .Y(n1488) );
INVX4TS U1153 ( .A(n1287), .Y(n940) );
AOI222X1TS U1154 ( .A0(n1528), .A1(DMP_SFG[1]), .B0(n1528), .B1(n1527), .C0(
DMP_SFG[1]), .C1(n1527), .Y(n1557) );
INVX2TS U1155 ( .A(n1182), .Y(n1460) );
BUFX3TS U1156 ( .A(n928), .Y(n1346) );
BUFX3TS U1157 ( .A(n928), .Y(n1333) );
CLKBUFX2TS U1158 ( .A(n928), .Y(n1255) );
AO22XLTS U1159 ( .A0(n1393), .A1(Data_X[14]), .B0(n1404), .B1(intDX_EWSW[14]), .Y(n899) );
AO22XLTS U1160 ( .A0(n1401), .A1(Data_X[20]), .B0(n1404), .B1(intDX_EWSW[20]), .Y(n893) );
AO22XLTS U1161 ( .A0(n1401), .A1(Data_X[31]), .B0(n1394), .B1(intDX_EWSW[31]), .Y(n882) );
AO22XLTS U1162 ( .A0(n1450), .A1(DMP_SHT2_EWSW[10]), .B0(n1448), .B1(
DMP_SFG[10]), .Y(n738) );
AO22XLTS U1163 ( .A0(n1403), .A1(Data_X[18]), .B0(n1404), .B1(intDX_EWSW[18]), .Y(n895) );
AO22XLTS U1164 ( .A0(n1403), .A1(Data_X[2]), .B0(n1391), .B1(intDX_EWSW[2]),
.Y(n911) );
AO22XLTS U1165 ( .A0(n1401), .A1(Data_X[9]), .B0(n1391), .B1(intDX_EWSW[9]),
.Y(n904) );
AO22XLTS U1166 ( .A0(n1401), .A1(Data_X[8]), .B0(n1391), .B1(intDX_EWSW[8]),
.Y(n905) );
AO22XLTS U1167 ( .A0(n1392), .A1(Data_X[17]), .B0(n1404), .B1(intDX_EWSW[17]), .Y(n896) );
AO22XLTS U1168 ( .A0(n1401), .A1(Data_X[21]), .B0(n1394), .B1(intDX_EWSW[21]), .Y(n892) );
AO22XLTS U1169 ( .A0(n1392), .A1(Data_X[13]), .B0(n1404), .B1(intDX_EWSW[13]), .Y(n900) );
AO22XLTS U1170 ( .A0(n1392), .A1(Data_X[15]), .B0(n1404), .B1(intDX_EWSW[15]), .Y(n898) );
AO22XLTS U1171 ( .A0(n1403), .A1(Data_X[4]), .B0(n1391), .B1(intDX_EWSW[4]),
.Y(n909) );
AO22XLTS U1172 ( .A0(n1398), .A1(Data_X[5]), .B0(n1391), .B1(intDX_EWSW[5]),
.Y(n908) );
AO22XLTS U1173 ( .A0(n1398), .A1(Data_X[6]), .B0(n1391), .B1(intDX_EWSW[6]),
.Y(n907) );
AO22XLTS U1174 ( .A0(n1401), .A1(Data_X[7]), .B0(n1391), .B1(intDX_EWSW[7]),
.Y(n906) );
AO22XLTS U1175 ( .A0(n1400), .A1(intDY_EWSW[18]), .B0(n1397), .B1(Data_Y[18]), .Y(n861) );
AO22XLTS U1176 ( .A0(n1400), .A1(intDY_EWSW[20]), .B0(n1398), .B1(Data_Y[20]), .Y(n859) );
AO22XLTS U1177 ( .A0(n1400), .A1(intDY_EWSW[21]), .B0(n1405), .B1(Data_Y[21]), .Y(n858) );
AO22XLTS U1178 ( .A0(n1400), .A1(intDY_EWSW[22]), .B0(n1405), .B1(Data_Y[22]), .Y(n857) );
AO22XLTS U1179 ( .A0(n1395), .A1(intDY_EWSW[3]), .B0(n1397), .B1(Data_Y[3]),
.Y(n876) );
AO22XLTS U1180 ( .A0(n1396), .A1(intDY_EWSW[8]), .B0(n1398), .B1(Data_Y[8]),
.Y(n871) );
AO22XLTS U1181 ( .A0(n1396), .A1(intDY_EWSW[11]), .B0(n1399), .B1(Data_Y[11]), .Y(n868) );
AO22XLTS U1182 ( .A0(n1396), .A1(intDY_EWSW[15]), .B0(n1399), .B1(Data_Y[15]), .Y(n864) );
AO22XLTS U1183 ( .A0(n1396), .A1(intDY_EWSW[17]), .B0(n1399), .B1(Data_Y[17]), .Y(n862) );
AO22XLTS U1184 ( .A0(n1396), .A1(intDY_EWSW[12]), .B0(n1399), .B1(Data_Y[12]), .Y(n867) );
AO22XLTS U1185 ( .A0(n1396), .A1(intDY_EWSW[13]), .B0(n1399), .B1(Data_Y[13]), .Y(n866) );
AO22XLTS U1186 ( .A0(n1396), .A1(intDY_EWSW[14]), .B0(n1399), .B1(Data_Y[14]), .Y(n865) );
AO22XLTS U1187 ( .A0(n1394), .A1(intDX_EWSW[28]), .B0(n1398), .B1(Data_X[28]), .Y(n885) );
AO22XLTS U1188 ( .A0(n1403), .A1(Data_X[3]), .B0(n1391), .B1(intDX_EWSW[3]),
.Y(n910) );
AO22XLTS U1189 ( .A0(n1395), .A1(intDY_EWSW[5]), .B0(n1398), .B1(Data_Y[5]),
.Y(n874) );
AO22XLTS U1190 ( .A0(n1395), .A1(intDY_EWSW[0]), .B0(n1397), .B1(Data_Y[0]),
.Y(n879) );
AO22XLTS U1191 ( .A0(n1395), .A1(intDX_EWSW[30]), .B0(n1397), .B1(Data_X[30]), .Y(n883) );
AO22XLTS U1192 ( .A0(n1400), .A1(intDY_EWSW[19]), .B0(n1397), .B1(Data_Y[19]), .Y(n860) );
AO22XLTS U1193 ( .A0(n1396), .A1(intDY_EWSW[10]), .B0(n1399), .B1(Data_Y[10]), .Y(n869) );
AO22XLTS U1194 ( .A0(n1395), .A1(intDY_EWSW[6]), .B0(n1398), .B1(Data_Y[6]),
.Y(n873) );
AO22XLTS U1195 ( .A0(n1395), .A1(intDY_EWSW[7]), .B0(n1398), .B1(Data_Y[7]),
.Y(n872) );
AO22XLTS U1196 ( .A0(n1396), .A1(intDY_EWSW[9]), .B0(n1397), .B1(Data_Y[9]),
.Y(n870) );
AO22XLTS U1197 ( .A0(n1395), .A1(intDY_EWSW[2]), .B0(n1397), .B1(Data_Y[2]),
.Y(n877) );
AO22XLTS U1198 ( .A0(n1395), .A1(intDY_EWSW[4]), .B0(n1397), .B1(Data_Y[4]),
.Y(n875) );
AO22XLTS U1199 ( .A0(n1396), .A1(intDY_EWSW[16]), .B0(n1399), .B1(Data_Y[16]), .Y(n863) );
AO22XLTS U1200 ( .A0(n1395), .A1(intDX_EWSW[29]), .B0(n1397), .B1(Data_X[29]), .Y(n884) );
NAND3XLTS U1201 ( .A(n1693), .B(n987), .C(intDX_EWSW[8]), .Y(n975) );
NAND2BXLTS U1202 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n976) );
AOI222X1TS U1203 ( .A0(intDY_EWSW[4]), .A1(n1639), .B0(n997), .B1(n996),
.C0(intDY_EWSW[5]), .C1(n1662), .Y(n999) );
AOI2BB2XLTS U1204 ( .B0(intDX_EWSW[3]), .B1(n1687), .A0N(intDY_EWSW[2]),
.A1N(n995), .Y(n996) );
INVX2TS U1205 ( .A(n985), .Y(n989) );
INVX2TS U1206 ( .A(n984), .Y(n1008) );
NOR2BX1TS U1207 ( .AN(n1003), .B(n1002), .Y(n1007) );
NOR2BX1TS U1208 ( .AN(n989), .B(n988), .Y(n1003) );
OAI32X1TS U1209 ( .A0(n1001), .A1(n1000), .A2(n999), .B0(n998), .B1(n1000),
.Y(n1002) );
NOR2BX1TS U1210 ( .AN(n1005), .B(n1010), .Y(n1006) );
INVX2TS U1211 ( .A(n1049), .Y(n1063) );
AOI22X1TS U1212 ( .A0(Data_array_SWR[20]), .A1(n1537), .B0(
Data_array_SWR[24]), .B1(n1536), .Y(n1554) );
NAND2X1TS U1213 ( .A(Raw_mant_NRM_SWR[14]), .B(n1358), .Y(n1060) );
NOR2XLTS U1214 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[16]), .Y(
n1054) );
INVX2TS U1215 ( .A(n1024), .Y(n1025) );
INVX2TS U1216 ( .A(DP_OP_15J23_123_2314_n4), .Y(n1084) );
AOI2BB2XLTS U1217 ( .B0(intDX_EWSW[7]), .B1(n1681), .A0N(n1681), .A1N(
intDX_EWSW[7]), .Y(n1146) );
NAND4XLTS U1218 ( .A(n1165), .B(n1164), .C(n1163), .D(n1162), .Y(n1175) );
NAND2X1TS U1219 ( .A(n1074), .B(n1073), .Y(n1311) );
AOI222X4TS U1220 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n1323), .B0(n960), .B1(
DmP_mant_SHT1_SW[13]), .C0(n1240), .C1(DmP_mant_SHT1_SW[14]), .Y(n1246) );
AO22X2TS U1221 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n1407), .B0(
Raw_mant_NRM_SWR[0]), .B1(n1409), .Y(n1408) );
AO22XLTS U1222 ( .A0(DmP_mant_SFG_SWR[11]), .A1(n1523), .B0(n1529), .B1(n926), .Y(n930) );
INVX2TS U1223 ( .A(n1385), .Y(n1383) );
NAND2X1TS U1224 ( .A(n1664), .B(LZD_output_NRM2_EW[0]), .Y(
DP_OP_15J23_123_2314_n8) );
NAND4XLTS U1225 ( .A(n1363), .B(n1367), .C(n1362), .D(n1361), .Y(n1364) );
NOR2X2TS U1226 ( .A(n1071), .B(n942), .Y(n1376) );
OAI21XLTS U1227 ( .A0(n1369), .A1(n1368), .B0(n1367), .Y(n1375) );
AOI2BB2XLTS U1228 ( .B0(OP_FLAG_SFG), .B1(DmP_mant_SFG_SWR[16]), .A0N(
DmP_mant_SFG_SWR[16]), .A1N(n1522), .Y(n1471) );
AO22XLTS U1229 ( .A0(n1389), .A1(busy), .B0(n1388), .B1(Shift_reg_FLAGS_7[3]), .Y(n917) );
AOI2BB2XLTS U1230 ( .B0(n1464), .B1(n1432), .A0N(Shift_amount_SHT1_EWR[0]),
.A1N(n1441), .Y(n817) );
AO22XLTS U1231 ( .A0(n1464), .A1(DmP_EXP_EWSW[17]), .B0(n1456), .B1(
DmP_mant_SHT1_SW[17]), .Y(n626) );
AO22XLTS U1232 ( .A0(n1464), .A1(DmP_EXP_EWSW[16]), .B0(n1456), .B1(
DmP_mant_SHT1_SW[16]), .Y(n628) );
AO22XLTS U1233 ( .A0(n962), .A1(DmP_EXP_EWSW[7]), .B0(n1455), .B1(
DmP_mant_SHT1_SW[7]), .Y(n646) );
AO22XLTS U1234 ( .A0(n1464), .A1(DmP_EXP_EWSW[19]), .B0(n1462), .B1(
DmP_mant_SHT1_SW[19]), .Y(n622) );
AO22XLTS U1235 ( .A0(n1454), .A1(DmP_EXP_EWSW[4]), .B0(n1455), .B1(
DmP_mant_SHT1_SW[4]), .Y(n652) );
AO22XLTS U1236 ( .A0(n1464), .A1(DmP_EXP_EWSW[20]), .B0(n1462), .B1(
DmP_mant_SHT1_SW[20]), .Y(n620) );
AO22XLTS U1237 ( .A0(n962), .A1(DmP_EXP_EWSW[13]), .B0(n1456), .B1(
DmP_mant_SHT1_SW[13]), .Y(n634) );
AO22XLTS U1238 ( .A0(n962), .A1(DmP_EXP_EWSW[11]), .B0(n1456), .B1(
DmP_mant_SHT1_SW[11]), .Y(n638) );
AO22XLTS U1239 ( .A0(n962), .A1(DmP_EXP_EWSW[9]), .B0(n1456), .B1(
DmP_mant_SHT1_SW[9]), .Y(n642) );
AO22XLTS U1240 ( .A0(n1638), .A1(DmP_EXP_EWSW[6]), .B0(n1455), .B1(
DmP_mant_SHT1_SW[6]), .Y(n648) );
AO22XLTS U1241 ( .A0(n1454), .A1(DmP_EXP_EWSW[2]), .B0(n1455), .B1(
DmP_mant_SHT1_SW[2]), .Y(n656) );
AO22XLTS U1242 ( .A0(n1464), .A1(DmP_EXP_EWSW[21]), .B0(n1462), .B1(
DmP_mant_SHT1_SW[21]), .Y(n618) );
AO22XLTS U1243 ( .A0(n1454), .A1(DmP_EXP_EWSW[5]), .B0(n1455), .B1(
DmP_mant_SHT1_SW[5]), .Y(n650) );
AO22XLTS U1244 ( .A0(n1454), .A1(DmP_EXP_EWSW[1]), .B0(n1455), .B1(
DmP_mant_SHT1_SW[1]), .Y(n658) );
AO22XLTS U1245 ( .A0(n1454), .A1(DmP_EXP_EWSW[0]), .B0(n1455), .B1(
DmP_mant_SHT1_SW[0]), .Y(n660) );
AO22XLTS U1246 ( .A0(n962), .A1(DmP_EXP_EWSW[15]), .B0(n1456), .B1(
DmP_mant_SHT1_SW[15]), .Y(n630) );
AO22XLTS U1247 ( .A0(n962), .A1(DmP_EXP_EWSW[14]), .B0(n1456), .B1(
DmP_mant_SHT1_SW[14]), .Y(n632) );
AO22XLTS U1248 ( .A0(n1464), .A1(DmP_EXP_EWSW[18]), .B0(n1456), .B1(
DmP_mant_SHT1_SW[18]), .Y(n624) );
AO22XLTS U1249 ( .A0(n962), .A1(DmP_EXP_EWSW[12]), .B0(n1456), .B1(
DmP_mant_SHT1_SW[12]), .Y(n636) );
AO22XLTS U1250 ( .A0(n962), .A1(DmP_EXP_EWSW[10]), .B0(n1456), .B1(
DmP_mant_SHT1_SW[10]), .Y(n640) );
AO22XLTS U1251 ( .A0(n962), .A1(DmP_EXP_EWSW[8]), .B0(n1455), .B1(
DmP_mant_SHT1_SW[8]), .Y(n644) );
AO22XLTS U1252 ( .A0(n1454), .A1(DmP_EXP_EWSW[3]), .B0(n1455), .B1(
DmP_mant_SHT1_SW[3]), .Y(n654) );
AOI2BB2XLTS U1253 ( .B0(Raw_mant_NRM_SWR[5]), .B1(n940), .A0N(n1281), .A1N(
n948), .Y(n1282) );
AOI2BB2XLTS U1254 ( .B0(n970), .B1(n1517), .A0N(Raw_mant_NRM_SWR[0]), .A1N(
n1584), .Y(n571) );
AO22XLTS U1255 ( .A0(n1403), .A1(Data_X[1]), .B0(n1402), .B1(intDX_EWSW[1]),
.Y(n912) );
AO22XLTS U1256 ( .A0(n1405), .A1(Data_Y[31]), .B0(n1404), .B1(intDY_EWSW[31]), .Y(n848) );
AO22XLTS U1257 ( .A0(n1388), .A1(n1387), .B0(n1389), .B1(
Shift_reg_FLAGS_7[3]), .Y(n916) );
AO22XLTS U1258 ( .A0(n1450), .A1(DMP_SHT2_EWSW[12]), .B0(n1448), .B1(
DMP_SFG[12]), .Y(n732) );
AO22XLTS U1259 ( .A0(n1450), .A1(DMP_SHT2_EWSW[14]), .B0(n1448), .B1(
DMP_SFG[14]), .Y(n726) );
AO22XLTS U1260 ( .A0(n1450), .A1(DMP_SHT2_EWSW[16]), .B0(n1448), .B1(
DMP_SFG[16]), .Y(n720) );
AO22XLTS U1261 ( .A0(n1450), .A1(DMP_SHT2_EWSW[18]), .B0(n1448), .B1(
DMP_SFG[18]), .Y(n714) );
AO22XLTS U1262 ( .A0(n1450), .A1(DMP_SHT2_EWSW[20]), .B0(n1518), .B1(
DMP_SFG[20]), .Y(n708) );
AO22XLTS U1263 ( .A0(n1453), .A1(DMP_SHT2_EWSW[22]), .B0(n1518), .B1(
DMP_SFG[22]), .Y(n702) );
AO22XLTS U1264 ( .A0(n1401), .A1(Data_Y[28]), .B0(n1402), .B1(intDY_EWSW[28]), .Y(n851) );
MX2X1TS U1265 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(n923),
.Y(n692) );
MX2X1TS U1266 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(n1372),
.Y(n687) );
MX2X1TS U1267 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(n923),
.Y(n682) );
MX2X1TS U1268 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(n1372),
.Y(n677) );
OAI21XLTS U1269 ( .A0(n1702), .A1(n1348), .B0(n1344), .Y(n781) );
AO22XLTS U1270 ( .A0(n1441), .A1(n1436), .B0(n1463), .B1(
Shift_amount_SHT1_EWR[1]), .Y(n816) );
AO22XLTS U1271 ( .A0(n1450), .A1(DMP_SHT2_EWSW[13]), .B0(n1448), .B1(
DMP_SFG[13]), .Y(n729) );
AO22XLTS U1272 ( .A0(n1453), .A1(DMP_SHT2_EWSW[0]), .B0(n1483), .B1(
DMP_SFG[0]), .Y(n768) );
AO22XLTS U1273 ( .A0(n1519), .A1(n1619), .B0(n1518), .B1(DmP_mant_SFG_SWR[2]), .Y(n570) );
AO22XLTS U1274 ( .A0(n1538), .A1(DmP_mant_SFG_SWR[3]), .B0(n1465), .B1(n1603), .Y(n566) );
AO22XLTS U1275 ( .A0(n1624), .A1(DmP_mant_SFG_SWR[7]), .B0(n1623), .B1(n1545), .Y(n562) );
AO22XLTS U1276 ( .A0(n1624), .A1(DmP_mant_SFG_SWR[6]), .B0(n1623), .B1(n1560), .Y(n557) );
AO22XLTS U1277 ( .A0(n1538), .A1(DmP_mant_SFG_SWR[9]), .B0(n1465), .B1(n1185), .Y(n555) );
AO22XLTS U1278 ( .A0(n1624), .A1(DmP_mant_SFG_SWR[16]), .B0(n1465), .B1(
n1139), .Y(n523) );
AO22XLTS U1279 ( .A0(n1538), .A1(DmP_mant_SFG_SWR[18]), .B0(n1465), .B1(
n1142), .Y(n521) );
AO22XLTS U1280 ( .A0(n1444), .A1(DmP_mant_SFG_SWR[19]), .B0(n1465), .B1(
n1141), .Y(n520) );
AO22XLTS U1281 ( .A0(n1624), .A1(DmP_mant_SFG_SWR[22]), .B0(n1623), .B1(
n1622), .Y(n517) );
AO22XLTS U1282 ( .A0(n1624), .A1(DmP_mant_SFG_SWR[23]), .B0(n1465), .B1(
n1137), .Y(n516) );
AO22XLTS U1283 ( .A0(n1464), .A1(DmP_EXP_EWSW[22]), .B0(n1462), .B1(
DmP_mant_SHT1_SW[22]), .Y(n616) );
AO22XLTS U1284 ( .A0(n1623), .A1(DMP_SHT2_EWSW[8]), .B0(n1483), .B1(
DMP_SFG[8]), .Y(n744) );
AO22XLTS U1285 ( .A0(n1623), .A1(DMP_SHT2_EWSW[4]), .B0(n1483), .B1(
DMP_SFG[4]), .Y(n756) );
AO22XLTS U1286 ( .A0(n1623), .A1(DMP_SHT2_EWSW[6]), .B0(n1483), .B1(
DMP_SFG[6]), .Y(n750) );
AO22XLTS U1287 ( .A0(n1180), .A1(DmP_mant_SFG_SWR[12]), .B0(n1465), .B1(
n1179), .Y(n549) );
AO22XLTS U1288 ( .A0(n1450), .A1(DMP_SHT2_EWSW[15]), .B0(n1448), .B1(
DMP_SFG[15]), .Y(n723) );
AO22XLTS U1289 ( .A0(n1450), .A1(DMP_SHT2_EWSW[17]), .B0(n1448), .B1(
DMP_SFG[17]), .Y(n717) );
AO22XLTS U1290 ( .A0(n1450), .A1(DMP_SHT2_EWSW[19]), .B0(n1448), .B1(
DMP_SFG[19]), .Y(n711) );
AO22XLTS U1291 ( .A0(n1453), .A1(DMP_SHT2_EWSW[21]), .B0(n1518), .B1(
DMP_SFG[21]), .Y(n705) );
AO22XLTS U1292 ( .A0(n1623), .A1(DMP_SHT2_EWSW[5]), .B0(n1483), .B1(
DMP_SFG[5]), .Y(n753) );
AO22XLTS U1293 ( .A0(n1623), .A1(DMP_SHT2_EWSW[7]), .B0(n1483), .B1(
DMP_SFG[7]), .Y(n747) );
AO22XLTS U1294 ( .A0(n1623), .A1(DMP_SHT2_EWSW[11]), .B0(n1448), .B1(
DMP_SFG[11]), .Y(n735) );
AO22XLTS U1295 ( .A0(n1619), .A1(DMP_SHT2_EWSW[1]), .B0(n1483), .B1(
DMP_SFG[1]), .Y(n765) );
AO22XLTS U1296 ( .A0(n1623), .A1(DMP_SHT2_EWSW[9]), .B0(n1483), .B1(
DMP_SFG[9]), .Y(n741) );
OAI211XLTS U1297 ( .A0(n1310), .A1(n950), .B0(n1306), .C0(n1305), .Y(n827)
);
OAI211XLTS U1298 ( .A0(n1318), .A1(n950), .B0(n1317), .C0(n1316), .Y(n826)
);
AO22XLTS U1299 ( .A0(n1403), .A1(Data_X[0]), .B0(n1402), .B1(intDX_EWSW[0]),
.Y(n913) );
AOI2BB2XLTS U1300 ( .B0(n1387), .B1(n1499), .A0N(Raw_mant_NRM_SWR[1]), .A1N(
n1584), .Y(n577) );
AOI2BB2XLTS U1301 ( .B0(n1387), .B1(n1533), .A0N(Raw_mant_NRM_SWR[5]), .A1N(
n1584), .Y(n565) );
AOI2BB2XLTS U1302 ( .B0(DMP_SFG[3]), .B1(n1540), .A0N(n1540), .A1N(
DMP_SFG[3]), .Y(n1531) );
AO22XLTS U1303 ( .A0(n1401), .A1(Data_X[23]), .B0(n1394), .B1(intDX_EWSW[23]), .Y(n890) );
AO22XLTS U1304 ( .A0(n1400), .A1(intDY_EWSW[25]), .B0(n1405), .B1(Data_Y[25]), .Y(n854) );
AO22XLTS U1305 ( .A0(n1400), .A1(intDY_EWSW[26]), .B0(n1405), .B1(Data_Y[26]), .Y(n853) );
AO22XLTS U1306 ( .A0(n1400), .A1(intDY_EWSW[23]), .B0(n1405), .B1(Data_Y[23]), .Y(n856) );
AO22XLTS U1307 ( .A0(n1394), .A1(intDX_EWSW[25]), .B0(n1398), .B1(Data_X[25]), .Y(n888) );
AO22XLTS U1308 ( .A0(n1394), .A1(intDX_EWSW[26]), .B0(n1398), .B1(Data_X[26]), .Y(n887) );
AO22XLTS U1309 ( .A0(n1394), .A1(intDX_EWSW[24]), .B0(n1399), .B1(Data_X[24]), .Y(n889) );
AO22XLTS U1310 ( .A0(n1564), .A1(Raw_mant_NRM_SWR[6]), .B0(n1584), .B1(n1563), .Y(n556) );
MX2X1TS U1311 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(n1372),
.Y(n697) );
AO22XLTS U1312 ( .A0(n1726), .A1(ZERO_FLAG_SHT1SHT2), .B0(n1610), .B1(
zero_flag), .Y(n603) );
AO22XLTS U1313 ( .A0(n1400), .A1(intDY_EWSW[24]), .B0(n1393), .B1(Data_Y[24]), .Y(n855) );
AO22XLTS U1314 ( .A0(n1403), .A1(Data_Y[30]), .B0(n1402), .B1(intDY_EWSW[30]), .Y(n849) );
AO22XLTS U1315 ( .A0(n1401), .A1(Data_Y[29]), .B0(n1402), .B1(intDY_EWSW[29]), .Y(n850) );
AOI2BB2XLTS U1316 ( .B0(beg_OP), .B1(n1644), .A0N(n1644), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n1077) );
MX2X1TS U1317 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(n1372),
.Y(n667) );
MX2X1TS U1318 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(n923),
.Y(n672) );
AO22XLTS U1319 ( .A0(n1395), .A1(intDY_EWSW[1]), .B0(n1397), .B1(Data_Y[1]),
.Y(n878) );
AO22XLTS U1320 ( .A0(n1400), .A1(intDY_EWSW[27]), .B0(n1399), .B1(Data_Y[27]), .Y(n852) );
AO22XLTS U1321 ( .A0(n1444), .A1(DMP_SFG[3]), .B0(n1465), .B1(
DMP_SHT2_EWSW[3]), .Y(n759) );
MX2X1TS U1322 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(n923),
.Y(n662) );
OAI211XLTS U1323 ( .A0(n1303), .A1(n1211), .B0(n1299), .C0(n1298), .Y(n829)
);
AO22XLTS U1324 ( .A0(n1585), .A1(Raw_mant_NRM_SWR[10]), .B0(n1584), .B1(
n1583), .Y(n550) );
AO21XLTS U1325 ( .A0(LZD_output_NRM2_EW[1]), .A1(n943), .B0(n1376), .Y(n573)
);
AO21XLTS U1326 ( .A0(LZD_output_NRM2_EW[4]), .A1(n944), .B0(n1357), .Y(n579)
);
AOI2BB2XLTS U1327 ( .B0(n1549), .B1(n1493), .A0N(Raw_mant_NRM_SWR[13]),
.A1N(n1584), .Y(n580) );
AO22X1TS U1328 ( .A0(n1549), .A1(n1046), .B0(n1564), .B1(
Raw_mant_NRM_SWR[22]), .Y(n585) );
AO22XLTS U1329 ( .A0(n1549), .A1(n1083), .B0(n1564), .B1(
Raw_mant_NRM_SWR[20]), .Y(n587) );
AO22XLTS U1330 ( .A0(n1585), .A1(Raw_mant_NRM_SWR[17]), .B0(n1476), .B1(
n1475), .Y(n590) );
AO22XLTS U1331 ( .A0(n1585), .A1(Raw_mant_NRM_SWR[16]), .B0(n1476), .B1(
n1472), .Y(n591) );
AO22XLTS U1332 ( .A0(n1549), .A1(n1129), .B0(n1564), .B1(
Raw_mant_NRM_SWR[15]), .Y(n592) );
AO22XLTS U1333 ( .A0(n1585), .A1(Raw_mant_NRM_SWR[14]), .B0(n1584), .B1(
n1469), .Y(n593) );
AO22XLTS U1334 ( .A0(n1372), .A1(SIGN_FLAG_NRM), .B0(n944), .B1(
SIGN_FLAG_SHT1SHT2), .Y(n595) );
AO22XLTS U1335 ( .A0(n1476), .A1(SIGN_FLAG_SFG), .B0(n1564), .B1(
SIGN_FLAG_NRM), .Y(n596) );
AO22XLTS U1336 ( .A0(n1619), .A1(SIGN_FLAG_SHT2), .B0(n1518), .B1(
SIGN_FLAG_SFG), .Y(n597) );
AO22XLTS U1337 ( .A0(busy), .A1(SIGN_FLAG_SHT1), .B0(n938), .B1(
SIGN_FLAG_SHT2), .Y(n598) );
AO22XLTS U1338 ( .A0(n962), .A1(SIGN_FLAG_EXP), .B0(n1466), .B1(
SIGN_FLAG_SHT1), .Y(n599) );
AO22XLTS U1339 ( .A0(n1538), .A1(n1522), .B0(n1465), .B1(OP_FLAG_SHT2), .Y(
n600) );
AO22XLTS U1340 ( .A0(busy), .A1(OP_FLAG_SHT1), .B0(n1768), .B1(OP_FLAG_SHT2),
.Y(n601) );
AO22XLTS U1341 ( .A0(n1464), .A1(OP_FLAG_EXP), .B0(n1463), .B1(OP_FLAG_SHT1),
.Y(n602) );
AO22XLTS U1342 ( .A0(n1372), .A1(ZERO_FLAG_NRM), .B0(n943), .B1(
ZERO_FLAG_SHT1SHT2), .Y(n604) );
AO22XLTS U1343 ( .A0(n1476), .A1(ZERO_FLAG_SFG), .B0(n1564), .B1(
ZERO_FLAG_NRM), .Y(n605) );
AO22XLTS U1344 ( .A0(n1619), .A1(ZERO_FLAG_SHT2), .B0(n1518), .B1(
ZERO_FLAG_SFG), .Y(n606) );
AO22XLTS U1345 ( .A0(busy), .A1(ZERO_FLAG_SHT1), .B0(n938), .B1(
ZERO_FLAG_SHT2), .Y(n607) );
AO22XLTS U1346 ( .A0(n1464), .A1(ZERO_FLAG_EXP), .B0(n1462), .B1(
ZERO_FLAG_SHT1), .Y(n608) );
OAI21XLTS U1347 ( .A0(n1650), .A1(n1280), .B0(n1260), .Y(n623) );
OAI21XLTS U1348 ( .A0(n1704), .A1(n1280), .B0(n1254), .Y(n625) );
OAI21XLTS U1349 ( .A0(n1688), .A1(n1280), .B0(n1252), .Y(n627) );
OAI21XLTS U1350 ( .A0(n1698), .A1(n1280), .B0(n1267), .Y(n629) );
OAI21XLTS U1351 ( .A0(n1647), .A1(n1280), .B0(n1279), .Y(n631) );
OAI21XLTS U1352 ( .A0(n1666), .A1(n1277), .B0(n1271), .Y(n641) );
OAI21XLTS U1353 ( .A0(n1689), .A1(n1277), .B0(n1276), .Y(n643) );
OAI21XLTS U1354 ( .A0(n1681), .A1(n1277), .B0(n1266), .Y(n647) );
OAI21XLTS U1355 ( .A0(n1680), .A1(n1277), .B0(n1257), .Y(n649) );
OAI21XLTS U1356 ( .A0(n1694), .A1(n1277), .B0(n1258), .Y(n657) );
AO22XLTS U1357 ( .A0(n1549), .A1(DMP_SFG[30]), .B0(n1564), .B1(
DMP_exp_NRM_EW[7]), .Y(n663) );
AO22XLTS U1358 ( .A0(n1619), .A1(DMP_SHT2_EWSW[30]), .B0(n1444), .B1(
DMP_SFG[30]), .Y(n664) );
AO22XLTS U1359 ( .A0(busy), .A1(DMP_SHT1_EWSW[30]), .B0(n938), .B1(
DMP_SHT2_EWSW[30]), .Y(n665) );
AO22XLTS U1360 ( .A0(n1454), .A1(DMP_EXP_EWSW[30]), .B0(n1455), .B1(
DMP_SHT1_EWSW[30]), .Y(n666) );
AO22XLTS U1361 ( .A0(n1549), .A1(DMP_SFG[29]), .B0(n1564), .B1(
DMP_exp_NRM_EW[6]), .Y(n668) );
AO22XLTS U1362 ( .A0(n1453), .A1(DMP_SHT2_EWSW[29]), .B0(n1444), .B1(
DMP_SFG[29]), .Y(n669) );
AO22XLTS U1363 ( .A0(busy), .A1(DMP_SHT1_EWSW[29]), .B0(n938), .B1(
DMP_SHT2_EWSW[29]), .Y(n670) );
AO22XLTS U1364 ( .A0(n1454), .A1(DMP_EXP_EWSW[29]), .B0(n1466), .B1(
DMP_SHT1_EWSW[29]), .Y(n671) );
AO22XLTS U1365 ( .A0(n1476), .A1(DMP_SFG[28]), .B0(n1723), .B1(
DMP_exp_NRM_EW[5]), .Y(n673) );
AO22XLTS U1366 ( .A0(n1453), .A1(DMP_SHT2_EWSW[28]), .B0(n1444), .B1(
DMP_SFG[28]), .Y(n674) );
AO22XLTS U1367 ( .A0(busy), .A1(DMP_SHT1_EWSW[28]), .B0(n938), .B1(
DMP_SHT2_EWSW[28]), .Y(n675) );
AO22XLTS U1368 ( .A0(n1454), .A1(DMP_EXP_EWSW[28]), .B0(n1466), .B1(
DMP_SHT1_EWSW[28]), .Y(n676) );
AO22XLTS U1369 ( .A0(n1476), .A1(DMP_SFG[27]), .B0(n1723), .B1(
DMP_exp_NRM_EW[4]), .Y(n678) );
AO22XLTS U1370 ( .A0(n1453), .A1(DMP_SHT2_EWSW[27]), .B0(n1444), .B1(
DMP_SFG[27]), .Y(n679) );
AO22XLTS U1371 ( .A0(busy), .A1(DMP_SHT1_EWSW[27]), .B0(n938), .B1(
DMP_SHT2_EWSW[27]), .Y(n680) );
AO22XLTS U1372 ( .A0(n1454), .A1(DMP_EXP_EWSW[27]), .B0(n1466), .B1(
DMP_SHT1_EWSW[27]), .Y(n681) );
AO22XLTS U1373 ( .A0(n1476), .A1(DMP_SFG[26]), .B0(n1723), .B1(
DMP_exp_NRM_EW[3]), .Y(n683) );
AO22XLTS U1374 ( .A0(n1453), .A1(DMP_SHT2_EWSW[26]), .B0(n1518), .B1(
DMP_SFG[26]), .Y(n684) );
AO22XLTS U1375 ( .A0(n1452), .A1(DMP_SHT1_EWSW[26]), .B0(n938), .B1(
DMP_SHT2_EWSW[26]), .Y(n685) );
AO22XLTS U1376 ( .A0(n1441), .A1(DMP_EXP_EWSW[26]), .B0(n1466), .B1(
DMP_SHT1_EWSW[26]), .Y(n686) );
AO22XLTS U1377 ( .A0(n1476), .A1(DMP_SFG[25]), .B0(n1723), .B1(
DMP_exp_NRM_EW[2]), .Y(n688) );
AO22XLTS U1378 ( .A0(n1453), .A1(DMP_SHT2_EWSW[25]), .B0(n1518), .B1(
DMP_SFG[25]), .Y(n689) );
AO22XLTS U1379 ( .A0(n961), .A1(DMP_SHT1_EWSW[25]), .B0(n1451), .B1(
DMP_SHT2_EWSW[25]), .Y(n690) );
AO22XLTS U1380 ( .A0(n1638), .A1(DMP_EXP_EWSW[25]), .B0(n1466), .B1(
DMP_SHT1_EWSW[25]), .Y(n691) );
AO22XLTS U1381 ( .A0(n1476), .A1(DMP_SFG[24]), .B0(n1723), .B1(
DMP_exp_NRM_EW[1]), .Y(n693) );
AO22XLTS U1382 ( .A0(n1453), .A1(DMP_SHT2_EWSW[24]), .B0(n1518), .B1(
DMP_SFG[24]), .Y(n694) );
AO22XLTS U1383 ( .A0(n1452), .A1(DMP_SHT1_EWSW[24]), .B0(n1451), .B1(
DMP_SHT2_EWSW[24]), .Y(n695) );
AO22XLTS U1384 ( .A0(n1638), .A1(DMP_EXP_EWSW[24]), .B0(n1466), .B1(
DMP_SHT1_EWSW[24]), .Y(n696) );
AO22XLTS U1385 ( .A0(n1476), .A1(DMP_SFG[23]), .B0(n1723), .B1(
DMP_exp_NRM_EW[0]), .Y(n698) );
AO22XLTS U1386 ( .A0(n1453), .A1(DMP_SHT2_EWSW[23]), .B0(n1518), .B1(
DMP_SFG[23]), .Y(n699) );
AO22XLTS U1387 ( .A0(n1452), .A1(DMP_SHT1_EWSW[23]), .B0(n1451), .B1(
DMP_SHT2_EWSW[23]), .Y(n700) );
AO22XLTS U1388 ( .A0(n1638), .A1(DMP_EXP_EWSW[23]), .B0(n1466), .B1(
DMP_SHT1_EWSW[23]), .Y(n701) );
AO22XLTS U1389 ( .A0(n1452), .A1(DMP_SHT1_EWSW[22]), .B0(n1451), .B1(
DMP_SHT2_EWSW[22]), .Y(n703) );
AO22XLTS U1390 ( .A0(n1638), .A1(DMP_EXP_EWSW[22]), .B0(n1466), .B1(
DMP_SHT1_EWSW[22]), .Y(n704) );
AO22XLTS U1391 ( .A0(n1452), .A1(DMP_SHT1_EWSW[21]), .B0(n1451), .B1(
DMP_SHT2_EWSW[21]), .Y(n706) );
AO22XLTS U1392 ( .A0(n1638), .A1(DMP_EXP_EWSW[21]), .B0(n1466), .B1(
DMP_SHT1_EWSW[21]), .Y(n707) );
AO22XLTS U1393 ( .A0(n1452), .A1(DMP_SHT1_EWSW[20]), .B0(n1451), .B1(
DMP_SHT2_EWSW[20]), .Y(n709) );
AO22XLTS U1394 ( .A0(n1638), .A1(DMP_EXP_EWSW[20]), .B0(n1449), .B1(
DMP_SHT1_EWSW[20]), .Y(n710) );
AO22XLTS U1395 ( .A0(n1452), .A1(DMP_SHT1_EWSW[19]), .B0(n1451), .B1(
DMP_SHT2_EWSW[19]), .Y(n712) );
AO22XLTS U1396 ( .A0(n1638), .A1(DMP_EXP_EWSW[19]), .B0(n1449), .B1(
DMP_SHT1_EWSW[19]), .Y(n713) );
AO22XLTS U1397 ( .A0(n1452), .A1(DMP_SHT1_EWSW[18]), .B0(n1451), .B1(
DMP_SHT2_EWSW[18]), .Y(n715) );
AO22XLTS U1398 ( .A0(n1638), .A1(DMP_EXP_EWSW[18]), .B0(n1449), .B1(
DMP_SHT1_EWSW[18]), .Y(n716) );
AO22XLTS U1399 ( .A0(n1452), .A1(DMP_SHT1_EWSW[17]), .B0(n1451), .B1(
DMP_SHT2_EWSW[17]), .Y(n718) );
AO22XLTS U1400 ( .A0(n1447), .A1(DMP_EXP_EWSW[17]), .B0(n1449), .B1(
DMP_SHT1_EWSW[17]), .Y(n719) );
AO22XLTS U1401 ( .A0(n1452), .A1(DMP_SHT1_EWSW[16]), .B0(n1451), .B1(
DMP_SHT2_EWSW[16]), .Y(n721) );
AO22XLTS U1402 ( .A0(n1447), .A1(DMP_EXP_EWSW[16]), .B0(n1449), .B1(
DMP_SHT1_EWSW[16]), .Y(n722) );
AO22XLTS U1403 ( .A0(n937), .A1(DMP_SHT1_EWSW[15]), .B0(n1768), .B1(
DMP_SHT2_EWSW[15]), .Y(n724) );
AO22XLTS U1404 ( .A0(n1447), .A1(DMP_EXP_EWSW[15]), .B0(n1449), .B1(
DMP_SHT1_EWSW[15]), .Y(n725) );
AO22XLTS U1405 ( .A0(n937), .A1(DMP_SHT1_EWSW[14]), .B0(n1768), .B1(
DMP_SHT2_EWSW[14]), .Y(n727) );
AO22XLTS U1406 ( .A0(n1447), .A1(DMP_EXP_EWSW[14]), .B0(n1449), .B1(
DMP_SHT1_EWSW[14]), .Y(n728) );
AO22XLTS U1407 ( .A0(n937), .A1(DMP_SHT1_EWSW[13]), .B0(n1768), .B1(
DMP_SHT2_EWSW[13]), .Y(n730) );
AO22XLTS U1408 ( .A0(n1447), .A1(DMP_EXP_EWSW[13]), .B0(n1449), .B1(
DMP_SHT1_EWSW[13]), .Y(n731) );
AO22XLTS U1409 ( .A0(n937), .A1(DMP_SHT1_EWSW[12]), .B0(n1768), .B1(
DMP_SHT2_EWSW[12]), .Y(n733) );
AO22XLTS U1410 ( .A0(n1447), .A1(DMP_EXP_EWSW[12]), .B0(n1449), .B1(
DMP_SHT1_EWSW[12]), .Y(n734) );
AO22XLTS U1411 ( .A0(n937), .A1(DMP_SHT1_EWSW[11]), .B0(n1768), .B1(
DMP_SHT2_EWSW[11]), .Y(n736) );
AO22XLTS U1412 ( .A0(n1447), .A1(DMP_EXP_EWSW[11]), .B0(n1449), .B1(
DMP_SHT1_EWSW[11]), .Y(n737) );
AO22XLTS U1413 ( .A0(n937), .A1(DMP_SHT1_EWSW[10]), .B0(n1768), .B1(
DMP_SHT2_EWSW[10]), .Y(n739) );
AO22XLTS U1414 ( .A0(n1447), .A1(DMP_EXP_EWSW[10]), .B0(n1446), .B1(
DMP_SHT1_EWSW[10]), .Y(n740) );
AO22XLTS U1415 ( .A0(n937), .A1(DMP_SHT1_EWSW[9]), .B0(n1768), .B1(
DMP_SHT2_EWSW[9]), .Y(n742) );
AO22XLTS U1416 ( .A0(n1447), .A1(DMP_EXP_EWSW[9]), .B0(n1446), .B1(
DMP_SHT1_EWSW[9]), .Y(n743) );
AO22XLTS U1417 ( .A0(n961), .A1(DMP_SHT1_EWSW[8]), .B0(n1768), .B1(
DMP_SHT2_EWSW[8]), .Y(n745) );
AO22XLTS U1418 ( .A0(n1447), .A1(DMP_EXP_EWSW[8]), .B0(n1446), .B1(
DMP_SHT1_EWSW[8]), .Y(n746) );
AO22XLTS U1419 ( .A0(n961), .A1(DMP_SHT1_EWSW[7]), .B0(n938), .B1(
DMP_SHT2_EWSW[7]), .Y(n748) );
AO22XLTS U1420 ( .A0(n1445), .A1(DMP_EXP_EWSW[7]), .B0(n1446), .B1(
DMP_SHT1_EWSW[7]), .Y(n749) );
AO22XLTS U1421 ( .A0(n961), .A1(DMP_SHT1_EWSW[6]), .B0(n939), .B1(
DMP_SHT2_EWSW[6]), .Y(n751) );
AO22XLTS U1422 ( .A0(n1445), .A1(DMP_EXP_EWSW[6]), .B0(n1446), .B1(
DMP_SHT1_EWSW[6]), .Y(n752) );
AO22XLTS U1423 ( .A0(n961), .A1(DMP_SHT1_EWSW[5]), .B0(n939), .B1(
DMP_SHT2_EWSW[5]), .Y(n754) );
AO22XLTS U1424 ( .A0(n1445), .A1(DMP_EXP_EWSW[5]), .B0(n1446), .B1(
DMP_SHT1_EWSW[5]), .Y(n755) );
AO22XLTS U1425 ( .A0(n961), .A1(DMP_SHT1_EWSW[4]), .B0(n939), .B1(
DMP_SHT2_EWSW[4]), .Y(n757) );
AO22XLTS U1426 ( .A0(n1445), .A1(DMP_EXP_EWSW[4]), .B0(n1446), .B1(
DMP_SHT1_EWSW[4]), .Y(n758) );
AO22XLTS U1427 ( .A0(n961), .A1(DMP_SHT1_EWSW[3]), .B0(n939), .B1(
DMP_SHT2_EWSW[3]), .Y(n760) );
AO22XLTS U1428 ( .A0(n1445), .A1(DMP_EXP_EWSW[3]), .B0(n1446), .B1(
DMP_SHT1_EWSW[3]), .Y(n761) );
AO22XLTS U1429 ( .A0(n1180), .A1(DMP_SFG[2]), .B0(n1465), .B1(
DMP_SHT2_EWSW[2]), .Y(n762) );
AO22XLTS U1430 ( .A0(n961), .A1(DMP_SHT1_EWSW[2]), .B0(n939), .B1(
DMP_SHT2_EWSW[2]), .Y(n763) );
AO22XLTS U1431 ( .A0(n1445), .A1(DMP_EXP_EWSW[2]), .B0(n1446), .B1(
DMP_SHT1_EWSW[2]), .Y(n764) );
AO22XLTS U1432 ( .A0(n961), .A1(DMP_SHT1_EWSW[1]), .B0(n939), .B1(
DMP_SHT2_EWSW[1]), .Y(n766) );
AO22XLTS U1433 ( .A0(n1445), .A1(DMP_EXP_EWSW[1]), .B0(n1446), .B1(
DMP_SHT1_EWSW[1]), .Y(n767) );
AO22XLTS U1434 ( .A0(n961), .A1(DMP_SHT1_EWSW[0]), .B0(n939), .B1(
DMP_SHT2_EWSW[0]), .Y(n769) );
AO22XLTS U1435 ( .A0(n1445), .A1(DMP_EXP_EWSW[0]), .B0(n1725), .B1(
DMP_SHT1_EWSW[0]), .Y(n770) );
AO22XLTS U1436 ( .A0(n1355), .A1(n1442), .B0(ZERO_FLAG_EXP), .B1(n1443), .Y(
n772) );
AO21XLTS U1437 ( .A0(OP_FLAG_EXP), .A1(n1443), .B0(n1442), .Y(n773) );
OAI21XLTS U1438 ( .A0(n1691), .A1(n1348), .B0(n1347), .Y(n783) );
OAI21XLTS U1439 ( .A0(n1698), .A1(n1348), .B0(n1320), .Y(n788) );
OAI21XLTS U1440 ( .A0(n1697), .A1(n1348), .B0(n1329), .Y(n790) );
OAI21XLTS U1441 ( .A0(n1690), .A1(n1348), .B0(n1043), .Y(n791) );
OAI21XLTS U1442 ( .A0(n1681), .A1(n1335), .B0(n1319), .Y(n797) );
OAI21XLTS U1443 ( .A0(n1680), .A1(n1335), .B0(n1232), .Y(n798) );
OAI21XLTS U1444 ( .A0(n1645), .A1(n1335), .B0(n1230), .Y(n799) );
OAI21XLTS U1445 ( .A0(n1695), .A1(n1335), .B0(n1231), .Y(n800) );
OAI21XLTS U1446 ( .A0(n1687), .A1(n1335), .B0(n1228), .Y(n801) );
AO22XLTS U1447 ( .A0(n1445), .A1(n1136), .B0(n1725), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n813) );
AO22XLTS U1448 ( .A0(n1445), .A1(n1131), .B0(n1725), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n814) );
AO22XLTS U1449 ( .A0(n1441), .A1(n1440), .B0(n1725), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n815) );
AO22XLTS U1450 ( .A0(n1388), .A1(n1458), .B0(n1389), .B1(n1390), .Y(n920) );
INVX2TS U1451 ( .A(n954), .Y(n1595) );
INVX2TS U1452 ( .A(n1604), .Y(n1613) );
NAND2X1TS U1453 ( .A(n1376), .B(n1212), .Y(n1225) );
AND2X2TS U1454 ( .A(n1210), .B(n1429), .Y(n927) );
AND2X4TS U1455 ( .A(n1458), .B(n1042), .Y(n928) );
BUFX3TS U1456 ( .A(n1047), .Y(n1428) );
INVX2TS U1457 ( .A(n937), .Y(n939) );
CLKINVX3TS U1458 ( .A(rst), .Y(n1124) );
ADDFHX2TS U1459 ( .A(DMP_SFG[13]), .B(n1128), .CI(n1127), .CO(n1470), .S(
n1129) );
INVX2TS U1460 ( .A(n1225), .Y(n933) );
INVX2TS U1461 ( .A(n1225), .Y(n934) );
INVX2TS U1462 ( .A(n1726), .Y(n935) );
INVX2TS U1463 ( .A(n937), .Y(n938) );
INVX2TS U1464 ( .A(n1372), .Y(n942) );
INVX2TS U1465 ( .A(n923), .Y(n943) );
INVX2TS U1466 ( .A(n923), .Y(n944) );
INVX2TS U1467 ( .A(n1595), .Y(n945) );
INVX2TS U1468 ( .A(n945), .Y(n946) );
INVX2TS U1469 ( .A(n945), .Y(n947) );
INVX2TS U1470 ( .A(n1315), .Y(n948) );
INVX2TS U1471 ( .A(n927), .Y(n949) );
INVX2TS U1472 ( .A(n927), .Y(n950) );
INVX2TS U1473 ( .A(n927), .Y(n951) );
INVX2TS U1474 ( .A(n1429), .Y(n952) );
NAND2X1TS U1475 ( .A(n1076), .B(n1075), .Y(n822) );
BUFX3TS U1476 ( .A(n1124), .Y(n1123) );
CLKBUFX3TS U1477 ( .A(n1124), .Y(n1122) );
AOI221X1TS U1478 ( .A0(n1700), .A1(intDX_EWSW[27]), .B0(intDY_EWSW[28]),
.B1(n1703), .C0(n1144), .Y(n1148) );
AOI222X4TS U1479 ( .A0(Data_array_SWR[20]), .A1(n1551), .B0(
Data_array_SWR[16]), .B1(n1550), .C0(Data_array_SWR[24]), .C1(n1101),
.Y(n1485) );
AOI222X4TS U1480 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n1407), .B0(n958), .B1(
DmP_mant_SHT1_SW[21]), .C0(n1240), .C1(DmP_mant_SHT1_SW[22]), .Y(n1268) );
INVX2TS U1481 ( .A(n930), .Y(n953) );
NOR2XLTS U1482 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .Y(n1194)
);
INVX2TS U1483 ( .A(n924), .Y(n954) );
AOI222X2TS U1484 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1407), .B0(
DmP_mant_SHT1_SW[20]), .B1(n1240), .C0(n959), .C1(DmP_mant_SHT1_SW[19]), .Y(n1281) );
AOI222X1TS U1485 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1323), .B0(n958), .B1(
DmP_mant_SHT1_SW[11]), .C0(n1240), .C1(DmP_mant_SHT1_SW[12]), .Y(n1237) );
AOI222X1TS U1486 ( .A0(Raw_mant_NRM_SWR[14]), .A1(n1323), .B0(n960), .B1(
DmP_mant_SHT1_SW[9]), .C0(n1072), .C1(DmP_mant_SHT1_SW[10]), .Y(n1300)
);
AOI222X4TS U1487 ( .A0(Data_array_SWR[19]), .A1(n1536), .B0(
Data_array_SWR[23]), .B1(n1494), .C0(Data_array_SWR[15]), .C1(n1537),
.Y(n1513) );
NAND2X4TS U1488 ( .A(n1198), .B(Raw_mant_NRM_SWR[0]), .Y(n1199) );
INVX2TS U1489 ( .A(Data_array_SWR[14]), .Y(n955) );
AOI221X1TS U1490 ( .A0(n1666), .A1(intDX_EWSW[10]), .B0(intDX_EWSW[11]),
.B1(n1676), .C0(n1159), .Y(n1164) );
AOI221X1TS U1491 ( .A0(n1648), .A1(intDX_EWSW[22]), .B0(intDX_EWSW[23]),
.B1(n1702), .C0(n1153), .Y(n1154) );
AOI221X1TS U1492 ( .A0(n1697), .A1(intDX_EWSW[14]), .B0(intDX_EWSW[15]),
.B1(n1647), .C0(n1161), .Y(n1162) );
AOI221X1TS U1493 ( .A0(n1699), .A1(intDX_EWSW[20]), .B0(intDX_EWSW[21]),
.B1(n1691), .C0(n1152), .Y(n1155) );
AOI221X1TS U1494 ( .A0(n1696), .A1(intDX_EWSW[12]), .B0(intDX_EWSW[13]),
.B1(n1690), .C0(n1160), .Y(n1163) );
OAI2BB2XLTS U1495 ( .B0(intDY_EWSW[0]), .B1(n992), .A0N(intDX_EWSW[1]),
.A1N(n1692), .Y(n994) );
AOI221X1TS U1496 ( .A0(n1265), .A1(intDX_EWSW[1]), .B0(intDX_EWSW[17]), .B1(
n1688), .C0(n1150), .Y(n1157) );
INVX2TS U1497 ( .A(n1047), .Y(n956) );
NOR2X4TS U1498 ( .A(n1460), .B(n1381), .Y(n1604) );
OAI2BB1X2TS U1499 ( .A0N(n1095), .A1N(n1098), .B0(n1726), .Y(n1381) );
OAI21XLTS U1500 ( .A0(DmP_EXP_EWSW[25]), .A1(n967), .B0(n1437), .Y(n1438) );
OAI31XLTS U1501 ( .A0(n1355), .A1(n1354), .A2(n1459), .B0(n1353), .Y(n771)
);
NOR2X2TS U1502 ( .A(n966), .B(DMP_EXP_EWSW[23]), .Y(n1435) );
XNOR2X2TS U1503 ( .A(DMP_exp_NRM2_EW[0]), .B(n968), .Y(n1377) );
BUFX3TS U1504 ( .A(n1124), .Y(n1126) );
AOI2BB2X2TS U1505 ( .B0(n1523), .B1(DmP_mant_SFG_SWR[3]), .A0N(
DmP_mant_SFG_SWR[3]), .A1N(n1522), .Y(n1527) );
AOI2BB2X2TS U1506 ( .B0(n1523), .B1(DmP_mant_SFG_SWR[7]), .A0N(
DmP_mant_SFG_SWR[7]), .A1N(OP_FLAG_SFG), .Y(n1541) );
AOI2BB2X2TS U1507 ( .B0(n1523), .B1(DmP_mant_SFG_SWR[9]), .A0N(
DmP_mant_SFG_SWR[9]), .A1N(n1522), .Y(n1567) );
AOI22X2TS U1508 ( .A0(Data_array_SWR[21]), .A1(n1536), .B0(
Data_array_SWR[17]), .B1(n1537), .Y(n1188) );
OAI211XLTS U1509 ( .A0(n1300), .A1(n950), .B0(n1239), .C0(n1238), .Y(n833)
);
AOI22X2TS U1510 ( .A0(n1530), .A1(n931), .B0(DmP_mant_SFG_SWR[5]), .B1(n1529), .Y(n1540) );
OAI21XLTS U1511 ( .A0(n1349), .A1(intDX_EWSW[31]), .B0(n1458), .Y(n1178) );
OAI2BB1X1TS U1512 ( .A0N(n1491), .A1N(DMP_SFG[11]), .B0(n1045), .Y(n1467) );
AOI222X4TS U1513 ( .A0(DMP_SFG[9]), .A1(n953), .B0(DMP_SFG[9]), .B1(n1488),
.C0(n953), .C1(n1488), .Y(n1572) );
INVX2TS U1514 ( .A(n929), .Y(n958) );
INVX2TS U1515 ( .A(n929), .Y(n959) );
INVX2TS U1516 ( .A(n929), .Y(n960) );
AOI222X4TS U1517 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n1323), .B0(n958), .B1(
DmP_mant_SHT1_SW[16]), .C0(n1072), .C1(DmP_mant_SHT1_SW[17]), .Y(n1288) );
AOI222X4TS U1518 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n1323), .B0(n960), .B1(
DmP_mant_SHT1_SW[6]), .C0(n1072), .C1(DmP_mant_SHT1_SW[7]), .Y(n1324)
);
AOI22X2TS U1519 ( .A0(Data_array_SWR[22]), .A1(n1536), .B0(
Data_array_SWR[18]), .B1(n1537), .Y(n1186) );
AOI221X1TS U1520 ( .A0(n1704), .A1(intDX_EWSW[18]), .B0(intDX_EWSW[19]),
.B1(n1650), .C0(n1151), .Y(n1156) );
AOI32X1TS U1521 ( .A0(n1704), .A1(n1012), .A2(intDX_EWSW[18]), .B0(
intDX_EWSW[19]), .B1(n1650), .Y(n1013) );
NAND2X1TS U1522 ( .A(Raw_mant_NRM_SWR[1]), .B(n1198), .Y(n1362) );
OAI21X2TS U1523 ( .A0(intDX_EWSW[18]), .A1(n1704), .B0(n1012), .Y(n1151) );
OAI211XLTS U1524 ( .A0(n1237), .A1(n951), .B0(n1234), .C0(n1233), .Y(n835)
);
INVX2TS U1525 ( .A(n939), .Y(n961) );
NOR2XLTS U1526 ( .A(n1676), .B(intDX_EWSW[11]), .Y(n972) );
NOR2X1TS U1527 ( .A(n1688), .B(intDX_EWSW[17]), .Y(n1010) );
BUFX3TS U1528 ( .A(n1638), .Y(n962) );
OAI21XLTS U1529 ( .A0(intDX_EWSW[13]), .A1(n1690), .B0(intDX_EWSW[12]), .Y(
n971) );
OA22X1TS U1530 ( .A0(n1648), .A1(intDX_EWSW[22]), .B0(n1702), .B1(
intDX_EWSW[23]), .Y(n1020) );
OA22X1TS U1531 ( .A0(n1697), .A1(intDX_EWSW[14]), .B0(n1647), .B1(
intDX_EWSW[15]), .Y(n983) );
OAI21XLTS U1532 ( .A0(intDX_EWSW[1]), .A1(n1692), .B0(intDX_EWSW[0]), .Y(
n992) );
OAI21XLTS U1533 ( .A0(intDX_EWSW[3]), .A1(n1687), .B0(intDX_EWSW[2]), .Y(
n995) );
NOR3X6TS U1534 ( .A(Raw_mant_NRM_SWR[6]), .B(Raw_mant_NRM_SWR[5]), .C(n1192),
.Y(n1197) );
OR2X4TS U1535 ( .A(n944), .B(n1212), .Y(n1208) );
NOR2XLTS U1536 ( .A(n1484), .B(n946), .Y(n1487) );
OAI21XLTS U1537 ( .A0(n1520), .A1(DMP_SFG[0]), .B0(n1526), .Y(n1521) );
BUFX3TS U1538 ( .A(n1393), .Y(n1403) );
OAI2BB2XLTS U1539 ( .B0(intDY_EWSW[12]), .B1(n971), .A0N(intDX_EWSW[13]),
.A1N(n1690), .Y(n982) );
AOI22X1TS U1540 ( .A0(intDX_EWSW[11]), .A1(n1676), .B0(intDX_EWSW[10]), .B1(
n973), .Y(n978) );
AOI21X1TS U1541 ( .A0(n976), .A1(n975), .B0(n985), .Y(n977) );
OAI22X1TS U1542 ( .A0(n1666), .A1(intDX_EWSW[10]), .B0(n1676), .B1(
intDX_EWSW[11]), .Y(n1159) );
INVX2TS U1543 ( .A(n1159), .Y(n986) );
OAI2BB2XLTS U1544 ( .B0(intDY_EWSW[14]), .B1(n979), .A0N(intDX_EWSW[15]),
.A1N(n1647), .Y(n980) );
AOI211X1TS U1545 ( .A0(n983), .A1(n982), .B0(n981), .C0(n980), .Y(n984) );
OAI2BB1X1TS U1546 ( .A0N(n1662), .A1N(intDY_EWSW[5]), .B0(intDX_EWSW[4]),
.Y(n990) );
OAI22X1TS U1547 ( .A0(intDY_EWSW[4]), .A1(n990), .B0(n1662), .B1(
intDY_EWSW[5]), .Y(n1001) );
OAI2BB1X1TS U1548 ( .A0N(n1663), .A1N(intDY_EWSW[7]), .B0(intDX_EWSW[6]),
.Y(n991) );
OAI22X1TS U1549 ( .A0(intDY_EWSW[6]), .A1(n991), .B0(n1663), .B1(
intDY_EWSW[7]), .Y(n1000) );
AOI22X1TS U1550 ( .A0(intDY_EWSW[7]), .A1(n1663), .B0(intDY_EWSW[6]), .B1(
n1642), .Y(n998) );
AOI211X1TS U1551 ( .A0(intDY_EWSW[16]), .A1(n1669), .B0(n1015), .C0(n1151),
.Y(n1005) );
OAI2BB2XLTS U1552 ( .B0(intDY_EWSW[20]), .B1(n1009), .A0N(intDX_EWSW[21]),
.A1N(n1691), .Y(n1019) );
AOI22X1TS U1553 ( .A0(intDX_EWSW[17]), .A1(n1688), .B0(intDX_EWSW[16]), .B1(
n1011), .Y(n1014) );
OAI32X1TS U1554 ( .A0(n1151), .A1(n1015), .A2(n1014), .B0(n1013), .B1(n1015),
.Y(n1018) );
OAI2BB2XLTS U1555 ( .B0(intDY_EWSW[22]), .B1(n1016), .A0N(intDX_EWSW[23]),
.A1N(n1702), .Y(n1017) );
AOI211X1TS U1556 ( .A0(n1020), .A1(n1019), .B0(n1018), .C0(n1017), .Y(n1021)
);
OAI21X1TS U1557 ( .A0(intDX_EWSW[26]), .A1(n1685), .B0(n1029), .Y(n1032) );
NOR2X1TS U1558 ( .A(n1686), .B(intDX_EWSW[25]), .Y(n1027) );
NOR2X1TS U1559 ( .A(n1643), .B(intDX_EWSW[30]), .Y(n1036) );
NOR2X1TS U1560 ( .A(n1675), .B(intDX_EWSW[29]), .Y(n1034) );
NAND4BBX1TS U1561 ( .AN(n1032), .BN(n1027), .C(n1038), .D(n1023), .Y(n1024)
);
AOI22X1TS U1562 ( .A0(intDX_EWSW[25]), .A1(n1686), .B0(intDX_EWSW[24]), .B1(
n1028), .Y(n1033) );
OAI211X1TS U1563 ( .A0(n1033), .A1(n1032), .B0(n1031), .C0(n1030), .Y(n1039)
);
NOR3X1TS U1564 ( .A(n1703), .B(n1034), .C(intDY_EWSW[28]), .Y(n1035) );
AOI221X1TS U1565 ( .A0(intDX_EWSW[30]), .A1(n1643), .B0(intDX_EWSW[29]),
.B1(n1675), .C0(n1035), .Y(n1037) );
NOR2X4TS U1566 ( .A(n1042), .B(n1443), .Y(n1291) );
CLKBUFX2TS U1567 ( .A(n1253), .Y(n1220) );
BUFX3TS U1568 ( .A(n1220), .Y(n1332) );
AOI22X1TS U1569 ( .A0(intDX_EWSW[13]), .A1(n1333), .B0(DMP_EXP_EWSW[13]),
.B1(n1332), .Y(n1043) );
AOI22X1TS U1570 ( .A0(intDX_EWSW[15]), .A1(n1333), .B0(DMP_EXP_EWSW[15]),
.B1(n1332), .Y(n1044) );
BUFX3TS U1571 ( .A(n1723), .Y(n1575) );
INVX2TS U1572 ( .A(n1575), .Y(n1549) );
INVX2TS U1573 ( .A(n1670), .Y(n1522) );
AOI22X1TS U1574 ( .A0(n1530), .A1(DmP_mant_SFG_SWR[21]), .B0(n1620), .B1(
n1529), .Y(n1478) );
AOI22X1TS U1575 ( .A0(n1530), .A1(DmP_mant_SFG_SWR[20]), .B0(n1617), .B1(
n1529), .Y(n1082) );
AOI22X1TS U1576 ( .A0(n1530), .A1(DmP_mant_SFG_SWR[17]), .B0(n965), .B1(
n1529), .Y(n1474) );
AOI22X1TS U1577 ( .A0(n1530), .A1(DmP_mant_SFG_SWR[15]), .B0(n964), .B1(
n1529), .Y(n1128) );
AOI22X1TS U1578 ( .A0(n1530), .A1(DmP_mant_SFG_SWR[14]), .B0(n963), .B1(
n1670), .Y(n1468) );
INVX4TS U1579 ( .A(n1670), .Y(n1523) );
AOI2BB2X2TS U1580 ( .B0(OP_FLAG_SFG), .B1(DmP_mant_SFG_SWR[12]), .A0N(
DmP_mant_SFG_SWR[12]), .A1N(OP_FLAG_SFG), .Y(n1573) );
BUFX3TS U1581 ( .A(n1575), .Y(n1564) );
INVX2TS U1582 ( .A(n1429), .Y(n1047) );
NOR3X4TS U1583 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[19]), .C(
Raw_mant_NRM_SWR[20]), .Y(n1369) );
NOR2X4TS U1584 ( .A(Raw_mant_NRM_SWR[18]), .B(n1049), .Y(n1359) );
NOR2X1TS U1585 ( .A(Raw_mant_NRM_SWR[3]), .B(Raw_mant_NRM_SWR[2]), .Y(n1053)
);
NAND2X4TS U1586 ( .A(n1197), .B(n1641), .Y(n1370) );
OAI21X1TS U1587 ( .A0(Raw_mant_NRM_SWR[6]), .A1(Raw_mant_NRM_SWR[7]), .B0(
n1051), .Y(n1052) );
OAI21X2TS U1588 ( .A0(n1053), .A1(n1370), .B0(n1052), .Y(n1196) );
NOR2X1TS U1589 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[20]), .Y(
n1055) );
AOI32X1TS U1590 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n1055), .A2(n1054), .B0(
Raw_mant_NRM_SWR[19]), .B1(n1055), .Y(n1056) );
AOI211X1TS U1591 ( .A0(n1057), .A1(n1056), .B0(Raw_mant_NRM_SWR[24]), .C0(
Raw_mant_NRM_SWR[25]), .Y(n1058) );
AOI32X1TS U1592 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n1651), .A2(n1707), .B0(
Raw_mant_NRM_SWR[22]), .B1(n1651), .Y(n1061) );
NOR3X4TS U1593 ( .A(Raw_mant_NRM_SWR[3]), .B(Raw_mant_NRM_SWR[2]), .C(n1370),
.Y(n1198) );
AOI21X1TS U1594 ( .A0(n1197), .A1(n1065), .B0(n1064), .Y(n1067) );
NAND2X1TS U1595 ( .A(Raw_mant_NRM_SWR[12]), .B(n1066), .Y(n1363) );
AOI31X1TS U1596 ( .A0(n1068), .A1(Raw_mant_NRM_SWR[8]), .A2(n1668), .B0(
n1374), .Y(n1069) );
OAI211X4TS U1597 ( .A0(n1667), .A1(n1192), .B0(n1070), .C0(n1069), .Y(n1212)
);
NAND2X2TS U1598 ( .A(n1071), .B(n1409), .Y(n1287) );
AOI22X1TS U1599 ( .A0(n952), .A1(Data_array_SWR[0]), .B0(
Raw_mant_NRM_SWR[24]), .B1(n941), .Y(n1076) );
INVX8TS U1600 ( .A(n1208), .Y(n1422) );
NOR2X4TS U1601 ( .A(n952), .B(n1210), .Y(n1315) );
BUFX3TS U1602 ( .A(n1240), .Y(n1418) );
AOI22X1TS U1603 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n1409), .B0(n1418), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1074) );
AOI22X1TS U1604 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n1422), .B0(n959), .B1(
DmP_mant_SHT1_SW[0]), .Y(n1073) );
AOI22X1TS U1605 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n1422), .B0(n1315), .B1(
n1311), .Y(n1075) );
NOR2X2TS U1606 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1682), .Y(n1385) );
INVX2TS U1607 ( .A(n1723), .Y(n1584) );
INVX1TS U1608 ( .A(DmP_mant_SFG_SWR[24]), .Y(n1625) );
AOI22X1TS U1609 ( .A0(n1530), .A1(DmP_mant_SFG_SWR[24]), .B0(n1625), .B1(
n1529), .Y(n1203) );
AOI2BB2X1TS U1610 ( .B0(OP_FLAG_SFG), .B1(DmP_mant_SFG_SWR[23]), .A0N(
DmP_mant_SFG_SWR[23]), .A1N(OP_FLAG_SFG), .Y(n1481) );
BUFX3TS U1611 ( .A(Shift_reg_FLAGS_7[0]), .Y(n1726) );
XNOR2X2TS U1612 ( .A(DMP_exp_NRM2_EW[6]), .B(n1090), .Y(n1379) );
INVX2TS U1613 ( .A(exp_rslt_NRM2_EW1[3]), .Y(n1086) );
INVX2TS U1614 ( .A(exp_rslt_NRM2_EW1[2]), .Y(n1085) );
XNOR2X2TS U1615 ( .A(DMP_exp_NRM2_EW[5]), .B(DP_OP_15J23_123_2314_n4), .Y(
n1378) );
INVX2TS U1616 ( .A(n1090), .Y(n1091) );
XNOR2X2TS U1617 ( .A(DMP_exp_NRM2_EW[7]), .B(n1096), .Y(n1183) );
AND4X1TS U1618 ( .A(exp_rslt_NRM2_EW1[3]), .B(n1377), .C(
exp_rslt_NRM2_EW1[2]), .D(exp_rslt_NRM2_EW1[1]), .Y(n1093) );
INVX2TS U1619 ( .A(n1096), .Y(n1097) );
NOR2X4TS U1620 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n1537) );
INVX2TS U1621 ( .A(n1537), .Y(n1100) );
NOR2X4TS U1622 ( .A(n1100), .B(shift_value_SHT2_EWR[4]), .Y(n1510) );
NAND2X1TS U1623 ( .A(n954), .B(n1510), .Y(n1099) );
BUFX3TS U1624 ( .A(n1099), .Y(n1592) );
NOR2X2TS U1625 ( .A(shift_value_SHT2_EWR[4]), .B(n954), .Y(n1606) );
INVX2TS U1626 ( .A(n1606), .Y(n1111) );
NOR2X4TS U1627 ( .A(n1661), .B(shift_value_SHT2_EWR[3]), .Y(n1536) );
NOR2X2TS U1628 ( .A(n1671), .B(shift_value_SHT2_EWR[2]), .Y(n1494) );
NOR2X2TS U1629 ( .A(n1640), .B(n1100), .Y(n1500) );
NAND2X2TS U1630 ( .A(n1640), .B(n1536), .Y(n1577) );
NAND3X2TS U1631 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.C(n1640), .Y(n1578) );
INVX2TS U1632 ( .A(n1102), .Y(n1551) );
AOI22X1TS U1633 ( .A0(Data_array_SWR[20]), .A1(n1101), .B0(
Data_array_SWR[16]), .B1(n1551), .Y(n1103) );
OAI2BB1X1TS U1634 ( .A0N(Data_array_SWR[13]), .A1N(n1550), .B0(n1103), .Y(
n1104) );
AOI21X1TS U1635 ( .A0(Data_array_SWR[24]), .A1(n1500), .B0(n1104), .Y(n1140)
);
OAI222X1TS U1636 ( .A0(n1592), .A1(n1719), .B0(n1111), .B1(n1513), .C0(n1595), .C1(n1140), .Y(n1139) );
INVX2TS U1637 ( .A(n1635), .Y(n1181) );
INVX2TS U1638 ( .A(n1105), .Y(n1629) );
INVX2TS U1639 ( .A(n1099), .Y(n1608) );
AOI22X1TS U1640 ( .A0(Data_array_SWR[12]), .A1(n1629), .B0(
Data_array_SWR[13]), .B1(n1608), .Y(n1106) );
OAI221X1TS U1641 ( .A0(n954), .A1(n1484), .B0(n947), .B1(n1485), .C0(n1106),
.Y(n1179) );
AOI22X1TS U1642 ( .A0(Data_array_SWR[18]), .A1(n1101), .B0(
Data_array_SWR[11]), .B1(n1550), .Y(n1107) );
AOI21X1TS U1643 ( .A0(Data_array_SWR[22]), .A1(n1500), .B0(n1108), .Y(n1190)
);
OAI222X1TS U1644 ( .A0(n1592), .A1(n1717), .B0(n1111), .B1(n1188), .C0(n947),
.C1(n1190), .Y(n1142) );
AOI22X1TS U1645 ( .A0(Data_array_SWR[10]), .A1(n1550), .B0(
Data_array_SWR[17]), .B1(n1101), .Y(n1109) );
AOI21X1TS U1646 ( .A0(Data_array_SWR[21]), .A1(n1500), .B0(n1110), .Y(n1187)
);
OAI222X1TS U1647 ( .A0(n1592), .A1(n1716), .B0(n1111), .B1(n1186), .C0(n1595), .C1(n1187), .Y(n1141) );
INVX2TS U1648 ( .A(n1181), .Y(n1610) );
OAI22X1TS U1649 ( .A0(n955), .A1(n1578), .B0(n1715), .B1(n1102), .Y(n1119)
);
OAI22X1TS U1650 ( .A0(n1186), .A1(n1640), .B0(n1717), .B1(n1577), .Y(n1118)
);
AOI211X1TS U1651 ( .A0(Data_array_SWR[3]), .A1(n1510), .B0(n1119), .C0(n1118), .Y(n1138) );
OAI22X1TS U1652 ( .A0(n1138), .A1(n947), .B0(n1636), .B1(n1105), .Y(n1622)
);
OAI22X1TS U1653 ( .A0(n1654), .A1(n1578), .B0(n1714), .B1(n1102), .Y(n1121)
);
OAI22X1TS U1654 ( .A0(n1188), .A1(n1640), .B0(n1716), .B1(n1577), .Y(n1120)
);
AOI211X1TS U1655 ( .A0(Data_array_SWR[2]), .A1(n1510), .B0(n1121), .C0(n1120), .Y(n1191) );
OAI22X1TS U1656 ( .A0(n1191), .A1(n1595), .B0(n1637), .B1(n1105), .Y(n1137)
);
BUFX3TS U1657 ( .A(n1740), .Y(n1747) );
BUFX3TS U1658 ( .A(n1126), .Y(n1748) );
BUFX3TS U1659 ( .A(n1738), .Y(n1749) );
BUFX3TS U1660 ( .A(n1126), .Y(n1750) );
BUFX3TS U1661 ( .A(n1738), .Y(n1751) );
BUFX3TS U1662 ( .A(n1739), .Y(n1752) );
BUFX3TS U1663 ( .A(n1742), .Y(n1753) );
BUFX3TS U1664 ( .A(n1743), .Y(n1754) );
BUFX3TS U1665 ( .A(n1740), .Y(n1755) );
CLKBUFX2TS U1666 ( .A(n1124), .Y(n1125) );
BUFX3TS U1667 ( .A(n1738), .Y(n1758) );
BUFX3TS U1668 ( .A(n1124), .Y(n1738) );
BUFX3TS U1669 ( .A(n1124), .Y(n1739) );
BUFX3TS U1670 ( .A(n1742), .Y(n1741) );
BUFX3TS U1671 ( .A(n1739), .Y(n1744) );
BUFX3TS U1672 ( .A(n1742), .Y(n1745) );
BUFX3TS U1673 ( .A(n1743), .Y(n1746) );
BUFX3TS U1674 ( .A(n1122), .Y(n1729) );
BUFX3TS U1675 ( .A(n1739), .Y(n1757) );
BUFX3TS U1676 ( .A(n1124), .Y(n1742) );
BUFX3TS U1677 ( .A(n1740), .Y(n1728) );
BUFX3TS U1678 ( .A(n1743), .Y(n1763) );
BUFX3TS U1679 ( .A(n1126), .Y(n1734) );
BUFX3TS U1680 ( .A(n1742), .Y(n1759) );
BUFX3TS U1681 ( .A(n1126), .Y(n1732) );
BUFX3TS U1682 ( .A(n1743), .Y(n1760) );
BUFX3TS U1683 ( .A(n1738), .Y(n1727) );
BUFX3TS U1684 ( .A(n1740), .Y(n1737) );
BUFX3TS U1685 ( .A(n1740), .Y(n1735) );
BUFX3TS U1686 ( .A(n1126), .Y(n1736) );
BUFX3TS U1687 ( .A(n1123), .Y(n1765) );
BUFX3TS U1688 ( .A(n1739), .Y(n1731) );
BUFX3TS U1689 ( .A(n1742), .Y(n1733) );
BUFX3TS U1690 ( .A(n1123), .Y(n1756) );
BUFX3TS U1691 ( .A(n1124), .Y(n1740) );
BUFX3TS U1692 ( .A(n1124), .Y(n1743) );
BUFX3TS U1693 ( .A(n1122), .Y(n1761) );
BUFX3TS U1694 ( .A(n1122), .Y(n1762) );
BUFX3TS U1695 ( .A(n1743), .Y(n1730) );
BUFX3TS U1696 ( .A(n1125), .Y(n1766) );
BUFX3TS U1697 ( .A(n1738), .Y(n1764) );
BUFX3TS U1698 ( .A(n1739), .Y(n1767) );
OAI21XLTS U1699 ( .A0(busy), .A1(n1595), .B0(n944), .Y(n880) );
CLKBUFX2TS U1700 ( .A(n1725), .Y(n1463) );
INVX2TS U1701 ( .A(n1463), .Y(n1445) );
NAND2X1TS U1702 ( .A(DmP_EXP_EWSW[25]), .B(n967), .Y(n1437) );
NOR2X1TS U1703 ( .A(n1652), .B(DMP_EXP_EWSW[24]), .Y(n1433) );
OAI22X1TS U1704 ( .A0(n1435), .A1(n1433), .B0(DmP_EXP_EWSW[24]), .B1(n1653),
.Y(n1439) );
AOI22X1TS U1705 ( .A0(DMP_EXP_EWSW[25]), .A1(n1721), .B0(n1437), .B1(n1439),
.Y(n1132) );
NOR2X1TS U1706 ( .A(n932), .B(DMP_EXP_EWSW[26]), .Y(n1133) );
AOI21X1TS U1707 ( .A0(DMP_EXP_EWSW[26]), .A1(n932), .B0(n1133), .Y(n1130) );
XNOR2X1TS U1708 ( .A(n1132), .B(n1130), .Y(n1131) );
OAI22X1TS U1709 ( .A0(n1133), .A1(n1132), .B0(DmP_EXP_EWSW[26]), .B1(n1720),
.Y(n1135) );
XNOR2X1TS U1710 ( .A(DmP_EXP_EWSW[27]), .B(DMP_EXP_EWSW[27]), .Y(n1134) );
XOR2X1TS U1711 ( .A(n1135), .B(n1134), .Y(n1136) );
BUFX3TS U1712 ( .A(n1538), .Y(n1624) );
BUFX3TS U1713 ( .A(n1180), .Y(n1444) );
INVX2TS U1714 ( .A(n1444), .Y(n1465) );
OAI22X1TS U1715 ( .A0(n954), .A1(n1138), .B0(n1636), .B1(n1592), .Y(n1603)
);
NOR2X2TS U1716 ( .A(shift_value_SHT2_EWR[4]), .B(n946), .Y(n1555) );
INVX2TS U1717 ( .A(n1555), .Y(n1189) );
OAI222X1TS U1718 ( .A0(n1105), .A1(n1719), .B0(n945), .B1(n1140), .C0(n1189),
.C1(n1513), .Y(n1185) );
OAI22X1TS U1719 ( .A0(n1686), .A1(intDX_EWSW[25]), .B0(n1685), .B1(
intDX_EWSW[26]), .Y(n1143) );
AOI221X1TS U1720 ( .A0(n1686), .A1(intDX_EWSW[25]), .B0(intDX_EWSW[26]),
.B1(n1685), .C0(n1143), .Y(n1149) );
OAI22X1TS U1721 ( .A0(n1700), .A1(intDX_EWSW[27]), .B0(n1703), .B1(
intDY_EWSW[28]), .Y(n1144) );
OAI22X1TS U1722 ( .A0(n1701), .A1(intDY_EWSW[29]), .B0(n1649), .B1(
intDY_EWSW[30]), .Y(n1145) );
AOI221X1TS U1723 ( .A0(n1701), .A1(intDY_EWSW[29]), .B0(intDY_EWSW[30]),
.B1(n1649), .C0(n1145), .Y(n1147) );
INVX2TS U1724 ( .A(intDY_EWSW[1]), .Y(n1265) );
OAI22X1TS U1725 ( .A0(n1265), .A1(intDX_EWSW[1]), .B0(n1688), .B1(
intDX_EWSW[17]), .Y(n1150) );
OAI22X1TS U1726 ( .A0(n1699), .A1(intDX_EWSW[20]), .B0(n1691), .B1(
intDX_EWSW[21]), .Y(n1152) );
OAI22X1TS U1727 ( .A0(n1648), .A1(intDX_EWSW[22]), .B0(n1702), .B1(
intDX_EWSW[23]), .Y(n1153) );
OAI22X1TS U1728 ( .A0(n1634), .A1(intDX_EWSW[24]), .B0(n1689), .B1(
intDX_EWSW[9]), .Y(n1158) );
AOI221X1TS U1729 ( .A0(n1634), .A1(intDX_EWSW[24]), .B0(intDX_EWSW[9]), .B1(
n1689), .C0(n1158), .Y(n1165) );
OAI22X1TS U1730 ( .A0(n1696), .A1(intDX_EWSW[12]), .B0(n1690), .B1(
intDX_EWSW[13]), .Y(n1160) );
OAI22X1TS U1731 ( .A0(n1697), .A1(intDX_EWSW[14]), .B0(n1647), .B1(
intDX_EWSW[15]), .Y(n1161) );
OAI22X1TS U1732 ( .A0(n1698), .A1(intDX_EWSW[16]), .B0(n1646), .B1(
intDX_EWSW[0]), .Y(n1166) );
AOI221X1TS U1733 ( .A0(n1698), .A1(intDX_EWSW[16]), .B0(intDX_EWSW[0]), .B1(
n1646), .C0(n1166), .Y(n1173) );
OAI22X1TS U1734 ( .A0(n1694), .A1(intDX_EWSW[2]), .B0(n1687), .B1(
intDX_EWSW[3]), .Y(n1167) );
AOI221X1TS U1735 ( .A0(n1694), .A1(intDX_EWSW[2]), .B0(intDX_EWSW[3]), .B1(
n1687), .C0(n1167), .Y(n1172) );
OAI22X1TS U1736 ( .A0(n1695), .A1(intDX_EWSW[4]), .B0(n1645), .B1(
intDX_EWSW[5]), .Y(n1168) );
AOI221X1TS U1737 ( .A0(n1695), .A1(intDX_EWSW[4]), .B0(intDX_EWSW[5]), .B1(
n1645), .C0(n1168), .Y(n1171) );
OAI22X1TS U1738 ( .A0(n1693), .A1(intDX_EWSW[8]), .B0(n1680), .B1(
intDX_EWSW[6]), .Y(n1169) );
AOI221X1TS U1739 ( .A0(n1693), .A1(intDX_EWSW[8]), .B0(intDX_EWSW[6]), .B1(
n1680), .C0(n1169), .Y(n1170) );
NOR4X1TS U1740 ( .A(n1177), .B(n1176), .C(n1175), .D(n1174), .Y(n1355) );
CLKXOR2X2TS U1741 ( .A(intDY_EWSW[31]), .B(intAS), .Y(n1349) );
AOI21X1TS U1742 ( .A0(n1349), .A1(intDX_EWSW[31]), .B0(n1178), .Y(n1442) );
NAND2X2TS U1743 ( .A(n1182), .B(n1181), .Y(n1380) );
OA22X1TS U1744 ( .A0(n1380), .A1(exp_rslt_NRM2_EW1[3]), .B0(n1181), .B1(
final_result_ieee[26]), .Y(n809) );
OA22X1TS U1745 ( .A0(n1380), .A1(exp_rslt_NRM2_EW1[2]), .B0(n1181), .B1(
final_result_ieee[25]), .Y(n810) );
OA22X1TS U1746 ( .A0(n1380), .A1(exp_rslt_NRM2_EW1[1]), .B0(n1726), .B1(
final_result_ieee[24]), .Y(n811) );
OA22X1TS U1747 ( .A0(n1380), .A1(exp_rslt_NRM2_EW1[4]), .B0(n1726), .B1(
final_result_ieee[27]), .Y(n808) );
OAI222X1TS U1748 ( .A0(n1105), .A1(n1716), .B0(left_right_SHT2), .B1(n1187),
.C0(n1189), .C1(n1186), .Y(n1560) );
OAI222X1TS U1749 ( .A0(n1105), .A1(n1717), .B0(left_right_SHT2), .B1(n1190),
.C0(n1189), .C1(n1188), .Y(n1545) );
OAI22X1TS U1750 ( .A0(left_right_SHT2), .A1(n1191), .B0(n1637), .B1(n1592),
.Y(n1519) );
NAND2BX1TS U1751 ( .AN(n1192), .B(Raw_mant_NRM_SWR[5]), .Y(n1371) );
OAI21XLTS U1752 ( .A0(n1194), .A1(n1193), .B0(n1371), .Y(n1195) );
AOI211X1TS U1753 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1197), .B0(n1196), .C0(
n1195), .Y(n1200) );
AOI31X1TS U1754 ( .A0(n1200), .A1(n1199), .A2(n1362), .B0(n943), .Y(n1357)
);
INVX1TS U1755 ( .A(DmP_mant_SFG_SWR[25]), .Y(n1631) );
AOI22X1TS U1756 ( .A0(n1523), .A1(DmP_mant_SFG_SWR[25]), .B0(n1631), .B1(
n1529), .Y(n1205) );
AOI22X1TS U1757 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n1409), .B0(n1418), .B1(
DmP_mant_SHT1_SW[15]), .Y(n1207) );
AOI21X1TS U1758 ( .A0(n959), .A1(DmP_mant_SHT1_SW[14]), .B0(n1209), .Y(n1417) );
INVX8TS U1759 ( .A(n1208), .Y(n1323) );
OAI22X1TS U1760 ( .A0(n1288), .A1(n948), .B0(n1667), .B1(n1225), .Y(n1213)
);
AOI21X1TS U1761 ( .A0(n952), .A1(Data_array_SWR[15]), .B0(n1213), .Y(n1214)
);
INVX2TS U1762 ( .A(n1293), .Y(n1217) );
AOI22X1TS U1763 ( .A0(intDX_EWSW[2]), .A1(n928), .B0(DMP_EXP_EWSW[2]), .B1(
n1443), .Y(n1215) );
AOI22X1TS U1764 ( .A0(intDX_EWSW[1]), .A1(n928), .B0(DMP_EXP_EWSW[1]), .B1(
n1443), .Y(n1216) );
BUFX3TS U1765 ( .A(n1220), .Y(n1386) );
AOI22X1TS U1766 ( .A0(intDX_EWSW[21]), .A1(n1259), .B0(DmP_EXP_EWSW[21]),
.B1(n1386), .Y(n1218) );
AOI22X1TS U1767 ( .A0(intDX_EWSW[20]), .A1(n1259), .B0(DmP_EXP_EWSW[20]),
.B1(n1386), .Y(n1219) );
BUFX3TS U1768 ( .A(n1220), .Y(n1345) );
AOI22X1TS U1769 ( .A0(intDY_EWSW[28]), .A1(n1259), .B0(DMP_EXP_EWSW[28]),
.B1(n1345), .Y(n1221) );
AOI22X1TS U1770 ( .A0(intDX_EWSW[22]), .A1(n1259), .B0(DmP_EXP_EWSW[22]),
.B1(n1386), .Y(n1222) );
AOI22X1TS U1771 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1409), .B0(n1418), .B1(
DmP_mant_SHT1_SW[5]), .Y(n1224) );
AOI22X1TS U1772 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n1422), .B0(n958), .B1(
DmP_mant_SHT1_SW[4]), .Y(n1223) );
NAND2X1TS U1773 ( .A(n1224), .B(n1223), .Y(n1314) );
AOI22X1TS U1774 ( .A0(n1047), .A1(Data_array_SWR[6]), .B0(n927), .B1(n1314),
.Y(n1227) );
NAND2X1TS U1775 ( .A(Raw_mant_NRM_SWR[16]), .B(n934), .Y(n1226) );
AOI22X1TS U1776 ( .A0(intDX_EWSW[3]), .A1(n928), .B0(DMP_EXP_EWSW[3]), .B1(
n1443), .Y(n1228) );
AOI22X1TS U1777 ( .A0(intDX_EWSW[0]), .A1(n928), .B0(DMP_EXP_EWSW[0]), .B1(
n1443), .Y(n1229) );
AOI22X1TS U1778 ( .A0(intDX_EWSW[5]), .A1(n1255), .B0(DMP_EXP_EWSW[5]), .B1(
n1332), .Y(n1230) );
AOI22X1TS U1779 ( .A0(intDX_EWSW[4]), .A1(n1255), .B0(DMP_EXP_EWSW[4]), .B1(
n1332), .Y(n1231) );
AOI22X1TS U1780 ( .A0(intDX_EWSW[6]), .A1(n928), .B0(DMP_EXP_EWSW[6]), .B1(
n1332), .Y(n1232) );
AOI22X1TS U1781 ( .A0(n952), .A1(Data_array_SWR[13]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n933), .Y(n1234) );
AOI2BB2X1TS U1782 ( .B0(Raw_mant_NRM_SWR[11]), .B1(n940), .A0N(n1246), .A1N(
n948), .Y(n1233) );
INVX4TS U1783 ( .A(n1208), .Y(n1407) );
AOI22X1TS U1784 ( .A0(n1047), .A1(Data_array_SWR[20]), .B0(
Raw_mant_NRM_SWR[1]), .B1(n934), .Y(n1236) );
AOI2BB2X1TS U1785 ( .B0(Raw_mant_NRM_SWR[3]), .B1(n941), .A0N(n1268), .A1N(
n948), .Y(n1235) );
AOI22X1TS U1786 ( .A0(n1047), .A1(Data_array_SWR[11]), .B0(
Raw_mant_NRM_SWR[11]), .B1(n933), .Y(n1239) );
AOI2BB2X1TS U1787 ( .B0(Raw_mant_NRM_SWR[13]), .B1(n940), .A0N(n1237), .A1N(
n948), .Y(n1238) );
AOI22X1TS U1788 ( .A0(n1428), .A1(Data_array_SWR[16]), .B0(
Raw_mant_NRM_SWR[5]), .B1(n934), .Y(n1242) );
AOI2BB2X1TS U1789 ( .B0(Raw_mant_NRM_SWR[7]), .B1(n940), .A0N(n1284), .A1N(
n948), .Y(n1241) );
AOI22X1TS U1790 ( .A0(n1047), .A1(Data_array_SWR[14]), .B0(
Raw_mant_NRM_SWR[7]), .B1(n934), .Y(n1245) );
AOI2BB2X1TS U1791 ( .B0(Raw_mant_NRM_SWR[9]), .B1(n941), .A0N(n1243), .A1N(
n948), .Y(n1244) );
OAI211X1TS U1792 ( .A0(n1246), .A1(n950), .B0(n1245), .C0(n1244), .Y(n837)
);
AOI22X1TS U1793 ( .A0(Raw_mant_NRM_SWR[24]), .A1(n1422), .B0(n1418), .B1(
DmP_mant_SHT1_SW[0]), .Y(n1251) );
AOI22X1TS U1794 ( .A0(n952), .A1(Data_array_SWR[1]), .B0(
Raw_mant_NRM_SWR[23]), .B1(n940), .Y(n1250) );
AOI22X1TS U1795 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n1409), .B0(n1418), .B1(
DmP_mant_SHT1_SW[2]), .Y(n1248) );
AOI22X1TS U1796 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n1422), .B0(n959), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1247) );
NAND2X1TS U1797 ( .A(n1248), .B(n1247), .Y(n1307) );
NAND2X1TS U1798 ( .A(n1315), .B(n1307), .Y(n1249) );
AOI22X1TS U1799 ( .A0(intDX_EWSW[17]), .A1(n1259), .B0(DmP_EXP_EWSW[17]),
.B1(n1386), .Y(n1252) );
AOI22X1TS U1800 ( .A0(intDX_EWSW[18]), .A1(n1259), .B0(DmP_EXP_EWSW[18]),
.B1(n1253), .Y(n1254) );
BUFX3TS U1801 ( .A(n1443), .Y(n1351) );
AOI22X1TS U1802 ( .A0(intDX_EWSW[3]), .A1(n1338), .B0(DmP_EXP_EWSW[3]), .B1(
n1351), .Y(n1256) );
AOI22X1TS U1803 ( .A0(intDX_EWSW[6]), .A1(n1259), .B0(DmP_EXP_EWSW[6]), .B1(
n1351), .Y(n1257) );
AOI22X1TS U1804 ( .A0(intDX_EWSW[2]), .A1(n1259), .B0(DmP_EXP_EWSW[2]), .B1(
n1351), .Y(n1258) );
AOI22X1TS U1805 ( .A0(intDX_EWSW[19]), .A1(n1259), .B0(DmP_EXP_EWSW[19]),
.B1(n1386), .Y(n1260) );
AOI22X1TS U1806 ( .A0(DmP_EXP_EWSW[27]), .A1(n1386), .B0(intDX_EWSW[27]),
.B1(n1338), .Y(n1261) );
AOI22X1TS U1807 ( .A0(intDX_EWSW[4]), .A1(n1338), .B0(DmP_EXP_EWSW[4]), .B1(
n1351), .Y(n1262) );
AOI22X1TS U1808 ( .A0(intDX_EWSW[5]), .A1(n1338), .B0(DmP_EXP_EWSW[5]), .B1(
n1253), .Y(n1263) );
AOI22X1TS U1809 ( .A0(intDX_EWSW[1]), .A1(n1338), .B0(DmP_EXP_EWSW[1]), .B1(
n1351), .Y(n1264) );
AOI22X1TS U1810 ( .A0(intDX_EWSW[7]), .A1(n1293), .B0(DmP_EXP_EWSW[7]), .B1(
n1253), .Y(n1266) );
AOI22X1TS U1811 ( .A0(intDX_EWSW[16]), .A1(n1293), .B0(DmP_EXP_EWSW[16]),
.B1(n1253), .Y(n1267) );
AOI21X1TS U1812 ( .A0(n1422), .A1(Raw_mant_NRM_SWR[0]), .B0(n960), .Y(n1406)
);
OAI22X1TS U1813 ( .A0(n1268), .A1(n949), .B0(n956), .B1(n1637), .Y(n1269) );
AOI21X1TS U1814 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n941), .B0(n1269), .Y(n1270)
);
AOI22X1TS U1815 ( .A0(intDX_EWSW[10]), .A1(n1293), .B0(DmP_EXP_EWSW[10]),
.B1(n1351), .Y(n1271) );
AOI22X1TS U1816 ( .A0(intDX_EWSW[14]), .A1(n1338), .B0(DmP_EXP_EWSW[14]),
.B1(n1220), .Y(n1272) );
AOI22X1TS U1817 ( .A0(intDX_EWSW[11]), .A1(n1291), .B0(DmP_EXP_EWSW[11]),
.B1(n1220), .Y(n1273) );
AOI22X1TS U1818 ( .A0(intDX_EWSW[8]), .A1(n1291), .B0(DmP_EXP_EWSW[8]), .B1(
n969), .Y(n1274) );
AOI22X1TS U1819 ( .A0(intDX_EWSW[12]), .A1(n1291), .B0(DmP_EXP_EWSW[12]),
.B1(n1220), .Y(n1275) );
AOI22X1TS U1820 ( .A0(intDX_EWSW[9]), .A1(n1293), .B0(DmP_EXP_EWSW[9]), .B1(
n1253), .Y(n1276) );
AOI22X1TS U1821 ( .A0(intDX_EWSW[13]), .A1(n1291), .B0(DmP_EXP_EWSW[13]),
.B1(n969), .Y(n1278) );
AOI22X1TS U1822 ( .A0(intDX_EWSW[15]), .A1(n1293), .B0(DmP_EXP_EWSW[15]),
.B1(n1386), .Y(n1279) );
AOI22X1TS U1823 ( .A0(n1428), .A1(Data_array_SWR[18]), .B0(
Raw_mant_NRM_SWR[3]), .B1(n933), .Y(n1283) );
AOI22X1TS U1824 ( .A0(n960), .A1(DmP_mant_SHT1_SW[18]), .B0(n1072), .B1(
DmP_mant_SHT1_SW[19]), .Y(n1285) );
AOI21X1TS U1825 ( .A0(Raw_mant_NRM_SWR[5]), .A1(n1422), .B0(n1286), .Y(n1413) );
OAI22X1TS U1826 ( .A0(n1288), .A1(n949), .B0(n1667), .B1(n1287), .Y(n1289)
);
AOI21X1TS U1827 ( .A0(n952), .A1(Data_array_SWR[17]), .B0(n1289), .Y(n1290)
);
INVX2TS U1828 ( .A(n928), .Y(n1350) );
AOI22X1TS U1829 ( .A0(intDY_EWSW[30]), .A1(n1291), .B0(DMP_EXP_EWSW[30]),
.B1(n1351), .Y(n1292) );
AOI22X1TS U1830 ( .A0(intDY_EWSW[29]), .A1(n1293), .B0(DMP_EXP_EWSW[29]),
.B1(n1351), .Y(n1294) );
AOI22X1TS U1831 ( .A0(intDX_EWSW[0]), .A1(n1338), .B0(DmP_EXP_EWSW[0]), .B1(
n1351), .Y(n1295) );
AOI22X1TS U1832 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n1409), .B0(n1418), .B1(
DmP_mant_SHT1_SW[6]), .Y(n1297) );
AOI22X1TS U1833 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1422), .B0(n959), .B1(
DmP_mant_SHT1_SW[5]), .Y(n1296) );
NAND2X1TS U1834 ( .A(n1297), .B(n1296), .Y(n1304) );
AOI22X1TS U1835 ( .A0(n1428), .A1(Data_array_SWR[7]), .B0(n927), .B1(n1304),
.Y(n1299) );
NAND2X1TS U1836 ( .A(Raw_mant_NRM_SWR[15]), .B(n934), .Y(n1298) );
AOI22X1TS U1837 ( .A0(n1428), .A1(Data_array_SWR[9]), .B0(
Raw_mant_NRM_SWR[13]), .B1(n934), .Y(n1302) );
AOI2BB2X1TS U1838 ( .B0(Raw_mant_NRM_SWR[15]), .B1(n941), .A0N(n1300), .A1N(
n948), .Y(n1301) );
AOI22X1TS U1839 ( .A0(n1047), .A1(Data_array_SWR[5]), .B0(n1315), .B1(n1304),
.Y(n1306) );
NAND2X1TS U1840 ( .A(Raw_mant_NRM_SWR[19]), .B(n941), .Y(n1305) );
AOI22X1TS U1841 ( .A0(n1428), .A1(Data_array_SWR[3]), .B0(n927), .B1(n1307),
.Y(n1309) );
NAND2X1TS U1842 ( .A(Raw_mant_NRM_SWR[19]), .B(n933), .Y(n1308) );
AOI22X1TS U1843 ( .A0(n952), .A1(Data_array_SWR[2]), .B0(n927), .B1(n1311),
.Y(n1313) );
NAND2X1TS U1844 ( .A(Raw_mant_NRM_SWR[20]), .B(n933), .Y(n1312) );
AOI22X1TS U1845 ( .A0(n1428), .A1(Data_array_SWR[4]), .B0(n1315), .B1(n1314),
.Y(n1317) );
NAND2X1TS U1846 ( .A(Raw_mant_NRM_SWR[20]), .B(n941), .Y(n1316) );
AOI22X1TS U1847 ( .A0(intDX_EWSW[7]), .A1(n1333), .B0(DMP_EXP_EWSW[7]), .B1(
n1332), .Y(n1319) );
AOI22X1TS U1848 ( .A0(intDX_EWSW[16]), .A1(n1333), .B0(DMP_EXP_EWSW[16]),
.B1(n1345), .Y(n1320) );
AOI22X1TS U1849 ( .A0(n958), .A1(DmP_mant_SHT1_SW[8]), .B0(n1418), .B1(
DmP_mant_SHT1_SW[9]), .Y(n1321) );
AOI21X1TS U1850 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n1323), .B0(n1322), .Y(
n1424) );
OAI2BB2X1TS U1851 ( .B0(n1324), .B1(n949), .A0N(Raw_mant_NRM_SWR[16]), .A1N(
n940), .Y(n1325) );
AOI21X1TS U1852 ( .A0(n1428), .A1(Data_array_SWR[8]), .B0(n1325), .Y(n1326)
);
OAI21X1TS U1853 ( .A0(n1424), .A1(n1211), .B0(n1326), .Y(n830) );
AOI22X1TS U1854 ( .A0(intDX_EWSW[10]), .A1(n1333), .B0(DMP_EXP_EWSW[10]),
.B1(n1332), .Y(n1327) );
AOI22X1TS U1855 ( .A0(intDX_EWSW[9]), .A1(n1333), .B0(DMP_EXP_EWSW[9]), .B1(
n1332), .Y(n1328) );
AOI22X1TS U1856 ( .A0(intDX_EWSW[14]), .A1(n1333), .B0(DMP_EXP_EWSW[14]),
.B1(n1345), .Y(n1329) );
AOI22X1TS U1857 ( .A0(intDX_EWSW[11]), .A1(n1333), .B0(DMP_EXP_EWSW[11]),
.B1(n1345), .Y(n1330) );
AOI22X1TS U1858 ( .A0(intDX_EWSW[8]), .A1(n1333), .B0(DMP_EXP_EWSW[8]), .B1(
n1332), .Y(n1331) );
AOI22X1TS U1859 ( .A0(intDX_EWSW[12]), .A1(n1333), .B0(DMP_EXP_EWSW[12]),
.B1(n1332), .Y(n1334) );
AOI22X1TS U1860 ( .A0(intDX_EWSW[19]), .A1(n1346), .B0(DMP_EXP_EWSW[19]),
.B1(n1345), .Y(n1336) );
AOI22X1TS U1861 ( .A0(intDX_EWSW[18]), .A1(n1346), .B0(DMP_EXP_EWSW[18]),
.B1(n1345), .Y(n1337) );
AOI222X1TS U1862 ( .A0(n1338), .A1(intDX_EWSW[23]), .B0(DmP_EXP_EWSW[23]),
.B1(n1443), .C0(intDY_EWSW[23]), .C1(n1346), .Y(n1339) );
INVX2TS U1863 ( .A(n1339), .Y(n615) );
AOI22X1TS U1864 ( .A0(intDX_EWSW[22]), .A1(n1346), .B0(DMP_EXP_EWSW[22]),
.B1(n1345), .Y(n1340) );
AOI22X1TS U1865 ( .A0(intDX_EWSW[17]), .A1(n1346), .B0(DMP_EXP_EWSW[17]),
.B1(n1345), .Y(n1341) );
AOI22X1TS U1866 ( .A0(intDX_EWSW[20]), .A1(n1346), .B0(DMP_EXP_EWSW[20]),
.B1(n1345), .Y(n1342) );
AOI22X1TS U1867 ( .A0(DMP_EXP_EWSW[27]), .A1(n1386), .B0(intDX_EWSW[27]),
.B1(n1346), .Y(n1343) );
AOI22X1TS U1868 ( .A0(DMP_EXP_EWSW[23]), .A1(n1386), .B0(intDX_EWSW[23]),
.B1(n1346), .Y(n1344) );
AOI22X1TS U1869 ( .A0(intDX_EWSW[21]), .A1(n1346), .B0(DMP_EXP_EWSW[21]),
.B1(n1345), .Y(n1347) );
INVX2TS U1870 ( .A(n1349), .Y(n1354) );
AOI22X1TS U1871 ( .A0(intDX_EWSW[31]), .A1(n1352), .B0(SIGN_FLAG_EXP), .B1(
n1351), .Y(n1353) );
OAI2BB2XLTS U1872 ( .B0(n1356), .B1(n1381), .A0N(n1612), .A1N(
final_result_ieee[31]), .Y(n594) );
OAI211X1TS U1873 ( .A0(Raw_mant_NRM_SWR[11]), .A1(Raw_mant_NRM_SWR[13]),
.B0(n1358), .C0(n1657), .Y(n1367) );
OAI2BB1X1TS U1874 ( .A0N(n1360), .A1N(n1657), .B0(n1359), .Y(n1361) );
OAI21X1TS U1875 ( .A0(n1365), .A1(n1364), .B0(n1372), .Y(n1430) );
OAI2BB1X1TS U1876 ( .A0N(LZD_output_NRM2_EW[3]), .A1N(n944), .B0(n1430), .Y(
n567) );
OAI22X1TS U1877 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n1371), .B0(n1370), .B1(
n1708), .Y(n1373) );
OAI31X1TS U1878 ( .A0(n1375), .A1(n1374), .A2(n1373), .B0(n1372), .Y(n1426)
);
OAI2BB1X1TS U1879 ( .A0N(LZD_output_NRM2_EW[2]), .A1N(n943), .B0(n1426), .Y(
n576) );
OAI2BB1X1TS U1880 ( .A0N(LZD_output_NRM2_EW[0]), .A1N(n943), .B0(n1420), .Y(
n560) );
OA22X1TS U1881 ( .A0(n1380), .A1(n1377), .B0(n1726), .B1(
final_result_ieee[23]), .Y(n812) );
OA22X1TS U1882 ( .A0(n1380), .A1(n1378), .B0(n1726), .B1(
final_result_ieee[28]), .Y(n807) );
OA22X1TS U1883 ( .A0(n1380), .A1(n1379), .B0(n1726), .B1(
final_result_ieee[29]), .Y(n806) );
OA21XLTS U1884 ( .A0(n1726), .A1(overflow_flag), .B0(n1381), .Y(n609) );
AOI22X1TS U1885 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n1383), .B1(n1644), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U1886 ( .A(n1383), .B(n1382), .Y(n922) );
AOI32X4TS U1887 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n1384), .B1(n1682), .Y(n1389)
);
INVX2TS U1888 ( .A(n1389), .Y(n1388) );
AOI22X1TS U1889 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n1385), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n1644), .Y(n1390) );
BUFX3TS U1890 ( .A(n1725), .Y(n1462) );
AOI22X1TS U1891 ( .A0(n1389), .A1(n1386), .B0(n1462), .B1(n1388), .Y(n919)
);
AOI22X1TS U1892 ( .A0(n1389), .A1(n1462), .B0(n939), .B1(n1388), .Y(n918) );
INVX2TS U1893 ( .A(n1575), .Y(n1387) );
AOI22X1TS U1894 ( .A0(n1389), .A1(n1575), .B0(n944), .B1(n1388), .Y(n915) );
AOI22X1TS U1895 ( .A0(n1389), .A1(n943), .B0(n1612), .B1(n1388), .Y(n914) );
INVX2TS U1896 ( .A(n1393), .Y(n1402) );
INVX2TS U1897 ( .A(n1403), .Y(n1391) );
BUFX3TS U1898 ( .A(n1393), .Y(n1398) );
BUFX3TS U1899 ( .A(n1393), .Y(n1401) );
BUFX3TS U1900 ( .A(n1405), .Y(n1392) );
INVX2TS U1901 ( .A(n1403), .Y(n1404) );
INVX2TS U1902 ( .A(n1405), .Y(n1394) );
BUFX3TS U1903 ( .A(n1393), .Y(n1399) );
INVX2TS U1904 ( .A(n1405), .Y(n1395) );
BUFX3TS U1905 ( .A(n1393), .Y(n1397) );
INVX2TS U1906 ( .A(n1405), .Y(n1396) );
INVX2TS U1907 ( .A(n1403), .Y(n1400) );
OAI2BB2XLTS U1908 ( .B0(n1406), .B1(n951), .A0N(n1428), .A1N(
Data_array_SWR[24]), .Y(n847) );
AOI211X1TS U1909 ( .A0(DmP_mant_SHT1_SW[22]), .A1(n944), .B0(n1418), .C0(
n1408), .Y(n1412) );
OAI2BB2XLTS U1910 ( .B0(n1412), .B1(n950), .A0N(n1047), .A1N(
Data_array_SWR[23]), .Y(n846) );
AOI22X1TS U1911 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n1409), .B0(
DmP_mant_SHT1_SW[21]), .B1(n1072), .Y(n1410) );
AOI21X1TS U1912 ( .A0(DmP_mant_SHT1_SW[20]), .A1(n958), .B0(n1411), .Y(n1414) );
OAI222X1TS U1913 ( .A0(n956), .A1(n1636), .B0(n1211), .B1(n1412), .C0(n951),
.C1(n1414), .Y(n844) );
OAI222X1TS U1914 ( .A0(n1722), .A1(n956), .B0(n1211), .B1(n1414), .C0(n951),
.C1(n1413), .Y(n842) );
AOI22X1TS U1915 ( .A0(n960), .A1(DmP_mant_SHT1_SW[12]), .B0(n1418), .B1(
DmP_mant_SHT1_SW[13]), .Y(n1415) );
AOI21X1TS U1916 ( .A0(Raw_mant_NRM_SWR[11]), .A1(n1422), .B0(n1416), .Y(
n1423) );
OAI222X1TS U1917 ( .A0(n1654), .A1(n956), .B0(n1211), .B1(n1417), .C0(n950),
.C1(n1423), .Y(n836) );
AOI22X1TS U1918 ( .A0(n959), .A1(DmP_mant_SHT1_SW[10]), .B0(n1418), .B1(
DmP_mant_SHT1_SW[11]), .Y(n1419) );
AOI21X1TS U1919 ( .A0(Raw_mant_NRM_SWR[13]), .A1(n1422), .B0(n1421), .Y(
n1425) );
OAI222X1TS U1920 ( .A0(n1709), .A1(n956), .B0(n1211), .B1(n1423), .C0(n950),
.C1(n1425), .Y(n834) );
OAI222X1TS U1921 ( .A0(n1714), .A1(n956), .B0(n1211), .B1(n1425), .C0(n951),
.C1(n1424), .Y(n832) );
AOI32X1TS U1922 ( .A0(Shift_amount_SHT1_EWR[2]), .A1(n956), .A2(n943), .B0(
shift_value_SHT2_EWR[2]), .B1(n1047), .Y(n1427) );
NAND2X1TS U1923 ( .A(n1427), .B(n1426), .Y(n821) );
AOI32X1TS U1924 ( .A0(Shift_amount_SHT1_EWR[3]), .A1(n956), .A2(n944), .B0(
shift_value_SHT2_EWR[3]), .B1(n1428), .Y(n1431) );
NAND2X1TS U1925 ( .A(n1431), .B(n1430), .Y(n820) );
INVX2TS U1926 ( .A(n1462), .Y(n1464) );
AOI21X1TS U1927 ( .A0(DMP_EXP_EWSW[23]), .A1(n966), .B0(n1435), .Y(n1432) );
INVX2TS U1928 ( .A(n1463), .Y(n1441) );
AOI21X1TS U1929 ( .A0(DMP_EXP_EWSW[24]), .A1(n1652), .B0(n1433), .Y(n1434)
);
XNOR2X1TS U1930 ( .A(n1435), .B(n1434), .Y(n1436) );
XNOR2X1TS U1931 ( .A(n1439), .B(n1438), .Y(n1440) );
OAI222X1TS U1932 ( .A0(n1457), .A1(n1718), .B0(n1653), .B1(n1458), .C0(n1634), .C1(n1459), .Y(n780) );
OAI222X1TS U1933 ( .A0(n1457), .A1(n1655), .B0(n967), .B1(n1458), .C0(n1686),
.C1(n1459), .Y(n779) );
OAI222X1TS U1934 ( .A0(n1457), .A1(n1656), .B0(n1720), .B1(n1458), .C0(n1685), .C1(n1459), .Y(n778) );
INVX2TS U1935 ( .A(n1444), .Y(n1453) );
BUFX3TS U1936 ( .A(n1538), .Y(n1483) );
BUFX3TS U1937 ( .A(n1725), .Y(n1446) );
INVX2TS U1938 ( .A(n1444), .Y(n1619) );
INVX2TS U1939 ( .A(n1444), .Y(n1623) );
INVX2TS U1940 ( .A(n1463), .Y(n1447) );
INVX2TS U1941 ( .A(n1483), .Y(n1450) );
BUFX3TS U1942 ( .A(n1538), .Y(n1448) );
BUFX3TS U1943 ( .A(n1725), .Y(n1449) );
INVX2TS U1944 ( .A(n938), .Y(n1452) );
BUFX3TS U1945 ( .A(n939), .Y(n1451) );
BUFX3TS U1946 ( .A(n1538), .Y(n1518) );
BUFX3TS U1947 ( .A(n1725), .Y(n1466) );
INVX2TS U1948 ( .A(n1575), .Y(n1476) );
INVX2TS U1949 ( .A(n1462), .Y(n1454) );
BUFX3TS U1950 ( .A(n1463), .Y(n1455) );
BUFX3TS U1951 ( .A(n1462), .Y(n1456) );
OAI222X1TS U1952 ( .A0(n1459), .A1(n1718), .B0(n1652), .B1(n1458), .C0(n1634), .C1(n1457), .Y(n614) );
OAI222X1TS U1953 ( .A0(n1459), .A1(n1655), .B0(n1721), .B1(n1458), .C0(n1686), .C1(n1457), .Y(n613) );
OAI222X1TS U1954 ( .A0(n1459), .A1(n1656), .B0(n932), .B1(n1458), .C0(n1685),
.C1(n1457), .Y(n612) );
NAND2X1TS U1955 ( .A(n1460), .B(n1726), .Y(n1461) );
OAI2BB1X1TS U1956 ( .A0N(underflow_flag), .A1N(n1635), .B0(n1461), .Y(n610)
);
BUFX3TS U1957 ( .A(n1575), .Y(n1585) );
OAI22X1TS U1958 ( .A0(left_right_SHT2), .A1(n1485), .B0(n1709), .B1(n1592),
.Y(n1486) );
AOI211X1TS U1959 ( .A0(Data_array_SWR[13]), .A1(n1629), .B0(n1487), .C0(
n1486), .Y(n1586) );
AOI22X1TS U1960 ( .A0(n1633), .A1(n1586), .B0(n1674), .B1(n1624), .Y(n581)
);
AOI22X1TS U1961 ( .A0(n1523), .A1(DmP_mant_SFG_SWR[10]), .B0(n1580), .B1(
n1670), .Y(n1581) );
INVX2TS U1962 ( .A(n1572), .Y(n1489) );
AOI222X1TS U1963 ( .A0(DMP_SFG[10]), .A1(n1489), .B0(DMP_SFG[10]), .B1(n1573), .C0(n1489), .C1(n1573), .Y(n1490) );
XOR2X1TS U1964 ( .A(n1491), .B(n1490), .Y(n1492) );
XOR2X1TS U1965 ( .A(DMP_SFG[11]), .B(n1492), .Y(n1493) );
AOI22X1TS U1966 ( .A0(Data_array_SWR[13]), .A1(n1101), .B0(Data_array_SWR[9]), .B1(n1551), .Y(n1496) );
AOI22X1TS U1967 ( .A0(Data_array_SWR[5]), .A1(n1550), .B0(Data_array_SWR[1]),
.B1(n1510), .Y(n1495) );
OAI211X1TS U1968 ( .A0(n1503), .A1(n1640), .B0(n1496), .C0(n1495), .Y(n1611)
);
AOI22X1TS U1969 ( .A0(Data_array_SWR[23]), .A1(n1608), .B0(n1595), .B1(n1611), .Y(n1497) );
INVX1TS U1970 ( .A(DmP_mant_SFG_SWR[1]), .Y(n1498) );
AOI22X1TS U1971 ( .A0(n1633), .A1(n1497), .B0(n1498), .B1(n1624), .Y(n578)
);
AOI22X1TS U1972 ( .A0(n1523), .A1(n1498), .B0(DmP_mant_SFG_SWR[1]), .B1(
n1670), .Y(n1499) );
AOI22X1TS U1973 ( .A0(Data_array_SWR[12]), .A1(n1550), .B0(
Data_array_SWR[15]), .B1(n1551), .Y(n1502) );
AOI22X1TS U1974 ( .A0(Data_array_SWR[19]), .A1(n1101), .B0(
Data_array_SWR[23]), .B1(n1500), .Y(n1501) );
NAND2X1TS U1975 ( .A(n1502), .B(n1501), .Y(n1609) );
INVX2TS U1976 ( .A(n1503), .Y(n1607) );
INVX1TS U1977 ( .A(DmP_mant_SFG_SWR[8]), .Y(n1504) );
AOI22X1TS U1978 ( .A0(n1633), .A1(n1605), .B0(n1504), .B1(n1624), .Y(n575)
);
AOI22X1TS U1979 ( .A0(n1530), .A1(DmP_mant_SFG_SWR[8]), .B0(n1504), .B1(
n1670), .Y(n1565) );
AOI2BB2X1TS U1980 ( .B0(n1523), .B1(DmP_mant_SFG_SWR[6]), .A0N(
DmP_mant_SFG_SWR[6]), .A1N(OP_FLAG_SFG), .Y(n1561) );
OAI2BB1X1TS U1981 ( .A0N(n1541), .A1N(DMP_SFG[5]), .B0(n1506), .Y(n1546) );
XNOR2X1TS U1982 ( .A(DMP_SFG[7]), .B(n1567), .Y(n1507) );
XOR2X1TS U1983 ( .A(n1508), .B(n1507), .Y(n1509) );
AOI22X1TS U1984 ( .A0(n1387), .A1(n1509), .B0(n1668), .B1(n1585), .Y(n574)
);
AOI22X1TS U1985 ( .A0(Data_array_SWR[12]), .A1(n1101), .B0(Data_array_SWR[8]), .B1(n1551), .Y(n1512) );
AOI22X1TS U1986 ( .A0(Data_array_SWR[4]), .A1(n1550), .B0(Data_array_SWR[0]),
.B1(n1510), .Y(n1511) );
OAI211X1TS U1987 ( .A0(n1513), .A1(n1640), .B0(n1512), .C0(n1511), .Y(n1627)
);
AOI22X1TS U1988 ( .A0(Data_array_SWR[24]), .A1(n1608), .B0(n947), .B1(n1627),
.Y(n1514) );
INVX1TS U1989 ( .A(DmP_mant_SFG_SWR[0]), .Y(n1516) );
AOI22X1TS U1990 ( .A0(n1633), .A1(n1514), .B0(n1516), .B1(n1624), .Y(n572)
);
AOI22X1TS U1991 ( .A0(n1530), .A1(n1516), .B0(DmP_mant_SFG_SWR[0]), .B1(
n1670), .Y(n1517) );
AOI2BB2X1TS U1992 ( .B0(n1523), .B1(DmP_mant_SFG_SWR[2]), .A0N(
DmP_mant_SFG_SWR[2]), .A1N(n1522), .Y(n1520) );
NAND2X1TS U1993 ( .A(n1520), .B(DMP_SFG[0]), .Y(n1526) );
AOI22X1TS U1994 ( .A0(n1387), .A1(n1521), .B0(n1672), .B1(n1585), .Y(n569)
);
XNOR2X1TS U1995 ( .A(DMP_SFG[1]), .B(n1526), .Y(n1524) );
XNOR2X1TS U1996 ( .A(n1524), .B(n1527), .Y(n1525) );
AOI22X1TS U1997 ( .A0(n1387), .A1(n1525), .B0(n1708), .B1(n1585), .Y(n568)
);
INVX1TS U1998 ( .A(DmP_mant_SFG_SWR[4]), .Y(n1556) );
AOI22X1TS U1999 ( .A0(n1530), .A1(n1556), .B0(DmP_mant_SFG_SWR[4]), .B1(
n1529), .Y(n1558) );
INVX2TS U2000 ( .A(n1526), .Y(n1528) );
XNOR2X1TS U2001 ( .A(n1532), .B(n1531), .Y(n1533) );
AOI22X1TS U2002 ( .A0(Data_array_SWR[13]), .A1(n1551), .B0(Data_array_SWR[9]), .B1(n1550), .Y(n1535) );
NAND2X1TS U2003 ( .A(Data_array_SWR[16]), .B(n1101), .Y(n1534) );
OAI211X1TS U2004 ( .A0(n1554), .A1(n1640), .B0(n1535), .C0(n1534), .Y(n1602)
);
AO22X1TS U2005 ( .A0(Data_array_SWR[19]), .A1(n1537), .B0(Data_array_SWR[23]), .B1(n1536), .Y(n1601) );
BUFX3TS U2006 ( .A(n1538), .Y(n1630) );
AOI22X1TS U2007 ( .A0(n1619), .A1(n1600), .B0(n931), .B1(n1630), .Y(n564) );
AOI222X1TS U2008 ( .A0(n1712), .A1(n1540), .B0(n1712), .B1(n1539), .C0(n1540), .C1(n1539), .Y(n1562) );
XNOR2X1TS U2009 ( .A(DMP_SFG[5]), .B(n1541), .Y(n1542) );
XOR2X1TS U2010 ( .A(n1543), .B(n1542), .Y(n1544) );
AOI22X1TS U2011 ( .A0(n1387), .A1(n1544), .B0(n1659), .B1(n1585), .Y(n563)
);
AOI22X1TS U2012 ( .A0(Data_array_SWR[12]), .A1(n1551), .B0(Data_array_SWR[8]), .B1(n1550), .Y(n1553) );
AOI22X1TS U2013 ( .A0(Data_array_SWR[15]), .A1(n1101), .B0(
shift_value_SHT2_EWR[4]), .B1(n1601), .Y(n1552) );
NAND2X1TS U2014 ( .A(n1553), .B(n1552), .Y(n1599) );
INVX2TS U2015 ( .A(n1554), .Y(n1598) );
AOI22X1TS U2016 ( .A0(n1619), .A1(n1597), .B0(n1556), .B1(n1630), .Y(n559)
);
CMPR32X2TS U2017 ( .A(n1724), .B(n1558), .C(n1557), .CO(n1532), .S(n1559) );
AOI22X1TS U2018 ( .A0(n970), .A1(n1559), .B0(n1641), .B1(n1575), .Y(n558) );
OAI2BB1X1TS U2019 ( .A0N(n1567), .A1N(DMP_SFG[7]), .B0(n1566), .Y(n1582) );
XNOR2X1TS U2020 ( .A(DMP_SFG[9]), .B(n953), .Y(n1568) );
XOR2X1TS U2021 ( .A(n1569), .B(n1568), .Y(n1570) );
AOI22X1TS U2022 ( .A0(n1387), .A1(n1570), .B0(n1660), .B1(n1575), .Y(n554)
);
OAI22X1TS U2023 ( .A0(n1636), .A1(n1102), .B0(n1711), .B1(n1577), .Y(n1594)
);
OAI222X1TS U2024 ( .A0(n1577), .A1(n955), .B0(n1578), .B1(n1637), .C0(n1710),
.C1(n1102), .Y(n1596) );
OAI22X1TS U2025 ( .A0(n1654), .A1(n1592), .B0(n1715), .B1(n1105), .Y(n1571)
);
AOI221X1TS U2026 ( .A0(left_right_SHT2), .A1(n1594), .B0(n947), .B1(n1596),
.C0(n1571), .Y(n1591) );
AOI22X1TS U2027 ( .A0(n1619), .A1(n1591), .B0(n926), .B1(n1624), .Y(n553) );
XNOR2X1TS U2028 ( .A(DMP_SFG[10]), .B(n1572), .Y(n1574) );
XNOR2X1TS U2029 ( .A(n1574), .B(n1573), .Y(n1576) );
AOI22X1TS U2030 ( .A0(n1387), .A1(n1576), .B0(n1658), .B1(n1575), .Y(n552)
);
OAI22X1TS U2031 ( .A0(n1637), .A1(n1102), .B0(n1710), .B1(n1577), .Y(n1589)
);
OAI222X1TS U2032 ( .A0(n1102), .A1(n1711), .B0(n1578), .B1(n1636), .C0(n1654), .C1(n1577), .Y(n1590) );
OAI22X1TS U2033 ( .A0(n1714), .A1(n1105), .B0(n955), .B1(n1592), .Y(n1579)
);
AOI221X1TS U2034 ( .A0(n954), .A1(n1589), .B0(n947), .B1(n1590), .C0(n1579),
.Y(n1587) );
AOI22X1TS U2035 ( .A0(n1619), .A1(n1587), .B0(n1580), .B1(n1630), .Y(n551)
);
OAI2BB2XLTS U2036 ( .B0(n1586), .B1(n936), .A0N(final_result_ieee[11]),
.A1N(n1610), .Y(n547) );
OAI2BB2XLTS U2037 ( .B0(n1587), .B1(n936), .A0N(final_result_ieee[8]), .A1N(
n1610), .Y(n546) );
OAI22X1TS U2038 ( .A0(n1714), .A1(n1592), .B0(n955), .B1(n1105), .Y(n1588)
);
AOI221X1TS U2039 ( .A0(left_right_SHT2), .A1(n1590), .B0(n946), .B1(n1589),
.C0(n1588), .Y(n1615) );
OAI2BB2XLTS U2040 ( .B0(n1615), .B1(n936), .A0N(final_result_ieee[13]),
.A1N(n1610), .Y(n545) );
OAI2BB2XLTS U2041 ( .B0(n1591), .B1(n936), .A0N(final_result_ieee[9]), .A1N(
n1610), .Y(n544) );
OAI22X1TS U2042 ( .A0(n1654), .A1(n1105), .B0(n1715), .B1(n1592), .Y(n1593)
);
AOI221X1TS U2043 ( .A0(n954), .A1(n1596), .B0(n947), .B1(n1594), .C0(n1593),
.Y(n1614) );
OAI2BB2XLTS U2044 ( .B0(n1614), .B1(n936), .A0N(final_result_ieee[12]),
.A1N(n1610), .Y(n543) );
OAI2BB2XLTS U2045 ( .B0(n1597), .B1(n1613), .A0N(final_result_ieee[2]),
.A1N(n1612), .Y(n538) );
OAI2BB2XLTS U2046 ( .B0(n1621), .B1(n936), .A0N(final_result_ieee[19]),
.A1N(n1612), .Y(n537) );
OAI2BB2XLTS U2047 ( .B0(n1600), .B1(n1613), .A0N(final_result_ieee[3]),
.A1N(n1612), .Y(n534) );
OAI2BB2XLTS U2048 ( .B0(n1618), .B1(n1613), .A0N(final_result_ieee[18]),
.A1N(n1612), .Y(n533) );
OAI2BB2XLTS U2049 ( .B0(n1605), .B1(n1613), .A0N(final_result_ieee[6]),
.A1N(n1612), .Y(n530) );
OAI2BB2XLTS U2050 ( .B0(n1616), .B1(n1613), .A0N(final_result_ieee[15]),
.A1N(n1610), .Y(n529) );
AOI22X1TS U2051 ( .A0(Data_array_SWR[23]), .A1(n1629), .B0(left_right_SHT2),
.B1(n1611), .Y(n1626) );
OAI2BB2XLTS U2052 ( .B0(n1626), .B1(n936), .A0N(final_result_ieee[22]),
.A1N(n1612), .Y(n526) );
AOI22X1TS U2053 ( .A0(n1633), .A1(n1614), .B0(n963), .B1(n1630), .Y(n525) );
AOI22X1TS U2054 ( .A0(n1633), .A1(n1615), .B0(n964), .B1(n1630), .Y(n524) );
AOI22X1TS U2055 ( .A0(n1633), .A1(n1616), .B0(n965), .B1(n1630), .Y(n522) );
AOI22X1TS U2056 ( .A0(n1619), .A1(n1618), .B0(n1617), .B1(n1630), .Y(n519)
);
AOI22X1TS U2057 ( .A0(n1633), .A1(n1621), .B0(n1620), .B1(n1630), .Y(n518)
);
AOI22X1TS U2058 ( .A0(n1633), .A1(n1626), .B0(n1625), .B1(n1630), .Y(n515)
);
AOI22X1TS U2059 ( .A0(Data_array_SWR[24]), .A1(n1629), .B0(n945), .B1(n1627),
.Y(n1632) );
AOI22X1TS U2060 ( .A0(n1633), .A1(n1632), .B0(n1631), .B1(n1630), .Y(n514)
);
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk10.tcl_ACAIIN16Q4_syn.sdf");
endmodule
|
// megafunction wizard: %RAM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: Ram_Real.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 178 05/31/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module Ram_Real (
address,
byteena,
clock,
data,
wren,
q);
input [9:0] address;
input [3:0] byteena;
input clock;
input [31:0] data;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [3:0] byteena;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "32"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "TRUE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: byteena 0 0 4 0 INPUT VCC "byteena[3..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL Ram_Real.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Ram_Real.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Ram_Real.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Ram_Real.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Ram_Real_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Ram_Real_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ac
//
// Generated
// by: wig
// on: Tue Jul 4 08:39:13 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ac.v,v 1.3 2007/03/05 13:33:58 wig Exp $
// $Date: 2007/03/05 13:33:58 $
// $Log: ent_ac.v,v $
// Revision 1.3 2007/03/05 13:33:58 wig
// Updated testcase output (only comments)!
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_ac
//
// No user `defines in this module
module ent_ac
//
// Generated Module inst_ac
//
(
port_ac_2 // Use internally test2, no port generated
);
// Generated Module Outputs:
output port_ac_2;
// Generated Wires:
reg port_ac_2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of ent_ac
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND3B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__AND3B_FUNCTIONAL_PP_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__and3b (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , C, not0_out, B );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND3B_FUNCTIONAL_PP_V |
///////////////////////////////////////////////////////////////////////////////
//
// Module: cnet_reg_iface.v
// Project: CPCI (PCI Control FPGA)
// Description: Register interface module to the CNET.
// Manages the crossing of data between the PCI clock domain
// and the *NET core clock domain.
// Performs chip to chip communication
//
// Note: cnet_rd_time should not change a few clocks before issuing a read.
// This is for synchronization reasons.
//
// Care should be taken not to have more than two reads in the buffer at
// the same time otherwise the result of one may overwrite the result
// of the other.
//
//
// Issues to address:
//
///////////////////////////////////////////////////////////////////////////////
module cnet_reg_iface (
// CPCI internal signals
// CPCI->CNET
input [`CPCI_CNET_DATA_WIDTH-1:0] p2n_data, // Data going from the CPCI to the CNET
input [`CPCI_CNET_ADDR_WIDTH-1:0] p2n_addr, // Data going from the CPCI to the CNET
input p2n_we, // Write enable signal
input p2n_req, // Read/Write request signal
output p2n_full, // Full signal for FIFO from CPCI to CNET
output p2n_almost_full, // Almost full signal
// CNET->CPCI
output reg [`CPCI_CNET_DATA_WIDTH-1:0] n2p_data, // Data going from the CPCI to the CNET
output reg n2p_rd_rdy, // Read enable signal
// Miscelaneous signals
input cnet_reprog, // Indicates that the CNET is
// currently being reprogrammed
input cnet_hit, // CNET hit signal
input [31:0] cnet_rd_time, // Number of clocks before a CNET read timeout occurs
output cnet_rd_timeout, // Indicated a timeout has occured
// CNET interface signals
output reg cpci_rd_wr_L, // Read or write request (read high, write low)
output reg cpci_req, // Transaction Request
output reg [`CPCI_CNET_ADDR_WIDTH-1:0] cpci_addr, // Address
output reg [`CPCI_CNET_DATA_WIDTH-1:0] cpci_data_wr, // Data
input [`CPCI_CNET_DATA_WIDTH-1:0] cpci_data_rd, // Data
output reg cpci_data_tri_en, // Tri-state enable
input cpci_wr_rdy, // Was the write accepted?
input cpci_rd_rdy, // Is the read result ready?
input reset,
input pclk, // PCI clock
input nclk // *NET clock
);
// ==================================================================
// Local
// ==================================================================
// Local version of external signals
// Allows flops in external signals to be pushed into the IOBs!
// Note: Don't need internal flops for cpci_req or cpci_data_tri_en
// as the next value doesn't depend upon the current value
wire [`CPCI_CNET_DATA_WIDTH-1:0] fifo_data;
wire [`CPCI_CNET_ADDR_WIDTH-1:0] fifo_addr;
wire fifo_wr;
reg [`CPCI_CNET_DATA_WIDTH-1:0] cpci_data_wr_nxt;
reg [`CPCI_CNET_ADDR_WIDTH-1:0] cpci_addr_nxt;
reg cpci_rd_wr_L_nxt;
reg want_cpci_req_nxt;
reg cpci_req_nxt;
reg cpci_data_tri_en_nxt;
// Is the output from FIFO "good" - meaning is it new unprocessed data?
reg fifo_data_good, fifo_data_good_nxt;
reg fifo_data_good_d1;
// Read or write transaction has completed successfully
wire rd_done, wr_done;
// Track data coming back from the CNET
reg cnet_rd_tgl_1, cnet_rd_tgl_1_nxt;
reg cnet_rd_tgl_2, cnet_rd_tgl_2_nxt;
reg [`CPCI_CNET_DATA_WIDTH-1:0] cnet_rd_result_1;
reg [`CPCI_CNET_DATA_WIDTH-1:0] cnet_rd_result_1_nxt;
reg [`CPCI_CNET_DATA_WIDTH-1:0] cnet_rd_result_2;
reg [`CPCI_CNET_DATA_WIDTH-1:0] cnet_rd_result_2_nxt;
reg cnet_rd_tgl_1_pclk1, cnet_rd_tgl_1_pclk2, cnet_rd_tgl_1_pclk2_d1;
reg cnet_rd_tgl_2_pclk1, cnet_rd_tgl_2_pclk2, cnet_rd_tgl_2_pclk2_d1;
reg curr_result_buf, curr_result_buf_nxt;
// N-Clk reset signal
reg nreset_1, nreset;
// N-Clk cnet_reprog signal
reg ncnet_reprog_1, ncnet_reprog;
// Force a FIFO read
reg force_fifo_rd;
wire force_fifo_rd_nxt;
// Read timer
reg [31:0] rd_timer, rd_timer_nxt;
reg [31:0] max_rd_time, max_rd_time_1;
reg nrd_timeout, nrd_timeout_nxt;
reg prd_timeout, prd_timeout_1, prd_timeout_d1, prd_timeout_d2;
// Signal to force data capture
wire n2p_data_capture_1;
wire n2p_data_capture_2;
// Delayed version of cpci_wr_rdy, cpci_rd_rdy and cpci_data_rd
reg cpci_wr_rdy_d1;
reg cpci_rd_rdy_d1;
reg [`CPCI_CNET_DATA_WIDTH-1:0] cpci_data_rd_d1;
// Want cpci req signal
reg want_cpci_req;
// ==================================================================
// Asynchronous FIFO
// ==================================================================
//cpci_pci2net_16x60 cpci_pci2net_fifo (
// .din ({p2n_we, p2n_addr, p2n_data}),
// .rd_clk (nclk),
// .rd_en (fifo_rd_en),
// .rst (reset || cnet_reprog),
// .wr_clk (pclk),
// .wr_en (p2n_req),
// .almost_full (p2n_almost_full),
// .dout ({fifo_wr, fifo_addr, fifo_data}),
// .empty (fifo_empty),
// .full (p2n_full)
// );
cpci_pci2net_16x60 cpci_pci2net_fifo (
.aclr (reset || cnet_reprog),
.clock (nclk),
.data ({p2n_we, p2n_addr, p2n_data}),
.rdreq (fifo_rd_en),
.wrreq (p2n_req),
.almost_full (p2n_almost_full),
.empty (fifo_empty),
.full (p2n_full),
.q ({fifo_wr, fifo_addr, fifo_data})
);
// ==================================================================
// Main state machine
// ==================================================================
reg [1:0] curr_state, curr_state_nxt;
`define Bus_Idle 2'h0
`define Bus_Read 2'h1
`define Bus_Write 2'h2
always @(posedge nclk)
begin
curr_state <= curr_state_nxt;
cpci_req <= cpci_req_nxt;
cpci_data_wr <= cpci_data_wr_nxt;
cpci_data_tri_en <= cpci_data_tri_en_nxt;
cpci_addr <= cpci_addr_nxt;
cpci_rd_wr_L <= cpci_rd_wr_L_nxt;
want_cpci_req <= want_cpci_req_nxt;
nrd_timeout <= nrd_timeout_nxt;
fifo_data_good <= fifo_data_good_nxt;
fifo_data_good_d1 <= fifo_data_good;
end
// Calculate the next state
always @*
begin
// Default to the previous state
curr_state_nxt = curr_state;
nrd_timeout_nxt = nrd_timeout;
// On either reset or the CNET being reprogrammed, go to the idle state
if (nreset || ncnet_reprog) begin
curr_state_nxt = `Bus_Idle;
nrd_timeout_nxt = 1'b0;
end
else
case (curr_state)
`Bus_Idle : begin
if (fifo_data_good)
if (fifo_wr)
curr_state_nxt = `Bus_Write;
else
curr_state_nxt = `Bus_Read;
end
`Bus_Read : begin
// Force a turn-around cycle after a read
if (rd_done) begin
curr_state_nxt = `Bus_Idle;
if (!cpci_rd_rdy_d1)
nrd_timeout_nxt = ~nrd_timeout;
end
end
`Bus_Write : begin
if (wr_done)
if (fifo_data_good) begin
if (fifo_wr)
curr_state_nxt = `Bus_Write;
else
curr_state_nxt = `Bus_Read;
end
else begin
curr_state_nxt = `Bus_Idle;
end
end
endcase
end
// Calculate the next value of the cpci* signals
always @*
begin
// Set defaults
cpci_data_wr_nxt = cpci_data_wr;
cpci_addr_nxt = cpci_addr;
cpci_rd_wr_L_nxt = cpci_rd_wr_L;
want_cpci_req_nxt = want_cpci_req && !rd_done && !(wr_done && cpci_wr_rdy_d1);
cpci_req_nxt = want_cpci_req && !rd_done && !(wr_done && cpci_wr_rdy_d1) && (cpci_rd_wr_L|| cpci_wr_rdy_d1);
cpci_data_tri_en_nxt = want_cpci_req && !rd_done && !(wr_done && cpci_wr_rdy_d1) && !cpci_rd_wr_L;
// On either reset or the CNET being reprogrammed, go to the idle state
if (nreset || ncnet_reprog) begin
cpci_data_wr_nxt = 'h0;
cpci_addr_nxt = 'h0;
cpci_rd_wr_L_nxt = 1'b0;
want_cpci_req_nxt = 1'b0;
cpci_req_nxt = 1'b0;
cpci_data_tri_en_nxt = 1'b0;
end
else if (fifo_data_good && (!want_cpci_req || wr_done)) begin
// Latch through the next values
cpci_data_wr_nxt = fifo_data;
cpci_addr_nxt = fifo_addr;
cpci_rd_wr_L_nxt = !fifo_wr;
want_cpci_req_nxt = 1'b1;
cpci_req_nxt = !fifo_wr || cpci_wr_rdy_d1;
cpci_data_tri_en_nxt = fifo_wr;
end
end
// fifo_data_good
always @*
begin
fifo_data_good_nxt = fifo_data_good;
if (reset || cnet_reprog)
fifo_data_good_nxt = 1'b0;
else if (fifo_rd_en && !fifo_empty)
fifo_data_good_nxt = 1'b1;
else if (fifo_data_good && (!want_cpci_req || wr_done) && cpci_wr_rdy_d1)
fifo_data_good_nxt = 1'b0;
end
// ==================================================================
// Latch the data returning from the CNET
// ==================================================================
always @(posedge nclk)
begin
curr_result_buf <= curr_result_buf_nxt;
cnet_rd_result_1 <= cnet_rd_result_1_nxt;
cnet_rd_tgl_1 <= cnet_rd_tgl_1_nxt;
cnet_rd_result_2 <= cnet_rd_result_2_nxt;
cnet_rd_tgl_2 <= cnet_rd_tgl_2_nxt;
end
always @*
begin
// Restore prev value
curr_result_buf_nxt = curr_result_buf;
cnet_rd_tgl_1_nxt = cnet_rd_tgl_1;
cnet_rd_result_1_nxt = cnet_rd_result_1;
cnet_rd_tgl_2_nxt = cnet_rd_tgl_2;
cnet_rd_result_2_nxt = cnet_rd_result_2;
if (nreset) begin
curr_result_buf_nxt = 1'b0;
cnet_rd_tgl_1_nxt = 1'b0;
cnet_rd_result_1_nxt = 'h0;
cnet_rd_tgl_2_nxt = 1'b0;
cnet_rd_result_2_nxt = 'h0;
end
else if (want_cpci_req && rd_done) begin
if (!curr_result_buf) begin
cnet_rd_tgl_1_nxt = !cnet_rd_tgl_1;
cnet_rd_result_1_nxt = cpci_rd_rdy_d1 ? cpci_data_rd_d1 : 'h dead_beef;
end
else begin
cnet_rd_tgl_2_nxt = !cnet_rd_tgl_2;
cnet_rd_result_2_nxt = cpci_rd_rdy_d1 ? cpci_data_rd_d1 : 'h dead_beef;
end
curr_result_buf_nxt = ~curr_result_buf_nxt;
end
end
// Synchronize
//
// Note: No series of flops for the bus to do with sync issues
//
// Wait for the capture signal to propagate through and then latch when
// capture is asserted. (The output on cnet_rd_result_1 HAS to be stable then
// provided that we haven't changed the value on it's output.)
always @(posedge pclk)
begin
if (n2p_data_capture_1) begin
n2p_data <= cnet_rd_result_1;
end
else if (n2p_data_capture_2) begin
n2p_data <= cnet_rd_result_2;
end
n2p_rd_rdy <= n2p_data_capture_1 | n2p_data_capture_2;
end
always @(posedge pclk)
begin
if (reset) begin
cnet_rd_tgl_1_pclk1 <= 1'b0;
cnet_rd_tgl_1_pclk2 <= 1'b0;
cnet_rd_tgl_1_pclk2_d1 <= 1'b0;
cnet_rd_tgl_2_pclk1 <= 1'b0;
cnet_rd_tgl_2_pclk2 <= 1'b0;
cnet_rd_tgl_2_pclk2_d1 <= 1'b0;
end
else begin
cnet_rd_tgl_1_pclk1 <= cnet_rd_tgl_1;
cnet_rd_tgl_1_pclk2 <= cnet_rd_tgl_1_pclk1;
cnet_rd_tgl_1_pclk2_d1 <= cnet_rd_tgl_1_pclk2;
cnet_rd_tgl_2_pclk1 <= cnet_rd_tgl_2;
cnet_rd_tgl_2_pclk2 <= cnet_rd_tgl_2_pclk1;
cnet_rd_tgl_2_pclk2_d1 <= cnet_rd_tgl_2_pclk2;
end
end
assign n2p_data_capture_1 = cnet_rd_tgl_1_pclk2 != cnet_rd_tgl_1_pclk2_d1;
assign n2p_data_capture_2 = cnet_rd_tgl_2_pclk2 != cnet_rd_tgl_2_pclk2_d1;
// ==================================================================
// Read timeout logic
// ==================================================================
always @(posedge nclk)
begin
rd_timer <= rd_timer_nxt;
end
always @*
begin
rd_timer_nxt = rd_timer;
if (fifo_rd_en && !fifo_empty)
rd_timer_nxt = max_rd_time;
else if (cpci_rd_wr_L && rd_timer != 0)
rd_timer_nxt = rd_timer - 'h1;
end
always @(posedge nclk)
begin
max_rd_time <= max_rd_time_1;
max_rd_time_1 <= cnet_rd_time;
end
always @(posedge pclk)
begin
if (reset) begin
prd_timeout_1 <= 1'b0;
prd_timeout <= 1'b0;
prd_timeout_d1 <= 1'b0;
prd_timeout_d2 <= 1'b0;
end
else begin
prd_timeout_1 <= nrd_timeout;
prd_timeout <= prd_timeout_1;
prd_timeout_d1 <= prd_timeout;
prd_timeout_d2 <= prd_timeout_d1;
end
end
// Note: Use d1 and d2 as output takes one extra clocked since it has to
// be registered before it is output.
assign cnet_rd_timeout = prd_timeout_d1 != prd_timeout_d2;
// ==================================================================
// N-Reset generation
// ==================================================================
always @(posedge nclk)
begin
nreset_1 <= reset;
nreset <= nreset_1;
end
always @(posedge nclk)
begin
ncnet_reprog_1 <= cnet_reprog;
ncnet_reprog <= ncnet_reprog_1;
end
// ==================================================================
// Miscelaneous signal generation
// ==================================================================
// Delay cpci_wr_rdy, cpci_rd_rdy and cpci_rd_data
// Allows FFs to be pushed into IOBs making timing *much* easier :)
always @(posedge nclk) begin
cpci_wr_rdy_d1 <= cpci_wr_rdy;
cpci_rd_rdy_d1 <= cpci_rd_rdy;
cpci_data_rd_d1 <= cpci_data_rd;
end
// Generate the read and write done signals
assign rd_done = cpci_rd_wr_L && (cpci_rd_rdy_d1 || rd_timer == 'h0);
assign wr_done = !cpci_rd_wr_L && cpci_wr_rdy_d1;
// When should data be read from the fifo?
assign fifo_rd_en = !fifo_data_good || force_fifo_rd || wr_done;
// Force a FIFO read on the next clock if the bus is currently idle and
// there isn't currently a read in progress
always @(posedge nclk) begin
force_fifo_rd <= force_fifo_rd_nxt;
end
assign force_fifo_rd_nxt = !want_cpci_req && !fifo_data_good && !fifo_rd_en;
// ==================================================================
// Debug logic
// ==================================================================
// synthesis translate_off
// Attempt to detect if the cnet_rd_time changes when starting a read
reg [31:0] cnet_rd_time_d1;
always @(posedge pclk)
begin
if (reset)
cnet_rd_time_d1 <= 'h0;
else
cnet_rd_time_d1 <= cnet_rd_time;
if (cnet_rd_time != cnet_rd_time_d1 && fifo_rd_en && !fifo_empty)
$display($time, " ERROR: cnet_rd_time changed while initiating a read in %m");
end
// Try to detect when a read result is missed (should never happen as there
// shouldn't be overlapping reads)
reg [1:0] wait_for_capture;
always @(posedge nclk)
begin
if (nreset)
wait_for_capture <= 2'b00;
else if (cpci_req && rd_done) begin
// Check to see if there is an outstanding capture request
if (wait_for_capture == 2'b11)
$display($time, " ERROR: Read data returned while waiting for previous read to be captured in %m");
wait_for_capture <= {wait_for_capture[0], 1'b1};
end
end
always @(posedge pclk)
begin
if (n2p_data_capture_1 || n2p_data_capture_2)
wait_for_capture <= {wait_for_capture[0], 1'b0};
end
// synthesis translate_on
endmodule // cnet_reg_iface
/* vim:set shiftwidth=3 softtabstop=3 expandtab: */
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