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(** * Logic: Logic in Coq *)
Require Export MoreCoq.
(** Coq's built-in logic is very small: the only primitives are
[Inductive] definitions, universal quantification ([forall]), and
implication ([->]), while all the other familiar logical
connectives -- conjunction, disjunction, negation, existential
quantification, even equality -- can be encoded using just these.
This chapter explains the encodings and shows how the tactics
we've seen can be used to carry out standard forms of logical
reasoning involving these connectives. *)
(* ########################################################### *)
(** * Propositions *)
(** In previous chapters, we have seen many examples of factual
claims (_propositions_) and ways of presenting evidence of their
truth (_proofs_). In particular, we have worked extensively with
_equality propositions_ of the form [e1 = e2], with
implications ([P -> Q]), and with quantified propositions
([forall x, P]).
*)
(** In Coq, the type of things that can (potentially)
be proven is [Prop]. *)
(** Here is an example of a provable proposition: *)
Check (3 = 3).
(* ===> Prop *)
(** Here is an example of an unprovable proposition: *)
Check (forall (n:nat), n = 2).
(* ===> Prop *)
(** Recall that [Check] asks Coq to tell us the type of the indicated
expression. *)
(* ########################################################### *)
(** * Proofs and Evidence *)
(** In Coq, propositions have the same status as other types, such as
[nat]. Just as the natural numbers [0], [1], [2], etc. inhabit
the type [nat], a Coq proposition [P] is inhabited by its
_proofs_. We will refer to such inhabitants as _proof term_ or
_proof object_ or _evidence_ for the truth of [P].
In Coq, when we state and then prove a lemma such as:
Lemma silly : 0 * 3 = 0.
Proof. reflexivity. Qed.
the tactics we use within the [Proof]...[Qed] keywords tell Coq
how to construct a proof term that inhabits the proposition. In
this case, the proposition [0 * 3 = 0] is justified by a
combination of the _definition_ of [mult], which says that [0 * 3]
_simplifies_ to just [0], and the _reflexive_ principle of
equality, which says that [0 = 0].
*)
(** *** *)
Lemma silly : 0 * 3 = 0.
Proof. reflexivity. Qed.
(** We can see which proof term Coq constructs for a given Lemma by
using the [Print] directive: *)
Print silly.
(* ===> silly = eq_refl : 0 * 3 = 0 *)
(** Here, the [eq_refl] proof term witnesses the equality. (More on equality later!)*)
(** ** Implications _are_ functions *)
(** Just as we can implement natural number multiplication as a
function:
[
mult : nat -> nat -> nat
]
The _proof term_ for an implication [P -> Q] is a _function_ that takes evidence for [P] as input and produces evidence for [Q] as its output.
*)
Lemma silly_implication : (1 + 1) = 2 -> 0 * 3 = 0.
Proof. intros H. reflexivity. Qed.
Definition silly_implication2 : (1 + 1) = 2 -> 0 * 3 = 0
:= fun _ => eq_refl.
(** We can see that the proof term for the above lemma is indeed a
function: *)
Print silly_implication.
(* ===> silly_implication = fun _ : 1 + 1 = 2 => eq_refl
: 1 + 1 = 2 -> 0 * 3 = 0 *)
(** ** Defining Propositions *)
(** Just as we can create user-defined inductive types (like the
lists, binary representations of natural numbers, etc., that we
seen before), we can also create _user-defined_ propositions.
Question: How do you define the meaning of a proposition?
*)
(** *** *)
(** The meaning of a proposition is given by _rules_ and _definitions_
that say how to construct _evidence_ for the truth of the
proposition from other evidence.
- Typically, rules are defined _inductively_, just like any other datatype.
- Sometimes a proposition is declared to be true without substantiating evidence. Such propositions are called _axioms_.
In this, and subsequence chapters, we'll see more about how these
proof terms work in more detail.
*)
(* ########################################################### *)
(** * Conjunction (Logical "and") *)
(** The logical conjunction of propositions [P] and [Q] can be
represented using an [Inductive] definition with one
constructor. *)
Inductive and (P Q : Prop) : Prop :=
conj : P -> Q -> (and P Q).
(** The intuition behind this definition is simple: to
construct evidence for [and P Q], we must provide evidence
for [P] and evidence for [Q]. More precisely:
- [conj p q] can be taken as evidence for [and P Q] if [p]
is evidence for [P] and [q] is evidence for [Q]; and
- this is the _only_ way to give evidence for [and P Q] --
that is, if someone gives us evidence for [and P Q], we
know it must have the form [conj p q], where [p] is
evidence for [P] and [q] is evidence for [Q].
Since we'll be using conjunction a lot, let's introduce a more
familiar-looking infix notation for it. *)
Print "/\".
(**
Inductive and (A B : Prop) : Prop := conj : A -> B -> A /\ B
For conj: Arguments A, B are implicit
For and: Argument scopes are [type_scope type_scope]
For conj: Argument scopes are [type_scope type_scope _ _]
**)
Notation "P /\ Q" := (and P Q) : type_scope.
Print "/\".
(**
Inductive and (P Q : Prop) : Prop := conj : P -> Q -> P /\ Q
For and: Argument scopes are [type_scope type_scope]
For conj: Argument scopes are [type_scope type_scope _ _]
**)
(** (The [type_scope] annotation tells Coq that this notation
will be appearing in propositions, not values.) *)
(** Consider the "type" of the constructor [conj]: *)
Check conj.
Print conj.
Check and.
(* ===> forall P Q : Prop, P -> Q -> P /\ Q *)
(** BELOW IS KEY **)
(** Notice that it takes 4 inputs -- namely the propositions [P]
and [Q] and evidence for [P] and [Q] -- and returns as output the
evidence of [P /\ Q]. *)
(** ** "Introducing" Conjuctions *)
(** Besides the elegance of building everything up from a tiny
foundation, what's nice about defining conjunction this way is
that we can prove statements involving conjunction using the
tactics that we already know. For example, if the goal statement
is a conjuction, we can prove it by applying the single
constructor [conj], which (as can be seen from the type of [conj])
solves the current goal and leaves the two parts of the
conjunction as subgoals to be proved separately. *)
Theorem and_example :
(0 = 0) /\ (4 = mult 2 2).
Proof.
apply conj.
Case "left". reflexivity.
Case "right". reflexivity. Qed.
Definition and_example2: (0 = 0) /\ (4 = mult 2 2)
:= conj (0 = 0) (4 = mult 2 2) eq_refl eq_refl.
(** Just for convenience, we can use the tactic [split] as a shorthand for
[apply conj]. *)
Theorem and_example' :
(0 = 0) /\ (4 = mult 2 2).
Proof.
split.
Case "left". reflexivity.
Case "right". reflexivity. Qed.
(** ** "Eliminating" conjunctions *)
(** Conversely, the [inversion] tactic can be used to take a
conjunction hypothesis in the context, calculate what evidence
must have been used to build it, and add variables representing
this evidence to the proof context. *)
Theorem proj1 : forall P Q : Prop,
P /\ Q -> P.
Proof.
intros P Q H.
inversion H as [HP HQ].
apply HP. Qed.
(** **** Exercise: 1 star, optional (proj2) *)
Theorem proj2 : forall P Q : Prop,
P /\ Q -> Q.
Proof.
intros P Q H.
inversion H.
apply H1.
Qed.
Theorem and_commut : forall P Q : Prop,
P /\ Q -> Q /\ P.
Proof.
(* WORKED IN CLASS *)
intros P Q H.
inversion H as [HP HQ].
split.
Case "left". apply HQ.
Case "right". apply HP. Qed.
(** **** Exercise: 2 stars (and_assoc) *)
(** In the following proof, notice how the _nested pattern_ in the
[inversion] breaks the hypothesis [H : P /\ (Q /\ R)] down into
[HP: P], [HQ : Q], and [HR : R]. Finish the proof from there: *)
Theorem and_assoc : forall P Q R : Prop,
P /\ (Q /\ R) -> (P /\ Q) /\ R.
Proof.
intros P Q R H.
inversion H as [HP [HQ HR]].
split.
split.
apply HP.
apply HQ.
apply HR.
Qed.
(* ###################################################### *)
(** * Iff *)
(** The handy "if and only if" connective is just the conjunction of
two implications. *)
Definition iff (P Q : Prop) := (P -> Q) /\ (Q -> P).
Notation "P <-> Q" := (iff P Q)
(at level 95, no associativity)
: type_scope.
Theorem iff_implies : forall P Q : Prop,
(P <-> Q) -> P -> Q.
Proof.
intros P Q H.
inversion H as [HAB HBA]. apply HAB. Qed.
Theorem iff_sym : forall P Q : Prop,
(P <-> Q) -> (Q <-> P).
Proof.
(* WORKED IN CLASS *)
intros P Q H.
inversion H as [HAB HBA].
split.
Case "->". apply HBA.
Case "<-". apply HAB. Qed.
(** **** Exercise: 1 star, optional (iff_properties) *)
(** Using the above proof that [<->] is symmetric ([iff_sym]) as
a guide, prove that it is also reflexive and transitive. *)
Theorem iff_refl : forall P : Prop,
P <-> P.
Proof.
intros P.
split.
intros H.
apply H.
intros H.
apply H.
Qed.
Theorem iff_trans : forall P Q R : Prop,
(P <-> Q) -> (Q <-> R) -> (P <-> R).
Proof.
intros P Q R.
split.
inversion H.
inversion H0.
intros T.
apply H3.
apply H1.
apply T.
inversion H.
inversion H0.
intros T.
apply H2.
apply H4.
apply T.
Qed.
(** Hint: If you have an iff hypothesis in the context, you can use
[inversion] to break it into two separate implications. (Think
about why this works.) *)
(** [] *)
(** Some of Coq's tactics treat [iff] statements specially, thus
avoiding the need for some low-level manipulation when reasoning
with them. In particular, [rewrite] can be used with [iff]
statements, not just equalities. *)
(* ############################################################ *)
(** * Disjunction (Logical "or") *)
(** ** Implementing Disjunction *)
(** Disjunction ("logical or") can also be defined as an
inductive proposition. *)
Inductive or (P Q : Prop) : Prop :=
| or_introl : P -> or P Q
| or_intror : Q -> or P Q.
Notation "P \/ Q" := (or P Q) : type_scope.
(** Consider the "type" of the constructor [or_introl]: *)
Check or_introl.
(* ===> forall P Q : Prop, P -> P \/ Q *)
(** It takes 3 inputs, namely the propositions [P], [Q] and
evidence of [P], and returns, as output, the evidence of [P \/ Q].
Next, look at the type of [or_intror]: *)
Check or_intror.
(* ===> forall P Q : Prop, Q -> P \/ Q *)
(** It is like [or_introl] but it requires evidence of [Q]
instead of evidence of [P]. *)
(** Intuitively, there are two ways of giving evidence for [P \/ Q]:
- give evidence for [P] (and say that it is [P] you are giving
evidence for -- this is the function of the [or_introl]
constructor), or
- give evidence for [Q], tagged with the [or_intror]
constructor. *)
(** *** *)
(** Since [P \/ Q] has two constructors, doing [inversion] on a
hypothesis of type [P \/ Q] yields two subgoals. *)
Theorem or_commut : forall P Q : Prop,
P \/ Q -> Q \/ P.
Proof.
intros P Q H.
inversion H as [HP | HQ].
Case "left". apply or_intror. apply HP.
Case "right". apply or_introl. apply HQ. Qed.
(** From here on, we'll use the shorthand tactics [left] and [right]
in place of [apply or_introl] and [apply or_intror]. *)
Theorem or_commut' : forall P Q : Prop,
P \/ Q -> Q \/ P.
Proof.
intros P Q H.
inversion H as [HP | HQ].
Case "left". right. apply HP.
Case "right". left. apply HQ. Qed.
Theorem or_distributes_over_and_1 : forall P Q R : Prop,
P \/ (Q /\ R) -> (P \/ Q) /\ (P \/ R).
Proof.
intros P Q R. intros H. inversion H as [HP | [HQ HR]].
Case "left". split.
SCase "left". left. apply HP.
SCase "right". left. apply HP.
Case "right". split.
SCase "left". right. apply HQ.
SCase "right". right. apply HR. Qed.
(** **** Exercise: 2 stars (or_distributes_over_and_2) *)
Theorem or_distributes_over_and_2 : forall P Q R : Prop,
(P \/ Q) /\ (P \/ R) -> P \/ (Q /\ R).
Proof.
intros P Q R.
intros H.
inversion H as [HPQ HPR].
inversion HPQ.
Case "HPQ : P".
left.
apply H0.
Case "HPQ : Q".
inversion HPR.
SCase "HPR : P".
left.
apply H1.
SCase "HPR : R".
right.
split.
apply H0.
apply H1.
Qed.
(** **** Exercise: 1 star, optional (or_distributes_over_and) *)
Theorem or_distributes_over_and : forall P Q R : Prop,
P \/ (Q /\ R) <-> (P \/ Q) /\ (P \/ R).
Proof.
intros P Q R.
split.
intros HPQR.
apply or_distributes_over_and_1 in HPQR.
apply HPQR.
intros HPQPR.
apply or_distributes_over_and_2 in HPQPR.
apply HPQPR.
Qed.
(* ################################################### *)
(** ** Relating [/\] and [\/] with [andb] and [orb] (advanced) *)
(** We've already seen several places where analogous structures
can be found in Coq's computational ([Type]) and logical ([Prop])
worlds. Here is one more: the boolean operators [andb] and [orb]
are clearly analogs of the logical connectives [/\] and [\/].
This analogy can be made more precise by the following theorems,
which show how to translate knowledge about [andb] and [orb]'s
behaviors on certain inputs into propositional facts about those
inputs. *)
Theorem andb_prop : forall b c,
andb b c = true -> b = true /\ c = true.
Proof.
(* WORKED IN CLASS *)
intros b c H.
destruct b.
Case "b = true". destruct c.
SCase "c = true". apply conj. reflexivity. reflexivity.
SCase "c = false". inversion H.
Case "b = false". inversion H. Qed.
Theorem andb_true_intro : forall b c,
b = true /\ c = true -> andb b c = true.
Proof.
(* WORKED IN CLASS *)
intros b c H.
inversion H.
rewrite H0. rewrite H1. reflexivity. Qed.
(** **** Exercise: 2 stars, optional (bool_prop) *)
Theorem andb_false : forall b c,
andb b c = false -> b = false \/ c = false.
Proof.
intros b c H.
destruct b eqn : Tb.
destruct c eqn : Tc.
inversion H.
right. reflexivity.
left. reflexivity.
Qed.
Theorem orb_prop : forall b c,
orb b c = true -> b = true \/ c = true.
Proof.
intros b c H.
destruct b eqn : Tb.
left. reflexivity.
right.
destruct c eqn : Tc.
reflexivity.
inversion H.
Qed.
Theorem orb_false_elim : forall b c,
orb b c = false -> b = false /\ c = false.
Proof.
intros b c H.
destruct b eqn : Tb.
inversion H.
destruct c eqn : Tc.
inversion H.
split. reflexivity. reflexivity.
Qed.
(* ################################################### *)
(** * Falsehood *)
(** Logical falsehood can be represented in Coq as an inductively
defined proposition with no constructors. *)
Inductive False : Prop := .
(** Intuition: [False] is a proposition for which there is no way
to give evidence. *)
(** Since [False] has no constructors, inverting an assumption
of type [False] always yields zero subgoals, allowing us to
immediately prove any goal. *)
Theorem False_implies_nonsense :
False -> 2 + 2 = 5.
Proof.
intros contra.
inversion contra. Qed.
(** How does this work? The [inversion] tactic breaks [contra] into
each of its possible cases, and yields a subgoal for each case.
As [contra] is evidence for [False], it has _no_ possible cases,
hence, there are no possible subgoals and the proof is done. *)
(** *** *)
(** Conversely, the only way to prove [False] is if there is already
something nonsensical or contradictory in the context: *)
Theorem nonsense_implies_False :
2 + 2 = 5 -> False.
Proof.
intros contra.
inversion contra. Qed.
(** Actually, since the proof of [False_implies_nonsense]
doesn't actually have anything to do with the specific nonsensical
thing being proved; it can easily be generalized to work for an
arbitrary [P]: *)
Theorem ex_falso_quodlibet : forall (P:Prop),
False -> P.
Proof.
(* WORKED IN CLASS *)
intros P contra.
inversion contra. Qed.
(** The Latin _ex falso quodlibet_ means, literally, "from
falsehood follows whatever you please." This theorem is also
known as the _principle of explosion_. *)
(* #################################################### *)
(** ** Truth *)
(** Since we have defined falsehood in Coq, one might wonder whether
it is possible to define truth in the same way. We can. *)
(** **** Exercise: 2 stars, advanced (True) *)
(** Define [True] as another inductively defined proposition. (The
intution is that [True] should be a proposition for which it is
trivial to give evidence.) *)
Inductive True : Prop := always_works.
(** However, unlike [False], which we'll use extensively, [True] is
used fairly rarely. By itself, it is trivial (and therefore
uninteresting) to prove as a goal, and it carries no useful
information as a hypothesis. But it can be useful when defining
complex [Prop]s using conditionals, or as a parameter to
higher-order [Prop]s. *)
(* #################################################### *)
(** * Negation *)
(** The logical complement of a proposition [P] is written [not
P] or, for shorthand, [~P]: *)
Definition not (P:Prop) := P -> False.
(** The intuition is that, if [P] is not true, then anything at
all (even [False]) follows from assuming [P]. *)
Notation "~ x" := (not x) : type_scope.
Check not.
(* ===> Prop -> Prop *)
(** It takes a little practice to get used to working with
negation in Coq. Even though you can see perfectly well why
something is true, it can be a little hard at first to get things
into the right configuration so that Coq can see it! Here are
proofs of a few familiar facts about negation to get you warmed
up. *)
Theorem not_False :
~ False.
Proof.
unfold not. intros H. inversion H. Qed.
(** *** *)
Theorem contradiction_implies_anything : forall P Q : Prop,
(P /\ ~P) -> Q.
Proof.
(* WORKED IN CLASS *)
intros P Q H. inversion H as [HP HNA]. unfold not in HNA.
apply HNA in HP. inversion HP. Qed.
Theorem double_neg : forall P : Prop,
P -> ~~P.
Proof.
(* WORKED IN CLASS *)
intros P H. unfold not. intros G. apply G. apply H. Qed.
(** **** Exercise: 2 stars, advanced (double_neg_inf) *)
(** Write an informal proof of [double_neg]:
_Theorem_: [P] implies [~~P], for any proposition [P].
_Proof_:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 2 stars (contrapositive) *)
Theorem contrapositive : forall P Q : Prop,
(P -> Q) -> (~Q -> ~P).
Proof.
intros P Q.
intros H.
unfold not.
intros H' H''.
apply H' in H.
inversion H.
apply H''.
Qed.
(** **** Exercise: 1 star (not_both_true_and_false) *)
Theorem not_both_true_and_false : forall P : Prop,
~ (P /\ ~P).
Proof.
intros P.
unfold not.
intros H.
inversion H.
apply H1 in H0.
inversion H0.
Qed.
(** **** Exercise: 1 star, advanced (informal_not_PNP) *)
(** Write an informal proof (in English) of the proposition [forall P
: Prop, ~(P /\ ~P)]. *)
(* FILL IN HERE *)
(** [] *)
(** *** Constructive logic *)
(** Note that some theorems that are true in classical logic are _not_
provable in Coq's (constructive) logic. E.g., let's look at how
this proof gets stuck... *)
Theorem classic_double_neg : forall P : Prop,
~~P -> P.
Proof.
(* WORKED IN CLASS *)
intros P H. unfold not in H.
(* But now what? There is no way to "invent" evidence for [~P]
from evidence for [P]. *)
Abort.
(** **** Exercise: 5 stars, advanced, optional (classical_axioms) *)
(** For those who like a challenge, here is an exercise
taken from the Coq'Art book (p. 123). The following five
statements are often considered as characterizations of
classical logic (as opposed to constructive logic, which is
what is "built in" to Coq). We can't prove them in Coq, but
we can consistently add any one of them as an unproven axiom
if we wish to work in classical logic. Prove that these five
propositions are equivalent. *)
Definition peirce := forall P Q: Prop,
((P->Q)->P)->P.
Definition classic := forall P:Prop,
~~P -> P.
Definition excluded_middle := forall P:Prop,
P \/ ~P.
Definition de_morgan_not_and_not := forall P Q:Prop,
~(~P /\ ~Q) -> P\/Q.
Definition implies_to_or := forall P Q:Prop,
(P->Q) -> (~P\/Q).
Theorem peirce_implies_classic_mimic :
peirce -> classic.
Proof.
unfold peirce.
unfold classic.
intros H P G.
unfold not in G.
(**
apply (H P False).
intros T.
destruct G as [].
unfold not.
apply T.
**)
apply H with (Q:=False).
intros T.
apply ex_falso_quodlibet.
apply G.
apply T.
Qed.
(** https://github.com/etosch/software_foundations/commit/318b4ee046dc649a9c711dbc4f3b00a00f42d0f9 **)
Theorem classic_implies_excluded_middle_mimic :
classic -> excluded_middle.
Proof.
unfold classic.
unfold excluded_middle.
intros classic.
intros P.
unfold not.
apply classic.
unfold not.
intros H.
apply H.
right.
intros H'.
apply H.
left.
apply H'.
Qed.
(**
https://github.com/suharahiromichi/coq/blob/master/sf/coq_sf_logic_classic.v
**)
(** right ---> apply orintror **)
(** split ---> destruct **)
Theorem excluded_middle_implies_de_morgan_not_and_not_mimic :
excluded_middle -> de_morgan_not_and_not.
Proof.
intros H0 P Q H1.
unfold excluded_middle in H0.
unfold not in H0.
unfold not in H1.
destruct (H0 P) as [A|B].
left. apply A.
right.
destruct (H0 Q) as [A'|B'].
apply A'.
destruct H1.
split.
apply B. apply B'.
Qed.
Theorem de_morgan_not_and_not_implies_implies_to_or :
de_morgan_not_and_not -> implies_to_or.
Proof.
unfold de_morgan_not_and_not.
intros H.
unfold implies_to_or.
intros P Q G.
apply H.
intros T.
unfold not in T.
destruct T as [].
apply H0.
intros U.
apply H1.
apply G.
apply U.
Qed.
Theorem implies_to_or_implies_peirce :
implies_to_or -> peirce.
Proof.
intros H1.
intros P Q H2.
unfold implies_to_or in H1.
assert(H3 : (~~P) \/ P).
apply (H1 (~P) P).
intros H3.
apply H2.
intros H4.
assert(H5 : P /\ ~P -> False).
apply not_both_true_and_false.
destruct H5.
split.
apply H4.
apply H3.
destruct H3 as [H3A|H3B].
assert (no_mid : ~P \/ P).
apply H1. intros H4. apply H4.
destruct no_mid as [no_midA|no_midB].
assert (H4 : (~P) /\ (~~P) -> False).
apply not_both_true_and_false.
destruct H4.
split.
apply no_midA.
apply H3A.
apply no_midB.
apply H3B.
Qed.
Theorem peirce_implies_classic :
peirce -> classic.
Proof.
unfold peirce.
unfold classic.
intros H1 P H2.
apply H1 with (Q:=P).
intros H3.
apply H1 with (Q:=False).
intros H4.
apply H1 with (Q:=(~P)).
intros H5.
unfold not in H5.
assert (H6 : ((False -> P) -> False) -> False).
apply (H1 False P).
destruct H6.
apply ex_falso_quodlibet.
assert (H7 : ((False -> ~P) -> False) -> False).
apply (H1 False (~P)).
apply H7.
intros H6.
assert (H8 : ((P -> False) -> P) -> P).
apply H1.
unfold not in H2.
destruct H2.
apply H4.
Qed.
Theorem classic_implies_excluded_middle :
classic -> excluded_middle.
Proof.
intros H1.
unfold classic in H1.
intros P.
unfold not.
apply H1.
unfold not.
intros H2.
apply H1.
unfold not.
intros H3.
apply H1.
unfold not.
unfold not in H1.
apply H1.
intros H4.
apply H2.
right.
intros H5.
apply H2.
left.
apply H5.
Qed.
Theorem excluded_middle_implies_de_morgan_not_and_not :
excluded_middle -> de_morgan_not_and_not.
Proof.
unfold excluded_middle.
unfold de_morgan_not_and_not.
intros H1.
intros P Q H2.
unfold not in H2.
unfold not in H1.
assert(H3 : P \/ (P -> False)). apply H1.
assert(H4 : Q \/ (Q -> False)). apply H1.
destruct H3 as [H3A|H3B].
left.
apply H3A.
destruct H4 as [H4A|H4B].
right.
apply H4A.
assert(H5 : False).
apply H2.
split.
apply H3B.
apply H4B.
inversion H5.
Qed.
(** practice **)
Theorem classic_implies_de_morgan_not_and_not :
classic -> de_morgan_not_and_not.
Proof.
unfold classic.
unfold de_morgan_not_and_not.
unfold not.
intros H1.
intros P Q H2.
apply H1.
intros H3.
apply H3.
assert(H4 : ((P -> False) -> False) -> P). apply H1.
left.
apply H4.
intros H5.
apply H3.
right.
assert(H6 : ((Q -> False) -> False) -> Q). apply H1.
apply H6.
intros H7.
apply H2.
split.
apply H5.
apply H7.
Qed.
(** This theorem implies that it is always safe to add a decidability
axiom (i.e. an instance of excluded middle) for any _particular_ Prop [P].
Why? Because we cannot prove the negation of such an axiom; if we could,
we would have both [~ (P \/ ~P)] and [~ ~ (P \/ ~P)], a contradiction. *)
Theorem excluded_middle_irrefutable: forall (P:Prop), ~ ~ (P \/ ~ P).
Proof.
intros P.
unfold not.
intros H.
apply H.
right.
intros T.
apply H.
left.
apply T.
Qed.
(* ########################################################## *)
(** ** Inequality *)
(** Saying [x <> y] is just the same as saying [~(x = y)]. *)
Notation "x <> y" := (~ (x = y)) : type_scope.
(** Since inequality involves a negation, it again requires
a little practice to be able to work with it fluently. Here
is one very useful trick. If you are trying to prove a goal
that is nonsensical (e.g., the goal state is [false = true]),
apply the lemma [ex_falso_quodlibet] to change the goal to
[False]. This makes it easier to use assumptions of the form
[~P] that are available in the context -- in particular,
assumptions of the form [x<>y]. *)
Theorem not_false_then_true : forall b : bool,
b <> false -> b = true.
Proof.
intros b H. destruct b.
Case "b = true". reflexivity.
Case "b = false".
unfold not in H.
apply ex_falso_quodlibet.
apply H. reflexivity. Qed.
(** *** *)
(** *** *)
(** *** *)
(** *** *)
(** *** *)
(** **** Exercise: 2 stars (false_beq_nat) *)
Theorem false_beq_nat : forall n m : nat,
n <> m ->
beq_nat n m = false.
Proof.
intros n m.
intros H.
unfold not in H.
destruct (beq_nat n m) eqn : G.
apply ex_falso_quodlibet.
apply H.
apply beq_nat_true.
apply G.
reflexivity.
Qed.
(** apply ex_falso_quodlibet with (P:=(n=m)) in H. **)
(** **** Exercise: 2 stars, optional (beq_nat_false) *)
Theorem beq_nat_false : forall n m,
beq_nat n m = false -> n <> m.
Proof.
intros n.
induction n as [|n'].
intros m e.
unfold not.
intros e2.
rewrite <- e2 in e.
inversion e.
intros m e.
unfold not.
intros e2.
rewrite <- e2 in e.
rewrite <- beq_nat_refl in e.
inversion e.
Qed.
(* $Date: 2014-06-05 07:22:21 -0400 (Thu, 05 Jun 2014) $ *) |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Wed Mar 01 09:52:03 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_util_vector_logic_1_0/system_util_vector_logic_1_0_sim_netlist.v
// Design : system_util_vector_logic_1_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_util_vector_logic_1_0,util_vector_logic,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "util_vector_logic,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_util_vector_logic_1_0
(Op1,
Op2,
Res);
input [0:0]Op1;
input [0:0]Op2;
output [0:0]Res;
wire [0:0]Op1;
wire [0:0]Op2;
wire [0:0]Res;
LUT2 #(
.INIT(4'hE))
\Res[0]_INST_0
(.I0(Op1),
.I1(Op2),
.O(Res));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: two_new2.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module two_new2 (
address,
clock,
q);
input [9:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../newnums2/two_new2.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 10,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../newnums2/two_new2.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../newnums2/two_new2.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL two_new2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL two_new2.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL two_new2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL two_new2.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL two_new2_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL two_new2_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: driver_7segment.v
//
// *Module Description:
// Driver for the four-digit, seven-segment LED display.
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
module driver_7segment (
// OUTPUTs
per_dout, // Peripheral data output
seg_a, // Segment A control
seg_b, // Segment B control
seg_c, // Segment C control
seg_d, // Segment D control
seg_e, // Segment E control
seg_f, // Segment F control
seg_g, // Segment G control
seg_dp, // Segment DP control
seg_an0, // Anode 0 control
seg_an1, // Anode 1 control
seg_an2, // Anode 2 control
seg_an3, // Anode 3 control
// INPUTs
mclk, // Main system clock
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_we, // Peripheral write enable (high active)
puc_rst // Main system reset
);
// OUTPUTs
//=========
output [15:0] per_dout; // Peripheral data output
output seg_a; // Segment A control
output seg_b; // Segment B control
output seg_c; // Segment C control
output seg_d; // Segment D control
output seg_e; // Segment E control
output seg_f; // Segment F control
output seg_g; // Segment G control
output seg_dp; // Segment DP control
output seg_an0; // Anode 0 control
output seg_an1; // Anode 1 control
output seg_an2; // Anode 2 control
output seg_an3; // Anode 3 control
// INPUTs
//=========
input mclk; // Main system clock
input [13:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_we; // Peripheral write enable (high active)
input puc_rst; // Main system reset
//=============================================================================
// 1) PARAMETER DECLARATION
//=============================================================================
// Register base address (must be aligned to decoder bit width)
parameter [14:0] BASE_ADDR = 15'h0090;
// Decoder bit width (defines how many bits are considered for address decoding)
parameter DEC_WD = 2;
// Register addresses offset
parameter [DEC_WD-1:0] DIGIT0 = 'h0,
DIGIT1 = 'h1,
DIGIT2 = 'h2,
DIGIT3 = 'h3;
// Register one-hot decoder utilities
parameter DEC_SZ = 2**DEC_WD;
parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1};
// Register one-hot decoder
parameter [DEC_SZ-1:0] DIGIT0_D = (BASE_REG << DIGIT0),
DIGIT1_D = (BASE_REG << DIGIT1),
DIGIT2_D = (BASE_REG << DIGIT2),
DIGIT3_D = (BASE_REG << DIGIT3);
//============================================================================
// 2) REGISTER DECODER
//============================================================================
// Local register selection
wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
// Register local address
wire [DEC_WD-1:0] reg_addr = {1'b0, per_addr[DEC_WD-2:0]};
// Register address decode
wire [DEC_SZ-1:0] reg_dec = (DIGIT0_D & {DEC_SZ{(reg_addr==(DIGIT0 >>1))}}) |
(DIGIT1_D & {DEC_SZ{(reg_addr==(DIGIT1 >>1))}}) |
(DIGIT2_D & {DEC_SZ{(reg_addr==(DIGIT2 >>1))}}) |
(DIGIT3_D & {DEC_SZ{(reg_addr==(DIGIT3 >>1))}});
// Read/Write probes
wire reg_lo_write = per_we[0] & reg_sel;
wire reg_hi_write = per_we[1] & reg_sel;
wire reg_read = ~|per_we & reg_sel;
// Read/Write vectors
wire [DEC_SZ-1:0] reg_hi_wr = reg_dec & {DEC_SZ{reg_hi_write}};
wire [DEC_SZ-1:0] reg_lo_wr = reg_dec & {DEC_SZ{reg_lo_write}};
wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}};
//============================================================================
// 3) REGISTERS
//============================================================================
// DIGIT0 Register
//-----------------
reg [7:0] digit0;
wire digit0_wr = DIGIT0[0] ? reg_hi_wr[DIGIT0] : reg_lo_wr[DIGIT0];
wire [7:0] digit0_nxt = DIGIT0[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) digit0 <= 8'h00;
else if (digit0_wr) digit0 <= digit0_nxt;
// DIGIT1 Register
//-----------------
reg [7:0] digit1;
wire digit1_wr = DIGIT1[0] ? reg_hi_wr[DIGIT1] : reg_lo_wr[DIGIT1];
wire [7:0] digit1_nxt = DIGIT1[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) digit1 <= 8'h00;
else if (digit1_wr) digit1 <= digit1_nxt;
// DIGIT2 Register
//-----------------
reg [7:0] digit2;
wire digit2_wr = DIGIT2[0] ? reg_hi_wr[DIGIT2] : reg_lo_wr[DIGIT2];
wire [7:0] digit2_nxt = DIGIT2[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) digit2 <= 8'h00;
else if (digit2_wr) digit2 <= digit2_nxt;
// DIGIT3 Register
//-----------------
reg [7:0] digit3;
wire digit3_wr = DIGIT3[0] ? reg_hi_wr[DIGIT3] : reg_lo_wr[DIGIT3];
wire [7:0] digit3_nxt = DIGIT3[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) digit3 <= 8'h00;
else if (digit3_wr) digit3 <= digit3_nxt;
//============================================================================
// 4) DATA OUTPUT GENERATION
//============================================================================
// Data output mux
wire [15:0] digit0_rd = (digit0 & {8{reg_rd[DIGIT0]}}) << (8 & {4{DIGIT0[0]}});
wire [15:0] digit1_rd = (digit1 & {8{reg_rd[DIGIT1]}}) << (8 & {4{DIGIT1[0]}});
wire [15:0] digit2_rd = (digit2 & {8{reg_rd[DIGIT2]}}) << (8 & {4{DIGIT2[0]}});
wire [15:0] digit3_rd = (digit3 & {8{reg_rd[DIGIT3]}}) << (8 & {4{DIGIT3[0]}});
wire [15:0] per_dout = digit0_rd |
digit1_rd |
digit2_rd |
digit3_rd;
//============================================================================
// 5) FOUR-DIGIT, SEVEN-SEGMENT LED DISPLAY DRIVER
//============================================================================
// Anode selection
//------------------
// Free running counter
reg [23:0] anode_cnt;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) anode_cnt <= 24'h00_0000;
else anode_cnt <= anode_cnt+24'h00_0001;
// Anode selection
wire [3:0] seg_an = (4'h1 << anode_cnt[17:16]);
wire seg_an0 = ~seg_an[0];
wire seg_an1 = ~seg_an[1];
wire seg_an2 = ~seg_an[2];
wire seg_an3 = ~seg_an[3];
// Segment selection
//----------------------------
wire [7:0] digit = seg_an[0] ? digit0 :
seg_an[1] ? digit1 :
seg_an[2] ? digit2 :
digit3;
wire seg_a = ~digit[7];
wire seg_b = ~digit[6];
wire seg_c = ~digit[5];
wire seg_d = ~digit[4];
wire seg_e = ~digit[3];
wire seg_f = ~digit[2];
wire seg_g = ~digit[1];
wire seg_dp = ~digit[0];
endmodule // driver_7segment
|
// soc_system_master_secure.v
// This file was auto-generated from altera_jtag_avalon_master_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 13.1 162 at 2014.01.24.12:33:12
`timescale 1 ps / 1 ps
module soc_system_master_secure #(
parameter USE_PLI = 0,
parameter PLI_PORT = 50000,
parameter FIFO_DEPTHS = 2
) (
input wire clk_clk, // clk.clk
input wire clk_reset_reset, // clk_reset.reset
output wire [31:0] master_address, // master.address
input wire [31:0] master_readdata, // .readdata
output wire master_read, // .read
output wire master_write, // .write
output wire [31:0] master_writedata, // .writedata
input wire master_waitrequest, // .waitrequest
input wire master_readdatavalid, // .readdatavalid
output wire [3:0] master_byteenable, // .byteenable
output wire master_reset_reset // master_reset.reset
);
wire jtag_phy_embedded_in_jtag_master_src_valid; // jtag_phy_embedded_in_jtag_master:source_valid -> timing_adt:in_valid
wire [7:0] jtag_phy_embedded_in_jtag_master_src_data; // jtag_phy_embedded_in_jtag_master:source_data -> timing_adt:in_data
wire timing_adt_out_valid; // timing_adt:out_valid -> fifo:in_valid
wire [7:0] timing_adt_out_data; // timing_adt:out_data -> fifo:in_data
wire timing_adt_out_ready; // fifo:in_ready -> timing_adt:out_ready
wire fifo_out_valid; // fifo:out_valid -> b2p:in_valid
wire [7:0] fifo_out_data; // fifo:out_data -> b2p:in_data
wire fifo_out_ready; // b2p:in_ready -> fifo:out_ready
wire b2p_out_packets_stream_endofpacket; // b2p:out_endofpacket -> b2p_adapter:in_endofpacket
wire b2p_out_packets_stream_valid; // b2p:out_valid -> b2p_adapter:in_valid
wire b2p_out_packets_stream_startofpacket; // b2p:out_startofpacket -> b2p_adapter:in_startofpacket
wire [7:0] b2p_out_packets_stream_data; // b2p:out_data -> b2p_adapter:in_data
wire b2p_out_packets_stream_ready; // b2p_adapter:in_ready -> b2p:out_ready
wire [7:0] b2p_out_packets_stream_channel; // b2p:out_channel -> b2p_adapter:in_channel
wire b2p_adapter_out_endofpacket; // b2p_adapter:out_endofpacket -> transacto:in_endofpacket
wire b2p_adapter_out_valid; // b2p_adapter:out_valid -> transacto:in_valid
wire b2p_adapter_out_startofpacket; // b2p_adapter:out_startofpacket -> transacto:in_startofpacket
wire [7:0] b2p_adapter_out_data; // b2p_adapter:out_data -> transacto:in_data
wire b2p_adapter_out_ready; // transacto:in_ready -> b2p_adapter:out_ready
wire transacto_out_stream_endofpacket; // transacto:out_endofpacket -> p2b_adapter:in_endofpacket
wire transacto_out_stream_valid; // transacto:out_valid -> p2b_adapter:in_valid
wire transacto_out_stream_startofpacket; // transacto:out_startofpacket -> p2b_adapter:in_startofpacket
wire [7:0] transacto_out_stream_data; // transacto:out_data -> p2b_adapter:in_data
wire transacto_out_stream_ready; // p2b_adapter:in_ready -> transacto:out_ready
wire p2b_adapter_out_endofpacket; // p2b_adapter:out_endofpacket -> p2b:in_endofpacket
wire p2b_adapter_out_valid; // p2b_adapter:out_valid -> p2b:in_valid
wire p2b_adapter_out_startofpacket; // p2b_adapter:out_startofpacket -> p2b:in_startofpacket
wire [7:0] p2b_adapter_out_data; // p2b_adapter:out_data -> p2b:in_data
wire [7:0] p2b_adapter_out_channel; // p2b_adapter:out_channel -> p2b:in_channel
wire p2b_adapter_out_ready; // p2b:in_ready -> p2b_adapter:out_ready
wire p2b_out_bytes_stream_valid; // p2b:out_valid -> jtag_phy_embedded_in_jtag_master:sink_valid
wire [7:0] p2b_out_bytes_stream_data; // p2b:out_data -> jtag_phy_embedded_in_jtag_master:sink_data
wire p2b_out_bytes_stream_ready; // jtag_phy_embedded_in_jtag_master:sink_ready -> p2b:out_ready
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [b2p:reset_n, b2p_adapter:reset_n, fifo:reset, jtag_phy_embedded_in_jtag_master:reset_n, p2b:reset_n, p2b_adapter:reset_n, timing_adt:reset_n, transacto:reset_n]
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (USE_PLI != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
use_pli_check ( .error(1'b1) );
end
if (PLI_PORT != 50000)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
pli_port_check ( .error(1'b1) );
end
if (FIFO_DEPTHS != 2)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
fifo_depths_check ( .error(1'b1) );
end
endgenerate
altera_avalon_st_jtag_interface #(
.PURPOSE (1),
.UPSTREAM_FIFO_SIZE (0),
.DOWNSTREAM_FIFO_SIZE (64),
.MGMT_CHANNEL_WIDTH (-1),
.USE_PLI (0),
.PLI_PORT (50000)
) jtag_phy_embedded_in_jtag_master (
.clk (clk_clk), // clock.clk
.reset_n (~rst_controller_reset_out_reset), // clock_reset.reset_n
.source_data (jtag_phy_embedded_in_jtag_master_src_data), // src.data
.source_valid (jtag_phy_embedded_in_jtag_master_src_valid), // .valid
.sink_data (p2b_out_bytes_stream_data), // sink.data
.sink_valid (p2b_out_bytes_stream_valid), // .valid
.sink_ready (p2b_out_bytes_stream_ready), // .ready
.resetrequest (master_reset_reset) // resetrequest.reset
);
soc_system_master_secure_timing_adt timing_adt (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.in_valid (jtag_phy_embedded_in_jtag_master_src_valid), // in.valid
.in_data (jtag_phy_embedded_in_jtag_master_src_data), // .data
.out_valid (timing_adt_out_valid), // out.valid
.out_data (timing_adt_out_data), // .data
.out_ready (timing_adt_out_ready) // .ready
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (8),
.FIFO_DEPTH (64),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (3),
.USE_MEMORY_BLOCKS (1),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) fifo (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (timing_adt_out_data), // in.data
.in_valid (timing_adt_out_valid), // .valid
.in_ready (timing_adt_out_ready), // .ready
.out_data (fifo_out_data), // out.data
.out_valid (fifo_out_valid), // .valid
.out_ready (fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_st_bytes_to_packets #(
.CHANNEL_WIDTH (8),
.ENCODING (0)
) b2p (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
.out_channel (b2p_out_packets_stream_channel), // out_packets_stream.channel
.out_ready (b2p_out_packets_stream_ready), // .ready
.out_valid (b2p_out_packets_stream_valid), // .valid
.out_data (b2p_out_packets_stream_data), // .data
.out_startofpacket (b2p_out_packets_stream_startofpacket), // .startofpacket
.out_endofpacket (b2p_out_packets_stream_endofpacket), // .endofpacket
.in_ready (fifo_out_ready), // in_bytes_stream.ready
.in_valid (fifo_out_valid), // .valid
.in_data (fifo_out_data) // .data
);
altera_avalon_st_packets_to_bytes #(
.CHANNEL_WIDTH (8),
.ENCODING (0)
) p2b (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
.in_ready (p2b_adapter_out_ready), // in_packets_stream.ready
.in_valid (p2b_adapter_out_valid), // .valid
.in_data (p2b_adapter_out_data), // .data
.in_channel (p2b_adapter_out_channel), // .channel
.in_startofpacket (p2b_adapter_out_startofpacket), // .startofpacket
.in_endofpacket (p2b_adapter_out_endofpacket), // .endofpacket
.out_ready (p2b_out_bytes_stream_ready), // out_bytes_stream.ready
.out_valid (p2b_out_bytes_stream_valid), // .valid
.out_data (p2b_out_bytes_stream_data) // .data
);
altera_avalon_packets_to_master #(
.FAST_VER (0),
.FIFO_DEPTHS (2),
.FIFO_WIDTHU (1)
) transacto (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // clk_reset.reset_n
.out_ready (transacto_out_stream_ready), // out_stream.ready
.out_valid (transacto_out_stream_valid), // .valid
.out_data (transacto_out_stream_data), // .data
.out_startofpacket (transacto_out_stream_startofpacket), // .startofpacket
.out_endofpacket (transacto_out_stream_endofpacket), // .endofpacket
.in_ready (b2p_adapter_out_ready), // in_stream.ready
.in_valid (b2p_adapter_out_valid), // .valid
.in_data (b2p_adapter_out_data), // .data
.in_startofpacket (b2p_adapter_out_startofpacket), // .startofpacket
.in_endofpacket (b2p_adapter_out_endofpacket), // .endofpacket
.address (master_address), // avalon_master.address
.readdata (master_readdata), // .readdata
.read (master_read), // .read
.write (master_write), // .write
.writedata (master_writedata), // .writedata
.waitrequest (master_waitrequest), // .waitrequest
.readdatavalid (master_readdatavalid), // .readdatavalid
.byteenable (master_byteenable) // .byteenable
);
soc_system_master_secure_b2p_adapter b2p_adapter (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.in_ready (b2p_out_packets_stream_ready), // in.ready
.in_valid (b2p_out_packets_stream_valid), // .valid
.in_data (b2p_out_packets_stream_data), // .data
.in_channel (b2p_out_packets_stream_channel), // .channel
.in_startofpacket (b2p_out_packets_stream_startofpacket), // .startofpacket
.in_endofpacket (b2p_out_packets_stream_endofpacket), // .endofpacket
.out_ready (b2p_adapter_out_ready), // out.ready
.out_valid (b2p_adapter_out_valid), // .valid
.out_data (b2p_adapter_out_data), // .data
.out_startofpacket (b2p_adapter_out_startofpacket), // .startofpacket
.out_endofpacket (b2p_adapter_out_endofpacket) // .endofpacket
);
soc_system_master_secure_p2b_adapter p2b_adapter (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.in_ready (transacto_out_stream_ready), // in.ready
.in_valid (transacto_out_stream_valid), // .valid
.in_data (transacto_out_stream_data), // .data
.in_startofpacket (transacto_out_stream_startofpacket), // .startofpacket
.in_endofpacket (transacto_out_stream_endofpacket), // .endofpacket
.out_ready (p2b_adapter_out_ready), // out.ready
.out_valid (p2b_adapter_out_valid), // .valid
.out_data (p2b_adapter_out_data), // .data
.out_startofpacket (p2b_adapter_out_startofpacket), // .startofpacket
.out_endofpacket (p2b_adapter_out_endofpacket), // .endofpacket
.out_channel (p2b_adapter_out_channel) // .channel
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (clk_reset_reset), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_3_pipe_sync.v
// Version : 1.3
//------------------------------------------------------------------------------
// Filename : pipe_sync.v
// Description : PIPE Sync Module for 7 Series Transceiver
// Version : 11.1
//------------------------------------------------------------------------------
// PCIE_TXSYNC_MODE : 0 = Manual TX sync (default).
// : 1 = Auto TX sync.
// PCIE_RXSYNC_MODE : 0 = Manual RX sync (default).
// : 1 = Auto RX sync.
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE Sync Module --------------------------------------------------
module pcie_7x_v1_3_pipe_sync #
(
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
parameter PCIE_RXBUF_EN = "TRUE", // PCIe TX buffer enable for Gen3 only
parameter PCIE_TXSYNC_MODE = 0, // PCIe TX sync mode
parameter PCIE_RXSYNC_MODE = 0, // PCIe RX sync mode
parameter PCIE_LANE = 1, // PCIe lane
parameter PCIE_LINK_SPEED = 3, // PCIe link speed
parameter BYPASS_TXDELAY_ALIGN = 0, // Bypass TX delay align
parameter BYPASS_RXDELAY_ALIGN = 0 // Bypass RX delay align
)
(
//---------- Input -------------------------------------
input SYNC_CLK,
input SYNC_RST_N,
input SYNC_SLAVE,
input SYNC_GEN3,
input SYNC_RATE_IDLE,
input SYNC_MMCM_LOCK,
input SYNC_RXELECIDLE,
input SYNC_RXCDRLOCK,
input SYNC_TXSYNC_START,
input SYNC_TXPHINITDONE,
input SYNC_TXDLYSRESETDONE,
input SYNC_TXPHALIGNDONE,
input SYNC_TXSYNCDONE,
input SYNC_RXSYNC_START,
input SYNC_RXDLYSRESETDONE,
input SYNC_RXPHALIGNDONE_M,
input SYNC_RXPHALIGNDONE_S,
input SYNC_RXSYNC_DONEM_IN,
input SYNC_RXSYNCDONE,
//---------- Output ------------------------------------
output SYNC_TXPHDLYRESET,
output SYNC_TXPHALIGN,
output SYNC_TXPHALIGNEN,
output SYNC_TXPHINIT,
output SYNC_TXDLYBYPASS,
output SYNC_TXDLYSRESET,
output SYNC_TXDLYEN,
output SYNC_TXSYNC_DONE,
output [ 5:0] SYNC_FSM_TX,
output SYNC_RXPHALIGN,
output SYNC_RXPHALIGNEN,
output SYNC_RXDLYBYPASS,
output SYNC_RXDLYSRESET,
output SYNC_RXDLYEN,
output SYNC_RXDDIEN,
output SYNC_RXSYNC_DONEM_OUT,
output SYNC_RXSYNC_DONE,
output [ 6:0] SYNC_FSM_RX
);
//---------- Input Register ----------------------------
reg gen3_reg1;
reg rate_idle_reg1;
reg mmcm_lock_reg1;
reg rxelecidle_reg1;
reg rxcdrlock_reg1;
reg gen3_reg2;
reg rate_idle_reg2;
reg mmcm_lock_reg2;
reg rxelecidle_reg2;
reg rxcdrlock_reg2;
reg txsync_start_reg1;
reg txphinitdone_reg1;
reg txdlysresetdone_reg1;
reg txphaligndone_reg1;
reg txsyncdone_reg1;
reg txsync_start_reg2;
reg txphinitdone_reg2;
reg txdlysresetdone_reg2;
reg txphaligndone_reg2;
reg txsyncdone_reg2;
reg rxsync_start_reg1;
reg rxdlysresetdone_reg1;
reg rxphaligndone_m_reg1;
reg rxphaligndone_s_reg1;
reg rxsync_donem_reg1;
reg rxsyncdone_reg1;
reg rxsync_start_reg2;
reg rxdlysresetdone_reg2;
reg rxphaligndone_m_reg2;
reg rxphaligndone_s_reg2;
reg rxsync_donem_reg2;
reg rxsyncdone_reg2;
//---------- Output Register ---------------------------
reg txdlyen = 1'd0;
reg txsync_done = 1'd0;
reg [ 5:0] fsm_tx = 6'd0;
reg rxdlyen = 1'd0;
reg rxsync_done = 1'd0;
reg [ 6:0] fsm_rx = 7'd0;
//---------- FSM ---------------------------------------
localparam FSM_TXSYNC_IDLE = 6'b000001;
localparam FSM_MMCM_LOCK = 6'b000010;
localparam FSM_TXSYNC_START = 6'b000100;
localparam FSM_TXPHINITDONE = 6'b001000; // Manual TX sync only
localparam FSM_TXSYNC_DONE1 = 6'b010000;
localparam FSM_TXSYNC_DONE2 = 6'b100000;
localparam FSM_RXSYNC_IDLE = 7'b0000001;
localparam FSM_RXCDRLOCK = 7'b0000010;
localparam FSM_RXSYNC_START = 7'b0000100;
localparam FSM_RXSYNC_DONE1 = 7'b0001000;
localparam FSM_RXSYNC_DONE2 = 7'b0010000;
localparam FSM_RXSYNC_DONES = 7'b0100000;
localparam FSM_RXSYNC_DONEM = 7'b1000000;
//---------- Input FF ----------------------------------------------------------
always @ (posedge SYNC_CLK)
begin
if (!SYNC_RST_N)
begin
//---------- 1st Stage FF --------------------------
gen3_reg1 <= 1'd0;
rate_idle_reg1 <= 1'd0;
mmcm_lock_reg1 <= 1'd0;
rxelecidle_reg1 <= 1'd0;
rxcdrlock_reg1 <= 1'd0;
txsync_start_reg1 <= 1'd0;
txphinitdone_reg1 <= 1'd0;
txdlysresetdone_reg1 <= 1'd0;
txphaligndone_reg1 <= 1'd0;
txsyncdone_reg1 <= 1'd0;
rxsync_start_reg1 <= 1'd0;
rxdlysresetdone_reg1 <= 1'd0;
rxphaligndone_m_reg1 <= 1'd0;
rxphaligndone_s_reg1 <= 1'd0;
rxsync_donem_reg1 <= 1'd0;
rxsyncdone_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
gen3_reg2 <= 1'd0;
rate_idle_reg2 <= 1'd0;
mmcm_lock_reg2 <= 1'd0;
rxelecidle_reg2 <= 1'd0;
rxcdrlock_reg2 <= 1'd0;
txsync_start_reg2 <= 1'd0;
txphinitdone_reg2 <= 1'd0;
txdlysresetdone_reg2 <= 1'd0;
txphaligndone_reg2 <= 1'd0;
txsyncdone_reg2 <= 1'd0;
rxsync_start_reg2 <= 1'd0;
rxdlysresetdone_reg2 <= 1'd0;
rxphaligndone_m_reg2 <= 1'd0;
rxphaligndone_s_reg2 <= 1'd0;
rxsync_donem_reg2 <= 1'd0;
rxsyncdone_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
gen3_reg1 <= SYNC_GEN3;
rate_idle_reg1 <= SYNC_RATE_IDLE;
mmcm_lock_reg1 <= SYNC_MMCM_LOCK;
rxelecidle_reg1 <= SYNC_RXELECIDLE;
rxcdrlock_reg1 <= SYNC_RXCDRLOCK;
txsync_start_reg1 <= SYNC_TXSYNC_START;
txphinitdone_reg1 <= SYNC_TXPHINITDONE;
txdlysresetdone_reg1 <= SYNC_TXDLYSRESETDONE;
txphaligndone_reg1 <= SYNC_TXPHALIGNDONE;
txsyncdone_reg1 <= SYNC_TXSYNCDONE;
rxsync_start_reg1 <= SYNC_RXSYNC_START;
rxdlysresetdone_reg1 <= SYNC_RXDLYSRESETDONE;
rxphaligndone_m_reg1 <= SYNC_RXPHALIGNDONE_M;
rxphaligndone_s_reg1 <= SYNC_RXPHALIGNDONE_S;
rxsync_donem_reg1 <= SYNC_RXSYNC_DONEM_IN;
rxsyncdone_reg1 <= SYNC_RXSYNCDONE;
//---------- 2nd Stage FF --------------------------
gen3_reg2 <= gen3_reg1;
rate_idle_reg2 <= rate_idle_reg1;
mmcm_lock_reg2 <= mmcm_lock_reg1;
rxelecidle_reg2 <= rxelecidle_reg1;
rxcdrlock_reg2 <= rxcdrlock_reg1;
txsync_start_reg2 <= txsync_start_reg1;
txphinitdone_reg2 <= txphinitdone_reg1;
txdlysresetdone_reg2 <= txdlysresetdone_reg1;
txphaligndone_reg2 <= txphaligndone_reg1;
txsyncdone_reg2 <= txsyncdone_reg1;
rxsync_start_reg2 <= rxsync_start_reg1;
rxdlysresetdone_reg2 <= rxdlysresetdone_reg1;
rxphaligndone_m_reg2 <= rxphaligndone_m_reg1;
rxphaligndone_s_reg2 <= rxphaligndone_s_reg1;
rxsync_donem_reg2 <= rxsync_donem_reg1;
rxsyncdone_reg2 <= rxsyncdone_reg1;
end
end
//---------- Generate TX Sync FSM ----------------------------------------------
generate if ((PCIE_LINK_SPEED == 3) || (PCIE_TXBUF_EN == "FALSE"))
begin : txsync_fsm
//---------- PIPE TX Sync FSM ----------------------------------------------
always @ (posedge SYNC_CLK)
begin
if (!SYNC_RST_N)
begin
fsm_tx <= FSM_TXSYNC_IDLE;
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
else
begin
case (fsm_tx)
//---------- Idle State ------------------------
FSM_TXSYNC_IDLE :
begin
//---------- Exiting Reset or Rate Change --
if (txsync_start_reg2)
begin
fsm_tx <= FSM_MMCM_LOCK;
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
else
begin
fsm_tx <= FSM_TXSYNC_IDLE;
txdlyen <= txdlyen;
txsync_done <= txsync_done;
end
end
//---------- Check MMCM Lock -------------------
FSM_MMCM_LOCK :
begin
fsm_tx <= (mmcm_lock_reg2 ? FSM_TXSYNC_START : FSM_MMCM_LOCK);
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
//---------- TX Delay Soft Reset ---------------
FSM_TXSYNC_START :
begin
fsm_tx <= (((!txdlysresetdone_reg2 && txdlysresetdone_reg1) || ((PCIE_GT_DEVICE == "GTH") && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE)) ? FSM_TXPHINITDONE : FSM_TXSYNC_START);
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
//---------- Wait for TX Phase Init Done (Manual Mode Only)
FSM_TXPHINITDONE :
begin
fsm_tx <= (((!txphinitdone_reg2 && txphinitdone_reg1) || (PCIE_TXSYNC_MODE == 1)) ? FSM_TXSYNC_DONE1 : FSM_TXPHINITDONE);
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
//---------- Wait for TX Phase Alignment Done --
FSM_TXSYNC_DONE1 :
begin
if ((PCIE_GT_DEVICE == "GTH") && (PCIE_TXSYNC_MODE == 1) && !SYNC_SLAVE)
fsm_tx <= ((!txsyncdone_reg2 && txsyncdone_reg1) ? FSM_TXSYNC_DONE2 : FSM_TXSYNC_DONE1);
else
fsm_tx <= ((!txphaligndone_reg2 && txphaligndone_reg1) ? FSM_TXSYNC_DONE2 : FSM_TXSYNC_DONE1);
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
//---------- Wait for Master TX Delay Alignment Done
FSM_TXSYNC_DONE2 :
begin
if ((!txphaligndone_reg2 && txphaligndone_reg1) || SYNC_SLAVE || ((PCIE_GT_DEVICE == "GTH") && (PCIE_TXSYNC_MODE == 1)) || (BYPASS_TXDELAY_ALIGN == 1))
begin
fsm_tx <= FSM_TXSYNC_IDLE;
txdlyen <= !SYNC_SLAVE;
txsync_done <= 1'd1;
end
else
begin
fsm_tx <= FSM_TXSYNC_DONE2;
txdlyen <= !SYNC_SLAVE;
txsync_done <= 1'd0;
end
end
//---------- Default State ---------------------
default :
begin
fsm_tx <= FSM_TXSYNC_IDLE;
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
endcase
end
end
end
//---------- TX Sync FSM Default------------------------------------------------
else
begin : txsync_fsm_disable
//---------- Default -------------------------------------------------------
always @ (posedge SYNC_CLK)
begin
fsm_tx <= FSM_TXSYNC_IDLE;
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
end
endgenerate
//---------- Generate RX Sync FSM ----------------------------------------------
generate if ((PCIE_LINK_SPEED == 3) && (PCIE_RXBUF_EN == "FALSE"))
begin : rxsync_fsm
//---------- PIPE RX Sync FSM ----------------------------------------------
always @ (posedge SYNC_CLK)
begin
if (!SYNC_RST_N)
begin
fsm_rx <= FSM_RXSYNC_IDLE;
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
else
begin
case (fsm_rx)
//---------- Idle State ------------------------
FSM_RXSYNC_IDLE :
begin
//---------- Exiting Rate Change -----------
if (rxsync_start_reg2)
begin
fsm_rx <= FSM_RXCDRLOCK;
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
//---------- Exiting Electrical Idle without Rate Change
else if (gen3_reg2 && rate_idle_reg2 && ((rxelecidle_reg2 == 1'd1) && (rxelecidle_reg1 == 1'd0)))
begin
fsm_rx <= FSM_RXCDRLOCK;
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
//---------- Idle --------------------------
else
begin
fsm_rx <= FSM_RXSYNC_IDLE;
rxdlyen <= rxelecidle_reg2 ? 1'd0 : rxdlyen;
rxsync_done <= rxelecidle_reg2 ? 1'd0 : rxsync_done;
end
end
//---------- Wait for RX Electrical Idle Exit and RX CDR Lock
FSM_RXCDRLOCK :
begin
fsm_rx <= ((!rxelecidle_reg2 && rxcdrlock_reg2) ? FSM_RXSYNC_START : FSM_RXCDRLOCK);
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
//---------- Start RX Sync with RX Delay Soft Reset
FSM_RXSYNC_START :
begin
fsm_rx <= ((!rxdlysresetdone_reg2 && rxdlysresetdone_reg1) ? FSM_RXSYNC_DONE1 : FSM_RXSYNC_START);
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
//---------- Wait for RX Phase Alignment Done --
FSM_RXSYNC_DONE1 :
begin
if (SYNC_SLAVE)
begin
fsm_rx <= ((!rxphaligndone_s_reg2 && rxphaligndone_s_reg1) ? FSM_RXSYNC_DONE2 : FSM_RXSYNC_DONE1);
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
else
begin
fsm_rx <= ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) ? FSM_RXSYNC_DONE2 : FSM_RXSYNC_DONE1);
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
end
//---------- Wait for Master RX Delay Alignment Done
FSM_RXSYNC_DONE2 :
begin
if (SYNC_SLAVE)
begin
fsm_rx <= FSM_RXSYNC_IDLE;
rxdlyen <= 1'd0;
rxsync_done <= 1'd1;
end
else if ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) || (BYPASS_RXDELAY_ALIGN == 1))
begin
fsm_rx <= ((PCIE_LANE == 1) ? FSM_RXSYNC_IDLE : FSM_RXSYNC_DONES);
rxdlyen <= (PCIE_LANE == 1);
rxsync_done <= (PCIE_LANE == 1);
end
else
begin
fsm_rx <= FSM_RXSYNC_DONE2;
rxdlyen <= 1'd1;
rxsync_done <= 1'd0;
end
end
//---------- Wait for Slave RX Phase Alignment Done
FSM_RXSYNC_DONES :
begin
if (!rxphaligndone_s_reg2 && rxphaligndone_s_reg1)
begin
fsm_rx <= FSM_RXSYNC_DONEM;
rxdlyen <= 1'd1;
rxsync_done <= 1'd0;
end
else
begin
fsm_rx <= FSM_RXSYNC_DONES;
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
end
//---------- Wait for Master RX Delay Alignment Done
FSM_RXSYNC_DONEM :
begin
if ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) || (BYPASS_RXDELAY_ALIGN == 1))
begin
fsm_rx <= FSM_RXSYNC_IDLE;
rxdlyen <= 1'd1;
rxsync_done <= 1'd1;
end
else
begin
fsm_rx <= FSM_RXSYNC_DONEM;
rxdlyen <= 1'd1;
rxsync_done <= 1'd0;
end
end
//---------- Default State ---------------------
default :
begin
fsm_rx <= FSM_RXSYNC_IDLE;
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
endcase
end
end
end
//---------- RX Sync FSM Default -----------------------------------------------
else
begin : rxsync_fsm_disable
//---------- Default -------------------------------------------------------
always @ (posedge SYNC_CLK)
begin
fsm_rx <= FSM_RXSYNC_IDLE;
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
end
endgenerate
//---------- PIPE Sync Output --------------------------------------------------
assign SYNC_TXPHALIGNEN = ((PCIE_TXSYNC_MODE == 1) || (!gen3_reg2 && (PCIE_TXBUF_EN == "TRUE"))) ? 1'd0 : 1'd1;
assign SYNC_TXDLYBYPASS = 1'd0;
assign SYNC_TXDLYSRESET = !((PCIE_GT_DEVICE == "GTH") && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE) ? (fsm_tx == FSM_TXSYNC_START) : 1'd0;
assign SYNC_TXPHDLYRESET = ((PCIE_GT_DEVICE == "GTH") && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE) ? (fsm_tx == FSM_TXSYNC_START) : 1'd0;
assign SYNC_TXPHINIT = PCIE_TXSYNC_MODE ? 1'd0 : (fsm_tx == FSM_TXPHINITDONE);
assign SYNC_TXPHALIGN = PCIE_TXSYNC_MODE ? 1'd0 : (fsm_tx == FSM_TXSYNC_DONE1);
assign SYNC_TXDLYEN = PCIE_TXSYNC_MODE ? 1'd0 : txdlyen;
assign SYNC_TXSYNC_DONE = txsync_done;
assign SYNC_FSM_TX = fsm_tx;
assign SYNC_RXPHALIGNEN = ((PCIE_RXSYNC_MODE == 1) || (!gen3_reg2) || (PCIE_RXBUF_EN == "TRUE")) ? 1'd0 : 1'd1;
assign SYNC_RXDLYBYPASS = !gen3_reg2 || (PCIE_RXBUF_EN == "TRUE");
assign SYNC_RXDLYSRESET = (fsm_rx == FSM_RXSYNC_START);
assign SYNC_RXPHALIGN = PCIE_RXSYNC_MODE ? 1'd0 : (!SYNC_SLAVE ? (fsm_rx == FSM_RXSYNC_DONE1) : (rxsync_donem_reg2 && (fsm_rx == FSM_RXSYNC_DONE1)));
assign SYNC_RXDLYEN = PCIE_RXSYNC_MODE ? 1'd0 : rxdlyen;
assign SYNC_RXDDIEN = gen3_reg2 && (PCIE_RXBUF_EN == "FALSE");
assign SYNC_RXSYNC_DONE = rxsync_done;
assign SYNC_RXSYNC_DONEM_OUT = (fsm_rx == FSM_RXSYNC_DONES);
assign SYNC_FSM_RX = fsm_rx;
endmodule
|
`timescale 1ns / 1ps
// Documented Verilog UART
// Copyright (C) 2010 Timothy Goddard ([email protected])
// Distributed under the MIT licence.
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
module uart(
input clk_uart_x4, // The master clock for this module
input rst, // Synchronous reset.
input rx, // Incoming serial line
output tx, // Outgoing serial line
input transmit, // Signal to transmit
input [7:0] tx_byte, // Byte to transmit
output received, // Indicated that a byte has been received.
output [7:0] rx_byte, // Byte received
output is_receiving, // Low when receive line is idle.
output is_transmitting, // Low when transmit line is idle.
output recv_error // Indicates error in receiving packet.
);
wire clk;
assign clk = clk_uart_x4;
// States for the receiving state machine.
// These are just constants, not parameters to override.
parameter RX_IDLE = 0;
parameter RX_CHECK_START = 1;
parameter RX_READ_BITS = 2;
parameter RX_CHECK_STOP = 3;
parameter RX_DELAY_RESTART = 4;
parameter RX_ERROR = 5;
parameter RX_RECEIVED = 6;
// States for the transmitting state machine.
// Constants - do not override.
parameter TX_IDLE = 0;
parameter TX_SENDING = 1;
parameter TX_DELAY_RESTART = 2;
reg [2:0] recv_state = RX_IDLE;
reg [3:0] rx_countdown;
reg [3:0] rx_bits_remaining;
reg [7:0] rx_data;
reg tx_out = 1'b1;
reg [1:0] tx_state = TX_IDLE;
reg [3:0] tx_countdown;
reg [3:0] tx_bits_remaining;
reg [7:0] tx_data;
assign received = recv_state == RX_RECEIVED;
assign recv_error = recv_state == RX_ERROR;
assign is_receiving = recv_state != RX_IDLE;
assign rx_byte = rx_data;
assign tx = tx_out;
assign is_transmitting = tx_state != TX_IDLE;
always @(posedge clk) begin //or posedge rst
if (rst) begin
recv_state = RX_IDLE;
tx_state = TX_IDLE;
end
rx_countdown = rx_countdown - 1;
tx_countdown = tx_countdown - 1;
// Receive state machine
case (recv_state)
RX_IDLE: begin
// A low pulse on the receive line indicates the
// start of data.
if (!rx) begin
// Wait half the period - should resume in the
// middle of this first pulse.
rx_countdown = 2;
recv_state = RX_CHECK_START;
end
end
RX_CHECK_START: begin
if (!rx_countdown) begin
// Check the pulse is still there
if (!rx) begin
// Pulse still there - good
// Wait the bit period to resume half-way
// through the first bit.
rx_countdown = 4;
rx_bits_remaining = 8;
recv_state = RX_READ_BITS;
end else begin
// Pulse lasted less than half the period -
// not a valid transmission.
recv_state = RX_ERROR;
end
end
end
RX_READ_BITS: begin
if (!rx_countdown) begin
// Should be half-way through a bit pulse here.
// Read this bit in, wait for the next if we
// have more to get.
rx_data = {rx, rx_data[7:1]};
rx_countdown = 4;
rx_bits_remaining = rx_bits_remaining - 1;
recv_state = rx_bits_remaining ? RX_READ_BITS : RX_CHECK_STOP;
end
end
RX_CHECK_STOP: begin
if (!rx_countdown) begin
// Should resume half-way through the stop bit
// This should be high - if not, reject the
// transmission and signal an error.
recv_state = rx ? RX_RECEIVED : RX_ERROR;
end
end
RX_DELAY_RESTART: begin
// Waits a set number of cycles before accepting
// another transmission.
recv_state = rx_countdown ? RX_DELAY_RESTART : RX_IDLE;
end
RX_ERROR: begin
// There was an error receiving.
// Raises the recv_error flag for one clock
// cycle while in this state and then waits
// 2 bit periods before accepting another
// transmission.
rx_countdown = 8;
recv_state = RX_DELAY_RESTART;
end
RX_RECEIVED: begin
// Successfully received a byte.
// Raises the received flag for one clock
// cycle while in this state.
recv_state = RX_IDLE;
end
endcase
// Transmit state machine
case (tx_state)
TX_IDLE: begin
if (transmit) begin
// If the transmit flag is raised in the idle
// state, start transmitting the current content
// of the tx_byte input.
tx_data = tx_byte;
// Send the initial, low pulse of 1 bit period
// to signal the start, followed by the data
tx_countdown = 4;
tx_out = 0;
tx_bits_remaining = 8;
tx_state = TX_SENDING;
end
end
TX_SENDING: begin
if (!tx_countdown) begin
if (tx_bits_remaining) begin
tx_bits_remaining = tx_bits_remaining - 1;
tx_out = tx_data[0];
tx_data = {1'b0, tx_data[7:1]};
tx_countdown = 4;
tx_state = TX_SENDING;
end else begin
// Set delay to send out 2 stop bits.
tx_out = 1;
tx_countdown = 8;
tx_state = TX_DELAY_RESTART;
end
end
end
TX_DELAY_RESTART: begin
// Wait until tx_countdown reaches the end before
// we send another transmission. This covers the
// "stop bit" delay.
tx_state = tx_countdown ? TX_DELAY_RESTART : TX_IDLE;
end
endcase
end
endmodule
|
//altiobuf_out CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" DEVICE_FAMILY="Cyclone V" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" PSEUDO_DIFFERENTIAL_MODE="TRUE" USE_DIFFERENTIAL_MODE="TRUE" USE_OE="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN1="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN2="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataout dataout_b
//VERSION_BEGIN 15.1 cbx_altiobuf_out 2015:10:14:18:59:15:SJ cbx_mgl 2015:10:21:19:02:34:SJ cbx_stratixiii 2015:10:14:18:59:15:SJ cbx_stratixv 2015:10:14:18:59:15:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = cyclonev_io_obuf 2 cyclonev_pseudo_diff_out 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module hps_sdram_p0_clock_pair_generator
(
datain,
dataout,
dataout_b) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obuf_ba_oe;
wire [0:0] wire_obufa_o;
wire [0:0] wire_obufa_oe;
wire [0:0] wire_pseudo_diffa_o;
wire [0:0] wire_pseudo_diffa_obar;
wire [0:0] wire_pseudo_diffa_oebout;
wire [0:0] wire_pseudo_diffa_oein;
wire [0:0] wire_pseudo_diffa_oeout;
wire [0:0] oe_w;
cyclonev_io_obuf obuf_ba_0
(
.i(wire_pseudo_diffa_obar),
.o(wire_obuf_ba_o[0:0]),
.obar(),
.oe(wire_obuf_ba_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obuf_ba_0.bus_hold = "false",
obuf_ba_0.open_drain_output = "false",
obuf_ba_0.lpm_type = "cyclonev_io_obuf";
assign
wire_obuf_ba_oe = {(~ wire_pseudo_diffa_oebout[0])};
cyclonev_io_obuf obufa_0
(
.i(wire_pseudo_diffa_o),
.o(wire_obufa_o[0:0]),
.obar(),
.oe(wire_obufa_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_0.bus_hold = "false",
obufa_0.open_drain_output = "false",
obufa_0.lpm_type = "cyclonev_io_obuf";
assign
wire_obufa_oe = {(~ wire_pseudo_diffa_oeout[0])};
cyclonev_pseudo_diff_out pseudo_diffa_0
(
.dtc(),
.dtcbar(),
.i(datain),
.o(wire_pseudo_diffa_o[0:0]),
.obar(wire_pseudo_diffa_obar[0:0]),
.oebout(wire_pseudo_diffa_oebout[0:0]),
.oein(wire_pseudo_diffa_oein[0:0]),
.oeout(wire_pseudo_diffa_oeout[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dtcin(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
assign
wire_pseudo_diffa_oein = {(~ oe_w[0])};
assign
dataout = wire_obufa_o,
dataout_b = wire_obuf_ba_o,
oe_w = 1'b1;
endmodule //hps_sdram_p0_clock_pair_generator
//VALID FILE
|
// ============================================================================
// Copyright (c) 2010
// ============================================================================
//
// Permission:
//
//
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods.
// ============================================================================
//
// ReConfigurable Computing Group
//
// web: http://www.ecs.umass.edu/ece/tessier/rcg/
//
//
// ============================================================================
// Major Functions/Design Description:
//
//
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |RCG |05/10/2011 |
// ============================================================================
//include "NF_2.1_defines.v"
//include "reg_defines_reference_router.v"
module remove_pkt
#(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH=DATA_WIDTH/8,
parameter NUM_OUTPUT_QUEUES = 8,
parameter SRAM_ADDR_WIDTH = 13,
parameter OQ_STAGE_NUM = 6,
parameter OP_LUT_STAGE_NUM = 4,
parameter IOQ_STAGE_NUM = `IO_QUEUE_STAGE_NUM,
parameter PKT_LEN_WIDTH = 11,
parameter PKT_WORDS_WIDTH = PKT_LEN_WIDTH-log2(CTRL_WIDTH),
parameter NUM_OQ_WIDTH = log2(NUM_OUTPUT_QUEUES)
)
( // --- Interface to SRAM
rd_0_ack,
rd_0_data,
rd_0_vld,
rd_0_addr,
rd_0_req,
// --- Interface to regs
src_oq,
rd_src_addr,
src_oq_rd_addr,
src_oq_high_addr,
src_oq_low_addr,
src_oq_empty,
src_oq_rd_addr_new,
pkt_removed,
removed_pkt_data_length,
removed_pkt_overhead_length,
removed_pkt_total_word_length,
removed_oq,
enable_send_pkt,
// --- Interface to datapath
out_data_0,
out_ctrl_0,
out_rdy_0,
out_wr_0,
out_data_1,
out_ctrl_1,
out_rdy_1,
out_wr_1,
out_data_2,
out_ctrl_2,
out_rdy_2,
out_wr_2,
out_data_3,
out_ctrl_3,
out_rdy_3,
out_wr_3,
out_data_4,
out_ctrl_4,
out_rdy_4,
out_wr_4,
out_data_5,
out_ctrl_5,
out_wr_5,
out_rdy_5,
out_data_6,
out_ctrl_6,
out_wr_6,
out_rdy_6,
out_data_7,
out_ctrl_7,
out_wr_7,
out_rdy_7,
// --- Misc
clk,
reset
);
input rd_0_ack;
input [DATA_WIDTH+CTRL_WIDTH-1:0] rd_0_data;
input rd_0_vld;
output reg [SRAM_ADDR_WIDTH-1:0] rd_0_addr;
output reg rd_0_req;
// --- Interface to regs
output reg [NUM_OQ_WIDTH-1:0] src_oq;
output reg rd_src_addr;
input [SRAM_ADDR_WIDTH-1:0] src_oq_rd_addr;
input [SRAM_ADDR_WIDTH-1:0] src_oq_high_addr;
input [SRAM_ADDR_WIDTH-1:0] src_oq_low_addr;
input [NUM_OUTPUT_QUEUES-1:0] src_oq_empty;
output [SRAM_ADDR_WIDTH-1:0] src_oq_rd_addr_new;
output reg pkt_removed;
output reg [PKT_LEN_WIDTH-1:0] removed_pkt_data_length;
output reg [CTRL_WIDTH-1:0] removed_pkt_overhead_length;
output reg [PKT_WORDS_WIDTH-1:0] removed_pkt_total_word_length;
output reg [NUM_OQ_WIDTH-1:0] removed_oq;
input [NUM_OUTPUT_QUEUES-1:0] enable_send_pkt;
// --- Interface to datapath
output [DATA_WIDTH-1:0] out_data_0;
output [CTRL_WIDTH-1:0] out_ctrl_0;
input out_rdy_0;
output reg out_wr_0;
output [DATA_WIDTH-1:0] out_data_1;
output [CTRL_WIDTH-1:0] out_ctrl_1;
input out_rdy_1;
output reg out_wr_1;
output [DATA_WIDTH-1:0] out_data_2;
output [CTRL_WIDTH-1:0] out_ctrl_2;
input out_rdy_2;
output reg out_wr_2;
output [DATA_WIDTH-1:0] out_data_3;
output [CTRL_WIDTH-1:0] out_ctrl_3;
input out_rdy_3;
output reg out_wr_3;
output [DATA_WIDTH-1:0] out_data_4;
output [CTRL_WIDTH-1:0] out_ctrl_4;
input out_rdy_4;
output reg out_wr_4;
output [DATA_WIDTH-1:0] out_data_5;
output [CTRL_WIDTH-1:0] out_ctrl_5;
output reg out_wr_5;
input out_rdy_5;
output [DATA_WIDTH-1:0] out_data_6;
output [CTRL_WIDTH-1:0] out_ctrl_6;
output reg out_wr_6;
input out_rdy_6;
output [DATA_WIDTH-1:0] out_data_7;
output [CTRL_WIDTH-1:0] out_ctrl_7;
output reg out_wr_7;
input out_rdy_7;
// --- Misc
input clk;
input reset;
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
//----------------- Internal parameters ----------------------
parameter NUM_REMOVE_STATES= 4;
parameter RM_IDLE = 1;
parameter RM_LATCH_ADDR = 2;
parameter RM_WAIT_PKT_LEN = 4;
parameter RM_MOVE_PKT = 8;
parameter COUNT_IDLE = 1;
parameter COUNT_HDRS = 2;
parameter COUNT_DATA = 4;
parameter HP_IDLE = 0;
parameter HP_WAIT_EOP = 1;
parameter SRAM_PIPELINE_DEPTH = 4;
//--------------------- Wires/Regs --------------------------
reg [NUM_REMOVE_STATES-1:0] remove_state;
reg [NUM_REMOVE_STATES-1:0] remove_state_next;
wire [NUM_OQ_WIDTH-1:0] src_oq_plus1;
reg [NUM_OQ_WIDTH-1:0] src_oq_next;
reg [SRAM_ADDR_WIDTH-1:0] rd_0_addr_next;
wire [SRAM_ADDR_WIDTH-1:0] rd_0_addr_plus1;
wire [CTRL_WIDTH-1:0] sram_ctrl_out;
wire [DATA_WIDTH-1:0] sram_data_out;
reg [PKT_WORDS_WIDTH-1:0] pkt_len_counter;
reg header_parse_state;
reg header_parse_state_next;
reg ld_pkt_len;
reg ld_oq_dst;
reg [NUM_OUTPUT_QUEUES-1:0] out_wr_selected;
reg [NUM_OQ_WIDTH-1:0] removed_oq_next;
reg pkt_removed_next;
reg [NUM_OUTPUT_QUEUES-1:0] output_fifo_wr_en;
wire [NUM_OUTPUT_QUEUES-1:0] output_fifo_rd_en;
wire [NUM_OUTPUT_QUEUES-1:0] output_fifo_empty;
wire [NUM_OUTPUT_QUEUES-1:0] output_fifo_almost_empty;
wire [DATA_WIDTH+CTRL_WIDTH-1:0] output_fifo_dout[0:NUM_OUTPUT_QUEUES-1];
reg [SRAM_ADDR_WIDTH-1:0] lo_addr;
reg [SRAM_ADDR_WIDTH-1:0] lo_addr_next;
reg [SRAM_ADDR_WIDTH-1:0] hi_addr;
reg [SRAM_ADDR_WIDTH-1:0] hi_addr_next;
// ---------------------- Modules -----------------------------
/* we wait for these fifos to empty before writing to them again
* We check if they are empty before pulling out a packet because
* these fifos drain at 1Gbps while the SRAMs can pullout data at
* 4Gbps. This prevents head-of-line blocking.
* In reality, we should check if the fifos are almost full to
* accomodate the SRAM latency and decrease turnaround time between
* packets.
*/
generate
genvar i;
if(DATA_WIDTH==32) begin:output_fifo32
for(i=0; i<NUM_OUTPUT_QUEUES; i=i+1) begin: output_fifos
/*
syncfifo_512x36 gmac_tx_fifo
(
.clk (clk),
.din (rd_0_data),
.wr_en (output_fifo_wr_en[i]),
.dout (output_fifo_dout[i]),
.rd_en (output_fifo_rd_en[i]),
.empty (output_fifo_empty[i]),
.full (),
.prog_empty (output_fifo_almost_empty[i]),
.rst (reset)
);
*/
syncfifo_512x36 gmac_tx_fifo
(
.aclr ( reset ),
.clock ( clk ),
.data ( rd_0_data ),
.rdreq ( output_fifo_rd_en[i] ),
.wrreq ( output_fifo_wr_en[i] ),
.almost_empty ( output_fifo_almost_empty[i] ),
.almost_full ( ),
.empty ( output_fifo_empty[i] ),
.full ( ),
.q ( output_fifo_dout[i] ),
.usedw ( )
);
end // block: output_fifos
end // block: output_fifo32
else if(DATA_WIDTH==64) begin: output_fifo64
for(i=0; i<NUM_OUTPUT_QUEUES; i=i+1) begin: output_fifos
// we only need 256x72, but since we are going to
// use 2 brams because of datawidth anyway...
/*
syncfifo_512x72 gmac_tx_fifo
(
.clk (clk),
.din (rd_0_data),
.wr_en (output_fifo_wr_en[i]),
.dout (output_fifo_dout[i]),
.rd_en (output_fifo_rd_en[i]),
.empty (output_fifo_empty[i]),
.full (),
.prog_empty (output_fifo_almost_empty[i]),
.rst (reset)
);
*/
syncfifo_512x72 gmac_tx_fifo
(
.aclr ( reset ),
.clock ( clk ),
.data ( rd_0_data ),
.rdreq ( output_fifo_rd_en[i] ),
.wrreq ( output_fifo_wr_en[i] ),
.almost_empty ( output_fifo_almost_empty[i] ),
.empty ( output_fifo_empty[i] ),
.full ( ),
.q ( output_fifo_dout[i] )
);
end // block: output_fifos
end // block: output_fifo64
endgenerate
//---------------------- Logic ------------------------------
/* address logic */
assign {sram_ctrl_out, sram_data_out} = rd_0_data;
assign src_oq_plus1 = (src_oq==NUM_OUTPUT_QUEUES-1) ? 0 : src_oq + 1;
assign rd_0_addr_plus1 = (rd_0_addr == hi_addr) ?
lo_addr : rd_0_addr + 1;
assign src_oq_rd_addr_new = rd_0_addr;
/***************************************************************
* Pipe the outputs to the tx queues
***************************************************************/
assign output_fifo_rd_en[0] = !output_fifo_empty[0] && out_rdy_0;
assign output_fifo_rd_en[1] = !output_fifo_empty[1] && out_rdy_1;
assign output_fifo_rd_en[2] = !output_fifo_empty[2] && out_rdy_2;
assign output_fifo_rd_en[3] = !output_fifo_empty[3] && out_rdy_3;
assign output_fifo_rd_en[4] = !output_fifo_empty[4] && out_rdy_4;
assign output_fifo_rd_en[5] = !output_fifo_empty[5] && out_rdy_5;
assign output_fifo_rd_en[6] = !output_fifo_empty[6] && out_rdy_6;
assign output_fifo_rd_en[7] = !output_fifo_empty[7] && out_rdy_7;
assign {out_ctrl_0, out_data_0} = output_fifo_dout[0];
assign {out_ctrl_1, out_data_1} = output_fifo_dout[1];
assign {out_ctrl_2, out_data_2} = output_fifo_dout[2];
assign {out_ctrl_3, out_data_3} = output_fifo_dout[3];
assign {out_ctrl_4, out_data_4} = output_fifo_dout[4];
assign {out_ctrl_5, out_data_5} = output_fifo_dout[5];
assign {out_ctrl_6, out_data_6} = output_fifo_dout[6];
assign {out_ctrl_7, out_data_7} = output_fifo_dout[7];
always @(posedge clk) begin
if(reset) begin
out_wr_0 <= 0;
out_wr_1 <= 0;
out_wr_2 <= 0;
out_wr_3 <= 0;
out_wr_4 <= 0;
out_wr_5 <= 0;
out_wr_6 <= 0;
out_wr_7 <= 0;
end
else begin
out_wr_0 <= output_fifo_rd_en[0];
out_wr_1 <= output_fifo_rd_en[1];
out_wr_2 <= output_fifo_rd_en[2];
out_wr_3 <= output_fifo_rd_en[3];
out_wr_4 <= output_fifo_rd_en[4];
out_wr_5 <= output_fifo_rd_en[5];
out_wr_6 <= output_fifo_rd_en[6];
out_wr_7 <= output_fifo_rd_en[7];
end
end // always @ (posedge clk)
/*****************************************************************
* cycle through the output queues until one of them is not empty
* send read requests until the pkt length is set
* Then issue exactly the required number of reads for this pkt
* Then start on the next pkt.
*****************************************************************/
always @(*) begin
remove_state_next = remove_state;
src_oq_next = src_oq;
removed_oq_next = removed_oq;
rd_0_req = 0;
rd_0_addr_next = rd_0_addr;
hi_addr_next = hi_addr;
lo_addr_next = lo_addr;
pkt_removed_next = 0; // signal to store the reg info until the pkt is removed
rd_src_addr = 0;
case(remove_state)
RM_IDLE: begin
/* loop until we find a non-empty queue
* whose fifo has space for a full packet */
if(src_oq_empty[src_oq] | !enable_send_pkt[src_oq] | !output_fifo_empty[src_oq]) begin
src_oq_next = src_oq_plus1;
end
else begin
remove_state_next = RM_LATCH_ADDR;
rd_src_addr = 1;
end
end // case: RM_IDLE
RM_LATCH_ADDR: begin
rd_0_addr_next = src_oq_rd_addr;
hi_addr_next = src_oq_high_addr;
lo_addr_next = src_oq_low_addr;
remove_state_next = RM_WAIT_PKT_LEN;
end
/* wait in this state until we know the pkt length */
RM_WAIT_PKT_LEN: begin
if(ld_pkt_len) begin
remove_state_next = RM_MOVE_PKT;
end
rd_0_req = 1;
if(rd_0_ack) begin
rd_0_addr_next = rd_0_addr_plus1;
end
end // case: RM_WAIT_PKT_LEN
/* issue enough reads to read just one pkt */
RM_MOVE_PKT: begin
/* if the rd address was accepted then put the next one */
rd_0_req = 1;
if(rd_0_ack) begin
rd_0_addr_next = rd_0_addr_plus1;
end
if(rd_0_ack && (pkt_len_counter == SRAM_PIPELINE_DEPTH)) begin
remove_state_next = RM_IDLE;
src_oq_next = src_oq_plus1;
pkt_removed_next = 1;
removed_oq_next = src_oq;
end
end // case: RM_MOVE_PKT
default: begin end
endcase // case(remove_state)
end // always @ (*)
always @(posedge clk) begin
if(reset) begin
remove_state <= RM_IDLE;
rd_0_addr <= 0;
src_oq <= 0;
removed_oq <= 0;
hi_addr <= 0;
lo_addr <= 0;
pkt_removed <= 0;
end
else begin
remove_state <= remove_state_next;
rd_0_addr <= rd_0_addr_next;
hi_addr <= hi_addr_next;
lo_addr <= lo_addr_next;
src_oq <= src_oq_next;
removed_oq <= removed_oq_next;
pkt_removed <= pkt_removed_next;
end
end // always @ (posedge clk)
/*************************************************************************
* Wait until a pkt starts to be removed from the SRAM
* Parse the headers and latch the output destination and the pkt length
*************************************************************************/
always @(*) begin
header_parse_state_next = header_parse_state;
ld_pkt_len = 0;
ld_oq_dst = 0;
output_fifo_wr_en = 0;
case(header_parse_state)
HP_IDLE: begin
if(rd_0_vld) begin
output_fifo_wr_en = out_wr_selected;
end
if(rd_0_vld & sram_ctrl_out == IOQ_STAGE_NUM) begin
ld_pkt_len = 1;
end
if(rd_0_vld & sram_ctrl_out == IOQ_STAGE_NUM) begin
ld_oq_dst = 1;
output_fifo_wr_en = sram_data_out[`IOQ_DST_PORT_POS + NUM_OUTPUT_QUEUES - 1:`IOQ_DST_PORT_POS] & output_fifo_empty;
end
if(rd_0_vld & sram_ctrl_out == 0) begin
header_parse_state_next = HP_WAIT_EOP;
end
end
HP_WAIT_EOP: begin
if(rd_0_vld) begin
output_fifo_wr_en = out_wr_selected;
if(sram_ctrl_out!=0) begin // eop
header_parse_state_next = HP_IDLE;
end
end
end
default: begin end
endcase // case pkt_len_parse_state
end // always @ (*)
always @(posedge clk) begin
if(reset) begin
header_parse_state <= HP_IDLE;
pkt_len_counter <= 0;
out_wr_selected <= 0;
end
else begin
header_parse_state <= header_parse_state_next;
if(ld_pkt_len) begin
pkt_len_counter <= sram_data_out[PKT_WORDS_WIDTH+`IOQ_WORD_LEN_POS:`IOQ_WORD_LEN_POS] + 'h1;
end
else if(rd_0_ack) begin
pkt_len_counter <= pkt_len_counter - 1;
end
/* only send the pkt to the destinations that are ready
* For unicasts, this was already checked before issuing SRAM reads,
* so this has no effect.
* For broadcasts, only ready queues will receive it */
if(ld_oq_dst) begin
out_wr_selected <= sram_data_out[`IOQ_DST_PORT_POS + NUM_OUTPUT_QUEUES - 1:`IOQ_DST_PORT_POS] & output_fifo_empty;
end
end
end // always @ (posedge clk)
always @(posedge clk) begin
if(reset) begin
removed_pkt_data_length <= 0;
removed_pkt_overhead_length <= 0;
removed_pkt_total_word_length <= 0;
end
else begin
if(ld_pkt_len) begin
removed_pkt_data_length <= sram_data_out[PKT_LEN_WIDTH+`IOQ_BYTE_LEN_POS:`IOQ_BYTE_LEN_POS];
removed_pkt_overhead_length <= CTRL_WIDTH;
removed_pkt_total_word_length <= sram_data_out[PKT_WORDS_WIDTH+`IOQ_WORD_LEN_POS:`IOQ_WORD_LEN_POS] + 1;
end
end // else: !if(reset)
end // always @ (posedge clk)
// synthesis translate_off
integer pkt_len_counter_sim;
reg in_pkt;
always @(posedge clk) begin
if(ld_pkt_len) begin
pkt_len_counter_sim <= sram_data_out[PKT_WORDS_WIDTH+`IOQ_WORD_LEN_POS:`IOQ_WORD_LEN_POS];
end
else if(rd_0_vld) begin
pkt_len_counter_sim <= pkt_len_counter_sim - 1;
end
if (reset)
in_pkt <= 1'b0;
else if (!in_pkt && rd_0_vld & sram_ctrl_out == 0)
in_pkt <= 1'b1;
else if(in_pkt && rd_0_vld & sram_ctrl_out != 0) begin
in_pkt <= 1'b0;
if (pkt_len_counter_sim != 1) begin
$display("%t %m ERROR: Pkt length count in SRAM is larger than the packet size!", $time);
$finish;
end
end
end // always @ (posedge clk)
// synthesis translate_on
endmodule // remove_pkt
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND4B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__AND4B_BEHAVIORAL_PP_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__and4b (
X ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , not0_out, B, C, D );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND4B_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CONB_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__CONB_PP_BLACKBOX_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__conb (
HI ,
LO ,
VPWR,
VGND,
VPB ,
VNB
);
output HI ;
output LO ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CONB_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O41A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__O41A_BEHAVIORAL_PP_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o41a (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O41A_BEHAVIORAL_PP_V |
/*
* Copyright (c) 2015-2016 The Ultiparc Project. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* Testbench for programmable interrupt controller
*/
`include "common.vh"
`include "ocp_const.vh"
`ifndef TRACE_FILE
`define TRACE_FILE "trace.vcd"
`endif
module tb_intr_controller();
localparam HCLK = 5;
localparam PCLK = 2*HCLK; /* Clock period */
/* Interrupt controller registers */
localparam [`ADDR_WIDTH-1:0] ISTATREG = 32'h000; /* Interrupts status register */
localparam [`ADDR_WIDTH-1:0] IMASKREG = 32'h004; /* Interrupts mask register */
localparam [`ADDR_WIDTH-1:0] IRAWREG = 32'h008; /* Raw interrupts register */
reg clk;
reg nrst;
reg [`ADDR_WIDTH-1:0] MAddr;
reg [2:0] MCmd;
reg [`DATA_WIDTH-1:0] MData;
reg [`BEN_WIDTH-1:0] MByteEn;
wire SCmdAccept;
wire [`DATA_WIDTH-1:0] SData;
wire [1:0] SResp;
reg [31:0] intr_vec;
wire intr;
always
#HCLK clk = !clk;
/* Issue bus read transaction */
task bus_read;
input [`ADDR_WIDTH-1:0] addr;
begin
@(posedge clk)
begin
MAddr <= addr;
MByteEn <= 4'hf;
MCmd <= `OCP_CMD_READ;
end
@(posedge clk)
begin
MAddr <= 0;
MByteEn <= 4'h0;
MCmd <= `OCP_CMD_IDLE;
end
end
endtask
/* Issue bus write transaction */
task bus_write;
input [`ADDR_WIDTH-1:0] addr;
input [`DATA_WIDTH-1:0] data;
begin
@(posedge clk)
begin
MAddr <= addr;
MData <= data;
MByteEn <= 4'hf;
MCmd <= `OCP_CMD_WRITE;
end
@(posedge clk)
begin
MAddr <= 0;
MData <= 0;
MByteEn <= 4'h0;
MCmd <= `OCP_CMD_IDLE;
end
end
endtask
/* Generate interrupt */
task gen_intr;
input [4:0] line;
begin
@(posedge clk)
begin
intr_vec[line] <= 1'b1;
end
@(posedge clk)
begin
intr_vec[line] <= 1'b0;
end
end
endtask
initial
begin
/* Set tracing */
$dumpfile(`TRACE_FILE);
$dumpvars(0, tb_intr_controller);
clk = 1;
nrst = 0;
MAddr = 0;
MData = 0;
MByteEn = 0;
MCmd = 0;
intr_vec = 0;
#(10*PCLK) nrst = 1;
#(2*PCLK)
/* Unmask line 0 */
bus_write(IMASKREG, 32'h1);
#(2*PCLK)
/* Generate interrupt on line 0 */
gen_intr(0);
#(2*PCLK)
/* Acknowledge */
bus_write(ISTATREG, 32'h1);
#(2*PCLK)
/* Generate interrupt on line 1 */
gen_intr(1);
#(2*PCLK)
/* Read raw status */
bus_read(IRAWREG);
#500 $finish;
end
/* Instantiate interrupt controller */
intr_controller intr_ctrl(
.clk(clk),
.nrst(nrst),
.i_MAddr(MAddr),
.i_MCmd(MCmd),
.i_MData(MData),
.i_MByteEn(MByteEn),
.o_SCmdAccept(SCmdAccept),
.o_SData(SData),
.o_SResp(SResp),
.o_intr(intr),
.i_intr_vec(intr_vec)
);
endmodule /* tb_intr_controller */
|
/**************************************************************************
Async Fifo
-parameter N
Queue data vector width
Example : DATA[3:0] is N=4
-parameter DEPTH
Queue entry depth
Example DEPTH 16 is DEPTH=16
-parameter D_N
Queue entry depth n size
Example PARAMETER_DEPTH16 is 4
-SDF Settings
Asynchronus Clock : iWR_CLOCK - iRD_CLOCK
-Make : 2013/2/13
-Update :
Takahiro Ito
**************************************************************************/
`default_nettype none
module mist1032sa_async_fifo
#(
parameter N = 16,
parameter DEPTH = 4,
parameter D_N = 2
)
(
//System
input wire inRESET,
//Remove
input wire iREMOVE,
//WR
input wire iWR_CLOCK,
input wire iWR_EN,
input wire [N-1:0] iWR_DATA,
output wire oWR_FULL,
//RD
input wire iRD_CLOCK,
input wire iRD_EN,
output wire [N-1:0] oRD_DATA,
output wire oRD_EMPTY
);
//Full
wire [D_N:0] full_count;
wire full;
wire [D_N:0] empty_count;
wire empty;
//Memory
reg [N-1:0] b_memory[0:DEPTH-1];
//Counter
reg [D_N:0] b_wr_counter/* synthesis preserve = 1 */; //Altera QuartusII Option
reg [D_N:0] b_rd_counter/* synthesis preserve = 1 */; //Altera QuartusII Option
wire [D_N:0] gray_d_fifo_rd_counter;
wire [D_N:0] binary_d_fifo_rd_counter;
wire [D_N:0] gray_d_fifo_wr_counter;
wire [D_N:0] binary_d_fifo_wr_counter;
//Assign
assign full_count = b_wr_counter - binary_d_fifo_rd_counter;
assign full = full_count[D_N] || (full_count[D_N-1:0] == {D_N{1'b1}})? 1'b1 : 1'b0;
//Empty
assign empty_count = binary_d_fifo_wr_counter - (b_rd_counter);
assign empty = (empty_count == {D_N+1{1'b0}})? 1'b1 : 1'b0;
/***************************************************
Memory
***************************************************/
//Write
always@(posedge iWR_CLOCK or negedge inRESET)begin
if(!inRESET)begin
b_wr_counter <= {D_N{1'b0}};
end
else if(iREMOVE)begin
b_wr_counter <= {D_N{1'b0}};
end
else begin
if(iWR_EN && !full)begin
b_memory[b_wr_counter[D_N-1:0]] <= iWR_DATA;
b_wr_counter <= b_wr_counter + {{D_N-1{1'b0}}, 1'b1};
end
end
end
//Read Pointer
always@(posedge iRD_CLOCK or negedge inRESET)begin
if(!inRESET)begin
b_rd_counter <= {D_N{1'b0}};
end
else if(iREMOVE)begin
b_rd_counter <= {D_N{1'b0}};
end
else begin
if(iRD_EN && !empty)begin
b_rd_counter <= b_rd_counter + {{D_N-1{1'b0}}, 1'b1};
end
end
end
/***************************************************
Counter Buffer
***************************************************/
mist1032sa_async_fifo_double_flipflop #(D_N+1) D_FIFO_READ(
.iCLOCK(iWR_CLOCK),
.inRESET(inRESET),
.iREQ_DATA(bin2gray(b_rd_counter)),
.oOUT_DATA(gray_d_fifo_rd_counter)
);
assign binary_d_fifo_rd_counter = gray2bin(gray_d_fifo_rd_counter);
mist1032sa_async_fifo_double_flipflop #(D_N+1) D_FIFO_WRITE(
.iCLOCK(iRD_CLOCK),
.inRESET(inRESET),
.iREQ_DATA(bin2gray(b_wr_counter)),
.oOUT_DATA(gray_d_fifo_wr_counter)
);
assign binary_d_fifo_wr_counter = gray2bin(gray_d_fifo_wr_counter);
/***************************************************
Function
***************************************************/
function [D_N:0] bin2gray;
input [D_N:0] binary;
begin
bin2gray = binary ^ (binary >> 1'b1);
end
endfunction
function[D_N:0] gray2bin(input[D_N:0] gray);
integer i;
for(i=D_N; i>=0; i=i-1)begin
if(i==D_N)begin
gray2bin[i] = gray[i];
end
else begin
gray2bin[i] = gray[i] ^ gray2bin[i+1];
end
end
endfunction
/***************************************************
Output Assign
***************************************************/
assign oWR_FULL = full;
assign oRD_EMPTY = empty;
assign oRD_DATA = b_memory[b_rd_counter[D_N-1:0]];
endmodule
`default_nettype wire
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Mon Jan 26 10:14:21 2015
// Host : xilinxvivadotools running 64-bit unknown
// Command : write_verilog -force -mode synth_stub
// /home/ece532/testing/ov7670/nexys4ddr_ov7670/nexys4ddr_ov7670.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v
// Design : clk_wiz_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module clk_wiz_0(clk_in1, clk_out1, clk_out2)
/* synthesis syn_black_box black_box_pad_pin="clk_in1,clk_out1,clk_out2" */;
input clk_in1;
output clk_out1;
output clk_out2;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O31AI_1_V
`define SKY130_FD_SC_MS__O31AI_1_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o31ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o31ai_1 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o31ai_1 (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O31AI_1_V
|
//
// mist_io.v
//
// mist_io for the MiST board
// http://code.google.com/p/mist-board/
//
// Copyright (c) 2014 Till Harbaum <[email protected]>
// Copyright (c) 2015-2017 Sorgelig
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
///////////////////////////////////////////////////////////////////////
//
// Use buffer to access SD card. It's time-critical part.
// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
// (Sorgelig)
//
// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
// clk_ps2 = clk_sys/(PS2DIV*2)
//
module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
(
// parameter STRLEN and the actual length of conf_str have to match
input [(8*STRLEN)-1:0] conf_str,
// Global clock. It should be around 100MHz (higher is better).
input clk_sys,
// Global SPI clock from ARM. 24MHz
input SPI_SCK,
input CONF_DATA0,
input SPI_SS2,
output SPI_DO,
input SPI_DI,
output reg [7:0] joystick_0,
output reg [7:0] joystick_1,
output reg [15:0] joystick_analog_0,
output reg [15:0] joystick_analog_1,
output [1:0] buttons,
output [1:0] switches,
output scandoubler_disable,
output ypbpr,
output reg [31:0] status,
// SD config
input sd_conf,
input sd_sdhc,
output [1:0] img_mounted, // signaling that new image has been mounted
output reg [31:0] img_size, // size of image in bytes
// SD block level access
input [31:0] sd_lba,
input [1:0] sd_rd,
input [1:0] sd_wr,
output reg sd_ack,
output reg sd_ack_conf,
// SD byte level access. Signals for 2-PORT altsyncram.
output reg [8:0] sd_buff_addr,
output reg [7:0] sd_buff_dout,
input [7:0] sd_buff_din,
output reg sd_buff_wr,
// ps2 keyboard emulation
output ps2_kbd_clk,
output reg ps2_kbd_data,
output ps2_mouse_clk,
output reg ps2_mouse_data,
// ps2 alternative interface.
// [8] - extended, [9] - pressed, [10] - toggles with every press/release
output reg [10:0] ps2_key = 0,
// [24] - toggles with every event
output reg [24:0] ps2_mouse = 0,
// ARM -> FPGA download
input ioctl_ce,
output reg ioctl_download = 0, // signal indicating an active download
output reg [7:0] ioctl_index, // menu index used to upload the file
output reg ioctl_wr = 0,
output reg [24:0] ioctl_addr,
output reg [7:0] ioctl_dout
);
reg [7:0] but_sw;
reg [2:0] stick_idx;
reg [1:0] mount_strobe = 0;
assign img_mounted = mount_strobe;
assign buttons = but_sw[1:0];
assign switches = but_sw[3:2];
assign scandoubler_disable = but_sw[4];
assign ypbpr = but_sw[5];
// this variant of user_io is for 8 bit cores (type == a4) only
wire [7:0] core_type = 8'ha4;
// command byte read by the io controller
wire drive_sel = sd_rd[1] | sd_wr[1];
wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] };
reg [7:0] cmd;
reg [2:0] bit_cnt; // counts bits 0-7 0-7 ...
reg [9:0] byte_cnt; // counts bytes
reg spi_do;
assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
reg [7:0] spi_data_out;
// SPI transmitter
always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt];
reg [7:0] spi_data_in;
reg spi_data_ready = 0;
// SPI receiver
always@(posedge SPI_SCK or posedge CONF_DATA0) begin
reg [6:0] sbuf;
reg [31:0] sd_lba_r;
reg drive_sel_r;
if(CONF_DATA0) begin
bit_cnt <= 0;
byte_cnt <= 0;
spi_data_out <= core_type;
end
else
begin
bit_cnt <= bit_cnt + 1'd1;
sbuf <= {sbuf[5:0], SPI_DI};
// finished reading command byte
if(bit_cnt == 7) begin
if(!byte_cnt) cmd <= {sbuf, SPI_DI};
spi_data_in <= {sbuf, SPI_DI};
spi_data_ready <= ~spi_data_ready;
if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
spi_data_out <= 0;
case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd})
// reading config string
8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8];
// reading sd card status
8'h16: if(byte_cnt == 0) begin
spi_data_out <= sd_cmd;
sd_lba_r <= sd_lba;
drive_sel_r <= drive_sel;
end else if (byte_cnt == 1) begin
spi_data_out <= drive_sel_r;
end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8];
// reading sd card write data
8'h18: spi_data_out <= sd_buff_din;
endcase
end
end
end
reg [31:0] ps2_key_raw = 0;
wire pressed = (ps2_key_raw[15:8] != 8'hf0);
wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
// transfer to clk_sys domain
always@(posedge clk_sys) begin
reg old_ss1, old_ss2;
reg old_ready1, old_ready2;
reg [2:0] b_wr;
reg got_ps2 = 0;
old_ss1 <= CONF_DATA0;
old_ss2 <= old_ss1;
old_ready1 <= spi_data_ready;
old_ready2 <= old_ready1;
sd_buff_wr <= b_wr[0];
if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
b_wr <= (b_wr<<1);
if(old_ss2) begin
got_ps2 <= 0;
sd_ack <= 0;
sd_ack_conf <= 0;
sd_buff_addr <= 0;
if(got_ps2) begin
if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24];
if(cmd == 5) begin
ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed
end
end
end
else
if(old_ready2 ^ old_ready1) begin
if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
if(byte_cnt < 2) begin
if (cmd == 8'h19) sd_ack_conf <= 1;
if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1;
mount_strobe <= 0;
if(cmd == 5) ps2_key_raw <= 0;
end else begin
case(cmd)
// buttons and switches
8'h01: but_sw <= spi_data_in;
8'h02: joystick_0 <= spi_data_in;
8'h03: joystick_1 <= spi_data_in;
// store incoming ps2 mouse bytes
8'h04: begin
got_ps2 <= 1;
case(byte_cnt)
2: ps2_mouse[7:0] <= spi_data_in;
3: ps2_mouse[15:8] <= spi_data_in;
4: ps2_mouse[23:16] <= spi_data_in;
endcase
ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in;
ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
end
// store incoming ps2 keyboard bytes
8'h05: begin
got_ps2 <= 1;
ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in};
ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in;
ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
end
8'h15: status[7:0] <= spi_data_in;
// send SD config IO -> FPGA
// flag that download begins
// sd card knows data is config if sd_dout_strobe is asserted
// with sd_ack still being inactive (low)
8'h19,
// send sector IO -> FPGA
// flag that download begins
8'h17: begin
sd_buff_dout <= spi_data_in;
b_wr <= 1;
end
// joystick analog
8'h1a: begin
// first byte is joystick index
if(byte_cnt == 2) stick_idx <= spi_data_in[2:0];
else if(byte_cnt == 3) begin
// second byte is x axis
if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in;
else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in;
end else if(byte_cnt == 4) begin
// third byte is y axis
if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in;
else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in;
end
end
// notify image selection
8'h1c: mount_strobe[spi_data_in[0]] <= 1;
// send image info
8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in;
// status, 32bit version
8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in;
default: ;
endcase
end
end
end
/////////////////////////////// PS2 ///////////////////////////////
// 8 byte fifos to store ps2 bytes
localparam PS2_FIFO_BITS = 3;
reg clk_ps2;
always @(negedge clk_sys) begin
integer cnt;
cnt <= cnt + 1'd1;
if(cnt == PS2DIV) begin
clk_ps2 <= ~clk_ps2;
cnt <= 0;
end
end
// keyboard
reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
// ps2 transmitter state machine
reg [3:0] ps2_kbd_tx_state;
reg [7:0] ps2_kbd_tx_byte;
reg ps2_kbd_parity;
assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
// ps2 transmitter
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
reg ps2_kbd_r_inc;
always@(posedge clk_sys) begin
reg old_clk;
old_clk <= clk_ps2;
if(~old_clk & clk_ps2) begin
ps2_kbd_r_inc <= 0;
if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
// transmitter is idle?
if(ps2_kbd_tx_state == 0) begin
// data in fifo present?
if(ps2_kbd_wptr != ps2_kbd_rptr) begin
// load tx register from fifo
ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
ps2_kbd_r_inc <= 1;
// reset parity
ps2_kbd_parity <= 1;
// start transmitter
ps2_kbd_tx_state <= 1;
// put start bit on data line
ps2_kbd_data <= 0; // start bit is 0
end
end else begin
// transmission of 8 data bits
if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits
ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
if(ps2_kbd_tx_byte[0])
ps2_kbd_parity <= !ps2_kbd_parity;
end
// transmission of parity
if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
// transmission of stop bit
if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1
// advance state machine
if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
else ps2_kbd_tx_state <= 0;
end
end
end
// mouse
reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
// ps2 transmitter state machine
reg [3:0] ps2_mouse_tx_state;
reg [7:0] ps2_mouse_tx_byte;
reg ps2_mouse_parity;
assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
// ps2 transmitter
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
reg ps2_mouse_r_inc;
always@(posedge clk_sys) begin
reg old_clk;
old_clk <= clk_ps2;
if(~old_clk & clk_ps2) begin
ps2_mouse_r_inc <= 0;
if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
// transmitter is idle?
if(ps2_mouse_tx_state == 0) begin
// data in fifo present?
if(ps2_mouse_wptr != ps2_mouse_rptr) begin
// load tx register from fifo
ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
ps2_mouse_r_inc <= 1;
// reset parity
ps2_mouse_parity <= 1;
// start transmitter
ps2_mouse_tx_state <= 1;
// put start bit on data line
ps2_mouse_data <= 0; // start bit is 0
end
end else begin
// transmission of 8 data bits
if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits
ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
if(ps2_mouse_tx_byte[0])
ps2_mouse_parity <= !ps2_mouse_parity;
end
// transmission of parity
if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
// transmission of stop bit
if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1
// advance state machine
if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
else ps2_mouse_tx_state <= 0;
end
end
end
/////////////////////////////// DOWNLOADING ///////////////////////////////
reg [7:0] data_w;
reg [24:0] addr_w;
reg rclk = 0;
localparam UIO_FILE_TX = 8'h53;
localparam UIO_FILE_TX_DAT = 8'h54;
localparam UIO_FILE_INDEX = 8'h55;
reg rdownload = 0;
// data_io has its own SPI interface to the io controller
always@(posedge SPI_SCK, posedge SPI_SS2) begin
reg [6:0] sbuf;
reg [7:0] cmd;
reg [4:0] cnt;
reg [24:0] addr;
if(SPI_SS2) cnt <= 0;
else begin
// don't shift in last bit. It is evaluated directly
// when writing to ram
if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
// count 0-7 8-15 8-15 ...
if(cnt < 15) cnt <= cnt + 1'd1;
else cnt <= 8;
// finished command byte
if(cnt == 7) cmd <= {sbuf, SPI_DI};
// prepare/end transmission
if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
// prepare
if(SPI_DI) begin
case(ioctl_index[4:0])
1: addr <= 25'h200000; // TRD buffer at 2MB
2: addr <= 25'h400000; // tape buffer at 4MB
default: addr <= 25'h150000; // boot rom
endcase
rdownload <= 1;
end else begin
addr_w <= addr;
rdownload <= 0;
end
end
// command 0x54: UIO_FILE_TX
if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
addr_w <= addr;
data_w <= {sbuf, SPI_DI};
addr <= addr + 1'd1;
rclk <= ~rclk;
end
// expose file (menu) index
if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
end
end
// transfer to ioctl_clk domain.
// ioctl_index is set before ioctl_download, so it's stable already
always@(posedge clk_sys) begin
reg rclkD, rclkD2;
if(ioctl_ce) begin
ioctl_download <= rdownload;
rclkD <= rclk;
rclkD2 <= rclkD;
ioctl_wr <= 0;
if(rclkD != rclkD2) begin
ioctl_dout <= data_w;
ioctl_addr <= addr_w;
ioctl_wr <= 1;
end
end
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE DMA Channel Select ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: wb_dma_ch_sel.v,v 1.4 2002-02-01 01:54:45 rudi Exp $
//
// $Date: 2002-02-01 01:54:45 $
// $Revision: 1.4 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.3 2001/10/19 04:35:04 rudi
//
// - Made the core parameterized
//
// Revision 1.2 2001/08/15 05:40:30 rudi
//
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
// - Added Section 3.10, describing DMA restart.
//
// Revision 1.1 2001/07/29 08:57:02 rudi
//
//
// 1) Changed Directory Structure
// 2) Added restart signal (REST)
//
// Revision 1.4 2001/06/14 08:52:00 rudi
//
//
// Changed arbiter module name.
//
// Revision 1.3 2001/06/13 02:26:48 rudi
//
//
// Small changes after running lint.
//
// Revision 1.2 2001/06/05 10:22:36 rudi
//
//
// - Added Support of up to 31 channels
// - Added support for 2,4 and 8 priority levels
// - Now can have up to 31 channels
// - Added many configuration items
// - Changed reset to async
//
// Revision 1.1.1.1 2001/03/19 13:10:35 rudi
// Initial Release
//
//
//
`include "wb_dma_defines.v"
module wb_dma_ch_sel(clk, rst,
// DMA Request Lines
req_i, ack_o, nd_i,
// DMA Registers Inputs
pointer0, pointer0_s, ch0_csr, ch0_txsz, ch0_adr0, ch0_adr1, ch0_am0, ch0_am1,
pointer1, pointer1_s, ch1_csr, ch1_txsz, ch1_adr0, ch1_adr1, ch1_am0, ch1_am1,
pointer2, pointer2_s, ch2_csr, ch2_txsz, ch2_adr0, ch2_adr1, ch2_am0, ch2_am1,
pointer3, pointer3_s, ch3_csr, ch3_txsz, ch3_adr0, ch3_adr1, ch3_am0, ch3_am1,
pointer4, pointer4_s, ch4_csr, ch4_txsz, ch4_adr0, ch4_adr1, ch4_am0, ch4_am1,
pointer5, pointer5_s, ch5_csr, ch5_txsz, ch5_adr0, ch5_adr1, ch5_am0, ch5_am1,
pointer6, pointer6_s, ch6_csr, ch6_txsz, ch6_adr0, ch6_adr1, ch6_am0, ch6_am1,
pointer7, pointer7_s, ch7_csr, ch7_txsz, ch7_adr0, ch7_adr1, ch7_am0, ch7_am1,
pointer8, pointer8_s, ch8_csr, ch8_txsz, ch8_adr0, ch8_adr1, ch8_am0, ch8_am1,
pointer9, pointer9_s, ch9_csr, ch9_txsz, ch9_adr0, ch9_adr1, ch9_am0, ch9_am1,
pointer10, pointer10_s, ch10_csr, ch10_txsz, ch10_adr0, ch10_adr1, ch10_am0, ch10_am1,
pointer11, pointer11_s, ch11_csr, ch11_txsz, ch11_adr0, ch11_adr1, ch11_am0, ch11_am1,
pointer12, pointer12_s, ch12_csr, ch12_txsz, ch12_adr0, ch12_adr1, ch12_am0, ch12_am1,
pointer13, pointer13_s, ch13_csr, ch13_txsz, ch13_adr0, ch13_adr1, ch13_am0, ch13_am1,
pointer14, pointer14_s, ch14_csr, ch14_txsz, ch14_adr0, ch14_adr1, ch14_am0, ch14_am1,
pointer15, pointer15_s, ch15_csr, ch15_txsz, ch15_adr0, ch15_adr1, ch15_am0, ch15_am1,
pointer16, pointer16_s, ch16_csr, ch16_txsz, ch16_adr0, ch16_adr1, ch16_am0, ch16_am1,
pointer17, pointer17_s, ch17_csr, ch17_txsz, ch17_adr0, ch17_adr1, ch17_am0, ch17_am1,
pointer18, pointer18_s, ch18_csr, ch18_txsz, ch18_adr0, ch18_adr1, ch18_am0, ch18_am1,
pointer19, pointer19_s, ch19_csr, ch19_txsz, ch19_adr0, ch19_adr1, ch19_am0, ch19_am1,
pointer20, pointer20_s, ch20_csr, ch20_txsz, ch20_adr0, ch20_adr1, ch20_am0, ch20_am1,
pointer21, pointer21_s, ch21_csr, ch21_txsz, ch21_adr0, ch21_adr1, ch21_am0, ch21_am1,
pointer22, pointer22_s, ch22_csr, ch22_txsz, ch22_adr0, ch22_adr1, ch22_am0, ch22_am1,
pointer23, pointer23_s, ch23_csr, ch23_txsz, ch23_adr0, ch23_adr1, ch23_am0, ch23_am1,
pointer24, pointer24_s, ch24_csr, ch24_txsz, ch24_adr0, ch24_adr1, ch24_am0, ch24_am1,
pointer25, pointer25_s, ch25_csr, ch25_txsz, ch25_adr0, ch25_adr1, ch25_am0, ch25_am1,
pointer26, pointer26_s, ch26_csr, ch26_txsz, ch26_adr0, ch26_adr1, ch26_am0, ch26_am1,
pointer27, pointer27_s, ch27_csr, ch27_txsz, ch27_adr0, ch27_adr1, ch27_am0, ch27_am1,
pointer28, pointer28_s, ch28_csr, ch28_txsz, ch28_adr0, ch28_adr1, ch28_am0, ch28_am1,
pointer29, pointer29_s, ch29_csr, ch29_txsz, ch29_adr0, ch29_adr1, ch29_am0, ch29_am1,
pointer30, pointer30_s, ch30_csr, ch30_txsz, ch30_adr0, ch30_adr1, ch30_am0, ch30_am1,
// DMA Registers Write Back Channel Select
ch_sel, ndnr,
// DMA Engine Interface
de_start, ndr, csr, pointer, txsz, adr0, adr1, am0, am1,
pointer_s, next_ch, de_ack, dma_busy
);
////////////////////////////////////////////////////////////////////
//
// Module Parameters
//
// chXX_conf = { CBUF, ED, ARS, EN }
parameter [1:0] pri_sel = 2'h0;
parameter [3:0] ch0_conf = 4'h1;
parameter [3:0] ch1_conf = 4'h0;
parameter [3:0] ch2_conf = 4'h0;
parameter [3:0] ch3_conf = 4'h0;
parameter [3:0] ch4_conf = 4'h0;
parameter [3:0] ch5_conf = 4'h0;
parameter [3:0] ch6_conf = 4'h0;
parameter [3:0] ch7_conf = 4'h0;
parameter [3:0] ch8_conf = 4'h0;
parameter [3:0] ch9_conf = 4'h0;
parameter [3:0] ch10_conf = 4'h0;
parameter [3:0] ch11_conf = 4'h0;
parameter [3:0] ch12_conf = 4'h0;
parameter [3:0] ch13_conf = 4'h0;
parameter [3:0] ch14_conf = 4'h0;
parameter [3:0] ch15_conf = 4'h0;
parameter [3:0] ch16_conf = 4'h0;
parameter [3:0] ch17_conf = 4'h0;
parameter [3:0] ch18_conf = 4'h0;
parameter [3:0] ch19_conf = 4'h0;
parameter [3:0] ch20_conf = 4'h0;
parameter [3:0] ch21_conf = 4'h0;
parameter [3:0] ch22_conf = 4'h0;
parameter [3:0] ch23_conf = 4'h0;
parameter [3:0] ch24_conf = 4'h0;
parameter [3:0] ch25_conf = 4'h0;
parameter [3:0] ch26_conf = 4'h0;
parameter [3:0] ch27_conf = 4'h0;
parameter [3:0] ch28_conf = 4'h0;
parameter [3:0] ch29_conf = 4'h0;
parameter [3:0] ch30_conf = 4'h0;
////////////////////////////////////////////////////////////////////
//
// Module IOs
//
input clk, rst;
// DMA Request Lines
input [30:0] req_i;
output [30:0] ack_o;
input [30:0] nd_i;
// Channel Registers Inputs
input [31:0] pointer0, pointer0_s, ch0_csr, ch0_txsz, ch0_adr0, ch0_adr1, ch0_am0, ch0_am1;
input [31:0] pointer1, pointer1_s, ch1_csr, ch1_txsz, ch1_adr0, ch1_adr1, ch1_am0, ch1_am1;
input [31:0] pointer2, pointer2_s, ch2_csr, ch2_txsz, ch2_adr0, ch2_adr1, ch2_am0, ch2_am1;
input [31:0] pointer3, pointer3_s, ch3_csr, ch3_txsz, ch3_adr0, ch3_adr1, ch3_am0, ch3_am1;
input [31:0] pointer4, pointer4_s, ch4_csr, ch4_txsz, ch4_adr0, ch4_adr1, ch4_am0, ch4_am1;
input [31:0] pointer5, pointer5_s, ch5_csr, ch5_txsz, ch5_adr0, ch5_adr1, ch5_am0, ch5_am1;
input [31:0] pointer6, pointer6_s, ch6_csr, ch6_txsz, ch6_adr0, ch6_adr1, ch6_am0, ch6_am1;
input [31:0] pointer7, pointer7_s, ch7_csr, ch7_txsz, ch7_adr0, ch7_adr1, ch7_am0, ch7_am1;
input [31:0] pointer8, pointer8_s, ch8_csr, ch8_txsz, ch8_adr0, ch8_adr1, ch8_am0, ch8_am1;
input [31:0] pointer9, pointer9_s, ch9_csr, ch9_txsz, ch9_adr0, ch9_adr1, ch9_am0, ch9_am1;
input [31:0] pointer10, pointer10_s, ch10_csr, ch10_txsz, ch10_adr0, ch10_adr1, ch10_am0, ch10_am1;
input [31:0] pointer11, pointer11_s, ch11_csr, ch11_txsz, ch11_adr0, ch11_adr1, ch11_am0, ch11_am1;
input [31:0] pointer12, pointer12_s, ch12_csr, ch12_txsz, ch12_adr0, ch12_adr1, ch12_am0, ch12_am1;
input [31:0] pointer13, pointer13_s, ch13_csr, ch13_txsz, ch13_adr0, ch13_adr1, ch13_am0, ch13_am1;
input [31:0] pointer14, pointer14_s, ch14_csr, ch14_txsz, ch14_adr0, ch14_adr1, ch14_am0, ch14_am1;
input [31:0] pointer15, pointer15_s, ch15_csr, ch15_txsz, ch15_adr0, ch15_adr1, ch15_am0, ch15_am1;
input [31:0] pointer16, pointer16_s, ch16_csr, ch16_txsz, ch16_adr0, ch16_adr1, ch16_am0, ch16_am1;
input [31:0] pointer17, pointer17_s, ch17_csr, ch17_txsz, ch17_adr0, ch17_adr1, ch17_am0, ch17_am1;
input [31:0] pointer18, pointer18_s, ch18_csr, ch18_txsz, ch18_adr0, ch18_adr1, ch18_am0, ch18_am1;
input [31:0] pointer19, pointer19_s, ch19_csr, ch19_txsz, ch19_adr0, ch19_adr1, ch19_am0, ch19_am1;
input [31:0] pointer20, pointer20_s, ch20_csr, ch20_txsz, ch20_adr0, ch20_adr1, ch20_am0, ch20_am1;
input [31:0] pointer21, pointer21_s, ch21_csr, ch21_txsz, ch21_adr0, ch21_adr1, ch21_am0, ch21_am1;
input [31:0] pointer22, pointer22_s, ch22_csr, ch22_txsz, ch22_adr0, ch22_adr1, ch22_am0, ch22_am1;
input [31:0] pointer23, pointer23_s, ch23_csr, ch23_txsz, ch23_adr0, ch23_adr1, ch23_am0, ch23_am1;
input [31:0] pointer24, pointer24_s, ch24_csr, ch24_txsz, ch24_adr0, ch24_adr1, ch24_am0, ch24_am1;
input [31:0] pointer25, pointer25_s, ch25_csr, ch25_txsz, ch25_adr0, ch25_adr1, ch25_am0, ch25_am1;
input [31:0] pointer26, pointer26_s, ch26_csr, ch26_txsz, ch26_adr0, ch26_adr1, ch26_am0, ch26_am1;
input [31:0] pointer27, pointer27_s, ch27_csr, ch27_txsz, ch27_adr0, ch27_adr1, ch27_am0, ch27_am1;
input [31:0] pointer28, pointer28_s, ch28_csr, ch28_txsz, ch28_adr0, ch28_adr1, ch28_am0, ch28_am1;
input [31:0] pointer29, pointer29_s, ch29_csr, ch29_txsz, ch29_adr0, ch29_adr1, ch29_am0, ch29_am1;
input [31:0] pointer30, pointer30_s, ch30_csr, ch30_txsz, ch30_adr0, ch30_adr1, ch30_am0, ch30_am1;
output [4:0] ch_sel; // Write Back Channel Select
output [30:0] ndnr; // Next Descriptor No Request
output de_start; // Start DMA Engine Indicator
output ndr; // Next Descriptor With Request (for current channel)
output [31:0] csr; // Selected Channel CSR
output [31:0] pointer; // LL Descriptor pointer
output [31:0] pointer_s; // LL Descriptor previous pointer
output [31:0] txsz; // Selected Channel Transfer Size
output [31:0] adr0, adr1; // Selected Channel Addresses
output [31:0] am0, am1; // Selected Channel Address Masks
input next_ch; // Indicates the DMA Engine is done
// with current transfer
input de_ack; // DMA engine ack output
input dma_busy;
////////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
reg [30:0] ack_o;
wire [30:0] valid; // Indicates which channel is valid
reg valid_sel;
reg [30:0] req_r; // Channel Request inputs
reg [30:0] ndr_r; // Next Descriptor Registered (and Request)
reg [30:0] ndnr; // Next Descriptor Registered (and Not Request)
wire [2:0] pri_out; // Highest unserviced priority
wire [2:0] pri0, pri1, pri2, pri3; // Channel Priorities
wire [2:0] pri4, pri5, pri6, pri7;
wire [2:0] pri8, pri9, pri10, pri11;
wire [2:0] pri12, pri13, pri14, pri15;
wire [2:0] pri16, pri17, pri18, pri19;
wire [2:0] pri20, pri21, pri22, pri23;
wire [2:0] pri24, pri25, pri26, pri27;
wire [2:0] pri28, pri29, pri30;
reg [4:0] ch_sel_d;
reg [4:0] ch_sel_r;
reg ndr;
reg next_start;
reg de_start_r;
reg [31:0] csr; // Selected Channel CSR
reg [31:0] pointer;
reg [31:0] pointer_s;
reg [31:0] txsz; // Selected Channel Transfer Size
reg [31:0] adr0, adr1; // Selected Channel Addresses
reg [31:0] am0, am1; // Selected Channel Address Masks
// Arbiter Request Inputs
wire [30:0] req_p0, req_p1, req_p2, req_p3;
wire [30:0] req_p4, req_p5, req_p6, req_p7;
wire [30:0] req_p8, req_p9, req_p10, req_p11;
wire [30:0] req_p12, req_p13, req_p14, req_p15;
wire [30:0] req_p16, req_p17, req_p18, req_p19;
wire [30:0] req_p20, req_p21, req_p22, req_p23;
wire [30:0] req_p24, req_p25, req_p26, req_p27;
wire [30:0] req_p28, req_p29, req_p30;
// Arbiter Grant Outputs
wire [4:0] gnt_p0_d, gnt_p1_d, gnt_p2_d, gnt_p3_d;
wire [4:0] gnt_p4_d, gnt_p5_d, gnt_p6_d, gnt_p7_d;
wire [4:0] gnt_p0, gnt_p1, gnt_p2, gnt_p3;
wire [4:0] gnt_p4, gnt_p5, gnt_p6, gnt_p7;
wire [4:0] gnt_p8, gnt_p9, gnt_p10, gnt_p11;
wire [4:0] gnt_p12, gnt_p13, gnt_p14, gnt_p15;
wire [4:0] gnt_p16, gnt_p17, gnt_p18, gnt_p19;
wire [4:0] gnt_p20, gnt_p21, gnt_p22, gnt_p23;
wire [4:0] gnt_p24, gnt_p25, gnt_p26, gnt_p27;
wire [4:0] gnt_p28, gnt_p29, gnt_p30;
////////////////////////////////////////////////////////////////////
//
// Aliases
//
assign pri0[0] = ch0_csr[13];
assign pri0[1] = (pri_sel == 2'd0) ? 1'b0 : ch0_csr[14];
assign pri0[2] = (pri_sel == 2'd2) ? ch0_csr[15] : 1'b0;
assign pri1[0] = ch1_csr[13];
assign pri1[1] = (pri_sel == 2'd0) ? 1'b0 : ch1_csr[14];
assign pri1[2] = (pri_sel == 2'd2) ? ch1_csr[15] : 1'b0;
assign pri2[0] = ch2_csr[13];
assign pri2[1] = (pri_sel == 2'd0) ? 1'b0 : ch2_csr[14];
assign pri2[2] = (pri_sel == 2'd2) ? ch2_csr[15] : 1'b0;
assign pri3[0] = ch3_csr[13];
assign pri3[1] = (pri_sel == 2'd0) ? 1'b0 : ch3_csr[14];
assign pri3[2] = (pri_sel == 2'd2) ? ch3_csr[15] : 1'b0;
assign pri4[0] = ch4_csr[13];
assign pri4[1] = (pri_sel == 2'd0) ? 1'b0 : ch4_csr[14];
assign pri4[2] = (pri_sel == 2'd2) ? ch4_csr[15] : 1'b0;
assign pri5[0] = ch5_csr[13];
assign pri5[1] = (pri_sel == 2'd0) ? 1'b0 : ch5_csr[14];
assign pri5[2] = (pri_sel == 2'd2) ? ch5_csr[15] : 1'b0;
assign pri6[0] = ch6_csr[13];
assign pri6[1] = (pri_sel == 2'd0) ? 1'b0 : ch6_csr[14];
assign pri6[2] = (pri_sel == 2'd2) ? ch6_csr[15] : 1'b0;
assign pri7[0] = ch7_csr[13];
assign pri7[1] = (pri_sel == 2'd0) ? 1'b0 : ch7_csr[14];
assign pri7[2] = (pri_sel == 2'd2) ? ch7_csr[15] : 1'b0;
assign pri8[0] = ch8_csr[13];
assign pri8[1] = (pri_sel == 2'd0) ? 1'b0 : ch8_csr[14];
assign pri8[2] = (pri_sel == 2'd2) ? ch8_csr[15] : 1'b0;
assign pri9[0] = ch9_csr[13];
assign pri9[1] = (pri_sel == 2'd0) ? 1'b0 : ch9_csr[14];
assign pri9[2] = (pri_sel == 2'd2) ? ch9_csr[15] : 1'b0;
assign pri10[0] = ch10_csr[13];
assign pri10[1] = (pri_sel == 2'd0) ? 1'b0 : ch10_csr[14];
assign pri10[2] = (pri_sel == 2'd2) ? ch10_csr[15] : 1'b0;
assign pri11[0] = ch11_csr[13];
assign pri11[1] = (pri_sel == 2'd0) ? 1'b0 : ch11_csr[14];
assign pri11[2] = (pri_sel == 2'd2) ? ch11_csr[15] : 1'b0;
assign pri12[0] = ch12_csr[13];
assign pri12[1] = (pri_sel == 2'd0) ? 1'b0 : ch12_csr[14];
assign pri12[2] = (pri_sel == 2'd2) ? ch12_csr[15] : 1'b0;
assign pri13[0] = ch13_csr[13];
assign pri13[1] = (pri_sel == 2'd0) ? 1'b0 : ch13_csr[14];
assign pri13[2] = (pri_sel == 2'd2) ? ch13_csr[15] : 1'b0;
assign pri14[0] = ch14_csr[13];
assign pri14[1] = (pri_sel == 2'd0) ? 1'b0 : ch14_csr[14];
assign pri14[2] = (pri_sel == 2'd2) ? ch14_csr[15] : 1'b0;
assign pri15[0] = ch15_csr[13];
assign pri15[1] = (pri_sel == 2'd0) ? 1'b0 : ch15_csr[14];
assign pri15[2] = (pri_sel == 2'd2) ? ch15_csr[15] : 1'b0;
assign pri16[0] = ch16_csr[13];
assign pri16[1] = (pri_sel == 2'd0) ? 1'b0 : ch16_csr[14];
assign pri16[2] = (pri_sel == 2'd2) ? ch16_csr[15] : 1'b0;
assign pri17[0] = ch17_csr[13];
assign pri17[1] = (pri_sel == 2'd0) ? 1'b0 : ch17_csr[14];
assign pri17[2] = (pri_sel == 2'd2) ? ch17_csr[15] : 1'b0;
assign pri18[0] = ch18_csr[13];
assign pri18[1] = (pri_sel == 2'd0) ? 1'b0 : ch18_csr[14];
assign pri18[2] = (pri_sel == 2'd2) ? ch18_csr[15] : 1'b0;
assign pri19[0] = ch19_csr[13];
assign pri19[1] = (pri_sel == 2'd0) ? 1'b0 : ch19_csr[14];
assign pri19[2] = (pri_sel == 2'd2) ? ch19_csr[15] : 1'b0;
assign pri20[0] = ch20_csr[13];
assign pri20[1] = (pri_sel == 2'd0) ? 1'b0 : ch20_csr[14];
assign pri20[2] = (pri_sel == 2'd2) ? ch20_csr[15] : 1'b0;
assign pri21[0] = ch21_csr[13];
assign pri21[1] = (pri_sel == 2'd0) ? 1'b0 : ch21_csr[14];
assign pri21[2] = (pri_sel == 2'd2) ? ch21_csr[15] : 1'b0;
assign pri22[0] = ch22_csr[13];
assign pri22[1] = (pri_sel == 2'd0) ? 1'b0 : ch22_csr[14];
assign pri22[2] = (pri_sel == 2'd2) ? ch22_csr[15] : 1'b0;
assign pri23[0] = ch23_csr[13];
assign pri23[1] = (pri_sel == 2'd0) ? 1'b0 : ch23_csr[14];
assign pri23[2] = (pri_sel == 2'd2) ? ch23_csr[15] : 1'b0;
assign pri24[0] = ch24_csr[13];
assign pri24[1] = (pri_sel == 2'd0) ? 1'b0 : ch24_csr[14];
assign pri24[2] = (pri_sel == 2'd2) ? ch24_csr[15] : 1'b0;
assign pri25[0] = ch25_csr[13];
assign pri25[1] = (pri_sel == 2'd0) ? 1'b0 : ch25_csr[14];
assign pri25[2] = (pri_sel == 2'd2) ? ch25_csr[15] : 1'b0;
assign pri26[0] = ch26_csr[13];
assign pri26[1] = (pri_sel == 2'd0) ? 1'b0 : ch26_csr[14];
assign pri26[2] = (pri_sel == 2'd2) ? ch26_csr[15] : 1'b0;
assign pri27[0] = ch27_csr[13];
assign pri27[1] = (pri_sel == 2'd0) ? 1'b0 : ch27_csr[14];
assign pri27[2] = (pri_sel == 2'd2) ? ch27_csr[15] : 1'b0;
assign pri28[0] = ch28_csr[13];
assign pri28[1] = (pri_sel == 2'd0) ? 1'b0 : ch28_csr[14];
assign pri28[2] = (pri_sel == 2'd2) ? ch28_csr[15] : 1'b0;
assign pri29[0] = ch29_csr[13];
assign pri29[1] = (pri_sel == 2'd0) ? 1'b0 : ch29_csr[14];
assign pri29[2] = (pri_sel == 2'd2) ? ch29_csr[15] : 1'b0;
assign pri30[0] = ch30_csr[13];
assign pri30[1] = (pri_sel == 2'd0) ? 1'b0 : ch30_csr[14];
assign pri30[2] = (pri_sel == 2'd2) ? ch30_csr[15] : 1'b0;
////////////////////////////////////////////////////////////////////
//
// Misc logic
//
// Chanel Valid flag
// The valid flag is asserted when the channel is enabled,
// and is either in "normal mode" (software control) or
// "hw handshake mode" (reqN control)
// validN = ch_enabled & (sw_mode | (hw_mode & reqN) )
always @(posedge clk)
req_r <= #1 req_i & ~ack_o;
assign valid[0] = ch0_conf[0] & ch0_csr[`WDMA_CH_EN] & (ch0_csr[`WDMA_MODE] ? (req_r[0] & !ack_o[0]) : 1'b1);
assign valid[1] = ch1_conf[0] & ch1_csr[`WDMA_CH_EN] & (ch1_csr[`WDMA_MODE] ? (req_r[1] & !ack_o[1]) : 1'b1);
assign valid[2] = ch2_conf[0] & ch2_csr[`WDMA_CH_EN] & (ch2_csr[`WDMA_MODE] ? (req_r[2] & !ack_o[2]) : 1'b1);
assign valid[3] = ch3_conf[0] & ch3_csr[`WDMA_CH_EN] & (ch3_csr[`WDMA_MODE] ? (req_r[3] & !ack_o[3]) : 1'b1);
assign valid[4] = ch4_conf[0] & ch4_csr[`WDMA_CH_EN] & (ch4_csr[`WDMA_MODE] ? (req_r[4] & !ack_o[4]) : 1'b1);
assign valid[5] = ch5_conf[0] & ch5_csr[`WDMA_CH_EN] & (ch5_csr[`WDMA_MODE] ? (req_r[5] & !ack_o[5]) : 1'b1);
assign valid[6] = ch6_conf[0] & ch6_csr[`WDMA_CH_EN] & (ch6_csr[`WDMA_MODE] ? (req_r[6] & !ack_o[6]) : 1'b1);
assign valid[7] = ch7_conf[0] & ch7_csr[`WDMA_CH_EN] & (ch7_csr[`WDMA_MODE] ? (req_r[7] & !ack_o[7]) : 1'b1);
assign valid[8] = ch8_conf[0] & ch8_csr[`WDMA_CH_EN] & (ch8_csr[`WDMA_MODE] ? (req_r[8] & !ack_o[8]) : 1'b1);
assign valid[9] = ch9_conf[0] & ch9_csr[`WDMA_CH_EN] & (ch9_csr[`WDMA_MODE] ? (req_r[9] & !ack_o[9]) : 1'b1);
assign valid[10] = ch10_conf[0] & ch10_csr[`WDMA_CH_EN] & (ch10_csr[`WDMA_MODE] ? (req_r[10] & !ack_o[10]) : 1'b1);
assign valid[11] = ch11_conf[0] & ch11_csr[`WDMA_CH_EN] & (ch11_csr[`WDMA_MODE] ? (req_r[11] & !ack_o[11]) : 1'b1);
assign valid[12] = ch12_conf[0] & ch12_csr[`WDMA_CH_EN] & (ch12_csr[`WDMA_MODE] ? (req_r[12] & !ack_o[12]) : 1'b1);
assign valid[13] = ch13_conf[0] & ch13_csr[`WDMA_CH_EN] & (ch13_csr[`WDMA_MODE] ? (req_r[13] & !ack_o[13]) : 1'b1);
assign valid[14] = ch14_conf[0] & ch14_csr[`WDMA_CH_EN] & (ch14_csr[`WDMA_MODE] ? (req_r[14] & !ack_o[14]) : 1'b1);
assign valid[15] = ch15_conf[0] & ch15_csr[`WDMA_CH_EN] & (ch15_csr[`WDMA_MODE] ? (req_r[15] & !ack_o[15]) : 1'b1);
assign valid[16] = ch16_conf[0] & ch16_csr[`WDMA_CH_EN] & (ch16_csr[`WDMA_MODE] ? (req_r[16] & !ack_o[16]) : 1'b1);
assign valid[17] = ch17_conf[0] & ch17_csr[`WDMA_CH_EN] & (ch17_csr[`WDMA_MODE] ? (req_r[17] & !ack_o[17]) : 1'b1);
assign valid[18] = ch18_conf[0] & ch18_csr[`WDMA_CH_EN] & (ch18_csr[`WDMA_MODE] ? (req_r[18] & !ack_o[18]) : 1'b1);
assign valid[19] = ch19_conf[0] & ch19_csr[`WDMA_CH_EN] & (ch19_csr[`WDMA_MODE] ? (req_r[19] & !ack_o[19]) : 1'b1);
assign valid[20] = ch20_conf[0] & ch20_csr[`WDMA_CH_EN] & (ch20_csr[`WDMA_MODE] ? (req_r[20] & !ack_o[20]) : 1'b1);
assign valid[21] = ch21_conf[0] & ch21_csr[`WDMA_CH_EN] & (ch21_csr[`WDMA_MODE] ? (req_r[21] & !ack_o[21]) : 1'b1);
assign valid[22] = ch22_conf[0] & ch22_csr[`WDMA_CH_EN] & (ch22_csr[`WDMA_MODE] ? (req_r[22] & !ack_o[22]) : 1'b1);
assign valid[23] = ch23_conf[0] & ch23_csr[`WDMA_CH_EN] & (ch23_csr[`WDMA_MODE] ? (req_r[23] & !ack_o[23]) : 1'b1);
assign valid[24] = ch24_conf[0] & ch24_csr[`WDMA_CH_EN] & (ch24_csr[`WDMA_MODE] ? (req_r[24] & !ack_o[24]) : 1'b1);
assign valid[25] = ch25_conf[0] & ch25_csr[`WDMA_CH_EN] & (ch25_csr[`WDMA_MODE] ? (req_r[25] & !ack_o[25]) : 1'b1);
assign valid[26] = ch26_conf[0] & ch26_csr[`WDMA_CH_EN] & (ch26_csr[`WDMA_MODE] ? (req_r[26] & !ack_o[26]) : 1'b1);
assign valid[27] = ch27_conf[0] & ch27_csr[`WDMA_CH_EN] & (ch27_csr[`WDMA_MODE] ? (req_r[27] & !ack_o[27]) : 1'b1);
assign valid[28] = ch28_conf[0] & ch28_csr[`WDMA_CH_EN] & (ch28_csr[`WDMA_MODE] ? (req_r[28] & !ack_o[28]) : 1'b1);
assign valid[29] = ch29_conf[0] & ch29_csr[`WDMA_CH_EN] & (ch29_csr[`WDMA_MODE] ? (req_r[29] & !ack_o[29]) : 1'b1);
assign valid[30] = ch30_conf[0] & ch30_csr[`WDMA_CH_EN] & (ch30_csr[`WDMA_MODE] ? (req_r[30] & !ack_o[30]) : 1'b1);
always @(posedge clk)
ndr_r <= #1 nd_i & req_i;
always @(posedge clk)
ndnr <= #1 nd_i & ~req_i;
// Start Signal for DMA engine
assign de_start = (valid_sel & !de_start_r ) | next_start;
always @(posedge clk)
de_start_r <= #1 valid_sel;
always @(posedge clk)
next_start <= #1 next_ch & valid_sel;
// Ack outputs for HW handshake mode
always @(posedge clk)
ack_o[0] <= #1 ch0_conf[0] & (ch_sel == 5'h0) & ch0_csr[`WDMA_MODE] & de_ack;
always @(posedge clk)
ack_o[1] <= #1 ch1_conf[0] & (ch_sel == 5'h1) & ch1_csr[`WDMA_MODE] & de_ack;
always @(posedge clk)
ack_o[2] <= #1 ch2_conf[0] & (ch_sel == 5'h2) & ch2_csr[`WDMA_MODE] & de_ack;
always @(posedge clk)
ack_o[3] <= #1 ch3_conf[0] & (ch_sel == 5'h3) & ch3_csr[`WDMA_MODE] & de_ack;
always @(posedge clk)
ack_o[4] <= #1 ch4_conf[0] & (ch_sel == 5'h4) & ch4_csr[`WDMA_MODE] & de_ack;
always @(posedge clk)
ack_o[5] <= #1 ch5_conf[0] & (ch_sel == 5'h5) & ch5_csr[`WDMA_MODE] & de_ack;
always @(posedge clk)
ack_o[6] <= #1 ch6_conf[0] & (ch_sel == 5'h6) & ch6_csr[`WDMA_MODE] & de_ack;
always @(posedge clk)
ack_o[7] <= #1 ch7_conf[0] & (ch_sel == 5'h7) & ch7_csr[`WDMA_MODE] & de_ack;
always @(posedge clk)
ack_o[8] <= #1 ch8_conf[0] & (ch_sel == 5'h8) & ch8_csr[`WDMA_MODE] & de_ack;
always @(posedge clk)
ack_o[9] <= #1 ch9_conf[0] & (ch_sel == 5'h9) & ch9_csr[`WDMA_MODE] & de_ack;
always @(posedge clk)
ack_o[10] <= #1 ch10_conf[0] & (ch_sel == 5'ha) & ch10_csr[`WDMA_MODE] & de_ack;
always @(posedge clk)
ack_o[11] <= #1 ch11_conf[0] & (ch_sel == 5'hb) & ch11_csr[`WDMA_MODE] & de_ack;
always @(posedge clk)
ack_o[12] <= #1 ch12_conf[0] & (ch_sel == 5'hc) & ch12_csr[`WDMA_MODE] & de_ack;
always @(posedge clk)
ack_o[13] <= #1 ch13_conf[0] & (ch_sel == 5'hd) & ch13_csr[`WDMA_MODE] & de_ack;
always @(posedge clk)
ack_o[14] <= #1 ch14_conf[0] & (ch_sel == 5'he) & ch14_csr[`WDMA_MODE] & de_ack;
always @(posedge clk)
ack_o[15] <= #1 ch15_conf[0] & (ch_sel == 5'hf) & ch15_csr[`WDMA_MODE] & de_ack;
always @(posedge clk)
ack_o[16] <= #1 ch16_conf[0] & (ch_sel == 5'h10) & ch16_csr[`WDMA_MODE] & de_ack;
always @(posedge clk)
ack_o[17] <= #1 ch17_conf[0] & (ch_sel == 5'h11) & ch17_csr[`WDMA_MODE] & de_ack;
always @(posedge clk)
ack_o[18] <= #1 ch18_conf[0] & (ch_sel == 5'h12) & ch18_csr[`WDMA_MODE] & de_ack;
always @(posedge clk)
ack_o[19] <= #1 ch19_conf[0] & (ch_sel == 5'h13) & ch19_csr[`WDMA_MODE] & de_ack;
always @(posedge clk)
ack_o[20] <= #1 ch20_conf[0] & (ch_sel == 5'h14) & ch20_csr[`WDMA_MODE] & de_ack;
always @(posedge clk)
ack_o[21] <= #1 ch21_conf[0] & (ch_sel == 5'h15) & ch21_csr[`WDMA_MODE] & de_ack;
always @(posedge clk)
ack_o[22] <= #1 ch22_conf[0] & (ch_sel == 5'h16) & ch22_csr[`WDMA_MODE] & de_ack;
always @(posedge clk)
ack_o[23] <= #1 ch23_conf[0] & (ch_sel == 5'h17) & ch23_csr[`WDMA_MODE] & de_ack;
always @(posedge clk)
ack_o[24] <= #1 ch24_conf[0] & (ch_sel == 5'h18) & ch24_csr[`WDMA_MODE] & de_ack;
always @(posedge clk)
ack_o[25] <= #1 ch25_conf[0] & (ch_sel == 5'h19) & ch25_csr[`WDMA_MODE] & de_ack;
always @(posedge clk)
ack_o[26] <= #1 ch26_conf[0] & (ch_sel == 5'h1a) & ch26_csr[`WDMA_MODE] & de_ack;
always @(posedge clk)
ack_o[27] <= #1 ch27_conf[0] & (ch_sel == 5'h1b) & ch27_csr[`WDMA_MODE] & de_ack;
always @(posedge clk)
ack_o[28] <= #1 ch28_conf[0] & (ch_sel == 5'h1c) & ch28_csr[`WDMA_MODE] & de_ack;
always @(posedge clk)
ack_o[29] <= #1 ch29_conf[0] & (ch_sel == 5'h1d) & ch29_csr[`WDMA_MODE] & de_ack;
always @(posedge clk)
ack_o[30] <= #1 ch30_conf[0] & (ch_sel == 5'h1e) & ch30_csr[`WDMA_MODE] & de_ack;
// Channel Select
always @(posedge clk or negedge rst)
if(!rst) ch_sel_r <= #1 0;
else
if(de_start) ch_sel_r <= #1 ch_sel_d;
assign ch_sel = !dma_busy ? ch_sel_d : ch_sel_r;
////////////////////////////////////////////////////////////////////
//
// Select Registers based on arbiter (and priority) outputs
//
always @(ch_sel or valid)
case(ch_sel) // synopsys parallel_case full_case
5'h0: valid_sel = valid[0];
5'h1: valid_sel = valid[1];
5'h2: valid_sel = valid[2];
5'h3: valid_sel = valid[3];
5'h4: valid_sel = valid[4];
5'h5: valid_sel = valid[5];
5'h6: valid_sel = valid[6];
5'h7: valid_sel = valid[7];
5'h8: valid_sel = valid[8];
5'h9: valid_sel = valid[9];
5'ha: valid_sel = valid[10];
5'hb: valid_sel = valid[11];
5'hc: valid_sel = valid[12];
5'hd: valid_sel = valid[13];
5'he: valid_sel = valid[14];
5'hf: valid_sel = valid[15];
5'h10: valid_sel = valid[16];
5'h11: valid_sel = valid[17];
5'h12: valid_sel = valid[18];
5'h13: valid_sel = valid[19];
5'h14: valid_sel = valid[20];
5'h15: valid_sel = valid[21];
5'h16: valid_sel = valid[22];
5'h17: valid_sel = valid[23];
5'h18: valid_sel = valid[24];
5'h19: valid_sel = valid[25];
5'h1a: valid_sel = valid[26];
5'h1b: valid_sel = valid[27];
5'h1c: valid_sel = valid[28];
5'h1d: valid_sel = valid[29];
5'h1e: valid_sel = valid[30];
endcase
always @(ch_sel or ndr_r)
case(ch_sel) // synopsys parallel_case full_case
5'h0: ndr = ndr_r[0];
5'h1: ndr = ndr_r[1];
5'h2: ndr = ndr_r[2];
5'h3: ndr = ndr_r[3];
5'h4: ndr = ndr_r[4];
5'h5: ndr = ndr_r[5];
5'h6: ndr = ndr_r[6];
5'h7: ndr = ndr_r[7];
5'h8: ndr = ndr_r[8];
5'h9: ndr = ndr_r[9];
5'ha: ndr = ndr_r[10];
5'hb: ndr = ndr_r[11];
5'hc: ndr = ndr_r[12];
5'hd: ndr = ndr_r[13];
5'he: ndr = ndr_r[14];
5'hf: ndr = ndr_r[15];
5'h10: ndr = ndr_r[16];
5'h11: ndr = ndr_r[17];
5'h12: ndr = ndr_r[18];
5'h13: ndr = ndr_r[19];
5'h14: ndr = ndr_r[20];
5'h15: ndr = ndr_r[21];
5'h16: ndr = ndr_r[22];
5'h17: ndr = ndr_r[23];
5'h18: ndr = ndr_r[24];
5'h19: ndr = ndr_r[25];
5'h1a: ndr = ndr_r[26];
5'h1b: ndr = ndr_r[27];
5'h1c: ndr = ndr_r[28];
5'h1d: ndr = ndr_r[29];
5'h1e: ndr = ndr_r[30];
endcase
always @(ch_sel or pointer0 or pointer1 or pointer2 or pointer3 or pointer4
or pointer5 or pointer6 or pointer7 or pointer8 or pointer9
or pointer10 or pointer11 or pointer12 or pointer13 or pointer14
or pointer15 or pointer16 or pointer17 or pointer18 or pointer19
or pointer20 or pointer21 or pointer22 or pointer23 or pointer24
or pointer25 or pointer26 or pointer27 or pointer28 or pointer29
or pointer30 )
case(ch_sel) // synopsys parallel_case full_case
5'h0: pointer = pointer0;
5'h1: pointer = pointer1;
5'h2: pointer = pointer2;
5'h3: pointer = pointer3;
5'h4: pointer = pointer4;
5'h5: pointer = pointer5;
5'h6: pointer = pointer6;
5'h7: pointer = pointer7;
5'h8: pointer = pointer8;
5'h9: pointer = pointer9;
5'ha: pointer = pointer10;
5'hb: pointer = pointer11;
5'hc: pointer = pointer12;
5'hd: pointer = pointer13;
5'he: pointer = pointer14;
5'hf: pointer = pointer15;
5'h10: pointer = pointer16;
5'h11: pointer = pointer17;
5'h12: pointer = pointer18;
5'h13: pointer = pointer19;
5'h14: pointer = pointer20;
5'h15: pointer = pointer21;
5'h16: pointer = pointer22;
5'h17: pointer = pointer23;
5'h18: pointer = pointer24;
5'h19: pointer = pointer25;
5'h1a: pointer = pointer26;
5'h1b: pointer = pointer27;
5'h1c: pointer = pointer28;
5'h1d: pointer = pointer29;
5'h1e: pointer = pointer30;
endcase
always @(ch_sel or pointer0_s or pointer1_s or pointer2_s or pointer3_s or pointer4_s
or pointer5_s or pointer6_s or pointer7_s or pointer8_s or pointer9_s
or pointer10_s or pointer11_s or pointer12_s or pointer13_s or pointer14_s
or pointer15_s or pointer16_s or pointer17_s or pointer18_s or pointer19_s
or pointer20_s or pointer21_s or pointer22_s or pointer23_s or pointer24_s
or pointer25_s or pointer26_s or pointer27_s or pointer28_s or pointer29_s
or pointer30_s )
case(ch_sel) // synopsys parallel_case full_case
5'h0: pointer_s = pointer0_s;
5'h1: pointer_s = pointer1_s;
5'h2: pointer_s = pointer2_s;
5'h3: pointer_s = pointer3_s;
5'h4: pointer_s = pointer4_s;
5'h5: pointer_s = pointer5_s;
5'h6: pointer_s = pointer6_s;
5'h7: pointer_s = pointer7_s;
5'h8: pointer_s = pointer8_s;
5'h9: pointer_s = pointer9_s;
5'ha: pointer_s = pointer10_s;
5'hb: pointer_s = pointer11_s;
5'hc: pointer_s = pointer12_s;
5'hd: pointer_s = pointer13_s;
5'he: pointer_s = pointer14_s;
5'hf: pointer_s = pointer15_s;
5'h10: pointer_s = pointer16_s;
5'h11: pointer_s = pointer17_s;
5'h12: pointer_s = pointer18_s;
5'h13: pointer_s = pointer19_s;
5'h14: pointer_s = pointer20_s;
5'h15: pointer_s = pointer21_s;
5'h16: pointer_s = pointer22_s;
5'h17: pointer_s = pointer23_s;
5'h18: pointer_s = pointer24_s;
5'h19: pointer_s = pointer25_s;
5'h1a: pointer_s = pointer26_s;
5'h1b: pointer_s = pointer27_s;
5'h1c: pointer_s = pointer28_s;
5'h1d: pointer_s = pointer29_s;
5'h1e: pointer_s = pointer30_s;
endcase
always @(ch_sel or ch0_csr or ch1_csr or ch2_csr or ch3_csr or ch4_csr
or ch5_csr or ch6_csr or ch7_csr or ch8_csr or ch9_csr
or ch10_csr or ch11_csr or ch12_csr or ch13_csr or ch14_csr
or ch15_csr or ch16_csr or ch17_csr or ch18_csr or ch19_csr
or ch20_csr or ch21_csr or ch22_csr or ch23_csr or ch24_csr
or ch25_csr or ch26_csr or ch27_csr or ch28_csr or ch29_csr
or ch30_csr )
case(ch_sel) // synopsys parallel_case full_case
5'h0: csr = ch0_csr;
5'h1: csr = ch1_csr;
5'h2: csr = ch2_csr;
5'h3: csr = ch3_csr;
5'h4: csr = ch4_csr;
5'h5: csr = ch5_csr;
5'h6: csr = ch6_csr;
5'h7: csr = ch7_csr;
5'h8: csr = ch8_csr;
5'h9: csr = ch9_csr;
5'ha: csr = ch10_csr;
5'hb: csr = ch11_csr;
5'hc: csr = ch12_csr;
5'hd: csr = ch13_csr;
5'he: csr = ch14_csr;
5'hf: csr = ch15_csr;
5'h10: csr = ch16_csr;
5'h11: csr = ch17_csr;
5'h12: csr = ch18_csr;
5'h13: csr = ch19_csr;
5'h14: csr = ch20_csr;
5'h15: csr = ch21_csr;
5'h16: csr = ch22_csr;
5'h17: csr = ch23_csr;
5'h18: csr = ch24_csr;
5'h19: csr = ch25_csr;
5'h1a: csr = ch26_csr;
5'h1b: csr = ch27_csr;
5'h1c: csr = ch28_csr;
5'h1d: csr = ch29_csr;
5'h1e: csr = ch30_csr;
endcase
always @(ch_sel or ch0_txsz or ch1_txsz or ch2_txsz or ch3_txsz or ch4_txsz
or ch5_txsz or ch6_txsz or ch7_txsz or ch8_txsz or ch9_txsz
or ch10_txsz or ch11_txsz or ch12_txsz or ch13_txsz or ch14_txsz
or ch15_txsz or ch16_txsz or ch17_txsz or ch18_txsz or ch19_txsz
or ch20_txsz or ch21_txsz or ch22_txsz or ch23_txsz or ch24_txsz
or ch25_txsz or ch26_txsz or ch27_txsz or ch28_txsz or ch29_txsz
or ch30_txsz )
case(ch_sel) // synopsys parallel_case full_case
5'h0: txsz = ch0_txsz;
5'h1: txsz = ch1_txsz;
5'h2: txsz = ch2_txsz;
5'h3: txsz = ch3_txsz;
5'h4: txsz = ch4_txsz;
5'h5: txsz = ch5_txsz;
5'h6: txsz = ch6_txsz;
5'h7: txsz = ch7_txsz;
5'h8: txsz = ch8_txsz;
5'h9: txsz = ch9_txsz;
5'ha: txsz = ch10_txsz;
5'hb: txsz = ch11_txsz;
5'hc: txsz = ch12_txsz;
5'hd: txsz = ch13_txsz;
5'he: txsz = ch14_txsz;
5'hf: txsz = ch15_txsz;
5'h10: txsz = ch16_txsz;
5'h11: txsz = ch17_txsz;
5'h12: txsz = ch18_txsz;
5'h13: txsz = ch19_txsz;
5'h14: txsz = ch20_txsz;
5'h15: txsz = ch21_txsz;
5'h16: txsz = ch22_txsz;
5'h17: txsz = ch23_txsz;
5'h18: txsz = ch24_txsz;
5'h19: txsz = ch25_txsz;
5'h1a: txsz = ch26_txsz;
5'h1b: txsz = ch27_txsz;
5'h1c: txsz = ch28_txsz;
5'h1d: txsz = ch29_txsz;
5'h1e: txsz = ch30_txsz;
endcase
always @(ch_sel or ch0_adr0 or ch1_adr0 or ch2_adr0 or ch3_adr0 or ch4_adr0
or ch5_adr0 or ch6_adr0 or ch7_adr0 or ch8_adr0 or ch9_adr0
or ch10_adr0 or ch11_adr0 or ch12_adr0 or ch13_adr0 or ch14_adr0
or ch15_adr0 or ch16_adr0 or ch17_adr0 or ch18_adr0 or ch19_adr0
or ch20_adr0 or ch21_adr0 or ch22_adr0 or ch23_adr0 or ch24_adr0
or ch25_adr0 or ch26_adr0 or ch27_adr0 or ch28_adr0 or ch29_adr0
or ch30_adr0 )
case(ch_sel) // synopsys parallel_case full_case
5'h0: adr0 = ch0_adr0;
5'h1: adr0 = ch1_adr0;
5'h2: adr0 = ch2_adr0;
5'h3: adr0 = ch3_adr0;
5'h4: adr0 = ch4_adr0;
5'h5: adr0 = ch5_adr0;
5'h6: adr0 = ch6_adr0;
5'h7: adr0 = ch7_adr0;
5'h8: adr0 = ch8_adr0;
5'h9: adr0 = ch9_adr0;
5'ha: adr0 = ch10_adr0;
5'hb: adr0 = ch11_adr0;
5'hc: adr0 = ch12_adr0;
5'hd: adr0 = ch13_adr0;
5'he: adr0 = ch14_adr0;
5'hf: adr0 = ch15_adr0;
5'h10: adr0 = ch16_adr0;
5'h11: adr0 = ch17_adr0;
5'h12: adr0 = ch18_adr0;
5'h13: adr0 = ch19_adr0;
5'h14: adr0 = ch20_adr0;
5'h15: adr0 = ch21_adr0;
5'h16: adr0 = ch22_adr0;
5'h17: adr0 = ch23_adr0;
5'h18: adr0 = ch24_adr0;
5'h19: adr0 = ch25_adr0;
5'h1a: adr0 = ch26_adr0;
5'h1b: adr0 = ch27_adr0;
5'h1c: adr0 = ch28_adr0;
5'h1d: adr0 = ch29_adr0;
5'h1e: adr0 = ch30_adr0;
endcase
always @(ch_sel or ch0_adr1 or ch1_adr1 or ch2_adr1 or ch3_adr1 or ch4_adr1
or ch5_adr1 or ch6_adr1 or ch7_adr1 or ch8_adr1 or ch9_adr1
or ch10_adr1 or ch11_adr1 or ch12_adr1 or ch13_adr1 or ch14_adr1
or ch15_adr1 or ch16_adr1 or ch17_adr1 or ch18_adr1 or ch19_adr1
or ch20_adr1 or ch21_adr1 or ch22_adr1 or ch23_adr1 or ch24_adr1
or ch25_adr1 or ch26_adr1 or ch27_adr1 or ch28_adr1 or ch29_adr1
or ch30_adr1 )
case(ch_sel) // synopsys parallel_case full_case
5'h0: adr1 = ch0_adr1;
5'h1: adr1 = ch1_adr1;
5'h2: adr1 = ch2_adr1;
5'h3: adr1 = ch3_adr1;
5'h4: adr1 = ch4_adr1;
5'h5: adr1 = ch5_adr1;
5'h6: adr1 = ch6_adr1;
5'h7: adr1 = ch7_adr1;
5'h8: adr1 = ch8_adr1;
5'h9: adr1 = ch9_adr1;
5'ha: adr1 = ch10_adr1;
5'hb: adr1 = ch11_adr1;
5'hc: adr1 = ch12_adr1;
5'hd: adr1 = ch13_adr1;
5'he: adr1 = ch14_adr1;
5'hf: adr1 = ch15_adr1;
5'h10: adr1 = ch16_adr1;
5'h11: adr1 = ch17_adr1;
5'h12: adr1 = ch18_adr1;
5'h13: adr1 = ch19_adr1;
5'h14: adr1 = ch20_adr1;
5'h15: adr1 = ch21_adr1;
5'h16: adr1 = ch22_adr1;
5'h17: adr1 = ch23_adr1;
5'h18: adr1 = ch24_adr1;
5'h19: adr1 = ch25_adr1;
5'h1a: adr1 = ch26_adr1;
5'h1b: adr1 = ch27_adr1;
5'h1c: adr1 = ch28_adr1;
5'h1d: adr1 = ch29_adr1;
5'h1e: adr1 = ch30_adr1;
endcase
always @(ch_sel or ch0_am0 or ch1_am0 or ch2_am0 or ch3_am0 or ch4_am0
or ch5_am0 or ch6_am0 or ch7_am0 or ch8_am0 or ch9_am0
or ch10_am0 or ch11_am0 or ch12_am0 or ch13_am0 or ch14_am0
or ch15_am0 or ch16_am0 or ch17_am0 or ch18_am0 or ch19_am0
or ch20_am0 or ch21_am0 or ch22_am0 or ch23_am0 or ch24_am0
or ch25_am0 or ch26_am0 or ch27_am0 or ch28_am0 or ch29_am0
or ch30_am0 )
case(ch_sel) // synopsys parallel_case full_case
5'h0: am0 = ch0_am0;
5'h1: am0 = ch1_am0;
5'h2: am0 = ch2_am0;
5'h3: am0 = ch3_am0;
5'h4: am0 = ch4_am0;
5'h5: am0 = ch5_am0;
5'h6: am0 = ch6_am0;
5'h7: am0 = ch7_am0;
5'h8: am0 = ch8_am0;
5'h9: am0 = ch9_am0;
5'ha: am0 = ch10_am0;
5'hb: am0 = ch11_am0;
5'hc: am0 = ch12_am0;
5'hd: am0 = ch13_am0;
5'he: am0 = ch14_am0;
5'hf: am0 = ch15_am0;
5'h10: am0 = ch16_am0;
5'h11: am0 = ch17_am0;
5'h12: am0 = ch18_am0;
5'h13: am0 = ch19_am0;
5'h14: am0 = ch20_am0;
5'h15: am0 = ch21_am0;
5'h16: am0 = ch22_am0;
5'h17: am0 = ch23_am0;
5'h18: am0 = ch24_am0;
5'h19: am0 = ch25_am0;
5'h1a: am0 = ch26_am0;
5'h1b: am0 = ch27_am0;
5'h1c: am0 = ch28_am0;
5'h1d: am0 = ch29_am0;
5'h1e: am0 = ch30_am0;
endcase
always @(ch_sel or ch0_am1 or ch1_am1 or ch2_am1 or ch3_am1 or ch4_am1
or ch5_am1 or ch6_am1 or ch7_am1 or ch8_am1 or ch9_am1
or ch10_am1 or ch11_am1 or ch12_am1 or ch13_am1 or ch14_am1
or ch15_am1 or ch16_am1 or ch17_am1 or ch18_am1 or ch19_am1
or ch20_am1 or ch21_am1 or ch22_am1 or ch23_am1 or ch24_am1
or ch25_am1 or ch26_am1 or ch27_am1 or ch28_am1 or ch29_am1
or ch30_am1 )
case(ch_sel) // synopsys parallel_case full_case
5'h0: am1 = ch0_am1;
5'h1: am1 = ch1_am1;
5'h2: am1 = ch2_am1;
5'h3: am1 = ch3_am1;
5'h4: am1 = ch4_am1;
5'h5: am1 = ch5_am1;
5'h6: am1 = ch6_am1;
5'h7: am1 = ch7_am1;
5'h8: am1 = ch8_am1;
5'h9: am1 = ch9_am1;
5'ha: am1 = ch10_am1;
5'hb: am1 = ch11_am1;
5'hc: am1 = ch12_am1;
5'hd: am1 = ch13_am1;
5'he: am1 = ch14_am1;
5'hf: am1 = ch15_am1;
5'h10: am1 = ch16_am1;
5'h11: am1 = ch17_am1;
5'h12: am1 = ch18_am1;
5'h13: am1 = ch19_am1;
5'h14: am1 = ch20_am1;
5'h15: am1 = ch21_am1;
5'h16: am1 = ch22_am1;
5'h17: am1 = ch23_am1;
5'h18: am1 = ch24_am1;
5'h19: am1 = ch25_am1;
5'h1a: am1 = ch26_am1;
5'h1b: am1 = ch27_am1;
5'h1c: am1 = ch28_am1;
5'h1d: am1 = ch29_am1;
5'h1e: am1 = ch30_am1;
endcase
////////////////////////////////////////////////////////////////////
//
// Actual Chanel Arbiter and Priority Encoder
//
// Select the arbiter for current highest priority
always @(pri_out or gnt_p0 or gnt_p1 or gnt_p2 or gnt_p3 or gnt_p4
or gnt_p5 or gnt_p6 or gnt_p7 )
case(pri_out) // synopsys parallel_case full_case
3'h0: ch_sel_d = gnt_p0;
3'h1: ch_sel_d = gnt_p1;
3'h2: ch_sel_d = gnt_p2;
3'h3: ch_sel_d = gnt_p3;
3'h4: ch_sel_d = gnt_p4;
3'h5: ch_sel_d = gnt_p5;
3'h6: ch_sel_d = gnt_p6;
3'h7: ch_sel_d = gnt_p7;
endcase
// Priority Encoder
wb_dma_ch_pri_enc
#( pri_sel,
ch0_conf,
ch1_conf,
ch2_conf,
ch3_conf,
ch4_conf,
ch5_conf,
ch6_conf,
ch7_conf,
ch8_conf,
ch9_conf,
ch10_conf,
ch11_conf,
ch12_conf,
ch13_conf,
ch14_conf,
ch15_conf,
ch16_conf,
ch17_conf,
ch18_conf,
ch19_conf,
ch20_conf,
ch21_conf,
ch22_conf,
ch23_conf,
ch24_conf,
ch25_conf,
ch26_conf,
ch27_conf,
ch28_conf,
ch29_conf,
ch30_conf)
u0(
.clk( clk ),
.valid( valid ),
.pri0( pri0 ),
.pri1( pri1 ),
.pri2( pri2 ),
.pri3( pri3 ),
.pri4( pri4 ),
.pri5( pri5 ),
.pri6( pri6 ),
.pri7( pri7 ),
.pri8( pri8 ),
.pri9( pri9 ),
.pri10( pri10 ),
.pri11( pri11 ),
.pri12( pri12 ),
.pri13( pri13 ),
.pri14( pri14 ),
.pri15( pri15 ),
.pri16( pri16 ),
.pri17( pri17 ),
.pri18( pri18 ),
.pri19( pri19 ),
.pri20( pri20 ),
.pri21( pri21 ),
.pri22( pri22 ),
.pri23( pri23 ),
.pri24( pri24 ),
.pri25( pri25 ),
.pri26( pri26 ),
.pri27( pri27 ),
.pri28( pri28 ),
.pri29( pri29 ),
.pri30( pri30 ),
.pri_out( pri_out )
);
// Arbiter request lines
// Generate request depending on priority and valid bits
assign req_p0[0] = valid[0] & (pri0==3'h0);
assign req_p0[1] = valid[1] & (pri1==3'h0);
assign req_p0[2] = valid[2] & (pri2==3'h0);
assign req_p0[3] = valid[3] & (pri3==3'h0);
assign req_p0[4] = valid[4] & (pri4==3'h0);
assign req_p0[5] = valid[5] & (pri5==3'h0);
assign req_p0[6] = valid[6] & (pri6==3'h0);
assign req_p0[7] = valid[7] & (pri7==3'h0);
assign req_p0[8] = valid[8] & (pri8==3'h0);
assign req_p0[9] = valid[9] & (pri9==3'h0);
assign req_p0[10] = valid[10] & (pri10==3'h0);
assign req_p0[11] = valid[11] & (pri11==3'h0);
assign req_p0[12] = valid[12] & (pri12==3'h0);
assign req_p0[13] = valid[13] & (pri13==3'h0);
assign req_p0[14] = valid[14] & (pri14==3'h0);
assign req_p0[15] = valid[15] & (pri15==3'h0);
assign req_p0[16] = valid[16] & (pri16==3'h0);
assign req_p0[17] = valid[17] & (pri17==3'h0);
assign req_p0[18] = valid[18] & (pri18==3'h0);
assign req_p0[19] = valid[19] & (pri19==3'h0);
assign req_p0[20] = valid[20] & (pri20==3'h0);
assign req_p0[21] = valid[21] & (pri21==3'h0);
assign req_p0[22] = valid[22] & (pri22==3'h0);
assign req_p0[23] = valid[23] & (pri23==3'h0);
assign req_p0[24] = valid[24] & (pri24==3'h0);
assign req_p0[25] = valid[25] & (pri25==3'h0);
assign req_p0[26] = valid[26] & (pri26==3'h0);
assign req_p0[27] = valid[27] & (pri27==3'h0);
assign req_p0[28] = valid[28] & (pri28==3'h0);
assign req_p0[29] = valid[29] & (pri29==3'h0);
assign req_p0[30] = valid[30] & (pri30==3'h0);
assign req_p1[0] = valid[0] & (pri0==3'h1);
assign req_p1[1] = valid[1] & (pri1==3'h1);
assign req_p1[2] = valid[2] & (pri2==3'h1);
assign req_p1[3] = valid[3] & (pri3==3'h1);
assign req_p1[4] = valid[4] & (pri4==3'h1);
assign req_p1[5] = valid[5] & (pri5==3'h1);
assign req_p1[6] = valid[6] & (pri6==3'h1);
assign req_p1[7] = valid[7] & (pri7==3'h1);
assign req_p1[8] = valid[8] & (pri8==3'h1);
assign req_p1[9] = valid[9] & (pri9==3'h1);
assign req_p1[10] = valid[10] & (pri10==3'h1);
assign req_p1[11] = valid[11] & (pri11==3'h1);
assign req_p1[12] = valid[12] & (pri12==3'h1);
assign req_p1[13] = valid[13] & (pri13==3'h1);
assign req_p1[14] = valid[14] & (pri14==3'h1);
assign req_p1[15] = valid[15] & (pri15==3'h1);
assign req_p1[16] = valid[16] & (pri16==3'h1);
assign req_p1[17] = valid[17] & (pri17==3'h1);
assign req_p1[18] = valid[18] & (pri18==3'h1);
assign req_p1[19] = valid[19] & (pri19==3'h1);
assign req_p1[20] = valid[20] & (pri20==3'h1);
assign req_p1[21] = valid[21] & (pri21==3'h1);
assign req_p1[22] = valid[22] & (pri22==3'h1);
assign req_p1[23] = valid[23] & (pri23==3'h1);
assign req_p1[24] = valid[24] & (pri24==3'h1);
assign req_p1[25] = valid[25] & (pri25==3'h1);
assign req_p1[26] = valid[26] & (pri26==3'h1);
assign req_p1[27] = valid[27] & (pri27==3'h1);
assign req_p1[28] = valid[28] & (pri28==3'h1);
assign req_p1[29] = valid[29] & (pri29==3'h1);
assign req_p1[30] = valid[30] & (pri30==3'h1);
assign req_p2[0] = valid[0] & (pri0==3'h2);
assign req_p2[1] = valid[1] & (pri1==3'h2);
assign req_p2[2] = valid[2] & (pri2==3'h2);
assign req_p2[3] = valid[3] & (pri3==3'h2);
assign req_p2[4] = valid[4] & (pri4==3'h2);
assign req_p2[5] = valid[5] & (pri5==3'h2);
assign req_p2[6] = valid[6] & (pri6==3'h2);
assign req_p2[7] = valid[7] & (pri7==3'h2);
assign req_p2[8] = valid[8] & (pri8==3'h2);
assign req_p2[9] = valid[9] & (pri9==3'h2);
assign req_p2[10] = valid[10] & (pri10==3'h2);
assign req_p2[11] = valid[11] & (pri11==3'h2);
assign req_p2[12] = valid[12] & (pri12==3'h2);
assign req_p2[13] = valid[13] & (pri13==3'h2);
assign req_p2[14] = valid[14] & (pri14==3'h2);
assign req_p2[15] = valid[15] & (pri15==3'h2);
assign req_p2[16] = valid[16] & (pri16==3'h2);
assign req_p2[17] = valid[17] & (pri17==3'h2);
assign req_p2[18] = valid[18] & (pri18==3'h2);
assign req_p2[19] = valid[19] & (pri19==3'h2);
assign req_p2[20] = valid[20] & (pri20==3'h2);
assign req_p2[21] = valid[21] & (pri21==3'h2);
assign req_p2[22] = valid[22] & (pri22==3'h2);
assign req_p2[23] = valid[23] & (pri23==3'h2);
assign req_p2[24] = valid[24] & (pri24==3'h2);
assign req_p2[25] = valid[25] & (pri25==3'h2);
assign req_p2[26] = valid[26] & (pri26==3'h2);
assign req_p2[27] = valid[27] & (pri27==3'h2);
assign req_p2[28] = valid[28] & (pri28==3'h2);
assign req_p2[29] = valid[29] & (pri29==3'h2);
assign req_p2[30] = valid[30] & (pri30==3'h2);
assign req_p3[0] = valid[0] & (pri0==3'h3);
assign req_p3[1] = valid[1] & (pri1==3'h3);
assign req_p3[2] = valid[2] & (pri2==3'h3);
assign req_p3[3] = valid[3] & (pri3==3'h3);
assign req_p3[4] = valid[4] & (pri4==3'h3);
assign req_p3[5] = valid[5] & (pri5==3'h3);
assign req_p3[6] = valid[6] & (pri6==3'h3);
assign req_p3[7] = valid[7] & (pri7==3'h3);
assign req_p3[8] = valid[8] & (pri8==3'h3);
assign req_p3[9] = valid[9] & (pri9==3'h3);
assign req_p3[10] = valid[10] & (pri10==3'h3);
assign req_p3[11] = valid[11] & (pri11==3'h3);
assign req_p3[12] = valid[12] & (pri12==3'h3);
assign req_p3[13] = valid[13] & (pri13==3'h3);
assign req_p3[14] = valid[14] & (pri14==3'h3);
assign req_p3[15] = valid[15] & (pri15==3'h3);
assign req_p3[16] = valid[16] & (pri16==3'h3);
assign req_p3[17] = valid[17] & (pri17==3'h3);
assign req_p3[18] = valid[18] & (pri18==3'h3);
assign req_p3[19] = valid[19] & (pri19==3'h3);
assign req_p3[20] = valid[20] & (pri20==3'h3);
assign req_p3[21] = valid[21] & (pri21==3'h3);
assign req_p3[22] = valid[22] & (pri22==3'h3);
assign req_p3[23] = valid[23] & (pri23==3'h3);
assign req_p3[24] = valid[24] & (pri24==3'h3);
assign req_p3[25] = valid[25] & (pri25==3'h3);
assign req_p3[26] = valid[26] & (pri26==3'h3);
assign req_p3[27] = valid[27] & (pri27==3'h3);
assign req_p3[28] = valid[28] & (pri28==3'h3);
assign req_p3[29] = valid[29] & (pri29==3'h3);
assign req_p3[30] = valid[30] & (pri30==3'h3);
assign req_p4[0] = valid[0] & (pri0==3'h4);
assign req_p4[1] = valid[1] & (pri1==3'h4);
assign req_p4[2] = valid[2] & (pri2==3'h4);
assign req_p4[3] = valid[3] & (pri3==3'h4);
assign req_p4[4] = valid[4] & (pri4==3'h4);
assign req_p4[5] = valid[5] & (pri5==3'h4);
assign req_p4[6] = valid[6] & (pri6==3'h4);
assign req_p4[7] = valid[7] & (pri7==3'h4);
assign req_p4[8] = valid[8] & (pri8==3'h4);
assign req_p4[9] = valid[9] & (pri9==3'h4);
assign req_p4[10] = valid[10] & (pri10==3'h4);
assign req_p4[11] = valid[11] & (pri11==3'h4);
assign req_p4[12] = valid[12] & (pri12==3'h4);
assign req_p4[13] = valid[13] & (pri13==3'h4);
assign req_p4[14] = valid[14] & (pri14==3'h4);
assign req_p4[15] = valid[15] & (pri15==3'h4);
assign req_p4[16] = valid[16] & (pri16==3'h4);
assign req_p4[17] = valid[17] & (pri17==3'h4);
assign req_p4[18] = valid[18] & (pri18==3'h4);
assign req_p4[19] = valid[19] & (pri19==3'h4);
assign req_p4[20] = valid[20] & (pri20==3'h4);
assign req_p4[21] = valid[21] & (pri21==3'h4);
assign req_p4[22] = valid[22] & (pri22==3'h4);
assign req_p4[23] = valid[23] & (pri23==3'h4);
assign req_p4[24] = valid[24] & (pri24==3'h4);
assign req_p4[25] = valid[25] & (pri25==3'h4);
assign req_p4[26] = valid[26] & (pri26==3'h4);
assign req_p4[27] = valid[27] & (pri27==3'h4);
assign req_p4[28] = valid[28] & (pri28==3'h4);
assign req_p4[29] = valid[29] & (pri29==3'h4);
assign req_p4[30] = valid[30] & (pri30==3'h4);
assign req_p5[0] = valid[0] & (pri0==3'h5);
assign req_p5[1] = valid[1] & (pri1==3'h5);
assign req_p5[2] = valid[2] & (pri2==3'h5);
assign req_p5[3] = valid[3] & (pri3==3'h5);
assign req_p5[4] = valid[4] & (pri4==3'h5);
assign req_p5[5] = valid[5] & (pri5==3'h5);
assign req_p5[6] = valid[6] & (pri6==3'h5);
assign req_p5[7] = valid[7] & (pri7==3'h5);
assign req_p5[8] = valid[8] & (pri8==3'h5);
assign req_p5[9] = valid[9] & (pri9==3'h5);
assign req_p5[10] = valid[10] & (pri10==3'h5);
assign req_p5[11] = valid[11] & (pri11==3'h5);
assign req_p5[12] = valid[12] & (pri12==3'h5);
assign req_p5[13] = valid[13] & (pri13==3'h5);
assign req_p5[14] = valid[14] & (pri14==3'h5);
assign req_p5[15] = valid[15] & (pri15==3'h5);
assign req_p5[16] = valid[16] & (pri16==3'h5);
assign req_p5[17] = valid[17] & (pri17==3'h5);
assign req_p5[18] = valid[18] & (pri18==3'h5);
assign req_p5[19] = valid[19] & (pri19==3'h5);
assign req_p5[20] = valid[20] & (pri20==3'h5);
assign req_p5[21] = valid[21] & (pri21==3'h5);
assign req_p5[22] = valid[22] & (pri22==3'h5);
assign req_p5[23] = valid[23] & (pri23==3'h5);
assign req_p5[24] = valid[24] & (pri24==3'h5);
assign req_p5[25] = valid[25] & (pri25==3'h5);
assign req_p5[26] = valid[26] & (pri26==3'h5);
assign req_p5[27] = valid[27] & (pri27==3'h5);
assign req_p5[28] = valid[28] & (pri28==3'h5);
assign req_p5[29] = valid[29] & (pri29==3'h5);
assign req_p5[30] = valid[30] & (pri30==3'h5);
assign req_p6[0] = valid[0] & (pri0==3'h6);
assign req_p6[1] = valid[1] & (pri1==3'h6);
assign req_p6[2] = valid[2] & (pri2==3'h6);
assign req_p6[3] = valid[3] & (pri3==3'h6);
assign req_p6[4] = valid[4] & (pri4==3'h6);
assign req_p6[5] = valid[5] & (pri5==3'h6);
assign req_p6[6] = valid[6] & (pri6==3'h6);
assign req_p6[7] = valid[7] & (pri7==3'h6);
assign req_p6[8] = valid[8] & (pri8==3'h6);
assign req_p6[9] = valid[9] & (pri9==3'h6);
assign req_p6[10] = valid[10] & (pri10==3'h6);
assign req_p6[11] = valid[11] & (pri11==3'h6);
assign req_p6[12] = valid[12] & (pri12==3'h6);
assign req_p6[13] = valid[13] & (pri13==3'h6);
assign req_p6[14] = valid[14] & (pri14==3'h6);
assign req_p6[15] = valid[15] & (pri15==3'h6);
assign req_p6[16] = valid[16] & (pri16==3'h6);
assign req_p6[17] = valid[17] & (pri17==3'h6);
assign req_p6[18] = valid[18] & (pri18==3'h6);
assign req_p6[19] = valid[19] & (pri19==3'h6);
assign req_p6[20] = valid[20] & (pri20==3'h6);
assign req_p6[21] = valid[21] & (pri21==3'h6);
assign req_p6[22] = valid[22] & (pri22==3'h6);
assign req_p6[23] = valid[23] & (pri23==3'h6);
assign req_p6[24] = valid[24] & (pri24==3'h6);
assign req_p6[25] = valid[25] & (pri25==3'h6);
assign req_p6[26] = valid[26] & (pri26==3'h6);
assign req_p6[27] = valid[27] & (pri27==3'h6);
assign req_p6[28] = valid[28] & (pri28==3'h6);
assign req_p6[29] = valid[29] & (pri29==3'h6);
assign req_p6[30] = valid[30] & (pri30==3'h6);
assign req_p7[0] = valid[0] & (pri0==3'h7);
assign req_p7[1] = valid[1] & (pri1==3'h7);
assign req_p7[2] = valid[2] & (pri2==3'h7);
assign req_p7[3] = valid[3] & (pri3==3'h7);
assign req_p7[4] = valid[4] & (pri4==3'h7);
assign req_p7[5] = valid[5] & (pri5==3'h7);
assign req_p7[6] = valid[6] & (pri6==3'h7);
assign req_p7[7] = valid[7] & (pri7==3'h7);
assign req_p7[8] = valid[8] & (pri8==3'h7);
assign req_p7[9] = valid[9] & (pri9==3'h7);
assign req_p7[10] = valid[10] & (pri10==3'h7);
assign req_p7[11] = valid[11] & (pri11==3'h7);
assign req_p7[12] = valid[12] & (pri12==3'h7);
assign req_p7[13] = valid[13] & (pri13==3'h7);
assign req_p7[14] = valid[14] & (pri14==3'h7);
assign req_p7[15] = valid[15] & (pri15==3'h7);
assign req_p7[16] = valid[16] & (pri16==3'h7);
assign req_p7[17] = valid[17] & (pri17==3'h7);
assign req_p7[18] = valid[18] & (pri18==3'h7);
assign req_p7[19] = valid[19] & (pri19==3'h7);
assign req_p7[20] = valid[20] & (pri20==3'h7);
assign req_p7[21] = valid[21] & (pri21==3'h7);
assign req_p7[22] = valid[22] & (pri22==3'h7);
assign req_p7[23] = valid[23] & (pri23==3'h7);
assign req_p7[24] = valid[24] & (pri24==3'h7);
assign req_p7[25] = valid[25] & (pri25==3'h7);
assign req_p7[26] = valid[26] & (pri26==3'h7);
assign req_p7[27] = valid[27] & (pri27==3'h7);
assign req_p7[28] = valid[28] & (pri28==3'h7);
assign req_p7[29] = valid[29] & (pri29==3'h7);
assign req_p7[30] = valid[30] & (pri30==3'h7);
// RR Arbiter for priority 0
wb_dma_ch_arb u1(
.clk( clk ),
.rst( rst ),
.req( req_p0 ),
.gnt( gnt_p0_d ),
.advance( next_ch )
);
// RR Arbiter for priority 1
wb_dma_ch_arb u2(
.clk( clk ),
.rst( rst ),
.req( req_p1 ),
.gnt( gnt_p1_d ),
.advance( next_ch )
);
// RR Arbiter for priority 2
wb_dma_ch_arb u3(
.clk( clk ),
.rst( rst ),
.req( req_p2 ),
.gnt( gnt_p2_d ),
.advance( next_ch )
);
// RR Arbiter for priority 3
wb_dma_ch_arb u4(
.clk( clk ),
.rst( rst ),
.req( req_p3 ),
.gnt( gnt_p3_d ),
.advance( next_ch )
);
// RR Arbiter for priority 4
wb_dma_ch_arb u5(
.clk( clk ),
.rst( rst ),
.req( req_p4 ),
.gnt( gnt_p4_d ),
.advance( next_ch )
);
// RR Arbiter for priority 5
wb_dma_ch_arb u6(
.clk( clk ),
.rst( rst ),
.req( req_p5 ),
.gnt( gnt_p5_d ),
.advance( next_ch )
);
// RR Arbiter for priority 6
wb_dma_ch_arb u7(
.clk( clk ),
.rst( rst ),
.req( req_p6 ),
.gnt( gnt_p6_d ),
.advance( next_ch )
);
// RR Arbiter for priority 7
wb_dma_ch_arb u8(
.clk( clk ),
.rst( rst ),
.req( req_p7 ),
.gnt( gnt_p7_d ),
.advance( next_ch )
);
// Select grant based on number of priorities
assign gnt_p0 = gnt_p0_d;
assign gnt_p1 = gnt_p1_d;
assign gnt_p2 = (pri_sel==2'd0) ? 5'h0 : gnt_p2_d;
assign gnt_p3 = (pri_sel==2'd0) ? 5'h0 : gnt_p3_d;
assign gnt_p4 = (pri_sel==2'd2) ? gnt_p4_d : 5'h0;
assign gnt_p5 = (pri_sel==2'd2) ? gnt_p5_d : 5'h0;
assign gnt_p6 = (pri_sel==2'd2) ? gnt_p6_d : 5'h0;
assign gnt_p7 = (pri_sel==2'd2) ? gnt_p7_d : 5'h0;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Tecnológico de Costa Rica
// Engineer: Juan José Rojas Salazar
//
// Create Date: 30.07.2016 10:22:05
// Design Name:
// Module Name: FSM_C_CORDIC
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
//////////////////////////////////////////////////////////////////////////////////
module FSM_C_CORDIC(
//INPUTS
input wire CLK, //system clock
input wire RST_LN, //system reset
input wire ACK_ADD_SUBTX, //RECIBE SI LA SUMA EN FLOTANTE X SE EJECUTO
input wire ACK_ADD_SUBTY, //RECIBE SI LA SUMA EN FLOTANTE Y SE EJECUTO
input wire ACK_ADD_SUBTZ, //RECIBE SI LA SUMA EN FLOTANTE Z SE EJECUTO
input wire Begin_FSM_LN, //inicia la maquina de estados
input wire [4:0] CONT_ITER, //LLEVA LA CUENTA DE LA ITERACIONES
//OUTPUT SIGNALS
output reg RST, //REALIZA EL RESET DE LOS REGISTROS
output reg MS_1, //SELECCION DEL MUX 1
output reg EN_REG3, //ENABLE PARA EL REGISTRO 3 CON EL VALOR INICIAL DE T ESCALADO POR 16
output reg EN_REG4, //ENABLE PARA EL REG 4 DEL RESULTADO FINAL
output reg ADD_SUBT, //SELECCION DE OPERACION PARA EL ADD/SUBT FLOTANTE
output reg Begin_SUMX, //INICIA ADD/SUM FLOTANTE X
output reg Begin_SUMY, //INICIA ADD/SUM FLOTANTE Y
output reg Begin_SUMZ, //INICIA ADD/SUM FLOTANTE Z
output reg EN_REG1X, //ENABLE PARA EL REGISTRO X DE LA PRIMERA ETAPA
output reg EN_REG1Y, //ENABLE PARA EL REGISTRO Y DE LA PRIMERA ETAPA
output reg EN_REG1Z, //ENABLE PARA EL REGISTRO Z DE LA PRIMERA ETAPA
output reg MS_2, //SELECCION DEL MUX 2
output reg MS_3, //SELECCION DEL MUX 3
output reg EN_REG2, //ENABLE PARA EL REGISTRO CON LOS VALORES DESPLAZADOS DE LA SEGUNDA ETAPA
output reg CLK_CDIR, //CLK PARA EL CONTADOR DE ITERACIONES
output reg EN_REG2XYZ, //ENABLE PARA EL VALOR ANTERIOR DE XYZ DE SEGUNDA ETAPA
output reg ACK_LN, //ACK PARA SABER SI LA OPERACION LN YA SE REALIZO
//REGISTROS DE SELECTORES
output reg EN_ADDSUBT,
output reg EN_MS1,
output reg EN_MS2,
output reg EN_MS3
);
parameter [5:0] //se definen los estados que se utilizaran en la maquina
a = 6'd0,
b = 6'd1,
c = 6'd2,
d = 6'd3,
e = 6'd4,
f = 6'd5,
g = 6'd6,
h = 6'd7,
i = 6'd8,
j = 6'd9,
k = 6'd10,
l = 6'd11,
m = 6'd12,
n = 6'd13,
o = 6'd14,
p = 6'd15,
q = 6'd16,
r = 6'd17,
s = 6'd18,
t = 6'd19;
reg [5:0] state_reg, state_next ; //state registers declaration
always @(posedge CLK, posedge RST_LN)
if (RST_LN) begin
state_reg <= a;
end
else begin
state_reg <= state_next;
end
///
always @*
begin
state_next = state_reg;
EN_REG2 = 0;
EN_REG3 = 0;
EN_REG4 = 0;
EN_REG1X = 0;
EN_REG1Y = 0;
EN_REG1Z = 0;
EN_REG2XYZ = 0;
Begin_SUMX = 0;
Begin_SUMY = 0;
Begin_SUMZ = 0;
ACK_LN = 0;
CLK_CDIR = 0;
RST = 0;
MS_1 = 0;
MS_2 = 0;
MS_3 = 0;
ADD_SUBT = 0;
EN_ADDSUBT = 0;
EN_MS1 = 0;
EN_MS2 = 0;
EN_MS3 = 0;
//nuevos estados
case(state_reg)
a:
begin
if(Begin_FSM_LN)
begin
RST = 1;
state_next = b;
end
else
state_next = a;
end
b:
begin
MS_1 = 1;
EN_MS1 = 1;
MS_2 = 1;
EN_MS2 = 1;
MS_3 = 0;
EN_MS3 = 1;
ADD_SUBT = 0;
EN_ADDSUBT = 1;
state_next = c;
end
c:
begin
EN_REG3 = 1;
state_next = d;
end
d:
begin
Begin_SUMX = 1;
Begin_SUMY = 1;
state_next = e;
end
e:
begin
state_next = f;
end
f:
begin
if(ACK_ADD_SUBTX && ACK_ADD_SUBTY )
begin
EN_REG1X = 1;
EN_REG1Y = 1;
EN_REG1Z = 1;
MS_1 = 0;
EN_MS1 = 1;
MS_2 = 0;
EN_MS2 = 1;
state_next = g;
end
else
state_next = f;
end
g:
begin
EN_REG2 = 1;
state_next = h;
end
h:
begin
EN_REG2XYZ = 1;
state_next = i;
end
i:
begin
Begin_SUMX = 1;
Begin_SUMZ = 1;
CLK_CDIR = 1;
state_next = j;
end
j:
begin
state_next = k;
end
k:
begin
Begin_SUMY = 1;
if(ACK_ADD_SUBTX && ACK_ADD_SUBTZ)
begin
EN_REG1X = 1;
EN_REG1Z = 1;
state_next = l;
end
else
state_next = k;
end
l:
begin
if(ACK_ADD_SUBTY)
begin
EN_REG1Y = 1;
state_next = m;
end
else
state_next = l;
end
m:
begin
if(CONT_ITER == 5'b01111) //15 iteraciones
begin
MS_3 = 1;
EN_MS3 = 1;
ADD_SUBT = 0;
EN_ADDSUBT = 1;
state_next = n;
end
else
state_next = g;
end
n:
begin
Begin_SUMZ = 1;
state_next = o;
end
o:
begin
if(ACK_ADD_SUBTZ)
begin
EN_REG4 = 1;
state_next = p;
end
else
state_next = o;
end
p:
begin
ACK_LN = 1;
if(RST_LN)
begin
RST = 1;
state_next = a;
end
end
default:
state_next=a;
endcase
end
endmodule
|
//MIT License
//
//Copyright (c) 2017 tvelliott
//
//Permission is hereby granted, free of charge, to any person obtaining a copy
//of this software and associated documentation files (the "Software"), to deal
//in the Software without restriction, including without limitation the rights
//to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
//copies of the Software, and to permit persons to whom the Software is
//furnished to do so, subject to the following conditions:
//
//The above copyright notice and this permission notice shall be included in all
//copies or substantial portions of the Software.
//
//THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
//IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
//FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
//AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
//LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
//OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
//SOFTWARE.
module spi_master (
input clk,
input rst,
input miso,
output mosi,
output sck,
input start,
input[7:0] data_in,
output[7:0] data_out,
output busy,
output new_data
);
localparam CLK_DIV=3;
localparam IDLE = 3'd0,
TRANSFER = 3'd1;
reg [2:0] state;
reg [7:0] data;
reg [CLK_DIV-1:0] sck_q;
assign sck = (sck_q[CLK_DIV-1] && state!=IDLE);
reg mosi;
reg [2:0] ctr;
reg [7:0] data_out;
reg new_data;
reg busy;
always @(posedge clk) begin
if (!rst) begin
ctr <= 3'b0;
sck_q <= 3'h0;
mosi <= 1'b0;
state <= IDLE;
data_out <= 8'b0;
new_data <= 1'b0;
end else begin
case (state)
IDLE: begin
sck_q <= 3'h0;
ctr <= 3'b0;
if (start == 1'b1) begin
busy<=1'b1;
new_data <= 1'b0;
data <= data_in;
state <= TRANSFER;
end
end
TRANSFER: begin
sck_q <= sck_q + 1'b1;
case(sck_q)
3'b000: begin
end
3'b001: begin
end
3'b010: begin
mosi <= data[7];
end
3'b011: begin
end
3'b100: begin
end
3'b101: begin
end
3'b110: begin
data <= {data[6:0], miso};
end
3'b111: begin
ctr <= ctr + 1'b1;
if (ctr == 3'b111) begin
data_out <= data;
busy<=1'b0;
new_data <= 1'b1;
state <= IDLE;
end
end
endcase
end
default: begin
state <= IDLE;
end
endcase
end
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Thu Nov 3 18:41:51 2016
/////////////////////////////////////////////////////////////
module FPU_Interface2_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, begin_operation,
ack_operation, operation, region_flag, Data_1, Data_2, r_mode,
overflow_flag, underflow_flag, NaN_flag, operation_ready, op_result,
busy );
input [2:0] operation;
input [1:0] region_flag;
input [31:0] Data_1;
input [31:0] Data_2;
input [1:0] r_mode;
output [31:0] op_result;
input clk, rst, begin_operation, ack_operation;
output overflow_flag, underflow_flag, NaN_flag, operation_ready, busy;
wire NaN_reg, ready_add_subt, underflow_flag_mult, overflow_flag_addsubt,
underflow_flag_addsubt, FPSENCOS_d_ff3_sign_out,
FPSENCOS_d_ff1_operation_out, FPMULT_FSM_selector_C,
FPMULT_FSM_selector_A, FPMULT_FSM_add_overflow_flag, FPMULT_zero_flag,
FPADDSUB_OP_FLAG_SFG, FPADDSUB_SIGN_FLAG_SFG, FPADDSUB_SIGN_FLAG_NRM,
FPADDSUB_SIGN_FLAG_SHT1SHT2, FPADDSUB_ADD_OVRFLW_NRM2,
FPADDSUB_OP_FLAG_SHT2, FPADDSUB_SIGN_FLAG_SHT2,
FPADDSUB_bit_shift_SHT2, FPADDSUB_left_right_SHT2,
FPADDSUB_ADD_OVRFLW_NRM, FPADDSUB_OP_FLAG_SHT1,
FPADDSUB_SIGN_FLAG_SHT1, FPADDSUB_OP_FLAG_EXP, FPADDSUB_SIGN_FLAG_EXP,
FPADDSUB_intAS, FPADDSUB_Shift_reg_FLAGS_7_5,
FPADDSUB_Shift_reg_FLAGS_7_6, FPMULT_Exp_module_Overflow_flag_A,
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N23,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N22,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N21,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N20,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N19,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N18,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N17,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N16,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N15,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N14,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N13,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N12,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N11,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N10,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N9,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N8,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N7,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N6,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N5,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N4,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N3,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N2,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N1,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N0,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N25,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N24,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N23,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N22,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N21,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N20,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N19,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N18,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N17,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N16,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N15,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N14,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N13,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N12,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N11,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N10,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N9,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N8,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N7,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N6,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N5,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N4,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N3,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N2,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N1,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N0,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N23,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N22,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N21,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N20,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N19,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N18,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N17,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N16,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N15,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N14,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N13,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N12,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N11,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N10,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N9,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N8,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N7,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N6,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N5,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N4,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N3,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N2,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N1,
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N0, n1180, n1181, n1182,
n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192,
n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202,
n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212,
n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222,
n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232,
n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242,
n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252,
n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262,
n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272,
n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282,
n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292,
n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302,
n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312,
n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322,
n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332,
n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342,
n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352,
n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362,
n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372,
n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382,
n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392,
n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402,
n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411, n1412,
n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422,
n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432,
n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442,
n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452,
n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462,
n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472,
n1473, n1474, n1475, n1476, n1477, n1478, n1481, n1483, n1484, n1485,
n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495,
n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505,
n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515,
n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525,
n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535,
n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545,
n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555,
n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565,
n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575,
n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585,
n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595,
n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605,
n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615,
n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625,
n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635,
n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645,
n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655,
n1656, n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665,
n1666, n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675,
n1676, n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685,
n1686, n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695,
n1696, n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705,
n1706, n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715,
n1716, n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725,
n1726, n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735,
n1736, n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745,
n1746, n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755,
n1756, n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765,
n1766, n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775,
n1776, n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785,
n1786, n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795,
n1796, n1797, n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805,
n1806, n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815,
n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825,
n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835,
n1836, n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845,
n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855,
n1856, n1857, n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865,
n1866, n1867, n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875,
n1876, n1877, n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885,
n1886, n1887, n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895,
n1896, n1897, n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905,
n1906, n1907, n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915,
n1916, n1917, n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925,
n1926, n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935,
n1936, n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945,
n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955,
n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965,
n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975,
n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985,
n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995,
n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005,
n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015,
n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025,
n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035,
n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045,
n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055,
n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065,
n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075,
n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085,
n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095,
n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105,
n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115,
n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125,
n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135,
n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145,
n2146, n2147, n2148, n2149, n2191, DP_OP_454J200_123_2743_n252,
DP_OP_454J200_123_2743_n251, DP_OP_454J200_123_2743_n250,
DP_OP_454J200_123_2743_n249, DP_OP_454J200_123_2743_n248,
DP_OP_454J200_123_2743_n247, DP_OP_454J200_123_2743_n246,
DP_OP_454J200_123_2743_n245, DP_OP_454J200_123_2743_n240,
DP_OP_454J200_123_2743_n236, DP_OP_454J200_123_2743_n235,
DP_OP_454J200_123_2743_n234, DP_OP_454J200_123_2743_n233,
DP_OP_454J200_123_2743_n232, DP_OP_454J200_123_2743_n231,
DP_OP_454J200_123_2743_n227, DP_OP_454J200_123_2743_n223,
DP_OP_454J200_123_2743_n219, DP_OP_454J200_123_2743_n218,
DP_OP_454J200_123_2743_n217, DP_OP_454J200_123_2743_n216,
DP_OP_454J200_123_2743_n215, DP_OP_454J200_123_2743_n214,
DP_OP_454J200_123_2743_n213, DP_OP_454J200_123_2743_n212,
DP_OP_454J200_123_2743_n210, DP_OP_454J200_123_2743_n204,
DP_OP_454J200_123_2743_n203, DP_OP_454J200_123_2743_n202,
DP_OP_454J200_123_2743_n200, DP_OP_454J200_123_2743_n199,
DP_OP_454J200_123_2743_n198, DP_OP_454J200_123_2743_n197,
DP_OP_454J200_123_2743_n196, DP_OP_454J200_123_2743_n195,
DP_OP_454J200_123_2743_n191, DP_OP_454J200_123_2743_n188,
DP_OP_454J200_123_2743_n187, DP_OP_454J200_123_2743_n186,
DP_OP_454J200_123_2743_n185, DP_OP_454J200_123_2743_n184,
DP_OP_454J200_123_2743_n183, DP_OP_454J200_123_2743_n182,
DP_OP_454J200_123_2743_n181, DP_OP_454J200_123_2743_n180,
DP_OP_454J200_123_2743_n179, DP_OP_454J200_123_2743_n178,
DP_OP_454J200_123_2743_n177, DP_OP_454J200_123_2743_n176,
DP_OP_454J200_123_2743_n175, DP_OP_454J200_123_2743_n172,
DP_OP_454J200_123_2743_n171, DP_OP_454J200_123_2743_n170,
DP_OP_454J200_123_2743_n169, DP_OP_454J200_123_2743_n168,
DP_OP_454J200_123_2743_n167, DP_OP_454J200_123_2743_n166,
DP_OP_454J200_123_2743_n165, DP_OP_454J200_123_2743_n164,
DP_OP_454J200_123_2743_n163, DP_OP_454J200_123_2743_n162,
DP_OP_454J200_123_2743_n156, DP_OP_454J200_123_2743_n155,
DP_OP_454J200_123_2743_n148, DP_OP_454J200_123_2743_n145,
DP_OP_454J200_123_2743_n144, DP_OP_454J200_123_2743_n143,
DP_OP_454J200_123_2743_n142, DP_OP_454J200_123_2743_n140,
DP_OP_454J200_123_2743_n139, DP_OP_454J200_123_2743_n138,
DP_OP_454J200_123_2743_n137, DP_OP_454J200_123_2743_n135,
DP_OP_454J200_123_2743_n134, DP_OP_454J200_123_2743_n133,
DP_OP_454J200_123_2743_n131, DP_OP_454J200_123_2743_n130,
DP_OP_454J200_123_2743_n129, DP_OP_454J200_123_2743_n128,
DP_OP_454J200_123_2743_n127, DP_OP_454J200_123_2743_n126,
DP_OP_454J200_123_2743_n125, DP_OP_454J200_123_2743_n124,
DP_OP_454J200_123_2743_n123, DP_OP_454J200_123_2743_n122,
DP_OP_454J200_123_2743_n121, DP_OP_454J200_123_2743_n120,
DP_OP_454J200_123_2743_n119, DP_OP_454J200_123_2743_n117,
DP_OP_454J200_123_2743_n116, DP_OP_454J200_123_2743_n115,
DP_OP_454J200_123_2743_n114, DP_OP_454J200_123_2743_n113,
DP_OP_454J200_123_2743_n112, DP_OP_454J200_123_2743_n111,
DP_OP_454J200_123_2743_n109, DP_OP_454J200_123_2743_n108,
DP_OP_454J200_123_2743_n107, DP_OP_454J200_123_2743_n106,
DP_OP_454J200_123_2743_n105, DP_OP_454J200_123_2743_n104,
DP_OP_454J200_123_2743_n103, DP_OP_454J200_123_2743_n102,
DP_OP_454J200_123_2743_n101, DP_OP_454J200_123_2743_n100,
DP_OP_454J200_123_2743_n99, DP_OP_454J200_123_2743_n98,
DP_OP_454J200_123_2743_n97, DP_OP_454J200_123_2743_n96,
DP_OP_454J200_123_2743_n94, DP_OP_454J200_123_2743_n93,
DP_OP_454J200_123_2743_n92, DP_OP_454J200_123_2743_n91,
DP_OP_454J200_123_2743_n90, DP_OP_454J200_123_2743_n89,
DP_OP_454J200_123_2743_n88, DP_OP_454J200_123_2743_n87,
DP_OP_454J200_123_2743_n84, DP_OP_454J200_123_2743_n83,
DP_OP_454J200_123_2743_n82, DP_OP_454J200_123_2743_n81,
DP_OP_454J200_123_2743_n80, DP_OP_454J200_123_2743_n79,
DP_OP_454J200_123_2743_n78, DP_OP_454J200_123_2743_n77,
DP_OP_454J200_123_2743_n76, DP_OP_454J200_123_2743_n75,
DP_OP_454J200_123_2743_n74, DP_OP_454J200_123_2743_n73,
DP_OP_454J200_123_2743_n72, DP_OP_454J200_123_2743_n71,
DP_OP_454J200_123_2743_n70, DP_OP_454J200_123_2743_n69,
DP_OP_454J200_123_2743_n68, DP_OP_454J200_123_2743_n67,
DP_OP_454J200_123_2743_n66, DP_OP_454J200_123_2743_n65,
DP_OP_454J200_123_2743_n64, DP_OP_454J200_123_2743_n63,
DP_OP_454J200_123_2743_n62, DP_OP_454J200_123_2743_n61,
DP_OP_454J200_123_2743_n60, DP_OP_454J200_123_2743_n59,
DP_OP_454J200_123_2743_n58, DP_OP_454J200_123_2743_n57,
DP_OP_454J200_123_2743_n56, DP_OP_454J200_123_2743_n55,
DP_OP_454J200_123_2743_n52, DP_OP_454J200_123_2743_n51,
DP_OP_454J200_123_2743_n50, DP_OP_454J200_123_2743_n49,
DP_OP_454J200_123_2743_n48, DP_OP_454J200_123_2743_n47,
DP_OP_454J200_123_2743_n46, DP_OP_454J200_123_2743_n45,
DP_OP_454J200_123_2743_n44, DP_OP_454J200_123_2743_n43,
DP_OP_454J200_123_2743_n42, DP_OP_454J200_123_2743_n41,
DP_OP_454J200_123_2743_n40, DP_OP_454J200_123_2743_n39,
DP_OP_454J200_123_2743_n38, DP_OP_454J200_123_2743_n37,
DP_OP_454J200_123_2743_n36, DP_OP_454J200_123_2743_n35,
mult_x_254_n232, mult_x_254_n228, mult_x_254_n220, mult_x_254_n219,
mult_x_254_n216, mult_x_254_n215, mult_x_254_n213, mult_x_254_n212,
mult_x_254_n211, mult_x_254_n208, mult_x_254_n207, mult_x_254_n206,
mult_x_254_n205, mult_x_254_n204, mult_x_254_n203, mult_x_254_n202,
mult_x_254_n200, mult_x_254_n199, mult_x_254_n198, mult_x_254_n197,
mult_x_254_n196, mult_x_254_n195, mult_x_254_n194, mult_x_254_n192,
mult_x_254_n191, mult_x_254_n190, mult_x_254_n189, mult_x_254_n186,
mult_x_254_n185, mult_x_254_n183, mult_x_254_n180, mult_x_254_n179,
mult_x_254_n178, mult_x_254_n176, mult_x_254_n175, mult_x_254_n174,
mult_x_254_n173, mult_x_254_n170, mult_x_254_n169, mult_x_254_n168,
mult_x_254_n167, mult_x_254_n166, mult_x_254_n165, mult_x_254_n164,
mult_x_254_n163, mult_x_254_n162, mult_x_254_n161, mult_x_254_n160,
mult_x_254_n159, mult_x_254_n158, mult_x_254_n157, mult_x_254_n151,
mult_x_254_n149, mult_x_254_n136, mult_x_254_n133, mult_x_254_n132,
mult_x_254_n131, mult_x_254_n130, mult_x_254_n129, mult_x_254_n128,
mult_x_254_n127, mult_x_254_n126, mult_x_254_n125, mult_x_254_n124,
mult_x_254_n123, mult_x_254_n122, mult_x_254_n121, mult_x_254_n120,
mult_x_254_n119, mult_x_254_n118, mult_x_254_n117, mult_x_254_n116,
mult_x_254_n115, mult_x_254_n114, mult_x_254_n113, mult_x_254_n112,
mult_x_254_n111, mult_x_254_n110, mult_x_254_n109, mult_x_254_n108,
mult_x_254_n107, mult_x_254_n106, mult_x_254_n105, mult_x_254_n104,
mult_x_254_n103, mult_x_254_n102, mult_x_254_n101, mult_x_254_n100,
mult_x_254_n99, mult_x_254_n98, mult_x_254_n97, mult_x_254_n96,
mult_x_254_n95, mult_x_254_n94, mult_x_254_n93, mult_x_254_n92,
mult_x_254_n90, mult_x_254_n89, mult_x_254_n88, mult_x_254_n87,
mult_x_254_n86, mult_x_254_n85, mult_x_254_n84, mult_x_254_n83,
mult_x_254_n80, mult_x_254_n79, mult_x_254_n78, mult_x_254_n77,
mult_x_254_n76, mult_x_254_n75, mult_x_254_n74, mult_x_254_n73,
mult_x_254_n72, mult_x_254_n71, mult_x_254_n70, mult_x_254_n69,
mult_x_254_n68, mult_x_254_n67, mult_x_254_n66, mult_x_254_n65,
mult_x_254_n64, mult_x_254_n63, mult_x_254_n62, mult_x_254_n61,
mult_x_254_n60, mult_x_254_n59, mult_x_254_n58, mult_x_254_n57,
mult_x_254_n56, mult_x_254_n55, mult_x_254_n54, mult_x_254_n53,
mult_x_254_n52, mult_x_254_n51, mult_x_254_n48, mult_x_254_n47,
mult_x_254_n46, mult_x_254_n45, mult_x_254_n44, mult_x_254_n43,
mult_x_254_n42, mult_x_254_n41, mult_x_254_n40, mult_x_254_n39,
mult_x_254_n38, mult_x_254_n37, mult_x_254_n36, mult_x_254_n35,
mult_x_254_n34, mult_x_254_n33, mult_x_254_n32, mult_x_254_n31,
mult_x_219_n226, mult_x_219_n222, mult_x_219_n214, mult_x_219_n213,
mult_x_219_n210, mult_x_219_n209, mult_x_219_n207, mult_x_219_n206,
mult_x_219_n205, mult_x_219_n202, mult_x_219_n201, mult_x_219_n200,
mult_x_219_n199, mult_x_219_n198, mult_x_219_n197, mult_x_219_n196,
mult_x_219_n194, mult_x_219_n193, mult_x_219_n192, mult_x_219_n191,
mult_x_219_n190, mult_x_219_n189, mult_x_219_n188, mult_x_219_n186,
mult_x_219_n185, mult_x_219_n184, mult_x_219_n183, mult_x_219_n180,
mult_x_219_n179, mult_x_219_n177, mult_x_219_n174, mult_x_219_n173,
mult_x_219_n172, mult_x_219_n170, mult_x_219_n169, mult_x_219_n168,
mult_x_219_n167, mult_x_219_n164, mult_x_219_n163, mult_x_219_n162,
mult_x_219_n161, mult_x_219_n160, mult_x_219_n159, mult_x_219_n158,
mult_x_219_n157, mult_x_219_n156, mult_x_219_n155, mult_x_219_n154,
mult_x_219_n153, mult_x_219_n152, mult_x_219_n151, mult_x_219_n136,
mult_x_219_n133, mult_x_219_n132, mult_x_219_n131, mult_x_219_n130,
mult_x_219_n129, mult_x_219_n128, mult_x_219_n127, mult_x_219_n126,
mult_x_219_n125, mult_x_219_n124, mult_x_219_n123, mult_x_219_n122,
mult_x_219_n121, mult_x_219_n120, mult_x_219_n119, mult_x_219_n118,
mult_x_219_n117, mult_x_219_n116, mult_x_219_n115, mult_x_219_n114,
mult_x_219_n113, mult_x_219_n112, mult_x_219_n111, mult_x_219_n110,
mult_x_219_n109, mult_x_219_n108, mult_x_219_n107, mult_x_219_n106,
mult_x_219_n105, mult_x_219_n104, mult_x_219_n103, mult_x_219_n102,
mult_x_219_n101, mult_x_219_n100, mult_x_219_n99, mult_x_219_n98,
mult_x_219_n97, mult_x_219_n96, mult_x_219_n95, mult_x_219_n94,
mult_x_219_n93, mult_x_219_n92, mult_x_219_n90, mult_x_219_n89,
mult_x_219_n88, mult_x_219_n87, mult_x_219_n86, mult_x_219_n85,
mult_x_219_n84, mult_x_219_n83, mult_x_219_n80, mult_x_219_n79,
mult_x_219_n78, mult_x_219_n77, mult_x_219_n76, mult_x_219_n75,
mult_x_219_n74, mult_x_219_n73, mult_x_219_n72, mult_x_219_n71,
mult_x_219_n70, mult_x_219_n69, mult_x_219_n68, mult_x_219_n67,
mult_x_219_n66, mult_x_219_n65, mult_x_219_n62, mult_x_219_n61,
mult_x_219_n60, mult_x_219_n59, mult_x_219_n58, mult_x_219_n57,
mult_x_219_n56, mult_x_219_n55, mult_x_219_n54, mult_x_219_n53,
mult_x_219_n52, mult_x_219_n51, mult_x_219_n48, mult_x_219_n47,
mult_x_219_n46, mult_x_219_n45, mult_x_219_n44, mult_x_219_n43,
mult_x_219_n42, mult_x_219_n41, mult_x_219_n40, mult_x_219_n39,
mult_x_219_n36, mult_x_219_n35, mult_x_219_n34, mult_x_219_n33,
mult_x_219_n32, mult_x_219_n31, DP_OP_26J200_124_9022_n18,
DP_OP_26J200_124_9022_n17, DP_OP_26J200_124_9022_n16,
DP_OP_26J200_124_9022_n15, DP_OP_26J200_124_9022_n14,
DP_OP_26J200_124_9022_n8, DP_OP_26J200_124_9022_n7,
DP_OP_26J200_124_9022_n6, DP_OP_26J200_124_9022_n5,
DP_OP_26J200_124_9022_n4, DP_OP_26J200_124_9022_n3,
DP_OP_26J200_124_9022_n2, DP_OP_26J200_124_9022_n1,
DP_OP_234J200_127_8543_n22, DP_OP_234J200_127_8543_n21,
DP_OP_234J200_127_8543_n20, DP_OP_234J200_127_8543_n19,
DP_OP_234J200_127_8543_n18, DP_OP_234J200_127_8543_n17,
DP_OP_234J200_127_8543_n16, DP_OP_234J200_127_8543_n15,
DP_OP_234J200_127_8543_n9, DP_OP_234J200_127_8543_n8,
DP_OP_234J200_127_8543_n7, DP_OP_234J200_127_8543_n6,
DP_OP_234J200_127_8543_n5, DP_OP_234J200_127_8543_n4,
DP_OP_234J200_127_8543_n3, DP_OP_234J200_127_8543_n2,
DP_OP_234J200_127_8543_n1, n2194, n2198, n2199, n2200, n2201, n2202,
n2203, n2204, n2205, n2206, n2207, n2208, n2209, n2210, n2211, n2212,
n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220, n2221, n2222,
n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230, n2231, n2232,
n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240, n2241, n2242,
n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250, n2251, n2252,
n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260, n2261, n2262,
n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270, n2271, n2272,
n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280, n2281, n2282,
n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290, n2291, n2292,
n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300, n2301, n2302,
n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311, n2312,
n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321, n2322,
n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330, n2331, n2332,
n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342,
n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352,
n2354, n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362, n2363,
n2364, n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372, n2373,
n2374, n2375, n2376, n2377, n2378, n2379, n2380, n2381, n2382, n2383,
n2384, n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392, n2393,
n2394, n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402, n2403,
n2404, n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412, n2413,
n2414, n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422, n2423,
n2424, n2425, n2426, n2427, n2428, n2429, n2430, n2431, n2432, n2433,
n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441, n2442, n2443,
n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451, n2452, n2453,
n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461, n2462, n2463,
n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471, n2472, n2473,
n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481, n2482, n2483,
n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491, n2492, n2493,
n2494, n2495, n2496, n2497, n2498, n2499, n2500, n2501, n2502, n2503,
n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2511, n2512, n2513,
n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522, n2523,
n2524, n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532, n2533,
n2534, n2535, n2536, n2537, n2538, n2539, n2540, n2541, n2542, n2543,
n2544, n2545, n2546, n2547, n2548, n2549, n2550, n2551, n2552, n2553,
n2554, n2555, n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563,
n2564, n2565, n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573,
n2574, n2575, n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583,
n2584, n2585, n2586, n2587, n2588, n2589, n2590, n2591, n2592, n2593,
n2594, n2595, n2596, n2597, n2598, n2599, n2600, n2601, n2602, n2603,
n2604, n2605, n2606, n2607, n2608, n2609, n2610, n2611, n2612, n2613,
n2614, n2615, n2616, n2617, n2618, n2619, n2620, n2621, n2622, n2623,
n2624, n2625, n2626, n2627, n2628, n2629, n2630, n2631, n2632, n2633,
n2634, n2635, n2636, n2637, n2638, n2639, n2640, n2641, n2642, n2643,
n2644, n2645, n2646, n2647, n2648, n2649, n2650, n2651, n2652, n2653,
n2654, n2655, n2656, n2657, n2658, n2659, n2660, n2661, n2662, n2663,
n2664, n2665, n2666, n2667, n2668, n2669, n2670, n2671, n2672, n2673,
n2674, n2675, n2676, n2677, n2678, n2679, n2680, n2681, n2682, n2683,
n2684, n2685, n2686, n2687, n2688, n2689, n2690, n2691, n2692, n2693,
n2694, n2695, n2696, n2697, n2698, n2699, n2700, n2701, n2702, n2703,
n2704, n2705, n2706, n2707, n2708, n2709, n2710, n2711, n2712, n2713,
n2714, n2715, n2716, n2717, n2718, n2719, n2720, n2721, n2722, n2723,
n2724, n2725, n2726, n2727, n2728, n2729, n2730, n2731, n2732, n2733,
n2734, n2735, n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743,
n2744, n2745, n2746, n2747, n2748, n2749, n2750, n2751, n2752, n2753,
n2754, n2755, n2756, n2757, n2758, n2759, n2760, n2761, n2762, n2763,
n2764, n2765, n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773,
n2774, n2775, n2776, n2777, n2778, n2779, n2780, n2781, n2782, n2783,
n2784, n2785, n2786, n2787, n2788, n2789, n2790, n2791, n2792, n2793,
n2794, n2795, n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803,
n2804, n2805, n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813,
n2814, n2815, n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823,
n2824, n2825, n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833,
n2834, n2835, n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843,
n2844, n2845, n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853,
n2854, n2855, n2856, n2857, n2858, n2859, n2860, n2861, n2862, n2863,
n2864, n2865, n2866, n2867, n2868, n2869, n2870, n2871, n2872, n2873,
n2874, n2875, n2876, n2877, n2878, n2879, n2880, n2881, n2882, n2883,
n2884, n2885, n2886, n2887, n2888, n2889, n2890, n2891, n2892, n2893,
n2894, n2895, n2896, n2897, n2898, n2899, n2900, n2901, n2902, n2903,
n2904, n2905, n2906, n2907, n2908, n2909, n2910, n2911, n2912, n2913,
n2914, n2915, n2916, n2917, n2918, n2919, n2920, n2921, n2922, n2923,
n2924, n2925, n2926, n2927, n2928, n2929, n2930, n2931, n2932, n2933,
n2934, n2935, n2936, n2937, n2938, n2939, n2940, n2941, n2942, n2943,
n2944, n2945, n2946, n2947, n2948, n2949, n2950, n2951, n2952, n2953,
n2954, n2955, n2956, n2957, n2958, n2959, n2960, n2961, n2962, n2963,
n2964, n2965, n2966, n2967, n2968, n2969, n2970, n2971, n2972, n2973,
n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981, n2982, n2983,
n2984, n2985, n2986, n2987, n2988, n2989, n2990, n2991, n2992, n2993,
n2994, n2995, n2996, n2997, n2998, n2999, n3000, n3001, n3002, n3003,
n3004, n3005, n3006, n3007, n3008, n3009, n3010, n3011, n3012, n3013,
n3014, n3015, n3016, n3017, n3018, n3019, n3020, n3021, n3022, n3023,
n3024, n3025, n3026, n3027, n3028, n3029, n3030, n3031, n3032, n3033,
n3034, n3035, n3036, n3037, n3038, n3039, n3040, n3041, n3042, n3043,
n3044, n3045, n3046, n3047, n3048, n3049, n3050, n3051, n3052, n3053,
n3054, n3055, n3056, n3057, n3058, n3059, n3060, n3061, n3062, n3063,
n3064, n3065, n3066, n3067, n3068, n3069, n3070, n3071, n3072, n3073,
n3074, n3075, n3076, n3077, n3078, n3079, n3080, n3081, n3082, n3083,
n3084, n3085, n3086, n3087, n3088, n3089, n3090, n3091, n3092, n3093,
n3094, n3095, n3096, n3097, n3098, n3099, n3100, n3101, n3102, n3103,
n3104, n3105, n3106, n3107, n3108, n3109, n3110, n3111, n3112, n3113,
n3114, n3115, n3116, n3117, n3118, n3119, n3120, n3121, n3122, n3123,
n3124, n3125, n3126, n3127, n3128, n3129, n3130, n3131, n3132, n3133,
n3134, n3135, n3136, n3137, n3138, n3139, n3140, n3141, n3142, n3143,
n3144, n3145, n3146, n3147, n3148, n3149, n3150, n3151, n3152, n3153,
n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162, n3163,
n3164, n3165, n3166, n3167, n3168, n3169, n3170, n3171, n3172, n3173,
n3174, n3175, n3176, n3177, n3178, n3179, n3180, n3181, n3182, n3183,
n3184, n3185, n3186, n3187, n3188, n3189, n3190, n3191, n3192, n3193,
n3194, n3195, n3196, n3197, n3198, n3199, n3200, n3201, n3202, n3203,
n3204, n3205, n3206, n3207, n3208, n3209, n3210, n3211, n3212, n3213,
n3214, n3215, n3216, n3217, n3218, n3219, n3220, n3221, n3222, n3223,
n3224, n3225, n3226, n3227, n3228, n3229, n3230, n3231, n3232, n3233,
n3234, n3235, n3236, n3237, n3238, n3239, n3240, n3241, n3242, n3243,
n3244, n3245, n3246, n3247, n3248, n3249, n3250, n3251, n3252, n3253,
n3254, n3255, n3256, n3257, n3258, n3259, n3260, n3261, n3262, n3263,
n3264, n3265, n3266, n3267, n3268, n3269, n3270, n3271, n3272, n3273,
n3274, n3275, n3276, n3277, n3278, n3279, n3280, n3281, n3282, n3283,
n3284, n3285, n3286, n3287, n3288, n3289, n3290, n3291, n3292, n3293,
n3294, n3295, n3296, n3297, n3298, n3299, n3300, n3301, n3302, n3303,
n3304, n3305, n3306, n3307, n3308, n3309, n3310, n3311, n3312, n3313,
n3314, n3315, n3316, n3317, n3318, n3319, n3320, n3321, n3322, n3323,
n3324, n3325, n3326, n3327, n3328, n3329, n3330, n3331, n3332, n3333,
n3334, n3335, n3336, n3337, n3338, n3339, n3340, n3341, n3342, n3343,
n3344, n3345, n3346, n3347, n3348, n3349, n3350, n3351, n3352, n3353,
n3354, n3355, n3356, n3357, n3358, n3359, n3360, n3361, n3362, n3363,
n3364, n3365, n3366, n3367, n3368, n3369, n3370, n3371, n3372, n3373,
n3374, n3375, n3376, n3377, n3378, n3379, n3380, n3381, n3382, n3383,
n3384, n3385, n3386, n3387, n3388, n3389, n3390, n3391, n3392, n3393,
n3394, n3395, n3396, n3397, n3398, n3399, n3400, n3401, n3402, n3403,
n3404, n3405, n3406, n3407, n3408, n3409, n3410, n3411, n3412, n3413,
n3414, n3415, n3416, n3417, n3418, n3419, n3420, n3421, n3422, n3423,
n3424, n3425, n3426, n3427, n3428, n3429, n3430, n3431, n3432, n3433,
n3434, n3435, n3436, n3437, n3438, n3439, n3440, n3441, n3442, n3443,
n3444, n3445, n3446, n3447, n3448, n3449, n3450, n3451, n3452, n3453,
n3454, n3455, n3456, n3457, n3458, n3459, n3460, n3461, n3462, n3463,
n3464, n3465, n3466, n3467, n3468, n3469, n3470, n3471, n3472, n3473,
n3474, n3475, n3476, n3477, n3478, n3479, n3480, n3481, n3482, n3483,
n3484, n3485, n3486, n3487, n3488, n3489, n3490, n3491, n3492, n3493,
n3494, n3495, n3496, n3497, n3498, n3499, n3500, n3501, n3502, n3503,
n3504, n3505, n3506, n3507, n3508, n3509, n3510, n3511, n3512, n3513,
n3514, n3515, n3516, n3517, n3518, n3519, n3520, n3521, n3522, n3523,
n3524, n3525, n3526, n3527, n3528, n3529, n3530, n3531, n3532, n3533,
n3534, n3535, n3536, n3537, n3538, n3539, n3540, n3541, n3542, n3543,
n3544, n3545, n3546, n3547, n3548, n3549, n3550, n3551, n3552, n3553,
n3554, n3555, n3556, n3557, n3558, n3559, n3560, n3561, n3562, n3563,
n3564, n3565, n3566, n3567, n3568, n3569, n3570, n3571, n3572, n3573,
n3574, n3575, n3576, n3577, n3578, n3579, n3580, n3581, n3582, n3583,
n3584, n3585, n3586, n3587, n3588, n3589, n3590, n3591, n3592, n3593,
n3594, n3595, n3596, n3597, n3598, n3599, n3600, n3601, n3602, n3603,
n3604, n3605, n3606, n3607, n3608, n3609, n3610, n3611, n3612, n3613,
n3614, n3615, n3616, n3617, n3618, n3619, n3620, n3621, n3622, n3623,
n3624, n3625, n3626, n3627, n3628, n3629, n3630, n3631, n3632, n3633,
n3634, n3635, n3636, n3637, n3638, n3639, n3640, n3641, n3642, n3643,
n3644, n3645, n3646, n3647, n3648, n3649, n3650, n3651, n3652, n3653,
n3654, n3655, n3656, n3657, n3658, n3659, n3660, n3661, n3662, n3663,
n3664, n3665, n3666, n3667, n3668, n3669, n3670, n3671, n3672, n3673,
n3674, n3675, n3676, n3677, n3678, n3679, n3680, n3681, n3682, n3683,
n3684, n3685, n3686, n3687, n3688, n3689, n3690, n3691, n3692, n3693,
n3694, n3695, n3696, n3697, n3698, n3699, n3700, n3701, n3702, n3703,
n3704, n3705, n3706, n3707, n3708, n3709, n3710, n3711, n3712, n3713,
n3714, n3715, n3716, n3717, n3718, n3719, n3720, n3721, n3722, n3723,
n3724, n3725, n3726, n3727, n3728, n3729, n3730, n3731, n3732, n3733,
n3734, n3735, n3736, n3737, n3738, n3739, n3740, n3741, n3742, n3743,
n3744, n3745, n3746, n3747, n3748, n3749, n3750, n3751, n3752, n3753,
n3754, n3755, n3756, n3757, n3758, n3759, n3760, n3761, n3762, n3763,
n3764, n3765, n3766, n3767, n3768, n3769, n3770, n3771, n3772, n3773,
n3774, n3775, n3776, n3777, n3778, n3779, n3780, n3781, n3782, n3783,
n3784, n3785, n3786, n3787, n3788, n3789, n3790, n3791, n3792, n3793,
n3794, n3795, n3796, n3797, n3798, n3799, n3800, n3801, n3802, n3803,
n3804, n3805, n3806, n3807, n3808, n3809, n3810, n3811, n3812, n3813,
n3814, n3815, n3816, n3817, n3818, n3819, n3820, n3821, n3822, n3823,
n3824, n3825, n3826, n3827, n3828, n3829, n3830, n3831, n3832, n3833,
n3834, n3835, n3836, n3837, n3838, n3839, n3840, n3841, n3842, n3843,
n3844, n3845, n3846, n3847, n3848, n3849, n3850, n3851, n3852, n3853,
n3854, n3855, n3856, n3857, n3858, n3859, n3860, n3861, n3862, n3863,
n3864, n3865, n3866, n3867, n3868, n3869, n3870, n3871, n3872, n3873,
n3874, n3875, n3876, n3877, n3878, n3879, n3880, n3881, n3882, n3883,
n3884, n3885, n3886, n3887, n3888, n3889, n3890, n3891, n3892, n3893,
n3894, n3895, n3896, n3897, n3898, n3899, n3900, n3901, n3902, n3903,
n3904, n3905, n3906, n3907, n3908, n3909, n3910, n3911, n3912, n3913,
n3914, n3915, n3916, n3917, n3918, n3919, n3920, n3921, n3922, n3923,
n3924, n3925, n3926, n3927, n3928, n3929, n3930, n3931, n3932, n3933,
n3934, n3935, n3936, n3937, n3938, n3939, n3940, n3941, n3942, n3943,
n3944, n3945, n3946, n3947, n3948, n3949, n3950, n3951, n3952, n3953,
n3954, n3955, n3956, n3957, n3958, n3959, n3960, n3961, n3962, n3963,
n3964, n3965, n3966, n3967, n3968, n3969, n3970, n3971, n3972, n3973,
n3974, n3975, n3976, n3977, n3978, n3979, n3980, n3981, n3982, n3983,
n3984, n3985, n3986, n3987, n3988, n3989, n3990, n3991, n3992, n3993,
n3994, n3995, n3996, n3997, n3998, n3999, n4000, n4001, n4002, n4003,
n4004, n4005, n4006, n4007, n4008, n4009, n4010, n4011, n4012, n4013,
n4014, n4015, n4016, n4017, n4018, n4019, n4020, n4021, n4022, n4023,
n4024, n4025, n4026, n4027, n4028, n4029, n4030, n4031, n4032, n4033,
n4034, n4035, n4036, n4037, n4038, n4039, n4040, n4041, n4042, n4043,
n4044, n4045, n4046, n4047, n4048, n4049, n4050, n4051, n4052, n4053,
n4054, n4055, n4056, n4057, n4058, n4059, n4060, n4061, n4062, n4063,
n4064, n4065, n4066, n4067, n4068, n4069, n4070, n4071, n4072, n4073,
n4074, n4075, n4076, n4077, n4078, n4079, n4080, n4081, n4082, n4083,
n4084, n4085, n4086, n4087, n4088, n4089, n4090, n4091, n4092, n4093,
n4094, n4095, n4096, n4097, n4098, n4099, n4100, n4101, n4102, n4103,
n4104, n4105, n4106, n4107, n4108, n4109, n4110, n4111, n4112, n4113,
n4114, n4115, n4116, n4117, n4118, n4119, n4120, n4121, n4122, n4123,
n4124, n4125, n4126, n4127, n4128, n4129, n4130, n4131, n4132, n4133,
n4134, n4135, n4136, n4137, n4138, n4139, n4140, n4141, n4142, n4143,
n4144, n4145, n4146, n4147, n4148, n4149, n4150, n4151, n4152, n4153,
n4154, n4155, n4156, n4157, n4158, n4159, n4160, n4161, n4162, n4163,
n4164, n4165, n4166, n4167, n4168, n4169, n4170, n4171, n4172, n4173,
n4174, n4175, n4176, n4177, n4178, n4179, n4180, n4181, n4182, n4183,
n4184, n4185, n4186, n4187, n4188, n4189, n4190, n4191, n4192, n4193,
n4194, n4195, n4196, n4197, n4198, n4199, n4200, n4201, n4202, n4203,
n4204, n4205, n4206, n4207, n4208, n4209, n4210, n4211, n4212, n4213,
n4214, n4215, n4216, n4217, n4218, n4219, n4220, n4221, n4222, n4223,
n4224, n4225, n4226, n4227, n4228, n4229, n4230, n4231, n4232, n4233,
n4234, n4235, n4236, n4237, n4238, n4239, n4240, n4241, n4242, n4243,
n4244, n4245, n4246, n4247, n4248, n4249, n4250, n4251, n4252, n4253,
n4254, n4255, n4256, n4257, n4258, n4259, n4260, n4261, n4262, n4263,
n4264, n4265, n4266, n4267, n4268, n4269, n4270, n4271, n4272, n4273,
n4274, n4275, n4276, n4277, n4278, n4279, n4280, n4281, n4282, n4283,
n4284, n4285, n4286, n4287, n4288, n4289, n4290, n4291, n4292, n4293,
n4294, n4295, n4296, n4297, n4298, n4299, n4300, n4301, n4302, n4303,
n4304, n4305, n4306, n4307, n4308, n4309, n4310, n4311, n4312, n4313,
n4314, n4315, n4316, n4317, n4318, n4319, n4320, n4321, n4322, n4323,
n4324, n4325, n4326, n4327, n4328, n4329, n4330, n4331, n4332, n4333,
n4334, n4335, n4336, n4337, n4338, n4339, n4340, n4341, n4342, n4343,
n4344, n4345, n4346, n4347, n4348, n4349, n4350, n4351, n4352, n4353,
n4354, n4355, n4356, n4357, n4358, n4359, n4360, n4361, n4362, n4363,
n4364, n4365, n4366, n4367, n4368, n4369, n4370, n4371, n4372, n4373,
n4374, n4375, n4376, n4377, n4378, n4379, n4380, n4381, n4382, n4383,
n4384, n4385, n4386, n4387, n4388, n4389, n4390, n4391, n4392, n4393,
n4394, n4395, n4396, n4397, n4398, n4399, n4400, n4401, n4402, n4403,
n4404, n4405, n4406, n4407, n4408, n4409, n4410, n4411, n4412, n4413,
n4414, n4415, n4416, n4417, n4418, n4419, n4420, n4421, n4422, n4423,
n4424, n4425, n4426, n4427, n4428, n4429, n4430, n4431, n4432, n4433,
n4434, n4435, n4436, n4437, n4438, n4439, n4440, n4441, n4442, n4443,
n4444, n4445, n4446, n4447, n4448, n4449, n4450, n4451, n4452, n4453,
n4454, n4455, n4456, n4457, n4458, n4459, n4460, n4461, n4462, n4463,
n4464, n4465, n4466, n4467, n4468, n4469, n4470, n4471, n4472, n4473,
n4474, n4475, n4476, n4477, n4478, n4479, n4480, n4481, n4482, n4483,
n4484, n4485, n4486, n4487, n4488, n4489, n4490, n4491, n4492, n4493,
n4494, n4495, n4496, n4497, n4498, n4499, n4500, n4501, n4502, n4503,
n4504, n4505, n4506, n4507, n4508, n4509, n4510, n4511, n4512, n4513,
n4514, n4515, n4516, n4517, n4518, n4519, n4520, n4521, n4522, n4523,
n4524, n4525, n4526, n4527, n4528, n4529, n4530, n4531, n4532, n4533,
n4534, n4535, n4536, n4537, n4538, n4539, n4540, n4541, n4542, n4543,
n4544, n4545, n4546, n4547, n4548, n4549, n4550, n4551, n4552, n4553,
n4554, n4555, n4556, n4557, n4558, n4559, n4560, n4561, n4562, n4563,
n4564, n4565, n4566, n4567, n4568, n4569, n4570, n4571, n4572, n4573,
n4574, n4575, n4576, n4577, n4578, n4579, n4580, n4581, n4582, n4583,
n4584, n4585, n4586, n4587, n4588, n4589, n4590, n4591, n4592, n4593,
n4594, n4595, n4596, n4597, n4598, n4599, n4600, n4601, n4602, n4603,
n4604, n4605, n4606, n4607, n4608, n4609, n4610, n4611, n4612, n4613,
n4614, n4615, n4616, n4617, n4618, n4619, n4620, n4621, n4622, n4623,
n4624, n4625, n4626, n4627, n4628, n4629, n4630, n4631, n4632, n4633,
n4634, n4635, n4636, n4637, n4638, n4639, n4640, n4641, n4642, n4643,
n4644, n4645, n4646, n4647, n4648, n4649, n4650, n4651, n4652, n4653,
n4654, n4655, n4656, n4657, n4658, n4659, n4660, n4661, n4662, n4663,
n4664, n4665, n4666, n4667, n4668, n4669, n4670, n4671, n4672, n4673,
n4674, n4675, n4676, n4677, n4678, n4679, n4680, n4681, n4682, n4683,
n4684, n4685, n4686, n4687, n4688, n4689, n4690, n4691, n4692, n4693,
n4694, n4695, n4696, n4697, n4698, n4699, n4700, n4701, n4702, n4703,
n4704, n4705, n4706, n4707, n4708, n4709, n4710, n4711, n4712, n4713,
n4714, n4715, n4716, n4717, n4718, n4719, n4720, n4721, n4722, n4723,
n4724, n4725, n4726, n4727, n4728, n4729, n4730, n4731, n4732, n4733,
n4734, n4735, n4736, n4737, n4738, n4739, n4740, n4741, n4742, n4743,
n4744, n4745, n4746, n4747, n4748, n4749, n4750, n4751, n4752, n4753,
n4754, n4755, n4756, n4757, n4758, n4759, n4760, n4761, n4762, n4763,
n4764, n4765, n4766, n4767, n4768, n4769, n4770, n4771, n4772, n4773,
n4774, n4775, n4776, n4777, n4778, n4779, n4780, n4781, n4782, n4783,
n4784, n4785, n4786, n4787, n4788, n4789, n4790, n4791, n4792, n4793,
n4794, n4795, n4796, n4797, n4798, n4799, n4800, n4801, n4802, n4803,
n4804, n4805, n4806, n4807, n4808, n4809, n4810, n4811, n4812, n4813,
n4814, n4815, n4816, n4817, n4818, n4819, n4820, n4821, n4822, n4823,
n4824, n4825, n4826, n4827, n4828, n4829, n4830, n4831, n4832, n4833,
n4834, n4835, n4836, n4837, n4838, n4839, n4840, n4841, n4842, n4843,
n4844, n4845, n4846, n4847, n4848, n4849, n4850, n4851, n4852, n4853,
n4854, n4855, n4856, n4857, n4858, n4859, n4860, n4861, n4862, n4863,
n4864, n4865, n4866, n4867, n4868, n4869, n4870, n4871, n4872, n4873,
n4874, n4875, n4876, n4877, n4878, n4879, n4880, n4881, n4882, n4883,
n4884, n4885, n4886, n4887, n4888, n4889, n4890, n4891, n4892, n4893,
n4894, n4895, n4896, n4897, n4898, n4899, n4900, n4901, n4902, n4903,
n4904, n4905, n4906, n4907, n4908, n4909, n4910, n4911, n4912, n4913,
n4914, n4915, n4916, n4917, n4918, n4919, n4920, n4921, n4922, n4923,
n4924, n4925, n4926, n4927, n4928, n4929, n4930, n4931, n4932, n4933,
n4934, n4935, n4936, n4937, n4938, n4939, n4940, n4941, n4942, n4943,
n4944, n4945, n4946, n4947, n4948, n4949, n4950, n4951, n4952, n4953,
n4954, n4955, n4956, n4957, n4958, n4959, n4960, n4961, n4962, n4963,
n4964, n4965, n4966, n4967, n4968, n4969, n4970, n4971, n4972, n4973,
n4974, n4975, n4976, n4977, n4978, n4979, n4980, n4981, n4982, n4983,
n4984, n4985, n4986, n4987, n4988, n4989, n4990, n4991, n4992, n4993,
n4994, n4995, n4996, n4997, n4998, n4999, n5000, n5001, n5002, n5003,
n5004, n5005, n5006, n5007, n5008, n5009, n5010, n5011, n5012, n5013,
n5014, n5015, n5016, n5017, n5018, n5019, n5020, n5021, n5022, n5023,
n5024, n5025, n5026, n5027, n5028, n5029, n5030, n5031, n5032, n5033,
n5034, n5035, n5036, n5037, n5038, n5039, n5040, n5041, n5042, n5043,
n5044, n5045, n5046, n5047, n5048, n5049, n5050, n5051, n5052, n5053,
n5054, n5055, n5056, n5057, n5058, n5059, n5060, n5061, n5062, n5063,
n5064, n5065, n5066, n5067, n5068, n5069, n5070, n5071, n5072, n5073,
n5074, n5075, n5076, n5077, n5078, n5079, n5080, n5081, n5082, n5083,
n5084, n5085, n5086, n5087, n5088, n5089, n5090, n5091, n5092, n5093,
n5094, n5095, n5096, n5097, n5098, n5099, n5100, n5101, n5102, n5103,
n5104, n5105, n5106, n5107, n5108, n5109, n5110, n5111, n5112, n5113,
n5114, n5115, n5116, n5117, n5118, n5119, n5120, n5121, n5122, n5123,
n5124, n5125, n5126, n5127, n5128, n5129, n5130, n5131, n5132, n5133,
n5134, n5135, n5136, n5137, n5138, n5139, n5140, n5141, n5142, n5143,
n5144, n5145, n5146, n5147, n5148, n5149, n5150, n5151, n5152, n5153,
n5154, n5155, n5156, n5157, n5158, n5159, n5160, n5161, n5162, n5163,
n5164, n5165, n5166, n5167, n5168, n5169, n5170, n5171, n5172, n5173,
n5174, n5175, n5176, n5177, n5178, n5179, n5180, n5181, n5182, n5183,
n5184, n5185, n5186, n5187, n5188, n5189, n5190, n5191, n5192, n5193,
n5194, n5195, n5196, n5197, n5198, n5199, n5200, n5201, n5202, n5203,
n5204, n5205, n5206, n5207, n5208, n5209, n5210, n5211, n5212, n5213,
n5214, n5215, n5216, n5217, n5218, n5219, n5220, n5221, n5222, n5223,
n5224, n5225, n5226, n5227, n5228, n5229, n5230, n5231, n5232, n5233,
n5234, n5235, n5236, n5237, n5238, n5239, n5240, n5241, n5242, n5243,
n5244, n5245, n5246, n5247, n5248, n5249, n5250, n5251, n5252, n5253,
n5254, n5255, n5256, n5257, n5258, n5259, n5260, n5261, n5262, n5263,
n5264, n5265, n5266, n5267, n5268, n5269, n5270, n5271, n5272, n5273,
n5274, n5275, n5276, n5277, n5278, n5279, n5280, n5281, n5282, n5283,
n5284, n5285, n5286, n5287, n5288, n5289, n5290, n5291, n5292, n5293,
n5294, n5295, n5296, n5297, n5298, n5299, n5300, n5301, n5302, n5303,
n5304, n5305, n5306, n5307, n5308, n5309, n5310, n5311, n5312, n5313,
n5314, n5315, n5316, n5317, n5318, n5319, n5320, n5321, n5322, n5323,
n5324, n5325, n5326, n5327, n5328, n5329, n5330, n5331, n5332, n5333,
n5334, n5335, n5336, n5337, n5338, n5339, n5340, n5341, n5342, n5343,
n5344, n5345, n5346, n5347, n5348, n5349, n5350, n5351, n5352, n5353,
n5354, n5355, n5356, n5357, n5358, n5359, n5361, n5362, n5363, n5364,
n5365, n5366, n5367, n5368, n5369, n5370, n5371, n5372, n5373, n5374,
n5375, n5376, n5377, n5378, n5379, n5380, n5381, n5382, n5383, n5384,
n5385, n5386, n5387, n5388, n5389, n5390, n5391, n5392, n5393, n5394,
n5395, n5396, n5397, n5398, n5399, n5400, n5401, n5402, n5403, n5404,
n5405, n5406, n5407, n5408, n5409, n5410, n5411, n5412, n5413, n5414,
n5415, n5416, n5417, n5418, n5419, n5420, n5421, n5422, n5423, n5424,
n5425, n5426, n5427, n5428, n5429, n5430, n5431, n5432, n5433, n5434,
n5435, n5436, n5437, n5438, n5439, n5440, n5441, n5442, n5443, n5444,
n5445, n5446, n5447, n5448, n5449, n5450, n5451, n5452, n5453, n5454,
n5455, n5456, n5457, n5458, n5459, n5460, n5461, n5462, n5463, n5464,
n5465, n5466, n5467, n5468, n5469;
wire [1:0] operation_reg;
wire [31:23] dataA;
wire [31:23] dataB;
wire [31:0] cordic_result;
wire [31:0] result_add_subt;
wire [31:0] mult_result;
wire [27:0] FPSENCOS_d_ff3_LUT_out;
wire [31:0] FPSENCOS_d_ff3_sh_y_out;
wire [31:0] FPSENCOS_d_ff3_sh_x_out;
wire [31:0] FPSENCOS_d_ff2_Z;
wire [31:0] FPSENCOS_d_ff2_Y;
wire [31:0] FPSENCOS_d_ff2_X;
wire [31:0] FPSENCOS_d_ff_Zn;
wire [31:0] FPSENCOS_d_ff_Yn;
wire [31:0] FPSENCOS_d_ff_Xn;
wire [31:0] FPSENCOS_d_ff1_Z;
wire [1:0] FPSENCOS_d_ff1_shift_region_flag_out;
wire [1:0] FPSENCOS_cont_var_out;
wire [3:0] FPSENCOS_cont_iter_out;
wire [23:0] FPMULT_Sgf_normalized_result;
wire [23:0] FPMULT_Add_result;
wire [8:0] FPMULT_S_Oper_A_exp;
wire [8:0] FPMULT_exp_oper_result;
wire [31:0] FPMULT_Op_MY;
wire [31:0] FPMULT_Op_MX;
wire [1:0] FPMULT_FSM_selector_B;
wire [47:0] FPMULT_P_Sgf;
wire [25:0] FPADDSUB_DmP_mant_SFG_SWR;
wire [30:0] FPADDSUB_DMP_SFG;
wire [7:0] FPADDSUB_exp_rslt_NRM2_EW1;
wire [4:0] FPADDSUB_LZD_output_NRM2_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM2_EW;
wire [4:2] FPADDSUB_shift_value_SHT2_EWR;
wire [30:0] FPADDSUB_DMP_SHT2_EWSW;
wire [25:0] FPADDSUB_Data_array_SWR;
wire [25:0] FPADDSUB_Raw_mant_NRM_SWR;
wire [4:0] FPADDSUB_Shift_amount_SHT1_EWR;
wire [22:0] FPADDSUB_DmP_mant_SHT1_SW;
wire [30:0] FPADDSUB_DMP_SHT1_EWSW;
wire [27:0] FPADDSUB_DmP_EXP_EWSW;
wire [30:0] FPADDSUB_DMP_EXP_EWSW;
wire [31:0] FPADDSUB_intDY_EWSW;
wire [31:0] FPADDSUB_intDX_EWSW;
wire [3:1] FPADDSUB_Shift_reg_FLAGS_7;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_next;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_reg;
wire [3:0] FPMULT_FS_Module_state_reg;
wire [8:0] FPMULT_Exp_module_Data_S;
wire [11:0] FPMULT_Sgf_operation_Result;
wire [25:0] FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle;
wire [23:12] FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right;
wire [23:0] FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left;
wire [2:0] FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg;
CMPR42X1TS DP_OP_454J200_123_2743_U75 ( .A(DP_OP_454J200_123_2743_n240), .B(
DP_OP_454J200_123_2743_n227), .C(DP_OP_454J200_123_2743_n148), .D(
DP_OP_454J200_123_2743_n252), .ICI(DP_OP_454J200_123_2743_n214), .S(
DP_OP_454J200_123_2743_n145), .ICO(DP_OP_454J200_123_2743_n143), .CO(
DP_OP_454J200_123_2743_n144) );
CMPR42X1TS DP_OP_454J200_123_2743_U73 ( .A(DP_OP_454J200_123_2743_n143), .B(
DP_OP_454J200_123_2743_n251), .C(DP_OP_454J200_123_2743_n142), .D(
DP_OP_454J200_123_2743_n213), .ICI(DP_OP_454J200_123_2743_n156), .S(
DP_OP_454J200_123_2743_n140), .ICO(DP_OP_454J200_123_2743_n138), .CO(
DP_OP_454J200_123_2743_n139) );
CMPR42X1TS DP_OP_454J200_123_2743_U71 ( .A(DP_OP_454J200_123_2743_n212), .B(
DP_OP_454J200_123_2743_n137), .C(DP_OP_454J200_123_2743_n138), .D(
DP_OP_454J200_123_2743_n250), .ICI(DP_OP_454J200_123_2743_n200), .S(
DP_OP_454J200_123_2743_n135), .ICO(DP_OP_454J200_123_2743_n133), .CO(
DP_OP_454J200_123_2743_n134) );
CMPR42X1TS DP_OP_454J200_123_2743_U68 ( .A(DP_OP_454J200_123_2743_n133), .B(
DP_OP_454J200_123_2743_n249), .C(DP_OP_454J200_123_2743_n130), .D(
DP_OP_454J200_123_2743_n199), .ICI(DP_OP_454J200_123_2743_n155), .S(
DP_OP_454J200_123_2743_n128), .ICO(DP_OP_454J200_123_2743_n126), .CO(
DP_OP_454J200_123_2743_n127) );
CMPR42X1TS DP_OP_454J200_123_2743_U67 ( .A(DP_OP_454J200_123_2743_n223), .B(
DP_OP_454J200_123_2743_n210), .C(DP_OP_454J200_123_2743_n131), .D(
DP_OP_454J200_123_2743_n236), .ICI(DP_OP_454J200_123_2743_n129), .S(
DP_OP_454J200_123_2743_n125), .ICO(DP_OP_454J200_123_2743_n123), .CO(
DP_OP_454J200_123_2743_n124) );
CMPR42X1TS DP_OP_454J200_123_2743_U66 ( .A(DP_OP_454J200_123_2743_n198), .B(
DP_OP_454J200_123_2743_n248), .C(DP_OP_454J200_123_2743_n187), .D(
DP_OP_454J200_123_2743_n126), .ICI(DP_OP_454J200_123_2743_n125), .S(
DP_OP_454J200_123_2743_n122), .ICO(DP_OP_454J200_123_2743_n120), .CO(
DP_OP_454J200_123_2743_n121) );
CMPR42X1TS DP_OP_454J200_123_2743_U64 ( .A(DP_OP_454J200_123_2743_n123), .B(
DP_OP_454J200_123_2743_n235), .C(DP_OP_454J200_123_2743_n119), .D(
DP_OP_454J200_123_2743_n197), .ICI(DP_OP_454J200_123_2743_n124), .S(
DP_OP_454J200_123_2743_n117), .ICO(DP_OP_454J200_123_2743_n115), .CO(
DP_OP_454J200_123_2743_n116) );
CMPR42X1TS DP_OP_454J200_123_2743_U63 ( .A(DP_OP_454J200_123_2743_n120), .B(
DP_OP_454J200_123_2743_n117), .C(DP_OP_454J200_123_2743_n247), .D(
DP_OP_454J200_123_2743_n121), .ICI(DP_OP_454J200_123_2743_n186), .S(
DP_OP_454J200_123_2743_n114), .ICO(DP_OP_454J200_123_2743_n112), .CO(
DP_OP_454J200_123_2743_n113) );
CMPR42X1TS DP_OP_454J200_123_2743_U61 ( .A(DP_OP_454J200_123_2743_n196), .B(
DP_OP_454J200_123_2743_n111), .C(DP_OP_454J200_123_2743_n115), .D(
DP_OP_454J200_123_2743_n234), .ICI(DP_OP_454J200_123_2743_n116), .S(
DP_OP_454J200_123_2743_n109), .ICO(DP_OP_454J200_123_2743_n107), .CO(
DP_OP_454J200_123_2743_n108) );
CMPR42X1TS DP_OP_454J200_123_2743_U60 ( .A(DP_OP_454J200_123_2743_n246), .B(
DP_OP_454J200_123_2743_n172), .C(DP_OP_454J200_123_2743_n185), .D(
DP_OP_454J200_123_2743_n109), .ICI(DP_OP_454J200_123_2743_n112), .S(
DP_OP_454J200_123_2743_n106), .ICO(DP_OP_454J200_123_2743_n104), .CO(
DP_OP_454J200_123_2743_n105) );
CMPR42X1TS DP_OP_454J200_123_2743_U58 ( .A(DP_OP_454J200_123_2743_n195), .B(
DP_OP_454J200_123_2743_n245), .C(DP_OP_454J200_123_2743_n103), .D(
DP_OP_454J200_123_2743_n107), .ICI(DP_OP_454J200_123_2743_n233), .S(
DP_OP_454J200_123_2743_n101), .ICO(DP_OP_454J200_123_2743_n99), .CO(
DP_OP_454J200_123_2743_n100) );
CMPR42X1TS DP_OP_454J200_123_2743_U57 ( .A(DP_OP_454J200_123_2743_n108), .B(
DP_OP_454J200_123_2743_n171), .C(DP_OP_454J200_123_2743_n184), .D(
DP_OP_454J200_123_2743_n101), .ICI(DP_OP_454J200_123_2743_n104), .S(
DP_OP_454J200_123_2743_n98), .ICO(DP_OP_454J200_123_2743_n96), .CO(
DP_OP_454J200_123_2743_n97) );
CMPR42X1TS DP_OP_454J200_123_2743_U54 ( .A(DP_OP_454J200_123_2743_n219), .B(
DP_OP_454J200_123_2743_n102), .C(DP_OP_454J200_123_2743_n94), .D(
DP_OP_454J200_123_2743_n99), .ICI(DP_OP_454J200_123_2743_n232), .S(
DP_OP_454J200_123_2743_n92), .ICO(DP_OP_454J200_123_2743_n90), .CO(
DP_OP_454J200_123_2743_n91) );
CMPR42X1TS DP_OP_454J200_123_2743_U53 ( .A(DP_OP_454J200_123_2743_n170), .B(
DP_OP_454J200_123_2743_n183), .C(DP_OP_454J200_123_2743_n100), .D(
DP_OP_454J200_123_2743_n96), .ICI(DP_OP_454J200_123_2743_n92), .S(
DP_OP_454J200_123_2743_n89), .ICO(DP_OP_454J200_123_2743_n87), .CO(
DP_OP_454J200_123_2743_n88) );
CMPR42X1TS DP_OP_454J200_123_2743_U50 ( .A(DP_OP_454J200_123_2743_n231), .B(
DP_OP_454J200_123_2743_n93), .C(DP_OP_454J200_123_2743_n84), .D(
DP_OP_454J200_123_2743_n90), .ICI(DP_OP_454J200_123_2743_n218), .S(
DP_OP_454J200_123_2743_n82), .ICO(DP_OP_454J200_123_2743_n80), .CO(
DP_OP_454J200_123_2743_n81) );
CMPR42X1TS DP_OP_454J200_123_2743_U49 ( .A(DP_OP_454J200_123_2743_n169), .B(
DP_OP_454J200_123_2743_n182), .C(DP_OP_454J200_123_2743_n91), .D(
DP_OP_454J200_123_2743_n87), .ICI(DP_OP_454J200_123_2743_n82), .S(
DP_OP_454J200_123_2743_n79), .ICO(DP_OP_454J200_123_2743_n77), .CO(
DP_OP_454J200_123_2743_n78) );
CMPR42X1TS DP_OP_454J200_123_2743_U47 ( .A(DP_OP_454J200_123_2743_n204), .B(
DP_OP_454J200_123_2743_n83), .C(DP_OP_454J200_123_2743_n76), .D(
DP_OP_454J200_123_2743_n80), .ICI(DP_OP_454J200_123_2743_n217), .S(
DP_OP_454J200_123_2743_n74), .ICO(DP_OP_454J200_123_2743_n72), .CO(
DP_OP_454J200_123_2743_n73) );
CMPR42X1TS DP_OP_454J200_123_2743_U46 ( .A(DP_OP_454J200_123_2743_n168), .B(
DP_OP_454J200_123_2743_n181), .C(DP_OP_454J200_123_2743_n81), .D(
DP_OP_454J200_123_2743_n74), .ICI(DP_OP_454J200_123_2743_n77), .S(
DP_OP_454J200_123_2743_n71), .ICO(DP_OP_454J200_123_2743_n69), .CO(
DP_OP_454J200_123_2743_n70) );
CMPR42X1TS DP_OP_454J200_123_2743_U44 ( .A(DP_OP_454J200_123_2743_n68), .B(
DP_OP_454J200_123_2743_n216), .C(DP_OP_454J200_123_2743_n75), .D(
DP_OP_454J200_123_2743_n72), .ICI(DP_OP_454J200_123_2743_n203), .S(
DP_OP_454J200_123_2743_n66), .ICO(DP_OP_454J200_123_2743_n64), .CO(
DP_OP_454J200_123_2743_n65) );
CMPR42X1TS DP_OP_454J200_123_2743_U43 ( .A(DP_OP_454J200_123_2743_n167), .B(
DP_OP_454J200_123_2743_n180), .C(DP_OP_454J200_123_2743_n73), .D(
DP_OP_454J200_123_2743_n66), .ICI(DP_OP_454J200_123_2743_n69), .S(
DP_OP_454J200_123_2743_n63), .ICO(DP_OP_454J200_123_2743_n61), .CO(
DP_OP_454J200_123_2743_n62) );
CMPR42X1TS DP_OP_454J200_123_2743_U42 ( .A(DP_OP_454J200_123_2743_n215), .B(
DP_OP_454J200_123_2743_n67), .C(DP_OP_454J200_123_2743_n191), .D(
DP_OP_454J200_123_2743_n64), .ICI(DP_OP_454J200_123_2743_n202), .S(
DP_OP_454J200_123_2743_n60), .ICO(DP_OP_454J200_123_2743_n58), .CO(
DP_OP_454J200_123_2743_n59) );
CMPR42X1TS DP_OP_454J200_123_2743_U41 ( .A(DP_OP_454J200_123_2743_n166), .B(
DP_OP_454J200_123_2743_n179), .C(DP_OP_454J200_123_2743_n65), .D(
DP_OP_454J200_123_2743_n60), .ICI(DP_OP_454J200_123_2743_n61), .S(
DP_OP_454J200_123_2743_n57), .ICO(DP_OP_454J200_123_2743_n55), .CO(
DP_OP_454J200_123_2743_n56) );
CMPR42X1TS DP_OP_454J200_123_2743_U38 ( .A(DP_OP_454J200_123_2743_n165), .B(
DP_OP_454J200_123_2743_n178), .C(DP_OP_454J200_123_2743_n52), .D(
DP_OP_454J200_123_2743_n59), .ICI(DP_OP_454J200_123_2743_n55), .S(
DP_OP_454J200_123_2743_n50), .ICO(DP_OP_454J200_123_2743_n48), .CO(
DP_OP_454J200_123_2743_n49) );
CMPR42X1TS DP_OP_454J200_123_2743_U36 ( .A(DP_OP_454J200_123_2743_n164), .B(
DP_OP_454J200_123_2743_n177), .C(DP_OP_454J200_123_2743_n51), .D(
DP_OP_454J200_123_2743_n47), .ICI(DP_OP_454J200_123_2743_n48), .S(
DP_OP_454J200_123_2743_n45), .ICO(DP_OP_454J200_123_2743_n43), .CO(
DP_OP_454J200_123_2743_n44) );
CMPR42X1TS DP_OP_454J200_123_2743_U34 ( .A(DP_OP_454J200_123_2743_n42), .B(
DP_OP_454J200_123_2743_n163), .C(DP_OP_454J200_123_2743_n176), .D(
DP_OP_454J200_123_2743_n46), .ICI(DP_OP_454J200_123_2743_n43), .S(
DP_OP_454J200_123_2743_n40), .ICO(DP_OP_454J200_123_2743_n38), .CO(
DP_OP_454J200_123_2743_n39) );
CMPR42X1TS DP_OP_454J200_123_2743_U33 ( .A(DP_OP_454J200_123_2743_n188), .B(
DP_OP_454J200_123_2743_n41), .C(DP_OP_454J200_123_2743_n162), .D(
DP_OP_454J200_123_2743_n175), .ICI(DP_OP_454J200_123_2743_n38), .S(
DP_OP_454J200_123_2743_n37), .ICO(DP_OP_454J200_123_2743_n35), .CO(
DP_OP_454J200_123_2743_n36) );
CMPR42X1TS mult_x_254_U69 ( .A(mult_x_254_n196), .B(mult_x_254_n232), .C(
mult_x_254_n220), .D(mult_x_254_n208), .ICI(mult_x_254_n136), .S(
mult_x_254_n133), .ICO(mult_x_254_n131), .CO(mult_x_254_n132) );
CMPR42X1TS mult_x_254_U67 ( .A(mult_x_254_n219), .B(mult_x_254_n195), .C(
mult_x_254_n207), .D(mult_x_254_n131), .ICI(mult_x_254_n130), .S(
mult_x_254_n128), .ICO(mult_x_254_n126), .CO(mult_x_254_n127) );
CMPR42X1TS mult_x_254_U65 ( .A(mult_x_254_n206), .B(mult_x_254_n194), .C(
mult_x_254_n129), .D(mult_x_254_n126), .ICI(mult_x_254_n125), .S(
mult_x_254_n123), .ICO(mult_x_254_n121), .CO(mult_x_254_n122) );
CMPR42X1TS mult_x_254_U62 ( .A(mult_x_254_n205), .B(mult_x_254_n124), .C(
mult_x_254_n120), .D(mult_x_254_n118), .ICI(mult_x_254_n121), .S(
mult_x_254_n116), .ICO(mult_x_254_n114), .CO(mult_x_254_n115) );
CMPR42X1TS mult_x_254_U61 ( .A(mult_x_254_n168), .B(mult_x_254_n228), .C(
mult_x_254_n216), .D(mult_x_254_n204), .ICI(mult_x_254_n180), .S(
mult_x_254_n113), .ICO(mult_x_254_n111), .CO(mult_x_254_n112) );
CMPR42X1TS mult_x_254_U60 ( .A(mult_x_254_n192), .B(mult_x_254_n119), .C(
mult_x_254_n117), .D(mult_x_254_n114), .ICI(mult_x_254_n113), .S(
mult_x_254_n110), .ICO(mult_x_254_n108), .CO(mult_x_254_n109) );
CMPR42X1TS mult_x_254_U58 ( .A(mult_x_254_n215), .B(mult_x_254_n167), .C(
mult_x_254_n203), .D(mult_x_254_n179), .ICI(mult_x_254_n107), .S(
mult_x_254_n105), .ICO(mult_x_254_n103), .CO(mult_x_254_n104) );
CMPR42X1TS mult_x_254_U57 ( .A(mult_x_254_n191), .B(mult_x_254_n111), .C(
mult_x_254_n108), .D(mult_x_254_n112), .ICI(mult_x_254_n105), .S(
mult_x_254_n102), .ICO(mult_x_254_n100), .CO(mult_x_254_n101) );
CMPR42X1TS mult_x_254_U55 ( .A(mult_x_254_n202), .B(mult_x_254_n166), .C(
mult_x_254_n190), .D(mult_x_254_n178), .ICI(mult_x_254_n99), .S(
mult_x_254_n97), .ICO(mult_x_254_n95), .CO(mult_x_254_n96) );
CMPR42X1TS mult_x_254_U54 ( .A(mult_x_254_n106), .B(mult_x_254_n103), .C(
mult_x_254_n104), .D(mult_x_254_n97), .ICI(mult_x_254_n100), .S(
mult_x_254_n94), .ICO(mult_x_254_n92), .CO(mult_x_254_n93) );
CMPR42X1TS mult_x_254_U51 ( .A(mult_x_254_n189), .B(mult_x_254_n165), .C(
mult_x_254_n213), .D(n5029), .ICI(mult_x_254_n90), .S(mult_x_254_n88),
.ICO(mult_x_254_n86), .CO(mult_x_254_n87) );
CMPR42X1TS mult_x_254_U50 ( .A(mult_x_254_n95), .B(mult_x_254_n98), .C(
mult_x_254_n96), .D(mult_x_254_n88), .ICI(mult_x_254_n92), .S(
mult_x_254_n85), .ICO(mult_x_254_n83), .CO(mult_x_254_n84) );
CMPR42X1TS mult_x_254_U47 ( .A(mult_x_254_n176), .B(mult_x_254_n212), .C(
mult_x_254_n200), .D(mult_x_254_n164), .ICI(mult_x_254_n89), .S(
mult_x_254_n78), .ICO(mult_x_254_n76), .CO(mult_x_254_n77) );
CMPR42X1TS mult_x_254_U46 ( .A(mult_x_254_n86), .B(mult_x_254_n80), .C(
mult_x_254_n87), .D(mult_x_254_n78), .ICI(mult_x_254_n83), .S(
mult_x_254_n75), .ICO(mult_x_254_n73), .CO(mult_x_254_n74) );
CMPR42X1TS mult_x_254_U44 ( .A(mult_x_254_n175), .B(mult_x_254_n163), .C(
mult_x_254_n199), .D(mult_x_254_n211), .ICI(mult_x_254_n72), .S(
mult_x_254_n70), .ICO(mult_x_254_n68), .CO(mult_x_254_n69) );
CMPR42X1TS mult_x_254_U43 ( .A(mult_x_254_n76), .B(mult_x_254_n79), .C(
mult_x_254_n77), .D(mult_x_254_n70), .ICI(mult_x_254_n73), .S(
mult_x_254_n67), .ICO(mult_x_254_n65), .CO(mult_x_254_n66) );
CMPR42X1TS mult_x_254_U41 ( .A(mult_x_254_n64), .B(mult_x_254_n174), .C(
mult_x_254_n186), .D(mult_x_254_n162), .ICI(mult_x_254_n198), .S(
mult_x_254_n62), .ICO(mult_x_254_n60), .CO(mult_x_254_n61) );
CMPR42X1TS mult_x_254_U40 ( .A(mult_x_254_n68), .B(mult_x_254_n71), .C(
mult_x_254_n69), .D(mult_x_254_n62), .ICI(mult_x_254_n65), .S(
mult_x_254_n59), .ICO(mult_x_254_n57), .CO(mult_x_254_n58) );
CMPR42X1TS mult_x_254_U39 ( .A(mult_x_254_n63), .B(mult_x_254_n151), .C(
mult_x_254_n185), .D(mult_x_254_n173), .ICI(mult_x_254_n161), .S(
mult_x_254_n56), .ICO(mult_x_254_n54), .CO(mult_x_254_n55) );
CMPR42X1TS mult_x_254_U38 ( .A(mult_x_254_n197), .B(mult_x_254_n60), .C(
mult_x_254_n61), .D(mult_x_254_n56), .ICI(mult_x_254_n57), .S(
mult_x_254_n53), .ICO(mult_x_254_n51), .CO(mult_x_254_n52) );
CMPR42X1TS mult_x_254_U35 ( .A(mult_x_254_n160), .B(mult_x_254_n54), .C(
mult_x_254_n48), .D(mult_x_254_n55), .ICI(mult_x_254_n51), .S(
mult_x_254_n46), .ICO(mult_x_254_n44), .CO(mult_x_254_n45) );
CMPR42X1TS mult_x_254_U33 ( .A(mult_x_254_n159), .B(mult_x_254_n183), .C(
mult_x_254_n43), .D(mult_x_254_n47), .ICI(mult_x_254_n44), .S(
mult_x_254_n41), .ICO(mult_x_254_n39), .CO(mult_x_254_n40) );
CMPR42X1TS mult_x_254_U31 ( .A(mult_x_254_n38), .B(mult_x_254_n170), .C(
mult_x_254_n158), .D(mult_x_254_n42), .ICI(mult_x_254_n39), .S(
mult_x_254_n36), .ICO(mult_x_254_n34), .CO(mult_x_254_n35) );
CMPR42X1TS mult_x_254_U30 ( .A(mult_x_254_n37), .B(mult_x_254_n149), .C(
mult_x_254_n157), .D(mult_x_254_n169), .ICI(mult_x_254_n34), .S(
mult_x_254_n33), .ICO(mult_x_254_n31), .CO(mult_x_254_n32) );
CMPR42X1TS mult_x_219_U69 ( .A(mult_x_219_n190), .B(mult_x_219_n226), .C(
mult_x_219_n214), .D(mult_x_219_n202), .ICI(mult_x_219_n136), .S(
mult_x_219_n133), .ICO(mult_x_219_n131), .CO(mult_x_219_n132) );
CMPR42X1TS mult_x_219_U67 ( .A(mult_x_219_n213), .B(mult_x_219_n189), .C(
mult_x_219_n201), .D(mult_x_219_n131), .ICI(mult_x_219_n130), .S(
mult_x_219_n128), .ICO(mult_x_219_n126), .CO(mult_x_219_n127) );
CMPR42X1TS mult_x_219_U65 ( .A(mult_x_219_n200), .B(mult_x_219_n188), .C(
mult_x_219_n129), .D(mult_x_219_n126), .ICI(mult_x_219_n125), .S(
mult_x_219_n123), .ICO(mult_x_219_n121), .CO(mult_x_219_n122) );
CMPR42X1TS mult_x_219_U62 ( .A(mult_x_219_n199), .B(mult_x_219_n124), .C(
mult_x_219_n120), .D(mult_x_219_n118), .ICI(mult_x_219_n121), .S(
mult_x_219_n116), .ICO(mult_x_219_n114), .CO(mult_x_219_n115) );
CMPR42X1TS mult_x_219_U61 ( .A(mult_x_219_n162), .B(mult_x_219_n222), .C(
mult_x_219_n210), .D(mult_x_219_n198), .ICI(mult_x_219_n174), .S(
mult_x_219_n113), .ICO(mult_x_219_n111), .CO(mult_x_219_n112) );
CMPR42X1TS mult_x_219_U60 ( .A(mult_x_219_n186), .B(mult_x_219_n119), .C(
mult_x_219_n117), .D(mult_x_219_n114), .ICI(mult_x_219_n113), .S(
mult_x_219_n110), .ICO(mult_x_219_n108), .CO(mult_x_219_n109) );
CMPR42X1TS mult_x_219_U58 ( .A(mult_x_219_n209), .B(mult_x_219_n161), .C(
mult_x_219_n197), .D(mult_x_219_n173), .ICI(mult_x_219_n107), .S(
mult_x_219_n105), .ICO(mult_x_219_n103), .CO(mult_x_219_n104) );
CMPR42X1TS mult_x_219_U57 ( .A(mult_x_219_n185), .B(mult_x_219_n111), .C(
mult_x_219_n108), .D(mult_x_219_n112), .ICI(mult_x_219_n105), .S(
mult_x_219_n102), .ICO(mult_x_219_n100), .CO(mult_x_219_n101) );
CMPR42X1TS mult_x_219_U55 ( .A(mult_x_219_n196), .B(mult_x_219_n160), .C(
mult_x_219_n184), .D(mult_x_219_n172), .ICI(mult_x_219_n99), .S(
mult_x_219_n97), .ICO(mult_x_219_n95), .CO(mult_x_219_n96) );
CMPR42X1TS mult_x_219_U54 ( .A(mult_x_219_n106), .B(mult_x_219_n103), .C(
mult_x_219_n104), .D(mult_x_219_n97), .ICI(mult_x_219_n100), .S(
mult_x_219_n94), .ICO(mult_x_219_n92), .CO(mult_x_219_n93) );
CMPR42X1TS mult_x_219_U51 ( .A(mult_x_219_n183), .B(mult_x_219_n159), .C(
mult_x_219_n207), .D(n4962), .ICI(mult_x_219_n90), .S(mult_x_219_n88),
.ICO(mult_x_219_n86), .CO(mult_x_219_n87) );
CMPR42X1TS mult_x_219_U50 ( .A(mult_x_219_n95), .B(mult_x_219_n98), .C(
mult_x_219_n96), .D(mult_x_219_n88), .ICI(mult_x_219_n92), .S(
mult_x_219_n85), .ICO(mult_x_219_n83), .CO(mult_x_219_n84) );
CMPR42X1TS mult_x_219_U47 ( .A(mult_x_219_n170), .B(mult_x_219_n206), .C(
mult_x_219_n194), .D(mult_x_219_n158), .ICI(mult_x_219_n89), .S(
mult_x_219_n78), .ICO(mult_x_219_n76), .CO(mult_x_219_n77) );
CMPR42X1TS mult_x_219_U46 ( .A(mult_x_219_n86), .B(mult_x_219_n80), .C(
mult_x_219_n87), .D(mult_x_219_n78), .ICI(mult_x_219_n83), .S(
mult_x_219_n75), .ICO(mult_x_219_n73), .CO(mult_x_219_n74) );
CMPR42X1TS mult_x_219_U44 ( .A(mult_x_219_n169), .B(mult_x_219_n157), .C(
mult_x_219_n193), .D(mult_x_219_n205), .ICI(mult_x_219_n72), .S(
mult_x_219_n70), .ICO(mult_x_219_n68), .CO(mult_x_219_n69) );
CMPR42X1TS mult_x_219_U43 ( .A(mult_x_219_n76), .B(mult_x_219_n79), .C(
mult_x_219_n77), .D(mult_x_219_n70), .ICI(mult_x_219_n73), .S(
mult_x_219_n67), .ICO(mult_x_219_n65), .CO(mult_x_219_n66) );
CMPR42X1TS mult_x_219_U41 ( .A(n5032), .B(mult_x_219_n168), .C(
mult_x_219_n180), .D(mult_x_219_n156), .ICI(mult_x_219_n192), .S(
mult_x_219_n62), .ICO(mult_x_219_n60), .CO(mult_x_219_n61) );
CMPR42X1TS mult_x_219_U40 ( .A(mult_x_219_n68), .B(mult_x_219_n71), .C(
mult_x_219_n69), .D(mult_x_219_n62), .ICI(mult_x_219_n65), .S(
mult_x_219_n59), .ICO(mult_x_219_n57), .CO(mult_x_219_n58) );
CMPR42X1TS mult_x_219_U39 ( .A(n2194), .B(FPMULT_Op_MY[17]), .C(
mult_x_219_n179), .D(mult_x_219_n167), .ICI(mult_x_219_n155), .S(
mult_x_219_n56), .ICO(mult_x_219_n54), .CO(mult_x_219_n55) );
CMPR42X1TS mult_x_219_U38 ( .A(mult_x_219_n191), .B(mult_x_219_n60), .C(
mult_x_219_n61), .D(mult_x_219_n56), .ICI(mult_x_219_n57), .S(
mult_x_219_n53), .ICO(mult_x_219_n51), .CO(mult_x_219_n52) );
CMPR42X1TS mult_x_219_U35 ( .A(mult_x_219_n154), .B(mult_x_219_n54), .C(
mult_x_219_n48), .D(mult_x_219_n55), .ICI(mult_x_219_n51), .S(
mult_x_219_n46), .ICO(mult_x_219_n44), .CO(mult_x_219_n45) );
CMPR42X1TS mult_x_219_U33 ( .A(mult_x_219_n153), .B(mult_x_219_n177), .C(
mult_x_219_n43), .D(mult_x_219_n47), .ICI(mult_x_219_n44), .S(
mult_x_219_n41), .ICO(mult_x_219_n39), .CO(mult_x_219_n40) );
CMPR42X1TS mult_x_219_U31 ( .A(n5031), .B(mult_x_219_n164), .C(
mult_x_219_n152), .D(mult_x_219_n42), .ICI(mult_x_219_n39), .S(
mult_x_219_n36), .ICO(mult_x_219_n34), .CO(mult_x_219_n35) );
CMPR42X1TS mult_x_219_U30 ( .A(FPMULT_Op_MY[20]), .B(FPMULT_Op_MY[21]), .C(
mult_x_219_n151), .D(mult_x_219_n163), .ICI(mult_x_219_n34), .S(
mult_x_219_n33), .ICO(mult_x_219_n31), .CO(mult_x_219_n32) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_8_ ( .D(n1595), .CK(n5385),
.RN(n5347), .Q(FPMULT_exp_oper_result[8]), .QN(n5249) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_26_ ( .D(n1850), .CK(n5433), .RN(n5331),
.Q(FPSENCOS_d_ff3_sh_y_out[26]), .QN(n5248) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_25_ ( .D(n1851), .CK(n5432), .RN(n5319),
.Q(FPSENCOS_d_ff3_sh_y_out[25]), .QN(n5247) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_24_ ( .D(n1852), .CK(n5432), .RN(n5318),
.Q(FPSENCOS_d_ff3_sh_y_out[24]), .QN(n5246) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_12_ ( .D(n1882), .CK(n5462), .RN(n5297),
.Q(FPSENCOS_d_ff3_sh_y_out[12]), .QN(n5244) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_10_ ( .D(n1886), .CK(n5460), .RN(n5298),
.Q(FPSENCOS_d_ff3_sh_y_out[10]), .QN(n5243) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_9_ ( .D(n1888), .CK(n5442), .RN(n5314),
.Q(FPSENCOS_d_ff3_sh_y_out[9]), .QN(n5242) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_8_ ( .D(n1890), .CK(n5457), .RN(n5300),
.Q(FPSENCOS_d_ff3_sh_y_out[8]), .QN(n5241) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_6_ ( .D(n1894), .CK(n5456), .RN(n5328),
.Q(FPSENCOS_d_ff3_sh_y_out[6]), .QN(n5240) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_4_ ( .D(n1898), .CK(n5452), .RN(n5303),
.Q(FPSENCOS_d_ff3_sh_y_out[4]), .QN(n5239) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_2_ ( .D(n1902), .CK(n5449), .RN(n5317),
.Q(FPSENCOS_d_ff3_sh_y_out[2]), .QN(n5238) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_1_ ( .D(n1904), .CK(n5459), .RN(n5315),
.Q(FPSENCOS_d_ff3_sh_y_out[1]), .QN(n5237) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_0_ ( .D(n1906), .CK(n5450), .RN(n5315),
.Q(FPSENCOS_d_ff3_sh_y_out[0]), .QN(n5236) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_9_ ( .D(n2124), .CK(n5433), .RN(n5320), .Q(
FPSENCOS_d_ff3_LUT_out[9]), .QN(n5235) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_7_ ( .D(n2126), .CK(n5429), .RN(n5320), .Q(
FPSENCOS_d_ff3_LUT_out[7]), .QN(n5234) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n1614), .CK(n5381),
.RN(n5352), .Q(FPMULT_Add_result[6]), .QN(n5233) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_31_ ( .D(n1943), .CK(n5441),
.RN(n5296), .Q(FPSENCOS_d_ff2_X[31]), .QN(n5232) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_22_ ( .D(n1961), .CK(n5423),
.RN(n5329), .Q(FPSENCOS_d_ff2_X[22]), .QN(n5231) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_21_ ( .D(n1963), .CK(n5445),
.RN(n5332), .Q(FPSENCOS_d_ff2_X[21]), .QN(n5230) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_15_ ( .D(n1975), .CK(n5457),
.RN(n5311), .Q(FPSENCOS_d_ff2_X[15]), .QN(n5229) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_11_ ( .D(n1983), .CK(n2656),
.RN(n5299), .Q(FPSENCOS_d_ff2_X[11]), .QN(n5228) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_9_ ( .D(n1987), .CK(n5442), .RN(
n5313), .Q(FPSENCOS_d_ff2_X[9]), .QN(n5227) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_8_ ( .D(n1989), .CK(n5457), .RN(
n5300), .Q(FPSENCOS_d_ff2_X[8]), .QN(n5226) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_4_ ( .D(n1997), .CK(n5452), .RN(
n5302), .Q(FPSENCOS_d_ff2_X[4]), .QN(n5225) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_0_ ( .D(n2005), .CK(n5463), .RN(
n5315), .Q(FPSENCOS_d_ff2_X[0]), .QN(n5224) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n1508), .CK(
n5455), .RN(n5344), .Q(FPMULT_Sgf_normalized_result[3]), .QN(n5223) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n1512), .CK(
n2669), .RN(n5345), .Q(FPMULT_Sgf_normalized_result[7]), .QN(n5222) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n1520), .CK(
n5369), .RN(n5345), .Q(FPMULT_Sgf_normalized_result[15]), .QN(n5221)
);
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n1522), .CK(
n5437), .RN(n5346), .Q(FPMULT_Sgf_normalized_result[17]), .QN(n5220)
);
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_30_ ( .D(n1952), .CK(n5421),
.RN(n5329), .Q(FPSENCOS_d_ff2_X[30]), .QN(n5219) );
DFFRX1TS FPMULT_Sel_B_Q_reg_0_ ( .D(n1623), .CK(n5385), .RN(n5348), .Q(
FPMULT_FSM_selector_B[0]), .QN(n5218) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n1507), .CK(
n5440), .RN(n5344), .Q(FPMULT_Sgf_normalized_result[2]), .QN(n5217) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n2149), .CK(
n5429), .RN(n5255), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]),
.QN(n5216) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n1608), .CK(n5393),
.RN(n5352), .Q(FPMULT_Add_result[12]), .QN(n5215) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n1283), .CK(n5377), .RN(
n5280), .Q(FPADDSUB_DmP_mant_SHT1_SW[9]), .QN(n5214) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n1270), .CK(n5387),
.RN(n5282), .Q(FPADDSUB_DmP_mant_SHT1_SW[12]), .QN(n5213) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_), .CK(n5429), .RN(n5255),
.Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n5212) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n1621), .CK(
n5377), .RN(n5346), .Q(FPMULT_Sgf_normalized_result[23]), .QN(n5211)
);
DFFRX1TS FPSENCOS_reg_region_flag_Q_reg_0_ ( .D(n2135), .CK(n5450), .RN(
n5321), .Q(FPSENCOS_d_ff1_shift_region_flag_out[0]), .QN(n5210) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n1843), .CK(n5383),
.RN(n5264), .Q(FPADDSUB_intDY_EWSW[0]), .QN(n5209) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n1476), .CK(n2336),
.RN(n5265), .Q(FPADDSUB_Shift_amount_SHT1_EWR[1]), .QN(n5208) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_26_ ( .D(n2114), .CK(n5432), .RN(n5322), .Q(
FPSENCOS_d_ff3_LUT_out[26]), .QN(n5207) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n1668), .CK(
n5390), .RN(n5355), .Q(FPMULT_Op_MX[10]), .QN(n5206) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_2_ ( .D(n1690), .CK(n5431), .RN(
n5319), .Q(FPMULT_FS_Module_state_reg[2]), .QN(n5205) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n1311), .CK(n2656), .RN(
n5278), .Q(FPADDSUB_DmP_mant_SHT1_SW[2]), .QN(n5204) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n1379), .CK(n5404),
.RN(n5272), .Q(FPADDSUB_DmP_mant_SHT1_SW[13]), .QN(n5203) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n1388), .CK(n2660),
.RN(n5271), .Q(FPADDSUB_DmP_mant_SHT1_SW[17]), .QN(n5202) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n1394), .CK(n5404),
.RN(n5271), .Q(FPADDSUB_DmP_mant_SHT1_SW[19]), .QN(n5201) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n1391), .CK(n5413),
.RN(n5271), .Q(FPADDSUB_DmP_mant_SHT1_SW[20]), .QN(n5200) );
DFFRXLTS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_47_ ( .D(n1694),
.CK(n5434), .RN(n5310), .Q(FPMULT_P_Sgf[47]), .QN(n5199) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_25_ ( .D(n1415), .CK(n5404), .RN(n5269), .Q(FPADDSUB_DmP_EXP_EWSW[25]), .QN(n5198) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n1913), .CK(n5419),
.RN(n5256), .Q(FPADDSUB_intDX_EWSW[28]), .QN(n5197) );
DFFRX2TS FPADDSUB_inst_ShiftRegister_Q_reg_4_ ( .D(n2146), .CK(n5450), .RN(
n5255), .Q(n4938), .QN(n5196) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n1466), .CK(n5369), .RN(
n5292), .Q(result_add_subt[30]), .QN(n5195) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n1473), .CK(n2336), .RN(
n5291), .Q(result_add_subt[23]), .QN(n5194) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n1840), .CK(n5437),
.RN(n5262), .Q(FPADDSUB_intDY_EWSW[3]), .QN(n5193) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n1344), .CK(n2660), .RN(
n5294), .Q(FPADDSUB_Raw_mant_NRM_SWR[5]), .QN(n5192) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n2191), .CK(
n5444), .RN(n5255), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]),
.QN(n5191) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_28_ ( .D(n1856), .CK(n5419),
.RN(n5322), .Q(FPSENCOS_d_ff2_Y[28]), .QN(n5190) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n1934), .CK(n5450),
.RN(n5263), .Q(FPADDSUB_intDX_EWSW[7]), .QN(n5189) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_23_ ( .D(n1853), .CK(n5432), .RN(n2404),
.QN(n5188) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n1603), .CK(n5384),
.RN(n5353), .Q(FPMULT_Add_result[17]), .QN(n5187) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n1819), .CK(n5420),
.RN(n5256), .Q(FPADDSUB_intDY_EWSW[24]), .QN(n5186) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n1837), .CK(n5435),
.RN(n5260), .Q(FPADDSUB_intDY_EWSW[6]), .QN(n5185) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n1833), .CK(n5460),
.RN(n5261), .Q(FPADDSUB_intDY_EWSW[10]), .QN(n5184) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n1820), .CK(n5422),
.RN(n5256), .Q(FPADDSUB_intDY_EWSW[23]), .QN(n5183) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n1911), .CK(n5423),
.RN(n5256), .Q(FPADDSUB_intDX_EWSW[30]), .QN(n5182) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]), .CK(n5428), .RN(n5322),
.Q(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .QN(n5181) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n1337), .CK(n5378), .RN(
n2410), .Q(FPADDSUB_Raw_mant_NRM_SWR[12]), .QN(n5180) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_19_ ( .D(n1222), .CK(n5398), .RN(n5286), .Q(FPADDSUB_DMP_SFG[19]), .QN(n5179) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n1915), .CK(n5414),
.RN(n5256), .Q(FPADDSUB_intDX_EWSW[26]), .QN(n5178) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n1525), .CK(
n5377), .RN(n5346), .Q(FPMULT_Sgf_normalized_result[20]), .QN(n5177)
);
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n1523), .CK(
n5377), .RN(n5346), .Q(FPMULT_Sgf_normalized_result[18]), .QN(n5176)
);
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n1521), .CK(
n2662), .RN(n5346), .Q(FPMULT_Sgf_normalized_result[16]), .QN(n5175)
);
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n1517), .CK(
n2664), .RN(n5345), .Q(FPMULT_Sgf_normalized_result[12]), .QN(n5174)
);
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n1513), .CK(
n5366), .RN(n5345), .Q(FPMULT_Sgf_normalized_result[8]), .QN(n5173) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_13_ ( .D(n1242), .CK(n5396), .RN(n5284), .Q(FPADDSUB_DMP_SFG[13]), .QN(n5172) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n1197), .CK(n5401), .RN(
n5289), .Q(FPADDSUB_DmP_mant_SFG_SWR[8]), .QN(n5171) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n1198), .CK(n5400), .RN(
n5289), .Q(FPADDSUB_DmP_mant_SFG_SWR[7]), .QN(n5170) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_29_ ( .D(n1953), .CK(n5463),
.RN(n5330), .Q(FPSENCOS_d_ff2_X[29]), .QN(n5168) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_27_ ( .D(n1955), .CK(n2255),
.RN(n5332), .Q(FPSENCOS_d_ff2_X[27]), .QN(n5167) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n1931), .CK(n5460),
.RN(n5261), .Q(FPADDSUB_intDX_EWSW[10]), .QN(n5149) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n1930), .CK(n2666),
.RN(n5261), .Q(FPADDSUB_intDX_EWSW[11]), .QN(n5148) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n1935), .CK(n5367),
.RN(n5260), .Q(FPADDSUB_intDX_EWSW[6]), .QN(n5147) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_10_ ( .D(n1262), .CK(n5394), .RN(n5282), .QN(n5146) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n1823), .CK(n5429),
.RN(n5259), .Q(FPADDSUB_intDY_EWSW[20]), .QN(n5145) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n1180), .CK(n5410), .RN(
n5291), .Q(FPADDSUB_DmP_mant_SFG_SWR[25]), .QN(n5144) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_17_ ( .D(n1230), .CK(n5397), .RN(n5286), .Q(FPADDSUB_DMP_SFG[17]), .QN(n5143) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n1822), .CK(n5424),
.RN(n5258), .Q(FPADDSUB_intDY_EWSW[21]), .QN(n5142) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n1921), .CK(n5428),
.RN(n5259), .Q(FPADDSUB_intDX_EWSW[20]), .QN(n5141) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n1920), .CK(n2668),
.RN(n5258), .Q(FPADDSUB_intDX_EWSW[21]), .QN(n5140) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n1813), .CK(n5420),
.RN(n5257), .Q(FPADDSUB_intDY_EWSW[30]), .QN(n5139) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n1410), .CK(n5406), .RN(
n5269), .Q(FPADDSUB_Raw_mant_NRM_SWR[25]), .QN(n5138) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n1189), .CK(n5401), .RN(
n5290), .Q(FPADDSUB_DmP_mant_SFG_SWR[16]), .QN(n5137) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_18_ ( .D(n1214), .CK(n5363), .RN(n5287), .Q(FPADDSUB_DMP_SFG[18]), .QN(n5136) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_16_ ( .D(n1246), .CK(n5396), .RN(n5284), .Q(FPADDSUB_DMP_SFG[16]), .QN(n5135) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_12_ ( .D(n1266), .CK(n5394), .RN(n5282), .Q(FPADDSUB_DMP_SFG[12]), .QN(n5134) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_9_ ( .D(n1279), .CK(n5451), .RN(n5281),
.Q(FPADDSUB_DMP_SFG[9]), .QN(n5133) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_8_ ( .D(n1250), .CK(n5395), .RN(n5284),
.Q(FPADDSUB_DMP_SFG[8]), .QN(n5132) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_7_ ( .D(n1300), .CK(n5396), .RN(n5279),
.Q(FPADDSUB_DMP_SFG[7]), .QN(n5131) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n1184), .CK(n5361), .RN(
n5290), .Q(FPADDSUB_DmP_mant_SFG_SWR[21]), .QN(n5130) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_28_ ( .D(n1769), .CK(n5419), .RN(n5322),
.Q(FPSENCOS_d_ff_Xn[28]), .QN(n5129) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_11_ ( .D(n1254), .CK(n5395), .RN(n5283), .Q(FPADDSUB_DMP_SFG[11]), .QN(n5128) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_3_ ( .D(n1323), .CK(n5411), .RN(n5277),
.Q(FPADDSUB_DMP_SFG[3]), .QN(n5127) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_22_ ( .D(n1206), .CK(n5400), .RN(n5288), .Q(FPADDSUB_DMP_SFG[22]), .QN(n5126) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n1807), .CK(n5372), .RN(
n5258), .Q(FPADDSUB_Data_array_SWR[20]), .QN(n5125) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n1808), .CK(n5421), .RN(
n5257), .Q(FPADDSUB_Data_array_SWR[21]), .QN(n5124) );
DFFRX2TS FPADDSUB_inst_ShiftRegister_Q_reg_1_ ( .D(n2143), .CK(n5444), .RN(
n5294), .Q(FPADDSUB_Shift_reg_FLAGS_7[1]), .QN(n4958) );
DFFRX2TS FPADDSUB_inst_ShiftRegister_Q_reg_2_ ( .D(n2144), .CK(n5428), .RN(
n5255), .Q(FPADDSUB_Shift_reg_FLAGS_7[2]), .QN(n4985) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n2079), .CK(n2376),
.RN(n5262), .Q(FPADDSUB_bit_shift_SHT2), .QN(n5123) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_0_ ( .D(n1293), .CK(n5459), .RN(n5279),
.Q(FPADDSUB_DMP_SFG[0]), .QN(n5122) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n1509), .CK(
n5463), .RN(n5344), .Q(FPMULT_Sgf_normalized_result[4]), .QN(n5121) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n1356), .CK(n2334), .RN(
n5275), .Q(result_add_subt[31]), .QN(n5120) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n1662), .CK(n2659), .RN(n5354), .Q(FPMULT_Op_MX[4]), .QN(n5119) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_23_ ( .D(n1959), .CK(n5416),
.RN(n5334), .Q(FPSENCOS_d_ff2_X[23]), .QN(n5118) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_4_ ( .D(n1234), .CK(n5397), .RN(n5285),
.Q(FPADDSUB_DMP_SFG[4]), .QN(n5117) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_8_ ( .D(n1666), .CK(n5377), .RN(n5354), .Q(FPMULT_Op_MX[8]), .QN(n5116) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n1601), .CK(n5379),
.RN(n5353), .QN(n5115) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_2_ ( .D(n1660), .CK(n5380), .RN(n5354), .Q(FPMULT_Op_MX[2]), .QN(n5114) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n1939), .CK(n5373),
.RN(n5263), .Q(FPADDSUB_intDX_EWSW[2]), .QN(n5113) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n1810), .CK(n5444), .RN(
n5263), .Q(FPADDSUB_Data_array_SWR[23]), .QN(n5112) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n1611), .CK(n5386),
.RN(n5352), .QN(n5111) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n1607), .CK(n5382),
.RN(n5352), .QN(n5110) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n1937), .CK(n5443),
.RN(n5259), .Q(FPADDSUB_intDX_EWSW[4]), .QN(n5109) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n1511), .CK(
n5399), .RN(n5345), .Q(FPMULT_Sgf_normalized_result[6]), .QN(n5108) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n1515), .CK(
n2669), .RN(n5345), .Q(FPMULT_Sgf_normalized_result[10]), .QN(n5107)
);
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n1519), .CK(
n2664), .RN(n5345), .Q(FPMULT_Sgf_normalized_result[14]), .QN(n5106)
);
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n1941), .CK(n5463),
.RN(n5264), .Q(FPADDSUB_intDX_EWSW[0]), .QN(n5105) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n1619), .CK(n5379),
.RN(n5351), .QN(n5104) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n1285), .CK(n5443), .RN(
n5280), .Q(result_add_subt[9]), .QN(n5103) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n1299), .CK(n5390), .RN(
n5279), .Q(result_add_subt[0]), .QN(n5102) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n1372), .CK(n5407), .RN(
n5273), .Q(result_add_subt[11]), .QN(n5101) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n1375), .CK(n5407), .RN(
n5273), .Q(result_add_subt[8]), .QN(n5100) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n1387), .CK(n5404), .RN(
n5272), .Q(result_add_subt[4]), .QN(n5099) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n1399), .CK(n5405), .RN(
n5270), .Q(result_add_subt[21]), .QN(n5098) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n1402), .CK(n5406), .RN(
n5270), .Q(result_add_subt[18]), .QN(n5097) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n1405), .CK(n5409), .RN(
n5270), .Q(result_add_subt[15]), .QN(n5096) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n1408), .CK(n5403), .RN(
n5269), .Q(result_add_subt[22]), .QN(n5095) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n1467), .CK(n2662), .RN(
n5291), .Q(result_add_subt[29]), .QN(n5094) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n1469), .CK(n2336), .RN(
n5291), .Q(result_add_subt[27]), .QN(n5093) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n1471), .CK(n2336), .RN(
n5291), .Q(result_add_subt[25]), .QN(n5092) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n1472), .CK(n2336), .RN(
n5291), .Q(result_add_subt[24]), .QN(n5091) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n1828), .CK(n5420),
.RN(n5257), .Q(FPADDSUB_intDY_EWSW[15]), .QN(n5090) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n1599), .CK(n5386),
.RN(n5353), .QN(n5089) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n1801), .CK(n5377), .RN(
n5260), .Q(FPADDSUB_Data_array_SWR[14]), .QN(n5088) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n1925), .CK(n5454),
.RN(n5260), .Q(FPADDSUB_intDX_EWSW[16]), .QN(n5087) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n1331), .CK(n5399), .RN(
n5276), .Q(FPADDSUB_Raw_mant_NRM_SWR[18]), .QN(n5086) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n1938), .CK(n5410),
.RN(n5263), .Q(FPADDSUB_intDX_EWSW[3]), .QN(n5085) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n1348), .CK(n5406), .RN(
n5275), .Q(FPADDSUB_Raw_mant_NRM_SWR[1]), .QN(n5084) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n1201), .CK(n5400), .RN(
n5289), .Q(FPADDSUB_DmP_mant_SFG_SWR[4]), .QN(n5083) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n1202), .CK(n5400), .RN(
n5288), .Q(FPADDSUB_DmP_mant_SFG_SWR[3]), .QN(n5082) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n2077), .CK(n5454),
.RN(n5263), .Q(FPADDSUB_shift_value_SHT2_EWR[2]), .QN(n5081) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_16_ ( .D(n1674), .CK(
n5364), .RN(n5355), .Q(FPMULT_Op_MX[16]), .QN(n5080) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_12_ ( .D(n1670), .CK(
n5454), .RN(n5355), .Q(FPMULT_Op_MX[12]), .QN(n5077) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n1929), .CK(n5461),
.RN(n5262), .Q(FPADDSUB_intDX_EWSW[12]), .QN(n5076) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n1182), .CK(n5365), .RN(
n5290), .Q(FPADDSUB_DmP_mant_SFG_SWR[23]), .QN(n5075) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n1183), .CK(n5366), .RN(
n5290), .Q(FPADDSUB_DmP_mant_SFG_SWR[22]), .QN(n5074) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n1188), .CK(n5401), .RN(
n5290), .Q(FPADDSUB_DmP_mant_SFG_SWR[17]), .QN(n5073) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n1830), .CK(n5456),
.RN(n5260), .Q(FPADDSUB_intDY_EWSW[13]), .QN(n5072) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n1470), .CK(n2336), .RN(
n5291), .Q(result_add_subt[26]), .QN(n5071) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n1278), .CK(n5437), .RN(
n5281), .Q(result_add_subt[5]), .QN(n5070) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n1292), .CK(n5441), .RN(
n5279), .Q(result_add_subt[1]), .QN(n5069) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n1306), .CK(n5413), .RN(
n5278), .Q(result_add_subt[7]), .QN(n5068) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n1313), .CK(n5375), .RN(
n5277), .Q(result_add_subt[2]), .QN(n5067) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n1329), .CK(n5411), .RN(
n5276), .Q(result_add_subt[3]), .QN(n5066) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n1363), .CK(n5408), .RN(
n5274), .Q(result_add_subt[12]), .QN(n5065) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n1366), .CK(n5373), .RN(
n5274), .Q(result_add_subt[10]), .QN(n5064) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n1369), .CK(n5407), .RN(
n5273), .Q(result_add_subt[14]), .QN(n5063) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n1378), .CK(n5407), .RN(
n5272), .Q(result_add_subt[16]), .QN(n5062) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n1381), .CK(n5413), .RN(
n5272), .Q(result_add_subt[13]), .QN(n5061) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n1384), .CK(n2660), .RN(
n5272), .Q(result_add_subt[6]), .QN(n5060) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n1390), .CK(n5404), .RN(
n5271), .Q(result_add_subt[17]), .QN(n5059) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n1393), .CK(n5413), .RN(
n5271), .Q(result_add_subt[20]), .QN(n5058) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n1396), .CK(n2660), .RN(
n5271), .Q(result_add_subt[19]), .QN(n5057) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n1332), .CK(n2665), .RN(
n5276), .Q(FPADDSUB_Raw_mant_NRM_SWR[17]), .QN(n5056) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_3_ ( .D(n2138), .CK(n5444), .RN(n5313),
.Q(FPSENCOS_cont_iter_out[3]), .QN(n5055) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_18_ ( .D(n1676), .CK(
n2666), .RN(n5355), .Q(FPMULT_Op_MX[18]), .QN(n5054) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_1_ ( .D(n2136), .CK(n5439), .RN(n5321),
.Q(FPSENCOS_cont_var_out[1]), .QN(n5053) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_0_ ( .D(n1692), .CK(n2373), .RN(
n2408), .Q(FPMULT_FS_Module_state_reg[0]), .QN(n5052) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_20_ ( .D(n1678), .CK(
n5378), .RN(n5356), .Q(FPMULT_Op_MX[20]), .QN(n5048) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_0_ ( .D(n2141), .CK(n5439), .RN(n5307),
.Q(FPSENCOS_cont_iter_out[0]), .QN(n5044) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_1_ ( .D(n1627), .CK(n5385), .RN(n5348), .Q(FPMULT_Op_MY[1]), .QN(n5043) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n1632), .CK(n2654), .RN(n5348), .Q(FPMULT_Op_MY[6]), .QN(n5042) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_3_ ( .D(n1629), .CK(n5381), .RN(n5348), .Q(FPMULT_Op_MY[3]), .QN(n5041) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n1633), .CK(n5382), .RN(n5348), .Q(FPMULT_Op_MY[7]), .QN(n5040) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_5_ ( .D(n1631), .CK(n5386), .RN(n5348), .Q(FPMULT_Op_MY[5]), .QN(n5038) );
DFFRX2TS FPMULT_Sel_B_Q_reg_1_ ( .D(n1622), .CK(n5385), .RN(n5347), .Q(
FPMULT_FSM_selector_B[1]), .QN(n5036) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n1635), .CK(n5388), .RN(n5349), .Q(FPMULT_Op_MY[9]), .QN(n5035) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_14_ ( .D(n1640), .CK(
n5455), .RN(n5349), .Q(FPMULT_Op_MY[14]), .QN(n5034) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_19_ ( .D(n1645), .CK(
n5363), .RN(n5350), .Q(FPMULT_Op_MY[19]), .QN(n5033) );
DFFRX2TS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n1352), .CK(n5405), .RN(
n5275), .Q(FPADDSUB_OP_FLAG_SFG), .QN(n5030) );
DFFRX1TS FPADDSUB_inst_ShiftRegister_Q_reg_0_ ( .D(n2142), .CK(n5428), .RN(
n5292), .Q(n4951), .QN(n5250) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_18_ ( .D(n1969), .CK(n5424),
.RN(n5327), .Q(FPSENCOS_d_ff2_X[18]), .QN(n5025) );
DFFRX1TS FPSENCOS_reg_region_flag_Q_reg_1_ ( .D(n2134), .CK(n5427), .RN(
n5321), .Q(FPSENCOS_d_ff1_shift_region_flag_out[1]), .QN(n5024) );
DFFRX2TS FPMULT_Sel_A_Q_reg_0_ ( .D(n1689), .CK(n5446), .RN(n5341), .Q(
FPMULT_FSM_selector_A), .QN(n5022) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n1346), .CK(n5403), .RN(
n5275), .Q(FPADDSUB_Raw_mant_NRM_SWR[3]), .QN(n5021) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n1338), .CK(n5367), .RN(
n2411), .Q(FPADDSUB_Raw_mant_NRM_SWR[11]), .QN(n5019) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n1597), .CK(n5376),
.RN(n5351), .Q(FPMULT_Add_result[23]), .QN(n5018) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n1825), .CK(n2334),
.RN(n5258), .Q(FPADDSUB_intDY_EWSW[18]), .QN(n5017) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n1321), .CK(n5411), .RN(
n5277), .Q(FPADDSUB_Raw_mant_NRM_SWR[19]), .QN(n5016) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n1917), .CK(n2374),
.RN(n5256), .Q(FPADDSUB_intDX_EWSW[24]), .QN(n5015) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n1339), .CK(n5361), .RN(
n2405), .Q(FPADDSUB_Raw_mant_NRM_SWR[10]), .QN(n5014) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n1923), .CK(n5424),
.RN(n5258), .Q(FPADDSUB_intDX_EWSW[18]), .QN(n5013) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n1817), .CK(n5447),
.RN(n5257), .Q(FPADDSUB_intDY_EWSW[26]), .QN(n5012) );
DFFRX1TS FPMULT_Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n1625), .CK(
n5385), .RN(n5348), .Q(FPMULT_zero_flag), .QN(n5011) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n1185), .CK(n5408), .RN(
n5290), .Q(FPADDSUB_DmP_mant_SFG_SWR[20]), .QN(n5010) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n1186), .CK(n5402), .RN(
n5290), .Q(FPADDSUB_DmP_mant_SFG_SWR[19]), .QN(n5009) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n1187), .CK(n5367), .RN(
n5290), .Q(FPADDSUB_DmP_mant_SFG_SWR[18]), .QN(n5008) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n1191), .CK(n5401), .RN(
n5290), .Q(FPADDSUB_DmP_mant_SFG_SWR[14]), .QN(n5007) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n1194), .CK(n5401), .RN(
n5289), .Q(FPADDSUB_DmP_mant_SFG_SWR[11]), .QN(n5006) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n1195), .CK(n5401), .RN(
n5289), .Q(FPADDSUB_DmP_mant_SFG_SWR[10]), .QN(n5005) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_29_ ( .D(n1766), .CK(n5424), .RN(n5330),
.Q(FPSENCOS_d_ff_Xn[29]), .QN(n5004) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_27_ ( .D(n1772), .CK(n5414), .RN(n5332),
.Q(FPSENCOS_d_ff_Xn[27]), .QN(n5003) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_26_ ( .D(n1775), .CK(n5418), .RN(n5332),
.Q(FPSENCOS_d_ff_Xn[26]), .QN(n5002) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_25_ ( .D(n1778), .CK(n5418), .RN(n5333),
.Q(FPSENCOS_d_ff_Xn[25]), .QN(n5001) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_24_ ( .D(n1781), .CK(n2374), .RN(n5334),
.Q(FPSENCOS_d_ff_Xn[24]), .QN(n5000) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_20_ ( .D(n2012), .CK(n5430), .RN(n5304),
.Q(FPSENCOS_d_ff_Xn[20]), .QN(n4999) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_19_ ( .D(n2015), .CK(n5410), .RN(n5305),
.Q(FPSENCOS_d_ff_Xn[19]), .QN(n4998) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_17_ ( .D(n2021), .CK(n2659), .RN(n5303),
.Q(FPSENCOS_d_ff_Xn[17]), .QN(n4997) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_16_ ( .D(n2024), .CK(n5361), .RN(n5338),
.Q(FPSENCOS_d_ff_Xn[16]), .QN(n4996) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_14_ ( .D(n2030), .CK(n5459), .RN(n5299),
.Q(FPSENCOS_d_ff_Xn[14]), .QN(n4995) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_13_ ( .D(n2033), .CK(n5361), .RN(n5301),
.Q(FPSENCOS_d_ff_Xn[13]), .QN(n4994) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_12_ ( .D(n2036), .CK(n5461), .RN(n5297),
.Q(FPSENCOS_d_ff_Xn[12]), .QN(n4993) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_10_ ( .D(n2042), .CK(n5460), .RN(n5298),
.Q(FPSENCOS_d_ff_Xn[10]), .QN(n4992) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_7_ ( .D(n2051), .CK(n5438), .RN(n5318), .Q(
FPSENCOS_d_ff_Xn[7]), .QN(n4991) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_6_ ( .D(n2054), .CK(n5453), .RN(n5328), .Q(
FPSENCOS_d_ff_Xn[6]), .QN(n4990) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_5_ ( .D(n2057), .CK(n5443), .RN(n5313), .Q(
FPSENCOS_d_ff_Xn[5]), .QN(n4989) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_3_ ( .D(n2063), .CK(n5369), .RN(n5295), .Q(
FPSENCOS_d_ff_Xn[3]), .QN(n4988) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_2_ ( .D(n2066), .CK(n5369), .RN(n5317), .Q(
FPSENCOS_d_ff_Xn[2]), .QN(n4987) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_1_ ( .D(n2069), .CK(n5459), .RN(n5314), .Q(
FPSENCOS_d_ff_Xn[1]), .QN(n4986) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n1914), .CK(n2668),
.RN(n5256), .Q(FPADDSUB_intDX_EWSW[27]), .QN(n4983) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_23_ ( .D(n1465), .CK(n5377), .RN(n5266), .Q(FPADDSUB_DMP_EXP_EWSW[23]), .QN(n4982) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n1832), .CK(n5402),
.RN(n5261), .Q(FPADDSUB_intDY_EWSW[11]), .QN(n4981) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n1196), .CK(n5401), .RN(
n5289), .Q(FPADDSUB_DmP_mant_SFG_SWR[9]), .QN(n4980) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n1814), .CK(n5447),
.RN(n5257), .Q(FPADDSUB_intDY_EWSW[29]), .QN(n4979) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n1836), .CK(n5429),
.RN(n5263), .Q(FPADDSUB_intDY_EWSW[7]), .QN(n4978) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n1200), .CK(n5400), .RN(
n5289), .Q(FPADDSUB_DmP_mant_SFG_SWR[5]), .QN(n4977) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n1468), .CK(n2336), .RN(
n5291), .Q(result_add_subt[28]), .QN(n4976) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n1811), .CK(n5431), .RN(
n5263), .Q(FPADDSUB_Data_array_SWR[24]), .QN(n4975) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n1315), .CK(n5453), .RN(
n5277), .Q(FPADDSUB_Raw_mant_NRM_SWR[24]), .QN(n4974) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n1181), .CK(n5412), .RN(
n5291), .Q(FPADDSUB_DmP_mant_SFG_SWR[24]), .QN(n4973) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n1192), .CK(n5401), .RN(
n5289), .Q(FPADDSUB_DmP_mant_SFG_SWR[13]), .QN(n4972) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n1812), .CK(n5362), .RN(
n5263), .Q(FPADDSUB_Data_array_SWR[25]), .QN(n4971) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n1829), .CK(n5441),
.RN(n5261), .Q(FPADDSUB_intDY_EWSW[14]), .QN(n4970) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n1190), .CK(n5401), .RN(
n5290), .Q(FPADDSUB_DmP_mant_SFG_SWR[15]), .QN(n4969) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n1193), .CK(n5401), .RN(
n5289), .Q(FPADDSUB_DmP_mant_SFG_SWR[12]), .QN(n4968) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_28_ ( .D(n1954), .CK(n5419),
.RN(n2404), .QN(n4967) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n1821), .CK(n5420),
.RN(n5257), .Q(FPADDSUB_intDY_EWSW[22]), .QN(n4966) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_3_ ( .D(n1693), .CK(n5434), .RN(
n5318), .Q(FPMULT_FS_Module_state_reg[3]), .QN(n4965) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n1345), .CK(n2660), .RN(
n2412), .QN(n4964) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_2_ ( .D(n2139), .CK(n5427), .RN(n5331),
.Q(FPSENCOS_cont_iter_out[2]), .QN(n4963) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_13_ ( .D(n1671), .CK(
n2664), .RN(n5355), .Q(FPMULT_Op_MX[13]), .QN(n4962) );
DFFRX1TS FPSENCOS_reg_operation_Q_reg_0_ ( .D(n2080), .CK(n5416), .RN(n5335),
.Q(FPSENCOS_d_ff1_operation_out), .QN(n4954) );
DFFRX1TS FPADDSUB_EXP_STAGE_DmP_Q_reg_26_ ( .D(n1414), .CK(n5409), .RN(n5269), .QN(n4953) );
DFFRX1TS FPADDSUB_EXP_STAGE_DmP_Q_reg_24_ ( .D(n1416), .CK(n5403), .RN(n5269), .QN(n4952) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n1918), .CK(n5416),
.RN(n5255), .Q(FPADDSUB_intDX_EWSW[23]), .QN(n4950) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n1343), .CK(n5405), .RN(
n5294), .Q(FPADDSUB_Raw_mant_NRM_SWR[6]), .QN(n4949) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n1334), .CK(n2664), .RN(
n5276), .Q(FPADDSUB_Raw_mant_NRM_SWR[15]), .QN(n4948) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n1818), .CK(n5421),
.RN(n5256), .Q(FPADDSUB_intDY_EWSW[25]), .QN(n4947) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n1335), .CK(n5408), .RN(
n5276), .Q(FPADDSUB_Raw_mant_NRM_SWR[14]), .QN(n4946) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n1317), .CK(n5454), .RN(
n5277), .Q(FPADDSUB_Raw_mant_NRM_SWR[22]), .QN(n4945) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n1936), .CK(n5402),
.RN(n5264), .Q(FPADDSUB_intDX_EWSW[5]), .QN(n4944) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n1319), .CK(n5408), .RN(
n5277), .Q(FPADDSUB_Raw_mant_NRM_SWR[21]), .QN(n4943) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n1824), .CK(n5453),
.RN(n5258), .Q(FPADDSUB_intDY_EWSW[19]), .QN(n4942) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n1924), .CK(n5451),
.RN(n5259), .Q(FPADDSUB_intDX_EWSW[17]), .QN(n4941) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n1932), .CK(n5456),
.RN(n5264), .Q(FPADDSUB_intDX_EWSW[9]), .QN(n4940) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n1940), .CK(n5441),
.RN(n5264), .Q(FPADDSUB_intDX_EWSW[1]), .QN(n4939) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_0_ ( .D(n2137), .CK(n5427), .RN(n5321),
.Q(FPSENCOS_cont_var_out[0]), .QN(n4937) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_1_ ( .D(n1691), .CK(n5438), .RN(
n5317), .Q(FPMULT_FS_Module_state_reg[1]), .QN(n4936) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n1933), .CK(n5420),
.RN(n5261), .Q(FPADDSUB_intDX_EWSW[8]), .QN(n4930) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n1316), .CK(n5367), .RN(
n5277), .Q(FPADDSUB_Raw_mant_NRM_SWR[23]), .QN(n4929) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_13_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N13), .CK(n5454), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[13]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_14_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N14), .CK(n5364), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[14]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_16_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N16), .CK(n5458), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[16]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_18_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N18), .CK(n5464), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[18]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_20_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N20), .CK(n5361), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[20]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_22_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N22), .CK(n5364), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[22]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_23_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N23), .CK(n2665), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[23]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_0_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N0), .CK(n2664), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[0]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_24_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N24), .CK(n2669), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[24]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_12_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N12), .CK(n5410), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[12]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_25_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N25), .CK(n2664), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[25]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_12_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N12), .CK(n5448), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[12]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_13_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N13), .CK(n5402), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[13]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_14_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N14), .CK(n2665), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[14]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_15_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N15), .CK(n5378), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[15]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_16_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N16), .CK(n5365), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[16]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_17_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N17), .CK(n5448), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[17]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_18_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N18), .CK(n5458), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[18]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_19_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N19), .CK(n5378), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[19]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_20_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N20), .CK(n2665), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[20]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_21_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N21), .CK(n5365), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[21]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_22_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N22), .CK(n5458), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[22]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_23_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N23), .CK(n2665), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[23]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_2_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N2), .CK(n2669), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[2]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_3_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N3), .CK(n5366), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[3]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_4_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N4), .CK(n2664), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[4]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_5_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N5), .CK(n5456), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[5]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_6_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N6), .CK(n5364), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[6]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_7_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N7), .CK(n5378), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[7]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_8_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N8), .CK(n5399), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[8]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_9_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N9), .CK(n2666), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[9]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_10_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N10), .CK(n5443), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[10]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_11_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N11), .CK(n2666), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[11]) );
DFFRXLTS NaN_dff_Q_reg_0_ ( .D(NaN_reg), .CK(n5439), .RN(n5328), .Q(NaN_flag) );
DFFRXLTS reg_dataB_Q_reg_31_ ( .D(Data_2[31]), .CK(n5427), .RN(n5302), .Q(
dataB[31]) );
DFFRXLTS reg_dataA_Q_reg_31_ ( .D(Data_1[31]), .CK(n5426), .RN(n5324), .Q(
dataA[31]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_2_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N2), .CK(n5399), .Q(
FPMULT_Sgf_operation_Result[2]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_3_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N3), .CK(n5366), .Q(
FPMULT_Sgf_operation_Result[3]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_4_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N4), .CK(n2669), .Q(
FPMULT_Sgf_operation_Result[4]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_5_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N5), .CK(n2664), .Q(
FPMULT_Sgf_operation_Result[5]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_6_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N6), .CK(n5399), .Q(
FPMULT_Sgf_operation_Result[6]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_7_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N7), .CK(n5366), .Q(
FPMULT_Sgf_operation_Result[7]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_8_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N8), .CK(n5453), .Q(
FPMULT_Sgf_operation_Result[8]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_9_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N9), .CK(n2669), .Q(
FPMULT_Sgf_operation_Result[9]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_10_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N10), .CK(n5367), .Q(
FPMULT_Sgf_operation_Result[10]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_11_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N11), .CK(n5410), .Q(
FPMULT_Sgf_operation_Result[11]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_1_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N1), .CK(n5372), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[1]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_4_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N4), .CK(n5364), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[4]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_1_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N1), .CK(n5458), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[1]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_14_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N14), .CK(n5453), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[14]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_21_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N21), .CK(n5392), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[21]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_22_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N22), .CK(n2659), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[22]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_0_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N0), .CK(n5378), .Q(
FPMULT_Sgf_operation_Result[0]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_1_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N1), .CK(n5399), .Q(
FPMULT_Sgf_operation_Result[1]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_2_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N2), .CK(n2669), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[2]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_3_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N3), .CK(n5362), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[3]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_5_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N5), .CK(n5363), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[5]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_6_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N6), .CK(n5362), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[6]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_15_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N15), .CK(n5367), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[15]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_23_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N23), .CK(n5456), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[23]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n1353), .CK(n5455), .RN(
n5275), .Q(FPADDSUB_OP_FLAG_SHT2) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_3_ ( .D(n1324), .CK(n5411), .RN(n5277), .Q(FPADDSUB_DMP_SHT2_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_2_ ( .D(n1308), .CK(n5403), .RN(n5278), .Q(FPADDSUB_DMP_SHT2_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_7_ ( .D(n1301), .CK(n5405), .RN(n5279), .Q(FPADDSUB_DMP_SHT2_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_0_ ( .D(n1294), .CK(n5391), .RN(n5279), .Q(FPADDSUB_DMP_SHT2_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_1_ ( .D(n1287), .CK(n5391), .RN(n5280), .Q(FPADDSUB_DMP_SHT2_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_9_ ( .D(n1280), .CK(n5368), .RN(n5281), .Q(FPADDSUB_DMP_SHT2_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_5_ ( .D(n1273), .CK(n5393), .RN(n5281), .Q(FPADDSUB_DMP_SHT2_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_12_ ( .D(n1267), .CK(n5379), .RN(
n5282), .Q(FPADDSUB_DMP_SHT2_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_10_ ( .D(n1263), .CK(n5394), .RN(
n5282), .Q(FPADDSUB_DMP_SHT2_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_14_ ( .D(n1259), .CK(n5394), .RN(
n5283), .Q(FPADDSUB_DMP_SHT2_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_11_ ( .D(n1255), .CK(n5395), .RN(
n5283), .Q(FPADDSUB_DMP_SHT2_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_8_ ( .D(n1251), .CK(n5395), .RN(n5284), .Q(FPADDSUB_DMP_SHT2_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_16_ ( .D(n1247), .CK(n5395), .RN(
n5284), .Q(FPADDSUB_DMP_SHT2_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_13_ ( .D(n1243), .CK(n5396), .RN(
n5284), .Q(FPADDSUB_DMP_SHT2_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_6_ ( .D(n1239), .CK(n5396), .RN(n5285), .Q(FPADDSUB_DMP_SHT2_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_4_ ( .D(n1235), .CK(n5397), .RN(n5285), .Q(FPADDSUB_DMP_SHT2_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_17_ ( .D(n1231), .CK(n5397), .RN(
n5286), .Q(FPADDSUB_DMP_SHT2_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_20_ ( .D(n1227), .CK(n5398), .RN(
n5286), .Q(FPADDSUB_DMP_SHT2_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_19_ ( .D(n1223), .CK(n5398), .RN(
n5286), .Q(FPADDSUB_DMP_SHT2_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_21_ ( .D(n1219), .CK(n5398), .RN(
n5287), .Q(FPADDSUB_DMP_SHT2_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_18_ ( .D(n1215), .CK(n5408), .RN(
n5287), .Q(FPADDSUB_DMP_SHT2_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_15_ ( .D(n1211), .CK(n5373), .RN(
n5288), .Q(FPADDSUB_DMP_SHT2_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_22_ ( .D(n1207), .CK(n5400), .RN(
n5288), .Q(FPADDSUB_DMP_SHT2_EWSW[22]) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n1362), .CK(n5408), .RN(
n5274), .Q(FPADDSUB_SIGN_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_23_ ( .D(n1457), .CK(n5443), .RN(
n5266), .Q(FPADDSUB_DMP_SHT1_EWSW[23]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_23_ ( .D(n1456), .CK(n5392), .RN(
n5266), .Q(FPADDSUB_DMP_SHT2_EWSW[23]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_23_ ( .D(n1455), .CK(n5437), .RN(n5267), .Q(FPADDSUB_DMP_SFG[23]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_24_ ( .D(n1452), .CK(n5383), .RN(
n5267), .Q(FPADDSUB_DMP_SHT1_EWSW[24]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_24_ ( .D(n1451), .CK(n5373), .RN(
n5267), .Q(FPADDSUB_DMP_SHT2_EWSW[24]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_24_ ( .D(n1450), .CK(n5368), .RN(n5267), .Q(FPADDSUB_DMP_SFG[24]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_25_ ( .D(n1447), .CK(n2654), .RN(
n5267), .Q(FPADDSUB_DMP_SHT1_EWSW[25]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_25_ ( .D(n1446), .CK(n5386), .RN(
n5267), .Q(FPADDSUB_DMP_SHT2_EWSW[25]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_25_ ( .D(n1445), .CK(n5376), .RN(n5267), .Q(FPADDSUB_DMP_SFG[25]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_26_ ( .D(n1442), .CK(n5389), .RN(
n5267), .Q(FPADDSUB_DMP_SHT1_EWSW[26]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_26_ ( .D(n1441), .CK(n5379), .RN(
n5267), .Q(FPADDSUB_DMP_SHT2_EWSW[26]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_26_ ( .D(n1440), .CK(n5389), .RN(n5267), .Q(FPADDSUB_DMP_SFG[26]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_27_ ( .D(n1437), .CK(n5443), .RN(
n5268), .Q(FPADDSUB_DMP_SHT1_EWSW[27]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_27_ ( .D(n1436), .CK(n5451), .RN(
n5268), .Q(FPADDSUB_DMP_SHT2_EWSW[27]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_27_ ( .D(n1435), .CK(n5451), .RN(n5268), .Q(FPADDSUB_DMP_SFG[27]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_28_ ( .D(n1432), .CK(n5464), .RN(
n5268), .Q(FPADDSUB_DMP_SHT1_EWSW[28]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_28_ ( .D(n1431), .CK(n2659), .RN(
n5268), .Q(FPADDSUB_DMP_SHT2_EWSW[28]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_28_ ( .D(n1430), .CK(n5372), .RN(n5268), .Q(FPADDSUB_DMP_SFG[28]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_29_ ( .D(n1427), .CK(n5369), .RN(
n5268), .Q(FPADDSUB_DMP_SHT1_EWSW[29]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_29_ ( .D(n1426), .CK(n5368), .RN(
n5268), .Q(FPADDSUB_DMP_SHT2_EWSW[29]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_29_ ( .D(n1425), .CK(n5383), .RN(n5268), .Q(FPADDSUB_DMP_SFG[29]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_30_ ( .D(n1422), .CK(n2656), .RN(
n5268), .Q(FPADDSUB_DMP_SHT1_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_30_ ( .D(n1421), .CK(n5458), .RN(
n5269), .Q(FPADDSUB_DMP_SHT2_EWSW[30]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_30_ ( .D(n1420), .CK(n5399), .RN(n5269), .Q(FPADDSUB_DMP_SFG[30]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n1361), .CK(n5449), .RN(
n5274), .Q(FPADDSUB_SIGN_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n1360), .CK(n5442), .RN(
n5274), .Q(FPADDSUB_SIGN_FLAG_SHT2) );
DFFRXLTS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n1359), .CK(n5409), .RN(
n5274), .Q(FPADDSUB_SIGN_FLAG_SFG) );
DFFRXLTS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n1358), .CK(n5435), .RN(
n5274), .Q(FPADDSUB_SIGN_FLAG_NRM) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n1354), .CK(n5456), .RN(
n5275), .Q(FPADDSUB_OP_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_3_ ( .D(n1325), .CK(n5411), .RN(n5276), .Q(FPADDSUB_DMP_SHT1_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_2_ ( .D(n1309), .CK(n5404), .RN(n5278), .Q(FPADDSUB_DMP_SHT1_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_7_ ( .D(n1302), .CK(n5413), .RN(n5278), .Q(FPADDSUB_DMP_SHT1_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_0_ ( .D(n1295), .CK(n5391), .RN(n5279), .Q(FPADDSUB_DMP_SHT1_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_1_ ( .D(n1288), .CK(n5391), .RN(n5280), .Q(FPADDSUB_DMP_SHT1_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_9_ ( .D(n1281), .CK(n5455), .RN(n5281), .Q(FPADDSUB_DMP_SHT1_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_5_ ( .D(n1274), .CK(n5381), .RN(n5281), .Q(FPADDSUB_DMP_SHT1_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_12_ ( .D(n1268), .CK(n5380), .RN(
n5282), .Q(FPADDSUB_DMP_SHT1_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_10_ ( .D(n1264), .CK(n5394), .RN(
n5282), .Q(FPADDSUB_DMP_SHT1_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_14_ ( .D(n1260), .CK(n5394), .RN(
n5283), .Q(FPADDSUB_DMP_SHT1_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_11_ ( .D(n1256), .CK(n5395), .RN(
n5283), .Q(FPADDSUB_DMP_SHT1_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_8_ ( .D(n1252), .CK(n5395), .RN(n5283), .Q(FPADDSUB_DMP_SHT1_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_16_ ( .D(n1248), .CK(n5395), .RN(
n5284), .Q(FPADDSUB_DMP_SHT1_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_13_ ( .D(n1244), .CK(n5396), .RN(
n5284), .Q(FPADDSUB_DMP_SHT1_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_6_ ( .D(n1240), .CK(n5396), .RN(n5285), .Q(FPADDSUB_DMP_SHT1_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_4_ ( .D(n1236), .CK(n5397), .RN(n5285), .Q(FPADDSUB_DMP_SHT1_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_17_ ( .D(n1232), .CK(n5397), .RN(
n5285), .Q(FPADDSUB_DMP_SHT1_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_20_ ( .D(n1228), .CK(n5397), .RN(
n5286), .Q(FPADDSUB_DMP_SHT1_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_19_ ( .D(n1224), .CK(n5398), .RN(
n5286), .Q(FPADDSUB_DMP_SHT1_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_21_ ( .D(n1220), .CK(n5398), .RN(
n5287), .Q(FPADDSUB_DMP_SHT1_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_18_ ( .D(n1216), .CK(n5449), .RN(
n5287), .Q(FPADDSUB_DMP_SHT1_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_15_ ( .D(n1212), .CK(n5442), .RN(
n5287), .Q(FPADDSUB_DMP_SHT1_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_22_ ( .D(n1208), .CK(n2665), .RN(
n5288), .Q(FPADDSUB_DMP_SHT1_EWSW[22]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n1314), .CK(n5449), .RN(
n5292), .Q(FPADDSUB_LZD_output_NRM2_EW[0]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1412), .CK(n5413), .RN(
n5269), .Q(underflow_flag_addsubt) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1411), .CK(n2660), .RN(
n5292), .Q(overflow_flag_addsubt) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n1409), .CK(n5405), .RN(
n5292), .Q(FPADDSUB_LZD_output_NRM2_EW[1]) );
DFFRXLTS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_2_ ( .D(n1531),
.CK(n5368), .RN(n5306), .Q(FPMULT_P_Sgf[2]) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n1657), .CK(
n5388), .RN(n5353), .Q(FPMULT_Op_MX[31]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1357), .CK(n2333),
.RN(n5291), .Q(FPADDSUB_SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_21_ ( .D(n2011), .CK(n2668), .RN(n5327),
.Q(FPSENCOS_d_ff_Zn[21]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_19_ ( .D(n2017), .CK(n5424), .RN(n5305),
.Q(FPSENCOS_d_ff_Zn[19]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_31_ ( .D(n1909), .CK(n5462), .RN(n5297),
.Q(FPSENCOS_d_ff_Zn[31]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_23_ ( .D(n1786), .CK(n5416), .RN(n5335),
.Q(FPSENCOS_d_ff_Zn[23]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_24_ ( .D(n1783), .CK(n5416), .RN(n5334),
.Q(FPSENCOS_d_ff_Zn[24]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_25_ ( .D(n1780), .CK(n5417), .RN(n5334),
.Q(FPSENCOS_d_ff_Zn[25]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_26_ ( .D(n1777), .CK(n5418), .RN(n5333),
.Q(FPSENCOS_d_ff_Zn[26]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_27_ ( .D(n1774), .CK(n2663), .RN(n5332),
.Q(FPSENCOS_d_ff_Zn[27]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_28_ ( .D(n1771), .CK(n5419), .RN(n2404),
.Q(FPSENCOS_d_ff_Zn[28]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_29_ ( .D(n1768), .CK(n5425), .RN(n5340),
.Q(FPSENCOS_d_ff_Zn[29]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_30_ ( .D(n1765), .CK(n5414), .RN(n5330),
.Q(FPSENCOS_d_ff_Zn[30]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_22_ ( .D(n2008), .CK(n5420), .RN(n5329),
.Q(FPSENCOS_d_ff_Zn[22]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_15_ ( .D(n2029), .CK(n5457), .RN(n5339),
.Q(FPSENCOS_d_ff_Zn[15]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_18_ ( .D(n2020), .CK(n5457), .RN(n5328),
.Q(FPSENCOS_d_ff_Zn[18]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_20_ ( .D(n2014), .CK(n5449), .RN(n5305),
.Q(FPSENCOS_d_ff_Zn[20]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_17_ ( .D(n2023), .CK(n5451), .RN(n5304),
.Q(FPSENCOS_d_ff_Zn[17]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_4_ ( .D(n2062), .CK(n5452), .RN(n5303), .Q(
FPSENCOS_d_ff_Zn[4]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_6_ ( .D(n2056), .CK(n5437), .RN(n2406), .Q(
FPSENCOS_d_ff_Zn[6]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_13_ ( .D(n2035), .CK(n5435), .RN(n5301),
.Q(FPSENCOS_d_ff_Zn[13]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_16_ ( .D(n2026), .CK(n2656), .RN(n5301),
.Q(FPSENCOS_d_ff_Zn[16]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_8_ ( .D(n2050), .CK(n5361), .RN(n5311), .Q(
FPSENCOS_d_ff_Zn[8]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_11_ ( .D(n2041), .CK(n5457), .RN(n5300),
.Q(FPSENCOS_d_ff_Zn[11]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_14_ ( .D(n2032), .CK(n5364), .RN(n5299),
.Q(FPSENCOS_d_ff_Zn[14]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_10_ ( .D(n2044), .CK(n5441), .RN(n5298),
.Q(FPSENCOS_d_ff_Zn[10]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_12_ ( .D(n2038), .CK(n5462), .RN(n5297),
.Q(FPSENCOS_d_ff_Zn[12]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_3_ ( .D(n2065), .CK(n2376), .RN(n5296), .Q(
FPSENCOS_d_ff_Zn[3]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_2_ ( .D(n2068), .CK(n5456), .RN(n5295), .Q(
FPSENCOS_d_ff_Zn[2]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_7_ ( .D(n2053), .CK(n2373), .RN(n5317), .Q(
FPSENCOS_d_ff_Zn[7]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_1_ ( .D(n2071), .CK(n5383), .RN(n5315), .Q(
FPSENCOS_d_ff_Zn[1]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_9_ ( .D(n2047), .CK(n5441), .RN(n5314), .Q(
FPSENCOS_d_ff_Zn[9]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_5_ ( .D(n2059), .CK(n5402), .RN(n5331), .Q(
FPSENCOS_d_ff_Zn[5]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_0_ ( .D(n2074), .CK(n5444), .RN(n5331), .Q(
FPSENCOS_d_ff_Zn[0]) );
DFFRXLTS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_10_ ( .D(n1539),
.CK(n5390), .RN(n5322), .Q(FPMULT_P_Sgf[10]) );
DFFRXLTS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_7_ ( .D(n1536),
.CK(n5390), .RN(n5306), .Q(FPMULT_P_Sgf[7]) );
DFFRXLTS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_0_ ( .D(n1529),
.CK(n5392), .RN(n5306), .Q(FPMULT_P_Sgf[0]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n1330), .CK(n5408),
.RN(n5292), .Q(FPADDSUB_LZD_output_NRM2_EW[4]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n1322), .CK(n5411),
.RN(n5292), .Q(FPADDSUB_LZD_output_NRM2_EW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n1318), .CK(n5454),
.RN(n5292), .Q(FPADDSUB_LZD_output_NRM2_EW[2]) );
DFFRXLTS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_9_ ( .D(n1538),
.CK(n5390), .RN(n5306), .Q(FPMULT_P_Sgf[9]) );
DFFRXLTS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_6_ ( .D(n1535),
.CK(n5390), .RN(n5306), .Q(FPMULT_P_Sgf[6]) );
DFFRXLTS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_5_ ( .D(n1534),
.CK(n5402), .RN(n5306), .Q(FPMULT_P_Sgf[5]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_1_ ( .D(n2111), .CK(n5433), .RN(n5338), .Q(
FPSENCOS_d_ff1_Z[1]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_2_ ( .D(n2110), .CK(n5433), .RN(n5338), .Q(
FPSENCOS_d_ff1_Z[2]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_3_ ( .D(n2109), .CK(n5431), .RN(n5338), .Q(
FPSENCOS_d_ff1_Z[3]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_4_ ( .D(n2108), .CK(n2373), .RN(n5338), .Q(
FPSENCOS_d_ff1_Z[4]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_5_ ( .D(n2107), .CK(n5446), .RN(n5338), .Q(
FPSENCOS_d_ff1_Z[5]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_6_ ( .D(n2106), .CK(n5434), .RN(n5338), .Q(
FPSENCOS_d_ff1_Z[6]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_7_ ( .D(n2105), .CK(n5438), .RN(n5338), .Q(
FPSENCOS_d_ff1_Z[7]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_8_ ( .D(n2104), .CK(n5433), .RN(n5337), .Q(
FPSENCOS_d_ff1_Z[8]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_9_ ( .D(n2103), .CK(n5431), .RN(n5337), .Q(
FPSENCOS_d_ff1_Z[9]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_10_ ( .D(n2102), .CK(n5446), .RN(n5337), .Q(
FPSENCOS_d_ff1_Z[10]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_12_ ( .D(n2100), .CK(n2254), .RN(n5337), .Q(
FPSENCOS_d_ff1_Z[12]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_13_ ( .D(n2099), .CK(n2255), .RN(n5337), .Q(
FPSENCOS_d_ff1_Z[13]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_14_ ( .D(n2098), .CK(n2254), .RN(n5337), .Q(
FPSENCOS_d_ff1_Z[14]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_15_ ( .D(n2097), .CK(n2255), .RN(n5337), .Q(
FPSENCOS_d_ff1_Z[15]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_16_ ( .D(n2096), .CK(n2254), .RN(n5337), .Q(
FPSENCOS_d_ff1_Z[16]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_17_ ( .D(n2095), .CK(n2255), .RN(n5337), .Q(
FPSENCOS_d_ff1_Z[17]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_18_ ( .D(n2094), .CK(n2254), .RN(n5336), .Q(
FPSENCOS_d_ff1_Z[18]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_19_ ( .D(n2093), .CK(n2253), .RN(n5336), .Q(
FPSENCOS_d_ff1_Z[19]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_20_ ( .D(n2092), .CK(n2253), .RN(n5336), .Q(
FPSENCOS_d_ff1_Z[20]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_21_ ( .D(n2091), .CK(n2253), .RN(n5336), .Q(
FPSENCOS_d_ff1_Z[21]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_22_ ( .D(n2090), .CK(n5415), .RN(n5336), .Q(
FPSENCOS_d_ff1_Z[22]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_23_ ( .D(n2089), .CK(n5415), .RN(n5336), .Q(
FPSENCOS_d_ff1_Z[23]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_24_ ( .D(n2088), .CK(n5415), .RN(n5336), .Q(
FPSENCOS_d_ff1_Z[24]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_25_ ( .D(n2087), .CK(n5415), .RN(n5336), .Q(
FPSENCOS_d_ff1_Z[25]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_26_ ( .D(n2086), .CK(n5415), .RN(n5336), .Q(
FPSENCOS_d_ff1_Z[26]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_27_ ( .D(n2085), .CK(n5415), .RN(n5336), .Q(
FPSENCOS_d_ff1_Z[27]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_28_ ( .D(n2084), .CK(n5415), .RN(n5335), .Q(
FPSENCOS_d_ff1_Z[28]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_29_ ( .D(n2083), .CK(n5415), .RN(n5335), .Q(
FPSENCOS_d_ff1_Z[29]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_30_ ( .D(n2082), .CK(n5415), .RN(n5335), .Q(
FPSENCOS_d_ff1_Z[30]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_31_ ( .D(n2081), .CK(n2253), .RN(n5335), .Q(
FPSENCOS_d_ff1_Z[31]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_0_ ( .D(n2112), .CK(n5431), .RN(n2406), .Q(
FPSENCOS_d_ff1_Z[0]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_3_ ( .D(n2130), .CK(n5450), .RN(n5321), .Q(
FPSENCOS_d_ff3_LUT_out[3]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_13_ ( .D(n2121), .CK(n2373), .RN(n5320), .Q(
FPSENCOS_d_ff3_LUT_out[13]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_19_ ( .D(n2119), .CK(n5434), .RN(n5320), .Q(
FPSENCOS_d_ff3_LUT_out[19]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_27_ ( .D(n2113), .CK(n5432), .RN(n5310), .Q(
FPSENCOS_d_ff3_LUT_out[27]) );
DFFRXLTS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_19_ ( .D(n1548),
.CK(n5382), .RN(n2404), .Q(FPMULT_P_Sgf[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n1406), .CK(n5404),
.RN(n5270), .Q(FPADDSUB_DmP_mant_SHT1_SW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n1397), .CK(n5406),
.RN(n5271), .Q(FPADDSUB_DmP_mant_SHT1_SW[21]) );
DFFRXLTS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_23_ ( .D(n1552),
.CK(n5386), .RN(n5308), .Q(FPMULT_P_Sgf[23]) );
DFFRXLTS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_22_ ( .D(n1551),
.CK(n5387), .RN(n5308), .Q(FPMULT_P_Sgf[22]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n1454), .CK(n2662), .RN(
n5293), .Q(FPADDSUB_DMP_exp_NRM_EW[0]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n1449), .CK(n5455), .RN(
n5293), .Q(FPADDSUB_DMP_exp_NRM_EW[1]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n1444), .CK(n5388), .RN(
n5293), .Q(FPADDSUB_DMP_exp_NRM_EW[2]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n1439), .CK(n5380), .RN(
n5293), .Q(FPADDSUB_DMP_exp_NRM_EW[3]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n1434), .CK(n2659), .RN(
n5293), .Q(FPADDSUB_DMP_exp_NRM_EW[4]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n1429), .CK(n5464), .RN(
n5294), .Q(FPADDSUB_DMP_exp_NRM_EW[5]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n1424), .CK(n5443), .RN(
n5294), .Q(FPADDSUB_DMP_exp_NRM_EW[6]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n1419), .CK(n5406), .RN(
n5294), .Q(FPADDSUB_DMP_exp_NRM_EW[7]) );
DFFRXLTS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_20_ ( .D(n1549),
.CK(n5384), .RN(n5308), .Q(FPMULT_P_Sgf[20]) );
DFFRXLTS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_13_ ( .D(n1542),
.CK(n5376), .RN(n5316), .Q(FPMULT_P_Sgf[13]) );
DFFRXLTS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_11_ ( .D(n1540),
.CK(n5390), .RN(n5307), .Q(FPMULT_P_Sgf[11]) );
DFFRXLTS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_4_ ( .D(n1533),
.CK(n5368), .RN(n5306), .Q(FPMULT_P_Sgf[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n1355), .CK(n2668), .RN(
n5275), .Q(FPADDSUB_OP_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n1364), .CK(n2665),
.RN(n5274), .Q(FPADDSUB_DmP_mant_SHT1_SW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n1478), .CK(n5363),
.RN(n5265), .Q(FPADDSUB_Shift_amount_SHT1_EWR[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n1477), .CK(n2336),
.RN(n5265), .Q(FPADDSUB_Shift_amount_SHT1_EWR[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n1474), .CK(n2336),
.RN(n5265), .Q(FPADDSUB_Shift_amount_SHT1_EWR[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n1400), .CK(n5413),
.RN(n5270), .Q(FPADDSUB_DmP_mant_SHT1_SW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n1385), .CK(n5409), .RN(
n5272), .Q(FPADDSUB_DmP_mant_SHT1_SW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n1373), .CK(n5407), .RN(
n5273), .Q(FPADDSUB_DmP_mant_SHT1_SW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n1367), .CK(n5366),
.RN(n5274), .Q(FPADDSUB_DmP_mant_SHT1_SW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n1290), .CK(n5391), .RN(
n5280), .Q(FPADDSUB_DmP_mant_SHT1_SW[1]) );
DFFRXLTS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_8_ ( .D(n1537),
.CK(n5390), .RN(n5306), .Q(FPMULT_P_Sgf[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n1475), .CK(n2336),
.RN(n5265), .Q(FPADDSUB_Shift_amount_SHT1_EWR[0]) );
DFFRXLTS reg_dataB_Q_reg_23_ ( .D(Data_2[23]), .CK(n5426), .RN(n5339), .Q(
dataB[23]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n1624), .CK(
n5438), .RN(n5349), .Q(FPMULT_Op_MY[31]) );
DFFRXLTS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_31_ ( .D(n1560),
.CK(n5384), .RN(n5309), .Q(FPMULT_P_Sgf[31]) );
DFFRXLTS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_28_ ( .D(n1557),
.CK(n5379), .RN(n5308), .Q(FPMULT_P_Sgf[28]) );
DFFRXLTS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_24_ ( .D(n1553),
.CK(n5382), .RN(n5308), .Q(FPMULT_P_Sgf[24]) );
DFFRXLTS reg_dataB_Q_reg_27_ ( .D(Data_2[27]), .CK(n2334), .RN(n5311), .Q(
dataB[27]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(
n1576), .CK(n5455), .RN(n5344), .Q(mult_result[31]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_5_ ( .D(n2128), .CK(n5444), .RN(n5321), .Q(
FPSENCOS_d_ff3_LUT_out[5]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_15_ ( .D(n2120), .CK(n5438), .RN(n5320), .Q(
FPSENCOS_d_ff3_LUT_out[15]) );
DFFRXLTS reg_dataB_Q_reg_29_ ( .D(Data_2[29]), .CK(n5429), .RN(n5323), .Q(
dataB[29]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_18_ ( .D(n1968), .CK(n5448), .RN(n5327),
.Q(FPSENCOS_d_ff3_sh_x_out[18]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_21_ ( .D(n1962), .CK(n5362), .RN(n5305),
.Q(FPSENCOS_d_ff3_sh_x_out[21]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_23_ ( .D(n1951), .CK(n5446), .RN(n5313),
.Q(FPSENCOS_d_ff3_sh_x_out[23]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_24_ ( .D(n1950), .CK(n2373), .RN(n5331),
.Q(FPSENCOS_d_ff3_sh_x_out[24]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_25_ ( .D(n1949), .CK(n5434), .RN(n5319),
.Q(FPSENCOS_d_ff3_sh_x_out[25]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_26_ ( .D(n1948), .CK(n5438), .RN(n5318),
.Q(FPSENCOS_d_ff3_sh_x_out[26]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_28_ ( .D(n1946), .CK(n5433), .RN(n5322),
.Q(FPSENCOS_d_ff3_sh_x_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_30_ ( .D(n1944), .CK(n2373), .RN(n5317),
.Q(FPSENCOS_d_ff3_sh_x_out[30]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_22_ ( .D(n1960), .CK(n5457), .RN(n5329),
.Q(FPSENCOS_d_ff3_sh_x_out[22]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_15_ ( .D(n1974), .CK(n5457), .RN(n5302),
.Q(FPSENCOS_d_ff3_sh_x_out[15]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_19_ ( .D(n1966), .CK(n5449), .RN(n5305),
.Q(FPSENCOS_d_ff3_sh_x_out[19]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_20_ ( .D(n1964), .CK(n5428), .RN(n5304),
.Q(FPSENCOS_d_ff3_sh_x_out[20]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_17_ ( .D(n1970), .CK(n5368), .RN(n5303),
.Q(FPSENCOS_d_ff3_sh_x_out[17]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_4_ ( .D(n1996), .CK(n5452), .RN(n5323),
.Q(FPSENCOS_d_ff3_sh_x_out[4]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_6_ ( .D(n1992), .CK(n5436), .RN(n5301),
.Q(FPSENCOS_d_ff3_sh_x_out[6]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_13_ ( .D(n1978), .CK(n5453), .RN(n5301),
.Q(FPSENCOS_d_ff3_sh_x_out[13]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_16_ ( .D(n1972), .CK(n5456), .RN(n5339),
.Q(FPSENCOS_d_ff3_sh_x_out[16]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_8_ ( .D(n1988), .CK(n5457), .RN(n5300),
.Q(FPSENCOS_d_ff3_sh_x_out[8]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_11_ ( .D(n1982), .CK(n5442), .RN(n5299),
.Q(FPSENCOS_d_ff3_sh_x_out[11]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_14_ ( .D(n1976), .CK(n5391), .RN(n5298),
.Q(FPSENCOS_d_ff3_sh_x_out[14]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_10_ ( .D(n1984), .CK(n5460), .RN(n5298),
.Q(FPSENCOS_d_ff3_sh_x_out[10]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_12_ ( .D(n1980), .CK(n5462), .RN(n5297),
.Q(FPSENCOS_d_ff3_sh_x_out[12]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_31_ ( .D(n1942), .CK(n2376), .RN(n5296),
.Q(FPSENCOS_d_ff3_sh_x_out[31]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_3_ ( .D(n1998), .CK(n5436), .RN(n5295),
.Q(FPSENCOS_d_ff3_sh_x_out[3]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_2_ ( .D(n2000), .CK(n5369), .RN(n5317),
.Q(FPSENCOS_d_ff3_sh_x_out[2]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_7_ ( .D(n1990), .CK(n5434), .RN(n5319),
.Q(FPSENCOS_d_ff3_sh_x_out[7]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_0_ ( .D(n2004), .CK(n5440), .RN(n5315),
.Q(FPSENCOS_d_ff3_sh_x_out[0]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_1_ ( .D(n2002), .CK(n5441), .RN(n5314),
.Q(FPSENCOS_d_ff3_sh_x_out[1]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_9_ ( .D(n1986), .CK(n5442), .RN(n5319),
.Q(FPSENCOS_d_ff3_sh_x_out[9]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_5_ ( .D(n1994), .CK(n5363), .RN(n5312),
.Q(FPSENCOS_d_ff3_sh_x_out[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n1403), .CK(n5406),
.RN(n5270), .Q(FPADDSUB_DmP_mant_SHT1_SW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n1376), .CK(n5407),
.RN(n5273), .Q(FPADDSUB_DmP_mant_SHT1_SW[16]) );
DFFRX1TS reg_dataA_Q_reg_25_ ( .D(Data_1[25]), .CK(n5425), .RN(n5325), .Q(
dataA[25]) );
DFFRX1TS reg_dataA_Q_reg_28_ ( .D(Data_1[28]), .CK(n5455), .RN(n5324), .Q(
dataA[28]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_19_ ( .D(n1395), .CK(n5409), .RN(n5271), .Q(FPADDSUB_DmP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_20_ ( .D(n1392), .CK(n5403), .RN(n5271), .Q(FPADDSUB_DmP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_17_ ( .D(n1389), .CK(n5403), .RN(n5271), .Q(FPADDSUB_DmP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_13_ ( .D(n1380), .CK(n5405), .RN(n5272), .Q(FPADDSUB_DmP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n1327), .CK(n5411), .RN(
n5276), .Q(FPADDSUB_DmP_mant_SHT1_SW[3]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_2_ ( .D(n1312), .CK(n5365), .RN(n5277),
.Q(FPADDSUB_DmP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n1297), .CK(n5390), .RN(
n5279), .Q(FPADDSUB_DmP_mant_SHT1_SW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_1_ ( .D(n1291), .CK(n5391), .RN(n5280),
.Q(FPADDSUB_DmP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_9_ ( .D(n1284), .CK(n5373), .RN(n5280),
.Q(FPADDSUB_DmP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_12_ ( .D(n1271), .CK(n5386), .RN(n5282), .Q(FPADDSUB_DmP_EXP_EWSW[12]) );
DFFRX1TS reg_dataA_Q_reg_23_ ( .D(Data_1[23]), .CK(n2334), .RN(n5325), .Q(
dataA[23]) );
DFFRX1TS reg_dataA_Q_reg_27_ ( .D(Data_1[27]), .CK(n2333), .RN(n5324), .Q(
dataA[27]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(
n1504), .CK(n2665), .RN(n5343), .Q(mult_result[0]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(
n1503), .CK(n5458), .RN(n5343), .Q(mult_result[1]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(
n1502), .CK(n2665), .RN(n5343), .Q(mult_result[2]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(
n1501), .CK(n5458), .RN(n5343), .Q(mult_result[3]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(
n1500), .CK(n5458), .RN(n5342), .Q(mult_result[4]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(
n1499), .CK(n2666), .RN(n5342), .Q(mult_result[5]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(
n1498), .CK(n5448), .RN(n5342), .Q(mult_result[6]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(
n1497), .CK(n5362), .RN(n5342), .Q(mult_result[7]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(
n1496), .CK(n2666), .RN(n5342), .Q(mult_result[8]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(
n1495), .CK(n5448), .RN(n5342), .Q(mult_result[9]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(
n1494), .CK(n5362), .RN(n5342), .Q(mult_result[10]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(
n1493), .CK(n5464), .RN(n5342), .Q(mult_result[11]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(
n1492), .CK(n5464), .RN(n5342), .Q(mult_result[12]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(
n1491), .CK(n5464), .RN(n5342), .Q(mult_result[13]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(
n1490), .CK(n5464), .RN(n5341), .Q(mult_result[14]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(
n1489), .CK(n5375), .RN(n5341), .Q(mult_result[15]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(
n1488), .CK(n5402), .RN(n5341), .Q(mult_result[16]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(
n1487), .CK(n5363), .RN(n5341), .Q(mult_result[17]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(
n1485), .CK(n5375), .RN(n5341), .Q(mult_result[19]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(
n1484), .CK(n5402), .RN(n5341), .Q(mult_result[20]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(
n1483), .CK(n5363), .RN(n5341), .Q(mult_result[21]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(
n1481), .CK(n5375), .RN(n5341), .Q(mult_result[22]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(
n1486), .CK(n5392), .RN(n5341), .Q(mult_result[18]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_27_ ( .D(n1947), .CK(n5434), .RN(n2404),
.Q(FPSENCOS_d_ff3_sh_x_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_29_ ( .D(n1945), .CK(n5438), .RN(n5310),
.Q(FPSENCOS_d_ff3_sh_x_out[29]) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n1620), .CK(n5387),
.RN(n5351), .Q(FPMULT_Add_result[0]) );
DFFRXLTS FPMULT_Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n1596), .CK(n2654),
.RN(n5351), .Q(FPMULT_FSM_add_overflow_flag) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_28_ ( .D(n1460), .CK(n2662), .RN(n5266), .Q(FPADDSUB_DMP_EXP_EWSW[28]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_29_ ( .D(n1459), .CK(n5377), .RN(n5266), .Q(FPADDSUB_DMP_EXP_EWSW[29]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_30_ ( .D(n1458), .CK(n5369), .RN(n5266), .Q(FPADDSUB_DMP_EXP_EWSW[30]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_22_ ( .D(n1407), .CK(n5409), .RN(n5270), .Q(FPADDSUB_DmP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_15_ ( .D(n1404), .CK(n5403), .RN(n5270), .Q(FPADDSUB_DmP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_18_ ( .D(n1401), .CK(n5405), .RN(n5270), .Q(FPADDSUB_DmP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_21_ ( .D(n1398), .CK(n5405), .RN(n5270), .Q(FPADDSUB_DmP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_4_ ( .D(n1386), .CK(n5413), .RN(n5272),
.Q(FPADDSUB_DmP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_6_ ( .D(n1383), .CK(n5406), .RN(n5272),
.Q(FPADDSUB_DmP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_16_ ( .D(n1377), .CK(n5407), .RN(n5273), .Q(FPADDSUB_DmP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_8_ ( .D(n1374), .CK(n5407), .RN(n5273),
.Q(FPADDSUB_DmP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_11_ ( .D(n1371), .CK(n5407), .RN(n5273), .Q(FPADDSUB_DmP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_14_ ( .D(n1368), .CK(n5458), .RN(n5273), .Q(FPADDSUB_DmP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_10_ ( .D(n1365), .CK(n5366), .RN(n5274), .Q(FPADDSUB_DmP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_3_ ( .D(n1328), .CK(n5411), .RN(n5276),
.Q(FPADDSUB_DmP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_3_ ( .D(n1326), .CK(n5411), .RN(n5276),
.Q(FPADDSUB_DMP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_2_ ( .D(n1310), .CK(n5399), .RN(n5278),
.Q(FPADDSUB_DMP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_7_ ( .D(n1305), .CK(n5406), .RN(n5278),
.Q(FPADDSUB_DmP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_7_ ( .D(n1303), .CK(n5409), .RN(n5278),
.Q(FPADDSUB_DMP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_0_ ( .D(n1298), .CK(n5390), .RN(n5279),
.Q(FPADDSUB_DmP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_0_ ( .D(n1296), .CK(n5391), .RN(n5279),
.Q(FPADDSUB_DMP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_1_ ( .D(n1289), .CK(n5391), .RN(n5280),
.Q(FPADDSUB_DMP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_9_ ( .D(n1282), .CK(n5372), .RN(n5280),
.Q(FPADDSUB_DMP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_5_ ( .D(n1277), .CK(n5392), .RN(n5281),
.Q(FPADDSUB_DmP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_5_ ( .D(n1275), .CK(n5393), .RN(n5281),
.Q(FPADDSUB_DMP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_12_ ( .D(n1269), .CK(n5389), .RN(n5282), .Q(FPADDSUB_DMP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_10_ ( .D(n1265), .CK(n5394), .RN(n5282), .Q(FPADDSUB_DMP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_14_ ( .D(n1261), .CK(n5394), .RN(n5283), .Q(FPADDSUB_DMP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_11_ ( .D(n1257), .CK(n5394), .RN(n5283), .Q(FPADDSUB_DMP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_8_ ( .D(n1253), .CK(n5395), .RN(n5283),
.Q(FPADDSUB_DMP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_16_ ( .D(n1249), .CK(n5395), .RN(n5284), .Q(FPADDSUB_DMP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_13_ ( .D(n1245), .CK(n5396), .RN(n5284), .Q(FPADDSUB_DMP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_6_ ( .D(n1241), .CK(n5396), .RN(n5285),
.Q(FPADDSUB_DMP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_4_ ( .D(n1237), .CK(n5397), .RN(n5285),
.Q(FPADDSUB_DMP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_17_ ( .D(n1233), .CK(n5397), .RN(n5285), .Q(FPADDSUB_DMP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_20_ ( .D(n1229), .CK(n5397), .RN(n5286), .Q(FPADDSUB_DMP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_19_ ( .D(n1225), .CK(n5398), .RN(n5286), .Q(FPADDSUB_DMP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_21_ ( .D(n1221), .CK(n5398), .RN(n5287), .Q(FPADDSUB_DMP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_18_ ( .D(n1217), .CK(n5366), .RN(n5287), .Q(FPADDSUB_DMP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_15_ ( .D(n1213), .CK(n5408), .RN(n5287), .Q(FPADDSUB_DMP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_22_ ( .D(n1209), .CK(n2656), .RN(n5288), .Q(FPADDSUB_DMP_EXP_EWSW[22]) );
DFFRXLTS reg_dataB_Q_reg_25_ ( .D(Data_2[25]), .CK(n5455), .RN(n5339), .Q(
dataB[25]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_8_ ( .D(n2125), .CK(n5428), .RN(n5320), .Q(
FPSENCOS_d_ff3_LUT_out[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n1382), .CK(n5406), .RN(
n5272), .Q(FPADDSUB_DmP_mant_SHT1_SW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n1370), .CK(n5407),
.RN(n5273), .Q(FPADDSUB_DmP_mant_SHT1_SW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n1304), .CK(n5403), .RN(
n5278), .Q(FPADDSUB_DmP_mant_SHT1_SW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n1276), .CK(n5381), .RN(
n5281), .Q(FPADDSUB_DmP_mant_SHT1_SW[5]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_18_ ( .D(n1870), .CK(n2666), .RN(n5327),
.Q(FPSENCOS_d_ff3_sh_y_out[18]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_31_ ( .D(n1844), .CK(n5462), .RN(n5296),
.Q(FPSENCOS_d_ff3_sh_y_out[31]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_23_ ( .D(n2117), .CK(n5433), .RN(n5316), .Q(
FPSENCOS_d_ff3_LUT_out[23]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_25_ ( .D(n2115), .CK(n2373), .RN(n5307), .Q(
FPSENCOS_d_ff3_LUT_out[25]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_28_ ( .D(n1848), .CK(n5432), .RN(n5316),
.Q(FPSENCOS_d_ff3_sh_y_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_30_ ( .D(n1846), .CK(n5432), .RN(n5307),
.Q(FPSENCOS_d_ff3_sh_y_out[30]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_22_ ( .D(n1862), .CK(n5422), .RN(n5329),
.Q(FPSENCOS_d_ff3_sh_y_out[22]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_15_ ( .D(n1876), .CK(n5457), .RN(n5311),
.Q(FPSENCOS_d_ff3_sh_y_out[15]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_19_ ( .D(n1868), .CK(n5449), .RN(n5305),
.Q(FPSENCOS_d_ff3_sh_y_out[19]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_20_ ( .D(n1866), .CK(n5430), .RN(n5304),
.Q(FPSENCOS_d_ff3_sh_y_out[20]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_17_ ( .D(n1872), .CK(n2659), .RN(n5303),
.Q(FPSENCOS_d_ff3_sh_y_out[17]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_13_ ( .D(n1880), .CK(n2656), .RN(n5301),
.Q(FPSENCOS_d_ff3_sh_y_out[13]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_16_ ( .D(n1874), .CK(n5383), .RN(n2406),
.Q(FPSENCOS_d_ff3_sh_y_out[16]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_11_ ( .D(n1884), .CK(n5372), .RN(n5299),
.Q(FPSENCOS_d_ff3_sh_y_out[11]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_14_ ( .D(n1878), .CK(n5391), .RN(n5299),
.Q(FPSENCOS_d_ff3_sh_y_out[14]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_3_ ( .D(n1900), .CK(n5435), .RN(n5295),
.Q(FPSENCOS_d_ff3_sh_y_out[3]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_7_ ( .D(n1892), .CK(n5438), .RN(n5318),
.Q(FPSENCOS_d_ff3_sh_y_out[7]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_5_ ( .D(n1896), .CK(n5373), .RN(n5318),
.Q(FPSENCOS_d_ff3_sh_y_out[5]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n1790), .CK(n5449), .RN(
n5259), .Q(FPADDSUB_Data_array_SWR[3]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(
n1584), .CK(n5463), .RN(n5344), .Q(mult_result[23]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(
n1583), .CK(n5440), .RN(n5344), .Q(mult_result[24]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(
n1582), .CK(n5463), .RN(n5343), .Q(mult_result[25]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(
n1581), .CK(n5378), .RN(n5343), .Q(mult_result[26]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(
n1580), .CK(n5365), .RN(n5343), .Q(mult_result[27]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(
n1579), .CK(n5378), .RN(n5343), .Q(mult_result[28]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(
n1578), .CK(n5365), .RN(n5343), .Q(mult_result[29]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(
n1577), .CK(n5378), .RN(n5343), .Q(mult_result[30]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n1789), .CK(n5448), .RN(
n5258), .Q(FPADDSUB_Data_array_SWR[2]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_27_ ( .D(n1849), .CK(n5432), .RN(n5313),
.Q(FPSENCOS_d_ff3_sh_y_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_29_ ( .D(n1847), .CK(n5432), .RN(n5313),
.Q(FPSENCOS_d_ff3_sh_y_out[29]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_1_ ( .D(n2132), .CK(n5427), .RN(n5321), .Q(
FPSENCOS_d_ff3_LUT_out[1]) );
DFFRX1TS reg_dataA_Q_reg_29_ ( .D(Data_1[29]), .CK(n5426), .RN(n5324), .Q(
dataA[29]) );
DFFRX1TS reg_dataA_Q_reg_30_ ( .D(Data_1[30]), .CK(n5463), .RN(n5324), .Q(
dataA[30]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_31_ ( .D(n1695), .CK(n5430), .RN(
n5312), .Q(cordic_result[31]) );
DFFRX1TS reg_dataB_Q_reg_30_ ( .D(Data_2[30]), .CK(n5427), .RN(n5302), .Q(
dataB[30]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_32_ ( .D(n1561),
.CK(n5376), .RN(n5309), .Q(FPMULT_P_Sgf[32]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_35_ ( .D(n1564),
.CK(n5388), .RN(n5309), .Q(FPMULT_P_Sgf[35]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_21_ ( .D(n1743), .CK(n2666),
.RN(n5327), .Q(FPSENCOS_d_ff2_Z[21]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_23_ ( .D(n1741), .CK(n5416),
.RN(n5335), .Q(FPSENCOS_d_ff2_Z[23]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_24_ ( .D(n1740), .CK(n2374),
.RN(n5334), .Q(FPSENCOS_d_ff2_Z[24]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_25_ ( .D(n1739), .CK(n2374),
.RN(n5333), .Q(FPSENCOS_d_ff2_Z[25]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_26_ ( .D(n1738), .CK(n5418),
.RN(n5333), .Q(FPSENCOS_d_ff2_Z[26]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_27_ ( .D(n1737), .CK(n5465),
.RN(n5332), .Q(FPSENCOS_d_ff2_Z[27]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_28_ ( .D(n1736), .CK(n5419),
.RN(n5310), .Q(FPSENCOS_d_ff2_Z[28]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_29_ ( .D(n1735), .CK(n5414),
.RN(n5313), .Q(FPSENCOS_d_ff2_Z[29]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_30_ ( .D(n1734), .CK(n5414),
.RN(n5330), .Q(FPSENCOS_d_ff2_Z[30]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_22_ ( .D(n1742), .CK(n5421),
.RN(n5329), .Q(FPSENCOS_d_ff2_Z[22]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_15_ ( .D(n1749), .CK(n5422),
.RN(n2408), .Q(FPSENCOS_d_ff2_Z[15]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_18_ ( .D(n1746), .CK(n5422),
.RN(n2408), .Q(FPSENCOS_d_ff2_Z[18]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_19_ ( .D(n1745), .CK(n2662),
.RN(n5305), .Q(FPSENCOS_d_ff2_Z[19]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_20_ ( .D(n1744), .CK(n5450),
.RN(n5304), .Q(FPSENCOS_d_ff2_Z[20]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_17_ ( .D(n1747), .CK(n5368),
.RN(n5304), .Q(FPSENCOS_d_ff2_Z[17]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_4_ ( .D(n1760), .CK(n5452), .RN(
n5303), .Q(FPSENCOS_d_ff2_Z[4]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_6_ ( .D(n1758), .CK(n2662), .RN(
n2406), .Q(FPSENCOS_d_ff2_Z[6]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_13_ ( .D(n1751), .CK(n5448),
.RN(n5301), .Q(FPSENCOS_d_ff2_Z[13]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_16_ ( .D(n1748), .CK(n5372),
.RN(n5326), .Q(FPSENCOS_d_ff2_Z[16]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_8_ ( .D(n1756), .CK(n5456), .RN(
n5339), .Q(FPSENCOS_d_ff2_Z[8]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_11_ ( .D(n1753), .CK(n5422),
.RN(n5300), .Q(FPSENCOS_d_ff2_Z[11]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_14_ ( .D(n1750), .CK(n5372),
.RN(n5299), .Q(FPSENCOS_d_ff2_Z[14]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_10_ ( .D(n1754), .CK(n5460),
.RN(n5298), .Q(FPSENCOS_d_ff2_Z[10]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_12_ ( .D(n1752), .CK(n5461),
.RN(n5297), .Q(FPSENCOS_d_ff2_Z[12]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_3_ ( .D(n1761), .CK(n2376), .RN(
n5296), .Q(FPSENCOS_d_ff2_Z[3]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_2_ ( .D(n1762), .CK(n2666), .RN(
n5295), .Q(FPSENCOS_d_ff2_Z[2]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_7_ ( .D(n1757), .CK(n2373), .RN(
n5317), .Q(FPSENCOS_d_ff2_Z[7]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_1_ ( .D(n1763), .CK(n5455), .RN(
n5315), .Q(FPSENCOS_d_ff2_Z[1]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_9_ ( .D(n1755), .CK(n5454), .RN(
n5314), .Q(FPSENCOS_d_ff2_Z[9]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_5_ ( .D(n1759), .CK(n5363), .RN(
n5307), .Q(FPSENCOS_d_ff2_Z[5]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_36_ ( .D(n1565),
.CK(n5380), .RN(n5309), .Q(FPMULT_P_Sgf[36]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_23_ ( .D(n1703), .CK(n5416), .RN(
n5334), .Q(cordic_result[23]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_24_ ( .D(n1702), .CK(n5417), .RN(
n5334), .Q(cordic_result[24]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_25_ ( .D(n1701), .CK(n5418), .RN(
n5333), .Q(cordic_result[25]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_26_ ( .D(n1700), .CK(n5414), .RN(
n5332), .Q(cordic_result[26]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_27_ ( .D(n1699), .CK(n5419), .RN(
n5319), .Q(cordic_result[27]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_28_ ( .D(n1698), .CK(n5419), .RN(
n5318), .Q(cordic_result[28]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_29_ ( .D(n1697), .CK(n5414), .RN(
n5330), .Q(cordic_result[29]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_30_ ( .D(n1696), .CK(n5420), .RN(
n5329), .Q(cordic_result[30]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_3_ ( .D(n1723), .CK(n5367), .RN(n5295), .Q(cordic_result[3]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_2_ ( .D(n1724), .CK(n5446), .RN(n5317), .Q(cordic_result[2]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_7_ ( .D(n1719), .CK(n5428), .RN(n5313), .Q(cordic_result[7]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_0_ ( .D(n1764), .CK(n5430), .RN(
n5307), .Q(FPSENCOS_d_ff2_Z[0]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_0_ ( .D(n1726), .CK(n5440), .RN(n5315), .Q(cordic_result[0]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_1_ ( .D(n1725), .CK(n5459), .RN(n5314), .Q(cordic_result[1]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_9_ ( .D(n1717), .CK(n5412), .RN(n5331), .Q(cordic_result[9]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_5_ ( .D(n1721), .CK(n5450), .RN(n5312), .Q(cordic_result[5]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_12_ ( .D(n1714), .CK(n5444), .RN(
n5312), .Q(cordic_result[12]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_10_ ( .D(n1716), .CK(n5439), .RN(
n5312), .Q(cordic_result[10]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_14_ ( .D(n1712), .CK(n5450), .RN(
n5312), .Q(cordic_result[14]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_11_ ( .D(n1715), .CK(n5444), .RN(
n5312), .Q(cordic_result[11]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_8_ ( .D(n1718), .CK(n5429), .RN(n5312), .Q(cordic_result[8]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_16_ ( .D(n1710), .CK(n2375), .RN(
n5312), .Q(cordic_result[16]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_13_ ( .D(n1713), .CK(n2375), .RN(
n5312), .Q(cordic_result[13]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_6_ ( .D(n1720), .CK(n2375), .RN(n5328), .Q(cordic_result[6]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_4_ ( .D(n1722), .CK(n2375), .RN(n5302), .Q(cordic_result[4]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_17_ ( .D(n1709), .CK(n2375), .RN(
n5311), .Q(cordic_result[17]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_20_ ( .D(n1706), .CK(n2375), .RN(
n5323), .Q(cordic_result[20]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_19_ ( .D(n1707), .CK(n2375), .RN(
n5302), .Q(cordic_result[19]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_21_ ( .D(n1705), .CK(n2375), .RN(
n5328), .Q(cordic_result[21]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_18_ ( .D(n1708), .CK(n2375), .RN(
n5311), .Q(cordic_result[18]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_15_ ( .D(n1711), .CK(n5434), .RN(
n5323), .Q(cordic_result[15]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_22_ ( .D(n1704), .CK(n5438), .RN(
n5328), .Q(cordic_result[22]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_21_ ( .D(n2118), .CK(n5433), .RN(n5320), .Q(
FPSENCOS_d_ff3_LUT_out[21]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n1787), .CK(n5433), .RN(
n5265), .Q(FPADDSUB_Data_array_SWR[0]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n1731), .CK(n5461), .RN(
n5262), .Q(FPADDSUB_intAS) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n1728), .CK(n2376),
.RN(n5262), .Q(FPADDSUB_intDY_EWSW[31]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n1788), .CK(n5420), .RN(
n5257), .Q(FPADDSUB_Data_array_SWR[1]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_0_ ( .D(n2133), .CK(n5439), .RN(n5321), .Q(
FPSENCOS_d_ff3_LUT_out[0]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_2_ ( .D(n2131), .CK(n5427), .RN(n5321), .Q(
FPSENCOS_d_ff3_LUT_out[2]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_4_ ( .D(n2129), .CK(n5450), .RN(n5321), .Q(
FPSENCOS_d_ff3_LUT_out[4]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_6_ ( .D(n2127), .CK(n5444), .RN(n5320), .Q(
FPSENCOS_d_ff3_LUT_out[6]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_10_ ( .D(n2123), .CK(n5431), .RN(n5320), .Q(
FPSENCOS_d_ff3_LUT_out[10]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_12_ ( .D(n2122), .CK(n5446), .RN(n5320), .Q(
FPSENCOS_d_ff3_LUT_out[12]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_24_ ( .D(n2116), .CK(n2373), .RN(n5310), .Q(
FPSENCOS_d_ff3_LUT_out[24]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n1453), .CK(n5392), .RN(
n5292), .Q(FPADDSUB_DMP_exp_NRM2_EW[0]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n1448), .CK(n5383), .RN(
n5293), .Q(FPADDSUB_DMP_exp_NRM2_EW[1]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n1443), .CK(n2654), .RN(
n5293), .Q(FPADDSUB_DMP_exp_NRM2_EW[2]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n1438), .CK(n5376), .RN(
n5293), .Q(FPADDSUB_DMP_exp_NRM2_EW[3]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n1433), .CK(n5369), .RN(
n5293), .Q(FPADDSUB_DMP_exp_NRM2_EW[4]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n1428), .CK(n5448), .RN(
n5293), .Q(FPADDSUB_DMP_exp_NRM2_EW[5]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n1423), .CK(n5451), .RN(
n5294), .Q(FPADDSUB_DMP_exp_NRM2_EW[6]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n1418), .CK(n5405), .RN(
n5294), .Q(FPADDSUB_DMP_exp_NRM2_EW[7]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_15_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N15), .CK(n5373), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[15]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_21_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N21), .CK(n5375), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[21]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_17_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N17), .CK(n5364), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[17]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_19_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N19), .CK(n5372), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[19]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_12_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N12), .CK(n5464), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[12]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_13_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N13), .CK(n5453), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[13]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_16_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N16), .CK(n5410), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[16]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_17_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N17), .CK(n5367), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[17]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_18_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N18), .CK(n5410), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[18]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_19_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N19), .CK(n5451), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[19]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_20_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N20), .CK(n5368), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[20]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_7_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N7), .CK(n5364), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[7]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_8_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N8), .CK(n5365), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[8]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_9_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N9), .CK(n5412), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[9]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_10_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N10), .CK(n5364), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[10]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_11_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N11), .CK(n5365), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[11]) );
DFFQX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_0_ ( .D(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N0), .CK(n5366), .Q(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[0]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n1653), .CK(
n2654), .RN(n5351), .Q(FPMULT_Op_MY[27]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_23_ ( .D(n1784), .CK(n5416), .RN(n5335),
.Q(FPSENCOS_d_ff_Xn[23]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_30_ ( .D(n1729), .CK(n5422), .RN(n5330),
.Q(FPSENCOS_d_ff_Xn[30]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_22_ ( .D(n2006), .CK(n5423), .RN(n5329),
.Q(FPSENCOS_d_ff_Xn[22]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_15_ ( .D(n2027), .CK(n5423), .RN(n2408),
.Q(FPSENCOS_d_ff_Xn[15]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_18_ ( .D(n2018), .CK(n2333), .RN(n5327),
.Q(FPSENCOS_d_ff_Xn[18]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_21_ ( .D(n2009), .CK(n5424), .RN(n5326),
.Q(FPSENCOS_d_ff_Xn[21]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_4_ ( .D(n2060), .CK(n5452), .RN(n5339), .Q(
FPSENCOS_d_ff_Xn[4]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_8_ ( .D(n2048), .CK(n5423), .RN(n5300), .Q(
FPSENCOS_d_ff_Xn[8]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_11_ ( .D(n2039), .CK(n5458), .RN(n5299),
.Q(FPSENCOS_d_ff_Xn[11]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_0_ ( .D(n2072), .CK(n5439), .RN(n5315), .Q(
FPSENCOS_d_ff_Xn[0]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_9_ ( .D(n2045), .CK(n5361), .RN(n5314), .Q(
FPSENCOS_d_ff_Xn[9]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n1654), .CK(
n5389), .RN(n5351), .Q(FPMULT_Op_MY[28]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n1650), .CK(
n5386), .RN(n5350), .Q(FPMULT_Op_MY[24]) );
DFFRX1TS FPADDSUB_inst_ShiftRegister_Q_reg_3_ ( .D(n2145), .CK(n5430), .RN(
n5255), .Q(FPADDSUB_Shift_reg_FLAGS_7[3]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_39_ ( .D(n1568),
.CK(n5382), .RN(n5309), .Q(FPMULT_P_Sgf[39]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n1652), .CK(
n5379), .RN(n5350), .Q(FPMULT_Op_MY[26]) );
DFFRX1TS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_2_ ( .D(n1351), .CK(n2333), .RN(
n5275), .Q(FPADDSUB_ADD_OVRFLW_NRM) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n1655), .CK(
n5393), .RN(n5351), .Q(FPMULT_Op_MY[29]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n1651), .CK(
n5382), .RN(n5350), .Q(FPMULT_Op_MY[25]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_23_ ( .D(n1785), .CK(n5416), .RN(n5335),
.Q(FPSENCOS_d_ff_Yn[23]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_24_ ( .D(n1782), .CK(n5417), .RN(n5334),
.Q(FPSENCOS_d_ff_Yn[24]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_25_ ( .D(n1779), .CK(n5417), .RN(n5333),
.Q(FPSENCOS_d_ff_Yn[25]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_26_ ( .D(n1776), .CK(n5418), .RN(n5333),
.Q(FPSENCOS_d_ff_Yn[26]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_27_ ( .D(n1773), .CK(n5445), .RN(n5332),
.Q(FPSENCOS_d_ff_Yn[27]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_28_ ( .D(n1770), .CK(n5419), .RN(n5307),
.Q(FPSENCOS_d_ff_Yn[28]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_29_ ( .D(n1767), .CK(n5426), .RN(n5330),
.Q(FPSENCOS_d_ff_Yn[29]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_30_ ( .D(n1730), .CK(n5423), .RN(n5330),
.Q(FPSENCOS_d_ff_Yn[30]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_22_ ( .D(n2007), .CK(n5422), .RN(n5329),
.Q(FPSENCOS_d_ff_Yn[22]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_15_ ( .D(n2028), .CK(n5447), .RN(n2408),
.Q(FPSENCOS_d_ff_Yn[15]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_18_ ( .D(n2019), .CK(n5447), .RN(n5327),
.Q(FPSENCOS_d_ff_Yn[18]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_21_ ( .D(n2010), .CK(n5424), .RN(n5327),
.Q(FPSENCOS_d_ff_Yn[21]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_19_ ( .D(n2016), .CK(n5410), .RN(n5305),
.Q(FPSENCOS_d_ff_Yn[19]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_20_ ( .D(n2013), .CK(n5444), .RN(n5304),
.Q(FPSENCOS_d_ff_Yn[20]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_17_ ( .D(n2022), .CK(n2659), .RN(n5304),
.Q(FPSENCOS_d_ff_Yn[17]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_4_ ( .D(n2061), .CK(n5452), .RN(n5303), .Q(
FPSENCOS_d_ff_Yn[4]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_6_ ( .D(n2055), .CK(n5456), .RN(n2406), .Q(
FPSENCOS_d_ff_Yn[6]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_13_ ( .D(n2034), .CK(n5435), .RN(n5301),
.Q(FPSENCOS_d_ff_Yn[13]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_16_ ( .D(n2025), .CK(n5435), .RN(n2406),
.Q(FPSENCOS_d_ff_Yn[16]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_8_ ( .D(n2049), .CK(n5454), .RN(n2408), .Q(
FPSENCOS_d_ff_Yn[8]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_11_ ( .D(n2040), .CK(n5447), .RN(n5300),
.Q(FPSENCOS_d_ff_Yn[11]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_14_ ( .D(n2031), .CK(n5459), .RN(n5299),
.Q(FPSENCOS_d_ff_Yn[14]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_10_ ( .D(n2043), .CK(n5460), .RN(n5298),
.Q(FPSENCOS_d_ff_Yn[10]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_12_ ( .D(n2037), .CK(n5461), .RN(n5297),
.Q(FPSENCOS_d_ff_Yn[12]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_3_ ( .D(n2064), .CK(n2376), .RN(n5296), .Q(
FPSENCOS_d_ff_Yn[3]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_2_ ( .D(n2067), .CK(n5410), .RN(n5295), .Q(
FPSENCOS_d_ff_Yn[2]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_7_ ( .D(n2052), .CK(n5434), .RN(n5317), .Q(
FPSENCOS_d_ff_Yn[7]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_0_ ( .D(n2073), .CK(n5429), .RN(n5331), .Q(
FPSENCOS_d_ff_Yn[0]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_1_ ( .D(n2070), .CK(n5383), .RN(n5315), .Q(
FPSENCOS_d_ff_Yn[1]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_9_ ( .D(n2046), .CK(n5454), .RN(n5314), .Q(
FPSENCOS_d_ff_Yn[9]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_5_ ( .D(n2058), .CK(n5373), .RN(n5316), .Q(
FPSENCOS_d_ff_Yn[5]) );
DFFRX1TS operation_dff_Q_reg_1_ ( .D(operation[2]), .CK(n5434), .RN(n5326),
.Q(operation_reg[1]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n1649), .CK(
n5381), .RN(n5350), .Q(FPMULT_Op_MY[23]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n1656), .CK(
n5389), .RN(n5351), .Q(FPMULT_Op_MY[30]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_38_ ( .D(n1567),
.CK(n5384), .RN(n5309), .Q(FPMULT_P_Sgf[38]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_30_ ( .D(n1559),
.CK(n5387), .RN(n5309), .Q(FPMULT_P_Sgf[30]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_27_ ( .D(n1556),
.CK(n5376), .RN(n5308), .Q(FPMULT_P_Sgf[27]) );
DFFRX1TS FPSENCOS_reg_sign_Q_reg_0_ ( .D(n1732), .CK(n5461), .RN(n5296), .Q(
FPSENCOS_d_ff3_sign_out) );
DFFRX1TS operation_dff_Q_reg_0_ ( .D(operation[1]), .CK(n5373), .RN(n5295),
.Q(operation_reg[0]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_31_ ( .D(n1727), .CK(n5461), .RN(n5296),
.Q(FPSENCOS_d_ff_Xn[31]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n1685), .CK(
n5421), .RN(n5356), .Q(FPMULT_Op_MX[27]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n1681), .CK(
n5422), .RN(n5356), .Q(FPMULT_Op_MX[23]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_21_ ( .D(n1865), .CK(n2668),
.RN(n5327), .Q(FPSENCOS_d_ff2_Y[21]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_4_ ( .D(n1899), .CK(n5452), .RN(
n5303), .Q(FPSENCOS_d_ff2_Y[4]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_6_ ( .D(n1895), .CK(n5362), .RN(
n5339), .Q(FPSENCOS_d_ff2_Y[6]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_8_ ( .D(n1891), .CK(n5412), .RN(
n5300), .Q(FPSENCOS_d_ff2_Y[8]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_10_ ( .D(n1887), .CK(n5460),
.RN(n5298), .Q(FPSENCOS_d_ff2_Y[10]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_12_ ( .D(n1883), .CK(n5461),
.RN(n5297), .Q(FPSENCOS_d_ff2_Y[12]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_2_ ( .D(n1903), .CK(n5412), .RN(
n5300), .Q(FPSENCOS_d_ff2_Y[2]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_0_ ( .D(n1907), .CK(n5428), .RN(
n5316), .Q(FPSENCOS_d_ff2_Y[0]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_1_ ( .D(n1905), .CK(n5463), .RN(
n5315), .Q(FPSENCOS_d_ff2_Y[1]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_9_ ( .D(n1889), .CK(n5412), .RN(
n5314), .Q(FPSENCOS_d_ff2_Y[9]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n1686), .CK(
n5423), .RN(n5356), .Q(FPMULT_Op_MX[28]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n1683), .CK(
n5447), .RN(n5356), .Q(FPMULT_Op_MX[25]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n1682), .CK(
n5420), .RN(n5356), .Q(FPMULT_Op_MX[24]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_22_ ( .D(n1863), .CK(n5423),
.RN(n5329), .Q(FPSENCOS_d_ff2_Y[22]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_15_ ( .D(n1877), .CK(n5421),
.RN(n2408), .Q(FPSENCOS_d_ff2_Y[15]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_18_ ( .D(n1871), .CK(n5424),
.RN(n5327), .Q(FPSENCOS_d_ff2_Y[18]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_19_ ( .D(n1869), .CK(n5453),
.RN(n5305), .Q(FPSENCOS_d_ff2_Y[19]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_20_ ( .D(n1867), .CK(n5427),
.RN(n5304), .Q(FPSENCOS_d_ff2_Y[20]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_17_ ( .D(n1873), .CK(n5392),
.RN(n5303), .Q(FPSENCOS_d_ff2_Y[17]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_13_ ( .D(n1881), .CK(n5453),
.RN(n5301), .Q(FPSENCOS_d_ff2_Y[13]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_16_ ( .D(n1875), .CK(n5363),
.RN(n5326), .Q(FPSENCOS_d_ff2_Y[16]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_11_ ( .D(n1885), .CK(n5443),
.RN(n5300), .Q(FPSENCOS_d_ff2_Y[11]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_14_ ( .D(n1879), .CK(n5441),
.RN(n5299), .Q(FPSENCOS_d_ff2_Y[14]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_31_ ( .D(n1845), .CK(n5462),
.RN(n5296), .Q(FPSENCOS_d_ff2_Y[31]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_3_ ( .D(n1901), .CK(n2376), .RN(
n5295), .Q(FPSENCOS_d_ff2_Y[3]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_7_ ( .D(n1893), .CK(n5438), .RN(
n5340), .Q(FPSENCOS_d_ff2_Y[7]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_5_ ( .D(n1897), .CK(n5375), .RN(
n5340), .Q(FPSENCOS_d_ff2_Y[5]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n1204), .CK(n5400), .RN(
n5288), .Q(FPADDSUB_DmP_mant_SFG_SWR[1]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_0_ ( .D(n1594), .CK(n5385),
.RN(n5347), .Q(FPMULT_exp_oper_result[0]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_1_ ( .D(n1593), .CK(n5385),
.RN(n5347), .Q(FPMULT_exp_oper_result[1]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_2_ ( .D(n1592), .CK(n5385),
.RN(n5347), .Q(FPMULT_exp_oper_result[2]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_3_ ( .D(n1591), .CK(n5385),
.RN(n5347), .Q(FPMULT_exp_oper_result[3]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_4_ ( .D(n1590), .CK(n5384),
.RN(n5347), .Q(FPMULT_exp_oper_result[4]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_5_ ( .D(n1589), .CK(n5387),
.RN(n5347), .Q(FPMULT_exp_oper_result[5]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_6_ ( .D(n1588), .CK(n5389),
.RN(n5347), .Q(FPMULT_exp_oper_result[6]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_7_ ( .D(n1587), .CK(n5379),
.RN(n5347), .Q(FPMULT_exp_oper_result[7]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_31_ ( .D(n1908), .CK(n5462), .RN(n5296),
.Q(FPSENCOS_d_ff_Yn[31]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_45_ ( .D(n1574),
.CK(n5380), .RN(n5331), .Q(FPMULT_P_Sgf[45]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n1684), .CK(
n5421), .RN(n5356), .Q(FPMULT_Op_MX[26]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DmP_Q_reg_23_ ( .D(n1417), .CK(n5404), .RN(n5269), .Q(FPADDSUB_DmP_EXP_EWSW[23]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_25_ ( .D(n1554),
.CK(n5380), .RN(n5308), .Q(FPMULT_P_Sgf[25]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n1688), .CK(
n5422), .RN(n5357), .Q(FPMULT_Op_MX[30]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n1687), .CK(
n5423), .RN(n5356), .Q(FPMULT_Op_MX[29]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n1793), .CK(n5452), .RN(
n5259), .Q(FPADDSUB_Data_array_SWR[6]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_29_ ( .D(n1558),
.CK(n5379), .RN(n5308), .Q(FPMULT_P_Sgf[29]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_26_ ( .D(n1555),
.CK(n5384), .RN(n5308), .Q(FPMULT_P_Sgf[26]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_46_ ( .D(n1575),
.CK(n5388), .RN(n5316), .Q(FPMULT_P_Sgf[46]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_44_ ( .D(n1573),
.CK(n2654), .RN(n5340), .Q(FPMULT_P_Sgf[44]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DmP_Q_reg_27_ ( .D(n1413), .CK(n5413), .RN(n5269), .Q(FPADDSUB_DmP_EXP_EWSW[27]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_43_ ( .D(n1572),
.CK(n5384), .RN(n5322), .Q(FPMULT_P_Sgf[43]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_41_ ( .D(n1570),
.CK(n5387), .RN(n2404), .Q(FPMULT_P_Sgf[41]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_42_ ( .D(n1571),
.CK(n5382), .RN(n5310), .Q(FPMULT_P_Sgf[42]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_40_ ( .D(n1569),
.CK(n5380), .RN(n5319), .Q(FPMULT_P_Sgf[40]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_34_ ( .D(n1563),
.CK(n5387), .RN(n5309), .Q(FPMULT_P_Sgf[34]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_31_ ( .D(n1733), .CK(n5462),
.RN(n5297), .Q(FPSENCOS_d_ff2_Z[31]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_37_ ( .D(n1566),
.CK(n5382), .RN(n5309), .Q(FPMULT_P_Sgf[37]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_33_ ( .D(n1562),
.CK(n5389), .RN(n5309), .Q(FPMULT_P_Sgf[33]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n1605), .CK(n5376),
.RN(n5353), .Q(FPMULT_Add_result[15]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n1609), .CK(n5380),
.RN(n5352), .Q(FPMULT_Add_result[11]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n1613), .CK(n5388),
.RN(n5352), .Q(FPMULT_Add_result[7]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n1600), .CK(n5386),
.RN(n5353), .Q(FPMULT_Add_result[20]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n1606), .CK(n5386),
.RN(n5353), .Q(FPMULT_Add_result[14]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n1616), .CK(n5393),
.RN(n5352), .Q(FPMULT_Add_result[4]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n1615), .CK(n5384),
.RN(n5352), .Q(FPMULT_Add_result[5]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n1602), .CK(n5384),
.RN(n5353), .Q(FPMULT_Add_result[18]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n1604), .CK(n5393),
.RN(n5353), .Q(FPMULT_Add_result[16]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n1610), .CK(n5376),
.RN(n5352), .Q(FPMULT_Add_result[10]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n1791), .CK(n2375), .RN(
n5265), .Q(FPADDSUB_Data_array_SWR[4]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n1618), .CK(n5381),
.RN(n5351), .Q(FPMULT_Add_result[2]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n1612), .CK(n5381),
.RN(n5352), .Q(FPMULT_Add_result[8]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n1792), .CK(n5421), .RN(
n5258), .Q(FPADDSUB_Data_array_SWR[5]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n1794), .CK(n5435), .RN(
n5260), .Q(FPADDSUB_Data_array_SWR[7]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_24_ ( .D(n1464), .CK(n5437), .RN(n5266), .Q(FPADDSUB_DMP_EXP_EWSW[24]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_26_ ( .D(n1462), .CK(n5437), .RN(n5266), .Q(FPADDSUB_DMP_EXP_EWSW[26]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n1598), .CK(n2654),
.RN(n5353), .Q(FPMULT_Add_result[22]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_24_ ( .D(n1860), .CK(n5417),
.RN(n5334), .Q(FPSENCOS_d_ff2_Y[24]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_25_ ( .D(n1859), .CK(n5418),
.RN(n5333), .Q(FPSENCOS_d_ff2_Y[25]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_26_ ( .D(n1858), .CK(n5418),
.RN(n5333), .Q(FPSENCOS_d_ff2_Y[26]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_25_ ( .D(n1463), .CK(n5437), .RN(n5266), .Q(FPADDSUB_DMP_EXP_EWSW[25]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_27_ ( .D(n1461), .CK(n2662), .RN(n5266), .Q(FPADDSUB_DMP_EXP_EWSW[27]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n1205), .CK(n5400), .RN(
n5288), .Q(FPADDSUB_DmP_mant_SFG_SWR[0]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n1518), .CK(
n2669), .RN(n5345), .Q(FPMULT_Sgf_normalized_result[13]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n1514), .CK(
n2664), .RN(n5345), .Q(FPMULT_Sgf_normalized_result[9]) );
DFFRX1TS FPMULT_Exp_module_Underflow_m_Q_reg_0_ ( .D(n1586), .CK(n5383),
.RN(n5344), .Q(underflow_flag_mult) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_30_ ( .D(n1854), .CK(n5447),
.RN(n5330), .Q(FPSENCOS_d_ff2_Y[30]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n1815), .CK(n5447),
.RN(n5257), .Q(FPADDSUB_intDY_EWSW[28]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_23_ ( .D(n1861), .CK(n5416),
.RN(n5335), .Q(FPSENCOS_d_ff2_Y[23]) );
DFFRX1TS FPMULT_Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n1585), .CK(n5387), .RN(
n5346), .Q(FPMULT_Exp_module_Overflow_flag_A) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n1526), .CK(
n2662), .RN(n5346), .Q(FPMULT_Sgf_normalized_result[21]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n1527), .CK(
n5369), .RN(n5346), .Q(FPMULT_Sgf_normalized_result[22]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n1524), .CK(
n5377), .RN(n5346), .Q(FPMULT_Sgf_normalized_result[19]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n1516), .CK(
n2669), .RN(n5345), .Q(FPMULT_Sgf_normalized_result[11]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n1510), .CK(
n2664), .RN(n5344), .Q(FPMULT_Sgf_normalized_result[5]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_27_ ( .D(n1857), .CK(n5465),
.RN(n5332), .Q(FPSENCOS_d_ff2_Y[27]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_29_ ( .D(n1855), .CK(n5417),
.RN(n5330), .Q(FPSENCOS_d_ff2_Y[29]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n1910), .CK(n2376),
.RN(n5262), .Q(FPADDSUB_intDX_EWSW[31]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n1797), .CK(n5428), .RN(
n5265), .Q(FPADDSUB_Data_array_SWR[10]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n1798), .CK(n5460), .RN(
n5262), .Q(FPADDSUB_Data_array_SWR[11]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n1796), .CK(n5362), .RN(
n5261), .Q(FPADDSUB_Data_array_SWR[9]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n1912), .CK(n2374),
.RN(n5256), .Q(FPADDSUB_intDX_EWSW[29]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n1795), .CK(n5430), .RN(
n5265), .Q(FPADDSUB_Data_array_SWR[8]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_14_ ( .D(n1258), .CK(n5394), .RN(n5283), .Q(FPADDSUB_DMP_SFG[14]) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]), .CK(n5429), .RN(n5316),
.Q(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_2_ ( .D(n1307), .CK(n5409), .RN(n5278),
.Q(FPADDSUB_DMP_SFG[2]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_20_ ( .D(n1226), .CK(n5398), .RN(n5286), .Q(FPADDSUB_DMP_SFG[20]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_21_ ( .D(n1218), .CK(n5398), .RN(n5287), .Q(FPADDSUB_DMP_SFG[21]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_1_ ( .D(n1286), .CK(n5383), .RN(n5280),
.Q(FPADDSUB_DMP_SFG[1]) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]), .CK(n5429), .RN(n2408),
.Q(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_5_ ( .D(n1272), .CK(n5376), .RN(n5281),
.Q(FPADDSUB_DMP_SFG[5]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_6_ ( .D(n1238), .CK(n5396), .RN(n5285),
.Q(FPADDSUB_DMP_SFG[6]) );
DFFRX2TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n1506), .CK(
n5455), .RN(n5344), .Q(FPMULT_Sgf_normalized_result[1]) );
DFFRX2TS FPADDSUB_Ready_reg_Q_reg_0_ ( .D(n4877), .CK(n5428), .RN(n5255),
.Q(ready_add_subt) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n1804), .CK(n5430), .RN(
n5265), .Q(FPADDSUB_Data_array_SWR[17]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n1347), .CK(n5406), .RN(
n5275), .Q(FPADDSUB_Raw_mant_NRM_SWR[2]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n1839), .CK(n5452),
.RN(n5259), .Q(FPADDSUB_intDY_EWSW[4]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n1349), .CK(n2660), .RN(
n5275), .Q(FPADDSUB_Raw_mant_NRM_SWR[0]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n1803), .CK(n5443), .RN(
n5259), .Q(FPADDSUB_Data_array_SWR[16]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n1336), .CK(n5408), .RN(
n2701), .Q(FPADDSUB_Raw_mant_NRM_SWR[13]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n1816), .CK(n5422),
.RN(n5257), .Q(FPADDSUB_intDY_EWSW[27]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n1799), .CK(n5447), .RN(
n5261), .Q(FPADDSUB_Data_array_SWR[12]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n1342), .CK(n2660), .RN(
n2410), .Q(FPADDSUB_Raw_mant_NRM_SWR[7]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n1800), .CK(n5459), .RN(
n5261), .Q(FPADDSUB_Data_array_SWR[13]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n1926), .CK(n5420),
.RN(n5258), .Q(FPADDSUB_intDX_EWSW[15]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n1827), .CK(n5361),
.RN(n5260), .Q(FPADDSUB_intDY_EWSW[16]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n1916), .CK(n5418),
.RN(n5256), .Q(FPADDSUB_intDX_EWSW[25]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n1927), .CK(n5459),
.RN(n5261), .Q(FPADDSUB_intDX_EWSW[14]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n1805), .CK(n5459), .RN(
n5264), .Q(FPADDSUB_Data_array_SWR[18]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n1802), .CK(n5454), .RN(
n5260), .Q(FPADDSUB_Data_array_SWR[15]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n1831), .CK(n5462),
.RN(n5262), .Q(FPADDSUB_intDY_EWSW[12]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n1928), .CK(n5367),
.RN(n5260), .Q(FPADDSUB_intDX_EWSW[13]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n1841), .CK(n5435),
.RN(n5263), .Q(FPADDSUB_intDY_EWSW[2]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n1922), .CK(n5410),
.RN(n5258), .Q(FPADDSUB_intDX_EWSW[19]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n1838), .CK(n5402),
.RN(n5264), .Q(FPADDSUB_intDY_EWSW[5]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n1919), .CK(n5423),
.RN(n5257), .Q(FPADDSUB_intDX_EWSW[22]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n1809), .CK(n5440), .RN(
n5264), .Q(FPADDSUB_Data_array_SWR[22]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n1806), .CK(n5450), .RN(
n5259), .Q(FPADDSUB_Data_array_SWR[19]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n1835), .CK(n5421),
.RN(n5260), .Q(FPADDSUB_intDY_EWSW[8]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n1842), .CK(n5459),
.RN(n5264), .Q(FPADDSUB_intDY_EWSW[1]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n1826), .CK(n5368),
.RN(n5259), .Q(FPADDSUB_intDY_EWSW[17]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n1834), .CK(n5412),
.RN(n5264), .Q(FPADDSUB_intDY_EWSW[9]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_15_ ( .D(n1210), .CK(n5412), .RN(n5288), .Q(FPADDSUB_DMP_SFG[15]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n1203), .CK(n5400), .RN(
n5288), .Q(FPADDSUB_DmP_mant_SFG_SWR[2]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n1340), .CK(n2660), .RN(
n5294), .Q(FPADDSUB_Raw_mant_NRM_SWR[9]) );
DFFRX2TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n1505), .CK(
n5440), .RN(n5344), .Q(FPMULT_Sgf_normalized_result[0]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n1199), .CK(n5400), .RN(
n5289), .Q(FPADDSUB_DmP_mant_SFG_SWR[6]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n1341), .CK(n5409), .RN(
n5294), .Q(FPADDSUB_Raw_mant_NRM_SWR[8]) );
DFFRX2TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n2076), .CK(n5375),
.RN(n5263), .Q(FPADDSUB_shift_value_SHT2_EWR[3]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n1333), .CK(n5373), .RN(
n5276), .Q(FPADDSUB_Raw_mant_NRM_SWR[16]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n1320), .CK(n5411), .RN(
n5277), .Q(FPADDSUB_Raw_mant_NRM_SWR[20]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n1634), .CK(n5387), .RN(n5349), .Q(n2205), .QN(n5049) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n1648), .CK(
n5393), .RN(n5350), .Q(FPMULT_Op_MY[22]), .QN(n4960) );
CMPR32X2TS DP_OP_234J200_127_8543_U10 ( .A(FPMULT_S_Oper_A_exp[0]), .B(n2274), .C(DP_OP_234J200_127_8543_n22), .CO(DP_OP_234J200_127_8543_n9), .S(
FPMULT_Exp_module_Data_S[0]) );
CMPR32X2TS DP_OP_234J200_127_8543_U9 ( .A(DP_OP_234J200_127_8543_n21), .B(
FPMULT_S_Oper_A_exp[1]), .C(DP_OP_234J200_127_8543_n9), .CO(
DP_OP_234J200_127_8543_n8), .S(FPMULT_Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_234J200_127_8543_U8 ( .A(DP_OP_234J200_127_8543_n20), .B(
FPMULT_S_Oper_A_exp[2]), .C(DP_OP_234J200_127_8543_n8), .CO(
DP_OP_234J200_127_8543_n7), .S(FPMULT_Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_234J200_127_8543_U7 ( .A(DP_OP_234J200_127_8543_n19), .B(
FPMULT_S_Oper_A_exp[3]), .C(DP_OP_234J200_127_8543_n7), .CO(
DP_OP_234J200_127_8543_n6), .S(FPMULT_Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_234J200_127_8543_U6 ( .A(DP_OP_234J200_127_8543_n18), .B(
FPMULT_S_Oper_A_exp[4]), .C(DP_OP_234J200_127_8543_n6), .CO(
DP_OP_234J200_127_8543_n5), .S(FPMULT_Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_234J200_127_8543_U5 ( .A(DP_OP_234J200_127_8543_n17), .B(
FPMULT_S_Oper_A_exp[5]), .C(DP_OP_234J200_127_8543_n5), .CO(
DP_OP_234J200_127_8543_n4), .S(FPMULT_Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_234J200_127_8543_U4 ( .A(DP_OP_234J200_127_8543_n16), .B(
FPMULT_S_Oper_A_exp[6]), .C(DP_OP_234J200_127_8543_n4), .CO(
DP_OP_234J200_127_8543_n3), .S(FPMULT_Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_234J200_127_8543_U3 ( .A(DP_OP_234J200_127_8543_n15), .B(
FPMULT_S_Oper_A_exp[7]), .C(DP_OP_234J200_127_8543_n3), .CO(
DP_OP_234J200_127_8543_n2), .S(FPMULT_Exp_module_Data_S[7]) );
CMPR32X2TS DP_OP_26J200_124_9022_U8 ( .A(DP_OP_26J200_124_9022_n17), .B(
FPADDSUB_DMP_exp_NRM2_EW[1]), .C(DP_OP_26J200_124_9022_n8), .CO(
DP_OP_26J200_124_9022_n7), .S(FPADDSUB_exp_rslt_NRM2_EW1[1]) );
CMPR32X2TS DP_OP_26J200_124_9022_U7 ( .A(DP_OP_26J200_124_9022_n16), .B(
FPADDSUB_DMP_exp_NRM2_EW[2]), .C(DP_OP_26J200_124_9022_n7), .CO(
DP_OP_26J200_124_9022_n6), .S(FPADDSUB_exp_rslt_NRM2_EW1[2]) );
CMPR32X2TS DP_OP_26J200_124_9022_U6 ( .A(DP_OP_26J200_124_9022_n15), .B(
FPADDSUB_DMP_exp_NRM2_EW[3]), .C(DP_OP_26J200_124_9022_n6), .CO(
DP_OP_26J200_124_9022_n5), .S(FPADDSUB_exp_rslt_NRM2_EW1[3]) );
CMPR32X2TS DP_OP_26J200_124_9022_U5 ( .A(DP_OP_26J200_124_9022_n14), .B(
FPADDSUB_DMP_exp_NRM2_EW[4]), .C(DP_OP_26J200_124_9022_n5), .CO(
DP_OP_26J200_124_9022_n4), .S(FPADDSUB_exp_rslt_NRM2_EW1[4]) );
CMPR32X2TS DP_OP_234J200_127_8543_U2 ( .A(n2274), .B(FPMULT_S_Oper_A_exp[8]),
.C(DP_OP_234J200_127_8543_n2), .CO(DP_OP_234J200_127_8543_n1), .S(
FPMULT_Exp_module_Data_S[8]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_21_ ( .D(n1864), .CK(n5362), .RN(n5326),
.Q(FPSENCOS_d_ff3_sh_y_out[21]), .QN(n5245) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_1_ ( .D(n1659), .CK(n5388), .RN(n5354), .Q(FPMULT_Op_MX[1]), .QN(n5029) );
DFFRX4TS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n2078), .CK(n2376),
.RN(n5262), .Q(FPADDSUB_left_right_SHT2), .QN(n5026) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_19_ ( .D(n1677), .CK(
n5365), .RN(n5355), .Q(FPMULT_Op_MX[19]), .QN(n4927) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_14_ ( .D(n1672), .CK(
n5372), .RN(n5355), .Q(FPMULT_Op_MX[14]), .QN(n5078) );
DFFRX1TS reg_dataB_Q_reg_26_ ( .D(Data_2[26]), .CK(n5426), .RN(n5311), .Q(
dataB[26]) );
DFFRX1TS reg_dataB_Q_reg_28_ ( .D(Data_2[28]), .CK(n5426), .RN(n5323), .Q(
dataB[28]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_6_ ( .D(n1664), .CK(n5463), .RN(n5354), .Q(FPMULT_Op_MX[6]), .QN(n5079) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_10_ ( .D(n1636), .CK(
n5379), .RN(n5349), .Q(FPMULT_Op_MY[10]), .QN(n5045) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_18_ ( .D(n1547),
.CK(n2654), .RN(n5340), .Q(FPMULT_P_Sgf[18]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_16_ ( .D(n1545),
.CK(n5382), .RN(n2404), .Q(FPMULT_P_Sgf[16]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_12_ ( .D(n1541),
.CK(n2654), .RN(n5322), .Q(FPMULT_P_Sgf[12]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_21_ ( .D(n1550),
.CK(n5389), .RN(n5308), .Q(FPMULT_P_Sgf[21]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_17_ ( .D(n1546),
.CK(n5388), .RN(n5307), .Q(FPMULT_P_Sgf[17]) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]), .CK(n5430), .RN(n2404),
.Q(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .QN(n5020) );
DFFRX1TS FPSENCOS_reg_Z0_Q_reg_11_ ( .D(n2101), .CK(n5419), .RN(n5337), .Q(
FPSENCOS_d_ff1_Z[11]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_3_ ( .D(n1532),
.CK(n2659), .RN(n5306), .Q(FPMULT_P_Sgf[3]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_1_ ( .D(n1530),
.CK(n5368), .RN(n5306), .Q(FPMULT_P_Sgf[1]) );
DFFRX1TS reg_dataB_Q_reg_24_ ( .D(Data_2[24]), .CK(n2668), .RN(n5323), .Q(
dataB[24]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_21_ ( .D(n1679), .CK(
n5447), .RN(n5356), .Q(FPMULT_Op_MX[21]), .QN(n4931) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n1647), .CK(
n5387), .RN(n5350), .Q(FPMULT_Op_MY[21]), .QN(n5037) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_17_ ( .D(n1643), .CK(
n2656), .RN(n5350), .Q(FPMULT_Op_MY[17]), .QN(n5039) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_13_ ( .D(n1639), .CK(
n5436), .RN(n5349), .Q(FPMULT_Op_MY[13]), .QN(n4959) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_20_ ( .D(n1646), .CK(
n2659), .RN(n5350), .Q(FPMULT_Op_MY[20]), .QN(n5031) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_18_ ( .D(n1644), .CK(
n5437), .RN(n5350), .Q(FPMULT_Op_MY[18]), .QN(n4961) );
DFFRX4TS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1350), .CK(n5409),
.RN(n5292), .Q(FPADDSUB_ADD_OVRFLW_NRM2), .QN(n5028) );
DFFRX1TS R_12 ( .D(n5251), .CK(n5424), .RN(n5326), .Q(n5466) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_2_ ( .D(n1628), .CK(n5393), .RN(n5348), .Q(FPMULT_Op_MY[2]), .QN(n5051) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]), .CK(n5439), .RN(n5340),
.Q(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(n5358), .CK(n5430), .RN(n2404), .Q(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]), .CK(n5427), .RN(n5322),
.Q(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRX1TS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_15_ ( .D(n1544),
.CK(n5388), .RN(n5310), .Q(FPMULT_P_Sgf[15]) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_1_ ( .D(n2140), .CK(n5439), .RN(n5310),
.Q(FPSENCOS_cont_iter_out[1]), .QN(n2202) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_3_ ( .D(n1661), .CK(n5386), .RN(n5354), .Q(n2198), .QN(n4956) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_22_ ( .D(n1680), .CK(
n5421), .RN(n5356), .Q(n2200), .QN(n2230) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_0_ ( .D(n1658), .CK(n5376), .RN(n5354), .Q(FPMULT_Op_MX[0]), .QN(n4932) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_7_ ( .D(n1665), .CK(n5451), .RN(n5354), .Q(FPMULT_Op_MX[7]), .QN(n4934) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_17_ ( .D(n1675), .CK(
n5399), .RN(n5355), .Q(FPMULT_Op_MX[17]), .QN(n4928) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n1637), .CK(
n5451), .RN(n5349), .Q(n2201), .QN(n5047) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_0_ ( .D(n1626), .CK(n5385), .RN(n5348), .Q(FPMULT_Op_MY[0]), .QN(n4957) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_12_ ( .D(n1638), .CK(
n5436), .RN(n5349), .Q(FPMULT_Op_MY[12]), .QN(n4935) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_15_ ( .D(n1641), .CK(
n5436), .RN(n5349), .Q(n2203), .QN(n5046) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_4_ ( .D(n1630), .CK(n5381), .RN(n5348), .Q(n2204), .QN(n5050) );
DFFRX2TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n2075), .CK(n2376),
.RN(n5262), .Q(FPADDSUB_shift_value_SHT2_EWR[4]), .QN(n2199) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_9_ ( .D(n1667), .CK(n5384), .RN(n5354), .Q(FPMULT_Op_MX[9]), .QN(n4933) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_15_ ( .D(n1673), .CK(
n5378), .RN(n5355), .Q(FPMULT_Op_MX[15]), .QN(n5027) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n1669), .CK(
n2669), .RN(n5355), .Q(FPMULT_Op_MX[11]), .QN(n4926) );
DFFSX1TS R_4 ( .D(n5253), .CK(n5425), .SN(n2404), .Q(n5469) );
DFFSX1TS R_11 ( .D(n5252), .CK(n5425), .SN(n5339), .Q(n5467) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n1617), .CK(n5389),
.RN(n5351), .Q(FPMULT_Add_result[3]), .QN(n5169) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_26_ ( .D(n1956), .CK(n2663),
.RN(n5332), .Q(FPSENCOS_d_ff2_X[26]), .QN(n5166) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_25_ ( .D(n1957), .CK(n5418),
.RN(n5333), .Q(FPSENCOS_d_ff2_X[25]), .QN(n5165) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_24_ ( .D(n1958), .CK(n2374),
.RN(n5334), .Q(FPSENCOS_d_ff2_X[24]), .QN(n5164) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_20_ ( .D(n1965), .CK(n5439),
.RN(n5304), .Q(FPSENCOS_d_ff2_X[20]), .QN(n5163) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_19_ ( .D(n1967), .CK(n5453),
.RN(n5305), .Q(FPSENCOS_d_ff2_X[19]), .QN(n5162) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_17_ ( .D(n1971), .CK(n5392),
.RN(n5303), .Q(FPSENCOS_d_ff2_X[17]), .QN(n5161) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_16_ ( .D(n1973), .CK(n5412),
.RN(n2408), .Q(FPSENCOS_d_ff2_X[16]), .QN(n5160) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_14_ ( .D(n1977), .CK(n5441),
.RN(n5298), .Q(FPSENCOS_d_ff2_X[14]), .QN(n5159) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_13_ ( .D(n1979), .CK(n5375),
.RN(n5301), .Q(FPSENCOS_d_ff2_X[13]), .QN(n5158) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_12_ ( .D(n1981), .CK(n5461),
.RN(n5297), .Q(FPSENCOS_d_ff2_X[12]), .QN(n5157) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_10_ ( .D(n1985), .CK(n5460),
.RN(n5298), .Q(FPSENCOS_d_ff2_X[10]), .QN(n5156) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_7_ ( .D(n1991), .CK(n5433), .RN(
n5319), .Q(FPSENCOS_d_ff2_X[7]), .QN(n5155) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_6_ ( .D(n1993), .CK(n5435), .RN(
n5302), .Q(FPSENCOS_d_ff2_X[6]), .QN(n5154) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_5_ ( .D(n1995), .CK(n5375), .RN(
n5318), .Q(FPSENCOS_d_ff2_X[5]), .QN(n5153) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_3_ ( .D(n1999), .CK(n5448), .RN(
n5295), .Q(FPSENCOS_d_ff2_X[3]), .QN(n5152) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_2_ ( .D(n2001), .CK(n5361), .RN(
n5317), .Q(FPSENCOS_d_ff2_X[2]), .QN(n5151) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_1_ ( .D(n2003), .CK(n5441), .RN(
n5314), .Q(FPSENCOS_d_ff2_X[1]), .QN(n5150) );
DFFSX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]), .CK(n5461), .SN(n5338),
.Q(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]) );
DFFSX1TS R_3 ( .D(n5254), .CK(n5425), .SN(n5324), .Q(n5468) );
DFFRX1TS FPMULT_Sel_C_Q_reg_0_ ( .D(n1528), .CK(n2662), .RN(n5346), .Q(
FPMULT_FSM_selector_C) );
DFFRXLTS reg_dataA_Q_reg_26_ ( .D(Data_1[26]), .CK(n5425), .RN(n5325), .Q(
dataA[26]) );
DFFRXLTS reg_dataA_Q_reg_24_ ( .D(Data_1[24]), .CK(n5440), .RN(n5325), .Q(
dataA[24]) );
DFFRXLTS FPMULT_Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_14_ ( .D(n1543),
.CK(n5379), .RN(n5316), .Q(FPMULT_P_Sgf[14]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_5_ ( .D(n1663), .CK(n5369), .RN(n5354), .Q(FPMULT_Op_MX[5]), .QN(n4955) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_16_ ( .D(n1642), .CK(
n5392), .RN(n5349), .Q(n2194), .QN(n5032) );
CMPR32X2TS DP_OP_26J200_124_9022_U9 ( .A(FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
n5028), .C(DP_OP_26J200_124_9022_n18), .CO(DP_OP_26J200_124_9022_n8),
.S(FPADDSUB_exp_rslt_NRM2_EW1[0]) );
CMPR32X2TS DP_OP_26J200_124_9022_U4 ( .A(n5028), .B(
FPADDSUB_DMP_exp_NRM2_EW[5]), .C(DP_OP_26J200_124_9022_n4), .CO(
DP_OP_26J200_124_9022_n3), .S(FPADDSUB_exp_rslt_NRM2_EW1[5]) );
DFFRX2TS FPADDSUB_inst_ShiftRegister_Q_reg_6_ ( .D(n2148), .CK(n5430), .RN(
n5255), .Q(FPADDSUB_Shift_reg_FLAGS_7_6), .QN(n5023) );
CMPR32X2TS DP_OP_26J200_124_9022_U3 ( .A(n5028), .B(
FPADDSUB_DMP_exp_NRM2_EW[6]), .C(DP_OP_26J200_124_9022_n3), .CO(
DP_OP_26J200_124_9022_n2), .S(FPADDSUB_exp_rslt_NRM2_EW1[6]) );
CMPR32X2TS DP_OP_26J200_124_9022_U2 ( .A(n5028), .B(
FPADDSUB_DMP_exp_NRM2_EW[7]), .C(DP_OP_26J200_124_9022_n2), .CO(
DP_OP_26J200_124_9022_n1), .S(FPADDSUB_exp_rslt_NRM2_EW1[7]) );
DFFRX2TS FPADDSUB_inst_ShiftRegister_Q_reg_5_ ( .D(n2147), .CK(n5427), .RN(
n5255), .Q(FPADDSUB_Shift_reg_FLAGS_7_5), .QN(n4984) );
AOI222X4TS U2217 ( .A0(n4677), .A1(n5213), .B0(n4946), .B1(n3565), .C0(n5019), .C1(n2391), .Y(n3327) );
CLKBUFX2TS U2218 ( .A(n5358), .Y(n4689) );
CMPR32X2TS U2219 ( .A(FPSENCOS_d_ff2_Y[26]), .B(n5055), .C(n4182), .CO(n4183), .S(n4070) );
CMPR32X2TS U2220 ( .A(FPSENCOS_d_ff2_X[26]), .B(n5055), .C(n4194), .CO(n4246), .S(n4195) );
CMPR32X2TS U2221 ( .A(FPMULT_Op_MY[18]), .B(FPMULT_Op_MY[19]), .C(n4390),
.CO(mult_x_219_n42), .S(mult_x_219_n43) );
CMPR32X2TS U2222 ( .A(n4384), .B(n3731), .C(n3730), .CO(n3195), .S(n3732) );
CMPR32X2TS U2223 ( .A(FPMULT_Op_MY[13]), .B(n2235), .C(n4399), .CO(
mult_x_219_n71), .S(mult_x_219_n72) );
CMPR32X2TS U2224 ( .A(FPMULT_Op_MY[9]), .B(FPMULT_Op_MY[21]), .C(n3700),
.CO(n3689), .S(n4619) );
CMPR32X2TS U2225 ( .A(n2368), .B(FPMULT_Op_MY[20]), .C(n3214), .CO(n3700),
.S(n4622) );
CMPR32X2TS U2226 ( .A(n2341), .B(n2401), .C(n2799), .CO(n3752), .S(n4407) );
CMPR32X2TS U2227 ( .A(FPMULT_Op_MY[6]), .B(FPMULT_Op_MY[18]), .C(n2676),
.CO(n3206), .S(n4569) );
CMPR32X2TS U2228 ( .A(FPMULT_Op_MY[5]), .B(FPMULT_Op_MY[17]), .C(n2674),
.CO(n2676), .S(n4572) );
CMPR32X2TS U2229 ( .A(n2308), .B(FPMULT_Op_MX[19]), .C(n2694), .CO(n2695),
.S(n4592) );
CMPR32X2TS U2230 ( .A(FPMULT_Op_MX[5]), .B(n2306), .C(n2413), .CO(n2458),
.S(n4601) );
CMPR32X2TS U2231 ( .A(FPMULT_Op_MY[2]), .B(FPMULT_Op_MY[14]), .C(n2682),
.CO(n2681), .S(n4581) );
CMPR32X2TS U2232 ( .A(n2271), .B(FPMULT_Op_MX[15]), .C(n2673), .CO(n2672),
.S(n4624) );
CMPR32X2TS U2233 ( .A(FPMULT_Op_MX[2]), .B(FPMULT_Op_MX[14]), .C(n2679),
.CO(n2673), .S(n4612) );
CMPR32X2TS U2234 ( .A(n2399), .B(FPMULT_Op_MX[13]), .C(n2685), .CO(n2679),
.S(n4634) );
CLKBUFX3TS U2235 ( .A(n4590), .Y(n2268) );
CLKBUFX3TS U2236 ( .A(n4414), .Y(n2286) );
OR2X2TS U2237 ( .A(n4889), .B(n2344), .Y(n2963) );
CLKAND2X2TS U2238 ( .A(FPADDSUB_Shift_reg_FLAGS_7_6), .B(n2344), .Y(n2964)
);
NAND2BX4TS U2239 ( .AN(n4777), .B(n4776), .Y(n4884) );
CLKBUFX3TS U2240 ( .A(n4115), .Y(n3899) );
CLKBUFX3TS U2241 ( .A(n2863), .Y(n4115) );
NOR2X4TS U2242 ( .A(n2862), .B(n4670), .Y(n2861) );
NOR2X4TS U2243 ( .A(operation[1]), .B(n3368), .Y(n2860) );
ADDFX1TS U2244 ( .A(FPMULT_Op_MY[18]), .B(n3720), .CI(n3719), .CO(n3189),
.S(n3721) );
CMPR32X2TS U2245 ( .A(n2234), .B(n2194), .C(n2671), .CO(n2674), .S(n4575) );
CLKBUFX3TS U2246 ( .A(n3025), .Y(n4687) );
AOI21X2TS U2247 ( .A0(n3565), .A1(n5056), .B0(n3277), .Y(n2210) );
NOR2X4TS U2248 ( .A(n4688), .B(n3026), .Y(n3480) );
NAND2X2TS U2249 ( .A(n2858), .B(n4122), .Y(n2859) );
ADDFX1TS U2250 ( .A(n4384), .B(n4383), .CI(n4382), .CO(mult_x_254_n42), .S(
mult_x_254_n43) );
CLKBUFX2TS U2251 ( .A(n4683), .Y(n2360) );
CLKBUFX2TS U2252 ( .A(n4821), .Y(n2361) );
CLKBUFX2TS U2253 ( .A(n4778), .Y(n2362) );
OR3X2TS U2254 ( .A(FPMULT_FS_Module_state_reg[1]), .B(n5052), .C(n2632), .Y(
n2442) );
CLKBUFX2TS U2255 ( .A(FPMULT_Op_MY[22]), .Y(n2379) );
CLKAND2X2TS U2256 ( .A(n4464), .B(n4495), .Y(n4493) );
AND2X2TS U2257 ( .A(FPADDSUB_ADD_OVRFLW_NRM), .B(n4290), .Y(n4439) );
CLKBUFX3TS U2258 ( .A(n4927), .Y(n2299) );
NAND3X2TS U2259 ( .A(n4937), .B(FPSENCOS_cont_var_out[1]), .C(ready_add_subt), .Y(n3936) );
NOR2X4TS U2260 ( .A(operation[2]), .B(n4046), .Y(n3774) );
NAND2BXLTS U2261 ( .AN(mult_x_219_n163), .B(n4449), .Y(n4450) );
AO21XLTS U2262 ( .A0(FPMULT_Op_MX[16]), .A1(FPMULT_Op_MX[15]), .B0(n2354),
.Y(n2225) );
NAND2BXLTS U2263 ( .AN(mult_x_254_n169), .B(n4504), .Y(n4505) );
AOI32X1TS U2264 ( .A0(FPMULT_Op_MX[0]), .A1(n5029), .A2(n2205), .B0(n2400),
.B1(n2724), .Y(n3746) );
AO21XLTS U2265 ( .A0(FPMULT_Op_MX[4]), .A1(n2315), .B0(n4530), .Y(n2216) );
AO21XLTS U2266 ( .A0(n2675), .A1(n2340), .B0(n4599), .Y(n2208) );
CLKAND2X2TS U2267 ( .A(n2240), .B(n4636), .Y(n2227) );
OAI21X1TS U2268 ( .A0(FPMULT_Op_MX[11]), .A1(n3856), .B0(n2302), .Y(n4586)
);
AOI32X1TS U2269 ( .A0(FPMULT_Op_MX[18]), .A1(n2299), .A2(n2364), .B0(n4395),
.B1(n2398), .Y(n3719) );
AO22XLTS U2270 ( .A0(n4403), .A1(n2262), .B0(n4491), .B1(n4402), .Y(
mult_x_219_n206) );
AO22XLTS U2271 ( .A0(n4395), .A1(n4394), .B0(n2364), .B1(n4393), .Y(
mult_x_219_n189) );
AOI32X1TS U2272 ( .A0(n2384), .A1(FPADDSUB_Raw_mant_NRM_SWR[10]), .A2(n3011),
.B0(FPADDSUB_Raw_mant_NRM_SWR[18]), .B1(n2384), .Y(n2995) );
AOI32X1TS U2273 ( .A0(n2237), .A1(n5029), .A2(n2204), .B0(n2400), .B1(n2425),
.Y(n2750) );
OAI32X1TS U2274 ( .A0(n2402), .A1(n4406), .A2(n5048), .B0(n4470), .B1(n2331),
.Y(mult_x_219_n164) );
NAND4XLTS U2275 ( .A(n5138), .B(n4974), .C(n4929), .D(n4945), .Y(n2976) );
INVX2TS U2276 ( .A(n5026), .Y(n2320) );
AOI211X1TS U2277 ( .A0(n3972), .A1(n5208), .B0(n3973), .C0(n4439), .Y(n3002)
);
AO22XLTS U2278 ( .A0(FPADDSUB_Data_array_SWR[13]), .A1(n2305), .B0(
FPADDSUB_Data_array_SWR[17]), .B1(n2395), .Y(n4086) );
CLKAND2X2TS U2279 ( .A(n4312), .B(n5030), .Y(n2215) );
AO22XLTS U2280 ( .A0(n4000), .A1(n2962), .B0(n2961), .B1(n2960), .Y(n2211)
);
AOI32X1TS U2281 ( .A0(n2237), .A1(n5029), .A2(FPMULT_Op_MY[5]), .B0(n2740),
.B1(n2400), .Y(n2746) );
OAI32X1TS U2282 ( .A0(n2270), .A1(n2290), .A2(n5119), .B0(n2259), .B1(
mult_x_254_n197), .Y(n2747) );
OAI32X1TS U2283 ( .A0(n2258), .A1(n2417), .A2(n5029), .B0(n4543), .B1(n2269),
.Y(n3825) );
AOI222X1TS U2284 ( .A0(n2400), .A1(n2416), .B0(FPMULT_Op_MY[1]), .B1(n2319),
.C0(n5029), .C1(n2415), .Y(n3826) );
AOI211X2TS U2285 ( .A0(n2209), .A1(n4584), .B0(n4587), .C0(n2239), .Y(n3837)
);
NAND2BX1TS U2286 ( .AN(n3002), .B(n4693), .Y(n4694) );
CLKBUFX2TS U2287 ( .A(n2963), .Y(n4091) );
NAND2X1TS U2288 ( .A(n3002), .B(n4693), .Y(n3367) );
CLKINVX3TS U2289 ( .A(n5358), .Y(n4215) );
CLKINVX3TS U2290 ( .A(n3965), .Y(n4759) );
AO22XLTS U2291 ( .A0(operation[1]), .A1(n3990), .B0(begin_operation), .B1(
n3813), .Y(n2858) );
CLKINVX3TS U2292 ( .A(rst), .Y(n2409) );
AOI211X1TS U2293 ( .A0(n3089), .A1(n3088), .B0(n3087), .C0(n2323), .Y(n3090)
);
AOI211X1TS U2294 ( .A0(n3288), .A1(n3287), .B0(n3286), .C0(n2323), .Y(n3289)
);
OAI31X1TS U2295 ( .A0(n2270), .A1(n2417), .A2(n5029), .B0(n2414), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N1) );
AOI211X1TS U2296 ( .A0(n2920), .A1(n2919), .B0(n4188), .C0(n2323), .Y(n2921)
);
AOI211X1TS U2297 ( .A0(n2467), .A1(n2466), .B0(n2465), .C0(n2323), .Y(n2468)
);
BUFX6TS U2298 ( .A(n5370), .Y(n5405) );
AOI32X1TS U2299 ( .A0(n4044), .A1(n4043), .A2(n4042), .B0(n4041), .B1(n4043),
.Y(n1337) );
AOI211X1TS U2300 ( .A0(n4044), .A1(n4038), .B0(n4037), .C0(n2323), .Y(n4039)
);
AOI211X1TS U2301 ( .A0(n3162), .A1(n3161), .B0(n3160), .C0(n2323), .Y(n3163)
);
OR2X1TS U2302 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n4146), .Y(n2206)
);
BUFX4TS U2303 ( .A(n5413), .Y(n5414) );
NOR2X1TS U2304 ( .A(n2238), .B(n5044), .Y(n4302) );
OR2X1TS U2305 ( .A(n2262), .B(FPMULT_Op_MX[16]), .Y(n2207) );
INVX2TS U2306 ( .A(n2325), .Y(n2327) );
INVX2TS U2307 ( .A(n3208), .Y(n4414) );
CLKBUFX3TS U2308 ( .A(n3923), .Y(n4326) );
AOI21X2TS U2309 ( .A0(n2319), .A1(n5077), .B0(n2685), .Y(n2209) );
OA21XLTS U2310 ( .A0(FPADDSUB_DMP_SFG[2]), .A1(n5083), .B0(n2903), .Y(n2212)
);
OA21XLTS U2311 ( .A0(FPADDSUB_DMP_SFG[21]), .A1(n5075), .B0(n2917), .Y(n2213) );
OR2X1TS U2312 ( .A(n4759), .B(n2445), .Y(n2214) );
OA21XLTS U2313 ( .A0(n2327), .A1(n3858), .B0(n3859), .Y(n2217) );
INVX2TS U2314 ( .A(n2355), .Y(n2357) );
OR2X1TS U2315 ( .A(n4694), .B(n3364), .Y(n2218) );
OR2X1TS U2316 ( .A(n3367), .B(n3005), .Y(n2219) );
OR2X1TS U2317 ( .A(n3367), .B(n3364), .Y(n2220) );
AND3X1TS U2318 ( .A(n2250), .B(FPMULT_FSM_selector_C), .C(n4759), .Y(n2221)
);
INVX2TS U2319 ( .A(n2345), .Y(n2346) );
OR2X1TS U2320 ( .A(n3965), .B(n3133), .Y(n2222) );
OR2X1TS U2321 ( .A(FPADDSUB_shift_value_SHT2_EWR[2]), .B(
FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n2223) );
OR2X1TS U2322 ( .A(n4103), .B(n2699), .Y(n2224) );
OA21XLTS U2323 ( .A0(n5054), .A1(n2297), .B0(n4452), .Y(n2226) );
INVX2TS U2324 ( .A(n2350), .Y(n2351) );
INVX2TS U2325 ( .A(n2338), .Y(n2339) );
AND2X2TS U2326 ( .A(FPMULT_Op_MX[11]), .B(n3856), .Y(n2228) );
OR2X1TS U2327 ( .A(n2236), .B(n3210), .Y(n2229) );
INVX2TS U2328 ( .A(n2371), .Y(n2372) );
INVX2TS U2329 ( .A(n4302), .Y(n2371) );
OR3X1TS U2330 ( .A(FPMULT_FS_Module_state_reg[1]), .B(
FPMULT_FS_Module_state_reg[0]), .C(n3178), .Y(n2231) );
INVX2TS U2331 ( .A(n4509), .Y(n2232) );
INVX2TS U2332 ( .A(n2232), .Y(n2233) );
INVX2TS U2333 ( .A(n5050), .Y(n2234) );
INVX2TS U2334 ( .A(n5046), .Y(n2235) );
INVX2TS U2335 ( .A(n5047), .Y(n2236) );
INVX2TS U2336 ( .A(n4932), .Y(n2237) );
INVX2TS U2337 ( .A(FPSENCOS_cont_iter_out[1]), .Y(n2238) );
INVX2TS U2338 ( .A(n4634), .Y(n2239) );
INVX2TS U2339 ( .A(n2239), .Y(n2240) );
INVX2TS U2340 ( .A(n2221), .Y(n2241) );
INVX2TS U2341 ( .A(n2221), .Y(n2242) );
INVX2TS U2342 ( .A(n2227), .Y(n2243) );
INVX2TS U2343 ( .A(n2227), .Y(n2244) );
INVX2TS U2344 ( .A(n2229), .Y(n2245) );
INVX2TS U2345 ( .A(n2229), .Y(n2246) );
INVX2TS U2346 ( .A(n2224), .Y(n2247) );
INVX2TS U2347 ( .A(n2224), .Y(n2248) );
INVX2TS U2348 ( .A(n2346), .Y(n2249) );
INVX2TS U2349 ( .A(n2249), .Y(n2250) );
INVX2TS U2350 ( .A(n4834), .Y(n2251) );
INVX2TS U2351 ( .A(n4834), .Y(n2252) );
INVX2TS U2352 ( .A(n2332), .Y(n2253) );
INVX2TS U2353 ( .A(n2335), .Y(n2254) );
INVX2TS U2354 ( .A(n2335), .Y(n2255) );
INVX2TS U2355 ( .A(n4587), .Y(n2256) );
INVX2TS U2356 ( .A(n4587), .Y(n2257) );
INVX2TS U2357 ( .A(n4957), .Y(n2258) );
INVX2TS U2358 ( .A(n4957), .Y(n2259) );
INVX2TS U2359 ( .A(FPMULT_Op_MY[12]), .Y(n2260) );
INVX2TS U2360 ( .A(FPMULT_Op_MY[12]), .Y(n2261) );
INVX2TS U2361 ( .A(n5027), .Y(n2262) );
INVX2TS U2362 ( .A(n2262), .Y(n2263) );
INVX2TS U2363 ( .A(n2223), .Y(n2264) );
INVX2TS U2364 ( .A(n2223), .Y(n2265) );
INVX2TS U2365 ( .A(n2216), .Y(n2266) );
INVX2TS U2366 ( .A(n2216), .Y(n2267) );
INVX2TS U2367 ( .A(FPMULT_Op_MY[0]), .Y(n2269) );
INVX2TS U2368 ( .A(FPMULT_Op_MY[0]), .Y(n2270) );
INVX2TS U2369 ( .A(n4956), .Y(n2271) );
INVX2TS U2370 ( .A(n2271), .Y(n2272) );
INVX2TS U2371 ( .A(n2271), .Y(n2273) );
INVX2TS U2372 ( .A(n2231), .Y(n2274) );
INVX2TS U2373 ( .A(n2231), .Y(n2275) );
INVX2TS U2374 ( .A(n4601), .Y(n2276) );
INVX2TS U2375 ( .A(FPMULT_Op_MX[7]), .Y(n2277) );
INVX2TS U2376 ( .A(FPMULT_Op_MX[7]), .Y(n2278) );
INVX2TS U2377 ( .A(FPMULT_Op_MX[9]), .Y(n2279) );
INVX2TS U2378 ( .A(FPMULT_Op_MX[9]), .Y(n2280) );
INVX2TS U2379 ( .A(n2217), .Y(n2281) );
INVX2TS U2380 ( .A(n2217), .Y(n2282) );
INVX2TS U2381 ( .A(n4493), .Y(n2283) );
INVX2TS U2382 ( .A(n4493), .Y(n2284) );
INVX2TS U2383 ( .A(n4592), .Y(n2285) );
INVX2TS U2384 ( .A(n4935), .Y(n2287) );
INVX2TS U2385 ( .A(n4935), .Y(n2288) );
INVX2TS U2386 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .Y(n2289) );
INVX2TS U2387 ( .A(n4955), .Y(n2290) );
INVX2TS U2388 ( .A(n2290), .Y(n2291) );
INVX2TS U2389 ( .A(n2220), .Y(n2292) );
INVX2TS U2390 ( .A(n2220), .Y(n2293) );
INVX2TS U2391 ( .A(n2300), .Y(n3565) );
INVX2TS U2392 ( .A(n4586), .Y(n2294) );
INVX2TS U2393 ( .A(n4838), .Y(n2295) );
INVX2TS U2394 ( .A(n4838), .Y(n2296) );
INVX2TS U2395 ( .A(FPMULT_Op_MX[17]), .Y(n2297) );
INVX2TS U2396 ( .A(FPMULT_Op_MX[17]), .Y(n2298) );
INVX2TS U2397 ( .A(n4439), .Y(n2300) );
INVX2TS U2398 ( .A(n4439), .Y(n2301) );
INVX2TS U2399 ( .A(n2228), .Y(n2302) );
INVX2TS U2400 ( .A(n2228), .Y(n2303) );
INVX2TS U2401 ( .A(n2206), .Y(n2304) );
INVX2TS U2402 ( .A(n2206), .Y(n2305) );
INVX2TS U2403 ( .A(n4928), .Y(n2306) );
INVX2TS U2404 ( .A(n4928), .Y(n2307) );
INVX2TS U2405 ( .A(n4934), .Y(n2308) );
INVX2TS U2406 ( .A(n4934), .Y(n2309) );
INVX2TS U2407 ( .A(n2219), .Y(n2310) );
INVX2TS U2408 ( .A(n2219), .Y(n2311) );
INVX2TS U2409 ( .A(n2392), .Y(n2312) );
INVX2TS U2410 ( .A(n2391), .Y(n2313) );
INVX2TS U2411 ( .A(n3397), .Y(n2314) );
INVX2TS U2412 ( .A(n4956), .Y(n2315) );
INVX2TS U2413 ( .A(n4624), .Y(n2316) );
INVX2TS U2414 ( .A(n4624), .Y(n2317) );
INVX2TS U2415 ( .A(FPMULT_Op_MX[0]), .Y(n2318) );
CLKINVX3TS U2416 ( .A(FPMULT_Op_MX[0]), .Y(n2319) );
INVX2TS U2417 ( .A(n2320), .Y(n2321) );
INVX2TS U2418 ( .A(n2215), .Y(n2322) );
CLKINVX3TS U2419 ( .A(n2215), .Y(n2323) );
CLKINVX3TS U2420 ( .A(n4933), .Y(n2324) );
OAI33X1TS U2421 ( .A0(n2258), .A1(FPMULT_Op_MX[8]), .A2(n2279), .B0(n2269),
.B1(n5116), .B2(n2341), .Y(n3201) );
NAND2X1TS U2422 ( .A(FPMULT_Op_MX[10]), .B(n2341), .Y(n4555) );
INVX2TS U2423 ( .A(n4933), .Y(n2341) );
INVX2TS U2424 ( .A(n4407), .Y(n2325) );
INVX2TS U2425 ( .A(n2325), .Y(n2326) );
CLKINVX3TS U2426 ( .A(n2214), .Y(n2328) );
CLKINVX3TS U2427 ( .A(n2214), .Y(n2329) );
INVX2TS U2428 ( .A(FPMULT_Op_MX[21]), .Y(n2330) );
INVX2TS U2429 ( .A(FPMULT_Op_MX[21]), .Y(n2331) );
INVX2TS U2430 ( .A(n2663), .Y(n2332) );
CLKINVX6TS U2431 ( .A(n2332), .Y(n2333) );
CLKBUFX2TS U2432 ( .A(clk), .Y(n2663) );
CLKINVX6TS U2433 ( .A(n2332), .Y(n2334) );
CLKBUFX2TS U2434 ( .A(clk), .Y(n5465) );
BUFX4TS U2435 ( .A(n2665), .Y(n5388) );
BUFX6TS U2436 ( .A(n2333), .Y(n5366) );
BUFX4TS U2437 ( .A(n2333), .Y(n5399) );
BUFX6TS U2438 ( .A(n2333), .Y(n2669) );
BUFX6TS U2439 ( .A(n5374), .Y(n5423) );
BUFX6TS U2440 ( .A(n5374), .Y(n5422) );
BUFX6TS U2441 ( .A(n5404), .Y(n5416) );
INVX2TS U2442 ( .A(n5442), .Y(n2335) );
CLKINVX6TS U2443 ( .A(n2335), .Y(n2336) );
BUFX4TS U2444 ( .A(n5445), .Y(n5449) );
BUFX4TS U2445 ( .A(n5445), .Y(n5367) );
BUFX6TS U2446 ( .A(n5445), .Y(n5453) );
BUFX6TS U2447 ( .A(n5445), .Y(n5410) );
BUFX6TS U2448 ( .A(n2655), .Y(n5442) );
BUFX6TS U2449 ( .A(n2655), .Y(n5456) );
BUFX6TS U2450 ( .A(n2655), .Y(n5454) );
BUFX6TS U2451 ( .A(n5370), .Y(n5407) );
BUFX6TS U2452 ( .A(n5374), .Y(n5457) );
BUFX6TS U2453 ( .A(n5374), .Y(n5447) );
BUFX6TS U2454 ( .A(n5374), .Y(n5421) );
BUFX6TS U2455 ( .A(n5374), .Y(n5420) );
BUFX6TS U2456 ( .A(n5380), .Y(n5394) );
BUFX4TS U2457 ( .A(n2334), .Y(n5365) );
BUFX6TS U2458 ( .A(n2334), .Y(n5378) );
BUFX6TS U2459 ( .A(n2334), .Y(n2665) );
BUFX4TS U2460 ( .A(n2661), .Y(n5440) );
BUFX4TS U2461 ( .A(n5370), .Y(n5463) );
BUFX6TS U2462 ( .A(n5436), .Y(n5391) );
BUFX6TS U2463 ( .A(n5436), .Y(n5441) );
BUFX6TS U2464 ( .A(n2660), .Y(n5400) );
BUFX6TS U2465 ( .A(n5389), .Y(n5396) );
BUFX6TS U2466 ( .A(n5382), .Y(n5398) );
BUFX6TS U2467 ( .A(n2661), .Y(n5428) );
OAI21X2TS U2468 ( .A0(n2300), .A1(n5192), .B0(n3050), .Y(n3564) );
BUFX6TS U2469 ( .A(n5370), .Y(n5418) );
BUFX6TS U2470 ( .A(n5374), .Y(n5387) );
BUFX6TS U2471 ( .A(n2334), .Y(n5376) );
BUFX6TS U2472 ( .A(n5414), .Y(n5386) );
BUFX6TS U2473 ( .A(n2658), .Y(n2654) );
BUFX4TS U2474 ( .A(n5464), .Y(n5424) );
BUFX4TS U2475 ( .A(n2667), .Y(n2656) );
BUFX6TS U2476 ( .A(n2667), .Y(n5373) );
BUFX4TS U2477 ( .A(n2667), .Y(n5443) );
BUFX4TS U2478 ( .A(n5442), .Y(n5462) );
BUFX6TS U2479 ( .A(n5442), .Y(n5461) );
BUFX3TS U2480 ( .A(n2657), .Y(n2661) );
BUFX4TS U2481 ( .A(n2657), .Y(n5451) );
BUFX4TS U2482 ( .A(n2657), .Y(n2659) );
INVX2TS U2483 ( .A(n5146), .Y(n2337) );
OAI2BB2X1TS U2484 ( .B0(n4524), .B1(n4523), .A0N(n4529), .A1N(n4522), .Y(
mult_x_254_n186) );
OAI2BB2X1TS U2485 ( .B0(n4536), .B1(n4535), .A0N(n4534), .A1N(n4533), .Y(
mult_x_254_n200) );
OAI2BB2X1TS U2486 ( .B0(n4491), .B1(n4490), .A0N(n4489), .A1N(n4488), .Y(
mult_x_219_n210) );
OAI2BB2X1TS U2487 ( .B0(n4484), .B1(n4483), .A0N(n4482), .A1N(n4481), .Y(
mult_x_219_n194) );
NOR2X1TS U2488 ( .A(n2261), .B(n2364), .Y(mult_x_219_n190) );
OAI2BB2X1TS U2489 ( .B0(n4470), .B1(n4467), .A0N(n2703), .A1N(n2704), .Y(
mult_x_219_n170) );
OAI2BB2X1TS U2490 ( .B0(n4611), .B1(n4607), .A0N(n4606), .A1N(n4605), .Y(
DP_OP_454J200_123_2743_n223) );
OAI2BB2X1TS U2491 ( .B0(n4598), .B1(n4597), .A0N(n4596), .A1N(n4595), .Y(
DP_OP_454J200_123_2743_n204) );
OAI2BB2X1TS U2492 ( .B0(n2364), .B1(n4479), .A0N(n4478), .A1N(n4477), .Y(
mult_x_219_n186) );
NOR2XLTS U2493 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .Y(n2447) );
NAND3X2TS U2494 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(n2447),
.C(n2630), .Y(n4671) );
NOR2X2TS U2495 ( .A(n2403), .B(n5078), .Y(n4402) );
AOI32X1TS U2496 ( .A0(FPMULT_Op_MX[15]), .A1(n2261), .A2(n5078), .B0(n4402),
.B1(n2288), .Y(n2808) );
INVX2TS U2497 ( .A(n4624), .Y(n2338) );
INVX2TS U2498 ( .A(n2338), .Y(n2340) );
NOR4X2TS U2499 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .Y(n2448) );
NOR4X2TS U2500 ( .A(FPADDSUB_Raw_mant_NRM_SWR[17]), .B(
FPADDSUB_Raw_mant_NRM_SWR[15]), .C(FPADDSUB_Raw_mant_NRM_SWR[16]), .D(
n3010), .Y(n2981) );
OAI2BB2X1TS U2501 ( .B0(n2232), .B1(n4508), .A0N(n2247), .A1N(n4080), .Y(
mult_x_254_n165) );
NOR2X2TS U2502 ( .A(FPSENCOS_d_ff2_X[29]), .B(n4243), .Y(n4242) );
NOR2X2TS U2503 ( .A(FPSENCOS_d_ff2_Y[29]), .B(n4232), .Y(n4235) );
OAI33X1TS U2504 ( .A0(n2287), .A1(FPMULT_Op_MX[18]), .A2(n4927), .B0(n2260),
.B1(n5054), .B2(n2398), .Y(n4393) );
AOI222X1TS U2505 ( .A0(n2249), .A1(n5211), .B0(n2389), .B1(n2446), .C0(n5018), .C1(n2329), .Y(n1621) );
INVX2TS U2506 ( .A(n3392), .Y(n2389) );
NOR3BX2TS U2507 ( .AN(n4504), .B(mult_x_254_n169), .C(n4506), .Y(
mult_x_254_n119) );
NOR2X2TS U2508 ( .A(n4445), .B(n4446), .Y(n4444) );
NOR2X2TS U2509 ( .A(n5177), .B(n3975), .Y(n4738) );
AOI21X2TS U2510 ( .A0(FPADDSUB_DMP_SFG[6]), .A1(n5171), .B0(n3104), .Y(n3086) );
OAI211XLTS U2511 ( .A0(FPMULT_Sgf_normalized_result[9]), .A1(n3987), .B0(
n4734), .C0(n3985), .Y(n3361) );
NOR2X2TS U2512 ( .A(n5173), .B(n4727), .Y(n3987) );
OAI211XLTS U2513 ( .A0(FPMULT_Sgf_normalized_result[17]), .A1(n3983), .B0(
n4734), .C0(n3981), .Y(n3156) );
NOR2X2TS U2514 ( .A(n5175), .B(n4733), .Y(n3983) );
OAI211XLTS U2515 ( .A0(FPMULT_Sgf_normalized_result[13]), .A1(n4061), .B0(
n4734), .C0(n3977), .Y(n3360) );
NOR2X2TS U2516 ( .A(n5174), .B(n4730), .Y(n4061) );
NOR2X2TS U2517 ( .A(n3959), .B(n3958), .Y(n3957) );
NOR2X2TS U2518 ( .A(n4254), .B(n4253), .Y(n4753) );
NOR2X2TS U2519 ( .A(n3951), .B(n3948), .Y(n4750) );
INVX2TS U2520 ( .A(n2212), .Y(n2342) );
INVX2TS U2521 ( .A(n2213), .Y(n2343) );
OAI33X1TS U2522 ( .A0(n2287), .A1(FPMULT_Op_MX[16]), .A2(n2297), .B0(n2261),
.B1(n5080), .B2(n2306), .Y(n2824) );
NAND2X2TS U2523 ( .A(n4128), .B(n2372), .Y(n4680) );
NOR2X2TS U2524 ( .A(FPADDSUB_Raw_mant_NRM_SWR[7]), .B(
FPADDSUB_Raw_mant_NRM_SWR[6]), .Y(n3017) );
NOR2X4TS U2525 ( .A(FPSENCOS_cont_iter_out[2]), .B(n4353), .Y(n4307) );
CLKINVX3TS U2526 ( .A(n4238), .Y(n4353) );
NOR2X2TS U2527 ( .A(FPMULT_FS_Module_state_reg[0]), .B(n2632), .Y(n2875) );
AOI21X2TS U2528 ( .A0(n2258), .A1(n3199), .B0(mult_x_254_n211), .Y(n2735) );
NOR2X2TS U2529 ( .A(FPSENCOS_cont_iter_out[0]), .B(FPSENCOS_cont_iter_out[3]), .Y(n4306) );
NOR2X2TS U2530 ( .A(n4046), .B(n3368), .Y(n4323) );
CLKBUFX3TS U2531 ( .A(n4087), .Y(n3368) );
NOR2X2TS U2532 ( .A(operation[1]), .B(operation[2]), .Y(n3813) );
AOI21X2TS U2533 ( .A0(FPADDSUB_Data_array_SWR[21]), .A1(n2264), .B0(n3912),
.Y(n4792) );
OAI21X1TS U2534 ( .A0(n4146), .A1(n4971), .B0(n4145), .Y(n3912) );
AOI21X2TS U2535 ( .A0(FPADDSUB_Data_array_SWR[19]), .A1(n2265), .B0(n4147),
.Y(n4802) );
OAI21X1TS U2536 ( .A0(n4146), .A1(n5112), .B0(n4145), .Y(n4147) );
AOI21X2TS U2537 ( .A0(FPADDSUB_Data_array_SWR[20]), .A1(n2265), .B0(n3915),
.Y(n4784) );
OAI21X1TS U2538 ( .A0(n4146), .A1(n4975), .B0(n4145), .Y(n3915) );
NOR2X2TS U2539 ( .A(FPSENCOS_cont_iter_out[1]), .B(n4353), .Y(n4305) );
INVX2TS U2540 ( .A(n2211), .Y(n2344) );
OAI22X2TS U2541 ( .A0(n2337), .A1(n4968), .B0(n2431), .B1(n4042), .Y(n3285)
);
AOI21X2TS U2542 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[11]), .A1(n5133), .B0(n3254),
.Y(n4042) );
OAI21X2TS U2543 ( .A0(n4929), .A1(n2312), .B0(n3566), .Y(n3621) );
INVX2TS U2544 ( .A(n4290), .Y(n3972) );
CLKINVX3TS U2545 ( .A(n4290), .Y(n4677) );
NOR4X2TS U2546 ( .A(n2699), .B(mult_x_254_n168), .C(n4503), .D(n4926), .Y(
mult_x_254_n106) );
NOR2X2TS U2547 ( .A(n2269), .B(n4511), .Y(mult_x_254_n168) );
CLKINVX3TS U2548 ( .A(n4091), .Y(n3572) );
INVX2TS U2549 ( .A(n3397), .Y(n2345) );
AOI21X1TS U2550 ( .A0(n3178), .A1(n3893), .B0(n4936), .Y(n3397) );
INVX2TS U2551 ( .A(n2208), .Y(n2347) );
AOI211X2TS U2552 ( .A0(n2287), .A1(n4452), .B0(n4454), .C0(mult_x_219_n177),
.Y(mult_x_219_n129) );
OAI21X2TS U2553 ( .A0(n2297), .A1(n5054), .B0(n2398), .Y(mult_x_219_n177) );
INVX2TS U2554 ( .A(n2225), .Y(n2348) );
INVX2TS U2555 ( .A(n2225), .Y(n2349) );
CLKBUFX3TS U2556 ( .A(n5311), .Y(n5326) );
BUFX4TS U2557 ( .A(n2658), .Y(n5437) );
BUFX4TS U2558 ( .A(n2658), .Y(n2662) );
BUFX4TS U2559 ( .A(n2333), .Y(n5436) );
BUFX4TS U2560 ( .A(n2661), .Y(n5464) );
BUFX4TS U2561 ( .A(clk), .Y(n5372) );
OAI21X2TS U2562 ( .A0(n2316), .A1(n2693), .B0(n2357), .Y(
DP_OP_454J200_123_2743_n215) );
BUFX4TS U2563 ( .A(clk), .Y(n2668) );
AOI21X2TS U2564 ( .A0(n2264), .A1(FPADDSUB_Data_array_SWR[25]), .B0(n4144),
.Y(n4894) );
AOI21X2TS U2565 ( .A0(n2264), .A1(FPADDSUB_Data_array_SWR[23]), .B0(n4144),
.Y(n4874) );
AOI21X2TS U2566 ( .A0(n2264), .A1(FPADDSUB_Data_array_SWR[22]), .B0(n4144),
.Y(n4796) );
INVX2TS U2567 ( .A(n4592), .Y(n2350) );
CLKINVX3TS U2568 ( .A(n2350), .Y(n2352) );
NOR2X2TS U2569 ( .A(n2260), .B(n2283), .Y(mult_x_219_n162) );
NOR2X2TS U2570 ( .A(n2399), .B(FPMULT_Op_MX[2]), .Y(n4537) );
CMPR32X4TS U2571 ( .A(FPMULT_Op_MY[1]), .B(FPMULT_Op_MY[13]), .C(n2670),
.CO(n2682), .S(n4584) );
BUFX3TS U2572 ( .A(n2412), .Y(n5294) );
INVX2TS U2573 ( .A(n2207), .Y(n2354) );
CLKINVX3TS U2574 ( .A(n5358), .Y(n3495) );
CLKINVX3TS U2575 ( .A(n5358), .Y(n4688) );
CLKINVX3TS U2576 ( .A(n5358), .Y(n4280) );
NOR3BX2TS U2577 ( .AN(n2899), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]),
.C(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .Y(n2901) );
NOR3X2TS U2578 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .Y(n2899) );
BUFX3TS U2579 ( .A(n5371), .Y(n5426) );
BUFX3TS U2580 ( .A(n5371), .Y(n5425) );
INVX2TS U2581 ( .A(n4601), .Y(n2355) );
CLKINVX3TS U2582 ( .A(n2355), .Y(n2356) );
INVX2TS U2583 ( .A(n2218), .Y(n2358) );
INVX2TS U2584 ( .A(n2218), .Y(n2359) );
NAND3X2TS U2585 ( .A(n2199), .B(FPADDSUB_shift_value_SHT2_EWR[3]), .C(
FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n4834) );
CLKBUFX3TS U2586 ( .A(n5331), .Y(n2408) );
BUFX3TS U2587 ( .A(n5319), .Y(n5339) );
BUFX3TS U2588 ( .A(n5318), .Y(n2406) );
AOI211XLTS U2589 ( .A0(n2265), .A1(FPADDSUB_Data_array_SWR[16]), .B0(n4808),
.C0(n4023), .Y(n4821) );
AOI211XLTS U2590 ( .A0(n2265), .A1(FPADDSUB_Data_array_SWR[17]), .B0(n4808),
.C0(n4036), .Y(n4778) );
CLKBUFX3TS U2591 ( .A(n2701), .Y(n2410) );
BUFX4TS U2592 ( .A(n2667), .Y(n5402) );
BUFX6TS U2593 ( .A(n5381), .Y(n5385) );
BUFX4TS U2594 ( .A(n2656), .Y(n5381) );
BUFX4TS U2595 ( .A(n5374), .Y(n5383) );
INVX2TS U2596 ( .A(n2226), .Y(n2363) );
INVX2TS U2597 ( .A(n2226), .Y(n2364) );
INVX2TS U2598 ( .A(n4926), .Y(n2365) );
INVX2TS U2599 ( .A(n2365), .Y(n2366) );
INVX2TS U2600 ( .A(n2365), .Y(n2367) );
INVX2TS U2601 ( .A(n5049), .Y(n2368) );
AOI21X2TS U2602 ( .A0(n4187), .A1(n5044), .B0(n4186), .Y(n4338) );
NOR2X4TS U2603 ( .A(FPSENCOS_cont_iter_out[3]), .B(FPSENCOS_cont_iter_out[2]), .Y(n4187) );
NAND2X2TS U2604 ( .A(FPSENCOS_cont_iter_out[3]), .B(
FPSENCOS_cont_iter_out[2]), .Y(n4292) );
INVX2TS U2605 ( .A(n2222), .Y(n2369) );
INVX2TS U2606 ( .A(n2222), .Y(n2370) );
AOI21X4TS U2607 ( .A0(FPMULT_Op_MX[8]), .A1(n2308), .B0(n4515), .Y(n3203) );
NOR2X2TS U2608 ( .A(n2308), .B(FPMULT_Op_MX[8]), .Y(n4515) );
AOI21X2TS U2609 ( .A0(n3565), .A1(n5086), .B0(n3278), .Y(n3338) );
OAI32X1TS U2610 ( .A0(n2260), .A1(n2402), .A2(n5048), .B0(n2287), .B1(
mult_x_219_n163), .Y(n3192) );
NOR3BX2TS U2611 ( .AN(n4449), .B(n4451), .C(mult_x_219_n163), .Y(
mult_x_219_n119) );
OAI21X2TS U2612 ( .A0(n4927), .A1(n5048), .B0(n2402), .Y(mult_x_219_n163) );
ADDFX2TS U2613 ( .A(FPMULT_Op_MY[3]), .B(n2235), .CI(n2681), .CO(n2671), .S(
n4578) );
BUFX6TS U2614 ( .A(n2657), .Y(n5368) );
BUFX6TS U2615 ( .A(n5364), .Y(n5460) );
BUFX6TS U2616 ( .A(n2668), .Y(n5364) );
BUFX6TS U2617 ( .A(n5465), .Y(n5419) );
BUFX4TS U2618 ( .A(n5371), .Y(n2373) );
BUFX4TS U2619 ( .A(n5371), .Y(n5432) );
BUFX6TS U2620 ( .A(n5371), .Y(n5434) );
BUFX6TS U2621 ( .A(n5371), .Y(n5438) );
BUFX6TS U2622 ( .A(n5371), .Y(n5433) );
BUFX6TS U2623 ( .A(clk), .Y(n5455) );
BUFX6TS U2624 ( .A(n2661), .Y(n5430) );
BUFX6TS U2625 ( .A(n2658), .Y(n5369) );
BUFX6TS U2626 ( .A(n5442), .Y(n5401) );
BUFX4TS U2627 ( .A(n2655), .Y(n5412) );
BUFX3TS U2628 ( .A(n5403), .Y(n2374) );
BUFX6TS U2629 ( .A(n5370), .Y(n5403) );
BUFX6TS U2630 ( .A(n5436), .Y(n5459) );
BUFX4TS U2631 ( .A(n5371), .Y(n5362) );
BUFX6TS U2632 ( .A(n2656), .Y(n5452) );
BUFX4TS U2633 ( .A(n2667), .Y(n5363) );
BUFX6TS U2634 ( .A(n5449), .Y(n5411) );
BUFX6TS U2635 ( .A(n5370), .Y(n5409) );
BUFX3TS U2636 ( .A(clk), .Y(n5445) );
BUFX6TS U2637 ( .A(n5393), .Y(n5395) );
BUFX4TS U2638 ( .A(n5371), .Y(n5393) );
BUFX6TS U2639 ( .A(n2661), .Y(n5390) );
BUFX4TS U2640 ( .A(n2657), .Y(n5392) );
BUFX4TS U2641 ( .A(n5405), .Y(n5415) );
BUFX4TS U2642 ( .A(n2668), .Y(n5435) );
BUFX6TS U2643 ( .A(n2334), .Y(n5458) );
BUFX6TS U2644 ( .A(n2333), .Y(n2664) );
BUFX4TS U2645 ( .A(n2334), .Y(n5448) );
BUFX4TS U2646 ( .A(n2655), .Y(n5361) );
BUFX4TS U2647 ( .A(n2668), .Y(n5408) );
BUFX6TS U2648 ( .A(n5370), .Y(n5406) );
BUFX6TS U2649 ( .A(n5370), .Y(n2660) );
BUFX6TS U2650 ( .A(n5370), .Y(n5413) );
BUFX4TS U2651 ( .A(n5366), .Y(n5404) );
BUFX6TS U2652 ( .A(n2661), .Y(n5450) );
BUFX6TS U2653 ( .A(n5440), .Y(n5389) );
CLKINVX6TS U2654 ( .A(n2332), .Y(n2375) );
BUFX6TS U2655 ( .A(n2661), .Y(n5429) );
BUFX6TS U2656 ( .A(n2661), .Y(n5427) );
BUFX4TS U2657 ( .A(n2661), .Y(n5439) );
BUFX6TS U2658 ( .A(n2661), .Y(n5444) );
CLKINVX6TS U2659 ( .A(n2335), .Y(n2376) );
BUFX4TS U2660 ( .A(n2667), .Y(n5375) );
BUFX4TS U2661 ( .A(n5374), .Y(n2666) );
BUFX4TS U2662 ( .A(n2658), .Y(n5377) );
BUFX6TS U2663 ( .A(n2654), .Y(n5397) );
BUFX6TS U2664 ( .A(n2657), .Y(n5384) );
BUFX6TS U2665 ( .A(n5374), .Y(n5379) );
BUFX4TS U2666 ( .A(n5414), .Y(n5380) );
BUFX6TS U2667 ( .A(n2655), .Y(n5382) );
INVX2TS U2668 ( .A(n4951), .Y(n2377) );
INVX2TS U2669 ( .A(n2377), .Y(n2378) );
CLKBUFX3TS U2670 ( .A(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n4290) );
CLKBUFX3TS U2671 ( .A(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n3560) );
OAI21X2TS U2672 ( .A0(n2291), .A1(n5079), .B0(n2308), .Y(mult_x_254_n183) );
INVX2TS U2673 ( .A(n2230), .Y(n2380) );
INVX2TS U2674 ( .A(n4586), .Y(n2381) );
INVX2TS U2675 ( .A(n2381), .Y(n2382) );
INVX2TS U2676 ( .A(n2381), .Y(n2383) );
OAI32X1TS U2677 ( .A0(n2270), .A1(n2315), .A2(n5114), .B0(n2259), .B1(
mult_x_254_n211), .Y(n2418) );
NOR2X1TS U2678 ( .A(n2269), .B(n2260), .Y(n2670) );
NOR2X4TS U2679 ( .A(n2199), .B(n5123), .Y(n4831) );
NAND2X4TS U2680 ( .A(n2199), .B(n5026), .Y(n4820) );
CLKBUFX3TS U2681 ( .A(n3630), .Y(n3632) );
CLKBUFX3TS U2682 ( .A(n3512), .Y(n3630) );
AOI211X4TS U2683 ( .A0(n2437), .A1(n2436), .B0(n2852), .C0(n2323), .Y(n2438)
);
AOI211X4TS U2684 ( .A0(n3318), .A1(n3317), .B0(n3316), .C0(n2323), .Y(n3319)
);
AOI211X4TS U2685 ( .A0(n3301), .A1(n3300), .B0(n3299), .C0(n2323), .Y(n3306)
);
OAI2BB2X1TS U2686 ( .B0(n4543), .B1(n4540), .A0N(n3197), .A1N(n3198), .Y(
mult_x_254_n216) );
OAI2BB2X1TS U2687 ( .B0(n4611), .B1(n4604), .A0N(n4606), .A1N(n4603), .Y(
DP_OP_454J200_123_2743_n219) );
OAI2BB2X1TS U2688 ( .B0(n4521), .B1(n4518), .A0N(n2707), .A1N(n2708), .Y(
mult_x_254_n176) );
OAI2BB2X1TS U2689 ( .B0(n4632), .B1(n4631), .A0N(n4630), .A1N(n4629), .Y(
DP_OP_454J200_123_2743_n240) );
OAI2BB2X1TS U2690 ( .B0(n4598), .B1(n2690), .A0N(n2726), .A1N(n4595), .Y(
DP_OP_454J200_123_2743_n210) );
OAI2BB2X1TS U2691 ( .B0(n4528), .B1(n4524), .A0N(n4529), .A1N(n3200), .Y(
mult_x_254_n194) );
NOR4X1TS U2692 ( .A(Data_2[2]), .B(Data_2[10]), .C(Data_2[12]), .D(
Data_2[14]), .Y(n5254) );
NOR4X1TS U2693 ( .A(Data_2[7]), .B(Data_2[9]), .C(Data_2[11]), .D(Data_2[6]),
.Y(n5253) );
NOR4X1TS U2694 ( .A(Data_2[17]), .B(Data_2[16]), .C(Data_2[8]), .D(n2453),
.Y(n5252) );
CLKBUFX3TS U2695 ( .A(n3687), .Y(n3670) );
CLKBUFX3TS U2696 ( .A(n3510), .Y(n3687) );
OAI33X1TS U2697 ( .A0(FPSENCOS_d_ff1_shift_region_flag_out[1]), .A1(
FPSENCOS_d_ff1_operation_out), .A2(n5210), .B0(n5024), .B1(n4954),
.B2(FPSENCOS_d_ff1_shift_region_flag_out[0]), .Y(n2476) );
OR4X2TS U2698 ( .A(FPADDSUB_Raw_mant_NRM_SWR[21]), .B(
FPADDSUB_Raw_mant_NRM_SWR[20]), .C(FPADDSUB_Raw_mant_NRM_SWR[19]), .D(
n2976), .Y(n2984) );
INVX2TS U2699 ( .A(n2984), .Y(n2384) );
NOR2X2TS U2700 ( .A(n2318), .B(n5043), .Y(n2417) );
OAI211XLTS U2701 ( .A0(FPMULT_Sgf_normalized_result[19]), .A1(n3980), .B0(
n4734), .C0(n3975), .Y(n3377) );
NOR2X2TS U2702 ( .A(n5176), .B(n3981), .Y(n3980) );
OAI211X4TS U2703 ( .A0(FPMULT_Sgf_normalized_result[7]), .A1(n4728), .B0(
n4734), .C0(n4727), .Y(n4729) );
NOR2X2TS U2704 ( .A(n5108), .B(n4724), .Y(n4728) );
OAI211XLTS U2705 ( .A0(FPMULT_Sgf_normalized_result[15]), .A1(n4735), .B0(
n4734), .C0(n4733), .Y(n4736) );
NOR2X2TS U2706 ( .A(n5106), .B(n3977), .Y(n4735) );
OAI211X4TS U2707 ( .A0(FPMULT_Sgf_normalized_result[11]), .A1(n4731), .B0(
n4734), .C0(n4730), .Y(n4732) );
NOR2X2TS U2708 ( .A(n5107), .B(n3985), .Y(n4731) );
NOR2X2TS U2709 ( .A(n4613), .B(n3835), .Y(n3841) );
NOR2X2TS U2710 ( .A(FPSENCOS_d_ff2_X[27]), .B(n4246), .Y(n4245) );
NOR2X2TS U2711 ( .A(FPSENCOS_d_ff2_Y[27]), .B(n4183), .Y(n4233) );
NOR2X2TS U2712 ( .A(n4752), .B(n3962), .Y(n3961) );
NOR2X2TS U2713 ( .A(n3839), .B(n3838), .Y(n3860) );
AOI21X2TS U2714 ( .A0(n2264), .A1(FPADDSUB_Data_array_SWR[24]), .B0(n4144),
.Y(n4899) );
NAND2X1TS U2715 ( .A(n2297), .B(n5054), .Y(n4452) );
NOR2X2TS U2716 ( .A(FPADDSUB_Raw_mant_NRM_SWR[7]), .B(n2998), .Y(n3020) );
OAI2BB2X2TS U2717 ( .B0(n5082), .B1(FPADDSUB_DMP_SFG[1]), .A0N(
FPADDSUB_DMP_SFG[1]), .A1N(n5082), .Y(n3263) );
NOR2X2TS U2718 ( .A(FPMULT_Op_MX[13]), .B(FPMULT_Op_MX[14]), .Y(n4102) );
CLKINVX3TS U2719 ( .A(n4905), .Y(n4921) );
CLKBUFX3TS U2720 ( .A(n4904), .Y(n4905) );
AOI22X2TS U2721 ( .A0(FPADDSUB_intDY_EWSW[9]), .A1(n4940), .B0(
FPADDSUB_intDY_EWSW[10]), .B1(n5149), .Y(n4001) );
AOI222X4TS U2722 ( .A0(n4212), .A1(n4211), .B0(n4212), .B1(n3437), .C0(n4211), .C1(n3437), .Y(n4328) );
OAI21X2TS U2723 ( .A0(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[20]),
.A1(n4299), .B0(n4298), .Y(n4211) );
OAI21X2TS U2724 ( .A0(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[0]), .A1(
n2610), .B0(n2609), .Y(n3924) );
OAI21X2TS U2725 ( .A0(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[13]),
.A1(n4295), .B0(n4294), .Y(n4203) );
CLKINVX3TS U2726 ( .A(n4091), .Y(n4890) );
CLKINVX3TS U2727 ( .A(n4702), .Y(n4703) );
CLKBUFX3TS U2728 ( .A(n4698), .Y(n4702) );
AOI22X2TS U2729 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[18]), .A1(
FPADDSUB_DMP_SFG[16]), .B0(n5135), .B1(n5008), .Y(n3314) );
AOI22X2TS U2730 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[11]), .A1(
FPADDSUB_DMP_SFG[9]), .B0(n5133), .B1(n5006), .Y(n3255) );
AOI22X2TS U2731 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[10]), .A1(
FPADDSUB_DMP_SFG[8]), .B0(n5132), .B1(n5005), .Y(n3244) );
AOI22X2TS U2732 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[14]), .A1(
FPADDSUB_DMP_SFG[12]), .B0(n5134), .B1(n5007), .Y(n2886) );
AOI22X2TS U2733 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[20]), .A1(
FPADDSUB_DMP_SFG[18]), .B0(n5136), .B1(n5010), .Y(n3122) );
CLKINVX3TS U2734 ( .A(n4238), .Y(n4313) );
CLKBUFX3TS U2735 ( .A(n4257), .Y(n4238) );
OAI21X2TS U2736 ( .A0(n5027), .A1(n5080), .B0(n2306), .Y(mult_x_219_n191) );
NOR2X2TS U2737 ( .A(n5042), .B(n4926), .Y(n4384) );
CLKBUFX3TS U2738 ( .A(n3936), .Y(n3953) );
CLKBUFX3TS U2739 ( .A(FPADDSUB_Shift_reg_FLAGS_7_5), .Y(n4056) );
CLKBUFX3TS U2740 ( .A(n4326), .Y(n4320) );
AOI211X1TS U2741 ( .A0(n3304), .A1(n3303), .B0(n3302), .C0(n3321), .Y(n3305)
);
AOI2BB2X2TS U2742 ( .B0(FPADDSUB_DmP_mant_SFG_SWR[7]), .B1(
FPADDSUB_DMP_SFG[5]), .A0N(FPADDSUB_DMP_SFG[5]), .A1N(
FPADDSUB_DmP_mant_SFG_SWR[7]), .Y(n3303) );
AOI211X1TS U2743 ( .A0(n3106), .A1(n3105), .B0(n3104), .C0(n3321), .Y(n3107)
);
AOI2BB2X2TS U2744 ( .B0(FPADDSUB_DmP_mant_SFG_SWR[8]), .B1(
FPADDSUB_DMP_SFG[6]), .A0N(FPADDSUB_DMP_SFG[6]), .A1N(
FPADDSUB_DmP_mant_SFG_SWR[8]), .Y(n3105) );
AOI211X1TS U2745 ( .A0(n3117), .A1(n3116), .B0(n3115), .C0(n3321), .Y(n3118)
);
AOI2BB2X2TS U2746 ( .B0(FPADDSUB_DmP_mant_SFG_SWR[16]), .B1(
FPADDSUB_DMP_SFG[14]), .A0N(FPADDSUB_DMP_SFG[14]), .A1N(
FPADDSUB_DmP_mant_SFG_SWR[16]), .Y(n3116) );
CLKBUFX2TS U2747 ( .A(n4412), .Y(n2385) );
XNOR2X2TS U2748 ( .A(FPADDSUB_intDY_EWSW[31]), .B(FPADDSUB_intAS), .Y(n4016)
);
NOR2X2TS U2749 ( .A(n2198), .B(FPMULT_Op_MX[4]), .Y(n4530) );
NOR2X2TS U2750 ( .A(n5081), .B(n4145), .Y(n4808) );
NAND2X2TS U2751 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_bit_shift_SHT2), .Y(n4145) );
NAND2X4TS U2752 ( .A(n4674), .B(n4677), .Y(n4693) );
CLKBUFX3TS U2753 ( .A(n5196), .Y(n4674) );
INVX2TS U2754 ( .A(n4689), .Y(n2386) );
AOI222X1TS U2755 ( .A0(n4123), .A1(FPSENCOS_d_ff2_Z[12]), .B0(n3482), .B1(
FPSENCOS_d_ff_Zn[12]), .C0(n3480), .C1(FPSENCOS_d_ff1_Z[12]), .Y(n3484) );
AOI222X1TS U2756 ( .A0(n2386), .A1(FPSENCOS_d_ff2_Z[16]), .B0(n3482), .B1(
FPSENCOS_d_ff_Zn[16]), .C0(n3480), .C1(FPSENCOS_d_ff1_Z[16]), .Y(n3475) );
AOI222X4TS U2757 ( .A0(n4691), .A1(FPSENCOS_d_ff2_Z[17]), .B0(n3482), .B1(
FPSENCOS_d_ff_Zn[17]), .C0(n3477), .C1(FPSENCOS_d_ff1_Z[17]), .Y(n3471) );
AOI222X1TS U2758 ( .A0(n4311), .A1(FPSENCOS_d_ff2_Z[20]), .B0(n3482), .B1(
FPSENCOS_d_ff_Zn[20]), .C0(n3469), .C1(FPSENCOS_d_ff1_Z[20]), .Y(n3470) );
AOI222X4TS U2759 ( .A0(n4375), .A1(FPSENCOS_d_ff2_Z[19]), .B0(n3482), .B1(
FPSENCOS_d_ff_Zn[19]), .C0(n3477), .C1(FPSENCOS_d_ff1_Z[19]), .Y(n3468) );
AOI222X1TS U2760 ( .A0(n2386), .A1(FPSENCOS_d_ff2_Z[18]), .B0(n3482), .B1(
FPSENCOS_d_ff_Zn[18]), .C0(n3480), .C1(FPSENCOS_d_ff1_Z[18]), .Y(n3467) );
AOI222X1TS U2761 ( .A0(n4123), .A1(FPSENCOS_d_ff2_Z[15]), .B0(n3482), .B1(
FPSENCOS_d_ff_Zn[15]), .C0(n3477), .C1(FPSENCOS_d_ff1_Z[15]), .Y(n3466) );
AOI222X1TS U2762 ( .A0(n4375), .A1(FPSENCOS_d_ff2_Z[22]), .B0(n3464), .B1(
FPSENCOS_d_ff_Zn[22]), .C0(n3469), .C1(FPSENCOS_d_ff1_Z[22]), .Y(n3465) );
AOI222X1TS U2763 ( .A0(n4311), .A1(FPSENCOS_d_ff2_Z[21]), .B0(n3464), .B1(
FPSENCOS_d_ff_Zn[21]), .C0(n3469), .C1(FPSENCOS_d_ff1_Z[21]), .Y(n3455) );
AOI222X4TS U2764 ( .A0(n4691), .A1(FPSENCOS_d_ff2_Z[31]), .B0(n4279), .B1(
FPSENCOS_d_ff_Zn[31]), .C0(n3477), .C1(FPSENCOS_d_ff1_Z[31]), .Y(n3027) );
BUFX3TS U2765 ( .A(n2409), .Y(n2404) );
CLKBUFX3TS U2766 ( .A(n3817), .Y(n4705) );
CLKBUFX3TS U2767 ( .A(n4174), .Y(n4316) );
CLKBUFX3TS U2768 ( .A(n4700), .Y(n2634) );
CLKBUFX3TS U2769 ( .A(n2473), .Y(n4700) );
CLKBUFX3TS U2770 ( .A(n4711), .Y(n4335) );
NOR4BX2TS U2771 ( .AN(n2630), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]),
.C(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .D(n5020), .Y(n3991) );
NOR2BX2TS U2772 ( .AN(n2448), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]),
.Y(n2630) );
NOR2X2TS U2773 ( .A(n4759), .B(n3133), .Y(n3141) );
AOI22X2TS U2774 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[5]), .A1(n5127), .B0(
FPADDSUB_DMP_SFG[3]), .B1(n4977), .Y(n3162) );
AOI22X2TS U2775 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[13]), .A1(n5128), .B0(
FPADDSUB_DMP_SFG[11]), .B1(n4972), .Y(n3288) );
AOI22X2TS U2776 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[24]), .A1(n5126), .B0(
FPADDSUB_DMP_SFG[22]), .B1(n4973), .Y(n2919) );
AOI22X2TS U2777 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[9]), .A1(n5131), .B0(
FPADDSUB_DMP_SFG[7]), .B1(n4980), .Y(n3089) );
AOI22X2TS U2778 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[19]), .A1(n5143), .B0(
FPADDSUB_DMP_SFG[17]), .B1(n5009), .Y(n2466) );
AOI22X2TS U2779 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[12]), .A1(n5146), .B0(n2337),
.B1(n4968), .Y(n4044) );
OAI21X2TS U2780 ( .A0(n2277), .A1(n5116), .B0(n2341), .Y(mult_x_254_n169) );
AOI21X4TS U2781 ( .A0(n2269), .A1(n2260), .B0(n2670), .Y(n4587) );
INVX2TS U2782 ( .A(n3909), .Y(n2387) );
NOR2X4TS U2783 ( .A(n3005), .B(n4694), .Y(n3611) );
OR2X1TS U2784 ( .A(FPMULT_FSM_selector_C), .B(n2249), .Y(n3392) );
INVX2TS U2785 ( .A(n3392), .Y(n2388) );
INVX2TS U2786 ( .A(n4407), .Y(n2390) );
NOR2X4TS U2787 ( .A(n4636), .B(n2239), .Y(n3758) );
NOR2X2TS U2788 ( .A(n2269), .B(n4526), .Y(mult_x_254_n196) );
INVX2TS U2789 ( .A(n4526), .Y(n4529) );
OAI21X2TS U2790 ( .A0(n5079), .A1(n2291), .B0(n4101), .Y(n4526) );
OR2X1TS U2791 ( .A(FPADDSUB_ADD_OVRFLW_NRM), .B(n3972), .Y(n3619) );
INVX2TS U2792 ( .A(n3619), .Y(n2391) );
INVX2TS U2793 ( .A(n3619), .Y(n2392) );
AOI21X2TS U2794 ( .A0(n2392), .A1(n5086), .B0(n3004), .Y(n3055) );
AOI21X2TS U2795 ( .A0(n2391), .A1(n5056), .B0(n3006), .Y(n3233) );
AOI21X2TS U2796 ( .A0(n2392), .A1(n5180), .B0(n3223), .Y(n3308) );
CLKBUFX2TS U2797 ( .A(n3391), .Y(n2393) );
INVX2TS U2798 ( .A(n4040), .Y(n2394) );
NOR2X4TS U2799 ( .A(rst), .B(n4128), .Y(n2701) );
NOR2X4TS U2800 ( .A(FPMULT_Op_MX[12]), .B(n4962), .Y(n3821) );
CLKBUFX2TS U2801 ( .A(n4835), .Y(n2395) );
CLKBUFX3TS U2802 ( .A(n4884), .Y(n2396) );
CLKBUFX2TS U2803 ( .A(n4884), .Y(n2397) );
NOR3X2TS U2804 ( .A(n3382), .B(n3379), .C(n3378), .Y(n4777) );
AOI31X4TS U2805 ( .A0(n3382), .A1(n3381), .A2(n3380), .B0(n5250), .Y(n4776)
);
NOR3X4TS U2806 ( .A(n5052), .B(n4936), .C(n2632), .Y(n4744) );
NAND2X2TS U2807 ( .A(FPMULT_FS_Module_state_reg[3]), .B(n5205), .Y(n2632) );
CLKBUFX3TS U2808 ( .A(FPMULT_Op_MX[19]), .Y(n2398) );
AOI22X4TS U2809 ( .A0(FPMULT_Op_MX[19]), .A1(FPMULT_Op_MX[20]), .B0(n5048),
.B1(n4927), .Y(n4406) );
NAND2X4TS U2810 ( .A(FPADDSUB_left_right_SHT2), .B(n2199), .Y(n4898) );
AOI211X1TS U2811 ( .A0(n2320), .A1(n4897), .B0(n4824), .C0(n4775), .Y(n4924)
);
AOI211X1TS U2812 ( .A0(n2320), .A1(n4813), .B0(n4824), .C0(n4812), .Y(n4914)
);
AOI221X1TS U2813 ( .A0(n2320), .A1(n4829), .B0(n2321), .B1(n4830), .C0(n4831), .Y(n4909) );
AOI221X4TS U2814 ( .A0(n2320), .A1(n4830), .B0(n2321), .B1(n4829), .C0(n4831), .Y(n4908) );
BUFX3TS U2815 ( .A(FPMULT_Op_MX[1]), .Y(n2399) );
CLKBUFX3TS U2816 ( .A(FPMULT_Op_MX[1]), .Y(n2400) );
CLKBUFX3TS U2817 ( .A(FPMULT_Op_MX[21]), .Y(n2401) );
CLKBUFX3TS U2818 ( .A(FPMULT_Op_MX[21]), .Y(n2402) );
CLKBUFX3TS U2819 ( .A(FPMULT_Op_MX[15]), .Y(n2403) );
OAI21XLTS U2820 ( .A0(FPADDSUB_intDX_EWSW[3]), .A1(n5193), .B0(
FPADDSUB_intDX_EWSW[2]), .Y(n2930) );
AOI31XLTS U2821 ( .A0(n4003), .A1(n2932), .A2(n3995), .B0(n2931), .Y(n2933)
);
OAI211XLTS U2822 ( .A0(FPADDSUB_intDY_EWSW[23]), .A1(n4950), .B0(n2955),
.C0(n2954), .Y(n2956) );
NOR2XLTS U2823 ( .A(FPADDSUB_DmP_mant_SFG_SWR[15]), .B(n5172), .Y(n2433) );
INVX2TS U2824 ( .A(DP_OP_454J200_123_2743_n58), .Y(n3696) );
OAI21XLTS U2825 ( .A0(FPMULT_FSM_selector_B[0]), .A1(n2642), .B0(n2645), .Y(
n2643) );
AOI31XLTS U2826 ( .A0(n4662), .A1(n4661), .A2(n4660), .B0(n4667), .Y(n4665)
);
NOR2XLTS U2827 ( .A(FPADDSUB_DMP_SFG[7]), .B(n4980), .Y(n2430) );
INVX2TS U2828 ( .A(mult_x_219_n128), .Y(n3583) );
INVX2TS U2829 ( .A(mult_x_219_n101), .Y(n3642) );
AOI31XLTS U2830 ( .A0(n3018), .A1(n3017), .A2(n3016), .B0(n3015), .Y(n3019)
);
INVX2TS U2831 ( .A(mult_x_219_n133), .Y(n3072) );
OR2X1TS U2832 ( .A(n4444), .B(n2815), .Y(n3828) );
INVX2TS U2833 ( .A(mult_x_254_n122), .Y(n2765) );
INVX2TS U2834 ( .A(mult_x_219_n32), .Y(n4499) );
OAI21XLTS U2835 ( .A0(n2853), .A1(n2851), .B0(n2917), .Y(n2856) );
OAI211XLTS U2836 ( .A0(n2997), .A1(n5021), .B0(n2988), .C0(n2978), .Y(n2979)
);
OAI211XLTS U2837 ( .A0(FPMULT_Sgf_normalized_result[5]), .A1(n4725), .B0(
n4734), .C0(n4724), .Y(n4726) );
OAI21XLTS U2838 ( .A0(FPADDSUB_DmP_EXP_EWSW[23]), .A1(n4982), .B0(n4222),
.Y(n4224) );
NOR2XLTS U2839 ( .A(n2239), .B(n2257), .Y(n2772) );
OAI21XLTS U2840 ( .A0(n2742), .A1(n2738), .B0(n2739), .Y(n2737) );
OAI211XLTS U2841 ( .A0(n2464), .A1(n2466), .B0(n4040), .C0(n2463), .Y(n2470)
);
NOR2XLTS U2842 ( .A(n4883), .B(n4860), .Y(n4861) );
AOI31XLTS U2843 ( .A0(n2858), .A1(n4048), .A2(n5212), .B0(n4049), .Y(n2449)
);
OAI21XLTS U2844 ( .A0(n4693), .A1(n2321), .B0(n2313), .Y(n2078) );
OAI211XLTS U2845 ( .A0(n5104), .A1(n2241), .B0(n3098), .C0(n3097), .Y(n1505)
);
OAI211XLTS U2846 ( .A0(n3419), .A1(n5238), .B0(n3363), .C0(n3362), .Y(n1841)
);
OAI211XLTS U2847 ( .A0(n3616), .A1(n3238), .B0(n3237), .C0(n3236), .Y(n1795)
);
OAI21XLTS U2848 ( .A0(n2896), .A1(n4671), .B0(n4353), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]) );
AOI31XLTS U2849 ( .A0(n3061), .A1(n4739), .A2(n4742), .B0(n3060), .Y(n1598)
);
OAI21XLTS U2850 ( .A0(n3508), .A1(n3947), .B0(n3507), .Y(n1565) );
OAI21XLTS U2851 ( .A0(n3454), .A1(n3965), .B0(n3453), .Y(n1564) );
OAI211XLTS U2852 ( .A0(n3570), .A1(n3625), .B0(n3569), .C0(n3568), .Y(n1789)
);
OAI21XLTS U2853 ( .A0(n5072), .A1(n3574), .B0(n3550), .Y(n1245) );
OAI21XLTS U2854 ( .A0(n5113), .A1(n3543), .B0(n3542), .Y(n1310) );
OAI21XLTS U2855 ( .A0(n4979), .A1(n3559), .B0(n3558), .Y(n1459) );
OAI21XLTS U2856 ( .A0(n4942), .A1(n3543), .B0(n3427), .Y(n1395) );
OAI211XLTS U2857 ( .A0(n3372), .A1(n5150), .B0(n2878), .C0(n2877), .Y(n1940)
);
OAI21XLTS U2858 ( .A0(n4312), .A1(n4964), .B0(n2910), .Y(n1345) );
OAI211XLTS U2859 ( .A0(n3346), .A1(n5248), .B0(n3240), .C0(n3239), .Y(n1817)
);
OAI21XLTS U2860 ( .A0(n3298), .A1(n2313), .B0(n3297), .Y(n2077) );
OAI211XLTS U2861 ( .A0(n2346), .A1(n5106), .B0(n3348), .C0(n3347), .Y(n1519)
);
OAI211XLTS U2862 ( .A0(n3405), .A1(n3616), .B0(n3401), .C0(n3400), .Y(n1808)
);
OAI211XLTS U2863 ( .A0(n3419), .A1(n5219), .B0(n3147), .C0(n3146), .Y(n1911)
);
OAI211XLTS U2864 ( .A0(n3390), .A1(n4967), .B0(n3167), .C0(n3166), .Y(n1913)
);
OAI211XLTS U2865 ( .A0(n2241), .A1(n5169), .B0(n3177), .C0(n3176), .Y(n1507)
);
OAI21XLTS U2866 ( .A0(n3799), .A1(n5102), .B0(n3775), .Y(op_result[0]) );
OAI21XLTS U2867 ( .A0(n3795), .A1(n5067), .B0(n3794), .Y(op_result[2]) );
OAI21XLTS U2868 ( .A0(n3820), .A1(n5059), .B0(n3791), .Y(op_result[17]) );
OAI21XLTS U2869 ( .A0(n3816), .A1(n3815), .B0(n3814), .Y(operation_ready) );
CLKBUFX2TS U2870 ( .A(n2409), .Y(n5340) );
BUFX3TS U2871 ( .A(n5331), .Y(n5336) );
BUFX3TS U2872 ( .A(n5313), .Y(n5337) );
CLKBUFX3TS U2873 ( .A(n5322), .Y(n5338) );
BUFX3TS U2874 ( .A(n2409), .Y(n5307) );
BUFX3TS U2875 ( .A(n5323), .Y(n5306) );
NAND4BXLTS U2876 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .C(n5181), .D(n2901), .Y(
n4113) );
INVX2TS U2877 ( .A(n4113), .Y(n4128) );
CLKBUFX3TS U2878 ( .A(n2701), .Y(n2412) );
BUFX3TS U2879 ( .A(n2412), .Y(n5293) );
BUFX3TS U2880 ( .A(n5339), .Y(n5312) );
BUFX3TS U2881 ( .A(n2409), .Y(n5318) );
NAND4X2TS U2882 ( .A(n5205), .B(n4936), .C(n5052), .D(n4965), .Y(n2407) );
BUFX3TS U2883 ( .A(n2407), .Y(n5342) );
CLKBUFX3TS U2884 ( .A(n2701), .Y(n2405) );
BUFX3TS U2885 ( .A(n2405), .Y(n5270) );
BUFX3TS U2886 ( .A(n5326), .Y(n5320) );
BUFX3TS U2887 ( .A(n2409), .Y(n5319) );
BUFX3TS U2888 ( .A(n2412), .Y(n5268) );
CLKBUFX3TS U2889 ( .A(n2701), .Y(n2411) );
BUFX3TS U2890 ( .A(n2411), .Y(n5284) );
BUFX3TS U2891 ( .A(n2410), .Y(n5282) );
BUFX3TS U2892 ( .A(n2410), .Y(n5279) );
CLKBUFX2TS U2893 ( .A(n5323), .Y(n5324) );
BUFX3TS U2894 ( .A(n2412), .Y(n5291) );
BUFX3TS U2895 ( .A(n2412), .Y(n5290) );
BUFX3TS U2896 ( .A(n2407), .Y(n5341) );
BUFX3TS U2897 ( .A(n5313), .Y(n5311) );
CLKBUFX2TS U2898 ( .A(n2406), .Y(n5325) );
BUFX3TS U2899 ( .A(n5325), .Y(n5321) );
BUFX3TS U2900 ( .A(n2410), .Y(n5273) );
BUFX3TS U2901 ( .A(n2410), .Y(n5278) );
BUFX3TS U2902 ( .A(n5318), .Y(n5317) );
BUFX3TS U2903 ( .A(n2409), .Y(n5316) );
BUFX3TS U2904 ( .A(n2411), .Y(n5286) );
BUFX3TS U2905 ( .A(n2411), .Y(n5287) );
BUFX3TS U2906 ( .A(n2410), .Y(n5280) );
BUFX3TS U2907 ( .A(n5307), .Y(n5323) );
BUFX3TS U2908 ( .A(n2410), .Y(n5281) );
CLKBUFX2TS U2909 ( .A(n2407), .Y(n2472) );
BUFX3TS U2910 ( .A(n2472), .Y(n5348) );
BUFX3TS U2911 ( .A(n2410), .Y(n5277) );
BUFX3TS U2912 ( .A(n2411), .Y(n5285) );
BUFX3TS U2913 ( .A(n2405), .Y(n5276) );
BUFX3TS U2914 ( .A(n2411), .Y(n5263) );
BUFX3TS U2915 ( .A(n2407), .Y(n5353) );
BUFX3TS U2916 ( .A(n2412), .Y(n5292) );
BUFX3TS U2917 ( .A(n5311), .Y(n5301) );
BUFX3TS U2918 ( .A(n2405), .Y(n5255) );
BUFX3TS U2919 ( .A(n2412), .Y(n5289) );
BUFX3TS U2920 ( .A(n5323), .Y(n5299) );
BUFX3TS U2921 ( .A(n5319), .Y(n5334) );
BUFX3TS U2922 ( .A(n2406), .Y(n5298) );
BUFX3TS U2923 ( .A(n2407), .Y(n5352) );
BUFX3TS U2924 ( .A(n5323), .Y(n5300) );
BUFX3TS U2925 ( .A(n5307), .Y(n5333) );
BUFX3TS U2926 ( .A(n2406), .Y(n5297) );
BUFX3TS U2927 ( .A(n2409), .Y(n5331) );
BUFX3TS U2928 ( .A(n2412), .Y(n5275) );
BUFX3TS U2929 ( .A(n2405), .Y(n5258) );
BUFX3TS U2930 ( .A(n5325), .Y(n5309) );
BUFX3TS U2931 ( .A(n2472), .Y(n5345) );
BUFX3TS U2932 ( .A(n5302), .Y(n5332) );
BUFX3TS U2933 ( .A(n2405), .Y(n5259) );
BUFX3TS U2934 ( .A(n2472), .Y(n5346) );
BUFX3TS U2935 ( .A(n5328), .Y(n5303) );
BUFX3TS U2936 ( .A(n2411), .Y(n5288) );
BUFX3TS U2937 ( .A(n5326), .Y(n5308) );
BUFX3TS U2938 ( .A(n2472), .Y(n5351) );
BUFX3TS U2939 ( .A(n5302), .Y(n5305) );
BUFX3TS U2940 ( .A(n2406), .Y(n5295) );
BUFX3TS U2941 ( .A(n5316), .Y(n5335) );
BUFX3TS U2942 ( .A(n5302), .Y(n5304) );
BUFX3TS U2943 ( .A(n5328), .Y(n5315) );
BUFX3TS U2944 ( .A(n5316), .Y(n5302) );
BUFX3TS U2945 ( .A(n2411), .Y(n5265) );
BUFX3TS U2946 ( .A(n2405), .Y(n5257) );
BUFX3TS U2947 ( .A(n2405), .Y(n5260) );
BUFX3TS U2948 ( .A(n5310), .Y(n5327) );
BUFX3TS U2949 ( .A(n2472), .Y(n5349) );
BUFX3TS U2950 ( .A(n2405), .Y(n5256) );
BUFX3TS U2951 ( .A(n5326), .Y(n5314) );
BUFX3TS U2952 ( .A(n2409), .Y(n5310) );
BUFX3TS U2953 ( .A(n5310), .Y(n5328) );
BUFX3TS U2954 ( .A(n2407), .Y(n5356) );
BUFX3TS U2955 ( .A(n5339), .Y(n5296) );
BUFX3TS U2956 ( .A(n2409), .Y(n5313) );
BUFX3TS U2957 ( .A(n2411), .Y(n5283) );
BUFX3TS U2958 ( .A(n2412), .Y(n5264) );
BUFX3TS U2959 ( .A(n2405), .Y(n5261) );
BUFX3TS U2960 ( .A(n5328), .Y(n5330) );
BUFX3TS U2961 ( .A(n2472), .Y(n5347) );
BUFX3TS U2962 ( .A(n2407), .Y(n5354) );
BUFX3TS U2963 ( .A(n5311), .Y(n5329) );
BUFX3TS U2964 ( .A(n2409), .Y(n5322) );
BUFX3TS U2965 ( .A(n2410), .Y(n5262) );
BUFX3TS U2966 ( .A(n2411), .Y(n5269) );
AOI22X1TS U2967 ( .A0(FPMULT_Op_MY[14]), .A1(n2401), .B0(n2330), .B1(n5034),
.Y(n2454) );
AOI22X1TS U2968 ( .A0(FPMULT_Op_MY[13]), .A1(n2401), .B0(n2331), .B1(n4959),
.Y(n3193) );
INVX2TS U2969 ( .A(n4406), .Y(n4470) );
OAI221X4TS U2970 ( .A0(FPMULT_Op_MX[20]), .A1(n2402), .B0(n5048), .B1(n2330),
.C0(n4470), .Y(n4468) );
INVX2TS U2971 ( .A(n4468), .Y(n2703) );
AO22XLTS U2972 ( .A0(n4406), .A1(n2454), .B0(n3193), .B1(n2703), .Y(
mult_x_219_n174) );
AOI22X1TS U2973 ( .A0(FPMULT_Op_MY[2]), .A1(n2341), .B0(n2280), .B1(n5051),
.Y(n2456) );
INVX2TS U2974 ( .A(n3203), .Y(n4521) );
OAI221X4TS U2975 ( .A0(n2324), .A1(FPMULT_Op_MX[8]), .B0(n2280), .B1(n5116),
.C0(n4521), .Y(n4519) );
INVX2TS U2976 ( .A(n4519), .Y(n2707) );
AOI22X1TS U2977 ( .A0(FPMULT_Op_MY[1]), .A1(n2341), .B0(n2280), .B1(n5043),
.Y(n3202) );
AO22XLTS U2978 ( .A0(n3203), .A1(n2456), .B0(n2707), .B1(n3202), .Y(
mult_x_254_n180) );
NOR2X1TS U2979 ( .A(n2318), .B(n5077), .Y(n2685) );
NAND2X1TS U2980 ( .A(n2357), .B(n2460), .Y(n3205) );
OAI21X4TS U2981 ( .A0(n2356), .A1(n2460), .B0(n3205), .Y(n4598) );
NOR2X1TS U2982 ( .A(n2256), .B(n4598), .Y(DP_OP_454J200_123_2743_n214) );
OAI21XLTS U2983 ( .A0(n2270), .A1(n5029), .B0(n2417), .Y(n2414) );
OAI21X2TS U2984 ( .A0(n5029), .A1(n5114), .B0(n2198), .Y(mult_x_254_n211) );
NOR2X1TS U2985 ( .A(n2318), .B(n5051), .Y(n2416) );
INVX2TS U2986 ( .A(n2416), .Y(n2415) );
AOI21X4TS U2987 ( .A0(FPMULT_Op_MX[2]), .A1(n2399), .B0(n4537), .Y(n3199) );
INVX2TS U2988 ( .A(n3199), .Y(n4543) );
NAND2X1TS U2989 ( .A(n3826), .B(n3825), .Y(n2734) );
INVX2TS U2990 ( .A(n2734), .Y(n3824) );
AOI22X1TS U2991 ( .A0(n2198), .A1(FPMULT_Op_MY[1]), .B0(n5043), .B1(n2272),
.Y(n2424) );
AOI22X1TS U2992 ( .A0(n3199), .A1(n2424), .B0(n2418), .B1(n4543), .Y(n2422)
);
NOR2X1TS U2993 ( .A(n2318), .B(n5041), .Y(n2420) );
AOI22X1TS U2994 ( .A0(FPMULT_Op_MY[2]), .A1(n2318), .B0(n2420), .B1(n2399),
.Y(n2419) );
OAI21X1TS U2995 ( .A0(n2420), .A1(n2399), .B0(n2419), .Y(n2421) );
NOR2X2TS U2996 ( .A(n2422), .B(n2421), .Y(n2742) );
NAND2X1TS U2997 ( .A(n2422), .B(n2421), .Y(n2736) );
OAI31X1TS U2998 ( .A0(n2742), .A1(n3824), .A2(n2735), .B0(n2736), .Y(n2423)
);
AOI31X1TS U2999 ( .A0(n3824), .A1(n2742), .A2(n2735), .B0(n2423), .Y(n2428)
);
NAND2X1TS U3000 ( .A(n2259), .B(n2266), .Y(n2752) );
AOI22X1TS U3001 ( .A0(n2271), .A1(FPMULT_Op_MY[2]), .B0(n5051), .B1(n2272),
.Y(n2748) );
OAI221X4TS U3002 ( .A0(FPMULT_Op_MX[2]), .A1(n2315), .B0(n5114), .B1(n2273),
.C0(n4543), .Y(n4541) );
INVX2TS U3003 ( .A(n4541), .Y(n3197) );
AOI22X1TS U3004 ( .A0(n3199), .A1(n2748), .B0(n2424), .B1(n3197), .Y(n2751)
);
AOI22X1TS U3005 ( .A0(n2237), .A1(n2204), .B0(FPMULT_Op_MY[3]), .B1(n2319),
.Y(n2425) );
INVX2TS U3006 ( .A(n2426), .Y(n2427) );
NAND2X1TS U3007 ( .A(n2427), .B(n2428), .Y(n2743) );
OA21XLTS U3008 ( .A0(n2428), .A1(n2427), .B0(n2743), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N4) );
CLKBUFX3TS U3009 ( .A(FPADDSUB_Shift_reg_FLAGS_7[2]), .Y(n4312) );
NAND2X2TS U3010 ( .A(n4312), .B(FPADDSUB_OP_FLAG_SFG), .Y(n3321) );
INVX2TS U3011 ( .A(n3321), .Y(n4040) );
AOI2BB2X2TS U3012 ( .B0(FPADDSUB_DMP_SFG[20]), .B1(n5074), .A0N(n5074),
.A1N(FPADDSUB_DMP_SFG[20]), .Y(n2436) );
NOR2X1TS U3013 ( .A(FPADDSUB_DmP_mant_SFG_SWR[21]), .B(n5179), .Y(n4862) );
NAND2X1TS U3014 ( .A(FPADDSUB_DMP_SFG[11]), .B(n4972), .Y(n2432) );
NOR2XLTS U3015 ( .A(FPADDSUB_DmP_mant_SFG_SWR[12]), .B(n5146), .Y(n2431) );
NOR2X1TS U3016 ( .A(FPADDSUB_DmP_mant_SFG_SWR[6]), .B(n5117), .Y(n4841) );
NAND2X1TS U3017 ( .A(FPADDSUB_DMP_SFG[3]), .B(n4977), .Y(n2429) );
AOI2BB2X2TS U3018 ( .B0(FPADDSUB_DMP_SFG[2]), .B1(n5083), .A0N(n5083), .A1N(
FPADDSUB_DMP_SFG[2]), .Y(n2906) );
NOR2X1TS U3019 ( .A(FPADDSUB_DmP_mant_SFG_SWR[1]), .B(
FPADDSUB_DmP_mant_SFG_SWR[0]), .Y(n4129) );
NAND2X1TS U3020 ( .A(FPADDSUB_DmP_mant_SFG_SWR[2]), .B(n5122), .Y(n4130) );
AOI2BB2X1TS U3021 ( .B0(n4129), .B1(n4130), .A0N(n5122), .A1N(
FPADDSUB_DmP_mant_SFG_SWR[2]), .Y(n3266) );
INVX2TS U3022 ( .A(n3263), .Y(n3265) );
NAND2X1TS U3023 ( .A(n3266), .B(n3265), .Y(n3264) );
OAI21X1TS U3024 ( .A0(FPADDSUB_DMP_SFG[1]), .A1(n5082), .B0(n3264), .Y(n2904) );
NAND2X1TS U3025 ( .A(n2906), .B(n2904), .Y(n2903) );
AOI22X1TS U3026 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[5]), .A1(n5127), .B0(n2429),
.B1(n2342), .Y(n4842) );
OAI2BB2X1TS U3027 ( .B0(n4841), .B1(n4842), .A0N(n5117), .A1N(
FPADDSUB_DmP_mant_SFG_SWR[6]), .Y(n3304) );
NOR2X1TS U3028 ( .A(n3304), .B(n3303), .Y(n3302) );
AOI21X1TS U3029 ( .A0(FPADDSUB_DMP_SFG[5]), .A1(n5170), .B0(n3302), .Y(n3106) );
NOR2X1TS U3030 ( .A(n3106), .B(n3105), .Y(n3104) );
OAI22X1TS U3031 ( .A0(n2430), .A1(n3086), .B0(FPADDSUB_DmP_mant_SFG_SWR[9]),
.B1(n5131), .Y(n3245) );
NOR2X1TS U3032 ( .A(n3245), .B(n3244), .Y(n3243) );
AOI21X1TS U3033 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[10]), .A1(n5132), .B0(n3243),
.Y(n3256) );
NOR2X1TS U3034 ( .A(n3256), .B(n3255), .Y(n3254) );
AOI22X1TS U3035 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[13]), .A1(n5128), .B0(n2432),
.B1(n3285), .Y(n2887) );
NOR2X1TS U3036 ( .A(n2887), .B(n2886), .Y(n2885) );
AOI21X1TS U3037 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[14]), .A1(n5134), .B0(n2885),
.Y(n4849) );
OAI22X1TS U3038 ( .A0(FPADDSUB_DMP_SFG[13]), .A1(n4969), .B0(n2433), .B1(
n4849), .Y(n3117) );
NOR2X1TS U3039 ( .A(n3117), .B(n3116), .Y(n3115) );
AOI21X1TS U3040 ( .A0(FPADDSUB_DMP_SFG[14]), .A1(n5137), .B0(n3115), .Y(
n4855) );
NAND2X1TS U3041 ( .A(FPADDSUB_DMP_SFG[15]), .B(n5073), .Y(n4856) );
AOI2BB2X1TS U3042 ( .B0(n4855), .B1(n4856), .A0N(n5073), .A1N(
FPADDSUB_DMP_SFG[15]), .Y(n3315) );
NOR2X1TS U3043 ( .A(n3315), .B(n3314), .Y(n3313) );
AOI21X1TS U3044 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[18]), .A1(n5135), .B0(n3313),
.Y(n2464) );
NAND2X1TS U3045 ( .A(n2464), .B(n2466), .Y(n2463) );
OAI21X1TS U3046 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[19]), .A1(n5143), .B0(n2463),
.Y(n3123) );
NOR2X1TS U3047 ( .A(n3123), .B(n3122), .Y(n3121) );
AOI21X1TS U3048 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[20]), .A1(n5136), .B0(n3121),
.Y(n4863) );
OAI22X1TS U3049 ( .A0(FPADDSUB_DMP_SFG[19]), .A1(n5130), .B0(n4862), .B1(
n4863), .Y(n2434) );
NAND2X1TS U3050 ( .A(n2436), .B(n2434), .Y(n2850) );
OAI21XLTS U3051 ( .A0(n2436), .A1(n2434), .B0(n2850), .Y(n2439) );
INVX2TS U3052 ( .A(n3122), .Y(n3125) );
INVX2TS U3053 ( .A(n3314), .Y(n3317) );
INVX2TS U3054 ( .A(n3116), .Y(n3113) );
AOI22X1TS U3055 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[15]), .A1(
FPADDSUB_DMP_SFG[13]), .B0(n5172), .B1(n4969), .Y(n4850) );
INVX2TS U3056 ( .A(n2886), .Y(n2889) );
INVX2TS U3057 ( .A(n3255), .Y(n3258) );
INVX2TS U3058 ( .A(n3244), .Y(n3247) );
INVX2TS U3059 ( .A(n3105), .Y(n3102) );
INVX2TS U3060 ( .A(n3303), .Y(n3300) );
AND3X1TS U3061 ( .A(FPADDSUB_DmP_mant_SFG_SWR[2]), .B(FPADDSUB_DMP_SFG[0]),
.C(n3263), .Y(n3270) );
AOI21X1TS U3062 ( .A0(FPADDSUB_DMP_SFG[1]), .A1(FPADDSUB_DmP_mant_SFG_SWR[3]), .B0(n3270), .Y(n2907) );
NOR2X1TS U3063 ( .A(n2906), .B(n2907), .Y(n2905) );
AOI21X1TS U3064 ( .A0(FPADDSUB_DMP_SFG[2]), .A1(FPADDSUB_DmP_mant_SFG_SWR[4]), .B0(n2905), .Y(n3161) );
NOR2X1TS U3065 ( .A(n3161), .B(n3162), .Y(n3160) );
AO21X1TS U3066 ( .A0(FPADDSUB_DMP_SFG[3]), .A1(FPADDSUB_DmP_mant_SFG_SWR[5]),
.B0(n3160), .Y(n4843) );
AOI222X1TS U3067 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[6]), .A1(
FPADDSUB_DMP_SFG[4]), .B0(FPADDSUB_DmP_mant_SFG_SWR[6]), .B1(n4843),
.C0(FPADDSUB_DMP_SFG[4]), .C1(n4843), .Y(n3301) );
NOR2X1TS U3068 ( .A(n3300), .B(n3301), .Y(n3299) );
AOI21X1TS U3069 ( .A0(FPADDSUB_DMP_SFG[5]), .A1(FPADDSUB_DmP_mant_SFG_SWR[7]), .B0(n3299), .Y(n3103) );
NOR2X1TS U3070 ( .A(n3102), .B(n3103), .Y(n3101) );
AOI21X1TS U3071 ( .A0(FPADDSUB_DMP_SFG[6]), .A1(FPADDSUB_DmP_mant_SFG_SWR[8]), .B0(n3101), .Y(n3088) );
NOR2X1TS U3072 ( .A(n3088), .B(n3089), .Y(n3087) );
AOI21X1TS U3073 ( .A0(FPADDSUB_DMP_SFG[7]), .A1(FPADDSUB_DmP_mant_SFG_SWR[9]), .B0(n3087), .Y(n3248) );
NOR2X1TS U3074 ( .A(n3247), .B(n3248), .Y(n3246) );
AOI21X1TS U3075 ( .A0(FPADDSUB_DMP_SFG[8]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[10]), .B0(n3246), .Y(n3259) );
NOR2X1TS U3076 ( .A(n3258), .B(n3259), .Y(n3257) );
AOI21X1TS U3077 ( .A0(FPADDSUB_DMP_SFG[9]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[11]), .B0(n3257), .Y(n4038) );
NOR2X1TS U3078 ( .A(n4038), .B(n4044), .Y(n4037) );
AOI21X1TS U3079 ( .A0(n2337), .A1(FPADDSUB_DmP_mant_SFG_SWR[12]), .B0(n4037),
.Y(n3287) );
NOR2X1TS U3080 ( .A(n3287), .B(n3288), .Y(n3286) );
AOI21X1TS U3081 ( .A0(FPADDSUB_DMP_SFG[11]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[13]), .B0(n3286), .Y(n2890) );
NOR2X1TS U3082 ( .A(n2889), .B(n2890), .Y(n2888) );
AOI21X1TS U3083 ( .A0(FPADDSUB_DMP_SFG[12]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[14]), .B0(n2888), .Y(n4848) );
INVX2TS U3084 ( .A(n4848), .Y(n2435) );
AOI22X1TS U3085 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[15]), .A1(
FPADDSUB_DMP_SFG[13]), .B0(n4850), .B1(n2435), .Y(n3114) );
NOR2X1TS U3086 ( .A(n3113), .B(n3114), .Y(n3112) );
AO21X1TS U3087 ( .A0(FPADDSUB_DMP_SFG[14]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[16]), .B0(n3112), .Y(n4854) );
AOI222X1TS U3088 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[17]), .A1(
FPADDSUB_DMP_SFG[15]), .B0(FPADDSUB_DmP_mant_SFG_SWR[17]), .B1(n4854),
.C0(FPADDSUB_DMP_SFG[15]), .C1(n4854), .Y(n3318) );
NOR2X1TS U3089 ( .A(n3317), .B(n3318), .Y(n3316) );
AOI21X1TS U3090 ( .A0(FPADDSUB_DMP_SFG[16]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[18]), .B0(n3316), .Y(n2467) );
NOR2X1TS U3091 ( .A(n2466), .B(n2467), .Y(n2465) );
AOI21X1TS U3092 ( .A0(FPADDSUB_DMP_SFG[17]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[19]), .B0(n2465), .Y(n3126) );
NOR2X1TS U3093 ( .A(n3125), .B(n3126), .Y(n3124) );
AO21X1TS U3094 ( .A0(FPADDSUB_DMP_SFG[18]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[20]), .B0(n3124), .Y(n4864) );
AOI222X1TS U3095 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[21]), .A1(
FPADDSUB_DMP_SFG[19]), .B0(FPADDSUB_DmP_mant_SFG_SWR[21]), .B1(n4864),
.C0(FPADDSUB_DMP_SFG[19]), .C1(n4864), .Y(n2437) );
NOR2X1TS U3096 ( .A(n2436), .B(n2437), .Y(n2852) );
AOI21X1TS U3097 ( .A0(n4040), .A1(n2439), .B0(n2438), .Y(n2440) );
OAI21XLTS U3098 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(n4945), .B0(n2440),
.Y(n1317) );
NAND2X2TS U3099 ( .A(FPMULT_FS_Module_state_reg[2]), .B(n4965), .Y(n3178) );
INVX2TS U3100 ( .A(operation[1]), .Y(n4046) );
NAND2X1TS U3101 ( .A(operation[2]), .B(n4046), .Y(n3816) );
INVX2TS U3102 ( .A(n3816), .Y(n3817) );
NAND4XLTS U3103 ( .A(FPMULT_FS_Module_state_reg[2]), .B(
FPMULT_FS_Module_state_reg[3]), .C(n5052), .D(n4936), .Y(n3815) );
AOI21X1TS U3104 ( .A0(ack_operation), .A1(n4705), .B0(n3815), .Y(n3172) );
AOI21X1TS U3105 ( .A0(FPMULT_zero_flag), .A1(n2275), .B0(n3172), .Y(n2441)
);
OAI211XLTS U3106 ( .A0(n4936), .A1(n3178), .B0(n2441), .C0(n2632), .Y(n1693)
);
CLKBUFX2TS U3107 ( .A(n2442), .Y(n4722) );
CLKBUFX2TS U3108 ( .A(n4722), .Y(n4065) );
INVX2TS U3109 ( .A(n4065), .Y(n4241) );
NOR2X1TS U3110 ( .A(FPMULT_Sgf_normalized_result[1]), .B(
FPMULT_Sgf_normalized_result[0]), .Y(n4718) );
OR3X1TS U3111 ( .A(FPMULT_Sgf_normalized_result[2]), .B(
FPMULT_Sgf_normalized_result[1]), .C(FPMULT_Sgf_normalized_result[0]),
.Y(n4721) );
OAI21XLTS U3112 ( .A0(n4718), .A1(n5217), .B0(n4721), .Y(n2443) );
CLKBUFX2TS U3113 ( .A(n2442), .Y(n4737) );
AO22XLTS U3114 ( .A0(n4241), .A1(n2443), .B0(n4737), .B1(
FPMULT_Add_result[2]), .Y(n1618) );
INVX2TS U3115 ( .A(n2875), .Y(n3893) );
NOR2XLTS U3116 ( .A(FPMULT_FS_Module_state_reg[0]), .B(n3178), .Y(n2444) );
AOI31X4TS U3117 ( .A0(FPMULT_FS_Module_state_reg[1]), .A1(n2875), .A2(
FPMULT_FSM_add_overflow_flag), .B0(n2444), .Y(n3947) );
CLKBUFX3TS U3118 ( .A(n3947), .Y(n3965) );
NOR2XLTS U3119 ( .A(FPMULT_P_Sgf[46]), .B(n4759), .Y(n2446) );
NAND2X1TS U3120 ( .A(n2250), .B(FPMULT_FSM_selector_C), .Y(n2445) );
NAND2X1TS U3121 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B(n5191),
.Y(n4048) );
NAND2X1TS U3122 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B(n4048),
.Y(n4121) );
NAND3X1TS U3123 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(n2448),
.C(n2899), .Y(n4672) );
NAND2X1TS U3124 ( .A(n4671), .B(n4672), .Y(n3990) );
NOR3X1TS U3125 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .C(n5191), .Y(n4049) );
OAI21XLTS U3126 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .A1(
n4121), .B0(n2449), .Y(n2149) );
NOR4X1TS U3127 ( .A(Data_2[15]), .B(Data_2[19]), .C(Data_2[13]), .D(
Data_2[21]), .Y(n2452) );
NOR4X1TS U3128 ( .A(Data_2[4]), .B(Data_2[18]), .C(Data_2[20]), .D(Data_2[1]), .Y(n2451) );
NOR4X1TS U3129 ( .A(Data_2[3]), .B(Data_2[5]), .C(Data_2[22]), .D(Data_2[0]),
.Y(n2450) );
NAND3XLTS U3130 ( .A(n2452), .B(n2451), .C(n2450), .Y(n2453) );
AOI22X1TS U3131 ( .A0(n2194), .A1(n2401), .B0(n4931), .B1(n5032), .Y(n2702)
);
AOI22X1TS U3132 ( .A0(n2235), .A1(n2401), .B0(n2330), .B1(n5046), .Y(n2455)
);
AO22XLTS U3133 ( .A0(n4406), .A1(n2702), .B0(n2703), .B1(n2455), .Y(
mult_x_219_n172) );
AO22XLTS U3134 ( .A0(n4406), .A1(n2455), .B0(n2703), .B1(n2454), .Y(
mult_x_219_n173) );
AOI22X1TS U3135 ( .A0(n2234), .A1(n2341), .B0(n2280), .B1(n5050), .Y(n2706)
);
AOI22X1TS U3136 ( .A0(FPMULT_Op_MY[3]), .A1(n2341), .B0(n2280), .B1(n5041),
.Y(n2457) );
AO22XLTS U3137 ( .A0(n3203), .A1(n2706), .B0(n2707), .B1(n2457), .Y(
mult_x_254_n178) );
AO22XLTS U3138 ( .A0(n3203), .A1(n2457), .B0(n2707), .B1(n2456), .Y(
mult_x_254_n179) );
CMPR32X2TS U3139 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MX[18]), .C(n2458),
.CO(n2694), .S(n2460) );
NOR2XLTS U3140 ( .A(n2357), .B(n2460), .Y(n2459) );
AOI32X4TS U3141 ( .A0(n2460), .A1(n2285), .A2(n2357), .B0(n2459), .B1(n2352),
.Y(n4594) );
AOI22X1TS U3142 ( .A0(n4587), .A1(n2350), .B0(n2352), .B1(n2257), .Y(n4082)
);
INVX2TS U3143 ( .A(n4598), .Y(n4417) );
INVX2TS U3144 ( .A(n4584), .Y(n4583) );
AOI22X1TS U3145 ( .A0(n4584), .A1(n2351), .B0(n2285), .B1(n4583), .Y(n4415)
);
OAI2BB2XLTS U3146 ( .B0(n4594), .B1(n4082), .A0N(n4417), .A1N(n4415), .Y(
DP_OP_454J200_123_2743_n213) );
INVX2TS U3147 ( .A(n2388), .Y(n3133) );
AOI22X1TS U3148 ( .A0(FPMULT_Sgf_normalized_result[11]), .A1(n2314), .B0(
FPMULT_P_Sgf[35]), .B1(n2370), .Y(n2462) );
AOI22X1TS U3149 ( .A0(FPMULT_P_Sgf[34]), .A1(n3141), .B0(
FPMULT_Add_result[11]), .B1(n2328), .Y(n2461) );
OAI211XLTS U3150 ( .A0(n5215), .A1(n2241), .B0(n2462), .C0(n2461), .Y(n1516)
);
CLKBUFX2TS U3151 ( .A(FPADDSUB_Shift_reg_FLAGS_7[2]), .Y(n4853) );
INVX2TS U3152 ( .A(n4853), .Y(n4846) );
AOI21X1TS U3153 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[19]), .A1(n4319), .B0(n2468),
.Y(n2469) );
NAND2X1TS U3154 ( .A(n2470), .B(n2469), .Y(n1321) );
INVX2TS U3155 ( .A(n4722), .Y(n4734) );
AOI22X1TS U3156 ( .A0(n4734), .A1(FPMULT_Sgf_normalized_result[23]), .B0(
FPMULT_Add_result[23]), .B1(n4722), .Y(n2471) );
NAND2X1TS U3157 ( .A(FPMULT_Sgf_normalized_result[3]), .B(n4721), .Y(n4720)
);
NAND2X1TS U3158 ( .A(n5121), .B(n4720), .Y(n4725) );
NAND2X1TS U3159 ( .A(FPMULT_Sgf_normalized_result[5]), .B(n4725), .Y(n4724)
);
NAND2X1TS U3160 ( .A(FPMULT_Sgf_normalized_result[7]), .B(n4728), .Y(n4727)
);
NAND2X1TS U3161 ( .A(FPMULT_Sgf_normalized_result[9]), .B(n3987), .Y(n3985)
);
NAND2X1TS U3162 ( .A(FPMULT_Sgf_normalized_result[11]), .B(n4731), .Y(n4730)
);
NAND2X1TS U3163 ( .A(FPMULT_Sgf_normalized_result[13]), .B(n4061), .Y(n3977)
);
NAND2X1TS U3164 ( .A(FPMULT_Sgf_normalized_result[15]), .B(n4735), .Y(n4733)
);
NAND2X1TS U3165 ( .A(FPMULT_Sgf_normalized_result[17]), .B(n3983), .Y(n3981)
);
NAND2X1TS U3166 ( .A(FPMULT_Sgf_normalized_result[19]), .B(n3980), .Y(n3975)
);
NAND2X1TS U3167 ( .A(FPMULT_Sgf_normalized_result[21]), .B(n4738), .Y(n4739)
);
INVX2TS U3168 ( .A(n4065), .Y(n3989) );
NAND3BXLTS U3169 ( .AN(n4739), .B(FPMULT_Sgf_normalized_result[22]), .C(
n3989), .Y(n4239) );
MXI2X1TS U3170 ( .A(FPMULT_Sgf_normalized_result[23]), .B(n2471), .S0(n4239),
.Y(n1597) );
CLKBUFX2TS U3171 ( .A(n2472), .Y(n5357) );
NOR3BXLTS U3172 ( .AN(n4671), .B(n4128), .C(ready_add_subt), .Y(n4683) );
NOR2X1TS U3173 ( .A(n2360), .B(n4937), .Y(n4682) );
OAI32X1TS U3174 ( .A0(FPSENCOS_cont_var_out[1]), .A1(n2360), .A2(n4937),
.B0(n4682), .B1(n5053), .Y(n2136) );
NOR2X2TS U3175 ( .A(n4680), .B(n4292), .Y(n4119) );
OAI32X1TS U3176 ( .A0(n4119), .A1(n4680), .A2(n4963), .B0(n5055), .B1(n4119),
.Y(n2138) );
INVX2TS U3177 ( .A(n5250), .Y(n5359) );
OAI21XLTS U3178 ( .A0(n4693), .A1(n5123), .B0(n2301), .Y(n2079) );
NAND3X1TS U3179 ( .A(n5053), .B(FPSENCOS_cont_var_out[0]), .C(ready_add_subt), .Y(n2473) );
CLKBUFX3TS U3180 ( .A(n4700), .Y(n4701) );
OAI2BB2XLTS U3181 ( .B0(n4701), .B1(n5093), .A0N(n2634), .A1N(
FPSENCOS_d_ff_Yn[27]), .Y(n1773) );
OAI2BB2XLTS U3182 ( .B0(n4701), .B1(n5071), .A0N(n2634), .A1N(
FPSENCOS_d_ff_Yn[26]), .Y(n1776) );
NOR2X1TS U3183 ( .A(n3991), .B(n4119), .Y(n2474) );
CLKBUFX2TS U3184 ( .A(n2474), .Y(n3579) );
XNOR2X1TS U3185 ( .A(FPSENCOS_d_ff1_shift_region_flag_out[1]), .B(
FPSENCOS_d_ff1_operation_out), .Y(n2475) );
CLKXOR2X2TS U3186 ( .A(FPSENCOS_d_ff1_shift_region_flag_out[0]), .B(n2475),
.Y(n3509) );
INVX2TS U3187 ( .A(n3509), .Y(n3511) );
AOI22X1TS U3188 ( .A0(n3509), .A1(FPSENCOS_d_ff_Xn[31]), .B0(
FPSENCOS_d_ff_Yn[31]), .B1(n3511), .Y(n2477) );
XOR2XLTS U3189 ( .A(n2477), .B(n2476), .Y(n2478) );
OAI2BB2XLTS U3190 ( .B0(n3579), .B1(n2478), .A0N(n3579), .A1N(
cordic_result[31]), .Y(n1695) );
OAI2BB2XLTS U3191 ( .B0(n4701), .B1(n5092), .A0N(n2634), .A1N(
FPSENCOS_d_ff_Yn[25]), .Y(n1779) );
OAI2BB2XLTS U3192 ( .B0(n4701), .B1(n5091), .A0N(n2634), .A1N(
FPSENCOS_d_ff_Yn[24]), .Y(n1782) );
NAND4BXLTS U3193 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .C(n5181), .D(n2901), .Y(
n2479) );
INVX2TS U3194 ( .A(n2479), .Y(n5358) );
INVX2TS U3195 ( .A(FPMULT_Sgf_operation_Result[10]), .Y(n2554) );
INVX2TS U3196 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[10]), .Y(
n2553) );
INVX2TS U3197 ( .A(n2480), .Y(n2558) );
INVX2TS U3198 ( .A(FPMULT_Sgf_operation_Result[9]), .Y(n2483) );
INVX2TS U3199 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[9]), .Y(n2482) );
INVX2TS U3200 ( .A(n2481), .Y(n2557) );
CMPR32X2TS U3201 ( .A(n2483), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[9]), .C(n2482), .CO(
n2481), .S(n2484) );
INVX2TS U3202 ( .A(n2484), .Y(n2514) );
INVX2TS U3203 ( .A(FPMULT_Sgf_operation_Result[8]), .Y(n2487) );
INVX2TS U3204 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[8]), .Y(n2486) );
INVX2TS U3205 ( .A(n2485), .Y(n2513) );
CMPR32X2TS U3206 ( .A(n2487), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[8]), .C(n2486), .CO(
n2485), .S(n2488) );
INVX2TS U3207 ( .A(n2488), .Y(n2517) );
INVX2TS U3208 ( .A(FPMULT_Sgf_operation_Result[7]), .Y(n2491) );
INVX2TS U3209 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[7]), .Y(n2490) );
INVX2TS U3210 ( .A(n2489), .Y(n2516) );
CMPR32X2TS U3211 ( .A(n2491), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[7]), .C(n2490), .CO(
n2489), .S(n2492) );
INVX2TS U3212 ( .A(n2492), .Y(n2520) );
INVX2TS U3213 ( .A(FPMULT_Sgf_operation_Result[6]), .Y(n2495) );
INVX2TS U3214 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[6]), .Y(n2494) );
INVX2TS U3215 ( .A(n2493), .Y(n2519) );
CMPR32X2TS U3216 ( .A(n2495), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[6]), .C(n2494), .CO(
n2493), .S(n2496) );
INVX2TS U3217 ( .A(n2496), .Y(n2523) );
INVX2TS U3218 ( .A(FPMULT_Sgf_operation_Result[5]), .Y(n2499) );
INVX2TS U3219 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[5]), .Y(n2498) );
INVX2TS U3220 ( .A(n2497), .Y(n2522) );
CMPR32X2TS U3221 ( .A(n2499), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[5]), .C(n2498), .CO(
n2497), .S(n2500) );
INVX2TS U3222 ( .A(n2500), .Y(n2526) );
INVX2TS U3223 ( .A(FPMULT_Sgf_operation_Result[4]), .Y(n2502) );
INVX2TS U3224 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[4]), .Y(n2617) );
INVX2TS U3225 ( .A(n2501), .Y(n2525) );
CMPR32X2TS U3226 ( .A(n2502), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[4]), .C(n2617), .CO(
n2501), .S(n2503) );
INVX2TS U3227 ( .A(n2503), .Y(n2540) );
INVX2TS U3228 ( .A(FPMULT_Sgf_operation_Result[3]), .Y(n2506) );
INVX2TS U3229 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[3]), .Y(n2505) );
INVX2TS U3230 ( .A(n2504), .Y(n2539) );
CMPR32X2TS U3231 ( .A(n2506), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[3]), .C(n2505), .CO(
n2504), .S(n2507) );
INVX2TS U3232 ( .A(n2507), .Y(n2529) );
INVX2TS U3233 ( .A(FPMULT_Sgf_operation_Result[2]), .Y(n2510) );
INVX2TS U3234 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[2]), .Y(n2509) );
INVX2TS U3235 ( .A(n2508), .Y(n2528) );
INVX2TS U3236 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[1]), .Y(n2611) );
NOR2X1TS U3237 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[1]), .B(
n2611), .Y(n2533) );
CMPR32X2TS U3238 ( .A(n2510), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[2]), .C(n2509), .CO(
n2508), .S(n2511) );
INVX2TS U3239 ( .A(n2511), .Y(n2532) );
INVX2TS U3240 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[0]), .Y(
n2534) );
AOI21X1TS U3241 ( .A0(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[1]),
.A1(n2611), .B0(n2533), .Y(n2535) );
INVX2TS U3242 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[22]), .Y(
n3445) );
CMPR32X2TS U3243 ( .A(n2514), .B(n2513), .C(n2512), .CO(n2556), .S(n4212) );
CMPR32X2TS U3244 ( .A(n2517), .B(n2516), .C(n2515), .CO(n2512), .S(n2550) );
CMPR32X2TS U3245 ( .A(n2520), .B(n2519), .C(n2518), .CO(n2515), .S(n2548) );
CMPR32X2TS U3246 ( .A(n2523), .B(n2522), .C(n2521), .CO(n2518), .S(n2546) );
CMPR32X2TS U3247 ( .A(n2526), .B(n2525), .C(n2524), .CO(n2521), .S(n2544) );
CMPR32X2TS U3248 ( .A(n2529), .B(n2528), .C(n2527), .CO(n2538), .S(n2530) );
INVX2TS U3249 ( .A(n2530), .Y(n4341) );
CMPR32X2TS U3250 ( .A(n2533), .B(n2532), .C(n2531), .CO(n2527), .S(n4204) );
INVX2TS U3251 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[14]), .Y(
n2584) );
CMPR32X2TS U3252 ( .A(FPMULT_Sgf_operation_Result[0]), .B(n2534), .C(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[0]), .CO(n2536), .S(n4277)
);
CMPR32X2TS U3253 ( .A(FPMULT_Sgf_operation_Result[1]), .B(n2536), .C(n2535),
.CO(n2531), .S(n2537) );
INVX2TS U3254 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[12]), .Y(
n4276) );
NOR3X1TS U3255 ( .A(n4277), .B(n2537), .C(n4276), .Y(n4295) );
OAI21X1TS U3256 ( .A0(n4277), .A1(n4276), .B0(n2537), .Y(n4294) );
AOI222X1TS U3257 ( .A0(n4204), .A1(n2584), .B0(n4204), .B1(n4203), .C0(n2584), .C1(n4203), .Y(n4340) );
CMPR32X2TS U3258 ( .A(n2540), .B(n2539), .C(n2538), .CO(n2524), .S(n2541) );
NOR2BX1TS U3259 ( .AN(n2542), .B(n2541), .Y(n4282) );
NAND2BXLTS U3260 ( .AN(n2542), .B(n2541), .Y(n4281) );
OAI21X1TS U3261 ( .A0(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[16]),
.A1(n4282), .B0(n4281), .Y(n2543) );
NOR2X1TS U3262 ( .A(n2544), .B(n2543), .Y(n4208) );
NAND2X1TS U3263 ( .A(n2544), .B(n2543), .Y(n4207) );
OAI21X1TS U3264 ( .A0(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[17]),
.A1(n4208), .B0(n4207), .Y(n2545) );
NOR2X1TS U3265 ( .A(n2546), .B(n2545), .Y(n4286) );
NAND2X1TS U3266 ( .A(n2546), .B(n2545), .Y(n4285) );
OAI21X1TS U3267 ( .A0(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[18]),
.A1(n4286), .B0(n4285), .Y(n2547) );
NOR2X1TS U3268 ( .A(n2548), .B(n2547), .Y(n4348) );
NAND2X1TS U3269 ( .A(n2548), .B(n2547), .Y(n4347) );
OAI21X1TS U3270 ( .A0(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[19]),
.A1(n4348), .B0(n4347), .Y(n2549) );
NOR2X1TS U3271 ( .A(n2550), .B(n2549), .Y(n4299) );
NAND2X1TS U3272 ( .A(n2550), .B(n2549), .Y(n4298) );
INVX2TS U3273 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[21]), .Y(
n3437) );
INVX2TS U3274 ( .A(n4328), .Y(n2551) );
AOI222X1TS U3275 ( .A0(n4329), .A1(n3445), .B0(n4329), .B1(n2551), .C0(n3445), .C1(n2551), .Y(n4333) );
INVX2TS U3276 ( .A(FPMULT_Sgf_operation_Result[11]), .Y(n2562) );
INVX2TS U3277 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[11]), .Y(
n2561) );
INVX2TS U3278 ( .A(n2552), .Y(n2566) );
CMPR32X2TS U3279 ( .A(n2554), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[10]), .C(n2553), .CO(
n2555), .S(n2480) );
INVX2TS U3280 ( .A(n2555), .Y(n2565) );
CMPR32X2TS U3281 ( .A(n2558), .B(n2557), .C(n2556), .CO(n2564), .S(n4329) );
INVX2TS U3282 ( .A(n2559), .Y(n4332) );
INVX2TS U3283 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[12]), .Y(
n2589) );
INVX2TS U3284 ( .A(n2560), .Y(n2593) );
CMPR32X2TS U3285 ( .A(n2562), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[11]), .C(n2561), .CO(
n2563), .S(n2552) );
INVX2TS U3286 ( .A(n2563), .Y(n2592) );
CMPR32X2TS U3287 ( .A(n2566), .B(n2565), .C(n2564), .CO(n2591), .S(n2559) );
NOR2BX1TS U3288 ( .AN(n2568), .B(n2567), .Y(n2610) );
NAND2BXLTS U3289 ( .AN(n2568), .B(n2567), .Y(n2609) );
NAND2BXLTS U3290 ( .AN(n2610), .B(n2609), .Y(n2569) );
XNOR2X1TS U3291 ( .A(n2569), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[0]), .Y(n2570) );
INVX2TS U3292 ( .A(n3965), .Y(n2628) );
CLKBUFX3TS U3293 ( .A(n3947), .Y(n3216) );
CLKAND2X2TS U3294 ( .A(FPMULT_P_Sgf[24]), .B(n3216), .Y(n3272) );
AO21XLTS U3295 ( .A0(n2570), .A1(n2628), .B0(n3272), .Y(n1553) );
INVX2TS U3296 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[18]), .Y(
n2620) );
INVX2TS U3297 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[18]), .Y(
n3958) );
INVX2TS U3298 ( .A(n2571), .Y(n2624) );
INVX2TS U3299 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[17]), .Y(
n2574) );
INVX2TS U3300 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[17]), .Y(
n2573) );
INVX2TS U3301 ( .A(n2572), .Y(n2623) );
CMPR32X2TS U3302 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[17]),
.B(n2574), .C(n2573), .CO(n2572), .S(n2575) );
INVX2TS U3303 ( .A(n2575), .Y(n2597) );
INVX2TS U3304 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[16]), .Y(
n2577) );
INVX2TS U3305 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[16]), .Y(
n3962) );
INVX2TS U3306 ( .A(n2576), .Y(n2596) );
CMPR32X2TS U3307 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[16]),
.B(n2577), .C(n3962), .CO(n2576), .S(n2578) );
INVX2TS U3308 ( .A(n2578), .Y(n2601) );
INVX2TS U3309 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[15]), .Y(
n2581) );
INVX2TS U3310 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[15]), .Y(
n2580) );
INVX2TS U3311 ( .A(n2579), .Y(n2600) );
CMPR32X2TS U3312 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[15]),
.B(n2581), .C(n2580), .CO(n2579), .S(n2582) );
INVX2TS U3313 ( .A(n2582), .Y(n2604) );
INVX2TS U3314 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[14]), .Y(
n4254) );
INVX2TS U3315 ( .A(n2583), .Y(n2603) );
CMPR32X2TS U3316 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[14]),
.B(n2584), .C(n4254), .CO(n2583), .S(n2585) );
INVX2TS U3317 ( .A(n2585), .Y(n2614) );
INVX2TS U3318 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[13]), .Y(
n2587) );
INVX2TS U3319 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[13]), .Y(
n4756) );
INVX2TS U3320 ( .A(n2586), .Y(n2613) );
CMPR32X2TS U3321 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[13]),
.B(n2587), .C(n4756), .CO(n2586), .S(n2588) );
INVX2TS U3322 ( .A(n2588), .Y(n2608) );
CMPR32X2TS U3323 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[12]),
.B(n4276), .C(n2589), .CO(n2590), .S(n2560) );
INVX2TS U3324 ( .A(n2590), .Y(n2607) );
CMPR32X2TS U3325 ( .A(n2593), .B(n2592), .C(n2591), .CO(n2606), .S(n2567) );
INVX2TS U3326 ( .A(n2594), .Y(n4259) );
CMPR32X2TS U3327 ( .A(n2597), .B(n2596), .C(n2595), .CO(n2622), .S(n2598) );
INVX2TS U3328 ( .A(n2598), .Y(n3931) );
CMPR32X2TS U3329 ( .A(n2601), .B(n2600), .C(n2599), .CO(n2595), .S(n4217) );
CMPR32X2TS U3330 ( .A(n2604), .B(n2603), .C(n2602), .CO(n2599), .S(n2605) );
INVX2TS U3331 ( .A(n2605), .Y(n4266) );
CMPR32X2TS U3332 ( .A(n2608), .B(n2607), .C(n2606), .CO(n2612), .S(n3925) );
AOI222X1TS U3333 ( .A0(n3925), .A1(n2611), .B0(n3925), .B1(n3924), .C0(n2611), .C1(n3924), .Y(n3934) );
CMPR32X2TS U3334 ( .A(n2614), .B(n2613), .C(n2612), .CO(n2602), .S(n2615) );
INVX2TS U3335 ( .A(n2615), .Y(n3933) );
NOR2BX1TS U3336 ( .AN(n4217), .B(n4216), .Y(n2618) );
NAND2BXLTS U3337 ( .AN(n4217), .B(n4216), .Y(n2616) );
OAI21XLTS U3338 ( .A0(n2618), .A1(n2617), .B0(n2616), .Y(n3930) );
INVX2TS U3339 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[19]), .Y(
n3032) );
INVX2TS U3340 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[19]), .Y(
n3031) );
INVX2TS U3341 ( .A(n2619), .Y(n3036) );
CMPR32X2TS U3342 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[18]),
.B(n2620), .C(n3958), .CO(n2621), .S(n2571) );
INVX2TS U3343 ( .A(n2621), .Y(n3035) );
CMPR32X2TS U3344 ( .A(n2624), .B(n2623), .C(n2622), .CO(n3034), .S(n2594) );
NOR2BX1TS U3345 ( .AN(n2626), .B(n2625), .Y(n3028) );
NAND2BXLTS U3346 ( .AN(n2626), .B(n2625), .Y(n3029) );
NAND2BXLTS U3347 ( .AN(n3028), .B(n3029), .Y(n2627) );
XNOR2X1TS U3348 ( .A(n2627), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[7]), .Y(n2629) );
CLKBUFX3TS U3349 ( .A(n3947), .Y(n3394) );
CLKAND2X2TS U3350 ( .A(FPMULT_P_Sgf[31]), .B(n3394), .Y(n3130) );
AO21XLTS U3351 ( .A0(n2629), .A1(n2628), .B0(n3130), .Y(n1560) );
CLKBUFX3TS U3352 ( .A(n2473), .Y(n2633) );
CLKBUFX3TS U3353 ( .A(n4700), .Y(n4684) );
OAI2BB2XLTS U3354 ( .B0(n2633), .B1(n5101), .A0N(n4684), .A1N(
FPSENCOS_d_ff_Yn[11]), .Y(n2040) );
CLKBUFX3TS U3355 ( .A(n2473), .Y(n4685) );
OAI2BB2XLTS U3356 ( .B0(n4685), .B1(n5100), .A0N(n4684), .A1N(
FPSENCOS_d_ff_Yn[8]), .Y(n2049) );
OAI2BB2XLTS U3357 ( .B0(n2633), .B1(n5063), .A0N(n4684), .A1N(
FPSENCOS_d_ff_Yn[14]), .Y(n2031) );
OAI2BB2XLTS U3358 ( .B0(n2633), .B1(n5062), .A0N(n4684), .A1N(
FPSENCOS_d_ff_Yn[16]), .Y(n2025) );
OAI2BB2XLTS U3359 ( .B0(n4685), .B1(n5064), .A0N(n4684), .A1N(
FPSENCOS_d_ff_Yn[10]), .Y(n2043) );
OAI2BB2XLTS U3360 ( .B0(n2633), .B1(n5065), .A0N(n4684), .A1N(
FPSENCOS_d_ff_Yn[12]), .Y(n2037) );
OAI2BB2XLTS U3361 ( .B0(n2633), .B1(n5061), .A0N(n4684), .A1N(
FPSENCOS_d_ff_Yn[13]), .Y(n2034) );
OAI2BB2XLTS U3362 ( .B0(n4685), .B1(n5066), .A0N(n2634), .A1N(
FPSENCOS_d_ff_Yn[3]), .Y(n2064) );
CLKBUFX3TS U3363 ( .A(n4700), .Y(n2647) );
OAI2BB2XLTS U3364 ( .B0(n4685), .B1(n5060), .A0N(n2647), .A1N(
FPSENCOS_d_ff_Yn[6]), .Y(n2055) );
NAND4BXLTS U3365 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .C(n2630), .D(n5020), .Y(
n2631) );
INVX2TS U3366 ( .A(n2631), .Y(n4262) );
CLKBUFX2TS U3367 ( .A(n4262), .Y(n4252) );
INVX2TS U3368 ( .A(n4252), .Y(n4346) );
CLKBUFX2TS U3369 ( .A(n4262), .Y(n4257) );
AO21XLTS U3370 ( .A0(FPSENCOS_d_ff3_LUT_out[8]), .A1(n4346), .B0(n4307), .Y(
n2125) );
OAI2BB2XLTS U3371 ( .B0(n4685), .B1(n5068), .A0N(n2647), .A1N(
FPSENCOS_d_ff_Yn[7]), .Y(n2052) );
OAI2BB2XLTS U3372 ( .B0(n2633), .B1(n5059), .A0N(n4684), .A1N(
FPSENCOS_d_ff_Yn[17]), .Y(n2022) );
OAI2BB2XLTS U3373 ( .B0(n4685), .B1(n5069), .A0N(n2634), .A1N(
FPSENCOS_d_ff_Yn[1]), .Y(n2070) );
OAI2BB2XLTS U3374 ( .B0(n2633), .B1(n5058), .A0N(n2647), .A1N(
FPSENCOS_d_ff_Yn[20]), .Y(n2013) );
OAI2BB2XLTS U3375 ( .B0(n4685), .B1(n5103), .A0N(n2647), .A1N(
FPSENCOS_d_ff_Yn[9]), .Y(n2046) );
OAI2BB2XLTS U3376 ( .B0(n2633), .B1(n5057), .A0N(n2647), .A1N(
FPSENCOS_d_ff_Yn[19]), .Y(n2016) );
OAI2BB2XLTS U3377 ( .B0(n4685), .B1(n5070), .A0N(n2647), .A1N(
FPSENCOS_d_ff_Yn[5]), .Y(n2058) );
OAI2BB2XLTS U3378 ( .B0(n4701), .B1(n5098), .A0N(n2634), .A1N(
FPSENCOS_d_ff_Yn[21]), .Y(n2010) );
OAI2BB2XLTS U3379 ( .B0(n2633), .B1(n5097), .A0N(n2647), .A1N(
FPSENCOS_d_ff_Yn[18]), .Y(n2019) );
OAI2BB2XLTS U3380 ( .B0(n4685), .B1(n5096), .A0N(n2647), .A1N(
FPSENCOS_d_ff_Yn[15]), .Y(n2028) );
OAI2BB2XLTS U3381 ( .B0(n4701), .B1(n5095), .A0N(n2647), .A1N(
FPSENCOS_d_ff_Yn[22]), .Y(n2007) );
INVX2TS U3382 ( .A(n4744), .Y(n4273) );
CLKBUFX3TS U3383 ( .A(n4273), .Y(n4745) );
OR4X2TS U3384 ( .A(FPMULT_exp_oper_result[8]), .B(
FPMULT_Exp_module_Overflow_flag_A), .C(underflow_flag_mult), .D(n4745),
.Y(n4743) );
CLKBUFX2TS U3385 ( .A(n4743), .Y(n4269) );
OA22X1TS U3386 ( .A0(n4744), .A1(mult_result[23]), .B0(
FPMULT_exp_oper_result[0]), .B1(n4269), .Y(n1584) );
OAI2BB2XLTS U3387 ( .B0(n2633), .B1(n5195), .A0N(n2634), .A1N(
FPSENCOS_d_ff_Yn[30]), .Y(n1730) );
OA22X1TS U3388 ( .A0(n4744), .A1(mult_result[24]), .B0(
FPMULT_exp_oper_result[1]), .B1(n4269), .Y(n1583) );
OA22X1TS U3389 ( .A0(n4744), .A1(mult_result[26]), .B0(
FPMULT_exp_oper_result[3]), .B1(n4269), .Y(n1581) );
OAI2BB2XLTS U3390 ( .B0(n4701), .B1(n4976), .A0N(n2634), .A1N(
FPSENCOS_d_ff_Yn[28]), .Y(n1770) );
NOR3BX1TS U3391 ( .AN(FPMULT_Op_MY[30]), .B(FPMULT_FSM_selector_B[1]), .C(
FPMULT_FSM_selector_B[0]), .Y(n2635) );
XOR2X1TS U3392 ( .A(n2274), .B(n2635), .Y(DP_OP_234J200_127_8543_n15) );
NAND2X1TS U3393 ( .A(FPSENCOS_cont_iter_out[0]), .B(n4187), .Y(n4303) );
CLKBUFX3TS U3394 ( .A(n4262), .Y(n4249) );
NAND2X2TS U3395 ( .A(n4249), .B(n4292), .Y(n4186) );
INVX2TS U3396 ( .A(n4186), .Y(n4345) );
NAND2X1TS U3397 ( .A(n4303), .B(n4345), .Y(n3492) );
AOI22X1TS U3398 ( .A0(FPSENCOS_d_ff3_LUT_out[12]), .A1(n4313), .B0(
FPSENCOS_cont_iter_out[3]), .B1(n4307), .Y(n2636) );
OAI21XLTS U3399 ( .A0(n2202), .A1(n3492), .B0(n2636), .Y(n2122) );
NAND2X2TS U3400 ( .A(FPMULT_FSM_selector_B[0]), .B(n5036), .Y(n2645) );
OAI2BB1X1TS U3401 ( .A0N(FPMULT_Op_MY[29]), .A1N(n5036), .B0(n2645), .Y(
n2637) );
XOR2X1TS U3402 ( .A(n2274), .B(n2637), .Y(DP_OP_234J200_127_8543_n16) );
INVX2TS U3403 ( .A(n4305), .Y(n4291) );
AOI22X1TS U3404 ( .A0(FPSENCOS_d_ff3_LUT_out[2]), .A1(n4313), .B0(n2372),
.B1(n4307), .Y(n2638) );
OAI31X1TS U3405 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(n4963), .A2(n4291),
.B0(n2638), .Y(n2131) );
OAI2BB1X1TS U3406 ( .A0N(FPMULT_Op_MY[28]), .A1N(n5036), .B0(n2645), .Y(
n2639) );
XOR2X1TS U3407 ( .A(n2275), .B(n2639), .Y(DP_OP_234J200_127_8543_n17) );
NOR2XLTS U3408 ( .A(n5077), .B(n2261), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N0) );
OAI2BB1X1TS U3409 ( .A0N(FPMULT_Op_MY[27]), .A1N(n5036), .B0(n2645), .Y(
n2640) );
XOR2X1TS U3410 ( .A(n2275), .B(n2640), .Y(DP_OP_234J200_127_8543_n18) );
OAI2BB1X1TS U3411 ( .A0N(FPMULT_Op_MY[26]), .A1N(n5036), .B0(n2645), .Y(
n2641) );
XOR2X1TS U3412 ( .A(n2275), .B(n2641), .Y(DP_OP_234J200_127_8543_n19) );
NOR2XLTS U3413 ( .A(FPMULT_FSM_selector_B[1]), .B(FPMULT_Op_MY[23]), .Y(
n2642) );
XOR2X1TS U3414 ( .A(n2275), .B(n2643), .Y(DP_OP_234J200_127_8543_n22) );
OAI2BB1X1TS U3415 ( .A0N(FPMULT_Op_MY[24]), .A1N(n5036), .B0(n2645), .Y(
n2644) );
XOR2X1TS U3416 ( .A(n2275), .B(n2644), .Y(DP_OP_234J200_127_8543_n21) );
OAI2BB1X1TS U3417 ( .A0N(FPMULT_Op_MY[25]), .A1N(n5036), .B0(n2645), .Y(
n2646) );
XOR2X1TS U3418 ( .A(n2275), .B(n2646), .Y(DP_OP_234J200_127_8543_n20) );
OAI2BB2XLTS U3419 ( .B0(n4701), .B1(n5120), .A0N(n2647), .A1N(
FPSENCOS_d_ff_Yn[31]), .Y(n1908) );
NAND2X2TS U3420 ( .A(FPMULT_Op_MX[12]), .B(n4962), .Y(n3745) );
NOR2X2TS U3421 ( .A(n5077), .B(n4962), .Y(n4401) );
INVX2TS U3422 ( .A(n4401), .Y(n2811) );
AOI22X1TS U3423 ( .A0(FPMULT_Op_MY[17]), .A1(n3745), .B0(n2811), .B1(n5039),
.Y(n2648) );
AOI21X1TS U3424 ( .A0(n3821), .A1(n5032), .B0(n2648), .Y(n2806) );
AOI211X1TS U3425 ( .A0(n2287), .A1(n2207), .B0(n2806), .C0(mult_x_219_n191),
.Y(mult_x_219_n136) );
CLKBUFX3TS U3426 ( .A(FPADDSUB_Shift_reg_FLAGS_7_5), .Y(n4357) );
NAND2X1TS U3427 ( .A(FPADDSUB_DmP_EXP_EWSW[23]), .B(n4982), .Y(n4222) );
AOI2BB2XLTS U3428 ( .B0(FPADDSUB_DMP_EXP_EWSW[27]), .B1(
FPADDSUB_DmP_EXP_EWSW[27]), .A0N(FPADDSUB_DmP_EXP_EWSW[27]), .A1N(
FPADDSUB_DMP_EXP_EWSW[27]), .Y(n2649) );
XNOR2X1TS U3429 ( .A(n2650), .B(n2649), .Y(n2651) );
CLKBUFX2TS U3430 ( .A(FPADDSUB_Shift_reg_FLAGS_7_5), .Y(n4060) );
INVX2TS U3431 ( .A(n4060), .Y(n4223) );
AO22XLTS U3432 ( .A0(n4357), .A1(n2651), .B0(n4223), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[4]), .Y(n1474) );
CLKBUFX3TS U3433 ( .A(FPADDSUB_Shift_reg_FLAGS_7_5), .Y(n4356) );
CMPR32X2TS U3434 ( .A(n5198), .B(FPADDSUB_DMP_EXP_EWSW[25]), .C(n2652), .CO(
n4359), .S(n2653) );
AO22XLTS U3435 ( .A0(n4356), .A1(n2653), .B0(n4223), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[2]), .Y(n1477) );
CLKBUFX2TS U3436 ( .A(clk), .Y(n2655) );
CLKBUFX2TS U3437 ( .A(clk), .Y(n2657) );
BUFX3TS U3438 ( .A(n5371), .Y(n5431) );
CLKBUFX2TS U3439 ( .A(clk), .Y(n2658) );
BUFX3TS U3440 ( .A(n2658), .Y(n5374) );
BUFX3TS U3441 ( .A(n5403), .Y(n5417) );
CLKBUFX2TS U3442 ( .A(clk), .Y(n2667) );
BUFX3TS U3443 ( .A(n2333), .Y(n5370) );
BUFX3TS U3444 ( .A(n5440), .Y(n5446) );
BUFX3TS U3445 ( .A(n5370), .Y(n5371) );
AOI22X1TS U3446 ( .A0(n2271), .A1(n2204), .B0(n5050), .B1(n2272), .Y(n2696)
);
AOI22X1TS U3447 ( .A0(n2271), .A1(FPMULT_Op_MY[3]), .B0(n5041), .B1(n2272),
.Y(n2749) );
AO22XLTS U3448 ( .A0(n3199), .A1(n2696), .B0(n3197), .B1(n2749), .Y(
mult_x_254_n220) );
AOI22X1TS U3449 ( .A0(n2271), .A1(n5049), .B0(n2205), .B1(n2272), .Y(n4540)
);
AOI22X1TS U3450 ( .A0(n2271), .A1(FPMULT_Op_MY[7]), .B0(n5040), .B1(n2273),
.Y(n3198) );
INVX2TS U3451 ( .A(n4575), .Y(n4574) );
AOI22X1TS U3452 ( .A0(n4575), .A1(n2350), .B0(n2352), .B1(n4574), .Y(n2690)
);
INVX2TS U3453 ( .A(n4572), .Y(n4571) );
AOI22X1TS U3454 ( .A0(n4572), .A1(n2350), .B0(n2352), .B1(n4571), .Y(n3703)
);
OAI22X1TS U3455 ( .A0(n4594), .A1(n2690), .B0(n4598), .B1(n3703), .Y(n2678)
);
CMPR32X2TS U3456 ( .A(FPMULT_Op_MX[4]), .B(FPMULT_Op_MX[16]), .C(n2672),
.CO(n2413), .S(n2675) );
NOR2X1TS U3457 ( .A(n2340), .B(n2675), .Y(n4599) );
INVX2TS U3458 ( .A(n2347), .Y(n4611) );
INVX2TS U3459 ( .A(n4566), .Y(n4565) );
AOI22X1TS U3460 ( .A0(n2356), .A1(n4565), .B0(n4566), .B1(n2276), .Y(n3701)
);
INVX2TS U3461 ( .A(n2675), .Y(n2693) );
OAI33X4TS U3462 ( .A0(n2317), .A1(n2693), .A2(n2357), .B0(n2276), .B1(n2675),
.B2(n2340), .Y(n4606) );
INVX2TS U3463 ( .A(n4606), .Y(n4608) );
INVX2TS U3464 ( .A(n4569), .Y(n4568) );
AOI22X1TS U3465 ( .A0(n2356), .A1(n4568), .B0(n4569), .B1(n2276), .Y(n4607)
);
OAI22X1TS U3466 ( .A0(n4611), .A1(n3701), .B0(n4608), .B1(n4607), .Y(n2677)
);
NAND2X1TS U3467 ( .A(n2677), .B(n2678), .Y(n3741) );
OA21XLTS U3468 ( .A0(n2678), .A1(n2677), .B0(n3741), .Y(
DP_OP_454J200_123_2743_n119) );
AOI22X1TS U3469 ( .A0(n2356), .A1(n4572), .B0(n4571), .B1(n2276), .Y(n4605)
);
AOI22X1TS U3470 ( .A0(n2356), .A1(n4575), .B0(n4574), .B1(n2355), .Y(n2732)
);
AOI22X1TS U3471 ( .A0(n2347), .A1(n4605), .B0(n4606), .B1(n2732), .Y(n2727)
);
NAND2X1TS U3472 ( .A(n2240), .B(n4612), .Y(n2680) );
OAI21X4TS U3473 ( .A0(n4634), .A1(n4612), .B0(n2680), .Y(n4632) );
INVX2TS U3474 ( .A(n4632), .Y(n3849) );
AOI22X1TS U3475 ( .A0(n2339), .A1(n4566), .B0(n4565), .B1(n2316), .Y(n4627)
);
AOI22X1TS U3476 ( .A0(n2339), .A1(n4569), .B0(n4568), .B1(n2316), .Y(n2730)
);
OAI32X4TS U3477 ( .A0(n2317), .A1(n2240), .A2(n4612), .B0(n2340), .B1(n2680),
.Y(n4629) );
AOI22X1TS U3478 ( .A0(n3849), .A1(n4627), .B0(n2730), .B1(n4629), .Y(n2728)
);
NOR2X1TS U3479 ( .A(n2727), .B(n2728), .Y(DP_OP_454J200_123_2743_n131) );
INVX2TS U3480 ( .A(n4578), .Y(n4577) );
AOI22X1TS U3481 ( .A0(n4578), .A1(n2355), .B0(n2357), .B1(n4577), .Y(n2731)
);
INVX2TS U3482 ( .A(n4581), .Y(n4580) );
AOI22X1TS U3483 ( .A0(n4581), .A1(n2355), .B0(n2357), .B1(n4580), .Y(n4610)
);
OAI22X1TS U3484 ( .A0(n4611), .A1(n2731), .B0(n4608), .B1(n4610), .Y(n2684)
);
INVX2TS U3485 ( .A(n4629), .Y(n4626) );
AOI22X1TS U3486 ( .A0(n2339), .A1(n4574), .B0(n4575), .B1(n2316), .Y(n4631)
);
AOI22X1TS U3487 ( .A0(n2339), .A1(n4571), .B0(n4572), .B1(n2316), .Y(n2729)
);
OAI22X1TS U3488 ( .A0(n4626), .A1(n4631), .B0(n4632), .B1(n2729), .Y(n2683)
);
NAND2X1TS U3489 ( .A(n2683), .B(n2684), .Y(n3765) );
OA21XLTS U3490 ( .A0(n2684), .A1(n2683), .B0(n3765), .Y(
DP_OP_454J200_123_2743_n142) );
AOI22X1TS U3491 ( .A0(n4578), .A1(n2340), .B0(n2316), .B1(n4577), .Y(n4630)
);
AOI22X1TS U3492 ( .A0(n4581), .A1(n2340), .B0(n2316), .B1(n4580), .Y(n3848)
);
AOI22X1TS U3493 ( .A0(n3849), .A1(n4630), .B0(n3848), .B1(n4629), .Y(n3864)
);
INVX2TS U3494 ( .A(n2209), .Y(n4636) );
NOR2X4TS U3495 ( .A(n4634), .B(n4636), .Y(n3846) );
INVX2TS U3496 ( .A(n3758), .Y(n3844) );
OAI22X1TS U3497 ( .A0(n4575), .A1(n2243), .B0(n4572), .B1(n3844), .Y(n2686)
);
AOI21X1TS U3498 ( .A0(n3846), .A1(n4572), .B0(n2686), .Y(n3865) );
NOR2X1TS U3499 ( .A(n3864), .B(n3865), .Y(DP_OP_454J200_123_2743_n148) );
AOI21X4TS U3500 ( .A0(FPMULT_Op_MX[14]), .A1(FPMULT_Op_MX[13]), .B0(n4102),
.Y(n4403) );
AOI22X1TS U3501 ( .A0(n2262), .A1(n2194), .B0(n5032), .B1(n2263), .Y(n2700)
);
INVX2TS U3502 ( .A(n4403), .Y(n4491) );
AOI32X4TS U3503 ( .A0(n2403), .A1(n4491), .A2(n5078), .B0(n4402), .B1(n4491),
.Y(n4486) );
INVX2TS U3504 ( .A(n4486), .Y(n4489) );
AOI22X1TS U3505 ( .A0(FPMULT_Op_MX[15]), .A1(n2203), .B0(n5046), .B1(n5027),
.Y(n2820) );
AO22XLTS U3506 ( .A0(n4403), .A1(n2700), .B0(n4489), .B1(n2820), .Y(
mult_x_219_n214) );
AOI22X1TS U3507 ( .A0(FPMULT_Op_MY[1]), .A1(n2277), .B0(n2309), .B1(n5043),
.Y(n4528) );
NAND2X1TS U3508 ( .A(n4955), .B(n5079), .Y(n4101) );
AOI221X4TS U3509 ( .A0(n2309), .A1(FPMULT_Op_MX[6]), .B0(n2278), .B1(n5079),
.C0(n4529), .Y(n4427) );
INVX2TS U3510 ( .A(n4427), .Y(n4524) );
AOI22X1TS U3511 ( .A0(FPMULT_Op_MY[2]), .A1(n2308), .B0(n2277), .B1(n5051),
.Y(n3200) );
OAI33X4TS U3512 ( .A0(FPMULT_Op_MX[10]), .A1(n2324), .A2(n2367), .B0(n5206),
.B1(n2280), .B2(n2365), .Y(n4509) );
NAND2X1TS U3513 ( .A(FPMULT_Op_MY[2]), .B(FPMULT_Op_MX[11]), .Y(n3750) );
OAI21X1TS U3514 ( .A0(FPMULT_Op_MY[2]), .A1(FPMULT_Op_MX[11]), .B0(n3750),
.Y(n4508) );
NOR2X1TS U3515 ( .A(FPMULT_Op_MX[10]), .B(n2324), .Y(n4103) );
INVX2TS U3516 ( .A(n4555), .Y(n2699) );
NOR2X1TS U3517 ( .A(n5041), .B(n2367), .Y(n4398) );
AOI21X1TS U3518 ( .A0(n5041), .A1(n2366), .B0(n4398), .Y(n4080) );
INVX2TS U3519 ( .A(n2363), .Y(n4395) );
AOI22X1TS U3520 ( .A0(FPMULT_Op_MY[14]), .A1(FPMULT_Op_MX[19]), .B0(n2299),
.B1(n5034), .Y(n3191) );
OAI221X4TS U3521 ( .A0(n2398), .A1(FPMULT_Op_MX[18]), .B0(n2299), .B1(n5054),
.C0(n2364), .Y(n4475) );
INVX2TS U3522 ( .A(n4475), .Y(n4478) );
AOI22X1TS U3523 ( .A0(FPMULT_Op_MY[13]), .A1(FPMULT_Op_MX[19]), .B0(n2299),
.B1(n4959), .Y(n4394) );
AO22XLTS U3524 ( .A0(n4395), .A1(n3191), .B0(n4478), .B1(n4394), .Y(
mult_x_219_n188) );
NOR2X1TS U3525 ( .A(n2270), .B(n2366), .Y(n4513) );
AOI21X1TS U3526 ( .A0(n2201), .A1(n2319), .B0(n5029), .Y(n2688) );
AOI22X1TS U3527 ( .A0(n2315), .A1(n5045), .B0(FPMULT_Op_MY[10]), .B1(n2273),
.Y(n4538) );
AOI22X1TS U3528 ( .A0(n2315), .A1(n5035), .B0(FPMULT_Op_MY[9]), .B1(n2273),
.Y(n4542) );
OAI22X1TS U3529 ( .A0(n4543), .A1(n4538), .B0(n4541), .B1(n4542), .Y(n2687)
);
CMPR32X2TS U3530 ( .A(n4513), .B(n2688), .C(n2687), .CO(mult_x_254_n98), .S(
mult_x_254_n99) );
NAND2X1TS U3531 ( .A(n2288), .B(n4406), .Y(n4449) );
AOI22X1TS U3532 ( .A0(FPMULT_Op_MY[21]), .A1(n3745), .B0(n2811), .B1(n5037),
.Y(n2689) );
AOI21X1TS U3533 ( .A0(n3821), .A1(n5031), .B0(n2689), .Y(n4451) );
AOI22X1TS U3534 ( .A0(n4578), .A1(n2351), .B0(n2350), .B1(n4577), .Y(n2726)
);
INVX2TS U3535 ( .A(n4594), .Y(n4595) );
NAND2X1TS U3536 ( .A(n2259), .B(n3203), .Y(n4504) );
NOR2X1TS U3537 ( .A(n2318), .B(n5035), .Y(n2692) );
AOI22X1TS U3538 ( .A0(n2368), .A1(n2318), .B0(n2692), .B1(n2399), .Y(n2691)
);
OAI21X1TS U3539 ( .A0(n2692), .A1(n2400), .B0(n2691), .Y(n4506) );
CMPR32X2TS U3540 ( .A(FPMULT_Op_MX[8]), .B(FPMULT_Op_MX[20]), .C(n2695),
.CO(n2799), .S(n2719) );
NAND2X1TS U3541 ( .A(n2352), .B(n2719), .Y(n3209) );
NAND2X1TS U3542 ( .A(n2327), .B(n3209), .Y(DP_OP_454J200_123_2743_n188) );
AOI22X1TS U3543 ( .A0(n2315), .A1(FPMULT_Op_MY[5]), .B0(n5038), .B1(n2273),
.Y(n2723) );
AO22XLTS U3544 ( .A0(n3199), .A1(n2723), .B0(n3197), .B1(n2696), .Y(
mult_x_254_n219) );
INVX2TS U3545 ( .A(n2247), .Y(n4511) );
NOR2X1TS U3546 ( .A(n2319), .B(n5047), .Y(n2698) );
AOI22X1TS U3547 ( .A0(FPMULT_Op_MY[10]), .A1(n2318), .B0(n2698), .B1(n2399),
.Y(n2697) );
OAI21X1TS U3548 ( .A0(n2698), .A1(n2400), .B0(n2697), .Y(n4503) );
AOI22X1TS U3549 ( .A0(FPMULT_Op_MY[6]), .A1(n2279), .B0(n2324), .B1(n5042),
.Y(n4518) );
AOI22X1TS U3550 ( .A0(FPMULT_Op_MY[5]), .A1(n2341), .B0(n2280), .B1(n5038),
.Y(n2708) );
NAND2X1TS U3551 ( .A(n2204), .B(FPMULT_Op_MX[11]), .Y(mult_x_254_n64) );
NAND2X1TS U3552 ( .A(n2205), .B(FPMULT_Op_MX[11]), .Y(mult_x_254_n38) );
AOI22X1TS U3553 ( .A0(n2262), .A1(FPMULT_Op_MY[17]), .B0(n5039), .B1(n5027),
.Y(n2717) );
AO22XLTS U3554 ( .A0(n4403), .A1(n2717), .B0(n4489), .B1(n2700), .Y(
mult_x_219_n213) );
OR2X1TS U3555 ( .A(n2380), .B(n2402), .Y(n4464) );
NAND2X1TS U3556 ( .A(n2402), .B(n2380), .Y(n4495) );
AOI22X1TS U3557 ( .A0(FPMULT_Op_MY[18]), .A1(n4931), .B0(n2401), .B1(n4961),
.Y(n4467) );
AOI22X1TS U3558 ( .A0(FPMULT_Op_MY[17]), .A1(n2401), .B0(n2331), .B1(n5039),
.Y(n2704) );
CLKBUFX2TS U3559 ( .A(n5196), .Y(n4018) );
INVX2TS U3560 ( .A(n4018), .Y(busy) );
BUFX3TS U3561 ( .A(n5357), .Y(n5343) );
BUFX3TS U3562 ( .A(n2701), .Y(n5267) );
BUFX3TS U3563 ( .A(n2701), .Y(n5271) );
BUFX3TS U3564 ( .A(n2701), .Y(n5272) );
BUFX3TS U3565 ( .A(n2701), .Y(n5274) );
BUFX3TS U3566 ( .A(n5357), .Y(n5344) );
BUFX3TS U3567 ( .A(n5357), .Y(n5350) );
BUFX3TS U3568 ( .A(n5357), .Y(n5355) );
BUFX3TS U3569 ( .A(n2701), .Y(n5266) );
AOI22X1TS U3570 ( .A0(n4406), .A1(n2704), .B0(n2703), .B1(n2702), .Y(n2714)
);
AOI22X1TS U3571 ( .A0(FPMULT_Op_MY[21]), .A1(n2306), .B0(n2297), .B1(n5037),
.Y(n4482) );
OAI33X4TS U3572 ( .A0(n2403), .A1(FPMULT_Op_MX[16]), .A2(n2298), .B0(n2263),
.B1(n5080), .B2(n2307), .Y(n4481) );
AOI22X1TS U3573 ( .A0(FPMULT_Op_MY[20]), .A1(n2306), .B0(n2297), .B1(n5031),
.Y(n4436) );
AOI22X1TS U3574 ( .A0(n2348), .A1(n4482), .B0(n4481), .B1(n4436), .Y(n2713)
);
INVX2TS U3575 ( .A(n2705), .Y(mult_x_219_n89) );
NOR2X2TS U3576 ( .A(n5043), .B(n4926), .Y(n4507) );
AOI22X1TS U3577 ( .A0(n3203), .A1(n2708), .B0(n2707), .B1(n2706), .Y(n2711)
);
AOI22X1TS U3578 ( .A0(FPMULT_Op_MY[9]), .A1(FPMULT_Op_MX[5]), .B0(n2291),
.B1(n5035), .Y(n4534) );
AOI221X4TS U3579 ( .A0(FPMULT_Op_MX[4]), .A1(n2290), .B0(n5119), .B1(n2291),
.C0(n2266), .Y(n4533) );
AOI22X1TS U3580 ( .A0(n2368), .A1(FPMULT_Op_MX[5]), .B0(n2291), .B1(n5049),
.Y(n4425) );
AOI22X1TS U3581 ( .A0(n2266), .A1(n4534), .B0(n4533), .B1(n4425), .Y(n2710)
);
INVX2TS U3582 ( .A(n2709), .Y(mult_x_254_n89) );
CMPR32X2TS U3583 ( .A(n4507), .B(n2711), .C(n2710), .CO(n2709), .S(n2712) );
INVX2TS U3584 ( .A(n2712), .Y(mult_x_254_n90) );
CMPR32X2TS U3585 ( .A(FPMULT_Op_MY[13]), .B(n2714), .C(n2713), .CO(n2705),
.S(n2715) );
INVX2TS U3586 ( .A(n2715), .Y(mult_x_219_n90) );
AOI22X1TS U3587 ( .A0(FPMULT_Op_MY[20]), .A1(n3745), .B0(n2811), .B1(n5031),
.Y(n2716) );
AOI21X1TS U3588 ( .A0(n3821), .A1(n5033), .B0(n2716), .Y(n3735) );
AOI22X1TS U3589 ( .A0(FPMULT_Op_MX[15]), .A1(FPMULT_Op_MY[18]), .B0(n4961),
.B1(n5027), .Y(n3190) );
AOI22X1TS U3590 ( .A0(n4403), .A1(n3190), .B0(n4489), .B1(n2717), .Y(n3734)
);
INVX2TS U3591 ( .A(n2718), .Y(mult_x_219_n125) );
OAI21X1TS U3592 ( .A0(n2352), .A1(n2719), .B0(n3209), .Y(n3208) );
NOR2X1TS U3593 ( .A(n2256), .B(n3208), .Y(DP_OP_454J200_123_2743_n200) );
NOR2XLTS U3594 ( .A(DP_OP_454J200_123_2743_n200), .B(
DP_OP_454J200_123_2743_n188), .Y(DP_OP_454J200_123_2743_n155) );
INVX2TS U3595 ( .A(n4495), .Y(n2722) );
INVX2TS U3596 ( .A(n3745), .Y(n2720) );
AOI21X1TS U3597 ( .A0(n3821), .A1(n4960), .B0(n2720), .Y(n2721) );
NOR3X2TS U3598 ( .A(n2722), .B(n2721), .C(mult_x_219_n162), .Y(
mult_x_219_n106) );
OAI32X1TS U3599 ( .A0(mult_x_219_n106), .A1(n2722), .A2(mult_x_219_n162),
.B0(n2721), .B1(mult_x_219_n106), .Y(mult_x_219_n107) );
AOI22X1TS U3600 ( .A0(n2315), .A1(FPMULT_Op_MY[6]), .B0(n5042), .B1(n2273),
.Y(n3196) );
AOI22X1TS U3601 ( .A0(n3199), .A1(n3196), .B0(n3197), .B1(n2723), .Y(n3747)
);
AOI22X1TS U3602 ( .A0(n2237), .A1(n2205), .B0(FPMULT_Op_MY[7]), .B1(n2319),
.Y(n2724) );
INVX2TS U3603 ( .A(n2725), .Y(mult_x_254_n125) );
AOI22X1TS U3604 ( .A0(n4581), .A1(n2351), .B0(n2350), .B1(n4580), .Y(n4416)
);
AOI22X1TS U3605 ( .A0(n4417), .A1(n2726), .B0(n4416), .B1(n4595), .Y(n3728)
);
AO21XLTS U3606 ( .A0(n2728), .A1(n2727), .B0(DP_OP_454J200_123_2743_n131),
.Y(n3727) );
AOI2BB2XLTS U3607 ( .B0(n3849), .B1(n2730), .A0N(n4626), .A1N(n2729), .Y(
n3764) );
AOI2BB2XLTS U3608 ( .B0(n2347), .B1(n2732), .A0N(n4608), .A1N(n2731), .Y(
n3763) );
INVX2TS U3609 ( .A(n2733), .Y(DP_OP_454J200_123_2743_n129) );
NOR3X1TS U3610 ( .A(n2734), .B(n2258), .C(mult_x_254_n211), .Y(n2741) );
AOI2BB1X1TS U3611 ( .A0N(n3824), .A1N(n2735), .B0(n2741), .Y(n2739) );
INVX2TS U3612 ( .A(n2736), .Y(n2738) );
OAI31X1TS U3613 ( .A0(n2742), .A1(n2739), .A2(n2738), .B0(n2737), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N3) );
OAI21X2TS U3614 ( .A0(n2272), .A1(n5119), .B0(FPMULT_Op_MX[5]), .Y(
mult_x_254_n197) );
AOI22X1TS U3615 ( .A0(n2237), .A1(FPMULT_Op_MY[5]), .B0(n2204), .B1(n2319),
.Y(n2740) );
NOR3BX1TS U3616 ( .AN(n2752), .B(n2746), .C(mult_x_254_n197), .Y(
mult_x_254_n136) );
INVX2TS U3617 ( .A(mult_x_254_n116), .Y(n2764) );
INVX2TS U3618 ( .A(mult_x_254_n127), .Y(n2779) );
INVX2TS U3619 ( .A(mult_x_254_n123), .Y(n2778) );
INVX2TS U3620 ( .A(mult_x_254_n132), .Y(n2761) );
INVX2TS U3621 ( .A(mult_x_254_n128), .Y(n2760) );
INVX2TS U3622 ( .A(mult_x_254_n133), .Y(n2789) );
NAND2X1TS U3623 ( .A(n2742), .B(n2741), .Y(n2744) );
NAND2X1TS U3624 ( .A(n2744), .B(n2743), .Y(n4368) );
NAND2BXLTS U3625 ( .AN(mult_x_254_n197), .B(n2752), .Y(n2745) );
AOI21X1TS U3626 ( .A0(n2746), .A1(n2745), .B0(mult_x_254_n136), .Y(n4367) );
AOI22X1TS U3627 ( .A0(FPMULT_Op_MY[1]), .A1(FPMULT_Op_MX[5]), .B0(n2291),
.B1(n5043), .Y(n4081) );
INVX2TS U3628 ( .A(n2266), .Y(n4536) );
AOI22X1TS U3629 ( .A0(n2266), .A1(n4081), .B0(n2747), .B1(n4536), .Y(n2757)
);
AOI22X1TS U3630 ( .A0(n3199), .A1(n2749), .B0(n3197), .B1(n2748), .Y(n2756)
);
CMPR32X2TS U3631 ( .A(n2752), .B(n2751), .C(n2750), .CO(n2755), .S(n2426) );
INVX2TS U3632 ( .A(n2753), .Y(n4366) );
INVX2TS U3633 ( .A(n2754), .Y(n2788) );
CMPR32X2TS U3634 ( .A(n2757), .B(n2756), .C(n2755), .CO(n2787), .S(n2753) );
INVX2TS U3635 ( .A(n2758), .Y(FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N9)
);
CMPR32X2TS U3636 ( .A(n2761), .B(n2760), .C(n2759), .CO(n2777), .S(n2762) );
INVX2TS U3637 ( .A(n2762), .Y(FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N7)
);
INVX2TS U3638 ( .A(mult_x_254_n32), .Y(n4548) );
INVX2TS U3639 ( .A(mult_x_254_n31), .Y(n4551) );
AOI22X1TS U3640 ( .A0(n2236), .A1(FPMULT_Op_MX[11]), .B0(n4926), .B1(n5047),
.Y(n4387) );
AOI22X1TS U3641 ( .A0(FPMULT_Op_MX[11]), .A1(n2247), .B0(n2233), .B1(n4387),
.Y(n4550) );
NOR2X1TS U3642 ( .A(n5045), .B(n2367), .Y(n4549) );
INVX2TS U3643 ( .A(mult_x_254_n33), .Y(n2783) );
INVX2TS U3644 ( .A(mult_x_254_n35), .Y(n2782) );
INVX2TS U3645 ( .A(mult_x_254_n36), .Y(n3577) );
INVX2TS U3646 ( .A(mult_x_254_n40), .Y(n3576) );
INVX2TS U3647 ( .A(mult_x_254_n41), .Y(n3664) );
INVX2TS U3648 ( .A(mult_x_254_n45), .Y(n3663) );
INVX2TS U3649 ( .A(mult_x_254_n52), .Y(n3683) );
INVX2TS U3650 ( .A(mult_x_254_n46), .Y(n3682) );
INVX2TS U3651 ( .A(mult_x_254_n58), .Y(n2797) );
INVX2TS U3652 ( .A(mult_x_254_n53), .Y(n2796) );
INVX2TS U3653 ( .A(mult_x_254_n66), .Y(n3653) );
INVX2TS U3654 ( .A(mult_x_254_n59), .Y(n3652) );
INVX2TS U3655 ( .A(mult_x_254_n74), .Y(n3068) );
INVX2TS U3656 ( .A(mult_x_254_n67), .Y(n3067) );
INVX2TS U3657 ( .A(mult_x_254_n84), .Y(n2769) );
INVX2TS U3658 ( .A(mult_x_254_n75), .Y(n2768) );
INVX2TS U3659 ( .A(mult_x_254_n93), .Y(n3679) );
INVX2TS U3660 ( .A(mult_x_254_n85), .Y(n3678) );
INVX2TS U3661 ( .A(mult_x_254_n101), .Y(n2803) );
INVX2TS U3662 ( .A(mult_x_254_n94), .Y(n2802) );
INVX2TS U3663 ( .A(mult_x_254_n109), .Y(n2775) );
INVX2TS U3664 ( .A(mult_x_254_n102), .Y(n2774) );
INVX2TS U3665 ( .A(mult_x_254_n115), .Y(n2793) );
INVX2TS U3666 ( .A(mult_x_254_n110), .Y(n2792) );
CMPR32X2TS U3667 ( .A(n2765), .B(n2764), .C(n2763), .CO(n2791), .S(n2758) );
INVX2TS U3668 ( .A(n2766), .Y(FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N22) );
CMPR32X2TS U3669 ( .A(n2769), .B(n2768), .C(n2767), .CO(n3066), .S(n2770) );
INVX2TS U3670 ( .A(n2770), .Y(FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N14) );
AOI22X1TS U3671 ( .A0(n2209), .A1(n4584), .B0(n2240), .B1(n4587), .Y(n2771)
);
AOI31XLTS U3672 ( .A0(n4584), .A1(n2209), .A2(n2772), .B0(n2771), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N1) );
CMPR32X2TS U3673 ( .A(n2775), .B(n2774), .C(n2773), .CO(n2801), .S(n2776) );
INVX2TS U3674 ( .A(n2776), .Y(FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N11) );
CMPR32X2TS U3675 ( .A(n2779), .B(n2778), .C(n2777), .CO(n2763), .S(n2780) );
INVX2TS U3676 ( .A(n2780), .Y(FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N8)
);
CMPR32X2TS U3677 ( .A(n2783), .B(n2782), .C(n2781), .CO(n4546), .S(n2784) );
INVX2TS U3678 ( .A(n2784), .Y(FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N21) );
INVX2TS U3679 ( .A(n2328), .Y(n3275) );
NAND2X1TS U3680 ( .A(n3216), .B(FPMULT_P_Sgf[32]), .Y(n3431) );
AOI2BB2XLTS U3681 ( .B0(FPMULT_Sgf_normalized_result[9]), .B1(n2345), .A0N(
n3133), .A1N(n3431), .Y(n2786) );
INVX2TS U3682 ( .A(n2241), .Y(n3391) );
AOI22X1TS U3683 ( .A0(FPMULT_Add_result[10]), .A1(n3391), .B0(
FPMULT_P_Sgf[33]), .B1(n2370), .Y(n2785) );
OAI211XLTS U3684 ( .A0(n5111), .A1(n3275), .B0(n2786), .C0(n2785), .Y(n1514)
);
CMPR32X2TS U3685 ( .A(n2789), .B(n2788), .C(n2787), .CO(n2759), .S(n2790) );
INVX2TS U3686 ( .A(n2790), .Y(FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N6)
);
CMPR32X2TS U3687 ( .A(n2793), .B(n2792), .C(n2791), .CO(n2773), .S(n2794) );
INVX2TS U3688 ( .A(n2794), .Y(FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N10) );
CMPR32X2TS U3689 ( .A(n2797), .B(n2796), .C(n2795), .CO(n3681), .S(n2798) );
INVX2TS U3690 ( .A(n2798), .Y(FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N17) );
NAND2X1TS U3691 ( .A(n2327), .B(n3858), .Y(n3859) );
NOR2X1TS U3692 ( .A(n2256), .B(n2282), .Y(DP_OP_454J200_123_2743_n187) );
NOR2X1TS U3693 ( .A(n4632), .B(n2257), .Y(n3835) );
AOI22X1TS U3694 ( .A0(n4581), .A1(n3846), .B0(n3758), .B1(n4580), .Y(n2800)
);
OAI21X1TS U3695 ( .A0(n4584), .A1(n2243), .B0(n2800), .Y(n3836) );
CMPR32X2TS U3696 ( .A(n2803), .B(n2802), .C(n2801), .CO(n3677), .S(n2804) );
INVX2TS U3697 ( .A(n2804), .Y(FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N12) );
NOR2XLTS U3698 ( .A(n4636), .B(n2257), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N0) );
OAI21X1TS U3699 ( .A0(n4962), .A1(n5078), .B0(FPMULT_Op_MX[15]), .Y(
mult_x_219_n205) );
INVX2TS U3700 ( .A(mult_x_219_n33), .Y(n3649) );
INVX2TS U3701 ( .A(mult_x_219_n35), .Y(n3648) );
INVX2TS U3702 ( .A(mult_x_219_n36), .Y(n2832) );
INVX2TS U3703 ( .A(mult_x_219_n40), .Y(n2831) );
INVX2TS U3704 ( .A(mult_x_219_n41), .Y(n3675) );
INVX2TS U3705 ( .A(mult_x_219_n45), .Y(n3674) );
INVX2TS U3706 ( .A(mult_x_219_n52), .Y(n2836) );
INVX2TS U3707 ( .A(mult_x_219_n46), .Y(n2835) );
INVX2TS U3708 ( .A(mult_x_219_n58), .Y(n3659) );
INVX2TS U3709 ( .A(mult_x_219_n53), .Y(n3658) );
INVX2TS U3710 ( .A(mult_x_219_n66), .Y(n2840) );
INVX2TS U3711 ( .A(mult_x_219_n59), .Y(n2839) );
INVX2TS U3712 ( .A(mult_x_219_n74), .Y(n3668) );
INVX2TS U3713 ( .A(mult_x_219_n67), .Y(n3667) );
INVX2TS U3714 ( .A(mult_x_219_n84), .Y(n2844) );
INVX2TS U3715 ( .A(mult_x_219_n75), .Y(n2843) );
INVX2TS U3716 ( .A(mult_x_219_n93), .Y(n2848) );
INVX2TS U3717 ( .A(mult_x_219_n85), .Y(n2847) );
INVX2TS U3718 ( .A(mult_x_219_n94), .Y(n3641) );
INVX2TS U3719 ( .A(mult_x_219_n109), .Y(n3608) );
INVX2TS U3720 ( .A(mult_x_219_n102), .Y(n3607) );
INVX2TS U3721 ( .A(mult_x_219_n115), .Y(n3602) );
INVX2TS U3722 ( .A(mult_x_219_n110), .Y(n3601) );
INVX2TS U3723 ( .A(mult_x_219_n122), .Y(n3596) );
INVX2TS U3724 ( .A(mult_x_219_n116), .Y(n3595) );
INVX2TS U3725 ( .A(mult_x_219_n127), .Y(n3590) );
INVX2TS U3726 ( .A(mult_x_219_n123), .Y(n3589) );
INVX2TS U3727 ( .A(mult_x_219_n132), .Y(n3584) );
AO21XLTS U3728 ( .A0(n2207), .A1(n2288), .B0(mult_x_219_n191), .Y(n2805) );
AO21XLTS U3729 ( .A0(n2806), .A1(n2805), .B0(mult_x_219_n136), .Y(n3076) );
AOI22X1TS U3730 ( .A0(FPMULT_Op_MX[12]), .A1(n2203), .B0(FPMULT_Op_MX[13]),
.B1(n5034), .Y(n2807) );
AOI22X1TS U3731 ( .A0(n4401), .A1(n2203), .B0(n2807), .B1(n2811), .Y(n2813)
);
AOI22X1TS U3732 ( .A0(n2262), .A1(n4959), .B0(FPMULT_Op_MY[13]), .B1(n5027),
.Y(n2810) );
AOI22X1TS U3733 ( .A0(n4403), .A1(n2810), .B0(n2808), .B1(n4491), .Y(n2814)
);
NAND2X1TS U3734 ( .A(n2813), .B(n2814), .Y(n3829) );
NAND2X1TS U3735 ( .A(FPMULT_Op_MX[12]), .B(FPMULT_Op_MY[13]), .Y(n4447) );
AOI32X1TS U3736 ( .A0(FPMULT_Op_MX[13]), .A1(n2261), .A2(n4447), .B0(n4403),
.B1(n2288), .Y(n4445) );
AOI22X1TS U3737 ( .A0(FPMULT_Op_MX[13]), .A1(FPMULT_Op_MY[14]), .B0(n5034),
.B1(n4962), .Y(n2809) );
AOI22X1TS U3738 ( .A0(FPMULT_Op_MX[12]), .A1(n2809), .B0(n3821), .B1(n4959),
.Y(n4446) );
AOI2BB1X1TS U3739 ( .A0N(n2261), .A1N(n4102), .B0(mult_x_219_n205), .Y(n2815) );
NAND2X1TS U3740 ( .A(n4444), .B(n2815), .Y(n3827) );
NOR2X1TS U3741 ( .A(n3829), .B(n3827), .Y(n2818) );
NAND2X1TS U3742 ( .A(n2288), .B(n2348), .Y(n2823) );
AOI22X1TS U3743 ( .A0(n2403), .A1(FPMULT_Op_MY[14]), .B0(n5034), .B1(n2263),
.Y(n2819) );
AOI2BB2XLTS U3744 ( .B0(n4403), .B1(n2819), .A0N(n2810), .A1N(n4486), .Y(
n2822) );
AOI22X1TS U3745 ( .A0(n2194), .A1(n3745), .B0(n2811), .B1(n5032), .Y(n2812)
);
AOI21X1TS U3746 ( .A0(n3821), .A1(n5046), .B0(n2812), .Y(n2821) );
OR2X1TS U3747 ( .A(n2814), .B(n2813), .Y(n3830) );
INVX2TS U3748 ( .A(n2818), .Y(n2817) );
INVX2TS U3749 ( .A(n3829), .Y(n2816) );
AOI32X1TS U3750 ( .A0(n3830), .A1(n2817), .A2(n3828), .B0(n2816), .B1(n2817),
.Y(n4442) );
NOR2X1TS U3751 ( .A(n4443), .B(n4442), .Y(n4441) );
NOR2XLTS U3752 ( .A(n2818), .B(n4441), .Y(n3075) );
AOI22X1TS U3753 ( .A0(n4403), .A1(n2820), .B0(n4489), .B1(n2819), .Y(n2827)
);
CMPR32X2TS U3754 ( .A(n2823), .B(n2822), .C(n2821), .CO(n2826), .S(n4443) );
AOI22X1TS U3755 ( .A0(FPMULT_Op_MY[13]), .A1(n2306), .B0(n2298), .B1(n4959),
.Y(n4078) );
INVX2TS U3756 ( .A(n2348), .Y(n4484) );
AOI22X1TS U3757 ( .A0(n2348), .A1(n4078), .B0(n2824), .B1(n4484), .Y(n2825)
);
CMPR32X2TS U3758 ( .A(n2827), .B(n2826), .C(n2825), .CO(n3070), .S(n3074) );
INVX2TS U3759 ( .A(mult_x_219_n31), .Y(n4492) );
AOI22X1TS U3760 ( .A0(n2379), .A1(mult_x_219_n31), .B0(n4492), .B1(n4960),
.Y(n2828) );
XNOR2X1TS U3761 ( .A(n2283), .B(n2828), .Y(n4497) );
INVX2TS U3762 ( .A(n2829), .Y(FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N22)
);
CMPR32X2TS U3763 ( .A(n2832), .B(n2831), .C(n2830), .CO(n3647), .S(n2833) );
INVX2TS U3764 ( .A(n2833), .Y(FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N20)
);
CMPR32X2TS U3765 ( .A(n2836), .B(n2835), .C(n2834), .CO(n3673), .S(n2837) );
INVX2TS U3766 ( .A(n2837), .Y(FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N18)
);
CMPR32X2TS U3767 ( .A(n2840), .B(n2839), .C(n2838), .CO(n3657), .S(n2841) );
INVX2TS U3768 ( .A(n2841), .Y(FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N16)
);
CMPR32X2TS U3769 ( .A(n2844), .B(n2843), .C(n2842), .CO(n3666), .S(n2845) );
INVX2TS U3770 ( .A(n2845), .Y(FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N14)
);
CMPR32X2TS U3771 ( .A(n2848), .B(n2847), .C(n2846), .CO(n2842), .S(n2849) );
INVX2TS U3772 ( .A(n2849), .Y(FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N13)
);
AOI2BB2X2TS U3773 ( .B0(FPADDSUB_DMP_SFG[21]), .B1(n5075), .A0N(n5075),
.A1N(FPADDSUB_DMP_SFG[21]), .Y(n2853) );
OAI21X1TS U3774 ( .A0(FPADDSUB_DMP_SFG[20]), .A1(n5074), .B0(n2850), .Y(
n2851) );
NAND2X1TS U3775 ( .A(n2853), .B(n2851), .Y(n2917) );
AOI21X1TS U3776 ( .A0(FPADDSUB_DMP_SFG[20]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[22]), .B0(n2852), .Y(n2854) );
NOR2X1TS U3777 ( .A(n2853), .B(n2854), .Y(n2918) );
AOI211X1TS U3778 ( .A0(n2854), .A1(n2853), .B0(n2918), .C0(n2322), .Y(n2855)
);
AOI21X1TS U3779 ( .A0(n4040), .A1(n2856), .B0(n2855), .Y(n2857) );
OAI21XLTS U3780 ( .A0(n4312), .A1(n4929), .B0(n2857), .Y(n1316) );
OAI21X1TS U3781 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B0(n4121), .Y(n4122) );
CLKBUFX2TS U3782 ( .A(n2859), .Y(n4087) );
AND3X2TS U3783 ( .A(FPSENCOS_cont_var_out[0]), .B(n4323), .C(n5053), .Y(
n4174) );
CLKBUFX3TS U3784 ( .A(n4174), .Y(n4159) );
INVX2TS U3785 ( .A(n4159), .Y(n3372) );
CLKBUFX3TS U3786 ( .A(n2859), .Y(n3354) );
AOI22X1TS U3787 ( .A0(FPADDSUB_intDX_EWSW[8]), .A1(n3354), .B0(n2860), .B1(
Data_1[8]), .Y(n2865) );
INVX2TS U3788 ( .A(n4323), .Y(n2862) );
NAND2X1TS U3789 ( .A(FPSENCOS_cont_var_out[0]), .B(FPSENCOS_cont_var_out[1]),
.Y(n4670) );
CLKBUFX3TS U3790 ( .A(n2861), .Y(n3355) );
NOR3XLTS U3791 ( .A(FPSENCOS_cont_var_out[0]), .B(n2862), .C(n5053), .Y(
n2863) );
CLKBUFX3TS U3792 ( .A(n4115), .Y(n3369) );
AOI22X1TS U3793 ( .A0(n3355), .A1(FPSENCOS_d_ff2_Z[8]), .B0(n3369), .B1(
FPSENCOS_d_ff2_Y[8]), .Y(n2864) );
OAI211XLTS U3794 ( .A0(n3372), .A1(n5226), .B0(n2865), .C0(n2864), .Y(n1933)
);
NOR4X1TS U3795 ( .A(FPMULT_P_Sgf[17]), .B(FPMULT_P_Sgf[13]), .C(
FPMULT_P_Sgf[15]), .D(FPMULT_P_Sgf[16]), .Y(n2874) );
NOR4X1TS U3796 ( .A(FPMULT_P_Sgf[21]), .B(FPMULT_P_Sgf[20]), .C(
FPMULT_P_Sgf[19]), .D(FPMULT_P_Sgf[18]), .Y(n2873) );
NOR4X1TS U3797 ( .A(FPMULT_P_Sgf[1]), .B(FPMULT_P_Sgf[5]), .C(
FPMULT_P_Sgf[3]), .D(FPMULT_P_Sgf[4]), .Y(n2869) );
NOR3XLTS U3798 ( .A(FPMULT_P_Sgf[22]), .B(FPMULT_P_Sgf[2]), .C(
FPMULT_P_Sgf[0]), .Y(n2868) );
NOR4X1TS U3799 ( .A(FPMULT_P_Sgf[14]), .B(FPMULT_P_Sgf[9]), .C(
FPMULT_P_Sgf[10]), .D(FPMULT_P_Sgf[12]), .Y(n2867) );
NOR4X1TS U3800 ( .A(FPMULT_P_Sgf[8]), .B(FPMULT_P_Sgf[6]), .C(
FPMULT_P_Sgf[7]), .D(FPMULT_P_Sgf[11]), .Y(n2866) );
AND4X1TS U3801 ( .A(n2869), .B(n2868), .C(n2867), .D(n2866), .Y(n2872) );
XOR2X1TS U3802 ( .A(FPMULT_Op_MY[31]), .B(FPMULT_Op_MX[31]), .Y(n4747) );
MXI2X1TS U3803 ( .A(r_mode[0]), .B(r_mode[1]), .S0(n4747), .Y(n2870) );
OAI21XLTS U3804 ( .A0(r_mode[1]), .A1(r_mode[0]), .B0(n2870), .Y(n2871) );
AOI31X1TS U3805 ( .A0(n2874), .A1(n2873), .A2(n2872), .B0(n2871), .Y(n3892)
);
AOI31XLTS U3806 ( .A0(n4936), .A1(n2875), .A2(n3892), .B0(
FPMULT_FSM_selector_C), .Y(n2876) );
INVX2TS U3807 ( .A(n2876), .Y(n1528) );
CLKBUFX2TS U3808 ( .A(n2860), .Y(n3353) );
AOI22X1TS U3809 ( .A0(FPADDSUB_intDX_EWSW[1]), .A1(n3368), .B0(n3157), .B1(
Data_1[1]), .Y(n2878) );
CLKBUFX3TS U3810 ( .A(n2861), .Y(n4050) );
AOI22X1TS U3811 ( .A0(n4050), .A1(FPSENCOS_d_ff2_Z[1]), .B0(n3369), .B1(
FPSENCOS_d_ff2_Y[1]), .Y(n2877) );
AOI22X1TS U3812 ( .A0(FPADDSUB_intDX_EWSW[9]), .A1(n3354), .B0(n3353), .B1(
Data_1[9]), .Y(n2880) );
AOI22X1TS U3813 ( .A0(n3355), .A1(FPSENCOS_d_ff2_Z[9]), .B0(n3369), .B1(
FPSENCOS_d_ff2_Y[9]), .Y(n2879) );
OAI211XLTS U3814 ( .A0(n3372), .A1(n5227), .B0(n2880), .C0(n2879), .Y(n1932)
);
INVX2TS U3815 ( .A(n4316), .Y(n3376) );
CLKBUFX3TS U3816 ( .A(n4087), .Y(n3385) );
CLKBUFX3TS U3817 ( .A(n3353), .Y(n3384) );
AOI22X1TS U3818 ( .A0(FPADDSUB_intDX_EWSW[17]), .A1(n3385), .B0(n3384), .B1(
Data_1[17]), .Y(n2882) );
CLKBUFX3TS U3819 ( .A(n2861), .Y(n3387) );
CLKBUFX3TS U3820 ( .A(n3899), .Y(n3373) );
AOI22X1TS U3821 ( .A0(n3387), .A1(FPSENCOS_d_ff2_Z[17]), .B0(n3373), .B1(
FPSENCOS_d_ff2_Y[17]), .Y(n2881) );
OAI211XLTS U3822 ( .A0(n3376), .A1(n5161), .B0(n2882), .C0(n2881), .Y(n1924)
);
CLKBUFX2TS U3823 ( .A(n2860), .Y(n3157) );
AOI22X1TS U3824 ( .A0(FPADDSUB_intDX_EWSW[5]), .A1(n3354), .B0(n3157), .B1(
Data_1[5]), .Y(n2884) );
AOI22X1TS U3825 ( .A0(n3355), .A1(FPSENCOS_d_ff2_Z[5]), .B0(n3369), .B1(
FPSENCOS_d_ff2_Y[5]), .Y(n2883) );
OAI211XLTS U3826 ( .A0(n3372), .A1(n5153), .B0(n2884), .C0(n2883), .Y(n1936)
);
AOI21X1TS U3827 ( .A0(n2887), .A1(n2886), .B0(n2885), .Y(n2893) );
AOI211X1TS U3828 ( .A0(n2890), .A1(n2889), .B0(n2888), .C0(n2322), .Y(n2891)
);
AOI21X1TS U3829 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[14]), .A1(n4867), .B0(n2891),
.Y(n2892) );
OAI21XLTS U3830 ( .A0(n2893), .A1(n2394), .B0(n2892), .Y(n1335) );
INVX2TS U3831 ( .A(n4159), .Y(n3346) );
CLKBUFX3TS U3832 ( .A(n3368), .Y(n4322) );
CLKBUFX3TS U3833 ( .A(n3157), .Y(n4321) );
AOI22X1TS U3834 ( .A0(FPADDSUB_intDY_EWSW[25]), .A1(n4322), .B0(n4321), .B1(
Data_2[25]), .Y(n2895) );
CLKBUFX3TS U3835 ( .A(n2861), .Y(n3411) );
AOI22X1TS U3836 ( .A0(n3411), .A1(FPSENCOS_d_ff3_LUT_out[25]), .B0(n4115),
.B1(FPSENCOS_d_ff3_sh_x_out[25]), .Y(n2894) );
OAI211XLTS U3837 ( .A0(n3346), .A1(n5247), .B0(n2895), .C0(n2894), .Y(n1818)
);
INVX2TS U3838 ( .A(n4670), .Y(n2896) );
INVX2TS U3839 ( .A(n4159), .Y(n3390) );
AOI22X1TS U3840 ( .A0(FPADDSUB_intDX_EWSW[23]), .A1(n3385), .B0(n3384), .B1(
Data_1[23]), .Y(n2898) );
CLKBUFX3TS U3841 ( .A(n4115), .Y(n3386) );
AOI22X1TS U3842 ( .A0(n3387), .A1(FPSENCOS_d_ff2_Z[23]), .B0(n3386), .B1(
FPSENCOS_d_ff2_Y[23]), .Y(n2897) );
OAI211XLTS U3843 ( .A0(n3390), .A1(n5118), .B0(n2898), .C0(n2897), .Y(n1918)
);
OR3X1TS U3844 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .Y(n2900) );
NAND4BBX1TS U3845 ( .AN(n2900), .BN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .C(n2899), .D(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .Y(n4045) );
NAND4BBX1TS U3846 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .BN(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .D(n2901), .Y(n4114) );
NAND2X1TS U3847 ( .A(n4045), .B(n4114), .Y(n3923) );
INVX2TS U3848 ( .A(n4320), .Y(n4363) );
INVX2TS U3849 ( .A(operation[0]), .Y(n2902) );
OAI32X1TS U3850 ( .A0(n4363), .A1(n2902), .A2(n4046), .B0(n4954), .B1(n4320),
.Y(n2080) );
OAI21XLTS U3851 ( .A0(n2906), .A1(n2904), .B0(n2903), .Y(n2909) );
AOI211X1TS U3852 ( .A0(n2907), .A1(n2906), .B0(n2905), .C0(n2322), .Y(n2908)
);
AOI21X1TS U3853 ( .A0(n4040), .A1(n2909), .B0(n2908), .Y(n2910) );
CLKAND2X2TS U3854 ( .A(FPMULT_P_Sgf[44]), .B(n3216), .Y(n2911) );
AOI22X1TS U3855 ( .A0(n2911), .A1(n2388), .B0(
FPMULT_Sgf_normalized_result[21]), .B1(n2314), .Y(n2913) );
AOI22X1TS U3856 ( .A0(FPMULT_P_Sgf[45]), .A1(n2369), .B0(
FPMULT_Add_result[22]), .B1(n2393), .Y(n2912) );
OAI211XLTS U3857 ( .A0(n5089), .A1(n3275), .B0(n2913), .C0(n2912), .Y(n1526)
);
CLKAND2X2TS U3858 ( .A(FPMULT_P_Sgf[45]), .B(n3216), .Y(n2914) );
AOI22X1TS U3859 ( .A0(n2914), .A1(n2388), .B0(
FPMULT_Sgf_normalized_result[22]), .B1(n2345), .Y(n2916) );
AOI22X1TS U3860 ( .A0(FPMULT_P_Sgf[46]), .A1(n2369), .B0(
FPMULT_Add_result[22]), .B1(n2328), .Y(n2915) );
OAI211XLTS U3861 ( .A0(n5018), .A1(n2242), .B0(n2916), .C0(n2915), .Y(n1527)
);
AOI2BB2XLTS U3862 ( .B0(n2919), .B1(n2343), .A0N(n2343), .A1N(n2919), .Y(
n2923) );
AOI21X1TS U3863 ( .A0(FPADDSUB_DMP_SFG[21]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[23]), .B0(n2918), .Y(n2920) );
NOR2X1TS U3864 ( .A(n2919), .B(n2920), .Y(n4188) );
AOI21X1TS U3865 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[24]), .A1(n4846), .B0(n2921),
.Y(n2922) );
OAI21XLTS U3866 ( .A0(n3321), .A1(n2923), .B0(n2922), .Y(n1315) );
AOI22X1TS U3867 ( .A0(FPMULT_Sgf_normalized_result[19]), .A1(n2314), .B0(
FPMULT_Add_result[20]), .B1(n2393), .Y(n2925) );
INVX2TS U3868 ( .A(n3965), .Y(n3393) );
OAI221XLTS U3869 ( .A0(n3394), .A1(FPMULT_P_Sgf[43]), .B0(n3393), .B1(
FPMULT_P_Sgf[42]), .C0(n2388), .Y(n2924) );
OAI211XLTS U3870 ( .A0(n3275), .A1(n5115), .B0(n2925), .C0(n2924), .Y(n1524)
);
CLKBUFX3TS U3871 ( .A(n5023), .Y(n4889) );
NOR2X1TS U3872 ( .A(FPADDSUB_intDX_EWSW[29]), .B(n4979), .Y(n2959) );
AO22XLTS U3873 ( .A0(n5197), .A1(FPADDSUB_intDY_EWSW[28]), .B0(n4983), .B1(
FPADDSUB_intDY_EWSW[27]), .Y(n2926) );
AOI211X1TS U3874 ( .A0(FPADDSUB_intDY_EWSW[30]), .A1(n5182), .B0(n2959),
.C0(n2926), .Y(n4000) );
OAI22X1TS U3875 ( .A0(FPADDSUB_intDX_EWSW[25]), .A1(n4947), .B0(
FPADDSUB_intDX_EWSW[26]), .B1(n5012), .Y(n4005) );
OAI22X1TS U3876 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n5087), .B0(
FPADDSUB_intDY_EWSW[17]), .B1(n4941), .Y(n2927) );
AOI22X1TS U3877 ( .A0(FPADDSUB_intDY_EWSW[17]), .A1(n4941), .B0(
FPADDSUB_intDY_EWSW[18]), .B1(n5013), .Y(n2946) );
AOI222X1TS U3878 ( .A0(n4942), .A1(FPADDSUB_intDX_EWSW[19]), .B0(n5017),
.B1(FPADDSUB_intDX_EWSW[18]), .C0(n2927), .C1(n2946), .Y(n2928) );
OAI22X1TS U3879 ( .A0(FPADDSUB_intDX_EWSW[19]), .A1(n4942), .B0(
FPADDSUB_intDX_EWSW[20]), .B1(n5145), .Y(n2948) );
OAI22X1TS U3880 ( .A0(FPADDSUB_intDY_EWSW[20]), .A1(n5141), .B0(n2928), .B1(
n2948), .Y(n2953) );
NOR2X1TS U3881 ( .A(FPADDSUB_intDX_EWSW[13]), .B(n5072), .Y(n2942) );
AOI22X1TS U3882 ( .A0(FPADDSUB_intDX_EWSW[14]), .A1(n4970), .B0(
FPADDSUB_intDX_EWSW[13]), .B1(n5072), .Y(n2929) );
OAI31X1TS U3883 ( .A0(n2942), .A1(FPADDSUB_intDY_EWSW[12]), .A2(n5076), .B0(
n2929), .Y(n2945) );
OAI22X1TS U3884 ( .A0(n5090), .A1(FPADDSUB_intDX_EWSW[15]), .B0(n4970), .B1(
FPADDSUB_intDX_EWSW[14]), .Y(n2941) );
INVX2TS U3885 ( .A(n2941), .Y(n2944) );
NAND2X1TS U3886 ( .A(n5109), .B(FPADDSUB_intDY_EWSW[4]), .Y(n3996) );
INVX2TS U3887 ( .A(n3996), .Y(n2934) );
AOI22X1TS U3888 ( .A0(FPADDSUB_intDY_EWSW[1]), .A1(n4939), .B0(
FPADDSUB_intDY_EWSW[3]), .B1(n5085), .Y(n4003) );
OAI22X1TS U3889 ( .A0(FPADDSUB_intDY_EWSW[1]), .A1(n4939), .B0(
FPADDSUB_intDY_EWSW[0]), .B1(n5105), .Y(n2932) );
NAND2X1TS U3890 ( .A(FPADDSUB_intDY_EWSW[2]), .B(n5113), .Y(n3995) );
OAI22X1TS U3891 ( .A0(FPADDSUB_intDY_EWSW[2]), .A1(n2930), .B0(n5085), .B1(
FPADDSUB_intDY_EWSW[3]), .Y(n2931) );
OAI222X1TS U3892 ( .A0(n4944), .A1(FPADDSUB_intDY_EWSW[5]), .B0(n5109), .B1(
FPADDSUB_intDY_EWSW[4]), .C0(n2934), .C1(n2933), .Y(n2935) );
AOI22X1TS U3893 ( .A0(FPADDSUB_intDY_EWSW[5]), .A1(n4944), .B0(
FPADDSUB_intDY_EWSW[6]), .B1(n5147), .Y(n4002) );
AOI222X1TS U3894 ( .A0(n4978), .A1(FPADDSUB_intDX_EWSW[7]), .B0(n5185), .B1(
FPADDSUB_intDX_EWSW[6]), .C0(n2935), .C1(n4002), .Y(n2940) );
AOI22X1TS U3895 ( .A0(FPADDSUB_intDY_EWSW[8]), .A1(n4930), .B0(
FPADDSUB_intDY_EWSW[11]), .B1(n5148), .Y(n4004) );
OAI211XLTS U3896 ( .A0(FPADDSUB_intDX_EWSW[7]), .A1(n4978), .B0(n4004), .C0(
n4001), .Y(n2939) );
NOR2XLTS U3897 ( .A(FPADDSUB_intDX_EWSW[11]), .B(n4981), .Y(n2938) );
OAI22X1TS U3898 ( .A0(FPADDSUB_intDY_EWSW[8]), .A1(n4930), .B0(
FPADDSUB_intDY_EWSW[9]), .B1(n4940), .Y(n2936) );
AOI222X1TS U3899 ( .A0(n4981), .A1(FPADDSUB_intDX_EWSW[11]), .B0(n5184),
.B1(FPADDSUB_intDX_EWSW[10]), .C0(n2936), .C1(n4001), .Y(n2937) );
OAI22X1TS U3900 ( .A0(n2940), .A1(n2939), .B0(n2938), .B1(n2937), .Y(n2943)
);
AOI211X1TS U3901 ( .A0(FPADDSUB_intDY_EWSW[12]), .A1(n5076), .B0(n2942),
.C0(n2941), .Y(n4007) );
AOI222X1TS U3902 ( .A0(n2945), .A1(n2944), .B0(n5090), .B1(
FPADDSUB_intDX_EWSW[15]), .C0(n2943), .C1(n4007), .Y(n2950) );
INVX2TS U3903 ( .A(n2946), .Y(n2947) );
AOI211X1TS U3904 ( .A0(n5087), .A1(FPADDSUB_intDY_EWSW[16]), .B0(n2948),
.C0(n2947), .Y(n3999) );
INVX2TS U3905 ( .A(n3999), .Y(n2949) );
OAI22X1TS U3906 ( .A0(FPADDSUB_intDY_EWSW[21]), .A1(n5140), .B0(n2950), .B1(
n2949), .Y(n2952) );
OAI22X1TS U3907 ( .A0(FPADDSUB_intDX_EWSW[21]), .A1(n5142), .B0(
FPADDSUB_intDX_EWSW[22]), .B1(n4966), .Y(n2951) );
AOI21X1TS U3908 ( .A0(FPADDSUB_intDY_EWSW[23]), .A1(n4950), .B0(n2951), .Y(
n4006) );
OAI21XLTS U3909 ( .A0(n2953), .A1(n2952), .B0(n4006), .Y(n2955) );
OAI211XLTS U3910 ( .A0(FPADDSUB_intDX_EWSW[23]), .A1(n5183), .B0(
FPADDSUB_intDX_EWSW[22]), .C0(n4966), .Y(n2954) );
NAND2X1TS U3911 ( .A(FPADDSUB_intDY_EWSW[24]), .B(n5015), .Y(n3998) );
AOI222X1TS U3912 ( .A0(n2956), .A1(n3998), .B0(n4947), .B1(
FPADDSUB_intDX_EWSW[25]), .C0(n5186), .C1(FPADDSUB_intDX_EWSW[24]),
.Y(n2957) );
OAI222X1TS U3913 ( .A0(n5178), .A1(FPADDSUB_intDY_EWSW[26]), .B0(n4005),
.B1(n2957), .C0(n4983), .C1(FPADDSUB_intDY_EWSW[27]), .Y(n2962) );
NAND2X1TS U3914 ( .A(FPADDSUB_intDY_EWSW[30]), .B(n5182), .Y(n2961) );
AOI22X1TS U3915 ( .A0(FPADDSUB_intDX_EWSW[30]), .A1(n5139), .B0(
FPADDSUB_intDX_EWSW[29]), .B1(n4979), .Y(n2958) );
OAI31X1TS U3916 ( .A0(n2959), .A1(FPADDSUB_intDY_EWSW[28]), .A2(n5197), .B0(
n2958), .Y(n2960) );
CLKBUFX2TS U3917 ( .A(n2963), .Y(n3543) );
INVX2TS U3918 ( .A(n3543), .Y(n3168) );
CLKBUFX3TS U3919 ( .A(n2964), .Y(n4010) );
AOI222X1TS U3920 ( .A0(n4826), .A1(FPADDSUB_intDY_EWSW[23]), .B0(
FPADDSUB_DmP_EXP_EWSW[23]), .B1(n5023), .C0(n4010), .C1(
FPADDSUB_intDX_EWSW[23]), .Y(n2965) );
INVX2TS U3921 ( .A(n2965), .Y(n1417) );
NAND2X1TS U3922 ( .A(n2384), .B(n5086), .Y(n3010) );
NAND2X1TS U3923 ( .A(n2981), .B(n4946), .Y(n2974) );
NOR2X1TS U3924 ( .A(FPADDSUB_Raw_mant_NRM_SWR[13]), .B(n2974), .Y(n2973) );
INVX2TS U3925 ( .A(n2973), .Y(n2985) );
NOR2X1TS U3926 ( .A(FPADDSUB_Raw_mant_NRM_SWR[12]), .B(n2985), .Y(n3001) );
NOR2XLTS U3927 ( .A(FPADDSUB_Raw_mant_NRM_SWR[11]), .B(
FPADDSUB_Raw_mant_NRM_SWR[10]), .Y(n2966) );
NAND2X1TS U3928 ( .A(n3001), .B(n2966), .Y(n3015) );
NOR3X1TS U3929 ( .A(FPADDSUB_Raw_mant_NRM_SWR[9]), .B(
FPADDSUB_Raw_mant_NRM_SWR[8]), .C(n3015), .Y(n2967) );
INVX2TS U3930 ( .A(n2967), .Y(n2998) );
NAND3X1TS U3931 ( .A(n3017), .B(n2967), .C(n5192), .Y(n2970) );
INVX2TS U3932 ( .A(n2970), .Y(n3013) );
NAND2X1TS U3933 ( .A(n3013), .B(n4964), .Y(n2997) );
NOR3XLTS U3934 ( .A(FPADDSUB_Raw_mant_NRM_SWR[17]), .B(
FPADDSUB_Raw_mant_NRM_SWR[15]), .C(FPADDSUB_Raw_mant_NRM_SWR[16]), .Y(
n2968) );
NOR2X1TS U3935 ( .A(FPADDSUB_Raw_mant_NRM_SWR[13]), .B(
FPADDSUB_Raw_mant_NRM_SWR[11]), .Y(n2975) );
AND4X1TS U3936 ( .A(n2968), .B(n2975), .C(n4946), .D(n5180), .Y(n3011) );
INVX2TS U3937 ( .A(n2995), .Y(n2972) );
AOI21X1TS U3938 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[0]), .A1(n5084), .B0(
FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n2969) );
OAI32X1TS U3939 ( .A0(n2970), .A1(FPADDSUB_Raw_mant_NRM_SWR[3]), .A2(n2969),
.B0(n4964), .B1(n2970), .Y(n2971) );
AOI211X1TS U3940 ( .A0(n2973), .A1(FPADDSUB_Raw_mant_NRM_SWR[12]), .B0(n2972), .C0(n2971), .Y(n2988) );
NOR3XLTS U3941 ( .A(FPADDSUB_Raw_mant_NRM_SWR[21]), .B(
FPADDSUB_Raw_mant_NRM_SWR[20]), .C(FPADDSUB_Raw_mant_NRM_SWR[19]), .Y(
n2977) );
OA22X1TS U3942 ( .A0(n2977), .A1(n2976), .B0(n2975), .B1(n2974), .Y(n2978)
);
AOI31X1TS U3943 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[5]), .A1(n3020), .A2(n4949),
.B0(n2979), .Y(n3298) );
NAND2X1TS U3944 ( .A(FPADDSUB_LZD_output_NRM2_EW[2]), .B(n3972), .Y(n2980)
);
OAI21XLTS U3945 ( .A0(n3298), .A1(n4677), .B0(n2980), .Y(n1318) );
NAND2X1TS U3946 ( .A(FPADDSUB_Raw_mant_NRM_SWR[14]), .B(n2981), .Y(n2996) );
AOI32X1TS U3947 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[20]), .A1(n4929), .A2(n4943),
.B0(FPADDSUB_Raw_mant_NRM_SWR[22]), .B1(n4929), .Y(n2982) );
AOI32X1TS U3948 ( .A0(n4974), .A1(n2996), .A2(n2982), .B0(
FPADDSUB_Raw_mant_NRM_SWR[25]), .B1(n2996), .Y(n2983) );
AOI31XLTS U3949 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[16]), .A1(n2384), .A2(n5056),
.B0(n2983), .Y(n2989) );
NOR4X1TS U3950 ( .A(FPADDSUB_Raw_mant_NRM_SWR[11]), .B(
FPADDSUB_Raw_mant_NRM_SWR[9]), .C(FPADDSUB_Raw_mant_NRM_SWR[10]), .D(
n2985), .Y(n2986) );
AOI22X1TS U3951 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[8]), .A1(n2986), .B0(
FPADDSUB_Raw_mant_NRM_SWR[6]), .B1(n3020), .Y(n2987) );
AOI31X1TS U3952 ( .A0(n2989), .A1(n2988), .A2(n2987), .B0(n4677), .Y(n3974)
);
AOI211X4TS U3953 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[0]), .A1(n3972), .B0(
n3974), .C0(n4439), .Y(n3364) );
INVX2TS U3954 ( .A(n3364), .Y(n3005) );
NOR2XLTS U3955 ( .A(FPADDSUB_Raw_mant_NRM_SWR[21]), .B(
FPADDSUB_Raw_mant_NRM_SWR[20]), .Y(n2993) );
NOR2X1TS U3956 ( .A(FPADDSUB_Raw_mant_NRM_SWR[25]), .B(
FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n2992) );
OAI31X1TS U3957 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[17]), .A1(
FPADDSUB_Raw_mant_NRM_SWR[16]), .A2(n4948), .B0(n5016), .Y(n2991) );
NAND2X1TS U3958 ( .A(n4929), .B(n4945), .Y(n2990) );
AOI32X1TS U3959 ( .A0(n2993), .A1(n2992), .A2(n2991), .B0(n2990), .B1(n2992),
.Y(n2994) );
NAND4XLTS U3960 ( .A(n3560), .B(n2996), .C(n2995), .D(n2994), .Y(n3000) );
NOR2X1TS U3961 ( .A(FPADDSUB_Raw_mant_NRM_SWR[3]), .B(
FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n3009) );
OAI22X1TS U3962 ( .A0(n3017), .A1(n2998), .B0(n3009), .B1(n2997), .Y(n2999)
);
AOI211X1TS U3963 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[11]), .A1(n3001), .B0(n3000), .C0(n2999), .Y(n3973) );
INVX2TS U3964 ( .A(n3611), .Y(n3909) );
OAI222X4TS U3965 ( .A0(n2313), .A1(FPADDSUB_Raw_mant_NRM_SWR[19]), .B0(n2301), .B1(FPADDSUB_Raw_mant_NRM_SWR[6]), .C0(FPADDSUB_DmP_mant_SHT1_SW[4]), .C1(
n4290), .Y(n3563) );
INVX2TS U3966 ( .A(n4693), .Y(n3276) );
CLKBUFX3TS U3967 ( .A(n3276), .Y(n3612) );
OAI22X1TS U3968 ( .A0(n4290), .A1(FPADDSUB_DmP_mant_SHT1_SW[7]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[16]), .B1(n2312), .Y(n3003) );
AOI2BB1X2TS U3969 ( .A0N(n2300), .A1N(FPADDSUB_Raw_mant_NRM_SWR[9]), .B0(
n3003), .Y(n3235) );
AOI22X1TS U3970 ( .A0(n3612), .A1(FPADDSUB_Data_array_SWR[6]), .B0(n2292),
.B1(n3235), .Y(n3008) );
OAI22X1TS U3971 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(
FPADDSUB_DmP_mant_SHT1_SW[5]), .B0(FPADDSUB_Raw_mant_NRM_SWR[7]), .B1(
n2300), .Y(n3004) );
OAI22X1TS U3972 ( .A0(n3560), .A1(FPADDSUB_DmP_mant_SHT1_SW[6]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[8]), .B1(n2300), .Y(n3006) );
AOI22X1TS U3973 ( .A0(n2358), .A1(n3055), .B0(n2310), .B1(n3233), .Y(n3007)
);
OAI211XLTS U3974 ( .A0(n3909), .A1(n3563), .B0(n3008), .C0(n3007), .Y(n1793)
);
CLKAND2X2TS U3975 ( .A(n3009), .B(n4964), .Y(n3018) );
AOI21X1TS U3976 ( .A0(n5014), .A1(n3011), .B0(n3010), .Y(n3012) );
AOI31X1TS U3977 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[1]), .A1(n3013), .A2(n3018),
.B0(n3012), .Y(n3111) );
NAND2X1TS U3978 ( .A(FPADDSUB_LZD_output_NRM2_EW[3]), .B(n4677), .Y(n3014)
);
OAI21XLTS U3979 ( .A0(n3111), .A1(n3972), .B0(n3014), .Y(n1322) );
NOR4X1TS U3980 ( .A(FPADDSUB_Raw_mant_NRM_SWR[9]), .B(
FPADDSUB_Raw_mant_NRM_SWR[8]), .C(FPADDSUB_Raw_mant_NRM_SWR[1]), .D(
FPADDSUB_Raw_mant_NRM_SWR[0]), .Y(n3016) );
AOI21X1TS U3981 ( .A0(n3020), .A1(FPADDSUB_Raw_mant_NRM_SWR[5]), .B0(n3019),
.Y(n3023) );
NAND2X1TS U3982 ( .A(FPADDSUB_LZD_output_NRM2_EW[4]), .B(n3972), .Y(n3021)
);
OAI21XLTS U3983 ( .A0(n3023), .A1(n4677), .B0(n3021), .Y(n1330) );
AOI32X1TS U3984 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[4]), .A1(n4693), .A2(
n4958), .B0(FPADDSUB_shift_value_SHT2_EWR[4]), .B1(n3612), .Y(n3022)
);
OAI21XLTS U3985 ( .A0(n3023), .A1(n2313), .B0(n3022), .Y(n2075) );
CLKBUFX2TS U3986 ( .A(n2964), .Y(n4828) );
INVX2TS U3987 ( .A(n4828), .Y(n3559) );
INVX2TS U3988 ( .A(n3543), .Y(n4782) );
CLKBUFX2TS U3989 ( .A(n5023), .Y(n4765) );
AOI22X1TS U3990 ( .A0(n4826), .A1(FPADDSUB_intDY_EWSW[27]), .B0(
FPADDSUB_DmP_EXP_EWSW[27]), .B1(n4765), .Y(n3024) );
OAI21XLTS U3991 ( .A0(n4983), .A1(n3559), .B0(n3024), .Y(n1413) );
INVX2TS U3992 ( .A(n4689), .Y(n3483) );
AOI31XLTS U3993 ( .A0(n4187), .A1(n2202), .A2(n5044), .B0(n3495), .Y(n3025)
);
CLKBUFX3TS U3994 ( .A(n4687), .Y(n4279) );
NAND3XLTS U3995 ( .A(n4187), .B(n2202), .C(n5044), .Y(n3026) );
CLKBUFX2TS U3996 ( .A(n3480), .Y(n3477) );
INVX2TS U3997 ( .A(n3027), .Y(n1733) );
AOI21X1TS U3998 ( .A0(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[7]), .A1(
n3029), .B0(n3028), .Y(n3038) );
INVX2TS U3999 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[20]), .Y(
n3040) );
INVX2TS U4000 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[20]), .Y(
n3948) );
INVX2TS U4001 ( .A(n3030), .Y(n3044) );
CMPR32X2TS U4002 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[19]),
.B(n3032), .C(n3031), .CO(n3033), .S(n2619) );
INVX2TS U4003 ( .A(n3033), .Y(n3043) );
CMPR32X2TS U4004 ( .A(n3036), .B(n3035), .C(n3034), .CO(n3042), .S(n2625) );
NAND2X1TS U4005 ( .A(n3038), .B(n3037), .Y(n3429) );
NOR2X1TS U4006 ( .A(n3038), .B(n3037), .Y(n3428) );
AOI21X1TS U4007 ( .A0(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[8]), .A1(
n3429), .B0(n3428), .Y(n3046) );
INVX2TS U4008 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[21]), .Y(
n3436) );
INVX2TS U4009 ( .A(n3039), .Y(n3441) );
CMPR32X2TS U4010 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[20]),
.B(n3040), .C(n3948), .CO(n3041), .S(n3030) );
INVX2TS U4011 ( .A(n3041), .Y(n3440) );
CMPR32X2TS U4012 ( .A(n3044), .B(n3043), .C(n3042), .CO(n3439), .S(n3037) );
NAND2X1TS U4013 ( .A(n3046), .B(n3045), .Y(n3434) );
NOR2X1TS U4014 ( .A(n3046), .B(n3045), .Y(n3433) );
NOR2BX1TS U4015 ( .AN(n3434), .B(n3433), .Y(n3047) );
XNOR2X1TS U4016 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[9]), .B(
n3047), .Y(n3049) );
CLKBUFX3TS U4017 ( .A(n3947), .Y(n4755) );
NAND2X1TS U4018 ( .A(n3216), .B(FPMULT_P_Sgf[33]), .Y(n3048) );
OAI21XLTS U4019 ( .A0(n3049), .A1(n4755), .B0(n3048), .Y(n1562) );
INVX2TS U4020 ( .A(n2310), .Y(n3616) );
AOI22X1TS U4021 ( .A0(n3612), .A1(FPADDSUB_Data_array_SWR[4]), .B0(n2292),
.B1(n3055), .Y(n3052) );
AOI222X4TS U4022 ( .A0(n5204), .A1(n4677), .B0(n4943), .B1(n2391), .C0(n4964), .C1(n4439), .Y(n3613) );
AOI22X1TS U4023 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[20]), .A1(n2391), .B0(
FPADDSUB_DmP_mant_SHT1_SW[3]), .B1(n4958), .Y(n3050) );
AOI22X1TS U4024 ( .A0(n3611), .A1(n3613), .B0(n2359), .B1(n3564), .Y(n3051)
);
OAI211XLTS U4025 ( .A0(n3616), .A1(n3563), .B0(n3052), .C0(n3051), .Y(n1791)
);
INVX2TS U4026 ( .A(n2358), .Y(n3910) );
AOI22X1TS U4027 ( .A0(n3612), .A1(FPADDSUB_Data_array_SWR[5]), .B0(n2310),
.B1(n3055), .Y(n3054) );
AOI22X1TS U4028 ( .A0(n3611), .A1(n3564), .B0(n2292), .B1(n3233), .Y(n3053)
);
OAI211XLTS U4029 ( .A0(n3910), .A1(n3563), .B0(n3054), .C0(n3053), .Y(n1792)
);
INVX2TS U4030 ( .A(n2292), .Y(n3625) );
OAI222X4TS U4031 ( .A0(n2313), .A1(FPADDSUB_Raw_mant_NRM_SWR[15]), .B0(n2301), .B1(FPADDSUB_Raw_mant_NRM_SWR[10]), .C0(FPADDSUB_DmP_mant_SHT1_SW[8]), .C1(
n3560), .Y(n3238) );
AOI22X1TS U4032 ( .A0(n3612), .A1(FPADDSUB_Data_array_SWR[7]), .B0(n3611),
.B1(n3055), .Y(n3057) );
AOI22X1TS U4033 ( .A0(n2358), .A1(n3233), .B0(n2310), .B1(n3235), .Y(n3056)
);
OAI211XLTS U4034 ( .A0(n3625), .A1(n3238), .B0(n3057), .C0(n3056), .Y(n1794)
);
AOI222X1TS U4035 ( .A0(n3168), .A1(FPADDSUB_intDX_EWSW[24]), .B0(
FPADDSUB_DMP_EXP_EWSW[24]), .B1(n4765), .C0(n4010), .C1(
FPADDSUB_intDY_EWSW[24]), .Y(n3058) );
INVX2TS U4036 ( .A(n3058), .Y(n1464) );
AOI222X1TS U4037 ( .A0(n4782), .A1(FPADDSUB_intDX_EWSW[26]), .B0(
FPADDSUB_DMP_EXP_EWSW[26]), .B1(n5023), .C0(n4010), .C1(
FPADDSUB_intDY_EWSW[26]), .Y(n3059) );
INVX2TS U4038 ( .A(n3059), .Y(n1462) );
NAND2X1TS U4039 ( .A(n3989), .B(FPMULT_Sgf_normalized_result[22]), .Y(n3061)
);
INVX2TS U4040 ( .A(n4065), .Y(n4742) );
OAI22X1TS U4041 ( .A0(n3061), .A1(n4739), .B0(n4734), .B1(
FPMULT_Add_result[22]), .Y(n3060) );
CLKBUFX2TS U4042 ( .A(n2964), .Y(n4892) );
INVX2TS U4043 ( .A(n4892), .Y(n4090) );
AOI22X1TS U4044 ( .A0(n3168), .A1(FPADDSUB_intDX_EWSW[25]), .B0(
FPADDSUB_DMP_EXP_EWSW[25]), .B1(n4765), .Y(n3062) );
OAI21XLTS U4045 ( .A0(n4947), .A1(n4090), .B0(n3062), .Y(n1463) );
AOI222X1TS U4046 ( .A0(n4826), .A1(FPADDSUB_intDX_EWSW[27]), .B0(
FPADDSUB_DMP_EXP_EWSW[27]), .B1(n5023), .C0(n4010), .C1(
FPADDSUB_intDY_EWSW[27]), .Y(n3063) );
INVX2TS U4047 ( .A(n3063), .Y(n1461) );
NAND2X1TS U4048 ( .A(n3216), .B(FPMULT_P_Sgf[36]), .Y(n3507) );
AOI2BB2XLTS U4049 ( .B0(FPMULT_Sgf_normalized_result[13]), .B1(n2249), .A0N(
n3507), .A1N(n3133), .Y(n3065) );
AOI22X1TS U4050 ( .A0(FPMULT_P_Sgf[37]), .A1(n2369), .B0(
FPMULT_Add_result[14]), .B1(n2393), .Y(n3064) );
OAI211XLTS U4051 ( .A0(n5110), .A1(n3275), .B0(n3065), .C0(n3064), .Y(n1518)
);
CMPR32X2TS U4052 ( .A(n3068), .B(n3067), .C(n3066), .CO(n3651), .S(n3069) );
INVX2TS U4053 ( .A(n3069), .Y(FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N15) );
CMPR32X2TS U4054 ( .A(n3072), .B(n3071), .C(n3070), .CO(n3582), .S(n3073) );
INVX2TS U4055 ( .A(n3073), .Y(FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N6)
);
CMPR32X2TS U4056 ( .A(n3076), .B(n3075), .C(n3074), .CO(n3071), .S(n3077) );
INVX2TS U4057 ( .A(n3077), .Y(FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N5)
);
INVX2TS U4058 ( .A(n4159), .Y(n3419) );
CLKBUFX3TS U4059 ( .A(n3353), .Y(n4157) );
AOI22X1TS U4060 ( .A0(FPADDSUB_intDY_EWSW[9]), .A1(n2859), .B0(n4157), .B1(
Data_2[9]), .Y(n3079) );
CLKBUFX3TS U4061 ( .A(n3899), .Y(n4173) );
AOI22X1TS U4062 ( .A0(n3411), .A1(FPSENCOS_d_ff3_LUT_out[9]), .B0(n4173),
.B1(FPSENCOS_d_ff3_sh_x_out[9]), .Y(n3078) );
OAI211XLTS U4063 ( .A0(n3419), .A1(n5242), .B0(n3079), .C0(n3078), .Y(n1834)
);
AOI22X1TS U4064 ( .A0(FPADDSUB_intDX_EWSW[21]), .A1(n3385), .B0(n3384), .B1(
Data_1[21]), .Y(n3081) );
AOI22X1TS U4065 ( .A0(n3387), .A1(FPSENCOS_d_ff2_Z[21]), .B0(n3386), .B1(
FPSENCOS_d_ff2_Y[21]), .Y(n3080) );
OAI211XLTS U4066 ( .A0(n3390), .A1(n5230), .B0(n3081), .C0(n3080), .Y(n1920)
);
AOI22X1TS U4067 ( .A0(FPADDSUB_intDX_EWSW[20]), .A1(n3385), .B0(n3384), .B1(
Data_1[20]), .Y(n3083) );
AOI22X1TS U4068 ( .A0(n3387), .A1(FPSENCOS_d_ff2_Z[20]), .B0(n3386), .B1(
FPSENCOS_d_ff2_Y[20]), .Y(n3082) );
OAI211XLTS U4069 ( .A0(n3390), .A1(n5163), .B0(n3083), .C0(n3082), .Y(n1921)
);
CLKBUFX3TS U4070 ( .A(n2859), .Y(n4172) );
CLKBUFX3TS U4071 ( .A(n2860), .Y(n4171) );
AOI22X1TS U4072 ( .A0(FPADDSUB_intDY_EWSW[21]), .A1(n4172), .B0(n4171), .B1(
Data_2[21]), .Y(n3085) );
AOI22X1TS U4073 ( .A0(n3411), .A1(FPSENCOS_d_ff3_LUT_out[21]), .B0(n4115),
.B1(FPSENCOS_d_ff3_sh_x_out[21]), .Y(n3084) );
OAI211XLTS U4074 ( .A0(n3346), .A1(n5245), .B0(n3085), .C0(n3084), .Y(n1822)
);
AOI2BB2XLTS U4075 ( .B0(n3086), .B1(n3089), .A0N(n3089), .A1N(n3086), .Y(
n3092) );
AOI21X1TS U4076 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[9]), .A1(n4985), .B0(n3090),
.Y(n3091) );
OAI21XLTS U4077 ( .A0(n3321), .A1(n3092), .B0(n3091), .Y(n1340) );
AOI22X1TS U4078 ( .A0(FPADDSUB_intDX_EWSW[6]), .A1(n3354), .B0(n2860), .B1(
Data_1[6]), .Y(n3094) );
AOI22X1TS U4079 ( .A0(n4050), .A1(FPSENCOS_d_ff2_Z[6]), .B0(n3369), .B1(
FPSENCOS_d_ff2_Y[6]), .Y(n3093) );
OAI211XLTS U4080 ( .A0(n3372), .A1(n5154), .B0(n3094), .C0(n3093), .Y(n1935)
);
AOI22X1TS U4081 ( .A0(FPADDSUB_intDX_EWSW[11]), .A1(n3354), .B0(n3157), .B1(
Data_1[11]), .Y(n3096) );
AOI22X1TS U4082 ( .A0(n3355), .A1(FPSENCOS_d_ff2_Z[11]), .B0(n3373), .B1(
FPSENCOS_d_ff2_Y[11]), .Y(n3095) );
OAI211XLTS U4083 ( .A0(n3376), .A1(n5228), .B0(n3096), .C0(n3095), .Y(n1930)
);
AOI22X1TS U4084 ( .A0(FPMULT_Sgf_normalized_result[0]), .A1(n2314), .B0(
n2328), .B1(FPMULT_Add_result[0]), .Y(n3098) );
OAI221XLTS U4085 ( .A0(n3394), .A1(FPMULT_P_Sgf[24]), .B0(n3393), .B1(
FPMULT_P_Sgf[23]), .C0(n2389), .Y(n3097) );
AOI22X1TS U4086 ( .A0(FPADDSUB_intDX_EWSW[10]), .A1(n3354), .B0(n2860), .B1(
Data_1[10]), .Y(n3100) );
AOI22X1TS U4087 ( .A0(n3355), .A1(FPSENCOS_d_ff2_Z[10]), .B0(n3373), .B1(
FPSENCOS_d_ff2_Y[10]), .Y(n3099) );
OAI211XLTS U4088 ( .A0(n3376), .A1(n5156), .B0(n3100), .C0(n3099), .Y(n1931)
);
INVX2TS U4089 ( .A(n4853), .Y(n4867) );
AOI211X1TS U4090 ( .A0(n3103), .A1(n3102), .B0(n3101), .C0(n2322), .Y(n3108)
);
AOI211X1TS U4091 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[8]), .A1(n4846), .B0(n3108),
.C0(n3107), .Y(n3109) );
INVX2TS U4092 ( .A(n3109), .Y(n1341) );
AOI32X1TS U4093 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[3]), .A1(n4693), .A2(
n4958), .B0(FPADDSUB_shift_value_SHT2_EWR[3]), .B1(n3612), .Y(n3110)
);
OAI21XLTS U4094 ( .A0(n3111), .A1(n2313), .B0(n3110), .Y(n2076) );
AOI211X1TS U4095 ( .A0(n3114), .A1(n3113), .B0(n3112), .C0(n2322), .Y(n3119)
);
AOI211X1TS U4096 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[16]), .A1(n4319), .B0(n3119), .C0(n3118), .Y(n3120) );
INVX2TS U4097 ( .A(n3120), .Y(n1333) );
AOI21X1TS U4098 ( .A0(n3123), .A1(n3122), .B0(n3121), .Y(n3129) );
AOI211X1TS U4099 ( .A0(n3126), .A1(n3125), .B0(n3124), .C0(n2322), .Y(n3127)
);
AOI21X1TS U4100 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[20]), .A1(n4319), .B0(n3127),
.Y(n3128) );
OAI21XLTS U4101 ( .A0(n3129), .A1(n2394), .B0(n3128), .Y(n1320) );
AOI22X1TS U4102 ( .A0(FPMULT_Sgf_normalized_result[8]), .A1(n2314), .B0(
n2388), .B1(n3130), .Y(n3132) );
AOI22X1TS U4103 ( .A0(FPMULT_Add_result[8]), .A1(n2328), .B0(n2370), .B1(
FPMULT_P_Sgf[32]), .Y(n3131) );
OAI211XLTS U4104 ( .A0(n5111), .A1(n2242), .B0(n3132), .C0(n3131), .Y(n1513)
);
NAND2X1TS U4105 ( .A(n3216), .B(FPMULT_P_Sgf[35]), .Y(n3453) );
AOI2BB2XLTS U4106 ( .B0(FPMULT_Sgf_normalized_result[12]), .B1(n2345), .A0N(
n3453), .A1N(n3133), .Y(n3135) );
AOI22X1TS U4107 ( .A0(FPMULT_P_Sgf[36]), .A1(n2369), .B0(
FPMULT_Add_result[12]), .B1(n2329), .Y(n3134) );
OAI211XLTS U4108 ( .A0(n5110), .A1(n2242), .B0(n3135), .C0(n3134), .Y(n1517)
);
CLKAND2X2TS U4109 ( .A(FPMULT_P_Sgf[39]), .B(n3216), .Y(n3136) );
AOI22X1TS U4110 ( .A0(n3136), .A1(n2388), .B0(
FPMULT_Sgf_normalized_result[16]), .B1(n2345), .Y(n3138) );
AOI22X1TS U4111 ( .A0(FPMULT_P_Sgf[40]), .A1(n2369), .B0(
FPMULT_Add_result[16]), .B1(n2329), .Y(n3137) );
OAI211XLTS U4112 ( .A0(n5187), .A1(n2242), .B0(n3138), .C0(n3137), .Y(n1521)
);
AOI22X1TS U4113 ( .A0(FPMULT_P_Sgf[42]), .A1(n2369), .B0(
FPMULT_Sgf_normalized_result[18]), .B1(n2249), .Y(n3140) );
AOI22X1TS U4114 ( .A0(FPMULT_P_Sgf[41]), .A1(n3141), .B0(
FPMULT_Add_result[18]), .B1(n2329), .Y(n3139) );
OAI211XLTS U4115 ( .A0(n5115), .A1(n2242), .B0(n3140), .C0(n3139), .Y(n1523)
);
AOI22X1TS U4116 ( .A0(FPMULT_P_Sgf[44]), .A1(n2370), .B0(
FPMULT_Sgf_normalized_result[20]), .B1(n2345), .Y(n3143) );
AOI22X1TS U4117 ( .A0(FPMULT_P_Sgf[43]), .A1(n3141), .B0(
FPMULT_Add_result[20]), .B1(n2329), .Y(n3142) );
OAI211XLTS U4118 ( .A0(n5089), .A1(n2242), .B0(n3143), .C0(n3142), .Y(n1525)
);
CLKBUFX3TS U4119 ( .A(n4087), .Y(n3415) );
CLKBUFX3TS U4120 ( .A(n3353), .Y(n3414) );
AOI22X1TS U4121 ( .A0(FPADDSUB_intDX_EWSW[26]), .A1(n3415), .B0(n3414), .B1(
Data_1[26]), .Y(n3145) );
CLKBUFX3TS U4122 ( .A(n2861), .Y(n3416) );
AOI22X1TS U4123 ( .A0(n3416), .A1(FPSENCOS_d_ff2_Z[26]), .B0(n3386), .B1(
FPSENCOS_d_ff2_Y[26]), .Y(n3144) );
OAI211XLTS U4124 ( .A0(n3390), .A1(n5166), .B0(n3145), .C0(n3144), .Y(n1915)
);
AOI22X1TS U4125 ( .A0(FPADDSUB_intDX_EWSW[30]), .A1(n3415), .B0(n3414), .B1(
Data_1[30]), .Y(n3147) );
CLKBUFX3TS U4126 ( .A(n3899), .Y(n4158) );
AOI22X1TS U4127 ( .A0(n3416), .A1(FPSENCOS_d_ff2_Z[30]), .B0(n4158), .B1(
FPSENCOS_d_ff2_Y[30]), .Y(n3146) );
AOI22X1TS U4128 ( .A0(FPADDSUB_intDY_EWSW[23]), .A1(n4322), .B0(n4321), .B1(
Data_2[23]), .Y(n3149) );
AOI22X1TS U4129 ( .A0(n3411), .A1(FPSENCOS_d_ff3_LUT_out[23]), .B0(n3899),
.B1(FPSENCOS_d_ff3_sh_x_out[23]), .Y(n3148) );
OAI211XLTS U4130 ( .A0(n3346), .A1(n5188), .B0(n3149), .C0(n3148), .Y(n1820)
);
AOI22X1TS U4131 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n2859), .B0(n4157), .B1(
Data_2[10]), .Y(n3151) );
AOI22X1TS U4132 ( .A0(n3411), .A1(FPSENCOS_d_ff3_LUT_out[10]), .B0(n4173),
.B1(FPSENCOS_d_ff3_sh_x_out[10]), .Y(n3150) );
OAI211XLTS U4133 ( .A0(n3419), .A1(n5243), .B0(n3151), .C0(n3150), .Y(n1833)
);
AOI22X1TS U4134 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n2859), .B0(n4157), .B1(
Data_2[6]), .Y(n3153) );
AOI22X1TS U4135 ( .A0(n3411), .A1(FPSENCOS_d_ff3_LUT_out[6]), .B0(n4158),
.B1(FPSENCOS_d_ff3_sh_x_out[6]), .Y(n3152) );
OAI211XLTS U4136 ( .A0(n3419), .A1(n5240), .B0(n3153), .C0(n3152), .Y(n1837)
);
AOI22X1TS U4137 ( .A0(FPADDSUB_intDY_EWSW[24]), .A1(n4322), .B0(n4321), .B1(
Data_2[24]), .Y(n3155) );
AOI22X1TS U4138 ( .A0(n3411), .A1(FPSENCOS_d_ff3_LUT_out[24]), .B0(n4115),
.B1(FPSENCOS_d_ff3_sh_x_out[24]), .Y(n3154) );
OAI211XLTS U4139 ( .A0(n3346), .A1(n5246), .B0(n3155), .C0(n3154), .Y(n1819)
);
OAI21XLTS U4140 ( .A0(n5187), .A1(n4742), .B0(n3156), .Y(n1603) );
AOI22X1TS U4141 ( .A0(FPADDSUB_intDX_EWSW[7]), .A1(n3354), .B0(n3157), .B1(
Data_1[7]), .Y(n3159) );
AOI22X1TS U4142 ( .A0(n3355), .A1(FPSENCOS_d_ff2_Z[7]), .B0(n3369), .B1(
FPSENCOS_d_ff2_Y[7]), .Y(n3158) );
OAI211XLTS U4143 ( .A0(n3372), .A1(n5155), .B0(n3159), .C0(n3158), .Y(n1934)
);
AOI2BB2XLTS U4144 ( .B0(n3162), .B1(n2342), .A0N(n2342), .A1N(n3162), .Y(
n3165) );
AOI21X1TS U4145 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[5]), .A1(n4985), .B0(n3163),
.Y(n3164) );
OAI21XLTS U4146 ( .A0(n3321), .A1(n3165), .B0(n3164), .Y(n1344) );
AOI22X1TS U4147 ( .A0(FPADDSUB_intDX_EWSW[28]), .A1(n3415), .B0(n3414), .B1(
Data_1[28]), .Y(n3167) );
AOI22X1TS U4148 ( .A0(n3416), .A1(FPSENCOS_d_ff2_Z[28]), .B0(n3386), .B1(
FPSENCOS_d_ff2_Y[28]), .Y(n3166) );
AOI222X1TS U4149 ( .A0(n3168), .A1(FPADDSUB_intDY_EWSW[25]), .B0(
FPADDSUB_DmP_EXP_EWSW[25]), .B1(n5023), .C0(n4010), .C1(
FPADDSUB_intDX_EWSW[25]), .Y(n3169) );
INVX2TS U4150 ( .A(n3169), .Y(n1415) );
NAND2X1TS U4151 ( .A(FPMULT_FS_Module_state_reg[0]), .B(
FPMULT_FS_Module_state_reg[1]), .Y(n3170) );
AOI22X1TS U4152 ( .A0(FPMULT_FS_Module_state_reg[2]), .A1(
FPMULT_FS_Module_state_reg[1]), .B0(n3178), .B1(n3170), .Y(n3171) );
OR2X1TS U4153 ( .A(n3172), .B(n3171), .Y(n1690) );
AOI22X1TS U4154 ( .A0(FPADDSUB_intDY_EWSW[0]), .A1(n3415), .B0(n3414), .B1(
Data_2[0]), .Y(n3174) );
AOI22X1TS U4155 ( .A0(n3416), .A1(FPSENCOS_d_ff3_LUT_out[0]), .B0(n4158),
.B1(FPSENCOS_d_ff3_sh_x_out[0]), .Y(n3173) );
OAI211XLTS U4156 ( .A0(n3419), .A1(n5236), .B0(n3174), .C0(n3173), .Y(n1843)
);
CLKAND2X2TS U4157 ( .A(FPMULT_P_Sgf[25]), .B(n3216), .Y(n3175) );
AOI22X1TS U4158 ( .A0(FPMULT_Sgf_normalized_result[2]), .A1(n2314), .B0(
n2388), .B1(n3175), .Y(n3177) );
AOI22X1TS U4159 ( .A0(n2328), .A1(FPMULT_Add_result[2]), .B0(n2370), .B1(
FPMULT_P_Sgf[26]), .Y(n3176) );
NAND2X1TS U4160 ( .A(FPMULT_FS_Module_state_reg[0]), .B(n4936), .Y(n3928) );
NOR2X1TS U4161 ( .A(n3178), .B(n3928), .Y(n4704) );
NAND2X1TS U4162 ( .A(FPMULT_P_Sgf[47]), .B(n4704), .Y(n3271) );
INVX2TS U4163 ( .A(n3271), .Y(n3179) );
NAND4X2TS U4164 ( .A(FPMULT_FS_Module_state_reg[0]), .B(
FPMULT_FS_Module_state_reg[1]), .C(n5205), .D(n4965), .Y(n4120) );
OAI211XLTS U4165 ( .A0(n3179), .A1(n5218), .B0(n4065), .C0(n4120), .Y(n1623)
);
AOI22X1TS U4166 ( .A0(FPMULT_Add_result[18]), .A1(n3391), .B0(
FPMULT_Add_result[17]), .B1(n2329), .Y(n3181) );
OAI221XLTS U4167 ( .A0(n3394), .A1(FPMULT_P_Sgf[41]), .B0(n3393), .B1(
FPMULT_P_Sgf[40]), .C0(n2389), .Y(n3180) );
OAI211XLTS U4168 ( .A0(n2250), .A1(n5220), .B0(n3181), .C0(n3180), .Y(n1522)
);
AOI22X1TS U4169 ( .A0(FPMULT_Add_result[16]), .A1(n3391), .B0(
FPMULT_Add_result[15]), .B1(n2329), .Y(n3183) );
OAI221XLTS U4170 ( .A0(n3394), .A1(FPMULT_P_Sgf[39]), .B0(n3393), .B1(
FPMULT_P_Sgf[38]), .C0(n2389), .Y(n3182) );
OAI211XLTS U4171 ( .A0(n2250), .A1(n5221), .B0(n3183), .C0(n3182), .Y(n1520)
);
AOI22X1TS U4172 ( .A0(FPMULT_Add_result[8]), .A1(n3391), .B0(
FPMULT_Add_result[7]), .B1(n2329), .Y(n3185) );
CLKBUFX3TS U4173 ( .A(n3947), .Y(n4268) );
OAI221XLTS U4174 ( .A0(n4268), .A1(FPMULT_P_Sgf[31]), .B0(n3393), .B1(
FPMULT_P_Sgf[30]), .C0(n2389), .Y(n3184) );
OAI211XLTS U4175 ( .A0(n2346), .A1(n5222), .B0(n3185), .C0(n3184), .Y(n1512)
);
AOI22X1TS U4176 ( .A0(n3391), .A1(FPMULT_Add_result[4]), .B0(n2328), .B1(
FPMULT_Add_result[3]), .Y(n3187) );
OAI221XLTS U4177 ( .A0(n3394), .A1(FPMULT_P_Sgf[27]), .B0(n3393), .B1(
FPMULT_P_Sgf[26]), .C0(n2389), .Y(n3186) );
OAI211XLTS U4178 ( .A0(n2346), .A1(n5223), .B0(n3187), .C0(n3186), .Y(n1508)
);
NOR2X1TS U4179 ( .A(n2238), .B(n4186), .Y(n3627) );
INVX2TS U4180 ( .A(n3627), .Y(n3489) );
OAI211XLTS U4181 ( .A0(n4249), .A1(n5234), .B0(n3492), .C0(n3489), .Y(n2126)
);
NAND2X1TS U4182 ( .A(n4345), .B(n2202), .Y(n3188) );
OAI211XLTS U4183 ( .A0(n4249), .A1(n5235), .B0(n3188), .C0(n3492), .Y(n2124)
);
NOR2XLTS U4184 ( .A(n5249), .B(n5022), .Y(FPMULT_S_Oper_A_exp[8]) );
AOI22X1TS U4185 ( .A0(FPMULT_Op_MY[22]), .A1(n2331), .B0(n2401), .B1(n4960),
.Y(n4389) );
AOI22X1TS U4186 ( .A0(FPMULT_Op_MY[21]), .A1(n4931), .B0(n2402), .B1(n5037),
.Y(n4465) );
OA22X1TS U4187 ( .A0(n4470), .A1(n4389), .B0(n4468), .B1(n4465), .Y(n3720)
);
INVX2TS U4188 ( .A(n3189), .Y(mult_x_219_n47) );
AOI22X1TS U4189 ( .A0(FPMULT_Op_MX[15]), .A1(FPMULT_Op_MY[19]), .B0(n5033),
.B1(n2263), .Y(n4488) );
AOI22X1TS U4190 ( .A0(n4403), .A1(n4488), .B0(n4489), .B1(n3190), .Y(n3724)
);
AOI22X1TS U4191 ( .A0(n2203), .A1(FPMULT_Op_MX[19]), .B0(n2299), .B1(n5046),
.Y(n4477) );
AOI22X1TS U4192 ( .A0(n4395), .A1(n4477), .B0(n4478), .B1(n3191), .Y(n3723)
);
AOI22X1TS U4193 ( .A0(n4406), .A1(n3193), .B0(n3192), .B1(n4470), .Y(n3722)
);
INVX2TS U4194 ( .A(n3194), .Y(mult_x_219_n118) );
AOI22X1TS U4195 ( .A0(FPMULT_Op_MY[10]), .A1(n2279), .B0(n2324), .B1(n5045),
.Y(n4381) );
AOI22X1TS U4196 ( .A0(FPMULT_Op_MY[9]), .A1(n2279), .B0(n2324), .B1(n5035),
.Y(n4516) );
OA22X1TS U4197 ( .A0(n4521), .A1(n4381), .B0(n4519), .B1(n4516), .Y(n3731)
);
AOI22X1TS U4198 ( .A0(n2236), .A1(n2308), .B0(n2277), .B1(n5047), .Y(n4385)
);
INVX2TS U4199 ( .A(mult_x_254_n183), .Y(n4525) );
AOI22X1TS U4200 ( .A0(n4385), .A1(n4427), .B0(n4525), .B1(n4101), .Y(n3730)
);
INVX2TS U4201 ( .A(n3195), .Y(mult_x_254_n47) );
AOI22X1TS U4202 ( .A0(n3199), .A1(n3198), .B0(n3197), .B1(n3196), .Y(n3710)
);
AOI22X1TS U4203 ( .A0(FPMULT_Op_MY[3]), .A1(n2308), .B0(n2278), .B1(n5041),
.Y(n4421) );
AOI22X1TS U4204 ( .A0(n4529), .A1(n4421), .B0(n4427), .B1(n3200), .Y(n3709)
);
AOI22X1TS U4205 ( .A0(n3203), .A1(n3202), .B0(n3201), .B1(n4521), .Y(n3708)
);
INVX2TS U4206 ( .A(n3204), .Y(mult_x_254_n118) );
CLKAND2X2TS U4207 ( .A(n3205), .B(n2352), .Y(n4560) );
NOR2XLTS U4208 ( .A(n2352), .B(n3205), .Y(n3207) );
CMPR32X2TS U4209 ( .A(FPMULT_Op_MY[7]), .B(FPMULT_Op_MY[19]), .C(n3206),
.CO(n3214), .S(n4566) );
INVX2TS U4210 ( .A(n2245), .Y(n4633) );
AOI22X1TS U4211 ( .A0(n2351), .A1(n2245), .B0(n4633), .B1(n2285), .Y(n4591)
);
OAI2BB2X1TS U4212 ( .B0(n3207), .B1(n4560), .A0N(n4591), .A1N(n4598), .Y(
n3691) );
AOI22X1TS U4213 ( .A0(n2326), .A1(n4633), .B0(n2246), .B1(n2390), .Y(n3755)
);
OAI21X1TS U4214 ( .A0(n2327), .A1(n3209), .B0(DP_OP_454J200_123_2743_n188),
.Y(n3754) );
NOR2BX4TS U4215 ( .AN(n3754), .B(n2286), .Y(n4412) );
AOI21X4TS U4216 ( .A0(n3210), .A1(n2236), .B0(n2245), .Y(n4640) );
INVX2TS U4217 ( .A(n4640), .Y(n4635) );
AOI22X1TS U4218 ( .A0(n2326), .A1(n4635), .B0(n4640), .B1(n2325), .Y(n3690)
);
AOI22X1TS U4219 ( .A0(n2286), .A1(n3755), .B0(n4412), .B1(n3690), .Y(n3212)
);
INVX2TS U4220 ( .A(n3211), .Y(DP_OP_454J200_123_2743_n46) );
CMPR32X2TS U4221 ( .A(n4560), .B(n3691), .C(n3212), .CO(n3211), .S(n3213) );
INVX2TS U4222 ( .A(n3213), .Y(DP_OP_454J200_123_2743_n47) );
INVX2TS U4223 ( .A(n4622), .Y(n4623) );
AOI22X1TS U4224 ( .A0(n4622), .A1(n3846), .B0(n3758), .B1(n4623), .Y(n3215)
);
OAI21XLTS U4225 ( .A0(n4566), .A1(n2244), .B0(n3215), .Y(
DP_OP_454J200_123_2743_n250) );
CLKAND2X2TS U4226 ( .A(FPMULT_P_Sgf[28]), .B(n3216), .Y(n4219) );
AOI22X1TS U4227 ( .A0(FPMULT_Sgf_normalized_result[5]), .A1(n2314), .B0(
n2388), .B1(n4219), .Y(n3218) );
AOI22X1TS U4228 ( .A0(n2328), .A1(FPMULT_Add_result[5]), .B0(n2370), .B1(
FPMULT_P_Sgf[29]), .Y(n3217) );
OAI211XLTS U4229 ( .A0(n2241), .A1(n5233), .B0(n3218), .C0(n3217), .Y(n1510)
);
AOI22X1TS U4230 ( .A0(FPADDSUB_intDX_EWSW[27]), .A1(n3415), .B0(n3414), .B1(
Data_1[27]), .Y(n3220) );
AOI22X1TS U4231 ( .A0(n3416), .A1(FPSENCOS_d_ff2_Z[27]), .B0(n3386), .B1(
FPSENCOS_d_ff2_Y[27]), .Y(n3219) );
OAI211XLTS U4232 ( .A0(n3390), .A1(n5167), .B0(n3220), .C0(n3219), .Y(n1914)
);
AOI22X1TS U4233 ( .A0(FPADDSUB_intDX_EWSW[31]), .A1(n3415), .B0(n3414), .B1(
Data_1[31]), .Y(n3222) );
AOI22X1TS U4234 ( .A0(n3416), .A1(FPSENCOS_d_ff2_Z[31]), .B0(n4158), .B1(
FPSENCOS_d_ff2_Y[31]), .Y(n3221) );
OAI211XLTS U4235 ( .A0(n3419), .A1(n5232), .B0(n3222), .C0(n3221), .Y(n1910)
);
CLKBUFX3TS U4236 ( .A(n3276), .Y(n3337) );
OAI222X4TS U4237 ( .A0(n2313), .A1(FPADDSUB_Raw_mant_NRM_SWR[13]), .B0(n2301), .B1(FPADDSUB_Raw_mant_NRM_SWR[12]), .C0(n3560), .C1(
FPADDSUB_DmP_mant_SHT1_SW[10]), .Y(n3296) );
INVX2TS U4238 ( .A(n3296), .Y(n3228) );
AOI22X1TS U4239 ( .A0(n3337), .A1(FPADDSUB_Data_array_SWR[10]), .B0(n2310),
.B1(n3228), .Y(n3225) );
AOI222X4TS U4240 ( .A0(n4958), .A1(n5214), .B0(n4946), .B1(n2392), .C0(n5019), .C1(n4439), .Y(n3234) );
OAI22X1TS U4241 ( .A0(n3560), .A1(FPADDSUB_DmP_mant_SHT1_SW[11]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[13]), .B1(n2300), .Y(n3223) );
AOI22X1TS U4242 ( .A0(n2358), .A1(n3234), .B0(n2292), .B1(n3308), .Y(n3224)
);
OAI211XLTS U4243 ( .A0(n3909), .A1(n3238), .B0(n3225), .C0(n3224), .Y(n1797)
);
AOI22X1TS U4244 ( .A0(n3337), .A1(FPADDSUB_Data_array_SWR[11]), .B0(n2310),
.B1(n3308), .Y(n3227) );
AOI22X1TS U4245 ( .A0(n3611), .A1(n3234), .B0(n2292), .B1(n3327), .Y(n3226)
);
OAI211XLTS U4246 ( .A0(n3910), .A1(n3296), .B0(n3227), .C0(n3226), .Y(n1798)
);
AOI22X1TS U4247 ( .A0(n3337), .A1(FPADDSUB_Data_array_SWR[9]), .B0(n2310),
.B1(n3234), .Y(n3230) );
AOI22X1TS U4248 ( .A0(n3611), .A1(n3235), .B0(n2293), .B1(n3228), .Y(n3229)
);
OAI211XLTS U4249 ( .A0(n3910), .A1(n3238), .B0(n3230), .C0(n3229), .Y(n1796)
);
AOI22X1TS U4250 ( .A0(FPADDSUB_intDX_EWSW[29]), .A1(n3415), .B0(n3414), .B1(
Data_1[29]), .Y(n3232) );
AOI22X1TS U4251 ( .A0(n3416), .A1(FPSENCOS_d_ff2_Z[29]), .B0(n3386), .B1(
FPSENCOS_d_ff2_Y[29]), .Y(n3231) );
OAI211XLTS U4252 ( .A0(n3390), .A1(n5168), .B0(n3232), .C0(n3231), .Y(n1912)
);
AOI22X1TS U4253 ( .A0(n3337), .A1(FPADDSUB_Data_array_SWR[8]), .B0(n3611),
.B1(n3233), .Y(n3237) );
AOI22X1TS U4254 ( .A0(n2358), .A1(n3235), .B0(n2293), .B1(n3234), .Y(n3236)
);
AOI22X1TS U4255 ( .A0(FPADDSUB_intDY_EWSW[26]), .A1(n4322), .B0(n4321), .B1(
Data_2[26]), .Y(n3240) );
AOI22X1TS U4256 ( .A0(n3411), .A1(FPSENCOS_d_ff3_LUT_out[26]), .B0(n4115),
.B1(FPSENCOS_d_ff3_sh_x_out[26]), .Y(n3239) );
AOI22X1TS U4257 ( .A0(FPADDSUB_intDX_EWSW[18]), .A1(n3385), .B0(n3384), .B1(
Data_1[18]), .Y(n3242) );
AOI22X1TS U4258 ( .A0(n3387), .A1(FPSENCOS_d_ff2_Z[18]), .B0(n3373), .B1(
FPSENCOS_d_ff2_Y[18]), .Y(n3241) );
OAI211XLTS U4259 ( .A0(n3376), .A1(n5025), .B0(n3242), .C0(n3241), .Y(n1923)
);
AOI21X1TS U4260 ( .A0(n3245), .A1(n3244), .B0(n3243), .Y(n3251) );
AOI211X1TS U4261 ( .A0(n3248), .A1(n3247), .B0(n3246), .C0(n2322), .Y(n3249)
);
AOI21X1TS U4262 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[10]), .A1(n4867), .B0(n3249),
.Y(n3250) );
OAI21XLTS U4263 ( .A0(n3251), .A1(n2394), .B0(n3250), .Y(n1339) );
AOI22X1TS U4264 ( .A0(FPADDSUB_intDX_EWSW[24]), .A1(n3385), .B0(n3384), .B1(
Data_1[24]), .Y(n3253) );
AOI22X1TS U4265 ( .A0(n3387), .A1(FPSENCOS_d_ff2_Z[24]), .B0(n3386), .B1(
FPSENCOS_d_ff2_Y[24]), .Y(n3252) );
OAI211XLTS U4266 ( .A0(n3390), .A1(n5164), .B0(n3253), .C0(n3252), .Y(n1917)
);
AOI21X1TS U4267 ( .A0(n3256), .A1(n3255), .B0(n3254), .Y(n3262) );
AOI211X1TS U4268 ( .A0(n3259), .A1(n3258), .B0(n3257), .C0(n2322), .Y(n3260)
);
AOI21X1TS U4269 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[11]), .A1(n4846), .B0(n3260),
.Y(n3261) );
OAI21XLTS U4270 ( .A0(n3262), .A1(n2394), .B0(n3261), .Y(n1338) );
AOI21X1TS U4271 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[2]), .A1(FPADDSUB_DMP_SFG[0]), .B0(n3263), .Y(n3269) );
OAI21XLTS U4272 ( .A0(n3266), .A1(n3265), .B0(n3264), .Y(n3267) );
AOI22X1TS U4273 ( .A0(n4040), .A1(n3267), .B0(FPADDSUB_Raw_mant_NRM_SWR[3]),
.B1(n4846), .Y(n3268) );
OAI31X1TS U4274 ( .A0(n3270), .A1(n3269), .A2(n2322), .B0(n3268), .Y(n1346)
);
NOR2XLTS U4275 ( .A(n4672), .B(n3953), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]) );
INVX2TS U4276 ( .A(n4120), .Y(n4111) );
OAI31X1TS U4277 ( .A0(n3989), .A1(n4111), .A2(n5036), .B0(n3271), .Y(n1622)
);
AOI22X1TS U4278 ( .A0(FPMULT_Sgf_normalized_result[1]), .A1(n2314), .B0(
n2388), .B1(n3272), .Y(n3274) );
AOI22X1TS U4279 ( .A0(n3391), .A1(FPMULT_Add_result[2]), .B0(n2370), .B1(
FPMULT_P_Sgf[25]), .Y(n3273) );
OAI211XLTS U4280 ( .A0(n3275), .A1(n5104), .B0(n3274), .C0(n3273), .Y(n1506)
);
OAI222X4TS U4281 ( .A0(n2301), .A1(FPADDSUB_Raw_mant_NRM_SWR[20]), .B0(n2312), .B1(FPADDSUB_Raw_mant_NRM_SWR[5]), .C0(FPADDSUB_DmP_mant_SHT1_SW[18]), .C1(
FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n3410) );
AOI222X4TS U4282 ( .A0(n5202), .A1(n3972), .B0(n5016), .B1(n3565), .C0(n4949), .C1(n2392), .Y(n3402) );
AOI22X1TS U4283 ( .A0(n3276), .A1(FPADDSUB_Data_array_SWR[17]), .B0(n2310),
.B1(n3402), .Y(n3280) );
OAI22X1TS U4284 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[8]), .A1(n2312), .B0(n4290),
.B1(FPADDSUB_DmP_mant_SHT1_SW[15]), .Y(n3277) );
OAI22X1TS U4285 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[7]), .A1(n2312), .B0(n3560),
.B1(FPADDSUB_DmP_mant_SHT1_SW[16]), .Y(n3278) );
AOI22X1TS U4286 ( .A0(n3611), .A1(n2210), .B0(n2359), .B1(n3338), .Y(n3279)
);
OAI211XLTS U4287 ( .A0(n3625), .A1(n3410), .B0(n3280), .C0(n3279), .Y(n1804)
);
AOI22X1TS U4288 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n2859), .B0(n4157), .B1(
Data_2[4]), .Y(n3282) );
AOI22X1TS U4289 ( .A0(n3416), .A1(FPSENCOS_d_ff3_LUT_out[4]), .B0(n4158),
.B1(FPSENCOS_d_ff3_sh_x_out[4]), .Y(n3281) );
OAI211XLTS U4290 ( .A0(n3419), .A1(n5239), .B0(n3282), .C0(n3281), .Y(n1839)
);
OAI222X4TS U4291 ( .A0(n2301), .A1(FPADDSUB_Raw_mant_NRM_SWR[16]), .B0(n2313), .B1(FPADDSUB_Raw_mant_NRM_SWR[9]), .C0(FPADDSUB_DmP_mant_SHT1_SW[14]), .C1(
n3560), .Y(n3341) );
AOI22X1TS U4292 ( .A0(n3337), .A1(FPADDSUB_Data_array_SWR[16]), .B0(n2311),
.B1(n3338), .Y(n3284) );
AOI22X1TS U4293 ( .A0(n2358), .A1(n2210), .B0(n2293), .B1(n3402), .Y(n3283)
);
OAI211XLTS U4294 ( .A0(n3909), .A1(n3341), .B0(n3284), .C0(n3283), .Y(n1803)
);
AOI2BB2XLTS U4295 ( .B0(n3288), .B1(n3285), .A0N(n3285), .A1N(n3288), .Y(
n3291) );
AOI21X1TS U4296 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[13]), .A1(n4319), .B0(n3289),
.Y(n3290) );
OAI21XLTS U4297 ( .A0(n3321), .A1(n3291), .B0(n3290), .Y(n1336) );
AOI22X1TS U4298 ( .A0(FPADDSUB_intDX_EWSW[12]), .A1(n3354), .B0(n3353), .B1(
Data_1[12]), .Y(n3293) );
AOI22X1TS U4299 ( .A0(n3387), .A1(FPSENCOS_d_ff2_Z[12]), .B0(n3373), .B1(
FPSENCOS_d_ff2_Y[12]), .Y(n3292) );
OAI211XLTS U4300 ( .A0(n3376), .A1(n5157), .B0(n3293), .C0(n3292), .Y(n1929)
);
AOI22X1TS U4301 ( .A0(n3337), .A1(FPADDSUB_Data_array_SWR[12]), .B0(n2311),
.B1(n3327), .Y(n3295) );
AOI222X4TS U4302 ( .A0(n5203), .A1(n3972), .B0(n4948), .B1(n3565), .C0(n5014), .C1(n2391), .Y(n3336) );
AOI22X1TS U4303 ( .A0(n2358), .A1(n3308), .B0(n2293), .B1(n3336), .Y(n3294)
);
OAI211XLTS U4304 ( .A0(n3909), .A1(n3296), .B0(n3295), .C0(n3294), .Y(n1799)
);
AOI32X1TS U4305 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[2]), .A1(n4693), .A2(
n4958), .B0(FPADDSUB_shift_value_SHT2_EWR[2]), .B1(n3612), .Y(n3297)
);
AOI211X1TS U4306 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[7]), .A1(n4867), .B0(n3306),
.C0(n3305), .Y(n3307) );
INVX2TS U4307 ( .A(n3307), .Y(n1342) );
AOI22X1TS U4308 ( .A0(n3337), .A1(FPADDSUB_Data_array_SWR[13]), .B0(n3611),
.B1(n3308), .Y(n3310) );
AOI22X1TS U4309 ( .A0(n2358), .A1(n3327), .B0(n2311), .B1(n3336), .Y(n3309)
);
OAI211XLTS U4310 ( .A0(n3625), .A1(n3341), .B0(n3310), .C0(n3309), .Y(n1800)
);
AOI22X1TS U4311 ( .A0(FPADDSUB_intDX_EWSW[3]), .A1(n3368), .B0(n3157), .B1(
Data_1[3]), .Y(n3312) );
AOI22X1TS U4312 ( .A0(n4050), .A1(FPSENCOS_d_ff2_Z[3]), .B0(n3369), .B1(
FPSENCOS_d_ff2_Y[3]), .Y(n3311) );
OAI211XLTS U4313 ( .A0(n3372), .A1(n5152), .B0(n3312), .C0(n3311), .Y(n1938)
);
AOI21X1TS U4314 ( .A0(n3315), .A1(n3314), .B0(n3313), .Y(n3322) );
AOI21X1TS U4315 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[18]), .A1(n4867), .B0(n3319),
.Y(n3320) );
OAI21XLTS U4316 ( .A0(n3322), .A1(n2394), .B0(n3320), .Y(n1331) );
AOI22X1TS U4317 ( .A0(FPADDSUB_intDX_EWSW[16]), .A1(n3385), .B0(n3384), .B1(
Data_1[16]), .Y(n3324) );
AOI22X1TS U4318 ( .A0(n3355), .A1(FPSENCOS_d_ff2_Z[16]), .B0(n3373), .B1(
FPSENCOS_d_ff2_Y[16]), .Y(n3323) );
OAI211XLTS U4319 ( .A0(n3376), .A1(n5160), .B0(n3324), .C0(n3323), .Y(n1925)
);
AOI22X1TS U4320 ( .A0(FPADDSUB_intDX_EWSW[15]), .A1(n3385), .B0(n3384), .B1(
Data_1[15]), .Y(n3326) );
AOI22X1TS U4321 ( .A0(n3355), .A1(FPSENCOS_d_ff2_Z[15]), .B0(n3373), .B1(
FPSENCOS_d_ff2_Y[15]), .Y(n3325) );
OAI211XLTS U4322 ( .A0(n3376), .A1(n5229), .B0(n3326), .C0(n3325), .Y(n1926)
);
AOI22X1TS U4323 ( .A0(n3337), .A1(FPADDSUB_Data_array_SWR[14]), .B0(n2387),
.B1(n3327), .Y(n3329) );
AOI22X1TS U4324 ( .A0(n2359), .A1(n3336), .B0(n2293), .B1(n2210), .Y(n3328)
);
OAI211XLTS U4325 ( .A0(n3616), .A1(n3341), .B0(n3329), .C0(n3328), .Y(n1801)
);
AOI22X1TS U4326 ( .A0(FPADDSUB_intDX_EWSW[25]), .A1(n3415), .B0(n3414), .B1(
Data_1[25]), .Y(n3331) );
AOI22X1TS U4327 ( .A0(n3387), .A1(FPSENCOS_d_ff2_Z[25]), .B0(n3386), .B1(
FPSENCOS_d_ff2_Y[25]), .Y(n3330) );
OAI211XLTS U4328 ( .A0(n3390), .A1(n5165), .B0(n3331), .C0(n3330), .Y(n1916)
);
AOI22X1TS U4329 ( .A0(FPADDSUB_intDX_EWSW[14]), .A1(n3354), .B0(n2860), .B1(
Data_1[14]), .Y(n3333) );
AOI22X1TS U4330 ( .A0(n3355), .A1(FPSENCOS_d_ff2_Z[14]), .B0(n3373), .B1(
FPSENCOS_d_ff2_Y[14]), .Y(n3332) );
OAI211XLTS U4331 ( .A0(n3376), .A1(n5159), .B0(n3333), .C0(n3332), .Y(n1927)
);
AOI22X1TS U4332 ( .A0(n3337), .A1(FPADDSUB_Data_array_SWR[18]), .B0(n2387),
.B1(n3338), .Y(n3335) );
AOI222X4TS U4333 ( .A0(n5201), .A1(n4677), .B0(n4943), .B1(n3565), .C0(n4964), .C1(n2392), .Y(n3407) );
AOI22X1TS U4334 ( .A0(n2359), .A1(n3402), .B0(n2293), .B1(n3407), .Y(n3334)
);
OAI211XLTS U4335 ( .A0(n3616), .A1(n3410), .B0(n3335), .C0(n3334), .Y(n1805)
);
AOI22X1TS U4336 ( .A0(n3337), .A1(FPADDSUB_Data_array_SWR[15]), .B0(n2387),
.B1(n3336), .Y(n3340) );
AOI22X1TS U4337 ( .A0(n2292), .A1(n3338), .B0(n2311), .B1(n2210), .Y(n3339)
);
OAI211XLTS U4338 ( .A0(n3910), .A1(n3341), .B0(n3340), .C0(n3339), .Y(n1802)
);
AOI22X1TS U4339 ( .A0(FPADDSUB_intDX_EWSW[0]), .A1(n3368), .B0(Data_1[0]),
.B1(n3157), .Y(n3343) );
AOI22X1TS U4340 ( .A0(FPSENCOS_d_ff2_Z[0]), .A1(n4050), .B0(n3369), .B1(
FPSENCOS_d_ff2_Y[0]), .Y(n3342) );
OAI211XLTS U4341 ( .A0(n3372), .A1(n5224), .B0(n3343), .C0(n3342), .Y(n1941)
);
AOI22X1TS U4342 ( .A0(FPADDSUB_intDY_EWSW[12]), .A1(n2859), .B0(n4157), .B1(
Data_2[12]), .Y(n3345) );
AOI22X1TS U4343 ( .A0(n3411), .A1(FPSENCOS_d_ff3_LUT_out[12]), .B0(n4173),
.B1(FPSENCOS_d_ff3_sh_x_out[12]), .Y(n3344) );
OAI211XLTS U4344 ( .A0(n3346), .A1(n5244), .B0(n3345), .C0(n3344), .Y(n1831)
);
AOI22X1TS U4345 ( .A0(FPMULT_Add_result[15]), .A1(n2393), .B0(
FPMULT_Add_result[14]), .B1(n2329), .Y(n3348) );
OAI221XLTS U4346 ( .A0(n3394), .A1(FPMULT_P_Sgf[38]), .B0(n3393), .B1(
FPMULT_P_Sgf[37]), .C0(n2389), .Y(n3347) );
AOI22X1TS U4347 ( .A0(FPMULT_Add_result[11]), .A1(n2393), .B0(
FPMULT_Add_result[10]), .B1(n2329), .Y(n3350) );
OAI221XLTS U4348 ( .A0(n3394), .A1(FPMULT_P_Sgf[34]), .B0(n3393), .B1(
FPMULT_P_Sgf[33]), .C0(n2389), .Y(n3349) );
OAI211XLTS U4349 ( .A0(n2250), .A1(n5107), .B0(n3350), .C0(n3349), .Y(n1515)
);
AOI22X1TS U4350 ( .A0(FPMULT_Add_result[7]), .A1(n2393), .B0(n2328), .B1(
FPMULT_Add_result[6]), .Y(n3352) );
OAI221XLTS U4351 ( .A0(n3394), .A1(FPMULT_P_Sgf[30]), .B0(n3393), .B1(
FPMULT_P_Sgf[29]), .C0(n2389), .Y(n3351) );
OAI211XLTS U4352 ( .A0(n2346), .A1(n5108), .B0(n3352), .C0(n3351), .Y(n1511)
);
AOI22X1TS U4353 ( .A0(FPADDSUB_intDX_EWSW[13]), .A1(n3354), .B0(n3353), .B1(
Data_1[13]), .Y(n3357) );
AOI22X1TS U4354 ( .A0(n3355), .A1(FPSENCOS_d_ff2_Z[13]), .B0(n3373), .B1(
FPSENCOS_d_ff2_Y[13]), .Y(n3356) );
OAI211XLTS U4355 ( .A0(n3376), .A1(n5158), .B0(n3357), .C0(n3356), .Y(n1928)
);
AOI22X1TS U4356 ( .A0(FPADDSUB_intDX_EWSW[4]), .A1(n3368), .B0(n3353), .B1(
Data_1[4]), .Y(n3359) );
AOI22X1TS U4357 ( .A0(n4050), .A1(FPSENCOS_d_ff2_Z[4]), .B0(n3369), .B1(
FPSENCOS_d_ff2_Y[4]), .Y(n3358) );
OAI211XLTS U4358 ( .A0(n3372), .A1(n5225), .B0(n3359), .C0(n3358), .Y(n1937)
);
OAI21XLTS U4359 ( .A0(n5110), .A1(n4742), .B0(n3360), .Y(n1607) );
OAI21XLTS U4360 ( .A0(n5111), .A1(n4742), .B0(n3361), .Y(n1611) );
AOI22X1TS U4361 ( .A0(FPADDSUB_intDY_EWSW[2]), .A1(n3415), .B0(n3414), .B1(
Data_2[2]), .Y(n3363) );
AOI22X1TS U4362 ( .A0(n3416), .A1(FPSENCOS_d_ff3_LUT_out[2]), .B0(n4158),
.B1(FPSENCOS_d_ff3_sh_x_out[2]), .Y(n3362) );
OAI22X1TS U4363 ( .A0(n3364), .A1(n3565), .B0(FPADDSUB_Raw_mant_NRM_SWR[0]),
.B1(n2312), .Y(n4695) );
AOI222X4TS U4364 ( .A0(n4958), .A1(FPADDSUB_DmP_mant_SHT1_SW[21]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[2]), .B1(n2391), .C0(
FPADDSUB_Raw_mant_NRM_SWR[23]), .C1(n4439), .Y(n3405) );
AOI222X4TS U4365 ( .A0(n4958), .A1(FPADDSUB_DmP_mant_SHT1_SW[22]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[1]), .B1(n2392), .C0(
FPADDSUB_Raw_mant_NRM_SWR[24]), .C1(n4439), .Y(n3908) );
OAI22X1TS U4366 ( .A0(n3405), .A1(n3909), .B0(n3908), .B1(n3910), .Y(n3365)
);
AOI21X1TS U4367 ( .A0(n3276), .A1(FPADDSUB_Data_array_SWR[23]), .B0(n3365),
.Y(n3366) );
OAI21XLTS U4368 ( .A0(n4695), .A1(n3367), .B0(n3366), .Y(n1810) );
AOI22X1TS U4369 ( .A0(FPADDSUB_intDX_EWSW[2]), .A1(n3368), .B0(n2860), .B1(
Data_1[2]), .Y(n3371) );
AOI22X1TS U4370 ( .A0(n4050), .A1(FPSENCOS_d_ff2_Z[2]), .B0(n3369), .B1(
FPSENCOS_d_ff2_Y[2]), .Y(n3370) );
OAI211XLTS U4371 ( .A0(n3372), .A1(n5151), .B0(n3371), .C0(n3370), .Y(n1939)
);
AOI22X1TS U4372 ( .A0(FPADDSUB_intDX_EWSW[19]), .A1(n3385), .B0(n3384), .B1(
Data_1[19]), .Y(n3375) );
AOI22X1TS U4373 ( .A0(n3387), .A1(FPSENCOS_d_ff2_Z[19]), .B0(n3373), .B1(
FPSENCOS_d_ff2_Y[19]), .Y(n3374) );
OAI211XLTS U4374 ( .A0(n3376), .A1(n5162), .B0(n3375), .C0(n3374), .Y(n1922)
);
OAI21XLTS U4375 ( .A0(n5115), .A1(n4742), .B0(n3377), .Y(n1601) );
XNOR2X1TS U4376 ( .A(DP_OP_26J200_124_9022_n1), .B(FPADDSUB_ADD_OVRFLW_NRM2),
.Y(n3382) );
OR4X2TS U4377 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[7]), .C(FPADDSUB_exp_rslt_NRM2_EW1[5]), .D(
FPADDSUB_exp_rslt_NRM2_EW1[4]), .Y(n3379) );
OR4X2TS U4378 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[2]), .C(FPADDSUB_exp_rslt_NRM2_EW1[1]), .D(
FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(n3378) );
AND4X1TS U4379 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[5]), .C(FPADDSUB_exp_rslt_NRM2_EW1[4]), .D(
FPADDSUB_exp_rslt_NRM2_EW1[7]), .Y(n3381) );
AND4X1TS U4380 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[2]), .C(FPADDSUB_exp_rslt_NRM2_EW1[1]), .D(
FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(n3380) );
OAI21XLTS U4381 ( .A0(n4777), .A1(FPADDSUB_SIGN_FLAG_SHT1SHT2), .B0(n4776),
.Y(n3383) );
OAI21XLTS U4382 ( .A0(n4877), .A1(n5120), .B0(n3383), .Y(n1356) );
AOI22X1TS U4383 ( .A0(FPADDSUB_intDX_EWSW[22]), .A1(n3385), .B0(n3384), .B1(
Data_1[22]), .Y(n3389) );
AOI22X1TS U4384 ( .A0(n3387), .A1(FPSENCOS_d_ff2_Z[22]), .B0(n3386), .B1(
FPSENCOS_d_ff2_Y[22]), .Y(n3388) );
OAI211XLTS U4385 ( .A0(n3390), .A1(n5231), .B0(n3389), .C0(n3388), .Y(n1919)
);
AOI22X1TS U4386 ( .A0(n3391), .A1(FPMULT_Add_result[5]), .B0(n2328), .B1(
FPMULT_Add_result[4]), .Y(n3396) );
OAI221XLTS U4387 ( .A0(n3394), .A1(FPMULT_P_Sgf[28]), .B0(n3393), .B1(
FPMULT_P_Sgf[27]), .C0(n2389), .Y(n3395) );
OAI211XLTS U4388 ( .A0(n2250), .A1(n5121), .B0(n3396), .C0(n3395), .Y(n1509)
);
OAI22X1TS U4389 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[0]), .A1(n2312), .B0(
FPADDSUB_Raw_mant_NRM_SWR[25]), .B1(n2300), .Y(n3911) );
AOI222X4TS U4390 ( .A0(n5200), .A1(n4677), .B0(n4945), .B1(n4439), .C0(n5021), .C1(n2391), .Y(n3406) );
AOI22X1TS U4391 ( .A0(n3276), .A1(FPADDSUB_Data_array_SWR[22]), .B0(n2387),
.B1(n3406), .Y(n3399) );
OA22X1TS U4392 ( .A0(n3908), .A1(n3616), .B0(n3405), .B1(n3910), .Y(n3398)
);
OAI211XLTS U4393 ( .A0(n3625), .A1(n3911), .B0(n3399), .C0(n3398), .Y(n1809)
);
AOI22X1TS U4394 ( .A0(n3276), .A1(FPADDSUB_Data_array_SWR[21]), .B0(n2387),
.B1(n3407), .Y(n3401) );
AOI2BB2XLTS U4395 ( .B0(n2359), .B1(n3406), .A0N(n3625), .A1N(n3908), .Y(
n3400) );
AOI22X1TS U4396 ( .A0(n3276), .A1(FPADDSUB_Data_array_SWR[19]), .B0(n2311),
.B1(n3407), .Y(n3404) );
AOI22X1TS U4397 ( .A0(n3611), .A1(n3402), .B0(n2293), .B1(n3406), .Y(n3403)
);
OAI211XLTS U4398 ( .A0(n3910), .A1(n3410), .B0(n3404), .C0(n3403), .Y(n1806)
);
AOI2BB2XLTS U4399 ( .B0(n3276), .B1(FPADDSUB_Data_array_SWR[20]), .A0N(n3625), .A1N(n3405), .Y(n3409) );
AOI22X1TS U4400 ( .A0(n2359), .A1(n3407), .B0(n2311), .B1(n3406), .Y(n3408)
);
OAI211XLTS U4401 ( .A0(n3909), .A1(n3410), .B0(n3409), .C0(n3408), .Y(n1807)
);
AOI22X1TS U4402 ( .A0(FPADDSUB_intDY_EWSW[8]), .A1(n4087), .B0(n4157), .B1(
Data_2[8]), .Y(n3413) );
AOI22X1TS U4403 ( .A0(n3411), .A1(FPSENCOS_d_ff3_LUT_out[8]), .B0(n4173),
.B1(FPSENCOS_d_ff3_sh_x_out[8]), .Y(n3412) );
OAI211XLTS U4404 ( .A0(n3419), .A1(n5241), .B0(n3413), .C0(n3412), .Y(n1835)
);
AOI22X1TS U4405 ( .A0(FPADDSUB_intDY_EWSW[1]), .A1(n3415), .B0(n3414), .B1(
Data_2[1]), .Y(n3418) );
AOI22X1TS U4406 ( .A0(n3416), .A1(FPSENCOS_d_ff3_LUT_out[1]), .B0(n4158),
.B1(FPSENCOS_d_ff3_sh_x_out[1]), .Y(n3417) );
OAI211XLTS U4407 ( .A0(n3419), .A1(n5237), .B0(n3418), .C0(n3417), .Y(n1842)
);
AOI22X1TS U4408 ( .A0(n4569), .A1(n3846), .B0(n3758), .B1(n4568), .Y(n3420)
);
OAI21XLTS U4409 ( .A0(n4572), .A1(n2244), .B0(n3420), .Y(
DP_OP_454J200_123_2743_n252) );
INVX2TS U4410 ( .A(n4828), .Y(n3574) );
CLKBUFX3TS U4411 ( .A(n5023), .Y(n3571) );
AOI22X1TS U4412 ( .A0(n3572), .A1(FPADDSUB_intDY_EWSW[9]), .B0(
FPADDSUB_DmP_EXP_EWSW[9]), .B1(n3571), .Y(n3421) );
OAI21XLTS U4413 ( .A0(n4940), .A1(n3574), .B0(n3421), .Y(n1284) );
AOI22X1TS U4414 ( .A0(n3572), .A1(FPADDSUB_intDY_EWSW[1]), .B0(
FPADDSUB_DmP_EXP_EWSW[1]), .B1(n3571), .Y(n3422) );
OAI21XLTS U4415 ( .A0(n4939), .A1(n3574), .B0(n3422), .Y(n1291) );
INVX2TS U4416 ( .A(n4828), .Y(n3552) );
CLKBUFX3TS U4417 ( .A(n4765), .Y(n4825) );
AOI22X1TS U4418 ( .A0(n3572), .A1(FPADDSUB_intDY_EWSW[2]), .B0(
FPADDSUB_DmP_EXP_EWSW[2]), .B1(n4825), .Y(n3423) );
OAI21XLTS U4419 ( .A0(n5113), .A1(n3552), .B0(n3423), .Y(n1312) );
CLKBUFX3TS U4420 ( .A(n5023), .Y(n4781) );
AOI22X1TS U4421 ( .A0(n4010), .A1(FPADDSUB_intDX_EWSW[13]), .B0(
FPADDSUB_DmP_EXP_EWSW[13]), .B1(n4781), .Y(n3424) );
OAI21XLTS U4422 ( .A0(n5072), .A1(n2963), .B0(n3424), .Y(n1380) );
AOI22X1TS U4423 ( .A0(n4782), .A1(FPADDSUB_intDY_EWSW[17]), .B0(
FPADDSUB_DmP_EXP_EWSW[17]), .B1(n4781), .Y(n3425) );
OAI21XLTS U4424 ( .A0(n4941), .A1(n3559), .B0(n3425), .Y(n1389) );
AOI22X1TS U4425 ( .A0(n4826), .A1(FPADDSUB_intDY_EWSW[20]), .B0(
FPADDSUB_DmP_EXP_EWSW[20]), .B1(n4781), .Y(n3426) );
OAI21XLTS U4426 ( .A0(n5141), .A1(n3559), .B0(n3426), .Y(n1392) );
AOI22X1TS U4427 ( .A0(n4010), .A1(FPADDSUB_intDX_EWSW[19]), .B0(
FPADDSUB_DmP_EXP_EWSW[19]), .B1(n4781), .Y(n3427) );
NOR2BX1TS U4428 ( .AN(n3429), .B(n3428), .Y(n3430) );
XNOR2X1TS U4429 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[8]), .B(
n3430), .Y(n3432) );
OAI21XLTS U4430 ( .A0(n3432), .A1(n4755), .B0(n3431), .Y(n1561) );
AOI21X1TS U4431 ( .A0(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[9]), .A1(
n3434), .B0(n3433), .Y(n3443) );
INVX2TS U4432 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[22]), .Y(
n3945) );
INVX2TS U4433 ( .A(n3435), .Y(n3449) );
CMPR32X2TS U4434 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[21]),
.B(n3437), .C(n3436), .CO(n3438), .S(n3039) );
INVX2TS U4435 ( .A(n3438), .Y(n3448) );
CMPR32X2TS U4436 ( .A(n3441), .B(n3440), .C(n3439), .CO(n3447), .S(n3045) );
NAND2X1TS U4437 ( .A(n3443), .B(n3442), .Y(n3966) );
NOR2X1TS U4438 ( .A(n3443), .B(n3442), .Y(n3967) );
AOI21X1TS U4439 ( .A0(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[10]), .A1(
n3966), .B0(n3967), .Y(n3451) );
INVX2TS U4440 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[23]), .Y(
n4053) );
INVX2TS U4441 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[23]), .Y(
n3499) );
INVX2TS U4442 ( .A(n3444), .Y(n3503) );
CMPR32X2TS U4443 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[22]),
.B(n3445), .C(n3945), .CO(n3446), .S(n3435) );
INVX2TS U4444 ( .A(n3446), .Y(n3502) );
CMPR32X2TS U4445 ( .A(n3449), .B(n3448), .C(n3447), .CO(n3501), .S(n3442) );
NAND2X1TS U4446 ( .A(n3451), .B(n3450), .Y(n3498) );
NOR2X1TS U4447 ( .A(n3451), .B(n3450), .Y(n3497) );
NOR2BX1TS U4448 ( .AN(n3498), .B(n3497), .Y(n3452) );
XNOR2X1TS U4449 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[11]), .B(
n3452), .Y(n3454) );
CLKBUFX3TS U4450 ( .A(n4687), .Y(n3464) );
CLKBUFX3TS U4451 ( .A(n3480), .Y(n3469) );
INVX2TS U4452 ( .A(n3455), .Y(n1743) );
INVX2TS U4453 ( .A(n4689), .Y(n4691) );
AOI222X1TS U4454 ( .A0(n3483), .A1(FPSENCOS_d_ff2_Z[23]), .B0(n3464), .B1(
FPSENCOS_d_ff_Zn[23]), .C0(n3469), .C1(FPSENCOS_d_ff1_Z[23]), .Y(n3456) );
INVX2TS U4455 ( .A(n3456), .Y(n1741) );
AOI222X1TS U4456 ( .A0(n3483), .A1(FPSENCOS_d_ff2_Z[24]), .B0(n3464), .B1(
FPSENCOS_d_ff_Zn[24]), .C0(n3469), .C1(FPSENCOS_d_ff1_Z[24]), .Y(n3457) );
INVX2TS U4457 ( .A(n3457), .Y(n1740) );
AOI222X1TS U4458 ( .A0(n3483), .A1(FPSENCOS_d_ff2_Z[25]), .B0(n3464), .B1(
FPSENCOS_d_ff_Zn[25]), .C0(n3469), .C1(FPSENCOS_d_ff1_Z[25]), .Y(n3458) );
INVX2TS U4459 ( .A(n3458), .Y(n1739) );
AOI222X1TS U4460 ( .A0(n3483), .A1(FPSENCOS_d_ff2_Z[26]), .B0(n3464), .B1(
FPSENCOS_d_ff_Zn[26]), .C0(n3469), .C1(FPSENCOS_d_ff1_Z[26]), .Y(n3459) );
INVX2TS U4461 ( .A(n3459), .Y(n1738) );
AOI222X1TS U4462 ( .A0(n3483), .A1(FPSENCOS_d_ff2_Z[27]), .B0(n3464), .B1(
FPSENCOS_d_ff_Zn[27]), .C0(n3469), .C1(FPSENCOS_d_ff1_Z[27]), .Y(n3460) );
INVX2TS U4463 ( .A(n3460), .Y(n1737) );
AOI222X1TS U4464 ( .A0(n3483), .A1(FPSENCOS_d_ff2_Z[28]), .B0(n3464), .B1(
FPSENCOS_d_ff_Zn[28]), .C0(n3469), .C1(FPSENCOS_d_ff1_Z[28]), .Y(n3461) );
INVX2TS U4465 ( .A(n3461), .Y(n1736) );
AOI222X1TS U4466 ( .A0(n3483), .A1(FPSENCOS_d_ff2_Z[29]), .B0(n3464), .B1(
FPSENCOS_d_ff_Zn[29]), .C0(n3469), .C1(FPSENCOS_d_ff1_Z[29]), .Y(n3462) );
INVX2TS U4467 ( .A(n3462), .Y(n1735) );
AOI222X1TS U4468 ( .A0(n3483), .A1(FPSENCOS_d_ff2_Z[30]), .B0(n3464), .B1(
FPSENCOS_d_ff_Zn[30]), .C0(n3477), .C1(FPSENCOS_d_ff1_Z[30]), .Y(n3463) );
INVX2TS U4469 ( .A(n3463), .Y(n1734) );
INVX2TS U4470 ( .A(n3465), .Y(n1742) );
CLKBUFX3TS U4471 ( .A(n4687), .Y(n3482) );
INVX2TS U4472 ( .A(n3466), .Y(n1749) );
INVX2TS U4473 ( .A(n3467), .Y(n1746) );
INVX2TS U4474 ( .A(n3468), .Y(n1745) );
INVX2TS U4475 ( .A(n3470), .Y(n1744) );
INVX2TS U4476 ( .A(n3471), .Y(n1747) );
CLKBUFX3TS U4477 ( .A(n4687), .Y(n3494) );
CLKBUFX3TS U4478 ( .A(n3480), .Y(n3655) );
AOI222X1TS U4479 ( .A0(n3495), .A1(FPSENCOS_d_ff2_Z[4]), .B0(n3494), .B1(
FPSENCOS_d_ff_Zn[4]), .C0(n3655), .C1(FPSENCOS_d_ff1_Z[4]), .Y(n3472)
);
INVX2TS U4480 ( .A(n3472), .Y(n1760) );
AOI222X1TS U4481 ( .A0(n4688), .A1(FPSENCOS_d_ff2_Z[6]), .B0(n3494), .B1(
FPSENCOS_d_ff_Zn[6]), .C0(n3655), .C1(FPSENCOS_d_ff1_Z[6]), .Y(n3473)
);
INVX2TS U4482 ( .A(n3473), .Y(n1758) );
AOI222X1TS U4483 ( .A0(n3495), .A1(FPSENCOS_d_ff2_Z[13]), .B0(n3482), .B1(
FPSENCOS_d_ff_Zn[13]), .C0(n3477), .C1(FPSENCOS_d_ff1_Z[13]), .Y(n3474) );
INVX2TS U4484 ( .A(n3474), .Y(n1751) );
INVX2TS U4485 ( .A(n3475), .Y(n1748) );
AOI222X1TS U4486 ( .A0(n4215), .A1(FPSENCOS_d_ff2_Z[8]), .B0(n3494), .B1(
FPSENCOS_d_ff_Zn[8]), .C0(n3655), .C1(FPSENCOS_d_ff1_Z[8]), .Y(n3476)
);
INVX2TS U4487 ( .A(n3476), .Y(n1756) );
AOI222X1TS U4488 ( .A0(n4280), .A1(FPSENCOS_d_ff2_Z[11]), .B0(n3482), .B1(
FPSENCOS_d_ff_Zn[11]), .C0(n3477), .C1(FPSENCOS_d_ff1_Z[11]), .Y(n3478) );
INVX2TS U4489 ( .A(n3478), .Y(n1753) );
AOI222X1TS U4490 ( .A0(n4688), .A1(FPSENCOS_d_ff2_Z[14]), .B0(n3482), .B1(
FPSENCOS_d_ff_Zn[14]), .C0(n3480), .C1(FPSENCOS_d_ff1_Z[14]), .Y(n3479) );
INVX2TS U4491 ( .A(n3479), .Y(n1750) );
AOI222X1TS U4492 ( .A0(n3495), .A1(FPSENCOS_d_ff2_Z[10]), .B0(n3494), .B1(
FPSENCOS_d_ff_Zn[10]), .C0(n3480), .C1(FPSENCOS_d_ff1_Z[10]), .Y(n3481) );
INVX2TS U4493 ( .A(n3481), .Y(n1754) );
INVX2TS U4494 ( .A(n3484), .Y(n1752) );
AOI222X1TS U4495 ( .A0(n4280), .A1(FPSENCOS_d_ff2_Z[3]), .B0(n3494), .B1(
FPSENCOS_d_ff_Zn[3]), .C0(n3655), .C1(FPSENCOS_d_ff1_Z[3]), .Y(n3485)
);
INVX2TS U4496 ( .A(n3485), .Y(n1761) );
AOI222X1TS U4497 ( .A0(n4215), .A1(FPSENCOS_d_ff2_Z[2]), .B0(n3494), .B1(
FPSENCOS_d_ff_Zn[2]), .C0(n3655), .C1(FPSENCOS_d_ff1_Z[2]), .Y(n3486)
);
INVX2TS U4498 ( .A(n3486), .Y(n1762) );
AOI222X1TS U4499 ( .A0(n4280), .A1(FPSENCOS_d_ff2_Z[7]), .B0(n3494), .B1(
FPSENCOS_d_ff_Zn[7]), .C0(n3655), .C1(FPSENCOS_d_ff1_Z[7]), .Y(n3487)
);
INVX2TS U4500 ( .A(n3487), .Y(n1757) );
AOI222X1TS U4501 ( .A0(n4215), .A1(FPSENCOS_d_ff2_Z[1]), .B0(n3494), .B1(
FPSENCOS_d_ff_Zn[1]), .C0(n3655), .C1(FPSENCOS_d_ff1_Z[1]), .Y(n3488)
);
INVX2TS U4502 ( .A(n3488), .Y(n1763) );
NAND2X1TS U4503 ( .A(FPSENCOS_d_ff3_LUT_out[15]), .B(n4353), .Y(n3490) );
OAI211XLTS U4504 ( .A0(n4187), .A1(n4186), .B0(n3490), .C0(n3489), .Y(n2120)
);
AOI222X1TS U4505 ( .A0(n4688), .A1(FPSENCOS_d_ff2_Z[9]), .B0(n3494), .B1(
FPSENCOS_d_ff_Zn[9]), .C0(n3655), .C1(FPSENCOS_d_ff1_Z[9]), .Y(n3491)
);
INVX2TS U4506 ( .A(n3491), .Y(n1755) );
AOI2BB2XLTS U4507 ( .B0(FPSENCOS_d_ff3_LUT_out[5]), .B1(n4353), .A0N(n2202),
.A1N(n3492), .Y(n3493) );
OAI31X1TS U4508 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n4306), .A2(n4186),
.B0(n3493), .Y(n2128) );
AOI222X1TS U4509 ( .A0(n4280), .A1(FPSENCOS_d_ff2_Z[5]), .B0(n3494), .B1(
FPSENCOS_d_ff_Zn[5]), .C0(n3655), .C1(FPSENCOS_d_ff1_Z[5]), .Y(n3496)
);
INVX2TS U4510 ( .A(n3496), .Y(n1759) );
AOI21X1TS U4511 ( .A0(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[11]), .A1(
n3498), .B0(n3497), .Y(n3505) );
INVX2TS U4512 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[24]), .Y(
n3939) );
CMPR32X2TS U4513 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[23]),
.B(n4053), .C(n3499), .CO(n3500), .S(n3444) );
INVX2TS U4514 ( .A(n3500), .Y(n3938) );
CMPR32X2TS U4515 ( .A(n3503), .B(n3502), .C(n3501), .CO(n3937), .S(n3450) );
NAND2X1TS U4516 ( .A(n3505), .B(n3504), .Y(n3941) );
NOR2X1TS U4517 ( .A(n3505), .B(n3504), .Y(n3942) );
NOR2BX1TS U4518 ( .AN(n3941), .B(n3942), .Y(n3506) );
XNOR2X1TS U4519 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[12]), .B(
n3506), .Y(n3508) );
CLKBUFX3TS U4520 ( .A(n3579), .Y(n3671) );
NOR2XLTS U4521 ( .A(n3671), .B(n3509), .Y(n3510) );
CLKBUFX3TS U4522 ( .A(n3687), .Y(n3633) );
NOR2XLTS U4523 ( .A(n3671), .B(n3511), .Y(n3512) );
AOI222X1TS U4524 ( .A0(n3671), .A1(cordic_result[23]), .B0(n3633), .B1(
FPSENCOS_d_ff_Yn[23]), .C0(n3632), .C1(FPSENCOS_d_ff_Xn[23]), .Y(n3513) );
INVX2TS U4525 ( .A(n3513), .Y(n1703) );
CLKBUFX3TS U4526 ( .A(n3579), .Y(n3638) );
AOI222X1TS U4527 ( .A0(n3638), .A1(cordic_result[24]), .B0(n3633), .B1(
FPSENCOS_d_ff_Yn[24]), .C0(n3630), .C1(FPSENCOS_d_ff_Xn[24]), .Y(n3514) );
INVX2TS U4528 ( .A(n3514), .Y(n1702) );
AOI222X1TS U4529 ( .A0(n3671), .A1(cordic_result[25]), .B0(n3633), .B1(
FPSENCOS_d_ff_Yn[25]), .C0(n3630), .C1(FPSENCOS_d_ff_Xn[25]), .Y(n3515) );
INVX2TS U4530 ( .A(n3515), .Y(n1701) );
AOI222X1TS U4531 ( .A0(n3671), .A1(cordic_result[26]), .B0(n3633), .B1(
FPSENCOS_d_ff_Yn[26]), .C0(n3632), .C1(FPSENCOS_d_ff_Xn[26]), .Y(n3516) );
INVX2TS U4532 ( .A(n3516), .Y(n1700) );
AOI222X1TS U4533 ( .A0(n3671), .A1(cordic_result[27]), .B0(n3633), .B1(
FPSENCOS_d_ff_Yn[27]), .C0(n3630), .C1(FPSENCOS_d_ff_Xn[27]), .Y(n3517) );
INVX2TS U4534 ( .A(n3517), .Y(n1699) );
AOI222X1TS U4535 ( .A0(n3671), .A1(cordic_result[28]), .B0(n3633), .B1(
FPSENCOS_d_ff_Yn[28]), .C0(n3632), .C1(FPSENCOS_d_ff_Xn[28]), .Y(n3518) );
INVX2TS U4536 ( .A(n3518), .Y(n1698) );
AOI222X1TS U4537 ( .A0(n3671), .A1(cordic_result[29]), .B0(n3633), .B1(
FPSENCOS_d_ff_Yn[29]), .C0(n3632), .C1(FPSENCOS_d_ff_Xn[29]), .Y(n3519) );
INVX2TS U4538 ( .A(n3519), .Y(n1697) );
AOI222X1TS U4539 ( .A0(n3671), .A1(cordic_result[30]), .B0(n3670), .B1(
FPSENCOS_d_ff_Yn[30]), .C0(n3630), .C1(FPSENCOS_d_ff_Xn[30]), .Y(n3520) );
INVX2TS U4540 ( .A(n3520), .Y(n1696) );
CLKBUFX3TS U4541 ( .A(n5023), .Y(n4887) );
AOI22X1TS U4542 ( .A0(n4890), .A1(FPADDSUB_intDX_EWSW[6]), .B0(
FPADDSUB_DMP_EXP_EWSW[6]), .B1(n4887), .Y(n3521) );
OAI21XLTS U4543 ( .A0(n5185), .A1(n4090), .B0(n3521), .Y(n1241) );
AOI22X1TS U4544 ( .A0(n2964), .A1(FPADDSUB_intDY_EWSW[8]), .B0(
FPADDSUB_DMP_EXP_EWSW[8]), .B1(n4887), .Y(n3522) );
OAI21XLTS U4545 ( .A0(n4930), .A1(n2963), .B0(n3522), .Y(n1253) );
AOI22X1TS U4546 ( .A0(n4890), .A1(FPADDSUB_intDX_EWSW[11]), .B0(
FPADDSUB_DMP_EXP_EWSW[11]), .B1(n4887), .Y(n3523) );
OAI21XLTS U4547 ( .A0(n4981), .A1(n3574), .B0(n3523), .Y(n1257) );
AOI22X1TS U4548 ( .A0(n3572), .A1(FPADDSUB_intDX_EWSW[14]), .B0(
FPADDSUB_DMP_EXP_EWSW[14]), .B1(n4887), .Y(n3524) );
OAI21XLTS U4549 ( .A0(n4970), .A1(n3574), .B0(n3524), .Y(n1261) );
AOI22X1TS U4550 ( .A0(n4010), .A1(FPADDSUB_intDY_EWSW[17]), .B0(
FPADDSUB_DMP_EXP_EWSW[17]), .B1(n4887), .Y(n3525) );
OAI21XLTS U4551 ( .A0(n4941), .A1(n2963), .B0(n3525), .Y(n1233) );
AOI22X1TS U4552 ( .A0(n3572), .A1(FPADDSUB_intDX_EWSW[10]), .B0(
FPADDSUB_DMP_EXP_EWSW[10]), .B1(n4887), .Y(n3526) );
OAI21XLTS U4553 ( .A0(n5184), .A1(n3574), .B0(n3526), .Y(n1265) );
AOI22X1TS U4554 ( .A0(n4890), .A1(FPADDSUB_intDX_EWSW[20]), .B0(
FPADDSUB_DMP_EXP_EWSW[20]), .B1(n4889), .Y(n3527) );
OAI21XLTS U4555 ( .A0(n5145), .A1(n4090), .B0(n3527), .Y(n1229) );
AOI22X1TS U4556 ( .A0(n4828), .A1(FPADDSUB_intDY_EWSW[12]), .B0(
FPADDSUB_DMP_EXP_EWSW[12]), .B1(n4887), .Y(n3528) );
OAI21XLTS U4557 ( .A0(n5076), .A1(n2963), .B0(n3528), .Y(n1269) );
AOI22X1TS U4558 ( .A0(n4892), .A1(FPADDSUB_intDY_EWSW[5]), .B0(
FPADDSUB_DMP_EXP_EWSW[5]), .B1(n4887), .Y(n3529) );
OAI21XLTS U4559 ( .A0(n4944), .A1(n2963), .B0(n3529), .Y(n1275) );
AOI22X1TS U4560 ( .A0(n4890), .A1(FPADDSUB_intDX_EWSW[19]), .B0(
FPADDSUB_DMP_EXP_EWSW[19]), .B1(n4889), .Y(n3530) );
OAI21XLTS U4561 ( .A0(n4942), .A1(n4090), .B0(n3530), .Y(n1225) );
AOI22X1TS U4562 ( .A0(n3572), .A1(FPADDSUB_intDY_EWSW[5]), .B0(
FPADDSUB_DmP_EXP_EWSW[5]), .B1(n3571), .Y(n3531) );
OAI21XLTS U4563 ( .A0(n4944), .A1(n3574), .B0(n3531), .Y(n1277) );
AOI22X1TS U4564 ( .A0(n4890), .A1(FPADDSUB_intDX_EWSW[21]), .B0(
FPADDSUB_DMP_EXP_EWSW[21]), .B1(n4889), .Y(n3532) );
OAI21XLTS U4565 ( .A0(n5142), .A1(n4090), .B0(n3532), .Y(n1221) );
AOI22X1TS U4566 ( .A0(n2964), .A1(FPADDSUB_intDY_EWSW[9]), .B0(
FPADDSUB_DMP_EXP_EWSW[9]), .B1(n3571), .Y(n3533) );
OAI21XLTS U4567 ( .A0(n4940), .A1(n2963), .B0(n3533), .Y(n1282) );
AOI22X1TS U4568 ( .A0(n4828), .A1(FPADDSUB_intDY_EWSW[1]), .B0(
FPADDSUB_DMP_EXP_EWSW[1]), .B1(n3571), .Y(n3534) );
OAI21XLTS U4569 ( .A0(n4939), .A1(n3543), .B0(n3534), .Y(n1289) );
AOI22X1TS U4570 ( .A0(n4890), .A1(FPADDSUB_intDX_EWSW[18]), .B0(
FPADDSUB_DMP_EXP_EWSW[18]), .B1(n4889), .Y(n3535) );
OAI21XLTS U4571 ( .A0(n5017), .A1(n4090), .B0(n3535), .Y(n1217) );
AOI22X1TS U4572 ( .A0(n4892), .A1(FPADDSUB_intDY_EWSW[0]), .B0(
FPADDSUB_DMP_EXP_EWSW[0]), .B1(n3571), .Y(n3536) );
OAI21XLTS U4573 ( .A0(n5105), .A1(n2963), .B0(n3536), .Y(n1296) );
AOI22X1TS U4574 ( .A0(n4890), .A1(FPADDSUB_intDX_EWSW[15]), .B0(
FPADDSUB_DMP_EXP_EWSW[15]), .B1(n4889), .Y(n3537) );
OAI21XLTS U4575 ( .A0(n5090), .A1(n4090), .B0(n3537), .Y(n1213) );
AOI22X1TS U4576 ( .A0(n3572), .A1(FPADDSUB_intDY_EWSW[0]), .B0(
FPADDSUB_DmP_EXP_EWSW[0]), .B1(n3571), .Y(n3538) );
OAI21XLTS U4577 ( .A0(n5105), .A1(n3574), .B0(n3538), .Y(n1298) );
INVX2TS U4578 ( .A(n3543), .Y(n4826) );
AOI22X1TS U4579 ( .A0(n4782), .A1(FPADDSUB_intDX_EWSW[22]), .B0(
FPADDSUB_DMP_EXP_EWSW[22]), .B1(n4825), .Y(n3539) );
OAI21XLTS U4580 ( .A0(n4966), .A1(n3552), .B0(n3539), .Y(n1209) );
AOI22X1TS U4581 ( .A0(n3572), .A1(FPADDSUB_intDX_EWSW[7]), .B0(
FPADDSUB_DMP_EXP_EWSW[7]), .B1(n3571), .Y(n3540) );
OAI21XLTS U4582 ( .A0(n4978), .A1(n3574), .B0(n3540), .Y(n1303) );
AOI22X1TS U4583 ( .A0(n3572), .A1(FPADDSUB_intDY_EWSW[7]), .B0(
FPADDSUB_DmP_EXP_EWSW[7]), .B1(n3571), .Y(n3541) );
OAI21XLTS U4584 ( .A0(n5189), .A1(n3552), .B0(n3541), .Y(n1305) );
AOI22X1TS U4585 ( .A0(n2964), .A1(FPADDSUB_intDY_EWSW[2]), .B0(
FPADDSUB_DMP_EXP_EWSW[2]), .B1(n4825), .Y(n3542) );
AOI22X1TS U4586 ( .A0(n4826), .A1(FPADDSUB_intDX_EWSW[3]), .B0(
FPADDSUB_DMP_EXP_EWSW[3]), .B1(n4825), .Y(n3544) );
OAI21XLTS U4587 ( .A0(n5193), .A1(n3552), .B0(n3544), .Y(n1326) );
AOI22X1TS U4588 ( .A0(n3168), .A1(FPADDSUB_intDY_EWSW[3]), .B0(
FPADDSUB_DmP_EXP_EWSW[3]), .B1(n4825), .Y(n3545) );
OAI21XLTS U4589 ( .A0(n5085), .A1(n3552), .B0(n3545), .Y(n1328) );
AOI22X1TS U4590 ( .A0(n4782), .A1(FPADDSUB_intDY_EWSW[10]), .B0(
FPADDSUB_DmP_EXP_EWSW[10]), .B1(n4825), .Y(n3546) );
OAI21XLTS U4591 ( .A0(n5149), .A1(n3552), .B0(n3546), .Y(n1365) );
AOI22X1TS U4592 ( .A0(n4826), .A1(FPADDSUB_intDY_EWSW[11]), .B0(
FPADDSUB_DmP_EXP_EWSW[11]), .B1(n4825), .Y(n3547) );
OAI21XLTS U4593 ( .A0(n5148), .A1(n3552), .B0(n3547), .Y(n1371) );
AOI22X1TS U4594 ( .A0(n3168), .A1(FPADDSUB_intDY_EWSW[8]), .B0(
FPADDSUB_DmP_EXP_EWSW[8]), .B1(n4825), .Y(n3548) );
OAI21XLTS U4595 ( .A0(n4930), .A1(n3552), .B0(n3548), .Y(n1374) );
AOI22X1TS U4596 ( .A0(n4782), .A1(FPADDSUB_intDY_EWSW[16]), .B0(
FPADDSUB_DmP_EXP_EWSW[16]), .B1(n4825), .Y(n3549) );
OAI21XLTS U4597 ( .A0(n5087), .A1(n3552), .B0(n3549), .Y(n1377) );
AOI22X1TS U4598 ( .A0(n4890), .A1(FPADDSUB_intDX_EWSW[13]), .B0(
FPADDSUB_DMP_EXP_EWSW[13]), .B1(n4887), .Y(n3550) );
AOI22X1TS U4599 ( .A0(n4826), .A1(FPADDSUB_intDY_EWSW[6]), .B0(
FPADDSUB_DmP_EXP_EWSW[6]), .B1(n4781), .Y(n3551) );
OAI21XLTS U4600 ( .A0(n5147), .A1(n3552), .B0(n3551), .Y(n1383) );
AOI22X1TS U4601 ( .A0(n3168), .A1(FPADDSUB_intDY_EWSW[4]), .B0(
FPADDSUB_DmP_EXP_EWSW[4]), .B1(n4781), .Y(n3553) );
OAI21XLTS U4602 ( .A0(n5109), .A1(n3559), .B0(n3553), .Y(n1386) );
AOI22X1TS U4603 ( .A0(n3168), .A1(FPADDSUB_intDY_EWSW[21]), .B0(
FPADDSUB_DmP_EXP_EWSW[21]), .B1(n4781), .Y(n3554) );
OAI21XLTS U4604 ( .A0(n5140), .A1(n3559), .B0(n3554), .Y(n1398) );
AOI22X1TS U4605 ( .A0(n4782), .A1(FPADDSUB_intDY_EWSW[18]), .B0(
FPADDSUB_DmP_EXP_EWSW[18]), .B1(n4781), .Y(n3555) );
OAI21XLTS U4606 ( .A0(n5013), .A1(n3559), .B0(n3555), .Y(n1401) );
AOI22X1TS U4607 ( .A0(n4010), .A1(FPADDSUB_intDX_EWSW[22]), .B0(
FPADDSUB_DmP_EXP_EWSW[22]), .B1(n4781), .Y(n3556) );
OAI21XLTS U4608 ( .A0(n4966), .A1(n4091), .B0(n3556), .Y(n1407) );
AOI22X1TS U4609 ( .A0(n4826), .A1(FPADDSUB_intDX_EWSW[30]), .B0(
FPADDSUB_DMP_EXP_EWSW[30]), .B1(n5023), .Y(n3557) );
OAI21XLTS U4610 ( .A0(n5139), .A1(n3559), .B0(n3557), .Y(n1458) );
AOI22X1TS U4611 ( .A0(n3168), .A1(FPADDSUB_intDX_EWSW[29]), .B0(
FPADDSUB_DMP_EXP_EWSW[29]), .B1(n4765), .Y(n3558) );
OAI222X4TS U4612 ( .A0(FPADDSUB_DmP_mant_SHT1_SW[1]), .A1(n3560), .B0(
FPADDSUB_Raw_mant_NRM_SWR[22]), .B1(n2313), .C0(
FPADDSUB_Raw_mant_NRM_SWR[3]), .C1(n2301), .Y(n3624) );
INVX2TS U4613 ( .A(n3624), .Y(n3567) );
AOI22X1TS U4614 ( .A0(n3612), .A1(FPADDSUB_Data_array_SWR[3]), .B0(n2387),
.B1(n3567), .Y(n3562) );
AOI22X1TS U4615 ( .A0(n2359), .A1(n3613), .B0(n2311), .B1(n3564), .Y(n3561)
);
OAI211XLTS U4616 ( .A0(n3625), .A1(n3563), .B0(n3562), .C0(n3561), .Y(n1790)
);
INVX2TS U4617 ( .A(n3564), .Y(n3570) );
AOI22X1TS U4618 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[2]), .A1(n3565), .B0(
FPADDSUB_DmP_mant_SHT1_SW[0]), .B1(n4958), .Y(n3566) );
AOI22X1TS U4619 ( .A0(n3612), .A1(FPADDSUB_Data_array_SWR[2]), .B0(n2387),
.B1(n3621), .Y(n3569) );
AOI22X1TS U4620 ( .A0(n2359), .A1(n3567), .B0(n2311), .B1(n3613), .Y(n3568)
);
AOI22X1TS U4621 ( .A0(n3572), .A1(FPADDSUB_intDY_EWSW[12]), .B0(
FPADDSUB_DmP_EXP_EWSW[12]), .B1(n3571), .Y(n3573) );
OAI21XLTS U4622 ( .A0(n5076), .A1(n3574), .B0(n3573), .Y(n1271) );
CMPR32X2TS U4623 ( .A(n3577), .B(n3576), .C(n3575), .CO(n2781), .S(n3578) );
INVX2TS U4624 ( .A(n3578), .Y(FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N20) );
CLKBUFX3TS U4625 ( .A(n3579), .Y(n3644) );
CLKBUFX3TS U4626 ( .A(n3632), .Y(n3686) );
AOI222X1TS U4627 ( .A0(n3644), .A1(cordic_result[5]), .B0(n3687), .B1(
FPSENCOS_d_ff_Yn[5]), .C0(n3686), .C1(FPSENCOS_d_ff_Xn[5]), .Y(n3580)
);
INVX2TS U4628 ( .A(n3580), .Y(n1721) );
CLKBUFX3TS U4629 ( .A(n3670), .Y(n3637) );
CLKBUFX3TS U4630 ( .A(n3632), .Y(n3636) );
AOI222X1TS U4631 ( .A0(n3644), .A1(cordic_result[12]), .B0(n3637), .B1(
FPSENCOS_d_ff_Yn[12]), .C0(n3636), .C1(FPSENCOS_d_ff_Xn[12]), .Y(n3581) );
INVX2TS U4632 ( .A(n3581), .Y(n1714) );
CMPR32X2TS U4633 ( .A(n3584), .B(n3583), .C(n3582), .CO(n3588), .S(n3585) );
INVX2TS U4634 ( .A(n3585), .Y(FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N7)
);
AOI222X1TS U4635 ( .A0(n3644), .A1(cordic_result[10]), .B0(n3637), .B1(
FPSENCOS_d_ff_Yn[10]), .C0(n3636), .C1(FPSENCOS_d_ff_Xn[10]), .Y(n3586) );
INVX2TS U4636 ( .A(n3586), .Y(n1716) );
AOI222X1TS U4637 ( .A0(n3638), .A1(cordic_result[14]), .B0(n3637), .B1(
FPSENCOS_d_ff_Yn[14]), .C0(n3636), .C1(FPSENCOS_d_ff_Xn[14]), .Y(n3587) );
INVX2TS U4638 ( .A(n3587), .Y(n1712) );
CMPR32X2TS U4639 ( .A(n3590), .B(n3589), .C(n3588), .CO(n3594), .S(n3591) );
INVX2TS U4640 ( .A(n3591), .Y(FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N8)
);
AOI222X1TS U4641 ( .A0(n3644), .A1(cordic_result[11]), .B0(n3637), .B1(
FPSENCOS_d_ff_Yn[11]), .C0(n3636), .C1(FPSENCOS_d_ff_Xn[11]), .Y(n3592) );
INVX2TS U4642 ( .A(n3592), .Y(n1715) );
AOI222X1TS U4643 ( .A0(n3644), .A1(cordic_result[8]), .B0(n3670), .B1(
FPSENCOS_d_ff_Yn[8]), .C0(n3686), .C1(FPSENCOS_d_ff_Xn[8]), .Y(n3593)
);
INVX2TS U4644 ( .A(n3593), .Y(n1718) );
CMPR32X2TS U4645 ( .A(n3596), .B(n3595), .C(n3594), .CO(n3600), .S(n3597) );
INVX2TS U4646 ( .A(n3597), .Y(FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N9)
);
NOR2X1TS U4647 ( .A(n4187), .B(n4306), .Y(n4058) );
AOI22X1TS U4648 ( .A0(FPSENCOS_d_ff3_LUT_out[4]), .A1(n4313), .B0(
FPSENCOS_cont_iter_out[1]), .B1(n4307), .Y(n3598) );
OAI21XLTS U4649 ( .A0(n4058), .A1(n4291), .B0(n3598), .Y(n2129) );
AOI222X1TS U4650 ( .A0(n3638), .A1(cordic_result[16]), .B0(n3637), .B1(
FPSENCOS_d_ff_Yn[16]), .C0(n3636), .C1(FPSENCOS_d_ff_Xn[16]), .Y(n3599) );
INVX2TS U4651 ( .A(n3599), .Y(n1710) );
CMPR32X2TS U4652 ( .A(n3602), .B(n3601), .C(n3600), .CO(n3606), .S(n3603) );
INVX2TS U4653 ( .A(n3603), .Y(FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N10)
);
AOI222X1TS U4654 ( .A0(n3644), .A1(cordic_result[9]), .B0(n3687), .B1(
FPSENCOS_d_ff_Yn[9]), .C0(n3686), .C1(FPSENCOS_d_ff_Xn[9]), .Y(n3604)
);
INVX2TS U4655 ( .A(n3604), .Y(n1717) );
AOI222X1TS U4656 ( .A0(n3644), .A1(cordic_result[13]), .B0(n3637), .B1(
FPSENCOS_d_ff_Yn[13]), .C0(n3636), .C1(FPSENCOS_d_ff_Xn[13]), .Y(n3605) );
INVX2TS U4657 ( .A(n3605), .Y(n1713) );
CMPR32X2TS U4658 ( .A(n3608), .B(n3607), .C(n3606), .CO(n3640), .S(n3609) );
INVX2TS U4659 ( .A(n3609), .Y(FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N11)
);
AOI222X1TS U4660 ( .A0(n3644), .A1(cordic_result[6]), .B0(n3670), .B1(
FPSENCOS_d_ff_Yn[6]), .C0(n3686), .C1(FPSENCOS_d_ff_Xn[6]), .Y(n3610)
);
INVX2TS U4661 ( .A(n3610), .Y(n1720) );
OAI22X1TS U4662 ( .A0(n4974), .A1(n2312), .B0(n2300), .B1(n5084), .Y(n3620)
);
AOI22X1TS U4663 ( .A0(n3612), .A1(FPADDSUB_Data_array_SWR[1]), .B0(n2387),
.B1(n3620), .Y(n3615) );
AOI22X1TS U4664 ( .A0(n2359), .A1(n3621), .B0(n2293), .B1(n3613), .Y(n3614)
);
OAI211XLTS U4665 ( .A0(n3616), .A1(n3624), .B0(n3615), .C0(n3614), .Y(n1788)
);
AOI222X1TS U4666 ( .A0(n3644), .A1(cordic_result[4]), .B0(n3670), .B1(
FPSENCOS_d_ff_Yn[4]), .C0(n3686), .C1(FPSENCOS_d_ff_Xn[4]), .Y(n3617)
);
INVX2TS U4667 ( .A(n3617), .Y(n1722) );
AOI222X1TS U4668 ( .A0(n3638), .A1(cordic_result[17]), .B0(n3637), .B1(
FPSENCOS_d_ff_Yn[17]), .C0(n3636), .C1(FPSENCOS_d_ff_Xn[17]), .Y(n3618) );
INVX2TS U4669 ( .A(n3618), .Y(n1709) );
AOI22X1TS U4670 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[25]), .A1(n2392), .B0(n3276),
.B1(FPADDSUB_Data_array_SWR[0]), .Y(n3623) );
AOI21X1TS U4671 ( .A0(n2311), .A1(n3621), .B0(n3620), .Y(n3622) );
OAI211XLTS U4672 ( .A0(n3625), .A1(n3624), .B0(n3623), .C0(n3622), .Y(n1787)
);
AOI222X1TS U4673 ( .A0(n3638), .A1(cordic_result[20]), .B0(n3633), .B1(
FPSENCOS_d_ff_Yn[20]), .C0(n3630), .C1(FPSENCOS_d_ff_Xn[20]), .Y(n3626) );
INVX2TS U4674 ( .A(n3626), .Y(n1706) );
AOI211X1TS U4675 ( .A0(n4313), .A1(FPSENCOS_d_ff3_LUT_out[21]), .B0(n4338),
.C0(n3627), .Y(n3628) );
INVX2TS U4676 ( .A(n3628), .Y(n2118) );
AOI222X1TS U4677 ( .A0(n3638), .A1(cordic_result[19]), .B0(n3637), .B1(
FPSENCOS_d_ff_Yn[19]), .C0(n3636), .C1(FPSENCOS_d_ff_Xn[19]), .Y(n3629) );
INVX2TS U4678 ( .A(n3629), .Y(n1707) );
AOI222X1TS U4679 ( .A0(n3638), .A1(cordic_result[21]), .B0(n3633), .B1(
FPSENCOS_d_ff_Yn[21]), .C0(n3630), .C1(FPSENCOS_d_ff_Xn[21]), .Y(n3631) );
INVX2TS U4680 ( .A(n3631), .Y(n1705) );
AOI222X1TS U4681 ( .A0(n3638), .A1(cordic_result[22]), .B0(n3633), .B1(
FPSENCOS_d_ff_Yn[22]), .C0(n3632), .C1(FPSENCOS_d_ff_Xn[22]), .Y(n3634) );
INVX2TS U4682 ( .A(n3634), .Y(n1704) );
AOI222X1TS U4683 ( .A0(n3638), .A1(cordic_result[15]), .B0(n3637), .B1(
FPSENCOS_d_ff_Yn[15]), .C0(n3636), .C1(FPSENCOS_d_ff_Xn[15]), .Y(n3635) );
INVX2TS U4684 ( .A(n3635), .Y(n1711) );
AOI222X1TS U4685 ( .A0(n3638), .A1(cordic_result[18]), .B0(n3637), .B1(
FPSENCOS_d_ff_Yn[18]), .C0(n3636), .C1(FPSENCOS_d_ff_Xn[18]), .Y(n3639) );
INVX2TS U4686 ( .A(n3639), .Y(n1708) );
CMPR32X2TS U4687 ( .A(n3642), .B(n3641), .C(n3640), .CO(n2846), .S(n3643) );
INVX2TS U4688 ( .A(n3643), .Y(FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N12)
);
AOI222X1TS U4689 ( .A0(n3644), .A1(cordic_result[7]), .B0(n3687), .B1(
FPSENCOS_d_ff_Yn[7]), .C0(n3686), .C1(FPSENCOS_d_ff_Xn[7]), .Y(n3645)
);
INVX2TS U4690 ( .A(n3645), .Y(n1719) );
AOI32X1TS U4691 ( .A0(FPADDSUB_intDX_EWSW[31]), .A1(
FPADDSUB_Shift_reg_FLAGS_7_6), .A2(n4016), .B0(FPADDSUB_OP_FLAG_EXP),
.B1(n4889), .Y(n3646) );
OAI31X1TS U4692 ( .A0(FPADDSUB_intDX_EWSW[31]), .A1(n4889), .A2(n4016), .B0(
n3646), .Y(n1355) );
CMPR32X2TS U4693 ( .A(n3649), .B(n3648), .C(n3647), .CO(n4498), .S(n3650) );
INVX2TS U4694 ( .A(n3650), .Y(FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N21)
);
CMPR32X2TS U4695 ( .A(n3653), .B(n3652), .C(n3651), .CO(n2795), .S(n3654) );
INVX2TS U4696 ( .A(n3654), .Y(FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N16) );
AOI222X1TS U4697 ( .A0(n4215), .A1(FPSENCOS_d_ff2_Z[0]), .B0(n3655), .B1(
FPSENCOS_d_ff1_Z[0]), .C0(FPSENCOS_d_ff_Zn[0]), .C1(n4279), .Y(n3656)
);
INVX2TS U4698 ( .A(n3656), .Y(n1764) );
CMPR32X2TS U4699 ( .A(n3659), .B(n3658), .C(n3657), .CO(n2834), .S(n3660) );
INVX2TS U4700 ( .A(n3660), .Y(FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N17)
);
AOI222X1TS U4701 ( .A0(n2474), .A1(cordic_result[2]), .B0(n3670), .B1(
FPSENCOS_d_ff_Yn[2]), .C0(n3686), .C1(FPSENCOS_d_ff_Xn[2]), .Y(n3661)
);
INVX2TS U4702 ( .A(n3661), .Y(n1724) );
CMPR32X2TS U4703 ( .A(n3664), .B(n3663), .C(n3662), .CO(n3575), .S(n3665) );
INVX2TS U4704 ( .A(n3665), .Y(FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N19) );
CMPR32X2TS U4705 ( .A(n3668), .B(n3667), .C(n3666), .CO(n2838), .S(n3669) );
INVX2TS U4706 ( .A(n3669), .Y(FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N15)
);
AOI222X1TS U4707 ( .A0(n3671), .A1(cordic_result[0]), .B0(n3670), .B1(
FPSENCOS_d_ff_Yn[0]), .C0(n3686), .C1(FPSENCOS_d_ff_Xn[0]), .Y(n3672)
);
INVX2TS U4708 ( .A(n3672), .Y(n1726) );
CMPR32X2TS U4709 ( .A(n3675), .B(n3674), .C(n3673), .CO(n2830), .S(n3676) );
INVX2TS U4710 ( .A(n3676), .Y(FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N19)
);
CMPR32X2TS U4711 ( .A(n3679), .B(n3678), .C(n3677), .CO(n2767), .S(n3680) );
INVX2TS U4712 ( .A(n3680), .Y(FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N13) );
CMPR32X2TS U4713 ( .A(n3683), .B(n3682), .C(n3681), .CO(n3662), .S(n3684) );
INVX2TS U4714 ( .A(n3684), .Y(FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N18) );
AOI222X1TS U4715 ( .A0(n3579), .A1(cordic_result[1]), .B0(n3687), .B1(
FPSENCOS_d_ff_Yn[1]), .C0(n3686), .C1(FPSENCOS_d_ff_Xn[1]), .Y(n3685)
);
INVX2TS U4716 ( .A(n3685), .Y(n1725) );
AOI222X1TS U4717 ( .A0(n3579), .A1(cordic_result[3]), .B0(n3687), .B1(
FPSENCOS_d_ff_Yn[3]), .C0(n3686), .C1(FPSENCOS_d_ff_Xn[3]), .Y(n3688)
);
INVX2TS U4718 ( .A(n3688), .Y(n1723) );
CMPR32X2TS U4719 ( .A(FPMULT_Op_MY[10]), .B(FPMULT_Op_MY[22]), .C(n3689),
.CO(n3210), .S(n4616) );
INVX2TS U4720 ( .A(n4616), .Y(n4617) );
AOI22X1TS U4721 ( .A0(n2326), .A1(n4616), .B0(n4617), .B1(n2390), .Y(n4378)
);
AOI22X1TS U4722 ( .A0(n2286), .A1(n3690), .B0(n4412), .B1(n4378), .Y(n3695)
);
INVX2TS U4723 ( .A(n3691), .Y(n3694) );
INVX2TS U4724 ( .A(n3692), .Y(DP_OP_454J200_123_2743_n52) );
AOI21X1TS U4725 ( .A0(n2240), .A1(n4612), .B0(n2317), .Y(n3834) );
AOI22X1TS U4726 ( .A0(n2326), .A1(n4622), .B0(n4623), .B1(n2390), .Y(n3756)
);
AOI22X1TS U4727 ( .A0(n4566), .A1(n2326), .B0(n2325), .B1(n4565), .Y(n3706)
);
AOI22X1TS U4728 ( .A0(n2286), .A1(n3756), .B0(n4412), .B1(n3706), .Y(n3712)
);
INVX2TS U4729 ( .A(n3693), .Y(DP_OP_454J200_123_2743_n76) );
CMPR32X2TS U4730 ( .A(n3696), .B(n3695), .C(n3694), .CO(n3697), .S(n3692) );
INVX2TS U4731 ( .A(n3697), .Y(DP_OP_454J200_123_2743_n51) );
NOR2X1TS U4732 ( .A(n2319), .B(n5040), .Y(n3699) );
AOI22X1TS U4733 ( .A0(FPMULT_Op_MY[6]), .A1(n2318), .B0(n3699), .B1(n2399),
.Y(n3698) );
OAI21X1TS U4734 ( .A0(n3699), .A1(n2400), .B0(n3698), .Y(n3823) );
NOR3X2TS U4735 ( .A(mult_x_254_n196), .B(n3823), .C(mult_x_254_n183), .Y(
mult_x_254_n129) );
INVX2TS U4736 ( .A(n4619), .Y(n4620) );
AOI22X1TS U4737 ( .A0(n2356), .A1(n4619), .B0(n4620), .B1(n2355), .Y(n4603)
);
AOI22X1TS U4738 ( .A0(n2356), .A1(n4622), .B0(n4623), .B1(n2276), .Y(n3702)
);
AOI22X1TS U4739 ( .A0(n2347), .A1(n4603), .B0(n4606), .B1(n3702), .Y(n3769)
);
AOI22X1TS U4740 ( .A0(n4566), .A1(n2352), .B0(n2350), .B1(n4565), .Y(n3714)
);
AOI22X1TS U4741 ( .A0(n4569), .A1(n2352), .B0(n2285), .B1(n4568), .Y(n3704)
);
AOI22X1TS U4742 ( .A0(n4417), .A1(n3714), .B0(n3704), .B1(n4595), .Y(n3768)
);
AOI2BB2XLTS U4743 ( .B0(n2347), .B1(n3702), .A0N(n4608), .A1N(n3701), .Y(
n3740) );
AOI2BB2XLTS U4744 ( .B0(n4417), .B1(n3704), .A0N(n4594), .A1N(n3703), .Y(
n3739) );
INVX2TS U4745 ( .A(n3705), .Y(DP_OP_454J200_123_2743_n103) );
AOI22X1TS U4746 ( .A0(n2351), .A1(n4619), .B0(n4620), .B1(n2285), .Y(n4596)
);
AOI22X1TS U4747 ( .A0(n2351), .A1(n4622), .B0(n4623), .B1(n2285), .Y(n3715)
);
AOI22X1TS U4748 ( .A0(n4417), .A1(n4596), .B0(n3715), .B1(n4595), .Y(n3761)
);
AOI22X1TS U4749 ( .A0(n4569), .A1(n2327), .B0(n2390), .B1(n4568), .Y(n3716)
);
AOI22X1TS U4750 ( .A0(n2286), .A1(n3706), .B0(n4412), .B1(n3716), .Y(n3760)
);
INVX2TS U4751 ( .A(n3707), .Y(DP_OP_454J200_123_2743_n84) );
NOR2X1TS U4752 ( .A(n2379), .B(n4464), .Y(mult_x_219_n151) );
CMPR32X2TS U4753 ( .A(n3710), .B(n3709), .C(n3708), .CO(n3711), .S(n3204) );
INVX2TS U4754 ( .A(n3711), .Y(mult_x_254_n117) );
CMPR32X2TS U4755 ( .A(n4634), .B(n3834), .C(n3712), .CO(n3713), .S(n3693) );
INVX2TS U4756 ( .A(n3713), .Y(DP_OP_454J200_123_2743_n75) );
AOI22X1TS U4757 ( .A0(n4417), .A1(n3715), .B0(n3714), .B1(n4595), .Y(n3772)
);
AOI22X1TS U4758 ( .A0(n4572), .A1(n2327), .B0(n2325), .B1(n4571), .Y(n4410)
);
AOI22X1TS U4759 ( .A0(n2286), .A1(n3716), .B0(n4412), .B1(n4410), .Y(n3771)
);
INVX2TS U4760 ( .A(n3717), .Y(DP_OP_454J200_123_2743_n94) );
AOI22X1TS U4761 ( .A0(n4640), .A1(n3758), .B0(n3846), .B1(n4635), .Y(n3718)
);
OAI21X1TS U4762 ( .A0(n4616), .A1(n2244), .B0(n3718), .Y(
DP_OP_454J200_123_2743_n247) );
INVX2TS U4763 ( .A(n3721), .Y(mult_x_219_n48) );
CMPR32X2TS U4764 ( .A(n3724), .B(n3723), .C(n3722), .CO(n3725), .S(n3194) );
INVX2TS U4765 ( .A(n3725), .Y(mult_x_219_n117) );
CMPR32X2TS U4766 ( .A(n3728), .B(n3727), .C(n3726), .CO(n2733), .S(n3729) );
INVX2TS U4767 ( .A(n3729), .Y(DP_OP_454J200_123_2743_n130) );
INVX2TS U4768 ( .A(n3732), .Y(mult_x_254_n48) );
AOI22X1TS U4769 ( .A0(FPMULT_Op_MY[7]), .A1(n2308), .B0(n2278), .B1(n5040),
.Y(n4428) );
AOI22X1TS U4770 ( .A0(n2368), .A1(n2277), .B0(n2309), .B1(n5049), .Y(n4396)
);
AOI2BB2XLTS U4771 ( .B0(n4427), .B1(n4428), .A0N(n4526), .A1N(n4396), .Y(
n3749) );
INVX2TS U4772 ( .A(n3733), .Y(mult_x_254_n79) );
CMPR32X2TS U4773 ( .A(n3735), .B(n4449), .C(n3734), .CO(n3736), .S(n2718) );
INVX2TS U4774 ( .A(n3736), .Y(mult_x_219_n124) );
NOR2X1TS U4775 ( .A(n5038), .B(n2367), .Y(mult_x_254_n151) );
NAND2X1TS U4776 ( .A(n2237), .B(FPMULT_Op_MY[10]), .Y(n3738) );
OAI211XLTS U4777 ( .A0(n5035), .A1(FPMULT_Op_MX[0]), .B0(n3738), .C0(n2400),
.Y(n3737) );
OAI21X1TS U4778 ( .A0(n2399), .A1(n3738), .B0(n3737), .Y(mult_x_254_n228) );
CMPR32X2TS U4779 ( .A(n3741), .B(n3740), .C(n3739), .CO(n3767), .S(n3742) );
INVX2TS U4780 ( .A(n3742), .Y(DP_OP_454J200_123_2743_n111) );
AOI22X1TS U4781 ( .A0(n4401), .A1(n4960), .B0(n3821), .B1(n5037), .Y(n3743)
);
OAI21X1TS U4782 ( .A0(n4960), .A1(n3745), .B0(n3743), .Y(mult_x_219_n222) );
AOI22X1TS U4783 ( .A0(n4401), .A1(n4961), .B0(n3821), .B1(n5039), .Y(n3744)
);
OAI21X1TS U4784 ( .A0(n4961), .A1(n3745), .B0(n3744), .Y(mult_x_219_n226) );
CMPR32X2TS U4785 ( .A(n4504), .B(n3747), .C(n3746), .CO(n3748), .S(n2725) );
INVX2TS U4786 ( .A(n3748), .Y(mult_x_254_n124) );
CMPR32X2TS U4787 ( .A(n4507), .B(n3750), .C(n3749), .CO(n3733), .S(n3751) );
INVX2TS U4788 ( .A(n3751), .Y(mult_x_254_n80) );
CMPR32X2TS U4789 ( .A(FPMULT_Op_MX[10]), .B(n2380), .C(n3752), .CO(n3856),
.S(n3858) );
INVX2TS U4790 ( .A(n2302), .Y(n4641) );
NOR2X1TS U4791 ( .A(n2228), .B(n2257), .Y(DP_OP_454J200_123_2743_n172) );
AOI22X1TS U4792 ( .A0(n4566), .A1(n3846), .B0(n3758), .B1(n4565), .Y(n3753)
);
OAI21X1TS U4793 ( .A0(n4569), .A1(n2244), .B0(n3753), .Y(
DP_OP_454J200_123_2743_n251) );
OAI21X1TS U4794 ( .A0(n4414), .A1(n3755), .B0(n3754), .Y(
DP_OP_454J200_123_2743_n42) );
INVX2TS U4795 ( .A(DP_OP_454J200_123_2743_n42), .Y(
DP_OP_454J200_123_2743_n41) );
AOI22X1TS U4796 ( .A0(n2326), .A1(n4619), .B0(n4620), .B1(n2390), .Y(n4377)
);
AOI22X1TS U4797 ( .A0(n4414), .A1(n4377), .B0(n4412), .B1(n3756), .Y(
DP_OP_454J200_123_2743_n68) );
INVX2TS U4798 ( .A(DP_OP_454J200_123_2743_n68), .Y(
DP_OP_454J200_123_2743_n67) );
AOI22X1TS U4799 ( .A0(n4619), .A1(n3846), .B0(n3758), .B1(n4620), .Y(n3757)
);
OAI21X1TS U4800 ( .A0(n4622), .A1(n2244), .B0(n3757), .Y(
DP_OP_454J200_123_2743_n249) );
AOI22X1TS U4801 ( .A0(n4616), .A1(n3846), .B0(n3758), .B1(n4617), .Y(n3759)
);
OAI21X1TS U4802 ( .A0(n4619), .A1(n2244), .B0(n3759), .Y(
DP_OP_454J200_123_2743_n248) );
CMPR32X2TS U4803 ( .A(n2239), .B(n3761), .C(n3760), .CO(n3762), .S(n3707) );
INVX2TS U4804 ( .A(n3762), .Y(DP_OP_454J200_123_2743_n83) );
CMPR32X2TS U4805 ( .A(n3765), .B(n3764), .C(n3763), .CO(n3726), .S(n3766) );
INVX2TS U4806 ( .A(n3766), .Y(DP_OP_454J200_123_2743_n137) );
CMPR32X2TS U4807 ( .A(n3769), .B(n3768), .C(n3767), .CO(n3770), .S(n3705) );
INVX2TS U4808 ( .A(n3770), .Y(DP_OP_454J200_123_2743_n102) );
CMPR32X2TS U4809 ( .A(n2239), .B(n3772), .C(n3771), .CO(n3773), .S(n3717) );
INVX2TS U4810 ( .A(n3773), .Y(DP_OP_454J200_123_2743_n93) );
INVX2TS U4811 ( .A(mult_x_254_n64), .Y(mult_x_254_n63) );
NOR2X1TS U4812 ( .A(n5035), .B(n2366), .Y(mult_x_254_n149) );
INVX2TS U4813 ( .A(mult_x_254_n38), .Y(mult_x_254_n37) );
INVX2TS U4814 ( .A(n3813), .Y(n3799) );
CLKBUFX2TS U4815 ( .A(n3799), .Y(n3795) );
AOI22X1TS U4816 ( .A0(cordic_result[0]), .A1(n3774), .B0(n4705), .B1(
mult_result[0]), .Y(n3775) );
AOI22X1TS U4817 ( .A0(cordic_result[1]), .A1(n3774), .B0(n4705), .B1(
mult_result[1]), .Y(n3776) );
OAI21XLTS U4818 ( .A0(n3799), .A1(n5069), .B0(n3776), .Y(op_result[1]) );
CLKBUFX3TS U4819 ( .A(n3774), .Y(n3793) );
CLKBUFX3TS U4820 ( .A(n3817), .Y(n3792) );
AOI22X1TS U4821 ( .A0(cordic_result[3]), .A1(n3793), .B0(n3792), .B1(
mult_result[3]), .Y(n3777) );
OAI21XLTS U4822 ( .A0(n3799), .A1(n5066), .B0(n3777), .Y(op_result[3]) );
AOI22X1TS U4823 ( .A0(cordic_result[4]), .A1(n3793), .B0(n3792), .B1(
mult_result[4]), .Y(n3778) );
OAI21XLTS U4824 ( .A0(n3799), .A1(n5099), .B0(n3778), .Y(op_result[4]) );
AOI22X1TS U4825 ( .A0(cordic_result[5]), .A1(n3793), .B0(n3792), .B1(
mult_result[5]), .Y(n3779) );
OAI21XLTS U4826 ( .A0(n3795), .A1(n5070), .B0(n3779), .Y(op_result[5]) );
AOI22X1TS U4827 ( .A0(cordic_result[6]), .A1(n3793), .B0(n3792), .B1(
mult_result[6]), .Y(n3780) );
OAI21XLTS U4828 ( .A0(n3799), .A1(n5060), .B0(n3780), .Y(op_result[6]) );
AOI22X1TS U4829 ( .A0(cordic_result[7]), .A1(n3793), .B0(n3792), .B1(
mult_result[7]), .Y(n3781) );
OAI21XLTS U4830 ( .A0(n3795), .A1(n5068), .B0(n3781), .Y(op_result[7]) );
AOI22X1TS U4831 ( .A0(cordic_result[8]), .A1(n3793), .B0(n3792), .B1(
mult_result[8]), .Y(n3782) );
OAI21XLTS U4832 ( .A0(n3799), .A1(n5100), .B0(n3782), .Y(op_result[8]) );
AOI22X1TS U4833 ( .A0(cordic_result[9]), .A1(n3793), .B0(n3792), .B1(
mult_result[9]), .Y(n3783) );
OAI21XLTS U4834 ( .A0(n3795), .A1(n5103), .B0(n3783), .Y(op_result[9]) );
AOI22X1TS U4835 ( .A0(cordic_result[10]), .A1(n3793), .B0(n3792), .B1(
mult_result[10]), .Y(n3784) );
OAI21XLTS U4836 ( .A0(n3795), .A1(n5064), .B0(n3784), .Y(op_result[10]) );
AOI22X1TS U4837 ( .A0(cordic_result[11]), .A1(n3793), .B0(n3792), .B1(
mult_result[11]), .Y(n3785) );
OAI21XLTS U4838 ( .A0(n3795), .A1(n5101), .B0(n3785), .Y(op_result[11]) );
CLKBUFX3TS U4839 ( .A(n3795), .Y(n3820) );
CLKBUFX3TS U4840 ( .A(n3774), .Y(n3818) );
AOI22X1TS U4841 ( .A0(cordic_result[12]), .A1(n3818), .B0(n3817), .B1(
mult_result[12]), .Y(n3786) );
OAI21XLTS U4842 ( .A0(n3820), .A1(n5065), .B0(n3786), .Y(op_result[12]) );
AOI22X1TS U4843 ( .A0(cordic_result[13]), .A1(n3818), .B0(n3817), .B1(
mult_result[13]), .Y(n3787) );
OAI21XLTS U4844 ( .A0(n3820), .A1(n5061), .B0(n3787), .Y(op_result[13]) );
AOI22X1TS U4845 ( .A0(cordic_result[14]), .A1(n3818), .B0(n4705), .B1(
mult_result[14]), .Y(n3788) );
OAI21XLTS U4846 ( .A0(n3820), .A1(n5063), .B0(n3788), .Y(op_result[14]) );
AOI22X1TS U4847 ( .A0(cordic_result[15]), .A1(n3818), .B0(n3817), .B1(
mult_result[15]), .Y(n3789) );
OAI21XLTS U4848 ( .A0(n3820), .A1(n5096), .B0(n3789), .Y(op_result[15]) );
AOI22X1TS U4849 ( .A0(cordic_result[16]), .A1(n3818), .B0(n4705), .B1(
mult_result[16]), .Y(n3790) );
OAI21XLTS U4850 ( .A0(n3820), .A1(n5062), .B0(n3790), .Y(op_result[16]) );
AOI22X1TS U4851 ( .A0(cordic_result[17]), .A1(n3818), .B0(n3817), .B1(
mult_result[17]), .Y(n3791) );
AOI22X1TS U4852 ( .A0(cordic_result[2]), .A1(n3793), .B0(n3792), .B1(
mult_result[2]), .Y(n3794) );
AOI22X1TS U4853 ( .A0(cordic_result[19]), .A1(n3818), .B0(n3817), .B1(
mult_result[19]), .Y(n3796) );
OAI21XLTS U4854 ( .A0(n3820), .A1(n5057), .B0(n3796), .Y(op_result[19]) );
AOI22X1TS U4855 ( .A0(cordic_result[20]), .A1(n3818), .B0(n4705), .B1(
mult_result[20]), .Y(n3797) );
OAI21XLTS U4856 ( .A0(n3820), .A1(n5058), .B0(n3797), .Y(op_result[20]) );
AOI22X1TS U4857 ( .A0(cordic_result[21]), .A1(n3818), .B0(n4705), .B1(
mult_result[21]), .Y(n3798) );
OAI21XLTS U4858 ( .A0(n3820), .A1(n5098), .B0(n3798), .Y(op_result[21]) );
CLKBUFX3TS U4859 ( .A(n3799), .Y(n3812) );
CLKBUFX3TS U4860 ( .A(n3774), .Y(n3810) );
CLKBUFX3TS U4861 ( .A(n3817), .Y(n3809) );
AOI22X1TS U4862 ( .A0(cordic_result[22]), .A1(n3810), .B0(n3809), .B1(
mult_result[22]), .Y(n3800) );
OAI21XLTS U4863 ( .A0(n3812), .A1(n5095), .B0(n3800), .Y(op_result[22]) );
AOI22X1TS U4864 ( .A0(cordic_result[23]), .A1(n3810), .B0(n3809), .B1(
mult_result[23]), .Y(n3801) );
OAI21XLTS U4865 ( .A0(n3812), .A1(n5194), .B0(n3801), .Y(op_result[23]) );
AOI22X1TS U4866 ( .A0(cordic_result[24]), .A1(n3810), .B0(n3809), .B1(
mult_result[24]), .Y(n3802) );
OAI21XLTS U4867 ( .A0(n3812), .A1(n5091), .B0(n3802), .Y(op_result[24]) );
AOI22X1TS U4868 ( .A0(cordic_result[25]), .A1(n3810), .B0(n3809), .B1(
mult_result[25]), .Y(n3803) );
OAI21XLTS U4869 ( .A0(n3812), .A1(n5092), .B0(n3803), .Y(op_result[25]) );
AOI22X1TS U4870 ( .A0(cordic_result[26]), .A1(n3810), .B0(n3809), .B1(
mult_result[26]), .Y(n3804) );
OAI21XLTS U4871 ( .A0(n3812), .A1(n5071), .B0(n3804), .Y(op_result[26]) );
AOI22X1TS U4872 ( .A0(cordic_result[27]), .A1(n3810), .B0(n3809), .B1(
mult_result[27]), .Y(n3805) );
OAI21XLTS U4873 ( .A0(n3812), .A1(n5093), .B0(n3805), .Y(op_result[27]) );
AOI22X1TS U4874 ( .A0(cordic_result[28]), .A1(n3810), .B0(n3809), .B1(
mult_result[28]), .Y(n3806) );
OAI21XLTS U4875 ( .A0(n3812), .A1(n4976), .B0(n3806), .Y(op_result[28]) );
AOI22X1TS U4876 ( .A0(cordic_result[29]), .A1(n3810), .B0(n3809), .B1(
mult_result[29]), .Y(n3807) );
OAI21XLTS U4877 ( .A0(n3812), .A1(n5094), .B0(n3807), .Y(op_result[29]) );
AOI22X1TS U4878 ( .A0(cordic_result[30]), .A1(n3810), .B0(n3809), .B1(
mult_result[30]), .Y(n3808) );
OAI21XLTS U4879 ( .A0(n3812), .A1(n5195), .B0(n3808), .Y(op_result[30]) );
AOI22X1TS U4880 ( .A0(cordic_result[31]), .A1(n3810), .B0(n3809), .B1(
mult_result[31]), .Y(n3811) );
OAI21XLTS U4881 ( .A0(n3812), .A1(n5120), .B0(n3811), .Y(op_result[31]) );
AOI22X1TS U4882 ( .A0(n3813), .A1(ready_add_subt), .B0(n3991), .B1(n3774),
.Y(n3814) );
AOI22X1TS U4883 ( .A0(cordic_result[18]), .A1(n3818), .B0(n3817), .B1(
mult_result[18]), .Y(n3819) );
OAI21XLTS U4884 ( .A0(n3820), .A1(n5097), .B0(n3819), .Y(op_result[18]) );
AOI22X1TS U4885 ( .A0(FPMULT_Op_MX[13]), .A1(FPMULT_Op_MY[19]), .B0(n5033),
.B1(n4962), .Y(n3822) );
AOI22X1TS U4886 ( .A0(FPMULT_Op_MX[12]), .A1(n3822), .B0(n3821), .B1(n4961),
.Y(n4454) );
OAI32X1TS U4887 ( .A0(n2306), .A1(n2348), .A2(n5080), .B0(n4484), .B1(n2297),
.Y(mult_x_219_n192) );
NOR2X1TS U4888 ( .A(n5040), .B(n4926), .Y(n4383) );
AOI21X1TS U4889 ( .A0(n5040), .A1(n2367), .B0(n4383), .Y(n4429) );
AOI21X1TS U4890 ( .A0(n5042), .A1(n2367), .B0(n4384), .Y(n4079) );
AO22XLTS U4891 ( .A0(n2247), .A1(n4429), .B0(n2233), .B1(n4079), .Y(
mult_x_254_n161) );
OAI32X1TS U4892 ( .A0(mult_x_254_n129), .A1(mult_x_254_n196), .A2(
mult_x_254_n183), .B0(n3823), .B1(mult_x_254_n129), .Y(mult_x_254_n130) );
AOI2BB1XLTS U4893 ( .A0N(n3826), .A1N(n3825), .B0(n3824), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N2) );
NAND2X1TS U4894 ( .A(n3828), .B(n3827), .Y(n3832) );
NAND2X1TS U4895 ( .A(n3830), .B(n3829), .Y(n3831) );
XOR2XLTS U4896 ( .A(n3832), .B(n3831), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N3) );
CLKBUFX3TS U4897 ( .A(n4687), .Y(n4374) );
AO22XLTS U4898 ( .A0(FPSENCOS_d_ff2_Y[23]), .A1(n4688), .B0(
FPSENCOS_d_ff_Yn[23]), .B1(n4374), .Y(n1861) );
OAI22X1TS U4899 ( .A0(n4578), .A1(n3844), .B0(n4581), .B1(n2243), .Y(n3833)
);
AOI21X1TS U4900 ( .A0(n4578), .A1(n3846), .B0(n3833), .Y(n3839) );
AOI22X1TS U4901 ( .A0(n2339), .A1(n4584), .B0(n4583), .B1(n2316), .Y(n3847)
);
AOI22X1TS U4902 ( .A0(n2339), .A1(n4587), .B0(n2256), .B1(n2316), .Y(n3866)
);
AOI22X1TS U4903 ( .A0(n3849), .A1(n3847), .B0(n3866), .B1(n4629), .Y(n3838)
);
XOR2X1TS U4904 ( .A(n3839), .B(n3838), .Y(n3855) );
INVX2TS U4905 ( .A(n3834), .Y(n4613) );
CMPR32X2TS U4906 ( .A(n3835), .B(n3837), .C(n3836), .CO(n3840), .S(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N2) );
NAND3X1TS U4907 ( .A(n3837), .B(n3841), .C(n3836), .Y(n3861) );
OAI21X1TS U4908 ( .A0(n3841), .A1(n3840), .B0(n3861), .Y(n3854) );
NOR2X1TS U4909 ( .A(n3855), .B(n3854), .Y(n3853) );
NOR2XLTS U4910 ( .A(n3841), .B(n3840), .Y(n3843) );
NAND2X1TS U4911 ( .A(n3860), .B(n3861), .Y(n3842) );
OAI31X1TS U4912 ( .A0(n3853), .A1(n3860), .A2(n3843), .B0(n3842), .Y(n3852)
);
OAI22X1TS U4913 ( .A0(n4578), .A1(n2243), .B0(n4575), .B1(n3844), .Y(n3845)
);
AOI21X1TS U4914 ( .A0(n3846), .A1(n4575), .B0(n3845), .Y(n3870) );
NAND2X1TS U4915 ( .A(n4587), .B(n2347), .Y(n3867) );
AOI22X1TS U4916 ( .A0(n3849), .A1(n3848), .B0(n3847), .B1(n4629), .Y(n3869)
);
INVX2TS U4917 ( .A(n3850), .Y(n3851) );
NAND2X1TS U4918 ( .A(n3851), .B(n3852), .Y(n3862) );
OA21XLTS U4919 ( .A0(n3852), .A1(n3851), .B0(n3862), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N4) );
AO21XLTS U4920 ( .A0(n3855), .A1(n3854), .B0(n3853), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N3) );
AOI22X1TS U4921 ( .A0(n4641), .A1(n4617), .B0(n4640), .B1(n2302), .Y(n4644)
);
INVX2TS U4922 ( .A(n4644), .Y(n4643) );
NOR2XLTS U4923 ( .A(n2327), .B(n3858), .Y(n3857) );
AOI32X4TS U4924 ( .A0(n3858), .A1(n2294), .A2(n2327), .B0(n3857), .B1(n2383),
.Y(n4590) );
AOI22X1TS U4925 ( .A0(n2245), .A1(n2382), .B0(n2294), .B1(n4633), .Y(n4561)
);
OAI22X1TS U4926 ( .A0(n4590), .A1(n4561), .B0(n2381), .B1(n2282), .Y(n4642)
);
NAND2X1TS U4927 ( .A(n2383), .B(n3859), .Y(n4646) );
NOR2XLTS U4928 ( .A(DP_OP_454J200_123_2743_n187), .B(n4646), .Y(n3888) );
NAND2BXLTS U4929 ( .AN(n3861), .B(n3860), .Y(n3863) );
NAND2X1TS U4930 ( .A(n3863), .B(n3862), .Y(n3922) );
AOI21X1TS U4931 ( .A0(n3865), .A1(n3864), .B0(DP_OP_454J200_123_2743_n148),
.Y(n3921) );
AOI22X1TS U4932 ( .A0(n4584), .A1(n2355), .B0(n2357), .B1(n4583), .Y(n4609)
);
OAI22X1TS U4933 ( .A0(n3866), .A1(n4608), .B0(n4609), .B1(n4611), .Y(n3872)
);
NAND2BX1TS U4934 ( .AN(DP_OP_454J200_123_2743_n215), .B(n3867), .Y(n3874) );
CMPR32X2TS U4935 ( .A(n3870), .B(n3867), .C(n3869), .CO(n3875), .S(n3850) );
NAND2X1TS U4936 ( .A(n3875), .B(n3874), .Y(n3868) );
OAI31X1TS U4937 ( .A0(n3870), .A1(n3869), .A2(n3874), .B0(n3868), .Y(n3871)
);
NOR2X1TS U4938 ( .A(n3872), .B(n3871), .Y(n3873) );
AO21XLTS U4939 ( .A0(n3872), .A1(n3871), .B0(n3873), .Y(n3920) );
AOI21X1TS U4940 ( .A0(n3875), .A1(n3874), .B0(n3873), .Y(n3918) );
CMPR32X2TS U4941 ( .A(DP_OP_454J200_123_2743_n39), .B(
DP_OP_454J200_123_2743_n37), .C(n3876), .CO(n4638), .S(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N22) );
CMPR32X2TS U4942 ( .A(DP_OP_454J200_123_2743_n44), .B(
DP_OP_454J200_123_2743_n40), .C(n3877), .CO(n3876), .S(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N21) );
CMPR32X2TS U4943 ( .A(DP_OP_454J200_123_2743_n45), .B(
DP_OP_454J200_123_2743_n49), .C(n3878), .CO(n3877), .S(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N20) );
CMPR32X2TS U4944 ( .A(DP_OP_454J200_123_2743_n56), .B(
DP_OP_454J200_123_2743_n50), .C(n3879), .CO(n3878), .S(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N19) );
CMPR32X2TS U4945 ( .A(DP_OP_454J200_123_2743_n62), .B(
DP_OP_454J200_123_2743_n57), .C(n3880), .CO(n3879), .S(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N18) );
CMPR32X2TS U4946 ( .A(DP_OP_454J200_123_2743_n70), .B(
DP_OP_454J200_123_2743_n63), .C(n3881), .CO(n3880), .S(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N17) );
CMPR32X2TS U4947 ( .A(DP_OP_454J200_123_2743_n78), .B(
DP_OP_454J200_123_2743_n71), .C(n3882), .CO(n3881), .S(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N16) );
CMPR32X2TS U4948 ( .A(DP_OP_454J200_123_2743_n88), .B(
DP_OP_454J200_123_2743_n79), .C(n3883), .CO(n3882), .S(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N15) );
CMPR32X2TS U4949 ( .A(DP_OP_454J200_123_2743_n97), .B(
DP_OP_454J200_123_2743_n89), .C(n3884), .CO(n3883), .S(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N14) );
CMPR32X2TS U4950 ( .A(DP_OP_454J200_123_2743_n105), .B(
DP_OP_454J200_123_2743_n98), .C(n3885), .CO(n3884), .S(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N13) );
CMPR32X2TS U4951 ( .A(DP_OP_454J200_123_2743_n113), .B(
DP_OP_454J200_123_2743_n106), .C(n3886), .CO(n3885), .S(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N12) );
CMPR32X2TS U4952 ( .A(DP_OP_454J200_123_2743_n114), .B(n3888), .C(n3887),
.CO(n3886), .S(FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N11) );
CMPR32X2TS U4953 ( .A(DP_OP_454J200_123_2743_n127), .B(
DP_OP_454J200_123_2743_n122), .C(n3889), .CO(n3887), .S(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N10) );
CMPR32X2TS U4954 ( .A(DP_OP_454J200_123_2743_n134), .B(
DP_OP_454J200_123_2743_n128), .C(n3890), .CO(n3889), .S(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N9) );
NAND2X1TS U4955 ( .A(n5052), .B(n5205), .Y(n4707) );
NOR2XLTS U4956 ( .A(n5205), .B(n4965), .Y(n3891) );
OAI222X1TS U4957 ( .A0(n3893), .A1(n3892), .B0(n4936), .B1(n4707), .C0(n3928), .C1(n3891), .Y(n1691) );
NOR3XLTS U4958 ( .A(FPMULT_Exp_module_Data_S[7]), .B(
FPMULT_Exp_module_Data_S[8]), .C(n4120), .Y(n3896) );
AND4X1TS U4959 ( .A(FPMULT_Exp_module_Data_S[6]), .B(
FPMULT_Exp_module_Data_S[3]), .C(FPMULT_Exp_module_Data_S[2]), .D(
FPMULT_Exp_module_Data_S[1]), .Y(n3894) );
NAND4XLTS U4960 ( .A(FPMULT_Exp_module_Data_S[5]), .B(
FPMULT_Exp_module_Data_S[4]), .C(FPMULT_Exp_module_Data_S[0]), .D(
n3894), .Y(n3895) );
AO22XLTS U4961 ( .A0(n3896), .A1(n3895), .B0(underflow_flag_mult), .B1(n4120), .Y(n1586) );
AOI22X1TS U4962 ( .A0(FPADDSUB_intDY_EWSW[19]), .A1(n4172), .B0(n4171), .B1(
Data_2[19]), .Y(n3898) );
AOI22X1TS U4963 ( .A0(n4174), .A1(FPSENCOS_d_ff3_sh_y_out[19]), .B0(n3899),
.B1(FPSENCOS_d_ff3_sh_x_out[19]), .Y(n3897) );
NAND2X1TS U4964 ( .A(n2861), .B(FPSENCOS_d_ff3_LUT_out[19]), .Y(n3902) );
NAND3XLTS U4965 ( .A(n3898), .B(n3897), .C(n3902), .Y(n1824) );
AO22XLTS U4966 ( .A0(FPSENCOS_d_ff2_Y[30]), .A1(n4688), .B0(
FPSENCOS_d_ff_Yn[30]), .B1(n4374), .Y(n1854) );
AOI22X1TS U4967 ( .A0(FPADDSUB_intDY_EWSW[28]), .A1(n4322), .B0(n4321), .B1(
Data_2[28]), .Y(n3901) );
AOI22X1TS U4968 ( .A0(n4316), .A1(FPSENCOS_d_ff3_sh_y_out[28]), .B0(n3899),
.B1(FPSENCOS_d_ff3_sh_x_out[28]), .Y(n3900) );
NAND2X1TS U4969 ( .A(n4050), .B(FPSENCOS_d_ff3_LUT_out[27]), .Y(n4141) );
NAND3XLTS U4970 ( .A(n3901), .B(n3900), .C(n4141), .Y(n1815) );
OAI222X1TS U4971 ( .A0(n4091), .A1(n5186), .B0(n4952), .B1(
FPADDSUB_Shift_reg_FLAGS_7_6), .C0(n4090), .C1(n5015), .Y(n1416) );
OAI222X1TS U4972 ( .A0(n4091), .A1(n5012), .B0(n4953), .B1(
FPADDSUB_Shift_reg_FLAGS_7_6), .C0(n4090), .C1(n5178), .Y(n1414) );
AOI22X1TS U4973 ( .A0(FPADDSUB_intDY_EWSW[22]), .A1(n4172), .B0(n4171), .B1(
Data_2[22]), .Y(n3904) );
AOI22X1TS U4974 ( .A0(n4174), .A1(FPSENCOS_d_ff3_sh_y_out[22]), .B0(n4115),
.B1(FPSENCOS_d_ff3_sh_x_out[22]), .Y(n3903) );
NAND3XLTS U4975 ( .A(n3904), .B(n3903), .C(n3902), .Y(n1821) );
XNOR2X1TS U4976 ( .A(DP_OP_234J200_127_8543_n1), .B(n2231), .Y(n3905) );
MX2X1TS U4977 ( .A(n3905), .B(FPMULT_Exp_module_Overflow_flag_A), .S0(n3947),
.Y(n1585) );
AOI22X1TS U4978 ( .A0(FPADDSUB_intDY_EWSW[14]), .A1(n4172), .B0(n4171), .B1(
Data_2[14]), .Y(n3907) );
AOI22X1TS U4979 ( .A0(n4174), .A1(FPSENCOS_d_ff3_sh_y_out[14]), .B0(n4173),
.B1(FPSENCOS_d_ff3_sh_x_out[14]), .Y(n3906) );
NAND2X1TS U4980 ( .A(n4050), .B(FPSENCOS_d_ff3_LUT_out[5]), .Y(n4160) );
NAND3XLTS U4981 ( .A(n3907), .B(n3906), .C(n4160), .Y(n1829) );
OAI222X1TS U4982 ( .A0(n3911), .A1(n3910), .B0(n3909), .B1(n3908), .C0(n4693), .C1(n4975), .Y(n1811) );
AND2X2TS U4983 ( .A(FPADDSUB_Shift_reg_FLAGS_7[3]), .B(n2377), .Y(n4170) );
CLKBUFX2TS U4984 ( .A(n4170), .Y(n4904) );
INVX2TS U4985 ( .A(n4905), .Y(n4923) );
CLKBUFX3TS U4986 ( .A(n4904), .Y(n4919) );
NAND2X1TS U4987 ( .A(n2320), .B(n4831), .Y(n4800) );
NAND2X2TS U4988 ( .A(n4919), .B(n4800), .Y(n4903) );
NOR2X1TS U4989 ( .A(n5081), .B(FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n4029)
);
INVX2TS U4990 ( .A(n4029), .Y(n4146) );
NAND2X1TS U4991 ( .A(n2289), .B(n2265), .Y(n4838) );
AO22XLTS U4992 ( .A0(FPADDSUB_Data_array_SWR[17]), .A1(n2252), .B0(
FPADDSUB_Data_array_SWR[5]), .B1(n2296), .Y(n3914) );
NAND3X1TS U4993 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(n5081), .C(n2289),
.Y(n4810) );
INVX2TS U4994 ( .A(n4810), .Y(n4835) );
OAI2BB2XLTS U4995 ( .B0(n4792), .B1(n2289), .A0N(FPADDSUB_Data_array_SWR[13]), .A1N(n2395), .Y(n3913) );
AOI211X1TS U4996 ( .A0(FPADDSUB_Data_array_SWR[9]), .A1(n2304), .B0(n3914),
.C0(n3913), .Y(n4785) );
OAI22X1TS U4997 ( .A0(FPADDSUB_left_right_SHT2), .A1(n4785), .B0(n4784),
.B1(n4898), .Y(n4860) );
AOI2BB2XLTS U4998 ( .B0(n4977), .B1(n4923), .A0N(n4903), .A1N(n4860), .Y(
n1200) );
CMPR32X2TS U4999 ( .A(DP_OP_454J200_123_2743_n139), .B(
DP_OP_454J200_123_2743_n135), .C(n3916), .CO(n3890), .S(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N8) );
CMPR32X2TS U5000 ( .A(DP_OP_454J200_123_2743_n140), .B(
DP_OP_454J200_123_2743_n144), .C(n3917), .CO(n3916), .S(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N7) );
CMPR32X2TS U5001 ( .A(DP_OP_454J200_123_2743_n145), .B(n3919), .C(n3918),
.CO(n3917), .S(FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N6) );
CMPR32X2TS U5002 ( .A(n3922), .B(n3921), .C(n3920), .CO(n3919), .S(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N5) );
INVX2TS U5003 ( .A(n3923), .Y(n4373) );
CLKBUFX3TS U5004 ( .A(n4326), .Y(n4372) );
AO22XLTS U5005 ( .A0(n4373), .A1(FPSENCOS_d_ff1_Z[8]), .B0(n4372), .B1(
Data_1[8]), .Y(n2104) );
AO22XLTS U5006 ( .A0(n4373), .A1(FPSENCOS_d_ff1_Z[7]), .B0(n4372), .B1(
Data_1[7]), .Y(n2105) );
AO22XLTS U5007 ( .A0(n4373), .A1(FPSENCOS_d_ff1_Z[6]), .B0(n4372), .B1(
Data_1[6]), .Y(n2106) );
INVX2TS U5008 ( .A(n3965), .Y(n4351) );
XNOR2X1TS U5009 ( .A(n3925), .B(n3924), .Y(n3926) );
XNOR2X1TS U5010 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[1]), .B(
n3926), .Y(n3927) );
AO22XLTS U5011 ( .A0(n4268), .A1(FPMULT_P_Sgf[25]), .B0(n4351), .B1(n3927),
.Y(n1554) );
AO22XLTS U5012 ( .A0(n4373), .A1(FPSENCOS_d_ff1_Z[5]), .B0(n3923), .B1(
Data_1[5]), .Y(n2107) );
AO22XLTS U5013 ( .A0(n4373), .A1(FPSENCOS_d_ff1_Z[4]), .B0(n4326), .B1(
Data_1[4]), .Y(n2108) );
AO22XLTS U5014 ( .A0(n4363), .A1(FPSENCOS_d_ff1_Z[3]), .B0(n4326), .B1(
Data_1[3]), .Y(n2109) );
NOR3XLTS U5015 ( .A(FPMULT_FS_Module_state_reg[2]), .B(
FPMULT_FS_Module_state_reg[3]), .C(n3928), .Y(n3929) );
CLKBUFX2TS U5016 ( .A(n3929), .Y(n4709) );
CLKBUFX2TS U5017 ( .A(n4709), .Y(n4711) );
CLKBUFX2TS U5018 ( .A(n4711), .Y(n4369) );
INVX2TS U5019 ( .A(n4369), .Y(n4370) );
AO22XLTS U5020 ( .A0(FPMULT_Op_MX[30]), .A1(n4370), .B0(n4369), .B1(
Data_1[30]), .Y(n1688) );
AO22XLTS U5021 ( .A0(n4363), .A1(FPSENCOS_d_ff1_Z[2]), .B0(n4320), .B1(
Data_1[2]), .Y(n2110) );
AO22XLTS U5022 ( .A0(n4363), .A1(FPSENCOS_d_ff1_Z[1]), .B0(n4326), .B1(
Data_1[1]), .Y(n2111) );
AO22XLTS U5023 ( .A0(n4351), .A1(FPMULT_Sgf_operation_Result[5]), .B0(n4755),
.B1(FPMULT_P_Sgf[5]), .Y(n1534) );
AO22XLTS U5024 ( .A0(FPMULT_Op_MX[29]), .A1(n4370), .B0(n4369), .B1(
Data_1[29]), .Y(n1687) );
INVX2TS U5025 ( .A(n3965), .Y(n4764) );
CLKBUFX3TS U5026 ( .A(n3947), .Y(n4344) );
AO22XLTS U5027 ( .A0(n4764), .A1(FPMULT_Sgf_operation_Result[6]), .B0(n4344),
.B1(FPMULT_P_Sgf[6]), .Y(n1535) );
AO22XLTS U5028 ( .A0(n4764), .A1(FPMULT_Sgf_operation_Result[9]), .B0(n4344),
.B1(FPMULT_P_Sgf[9]), .Y(n1538) );
INVX2TS U5029 ( .A(n3965), .Y(n4261) );
AO22XLTS U5030 ( .A0(n3965), .A1(FPMULT_P_Sgf[0]), .B0(n4261), .B1(
FPMULT_Sgf_operation_Result[0]), .Y(n1529) );
CMPR32X2TS U5031 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[5]), .B(
n3931), .C(n3930), .CO(n4258), .S(n3932) );
AO22XLTS U5032 ( .A0(n4268), .A1(FPMULT_P_Sgf[29]), .B0(n4261), .B1(n3932),
.Y(n1558) );
AO22XLTS U5033 ( .A0(n4764), .A1(FPMULT_Sgf_operation_Result[3]), .B0(n4755),
.B1(FPMULT_P_Sgf[3]), .Y(n1532) );
AO22XLTS U5034 ( .A0(n4351), .A1(FPMULT_Sgf_operation_Result[7]), .B0(n4344),
.B1(FPMULT_P_Sgf[7]), .Y(n1536) );
AO22XLTS U5035 ( .A0(n4764), .A1(FPMULT_Sgf_operation_Result[10]), .B0(n4755), .B1(FPMULT_P_Sgf[10]), .Y(n1539) );
CMPR32X2TS U5036 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[2]), .B(
n3934), .C(n3933), .CO(n4265), .S(n3935) );
AO22XLTS U5037 ( .A0(n4268), .A1(FPMULT_P_Sgf[26]), .B0(n4351), .B1(n3935),
.Y(n1555) );
INVX2TS U5038 ( .A(n3936), .Y(n3956) );
AO22XLTS U5039 ( .A0(n3956), .A1(result_add_subt[0]), .B0(n3936), .B1(
FPSENCOS_d_ff_Zn[0]), .Y(n2074) );
CLKBUFX2TS U5040 ( .A(n3936), .Y(n3964) );
INVX2TS U5041 ( .A(n3964), .Y(n3950) );
AO22XLTS U5042 ( .A0(n3950), .A1(result_add_subt[5]), .B0(n3953), .B1(
FPSENCOS_d_ff_Zn[5]), .Y(n2059) );
INVX2TS U5043 ( .A(n3936), .Y(n3970) );
CLKBUFX3TS U5044 ( .A(n3936), .Y(n3955) );
AO22XLTS U5045 ( .A0(n3970), .A1(result_add_subt[9]), .B0(n3955), .B1(
FPSENCOS_d_ff_Zn[9]), .Y(n2047) );
CMPR32X2TS U5046 ( .A(n3939), .B(n3938), .C(n3937), .CO(n3940), .S(n3504) );
XOR2X1TS U5047 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_middle[25]), .B(
n3940), .Y(n3944) );
OA21XLTS U5048 ( .A0(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[12]), .A1(
n3942), .B0(n3941), .Y(n3943) );
NOR2X1TS U5049 ( .A(n3944), .B(n3943), .Y(n4761) );
INVX2TS U5050 ( .A(n4761), .Y(n4758) );
NAND2X1TS U5051 ( .A(n3944), .B(n3943), .Y(n4757) );
NAND2X1TS U5052 ( .A(n4756), .B(n4757), .Y(n4760) );
NAND2X1TS U5053 ( .A(n4758), .B(n4760), .Y(n4253) );
NAND2X1TS U5054 ( .A(n4753), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[15]), .Y(n4752) );
NAND2X1TS U5055 ( .A(n3961), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[17]), .Y(n3959) );
NAND2X1TS U5056 ( .A(n3957), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[19]), .Y(n3951) );
NAND2X1TS U5057 ( .A(n4750), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[21]), .Y(n4749) );
NOR2X1TS U5058 ( .A(n4749), .B(n3945), .Y(n4054) );
AOI21X1TS U5059 ( .A0(n4749), .A1(n3945), .B0(n4054), .Y(n3946) );
AO22XLTS U5060 ( .A0(n4755), .A1(FPMULT_P_Sgf[46]), .B0(n4261), .B1(n3946),
.Y(n1575) );
AO22XLTS U5061 ( .A0(n3956), .A1(result_add_subt[1]), .B0(n3953), .B1(
FPSENCOS_d_ff_Zn[1]), .Y(n2071) );
AO22XLTS U5062 ( .A0(n3950), .A1(result_add_subt[7]), .B0(n3955), .B1(
FPSENCOS_d_ff_Zn[7]), .Y(n2053) );
AO22XLTS U5063 ( .A0(n3956), .A1(result_add_subt[2]), .B0(n3953), .B1(
FPSENCOS_d_ff_Zn[2]), .Y(n2068) );
CLKBUFX3TS U5064 ( .A(n3947), .Y(n4352) );
AOI21X1TS U5065 ( .A0(n3951), .A1(n3948), .B0(n4750), .Y(n3949) );
AO22XLTS U5066 ( .A0(n4352), .A1(FPMULT_P_Sgf[44]), .B0(n4261), .B1(n3949),
.Y(n1573) );
AO22XLTS U5067 ( .A0(n3956), .A1(result_add_subt[3]), .B0(n3953), .B1(
FPSENCOS_d_ff_Zn[3]), .Y(n2065) );
AO22XLTS U5068 ( .A0(n3970), .A1(result_add_subt[12]), .B0(n3955), .B1(
FPSENCOS_d_ff_Zn[12]), .Y(n2038) );
AO22XLTS U5069 ( .A0(n3970), .A1(result_add_subt[10]), .B0(n3955), .B1(
FPSENCOS_d_ff_Zn[10]), .Y(n2044) );
AO22XLTS U5070 ( .A0(n3956), .A1(result_add_subt[14]), .B0(n3955), .B1(
FPSENCOS_d_ff_Zn[14]), .Y(n2032) );
AO22XLTS U5071 ( .A0(n3970), .A1(result_add_subt[11]), .B0(n3955), .B1(
FPSENCOS_d_ff_Zn[11]), .Y(n2041) );
INVX2TS U5072 ( .A(n3953), .Y(n4673) );
AO22XLTS U5073 ( .A0(n4673), .A1(result_add_subt[8]), .B0(n3955), .B1(
FPSENCOS_d_ff_Zn[8]), .Y(n2050) );
AO22XLTS U5074 ( .A0(n3956), .A1(result_add_subt[16]), .B0(n3955), .B1(
FPSENCOS_d_ff_Zn[16]), .Y(n2026) );
AO22XLTS U5075 ( .A0(n3970), .A1(result_add_subt[13]), .B0(n3955), .B1(
FPSENCOS_d_ff_Zn[13]), .Y(n2035) );
AO22XLTS U5076 ( .A0(n3950), .A1(result_add_subt[6]), .B0(n3953), .B1(
FPSENCOS_d_ff_Zn[6]), .Y(n2056) );
OAI21XLTS U5077 ( .A0(n3957), .A1(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[19]), .B0(n3951), .Y(n3952) );
AOI2BB2XLTS U5078 ( .B0(n3952), .B1(n4759), .A0N(n4764), .A1N(
FPMULT_P_Sgf[43]), .Y(n1572) );
AO22XLTS U5079 ( .A0(n3956), .A1(result_add_subt[4]), .B0(n3953), .B1(
FPSENCOS_d_ff_Zn[4]), .Y(n2062) );
CLKBUFX3TS U5080 ( .A(n3936), .Y(n3971) );
AO22XLTS U5081 ( .A0(n3956), .A1(result_add_subt[17]), .B0(n3971), .B1(
FPSENCOS_d_ff_Zn[17]), .Y(n2023) );
AO22XLTS U5082 ( .A0(n4673), .A1(result_add_subt[20]), .B0(n3971), .B1(
FPSENCOS_d_ff_Zn[20]), .Y(n2014) );
OAI21XLTS U5083 ( .A0(n3961), .A1(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[17]), .B0(n3959), .Y(n3954) );
AOI2BB2XLTS U5084 ( .B0(n3954), .B1(n4759), .A0N(n4764), .A1N(
FPMULT_P_Sgf[41]), .Y(n1570) );
AO22XLTS U5085 ( .A0(n3956), .A1(result_add_subt[18]), .B0(n3971), .B1(
FPSENCOS_d_ff_Zn[18]), .Y(n2020) );
AO22XLTS U5086 ( .A0(n3956), .A1(result_add_subt[15]), .B0(n3955), .B1(
FPSENCOS_d_ff_Zn[15]), .Y(n2029) );
AO22XLTS U5087 ( .A0(n4673), .A1(result_add_subt[22]), .B0(n3971), .B1(
FPSENCOS_d_ff_Zn[22]), .Y(n2008) );
AOI21X1TS U5088 ( .A0(n3959), .A1(n3958), .B0(n3957), .Y(n3960) );
AO22XLTS U5089 ( .A0(n4268), .A1(FPMULT_P_Sgf[42]), .B0(n4261), .B1(n3960),
.Y(n1571) );
AO22XLTS U5090 ( .A0(n4673), .A1(result_add_subt[30]), .B0(n3964), .B1(
FPSENCOS_d_ff_Zn[30]), .Y(n1765) );
AO22XLTS U5091 ( .A0(n4673), .A1(result_add_subt[29]), .B0(n3964), .B1(
FPSENCOS_d_ff_Zn[29]), .Y(n1768) );
AO22XLTS U5092 ( .A0(n3970), .A1(result_add_subt[28]), .B0(n3964), .B1(
FPSENCOS_d_ff_Zn[28]), .Y(n1771) );
AOI21X1TS U5093 ( .A0(n4752), .A1(n3962), .B0(n3961), .Y(n3963) );
AO22XLTS U5094 ( .A0(n4268), .A1(FPMULT_P_Sgf[40]), .B0(n4261), .B1(n3963),
.Y(n1569) );
AO22XLTS U5095 ( .A0(n3970), .A1(result_add_subt[27]), .B0(n3964), .B1(
FPSENCOS_d_ff_Zn[27]), .Y(n1774) );
AO22XLTS U5096 ( .A0(n3970), .A1(result_add_subt[26]), .B0(n3964), .B1(
FPSENCOS_d_ff_Zn[26]), .Y(n1777) );
AO22XLTS U5097 ( .A0(n3970), .A1(result_add_subt[25]), .B0(n3971), .B1(
FPSENCOS_d_ff_Zn[25]), .Y(n1780) );
INVX2TS U5098 ( .A(n3965), .Y(n4343) );
NAND2BXLTS U5099 ( .AN(n3967), .B(n3966), .Y(n3968) );
XNOR2X1TS U5100 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[10]), .B(
n3968), .Y(n3969) );
AO22XLTS U5101 ( .A0(n4268), .A1(FPMULT_P_Sgf[34]), .B0(n4343), .B1(n3969),
.Y(n1563) );
AO22XLTS U5102 ( .A0(n3970), .A1(result_add_subt[24]), .B0(n3971), .B1(
FPSENCOS_d_ff_Zn[24]), .Y(n1783) );
AO22XLTS U5103 ( .A0(n4673), .A1(result_add_subt[23]), .B0(n3971), .B1(
FPSENCOS_d_ff_Zn[23]), .Y(n1786) );
AO22XLTS U5104 ( .A0(n4673), .A1(result_add_subt[31]), .B0(n3971), .B1(
FPSENCOS_d_ff_Zn[31]), .Y(n1909) );
AO22XLTS U5105 ( .A0(n4673), .A1(result_add_subt[19]), .B0(n3971), .B1(
FPSENCOS_d_ff_Zn[19]), .Y(n2017) );
AO22XLTS U5106 ( .A0(n4673), .A1(result_add_subt[21]), .B0(n3971), .B1(
FPSENCOS_d_ff_Zn[21]), .Y(n2011) );
AO22XLTS U5107 ( .A0(n3560), .A1(FPADDSUB_SIGN_FLAG_NRM), .B0(n4677), .B1(
FPADDSUB_SIGN_FLAG_SHT1SHT2), .Y(n1357) );
CLKBUFX2TS U5108 ( .A(n4709), .Y(n4717) );
CLKBUFX2TS U5109 ( .A(n4709), .Y(n4710) );
INVX2TS U5110 ( .A(n4710), .Y(n4221) );
AO22XLTS U5111 ( .A0(n4717), .A1(Data_1[31]), .B0(n4221), .B1(
FPMULT_Op_MX[31]), .Y(n1657) );
AO22XLTS U5112 ( .A0(n4351), .A1(FPMULT_Sgf_operation_Result[2]), .B0(n4755),
.B1(FPMULT_P_Sgf[2]), .Y(n1531) );
AOI2BB1XLTS U5113 ( .A0N(n4290), .A1N(FPADDSUB_LZD_output_NRM2_EW[1]), .B0(
n3973), .Y(n1409) );
INVX2TS U5114 ( .A(n2377), .Y(n4886) );
AOI2BB1XLTS U5115 ( .A0N(n4886), .A1N(overflow_flag_addsubt), .B0(n4776),
.Y(n1411) );
NOR2X1TS U5116 ( .A(n4777), .B(n2377), .Y(n4137) );
AOI2BB1XLTS U5117 ( .A0N(n5359), .A1N(underflow_flag_addsubt), .B0(n4137),
.Y(n1412) );
AO21XLTS U5118 ( .A0(FPADDSUB_LZD_output_NRM2_EW[0]), .A1(n3972), .B0(n3974),
.Y(n1314) );
INVX2TS U5119 ( .A(FPADDSUB_Shift_reg_FLAGS_7_5), .Y(n4225) );
AO22XLTS U5120 ( .A0(n4056), .A1(FPADDSUB_DMP_EXP_EWSW[22]), .B0(n4225),
.B1(FPADDSUB_DMP_SHT1_EWSW[22]), .Y(n1208) );
INVX2TS U5121 ( .A(n4060), .Y(n4360) );
AO22XLTS U5122 ( .A0(FPADDSUB_Shift_reg_FLAGS_7_5), .A1(
FPADDSUB_DMP_EXP_EWSW[15]), .B0(n4360), .B1(FPADDSUB_DMP_SHT1_EWSW[15]), .Y(n1212) );
AO22XLTS U5123 ( .A0(n4056), .A1(FPADDSUB_DMP_EXP_EWSW[18]), .B0(n4360),
.B1(FPADDSUB_DMP_SHT1_EWSW[18]), .Y(n1216) );
AO22XLTS U5124 ( .A0(n4056), .A1(FPADDSUB_DMP_EXP_EWSW[21]), .B0(n4360),
.B1(FPADDSUB_DMP_SHT1_EWSW[21]), .Y(n1220) );
AO22XLTS U5125 ( .A0(n4056), .A1(FPADDSUB_DMP_EXP_EWSW[19]), .B0(n4360),
.B1(FPADDSUB_DMP_SHT1_EWSW[19]), .Y(n1224) );
INVX2TS U5126 ( .A(n4060), .Y(n4227) );
AO22XLTS U5127 ( .A0(n4056), .A1(FPADDSUB_DMP_EXP_EWSW[20]), .B0(n4227),
.B1(FPADDSUB_DMP_SHT1_EWSW[20]), .Y(n1228) );
AO22XLTS U5128 ( .A0(n4056), .A1(FPADDSUB_DMP_EXP_EWSW[17]), .B0(n4360),
.B1(FPADDSUB_DMP_SHT1_EWSW[17]), .Y(n1232) );
AO22XLTS U5129 ( .A0(n4056), .A1(FPADDSUB_DMP_EXP_EWSW[4]), .B0(n4227), .B1(
FPADDSUB_DMP_SHT1_EWSW[4]), .Y(n1236) );
CLKBUFX3TS U5130 ( .A(FPADDSUB_Shift_reg_FLAGS_7_5), .Y(n4226) );
AO22XLTS U5131 ( .A0(n4226), .A1(FPADDSUB_DMP_EXP_EWSW[6]), .B0(n4360), .B1(
FPADDSUB_DMP_SHT1_EWSW[6]), .Y(n1240) );
AOI21X1TS U5132 ( .A0(n5177), .A1(n3975), .B0(n4738), .Y(n3976) );
AO22XLTS U5133 ( .A0(n3989), .A1(n3976), .B0(n2442), .B1(
FPMULT_Add_result[20]), .Y(n1600) );
CLKBUFX3TS U5134 ( .A(FPADDSUB_Shift_reg_FLAGS_7_5), .Y(n4228) );
AO22XLTS U5135 ( .A0(n4228), .A1(FPADDSUB_DMP_EXP_EWSW[13]), .B0(n4227),
.B1(FPADDSUB_DMP_SHT1_EWSW[13]), .Y(n1244) );
AO22XLTS U5136 ( .A0(n4228), .A1(FPADDSUB_DMP_EXP_EWSW[16]), .B0(n4360),
.B1(FPADDSUB_DMP_SHT1_EWSW[16]), .Y(n1248) );
AO22XLTS U5137 ( .A0(n4373), .A1(FPSENCOS_d_ff1_Z[9]), .B0(n4372), .B1(
Data_1[9]), .Y(n2103) );
AO22XLTS U5138 ( .A0(n4228), .A1(FPADDSUB_DMP_EXP_EWSW[8]), .B0(n4227), .B1(
FPADDSUB_DMP_SHT1_EWSW[8]), .Y(n1252) );
AOI21X1TS U5139 ( .A0(n5106), .A1(n3977), .B0(n4735), .Y(n3978) );
AO22XLTS U5140 ( .A0(n3989), .A1(n3978), .B0(n2442), .B1(
FPMULT_Add_result[14]), .Y(n1606) );
AO22XLTS U5141 ( .A0(n4228), .A1(FPADDSUB_DMP_EXP_EWSW[11]), .B0(n4360),
.B1(FPADDSUB_DMP_SHT1_EWSW[11]), .Y(n1256) );
AO22XLTS U5142 ( .A0(n4228), .A1(FPADDSUB_DMP_EXP_EWSW[14]), .B0(n4227),
.B1(FPADDSUB_DMP_SHT1_EWSW[14]), .Y(n1260) );
AO22XLTS U5143 ( .A0(n4228), .A1(FPADDSUB_DMP_EXP_EWSW[10]), .B0(n4227),
.B1(FPADDSUB_DMP_SHT1_EWSW[10]), .Y(n1264) );
OAI21XLTS U5144 ( .A0(n4720), .A1(n5121), .B0(n4725), .Y(n3979) );
AO22XLTS U5145 ( .A0(n3989), .A1(n3979), .B0(n4737), .B1(
FPMULT_Add_result[4]), .Y(n1616) );
AO22XLTS U5146 ( .A0(n4228), .A1(FPADDSUB_DMP_EXP_EWSW[12]), .B0(n4227),
.B1(FPADDSUB_DMP_SHT1_EWSW[12]), .Y(n1268) );
AO22XLTS U5147 ( .A0(n4228), .A1(FPADDSUB_DMP_EXP_EWSW[5]), .B0(n4227), .B1(
FPADDSUB_DMP_SHT1_EWSW[5]), .Y(n1274) );
AO22XLTS U5148 ( .A0(n4228), .A1(FPADDSUB_DMP_EXP_EWSW[9]), .B0(n4227), .B1(
FPADDSUB_DMP_SHT1_EWSW[9]), .Y(n1281) );
AO22XLTS U5149 ( .A0(n4226), .A1(FPADDSUB_DMP_EXP_EWSW[1]), .B0(n4225), .B1(
FPADDSUB_DMP_SHT1_EWSW[1]), .Y(n1288) );
AO22XLTS U5150 ( .A0(n4226), .A1(FPADDSUB_DMP_EXP_EWSW[0]), .B0(n4225), .B1(
FPADDSUB_DMP_SHT1_EWSW[0]), .Y(n1295) );
AO22XLTS U5151 ( .A0(n4226), .A1(FPADDSUB_DMP_EXP_EWSW[7]), .B0(n4225), .B1(
FPADDSUB_DMP_SHT1_EWSW[7]), .Y(n1302) );
AOI21X1TS U5152 ( .A0(n5176), .A1(n3981), .B0(n3980), .Y(n3982) );
AO22XLTS U5153 ( .A0(n3989), .A1(n3982), .B0(n4737), .B1(
FPMULT_Add_result[18]), .Y(n1602) );
AO22XLTS U5154 ( .A0(n4226), .A1(FPADDSUB_DMP_EXP_EWSW[2]), .B0(n4225), .B1(
FPADDSUB_DMP_SHT1_EWSW[2]), .Y(n1309) );
AO22XLTS U5155 ( .A0(n4226), .A1(FPADDSUB_DMP_EXP_EWSW[3]), .B0(n4225), .B1(
FPADDSUB_DMP_SHT1_EWSW[3]), .Y(n1325) );
AO22XLTS U5156 ( .A0(n4226), .A1(FPADDSUB_OP_FLAG_EXP), .B0(n4225), .B1(
FPADDSUB_OP_FLAG_SHT1), .Y(n1354) );
AOI21X1TS U5157 ( .A0(n5175), .A1(n4733), .B0(n3983), .Y(n3984) );
AO22XLTS U5158 ( .A0(n3989), .A1(n3984), .B0(n4722), .B1(
FPMULT_Add_result[16]), .Y(n1604) );
AO22XLTS U5159 ( .A0(n4853), .A1(FPADDSUB_SIGN_FLAG_SFG), .B0(n4985), .B1(
FPADDSUB_SIGN_FLAG_NRM), .Y(n1358) );
CLKBUFX2TS U5160 ( .A(n4904), .Y(n4896) );
INVX2TS U5161 ( .A(n4896), .Y(n4169) );
AO22XLTS U5162 ( .A0(n4170), .A1(FPADDSUB_SIGN_FLAG_SHT2), .B0(n4169), .B1(
FPADDSUB_SIGN_FLAG_SFG), .Y(n1359) );
CLKBUFX3TS U5163 ( .A(n5196), .Y(n4020) );
AO22XLTS U5164 ( .A0(n4938), .A1(FPADDSUB_SIGN_FLAG_SHT1), .B0(n4020), .B1(
FPADDSUB_SIGN_FLAG_SHT2), .Y(n1360) );
AOI21X1TS U5165 ( .A0(n5107), .A1(n3985), .B0(n4731), .Y(n3986) );
AO22XLTS U5166 ( .A0(n3989), .A1(n3986), .B0(n2442), .B1(
FPMULT_Add_result[10]), .Y(n1610) );
CLKBUFX3TS U5167 ( .A(FPADDSUB_Shift_reg_FLAGS_7_5), .Y(n4365) );
INVX2TS U5168 ( .A(n4060), .Y(n4364) );
AO22XLTS U5169 ( .A0(n4365), .A1(FPADDSUB_SIGN_FLAG_EXP), .B0(n4364), .B1(
FPADDSUB_SIGN_FLAG_SHT1), .Y(n1361) );
AO22XLTS U5170 ( .A0(n4904), .A1(FPADDSUB_DMP_SHT2_EWSW[30]), .B0(n4169),
.B1(FPADDSUB_DMP_SFG[30]), .Y(n1420) );
AO22XLTS U5171 ( .A0(n4938), .A1(FPADDSUB_DMP_SHT1_EWSW[30]), .B0(n4020),
.B1(FPADDSUB_DMP_SHT2_EWSW[30]), .Y(n1421) );
AO22XLTS U5172 ( .A0(n4356), .A1(FPADDSUB_DMP_EXP_EWSW[30]), .B0(n4984),
.B1(FPADDSUB_DMP_SHT1_EWSW[30]), .Y(n1422) );
AO22XLTS U5173 ( .A0(n4905), .A1(FPADDSUB_DMP_SHT2_EWSW[29]), .B0(n4169),
.B1(FPADDSUB_DMP_SFG[29]), .Y(n1425) );
AO22XLTS U5174 ( .A0(n4938), .A1(FPADDSUB_DMP_SHT1_EWSW[29]), .B0(n4020),
.B1(FPADDSUB_DMP_SHT2_EWSW[29]), .Y(n1426) );
AO22XLTS U5175 ( .A0(n4356), .A1(FPADDSUB_DMP_EXP_EWSW[29]), .B0(n4984),
.B1(FPADDSUB_DMP_SHT1_EWSW[29]), .Y(n1427) );
AO22XLTS U5176 ( .A0(n4170), .A1(FPADDSUB_DMP_SHT2_EWSW[28]), .B0(n4169),
.B1(FPADDSUB_DMP_SFG[28]), .Y(n1430) );
AO22XLTS U5177 ( .A0(n4938), .A1(FPADDSUB_DMP_SHT1_EWSW[28]), .B0(n4674),
.B1(FPADDSUB_DMP_SHT2_EWSW[28]), .Y(n1431) );
AOI21X1TS U5178 ( .A0(n5173), .A1(n4727), .B0(n3987), .Y(n3988) );
AO22XLTS U5179 ( .A0(n3989), .A1(n3988), .B0(n4737), .B1(
FPMULT_Add_result[8]), .Y(n1612) );
AO22XLTS U5180 ( .A0(n4356), .A1(FPADDSUB_DMP_EXP_EWSW[28]), .B0(n4984),
.B1(FPADDSUB_DMP_SHT1_EWSW[28]), .Y(n1432) );
INVX2TS U5181 ( .A(n4896), .Y(n3994) );
AO22XLTS U5182 ( .A0(n4170), .A1(FPADDSUB_DMP_SHT2_EWSW[27]), .B0(n3994),
.B1(FPADDSUB_DMP_SFG[27]), .Y(n1435) );
AO22XLTS U5183 ( .A0(n4938), .A1(FPADDSUB_DMP_SHT1_EWSW[27]), .B0(n4674),
.B1(FPADDSUB_DMP_SHT2_EWSW[27]), .Y(n1436) );
AO22XLTS U5184 ( .A0(n4356), .A1(FPADDSUB_DMP_EXP_EWSW[27]), .B0(n4984),
.B1(FPADDSUB_DMP_SHT1_EWSW[27]), .Y(n1437) );
AO22XLTS U5185 ( .A0(n4170), .A1(FPADDSUB_DMP_SHT2_EWSW[26]), .B0(n3994),
.B1(FPADDSUB_DMP_SFG[26]), .Y(n1440) );
AO22XLTS U5186 ( .A0(n4938), .A1(FPADDSUB_DMP_SHT1_EWSW[26]), .B0(n4674),
.B1(FPADDSUB_DMP_SHT2_EWSW[26]), .Y(n1441) );
NOR4X1TS U5187 ( .A(n4249), .B(n4128), .C(n5358), .D(n3990), .Y(n3992) );
OAI2BB1X1TS U5188 ( .A0N(operation[1]), .A1N(ack_operation), .B0(n3991), .Y(
n4118) );
NAND3XLTS U5189 ( .A(n4363), .B(n3992), .C(n4118), .Y(n3993) );
AOI32X1TS U5190 ( .A0(begin_operation), .A1(n3993), .A2(operation[1]), .B0(
n4045), .B1(n3993), .Y(FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]) );
AO22XLTS U5191 ( .A0(n4357), .A1(FPADDSUB_DMP_EXP_EWSW[26]), .B0(n4223),
.B1(FPADDSUB_DMP_SHT1_EWSW[26]), .Y(n1442) );
AO22XLTS U5192 ( .A0(n4896), .A1(FPADDSUB_DMP_SHT2_EWSW[25]), .B0(n3994),
.B1(FPADDSUB_DMP_SFG[25]), .Y(n1445) );
AO22XLTS U5193 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[25]), .B0(n4674),
.B1(FPADDSUB_DMP_SHT2_EWSW[25]), .Y(n1446) );
AO22XLTS U5194 ( .A0(n4365), .A1(FPADDSUB_DMP_EXP_EWSW[25]), .B0(n4984),
.B1(FPADDSUB_DMP_SHT1_EWSW[25]), .Y(n1447) );
AO22XLTS U5195 ( .A0(n4170), .A1(FPADDSUB_DMP_SHT2_EWSW[24]), .B0(n3994),
.B1(FPADDSUB_DMP_SFG[24]), .Y(n1450) );
AO22XLTS U5196 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[24]), .B0(n4674),
.B1(FPADDSUB_DMP_SHT2_EWSW[24]), .Y(n1451) );
AO22XLTS U5197 ( .A0(n4357), .A1(FPADDSUB_DMP_EXP_EWSW[24]), .B0(n4984),
.B1(FPADDSUB_DMP_SHT1_EWSW[24]), .Y(n1452) );
AO22XLTS U5198 ( .A0(n4919), .A1(FPADDSUB_DMP_SHT2_EWSW[23]), .B0(n3994),
.B1(FPADDSUB_DMP_SFG[23]), .Y(n1455) );
AO22XLTS U5199 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[23]), .B0(n4018),
.B1(FPADDSUB_DMP_SHT2_EWSW[23]), .Y(n1456) );
AO22XLTS U5200 ( .A0(n4356), .A1(FPADDSUB_DMP_EXP_EWSW[23]), .B0(n4984),
.B1(FPADDSUB_DMP_SHT1_EWSW[23]), .Y(n1457) );
NAND2X1TS U5201 ( .A(FPADDSUB_Shift_reg_FLAGS_7_6), .B(
FPADDSUB_intDX_EWSW[31]), .Y(n4015) );
INVX2TS U5202 ( .A(n3995), .Y(n4013) );
NAND2X1TS U5203 ( .A(FPADDSUB_intDY_EWSW[7]), .B(n5189), .Y(n3997) );
NAND4XLTS U5204 ( .A(n3999), .B(n3998), .C(n3997), .D(n3996), .Y(n4012) );
OAI211XLTS U5205 ( .A0(n5209), .A1(FPADDSUB_intDX_EWSW[0]), .B0(n4001), .C0(
n4000), .Y(n4009) );
NAND4BXLTS U5206 ( .AN(n4005), .B(n4004), .C(n4003), .D(n4002), .Y(n4008) );
NAND4BBX1TS U5207 ( .AN(n4009), .BN(n4008), .C(n4007), .D(n4006), .Y(n4011)
);
OAI31X1TS U5208 ( .A0(n4013), .A1(n4012), .A2(n4011), .B0(n4010), .Y(n4014)
);
AOI22X1TS U5209 ( .A0(n2344), .A1(n4016), .B0(n4015), .B1(n4014), .Y(n4017)
);
AO21XLTS U5210 ( .A0(FPADDSUB_SIGN_FLAG_EXP), .A1(n4765), .B0(n4017), .Y(
n1362) );
INVX2TS U5211 ( .A(n4674), .Y(n4019) );
AO22XLTS U5212 ( .A0(n4019), .A1(FPADDSUB_DMP_SHT1_EWSW[22]), .B0(n5196),
.B1(FPADDSUB_DMP_SHT2_EWSW[22]), .Y(n1207) );
AO22XLTS U5213 ( .A0(n4019), .A1(FPADDSUB_DMP_SHT1_EWSW[15]), .B0(n4018),
.B1(FPADDSUB_DMP_SHT2_EWSW[15]), .Y(n1211) );
AO22XLTS U5214 ( .A0(n4019), .A1(FPADDSUB_DMP_SHT1_EWSW[18]), .B0(n5196),
.B1(FPADDSUB_DMP_SHT2_EWSW[18]), .Y(n1215) );
AO22XLTS U5215 ( .A0(FPSENCOS_d_ff2_Y[24]), .A1(n4688), .B0(
FPSENCOS_d_ff_Yn[24]), .B1(n4279), .Y(n1860) );
AO22XLTS U5216 ( .A0(n4019), .A1(FPADDSUB_DMP_SHT1_EWSW[21]), .B0(n4018),
.B1(FPADDSUB_DMP_SHT2_EWSW[21]), .Y(n1219) );
AO22XLTS U5217 ( .A0(n4019), .A1(FPADDSUB_DMP_SHT1_EWSW[19]), .B0(n5196),
.B1(FPADDSUB_DMP_SHT2_EWSW[19]), .Y(n1223) );
AO22XLTS U5218 ( .A0(n4019), .A1(FPADDSUB_DMP_SHT1_EWSW[20]), .B0(n4018),
.B1(FPADDSUB_DMP_SHT2_EWSW[20]), .Y(n1227) );
AO22XLTS U5219 ( .A0(FPSENCOS_d_ff2_Y[25]), .A1(n4280), .B0(
FPSENCOS_d_ff_Yn[25]), .B1(n4279), .Y(n1859) );
AO22XLTS U5220 ( .A0(n4019), .A1(FPADDSUB_DMP_SHT1_EWSW[17]), .B0(n5196),
.B1(FPADDSUB_DMP_SHT2_EWSW[17]), .Y(n1231) );
INVX2TS U5221 ( .A(n4018), .Y(n4181) );
CLKBUFX3TS U5222 ( .A(n5196), .Y(n4180) );
AO22XLTS U5223 ( .A0(n4181), .A1(FPADDSUB_DMP_SHT1_EWSW[4]), .B0(n4180),
.B1(FPADDSUB_DMP_SHT2_EWSW[4]), .Y(n1235) );
AO22XLTS U5224 ( .A0(n4019), .A1(FPADDSUB_DMP_SHT1_EWSW[6]), .B0(n4180),
.B1(FPADDSUB_DMP_SHT2_EWSW[6]), .Y(n1239) );
AO22XLTS U5225 ( .A0(FPSENCOS_d_ff2_Y[26]), .A1(n3495), .B0(
FPSENCOS_d_ff_Yn[26]), .B1(n4374), .Y(n1858) );
AO22XLTS U5226 ( .A0(n4019), .A1(FPADDSUB_DMP_SHT1_EWSW[13]), .B0(n4180),
.B1(FPADDSUB_DMP_SHT2_EWSW[13]), .Y(n1243) );
AO22XLTS U5227 ( .A0(n4019), .A1(FPADDSUB_DMP_SHT1_EWSW[16]), .B0(n4180),
.B1(FPADDSUB_DMP_SHT2_EWSW[16]), .Y(n1247) );
AO22XLTS U5228 ( .A0(n4181), .A1(FPADDSUB_DMP_SHT1_EWSW[8]), .B0(n4180),
.B1(FPADDSUB_DMP_SHT2_EWSW[8]), .Y(n1251) );
AO22XLTS U5229 ( .A0(n4181), .A1(FPADDSUB_DMP_SHT1_EWSW[14]), .B0(n4180),
.B1(FPADDSUB_DMP_SHT2_EWSW[14]), .Y(n1259) );
AO22XLTS U5230 ( .A0(n4181), .A1(FPADDSUB_DMP_SHT1_EWSW[10]), .B0(n4180),
.B1(FPADDSUB_DMP_SHT2_EWSW[10]), .Y(n1263) );
AO22XLTS U5231 ( .A0(n4181), .A1(FPADDSUB_DMP_SHT1_EWSW[12]), .B0(n4180),
.B1(FPADDSUB_DMP_SHT2_EWSW[12]), .Y(n1267) );
AO22XLTS U5232 ( .A0(n4181), .A1(FPADDSUB_DMP_SHT1_EWSW[5]), .B0(n4180),
.B1(FPADDSUB_DMP_SHT2_EWSW[5]), .Y(n1273) );
AO22XLTS U5233 ( .A0(n4181), .A1(FPADDSUB_DMP_SHT1_EWSW[9]), .B0(n4020),
.B1(FPADDSUB_DMP_SHT2_EWSW[9]), .Y(n1280) );
AO22XLTS U5234 ( .A0(n4181), .A1(FPADDSUB_DMP_SHT1_EWSW[1]), .B0(n4020),
.B1(FPADDSUB_DMP_SHT2_EWSW[1]), .Y(n1287) );
AO22XLTS U5235 ( .A0(n4181), .A1(FPADDSUB_DMP_SHT1_EWSW[0]), .B0(n4020),
.B1(FPADDSUB_DMP_SHT2_EWSW[0]), .Y(n1294) );
AO22XLTS U5236 ( .A0(n4938), .A1(FPADDSUB_DMP_SHT1_EWSW[7]), .B0(n4020),
.B1(FPADDSUB_DMP_SHT2_EWSW[7]), .Y(n1301) );
AO22XLTS U5237 ( .A0(n4938), .A1(FPADDSUB_DMP_SHT1_EWSW[2]), .B0(n4020),
.B1(FPADDSUB_DMP_SHT2_EWSW[2]), .Y(n1308) );
AO22XLTS U5238 ( .A0(n4938), .A1(FPADDSUB_DMP_SHT1_EWSW[3]), .B0(n4020),
.B1(FPADDSUB_DMP_SHT2_EWSW[3]), .Y(n1324) );
AO22XLTS U5239 ( .A0(n4938), .A1(FPADDSUB_OP_FLAG_SHT1), .B0(n4020), .B1(
FPADDSUB_OP_FLAG_SHT2), .Y(n1353) );
AO22XLTS U5240 ( .A0(n4373), .A1(FPSENCOS_d_ff1_Z[10]), .B0(n4372), .B1(
Data_1[10]), .Y(n2102) );
AOI22X1TS U5241 ( .A0(FPADDSUB_intDY_EWSW[30]), .A1(n4322), .B0(n4321), .B1(
Data_2[30]), .Y(n4022) );
AOI22X1TS U5242 ( .A0(n4316), .A1(FPSENCOS_d_ff3_sh_y_out[30]), .B0(n3899),
.B1(FPSENCOS_d_ff3_sh_x_out[30]), .Y(n4021) );
NAND2X1TS U5243 ( .A(n4022), .B(n4021), .Y(n1813) );
INVX2TS U5244 ( .A(n4905), .Y(n4916) );
CLKBUFX3TS U5245 ( .A(n4904), .Y(n4168) );
AO22XLTS U5246 ( .A0(n4916), .A1(FPADDSUB_DMP_SFG[15]), .B0(n4168), .B1(
FPADDSUB_DMP_SHT2_EWSW[15]), .Y(n1210) );
AO22XLTS U5247 ( .A0(n4916), .A1(FPADDSUB_DMP_SFG[17]), .B0(n4168), .B1(
FPADDSUB_DMP_SHT2_EWSW[17]), .Y(n1230) );
NAND2X1TS U5248 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(n5081), .Y(n4035)
);
OAI22X1TS U5249 ( .A0(n5125), .A1(n4146), .B0(n4975), .B1(n4035), .Y(n4023)
);
AOI22X1TS U5250 ( .A0(FPADDSUB_Data_array_SWR[12]), .A1(n2251), .B0(
FPADDSUB_Data_array_SWR[0]), .B1(n2295), .Y(n4025) );
AOI22X1TS U5251 ( .A0(FPADDSUB_Data_array_SWR[8]), .A1(n4835), .B0(
FPADDSUB_Data_array_SWR[4]), .B1(n2305), .Y(n4024) );
OAI211X1TS U5252 ( .A0(n2361), .A1(n2289), .B0(n4025), .C0(n4024), .Y(n4893)
);
NOR2X2TS U5253 ( .A(n2264), .B(n5123), .Y(n4144) );
AOI2BB2XLTS U5254 ( .B0(FPADDSUB_left_right_SHT2), .B1(n4893), .A0N(n4894),
.A1N(n4820), .Y(n4026) );
NAND2X1TS U5255 ( .A(n2321), .B(n4831), .Y(n4774) );
AOI32X1TS U5256 ( .A0(n4026), .A1(n4919), .A2(n4774), .B0(n5144), .B1(n4923),
.Y(n1180) );
AOI22X1TS U5257 ( .A0(FPADDSUB_intDY_EWSW[20]), .A1(n4172), .B0(n4171), .B1(
Data_2[20]), .Y(n4028) );
AOI22X1TS U5258 ( .A0(n4174), .A1(FPSENCOS_d_ff3_sh_y_out[20]), .B0(n3899),
.B1(FPSENCOS_d_ff3_sh_x_out[20]), .Y(n4027) );
NAND2X1TS U5259 ( .A(n4050), .B(FPSENCOS_d_ff3_LUT_out[15]), .Y(n4175) );
NAND3XLTS U5260 ( .A(n4028), .B(n4027), .C(n4175), .Y(n1823) );
INVX2TS U5261 ( .A(n4896), .Y(n4179) );
CLKBUFX2TS U5262 ( .A(n4170), .Y(n4178) );
AO22XLTS U5263 ( .A0(n4179), .A1(n2337), .B0(n4178), .B1(
FPADDSUB_DMP_SHT2_EWSW[10]), .Y(n1262) );
AOI22X1TS U5264 ( .A0(FPADDSUB_Data_array_SWR[22]), .A1(n4029), .B0(
FPADDSUB_Data_array_SWR[18]), .B1(n2265), .Y(n4030) );
NAND2X1TS U5265 ( .A(n4030), .B(n4145), .Y(n4789) );
INVX2TS U5266 ( .A(n4789), .Y(n4811) );
AOI22X1TS U5267 ( .A0(FPADDSUB_Data_array_SWR[19]), .A1(n2251), .B0(
FPADDSUB_Data_array_SWR[11]), .B1(n2305), .Y(n4032) );
AOI22X1TS U5268 ( .A0(FPADDSUB_Data_array_SWR[15]), .A1(n4835), .B0(
FPADDSUB_Data_array_SWR[7]), .B1(n2295), .Y(n4031) );
OAI211X1TS U5269 ( .A0(n4874), .A1(n2289), .B0(n4032), .C0(n4031), .Y(n4813)
);
OAI2BB2X1TS U5270 ( .B0(n4898), .B1(n4811), .A0N(n2321), .A1N(n4813), .Y(
n4882) );
AOI2BB2XLTS U5271 ( .B0(n5170), .B1(n4923), .A0N(n4903), .A1N(n4882), .Y(
n1198) );
AO22XLTS U5272 ( .A0(FPADDSUB_Data_array_SWR[16]), .A1(n2395), .B0(
FPADDSUB_Data_array_SWR[12]), .B1(n2305), .Y(n4034) );
OAI22X1TS U5273 ( .A0(n4899), .A1(n2199), .B0(n5125), .B1(n4834), .Y(n4033)
);
AOI211X1TS U5274 ( .A0(FPADDSUB_Data_array_SWR[8]), .A1(n2295), .B0(n4034),
.C0(n4033), .Y(n4779) );
OAI22X1TS U5275 ( .A0(n5124), .A1(n4146), .B0(n4971), .B1(n4035), .Y(n4036)
);
OAI22X1TS U5276 ( .A0(FPADDSUB_left_right_SHT2), .A1(n4779), .B0(n2362),
.B1(n4898), .Y(n4804) );
AOI2BB2XLTS U5277 ( .B0(n5171), .B1(n4923), .A0N(n4903), .A1N(n4804), .Y(
n1197) );
AO22XLTS U5278 ( .A0(n4179), .A1(FPADDSUB_DMP_SFG[13]), .B0(n4168), .B1(
FPADDSUB_DMP_SHT2_EWSW[13]), .Y(n1242) );
CLKBUFX2TS U5279 ( .A(n4711), .Y(n4126) );
AO22XLTS U5280 ( .A0(n4221), .A1(FPMULT_Op_MY[2]), .B0(n4126), .B1(Data_2[2]), .Y(n1628) );
INVX2TS U5281 ( .A(n4710), .Y(n4127) );
CLKBUFX3TS U5282 ( .A(n4711), .Y(n4125) );
AO22XLTS U5283 ( .A0(n4127), .A1(FPMULT_Op_MY[10]), .B0(n4125), .B1(
Data_2[10]), .Y(n1636) );
INVX2TS U5284 ( .A(n4710), .Y(n4124) );
AO22XLTS U5285 ( .A0(n4124), .A1(FPMULT_Op_MY[13]), .B0(n4125), .B1(
Data_2[13]), .Y(n1639) );
AO22XLTS U5286 ( .A0(n4916), .A1(FPADDSUB_DMP_SFG[19]), .B0(n4168), .B1(
FPADDSUB_DMP_SHT2_EWSW[19]), .Y(n1222) );
AOI21X1TS U5287 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[12]), .A1(n4846), .B0(n4039),
.Y(n4043) );
OAI21XLTS U5288 ( .A0(n4042), .A1(n4044), .B0(n4040), .Y(n4041) );
NOR3BXLTS U5289 ( .AN(begin_operation), .B(n4046), .C(n4045), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]) );
AO22XLTS U5290 ( .A0(n4124), .A1(FPMULT_Op_MY[20]), .B0(n4709), .B1(
Data_2[20]), .Y(n1646) );
AO22XLTS U5291 ( .A0(n4124), .A1(n2194), .B0(n4125), .B1(Data_2[16]), .Y(
n1642) );
AO22XLTS U5292 ( .A0(n4124), .A1(FPMULT_Op_MY[18]), .B0(n4711), .B1(
Data_2[18]), .Y(n1644) );
OR2X1TS U5293 ( .A(FPSENCOS_d_ff2_Y[23]), .B(n5044), .Y(n4067) );
NAND2X1TS U5294 ( .A(FPSENCOS_d_ff2_Y[23]), .B(n5044), .Y(n4047) );
AOI32X1TS U5295 ( .A0(n4067), .A1(n4249), .A2(n4047), .B0(n5188), .B1(n4313),
.Y(n1853) );
AO22XLTS U5296 ( .A0(FPSENCOS_d_ff2_Y[28]), .A1(n4688), .B0(
FPSENCOS_d_ff_Yn[28]), .B1(n4374), .Y(n1856) );
AO22XLTS U5297 ( .A0(n4124), .A1(FPMULT_Op_MY[21]), .B0(n4717), .B1(
Data_2[21]), .Y(n1647) );
NAND2BXLTS U5298 ( .AN(n4049), .B(n4048), .Y(n2191) );
AOI22X1TS U5299 ( .A0(FPADDSUB_intDY_EWSW[3]), .A1(n2859), .B0(n4157), .B1(
Data_2[3]), .Y(n4052) );
AOI22X1TS U5300 ( .A0(n4159), .A1(FPSENCOS_d_ff3_sh_y_out[3]), .B0(n4158),
.B1(FPSENCOS_d_ff3_sh_x_out[3]), .Y(n4051) );
NAND2X1TS U5301 ( .A(n4050), .B(FPSENCOS_d_ff3_LUT_out[3]), .Y(n4154) );
NAND3XLTS U5302 ( .A(n4052), .B(n4051), .C(n4154), .Y(n1840) );
INVX2TS U5303 ( .A(n4717), .Y(n4712) );
AO22XLTS U5304 ( .A0(n4712), .A1(FPMULT_Op_MY[17]), .B0(n4717), .B1(
Data_2[17]), .Y(n1643) );
AO22XLTS U5305 ( .A0(n2377), .A1(result_add_subt[30]), .B0(
FPADDSUB_exp_rslt_NRM2_EW1[7]), .B1(n4776), .Y(n1466) );
AO22XLTS U5306 ( .A0(n4124), .A1(n2201), .B0(n4125), .B1(Data_2[11]), .Y(
n1637) );
XNOR2X1TS U5307 ( .A(n4054), .B(n4053), .Y(n4055) );
AO22XLTS U5308 ( .A0(n4352), .A1(FPMULT_P_Sgf[47]), .B0(n4343), .B1(n4055),
.Y(n1694) );
INVX2TS U5309 ( .A(n4056), .Y(n4675) );
AO22XLTS U5310 ( .A0(n4675), .A1(FPADDSUB_DmP_mant_SHT1_SW[20]), .B0(n4357),
.B1(FPADDSUB_DmP_EXP_EWSW[20]), .Y(n1391) );
AO22XLTS U5311 ( .A0(n4675), .A1(FPADDSUB_DmP_mant_SHT1_SW[19]), .B0(n4357),
.B1(FPADDSUB_DmP_EXP_EWSW[19]), .Y(n1394) );
AO22XLTS U5312 ( .A0(n4127), .A1(n2204), .B0(n4126), .B1(Data_2[4]), .Y(
n1630) );
AO22XLTS U5313 ( .A0(n4675), .A1(FPADDSUB_DmP_mant_SHT1_SW[17]), .B0(n4357),
.B1(FPADDSUB_DmP_EXP_EWSW[17]), .Y(n1388) );
AO22XLTS U5314 ( .A0(n4675), .A1(FPADDSUB_DmP_mant_SHT1_SW[13]), .B0(n4357),
.B1(FPADDSUB_DmP_EXP_EWSW[13]), .Y(n1379) );
AO22XLTS U5315 ( .A0(n4675), .A1(FPADDSUB_DmP_mant_SHT1_SW[2]), .B0(n4060),
.B1(FPADDSUB_DmP_EXP_EWSW[2]), .Y(n1311) );
AO22XLTS U5316 ( .A0(n4127), .A1(n2205), .B0(n4125), .B1(Data_2[8]), .Y(
n1634) );
NAND2X1TS U5317 ( .A(n2202), .B(n5055), .Y(n4057) );
AOI32X1TS U5318 ( .A0(n4058), .A1(n4249), .A2(n4057), .B0(n5207), .B1(n4313),
.Y(n2114) );
AO22XLTS U5319 ( .A0(n4916), .A1(FPADDSUB_DMP_SFG[18]), .B0(n4168), .B1(
FPADDSUB_DMP_SHT2_EWSW[18]), .Y(n1214) );
AO22XLTS U5320 ( .A0(n4124), .A1(n2203), .B0(n4126), .B1(Data_2[15]), .Y(
n1641) );
CMPR32X2TS U5321 ( .A(n4952), .B(FPADDSUB_DMP_EXP_EWSW[24]), .C(n4222), .CO(
n2652), .S(n4059) );
AO22XLTS U5322 ( .A0(n4675), .A1(FPADDSUB_Shift_amount_SHT1_EWR[1]), .B0(
n4060), .B1(n4059), .Y(n1476) );
INVX2TS U5323 ( .A(n4326), .Y(n4362) );
AO22XLTS U5324 ( .A0(n4362), .A1(FPSENCOS_d_ff1_shift_region_flag_out[0]),
.B0(n4320), .B1(region_flag[0]), .Y(n2135) );
AO22XLTS U5325 ( .A0(n4221), .A1(n2259), .B0(n4126), .B1(Data_2[0]), .Y(
n1626) );
AO22XLTS U5326 ( .A0(n4675), .A1(FPADDSUB_DmP_mant_SHT1_SW[12]), .B0(n4357),
.B1(FPADDSUB_DmP_EXP_EWSW[12]), .Y(n1270) );
AO22XLTS U5327 ( .A0(n4124), .A1(n2379), .B0(n4711), .B1(Data_2[22]), .Y(
n1648) );
AO22XLTS U5328 ( .A0(n4675), .A1(FPADDSUB_DmP_mant_SHT1_SW[9]), .B0(n4357),
.B1(FPADDSUB_DmP_EXP_EWSW[9]), .Y(n1283) );
AOI21X1TS U5329 ( .A0(n5174), .A1(n4730), .B0(n4061), .Y(n4062) );
AO22XLTS U5330 ( .A0(n4065), .A1(FPMULT_Add_result[12]), .B0(n4241), .B1(
n4062), .Y(n1608) );
INVX2TS U5331 ( .A(n4689), .Y(n4311) );
CLKBUFX3TS U5332 ( .A(n4687), .Y(n4289) );
AO22XLTS U5333 ( .A0(FPSENCOS_d_ff2_X[30]), .A1(n4691), .B0(
FPSENCOS_d_ff_Xn[30]), .B1(n4289), .Y(n1952) );
AO22XLTS U5334 ( .A0(n4127), .A1(n2288), .B0(n4125), .B1(Data_2[12]), .Y(
n1638) );
CLKBUFX2TS U5335 ( .A(n4687), .Y(n4063) );
AO22XLTS U5336 ( .A0(FPSENCOS_d_ff2_X[0]), .A1(n4280), .B0(
FPSENCOS_d_ff_Xn[0]), .B1(n4063), .Y(n2005) );
INVX2TS U5337 ( .A(n4689), .Y(n4123) );
AO22XLTS U5338 ( .A0(FPSENCOS_d_ff2_X[4]), .A1(n2386), .B0(
FPSENCOS_d_ff_Xn[4]), .B1(n4063), .Y(n1997) );
AO22XLTS U5339 ( .A0(FPSENCOS_d_ff2_X[8]), .A1(n4311), .B0(
FPSENCOS_d_ff_Xn[8]), .B1(n4063), .Y(n1989) );
AO22XLTS U5340 ( .A0(FPSENCOS_d_ff2_X[9]), .A1(n4375), .B0(
FPSENCOS_d_ff_Xn[9]), .B1(n4063), .Y(n1987) );
AO22XLTS U5341 ( .A0(FPSENCOS_d_ff2_X[11]), .A1(n4123), .B0(
FPSENCOS_d_ff_Xn[11]), .B1(n4063), .Y(n1983) );
AO22XLTS U5342 ( .A0(FPSENCOS_d_ff2_X[15]), .A1(n4691), .B0(
FPSENCOS_d_ff_Xn[15]), .B1(n4063), .Y(n1975) );
AO22XLTS U5343 ( .A0(FPSENCOS_d_ff2_X[21]), .A1(n4311), .B0(
FPSENCOS_d_ff_Xn[21]), .B1(n4289), .Y(n1963) );
AO22XLTS U5344 ( .A0(FPSENCOS_d_ff2_X[22]), .A1(n4375), .B0(
FPSENCOS_d_ff_Xn[22]), .B1(n4289), .Y(n1961) );
AO22XLTS U5345 ( .A0(FPSENCOS_d_ff2_X[31]), .A1(n2386), .B0(n4279), .B1(
FPSENCOS_d_ff_Xn[31]), .Y(n1943) );
AOI21X1TS U5346 ( .A0(n5108), .A1(n4724), .B0(n4728), .Y(n4064) );
AO22XLTS U5347 ( .A0(n4065), .A1(FPMULT_Add_result[6]), .B0(n4241), .B1(
n4064), .Y(n1614) );
INVX2TS U5348 ( .A(n4238), .Y(n4236) );
CLKBUFX3TS U5349 ( .A(n4257), .Y(n4202) );
AO22XLTS U5350 ( .A0(n4236), .A1(FPSENCOS_d_ff3_sh_y_out[0]), .B0(n4202),
.B1(FPSENCOS_d_ff2_Y[0]), .Y(n1906) );
AO22XLTS U5351 ( .A0(n4236), .A1(FPSENCOS_d_ff3_sh_y_out[1]), .B0(n4238),
.B1(FPSENCOS_d_ff2_Y[1]), .Y(n1904) );
AO22XLTS U5352 ( .A0(n4236), .A1(FPSENCOS_d_ff3_sh_y_out[2]), .B0(n4202),
.B1(FPSENCOS_d_ff2_Y[2]), .Y(n1902) );
AO22XLTS U5353 ( .A0(n4236), .A1(FPSENCOS_d_ff3_sh_y_out[4]), .B0(n4202),
.B1(FPSENCOS_d_ff2_Y[4]), .Y(n1898) );
AO22XLTS U5354 ( .A0(n4236), .A1(FPSENCOS_d_ff3_sh_y_out[6]), .B0(n4238),
.B1(FPSENCOS_d_ff2_Y[6]), .Y(n1894) );
AO22XLTS U5355 ( .A0(n4236), .A1(FPSENCOS_d_ff3_sh_y_out[8]), .B0(n4252),
.B1(FPSENCOS_d_ff2_Y[8]), .Y(n1890) );
CLKBUFX2TS U5356 ( .A(n4257), .Y(n4247) );
AO22XLTS U5357 ( .A0(n4236), .A1(FPSENCOS_d_ff3_sh_y_out[9]), .B0(n4247),
.B1(FPSENCOS_d_ff2_Y[9]), .Y(n1888) );
AO22XLTS U5358 ( .A0(n4236), .A1(FPSENCOS_d_ff3_sh_y_out[10]), .B0(n4262),
.B1(FPSENCOS_d_ff2_Y[10]), .Y(n1886) );
CLKBUFX2TS U5359 ( .A(n4247), .Y(n4263) );
AO22XLTS U5360 ( .A0(n4236), .A1(FPSENCOS_d_ff3_sh_y_out[12]), .B0(n4263),
.B1(FPSENCOS_d_ff2_Y[12]), .Y(n1882) );
AO22XLTS U5361 ( .A0(n4353), .A1(FPSENCOS_d_ff3_sh_y_out[21]), .B0(n4263),
.B1(FPSENCOS_d_ff2_Y[21]), .Y(n1864) );
AO22XLTS U5362 ( .A0(n4353), .A1(FPSENCOS_d_ff3_sh_y_out[24]), .B0(n4252),
.B1(n4066), .Y(n1852) );
CMPR32X2TS U5363 ( .A(FPSENCOS_d_ff2_Y[24]), .B(n2238), .C(n4067), .CO(n4069), .S(n4066) );
AO22XLTS U5364 ( .A0(n4353), .A1(FPSENCOS_d_ff3_sh_y_out[25]), .B0(n4262),
.B1(n4068), .Y(n1851) );
CMPR32X2TS U5365 ( .A(FPSENCOS_d_ff2_Y[25]), .B(n4963), .C(n4069), .CO(n4182), .S(n4068) );
AO22XLTS U5366 ( .A0(n4353), .A1(FPSENCOS_d_ff3_sh_y_out[26]), .B0(n4202),
.B1(n4070), .Y(n1850) );
NOR2X4TS U5367 ( .A(n4111), .B(n4759), .Y(n4354) );
MX2X1TS U5368 ( .A(FPMULT_Exp_module_Data_S[8]), .B(
FPMULT_exp_oper_result[8]), .S0(n4354), .Y(n1595) );
NOR4X1TS U5369 ( .A(Data_1[12]), .B(Data_1[11]), .C(Data_1[10]), .D(
Data_1[9]), .Y(n4077) );
NOR4X1TS U5370 ( .A(Data_1[8]), .B(Data_1[7]), .C(Data_1[6]), .D(Data_1[0]),
.Y(n4076) );
NOR4X1TS U5371 ( .A(Data_1[3]), .B(Data_1[16]), .C(Data_1[1]), .D(Data_1[22]), .Y(n4074) );
NOR3XLTS U5372 ( .A(Data_1[2]), .B(Data_1[5]), .C(Data_1[4]), .Y(n4073) );
NOR4X1TS U5373 ( .A(Data_1[21]), .B(Data_1[19]), .C(Data_1[14]), .D(
Data_1[20]), .Y(n4072) );
NOR4X1TS U5374 ( .A(Data_1[13]), .B(Data_1[15]), .C(Data_1[17]), .D(
Data_1[18]), .Y(n4071) );
AND4X1TS U5375 ( .A(n4074), .B(n4073), .C(n4072), .D(n4071), .Y(n4075) );
NAND3XLTS U5376 ( .A(n4077), .B(n4076), .C(n4075), .Y(n5251) );
AOI22X1TS U5377 ( .A0(FPMULT_Op_MY[18]), .A1(n2306), .B0(n2298), .B1(n4961),
.Y(n4386) );
AOI22X1TS U5378 ( .A0(FPMULT_Op_MY[17]), .A1(n2307), .B0(n2298), .B1(n5039),
.Y(n4434) );
AO22XLTS U5379 ( .A0(n2348), .A1(n4386), .B0(n4481), .B1(n4434), .Y(
mult_x_219_n198) );
AOI22X1TS U5380 ( .A0(FPMULT_Op_MY[14]), .A1(n2307), .B0(n2298), .B1(n5034),
.Y(n4380) );
AO22XLTS U5381 ( .A0(n2349), .A1(n4380), .B0(n4481), .B1(n4078), .Y(
mult_x_219_n202) );
AOI21X1TS U5382 ( .A0(n5038), .A1(n2366), .B0(mult_x_254_n151), .Y(n4392) );
AO22XLTS U5383 ( .A0(n2247), .A1(n4079), .B0(n2233), .B1(n4392), .Y(
mult_x_254_n162) );
AOI21X1TS U5384 ( .A0(n5050), .A1(n4926), .B0(mult_x_254_n63), .Y(n4391) );
AO22XLTS U5385 ( .A0(n2248), .A1(n4391), .B0(n4509), .B1(n4080), .Y(
mult_x_254_n164) );
AOI22X1TS U5386 ( .A0(FPMULT_Op_MY[6]), .A1(FPMULT_Op_MX[5]), .B0(n4955),
.B1(n5042), .Y(n4379) );
AOI22X1TS U5387 ( .A0(FPMULT_Op_MY[5]), .A1(FPMULT_Op_MX[5]), .B0(n4955),
.B1(n5038), .Y(n4420) );
AO22XLTS U5388 ( .A0(n2267), .A1(n4379), .B0(n4533), .B1(n4420), .Y(
mult_x_254_n204) );
AOI22X1TS U5389 ( .A0(FPMULT_Op_MY[2]), .A1(FPMULT_Op_MX[5]), .B0(n4955),
.B1(n5051), .Y(n4376) );
AO22XLTS U5390 ( .A0(n2267), .A1(n4376), .B0(n4081), .B1(n4533), .Y(
mult_x_254_n208) );
AOI22X1TS U5391 ( .A0(n4578), .A1(n2326), .B0(n2390), .B1(n4577), .Y(n4408)
);
AOI22X1TS U5392 ( .A0(n4581), .A1(n2326), .B0(n2325), .B1(n4580), .Y(n4413)
);
AO22XLTS U5393 ( .A0(n2286), .A1(n4408), .B0(n4412), .B1(n4413), .Y(
DP_OP_454J200_123_2743_n197) );
AOI22X1TS U5394 ( .A0(n4584), .A1(n2326), .B0(n2390), .B1(n4583), .Y(n4411)
);
AO22XLTS U5395 ( .A0(n4414), .A1(n4411), .B0(n4412), .B1(n4082), .Y(
DP_OP_454J200_123_2743_n199) );
AO22XLTS U5396 ( .A0(n4179), .A1(FPADDSUB_DMP_SFG[16]), .B0(n4904), .B1(
FPADDSUB_DMP_SHT2_EWSW[16]), .Y(n1246) );
AOI22X1TS U5397 ( .A0(FPADDSUB_intDY_EWSW[29]), .A1(n4322), .B0(n4321), .B1(
Data_2[29]), .Y(n4084) );
AOI22X1TS U5398 ( .A0(n4316), .A1(FPSENCOS_d_ff3_sh_y_out[29]), .B0(n3899),
.B1(FPSENCOS_d_ff3_sh_x_out[29]), .Y(n4083) );
NAND3XLTS U5399 ( .A(n4084), .B(n4083), .C(n4141), .Y(n1814) );
OAI22X1TS U5400 ( .A0(n4894), .A1(n2199), .B0(n5124), .B1(n4834), .Y(n4085)
);
AOI211X1TS U5401 ( .A0(FPADDSUB_Data_array_SWR[9]), .A1(n2295), .B0(n4086),
.C0(n4085), .Y(n4822) );
OAI22X1TS U5402 ( .A0(n2320), .A1(n4822), .B0(n2361), .B1(n4898), .Y(n4872)
);
AOI2BB2XLTS U5403 ( .B0(n4980), .B1(n4923), .A0N(n4903), .A1N(n4872), .Y(
n1196) );
AOI22X1TS U5404 ( .A0(FPADDSUB_intDY_EWSW[11]), .A1(n4087), .B0(n4157), .B1(
Data_2[11]), .Y(n4089) );
AOI22X1TS U5405 ( .A0(n4159), .A1(FPSENCOS_d_ff3_sh_y_out[11]), .B0(n4173),
.B1(FPSENCOS_d_ff3_sh_x_out[11]), .Y(n4088) );
NAND2X1TS U5406 ( .A(n2861), .B(FPSENCOS_d_ff3_LUT_out[7]), .Y(n4134) );
NAND3XLTS U5407 ( .A(n4089), .B(n4088), .C(n4134), .Y(n1832) );
OAI222X1TS U5408 ( .A0(n4091), .A1(n4950), .B0(n4982), .B1(
FPADDSUB_Shift_reg_FLAGS_7_6), .C0(n4090), .C1(n5183), .Y(n1465) );
AO22XLTS U5409 ( .A0(FPSENCOS_d_ff2_Y[27]), .A1(n3495), .B0(
FPSENCOS_d_ff_Yn[27]), .B1(n4374), .Y(n1857) );
AO22XLTS U5410 ( .A0(FPSENCOS_d_ff2_Y[29]), .A1(n3495), .B0(
FPSENCOS_d_ff_Yn[29]), .B1(n4374), .Y(n1855) );
AO22XLTS U5411 ( .A0(n4179), .A1(FPADDSUB_DMP_SFG[14]), .B0(n4170), .B1(
FPADDSUB_DMP_SHT2_EWSW[14]), .Y(n1258) );
NOR2X1TS U5412 ( .A(FPMULT_Op_MY[10]), .B(n2201), .Y(n4552) );
NOR4X1TS U5413 ( .A(FPMULT_Op_MY[29]), .B(FPMULT_Op_MY[28]), .C(
FPMULT_Op_MY[27]), .D(FPMULT_Op_MY[26]), .Y(n4100) );
NOR4X1TS U5414 ( .A(n2235), .B(FPMULT_Op_MY[20]), .C(FPMULT_Op_MY[21]), .D(
FPMULT_Op_MY[18]), .Y(n4092) );
NAND3XLTS U5415 ( .A(n4092), .B(n4959), .C(n5034), .Y(n4098) );
NOR4X1TS U5416 ( .A(FPMULT_Op_MY[1]), .B(n2234), .C(FPMULT_Op_MY[6]), .D(
n2368), .Y(n4096) );
NOR4X1TS U5417 ( .A(FPMULT_Op_MY[25]), .B(FPMULT_Op_MY[24]), .C(
FPMULT_Op_MY[23]), .D(FPMULT_Op_MY[30]), .Y(n4095) );
NOR4X1TS U5418 ( .A(n2258), .B(FPMULT_Op_MY[9]), .C(n2194), .D(
FPMULT_Op_MY[17]), .Y(n4094) );
NOR4X1TS U5419 ( .A(FPMULT_Op_MY[2]), .B(FPMULT_Op_MY[3]), .C(
FPMULT_Op_MY[5]), .D(FPMULT_Op_MY[7]), .Y(n4093) );
NAND4XLTS U5420 ( .A(n4096), .B(n4095), .C(n4094), .D(n4093), .Y(n4097) );
NOR4X1TS U5421 ( .A(n2287), .B(FPMULT_Op_MY[22]), .C(n4098), .D(n4097), .Y(
n4099) );
NAND4XLTS U5422 ( .A(n4552), .B(n4100), .C(n4099), .D(n5033), .Y(n4112) );
NOR4BX1TS U5423 ( .AN(n4515), .B(FPMULT_Op_MX[12]), .C(n4464), .D(n4101),
.Y(n4109) );
NOR4X1TS U5424 ( .A(n2237), .B(FPMULT_Op_MX[24]), .C(FPMULT_Op_MX[23]), .D(
FPMULT_Op_MX[11]), .Y(n4108) );
NOR4X1TS U5425 ( .A(FPMULT_Op_MX[29]), .B(FPMULT_Op_MX[25]), .C(
FPMULT_Op_MX[27]), .D(FPMULT_Op_MX[26]), .Y(n4107) );
NAND4BXLTS U5426 ( .AN(n4452), .B(n4537), .C(n4102), .D(n2354), .Y(n4105) );
NAND4XLTS U5427 ( .A(n4530), .B(n4103), .C(n5048), .D(n2299), .Y(n4104) );
NOR4X1TS U5428 ( .A(FPMULT_Op_MX[30]), .B(FPMULT_Op_MX[28]), .C(n4105), .D(
n4104), .Y(n4106) );
NAND4XLTS U5429 ( .A(n4109), .B(n4108), .C(n4107), .D(n4106), .Y(n4110) );
AOI32X1TS U5430 ( .A0(n4112), .A1(n4111), .A2(n4110), .B0(n5011), .B1(n4120),
.Y(n1625) );
INVX2TS U5431 ( .A(n4292), .Y(n4229) );
AOI32X1TS U5432 ( .A0(n4302), .A1(n4114), .A2(n4229), .B0(n4113), .B1(n4114),
.Y(FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]) );
AO22XLTS U5433 ( .A0(n4169), .A1(FPADDSUB_DMP_SFG[2]), .B0(n4178), .B1(
FPADDSUB_DMP_SHT2_EWSW[2]), .Y(n1307) );
AOI22X1TS U5434 ( .A0(FPADDSUB_intDY_EWSW[18]), .A1(n4172), .B0(n4171), .B1(
Data_2[18]), .Y(n4117) );
AOI22X1TS U5435 ( .A0(n4159), .A1(FPSENCOS_d_ff3_sh_y_out[18]), .B0(n4115),
.B1(FPSENCOS_d_ff3_sh_x_out[18]), .Y(n4116) );
NAND2X1TS U5436 ( .A(n2861), .B(FPSENCOS_d_ff3_LUT_out[13]), .Y(n4138) );
NAND3XLTS U5437 ( .A(n4117), .B(n4116), .C(n4138), .Y(n1825) );
AO22XLTS U5438 ( .A0(n4916), .A1(FPADDSUB_DMP_SFG[20]), .B0(n4168), .B1(
FPADDSUB_DMP_SHT2_EWSW[20]), .Y(n1226) );
NAND2BXLTS U5439 ( .AN(n4119), .B(n4118), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]) );
NAND2X1TS U5440 ( .A(n4120), .B(n5022), .Y(n1689) );
AO22XLTS U5441 ( .A0(n4916), .A1(FPADDSUB_DMP_SFG[21]), .B0(n4905), .B1(
FPADDSUB_DMP_SHT2_EWSW[21]), .Y(n1218) );
OAI32X4TS U5442 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .A2(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B0(n4121), .B1(n5216),
.Y(n4676) );
NOR2BX1TS U5443 ( .AN(n4122), .B(n4676), .Y(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_) );
AO21XLTS U5444 ( .A0(FPADDSUB_Shift_reg_FLAGS_7_6), .A1(n4676), .B0(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_), .Y(n2148) );
AO22XLTS U5445 ( .A0(n4363), .A1(FPSENCOS_d_ff1_shift_region_flag_out[1]),
.B0(n4320), .B1(region_flag[1]), .Y(n2134) );
AO22XLTS U5446 ( .A0(FPSENCOS_d_ff2_X[18]), .A1(n4123), .B0(
FPSENCOS_d_ff_Xn[18]), .B1(n4289), .Y(n1969) );
AO22XLTS U5447 ( .A0(n4169), .A1(FPADDSUB_DMP_SFG[1]), .B0(n4178), .B1(
FPADDSUB_DMP_SHT2_EWSW[1]), .Y(n1286) );
AO22XLTS U5448 ( .A0(n4169), .A1(FPADDSUB_OP_FLAG_SFG), .B0(n4896), .B1(
FPADDSUB_OP_FLAG_SHT2), .Y(n1352) );
AO22XLTS U5449 ( .A0(n4124), .A1(FPMULT_Op_MY[19]), .B0(n4710), .B1(
Data_2[19]), .Y(n1645) );
AO22XLTS U5450 ( .A0(n4124), .A1(FPMULT_Op_MY[14]), .B0(n4125), .B1(
Data_2[14]), .Y(n1640) );
AO22XLTS U5451 ( .A0(n4127), .A1(FPMULT_Op_MY[9]), .B0(n4125), .B1(Data_2[9]), .Y(n1635) );
AO22XLTS U5452 ( .A0(n4179), .A1(FPADDSUB_DMP_SFG[5]), .B0(n4178), .B1(
FPADDSUB_DMP_SHT2_EWSW[5]), .Y(n1272) );
AO22XLTS U5453 ( .A0(n4127), .A1(FPMULT_Op_MY[5]), .B0(n4126), .B1(Data_2[5]), .Y(n1631) );
AO22XLTS U5454 ( .A0(n4127), .A1(FPMULT_Op_MY[7]), .B0(n4125), .B1(Data_2[7]), .Y(n1633) );
AO22XLTS U5455 ( .A0(n4127), .A1(FPMULT_Op_MY[3]), .B0(n4126), .B1(Data_2[3]), .Y(n1629) );
AO22XLTS U5456 ( .A0(n4179), .A1(FPADDSUB_DMP_SFG[6]), .B0(n4168), .B1(
FPADDSUB_DMP_SHT2_EWSW[6]), .Y(n1238) );
AO22XLTS U5457 ( .A0(n4127), .A1(FPMULT_Op_MY[6]), .B0(n4125), .B1(Data_2[6]), .Y(n1632) );
AO22XLTS U5458 ( .A0(n4127), .A1(FPMULT_Op_MY[1]), .B0(n4126), .B1(Data_2[1]), .Y(n1627) );
NAND2X1TS U5459 ( .A(n4128), .B(FPSENCOS_cont_iter_out[0]), .Y(n4679) );
OA21XLTS U5460 ( .A0(n4128), .A1(FPSENCOS_cont_iter_out[0]), .B0(n4679), .Y(
n2141) );
NOR2XLTS U5461 ( .A(n4129), .B(n5030), .Y(n4132) );
OAI21XLTS U5462 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[2]), .A1(n5122), .B0(n4130),
.Y(n4131) );
XNOR2X1TS U5463 ( .A(n4132), .B(n4131), .Y(n4133) );
CLKBUFX2TS U5464 ( .A(FPADDSUB_Shift_reg_FLAGS_7[2]), .Y(n4869) );
AOI2BB2XLTS U5465 ( .B0(n4312), .B1(n4133), .A0N(
FPADDSUB_Raw_mant_NRM_SWR[2]), .A1N(n4869), .Y(n1347) );
AOI22X1TS U5466 ( .A0(FPADDSUB_intDY_EWSW[7]), .A1(n4087), .B0(n4157), .B1(
Data_2[7]), .Y(n4136) );
AOI22X1TS U5467 ( .A0(n4174), .A1(FPSENCOS_d_ff3_sh_y_out[7]), .B0(n4158),
.B1(FPSENCOS_d_ff3_sh_x_out[7]), .Y(n4135) );
NAND3XLTS U5468 ( .A(n4136), .B(n4135), .C(n4134), .Y(n1836) );
AO22XLTS U5469 ( .A0(n4312), .A1(FPADDSUB_DmP_mant_SFG_SWR[0]), .B0(n4985),
.B1(FPADDSUB_Raw_mant_NRM_SWR[0]), .Y(n1349) );
INVX2TS U5470 ( .A(n4137), .Y(n4440) );
AOI2BB2XLTS U5471 ( .B0(n5250), .B1(n5071), .A0N(
FPADDSUB_exp_rslt_NRM2_EW1[3]), .A1N(n4440), .Y(n1470) );
AOI22X1TS U5472 ( .A0(FPADDSUB_intDY_EWSW[13]), .A1(n4172), .B0(n4171), .B1(
Data_2[13]), .Y(n4140) );
AOI22X1TS U5473 ( .A0(n4316), .A1(FPSENCOS_d_ff3_sh_y_out[13]), .B0(n4173),
.B1(FPSENCOS_d_ff3_sh_x_out[13]), .Y(n4139) );
NAND3XLTS U5474 ( .A(n4140), .B(n4139), .C(n4138), .Y(n1830) );
AOI22X1TS U5475 ( .A0(FPADDSUB_intDY_EWSW[27]), .A1(n4322), .B0(n4321), .B1(
Data_2[27]), .Y(n4143) );
AOI22X1TS U5476 ( .A0(n4316), .A1(FPSENCOS_d_ff3_sh_y_out[27]), .B0(n4115),
.B1(FPSENCOS_d_ff3_sh_x_out[27]), .Y(n4142) );
NAND3XLTS U5477 ( .A(n4143), .B(n4142), .C(n4141), .Y(n1816) );
AO22XLTS U5478 ( .A0(FPADDSUB_Data_array_SWR[15]), .A1(n2252), .B0(
FPADDSUB_Data_array_SWR[11]), .B1(n2395), .Y(n4149) );
OAI2BB2XLTS U5479 ( .B0(n4802), .B1(n2289), .A0N(FPADDSUB_Data_array_SWR[3]),
.A1N(n2296), .Y(n4148) );
AOI211X1TS U5480 ( .A0(FPADDSUB_Data_array_SWR[7]), .A1(n2304), .B0(n4149),
.C0(n4148), .Y(n4794) );
OAI22X1TS U5481 ( .A0(n4796), .A1(n4898), .B0(FPADDSUB_left_right_SHT2),
.B1(n4794), .Y(n4878) );
AOI2BB2XLTS U5482 ( .B0(n5082), .B1(n4923), .A0N(n4903), .A1N(n4878), .Y(
n1202) );
AO22XLTS U5483 ( .A0(FPADDSUB_Data_array_SWR[16]), .A1(n2252), .B0(
FPADDSUB_Data_array_SWR[4]), .B1(n2296), .Y(n4151) );
OAI2BB2XLTS U5484 ( .B0(n4784), .B1(n2289), .A0N(FPADDSUB_Data_array_SWR[12]), .A1N(n2395), .Y(n4150) );
AOI211X1TS U5485 ( .A0(FPADDSUB_Data_array_SWR[8]), .A1(n2304), .B0(n4151),
.C0(n4150), .Y(n4791) );
OAI22X1TS U5486 ( .A0(n2320), .A1(n4791), .B0(n4792), .B1(n4898), .Y(n4870)
);
AOI2BB2XLTS U5487 ( .B0(n5083), .B1(n4923), .A0N(n4903), .A1N(n4870), .Y(
n1201) );
AOI22X1TS U5488 ( .A0(FPADDSUB_intDY_EWSW[15]), .A1(n4172), .B0(n4171), .B1(
Data_2[15]), .Y(n4153) );
AOI22X1TS U5489 ( .A0(n4159), .A1(FPSENCOS_d_ff3_sh_y_out[15]), .B0(n4173),
.B1(FPSENCOS_d_ff3_sh_x_out[15]), .Y(n4152) );
NAND3XLTS U5490 ( .A(n4153), .B(n4152), .C(n4175), .Y(n1828) );
AOI22X1TS U5491 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n4172), .B0(n4171), .B1(
Data_2[16]), .Y(n4156) );
AOI22X1TS U5492 ( .A0(n4316), .A1(FPSENCOS_d_ff3_sh_y_out[16]), .B0(n4173),
.B1(FPSENCOS_d_ff3_sh_x_out[16]), .Y(n4155) );
NAND3XLTS U5493 ( .A(n4156), .B(n4155), .C(n4154), .Y(n1827) );
AO22XLTS U5494 ( .A0(n4916), .A1(FPADDSUB_DMP_SFG[4]), .B0(n4905), .B1(
FPADDSUB_DMP_SHT2_EWSW[4]), .Y(n1234) );
AOI22X1TS U5495 ( .A0(FPADDSUB_intDY_EWSW[5]), .A1(n3368), .B0(n4157), .B1(
Data_2[5]), .Y(n4162) );
AOI22X1TS U5496 ( .A0(n4159), .A1(FPSENCOS_d_ff3_sh_y_out[5]), .B0(n4158),
.B1(FPSENCOS_d_ff3_sh_x_out[5]), .Y(n4161) );
NAND3XLTS U5497 ( .A(n4162), .B(n4161), .C(n4160), .Y(n1838) );
AO22XLTS U5498 ( .A0(FPSENCOS_d_ff2_X[23]), .A1(n4280), .B0(
FPSENCOS_d_ff_Xn[23]), .B1(n4289), .Y(n1959) );
OR2X1TS U5499 ( .A(FPADDSUB_ADD_OVRFLW_NRM2), .B(
FPADDSUB_LZD_output_NRM2_EW[0]), .Y(n4163) );
XOR2X1TS U5500 ( .A(n5028), .B(n4163), .Y(DP_OP_26J200_124_9022_n18) );
NOR2BX1TS U5501 ( .AN(FPADDSUB_LZD_output_NRM2_EW[1]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4164) );
XOR2X1TS U5502 ( .A(n5028), .B(n4164), .Y(DP_OP_26J200_124_9022_n17) );
NOR2BX1TS U5503 ( .AN(FPADDSUB_LZD_output_NRM2_EW[2]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4165) );
XOR2X1TS U5504 ( .A(n5028), .B(n4165), .Y(DP_OP_26J200_124_9022_n16) );
NOR2BX1TS U5505 ( .AN(FPADDSUB_LZD_output_NRM2_EW[3]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4166) );
XOR2X1TS U5506 ( .A(n5028), .B(n4166), .Y(DP_OP_26J200_124_9022_n15) );
NOR2BX1TS U5507 ( .AN(FPADDSUB_LZD_output_NRM2_EW[4]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4167) );
XOR2X1TS U5508 ( .A(n5028), .B(n4167), .Y(DP_OP_26J200_124_9022_n14) );
AO22XLTS U5509 ( .A0(n4169), .A1(FPADDSUB_DMP_SFG[0]), .B0(n4178), .B1(
FPADDSUB_DMP_SHT2_EWSW[0]), .Y(n1293) );
INVX2TS U5510 ( .A(n4676), .Y(n4678) );
AO22XLTS U5511 ( .A0(n4676), .A1(n4869), .B0(n4678), .B1(
FPADDSUB_Shift_reg_FLAGS_7[3]), .Y(n2144) );
AO22XLTS U5512 ( .A0(n4916), .A1(FPADDSUB_DMP_SFG[22]), .B0(n4168), .B1(
FPADDSUB_DMP_SHT2_EWSW[22]), .Y(n1206) );
AO22XLTS U5513 ( .A0(n4169), .A1(FPADDSUB_DMP_SFG[3]), .B0(n4168), .B1(
FPADDSUB_DMP_SHT2_EWSW[3]), .Y(n1323) );
AO22XLTS U5514 ( .A0(n4179), .A1(FPADDSUB_DMP_SFG[11]), .B0(n4178), .B1(
FPADDSUB_DMP_SHT2_EWSW[11]), .Y(n1254) );
AO22XLTS U5515 ( .A0(n4169), .A1(FPADDSUB_DMP_SFG[7]), .B0(n4168), .B1(
FPADDSUB_DMP_SHT2_EWSW[7]), .Y(n1300) );
AO22XLTS U5516 ( .A0(n4179), .A1(FPADDSUB_DMP_SFG[8]), .B0(n4170), .B1(
FPADDSUB_DMP_SHT2_EWSW[8]), .Y(n1250) );
AO22XLTS U5517 ( .A0(n4179), .A1(FPADDSUB_DMP_SFG[9]), .B0(n4896), .B1(
FPADDSUB_DMP_SHT2_EWSW[9]), .Y(n1279) );
AOI22X1TS U5518 ( .A0(FPADDSUB_intDY_EWSW[17]), .A1(n4172), .B0(n4171), .B1(
Data_2[17]), .Y(n4177) );
AOI22X1TS U5519 ( .A0(n4174), .A1(FPSENCOS_d_ff3_sh_y_out[17]), .B0(n4173),
.B1(FPSENCOS_d_ff3_sh_x_out[17]), .Y(n4176) );
NAND3XLTS U5520 ( .A(n4177), .B(n4176), .C(n4175), .Y(n1826) );
AO22XLTS U5521 ( .A0(n4179), .A1(FPADDSUB_DMP_SFG[12]), .B0(n4178), .B1(
FPADDSUB_DMP_SHT2_EWSW[12]), .Y(n1266) );
AO22XLTS U5522 ( .A0(n4181), .A1(FPADDSUB_DMP_SHT1_EWSW[11]), .B0(n4180),
.B1(FPADDSUB_DMP_SHT2_EWSW[11]), .Y(n1255) );
AOI21X1TS U5523 ( .A0(n4183), .A1(FPSENCOS_d_ff2_Y[27]), .B0(n4233), .Y(
n4184) );
AOI2BB2XLTS U5524 ( .B0(n4249), .B1(n4184), .A0N(FPSENCOS_d_ff3_sh_y_out[27]), .A1N(n4247), .Y(n1849) );
NAND2X1TS U5525 ( .A(n4233), .B(n5190), .Y(n4232) );
AOI21X1TS U5526 ( .A0(FPSENCOS_d_ff2_Y[29]), .A1(n4232), .B0(n4235), .Y(
n4185) );
AOI2BB2XLTS U5527 ( .B0(n4249), .B1(n4185), .A0N(FPSENCOS_d_ff3_sh_y_out[29]), .A1N(n4247), .Y(n1847) );
AO22XLTS U5528 ( .A0(n4226), .A1(FPADDSUB_DmP_EXP_EWSW[0]), .B0(n4225), .B1(
FPADDSUB_DmP_mant_SHT1_SW[0]), .Y(n1297) );
AO22XLTS U5529 ( .A0(FPSENCOS_d_ff2_Y[21]), .A1(n4215), .B0(
FPSENCOS_d_ff_Yn[21]), .B1(n4279), .Y(n1865) );
INVX2TS U5530 ( .A(n4252), .Y(n4339) );
AOI21X1TS U5531 ( .A0(n4187), .A1(FPSENCOS_cont_iter_out[1]), .B0(n4186),
.Y(n4337) );
AO22XLTS U5532 ( .A0(FPSENCOS_d_ff3_LUT_out[1]), .A1(n4339), .B0(n4303),
.B1(n4337), .Y(n2132) );
AO22XLTS U5533 ( .A0(n4226), .A1(FPADDSUB_DmP_EXP_EWSW[3]), .B0(n4225), .B1(
FPADDSUB_DmP_mant_SHT1_SW[3]), .Y(n1327) );
AO22XLTS U5534 ( .A0(FPSENCOS_d_ff2_Y[4]), .A1(n4375), .B0(
FPSENCOS_d_ff_Yn[4]), .B1(n4289), .Y(n1899) );
CLKBUFX3TS U5535 ( .A(n4687), .Y(n4358) );
AO22XLTS U5536 ( .A0(FPSENCOS_d_ff2_Y[6]), .A1(n4311), .B0(
FPSENCOS_d_ff_Yn[6]), .B1(n4358), .Y(n1895) );
INVX2TS U5537 ( .A(n4689), .Y(n4375) );
AO22XLTS U5538 ( .A0(FPSENCOS_d_ff2_Y[8]), .A1(n2386), .B0(
FPSENCOS_d_ff_Yn[8]), .B1(n4358), .Y(n1891) );
AO22XLTS U5539 ( .A0(n4365), .A1(FPADDSUB_DmP_EXP_EWSW[16]), .B0(n4364),
.B1(FPADDSUB_DmP_mant_SHT1_SW[16]), .Y(n1376) );
AO22XLTS U5540 ( .A0(n4356), .A1(FPADDSUB_DmP_EXP_EWSW[15]), .B0(n4984),
.B1(FPADDSUB_DmP_mant_SHT1_SW[15]), .Y(n1403) );
CLKBUFX3TS U5541 ( .A(n4257), .Y(n4190) );
AO22XLTS U5542 ( .A0(n4190), .A1(FPSENCOS_d_ff2_X[5]), .B0(n4339), .B1(
FPSENCOS_d_ff3_sh_x_out[5]), .Y(n1994) );
AO22XLTS U5543 ( .A0(FPSENCOS_d_ff2_Y[10]), .A1(n4375), .B0(
FPSENCOS_d_ff_Yn[10]), .B1(n4358), .Y(n1887) );
INVX2TS U5544 ( .A(n4252), .Y(n4191) );
AO22XLTS U5545 ( .A0(n4190), .A1(FPSENCOS_d_ff2_X[9]), .B0(n4191), .B1(
FPSENCOS_d_ff3_sh_x_out[9]), .Y(n1986) );
AO22XLTS U5546 ( .A0(n4190), .A1(FPSENCOS_d_ff2_X[1]), .B0(n4339), .B1(
FPSENCOS_d_ff3_sh_x_out[1]), .Y(n2002) );
CLKBUFX3TS U5547 ( .A(n4247), .Y(n4271) );
AO22XLTS U5548 ( .A0(n4271), .A1(FPSENCOS_d_ff2_X[0]), .B0(n4339), .B1(
FPSENCOS_d_ff3_sh_x_out[0]), .Y(n2004) );
AO22XLTS U5549 ( .A0(FPSENCOS_d_ff2_Y[12]), .A1(n4311), .B0(
FPSENCOS_d_ff_Yn[12]), .B1(n4358), .Y(n1883) );
AO22XLTS U5550 ( .A0(n4190), .A1(FPSENCOS_d_ff2_X[7]), .B0(n4191), .B1(
FPSENCOS_d_ff3_sh_x_out[7]), .Y(n1990) );
AO22XLTS U5551 ( .A0(n4190), .A1(FPSENCOS_d_ff2_X[2]), .B0(n4339), .B1(
FPSENCOS_d_ff3_sh_x_out[2]), .Y(n2000) );
INVX2TS U5552 ( .A(n4717), .Y(n4716) );
AO22XLTS U5553 ( .A0(FPMULT_Op_MY[25]), .A1(n4716), .B0(n4335), .B1(
Data_2[25]), .Y(n1651) );
AO22XLTS U5554 ( .A0(n4190), .A1(FPSENCOS_d_ff2_X[3]), .B0(n4339), .B1(
FPSENCOS_d_ff3_sh_x_out[3]), .Y(n1998) );
AO22XLTS U5555 ( .A0(FPSENCOS_d_ff2_Y[2]), .A1(n3483), .B0(
FPSENCOS_d_ff_Yn[2]), .B1(n4289), .Y(n1903) );
INVX2TS U5556 ( .A(n4263), .Y(n4270) );
AO22XLTS U5557 ( .A0(n4247), .A1(FPSENCOS_d_ff2_X[31]), .B0(n4270), .B1(
FPSENCOS_d_ff3_sh_x_out[31]), .Y(n1942) );
AO22XLTS U5558 ( .A0(n4271), .A1(FPSENCOS_d_ff2_X[12]), .B0(n4191), .B1(
FPSENCOS_d_ff3_sh_x_out[12]), .Y(n1980) );
AO22XLTS U5559 ( .A0(FPMULT_Op_MY[29]), .A1(n4370), .B0(n4335), .B1(
Data_2[29]), .Y(n1655) );
AO22XLTS U5560 ( .A0(n4190), .A1(FPSENCOS_d_ff2_X[10]), .B0(n4191), .B1(
FPSENCOS_d_ff3_sh_x_out[10]), .Y(n1984) );
AO22XLTS U5561 ( .A0(FPSENCOS_d_ff2_Y[0]), .A1(n4123), .B0(
FPSENCOS_d_ff_Yn[0]), .B1(n4289), .Y(n1907) );
AO22XLTS U5562 ( .A0(n4190), .A1(FPSENCOS_d_ff2_X[14]), .B0(n4191), .B1(
FPSENCOS_d_ff3_sh_x_out[14]), .Y(n1976) );
AO22XLTS U5563 ( .A0(n4202), .A1(FPSENCOS_d_ff2_X[11]), .B0(n4191), .B1(
FPSENCOS_d_ff3_sh_x_out[11]), .Y(n1982) );
AO22XLTS U5564 ( .A0(n4202), .A1(FPSENCOS_d_ff2_X[8]), .B0(n4191), .B1(
FPSENCOS_d_ff3_sh_x_out[8]), .Y(n1988) );
AO22XLTS U5565 ( .A0(FPSENCOS_d_ff2_Y[1]), .A1(n4691), .B0(
FPSENCOS_d_ff_Yn[1]), .B1(n4289), .Y(n1905) );
INVX2TS U5566 ( .A(n4853), .Y(n4319) );
AOI21X1TS U5567 ( .A0(FPADDSUB_DMP_SFG[22]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[24]), .B0(n4188), .Y(n4768) );
AOI21X1TS U5568 ( .A0(n4768), .A1(n5144), .B0(n2323), .Y(n4189) );
AO21XLTS U5569 ( .A0(FPADDSUB_ADD_OVRFLW_NRM), .A1(n4319), .B0(n4189), .Y(
n1351) );
INVX2TS U5570 ( .A(n4263), .Y(n4201) );
AO22XLTS U5571 ( .A0(n4190), .A1(FPSENCOS_d_ff2_X[16]), .B0(n4201), .B1(
FPSENCOS_d_ff3_sh_x_out[16]), .Y(n1972) );
AO22XLTS U5572 ( .A0(n4252), .A1(FPSENCOS_d_ff2_X[13]), .B0(n4191), .B1(
FPSENCOS_d_ff3_sh_x_out[13]), .Y(n1978) );
AO22XLTS U5573 ( .A0(n4202), .A1(FPSENCOS_d_ff2_X[6]), .B0(n4191), .B1(
FPSENCOS_d_ff3_sh_x_out[6]), .Y(n1992) );
AO22XLTS U5574 ( .A0(FPSENCOS_d_ff2_Y[9]), .A1(n4691), .B0(
FPSENCOS_d_ff_Yn[9]), .B1(n4358), .Y(n1889) );
AO22XLTS U5575 ( .A0(FPMULT_Op_MX[23]), .A1(n4370), .B0(n4335), .B1(
Data_1[23]), .Y(n1681) );
AO22XLTS U5576 ( .A0(FPMULT_Op_MY[26]), .A1(n4716), .B0(n4335), .B1(
Data_2[26]), .Y(n1652) );
AO22XLTS U5577 ( .A0(n4190), .A1(FPSENCOS_d_ff2_X[4]), .B0(n4339), .B1(
FPSENCOS_d_ff3_sh_x_out[4]), .Y(n1996) );
AO22XLTS U5578 ( .A0(n4202), .A1(FPSENCOS_d_ff2_X[17]), .B0(n4201), .B1(
FPSENCOS_d_ff3_sh_x_out[17]), .Y(n1970) );
AO22XLTS U5579 ( .A0(n4271), .A1(FPSENCOS_d_ff2_X[20]), .B0(n4201), .B1(
FPSENCOS_d_ff3_sh_x_out[20]), .Y(n1964) );
AO22XLTS U5580 ( .A0(FPMULT_Op_MX[28]), .A1(n4370), .B0(n4369), .B1(
Data_1[28]), .Y(n1686) );
AO22XLTS U5581 ( .A0(n4271), .A1(FPSENCOS_d_ff2_X[19]), .B0(n4201), .B1(
FPSENCOS_d_ff3_sh_x_out[19]), .Y(n1966) );
AO22XLTS U5582 ( .A0(n4202), .A1(FPSENCOS_d_ff2_X[15]), .B0(n4191), .B1(
FPSENCOS_d_ff3_sh_x_out[15]), .Y(n1974) );
AO22XLTS U5583 ( .A0(n4271), .A1(FPSENCOS_d_ff2_X[22]), .B0(n4201), .B1(
FPSENCOS_d_ff3_sh_x_out[22]), .Y(n1960) );
AO22XLTS U5584 ( .A0(FPMULT_Op_MX[25]), .A1(n4370), .B0(n4369), .B1(
Data_1[25]), .Y(n1683) );
NAND2X1TS U5585 ( .A(FPSENCOS_cont_iter_out[0]), .B(n5118), .Y(n4199) );
NAND2X1TS U5586 ( .A(n4245), .B(n4967), .Y(n4243) );
AOI2BB2XLTS U5587 ( .B0(FPSENCOS_d_ff2_X[30]), .B1(n4242), .A0N(n4242),
.A1N(FPSENCOS_d_ff2_X[30]), .Y(n4192) );
AO22XLTS U5588 ( .A0(n4238), .A1(n4192), .B0(n4270), .B1(
FPSENCOS_d_ff3_sh_x_out[30]), .Y(n1944) );
OAI21XLTS U5589 ( .A0(n4245), .A1(n4967), .B0(n4243), .Y(n4193) );
AO22XLTS U5590 ( .A0(n4262), .A1(n4193), .B0(n4270), .B1(
FPSENCOS_d_ff3_sh_x_out[28]), .Y(n1946) );
CLKBUFX3TS U5591 ( .A(n4257), .Y(n4250) );
AO22XLTS U5592 ( .A0(n4250), .A1(n4195), .B0(n4270), .B1(
FPSENCOS_d_ff3_sh_x_out[26]), .Y(n1948) );
AO22XLTS U5593 ( .A0(n4678), .A1(busy), .B0(n4676), .B1(
FPADDSUB_Shift_reg_FLAGS_7[3]), .Y(n2145) );
AO22XLTS U5594 ( .A0(FPMULT_Op_MX[24]), .A1(n4370), .B0(n4335), .B1(
Data_1[24]), .Y(n1682) );
CMPR32X2TS U5595 ( .A(FPSENCOS_d_ff2_X[25]), .B(n4963), .C(n4196), .CO(n4194), .S(n4197) );
AO22XLTS U5596 ( .A0(n4250), .A1(n4197), .B0(n4201), .B1(
FPSENCOS_d_ff3_sh_x_out[25]), .Y(n1949) );
CMPR32X2TS U5597 ( .A(FPSENCOS_d_ff2_X[24]), .B(n2238), .C(n4199), .CO(n4196), .S(n4198) );
AO22XLTS U5598 ( .A0(n4271), .A1(n4198), .B0(n4201), .B1(
FPSENCOS_d_ff3_sh_x_out[24]), .Y(n1950) );
OAI21XLTS U5599 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n5118), .B0(n4199),
.Y(n4200) );
AO22XLTS U5600 ( .A0(n4271), .A1(n4200), .B0(n4201), .B1(
FPSENCOS_d_ff3_sh_x_out[23]), .Y(n1951) );
AO22XLTS U5601 ( .A0(FPSENCOS_d_ff2_Y[22]), .A1(n4215), .B0(
FPSENCOS_d_ff_Yn[22]), .B1(n4279), .Y(n1863) );
AO22XLTS U5602 ( .A0(FPMULT_Op_MY[24]), .A1(n4716), .B0(n4335), .B1(
Data_2[24]), .Y(n1650) );
AO22XLTS U5603 ( .A0(n4271), .A1(FPSENCOS_d_ff2_X[21]), .B0(n4201), .B1(
FPSENCOS_d_ff3_sh_x_out[21]), .Y(n1962) );
AO22XLTS U5604 ( .A0(n4202), .A1(FPSENCOS_d_ff2_X[18]), .B0(n4201), .B1(
FPSENCOS_d_ff3_sh_x_out[18]), .Y(n1968) );
AO22XLTS U5605 ( .A0(FPSENCOS_d_ff2_Y[15]), .A1(n4123), .B0(
FPSENCOS_d_ff_Yn[15]), .B1(n4374), .Y(n1877) );
AO22XLTS U5606 ( .A0(FPMULT_Op_MY[28]), .A1(n4716), .B0(n4335), .B1(
Data_2[28]), .Y(n1654) );
AO22XLTS U5607 ( .A0(FPSENCOS_d_ff2_Y[18]), .A1(n3495), .B0(
FPSENCOS_d_ff_Yn[18]), .B1(n4374), .Y(n1871) );
AO22XLTS U5608 ( .A0(n4344), .A1(FPMULT_P_Sgf[1]), .B0(n4261), .B1(
FPMULT_Sgf_operation_Result[1]), .Y(n1530) );
AO22XLTS U5609 ( .A0(FPSENCOS_d_ff2_Y[19]), .A1(n4215), .B0(
FPSENCOS_d_ff_Yn[19]), .B1(n4279), .Y(n1869) );
NAND3X1TS U5610 ( .A(n4937), .B(n5053), .C(ready_add_subt), .Y(n4698) );
INVX2TS U5611 ( .A(n4698), .Y(n4336) );
CLKBUFX2TS U5612 ( .A(n4702), .Y(n4686) );
AO22XLTS U5613 ( .A0(n4697), .A1(result_add_subt[9]), .B0(n4686), .B1(
FPSENCOS_d_ff_Xn[9]), .Y(n2045) );
XNOR2X1TS U5614 ( .A(n4204), .B(n4203), .Y(n4205) );
XNOR2X1TS U5615 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[14]), .B(
n4205), .Y(n4206) );
AO22XLTS U5616 ( .A0(n4344), .A1(FPMULT_P_Sgf[14]), .B0(n4343), .B1(n4206),
.Y(n1543) );
NAND2BXLTS U5617 ( .AN(n4208), .B(n4207), .Y(n4209) );
XNOR2X1TS U5618 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[17]), .B(
n4209), .Y(n4210) );
AO22XLTS U5619 ( .A0(n4352), .A1(FPMULT_P_Sgf[17]), .B0(n4343), .B1(n4210),
.Y(n1546) );
XNOR2X1TS U5620 ( .A(n4212), .B(n4211), .Y(n4213) );
XNOR2X1TS U5621 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[21]), .B(
n4213), .Y(n4214) );
AO22XLTS U5622 ( .A0(n4352), .A1(FPMULT_P_Sgf[21]), .B0(n4343), .B1(n4214),
.Y(n1550) );
AO22XLTS U5623 ( .A0(FPSENCOS_d_ff2_Y[20]), .A1(n4280), .B0(
FPSENCOS_d_ff_Yn[20]), .B1(n4279), .Y(n1867) );
AO22XLTS U5624 ( .A0(n4336), .A1(result_add_subt[0]), .B0(n4702), .B1(
FPSENCOS_d_ff_Xn[0]), .Y(n2072) );
XOR2XLTS U5625 ( .A(n4217), .B(n4216), .Y(n4218) );
XNOR2X1TS U5626 ( .A(n4218), .B(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[4]), .Y(n4220) );
AO21XLTS U5627 ( .A0(n4220), .A1(n4261), .B0(n4219), .Y(n1557) );
AO22XLTS U5628 ( .A0(FPSENCOS_d_ff2_Y[17]), .A1(n4123), .B0(
FPSENCOS_d_ff_Yn[17]), .B1(n4374), .Y(n1873) );
AO22XLTS U5629 ( .A0(n4709), .A1(Data_2[31]), .B0(n4221), .B1(
FPMULT_Op_MY[31]), .Y(n1624) );
AO22XLTS U5630 ( .A0(n4356), .A1(n4224), .B0(n4223), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[0]), .Y(n1475) );
AO22XLTS U5631 ( .A0(n4371), .A1(result_add_subt[11]), .B0(n4686), .B1(
FPSENCOS_d_ff_Xn[11]), .Y(n2039) );
AO22XLTS U5632 ( .A0(FPSENCOS_d_ff2_Y[13]), .A1(n2386), .B0(
FPSENCOS_d_ff_Yn[13]), .B1(n4358), .Y(n1881) );
AO22XLTS U5633 ( .A0(n4764), .A1(FPMULT_Sgf_operation_Result[8]), .B0(n4344),
.B1(FPMULT_P_Sgf[8]), .Y(n1537) );
AO22XLTS U5634 ( .A0(n4365), .A1(FPADDSUB_DmP_EXP_EWSW[6]), .B0(n4364), .B1(
FPADDSUB_DmP_mant_SHT1_SW[6]), .Y(n1382) );
AO22XLTS U5635 ( .A0(n4365), .A1(FPADDSUB_DmP_EXP_EWSW[11]), .B0(n4364),
.B1(FPADDSUB_DmP_mant_SHT1_SW[11]), .Y(n1370) );
AO22XLTS U5636 ( .A0(n4226), .A1(FPADDSUB_DmP_EXP_EWSW[7]), .B0(n4225), .B1(
FPADDSUB_DmP_mant_SHT1_SW[7]), .Y(n1304) );
AO22XLTS U5637 ( .A0(n4228), .A1(FPADDSUB_DmP_EXP_EWSW[5]), .B0(n4227), .B1(
FPADDSUB_DmP_mant_SHT1_SW[5]), .Y(n1276) );
INVX2TS U5638 ( .A(n4263), .Y(n4256) );
AO22XLTS U5639 ( .A0(n4250), .A1(FPSENCOS_d_ff2_Y[18]), .B0(n4256), .B1(
FPSENCOS_d_ff3_sh_y_out[18]), .Y(n1870) );
AO22XLTS U5640 ( .A0(n4250), .A1(FPSENCOS_d_ff2_Y[31]), .B0(n4256), .B1(
FPSENCOS_d_ff3_sh_y_out[31]), .Y(n1844) );
AOI22X1TS U5641 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n4229), .B0(n4292),
.B1(n5044), .Y(n4230) );
AO22XLTS U5642 ( .A0(n4250), .A1(n4230), .B0(n4339), .B1(
FPSENCOS_d_ff3_LUT_out[23]), .Y(n2117) );
OAI32X1TS U5643 ( .A0(n2371), .A1(FPSENCOS_cont_iter_out[3]), .A2(n4963),
.B0(FPSENCOS_cont_iter_out[2]), .B1(n2372), .Y(n4231) );
AO22XLTS U5644 ( .A0(n4262), .A1(n4231), .B0(n4339), .B1(
FPSENCOS_d_ff3_LUT_out[25]), .Y(n2115) );
OAI21XLTS U5645 ( .A0(n4233), .A1(n5190), .B0(n4232), .Y(n4234) );
AO22XLTS U5646 ( .A0(n4250), .A1(n4234), .B0(n4256), .B1(
FPSENCOS_d_ff3_sh_y_out[28]), .Y(n1848) );
AOI2BB2XLTS U5647 ( .B0(FPSENCOS_d_ff2_Y[30]), .B1(n4235), .A0N(n4235),
.A1N(FPSENCOS_d_ff2_Y[30]), .Y(n4237) );
AO22XLTS U5648 ( .A0(n4238), .A1(n4237), .B0(n4236), .B1(
FPSENCOS_d_ff3_sh_y_out[30]), .Y(n1846) );
AO22XLTS U5649 ( .A0(n4263), .A1(FPSENCOS_d_ff2_Y[22]), .B0(n4256), .B1(
FPSENCOS_d_ff3_sh_y_out[22]), .Y(n1862) );
INVX2TS U5650 ( .A(n4239), .Y(n4240) );
AO22XLTS U5651 ( .A0(n4240), .A1(FPMULT_Sgf_normalized_result[23]), .B0(
FPMULT_FSM_add_overflow_flag), .B1(n4737), .Y(n1596) );
AOI2BB2XLTS U5652 ( .B0(n4742), .B1(FPMULT_Sgf_normalized_result[0]), .A0N(
FPMULT_Add_result[0]), .A1N(n4241), .Y(n1620) );
AO22XLTS U5653 ( .A0(n4250), .A1(FPSENCOS_d_ff2_Y[15]), .B0(n4270), .B1(
FPSENCOS_d_ff3_sh_y_out[15]), .Y(n1876) );
AOI21X1TS U5654 ( .A0(FPSENCOS_d_ff2_X[29]), .A1(n4243), .B0(n4242), .Y(
n4244) );
AOI2BB2XLTS U5655 ( .B0(n4249), .B1(n4244), .A0N(FPSENCOS_d_ff3_sh_x_out[29]), .A1N(n4257), .Y(n1945) );
AO22XLTS U5656 ( .A0(n4250), .A1(FPSENCOS_d_ff2_Y[19]), .B0(n4256), .B1(
FPSENCOS_d_ff3_sh_y_out[19]), .Y(n1868) );
AOI21X1TS U5657 ( .A0(n4246), .A1(FPSENCOS_d_ff2_X[27]), .B0(n4245), .Y(
n4248) );
AOI2BB2XLTS U5658 ( .B0(n4249), .B1(n4248), .A0N(FPSENCOS_d_ff3_sh_x_out[27]), .A1N(n4247), .Y(n1947) );
INVX2TS U5659 ( .A(n4269), .Y(n4264) );
AO22XLTS U5660 ( .A0(FPMULT_Sgf_normalized_result[18]), .A1(n4264), .B0(
mult_result[18]), .B1(n4745), .Y(n1486) );
AO22XLTS U5661 ( .A0(n4250), .A1(FPSENCOS_d_ff2_Y[20]), .B0(n4256), .B1(
FPSENCOS_d_ff3_sh_y_out[20]), .Y(n1866) );
CLKBUFX3TS U5662 ( .A(n4709), .Y(n4715) );
AO22XLTS U5663 ( .A0(FPMULT_Op_MY[23]), .A1(n4716), .B0(n4715), .B1(
Data_2[23]), .Y(n1649) );
INVX2TS U5664 ( .A(n4269), .Y(n4251) );
CLKBUFX3TS U5665 ( .A(n4273), .Y(n4272) );
AO22XLTS U5666 ( .A0(FPMULT_Sgf_normalized_result[22]), .A1(n4251), .B0(
mult_result[22]), .B1(n4272), .Y(n1481) );
AO22XLTS U5667 ( .A0(n4250), .A1(FPSENCOS_d_ff2_Y[17]), .B0(n4256), .B1(
FPSENCOS_d_ff3_sh_y_out[17]), .Y(n1872) );
AO22XLTS U5668 ( .A0(FPMULT_Sgf_normalized_result[21]), .A1(n4251), .B0(
mult_result[21]), .B1(n4745), .Y(n1483) );
AO22XLTS U5669 ( .A0(n4271), .A1(FPSENCOS_d_ff2_Y[13]), .B0(n4270), .B1(
FPSENCOS_d_ff3_sh_y_out[13]), .Y(n1880) );
AO22XLTS U5670 ( .A0(FPMULT_Sgf_normalized_result[20]), .A1(n4251), .B0(
mult_result[20]), .B1(n4745), .Y(n1484) );
AO22XLTS U5671 ( .A0(n4370), .A1(FPMULT_Op_MY[30]), .B0(n4335), .B1(
Data_2[30]), .Y(n1656) );
AO22XLTS U5672 ( .A0(n4262), .A1(FPSENCOS_d_ff2_Y[16]), .B0(n4256), .B1(
FPSENCOS_d_ff3_sh_y_out[16]), .Y(n1874) );
AO22XLTS U5673 ( .A0(FPMULT_Sgf_normalized_result[19]), .A1(n4264), .B0(
mult_result[19]), .B1(n4745), .Y(n1485) );
AO22XLTS U5674 ( .A0(FPMULT_Sgf_normalized_result[17]), .A1(n4264), .B0(
mult_result[17]), .B1(n4745), .Y(n1487) );
AO22XLTS U5675 ( .A0(n4252), .A1(FPSENCOS_d_ff2_Y[11]), .B0(n4256), .B1(
FPSENCOS_d_ff3_sh_y_out[11]), .Y(n1884) );
AO22XLTS U5676 ( .A0(FPMULT_Sgf_normalized_result[16]), .A1(n4264), .B0(
mult_result[16]), .B1(n4745), .Y(n1488) );
AOI21X1TS U5677 ( .A0(n4254), .A1(n4253), .B0(n4753), .Y(n4255) );
AO22XLTS U5678 ( .A0(n4268), .A1(FPMULT_P_Sgf[38]), .B0(n4261), .B1(n4255),
.Y(n1567) );
AO22XLTS U5679 ( .A0(n4262), .A1(FPSENCOS_d_ff2_Y[14]), .B0(n4256), .B1(
FPSENCOS_d_ff3_sh_y_out[14]), .Y(n1878) );
AO22XLTS U5680 ( .A0(FPMULT_Sgf_normalized_result[15]), .A1(n4264), .B0(
mult_result[15]), .B1(n4745), .Y(n1489) );
AO22XLTS U5681 ( .A0(FPMULT_Sgf_normalized_result[14]), .A1(n4264), .B0(
mult_result[14]), .B1(n4745), .Y(n1490) );
AO22XLTS U5682 ( .A0(n4257), .A1(FPSENCOS_d_ff2_Y[3]), .B0(n4270), .B1(
FPSENCOS_d_ff3_sh_y_out[3]), .Y(n1900) );
AO22XLTS U5683 ( .A0(FPMULT_Sgf_normalized_result[13]), .A1(n4264), .B0(
mult_result[13]), .B1(n4272), .Y(n1491) );
CMPR32X2TS U5684 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[6]), .B(
n4259), .C(n4258), .CO(n2626), .S(n4260) );
AO22XLTS U5685 ( .A0(n4268), .A1(FPMULT_P_Sgf[30]), .B0(n4261), .B1(n4260),
.Y(n1559) );
AO22XLTS U5686 ( .A0(n4262), .A1(FPSENCOS_d_ff2_Y[7]), .B0(n4270), .B1(
FPSENCOS_d_ff3_sh_y_out[7]), .Y(n1892) );
AO22XLTS U5687 ( .A0(FPMULT_Sgf_normalized_result[12]), .A1(n4264), .B0(
mult_result[12]), .B1(n4272), .Y(n1492) );
AO22XLTS U5688 ( .A0(FPMULT_Sgf_normalized_result[11]), .A1(n4264), .B0(
mult_result[11]), .B1(n4272), .Y(n1493) );
AO22XLTS U5689 ( .A0(n4263), .A1(FPSENCOS_d_ff2_Y[5]), .B0(n4270), .B1(
FPSENCOS_d_ff3_sh_y_out[5]), .Y(n1896) );
AO22XLTS U5690 ( .A0(FPMULT_Sgf_normalized_result[10]), .A1(n4264), .B0(
mult_result[10]), .B1(n4272), .Y(n1494) );
CMPR32X2TS U5691 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[3]), .B(
n4266), .C(n4265), .CO(n4216), .S(n4267) );
AO22XLTS U5692 ( .A0(n4268), .A1(FPMULT_P_Sgf[27]), .B0(n4351), .B1(n4267),
.Y(n1556) );
INVX2TS U5693 ( .A(n4269), .Y(n4274) );
AO22XLTS U5694 ( .A0(FPMULT_Sgf_normalized_result[9]), .A1(n4274), .B0(
mult_result[9]), .B1(n4272), .Y(n1495) );
AO22XLTS U5695 ( .A0(FPMULT_Sgf_normalized_result[8]), .A1(n4274), .B0(
mult_result[8]), .B1(n4272), .Y(n1496) );
AO22XLTS U5696 ( .A0(FPMULT_Sgf_normalized_result[7]), .A1(n4274), .B0(
mult_result[7]), .B1(n4272), .Y(n1497) );
AO22XLTS U5697 ( .A0(n4271), .A1(FPSENCOS_d_ff2_Z[31]), .B0(n4270), .B1(
FPSENCOS_d_ff3_sign_out), .Y(n1732) );
AO22XLTS U5698 ( .A0(FPMULT_Sgf_normalized_result[6]), .A1(n4274), .B0(
mult_result[6]), .B1(n4272), .Y(n1498) );
AO22XLTS U5699 ( .A0(FPMULT_Sgf_normalized_result[5]), .A1(n4274), .B0(
mult_result[5]), .B1(n4272), .Y(n1499) );
AO22XLTS U5700 ( .A0(FPMULT_Sgf_normalized_result[4]), .A1(n4274), .B0(
mult_result[4]), .B1(n4273), .Y(n1500) );
AO22XLTS U5701 ( .A0(FPMULT_Sgf_normalized_result[3]), .A1(n4274), .B0(
mult_result[3]), .B1(n4273), .Y(n1501) );
AO22XLTS U5702 ( .A0(FPMULT_Sgf_normalized_result[2]), .A1(n4274), .B0(
mult_result[2]), .B1(n4273), .Y(n1502) );
CLKBUFX3TS U5703 ( .A(n4702), .Y(n4696) );
AO22XLTS U5704 ( .A0(n4697), .A1(result_add_subt[31]), .B0(n4696), .B1(
FPSENCOS_d_ff_Xn[31]), .Y(n1727) );
AO22XLTS U5705 ( .A0(FPMULT_Sgf_normalized_result[1]), .A1(n4274), .B0(
mult_result[1]), .B1(n4273), .Y(n1503) );
AO22XLTS U5706 ( .A0(FPMULT_Sgf_normalized_result[0]), .A1(n4274), .B0(
mult_result[0]), .B1(n4273), .Y(n1504) );
AO22XLTS U5707 ( .A0(FPMULT_Op_MX[27]), .A1(n4370), .B0(n4369), .B1(
Data_1[27]), .Y(n1685) );
MX2X1TS U5708 ( .A(FPADDSUB_DMP_exp_NRM2_EW[4]), .B(
FPADDSUB_DMP_exp_NRM_EW[4]), .S0(n4290), .Y(n1433) );
NOR2XLTS U5709 ( .A(n4277), .B(n4276), .Y(n4275) );
AOI21X1TS U5710 ( .A0(n4277), .A1(n4276), .B0(n4275), .Y(n4278) );
AO22XLTS U5711 ( .A0(n4344), .A1(FPMULT_P_Sgf[12]), .B0(n4343), .B1(n4278),
.Y(n1541) );
AO22XLTS U5712 ( .A0(FPSENCOS_d_ff2_Y[31]), .A1(n4215), .B0(n4279), .B1(
FPSENCOS_d_ff_Yn[31]), .Y(n1845) );
AO22XLTS U5713 ( .A0(n4336), .A1(result_add_subt[21]), .B0(n4696), .B1(
FPSENCOS_d_ff_Xn[21]), .Y(n2009) );
CLKBUFX3TS U5714 ( .A(n4326), .Y(n4355) );
AO22XLTS U5715 ( .A0(n4362), .A1(FPSENCOS_d_ff1_Z[19]), .B0(n4355), .B1(
Data_1[19]), .Y(n2093) );
MX2X1TS U5716 ( .A(FPADDSUB_DMP_exp_NRM2_EW[3]), .B(
FPADDSUB_DMP_exp_NRM_EW[3]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1438) );
NAND2BXLTS U5717 ( .AN(n4282), .B(n4281), .Y(n4283) );
XNOR2X1TS U5718 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[16]), .B(
n4283), .Y(n4284) );
AO22XLTS U5719 ( .A0(n4352), .A1(FPMULT_P_Sgf[16]), .B0(n4343), .B1(n4284),
.Y(n1545) );
MX2X1TS U5720 ( .A(FPADDSUB_DMP_exp_NRM2_EW[2]), .B(
FPADDSUB_DMP_exp_NRM_EW[2]), .S0(n3560), .Y(n1443) );
AO22XLTS U5721 ( .A0(n4362), .A1(FPSENCOS_d_ff1_Z[20]), .B0(n4355), .B1(
Data_1[20]), .Y(n2092) );
NAND2BXLTS U5722 ( .AN(n4286), .B(n4285), .Y(n4287) );
XNOR2X1TS U5723 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[18]), .B(
n4287), .Y(n4288) );
AO22XLTS U5724 ( .A0(n4352), .A1(FPMULT_P_Sgf[18]), .B0(n4343), .B1(n4288),
.Y(n1547) );
MX2X1TS U5725 ( .A(FPADDSUB_DMP_exp_NRM2_EW[1]), .B(
FPADDSUB_DMP_exp_NRM_EW[1]), .S0(n4290), .Y(n1448) );
AO22XLTS U5726 ( .A0(n4764), .A1(FPMULT_Sgf_operation_Result[4]), .B0(n4755),
.B1(FPMULT_P_Sgf[4]), .Y(n1533) );
MX2X1TS U5727 ( .A(FPMULT_Exp_module_Data_S[7]), .B(
FPMULT_exp_oper_result[7]), .S0(n4354), .Y(n1587) );
MX2X1TS U5728 ( .A(FPMULT_Op_MX[30]), .B(FPMULT_exp_oper_result[7]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[7]) );
AO22XLTS U5729 ( .A0(n4362), .A1(FPSENCOS_d_ff1_Z[21]), .B0(n4355), .B1(
Data_1[21]), .Y(n2091) );
AO22XLTS U5730 ( .A0(FPSENCOS_d_ff2_Y[3]), .A1(n2386), .B0(
FPSENCOS_d_ff_Yn[3]), .B1(n4289), .Y(n1901) );
MX2X1TS U5731 ( .A(FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
FPADDSUB_DMP_exp_NRM_EW[0]), .S0(n4290), .Y(n1453) );
AO22XLTS U5732 ( .A0(n4764), .A1(FPMULT_Sgf_operation_Result[11]), .B0(n4344), .B1(FPMULT_P_Sgf[11]), .Y(n1540) );
AO22XLTS U5733 ( .A0(n4362), .A1(FPSENCOS_d_ff1_Z[22]), .B0(n4355), .B1(
Data_1[22]), .Y(n2090) );
AO22XLTS U5734 ( .A0(n4371), .A1(result_add_subt[18]), .B0(n4696), .B1(
FPSENCOS_d_ff_Xn[18]), .Y(n2018) );
AOI22X1TS U5735 ( .A0(FPSENCOS_d_ff3_LUT_out[24]), .A1(n4313), .B0(n2372),
.B1(n4345), .Y(n4293) );
AOI32X1TS U5736 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n4293), .A2(n4292),
.B0(n4291), .B1(n4293), .Y(n2116) );
NAND2BXLTS U5737 ( .AN(n4295), .B(n4294), .Y(n4296) );
XNOR2X1TS U5738 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[13]), .B(
n4296), .Y(n4297) );
AO22XLTS U5739 ( .A0(n4344), .A1(FPMULT_P_Sgf[13]), .B0(n4343), .B1(n4297),
.Y(n1542) );
AO22XLTS U5740 ( .A0(n4373), .A1(FPSENCOS_d_ff1_Z[23]), .B0(n4355), .B1(
Data_1[23]), .Y(n2089) );
NAND2BXLTS U5741 ( .AN(n4299), .B(n4298), .Y(n4300) );
XNOR2X1TS U5742 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[20]), .B(
n4300), .Y(n4301) );
AO22XLTS U5743 ( .A0(n4352), .A1(FPMULT_P_Sgf[20]), .B0(n4351), .B1(n4301),
.Y(n1549) );
AO22XLTS U5744 ( .A0(FPSENCOS_d_ff2_Y[7]), .A1(n4375), .B0(
FPSENCOS_d_ff_Yn[7]), .B1(n4358), .Y(n1893) );
MX2X1TS U5745 ( .A(FPMULT_Exp_module_Data_S[6]), .B(
FPMULT_exp_oper_result[6]), .S0(n4354), .Y(n1588) );
MX2X1TS U5746 ( .A(FPMULT_Op_MX[29]), .B(FPMULT_exp_oper_result[6]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[6]) );
AOI22X1TS U5747 ( .A0(FPSENCOS_d_ff3_LUT_out[10]), .A1(n4313), .B0(n2372),
.B1(n4345), .Y(n4304) );
NAND3XLTS U5748 ( .A(FPSENCOS_cont_iter_out[1]), .B(
FPSENCOS_cont_iter_out[3]), .C(n4307), .Y(n4309) );
NAND3XLTS U5749 ( .A(n4305), .B(n4963), .C(n4303), .Y(n4314) );
NAND3XLTS U5750 ( .A(n4304), .B(n4309), .C(n4314), .Y(n2123) );
AO22XLTS U5751 ( .A0(n4362), .A1(FPSENCOS_d_ff1_Z[24]), .B0(n4355), .B1(
Data_1[24]), .Y(n2088) );
AO22XLTS U5752 ( .A0(n4312), .A1(FPADDSUB_DMP_SFG[30]), .B0(n4985), .B1(
FPADDSUB_DMP_exp_NRM_EW[7]), .Y(n1419) );
AO22XLTS U5753 ( .A0(n4363), .A1(FPSENCOS_d_ff1_Z[25]), .B0(n4320), .B1(
Data_1[25]), .Y(n2087) );
AOI22X1TS U5754 ( .A0(FPSENCOS_d_ff3_LUT_out[6]), .A1(n4313), .B0(n4306),
.B1(n4305), .Y(n4310) );
OAI211XLTS U5755 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(
FPSENCOS_cont_iter_out[3]), .B0(FPSENCOS_cont_iter_out[0]), .C0(n4307),
.Y(n4308) );
NAND3XLTS U5756 ( .A(n4310), .B(n4309), .C(n4308), .Y(n2127) );
AO22XLTS U5757 ( .A0(n4312), .A1(FPADDSUB_DMP_SFG[29]), .B0(n4985), .B1(
FPADDSUB_DMP_exp_NRM_EW[6]), .Y(n1424) );
AO22XLTS U5758 ( .A0(n4697), .A1(result_add_subt[15]), .B0(n4696), .B1(
FPSENCOS_d_ff_Xn[15]), .Y(n2027) );
AO22XLTS U5759 ( .A0(n4312), .A1(FPADDSUB_DMP_SFG[28]), .B0(n4985), .B1(
FPADDSUB_DMP_exp_NRM_EW[5]), .Y(n1429) );
AO22XLTS U5760 ( .A0(FPSENCOS_d_ff2_Y[5]), .A1(n4311), .B0(
FPSENCOS_d_ff_Yn[5]), .B1(n4358), .Y(n1897) );
INVX2TS U5761 ( .A(n4326), .Y(n4327) );
AO22XLTS U5762 ( .A0(n4327), .A1(FPSENCOS_d_ff1_Z[26]), .B0(n4320), .B1(
Data_1[26]), .Y(n2086) );
AO22XLTS U5763 ( .A0(n4312), .A1(FPADDSUB_DMP_SFG[27]), .B0(n4985), .B1(
FPADDSUB_DMP_exp_NRM_EW[4]), .Y(n1434) );
MX2X1TS U5764 ( .A(FPMULT_Exp_module_Data_S[5]), .B(
FPMULT_exp_oper_result[5]), .S0(n4354), .Y(n1589) );
MX2X1TS U5765 ( .A(FPMULT_Op_MX[28]), .B(FPMULT_exp_oper_result[5]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[5]) );
AO22XLTS U5766 ( .A0(n4327), .A1(FPSENCOS_d_ff1_Z[27]), .B0(n4320), .B1(
Data_1[27]), .Y(n2085) );
AOI22X1TS U5767 ( .A0(FPSENCOS_d_ff3_LUT_out[0]), .A1(n4313), .B0(
FPSENCOS_cont_iter_out[1]), .B1(n4338), .Y(n4315) );
NAND2X1TS U5768 ( .A(n4315), .B(n4314), .Y(n2133) );
AO22XLTS U5769 ( .A0(n4869), .A1(FPADDSUB_DMP_SFG[26]), .B0(n4319), .B1(
FPADDSUB_DMP_exp_NRM_EW[3]), .Y(n1439) );
AO22XLTS U5770 ( .A0(n4327), .A1(FPSENCOS_d_ff1_Z[28]), .B0(n4355), .B1(
Data_1[28]), .Y(n2084) );
AO22XLTS U5771 ( .A0(n4869), .A1(FPADDSUB_DMP_SFG[25]), .B0(n4985), .B1(
FPADDSUB_DMP_exp_NRM_EW[2]), .Y(n1444) );
AO22XLTS U5772 ( .A0(n4327), .A1(FPSENCOS_d_ff1_Z[29]), .B0(n4320), .B1(
Data_1[29]), .Y(n2083) );
AO22XLTS U5773 ( .A0(n4336), .A1(result_add_subt[22]), .B0(n4696), .B1(
FPSENCOS_d_ff_Xn[22]), .Y(n2006) );
AO22XLTS U5774 ( .A0(n4869), .A1(FPADDSUB_DMP_SFG[24]), .B0(n4867), .B1(
FPADDSUB_DMP_exp_NRM_EW[1]), .Y(n1449) );
AOI22X1TS U5775 ( .A0(FPADDSUB_intDY_EWSW[31]), .A1(n4322), .B0(n4321), .B1(
Data_2[31]), .Y(n4318) );
AOI22X1TS U5776 ( .A0(n4316), .A1(FPSENCOS_d_ff3_sh_y_out[31]), .B0(n3899),
.B1(FPSENCOS_d_ff3_sh_x_out[31]), .Y(n4317) );
NAND2X1TS U5777 ( .A(n4318), .B(n4317), .Y(n1728) );
MX2X1TS U5778 ( .A(FPMULT_Exp_module_Data_S[4]), .B(
FPMULT_exp_oper_result[4]), .S0(n4354), .Y(n1590) );
MX2X1TS U5779 ( .A(FPMULT_Op_MX[27]), .B(FPMULT_exp_oper_result[4]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[4]) );
AO22XLTS U5780 ( .A0(n4869), .A1(FPADDSUB_DMP_SFG[23]), .B0(n4846), .B1(
FPADDSUB_DMP_exp_NRM_EW[0]), .Y(n1454) );
AO22XLTS U5781 ( .A0(n4327), .A1(FPSENCOS_d_ff1_Z[30]), .B0(n4320), .B1(
Data_1[30]), .Y(n2082) );
AOI22X1TS U5782 ( .A0(FPADDSUB_intAS), .A1(n4322), .B0(n4321), .B1(
operation[0]), .Y(n4325) );
OAI21XLTS U5783 ( .A0(FPSENCOS_cont_var_out[0]), .A1(FPSENCOS_d_ff3_sign_out), .B0(n4323), .Y(n4324) );
AOI32X1TS U5784 ( .A0(FPSENCOS_d_ff3_sign_out), .A1(n4325), .A2(
FPSENCOS_cont_var_out[0]), .B0(n4324), .B1(n4325), .Y(n1731) );
AO22XLTS U5785 ( .A0(n4327), .A1(FPSENCOS_d_ff1_Z[31]), .B0(n4326), .B1(
Data_1[31]), .Y(n2081) );
XOR2XLTS U5786 ( .A(n4329), .B(n4328), .Y(n4330) );
XNOR2X1TS U5787 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[22]), .B(
n4330), .Y(n4331) );
AO22XLTS U5788 ( .A0(n4352), .A1(FPMULT_P_Sgf[22]), .B0(n4351), .B1(n4331),
.Y(n1551) );
MX2X1TS U5789 ( .A(FPMULT_Exp_module_Data_S[0]), .B(
FPMULT_exp_oper_result[0]), .S0(n4354), .Y(n1594) );
CMPR32X2TS U5790 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[23]), .B(
n4333), .C(n4332), .CO(n2568), .S(n4334) );
AO22XLTS U5791 ( .A0(n4352), .A1(FPMULT_P_Sgf[23]), .B0(n4351), .B1(n4334),
.Y(n1552) );
AO22XLTS U5792 ( .A0(FPMULT_Op_MY[27]), .A1(n4716), .B0(n4335), .B1(
Data_2[27]), .Y(n1653) );
AO22XLTS U5793 ( .A0(n4363), .A1(FPSENCOS_d_ff1_Z[0]), .B0(n4326), .B1(
Data_1[0]), .Y(n2112) );
MX2X1TS U5794 ( .A(FPMULT_Exp_module_Data_S[3]), .B(
FPMULT_exp_oper_result[3]), .S0(n4354), .Y(n1591) );
MX2X1TS U5795 ( .A(FPMULT_Op_MX[26]), .B(FPMULT_exp_oper_result[3]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[3]) );
AO22XLTS U5796 ( .A0(n4371), .A1(result_add_subt[30]), .B0(n4696), .B1(
FPSENCOS_d_ff_Xn[30]), .Y(n1729) );
AO22XLTS U5797 ( .A0(n4697), .A1(result_add_subt[23]), .B0(n4696), .B1(
FPSENCOS_d_ff_Xn[23]), .Y(n1784) );
AO21XLTS U5798 ( .A0(FPSENCOS_d_ff3_LUT_out[3]), .A1(n4346), .B0(n4337), .Y(
n2130) );
AO22XLTS U5799 ( .A0(n4365), .A1(FPADDSUB_DmP_EXP_EWSW[22]), .B0(n4984),
.B1(FPADDSUB_DmP_mant_SHT1_SW[22]), .Y(n1406) );
MX2X1TS U5800 ( .A(FPMULT_Exp_module_Data_S[1]), .B(
FPMULT_exp_oper_result[1]), .S0(n4354), .Y(n1593) );
AO21XLTS U5801 ( .A0(FPSENCOS_d_ff3_LUT_out[13]), .A1(n4339), .B0(n4338),
.Y(n2121) );
CMPR32X2TS U5802 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[15]), .B(
n4341), .C(n4340), .CO(n2542), .S(n4342) );
AO22XLTS U5803 ( .A0(n4344), .A1(FPMULT_P_Sgf[15]), .B0(n4343), .B1(n4342),
.Y(n1544) );
AO21XLTS U5804 ( .A0(FPSENCOS_d_ff3_LUT_out[19]), .A1(n4346), .B0(n4345),
.Y(n2119) );
NAND2BXLTS U5805 ( .AN(n4348), .B(n4347), .Y(n4349) );
XNOR2X1TS U5806 ( .A(FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_right[19]), .B(
n4349), .Y(n4350) );
AO22XLTS U5807 ( .A0(n4352), .A1(FPMULT_P_Sgf[19]), .B0(n4351), .B1(n4350),
.Y(n1548) );
NAND2BXLTS U5808 ( .AN(FPSENCOS_d_ff3_LUT_out[27]), .B(n4353), .Y(n2113) );
MX2X1TS U5809 ( .A(FPMULT_Exp_module_Data_S[2]), .B(
FPMULT_exp_oper_result[2]), .S0(n4354), .Y(n1592) );
MX2X1TS U5810 ( .A(FPMULT_Op_MX[23]), .B(FPMULT_exp_oper_result[0]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[0]) );
MX2X1TS U5811 ( .A(FPMULT_Op_MX[24]), .B(FPMULT_exp_oper_result[1]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[1]) );
MX2X1TS U5812 ( .A(FPMULT_Op_MX[25]), .B(FPMULT_exp_oper_result[2]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[2]) );
AO22XLTS U5813 ( .A0(n4356), .A1(FPADDSUB_DmP_EXP_EWSW[21]), .B0(n4364),
.B1(FPADDSUB_DmP_mant_SHT1_SW[21]), .Y(n1397) );
AO22XLTS U5814 ( .A0(n4362), .A1(FPSENCOS_d_ff1_Z[18]), .B0(n4355), .B1(
Data_1[18]), .Y(n2094) );
AO22XLTS U5815 ( .A0(n4362), .A1(FPSENCOS_d_ff1_Z[16]), .B0(n4355), .B1(
Data_1[16]), .Y(n2096) );
AO22XLTS U5816 ( .A0(n4363), .A1(FPSENCOS_d_ff1_Z[14]), .B0(n4372), .B1(
Data_1[14]), .Y(n2098) );
AO22XLTS U5817 ( .A0(n4365), .A1(FPADDSUB_DmP_EXP_EWSW[18]), .B0(n4364),
.B1(FPADDSUB_DmP_mant_SHT1_SW[18]), .Y(n1400) );
AO22XLTS U5818 ( .A0(n4362), .A1(FPSENCOS_d_ff1_Z[17]), .B0(n4355), .B1(
Data_1[17]), .Y(n2095) );
AO22XLTS U5819 ( .A0(n4365), .A1(FPADDSUB_DmP_EXP_EWSW[10]), .B0(n4364),
.B1(FPADDSUB_DmP_mant_SHT1_SW[10]), .Y(n1364) );
AO22XLTS U5820 ( .A0(FPSENCOS_d_ff2_Y[14]), .A1(n4375), .B0(
FPSENCOS_d_ff_Yn[14]), .B1(n4358), .Y(n1879) );
AO22XLTS U5821 ( .A0(n4356), .A1(FPADDSUB_DmP_EXP_EWSW[4]), .B0(n4364), .B1(
FPADDSUB_DmP_mant_SHT1_SW[4]), .Y(n1385) );
AO22XLTS U5822 ( .A0(n4360), .A1(FPADDSUB_DmP_mant_SHT1_SW[1]), .B0(n4357),
.B1(FPADDSUB_DmP_EXP_EWSW[1]), .Y(n1290) );
AO22XLTS U5823 ( .A0(n4373), .A1(FPSENCOS_d_ff1_Z[11]), .B0(n4372), .B1(
Data_1[11]), .Y(n2101) );
MX2X1TS U5824 ( .A(FPADDSUB_DMP_exp_NRM2_EW[6]), .B(
FPADDSUB_DMP_exp_NRM_EW[6]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1423) );
AO22XLTS U5825 ( .A0(FPSENCOS_d_ff2_Y[11]), .A1(n4691), .B0(
FPSENCOS_d_ff_Yn[11]), .B1(n4358), .Y(n1885) );
CMPR32X2TS U5826 ( .A(n4953), .B(FPADDSUB_DMP_EXP_EWSW[26]), .C(n4359), .CO(
n2650), .S(n4361) );
AO22XLTS U5827 ( .A0(FPADDSUB_Shift_reg_FLAGS_7_5), .A1(n4361), .B0(n4360),
.B1(FPADDSUB_Shift_amount_SHT1_EWR[3]), .Y(n1478) );
AO22XLTS U5828 ( .A0(n4362), .A1(FPSENCOS_d_ff1_Z[15]), .B0(n4372), .B1(
Data_1[15]), .Y(n2097) );
AO22XLTS U5829 ( .A0(n4365), .A1(FPADDSUB_DmP_EXP_EWSW[8]), .B0(n4364), .B1(
FPADDSUB_DmP_mant_SHT1_SW[8]), .Y(n1373) );
AO22XLTS U5830 ( .A0(n4363), .A1(FPSENCOS_d_ff1_Z[13]), .B0(n4372), .B1(
Data_1[13]), .Y(n2099) );
AO22XLTS U5831 ( .A0(n4365), .A1(FPADDSUB_DmP_EXP_EWSW[14]), .B0(n4364),
.B1(FPADDSUB_DmP_mant_SHT1_SW[14]), .Y(n1367) );
MX2X1TS U5832 ( .A(FPADDSUB_DMP_exp_NRM2_EW[5]), .B(
FPADDSUB_DMP_exp_NRM_EW[5]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1428) );
CMPR32X2TS U5833 ( .A(n4368), .B(n4367), .C(n4366), .CO(n2754), .S(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N5) );
MX2X1TS U5834 ( .A(FPADDSUB_DMP_exp_NRM2_EW[7]), .B(
FPADDSUB_DMP_exp_NRM_EW[7]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1418) );
AO22XLTS U5835 ( .A0(FPMULT_Op_MX[26]), .A1(n4370), .B0(n4369), .B1(
Data_1[26]), .Y(n1684) );
INVX2TS U5836 ( .A(n4702), .Y(n4371) );
AO22XLTS U5837 ( .A0(n4336), .A1(result_add_subt[4]), .B0(n4686), .B1(
FPSENCOS_d_ff_Xn[4]), .Y(n2060) );
AO22XLTS U5838 ( .A0(n4371), .A1(result_add_subt[8]), .B0(n4686), .B1(
FPSENCOS_d_ff_Xn[8]), .Y(n2048) );
AO22XLTS U5839 ( .A0(n4373), .A1(FPSENCOS_d_ff1_Z[12]), .B0(n4372), .B1(
Data_1[12]), .Y(n2100) );
AO22XLTS U5840 ( .A0(FPSENCOS_d_ff2_Y[16]), .A1(n4311), .B0(
FPSENCOS_d_ff_Yn[16]), .B1(n4374), .Y(n1875) );
AOI22X1TS U5841 ( .A0(FPMULT_Op_MY[3]), .A1(FPMULT_Op_MX[5]), .B0(n4955),
.B1(n5041), .Y(n4418) );
AO22XLTS U5842 ( .A0(n2267), .A1(n4418), .B0(n4533), .B1(n4376), .Y(
mult_x_254_n207) );
AOI22X1TS U5843 ( .A0(FPMULT_Op_MY[6]), .A1(n2309), .B0(n2278), .B1(n5042),
.Y(n4426) );
AOI22X1TS U5844 ( .A0(FPMULT_Op_MY[5]), .A1(n2309), .B0(n2278), .B1(n5038),
.Y(n4423) );
AO22XLTS U5845 ( .A0(n4529), .A1(n4426), .B0(n4427), .B1(n4423), .Y(
mult_x_254_n190) );
AO22XLTS U5846 ( .A0(n4414), .A1(n4378), .B0(n4412), .B1(n4377), .Y(
DP_OP_454J200_123_2743_n191) );
AOI22X1TS U5847 ( .A0(FPMULT_Op_MY[7]), .A1(n2290), .B0(n4955), .B1(n5040),
.Y(n4424) );
AO22XLTS U5848 ( .A0(n2267), .A1(n4424), .B0(n4533), .B1(n4379), .Y(
mult_x_254_n203) );
AOI22X1TS U5849 ( .A0(n2203), .A1(n2307), .B0(n2298), .B1(n5046), .Y(n4432)
);
AO22XLTS U5850 ( .A0(n2349), .A1(n4432), .B0(n4481), .B1(n4380), .Y(
mult_x_219_n201) );
AOI22X1TS U5851 ( .A0(n2236), .A1(n2279), .B0(n2324), .B1(n5047), .Y(n4514)
);
OAI22X1TS U5852 ( .A0(n4521), .A1(n4514), .B0(n4519), .B1(n4381), .Y(n4382)
);
AOI22X1TS U5853 ( .A0(FPMULT_Op_MY[10]), .A1(n2309), .B0(n2278), .B1(n5045),
.Y(n4522) );
AO22XLTS U5854 ( .A0(n4529), .A1(n4385), .B0(n4427), .B1(n4522), .Y(
mult_x_254_n185) );
AOI22X1TS U5855 ( .A0(FPMULT_Op_MY[19]), .A1(n2307), .B0(n2298), .B1(n5033),
.Y(n4435) );
AO22XLTS U5856 ( .A0(n2349), .A1(n4435), .B0(n4481), .B1(n4386), .Y(
mult_x_219_n197) );
AOI21X1TS U5857 ( .A0(n5045), .A1(n2367), .B0(n4549), .Y(n4388) );
AO22XLTS U5858 ( .A0(n2248), .A1(n4387), .B0(n4509), .B1(n4388), .Y(
mult_x_254_n157) );
AOI21X1TS U5859 ( .A0(n5035), .A1(n2366), .B0(mult_x_254_n149), .Y(n4431) );
AO22XLTS U5860 ( .A0(n2248), .A1(n4388), .B0(n2233), .B1(n4431), .Y(
mult_x_254_n158) );
OAI22X1TS U5861 ( .A0(n2401), .A1(n4470), .B0(n4389), .B1(n4468), .Y(n4390)
);
AO22XLTS U5862 ( .A0(n2248), .A1(n4392), .B0(n4509), .B1(n4391), .Y(
mult_x_254_n163) );
AOI22X1TS U5863 ( .A0(FPMULT_Op_MY[9]), .A1(n2277), .B0(n2309), .B1(n5035),
.Y(n4523) );
OAI22X1TS U5864 ( .A0(n4526), .A1(n4523), .B0(n4524), .B1(n4396), .Y(n4397)
);
CMPR32X2TS U5865 ( .A(n4507), .B(n4398), .C(n4397), .CO(mult_x_254_n71), .S(
mult_x_254_n72) );
AOI22X1TS U5866 ( .A0(FPMULT_Op_MY[21]), .A1(n4927), .B0(FPMULT_Op_MX[19]),
.B1(n5037), .Y(n4471) );
AOI22X1TS U5867 ( .A0(FPMULT_Op_MY[20]), .A1(n4927), .B0(FPMULT_Op_MX[19]),
.B1(n5031), .Y(n4404) );
OAI22X1TS U5868 ( .A0(n2363), .A1(n4471), .B0(n4475), .B1(n4404), .Y(n4399)
);
AOI22X1TS U5869 ( .A0(n2403), .A1(n4960), .B0(n2379), .B1(n2263), .Y(n4485)
);
AOI22X1TS U5870 ( .A0(n2262), .A1(n5037), .B0(FPMULT_Op_MY[21]), .B1(n2263),
.Y(n4487) );
OAI22X1TS U5871 ( .A0(n4491), .A1(n4485), .B0(n4486), .B1(n4487), .Y(n4400)
);
CMPR32X2TS U5872 ( .A(n2287), .B(n4401), .C(n4400), .CO(mult_x_219_n98), .S(
mult_x_219_n99) );
AOI22X1TS U5873 ( .A0(FPMULT_Op_MY[19]), .A1(n4927), .B0(FPMULT_Op_MX[19]),
.B1(n5033), .Y(n4473) );
OAI22X1TS U5874 ( .A0(n2363), .A1(n4404), .B0(n4475), .B1(n4473), .Y(n4405)
);
CMPR32X2TS U5875 ( .A(FPMULT_Op_MY[14]), .B(n4959), .C(n4405), .CO(
mult_x_219_n79), .S(mult_x_219_n80) );
AOI22X1TS U5876 ( .A0(n4575), .A1(n2327), .B0(n2325), .B1(n4574), .Y(n4409)
);
AO22XLTS U5877 ( .A0(n4414), .A1(n4409), .B0(n2385), .B1(n4408), .Y(
DP_OP_454J200_123_2743_n196) );
AO22XLTS U5878 ( .A0(n4414), .A1(n4410), .B0(n2385), .B1(n4409), .Y(
DP_OP_454J200_123_2743_n195) );
AO22XLTS U5879 ( .A0(n4414), .A1(n4413), .B0(n2385), .B1(n4411), .Y(
DP_OP_454J200_123_2743_n198) );
AO22XLTS U5880 ( .A0(n4417), .A1(n4416), .B0(n4415), .B1(n4595), .Y(
DP_OP_454J200_123_2743_n212) );
AOI22X1TS U5881 ( .A0(n2234), .A1(n2290), .B0(n4955), .B1(n5050), .Y(n4419)
);
AO22XLTS U5882 ( .A0(n2267), .A1(n4419), .B0(n4533), .B1(n4418), .Y(
mult_x_254_n206) );
AO22XLTS U5883 ( .A0(n2267), .A1(n4420), .B0(n4533), .B1(n4419), .Y(
mult_x_254_n205) );
AOI22X1TS U5884 ( .A0(n2234), .A1(n2309), .B0(n2278), .B1(n5050), .Y(n4422)
);
AO22XLTS U5885 ( .A0(n4529), .A1(n4422), .B0(n4427), .B1(n4421), .Y(
mult_x_254_n192) );
AO22XLTS U5886 ( .A0(n4529), .A1(n4423), .B0(n4427), .B1(n4422), .Y(
mult_x_254_n191) );
AO22XLTS U5887 ( .A0(n2266), .A1(n4425), .B0(n4533), .B1(n4424), .Y(
mult_x_254_n202) );
AO22XLTS U5888 ( .A0(n4529), .A1(n4428), .B0(n4427), .B1(n4426), .Y(
mult_x_254_n189) );
AOI21X1TS U5889 ( .A0(n5049), .A1(n2366), .B0(mult_x_254_n37), .Y(n4430) );
AO22XLTS U5890 ( .A0(n2248), .A1(n4430), .B0(n4509), .B1(n4429), .Y(
mult_x_254_n160) );
AO22XLTS U5891 ( .A0(n2248), .A1(n4431), .B0(n2233), .B1(n4430), .Y(
mult_x_254_n159) );
AOI22X1TS U5892 ( .A0(n2194), .A1(n2307), .B0(n2298), .B1(n5032), .Y(n4433)
);
AO22XLTS U5893 ( .A0(n2349), .A1(n4433), .B0(n4481), .B1(n4432), .Y(
mult_x_219_n200) );
AO22XLTS U5894 ( .A0(n2349), .A1(n4434), .B0(n4481), .B1(n4433), .Y(
mult_x_219_n199) );
AO22XLTS U5895 ( .A0(n2349), .A1(n4436), .B0(n4481), .B1(n4435), .Y(
mult_x_219_n196) );
OR2X1TS U5896 ( .A(FPMULT_exp_oper_result[8]), .B(
FPMULT_Exp_module_Overflow_flag_A), .Y(n4437) );
INVX2TS U5897 ( .A(operation[2]), .Y(n4438) );
AO22XLTS U5898 ( .A0(operation[2]), .A1(n4437), .B0(n4438), .B1(
overflow_flag_addsubt), .Y(overflow_flag) );
AO22XLTS U5899 ( .A0(operation[2]), .A1(underflow_flag_mult), .B0(n4438),
.B1(underflow_flag_addsubt), .Y(underflow_flag) );
OAI21XLTS U5900 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(n5028), .B0(n2301),
.Y(n1350) );
OA22X1TS U5901 ( .A0(FPADDSUB_exp_rslt_NRM2_EW1[6]), .A1(n4440), .B0(n4886),
.B1(result_add_subt[29]), .Y(n1467) );
OA22X1TS U5902 ( .A0(FPADDSUB_exp_rslt_NRM2_EW1[5]), .A1(n4440), .B0(n4886),
.B1(result_add_subt[28]), .Y(n1468) );
OA22X1TS U5903 ( .A0(FPADDSUB_exp_rslt_NRM2_EW1[4]), .A1(n4440), .B0(n4886),
.B1(result_add_subt[27]), .Y(n1469) );
OA22X1TS U5904 ( .A0(FPADDSUB_exp_rslt_NRM2_EW1[2]), .A1(n4440), .B0(n4886),
.B1(result_add_subt[25]), .Y(n1471) );
OA22X1TS U5905 ( .A0(FPADDSUB_exp_rslt_NRM2_EW1[1]), .A1(n4440), .B0(n4886),
.B1(result_add_subt[24]), .Y(n1472) );
OA22X1TS U5906 ( .A0(FPADDSUB_exp_rslt_NRM2_EW1[0]), .A1(n4440), .B0(n4886),
.B1(result_add_subt[23]), .Y(n1473) );
AOI21X1TS U5907 ( .A0(n4443), .A1(n4442), .B0(n4441), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N4) );
AOI21X1TS U5908 ( .A0(n4446), .A1(n4445), .B0(n4444), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N2) );
NOR2XLTS U5909 ( .A(n4962), .B(n2261), .Y(n4448) );
XNOR2X1TS U5910 ( .A(n4448), .B(n4447), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N1) );
AOI21X1TS U5911 ( .A0(n4451), .A1(n4450), .B0(mult_x_219_n119), .Y(
mult_x_219_n120) );
AO21XLTS U5912 ( .A0(n4452), .A1(n2288), .B0(mult_x_219_n177), .Y(n4453) );
AOI21X1TS U5913 ( .A0(n4454), .A1(n4453), .B0(mult_x_219_n129), .Y(
mult_x_219_n130) );
NAND2X1TS U5914 ( .A(n5037), .B(n2330), .Y(n4455) );
OAI22X1TS U5915 ( .A0(n2380), .A1(n4455), .B0(FPMULT_Op_MY[22]), .B1(n2283),
.Y(mult_x_219_n152) );
NAND2X1TS U5916 ( .A(n5031), .B(n2331), .Y(n4456) );
OAI22X1TS U5917 ( .A0(n2380), .A1(n4456), .B0(FPMULT_Op_MY[21]), .B1(n2283),
.Y(mult_x_219_n153) );
NAND2X1TS U5918 ( .A(n5033), .B(n2330), .Y(n4457) );
OAI22X1TS U5919 ( .A0(n2380), .A1(n4457), .B0(FPMULT_Op_MY[20]), .B1(n2283),
.Y(mult_x_219_n154) );
NAND2X1TS U5920 ( .A(n4961), .B(n2331), .Y(n4458) );
OAI22X1TS U5921 ( .A0(n2380), .A1(n4458), .B0(FPMULT_Op_MY[19]), .B1(n2284),
.Y(mult_x_219_n155) );
NAND2X1TS U5922 ( .A(n5039), .B(n2330), .Y(n4459) );
OAI22X1TS U5923 ( .A0(n2380), .A1(n4459), .B0(FPMULT_Op_MY[18]), .B1(n2284),
.Y(mult_x_219_n156) );
NAND2X1TS U5924 ( .A(n5032), .B(n2331), .Y(n4460) );
OAI22X1TS U5925 ( .A0(n2200), .A1(n4460), .B0(FPMULT_Op_MY[17]), .B1(n2284),
.Y(mult_x_219_n157) );
NAND2X1TS U5926 ( .A(n5046), .B(n2330), .Y(n4461) );
OAI22X1TS U5927 ( .A0(n2200), .A1(n4461), .B0(n2194), .B1(n2284), .Y(
mult_x_219_n158) );
NAND2X1TS U5928 ( .A(n5034), .B(n2331), .Y(n4462) );
OAI22X1TS U5929 ( .A0(n2200), .A1(n4462), .B0(n2235), .B1(n2284), .Y(
mult_x_219_n159) );
NAND2X1TS U5930 ( .A(n4959), .B(n2330), .Y(n4463) );
OAI22X1TS U5931 ( .A0(n2200), .A1(n4463), .B0(FPMULT_Op_MY[14]), .B1(n2284),
.Y(mult_x_219_n160) );
OAI22X1TS U5932 ( .A0(FPMULT_Op_MY[13]), .A1(n2283), .B0(n2288), .B1(n4464),
.Y(mult_x_219_n161) );
AOI22X1TS U5933 ( .A0(FPMULT_Op_MY[20]), .A1(n2330), .B0(n2402), .B1(n5031),
.Y(n4466) );
OAI22X1TS U5934 ( .A0(n4470), .A1(n4465), .B0(n4468), .B1(n4466), .Y(
mult_x_219_n167) );
AOI22X1TS U5935 ( .A0(FPMULT_Op_MY[19]), .A1(n4931), .B0(n2402), .B1(n5033),
.Y(n4469) );
OAI22X1TS U5936 ( .A0(n4470), .A1(n4466), .B0(n4468), .B1(n4469), .Y(
mult_x_219_n168) );
OAI22X1TS U5937 ( .A0(n4470), .A1(n4469), .B0(n4468), .B1(n4467), .Y(
mult_x_219_n169) );
AOI22X1TS U5938 ( .A0(FPMULT_Op_MY[22]), .A1(n2299), .B0(n2398), .B1(n4960),
.Y(n4472) );
OAI22X1TS U5939 ( .A0(FPMULT_Op_MX[19]), .A1(n2363), .B0(n4472), .B1(n4475),
.Y(mult_x_219_n179) );
OAI22X1TS U5940 ( .A0(n2363), .A1(n4472), .B0(n4471), .B1(n4475), .Y(
mult_x_219_n180) );
AOI22X1TS U5941 ( .A0(FPMULT_Op_MY[18]), .A1(n4927), .B0(n2398), .B1(n4961),
.Y(n4474) );
OAI22X1TS U5942 ( .A0(n2363), .A1(n4473), .B0(n4475), .B1(n4474), .Y(
mult_x_219_n183) );
AOI22X1TS U5943 ( .A0(FPMULT_Op_MY[17]), .A1(n2299), .B0(n2398), .B1(n5039),
.Y(n4476) );
OAI22X1TS U5944 ( .A0(n2364), .A1(n4474), .B0(n4475), .B1(n4476), .Y(
mult_x_219_n184) );
AOI22X1TS U5945 ( .A0(n2194), .A1(n2299), .B0(n2398), .B1(n5032), .Y(n4479)
);
OAI22X1TS U5946 ( .A0(n2364), .A1(n4476), .B0(n4475), .B1(n4479), .Y(
mult_x_219_n185) );
AOI22X1TS U5947 ( .A0(n2379), .A1(n2297), .B0(n2307), .B1(n4960), .Y(n4483)
);
INVX2TS U5948 ( .A(n4481), .Y(n4480) );
OAI22X1TS U5949 ( .A0(n2307), .A1(n4484), .B0(n4483), .B1(n4480), .Y(
mult_x_219_n193) );
OAI22X1TS U5950 ( .A0(n2403), .A1(n4491), .B0(n4485), .B1(n4486), .Y(
mult_x_219_n207) );
AOI22X1TS U5951 ( .A0(n2403), .A1(n5031), .B0(FPMULT_Op_MY[20]), .B1(n2263),
.Y(n4490) );
OAI22X1TS U5952 ( .A0(n4491), .A1(n4487), .B0(n4486), .B1(n4490), .Y(
mult_x_219_n209) );
AOI22X1TS U5953 ( .A0(mult_x_219_n31), .A1(n2283), .B0(n2379), .B1(n4492),
.Y(n4496) );
OAI211XLTS U5954 ( .A0(n2284), .A1(n2379), .B0(n4495), .C0(n4496), .Y(n4494)
);
OAI21XLTS U5955 ( .A0(n4496), .A1(n4495), .B0(n4494), .Y(n4501) );
CMPR32X2TS U5956 ( .A(n4499), .B(n4498), .C(n4497), .CO(n4500), .S(n2829) );
XNOR2X1TS U5957 ( .A(n4501), .B(n4500), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_left_N23) );
NAND3BXLTS U5958 ( .AN(mult_x_254_n168), .B(n2365), .C(n4555), .Y(n4502) );
AOI21X1TS U5959 ( .A0(n4503), .A1(n4502), .B0(mult_x_254_n106), .Y(
mult_x_254_n107) );
AOI21X1TS U5960 ( .A0(n4506), .A1(n4505), .B0(mult_x_254_n119), .Y(
mult_x_254_n120) );
AO21XLTS U5961 ( .A0(n5043), .A1(n2366), .B0(n4507), .Y(n4510) );
OAI22X1TS U5962 ( .A0(n4511), .A1(n4508), .B0(n2232), .B1(n4510), .Y(
mult_x_254_n166) );
OAI21XLTS U5963 ( .A0(n2259), .A1(n2365), .B0(n2233), .Y(n4512) );
OAI22X1TS U5964 ( .A0(n4513), .A1(n4512), .B0(n4511), .B1(n4510), .Y(
mult_x_254_n167) );
OAI22X1TS U5965 ( .A0(n4515), .A1(mult_x_254_n169), .B0(n4519), .B1(n4514),
.Y(mult_x_254_n170) );
AOI22X1TS U5966 ( .A0(n2205), .A1(n2279), .B0(n2324), .B1(n5049), .Y(n4517)
);
OAI22X1TS U5967 ( .A0(n4521), .A1(n4516), .B0(n4519), .B1(n4517), .Y(
mult_x_254_n173) );
AOI22X1TS U5968 ( .A0(FPMULT_Op_MY[7]), .A1(n2279), .B0(n2324), .B1(n5040),
.Y(n4520) );
OAI22X1TS U5969 ( .A0(n4521), .A1(n4517), .B0(n4519), .B1(n4520), .Y(
mult_x_254_n174) );
OAI22X1TS U5970 ( .A0(n4521), .A1(n4520), .B0(n4519), .B1(n4518), .Y(
mult_x_254_n175) );
AOI32X1TS U5971 ( .A0(FPMULT_Op_MX[6]), .A1(n2258), .A2(n2277), .B0(n4525),
.B1(n2270), .Y(n4527) );
AOI22X1TS U5972 ( .A0(n4529), .A1(n4528), .B0(n4527), .B1(n4526), .Y(
mult_x_254_n195) );
AOI22X1TS U5973 ( .A0(n2201), .A1(n2291), .B0(n2290), .B1(n5047), .Y(n4532)
);
INVX2TS U5974 ( .A(n4533), .Y(n4531) );
OAI22X1TS U5975 ( .A0(n4530), .A1(mult_x_254_n197), .B0(n4532), .B1(n4531),
.Y(mult_x_254_n198) );
AOI22X1TS U5976 ( .A0(FPMULT_Op_MY[10]), .A1(n2291), .B0(n2290), .B1(n5045),
.Y(n4535) );
OAI22X1TS U5977 ( .A0(n4536), .A1(n4532), .B0(n4531), .B1(n4535), .Y(
mult_x_254_n199) );
AOI22X1TS U5978 ( .A0(n2315), .A1(n5047), .B0(n2201), .B1(n2273), .Y(n4539)
);
OAI22X1TS U5979 ( .A0(n4537), .A1(mult_x_254_n211), .B0(n4539), .B1(n4541),
.Y(mult_x_254_n212) );
OAI22X1TS U5980 ( .A0(n4543), .A1(n4539), .B0(n4538), .B1(n4541), .Y(
mult_x_254_n213) );
OAI22X1TS U5981 ( .A0(n4543), .A1(n4542), .B0(n4541), .B1(n4540), .Y(
mult_x_254_n215) );
NOR2X1TS U5982 ( .A(n2319), .B(n5042), .Y(n4545) );
OAI22X1TS U5983 ( .A0(n5038), .A1(n2237), .B0(n4545), .B1(n2399), .Y(n4544)
);
AOI21X1TS U5984 ( .A0(n4545), .A1(n2400), .B0(n4544), .Y(mult_x_254_n232) );
NOR2XLTS U5985 ( .A(n2319), .B(n2270), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N0) );
CMPR32X2TS U5986 ( .A(n4548), .B(n4547), .C(n4546), .CO(n4559), .S(n2766) );
CMPR32X2TS U5987 ( .A(n4551), .B(n4550), .C(n4549), .CO(n4557), .S(n4547) );
AOI21X1TS U5988 ( .A0(n2201), .A1(FPMULT_Op_MY[10]), .B0(n4552), .Y(n4554)
);
NOR2XLTS U5989 ( .A(n4555), .B(n4554), .Y(n4553) );
AOI211XLTS U5990 ( .A0(n4555), .A1(n4554), .B0(n2366), .C0(n4553), .Y(n4556)
);
XOR2XLTS U5991 ( .A(n4557), .B(n4556), .Y(n4558) );
XNOR2X1TS U5992 ( .A(n4559), .B(n4558), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_right_N23) );
NOR2BX1TS U5993 ( .AN(n4560), .B(DP_OP_454J200_123_2743_n214), .Y(
DP_OP_454J200_123_2743_n156) );
AOI22X1TS U5994 ( .A0(n2228), .A1(n4620), .B0(n4617), .B1(n2302), .Y(
DP_OP_454J200_123_2743_n162) );
AOI22X1TS U5995 ( .A0(n4641), .A1(n4623), .B0(n4620), .B1(n2302), .Y(
DP_OP_454J200_123_2743_n163) );
AOI22X1TS U5996 ( .A0(n2228), .A1(n4565), .B0(n4623), .B1(n2302), .Y(
DP_OP_454J200_123_2743_n164) );
AOI22X1TS U5997 ( .A0(n4641), .A1(n4568), .B0(n4565), .B1(n2302), .Y(
DP_OP_454J200_123_2743_n165) );
AOI22X1TS U5998 ( .A0(n4641), .A1(n4571), .B0(n4568), .B1(n2303), .Y(
DP_OP_454J200_123_2743_n166) );
AOI22X1TS U5999 ( .A0(n4641), .A1(n4574), .B0(n4571), .B1(n2303), .Y(
DP_OP_454J200_123_2743_n167) );
AOI22X1TS U6000 ( .A0(n2228), .A1(n4577), .B0(n4574), .B1(n2303), .Y(
DP_OP_454J200_123_2743_n168) );
AOI22X1TS U6001 ( .A0(n4641), .A1(n4580), .B0(n4577), .B1(n2303), .Y(
DP_OP_454J200_123_2743_n169) );
AOI22X1TS U6002 ( .A0(n2228), .A1(n4583), .B0(n4580), .B1(n2303), .Y(
DP_OP_454J200_123_2743_n170) );
AOI22X1TS U6003 ( .A0(n4641), .A1(n2256), .B0(n4583), .B1(n2303), .Y(
DP_OP_454J200_123_2743_n171) );
AOI22X1TS U6004 ( .A0(n4640), .A1(n2382), .B0(n2294), .B1(n4635), .Y(n4562)
);
OAI22X1TS U6005 ( .A0(n4590), .A1(n4562), .B0(n2281), .B1(n4561), .Y(
DP_OP_454J200_123_2743_n175) );
AOI22X1TS U6006 ( .A0(n4616), .A1(n2381), .B0(n2382), .B1(n4617), .Y(n4563)
);
OAI22X1TS U6007 ( .A0(n4590), .A1(n4563), .B0(n4562), .B1(n2282), .Y(
DP_OP_454J200_123_2743_n176) );
AOI22X1TS U6008 ( .A0(n2381), .A1(n4619), .B0(n4620), .B1(n2383), .Y(n4564)
);
OAI22X1TS U6009 ( .A0(n4590), .A1(n4564), .B0(n4563), .B1(n2282), .Y(
DP_OP_454J200_123_2743_n177) );
AOI22X1TS U6010 ( .A0(n4622), .A1(n2381), .B0(n2382), .B1(n4623), .Y(n4567)
);
OAI22X1TS U6011 ( .A0(n2268), .A1(n4567), .B0(n4564), .B1(n2282), .Y(
DP_OP_454J200_123_2743_n178) );
AOI22X1TS U6012 ( .A0(n4566), .A1(n2381), .B0(n2382), .B1(n4565), .Y(n4570)
);
OAI22X1TS U6013 ( .A0(n4590), .A1(n4570), .B0(n4567), .B1(n2282), .Y(
DP_OP_454J200_123_2743_n179) );
AOI22X1TS U6014 ( .A0(n4569), .A1(n2294), .B0(n2382), .B1(n4568), .Y(n4573)
);
OAI22X1TS U6015 ( .A0(n4590), .A1(n4573), .B0(n4570), .B1(n2281), .Y(
DP_OP_454J200_123_2743_n180) );
AOI22X1TS U6016 ( .A0(n4572), .A1(n2381), .B0(n2382), .B1(n4571), .Y(n4576)
);
OAI22X1TS U6017 ( .A0(n2268), .A1(n4576), .B0(n4573), .B1(n2281), .Y(
DP_OP_454J200_123_2743_n181) );
AOI22X1TS U6018 ( .A0(n4575), .A1(n2294), .B0(n2383), .B1(n4574), .Y(n4579)
);
OAI22X1TS U6019 ( .A0(n2268), .A1(n4579), .B0(n4576), .B1(n2281), .Y(
DP_OP_454J200_123_2743_n182) );
AOI22X1TS U6020 ( .A0(n4578), .A1(n2294), .B0(n2383), .B1(n4577), .Y(n4582)
);
OAI22X1TS U6021 ( .A0(n2268), .A1(n4582), .B0(n4579), .B1(n2281), .Y(
DP_OP_454J200_123_2743_n183) );
AOI22X1TS U6022 ( .A0(n4581), .A1(n2294), .B0(n2383), .B1(n4580), .Y(n4585)
);
OAI22X1TS U6023 ( .A0(n2268), .A1(n4585), .B0(n4582), .B1(n2281), .Y(
DP_OP_454J200_123_2743_n184) );
AOI22X1TS U6024 ( .A0(n4584), .A1(n2294), .B0(n2383), .B1(n4583), .Y(n4588)
);
OAI22X1TS U6025 ( .A0(n2268), .A1(n4588), .B0(n4585), .B1(n2281), .Y(
DP_OP_454J200_123_2743_n185) );
AOI22X1TS U6026 ( .A0(n4587), .A1(n2294), .B0(n2383), .B1(n2257), .Y(n4589)
);
OAI22X1TS U6027 ( .A0(n2268), .A1(n4589), .B0(n4588), .B1(n2282), .Y(
DP_OP_454J200_123_2743_n186) );
AOI22X1TS U6028 ( .A0(n2351), .A1(n4640), .B0(n4635), .B1(n2285), .Y(n4593)
);
OAI22X1TS U6029 ( .A0(n4594), .A1(n4593), .B0(n4591), .B1(n4598), .Y(
DP_OP_454J200_123_2743_n202) );
AOI22X1TS U6030 ( .A0(n2351), .A1(n4617), .B0(n4616), .B1(n2285), .Y(n4597)
);
OAI22X1TS U6031 ( .A0(n4594), .A1(n4597), .B0(n4593), .B1(n4598), .Y(
DP_OP_454J200_123_2743_n203) );
AOI22X1TS U6032 ( .A0(n2356), .A1(n2246), .B0(n4633), .B1(n2276), .Y(n4600)
);
OAI22X1TS U6033 ( .A0(n4599), .A1(DP_OP_454J200_123_2743_n215), .B0(n4600),
.B1(n4608), .Y(DP_OP_454J200_123_2743_n216) );
AOI22X1TS U6034 ( .A0(n2356), .A1(n4640), .B0(n4635), .B1(n2276), .Y(n4602)
);
OAI22X1TS U6035 ( .A0(n4600), .A1(n4611), .B0(n4602), .B1(n4608), .Y(
DP_OP_454J200_123_2743_n217) );
AOI22X1TS U6036 ( .A0(n2357), .A1(n4617), .B0(n4616), .B1(n2276), .Y(n4604)
);
OAI22X1TS U6037 ( .A0(n4602), .A1(n4611), .B0(n4608), .B1(n4604), .Y(
DP_OP_454J200_123_2743_n218) );
OAI22X1TS U6038 ( .A0(n4611), .A1(n4610), .B0(n4609), .B1(n4608), .Y(
DP_OP_454J200_123_2743_n227) );
AOI22X1TS U6039 ( .A0(n2339), .A1(n2246), .B0(n4633), .B1(n2317), .Y(n4615)
);
NAND3XLTS U6040 ( .A(n4612), .B(n2240), .C(n2317), .Y(n4614) );
AOI22X1TS U6041 ( .A0(n4615), .A1(n4632), .B0(n4614), .B1(n4613), .Y(
DP_OP_454J200_123_2743_n231) );
AOI22X1TS U6042 ( .A0(n2339), .A1(n4640), .B0(n4635), .B1(n2317), .Y(n4618)
);
OAI22X1TS U6043 ( .A0(n4626), .A1(n4618), .B0(n4615), .B1(n4632), .Y(
DP_OP_454J200_123_2743_n232) );
AOI22X1TS U6044 ( .A0(n2340), .A1(n4617), .B0(n4616), .B1(n2317), .Y(n4621)
);
OAI22X1TS U6045 ( .A0(n4626), .A1(n4621), .B0(n4618), .B1(n4632), .Y(
DP_OP_454J200_123_2743_n233) );
AOI22X1TS U6046 ( .A0(n2340), .A1(n4620), .B0(n4619), .B1(n2317), .Y(n4625)
);
OAI22X1TS U6047 ( .A0(n4626), .A1(n4625), .B0(n4632), .B1(n4621), .Y(
DP_OP_454J200_123_2743_n234) );
AOI22X1TS U6048 ( .A0(n2340), .A1(n4623), .B0(n4622), .B1(n2317), .Y(n4628)
);
OAI22X1TS U6049 ( .A0(n4626), .A1(n4628), .B0(n4632), .B1(n4625), .Y(
DP_OP_454J200_123_2743_n235) );
OAI2BB2XLTS U6050 ( .B0(n4632), .B1(n4628), .A0N(n4627), .A1N(n4629), .Y(
DP_OP_454J200_123_2743_n236) );
AOI21X1TS U6051 ( .A0(n4636), .A1(n4633), .B0(n2239), .Y(
DP_OP_454J200_123_2743_n245) );
AOI22X1TS U6052 ( .A0(n2240), .A1(n2246), .B0(n4633), .B1(n2239), .Y(n4637)
);
OAI22X1TS U6053 ( .A0(n4637), .A1(n4636), .B0(n2243), .B1(n4635), .Y(
DP_OP_454J200_123_2743_n246) );
CMPR32X2TS U6054 ( .A(DP_OP_454J200_123_2743_n36), .B(n4639), .C(n4638),
.CO(n4649), .S(FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N23) );
AOI22X1TS U6055 ( .A0(n4641), .A1(n4640), .B0(n2246), .B1(n2303), .Y(n4645)
);
CMPR32X2TS U6056 ( .A(DP_OP_454J200_123_2743_n35), .B(n4643), .C(n4642),
.CO(n4647), .S(n4639) );
CMPR32X2TS U6057 ( .A(n4646), .B(n4645), .C(n4644), .CO(n4653), .S(n4648) );
CMPR32X2TS U6058 ( .A(n4649), .B(n4648), .C(n4647), .CO(n4651), .S(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N24) );
OAI21XLTS U6059 ( .A0(n2246), .A1(n2303), .B0(n4651), .Y(n4650) );
OAI31X1TS U6060 ( .A0(n2245), .A1(n4651), .A2(n2302), .B0(n4650), .Y(n4652)
);
XNOR2X1TS U6061 ( .A(n4653), .B(n4652), .Y(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_middle_N25) );
NOR4BX1TS U6062 ( .AN(operation_reg[1]), .B(dataB[28]), .C(operation_reg[0]),
.D(dataB[23]), .Y(n4658) );
NOR4X1TS U6063 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[26]), .D(dataB[25]),
.Y(n4657) );
NAND4XLTS U6064 ( .A(dataA[30]), .B(dataA[27]), .C(dataA[28]), .D(dataA[26]),
.Y(n4655) );
NAND4XLTS U6065 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(dataA[24]),
.Y(n4654) );
OR3X1TS U6066 ( .A(n5466), .B(n4655), .C(n4654), .Y(n4659) );
NOR3XLTS U6067 ( .A(dataB[29]), .B(dataB[31]), .C(n4659), .Y(n4656) );
AOI31XLTS U6068 ( .A0(n4658), .A1(n4657), .A2(n4656), .B0(dataB[27]), .Y(
n4669) );
NOR4X1TS U6069 ( .A(dataA[30]), .B(dataA[27]), .C(dataA[28]), .D(dataA[26]),
.Y(n4662) );
NOR4X1TS U6070 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(dataA[24]),
.Y(n4661) );
NOR4BX1TS U6071 ( .AN(operation_reg[1]), .B(operation_reg[0]), .C(dataA[31]),
.D(n5466), .Y(n4660) );
NOR2X1TS U6072 ( .A(operation_reg[1]), .B(n4659), .Y(n4667) );
NAND3XLTS U6073 ( .A(dataB[28]), .B(dataB[23]), .C(dataB[29]), .Y(n4664) );
NAND4XLTS U6074 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[26]), .D(dataB[25]),
.Y(n4663) );
OAI31X1TS U6075 ( .A0(n4665), .A1(n4664), .A2(n4663), .B0(dataB[27]), .Y(
n4666) );
NAND4XLTS U6076 ( .A(n5469), .B(n5468), .C(n5467), .D(n4666), .Y(n4668) );
OAI2BB2XLTS U6077 ( .B0(n4669), .B1(n4668), .A0N(n4667), .A1N(
operation_reg[0]), .Y(NaN_reg) );
OAI22X1TS U6078 ( .A0(n4673), .A1(n4672), .B0(n4671), .B1(n4670), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]) );
AOI22X1TS U6079 ( .A0(n4678), .A1(n4889), .B0(n4675), .B1(n4676), .Y(n2147)
);
AOI22X1TS U6080 ( .A0(n4678), .A1(n4675), .B0(n4674), .B1(n4676), .Y(n2146)
);
AOI22X1TS U6081 ( .A0(n4678), .A1(n4867), .B0(n4958), .B1(n4676), .Y(n2143)
);
AOI22X1TS U6082 ( .A0(n4678), .A1(n3972), .B0(n5250), .B1(n4676), .Y(n2142)
);
INVX2TS U6083 ( .A(n4680), .Y(n4681) );
AOI21X1TS U6084 ( .A0(n2238), .A1(n4679), .B0(n4681), .Y(n2140) );
AOI22X1TS U6085 ( .A0(n4681), .A1(FPSENCOS_cont_iter_out[2]), .B0(n4963),
.B1(n4680), .Y(n2139) );
AOI21X1TS U6086 ( .A0(n2360), .A1(n4937), .B0(n4682), .Y(n2137) );
OAI2BB2XLTS U6087 ( .B0(n4684), .B1(n5102), .A0N(n4700), .A1N(
FPSENCOS_d_ff_Yn[0]), .Y(n2073) );
AOI22X1TS U6088 ( .A0(n4703), .A1(n5069), .B0(n4986), .B1(n4686), .Y(n2069)
);
OAI2BB2XLTS U6089 ( .B0(n4684), .B1(n5067), .A0N(n4700), .A1N(
FPSENCOS_d_ff_Yn[2]), .Y(n2067) );
AOI22X1TS U6090 ( .A0(n4703), .A1(n5067), .B0(n4987), .B1(n4702), .Y(n2066)
);
AOI22X1TS U6091 ( .A0(n4703), .A1(n5066), .B0(n4988), .B1(n4686), .Y(n2063)
);
OAI2BB2XLTS U6092 ( .B0(n4685), .B1(n5099), .A0N(n4700), .A1N(
FPSENCOS_d_ff_Yn[4]), .Y(n2061) );
AOI22X1TS U6093 ( .A0(n4703), .A1(n5070), .B0(n4989), .B1(n4686), .Y(n2057)
);
AOI22X1TS U6094 ( .A0(n4703), .A1(n5060), .B0(n4990), .B1(n4702), .Y(n2054)
);
CLKBUFX3TS U6095 ( .A(n4702), .Y(n4699) );
AOI22X1TS U6096 ( .A0(n4703), .A1(n5068), .B0(n4991), .B1(n4699), .Y(n2051)
);
AOI22X1TS U6097 ( .A0(n4703), .A1(n5064), .B0(n4992), .B1(n4699), .Y(n2042)
);
INVX2TS U6098 ( .A(n4702), .Y(n4697) );
AOI22X1TS U6099 ( .A0(n4697), .A1(n5065), .B0(n4993), .B1(n4699), .Y(n2036)
);
AOI22X1TS U6100 ( .A0(n4336), .A1(n5061), .B0(n4994), .B1(n4699), .Y(n2033)
);
AOI22X1TS U6101 ( .A0(n4371), .A1(n5063), .B0(n4995), .B1(n4699), .Y(n2030)
);
AOI22X1TS U6102 ( .A0(n4697), .A1(n5062), .B0(n4996), .B1(n4699), .Y(n2024)
);
AOI22X1TS U6103 ( .A0(n4336), .A1(n5059), .B0(n4997), .B1(n4699), .Y(n2021)
);
AOI22X1TS U6104 ( .A0(n4371), .A1(n5057), .B0(n4998), .B1(n4696), .Y(n2015)
);
AOI22X1TS U6105 ( .A0(n4697), .A1(n5058), .B0(n4999), .B1(n4696), .Y(n2012)
);
CLKBUFX3TS U6106 ( .A(n4687), .Y(n4690) );
AOI22X1TS U6107 ( .A0(n4690), .A1(n4986), .B0(n5150), .B1(n4280), .Y(n2003)
);
AOI22X1TS U6108 ( .A0(n4690), .A1(n4987), .B0(n5151), .B1(n4688), .Y(n2001)
);
AOI22X1TS U6109 ( .A0(n4690), .A1(n4988), .B0(n5152), .B1(n4280), .Y(n1999)
);
AOI22X1TS U6110 ( .A0(n4690), .A1(n4989), .B0(n5153), .B1(n4215), .Y(n1995)
);
AOI22X1TS U6111 ( .A0(n4690), .A1(n4990), .B0(n5154), .B1(n3495), .Y(n1993)
);
AOI22X1TS U6112 ( .A0(n4690), .A1(n4991), .B0(n5155), .B1(n4688), .Y(n1991)
);
AOI22X1TS U6113 ( .A0(n4690), .A1(n4992), .B0(n5156), .B1(n3495), .Y(n1985)
);
AOI22X1TS U6114 ( .A0(n4690), .A1(n4993), .B0(n5157), .B1(n4215), .Y(n1981)
);
AOI22X1TS U6115 ( .A0(n4690), .A1(n4994), .B0(n5158), .B1(n4311), .Y(n1979)
);
CLKBUFX3TS U6116 ( .A(n4687), .Y(n4692) );
AOI22X1TS U6117 ( .A0(n4692), .A1(n4995), .B0(n5159), .B1(n4691), .Y(n1977)
);
AOI22X1TS U6118 ( .A0(n4692), .A1(n4996), .B0(n5160), .B1(n2479), .Y(n1973)
);
AOI22X1TS U6119 ( .A0(n4692), .A1(n4997), .B0(n5161), .B1(n4123), .Y(n1971)
);
AOI22X1TS U6120 ( .A0(n4690), .A1(n4998), .B0(n5162), .B1(n2386), .Y(n1967)
);
AOI22X1TS U6121 ( .A0(n4692), .A1(n4999), .B0(n5163), .B1(n4375), .Y(n1965)
);
AOI22X1TS U6122 ( .A0(n4692), .A1(n5000), .B0(n5164), .B1(n4691), .Y(n1958)
);
AOI22X1TS U6123 ( .A0(n4692), .A1(n5001), .B0(n5165), .B1(n4311), .Y(n1957)
);
AOI22X1TS U6124 ( .A0(n4692), .A1(n5002), .B0(n5166), .B1(n4123), .Y(n1956)
);
AOI22X1TS U6125 ( .A0(n4692), .A1(n5003), .B0(n5167), .B1(n2386), .Y(n1955)
);
AOI22X1TS U6126 ( .A0(n4692), .A1(n5129), .B0(n4967), .B1(n4123), .Y(n1954)
);
AOI22X1TS U6127 ( .A0(n4692), .A1(n5004), .B0(n5168), .B1(n4375), .Y(n1953)
);
OAI22X1TS U6128 ( .A0(n4695), .A1(n4694), .B0(n4693), .B1(n4971), .Y(n1812)
);
OAI2BB2XLTS U6129 ( .B0(n4701), .B1(n5194), .A0N(n4700), .A1N(
FPSENCOS_d_ff_Yn[23]), .Y(n1785) );
AOI22X1TS U6130 ( .A0(n4336), .A1(n5091), .B0(n5000), .B1(n4696), .Y(n1781)
);
AOI22X1TS U6131 ( .A0(n4371), .A1(n5092), .B0(n5001), .B1(n4699), .Y(n1778)
);
AOI22X1TS U6132 ( .A0(n4697), .A1(n5071), .B0(n5002), .B1(n4699), .Y(n1775)
);
AOI22X1TS U6133 ( .A0(n4703), .A1(n5093), .B0(n5003), .B1(n4698), .Y(n1772)
);
AOI22X1TS U6134 ( .A0(n4703), .A1(n4976), .B0(n5129), .B1(n4699), .Y(n1769)
);
OAI2BB2XLTS U6135 ( .B0(n4701), .B1(n5094), .A0N(n4700), .A1N(
FPSENCOS_d_ff_Yn[29]), .Y(n1767) );
AOI22X1TS U6136 ( .A0(n4703), .A1(n5094), .B0(n5004), .B1(n4702), .Y(n1766)
);
AOI22X1TS U6137 ( .A0(n2274), .A1(n5011), .B0(n4704), .B1(n5199), .Y(n4708)
);
AOI21X1TS U6138 ( .A0(begin_operation), .A1(n4705), .B0(n5357), .Y(n4706) );
AOI21X1TS U6139 ( .A0(n4708), .A1(n4707), .B0(n4706), .Y(n1692) );
OA22X1TS U6140 ( .A0(n2380), .A1(n4710), .B0(n4716), .B1(Data_1[22]), .Y(
n1680) );
OA22X1TS U6141 ( .A0(n2402), .A1(n4709), .B0(n4712), .B1(Data_1[21]), .Y(
n1679) );
OA22X1TS U6142 ( .A0(FPMULT_Op_MX[20]), .A1(n4710), .B0(n4712), .B1(
Data_1[20]), .Y(n1678) );
CLKBUFX3TS U6143 ( .A(n4711), .Y(n4713) );
OA22X1TS U6144 ( .A0(n2398), .A1(n4713), .B0(n4712), .B1(Data_1[19]), .Y(
n1677) );
OA22X1TS U6145 ( .A0(FPMULT_Op_MX[18]), .A1(n4713), .B0(n4712), .B1(
Data_1[18]), .Y(n1676) );
OA22X1TS U6146 ( .A0(n2307), .A1(n4713), .B0(n4712), .B1(Data_1[17]), .Y(
n1675) );
OA22X1TS U6147 ( .A0(FPMULT_Op_MX[16]), .A1(n4713), .B0(n4712), .B1(
Data_1[16]), .Y(n1674) );
INVX2TS U6148 ( .A(n4717), .Y(n4714) );
OA22X1TS U6149 ( .A0(n2403), .A1(n4713), .B0(n4714), .B1(Data_1[15]), .Y(
n1673) );
OA22X1TS U6150 ( .A0(FPMULT_Op_MX[14]), .A1(n4713), .B0(n4712), .B1(
Data_1[14]), .Y(n1672) );
OA22X1TS U6151 ( .A0(FPMULT_Op_MX[13]), .A1(n4713), .B0(n4712), .B1(
Data_1[13]), .Y(n1671) );
OA22X1TS U6152 ( .A0(FPMULT_Op_MX[12]), .A1(n4713), .B0(n4712), .B1(
Data_1[12]), .Y(n1670) );
OA22X1TS U6153 ( .A0(n2365), .A1(n4713), .B0(n4714), .B1(Data_1[11]), .Y(
n1669) );
OA22X1TS U6154 ( .A0(FPMULT_Op_MX[10]), .A1(n4713), .B0(n4714), .B1(
Data_1[10]), .Y(n1668) );
OA22X1TS U6155 ( .A0(n2324), .A1(n4715), .B0(n4714), .B1(Data_1[9]), .Y(
n1667) );
OA22X1TS U6156 ( .A0(FPMULT_Op_MX[8]), .A1(n4715), .B0(n4714), .B1(Data_1[8]), .Y(n1666) );
OA22X1TS U6157 ( .A0(n2309), .A1(n4715), .B0(n4714), .B1(Data_1[7]), .Y(
n1665) );
OA22X1TS U6158 ( .A0(FPMULT_Op_MX[6]), .A1(n4715), .B0(n4714), .B1(Data_1[6]), .Y(n1664) );
OA22X1TS U6159 ( .A0(n2290), .A1(n4715), .B0(n4714), .B1(Data_1[5]), .Y(
n1663) );
OA22X1TS U6160 ( .A0(FPMULT_Op_MX[4]), .A1(n4715), .B0(n4714), .B1(Data_1[4]), .Y(n1662) );
OA22X1TS U6161 ( .A0(n2315), .A1(n4715), .B0(n4714), .B1(Data_1[3]), .Y(
n1661) );
OA22X1TS U6162 ( .A0(FPMULT_Op_MX[2]), .A1(n4715), .B0(n4716), .B1(Data_1[2]), .Y(n1660) );
OA22X1TS U6163 ( .A0(n2400), .A1(n4715), .B0(n4716), .B1(Data_1[1]), .Y(
n1659) );
OA22X1TS U6164 ( .A0(n2237), .A1(n4717), .B0(n4716), .B1(Data_1[0]), .Y(
n1658) );
AOI21X1TS U6165 ( .A0(FPMULT_Sgf_normalized_result[0]), .A1(
FPMULT_Sgf_normalized_result[1]), .B0(n4718), .Y(n4719) );
AOI22X1TS U6166 ( .A0(n4742), .A1(n4719), .B0(n5104), .B1(n4722), .Y(n1619)
);
OAI21XLTS U6167 ( .A0(FPMULT_Sgf_normalized_result[3]), .A1(n4721), .B0(
n4720), .Y(n4723) );
AOI22X1TS U6168 ( .A0(n4742), .A1(n4723), .B0(n5169), .B1(n4722), .Y(n1617)
);
OAI2BB1X1TS U6169 ( .A0N(FPMULT_Add_result[5]), .A1N(n2442), .B0(n4726), .Y(
n1615) );
OAI2BB1X1TS U6170 ( .A0N(FPMULT_Add_result[7]), .A1N(n4737), .B0(n4729), .Y(
n1613) );
OAI2BB1X1TS U6171 ( .A0N(FPMULT_Add_result[11]), .A1N(n2442), .B0(n4732),
.Y(n1609) );
OAI2BB1X1TS U6172 ( .A0N(FPMULT_Add_result[15]), .A1N(n4737), .B0(n4736),
.Y(n1605) );
NOR2XLTS U6173 ( .A(FPMULT_Sgf_normalized_result[21]), .B(n4738), .Y(n4741)
);
NAND2X1TS U6174 ( .A(n4742), .B(n4739), .Y(n4740) );
OAI22X1TS U6175 ( .A0(n4742), .A1(n5089), .B0(n4741), .B1(n4740), .Y(n1599)
);
OA22X1TS U6176 ( .A0(n4744), .A1(mult_result[25]), .B0(
FPMULT_exp_oper_result[2]), .B1(n4743), .Y(n1582) );
OA22X1TS U6177 ( .A0(n4744), .A1(mult_result[27]), .B0(
FPMULT_exp_oper_result[4]), .B1(n4743), .Y(n1580) );
OA22X1TS U6178 ( .A0(n4744), .A1(mult_result[28]), .B0(
FPMULT_exp_oper_result[5]), .B1(n4743), .Y(n1579) );
OA22X1TS U6179 ( .A0(n4744), .A1(mult_result[29]), .B0(
FPMULT_exp_oper_result[6]), .B1(n4743), .Y(n1578) );
OA22X1TS U6180 ( .A0(n4744), .A1(mult_result[30]), .B0(
FPMULT_exp_oper_result[7]), .B1(n4743), .Y(n1577) );
NOR3XLTS U6181 ( .A(FPMULT_exp_oper_result[8]), .B(
FPMULT_Exp_module_Overflow_flag_A), .C(n4745), .Y(n4746) );
OAI21XLTS U6182 ( .A0(n4747), .A1(underflow_flag_mult), .B0(n4746), .Y(n4748) );
OAI2BB1X1TS U6183 ( .A0N(mult_result[31]), .A1N(n4273), .B0(n4748), .Y(n1576) );
OAI211XLTS U6184 ( .A0(n4750), .A1(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[21]), .B0(n4759), .C0(
n4749), .Y(n4751) );
OAI2BB1X1TS U6185 ( .A0N(FPMULT_P_Sgf[45]), .A1N(n4755), .B0(n4751), .Y(
n1574) );
OAI211XLTS U6186 ( .A0(n4753), .A1(
FPMULT_Sgf_operation_RECURSIVE_EVEN1_Q_left[15]), .B0(n4759), .C0(
n4752), .Y(n4754) );
OAI2BB1X1TS U6187 ( .A0N(FPMULT_P_Sgf[39]), .A1N(n4755), .B0(n4754), .Y(
n1568) );
AOI21X1TS U6188 ( .A0(n4758), .A1(n4757), .B0(n4756), .Y(n4763) );
OAI21XLTS U6189 ( .A0(n4761), .A1(n4760), .B0(n4759), .Y(n4762) );
OA22X1TS U6190 ( .A0(FPMULT_P_Sgf[37]), .A1(n4764), .B0(n4763), .B1(n4762),
.Y(n1566) );
AOI22X1TS U6191 ( .A0(n4782), .A1(FPADDSUB_intDX_EWSW[28]), .B0(
FPADDSUB_DMP_EXP_EWSW[28]), .B1(n4765), .Y(n4766) );
OAI2BB1X1TS U6192 ( .A0N(FPADDSUB_intDY_EWSW[28]), .A1N(n4892), .B0(n4766),
.Y(n1460) );
NAND2X1TS U6193 ( .A(FPADDSUB_DMP_SFG[22]), .B(n4973), .Y(n4767) );
AOI22X1TS U6194 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[24]), .A1(n5126), .B0(n4767),
.B1(n2343), .Y(n4769) );
AOI22X1TS U6195 ( .A0(FPADDSUB_OP_FLAG_SFG), .A1(n4769), .B0(n4768), .B1(
n5030), .Y(n4770) );
XOR2X1TS U6196 ( .A(FPADDSUB_DmP_mant_SFG_SWR[25]), .B(n4770), .Y(n4771) );
AOI22X1TS U6197 ( .A0(n4853), .A1(n4771), .B0(n5138), .B1(n4319), .Y(n1410)
);
AOI22X1TS U6198 ( .A0(FPADDSUB_Data_array_SWR[5]), .A1(n2304), .B0(
FPADDSUB_Data_array_SWR[1]), .B1(n2295), .Y(n4773) );
AOI22X1TS U6199 ( .A0(FPADDSUB_Data_array_SWR[13]), .A1(n2251), .B0(
FPADDSUB_Data_array_SWR[9]), .B1(n4835), .Y(n4772) );
OAI211X1TS U6200 ( .A0(n2362), .A1(n2289), .B0(n4773), .C0(n4772), .Y(n4897)
);
INVX2TS U6201 ( .A(n4774), .Y(n4824) );
NOR2XLTS U6202 ( .A(n4899), .B(n4820), .Y(n4775) );
OAI22X1TS U6203 ( .A0(n2378), .A1(n5095), .B0(n4924), .B1(n2396), .Y(n1408)
);
OAI22X1TS U6204 ( .A0(n4779), .A1(n5026), .B0(n2362), .B1(n4820), .Y(n4780)
);
NOR2X1TS U6205 ( .A(n4824), .B(n4780), .Y(n4913) );
OAI22X1TS U6206 ( .A0(n2378), .A1(n5096), .B0(n4913), .B1(n2396), .Y(n1405)
);
AOI22X1TS U6207 ( .A0(n4826), .A1(FPADDSUB_intDY_EWSW[15]), .B0(
FPADDSUB_DmP_EXP_EWSW[15]), .B1(n4781), .Y(n4783) );
OAI2BB1X1TS U6208 ( .A0N(FPADDSUB_intDX_EWSW[15]), .A1N(n4892), .B0(n4783),
.Y(n1404) );
OAI22X1TS U6209 ( .A0(n4785), .A1(n5026), .B0(n4784), .B1(n4820), .Y(n4786)
);
NOR2X1TS U6210 ( .A(n4824), .B(n4786), .Y(n4917) );
OAI22X1TS U6211 ( .A0(n2378), .A1(n5097), .B0(n4917), .B1(n2396), .Y(n1402)
);
AO22XLTS U6212 ( .A0(FPADDSUB_Data_array_SWR[14]), .A1(n2252), .B0(
FPADDSUB_Data_array_SWR[10]), .B1(n2395), .Y(n4788) );
AO22XLTS U6213 ( .A0(FPADDSUB_Data_array_SWR[6]), .A1(n2305), .B0(
FPADDSUB_Data_array_SWR[2]), .B1(n2296), .Y(n4787) );
AOI211X1TS U6214 ( .A0(FPADDSUB_shift_value_SHT2_EWR[4]), .A1(n4789), .B0(
n4788), .C0(n4787), .Y(n4875) );
OAI22X1TS U6215 ( .A0(n4875), .A1(n5026), .B0(n4874), .B1(n4820), .Y(n4790)
);
NOR2X1TS U6216 ( .A(n4824), .B(n4790), .Y(n4922) );
OAI22X1TS U6217 ( .A0(n2378), .A1(n5098), .B0(n4922), .B1(n2396), .Y(n1399)
);
OAI22X1TS U6218 ( .A0(n4792), .A1(n4820), .B0(n4791), .B1(n5026), .Y(n4793)
);
NOR2X1TS U6219 ( .A(n4824), .B(n4793), .Y(n4918) );
OAI22X1TS U6220 ( .A0(n4877), .A1(n5057), .B0(n4918), .B1(n2396), .Y(n1396)
);
OAI22X1TS U6221 ( .A0(n4796), .A1(n4820), .B0(n4794), .B1(n5026), .Y(n4795)
);
NOR2X1TS U6222 ( .A(n4824), .B(n4795), .Y(n4920) );
OAI22X1TS U6223 ( .A0(n5359), .A1(n5058), .B0(n4920), .B1(n2396), .Y(n1393)
);
AO22XLTS U6224 ( .A0(FPADDSUB_Data_array_SWR[18]), .A1(n2252), .B0(
FPADDSUB_Data_array_SWR[6]), .B1(n2296), .Y(n4798) );
OAI22X1TS U6225 ( .A0(n4796), .A1(n2199), .B0(n5088), .B1(n4810), .Y(n4797)
);
AOI211X1TS U6226 ( .A0(FPADDSUB_Data_array_SWR[10]), .A1(n2304), .B0(n4798),
.C0(n4797), .Y(n4801) );
OAI22X1TS U6227 ( .A0(n4801), .A1(n5026), .B0(n4802), .B1(n4820), .Y(n4799)
);
NOR2X1TS U6228 ( .A(n4824), .B(n4799), .Y(n4915) );
OAI22X1TS U6229 ( .A0(n4877), .A1(n5059), .B0(n4915), .B1(n2396), .Y(n1390)
);
INVX2TS U6230 ( .A(n4800), .Y(n4883) );
OAI22X1TS U6231 ( .A0(n4802), .A1(n4898), .B0(FPADDSUB_left_right_SHT2),
.B1(n4801), .Y(n4902) );
NOR2XLTS U6232 ( .A(n4883), .B(n4902), .Y(n4803) );
OAI22X1TS U6233 ( .A0(n2378), .A1(n5099), .B0(n4803), .B1(n2396), .Y(n1387)
);
INVX2TS U6234 ( .A(n2377), .Y(n4877) );
NOR2XLTS U6235 ( .A(n4883), .B(n4804), .Y(n4805) );
OAI22X1TS U6236 ( .A0(n4877), .A1(n5060), .B0(n4805), .B1(n4884), .Y(n1384)
);
AOI21X1TS U6237 ( .A0(FPADDSUB_Data_array_SWR[10]), .A1(n2296), .B0(n4831),
.Y(n4807) );
AOI22X1TS U6238 ( .A0(FPADDSUB_Data_array_SWR[22]), .A1(n2251), .B0(
FPADDSUB_Data_array_SWR[18]), .B1(n2395), .Y(n4806) );
OAI211X1TS U6239 ( .A0(n5088), .A1(n2206), .B0(n4807), .C0(n4806), .Y(n4814)
);
NOR2X1TS U6240 ( .A(n4831), .B(n4808), .Y(n4837) );
AOI22X1TS U6241 ( .A0(FPADDSUB_Data_array_SWR[19]), .A1(n2304), .B0(
FPADDSUB_Data_array_SWR[15]), .B1(n2295), .Y(n4809) );
OAI211X1TS U6242 ( .A0(n5112), .A1(n4810), .B0(n4837), .C0(n4809), .Y(n4815)
);
AOI22X1TS U6243 ( .A0(FPADDSUB_left_right_SHT2), .A1(n4814), .B0(n4815),
.B1(n5026), .Y(n4911) );
OAI22X1TS U6244 ( .A0(n2378), .A1(n5061), .B0(n4911), .B1(n2397), .Y(n1381)
);
NOR2XLTS U6245 ( .A(n4811), .B(n4820), .Y(n4812) );
OAI22X1TS U6246 ( .A0(n5359), .A1(n5062), .B0(n4914), .B1(n4884), .Y(n1378)
);
AOI22X1TS U6247 ( .A0(FPADDSUB_left_right_SHT2), .A1(n4815), .B0(n4814),
.B1(n2321), .Y(n4906) );
OAI22X1TS U6248 ( .A0(n5359), .A1(n5100), .B0(n4906), .B1(n2397), .Y(n1375)
);
AOI22X1TS U6249 ( .A0(FPADDSUB_Data_array_SWR[16]), .A1(n2304), .B0(
FPADDSUB_Data_array_SWR[24]), .B1(n2251), .Y(n4817) );
AOI22X1TS U6250 ( .A0(FPADDSUB_Data_array_SWR[20]), .A1(n4835), .B0(
FPADDSUB_Data_array_SWR[12]), .B1(n2296), .Y(n4816) );
NAND2X1TS U6251 ( .A(n4817), .B(n4816), .Y(n4829) );
AOI22X1TS U6252 ( .A0(FPADDSUB_Data_array_SWR[21]), .A1(n4835), .B0(
FPADDSUB_Data_array_SWR[17]), .B1(n2305), .Y(n4819) );
AOI22X1TS U6253 ( .A0(FPADDSUB_Data_array_SWR[13]), .A1(n2295), .B0(
FPADDSUB_Data_array_SWR[25]), .B1(n2252), .Y(n4818) );
NAND2X1TS U6254 ( .A(n4819), .B(n4818), .Y(n4830) );
OAI22X1TS U6255 ( .A0(n4877), .A1(n5101), .B0(n4909), .B1(n4884), .Y(n1372)
);
OAI22X1TS U6256 ( .A0(n4822), .A1(n5026), .B0(n2361), .B1(n4820), .Y(n4823)
);
NOR2X1TS U6257 ( .A(n4824), .B(n4823), .Y(n4912) );
OAI22X1TS U6258 ( .A0(n5359), .A1(n5063), .B0(n4912), .B1(n2397), .Y(n1369)
);
AOI22X1TS U6259 ( .A0(n4782), .A1(FPADDSUB_intDY_EWSW[14]), .B0(
FPADDSUB_DmP_EXP_EWSW[14]), .B1(n4825), .Y(n4827) );
OAI2BB1X1TS U6260 ( .A0N(FPADDSUB_intDX_EWSW[14]), .A1N(n4828), .B0(n4827),
.Y(n1368) );
OAI22X1TS U6261 ( .A0(n4877), .A1(n5064), .B0(n4908), .B1(n4884), .Y(n1366)
);
AOI21X1TS U6262 ( .A0(FPADDSUB_Data_array_SWR[15]), .A1(n2305), .B0(n4831),
.Y(n4833) );
AOI22X1TS U6263 ( .A0(FPADDSUB_Data_array_SWR[19]), .A1(n4835), .B0(
FPADDSUB_Data_array_SWR[11]), .B1(n2296), .Y(n4832) );
OAI211X1TS U6264 ( .A0(n5112), .A1(n4834), .B0(n4833), .C0(n4832), .Y(n4880)
);
AOI22X1TS U6265 ( .A0(FPADDSUB_Data_array_SWR[22]), .A1(n4835), .B0(
FPADDSUB_Data_array_SWR[18]), .B1(n2305), .Y(n4836) );
OAI211X1TS U6266 ( .A0(n5088), .A1(n4838), .B0(n4837), .C0(n4836), .Y(n4881)
);
AOI22X1TS U6267 ( .A0(FPADDSUB_left_right_SHT2), .A1(n4880), .B0(n4881),
.B1(n2321), .Y(n4910) );
OAI22X1TS U6268 ( .A0(n5359), .A1(n5065), .B0(n4910), .B1(n2397), .Y(n1363)
);
NAND2X1TS U6269 ( .A(FPADDSUB_OP_FLAG_SFG), .B(FPADDSUB_DmP_mant_SFG_SWR[0]),
.Y(n4839) );
XOR2X1TS U6270 ( .A(FPADDSUB_DmP_mant_SFG_SWR[1]), .B(n4839), .Y(n4840) );
AOI22X1TS U6271 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(n4840), .B0(n5084),
.B1(n4867), .Y(n1348) );
AOI21X1TS U6272 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[6]), .A1(n5117), .B0(n4841),
.Y(n4845) );
AOI2BB2XLTS U6273 ( .B0(n4843), .B1(n5030), .A0N(n5030), .A1N(n4842), .Y(
n4844) );
XNOR2X1TS U6274 ( .A(n4845), .B(n4844), .Y(n4847) );
AOI22X1TS U6275 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(n4847), .B0(n4949),
.B1(n4846), .Y(n1343) );
AOI22X1TS U6276 ( .A0(FPADDSUB_OP_FLAG_SFG), .A1(n4849), .B0(n4848), .B1(
n5030), .Y(n4851) );
XNOR2X1TS U6277 ( .A(n4851), .B(n4850), .Y(n4852) );
AOI22X1TS U6278 ( .A0(n4853), .A1(n4852), .B0(n4948), .B1(n4846), .Y(n1334)
);
AOI22X1TS U6279 ( .A0(FPADDSUB_OP_FLAG_SFG), .A1(n4855), .B0(n4854), .B1(
n5030), .Y(n4858) );
OAI21XLTS U6280 ( .A0(FPADDSUB_DMP_SFG[15]), .A1(n5073), .B0(n4856), .Y(
n4857) );
XOR2X1TS U6281 ( .A(n4858), .B(n4857), .Y(n4859) );
AOI22X1TS U6282 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[2]), .A1(n4859), .B0(n5056),
.B1(n4319), .Y(n1332) );
OAI22X1TS U6283 ( .A0(n4877), .A1(n5066), .B0(n4861), .B1(n4884), .Y(n1329)
);
AOI21X1TS U6284 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[21]), .A1(n5179), .B0(n4862),
.Y(n4866) );
AOI2BB2XLTS U6285 ( .B0(n4864), .B1(n5030), .A0N(n5030), .A1N(n4863), .Y(
n4865) );
XNOR2X1TS U6286 ( .A(n4866), .B(n4865), .Y(n4868) );
AOI22X1TS U6287 ( .A0(n4869), .A1(n4868), .B0(n4943), .B1(n4867), .Y(n1319)
);
NOR2XLTS U6288 ( .A(n4883), .B(n4870), .Y(n4871) );
OAI22X1TS U6289 ( .A0(n5359), .A1(n5067), .B0(n4871), .B1(n2397), .Y(n1313)
);
NOR2XLTS U6290 ( .A(n4883), .B(n4872), .Y(n4873) );
OAI22X1TS U6291 ( .A0(n4877), .A1(n5068), .B0(n4873), .B1(n4884), .Y(n1306)
);
OAI22X1TS U6292 ( .A0(n2320), .A1(n4875), .B0(n4874), .B1(n4898), .Y(n4901)
);
NOR2XLTS U6293 ( .A(n4883), .B(n4901), .Y(n4876) );
OAI22X1TS U6294 ( .A0(n5359), .A1(n5102), .B0(n4876), .B1(n2397), .Y(n1299)
);
NOR2XLTS U6295 ( .A(n4883), .B(n4878), .Y(n4879) );
OAI22X1TS U6296 ( .A0(n4886), .A1(n5069), .B0(n4879), .B1(n4884), .Y(n1292)
);
AOI22X1TS U6297 ( .A0(FPADDSUB_left_right_SHT2), .A1(n4881), .B0(n4880),
.B1(n2321), .Y(n4907) );
OAI22X1TS U6298 ( .A0(n4886), .A1(n5103), .B0(n4907), .B1(n2397), .Y(n1285)
);
NOR2XLTS U6299 ( .A(n4883), .B(n4882), .Y(n4885) );
OAI22X1TS U6300 ( .A0(n4886), .A1(n5070), .B0(n4885), .B1(n4884), .Y(n1278)
);
AOI22X1TS U6301 ( .A0(n4890), .A1(FPADDSUB_intDX_EWSW[16]), .B0(
FPADDSUB_DMP_EXP_EWSW[16]), .B1(n4887), .Y(n4888) );
OAI2BB1X1TS U6302 ( .A0N(FPADDSUB_intDY_EWSW[16]), .A1N(n4892), .B0(n4888),
.Y(n1249) );
AOI22X1TS U6303 ( .A0(n4890), .A1(FPADDSUB_intDX_EWSW[4]), .B0(
FPADDSUB_DMP_EXP_EWSW[4]), .B1(n4889), .Y(n4891) );
OAI2BB1X1TS U6304 ( .A0N(FPADDSUB_intDY_EWSW[4]), .A1N(n4892), .B0(n4891),
.Y(n1237) );
OAI2BB2XLTS U6305 ( .B0(n4894), .B1(n4898), .A0N(n2321), .A1N(n4893), .Y(
n4895) );
OA22X1TS U6306 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[0]), .A1(n4896), .B0(n4895),
.B1(n4903), .Y(n1205) );
OAI2BB2XLTS U6307 ( .B0(n4899), .B1(n4898), .A0N(n2321), .A1N(n4897), .Y(
n4900) );
OA22X1TS U6308 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[1]), .A1(n4919), .B0(n4900),
.B1(n4903), .Y(n1204) );
OA22X1TS U6309 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[2]), .A1(n4905), .B0(n4903),
.B1(n4901), .Y(n1203) );
OA22X1TS U6310 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[6]), .A1(n4919), .B0(n4903),
.B1(n4902), .Y(n1199) );
CLKBUFX3TS U6311 ( .A(n4904), .Y(n4925) );
AOI22X1TS U6312 ( .A0(n4925), .A1(n4906), .B0(n5005), .B1(n4921), .Y(n1195)
);
AOI22X1TS U6313 ( .A0(n4925), .A1(n4907), .B0(n5006), .B1(n4921), .Y(n1194)
);
AOI22X1TS U6314 ( .A0(n4925), .A1(n4908), .B0(n4968), .B1(n4921), .Y(n1193)
);
AOI22X1TS U6315 ( .A0(n4925), .A1(n4909), .B0(n4972), .B1(n4916), .Y(n1192)
);
AOI22X1TS U6316 ( .A0(n4925), .A1(n4910), .B0(n5007), .B1(n4921), .Y(n1191)
);
AOI22X1TS U6317 ( .A0(n4919), .A1(n4911), .B0(n4969), .B1(n4921), .Y(n1190)
);
AOI22X1TS U6318 ( .A0(n4919), .A1(n4912), .B0(n5137), .B1(n4921), .Y(n1189)
);
AOI22X1TS U6319 ( .A0(n4919), .A1(n4913), .B0(n5073), .B1(n4921), .Y(n1188)
);
AOI22X1TS U6320 ( .A0(n4925), .A1(n4914), .B0(n5008), .B1(n4921), .Y(n1187)
);
AOI22X1TS U6321 ( .A0(n4919), .A1(n4915), .B0(n5009), .B1(n4923), .Y(n1186)
);
AOI22X1TS U6322 ( .A0(n4925), .A1(n4917), .B0(n5010), .B1(n4916), .Y(n1185)
);
AOI22X1TS U6323 ( .A0(n4919), .A1(n4918), .B0(n5130), .B1(n4923), .Y(n1184)
);
AOI22X1TS U6324 ( .A0(n4925), .A1(n4920), .B0(n5074), .B1(n4921), .Y(n1183)
);
AOI22X1TS U6325 ( .A0(n4925), .A1(n4922), .B0(n5075), .B1(n4921), .Y(n1182)
);
AOI22X1TS U6326 ( .A0(n4925), .A1(n4924), .B0(n4973), .B1(n4923), .Y(n1181)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/06/07 12:57:48
// Design Name:
// Module Name: shift_out_register
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module shift_out_register
#(parameter WIDTH = 3)
(
input [WIDTH:0] start,
input clk,
input load,
input shift,
input [(WIDTH-1):0] D,
input shift_in,
output [(WIDTH-1):0] Q,
output shift_out
);
reg [(WIDTH-1):0] shift_reg;
always @(posedge start[0] or posedge clk) begin
if (start[0]) begin
shift_reg <= start[WIDTH:1];
end
else begin
if (load) begin
shift_reg <= D;
end
else if (shift) begin
if (WIDTH == 1) begin
shift_reg <= shift_in;
end
else begin
shift_reg <= {shift_in, shift_reg[(WIDTH-1):1]};
end
end
end
end
assign shift_out = shift_reg[0];
assign Q = shift_reg;
endmodule
|
/////////////////////////////////////////////////////////////////////////
//
// pLIB
// D-FLIP-FLOPS
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
// p_I_FD FD error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FD (Q,D,C,E);
parameter INIT=1'b0;
output Q;
input D;
input C;
input E;
wire Dtemp;
// Xilinx FD instance
defparam FD_z.INIT=INIT;
FD FD_z (.Q(Q),.D(Dtemp),.C(C));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FD FD error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FD (Q,D,C,E);
parameter INIT = 1'b0;
output Q;
input D;
input C;
input E;
wire Qtemp;
// Xilinx FD instance
FD #(.INIT(INIT)) FD_z (.Q(Qtemp),.D(D),.C(C));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FD_1 FD_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FD_1 (Q,D,C,E);
output Q;
input D;
input C;
input E;
wire Dtemp;
// Xilinx FD instance
FD_1 FD_z (.Q(Q),.D(Dtemp),.C(C));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FD_1 FD_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FD_1 (Q,D,C,E);
output Q;
input D;
input C;
input E;
wire Qtemp;
// Xilinx FD instance
FD_1 FD_z (.Q(Qtemp),.D(D),.C(C));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDC FDC error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDC (Q,D,C,CLR,E);
output Q;
input D;
input C;
input E;
input CLR;
wire Dtemp;
// Xilinx FD instance
FDC FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDC FDC error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDC (Q,D,C,CLR,E);
output Q;
input D;
input C;
input E;
input CLR;
wire Qtemp;
// Xilinx FD instance
FDC FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDC_1 FDC_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDC_1 (Q,D,C,CLR,E);
output Q;
input D;
input C;
input E;
input CLR;
wire Dtemp;
// Xilinx FD instance
FDC_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDC_1 FDC_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDC_1 (Q,D,C,CLR,E);
output Q;
input D;
input C;
input E;
input CLR;
wire Qtemp;
// Xilinx FD instance
FDC_1 FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDCE FDCE error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDCE (Q,D,C,CLR,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input CE;
wire Dtemp;
// Xilinx FD instance
FDCE FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR),.CE(CE));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDCE FDCE error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDCE (Q,D,C,CLR,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input CE;
wire Qtemp;
// Xilinx FD instance
FDCE FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR),.CE(CE));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDCE_1 FDCE error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDCE_1 (Q,D,C,CLR,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input CE;
wire Dtemp;
// Xilinx FD instance
FDCE_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR),.CE(CE));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDCE_1 FDCE_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDCE_1 (Q,D,C,CLR,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input CE;
wire Qtemp;
// Xilinx FD instance
FDCE_1 FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR),.CE(CE));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDCP FDCP error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDCP (Q,D,C,CLR,PRE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
wire Dtemp;
// Xilinx FD instance
FDCP FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR),.PRE(PRE));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDCP FDCP error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDCP (Q,D,C,CLR,PRE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
wire Qtemp;
// Xilinx FD instance
FDCP FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR),.PRE(PRE));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDCP_1 FDCP_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDCP_1 (Q,D,C,CLR,PRE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
wire Dtemp;
// Xilinx FD instance
FDCP_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR),.PRE(PRE));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDCP_1 FDCP_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDCP_1 (Q,D,C,CLR,PRE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
wire Qtemp;
// Xilinx FD instance
FDCP_1 FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR),.PRE(PRE));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDCPE FDCPE error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDCPE (Q,D,C,CLR,PRE,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
input CE;
wire Dtemp;
// Xilinx FD instance
FDCPE FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR),.PRE(PRE),.CE(CE));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDCPE FDCPE error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDCPE (Q,D,C,CLR,PRE,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
input CE;
wire Qtemp;
// Xilinx FD instance
FDCPE FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR),.PRE(PRE),.CE(CE));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDCPE_1 FDCPE_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDCPE_1 (Q,D,C,CLR,PRE,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
input CE;
wire Dtemp;
// Xilinx FD instance
FDCPE_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR),.PRE(PRE),.CE(CE));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDCPE_1 FDCPE_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDCPE_1 (Q,D,C,CLR,PRE,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
input CE;
wire Qtemp;
// Xilinx FD instance
FDCPE_1 FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR),.PRE(PRE),.CE(CE));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDE FDE error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDE (Q,D,C,CE,E);
output Q;
input D;
input C;
input E;
input CE;
wire Dtemp;
// Xilinx FD instance
FDE FD_z (.Q(Q),.D(Dtemp),.C(C),.CE(CE));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDE FDE error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDE (Q,D,C,CE,E);
output Q;
input D;
input C;
input E;
input CE;
wire Qtemp;
// Xilinx FD instance
FDE FD_z (.Q(Qtemp),.D(D),.C(C),.CE(CE));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDE_1 FDE_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDE_1 (Q,D,C,CE,E);
output Q;
input D;
input C;
input E;
input CE;
wire Dtemp;
// Xilinx FD instance
FDE_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.CE(CE));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDE_1 FDE_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDE_1 (Q,D,C,CE,E);
output Q;
input D;
input C;
input E;
input CE;
wire Qtemp;
// Xilinx FD instance
FDE_1 FD_z (.Q(Qtemp),.D(D),.C(C),.CE(CE));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDP FDP error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDP (Q,D,C,PRE,E);
output Q;
input D;
input C;
input E;
input PRE;
wire Dtemp;
// Xilinx FD instance
FDP FD_z (.Q(Q),.D(Dtemp),.C(C),.PRE(PRE));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDP FDP error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDP (Q,D,C,PRE,E);
output Q;
input D;
input C;
input E;
input PRE;
wire Qtemp;
// Xilinx FD instance
FDP FD_z (.Q(Qtemp),.D(D),.C(C),.PRE(PRE));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDP_1 FDP_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDP_1 (Q,D,C,PRE,E);
output Q;
input D;
input C;
input E;
input PRE;
wire Dtemp;
// Xilinx FD instance
FDP_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.PRE(PRE));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDP_1 FDP_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDP_1 (Q,D,C,PRE,E);
output Q;
input D;
input C;
input E;
input PRE;
wire Qtemp;
// Xilinx FD instance
FDP_1 FD_z (.Q(Qtemp),.D(D),.C(C),.PRE(PRE));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDPE FDPE error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDPE (Q,D,C,PRE,CE,E);
output Q;
input D;
input C;
input E;
input PRE;
input CE;
wire Dtemp;
// Xilinx FD instance
FDPE FD_z (.Q(Q),.D(Dtemp),.C(C),.PRE(PRE),.CE(CE));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDPE FDPE error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDPE (Q,D,C,PRE,CE,E);
output Q;
input D;
input C;
input E;
input PRE;
input CE;
wire Qtemp;
// Xilinx FD instance
FDPE FD_z (.Q(Qtemp),.D(D),.C(C),.PRE(PRE),.CE(CE));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDPE_1 FDPE_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDPE_1 (Q,D,C,PRE,CE,E);
output Q;
input D;
input C;
input E;
input PRE;
input CE;
wire Dtemp;
// Xilinx FD instance
FDPE_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.PRE(PRE),.CE(CE));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDPE_1 FDPE_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDPE_1 (Q,D,C,PRE,CE,E);
output Q;
input D;
input C;
input E;
input PRE;
input CE;
wire Qtemp;
// Xilinx FD instance
FDPE_1 FD_z (.Q(Qtemp),.D(D),.C(C),.PRE(PRE),.CE(CE));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDR FDR error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDR (Q,D,C,R,E);
output Q;
input D;
input C;
input E;
input R;
wire Dtemp;
// Xilinx FD instance
FDR FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDR FDR error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDR (Q,D,C,R,E);
parameter INIT=1'b0;
output Q;
input D;
input C;
input E;
input R;
wire Qtemp;
defparam FD_z.INIT=INIT;
// Xilinx FD instance
FDR FD_z (.Q(Qtemp),.D(D),.C(C),.R(R));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDR_1 FDR_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDR_1 (Q,D,C,R,E);
output Q;
input D;
input C;
input E;
input R;
wire Dtemp;
// Xilinx FD instance
FDR_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDR_1 FDR_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDR_1 (Q,D,C,R,E);
output Q;
input D;
input C;
input E;
input R;
wire Qtemp;
// Xilinx FD instance
FDR_1 FD_z (.Q(Qtemp),.D(D),.C(C),.R(R));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDRE FDRE error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDRE (Q,D,C,R,CE,E);
output Q;
input D;
input C;
input E;
input R;
input CE;
wire Dtemp;
// Xilinx FD instance
FDRE FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R),.CE(CE));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDRE FDRE error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDRE (Q,D,C,R,CE,E);
parameter INIT=1'b0;
output Q;
input D;
input C;
input E;
input R;
input CE;
wire Qtemp;
// Xilinx FD instance
FDRE #(.INIT(INIT)) FD_z (.Q(Qtemp),.D(D),.C(C),.R(R),.CE(CE));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDRE_1 FDRE_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDRE_1 (Q,D,C,R,CE,E);
output Q;
input D;
input C;
input E;
input R;
input CE;
wire Dtemp;
// Xilinx FD instance
FDRE_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R),.CE(CE));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDRE_1 FDRE_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDRE_1 (Q,D,C,R,CE,E);
output Q;
input D;
input C;
input E;
input R;
input CE;
wire Qtemp;
// Xilinx FD instance
FDRE_1 FD_z (.Q(Qtemp),.D(D),.C(C),.R(R),.CE(CE));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDRS FDRS error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDRS (Q,D,C,R,S,E);
output Q;
input D;
input C;
input E;
input R;
input S;
wire Dtemp;
// Xilinx FD instance
FDRS FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R),.S(S));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDRS FDRS error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDRS (Q,D,C,R,S,E);
output Q;
input D;
input C;
input E;
input R;
input S;
wire Qtemp;
// Xilinx FD instance
FDRS FD_z (.Q(Qtemp),.D(D),.C(C),.R(R),.S(S));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDRS_1 FDRS_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDRS_1 (Q,D,C,R,S,E);
output Q;
input D;
input C;
input E;
input R;
input S;
wire Dtemp;
// Xilinx FD instance
FDRS_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R),.S(S));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDRS_1 FDRS_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDRS_1 (Q,D,C,R,S,E);
output Q;
input D;
input C;
input E;
input R;
input S;
wire Qtemp;
// Xilinx FD instance
FDRS_1 FD_z (.Q(Qtemp),.D(D),.C(C),.R(R),.S(S));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDRSE FDRS error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDRSE (Q,D,C,R,S,CE,E);
output Q;
input D;
input C;
input E;
input R;
input S;
input CE;
wire Dtemp;
// Xilinx FD instance
FDRSE FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R),.S(S),.CE(CE));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDRSE FDRSE error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDRSE (Q,D,C,R,S,CE,E);
output Q;
input D;
input C;
input E;
input R;
input S;
input CE;
wire Qtemp;
// Xilinx FD instance
FDRSE FD_z (.Q(Qtemp),.D(D),.C(C),.R(R),.S(S),.CE(CE));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDRSE_1 FDRSE_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDRSE_1 (Q,D,C,R,S,CE,E);
output Q;
input D;
input C;
input E;
input R;
input S;
input CE;
wire Dtemp;
// Xilinx FD instance
FDRSE_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R),.S(S),.CE(CE));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDRSE_1 FDRSE_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDRSE_1 (Q,D,C,R,S,CE,E);
output Q;
input D;
input C;
input E;
input R;
input S;
input CE;
wire Qtemp;
// Xilinx FD instance
FDRSE_1 FD_z (.Q(Qtemp),.D(D),.C(C),.R(R),.S(S),.CE(CE));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDS FDS error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDS (Q,D,C,S,E);
output Q;
input D;
input C;
input E;
input S;
wire Dtemp;
// Xilinx FD instance
FDS FD_z (.Q(Q),.D(Dtemp),.C(C),.S(S));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDS FDS error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDS (Q,D,C,S,E);
output Q;
input D;
input C;
input E;
input S;
wire Qtemp;
// Xilinx FD instance
FDS FD_z (.Q(Qtemp),.D(D),.C(C),.S(S));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDS_1 FDS_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDS_1 (Q,D,C,S,E);
output Q;
input D;
input C;
input E;
input S;
wire Dtemp;
// Xilinx FD instance
FDS_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.S(S));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDS_1 FDS_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDS_1 (Q,D,C,S,E);
output Q;
input D;
input C;
input E;
input S;
wire Qtemp;
// Xilinx FD instance
FDS_1 FD_z (.Q(Qtemp),.D(D),.C(C),.S(S));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDSE FDSE error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDSE (Q,D,C,S,CE,E);
output Q;
input D;
input C;
input E;
input S;
input CE;
wire Dtemp;
// Xilinx FD instance
FDSE FD_z (.Q(Q),.D(Dtemp),.C(C),.S(S),.CE(CE));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDSE FDSE error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDSE (Q,D,C,S,CE,E);
output Q;
input D;
input C;
input E;
input S;
input CE;
wire Qtemp;
// Xilinx FD instance
FDSE FD_z (.Q(Qtemp),.D(D),.C(C),.S(S),.CE(CE));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDSE_1 FDSE_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDSE_1 (Q,D,C,S,CE,E);
output Q;
input D;
input C;
input E;
input S;
input CE;
wire Dtemp;
// Xilinx FD instance
FDSE_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.S(S),.CE(CE));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDSE_1 FDSE_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDSE_1 (Q,D,C,S,CE,E);
output Q;
input D;
input C;
input E;
input S;
input CE;
wire Qtemp;
// Xilinx FD instance
FDSE_1 FD_z (.Q(Qtemp),.D(D),.C(C),.S(S),.CE(CE));
// Error injection
and (Q,Qtemp,E);
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_cpu_jtag_debug_module_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ps / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_amphy_controller_phy (
// inputs:
dqs_delay_ctrl_import,
dqs_offset_delay_ctrl,
global_reset_n,
hc_scan_ck,
hc_scan_din,
hc_scan_enable_access,
hc_scan_enable_dm,
hc_scan_enable_dq,
hc_scan_enable_dqs,
hc_scan_enable_dqs_config,
hc_scan_update,
local_address,
local_autopch_req,
local_be,
local_burstbegin,
local_multicast_req,
local_read_req,
local_refresh_chip,
local_refresh_req,
local_self_rfsh_chip,
local_self_rfsh_req,
local_size,
local_wdata,
local_write_req,
oct_ctl_rs_value,
oct_ctl_rt_value,
pll_phasecounterselect,
pll_phasestep,
pll_phaseupdown,
pll_reconfig,
pll_reconfig_counter_param,
pll_reconfig_counter_type,
pll_reconfig_data_in,
pll_reconfig_enable,
pll_reconfig_read_param,
pll_reconfig_soft_reset_en_n,
pll_reconfig_write_param,
pll_ref_clk,
soft_reset_n,
// outputs:
aux_full_rate_clk,
aux_half_rate_clk,
aux_scan_clk,
aux_scan_clk_reset_n,
dll_reference_clk,
dqs_delay_ctrl_export,
ecc_interrupt,
hc_scan_dout,
local_init_done,
local_power_down_ack,
local_rdata,
local_rdata_valid,
local_ready,
local_refresh_ack,
local_self_rfsh_ack,
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_clk,
mem_clk_n,
mem_cs_n,
mem_dm,
mem_dq,
mem_dqs,
mem_dqsn,
mem_odt,
mem_ras_n,
mem_reset_n,
mem_we_n,
phy_clk,
pll_phase_done,
pll_reconfig_busy,
pll_reconfig_clk,
pll_reconfig_data_out,
pll_reconfig_reset,
reset_phy_clk_n,
reset_request_n
)
;
output aux_full_rate_clk;
output aux_half_rate_clk;
output aux_scan_clk;
output aux_scan_clk_reset_n;
output dll_reference_clk;
output [ 5: 0] dqs_delay_ctrl_export;
output ecc_interrupt;
output [ 7: 0] hc_scan_dout;
output local_init_done;
output local_power_down_ack;
output [ 31: 0] local_rdata;
output local_rdata_valid;
output local_ready;
output local_refresh_ack;
output local_self_rfsh_ack;
output [ 12: 0] mem_addr;
output [ 2: 0] mem_ba;
output mem_cas_n;
output [ 0: 0] mem_cke;
inout [ 0: 0] mem_clk;
inout [ 0: 0] mem_clk_n;
output [ 0: 0] mem_cs_n;
output [ 0: 0] mem_dm;
inout [ 7: 0] mem_dq;
inout [ 0: 0] mem_dqs;
inout [ 0: 0] mem_dqsn;
output [ 0: 0] mem_odt;
output mem_ras_n;
output mem_reset_n;
output mem_we_n;
output phy_clk;
output pll_phase_done;
output pll_reconfig_busy;
output pll_reconfig_clk;
output pll_reconfig_data_out;
output pll_reconfig_reset;
output reset_phy_clk_n;
output reset_request_n;
input [ 5: 0] dqs_delay_ctrl_import;
input [ 5: 0] dqs_offset_delay_ctrl;
input global_reset_n;
input hc_scan_ck;
input [ 0: 0] hc_scan_din;
input hc_scan_enable_access;
input [ 0: 0] hc_scan_enable_dm;
input [ 7: 0] hc_scan_enable_dq;
input [ 0: 0] hc_scan_enable_dqs;
input [ 0: 0] hc_scan_enable_dqs_config;
input [ 0: 0] hc_scan_update;
input [ 23: 0] local_address;
input local_autopch_req;
input [ 3: 0] local_be;
input local_burstbegin;
input local_multicast_req;
input local_read_req;
input local_refresh_chip;
input local_refresh_req;
input local_self_rfsh_chip;
input local_self_rfsh_req;
input [ 2: 0] local_size;
input [ 31: 0] local_wdata;
input local_write_req;
input [ 13: 0] oct_ctl_rs_value;
input [ 13: 0] oct_ctl_rt_value;
input [ 3: 0] pll_phasecounterselect;
input pll_phasestep;
input pll_phaseupdown;
input pll_reconfig;
input [ 2: 0] pll_reconfig_counter_param;
input [ 3: 0] pll_reconfig_counter_type;
input pll_reconfig_data_in;
input pll_reconfig_enable;
input pll_reconfig_read_param;
input pll_reconfig_soft_reset_en_n;
input pll_reconfig_write_param;
input pll_ref_clk;
input soft_reset_n;
wire [ 25: 0] afi_addr;
wire [ 5: 0] afi_ba;
wire [ 1: 0] afi_cas_n;
wire [ 1: 0] afi_cke;
wire [ 1: 0] afi_cs_n;
wire afi_ctl_long_idle;
wire afi_ctl_refresh_done;
wire [ 3: 0] afi_dm;
wire [ 1: 0] afi_dqs_burst;
wire [ 1: 0] afi_odt;
wire [ 1: 0] afi_ras_n;
wire [ 31: 0] afi_rdata;
wire [ 1: 0] afi_rdata_en;
wire [ 1: 0] afi_rdata_en_full;
wire [ 1: 0] afi_rdata_valid;
wire [ 1: 0] afi_rst_n;
wire [ 31: 0] afi_wdata;
wire [ 1: 0] afi_wdata_valid;
wire [ 1: 0] afi_we_n;
wire [ 4: 0] afi_wlat;
wire aux_full_rate_clk;
wire aux_half_rate_clk;
wire aux_scan_clk;
wire aux_scan_clk_reset_n;
wire [ 31: 0] csr_rdata_sig;
wire csr_rdata_valid_sig;
wire csr_waitrequest_sig;
wire ctl_cal_byte_lane_sel_n;
wire ctl_cal_fail;
wire ctl_cal_req;
wire ctl_cal_success;
wire ctl_clk;
wire ctl_mem_clk_disable;
wire [ 4: 0] ctl_rlat;
wire [ 31: 0] dbg_rd_data_sig;
wire dbg_waitrequest_sig;
wire dll_reference_clk;
wire [ 5: 0] dqs_delay_ctrl_export;
wire ecc_interrupt;
wire [ 7: 0] hc_scan_dout;
wire local_init_done;
wire local_power_down_ack;
wire [ 31: 0] local_rdata;
wire local_rdata_valid;
wire local_ready;
wire local_refresh_ack;
wire local_self_rfsh_ack;
wire mem_ac_parity;
wire [ 12: 0] mem_addr;
wire [ 2: 0] mem_ba;
wire mem_cas_n;
wire [ 0: 0] mem_cke;
wire [ 0: 0] mem_clk;
wire [ 0: 0] mem_clk_n;
wire [ 0: 0] mem_cs_n;
wire [ 0: 0] mem_dm;
wire [ 7: 0] mem_dq;
wire [ 0: 0] mem_dqs;
wire [ 0: 0] mem_dqsn;
wire mem_err_out_n;
wire [ 0: 0] mem_odt;
wire mem_ras_n;
wire mem_reset_n;
wire mem_we_n;
wire parity_error_n;
wire phy_clk;
wire pll_phase_done;
wire pll_reconfig_busy;
wire pll_reconfig_clk;
wire pll_reconfig_data_out;
wire pll_reconfig_reset;
wire reset_ctl_clk_n;
wire reset_phy_clk_n;
wire reset_request_n;
assign mem_err_out_n = 1'b1;
assign phy_clk = ctl_clk;
assign reset_phy_clk_n = reset_ctl_clk_n;
ddr3_s4_amphy_alt_mem_ddrx_controller_top ddr3_s4_amphy_alt_mem_ddrx_controller_top_inst
(
.afi_addr (afi_addr),
.afi_ba (afi_ba),
.afi_cal_byte_lane_sel_n (ctl_cal_byte_lane_sel_n),
.afi_cal_fail (ctl_cal_fail),
.afi_cal_req (ctl_cal_req),
.afi_cal_success (ctl_cal_success),
.afi_cas_n (afi_cas_n),
.afi_cke (afi_cke),
.afi_cs_n (afi_cs_n),
.afi_ctl_long_idle (afi_ctl_long_idle),
.afi_ctl_refresh_done (afi_ctl_refresh_done),
.afi_dm (afi_dm),
.afi_dqs_burst (afi_dqs_burst),
.afi_mem_clk_disable (ctl_mem_clk_disable),
.afi_odt (afi_odt),
.afi_ras_n (afi_ras_n),
.afi_rdata (afi_rdata),
.afi_rdata_en (afi_rdata_en),
.afi_rdata_en_full (afi_rdata_en_full),
.afi_rdata_valid (afi_rdata_valid),
.afi_rlat (ctl_rlat),
.afi_rst_n (afi_rst_n),
.afi_seq_busy ({1{1'b0}}),
.afi_wdata (afi_wdata),
.afi_wdata_valid (afi_wdata_valid),
.afi_we_n (afi_we_n),
.afi_wlat (afi_wlat),
.clk (ctl_clk),
.csr_addr (16'b0),
.csr_be (4'b0),
.csr_beginbursttransfer (1'b0),
.csr_burst_count (1'b0),
.csr_rdata (csr_rdata_sig),
.csr_rdata_valid (csr_rdata_valid_sig),
.csr_read_req (1'b0),
.csr_waitrequest (csr_waitrequest_sig),
.csr_wdata (32'b0),
.csr_write_req (1'b0),
.ecc_interrupt (ecc_interrupt),
.half_clk (aux_half_rate_clk),
.local_address (local_address),
.local_autopch_req (local_autopch_req),
.local_beginbursttransfer (local_burstbegin),
.local_burstcount (local_size),
.local_byteenable (local_be),
.local_init_done (local_init_done),
.local_multicast (local_multicast_req),
.local_powerdn_ack (local_power_down_ack),
.local_powerdn_req (1'b0),
.local_priority (1'b1),
.local_read (local_read_req),
.local_readdata (local_rdata),
.local_readdatavalid (local_rdata_valid),
.local_ready (local_ready),
.local_refresh_ack (local_refresh_ack),
.local_refresh_chip (local_refresh_chip),
.local_refresh_req (local_refresh_req),
.local_self_rfsh_ack (local_self_rfsh_ack),
.local_self_rfsh_chip (local_self_rfsh_chip),
.local_self_rfsh_req (local_self_rfsh_req),
.local_write (local_write_req),
.local_writedata (local_wdata),
.reset_n (reset_ctl_clk_n)
);
ddr3_s4_amphy_phy ddr3_s4_amphy_phy_inst
(
.aux_full_rate_clk (aux_full_rate_clk),
.aux_half_rate_clk (aux_half_rate_clk),
.aux_scan_clk (aux_scan_clk),
.aux_scan_clk_reset_n (aux_scan_clk_reset_n),
.ctl_addr (afi_addr),
.ctl_ba (afi_ba),
.ctl_cal_byte_lane_sel_n (ctl_cal_byte_lane_sel_n),
.ctl_cal_fail (ctl_cal_fail),
.ctl_cal_req (ctl_cal_req),
.ctl_cal_success (ctl_cal_success),
.ctl_cas_n (afi_cas_n),
.ctl_cke (afi_cke),
.ctl_clk (ctl_clk),
.ctl_cs_n (afi_cs_n),
.ctl_dm (afi_dm),
.ctl_doing_rd (afi_rdata_en),
.ctl_dqs_burst (afi_dqs_burst),
.ctl_mem_clk_disable (ctl_mem_clk_disable),
.ctl_odt (afi_odt),
.ctl_ras_n (afi_ras_n),
.ctl_rdata (afi_rdata),
.ctl_rdata_valid (afi_rdata_valid),
.ctl_reset_n (reset_ctl_clk_n),
.ctl_rlat (ctl_rlat),
.ctl_rst_n (afi_rst_n),
.ctl_wdata (afi_wdata),
.ctl_wdata_valid (afi_wdata_valid),
.ctl_we_n (afi_we_n),
.ctl_wlat (afi_wlat),
.dbg_addr (13'b0),
.dbg_clk (ctl_clk),
.dbg_cs (1'b0),
.dbg_rd (1'b0),
.dbg_rd_data (dbg_rd_data_sig),
.dbg_reset_n (reset_ctl_clk_n),
.dbg_waitrequest (dbg_waitrequest_sig),
.dbg_wr (1'b0),
.dbg_wr_data (32'b0),
.dll_reference_clk (dll_reference_clk),
.dqs_delay_ctrl_export (dqs_delay_ctrl_export),
.dqs_delay_ctrl_import (dqs_delay_ctrl_import),
.dqs_offset_delay_ctrl (dqs_offset_delay_ctrl),
.global_reset_n (global_reset_n),
.hc_scan_ck (hc_scan_ck),
.hc_scan_din (hc_scan_din),
.hc_scan_dout (hc_scan_dout[7 : 0]),
.hc_scan_enable_access (hc_scan_enable_access),
.hc_scan_enable_dm (hc_scan_enable_dm),
.hc_scan_enable_dq (hc_scan_enable_dq),
.hc_scan_enable_dqs (hc_scan_enable_dqs),
.hc_scan_enable_dqs_config (hc_scan_enable_dqs_config),
.hc_scan_update (hc_scan_update),
.mem_ac_parity (mem_ac_parity),
.mem_addr (mem_addr),
.mem_ba (mem_ba),
.mem_cas_n (mem_cas_n),
.mem_cke (mem_cke),
.mem_clk (mem_clk),
.mem_clk_n (mem_clk_n),
.mem_cs_n (mem_cs_n),
.mem_dm (mem_dm),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs),
.mem_dqs_n (mem_dqsn),
.mem_err_out_n (mem_err_out_n),
.mem_odt (mem_odt),
.mem_ras_n (mem_ras_n),
.mem_reset_n (mem_reset_n),
.mem_we_n (mem_we_n),
.oct_ctl_rs_value (oct_ctl_rs_value),
.oct_ctl_rt_value (oct_ctl_rt_value),
.parity_error_n (parity_error_n),
.pll_phase_done (pll_phase_done),
.pll_phasecounterselect (pll_phasecounterselect),
.pll_phasestep (pll_phasestep),
.pll_phaseupdown (pll_phaseupdown),
.pll_reconfig_enable (pll_reconfig_enable),
.pll_ref_clk (pll_ref_clk),
.reset_request_n (reset_request_n),
.soft_reset_n (soft_reset_n)
);
//<< start europa
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 14:08:20 2016
/////////////////////////////////////////////////////////////
module FPU_Multiplication_Function_W32_EW8_SW23 ( clk, rst, beg_FSM, ack_FSM,
Data_MX, Data_MY, round_mode, overflow_flag, underflow_flag, ready,
final_result_ieee );
input [31:0] Data_MX;
input [31:0] Data_MY;
input [1:0] round_mode;
output [31:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM;
output overflow_flag, underflow_flag, ready;
wire zero_flag, FSM_add_overflow_flag, FSM_selector_A, FSM_selector_C,
Exp_module_Overflow_flag_A, n167, n168, n170, n171, n172, n173, n174,
n175, n176, n177, n178, n179, n180, n181, n182, n183, n184, n185,
n186, n187, n188, n189, n190, n191, n192, n193, n194, n195, n196,
n197, n198, n199, n200, n201, n202, n203, n204, n205, n206, n207,
n208, n209, n210, n211, n212, n213, n214, n215, n216, n217, n218,
n219, n220, n221, n222, n223, n224, n225, n226, n227, n228, n229,
n230, n231, n232, n233, n234, n235, n236, n237, n238, n239, n240,
n241, n242, n243, n244, n245, n246, n247, n248, n249, n250, n251,
n252, n253, n254, n255, n256, n257, n258, n259, n260, n261, n262,
n263, n264, n265, n266, n267, n268, n269, n270, n271, n272, n273,
n274, n275, n276, n277, n278, n279, n280, n281, n282, n283, n284,
n285, n286, n287, n288, n289, n290, n291, n292, n293, n294, n295,
n296, n297, n298, n299, n300, n301, n302, n303, n304, n305, n306,
n307, n308, n309, n310, n311, n312, n313, n314, n315, n316, n317,
n318, n319, n320, n321, n322, n323, n324, n325, n326, n327, n328,
n329, n330, n331, n332, n333, n334, n335, n336, n337, n338, n339,
n340, n341, n342, n343, n344, n345, n347, n348, n349, n350, n351,
n352, n353, n354, n355, n356, n357, n358, n359, n360, n361, n362,
n363, n364, n365, n366, n367, n368, n369, n370, n371, n372, n373,
n374, n375, n376, n377, n378, n379, n380, n381,
DP_OP_32J15_122_6543_n33, DP_OP_32J15_122_6543_n22,
DP_OP_32J15_122_6543_n21, DP_OP_32J15_122_6543_n20,
DP_OP_32J15_122_6543_n19, DP_OP_32J15_122_6543_n18,
DP_OP_32J15_122_6543_n17, DP_OP_32J15_122_6543_n16,
DP_OP_32J15_122_6543_n15, DP_OP_32J15_122_6543_n9,
DP_OP_32J15_122_6543_n8, DP_OP_32J15_122_6543_n7,
DP_OP_32J15_122_6543_n6, DP_OP_32J15_122_6543_n5,
DP_OP_32J15_122_6543_n4, DP_OP_32J15_122_6543_n3,
DP_OP_32J15_122_6543_n2, DP_OP_32J15_122_6543_n1, mult_x_19_n779,
mult_x_19_n778, mult_x_19_n771, mult_x_19_n770, mult_x_19_n769,
mult_x_19_n768, mult_x_19_n767, mult_x_19_n766, mult_x_19_n765,
mult_x_19_n764, mult_x_19_n763, mult_x_19_n762, mult_x_19_n761,
mult_x_19_n760, mult_x_19_n759, mult_x_19_n758, mult_x_19_n757,
mult_x_19_n756, mult_x_19_n755, mult_x_19_n753, mult_x_19_n752,
mult_x_19_n747, mult_x_19_n746, mult_x_19_n745, mult_x_19_n744,
mult_x_19_n743, mult_x_19_n742, mult_x_19_n741, mult_x_19_n740,
mult_x_19_n739, mult_x_19_n738, mult_x_19_n737, mult_x_19_n736,
mult_x_19_n735, mult_x_19_n734, mult_x_19_n733, mult_x_19_n732,
mult_x_19_n731, mult_x_19_n730, mult_x_19_n729, mult_x_19_n728,
mult_x_19_n726, mult_x_19_n725, mult_x_19_n717, mult_x_19_n716,
mult_x_19_n715, mult_x_19_n714, mult_x_19_n713, mult_x_19_n712,
mult_x_19_n711, mult_x_19_n710, mult_x_19_n709, mult_x_19_n708,
mult_x_19_n707, mult_x_19_n706, mult_x_19_n705, mult_x_19_n704,
mult_x_19_n703, mult_x_19_n702, mult_x_19_n701, mult_x_19_n699,
mult_x_19_n698, mult_x_19_n693, mult_x_19_n692, mult_x_19_n691,
mult_x_19_n690, mult_x_19_n689, mult_x_19_n688, mult_x_19_n687,
mult_x_19_n686, mult_x_19_n685, mult_x_19_n684, mult_x_19_n683,
mult_x_19_n682, mult_x_19_n681, mult_x_19_n680, mult_x_19_n679,
mult_x_19_n678, mult_x_19_n677, mult_x_19_n676, mult_x_19_n675,
mult_x_19_n674, mult_x_19_n672, mult_x_19_n671, mult_x_19_n663,
mult_x_19_n662, mult_x_19_n661, mult_x_19_n660, mult_x_19_n659,
mult_x_19_n658, mult_x_19_n657, mult_x_19_n656, mult_x_19_n655,
mult_x_19_n654, mult_x_19_n653, mult_x_19_n652, mult_x_19_n651,
mult_x_19_n650, mult_x_19_n649, mult_x_19_n648, mult_x_19_n647,
mult_x_19_n645, mult_x_19_n644, mult_x_19_n639, mult_x_19_n638,
mult_x_19_n637, mult_x_19_n636, mult_x_19_n635, mult_x_19_n634,
mult_x_19_n633, mult_x_19_n632, mult_x_19_n631, mult_x_19_n630,
mult_x_19_n629, mult_x_19_n628, mult_x_19_n627, mult_x_19_n626,
mult_x_19_n625, mult_x_19_n624, mult_x_19_n623, mult_x_19_n622,
mult_x_19_n621, mult_x_19_n620, mult_x_19_n618, mult_x_19_n617,
mult_x_19_n608, mult_x_19_n607, mult_x_19_n606, mult_x_19_n605,
mult_x_19_n602, mult_x_19_n601, mult_x_19_n600, mult_x_19_n599,
mult_x_19_n597, mult_x_19_n596, mult_x_19_n595, mult_x_19_n594,
mult_x_19_n593, mult_x_19_n474, mult_x_19_n472, mult_x_19_n471,
mult_x_19_n469, mult_x_19_n468, mult_x_19_n467, mult_x_19_n466,
mult_x_19_n464, mult_x_19_n463, mult_x_19_n462, mult_x_19_n461,
mult_x_19_n459, mult_x_19_n458, mult_x_19_n457, mult_x_19_n454,
mult_x_19_n452, mult_x_19_n451, mult_x_19_n450, mult_x_19_n447,
mult_x_19_n445, mult_x_19_n444, mult_x_19_n443, mult_x_19_n441,
mult_x_19_n440, mult_x_19_n439, mult_x_19_n438, mult_x_19_n437,
mult_x_19_n436, mult_x_19_n435, mult_x_19_n433, mult_x_19_n432,
mult_x_19_n431, mult_x_19_n430, mult_x_19_n429, mult_x_19_n428,
mult_x_19_n427, mult_x_19_n425, mult_x_19_n424, mult_x_19_n423,
mult_x_19_n422, mult_x_19_n421, mult_x_19_n420, mult_x_19_n419,
mult_x_19_n417, mult_x_19_n416, mult_x_19_n415, mult_x_19_n414,
mult_x_19_n413, mult_x_19_n412, mult_x_19_n409, mult_x_19_n407,
mult_x_19_n406, mult_x_19_n405, mult_x_19_n404, mult_x_19_n403,
mult_x_19_n402, mult_x_19_n399, mult_x_19_n397, mult_x_19_n396,
mult_x_19_n395, mult_x_19_n394, mult_x_19_n393, mult_x_19_n392,
mult_x_19_n390, mult_x_19_n389, mult_x_19_n388, mult_x_19_n387,
mult_x_19_n386, mult_x_19_n385, mult_x_19_n384, mult_x_19_n383,
mult_x_19_n382, mult_x_19_n381, mult_x_19_n379, mult_x_19_n378,
mult_x_19_n377, mult_x_19_n376, mult_x_19_n375, mult_x_19_n374,
mult_x_19_n373, mult_x_19_n372, mult_x_19_n371, mult_x_19_n370,
mult_x_19_n368, mult_x_19_n367, mult_x_19_n366, mult_x_19_n365,
mult_x_19_n364, mult_x_19_n363, mult_x_19_n362, mult_x_19_n361,
mult_x_19_n360, mult_x_19_n359, mult_x_19_n357, mult_x_19_n356,
mult_x_19_n355, mult_x_19_n354, mult_x_19_n353, mult_x_19_n352,
mult_x_19_n351, mult_x_19_n350, mult_x_19_n349, mult_x_19_n348,
mult_x_19_n346, mult_x_19_n345, mult_x_19_n344, mult_x_19_n343,
mult_x_19_n342, mult_x_19_n341, mult_x_19_n340, mult_x_19_n339,
mult_x_19_n338, mult_x_19_n337, mult_x_19_n336, mult_x_19_n335,
mult_x_19_n334, mult_x_19_n333, mult_x_19_n332, mult_x_19_n331,
mult_x_19_n330, mult_x_19_n329, mult_x_19_n328, mult_x_19_n327,
mult_x_19_n326, mult_x_19_n325, mult_x_19_n324, mult_x_19_n323,
mult_x_19_n322, mult_x_19_n321, mult_x_19_n320, mult_x_19_n319,
mult_x_19_n318, mult_x_19_n317, mult_x_19_n316, mult_x_19_n315,
mult_x_19_n314, mult_x_19_n313, mult_x_19_n312, mult_x_19_n311,
mult_x_19_n310, mult_x_19_n309, mult_x_19_n308, mult_x_19_n307,
mult_x_19_n306, mult_x_19_n305, mult_x_19_n304, mult_x_19_n303,
mult_x_19_n302, mult_x_19_n301, mult_x_19_n300, mult_x_19_n299,
mult_x_19_n298, mult_x_19_n297, mult_x_19_n296, mult_x_19_n295,
mult_x_19_n294, mult_x_19_n293, mult_x_19_n292, mult_x_19_n291,
mult_x_19_n290, mult_x_19_n289, mult_x_19_n288, mult_x_19_n287,
mult_x_19_n286, mult_x_19_n285, mult_x_19_n284, mult_x_19_n283,
mult_x_19_n282, mult_x_19_n281, mult_x_19_n280, mult_x_19_n279,
mult_x_19_n278, mult_x_19_n277, mult_x_19_n276, mult_x_19_n275,
mult_x_19_n274, mult_x_19_n273, mult_x_19_n272, mult_x_19_n271,
mult_x_19_n270, mult_x_19_n269, mult_x_19_n268, mult_x_19_n267,
mult_x_19_n266, mult_x_19_n265, mult_x_19_n264, mult_x_19_n263,
mult_x_19_n262, mult_x_19_n261, mult_x_19_n260, mult_x_19_n259,
mult_x_19_n258, mult_x_19_n257, mult_x_19_n256, mult_x_19_n255,
mult_x_19_n254, mult_x_19_n252, mult_x_19_n251, mult_x_19_n250,
mult_x_19_n249, mult_x_19_n248, mult_x_19_n247, mult_x_19_n246,
mult_x_19_n245, mult_x_19_n243, mult_x_19_n242, mult_x_19_n241,
mult_x_19_n240, mult_x_19_n239, mult_x_19_n238, mult_x_19_n237,
mult_x_19_n236, mult_x_19_n235, mult_x_19_n234, mult_x_19_n233,
mult_x_19_n232, mult_x_19_n231, mult_x_19_n230, mult_x_19_n229,
mult_x_19_n228, mult_x_19_n227, mult_x_19_n226, mult_x_19_n225,
mult_x_19_n224, mult_x_19_n223, mult_x_19_n222, mult_x_19_n221,
mult_x_19_n220, mult_x_19_n219, mult_x_19_n218, mult_x_19_n217,
mult_x_19_n216, mult_x_19_n215, mult_x_19_n214, mult_x_19_n213,
mult_x_19_n212, mult_x_19_n211, mult_x_19_n210, mult_x_19_n209,
mult_x_19_n208, mult_x_19_n206, mult_x_19_n204, mult_x_19_n203,
mult_x_19_n202, mult_x_19_n200, mult_x_19_n199, mult_x_19_n198,
mult_x_19_n197, mult_x_19_n196, mult_x_19_n195, mult_x_19_n194,
mult_x_19_n193, mult_x_19_n192, mult_x_19_n191, mult_x_19_n189,
mult_x_19_n188, mult_x_19_n187, mult_x_19_n185, mult_x_19_n184,
mult_x_19_n183, mult_x_19_n182, mult_x_19_n181, mult_x_19_n180, n391,
n392, n393, n394, n395, n396, n397, n398, n399, n400, n401, n402,
n403, n404, n405, n406, n407, n408, n409, n410, n411, n412, n413,
n414, n415, n416, n417, n418, n419, n420, n421, n422, n423, n424,
n425, n426, n427, n428, n429, n430, n431, n432, n433, n434, n435,
n436, n437, n438, n439, n440, n441, n442, n443, n444, n445, n446,
n447, n448, n449, n450, n451, n452, n453, n454, n455, n456, n457,
n458, n459, n460, n461, n462, n463, n464, n465, n466, n467, n468,
n469, n470, n471, n472, n473, n474, n475, n476, n477, n478, n479,
n480, n481, n482, n483, n484, n485, n486, n487, n488, n489, n490,
n491, n492, n493, n494, n495, n496, n497, n498, n499, n500, n501,
n502, n503, n504, n505, n506, n507, n508, n509, n510, n511, n512,
n513, n514, n515, n516, n517, n518, n519, n520, n521, n522, n523,
n524, n525, n526, n527, n528, n529, n530, n531, n532, n533, n534,
n535, n536, n537, n538, n539, n540, n541, n542, n543, n544, n545,
n546, n547, n548, n549, n550, n551, n552, n553, n554, n555, n556,
n557, n558, n559, n560, n561, n562, n563, n564, n565, n566, n567,
n568, n569, n570, n571, n572, n573, n574, n575, n576, n577, n578,
n579, n580, n581, n582, n583, n584, n585, n586, n587, n588, n589,
n590, n591, n592, n593, n594, n595, n596, n597, n598, n599, n600,
n601, n602, n603, n604, n605, n606, n607, n608, n609, n610, n611,
n612, n613, n614, n615, n616, n617, n618, n619, n620, n621, n622,
n623, n624, n625, n626, n627, n628, n629, n630, n631, n632, n633,
n634, n635, n636, n637, n638, n639, n640, n641, n642, n643, n644,
n645, n646, n647, n648, n649, n650, n651, n652, n653, n654, n655,
n656, n657, n658, n659, n660, n661, n662, n663, n664, n665, n666,
n667, n668, n669, n670, n671, n672, n673, n674, n675, n676, n677,
n678, n679, n680, n681, n682, n683, n684, n685, n686, n687, n688,
n689, n690, n691, n692, n693, n694, n695, n696, n697, n698, n699,
n700, n701, n702, n703, n704, n705, n706, n707, n708, n709, n710,
n711, n712, n713, n714, n715, n716, n717, n718, n719, n720, n721,
n722, n723, n724, n725, n726, n727, n728, n729, n730, n731, n732,
n733, n734, n735, n736, n737, n738, n739, n740, n741, n742, n743,
n744, n745, n746, n747, n748, n749, n750, n751, n752, n753, n754,
n755, n756, n757, n758, n759, n760, n761, n762, n763, n764, n765,
n766, n767, n768, n769, n770, n771, n772, n773, n774, n775, n776,
n777, n778, n779, n780, n781, n782, n783, n784, n785, n786, n787,
n788, n789, n790, n791, n792, n793, n794, n795, n796, n797, n798,
n799, n800, n801, n802, n803, n804, n805, n806, n807, n808, n809,
n810, n811, n812, n813, n814, n815, n816, n817, n818, n819, n820,
n821, n822, n823, n824, n825, n826, n827, n828, n829, n830, n831,
n832, n833, n834, n835, n836, n837, n838, n839, n840, n841, n842,
n843, n844, n845, n846, n847, n848, n849, n850, n851, n852, n853,
n854, n855, n856, n857, n858, n859, n860, n861, n862, n863, n864,
n865, n866, n867, n868, n869, n870, n871, n872, n873, n874, n875,
n876, n877, n878, n879, n880, n881, n882, n883, n884, n885, n886,
n887, n888, n889, n890, n891, n892, n893, n894, n895, n896, n897,
n898, n899, n900, n901, n902, n903, n904, n905, n906, n907, n908,
n909, n910, n911, n912, n913, n914, n915, n916, n917, n918, n919,
n920, n921, n922, n923, n924, n925, n926, n927, n928, n929, n930,
n931, n932, n933, n934, n935, n936, n937, n938, n939, n940, n941,
n942, n943, n944, n945, n946, n947, n948, n949, n950, n951, n952,
n953, n954, n955, n956, n957, n958, n959, n960, n961, n962, n963,
n964, n965, n966, n967, n968, n969, n970, n971, n972, n973, n974,
n975, n976, n977, n978, n979, n980, n981, n982, n983, n984, n985,
n986, n987, n988, n989, n990, n991, n992, n993, n994, n995, n996,
n997, n998, n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006,
n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016,
n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026,
n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036,
n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046,
n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056,
n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066,
n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076,
n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086,
n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096,
n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106,
n1107, n1108, n1109, n1110, n1112, n1113, n1114, n1115, n1116, n1117,
n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127,
n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137,
n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147,
n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157,
n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167,
n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177,
n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187,
n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197,
n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207,
n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217,
n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227,
n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237,
n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247,
n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257,
n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267,
n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277,
n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287,
n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297,
n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307,
n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317,
n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327,
n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337,
n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347,
n1348, n1349, n1350, n1352, n1353, n1354, n1355, n1356, n1357, n1358,
n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367, n1368,
n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377, n1378,
n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387, n1388,
n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1397, n1398, n1399,
n1400, n1401, n1402, n1404, n1405, n1406, n1407, n1408, n1409, n1410,
n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420,
n1421, n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430,
n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440,
n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450,
n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460,
n1461, n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470,
n1471, n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480,
n1481, n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490,
n1491, n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500,
n1501, n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510,
n1511, n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520,
n1521, n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530,
n1531, n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540,
n1541, n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550,
n1551, n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560,
n1561, n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570,
n1571, n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580,
n1581, n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590,
n1591, n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600,
n1601, n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610,
n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620,
n1621, n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630,
n1631, n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640,
n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650,
n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660,
n1661, n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670,
n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680,
n1681;
wire [47:0] P_Sgf;
wire [1:0] FSM_selector_B;
wire [31:0] Op_MX;
wire [31:0] Op_MY;
wire [8:0] exp_oper_result;
wire [8:0] S_Oper_A_exp;
wire [23:0] Add_result;
wire [23:0] Sgf_normalized_result;
wire [3:0] FS_Module_state_reg;
wire [8:0] Exp_module_Data_S;
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n381), .CK(clk), .RN(
n395), .Q(Op_MY[31]) );
DFFRXLTS Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n311), .CK(clk),
.RN(n1678), .Q(zero_flag), .QN(n474) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n374), .CK(clk), .RN(
n1676), .QN(n414) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n373), .CK(clk), .RN(
n1676), .QN(n402) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_17_ ( .D(n361), .CK(clk), .RN(
n1674), .QN(n479) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_1_ ( .D(n345), .CK(clk), .RN(
n1677), .QN(n404) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n343), .CK(clk), .RN(
n1675), .Q(Op_MX[31]) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n287), .CK(clk), .RN(n1677),
.QN(n423) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n288), .CK(clk), .RN(n1675),
.QN(n432) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n289), .CK(clk), .RN(n1674),
.QN(n422) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n290), .CK(clk), .RN(n395),
.QN(n431) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n291), .CK(clk), .RN(n393),
.QN(n421) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n292), .CK(clk), .RN(n392),
.QN(n430) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n293), .CK(clk), .RN(n393),
.QN(n420) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n294), .CK(clk), .RN(n395),
.QN(n429) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n295), .CK(clk), .RN(n393),
.QN(n419) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n296), .CK(clk), .RN(n1678),
.QN(n428) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n297), .CK(clk), .RN(n1676),
.QN(n418) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n298), .CK(clk), .RN(n392),
.QN(n427) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n299), .CK(clk), .RN(n395),
.QN(n417) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n300), .CK(clk), .RN(n1678),
.QN(n426) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n301), .CK(clk), .RN(n395),
.QN(n416) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n302), .CK(clk), .RN(n1676),
.QN(n425) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n303), .CK(clk), .RN(n393),
.QN(n415) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n304), .CK(clk), .RN(n392),
.QN(n435) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n305), .CK(clk), .RN(n395),
.QN(n433) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n306), .CK(clk), .RN(n1677),
.QN(n434) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n308), .CK(clk), .RN(n1675),
.QN(n424) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n309), .CK(clk), .RN(n1674),
.Q(Add_result[0]) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n286), .CK(clk), .RN(n395),
.Q(Add_result[23]) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n342), .CK(clk), .RN(
n392), .QN(n412) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n341), .CK(clk), .RN(
n392), .QN(n413) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n340), .CK(clk), .RN(
n393), .QN(n401) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n338), .CK(clk), .RN(
n1678), .QN(n398) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n337), .CK(clk), .RN(
n1676), .QN(n400) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n336), .CK(clk), .RN(
n395), .QN(n397) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_46_ ( .D(n284), .CK(clk), .RN(n1679),
.Q(P_Sgf[46]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_45_ ( .D(n283), .CK(clk), .RN(n1680),
.Q(P_Sgf[45]), .QN(n1657) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_44_ ( .D(n282), .CK(clk), .RN(n167),
.Q(P_Sgf[44]), .QN(n1651) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_43_ ( .D(n281), .CK(clk), .RN(n1679),
.Q(P_Sgf[43]), .QN(n1658) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_42_ ( .D(n280), .CK(clk), .RN(n1680),
.Q(P_Sgf[42]), .QN(n1659) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_41_ ( .D(n279), .CK(clk), .RN(n167),
.Q(P_Sgf[41]), .QN(n1660) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_40_ ( .D(n278), .CK(clk), .RN(n1679),
.Q(P_Sgf[40]), .QN(n1661) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_39_ ( .D(n277), .CK(clk), .RN(n1680),
.Q(P_Sgf[39]), .QN(n1662) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_38_ ( .D(n276), .CK(clk), .RN(n167),
.Q(P_Sgf[38]), .QN(n1663) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_37_ ( .D(n275), .CK(clk), .RN(n1679),
.Q(P_Sgf[37]), .QN(n1664) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_36_ ( .D(n274), .CK(clk), .RN(n1680),
.Q(P_Sgf[36]), .QN(n1665) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_35_ ( .D(n273), .CK(clk), .RN(n167),
.Q(P_Sgf[35]), .QN(n1666) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_34_ ( .D(n272), .CK(clk), .RN(n1679),
.Q(P_Sgf[34]), .QN(n1667) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_33_ ( .D(n271), .CK(clk), .RN(n1680),
.Q(P_Sgf[33]), .QN(n1668) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_32_ ( .D(n270), .CK(clk), .RN(n167),
.Q(P_Sgf[32]), .QN(n1669) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_31_ ( .D(n269), .CK(clk), .RN(n1679),
.Q(P_Sgf[31]), .QN(n1670) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_30_ ( .D(n268), .CK(clk), .RN(n1680),
.Q(P_Sgf[30]), .QN(n1671) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_29_ ( .D(n267), .CK(clk), .RN(n167),
.Q(P_Sgf[29]), .QN(n1672) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_28_ ( .D(n266), .CK(clk), .RN(n1679),
.Q(P_Sgf[28]), .QN(n1652) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_27_ ( .D(n265), .CK(clk), .RN(n1680),
.Q(P_Sgf[27]), .QN(n1653) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_26_ ( .D(n264), .CK(clk), .RN(n167),
.Q(P_Sgf[26]), .QN(n1654) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_25_ ( .D(n263), .CK(clk), .RN(n1679),
.Q(P_Sgf[25]), .QN(n1655) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_24_ ( .D(n262), .CK(clk), .RN(n1680),
.Q(P_Sgf[24]), .QN(n1656) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_23_ ( .D(n261), .CK(clk), .RN(n167),
.Q(P_Sgf[23]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_22_ ( .D(n260), .CK(clk), .RN(n1679),
.Q(P_Sgf[22]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_21_ ( .D(n259), .CK(clk), .RN(n1680),
.Q(P_Sgf[21]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_20_ ( .D(n258), .CK(clk), .RN(n167),
.Q(P_Sgf[20]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_19_ ( .D(n257), .CK(clk), .RN(n1679),
.Q(P_Sgf[19]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_18_ ( .D(n256), .CK(clk), .RN(n1680),
.Q(P_Sgf[18]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_17_ ( .D(n255), .CK(clk), .RN(n167),
.Q(P_Sgf[17]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_16_ ( .D(n254), .CK(clk), .RN(n1679),
.Q(P_Sgf[16]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_15_ ( .D(n253), .CK(clk), .RN(n1680),
.Q(P_Sgf[15]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_14_ ( .D(n252), .CK(clk), .RN(n167),
.Q(P_Sgf[14]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_13_ ( .D(n251), .CK(clk), .RN(n1679),
.Q(P_Sgf[13]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_12_ ( .D(n250), .CK(clk), .RN(n1681),
.Q(P_Sgf[12]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_11_ ( .D(n249), .CK(clk), .RN(n1681),
.Q(P_Sgf[11]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_10_ ( .D(n248), .CK(clk), .RN(n1681),
.Q(P_Sgf[10]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_8_ ( .D(n246), .CK(clk), .RN(n1681),
.Q(P_Sgf[8]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_7_ ( .D(n245), .CK(clk), .RN(n1681),
.Q(P_Sgf[7]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_6_ ( .D(n244), .CK(clk), .RN(n1681),
.Q(P_Sgf[6]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_5_ ( .D(n243), .CK(clk), .RN(n1681),
.Q(P_Sgf[5]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_4_ ( .D(n242), .CK(clk), .RN(n1681),
.Q(P_Sgf[4]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_3_ ( .D(n241), .CK(clk), .RN(n1681),
.Q(P_Sgf[3]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_2_ ( .D(n240), .CK(clk), .RN(n1681),
.Q(P_Sgf[2]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_1_ ( .D(n239), .CK(clk), .RN(n167),
.Q(P_Sgf[1]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_0_ ( .D(n238), .CK(clk), .RN(n167),
.Q(P_Sgf[0]) );
DFFRXLTS Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n225), .CK(clk), .RN(n395), .Q(
Exp_module_Overflow_flag_A) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n204), .CK(clk),
.RN(n1678), .QN(n399) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n203), .CK(clk),
.RN(n1676), .QN(n410) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n200),
.CK(clk), .RN(n392), .Q(final_result_ieee[0]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n199),
.CK(clk), .RN(n1675), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n198),
.CK(clk), .RN(n1674), .Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n197),
.CK(clk), .RN(n1677), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n196),
.CK(clk), .RN(n395), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n195),
.CK(clk), .RN(n392), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n194),
.CK(clk), .RN(n392), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n193),
.CK(clk), .RN(n393), .Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n192),
.CK(clk), .RN(n1678), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n191),
.CK(clk), .RN(n1676), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n190),
.CK(clk), .RN(n1677), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n189),
.CK(clk), .RN(n1675), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n188),
.CK(clk), .RN(n1674), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n187),
.CK(clk), .RN(n391), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n186),
.CK(clk), .RN(n391), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n185),
.CK(clk), .RN(n391), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n184),
.CK(clk), .RN(n391), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n183),
.CK(clk), .RN(n391), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n182),
.CK(clk), .RN(n391), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n181),
.CK(clk), .RN(n391), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n180),
.CK(clk), .RN(n391), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n179),
.CK(clk), .RN(n393), .Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n178),
.CK(clk), .RN(n392), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n177),
.CK(clk), .RN(n393), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n176),
.CK(clk), .RN(n1678), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n175),
.CK(clk), .RN(n392), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n174),
.CK(clk), .RN(n393), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n173),
.CK(clk), .RN(n1678), .Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n172),
.CK(clk), .RN(n1676), .Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n171),
.CK(clk), .RN(n395), .Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n170),
.CK(clk), .RN(n393), .Q(final_result_ieee[30]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n168),
.CK(clk), .RN(n392), .Q(final_result_ieee[31]), .QN(n1673) );
CMPR32X2TS DP_OP_32J15_122_6543_U9 ( .A(DP_OP_32J15_122_6543_n21), .B(
S_Oper_A_exp[1]), .C(DP_OP_32J15_122_6543_n9), .CO(
DP_OP_32J15_122_6543_n8), .S(Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_32J15_122_6543_U8 ( .A(DP_OP_32J15_122_6543_n20), .B(
S_Oper_A_exp[2]), .C(DP_OP_32J15_122_6543_n8), .CO(
DP_OP_32J15_122_6543_n7), .S(Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_32J15_122_6543_U7 ( .A(DP_OP_32J15_122_6543_n19), .B(
S_Oper_A_exp[3]), .C(DP_OP_32J15_122_6543_n7), .CO(
DP_OP_32J15_122_6543_n6), .S(Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_32J15_122_6543_U6 ( .A(DP_OP_32J15_122_6543_n18), .B(
S_Oper_A_exp[4]), .C(DP_OP_32J15_122_6543_n6), .CO(
DP_OP_32J15_122_6543_n5), .S(Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_32J15_122_6543_U5 ( .A(DP_OP_32J15_122_6543_n17), .B(
S_Oper_A_exp[5]), .C(DP_OP_32J15_122_6543_n5), .CO(
DP_OP_32J15_122_6543_n4), .S(Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_32J15_122_6543_U4 ( .A(DP_OP_32J15_122_6543_n16), .B(
S_Oper_A_exp[6]), .C(DP_OP_32J15_122_6543_n4), .CO(
DP_OP_32J15_122_6543_n3), .S(Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_32J15_122_6543_U3 ( .A(DP_OP_32J15_122_6543_n15), .B(
S_Oper_A_exp[7]), .C(DP_OP_32J15_122_6543_n3), .CO(
DP_OP_32J15_122_6543_n2), .S(Exp_module_Data_S[7]) );
CMPR32X2TS DP_OP_32J15_122_6543_U2 ( .A(DP_OP_32J15_122_6543_n33), .B(
S_Oper_A_exp[8]), .C(DP_OP_32J15_122_6543_n2), .CO(
DP_OP_32J15_122_6543_n1), .S(Exp_module_Data_S[8]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n307), .CK(clk), .RN(n1677),
.Q(Add_result[2]), .QN(n1649) );
DFFRX1TS Exp_module_Underflow_m_Q_reg_0_ ( .D(n201), .CK(clk), .RN(n1675),
.Q(underflow_flag), .QN(n1648) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n224), .CK(clk),
.RN(n1675), .Q(Sgf_normalized_result[22]), .QN(n1646) );
DFFRX2TS FS_Module_state_reg_reg_0_ ( .D(n379), .CK(clk), .RN(n1679), .Q(
FS_Module_state_reg[0]), .QN(n1645) );
DFFRX1TS Sel_C_Q_reg_0_ ( .D(n375), .CK(clk), .RN(n1678), .Q(FSM_selector_C),
.QN(n1644) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n222), .CK(clk),
.RN(n1678), .Q(Sgf_normalized_result[20]), .QN(n1643) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n220), .CK(clk),
.RN(n1676), .Q(Sgf_normalized_result[18]), .QN(n1642) );
DFFRX2TS Sel_B_Q_reg_1_ ( .D(n235), .CK(clk), .RN(n1677), .Q(
FSM_selector_B[1]), .QN(n1641) );
DFFRX1TS Sel_B_Q_reg_0_ ( .D(n236), .CK(clk), .RN(n393), .Q(
FSM_selector_B[0]), .QN(n1640) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n218), .CK(clk),
.RN(n395), .Q(Sgf_normalized_result[16]), .QN(n1639) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n216), .CK(clk),
.RN(n393), .Q(Sgf_normalized_result[14]), .QN(n1638) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n214), .CK(clk),
.RN(n1676), .Q(Sgf_normalized_result[12]), .QN(n1637) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n212), .CK(clk),
.RN(n392), .Q(Sgf_normalized_result[10]), .QN(n1636) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n210), .CK(clk),
.RN(n1677), .Q(Sgf_normalized_result[8]), .QN(n1635) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n206), .CK(clk),
.RN(n392), .Q(Sgf_normalized_result[4]), .QN(n1633) );
DFFRX2TS FS_Module_state_reg_reg_2_ ( .D(n377), .CK(clk), .RN(n1679), .Q(
FS_Module_state_reg[2]), .QN(n1632) );
CMPR42X1TS mult_x_19_U292 ( .A(mult_x_19_n471), .B(mult_x_19_n747), .C(
mult_x_19_n474), .D(mult_x_19_n771), .ICI(mult_x_19_n472), .S(
mult_x_19_n469), .ICO(mult_x_19_n467), .CO(mult_x_19_n468) );
CMPR42X1TS mult_x_19_U290 ( .A(mult_x_19_n746), .B(mult_x_19_n466), .C(
mult_x_19_n467), .D(mult_x_19_n770), .ICI(mult_x_19_n468), .S(
mult_x_19_n464), .ICO(mult_x_19_n462), .CO(mult_x_19_n463) );
CMPR42X1TS mult_x_19_U288 ( .A(mult_x_19_n745), .B(mult_x_19_n461), .C(
mult_x_19_n462), .D(mult_x_19_n769), .ICI(mult_x_19_n463), .S(
mult_x_19_n459), .ICO(mult_x_19_n457), .CO(mult_x_19_n458) );
CMPR42X1TS mult_x_19_U285 ( .A(mult_x_19_n744), .B(mult_x_19_n454), .C(
mult_x_19_n457), .D(mult_x_19_n768), .ICI(mult_x_19_n458), .S(
mult_x_19_n452), .ICO(mult_x_19_n450), .CO(mult_x_19_n451) );
CMPR42X1TS mult_x_19_U282 ( .A(mult_x_19_n743), .B(mult_x_19_n447), .C(
mult_x_19_n450), .D(mult_x_19_n767), .ICI(mult_x_19_n451), .S(
mult_x_19_n445), .ICO(mult_x_19_n443), .CO(mult_x_19_n444) );
CMPR42X1TS mult_x_19_U279 ( .A(mult_x_19_n742), .B(mult_x_19_n440), .C(
mult_x_19_n443), .D(mult_x_19_n766), .ICI(mult_x_19_n444), .S(
mult_x_19_n438), .ICO(mult_x_19_n436), .CO(mult_x_19_n437) );
CMPR42X1TS mult_x_19_U277 ( .A(mult_x_19_n435), .B(mult_x_19_n693), .C(
mult_x_19_n441), .D(mult_x_19_n717), .ICI(mult_x_19_n439), .S(
mult_x_19_n433), .ICO(mult_x_19_n431), .CO(mult_x_19_n432) );
CMPR42X1TS mult_x_19_U276 ( .A(mult_x_19_n741), .B(mult_x_19_n433), .C(
mult_x_19_n436), .D(mult_x_19_n765), .ICI(mult_x_19_n437), .S(
mult_x_19_n430), .ICO(mult_x_19_n428), .CO(mult_x_19_n429) );
CMPR42X1TS mult_x_19_U274 ( .A(mult_x_19_n692), .B(mult_x_19_n427), .C(
mult_x_19_n431), .D(mult_x_19_n716), .ICI(mult_x_19_n432), .S(
mult_x_19_n425), .ICO(mult_x_19_n423), .CO(mult_x_19_n424) );
CMPR42X1TS mult_x_19_U273 ( .A(mult_x_19_n740), .B(mult_x_19_n425), .C(
mult_x_19_n428), .D(mult_x_19_n764), .ICI(mult_x_19_n429), .S(
mult_x_19_n422), .ICO(mult_x_19_n420), .CO(mult_x_19_n421) );
CMPR42X1TS mult_x_19_U271 ( .A(mult_x_19_n691), .B(mult_x_19_n419), .C(
mult_x_19_n423), .D(mult_x_19_n715), .ICI(mult_x_19_n424), .S(
mult_x_19_n417), .ICO(mult_x_19_n415), .CO(mult_x_19_n416) );
CMPR42X1TS mult_x_19_U270 ( .A(mult_x_19_n739), .B(mult_x_19_n417), .C(
mult_x_19_n420), .D(mult_x_19_n763), .ICI(mult_x_19_n421), .S(
mult_x_19_n414), .ICO(mult_x_19_n412), .CO(mult_x_19_n413) );
CMPR42X1TS mult_x_19_U267 ( .A(mult_x_19_n690), .B(mult_x_19_n409), .C(
mult_x_19_n415), .D(mult_x_19_n714), .ICI(mult_x_19_n416), .S(
mult_x_19_n407), .ICO(mult_x_19_n405), .CO(mult_x_19_n406) );
CMPR42X1TS mult_x_19_U266 ( .A(mult_x_19_n738), .B(mult_x_19_n407), .C(
mult_x_19_n412), .D(mult_x_19_n762), .ICI(mult_x_19_n413), .S(
mult_x_19_n404), .ICO(mult_x_19_n402), .CO(mult_x_19_n403) );
CMPR42X1TS mult_x_19_U263 ( .A(mult_x_19_n689), .B(mult_x_19_n399), .C(
mult_x_19_n405), .D(mult_x_19_n713), .ICI(mult_x_19_n406), .S(
mult_x_19_n397), .ICO(mult_x_19_n395), .CO(mult_x_19_n396) );
CMPR42X1TS mult_x_19_U262 ( .A(mult_x_19_n397), .B(mult_x_19_n737), .C(
mult_x_19_n402), .D(mult_x_19_n761), .ICI(mult_x_19_n403), .S(
mult_x_19_n394), .ICO(mult_x_19_n392), .CO(mult_x_19_n393) );
CMPR42X1TS mult_x_19_U259 ( .A(mult_x_19_n688), .B(mult_x_19_n389), .C(
mult_x_19_n395), .D(mult_x_19_n712), .ICI(mult_x_19_n396), .S(
mult_x_19_n387), .ICO(mult_x_19_n385), .CO(mult_x_19_n386) );
CMPR42X1TS mult_x_19_U258 ( .A(mult_x_19_n387), .B(mult_x_19_n736), .C(
mult_x_19_n392), .D(mult_x_19_n760), .ICI(mult_x_19_n393), .S(
mult_x_19_n384), .ICO(mult_x_19_n382), .CO(mult_x_19_n383) );
CMPR42X1TS mult_x_19_U256 ( .A(mult_x_19_n381), .B(mult_x_19_n639), .C(
mult_x_19_n390), .D(mult_x_19_n663), .ICI(mult_x_19_n388), .S(
mult_x_19_n379), .ICO(mult_x_19_n377), .CO(mult_x_19_n378) );
CMPR42X1TS mult_x_19_U255 ( .A(mult_x_19_n687), .B(mult_x_19_n379), .C(
mult_x_19_n385), .D(mult_x_19_n711), .ICI(mult_x_19_n386), .S(
mult_x_19_n376), .ICO(mult_x_19_n374), .CO(mult_x_19_n375) );
CMPR42X1TS mult_x_19_U254 ( .A(mult_x_19_n376), .B(mult_x_19_n735), .C(
mult_x_19_n382), .D(mult_x_19_n759), .ICI(mult_x_19_n383), .S(
mult_x_19_n373), .ICO(mult_x_19_n371), .CO(mult_x_19_n372) );
CMPR42X1TS mult_x_19_U252 ( .A(mult_x_19_n370), .B(mult_x_19_n638), .C(
mult_x_19_n377), .D(mult_x_19_n662), .ICI(mult_x_19_n378), .S(
mult_x_19_n368), .ICO(mult_x_19_n366), .CO(mult_x_19_n367) );
CMPR42X1TS mult_x_19_U251 ( .A(mult_x_19_n686), .B(mult_x_19_n368), .C(
mult_x_19_n374), .D(mult_x_19_n710), .ICI(mult_x_19_n375), .S(
mult_x_19_n365), .ICO(mult_x_19_n363), .CO(mult_x_19_n364) );
CMPR42X1TS mult_x_19_U250 ( .A(mult_x_19_n365), .B(mult_x_19_n734), .C(
mult_x_19_n371), .D(mult_x_19_n758), .ICI(mult_x_19_n372), .S(
mult_x_19_n362), .ICO(mult_x_19_n360), .CO(mult_x_19_n361) );
CMPR42X1TS mult_x_19_U248 ( .A(mult_x_19_n359), .B(mult_x_19_n637), .C(
mult_x_19_n366), .D(mult_x_19_n661), .ICI(mult_x_19_n367), .S(
mult_x_19_n357), .ICO(mult_x_19_n355), .CO(mult_x_19_n356) );
CMPR42X1TS mult_x_19_U247 ( .A(mult_x_19_n685), .B(mult_x_19_n357), .C(
mult_x_19_n363), .D(mult_x_19_n709), .ICI(mult_x_19_n364), .S(
mult_x_19_n354), .ICO(mult_x_19_n352), .CO(mult_x_19_n353) );
CMPR42X1TS mult_x_19_U246 ( .A(mult_x_19_n354), .B(mult_x_19_n733), .C(
mult_x_19_n360), .D(mult_x_19_n757), .ICI(mult_x_19_n361), .S(
mult_x_19_n351), .ICO(mult_x_19_n349), .CO(mult_x_19_n350) );
CMPR42X1TS mult_x_19_U244 ( .A(mult_x_19_n348), .B(mult_x_19_n636), .C(
mult_x_19_n355), .D(mult_x_19_n660), .ICI(mult_x_19_n356), .S(
mult_x_19_n346), .ICO(mult_x_19_n344), .CO(mult_x_19_n345) );
CMPR42X1TS mult_x_19_U243 ( .A(mult_x_19_n684), .B(mult_x_19_n346), .C(
mult_x_19_n352), .D(mult_x_19_n708), .ICI(mult_x_19_n353), .S(
mult_x_19_n343), .ICO(mult_x_19_n341), .CO(mult_x_19_n342) );
CMPR42X1TS mult_x_19_U242 ( .A(mult_x_19_n343), .B(mult_x_19_n732), .C(
mult_x_19_n349), .D(mult_x_19_n756), .ICI(mult_x_19_n350), .S(
mult_x_19_n340), .ICO(mult_x_19_n338), .CO(mult_x_19_n339) );
CMPR42X1TS mult_x_19_U240 ( .A(mult_x_19_n337), .B(mult_x_19_n635), .C(
mult_x_19_n344), .D(mult_x_19_n659), .ICI(mult_x_19_n345), .S(
mult_x_19_n335), .ICO(mult_x_19_n333), .CO(mult_x_19_n334) );
CMPR42X1TS mult_x_19_U239 ( .A(mult_x_19_n335), .B(mult_x_19_n683), .C(
mult_x_19_n341), .D(mult_x_19_n707), .ICI(mult_x_19_n342), .S(
mult_x_19_n332), .ICO(mult_x_19_n330), .CO(mult_x_19_n331) );
CMPR42X1TS mult_x_19_U238 ( .A(mult_x_19_n332), .B(mult_x_19_n731), .C(
mult_x_19_n338), .D(mult_x_19_n755), .ICI(mult_x_19_n779), .S(
mult_x_19_n329), .ICO(mult_x_19_n327), .CO(mult_x_19_n328) );
CMPR42X1TS mult_x_19_U236 ( .A(mult_x_19_n326), .B(mult_x_19_n336), .C(
mult_x_19_n634), .D(mult_x_19_n333), .ICI(mult_x_19_n658), .S(
mult_x_19_n324), .ICO(mult_x_19_n322), .CO(mult_x_19_n323) );
CMPR42X1TS mult_x_19_U235 ( .A(mult_x_19_n324), .B(mult_x_19_n334), .C(
mult_x_19_n682), .D(mult_x_19_n330), .ICI(mult_x_19_n706), .S(
mult_x_19_n321), .ICO(mult_x_19_n319), .CO(mult_x_19_n320) );
CMPR42X1TS mult_x_19_U234 ( .A(mult_x_19_n331), .B(mult_x_19_n321), .C(
mult_x_19_n730), .D(mult_x_19_n327), .ICI(mult_x_19_n328), .S(
mult_x_19_n318), .ICO(mult_x_19_n316), .CO(mult_x_19_n317) );
CMPR42X1TS mult_x_19_U232 ( .A(mult_x_19_n325), .B(mult_x_19_n315), .C(
mult_x_19_n322), .D(mult_x_19_n633), .ICI(mult_x_19_n323), .S(
mult_x_19_n313), .ICO(mult_x_19_n311), .CO(mult_x_19_n312) );
CMPR42X1TS mult_x_19_U231 ( .A(mult_x_19_n657), .B(mult_x_19_n313), .C(
mult_x_19_n319), .D(mult_x_19_n681), .ICI(mult_x_19_n320), .S(
mult_x_19_n310), .ICO(mult_x_19_n308), .CO(mult_x_19_n309) );
CMPR42X1TS mult_x_19_U230 ( .A(mult_x_19_n705), .B(mult_x_19_n310), .C(
mult_x_19_n316), .D(mult_x_19_n729), .ICI(mult_x_19_n753), .S(
mult_x_19_n307), .ICO(mult_x_19_n305), .CO(mult_x_19_n306) );
CMPR42X1TS mult_x_19_U228 ( .A(mult_x_19_n314), .B(mult_x_19_n304), .C(
mult_x_19_n311), .D(mult_x_19_n632), .ICI(mult_x_19_n312), .S(
mult_x_19_n302), .ICO(mult_x_19_n300), .CO(mult_x_19_n301) );
CMPR42X1TS mult_x_19_U227 ( .A(mult_x_19_n656), .B(mult_x_19_n302), .C(
mult_x_19_n308), .D(mult_x_19_n680), .ICI(mult_x_19_n309), .S(
mult_x_19_n299), .ICO(mult_x_19_n297), .CO(mult_x_19_n298) );
CMPR42X1TS mult_x_19_U226 ( .A(mult_x_19_n704), .B(mult_x_19_n299), .C(
mult_x_19_n305), .D(mult_x_19_n728), .ICI(mult_x_19_n752), .S(
mult_x_19_n296), .ICO(mult_x_19_n294), .CO(mult_x_19_n295) );
CMPR42X1TS mult_x_19_U224 ( .A(mult_x_19_n293), .B(mult_x_19_n608), .C(
mult_x_19_n303), .D(mult_x_19_n300), .ICI(mult_x_19_n631), .S(
mult_x_19_n291), .ICO(mult_x_19_n289), .CO(mult_x_19_n290) );
CMPR42X1TS mult_x_19_U223 ( .A(mult_x_19_n291), .B(mult_x_19_n301), .C(
mult_x_19_n655), .D(mult_x_19_n297), .ICI(mult_x_19_n679), .S(
mult_x_19_n288), .ICO(mult_x_19_n286), .CO(mult_x_19_n287) );
CMPR42X1TS mult_x_19_U222 ( .A(mult_x_19_n288), .B(mult_x_19_n298), .C(
mult_x_19_n703), .D(mult_x_19_n294), .ICI(mult_x_19_n295), .S(
mult_x_19_n285), .ICO(mult_x_19_n283), .CO(mult_x_19_n284) );
CMPR42X1TS mult_x_19_U220 ( .A(mult_x_19_n282), .B(mult_x_19_n292), .C(
mult_x_19_n289), .D(mult_x_19_n607), .ICI(mult_x_19_n630), .S(
mult_x_19_n281), .ICO(mult_x_19_n279), .CO(mult_x_19_n280) );
CMPR42X1TS mult_x_19_U219 ( .A(mult_x_19_n290), .B(mult_x_19_n281), .C(
mult_x_19_n286), .D(mult_x_19_n654), .ICI(mult_x_19_n678), .S(
mult_x_19_n278), .ICO(mult_x_19_n276), .CO(mult_x_19_n277) );
CMPR42X1TS mult_x_19_U218 ( .A(mult_x_19_n287), .B(mult_x_19_n278), .C(
mult_x_19_n283), .D(mult_x_19_n702), .ICI(mult_x_19_n726), .S(
mult_x_19_n275), .ICO(mult_x_19_n273), .CO(mult_x_19_n274) );
CMPR42X1TS mult_x_19_U216 ( .A(Op_MY[6]), .B(mult_x_19_n272), .C(
mult_x_19_n279), .D(mult_x_19_n606), .ICI(mult_x_19_n280), .S(
mult_x_19_n271), .ICO(mult_x_19_n269), .CO(mult_x_19_n270) );
CMPR42X1TS mult_x_19_U215 ( .A(mult_x_19_n629), .B(mult_x_19_n271), .C(
mult_x_19_n276), .D(mult_x_19_n653), .ICI(mult_x_19_n277), .S(
mult_x_19_n268), .ICO(mult_x_19_n266), .CO(mult_x_19_n267) );
CMPR42X1TS mult_x_19_U214 ( .A(mult_x_19_n677), .B(mult_x_19_n268), .C(
mult_x_19_n273), .D(mult_x_19_n701), .ICI(mult_x_19_n725), .S(
mult_x_19_n265), .ICO(mult_x_19_n263), .CO(mult_x_19_n264) );
CMPR42X1TS mult_x_19_U213 ( .A(n1631), .B(Op_MY[8]), .C(Op_MY[7]), .D(
mult_x_19_n269), .ICI(mult_x_19_n605), .S(mult_x_19_n262), .ICO(
mult_x_19_n260), .CO(mult_x_19_n261) );
CMPR42X1TS mult_x_19_U212 ( .A(mult_x_19_n262), .B(mult_x_19_n270), .C(
mult_x_19_n628), .D(mult_x_19_n266), .ICI(mult_x_19_n652), .S(
mult_x_19_n259), .ICO(mult_x_19_n257), .CO(mult_x_19_n258) );
CMPR42X1TS mult_x_19_U211 ( .A(mult_x_19_n259), .B(mult_x_19_n267), .C(
mult_x_19_n676), .D(mult_x_19_n263), .ICI(mult_x_19_n264), .S(
mult_x_19_n256), .ICO(mult_x_19_n254), .CO(mult_x_19_n255) );
CMPR42X1TS mult_x_19_U208 ( .A(mult_x_19_n261), .B(mult_x_19_n252), .C(
mult_x_19_n257), .D(mult_x_19_n627), .ICI(mult_x_19_n651), .S(
mult_x_19_n250), .ICO(mult_x_19_n248), .CO(mult_x_19_n249) );
CMPR42X1TS mult_x_19_U207 ( .A(mult_x_19_n258), .B(mult_x_19_n250), .C(
mult_x_19_n254), .D(mult_x_19_n675), .ICI(mult_x_19_n699), .S(
mult_x_19_n247), .ICO(mult_x_19_n245), .CO(mult_x_19_n246) );
CMPR42X1TS mult_x_19_U204 ( .A(mult_x_19_n251), .B(mult_x_19_n243), .C(
mult_x_19_n248), .D(mult_x_19_n626), .ICI(mult_x_19_n249), .S(
mult_x_19_n241), .ICO(mult_x_19_n239), .CO(mult_x_19_n240) );
CMPR42X1TS mult_x_19_U203 ( .A(mult_x_19_n650), .B(mult_x_19_n241), .C(
mult_x_19_n245), .D(mult_x_19_n674), .ICI(mult_x_19_n698), .S(
mult_x_19_n238), .ICO(mult_x_19_n236), .CO(mult_x_19_n237) );
CMPR42X1TS mult_x_19_U201 ( .A(mult_x_19_n235), .B(mult_x_19_n242), .C(
mult_x_19_n602), .D(mult_x_19_n239), .ICI(mult_x_19_n625), .S(
mult_x_19_n233), .ICO(mult_x_19_n231), .CO(mult_x_19_n232) );
CMPR42X1TS mult_x_19_U200 ( .A(mult_x_19_n233), .B(mult_x_19_n240), .C(
mult_x_19_n649), .D(mult_x_19_n236), .ICI(mult_x_19_n237), .S(
mult_x_19_n230), .ICO(mult_x_19_n228), .CO(mult_x_19_n229) );
CMPR42X1TS mult_x_19_U198 ( .A(mult_x_19_n227), .B(mult_x_19_n234), .C(
mult_x_19_n231), .D(mult_x_19_n601), .ICI(mult_x_19_n624), .S(
mult_x_19_n226), .ICO(mult_x_19_n224), .CO(mult_x_19_n225) );
CMPR42X1TS mult_x_19_U197 ( .A(mult_x_19_n232), .B(mult_x_19_n226), .C(
mult_x_19_n228), .D(mult_x_19_n648), .ICI(mult_x_19_n672), .S(
mult_x_19_n223), .ICO(mult_x_19_n221), .CO(mult_x_19_n222) );
CMPR42X1TS mult_x_19_U195 ( .A(Op_MY[12]), .B(mult_x_19_n220), .C(
mult_x_19_n224), .D(mult_x_19_n600), .ICI(mult_x_19_n225), .S(
mult_x_19_n219), .ICO(mult_x_19_n217), .CO(mult_x_19_n218) );
CMPR42X1TS mult_x_19_U194 ( .A(mult_x_19_n623), .B(mult_x_19_n219), .C(
mult_x_19_n221), .D(mult_x_19_n647), .ICI(mult_x_19_n671), .S(
mult_x_19_n216), .ICO(mult_x_19_n214), .CO(mult_x_19_n215) );
CMPR42X1TS mult_x_19_U193 ( .A(n1630), .B(Op_MY[13]), .C(Op_MY[14]), .D(
mult_x_19_n217), .ICI(mult_x_19_n599), .S(mult_x_19_n213), .ICO(
mult_x_19_n211), .CO(mult_x_19_n212) );
CMPR42X1TS mult_x_19_U192 ( .A(mult_x_19_n213), .B(mult_x_19_n218), .C(
mult_x_19_n622), .D(mult_x_19_n214), .ICI(mult_x_19_n215), .S(
mult_x_19_n210), .ICO(mult_x_19_n208), .CO(mult_x_19_n209) );
CMPR42X1TS mult_x_19_U189 ( .A(mult_x_19_n212), .B(mult_x_19_n206), .C(
mult_x_19_n208), .D(mult_x_19_n621), .ICI(mult_x_19_n645), .S(
mult_x_19_n204), .ICO(mult_x_19_n202), .CO(mult_x_19_n203) );
CMPR42X1TS mult_x_19_U186 ( .A(mult_x_19_n597), .B(mult_x_19_n200), .C(
mult_x_19_n202), .D(mult_x_19_n620), .ICI(mult_x_19_n644), .S(
mult_x_19_n198), .ICO(mult_x_19_n196), .CO(mult_x_19_n197) );
CMPR42X1TS mult_x_19_U184 ( .A(mult_x_19_n195), .B(mult_x_19_n199), .C(
mult_x_19_n596), .D(mult_x_19_n196), .ICI(mult_x_19_n197), .S(
mult_x_19_n193), .ICO(mult_x_19_n191), .CO(mult_x_19_n192) );
CMPR42X1TS mult_x_19_U182 ( .A(n1628), .B(mult_x_19_n194), .C(mult_x_19_n191), .D(mult_x_19_n595), .ICI(mult_x_19_n618), .S(mult_x_19_n189), .ICO(
mult_x_19_n187), .CO(mult_x_19_n188) );
CMPR42X1TS mult_x_19_U180 ( .A(Op_MY[19]), .B(n1628), .C(mult_x_19_n187),
.D(mult_x_19_n594), .ICI(mult_x_19_n617), .S(mult_x_19_n185), .ICO(
mult_x_19_n183), .CO(mult_x_19_n184) );
CMPR42X1TS mult_x_19_U179 ( .A(n1629), .B(Op_MY[18]), .C(Op_MY[20]), .D(
mult_x_19_n183), .ICI(mult_x_19_n593), .S(mult_x_19_n182), .ICO(
mult_x_19_n180), .CO(mult_x_19_n181) );
DFFSX4TS Operands_load_reg_XMRegister_Q_reg_2_ ( .D(n411), .CK(clk), .SN(
n1676), .Q(mult_x_19_n778), .QN(Op_MX[2]) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n310), .CK(clk),
.RN(n395), .Q(Sgf_normalized_result[23]), .QN(n1650) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n208), .CK(clk),
.RN(n393), .Q(Sgf_normalized_result[6]), .QN(n1634) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n334), .CK(clk), .RN(
n437), .Q(Op_MY[22]), .QN(n408) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_1_ ( .D(n313), .CK(clk), .RN(
n1678), .Q(Op_MY[1]), .QN(n407) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n320), .CK(clk), .RN(
n1678), .Q(Op_MY[8]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_13_ ( .D(n325), .CK(clk), .RN(
n395), .Q(Op_MY[13]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_19_ ( .D(n331), .CK(clk), .RN(
n392), .Q(Op_MY[19]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_5_ ( .D(n317), .CK(clk), .RN(
n1674), .Q(Op_MY[5]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_17_ ( .D(n329), .CK(clk), .RN(
n393), .Q(Op_MY[17]) );
DFFRX2TS FS_Module_state_reg_reg_3_ ( .D(n380), .CK(clk), .RN(n1679), .Q(
FS_Module_state_reg[3]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_20_ ( .D(n364), .CK(clk), .RN(
n395), .Q(Op_MX[20]), .QN(n481) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_14_ ( .D(n358), .CK(clk), .RN(
n393), .Q(Op_MX[14]), .QN(n483) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n355), .CK(clk), .RN(
n392), .Q(Op_MX[11]), .QN(n478) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_8_ ( .D(n352), .CK(clk), .RN(
n1674), .Q(Op_MX[8]), .QN(n482) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n202), .CK(clk),
.RN(n437), .Q(Sgf_normalized_result[0]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_0_ ( .D(n344), .CK(clk), .RN(
n1675), .Q(Op_MX[0]), .QN(n406) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_5_ ( .D(n349), .CK(clk), .RN(
n1677), .Q(Op_MX[5]), .QN(n484) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_22_ ( .D(n366), .CK(clk), .RN(
n1676), .Q(Op_MX[22]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n321), .CK(clk), .RN(
n395), .Q(Op_MY[9]), .QN(n475) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_16_ ( .D(n328), .CK(clk), .RN(
n437), .Q(Op_MY[16]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n205), .CK(clk),
.RN(n1676), .Q(Sgf_normalized_result[3]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n207), .CK(clk),
.RN(n1678), .Q(Sgf_normalized_result[5]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n209), .CK(clk),
.RN(n393), .Q(Sgf_normalized_result[7]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n211), .CK(clk),
.RN(n395), .Q(Sgf_normalized_result[9]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n213), .CK(clk),
.RN(n391), .Q(Sgf_normalized_result[11]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n215), .CK(clk),
.RN(n395), .Q(Sgf_normalized_result[13]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n217), .CK(clk),
.RN(n393), .Q(Sgf_normalized_result[15]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n219), .CK(clk),
.RN(n392), .Q(Sgf_normalized_result[17]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n221), .CK(clk),
.RN(n1677), .Q(Sgf_normalized_result[19]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n223), .CK(clk),
.RN(n1674), .Q(Sgf_normalized_result[21]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_47_ ( .D(n237), .CK(clk), .RN(n167),
.Q(P_Sgf[47]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_7_ ( .D(n227), .CK(clk), .RN(n392),
.Q(exp_oper_result[7]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_6_ ( .D(n228), .CK(clk), .RN(n393),
.Q(exp_oper_result[6]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_5_ ( .D(n229), .CK(clk), .RN(n395),
.Q(exp_oper_result[5]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_4_ ( .D(n230), .CK(clk), .RN(n1676),
.Q(exp_oper_result[4]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_3_ ( .D(n231), .CK(clk), .RN(n1678),
.Q(exp_oper_result[3]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_2_ ( .D(n232), .CK(clk), .RN(n391),
.Q(exp_oper_result[2]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_1_ ( .D(n233), .CK(clk), .RN(n395),
.Q(exp_oper_result[1]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_0_ ( .D(n234), .CK(clk), .RN(n393),
.Q(exp_oper_result[0]) );
DFFRX1TS Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n285), .CK(clk), .RN(n395), .Q(FSM_add_overflow_flag) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_8_ ( .D(n226), .CK(clk), .RN(n392),
.Q(exp_oper_result[8]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n318), .CK(clk), .RN(
n1675), .Q(Op_MY[6]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_12_ ( .D(n324), .CK(clk), .RN(
n437), .Q(Op_MY[12]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n354), .CK(clk), .RN(
n395), .Q(Op_MX[10]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n348), .CK(clk), .RN(
n393), .Q(Op_MX[4]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_9_ ( .D(n247), .CK(clk), .RN(n1681),
.Q(P_Sgf[9]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_0_ ( .D(n312), .CK(clk), .RN(
n392), .Q(Op_MY[0]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_20_ ( .D(n332), .CK(clk), .RN(
n437), .Q(Op_MY[20]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n319), .CK(clk), .RN(
n395), .Q(Op_MY[7]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_14_ ( .D(n326), .CK(clk), .RN(
n437), .Q(Op_MY[14]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_10_ ( .D(n322), .CK(clk), .RN(
n437), .Q(Op_MY[10]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_2_ ( .D(n314), .CK(clk), .RN(
n393), .Q(Op_MY[2]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_3_ ( .D(n315), .CK(clk), .RN(
n392), .Q(Op_MY[3]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_4_ ( .D(n316), .CK(clk), .RN(
n391), .Q(Op_MY[4]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n323), .CK(clk), .RN(
n437), .Q(Op_MY[11]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_18_ ( .D(n330), .CK(clk), .RN(
n437), .Q(Op_MY[18]), .QN(n476) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_15_ ( .D(n327), .CK(clk), .RN(
n437), .Q(Op_MY[15]), .QN(n480) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n333), .CK(clk), .RN(
n437), .Q(Op_MY[21]), .QN(n477) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_21_ ( .D(n365), .CK(clk), .RN(
n392), .Q(Op_MX[21]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_3_ ( .D(n347), .CK(clk), .RN(
n392), .Q(Op_MX[3]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_18_ ( .D(n362), .CK(clk), .RN(
n1678), .Q(Op_MX[18]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_13_ ( .D(n357), .CK(clk), .RN(
n393), .Q(Op_MX[13]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_9_ ( .D(n353), .CK(clk), .RN(
n1676), .Q(Op_MX[9]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_19_ ( .D(n363), .CK(clk), .RN(
n395), .Q(Op_MX[19]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_7_ ( .D(n351), .CK(clk), .RN(
n393), .Q(Op_MX[7]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_16_ ( .D(n360), .CK(clk), .RN(
n1676), .Q(Op_MX[16]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_15_ ( .D(n359), .CK(clk), .RN(
n1678), .Q(Op_MX[15]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_12_ ( .D(n356), .CK(clk), .RN(
n391), .Q(Op_MX[12]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n371), .CK(clk), .RN(
n393), .Q(Op_MX[27]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n367), .CK(clk), .RN(
n392), .Q(Op_MX[23]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n370), .CK(clk), .RN(
n1674), .Q(Op_MX[26]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n369), .CK(clk), .RN(
n1675), .Q(Op_MX[25]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n335), .CK(clk), .RN(
n1674), .Q(Op_MY[23]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n372), .CK(clk), .RN(
n1674), .Q(Op_MX[28]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n368), .CK(clk), .RN(
n1677), .Q(Op_MX[24]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n339), .CK(clk), .RN(
n1675), .Q(Op_MY[27]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_6_ ( .D(n350), .CK(clk), .RN(
n392), .Q(Op_MX[6]), .QN(n405) );
DFFRX4TS FS_Module_state_reg_reg_1_ ( .D(n378), .CK(clk), .RN(n167), .Q(
FS_Module_state_reg[1]) );
DFFRX2TS Sel_A_Q_reg_0_ ( .D(n376), .CK(clk), .RN(n395), .Q(FSM_selector_A),
.QN(n1647) );
CMPR32X2TS DP_OP_32J15_122_6543_U10 ( .A(S_Oper_A_exp[0]), .B(
DP_OP_32J15_122_6543_n33), .C(DP_OP_32J15_122_6543_n22), .CO(
DP_OP_32J15_122_6543_n9), .S(Exp_module_Data_S[0]) );
OR2X6TS U406 ( .A(n1437), .B(FSM_selector_C), .Y(n1359) );
CMPR32X2TS U407 ( .A(mult_x_19_n182), .B(mult_x_19_n184), .C(n1494), .CO(
n1491), .S(n1495) );
CMPR32X2TS U408 ( .A(mult_x_19_n193), .B(n1501), .C(n1500), .CO(n1498), .S(
n1502) );
CMPR32X2TS U409 ( .A(Op_MY[17]), .B(n1128), .C(Op_MY[15]), .CO(
mult_x_19_n194), .S(mult_x_19_n195) );
CMPR32X2TS U410 ( .A(mult_x_19_n210), .B(n1508), .C(n1507), .CO(n1505), .S(
n1509) );
CMPR32X2TS U411 ( .A(mult_x_19_n318), .B(n1537), .C(n1536), .CO(n1534), .S(
n1538) );
CMPR32X2TS U412 ( .A(n1103), .B(n473), .C(Op_MY[5]), .CO(mult_x_19_n292),
.S(mult_x_19_n293) );
CMPR32X2TS U413 ( .A(Op_MY[4]), .B(Op_MX[2]), .C(n503), .CO(mult_x_19_n303),
.S(mult_x_19_n304) );
CMPR32X2TS U414 ( .A(Op_MY[3]), .B(Op_MX[2]), .C(n507), .CO(mult_x_19_n314),
.S(mult_x_19_n315) );
CMPR32X2TS U415 ( .A(Op_MY[2]), .B(Op_MX[2]), .C(n511), .CO(mult_x_19_n325),
.S(mult_x_19_n326) );
CMPR32X2TS U416 ( .A(n1564), .B(mult_x_19_n414), .C(n1563), .CO(n1560), .S(
n1565) );
CMPR32X2TS U417 ( .A(Op_MY[21]), .B(Op_MY[22]), .C(n622), .CO(n660), .S(n754) );
CMPR32X2TS U418 ( .A(Op_MY[20]), .B(Op_MY[21]), .C(n625), .CO(n622), .S(n750) );
CLKINVX6TS U419 ( .A(n1109), .Y(n486) );
CMPR32X2TS U420 ( .A(n1570), .B(mult_x_19_n430), .C(n1569), .CO(n1566), .S(
n1571) );
CMPR32X2TS U421 ( .A(Op_MY[18]), .B(Op_MY[19]), .C(n631), .CO(n628), .S(n742) );
CMPR32X2TS U422 ( .A(Op_MY[17]), .B(Op_MY[18]), .C(n618), .CO(n631), .S(n738) );
CMPR32X2TS U423 ( .A(Op_MY[16]), .B(Op_MY[17]), .C(n634), .CO(n618), .S(n734) );
CMPR32X2TS U424 ( .A(mult_x_19_n452), .B(n1580), .C(n1579), .CO(n1576), .S(
n1581) );
CMPR32X2TS U425 ( .A(Op_MY[14]), .B(Op_MY[15]), .C(n640), .CO(n637), .S(n726) );
CMPR32X2TS U426 ( .A(mult_x_19_n464), .B(n1587), .C(n1586), .CO(n1582), .S(
n1588) );
CMPR32X2TS U427 ( .A(Op_MY[13]), .B(Op_MY[14]), .C(n643), .CO(n640), .S(n722) );
CMPR32X2TS U428 ( .A(n1594), .B(n1593), .C(n1592), .CO(n1589), .S(n1595) );
CMPR32X2TS U429 ( .A(n1602), .B(n1601), .C(n1600), .CO(n1596), .S(n1603) );
OAI21XLTS U430 ( .A0(n1039), .A1(n1037), .B0(n1038), .Y(n1036) );
OAI21XLTS U431 ( .A0(n1047), .A1(n1046), .B0(n1044), .Y(n1045) );
OAI21XLTS U432 ( .A0(n983), .A1(n982), .B0(n1038), .Y(n981) );
OAI21XLTS U433 ( .A0(n1015), .A1(n1014), .B0(n1058), .Y(n1013) );
OAI21XLTS U434 ( .A0(n1056), .A1(n1055), .B0(n1058), .Y(n1054) );
OAI21XLTS U435 ( .A0(n810), .A1(n809), .B0(n815), .Y(n808) );
OAI21XLTS U436 ( .A0(n757), .A1(n756), .B0(n484), .Y(n755) );
OAI21XLTS U437 ( .A0(n680), .A1(n1159), .B0(n396), .Y(n681) );
OAI21XLTS U438 ( .A0(n852), .A1(n851), .B0(n1631), .Y(n850) );
OAI21XLTS U439 ( .A0(n674), .A1(n1159), .B0(n849), .Y(n675) );
OAI21XLTS U440 ( .A0(n999), .A1(n998), .B0(n1038), .Y(n997) );
OAI21XLTS U441 ( .A0(n1005), .A1(n1004), .B0(n1038), .Y(n1003) );
OAI21XLTS U442 ( .A0(n1012), .A1(n1011), .B0(n1128), .Y(n1010) );
OAI21XLTS U443 ( .A0(n1199), .A1(n1198), .B0(n1272), .Y(n1197) );
OAI21XLTS U444 ( .A0(n1170), .A1(n1169), .B0(n1272), .Y(n1168) );
OR2X6TS U445 ( .A(FS_Module_state_reg[1]), .B(n1295), .Y(n391) );
AO22XLTS U446 ( .A0(n1623), .A1(P_Sgf[39]), .B0(n1531), .B1(n1506), .Y(n277)
);
OAI21X1TS U447 ( .A0(n753), .A1(n752), .B0(n484), .Y(n751) );
OAI21XLTS U448 ( .A0(n486), .A1(n476), .B0(n629), .Y(n630) );
OAI21X1TS U449 ( .A0(n830), .A1(n829), .B0(n1631), .Y(n828) );
OAI21X1TS U450 ( .A0(n818), .A1(n817), .B0(n815), .Y(n816) );
OAI21X1TS U451 ( .A0(n859), .A1(n858), .B0(n914), .Y(n857) );
ADDFX1TS U452 ( .A(Op_MY[19]), .B(Op_MY[20]), .CI(n628), .CO(n625), .S(n746)
);
OAI21XLTS U453 ( .A0(n486), .A1(n1196), .B0(n488), .Y(n489) );
OAI21X1TS U454 ( .A0(n848), .A1(n847), .B0(n914), .Y(n846) );
OAI21X1TS U455 ( .A0(n924), .A1(n923), .B0(n1044), .Y(n922) );
OAI21XLTS U456 ( .A0(n486), .A1(mult_x_19_n227), .B0(n644), .Y(n645) );
OAI21X1TS U457 ( .A0(n952), .A1(n951), .B0(n1038), .Y(n950) );
OAI21XLTS U458 ( .A0(n486), .A1(n1219), .B0(n493), .Y(n494) );
OAI21XLTS U459 ( .A0(n486), .A1(n1224), .B0(n497), .Y(n498) );
OAI21X1TS U460 ( .A0(n970), .A1(n969), .B0(n1058), .Y(n968) );
OAI31X1TS U461 ( .A0(n1261), .A1(mult_x_19_n778), .A2(n1260), .B0(n1259),
.Y(n1605) );
OAI31X1TS U462 ( .A0(n1268), .A1(mult_x_19_n778), .A2(n1267), .B0(n1266),
.Y(n1609) );
OAI21X1TS U463 ( .A0(n486), .A1(n1265), .B0(n505), .Y(n506) );
OAI31X1TS U464 ( .A0(n1275), .A1(mult_x_19_n778), .A2(n1274), .B0(n1273),
.Y(n1613) );
OAI31X1TS U465 ( .A0(n1282), .A1(mult_x_19_n778), .A2(n1281), .B0(n1280),
.Y(n1617) );
OAI21X1TS U466 ( .A0(n486), .A1(n1271), .B0(n509), .Y(n510) );
BUFX6TS U467 ( .A(n391), .Y(n392) );
OA21X1TS U468 ( .A0(n1307), .A1(n1389), .B0(FS_Module_state_reg[1]), .Y(
n1308) );
NAND2X4TS U469 ( .A(n1391), .B(n1294), .Y(n1401) );
AO22XLTS U470 ( .A0(n1572), .A1(P_Sgf[38]), .B0(n1531), .B1(n1509), .Y(n276)
);
AO22XLTS U471 ( .A0(n1623), .A1(P_Sgf[37]), .B0(n1531), .B1(n1511), .Y(n275)
);
OAI21XLTS U472 ( .A0(n486), .A1(n480), .B0(n635), .Y(n636) );
OAI21X1TS U473 ( .A0(n934), .A1(n933), .B0(n1044), .Y(n932) );
OAI21XLTS U474 ( .A0(n486), .A1(n1205), .B0(n638), .Y(n639) );
OAI21X1TS U475 ( .A0(n911), .A1(n910), .B0(n1044), .Y(n909) );
OAI21XLTS U476 ( .A0(n486), .A1(mult_x_19_n220), .B0(n641), .Y(n642) );
OAI31X1TS U477 ( .A0(n1217), .A1(mult_x_19_n778), .A2(n1216), .B0(n1215),
.Y(n1580) );
OAI21XLTS U478 ( .A0(n486), .A1(n1229), .B0(n647), .Y(n648) );
OAI21XLTS U479 ( .A0(n486), .A1(mult_x_19_n282), .B0(n658), .Y(n659) );
CLKINVX6TS U480 ( .A(n1116), .Y(n532) );
CLKINVX6TS U481 ( .A(n1122), .Y(n544) );
CLKINVX6TS U482 ( .A(n1142), .Y(n759) );
OR3X2TS U483 ( .A(underflow_flag), .B(overflow_flag), .C(n1624), .Y(n1626)
);
CLKINVX6TS U484 ( .A(n1129), .Y(n578) );
CLKINVX6TS U485 ( .A(n1135), .Y(n589) );
CLKINVX6TS U486 ( .A(n1284), .Y(n1166) );
CLKINVX6TS U487 ( .A(n1148), .Y(n690) );
BUFX6TS U488 ( .A(n391), .Y(n393) );
INVX6TS U489 ( .A(n1308), .Y(n394) );
AO22X1TS U490 ( .A0(n1623), .A1(P_Sgf[47]), .B0(n1585), .B1(n1293), .Y(n237)
);
AO22X1TS U491 ( .A0(n1572), .A1(P_Sgf[46]), .B0(n1553), .B1(n1490), .Y(n284)
);
AO22X1TS U492 ( .A0(n1623), .A1(P_Sgf[45]), .B0(n1531), .B1(n1493), .Y(n283)
);
AO22X1TS U493 ( .A0(n1572), .A1(P_Sgf[44]), .B0(n1585), .B1(n1495), .Y(n282)
);
AO22X1TS U494 ( .A0(n1623), .A1(P_Sgf[43]), .B0(n1585), .B1(n1497), .Y(n281)
);
AO22X1TS U495 ( .A0(n1572), .A1(P_Sgf[42]), .B0(n1531), .B1(n1499), .Y(n280)
);
AO22X1TS U496 ( .A0(n1623), .A1(P_Sgf[41]), .B0(n1531), .B1(n1502), .Y(n279)
);
AO22X1TS U497 ( .A0(n1572), .A1(P_Sgf[40]), .B0(n1531), .B1(n1504), .Y(n278)
);
ADDFX1TS U498 ( .A(mult_x_19_n230), .B(n1515), .CI(n1514), .CO(n1512), .S(
n1516) );
ADDFX1TS U499 ( .A(mult_x_19_n256), .B(n1522), .CI(n1521), .CO(n1519), .S(
n1523) );
ADDFX1TS U500 ( .A(mult_x_19_n285), .B(n1529), .CI(n1528), .CO(n1526), .S(
n1530) );
OAI21X1TS U501 ( .A0(n1031), .A1(n1030), .B0(n1629), .Y(n1029) );
OAI21XLTS U502 ( .A0(n528), .A1(n1159), .B0(n1025), .Y(n662) );
OAI21X1TS U503 ( .A0(n541), .A1(n1159), .B0(n1009), .Y(n665) );
OAI21X1TS U504 ( .A0(n1018), .A1(n1017), .B0(n1128), .Y(n1016) );
OAI21X1TS U505 ( .A0(n855), .A1(n854), .B0(n1631), .Y(n853) );
OAI21X1TS U506 ( .A0(n587), .A1(n1159), .B0(n925), .Y(n671) );
OAI21X1TS U507 ( .A0(n575), .A1(n1159), .B0(n974), .Y(n668) );
OAI21X1TS U508 ( .A0(n931), .A1(n930), .B0(n1141), .Y(n929) );
OAI21X1TS U509 ( .A0(n986), .A1(n985), .B0(n1630), .Y(n984) );
OAI21X1TS U510 ( .A0(n977), .A1(n976), .B0(n1630), .Y(n975) );
OAI21X1TS U511 ( .A0(n928), .A1(n927), .B0(n1141), .Y(n926) );
OAI21X1TS U512 ( .A0(n1028), .A1(n1027), .B0(n1629), .Y(n1026) );
NOR2X1TS U513 ( .A(Op_MY[22]), .B(n660), .Y(n661) );
OAI21X1TS U514 ( .A0(n1024), .A1(n1023), .B0(n1629), .Y(n1022) );
OAI21X1TS U515 ( .A0(n967), .A1(n966), .B0(n1630), .Y(n965) );
OAI21X1TS U516 ( .A0(n842), .A1(n841), .B0(n1631), .Y(n840) );
OAI21X1TS U517 ( .A0(n915), .A1(n913), .B0(n914), .Y(n912) );
OAI21X1TS U518 ( .A0(n899), .A1(n898), .B0(n914), .Y(n897) );
OAI21X1TS U519 ( .A0(n1021), .A1(n1020), .B0(n1058), .Y(n1019) );
OAI21X1TS U520 ( .A0(n958), .A1(n957), .B0(n1630), .Y(n956) );
OAI21X1TS U521 ( .A0(n1061), .A1(n1060), .B0(n1058), .Y(n1059) );
OAI21X1TS U522 ( .A0(n993), .A1(n992), .B0(n1038), .Y(n991) );
OAI21X1TS U523 ( .A0(n893), .A1(n892), .B0(n914), .Y(n891) );
OAI21X1TS U524 ( .A0(n1042), .A1(n1041), .B0(n1044), .Y(n1040) );
OAI21X1TS U525 ( .A0(n989), .A1(n988), .B0(n1038), .Y(n987) );
OAI21X1TS U526 ( .A0(n973), .A1(n972), .B0(n1038), .Y(n971) );
OAI21X1TS U527 ( .A0(n1008), .A1(n1007), .B0(n1058), .Y(n1006) );
OAI21X1TS U528 ( .A0(n964), .A1(n963), .B0(n1038), .Y(n962) );
OAI21X1TS U529 ( .A0(n1002), .A1(n1001), .B0(n1058), .Y(n1000) );
ADDFX1TS U530 ( .A(n1229), .B(Op_MY[10]), .CI(n495), .CO(mult_x_19_n242),
.S(mult_x_19_n243) );
OAI21X1TS U531 ( .A0(n996), .A1(n995), .B0(n1058), .Y(n994) );
OAI21X1TS U532 ( .A0(n955), .A1(n954), .B0(n1038), .Y(n953) );
ADDFX1TS U533 ( .A(Op_MY[15]), .B(Op_MY[16]), .CI(n637), .CO(n634), .S(n730)
);
OAI21X1TS U534 ( .A0(n1053), .A1(n1052), .B0(n1058), .Y(n1051) );
OAI21X1TS U535 ( .A0(n1050), .A1(n1049), .B0(n1058), .Y(n1048) );
OAI21X1TS U536 ( .A0(n980), .A1(n979), .B0(n1058), .Y(n978) );
ADDFX1TS U537 ( .A(Op_MY[12]), .B(Op_MY[13]), .CI(n492), .CO(n643), .S(n718)
);
ADDFX1TS U538 ( .A(n1610), .B(n1609), .CI(n1608), .CO(n1604), .S(n1611) );
ADDFX1TS U539 ( .A(Op_MY[11]), .B(Op_MY[12]), .CI(n496), .CO(n492), .S(n714)
);
ADDFX1TS U540 ( .A(Op_MY[10]), .B(Op_MY[11]), .CI(n646), .CO(n496), .S(n710)
);
OAI21X1TS U541 ( .A0(n961), .A1(n960), .B0(n1058), .Y(n959) );
OAI21XLTS U542 ( .A0(n408), .A1(n1025), .B0(n530), .Y(n663) );
ADDFX1TS U543 ( .A(Op_MY[9]), .B(Op_MY[10]), .CI(n649), .CO(n646), .S(n706)
);
OAI21XLTS U544 ( .A0(n1172), .A1(n1009), .B0(n1124), .Y(n1125) );
OAI21XLTS U545 ( .A0(n408), .A1(n1009), .B0(n547), .Y(n666) );
OAI21X1TS U546 ( .A0(n486), .A1(n1258), .B0(n501), .Y(n502) );
BUFX6TS U547 ( .A(n1057), .Y(n1025) );
ADDFX1TS U548 ( .A(Op_MY[7]), .B(Op_MY[8]), .CI(n655), .CO(n652), .S(n698)
);
BUFX6TS U549 ( .A(n990), .Y(n1009) );
ADDFX1TS U550 ( .A(Op_MY[6]), .B(Op_MY[7]), .CI(n500), .CO(n655), .S(n694)
);
INVX6TS U551 ( .A(n1117), .Y(n530) );
NAND2X6TS U552 ( .A(n534), .B(n531), .Y(n528) );
NOR2X4TS U553 ( .A(n1434), .B(n1622), .Y(n1395) );
BUFX6TS U554 ( .A(n814), .Y(n849) );
ADDHXLTS U555 ( .A(Op_MX[11]), .B(n617), .CO(n1084), .S(mult_x_19_n471) );
NAND2X6TS U556 ( .A(n543), .B(n546), .Y(n541) );
BUFX6TS U557 ( .A(n1043), .Y(n974) );
INVX6TS U558 ( .A(n1627), .Y(n1624) );
BUFX6TS U559 ( .A(n890), .Y(n925) );
INVX6TS U560 ( .A(n1143), .Y(n677) );
ADDFX1TS U561 ( .A(Op_MY[4]), .B(Op_MY[5]), .CI(n508), .CO(n504), .S(n542)
);
INVX6TS U562 ( .A(n1130), .Y(n576) );
BUFX6TS U563 ( .A(n391), .Y(n395) );
INVX6TS U564 ( .A(n1123), .Y(n547) );
INVX6TS U565 ( .A(n1136), .Y(n592) );
NAND2BX4TS U566 ( .AN(n1306), .B(n1108), .Y(n1553) );
ADDFX1TS U567 ( .A(Op_MY[3]), .B(Op_MY[4]), .CI(n513), .CO(n508), .S(n553)
);
INVX6TS U568 ( .A(n1283), .Y(n1157) );
NAND2X6TS U569 ( .A(n758), .B(n403), .Y(n674) );
ADDFX1TS U570 ( .A(Op_MY[2]), .B(Op_MY[3]), .CI(n516), .CO(n513), .S(n557)
);
NOR2X4TS U571 ( .A(Op_MX[22]), .B(n512), .Y(n522) );
INVX6TS U572 ( .A(n1149), .Y(n684) );
NAND2X6TS U573 ( .A(n689), .B(n683), .Y(n680) );
NAND2X6TS U574 ( .A(n588), .B(n591), .Y(n587) );
BUFX6TS U575 ( .A(n688), .Y(n396) );
NAND2X6TS U576 ( .A(n580), .B(n577), .Y(n575) );
ADDFX1TS U577 ( .A(Op_MY[1]), .B(Op_MY[2]), .CI(n519), .CO(n516), .S(n529)
);
NOR2X1TS U578 ( .A(n1096), .B(Op_MX[6]), .Y(n472) );
CLKINVX6TS U579 ( .A(Op_MY[2]), .Y(n1279) );
CLKINVX6TS U580 ( .A(Op_MY[3]), .Y(n1271) );
ADDHX2TS U581 ( .A(Op_MY[1]), .B(Op_MY[0]), .CO(n519), .S(n1285) );
NOR2X1TS U582 ( .A(Op_MX[5]), .B(n405), .Y(n471) );
CLKINVX6TS U583 ( .A(Op_MY[5]), .Y(n1258) );
CLKINVX6TS U584 ( .A(Op_MY[4]), .Y(n1265) );
OAI31X1TS U585 ( .A0(n540), .A1(Op_MX[20]), .A2(n1289), .B0(n539), .Y(n561)
);
OAI21XLTS U586 ( .A0(n537), .A1(n536), .B0(n1629), .Y(n535) );
OAI21XLTS U587 ( .A0(n937), .A1(n936), .B0(n1058), .Y(n935) );
OAI21XLTS U588 ( .A0(n943), .A1(n942), .B0(n1058), .Y(n941) );
OAI21XLTS U589 ( .A0(n946), .A1(n945), .B0(n1058), .Y(n944) );
OAI21XLTS U590 ( .A0(n949), .A1(n948), .B0(n1058), .Y(n947) );
INVX2TS U591 ( .A(n470), .Y(n527) );
OAI31X1TS U592 ( .A0(n586), .A1(Op_MX[14]), .A2(n1289), .B0(n585), .Y(n604)
);
OAI21XLTS U593 ( .A0(n801), .A1(n800), .B0(n914), .Y(n799) );
OAI21XLTS U594 ( .A0(n807), .A1(n806), .B0(n914), .Y(n805) );
OAI21XLTS U595 ( .A0(n824), .A1(n823), .B0(n914), .Y(n822) );
OAI21XLTS U596 ( .A0(n560), .A1(n559), .B0(n1038), .Y(n558) );
OAI21XLTS U597 ( .A0(n821), .A1(n820), .B0(n914), .Y(n819) );
OAI21XLTS U598 ( .A0(n556), .A1(n555), .B0(n1038), .Y(n554) );
OAI21XLTS U599 ( .A0(n827), .A1(n826), .B0(n914), .Y(n825) );
OAI21XLTS U600 ( .A0(n550), .A1(n549), .B0(n1038), .Y(n548) );
OAI21XLTS U601 ( .A0(n833), .A1(n832), .B0(n914), .Y(n831) );
OAI21XLTS U602 ( .A0(n902), .A1(n901), .B0(n1038), .Y(n900) );
OAI21XLTS U603 ( .A0(n836), .A1(n835), .B0(n914), .Y(n834) );
OAI21XLTS U604 ( .A0(n905), .A1(n904), .B0(n1038), .Y(n903) );
OAI21XLTS U605 ( .A0(n839), .A1(n838), .B0(n914), .Y(n837) );
OAI21XLTS U606 ( .A0(n908), .A1(n907), .B0(n1038), .Y(n906) );
OAI21XLTS U607 ( .A0(n845), .A1(n844), .B0(n914), .Y(n843) );
OAI21XLTS U608 ( .A0(n486), .A1(mult_x_19_n272), .B0(n653), .Y(n654) );
OAI21XLTS U609 ( .A0(n486), .A1(n1236), .B0(n650), .Y(n651) );
OAI31X1TS U610 ( .A0(n610), .A1(Op_MX[11]), .A2(n1289), .B0(n609), .Y(n617)
);
OAI31X1TS U611 ( .A0(n1067), .A1(Op_MX[8]), .A2(n1289), .B0(n1066), .Y(n1100) );
INVX2TS U612 ( .A(n694), .Y(n1244) );
INVX2TS U613 ( .A(n706), .Y(n1223) );
OAI21XLTS U614 ( .A0(n771), .A1(n770), .B0(n815), .Y(n769) );
OAI21XLTS U615 ( .A0(n603), .A1(n602), .B0(n914), .Y(n601) );
OAI21XLTS U616 ( .A0(n713), .A1(n712), .B0(n1096), .Y(n711) );
OAI21XLTS U617 ( .A0(n595), .A1(n594), .B0(n914), .Y(n593) );
INVX2TS U618 ( .A(n726), .Y(n1200) );
OAI21XLTS U619 ( .A0(n717), .A1(n716), .B0(n1096), .Y(n715) );
OAI21XLTS U620 ( .A0(n865), .A1(n864), .B0(n1044), .Y(n863) );
OAI21XLTS U621 ( .A0(n721), .A1(n720), .B0(n1096), .Y(n719) );
OAI21XLTS U622 ( .A0(n862), .A1(n861), .B0(n1044), .Y(n860) );
INVX2TS U623 ( .A(n734), .Y(n1190) );
OAI21XLTS U624 ( .A0(n725), .A1(n724), .B0(n1096), .Y(n723) );
OAI21XLTS U625 ( .A0(n813), .A1(n812), .B0(n914), .Y(n811) );
OAI21XLTS U626 ( .A0(n729), .A1(n728), .B0(n1096), .Y(n727) );
OAI21XLTS U627 ( .A0(n871), .A1(n870), .B0(n1044), .Y(n869) );
OAI21XLTS U628 ( .A0(n733), .A1(n732), .B0(n1096), .Y(n731) );
OAI21XLTS U629 ( .A0(n737), .A1(n736), .B0(n1096), .Y(n735) );
OAI21XLTS U630 ( .A0(n877), .A1(n876), .B0(n1044), .Y(n875) );
OAI21XLTS U631 ( .A0(n741), .A1(n740), .B0(n1096), .Y(n739) );
OAI21XLTS U632 ( .A0(n880), .A1(n879), .B0(n1044), .Y(n878) );
OAI21XLTS U633 ( .A0(n745), .A1(n744), .B0(n1096), .Y(n743) );
OAI21XLTS U634 ( .A0(n749), .A1(n748), .B0(n1096), .Y(n747) );
OAI21XLTS U635 ( .A0(n889), .A1(n888), .B0(n1044), .Y(n887) );
NAND3XLTS U636 ( .A(n689), .B(n1107), .C(n682), .Y(n688) );
OAI21XLTS U637 ( .A0(n408), .A1(n396), .B0(n684), .Y(n685) );
OAI21XLTS U638 ( .A0(n408), .A1(n849), .B0(n677), .Y(n678) );
OAI21XLTS U639 ( .A0(n408), .A1(n925), .B0(n592), .Y(n672) );
OAI21XLTS U640 ( .A0(n408), .A1(n974), .B0(n576), .Y(n669) );
OAI21XLTS U641 ( .A0(n486), .A1(n1191), .B0(n632), .Y(n633) );
OAI21XLTS U642 ( .A0(n693), .A1(n692), .B0(n1096), .Y(n691) );
INVX2TS U643 ( .A(n702), .Y(n1228) );
OAI31X1TS U644 ( .A0(n1107), .A1(Op_MX[5]), .A2(n1289), .B0(n1106), .Y(n1269) );
INVX2TS U645 ( .A(n687), .Y(n1251) );
OAI21XLTS U646 ( .A0(n697), .A1(n696), .B0(n1096), .Y(n695) );
OAI21XLTS U647 ( .A0(n701), .A1(n700), .B0(n1096), .Y(n699) );
INVX2TS U648 ( .A(n710), .Y(n1218) );
OAI21XLTS U649 ( .A0(n705), .A1(n704), .B0(n1096), .Y(n703) );
INVX2TS U650 ( .A(n714), .Y(n1214) );
OAI21XLTS U651 ( .A0(n774), .A1(n773), .B0(n815), .Y(n772) );
INVX2TS U652 ( .A(n718), .Y(n1210) );
OAI21XLTS U653 ( .A0(n777), .A1(n776), .B0(n815), .Y(n775) );
OAI21XLTS U654 ( .A0(n780), .A1(n779), .B0(n815), .Y(n778) );
INVX2TS U655 ( .A(n730), .Y(n1195) );
OAI21XLTS U656 ( .A0(n789), .A1(n788), .B0(n815), .Y(n787) );
OAI21XLTS U657 ( .A0(n792), .A1(n791), .B0(n815), .Y(n790) );
INVX2TS U658 ( .A(n742), .Y(n1181) );
OAI21XLTS U659 ( .A0(n798), .A1(n797), .B0(n815), .Y(n796) );
OAI21XLTS U660 ( .A0(n804), .A1(n803), .B0(n815), .Y(n802) );
BUFX4TS U661 ( .A(n661), .Y(n1159) );
OAI21XLTS U662 ( .A0(n486), .A1(n1177), .B0(n623), .Y(n624) );
OAI21XLTS U663 ( .A0(n1172), .A1(n486), .B0(n620), .Y(n621) );
OAI31X1TS U664 ( .A0(n1194), .A1(mult_x_19_n778), .A2(n1193), .B0(n1192),
.Y(n1564) );
OAI21XLTS U665 ( .A0(n1189), .A1(n1188), .B0(n1272), .Y(n1187) );
OAI21XLTS U666 ( .A0(n1185), .A1(n1184), .B0(n1272), .Y(n1183) );
OAI31X1TS U667 ( .A0(n1175), .A1(mult_x_19_n778), .A2(n1174), .B0(n1173),
.Y(n1551) );
OAI21XLTS U668 ( .A0(n1175), .A1(n1174), .B0(n1272), .Y(n1173) );
OAI31X1TS U669 ( .A0(n1170), .A1(n473), .A2(n1169), .B0(n1168), .Y(n1548) );
OAI21XLTS U670 ( .A0(n408), .A1(n1278), .B0(n1157), .Y(n1158) );
OAI21XLTS U671 ( .A0(n1172), .A1(n396), .B0(n1150), .Y(n1151) );
OAI21XLTS U672 ( .A0(n1172), .A1(n849), .B0(n1144), .Y(n1145) );
OAI21XLTS U673 ( .A0(n1172), .A1(n925), .B0(n1137), .Y(n1138) );
OAI21XLTS U674 ( .A0(n1172), .A1(n974), .B0(n1131), .Y(n1132) );
OAI21XLTS U675 ( .A0(n1172), .A1(n1025), .B0(n1118), .Y(n1119) );
AO22XLTS U676 ( .A0(n1410), .A1(Data_MX[6]), .B0(n1408), .B1(Op_MX[6]), .Y(
n350) );
AO22XLTS U677 ( .A0(Data_MY[27]), .A1(n1394), .B0(n1409), .B1(Op_MY[27]),
.Y(n339) );
AO22XLTS U678 ( .A0(Data_MX[24]), .A1(n1410), .B0(n1409), .B1(Op_MX[24]),
.Y(n368) );
AO22XLTS U679 ( .A0(Data_MX[28]), .A1(n1410), .B0(n1409), .B1(Op_MX[28]),
.Y(n372) );
AO22XLTS U680 ( .A0(Data_MX[25]), .A1(n1394), .B0(n1409), .B1(Op_MX[25]),
.Y(n369) );
AO22XLTS U681 ( .A0(Data_MX[26]), .A1(n1394), .B0(n1409), .B1(Op_MX[26]),
.Y(n370) );
AO22XLTS U682 ( .A0(Data_MX[23]), .A1(n1394), .B0(n1409), .B1(Op_MX[23]),
.Y(n367) );
AO22XLTS U683 ( .A0(Data_MX[27]), .A1(n1394), .B0(n1409), .B1(Op_MX[27]),
.Y(n371) );
AO22XLTS U684 ( .A0(n1410), .A1(Data_MX[12]), .B0(n1411), .B1(Op_MX[12]),
.Y(n356) );
AO22XLTS U685 ( .A0(n1410), .A1(Data_MX[15]), .B0(n1411), .B1(Op_MX[15]),
.Y(n359) );
AO22XLTS U686 ( .A0(n1410), .A1(Data_MX[16]), .B0(n1411), .B1(Op_MX[16]),
.Y(n360) );
AO22XLTS U687 ( .A0(n1412), .A1(Data_MX[7]), .B0(n1408), .B1(Op_MX[7]), .Y(
n351) );
AO22XLTS U688 ( .A0(n1410), .A1(Data_MX[19]), .B0(n1411), .B1(Op_MX[19]),
.Y(n363) );
AO22XLTS U689 ( .A0(n1410), .A1(Data_MX[9]), .B0(n1408), .B1(Op_MX[9]), .Y(
n353) );
AO22XLTS U690 ( .A0(n1410), .A1(Data_MX[13]), .B0(n1411), .B1(Op_MX[13]),
.Y(n357) );
AO22XLTS U691 ( .A0(n1410), .A1(Data_MX[18]), .B0(n1411), .B1(Op_MX[18]),
.Y(n362) );
AO22XLTS U692 ( .A0(n1412), .A1(Data_MX[3]), .B0(n1408), .B1(Op_MX[3]), .Y(
n347) );
AO22XLTS U693 ( .A0(n1410), .A1(Data_MX[21]), .B0(n1411), .B1(Op_MX[21]),
.Y(n365) );
AO22XLTS U694 ( .A0(n1412), .A1(Data_MY[21]), .B0(n1407), .B1(Op_MY[21]),
.Y(n333) );
AO22XLTS U695 ( .A0(n1394), .A1(Data_MY[15]), .B0(n1407), .B1(Op_MY[15]),
.Y(n327) );
AO22XLTS U696 ( .A0(n1394), .A1(Data_MY[18]), .B0(n1407), .B1(Op_MY[18]),
.Y(n330) );
AO22XLTS U697 ( .A0(n1410), .A1(Data_MY[11]), .B0(n1408), .B1(Op_MY[11]),
.Y(n323) );
AO22XLTS U698 ( .A0(n1410), .A1(Data_MY[4]), .B0(n1408), .B1(Op_MY[4]), .Y(
n316) );
AO22XLTS U699 ( .A0(n1394), .A1(Data_MY[3]), .B0(n1409), .B1(Op_MY[3]), .Y(
n315) );
AO22XLTS U700 ( .A0(n1394), .A1(Data_MY[2]), .B0(n1411), .B1(Op_MY[2]), .Y(
n314) );
AO22XLTS U701 ( .A0(n1410), .A1(Data_MY[10]), .B0(n1409), .B1(Op_MY[10]),
.Y(n322) );
AO22XLTS U702 ( .A0(n1410), .A1(Data_MY[14]), .B0(n1407), .B1(Op_MY[14]),
.Y(n326) );
AO22XLTS U703 ( .A0(n1394), .A1(Data_MY[7]), .B0(n1409), .B1(Op_MY[7]), .Y(
n319) );
AO22XLTS U704 ( .A0(n1412), .A1(Data_MY[20]), .B0(n1407), .B1(Op_MY[20]),
.Y(n332) );
AO22XLTS U705 ( .A0(n1412), .A1(Data_MY[0]), .B0(n1411), .B1(Op_MY[0]), .Y(
n312) );
AO22XLTS U706 ( .A0(n1412), .A1(Data_MX[4]), .B0(n1408), .B1(Op_MX[4]), .Y(
n348) );
AO22XLTS U707 ( .A0(n1410), .A1(Data_MX[10]), .B0(n1408), .B1(Op_MX[10]),
.Y(n354) );
AO22XLTS U708 ( .A0(n1410), .A1(Data_MY[12]), .B0(n1409), .B1(Op_MY[12]),
.Y(n324) );
AO22XLTS U709 ( .A0(n1394), .A1(Data_MY[6]), .B0(n1409), .B1(Op_MY[6]), .Y(
n318) );
XOR2X1TS U710 ( .A(n1291), .B(n1290), .Y(n1292) );
AO22XLTS U711 ( .A0(n1394), .A1(Data_MY[16]), .B0(n1407), .B1(Op_MY[16]),
.Y(n328) );
AO22XLTS U712 ( .A0(n1410), .A1(Data_MY[9]), .B0(n1407), .B1(Op_MY[9]), .Y(
n321) );
AO22XLTS U713 ( .A0(n1412), .A1(Data_MX[22]), .B0(n1411), .B1(Op_MX[22]),
.Y(n366) );
AO22XLTS U714 ( .A0(n1412), .A1(Data_MX[5]), .B0(n1408), .B1(Op_MX[5]), .Y(
n349) );
AO22XLTS U715 ( .A0(n1412), .A1(Data_MX[0]), .B0(n1407), .B1(Op_MX[0]), .Y(
n344) );
AO22XLTS U716 ( .A0(n1410), .A1(Data_MX[8]), .B0(n1408), .B1(Op_MX[8]), .Y(
n352) );
AO22XLTS U717 ( .A0(n1410), .A1(Data_MX[11]), .B0(n1408), .B1(Op_MX[11]),
.Y(n355) );
AO22XLTS U718 ( .A0(n1410), .A1(Data_MX[14]), .B0(n1411), .B1(Op_MX[14]),
.Y(n358) );
AO22XLTS U719 ( .A0(n1410), .A1(Data_MX[20]), .B0(n1411), .B1(Op_MX[20]),
.Y(n364) );
AO22XLTS U720 ( .A0(n1394), .A1(Data_MY[17]), .B0(n1407), .B1(Op_MY[17]),
.Y(n329) );
AO22XLTS U721 ( .A0(n1394), .A1(Data_MY[5]), .B0(n1407), .B1(Op_MY[5]), .Y(
n317) );
AO22XLTS U722 ( .A0(n1412), .A1(Data_MY[19]), .B0(n1407), .B1(Op_MY[19]),
.Y(n331) );
AO22XLTS U723 ( .A0(n1394), .A1(Data_MY[13]), .B0(n1408), .B1(Op_MY[13]),
.Y(n325) );
AO22XLTS U724 ( .A0(n1410), .A1(Data_MY[8]), .B0(n1407), .B1(Op_MY[8]), .Y(
n320) );
AO22XLTS U725 ( .A0(n1410), .A1(Data_MY[1]), .B0(n1411), .B1(Op_MY[1]), .Y(
n313) );
AO22XLTS U726 ( .A0(n1412), .A1(Data_MY[22]), .B0(n1407), .B1(Op_MY[22]),
.Y(n334) );
AO22XLTS U727 ( .A0(n1572), .A1(P_Sgf[25]), .B0(n1553), .B1(n1540), .Y(n263)
);
AO22XLTS U728 ( .A0(n1572), .A1(P_Sgf[26]), .B0(n1553), .B1(n1538), .Y(n264)
);
AO22XLTS U729 ( .A0(n1572), .A1(P_Sgf[27]), .B0(n1553), .B1(n1535), .Y(n265)
);
AO22XLTS U730 ( .A0(n1572), .A1(P_Sgf[28]), .B0(n1553), .B1(n1533), .Y(n266)
);
AO22XLTS U731 ( .A0(n1572), .A1(P_Sgf[29]), .B0(n1531), .B1(n1530), .Y(n267)
);
AO22XLTS U732 ( .A0(n1572), .A1(P_Sgf[30]), .B0(n1585), .B1(n1527), .Y(n268)
);
AO22XLTS U733 ( .A0(n1572), .A1(P_Sgf[31]), .B0(n1531), .B1(n1525), .Y(n269)
);
AO22XLTS U734 ( .A0(n1572), .A1(P_Sgf[32]), .B0(n1531), .B1(n1523), .Y(n270)
);
AO22XLTS U735 ( .A0(n1623), .A1(P_Sgf[33]), .B0(n1531), .B1(n1520), .Y(n271)
);
AO22XLTS U736 ( .A0(n1572), .A1(P_Sgf[34]), .B0(n1531), .B1(n1518), .Y(n272)
);
AO22XLTS U737 ( .A0(n1623), .A1(P_Sgf[35]), .B0(n1531), .B1(n1516), .Y(n273)
);
AO22XLTS U738 ( .A0(n1572), .A1(P_Sgf[36]), .B0(n1531), .B1(n1513), .Y(n274)
);
OAI211XLTS U739 ( .A0(Sgf_normalized_result[3]), .A1(n1441), .B0(n1486),
.C0(n1443), .Y(n1442) );
AO22XLTS U740 ( .A0(n1486), .A1(n1444), .B0(n1481), .B1(n448), .Y(n305) );
OAI211XLTS U741 ( .A0(Sgf_normalized_result[5]), .A1(n1445), .B0(n1476),
.C0(n1447), .Y(n1446) );
AO22XLTS U742 ( .A0(n1486), .A1(n1448), .B0(n1481), .B1(n459), .Y(n303) );
AO22XLTS U743 ( .A0(n1486), .A1(n1451), .B0(n1481), .B1(n460), .Y(n301) );
AO22XLTS U744 ( .A0(n1486), .A1(n1455), .B0(n1481), .B1(n461), .Y(n299) );
AO22XLTS U745 ( .A0(n1486), .A1(n1459), .B0(n1481), .B1(n462), .Y(n297) );
AO22XLTS U746 ( .A0(n1486), .A1(n1463), .B0(n1481), .B1(n463), .Y(n295) );
AO22XLTS U747 ( .A0(n1486), .A1(n1467), .B0(n1481), .B1(n464), .Y(n293) );
AO22XLTS U748 ( .A0(n1486), .A1(n1471), .B0(n1481), .B1(n465), .Y(n291) );
AO22XLTS U749 ( .A0(n1486), .A1(n1475), .B0(n1481), .B1(n466), .Y(n289) );
AO22XLTS U750 ( .A0(n1394), .A1(Data_MX[1]), .B0(n1408), .B1(n468), .Y(n345)
);
AO22XLTS U751 ( .A0(n1410), .A1(Data_MX[17]), .B0(n1411), .B1(n470), .Y(n361) );
AO22XLTS U752 ( .A0(Data_MX[29]), .A1(n1394), .B0(n1409), .B1(n442), .Y(n373) );
AO22XLTS U753 ( .A0(Data_MX[30]), .A1(n1394), .B0(n1409), .B1(n441), .Y(n374) );
OR2X1TS U754 ( .A(n471), .B(n472), .Y(n403) );
OR2X1TS U755 ( .A(n1634), .B(n1447), .Y(n409) );
AOI22X1TS U756 ( .A0(n1412), .A1(Data_MX[2]), .B0(n1408), .B1(Op_MX[2]), .Y(
n411) );
CLKINVX6TS U757 ( .A(rst), .Y(n167) );
ADDHX1TS U758 ( .A(n1083), .B(n1082), .CO(n1034), .S(mult_x_19_n427) );
ADDHX1TS U759 ( .A(n1085), .B(n1084), .CO(n1032), .S(mult_x_19_n466) );
ADDHX1TS U760 ( .A(n1033), .B(n1032), .CO(n1068), .S(mult_x_19_n461) );
ADDHX1TS U761 ( .A(n1035), .B(n1034), .CO(n1071), .S(mult_x_19_n419) );
NOR2X2TS U762 ( .A(n1646), .B(n1479), .Y(n1482) );
AOI222X1TS U763 ( .A0(n1146), .A1(n1285), .B0(n1142), .B1(Op_MY[1]), .C0(
n1143), .C1(Op_MY[0]), .Y(n1065) );
NOR2X2TS U764 ( .A(n758), .B(n1067), .Y(n1142) );
AOI222X1TS U765 ( .A0(n1133), .A1(n1285), .B0(n1129), .B1(Op_MY[1]), .C0(
n1130), .C1(Op_MY[0]), .Y(n584) );
NOR2X2TS U766 ( .A(n577), .B(n579), .Y(n1130) );
AOI222X1TS U767 ( .A0(n1120), .A1(n1285), .B0(n1116), .B1(Op_MY[1]), .C0(
n1117), .C1(Op_MY[0]), .Y(n538) );
NOR2X2TS U768 ( .A(n531), .B(n533), .Y(n1117) );
AOI222X1TS U769 ( .A0(n1126), .A1(n1285), .B0(n1122), .B1(Op_MY[1]), .C0(
n1123), .C1(Op_MY[0]), .Y(n565) );
NOR2X2TS U770 ( .A(n546), .B(n545), .Y(n1123) );
INVX2TS U771 ( .A(n409), .Y(n436) );
NOR2X2TS U772 ( .A(n1635), .B(n1450), .Y(n1452) );
NOR2X2TS U773 ( .A(n1636), .B(n1454), .Y(n1456) );
NOR2X2TS U774 ( .A(n1637), .B(n1458), .Y(n1460) );
NOR2X2TS U775 ( .A(n1638), .B(n1462), .Y(n1464) );
NOR2X2TS U776 ( .A(n1639), .B(n1466), .Y(n1468) );
NOR2X2TS U777 ( .A(n1642), .B(n1470), .Y(n1472) );
NOR2X2TS U778 ( .A(n1643), .B(n1474), .Y(n1477) );
NOR4X1TS U779 ( .A(Op_MY[2]), .B(Op_MY[3]), .C(Op_MY[4]), .D(Op_MY[5]), .Y(
n1420) );
NOR2X2TS U780 ( .A(n580), .B(n586), .Y(n1129) );
NOR2X2TS U781 ( .A(n543), .B(n567), .Y(n1122) );
NOR2X2TS U782 ( .A(n534), .B(n540), .Y(n1116) );
BUFX6TS U783 ( .A(n522), .Y(n657) );
AOI222X1TS U784 ( .A0(n1286), .A1(n1285), .B0(n1284), .B1(Op_MY[1]), .C0(
n1283), .C1(Op_MY[0]), .Y(n1287) );
NOR2X2TS U785 ( .A(n1161), .B(n406), .Y(n1284) );
OAI22X2TS U786 ( .A0(beg_FSM), .A1(n391), .B0(ack_FSM), .B1(n1375), .Y(n1402) );
BUFX3TS U787 ( .A(n391), .Y(n437) );
BUFX4TS U788 ( .A(n391), .Y(n1678) );
BUFX4TS U789 ( .A(n391), .Y(n1676) );
INVX6TS U790 ( .A(n1401), .Y(n1410) );
INVX2TS U791 ( .A(n413), .Y(n438) );
INVX2TS U792 ( .A(n401), .Y(n439) );
NOR4X1TS U793 ( .A(Op_MY[22]), .B(n438), .C(n439), .D(Op_MY[27]), .Y(n1413)
);
NOR3XLTS U794 ( .A(Op_MX[24]), .B(Op_MX[0]), .C(n468), .Y(n1427) );
INVX2TS U795 ( .A(n397), .Y(n440) );
INVX2TS U796 ( .A(n414), .Y(n441) );
INVX2TS U797 ( .A(n402), .Y(n442) );
NOR4X1TS U798 ( .A(Op_MX[22]), .B(n441), .C(n442), .D(Op_MX[28]), .Y(n1421)
);
INVX2TS U799 ( .A(n400), .Y(n443) );
NOR3XLTS U800 ( .A(Op_MY[23]), .B(Op_MY[0]), .C(Op_MY[1]), .Y(n1419) );
INVX2TS U801 ( .A(n398), .Y(n444) );
INVX2TS U802 ( .A(n412), .Y(n445) );
INVX2TS U803 ( .A(n434), .Y(n446) );
INVX2TS U804 ( .A(n435), .Y(n447) );
INVX2TS U805 ( .A(n433), .Y(n448) );
INVX2TS U806 ( .A(n425), .Y(n449) );
INVX2TS U807 ( .A(n426), .Y(n450) );
INVX2TS U808 ( .A(n427), .Y(n451) );
INVX2TS U809 ( .A(n428), .Y(n452) );
INVX2TS U810 ( .A(n429), .Y(n453) );
INVX2TS U811 ( .A(n430), .Y(n454) );
INVX2TS U812 ( .A(n431), .Y(n455) );
INVX2TS U813 ( .A(n432), .Y(n456) );
INVX2TS U814 ( .A(n424), .Y(n457) );
INVX2TS U815 ( .A(n423), .Y(n458) );
INVX2TS U816 ( .A(n415), .Y(n459) );
INVX2TS U817 ( .A(n416), .Y(n460) );
INVX2TS U818 ( .A(n417), .Y(n461) );
INVX2TS U819 ( .A(n418), .Y(n462) );
INVX2TS U820 ( .A(n419), .Y(n463) );
INVX2TS U821 ( .A(n420), .Y(n464) );
INVX2TS U822 ( .A(n421), .Y(n465) );
INVX2TS U823 ( .A(n422), .Y(n466) );
BUFX6TS U824 ( .A(n480), .Y(n1201) );
CLKBUFX3TS U825 ( .A(n1299), .Y(n1484) );
BUFX6TS U826 ( .A(n1309), .Y(n1356) );
CLKINVX3TS U827 ( .A(n1484), .Y(n1476) );
INVX3TS U828 ( .A(n1484), .Y(n1486) );
BUFX6TS U829 ( .A(n1154), .Y(n1277) );
BUFX6TS U830 ( .A(n476), .Y(n1628) );
OAI21XLTS U831 ( .A0(n486), .A1(n1289), .B0(n520), .Y(n521) );
OAI21XLTS U832 ( .A0(n486), .A1(n407), .B0(n517), .Y(n518) );
OAI21XLTS U833 ( .A0(n486), .A1(n1279), .B0(n514), .Y(n515) );
BUFX4TS U834 ( .A(n1096), .Y(n1103) );
BUFX6TS U835 ( .A(n484), .Y(n1096) );
AOI222X1TS U836 ( .A0(n522), .A1(n1285), .B0(n656), .B1(Op_MY[1]), .C0(n1112), .C1(Op_MY[0]), .Y(n1076) );
BUFX6TS U837 ( .A(n485), .Y(n656) );
CLKINVX6TS U838 ( .A(n1626), .Y(n1625) );
BUFX6TS U839 ( .A(n619), .Y(n1112) );
BUFX6TS U840 ( .A(n1310), .Y(n1361) );
BUFX6TS U841 ( .A(n1155), .Y(n1278) );
XOR2X1TS U842 ( .A(n1141), .B(n608), .Y(n1085) );
OAI21XLTS U843 ( .A0(n607), .A1(n606), .B0(n1141), .Y(n605) );
BUFX6TS U844 ( .A(n914), .Y(n1141) );
OAI21XLTS U845 ( .A0(n1172), .A1(n1278), .B0(n1162), .Y(n1163) );
BUFX6TS U846 ( .A(n477), .Y(n1172) );
BUFX6TS U847 ( .A(n483), .Y(n1630) );
BUFX6TS U848 ( .A(n482), .Y(n1631) );
INVX2TS U849 ( .A(n399), .Y(n467) );
OAI2BB2X2TS U850 ( .B0(n478), .B1(Op_MX[12]), .A0N(Op_MX[12]), .A1N(n914),
.Y(n577) );
NOR4X1TS U851 ( .A(Op_MX[10]), .B(Op_MX[11]), .C(Op_MX[12]), .D(Op_MX[13]),
.Y(n1426) );
OAI2BB2X2TS U852 ( .B0(n483), .B1(Op_MX[15]), .A0N(Op_MX[15]), .A1N(n1044),
.Y(n546) );
NOR4X1TS U853 ( .A(Op_MX[14]), .B(Op_MX[15]), .C(Op_MX[16]), .D(n470), .Y(
n1423) );
OAI2BB2X2TS U854 ( .B0(n527), .B1(Op_MX[16]), .A0N(Op_MX[16]), .A1N(n527),
.Y(n543) );
OAI2BB2X2TS U855 ( .B0(n482), .B1(Op_MX[7]), .A0N(Op_MX[7]), .A1N(n482), .Y(
n758) );
NOR4X1TS U856 ( .A(Op_MX[6]), .B(Op_MX[7]), .C(Op_MX[8]), .D(Op_MX[9]), .Y(
n1425) );
OAI2BB2X2TS U857 ( .B0(n1058), .B1(Op_MX[19]), .A0N(Op_MX[19]), .A1N(n481),
.Y(n534) );
NOR4X1TS U858 ( .A(Op_MX[18]), .B(Op_MX[19]), .C(Op_MX[20]), .D(Op_MX[21]),
.Y(n1424) );
OAI2BB2X2TS U859 ( .B0(n482), .B1(Op_MX[9]), .A0N(Op_MX[9]), .A1N(n815), .Y(
n591) );
OAI2BB2X2TS U860 ( .B0(n483), .B1(Op_MX[13]), .A0N(Op_MX[13]), .A1N(n483),
.Y(n580) );
OAI2BB2X2TS U861 ( .B0(n527), .B1(Op_MX[18]), .A0N(Op_MX[18]), .A1N(n1038),
.Y(n531) );
INVX2TS U862 ( .A(n404), .Y(n468) );
NOR4X1TS U863 ( .A(Op_MX[2]), .B(Op_MX[3]), .C(Op_MX[4]), .D(Op_MX[5]), .Y(
n1428) );
INVX2TS U864 ( .A(n410), .Y(n469) );
NOR3X1TS U865 ( .A(Op_MX[20]), .B(Op_MX[21]), .C(Op_MX[22]), .Y(n1109) );
INVX2TS U866 ( .A(n1128), .Y(n470) );
NOR4X1TS U867 ( .A(Op_MY[18]), .B(Op_MY[19]), .C(Op_MY[20]), .D(Op_MY[21]),
.Y(n1416) );
NOR4X1TS U868 ( .A(Op_MY[14]), .B(Op_MY[15]), .C(Op_MY[16]), .D(Op_MY[17]),
.Y(n1415) );
CLKINVX6TS U869 ( .A(Op_MY[11]), .Y(n1219) );
CLKINVX6TS U870 ( .A(Op_MY[10]), .Y(n1224) );
CLKINVX6TS U871 ( .A(Op_MY[14]), .Y(n1205) );
INVX6TS U872 ( .A(Op_MY[7]), .Y(mult_x_19_n272) );
CLKINVX6TS U873 ( .A(Op_MY[20]), .Y(n1177) );
INVX6TS U874 ( .A(Op_MY[0]), .Y(n1289) );
AOI222X1TS U875 ( .A0(n1152), .A1(n1285), .B0(n1148), .B1(Op_MY[1]), .C0(
n1149), .C1(Op_MY[0]), .Y(n1105) );
NOR4X1TS U876 ( .A(P_Sgf[6]), .B(P_Sgf[7]), .C(P_Sgf[8]), .D(P_Sgf[9]), .Y(
n1364) );
BUFX4TS U877 ( .A(n167), .Y(n1679) );
NOR2X2TS U878 ( .A(n403), .B(n676), .Y(n1143) );
OAI2BB2X2TS U879 ( .B0(n1096), .B1(Op_MX[4]), .A0N(Op_MX[4]), .A1N(n484),
.Y(n689) );
OAI2BB2X2TS U880 ( .B0(n478), .B1(Op_MX[10]), .A0N(Op_MX[10]), .A1N(n478),
.Y(n588) );
INVX6TS U881 ( .A(n1553), .Y(n1572) );
INVX6TS U882 ( .A(Op_MY[12]), .Y(mult_x_19_n227) );
INVX6TS U883 ( .A(Op_MY[6]), .Y(mult_x_19_n282) );
INVX2TS U884 ( .A(Op_MX[2]), .Y(n473) );
OAI31X1TS U885 ( .A0(n1199), .A1(mult_x_19_n778), .A2(n1198), .B0(n1197),
.Y(n1567) );
OAI31X1TS U886 ( .A0(n1204), .A1(mult_x_19_n778), .A2(n1203), .B0(n1202),
.Y(n1570) );
OAI31X1TS U887 ( .A0(n1209), .A1(mult_x_19_n778), .A2(n1208), .B0(n1207),
.Y(n1574) );
OAI31X1TS U888 ( .A0(n1213), .A1(mult_x_19_n778), .A2(n1212), .B0(n1211),
.Y(n1577) );
OAI31X1TS U889 ( .A0(n1222), .A1(mult_x_19_n778), .A2(n1221), .B0(n1220),
.Y(n1583) );
OAI31X4TS U890 ( .A0(n1227), .A1(mult_x_19_n778), .A2(n1226), .B0(n1225),
.Y(n1587) );
OAI31X4TS U891 ( .A0(n1232), .A1(mult_x_19_n778), .A2(n1231), .B0(n1230),
.Y(n1590) );
OAI31X4TS U892 ( .A0(n1240), .A1(mult_x_19_n778), .A2(n1239), .B0(n1238),
.Y(n1593) );
OAI31X4TS U893 ( .A0(n1247), .A1(mult_x_19_n778), .A2(n1246), .B0(n1245),
.Y(n1597) );
OAI31X4TS U894 ( .A0(n1254), .A1(mult_x_19_n778), .A2(n1253), .B0(n1252),
.Y(n1601) );
CLKAND2X4TS U895 ( .A(n1306), .B(n1302), .Y(DP_OP_32J15_122_6543_n33) );
INVX4TS U896 ( .A(n1401), .Y(n1394) );
BUFX6TS U897 ( .A(n1312), .Y(n1360) );
OAI21XLTS U898 ( .A0(n564), .A1(n563), .B0(n1128), .Y(n562) );
BUFX6TS U899 ( .A(n1038), .Y(n1128) );
CLKINVX6TS U900 ( .A(Op_MY[16]), .Y(n1196) );
BUFX6TS U901 ( .A(n475), .Y(n1229) );
NOR2X2TS U902 ( .A(n1156), .B(Op_MX[0]), .Y(n1283) );
NOR3X2TS U903 ( .A(n1632), .B(FS_Module_state_reg[0]), .C(
FS_Module_state_reg[3]), .Y(n1306) );
CLKINVX6TS U904 ( .A(Op_MY[17]), .Y(n1191) );
CLKINVX6TS U905 ( .A(Op_MY[19]), .Y(n1182) );
INVX6TS U906 ( .A(Op_MY[13]), .Y(mult_x_19_n220) );
CLKINVX6TS U907 ( .A(Op_MY[8]), .Y(n1236) );
BUFX6TS U908 ( .A(n473), .Y(n1272) );
OAI21XLTS U909 ( .A0(n583), .A1(n582), .B0(n1630), .Y(n581) );
OAI21XLTS U910 ( .A0(n940), .A1(n939), .B0(n1058), .Y(n938) );
OAI21XLTS U911 ( .A0(n918), .A1(n917), .B0(n1038), .Y(n916) );
OAI21XLTS U912 ( .A0(n921), .A1(n920), .B0(n1038), .Y(n919) );
OAI21XLTS U913 ( .A0(n600), .A1(n599), .B0(n914), .Y(n598) );
OAI21XLTS U914 ( .A0(n868), .A1(n867), .B0(n1044), .Y(n866) );
OAI21XLTS U915 ( .A0(n874), .A1(n873), .B0(n1044), .Y(n872) );
OAI21XLTS U916 ( .A0(n883), .A1(n882), .B0(n1044), .Y(n881) );
OAI21XLTS U917 ( .A0(n886), .A1(n885), .B0(n1044), .Y(n884) );
OAI21XLTS U918 ( .A0(n896), .A1(n895), .B0(n1044), .Y(n894) );
OAI21XLTS U919 ( .A0(n768), .A1(n767), .B0(n815), .Y(n766) );
OAI21XLTS U920 ( .A0(n709), .A1(n708), .B0(n1096), .Y(n707) );
INVX2TS U921 ( .A(n722), .Y(n1206) );
OAI21XLTS U922 ( .A0(n783), .A1(n782), .B0(n815), .Y(n781) );
OAI21XLTS U923 ( .A0(n786), .A1(n785), .B0(n815), .Y(n784) );
INVX2TS U924 ( .A(n738), .Y(n1186) );
OAI21XLTS U925 ( .A0(n795), .A1(n794), .B0(n815), .Y(n793) );
OAI21XLTS U926 ( .A0(n486), .A1(n1182), .B0(n626), .Y(n627) );
OAI21XLTS U927 ( .A0(FSM_selector_B[0]), .A1(n1386), .B0(n1385), .Y(n1387)
);
OAI21XLTS U928 ( .A0(n1268), .A1(n1267), .B0(n1272), .Y(n1266) );
OAI21XLTS U929 ( .A0(n1247), .A1(n1246), .B0(n1272), .Y(n1245) );
OAI21XLTS U930 ( .A0(n1227), .A1(n1226), .B0(n1272), .Y(n1225) );
OAI21XLTS U931 ( .A0(n1204), .A1(n1203), .B0(n1272), .Y(n1202) );
OAI21XLTS U932 ( .A0(n1194), .A1(n1193), .B0(n1272), .Y(n1192) );
OAI21XLTS U933 ( .A0(n1180), .A1(n1179), .B0(n1272), .Y(n1178) );
XNOR2X1TS U934 ( .A(Op_MY[21]), .B(n1292), .Y(n1293) );
OAI21XLTS U935 ( .A0(n1482), .A1(Sgf_normalized_result[23]), .B0(n1485), .Y(
n1483) );
OAI211XLTS U936 ( .A0(Sgf_normalized_result[15]), .A1(n1464), .B0(n1476),
.C0(n1466), .Y(n1465) );
OAI211XLTS U937 ( .A0(n1359), .A1(n1661), .B0(n1355), .C0(n1354), .Y(n218)
);
OAI211XLTS U938 ( .A0(n1359), .A1(n1656), .B0(n1316), .C0(n1315), .Y(n202)
);
NOR2X2TS U939 ( .A(FS_Module_state_reg[1]), .B(n1645), .Y(n1391) );
NOR2X1TS U940 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[3]), .Y(
n1294) );
CLKINVX6TS U941 ( .A(n1401), .Y(n1412) );
BUFX3TS U942 ( .A(n1401), .Y(n1408) );
BUFX6TS U943 ( .A(n479), .Y(n1038) );
BUFX6TS U944 ( .A(n481), .Y(n1629) );
BUFX4TS U945 ( .A(n481), .Y(n1058) );
AOI2BB2X2TS U946 ( .B0(Op_MX[21]), .B1(n1629), .A0N(n1058), .A1N(Op_MX[21]),
.Y(n512) );
NOR2BX1TS U947 ( .AN(Op_MX[22]), .B(n512), .Y(n485) );
XNOR2X1TS U948 ( .A(Op_MX[21]), .B(Op_MX[22]), .Y(n487) );
NOR2BX1TS U949 ( .AN(n512), .B(n487), .Y(n619) );
AOI22X1TS U950 ( .A0(n657), .A1(n738), .B0(n1112), .B1(Op_MY[17]), .Y(n488)
);
AOI21X1TS U951 ( .A0(n656), .A1(Op_MY[18]), .B0(n489), .Y(n491) );
CMPR32X2TS U952 ( .A(n1201), .B(Op_MY[16]), .C(n490), .CO(mult_x_19_n199),
.S(mult_x_19_n200) );
CMPR32X2TS U953 ( .A(mult_x_19_n211), .B(n1201), .C(n491), .CO(n490), .S(
mult_x_19_n206) );
BUFX6TS U954 ( .A(n478), .Y(n914) );
CMPR32X2TS U955 ( .A(Op_MY[11]), .B(n1141), .C(Op_MY[9]), .CO(mult_x_19_n234), .S(mult_x_19_n235) );
AOI22X1TS U956 ( .A0(n657), .A1(n718), .B0(n1112), .B1(Op_MY[12]), .Y(n493)
);
AOI21X1TS U957 ( .A0(n656), .A1(Op_MY[13]), .B0(n494), .Y(n495) );
AOI22X1TS U958 ( .A0(n657), .A1(n714), .B0(n1112), .B1(Op_MY[11]), .Y(n497)
);
AOI21X1TS U959 ( .A0(n656), .A1(Op_MY[12]), .B0(n498), .Y(n499) );
CMPR32X2TS U960 ( .A(mult_x_19_n260), .B(n1229), .C(n499), .CO(
mult_x_19_n251), .S(mult_x_19_n252) );
AOI22X1TS U961 ( .A0(n657), .A1(n694), .B0(n1112), .B1(Op_MY[6]), .Y(n501)
);
AOI21X1TS U962 ( .A0(n656), .A1(Op_MY[7]), .B0(n502), .Y(n503) );
CMPR32X2TS U963 ( .A(Op_MY[5]), .B(Op_MY[6]), .C(n504), .CO(n500), .S(n687)
);
AOI22X1TS U964 ( .A0(n657), .A1(n687), .B0(n1112), .B1(Op_MY[5]), .Y(n505)
);
AOI21X1TS U965 ( .A0(n656), .A1(Op_MY[6]), .B0(n506), .Y(n507) );
AOI22X1TS U966 ( .A0(n657), .A1(n542), .B0(n1112), .B1(Op_MY[4]), .Y(n509)
);
AOI21X1TS U967 ( .A0(n656), .A1(Op_MY[5]), .B0(n510), .Y(n511) );
NOR2X1TS U968 ( .A(n512), .B(n1289), .Y(mult_x_19_n381) );
AOI22X1TS U969 ( .A0(n657), .A1(n553), .B0(n1112), .B1(Op_MY[3]), .Y(n514)
);
AOI21X1TS U970 ( .A0(n656), .A1(Op_MY[4]), .B0(n515), .Y(n524) );
AOI22X1TS U971 ( .A0(n657), .A1(n557), .B0(n1112), .B1(Op_MY[2]), .Y(n517)
);
AOI21X1TS U972 ( .A0(n656), .A1(Op_MY[3]), .B0(n518), .Y(n526) );
AOI22X1TS U973 ( .A0(n657), .A1(n529), .B0(n1112), .B1(Op_MY[1]), .Y(n520)
);
AOI21X1TS U974 ( .A0(n656), .A1(Op_MY[2]), .B0(n521), .Y(n1081) );
INVX2TS U975 ( .A(mult_x_19_n381), .Y(n1077) );
CMPR32X2TS U976 ( .A(n524), .B(Op_MY[1]), .C(n523), .CO(mult_x_19_n336), .S(
mult_x_19_n337) );
CMPR32X2TS U977 ( .A(n526), .B(Op_MY[0]), .C(n525), .CO(n523), .S(
mult_x_19_n348) );
INVX2TS U978 ( .A(n529), .Y(n1276) );
XNOR2X1TS U979 ( .A(Op_MX[19]), .B(Op_MX[18]), .Y(n533) );
OAI22X1TS U980 ( .A0(n528), .A1(n1276), .B0(n530), .B1(n407), .Y(n537) );
INVX2TS U981 ( .A(n531), .Y(n540) );
NAND3X1TS U982 ( .A(n534), .B(n540), .C(n533), .Y(n1057) );
OAI22X1TS U983 ( .A0(n532), .A1(n1279), .B0(n1025), .B1(n1289), .Y(n536) );
OAI31X1TS U984 ( .A0(n537), .A1(n1629), .A2(n536), .B0(n535), .Y(n1075) );
INVX2TS U985 ( .A(n528), .Y(n1120) );
XOR2X1TS U986 ( .A(n1629), .B(n538), .Y(n552) );
OAI21XLTS U987 ( .A0(n540), .A1(n1289), .B0(Op_MX[20]), .Y(n539) );
BUFX4TS U988 ( .A(n483), .Y(n1044) );
INVX2TS U989 ( .A(n542), .Y(n1257) );
INVX2TS U990 ( .A(n546), .Y(n567) );
XNOR2X1TS U991 ( .A(Op_MX[16]), .B(Op_MX[15]), .Y(n545) );
NAND3X1TS U992 ( .A(n543), .B(n567), .C(n545), .Y(n990) );
OAI22X1TS U993 ( .A0(n541), .A1(n1257), .B0(n1009), .B1(n1271), .Y(n550) );
OAI22X1TS U994 ( .A0(n544), .A1(n1258), .B0(n547), .B1(n1265), .Y(n549) );
OAI31X1TS U995 ( .A0(n550), .A1(n1128), .A2(n549), .B0(n548), .Y(n569) );
ADDHXLTS U996 ( .A(n552), .B(n551), .CO(n1074), .S(n573) );
INVX2TS U997 ( .A(n553), .Y(n1264) );
OAI22X1TS U998 ( .A0(n541), .A1(n1264), .B0(n1009), .B1(n1279), .Y(n556) );
OAI22X1TS U999 ( .A0(n544), .A1(n1265), .B0(n547), .B1(n1271), .Y(n555) );
OAI31X1TS U1000 ( .A0(n556), .A1(n1128), .A2(n555), .B0(n554), .Y(n572) );
INVX2TS U1001 ( .A(n557), .Y(n1270) );
OAI22X1TS U1002 ( .A0(n541), .A1(n1270), .B0(n1009), .B1(n407), .Y(n560) );
OAI22X1TS U1003 ( .A0(n544), .A1(n1271), .B0(n547), .B1(n1279), .Y(n559) );
OAI31X1TS U1004 ( .A0(n560), .A1(n1128), .A2(n559), .B0(n558), .Y(n1073) );
ADDHXLTS U1005 ( .A(Op_MX[20]), .B(n561), .CO(n551), .S(n1072) );
OAI22X1TS U1006 ( .A0(n541), .A1(n1276), .B0(n547), .B1(n407), .Y(n564) );
OAI22X1TS U1007 ( .A0(n544), .A1(n1279), .B0(n1009), .B1(n1289), .Y(n563) );
OAI31X1TS U1008 ( .A0(n564), .A1(n1128), .A2(n563), .B0(n562), .Y(n1035) );
INVX2TS U1009 ( .A(n541), .Y(n1126) );
XOR2X1TS U1010 ( .A(n1128), .B(n565), .Y(n1083) );
OAI21XLTS U1011 ( .A0(n567), .A1(n1289), .B0(n470), .Y(n566) );
OAI31X1TS U1012 ( .A0(n567), .A1(n470), .A2(n1289), .B0(n566), .Y(n574) );
CMPR32X2TS U1013 ( .A(n570), .B(n569), .C(n568), .CO(mult_x_19_n388), .S(
mult_x_19_n389) );
CMPR32X2TS U1014 ( .A(n573), .B(n572), .C(n571), .CO(n568), .S(
mult_x_19_n399) );
ADDHXLTS U1015 ( .A(n470), .B(n574), .CO(n1082), .S(mult_x_19_n435) );
XNOR2X1TS U1016 ( .A(Op_MX[13]), .B(Op_MX[12]), .Y(n579) );
OAI22X1TS U1017 ( .A0(n575), .A1(n1276), .B0(n576), .B1(n407), .Y(n583) );
INVX2TS U1018 ( .A(n577), .Y(n586) );
NAND3X1TS U1019 ( .A(n580), .B(n586), .C(n579), .Y(n1043) );
OAI22X1TS U1020 ( .A0(n578), .A1(n1279), .B0(n974), .B1(n1289), .Y(n582) );
OAI31X1TS U1021 ( .A0(n583), .A1(n1630), .A2(n582), .B0(n581), .Y(n1079) );
INVX2TS U1022 ( .A(n575), .Y(n1133) );
XOR2X1TS U1023 ( .A(n1630), .B(n584), .Y(n597) );
OAI21XLTS U1024 ( .A0(n586), .A1(n1289), .B0(Op_MX[14]), .Y(n585) );
BUFX4TS U1025 ( .A(n482), .Y(n815) );
INVX2TS U1026 ( .A(n591), .Y(n610) );
XNOR2X1TS U1027 ( .A(Op_MX[10]), .B(Op_MX[9]), .Y(n590) );
NAND3X1TS U1028 ( .A(n588), .B(n610), .C(n590), .Y(n890) );
OAI22X1TS U1029 ( .A0(n587), .A1(n1257), .B0(n925), .B1(n1271), .Y(n595) );
NOR2X2TS U1030 ( .A(n588), .B(n610), .Y(n1135) );
NOR2X2TS U1031 ( .A(n591), .B(n590), .Y(n1136) );
OAI22X1TS U1032 ( .A0(n589), .A1(n1258), .B0(n592), .B1(n1265), .Y(n594) );
OAI31X1TS U1033 ( .A0(n595), .A1(n1141), .A2(n594), .B0(n593), .Y(n612) );
ADDHXLTS U1034 ( .A(n597), .B(n596), .CO(n1078), .S(n616) );
OAI22X1TS U1035 ( .A0(n587), .A1(n1264), .B0(n925), .B1(n1279), .Y(n600) );
OAI22X1TS U1036 ( .A0(n589), .A1(n1265), .B0(n592), .B1(n1271), .Y(n599) );
OAI31X1TS U1037 ( .A0(n600), .A1(n1141), .A2(n599), .B0(n598), .Y(n615) );
OAI22X1TS U1038 ( .A0(n587), .A1(n1270), .B0(n925), .B1(n407), .Y(n603) );
OAI22X1TS U1039 ( .A0(n589), .A1(n1271), .B0(n592), .B1(n1279), .Y(n602) );
OAI31X1TS U1040 ( .A0(n603), .A1(n1141), .A2(n602), .B0(n601), .Y(n1070) );
ADDHXLTS U1041 ( .A(Op_MX[14]), .B(n604), .CO(n596), .S(n1069) );
OAI22X1TS U1042 ( .A0(n587), .A1(n1276), .B0(n592), .B1(n407), .Y(n607) );
OAI22X1TS U1043 ( .A0(n589), .A1(n1279), .B0(n925), .B1(n1289), .Y(n606) );
OAI31X1TS U1044 ( .A0(n607), .A1(n1141), .A2(n606), .B0(n605), .Y(n1033) );
INVX2TS U1045 ( .A(n587), .Y(n1139) );
AOI222X1TS U1046 ( .A0(n1139), .A1(n1285), .B0(n1135), .B1(Op_MY[1]), .C0(
n1136), .C1(Op_MY[0]), .Y(n608) );
OAI21XLTS U1047 ( .A0(n610), .A1(n1289), .B0(Op_MX[11]), .Y(n609) );
CMPR32X2TS U1048 ( .A(n613), .B(n612), .C(n611), .CO(mult_x_19_n439), .S(
mult_x_19_n440) );
CMPR32X2TS U1049 ( .A(n616), .B(n615), .C(n614), .CO(n611), .S(
mult_x_19_n447) );
AOI2BB2X4TS U1050 ( .B0(n660), .B1(n408), .A0N(n408), .A1N(n660), .Y(n1164)
);
AOI21X1TS U1051 ( .A0(Op_MY[22]), .A1(n619), .B0(n656), .Y(n620) );
AOI21X1TS U1052 ( .A0(n522), .A1(n1164), .B0(n621), .Y(mult_x_19_n593) );
AOI22X1TS U1053 ( .A0(Op_MY[22]), .A1(n656), .B0(n522), .B1(n754), .Y(n623)
);
AOI21X1TS U1054 ( .A0(Op_MY[21]), .A1(n1112), .B0(n624), .Y(mult_x_19_n594)
);
AOI22X1TS U1055 ( .A0(n522), .A1(n750), .B0(n1112), .B1(Op_MY[20]), .Y(n626)
);
AOI21X1TS U1056 ( .A0(Op_MY[21]), .A1(n656), .B0(n627), .Y(mult_x_19_n595)
);
AOI22X1TS U1057 ( .A0(n657), .A1(n746), .B0(n1112), .B1(Op_MY[19]), .Y(n629)
);
AOI21X1TS U1058 ( .A0(n656), .A1(Op_MY[20]), .B0(n630), .Y(mult_x_19_n596)
);
AOI22X1TS U1059 ( .A0(n657), .A1(n742), .B0(n656), .B1(Op_MY[19]), .Y(n632)
);
AOI21X1TS U1060 ( .A0(n1112), .A1(Op_MY[18]), .B0(n633), .Y(mult_x_19_n597)
);
AOI22X1TS U1061 ( .A0(n657), .A1(n734), .B0(n1112), .B1(Op_MY[16]), .Y(n635)
);
AOI21X1TS U1062 ( .A0(n656), .A1(Op_MY[17]), .B0(n636), .Y(mult_x_19_n599)
);
AOI22X1TS U1063 ( .A0(n657), .A1(n730), .B0(n656), .B1(Op_MY[16]), .Y(n638)
);
AOI21X1TS U1064 ( .A0(n1112), .A1(Op_MY[15]), .B0(n639), .Y(mult_x_19_n600)
);
AOI22X1TS U1065 ( .A0(n657), .A1(n726), .B0(n1112), .B1(Op_MY[14]), .Y(n641)
);
AOI21X1TS U1066 ( .A0(n656), .A1(Op_MY[15]), .B0(n642), .Y(mult_x_19_n601)
);
AOI22X1TS U1067 ( .A0(n657), .A1(n722), .B0(n656), .B1(Op_MY[14]), .Y(n644)
);
AOI21X1TS U1068 ( .A0(n1112), .A1(Op_MY[13]), .B0(n645), .Y(mult_x_19_n602)
);
AOI22X1TS U1069 ( .A0(n657), .A1(n710), .B0(n1112), .B1(Op_MY[10]), .Y(n647)
);
AOI21X1TS U1070 ( .A0(n656), .A1(Op_MY[11]), .B0(n648), .Y(mult_x_19_n605)
);
AOI22X1TS U1071 ( .A0(n657), .A1(n706), .B0(n656), .B1(Op_MY[10]), .Y(n650)
);
AOI21X1TS U1072 ( .A0(n1112), .A1(Op_MY[9]), .B0(n651), .Y(mult_x_19_n606)
);
CMPR32X2TS U1073 ( .A(Op_MY[8]), .B(Op_MY[9]), .C(n652), .CO(n649), .S(n702)
);
AOI22X1TS U1074 ( .A0(n657), .A1(n702), .B0(n1112), .B1(Op_MY[8]), .Y(n653)
);
AOI21X1TS U1075 ( .A0(n656), .A1(Op_MY[9]), .B0(n654), .Y(mult_x_19_n607) );
AOI22X1TS U1076 ( .A0(n657), .A1(n698), .B0(n656), .B1(Op_MY[8]), .Y(n658)
);
AOI21X1TS U1077 ( .A0(n1112), .A1(Op_MY[7]), .B0(n659), .Y(mult_x_19_n608)
);
XOR2XLTS U1078 ( .A(Op_MX[20]), .B(n662), .Y(mult_x_19_n617) );
AOI21X1TS U1079 ( .A0(n1159), .A1(n1120), .B0(n663), .Y(n664) );
XOR2XLTS U1080 ( .A(n1629), .B(n664), .Y(mult_x_19_n618) );
XOR2XLTS U1081 ( .A(n470), .B(n665), .Y(mult_x_19_n644) );
AOI21X1TS U1082 ( .A0(n1159), .A1(n1126), .B0(n666), .Y(n667) );
XOR2X1TS U1083 ( .A(n1128), .B(n667), .Y(mult_x_19_n645) );
XOR2X1TS U1084 ( .A(Op_MX[14]), .B(n668), .Y(mult_x_19_n671) );
AOI21X1TS U1085 ( .A0(n1159), .A1(n1133), .B0(n669), .Y(n670) );
XOR2X1TS U1086 ( .A(n1630), .B(n670), .Y(mult_x_19_n672) );
XOR2X1TS U1087 ( .A(Op_MX[11]), .B(n671), .Y(mult_x_19_n698) );
AOI21X1TS U1088 ( .A0(n1159), .A1(n1139), .B0(n672), .Y(n673) );
XOR2X1TS U1089 ( .A(n1141), .B(n673), .Y(mult_x_19_n699) );
INVX2TS U1090 ( .A(n403), .Y(n1067) );
XNOR2X1TS U1091 ( .A(Op_MX[7]), .B(Op_MX[6]), .Y(n676) );
NAND3X1TS U1092 ( .A(n758), .B(n1067), .C(n676), .Y(n814) );
XOR2X1TS U1093 ( .A(Op_MX[8]), .B(n675), .Y(mult_x_19_n725) );
INVX2TS U1094 ( .A(n674), .Y(n1146) );
AOI21X1TS U1095 ( .A0(n1159), .A1(n1146), .B0(n678), .Y(n679) );
XOR2X1TS U1096 ( .A(n1631), .B(n679), .Y(mult_x_19_n726) );
OAI2BB2X2TS U1097 ( .B0(mult_x_19_n778), .B1(Op_MX[3]), .A0N(Op_MX[3]),
.A1N(mult_x_19_n778), .Y(n683) );
INVX2TS U1098 ( .A(n683), .Y(n1107) );
XNOR2X1TS U1099 ( .A(Op_MX[4]), .B(Op_MX[3]), .Y(n682) );
XOR2X1TS U1100 ( .A(Op_MX[5]), .B(n681), .Y(mult_x_19_n752) );
INVX2TS U1101 ( .A(n680), .Y(n1152) );
NOR2X2TS U1102 ( .A(n683), .B(n682), .Y(n1149) );
AOI21X1TS U1103 ( .A0(n1159), .A1(n1152), .B0(n685), .Y(n686) );
XOR2X1TS U1104 ( .A(n484), .B(n686), .Y(mult_x_19_n753) );
OAI22X1TS U1105 ( .A0(n680), .A1(n1251), .B0(n396), .B1(n1265), .Y(n693) );
NOR2X2TS U1106 ( .A(n689), .B(n1107), .Y(n1148) );
OAI22X1TS U1107 ( .A0(n690), .A1(mult_x_19_n282), .B0(n684), .B1(n1258), .Y(
n692) );
OAI31X1TS U1108 ( .A0(n693), .A1(n1103), .A2(n692), .B0(n691), .Y(
mult_x_19_n771) );
OAI22X1TS U1109 ( .A0(n680), .A1(n1244), .B0(n396), .B1(n1258), .Y(n697) );
OAI22X1TS U1110 ( .A0(n690), .A1(mult_x_19_n272), .B0(n684), .B1(
mult_x_19_n282), .Y(n696) );
OAI31X1TS U1111 ( .A0(n697), .A1(n1103), .A2(n696), .B0(n695), .Y(
mult_x_19_n770) );
INVX2TS U1112 ( .A(n698), .Y(n1237) );
OAI22X1TS U1113 ( .A0(n680), .A1(n1237), .B0(n690), .B1(n1236), .Y(n701) );
OAI22X1TS U1114 ( .A0(n684), .A1(mult_x_19_n272), .B0(n396), .B1(
mult_x_19_n282), .Y(n700) );
OAI31X1TS U1115 ( .A0(n701), .A1(n1103), .A2(n700), .B0(n699), .Y(
mult_x_19_n769) );
OAI22X1TS U1116 ( .A0(n680), .A1(n1228), .B0(n684), .B1(n1236), .Y(n705) );
OAI22X1TS U1117 ( .A0(n690), .A1(n1229), .B0(n396), .B1(mult_x_19_n272), .Y(
n704) );
OAI31X1TS U1118 ( .A0(n705), .A1(n1103), .A2(n704), .B0(n703), .Y(
mult_x_19_n768) );
OAI22X1TS U1119 ( .A0(n680), .A1(n1223), .B0(n396), .B1(n1236), .Y(n709) );
OAI22X1TS U1120 ( .A0(n690), .A1(n1224), .B0(n684), .B1(n1229), .Y(n708) );
OAI31X1TS U1121 ( .A0(n709), .A1(n1103), .A2(n708), .B0(n707), .Y(
mult_x_19_n767) );
OAI22X1TS U1122 ( .A0(n680), .A1(n1218), .B0(n684), .B1(n1224), .Y(n713) );
OAI22X1TS U1123 ( .A0(n690), .A1(n1219), .B0(n396), .B1(n1229), .Y(n712) );
OAI31X1TS U1124 ( .A0(n713), .A1(n1103), .A2(n712), .B0(n711), .Y(
mult_x_19_n766) );
OAI22X1TS U1125 ( .A0(n680), .A1(n1214), .B0(n396), .B1(n1224), .Y(n717) );
OAI22X1TS U1126 ( .A0(n690), .A1(mult_x_19_n227), .B0(n684), .B1(n1219), .Y(
n716) );
OAI31X1TS U1127 ( .A0(n717), .A1(n1103), .A2(n716), .B0(n715), .Y(
mult_x_19_n765) );
OAI22X1TS U1128 ( .A0(n680), .A1(n1210), .B0(n396), .B1(n1219), .Y(n721) );
OAI22X1TS U1129 ( .A0(n690), .A1(mult_x_19_n220), .B0(n684), .B1(
mult_x_19_n227), .Y(n720) );
OAI31X1TS U1130 ( .A0(n721), .A1(n1103), .A2(n720), .B0(n719), .Y(
mult_x_19_n764) );
OAI22X1TS U1131 ( .A0(n680), .A1(n1206), .B0(n690), .B1(n1205), .Y(n725) );
OAI22X1TS U1132 ( .A0(n684), .A1(mult_x_19_n220), .B0(n396), .B1(
mult_x_19_n227), .Y(n724) );
OAI31X1TS U1133 ( .A0(n725), .A1(n1096), .A2(n724), .B0(n723), .Y(
mult_x_19_n763) );
OAI22X1TS U1134 ( .A0(n680), .A1(n1200), .B0(n684), .B1(n1205), .Y(n729) );
OAI22X1TS U1135 ( .A0(n690), .A1(n1201), .B0(n396), .B1(mult_x_19_n220), .Y(
n728) );
OAI31X1TS U1136 ( .A0(n729), .A1(n1096), .A2(n728), .B0(n727), .Y(
mult_x_19_n762) );
OAI22X1TS U1137 ( .A0(n680), .A1(n1195), .B0(n396), .B1(n1205), .Y(n733) );
OAI22X1TS U1138 ( .A0(n690), .A1(n1196), .B0(n684), .B1(n1201), .Y(n732) );
OAI31X1TS U1139 ( .A0(n733), .A1(n484), .A2(n732), .B0(n731), .Y(
mult_x_19_n761) );
OAI22X1TS U1140 ( .A0(n680), .A1(n1190), .B0(n684), .B1(n1196), .Y(n737) );
OAI22X1TS U1141 ( .A0(n690), .A1(n1191), .B0(n396), .B1(n1201), .Y(n736) );
OAI31X1TS U1142 ( .A0(n737), .A1(n484), .A2(n736), .B0(n735), .Y(
mult_x_19_n760) );
OAI22X1TS U1143 ( .A0(n680), .A1(n1186), .B0(n396), .B1(n1196), .Y(n741) );
OAI22X1TS U1144 ( .A0(n690), .A1(n1628), .B0(n684), .B1(n1191), .Y(n740) );
OAI31X1TS U1145 ( .A0(n741), .A1(n484), .A2(n740), .B0(n739), .Y(
mult_x_19_n759) );
OAI22X1TS U1146 ( .A0(n680), .A1(n1181), .B0(n396), .B1(n1191), .Y(n745) );
OAI22X1TS U1147 ( .A0(n690), .A1(n1182), .B0(n684), .B1(n1628), .Y(n744) );
OAI31X1TS U1148 ( .A0(n745), .A1(n484), .A2(n744), .B0(n743), .Y(
mult_x_19_n758) );
INVX2TS U1149 ( .A(n746), .Y(n1176) );
OAI22X1TS U1150 ( .A0(n680), .A1(n1176), .B0(n684), .B1(n1182), .Y(n749) );
OAI22X1TS U1151 ( .A0(n690), .A1(n1177), .B0(n396), .B1(n1628), .Y(n748) );
OAI31X1TS U1152 ( .A0(n749), .A1(n1103), .A2(n748), .B0(n747), .Y(
mult_x_19_n757) );
INVX2TS U1153 ( .A(n750), .Y(n1171) );
OAI22X1TS U1154 ( .A0(n680), .A1(n1171), .B0(n396), .B1(n1182), .Y(n753) );
OAI22X1TS U1155 ( .A0(n1172), .A1(n690), .B0(n684), .B1(n1177), .Y(n752) );
OAI31X1TS U1156 ( .A0(n753), .A1(n1103), .A2(n752), .B0(n751), .Y(
mult_x_19_n756) );
INVX2TS U1157 ( .A(n754), .Y(n1167) );
OAI22X1TS U1158 ( .A0(n408), .A1(n690), .B0(n680), .B1(n1167), .Y(n757) );
OAI22X1TS U1159 ( .A0(n1172), .A1(n684), .B0(n396), .B1(n1177), .Y(n756) );
OAI31X1TS U1160 ( .A0(n757), .A1(n1103), .A2(n756), .B0(n755), .Y(
mult_x_19_n755) );
OAI22X1TS U1161 ( .A0(n674), .A1(n1264), .B0(n849), .B1(n1279), .Y(n762) );
OAI22X1TS U1162 ( .A0(n759), .A1(n1265), .B0(n677), .B1(n1271), .Y(n761) );
OAI21XLTS U1163 ( .A0(n762), .A1(n761), .B0(n815), .Y(n760) );
OAI31X1TS U1164 ( .A0(n762), .A1(n1631), .A2(n761), .B0(n760), .Y(
mult_x_19_n746) );
OAI22X1TS U1165 ( .A0(n674), .A1(n1270), .B0(n849), .B1(n407), .Y(n765) );
OAI22X1TS U1166 ( .A0(n759), .A1(n1271), .B0(n677), .B1(n1279), .Y(n764) );
OAI21XLTS U1167 ( .A0(n765), .A1(n764), .B0(n815), .Y(n763) );
OAI31X1TS U1168 ( .A0(n765), .A1(n1631), .A2(n764), .B0(n763), .Y(
mult_x_19_n747) );
OAI22X1TS U1169 ( .A0(n674), .A1(n1257), .B0(n849), .B1(n1271), .Y(n768) );
OAI22X1TS U1170 ( .A0(n759), .A1(n1258), .B0(n677), .B1(n1265), .Y(n767) );
OAI31X1TS U1171 ( .A0(n768), .A1(n1631), .A2(n767), .B0(n766), .Y(
mult_x_19_n745) );
OAI22X1TS U1172 ( .A0(n674), .A1(n1251), .B0(n849), .B1(n1265), .Y(n771) );
OAI22X1TS U1173 ( .A0(n759), .A1(mult_x_19_n282), .B0(n677), .B1(n1258), .Y(
n770) );
OAI31X1TS U1174 ( .A0(n771), .A1(n1631), .A2(n770), .B0(n769), .Y(
mult_x_19_n744) );
OAI22X1TS U1175 ( .A0(n674), .A1(n1244), .B0(n849), .B1(n1258), .Y(n774) );
OAI22X1TS U1176 ( .A0(n759), .A1(mult_x_19_n272), .B0(n677), .B1(
mult_x_19_n282), .Y(n773) );
OAI31X1TS U1177 ( .A0(n774), .A1(n1631), .A2(n773), .B0(n772), .Y(
mult_x_19_n743) );
OAI22X1TS U1178 ( .A0(n674), .A1(n1237), .B0(n759), .B1(n1236), .Y(n777) );
OAI22X1TS U1179 ( .A0(n677), .A1(mult_x_19_n272), .B0(n849), .B1(
mult_x_19_n282), .Y(n776) );
OAI31X1TS U1180 ( .A0(n777), .A1(n815), .A2(n776), .B0(n775), .Y(
mult_x_19_n742) );
OAI22X1TS U1181 ( .A0(n674), .A1(n1228), .B0(n677), .B1(n1236), .Y(n780) );
OAI22X1TS U1182 ( .A0(n759), .A1(n1229), .B0(n849), .B1(mult_x_19_n272), .Y(
n779) );
OAI31X1TS U1183 ( .A0(n780), .A1(n815), .A2(n779), .B0(n778), .Y(
mult_x_19_n741) );
OAI22X1TS U1184 ( .A0(n674), .A1(n1223), .B0(n849), .B1(n1236), .Y(n783) );
OAI22X1TS U1185 ( .A0(n759), .A1(n1224), .B0(n677), .B1(n1229), .Y(n782) );
OAI31X1TS U1186 ( .A0(n783), .A1(n482), .A2(n782), .B0(n781), .Y(
mult_x_19_n740) );
OAI22X1TS U1187 ( .A0(n674), .A1(n1218), .B0(n677), .B1(n1224), .Y(n786) );
OAI22X1TS U1188 ( .A0(n759), .A1(n1219), .B0(n849), .B1(n1229), .Y(n785) );
OAI31X1TS U1189 ( .A0(n786), .A1(n482), .A2(n785), .B0(n784), .Y(
mult_x_19_n739) );
OAI22X1TS U1190 ( .A0(n674), .A1(n1214), .B0(n849), .B1(n1224), .Y(n789) );
OAI22X1TS U1191 ( .A0(n759), .A1(mult_x_19_n227), .B0(n677), .B1(n1219), .Y(
n788) );
OAI31X1TS U1192 ( .A0(n789), .A1(n482), .A2(n788), .B0(n787), .Y(
mult_x_19_n738) );
OAI22X1TS U1193 ( .A0(n674), .A1(n1210), .B0(n849), .B1(n1219), .Y(n792) );
OAI22X1TS U1194 ( .A0(n759), .A1(mult_x_19_n220), .B0(n677), .B1(
mult_x_19_n227), .Y(n791) );
OAI31X1TS U1195 ( .A0(n792), .A1(n1631), .A2(n791), .B0(n790), .Y(
mult_x_19_n737) );
OAI22X1TS U1196 ( .A0(n674), .A1(n1206), .B0(n759), .B1(n1205), .Y(n795) );
OAI22X1TS U1197 ( .A0(n677), .A1(mult_x_19_n220), .B0(n849), .B1(
mult_x_19_n227), .Y(n794) );
OAI31X1TS U1198 ( .A0(n795), .A1(n1631), .A2(n794), .B0(n793), .Y(
mult_x_19_n736) );
OAI22X1TS U1199 ( .A0(n674), .A1(n1200), .B0(n677), .B1(n1205), .Y(n798) );
OAI22X1TS U1200 ( .A0(n759), .A1(n1201), .B0(n849), .B1(mult_x_19_n220), .Y(
n797) );
OAI31X1TS U1201 ( .A0(n798), .A1(n1631), .A2(n797), .B0(n796), .Y(
mult_x_19_n735) );
OAI22X1TS U1202 ( .A0(n587), .A1(n1251), .B0(n925), .B1(n1265), .Y(n801) );
OAI22X1TS U1203 ( .A0(n589), .A1(mult_x_19_n282), .B0(n592), .B1(n1258), .Y(
n800) );
OAI31X1TS U1204 ( .A0(n801), .A1(n1141), .A2(n800), .B0(n799), .Y(
mult_x_19_n717) );
OAI22X1TS U1205 ( .A0(n674), .A1(n1195), .B0(n849), .B1(n1205), .Y(n804) );
OAI22X1TS U1206 ( .A0(n759), .A1(n1196), .B0(n677), .B1(n1201), .Y(n803) );
OAI31X1TS U1207 ( .A0(n804), .A1(n1631), .A2(n803), .B0(n802), .Y(
mult_x_19_n734) );
OAI22X1TS U1208 ( .A0(n587), .A1(n1244), .B0(n925), .B1(n1258), .Y(n807) );
OAI22X1TS U1209 ( .A0(n589), .A1(mult_x_19_n272), .B0(n592), .B1(
mult_x_19_n282), .Y(n806) );
OAI31X1TS U1210 ( .A0(n807), .A1(n1141), .A2(n806), .B0(n805), .Y(
mult_x_19_n716) );
OAI22X1TS U1211 ( .A0(n674), .A1(n1190), .B0(n677), .B1(n1196), .Y(n810) );
OAI22X1TS U1212 ( .A0(n759), .A1(n1191), .B0(n814), .B1(n1201), .Y(n809) );
OAI31X1TS U1213 ( .A0(n810), .A1(n1631), .A2(n809), .B0(n808), .Y(
mult_x_19_n733) );
OAI22X1TS U1214 ( .A0(n587), .A1(n1237), .B0(n589), .B1(n1236), .Y(n813) );
OAI22X1TS U1215 ( .A0(n592), .A1(mult_x_19_n272), .B0(n925), .B1(
mult_x_19_n282), .Y(n812) );
OAI31X1TS U1216 ( .A0(n813), .A1(n914), .A2(n812), .B0(n811), .Y(
mult_x_19_n715) );
OAI22X1TS U1217 ( .A0(n674), .A1(n1186), .B0(n814), .B1(n1196), .Y(n818) );
OAI22X1TS U1218 ( .A0(n759), .A1(n1628), .B0(n677), .B1(n1191), .Y(n817) );
OAI31X1TS U1219 ( .A0(n818), .A1(n1631), .A2(n817), .B0(n816), .Y(
mult_x_19_n732) );
OAI22X1TS U1220 ( .A0(n587), .A1(n1223), .B0(n925), .B1(n1236), .Y(n821) );
OAI22X1TS U1221 ( .A0(n589), .A1(n1224), .B0(n592), .B1(n1229), .Y(n820) );
OAI31X1TS U1222 ( .A0(n821), .A1(n914), .A2(n820), .B0(n819), .Y(
mult_x_19_n713) );
OAI22X1TS U1223 ( .A0(n587), .A1(n1228), .B0(n592), .B1(n1236), .Y(n824) );
OAI22X1TS U1224 ( .A0(n589), .A1(n1229), .B0(n925), .B1(mult_x_19_n272), .Y(
n823) );
OAI31X1TS U1225 ( .A0(n824), .A1(n914), .A2(n823), .B0(n822), .Y(
mult_x_19_n714) );
OAI22X1TS U1226 ( .A0(n587), .A1(n1218), .B0(n592), .B1(n1224), .Y(n827) );
OAI22X1TS U1227 ( .A0(n589), .A1(n1219), .B0(n925), .B1(n1229), .Y(n826) );
OAI31X1TS U1228 ( .A0(n827), .A1(n914), .A2(n826), .B0(n825), .Y(
mult_x_19_n712) );
OAI22X1TS U1229 ( .A0(n674), .A1(n1181), .B0(n849), .B1(n1191), .Y(n830) );
OAI22X1TS U1230 ( .A0(n759), .A1(n1182), .B0(n677), .B1(n1628), .Y(n829) );
OAI31X1TS U1231 ( .A0(n830), .A1(n1631), .A2(n829), .B0(n828), .Y(
mult_x_19_n731) );
OAI22X1TS U1232 ( .A0(n587), .A1(n1214), .B0(n925), .B1(n1224), .Y(n833) );
OAI22X1TS U1233 ( .A0(n589), .A1(mult_x_19_n227), .B0(n592), .B1(n1219), .Y(
n832) );
OAI31X1TS U1234 ( .A0(n833), .A1(n1141), .A2(n832), .B0(n831), .Y(
mult_x_19_n711) );
OAI22X1TS U1235 ( .A0(n587), .A1(n1210), .B0(n925), .B1(n1219), .Y(n836) );
OAI22X1TS U1236 ( .A0(n589), .A1(mult_x_19_n220), .B0(n592), .B1(
mult_x_19_n227), .Y(n835) );
OAI31X1TS U1237 ( .A0(n836), .A1(n1141), .A2(n835), .B0(n834), .Y(
mult_x_19_n710) );
OAI22X1TS U1238 ( .A0(n587), .A1(n1206), .B0(n589), .B1(n1205), .Y(n839) );
OAI22X1TS U1239 ( .A0(n592), .A1(mult_x_19_n220), .B0(n925), .B1(
mult_x_19_n227), .Y(n838) );
OAI31X1TS U1240 ( .A0(n839), .A1(n1141), .A2(n838), .B0(n837), .Y(
mult_x_19_n709) );
OAI22X1TS U1241 ( .A0(n674), .A1(n1176), .B0(n677), .B1(n1182), .Y(n842) );
OAI22X1TS U1242 ( .A0(n759), .A1(n1177), .B0(n849), .B1(n1628), .Y(n841) );
OAI31X1TS U1243 ( .A0(n842), .A1(n1631), .A2(n841), .B0(n840), .Y(
mult_x_19_n730) );
OAI22X1TS U1244 ( .A0(n587), .A1(n1200), .B0(n592), .B1(n1205), .Y(n845) );
OAI22X1TS U1245 ( .A0(n589), .A1(n1201), .B0(n925), .B1(mult_x_19_n220), .Y(
n844) );
OAI31X1TS U1246 ( .A0(n845), .A1(n1141), .A2(n844), .B0(n843), .Y(
mult_x_19_n708) );
OAI22X1TS U1247 ( .A0(n587), .A1(n1195), .B0(n925), .B1(n1205), .Y(n848) );
OAI22X1TS U1248 ( .A0(n589), .A1(n1196), .B0(n592), .B1(n1201), .Y(n847) );
OAI31X1TS U1249 ( .A0(n848), .A1(n1141), .A2(n847), .B0(n846), .Y(
mult_x_19_n707) );
OAI22X1TS U1250 ( .A0(n674), .A1(n1171), .B0(n849), .B1(n1182), .Y(n852) );
OAI22X1TS U1251 ( .A0(n1172), .A1(n759), .B0(n677), .B1(n1177), .Y(n851) );
OAI31X1TS U1252 ( .A0(n852), .A1(n1631), .A2(n851), .B0(n850), .Y(
mult_x_19_n729) );
OAI22X1TS U1253 ( .A0(n408), .A1(n759), .B0(n674), .B1(n1167), .Y(n855) );
OAI22X1TS U1254 ( .A0(n1172), .A1(n677), .B0(n849), .B1(n1177), .Y(n854) );
OAI31X1TS U1255 ( .A0(n855), .A1(n1631), .A2(n854), .B0(n853), .Y(
mult_x_19_n728) );
INVX2TS U1256 ( .A(n468), .Y(n1156) );
AOI21X1TS U1257 ( .A0(Op_MX[0]), .A1(n1159), .B0(n468), .Y(n856) );
OAI32X1TS U1258 ( .A0(n406), .A1(n1156), .A2(n1159), .B0(n856), .B1(n1272),
.Y(mult_x_19_n779) );
OAI22X1TS U1259 ( .A0(n587), .A1(n1190), .B0(n592), .B1(n1196), .Y(n859) );
OAI22X1TS U1260 ( .A0(n589), .A1(n1191), .B0(n890), .B1(n1201), .Y(n858) );
OAI31X1TS U1261 ( .A0(n859), .A1(n1141), .A2(n858), .B0(n857), .Y(
mult_x_19_n706) );
OAI22X1TS U1262 ( .A0(n575), .A1(n1264), .B0(n974), .B1(n1279), .Y(n862) );
OAI22X1TS U1263 ( .A0(n578), .A1(n1265), .B0(n576), .B1(n1271), .Y(n861) );
OAI31X1TS U1264 ( .A0(n862), .A1(n1630), .A2(n861), .B0(n860), .Y(
mult_x_19_n692) );
OAI22X1TS U1265 ( .A0(n575), .A1(n1270), .B0(n974), .B1(n407), .Y(n865) );
OAI22X1TS U1266 ( .A0(n578), .A1(n1271), .B0(n576), .B1(n1279), .Y(n864) );
OAI31X1TS U1267 ( .A0(n865), .A1(n1630), .A2(n864), .B0(n863), .Y(
mult_x_19_n693) );
OAI22X1TS U1268 ( .A0(n575), .A1(n1257), .B0(n974), .B1(n1271), .Y(n868) );
OAI22X1TS U1269 ( .A0(n578), .A1(n1258), .B0(n576), .B1(n1265), .Y(n867) );
OAI31X1TS U1270 ( .A0(n868), .A1(n1630), .A2(n867), .B0(n866), .Y(
mult_x_19_n691) );
OAI22X1TS U1271 ( .A0(n575), .A1(n1251), .B0(n974), .B1(n1265), .Y(n871) );
OAI22X1TS U1272 ( .A0(n578), .A1(mult_x_19_n282), .B0(n576), .B1(n1258), .Y(
n870) );
OAI31X1TS U1273 ( .A0(n871), .A1(n1630), .A2(n870), .B0(n869), .Y(
mult_x_19_n690) );
OAI22X1TS U1274 ( .A0(n575), .A1(n1244), .B0(n974), .B1(n1258), .Y(n874) );
OAI22X1TS U1275 ( .A0(n578), .A1(mult_x_19_n272), .B0(n576), .B1(
mult_x_19_n282), .Y(n873) );
OAI31X1TS U1276 ( .A0(n874), .A1(n1630), .A2(n873), .B0(n872), .Y(
mult_x_19_n689) );
OAI22X1TS U1277 ( .A0(n575), .A1(n1237), .B0(n578), .B1(n1236), .Y(n877) );
OAI22X1TS U1278 ( .A0(n576), .A1(mult_x_19_n272), .B0(n974), .B1(
mult_x_19_n282), .Y(n876) );
OAI31X1TS U1279 ( .A0(n877), .A1(n1044), .A2(n876), .B0(n875), .Y(
mult_x_19_n688) );
OAI22X1TS U1280 ( .A0(n575), .A1(n1228), .B0(n576), .B1(n1236), .Y(n880) );
OAI22X1TS U1281 ( .A0(n578), .A1(n1229), .B0(n974), .B1(mult_x_19_n272), .Y(
n879) );
OAI31X1TS U1282 ( .A0(n880), .A1(n1044), .A2(n879), .B0(n878), .Y(
mult_x_19_n687) );
OAI22X1TS U1283 ( .A0(n575), .A1(n1223), .B0(n974), .B1(n1236), .Y(n883) );
OAI22X1TS U1284 ( .A0(n578), .A1(n1224), .B0(n576), .B1(n1229), .Y(n882) );
OAI31X1TS U1285 ( .A0(n883), .A1(n483), .A2(n882), .B0(n881), .Y(
mult_x_19_n686) );
OAI22X1TS U1286 ( .A0(n575), .A1(n1218), .B0(n576), .B1(n1224), .Y(n886) );
OAI22X1TS U1287 ( .A0(n578), .A1(n1219), .B0(n974), .B1(n1229), .Y(n885) );
OAI31X1TS U1288 ( .A0(n886), .A1(n483), .A2(n885), .B0(n884), .Y(
mult_x_19_n685) );
OAI22X1TS U1289 ( .A0(n575), .A1(n1214), .B0(n974), .B1(n1224), .Y(n889) );
OAI22X1TS U1290 ( .A0(n578), .A1(mult_x_19_n227), .B0(n576), .B1(n1219), .Y(
n888) );
OAI31X1TS U1291 ( .A0(n889), .A1(n483), .A2(n888), .B0(n887), .Y(
mult_x_19_n684) );
OAI22X1TS U1292 ( .A0(n587), .A1(n1186), .B0(n890), .B1(n1196), .Y(n893) );
OAI22X1TS U1293 ( .A0(n589), .A1(n1628), .B0(n592), .B1(n1191), .Y(n892) );
OAI31X1TS U1294 ( .A0(n893), .A1(n1141), .A2(n892), .B0(n891), .Y(
mult_x_19_n705) );
OAI22X1TS U1295 ( .A0(n575), .A1(n1210), .B0(n974), .B1(n1219), .Y(n896) );
OAI22X1TS U1296 ( .A0(n578), .A1(mult_x_19_n220), .B0(n576), .B1(
mult_x_19_n227), .Y(n895) );
OAI31X1TS U1297 ( .A0(n896), .A1(n1630), .A2(n895), .B0(n894), .Y(
mult_x_19_n683) );
OAI22X1TS U1298 ( .A0(n587), .A1(n1181), .B0(n925), .B1(n1191), .Y(n899) );
OAI22X1TS U1299 ( .A0(n589), .A1(n1182), .B0(n592), .B1(n1628), .Y(n898) );
OAI31X1TS U1300 ( .A0(n899), .A1(n1141), .A2(n898), .B0(n897), .Y(
mult_x_19_n704) );
OAI22X1TS U1301 ( .A0(n541), .A1(n1251), .B0(n1009), .B1(n1265), .Y(n902) );
OAI22X1TS U1302 ( .A0(n544), .A1(mult_x_19_n282), .B0(n547), .B1(n1258), .Y(
n901) );
OAI31X1TS U1303 ( .A0(n902), .A1(n1128), .A2(n901), .B0(n900), .Y(
mult_x_19_n663) );
OAI22X1TS U1304 ( .A0(n541), .A1(n1244), .B0(n1009), .B1(n1258), .Y(n905) );
OAI22X1TS U1305 ( .A0(n544), .A1(mult_x_19_n272), .B0(n547), .B1(
mult_x_19_n282), .Y(n904) );
OAI31X1TS U1306 ( .A0(n905), .A1(n1128), .A2(n904), .B0(n903), .Y(
mult_x_19_n662) );
OAI22X1TS U1307 ( .A0(n541), .A1(n1237), .B0(n544), .B1(n1236), .Y(n908) );
OAI22X1TS U1308 ( .A0(n547), .A1(mult_x_19_n272), .B0(n1009), .B1(
mult_x_19_n282), .Y(n907) );
OAI31X1TS U1309 ( .A0(n908), .A1(n1038), .A2(n907), .B0(n906), .Y(
mult_x_19_n661) );
OAI22X1TS U1310 ( .A0(n575), .A1(n1206), .B0(n578), .B1(n1205), .Y(n911) );
OAI22X1TS U1311 ( .A0(n576), .A1(mult_x_19_n220), .B0(n974), .B1(
mult_x_19_n227), .Y(n910) );
OAI31X1TS U1312 ( .A0(n911), .A1(n1630), .A2(n910), .B0(n909), .Y(
mult_x_19_n682) );
OAI22X1TS U1313 ( .A0(n587), .A1(n1176), .B0(n592), .B1(n1182), .Y(n915) );
OAI22X1TS U1314 ( .A0(n589), .A1(n1177), .B0(n925), .B1(n1628), .Y(n913) );
OAI31X1TS U1315 ( .A0(n915), .A1(n914), .A2(n913), .B0(n912), .Y(
mult_x_19_n703) );
OAI22X1TS U1316 ( .A0(n541), .A1(n1228), .B0(n547), .B1(n1236), .Y(n918) );
OAI22X1TS U1317 ( .A0(n544), .A1(n1229), .B0(n1009), .B1(mult_x_19_n272),
.Y(n917) );
OAI31X1TS U1318 ( .A0(n918), .A1(n1038), .A2(n917), .B0(n916), .Y(
mult_x_19_n660) );
OAI22X1TS U1319 ( .A0(n541), .A1(n1223), .B0(n1009), .B1(n1236), .Y(n921) );
OAI22X1TS U1320 ( .A0(n544), .A1(n1224), .B0(n547), .B1(n1229), .Y(n920) );
OAI31X1TS U1321 ( .A0(n921), .A1(n1038), .A2(n920), .B0(n919), .Y(
mult_x_19_n659) );
OAI22X1TS U1322 ( .A0(n575), .A1(n1200), .B0(n576), .B1(n1205), .Y(n924) );
OAI22X1TS U1323 ( .A0(n578), .A1(n1201), .B0(n974), .B1(mult_x_19_n220), .Y(
n923) );
OAI31X1TS U1324 ( .A0(n924), .A1(n1630), .A2(n923), .B0(n922), .Y(
mult_x_19_n681) );
OAI22X1TS U1325 ( .A0(n587), .A1(n1171), .B0(n925), .B1(n1182), .Y(n928) );
OAI22X1TS U1326 ( .A0(n1172), .A1(n589), .B0(n592), .B1(n1177), .Y(n927) );
OAI31X1TS U1327 ( .A0(n928), .A1(n1141), .A2(n927), .B0(n926), .Y(
mult_x_19_n702) );
OAI22X1TS U1328 ( .A0(n408), .A1(n589), .B0(n587), .B1(n1167), .Y(n931) );
OAI22X1TS U1329 ( .A0(n1172), .A1(n592), .B0(n925), .B1(n1177), .Y(n930) );
OAI31X1TS U1330 ( .A0(n931), .A1(n1141), .A2(n930), .B0(n929), .Y(
mult_x_19_n701) );
OAI22X1TS U1331 ( .A0(n575), .A1(n1195), .B0(n974), .B1(n1205), .Y(n934) );
OAI22X1TS U1332 ( .A0(n578), .A1(n1196), .B0(n576), .B1(n1201), .Y(n933) );
OAI31X1TS U1333 ( .A0(n934), .A1(n1630), .A2(n933), .B0(n932), .Y(
mult_x_19_n680) );
OAI22X1TS U1334 ( .A0(n528), .A1(n1270), .B0(n1025), .B1(n407), .Y(n937) );
OAI22X1TS U1335 ( .A0(n532), .A1(n1271), .B0(n530), .B1(n1279), .Y(n936) );
OAI31X1TS U1336 ( .A0(n937), .A1(n1629), .A2(n936), .B0(n935), .Y(
mult_x_19_n639) );
OAI22X1TS U1337 ( .A0(n528), .A1(n1264), .B0(n1025), .B1(n1279), .Y(n940) );
OAI22X1TS U1338 ( .A0(n532), .A1(n1265), .B0(n530), .B1(n1271), .Y(n939) );
OAI31X1TS U1339 ( .A0(n940), .A1(n1629), .A2(n939), .B0(n938), .Y(
mult_x_19_n638) );
OAI22X1TS U1340 ( .A0(n528), .A1(n1257), .B0(n1025), .B1(n1271), .Y(n943) );
OAI22X1TS U1341 ( .A0(n532), .A1(n1258), .B0(n530), .B1(n1265), .Y(n942) );
OAI31X1TS U1342 ( .A0(n943), .A1(n1629), .A2(n942), .B0(n941), .Y(
mult_x_19_n637) );
OAI22X1TS U1343 ( .A0(n528), .A1(n1251), .B0(n1025), .B1(n1265), .Y(n946) );
OAI22X1TS U1344 ( .A0(n532), .A1(mult_x_19_n282), .B0(n530), .B1(n1258), .Y(
n945) );
OAI31X1TS U1345 ( .A0(n946), .A1(n1629), .A2(n945), .B0(n944), .Y(
mult_x_19_n636) );
OAI22X1TS U1346 ( .A0(n528), .A1(n1244), .B0(n1025), .B1(n1258), .Y(n949) );
OAI22X1TS U1347 ( .A0(n532), .A1(mult_x_19_n272), .B0(n530), .B1(
mult_x_19_n282), .Y(n948) );
OAI31X1TS U1348 ( .A0(n949), .A1(n1629), .A2(n948), .B0(n947), .Y(
mult_x_19_n635) );
OAI22X1TS U1349 ( .A0(n541), .A1(n1214), .B0(n1009), .B1(n1224), .Y(n952) );
OAI22X1TS U1350 ( .A0(n544), .A1(mult_x_19_n227), .B0(n547), .B1(n1219), .Y(
n951) );
OAI31X1TS U1351 ( .A0(n952), .A1(n1128), .A2(n951), .B0(n950), .Y(
mult_x_19_n657) );
OAI22X1TS U1352 ( .A0(n541), .A1(n1210), .B0(n1009), .B1(n1219), .Y(n955) );
OAI22X1TS U1353 ( .A0(n544), .A1(mult_x_19_n220), .B0(n547), .B1(
mult_x_19_n227), .Y(n954) );
OAI31X1TS U1354 ( .A0(n955), .A1(n1128), .A2(n954), .B0(n953), .Y(
mult_x_19_n656) );
OAI22X1TS U1355 ( .A0(n575), .A1(n1181), .B0(n974), .B1(n1191), .Y(n958) );
OAI22X1TS U1356 ( .A0(n578), .A1(n1182), .B0(n576), .B1(n1628), .Y(n957) );
OAI31X1TS U1357 ( .A0(n958), .A1(n1630), .A2(n957), .B0(n956), .Y(
mult_x_19_n677) );
OAI22X1TS U1358 ( .A0(n528), .A1(n1237), .B0(n532), .B1(n1236), .Y(n961) );
OAI22X1TS U1359 ( .A0(n530), .A1(mult_x_19_n272), .B0(n1025), .B1(
mult_x_19_n282), .Y(n960) );
OAI31X1TS U1360 ( .A0(n961), .A1(n481), .A2(n960), .B0(n959), .Y(
mult_x_19_n634) );
OAI22X1TS U1361 ( .A0(n541), .A1(n1206), .B0(n544), .B1(n1205), .Y(n964) );
OAI22X1TS U1362 ( .A0(n547), .A1(mult_x_19_n220), .B0(n1009), .B1(
mult_x_19_n227), .Y(n963) );
OAI31X1TS U1363 ( .A0(n964), .A1(n1128), .A2(n963), .B0(n962), .Y(
mult_x_19_n655) );
OAI22X1TS U1364 ( .A0(n575), .A1(n1176), .B0(n576), .B1(n1182), .Y(n967) );
OAI22X1TS U1365 ( .A0(n578), .A1(n1177), .B0(n974), .B1(n1628), .Y(n966) );
OAI31X1TS U1366 ( .A0(n967), .A1(n1630), .A2(n966), .B0(n965), .Y(
mult_x_19_n676) );
OAI22X1TS U1367 ( .A0(n528), .A1(n1228), .B0(n530), .B1(n1236), .Y(n970) );
OAI22X1TS U1368 ( .A0(n532), .A1(n1229), .B0(n1025), .B1(mult_x_19_n272),
.Y(n969) );
OAI31X1TS U1369 ( .A0(n970), .A1(n481), .A2(n969), .B0(n968), .Y(
mult_x_19_n633) );
OAI22X1TS U1370 ( .A0(n541), .A1(n1200), .B0(n547), .B1(n1205), .Y(n973) );
OAI22X1TS U1371 ( .A0(n544), .A1(n1201), .B0(n1009), .B1(mult_x_19_n220),
.Y(n972) );
OAI31X1TS U1372 ( .A0(n973), .A1(n1128), .A2(n972), .B0(n971), .Y(
mult_x_19_n654) );
OAI22X1TS U1373 ( .A0(n575), .A1(n1171), .B0(n974), .B1(n1182), .Y(n977) );
OAI22X1TS U1374 ( .A0(n1172), .A1(n578), .B0(n576), .B1(n1177), .Y(n976) );
OAI31X1TS U1375 ( .A0(n977), .A1(n1630), .A2(n976), .B0(n975), .Y(
mult_x_19_n675) );
OAI22X1TS U1376 ( .A0(n528), .A1(n1223), .B0(n1025), .B1(n1236), .Y(n980) );
OAI22X1TS U1377 ( .A0(n532), .A1(n1224), .B0(n530), .B1(n1229), .Y(n979) );
OAI31X1TS U1378 ( .A0(n980), .A1(n481), .A2(n979), .B0(n978), .Y(
mult_x_19_n632) );
OAI22X1TS U1379 ( .A0(n541), .A1(n1195), .B0(n1009), .B1(n1205), .Y(n983) );
OAI22X1TS U1380 ( .A0(n544), .A1(n1196), .B0(n547), .B1(n1201), .Y(n982) );
OAI31X1TS U1381 ( .A0(n983), .A1(n1128), .A2(n982), .B0(n981), .Y(
mult_x_19_n653) );
OAI22X1TS U1382 ( .A0(n575), .A1(n1167), .B0(n974), .B1(n1177), .Y(n986) );
OAI22X1TS U1383 ( .A0(n408), .A1(n578), .B0(n1172), .B1(n576), .Y(n985) );
OAI31X1TS U1384 ( .A0(n986), .A1(n1630), .A2(n985), .B0(n984), .Y(
mult_x_19_n674) );
OAI22X1TS U1385 ( .A0(n541), .A1(n1190), .B0(n547), .B1(n1196), .Y(n989) );
OAI22X1TS U1386 ( .A0(n544), .A1(n1191), .B0(n990), .B1(n480), .Y(n988) );
OAI31X1TS U1387 ( .A0(n989), .A1(n1128), .A2(n988), .B0(n987), .Y(
mult_x_19_n652) );
OAI22X1TS U1388 ( .A0(n541), .A1(n1186), .B0(n990), .B1(n1196), .Y(n993) );
OAI22X1TS U1389 ( .A0(n544), .A1(n1628), .B0(n547), .B1(n1191), .Y(n992) );
OAI31X1TS U1390 ( .A0(n993), .A1(n1128), .A2(n992), .B0(n991), .Y(
mult_x_19_n651) );
OAI22X1TS U1391 ( .A0(n528), .A1(n1210), .B0(n1025), .B1(n1219), .Y(n996) );
OAI22X1TS U1392 ( .A0(n532), .A1(mult_x_19_n220), .B0(n530), .B1(
mult_x_19_n227), .Y(n995) );
OAI31X1TS U1393 ( .A0(n996), .A1(n1629), .A2(n995), .B0(n994), .Y(
mult_x_19_n629) );
OAI22X1TS U1394 ( .A0(n541), .A1(n1181), .B0(n1009), .B1(n1191), .Y(n999) );
OAI22X1TS U1395 ( .A0(n544), .A1(n1182), .B0(n547), .B1(n1628), .Y(n998) );
OAI31X1TS U1396 ( .A0(n999), .A1(n1128), .A2(n998), .B0(n997), .Y(
mult_x_19_n650) );
OAI22X1TS U1397 ( .A0(n528), .A1(n1206), .B0(n532), .B1(n1205), .Y(n1002) );
OAI22X1TS U1398 ( .A0(n530), .A1(mult_x_19_n220), .B0(n1025), .B1(
mult_x_19_n227), .Y(n1001) );
OAI31X1TS U1399 ( .A0(n1002), .A1(n1629), .A2(n1001), .B0(n1000), .Y(
mult_x_19_n628) );
OAI22X1TS U1400 ( .A0(n541), .A1(n1176), .B0(n547), .B1(n1182), .Y(n1005) );
OAI22X1TS U1401 ( .A0(n544), .A1(n1177), .B0(n1009), .B1(n1628), .Y(n1004)
);
OAI31X1TS U1402 ( .A0(n1005), .A1(n1038), .A2(n1004), .B0(n1003), .Y(
mult_x_19_n649) );
OAI22X1TS U1403 ( .A0(n528), .A1(n1200), .B0(n530), .B1(n1205), .Y(n1008) );
OAI22X1TS U1404 ( .A0(n532), .A1(n1201), .B0(n1025), .B1(mult_x_19_n220),
.Y(n1007) );
OAI31X1TS U1405 ( .A0(n1008), .A1(n1629), .A2(n1007), .B0(n1006), .Y(
mult_x_19_n627) );
OAI22X1TS U1406 ( .A0(n541), .A1(n1171), .B0(n1009), .B1(n1182), .Y(n1012)
);
OAI22X1TS U1407 ( .A0(n1172), .A1(n544), .B0(n547), .B1(n1177), .Y(n1011) );
OAI31X1TS U1408 ( .A0(n1012), .A1(n1128), .A2(n1011), .B0(n1010), .Y(
mult_x_19_n648) );
OAI22X1TS U1409 ( .A0(n528), .A1(n1195), .B0(n1025), .B1(n1205), .Y(n1015)
);
OAI22X1TS U1410 ( .A0(n532), .A1(n1196), .B0(n530), .B1(n480), .Y(n1014) );
OAI31X1TS U1411 ( .A0(n1015), .A1(n1629), .A2(n1014), .B0(n1013), .Y(
mult_x_19_n626) );
OAI22X1TS U1412 ( .A0(n541), .A1(n1167), .B0(n1009), .B1(n1177), .Y(n1018)
);
OAI22X1TS U1413 ( .A0(n408), .A1(n544), .B0(n1172), .B1(n547), .Y(n1017) );
OAI31X1TS U1414 ( .A0(n1018), .A1(n1128), .A2(n1017), .B0(n1016), .Y(
mult_x_19_n647) );
OAI22X1TS U1415 ( .A0(n528), .A1(n1181), .B0(n1025), .B1(n1191), .Y(n1021)
);
OAI22X1TS U1416 ( .A0(n532), .A1(n1182), .B0(n530), .B1(n1628), .Y(n1020) );
OAI31X1TS U1417 ( .A0(n1021), .A1(n1629), .A2(n1020), .B0(n1019), .Y(
mult_x_19_n623) );
OAI22X1TS U1418 ( .A0(n528), .A1(n1176), .B0(n530), .B1(n1182), .Y(n1024) );
OAI22X1TS U1419 ( .A0(n532), .A1(n1177), .B0(n1025), .B1(n476), .Y(n1023) );
OAI31X1TS U1420 ( .A0(n1024), .A1(n1629), .A2(n1023), .B0(n1022), .Y(
mult_x_19_n622) );
OAI22X1TS U1421 ( .A0(n528), .A1(n1171), .B0(n1025), .B1(n1182), .Y(n1028)
);
OAI22X1TS U1422 ( .A0(n1172), .A1(n532), .B0(n530), .B1(n1177), .Y(n1027) );
OAI31X1TS U1423 ( .A0(n1028), .A1(n1629), .A2(n1027), .B0(n1026), .Y(
mult_x_19_n621) );
OAI22X1TS U1424 ( .A0(n528), .A1(n1167), .B0(n1025), .B1(n1177), .Y(n1031)
);
OAI22X1TS U1425 ( .A0(n408), .A1(n532), .B0(n1172), .B1(n530), .Y(n1030) );
OAI31X1TS U1426 ( .A0(n1031), .A1(n1629), .A2(n1030), .B0(n1029), .Y(
mult_x_19_n620) );
OAI22X1TS U1427 ( .A0(n541), .A1(n1218), .B0(n547), .B1(n1224), .Y(n1039) );
OAI22X1TS U1428 ( .A0(n544), .A1(n1219), .B0(n1009), .B1(n1229), .Y(n1037)
);
OAI31X1TS U1429 ( .A0(n1039), .A1(n1038), .A2(n1037), .B0(n1036), .Y(
mult_x_19_n658) );
OAI22X1TS U1430 ( .A0(n575), .A1(n1190), .B0(n576), .B1(n1196), .Y(n1042) );
OAI22X1TS U1431 ( .A0(n578), .A1(n1191), .B0(n1043), .B1(n1201), .Y(n1041)
);
OAI31X1TS U1432 ( .A0(n1042), .A1(n1630), .A2(n1041), .B0(n1040), .Y(
mult_x_19_n679) );
OAI22X1TS U1433 ( .A0(n575), .A1(n1186), .B0(n1043), .B1(n1196), .Y(n1047)
);
OAI22X1TS U1434 ( .A0(n578), .A1(n1628), .B0(n576), .B1(n1191), .Y(n1046) );
OAI31X1TS U1435 ( .A0(n1047), .A1(n1630), .A2(n1046), .B0(n1045), .Y(
mult_x_19_n678) );
OAI22X1TS U1436 ( .A0(n528), .A1(n1218), .B0(n530), .B1(n1224), .Y(n1050) );
OAI22X1TS U1437 ( .A0(n532), .A1(n1219), .B0(n1025), .B1(n1229), .Y(n1049)
);
OAI31X1TS U1438 ( .A0(n1050), .A1(n481), .A2(n1049), .B0(n1048), .Y(
mult_x_19_n631) );
OAI22X1TS U1439 ( .A0(n528), .A1(n1214), .B0(n1025), .B1(n1224), .Y(n1053)
);
OAI22X1TS U1440 ( .A0(n532), .A1(mult_x_19_n227), .B0(n530), .B1(n1219), .Y(
n1052) );
OAI31X1TS U1441 ( .A0(n1053), .A1(n481), .A2(n1052), .B0(n1051), .Y(
mult_x_19_n630) );
OAI22X1TS U1442 ( .A0(n528), .A1(n1190), .B0(n530), .B1(n1196), .Y(n1056) );
OAI22X1TS U1443 ( .A0(n532), .A1(n1191), .B0(n1057), .B1(n480), .Y(n1055) );
OAI31X1TS U1444 ( .A0(n1056), .A1(n1629), .A2(n1055), .B0(n1054), .Y(
mult_x_19_n625) );
OAI22X1TS U1445 ( .A0(n528), .A1(n1186), .B0(n1057), .B1(n1196), .Y(n1061)
);
OAI22X1TS U1446 ( .A0(n532), .A1(n1628), .B0(n530), .B1(n1191), .Y(n1060) );
OAI31X1TS U1447 ( .A0(n1061), .A1(n1629), .A2(n1060), .B0(n1059), .Y(
mult_x_19_n624) );
OAI22X1TS U1448 ( .A0(n674), .A1(n1276), .B0(n677), .B1(n407), .Y(n1064) );
OAI22X1TS U1449 ( .A0(n759), .A1(n1279), .B0(n849), .B1(n1289), .Y(n1063) );
OAI21XLTS U1450 ( .A0(n1064), .A1(n1063), .B0(n1631), .Y(n1062) );
OAI31X1TS U1451 ( .A0(n1064), .A1(n1631), .A2(n1063), .B0(n1062), .Y(n1087)
);
XOR2XLTS U1452 ( .A(n1631), .B(n1065), .Y(n1092) );
OAI21XLTS U1453 ( .A0(n1067), .A1(n1289), .B0(Op_MX[8]), .Y(n1066) );
CMPR32X2TS U1454 ( .A(n1070), .B(n1069), .C(n1068), .CO(n614), .S(
mult_x_19_n454) );
CMPR32X2TS U1455 ( .A(n1073), .B(n1072), .C(n1071), .CO(n571), .S(
mult_x_19_n409) );
ADDHXLTS U1456 ( .A(n1075), .B(n1074), .CO(mult_x_19_n390), .S(n570) );
ADDHXLTS U1457 ( .A(n1077), .B(n1076), .CO(n1080), .S(mult_x_19_n370) );
ADDHXLTS U1458 ( .A(n1079), .B(n1078), .CO(mult_x_19_n441), .S(n613) );
ADDHXLTS U1459 ( .A(n1081), .B(n1080), .CO(n525), .S(mult_x_19_n359) );
INVX2TS U1460 ( .A(FS_Module_state_reg[1]), .Y(n1302) );
ADDHXLTS U1461 ( .A(n1087), .B(n1086), .CO(mult_x_19_n474), .S(n1235) );
OAI22X1TS U1462 ( .A0(n680), .A1(n1257), .B0(n396), .B1(n1271), .Y(n1090) );
OAI22X1TS U1463 ( .A0(n690), .A1(n1258), .B0(n684), .B1(n1265), .Y(n1089) );
OAI21XLTS U1464 ( .A0(n1090), .A1(n1089), .B0(n1096), .Y(n1088) );
OAI31X1TS U1465 ( .A0(n1090), .A1(n1103), .A2(n1089), .B0(n1088), .Y(n1234)
);
ADDHXLTS U1466 ( .A(n1092), .B(n1091), .CO(n1086), .S(n1243) );
OAI22X1TS U1467 ( .A0(n680), .A1(n1264), .B0(n396), .B1(n1279), .Y(n1095) );
OAI22X1TS U1468 ( .A0(n690), .A1(n1265), .B0(n684), .B1(n1271), .Y(n1094) );
OAI21XLTS U1469 ( .A0(n1095), .A1(n1094), .B0(n1096), .Y(n1093) );
OAI31X1TS U1470 ( .A0(n1095), .A1(n1103), .A2(n1094), .B0(n1093), .Y(n1242)
);
OAI22X1TS U1471 ( .A0(n680), .A1(n1270), .B0(n396), .B1(n407), .Y(n1099) );
OAI22X1TS U1472 ( .A0(n690), .A1(n1271), .B0(n684), .B1(n1279), .Y(n1098) );
OAI21XLTS U1473 ( .A0(n1099), .A1(n1098), .B0(n1096), .Y(n1097) );
OAI31X1TS U1474 ( .A0(n1099), .A1(n1103), .A2(n1098), .B0(n1097), .Y(n1250)
);
ADDHXLTS U1475 ( .A(Op_MX[8]), .B(n1100), .CO(n1091), .S(n1249) );
OAI22X1TS U1476 ( .A0(n680), .A1(n1276), .B0(n684), .B1(n407), .Y(n1104) );
OAI22X1TS U1477 ( .A0(n690), .A1(n1279), .B0(n396), .B1(n1289), .Y(n1102) );
OAI21XLTS U1478 ( .A0(n1104), .A1(n1102), .B0(n1103), .Y(n1101) );
OAI31X1TS U1479 ( .A0(n1104), .A1(n1103), .A2(n1102), .B0(n1101), .Y(n1256)
);
XOR2XLTS U1480 ( .A(n1103), .B(n1105), .Y(n1263) );
OAI21XLTS U1481 ( .A0(n1107), .A1(n1289), .B0(Op_MX[5]), .Y(n1106) );
NAND2X1TS U1482 ( .A(FS_Module_state_reg[3]), .B(n1632), .Y(n1303) );
NOR2X2TS U1483 ( .A(FS_Module_state_reg[0]), .B(n1303), .Y(n1389) );
NAND3XLTS U1484 ( .A(FS_Module_state_reg[1]), .B(FSM_add_overflow_flag), .C(
n1389), .Y(n1108) );
CLKINVX6TS U1485 ( .A(n1553), .Y(n1623) );
BUFX3TS U1486 ( .A(n1553), .Y(n1585) );
INVX2TS U1487 ( .A(n1159), .Y(n1110) );
AOI21X1TS U1488 ( .A0(n522), .A1(n1110), .B0(n1109), .Y(n1114) );
NOR2XLTS U1489 ( .A(n408), .B(n486), .Y(n1113) );
AOI211X1TS U1490 ( .A0(n1159), .A1(n522), .B0(n1113), .C0(n1112), .Y(n1115)
);
CMPR32X2TS U1491 ( .A(n1172), .B(Op_MY[22]), .C(n1114), .CO(n1291), .S(n1488) );
CMPR32X2TS U1492 ( .A(mult_x_19_n180), .B(n1172), .C(n1115), .CO(n1489), .S(
n1492) );
AOI21X1TS U1493 ( .A0(Op_MY[22]), .A1(n1117), .B0(n1116), .Y(n1118) );
AOI21X1TS U1494 ( .A0(n1120), .A1(n1164), .B0(n1119), .Y(n1121) );
XOR2X1TS U1495 ( .A(n1629), .B(n1121), .Y(n1501) );
AOI21X1TS U1496 ( .A0(Op_MY[22]), .A1(n1123), .B0(n1122), .Y(n1124) );
AOI21X1TS U1497 ( .A0(n1126), .A1(n1164), .B0(n1125), .Y(n1127) );
XOR2X1TS U1498 ( .A(n1128), .B(n1127), .Y(n1508) );
AOI21X1TS U1499 ( .A0(Op_MY[22]), .A1(n1130), .B0(n1129), .Y(n1131) );
AOI21X1TS U1500 ( .A0(n1133), .A1(n1164), .B0(n1132), .Y(n1134) );
XOR2X1TS U1501 ( .A(n1630), .B(n1134), .Y(n1515) );
AOI21X1TS U1502 ( .A0(Op_MY[22]), .A1(n1136), .B0(n1135), .Y(n1137) );
AOI21X1TS U1503 ( .A0(n1139), .A1(n1164), .B0(n1138), .Y(n1140) );
XOR2X1TS U1504 ( .A(n1141), .B(n1140), .Y(n1522) );
AOI21X1TS U1505 ( .A0(Op_MY[22]), .A1(n1143), .B0(n1142), .Y(n1144) );
AOI21X1TS U1506 ( .A0(n1146), .A1(n1164), .B0(n1145), .Y(n1147) );
XOR2X1TS U1507 ( .A(n1631), .B(n1147), .Y(n1529) );
AOI21X1TS U1508 ( .A0(Op_MY[22]), .A1(n1149), .B0(n1148), .Y(n1150) );
AOI21X1TS U1509 ( .A0(n1152), .A1(n1164), .B0(n1151), .Y(n1153) );
XOR2X1TS U1510 ( .A(n1096), .B(n1153), .Y(n1537) );
OAI22X1TS U1511 ( .A0(n1272), .A1(n468), .B0(n1156), .B1(Op_MX[2]), .Y(n1161) );
NAND2X1TS U1512 ( .A(n1161), .B(Op_MX[0]), .Y(n1154) );
INVX2TS U1513 ( .A(n1277), .Y(n1286) );
NAND3XLTS U1514 ( .A(n1156), .B(n406), .C(Op_MX[2]), .Y(n1155) );
AOI21X1TS U1515 ( .A0(n1159), .A1(n1286), .B0(n1158), .Y(n1160) );
XOR2X1TS U1516 ( .A(n1272), .B(n1160), .Y(n1542) );
AOI21X1TS U1517 ( .A0(Op_MY[22]), .A1(n1283), .B0(n1284), .Y(n1162) );
AOI21X1TS U1518 ( .A0(n1286), .A1(n1164), .B0(n1163), .Y(n1165) );
XOR2X1TS U1519 ( .A(n473), .B(n1165), .Y(n1545) );
OAI22X1TS U1520 ( .A0(n408), .A1(n1166), .B0(n1277), .B1(n1167), .Y(n1170)
);
OAI22X1TS U1521 ( .A0(n1172), .A1(n1157), .B0(n1278), .B1(n1177), .Y(n1169)
);
OAI22X1TS U1522 ( .A0(n1277), .A1(n1171), .B0(n1278), .B1(n1182), .Y(n1175)
);
OAI22X1TS U1523 ( .A0(n1172), .A1(n1166), .B0(n1157), .B1(n1177), .Y(n1174)
);
OAI22X1TS U1524 ( .A0(n1277), .A1(n1176), .B0(n1157), .B1(n1182), .Y(n1180)
);
OAI22X1TS U1525 ( .A0(n1166), .A1(n1177), .B0(n1278), .B1(n1628), .Y(n1179)
);
OAI31X1TS U1526 ( .A0(n1180), .A1(n473), .A2(n1179), .B0(n1178), .Y(n1555)
);
OAI22X1TS U1527 ( .A0(n1277), .A1(n1181), .B0(n1278), .B1(n1191), .Y(n1185)
);
OAI22X1TS U1528 ( .A0(n1166), .A1(n1182), .B0(n1157), .B1(n1628), .Y(n1184)
);
OAI31X1TS U1529 ( .A0(n1185), .A1(n473), .A2(n1184), .B0(n1183), .Y(n1558)
);
OAI22X1TS U1530 ( .A0(n1277), .A1(n1186), .B0(n1278), .B1(n1196), .Y(n1189)
);
OAI22X1TS U1531 ( .A0(n1166), .A1(n1628), .B0(n1157), .B1(n1191), .Y(n1188)
);
OAI31X1TS U1532 ( .A0(n1189), .A1(n473), .A2(n1188), .B0(n1187), .Y(n1561)
);
OAI22X1TS U1533 ( .A0(n1277), .A1(n1190), .B0(n1157), .B1(n1196), .Y(n1194)
);
OAI22X1TS U1534 ( .A0(n1166), .A1(n1191), .B0(n1278), .B1(n1201), .Y(n1193)
);
OAI22X1TS U1535 ( .A0(n1277), .A1(n1195), .B0(n1278), .B1(n1205), .Y(n1199)
);
OAI22X1TS U1536 ( .A0(n1166), .A1(n1196), .B0(n1157), .B1(n1201), .Y(n1198)
);
OAI22X1TS U1537 ( .A0(n1277), .A1(n1200), .B0(n1157), .B1(n1205), .Y(n1204)
);
OAI22X1TS U1538 ( .A0(n1166), .A1(n1201), .B0(n1278), .B1(mult_x_19_n220),
.Y(n1203) );
OAI22X1TS U1539 ( .A0(n1277), .A1(n1206), .B0(n1166), .B1(n1205), .Y(n1209)
);
OAI22X1TS U1540 ( .A0(n1157), .A1(mult_x_19_n220), .B0(n1278), .B1(
mult_x_19_n227), .Y(n1208) );
OAI21XLTS U1541 ( .A0(n1209), .A1(n1208), .B0(n1272), .Y(n1207) );
OAI22X1TS U1542 ( .A0(n1277), .A1(n1210), .B0(n1278), .B1(n1219), .Y(n1213)
);
OAI22X1TS U1543 ( .A0(n1166), .A1(mult_x_19_n220), .B0(n1157), .B1(
mult_x_19_n227), .Y(n1212) );
OAI21XLTS U1544 ( .A0(n1213), .A1(n1212), .B0(n1272), .Y(n1211) );
OAI22X1TS U1545 ( .A0(n1277), .A1(n1214), .B0(n1278), .B1(n1224), .Y(n1217)
);
OAI22X1TS U1546 ( .A0(n1166), .A1(mult_x_19_n227), .B0(n1157), .B1(n1219),
.Y(n1216) );
OAI21X1TS U1547 ( .A0(n1217), .A1(n1216), .B0(n1272), .Y(n1215) );
OAI22X1TS U1548 ( .A0(n1277), .A1(n1218), .B0(n1157), .B1(n1224), .Y(n1222)
);
OAI22X1TS U1549 ( .A0(n1166), .A1(n1219), .B0(n1278), .B1(n1229), .Y(n1221)
);
OAI21XLTS U1550 ( .A0(n1222), .A1(n1221), .B0(n1272), .Y(n1220) );
OAI22X1TS U1551 ( .A0(n1277), .A1(n1223), .B0(n1278), .B1(n1236), .Y(n1227)
);
OAI22X1TS U1552 ( .A0(n1166), .A1(n1224), .B0(n1157), .B1(n1229), .Y(n1226)
);
OAI22X1TS U1553 ( .A0(n1277), .A1(n1228), .B0(n1157), .B1(n1236), .Y(n1232)
);
OAI22X1TS U1554 ( .A0(n1166), .A1(n1229), .B0(n1278), .B1(mult_x_19_n272),
.Y(n1231) );
OAI21XLTS U1555 ( .A0(n1232), .A1(n1231), .B0(n1272), .Y(n1230) );
CMPR32X2TS U1556 ( .A(n1235), .B(n1234), .C(n1233), .CO(mult_x_19_n472), .S(
n1594) );
OAI22X1TS U1557 ( .A0(n1277), .A1(n1237), .B0(n1166), .B1(n1236), .Y(n1240)
);
OAI22X1TS U1558 ( .A0(n1157), .A1(mult_x_19_n272), .B0(n1278), .B1(
mult_x_19_n282), .Y(n1239) );
OAI21XLTS U1559 ( .A0(n1240), .A1(n1239), .B0(n1272), .Y(n1238) );
CMPR32X2TS U1560 ( .A(n1243), .B(n1242), .C(n1241), .CO(n1233), .S(n1598) );
OAI22X1TS U1561 ( .A0(n1277), .A1(n1244), .B0(n1278), .B1(n1258), .Y(n1247)
);
OAI22X1TS U1562 ( .A0(n1166), .A1(mult_x_19_n272), .B0(n1157), .B1(
mult_x_19_n282), .Y(n1246) );
CMPR32X2TS U1563 ( .A(n1250), .B(n1249), .C(n1248), .CO(n1241), .S(n1602) );
OAI22X1TS U1564 ( .A0(n1277), .A1(n1251), .B0(n1278), .B1(n1265), .Y(n1254)
);
OAI22X1TS U1565 ( .A0(n1166), .A1(mult_x_19_n282), .B0(n1157), .B1(n1258),
.Y(n1253) );
OAI21XLTS U1566 ( .A0(n1254), .A1(n1253), .B0(n1272), .Y(n1252) );
ADDHXLTS U1567 ( .A(n1256), .B(n1255), .CO(n1248), .S(n1606) );
OAI22X1TS U1568 ( .A0(n1277), .A1(n1257), .B0(n1278), .B1(n1271), .Y(n1261)
);
OAI22X1TS U1569 ( .A0(n1166), .A1(n1258), .B0(n1157), .B1(n1265), .Y(n1260)
);
OAI21XLTS U1570 ( .A0(n1261), .A1(n1260), .B0(n1272), .Y(n1259) );
ADDHXLTS U1571 ( .A(n1263), .B(n1262), .CO(n1255), .S(n1610) );
OAI22X1TS U1572 ( .A0(n1277), .A1(n1264), .B0(n1278), .B1(n1279), .Y(n1268)
);
OAI22X1TS U1573 ( .A0(n1166), .A1(n1265), .B0(n1157), .B1(n1271), .Y(n1267)
);
ADDHXLTS U1574 ( .A(Op_MX[5]), .B(n1269), .CO(n1262), .S(n1614) );
OAI22X1TS U1575 ( .A0(n1277), .A1(n1270), .B0(n1278), .B1(n407), .Y(n1275)
);
OAI22X1TS U1576 ( .A0(n1166), .A1(n1271), .B0(n1157), .B1(n1279), .Y(n1274)
);
OAI21XLTS U1577 ( .A0(n1275), .A1(n1274), .B0(n1272), .Y(n1273) );
OAI22X1TS U1578 ( .A0(n1277), .A1(n1276), .B0(n1157), .B1(n407), .Y(n1282)
);
OAI22X1TS U1579 ( .A0(n1166), .A1(n1279), .B0(n1278), .B1(n1289), .Y(n1281)
);
OAI21XLTS U1580 ( .A0(n1282), .A1(n1281), .B0(n1272), .Y(n1280) );
XOR2XLTS U1581 ( .A(n1272), .B(n1287), .Y(n1620) );
OAI21XLTS U1582 ( .A0(n406), .A1(n1289), .B0(Op_MX[2]), .Y(n1288) );
OAI31X1TS U1583 ( .A0(n406), .A1(Op_MX[2]), .A2(n1289), .B0(n1288), .Y(n1296) );
NAND2X1TS U1584 ( .A(n1645), .B(n1294), .Y(n1295) );
OR2X1TS U1585 ( .A(exp_oper_result[8]), .B(Exp_module_Overflow_flag_A), .Y(
overflow_flag) );
BUFX3TS U1586 ( .A(n167), .Y(n1680) );
BUFX3TS U1587 ( .A(n167), .Y(n1681) );
BUFX3TS U1588 ( .A(n1553), .Y(n1622) );
ADDHXLTS U1589 ( .A(Op_MX[2]), .B(n1296), .CO(n1619), .S(n1297) );
AO22XLTS U1590 ( .A0(n1623), .A1(P_Sgf[0]), .B0(n1622), .B1(n1297), .Y(n238)
);
BUFX3TS U1591 ( .A(n391), .Y(n1675) );
BUFX3TS U1592 ( .A(n391), .Y(n1674) );
BUFX3TS U1593 ( .A(n391), .Y(n1677) );
NOR2X1TS U1594 ( .A(n1302), .B(FS_Module_state_reg[2]), .Y(n1393) );
NOR2XLTS U1595 ( .A(FS_Module_state_reg[3]), .B(n1645), .Y(n1298) );
NAND2X1TS U1596 ( .A(n1393), .B(n1298), .Y(n1435) );
INVX2TS U1597 ( .A(n1435), .Y(n1434) );
NAND3XLTS U1598 ( .A(FS_Module_state_reg[3]), .B(n1391), .C(n1632), .Y(n1299) );
NOR2X1TS U1599 ( .A(FS_Module_state_reg[3]), .B(n1632), .Y(n1307) );
NAND2X1TS U1600 ( .A(n1391), .B(n1307), .Y(n1404) );
NOR2BX1TS U1601 ( .AN(P_Sgf[47]), .B(n1404), .Y(n1301) );
INVX2TS U1602 ( .A(n1301), .Y(n1300) );
OAI31X1TS U1603 ( .A0(n1434), .A1(n1486), .A2(n1641), .B0(n1300), .Y(n235)
);
OAI211XLTS U1604 ( .A0(n1301), .A1(n1640), .B0(n1484), .C0(n1435), .Y(n236)
);
NOR3XLTS U1605 ( .A(n1303), .B(n1302), .C(n1645), .Y(n1304) );
CLKBUFX3TS U1606 ( .A(n1304), .Y(n1627) );
XOR2X1TS U1607 ( .A(Op_MX[31]), .B(Op_MY[31]), .Y(n1371) );
NOR2XLTS U1608 ( .A(n1371), .B(underflow_flag), .Y(n1305) );
OAI32X1TS U1609 ( .A0(n1624), .A1(n1305), .A2(overflow_flag), .B0(n1627),
.B1(n1673), .Y(n168) );
AOI32X2TS U1610 ( .A0(FSM_add_overflow_flag), .A1(FS_Module_state_reg[1]),
.A2(n1389), .B0(n1306), .B1(FS_Module_state_reg[1]), .Y(n1437) );
NOR2XLTS U1611 ( .A(n1437), .B(n1644), .Y(n1309) );
AOI22X1TS U1612 ( .A0(n467), .A1(n394), .B0(n1356), .B1(n446), .Y(n1314) );
NAND2X1TS U1613 ( .A(n1308), .B(n1437), .Y(n1311) );
NOR2XLTS U1614 ( .A(FSM_selector_C), .B(n1311), .Y(n1310) );
NOR2XLTS U1615 ( .A(n1644), .B(n1311), .Y(n1312) );
AOI22X1TS U1616 ( .A0(n1361), .A1(P_Sgf[25]), .B0(n1360), .B1(Add_result[2]),
.Y(n1313) );
OAI211XLTS U1617 ( .A0(n1359), .A1(n1654), .B0(n1314), .C0(n1313), .Y(n204)
);
AOI22X1TS U1618 ( .A0(Sgf_normalized_result[0]), .A1(n394), .B0(n1356), .B1(
n457), .Y(n1316) );
AOI22X1TS U1619 ( .A0(n1361), .A1(P_Sgf[23]), .B0(n1360), .B1(Add_result[0]),
.Y(n1315) );
AOI22X1TS U1620 ( .A0(n469), .A1(n394), .B0(n1356), .B1(Add_result[2]), .Y(
n1318) );
AOI22X1TS U1621 ( .A0(n1361), .A1(P_Sgf[24]), .B0(n1360), .B1(n457), .Y(
n1317) );
OAI211XLTS U1622 ( .A0(n1359), .A1(n1655), .B0(n1318), .C0(n1317), .Y(n203)
);
AOI22X1TS U1623 ( .A0(Sgf_normalized_result[5]), .A1(n394), .B0(n459), .B1(
n1356), .Y(n1320) );
AOI22X1TS U1624 ( .A0(n1361), .A1(P_Sgf[28]), .B0(n1360), .B1(n447), .Y(
n1319) );
OAI211XLTS U1625 ( .A0(n1359), .A1(n1672), .B0(n1320), .C0(n1319), .Y(n207)
);
AOI22X1TS U1626 ( .A0(Sgf_normalized_result[3]), .A1(n394), .B0(n1356), .B1(
n448), .Y(n1322) );
AOI22X1TS U1627 ( .A0(n1361), .A1(P_Sgf[26]), .B0(n1360), .B1(n446), .Y(
n1321) );
OAI211XLTS U1628 ( .A0(n1359), .A1(n1653), .B0(n1322), .C0(n1321), .Y(n205)
);
AOI22X1TS U1629 ( .A0(Sgf_normalized_result[4]), .A1(n394), .B0(n1356), .B1(
n447), .Y(n1324) );
AOI22X1TS U1630 ( .A0(n1361), .A1(P_Sgf[27]), .B0(n1360), .B1(n448), .Y(
n1323) );
OAI211XLTS U1631 ( .A0(n1359), .A1(n1652), .B0(n1324), .C0(n1323), .Y(n206)
);
AOI22X1TS U1632 ( .A0(Sgf_normalized_result[17]), .A1(n394), .B0(n465), .B1(
n1356), .Y(n1326) );
AOI22X1TS U1633 ( .A0(n454), .A1(n1360), .B0(n1361), .B1(P_Sgf[40]), .Y(
n1325) );
OAI211XLTS U1634 ( .A0(n1359), .A1(n1660), .B0(n1326), .C0(n1325), .Y(n219)
);
AOI22X1TS U1635 ( .A0(Sgf_normalized_result[21]), .A1(n394), .B0(n458), .B1(
n1356), .Y(n1328) );
AOI22X1TS U1636 ( .A0(n456), .A1(n1360), .B0(n1361), .B1(P_Sgf[44]), .Y(
n1327) );
OAI211XLTS U1637 ( .A0(n1657), .A1(n1359), .B0(n1328), .C0(n1327), .Y(n223)
);
AOI22X1TS U1638 ( .A0(Sgf_normalized_result[7]), .A1(n394), .B0(n460), .B1(
n1356), .Y(n1330) );
AOI22X1TS U1639 ( .A0(n449), .A1(n1360), .B0(n1361), .B1(P_Sgf[30]), .Y(
n1329) );
OAI211XLTS U1640 ( .A0(n1359), .A1(n1670), .B0(n1330), .C0(n1329), .Y(n209)
);
AOI22X1TS U1641 ( .A0(Sgf_normalized_result[19]), .A1(n394), .B0(n466), .B1(
n1356), .Y(n1332) );
AOI22X1TS U1642 ( .A0(n455), .A1(n1360), .B0(n1361), .B1(P_Sgf[42]), .Y(
n1331) );
OAI211XLTS U1643 ( .A0(n1359), .A1(n1658), .B0(n1332), .C0(n1331), .Y(n221)
);
AOI22X1TS U1644 ( .A0(Sgf_normalized_result[15]), .A1(n394), .B0(n464), .B1(
n1356), .Y(n1334) );
AOI22X1TS U1645 ( .A0(n453), .A1(n1360), .B0(n1361), .B1(P_Sgf[38]), .Y(
n1333) );
OAI211XLTS U1646 ( .A0(n1359), .A1(n1662), .B0(n1334), .C0(n1333), .Y(n217)
);
AOI22X1TS U1647 ( .A0(Sgf_normalized_result[11]), .A1(n394), .B0(n462), .B1(
n1356), .Y(n1336) );
AOI22X1TS U1648 ( .A0(n451), .A1(n1360), .B0(n1361), .B1(P_Sgf[34]), .Y(
n1335) );
OAI211XLTS U1649 ( .A0(n1359), .A1(n1666), .B0(n1336), .C0(n1335), .Y(n213)
);
AOI22X1TS U1650 ( .A0(Sgf_normalized_result[9]), .A1(n394), .B0(n461), .B1(
n1356), .Y(n1338) );
AOI22X1TS U1651 ( .A0(n450), .A1(n1360), .B0(n1361), .B1(P_Sgf[32]), .Y(
n1337) );
OAI211XLTS U1652 ( .A0(n1359), .A1(n1668), .B0(n1338), .C0(n1337), .Y(n211)
);
AOI22X1TS U1653 ( .A0(Sgf_normalized_result[13]), .A1(n394), .B0(n463), .B1(
n1356), .Y(n1340) );
AOI22X1TS U1654 ( .A0(n452), .A1(n1360), .B0(n1361), .B1(P_Sgf[36]), .Y(
n1339) );
OAI211XLTS U1655 ( .A0(n1359), .A1(n1664), .B0(n1340), .C0(n1339), .Y(n215)
);
AOI22X1TS U1656 ( .A0(Sgf_normalized_result[10]), .A1(n394), .B0(n451), .B1(
n1356), .Y(n1342) );
AOI22X1TS U1657 ( .A0(n461), .A1(n1360), .B0(n1361), .B1(P_Sgf[33]), .Y(
n1341) );
OAI211XLTS U1658 ( .A0(n1359), .A1(n1667), .B0(n1342), .C0(n1341), .Y(n212)
);
AOI22X1TS U1659 ( .A0(Sgf_normalized_result[6]), .A1(n394), .B0(n449), .B1(
n1356), .Y(n1344) );
AOI22X1TS U1660 ( .A0(n459), .A1(n1360), .B0(n1361), .B1(P_Sgf[29]), .Y(
n1343) );
OAI211XLTS U1661 ( .A0(n1359), .A1(n1671), .B0(n1344), .C0(n1343), .Y(n208)
);
AOI22X1TS U1662 ( .A0(Sgf_normalized_result[20]), .A1(n394), .B0(n456), .B1(
n1356), .Y(n1346) );
AOI22X1TS U1663 ( .A0(n466), .A1(n1360), .B0(n1361), .B1(P_Sgf[43]), .Y(
n1345) );
OAI211XLTS U1664 ( .A0(n1651), .A1(n1359), .B0(n1346), .C0(n1345), .Y(n222)
);
AOI22X1TS U1665 ( .A0(Sgf_normalized_result[12]), .A1(n394), .B0(n452), .B1(
n1356), .Y(n1348) );
AOI22X1TS U1666 ( .A0(n462), .A1(n1360), .B0(n1361), .B1(P_Sgf[35]), .Y(
n1347) );
OAI211XLTS U1667 ( .A0(n1359), .A1(n1665), .B0(n1348), .C0(n1347), .Y(n214)
);
AOI22X1TS U1668 ( .A0(Sgf_normalized_result[8]), .A1(n394), .B0(n450), .B1(
n1356), .Y(n1350) );
AOI22X1TS U1669 ( .A0(n460), .A1(n1360), .B0(n1361), .B1(P_Sgf[31]), .Y(
n1349) );
OAI211XLTS U1670 ( .A0(n1359), .A1(n1669), .B0(n1350), .C0(n1349), .Y(n210)
);
AOI22X1TS U1671 ( .A0(Sgf_normalized_result[18]), .A1(n394), .B0(n455), .B1(
n1356), .Y(n1353) );
AOI22X1TS U1672 ( .A0(n465), .A1(n1360), .B0(n1361), .B1(P_Sgf[41]), .Y(
n1352) );
OAI211XLTS U1673 ( .A0(n1359), .A1(n1659), .B0(n1353), .C0(n1352), .Y(n220)
);
AOI22X1TS U1674 ( .A0(Sgf_normalized_result[16]), .A1(n394), .B0(n454), .B1(
n1356), .Y(n1355) );
AOI22X1TS U1675 ( .A0(n464), .A1(n1360), .B0(n1361), .B1(P_Sgf[39]), .Y(
n1354) );
AOI22X1TS U1676 ( .A0(Sgf_normalized_result[14]), .A1(n394), .B0(n453), .B1(
n1356), .Y(n1358) );
AOI22X1TS U1677 ( .A0(n463), .A1(n1360), .B0(n1361), .B1(P_Sgf[37]), .Y(
n1357) );
OAI211XLTS U1678 ( .A0(n1359), .A1(n1663), .B0(n1358), .C0(n1357), .Y(n216)
);
AOI22X1TS U1679 ( .A0(FSM_selector_C), .A1(Add_result[23]), .B0(P_Sgf[46]),
.B1(n1644), .Y(n1436) );
AOI22X1TS U1680 ( .A0(Sgf_normalized_result[22]), .A1(n394), .B0(n458), .B1(
n1360), .Y(n1363) );
NAND2X1TS U1681 ( .A(n1361), .B(P_Sgf[45]), .Y(n1362) );
OAI211XLTS U1682 ( .A0(n1437), .A1(n1436), .B0(n1363), .C0(n1362), .Y(n224)
);
INVX2TS U1683 ( .A(n1389), .Y(n1374) );
NOR4X1TS U1684 ( .A(P_Sgf[14]), .B(P_Sgf[15]), .C(P_Sgf[16]), .D(P_Sgf[17]),
.Y(n1370) );
NOR4X1TS U1685 ( .A(P_Sgf[18]), .B(P_Sgf[19]), .C(P_Sgf[20]), .D(P_Sgf[21]),
.Y(n1369) );
NOR4X1TS U1686 ( .A(P_Sgf[2]), .B(P_Sgf[3]), .C(P_Sgf[4]), .D(P_Sgf[5]), .Y(
n1367) );
NOR3XLTS U1687 ( .A(P_Sgf[22]), .B(P_Sgf[0]), .C(P_Sgf[1]), .Y(n1366) );
NOR4X1TS U1688 ( .A(P_Sgf[10]), .B(P_Sgf[11]), .C(P_Sgf[12]), .D(P_Sgf[13]),
.Y(n1365) );
AND4X1TS U1689 ( .A(n1367), .B(n1366), .C(n1365), .D(n1364), .Y(n1368) );
NAND3XLTS U1690 ( .A(n1370), .B(n1369), .C(n1368), .Y(n1373) );
MXI2X1TS U1691 ( .A(round_mode[0]), .B(round_mode[1]), .S0(n1371), .Y(n1372)
);
OAI211X1TS U1692 ( .A0(round_mode[0]), .A1(round_mode[1]), .B0(n1373), .C0(
n1372), .Y(n1388) );
OAI31X1TS U1693 ( .A0(FS_Module_state_reg[1]), .A1(n1374), .A2(n1388), .B0(
n1644), .Y(n375) );
NAND2X1TS U1694 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[3]),
.Y(n1390) );
NOR3X1TS U1695 ( .A(FS_Module_state_reg[1]), .B(FS_Module_state_reg[0]), .C(
n1390), .Y(ready) );
AOI22X1TS U1696 ( .A0(DP_OP_32J15_122_6543_n33), .A1(n474), .B0(n1632), .B1(
n1645), .Y(n1376) );
INVX2TS U1697 ( .A(ready), .Y(n1375) );
OAI22X1TS U1698 ( .A0(n1376), .A1(n1402), .B0(P_Sgf[47]), .B1(n1404), .Y(
n379) );
INVX2TS U1699 ( .A(DP_OP_32J15_122_6543_n33), .Y(n1405) );
OAI21XLTS U1700 ( .A0(n1632), .A1(n1402), .B0(FS_Module_state_reg[3]), .Y(
n1377) );
OAI211XLTS U1701 ( .A0(n474), .A1(n1405), .B0(n394), .C0(n1377), .Y(n380) );
NOR3BX1TS U1702 ( .AN(n445), .B(FSM_selector_B[0]), .C(FSM_selector_B[1]),
.Y(n1378) );
XOR2X1TS U1703 ( .A(DP_OP_32J15_122_6543_n33), .B(n1378), .Y(
DP_OP_32J15_122_6543_n15) );
OR2X2TS U1704 ( .A(FSM_selector_B[1]), .B(n1640), .Y(n1385) );
OAI2BB1X1TS U1705 ( .A0N(n438), .A1N(n1641), .B0(n1385), .Y(n1379) );
XOR2X1TS U1706 ( .A(DP_OP_32J15_122_6543_n33), .B(n1379), .Y(
DP_OP_32J15_122_6543_n16) );
OAI2BB1X1TS U1707 ( .A0N(n439), .A1N(n1641), .B0(n1385), .Y(n1380) );
XOR2X1TS U1708 ( .A(DP_OP_32J15_122_6543_n33), .B(n1380), .Y(
DP_OP_32J15_122_6543_n17) );
OAI2BB1X1TS U1709 ( .A0N(Op_MY[27]), .A1N(n1641), .B0(n1385), .Y(n1381) );
XOR2X1TS U1710 ( .A(DP_OP_32J15_122_6543_n33), .B(n1381), .Y(
DP_OP_32J15_122_6543_n18) );
OAI2BB1X1TS U1711 ( .A0N(n444), .A1N(n1641), .B0(n1385), .Y(n1382) );
XOR2X1TS U1712 ( .A(DP_OP_32J15_122_6543_n33), .B(n1382), .Y(
DP_OP_32J15_122_6543_n19) );
OAI2BB1X1TS U1713 ( .A0N(n443), .A1N(n1641), .B0(n1385), .Y(n1383) );
XOR2X1TS U1714 ( .A(DP_OP_32J15_122_6543_n33), .B(n1383), .Y(
DP_OP_32J15_122_6543_n20) );
OAI2BB1X1TS U1715 ( .A0N(n440), .A1N(n1641), .B0(n1385), .Y(n1384) );
XOR2X1TS U1716 ( .A(DP_OP_32J15_122_6543_n33), .B(n1384), .Y(
DP_OP_32J15_122_6543_n21) );
NOR2XLTS U1717 ( .A(FSM_selector_B[1]), .B(Op_MY[23]), .Y(n1386) );
XOR2X1TS U1718 ( .A(DP_OP_32J15_122_6543_n33), .B(n1387), .Y(
DP_OP_32J15_122_6543_n22) );
AOI22X1TS U1719 ( .A0(n1391), .A1(n1390), .B0(n1389), .B1(n1388), .Y(n1392)
);
OAI2BB1X1TS U1720 ( .A0N(n1393), .A1N(n1645), .B0(n1392), .Y(n378) );
AO22XLTS U1721 ( .A0(Data_MY[26]), .A1(n1412), .B0(n1401), .B1(n444), .Y(
n338) );
AO22XLTS U1722 ( .A0(Data_MY[25]), .A1(n1412), .B0(n1401), .B1(n443), .Y(
n337) );
AO22XLTS U1723 ( .A0(Data_MY[30]), .A1(n1412), .B0(n1401), .B1(n445), .Y(
n342) );
AO22XLTS U1724 ( .A0(Data_MY[24]), .A1(n1412), .B0(n1401), .B1(n440), .Y(
n336) );
AO22XLTS U1725 ( .A0(Data_MY[29]), .A1(n1412), .B0(n1401), .B1(n438), .Y(
n341) );
AO22XLTS U1726 ( .A0(Data_MY[28]), .A1(n1412), .B0(n1401), .B1(n439), .Y(
n340) );
BUFX3TS U1727 ( .A(n1401), .Y(n1409) );
MX2X1TS U1728 ( .A(Op_MY[23]), .B(Data_MY[23]), .S0(n1412), .Y(n335) );
NAND2X1TS U1729 ( .A(n1435), .B(n1647), .Y(n376) );
NOR2BX1TS U1730 ( .AN(exp_oper_result[8]), .B(n1647), .Y(S_Oper_A_exp[8]) );
MX2X1TS U1731 ( .A(Exp_module_Data_S[7]), .B(exp_oper_result[7]), .S0(n1395),
.Y(n227) );
MX2X1TS U1732 ( .A(n441), .B(exp_oper_result[7]), .S0(FSM_selector_A), .Y(
S_Oper_A_exp[7]) );
MX2X1TS U1733 ( .A(Exp_module_Data_S[6]), .B(exp_oper_result[6]), .S0(n1395),
.Y(n228) );
MX2X1TS U1734 ( .A(n442), .B(exp_oper_result[6]), .S0(FSM_selector_A), .Y(
S_Oper_A_exp[6]) );
MX2X1TS U1735 ( .A(Exp_module_Data_S[5]), .B(exp_oper_result[5]), .S0(n1395),
.Y(n229) );
MX2X1TS U1736 ( .A(Op_MX[28]), .B(exp_oper_result[5]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[5]) );
MX2X1TS U1737 ( .A(Exp_module_Data_S[4]), .B(exp_oper_result[4]), .S0(n1395),
.Y(n230) );
MX2X1TS U1738 ( .A(Op_MX[27]), .B(exp_oper_result[4]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[4]) );
MX2X1TS U1739 ( .A(Exp_module_Data_S[3]), .B(exp_oper_result[3]), .S0(n1395),
.Y(n231) );
MX2X1TS U1740 ( .A(Op_MX[26]), .B(exp_oper_result[3]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[3]) );
MX2X1TS U1741 ( .A(Exp_module_Data_S[2]), .B(exp_oper_result[2]), .S0(n1395),
.Y(n232) );
MX2X1TS U1742 ( .A(Op_MX[25]), .B(exp_oper_result[2]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[2]) );
MX2X1TS U1743 ( .A(Exp_module_Data_S[1]), .B(exp_oper_result[1]), .S0(n1395),
.Y(n233) );
MX2X1TS U1744 ( .A(Op_MX[24]), .B(exp_oper_result[1]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[1]) );
MX2X1TS U1745 ( .A(Exp_module_Data_S[0]), .B(exp_oper_result[0]), .S0(n1395),
.Y(n234) );
MX2X1TS U1746 ( .A(Op_MX[23]), .B(exp_oper_result[0]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[0]) );
MX2X1TS U1747 ( .A(Exp_module_Data_S[8]), .B(exp_oper_result[8]), .S0(n1395),
.Y(n226) );
XNOR2X1TS U1748 ( .A(DP_OP_32J15_122_6543_n1), .B(n1405), .Y(n1397) );
MX2X1TS U1749 ( .A(n1397), .B(Exp_module_Overflow_flag_A), .S0(n1623), .Y(
n225) );
NAND4XLTS U1750 ( .A(Exp_module_Data_S[3]), .B(Exp_module_Data_S[2]), .C(
Exp_module_Data_S[1]), .D(Exp_module_Data_S[0]), .Y(n1398) );
NAND4BXLTS U1751 ( .AN(n1398), .B(Exp_module_Data_S[6]), .C(
Exp_module_Data_S[5]), .D(Exp_module_Data_S[4]), .Y(n1399) );
NAND3BXLTS U1752 ( .AN(Exp_module_Data_S[7]), .B(n1434), .C(n1399), .Y(n1400) );
OAI22X1TS U1753 ( .A0(Exp_module_Data_S[8]), .A1(n1400), .B0(n1434), .B1(
n1648), .Y(n201) );
AO22XLTS U1754 ( .A0(n1412), .A1(Data_MY[31]), .B0(n1401), .B1(Op_MY[31]),
.Y(n381) );
AOI32X1TS U1755 ( .A0(FS_Module_state_reg[1]), .A1(n1632), .A2(
FS_Module_state_reg[0]), .B0(FS_Module_state_reg[2]), .B1(n1402), .Y(
n1406) );
NAND3XLTS U1756 ( .A(n1406), .B(n1405), .C(n1404), .Y(n377) );
BUFX3TS U1757 ( .A(n1401), .Y(n1411) );
BUFX3TS U1758 ( .A(n1401), .Y(n1407) );
AO22XLTS U1759 ( .A0(n1412), .A1(Data_MX[31]), .B0(n1407), .B1(Op_MX[31]),
.Y(n343) );
NOR4X1TS U1760 ( .A(n444), .B(n443), .C(n445), .D(n440), .Y(n1414) );
NAND4XLTS U1761 ( .A(n1416), .B(n1415), .C(n1414), .D(n1413), .Y(n1432) );
NOR4X1TS U1762 ( .A(Op_MY[10]), .B(Op_MY[11]), .C(Op_MY[12]), .D(Op_MY[13]),
.Y(n1418) );
NOR4X1TS U1763 ( .A(Op_MY[6]), .B(Op_MY[7]), .C(Op_MY[8]), .D(Op_MY[9]), .Y(
n1417) );
NAND4XLTS U1764 ( .A(n1420), .B(n1419), .C(n1418), .D(n1417), .Y(n1431) );
NOR4X1TS U1765 ( .A(Op_MX[27]), .B(Op_MX[26]), .C(Op_MX[23]), .D(Op_MX[25]),
.Y(n1422) );
NAND4XLTS U1766 ( .A(n1424), .B(n1423), .C(n1422), .D(n1421), .Y(n1430) );
NAND4XLTS U1767 ( .A(n1428), .B(n1427), .C(n1426), .D(n1425), .Y(n1429) );
OAI22X1TS U1768 ( .A0(n1432), .A1(n1431), .B0(n1430), .B1(n1429), .Y(n1433)
);
AO22XLTS U1769 ( .A0(n1435), .A1(zero_flag), .B0(n1434), .B1(n1433), .Y(n311) );
AOI32X1TS U1770 ( .A0(n1437), .A1(n1308), .A2(n1436), .B0(n1650), .B1(n394),
.Y(n310) );
AOI2BB2XLTS U1771 ( .B0(n1486), .B1(Sgf_normalized_result[0]), .A0N(
Add_result[0]), .A1N(n1476), .Y(n309) );
NOR2XLTS U1772 ( .A(n469), .B(Sgf_normalized_result[0]), .Y(n1438) );
AOI21X1TS U1773 ( .A0(Sgf_normalized_result[0]), .A1(n469), .B0(n1438), .Y(
n1439) );
AOI2BB2XLTS U1774 ( .B0(n1486), .B1(n1439), .A0N(n457), .A1N(n1476), .Y(n308) );
OR3X1TS U1775 ( .A(n467), .B(n469), .C(Sgf_normalized_result[0]), .Y(n1441)
);
OAI21XLTS U1776 ( .A0(n469), .A1(Sgf_normalized_result[0]), .B0(n467), .Y(
n1440) );
AOI32X1TS U1777 ( .A0(n1441), .A1(n1486), .A2(n1440), .B0(n1649), .B1(n1484),
.Y(n307) );
BUFX4TS U1778 ( .A(n1484), .Y(n1481) );
NAND2X1TS U1779 ( .A(Sgf_normalized_result[3]), .B(n1441), .Y(n1443) );
OAI2BB1X1TS U1780 ( .A0N(n446), .A1N(n1481), .B0(n1442), .Y(n306) );
NAND2X1TS U1781 ( .A(n1633), .B(n1443), .Y(n1445) );
OAI21XLTS U1782 ( .A0(n1443), .A1(n1633), .B0(n1445), .Y(n1444) );
NAND2X1TS U1783 ( .A(Sgf_normalized_result[5]), .B(n1445), .Y(n1447) );
OAI2BB1X1TS U1784 ( .A0N(n447), .A1N(n1481), .B0(n1446), .Y(n304) );
AOI21X1TS U1785 ( .A0(n1634), .A1(n1447), .B0(n436), .Y(n1448) );
NAND2X1TS U1786 ( .A(Sgf_normalized_result[7]), .B(n436), .Y(n1450) );
OAI211XLTS U1787 ( .A0(Sgf_normalized_result[7]), .A1(n436), .B0(n1476),
.C0(n1450), .Y(n1449) );
OAI2BB1X1TS U1788 ( .A0N(n449), .A1N(n1481), .B0(n1449), .Y(n302) );
AOI21X1TS U1789 ( .A0(n1635), .A1(n1450), .B0(n1452), .Y(n1451) );
NAND2X1TS U1790 ( .A(Sgf_normalized_result[9]), .B(n1452), .Y(n1454) );
OAI211XLTS U1791 ( .A0(Sgf_normalized_result[9]), .A1(n1452), .B0(n1476),
.C0(n1454), .Y(n1453) );
OAI2BB1X1TS U1792 ( .A0N(n450), .A1N(n1481), .B0(n1453), .Y(n300) );
AOI21X1TS U1793 ( .A0(n1636), .A1(n1454), .B0(n1456), .Y(n1455) );
NAND2X1TS U1794 ( .A(Sgf_normalized_result[11]), .B(n1456), .Y(n1458) );
OAI211XLTS U1795 ( .A0(Sgf_normalized_result[11]), .A1(n1456), .B0(n1476),
.C0(n1458), .Y(n1457) );
OAI2BB1X1TS U1796 ( .A0N(n451), .A1N(n1481), .B0(n1457), .Y(n298) );
AOI21X1TS U1797 ( .A0(n1637), .A1(n1458), .B0(n1460), .Y(n1459) );
NAND2X1TS U1798 ( .A(Sgf_normalized_result[13]), .B(n1460), .Y(n1462) );
OAI211XLTS U1799 ( .A0(Sgf_normalized_result[13]), .A1(n1460), .B0(n1476),
.C0(n1462), .Y(n1461) );
OAI2BB1X1TS U1800 ( .A0N(n452), .A1N(n1481), .B0(n1461), .Y(n296) );
AOI21X1TS U1801 ( .A0(n1638), .A1(n1462), .B0(n1464), .Y(n1463) );
NAND2X1TS U1802 ( .A(Sgf_normalized_result[15]), .B(n1464), .Y(n1466) );
OAI2BB1X1TS U1803 ( .A0N(n453), .A1N(n1481), .B0(n1465), .Y(n294) );
AOI21X1TS U1804 ( .A0(n1639), .A1(n1466), .B0(n1468), .Y(n1467) );
NAND2X1TS U1805 ( .A(Sgf_normalized_result[17]), .B(n1468), .Y(n1470) );
OAI211XLTS U1806 ( .A0(Sgf_normalized_result[17]), .A1(n1468), .B0(n1476),
.C0(n1470), .Y(n1469) );
OAI2BB1X1TS U1807 ( .A0N(n454), .A1N(n1481), .B0(n1469), .Y(n292) );
AOI21X1TS U1808 ( .A0(n1642), .A1(n1470), .B0(n1472), .Y(n1471) );
NAND2X1TS U1809 ( .A(Sgf_normalized_result[19]), .B(n1472), .Y(n1474) );
OAI211XLTS U1810 ( .A0(Sgf_normalized_result[19]), .A1(n1472), .B0(n1476),
.C0(n1474), .Y(n1473) );
OAI2BB1X1TS U1811 ( .A0N(n455), .A1N(n1481), .B0(n1473), .Y(n290) );
AOI21X1TS U1812 ( .A0(n1643), .A1(n1474), .B0(n1477), .Y(n1475) );
NAND2X1TS U1813 ( .A(Sgf_normalized_result[21]), .B(n1477), .Y(n1479) );
OAI211XLTS U1814 ( .A0(Sgf_normalized_result[21]), .A1(n1477), .B0(n1476),
.C0(n1479), .Y(n1478) );
OAI2BB1X1TS U1815 ( .A0N(n456), .A1N(n1481), .B0(n1478), .Y(n288) );
AOI211XLTS U1816 ( .A0(n1646), .A1(n1479), .B0(n1482), .C0(n1484), .Y(n1480)
);
AO21XLTS U1817 ( .A0(n458), .A1(n1481), .B0(n1480), .Y(n287) );
AOI21X1TS U1818 ( .A0(n1482), .A1(Sgf_normalized_result[23]), .B0(n1484),
.Y(n1485) );
OAI2BB1X1TS U1819 ( .A0N(Add_result[23]), .A1N(n1484), .B0(n1483), .Y(n286)
);
AOI2BB1XLTS U1820 ( .A0N(n1476), .A1N(FSM_add_overflow_flag), .B0(n1485),
.Y(n285) );
CMPR32X2TS U1821 ( .A(n1489), .B(n1488), .C(n1487), .CO(n1290), .S(n1490) );
BUFX3TS U1822 ( .A(n1553), .Y(n1531) );
CMPR32X2TS U1823 ( .A(mult_x_19_n181), .B(n1492), .C(n1491), .CO(n1487), .S(
n1493) );
CMPR32X2TS U1824 ( .A(mult_x_19_n188), .B(mult_x_19_n185), .C(n1496), .CO(
n1494), .S(n1497) );
CMPR32X2TS U1825 ( .A(mult_x_19_n192), .B(mult_x_19_n189), .C(n1498), .CO(
n1496), .S(n1499) );
CMPR32X2TS U1826 ( .A(mult_x_19_n203), .B(mult_x_19_n198), .C(n1503), .CO(
n1500), .S(n1504) );
CMPR32X2TS U1827 ( .A(mult_x_19_n209), .B(mult_x_19_n204), .C(n1505), .CO(
n1503), .S(n1506) );
CMPR32X2TS U1828 ( .A(mult_x_19_n222), .B(mult_x_19_n216), .C(n1510), .CO(
n1507), .S(n1511) );
CMPR32X2TS U1829 ( .A(mult_x_19_n229), .B(mult_x_19_n223), .C(n1512), .CO(
n1510), .S(n1513) );
CMPR32X2TS U1830 ( .A(mult_x_19_n246), .B(mult_x_19_n238), .C(n1517), .CO(
n1514), .S(n1518) );
CMPR32X2TS U1831 ( .A(mult_x_19_n255), .B(mult_x_19_n247), .C(n1519), .CO(
n1517), .S(n1520) );
CMPR32X2TS U1832 ( .A(mult_x_19_n274), .B(mult_x_19_n265), .C(n1524), .CO(
n1521), .S(n1525) );
CMPR32X2TS U1833 ( .A(mult_x_19_n284), .B(mult_x_19_n275), .C(n1526), .CO(
n1524), .S(n1527) );
CMPR32X2TS U1834 ( .A(mult_x_19_n306), .B(mult_x_19_n296), .C(n1532), .CO(
n1528), .S(n1533) );
CMPR32X2TS U1835 ( .A(mult_x_19_n317), .B(mult_x_19_n307), .C(n1534), .CO(
n1532), .S(n1535) );
CMPR32X2TS U1836 ( .A(mult_x_19_n329), .B(mult_x_19_n339), .C(n1539), .CO(
n1536), .S(n1540) );
CMPR32X2TS U1837 ( .A(n1542), .B(mult_x_19_n340), .C(n1541), .CO(n1539), .S(
n1543) );
AO22XLTS U1838 ( .A0(n1572), .A1(P_Sgf[24]), .B0(n1553), .B1(n1543), .Y(n262) );
CMPR32X2TS U1839 ( .A(n1545), .B(mult_x_19_n351), .C(n1544), .CO(n1541), .S(
n1546) );
AO22XLTS U1840 ( .A0(n1572), .A1(P_Sgf[23]), .B0(n1622), .B1(n1546), .Y(n261) );
CMPR32X2TS U1841 ( .A(n1548), .B(mult_x_19_n362), .C(n1547), .CO(n1544), .S(
n1549) );
AO22XLTS U1842 ( .A0(n1572), .A1(P_Sgf[22]), .B0(n1553), .B1(n1549), .Y(n260) );
CMPR32X2TS U1843 ( .A(n1551), .B(mult_x_19_n373), .C(n1550), .CO(n1547), .S(
n1552) );
AO22XLTS U1844 ( .A0(n1572), .A1(P_Sgf[21]), .B0(n1553), .B1(n1552), .Y(n259) );
CMPR32X2TS U1845 ( .A(n1555), .B(mult_x_19_n384), .C(n1554), .CO(n1550), .S(
n1556) );
AO22XLTS U1846 ( .A0(n1572), .A1(P_Sgf[20]), .B0(n1585), .B1(n1556), .Y(n258) );
CMPR32X2TS U1847 ( .A(n1558), .B(mult_x_19_n394), .C(n1557), .CO(n1554), .S(
n1559) );
AO22XLTS U1848 ( .A0(n1572), .A1(P_Sgf[19]), .B0(n1585), .B1(n1559), .Y(n257) );
CMPR32X2TS U1849 ( .A(n1561), .B(mult_x_19_n404), .C(n1560), .CO(n1557), .S(
n1562) );
AO22XLTS U1850 ( .A0(n1572), .A1(P_Sgf[18]), .B0(n1585), .B1(n1562), .Y(n256) );
AO22XLTS U1851 ( .A0(n1572), .A1(P_Sgf[17]), .B0(n1585), .B1(n1565), .Y(n255) );
CMPR32X2TS U1852 ( .A(n1567), .B(mult_x_19_n422), .C(n1566), .CO(n1563), .S(
n1568) );
AO22XLTS U1853 ( .A0(n1572), .A1(P_Sgf[16]), .B0(n1585), .B1(n1568), .Y(n254) );
AO22XLTS U1854 ( .A0(n1572), .A1(P_Sgf[15]), .B0(n1585), .B1(n1571), .Y(n253) );
CMPR32X2TS U1855 ( .A(n1574), .B(mult_x_19_n438), .C(n1573), .CO(n1569), .S(
n1575) );
AO22XLTS U1856 ( .A0(n1623), .A1(P_Sgf[14]), .B0(n1585), .B1(n1575), .Y(n252) );
CMPR32X2TS U1857 ( .A(n1577), .B(mult_x_19_n445), .C(n1576), .CO(n1573), .S(
n1578) );
AO22XLTS U1858 ( .A0(n1623), .A1(P_Sgf[13]), .B0(n1585), .B1(n1578), .Y(n251) );
AO22XLTS U1859 ( .A0(n1623), .A1(P_Sgf[12]), .B0(n1585), .B1(n1581), .Y(n250) );
CMPR32X2TS U1860 ( .A(mult_x_19_n459), .B(n1583), .C(n1582), .CO(n1579), .S(
n1584) );
AO22XLTS U1861 ( .A0(n1623), .A1(P_Sgf[11]), .B0(n1585), .B1(n1584), .Y(n249) );
AO22XLTS U1862 ( .A0(n1623), .A1(P_Sgf[10]), .B0(n1622), .B1(n1588), .Y(n248) );
CMPR32X2TS U1863 ( .A(mult_x_19_n469), .B(n1590), .C(n1589), .CO(n1586), .S(
n1591) );
AO22XLTS U1864 ( .A0(n1623), .A1(P_Sgf[9]), .B0(n1622), .B1(n1591), .Y(n247)
);
AO22XLTS U1865 ( .A0(n1623), .A1(P_Sgf[8]), .B0(n1622), .B1(n1595), .Y(n246)
);
CMPR32X2TS U1866 ( .A(n1598), .B(n1597), .C(n1596), .CO(n1592), .S(n1599) );
AO22XLTS U1867 ( .A0(n1623), .A1(P_Sgf[7]), .B0(n1622), .B1(n1599), .Y(n245)
);
AO22XLTS U1868 ( .A0(n1623), .A1(P_Sgf[6]), .B0(n1622), .B1(n1603), .Y(n244)
);
CMPR32X2TS U1869 ( .A(n1606), .B(n1605), .C(n1604), .CO(n1600), .S(n1607) );
AO22XLTS U1870 ( .A0(n1623), .A1(P_Sgf[5]), .B0(n1622), .B1(n1607), .Y(n243)
);
AO22XLTS U1871 ( .A0(n1623), .A1(P_Sgf[4]), .B0(n1622), .B1(n1611), .Y(n242)
);
CMPR32X2TS U1872 ( .A(n1614), .B(n1613), .C(n1612), .CO(n1608), .S(n1615) );
AO22XLTS U1873 ( .A0(n1623), .A1(P_Sgf[3]), .B0(n1622), .B1(n1615), .Y(n241)
);
ADDHXLTS U1874 ( .A(n1617), .B(n1616), .CO(n1612), .S(n1618) );
AO22XLTS U1875 ( .A0(n1623), .A1(P_Sgf[2]), .B0(n1622), .B1(n1618), .Y(n240)
);
ADDHXLTS U1876 ( .A(n1620), .B(n1619), .CO(n1616), .S(n1621) );
AO22XLTS U1877 ( .A0(n1623), .A1(P_Sgf[1]), .B0(n1622), .B1(n1621), .Y(n239)
);
AO22XLTS U1878 ( .A0(Sgf_normalized_result[0]), .A1(n1625), .B0(
final_result_ieee[0]), .B1(n1624), .Y(n200) );
AO22XLTS U1879 ( .A0(n469), .A1(n1625), .B0(final_result_ieee[1]), .B1(n1624), .Y(n199) );
AO22XLTS U1880 ( .A0(n467), .A1(n1625), .B0(final_result_ieee[2]), .B1(n1624), .Y(n198) );
AO22XLTS U1881 ( .A0(Sgf_normalized_result[3]), .A1(n1625), .B0(
final_result_ieee[3]), .B1(n1624), .Y(n197) );
AO22XLTS U1882 ( .A0(Sgf_normalized_result[4]), .A1(n1625), .B0(
final_result_ieee[4]), .B1(n1624), .Y(n196) );
AO22XLTS U1883 ( .A0(Sgf_normalized_result[5]), .A1(n1625), .B0(
final_result_ieee[5]), .B1(n1624), .Y(n195) );
AO22XLTS U1884 ( .A0(Sgf_normalized_result[6]), .A1(n1625), .B0(
final_result_ieee[6]), .B1(n1624), .Y(n194) );
AO22XLTS U1885 ( .A0(Sgf_normalized_result[7]), .A1(n1625), .B0(
final_result_ieee[7]), .B1(n1624), .Y(n193) );
AO22XLTS U1886 ( .A0(Sgf_normalized_result[8]), .A1(n1625), .B0(
final_result_ieee[8]), .B1(n1624), .Y(n192) );
AO22XLTS U1887 ( .A0(Sgf_normalized_result[9]), .A1(n1625), .B0(
final_result_ieee[9]), .B1(n1624), .Y(n191) );
AO22XLTS U1888 ( .A0(Sgf_normalized_result[10]), .A1(n1625), .B0(
final_result_ieee[10]), .B1(n1624), .Y(n190) );
AO22XLTS U1889 ( .A0(Sgf_normalized_result[11]), .A1(n1625), .B0(
final_result_ieee[11]), .B1(n1624), .Y(n189) );
AO22XLTS U1890 ( .A0(Sgf_normalized_result[12]), .A1(n1625), .B0(
final_result_ieee[12]), .B1(n1624), .Y(n188) );
AO22XLTS U1891 ( .A0(Sgf_normalized_result[13]), .A1(n1625), .B0(
final_result_ieee[13]), .B1(n1624), .Y(n187) );
AO22XLTS U1892 ( .A0(Sgf_normalized_result[14]), .A1(n1625), .B0(
final_result_ieee[14]), .B1(n1624), .Y(n186) );
AO22XLTS U1893 ( .A0(Sgf_normalized_result[15]), .A1(n1625), .B0(
final_result_ieee[15]), .B1(n1624), .Y(n185) );
AO22XLTS U1894 ( .A0(Sgf_normalized_result[16]), .A1(n1625), .B0(
final_result_ieee[16]), .B1(n1624), .Y(n184) );
AO22XLTS U1895 ( .A0(Sgf_normalized_result[17]), .A1(n1625), .B0(
final_result_ieee[17]), .B1(n1624), .Y(n183) );
AO22XLTS U1896 ( .A0(Sgf_normalized_result[18]), .A1(n1625), .B0(
final_result_ieee[18]), .B1(n1624), .Y(n182) );
AO22XLTS U1897 ( .A0(Sgf_normalized_result[19]), .A1(n1625), .B0(
final_result_ieee[19]), .B1(n1624), .Y(n181) );
AO22XLTS U1898 ( .A0(Sgf_normalized_result[20]), .A1(n1625), .B0(
final_result_ieee[20]), .B1(n1624), .Y(n180) );
AO22XLTS U1899 ( .A0(Sgf_normalized_result[21]), .A1(n1625), .B0(
final_result_ieee[21]), .B1(n1624), .Y(n179) );
AO22XLTS U1900 ( .A0(Sgf_normalized_result[22]), .A1(n1625), .B0(
final_result_ieee[22]), .B1(n1624), .Y(n178) );
OA22X1TS U1901 ( .A0(n1627), .A1(final_result_ieee[23]), .B0(
exp_oper_result[0]), .B1(n1626), .Y(n177) );
OA22X1TS U1902 ( .A0(n1627), .A1(final_result_ieee[24]), .B0(
exp_oper_result[1]), .B1(n1626), .Y(n176) );
OA22X1TS U1903 ( .A0(n1627), .A1(final_result_ieee[25]), .B0(
exp_oper_result[2]), .B1(n1626), .Y(n175) );
OA22X1TS U1904 ( .A0(n1627), .A1(final_result_ieee[26]), .B0(
exp_oper_result[3]), .B1(n1626), .Y(n174) );
OA22X1TS U1905 ( .A0(n1627), .A1(final_result_ieee[27]), .B0(
exp_oper_result[4]), .B1(n1626), .Y(n173) );
OA22X1TS U1906 ( .A0(n1627), .A1(final_result_ieee[28]), .B0(
exp_oper_result[5]), .B1(n1626), .Y(n172) );
OA22X1TS U1907 ( .A0(n1627), .A1(final_result_ieee[29]), .B0(
exp_oper_result[6]), .B1(n1626), .Y(n171) );
OA22X1TS U1908 ( .A0(n1627), .A1(final_result_ieee[30]), .B0(
exp_oper_result[7]), .B1(n1626), .Y(n170) );
initial $sdf_annotate("FPU_Multiplication_Function_ASIC_fpu_syn_constraints_clk40.tcl_DW_1STAGE_syn.sdf");
endmodule
|
// hps_sdram.v
// This file was auto-generated from altera_mem_if_hps_emif_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module hps_sdram (
input wire pll_ref_clk, // pll_ref_clk.clk
input wire global_reset_n, // global_reset.reset_n
input wire soft_reset_n, // soft_reset.reset_n
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire [0:0] mem_ck, // .mem_ck
output wire [0:0] mem_ck_n, // .mem_ck_n
output wire [0:0] mem_cke, // .mem_cke
output wire [0:0] mem_cs_n, // .mem_cs_n
output wire [3:0] mem_dm, // .mem_dm
output wire [0:0] mem_ras_n, // .mem_ras_n
output wire [0:0] mem_cas_n, // .mem_cas_n
output wire [0:0] mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire [0:0] mem_odt, // .mem_odt
input wire oct_rzqin // oct.rzqin
);
wire pll_afi_clk_clk; // pll:afi_clk -> [c0:afi_clk, p0:afi_clk]
wire pll_afi_half_clk_clk; // pll:afi_half_clk -> [c0:afi_half_clk, p0:afi_half_clk]
wire [4:0] p0_afi_afi_rlat; // p0:afi_rlat -> c0:afi_rlat
wire p0_afi_afi_cal_success; // p0:afi_cal_success -> c0:afi_cal_success
wire [79:0] p0_afi_afi_rdata; // p0:afi_rdata -> c0:afi_rdata
wire [3:0] p0_afi_afi_wlat; // p0:afi_wlat -> c0:afi_wlat
wire p0_afi_afi_cal_fail; // p0:afi_cal_fail -> c0:afi_cal_fail
wire [0:0] p0_afi_afi_rdata_valid; // p0:afi_rdata_valid -> c0:afi_rdata_valid
wire p0_afi_reset_reset; // p0:afi_reset_n -> c0:afi_reset_n
wire [4:0] c0_afi_afi_rdata_en_full; // c0:afi_rdata_en_full -> p0:afi_rdata_en_full
wire [0:0] c0_afi_afi_rst_n; // c0:afi_rst_n -> p0:afi_rst_n
wire [4:0] c0_afi_afi_dqs_burst; // c0:afi_dqs_burst -> p0:afi_dqs_burst
wire [19:0] c0_afi_afi_addr; // c0:afi_addr -> p0:afi_addr
wire [9:0] c0_afi_afi_dm; // c0:afi_dm -> p0:afi_dm
wire [0:0] c0_afi_afi_mem_clk_disable; // c0:afi_mem_clk_disable -> p0:afi_mem_clk_disable
wire [0:0] c0_afi_afi_we_n; // c0:afi_we_n -> p0:afi_we_n
wire [4:0] c0_afi_afi_rdata_en; // c0:afi_rdata_en -> p0:afi_rdata_en
wire [1:0] c0_afi_afi_odt; // c0:afi_odt -> p0:afi_odt
wire [0:0] c0_afi_afi_ras_n; // c0:afi_ras_n -> p0:afi_ras_n
wire [1:0] c0_afi_afi_cke; // c0:afi_cke -> p0:afi_cke
wire [4:0] c0_afi_afi_wdata_valid; // c0:afi_wdata_valid -> p0:afi_wdata_valid
wire [79:0] c0_afi_afi_wdata; // c0:afi_wdata -> p0:afi_wdata
wire [2:0] c0_afi_afi_ba; // c0:afi_ba -> p0:afi_ba
wire [0:0] c0_afi_afi_cas_n; // c0:afi_cas_n -> p0:afi_cas_n
wire [1:0] c0_afi_afi_cs_n; // c0:afi_cs_n -> p0:afi_cs_n
wire [7:0] c0_hard_phy_cfg_cfg_tmrd; // c0:cfg_tmrd -> p0:cfg_tmrd
wire [23:0] c0_hard_phy_cfg_cfg_dramconfig; // c0:cfg_dramconfig -> p0:cfg_dramconfig
wire [7:0] c0_hard_phy_cfg_cfg_rowaddrwidth; // c0:cfg_rowaddrwidth -> p0:cfg_rowaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_devicewidth; // c0:cfg_devicewidth -> p0:cfg_devicewidth
wire [15:0] c0_hard_phy_cfg_cfg_trefi; // c0:cfg_trefi -> p0:cfg_trefi
wire [7:0] c0_hard_phy_cfg_cfg_tcl; // c0:cfg_tcl -> p0:cfg_tcl
wire [7:0] c0_hard_phy_cfg_cfg_csaddrwidth; // c0:cfg_csaddrwidth -> p0:cfg_csaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_coladdrwidth; // c0:cfg_coladdrwidth -> p0:cfg_coladdrwidth
wire [7:0] c0_hard_phy_cfg_cfg_trfc; // c0:cfg_trfc -> p0:cfg_trfc
wire [7:0] c0_hard_phy_cfg_cfg_addlat; // c0:cfg_addlat -> p0:cfg_addlat
wire [7:0] c0_hard_phy_cfg_cfg_bankaddrwidth; // c0:cfg_bankaddrwidth -> p0:cfg_bankaddrwidth
wire [7:0] c0_hard_phy_cfg_cfg_interfacewidth; // c0:cfg_interfacewidth -> p0:cfg_interfacewidth
wire [7:0] c0_hard_phy_cfg_cfg_twr; // c0:cfg_twr -> p0:cfg_twr
wire [7:0] c0_hard_phy_cfg_cfg_caswrlat; // c0:cfg_caswrlat -> p0:cfg_caswrlat
wire p0_ctl_clk_clk; // p0:ctl_clk -> c0:ctl_clk
wire p0_ctl_reset_reset; // p0:ctl_reset_n -> c0:ctl_reset_n
wire p0_io_int_io_intaficalfail; // p0:io_intaficalfail -> c0:io_intaficalfail
wire p0_io_int_io_intaficalsuccess; // p0:io_intaficalsuccess -> c0:io_intaficalsuccess
wire [15:0] oct_oct_sharing_parallelterminationcontrol; // oct:parallelterminationcontrol -> p0:parallelterminationcontrol
wire [15:0] oct_oct_sharing_seriesterminationcontrol; // oct:seriesterminationcontrol -> p0:seriesterminationcontrol
wire pll_pll_sharing_pll_write_clk; // pll:pll_write_clk -> p0:pll_write_clk
wire pll_pll_sharing_pll_avl_clk; // pll:pll_avl_clk -> p0:pll_avl_clk
wire pll_pll_sharing_pll_write_clk_pre_phy_clk; // pll:pll_write_clk_pre_phy_clk -> p0:pll_write_clk_pre_phy_clk
wire pll_pll_sharing_pll_addr_cmd_clk; // pll:pll_addr_cmd_clk -> p0:pll_addr_cmd_clk
wire pll_pll_sharing_pll_config_clk; // pll:pll_config_clk -> p0:pll_config_clk
wire pll_pll_sharing_pll_avl_phy_clk; // pll:pll_avl_phy_clk -> p0:pll_avl_phy_clk
wire pll_pll_sharing_afi_phy_clk; // pll:afi_phy_clk -> p0:afi_phy_clk
wire pll_pll_sharing_pll_mem_clk; // pll:pll_mem_clk -> p0:pll_mem_clk
wire pll_pll_sharing_pll_locked; // pll:pll_locked -> p0:pll_locked
wire pll_pll_sharing_pll_mem_phy_clk; // pll:pll_mem_phy_clk -> p0:pll_mem_phy_clk
wire p0_dll_clk_clk; // p0:dll_clk -> dll:clk
wire p0_dll_sharing_dll_pll_locked; // p0:dll_pll_locked -> dll:dll_pll_locked
wire [6:0] dll_dll_sharing_dll_delayctrl; // dll:dll_delayctrl -> p0:dll_delayctrl
hps_sdram_pll pll (
.global_reset_n (global_reset_n), // global_reset.reset_n
.pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_locked (pll_pll_sharing_pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk) // .pll_avl_phy_clk
);
hps_sdram_p0 p0 (
.global_reset_n (global_reset_n), // global_reset.reset_n
.soft_reset_n (soft_reset_n), // soft_reset.reset_n
.afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n
.afi_reset_export_n (), // afi_reset_export.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.avl_clk (), // avl_clk.clk
.avl_reset_n (), // avl_reset.reset_n
.scc_clk (), // scc_clk.clk
.scc_reset_n (), // scc_reset.reset_n
.avl_address (), // avl.address
.avl_write (), // .write
.avl_writedata (), // .writedata
.avl_read (), // .read
.avl_readdata (), // .readdata
.avl_waitrequest (), // .waitrequest
.dll_clk (p0_dll_clk_clk), // dll_clk.clk
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.scc_data (), // scc.scc_data
.scc_dqs_ena (), // .scc_dqs_ena
.scc_dqs_io_ena (), // .scc_dqs_io_ena
.scc_dq_ena (), // .scc_dq_ena
.scc_dm_ena (), // .scc_dm_ena
.capture_strobe_tracking (), // .capture_strobe_tracking
.scc_upd (), // .scc_upd
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // afi_mem_clk_disable.afi_mem_clk_disable
.pll_mem_clk (pll_pll_sharing_pll_mem_clk), // pll_sharing.pll_mem_clk
.pll_write_clk (pll_pll_sharing_pll_write_clk), // .pll_write_clk
.pll_locked (pll_pll_sharing_pll_locked), // .pll_locked
.pll_write_clk_pre_phy_clk (pll_pll_sharing_pll_write_clk_pre_phy_clk), // .pll_write_clk_pre_phy_clk
.pll_addr_cmd_clk (pll_pll_sharing_pll_addr_cmd_clk), // .pll_addr_cmd_clk
.pll_avl_clk (pll_pll_sharing_pll_avl_clk), // .pll_avl_clk
.pll_config_clk (pll_pll_sharing_pll_config_clk), // .pll_config_clk
.pll_mem_phy_clk (pll_pll_sharing_pll_mem_phy_clk), // .pll_mem_phy_clk
.afi_phy_clk (pll_pll_sharing_afi_phy_clk), // .afi_phy_clk
.pll_avl_phy_clk (pll_pll_sharing_pll_avl_phy_clk), // .pll_avl_phy_clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll_dll_sharing_dll_delayctrl), // .dll_delayctrl
.seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol), // .parallelterminationcontrol
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_dm (mem_dm), // .mem_dm
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.csr_soft_reset_req (1'b0), // (terminated)
.io_intaddrdout (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intbadout (12'b000000000000), // (terminated)
.io_intcasndout (4'b0000), // (terminated)
.io_intckdout (4'b0000), // (terminated)
.io_intckedout (8'b00000000), // (terminated)
.io_intckndout (4'b0000), // (terminated)
.io_intcsndout (8'b00000000), // (terminated)
.io_intdmdout (20'b00000000000000000000), // (terminated)
.io_intdqdin (), // (terminated)
.io_intdqdout (180'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqoe (90'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.io_intdqsbdout (20'b00000000000000000000), // (terminated)
.io_intdqsboe (10'b0000000000), // (terminated)
.io_intdqsdout (20'b00000000000000000000), // (terminated)
.io_intdqslogicdqsena (10'b0000000000), // (terminated)
.io_intdqslogicfiforeset (5'b00000), // (terminated)
.io_intdqslogicincrdataen (10'b0000000000), // (terminated)
.io_intdqslogicincwrptr (10'b0000000000), // (terminated)
.io_intdqslogicoct (10'b0000000000), // (terminated)
.io_intdqslogicrdatavalid (), // (terminated)
.io_intdqslogicreadlatency (25'b0000000000000000000000000), // (terminated)
.io_intdqsoe (10'b0000000000), // (terminated)
.io_intodtdout (8'b00000000), // (terminated)
.io_intrasndout (4'b0000), // (terminated)
.io_intresetndout (4'b0000), // (terminated)
.io_intwendout (4'b0000), // (terminated)
.io_intafirlat (), // (terminated)
.io_intafiwlat () // (terminated)
);
altera_mem_if_hhp_qseq_synth_top #(
.MEM_IF_DM_WIDTH (4),
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_DQ_WIDTH (32)
) seq (
);
altera_mem_if_hard_memory_controller_top_cyclonev #(
.MEM_IF_DQS_WIDTH (4),
.MEM_IF_CS_WIDTH (1),
.MEM_IF_CHIP_BITS (1),
.MEM_IF_CLK_PAIR_COUNT (1),
.CSR_ADDR_WIDTH (10),
.CSR_DATA_WIDTH (8),
.CSR_BE_WIDTH (1),
.AVL_ADDR_WIDTH (27),
.AVL_DATA_WIDTH (64),
.AVL_SIZE_WIDTH (3),
.AVL_DATA_WIDTH_PORT_0 (1),
.AVL_ADDR_WIDTH_PORT_0 (1),
.AVL_NUM_SYMBOLS_PORT_0 (1),
.LSB_WFIFO_PORT_0 (5),
.MSB_WFIFO_PORT_0 (5),
.LSB_RFIFO_PORT_0 (5),
.MSB_RFIFO_PORT_0 (5),
.AVL_DATA_WIDTH_PORT_1 (1),
.AVL_ADDR_WIDTH_PORT_1 (1),
.AVL_NUM_SYMBOLS_PORT_1 (1),
.LSB_WFIFO_PORT_1 (5),
.MSB_WFIFO_PORT_1 (5),
.LSB_RFIFO_PORT_1 (5),
.MSB_RFIFO_PORT_1 (5),
.AVL_DATA_WIDTH_PORT_2 (1),
.AVL_ADDR_WIDTH_PORT_2 (1),
.AVL_NUM_SYMBOLS_PORT_2 (1),
.LSB_WFIFO_PORT_2 (5),
.MSB_WFIFO_PORT_2 (5),
.LSB_RFIFO_PORT_2 (5),
.MSB_RFIFO_PORT_2 (5),
.AVL_DATA_WIDTH_PORT_3 (1),
.AVL_ADDR_WIDTH_PORT_3 (1),
.AVL_NUM_SYMBOLS_PORT_3 (1),
.LSB_WFIFO_PORT_3 (5),
.MSB_WFIFO_PORT_3 (5),
.LSB_RFIFO_PORT_3 (5),
.MSB_RFIFO_PORT_3 (5),
.AVL_DATA_WIDTH_PORT_4 (1),
.AVL_ADDR_WIDTH_PORT_4 (1),
.AVL_NUM_SYMBOLS_PORT_4 (1),
.LSB_WFIFO_PORT_4 (5),
.MSB_WFIFO_PORT_4 (5),
.LSB_RFIFO_PORT_4 (5),
.MSB_RFIFO_PORT_4 (5),
.AVL_DATA_WIDTH_PORT_5 (1),
.AVL_ADDR_WIDTH_PORT_5 (1),
.AVL_NUM_SYMBOLS_PORT_5 (1),
.LSB_WFIFO_PORT_5 (5),
.MSB_WFIFO_PORT_5 (5),
.LSB_RFIFO_PORT_5 (5),
.MSB_RFIFO_PORT_5 (5),
.ENUM_ATTR_COUNTER_ONE_RESET ("DISABLED"),
.ENUM_ATTR_COUNTER_ZERO_RESET ("DISABLED"),
.ENUM_ATTR_STATIC_CONFIG_VALID ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_0 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_1 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_2 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_3 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_4 ("DISABLED"),
.ENUM_AUTO_PCH_ENABLE_5 ("DISABLED"),
.ENUM_CAL_REQ ("DISABLED"),
.ENUM_CFG_BURST_LENGTH ("BL_8"),
.ENUM_CFG_INTERFACE_WIDTH ("DWIDTH_32"),
.ENUM_CFG_SELF_RFSH_EXIT_CYCLES ("SELF_RFSH_EXIT_CYCLES_512"),
.ENUM_CFG_STARVE_LIMIT ("STARVE_LIMIT_10"),
.ENUM_CFG_TYPE ("DDR3"),
.ENUM_CLOCK_OFF_0 ("DISABLED"),
.ENUM_CLOCK_OFF_1 ("DISABLED"),
.ENUM_CLOCK_OFF_2 ("DISABLED"),
.ENUM_CLOCK_OFF_3 ("DISABLED"),
.ENUM_CLOCK_OFF_4 ("DISABLED"),
.ENUM_CLOCK_OFF_5 ("DISABLED"),
.ENUM_CLR_INTR ("NO_CLR_INTR"),
.ENUM_CMD_PORT_IN_USE_0 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_1 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_2 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_3 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_4 ("FALSE"),
.ENUM_CMD_PORT_IN_USE_5 ("FALSE"),
.ENUM_CPORT0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT0_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT0_TYPE ("DISABLE"),
.ENUM_CPORT0_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT1_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT1_TYPE ("DISABLE"),
.ENUM_CPORT1_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT2_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT2_TYPE ("DISABLE"),
.ENUM_CPORT2_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT3_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT3_TYPE ("DISABLE"),
.ENUM_CPORT3_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT4_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT4_TYPE ("DISABLE"),
.ENUM_CPORT4_WFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_CPORT5_RFIFO_MAP ("FIFO_0"),
.ENUM_CPORT5_TYPE ("DISABLE"),
.ENUM_CPORT5_WFIFO_MAP ("FIFO_0"),
.ENUM_CTL_ADDR_ORDER ("CHIP_ROW_BANK_COL"),
.ENUM_CTL_ECC_ENABLED ("CTL_ECC_DISABLED"),
.ENUM_CTL_ECC_RMW_ENABLED ("CTL_ECC_RMW_DISABLED"),
.ENUM_CTL_REGDIMM_ENABLED ("REGDIMM_DISABLED"),
.ENUM_CTL_USR_REFRESH ("CTL_USR_REFRESH_DISABLED"),
.ENUM_CTRL_WIDTH ("DATA_WIDTH_64_BIT"),
.ENUM_DELAY_BONDING ("BONDING_LATENCY_0"),
.ENUM_DFX_BYPASS_ENABLE ("DFX_BYPASS_DISABLED"),
.ENUM_DISABLE_MERGING ("MERGING_ENABLED"),
.ENUM_ECC_DQ_WIDTH ("ECC_DQ_WIDTH_0"),
.ENUM_ENABLE_ATPG ("DISABLED"),
.ENUM_ENABLE_BONDING_0 ("DISABLED"),
.ENUM_ENABLE_BONDING_1 ("DISABLED"),
.ENUM_ENABLE_BONDING_2 ("DISABLED"),
.ENUM_ENABLE_BONDING_3 ("DISABLED"),
.ENUM_ENABLE_BONDING_4 ("DISABLED"),
.ENUM_ENABLE_BONDING_5 ("DISABLED"),
.ENUM_ENABLE_BONDING_WRAPBACK ("DISABLED"),
.ENUM_ENABLE_DQS_TRACKING ("ENABLED"),
.ENUM_ENABLE_ECC_CODE_OVERWRITES ("DISABLED"),
.ENUM_ENABLE_FAST_EXIT_PPD ("DISABLED"),
.ENUM_ENABLE_INTR ("DISABLED"),
.ENUM_ENABLE_NO_DM ("DISABLED"),
.ENUM_ENABLE_PIPELINEGLOBAL ("DISABLED"),
.ENUM_GANGED_ARF ("DISABLED"),
.ENUM_GEN_DBE ("GEN_DBE_DISABLED"),
.ENUM_GEN_SBE ("GEN_SBE_DISABLED"),
.ENUM_INC_SYNC ("FIFO_SET_2"),
.ENUM_LOCAL_IF_CS_WIDTH ("ADDR_WIDTH_0"),
.ENUM_MASK_CORR_DROPPED_INTR ("DISABLED"),
.ENUM_MASK_DBE_INTR ("DISABLED"),
.ENUM_MASK_SBE_INTR ("DISABLED"),
.ENUM_MEM_IF_AL ("AL_0"),
.ENUM_MEM_IF_BANKADDR_WIDTH ("ADDR_WIDTH_3"),
.ENUM_MEM_IF_BURSTLENGTH ("MEM_IF_BURSTLENGTH_8"),
.ENUM_MEM_IF_COLADDR_WIDTH ("ADDR_WIDTH_10"),
.ENUM_MEM_IF_CS_PER_RANK ("MEM_IF_CS_PER_RANK_1"),
.ENUM_MEM_IF_CS_WIDTH ("MEM_IF_CS_WIDTH_1"),
.ENUM_MEM_IF_DQ_PER_CHIP ("MEM_IF_DQ_PER_CHIP_8"),
.ENUM_MEM_IF_DQS_WIDTH ("DQS_WIDTH_4"),
.ENUM_MEM_IF_DWIDTH ("MEM_IF_DWIDTH_32"),
.ENUM_MEM_IF_MEMTYPE ("DDR3_SDRAM"),
.ENUM_MEM_IF_ROWADDR_WIDTH ("ADDR_WIDTH_15"),
.ENUM_MEM_IF_SPEEDBIN ("DDR3_1600_8_8_8"),
.ENUM_MEM_IF_TCCD ("TCCD_4"),
.ENUM_MEM_IF_TCL ("TCL_7"),
.ENUM_MEM_IF_TCWL ("TCWL_7"),
.ENUM_MEM_IF_TFAW ("TFAW_15"),
.ENUM_MEM_IF_TMRD ("TMRD_4"),
.ENUM_MEM_IF_TRAS ("TRAS_14"),
.ENUM_MEM_IF_TRC ("TRC_20"),
.ENUM_MEM_IF_TRCD ("TRCD_6"),
.ENUM_MEM_IF_TRP ("TRP_6"),
.ENUM_MEM_IF_TRRD ("TRRD_3"),
.ENUM_MEM_IF_TRTP ("TRTP_3"),
.ENUM_MEM_IF_TWR ("TWR_6"),
.ENUM_MEM_IF_TWTR ("TWTR_4"),
.ENUM_MMR_CFG_MEM_BL ("MP_BL_8"),
.ENUM_OUTPUT_REGD ("DISABLED"),
.ENUM_PDN_EXIT_CYCLES ("SLOW_EXIT"),
.ENUM_PORT0_WIDTH ("PORT_32_BIT"),
.ENUM_PORT1_WIDTH ("PORT_32_BIT"),
.ENUM_PORT2_WIDTH ("PORT_32_BIT"),
.ENUM_PORT3_WIDTH ("PORT_32_BIT"),
.ENUM_PORT4_WIDTH ("PORT_32_BIT"),
.ENUM_PORT5_WIDTH ("PORT_32_BIT"),
.ENUM_PRIORITY_0_0 ("WEIGHT_0"),
.ENUM_PRIORITY_0_1 ("WEIGHT_0"),
.ENUM_PRIORITY_0_2 ("WEIGHT_0"),
.ENUM_PRIORITY_0_3 ("WEIGHT_0"),
.ENUM_PRIORITY_0_4 ("WEIGHT_0"),
.ENUM_PRIORITY_0_5 ("WEIGHT_0"),
.ENUM_PRIORITY_1_0 ("WEIGHT_0"),
.ENUM_PRIORITY_1_1 ("WEIGHT_0"),
.ENUM_PRIORITY_1_2 ("WEIGHT_0"),
.ENUM_PRIORITY_1_3 ("WEIGHT_0"),
.ENUM_PRIORITY_1_4 ("WEIGHT_0"),
.ENUM_PRIORITY_1_5 ("WEIGHT_0"),
.ENUM_PRIORITY_2_0 ("WEIGHT_0"),
.ENUM_PRIORITY_2_1 ("WEIGHT_0"),
.ENUM_PRIORITY_2_2 ("WEIGHT_0"),
.ENUM_PRIORITY_2_3 ("WEIGHT_0"),
.ENUM_PRIORITY_2_4 ("WEIGHT_0"),
.ENUM_PRIORITY_2_5 ("WEIGHT_0"),
.ENUM_PRIORITY_3_0 ("WEIGHT_0"),
.ENUM_PRIORITY_3_1 ("WEIGHT_0"),
.ENUM_PRIORITY_3_2 ("WEIGHT_0"),
.ENUM_PRIORITY_3_3 ("WEIGHT_0"),
.ENUM_PRIORITY_3_4 ("WEIGHT_0"),
.ENUM_PRIORITY_3_5 ("WEIGHT_0"),
.ENUM_PRIORITY_4_0 ("WEIGHT_0"),
.ENUM_PRIORITY_4_1 ("WEIGHT_0"),
.ENUM_PRIORITY_4_2 ("WEIGHT_0"),
.ENUM_PRIORITY_4_3 ("WEIGHT_0"),
.ENUM_PRIORITY_4_4 ("WEIGHT_0"),
.ENUM_PRIORITY_4_5 ("WEIGHT_0"),
.ENUM_PRIORITY_5_0 ("WEIGHT_0"),
.ENUM_PRIORITY_5_1 ("WEIGHT_0"),
.ENUM_PRIORITY_5_2 ("WEIGHT_0"),
.ENUM_PRIORITY_5_3 ("WEIGHT_0"),
.ENUM_PRIORITY_5_4 ("WEIGHT_0"),
.ENUM_PRIORITY_5_5 ("WEIGHT_0"),
.ENUM_PRIORITY_6_0 ("WEIGHT_0"),
.ENUM_PRIORITY_6_1 ("WEIGHT_0"),
.ENUM_PRIORITY_6_2 ("WEIGHT_0"),
.ENUM_PRIORITY_6_3 ("WEIGHT_0"),
.ENUM_PRIORITY_6_4 ("WEIGHT_0"),
.ENUM_PRIORITY_6_5 ("WEIGHT_0"),
.ENUM_PRIORITY_7_0 ("WEIGHT_0"),
.ENUM_PRIORITY_7_1 ("WEIGHT_0"),
.ENUM_PRIORITY_7_2 ("WEIGHT_0"),
.ENUM_PRIORITY_7_3 ("WEIGHT_0"),
.ENUM_PRIORITY_7_4 ("WEIGHT_0"),
.ENUM_PRIORITY_7_5 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_RCFG_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_RCFG_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_RCFG_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_RD_DWIDTH_0 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_1 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_2 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_3 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_4 ("DWIDTH_0"),
.ENUM_RD_DWIDTH_5 ("DWIDTH_0"),
.ENUM_RD_FIFO_IN_USE_0 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_1 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_2 ("FALSE"),
.ENUM_RD_FIFO_IN_USE_3 ("FALSE"),
.ENUM_RD_PORT_INFO_0 ("USE_NO"),
.ENUM_RD_PORT_INFO_1 ("USE_NO"),
.ENUM_RD_PORT_INFO_2 ("USE_NO"),
.ENUM_RD_PORT_INFO_3 ("USE_NO"),
.ENUM_RD_PORT_INFO_4 ("USE_NO"),
.ENUM_RD_PORT_INFO_5 ("USE_NO"),
.ENUM_READ_ODT_CHIP ("ODT_DISABLED"),
.ENUM_REORDER_DATA ("DATA_REORDERING"),
.ENUM_RFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_RFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_SINGLE_READY_0 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_1 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_2 ("CONCATENATE_RDY"),
.ENUM_SINGLE_READY_3 ("CONCATENATE_RDY"),
.ENUM_STATIC_WEIGHT_0 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_1 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_2 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_3 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_4 ("WEIGHT_0"),
.ENUM_STATIC_WEIGHT_5 ("WEIGHT_0"),
.ENUM_SYNC_MODE_0 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_1 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_2 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_3 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_4 ("ASYNCHRONOUS"),
.ENUM_SYNC_MODE_5 ("ASYNCHRONOUS"),
.ENUM_TEST_MODE ("NORMAL_MODE"),
.ENUM_THLD_JAR1_0 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_1 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_2 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_3 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_4 ("THRESHOLD_32"),
.ENUM_THLD_JAR1_5 ("THRESHOLD_32"),
.ENUM_THLD_JAR2_0 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_1 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_2 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_3 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_4 ("THRESHOLD_16"),
.ENUM_THLD_JAR2_5 ("THRESHOLD_16"),
.ENUM_USE_ALMOST_EMPTY_0 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_1 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_2 ("EMPTY"),
.ENUM_USE_ALMOST_EMPTY_3 ("EMPTY"),
.ENUM_USER_ECC_EN ("DISABLE"),
.ENUM_USER_PRIORITY_0 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_1 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_2 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_3 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_4 ("PRIORITY_1"),
.ENUM_USER_PRIORITY_5 ("PRIORITY_1"),
.ENUM_WFIFO0_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO0_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO1_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO1_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO2_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO2_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WFIFO3_CPORT_MAP ("CMD_PORT_0"),
.ENUM_WFIFO3_RDY_ALMOST_FULL ("NOT_FULL"),
.ENUM_WR_DWIDTH_0 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_1 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_2 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_3 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_4 ("DWIDTH_0"),
.ENUM_WR_DWIDTH_5 ("DWIDTH_0"),
.ENUM_WR_FIFO_IN_USE_0 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_1 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_2 ("FALSE"),
.ENUM_WR_FIFO_IN_USE_3 ("FALSE"),
.ENUM_WR_PORT_INFO_0 ("USE_NO"),
.ENUM_WR_PORT_INFO_1 ("USE_NO"),
.ENUM_WR_PORT_INFO_2 ("USE_NO"),
.ENUM_WR_PORT_INFO_3 ("USE_NO"),
.ENUM_WR_PORT_INFO_4 ("USE_NO"),
.ENUM_WR_PORT_INFO_5 ("USE_NO"),
.ENUM_WRITE_ODT_CHIP ("WRITE_CHIP0_ODT0_CHIP1"),
.INTG_MEM_AUTO_PD_CYCLES (0),
.INTG_CYC_TO_RLD_JARS_0 (1),
.INTG_CYC_TO_RLD_JARS_1 (1),
.INTG_CYC_TO_RLD_JARS_2 (1),
.INTG_CYC_TO_RLD_JARS_3 (1),
.INTG_CYC_TO_RLD_JARS_4 (1),
.INTG_CYC_TO_RLD_JARS_5 (1),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_ACT_TO_RDWR (0),
.INTG_EXTRA_CTL_CLK_ARF_PERIOD (0),
.INTG_EXTRA_CTL_CLK_ARF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT (0),
.INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PCH_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_PDN_PERIOD (0),
.INTG_EXTRA_CTL_CLK_PDN_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_RD_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD (0),
.INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP (0),
.INTG_EXTRA_CTL_CLK_RD_TO_WR (2),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_BC (2),
.INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP (2),
.INTG_EXTRA_CTL_CLK_SRF_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL (0),
.INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID (0),
.INTG_EXTRA_CTL_CLK_WR_TO_PCH (0),
.INTG_EXTRA_CTL_CLK_WR_TO_RD (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_BC (3),
.INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP (3),
.INTG_EXTRA_CTL_CLK_WR_TO_WR (0),
.INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP (0),
.INTG_MEM_IF_TREFI (3120),
.INTG_MEM_IF_TRFC (120),
.INTG_RCFG_SUM_WT_PRIORITY_0 (0),
.INTG_RCFG_SUM_WT_PRIORITY_1 (0),
.INTG_RCFG_SUM_WT_PRIORITY_2 (0),
.INTG_RCFG_SUM_WT_PRIORITY_3 (0),
.INTG_RCFG_SUM_WT_PRIORITY_4 (0),
.INTG_RCFG_SUM_WT_PRIORITY_5 (0),
.INTG_RCFG_SUM_WT_PRIORITY_6 (0),
.INTG_RCFG_SUM_WT_PRIORITY_7 (0),
.INTG_SUM_WT_PRIORITY_0 (0),
.INTG_SUM_WT_PRIORITY_1 (0),
.INTG_SUM_WT_PRIORITY_2 (0),
.INTG_SUM_WT_PRIORITY_3 (0),
.INTG_SUM_WT_PRIORITY_4 (0),
.INTG_SUM_WT_PRIORITY_5 (0),
.INTG_SUM_WT_PRIORITY_6 (0),
.INTG_SUM_WT_PRIORITY_7 (0),
.INTG_POWER_SAVING_EXIT_CYCLES (5),
.INTG_MEM_CLK_ENTRY_CYCLES (10),
.ENUM_ENABLE_BURST_INTERRUPT ("DISABLED"),
.ENUM_ENABLE_BURST_TERMINATE ("DISABLED"),
.AFI_RATE_RATIO (1),
.AFI_ADDR_WIDTH (15),
.AFI_BANKADDR_WIDTH (3),
.AFI_CONTROL_WIDTH (1),
.AFI_CS_WIDTH (1),
.AFI_DM_WIDTH (8),
.AFI_DQ_WIDTH (64),
.AFI_ODT_WIDTH (1),
.AFI_WRITE_DQS_WIDTH (4),
.AFI_RLAT_WIDTH (6),
.AFI_WLAT_WIDTH (6),
.HARD_PHY (1)
) c0 (
.afi_clk (pll_afi_clk_clk), // afi_clk.clk
.afi_reset_n (p0_afi_reset_reset), // afi_reset.reset_n
.ctl_reset_n (p0_ctl_reset_reset), // ctl_reset.reset_n
.afi_half_clk (pll_afi_half_clk_clk), // afi_half_clk.clk
.ctl_clk (p0_ctl_clk_clk), // ctl_clk.clk
.local_init_done (), // status.local_init_done
.local_cal_success (), // .local_cal_success
.local_cal_fail (), // .local_cal_fail
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_mem_clk_disable (c0_afi_afi_mem_clk_disable), // .afi_mem_clk_disable
.afi_init_req (), // .afi_init_req
.afi_cal_req (), // .afi_cal_req
.afi_seq_busy (), // .afi_seq_busy
.afi_ctl_refresh_done (), // .afi_ctl_refresh_done
.afi_ctl_long_idle (), // .afi_ctl_long_idle
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.cfg_addlat (c0_hard_phy_cfg_cfg_addlat), // hard_phy_cfg.cfg_addlat
.cfg_bankaddrwidth (c0_hard_phy_cfg_cfg_bankaddrwidth), // .cfg_bankaddrwidth
.cfg_caswrlat (c0_hard_phy_cfg_cfg_caswrlat), // .cfg_caswrlat
.cfg_coladdrwidth (c0_hard_phy_cfg_cfg_coladdrwidth), // .cfg_coladdrwidth
.cfg_csaddrwidth (c0_hard_phy_cfg_cfg_csaddrwidth), // .cfg_csaddrwidth
.cfg_devicewidth (c0_hard_phy_cfg_cfg_devicewidth), // .cfg_devicewidth
.cfg_dramconfig (c0_hard_phy_cfg_cfg_dramconfig), // .cfg_dramconfig
.cfg_interfacewidth (c0_hard_phy_cfg_cfg_interfacewidth), // .cfg_interfacewidth
.cfg_rowaddrwidth (c0_hard_phy_cfg_cfg_rowaddrwidth), // .cfg_rowaddrwidth
.cfg_tcl (c0_hard_phy_cfg_cfg_tcl), // .cfg_tcl
.cfg_tmrd (c0_hard_phy_cfg_cfg_tmrd), // .cfg_tmrd
.cfg_trefi (c0_hard_phy_cfg_cfg_trefi), // .cfg_trefi
.cfg_trfc (c0_hard_phy_cfg_cfg_trfc), // .cfg_trfc
.cfg_twr (c0_hard_phy_cfg_cfg_twr), // .cfg_twr
.io_intaficalfail (p0_io_int_io_intaficalfail), // io_int.io_intaficalfail
.io_intaficalsuccess (p0_io_int_io_intaficalsuccess), // .io_intaficalsuccess
.mp_cmd_clk_0 (1'b0), // (terminated)
.mp_cmd_reset_n_0 (1'b1), // (terminated)
.mp_cmd_clk_1 (1'b0), // (terminated)
.mp_cmd_reset_n_1 (1'b1), // (terminated)
.mp_cmd_clk_2 (1'b0), // (terminated)
.mp_cmd_reset_n_2 (1'b1), // (terminated)
.mp_cmd_clk_3 (1'b0), // (terminated)
.mp_cmd_reset_n_3 (1'b1), // (terminated)
.mp_cmd_clk_4 (1'b0), // (terminated)
.mp_cmd_reset_n_4 (1'b1), // (terminated)
.mp_cmd_clk_5 (1'b0), // (terminated)
.mp_cmd_reset_n_5 (1'b1), // (terminated)
.mp_rfifo_clk_0 (1'b0), // (terminated)
.mp_rfifo_reset_n_0 (1'b1), // (terminated)
.mp_wfifo_clk_0 (1'b0), // (terminated)
.mp_wfifo_reset_n_0 (1'b1), // (terminated)
.mp_rfifo_clk_1 (1'b0), // (terminated)
.mp_rfifo_reset_n_1 (1'b1), // (terminated)
.mp_wfifo_clk_1 (1'b0), // (terminated)
.mp_wfifo_reset_n_1 (1'b1), // (terminated)
.mp_rfifo_clk_2 (1'b0), // (terminated)
.mp_rfifo_reset_n_2 (1'b1), // (terminated)
.mp_wfifo_clk_2 (1'b0), // (terminated)
.mp_wfifo_reset_n_2 (1'b1), // (terminated)
.mp_rfifo_clk_3 (1'b0), // (terminated)
.mp_rfifo_reset_n_3 (1'b1), // (terminated)
.mp_wfifo_clk_3 (1'b0), // (terminated)
.mp_wfifo_reset_n_3 (1'b1), // (terminated)
.csr_clk (1'b0), // (terminated)
.csr_reset_n (1'b1), // (terminated)
.avl_ready_0 (), // (terminated)
.avl_burstbegin_0 (1'b0), // (terminated)
.avl_addr_0 (1'b0), // (terminated)
.avl_rdata_valid_0 (), // (terminated)
.avl_rdata_0 (), // (terminated)
.avl_wdata_0 (1'b0), // (terminated)
.avl_be_0 (1'b0), // (terminated)
.avl_read_req_0 (1'b0), // (terminated)
.avl_write_req_0 (1'b0), // (terminated)
.avl_size_0 (3'b000), // (terminated)
.avl_ready_1 (), // (terminated)
.avl_burstbegin_1 (1'b0), // (terminated)
.avl_addr_1 (1'b0), // (terminated)
.avl_rdata_valid_1 (), // (terminated)
.avl_rdata_1 (), // (terminated)
.avl_wdata_1 (1'b0), // (terminated)
.avl_be_1 (1'b0), // (terminated)
.avl_read_req_1 (1'b0), // (terminated)
.avl_write_req_1 (1'b0), // (terminated)
.avl_size_1 (3'b000), // (terminated)
.avl_ready_2 (), // (terminated)
.avl_burstbegin_2 (1'b0), // (terminated)
.avl_addr_2 (1'b0), // (terminated)
.avl_rdata_valid_2 (), // (terminated)
.avl_rdata_2 (), // (terminated)
.avl_wdata_2 (1'b0), // (terminated)
.avl_be_2 (1'b0), // (terminated)
.avl_read_req_2 (1'b0), // (terminated)
.avl_write_req_2 (1'b0), // (terminated)
.avl_size_2 (3'b000), // (terminated)
.avl_ready_3 (), // (terminated)
.avl_burstbegin_3 (1'b0), // (terminated)
.avl_addr_3 (1'b0), // (terminated)
.avl_rdata_valid_3 (), // (terminated)
.avl_rdata_3 (), // (terminated)
.avl_wdata_3 (1'b0), // (terminated)
.avl_be_3 (1'b0), // (terminated)
.avl_read_req_3 (1'b0), // (terminated)
.avl_write_req_3 (1'b0), // (terminated)
.avl_size_3 (3'b000), // (terminated)
.avl_ready_4 (), // (terminated)
.avl_burstbegin_4 (1'b0), // (terminated)
.avl_addr_4 (1'b0), // (terminated)
.avl_rdata_valid_4 (), // (terminated)
.avl_rdata_4 (), // (terminated)
.avl_wdata_4 (1'b0), // (terminated)
.avl_be_4 (1'b0), // (terminated)
.avl_read_req_4 (1'b0), // (terminated)
.avl_write_req_4 (1'b0), // (terminated)
.avl_size_4 (3'b000), // (terminated)
.avl_ready_5 (), // (terminated)
.avl_burstbegin_5 (1'b0), // (terminated)
.avl_addr_5 (1'b0), // (terminated)
.avl_rdata_valid_5 (), // (terminated)
.avl_rdata_5 (), // (terminated)
.avl_wdata_5 (1'b0), // (terminated)
.avl_be_5 (1'b0), // (terminated)
.avl_read_req_5 (1'b0), // (terminated)
.avl_write_req_5 (1'b0), // (terminated)
.avl_size_5 (3'b000), // (terminated)
.csr_write_req (1'b0), // (terminated)
.csr_read_req (1'b0), // (terminated)
.csr_waitrequest (), // (terminated)
.csr_addr (10'b0000000000), // (terminated)
.csr_be (1'b0), // (terminated)
.csr_wdata (8'b00000000), // (terminated)
.csr_rdata (), // (terminated)
.csr_rdata_valid (), // (terminated)
.local_multicast (1'b0), // (terminated)
.local_refresh_req (1'b0), // (terminated)
.local_refresh_chip (1'b0), // (terminated)
.local_refresh_ack (), // (terminated)
.local_self_rfsh_req (1'b0), // (terminated)
.local_self_rfsh_chip (1'b0), // (terminated)
.local_self_rfsh_ack (), // (terminated)
.local_deep_powerdn_req (1'b0), // (terminated)
.local_deep_powerdn_chip (1'b0), // (terminated)
.local_deep_powerdn_ack (), // (terminated)
.local_powerdn_ack (), // (terminated)
.local_priority (1'b0), // (terminated)
.bonding_in_1 (4'b0000), // (terminated)
.bonding_in_2 (6'b000000), // (terminated)
.bonding_in_3 (6'b000000), // (terminated)
.bonding_out_1 (), // (terminated)
.bonding_out_2 (), // (terminated)
.bonding_out_3 () // (terminated)
);
altera_mem_if_oct_cyclonev #(
.OCT_TERM_CONTROL_WIDTH (16)
) oct (
.oct_rzqin (oct_rzqin), // oct.rzqin
.seriesterminationcontrol (oct_oct_sharing_seriesterminationcontrol), // oct_sharing.seriesterminationcontrol
.parallelterminationcontrol (oct_oct_sharing_parallelterminationcontrol) // .parallelterminationcontrol
);
altera_mem_if_dll_cyclonev #(
.DLL_DELAY_CTRL_WIDTH (7),
.DLL_OFFSET_CTRL_WIDTH (6),
.DELAY_BUFFER_MODE ("HIGH"),
.DELAY_CHAIN_LENGTH (8),
.DLL_INPUT_FREQUENCY_PS_STR ("2500 ps")
) dll (
.clk (p0_dll_clk_clk), // clk.clk
.dll_pll_locked (p0_dll_sharing_dll_pll_locked), // dll_sharing.dll_pll_locked
.dll_delayctrl (dll_dll_sharing_dll_delayctrl) // .dll_delayctrl
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A2BB2O_SYMBOL_V
`define SKY130_FD_SC_HD__A2BB2O_SYMBOL_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a2bb2o (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A2BB2O_SYMBOL_V
|
`timescale 1ns / 1ps
module hw_test(
input wire clk50000,
input wire rst,
input wire [6:0] sw,
output sck_o,
output bck_o,
output data_o,
output lrck_o);
reg clk24576;
always @(posedge clk50000)
clk24576 <= ~clk24576;
reg [1:0] pop_s;
wire [1:0] ack;
wire [23:0] data [1:0];
synth l(
.clk(clk24576), .rst(rst),
.pop_i(pop_s[0]), .ack_o(ack[0]), .data_o(data[0]));
synth r(
.clk(clk24576), .rst(rst),
.pop_i(pop_s[1]), .ack_o(ack[1]), .data_o(data[1]));
wire [23:0] data_d = (sw[0] ? (data[0] | data[1]) : 0) | (sw[1] ? 24'h800000 : 0) | (sw[2] ? 24'h7fffff : 0);
wire ack_d = |ack;
reg lrck_d;
wire pop_d;
dac_drv d(
.clk(clk24576), .rst(rst),
.sck_o(sck_o), .bck_o(bck_o), .data_o(data_o), .lrck_o(lrck_o),
.data_i(data_d), .lrck_i(lrck_d), .ack_i(ack_d), .pop_o(pop_d));
always @(posedge clk24576) begin
if(rst) begin
pop_s <= 2'b00;
lrck_d <= 0;
end else if(pop_d) begin
pop_s <= 2'b01;
lrck_d <= 0;
end else if(pop_s[0]) begin
pop_s <= 2'b10;
lrck_d <= 0;
end else begin
pop_s <= 2'b00;
lrck_d <= 1;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUF_2_V
`define SKY130_FD_SC_LP__BUF_2_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__buf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__buf_2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__buf_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUF_2_V
|
(** * Logic: Logic in Coq *)
(* $Date: 2011-06-22 10:06:32 -0400 (Wed, 22 Jun 2011) $ *)
Require Export "Prop".
Require Import LibTactics.
(** Coq's built-in logic is extremely small: [Inductive] definitions,
universal quantification ([forall]), and implication ([->]) are
primitive, but all the other familiar logical connectives --
conjunction, disjunction, negation, existential quantification,
even equality -- can be defined using just these. *)
(* ########################################################### *)
(** * Quantification and Implication *)
(** In fact, [->] and [forall] are the _same_ primitive! Coq's [->]
notation is actually just a shorthand for [forall]. The [forall]
notation is more general, because it allows us to _name_ the
hypothesis. *)
(** For example, consider this proposition: *)
Definition funny_prop1 := forall n, forall (E : ev n), ev (n+4).
(** If we had a proof term inhabiting this proposition, it would be a
function with two arguments: a number [n] and some evidence that
[n] is even. But the name [E] for this evidence is not used in
the rest of the statement of [funny_prop1], so it's a bit silly to
bother making up a name. We could write it like this instead: *)
Definition funny_prop1' := forall n, forall (_ : ev n), ev (n+4).
(** Or we can write it in more familiar notation: *)
Definition funny_prop1'' := forall n, ev n -> ev (n+4).
(** This illustrates that "[P -> Q]" is just syntactic sugar for
"[forall (_:P), Q]". *)
(* ########################################################### *)
(** * Conjunction *)
(** The logical conjunction of propositions [P] and [Q] is
represented using an [Inductive] definition with one
constructor. *)
Inductive and (P Q : Prop) : Prop :=
conj : P -> Q -> (and P Q).
(** Note that, like the definition of [ev] in the previous
chapter, this definition is parameterized; however, in this case,
the parameters are themselves propositions, rather than numbers. *)
(** The intuition behind this definition is simple: to
construct evidence for [and P Q], we must provide evidence
for [P] and evidence for [Q]. More precisely:
- [conj p q] can be taken as evidence for [and P Q] if [p]
is evidence for [P] and [q] is evidence for [Q]; and
- this is the _only_ way to give evidence for [and P Q] --
that is, if someone gives us evidence for [and P Q], we
know it must have the form [conj p q], where [p] is
evidence for [P] and [q] is evidence for [Q].
Since we'll be using conjunction a lot, let's introduce a more
familiar-looking infix notation for it. *)
Notation "P /\ Q" := (and P Q) : type_scope.
(** (The [type_scope] annotation tells Coq that this notation
will be appearing in propositions, not values.) *)
(** Consider the "type" of the constructor [conj]: *)
Check conj.
(* ===> forall P Q : Prop, P -> Q -> P /\ Q *)
(** Notice that it takes 4 inputs -- namely the propositions [P]
and [Q] and evidence for [P] and [Q] -- and returns as output the
evidence of [P /\ Q]. *)
(** Besides the elegance of building everything up from a tiny
foundation, what's nice about defining conjunction this way is
that we can prove statements involving conjunction using the
tactics that we already know. For example, if the goal statement
is a conjuction, we can prove it by applying the single
constructor [conj], which (as can be seen from the type of [conj])
solves the current goal and leaves the two parts of the
conjunction as subgoals to be proved separately. *)
Theorem and_example :
(ev 0) /\ (ev 4).
Proof.
apply conj.
(* Case "left". *) apply ev_0.
(* Case "right". *) apply ev_SS. apply ev_SS. apply ev_0. Qed.
(** Let's take a look at the proof object for the above theorem. *)
Print and_example.
(* ===> conj (ev 0) (ev 4) ev_0 (ev_SS 2 (ev_SS 0 ev_0))
: ev 0 /\ ev 4 *)
(** Note that the proof is of the form
[[
conj (ev 0) (ev 4) (...pf of ev 0...) (...pf of ev 4...)
]]
which is what you'd expect, given the type of [conj]. *)
(** Just for convenience, we can use the tactic [split] as a shorthand for
[apply conj]. *)
Theorem and_example' :
(ev 0) /\ (ev 4).
Proof.
split.
Case "left". apply ev_0.
Case "right". apply ev_SS. apply ev_SS. apply ev_0. Qed.
(** Conversely, the [inversion] tactic can be used to take a
conjunction hypothesis in the context, calculate what evidence
must have been used to build it, and put this evidence into the
proof context. *)
Theorem proj1 : forall P Q : Prop,
P /\ Q -> P.
Proof.
intros P Q H.
inversion H as [HP HQ].
apply HP. Qed.
(** **** Exercise: 1 star, optional (proj2) *)
Theorem proj2 : forall P Q : Prop,
P /\ Q -> Q.
Proof.
introv H.
inversion H as [HP HQ].
apply HQ. Qed.
(** [] *)
Theorem and_commut : forall P Q : Prop,
P /\ Q -> Q /\ P.
Proof.
introv H. inversion H as [HP HQ]. split; assumption.
Qed.
(*
(* WORKED IN CLASS *)
intros P Q H.
inversion H as [HP HQ].
split.
(* Case "left". *) apply HQ.
(* Case "right".*) apply HP. Qed. *)
(** Once again, we have commented out the [Case] tactics to make the
proof object for this theorem easy to understand. Examining it
shows that all that is really happening is taking apart a record
containing evidence for [P] and [Q] and rebuilding it in the
opposite order: *)
Print and_commut.
(* ===>
and_commut =
fun (P Q : Prop) (H : P /\ Q) =>
let H0 := match H with
| conj HP HQ => conj Q P HQ HP
end in H0
: forall P Q : Prop, P /\ Q -> Q /\ P *)
(** **** Exercise: 2 stars (and_assoc) *)
(** In the following proof, notice how the _nested pattern_ in the
[inversion] breaks [H : P /\ (Q /\ R)] down into [HP: P], [HQ :
Q], and [HR : R]. Finish the proof from there: *)
Theorem and_assoc : forall P Q R : Prop,
P /\ (Q /\ R) -> (P /\ Q) /\ R.
Proof.
intros P Q R H.
inversion H as [HP [HQ HR]].
split; [split | ]; assumption.
Qed.
(** [] *)
(** **** Exercise: 2 stars, recommended (even_ev) *)
(** Now we can prove the other direction of the equivalence of [even]
and [ev], which we left hanging in the last chapter. Notice that
the left-hand conjunct here is the statement we are actually
interested in; the right-hand conjunct is needed in order to make
the induction hypothesis strong enough that we can carry out the
reasoning in the inductive step. (To see why this is needed, try
proving the left conjunct by itself and observe where things get
stuck.) *)
Theorem even_ev_fails : forall n : nat,
even n -> ev n.
Proof.
induction n.
intros. apply ev_0.
Admitted.
Theorem even_ev : forall n : nat,
(even n -> ev n) /\ (even (S n) -> ev (S n)).
Proof.
(* Hint: Use induction on [n]. *)
induction n as [|n']; [| inversion IHn' as [H0 H1]]; split; intros.
apply ev_0.
inversion H.
apply H1. assumption.
apply ev_SS. apply H0. unfold even. unfold even in H. simpl in H. assumption.
Qed.
(** [] *)
(** **** Exercise: 2 stars *)
(** Construct a proof object demonstrating the following proposition. *)
Definition conj_fact : forall P Q R, P /\ Q -> Q /\ R -> P /\ R :=
fun _ _ _ pq qr =>
match pq with
| conj p q =>
match qr with
| conj q2 r => conj _ _ p r
end
end.
(** [] *)
(* ###################################################### *)
(** ** Iff *)
(** The familiar logical "if and only if" is just the
conjunction of two implications. *)
Definition iff (P Q : Prop) := (P -> Q) /\ (Q -> P).
Notation "P <-> Q" := (iff P Q)
(at level 95, no associativity) : type_scope.
Theorem iff_implies : forall P Q : Prop,
(P <-> Q) -> P -> Q.
Proof.
intros P Q H.
inversion H as [HAB HBA]. apply HAB. Qed.
Theorem iff_sym : forall P Q : Prop,
(P <-> Q) -> (Q <-> P).
Proof.
(* WORKED IN CLASS *)
intros P Q H.
inversion H as [HAB HBA].
split.
Case "->". apply HBA.
Case "<-". apply HAB. Qed.
(** **** Exercise: 1 star (iff_properties) *)
(** Using the above proof that [<->] is symmetric ([iff_sym]) as
a guide, prove that it is also reflexive and transitive. *)
Theorem iff_refl : forall P : Prop,
P <-> P.
Proof.
intros. split; intros; assumption.
Qed.
Theorem iff_trans : forall P Q R : Prop,
(P <-> Q) -> (Q <-> R) -> (P <-> R).
Proof.
introv pqEq qrEq. inversion pqEq as [pq qp]. inversion qrEq as [qr rq].
dup.
split; intros; tauto.
split.
Case "P -> R". introv p. apply qr. apply pq. apply p.
Case "R -> P". introv r. apply qp. apply rq. apply r.
Qed.
(** Hint: If you have an iff hypothesis in the context, you can use
[inversion] to break it into two separate implications. (Think
about why this works.) *)
(** [] *)
(** **** Exercise: 2 stars (MyProp_iff_ev) *)
(** We have seen that the families of propositions [MyProp] and [ev]
actually characterize the same set of numbers (the even ones).
Prove that [MyProp n <-> ev n] for all [n]. Just for fun, write
your proof as an explicit proof object, rather than using
tactics. (_Hint_: if you make use of previously defined thoerems,
you should only need a single line!) *)
Definition MyProp_iff_ev : forall n, MyProp n <-> ev n :=
fun n => conj _ _ (ev_MyProp _) (MyProp_ev _).
(** [] *)
(** Some of Coq's tactics treat [iff] statements specially, thus
avoiding the need for some low-level manipulation when reasoning
with them. In particular, [rewrite] can be used with [iff]
statements, not just equalities. *)
(* ############################################################ *)
(** * Disjunction *)
(** Disjunction ("logical or") can also be defined as an
inductive proposition. *)
Inductive or (P Q : Prop) : Prop :=
| or_introl : P -> or P Q
| or_intror : Q -> or P Q.
Notation "P \/ Q" := (or P Q) : type_scope.
(** Consider the "type" of the constructor [or_introl]: *)
Check or_introl.
(* ===> forall P Q : Prop, P -> P \/ Q *)
(** It takes 3 inputs, namely the propositions [P],[Q] and
evidence of [P], and returns as output, the evidence of [P /\ Q].
Next, look at the type of [or_intror]: *)
Check or_intror.
(* ===> forall P Q : Prop, Q -> P \/ Q *)
(** It is like [or_introl] but it requires evidence of [Q]
instead of evidence of [P]. *)
(** Intuitively, there are two ways of giving evidence for [P \/ Q]:
- give evidence for [P] (and say that it is [P] you are giving
evidence for! -- this is the function of the [or_introl]
constructor), or
- give evidence for [Q], tagged with the [or_intror]
constructor. *)
(** Since [P \/ Q] has two constructors, doing [inversion] on a
hypothesis of type [P \/ Q] yields two subgoals. *)
Theorem or_commut : forall P Q : Prop,
P \/ Q -> Q \/ P.
Proof.
intros P Q H.
inversion H as [HP | HQ].
Case "right". apply or_intror. apply HP.
Case "left". apply or_introl. apply HQ. Qed.
(** From here on, we'll use the shorthand tactics [left] and [right]
in place of [apply or_introl] and [apply or_intror]. *)
Theorem or_commut' : forall P Q : Prop,
P \/ Q -> Q \/ P.
Proof.
intros P Q H.
inversion H as [HP | HQ].
Case "right". right. apply HP.
Case "left". left. apply HQ. Qed.
(** **** Exercise: 2 stars, optional (or_commut'') *)
(** Try to write down an explicit proof object for [or_commut] (without
using [Print] to peek at the ones we already defined!). *)
Check or_commut'.
Definition or_commut'' P Q (pq: P \/ Q): Q \/ P :=
match pq with
| or_introl p => or_intror _ _ p
| or_intror q => or_introl _ _ q
end.
(** [] *)
Theorem or_distributes_over_and_1 : forall P Q R : Prop,
P \/ (Q /\ R) -> (P \/ Q) /\ (P \/ R).
Proof.
intros P Q R. intros H. inversion H as [HP | [HQ HR]].
Case "left". split.
SCase "left". left. apply HP.
SCase "right". left. apply HP.
Case "right". split.
SCase "left". right. apply HQ.
SCase "right". right. apply HR. Qed.
(** **** Exercise: 2 stars, recommended (or_distributes_over_and_2) *)
Theorem or_distributes_over_and_2 : forall P Q R : Prop,
(P \/ Q) /\ (P \/ R) -> P \/ (Q /\ R).
Proof.
introv H. inversion H as [[HP | HQ] [HP' | HR]].
Case "PP".
left. apply HP.
Case "PR".
left. apply HP.
Case "QP".
left. apply HP'.
Case "QR".
right. split; assumption.
Qed.
(** [] *)
(** **** Exercise: 1 star (or_distributes_over_and) *)
Theorem or_distributes_over_and : forall P Q R : Prop,
P \/ (Q /\ R) <-> (P \/ Q) /\ (P \/ R).
Proof.
split; [apply or_distributes_over_and_1 | apply or_distributes_over_and_2].
Qed.
(** [] *)
(* ################################################### *)
(** ** Relating [/\] and [\/] with [andb] and [orb] *)
(** We've already seen several places where analogous structures
can be found in Coq's computational ([Type]) and logical ([Prop])
worlds. Here is one more: the boolean operators [andb] and [orb]
are obviously analogs, in some sense, of the logical connectives
[/\] and [\/]. This analogy can be made more precise by the
following theorems, which show how to translate knowledge about
[andb] and [orb]'s behaviors on certain inputs into propositional
facts about those inputs. *)
Theorem andb_true__and : forall b c,
andb b c = true -> b = true /\ c = true.
Proof.
introv H. unfold andb in H. split.
Case "b = true".
destruct b; [reflexivity | inversion H].
Case "c = true".
destruct c; [reflexivity | destruct b; inversion H].
Qed.
(*
(* WORKED IN CLASS *)
intros b c H.
destruct b.
Case "b = true". destruct c.
SCase "c = true". apply conj. reflexivity. reflexivity.
SCase "c = false". inversion H.
Case "b = false". inversion H. Qed.
*)
Theorem and__andb_true : forall b c,
b = true /\ c = true -> andb b c = true.
Proof.
introv H.
inversion H. subst. reflexivity.
Qed.
(*
(* WORKED IN CLASS *)
intros b c H.
inversion H.
rewrite H0. rewrite H1. reflexivity. Qed.*)
(** **** Exercise: 1 star (bool_prop) *)
Theorem andb_false : forall b c,
andb b c = false -> b = false \/ c = false.
Proof.
introv H.
destruct b; destruct c; inversion H.
Case "c = false". right. reflexivity.
Case "b = false". left. reflexivity.
Case "b = c = false". left. reflexivity.
Qed.
Theorem orb_true : forall b c,
orb b c = true -> b = true \/ c = true.
Proof.
introv H.
destruct b; destruct c; inversion H.
Case "c = false". right. reflexivity.
Case "b = false". left. reflexivity.
Case "b = c = false". right. reflexivity.
Qed.
Theorem orb_false : forall b c,
orb b c = false -> b = false /\ c = false.
Proof.
introv H. destruct b; destruct c; inversion H; split; reflexivity.
Qed.
(** [] *)
(* ################################################### *)
(** * Falsehood *)
(** Logical falsehood can be represented in Coq as an inductively
defined proposition with no constructors. *)
Inductive False : Prop := .
(** Intuition: [False] is a proposition for which there is no way
to give evidence. *)
(** **** Exercise: 1 star (False_ind_principle) *)
(** Can you predict the induction principle for falsehood? *)
Check False_ind.
(* False_ind *)
(* : forall P : Prop, False -> P *)
(** [] *)
(** Since [False] has no constructors, inverting an assumption
of type [False] always yields zero subgoals, allowing us to
immediately prove any goal. *)
Theorem False_implies_nonsense :
False -> 2 + 2 = 5.
Proof.
intros contra.
inversion contra. Qed.
(** How does this work? The [inversion] tactic breaks [contra] into
each of its possible cases, and yields a subgoal for each case.
As [contra] is evidence for [False], it has _no_ possible cases,
hence, there are no possible subgoals and the proof is done. *)
(** Conversely, the only way to prove [False] is if there is already
something nonsensical or contradictory in the context: *)
Theorem nonsense_implies_False :
2 + 2 = 5 -> False.
Proof.
intros contra.
inversion contra. Qed.
(** Actually, since the proof of [False_implies_nonsense]
doesn't actually have anything to do with the specific nonsensical
thing being proved; it can easily be generalized to work for an
arbitrary [P]: *)
Theorem ex_falso_quodlibet : forall (P:Prop),
False -> P.
Proof.
intros P contra.
inversion contra. Qed.
(** The Latin _ex falso quodlibet_ means, literally, "from
falsehood follows whatever you please." This theorem is also
known as the _principle of explosion_. *)
(* #################################################### *)
(** ** Truth *)
(** Since we have defined falsehood in Coq, we might wonder whether it
is possible to define truth in the same way. Naturally, the
answer is yes. *)
(** **** Exercise: 2 stars (True_induction) *)
(** Define [True] as another inductively defined proposition. What
induction principle will Coq generate for your definition? (The
intution is that [True] should be a proposition for which it is
trivial to give evidence. Alternatively, you may find it easiest
to start with the induction principle and work backwards to the
inductive definition.) *)
Inductive True :=
| tt : True.
Check True_ind.
(** [] *)
(** However, unlike [False], which we'll use extensively, [True] is
just a theoretical curiosity: it is trivial (and therefore
uninteresting) to prove as a goal, and it carries no useful
information as a hypothesis. *)
(* #################################################### *)
(** * Negation *)
(** The logical complement of a proposition [P] is written [not
P] or, for shorthand, [~P]: *)
Definition not (P:Prop) := P -> False.
(** The intuition is that, if [P] is not true, then anything at
all (even [False]) follows from assuming [P]. *)
Notation "~ x" := (not x) : type_scope.
Check not.
(* ===> Prop -> Prop *)
(** It takes a little practice to get used to working with
negation in Coq. Even though you can see perfectly well why
something is true, it can be a little hard at first to get things
into the right configuration so that Coq can see it! Here are
proofs of a few familiar facts about negation to get you warmed
up. *)
Theorem not_False :
~ False.
Proof.
unfold not. intros H. inversion H. Qed.
Theorem contradiction_implies_anything : forall P Q : Prop,
(P /\ ~P) -> Q.
Proof.
introv contra. inversion contra as [HP HNP]. apply HNP in HP. inversion HP.
Restart.
(* WORKED IN CLASS *)
intros P Q H. inversion H as [HP HNA]. unfold not in HNA.
apply HNA in HP. inversion HP. Qed.
Theorem double_neg : forall P : Prop,
P -> ~~P.
Proof.
introv HP. unfold not. introv HNP. apply HNP. apply HP.
Restart.
(* WORKED IN CLASS *)
intros P H. unfold not. intros G. apply G. apply H. Qed.
(** **** Exercise: 2 stars, recommended (double_neg_inf) *)
(** Write an informal proof of [double_neg]:
_Theorem_: [P] implies [~~P], for any proposition [P].
_Proof_: Suppose that [P] is true. We need then to prove that
[~~P], that is that [(P -> False) -> False]. Let us introduce (HNP:
P -> False) in the context; we need now to prove False. Since we
know that P is true and that HNP is true, by modus ponens we can
conclude that P's conclusion, False, is true.
[] *)
(** **** Exercise: 2 stars, recommended (contrapositive) *)
Theorem contrapositive : forall P Q : Prop,
(P -> Q) -> (~Q -> ~P).
Proof.
unfold not.
introv HPQ HNQ HP. apply HNQ in HPQ. assumption. assumption.
Qed.
(** [] *)
(** **** Exercise: 1 star (not_both_true_and_false) *)
Theorem not_both_true_and_false : forall P : Prop,
~ (P /\ ~P).
Proof.
unfold not. introv HPNP. inversion HPNP as [HP HNP]. apply (HNP HP).
Qed.
(** [] *)
Theorem five_not_even :
~ ev 5.
Proof.
unfold not. introv H. inverts H as H. inverts H as H. inverts H as H.
Restart.
(* WORKED IN CLASS *)
unfold not. intros Hev5. inversion Hev5 as [|n Hev3 Heqn].
inversion Hev3 as [|n' Hev1 Heqn']. inversion Hev1. Qed.
(** **** Exercise: 1 star ev_not_ev_S *)
(** Theorem [five_not_even] confirms the unsurprising fact that five
is not an even number. Prove this more interesting fact: *)
Theorem ev_not_ev_S : forall n,
ev n -> ~ ev (S n).
Proof.
unfold not. intros n H. induction H. (* not n! *)
Case "n = 0". introv H. inversion H.
Case "n = S n'". introv H1. inverts H1 as. apply IHev.
Qed.
(** [] *)
(** **** Exercise: 1 star (informal_not_PNP) *)
(** Write an informal proof (in English) of the proposition [forall P
: Prop, ~(P /\ ~P)]. *)
(* FILL IN HERE *)
(** [] *)
(** Note that some theorems that are true in classical logic
are _not_ provable in Coq's "built in" constructive logic... *)
Theorem classic_double_neg : forall P : Prop,
~~P -> P.
Proof.
(* WORKED IN CLASS *)
intros P H. unfold not in H.
(* But now what? There is no way to "invent" evidence for [P]. *)
Admitted.
(** **** Exercise: 5 stars, optional (classical_axioms) *)
(** For those who like a challenge, here is an exercise
taken from the Coq'Art book (p. 123). The following five
statements are often considered as characterizations of
classical logic (as opposed to constructive logic, which is
what is "built in" to Coq). We can't prove them in Coq, but
we can consistently add any one of them as an unproven axiom
if we wish to work in classical logic. Prove that these five
propositions are equivalent. *)
Definition peirce := forall P Q: Prop,
((P->Q)->P)->P.
Definition classic := forall P:Prop,
~~P -> P.
Definition excluded_middle := forall P:Prop,
P \/ ~P.
Definition de_morgan_not_and_not := forall P Q:Prop,
~(~P/\~Q) -> P\/Q.
Definition implies_to_or := forall P Q:Prop,
(P->Q) -> (~P\/Q).
(* FILL IN HERE *)
Theorem excluded_middle_to_peirce : excluded_middle -> peirce.
Proof.
unfold peirce. unfold excluded_middle. unfold not.
introv no_middle. introv H.
assert (PorNP := no_middle P).
inversion PorNP as [| HNP].
Case "P". assumption.
Case "NP". apply H. intro HP. apply ex_falso_quodlibet. apply HNP. apply HP.
Qed.
(*
Theorem classic_to_peirce : classic -> peirce.
Proof.
unfold peirce. unfold classic. unfold not.
introv classic.
apply classic.
introv H. apply H.
introv Hpeirce. apply Hpeirce.
*)
Theorem excluded_middle_to_classic : excluded_middle -> classic.
Proof.
unfold classic. unfold excluded_middle. unfold not.
introv H HNNP.
assert (PorNP := H P).
inversion PorNP as [HP | HNP].
Case "P". apply HP.
Case "~P". apply HNNP in HNP. inversion HNP.
Qed.
(*
Theorem classic_to_excluded_middle : classic -> excluded_middle.
Proof.
unfold classic. unfold excluded_middle. unfold not.
introv classic. introv.
assert (classicP := classic P).
(* cases ((P -> False) -> False). *)
Admitted.
Theorem classic_to_de_morgan_not_and_not : classic -> de_morgan_not_and_not.
Proof.
unfold classic. unfold de_morgan_not_and_not. unfold not.
intros.
assert (H2 := H P).
*)
Theorem excluded_middle_to_de_morgan_not_and_not :
excluded_middle -> de_morgan_not_and_not.
Proof.
unfold excluded_middle. unfold de_morgan_not_and_not.
introv no_middle. introv no_conj.
assert (PorNP := no_middle P).
assert (QorNQ := no_middle Q).
inversion PorNP as [| NP].
Case "P". left. assumption.
Case "NQ".
inversion QorNQ as [| NQ].
SCase "Q". right. assumption.
SCase "NQ".
unfold not in no_conj, NP, NQ.
apply ex_falso_quodlibet.
apply (no_conj (conj _ _ NP NQ)).
Qed.
Theorem excluded_middle_to_implies_to_or : excluded_middle -> implies_to_or.
Proof.
unfold excluded_middle. unfold implies_to_or.
introv no_middle. introv PtoQ.
assert (PorNP := no_middle P).
inversion PorNP.
Case "P". right. apply PtoQ. assumption.
Case "NP". left. assumption.
Qed.
(*
Theorem implies_to_or_to_excluded_middle : implies_to_or -> excluded_middle.
Proof.
unfold implies_to_or. unfold excluded_middle. unfold not.
introv impl_to_or. introv
assert (H := impl_to_or P (~P)).
Theorem implies_to_or_to_classic : implies_to_or -> classic.
Proof.
unfold implies_to_or. unfold classic.
introv impl_to_or. introv NNP.
unfold not in NNP.
(* assert (H1 := impl_to_or P (~P)).
assert (H2 := impl_to_or (not P) False).
assert (H3 := impl_to_or P False). *)
unfold not in *.
apply H2 in NNP.
*)
(** [] *)
(* ########################################################## *)
(** ** Inequality *)
(** Saying [x <> y] is just the same as saying [~(x = y)]. *)
Notation "x <> y" := (~ (x = y)) : type_scope.
(** Since inequality involves a negation, it again requires
a little practice to be able to work with it fluently. Here
is one very useful trick. If you are trying to prove a goal
that is nonsensical (e.g., the goal state is [false = true]),
apply the lemma [ex_falso_quodlibet] to change the goal to
[False]. This makes it easier to use assumptions of the form
[~P] that are available in the context -- in particular,
assumptions of the form [x<>y]. *)
Theorem not_false_then_true : forall b : bool,
b <> false -> b = true.
Proof.
intros b H. destruct b.
Case "b = true". reflexivity.
Case "b = false".
unfold not in H.
apply ex_falso_quodlibet.
apply H. reflexivity. Qed.
SearchAbout beq_nat.
Check beq_nat_eq.
(* beq_nat_eq *)
(* : forall n m : nat, true = beq_nat n m -> n = m *)
(** **** Exercise: 2 stars, recommended (not_eq_beq_false) *)
Theorem not_eq_beq_false : forall n n' : nat,
n <> n' ->
beq_nat n n' = false.
Proof.
unfold not.
introv neq.
cases (beq_nat n n'); [| reflexivity].
apply ex_falso_quodlibet.
apply neq.
apply beq_nat_eq. symmetry. assumption.
Qed.
(* unfold not.
introv neq.
induction n as [|n0].
Case "n = 0".
induction n'.
apply ex_falso_quodlibet. apply neq. reflexivity.
reflexivity.
Case "n = S n0".
induction n'.
reflexivity.
simpl.
destruct (beq_nat n0 n'). apply ex_falso_quodlibet.
Restart.
unfold not.
introv neq.
cases (beq_nat n n'); [| reflexivity].
apply ex_falso_quodlibet.
apply neq.
destruct n; destruct n'; try reflexivity; inverts H. *)
(** [] *)
(** **** Exercise: 2 stars, optional (beq_false_not_eq) *)
Theorem beq_false_not_eq : forall n m,
false = beq_nat n m -> n <> m.
Proof.
unfold not.
introv beq_False nEqm. subst.
Check beq_nat_refl.
(* beq_nat_refl *)
(* : forall n : nat, true = beq_nat n n *)
rewrite <- beq_nat_refl in beq_False.
inversion beq_False.
Qed.
(** [] *)
(* ############################################################ *)
(** * Existential Quantification *)
(** Another critical logical connective is _existential
quantification_. We can capture what this means with the
following definition: *)
Inductive ex (X:Type) (P : X->Prop) : Prop :=
ex_intro : forall (witness:X), P witness -> ex X P.
(** That is, [ex] is a family of propositions indexed by a type [X]
and a property [P] over [X]. In order to give evidence for the
assertion "there exists an [x] for which the property [P] holds"
we must actually name a _witness_ -- a specific value [x] -- and
then give evidence for [P x], i.e., evidence that [x] has the
property [P].
For example, consider this existentially quantified proposition: *)
Definition some_nat_is_even : Prop :=
ex nat ev.
(** To prove this proposition, we need to choose a particular number
as witness -- say, 4 -- and give some evidence that that number is
even. *)
Definition snie : some_nat_is_even :=
ex_intro _ ev 4 (ev_SS 2 (ev_SS 0 ev_0)).
(** Coq's notation definition facility can be used to introduce
more familiar notation for writing existentially quantified
propositions, exactly parallel to the built-in syntax for
universally quantified propositions. Instead of writing [ex nat
ev] to express the proposition that there exists some number that
is even, for example, we can write [exists x:nat, ev x]. (It is
not necessary to understand exactly how the [Notation] definition
works.) *)
Notation "'exists' x , p" := (ex _ (fun x => p))
(at level 200, x ident, right associativity) : type_scope.
Notation "'exists' x : X , p" := (ex _ (fun x:X => p))
(at level 200, x ident, right associativity) : type_scope.
(** We can use the same set of tactics as always for
manipulating existentials. For example, if to prove an
existential, we [apply] the constructor [ex_intro]. Since the
premise of [ex_intro] involves a variable ([witness]) that does
not appear in its conclusion, we need to explicitly give its value
when we use [apply]. *)
Example exists_example_1 : exists n, n + (n * n) = 6.
Proof.
apply ex_intro with (witness:=2).
reflexivity. Qed.
(** Note, again, that we have to explicitly give the witness. *)
(** Or, instead of writing [apply ex_intro with (witness:=e)] all the
time, we can use the convenient shorthand [exists e], which means
the same thing. *)
Example exists_example_1' : exists n,
n + (n * n) = 6.
Proof.
exists 2.
reflexivity. Qed.
(** Conversely, if we have an existential hypothesis in the
context, we can eliminate it with [inversion]. Note the use
of the [as...] pattern to name the variable that Coq
introduces to name the witness value and get evidence that
the hypothesis holds for the witness. (If we don't
explicitly choose one, Coq will just call it [witness], which
makes proofs confusing.) *)
Theorem exists_example_2 : forall n,
(exists m, n = 4 + m) ->
(exists o, n = 2 + o).
Proof.
intros n H.
inversion H as [m Hm].
exists (2 + m).
apply Hm. Qed.
(** **** Exercise: 1 star (english_exists) *)
(** In English, what does the proposition
[[
ex nat (fun n => ev (S n))
]]
mean? *)
(* FILL IN HERE *)
(** Complete the definition of the following proof object: *)
Check ex_intro.
(* ex_intro *)
(* : forall (X : Type) (P : X -> Prop) (witness : X), *)
(* P witness -> exists x, P x *)
Definition p : ex nat (fun n => ev (S n)) := ex_intro _ (fun n => ev (S n)) 1 (ev_SS _ ev_0).
Check p.
(* p *)
(* : exists n : nat, ev (S n) *)
(** [] *)
(** **** Exercise: 1 star (dist_not_exists) *)
(** Prove that "[P] holds for all [x]" and "there is no [x] for
which [P] does not hold" are equivalent assertions. *)
Theorem dist_not_exists : forall (X:Type) (P : X -> Prop),
(forall x, P x) -> ~ (exists x, ~ P x).
Proof.
unfold not. introv forAll nExists.
inversion nExists as [x px].
apply px. apply forAll.
Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (not_exists_dist) *)
(** The other direction requires the classical "law of the excluded
middle": *)
Theorem not_exists_dist :
excluded_middle ->
forall (X:Type) (P : X -> Prop),
~ (exists x, ~ P x) -> (forall x, P x).
Proof.
unfold excluded_middle. unfold not.
introv no_middle nnExists. introv.
assert (H := no_middle (P x)).
inversion H.
Case "P x". assumption.
Case "~ (P x)".
apply ex_falso_quodlibet.
apply nnExists.
exists x. assumption.
Qed.
(** [] *)
(** **** Exercise: 2 stars (dist_exists_or) *)
(** Prove that existential quantification distributes over
disjunction. *)
Theorem dist_exists_or : forall (X:Type) (P Q : X -> Prop),
(exists x, P x \/ Q x) <-> (exists x, P x) \/ (exists x, Q x).
Proof.
split.
Case "->".
introv exOr.
inversion exOr as [x [Px | Qx]]; [left | right]; exists x; assumption.
Case "<-".
introv orEx.
inversion orEx as [[x Px] | [x Qx]]; exists x; [left | right]; assumption.
Qed.
(** [] *)
Print dist_exists_or.
(* ###################################################### *)
(** * Equality *)
(** Even Coq's equality relation is not built in. It has the
following inductive definition. (We enclose the definition in a
module to avoid confusion with the standard library equality,
which we have used extensively already.) *)
Module MyEquality.
Inductive eq (X:Type) : X -> X -> Prop :=
refl_equal : forall x, eq X x x.
Check eq_ind.
(* eq_ind *)
(* : forall (X : Type) (P : X -> X -> Prop), *)
(* (forall x : X, P x x) -> forall y y0 : X, eq X y y0 -> P y y0 *)
(** Standard infix notation (using Coq's type argument synthesis): *)
Notation "x = y" := (eq _ x y)
(at level 70, no associativity) : type_scope.
(** This is a bit subtle. The way to think about it is that, given a
set [X], it defines a _family_ of propositions "[x] is equal to
[y]," indexed by pairs of values ([x] and [y]) from [X]. There is
just one way of constructing evidence for members of this family:
applying the constructor [refl_equal] to a type [X] and a value [x
: X] yields evidence that [x] is equal to [x]. *)
(** Here is a slightly different definition -- the one that actually
appears in the Coq standard library. *)
Inductive eq' (X:Type) (x:X) : X -> Prop :=
refl_equal' : eq' X x x.
Check eq'_ind.
(* eq'_ind *)
(* : forall (X : Type) (x : X) (P : X -> Prop), *)
(* P x -> forall y : X, eq' X x y -> P y *)
Notation "x =' y" := (eq' _ x y)
(at level 70, no associativity) : type_scope.
(** **** Exercise: 3 stars, optional (two_defs_of_eq_coincide) *)
(** Verify that the two definitions of equality are equivalent. *)
Theorem two_defs_of_eq_coincide : forall (X:Type) (x y : X),
x = y <-> x =' y.
Proof.
split; introv eq; inverts eq; [apply refl_equal' | apply refl_equal].
Qed.
(** [] *)
(** The advantage of the second definition is that the induction
principle that Coq derives for it is precisely the familiar
principle of _Leibniz equality_: what we mean when we say "[x] and
[y] are equal" is that every property on [P] that is true of [x]
is also true of [y]. *)
Check eq'_ind.
(* ===> forall (X : Type) (x : X) (P : X -> Prop),
P x -> forall y : X, x =' y -> P y *)
(** One important consideration remains. Clearly, we can use
[refl_equal] to construct evidence that, for example, [2 = 2].
Can we also use it to construct evidence that [1 + 1 = 2]? Yes.
Indeed, it is the very same piece of evidence! The reason is that
Coq treats as "the same" any two terms that are _convertible_
according to a simple set of computation rules. These rules,
which are similar to those used by [Eval simpl], include
evaluation of function application, inlining of definitions, and
simplification of [match]es.
In tactic-based proofs of equality, the conversion rules are
normally hidden in uses of [simpl] (either explicit or implicit in
other tactics such as [reflexivity]). But you can see them
directly at work in the following explicit proof objects: *)
Definition four : 2 + 2 = 1 + 3 :=
refl_equal nat 4.
Definition singleton : forall (X:Set) (x:X), []++[x] = x::[] :=
fun (X:Set) (x:X) => refl_equal (list X) [x].
End MyEquality.
(* ####################################################### *)
(** ** Inversion, Again *)
(** We've seen [inversion] used with both equality hypotheses and
hypotheses about inductively defined propositions. Now that we've
seen that these are actually the same thing, we're in a position
to take a closer look at how [inversion] behaves...
In general, the [inversion] tactic
- takes a hypothesis [H] whose type [P] is inductively defined,
and
- for each constructor [C] in [P]'s definition,
- generates a new subgoal in which we assume [H] was
built with [C],
- adds the arguments (premises) of [C] to the context of
the subgoal as extra hypotheses,
- matches the conclusion (result type) of [C] against the
current goal and calculates a set of equalities that must
hold in order for [C] to be applicable,
- adds these equalities to the context of the subgoal, and
- if the equalities are not satisfiable (e.g., they involve
things like [S n = O]), immediately solves the subgoal.
_Example_: If we invert a hypothesis built with [or], there are two
constructors, so two subgoals get generated. The
conclusion (result type) of the constructor ([P \/ Q]) doesn't
place any restrictions on the form of [P] or [Q], so we don't get
any extra equalities in the context of the subgoal.
_Example_: If we invert a hypothesis built with [and], there is
only one constructor, so only one subgoal gets generated. Again,
the conclusion (result type) of the constructor ([P /\ Q]) doesn't
place any restrictions on the form of [P] or [Q], so we don't get
any extra equalities in the context of the subgoal. The
constructor does have two arguments, though, and these can be seen
in the context in the subgoal.
_Example_: If we invert a hypothesis built with [eq], there is
again only one constructor, so only one subgoal gets generated.
Now, though, the form of the [refl_equal] constructor does give us
some extra information: it tells us that the two arguments to [eq]
must be the same! The [inversion] tactic adds this fact to the
context. *)
(* ####################################################### *)
(** * Relations as Propositions *)
(** A proposition parameterized numbers (such as [ev]) can be
thought of as a _property_ -- i.e., it defines a subset of [nat],
namely those numbers for which the proposition is provable. In
the same way, a two-argument proposition can be thought of as a
_relation_ -- i.e., it defines a set of pairs for which the
proposition is provable. *)
Module LeFirstTry.
(** We've already seen an inductive definition of one
fundamental relation: equality. Another useful one is the "less
than or equal to" relation on numbers: *)
(** This definition should be fairly intuitive. It says that
there are two ways to give evidence that one number is less than
or equal to another: either observe that they are the same number,
or give evidence that the first is less than or equal to the
predecessor of the second. *)
Inductive le : nat -> nat -> Prop :=
| le_n : forall n, le n n
| le_S : forall n m, (le n m) -> (le n (S m)).
Check le_ind.
(* le_ind *)
(* : forall P : nat -> nat -> Prop, *)
(* (forall n : nat, P n n) -> *)
(* (forall n m : nat, le n m -> P n m -> P n (S m)) -> *)
(* forall n n0 : nat, le n n0 -> P n n0 *)
End LeFirstTry.
(** This is a reasonable definition of the [<=] relation, but we
can streamline it a little by observing that the left-hand
argument [n] is the same everywhere in the definition, so we can
actually make it a "general parameter" to the whole definition,
rather than an argument to each constructor. This is similar to
what we did in our second definition of the [eq] relation,
above. *)
Inductive le (n:nat) : nat -> Prop :=
| le_n : le n n
| le_S : forall m, (le n m) -> (le n (S m)).
Notation "m <= n" := (le m n).
(** The second one is better, even though it looks less symmetric.
Why? Because it gives us a simpler induction principle.
(The same was true of our second version of [eq].) *)
Check le_ind.
(* ===> forall (n : nat) (P : nat -> Prop),
P n ->
(forall m : nat, n <= m -> P m -> P (S m)) ->
forall n0 : nat, n <= n0 -> P n0 *)
(** By contrast, the induction principle that Coq calculates for the
first definition has a lot of extra quantifiers, which makes it
messier to work with when proving things by induction. Here is
the induction principle for the first [le]: *)
(* le_ind :
forall P : nat -> nat -> Prop,
(forall n : nat, P n n) ->
(forall n m : nat, le n m -> P n m -> P n (S m)) ->
forall n n0 : nat, le n n0 -> P n n0 *)
(** Proofs of facts about [<=] using the constructors [le_n] and
[le_S] follow the same patterns as proofs about properties, like
[ev] in the previous chapter. We can [apply] the constructors to
prove [<=] goals (e.g., to show that [3<=3] or [3<=6]), and we can
use tactics like [inversion] to extract information from [<=]
hypotheses in the context (e.g., to prove that [~(2 <= 1)].) *)
(** Here are some sanity checks on the definition. (Notice that,
although these are the same kind of simple "unit tests" as we gave
for the testing functions we wrote in the first few lectures, we
must construct their proofs explicitly -- [simpl] and
[reflexivity] don't do the job, because the proofs aren't just a
matter of simplifying computations. *)
Theorem test_le1 :
3 <= 3.
Proof.
(* WORKED IN CLASS *)
apply le_n. Qed.
Theorem test_le2 :
3 <= 6.
Proof.
(* WORKED IN CLASS *)
apply le_S. apply le_S. apply le_S. apply le_n. Qed.
Theorem test_le3 :
~ (2 <= 1).
Proof.
(* WORKED IN CLASS *)
intros H. inversion H. inversion H1. Qed.
(** The "strictly less than" relation [n < m] can now be defined
in terms of [le]. *)
Definition lt (n m:nat) := le (S n) m.
Notation "m < n" := (lt m n).
(** Here are a few more simple relations on numbers: *)
Inductive square_of : nat -> nat -> Prop :=
sq : forall n:nat, square_of n (n * n).
Inductive next_nat (n:nat) : nat -> Prop :=
| nn : next_nat n (S n).
Inductive next_even (n:nat) : nat -> Prop :=
| ne_1 : ev (S n) -> next_even n (S n)
| ne_2 : ev (S (S n)) -> next_even n (S (S n)).
(** **** Exercise: 2 stars, recommended (total_relation) *)
(** Define an inductive relation [total_relation] that holds
between every pair of natural numbers. *)
Inductive total_relation : nat -> nat -> Prop :=
r' : forall n m : nat, total_relation n m.
(** [] *)
(** **** Exercise: 2 stars (empty_relation) *)
(** Define an inductive relation [empty_relation] (on numbers)
that never holds. *)
Inductive empty_relation : nat -> nat -> Prop := .
(** [] *)
(** **** Exercise: 3 stars, recommended (R_provability) *)
Module R.
(** We can define three-place relations, four-place relations,
etc., in just the same way as binary relations. For example,
consider the following three-place relation on numbers: *)
Inductive R : nat -> nat -> nat -> Prop :=
| c1 : R 0 0 0
| c2 : forall m n o, R m n o -> R (S m) n (S o)
| c3 : forall m n o, R m n o -> R m (S n) (S o)
| c4 : forall m n o, R (S m) (S n) (S (S o)) -> R m n o
| c5 : forall m n o, R m n o -> R n m o.
(** - Which of the following propositions are provable?
- [R 1 1 2]
- [R 2 2 6]
- If we dropped constructor [c5] from the definition of [R],
would the set of provable propositions change? Briefly (1
sentence) explain your answer.
- If we dropped constructor [c4] from the definition of [R],
would the set of provable propositions change? Briefly (1
sentence) explain your answer.
- Yes; No.
- No; c5 only guarantees commutativity in the first two components, but the other constructors are already symmetric or dualizable.
- No.
*)
Definition R1 : R 1 1 2 := c3 _ _ _ (c2 _ _ _ c1).
Definition R1' : R 1 1 2 := c2 _ _ _ (c3 _ _ _ c1).
Print R1.
Print R1'.
(*
[]
*)
(** **** Exercise: 3 stars, optional (R_fact) *)
(** State and prove an equivalent characterization of the relation
[R]. That is, if [R m n o] is true, what can we say about [m],
[n], and [o], and vice versa?
*)
Theorem R_fact : forall m n o, R m n o <-> m + n = o.
Proof.
split; introv H.
Case "->".
induction H.
SCase "c1". reflexivity.
SCase "c2". simpl. congruence.
SCase "c3". rewrite <- plus_n_Sm; congruence.
SCase "c4".
inverts IHR as IHR. rewrite <- plus_n_Sm in IHR. inverts IHR. reflexivity.
SCase "c5".
subst. apply plus_comm.
Case "<-".
subst.
induction m as [|m']; simpl.
SCase "m = 0".
induction n as [|n'].
SSCase "n = 0". apply c1.
SSCase "n = S n'". apply c3. assumption.
SCase "m = S m'". apply c2. assumption.
Qed.
(** [] *)
End R.
(** **** Exercise: 3 stars, recommended (all_forallb) *)
(** Inductively define a property [all] of lists, parameterized by a
type [X] and a property [P : X -> Prop], such that [all X P l]
asserts that [P] is true for every element of the list [l]. *)
Inductive all (X : Type) (P : X -> Prop) : list X -> Prop :=
| all_nil : all X P []
| all_cons : forall x l, P x -> all X P l -> all X P (x :: l).
(** Recall the function [forallb], from the exercise
[forall_exists_challenge] in [Poly.v]: *)
Fixpoint forallb {X : Type} (test : X -> bool) (l : list X) : bool :=
match l with
| [] => true
| x :: l' => andb (test x) (forallb test l')
end.
(** Using the property [all], write down a specification for [forallb],
and prove that it satisfies the specification. Try to make your
specification as precise as possible.
Are there any important properties of the function [forallb] which
are not captured by your specification? *)
(* Complete specification of forallb. *)
Lemma forallb_all :
forall X test l, all X (fun x => test x = true) l <-> forallb test l = true.
Proof.
split; introv H.
Case "->".
induction H.
SCase "H = all_nil". reflexivity.
SCase "H = all_cons".
simpl. rewrite H. rewrite IHall. reflexivity.
Case "<-".
induction l as [| x l'].
SCase "l = []". apply all_nil.
SCase "l = x :: l'".
simpl in H.
assert (H2 : forallb test l' = true).
SSCase "proof of assertion".
apply andb_true_elim2 in H. apply H.
apply IHl' in H2.
assert (H3 : test x = true).
SSCase "proof of assertion".
apply andb_true_elim1 in H. apply H.
apply all_cons; assumption.
Qed.
(** [] *)
(** **** Exercise: 4 stars, optional (filter_challenge) *)
(** One of the main purposes of Coq is to prove that programs match
their specifications. To this end, let's prove that our
definition of [filter] matches a specification. Here is the
specification, written out informally in English.
Suppose we have a set [X], a function [test: X->bool], and a list
[l] of type [list X]. Suppose further that [l] is an "in-order
merge" of two lists, [l1] and [l2], such that every item in [l1]
satisfies [test] and no item in [l2] satisfies test. Then [filter
test l = l1].
A list [l] is an "in-order merge" of [l1] and [l2] if it contains
all the same elements as [l1] and [l2], in the same order as [l1]
and [l2], but possibly interleaved. For example,
[[
[1,4,6,2,3]
]]
is an in-order merge of
[[
[1,6,2]
]]
and
[[
[4,3].
]]
Your job is to translate this specification into a Coq theorem and
prove it. (Hint: You'll need to begin by defining what it means
for one list to be a merge of two others. Do this with an
inductive relation, not a [Fixpoint].) *)
Inductive merge_of {X} : list X -> list X -> list X -> Prop :=
| merge_of_nil : merge_of [] [] []
| merge_of_l : forall {x l1 l2 l3},
merge_of l1 l2 l3 ->
merge_of (x :: l1) l2 (x :: l3)
| merge_of_r : forall {x l1 l2 l3},
merge_of l1 l2 l3 ->
merge_of l1 (x :: l2) (x :: l3).
Example merge_of_1 : merge_of [1,6,2] [4,3] [1,4,6,2,3].
Proof.
apply merge_of_l.
apply merge_of_r.
repeat (apply merge_of_l).
apply merge_of_r.
apply merge_of_nil.
Qed.
Example merge_of_1' : merge_of [1,6,2] [4,3] [1,4,6,2,3] :=
merge_of_l (merge_of_r (merge_of_l (merge_of_l (merge_of_r merge_of_nil)))).
Print merge_of_1'.
Check filter.
Lemma merge_of_nil_any : forall X (l1 l2 : list X), merge_of [] l1 l2 -> l1 = l2.
Proof.
induction l1 as [|x1 l1']; introv H.
Case "l1 = []". inverts H. reflexivity.
Case "l1 = x1 :: l1'".
destruct l2 as [|x2 l2'].
SCase "l2 = []". inverts H.
SCase "l2 = x2 :: l2'".
inverts H as H.
apply IHl1' in H.
congruence.
Qed.
Theorem filter_spec_challenge :
forall X (l1 l2 l : list X) test,
all _ (fun x => test x = true) l1 ->
all _ (fun x => test x = false) l2 ->
merge_of l1 l2 l ->
filter test l = l1.
Proof.
introv all_l1_t all_l2_f.
induction all_l1_t; introv merge.
Case "all_nil".
inverts merge.
SCase "merge_of_nil". reflexivity.
SCase "merge_of_l".
apply merge_of_nil_any in H. subst.
induction (x :: l4) as [|x' l'].
SSCase "x :: l4 = []". reflexivity.
SSCase "x :: l4 = x' :: l'".
simpl.
inverts all_l2_f.
replace (test x') with false by assumption.
apply IHl', H2.
(*
inverts H.
SSCase "H = merge_of_nil".
inverts all_l2_f. simpl.
replace (test x) with false by assumption. reflexivity.
SSCase "H = ?".
(* inverts H0.
SCase "merge_of_r". *)
apply merge_of_nil_any in H0. subst. simpl.
inversion all_l2_f.
inversion H2. subst.
replace (test x) with false by assumption.
replace (test x0) with false by assumption.
*)
Case "all_cons".
Restart.
introv all_l1_t all_l2_f.
induction l as [|x l']; introv merge.
Case "l = []". inversion merge. reflexivity.
Case "l = cons".
Restart.
introv all_l1_t all_l2_f.
induction all_l2_f; introv merge.
Restart.
introv.
generalize dependent l2.
generalize dependent l1.
induction l as [|x l']; introv all_l1_t all_l2_f merge.
Case "l = []". inversion merge. reflexivity.
Case "l = x :: l'".
inverts merge.
SCase "merge_of_l".
inverts all_l1_t.
simpl. replace (test x) with true by assumption.
replace l0 with (filter test l'). reflexivity.
apply IHl' with (l2 := l2); assumption.
SCase "merge_of_r".
inverts all_l2_f.
simpl.
replace (test x) with false by assumption.
apply IHl' with (l2 := l3); assumption.
Qed.
(** [] *)
(** **** Exercise: 5 stars, optional (filter_challenge_2) *)
(** A different way to formally characterize the behavior of [filter]
goes like this: Among all subsequences of [l] with the property
that [test] evaluates to [true] on all their members, [filter test
l] is the longest. Express this claim formally and prove it. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 4 stars, optional (no_repeats) *)
(** The following inductively defined proposition... *)
Inductive appears_in {X:Type} (a:X) : list X -> Prop :=
| ai_here : forall l, appears_in a (a::l)
| ai_later : forall b l, appears_in a l -> appears_in a (b::l).
(** ...gives us a precise way of saying that a value [a] appears at
least once as a member of a list [l].
Here's a pair of warm-ups about [appears_in].
*)
Lemma appears_in_app : forall {X:Type} (xs ys : list X) (x:X),
appears_in x (xs ++ ys) -> appears_in x xs \/ appears_in x ys.
Proof.
(*
introv H.
inversion H.
Case "ai_here".
destruct xs as [|x' xs'].
SCase "xs = []".
simpl in H1. subst. right. constructor.
SCase "xs = x' :: xs'".
inverts H1. simpl in H. left. constructor.
Case "ai_later".
destruct xs as [|x' xs'].
SCase "xs = []".
simpl in H. subst. right. assumption.
SCase "xs = x' :: xs'".
simpl in H0. inverts H0.
inverts H1. simpl in H. left. constructor.
*)
introv. generalize dependent ys.
induction xs as [|x' xs']; simpl; introv H.
Case "xs = []".
right. assumption.
Case "xs = x' :: xs'".
inverts H.
SCase "left". left. constructor.
SCase "right".
apply IHxs' in H1.
destruct H1.
SSCase "left".
left. constructor. assumption.
SSCase "right".
right. assumption.
Qed.
Lemma app_appears_in : forall {X:Type} (xs ys : list X) (x:X),
appears_in x xs \/ appears_in x ys -> appears_in x (xs ++ ys).
Proof.
introv H. destruct H.
Case "appears_in x xs".
induction xs as [|x' xs']; simpl.
SCase "xs = []". inversion H.
SCase "xs = x' :: xs'".
inverts H; constructor.
SSCase "x <> x'".
apply IHxs', H1.
Case "appears_in x ys".
induction xs; simpl; [| constructor]; assumption.
Qed.
(** Now use [appears_in] to define a proposition [disjoint X l1 l2],
which should be provable exactly when [l1] and [l2] are
lists (with elements of type X) that have no elements in common. *)
Check all.
Definition disjoint {X} (l1 l2 : list X) := all _ (fun x => ~(appears_in x l2)) l1.
(** Next, use [appears_in] to define an inductive proposition
[no_repeats X l], which should be provable exactly when [l] is a
list (with elements of type [X]) where every member is different
from every other. For example, [no_repeats nat [1,2,3,4]] and
[no_repeats bool []] should be provable, while [no_repeats nat
[1,2,1]] and [no_repeats bool [true,true]] should not be. *)
Inductive no_repeats {X} : list X -> Prop :=
| nr_nil : no_repeats []
| nr_cons : forall x l, ~(appears_in x l) -> no_repeats l -> no_repeats (x :: l).
(** Finally, state and prove one or more interesting theorems relating
[disjoint], [no_repeats] and [++] (list append). *)
Lemma disjoint_distr :
forall X x (l1 l2 : list X),
disjoint (x :: l1) l2 -> disjoint l1 l2.
Proof.
unfold disjoint. introv H. inverts H. assumption.
Qed.
Lemma foo : forall X x (l1 l2 : list X), appears_in x (l1 ++ l2) -> no_repeats (x :: l1) -> appears_in x l2.
Proof.
introv Happ Hnr.
induction l1; simpl in Happ.
assumption.
apply IHl1; clear IHl1.
Case "1".
inverts Happ.
SCase "1".
inverts Hnr. apply ex_falso_quodlibet, H1. constructor.
SCase "2".
assumption.
Case "2".
inverts Hnr. constructor.
SCase "1".
unfold not in *. intro H. apply H1. constructor. assumption.
SCase "2". inverts H2. assumption.
Qed.
(*
inverts Happ as Happ.
Case "1".
destruct l1 as [|x' l1'].
SCase "l1 = []".
simpl in Happ. subst. constructor.
SCase "l1 = x' :: l1'".
simpl in Happ. inverts Happ. inverts Hnr.
apply ex_falso_quodlibet.
apply H1. constructor.
Case "2".
destruct l1 as [|x' l1'].
SCase "l1 = []".
simpl in H0. subst. constructor. assumption.
SCase "l1 = x' :: l1'".
simpl in H0. inverts H0.*)
Theorem no_r_distr :
forall X (l1 l2 : list X), disjoint l1 l2 -> no_repeats l1 -> no_repeats l2 ->
no_repeats (l1 ++ l2).
Proof.
introv disj nr_l1 nr_l2.
induction l1; simpl. assumption.
constructor.
Case "1st hp".
inverts disj.
intro H. apply foo in H. 2: apply nr_l1. apply H1 in H. assumption.
(* inversion H.
unfold not in H1. *)
Case "2nd hp".
apply IHl1.
apply disjoint_distr in disj. apply disj.
inverts nr_l1. assumption.
Qed.
(** [] *)
(* ######################################################### *)
(** ** Digression: More Facts about [<=] and [<] *)
(** Let's pause briefly to record several facts about the [<=]
and [<] relations that we are going to need later in the
course. The proofs make good practice exercises. *)
Print le.
(* Inductive le (n : nat) : nat -> Prop := *)
(* le_n : n <= n | le_S : forall m : nat, n <= m -> n <= S m *)
(** **** Exercise: 2 stars, optional (le_exercises) *)
Theorem O_le_n : forall n,
0 <= n.
Proof.
intros.
induction n; constructor. assumption.
Qed.
Check le_ind.
(* le_ind *)
(* : forall (n : nat) (P : nat -> Prop), *)
(* P n -> *)
(* (forall m : nat, n <= m -> P m -> P (S m)) -> *)
(* forall n0 : nat, n <= n0 -> P n0 *)
Theorem n_le_m__Sn_le_Sm : forall n m,
n <= m -> S n <= S m.
Proof.
introv H. induction H as [|m' H].
constructor.
constructor. assumption.
Restart.
intro n. apply le_ind.
constructor.
intros. constructor. assumption.
(*
generalize dependent n.
induction m as [|m']. intros. inversion H. constructor.
intros.
*)
(*
generalize dependent m.
induction n as [|n'].
induction m. constructor. constructor. apply IHm. apply O_le_n.
induction m as [|m']; introv H. inversion H.
constructor.
apply IHm'.
*)
Qed.
Theorem Sn_le_Sm__n_le_m : forall n m,
S n <= S m -> n <= m.
Proof.
intros n m. generalize dependent n. induction m.
introv H. inversion H.
constructor.
inversion H1.
introv H. inverts H.
constructor.
inverts H1.
repeat constructor.
constructor. apply IHm. constructor. assumption.
Qed.
Theorem le_plus_l : forall a b,
a <= a + b.
Proof.
induction a as [|a'].
apply O_le_n.
simpl.
introv.
Restart.
induction b as [|b'].
rewrite plus_0_r. constructor.
rewrite <- plus_n_Sm. constructor.
assumption.
Qed.
Theorem plus_lt : forall n1 n2 m,
n1 + n2 < m ->
n1 < m /\ n2 < m.
Proof.
split.
Case "n1 < m".
unfold lt in *.
induction m as [|m'].
SCase "m = 0". inversion H.
SCase "m = S m'".
inverts H.
SSCase "1".
clear IHm'.
induction n2 as [|n2'].
SSSCase "n2 = 0".
rewrite plus_0_r. constructor.
SSSCase "n2 = S n2'".
rewrite <- plus_n_Sm. constructor. apply IHn2'.
SSCase "2".
constructor. apply IHm', H1.
Case "n2 < m".
unfold lt in *.
induction m as [|m'].
SCase "m = 0". inversion H.
SCase "m = S m'".
inverts H.
SSCase "1".
clear IHm'.
induction n1 as [|n1']; simpl; constructor; assumption.
SSCase "2".
constructor. apply IHm'. assumption. Qed.
Theorem lt_S : forall n m,
n < m ->
n < S m.
Proof.
unfold lt. constructor. assumption. Qed.
Theorem ble_nat_true : forall n m,
ble_nat n m = true -> n <= m.
Proof.
induction n.
intros. apply O_le_n.
intros. destruct m.
inversion H.
simpl in H.
apply n_le_m__Sn_le_Sm. apply IHn. assumption. Qed.
Theorem ble_nat_n_Sn_false : forall n m,
ble_nat n (S m) = false ->
ble_nat n m = false.
Proof.
induction n as [|n']; introv H.
Case "n = 0".
inversion H.
Case "n = S n'".
inverts H. rewrite H1.
destruct m; simpl. reflexivity.
apply IHn'. assumption.
Qed.
SearchAbout ble_nat.
(* test_ble_nat1: ble_nat 2 2 = true *)
(* test_ble_nat2: ble_nat 2 4 = true *)
(* test_ble_nat3: ble_nat 4 2 = false *)
(* ble_nat_refl: forall n : nat, true = ble_nat n n *)
(* plus_ble_compat_l: *)
(* forall n m p : nat, ble_nat n m = true -> ble_nat (p + n) (p + m) = true *)
(* NatList.count_member_nonzero: *)
(* forall s : NatList.bag, *)
(* ble_nat 1 (NatList.count 1 (NatList.cons 1 s)) = true *)
(* NatList.ble_n_Sn: forall n : nat, ble_nat n (S n) = true *)
(* NatList.remove_decreases_count: *)
(* forall s : NatList.bag, *)
(* ble_nat (NatList.count 0 (NatList.remove_one 0 s)) (NatList.count 0 s) = *)
(* true *)
(* ble_nat_n_Sn_false: *)
(* forall n m : nat, ble_nat n (S m) = false -> ble_nat n m = false *)
(* ble_nat_true: forall n m : nat, ble_nat n m = true -> n <= m *)
SearchAbout le.
(* ble_nat_true: forall n m : nat, ble_nat n m = true -> n <= m *)
(* le_plus_l: forall a b : nat, a <= a + b *)
(* Sn_le_Sm__n_le_m: forall n m : nat, S n <= S m -> n <= m *)
(* n_le_m__Sn_le_Sm: forall n m : nat, n <= m -> S n <= S m *)
(* O_le_n: forall n : nat, 0 <= n *)
(* test_le3: ~ 2 <= 1 *)
(* test_le2: 3 <= 6 *)
(* test_le1: 3 <= 3 *)
(* le_ind: *)
(* forall (n : nat) (P : nat -> Prop), *)
(* P n -> *)
(* (forall m : nat, n <= m -> P m -> P (S m)) -> *)
(* forall n0 : nat, n <= n0 -> P n0 *)
(* le_n: forall n : nat, n <= n *)
(* le_S: forall n m : nat, n <= m -> n <= S m *)
Lemma le_Sn_m_remove_S : forall n m, S n <= m -> n <= m.
Proof.
introv H.
induction H. repeat constructor.
constructor; assumption.
Qed.
Theorem ble_nat_false : forall n m,
ble_nat n m = false -> ~(n <= m).
Proof.
(* Hint: Do the right induction! *)
unfold not.
introv H nm.
induction m as [|m'].
Case "m = 0".
inverts nm. inverts H.
Case "m = S m'".
destruct n as [|n']; inverts H.
SCase "n = S n'".
inverts nm.
rewrite <- ble_nat_refl in H1. inverts H1.
apply IHm', H0.
Restart.
unfold not.
introv H nm.
generalize dependent m.
induction n as [|n'].
Case "m = 0". intros. inverts H.
Case "m = S m'".
intros.
destruct m.
inverts nm.
inverts nm.
rewrite <- ble_nat_refl in H. inverts H.
inverts H as H.
(* inverts H1. apply ble_nat_n_Sn_false in H.
rewrite <- ble_nat_refl in H. inverts H. *)
apply IHn' with (m := m). assumption.
SearchAbout le.
clear H IHn'.
simpl.
apply le_Sn_m_remove_S, H1.
Qed.
(** [] *)
(** **** Exercise: 3 stars, recommended (nostutter) *)
(** Formulating inductive definitions of predicates is an important skill
you'll need in this course.
Try to solve this exercise without any help at all. If you do receive
assistance from anyone, please say so specifically in a comment.
We say that a list of numbers "stutters" if it repeats the same
number consecutively. The predicate "[nostutter mylist]" means
that [mylist] does not stutter. Formulate an inductive definition
for [nostutter]. (This is different from the [no_repeats]
predicate in the exercise above; the sequence [1,4,1] repeats but
does not stutter.)
*)
Inductive nostutter: list nat -> Prop :=
| ns_nil : nostutter nil
| ns_single : forall x, nostutter [x]
| ns_cons : forall x1 x2 l, x1 <> x2 -> nostutter (x2 :: l) -> nostutter (x1 :: x2 :: l).
(** Make sure each of these tests succeeds, but you are free
to change the proof if the given one doesn't work for you.
Your definition might be different from mine and still correct,
in which case the examples might need a different proof.
The suggested proofs for the examples (in comments) use a number
of tactics we haven't talked about, to try to make them robust
with respect to different possible ways of defining [nostutter].
You should be able to just uncomment and use them as-is, but if
you prefer you can also prove each example with more basic
tactics. *)
Example test_nostutter_1: nostutter [3,1,4,1,5,6].
Proof. repeat constructor; apply beq_false_not_eq; reflexivity. Qed.
(*
Proof. repeat constructor; apply beq_false_not_eq; auto. Qed.
*)
Example test_nostutter_2: nostutter [].
Proof. repeat constructor; apply beq_false_not_eq; auto. Qed.
(*
Proof. repeat constructor; apply beq_false_not_eq; auto. Qed.
*)
Example test_nostutter_3: nostutter [5].
Proof. repeat constructor; apply beq_false_not_eq; auto. Qed.
(*
Proof. repeat constructor; apply beq_false_not_eq; auto. Qed.
*)
Example test_nostutter_4: not (nostutter [3,1,1,4]).
Proof. intro.
repeat match goal with
h: nostutter _ |- _ => inversion h; clear h; subst
end.
contradiction H1; reflexivity. Qed.
(*
Proof. intro.
repeat match goal with
h: nostutter _ |- _ => inversion h; clear h; subst
end.
contradiction H1; auto. Qed.
*)
(** [] *)
(** **** Exercise: 4 stars, optional (pigeonhole principle) *)
(** The "pigeonhole principle" states a basic fact about counting:
if you distribute more than [n] items into [n] pigeonholes, some
pigeonhole must contain at least two items. As is often the case,
this apparently trivial fact about numbers requires non-trivial
machinery to prove, but we now have enough... *)
(** First a pair of useful lemmas... (we already proved this for lists
of naturals, but not for arbitrary lists.) *)
Lemma app_length : forall {X:Type} (l1 l2 : list X),
length (l1 ++ l2) = length l1 + length l2.
Proof.
induction l1; simpl; try reflexivity.
intros.
rewrite IHl1. reflexivity.
Qed.
Lemma appears_in_app_split : forall {X:Type} (x:X) (l:list X),
appears_in x l ->
exists l1, exists l2, l = l1 ++ (x::l2).
Proof.
intros.
induction l; inverts H.
exists (@nil X). exists l. reflexivity.
apply IHl in H1. clear IHl.
destruct H1 as [l1' [l2' H2]].
subst.
exists (x0 :: l1'). exists l2'.
reflexivity.
Qed.
(** Now define a predicate [repeats] (analogous to [no_repeats] in the
exercise above), such that [repeats X l] asserts that [l] contains
at least one repeated element (of type [X]). *)
Inductive repeats {X:Type} : list X -> Prop :=
| rp_base : forall x l, appears_in x l -> repeats (x :: l)
| rp_cons : forall x l, repeats l -> repeats (x :: l).
Lemma pigeonhole_principle_hard: forall {X:Type} (l1 l2:list X),
excluded_middle ->
(forall x, appears_in x l1 -> appears_in x l2) ->
length l2 = length l1 -> ~ repeats l1 ->
(forall x, appears_in x l2 -> appears_in x l1).
Proof.
intros X l1 l2 excl.
intros.
gen l1 l2.
induction l1.
Case "l1 = []".
intros.
simpl in H0.
destruct l2; try assumption.
inverts H0.
Case "l1 = x0 :: l1".
intros.
assert (Hexcl := excl (x = x0)).
destruct Hexcl.
SCase "x = x0".
subst. constructor.
SCase "x <> x0".
constructor.
Admitted.
(** Now here's a way to formalize the pigeonhole principle. List [l2]
represents a list of pigeonhole labels, and list [l1] represents an
assignment of items to labels: if there are more items than labels,
at least two items must have the same label. You will almost
certainly need to use the [excluded_middle] hypothesis. *)
Theorem pigeonhole_principle: forall {X:Type} (l1 l2:list X),
excluded_middle ->
(forall x, appears_in x l1 -> appears_in x l2) ->
length l2 < length l1 ->
repeats l1.
Proof.
(*
intros X l1 l2.
gen l1.
induction l2.
Case "l2 = []".
intros.
destruct l1.
inverts H1.
assert (Habs := H0 x).
apply ex_falso_quodlibet.
assert (Happ : appears_in x (x :: l1)). constructor.
apply Habs in Happ.
inverts Happ.
Case "l2 = x :: l2".
intro l1.
intro Hexcl.
intro Hcontained.
intro Hlen.
apply
apply IHl2 in Hexcl.
*)
intros X l1. induction l1; simpl.
Case "l1 = []".
introv H0 H1 H2. inversion H2.
Case "l1 = x :: l1".
introv excl H1 H2.
inverts H2.
SCase "length l2 = length l1".
assert (Hcases := excl (repeats l1)).
inverts Hcases.
SSCase "repeats l1".
apply rp_cons. assumption.
SSCase "~ (repeats l1)".
apply rp_base.
assert (appears_in x l2). apply H1. constructor.
SSCase "~ (repeats l1)".
apply (pigeonhole_principle_hard l1 l2); try assumption.
intros.
apply H1.
constructor. assumption.
SCase "length l2 < length l1".
apply rp_cons.
apply IHl1 with (l2 := l2).
assumption.
intros x0 app.
apply H1.
constructor.
assumption.
assumption.
(*
Check (IHl1 _ excl _ H0).
Check H1 x.
assert (Hcases := excl (repeats (x :: l1))).
inverts Hcases; try assumption.
(* unfold not in *.
apply ex_falso_quodlibet. *)
assert (Happ : appears_in x (x :: l1)). constructor.
apply (H1 x) in Happ.
assert (Hlemma: (forall x : X, appears_in x l1 -> appears_in x l2)).
introv Happears.
apply H1.
constructor. assumption.
assert (Hcases := excl (x = x0)).
inverts Hcases.
assumption.
Print appears_in.
(* Inductive appears_in (X : Type) (a : X) : list X -> Prop := *)
(* ai_here : forall l : list X, appears_in a (a :: l) *)
(* | ai_later : forall (b : X) (l : list X), *)
(* appears_in a l -> appears_in a (b :: l) *)
(* For appears_in: Argument X is implicit and maximally inserted *)
(* For ai_here: Argument X is implicit and maximally inserted *)
(* For ai_later: Argument X is implicit and maximally inserted *)
(* For appears_in: Argument scopes are [type_scope _ _] *)
(* For ai_here: Argument scopes are [type_scope _ _] *)
(* For ai_later: Argument scopes are [type_scope _ _ _ _] *)
apply (ai_later x0 x l1) in Happears. apply H1, Happears.
induction l2.
inversion Happ. simpl in *. inversion H2.
apply Sn_le_Sm__n_le_m in H2.
apply IHl2.
(* introv x1inl1.
inverts x1inl1.
admit.
apply Hlemma. *)
admit.
rewrite <- H3.
constructor. constructor.
admit.
assert (Hcases2 := excl (x = x0)).
inverts Hcases2.
introv xInL1.
(* inverts H2.
SSCase "length l2 = length l1".
assert (Hlemma2: appears_in x l1).
Lemma Hlemma2: forall {X} (x : X) l1 l2, length l1 = length l2 ->
(forall x : X, appears_in x l1 -> appears_in x l2) -> appears_in x l2 ->
appears_in x l1. Admitted.
admit.
constructor. apply Hlemma2.
SSCase "length l2 < length l1".
apply rp_cons. apply IHl1 with (l2 := l2); assumption. *)
*)
Qed.
(** [] *)
(* ##################################################### *)
(** * Optional Material *)
(* ################################################### *)
(** ** Induction Principles for [/\] and [\/] *)
(** The induction principles for conjunction and disjunction are a
good illustration of Coq's way of generating simplified induction
principles for [Inductive]ly defined propositions, which we
discussed in the last chapter. You try first: *)
(** **** Exercise: 1 star (and_ind_principle) *)
(** See if you can predict the induction principle for conjunction. *)
(* Check and_ind. *)
(** [] *)
(** **** Exercise: 1 star (or_ind_principle) *)
(** See if you can predict the induction principle for disjunction. *)
(* Check or_ind. *)
(** [] *)
Check and_ind.
(** From the inductive definition of the proposition [and P Q]
[[
Inductive and (P Q : Prop) : Prop :=
conj : P -> Q -> (and P Q).
]]
we might expect Coq to generate this induction principle
[[
and_ind_max :
forall (P Q : Prop) (P0 : P /\ Q -> Prop),
(forall (a : P) (b : Q), P0 (conj P Q a b)) ->
forall a : P /\ Q, P0 a
]]
but actually it generates this simpler and more useful one:
[[
and_ind :
forall P Q P0 : Prop,
(P -> Q -> P0) ->
P /\ Q -> P0
]]
In the same way, when given the inductive definition of [or P Q]
[[
Inductive or (P Q : Prop) : Prop :=
| or_introl : P -> or P Q
| or_intror : Q -> or P Q.
]]
instead of the "maximal induction principle"
[[
or_ind_max :
forall (P Q : Prop) (P0 : P \/ Q -> Prop),
(forall a : P, P0 (or_introl P Q a)) ->
(forall b : Q, P0 (or_intror P Q b)) ->
forall o : P \/ Q, P0 o
]]
what Coq actually generates is this:
[[
or_ind :
forall P Q P0 : Prop,
(P -> P0) ->
(Q -> P0) ->
P \/ Q -> P0
]]
*)
(* ######################################################### *)
(** ** Explicit Proof Objects for Induction *)
(** Although tactic-based proofs are normally much easier to
work with, the ability to write a proof term directly is sometimes
very handy, particularly when we want Coq to do something slightly
non-standard. *)
(** Recall the induction principle on naturals that Coq generates for
us automatically from the Inductive declation for [nat]. *)
(* Check nat_ind. *)
(* ===>
nat_ind : forall P : nat -> Prop,
P 0%nat ->
(forall n : nat, P n -> P (S n)) ->
forall n : nat, P n *)
(** There's nothing magic about this induction lemma: it's just
another Coq lemma that requires a proof. Coq generates the proof
automatically too... *)
Print nat_ind. Print nat_rect.
(* ===> (after some manual inlining)
nat_ind =
fun (P : nat -> Type)
(f : P 0%nat)
(f0 : forall n : nat, P n -> P (S n)) =>
fix F (n : nat) : P n :=
match n as n0 return (P n0) with
| 0%nat => f
| S n0 => f0 n0 (F n0)
end.
*)
(** We can read this as follows:
Suppose we have evidence [f] that [P] holds on 0, and
evidence [f0] that [forall n:nat, P n -> P (S n)].
Then we can prove that [P] holds of an arbitrary nat [n] via
a recursive function [F] (here defined using the expression
form [Fix] rather than by a top-level [Fixpoint]
declaration). [F] pattern matches on [n]:
- If it finds 0, [F] uses [f] to show that [P n] holds.
- If it finds [S n0], [F] applies itself recursively on [n0]
to obtain evidence that [P n0] holds; then it applies [f0]
on that evidence to show that [P (S n)] holds.
[F] is just an ordinary recursive function that happens to
operate on evidence in [Prop] rather than on terms in [Set].
Aside to those interested in functional programming: You may
notice that the [match] in [F] requires an annotation [as n0
return (P n0)] to help Coq's typechecker realize that the two arms
of the [match] actually return the same type (namely [P n]). This
is essentially like matching over a GADT (generalized algebraic
datatype) in Haskell. In fact, [F] has a _dependent_ type: its
result type depends on its argument; GADT's can be used to
describe simple dependent types like this.
We can adapt this approach to proving [nat_ind] to help prove
_non-standard_ induction principles too. Recall our desire to
prove that
[forall n : nat, even n -> ev n].
Attempts to do this by standard induction on [n] fail, because the
induction principle only lets us proceed when we can prove that
[even n -> even (S n)] -- which is of course never provable. What
we did earlier in this chapter was a bit of a hack:
[Theorem even_ev : forall n : nat,
(even n -> ev n) /\ (even (S n) -> ev (S n))].
We can make a much better proof by defining and proving a
non-standard induction principle that goes "by twos":
*)
Definition nat_ind2 :
forall (P : nat -> Prop),
P 0 ->
P 1 ->
(forall n : nat, P n -> P (S(S n))) ->
forall n : nat , P n :=
fun P => fun P0 => fun P1 => fun PSS =>
fix f (n:nat) := match n return P n with
0 => P0
| 1 => P1
| S (S n') => PSS n' (f n')
end.
(** Once you get the hang of it, it is entirely straightforward to
give an explicit proof term for induction principles like this.
Proving this as a lemma using tactics is much less intuitive (try
it!).
The [induction ... using] tactic gives a convenient way to
specify a non-standard induction principle like this. *)
Lemma even_ev' : forall n, even n -> ev n.
Proof.
intros.
induction n as [ | |n'] using nat_ind2.
Case "even 0".
apply ev_0.
Case "even 1".
inversion H.
Case "even (S(S n'))".
apply ev_SS.
apply IHn'. unfold even. unfold even in H. simpl in H. apply H.
Qed.
(* ######################################################### *)
(** ** The Coq Trusted Computing Base *)
(** One issue that arises with any automated proof assistant is "why
trust it?": what if there is a bug in the implementation that
renders all its reasoning suspect?
While it is impossible to allay such concerns completely, the fact
that Coq is based on the Curry-Howard Correspondence gives it a
strong foundation. Because propositions are just types and proofs
are just terms, checking that an alleged proof of a proposition is
valid just amounts to _type-checking_ the term. Type checkers are
relatively small and straightforward programs, so the "trusted
computing base" for Coq -- the part of the code that we have to
believe is operating correctly -- is small too.
What must a typechecker do? Its primary job is to make sure that
in each function application the expected and actual argument
types match, that the arms of a [match] expression are constructor
patterns belonging to the inductive type being matched over and
all arms of the [match] return the same type, and so on.
There are a few additional wrinkles:
- Since Coq types can themselves be expressions, the checker must
normalize these (by using the conversion rules) before
comparing them.
- The checker must make sure that [match] expressions are
_exhaustive_. That is, there must be an arm for every possible
constructor. To see why, consider the following alleged proof
object:
[[
Definition or_bogus : forall P Q, P \/ Q -> P :=
fun (P Q : Prop) (A : P \/ Q) =>
match A with
| or_introl H => H
end.
]]
All the types here match correctly, but the [match] only
considers one of the possible constructors for [or]. Coq's
exhaustiveness check will reject this definition.
- The checker must make sure that each [fix] expression
terminates. It does this using a syntactic check to make sure
that each recursive call is on a subexpression of the original
argument. To see why this is essential, consider this alleged
proof:
[[
Definition nat_false : forall (n:nat), False :=
fix f (n:nat) : False := f n.
]]
Again, this is perfectly well-typed, but (fortunately) Coq will
reject it. *)
(** Note that the soundness of Coq depends only on the correctness of
this typechecking engine, not on the tactic machinery. If there
is a bug in a tactic implementation (and this certainly does
happen!), that tactic might construct an invalid proof term. But
when you type [Qed], Coq checks the term for validity from
scratch. Only lemmas whose proofs pass the type-checker can be
used in further proof developments. *)
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:02:05 12/03/2016
// Design Name:
// Module Name: animation
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module animationV(clk, rst, height, ram_address, ram_data, mode, on_off);
input clk, rst, mode, on_off; //0 is home mode; 1 is party mode
input [8:0] ram_address;
output reg [47:0] ram_data;
reg [23:0] top, bottom;
input[3:0] height;
reg [4:0] inner_height;
reg [23:0] color;
reg addsub;
//parameter height = 9;
initial begin
top<=0;
bottom<=0;
ram_data <=0;
inner_height<=0;
color<=0;
addsub<=0;
end
//Top half of panel is controlled by last 24 bits of ram_data
always @ (posedge clk) begin
if ( mode == 1'b1) begin
if (ram_address == 0) begin
color<= color+1'b1;
inner_height<={0,height};
end
bottom <= {24{1'b0}};
top <= {24{1'b0}};
if (ram_address > 512 - 1 - $unsigned(inner_height)* 32 ) begin
top <= color;
//bottom <= {24{1'b0}};
end
if (ram_address < $unsigned(inner_height) * 32) begin
//top <= {24{1'b0}};
bottom <= color;
end
ram_data <= {bottom, top};
end
else begin
if (on_off == 1'b1) begin
ram_data <= {8'd179, 8'd255, 8'd255, 8'd179, 8'd255, 8'd255};
end
else begin
ram_data <= 48'b0;
end
end
end
endmodule
|
//
// Delay a signal by one clock...
//
module dly_signal (clk, indata, outdata);
parameter WIDTH = 1;
input clk;
input [WIDTH-1:0] indata;
output [WIDTH-1:0] outdata;
reg [WIDTH-1:0] outdata, next_outdata;
always @(posedge clk) outdata = next_outdata;
always @*
begin
#1;
next_outdata = indata;
end
endmodule
//
// Delay & Synchronizer pipelines...
//
module pipeline_stall (clk, reset, datain, dataout);
parameter WIDTH = 1;
parameter DELAY = 1;
input clk, reset;
input [WIDTH-1:0] datain;
output [WIDTH-1:0] dataout;
reg [(WIDTH*DELAY)-1:0] dly_datain, next_dly_datain;
assign dataout = dly_datain[(WIDTH*DELAY)-1 : WIDTH*(DELAY-1)];
initial dly_datain = 0;
always @ (posedge clk or posedge reset)
begin
if (reset)
dly_datain = 0;
else dly_datain = next_dly_datain;
end
always @*
begin
#1;
next_dly_datain = {dly_datain, datain};
end
endmodule
//
// Two back to back flop's. A full synchronizer (which XISE
// will convert into a nice shift register using a single LUT)
// to sample asynchronous signals safely.
//
module full_synchronizer (clk, reset, datain, dataout);
parameter WIDTH = 1;
input clk, reset;
input [WIDTH-1:0] datain;
output [WIDTH-1:0] dataout;
pipeline_stall #(WIDTH,2) sync (clk, reset, datain, dataout);
endmodule
//
// Create a stretched synchronized reset pulse...
//
module reset_sync (clk, hardreset, reset);
input clk, hardreset;
output reset;
reg [3:0] reset_reg, next_reset_reg;
assign reset = reset_reg[3];
initial reset_reg = 4'hF;
always @ (posedge clk or posedge hardreset)
begin
if (hardreset)
reset_reg = 4'hF;
else reset_reg = next_reset_reg;
end
always @*
begin
next_reset_reg = {reset_reg,1'b0};
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MAJ3_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__MAJ3_PP_BLACKBOX_V
/**
* maj3: 3-input majority vote.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__maj3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__MAJ3_PP_BLACKBOX_V
|
/****************************************************************************
* Copyright (c) 2009 by Focus Robotics. All rights reserved.
*
* This program is an unpublished work fully protected by the United States
* copyright laws and is considered a trade secret belonging to the copyright
* holder. No part of this design may be reproduced stored in a retrieval
* system, or transmitted, in any form or by any means, electronic,
* mechanical, photocopying, recording, or otherwise, without prior written
* permission of Focus Robotics, Inc.
*
* Proprietary and Confidential
*
* Created By : Andrew Worcester
* Creation_Date: Tue Mar 10 2009
*
* Brief Description:
*
* Functionality:
*
* Issues:
*
* Limitations:
*
* Testing:
*
* Synthesis:
*
******************************************************************************/
module fric_switch_nosym_8port
(
clk,
rst,
fric_in0,
fric_out0,
fric_in1,
fric_out1,
fric_in2,
fric_out2,
fric_in3,
fric_out3,
fric_in4,
fric_out4,
fric_in5,
fric_out5,
fric_in6,
fric_out6,
fric_in7,
fric_out7
);
// In/Out declarations
input clk;
input rst;
input [7:0] fric_in0;
output [7:0] fric_out0;
input [7:0] fric_in1;
output [7:0] fric_out1;
input [7:0] fric_in2;
output [7:0] fric_out2;
input [7:0] fric_in3;
output [7:0] fric_out3;
input [7:0] fric_in4;
output [7:0] fric_out4;
input [7:0] fric_in5;
output [7:0] fric_out5;
input [7:0] fric_in6;
output [7:0] fric_out6;
input [7:0] fric_in7;
output [7:0] fric_out7;
// Parameters
parameter [3:0] mp_idle = 4'h0,
mp_req_adr = 4'h1,
mp_wdat0 = 4'h2,
mp_wdat1 = 4'h3,
mp_wack = 4'h4,
mp_rep_adr = 4'h5,
mp_rdat0 = 4'h6,
mp_rdat1 = 4'h7,
mp_done = 4'hf;
// Regs and Wires
reg [3:0] mp_state, next_mp_state;
reg [7:0] fric_out0;
reg [7:0] fric_inr0;
reg [7:0] pdat;
reg [3:0] psel, type, psel_reg;
reg capt_psel;
reg chng_port_out;
reg chng_port_in;
reg [7:0] prep;
reg [7:0] fric_out1;
reg [7:0] fric_out2;
reg [7:0] fric_out3;
reg [7:0] fric_out4;
reg [7:0] fric_out5;
reg [7:0] fric_out6;
reg [7:0] fric_out7;
reg [7:0] fric_inr1;
reg [7:0] fric_inr2;
reg [7:0] fric_inr3;
reg [7:0] fric_inr4;
reg [7:0] fric_inr5;
reg [7:0] fric_inr6;
reg [7:0] fric_inr7;
// RTL or Instances
/****************************************************************************
* Subblock: Master Port (port0)
*
* This is the only port which will be receiving requests from it's client.
* Other ports will forward those requests to their clients and get and ack
* back from them.
*
* The FSM basically works like this: monitor fric_in0 upper 4 bits until
* they are non-zero. Select the output port from the lower 4 bits of that
* word. Overwrite the lower 4 bits of that word with 0's and send that to
* the output port. Send the next three words to that same output port and
* wait for the ack. So input port had to be selected the same as the output
* port. Forward the ack to fric_out0, overwriting the lower 4 bits of the
* first word with the selected port. Start again.
*
* Inputs: fric_in0, preply
*
* Outputs: psel, pdat
*
* Todo/Fixme:
*
*/
always @ (/*AS*/fric_inr0 or mp_state or prep or type)
begin
// FSM default outputs
next_mp_state = mp_state;
capt_psel = 0;
chng_port_out = 0;
chng_port_in = 0;
case(mp_state)
mp_idle: // wait for transaction to start then capture and send type and port
if(|fric_inr0[7:4]!=0) begin
capt_psel = 1'b1;
chng_port_out = 1'b1;
next_mp_state = mp_req_adr;
end
mp_req_adr: // send addr, go to wait ack if read, go to dat if write
if(type==4'b0010)
next_mp_state = mp_wdat0;
else if(type==4'b0011)
next_mp_state = mp_wack;
else
$display("Illegal type captured in fric switch nosym\n");
mp_wdat0:
next_mp_state = mp_wdat1;
mp_wdat1:
next_mp_state = mp_wack;
mp_wack:
// wait for ack to start and then send type, port
// change port value back from this port to slave port
// FIXME: should probably re-capture type instead of relying on
// the ack to be correct based on the request.
// FIXME: with quick turnaround, is it possible for the ack to
// start before we get to this state?!?! probably not...
if(|prep[7:0]!=0) begin
chng_port_in = 1'b1;
next_mp_state = mp_rep_adr;
end
mp_rep_adr:
// send reply addr, got to idle if this is a write ack or continue
// for a read ack
if(type==4'b0010) // write ack only 2 cycles
next_mp_state = mp_idle;
else
next_mp_state = mp_rdat0;
mp_rdat0:
next_mp_state = mp_rdat1;
mp_rdat1:
next_mp_state = mp_idle;
default: next_mp_state = mp_idle;
endcase // case(mp_state)
end // always @ (...
always @ (posedge clk)
begin
if(rst==1'b1)
begin
mp_state <= mp_idle;
fric_inr0 <= 0;
psel_reg <= 0;
type <= 0;
fric_out0 <= 0;
end
else
begin
mp_state <= next_mp_state;
fric_inr0 <= fric_in0;
if(capt_psel==1'b1) begin
psel_reg <= fric_inr0[3:0];
type <= fric_inr0[7:4];
end
if(chng_port_in==1'b1)
fric_out0 <= {prep[7:4], psel};
else
fric_out0 <= prep;
end
end // always @ (posedge clk)
always @ (/*AS*/capt_psel or chng_port_out or fric_inr0 or psel_reg)
begin
if(chng_port_out==1'b1)
pdat <= {fric_inr0[7:4], 4'h0};
else
pdat <= fric_inr0;
if(capt_psel==1'b1)
psel = fric_inr0[3:0];
else
psel = psel_reg;
end
/****************************************************************************
* Subblock: Slave Ports (ports 1-7)
*
* Note that the various slave fric_out ports aren't driven to zero
* explicitly so each transaction must go to zeroes before another one starts
*
* Inputs:
* psel, pdat: from master port
* fric_in1 - fric_in7
*
* Outputs: prep: from reply port back to master
* fric_out1 - fric_out7
*
* Todo/Fixme:
*
*/
always @ (posedge clk)
begin
if(rst==1'b1)
begin
prep <= 0;
fric_inr1 <= 0;
fric_inr2 <= 0;
fric_inr3 <= 0;
fric_inr4 <= 0;
fric_inr5 <= 0;
fric_inr6 <= 0;
fric_inr7 <= 0;
fric_out1 <= 0;
fric_out2 <= 0;
fric_out3 <= 0;
fric_out4 <= 0;
fric_out5 <= 0;
fric_out6 <= 0;
fric_out7 <= 0;
end
else
begin
fric_inr1 <= fric_in1;
fric_inr2 <= fric_in2;
fric_inr3 <= fric_in3;
fric_inr4 <= fric_in4;
fric_inr5 <= fric_in5;
fric_inr6 <= fric_in6;
fric_inr7 <= fric_in7;
case(psel)
3'b000: ;
3'b001: fric_out1 <= pdat;
3'b010: fric_out2 <= pdat;
3'b011: fric_out3 <= pdat;
3'b100: fric_out4 <= pdat;
3'b101: fric_out5 <= pdat;
3'b110: fric_out6 <= pdat;
3'b111: fric_out7 <= pdat;
endcase // case(psel)
end // else: !if(rst==1'b1)
end // always @ (posedge clk)
always @ (/*AS*/fric_inr1 or fric_inr2 or fric_inr3 or fric_inr4 or fric_inr5
or fric_inr6 or fric_inr7 or psel)
begin
case(psel)
3'b000: prep = 0;
3'b001: prep = fric_inr1;
3'b010: prep = fric_inr2;
3'b011: prep = fric_inr3;
3'b100: prep = fric_inr4;
3'b101: prep = fric_inr5;
3'b110: prep = fric_inr6;
3'b111: prep = fric_inr7;
endcase // case(psel)
end // always @ (...
/****************************************************************************
* Subblock
*
* Inputs:
*
* Outputs:
*
* Todo/Fixme:
*
*/
endmodule // fric_switch_8port
|
/*
Copyright (c) 2015-2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* PTP clock module
*/
module ptp_clock #
(
parameter PERIOD_NS_WIDTH = 4,
parameter OFFSET_NS_WIDTH = 4,
parameter DRIFT_NS_WIDTH = 4,
parameter FNS_WIDTH = 16,
parameter PERIOD_NS = 4'h6,
parameter PERIOD_FNS = 16'h6666,
parameter DRIFT_ENABLE = 1,
parameter DRIFT_NS = 4'h0,
parameter DRIFT_FNS = 16'h0002,
parameter DRIFT_RATE = 16'h0005,
parameter PIPELINE_OUTPUT = 0
)
(
input wire clk,
input wire rst,
/*
* Timestamp inputs for synchronization
*/
input wire [95:0] input_ts_96,
input wire input_ts_96_valid,
input wire [63:0] input_ts_64,
input wire input_ts_64_valid,
/*
* Period adjustment
*/
input wire [PERIOD_NS_WIDTH-1:0] input_period_ns,
input wire [FNS_WIDTH-1:0] input_period_fns,
input wire input_period_valid,
/*
* Offset adjustment
*/
input wire [OFFSET_NS_WIDTH-1:0] input_adj_ns,
input wire [FNS_WIDTH-1:0] input_adj_fns,
input wire [15:0] input_adj_count,
input wire input_adj_valid,
output wire input_adj_active,
/*
* Drift adjustment
*/
input wire [DRIFT_NS_WIDTH-1:0] input_drift_ns,
input wire [FNS_WIDTH-1:0] input_drift_fns,
input wire [15:0] input_drift_rate,
input wire input_drift_valid,
/*
* Timestamp outputs
*/
output wire [95:0] output_ts_96,
output wire [63:0] output_ts_64,
output wire output_ts_step,
/*
* PPS output
*/
output wire output_pps
);
parameter INC_NS_WIDTH = $clog2(2**PERIOD_NS_WIDTH + 2**OFFSET_NS_WIDTH + 2**DRIFT_NS_WIDTH);
reg [PERIOD_NS_WIDTH-1:0] period_ns_reg = PERIOD_NS;
reg [FNS_WIDTH-1:0] period_fns_reg = PERIOD_FNS;
reg [OFFSET_NS_WIDTH-1:0] adj_ns_reg = 0;
reg [FNS_WIDTH-1:0] adj_fns_reg = 0;
reg [15:0] adj_count_reg = 0;
reg adj_active_reg = 0;
reg [DRIFT_NS_WIDTH-1:0] drift_ns_reg = DRIFT_NS;
reg [FNS_WIDTH-1:0] drift_fns_reg = DRIFT_FNS;
reg [15:0] drift_rate_reg = DRIFT_RATE;
reg [INC_NS_WIDTH-1:0] ts_inc_ns_reg = 0;
reg [FNS_WIDTH-1:0] ts_inc_fns_reg = 0;
reg [47:0] ts_96_s_reg = 0;
reg [29:0] ts_96_ns_reg = 0;
reg [FNS_WIDTH-1:0] ts_96_fns_reg = 0;
reg [29:0] ts_96_ns_inc_reg = 0;
reg [FNS_WIDTH-1:0] ts_96_fns_inc_reg = 0;
reg [30:0] ts_96_ns_ovf_reg = 31'h7fffffff;
reg [FNS_WIDTH-1:0] ts_96_fns_ovf_reg = 16'hffff;
reg [47:0] ts_64_ns_reg = 0;
reg [FNS_WIDTH-1:0] ts_64_fns_reg = 0;
reg ts_step_reg = 1'b0;
reg [15:0] drift_cnt = 0;
reg [47:0] temp;
reg pps_reg = 0;
assign input_adj_active = adj_active_reg;
generate
if (PIPELINE_OUTPUT > 0) begin
// pipeline
(* shreg_extract = "no" *)
reg [95:0] output_ts_96_reg[0:PIPELINE_OUTPUT-1];
(* shreg_extract = "no" *)
reg [63:0] output_ts_64_reg[0:PIPELINE_OUTPUT-1];
(* shreg_extract = "no" *)
reg output_ts_step_reg[0:PIPELINE_OUTPUT-1];
(* shreg_extract = "no" *)
reg output_pps_reg[0:PIPELINE_OUTPUT-1];
assign output_ts_96 = output_ts_96_reg[PIPELINE_OUTPUT-1];
assign output_ts_64 = output_ts_64_reg[PIPELINE_OUTPUT-1];
assign output_ts_step = output_ts_step_reg[PIPELINE_OUTPUT-1];
assign output_pps = output_pps_reg[PIPELINE_OUTPUT-1];
integer i;
initial begin
for (i = 0; i < PIPELINE_OUTPUT; i = i + 1) begin
output_ts_96_reg[i] = 96'd0;
output_ts_64_reg[i] = 64'd0;
output_ts_step_reg[i] = 1'b0;
output_pps_reg[i] = 1'b0;
end
end
always @(posedge clk) begin
output_ts_96_reg[0][95:48] <= ts_96_s_reg;
output_ts_96_reg[0][47:46] <= 2'b00;
output_ts_96_reg[0][45:16] <= ts_96_ns_reg;
output_ts_96_reg[0][15:0] <= {ts_96_fns_reg, 16'd0} >> FNS_WIDTH;
output_ts_64_reg[0][63:16] <= ts_64_ns_reg;
output_ts_64_reg[0][15:0] <= {ts_64_fns_reg, 16'd0} >> FNS_WIDTH;
output_ts_step_reg[0] <= ts_step_reg;
output_pps_reg[0] <= pps_reg;
for (i = 0; i < PIPELINE_OUTPUT-1; i = i + 1) begin
output_ts_96_reg[i+1] <= output_ts_96_reg[i];
output_ts_64_reg[i+1] <= output_ts_64_reg[i];
output_ts_step_reg[i+1] <= output_ts_step_reg[i];
output_pps_reg[i+1] <= output_pps_reg[i];
end
if (rst) begin
for (i = 0; i < PIPELINE_OUTPUT; i = i + 1) begin
output_ts_96_reg[i] = 96'd0;
output_ts_64_reg[i] = 64'd0;
output_ts_step_reg[i] = 1'b0;
output_pps_reg[i] = 1'b0;
end
end
end
end else begin
assign output_ts_96[95:48] = ts_96_s_reg;
assign output_ts_96[47:46] = 2'b00;
assign output_ts_96[45:16] = ts_96_ns_reg;
assign output_ts_96[15:0] = {ts_96_fns_reg, 16'd0} >> FNS_WIDTH;
assign output_ts_64[63:16] = ts_64_ns_reg;
assign output_ts_64[15:0] = {ts_64_fns_reg, 16'd0} >> FNS_WIDTH;
assign output_ts_step = ts_step_reg;
assign output_pps = pps_reg;
end
endgenerate
always @(posedge clk) begin
ts_step_reg <= 0;
// latch parameters
if (input_period_valid) begin
period_ns_reg <= input_period_ns;
period_fns_reg <= input_period_fns;
end
if (input_adj_valid) begin
adj_ns_reg <= input_adj_ns;
adj_fns_reg <= input_adj_fns;
adj_count_reg <= input_adj_count;
end
if (DRIFT_ENABLE && input_drift_valid) begin
drift_ns_reg <= input_drift_ns;
drift_fns_reg <= input_drift_fns;
drift_rate_reg <= input_drift_rate;
end
// timestamp increment calculation
{ts_inc_ns_reg, ts_inc_fns_reg} <= $signed({1'b0, period_ns_reg, period_fns_reg}) +
(adj_active_reg ? $signed({adj_ns_reg, adj_fns_reg}) : 0) +
((DRIFT_ENABLE && drift_cnt == 0) ? $signed({drift_ns_reg, drift_fns_reg}) : 0);
// offset adjust counter
if (adj_count_reg > 0) begin
adj_count_reg <= adj_count_reg - 1;
adj_active_reg <= 1;
ts_step_reg <= 1;
end else begin
adj_active_reg <= 0;
end
// drift counter
if (drift_cnt == 0) begin
drift_cnt <= drift_rate_reg-1;
end else begin
drift_cnt <= drift_cnt - 1;
end
// 96 bit timestamp
if (!ts_96_ns_ovf_reg[30]) begin
// if the overflow lookahead did not borrow, one second has elapsed
// increment seconds field, pre-compute both normal increment and overflow values
{ts_96_ns_inc_reg, ts_96_fns_inc_reg} <= {ts_96_ns_ovf_reg, ts_96_fns_ovf_reg} + {ts_inc_ns_reg, ts_inc_fns_reg};
{ts_96_ns_ovf_reg, ts_96_fns_ovf_reg} <= {ts_96_ns_ovf_reg, ts_96_fns_ovf_reg} + {ts_inc_ns_reg, ts_inc_fns_reg} - {31'd1_000_000_000, {FNS_WIDTH{1'b0}}};
{ts_96_ns_reg, ts_96_fns_reg} <= {ts_96_ns_ovf_reg, ts_96_fns_ovf_reg};
ts_96_s_reg <= ts_96_s_reg + 1;
end else begin
// no increment seconds field, pre-compute both normal increment and overflow values
{ts_96_ns_inc_reg, ts_96_fns_inc_reg} <= {ts_96_ns_inc_reg, ts_96_fns_inc_reg} + {ts_inc_ns_reg, ts_inc_fns_reg};
{ts_96_ns_ovf_reg, ts_96_fns_ovf_reg} <= {ts_96_ns_inc_reg, ts_96_fns_inc_reg} + {ts_inc_ns_reg, ts_inc_fns_reg} - {31'd1_000_000_000, {FNS_WIDTH{1'b0}}};
{ts_96_ns_reg, ts_96_fns_reg} <= {ts_96_ns_inc_reg, ts_96_fns_inc_reg};
ts_96_s_reg <= ts_96_s_reg;
end
if (input_ts_96_valid) begin
// load timestamp
ts_96_s_reg <= input_ts_96[95:48];
ts_96_ns_reg <= input_ts_96[45:16];
ts_96_ns_inc_reg <= input_ts_96[45:16];
ts_96_ns_ovf_reg <= 31'h7fffffff;
ts_96_fns_reg <= FNS_WIDTH > 16 ? input_ts_96[15:0] << (FNS_WIDTH-16) : input_ts_96[15:0] >> (16-FNS_WIDTH);
ts_96_fns_inc_reg <= FNS_WIDTH > 16 ? input_ts_96[15:0] << (FNS_WIDTH-16) : input_ts_96[15:0] >> (16-FNS_WIDTH);
ts_96_fns_ovf_reg <= {FNS_WIDTH{1'b1}};
ts_step_reg <= 1;
end
// 64 bit timestamp
{ts_64_ns_reg, ts_64_fns_reg} <= {ts_64_ns_reg, ts_64_fns_reg} + {ts_inc_ns_reg, ts_inc_fns_reg};
if (input_ts_64_valid) begin
// load timestamp
{ts_64_ns_reg, ts_64_fns_reg} <= input_ts_64;
ts_step_reg <= 1;
end
pps_reg <= !ts_96_ns_ovf_reg[30];
if (rst) begin
period_ns_reg <= PERIOD_NS;
period_fns_reg <= PERIOD_FNS;
adj_ns_reg <= 0;
adj_fns_reg <= 0;
adj_count_reg <= 0;
adj_active_reg <= 0;
drift_ns_reg <= DRIFT_NS;
drift_fns_reg <= DRIFT_FNS;
drift_rate_reg <= DRIFT_RATE;
ts_inc_ns_reg <= 0;
ts_inc_fns_reg <= 0;
ts_96_s_reg <= 0;
ts_96_ns_reg <= 0;
ts_96_fns_reg <= 0;
ts_96_ns_inc_reg <= 0;
ts_96_fns_inc_reg <= 0;
ts_96_ns_ovf_reg <= 31'h7fffffff;
ts_96_fns_ovf_reg <= {FNS_WIDTH{1'b1}};
ts_64_ns_reg <= 0;
ts_64_fns_reg <= 0;
ts_step_reg <= 0;
drift_cnt <= 0;
pps_reg <= 0;
end
end
endmodule
`resetall
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FA_LP_V
`define SKY130_FD_SC_LP__FA_LP_V
/**
* fa: Full adder.
*
* Verilog wrapper for fa with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__fa.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__fa_lp (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__fa_lp (
COUT,
SUM ,
A ,
B ,
CIN
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__FA_LP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DFSTP_1_V
`define SKY130_FD_SC_HDLL__DFSTP_1_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog wrapper for dfstp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__dfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__dfstp_1 (
Q ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__dfstp_1 (
Q ,
CLK ,
D ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DFSTP_1_V
|
module ADT7310P32LS16L (
(* intersynth_port="Reset_n_i" *)
input Reset_n_i,
(* intersynth_port="Clk_i" *)
input Clk_i,
(* intersynth_port="ReconfModuleIn_s", intersynth_conntype="Bit" *)
input Enable_i,
(* intersynth_port="ReconfModuleIRQs_s", intersynth_conntype="Bit" *)
output CpuIntr_o,
(* intersynth_port="Outputs_o", intersynth_conntype="Bit" *)
output ADT7310CS_n_o,
(* intersynth_port="SPI_DataOut", intersynth_conntype="Byte" *)
input[7:0] SPI_Data_i,
(* intersynth_port="SPI_Write", intersynth_conntype="Bit" *)
output SPI_Write_o,
(* intersynth_port="SPI_ReadNext", intersynth_conntype="Bit" *)
output SPI_ReadNext_o,
(* intersynth_port="SPI_DataIn", intersynth_conntype="Byte" *)
output[7:0] SPI_Data_o,
(* intersynth_port="SPI_FIFOFull", intersynth_conntype="Bit" *)
input SPI_FIFOFull_i,
(* intersynth_port="SPI_FIFOEmpty", intersynth_conntype="Bit" *)
input SPI_FIFOEmpty_i,
(* intersynth_port="SPI_Transmission", intersynth_conntype="Bit" *)
input SPI_Transmission_i,
(* intersynth_param="SPICounterPreset_i", intersynth_conntype="Word" *)
input[15:0] SPICounterPreset_i,
(* intersynth_param="Threshold_i", intersynth_conntype="Word" *)
input[15:0] Threshold_i,
(* intersynth_param="PeriodCounterPresetH_i", intersynth_conntype="Word" *)
input[15:0] PeriodCounterPresetH_i,
(* intersynth_param="PeriodCounterPresetL_i", intersynth_conntype="Word" *)
input[15:0] PeriodCounterPresetL_i,
(* intersynth_param="SensorValue_o", intersynth_conntype="Word" *)
output[15:0] SensorValue_o,
(* intersynth_port="SPI_CPOL", intersynth_conntype="Bit" *)
output SPI_CPOL_o,
(* intersynth_port="SPI_CPHA", intersynth_conntype="Bit" *)
output SPI_CPHA_o,
(* intersynth_port="SPI_LSBFE", intersynth_conntype="Bit" *)
output SPI_LSBFE_o
);
/* constant value for dynamic signal */
assign SPI_CPOL_o = 1'b1;
/* constant value for dynamic signal */
assign SPI_CPHA_o = 1'b1;
/* constant value for dynamic signal */
assign SPI_LSBFE_o = 1'b0;
(* keep *)
wire SPIFSM_Start_s;
(* keep *)
wire SPIFSM_Done_s;
(* keep *)
wire [7:0] SPIFSM_Byte0_s;
(* keep *)
wire [7:0] SPIFSM_Byte1_s;
SPIFSM #(
.SPPRWidth (4),
.SPRWidth (4),
.DataWidth (8)
) SPIFSM_1 (
.Reset_n_i (Reset_n_i),
.Clk_i (Clk_i),
// FSM control
.Start_i (SPIFSM_Start_s),
.Done_o (SPIFSM_Done_s),
.Byte0_o (SPIFSM_Byte0_s),
.Byte1_o (SPIFSM_Byte1_s),
// to/from SPI_Master
.SPI_Transmission_i (SPI_Transmission_i),
.SPI_Write_o (SPI_Write_o),
.SPI_ReadNext_o (SPI_ReadNext_o),
.SPI_Data_o (SPI_Data_o),
.SPI_Data_i (SPI_Data_i),
.SPI_FIFOFull_i (SPI_FIFOFull_i),
.SPI_FIFOEmpty_i (SPI_FIFOEmpty_i),
// to ADT7310
.ADT7310CS_n_o (ADT7310CS_n_o),
// parameters
.ParamCounterPreset_i(SPICounterPreset_i)
);
SensorFSM #(
.DataWidth (8)
) SensorFSM_1 (
.Reset_n_i (Reset_n_i),
.Clk_i (Clk_i),
.Enable_i (Enable_i),
.CpuIntr_o (CpuIntr_o),
.SensorValue_o (SensorValue_o),
.MeasureFSM_Start_o (SPIFSM_Start_s),
.MeasureFSM_Done_i (SPIFSM_Done_s),
.MeasureFSM_Byte0_i (SPIFSM_Byte0_s),
.MeasureFSM_Byte1_i (SPIFSM_Byte1_s),
// parameters
.ParamThreshold_i (Threshold_i),
.ParamCounterPreset_i({PeriodCounterPresetH_i, PeriodCounterPresetL_i})
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dram0_ddr0_rptr.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module dram0_ddr0_rptr( /*AUTOARG*/
// Outputs
io_dram_data_valid_buf, io_dram_ecc_in_buf, io_dram_data_in_buf,
dram_io_cas_l_buf, dram_io_channel_disabled_buf, dram_io_cke_buf,
dram_io_clk_enable_buf, dram_io_drive_data_buf,
dram_io_drive_enable_buf, dram_io_pad_clk_inv_buf,
dram_io_pad_enable_buf, dram_io_ras_l_buf, dram_io_write_en_l_buf,
dram_io_addr_buf, dram_io_bank_buf, dram_io_cs_l_buf,
dram_io_data_out_buf, dram_io_ptr_clk_inv_buf,
// Inputs
io_dram_data_valid, io_dram_ecc_in, io_dram_data_in,
dram_io_cas_l, dram_io_channel_disabled, dram_io_cke,
dram_io_clk_enable, dram_io_drive_data, dram_io_drive_enable,
dram_io_pad_clk_inv, dram_io_pad_enable, dram_io_ras_l,
dram_io_write_en_l, dram_io_addr, dram_io_bank, dram_io_cs_l,
dram_io_data_out, dram_io_ptr_clk_inv
);
/*OUTPUTS*/
output io_dram_data_valid_buf;
output [31:0] io_dram_ecc_in_buf;
output [255:0] io_dram_data_in_buf;
output dram_io_cas_l_buf;
output dram_io_channel_disabled_buf;
output dram_io_cke_buf;
output dram_io_clk_enable_buf;
output dram_io_drive_data_buf;
output dram_io_drive_enable_buf;
output dram_io_pad_clk_inv_buf;
output dram_io_pad_enable_buf;
output dram_io_ras_l_buf;
output dram_io_write_en_l_buf;
output [14:0] dram_io_addr_buf;
output [2:0] dram_io_bank_buf;
output [3:0] dram_io_cs_l_buf;
output [287:0] dram_io_data_out_buf;
output [4:0] dram_io_ptr_clk_inv_buf;
/*INPUTS*/
input io_dram_data_valid;
input [31:0] io_dram_ecc_in;
input [255:0] io_dram_data_in;
input dram_io_cas_l;
input dram_io_channel_disabled;
input dram_io_cke;
input dram_io_clk_enable;
input dram_io_drive_data;
input dram_io_drive_enable;
input dram_io_pad_clk_inv;
input dram_io_pad_enable;
input dram_io_ras_l;
input dram_io_write_en_l;
input [14:0] dram_io_addr;
input [2:0] dram_io_bank;
input [3:0] dram_io_cs_l;
input [287:0] dram_io_data_out;
input [4:0] dram_io_ptr_clk_inv;
/************************* CODE *********************************/
assign io_dram_data_in_buf = io_dram_data_in[255:0];
assign io_dram_data_valid_buf = io_dram_data_valid;
assign io_dram_ecc_in_buf = io_dram_ecc_in[31:0];
assign dram_io_addr_buf = dram_io_addr[14:0];
assign dram_io_bank_buf = dram_io_bank[2:0];
assign dram_io_cas_l_buf = dram_io_cas_l;
assign dram_io_channel_disabled_buf = dram_io_channel_disabled;
assign dram_io_cke_buf = dram_io_cke;
assign dram_io_clk_enable_buf = dram_io_clk_enable;
assign dram_io_cs_l_buf = dram_io_cs_l[3:0];
assign dram_io_data_out_buf = dram_io_data_out[287:0];
assign dram_io_drive_data_buf = dram_io_drive_data;
assign dram_io_drive_enable_buf = dram_io_drive_enable;
assign dram_io_pad_clk_inv_buf = dram_io_pad_clk_inv;
assign dram_io_pad_enable_buf = dram_io_pad_enable;
assign dram_io_ptr_clk_inv_buf = dram_io_ptr_clk_inv[4:0];
assign dram_io_ras_l_buf = dram_io_ras_l;
assign dram_io_write_en_l_buf = dram_io_write_en_l;
endmodule
|
// final sub module for text
module game_text
(
input wire clk,
input wire [1:0] ball,
// ball's number (well, 9 is max)
input wire [3:0] dig0, dig1,
// score (well, I think a score more than 9 is highly possible)
input wire [9:0] pix_x, pix_y,
output wire [3:0] text_on,
output reg [2:0] text_rgb
// we output text_rgb only because we have to select it according to FSM
);
// signal declaration
wire [10:0] rom_addr;
reg [6:0] char_addr, char_addr_s, char_addr_l,
char_addr_r, char_addr_o;
// char_addr is the final address selected by MUX
// s stands for score (and ball, but I can not use sb...)
// l stands for logo (well, our special plalindrome logo WPPW)
// r stands for registration information (in this case, student ID and name)
// o stands for over (actually game over I assume, anyway)
reg [3:0] row_addr;
wire [3:0] row_addr_s, row_addr_l, row_addr_r, row_addr_o;
reg [2:0] bit_addr;
wire [2:0] bit_addr_s, bit_addr_l,bit_addr_r, bit_addr_o;
wire [7:0] font_word;
wire font_bit, score_on, logo_on, registration_on, over_on;
wire [5:0] registration_rom_addr;
// instantiate font ROM
font_rom font_unit
(.clk(clk), .addr(rom_addr), .data(font_word));
// this is a real font_rom
// implemented as a block rom
// not the same as the following simple roms
//-------------------------------------------
// score region
// - display two-digit score, ball on top left
// - scale to 16-by-32 font
// - line 1, 16 chars: "Score:DD Ball:D"
//-------------------------------------------
assign score_on = (pix_y[9:5]==0) && (pix_x[9:4]<16);
// all on signal comes out as text_on (array) signal
assign row_addr_s = pix_y[4:1];
assign bit_addr_s = pix_x[3:1];
// all addr will be selected using mux circuit
always @*
case (pix_x[7:4])
4'h0: char_addr_s = 7'h53; // S
4'h1: char_addr_s = 7'h63; // c
4'h2: char_addr_s = 7'h6f; // o
4'h3: char_addr_s = 7'h72; // r
4'h4: char_addr_s = 7'h65; // e
4'h5: char_addr_s = 7'h3a; // :
4'h6: char_addr_s = {3'b011, dig1}; // digit 10
4'h7: char_addr_s = {3'b011, dig0}; // digit 1
4'h8: char_addr_s = 7'h00; //
4'h9: char_addr_s = 7'h00; //
4'ha: char_addr_s = 7'h42; // B
4'hb: char_addr_s = 7'h61; // a
4'hc: char_addr_s = 7'h6c; // l
4'hd: char_addr_s = 7'h6c; // l
4'he: char_addr_s = 7'h3a; // :
4'hf: char_addr_s = {5'b01100, ball};
// this kind of concatenation is to perform num2str (matlab or python)
endcase
//-------------------------------------------
// logo region:
// - display logo "WPPW" at top center
// - stands for Wei Pang Peng Wei
// - used as background
// - scale to 64-by-128 font
//-------------------------------------------
assign logo_on = (pix_y[9:7]==2) &&
(3<=pix_x[9:6]) && (pix_x[9:6]<=6);
assign row_addr_l = pix_y[6:3];
assign bit_addr_l = pix_x[5:3];
always @*
case (pix_x[8:6])
3'o3: char_addr_l = 7'h57; // W
3'o4: char_addr_l = 7'h50; // P
3'o5: char_addr_l = 7'h50; // P
default: char_addr_l = 7'h57; // W
// using default to avoid warning
endcase
//-------------------------------------------
// registration region
// - display registration (4-by-16 tiles)on center
// - registration text:
// 3120103795
// Pengwei Wu
// 3120102358
// Wei Cheng
//-------------------------------------------
assign registration_on = (pix_x[9:7]==2) && (pix_y[9:6]==2);
assign row_addr_r = pix_y[3:0];
assign bit_addr_r = pix_x[2:0];
assign registration_rom_addr = {pix_y[5:4], pix_x[6:3]};
always @*
case (registration_rom_addr)
// row 1 generated by MATLAB
6'h00: char_addr_r = 7'h33;
6'h01: char_addr_r = 7'h31;
6'h02: char_addr_r = 7'h32;
6'h03: char_addr_r = 7'h30;
6'h04: char_addr_r = 7'h31;
6'h05: char_addr_r = 7'h30;
6'h06: char_addr_r = 7'h33;
6'h07: char_addr_r = 7'h37;
6'h08: char_addr_r = 7'h39;
6'h09: char_addr_r = 7'h35;
6'h0A: char_addr_r = 7'h20;
6'h0B: char_addr_r = 7'h20;
6'h0C: char_addr_r = 7'h20;
6'h0D: char_addr_r = 7'h20;
// visualization
// well
6'h0E: char_addr_r = 7'h20;
6'h0F: char_addr_r = 7'h20;
// row 2
6'h10: char_addr_r = 7'h50;
6'h11: char_addr_r = 7'h65;
6'h12: char_addr_r = 7'h6E;
6'h13: char_addr_r = 7'h67;
6'h14: char_addr_r = 7'h77;
6'h15: char_addr_r = 7'h65;
6'h16: char_addr_r = 7'h69;
6'h17: char_addr_r = 7'h20;
6'h18: char_addr_r = 7'h57;
6'h19: char_addr_r = 7'h75;
6'h1A: char_addr_r = 7'h20;
6'h1B: char_addr_r = 7'h20;
6'h1C: char_addr_r = 7'h20;
6'h1D: char_addr_r = 7'h20;
// visualization
// well
6'h1E: char_addr_r = 7'h20;
6'h1F: char_addr_r = 7'h20;
// row 3
6'h20: char_addr_r = 7'h33;
6'h21: char_addr_r = 7'h31;
6'h22: char_addr_r = 7'h32;
6'h23: char_addr_r = 7'h30;
6'h24: char_addr_r = 7'h31;
6'h25: char_addr_r = 7'h30;
6'h26: char_addr_r = 7'h32;
6'h27: char_addr_r = 7'h33;
6'h28: char_addr_r = 7'h35;
6'h29: char_addr_r = 7'h38;
6'h2A: char_addr_r = 7'h20;
6'h2B: char_addr_r = 7'h20;
6'h2C: char_addr_r = 7'h20;
6'h2D: char_addr_r = 7'h20;
// visualization
// well
6'h2E: char_addr_r = 7'h20;
6'h2F: char_addr_r = 7'h20;
// row 4
/* 6'h30: char_addr_r = 7'h20;
6'h31: char_addr_r = 7'h20;
6'h32: char_addr_r = 7'h20;
6'h33: char_addr_r = 7'h20;
6'h34: char_addr_r = 7'h20;
6'h35: char_addr_r = 7'h20;
6'h36: char_addr_r = 7'h20;
6'h37: char_addr_r = 7'h20;
6'h38: char_addr_r = 7'h20;
6'h39: char_addr_r = 7'h20;
6'h3A: char_addr_r = 7'h20;
6'h3B: char_addr_r = 7'h20;
6'h3C: char_addr_r = 7'h20;
6'h3D: char_addr_r = 7'h20;
// well, this is very annoying, try consola?
6'h3E: char_addr_r = 7'h20;
6'h3F: char_addr_r = 7'h20; */
6'h30: char_addr_r = 7'h57;
6'h31: char_addr_r = 7'h65;
6'h32: char_addr_r = 7'h69;
6'h33: char_addr_r = 7'h20;
6'h34: char_addr_r = 7'h43;
6'h35: char_addr_r = 7'h68;
6'h36: char_addr_r = 7'h65;
6'h37: char_addr_r = 7'h6E;
6'h38: char_addr_r = 7'h67;
6'h39: char_addr_r = 7'h20;
6'h3A: char_addr_r = 7'h20;
6'h3B: char_addr_r = 7'h20;
6'h3C: char_addr_r = 7'h20;
6'h3D: char_addr_r = 7'h20;
// well, this is very annoying, try consola?
6'h3E: char_addr_r = 7'h20;
6'h3F: char_addr_r = 7'h20;
endcase
//-------------------------------------------
// game over region
// - display "Game Over" at center
// - scale to 32-by-64 fonts
//-----------------------------------------
// don't worry about game over text display sequence
// will be adjusted in the top module by FSM
assign over_on = (pix_y[9:6]==3) &&
(5<=pix_x[9:5]) && (pix_x[9:5]<=13);
assign row_addr_o = pix_y[5:2];
assign bit_addr_o = pix_x[4:2];
always @*
case(pix_x[8:5])
4'h5: char_addr_o = 7'h47; // G
4'h6: char_addr_o = 7'h61; // a
4'h7: char_addr_o = 7'h6d; // m
4'h8: char_addr_o = 7'h65; // e
4'h9: char_addr_o = 7'h00; //
4'ha: char_addr_o = 7'h4f; // O
4'hb: char_addr_o = 7'h76; // v
4'hc: char_addr_o = 7'h65; // e
default: char_addr_o = 7'h72; // r
endcase
//-------------------------------------------
// mux for font ROM addresses and rgb
//-------------------------------------------
// you can adjust color here
always @*
begin
text_rgb = 3'b110; // background, yellow
if (score_on)
begin
char_addr = char_addr_s;
row_addr = row_addr_s;
bit_addr = bit_addr_s;
if (font_bit)
text_rgb = 3'b001;
end
else if (registration_on)
begin
char_addr = char_addr_r;
row_addr = row_addr_r;
bit_addr = bit_addr_r;
if (font_bit)
text_rgb = 3'b001;
end
else if (logo_on)
begin
char_addr = char_addr_l;
row_addr = row_addr_l;
bit_addr = bit_addr_l;
if (font_bit)
text_rgb = 3'b011;
end
else // game over
begin
char_addr = char_addr_o;
row_addr = row_addr_o;
bit_addr = bit_addr_o;
if (font_bit)
text_rgb = 3'b001;
end
end
assign text_on = {score_on, logo_on, registration_on, over_on};
//-------------------------------------------
// font rom interface (well)
//-------------------------------------------
// just concatenation
assign rom_addr = {char_addr, row_addr};
assign font_bit = font_word[~bit_addr];
endmodule
|
//------------------------------------------------------------------------------
// This confidential and proprietary software may be used only as authorized by
// a licensing agreement from Altera Corporation.
//
// Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// The entire notice above must be reproduced on all authorized copies and any
// such reproduction must be pursuant to a licensing agreement from Altera.
//
// Title : Example top level testbench for ddr3_int DDR/2/3 SDRAM High Performance Controller
// Project : DDR/2/3 SDRAM High Performance Controller
//
// File : ddr3_int_example_top_tb.v
//
// Revision : V10.0
//
// Abstract:
// Automatically generated testbench for the example top level design to allow
// functional and timing simulation.
//
//------------------------------------------------------------------------------
//
// *************** This is a MegaWizard generated file ****************
//
// If you need to edit this file make sure the edits are not inside any 'MEGAWIZARD'
// text insertion areas.
// (between "<< START MEGAWIZARD INSERT" and "<< END MEGAWIZARD INSERT" comments)
//
// Any edits inside these delimiters will be overwritten by the megawizard if you
// re-run it.
//
// If you really need to make changes inside these delimiters then delete
// both 'START' and 'END' delimiters. This will stop the megawizard updating this
// section again.
//
//----------------------------------------------------------------------------------
// << START MEGAWIZARD INSERT PARAMETER_LIST
// Parameters:
//
// Device Family : arria ii gx
// local Interface Data Width : 128
// MEM_CHIPSELS : 1
// MEM_CS_PER_RANK : 1
// MEM_BANK_BITS : 3
// MEM_ROW_BITS : 13
// MEM_COL_BITS : 10
// LOCAL_DATA_BITS : 128
// NUM_CLOCK_PAIRS : 1
// CLOCK_TICK_IN_PS : 3333
// REGISTERED_DIMM : false
// TINIT_CLOCKS : 75008
// Data_Width_Ratio : 4
// << END MEGAWIZARD INSERT PARAMETER_LIST
//----------------------------------------------------------------------------------
// << MEGAWIZARD PARSE FILE DDR10.0
`timescale 1 ps/1 ps
// << START MEGAWIZARD INSERT MODULE
module ddr3_int_example_top_tb ();
// << END MEGAWIZARD INSERT MODULE
// << START MEGAWIZARD INSERT PARAMS
parameter gMEM_CHIPSELS = 1;
parameter gMEM_CS_PER_RANK = 1;
parameter gMEM_NUM_RANKS = 1 / 1;
parameter gMEM_BANK_BITS = 3;
parameter gMEM_ROW_BITS = 13;
parameter gMEM_COL_BITS = 10;
parameter gMEM_ADDR_BITS = 13;
parameter gMEM_DQ_PER_DQS = 8;
parameter DM_DQS_WIDTH = 4;
parameter gLOCAL_DATA_BITS = 128;
parameter gLOCAL_IF_DWIDTH_AFTER_ECC = 128;
parameter gNUM_CLOCK_PAIRS = 1;
parameter RTL_ROUNDTRIP_CLOCKS = 0.0;
parameter CLOCK_TICK_IN_PS = 3333;
parameter REGISTERED_DIMM = 1'b0;
parameter BOARD_DQS_DELAY = 0;
parameter BOARD_CLK_DELAY = 0;
parameter DWIDTH_RATIO = 4;
parameter TINIT_CLOCKS = 75008;
parameter REF_CLOCK_TICK_IN_PS = 26666;
// Parameters below are for generic memory model
parameter gMEM_TQHS_PS = 300;
parameter gMEM_TAC_PS = 400;
parameter gMEM_TDQSQ_PS = 125;
parameter gMEM_IF_TRCD_NS = 13.5;
parameter gMEM_IF_TWTR_CK = 4;
parameter gMEM_TDSS_CK = 0.2;
parameter gMEM_IF_TRFC_NS = 110.0;
parameter gMEM_IF_TRP_NS = 13.5;
parameter gMEM_IF_TRCD_PS = gMEM_IF_TRCD_NS * 1000.0;
parameter gMEM_IF_TWTR_PS = gMEM_IF_TWTR_CK * CLOCK_TICK_IN_PS;
parameter gMEM_IF_TRFC_PS = gMEM_IF_TRFC_NS * 1000.0;
parameter gMEM_IF_TRP_PS = gMEM_IF_TRP_NS * 1000.0;
parameter CLOCK_TICK_IN_NS = CLOCK_TICK_IN_PS / 1000.0;
parameter gMEM_TDQSQ_NS = gMEM_TDQSQ_PS / 1000.0;
parameter gMEM_TDSS_NS = gMEM_TDSS_CK * CLOCK_TICK_IN_NS;
// << END MEGAWIZARD INSERT PARAMS
// set to zero for Gatelevel
parameter RTL_DELAYS = 1;
parameter USE_GENERIC_MEMORY_MODEL = 1'b0;
// The round trip delay is now modeled inside the datapath (<your core name>_auk_ddr_dqs_group.v/vhd) for RTL simulation.
parameter D90_DEG_DELAY = 0; //RTL only
parameter GATE_BOARD_DQS_DELAY = BOARD_DQS_DELAY * (RTL_DELAYS ? 0 : 1); // Gate level timing only
parameter GATE_BOARD_CLK_DELAY = BOARD_CLK_DELAY * (RTL_DELAYS ? 0 : 1); // Gate level timing only
// Below 5 lines for SPR272543:
// Testbench workaround for tests with "dedicated memory clock phase shift" failing,
// because dqs delay isnt' being modelled in simulations
parameter gMEM_CLK_PHASE_EN = "false";
parameter real gMEM_CLK_PHASE = 0;
parameter real MEM_CLK_RATIO = ((360.0-gMEM_CLK_PHASE)/360.0);
parameter MEM_CLK_DELAY = MEM_CLK_RATIO*CLOCK_TICK_IN_PS * ((gMEM_CLK_PHASE_EN=="true") ? 1 : 0);
wire clk_to_ram0, clk_to_ram1, clk_to_ram2;
wire cmd_bus_watcher_enabled;
reg clk;
reg clk_n;
reg reset_n;
wire mem_reset_n;
wire[gMEM_ADDR_BITS - 1:0] a;
wire[gMEM_BANK_BITS - 1:0] ba;
wire[gMEM_CHIPSELS - 1:0] cs_n;
wire[gMEM_NUM_RANKS - 1:0] cke;
wire[gMEM_NUM_RANKS - 1:0] odt; //DDR2 only
wire ras_n;
wire cas_n;
wire we_n;
wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dm;
//wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dqs;
//wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dqs_n;
//wire stratix_dqs_ref_clk; // only used on stratix to provide external dll reference clock
wire[gNUM_CLOCK_PAIRS - 1:0] clk_to_sdram;
wire[gNUM_CLOCK_PAIRS - 1:0] clk_to_sdram_n;
wire #(GATE_BOARD_CLK_DELAY * 1) clk_to_ram;
wire clk_to_ram_n;
wire[gMEM_ROW_BITS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) a_delayed;
wire[gMEM_BANK_BITS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) ba_delayed;
wire[gMEM_NUM_RANKS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) cke_delayed;
wire[gMEM_NUM_RANKS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) odt_delayed; //DDR2 only
wire[gMEM_NUM_RANKS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) cs_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) ras_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) cas_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) we_n_delayed;
wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dm_delayed;
// DDR3 parity only
wire ac_parity;
wire mem_err_out_n;
assign mem_err_out_n = 1'b1;
// pulldown (dm);
assign (weak1, weak0) dm = 0;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO - 1:0] mem_dq = 100'bz;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] mem_dqs = 100'bz;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] mem_dqs_n = 100'bz;
assign (weak1, weak0) mem_dq = 0;
assign (weak1, weak0) mem_dqs = 0;
assign (weak1, weak0) mem_dqs_n = 1;
wire [gMEM_BANK_BITS - 1:0] zero_one; //"01";
assign zero_one = 1;
wire test_complete;
wire [7:0] test_status;
// counter to count the number of sucessful read and write loops
integer test_complete_count;
wire pnf;
wire [gLOCAL_IF_DWIDTH_AFTER_ECC / 8 - 1:0] pnf_per_byte;
assign cmd_bus_watcher_enabled = 1'b0;
// Below 5 lines for SPR272543:
// Testbench workaround for tests with "dedicated memory clock phase shift" failing,
// because dqs delay isnt' being modelled in simulations
assign #(MEM_CLK_DELAY/4.0) clk_to_ram2 = clk_to_sdram[0];
assign #(MEM_CLK_DELAY/4.0) clk_to_ram1 = clk_to_ram2;
assign #(MEM_CLK_DELAY/4.0) clk_to_ram0 = clk_to_ram1;
assign #((MEM_CLK_DELAY/4.0)) clk_to_ram = clk_to_ram0;
assign clk_to_ram_n = ~clk_to_ram ; // mem model ignores clk_n ?
// ddr sdram interface
// << START MEGAWIZARD INSERT ENTITY
ddr3_int_example_top dut (
// << END MEGAWIZARD INSERT ENTITY
.clock_source(clk),
.global_reset_n(reset_n),
// << START MEGAWIZARD INSERT PORT_MAP
.mem_clk(clk_to_sdram),
.mem_clk_n(clk_to_sdram_n),
.mem_odt(odt),
.mem_dqsn(mem_dqs_n),
.mem_reset_n(mem_reset_n),
.mem_cke(cke),
.mem_cs_n(cs_n),
.mem_ras_n(ras_n),
.mem_cas_n(cas_n),
.mem_we_n(we_n),
.mem_ba(ba),
.mem_addr(a),
.mem_dq(mem_dq),
.mem_dqs(mem_dqs),
.mem_dm(dm),
// << END MEGAWIZARD INSERT PORT_MAP
.test_complete(test_complete),
.test_status(test_status),
.pnf_per_byte(pnf_per_byte),
.pnf(pnf)
);
// << START MEGAWIZARD INSERT MEMORY_ARRAY
// This will need updating to match the memory models you are using.
// Instantiate a generated DDR memory model to match the datawidth & chipselect requirements
ddr3_int_mem_model mem (
.mem_rst_n (mem_reset_n),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs),
.mem_dqs_n (mem_dqs_n),
.mem_addr (a_delayed),
.mem_ba (ba_delayed),
.mem_clk (clk_to_ram),
.mem_clk_n (clk_to_ram_n),
.mem_cke (cke_delayed),
.mem_cs_n (cs_n_delayed),
.mem_ras_n (ras_n_delayed),
.mem_cas_n (cas_n_delayed),
.mem_we_n (we_n_delayed),
.mem_dm (dm_delayed),
.mem_odt (odt_delayed)
);
// << END MEGAWIZARD INSERT MEMORY_ARRAY
always
begin
clk <= 1'b0 ;
clk_n <= 1'b1 ;
while (1'b1)
begin
#((REF_CLOCK_TICK_IN_PS / 2) * 1);
clk <= ~clk ;
clk_n <= ~clk_n ;
end
end
initial
begin
reset_n <= 1'b0 ;
@(clk);
@(clk);
@(clk);
@(clk);
@(clk);
@(clk);
reset_n <= 1'b1 ;
end
// control and data lines = 3 inches
assign a_delayed = a[gMEM_ROW_BITS - 1:0] ;
assign ba_delayed = ba ;
assign cke_delayed = cke ;
assign odt_delayed = odt ;
assign cs_n_delayed = cs_n ;
assign ras_n_delayed = ras_n ;
assign cas_n_delayed = cas_n ;
assign we_n_delayed = we_n ;
assign dm_delayed = dm ;
// ---------------------------------------------------------------
initial
begin : endit
integer count;
reg ln;
count = 0;
// Stop simulation after test_complete or TINIT + 600000 clocks
while ((count < (TINIT_CLOCKS + 600000)) & (test_complete !== 1))
begin
count = count + 1;
@(negedge clk_to_sdram[0]);
end
if (test_complete === 1)
begin
if (pnf)
begin
$write($time);
$write(" --- SIMULATION PASSED --- ");
$stop;
end
else
begin
$write($time);
$write(" --- SIMULATION FAILED --- ");
$stop;
end
end
else
begin
$write($time);
$write(" --- SIMULATION FAILED, DID NOT COMPLETE --- ");
$stop;
end
end
always @(clk_to_sdram[0] or reset_n)
begin
if (!reset_n)
begin
test_complete_count <= 0 ;
end
else if ((clk_to_sdram[0]))
begin
if (test_complete)
begin
test_complete_count <= test_complete_count + 1 ;
end
end
end
reg[2:0] cmd_bus;
//***********************************************************
// Watch the SDRAM command bus
always @(clk_to_ram)
begin
if (clk_to_ram)
begin
if (1'b1)
begin
cmd_bus = {ras_n_delayed, cas_n_delayed, we_n_delayed};
case (cmd_bus)
3'b000 :
begin
// LMR command
$write($time);
if (ba_delayed == zero_one)
begin
$write(" ELMR settings = ");
if (!(a_delayed[0]))
begin
$write("DLL enable");
end
end
else
begin
$write(" LMR settings = ");
case (a_delayed[1:0])
3'b00 : $write("BL = 8,");
3'b01 : $write("BL = On The Fly,");
3'b10 : $write("BL = 4,");
default : $write("BL = ??,");
endcase
case (a_delayed[6:4])
3'b001 : $write(" CL = 5.0,");
3'b010 : $write(" CL = 6.0,");
3'b011 : $write(" CL = 7.0,");
3'b100 : $write(" CL = 8.0,");
3'b101 : $write(" CL = 9.0,");
3'b110 : $write(" CL = 10.0,");
default : $write(" CL = ??,");
endcase
if ((a_delayed[8])) $write(" DLL reset");
end
$write("\n");
end
3'b001 :
begin
// ARF command
$write($time);
$write(" ARF\n");
end
3'b010 :
begin
// PCH command
$write($time);
$write(" PCH");
if ((a_delayed[10]))
begin
$write(" all banks \n");
end
else
begin
$write(" bank ");
$write("%H\n", ba_delayed);
end
end
3'b011 :
begin
// ACT command
$write($time);
$write(" ACT row address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b100 :
begin
// WR command
$write($time);
$write(" WR to col address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b101 :
begin
// RD command
$write($time);
$write(" RD from col address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b110 :
begin
// BT command
$write($time);
$write(" BT ");
end
3'b111 :
begin
// NOP command
end
endcase
end
else
begin
end // if enabled
end
end
endmodule
|
//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
module ghrd_10as066n2_ocm_0_altera_avalon_onchip_memory2_171_ehvj5ii (
// inputs:
address,
chipselect,
clk,
clken,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "ghrd_10as066n2_ocm_0_ocm_0.hex";
output [ 7: 0] readdata;
input [ 17: 0] address;
input chipselect;
input clk;
input clken;
input freeze;
input reset;
input reset_req;
input write;
input [ 7: 0] writedata;
wire clocken0;
wire [ 7: 0] readdata;
wire wren;
assign wren = chipselect & write & clken;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 262144,
the_altsyncram.numwords_a = 262144,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.read_during_write_mode_port_a = "DONT_CARE",
the_altsyncram.width_a = 8,
the_altsyncram.widthad_a = 18;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
// AUTOGEN
module iobus_1_connect(
// unused
input wire clk,
input wire reset,
// Master
input wire m_iob_poweron,
input wire m_iob_reset,
input wire m_datao_clear,
input wire m_datao_set,
input wire m_cono_clear,
input wire m_cono_set,
input wire m_iob_fm_datai,
input wire m_iob_fm_status,
input wire m_rdi_pulse,
input wire [3:9] m_ios,
input wire [0:35] m_iob_write,
output wire [1:7] m_pi_req,
output wire [0:35] m_iob_read,
output wire m_dr_split,
output wire m_rdi_data,
// Slave 0
output wire s0_iob_poweron,
output wire s0_iob_reset,
output wire s0_datao_clear,
output wire s0_datao_set,
output wire s0_cono_clear,
output wire s0_cono_set,
output wire s0_iob_fm_datai,
output wire s0_iob_fm_status,
output wire s0_rdi_pulse,
output wire [3:9] s0_ios,
output wire [0:35] s0_iob_write,
input wire [1:7] s0_pi_req,
input wire [0:35] s0_iob_read,
input wire s0_dr_split,
input wire s0_rdi_data
);
assign m_pi_req = 0 | s0_pi_req;
assign m_iob_read = m_iob_write | s0_iob_read;
assign m_dr_split = 0 | s0_dr_split;
assign m_rdi_data = 0 | s0_rdi_data;
assign s0_iob_poweron = m_iob_poweron;
assign s0_iob_reset = m_iob_reset;
assign s0_datao_clear = m_datao_clear;
assign s0_datao_set = m_datao_set;
assign s0_cono_clear = m_cono_clear;
assign s0_cono_set = m_cono_set;
assign s0_iob_fm_datai = m_iob_fm_datai;
assign s0_iob_fm_status = m_iob_fm_status;
assign s0_rdi_pulse = m_rdi_pulse;
assign s0_ios = m_ios;
assign s0_iob_write = m_iob_write;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__INV_BEHAVIORAL_V
`define SKY130_FD_SC_LS__INV_BEHAVIORAL_V
/**
* inv: Inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__inv (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__INV_BEHAVIORAL_V |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2017 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2018.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / User Interface to Global Clock, Reset and 3-State Controls
// /___/ /\ Filename : STARTUPE3.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 07/12/13 - Initial version.
// 02/06/14 - Fixed tristate of USRCCLKTS (CR 766066).
// 04/15/14 - Updated FCSBO, DO and DI to connect to glbl (CR 763244).
// 05/27/14 - New simulation library message format.
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module STARTUPE3 #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter PROG_USR = "FALSE",
parameter real SIM_CCLK_FREQ = 0.0
)(
output CFGCLK,
output CFGMCLK,
output [3:0] DI,
output EOS,
output PREQ,
input [3:0] DO,
input [3:0] DTS,
input FCSBO,
input FCSBTS,
input GSR,
input GTS,
input KEYCLEARB,
input PACK,
input USRCCLKO,
input USRCCLKTS,
input USRDONEO,
input USRDONETS
);
reg SIM_CCLK_FREQ_BINARY;
reg [2:0] PROG_USR_BINARY;
time CFGMCLK_PERIOD = 20000;
reg cfgmclk_out;
localparam MODULE_NAME = "STARTUPE3";
assign (strong1,weak0) glbl.GSR = GSR;
assign (strong1,weak0) glbl.GTS = GTS;
wire start_count;
integer edge_count;
reg preq_deassert;
reg PREQ_out;
wire EOS_out;
// Counters and Flags
reg [2:0] edge_count_cclko;
reg [2:0] cclko_wait_count;
reg start_glbl_cclko;
initial begin
case (PROG_USR)
"FALSE" : PROG_USR_BINARY = 3'b000;
"TRUE" : PROG_USR_BINARY = 3'b111;
default : begin
$display("Error: [Unisim %s-101] PROG_USR attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PROG_USR);
#1 $finish;
end
endcase
if ((SIM_CCLK_FREQ >= 0.0) && (SIM_CCLK_FREQ <= 10.0))
SIM_CCLK_FREQ_BINARY = SIM_CCLK_FREQ;
else begin
$display("Error: [Unisim %s-102] SIM_CCLK_FREQ attribute is set to %f. Legal values for this attribute are 0.0 to 10.0. Instance: %m", MODULE_NAME, SIM_CCLK_FREQ);
#1 $finish;
end
end
//-------------------------------------------------------------------------------
//----------------- Initial -----------------------------------------------------
//-------------------------------------------------------------------------------
initial begin
cfgmclk_out = 0;
edge_count = 0;
preq_deassert = 1'b0;
PREQ_out = 1'b0;
edge_count_cclko = 3'b000;
cclko_wait_count = 3'b010;
start_glbl_cclko = 1'b0;
forever #(CFGMCLK_PERIOD/2.0) cfgmclk_out = !cfgmclk_out;
end
//-------------------------------------------------------------------------------
//-------------------- PREQ -----------------------------------------------------
//-------------------------------------------------------------------------------
assign start_count = (PREQ_out && PACK)? 1'b1 : 1'b0;
always @(posedge cfgmclk_out) begin
if(start_count)
edge_count = edge_count + 1;
else
edge_count = 0;
if(edge_count == 35)
preq_deassert <= 1'b1;
else
preq_deassert <= 1'b0;
end
always @(negedge glbl.PROGB_GLBL, posedge preq_deassert)
PREQ_out <= ~glbl.PROGB_GLBL || ~preq_deassert;
//-------------------------------------------------------------------------------
//-------------------- ERROR MSG ------------------------------------------------
//-------------------------------------------------------------------------------
always @(posedge PACK) begin
if(PREQ_out == 1'b0)
$display("Warning: [Unisim %s-1] PACK received with no associate PREQ. Instance: %m", MODULE_NAME);
end
//-------------------------------------------------------------------------------
//--------------------- EOS -----------------------------------------------------
//-------------------------------------------------------------------------------
assign EOS_out = ~glbl.GSR;
//-------------------------------------------------------------------------------
//-------------------- glbl.CCLKO ---------------------------------------------
//-------------------------------------------------------------------------------
always @(posedge USRCCLKO) begin
if(EOS_out) edge_count_cclko <= edge_count_cclko + 1;
end
always @(edge_count_cclko)
if (edge_count_cclko == cclko_wait_count)
start_glbl_cclko = 1;
//-------------------------------------------------------------------------------
//-------------------- OUTPUT ---------------------------------------------------
//-------------------------------------------------------------------------------
assign CFGMCLK = cfgmclk_out;
assign PREQ = PREQ_out;
assign EOS = EOS_out;
assign glbl.CCLKO_GLBL = start_glbl_cclko ? (~USRCCLKTS ? USRCCLKO : 1'bz) : 1'b1;
assign glbl.FCSBO_GLBL = ~FCSBTS ? FCSBO : 1'bz;
assign glbl.DO_GLBL[0] = ~DTS[0] ? DO[0] : 1'bz;
assign glbl.DO_GLBL[1] = ~DTS[1] ? DO[1] : 1'bz;
assign glbl.DO_GLBL[2] = ~DTS[2] ? DO[2] : 1'bz;
assign glbl.DO_GLBL[3] = ~DTS[3] ? DO[3] : 1'bz;
assign DI = glbl.DI_GLBL;
endmodule
`endcelldefine
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A31OI_1_V
`define SKY130_FD_SC_MS__A31OI_1_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a31oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a31oi_1 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a31oi_1 (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A31OI_1_V
|
// --------------------------------------------------------------------------------
//| Avalon Streaming Channel Adapter
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module master_0_p2b_adapter (
// Interface: clk
input clk,
// Interface: reset
input reset_n,
// Interface: in
output reg in_ready,
input in_valid,
input [ 7: 0] in_data,
input in_startofpacket,
input in_endofpacket,
// Interface: out
input out_ready,
output reg out_valid,
output reg [ 7: 0] out_data,
output reg out_startofpacket,
output reg out_endofpacket,
output reg [ 7: 0] out_channel
);
reg in_channel = 0;
// ---------------------------------------------------------------------
//| Payload Mapping
// ---------------------------------------------------------------------
always @* begin
in_ready = out_ready;
out_valid = in_valid;
out_data = in_data;
out_startofpacket = in_startofpacket;
out_endofpacket = in_endofpacket;
out_channel = 0;
out_channel = in_channel;
end
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps / 1ps
`default_nettype none
module test_eth(
input wire RESET_N,
input wire clkin,
output wire [3:0] rgmii_txd,
output wire rgmii_tx_ctl,
output wire rgmii_txc,
input wire [3:0] rgmii_rxd,
input wire rgmii_rx_ctl,
input wire rgmii_rxc,
output wire mdio_phy_mdc,
inout wire mdio_phy_mdio,
output wire phy_rst_n,
output wire [7:0] LED
);
localparam VERSION = 8'd0;
wire RST;
wire CLK125_PLL, CLK125_90_PLL;
wire PLL_FEEDBACK, LOCKED;
PLLE2_BASE #(
.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
.CLKFBOUT_MULT(10), // Multiply value for all CLKOUT, (2-64)
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360.000-360.000).
.CLKIN1_PERIOD(10.000), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
.CLKOUT0_DIVIDE(8), // Divide amount for CLKOUT0 (1-128)
.CLKOUT0_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999).
.CLKOUT0_PHASE(0.0), // Phase offset for CLKOUT0 (-360.000-360.000).
.CLKOUT1_DIVIDE(8), // Divide amount for CLKOUT0 (1-128)
.CLKOUT1_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999).
.CLKOUT1_PHASE(90.0), // Phase offset for CLKOUT0 (-360.000-360.000).
.DIVCLK_DIVIDE(1), // Master division value, (1-56)
.REF_JITTER1(0.0), // Reference input jitter in UI, (0.000-0.999).
.STARTUP_WAIT("FALSE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
) PLLE2_BASE_inst (
.CLKOUT0(CLK125_PLL),
.CLKOUT1(CLK125_90_PLL),
.CLKOUT2(),
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5(),
.CLKFBOUT(PLL_FEEDBACK),
.LOCKED(LOCKED), // 1-bit output: LOCK
// Input 100 MHz clock
.CLKIN1(clkin),
// Control Ports
.PWRDWN(0),
.RST(!RESET_N),
// Feedback
.CLKFBIN(PLL_FEEDBACK)
);
wire PLL_FEEDBACK2, LOCKED2;
wire BUS_CLK_PLL;
PLLE2_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(16),
.CLKFBOUT_PHASE(0.0),
.CLKIN1_PERIOD(10.000),
.CLKOUT0_DIVIDE(12),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0.0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.0),
.STARTUP_WAIT("FALSE")
) PLLE2_BASE_inst_2 (
.CLKOUT0(BUS_CLK_PLL),
.CLKOUT1(),
.CLKOUT2(),
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5(),
.CLKFBOUT(PLL_FEEDBACK2),
.LOCKED(LOCKED2), // 1-bit output: LOCK
.CLKIN1(clkin),
.PWRDWN(0),
.RST(!RESET_N),
.CLKFBIN(PLL_FEEDBACK2)
);
wire BUS_CLK;
BUFG BUFG_inst_BUS_CLK (.O(BUS_CLK), .I(BUS_CLK_PLL)); // 133.3MHz
assign RST = !RESET_N | !LOCKED | !LOCKED2;
wire gmii_tx_clk;
wire gmii_tx_en;
wire [7:0] gmii_txd;
wire gmii_tx_er;
wire gmii_crs;
wire gmii_col;
wire gmii_rx_clk;
wire gmii_rx_dv;
wire [7:0] gmii_rxd;
wire gmii_rx_er;
wire mdio_gem_mdc;
wire mdio_gem_i;
wire mdio_gem_o;
wire mdio_gem_t;
wire link_status;
wire [1:0] clock_speed;
wire duplex_status;
reg GMII_1000M;
wire MII_TX_CLK, MII_TX_CLK_90;
BUFGMUX GMIIMUX (.O(MII_TX_CLK), .I0(rgmii_rxc), .I1(CLK125_PLL), .S(GMII_1000M));
BUFGMUX GMIIMUX90 (.O(MII_TX_CLK_90), .I0(rgmii_rxc), .I1(CLK125_90_PLL), .S(GMII_1000M));
rgmii_io rgmii (
.rgmii_txd(rgmii_txd),
.rgmii_tx_ctl(rgmii_tx_ctl),
.rgmii_txc(rgmii_txc),
.rgmii_rxd(rgmii_rxd),
.rgmii_rx_ctl(rgmii_rx_ctl),
.gmii_txd_int(gmii_txd), // Internal gmii_txd signal.
.gmii_tx_en_int(gmii_tx_en),
.gmii_tx_er_int(gmii_tx_er),
.gmii_col_int(gmii_col),
.gmii_crs_int(gmii_crs),
.gmii_rxd_reg(gmii_rxd), // RGMII double data rate data valid.
.gmii_rx_dv_reg(gmii_rx_dv), // gmii_rx_dv_ibuf registered in IOBs.
.gmii_rx_er_reg(gmii_rx_er), // gmii_rx_er_ibuf registered in IOBs.
.eth_link_status(link_status),
.eth_clock_speed(clock_speed),
.eth_duplex_status(duplex_status),
// FOllowing are generated by DCMs
.tx_rgmii_clk_int(MII_TX_CLK), // Internal RGMII transmitter clock.
.tx_rgmii_clk90_int(MII_TX_CLK_90), // Internal RGMII transmitter clock w/ 90 deg phase
.rx_rgmii_clk_int(rgmii_rxc), // Internal RGMII receiver clock
.reset(!phy_rst_n)
);
//assign GMII_1000M = &clock_speed;
always @(posedge BUS_CLK or posedge RST)begin
if (RST) begin
GMII_1000M <= 1'b0;
end else begin
GMII_1000M <= clock_speed[1];
end
end
// Instantiate tri-state buffer for MDIO
IOBUF i_iobuf_mdio (
.O(mdio_gem_i),
.IO(mdio_phy_mdio),
.I(mdio_gem_o),
.T(mdio_gem_t)
);
wire EEPROM_CS, EEPROM_SK, EEPROM_DI;
wire TCP_CLOSE_REQ;
wire RBCP_ACT, RBCP_WE, RBCP_RE;
wire [7:0] RBCP_WD, RBCP_RD;
wire [31:0] RBCP_ADDR;
wire TCP_RX_WR;
wire [7:0] TCP_RX_DATA;
//reg [15:0] TCP_RX_WC;
wire [15:0] TCP_RX_WC;
wire RBCP_ACK;
wire SiTCP_RST;
wire TCP_TX_FULL;
wire TCP_TX_WR;
wire [7:0] TCP_TX_DATA;
WRAP_SiTCP_GMII_XC7K_32K #(
.TIM_PERIOD(8'd133)
) sitcp (
.CLK(BUS_CLK) , // in : System Clock >129MHz
.RST(RST) , // in : System reset
// Configuration parameters
.FORCE_DEFAULTn(1'b0) , // in : Load default parameters
.EXT_IP_ADDR(32'hc0a80a10) , // in : IP address[31:0] //192.168.10.16
.EXT_TCP_PORT(16'd24) , // in : TCP port #[15:0]
.EXT_RBCP_PORT(16'd4660) , // in : RBCP port #[15:0]
.PHY_ADDR(5'd3) , // in : PHY-device MIF address[4:0]
// EEPROM
.EEPROM_CS(EEPROM_CS) , // out : Chip select
.EEPROM_SK(EEPROM_SK) , // out : Serial data clock
.EEPROM_DI(EEPROM_DI) , // out : Serial write data
.EEPROM_DO(1'b0) , // in : Serial read data
// user data, intialial values are stored in the EEPROM, 0xFFFF_FC3C-3F
.USR_REG_X3C() , // out : Stored at 0xFFFF_FF3C
.USR_REG_X3D() , // out : Stored at 0xFFFF_FF3D
.USR_REG_X3E() , // out : Stored at 0xFFFF_FF3E
.USR_REG_X3F() , // out : Stored at 0xFFFF_FF3F
// MII interface
.GMII_RSTn(phy_rst_n) , // out : PHY reset
.GMII_1000M(GMII_1000M) , // in : GMII mode (0:MII, 1:GMII)
// TX
.GMII_TX_CLK(MII_TX_CLK) , // in : Tx clock
.GMII_TX_EN(gmii_tx_en) , // out : Tx enable
.GMII_TXD(gmii_txd) , // out : Tx data[7:0]
.GMII_TX_ER(gmii_tx_er) , // out : TX error
// RX
.GMII_RX_CLK(rgmii_rxc) , // in : Rx clock
.GMII_RX_DV(gmii_rx_dv) , // in : Rx data valid
.GMII_RXD(gmii_rxd) , // in : Rx data[7:0]
.GMII_RX_ER(gmii_rx_er) , // in : Rx error
.GMII_CRS(gmii_crs) , // in : Carrier sense
.GMII_COL(gmii_col) , // in : Collision detected
// Management IF
.GMII_MDC(mdio_phy_mdc) , // out : Clock for MDIO
.GMII_MDIO_IN(mdio_gem_i) , // in : Data
.GMII_MDIO_OUT(mdio_gem_o) , // out : Data
.GMII_MDIO_OE(mdio_gem_t) , // out : MDIO output enable
// User I/F
.SiTCP_RST(SiTCP_RST) , // out : Reset for SiTCP and related circuits
// TCP connection control
.TCP_OPEN_REQ(1'b0) , // in : Reserved input, shoud be 0
.TCP_OPEN_ACK() , // out : Acknowledge for open (=Socket busy)
.TCP_ERROR() , // out : TCP error, its active period is equal to MSL
.TCP_CLOSE_REQ(TCP_CLOSE_REQ) , // out : Connection close request
.TCP_CLOSE_ACK(TCP_CLOSE_REQ) , // in : Acknowledge for closing
// FIFO I/F
.TCP_RX_WC(TCP_RX_WC) , // in : Rx FIFO write count[15:0] (Unused bits should be set 1)
.TCP_RX_WR(TCP_RX_WR) , // out : Write enable
.TCP_RX_DATA(TCP_RX_DATA) , // out : Write data[7:0]
.TCP_TX_FULL(TCP_TX_FULL) , // out : Almost full flag
.TCP_TX_WR(TCP_TX_WR) , // in : Write enable
.TCP_TX_DATA(TCP_TX_DATA) , // in : Write data[7:0]
// RBCP
.RBCP_ACT(RBCP_ACT) , // out : RBCP active
.RBCP_ADDR(RBCP_ADDR) , // out : Address[31:0]
.RBCP_WD(RBCP_WD) , // out : Data[7:0]
.RBCP_WE(RBCP_WE) , // out : Write enable
.RBCP_RE(RBCP_RE) , // out : Read enable
.RBCP_ACK(RBCP_ACK) , // in : Access acknowledge
.RBCP_RD(RBCP_RD) // in : Read data[7:0]
);
// ------- BUS SYGNALING ------- //
wire BUS_WR, BUS_RD, BUS_RST;
wire [31:0] BUS_ADD;
wire [7:0] BUS_DATA;
wire INVALID;
assign BUS_RST = SiTCP_RST;
tcp_to_bus itcp_to_bus (
.BUS_RST(BUS_RST),
.BUS_CLK(BUS_CLK),
.TCP_RX_WC(TCP_RX_WC),
.TCP_RX_WR(TCP_RX_WR),
.TCP_RX_DATA(TCP_RX_DATA),
.RBCP_ACT(RBCP_ACT),
.RBCP_ADDR(RBCP_ADDR),
.RBCP_WD(RBCP_WD),
.RBCP_WE(RBCP_WE),
.RBCP_RE(RBCP_RE),
.RBCP_ACK(RBCP_ACK),
.RBCP_RD(RBCP_RD),
.BUS_WR(BUS_WR),
.BUS_RD(BUS_RD),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.INVALID(INVALID)
);
// ------- MODULE ADREESSES ------- //
// Registers
wire SOFT_RST; // Address: 0
assign SOFT_RST = (BUS_ADD == 0 && BUS_WR);
// reset sync
// when writing to addr = 0 then reset
reg RST_FF, RST_FF2, BUS_RST_FF, BUS_RST_FF2;
always @(posedge BUS_CLK) begin
RST_FF <= SOFT_RST;
RST_FF2 <= RST_FF;
BUS_RST_FF <= BUS_RST;
BUS_RST_FF2 <= BUS_RST_FF;
end
wire SOFT_RST_FLAG;
assign SOFT_RST_FLAG = ~RST_FF2 & RST_FF;
wire BUS_RST_FLAG;
assign BUS_RST_FLAG = BUS_RST_FF2 & ~BUS_RST_FF; // trailing edge
wire RESET;
assign RESET = BUS_RST_FLAG | SOFT_RST_FLAG;
reg [7:0] status_regs[39:0];
wire [7:0] SETUP;
assign SETUP = status_regs[1];
wire [63:0] TEST_DATA;
assign TEST_DATA = {status_regs[9], status_regs[8], status_regs[7], status_regs[6],status_regs[5], status_regs[4], status_regs[3], status_regs[2]};
wire [15:0] TCP_WRITE_DLY;
assign TCP_WRITE_DLY = {status_regs[15], status_regs[14]};
always @(posedge BUS_CLK)
begin
if(RESET)
begin
status_regs[0] <= 8'b0; // Version, Reset
status_regs[1] <= 8'b0; // Setup
status_regs[2] <= 8'b0; // Test data
status_regs[3] <= 8'b0; // Test data
status_regs[4] <= 8'b0; // Test data
status_regs[5] <= 8'b0; // Test data
status_regs[6] <= 8'b0; // Test data
status_regs[7] <= 8'b0; // Test data
status_regs[8] <= 8'b0; // Test data
status_regs[9] <= 8'b0; // Test data
status_regs[10] <= 8'b0; // UDP write counter
status_regs[11] <= 8'b0; // UDP write counter
status_regs[12] <= 8'b0; // UDP write counter
status_regs[13] <= 8'b0; // UDP write counter
status_regs[14] <= 8'b0; // TCP write delay
status_regs[15] <= 8'b0; // TCP write delay
status_regs[16] <= 8'b0; // TCP write counter
status_regs[17] <= 8'b0; // TCP write counter
status_regs[18] <= 8'b0; // TCP write counter
status_regs[19] <= 8'b0; // TCP write counter
status_regs[20] <= 8'b0; // TCP write counter
status_regs[21] <= 8'b0; // TCP write counter
status_regs[22] <= 8'b0; // TCP write counter
status_regs[23] <= 8'b0; // TCP write counter
status_regs[24] <= 8'b0; // TCP failed write counter
status_regs[25] <= 8'b0; // TCP failed write counter
status_regs[26] <= 8'b0; // TCP failed write counter
status_regs[27] <= 8'b0; // TCP failed write counter
status_regs[28] <= 8'b0; // TCP failed write counter
status_regs[29] <= 8'b0; // TCP failed write counter
status_regs[30] <= 8'b0; // TCP failed write counter
status_regs[31] <= 8'b0; // TCP failed write counter
status_regs[32] <= 8'b0; // TCP recv write counter
status_regs[33] <= 8'b0; // TCP recv write counter
status_regs[34] <= 8'b0; // TCP recv write counter
status_regs[35] <= 8'b0; // TCP recv write counter
status_regs[36] <= 8'b0; // TCP recv write counter
status_regs[37] <= 8'b0; // TCP recv write counter
status_regs[38] <= 8'b0; // TCP recv write counter
status_regs[39] <= 8'b0; // TCP recv write counter
end
else if(BUS_WR && BUS_ADD < 40)
begin
status_regs[BUS_ADD[5:0]] <= BUS_DATA;
end
end
reg [31:0] UDP_WRITE_CNT;
reg [63:0] TCP_WRITE_CNT;
reg [63:0] TCP_FAILED_WRITE_CNT;
reg [63:0] TCP_RCV_WRITE_CNT;
reg [7:0] BUS_DATA_OUT;
always @(posedge BUS_CLK) begin
if(BUS_RD) begin
if (BUS_ADD == 0)
BUS_DATA_OUT <= VERSION[7:0];
else if (BUS_ADD == 1)
BUS_DATA_OUT <= SETUP;
else if (BUS_ADD == 2)
BUS_DATA_OUT <= TEST_DATA[7:0];
else if (BUS_ADD == 3)
BUS_DATA_OUT <= TEST_DATA[15:8];
else if (BUS_ADD == 4)
BUS_DATA_OUT <= TEST_DATA[23:16];
else if (BUS_ADD == 5)
BUS_DATA_OUT <= TEST_DATA[31:24];
else if (BUS_ADD == 6)
BUS_DATA_OUT <= TEST_DATA[39:32];
else if (BUS_ADD == 7)
BUS_DATA_OUT <= TEST_DATA[47:40];
else if (BUS_ADD == 8)
BUS_DATA_OUT <= TEST_DATA[55:48];
else if (BUS_ADD == 9)
BUS_DATA_OUT <= TEST_DATA[63:56];
else if (BUS_ADD == 10)
BUS_DATA_OUT <= UDP_WRITE_CNT[7:0];
else if (BUS_ADD == 11)
BUS_DATA_OUT <= UDP_WRITE_CNT[15:8];
else if (BUS_ADD == 12)
BUS_DATA_OUT <= UDP_WRITE_CNT[23:16];
else if (BUS_ADD == 13)
BUS_DATA_OUT <= UDP_WRITE_CNT[31:24];
else if (BUS_ADD == 14)
BUS_DATA_OUT <= TCP_WRITE_DLY[7:0];
else if (BUS_ADD == 15)
BUS_DATA_OUT <= TCP_WRITE_DLY[15:8];
else if (BUS_ADD == 16)
BUS_DATA_OUT <= TCP_WRITE_CNT[7:0];
else if (BUS_ADD == 17)
BUS_DATA_OUT <= TCP_WRITE_CNT[15:8];
else if (BUS_ADD == 18)
BUS_DATA_OUT <= TCP_WRITE_CNT[23:16];
else if (BUS_ADD == 19)
BUS_DATA_OUT <= TCP_WRITE_CNT[31:24];
else if (BUS_ADD == 20)
BUS_DATA_OUT <= TCP_WRITE_CNT[39:32];
else if (BUS_ADD == 21)
BUS_DATA_OUT <= TCP_WRITE_CNT[47:40];
else if (BUS_ADD == 22)
BUS_DATA_OUT <= TCP_WRITE_CNT[55:48];
else if (BUS_ADD == 23)
BUS_DATA_OUT <= TCP_WRITE_CNT[63:56];
else if (BUS_ADD == 24)
BUS_DATA_OUT <= TCP_FAILED_WRITE_CNT[7:0];
else if (BUS_ADD == 25)
BUS_DATA_OUT <= TCP_FAILED_WRITE_CNT[15:8];
else if (BUS_ADD == 26)
BUS_DATA_OUT <= TCP_FAILED_WRITE_CNT[23:16];
else if (BUS_ADD == 27)
BUS_DATA_OUT <= TCP_FAILED_WRITE_CNT[31:24];
else if (BUS_ADD == 28)
BUS_DATA_OUT <= TCP_FAILED_WRITE_CNT[39:32];
else if (BUS_ADD == 29)
BUS_DATA_OUT <= TCP_FAILED_WRITE_CNT[47:40];
else if (BUS_ADD == 30)
BUS_DATA_OUT <= TCP_FAILED_WRITE_CNT[55:48];
else if (BUS_ADD == 31)
BUS_DATA_OUT <= TCP_FAILED_WRITE_CNT[63:56];
else if (BUS_ADD == 32)
BUS_DATA_OUT <= TCP_RCV_WRITE_CNT[7:0];
else if (BUS_ADD == 33)
BUS_DATA_OUT <= TCP_RCV_WRITE_CNT[15:8];
else if (BUS_ADD == 34)
BUS_DATA_OUT <= TCP_RCV_WRITE_CNT[23:16];
else if (BUS_ADD == 35)
BUS_DATA_OUT <= TCP_RCV_WRITE_CNT[31:24];
else if (BUS_ADD == 36)
BUS_DATA_OUT <= TCP_RCV_WRITE_CNT[39:32];
else if (BUS_ADD == 37)
BUS_DATA_OUT <= TCP_RCV_WRITE_CNT[47:40];
else if (BUS_ADD == 38)
BUS_DATA_OUT <= TCP_RCV_WRITE_CNT[55:48];
else if (BUS_ADD == 39)
BUS_DATA_OUT <= TCP_RCV_WRITE_CNT[63:56];
else
BUS_DATA_OUT <= 0;
end
end
reg BUS_READ;
always @(posedge BUS_CLK)
if (BUS_RD & BUS_ADD < 40)
BUS_READ <= 1;
else
BUS_READ <= 0;
assign BUS_DATA = BUS_READ ? BUS_DATA_OUT : 8'hzz;
// Test registers
wire recv_tcp_data_wfull;
wire RECV_TCP_DATA_FULL;
assign RECV_TCP_DATA_FULL = recv_tcp_data_wfull;
wire recv_tcp_data_cdc_fifo_write;
assign recv_tcp_data_cdc_fifo_write = 1'b0; //TCP_RX_WR & ~RECV_TCP_DATA_FULL;
wire recv_tcp_data_fifo_full, recv_tcp_data_cdc_fifo_empty;
wire [7:0] recv_tcp_data_cdc_data_out;
cdc_syncfifo #(
.DSIZE(8),
.ASIZE(3)
) cdc_syncfifo_recv_tcp_data (
.rdata(recv_tcp_data_cdc_data_out),
.wfull(recv_tcp_data_wfull),
.rempty(recv_tcp_data_cdc_fifo_empty),
.wdata(TCP_RX_DATA),
.winc(recv_tcp_data_cdc_fifo_write), .wclk(BUS_CLK), .wrst(RESET),
.rinc(!recv_tcp_data_fifo_full), .rclk(BUS_CLK), .rrst(RESET)
);
always @(posedge BUS_CLK)
if(RESET) begin
TCP_RCV_WRITE_CNT <= 0;
//TCP_RX_WC <= 0;
end else if(recv_tcp_data_cdc_fifo_write) begin
TCP_RCV_WRITE_CNT <= TCP_RCV_WRITE_CNT + 1;
//TCP_RX_WC <= TCP_RX_WC + 1;
end else begin
TCP_RCV_WRITE_CNT <= TCP_RCV_WRITE_CNT;
//TCP_RX_WC <= 0;
end
wire RECV_TCP_DATA_FIFO_READ, RECV_TCP_DATA_FIFO_EMPTY;
wire [31:0] RECV_TCP_FIFO_DATA;
fifo_8_to_32 #(
.DEPTH(1024)
) fifo_recv_tcp_data_i (
.RST(RESET),
.CLK(BUS_CLK),
.WRITE(!recv_tcp_data_cdc_fifo_empty),
.READ(RECV_TCP_DATA_FIFO_READ),
.DATA_IN(recv_tcp_data_cdc_data_out),
.FULL(recv_tcp_data_fifo_full),
.EMPTY(RECV_TCP_DATA_FIFO_EMPTY),
.DATA_OUT(RECV_TCP_FIFO_DATA)
);
always @(posedge BUS_CLK)
begin
if (RESET)
UDP_WRITE_CNT <= 0;
else if (BUS_WR && (BUS_ADD >= 2 && BUS_ADD <= 9))
UDP_WRITE_CNT <= UDP_WRITE_CNT + 1;
else
UDP_WRITE_CNT <= UDP_WRITE_CNT;
end
reg [15:0] TCP_WRITE_DLY_CNT;
always @(posedge BUS_CLK)
if ((TCP_WRITE_DLY == 0) | RESET)
TCP_WRITE_DLY_CNT <= 0;
else if (TCP_WRITE_DLY_CNT == TCP_WRITE_DLY)
TCP_WRITE_DLY_CNT <= 1;
else
TCP_WRITE_DLY_CNT <= TCP_WRITE_DLY_CNT + 1;
reg [31:0] GEN_TCP_DATA;
reg GEN_TCP_DATA_WRITE, GEN_TCP_DATA_WRITE_FF;
always @(posedge BUS_CLK)
GEN_TCP_DATA_WRITE_FF <= GEN_TCP_DATA_WRITE;
always @(posedge BUS_CLK)
if (TCP_WRITE_DLY == 0 || RESET)
GEN_TCP_DATA <= 0;
else if (GEN_TCP_DATA_WRITE_FF)
GEN_TCP_DATA <= GEN_TCP_DATA + 1;
else
GEN_TCP_DATA <= GEN_TCP_DATA;
wire GEN_TCP_DATA_FULL;
wire GEN_TCP_DATA_READ_GRANT;
always @(posedge BUS_CLK)
if (RESET)
begin
GEN_TCP_DATA_WRITE <= 1'b0;
TCP_WRITE_CNT <= 0;
TCP_FAILED_WRITE_CNT <= 0;
end
else if (TCP_WRITE_DLY == 0)
begin
GEN_TCP_DATA_WRITE <= 1'b0;
TCP_WRITE_CNT <= TCP_WRITE_CNT;
TCP_FAILED_WRITE_CNT <= TCP_FAILED_WRITE_CNT;
end
else if (TCP_WRITE_DLY == TCP_WRITE_DLY_CNT && !GEN_TCP_DATA_FULL)
begin
GEN_TCP_DATA_WRITE <= 1'b1;
TCP_WRITE_CNT <= TCP_WRITE_CNT + 1;
TCP_FAILED_WRITE_CNT <= TCP_FAILED_WRITE_CNT;
end
else if (TCP_WRITE_DLY == TCP_WRITE_DLY_CNT && GEN_TCP_DATA_FULL)
begin
GEN_TCP_DATA_WRITE <= 1'b0;
TCP_WRITE_CNT <= TCP_WRITE_CNT;
TCP_FAILED_WRITE_CNT <= TCP_FAILED_WRITE_CNT + 1;
end
else
begin
GEN_TCP_DATA_WRITE <= 1'b0;
TCP_WRITE_CNT <= TCP_WRITE_CNT;
TCP_FAILED_WRITE_CNT <= TCP_FAILED_WRITE_CNT;
end
wire gen_tcp_data_wfull;
assign GEN_TCP_DATA_FULL = gen_tcp_data_wfull;
wire gen_tcp_data_cdc_fifo_write;
assign gen_tcp_data_cdc_fifo_write = GEN_TCP_DATA_WRITE;
wire gen_tcp_data_fifo_full, gen_tcp_data_cdc_fifo_empty;
wire [31:0] gen_tcp_data_cdc_data_out;
cdc_syncfifo #(
.DSIZE(32),
.ASIZE(3)
) cdc_syncfifo_send_tcp_data_i (
.rdata(gen_tcp_data_cdc_data_out),
.wfull(gen_tcp_data_wfull),
.rempty(gen_tcp_data_cdc_fifo_empty),
.wdata(GEN_TCP_DATA),
.winc(gen_tcp_data_cdc_fifo_write), .wclk(BUS_CLK), .wrst(RESET),
.rinc(!gen_tcp_data_fifo_full), .rclk(BUS_CLK), .rrst(RESET)
);
wire GEN_TCP_DATA_FIFO_READ, GEN_TCP_DATA_FIFO_EMPTY;
wire [31:0] GEN_TCP_FIFO_DATA;
gerneric_fifo #(
.DATA_SIZE(32),
.DEPTH(8)
) fifo_send_tcp_data_i (
.reset(RESET),
.clk(BUS_CLK),
.write(!gen_tcp_data_cdc_fifo_empty),
.read(GEN_TCP_DATA_FIFO_READ),
.data_in(gen_tcp_data_cdc_data_out),
.full(gen_tcp_data_fifo_full),
.empty(GEN_TCP_DATA_FIFO_EMPTY),
.data_out(GEN_TCP_FIFO_DATA),
.size()
);
wire ARB_READY_OUT, ARB_WRITE_OUT;
wire [31:0] ARB_DATA_OUT;
wire [1:0] READ_GRANT;
rrp_arbiter #(
.WIDTH(2)
) i_rrp_arbiter (
.RST(RESET),
.CLK(BUS_CLK),
.WRITE_REQ({~RECV_TCP_DATA_FIFO_EMPTY, ~GEN_TCP_DATA_FIFO_EMPTY}),
.HOLD_REQ({2'b0}),
.DATA_IN({RECV_TCP_FIFO_DATA, GEN_TCP_FIFO_DATA}),
.READ_GRANT(READ_GRANT),
.READY_OUT(ARB_READY_OUT),
.WRITE_OUT(ARB_WRITE_OUT),
.DATA_OUT(ARB_DATA_OUT)
);
assign GEN_TCP_DATA_FIFO_READ = READ_GRANT[0];
assign RECV_TCP_DATA_FIFO_READ = READ_GRANT[1];
//assign ARB_WRITE_OUT = GEN_TCP_DATA_WRITE;
//assign ARB_DATA_OUT = GEN_TCP_DATA;
//cdc_fifo is for timing reasons
wire FIFO_FULL;
wire [31:0] cdc_data_out;
wire full_32to8, cdc_fifo_empty;
cdc_syncfifo #(
.DSIZE(32),
.ASIZE(3)
) cdc_syncfifo_i (
.rdata(cdc_data_out),
.wfull(FIFO_FULL),
.rempty(cdc_fifo_empty),
.wdata(ARB_DATA_OUT),
.winc(ARB_WRITE_OUT), .wclk(BUS_CLK), .wrst(RESET),
.rinc(!full_32to8), .rclk(BUS_CLK), .rrst(RESET)
);
assign ARB_READY_OUT = !FIFO_FULL;
wire FIFO_EMPTY;
fifo_32_to_8 #(
.DEPTH(256*1024)
) i_data_fifo (
.RST(RESET),
.CLK(BUS_CLK),
.WRITE(!cdc_fifo_empty),
.READ(TCP_TX_WR),
.DATA_IN(cdc_data_out),
.FULL(full_32to8),
.EMPTY(FIFO_EMPTY),
.DATA_OUT(TCP_TX_DATA)
);
assign TCP_TX_WR = !TCP_TX_FULL && !FIFO_EMPTY;
wire CLK_1HZ, CE_1HZ;
clock_divider #(
.DIVISOR(133333333)
) i_clock_divisor_133MHz_to_1Hz (
.CLK(BUS_CLK),
.RESET(1'b0),
.CE(CE_1HZ),
.CLOCK(CLK_1HZ)
);
wire CLK_3HZ, CE_3HZ;
clock_divider #(
.DIVISOR(44444444)
) i_clock_divisor_133MHz_to_3Hz (
.CLK(BUS_CLK),
.RESET(1'b0),
.CE(CE_3HZ),
.CLOCK(CLK_3HZ)
);
wire FIFO_FULL_SYNC;
three_stage_synchronizer #(
.WIDTH(1)
) three_stage_fifo_full_synchronizer (
.CLK(BUS_CLK),
.IN(FIFO_FULL),
.OUT(FIFO_FULL_SYNC)
);
reg FIFO_WAS_FULL;
always @(posedge BUS_CLK or posedge FIFO_FULL_SYNC) begin
if (CE_3HZ || FIFO_FULL_SYNC) begin
if (FIFO_FULL_SYNC)
FIFO_WAS_FULL <= 1'b1;
else
FIFO_WAS_FULL <= 1'b0;
end
end
reg FIFO_WAS_ALMOST_EMPTY;
always @(posedge BUS_CLK or negedge FIFO_FULL_SYNC) begin
if (CE_3HZ || !FIFO_FULL_SYNC) begin
if (!FIFO_FULL_SYNC)
FIFO_WAS_ALMOST_EMPTY <= 1'b1;
else
FIFO_WAS_ALMOST_EMPTY <= 1'b0;
end
end
reg FIFO_FULL_SLOW;
always @(posedge BUS_CLK or posedge FIFO_WAS_FULL or negedge FIFO_WAS_ALMOST_EMPTY) begin
if (CE_3HZ || (FIFO_WAS_FULL && !FIFO_WAS_ALMOST_EMPTY)) begin
if (FIFO_WAS_FULL && !FIFO_WAS_ALMOST_EMPTY)
FIFO_FULL_SLOW <= 1'b1;
else if (FIFO_WAS_FULL && !FIFO_FULL_SLOW)
FIFO_FULL_SLOW <= 1'b1;
else
FIFO_FULL_SLOW <= 1'b0;
end
end
assign LED[7:4] = ~{clock_speed, duplex_status, (|clock_speed & link_status & (GMII_1000M ? CLK_1HZ : CLK_3HZ)) | INVALID};
assign LED[0] = ~CLK_1HZ;
assign LED[1] = ~FIFO_FULL_SLOW;
assign LED[2] = 1'b1;
assign LED[3] = 1'b1;
endmodule
|
module control_unit (
input wire clk,
input wire rst_n,
// to UART receiver
input wire[7:0] cmd,
input wire rx_rdy,
input wire tx_rdy,
output reg cmd_oen = 1,
output reg data_wen = 1,
output reg[7:0] data = 0,
// to servo fsm
input wire[7:0] servo_angle, // [-90 .. 90] in degrees projected to
output reg[7:0] start_angle, // [8'h00 .. 8'hFF] angle reg's value
output reg[7:0] end_angle,
// to servo driver
input wire servo_cycle_done,
// to sonar_driver
input wire sonar_ready,
input wire[7:0] sonar_distance,
output reg sonar_measure = 0
);
// Internal registers for sonar control
reg[7:0] distance = 0;
// Internal registers for cmd processing
parameter AUTO_MODE = 1'b0;
parameter MANUAL_MODE = 1'b1;
reg mode = AUTO_MODE;
parameter IDLE = 4'h0;
parameter FETCH_CMD = 4'h1;
parameter FETCH_DATA_PRE = 4'h2;
parameter FETCH_DATA = 4'h3;
parameter WAIT_SERVO_DONE = 4'h4;
parameter START_MEASURE = 4'h5;
parameter MEASURE = 4'h6;
parameter WAIT_TX_RDY = 4'h7;
parameter SEND_DATA = 4'h8;
parameter SEND_DATA_POST = 4'h9;
reg[3:0] state = IDLE;
reg[3:0] next_state = IDLE;
reg send_data_type = 0; // 0 - distance; 1 - angle;
// Cmd set
parameter MANUAL_CMD = 4'h0;
// Manual cmd set
parameter SET_ANGLE_CMD = 2'h0;
parameter SET_MODE_CMD = 2'h1;
parameter MEASURE_CMD = 2'h2;
// Assign new state logic
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state = IDLE;
end else begin
state = next_state;
end
end
// Next state logic
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
next_state = IDLE;
end else begin
case(state)
IDLE: begin
if (rx_rdy) begin
next_state = FETCH_CMD;
end else if (mode == AUTO_MODE) begin // In manual mode wait for measure cmd
next_state = WAIT_SERVO_DONE;
end
end
FETCH_CMD: begin
case (cmd[7:4])
MANUAL_CMD: begin // in this case
case (cmd[3:2])
SET_ANGLE_CMD: begin
next_state = FETCH_DATA_PRE;
end
SET_MODE_CMD: begin
next_state = IDLE;
end
MEASURE_CMD: begin
next_state = START_MEASURE;
end
endcase // manual cmd case
end
default: begin // In this case: [7:4] - end angle MSB, [3:0] - start angle MSB
next_state = IDLE;
end
endcase // cmd case
end
FETCH_DATA_PRE: begin
if (rx_rdy) begin
next_state = FETCH_DATA;
end
end
FETCH_DATA: begin
next_state = IDLE;
end
WAIT_SERVO_DONE: begin
if (servo_cycle_done) begin
next_state = START_MEASURE;
end
end
START_MEASURE: begin
next_state = MEASURE;
end
MEASURE: begin
if (sonar_ready) begin
next_state = WAIT_TX_RDY;
end
end
WAIT_TX_RDY: begin
if (tx_rdy) begin
next_state = SEND_DATA;
end
end
SEND_DATA: begin
next_state = SEND_DATA_POST;
end
SEND_DATA_POST: begin
case(send_data_type)
0: next_state = WAIT_TX_RDY;
1: next_state = IDLE;
endcase
end
endcase // state case
end
end
// Outputs logic
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
mode = AUTO_MODE;
cmd_oen = 1;
data_wen = 1;
data = 0;
sonar_measure = 0;
start_angle = 8'h00;
end_angle = 8'hFE;
end else begin
case(state)
IDLE: begin
cmd_oen = 1;
data_wen = 1;
sonar_measure = 0;
end
FETCH_CMD: begin
cmd_oen = 0;
case (cmd[7:4])
MANUAL_CMD: begin // in this case
case (cmd[3:2])
SET_MODE_CMD: begin
mode = cmd[0];
end
endcase // manual cmd case
end
default: begin // In this case: [7:4] - end angle MSB, [3:0] - start angle MSB
if (cmd[3:0] < cmd[7:4]) begin
start_angle = {cmd[3:0], 4'h0};
end_angle = {cmd[7:4], 4'h0};
end else begin
start_angle = {cmd[7:4], 4'h0};
end_angle = {cmd[3:0], 4'h0};
end
end
endcase // cmd case
end
FETCH_DATA_PRE: begin
cmd_oen = 1;
end
FETCH_DATA: begin
start_angle = cmd;
end_angle = cmd;
cmd_oen = 0;
end
WAIT_SERVO_DONE: begin
end
START_MEASURE: begin
sonar_measure = 1; // Generate measure pulse
end
MEASURE: begin
sonar_measure = 0;
distance = sonar_distance;
end
WAIT_TX_RDY: begin
if (tx_rdy) begin
case(send_data_type)
0: data = {distance[7:1], 1'b0}; // Add zero as LSB for show that it's distance byte
1: data = {servo_angle[7:1], 1'b1}; // Add one as LSB for show that it's angle byte
endcase
end
end
SEND_DATA: begin
data_wen = 0;
end
SEND_DATA_POST: begin
data_wen = 1;
send_data_type = !send_data_type;
end
endcase
end
end
endmodule
|
/*
-- ============================================================================
-- FILE NAME : bus_slave_mux.v
-- DESCRIPTION :×ÜÏß´ÓÊô¶à·¸´ÓÃÆ÷ʵÏÖ
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito ÐÂÒ×÷³É
-- ============================================================================
*/
/********** ¹«ÓÃÍ·Îļþ **********/
`include "nettype.h"
`include "stddef.h"
`include "global_config.h"
/********** Ä£¿éÍ·Îļþ **********/
`include "bus.h"
/********** Ä£¿é **********/
module bus_slave_mux (
/********** ÊäÈëÐźŠ**********/
input wire s0_cs_, // 0ºÅ×ÜÏß´ÓÊôƬѡ
input wire s1_cs_, // 1ºÅ×ÜÏß´ÓÊôƬѡ
input wire s2_cs_, // 2ºÅ×ÜÏß´ÓÊôƬѡ
input wire s3_cs_, // 3ºÅ×ÜÏß´ÓÊôƬѡ
input wire s4_cs_, // 4ºÅ×ÜÏß´ÓÊôƬѡ
input wire s5_cs_, // 5ºÅ×ÜÏß´ÓÊôƬѡ
input wire s6_cs_, // 6ºÅ×ÜÏß´ÓÊôƬѡ
input wire s7_cs_, // 7ºÅ×ÜÏß´ÓÊôƬѡ
/********** ¥Ð¥¹¥¹¥ì©`¥ÖÐźŠ**********/
// 0ºÅ×ÜÏß´ÓÊô
input wire [`WordDataBus] s0_rd_data, // ¶Á³öµÄÊý¾Ý
input wire s0_rdy_, // ¾ÍÐ÷
// 1ºÅ×ÜÏß´ÓÊô
input wire [`WordDataBus] s1_rd_data, // ¶Á³öµÄÊý¾Ý
input wire s1_rdy_, // ¾ÍÐ÷
// 2ºÅ×ÜÏß´ÓÊô
input wire [`WordDataBus] s2_rd_data, // ¶Á³öµÄÊý¾Ý
input wire s2_rdy_, // ¾ÍÐ÷
// 3ºÅ×ÜÏß´ÓÊô
input wire [`WordDataBus] s3_rd_data, // ¶Á³öµÄÊý¾Ý
input wire s3_rdy_, // ¾ÍÐ÷
// 4ºÅ×ÜÏß´ÓÊô
input wire [`WordDataBus] s4_rd_data, // ¶Á³öµÄÊý¾Ý
input wire s4_rdy_, // ¾ÍÐ÷
// 5ºÅ×ÜÏß´ÓÊô
input wire [`WordDataBus] s5_rd_data, // ¶Á³öµÄÊý¾Ý
input wire s5_rdy_, // ¾ÍÐ÷
// 6ºÅ×ÜÏß´ÓÊô
input wire [`WordDataBus] s6_rd_data, // ¶Á³öµÄÊý¾Ý
input wire s6_rdy_, // ¾ÍÐ÷
// 7ºÅ×ÜÏß´ÓÊô
input wire [`WordDataBus] s7_rd_data, // ¶Á³öµÄÊý¾Ý
input wire s7_rdy_, // ¾ÍÐ÷
/********** ×ÜÏßÖ÷¿Ø¹²ÏíÐźŠ**********/
output reg [`WordDataBus] m_rd_data, // ¶Á³öµÄÊý¾Ý
output reg m_rdy_ // ¾ÍÐ÷
);
/********** ×ÜÏß´ÓÊô¶à·¸´ÓÃÆ÷ **********/
always @(*) begin
/* Ñ¡ÔñƬѡÐźŶÔÓ¦µÄ´ÓÊô */
if (s0_cs_ == `ENABLE_) begin // ·ÃÎÊ0ºÅ×ÜÏß´ÓÊô
m_rd_data = s0_rd_data;
m_rdy_ = s0_rdy_;
end else if (s1_cs_ == `ENABLE_) begin // ·ÃÎÊ1ºÅ×ÜÏß´ÓÊô
m_rd_data = s1_rd_data;
m_rdy_ = s1_rdy_;
end else if (s2_cs_ == `ENABLE_) begin // ·ÃÎÊ2ºÅ×ÜÏß´ÓÊô
m_rd_data = s2_rd_data;
m_rdy_ = s2_rdy_;
end else if (s3_cs_ == `ENABLE_) begin // ·ÃÎÊ3ºÅ×ÜÏß´ÓÊô
m_rd_data = s3_rd_data;
m_rdy_ = s3_rdy_;
end else if (s4_cs_ == `ENABLE_) begin // ·ÃÎÊ4ºÅ×ÜÏß´ÓÊô
m_rd_data = s4_rd_data;
m_rdy_ = s4_rdy_;
end else if (s5_cs_ == `ENABLE_) begin // ·ÃÎÊ5ºÅ×ÜÏß´ÓÊô
m_rd_data = s5_rd_data;
m_rdy_ = s5_rdy_;
end else if (s6_cs_ == `ENABLE_) begin // ·ÃÎÊ6ºÅ×ÜÏß´ÓÊô
m_rd_data = s6_rd_data;
m_rdy_ = s6_rdy_;
end else if (s7_cs_ == `ENABLE_) begin // ·ÃÎÊ7ºÅ×ÜÏß´ÓÊô
m_rd_data = s7_rd_data;
m_rdy_ = s7_rdy_;
end else begin // ĬÈÏÖµ
m_rd_data = `WORD_DATA_W'h0;
m_rdy_ = `DISABLE_;
end
end
endmodule
|
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description:
*
* Changes:
*/
module nysa_host_interface (
input clk,
input rst
//output reg [7:0] o_reg_example
//input [7:0] i_reg_example
);
//local parameters
localparam PARAM1 = 32'h00000000;
//registes/wires
//submodules
//asynchronous logic
//synchronous logic
endmodule
|
//-----------------------------------------------------------------
// RISC-V Core
// V1.0.1
// Ultra-Embedded.com
// Copyright 2014-2019
//
// [email protected]
//
// License: BSD
//-----------------------------------------------------------------
//
// Copyright (c) 2014-2019, Ultra-Embedded.com
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer
// in the documentation and/or other materials provided with the
// distribution.
// - Neither the name of the author nor the names of its contributors
// may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
// SUCH DAMAGE.
//-----------------------------------------------------------------
module riscv_divider
(
// Inputs
input clk_i
,input rst_i
,input opcode_valid_i
,input [ 31:0] opcode_opcode_i
,input [ 31:0] opcode_pc_i
,input opcode_invalid_i
,input [ 4:0] opcode_rd_idx_i
,input [ 4:0] opcode_ra_idx_i
,input [ 4:0] opcode_rb_idx_i
,input [ 31:0] opcode_ra_operand_i
,input [ 31:0] opcode_rb_operand_i
// Outputs
,output writeback_valid_o
,output [ 31:0] writeback_value_o
);
//-----------------------------------------------------------------
// Includes
//-----------------------------------------------------------------
`include "riscv_defs.v"
//-------------------------------------------------------------
// Registers / Wires
//-------------------------------------------------------------
reg valid_q;
reg [31:0] wb_result_q;
//-------------------------------------------------------------
// Divider
//-------------------------------------------------------------
wire inst_div_w = (opcode_opcode_i & `INST_DIV_MASK) == `INST_DIV;
wire inst_divu_w = (opcode_opcode_i & `INST_DIVU_MASK) == `INST_DIVU;
wire inst_rem_w = (opcode_opcode_i & `INST_REM_MASK) == `INST_REM;
wire inst_remu_w = (opcode_opcode_i & `INST_REMU_MASK) == `INST_REMU;
wire div_rem_inst_w = ((opcode_opcode_i & `INST_DIV_MASK) == `INST_DIV) ||
((opcode_opcode_i & `INST_DIVU_MASK) == `INST_DIVU) ||
((opcode_opcode_i & `INST_REM_MASK) == `INST_REM) ||
((opcode_opcode_i & `INST_REMU_MASK) == `INST_REMU);
wire signed_operation_w = ((opcode_opcode_i & `INST_DIV_MASK) == `INST_DIV) || ((opcode_opcode_i & `INST_REM_MASK) == `INST_REM);
wire div_operation_w = ((opcode_opcode_i & `INST_DIV_MASK) == `INST_DIV) || ((opcode_opcode_i & `INST_DIVU_MASK) == `INST_DIVU);
reg [31:0] dividend_q;
reg [62:0] divisor_q;
reg [31:0] quotient_q;
reg [31:0] q_mask_q;
reg div_inst_q;
reg div_busy_q;
reg invert_res_q;
wire div_start_w = opcode_valid_i & div_rem_inst_w;
wire div_complete_w = !(|q_mask_q) & div_busy_q;
always @(posedge clk_i or posedge rst_i)
if (rst_i)
begin
div_busy_q <= 1'b0;
dividend_q <= 32'b0;
divisor_q <= 63'b0;
invert_res_q <= 1'b0;
quotient_q <= 32'b0;
q_mask_q <= 32'b0;
div_inst_q <= 1'b0;
end
else if (div_start_w)
begin
div_busy_q <= 1'b1;
div_inst_q <= div_operation_w;
if (signed_operation_w && opcode_ra_operand_i[31])
dividend_q <= -opcode_ra_operand_i;
else
dividend_q <= opcode_ra_operand_i;
if (signed_operation_w && opcode_rb_operand_i[31])
divisor_q <= {-opcode_rb_operand_i, 31'b0};
else
divisor_q <= {opcode_rb_operand_i, 31'b0};
invert_res_q <= (((opcode_opcode_i & `INST_DIV_MASK) == `INST_DIV) && (opcode_ra_operand_i[31] != opcode_rb_operand_i[31]) && |opcode_rb_operand_i) ||
(((opcode_opcode_i & `INST_REM_MASK) == `INST_REM) && opcode_ra_operand_i[31]);
quotient_q <= 32'b0;
q_mask_q <= 32'h80000000;
end
else if (div_complete_w)
begin
div_busy_q <= 1'b0;
end
else if (div_busy_q)
begin
if (divisor_q <= {31'b0, dividend_q})
begin
dividend_q <= dividend_q - divisor_q[31:0];
quotient_q <= quotient_q | q_mask_q;
end
divisor_q <= {1'b0, divisor_q[62:1]};
q_mask_q <= {1'b0, q_mask_q[31:1]};
end
reg [31:0] div_result_r;
always @ *
begin
div_result_r = 32'b0;
if (div_inst_q)
div_result_r = invert_res_q ? -quotient_q : quotient_q;
else
div_result_r = invert_res_q ? -dividend_q : dividend_q;
end
always @(posedge clk_i or posedge rst_i)
if (rst_i)
valid_q <= 1'b0;
else
valid_q <= div_complete_w;
always @(posedge clk_i or posedge rst_i)
if (rst_i)
wb_result_q <= 32'b0;
else if (div_complete_w)
wb_result_q <= div_result_r;
assign writeback_valid_o = valid_q;
assign writeback_value_o = wb_result_q;
endmodule
|
module clock_divider(
input wire clk,
input wire reset,
input wire enabled,
output reg refresh_clk,
output reg sys_clk
);
reg [8:0] counter1;
reg [8:0] counter2;
reg [8:0] clk_divid;
always@(posedge clk or negedge reset)
begin
if( ~reset )
begin
refresh_clk <= 1;
sys_clk <= 0;
counter1 <= 0;
counter2 <= 63;
clk_divid <= 127;
end
else if( enabled )
begin
clk_divid <= clk_divid;
if( counter1 < clk_divid )
begin
counter1 <= counter1 + 1;
refresh_clk <= refresh_clk;
end
else
begin
refresh_clk <= !refresh_clk;
counter1 <= 0;
end
if( counter2 < clk_divid )
begin
counter2 <= counter2 + 1;
sys_clk <= sys_clk;
end
else
begin
sys_clk <= !sys_clk;
counter2 <= 0;
end
end
end
endmodule
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* Simple/useful components
*
*/
module LAG_data_reg (data_in, data_out, clk, rst_n);
input flit_t data_in;
output flit_t data_out;
input clk, rst_n;
always@(posedge clk) begin
if (!rst_n) begin
data_out <= '0;
end else begin
data_out <= data_in;
end
end
endmodule
module LAG_ctrl_reg (ctrl_in, ctrl_out, clk, rst_n);
input chan_cntrl_t ctrl_in;
output chan_cntrl_t ctrl_out;
input clk, rst_n;
always@(posedge clk) begin
if (!rst_n) begin
ctrl_out <= '0;
end else begin
ctrl_out <= ctrl_in;
end
end
endmodule
module LAG_pipelined_channel (data_in, ctrl_in, data_out, ctrl_out, clk, rst_n);
parameter stages = 0;
parameter nPC = 1; // Number of physical channels per trunk
input flit_t data_in[nPC-1:0];
input chan_cntrl_t ctrl_in;
output flit_t data_out[nPC-1:0];
output chan_cntrl_t ctrl_out;
input clk, rst_n;
genvar st, pc;
flit_t ch_reg[stages-1:0][nPC-1:0];
chan_cntrl_t ctrl_reg[stages-1:0];
generate
if (stages==0) begin
// no registers in channel
assign data_out = data_in;
assign ctrl_out = ctrl_in;
end else begin
for (st=0; st<stages; st++) begin:eachstage
if (st==0) begin
for (pc = 0; pc < nPC; pc++) begin:eachPC1
LAG_data_reg data_rg (.data_in(data_in[pc]), .data_out(ch_reg[0][pc]), .clk, .rst_n);
end
//LAG_ctrl_reg ctrl_rg (.ctrl_in(ctrl_in), .ctrl_out(ctrl_reg[0]), .clk, .rst_n);
end else begin
for (pc = 0; pc < nPC; pc++) begin:eachPC2
LAG_data_reg data_rg (.data_in(ch_reg[st-1][pc]), .data_out(ch_reg[st][pc]), .clk, .rst_n);
end
//LAG_ctrl_reg ctrl_rg (.ctrl_in(ctrl_reg[st-1]), .ctrl_out(ctrl_reg[st]), .clk, .rst_n);
end
end
assign data_out = ch_reg[stages-1];
//assign ctrl_out = ctrl_reg[stages-1];
assign ctrl_out = ctrl_in;
end
endgenerate
endmodule
//
// Multiplexer with one-hot encoded select input
//
// - output is '0 if no select input is asserted
//
module LAG_mux_oh_select (data_in, select, data_out);
//parameter type dtype_t = byte;
parameter n = 4;
input flit_t data_in [n-1:0];
input [n-1:0] select;
output flit_t data_out;
int i;
always_comb
begin
data_out='0;
for (i=0; i<n; i++) begin
if (select[i]) data_out = data_in[i];
end
end
endmodule // LAG_mux_oh_select
//
// Crossbar built from multiplexers, one-hot encoded select input
//
module LAG_crossbar_oh_select (data_in, select, data_out);
//parameter type dtype_t = byte;
parameter n = 4;
input flit_t data_in [n-1:0];
// select[output][select-input];
input [n-1:0][n-1:0] select; // n one-hot encoded select signals per output
output flit_t data_out [n-1:0];
genvar i;
generate
for (i=0; i<n; i++) begin:outmuxes
LAG_mux_oh_select #(.n(n)) xbarmux (data_in, select[i], data_out[i]);
end
endgenerate
endmodule // LAG_crossbar_oh_select
|
// -----------------------------------------------------------------------------
//
// Copyright 2013(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED
// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// -----------------------------------------------------------------------------
// FILE NAME : debouncer.v
// MODULE NAME : debouncer
// AUTHOR : ACozma
// AUTHOR'S EMAIL : [email protected]
// -----------------------------------------------------------------------------
// KEYWORDS :
// -----------------------------------------------------------------------------
// PURPOSE : Module used for debouncing input signals
// -----------------------------------------------------------------------------
// REUSE ISSUES
// Reset Strategy :
// Clock Domains :
// Critical Timing :
// Test Features :
// Asynchronous I/F :
// Instantiations :
// Synthesizable (y/n) : y
// Target Device :
// Other :
// -----------------------------------------------------------------------------
`timescale 1ns / 1ps
module debouncer
//----------- Paramters Declarations -------------------------------------------
#(
parameter DEBOUNCER_LEN = 4
)
//----------- Ports Declarations -----------------------------------------------
(
input clk_i,
input rst_i,
input sig_i,
output reg sig_o
);
//------------------------------------------------------------------------------
//----------- Registers Declarations -------------------------------------------
//------------------------------------------------------------------------------
reg [DEBOUNCER_LEN-1:0] shift_reg;
//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
//------------------------------------------------------------------------------
always @(posedge clk_i)
begin
if(rst_i == 1)
begin
shift_reg <= 0;
sig_o <= 0;
end
else
begin
shift_reg <= {shift_reg[DEBOUNCER_LEN-2:0], sig_i};
if(shift_reg == {DEBOUNCER_LEN{1'b1}})
begin
sig_o <= 1'b1;
end
else if(shift_reg == {DEBOUNCER_LEN{1'b0}})
begin
sig_o <= 1'b0;
end
end
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:36:39 05/20/2014
// Design Name: program_counter
// Module Name: C:/Users/Deus/Windows Sync/Xilinx Workspace/Single/test_pc.v
// Project Name: Single
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: program_counter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_pc;
// Inputs
reg clk;
reg [31:0] pc_next;
// Outputs
wire [31:0] pc_now;
// Instantiate the Unit Under Test (UUT)
program_counter uut (
.clk(clk),
.pc_next(pc_next),
.pc_now(pc_now)
);
initial begin
// Initialize Inputs
clk = 0;
pc_next = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
always @* pc_next <= pc_now + 4;
always #10 clk = ~clk;
endmodule
|
//==================================================================================================
// Filename : CORDIC_FSM_v3.v
// Created On : 2016-10-03 15:59:21
// Last Modified : 2016-10-28 22:39:59
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description : CORDIC's FSM Unit
//
//
//==================================================================================================
`timescale 1ns / 1ps
module CORDIC_FSM_v3
(
//Input Signals
input wire clk, // Reloj del sitema.
input wire reset, // Reset del sitema.
input wire beg_FSM_CORDIC, // Señal de inicio de la maquina de estados.
input wire ACK_FSM_CORDIC, // Señal proveniente del modulo que recibe el resultado, indicado que el dato ha sido recibido.
input wire exception,
input wire max_tick_iter, // Señales que indican la maxima y minima cuenta, respectivamente, en el contador de iteraciones.
input wire max_tick_var, // Señales que indican la maxima y minima cuenta, respectivamente, en el contador de variables.
input wire enab_dff_z,
//Output Signals
//output reg reset_reg_cordic,
output reg ready_CORDIC, // Señal que indica que el calculo CORDIC se ha terminado.
output reg beg_add_subt, // Señal que indica al modulo de suma/resta que inicie su operacion.
output reg enab_cont_iter, // Señales de habilitacion y carga, respectivamente, en el contador de iteraciones.
output reg enab_cont_var, // Señales de habilitacion y carga, respectivamente, en el contador de variables.
output reg enab_RB1, enab_RB2, enab_RB3,
output reg enab_d_ff5_data_out
);
//symbolic state declaration
/*localparam [3:0] est0 = 8'b0000000,
est1 = 8'b0000001,
est2 = 8'b0000010,
est3 = 8'b0000100,
est4 = 8'b0001000,
est5 = 8'b0010000,
est6 = 8'b0100000,
est7 = 8'b1000000;*/
parameter est0 = 8'b00000001;
parameter est1 = 8'b00000010;
parameter est2 = 8'b00000100;
parameter est3 = 8'b00001000;
parameter est4 = 8'b00010000;
parameter est5 = 8'b00100000;
parameter est6 = 8'b01000000;
parameter est7 = 8'b10000000;
//signal declaration
reg [7:0] state_reg, state_next; // Guardan el estado actual y el estado futuro, respectivamente.
//state register
always @( posedge clk, posedge reset)
begin
if(reset) // Si hay reset, el estado actual es el estado inicial.
state_reg <= est0;
else //Si no hay reset el estado actual es igual al estado siguiente.
state_reg <= state_next;
end
//next-state logic and output logic
always @*
begin
state_next = state_reg; // default state : the same
//declaration of default outputs.
// reset_reg_cordic = 0;
enab_RB1 = 0;
enab_RB2 = 0;
enab_RB3 = 0;
enab_cont_var = 0;
enab_cont_iter = 0;
enab_d_ff5_data_out = 0;
ready_CORDIC = 0;
beg_add_subt = 0;
case(state_reg)
est0:
begin
// reset_reg_cordic = 1'b1;
enab_RB1 = 1'b1;
if(beg_FSM_CORDIC) begin
state_next = est1;
end else begin
state_next = est0;
end
end
est1:
begin
enab_RB1 = 1'b1;
state_next = est2;
end
est2:
begin
enab_RB2 = 1'b1;
if(exception) begin
state_next = est0;
end else begin
state_next = est3;
end
end
est3:
begin
enab_RB3 = 1'b1;
state_next = est4;
end
est4:
begin
enab_cont_var = 1'b1; //cont_var++
beg_add_subt = 1'b1;
if (max_tick_var) begin
state_next = est5;
end else begin
state_next = est4;
end
end
est5:
begin
beg_add_subt = 1'b1;
if (enab_dff_z) begin
state_next = est6;
end else begin
state_next = est5;
end
end
est6:
begin
enab_cont_iter = 1'b1; //cont_iter++
enab_cont_var = 1'b1; //rst cont to from 3 to 0
if (max_tick_iter) begin
state_next = est7; //Es la ultima iteracion, por lo tanto, seguimos a la siguiente etapa
enab_d_ff5_data_out = 1;
end else begin
state_next = est2; //Seguir las iteraciones
//
end
end
est7:
begin
ready_CORDIC = 1'b1;
enab_d_ff5_data_out = 1'b1;
if(ACK_FSM_CORDIC) begin
state_next = est0;
end else begin
state_next = est7;
end
end
default :
begin
state_next = est0;
end
endcase
end
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2012 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
/*******************************************************************************
* Generated from core with identifier: xilinx.com:ip:blk_mem_gen:7.2 *
* *
* The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port *
* Block Memory and Single Port Block Memory LogiCOREs, but is not a *
* direct drop-in replacement. It should be used in all new Xilinx *
* designs. The core supports RAM and ROM functions over a wide range of *
* widths and depths. Use this core to generate block memories with *
* symmetric or asymmetric read and write port widths, as well as cores *
* which can perform simultaneous write operations to separate *
* locations, and simultaneous read operations from the same location. *
* For more information on differences in interface and feature support *
* between this core and the Dual Port Block Memory and Single Port *
* Block Memory LogiCOREs, please consult the data sheet. *
*******************************************************************************/
// Synthesized Netlist Wrapper
// This file is provided to wrap around the synthesized netlist (if appropriate)
// Interfaces:
// CLK.ACLK
// AXI4 Interconnect Clock Input
// RST.ARESETN
// AXI4 Interconnect Reset Input
// AXI_SLAVE_S_AXI
// AXI_SLAVE
// AXILite_SLAVE_S_AXI
// AXILite_SLAVE
// BRAM_PORTA
// BRAM_PORTA
// BRAM_PORTB
// BRAM_PORTB
module ram_16x1k_dp (
clka,
ena,
wea,
addra,
dina,
douta,
clkb,
enb,
web,
addrb,
dinb,
doutb
);
input clka;
input ena;
input [1 : 0] wea;
input [9 : 0] addra;
input [15 : 0] dina;
output [15 : 0] douta;
input clkb;
input enb;
input [1 : 0] web;
input [9 : 0] addrb;
input [15 : 0] dinb;
output [15 : 0] doutb;
// WARNING: This file provides a module declaration only, it does not support
// direct instantiation. Please use an instantiation template (VEO) to
// instantiate the IP within a design.
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFBBN_FUNCTIONAL_V
`define SKY130_FD_SC_HS__DFBBN_FUNCTIONAL_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dfb_setdom_pg/sky130_fd_sc_hs__u_dfb_setdom_pg.v"
`celldefine
module sky130_fd_sc_hs__dfbbn (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
// Local signals
wire RESET ;
wire SET ;
wire CLK ;
wire buf_Q ;
wire CLK_N_delayed ;
wire RESET_B_delayed;
wire SET_B_delayed ;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
not not2 (CLK , CLK_N );
sky130_fd_sc_hs__u_dfb_setdom_pg `UNIT_DELAY u_dfb_setdom_pg0 (buf_Q , SET, RESET, CLK, D, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFBBN_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFBBP_BLACKBOX_V
`define SKY130_FD_SC_HD__DFBBP_BLACKBOX_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dfbbp (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFBBP_BLACKBOX_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_pixelq_op_img_cols_V_channel_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_pixelq_op_img_cols_V_channel (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_pixelq_op_img_cols_V_channel_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_pixelq_op_img_cols_V_channel_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: sys_pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
// ************************************************************
//Copyright (C) 2020 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sys_pll (
inclk0,
c0,
c1,
c2,
locked);
input inclk0;
output c0;
output c1;
output c2;
output locked;
wire [0:0] sub_wire2 = 1'h0;
wire [4:0] sub_wire3;
wire sub_wire7;
wire sub_wire0 = inclk0;
wire [1:0] sub_wire1 = {sub_wire2, sub_wire0};
wire [2:2] sub_wire6 = sub_wire3[2:2];
wire [1:1] sub_wire5 = sub_wire3[1:1];
wire [0:0] sub_wire4 = sub_wire3[0:0];
wire c0 = sub_wire4;
wire c1 = sub_wire5;
wire c2 = sub_wire6;
wire locked = sub_wire7;
altpll altpll_component (
.inclk (sub_wire1),
.clk (sub_wire3),
.locked (sub_wire7),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 25,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 2,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 3125,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 1,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 1,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 1,
altpll_component.clk2_phase_shift = "0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone 10 LP",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=sys_pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NO_COMPENSATION",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "ON",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "4.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "0.016000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "50.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "4.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "0.01600000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "50.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "sys_pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "25"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3125"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone 10 LP"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sys_pll_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:06:40 03/19/2011
// Design Name:
// Module Name: jace_en_fpga
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module fpga_ace (
input wire clkram,
input wire clk65,
input wire clkcpu,
input wire reset,
input wire ear,
output wire [7:0] filas,
input wire [4:0] columnas,
output wire video,
output wire hsync,
output wire vsync,
output wire mic,
output wire spk
);
// Los buses del Z80
wire [7:0] DinZ80;
wire [7:0] DoutZ80;
wire [15:0] AZ80;
// Señales de control, direccion y datos de parte de todas las memorias
wire iorq_n, mreq_n, int_n, rd_n, wr_n, wait_n;
wire rom_enable, sram_enable, cram_enable, uram_enable, xram_enable, eram_enable, data_from_jace_oe;
wire [7:0] dout_rom, dout_sram, dout_cram, dout_uram, dout_xram, dout_eram, data_from_jace;
wire [7:0] sram_data, cram_data;
wire [9:0] sram_addr, cram_addr;
// Señales para la implementación de la habilitación de escritura en ROM
wire enable_write_to_rom;
wire [7:0] dout_modulo_enable_write;
wire modulo_enable_write_oe;
// Copia del bus de direcciones para las filas del teclado
assign filas = AZ80[15:8];
// Multiplexor para asignar un valor al bus de datos de entrada del Z80
assign DinZ80 = (rom_enable == 1'b1)? dout_rom :
(sram_enable == 1'b1)? dout_sram :
(cram_enable == 1'b1)? dout_cram :
(uram_enable == 1'b1)? dout_uram :
(xram_enable == 1'b1)? dout_xram :
(eram_enable == 1'b1)? dout_eram :
(modulo_enable_write_oe == 1'b1)? dout_modulo_enable_write :
(data_from_jace_oe == 1'b1)? data_from_jace :
sram_data | cram_data; // By default, this is what the data bus sees
// Memoria del equipo
ram1k_dualport sram (
.clk(clkram),
.ce(sram_enable),
.a1(AZ80[9:0]),
.a2(sram_addr),
.din(DoutZ80),
.dout1(dout_sram),
.dout2(sram_data),
.we(~wr_n)
);
ram1k_dualport cram (
.clk(clkram),
.ce(cram_enable),
.a1(AZ80[9:0]),
.a2(cram_addr),
.din(DoutZ80),
.dout1(dout_cram),
.dout2(cram_data),
.we(~wr_n)
);
ram1k uram(
.clk(clkram),
.ce(uram_enable),
.a(AZ80[9:0]),
.din(DoutZ80),
.dout(dout_uram),
.we(~wr_n)
);
ram16k xram(
.clk(clkram),
.ce(xram_enable),
.a(AZ80[13:0]),
.din(DoutZ80),
.dout(dout_xram),
.we(~wr_n)
);
ram32k eram(
.clk(clkram),
.ce(eram_enable),
.a(AZ80[14:0]),
.din(DoutZ80),
.dout(dout_eram),
.we(~wr_n)
);
/* La ROM */
rom the_rom(
.clk(clkram),
.ce(rom_enable),
.a(AZ80[12:0]),
.din(DoutZ80),
.dout(dout_rom),
.we(~wr_n & enable_write_to_rom)
);
/* La CPU */
tv80n cpu(
// Outputs
.m1_n(), .mreq_n(mreq_n), .iorq_n(iorq_n), .rd_n(rd_n), .wr_n(wr_n), .rfsh_n(), .halt_n(), .busak_n(), .A(AZ80), .do(DoutZ80),
// Inputs
.di(DinZ80), .reset_n(reset), .clk(clkcpu), .wait_n(wait_n), .int_n(int_n), .nmi_n(1'b1), .busrq_n(1'b1)
);
jace_logic todo_lo_demas (
.clk(clk65),
// CPU interface
.cpu_addr(AZ80),
.mreq_n(mreq_n),
.iorq_n(iorq_n),
.rd_n(rd_n),
.wr_n(wr_n),
.data_from_cpu(DoutZ80),
.data_to_cpu(data_from_jace),
.data_to_cpu_oe(data_from_jace_oe),
.wait_n(wait_n),
.int_n(int_n),
// CPU-RAM interface
.rom_enable(rom_enable),
.sram_enable(sram_enable),
.cram_enable(cram_enable),
.uram_enable(uram_enable),
.xram_enable(xram_enable),
.eram_enable(eram_enable),
// Screen RAM and Char RAM interface
.screen_addr(sram_addr),
.screen_data(sram_data),
.char_addr(cram_addr),
.char_data(cram_data),
// Devices
.kbdcols(columnas),
.ear(ear),
.spk(spk),
.mic(mic),
.video(video),
.hsync_pal(hsync),
.vsync_pal(vsync)
);
io_write_to_rom modulo_habilitador_escrituras (
.clk(clk65),
.a(AZ80),
.iorq_n(iorq_n),
.rd_n(rd_n),
.wr_n(wr_n),
.din(DoutZ80),
.dout(dout_modulo_enable_write),
.dout_oe(modulo_enable_write_oe),
.enable_write_to_rom(enable_write_to_rom)
);
endmodule
|
// system_mm_interconnect_1.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.0 200 at 2015.04.26.20:39:47
`timescale 1 ps / 1 ps
module system_mm_interconnect_1 (
input wire acl_iface_kernel_clk_clk, // acl_iface_kernel_clk.clk
input wire cra_root_reset_reset_bridge_in_reset_reset, // cra_root_reset_reset_bridge_in_reset.reset
input wire [29:0] acl_iface_kernel_cra_address, // acl_iface_kernel_cra.address
output wire acl_iface_kernel_cra_waitrequest, // .waitrequest
input wire [0:0] acl_iface_kernel_cra_burstcount, // .burstcount
input wire [7:0] acl_iface_kernel_cra_byteenable, // .byteenable
input wire acl_iface_kernel_cra_read, // .read
output wire [63:0] acl_iface_kernel_cra_readdata, // .readdata
output wire acl_iface_kernel_cra_readdatavalid, // .readdatavalid
input wire acl_iface_kernel_cra_write, // .write
input wire [63:0] acl_iface_kernel_cra_writedata, // .writedata
input wire acl_iface_kernel_cra_debugaccess, // .debugaccess
output wire [3:0] cra_root_cra_slave_address, // cra_root_cra_slave.address
output wire cra_root_cra_slave_write, // .write
output wire cra_root_cra_slave_read, // .read
input wire [63:0] cra_root_cra_slave_readdata, // .readdata
output wire [63:0] cra_root_cra_slave_writedata, // .writedata
output wire [7:0] cra_root_cra_slave_byteenable, // .byteenable
input wire cra_root_cra_slave_readdatavalid, // .readdatavalid
input wire cra_root_cra_slave_waitrequest // .waitrequest
);
wire acl_iface_kernel_cra_translator_avalon_universal_master_0_waitrequest; // cra_root_cra_slave_translator:uav_waitrequest -> acl_iface_kernel_cra_translator:uav_waitrequest
wire [3:0] acl_iface_kernel_cra_translator_avalon_universal_master_0_burstcount; // acl_iface_kernel_cra_translator:uav_burstcount -> cra_root_cra_slave_translator:uav_burstcount
wire [63:0] acl_iface_kernel_cra_translator_avalon_universal_master_0_writedata; // acl_iface_kernel_cra_translator:uav_writedata -> cra_root_cra_slave_translator:uav_writedata
wire [29:0] acl_iface_kernel_cra_translator_avalon_universal_master_0_address; // acl_iface_kernel_cra_translator:uav_address -> cra_root_cra_slave_translator:uav_address
wire acl_iface_kernel_cra_translator_avalon_universal_master_0_lock; // acl_iface_kernel_cra_translator:uav_lock -> cra_root_cra_slave_translator:uav_lock
wire acl_iface_kernel_cra_translator_avalon_universal_master_0_write; // acl_iface_kernel_cra_translator:uav_write -> cra_root_cra_slave_translator:uav_write
wire acl_iface_kernel_cra_translator_avalon_universal_master_0_read; // acl_iface_kernel_cra_translator:uav_read -> cra_root_cra_slave_translator:uav_read
wire [63:0] acl_iface_kernel_cra_translator_avalon_universal_master_0_readdata; // cra_root_cra_slave_translator:uav_readdata -> acl_iface_kernel_cra_translator:uav_readdata
wire acl_iface_kernel_cra_translator_avalon_universal_master_0_debugaccess; // acl_iface_kernel_cra_translator:uav_debugaccess -> cra_root_cra_slave_translator:uav_debugaccess
wire [7:0] acl_iface_kernel_cra_translator_avalon_universal_master_0_byteenable; // acl_iface_kernel_cra_translator:uav_byteenable -> cra_root_cra_slave_translator:uav_byteenable
wire acl_iface_kernel_cra_translator_avalon_universal_master_0_readdatavalid; // cra_root_cra_slave_translator:uav_readdatavalid -> acl_iface_kernel_cra_translator:uav_readdatavalid
altera_merlin_master_translator #(
.AV_ADDRESS_W (30),
.AV_DATA_W (64),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (4),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) acl_iface_kernel_cra_translator (
.clk (acl_iface_kernel_clk_clk), // clk.clk
.reset (cra_root_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (acl_iface_kernel_cra_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (acl_iface_kernel_cra_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (acl_iface_kernel_cra_translator_avalon_universal_master_0_read), // .read
.uav_write (acl_iface_kernel_cra_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (acl_iface_kernel_cra_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (acl_iface_kernel_cra_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (acl_iface_kernel_cra_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (acl_iface_kernel_cra_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (acl_iface_kernel_cra_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (acl_iface_kernel_cra_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (acl_iface_kernel_cra_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (acl_iface_kernel_cra_address), // avalon_anti_master_0.address
.av_waitrequest (acl_iface_kernel_cra_waitrequest), // .waitrequest
.av_burstcount (acl_iface_kernel_cra_burstcount), // .burstcount
.av_byteenable (acl_iface_kernel_cra_byteenable), // .byteenable
.av_read (acl_iface_kernel_cra_read), // .read
.av_readdata (acl_iface_kernel_cra_readdata), // .readdata
.av_readdatavalid (acl_iface_kernel_cra_readdatavalid), // .readdatavalid
.av_write (acl_iface_kernel_cra_write), // .write
.av_writedata (acl_iface_kernel_cra_writedata), // .writedata
.av_debugaccess (acl_iface_kernel_cra_debugaccess), // .debugaccess
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (4),
.AV_DATA_W (64),
.UAV_DATA_W (64),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (8),
.UAV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (4),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) cra_root_cra_slave_translator (
.clk (acl_iface_kernel_clk_clk), // clk.clk
.reset (cra_root_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (acl_iface_kernel_cra_translator_avalon_universal_master_0_address), // avalon_universal_slave_0.address
.uav_burstcount (acl_iface_kernel_cra_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (acl_iface_kernel_cra_translator_avalon_universal_master_0_read), // .read
.uav_write (acl_iface_kernel_cra_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (acl_iface_kernel_cra_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (acl_iface_kernel_cra_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (acl_iface_kernel_cra_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (acl_iface_kernel_cra_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (acl_iface_kernel_cra_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (acl_iface_kernel_cra_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (acl_iface_kernel_cra_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (cra_root_cra_slave_address), // avalon_anti_slave_0.address
.av_write (cra_root_cra_slave_write), // .write
.av_read (cra_root_cra_slave_read), // .read
.av_readdata (cra_root_cra_slave_readdata), // .readdata
.av_writedata (cra_root_cra_slave_writedata), // .writedata
.av_byteenable (cra_root_cra_slave_byteenable), // .byteenable
.av_readdatavalid (cra_root_cra_slave_readdatavalid), // .readdatavalid
.av_waitrequest (cra_root_cra_slave_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2009 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file spartan6_pmem.v when simulating
// the core, spartan6_pmem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module spartan6_pmem(
clka,
ena,
wea,
addra,
dina,
douta);
input clka;
input ena;
input [1 : 0] wea;
input [11 : 0] addra;
input [15 : 0] dina;
output [15 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V3_3 #(
.C_ADDRA_WIDTH(12),
.C_ADDRB_WIDTH(12),
.C_ALGORITHM(1),
.C_BYTE_SIZE(8),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan6"),
.C_HAS_ENA(1),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(4096),
.C_READ_DEPTH_B(4096),
.C_READ_WIDTH_A(16),
.C_READ_WIDTH_B(16),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(1),
.C_USE_BYTE_WEB(1),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_WEA_WIDTH(2),
.C_WEB_WIDTH(2),
.C_WRITE_DEPTH_A(4096),
.C_WRITE_DEPTH_B(4096),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_WRITE_WIDTH_B(16),
.C_XDEVICEFAMILY("spartan6"))
inst (
.CLKA(clka),
.ENA(ena),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.RSTA(),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of spartan6_pmem is "black_box"
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A22OI_PP_SYMBOL_V
`define SKY130_FD_SC_MS__A22OI_PP_SYMBOL_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a22oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A22OI_PP_SYMBOL_V
|
(* -*- coding: utf-8; coq-prog-args: ("-coqlib" "../.." "-R" ".." "Coq" "-top" "Coq.Classes.CMorphisms") -*- *)
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2018 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(** * Typeclass-based morphism definition and standard, minimal instances
Author: Matthieu Sozeau
Institution: LRI, CNRS UMR 8623 - University Paris Sud
*)
Require Import Coq.Program.Basics.
Require Import Coq.Program.Tactics.
Require Export Coq.Classes.CRelationClasses.
Generalizable Variables A eqA B C D R RA RB RC m f x y.
Local Obligation Tactic := simpl_crelation.
Set Universe Polymorphism.
(** * Morphisms.
We now turn to the definition of [Proper] and declare standard instances.
These will be used by the [setoid_rewrite] tactic later. *)
(** A morphism for a relation [R] is a proper element of the relation.
The relation [R] will be instantiated by [respectful] and [A] by an arrow
type for usual morphisms. *)
Section Proper.
Context {A : Type}.
Class Proper (R : crelation A) (m : A) :=
proper_prf : R m m.
(** Every element in the carrier of a reflexive relation is a morphism
for this relation. We use a proxy class for this case which is used
internally to discharge reflexivity constraints. The [Reflexive]
instance will almost always be used, but it won't apply in general to
any kind of [Proper (A -> B) _ _] goal, making proof-search much
slower. A cleaner solution would be to be able to set different
priorities in different hint bases and select a particular hint
database for resolution of a type class constraint. *)
Class ProperProxy (R : crelation A) (m : A) :=
proper_proxy : R m m.
Lemma eq_proper_proxy (x : A) : ProperProxy (@eq A) x.
Proof. firstorder. Qed.
Lemma reflexive_proper_proxy `(Reflexive A R) (x : A) : ProperProxy R x.
Proof. firstorder. Qed.
Lemma proper_proper_proxy x `(Proper R x) : ProperProxy R x.
Proof. firstorder. Qed.
(** Respectful morphisms. *)
(** The fully dependent version, not used yet. *)
Definition respectful_hetero
(A B : Type)
(C : A -> Type) (D : B -> Type)
(R : A -> B -> Type)
(R' : forall (x : A) (y : B), C x -> D y -> Type) :
(forall x : A, C x) -> (forall x : B, D x) -> Type :=
fun f g => forall x y, R x y -> R' x y (f x) (g y).
(** The non-dependent version is an instance where we forget dependencies. *)
Definition respectful {B} (R : crelation A) (R' : crelation B) : crelation (A -> B) :=
Eval compute in @respectful_hetero A A (fun _ => B) (fun _ => B) R (fun _ _ => R').
End Proper.
(** We favor the use of Leibniz equality or a declared reflexive crelation
when resolving [ProperProxy], otherwise, if the crelation is given (not an evar),
we fall back to [Proper]. *)
Hint Extern 1 (ProperProxy _ _) =>
class_apply @eq_proper_proxy || class_apply @reflexive_proper_proxy : typeclass_instances.
Hint Extern 2 (ProperProxy ?R _) =>
not_evar R; class_apply @proper_proper_proxy : typeclass_instances.
(** Notations reminiscent of the old syntax for declaring morphisms. *)
Delimit Scope signature_scope with signature.
Module ProperNotations.
Notation " R ++> R' " := (@respectful _ _ (R%signature) (R'%signature))
(right associativity, at level 55) : signature_scope.
Notation " R ==> R' " := (@respectful _ _ (R%signature) (R'%signature))
(right associativity, at level 55) : signature_scope.
Notation " R --> R' " := (@respectful _ _ (flip (R%signature)) (R'%signature))
(right associativity, at level 55) : signature_scope.
End ProperNotations.
Arguments Proper {A}%type R%signature m.
Arguments respectful {A B}%type (R R')%signature _ _.
Export ProperNotations.
Local Open Scope signature_scope.
(** [solve_proper] try to solve the goal [Proper (?==> ... ==>?) f]
by repeated introductions and setoid rewrites. It should work
fine when [f] is a combination of already known morphisms and
quantifiers. *)
Ltac solve_respectful t :=
match goal with
| |- respectful _ _ _ _ =>
let H := fresh "H" in
intros ? ? H; solve_respectful ltac:(setoid_rewrite H; t)
| _ => t; reflexivity
end.
Ltac solve_proper := unfold Proper; solve_respectful ltac:(idtac).
(** [f_equiv] is a clone of [f_equal] that handles setoid equivalences.
For example, if we know that [f] is a morphism for [E1==>E2==>E],
then the goal [E (f x y) (f x' y')] will be transformed by [f_equiv]
into the subgoals [E1 x x'] and [E2 y y'].
*)
Ltac f_equiv :=
match goal with
| |- ?R (?f ?x) (?f' _) =>
let T := type of x in
let Rx := fresh "R" in
evar (Rx : crelation T);
let H := fresh in
assert (H : (Rx==>R)%signature f f');
unfold Rx in *; clear Rx; [ f_equiv | apply H; clear H; try reflexivity ]
| |- ?R ?f ?f' =>
solve [change (Proper R f); eauto with typeclass_instances | reflexivity ]
| _ => idtac
end.
Section Relations.
Context {A : Type}.
(** [forall_def] reifies the dependent product as a definition. *)
Definition forall_def (P : A -> Type) : Type := forall x : A, P x.
(** Dependent pointwise lifting of a crelation on the range. *)
Definition forall_relation (P : A -> Type)
(sig : forall a, crelation (P a)) : crelation (forall x, P x) :=
fun f g => forall a, sig a (f a) (g a).
(** Non-dependent pointwise lifting *)
Definition pointwise_relation {B} (R : crelation B) : crelation (A -> B) :=
fun f g => forall a, R (f a) (g a).
Lemma pointwise_pointwise {B} (R : crelation B) :
relation_equivalence (pointwise_relation R) (@eq A ==> R).
Proof. intros. split. simpl_crelation. firstorder. Qed.
(** Subcrelations induce a morphism on the identity. *)
Global Instance subrelation_id_proper `(subrelation A RA RA') : Proper (RA ==> RA') id.
Proof. firstorder. Qed.
(** The subrelation property goes through products as usual. *)
Lemma subrelation_respectful `(subl : subrelation A RA' RA, subr : subrelation B RB RB') :
subrelation (RA ==> RB) (RA' ==> RB').
Proof. simpl_crelation. Qed.
(** And of course it is reflexive. *)
Lemma subrelation_refl R : @subrelation A R R.
Proof. simpl_crelation. Qed.
(** [Proper] is itself a covariant morphism for [subrelation].
We use an unconvertible premise to avoid looping.
*)
Lemma subrelation_proper `(mor : Proper A R' m)
`(unc : Unconvertible (crelation A) R R')
`(sub : subrelation A R' R) : Proper R m.
Proof.
intros. apply sub. apply mor.
Qed.
Global Instance proper_subrelation_proper_arrow :
Proper (subrelation ++> eq ==> arrow) (@Proper A).
Proof. reduce. subst. firstorder. Qed.
Global Instance pointwise_subrelation `(sub : subrelation B R R') :
subrelation (pointwise_relation R) (pointwise_relation R') | 4.
Proof. reduce. unfold pointwise_relation in *. apply sub. auto. Qed.
(** For dependent function types. *)
Lemma forall_subrelation (P : A -> Type) (R S : forall x : A, crelation (P x)) :
(forall a, subrelation (R a) (S a)) ->
subrelation (forall_relation P R) (forall_relation P S).
Proof. reduce. firstorder. Qed.
End Relations.
Typeclasses Opaque respectful pointwise_relation forall_relation.
Arguments forall_relation {A P}%type sig%signature _ _.
Arguments pointwise_relation A%type {B}%type R%signature _ _.
Hint Unfold Reflexive : core.
Hint Unfold Symmetric : core.
Hint Unfold Transitive : core.
(** Resolution with subrelation: favor decomposing products over applying reflexivity
for unconstrained goals. *)
Ltac subrelation_tac T U :=
(is_ground T ; is_ground U ; class_apply @subrelation_refl) ||
class_apply @subrelation_respectful || class_apply @subrelation_refl.
Hint Extern 3 (@subrelation _ ?T ?U) => subrelation_tac T U : typeclass_instances.
CoInductive apply_subrelation : Prop := do_subrelation.
Ltac proper_subrelation :=
match goal with
[ H : apply_subrelation |- _ ] => clear H ; class_apply @subrelation_proper
end.
Hint Extern 5 (@Proper _ ?H _) => proper_subrelation : typeclass_instances.
(** Essential subrelation instances for [iff], [impl] and [pointwise_relation]. *)
Instance iff_impl_subrelation : subrelation iff impl | 2.
Proof. firstorder. Qed.
Instance iff_flip_impl_subrelation : subrelation iff (flip impl) | 2.
Proof. firstorder. Qed.
(** Essential subrelation instances for [iffT] and [arrow]. *)
Instance iffT_arrow_subrelation : subrelation iffT arrow | 2.
Proof. firstorder. Qed.
Instance iffT_flip_arrow_subrelation : subrelation iffT (flip arrow) | 2.
Proof. firstorder. Qed.
(** We use an extern hint to help unification. *)
Hint Extern 4 (subrelation (@forall_relation ?A ?B ?R) (@forall_relation _ _ ?S)) =>
apply (@forall_subrelation A B R S) ; intro : typeclass_instances.
Section GenericInstances.
(* Share universes *)
Implicit Types A B C : Type.
(** We can build a PER on the Coq function space if we have PERs on the domain and
codomain. *)
Program Instance respectful_per `(PER A R, PER B R') : PER (R ==> R').
Next Obligation.
Proof with auto.
assert(R x0 x0).
transitivity y0... symmetry...
transitivity (y x0)...
Qed.
Unset Strict Universe Declaration.
(** The complement of a crelation conserves its proper elements. *)
(** The [flip] too, actually the [flip] instance is a bit more general. *)
Program Definition flip_proper
`(mor : Proper (A -> B -> C) (RA ==> RB ==> RC) f) :
Proper (RB ==> RA ==> RC) (flip f) := _.
Next Obligation.
Proof.
apply mor ; auto.
Qed.
(** Every Transitive crelation gives rise to a binary morphism on [impl],
contravariant in the first argument, covariant in the second. *)
Global Program
Instance trans_contra_co_type_morphism
`(Transitive A R) : Proper (R --> R ++> arrow) R.
Next Obligation.
Proof with auto.
transitivity x...
transitivity x0...
Qed.
(** Proper declarations for partial applications. *)
Global Program
Instance trans_contra_inv_impl_type_morphism
`(Transitive A R) : Proper (R --> flip arrow) (R x) | 3.
Next Obligation.
Proof with auto.
transitivity y...
Qed.
Global Program
Instance trans_co_impl_type_morphism
`(Transitive A R) : Proper (R ++> arrow) (R x) | 3.
Next Obligation.
Proof with auto.
transitivity x0...
Qed.
Global Program
Instance trans_sym_co_inv_impl_type_morphism
`(PER A R) : Proper (R ++> flip arrow) (R x) | 3.
Next Obligation.
Proof with auto.
transitivity y... symmetry...
Qed.
Global Program Instance trans_sym_contra_arrow_morphism
`(PER A R) : Proper (R --> arrow) (R x) | 3.
Next Obligation.
Proof with auto.
transitivity x0... symmetry...
Qed.
Global Program Instance per_partial_app_type_morphism
`(PER A R) : Proper (R ==> iffT) (R x) | 2.
Next Obligation.
Proof with auto.
split. intros ; transitivity x0...
intros.
transitivity y...
symmetry...
Qed.
(** Every Transitive crelation induces a morphism by "pushing" an [R x y] on the left of an [R x z] proof to get an [R y z] goal. *)
Global Program
Instance trans_co_eq_inv_arrow_morphism
`(Transitive A R) : Proper (R ==> (@eq A) ==> flip arrow) R | 2.
Next Obligation.
Proof with auto.
transitivity y...
Qed.
(** Every Symmetric and Transitive crelation gives rise to an equivariant morphism. *)
Global Program
Instance PER_type_morphism `(PER A R) : Proper (R ==> R ==> iffT) R | 1.
Next Obligation.
Proof with auto.
split ; intros.
transitivity x0... transitivity x... symmetry...
transitivity y... transitivity y0... symmetry...
Qed.
Lemma symmetric_equiv_flip `(Symmetric A R) : relation_equivalence R (flip R).
Proof. firstorder. Qed.
Global Program Instance compose_proper A B C RA RB RC :
Proper ((RB ==> RC) ==> (RA ==> RB) ==> (RA ==> RC)) (@compose A B C).
Next Obligation.
Proof.
simpl_crelation.
unfold compose. firstorder.
Qed.
(** Coq functions are morphisms for Leibniz equality,
applied only if really needed. *)
Global Instance reflexive_eq_dom_reflexive `(Reflexive B R') :
Reflexive (@Logic.eq A ==> R').
Proof. simpl_crelation. Qed.
(** [respectful] is a morphism for crelation equivalence . *)
Global Instance respectful_morphism :
Proper (relation_equivalence ++> relation_equivalence ++> relation_equivalence)
(@respectful A B).
Proof.
intros A B R R' HRR' S S' HSS' f g.
unfold respectful , relation_equivalence in *; simpl in *.
split ; intros H x y Hxy.
apply (fst (HSS' _ _)). apply H. now apply (snd (HRR' _ _)).
apply (snd (HSS' _ _)). apply H. now apply (fst (HRR' _ _)).
Qed.
(** [R] is Reflexive, hence we can build the needed proof. *)
Lemma Reflexive_partial_app_morphism `(Proper (A -> B) (R ==> R') m, ProperProxy A R x) :
Proper R' (m x).
Proof. simpl_crelation. Qed.
Class Params {A} (of : A) (arity : nat).
Lemma flip_respectful {A B} (R : crelation A) (R' : crelation B) :
relation_equivalence (flip (R ==> R')) (flip R ==> flip R').
Proof.
intros.
unfold flip, respectful.
split ; intros ; intuition.
Qed.
(** Treating flip: can't make them direct instances as we
need at least a [flip] present in the goal. *)
Lemma flip1 `(subrelation A R' R) : subrelation (flip (flip R')) R.
Proof. firstorder. Qed.
Lemma flip2 `(subrelation A R R') : subrelation R (flip (flip R')).
Proof. firstorder. Qed.
(** That's if and only if *)
Lemma eq_subrelation `(Reflexive A R) : subrelation (@eq A) R.
Proof. simpl_crelation. Qed.
(** Once we have normalized, we will apply this instance to simplify the problem. *)
Definition proper_flip_proper `(mor : Proper A R m) : Proper (flip R) m := mor.
(** Every reflexive crelation gives rise to a morphism,
only for immediately solving goals without variables. *)
Lemma reflexive_proper `{Reflexive A R} (x : A) : Proper R x.
Proof. firstorder. Qed.
Lemma proper_eq {A} (x : A) : Proper (@eq A) x.
Proof. intros. apply reflexive_proper. Qed.
End GenericInstances.
Class PartialApplication.
CoInductive normalization_done : Prop := did_normalization.
Ltac partial_application_tactic :=
let rec do_partial_apps H m cont :=
match m with
| ?m' ?x => class_apply @Reflexive_partial_app_morphism ;
[(do_partial_apps H m' ltac:(idtac))|clear H]
| _ => cont
end
in
let rec do_partial H ar m :=
match ar with
| 0%nat => do_partial_apps H m ltac:(fail 1)
| S ?n' =>
match m with
?m' ?x => do_partial H n' m'
end
end
in
let params m sk fk :=
(let m' := fresh in head_of_constr m' m ;
let n := fresh in evar (n:nat) ;
let v := eval compute in n in clear n ;
let H := fresh in
assert(H:Params m' v) by typeclasses eauto ;
let v' := eval compute in v in subst m';
(sk H v' || fail 1))
|| fk
in
let on_morphism m cont :=
params m ltac:(fun H n => do_partial H n m)
ltac:(cont)
in
match goal with
| [ _ : normalization_done |- _ ] => fail 1
| [ _ : @Params _ _ _ |- _ ] => fail 1
| [ |- @Proper ?T _ (?m ?x) ] =>
match goal with
| [ H : PartialApplication |- _ ] =>
class_apply @Reflexive_partial_app_morphism; [|clear H]
| _ => on_morphism (m x)
ltac:(class_apply @Reflexive_partial_app_morphism)
end
end.
(** Bootstrap !!! *)
Instance proper_proper : Proper (relation_equivalence ==> eq ==> iffT) (@Proper A).
Proof.
intros A R R' HRR' x y <-. red in HRR'.
split ; red ; intros.
now apply (fst (HRR' _ _)).
now apply (snd (HRR' _ _)).
Qed.
Ltac proper_reflexive :=
match goal with
| [ _ : normalization_done |- _ ] => fail 1
| _ => class_apply proper_eq || class_apply @reflexive_proper
end.
Hint Extern 1 (subrelation (flip _) _) => class_apply @flip1 : typeclass_instances.
Hint Extern 1 (subrelation _ (flip _)) => class_apply @flip2 : typeclass_instances.
(* Hint Extern 1 (Proper _ (complement _)) => apply @complement_proper *)
(* : typeclass_instances. *)
Hint Extern 1 (Proper _ (flip _)) => apply @flip_proper
: typeclass_instances.
Hint Extern 2 (@Proper _ (flip _) _) => class_apply @proper_flip_proper
: typeclass_instances.
Hint Extern 4 (@Proper _ _ _) => partial_application_tactic
: typeclass_instances.
Hint Extern 7 (@Proper _ _ _) => proper_reflexive
: typeclass_instances.
(** Special-purpose class to do normalization of signatures w.r.t. flip. *)
Section Normalize.
Context (A : Type).
Class Normalizes (m : crelation A) (m' : crelation A) :=
normalizes : relation_equivalence m m'.
(** Current strategy: add [flip] everywhere and reduce using [subrelation]
afterwards. *)
Lemma proper_normalizes_proper `(Normalizes R0 R1, Proper A R1 m) : Proper R0 m.
Proof.
red in H, H0. red in H.
apply (snd (H _ _)).
assumption.
Qed.
Lemma flip_atom R : Normalizes R (flip (flip R)).
Proof.
firstorder.
Qed.
End Normalize.
Lemma flip_arrow `(NA : Normalizes A R (flip R'''), NB : Normalizes B R' (flip R'')) :
Normalizes (A -> B) (R ==> R') (flip (R''' ==> R'')%signature).
Proof.
unfold Normalizes in *. intros.
rewrite NA, NB. firstorder.
Qed.
Ltac normalizes :=
match goal with
| [ |- Normalizes _ (respectful _ _) _ ] => class_apply @flip_arrow
| _ => class_apply @flip_atom
end.
Ltac proper_normalization :=
match goal with
| [ _ : normalization_done |- _ ] => fail 1
| [ _ : apply_subrelation |- @Proper _ ?R _ ] =>
let H := fresh "H" in
set(H:=did_normalization) ; class_apply @proper_normalizes_proper
end.
Hint Extern 1 (Normalizes _ _ _) => normalizes : typeclass_instances.
Hint Extern 6 (@Proper _ _ _) => proper_normalization
: typeclass_instances.
(** When the crelation on the domain is symmetric, we can
flip the crelation on the codomain. Same for binary functions. *)
Lemma proper_sym_flip :
forall `(Symmetric A R1)`(Proper (A->B) (R1==>R2) f),
Proper (R1==>flip R2) f.
Proof.
intros A R1 Sym B R2 f Hf.
intros x x' Hxx'. apply Hf, Sym, Hxx'.
Qed.
Lemma proper_sym_flip_2 :
forall `(Symmetric A R1)`(Symmetric B R2)`(Proper (A->B->C) (R1==>R2==>R3) f),
Proper (R1==>R2==>flip R3) f.
Proof.
intros A R1 Sym1 B R2 Sym2 C R3 f Hf.
intros x x' Hxx' y y' Hyy'. apply Hf; auto.
Qed.
(** When the crelation on the domain is symmetric, a predicate is
compatible with [iff] as soon as it is compatible with [impl].
Same with a binary crelation. *)
Lemma proper_sym_impl_iff : forall `(Symmetric A R)`(Proper _ (R==>impl) f),
Proper (R==>iff) f.
Proof.
intros A R Sym f Hf x x' Hxx'. repeat red in Hf. split; eauto.
Qed.
Lemma proper_sym_arrow_iffT : forall `(Symmetric A R)`(Proper _ (R==>arrow) f),
Proper (R==>iffT) f.
Proof.
intros A R Sym f Hf x x' Hxx'. repeat red in Hf. split; eauto.
Qed.
Lemma proper_sym_impl_iff_2 :
forall `(Symmetric A R)`(Symmetric B R')`(Proper _ (R==>R'==>impl) f),
Proper (R==>R'==>iff) f.
Proof.
intros A R Sym B R' Sym' f Hf x x' Hxx' y y' Hyy'.
repeat red in Hf. split; eauto.
Qed.
Lemma proper_sym_arrow_iffT_2 :
forall `(Symmetric A R)`(Symmetric B R')`(Proper _ (R==>R'==>arrow) f),
Proper (R==>R'==>iffT) f.
Proof.
intros A R Sym B R' Sym' f Hf x x' Hxx' y y' Hyy'.
repeat red in Hf. split; eauto.
Qed.
(** A [PartialOrder] is compatible with its underlying equivalence. *)
Require Import Relation_Definitions.
Instance PartialOrder_proper_type `(PartialOrder A eqA R) :
Proper (eqA==>eqA==>iffT) R.
Proof.
intros.
apply proper_sym_arrow_iffT_2; auto with *.
intros x x' Hx y y' Hy Hr.
transitivity x.
generalize (partial_order_equivalence x x'); compute; intuition.
transitivity y; auto.
generalize (partial_order_equivalence y y'); compute; intuition.
Qed.
(** From a [PartialOrder] to the corresponding [StrictOrder]:
[lt = le /\ ~eq].
If the order is total, we could also say [gt = ~le]. *)
Lemma PartialOrder_StrictOrder `(PartialOrder A eqA R) :
StrictOrder (relation_conjunction R (complement eqA)).
Proof.
split; compute.
intros x (_,Hx). apply Hx, Equivalence_Reflexive.
intros x y z (Hxy,Hxy') (Hyz,Hyz'). split.
apply PreOrder_Transitive with y; assumption.
intro Hxz.
apply Hxy'.
apply partial_order_antisym; auto.
rewrite Hxz. auto.
Qed.
(** From a [StrictOrder] to the corresponding [PartialOrder]:
[le = lt \/ eq].
If the order is total, we could also say [ge = ~lt]. *)
Lemma StrictOrder_PreOrder
`(Equivalence A eqA, StrictOrder A R, Proper _ (eqA==>eqA==>iffT) R) :
PreOrder (relation_disjunction R eqA).
Proof.
split.
intros x. right. reflexivity.
intros x y z [Hxy|Hxy] [Hyz|Hyz].
left. transitivity y; auto.
left. rewrite <- Hyz; auto.
left. rewrite Hxy; auto.
right. transitivity y; auto.
Qed.
Hint Extern 4 (PreOrder (relation_disjunction _ _)) =>
class_apply StrictOrder_PreOrder : typeclass_instances.
Lemma StrictOrder_PartialOrder
`(Equivalence A eqA, StrictOrder A R, Proper _ (eqA==>eqA==>iffT) R) :
PartialOrder eqA (relation_disjunction R eqA).
Proof.
intros. intros x y. compute. intuition.
elim (StrictOrder_Irreflexive x).
transitivity y; auto.
Qed.
Hint Extern 4 (StrictOrder (relation_conjunction _ _)) =>
class_apply PartialOrder_StrictOrder : typeclass_instances.
Hint Extern 4 (PartialOrder _ (relation_disjunction _ _)) =>
class_apply StrictOrder_PartialOrder : typeclass_instances.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O221A_2_V
`define SKY130_FD_SC_LP__O221A_2_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog wrapper for o221a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o221a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o221a_2 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o221a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o221a_2 (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o221a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O221A_2_V
|
/* Memory mapped modules */
// Generate 25.00MHz
reg [1:0] clkdiv; // divider
always @(posedge sys_clk_in)
begin
case (clkdiv)
2'b11: clkdiv <= 2'b10;
2'b10: clkdiv <= 2'b00;
2'b00: clkdiv <= 2'b01;
2'b01: clkdiv <= 2'b11;
endcase
end
assign clk = clkdiv[1];
// Bi-directional SRAM data pins
wire [15:0] sram_in;
wire [15:0] sram_out;
wire data_we;
wire sram_vga_busy;
wire [2:0] rgb;
// AMBER: #ffff33
assign red=rgb[1]?4'he:4'b0;
assign green=rgb[0]?4'he:4'b0;
assign blue=rgb[2]?4'h3:4'b0;
SB_IO
#(
.PIN_TYPE(6'b 1010_01)
)
sram_data_pins [15:0]
(
.PACKAGE_PIN(DAT),
.OUTPUT_ENABLE(data_we_cpu),
.D_OUT_0(sram_out),
.D_IN_0(sram_in)
);
assign RAMCS_b = 1'b0;
assign RAMOE_b = !data_we;
assign RAMWE_b = (data_we);
assign RAMUB_b = 1'b0;
assign RAMLB_b = 1'b0;
wire [17:0] sram_adr_vga;
wire [17:0] sram_adr_cpu;
assign ADR = grant_vga?sram_adr_vga:grant_cpu?sram_adr_cpu:0;
wire data_we_cpu;
assign data_we = grant_vga?1:(!data_we_cpu);
wire data_rq_cpu;
wire data_rq_vga;
wire grant_cpu;
wire grant_vga;
arbiter arb1 (.clk(clk),
.rst(!rst),
.req0(data_rq_cpu),
.req1(data_rq_vga),
.req2(0), .req3(0),
.gnt0(grant_cpu),
.gnt1(grant_vga),
.gnt2(gnt2_),
.gnt3(gnt3_));
wire vgaenable;
vga640x480ice vga1 (.clk(clk),
.clk25mhz(clk),
.rst(vgaenable),
.sram_adr_vga(sram_adr_vga),
.sram_in(sram_in),
.data_rq_vga(data_rq_vga),
.grant_vga(grant_vga),
.hsync(hsync),
.vsync(vsync),
.rgb(rgb));
reg [9:0] reset_counter = 0;
reg hard_reset = 0;
always @(posedge clk) if (!hard_reset) begin
reset_counter <= reset_counter + 1;
if (reset_counter[9]) hard_reset <= 1;
end
assign rst = hard_reset;
wire [3:0] LED;
wire [3:0] LEDr;
outpin led0 (.clk(clk), .we(1'b1), .pin(LED1), .wd(LED[0]), .rd(LEDr[0]));
outpin led1 (.clk(clk), .we(1'b1), .pin(LED2), .wd(LED[1]), .rd(LEDr[1]));
outpin led2 (.clk(clk), .we(1'b1), .pin(LED3), .wd(LED[2]), .rd(LEDr[2]));
outpin led3 (.clk(clk), .we(1'b1), .pin(LED4), .wd(LED[3]), .rd(LEDr[3]));
ledwriter ledwr1 (.clk(clk),
.rst(rst),
.LED(LED),
.addr_b(ram_addr_in_b),
.data_b_in(ram_data_out_b),
.data_b_we(ram_we_out));
wire [31:0] data_bus_in_uart;
wire data_bus_strobe_uart;
`ifdef ENABLE_UART
uartmm uart1(.clk(clk),
.rst(rst),
.TX(TX),
.RX(RX),
.data_b(data_bus_in_uart),
.addr_b(ram_addr_in_b),
.strobe_b(data_bus_strobe_uart),
.data_b_in(ram_data_out_b),
.data_b_we(ram_we_out)
);
`else // !`ifdef ENABLE_UART
assign data_bus_strobe_uart = 0;
`endif // !`ifdef ENABLE_UART
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_b2g #(
parameter DATA_WIDTH = 8) (
input [DATA_WIDTH-1:0] din,
output [DATA_WIDTH-1:0] dout);
function [DATA_WIDTH-1:0] b2g;
input [DATA_WIDTH-1:0] b;
integer i;
begin
b2g[DATA_WIDTH-1] = b[DATA_WIDTH-1];
for (i = DATA_WIDTH-1; i > 0; i = i -1) begin
b2g[i-1] = b[i] ^ b[i-1];
end
end
endfunction
assign dout = b2g(din);
endmodule
|
`include "bsg_defines.v"
`include "config_defs.v"
module config_snooper_bind
(input clk, // this reflects the destiniation domain clock
input [data_max_bits_lp - 1 : 0] id_o,
input [data_max_bits_lp - 1 : 0] data_o);
logic [data_max_bits_lp - 1 : 0] id_o_r, id_o_n;
logic [data_max_bits_lp - 1 : 0] data_o_r, data_o_n;
logic [id_width_lp - 1 : 0] id_o_ref;
logic [data_max_bits_lp - 1 : 0] data_o_ref;
integer test_file;
integer rt, ch;
integer has_reset = 0;
integer node_id = -1;
integer test_sets = -1;
integer node_id_found = 0;
integer restart_pos; // start position of valid references
integer errors = 0;
initial
begin: initial_open_file
if ($test$plusargs("config-snooper-bind")) begin
test_file = $fopen("config_test.in", "r"); // open config_probe.in file to read
end else begin
test_file = 0;
end
if (!test_file) begin
disable initial_open_file;
end
id_o_ref = '0;
data_o_ref = '0; // need initialization to get rid of Lint warning about never assigning variables
ch = $fgetc(test_file);
while(ch != -1) begin // end of file
if ( (ch == "#") || (ch == " ") ) begin // comments, and white spaces are skipped
rt = $ungetc(ch, test_file);
while ( (ch != "\n") && (ch != -1) ) begin // dump chars until the end of this line
ch = $fgetc(test_file);
end
end else if (ch == "\n") begin // empty newlines are also skipped
ch = $fgetc(test_file);
continue;
end else begin
rt = $ungetc(ch, test_file);
restart_pos = $ftell(test_file); // bookmark the test_file position
rt = $fscanf(test_file, "%d\t\t%b\n", id_o_ref, data_o_ref);
break; // to be continued from here
end
ch = $fgetc(test_file);
end
end
assign id_o_n = id_o;
assign data_o_n = data_o;
always @ (posedge clk) begin
id_o_r <= id_o_n;
data_o_r <= data_o_n;
end
// Since the design is synchronized to posedge of clk, using negedge clk
// here is to allow all flip-flops become stable in the register connected
// to data_o. This might guarantee simulation correct even at gate level,
// when all flip-flops don't necessarily change at the same time.
always @ (negedge clk)
begin: always_check_change
if (test_file) begin
if (has_reset == 0) begin // reset value check
if (data_o === '0) begin
$display("\n @time %0d: \t snooper node data_o reset to %b", $time, data_o);
has_reset = 1;
end
end else begin
if ( (id_o !== id_o_r) || (data_o !== data_o_r) ) begin
$display("\n @time %0d: \t snooped id, tag, and data changed to %d, %b, %b", $time, id_o[0 +: id_width_lp], id_o[id_width_lp +: id_tag_bits_lp], data_o);
if (data_o !== data_o_ref) begin
$display("\n @time %0d: \t ERROR snooped data_o = %b <-> expected = %b", $time, data_o, data_o_ref);
errors += 1;
end
if (id_o[0 +: id_width_lp] !== id_o_ref) begin
$display("\n @time %0d: \t ERROR snooped id_o = %d <-> expected = %d", $time, id_o[0 +: id_width_lp], id_o_ref);
errors += 1;
end
ch = $fgetc(test_file);
if (ch == -1) begin // end of file
if ($test$plusargs("cyclic-test")) begin
rt = $fseek(test_file, restart_pos, 0); // circulate
rt = $fscanf(test_file, "%d\t\t%b\n", id_o_ref, data_o_ref);
has_reset = 0;
end
end else begin
rt = $ungetc(ch, test_file);
rt = $fscanf(test_file, "%d\t\t%b\n", id_o_ref, data_o_ref);
end
end
end
end else begin
disable always_check_change;
end
end
final
begin: final_statistics
if (test_file) begin
if (has_reset == 0) begin
$display("### FAILED: Snooper node has not reset properly!\n");
end else begin
if (errors != 0) begin
$display("### FAILED: Snooper node has detected at least %0d wrong packet(s)!\n", errors);
end else begin
$display("### PASSED: Snooper node is probably working properly.\n");
end
end
$fclose(test_file);
end else begin
disable final_statistics;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__PROBE_P_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__PROBE_P_PP_SYMBOL_V
/**
* probe_p: Virtual voltage probe point.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__probe_p (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__PROBE_P_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFBBP_1_V
`define SKY130_FD_SC_HD__DFBBP_1_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Verilog wrapper for dfbbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dfbbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dfbbp_1 (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dfbbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK(CLK),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dfbbp_1 (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dfbbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK(CLK),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFBBP_1_V
|
/*
** -----------------------------------------------------------------------------**
** csconvert_mono.v
**
** Monochrome and JP4 modules inplace of color converter ones
**
** Copyright (C) 2008 Elphel, Inc
**
** -----------------------------------------------------------------------------**
** This file is part of X353
** X333 is free software - hardware description language (HDL) code.
**
** This program is free software: you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation, either version 3 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program. If not, see <http://www.gnu.org/licenses/>.
** -----------------------------------------------------------------------------**
**
*/
module csconvert_mono (en,
clk,
din,
pre_first_in,
y_out,
yaddr,
ywe,
pre_first_out);
input en;
input clk; // clock
input [7:0] din; // input data in scanline sequence
input pre_first_in; // marks the first input pixel
output [7:0] y_out; // output Y (16x16) in scanline sequence. Valid if ys active
output [7:0] yaddr; // address for the external buffer memory to write 16x16x8bit Y data
output ywe; // wrire enable of Y data
output pre_first_out;
wire pre_first_out= pre_first_in;
// wire [7:0] y_out= din[7:0];
wire [7:0] y_out= {~din[7],din[6:0]};
reg [7:0] yaddr;
reg ywe;
always @ (posedge clk) begin
ywe <= en & (pre_first_in || (ywe && (yaddr[7:0] !=8'hff)));
if (!en || pre_first_in) yaddr[7:0] <= 8'h0;
else if (ywe) yaddr[7:0] <= yaddr[7:0] + 1;
end
endmodule
module csconvert_jp4 (en,
clk,
din,
pre_first_in,
y_out,
yaddr,
ywe,
pre_first_out);
input en;
input clk; // clock
input [7:0] din; // input data in scanline sequence
input pre_first_in; // marks the first input pixel
output [7:0] y_out; // output Y (16x16) in scanline sequence. Valid if ys active
output [7:0] yaddr; // address for the external buffer memory to write 16x16x8bit Y data
output ywe; // wrire enable of Y data
output pre_first_out;
wire pre_first_out= pre_first_in;
// wire [7:0] y_out= din[7:0];
wire [7:0] y_out= {~din[7],din[6:0]};
reg [7:0] yaddr_cntr;
reg ywe;
wire [7:0] yaddr= {yaddr_cntr[4],yaddr_cntr[7:5],yaddr_cntr[0],yaddr_cntr[3:1]};
always @ (posedge clk) begin
ywe <= en & (pre_first_in || (ywe && (yaddr[7:0] !=8'hff)));
if (!en || pre_first_in) yaddr_cntr[7:0] <= 8'h0;
else if (ywe) yaddr_cntr[7:0] <= yaddr_cntr[7:0] + 1;
end
endmodule
module csconvert_jp4diff (en,
clk,
scale_diff, // divide differences by 2 (to fit in 8-bit range)
hdr, // second green absolute, not difference
din,
pre_first_in,
y_out,
yaddr,
ywe,
pre_first_out,
bayer_phase);
// synthesis attribute shreg_extract of csconvert_jp4diff is yes;
input en;
input clk; // clock
input scale_diff;
input hdr;
input [7:0] din; // input data in scanline sequence
input pre_first_in; // marks the first input pixel
output [8:0] y_out; // output Y (16x16) in scanline sequence. Valid if ys active
output [7:0] yaddr; // address for the external buffer memory to write 16x16x8bit Y data
output ywe; // wrire enable of Y data
output pre_first_out;
input [1:0] bayer_phase; // selected pixel will be absolute, others - difference
reg pre_first_out;
reg [2:0] pre2_first_out;
reg [8:0] y_out;
reg [8:0] pre_y_out;
reg [7:0] yaddr_cntr;
reg [7:0] pre_yaddr_cntr;
reg [7:0] pre2_yaddr_cntr;
// reg [7:0] icntr;
reg ywe;
reg [2:0] pre_ywe;
reg [7:0] yaddr;
// reg [4:0] out_dly;
reg dly_1;
reg [14:0] dly_16;
reg dly_17;
// wire start_out=bayer_phase[1]?(bayer_phase[0]?dly_17:dly_16):(bayer_phase[0]?dly_1:pre_first_in);
///AF2015 - What was supposed to be here for "dly_16" (15 bits, expected 1) - any non-zero or [14]?
// wire start_out=bayer_phase[1]?(bayer_phase[0]?dly_17: (|dly_16)):(bayer_phase[0]?dly_1:pre_first_in);
wire start_out=bayer_phase[1]?(bayer_phase[0]?dly_17: dly_16[14]):(bayer_phase[0]?dly_1:pre_first_in);
reg [7:0] iadr;
reg iadr_run;
reg [1:0] mux_plus_sel;
reg [2:0] mux_minus_sel;
reg hdr_bit;
reg [1:0] scale_color;
reg [1:0] is_color;
reg [7:0] mux_plus;
reg [7:0] mux_minus;
reg [7:0] dd0;
reg [7:0] dd1;
wire [7:0] dd16;
reg [7:0] dd17;
reg [14:0] ddsr0,ddsr1,ddsr2,ddsr3,ddsr4,ddsr5,ddsr6,ddsr7;
wire [8:0] scaled_pre_y_out= (scale_color[1])? +{pre_y_out[8],pre_y_out[8:1]}: pre_y_out[8:0];
assign dd16[7:0]={ddsr7[14],ddsr6[14],ddsr5[14],ddsr4[14],ddsr3[14],ddsr2[14],ddsr1[14],ddsr0[14]};
always @ (posedge clk) begin
dly_1 <= pre_first_in;
dly_17 <= dly_16[14];
dly_16[14:0] <= {dly_16[13:0],dly_1};
pre2_first_out[2:0]<= {pre2_first_out[1:0], start_out};
pre_first_out<= pre2_first_out[2];
iadr_run <= en & (start_out || (iadr_run && (iadr[7:0]!=8'hff)));
pre_ywe[2:0] <= {pre_ywe[1:0],iadr_run};
ywe <= pre_ywe[2];
if (!en || start_out) iadr[7:0] <= 8'h0;
else if (iadr_run) iadr[7:0] <= iadr[7:0] + 1;
pre2_yaddr_cntr[7:0] <= iadr[7:0];
pre_yaddr_cntr [7:0] <= pre2_yaddr_cntr[7:0];
yaddr_cntr[7:0] <= pre_yaddr_cntr[7:0];
yaddr[7:0] <= {yaddr_cntr[4],yaddr_cntr[7:5],yaddr_cntr[0],yaddr_cntr[3:1]};
case ({bayer_phase[1:0],iadr[4],iadr[0]} )
4'b0000: begin mux_plus_sel <= 2'h0; mux_minus_sel <= 3'h4; hdr_bit <=1'h0; end
4'b0001: begin mux_plus_sel <= 2'h0; mux_minus_sel <= 3'h1; hdr_bit <=1'h0; end
4'b0010: begin mux_plus_sel <= 2'h0; mux_minus_sel <= 3'h2; hdr_bit <=1'h0; end
4'b0011: begin mux_plus_sel <= 2'h0; mux_minus_sel <= 3'h3; hdr_bit <=1'h1; end
4'b0100: begin mux_plus_sel <= 2'h1; mux_minus_sel <= 3'h0; hdr_bit <=1'h0; end
4'b0101: begin mux_plus_sel <= 2'h1; mux_minus_sel <= 3'h4; hdr_bit <=1'h0; end
4'b0110: begin mux_plus_sel <= 2'h1; mux_minus_sel <= 3'h2; hdr_bit <=1'h1; end
4'b0111: begin mux_plus_sel <= 2'h1; mux_minus_sel <= 3'h3; hdr_bit <=1'h0; end
4'b1000: begin mux_plus_sel <= 2'h2; mux_minus_sel <= 3'h0; hdr_bit <=1'h0; end
4'b1001: begin mux_plus_sel <= 2'h2; mux_minus_sel <= 3'h1; hdr_bit <=1'h1; end
4'b1010: begin mux_plus_sel <= 2'h2; mux_minus_sel <= 3'h4; hdr_bit <=1'h0; end
4'b1011: begin mux_plus_sel <= 2'h2; mux_minus_sel <= 3'h3; hdr_bit <=1'h0; end
4'b1100: begin mux_plus_sel <= 2'h3; mux_minus_sel <= 3'h0; hdr_bit <=1'h1; end
4'b1101: begin mux_plus_sel <= 2'h3; mux_minus_sel <= 3'h1; hdr_bit <=1'h0; end
4'b1110: begin mux_plus_sel <= 2'h3; mux_minus_sel <= 3'h2; hdr_bit <=1'h0; end
4'b1111: begin mux_plus_sel <= 2'h3; mux_minus_sel <= 3'h4; hdr_bit <=1'h0; end
endcase
/*
if (pre_ywe[0]) case (mux_plus_sel[1:0])
2'h0: mux_plus[7:0] <= dd17[7:0];
2'h1: mux_plus[7:0] <= dd16[7:0];
2'h2: mux_plus[7:0] <= dd1 [7:0];
2'h3: mux_plus[7:0] <= dd0 [7:0];
endcase
if (pre_ywe[0]) casex ({mux_minus_sel[2] | (hdr_bit & hdr), mux_minus_sel[1:0]})
3'h0: mux_minus[7:0] <= dd17[7:0];
3'h1: mux_minus[7:0] <= dd16[7:0];
3'h2: mux_minus[7:0] <= dd1 [7:0];
3'h3: mux_minus[7:0] <= dd0 [7:0];
3'b1xx: mux_minus[7:0] <= 8'h0;
endcase
*/
if (pre_ywe[0]) case (mux_plus_sel[1:0])
2'h0: mux_plus[7:0] <= dd0 [7:0];
2'h1: mux_plus[7:0] <= dd1 [7:0];
2'h2: mux_plus[7:0] <= dd16[7:0];
2'h3: mux_plus[7:0] <= dd17[7:0];
endcase
if (pre_ywe[0]) casex ({mux_minus_sel[2] | (hdr_bit & hdr), mux_minus_sel[1:0]})
3'h0: mux_minus[7:0] <= dd0 [7:0];
3'h1: mux_minus[7:0] <= dd1 [7:0];
3'h2: mux_minus[7:0] <= dd16[7:0];
3'h3: mux_minus[7:0] <= dd17[7:0];
3'b1xx: mux_minus[7:0] <= 8'h0;
endcase
is_color[1:0] <= {is_color[0], ~(mux_minus_sel[2] | (hdr_bit & hdr))}; // 1 for color components (diffs) ([0] valid at pre_ywe[1])
scale_color[1:0] <= {scale_color[0], ~(mux_minus_sel[2] | (hdr_bit & hdr)) & scale_diff}; // 1 for color components (diffs) ([0] valid at pre_ywe[1])
if (pre_ywe[1]) pre_y_out[8:0] <= {1'b0,mux_plus[7:0]} - {1'b0,mux_minus[7:0]};
// if (scaled_pre_y_out[8]==scaled_pre_y_out[7]) y_out[7:0] <= (scaled_pre_y_out[7:0]^ 8'h80); // limit differences by 0/ff
// else y_out[7:0] <= scaled_pre_y_out[8]?8'h0:8'hff;
y_out[8:0] <= scaled_pre_y_out[8:0] - {1'h0, ~is_color[1],7'h0}; // subtract 0x80 from Y components (make them -128+127)
dd0[7:0] <= din [7:0];
dd1[7:0] <= dd0 [7:0];
ddsr0[14:0] <= {ddsr0[13:0],dd1[0]};
ddsr1[14:0] <= {ddsr1[13:0],dd1[1]};
ddsr2[14:0] <= {ddsr2[13:0],dd1[2]};
ddsr3[14:0] <= {ddsr3[13:0],dd1[3]};
ddsr4[14:0] <= {ddsr4[13:0],dd1[4]};
ddsr5[14:0] <= {ddsr5[13:0],dd1[5]};
ddsr6[14:0] <= {ddsr6[13:0],dd1[6]};
ddsr7[14:0] <= {ddsr7[13:0],dd1[7]};
dd17[7:0] <= dd16 [7:0];
end
endmodule
|
(* -*- coq-prog-name: "coqtop.byte"; coq-prog-args: ("-emacs-U" "-top" "Coq.Classes.RelationClasses") -*- *)
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * CNRS-Ecole Polytechnique-INRIA Futurs-Universite Paris Sud *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(* Typeclass-based relations, tactics and standard instances.
This is the basic theory needed to formalize morphisms and setoids.
Author: Matthieu Sozeau
Institution: LRI, CNRS UMR 8623 - UniversitÃcopyright Paris Sud
91405 Orsay, France *)
(* $Id$ *)
Require Export Coq.Classes.Init.
Require Import Coq.Program.Basics.
Require Import Coq.Program.Tactics.
Require Export Coq.Relations.Relation_Definitions.
Notation inverse R := (flip (R:relation _) : relation _).
Definition complement {A} (R : relation A) : relation A := fun x y => R x y -> False.
Definition pointwise_relation {A B : Type} (R : relation B) : relation (A -> B) :=
fun f g => forall x : A, R (f x) (g x).
(** These are convertible. *)
Lemma complement_inverse : forall A (R : relation A), complement (inverse R) = inverse (complement R).
Proof. reflexivity. Qed.
(** We rebind relations in separate classes to be able to overload each proof. *)
Set Implicit Arguments.
Unset Strict Implicit.
Class Reflexive A (R : relation A) :=
reflexivity : forall x, R x x.
Class Irreflexive A (R : relation A) :=
irreflexivity :> Reflexive A (complement R).
Class Symmetric A (R : relation A) :=
symmetry : forall x y, R x y -> R y x.
Class Asymmetric A (R : relation A) :=
asymmetry : forall x y, R x y -> R y x -> False.
Class Transitive A (R : relation A) :=
transitivity : forall x y z, R x y -> R y z -> R x z.
Implicit Arguments Reflexive [A].
Implicit Arguments Irreflexive [A].
Implicit Arguments Symmetric [A].
Implicit Arguments Asymmetric [A].
Implicit Arguments Transitive [A].
Hint Resolve @irreflexivity : ord.
Unset Implicit Arguments.
(** We can already dualize all these properties. *)
Program Instance flip_Reflexive [ Reflexive A R ] : Reflexive (flip R) :=
reflexivity := reflexivity (R:=R).
Program Instance flip_Irreflexive [ Irreflexive A R ] : Irreflexive (flip R) :=
irreflexivity := irreflexivity (R:=R).
Program Instance flip_Symmetric [ Symmetric A R ] : Symmetric (flip R).
Solve Obligations using unfold flip ; program_simpl ; clapply Symmetric.
Program Instance flip_Asymmetric [ Asymmetric A R ] : Asymmetric (flip R).
Solve Obligations using program_simpl ; unfold flip in * ; intros ; clapply asymmetry.
Program Instance flip_Transitive [ Transitive A R ] : Transitive (flip R).
Solve Obligations using unfold flip ; program_simpl ; clapply transitivity.
Program Instance Reflexive_complement_Irreflexive [ Reflexive A (R : relation A) ]
: Irreflexive (complement R).
Next Obligation.
Proof.
unfold complement.
red. intros H.
intros H' ; apply H'.
apply reflexivity.
Qed.
Program Instance complement_Symmetric [ Symmetric A (R : relation A) ] : Symmetric (complement R).
Next Obligation.
Proof.
red ; intros H'.
apply (H (symmetry H')).
Qed.
(** * Standard instances. *)
Ltac reduce_hyp H :=
match type of H with
| context [ _ <-> _ ] => fail 1
| _ => red in H ; try reduce_hyp H
end.
Ltac reduce_goal :=
match goal with
| [ |- _ <-> _ ] => fail 1
| _ => red ; intros ; try reduce_goal
end.
Tactic Notation "reduce" "in" hyp(Hid) := reduce_hyp Hid.
Ltac reduce := reduce_goal.
Tactic Notation "apply" "*" constr(t) :=
first [ refine t | refine (t _) | refine (t _ _) | refine (t _ _ _) | refine (t _ _ _ _) |
refine (t _ _ _ _ _) | refine (t _ _ _ _ _ _) | refine (t _ _ _ _ _ _ _) ].
Ltac simpl_relation :=
unfold flip, impl, arrow ; try reduce ; program_simpl ;
try ( solve [ intuition ]).
Ltac obligation_tactic ::= simpl_relation.
(** Logical implication. *)
Program Instance impl_Reflexive : Reflexive impl.
Program Instance impl_Transitive : Transitive impl.
(** Logical equivalence. *)
Program Instance iff_Reflexive : Reflexive iff.
Program Instance iff_Symmetric : Symmetric iff.
Program Instance iff_Transitive : Transitive iff.
(** Leibniz equality. *)
Program Instance eq_Reflexive : Reflexive (@eq A).
Program Instance eq_Symmetric : Symmetric (@eq A).
Program Instance eq_Transitive : Transitive (@eq A).
(** Various combinations of reflexivity, symmetry and transitivity. *)
(** A [PreOrder] is both Reflexive and Transitive. *)
Class PreOrder A (R : relation A) : Prop :=
PreOrder_Reflexive :> Reflexive R ;
PreOrder_Transitive :> Transitive R.
(** A partial equivalence relation is Symmetric and Transitive. *)
Class PER (carrier : Type) (pequiv : relation carrier) : Prop :=
PER_Symmetric :> Symmetric pequiv ;
PER_Transitive :> Transitive pequiv.
(** Equivalence relations. *)
Class Equivalence (carrier : Type) (equiv : relation carrier) : Prop :=
Equivalence_Reflexive :> Reflexive equiv ;
Equivalence_Symmetric :> Symmetric equiv ;
Equivalence_Transitive :> Transitive equiv.
(** An Equivalence is a PER plus reflexivity. *)
Instance Equivalence_PER [ Equivalence A R ] : PER A R | 10 :=
PER_Symmetric := Equivalence_Symmetric ;
PER_Transitive := Equivalence_Transitive.
(** We can now define antisymmetry w.r.t. an equivalence relation on the carrier. *)
Class [ Equivalence A eqA ] => Antisymmetric (R : relation A) :=
antisymmetry : forall x y, R x y -> R y x -> eqA x y.
Program Instance flip_antiSymmetric [ eq : Equivalence A eqA, ! Antisymmetric eq R ] :
Antisymmetric eq (flip R).
(** Leibinz equality [eq] is an equivalence relation.
The instance has low priority as it is always applicable
if only the type is constrained. *)
Program Instance eq_equivalence : Equivalence A (@eq A) | 10.
(** Logical equivalence [iff] is an equivalence relation. *)
Program Instance iff_equivalence : Equivalence Prop iff.
(** We now develop a generalization of results on relations for arbitrary predicates.
The resulting theory can be applied to homogeneous binary relations but also to
arbitrary n-ary predicates. *)
Require Import List.
(* Notation " [ ] " := nil : list_scope. *)
(* Notation " [ x ; .. ; y ] " := (cons x .. (cons y nil) ..) (at level 1) : list_scope. *)
(* Open Local Scope list_scope. *)
(** A compact representation of non-dependent arities, with the codomain singled-out. *)
Fixpoint arrows (l : list Type) (r : Type) : Type :=
match l with
| nil => r
| A :: l' => A -> arrows l' r
end.
(** We can define abbreviations for operation and relation types based on [arrows]. *)
Definition unary_operation A := arrows (cons A nil) A.
Definition binary_operation A := arrows (cons A (cons A nil)) A.
Definition ternary_operation A := arrows (cons A (cons A (cons A nil))) A.
(** We define n-ary [predicate]s as functions into [Prop]. *)
Notation predicate l := (arrows l Prop).
(** Unary predicates, or sets. *)
Definition unary_predicate A := predicate (cons A nil).
(** Homogeneous binary relations, equivalent to [relation A]. *)
Definition binary_relation A := predicate (cons A (cons A nil)).
(** We can close a predicate by universal or existential quantification. *)
Fixpoint predicate_all (l : list Type) : predicate l -> Prop :=
match l with
| nil => fun f => f
| A :: tl => fun f => forall x : A, predicate_all tl (f x)
end.
Fixpoint predicate_exists (l : list Type) : predicate l -> Prop :=
match l with
| nil => fun f => f
| A :: tl => fun f => exists x : A, predicate_exists tl (f x)
end.
(** Pointwise extension of a binary operation on [T] to a binary operation
on functions whose codomain is [T].
For an operator on [Prop] this lifts the operator to a binary operation. *)
Fixpoint pointwise_extension {T : Type} (op : binary_operation T)
(l : list Type) : binary_operation (arrows l T) :=
match l with
| nil => fun R R' => op R R'
| A :: tl => fun R R' =>
fun x => pointwise_extension op tl (R x) (R' x)
end.
(** Pointwise lifting, equivalent to doing [pointwise_extension] and closing using [predicate_all]. *)
Fixpoint pointwise_lifting (op : binary_relation Prop) (l : list Type) : binary_relation (predicate l) :=
match l with
| nil => fun R R' => op R R'
| A :: tl => fun R R' =>
forall x, pointwise_lifting op tl (R x) (R' x)
end.
(** The n-ary equivalence relation, defined by lifting the 0-ary [iff] relation. *)
Definition predicate_equivalence {l : list Type} : binary_relation (predicate l) :=
pointwise_lifting iff l.
(** The n-ary implication relation, defined by lifting the 0-ary [impl] relation. *)
Definition predicate_implication {l : list Type} :=
pointwise_lifting impl l.
(** Notations for pointwise equivalence and implication of predicates. *)
Infix "<∙>" := predicate_equivalence (at level 95, no associativity) : predicate_scope.
Infix "-∙>" := predicate_implication (at level 70) : predicate_scope.
Open Local Scope predicate_scope.
(** The pointwise liftings of conjunction and disjunctions.
Note that these are [binary_operation]s, building new relations out of old ones. *)
Definition predicate_intersection := pointwise_extension and.
Definition predicate_union := pointwise_extension or.
Infix "/∙\" := predicate_intersection (at level 80, right associativity) : predicate_scope.
Infix "\∙/" := predicate_union (at level 85, right associativity) : predicate_scope.
(** The always [True] and always [False] predicates. *)
Fixpoint true_predicate {l : list Type} : predicate l :=
match l with
| nil => True
| A :: tl => fun _ => @true_predicate tl
end.
Fixpoint false_predicate {l : list Type} : predicate l :=
match l with
| nil => False
| A :: tl => fun _ => @false_predicate tl
end.
Notation "∙⊤∙" := true_predicate : predicate_scope.
Notation "∙⊥∙" := false_predicate : predicate_scope.
(** Predicate equivalence is an equivalence, and predicate implication defines a preorder. *)
Program Instance predicate_equivalence_equivalence :
Equivalence (predicate l) predicate_equivalence.
Next Obligation.
induction l ; firstorder.
Qed.
Next Obligation.
induction l ; firstorder.
Qed.
Next Obligation.
fold pointwise_lifting.
induction l. firstorder.
intros. simpl in *. pose (IHl (x x0) (y x0) (z x0)).
firstorder.
Qed.
Program Instance predicate_implication_preorder :
PreOrder (predicate l) predicate_implication.
Next Obligation.
induction l ; firstorder.
Qed.
Next Obligation.
induction l. firstorder.
unfold predicate_implication in *. simpl in *.
intro. pose (IHl (x x0) (y x0) (z x0)). firstorder.
Qed.
(** We define the various operations which define the algebra on binary relations,
from the general ones. *)
Definition relation_equivalence {A : Type} : relation (relation A) :=
@predicate_equivalence (cons _ (cons _ nil)).
Class subrelation {A:Type} (R R' : relation A) : Prop :=
is_subrelation : @predicate_implication (cons A (cons A nil)) R R'.
Implicit Arguments subrelation [[A]].
Definition relation_conjunction {A} (R : relation A) (R' : relation A) : relation A :=
@predicate_intersection (cons A (cons A nil)) R R'.
Definition relation_disjunction {A} (R : relation A) (R' : relation A) : relation A :=
@predicate_union (cons A (cons A nil)) R R'.
(** Relation equivalence is an equivalence, and subrelation defines a partial order. *)
Instance relation_equivalence_equivalence (A : Type) :
Equivalence (relation A) relation_equivalence.
Proof. intro A. exact (@predicate_equivalence_equivalence (cons A (cons A nil))). Qed.
Instance relation_implication_preorder : PreOrder (relation A) subrelation.
Proof. intro A. exact (@predicate_implication_preorder (cons A (cons A nil))). Qed.
(** *** Partial Order.
A partial order is a preorder which is additionally antisymmetric.
We give an equivalent definition, up-to an equivalence relation
on the carrier. *)
Class [ equ : Equivalence A eqA, PreOrder A R ] => PartialOrder :=
partial_order_equivalence : relation_equivalence eqA (relation_conjunction R (inverse R)).
(** The equivalence proof is sufficient for proving that [R] must be a morphism
for equivalence (see Morphisms).
It is also sufficient to show that [R] is antisymmetric w.r.t. [eqA] *)
Instance partial_order_antisym [ PartialOrder A eqA R ] : ! Antisymmetric A eqA R.
Proof with auto.
reduce_goal. pose proof partial_order_equivalence as poe. do 3 red in poe.
apply <- poe. firstorder.
Qed.
(** The partial order defined by subrelation and relation equivalence. *)
Program Instance subrelation_partial_order :
! PartialOrder (relation A) relation_equivalence subrelation.
Next Obligation.
Proof.
unfold relation_equivalence in *. firstorder.
Qed.
Lemma inverse_pointwise_relation A (R : relation A) :
relation_equivalence (pointwise_relation (inverse R)) (inverse (pointwise_relation (A:=A) R)).
Proof. reflexivity. Qed.
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
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// (individually and collectively, "Critical
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// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_3.v
// Version : 1.3
//
// Description: 7-series solution wrapper : Endpoint for PCI Express
//
//
//
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "pcie_7x_v1_3,pcie_7x_v1_3,{LINK_CAP_MAX_LINK_SPEED=2,LINK_CAP_MAX_LINK_WIDTH=08,PCIE_CAP_DEVICE_PORT_TYPE=0000,DEV_CAP_MAX_PAYLOAD_SUPPORTED=1,USER_CLK_FREQ=4,REF_CLK_FREQ=0,MSI_CAP_ON=TRUE,MSI_CAP_MULTIMSGCAP=0,MSI_CAP_MULTIMSG_EXTENSION=0,MSIX_CAP_ON=FALSE,TL_TX_RAM_RADDR_LATENCY=0,TL_TX_RAM_RDATA_LATENCY=2,TL_RX_RAM_RADDR_LATENCY=0,TL_RX_RAM_RDATA_LATENCY=2,TL_RX_RAM_WRITE_LATENCY=0,VC0_TX_LASTPACKET=28,VC0_RX_RAM_LIMIT=3FF,VC0_TOTAL_CREDITS_PH=4,VC0_TOTAL_CREDITS_PD=32,VC0_TOTAL_CREDITS_NPH=4,VC0_TOTAL_CREDITS_NPD=8,VC0_TOTAL_CREDITS_CH=72,VC0_TOTAL_CREDITS_CD=370,VC0_CPL_INFINITE=TRUE,DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT=0,DEV_CAP_EXT_TAG_SUPPORTED=FALSE,LINK_STATUS_SLOT_CLOCK_CONFIG=TRUE,ENABLE_RX_TD_ECRC_TRIM=TRUE,DISABLE_LANE_REVERSAL=TRUE,DISABLE_SCRAMBLING=FALSE,DSN_CAP_ON=TRUE,REVISION_ID=03,VC_CAP_ON=FALSE}" *)
module pcie_7x_v1_3 # (
parameter CFG_VEND_ID = 16'h10EE,
parameter CFG_DEV_ID = 16'h4243,
parameter CFG_REV_ID = 8'h03,
parameter CFG_SUBSYS_VEND_ID = 16'h10EE,
parameter CFG_SUBSYS_ID = 16'h0007,
parameter ALLOW_X8_GEN2 = "TRUE",
parameter PIPE_PIPELINE_STAGES = 1,
parameter [11:0] AER_BASE_PTR = 12'h000,
parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
parameter AER_CAP_MULTIHEADER = "FALSE",
parameter [11:0] AER_CAP_NEXTPTR = 12'h000,
parameter [23:0] AER_CAP_OPTIONAL_ERR_SUPPORT = 24'h000000,
parameter AER_CAP_ON = "FALSE",
parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "FALSE",
parameter [31:0] BAR0 = 32'hFF000000,
parameter [31:0] BAR1 = 32'hFFFF0000,
parameter [31:0] BAR2 = 32'h00000000,
parameter [31:0] BAR3 = 32'h00000000,
parameter [31:0] BAR4 = 32'h00000000,
parameter [31:0] BAR5 = 32'h00000000,
parameter C_DATA_WIDTH = 128,
parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000,
parameter [23:0] CLASS_CODE = 24'h058000,
parameter CMD_INTX_IMPLEMENTED = "TRUE",
parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE",
parameter [3:0] CPL_TIMEOUT_RANGES_SUPPORTED = 4'h2,
parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 0,
parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 7,
parameter DEV_CAP_EXT_TAG_SUPPORTED = "FALSE",
parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 1,
parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0,
parameter DEV_CAP2_ARI_FORWARDING_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED = "FALSE",
parameter DEV_CAP2_CAS128_COMPLETER_SUPPORTED = "FALSE",
parameter [1:0] DEV_CAP2_TPH_COMPLETER_SUPPORTED = 2'b00,
parameter DEV_CONTROL_EXT_TAG_DEFAULT = "FALSE",
parameter DISABLE_LANE_REVERSAL = "TRUE",
parameter DISABLE_RX_POISONED_RESP = "FALSE",
parameter DISABLE_SCRAMBLING = "FALSE",
parameter [11:0] DSN_BASE_PTR = 12'h100,
parameter [11:0] DSN_CAP_NEXTPTR = 12'h000,
parameter DSN_CAP_ON = "TRUE",
parameter [10:0] ENABLE_MSG_ROUTE = 11'b00000000000,
parameter ENABLE_RX_TD_ECRC_TRIM = "TRUE",
parameter [31:0] EXPANSION_ROM = 32'h00000000,
parameter [5:0] EXT_CFG_CAP_PTR = 6'h3F,
parameter [9:0] EXT_CFG_XP_CAP_PTR = 10'h3FF,
parameter [7:0] HEADER_TYPE = 8'h00,
parameter [7:0] INTERRUPT_PIN = 8'h1,
parameter [9:0] LAST_CONFIG_DWORD = 10'h3FF,
parameter LINK_CAP_ASPM_OPTIONALITY = "FALSE",
parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE",
parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE",
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h2,
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08,
parameter LINK_CTRL2_DEEMPHASIS = "FALSE",
parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE",
parameter [3:0] LINK_CTRL2_TARGET_LINK_SPEED = 4'h2,
parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE",
parameter [14:0] LL_ACK_TIMEOUT = 15'h0000,
parameter LL_ACK_TIMEOUT_EN = "FALSE",
parameter integer LL_ACK_TIMEOUT_FUNC = 0,
parameter [14:0] LL_REPLAY_TIMEOUT = 15'h0000,
parameter LL_REPLAY_TIMEOUT_EN = "FALSE",
parameter integer LL_REPLAY_TIMEOUT_FUNC = 1,
parameter [5:0] LTSSM_MAX_LINK_WIDTH = 6'h08,
parameter MSI_CAP_MULTIMSGCAP = 0,
parameter MSI_CAP_MULTIMSG_EXTENSION = 0,
parameter MSI_CAP_ON = "TRUE",
parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "FALSE",
parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE",
parameter MSIX_CAP_ON = "FALSE",
parameter MSIX_CAP_PBA_BIR = 0,
parameter [28:0] MSIX_CAP_PBA_OFFSET = 29'h0,
parameter MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] MSIX_CAP_TABLE_OFFSET = 29'h0,
parameter [10:0] MSIX_CAP_TABLE_SIZE = 11'h0,
parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0,
parameter [7:0] PCIE_CAP_NEXTPTR = 8'h00,
parameter PM_CAP_DSI = "FALSE",
parameter PM_CAP_D1SUPPORT = "FALSE",
parameter PM_CAP_D2SUPPORT = "FALSE",
parameter [7:0] PM_CAP_NEXTPTR = 8'h48,
parameter [4:0] PM_CAP_PMESUPPORT = 5'h0F,
parameter PM_CSR_NOSOFTRST = "TRUE",
parameter [1:0] PM_DATA_SCALE0 = 2'h0,
parameter [1:0] PM_DATA_SCALE1 = 2'h0,
parameter [1:0] PM_DATA_SCALE2 = 2'h0,
parameter [1:0] PM_DATA_SCALE3 = 2'h0,
parameter [1:0] PM_DATA_SCALE4 = 2'h0,
parameter [1:0] PM_DATA_SCALE5 = 2'h0,
parameter [1:0] PM_DATA_SCALE6 = 2'h0,
parameter [1:0] PM_DATA_SCALE7 = 2'h0,
parameter [7:0] PM_DATA0 = 8'h00,
parameter [7:0] PM_DATA1 = 8'h00,
parameter [7:0] PM_DATA2 = 8'h00,
parameter [7:0] PM_DATA3 = 8'h00,
parameter [7:0] PM_DATA4 = 8'h00,
parameter [7:0] PM_DATA5 = 8'h00,
parameter [7:0] PM_DATA6 = 8'h00,
parameter [7:0] PM_DATA7 = 8'h00,
parameter [11:0] RBAR_BASE_PTR = 12'h000,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR0 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR1 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR2 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR3 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR4 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR5 = 5'h00,
parameter [2:0] RBAR_CAP_INDEX0 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX1 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX2 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX3 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX4 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX5 = 3'h0,
parameter RBAR_CAP_ON = "FALSE",
parameter [31:0] RBAR_CAP_SUP0 = 32'h00001,
parameter [31:0] RBAR_CAP_SUP1 = 32'h00001,
parameter [31:0] RBAR_CAP_SUP2 = 32'h00001,
parameter [31:0] RBAR_CAP_SUP3 = 32'h00001,
parameter [31:0] RBAR_CAP_SUP4 = 32'h00001,
parameter [31:0] RBAR_CAP_SUP5 = 32'h00001,
parameter [2:0] RBAR_NUM = 3'h0,
parameter RECRC_CHK = 0,
parameter RECRC_CHK_TRIM = "FALSE",
parameter REF_CLK_FREQ = 0, // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1,
parameter KEEP_WIDTH = C_DATA_WIDTH / 8,
parameter TL_RX_RAM_RADDR_LATENCY = 0,
parameter TL_RX_RAM_RDATA_LATENCY = 2,
parameter TL_RX_RAM_WRITE_LATENCY = 0,
parameter TL_TX_RAM_RADDR_LATENCY = 0,
parameter TL_TX_RAM_RDATA_LATENCY = 2,
parameter TL_TX_RAM_WRITE_LATENCY = 0,
parameter TRN_NP_FC = "TRUE",
parameter TRN_DW = "TRUE",
parameter UPCONFIG_CAPABLE = "TRUE",
parameter UPSTREAM_FACING = "TRUE",
parameter UR_ATOMIC = "FALSE",
parameter UR_INV_REQ = "TRUE",
parameter UR_PRS_RESPONSE = "TRUE",
parameter USER_CLK_FREQ = 4,
parameter USER_CLK2_DIV2 = "TRUE",
parameter [11:0] VC_BASE_PTR = 12'h000,
parameter [11:0] VC_CAP_NEXTPTR = 12'h000,
parameter VC_CAP_ON = "FALSE",
parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE",
parameter VC0_CPL_INFINITE = "TRUE",
parameter [12:0] VC0_RX_RAM_LIMIT = 13'h3FF,
parameter VC0_TOTAL_CREDITS_CD = 370,
parameter VC0_TOTAL_CREDITS_CH = 72,
parameter VC0_TOTAL_CREDITS_NPH = 4,
parameter VC0_TOTAL_CREDITS_NPD = 8,
parameter VC0_TOTAL_CREDITS_PD = 32,
parameter VC0_TOTAL_CREDITS_PH = 4,
parameter VC0_TX_LASTPACKET = 28,
parameter [11:0] VSEC_BASE_PTR = 12'h000,
parameter [11:0] VSEC_CAP_NEXTPTR = 12'h000,
parameter VSEC_CAP_ON = "FALSE",
parameter DISABLE_ASPM_L1_TIMER = "FALSE",
parameter DISABLE_BAR_FILTERING = "FALSE",
parameter DISABLE_ID_CHECK = "FALSE",
parameter DISABLE_RX_TC_FILTER = "FALSE",
parameter [7:0] DNSTREAM_LINK_NUM = 8'h00,
parameter [15:0] DSN_CAP_ID = 16'h0003,
parameter [3:0] DSN_CAP_VERSION = 4'h1,
parameter ENTER_RVRY_EI_L0 = "TRUE",
parameter [4:0] INFER_EI = 5'h00,
parameter IS_SWITCH = "FALSE",
parameter LINK_CAP_ASPM_SUPPORT = 1,
parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE",
parameter LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7,
parameter LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7,
parameter LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7,
parameter LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7,
parameter LINK_CAP_RSVD_23 = 0,
parameter LINK_CONTROL_RCB = 0,
parameter [7:0] MSI_BASE_PTR = 8'h48,
parameter [7:0] MSI_CAP_ID = 8'h05,
parameter [7:0] MSI_CAP_NEXTPTR = 8'h60,
parameter [7:0] MSIX_BASE_PTR = 8'h9C,
parameter [7:0] MSIX_CAP_ID = 8'h11,
parameter [7:0] MSIX_CAP_NEXTPTR =8'h00,
parameter N_FTS_COMCLK_GEN1 = 255,
parameter N_FTS_COMCLK_GEN2 = 255,
parameter N_FTS_GEN1 = 255,
parameter N_FTS_GEN2 = 255,
parameter [7:0] PCIE_BASE_PTR = 8'h60,
parameter [7:0] PCIE_CAP_CAPABILITY_ID = 8'h10,
parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h2,
parameter PCIE_CAP_ON = "TRUE",
parameter PCIE_CAP_RSVD_15_14 = 0,
parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE",
parameter PCIE_REVISION = 2,
parameter PL_AUTO_CONFIG = 0,
parameter PL_FAST_TRAIN = "FALSE",
parameter PCIE_EXT_CLK = "FALSE",
parameter [7:0] PM_BASE_PTR = 8'h40,
parameter PM_CAP_AUXCURRENT = 0,
parameter [7:0] PM_CAP_ID = 8'h01,
parameter PM_CAP_ON = "TRUE",
parameter PM_CAP_PME_CLOCK = "FALSE",
parameter PM_CAP_RSVD_04 = 0,
parameter PM_CAP_VERSION = 3,
parameter PM_CSR_BPCCEN = "FALSE",
parameter PM_CSR_B2B3 = "FALSE",
parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE",
parameter SELECT_DLL_IF = "FALSE",
parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE",
parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE",
parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE",
parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE",
parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE",
parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE",
parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE",
parameter [12:0] SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000,
parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE",
parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE",
parameter SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0,
parameter [7:0] SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00,
parameter integer SPARE_BIT0 = 0,
parameter integer SPARE_BIT1 = 0,
parameter integer SPARE_BIT2 = 0,
parameter integer SPARE_BIT3 = 0,
parameter integer SPARE_BIT4 = 0,
parameter integer SPARE_BIT5 = 0,
parameter integer SPARE_BIT6 = 0,
parameter integer SPARE_BIT7 = 0,
parameter integer SPARE_BIT8 = 0,
parameter [7:0] SPARE_BYTE0 = 8'h00,
parameter [7:0] SPARE_BYTE1 = 8'h00,
parameter [7:0] SPARE_BYTE2 = 8'h00,
parameter [7:0] SPARE_BYTE3 = 8'h00,
parameter [31:0] SPARE_WORD0 = 32'h00000000,
parameter [31:0] SPARE_WORD1 = 32'h00000000,
parameter [31:0] SPARE_WORD2 = 32'h00000000,
parameter [31:0] SPARE_WORD3 = 32'h00000000,
parameter TL_RBYPASS = "FALSE",
parameter TL_TFC_DISABLE = "FALSE",
parameter TL_TX_CHECKS_DISABLE = "FALSE",
parameter EXIT_LOOPBACK_ON_EI = "TRUE",
parameter CFG_ECRC_ERR_CPLSTAT = 0,
parameter [7:0] CAPABILITIES_PTR = 8'h40,
parameter [6:0] CRM_MODULE_RSTS = 7'h00,
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE",
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE",
parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE",
parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE",
parameter DEV_CAP_RSVD_14_12 = 0,
parameter DEV_CAP_RSVD_17_16 = 0,
parameter DEV_CAP_RSVD_31_29 = 0,
parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE",
parameter [15:0] VC_CAP_ID = 16'h0002,
parameter [3:0] VC_CAP_VERSION = 4'h1,
parameter [15:0] VSEC_CAP_HDR_ID = 16'h1234,
parameter [11:0] VSEC_CAP_HDR_LENGTH = 12'h018,
parameter [3:0] VSEC_CAP_HDR_REVISION = 4'h1,
parameter [15:0] VSEC_CAP_ID = 16'h000B,
parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE",
parameter [3:0] VSEC_CAP_VERSION = 4'h1,
parameter DISABLE_ERR_MSG = "FALSE",
parameter DISABLE_LOCKED_FILTER = "FALSE",
parameter DISABLE_PPM_FILTER = "FALSE",
parameter ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED = "FALSE",
parameter INTERRUPT_STAT_AUTO = "TRUE",
parameter MPS_FORCE = "FALSE",
parameter [14:0] PM_ASPML0S_TIMEOUT = 15'h0000,
parameter PM_ASPML0S_TIMEOUT_EN = "FALSE",
parameter PM_ASPML0S_TIMEOUT_FUNC = 0,
parameter PM_ASPM_FASTEXIT = "FALSE",
parameter PM_MF = "FALSE",
parameter [1:0] RP_AUTO_SPD = 2'h1,
parameter [4:0] RP_AUTO_SPD_LOOPCNT = 5'h1f,
parameter SIM_VERSION = "1.0",
parameter SSL_MESSAGE_AUTO = "FALSE",
parameter TECRC_EP_INV = "FALSE",
parameter UR_CFG1 = "TRUE",
parameter USE_RID_PINS = "FALSE",
// New Parameters
parameter DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED = "FALSE",
parameter DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED = "FALSE",
parameter DEV_CAP2_LTR_MECHANISM_SUPPORTED = "FALSE",
parameter [1:0] DEV_CAP2_MAX_ENDEND_TLP_PREFIXES = 2'h0,
parameter DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING = "FALSE",
parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE",
parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
parameter [15:0] AER_CAP_ID = 16'h0001,
parameter [3:0] AER_CAP_VERSION = 4'h1,
parameter [15:0] RBAR_CAP_ID = 16'h0015,
parameter [11:0] RBAR_CAP_NEXTPTR = 12'h000,
parameter [3:0] RBAR_CAP_VERSION = 4'h1,
parameter PCIE_USE_MODE = "1.0"
)
(
//----------------------------------------------------------------------------------------------------------------//
// 1. PCI Express (pci_exp) Interface //
//----------------------------------------------------------------------------------------------------------------//
// Tx
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_txn,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_txp,
// Rx
input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_rxn,
input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_rxp,
//----------------------------------------------------------------------------------------------------------------//
// 2. Clock Inputs //
//----------------------------------------------------------------------------------------------------------------//
input PIPE_PCLK_IN,
input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PIPE_RXUSRCLK_IN,
input PIPE_RXOUTCLK_IN,
input PIPE_DCLK_IN,
input PIPE_USERCLK1_IN,
input PIPE_USERCLK2_IN,
input PIPE_OOBCLK_IN,
input PIPE_MMCM_LOCK_IN,
output PIPE_TXOUTCLK_OUT,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PIPE_RXOUTCLK_OUT,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] PIPE_PCLK_SEL_OUT,
output PIPE_GEN3_OUT,
//----------------------------------------------------------------------------------------------------------------//
// 3. AXI-S Interface //
//----------------------------------------------------------------------------------------------------------------//
// Common
output user_clk_out,
output reg user_reset_out,
output reg user_lnk_up,
// Tx
output [5:0] tx_buf_av,
output tx_err_drop,
output tx_cfg_req,
output s_axis_tx_tready,
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata,
input [KEEP_WIDTH-1:0] s_axis_tx_tkeep,
input [3:0] s_axis_tx_tuser,
input s_axis_tx_tlast,
input s_axis_tx_tvalid,
input tx_cfg_gnt,
// Rx
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata,
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep,
output m_axis_rx_tlast,
output m_axis_rx_tvalid,
input m_axis_rx_tready,
output [21:0] m_axis_rx_tuser,
input rx_np_ok,
input rx_np_req,
// Flow Control
output [11:0] fc_cpld,
output [7:0] fc_cplh,
output [11:0] fc_npd,
output [7:0] fc_nph,
output [11:0] fc_pd,
output [7:0] fc_ph,
input [2:0] fc_sel,
//----------------------------------------------------------------------------------------------------------------//
// 4. Configuration (CFG) Interface //
//----------------------------------------------------------------------------------------------------------------//
//------------------------------------------------//
// EP and RP //
//------------------------------------------------//
output wire [31:0] cfg_mgmt_do,
output wire cfg_mgmt_rd_wr_done,
output wire [15:0] cfg_status,
output wire [15:0] cfg_command,
output wire [15:0] cfg_dstatus,
output wire [15:0] cfg_dcommand,
output wire [15:0] cfg_lstatus,
output wire [15:0] cfg_lcommand,
output wire [15:0] cfg_dcommand2,
output [2:0] cfg_pcie_link_state,
output wire cfg_pmcsr_pme_en,
output wire [1:0] cfg_pmcsr_powerstate,
output wire cfg_pmcsr_pme_status,
output wire cfg_received_func_lvl_rst,
// Management Interface
input wire [31:0] cfg_mgmt_di,
input wire [3:0] cfg_mgmt_byte_en,
input wire [9:0] cfg_mgmt_dwaddr,
input wire cfg_mgmt_wr_en,
input wire cfg_mgmt_rd_en,
input wire cfg_mgmt_wr_readonly,
// Error Reporting Interface
input wire cfg_err_ecrc,
input wire cfg_err_ur,
input wire cfg_err_cpl_timeout,
input wire cfg_err_cpl_unexpect,
input wire cfg_err_cpl_abort,
input wire cfg_err_posted,
input wire cfg_err_cor,
input wire cfg_err_atomic_egress_blocked,
input wire cfg_err_internal_cor,
input wire cfg_err_malformed,
input wire cfg_err_mc_blocked,
input wire cfg_err_poisoned,
input wire cfg_err_norecovery,
input wire [47:0] cfg_err_tlp_cpl_header,
output wire cfg_err_cpl_rdy,
input wire cfg_err_locked,
input wire cfg_err_acs,
input wire cfg_err_internal_uncor,
input wire cfg_trn_pending,
input wire cfg_pm_halt_aspm_l0s,
input wire cfg_pm_halt_aspm_l1,
input wire cfg_pm_force_state_en,
input wire [1:0] cfg_pm_force_state,
input wire [63:0] cfg_dsn,
//------------------------------------------------//
// EP Only //
//------------------------------------------------//
// Interrupt Interface Signals
input wire cfg_interrupt,
output wire cfg_interrupt_rdy,
input wire cfg_interrupt_assert,
input wire [7:0] cfg_interrupt_di,
output wire [7:0] cfg_interrupt_do,
output wire [2:0] cfg_interrupt_mmenable,
output wire cfg_interrupt_msienable,
output wire cfg_interrupt_msixenable,
output wire cfg_interrupt_msixfm,
input wire cfg_interrupt_stat,
input wire [4:0] cfg_pciecap_interrupt_msgnum,
output cfg_to_turnoff,
input wire cfg_turnoff_ok,
output wire [7:0] cfg_bus_number,
output wire [4:0] cfg_device_number,
output wire [2:0] cfg_function_number,
input wire cfg_pm_wake,
//------------------------------------------------//
// RP Only //
//------------------------------------------------//
input wire cfg_pm_send_pme_to,
input wire [7:0] cfg_ds_bus_number,
input wire [4:0] cfg_ds_device_number,
input wire [2:0] cfg_ds_function_number,
input wire cfg_mgmt_wr_rw1c_as_rw,
output cfg_msg_received,
output [15:0] cfg_msg_data,
output wire cfg_bridge_serr_en,
output wire cfg_slot_control_electromech_il_ctl_pulse,
output wire cfg_root_control_syserr_corr_err_en,
output wire cfg_root_control_syserr_non_fatal_err_en,
output wire cfg_root_control_syserr_fatal_err_en,
output wire cfg_root_control_pme_int_en,
output wire cfg_aer_rooterr_corr_err_reporting_en,
output wire cfg_aer_rooterr_non_fatal_err_reporting_en,
output wire cfg_aer_rooterr_fatal_err_reporting_en,
output wire cfg_aer_rooterr_corr_err_received,
output wire cfg_aer_rooterr_non_fatal_err_received,
output wire cfg_aer_rooterr_fatal_err_received,
output wire cfg_msg_received_err_cor,
output wire cfg_msg_received_err_non_fatal,
output wire cfg_msg_received_err_fatal,
output wire cfg_msg_received_pm_as_nak,
output wire cfg_msg_received_pm_pme,
output wire cfg_msg_received_pme_to_ack,
output wire cfg_msg_received_assert_int_a,
output wire cfg_msg_received_assert_int_b,
output wire cfg_msg_received_assert_int_c,
output wire cfg_msg_received_assert_int_d,
output wire cfg_msg_received_deassert_int_a,
output wire cfg_msg_received_deassert_int_b,
output wire cfg_msg_received_deassert_int_c,
output wire cfg_msg_received_deassert_int_d,
output wire cfg_msg_received_setslotpowerlimit,
//----------------------------------------------------------------------------------------------------------------//
// 5. Physical Layer Control and Status (PL) Interface //
//----------------------------------------------------------------------------------------------------------------//
//------------------------------------------------//
// EP and RP //
//------------------------------------------------//
input wire [1:0] pl_directed_link_change,
input wire [1:0] pl_directed_link_width,
input wire pl_directed_link_speed,
input wire pl_directed_link_auton,
input wire pl_upstream_prefer_deemph,
output wire pl_sel_lnk_rate,
output wire [1:0] pl_sel_lnk_width,
output wire [5:0] pl_ltssm_state,
output wire [1:0] pl_lane_reversal_mode,
output wire pl_phy_lnk_up,
output wire [2:0] pl_tx_pm_state,
output wire [1:0] pl_rx_pm_state,
output wire pl_link_upcfg_cap,
output wire pl_link_gen2_cap,
output wire pl_link_partner_gen2_supported,
output wire [2:0] pl_initial_link_width,
output wire pl_directed_change_done,
//------------------------------------------------//
// EP Only //
//------------------------------------------------//
output wire pl_received_hot_rst,
//------------------------------------------------//
// RP Only //
//------------------------------------------------//
input wire pl_transmit_hot_rst,
input wire pl_downstream_deemph_source,
//----------------------------------------------------------------------------------------------------------------//
// 6. AER interface //
//----------------------------------------------------------------------------------------------------------------//
input wire [127:0] cfg_err_aer_headerlog,
input wire [4:0] cfg_aer_interrupt_msgnum,
output wire cfg_err_aer_headerlog_set,
output wire cfg_aer_ecrc_check_en,
output wire cfg_aer_ecrc_gen_en,
//----------------------------------------------------------------------------------------------------------------//
// 7. VC interface //
//----------------------------------------------------------------------------------------------------------------//
output wire [6:0] cfg_vc_tcvc_map,
//----------------------------------------------------------------------------------------------------------------//
// 8. System(SYS) Interface //
//----------------------------------------------------------------------------------------------------------------//
input wire sys_clk,
input wire sys_reset
);
wire user_clk;
wire user_clk2;
wire [15:0] cfg_vend_id = CFG_VEND_ID;
wire [15:0] cfg_dev_id = CFG_DEV_ID;
wire [7:0] cfg_rev_id = CFG_REV_ID;
wire [15:0] cfg_subsys_vend_id = CFG_SUBSYS_VEND_ID;
wire [15:0] cfg_subsys_id = CFG_SUBSYS_ID;
// PIPE Interface Wires
wire phy_rdy_n;
wire pipe_rx0_polarity_gt;
wire pipe_rx1_polarity_gt;
wire pipe_rx2_polarity_gt;
wire pipe_rx3_polarity_gt;
wire pipe_rx4_polarity_gt;
wire pipe_rx5_polarity_gt;
wire pipe_rx6_polarity_gt;
wire pipe_rx7_polarity_gt;
wire pipe_tx_deemph_gt;
wire [2:0] pipe_tx_margin_gt;
wire pipe_tx_rate_gt;
wire pipe_tx_rcvr_det_gt;
wire [1:0] pipe_tx0_char_is_k_gt;
wire pipe_tx0_compliance_gt;
wire [15:0] pipe_tx0_data_gt;
wire pipe_tx0_elec_idle_gt;
wire [1:0] pipe_tx0_powerdown_gt;
wire [1:0] pipe_tx1_char_is_k_gt;
wire pipe_tx1_compliance_gt;
wire [15:0] pipe_tx1_data_gt;
wire pipe_tx1_elec_idle_gt;
wire [1:0] pipe_tx1_powerdown_gt;
wire [1:0] pipe_tx2_char_is_k_gt;
wire pipe_tx2_compliance_gt;
wire [15:0] pipe_tx2_data_gt;
wire pipe_tx2_elec_idle_gt;
wire [1:0] pipe_tx2_powerdown_gt;
wire [1:0] pipe_tx3_char_is_k_gt;
wire pipe_tx3_compliance_gt;
wire [15:0] pipe_tx3_data_gt;
wire pipe_tx3_elec_idle_gt;
wire [1:0] pipe_tx3_powerdown_gt;
wire [1:0] pipe_tx4_char_is_k_gt;
wire pipe_tx4_compliance_gt;
wire [15:0] pipe_tx4_data_gt;
wire pipe_tx4_elec_idle_gt;
wire [1:0] pipe_tx4_powerdown_gt;
wire [1:0] pipe_tx5_char_is_k_gt;
wire pipe_tx5_compliance_gt;
wire [15:0] pipe_tx5_data_gt;
wire pipe_tx5_elec_idle_gt;
wire [1:0] pipe_tx5_powerdown_gt;
wire [1:0] pipe_tx6_char_is_k_gt;
wire pipe_tx6_compliance_gt;
wire [15:0] pipe_tx6_data_gt;
wire pipe_tx6_elec_idle_gt;
wire [1:0] pipe_tx6_powerdown_gt;
wire [1:0] pipe_tx7_char_is_k_gt;
wire pipe_tx7_compliance_gt;
wire [15:0] pipe_tx7_data_gt;
wire pipe_tx7_elec_idle_gt;
wire [1:0] pipe_tx7_powerdown_gt;
wire pipe_rx0_chanisaligned_gt;
wire [1:0] pipe_rx0_char_is_k_gt;
wire [15:0] pipe_rx0_data_gt;
wire pipe_rx0_elec_idle_gt;
wire pipe_rx0_phy_status_gt;
wire [2:0] pipe_rx0_status_gt;
wire pipe_rx0_valid_gt;
wire pipe_rx1_chanisaligned_gt;
wire [1:0] pipe_rx1_char_is_k_gt;
wire [15:0] pipe_rx1_data_gt;
wire pipe_rx1_elec_idle_gt;
wire pipe_rx1_phy_status_gt;
wire [2:0] pipe_rx1_status_gt;
wire pipe_rx1_valid_gt;
wire pipe_rx2_chanisaligned_gt;
wire [1:0] pipe_rx2_char_is_k_gt;
wire [15:0] pipe_rx2_data_gt;
wire pipe_rx2_elec_idle_gt;
wire pipe_rx2_phy_status_gt;
wire [2:0] pipe_rx2_status_gt;
wire pipe_rx2_valid_gt;
wire pipe_rx3_chanisaligned_gt;
wire [1:0] pipe_rx3_char_is_k_gt;
wire [15:0] pipe_rx3_data_gt;
wire pipe_rx3_elec_idle_gt;
wire pipe_rx3_phy_status_gt;
wire [2:0] pipe_rx3_status_gt;
wire pipe_rx3_valid_gt;
wire pipe_rx4_chanisaligned_gt;
wire [1:0] pipe_rx4_char_is_k_gt;
wire [15:0] pipe_rx4_data_gt;
wire pipe_rx4_elec_idle_gt;
wire pipe_rx4_phy_status_gt;
wire [2:0] pipe_rx4_status_gt;
wire pipe_rx4_valid_gt;
wire pipe_rx5_chanisaligned_gt;
wire [1:0] pipe_rx5_char_is_k_gt;
wire [15:0] pipe_rx5_data_gt;
wire pipe_rx5_elec_idle_gt;
wire pipe_rx5_phy_status_gt;
wire [2:0] pipe_rx5_status_gt;
wire pipe_rx5_valid_gt;
wire pipe_rx6_chanisaligned_gt;
wire [1:0] pipe_rx6_char_is_k_gt;
wire [15:0] pipe_rx6_data_gt;
wire pipe_rx6_elec_idle_gt;
wire pipe_rx6_phy_status_gt;
wire [2:0] pipe_rx6_status_gt;
wire pipe_rx6_valid_gt;
wire pipe_rx7_chanisaligned_gt;
wire [1:0] pipe_rx7_char_is_k_gt;
wire [15:0] pipe_rx7_data_gt;
wire pipe_rx7_elec_idle_gt;
wire pipe_rx7_phy_status_gt;
wire [2:0] pipe_rx7_status_gt;
wire pipe_rx7_valid_gt;
reg user_lnk_up_int;
reg user_reset_int;
wire user_rst_n;
reg pl_received_hot_rst_q;
wire pl_received_hot_rst_wire;
reg pl_phy_lnk_up_q;
wire pl_phy_lnk_up_wire;
wire sys_or_hot_rst;
wire trn_lnk_up;
wire sys_rst_n;
wire [5:0] pl_ltssm_state_int;
localparam TCQ = 100;
// Assign outputs
assign pl_ltssm_state = pl_ltssm_state_int;
assign pl_received_hot_rst = pl_received_hot_rst_q;
assign pl_phy_lnk_up = pl_phy_lnk_up_q;
// Register block outputs pl_received_hot_rst and phy_lnk_up to ease timing on block output
assign sys_or_hot_rst = !sys_rst_n || pl_received_hot_rst_q;
always @(posedge user_clk_out)
begin
if (!sys_rst_n) begin
pl_received_hot_rst_q <= #TCQ 1'b0;
pl_phy_lnk_up_q <= #TCQ 1'b0;
end else begin
pl_received_hot_rst_q <= #TCQ pl_received_hot_rst_wire;
pl_phy_lnk_up_q <= #TCQ pl_phy_lnk_up_wire;
end
end
//------------------------------------------------------------------------------------------------------------------//
// Convert incomign reset from AXI required active High //
// to active low as that is what is required by GT and PCIe Block //
//------------------------------------------------------------------------------------------------------------------//
assign sys_rst_n = ~sys_reset;
// Generate user_lnk_up
always @(posedge user_clk_out)
begin
if (!sys_rst_n) begin
user_lnk_up <= #TCQ 1'b0;
end else begin
user_lnk_up <= #TCQ user_lnk_up_int;
end
end
always @(posedge user_clk_out)
begin
if (!sys_rst_n) begin
user_lnk_up_int <= #TCQ 1'b0;
end else begin
user_lnk_up_int <= #TCQ trn_lnk_up;
end
end
//------------------------------------------------------------------------------------------------------------------//
// Generate user_reset_out //
// Once user reset output of PCIE and Phy Layer is active, de-assert reset //
// Only assert reset if system reset or hot reset is seen. Keep AXI backend/user application alive otherwise //
//------------------------------------------------------------------------------------------------------------------//
always @(posedge user_clk_out or posedge sys_or_hot_rst)
begin
if (sys_or_hot_rst) begin
user_reset_int <= #TCQ 1'b1;
end else if (user_rst_n && pl_phy_lnk_up_q) begin
user_reset_int <= #TCQ 1'b0;
end
end
// Invert active low reset to active high AXI reset
always @(posedge user_clk_out or posedge sys_or_hot_rst)
begin
if (sys_or_hot_rst) begin
user_reset_out <= #TCQ 1'b1;
end else begin
user_reset_out <= #TCQ user_reset_int;
end
end
//------------------------------------------------------------------------------------------------------------------//
// **** PCI Express Core Wrapper **** //
// The PCI Express Core Wrapper includes the following: //
// 1) AXI Streaming Bridge //
// 2) PCIE 2_1 Hard Block //
// 3) PCIE PIPE Interface Pipeline //
//------------------------------------------------------------------------------------------------------------------//
pcie_7x_v1_3_pcie_top # (
.PIPE_PIPELINE_STAGES ( PIPE_PIPELINE_STAGES ),
.AER_BASE_PTR ( AER_BASE_PTR ),
.AER_CAP_ECRC_CHECK_CAPABLE ( AER_CAP_ECRC_CHECK_CAPABLE ),
.AER_CAP_ECRC_GEN_CAPABLE ( AER_CAP_ECRC_GEN_CAPABLE ),
.AER_CAP_ID ( AER_CAP_ID ),
.AER_CAP_MULTIHEADER ( AER_CAP_MULTIHEADER ),
.AER_CAP_NEXTPTR ( AER_CAP_NEXTPTR ),
.AER_CAP_ON ( AER_CAP_ON ),
.AER_CAP_OPTIONAL_ERR_SUPPORT ( AER_CAP_OPTIONAL_ERR_SUPPORT ),
.AER_CAP_PERMIT_ROOTERR_UPDATE ( AER_CAP_PERMIT_ROOTERR_UPDATE ),
.AER_CAP_VERSION ( AER_CAP_VERSION ),
.ALLOW_X8_GEN2 ( ALLOW_X8_GEN2 ),
.BAR0 ( BAR0 ),
.BAR1 ( BAR1 ),
.BAR2 ( BAR2 ),
.BAR3 ( BAR3 ),
.BAR4 ( BAR4 ),
.BAR5 ( BAR5 ),
.C_DATA_WIDTH ( C_DATA_WIDTH ),
.CAPABILITIES_PTR ( CAPABILITIES_PTR ),
.CARDBUS_CIS_POINTER ( CARDBUS_CIS_POINTER ),
.CFG_ECRC_ERR_CPLSTAT ( CFG_ECRC_ERR_CPLSTAT ),
.CLASS_CODE ( CLASS_CODE ),
.CMD_INTX_IMPLEMENTED ( CMD_INTX_IMPLEMENTED ),
.CPL_TIMEOUT_DISABLE_SUPPORTED ( CPL_TIMEOUT_DISABLE_SUPPORTED ),
.CPL_TIMEOUT_RANGES_SUPPORTED ( CPL_TIMEOUT_RANGES_SUPPORTED ),
.CRM_MODULE_RSTS ( CRM_MODULE_RSTS ),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ),
.DEV_CAP_ENDPOINT_L0S_LATENCY ( DEV_CAP_ENDPOINT_L0S_LATENCY ),
.DEV_CAP_ENDPOINT_L1_LATENCY ( DEV_CAP_ENDPOINT_L1_LATENCY ),
.DEV_CAP_EXT_TAG_SUPPORTED ( DEV_CAP_EXT_TAG_SUPPORTED ),
.DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ( DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ),
.DEV_CAP_MAX_PAYLOAD_SUPPORTED ( DEV_CAP_MAX_PAYLOAD_SUPPORTED ),
.DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ( DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ),
.DEV_CAP_ROLE_BASED_ERROR ( DEV_CAP_ROLE_BASED_ERROR ),
.DEV_CAP_RSVD_14_12 ( DEV_CAP_RSVD_14_12 ),
.DEV_CAP_RSVD_17_16 ( DEV_CAP_RSVD_17_16 ),
.DEV_CAP_RSVD_31_29 ( DEV_CAP_RSVD_31_29 ),
.DEV_CONTROL_AUX_POWER_SUPPORTED ( DEV_CONTROL_AUX_POWER_SUPPORTED ),
.DEV_CONTROL_EXT_TAG_DEFAULT ( DEV_CONTROL_EXT_TAG_DEFAULT ),
.DISABLE_ASPM_L1_TIMER ( DISABLE_ASPM_L1_TIMER ),
.DISABLE_BAR_FILTERING ( DISABLE_BAR_FILTERING ),
.DISABLE_ID_CHECK ( DISABLE_ID_CHECK ),
.DISABLE_LANE_REVERSAL ( DISABLE_LANE_REVERSAL ),
.DISABLE_RX_POISONED_RESP ( DISABLE_RX_POISONED_RESP ),
.DISABLE_RX_TC_FILTER ( DISABLE_RX_TC_FILTER ),
.DISABLE_SCRAMBLING ( DISABLE_SCRAMBLING ),
.DNSTREAM_LINK_NUM ( DNSTREAM_LINK_NUM ),
.DSN_BASE_PTR ( DSN_BASE_PTR ),
.DSN_CAP_ID ( DSN_CAP_ID ),
.DSN_CAP_NEXTPTR ( DSN_CAP_NEXTPTR ),
.DSN_CAP_ON ( DSN_CAP_ON ),
.DSN_CAP_VERSION ( DSN_CAP_VERSION ),
.DEV_CAP2_ARI_FORWARDING_SUPPORTED ( DEV_CAP2_ARI_FORWARDING_SUPPORTED ),
.DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED ( DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED ),
.DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED ( DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED ),
.DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED ( DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED ),
.DEV_CAP2_CAS128_COMPLETER_SUPPORTED ( DEV_CAP2_CAS128_COMPLETER_SUPPORTED ),
.DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED ( DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED ),
.DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED ( DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED ),
.DEV_CAP2_LTR_MECHANISM_SUPPORTED ( DEV_CAP2_LTR_MECHANISM_SUPPORTED ),
.DEV_CAP2_MAX_ENDEND_TLP_PREFIXES ( DEV_CAP2_MAX_ENDEND_TLP_PREFIXES ),
.DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING ( DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING ),
.DEV_CAP2_TPH_COMPLETER_SUPPORTED ( DEV_CAP2_TPH_COMPLETER_SUPPORTED ),
.DISABLE_ERR_MSG ( DISABLE_ERR_MSG ),
.DISABLE_LOCKED_FILTER ( DISABLE_LOCKED_FILTER ),
.DISABLE_PPM_FILTER ( DISABLE_PPM_FILTER ),
.ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED ( ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED ),
.ENABLE_MSG_ROUTE ( ENABLE_MSG_ROUTE ),
.ENABLE_RX_TD_ECRC_TRIM ( ENABLE_RX_TD_ECRC_TRIM ),
.ENTER_RVRY_EI_L0 ( ENTER_RVRY_EI_L0 ),
.EXIT_LOOPBACK_ON_EI ( EXIT_LOOPBACK_ON_EI ),
.EXPANSION_ROM ( EXPANSION_ROM ),
.EXT_CFG_CAP_PTR ( EXT_CFG_CAP_PTR ),
.EXT_CFG_XP_CAP_PTR ( EXT_CFG_XP_CAP_PTR ),
.HEADER_TYPE ( HEADER_TYPE ),
.INFER_EI ( INFER_EI ),
.INTERRUPT_PIN ( INTERRUPT_PIN ),
.INTERRUPT_STAT_AUTO ( INTERRUPT_STAT_AUTO ),
.IS_SWITCH ( IS_SWITCH ),
.LAST_CONFIG_DWORD ( LAST_CONFIG_DWORD ),
.LINK_CAP_ASPM_OPTIONALITY ( LINK_CAP_ASPM_OPTIONALITY ),
.LINK_CAP_ASPM_SUPPORT ( LINK_CAP_ASPM_SUPPORT ),
.LINK_CAP_CLOCK_POWER_MANAGEMENT ( LINK_CAP_CLOCK_POWER_MANAGEMENT ),
.LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ( LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ),
.LINK_CAP_L0S_EXIT_LATENCY_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_GEN1 ),
.LINK_CAP_L0S_EXIT_LATENCY_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_GEN2 ),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ),
.LINK_CAP_L1_EXIT_LATENCY_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_GEN1 ),
.LINK_CAP_L1_EXIT_LATENCY_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_GEN2 ),
.LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ( LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ),
.LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ),
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.LINK_CAP_RSVD_23 ( LINK_CAP_RSVD_23 ),
.LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ( LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ),
.LINK_CONTROL_RCB ( LINK_CONTROL_RCB ),
.LINK_CTRL2_DEEMPHASIS ( LINK_CTRL2_DEEMPHASIS ),
.LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ( LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ),
.LINK_CTRL2_TARGET_LINK_SPEED ( LINK_CTRL2_TARGET_LINK_SPEED ),
.LINK_STATUS_SLOT_CLOCK_CONFIG ( LINK_STATUS_SLOT_CLOCK_CONFIG ),
.LL_ACK_TIMEOUT ( LL_ACK_TIMEOUT ),
.LL_ACK_TIMEOUT_EN ( LL_ACK_TIMEOUT_EN ),
.LL_ACK_TIMEOUT_FUNC ( LL_ACK_TIMEOUT_FUNC ),
.LL_REPLAY_TIMEOUT ( LL_REPLAY_TIMEOUT ),
.LL_REPLAY_TIMEOUT_EN ( LL_REPLAY_TIMEOUT_EN ),
.LL_REPLAY_TIMEOUT_FUNC ( LL_REPLAY_TIMEOUT_FUNC ),
.LTSSM_MAX_LINK_WIDTH ( LTSSM_MAX_LINK_WIDTH ),
.MPS_FORCE ( MPS_FORCE),
.MSI_BASE_PTR ( MSI_BASE_PTR ),
.MSI_CAP_ID ( MSI_CAP_ID ),
.MSI_CAP_MULTIMSGCAP ( MSI_CAP_MULTIMSGCAP ),
.MSI_CAP_MULTIMSG_EXTENSION ( MSI_CAP_MULTIMSG_EXTENSION ),
.MSI_CAP_NEXTPTR ( MSI_CAP_NEXTPTR ),
.MSI_CAP_ON ( MSI_CAP_ON ),
.MSI_CAP_PER_VECTOR_MASKING_CAPABLE ( MSI_CAP_PER_VECTOR_MASKING_CAPABLE ),
.MSI_CAP_64_BIT_ADDR_CAPABLE ( MSI_CAP_64_BIT_ADDR_CAPABLE ),
.MSIX_BASE_PTR ( MSIX_BASE_PTR ),
.MSIX_CAP_ID ( MSIX_CAP_ID ),
.MSIX_CAP_NEXTPTR ( MSIX_CAP_NEXTPTR ),
.MSIX_CAP_ON ( MSIX_CAP_ON ),
.MSIX_CAP_PBA_BIR ( MSIX_CAP_PBA_BIR ),
.MSIX_CAP_PBA_OFFSET ( MSIX_CAP_PBA_OFFSET ),
.MSIX_CAP_TABLE_BIR ( MSIX_CAP_TABLE_BIR ),
.MSIX_CAP_TABLE_OFFSET ( MSIX_CAP_TABLE_OFFSET ),
.MSIX_CAP_TABLE_SIZE ( MSIX_CAP_TABLE_SIZE ),
.N_FTS_COMCLK_GEN1 ( N_FTS_COMCLK_GEN1 ),
.N_FTS_COMCLK_GEN2 ( N_FTS_COMCLK_GEN2 ),
.N_FTS_GEN1 ( N_FTS_GEN1 ),
.N_FTS_GEN2 ( N_FTS_GEN2 ),
.PCIE_BASE_PTR ( PCIE_BASE_PTR ),
.PCIE_CAP_CAPABILITY_ID ( PCIE_CAP_CAPABILITY_ID ),
.PCIE_CAP_CAPABILITY_VERSION ( PCIE_CAP_CAPABILITY_VERSION ),
.PCIE_CAP_DEVICE_PORT_TYPE ( PCIE_CAP_DEVICE_PORT_TYPE ),
.PCIE_CAP_NEXTPTR ( PCIE_CAP_NEXTPTR ),
.PCIE_CAP_ON ( PCIE_CAP_ON ),
.PCIE_CAP_RSVD_15_14 ( PCIE_CAP_RSVD_15_14 ),
.PCIE_CAP_SLOT_IMPLEMENTED ( PCIE_CAP_SLOT_IMPLEMENTED ),
.PCIE_REVISION ( PCIE_REVISION ),
.PL_AUTO_CONFIG ( PL_AUTO_CONFIG ),
.PL_FAST_TRAIN ( PL_FAST_TRAIN ),
.PM_ASPML0S_TIMEOUT ( PM_ASPML0S_TIMEOUT ),
.PM_ASPML0S_TIMEOUT_EN ( PM_ASPML0S_TIMEOUT_EN ),
.PM_ASPML0S_TIMEOUT_FUNC ( PM_ASPML0S_TIMEOUT_FUNC ),
.PM_ASPM_FASTEXIT ( PM_ASPM_FASTEXIT ),
.PM_BASE_PTR ( PM_BASE_PTR ),
.PM_CAP_AUXCURRENT ( PM_CAP_AUXCURRENT ),
.PM_CAP_D1SUPPORT ( PM_CAP_D1SUPPORT ),
.PM_CAP_D2SUPPORT ( PM_CAP_D2SUPPORT ),
.PM_CAP_DSI ( PM_CAP_DSI ),
.PM_CAP_ID ( PM_CAP_ID ),
.PM_CAP_NEXTPTR ( PM_CAP_NEXTPTR ),
.PM_CAP_ON ( PM_CAP_ON ),
.PM_CAP_PME_CLOCK ( PM_CAP_PME_CLOCK ),
.PM_CAP_PMESUPPORT ( PM_CAP_PMESUPPORT ),
.PM_CAP_RSVD_04 ( PM_CAP_RSVD_04 ),
.PM_CAP_VERSION ( PM_CAP_VERSION ),
.PM_CSR_B2B3 ( PM_CSR_B2B3 ),
.PM_CSR_BPCCEN ( PM_CSR_BPCCEN ),
.PM_CSR_NOSOFTRST ( PM_CSR_NOSOFTRST ),
.PM_DATA0 ( PM_DATA0 ),
.PM_DATA1 ( PM_DATA1 ),
.PM_DATA2 ( PM_DATA2 ),
.PM_DATA3 ( PM_DATA3 ),
.PM_DATA4 ( PM_DATA4 ),
.PM_DATA5 ( PM_DATA5 ),
.PM_DATA6 ( PM_DATA6 ),
.PM_DATA7 ( PM_DATA7 ),
.PM_DATA_SCALE0 ( PM_DATA_SCALE0 ),
.PM_DATA_SCALE1 ( PM_DATA_SCALE1 ),
.PM_DATA_SCALE2 ( PM_DATA_SCALE2 ),
.PM_DATA_SCALE3 ( PM_DATA_SCALE3 ),
.PM_DATA_SCALE4 ( PM_DATA_SCALE4 ),
.PM_DATA_SCALE5 ( PM_DATA_SCALE5 ),
.PM_DATA_SCALE6 ( PM_DATA_SCALE6 ),
.PM_DATA_SCALE7 ( PM_DATA_SCALE7 ),
.PM_MF ( PM_MF ),
.RBAR_BASE_PTR ( RBAR_BASE_PTR ),
.RBAR_CAP_CONTROL_ENCODEDBAR0 ( RBAR_CAP_CONTROL_ENCODEDBAR0 ),
.RBAR_CAP_CONTROL_ENCODEDBAR1 ( RBAR_CAP_CONTROL_ENCODEDBAR1 ),
.RBAR_CAP_CONTROL_ENCODEDBAR2 ( RBAR_CAP_CONTROL_ENCODEDBAR2 ),
.RBAR_CAP_CONTROL_ENCODEDBAR3 ( RBAR_CAP_CONTROL_ENCODEDBAR3 ),
.RBAR_CAP_CONTROL_ENCODEDBAR4 ( RBAR_CAP_CONTROL_ENCODEDBAR4 ),
.RBAR_CAP_CONTROL_ENCODEDBAR5 ( RBAR_CAP_CONTROL_ENCODEDBAR5 ),
.RBAR_CAP_ID ( RBAR_CAP_ID),
.RBAR_CAP_INDEX0 ( RBAR_CAP_INDEX0 ),
.RBAR_CAP_INDEX1 ( RBAR_CAP_INDEX1 ),
.RBAR_CAP_INDEX2 ( RBAR_CAP_INDEX2 ),
.RBAR_CAP_INDEX3 ( RBAR_CAP_INDEX3 ),
.RBAR_CAP_INDEX4 ( RBAR_CAP_INDEX4 ),
.RBAR_CAP_INDEX5 ( RBAR_CAP_INDEX5 ),
.RBAR_CAP_NEXTPTR ( RBAR_CAP_NEXTPTR ),
.RBAR_CAP_ON ( RBAR_CAP_ON ),
.RBAR_CAP_SUP0 ( RBAR_CAP_SUP0 ),
.RBAR_CAP_SUP1 ( RBAR_CAP_SUP1 ),
.RBAR_CAP_SUP2 ( RBAR_CAP_SUP2 ),
.RBAR_CAP_SUP3 ( RBAR_CAP_SUP3 ),
.RBAR_CAP_SUP4 ( RBAR_CAP_SUP4 ),
.RBAR_CAP_SUP5 ( RBAR_CAP_SUP5 ),
.RBAR_CAP_VERSION ( RBAR_CAP_VERSION ),
.RBAR_NUM ( RBAR_NUM ),
.RECRC_CHK ( RECRC_CHK ),
.RECRC_CHK_TRIM ( RECRC_CHK_TRIM ),
.ROOT_CAP_CRS_SW_VISIBILITY ( ROOT_CAP_CRS_SW_VISIBILITY ),
.RP_AUTO_SPD ( RP_AUTO_SPD ),
.RP_AUTO_SPD_LOOPCNT ( RP_AUTO_SPD_LOOPCNT ),
.SELECT_DLL_IF ( SELECT_DLL_IF ),
.SLOT_CAP_ATT_BUTTON_PRESENT ( SLOT_CAP_ATT_BUTTON_PRESENT ),
.SLOT_CAP_ATT_INDICATOR_PRESENT ( SLOT_CAP_ATT_INDICATOR_PRESENT ),
.SLOT_CAP_ELEC_INTERLOCK_PRESENT ( SLOT_CAP_ELEC_INTERLOCK_PRESENT ),
.SLOT_CAP_HOTPLUG_CAPABLE ( SLOT_CAP_HOTPLUG_CAPABLE ),
.SLOT_CAP_HOTPLUG_SURPRISE ( SLOT_CAP_HOTPLUG_SURPRISE ),
.SLOT_CAP_MRL_SENSOR_PRESENT ( SLOT_CAP_MRL_SENSOR_PRESENT ),
.SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ( SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ),
.SLOT_CAP_PHYSICAL_SLOT_NUM ( SLOT_CAP_PHYSICAL_SLOT_NUM ),
.SLOT_CAP_POWER_CONTROLLER_PRESENT ( SLOT_CAP_POWER_CONTROLLER_PRESENT ),
.SLOT_CAP_POWER_INDICATOR_PRESENT ( SLOT_CAP_POWER_INDICATOR_PRESENT ),
.SLOT_CAP_SLOT_POWER_LIMIT_SCALE ( SLOT_CAP_SLOT_POWER_LIMIT_SCALE ),
.SLOT_CAP_SLOT_POWER_LIMIT_VALUE ( SLOT_CAP_SLOT_POWER_LIMIT_VALUE ),
.SPARE_BIT0 ( SPARE_BIT0 ),
.SPARE_BIT1 ( SPARE_BIT1 ),
.SPARE_BIT2 ( SPARE_BIT2 ),
.SPARE_BIT3 ( SPARE_BIT3 ),
.SPARE_BIT4 ( SPARE_BIT4 ),
.SPARE_BIT5 ( SPARE_BIT5 ),
.SPARE_BIT6 ( SPARE_BIT6 ),
.SPARE_BIT7 ( SPARE_BIT7 ),
.SPARE_BIT8 ( SPARE_BIT8 ),
.SPARE_BYTE0 ( SPARE_BYTE0 ),
.SPARE_BYTE1 ( SPARE_BYTE1 ),
.SPARE_BYTE2 ( SPARE_BYTE2 ),
.SPARE_BYTE3 ( SPARE_BYTE3 ),
.SPARE_WORD0 ( SPARE_WORD0 ),
.SPARE_WORD1 ( SPARE_WORD1 ),
.SPARE_WORD2 ( SPARE_WORD2 ),
.SPARE_WORD3 ( SPARE_WORD3 ),
.SSL_MESSAGE_AUTO ( SSL_MESSAGE_AUTO ),
.TECRC_EP_INV ( TECRC_EP_INV ),
.TL_RBYPASS ( TL_RBYPASS ),
.TL_RX_RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ),
.TL_RX_RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ),
.TL_RX_RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY ),
.TL_TFC_DISABLE ( TL_TFC_DISABLE ),
.TL_TX_CHECKS_DISABLE ( TL_TX_CHECKS_DISABLE ),
.TL_TX_RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ),
.TL_TX_RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ),
.TL_TX_RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY ),
.TRN_DW ( TRN_DW ),
.TRN_NP_FC ( TRN_NP_FC ),
.UPCONFIG_CAPABLE ( UPCONFIG_CAPABLE ),
.UPSTREAM_FACING ( UPSTREAM_FACING ),
.UR_ATOMIC ( UR_ATOMIC ),
.UR_CFG1 ( UR_CFG1 ),
.UR_INV_REQ ( UR_INV_REQ ),
.UR_PRS_RESPONSE ( UR_PRS_RESPONSE ),
.USER_CLK2_DIV2 ( USER_CLK2_DIV2 ),
.USER_CLK_FREQ ( USER_CLK_FREQ ),
.USE_RID_PINS ( USE_RID_PINS ),
.VC0_CPL_INFINITE ( VC0_CPL_INFINITE ),
.VC0_RX_RAM_LIMIT ( VC0_RX_RAM_LIMIT ),
.VC0_TOTAL_CREDITS_CD ( VC0_TOTAL_CREDITS_CD ),
.VC0_TOTAL_CREDITS_CH ( VC0_TOTAL_CREDITS_CH ),
.VC0_TOTAL_CREDITS_NPD ( VC0_TOTAL_CREDITS_NPD),
.VC0_TOTAL_CREDITS_NPH ( VC0_TOTAL_CREDITS_NPH ),
.VC0_TOTAL_CREDITS_PD ( VC0_TOTAL_CREDITS_PD ),
.VC0_TOTAL_CREDITS_PH ( VC0_TOTAL_CREDITS_PH ),
.VC0_TX_LASTPACKET ( VC0_TX_LASTPACKET ),
.VC_BASE_PTR ( VC_BASE_PTR ),
.VC_CAP_ID ( VC_CAP_ID ),
.VC_CAP_NEXTPTR ( VC_CAP_NEXTPTR ),
.VC_CAP_ON ( VC_CAP_ON ),
.VC_CAP_REJECT_SNOOP_TRANSACTIONS ( VC_CAP_REJECT_SNOOP_TRANSACTIONS ),
.VC_CAP_VERSION ( VC_CAP_VERSION ),
.VSEC_BASE_PTR ( VSEC_BASE_PTR ),
.VSEC_CAP_HDR_ID ( VSEC_CAP_HDR_ID ),
.VSEC_CAP_HDR_LENGTH ( VSEC_CAP_HDR_LENGTH ),
.VSEC_CAP_HDR_REVISION ( VSEC_CAP_HDR_REVISION ),
.VSEC_CAP_ID ( VSEC_CAP_ID ),
.VSEC_CAP_IS_LINK_VISIBLE ( VSEC_CAP_IS_LINK_VISIBLE ),
.VSEC_CAP_NEXTPTR ( VSEC_CAP_NEXTPTR ),
.VSEC_CAP_ON ( VSEC_CAP_ON ),
.VSEC_CAP_VERSION ( VSEC_CAP_VERSION )
// I/O
) pcie_top_i (
// AXI Interface
.user_clk_out ( user_clk_out ),
.user_reset ( user_reset_out ),
.user_lnk_up ( user_lnk_up ),
.user_rst_n ( user_rst_n ),
.trn_lnk_up ( trn_lnk_up ),
.tx_buf_av ( tx_buf_av ),
.tx_err_drop ( tx_err_drop ),
.tx_cfg_req ( tx_cfg_req ),
.s_axis_tx_tready ( s_axis_tx_tready ),
.s_axis_tx_tdata ( s_axis_tx_tdata ),
.s_axis_tx_tkeep ( s_axis_tx_tkeep ),
.s_axis_tx_tuser ( s_axis_tx_tuser ),
.s_axis_tx_tlast ( s_axis_tx_tlast),
.s_axis_tx_tvalid ( s_axis_tx_tvalid ),
.tx_cfg_gnt ( tx_cfg_gnt ),
.m_axis_rx_tdata ( m_axis_rx_tdata ),
.m_axis_rx_tkeep ( m_axis_rx_tkeep ),
.m_axis_rx_tlast ( m_axis_rx_tlast ),
.m_axis_rx_tvalid ( m_axis_rx_tvalid ),
.m_axis_rx_tready ( m_axis_rx_tready ),
.m_axis_rx_tuser ( m_axis_rx_tuser ),
.rx_np_ok ( rx_np_ok ),
.rx_np_req ( rx_np_req ),
.fc_cpld ( fc_cpld ),
.fc_cplh ( fc_cplh ),
.fc_npd ( fc_npd ),
.fc_nph ( fc_nph ),
.fc_pd ( fc_pd ),
.fc_ph ( fc_ph ),
.fc_sel ( fc_sel ),
.cfg_turnoff_ok ( cfg_turnoff_ok ),
.cfg_received_func_lvl_rst ( cfg_received_func_lvl_rst ),
.cm_rst_n ( 1'b1 ),
.func_lvl_rst_n ( 1'b1 ),
.cfg_dev_id ( cfg_dev_id ),
.cfg_vend_id ( cfg_vend_id ),
.cfg_rev_id ( cfg_rev_id ),
.cfg_subsys_id ( cfg_subsys_id ),
.cfg_subsys_vend_id ( cfg_subsys_vend_id ),
.cfg_pciecap_interrupt_msgnum ( cfg_pciecap_interrupt_msgnum ),
.cfg_bridge_serr_en ( cfg_bridge_serr_en ),
.cfg_command_bus_master_enable ( ),
.cfg_command_interrupt_disable ( ),
.cfg_command_io_enable ( ),
.cfg_command_mem_enable ( ),
.cfg_command_serr_en ( ),
.cfg_dev_control_aux_power_en ( ),
.cfg_dev_control_corr_err_reporting_en ( ),
.cfg_dev_control_enable_ro ( ),
.cfg_dev_control_ext_tag_en ( ),
.cfg_dev_control_fatal_err_reporting_en ( ),
.cfg_dev_control_max_payload ( ),
.cfg_dev_control_max_read_req ( ),
.cfg_dev_control_non_fatal_reporting_en ( ),
.cfg_dev_control_no_snoop_en ( ),
.cfg_dev_control_phantom_en ( ),
.cfg_dev_control_ur_err_reporting_en ( ),
.cfg_dev_control2_cpl_timeout_dis ( ),
.cfg_dev_control2_cpl_timeout_val ( ),
.cfg_dev_control2_ari_forward_en ( ),
.cfg_dev_control2_atomic_requester_en ( ),
.cfg_dev_control2_atomic_egress_block ( ),
.cfg_dev_control2_ido_req_en ( ),
.cfg_dev_control2_ido_cpl_en ( ),
.cfg_dev_control2_ltr_en ( ),
.cfg_dev_control2_tlp_prefix_block ( ),
.cfg_dev_status_corr_err_detected ( ),
.cfg_dev_status_fatal_err_detected ( ),
.cfg_dev_status_non_fatal_err_detected ( ),
.cfg_dev_status_ur_detected ( ),
.cfg_mgmt_do ( cfg_mgmt_do ),
.cfg_err_aer_headerlog_set ( cfg_err_aer_headerlog_set ),
.cfg_err_aer_headerlog ( cfg_err_aer_headerlog ),
.cfg_err_cpl_rdy ( cfg_err_cpl_rdy ),
.cfg_interrupt_do ( cfg_interrupt_do ),
.cfg_interrupt_mmenable ( cfg_interrupt_mmenable ),
.cfg_interrupt_msienable ( cfg_interrupt_msienable ),
.cfg_interrupt_msixenable ( cfg_interrupt_msixenable ),
.cfg_interrupt_msixfm ( cfg_interrupt_msixfm ),
.cfg_interrupt_rdy ( cfg_interrupt_rdy ),
.cfg_link_control_rcb ( ),
.cfg_link_control_aspm_control ( ),
.cfg_link_control_auto_bandwidth_int_en ( ),
.cfg_link_control_bandwidth_int_en ( ),
.cfg_link_control_clock_pm_en ( ),
.cfg_link_control_common_clock ( ),
.cfg_link_control_extended_sync ( ),
.cfg_link_control_hw_auto_width_dis ( ),
.cfg_link_control_link_disable ( ),
.cfg_link_control_retrain_link ( ),
.cfg_link_status_auto_bandwidth_status ( ),
.cfg_link_status_bandwidth_status ( ),
.cfg_link_status_current_speed ( ),
.cfg_link_status_dll_active ( ),
.cfg_link_status_link_training ( ),
.cfg_link_status_negotiated_width ( ),
.cfg_msg_data ( cfg_msg_data ),
.cfg_msg_received ( cfg_msg_received ),
.cfg_msg_received_assert_int_a ( cfg_msg_received_assert_int_a ),
.cfg_msg_received_assert_int_b ( cfg_msg_received_assert_int_b ),
.cfg_msg_received_assert_int_c ( cfg_msg_received_assert_int_c ),
.cfg_msg_received_assert_int_d ( cfg_msg_received_assert_int_d ),
.cfg_msg_received_deassert_int_a ( cfg_msg_received_deassert_int_a ),
.cfg_msg_received_deassert_int_b ( cfg_msg_received_deassert_int_b ),
.cfg_msg_received_deassert_int_c ( cfg_msg_received_deassert_int_c ),
.cfg_msg_received_deassert_int_d ( cfg_msg_received_deassert_int_d ),
.cfg_msg_received_err_cor ( cfg_msg_received_err_cor ),
.cfg_msg_received_err_fatal ( cfg_msg_received_err_fatal ),
.cfg_msg_received_err_non_fatal ( cfg_msg_received_err_non_fatal ),
.cfg_msg_received_pm_as_nak ( cfg_msg_received_pm_as_nak ),
.cfg_msg_received_pme_to ( ),
.cfg_msg_received_pme_to_ack ( cfg_msg_received_pme_to_ack ),
.cfg_msg_received_pm_pme ( cfg_msg_received_pm_pme ),
.cfg_msg_received_setslotpowerlimit ( cfg_msg_received_setslotpowerlimit ),
.cfg_msg_received_unlock ( ),
.cfg_to_turnoff ( cfg_to_turnoff ),
.cfg_status ( cfg_status ),
.cfg_command ( cfg_command ),
.cfg_dstatus ( cfg_dstatus ),
.cfg_dcommand ( cfg_dcommand ),
.cfg_lstatus ( cfg_lstatus ),
.cfg_lcommand ( cfg_lcommand ),
.cfg_dcommand2 ( cfg_dcommand2 ),
.cfg_pcie_link_state ( cfg_pcie_link_state ),
.cfg_pmcsr_pme_en ( cfg_pmcsr_pme_en ),
.cfg_pmcsr_powerstate ( cfg_pmcsr_powerstate ),
.cfg_pmcsr_pme_status ( cfg_pmcsr_pme_status ),
.cfg_pm_rcv_as_req_l1_n ( ),
.cfg_pm_rcv_enter_l1_n ( ),
.cfg_pm_rcv_enter_l23_n ( ),
.cfg_pm_rcv_req_ack_n ( ),
.cfg_mgmt_rd_wr_done ( cfg_mgmt_rd_wr_done ),
.cfg_slot_control_electromech_il_ctl_pulse ( cfg_slot_control_electromech_il_ctl_pulse ),
.cfg_root_control_syserr_corr_err_en ( cfg_root_control_syserr_corr_err_en ),
.cfg_root_control_syserr_non_fatal_err_en ( cfg_root_control_syserr_non_fatal_err_en ),
.cfg_root_control_syserr_fatal_err_en ( cfg_root_control_syserr_fatal_err_en ),
.cfg_root_control_pme_int_en ( cfg_root_control_pme_int_en),
.cfg_aer_ecrc_check_en ( cfg_aer_ecrc_check_en ),
.cfg_aer_ecrc_gen_en ( cfg_aer_ecrc_gen_en ),
.cfg_aer_rooterr_corr_err_reporting_en ( cfg_aer_rooterr_corr_err_reporting_en ),
.cfg_aer_rooterr_non_fatal_err_reporting_en ( cfg_aer_rooterr_non_fatal_err_reporting_en ),
.cfg_aer_rooterr_fatal_err_reporting_en ( cfg_aer_rooterr_fatal_err_reporting_en ),
.cfg_aer_rooterr_corr_err_received ( cfg_aer_rooterr_corr_err_received ),
.cfg_aer_rooterr_non_fatal_err_received ( cfg_aer_rooterr_non_fatal_err_received ),
.cfg_aer_rooterr_fatal_err_received ( cfg_aer_rooterr_fatal_err_received ),
.cfg_aer_interrupt_msgnum ( cfg_aer_interrupt_msgnum ),
.cfg_transaction ( ),
.cfg_transaction_addr ( ),
.cfg_transaction_type ( ),
.cfg_vc_tcvc_map ( cfg_vc_tcvc_map ),
.cfg_mgmt_byte_en_n ( ~cfg_mgmt_byte_en ),
.cfg_mgmt_di ( cfg_mgmt_di ),
.cfg_dsn ( cfg_dsn ),
.cfg_mgmt_dwaddr ( cfg_mgmt_dwaddr ),
.cfg_err_acs_n ( 1'b1 ),
.cfg_err_cor_n ( ~cfg_err_cor ),
.cfg_err_cpl_abort_n ( ~cfg_err_cpl_abort ),
.cfg_err_cpl_timeout_n ( ~cfg_err_cpl_timeout ),
.cfg_err_cpl_unexpect_n ( ~cfg_err_cpl_unexpect ),
.cfg_err_ecrc_n ( ~cfg_err_ecrc ),
.cfg_err_locked_n ( ~cfg_err_locked ),
.cfg_err_posted_n ( ~cfg_err_posted ),
.cfg_err_tlp_cpl_header ( cfg_err_tlp_cpl_header ),
.cfg_err_ur_n ( ~cfg_err_ur ),
.cfg_err_malformed_n ( ~cfg_err_malformed ),
.cfg_err_poisoned_n ( ~cfg_err_poisoned ),
.cfg_err_atomic_egress_blocked_n ( ~cfg_err_atomic_egress_blocked ),
.cfg_err_mc_blocked_n ( ~cfg_err_mc_blocked ),
.cfg_err_internal_uncor_n ( ~cfg_err_internal_uncor ),
.cfg_err_internal_cor_n ( ~cfg_err_internal_cor ),
.cfg_err_norecovery_n ( ~cfg_err_norecovery ),
.cfg_interrupt_assert_n ( ~cfg_interrupt_assert ),
.cfg_interrupt_di ( cfg_interrupt_di ),
.cfg_interrupt_n ( ~cfg_interrupt ),
.cfg_interrupt_stat_n ( ~cfg_interrupt_stat ),
.cfg_bus_number ( cfg_bus_number ),
.cfg_device_number ( cfg_device_number ),
.cfg_function_number ( cfg_function_number ),
.cfg_ds_bus_number ( cfg_ds_bus_number ),
.cfg_ds_device_number ( cfg_ds_device_number ),
.cfg_ds_function_number ( cfg_ds_function_number ),
.cfg_pm_send_pme_to_n ( 1'b1 ),
.cfg_pm_wake_n ( ~cfg_pm_wake ),
.cfg_pm_halt_aspm_l0s_n ( ~cfg_pm_halt_aspm_l0s ),
.cfg_pm_halt_aspm_l1_n ( ~cfg_pm_halt_aspm_l1 ),
.cfg_pm_force_state_en_n ( ~cfg_pm_force_state_en),
.cfg_pm_force_state ( cfg_pm_force_state ),
.cfg_force_mps ( 3'b0 ),
.cfg_force_common_clock_off ( 1'b0 ),
.cfg_force_extended_sync_on ( 1'b0 ),
.cfg_port_number ( 8'b0 ),
.cfg_mgmt_rd_en_n ( ~cfg_mgmt_rd_en ),
.cfg_trn_pending ( cfg_trn_pending ),
.cfg_mgmt_wr_en_n ( ~cfg_mgmt_wr_en ),
.cfg_mgmt_wr_readonly_n ( ~cfg_mgmt_wr_readonly ),
.cfg_mgmt_wr_rw1c_as_rw_n ( ~cfg_mgmt_wr_rw1c_as_rw ),
.pl_initial_link_width ( pl_initial_link_width ),
.pl_lane_reversal_mode ( pl_lane_reversal_mode ),
.pl_link_gen2_cap ( pl_link_gen2_cap ),
.pl_link_partner_gen2_supported ( pl_link_partner_gen2_supported ),
.pl_link_upcfg_cap ( pl_link_upcfg_cap ),
.pl_ltssm_state ( pl_ltssm_state_int ),
.pl_phy_lnk_up ( pl_phy_lnk_up_wire ),
.pl_received_hot_rst ( pl_received_hot_rst_wire ),
.pl_rx_pm_state ( pl_rx_pm_state ),
.pl_sel_lnk_rate ( pl_sel_lnk_rate ),
.pl_sel_lnk_width ( pl_sel_lnk_width ),
.pl_tx_pm_state ( pl_tx_pm_state ),
.pl_directed_link_auton ( pl_directed_link_auton ),
.pl_directed_link_change ( pl_directed_link_change ),
.pl_directed_link_speed ( pl_directed_link_speed ),
.pl_directed_link_width ( pl_directed_link_width ),
.pl_downstream_deemph_source ( pl_downstream_deemph_source ),
.pl_upstream_prefer_deemph ( pl_upstream_prefer_deemph ),
.pl_transmit_hot_rst ( pl_transmit_hot_rst ),
.pl_directed_ltssm_new_vld ( 1'b0 ),
.pl_directed_ltssm_new ( 6'b0 ),
.pl_directed_ltssm_stall ( 1'b0 ),
.pl_directed_change_done ( pl_directed_change_done ),
.phy_rdy_n ( phy_rdy_n ),
.dbg_sclr_a ( ),
.dbg_sclr_b ( ),
.dbg_sclr_c ( ),
.dbg_sclr_d ( ),
.dbg_sclr_e ( ),
.dbg_sclr_f ( ),
.dbg_sclr_g ( ),
.dbg_sclr_h ( ),
.dbg_sclr_i ( ),
.dbg_sclr_j ( ),
.dbg_sclr_k ( ),
.dbg_vec_a ( ),
.dbg_vec_b ( ),
.dbg_vec_c ( ),
.pl_dbg_vec ( ),
.trn_rdllp_data ( ),
.trn_rdllp_src_rdy ( ),
.dbg_mode ( ),
.dbg_sub_mode ( ),
.pl_dbg_mode ( ),
.drp_clk ( 1'b0 ),
.drp_do ( ),
.drp_rdy ( ),
.drp_addr ( 9'b0 ),
.drp_en ( 1'b0 ),
.drp_di ( 16'b0 ),
.drp_we ( 1'b0 ),
// Pipe Interface
.pipe_clk ( pipe_clk ),
.user_clk ( user_clk ),
.user_clk2 ( user_clk2 ),
.pipe_rx0_polarity_gt ( pipe_rx0_polarity_gt ),
.pipe_rx1_polarity_gt ( pipe_rx1_polarity_gt ),
.pipe_rx2_polarity_gt ( pipe_rx2_polarity_gt ),
.pipe_rx3_polarity_gt ( pipe_rx3_polarity_gt ),
.pipe_rx4_polarity_gt ( pipe_rx4_polarity_gt ),
.pipe_rx5_polarity_gt ( pipe_rx5_polarity_gt ),
.pipe_rx6_polarity_gt ( pipe_rx6_polarity_gt ),
.pipe_rx7_polarity_gt ( pipe_rx7_polarity_gt ),
.pipe_tx_deemph_gt ( pipe_tx_deemph_gt ),
.pipe_tx_margin_gt ( pipe_tx_margin_gt ),
.pipe_tx_rate_gt ( pipe_tx_rate_gt ),
.pipe_tx_rcvr_det_gt ( pipe_tx_rcvr_det_gt ),
.pipe_tx0_char_is_k_gt ( pipe_tx0_char_is_k_gt ),
.pipe_tx0_compliance_gt ( pipe_tx0_compliance_gt ),
.pipe_tx0_data_gt ( pipe_tx0_data_gt ),
.pipe_tx0_elec_idle_gt ( pipe_tx0_elec_idle_gt ),
.pipe_tx0_powerdown_gt ( pipe_tx0_powerdown_gt ),
.pipe_tx1_char_is_k_gt ( pipe_tx1_char_is_k_gt ),
.pipe_tx1_compliance_gt ( pipe_tx1_compliance_gt ),
.pipe_tx1_data_gt ( pipe_tx1_data_gt ),
.pipe_tx1_elec_idle_gt ( pipe_tx1_elec_idle_gt ),
.pipe_tx1_powerdown_gt ( pipe_tx1_powerdown_gt ),
.pipe_tx2_char_is_k_gt ( pipe_tx2_char_is_k_gt ),
.pipe_tx2_compliance_gt ( pipe_tx2_compliance_gt ),
.pipe_tx2_data_gt ( pipe_tx2_data_gt ),
.pipe_tx2_elec_idle_gt ( pipe_tx2_elec_idle_gt ),
.pipe_tx2_powerdown_gt ( pipe_tx2_powerdown_gt ),
.pipe_tx3_char_is_k_gt ( pipe_tx3_char_is_k_gt ),
.pipe_tx3_compliance_gt ( pipe_tx3_compliance_gt ),
.pipe_tx3_data_gt ( pipe_tx3_data_gt ),
.pipe_tx3_elec_idle_gt ( pipe_tx3_elec_idle_gt ),
.pipe_tx3_powerdown_gt ( pipe_tx3_powerdown_gt ),
.pipe_tx4_char_is_k_gt ( pipe_tx4_char_is_k_gt ),
.pipe_tx4_compliance_gt ( pipe_tx4_compliance_gt ),
.pipe_tx4_data_gt ( pipe_tx4_data_gt ),
.pipe_tx4_elec_idle_gt ( pipe_tx4_elec_idle_gt ),
.pipe_tx4_powerdown_gt ( pipe_tx4_powerdown_gt ),
.pipe_tx5_char_is_k_gt ( pipe_tx5_char_is_k_gt ),
.pipe_tx5_compliance_gt ( pipe_tx5_compliance_gt ),
.pipe_tx5_data_gt ( pipe_tx5_data_gt ),
.pipe_tx5_elec_idle_gt ( pipe_tx5_elec_idle_gt ),
.pipe_tx5_powerdown_gt ( pipe_tx5_powerdown_gt ),
.pipe_tx6_char_is_k_gt ( pipe_tx6_char_is_k_gt ),
.pipe_tx6_compliance_gt ( pipe_tx6_compliance_gt ),
.pipe_tx6_data_gt ( pipe_tx6_data_gt ),
.pipe_tx6_elec_idle_gt ( pipe_tx6_elec_idle_gt ),
.pipe_tx6_powerdown_gt ( pipe_tx6_powerdown_gt ),
.pipe_tx7_char_is_k_gt ( pipe_tx7_char_is_k_gt ),
.pipe_tx7_compliance_gt ( pipe_tx7_compliance_gt ),
.pipe_tx7_data_gt ( pipe_tx7_data_gt ),
.pipe_tx7_elec_idle_gt ( pipe_tx7_elec_idle_gt ),
.pipe_tx7_powerdown_gt ( pipe_tx7_powerdown_gt ),
.pipe_rx0_chanisaligned_gt ( pipe_rx0_chanisaligned_gt ),
.pipe_rx0_char_is_k_gt ( pipe_rx0_char_is_k_gt ),
.pipe_rx0_data_gt ( pipe_rx0_data_gt ),
.pipe_rx0_elec_idle_gt ( pipe_rx0_elec_idle_gt ),
.pipe_rx0_phy_status_gt ( pipe_rx0_phy_status_gt ),
.pipe_rx0_status_gt ( pipe_rx0_status_gt ),
.pipe_rx0_valid_gt ( pipe_rx0_valid_gt ),
.pipe_rx1_chanisaligned_gt ( pipe_rx1_chanisaligned_gt ),
.pipe_rx1_char_is_k_gt ( pipe_rx1_char_is_k_gt ),
.pipe_rx1_data_gt ( pipe_rx1_data_gt ),
.pipe_rx1_elec_idle_gt ( pipe_rx1_elec_idle_gt ),
.pipe_rx1_phy_status_gt ( pipe_rx1_phy_status_gt ),
.pipe_rx1_status_gt ( pipe_rx1_status_gt ),
.pipe_rx1_valid_gt ( pipe_rx1_valid_gt ),
.pipe_rx2_chanisaligned_gt ( pipe_rx2_chanisaligned_gt ),
.pipe_rx2_char_is_k_gt ( pipe_rx2_char_is_k_gt ),
.pipe_rx2_data_gt ( pipe_rx2_data_gt ),
.pipe_rx2_elec_idle_gt ( pipe_rx2_elec_idle_gt ),
.pipe_rx2_phy_status_gt ( pipe_rx2_phy_status_gt ),
.pipe_rx2_status_gt ( pipe_rx2_status_gt ),
.pipe_rx2_valid_gt ( pipe_rx2_valid_gt ),
.pipe_rx3_chanisaligned_gt ( pipe_rx3_chanisaligned_gt ),
.pipe_rx3_char_is_k_gt ( pipe_rx3_char_is_k_gt ),
.pipe_rx3_data_gt ( pipe_rx3_data_gt ),
.pipe_rx3_elec_idle_gt ( pipe_rx3_elec_idle_gt ),
.pipe_rx3_phy_status_gt ( pipe_rx3_phy_status_gt ),
.pipe_rx3_status_gt ( pipe_rx3_status_gt ),
.pipe_rx3_valid_gt ( pipe_rx3_valid_gt ),
.pipe_rx4_chanisaligned_gt ( pipe_rx4_chanisaligned_gt ),
.pipe_rx4_char_is_k_gt ( pipe_rx4_char_is_k_gt ),
.pipe_rx4_data_gt ( pipe_rx4_data_gt ),
.pipe_rx4_elec_idle_gt ( pipe_rx4_elec_idle_gt ),
.pipe_rx4_phy_status_gt ( pipe_rx4_phy_status_gt ),
.pipe_rx4_status_gt ( pipe_rx4_status_gt ),
.pipe_rx4_valid_gt ( pipe_rx4_valid_gt ),
.pipe_rx5_chanisaligned_gt ( pipe_rx5_chanisaligned_gt ),
.pipe_rx5_char_is_k_gt ( pipe_rx5_char_is_k_gt ),
.pipe_rx5_data_gt ( pipe_rx5_data_gt ),
.pipe_rx5_elec_idle_gt ( pipe_rx5_elec_idle_gt ),
.pipe_rx5_phy_status_gt ( pipe_rx5_phy_status_gt ),
.pipe_rx5_status_gt ( pipe_rx5_status_gt ),
.pipe_rx5_valid_gt ( pipe_rx5_valid_gt ),
.pipe_rx6_chanisaligned_gt ( pipe_rx6_chanisaligned_gt ),
.pipe_rx6_char_is_k_gt ( pipe_rx6_char_is_k_gt ),
.pipe_rx6_data_gt ( pipe_rx6_data_gt ),
.pipe_rx6_elec_idle_gt ( pipe_rx6_elec_idle_gt ),
.pipe_rx6_phy_status_gt ( pipe_rx6_phy_status_gt ),
.pipe_rx6_status_gt ( pipe_rx6_status_gt ),
.pipe_rx6_valid_gt ( pipe_rx6_valid_gt ),
.pipe_rx7_chanisaligned_gt ( pipe_rx7_chanisaligned_gt ),
.pipe_rx7_char_is_k_gt ( pipe_rx7_char_is_k_gt ),
.pipe_rx7_data_gt ( pipe_rx7_data_gt ),
.pipe_rx7_elec_idle_gt ( pipe_rx7_elec_idle_gt ),
.pipe_rx7_phy_status_gt ( pipe_rx7_phy_status_gt ),
.pipe_rx7_status_gt ( pipe_rx7_status_gt ),
.pipe_rx7_valid_gt ( pipe_rx7_valid_gt )
);
//------------------------------------------------------------------------------------------------------------------//
// **** Virtex7 GTX Wrapper **** //
// The Virtex7 GTX Wrapper includes the following: //
// 1) Virtex-7 GTX //
//------------------------------------------------------------------------------------------------------------------//
pcie_7x_v1_3_gt_top #(
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.REF_CLK_FREQ ( REF_CLK_FREQ ),
.USER_CLK_FREQ ( USER_CLK_FREQ ),
.USER_CLK2_DIV2 ( USER_CLK2_DIV2 ),
.PL_FAST_TRAIN ( PL_FAST_TRAIN ),
.PCIE_EXT_CLK ( PCIE_EXT_CLK ),
.PCIE_USE_MODE ( PCIE_USE_MODE )
) gt_top_i (
// pl ltssm
.pl_ltssm_state ( pl_ltssm_state_int ),
// Pipe Common Signals
.pipe_tx_rcvr_det ( pipe_tx_rcvr_det_gt ),
.pipe_tx_reset ( 1'b0 ),
.pipe_tx_rate ( pipe_tx_rate_gt ),
.pipe_tx_deemph ( pipe_tx_deemph_gt ),
.pipe_tx_margin ( pipe_tx_margin_gt ),
.pipe_tx_swing ( 1'b0 ),
// Pipe Per-Lane Signals - Lane 0
.pipe_rx0_char_is_k ( pipe_rx0_char_is_k_gt),
.pipe_rx0_data ( pipe_rx0_data_gt ),
.pipe_rx0_valid ( pipe_rx0_valid_gt ),
.pipe_rx0_chanisaligned ( pipe_rx0_chanisaligned_gt ),
.pipe_rx0_status ( pipe_rx0_status_gt ),
.pipe_rx0_phy_status ( pipe_rx0_phy_status_gt ),
.pipe_rx0_elec_idle ( pipe_rx0_elec_idle_gt ),
.pipe_rx0_polarity ( pipe_rx0_polarity_gt ),
.pipe_tx0_compliance ( pipe_tx0_compliance_gt ),
.pipe_tx0_char_is_k ( pipe_tx0_char_is_k_gt ),
.pipe_tx0_data ( pipe_tx0_data_gt ),
.pipe_tx0_elec_idle ( pipe_tx0_elec_idle_gt ),
.pipe_tx0_powerdown ( pipe_tx0_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 1
.pipe_rx1_char_is_k ( pipe_rx1_char_is_k_gt),
.pipe_rx1_data ( pipe_rx1_data_gt ),
.pipe_rx1_valid ( pipe_rx1_valid_gt ),
.pipe_rx1_chanisaligned ( pipe_rx1_chanisaligned_gt ),
.pipe_rx1_status ( pipe_rx1_status_gt ),
.pipe_rx1_phy_status ( pipe_rx1_phy_status_gt ),
.pipe_rx1_elec_idle ( pipe_rx1_elec_idle_gt ),
.pipe_rx1_polarity ( pipe_rx1_polarity_gt ),
.pipe_tx1_compliance ( pipe_tx1_compliance_gt ),
.pipe_tx1_char_is_k ( pipe_tx1_char_is_k_gt ),
.pipe_tx1_data ( pipe_tx1_data_gt ),
.pipe_tx1_elec_idle ( pipe_tx1_elec_idle_gt ),
.pipe_tx1_powerdown ( pipe_tx1_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 2
.pipe_rx2_char_is_k ( pipe_rx2_char_is_k_gt),
.pipe_rx2_data ( pipe_rx2_data_gt ),
.pipe_rx2_valid ( pipe_rx2_valid_gt ),
.pipe_rx2_chanisaligned ( pipe_rx2_chanisaligned_gt ),
.pipe_rx2_status ( pipe_rx2_status_gt ),
.pipe_rx2_phy_status ( pipe_rx2_phy_status_gt ),
.pipe_rx2_elec_idle ( pipe_rx2_elec_idle_gt ),
.pipe_rx2_polarity ( pipe_rx2_polarity_gt ),
.pipe_tx2_compliance ( pipe_tx2_compliance_gt ),
.pipe_tx2_char_is_k ( pipe_tx2_char_is_k_gt ),
.pipe_tx2_data ( pipe_tx2_data_gt ),
.pipe_tx2_elec_idle ( pipe_tx2_elec_idle_gt ),
.pipe_tx2_powerdown ( pipe_tx2_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 3
.pipe_rx3_char_is_k ( pipe_rx3_char_is_k_gt),
.pipe_rx3_data ( pipe_rx3_data_gt ),
.pipe_rx3_valid ( pipe_rx3_valid_gt ),
.pipe_rx3_chanisaligned ( pipe_rx3_chanisaligned_gt ),
.pipe_rx3_status ( pipe_rx3_status_gt ),
.pipe_rx3_phy_status ( pipe_rx3_phy_status_gt ),
.pipe_rx3_elec_idle ( pipe_rx3_elec_idle_gt ),
.pipe_rx3_polarity ( pipe_rx3_polarity_gt ),
.pipe_tx3_compliance ( pipe_tx3_compliance_gt ),
.pipe_tx3_char_is_k ( pipe_tx3_char_is_k_gt ),
.pipe_tx3_data ( pipe_tx3_data_gt ),
.pipe_tx3_elec_idle ( pipe_tx3_elec_idle_gt ),
.pipe_tx3_powerdown ( pipe_tx3_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 4
.pipe_rx4_char_is_k ( pipe_rx4_char_is_k_gt),
.pipe_rx4_data ( pipe_rx4_data_gt ),
.pipe_rx4_valid ( pipe_rx4_valid_gt ),
.pipe_rx4_chanisaligned ( pipe_rx4_chanisaligned_gt ),
.pipe_rx4_status ( pipe_rx4_status_gt ),
.pipe_rx4_phy_status ( pipe_rx4_phy_status_gt ),
.pipe_rx4_elec_idle ( pipe_rx4_elec_idle_gt ),
.pipe_rx4_polarity ( pipe_rx4_polarity_gt ),
.pipe_tx4_compliance ( pipe_tx4_compliance_gt ),
.pipe_tx4_char_is_k ( pipe_tx4_char_is_k_gt ),
.pipe_tx4_data ( pipe_tx4_data_gt ),
.pipe_tx4_elec_idle ( pipe_tx4_elec_idle_gt ),
.pipe_tx4_powerdown ( pipe_tx4_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 5
.pipe_rx5_char_is_k ( pipe_rx5_char_is_k_gt),
.pipe_rx5_data ( pipe_rx5_data_gt ),
.pipe_rx5_valid ( pipe_rx5_valid_gt ),
.pipe_rx5_chanisaligned ( pipe_rx5_chanisaligned_gt ),
.pipe_rx5_status ( pipe_rx5_status_gt ),
.pipe_rx5_phy_status ( pipe_rx5_phy_status_gt ),
.pipe_rx5_elec_idle ( pipe_rx5_elec_idle_gt ),
.pipe_rx5_polarity ( pipe_rx5_polarity_gt ),
.pipe_tx5_compliance ( pipe_tx5_compliance_gt ),
.pipe_tx5_char_is_k ( pipe_tx5_char_is_k_gt ),
.pipe_tx5_data ( pipe_tx5_data_gt ),
.pipe_tx5_elec_idle ( pipe_tx5_elec_idle_gt ),
.pipe_tx5_powerdown ( pipe_tx5_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 6
.pipe_rx6_char_is_k ( pipe_rx6_char_is_k_gt),
.pipe_rx6_data ( pipe_rx6_data_gt ),
.pipe_rx6_valid ( pipe_rx6_valid_gt ),
.pipe_rx6_chanisaligned ( pipe_rx6_chanisaligned_gt ),
.pipe_rx6_status ( pipe_rx6_status_gt ),
.pipe_rx6_phy_status ( pipe_rx6_phy_status_gt ),
.pipe_rx6_elec_idle ( pipe_rx6_elec_idle_gt ),
.pipe_rx6_polarity ( pipe_rx6_polarity_gt ),
.pipe_tx6_compliance ( pipe_tx6_compliance_gt ),
.pipe_tx6_char_is_k ( pipe_tx6_char_is_k_gt ),
.pipe_tx6_data ( pipe_tx6_data_gt ),
.pipe_tx6_elec_idle ( pipe_tx6_elec_idle_gt ),
.pipe_tx6_powerdown ( pipe_tx6_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 7
.pipe_rx7_char_is_k ( pipe_rx7_char_is_k_gt),
.pipe_rx7_data ( pipe_rx7_data_gt ),
.pipe_rx7_valid ( pipe_rx7_valid_gt ),
.pipe_rx7_chanisaligned ( pipe_rx7_chanisaligned_gt ),
.pipe_rx7_status ( pipe_rx7_status_gt ),
.pipe_rx7_phy_status ( pipe_rx7_phy_status_gt ),
.pipe_rx7_elec_idle ( pipe_rx7_elec_idle_gt ),
.pipe_rx7_polarity ( pipe_rx7_polarity_gt ),
.pipe_tx7_compliance ( pipe_tx7_compliance_gt ),
.pipe_tx7_char_is_k ( pipe_tx7_char_is_k_gt ),
.pipe_tx7_data ( pipe_tx7_data_gt ),
.pipe_tx7_elec_idle ( pipe_tx7_elec_idle_gt ),
.pipe_tx7_powerdown ( pipe_tx7_powerdown_gt ),
// PCI Express Signals
.pci_exp_txn ( pci_exp_txn ),
.pci_exp_txp ( pci_exp_txp ),
.pci_exp_rxn ( pci_exp_rxn ),
.pci_exp_rxp ( pci_exp_rxp ),
// Non PIPE Signals
.sys_clk ( sys_clk ),
.sys_rst_n ( sys_rst_n ),
.pipe_clk ( pipe_clk ),
.user_clk ( user_clk ),
.user_clk2 ( user_clk2 ),
.phy_rdy_n ( phy_rdy_n ),
.PIPE_PCLK_IN ( PIPE_PCLK_IN ),
.PIPE_RXUSRCLK_IN ( PIPE_RXUSRCLK_IN ),
.PIPE_RXOUTCLK_IN ( PIPE_RXOUTCLK_IN ),
.PIPE_DCLK_IN ( PIPE_DCLK_IN ),
.PIPE_USERCLK1_IN ( PIPE_USERCLK1_IN ),
.PIPE_USERCLK2_IN ( PIPE_USERCLK2_IN ),
.PIPE_OOBCLK_IN ( PIPE_OOBCLK_IN ),
.PIPE_MMCM_LOCK_IN ( PIPE_MMCM_LOCK_IN ),
.PIPE_TXOUTCLK_OUT ( PIPE_TXOUTCLK_OUT ),
.PIPE_RXOUTCLK_OUT ( PIPE_RXOUTCLK_OUT ),
.PIPE_PCLK_SEL_OUT ( PIPE_PCLK_SEL_OUT ),
.PIPE_GEN3_OUT ( PIPE_GEN3_OUT )
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O22AI_1_V
`define SKY130_FD_SC_LP__O22AI_1_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o22ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o22ai_1 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o22ai_1 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O22AI_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND2_4_V
`define SKY130_FD_SC_MS__NAND2_4_V
/**
* nand2: 2-input NAND.
*
* Verilog wrapper for nand2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nand2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nand2_4 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nand2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nand2_4 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nand2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND2_4_V
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2014, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//
//-------------------------------------------------------------------
//
// Filename : fme_interpolator_8x8.v
// Author : Yufeng Bai
// Email : [email protected]
//
// $Id$
//
//-------------------------------------------------------------------
`include "enc_defines.v"
module fme_interpolator_8x8 (
clk ,
rstn ,
blk_start_i ,
half_ip_flag_i ,
mv_x_i ,
mv_y_i ,
frac_x_i ,
frac_y_i ,
blk_idx_i ,
mv_x_o ,
mv_y_o ,
blk_idx_o ,
half_ip_flag_o ,
ip_ready_o ,
end_ip_o ,
mc_end_ip_o ,
refpel_valid_i ,
ref_pel0_i ,
ref_pel1_i ,
ref_pel2_i ,
ref_pel3_i ,
ref_pel4_i ,
ref_pel5_i ,
ref_pel6_i ,
ref_pel7_i ,
ref_pel8_i ,
ref_pel9_i ,
ref_pel10_i ,
ref_pel11_i ,
ref_pel12_i ,
ref_pel13_i ,
ref_pel14_i ,
ref_pel15_i ,
satd_start_o ,
candi0_valid_o ,
candi1_valid_o ,
candi2_valid_o ,
candi3_valid_o ,
candi4_valid_o ,
candi5_valid_o ,
candi6_valid_o ,
candi7_valid_o ,
candi8_valid_o ,
candi0_pixles_o ,
candi1_pixles_o ,
candi2_pixles_o ,
candi3_pixles_o ,
candi4_pixles_o ,
candi5_pixles_o ,
candi6_pixles_o ,
candi7_pixles_o ,
candi8_pixles_o
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input [1-1:0] clk ; // clk signal
input [1-1:0] rstn ; // asynchronous reset
input [1-1:0] blk_start_i ; // 8x8 block interpolation start signal
input [1-1:0] half_ip_flag_i ; // specify whtether half/quarter interpolation
input signed [`FMV_WIDTH-1:0] mv_x_i ; // mv_x input //
input signed [`FMV_WIDTH-1:0] mv_y_i ; // mv_x input //
input [2-1:0] frac_x_i ; // frac_y input , used for quarter interpolation
input [2-1:0] frac_y_i ; // frac_y input , used for quarter interpolation
input [6-1:0] blk_idx_i ; // index of the 8x8 block which is processed
output signed [`FMV_WIDTH-1:0] mv_x_o ; // mv_x output for satd module // x: ==0
output signed [`FMV_WIDTH-1:0] mv_y_o ; // mv_y output for satd module // 0x: ==0
output [6-1:0] blk_idx_o ; // index of the 8x8 block which is processed : pass to satd gen.
output [1-1:0] half_ip_flag_o ; // half_ip_flag: pass to satd gen
output [1-1:0] ip_ready_o ; // first interpolaton data ready : load data for satd
output [1-1:0] end_ip_o ; // interpolation done
output [1-1:0] mc_end_ip_o ; // all block interpolation done
input [1-1:0] refpel_valid_i ; // referrenced pixel valid
input [`PIXEL_WIDTH-1:0] ref_pel0_i ; // ref_pel0
input [`PIXEL_WIDTH-1:0] ref_pel1_i ; // ref_pel1
input [`PIXEL_WIDTH-1:0] ref_pel2_i ; // ref_pel2
input [`PIXEL_WIDTH-1:0] ref_pel3_i ; // ref_pel3
input [`PIXEL_WIDTH-1:0] ref_pel4_i ; // ref_pel4
input [`PIXEL_WIDTH-1:0] ref_pel5_i ; // ref_pel5
input [`PIXEL_WIDTH-1:0] ref_pel6_i ; // ref_pel6
input [`PIXEL_WIDTH-1:0] ref_pel7_i ; // ref_pel7
input [`PIXEL_WIDTH-1:0] ref_pel8_i ; // ref_pel8
input [`PIXEL_WIDTH-1:0] ref_pel9_i ; // ref_pel9
input [`PIXEL_WIDTH-1:0] ref_pel10_i ; // ref_pel10
input [`PIXEL_WIDTH-1:0] ref_pel11_i ; // ref_pel11
input [`PIXEL_WIDTH-1:0] ref_pel12_i ; // ref_pel12o
input [`PIXEL_WIDTH-1:0] ref_pel13_i ; // ref_pel13o
input [`PIXEL_WIDTH-1:0] ref_pel14_i ; // ref_pel14
input [`PIXEL_WIDTH-1:0] ref_pel15_i ; // ref_pel15
output [1-1:0] satd_start_o ;
output [1-1:0] candi0_valid_o ; // candidate 0 row pixels valid
output [1-1:0] candi1_valid_o ; // candidate 1 row pixels valid
output [1-1:0] candi2_valid_o ; // candidate 2 row pixels valid
output [1-1:0] candi3_valid_o ; // candidate 3 row pixels valid
output [1-1:0] candi4_valid_o ; // candidate 4 row pixels valid
output [1-1:0] candi5_valid_o ; // candidate 5 row pixels valid
output [1-1:0] candi6_valid_o ; // candidate 6 row pixels valid
output [1-1:0] candi7_valid_o ; // candidate 7 row pixels valid
output [1-1:0] candi8_valid_o ; // candidate 8 row pixels valid
output [`PIXEL_WIDTH*8-1:0] candi0_pixles_o ; // candidate 0 row pixels
output [`PIXEL_WIDTH*8-1:0] candi1_pixles_o ; // candidate 1 row pixels
output [`PIXEL_WIDTH*8-1:0] candi2_pixles_o ; // candidate 2 row pixels
output [`PIXEL_WIDTH*8-1:0] candi3_pixles_o ; // candidate 3 row pixels
output [`PIXEL_WIDTH*8-1:0] candi4_pixles_o ; // candidate 4 row pixels
output [`PIXEL_WIDTH*8-1:0] candi5_pixles_o ; // candidate 5 row pixels
output [`PIXEL_WIDTH*8-1:0] candi6_pixles_o ; // candidate 6 row pixels
output [`PIXEL_WIDTH*8-1:0] candi7_pixles_o ; // candidate 7 row pixels
output [`PIXEL_WIDTH*8-1:0] candi8_pixles_o ; // candidate 8 row pixels
// ********************************************
//
// WIRE / REG DECLARATION
//
// ********************************************
reg [3: 0] cnt_ref; // ref pixel cnt
reg [3: 0] cnt_hor; // hor buff cnt, one cycle delay of cnt_ref
reg [3: 0] cnt_ver; // ver buff cnt, one cycle delay of cnt_ver
reg signed [`FMV_WIDTH-1: 0] mv_x_r0; // buffer0 to store mv information
reg signed [`FMV_WIDTH-1: 0] mv_y_r0;
reg [2-1 : 0] frac_x_r0;
reg [2-1 : 0] frac_y_r0;
reg [6-1: 0] blk_idx_r0;
reg half_ip_flag_r0;
reg signed [`FMV_WIDTH-1: 0] mv_x_r1; // buffer1 to store mv information
reg signed [`FMV_WIDTH-1: 0] mv_y_r1;
reg [2-1 : 0] frac_x_r1;
reg [2-1 : 0] frac_y_r1;
reg [6-1: 0] blk_idx_r1;
reg half_ip_flag_r1;
reg mv_in_flag; // ping-pong buffer
reg mv_out_flag;
reg hor_start;
reg horbuf_valid;
reg ver_start;
reg refpel_valid_d;
reg vhalf_pel_valid_d;
reg diagonal_pel_valid_d;
wire [1: 0] frac_x;
wire [1: 0] frac_y;
wire [1-1: 0] half_ip_flag;
wire [`FMV_WIDTH-1: 0] mv_x;
wire [`FMV_WIDTH-1: 0] mv_y;
wire [6-1: 0] blk_idx ; // index of the 8x8 block which is processed : pass to satd gen.
wire fracyEqualZero, fracxEqualZero;
wire [8*`PIXEL_WIDTH-1:0] h_00,h_01,h_02,h_10,h_11,h_12;
wire [8*`PIXEL_WIDTH-1:0] q_13,q_11,q_31,q_33,q_12,q_32,q_10,q_30;
wire [8*`PIXEL_WIDTH-1:0] q_21,q_23,q_01,q_03,q_22,q_20,q_02;
reg [1-1:0] candi0_valid ; // candidate 0 row pixels valid
reg [1-1:0] candi1_valid ; // candidate 1 row pixels valid
reg [1-1:0] candi2_valid ; // candidate 2 row pixels valid
reg [1-1:0] candi3_valid ; // candidate 3 row pixels valid
reg [1-1:0] candi4_valid ; // candidate 4 row pixels valid
reg [1-1:0] candi5_valid ; // candidate 5 row pixels valid
reg [1-1:0] candi6_valid ; // candidate 6 row pixels valid
reg [1-1:0] candi7_valid ; // candidate 7 row pixels valid
reg [1-1:0] candi8_valid ; // candidate 8 row pixels valid
reg [`PIXEL_WIDTH*8-1:0] candi0_pixles ; // candidate 0 row pixels
reg [`PIXEL_WIDTH*8-1:0] candi1_pixles ; // candidate 1 row pixels
reg [`PIXEL_WIDTH*8-1:0] candi2_pixles ; // candidate 2 row pixels
reg [`PIXEL_WIDTH*8-1:0] candi3_pixles ; // candidate 3 row pixels
reg [`PIXEL_WIDTH*8-1:0] candi4_pixles ; // candidate 4 row pixels
reg [`PIXEL_WIDTH*8-1:0] candi5_pixles ; // candidate 5 row pixels
reg [`PIXEL_WIDTH*8-1:0] candi6_pixles ; // candidate 6 row pixels
reg [`PIXEL_WIDTH*8-1:0] candi7_pixles ; // candidate 7 row pixels
reg [`PIXEL_WIDTH*8-1:0] candi8_pixles ; // candidate 8 row pixels
reg [`PIXEL_WIDTH*8-1:0] candi0_pixles_o ; // candidate 0 row pixels
reg [`PIXEL_WIDTH*8-1:0] candi1_pixles_o ; // candidate 1 row pixels
reg [`PIXEL_WIDTH*8-1:0] candi2_pixles_o ; // candidate 2 row pixels
reg [`PIXEL_WIDTH*8-1:0] candi3_pixles_o ; // candidate 3 row pixels
reg [`PIXEL_WIDTH*8-1:0] candi4_pixles_o ; // candidate 4 row pixels
reg [`PIXEL_WIDTH*8-1:0] candi5_pixles_o ; // candidate 5 row pixels
reg [`PIXEL_WIDTH*8-1:0] candi6_pixles_o ; // candidate 6 row pixels
reg [`PIXEL_WIDTH*8-1:0] candi7_pixles_o ; // candidate 7 row pixels
reg [`PIXEL_WIDTH*8-1:0] candi8_pixles_o ; // candidate 8 row pixels
reg [2*`PIXEL_WIDTH-1 :0] half_buf_0, q1_buf_0, q3_buf_0;
reg [2*`PIXEL_WIDTH-1 :0] half_buf_1, q1_buf_1, q3_buf_1;
reg [2*`PIXEL_WIDTH-1 :0] half_buf_2, q1_buf_2, q3_buf_2;
reg [2*`PIXEL_WIDTH-1 :0] half_buf_3, q1_buf_3, q3_buf_3;
reg [2*`PIXEL_WIDTH-1 :0] half_buf_4, q1_buf_4, q3_buf_4;
reg [2*`PIXEL_WIDTH-1 :0] half_buf_5, q1_buf_5, q3_buf_5;
reg [2*`PIXEL_WIDTH-1 :0] half_buf_6, q1_buf_6, q3_buf_6;
reg [2*`PIXEL_WIDTH-1 :0] half_buf_7, q1_buf_7, q3_buf_7;
reg [2*`PIXEL_WIDTH-1 :0] half_buf_8, q1_buf_8, q3_buf_8;
wire [2*`PIXEL_WIDTH-1 :0] half_buf0, q1_buf0, q3_buf0;
wire [2*`PIXEL_WIDTH-1 :0] half_buf1, q1_buf1, q3_buf1;
wire [2*`PIXEL_WIDTH-1 :0] half_buf2, q1_buf2, q3_buf2;
wire [2*`PIXEL_WIDTH-1 :0] half_buf3, q1_buf3, q3_buf3;
wire [2*`PIXEL_WIDTH-1 :0] half_buf4, q1_buf4, q3_buf4;
wire [2*`PIXEL_WIDTH-1 :0] half_buf5, q1_buf5, q3_buf5;
wire [2*`PIXEL_WIDTH-1 :0] half_buf6, q1_buf6, q3_buf6;
wire [2*`PIXEL_WIDTH-1 :0] half_buf7, q1_buf7, q3_buf7;
wire [2*`PIXEL_WIDTH-1 :0] half_buf8, q1_buf8, q3_buf8;
wire [1-1:0] vquarter_1_valid ; // vertical quarter 1 predicted pixels wire valid
wire [1-1:0] vquarter_3_valid ; // vertical quarter 3 predicted pixels wire valid
wire [1-1:0] vquarter_1_2_valid ; // vertical quarter 2 predicted pixels wire valid
wire [1-1:0] vquarter_3_2_valid ; // vertical quarter 2 predicted pixels wire valid
wire [1-1:0] vquarter_1_0_valid ; // vertical quarter 0 predicted pixels wire valid
wire [1-1:0] vquarter_3_0_valid ; // vertical quarter 0 predicted pixels wire valid
wire [1-1:0] vhalf_valid ; // vertical half predicted pixels wire valid
wire [1-1:0] vpel_valid ; // vertical ref predicted pixels wire valid
wire [1-1:0] vhalf_pel_valid ; //undefined note
wire [1-1:0] diagonal_pel_valid ; // diagonal predicted pixels output valid
wire [1-1:0] hhalf_pel_valid ; // diagonal predicted pixels output valid
wire [`PIXEL_WIDTH-1:0] d_pel0 ; // diagonal pixel 0
wire [`PIXEL_WIDTH-1:0] d_pel1 ; // diagonal pixel 1
wire [`PIXEL_WIDTH-1:0] d_pel2 ; // diagonal pixel 2
wire [`PIXEL_WIDTH-1:0] d_pel3 ; // diagonal pixel 3
wire [`PIXEL_WIDTH-1:0] d_pel4 ; // diagonal pixel 4
wire [`PIXEL_WIDTH-1:0] d_pel5 ; // diagonal pixel 5
wire [`PIXEL_WIDTH-1:0] d_pel6 ; // diagonal pixel 6
wire [`PIXEL_WIDTH-1:0] d_pel7 ; // diagonal pixel 7
wire [`PIXEL_WIDTH-1:0] d_pel8 ; // diagonal pixel 8
wire [`PIXEL_WIDTH-1:0] vhalf_pel0 ;
wire [`PIXEL_WIDTH-1:0] vhalf_pel1 ;
wire [`PIXEL_WIDTH-1:0] vhalf_pel2 ;
wire [`PIXEL_WIDTH-1:0] vhalf_pel3 ;
wire [`PIXEL_WIDTH-1:0] vhalf_pel4 ;
wire [`PIXEL_WIDTH-1:0] vhalf_pel5 ;
wire [`PIXEL_WIDTH-1:0] vhalf_pel6 ;
wire [`PIXEL_WIDTH-1:0] vhalf_pel7 ;
wire [`PIXEL_WIDTH-1:0] hhalf_pel0 ; // cliped half pixel 0
wire [`PIXEL_WIDTH-1:0] hhalf_pel1 ; // cliped half pixel 1
wire [`PIXEL_WIDTH-1:0] hhalf_pel2 ; // cliped half pixel 2
wire [`PIXEL_WIDTH-1:0] hhalf_pel3 ; // cliped half pixel 3
wire [`PIXEL_WIDTH-1:0] hhalf_pel4 ; // cliped half pixel 4
wire [`PIXEL_WIDTH-1:0] hhalf_pel5 ; // cliped half pixel 5
wire [`PIXEL_WIDTH-1:0] hhalf_pel6 ; // cliped half pixel 6
wire [`PIXEL_WIDTH-1:0] hhalf_pel7 ; // cliped half pixel 7
wire [`PIXEL_WIDTH-1:0] hhalf_pel8 ; // cliped half pixel 8
wire [`PIXEL_WIDTH-1:0] vquarter_1_1_pel0 ; // from q1 vertical quarter 1 pixel 0
wire [`PIXEL_WIDTH-1:0] vquarter_1_1_pel1 ; // from q1 vertical quarter 1 pixel 1
wire [`PIXEL_WIDTH-1:0] vquarter_1_1_pel2 ; // from q1 vertical quarter 1 pixel 2
wire [`PIXEL_WIDTH-1:0] vquarter_1_1_pel3 ; // from q1 vertical quarter 1 pixel 3
wire [`PIXEL_WIDTH-1:0] vquarter_1_1_pel4 ; // from q1 vertical quarter 1 pixel 4
wire [`PIXEL_WIDTH-1:0] vquarter_1_1_pel5 ; // from q1 vertical quarter 1 pixel 5
wire [`PIXEL_WIDTH-1:0] vquarter_1_1_pel6 ; // from q1 vertical quarter 1 pixel 6
wire [`PIXEL_WIDTH-1:0] vquarter_1_1_pel7 ; // from q1 vertical quarter 1 pixel 7
wire [`PIXEL_WIDTH-1:0] vquarter_1_3_pel0 ; // from q3 vertical quarter 1 pixel 0
wire [`PIXEL_WIDTH-1:0] vquarter_1_3_pel1 ; // from q3 vertical quarter 1 pixel 1
wire [`PIXEL_WIDTH-1:0] vquarter_1_3_pel2 ; // from q3 vertical quarter 1 pixel 2
wire [`PIXEL_WIDTH-1:0] vquarter_1_3_pel3 ; // from q3 vertical quarter 1 pixel 3
wire [`PIXEL_WIDTH-1:0] vquarter_1_3_pel4 ; // from q3 vertical quarter 1 pixel 4
wire [`PIXEL_WIDTH-1:0] vquarter_1_3_pel5 ; // from q3 vertical quarter 1 pixel 5
wire [`PIXEL_WIDTH-1:0] vquarter_1_3_pel6 ; // from q3 vertical quarter 1 pixel 6
wire [`PIXEL_WIDTH-1:0] vquarter_1_3_pel7 ; // from q3 vertical quarter 1 pixel 7
wire [`PIXEL_WIDTH-1:0] vquarter_1_2_pel0 ; // from half vertical quarter 1 pixel 0
wire [`PIXEL_WIDTH-1:0] vquarter_1_2_pel1 ; // from half vertical quarter 1 pixel 1
wire [`PIXEL_WIDTH-1:0] vquarter_1_2_pel2 ; // from half vertical quarter 1 pixel 2
wire [`PIXEL_WIDTH-1:0] vquarter_1_2_pel3 ; // from half vertical quarter 1 pixel 3
wire [`PIXEL_WIDTH-1:0] vquarter_1_2_pel4 ; // from half vertical quarter 1 pixel 4
wire [`PIXEL_WIDTH-1:0] vquarter_1_2_pel5 ; // from half vertical quarter 1 pixel 5
wire [`PIXEL_WIDTH-1:0] vquarter_1_2_pel6 ; // from half vertical quarter 1 pixel 6
wire [`PIXEL_WIDTH-1:0] vquarter_1_2_pel7 ; // from half vertical quarter 1 pixel 7
wire [`PIXEL_WIDTH-1:0] vquarter_1_0_pel0 ; // from ref vertical quarter 1 pixel 0
wire [`PIXEL_WIDTH-1:0] vquarter_1_0_pel1 ; // from ref vertical quarter 1 pixel 1
wire [`PIXEL_WIDTH-1:0] vquarter_1_0_pel2 ; // from ref vertical quarter 1 pixel 2
wire [`PIXEL_WIDTH-1:0] vquarter_1_0_pel3 ; // from ref vertical quarter 1 pixel 3
wire [`PIXEL_WIDTH-1:0] vquarter_1_0_pel4 ; // from ref vertical quarter 1 pixel 4
wire [`PIXEL_WIDTH-1:0] vquarter_1_0_pel5 ; // from ref vertical quarter 1 pixel 5
wire [`PIXEL_WIDTH-1:0] vquarter_1_0_pel6 ; // from ref vertical quarter 1 pixel 6
wire [`PIXEL_WIDTH-1:0] vquarter_1_0_pel7 ; // from ref vertical quarter 1 pixel 7
wire [`PIXEL_WIDTH-1:0] vquarter_3_1_pel0 ; // from q1 vertical quarter 3 pixel 0
wire [`PIXEL_WIDTH-1:0] vquarter_3_1_pel1 ; // from q1 vertical quarter 3 pixel 1
wire [`PIXEL_WIDTH-1:0] vquarter_3_1_pel2 ; // from q1 vertical quarter 3 pixel 2
wire [`PIXEL_WIDTH-1:0] vquarter_3_1_pel3 ; // from q1 vertical quarter 3 pixel 3
wire [`PIXEL_WIDTH-1:0] vquarter_3_1_pel4 ; // from q1 vertical quarter 3 pixel 4
wire [`PIXEL_WIDTH-1:0] vquarter_3_1_pel5 ; // from q1 vertical quarter 3 pixel 5
wire [`PIXEL_WIDTH-1:0] vquarter_3_1_pel6 ; // from q1 vertical quarter 3 pixel 6
wire [`PIXEL_WIDTH-1:0] vquarter_3_1_pel7 ; // from q1 vertical quarter 3 pixel 7
wire [`PIXEL_WIDTH-1:0] vquarter_3_3_pel0 ; // from q3 vertical quarter 3 pixel 0
wire [`PIXEL_WIDTH-1:0] vquarter_3_3_pel1 ; // from q3 vertical quarter 3 pixel 1
wire [`PIXEL_WIDTH-1:0] vquarter_3_3_pel2 ; // from q3 vertical quarter 3 pixel 2
wire [`PIXEL_WIDTH-1:0] vquarter_3_3_pel3 ; // from q3 vertical quarter 3 pixel 3
wire [`PIXEL_WIDTH-1:0] vquarter_3_3_pel4 ; // from q3 vertical quarter 3 pixel 4
wire [`PIXEL_WIDTH-1:0] vquarter_3_3_pel5 ; // from q3 vertical quarter 3 pixel 5
wire [`PIXEL_WIDTH-1:0] vquarter_3_3_pel6 ; // from q3 vertical quarter 3 pixel 6
wire [`PIXEL_WIDTH-1:0] vquarter_3_3_pel7 ; // from q3 vertical quarter 3 pixel 7
wire [`PIXEL_WIDTH-1:0] vquarter_3_0_pel0 ; // from ref vertical quarter 3 pixel 0
wire [`PIXEL_WIDTH-1:0] vquarter_3_0_pel1 ; // from ref vertical quarter 3 pixel 1
wire [`PIXEL_WIDTH-1:0] vquarter_3_0_pel2 ; // from ref vertical quarter 3 pixel 2
wire [`PIXEL_WIDTH-1:0] vquarter_3_0_pel3 ; // from ref vertical quarter 3 pixel 3
wire [`PIXEL_WIDTH-1:0] vquarter_3_0_pel4 ; // from ref vertical quarter 3 pixel 4
wire [`PIXEL_WIDTH-1:0] vquarter_3_0_pel5 ; // from ref vertical quarter 3 pixel 5
wire [`PIXEL_WIDTH-1:0] vquarter_3_0_pel6 ; // from ref vertical quarter 3 pixel 6
wire [`PIXEL_WIDTH-1:0] vquarter_3_0_pel7 ; // from ref vertical quarter 3 pixel 7
wire [`PIXEL_WIDTH-1:0] vquarter_3_2_pel0 ; // from half vertical quarter 3 pixel 0
wire [`PIXEL_WIDTH-1:0] vquarter_3_2_pel1 ; // from half vertical quarter 3 pixel 1
wire [`PIXEL_WIDTH-1:0] vquarter_3_2_pel2 ; // from half vertical quarter 3 pixel 2
wire [`PIXEL_WIDTH-1:0] vquarter_3_2_pel3 ; // from half vertical quarter 3 pixel 3
wire [`PIXEL_WIDTH-1:0] vquarter_3_2_pel4 ; // from half vertical quarter 3 pixel 4
wire [`PIXEL_WIDTH-1:0] vquarter_3_2_pel5 ; // from half vertical quarter 3 pixel 5
wire [`PIXEL_WIDTH-1:0] vquarter_3_2_pel6 ; // from half vertical quarter 3 pixel 6
wire [`PIXEL_WIDTH-1:0] vquarter_3_2_pel7 ; // from half vertical quarter 3 pixel 7
wire [`PIXEL_WIDTH-1:0] vhalf_2_1_pel0 ;
wire [`PIXEL_WIDTH-1:0] vhalf_2_1_pel1 ;
wire [`PIXEL_WIDTH-1:0] vhalf_2_1_pel2 ;
wire [`PIXEL_WIDTH-1:0] vhalf_2_1_pel3 ;
wire [`PIXEL_WIDTH-1:0] vhalf_2_1_pel4 ;
wire [`PIXEL_WIDTH-1:0] vhalf_2_1_pel5 ;
wire [`PIXEL_WIDTH-1:0] vhalf_2_1_pel6 ;
wire [`PIXEL_WIDTH-1:0] vhalf_2_1_pel7 ;
wire [`PIXEL_WIDTH-1:0] vhalf_2_3_pel0 ;
wire [`PIXEL_WIDTH-1:0] vhalf_2_3_pel1 ;
wire [`PIXEL_WIDTH-1:0] vhalf_2_3_pel2 ;
wire [`PIXEL_WIDTH-1:0] vhalf_2_3_pel3 ;
wire [`PIXEL_WIDTH-1:0] vhalf_2_3_pel4 ;
wire [`PIXEL_WIDTH-1:0] vhalf_2_3_pel5 ;
wire [`PIXEL_WIDTH-1:0] vhalf_2_3_pel6 ;
wire [`PIXEL_WIDTH-1:0] vhalf_2_3_pel7 ;
wire [`PIXEL_WIDTH-1:0] vpel_0_1_pel0 ;
wire [`PIXEL_WIDTH-1:0] vpel_0_1_pel1 ;
wire [`PIXEL_WIDTH-1:0] vpel_0_1_pel2 ;
wire [`PIXEL_WIDTH-1:0] vpel_0_1_pel3 ;
wire [`PIXEL_WIDTH-1:0] vpel_0_1_pel4 ;
wire [`PIXEL_WIDTH-1:0] vpel_0_1_pel5 ;
wire [`PIXEL_WIDTH-1:0] vpel_0_1_pel6 ;
wire [`PIXEL_WIDTH-1:0] vpel_0_1_pel7 ;
wire [`PIXEL_WIDTH-1:0] vpel_0_3_pel0 ;
wire [`PIXEL_WIDTH-1:0] vpel_0_3_pel1 ;
wire [`PIXEL_WIDTH-1:0] vpel_0_3_pel2 ;
wire [`PIXEL_WIDTH-1:0] vpel_0_3_pel3 ;
wire [`PIXEL_WIDTH-1:0] vpel_0_3_pel4 ;
wire [`PIXEL_WIDTH-1:0] vpel_0_3_pel5 ;
wire [`PIXEL_WIDTH-1:0] vpel_0_3_pel6 ;
wire [`PIXEL_WIDTH-1:0] vpel_0_3_pel7 ;
//valid signals
wire cnthorLargerThan3;
wire cnthorLargerThan4;
wire cntrefLargerThan7;
wire cntrefLargerThan8;
wire cnthorLargerThan7;
wire cnthorLargerThan8;
wire cntverLargerThan7;
wire cntverLargerThan8;
// ********************************************
//
// Sequential Logic
//
// ********************************************
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
mv_x_r0 <= 'd0;
mv_x_r1 <= 'd0;
mv_y_r0 <= 'd0;
mv_y_r1 <= 'd0;
frac_x_r0 <= 'd0;
frac_x_r1 <= 'd0;
frac_y_r0 <= 'd0;
frac_y_r1 <= 'd0;
half_ip_flag_r0 <= 1'b0;
half_ip_flag_r1 <= 1'b0;
blk_idx_r0 <= 'd0;
blk_idx_r1 <= 'd0;
mv_in_flag <= 1'b0;
end
else if (blk_start_i) begin
mv_in_flag <= ~mv_in_flag;
if (~mv_in_flag) begin
mv_x_r0 <= mv_x_i;
mv_y_r0 <= mv_y_i;
frac_x_r0 <= frac_x_i;
frac_y_r0 <= frac_y_i;
blk_idx_r0 <= blk_idx_i;
half_ip_flag_r0 <= half_ip_flag_i;
end
else begin
mv_x_r1 <= mv_x_i;
mv_y_r1 <= mv_y_i;
frac_x_r1 <= frac_x_i;
frac_y_r1 <= frac_y_i;
blk_idx_r1 <= blk_idx_i;
half_ip_flag_r1 <= half_ip_flag_i;
end
end
end
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
mv_out_flag <= 'd0;
end
else if (end_ip_o) begin
mv_out_flag <= ~mv_out_flag;
end
end
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
cnt_ref <= 'd0;
end
else if (blk_start_i || cnt_ref == 'd15) begin
cnt_ref <= 'd0;
end
else if (refpel_valid_i) begin
cnt_ref <= cnt_ref + 'd1;
end
end
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
cnt_hor <= 'd0;
end
else if (hor_start || cnt_hor == 'd15) begin
cnt_hor <= 'd0;
end
else if (horbuf_valid) begin
cnt_hor <= cnt_hor + 'd1;
end
end
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
cnt_ver <= 'd0;
end
else if (ver_start) begin
cnt_ver <= 'd0;
end
else begin
cnt_ver <= cnt_hor;
end
end
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
hor_start <= 'd0;
horbuf_valid <= 'd0;
ver_start <= 'd0;
end
else begin
hor_start <= blk_start_i;
horbuf_valid <= refpel_valid_i;
ver_start <= hor_start;
end
end
always @ (posedge clk or negedge rstn) begin
if(~rstn) begin
refpel_valid_d <= 'd0;
vhalf_pel_valid_d <= 'd0;
diagonal_pel_valid_d <= 'd0;
end
else begin
refpel_valid_d <= refpel_valid_i;
vhalf_pel_valid_d <= vhalf_pel_valid;
diagonal_pel_valid_d <= diagonal_pel_valid;
end
end
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
half_buf_0 <= 'd0; q1_buf_0 <= 'd0; q3_buf_0 <= 'd0;
half_buf_1 <= 'd0; q1_buf_1 <= 'd0; q3_buf_1 <= 'd0;
half_buf_2 <= 'd0; q1_buf_2 <= 'd0; q3_buf_2 <= 'd0;
half_buf_3 <= 'd0; q1_buf_3 <= 'd0; q3_buf_3 <= 'd0;
half_buf_4 <= 'd0; q1_buf_4 <= 'd0; q3_buf_4 <= 'd0;
half_buf_5 <= 'd0; q1_buf_5 <= 'd0; q3_buf_5 <= 'd0;
half_buf_6 <= 'd0; q1_buf_6 <= 'd0; q3_buf_6 <= 'd0;
half_buf_7 <= 'd0; q1_buf_7 <= 'd0; q3_buf_7 <= 'd0;
half_buf_8 <= 'd0; q1_buf_8 <= 'd0; q3_buf_8 <= 'd0;
end
else begin
half_buf_0 <= half_buf0;
q1_buf_0 <= q1_buf0;
q3_buf_0 <= q3_buf0;
half_buf_1 <= half_buf1;
q1_buf_1 <= q1_buf1;
q3_buf_1 <= q3_buf1;
half_buf_2 <= half_buf2;
q1_buf_2 <= q1_buf2;
q3_buf_2 <= q3_buf2;
half_buf_3 <= half_buf3;
q1_buf_3 <= q1_buf3;
q3_buf_3 <= q3_buf3;
half_buf_4 <= half_buf4;
q1_buf_4 <= q1_buf4;
q3_buf_4 <= q3_buf4;
half_buf_5 <= half_buf5;
q1_buf_5 <= q1_buf5;
q3_buf_5 <= q3_buf5;
half_buf_6 <= half_buf6;
q1_buf_6 <= q1_buf6;
q3_buf_6 <= q3_buf6;
half_buf_7 <= half_buf7;
q1_buf_7 <= q1_buf7;
q3_buf_7 <= q3_buf7;
half_buf_8 <= half_buf8;
q1_buf_8 <= q1_buf8;
q3_buf_8 <= q3_buf8;
end
end
// ********************************************
//
// Sub Module
//
// ********************************************
fme_interpolator_8pel horizontal_interpolator(
.ref_pel0_i (ref_pel0_i ) ,
.ref_pel1_i (ref_pel1_i ) ,
.ref_pel2_i (ref_pel2_i ) ,
.ref_pel3_i (ref_pel3_i ) ,
.ref_pel4_i (ref_pel4_i ) ,
.ref_pel5_i (ref_pel5_i ) ,
.ref_pel6_i (ref_pel6_i ) ,
.ref_pel7_i (ref_pel7_i ) ,
.ref_pel8_i (ref_pel8_i ) ,
.ref_pel9_i (ref_pel9_i ) ,
.ref_pel10_i (ref_pel10_i) ,
.ref_pel11_i (ref_pel11_i) ,
.ref_pel12_i (ref_pel12_i) ,
.ref_pel13_i (ref_pel13_i) ,
.ref_pel14_i (ref_pel14_i) ,
.ref_pel15_i (ref_pel15_i) ,
.hhalf_pel0_o (hhalf_pel0),
.hhalf_pel1_o (hhalf_pel1),
.hhalf_pel2_o (hhalf_pel2),
.hhalf_pel3_o (hhalf_pel3),
.hhalf_pel4_o (hhalf_pel4),
.hhalf_pel5_o (hhalf_pel5),
.hhalf_pel6_o (hhalf_pel6),
.hhalf_pel7_o (hhalf_pel7),
.hhalf_pel8_o (hhalf_pel8),
.half_buf_0 (half_buf0 ) ,
.q1_buf_0 (q1_buf0 ) ,
.q3_buf_0 (q3_buf0 ) ,
.half_buf_1 (half_buf1 ) ,
.q1_buf_1 (q1_buf1 ) ,
.q3_buf_1 (q3_buf1 ) ,
.half_buf_2 (half_buf2 ) ,
.q1_buf_2 (q1_buf2 ) ,
.q3_buf_2 (q3_buf2 ) ,
.half_buf_3 (half_buf3 ) ,
.q1_buf_3 (q1_buf3 ) ,
.q3_buf_3 (q3_buf3 ) ,
.half_buf_4 (half_buf4 ) ,
.q1_buf_4 (q1_buf4 ) ,
.q3_buf_4 (q3_buf4 ) ,
.half_buf_5 (half_buf5 ) ,
.q1_buf_5 (q1_buf5 ) ,
.q3_buf_5 (q3_buf5 ) ,
.half_buf_6 (half_buf6 ) ,
.q1_buf_6 (q1_buf6 ) ,
.q3_buf_6 (q3_buf6 ) ,
.half_buf_7 (half_buf7 ) ,
.q1_buf_7 (q1_buf7 ) ,
.q3_buf_7 (q3_buf7 ) ,
.half_buf_8 (half_buf8 ) ,
.q1_buf_8 (q1_buf8 ) ,
.q3_buf_8 (q3_buf8 )
);
fme_ip_half_ver half_vertical_interpolator(
.clk (clk ),
.rstn (rstn ),
.blk_start_i (blk_start_i ),
.refpel_valid_i (refpel_valid_i ),
.ref_pel0_i (ref_pel4_i ),
.ref_pel1_i (ref_pel5_i ),
.ref_pel2_i (ref_pel6_i ),
.ref_pel3_i (ref_pel7_i ),
.ref_pel4_i (ref_pel8_i ),
.ref_pel5_i (ref_pel9_i ),
.ref_pel6_i (ref_pel10_i ),
.ref_pel7_i (ref_pel11_i ),
.vhalf_pel0_o (vhalf_pel0 ),
.vhalf_pel1_o (vhalf_pel1 ),
.vhalf_pel2_o (vhalf_pel2 ),
.vhalf_pel3_o (vhalf_pel3 ),
.vhalf_pel4_o (vhalf_pel4 ),
.vhalf_pel5_o (vhalf_pel5 ),
.vhalf_pel6_o (vhalf_pel6 ),
.vhalf_pel7_o (vhalf_pel7 ),
.hor_start_i (hor_start ),
.horbuf_valid_i (horbuf_valid ),
.h_buf0_i (half_buf_0 ),
.h_buf1_i (half_buf_1 ),
.h_buf2_i (half_buf_2 ),
.h_buf3_i (half_buf_3 ),
.h_buf4_i (half_buf_4 ),
.h_buf5_i (half_buf_5 ),
.h_buf6_i (half_buf_6 ),
.h_buf7_i (half_buf_7 ),
.h_buf8_i (half_buf_8 ),
.d_pel0_o (d_pel0 ),
.d_pel1_o (d_pel1 ),
.d_pel2_o (d_pel2 ),
.d_pel3_o (d_pel3 ),
.d_pel4_o (d_pel4 ),
.d_pel5_o (d_pel5 ),
.d_pel6_o (d_pel6 ),
.d_pel7_o (d_pel7 ),
.d_pel8_o (d_pel8 )
);
fme_ip_quarter_ver quarter_verical_interpolator (
.clk (clk ),
.rstn (rstn ),
.blk_start_i (blk_start_i ),
.refpel_valid_i (refpel_valid_i ),
.hor_start_i (hor_start ),
.horbuf_valid_i (horbuf_valid ),
.frac_x_i (frac_x ),
.frac_y_i (frac_y ),
.q1_buf0_i ((frac_x == 2'b01 || frac_x == 2'b00) ? q1_buf_1 : q1_buf_0 ), // q1_buf_1
.q1_buf1_i ((frac_x == 2'b01 || frac_x == 2'b00) ? q1_buf_2 : q1_buf_1 ), // q1_buf_2
.q1_buf2_i ((frac_x == 2'b01 || frac_x == 2'b00) ? q1_buf_3 : q1_buf_2 ), // q1_buf_3
.q1_buf3_i ((frac_x == 2'b01 || frac_x == 2'b00) ? q1_buf_4 : q1_buf_3 ), // q1_buf_4
.q1_buf4_i ((frac_x == 2'b01 || frac_x == 2'b00) ? q1_buf_5 : q1_buf_4 ), // q1_buf_5
.q1_buf5_i ((frac_x == 2'b01 || frac_x == 2'b00) ? q1_buf_6 : q1_buf_5 ), // q1_buf_6
.q1_buf6_i ((frac_x == 2'b01 || frac_x == 2'b00) ? q1_buf_7 : q1_buf_6 ), // q1_buf_7
.q1_buf7_i ((frac_x == 2'b01 || frac_x == 2'b00) ? q1_buf_8 : q1_buf_7 ), // q1_buf_8
.q3_buf0_i ((frac_x == 2'b01 ) ? q3_buf_1 : q3_buf_0), // q3_buf_1
.q3_buf1_i ((frac_x == 2'b01 ) ? q3_buf_2 : q3_buf_1), // q3_buf_2
.q3_buf2_i ((frac_x == 2'b01 ) ? q3_buf_3 : q3_buf_2), // q3_buf_3
.q3_buf3_i ((frac_x == 2'b01 ) ? q3_buf_4 : q3_buf_3), // q3_buf_4
.q3_buf4_i ((frac_x == 2'b01 ) ? q3_buf_5 : q3_buf_4), // q3_buf_5
.q3_buf5_i ((frac_x == 2'b01 ) ? q3_buf_6 : q3_buf_5), // q3_buf_6
.q3_buf6_i ((frac_x == 2'b01 ) ? q3_buf_7 : q3_buf_6), // q3_buf_7
.q3_buf7_i ((frac_x == 2'b01 ) ? q3_buf_8 : q3_buf_7), // q3_buf_8
.h_buf0_i ((frac_x == 2'b01 /*|| frac_x == 2'b00*/) ? half_buf_1 : half_buf_0), // half_buf_1
.h_buf1_i ((frac_x == 2'b01 /*|| frac_x == 2'b00*/) ? half_buf_2 : half_buf_1), // half_buf_2
.h_buf2_i ((frac_x == 2'b01 /*|| frac_x == 2'b00*/) ? half_buf_3 : half_buf_2), // half_buf_3
.h_buf3_i ((frac_x == 2'b01 /*|| frac_x == 2'b00*/) ? half_buf_4 : half_buf_3), // half_buf_4
.h_buf4_i ((frac_x == 2'b01 /*|| frac_x == 2'b00*/) ? half_buf_5 : half_buf_4), // half_buf_5
.h_buf5_i ((frac_x == 2'b01 /*|| frac_x == 2'b00*/) ? half_buf_6 : half_buf_5), // half_buf_6
.h_buf6_i ((frac_x == 2'b01 /*|| frac_x == 2'b00*/) ? half_buf_7 : half_buf_6), // half_buf_7
.h_buf7_i ((frac_x == 2'b01 /*|| frac_x == 2'b00*/) ? half_buf_8 : half_buf_7), // half_buf_8
.ref_pel0_i (ref_pel4_i ),
.ref_pel1_i (ref_pel5_i ),
.ref_pel2_i (ref_pel6_i ),
.ref_pel3_i (ref_pel7_i ),
.ref_pel4_i (ref_pel8_i ),
.ref_pel5_i (ref_pel9_i ),
.ref_pel6_i (ref_pel10_i ),
.ref_pel7_i (ref_pel11_i ),
//.vquarter_1_valid_o (vquarter_1_valid ), //1,1 | 3,1
//.vquarter_3_valid_o (vquarter_3_valid ), //1,3 | 3,3
//.vquarter_2_valid_o (vquarter_2_valid ), //1,2 | 3,2
//.vquarter_0_valid_o (vquarter_0_valid ), //1,0 | 3,0
//.vhalf_valid_o (vhalf_valid ), //2,1 | 2,3
//.vpel_valid_o (vpel_valid ), //0,1 | 0,3
.vquarter_1_1_pel0_o (vquarter_1_1_pel0 ),
.vquarter_1_1_pel1_o (vquarter_1_1_pel1 ),
.vquarter_1_1_pel2_o (vquarter_1_1_pel2 ),
.vquarter_1_1_pel3_o (vquarter_1_1_pel3 ),
.vquarter_1_1_pel4_o (vquarter_1_1_pel4 ),
.vquarter_1_1_pel5_o (vquarter_1_1_pel5 ),
.vquarter_1_1_pel6_o (vquarter_1_1_pel6 ),
.vquarter_1_1_pel7_o (vquarter_1_1_pel7 ),
.vquarter_1_3_pel0_o (vquarter_1_3_pel0 ),
.vquarter_1_3_pel1_o (vquarter_1_3_pel1 ),
.vquarter_1_3_pel2_o (vquarter_1_3_pel2 ),
.vquarter_1_3_pel3_o (vquarter_1_3_pel3 ),
.vquarter_1_3_pel4_o (vquarter_1_3_pel4 ),
.vquarter_1_3_pel5_o (vquarter_1_3_pel5 ),
.vquarter_1_3_pel6_o (vquarter_1_3_pel6 ),
.vquarter_1_3_pel7_o (vquarter_1_3_pel7 ),
.vquarter_1_2_pel0_o (vquarter_1_2_pel0 ),
.vquarter_1_2_pel1_o (vquarter_1_2_pel1 ),
.vquarter_1_2_pel2_o (vquarter_1_2_pel2 ),
.vquarter_1_2_pel3_o (vquarter_1_2_pel3 ),
.vquarter_1_2_pel4_o (vquarter_1_2_pel4 ),
.vquarter_1_2_pel5_o (vquarter_1_2_pel5 ),
.vquarter_1_2_pel6_o (vquarter_1_2_pel6 ),
.vquarter_1_2_pel7_o (vquarter_1_2_pel7 ),
.vquarter_1_0_pel0_o (vquarter_1_0_pel0 ),
.vquarter_1_0_pel1_o (vquarter_1_0_pel1 ),
.vquarter_1_0_pel2_o (vquarter_1_0_pel2 ),
.vquarter_1_0_pel3_o (vquarter_1_0_pel3 ),
.vquarter_1_0_pel4_o (vquarter_1_0_pel4 ),
.vquarter_1_0_pel5_o (vquarter_1_0_pel5 ),
.vquarter_1_0_pel6_o (vquarter_1_0_pel6 ),
.vquarter_1_0_pel7_o (vquarter_1_0_pel7 ),
.vquarter_3_1_pel0_o (vquarter_3_1_pel0 ),
.vquarter_3_1_pel1_o (vquarter_3_1_pel1 ),
.vquarter_3_1_pel2_o (vquarter_3_1_pel2 ),
.vquarter_3_1_pel3_o (vquarter_3_1_pel3 ),
.vquarter_3_1_pel4_o (vquarter_3_1_pel4 ),
.vquarter_3_1_pel5_o (vquarter_3_1_pel5 ),
.vquarter_3_1_pel6_o (vquarter_3_1_pel6 ),
.vquarter_3_1_pel7_o (vquarter_3_1_pel7 ),
.vquarter_3_3_pel0_o (vquarter_3_3_pel0 ),
.vquarter_3_3_pel1_o (vquarter_3_3_pel1 ),
.vquarter_3_3_pel2_o (vquarter_3_3_pel2 ),
.vquarter_3_3_pel3_o (vquarter_3_3_pel3 ),
.vquarter_3_3_pel4_o (vquarter_3_3_pel4 ),
.vquarter_3_3_pel5_o (vquarter_3_3_pel5 ),
.vquarter_3_3_pel6_o (vquarter_3_3_pel6 ),
.vquarter_3_3_pel7_o (vquarter_3_3_pel7 ),
.vquarter_3_2_pel0_o (vquarter_3_2_pel0 ),
.vquarter_3_2_pel1_o (vquarter_3_2_pel1 ),
.vquarter_3_2_pel2_o (vquarter_3_2_pel2 ),
.vquarter_3_2_pel3_o (vquarter_3_2_pel3 ),
.vquarter_3_2_pel4_o (vquarter_3_2_pel4 ),
.vquarter_3_2_pel5_o (vquarter_3_2_pel5 ),
.vquarter_3_2_pel6_o (vquarter_3_2_pel6 ),
.vquarter_3_2_pel7_o (vquarter_3_2_pel7 ),
.vquarter_3_0_pel0_o (vquarter_3_0_pel0 ),
.vquarter_3_0_pel1_o (vquarter_3_0_pel1 ),
.vquarter_3_0_pel2_o (vquarter_3_0_pel2 ),
.vquarter_3_0_pel3_o (vquarter_3_0_pel3 ),
.vquarter_3_0_pel4_o (vquarter_3_0_pel4 ),
.vquarter_3_0_pel5_o (vquarter_3_0_pel5 ),
.vquarter_3_0_pel6_o (vquarter_3_0_pel6 ),
.vquarter_3_0_pel7_o (vquarter_3_0_pel7 ),
.vpel_0_1_pel0_o (vpel_0_1_pel0 ),
.vpel_0_1_pel1_o (vpel_0_1_pel1 ),
.vpel_0_1_pel2_o (vpel_0_1_pel2 ),
.vpel_0_1_pel3_o (vpel_0_1_pel3 ),
.vpel_0_1_pel4_o (vpel_0_1_pel4 ),
.vpel_0_1_pel5_o (vpel_0_1_pel5 ),
.vpel_0_1_pel6_o (vpel_0_1_pel6 ),
.vpel_0_1_pel7_o (vpel_0_1_pel7 ),
.vpel_0_3_pel0_o (vpel_0_3_pel0 ),
.vpel_0_3_pel1_o (vpel_0_3_pel1 ),
.vpel_0_3_pel2_o (vpel_0_3_pel2 ),
.vpel_0_3_pel3_o (vpel_0_3_pel3 ),
.vpel_0_3_pel4_o (vpel_0_3_pel4 ),
.vpel_0_3_pel5_o (vpel_0_3_pel5 ),
.vpel_0_3_pel6_o (vpel_0_3_pel6 ),
.vpel_0_3_pel7_o (vpel_0_3_pel7 ),
.vhalf_2_1_pel0_o (vhalf_2_1_pel0 ),
.vhalf_2_1_pel1_o (vhalf_2_1_pel1 ),
.vhalf_2_1_pel2_o (vhalf_2_1_pel2 ),
.vhalf_2_1_pel3_o (vhalf_2_1_pel3 ),
.vhalf_2_1_pel4_o (vhalf_2_1_pel4 ),
.vhalf_2_1_pel5_o (vhalf_2_1_pel5 ),
.vhalf_2_1_pel6_o (vhalf_2_1_pel6 ),
.vhalf_2_1_pel7_o (vhalf_2_1_pel7 ),
.vhalf_2_3_pel0_o (vhalf_2_3_pel0 ),
.vhalf_2_3_pel1_o (vhalf_2_3_pel1 ),
.vhalf_2_3_pel2_o (vhalf_2_3_pel2 ),
.vhalf_2_3_pel3_o (vhalf_2_3_pel3 ),
.vhalf_2_3_pel4_o (vhalf_2_3_pel4 ),
.vhalf_2_3_pel5_o (vhalf_2_3_pel5 ),
.vhalf_2_3_pel6_o (vhalf_2_3_pel6 ),
.vhalf_2_3_pel7_o (vhalf_2_3_pel7 )
);
// ********************************************
//
// Combinational Logic
//
// ********************************************
// output signals
assign satd_start_o = (cnt_ref == 'd2);
//assign ip_ready_o = (cnt_ref >= 'd4 || cnt_hor == 'hf); // use it as cur lcu read enable signal
assign ip_ready_o = (cnt_ref == 'd4 || cnt_ref == 'd3); // use it as cur lcu read enable signal
assign end_ip_o = (cnt_ver == 'd15);
assign mv_x_o = (mv_out_flag) ? mv_x_r1: mv_x_r0;
assign mv_y_o = (mv_out_flag) ? mv_y_r1: mv_y_r0;
assign frac_x = (mv_out_flag) ? frac_x_r1: frac_x_r0;
assign frac_y = (mv_out_flag) ? frac_y_r1: frac_y_r0;
assign blk_idx_o = (mv_in_flag) ? blk_idx_r0: blk_idx_r1;
assign blk_idx = (mv_out_flag) ? blk_idx_r1: blk_idx_r0;
assign half_ip_flag = (mv_out_flag) ? half_ip_flag_r1 : half_ip_flag_r0;
assign half_ip_flag_o = half_ip_flag;
assign mc_end_ip_o = (&blk_idx) & end_ip_o;
//valid signal
//
assign diagonal_pel_valid = (cnt_hor[3]);
assign vhalf_pel_valid = (cnt_ref[3]);
assign hhalf_pel_valid = (cnt_hor >=4 && cnt_hor <12);
assign cnthorLargerThan3 = (cnt_hor >='d4 && cnt_hor <='d11);
assign cnthorLargerThan4 = (cnt_hor > 'd4 && cnt_hor <='d12);
assign cntrefLargerThan7 = (cnt_ref >='d7 && cnt_ref <='d14);
assign cntrefLargerThan8 = (cnt_ref [3]);
assign cnthorLargerThan7 = (cnt_hor >='d7 && cnt_hor <='d14);
assign cnthorLargerThan8 = (cnt_hor [3]);
assign cntverLargerThan7 = (cnt_ver >='d7 && cnt_ver <='d14);
assign cntverLargerThan8 = (cnt_ver [3]);
assign vquarter_1_valid = (frac_y == 2'b00 || frac_y == 2'b01) ? (cntverLargerThan8) : (cntverLargerThan7);
assign vquarter_3_valid = ( frac_y == 2'b01) ? (cntverLargerThan8) : (cntverLargerThan7);
assign vquarter_1_2_valid = (frac_y == 2'b00 || frac_y == 2'b01) ? (cntverLargerThan8) : (cntverLargerThan7);
assign vquarter_3_2_valid = ( frac_y == 2'b01) ? (cntverLargerThan8) : (cntverLargerThan7);
assign vquarter_1_0_valid = (frac_y == 2'b00 || frac_y == 2'b01) ? (cnthorLargerThan8) : (cnthorLargerThan7);
assign vquarter_3_0_valid = ( frac_y == 2'b01) ? (cnthorLargerThan8) : (cnthorLargerThan7);
assign vhalf_valid = ( frac_y == 2'b01) ? (cntverLargerThan8) : (cntverLargerThan7);
assign vpel_valid = (frac_y == 2'b00 || frac_y == 2'b01) ? (cnthorLargerThan4) : (cnthorLargerThan3);
// candidate selection
// combine pixel to one row
//
assign h_00 = {d_pel0, d_pel1, d_pel2, d_pel3, d_pel4, d_pel5, d_pel6, d_pel7};
assign h_01 = {vhalf_pel0, vhalf_pel1, vhalf_pel2, vhalf_pel3, vhalf_pel4, vhalf_pel5, vhalf_pel6, vhalf_pel7};
assign h_02 = {d_pel1, d_pel2, d_pel3, d_pel4, d_pel5, d_pel6, d_pel7, d_pel8};
assign h_10 = {hhalf_pel0, hhalf_pel1, hhalf_pel2, hhalf_pel3, hhalf_pel4, hhalf_pel5, hhalf_pel6, hhalf_pel7};
assign h_11 = {ref_pel4_i, ref_pel5_i, ref_pel6_i, ref_pel7_i, ref_pel8_i, ref_pel9_i, ref_pel10_i, ref_pel11_i};
assign h_12 = {hhalf_pel1, hhalf_pel2, hhalf_pel3, hhalf_pel4, hhalf_pel5, hhalf_pel6, hhalf_pel7, hhalf_pel8};
assign q_13 = {vquarter_1_3_pel0,vquarter_1_3_pel1,vquarter_1_3_pel2,vquarter_1_3_pel3,vquarter_1_3_pel4,vquarter_1_3_pel5,vquarter_1_3_pel6,vquarter_1_3_pel7};
assign q_11 = {vquarter_1_1_pel0,vquarter_1_1_pel1,vquarter_1_1_pel2,vquarter_1_1_pel3,vquarter_1_1_pel4,vquarter_1_1_pel5,vquarter_1_1_pel6,vquarter_1_1_pel7};
assign q_31 = {vquarter_3_1_pel0,vquarter_3_1_pel1,vquarter_3_1_pel2,vquarter_3_1_pel3,vquarter_3_1_pel4,vquarter_3_1_pel5,vquarter_3_1_pel6,vquarter_3_1_pel7};
assign q_33 = {vquarter_3_3_pel0,vquarter_3_3_pel1,vquarter_3_3_pel2,vquarter_3_3_pel3,vquarter_3_3_pel4,vquarter_3_3_pel5,vquarter_3_3_pel6,vquarter_3_3_pel7};
assign q_12 = {vquarter_1_2_pel0,vquarter_1_2_pel1,vquarter_1_2_pel2,vquarter_1_2_pel3,vquarter_1_2_pel4,vquarter_1_2_pel5,vquarter_1_2_pel6,vquarter_1_2_pel7};
assign q_32 = {vquarter_3_2_pel0,vquarter_3_2_pel1,vquarter_3_2_pel2,vquarter_3_2_pel3,vquarter_3_2_pel4,vquarter_3_2_pel5,vquarter_3_2_pel6,vquarter_3_2_pel7};
assign q_10 = {vquarter_1_0_pel0,vquarter_1_0_pel1,vquarter_1_0_pel2,vquarter_1_0_pel3,vquarter_1_0_pel4,vquarter_1_0_pel5,vquarter_1_0_pel6,vquarter_1_0_pel7};
assign q_30 = {vquarter_3_0_pel0,vquarter_3_0_pel1,vquarter_3_0_pel2,vquarter_3_0_pel3,vquarter_3_0_pel4,vquarter_3_0_pel5,vquarter_3_0_pel6,vquarter_3_0_pel7};
assign q_21 = {vhalf_2_1_pel0,vhalf_2_1_pel1,vhalf_2_1_pel2,vhalf_2_1_pel3,vhalf_2_1_pel4,vhalf_2_1_pel5,vhalf_2_1_pel6,vhalf_2_1_pel7};
assign q_23 = {vhalf_2_3_pel0,vhalf_2_3_pel1,vhalf_2_3_pel2,vhalf_2_3_pel3,vhalf_2_3_pel4,vhalf_2_3_pel5,vhalf_2_3_pel6,vhalf_2_3_pel7};
assign q_01 = {vpel_0_1_pel0,vpel_0_1_pel1,vpel_0_1_pel2,vpel_0_1_pel3,vpel_0_1_pel4,vpel_0_1_pel5,vpel_0_1_pel6,vpel_0_1_pel7};
assign q_03 = {vpel_0_3_pel0,vpel_0_3_pel1,vpel_0_3_pel2,vpel_0_3_pel3,vpel_0_3_pel4,vpel_0_3_pel5,vpel_0_3_pel6,vpel_0_3_pel7};
assign q_22 = (frac_x == 2'b01) ? h_02 : h_00;
assign q_02 = (frac_x == 2'b01) ? h_12 : h_10;
// choose candidates accorign to mv
//
assign fracyEqualZero = (frac_y == 2'b00);
assign fracxEqualZero = (frac_x == 2'b00);
// search candidate 0
always @(*) begin
if(half_ip_flag) begin
candi0_pixles = h_00;
candi0_valid = diagonal_pel_valid;
end
else begin
case({fracyEqualZero, fracxEqualZero})
2'b00: begin candi0_pixles = q_11; candi0_valid = vquarter_1_valid; end
2'b01: begin candi0_pixles = q_13; candi0_valid = vquarter_1_valid; end
2'b10: begin candi0_pixles = q_31; candi0_valid = vquarter_3_valid; end
2'b11: begin candi0_pixles = q_33; candi0_valid = vquarter_3_valid; end
endcase
end
end
// search candidate 1
always @(*) begin
if(half_ip_flag) begin
candi1_pixles = h_01;
candi1_valid = vhalf_pel_valid;
end
else begin
case({fracyEqualZero, fracxEqualZero})
2'b00: begin candi1_pixles = q_12; candi1_valid = vquarter_1_2_valid; end
2'b01: begin candi1_pixles = q_10; candi1_valid = vquarter_1_0_valid; end
2'b10: begin candi1_pixles = q_32; candi1_valid = vquarter_3_2_valid; end
2'b11: begin candi1_pixles = q_30; candi1_valid = vquarter_3_0_valid; end
endcase
end
end
// search candidate 2
always @(*) begin
if(half_ip_flag) begin
candi2_pixles = h_02;
candi2_valid = diagonal_pel_valid;
end
else begin
case({fracyEqualZero, fracxEqualZero})
2'b00: begin candi2_pixles = q_13; candi2_valid = vquarter_1_valid; end
2'b01: begin candi2_pixles = q_11; candi2_valid = vquarter_1_valid; end
2'b10: begin candi2_pixles = q_33; candi2_valid = vquarter_3_valid; end
2'b11: begin candi2_pixles = q_31; candi2_valid = vquarter_3_valid; end
endcase
end
end
// search candidate 3
always @(*) begin
if(half_ip_flag) begin
candi3_pixles = h_10;
candi3_valid = hhalf_pel_valid;
end
else begin
case({fracyEqualZero, fracxEqualZero})
2'b00: begin candi3_pixles = q_21; candi3_valid = vhalf_valid; end
2'b01: begin candi3_pixles = q_23; candi3_valid = vhalf_valid; end
2'b10: begin candi3_pixles = q_01; candi3_valid = vpel_valid; end
2'b11: begin candi3_pixles = q_03; candi3_valid = vpel_valid; end
endcase
end
end
// search candidate 4
always @(*) begin
if(half_ip_flag) begin
candi4_pixles = h_11;
candi4_valid = (cnt_ref > 4 && cnt_ref <=12) ;
end
else begin
case({fracyEqualZero, fracxEqualZero})
2'b00: begin candi4_pixles = q_22; candi4_valid = (frac_y == 2'b01) ? diagonal_pel_valid_d : diagonal_pel_valid ; end
2'b01: begin candi4_pixles = h_01; candi4_valid = (frac_y == 2'b01) ? vhalf_pel_valid_d : vhalf_pel_valid ; end
2'b10: begin candi4_pixles = q_02; candi4_valid = hhalf_pel_valid ; end
2'b11: begin candi4_pixles = h_11; candi4_valid = (cnt_ref > 4 && cnt_ref <=12); end
endcase
end
end
// search candidate 5
always @(*) begin
if(half_ip_flag) begin
candi5_pixles = h_12;
candi5_valid = hhalf_pel_valid ;
end
else begin
case({fracyEqualZero, fracxEqualZero})
2'b00: begin candi5_pixles = q_23; candi5_valid = vhalf_valid ; end
2'b01: begin candi5_pixles = q_21; candi5_valid = vhalf_valid ; end
2'b10: begin candi5_pixles = q_03; candi5_valid = vpel_valid ; end
2'b11: begin candi5_pixles = q_01; candi5_valid = vpel_valid ; end
endcase
end
end
// search candidate 6
always @(*) begin
if(half_ip_flag) begin
candi6_pixles = h_00;
candi6_valid = diagonal_pel_valid_d ;
end
else begin
case({fracyEqualZero, fracxEqualZero})
2'b00: begin candi6_pixles = q_31; candi6_valid = vquarter_3_valid ; end
2'b01: begin candi6_pixles = q_33; candi6_valid = vquarter_3_valid ; end
2'b10: begin candi6_pixles = q_11; candi6_valid = vquarter_1_valid ; end
2'b11: begin candi6_pixles = q_13; candi6_valid = vquarter_1_valid ; end
endcase
end
end
// search candidate 7
always @(*) begin
if(half_ip_flag) begin
candi7_pixles = h_01;
candi7_valid = vhalf_pel_valid_d ;
end
else begin
case({fracyEqualZero, fracxEqualZero})
2'b00: begin candi7_pixles = q_32; candi7_valid = vquarter_3_2_valid ; end
2'b01: begin candi7_pixles = q_30; candi7_valid = vquarter_3_0_valid ; end
2'b10: begin candi7_pixles = q_12; candi7_valid = vquarter_1_2_valid ; end
2'b11: begin candi7_pixles = q_10; candi7_valid = vquarter_1_0_valid ; end
endcase
end
end
// search candidate 8
always @(*) begin
if(half_ip_flag) begin
candi8_pixles = h_02;
candi8_valid = diagonal_pel_valid_d ;
end
else begin
case({fracyEqualZero, fracxEqualZero})
2'b00: begin candi8_pixles = q_33; candi8_valid = vquarter_3_valid ; end
2'b01: begin candi8_pixles = q_31; candi8_valid = vquarter_3_valid ; end
2'b10: begin candi8_pixles = q_13; candi8_valid = vquarter_1_valid ; end
2'b11: begin candi8_pixles = q_11; candi8_valid = vquarter_1_valid ; end
endcase
end
end
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
candi0_pixles_o <= 'd0;
candi1_pixles_o <= 'd0;
candi2_pixles_o <= 'd0;
candi3_pixles_o <= 'd0;
candi4_pixles_o <= 'd0;
candi5_pixles_o <= 'd0;
candi6_pixles_o <= 'd0;
candi7_pixles_o <= 'd0;
candi8_pixles_o <= 'd0;
end
else begin
candi0_pixles_o <= candi0_pixles;
candi1_pixles_o <= candi1_pixles;
candi2_pixles_o <= candi2_pixles;
candi3_pixles_o <= candi3_pixles;
candi4_pixles_o <= candi4_pixles;
candi5_pixles_o <= candi5_pixles;
candi6_pixles_o <= candi6_pixles;
candi7_pixles_o <= candi7_pixles;
candi8_pixles_o <= candi8_pixles;
end
end
assign candi0_valid_o = candi0_valid;
assign candi1_valid_o = candi1_valid;
assign candi2_valid_o = candi2_valid;
assign candi3_valid_o = candi3_valid;
assign candi4_valid_o = candi4_valid;
assign candi5_valid_o = candi5_valid;
assign candi6_valid_o = candi6_valid;
assign candi7_valid_o = candi7_valid;
assign candi8_valid_o = candi8_valid;
endmodule
|
`include "orpsoc-defines.v"
// One master, 2 slaves.
module arbiter_ibus
(
// instruction bus in
// Wishbone Master interface
wbm_adr_o,
wbm_dat_o,
wbm_sel_o,
wbm_we_o,
wbm_cyc_o,
wbm_stb_o,
wbm_cti_o,
wbm_bte_o,
wbm_dat_i,
wbm_ack_i,
wbm_err_i,
wbm_rty_i,
// Slave one
// Wishbone Slave interface
wbs0_adr_i,
wbs0_dat_i,
wbs0_sel_i,
wbs0_we_i,
wbs0_cyc_i,
wbs0_stb_i,
wbs0_cti_i,
wbs0_bte_i,
wbs0_dat_o,
wbs0_ack_o,
wbs0_err_o,
wbs0_rty_o,
// Slave two
// Wishbone Slave interface
wbs1_adr_i,
wbs1_dat_i,
wbs1_sel_i,
wbs1_we_i,
wbs1_cyc_i,
wbs1_stb_i,
wbs1_cti_i,
wbs1_bte_i,
wbs1_dat_o,
wbs1_ack_o,
wbs1_err_o,
wbs1_rty_o,
wb_clk,
wb_rst
);
parameter wb_dat_width = 32;
parameter wb_adr_width = 32;
parameter slave0_addr_width = 12;
parameter slave1_addr_width = 28;
input wb_clk;
input wb_rst;
// WB Master
input [wb_adr_width-1:0] wbm_adr_o;
input [wb_dat_width-1:0] wbm_dat_o;
input [3:0] wbm_sel_o;
input wbm_we_o;
input wbm_cyc_o;
input wbm_stb_o;
input [2:0] wbm_cti_o;
input [1:0] wbm_bte_o;
output [wb_dat_width-1:0] wbm_dat_i;
output wbm_ack_i;
output wbm_err_i;
output wbm_rty_i;
// WB Slave 0
output [wb_adr_width-1:0] wbs0_adr_i;
output [wb_dat_width-1:0] wbs0_dat_i;
output [3:0] wbs0_sel_i;
output wbs0_we_i;
output wbs0_cyc_i;
output wbs0_stb_i;
output [2:0] wbs0_cti_i;
output [1:0] wbs0_bte_i;
input [wb_dat_width-1:0] wbs0_dat_o;
input wbs0_ack_o;
input wbs0_err_o;
input wbs0_rty_o;
// WB Slave 1
output [wb_adr_width-1:0] wbs1_adr_i;
output [wb_dat_width-1:0] wbs1_dat_i;
output [3:0] wbs1_sel_i;
output wbs1_we_i;
output wbs1_cyc_i;
output wbs1_stb_i;
output [2:0] wbs1_cti_i;
output [1:0] wbs1_bte_i;
input [wb_dat_width-1:0] wbs1_dat_o;
input wbs1_ack_o;
input wbs1_err_o;
input wbs1_rty_o;
wire [1:0] slave_sel; // One bit per slave
reg watchdog_err;
`ifdef ARBITER_IBUS_WATCHDOG
reg [`ARBITER_IBUS_WATCHDOG_TIMER_WIDTH:0] watchdog_timer;
reg wbm_stb_r; // Register strobe
wire wbm_stb_edge; // Detect its edge
reg wbm_stb_edge_r, wbm_ack_i_r; // Reg these, better timing
always @(posedge wb_clk)
wbm_stb_r <= wbm_stb_o;
assign wbm_stb_edge = (wbm_stb_o & !wbm_stb_r);
always @(posedge wb_clk)
wbm_stb_edge_r <= wbm_stb_edge;
always @(posedge wb_clk)
wbm_ack_i_r <= wbm_ack_i;
// Counter logic
always @(posedge wb_clk)
if (wb_rst) watchdog_timer <= 0;
else if (wbm_ack_i_r) // When we see an ack, turn off timer
watchdog_timer <= 0;
else if (wbm_stb_edge_r) // New access means start timer again
watchdog_timer <= 1;
else if (|watchdog_timer) // Continue counting if counter > 0
watchdog_timer <= watchdog_timer + 1;
always @(posedge wb_clk)
watchdog_err <= (&watchdog_timer);
`else // !`ifdef ARBITER_IBUS_WATCHDOG
always @(posedge wb_clk)
watchdog_err <= 0;
`endif // !`ifdef ARBITER_IBUS_WATCHDOG
// Slave select
// ROM/RAM
assign slave_sel[0] = ~|wbm_adr_o[wb_adr_width - 1:slave0_addr_width];
// DDR
assign slave_sel[1] = ~slave_sel[0] & ~|wbm_adr_o[wb_adr_width - 1:slave1_addr_width];
// Slave out assigns
assign wbs0_adr_i = wbm_adr_o;
assign wbs0_dat_i = wbm_dat_o;
assign wbs0_we_i = wbm_we_o;
assign wbs0_sel_i = wbm_sel_o;
assign wbs0_cti_i = wbm_cti_o;
assign wbs0_bte_i = wbm_bte_o;
assign wbs0_cyc_i = wbm_cyc_o & slave_sel[0];
assign wbs0_stb_i = wbm_stb_o & slave_sel[0];
assign wbs1_adr_i = wbm_adr_o;
assign wbs1_dat_i = wbm_dat_o;
assign wbs1_we_i = wbm_we_o;
assign wbs1_sel_i = wbm_sel_o;
assign wbs1_cti_i = wbm_cti_o;
assign wbs1_bte_i = wbm_bte_o;
assign wbs1_cyc_i = wbm_cyc_o & slave_sel[1];
assign wbs1_stb_i = wbm_stb_o & slave_sel[1];
// Master out assigns
// Don't care about none selected...
assign wbm_dat_i = slave_sel[1] ? wbs1_dat_o :
wbs0_dat_o ;
assign wbm_ack_i = (slave_sel[0] & wbs0_ack_o) |
(slave_sel[1] & wbs1_ack_o);
assign wbm_err_i = (slave_sel[0] & wbs0_err_o) |
(slave_sel[1] & wbs1_err_o) |
watchdog_err;
assign wbm_rty_i = (slave_sel[0] & wbs0_rty_o) |
(slave_sel[1] & wbs1_rty_o);
endmodule // arbiter_ibus
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND3_1_V
`define SKY130_FD_SC_MS__AND3_1_V
/**
* and3: 3-input AND.
*
* Verilog wrapper for and3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__and3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and3_1 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__and3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__and3_1 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__and3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND3_1_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_cpx_rptr_2.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module sctag_cpx_rptr_2 (/*AUTOARG*/
// Outputs
sig_buf,
// Inputs
sig
);
// this repeater has 164 bits
output [163:0] sig_buf;
input [163:0] sig;
assign sig_buf = sig;
//output [7:0] sctag_cpx_req_cq_buf; // sctag to processor request
//output sctag_cpx_atom_cq_buf;
//output [`CPX_WIDTH-1:0] sctag_cpx_data_ca_buf; // sctag to cpx data pkt
//output [7:0] cpx_sctag_grant_cx_buf;
//input [7:0] sctag_cpx_req_cq; // sctag to processor request
//input sctag_cpx_atom_cq;
//input [`CPX_WIDTH-1:0] sctag_cpx_data_ca; // sctag to cpx data pkt
//input [7:0] cpx_sctag_grant_cx;
//assign sctag_cpx_atom_cq_buf = sctag_cpx_atom_cq;
//assign sctag_cpx_data_ca_buf = sctag_cpx_data_ca;
//assign cpx_sctag_grant_cx_buf = cpx_sctag_grant_cx;
//assign sctag_cpx_req_cq_buf = sctag_cpx_req_cq;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND4BB_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__AND4BB_FUNCTIONAL_PP_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__and4bb (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A_N, B_N );
and and0 (and0_out_X , nor0_out, C, D );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND4BB_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A31O_M_V
`define SKY130_FD_SC_LP__A31O_M_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31o with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a31o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a31o_m (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a31o_m (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A31O_M_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:06:29 02/27/2016
// Design Name: Register
// Module Name: C:/Users/Ranolazine/Desktop/Lab/lab5/test_Reg_with_reset.v
// Project Name: lab5
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Register
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_Reg_with_reset;
// Inputs
reg clock_in;
reg regWrite;
reg [4:0] readReg1;
reg [4:0] readReg2;
reg [4:0] writeReg;
reg [31:0] writeData;
reg reset;
parameter PERIOD = 100;
// Outputs
wire [31:0] readData1;
wire [31:0] readData2;
// Instantiate the Unit Under Test (UUT)
Register uut (
.clock_in(clock_in),
.regWrite(regWrite),
.readReg1(readReg1),
.readReg2(readReg2),
.writeReg(writeReg),
.writeData(writeData),
.reset(reset),
.readData1(readData1),
.readData2(readData2)
);
always #(PERIOD/2) clock_in = ~clock_in;
initial begin
// Initialize Inputs
clock_in = 0;
regWrite = 0;
readReg1 = 0;
readReg2 = 0;
writeReg = 0;
writeData = 0;
reset = 0;
// Wait 100 ns for global reset to finish
// Add stimulus here
#185;
regWrite = 'b1;
writeReg = 5'b10101;
writeData = 32'b11111111111111110000000000000000;
#200;
writeReg = 5'b01010;
writeData = 32'b00000000000000001111111111111111;
#200;
regWrite = 'b0;
writeReg = 'b00000;
writeData = 32'b00000000000000000000000000000000;
#50;
readReg1 = 'b10101;
readReg2 = 'b01010;
#20;
reset = 'b1;
end
endmodule
|
`timescale 1 ns / 1 ps
module axis_window #
(
parameter integer C_PIXEL_WIDTH = 8,
parameter integer C_IMG_WBITS = 12,
parameter integer C_IMG_HBITS = 12
)
(
input wire clk,
input wire resetn,
input wire [C_IMG_WBITS-1 : 0] win_left,
input wire [C_IMG_HBITS-1 : 0] win_top,
input wire [C_IMG_WBITS-1 : 0] win_width,
input wire [C_IMG_HBITS-1 : 0] win_height,
/// S_AXIS
input wire s_axis_tvalid,
input wire [C_PIXEL_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tuser,
input wire s_axis_tlast,
output wire s_axis_tready,
/// M_AXIS
output wire m_axis_tvalid,
output wire [C_PIXEL_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tuser,
output wire m_axis_tlast,
input wire m_axis_tready
);
reg gap0;
reg gap1;
reg streaming;
reg [C_PIXEL_WIDTH-1:0] idata;
///reg iuser;
reg ilast;
reg ivalid;
wire iready;
wire inext;
assign inext = ivalid && iready;
assign s_axis_tready = (streaming && ~ilast) && (~ivalid || iready);
wire mnext;
assign mnext = m_axis_tvalid && m_axis_tready;
wire snext;
assign snext = s_axis_tvalid && s_axis_tready;
always @(posedge clk) begin
if (resetn == 1'b0)
gap0 <= 0;
else if (~streaming && ~gap0 && s_axis_tvalid)
gap0 <= 1;
else
gap0 <= 0;
end
always @(posedge clk) begin
if (resetn == 1'b0)
gap1 <= 0;
else
gap1 <= gap0;
end
always @(posedge clk) begin
if (resetn == 1'b0)
streaming <= 0;
else if (gap0)
streaming <= 1;
else if (inext && ilast)
streaming <= 0;
else
streaming <= streaming;
end
always @(posedge clk) begin
if (resetn == 1'b0 || gap0) begin
idata <= 0;
///iuser <= 0;
ilast <= 0;
end
else if (snext) begin
idata <= s_axis_tdata;
///iuser <= s_axis_tuser;
ilast <= s_axis_tlast;
end
end
/**
* @NTOE: ensure the first 'col_update' of every line is at same clock
* as corresponding row_update, i.e. the first clock of 'streaming'
*/
reg [C_IMG_WBITS-1 : 0] col_idx;
reg [C_IMG_HBITS-1 : 0] row_idx;
reg [C_IMG_WBITS-1 : 0] col_idx_bak;
reg [C_IMG_HBITS-1 : 0] row_idx_bak;
wire col_update;
assign col_update = snext;
wire row_update;
assign row_update = gap1;
wire fsync;
assign fsync = gap0 && s_axis_tuser;
wire lsync;
assign lsync = gap0;
always @ (posedge clk) begin
if (resetn == 1'b0 || lsync) begin
col_idx <= 0;
col_idx_bak <= 1;
end
else if (col_update) begin
col_idx <= col_idx_bak;
col_idx_bak <= col_idx_bak + 1;
end
else begin
col_idx <= col_idx;
col_idx_bak <= col_idx_bak;
end
end
always @ (posedge clk) begin
if (resetn == 1'b0 || fsync) begin
row_idx <= 0;
row_idx_bak <= 1;
end
else if (row_update) begin
row_idx <= row_idx_bak;
row_idx_bak <= row_idx_bak + 1;
end
else begin
row_idx <= row_idx;
row_idx_bak <= row_idx_bak;
end
end
wire s_need;
axis_shifter_v2 # (
.C_PIXEL_WIDTH(C_PIXEL_WIDTH),
.C_IMG_WBITS(C_IMG_WBITS),
.C_IMG_HBITS(C_IMG_HBITS)
) axis_shifter_0 (
.clk(clk),
.resetn(resetn),
.fsync(fsync),
.lsync(lsync),
.col_idx(col_idx),
.col_idx_next(col_idx_bak),
.col_update(col_update),
.row_idx(row_idx),
///.row_idx_next(row_idx_bak),
.row_update(row_update),
.s_win_left(win_left),
.s_win_top(win_top),
.s_win_width(win_width),
.s_win_height(win_height),
.s_need(s_need),
.s_sof(m_axis_tuser),
.s_eol(m_axis_tlast)
);
always @ (posedge clk) begin
if (resetn == 1'b0)
ivalid <= 0;
else if (snext)
ivalid <= 1;
else if (mnext)
ivalid <= 0;
else
ivalid <= ivalid;
end
assign iready = ~s_need || m_axis_tready;
assign m_axis_tvalid = s_need && ivalid;
assign m_axis_tdata = idata;
endmodule
|
//////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013, Andrew "bunnie" Huang
//
// See the NOTICE file distributed with this work for additional
// information regarding copyright ownership. The copyright holder
// licenses this file to you under the Apache License, Version 2.0
// (the "License"); you may not use this file except in compliance
// with the License. You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing,
// code distributed under the License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
// KIND, either express or implied. See the License for the
// specific language governing permissions and limitations
// under the License.
//////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module adc_ddr3_tb;
reg clk_p;
wire clk_n;
reg [7:0] data_i_p;
wire [7:0] data_i_n;
reg [7:0] data_q_p;
wire [7:0] data_q_n;
wire [63:0] adc_i;
wire [63:0] adc_q;
reg clk;
reg [29:0] sample_length;
reg [17:0] rbk_startpage;
reg reset;
reg [2:0] EIM_A;
reg EIM_LBA;
reg EIM_RW;
reg [1:0] EIM_CS;
reg [15:0] eim_din;
wire [15:0] ro_d_b;
reg rbk_clear_error;
wire rbk_full_error;
wire rbk_empty_error;
reg rbk_enable;
reg rbk_init;
wire adc_reset;
sync_reset adc_res_sync( .glbl_reset(reset), .clk(clk), .reset(adc_reset) );
reg adc_oclk;
reg adc_sample;
reg [2:0] adc_sample_s;
wire adc_sample_oclk;
reg [29:0] sample_count;
always @(posedge adc_oclk) begin // bring adc_sample into oclk domain
adc_sample_s[2:0] <= {adc_sample_s[1:0], adc_sample};
end
always @(posedge adc_oclk) begin
if( !adc_sample_s[2] & adc_sample_s[1] ) begin
sample_count <= 30'b0;
end else if( adc_sample_s[2] && (sample_count < sample_length) ) begin
sample_count <= sample_count + 30'b1;
end else begin
sample_count <= sample_count;
end
end
assign adc_sample_oclk = (sample_count < sample_length) && adc_sample_s[2];
adc_rx adc_rx(.data_i_p(data_i_p[7:0]),
.data_i_n(data_i_n[7:0]),
.data_q_p(data_q_p[7:0]),
.data_q_n(data_q_n[7:0]),
.clk_p(clk_p),
.clk_n(clk_n),
.adc_i(adc_i),
.adc_q(adc_q),
.oclk(adc_oclk),
.reset(adc_reset)
);
//// ADC to DDR3 interface
// ddr3 port wires
wire adc_ddr3_cmd_en; // ok
wire [3:0] adc_ddr3_cmd_instr; // ok
wire [5:0] adc_ddr3_cmd_bl; // ok
wire [29:0] adc_ddr3_cmd_byte_addr; // ok
reg adc_ddr3_cmd_empty;
reg adc_ddr3_cmd_full; // ok
wire adc_ddr3_wr_en; // ok
wire [7:0] adc_ddr3_wr_mask; // ok
wire [63:0] adc_ddr3_wr_data; // ok
reg adc_ddr3_wr_full; // ok
reg adc_ddr3_wr_empty; // ok
reg [6:0] adc_ddr3_wr_count;
reg adc_ddr3_wr_underrun; // ok
reg adc_ddr3_wr_error; // ok
// local state
reg [5:0] ddr3_burstcnt;
reg [29:0] ddr3_adc_adr;
assign adc_ddr3_cmd_instr = 4'b0000;
assign adc_ddr3_cmd_byte_addr = ddr3_adc_adr[29:0];
assign adc_ddr3_cmd_bl = 6'b01_1111; // always write 32 fifo entries, 0-indexed
assign adc_ddr3_cmd_en = (ddr3_burstcnt == 6'b11_1111);
// i-data on even addresses, aligned on 64-bit boundaries
assign adc_ddr3_wr_data[63:0] = ddr3_burstcnt[0] ? adc_q[63:0] : adc_i[63:0];
// write whenever sampling is commanded, always write groups of 32
assign adc_ddr3_wr_en = (adc_sample_oclk || (ddr3_burstcnt != 6'b0));
assign adc_ddr3_wr_mask = 8'b0; // don't mask any writes
always @(posedge adc_oclk) begin
if( adc_sample_oclk || (ddr3_burstcnt != 6'b0) ) begin
ddr3_burstcnt <= ddr3_burstcnt + 6'b1;
end else begin
ddr3_burstcnt <= 6'b0;
end
// this line below means every time sample is toggled, write pointer goes to 0 automatically
if(!adc_ddr3_wr_en) begin // when we're not writing, reset pointer to 0
ddr3_adc_adr <= 30'b0; // reset buffer to zero when sampling is turned off, and buffer committed
// change the above constant if we want to do multiple offsets in DDR3
end else begin
if(adc_ddr3_cmd_en) begin
ddr3_adc_adr <= ddr3_adc_adr + 30'b1000;
end else begin
ddr3_adc_adr <= ddr3_adc_adr;
end
end
end // always @ (posedge adc_oclk)
/*
wire c1_clk0, c1_rst0;
wire ddr3_dll_locked;
wire ddr3clk;
wire ddr3_calib_done; // to mcb
wire ddr3_p3_cmd_en; // to mcb
wire [2:0] ddr3_p3_cmd_instr;
wire [5:0] ddr3_p3_cmd_bl;
wire [29:0] ddr3_p3_cmd_byte_addr;
wire ddr3_p3_cmd_empty; // from mcb
wire ddr3_p3_cmd_full;
wire ddr3_p3_rd_en; // to mcb
wire [31:0] ddr3_p3_rd_data; // from mcb
wire ddr3_p3_rd_full;
wire ddr3_p3_rd_empty;
wire [6:0] ddr3_p3_rd_count;
wire ddr3_p3_rd_overflow;
wire ddr3_p3_rd_error;
wire dll_reset;
ddr3_clkgen ddr3_clkgen (
.clk50in(clk),
.clk400(ddr3clk),
.RESET(dll_reset),
.LOCKED(ddr3_dll_locked)
);
wire p3_cmd_en;
wire p3_burst_cmd_en;
wire [2:0] p3_cmd_instr;
wire [2:0] p3_burst_cmd_instr;
wire [5:0] p3_cmd_bl;
wire [5:0] p3_burst_cmd_bl;
wire [29:0] p3_cmd_byte_addr;
wire [29:0] p3_burst_addr;
wire p3_rd_en;
wire p3_burst_rd_en;
assign p3_cmd_en = p3_burst_cmd_en;
assign p3_cmd_instr = p3_burst_cmd_instr;
assign p3_cmd_bl = p3_burst_cmd_bl;
assign p3_cmd_byte_addr = p3_burst_addr;
assign p3_rd_en = p3_burst_rd_en;
wire ddr3_reset_local;
ddr3_eim_burst eim_burst(.bclk(bclk_i),
.bus_ad(eim_din),
.bus_a(EIM_A[18:16]), .adv(!EIM_LBA), .rw(EIM_RW), .cs(!EIM_CS[1]),
.rbk_d(ro_d_b),
.ddr3_rd_cmd(p3_burst_cmd_instr),
.ddr3_rd_bl(p3_burst_cmd_bl),
.ddr3_rd_adr(p3_burst_addr),
.ddr3_rd_cmd_en(p3_burst_cmd_en),
.ddr3_rd_cmd_empty(ddr3_p3_cmd_empty),
.ddr3_rd_cmd_full(ddr3_p3_cmd_full),
.ddr3_rd_data(ddr3_p3_rd_data[31:0]),
.ddr3_rd_count(ddr3_p3_rd_count),
.ddr3_rd_empty(ddr3_p3_rd_empty),
.ddr3_rd_full(ddr3_p3_rd_full),
.ddr3_rd_en(p3_burst_rd_en),
.clear_error(rbk_clear_error),
.full_error(rbk_full_error),
.empty_error(rbk_empty_error),
.enable(rbk_enable),
.init(rbk_init),
.startpage(rbk_startpage[17:0]),
.bclk_reset(bclk_reset)
);
sync_reset ddr3_res_sync( .glbl_reset(log_reset), .clk(c1_clk0), .reset(ddr3_reset_local) );
parameter C1_MEM_ADDR_WIDTH = 14;
parameter C1_MEM_BANKADDR_WIDTH = 3;
parameter C1_NUM_DQ_PINS = 16;
wire [C1_MEM_ADDR_WIDTH-1:0] mcb1_dram_a;
wire [C1_MEM_BANKADDR_WIDTH-1:0] mcb1_dram_ba;
wire mcb1_dram_ck;
wire mcb1_dram_ck_n;
wire [C1_NUM_DQ_PINS-1:0] mcb1_dram_dq;
wire mcb1_dram_dqs;
wire mcb1_dram_dqs_n;
wire mcb1_dram_dm;
wire mcb1_dram_ras_n;
wire mcb1_dram_cas_n;
wire mcb1_dram_we_n;
wire mcb1_dram_cke;
wire mcb1_dram_odt;
wire mcb1_dram_reset_n;
wire mcb1_dram_udqs; // for X16 parts
wire mcb1_dram_udqs_n; // for X16 parts
wire mcb1_dram_udm; // for X16 parts
ddr3_if_4port # (
.C1_P0_MASK_SIZE(8),
.C1_P0_DATA_PORT_SIZE(64),
.C1_P1_MASK_SIZE(4),
.C1_P1_DATA_PORT_SIZE(32),
.DEBUG_EN(0),
.C1_MEMCLK_PERIOD(2500),
.C1_CALIB_SOFT_IP("TRUE"),
.C1_SIMULATION("FALSE"),
.C1_RST_ACT_LOW(0),
.C1_INPUT_CLK_TYPE("SINGLE_ENDED"),
.C1_MEM_ADDR_ORDER("ROW_BANK_COLUMN"),
.C1_NUM_DQ_PINS(16),
.C1_MEM_ADDR_WIDTH(14),
.C1_MEM_BANKADDR_WIDTH(3)
)
u_ddr3_if (
.c1_sys_clk (ddr3clk),
.c1_sys_rst_i (reset),
.mcb1_dram_dq (mcb1_dram_dq),
.mcb1_dram_a (mcb1_dram_a),
.mcb1_dram_ba (mcb1_dram_ba),
.mcb1_dram_ras_n (mcb1_dram_ras_n),
.mcb1_dram_cas_n (mcb1_dram_cas_n),
.mcb1_dram_we_n (mcb1_dram_we_n),
.mcb1_dram_odt (mcb1_dram_odt),
.mcb1_dram_cke (mcb1_dram_cke),
.mcb1_dram_ck (mcb1_dram_ck),
.mcb1_dram_ck_n (mcb1_dram_ck_n),
.mcb1_dram_dqs (mcb1_dram_dqs),
.mcb1_dram_dqs_n (mcb1_dram_dqs_n),
.mcb1_dram_udqs (mcb1_dram_udqs), // for X16 parts
.mcb1_dram_udqs_n (mcb1_dram_udqs_n), // for X16 parts
.mcb1_dram_udm (mcb1_dram_udm), // for X16 parts
.mcb1_dram_dm (mcb1_dram_dm),
.mcb1_dram_reset_n (mcb1_dram_reset_n),
.c1_clk0 (c1_clk0),
.c1_rst0 (c1_rst0),
.c1_calib_done (ddr3_calib_done),
.mcb1_rzq (F_DDR3_RZQ),
.mcb1_zio (F_DDR3_ZIO),
.c1_p0_cmd_clk (adc_oclk),
.c1_p0_cmd_en (adc_ddr3_cmd_en),
.c1_p0_cmd_instr (adc_ddr3_cmd_instr),
.c1_p0_cmd_bl (adc_ddr3_cmd_bl),
.c1_p0_cmd_byte_addr (adc_ddr3_cmd_byte_addr),
.c1_p0_cmd_empty (adc_ddr3_cmd_empty),
.c1_p0_cmd_full (adc_ddr3_cmd_full),
.c1_p0_wr_clk (adc_oclk),
.c1_p0_wr_en (adc_ddr3_wr_en),
.c1_p0_wr_mask (adc_ddr3_wr_mask),
.c1_p0_wr_data (adc_ddr3_wr_data),
.c1_p0_wr_full (adc_ddr3_wr_full),
.c1_p0_wr_empty (adc_ddr3_wr_empty),
.c1_p0_wr_count (adc_ddr3_wr_count),
.c1_p0_wr_underrun (adc_ddr3_wr_underrun),
.c1_p0_wr_error (adc_ddr3_wr_error),
.c1_p0_rd_clk (adc_oclk),
.c1_p0_rd_en (1'b0),
// .c1_p0_rd_data (adc_ddr3_rd_data), // read function is not used
// .c1_p0_rd_full (adc_ddr3_rd_full),
// .c1_p0_rd_empty (adc_ddr3_rd_empty),
// .c1_p0_rd_count (adc_ddr3_rd_count),
// .c1_p0_rd_overflow (adc_ddr3_rd_overflow),
// .c1_p0_rd_error (adc_ddr3_rd_error),
// port 2 dedicated to CPU interface
.c1_p2_cmd_clk (bclk_dll),
.c1_p2_cmd_en (p2_cmd_en),
.c1_p2_cmd_instr (p2_cmd_instr),
.c1_p2_cmd_bl (p2_cmd_bl),
.c1_p2_cmd_byte_addr (p2_cmd_byte_addr),
.c1_p2_cmd_empty (ddr3_p2_cmd_empty),
.c1_p2_cmd_full (ddr3_p2_cmd_full),
.c1_p2_wr_clk (bclk_dll),
.c1_p2_wr_en (p2_wr_en),
.c1_p2_wr_mask (p2_wr_mask),
.c1_p2_wr_data (p2_wr_data),
.c1_p2_wr_full (ddr3_p2_wr_full),
.c1_p2_wr_empty (ddr3_p2_wr_empty),
.c1_p2_wr_count (ddr3_p2_wr_count),
.c1_p2_wr_underrun (ddr3_p2_wr_underrun),
.c1_p2_wr_error (ddr3_p2_wr_error)
);
// ========================================================================== //
// Memory model instances //
// ========================================================================== //
generate
if(C1_NUM_DQ_PINS == 16) begin : MEM_INST1
ddr3_model_c1 u_mem_c1(
.ck (mcb1_dram_ck),
.ck_n (mcb1_dram_ck_n),
.cke (mcb1_dram_cke),
.cs_n (1'b0),
.ras_n (mcb1_dram_ras_n),
.cas_n (mcb1_dram_cas_n),
.we_n (mcb1_dram_we_n),
.dm_tdqs ({mcb1_dram_udm,mcb1_dram_dm}),
.ba (mcb1_dram_ba),
.addr (mcb1_dram_a),
.dq (mcb1_dram_dq),
.dqs ({mcb1_dram_udqs,mcb1_dram_dqs}),
.dqs_n ({mcb1_dram_udqs_n,mcb1_dram_dqs_n}),
.tdqs_n (),
.odt (mcb1_dram_odt),
.rst_n (mcb1_dram_reset_n)
);
end else begin
ddr3_model_c1 u_mem_c1(
.ck (mcb1_dram_ck),
.ck_n (mcb1_dram_ck_n),
.cke (mcb1_dram_cke),
.cs_n (1'b0),
.ras_n (mcb1_dram_ras_n),
.cas_n (mcb1_dram_cas_n),
.we_n (mcb1_dram_we_n),
.dm_tdqs (mcb1_dram_dm),
.ba (mcb1_dram_ba),
.addr (mcb1_dram_a),
.dq (mcb1_dram_dq),
.dqs (mcb1_dram_dqs),
.dqs_n (mcb1_dram_dqs_n),
.tdqs_n (),
.odt (mcb1_dram_odt),
.rst_n (mcb1_dram_reset_n)
);
end
endgenerate
*/
parameter PERIOD = 16'd4; // 250 MHz
always begin
clk_p = 1'b0;
#(PERIOD/2) clk_p = 1'b1;
#(PERIOD/2);
end
parameter PERIOD50 = 16'd20; // 50 MHz
always begin
clk = 1'b0;
#(PERIOD50/2) clk = 1'b1;
#(PERIOD50/2);
end
parameter PERIOD_OCLK = 16'd8; // 125 MHz
always begin
adc_oclk = 1'b0;
#(PERIOD_OCLK/2) adc_oclk = 1'b1;
#(PERIOD_OCLK/2);
end
assign clk_n = !clk_p;
assign data_i_n = ~data_i_p;
assign data_q_n = ~data_q_p;
initial begin
reset = 1'b1;
data_i_p[7:0] = 8'b0;
data_q_p[7:0] = 8'b0;
adc_ddr3_cmd_empty = 1'b0;
adc_ddr3_cmd_full = 1'b0;
adc_ddr3_wr_full = 1'b0;
adc_ddr3_wr_empty = 1'b0;
adc_ddr3_wr_count = 6'b0;
adc_ddr3_wr_error = 1'b0;
adc_ddr3_wr_underrun = 1'b0;
sample_length = 30'h1000;
adc_sample = 1'b0;
rbk_startpage = 18'h0;
rbk_clear_error = 1'b0;
rbk_enable = 1'b0;
rbk_init = 1'b0;
EIM_A = 3'b0;
EIM_LBA = 0;
EIM_RW = 0;
EIM_CS = 2'b11;
eim_din = 16'h0;
$stop;
#(PERIOD*128);
reset = 1'b0;
#(PERIOD*128);
// do stuff
repeat(100) begin
data_i_p[7:0] = ({$random} % 256);
data_q_p[7:0] = ({$random} % 256);
#(PERIOD/2);
end
adc_sample = 1'b1;
repeat(1000) begin
data_i_p[7:0] = ({$random} % 256);
data_q_p[7:0] = ({$random} % 256);
#(PERIOD/2);
end
$stop;
end // initial begin
endmodule // adc_ddr3_tb
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:34:40 05/17/2015
// Design Name: Main
// Module Name: C:/Users/dagosttv.ROSE-HULMAN/Documents/School/ECE/ECE398/CAN-Bus-Controller-/Main_test.v
// Project Name: CAN_Controller
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Main
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Main_test;
// Inputs
assign CAN_RX = CAN_TX;
reg RESET;
reg CLOCK_SIGNAL_IN;
reg send_data;
reg [7:0] transmit_data;
// Outputs
wire CAN_TX;
// Instantiate the Unit Under Test (UUT)
Main uut (
.CAN_TX(CAN_TX),
.CAN_RX(CAN_RX),
.RESET(RESET),
.CLOCK_SIGNAL_IN(CLOCK_SIGNAL_IN),
.send_data(send_data),
.transmit_data(transmit_data)
);
initial begin
// Initialize Inputs
RESET = 1;
CLOCK_SIGNAL_IN = 0;
send_data = 0;
transmit_data = 8'b11100011;
// Wait 100 ns for global reset to finish
#100;
#100 RESET = 0;
#1000 send_data = 1;
#100000 $stop;
// Add stimulus here
end
always #10 CLOCK_SIGNAL_IN = ~CLOCK_SIGNAL_IN;
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_181x128a.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_181x128a (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q);
input aclr;
input [191:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [191:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [191:0] sub_wire0;
wire [191:0] q = sub_wire0[191:0];
dcfifo dcfifo_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrfull (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Arria II GX",
dcfifo_component.lpm_numwords = 128,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 192,
dcfifo_component.lpm_widthu = 7,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "192"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "192"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "192"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 192 0 INPUT NODEFVAL "data[191..0]"
// Retrieval info: USED_PORT: q 0 0 192 0 OUTPUT NODEFVAL "q[191..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 192 0 data 0 0 192 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 192 0 @q 0 0 192 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_181x128a.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_181x128a.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_181x128a.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_181x128a.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_181x128a_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_181x128a_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/***************************************************************************************************
** fpga_nes/hw/src/cpu/apu/apu_frame_counter.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* APU frame counter sub-block.
***************************************************************************************************/
module apu_frame_counter
(
input clk_in, // system clock signal
input rst_in, // reset signal
input cpu_cycle_pulse_in, // 1 clk pulse on every cpu cycle
input apu_cycle_pulse_in, // 1 clk pulse on every apu cycle
input [1:0] mode_in, // mode ([0] = IRQ inhibit, [1] = sequence mode)
input mode_wr_in, // update mode
output reg e_pulse_out, // envelope and linear counter pulse (~240 Hz)
output reg l_pulse_out, // length counter and sweep pulse (~120 Hz)
output reg f_pulse_out // frame pulse (~60Hz, should drive IRQ)
);
reg [14:0] q_apu_cycle_cnt, d_apu_cycle_cnt;
reg q_seq_mode, d_seq_mode;
reg q_irq_inhibit, d_irq_inhibit;
always @(posedge clk_in)
begin
if (rst_in)
begin
q_apu_cycle_cnt <= 15'h0000;
q_seq_mode <= 1'b0;
q_irq_inhibit <= 1'b0;
end
else
begin
q_apu_cycle_cnt <= d_apu_cycle_cnt;
q_seq_mode <= d_seq_mode;
q_irq_inhibit <= d_irq_inhibit;
end
end
always @*
begin
d_apu_cycle_cnt = q_apu_cycle_cnt;
d_seq_mode = (mode_wr_in) ? mode_in[1] : q_seq_mode;
d_irq_inhibit = (mode_wr_in) ? mode_in[0] : q_irq_inhibit;
e_pulse_out = 1'b0;
l_pulse_out = 1'b0;
f_pulse_out = 1'b0;
if (apu_cycle_pulse_in)
begin
d_apu_cycle_cnt = q_apu_cycle_cnt + 15'h0001;
if ((q_apu_cycle_cnt == 15'h0E90) || (q_apu_cycle_cnt == 15'h2BB1))
begin
e_pulse_out = 1'b1;
end
else if (q_apu_cycle_cnt == 15'h1D20)
begin
e_pulse_out = 1'b1;
l_pulse_out = 1'b1;
end
else if (!q_seq_mode && (q_apu_cycle_cnt == 15'h3A42))
begin
e_pulse_out = 1'b1;
l_pulse_out = 1'b1;
f_pulse_out = ~q_irq_inhibit;
d_apu_cycle_cnt = 15'h0000;
end
else if ((q_apu_cycle_cnt == 15'h48d0))
begin
e_pulse_out = q_seq_mode;
l_pulse_out = q_seq_mode;
d_apu_cycle_cnt = 15'h0000;
end
end
if (cpu_cycle_pulse_in && mode_wr_in)
d_apu_cycle_cnt = 15'h48d0;
end
endmodule
|
//wb_gpio.v
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
8/31/2012
-Changed some of the naming for clarity
10/29/2011
-added an 'else' statement that so either the
reset HDL will be executed or the actual code
not both
10/23/2011
-fixed the wbs_ack_i to o_wbs_ack
-added the default entries for read and write
to illustrate the method of communication
-added license
9/10/2011
-removed the duplicate wbs_dat_i
-added the wbs_sel_i port
*/
/*
Use this to tell sycamore how to populate the Device ROM table
so that users can interact with your slave
META DATA
identification of your device 0 - 65536
DRT_ID: 1
DRT_SUB_ID: 1
flags (read drt.txt in the slave/device_rom_table directory 1 means
a standard device
DRT_FLAGS: 1
number of registers this should be equal to the nubmer of ???
parameters
DRT_SIZE: 7
USER_PARAMETER: DEFAULT_INTERRUPT_MASK
USER_PARAMETER: DEFAULT_INTERRUPT_EDGE
USER_PARAMETER: DEFAULT_INTERRUPT_BOTH_EDGE
USER_PARAMETER: DEFAULT_INTERRUPT_TIMEOUT
*/
`include "project_defines.v"
module wb_gpio#(
parameter DEFAULT_INTERRUPT_MASK = 0,
parameter DEFAULT_INTERRUPT_EDGE = 0,
parameter DEFAULT_INTERRUPT_BOTH_EDGE = 0,
parameter DEFAULT_INTERRUPT_TIMEOUT = 0
)(
input clk,
input rst,
output [31:0] debug,
//Add signals to control your device here
//Wishbone Bus Signals
input i_wbs_we,
input i_wbs_cyc,
input [3:0] i_wbs_sel,
input [31:0] i_wbs_dat,
input i_wbs_stb,
output reg o_wbs_ack,
output reg [31:0] o_wbs_dat,
input [31:0] i_wbs_adr,
//This interrupt can be controlled from this module or a submodule
output reg o_wbs_int,
output reg [31:0] gpio_out,
input [31:0] gpio_in
);
localparam GPIO = 32'h00000000;
localparam GPIO_OUTPUT_ENABLE = 32'h00000001;
localparam INTERRUPTS = 32'h00000002;
localparam INTERRUPT_ENABLE = 32'h00000003;
localparam INTERRUPT_EDGE = 32'h00000004;
localparam INTERRUPT_BOTH_EDGE = 32'h00000005;
localparam INTERRUPT_TIMEOUT = 32'h00000006;
localparam READ_CLOCK_RATE = 32'h00000007;
//gpio registers
reg [31:0] gpio_direction;
wire [31:0] gpio;
//interrupt registers
reg [31:0] interrupts;
reg [31:0] interrupt_enable;
reg [31:0] interrupt_edge;
reg [31:0] interrupt_both_edge;
reg [31:0] interrupt_timeout_count;
reg [31:0] interrupt_count;
reg clear_interrupts;
genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin : tsbuf
assign gpio[i] = gpio_direction[i] ? gpio_out[i] : gpio_in[i];
end
endgenerate
//blocks
always @ (posedge clk) begin
if (rst) begin
o_wbs_dat <= 32'h00000000;
o_wbs_ack <= 0;
//reset gpio's
gpio_out <= 32'h00000000;
gpio_direction <= 32'h00000000;
//reset interrupts
interrupt_enable <= DEFAULT_INTERRUPT_MASK;
interrupt_edge <= DEFAULT_INTERRUPT_EDGE;
interrupt_both_edge <= DEFAULT_INTERRUPT_BOTH_EDGE;
interrupt_timeout_count <= DEFAULT_INTERRUPT_TIMEOUT;
clear_interrupts <= 0;
end
else begin
clear_interrupts <= 0;
//when the master acks our ack, then put our ack down
if (o_wbs_ack & ~ i_wbs_stb)begin
o_wbs_ack <= 0;
end
if (i_wbs_stb & i_wbs_cyc) begin
//master is requesting somethign
if (i_wbs_we) begin
//write request
case (i_wbs_adr)
GPIO: begin
$display("user wrote %h", i_wbs_dat);
gpio_out <= i_wbs_dat & gpio_direction;
end
GPIO_OUTPUT_ENABLE: begin
$display("%h ->gpio_direction", i_wbs_dat);
gpio_direction <= i_wbs_dat;
end
INTERRUPTS: begin
$display("trying to write %h to interrupts?!", i_wbs_dat);
//can't write to the interrupt
end
INTERRUPT_ENABLE: begin
$display("%h -> interrupt enable", i_wbs_dat);
interrupt_enable <= i_wbs_dat;
clear_interrupts <= 1;
end
INTERRUPT_EDGE: begin
$display("%h -> interrupt_edge", i_wbs_dat);
interrupt_edge <= i_wbs_dat;
clear_interrupts <= 1;
end
INTERRUPT_BOTH_EDGE: begin
$display("%h -> interrupt_both_edge", i_wbs_dat);
interrupt_both_edge <= i_wbs_dat;
clear_interrupts <= 1;
end
INTERRUPT_TIMEOUT: begin
interrupt_timeout_count <= i_wbs_dat;
end
default: begin
end
endcase
end
else begin
if (!o_wbs_ack) begin //Fix double reads
//read request
case (i_wbs_adr)
GPIO: begin
$display("user read %h", i_wbs_adr);
o_wbs_dat <= gpio;
clear_interrupts <= 1;
end
GPIO_OUTPUT_ENABLE: begin
$display("user read %h", i_wbs_adr);
o_wbs_dat <= gpio_direction;
end
INTERRUPTS: begin
$display("user read %h", i_wbs_adr);
o_wbs_dat <= interrupts;
clear_interrupts <= 1;
end
INTERRUPT_ENABLE: begin
$display("user read %h", i_wbs_adr);
o_wbs_dat <= interrupt_enable;
end
INTERRUPT_EDGE: begin
$display("user read %h", i_wbs_adr);
o_wbs_dat <= interrupt_edge;
end
INTERRUPT_BOTH_EDGE: begin
$display("user read %h", i_wbs_adr);
o_wbs_dat <= interrupt_both_edge;
end
INTERRUPT_TIMEOUT: begin
o_wbs_dat <= interrupt_timeout_count;
end
READ_CLOCK_RATE: begin
o_wbs_dat <= `CLOCK_RATE;
end
default: begin
o_wbs_dat <= 32'h00;
end
endcase
end
end
o_wbs_ack <= 1;
end
end
end
//interrupts
reg [31:0] prev_gpio_in;
//this is the change
wire [31:0] pos_gpio_edge;
wire [31:0] neg_gpio_edge;
assign neg_gpio_edge = ((~interrupt_edge | interrupt_both_edge) & (interrupt_enable & ( prev_gpio_in & ~gpio_in)));
assign pos_gpio_edge = (( interrupt_edge | interrupt_both_edge) & (interrupt_enable & (~prev_gpio_in & gpio_in)));
/*
initial begin
$monitor ("%t, interrupts: %h, mask: %h, edge: %h, gpio_edge: %h", $time, interrupts, interrupt_enable, interrupt_edge, gpio_edge);
end
*/
assign debug[0] = gpio[2];
assign debug[1] = gpio[3];
assign debug[2] = interrupt_enable[2];
assign debug[3] = interrupt_enable[3];
assign debug[4] = interrupt_edge[2];
assign debug[5] = interrupt_edge[3];
assign debug[6] = prev_gpio_in[2];
assign debug[7] = prev_gpio_in[3];
assign debug[8] = pos_gpio_edge[2];
assign debug[9] = pos_gpio_edge[3];
assign debug[10] = neg_gpio_edge[2];
assign debug[11] = neg_gpio_edge[3];
assign debug[12] = interrupts[2];
assign debug[13] = interrupts[3];
assign debug[14] = clear_interrupts;
always @ (posedge clk) begin
if (rst) begin
interrupt_count <= 0;
interrupts <= 32'h00000000;
o_wbs_int <= 0;
end
else begin
//user requests to clear the interrupts
if (clear_interrupts) begin
interrupts <= 32'h00000000;
end
if ((pos_gpio_edge > 0) || (neg_gpio_edge > 0)) begin
//check to see if there was a negative or postive edge that occured
interrupts <= (pos_gpio_edge | neg_gpio_edge);
$display ("found an interrupt in the slave");
end
//Implement timeout behavior
if (interrupts == 0) begin
interrupt_count <= 0;
end
if ((interrupts > 0) && (interrupt_timeout_count > 0)) begin
if (interrupt_count < interrupt_timeout_count) begin
interrupt_count <= interrupt_count + 1;
end
else begin
interrupts <= 32'h00000000;
interrupt_count <= 0;
end
end
//Set the wishbone interrupt pin on this module
if (interrupts > 0) begin
o_wbs_int <= 1;
end
else begin
o_wbs_int <= 0;
end
prev_gpio_in <= gpio_in;
end
end
endmodule
|
(*
Copyright 2014 Cornell University
Copyright 2015 Cornell University
This file is part of VPrl (the Verified Nuprl project).
VPrl is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
VPrl is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with VPrl. If not, see <http://www.gnu.org/licenses/>.
Website: http://nuprl.org/html/verification/
Authors: Abhishek Anand & Vincent Rahli
*)
Require Export substitution.
Require Export library.
Require Export terms_pk.
(** printing # $\times$ #×# *)
(** printing <=> $\Leftrightarrow$ #⇔# *)
(* begin hide *)
Definition compute_step_apply_not_well_formed := "lambda or apply not well-formed".
(*Definition compute_step_apseq_not_well_formed := "apseq not well-formed".*)
Definition bad_first_arg := "bad first arg".
Definition fix_not_well_formed := "fix not well-formed".
Definition spread_or_pair_not_well_formed := "spread or pair not well-formed".
Definition bad_first_arg_to_spread := "bad first arg to spread".
Definition sup_or_dsup_not_well_formed := "sup or dsup not well-formed".
Definition bad_first_arg_to_dsup := "bad first arg to dsup".
Definition injection_or_decide_not_well_formed := "injection or decide not well-formed".
Definition bad_args_to_decide := "bad args to decide".
Definition callbyvalue_not_well_formed := "callbyvalue not well-formed".
Definition inappropriate_args_to_try := "inappropriate args to try".
Definition inappropriate_args_to_catch := "inappropriate args to catch".
Definition canonical_form_test_not_well_formed := "canonical form test not well-formed".
Definition arithmetic_operation_not_well_formed := "arithmetic operation not well-formed".
Definition too_few_args_to_arith_op := "too few args to arith op".
Definition cop_not_a_closed_term := "cop: not a closed term".
Definition cop_malformed_2nd_arg := "cop: malformed 2nd arg".
Definition bad_args := "bad args".
Definition too_few_args_to_comparison_op := "too few args to comparison op".
Definition sleep_not_well_formed := "sleep not well-formed".
Definition tuni_not_well_formed := "tuni not well-formed".
Definition minus_not_well_formed := "minus not well-formed".
Definition compute_step_error_not_closed := "not closed".
Definition compute_step_error_abs := "abstraction".
Definition too_few_args_to_parallel := "too few args to parallel".
Definition parallel_malformed_2nd_arg := "parallel: malformed 2nd arg".
Inductive Comput_Result {p} : tuniv :=
| csuccess : @NTerm p -> Comput_Result
| cfailure : String.string-> @NTerm p -> Comput_Result.
Definition on_success {p} (c : @Comput_Result p) (f : NTerm -> NTerm) :=
match c with
| csuccess t => csuccess (f t)
| cfailure s t => cfailure s t
end.
(* end hide *)
(*
To understand where the arguments to these
definitions come from, we will present them in the
context of the [t], original term that we
are computing with when these functions are invoked.
We will also remind the reader of the
binding structure of the
noncanonical [Opid].
*)
(** %\noindent \\*%
Now we define the functions -- compute_step_apply, compute_step_fix, etc. --
that perform a computation step on each of the noncanonicals forms.
We preface each with a reminder of the operator's binding structure and
the structure of [t], the original term we were computing with when the
function was called.
These definitions are
used above in the pattern matching(on [ncr]) that is nested inside
in the definition of [compute_step] above. So, while
defining these functions, we know that
the first argument of the head [Opid]
of the original term is already canonical.
** [NApply]
%\noindent% We begin with [NApply].
%\noindent% [OpBindings (NCan NApply) = [0,0]]
%\noindent% [t = oterm (NCan NApply) ((bterm [] (oterm (Can arg1c) arg1bts))::btsr)]
*)
Definition compute_step_apply {p}
(arg1c:@CanonicalOp p)
(t:@NTerm p)
(arg1bts btsr: list BTerm) :=
match arg1c with
| NLambda =>
match arg1bts, btsr with
| [bterm [v] b], [bterm [] arg] =>
csuccess (apply_bterm (bterm [v] b) [arg])
| _,_ => cfailure compute_step_apply_not_well_formed t
end
| Nseq f =>
match arg1bts, btsr with
| [], [bterm [] arg] => csuccess (mk_eapply (mk_nseq f) arg)
| _,_ => cfailure compute_step_apply_not_well_formed t
end
| _ => cfailure bad_first_arg t
end.
(*
Definition compute_step_apseq {o}
(f : nseq)
(arg1c : @CanonicalOp o)
(t : @NTerm o)
(arg1bts btsr : list (@BTerm o)) :=
match arg1c with
| Nint z =>
match arg1bts, btsr with
| [],[] =>
if Z_le_gt_dec 0 z
then csuccess (mk_nat (f (Z.to_nat z)))
else cfailure compute_step_apseq_not_well_formed t
| _,_ => cfailure compute_step_apseq_not_well_formed t
end
| _ => cfailure bad_first_arg t
end.
*)
Definition compute_step_eapply2 {o}
(t arg1 arg2 : @NTerm o)
(bs : list (@BTerm o)) :=
match bs with
| [] =>
match arg1 with
| oterm (Can NLambda) [bterm [v] b] => csuccess (apply_bterm (bterm [v] b) [arg2])
| oterm (Can (Nseq f)) [] =>
match arg2 with
| oterm (Can (Nint z)) [] =>
if Z_le_gt_dec 0 z
then csuccess (mk_nat (f (Z.to_nat z)))
else cfailure bad_args t
| _ => cfailure bad_args t
end
| sterm f =>
match arg2 with
| oterm (Can (Nint z)) [] =>
if Z_le_gt_dec 0 z
then csuccess (f (Z.to_nat z))
else cfailure bad_args t
| _ => cfailure bad_args t
end
| _ => cfailure bad_args t
end
| _ => cfailure bad_args t
end.
Definition compute_step_eapply1 {o}
(bs : list BTerm)
(t : @NTerm o)
(cstep : Comput_Result)
(arg1 : NTerm)
(ncr : NonCanonicalOp) :=
match bs with
| [] => cfailure bad_args t
| bterm (_ :: _) _ :: _ => cfailure bad_args t
| bterm [] (vterm _) :: _ => cfailure bad_args t
| bterm [] (oterm (Can _) _ as arg2) :: bs2 =>
compute_step_eapply2 t arg1 arg2 bs2
| bterm [] (oterm Exc _ as arg2) :: _ => csuccess arg2
| bterm [] (oterm _ _) :: bs2 => (* ncan/abs *)
on_success cstep (fun f => oterm (NCan ncr) (nobnd arg1 :: nobnd f :: bs2))
| bterm [] (sterm _ as arg2) :: btsr3 =>
compute_step_eapply2 t arg1 arg2 btsr3
end.
Definition eapply_wf {o} (t : @NTerm o) :=
match t with
| sterm _ => true
| oterm (Can (Nseq _)) [] => true
| oterm (Can NLambda) [bterm [_] _] => true
| _ => false
end.
Definition eapply_wf_def {o} (t : @NTerm o) :=
{f : ntseq & t = sterm f}
[+] {f : nseq & t = mk_nseq f}
[+] {v : NVar & {b : NTerm & t = mk_lam v b}}.
Lemma eapply_wf_dec {o} :
forall (t : @NTerm o), decidable (eapply_wf_def t).
Proof.
introv.
destruct t as [v|f|op bs]; allsimpl; tcsp;
try (complete (right;unfold eapply_wf_def;intro x; exrepnd; ginv; repndors; exrepnd; ginv)).
- left; left; eexists; eauto.
- destruct op; allsimpl; tcsp;
try (complete (right;unfold eapply_wf_def;intro x; exrepnd; ginv; repndors; exrepnd; ginv)).
destruct c; allsimpl; tcsp;
try (complete (right;unfold eapply_wf_def;intro x; exrepnd; ginv; repndors; exrepnd; ginv)).
{ destruct bs as [|b bs]; allsimpl; tcsp;
try (complete (right;unfold eapply_wf_def;intro x; exrepnd; ginv; repndors; exrepnd; ginv)).
destruct bs as [|? bs]; allsimpl; tcsp;
try (complete (right;unfold eapply_wf_def;intro x; exrepnd; ginv; repndors; exrepnd; ginv)).
destruct b as [l t].
destruct l as [|v l]; allsimpl; tcsp;
try (complete (right;unfold eapply_wf_def;intro x; exrepnd; ginv; repndors; exrepnd; ginv)).
destruct l as [|? l]; allsimpl; tcsp;
try (complete (right;unfold eapply_wf_def;intro x; exrepnd; ginv; repndors; exrepnd; ginv)).
left; right; right; eexists; eexists; unfold mk_lam; dands; eauto. }
{ destruct bs as [|b bs]; allsimpl; tcsp;
try (complete (right;unfold eapply_wf_def;intro x; exrepnd; ginv; repndors; exrepnd; ginv)).
left; right; left; eexists; unfold mk_nseq; eauto. }
Qed.
Definition compute_step_eapply {o}
(bs : list BTerm)
(t : @NTerm o)
(cstep : Comput_Result)
(arg1 : NTerm)
(ncr : NonCanonicalOp) :=
if eapply_wf arg1
then compute_step_eapply1 bs t cstep arg1 ncr
else cfailure bad_args t.
(** ** [NFix] %\label{sec:comp:step:NFix}%
%\noindent% [NFix] that behaves very much
like the Y combinator.
Note that because of the way [compute_step] was defined,
the following [compute_step_fix] gets invoked
only when the only argument to [NFix] is in
canonical form.
This informally means that
$fix(f)$ reduces to $f \; (fix f)$ only when
$f$ is already in canonical (normal) form.
Otherwise a step of computation will
only evaluate $f$ further.
This is unlike the way Crary defined it in
%\cite{Crary:1998}%, where
$fix(f)$ always reduces to $f \; (fix f)$
(even if $f$ is not in canonical form).
Our change was mainly motivated by
the simplicity of [compute_step] definition
when the first argument of all noncanonical
operators is principal.
Our change was mainly motivated by noting that
the definition of [compute_step] is simpler if
the first argument of all noncanonical operators is
principal. One could also argue that our new definition
avoids the duplication of computation that results from
having to reduce f to canonical form after each unfolding of fix.
It turned out (later) that some Crary's proofs
domain theoretic properties of $fix$ critically
dependend on $fix(f)$ always reducing to $f \; (fix f)$.
With some non-trivial effort, we were able to
restore these properties even for our new
operational semantics of [NFix].
We will describe
these new proofs later in this chapter.
%\noindent% [OpBindings (NCan NFix) = [0]]
%\noindent% [t = oterm (NCan NFix) ((bterm [] (oterm (Can arg1c) arg1bts))::btsr)]
*)
Definition compute_step_fix {p}
(t arg1 : @NTerm p)
(bs : list (@BTerm p)) :=
match bs with
| [] => csuccess (mk_apply arg1 t)
| _ => cfailure fix_not_well_formed t
end.
(** ** [NSpread]
%\noindent% [NSpread] is the elimination
form for [NPair].
%\noindent% [OpBindings (NCan NSpread) = [0,2]]
%\noindent% [t = oterm (NCan NSpread) ((bterm [] (oterm (Can arg1c) arg1bts))::btsr)]
*)
Definition compute_step_spread {p}
(arg1c:@CanonicalOp p)
(t:NTerm)
(arg1bts btsr: list (@BTerm p)) :=
match arg1c with
| NPair =>
match (arg1bts, btsr) with
| ([bterm [] a, bterm [] b], [bterm [va,vb] t]) =>
csuccess (apply_bterm (bterm [va,vb] t) [a,b])
| _ => cfailure spread_or_pair_not_well_formed t
end
| _ => cfailure bad_first_arg_to_spread t
end.
(** ** [NDsup]
%\noindent % [NDsup] behaves exactly like [NSpread]
on [NSup] which is exactly like [NPair].
%\noindent% [OpBindings (NCan NDsup) = [0,2]]
%\noindent% [t = oterm (NCan NDsup) ((bterm [] (oterm (Can arg1c) arg1bts))::btsr)]
*)
Definition compute_step_dsup {p}
(arg1c:@CanonicalOp p)
(t:NTerm)
(arg1bts btsr: list (@BTerm p)) :=
match arg1c with
| NSup =>
match (arg1bts, btsr) with
| ([bterm [] a, bterm [] b], [bterm [va,vb] t]) =>
csuccess (apply_bterm (bterm [va,vb] t) [a,b])
| _ => cfailure sup_or_dsup_not_well_formed t
end
| _ => cfailure bad_first_arg_to_dsup t
end.
(** ** [NDecide]
%\noindent% [NDecide] is the elimination
form for [NInl] and [NInr].
%\noindent% [OpBindings (NCan NDecide) = [0,1,1]]
%\noindent% [t = oterm (NCan NDecide) ((bterm [] (oterm (Can arg1c) arg1bts))::btsr)]
*)
Definition compute_step_decide {p}
(arg1c:@CanonicalOp p)
(t:NTerm)
(arg1bts btsr: list (@BTerm p)) :=
match arg1c with
| NInj ni =>
match arg1bts, btsr with
| [bterm [] u] , [bterm [v1] t1, bterm [v2] t2] =>
match ni with
| NInl => csuccess (apply_bterm (bterm [v1] t1) [u])
| NInr => csuccess (apply_bterm (bterm [v2] t2) [u])
end
| _, _ => cfailure injection_or_decide_not_well_formed t
end
| _ => cfailure bad_args_to_decide t
end.
(** ** [NCbv]
%\noindent% [NCbv] that is the call-by-value form
of application.
%\noindent% [OpBindings (NCan NCbv) = [0,1]]
%\noindent% [t = oterm (NCan NCbv) ((bterm [] (oterm (Can arg1c) arg1bts))::btsr)]
*)
Definition compute_step_cbv {p}
(t arg1 :NTerm)
(btsr : list (@BTerm p)) :=
match btsr with
| [bterm [vs] t] => csuccess (apply_bterm (bterm [vs] t) [arg1])
| _ => cfailure callbyvalue_not_well_formed t
end.
(** ** [NTryCatch]
%\noindent% [NTryCatch] is a feature still under development.
If the first argument of [NTryCatch] is a value then we simply return it.
*)
Definition compute_step_try {p}
(t arg1 : NTerm)
(btsr : list (@BTerm p)) :=
match btsr with
| [bterm [] a, bterm [_] _] =>
csuccess (mk_atom_eq a a arg1 mk_bot)
| _ => cfailure inappropriate_args_to_try t
end.
Definition compute_step_catch {p}
(nc : NonCanonicalOp)
(t : @NTerm p)
(arg1bts btsr : list BTerm) :=
match nc with
| NTryCatch =>
match (btsr, arg1bts) with
| ([bterm [] a, bterm [v] b], [bterm [] a', bterm [] e]) =>
csuccess (mk_atom_eq a a' (subst b v e) (oterm Exc arg1bts))
| _ => cfailure inappropriate_args_to_catch t
end
| _ => csuccess (oterm Exc arg1bts)
end.
(** ** [NCanTest _]
%\noindent% [NCanTest] was recently introduced in
%\cite{Rahli+Bickford+Anand:2013}%. We first define the following
helper function:
*)
Definition canonical_form_test_for {p} (test : CanonicalTest) (op : @CanonicalOp p) : bool :=
match test, op with
| CanIspair, NPair => true
| CanIssup, NSup => true
| CanIsaxiom, NAxiom => true
| CanIslambda, NLambda => true
| CanIsint, Nint _ => true
| CanIsinl, NInj NInl => true
| CanIsinr, NInj NInr => true
| CanIsatom, NTok _ => true
| CanIsuatom, NUTok _ => true
| _, _ => false
end.
(**
%\noindent% [OpBindings (NCan (NCanTest _)) = [0,0,0]]
%\noindent% [t = oterm (NCan (NCanTest _)) ((bterm [] (oterm (Can arg1c) arg1bts))::btsr)]
*)
Definition compute_step_can_test {p}
top
(arg1c:@CanonicalOp p)
(t:NTerm)
(arg1bts btsr: list (@BTerm p)) :=
match btsr with
| [bterm [] arg2nt, bterm [] arg3nt] =>
csuccess (if canonical_form_test_for top arg1c
then arg2nt
else arg3nt)
| _ => cfailure canonical_form_test_not_well_formed t
end.
(** ** [NArithOp _] and [NCompOp _]
%\noindent% The remaining two [NonCanonicalOp]s have the first two
arguments as pricipal, instead of just the first one.
Hence their definitions are a little more complicated
as they might need to recursively evaluate their
second argument if it is not canonical.
To avoid confusing the termination analysis for these recursive calls,
we define these as notations ([ca] and [co]). As evident
from their use in [compute_step], the [cstep] argument in
these notations represents the (recursive use of) [compute_step].
The [NonCanonicalOp]s that represent arithmetic operations just
call the corresponding coq functions and repackage the result
into the corresponding Nuprl [Nint].
[get_int_from_cop] below will
be used to extract the corresponding
Coq numbers out
terms that represent Nuprl numbers.
*)
Definition is_comp_op {o} (op : ComparisonOp) (c : @CanonicalOp o) :=
match op, c with
| CompOpLess, Nint _ => True
| CompOpEq, Nint _ => True
| CompOpEq, NTok _ => True
| CompOpEq, NUTok _ => True
| _,_ => False
end.
(** [get_arith_op] returns the corresponding
arithmetic operation of Coq. *)
Definition get_arith_op (a :ArithOp) : (Z->Z->Z) :=
match a with
| ArithOpAdd => Z.add
| ArithOpMul => Z.mul
| ArithOpSub => Z.sub
| ArithOpDiv => Z.quot
| ArithOpRem => Z.rem
end.
(* Atoms *)
Definition bare_atom_sub {o} := list (NVar # get_patom_set o).
Definition mematom {o} := memberb (get_patom_deq o).
Lemma assert_mematom {o} :
forall (a : get_patom_set o) l,
assert (mematom a l) <=> LIn a l.
Proof.
introv; unfold mematom.
rw @assert_memberb; sp.
Qed.
Definition bare_atom_sub_range {o} (s : @bare_atom_sub o) : list (get_patom_set o) :=
map (fun x => snd x) s.
Definition bare_atom_sub_dom {o} (s : @bare_atom_sub o) : list NVar :=
map (fun x => fst x) s.
Fixpoint wf_bare_atom_sub_b {o} (l : @bare_atom_sub o) : bool :=
match l with
| [] => true
| (v,a) :: l =>
negb (mematom a (bare_atom_sub_range l))
&& wf_bare_atom_sub_b l
end.
Definition wf_bare_atom_sub {o} (s : @bare_atom_sub o) :=
wf_bare_atom_sub_b s = true.
Lemma wf_bare_atom_sub_cons {o} :
forall v a (s : @bare_atom_sub o),
wf_bare_atom_sub ((v,a) :: s)
<=> (!LIn a (bare_atom_sub_range s) # wf_bare_atom_sub s).
Proof.
introv.
unfold wf_bare_atom_sub; simpl.
allrw andb_eq_true.
rw negb_eq_true.
rw @assert_mematom; sp.
Qed.
Lemma wf_bare_atom_sub_iff {o} :
forall (s : @bare_atom_sub o),
wf_bare_atom_sub s <=> no_repeats (bare_atom_sub_range s).
Proof.
induction s; simpl; split; introv k; tcsp.
- apply no_repeats_cons.
destruct a; allsimpl.
rw @wf_bare_atom_sub_cons in k; repnd.
rw <- IHs; sp.
- apply no_repeats_cons in k.
destruct a; allsimpl.
rw @wf_bare_atom_sub_cons; repnd.
rw IHs; sp.
Qed.
Lemma wf_bare_atom_sub_proof_irrelevance {o} :
forall (s : @bare_atom_sub o),
forall x y : wf_bare_atom_sub s,
x = y.
Proof.
sp.
apply UIP_dec.
apply bool_dec.
Qed.
Hint Extern 0 =>
let h := fresh "h" in
match goal with
| [ H1 : wf_bare_atom_sub ?s , H2 : wf_bare_atom_sub ?s |- _ ] =>
pose proof (wf_bare_atom_sub_proof_irrelevance s H2 H1) as h; subst
end : pi.
(*
Definition atom_sub {o} :=
{s : @bare_atom_sub o & wf_bare_atom_sub s}.
*)
(*
Definition in_atom_sub {o} v a (s : @atom_sub o) :=
LIn (v,a) (projT1 s).
Definition atom_sub_dom {o} (s : @atom_sub o) : list NVar :=
bare_atom_sub_dom (projT1 s).
Definition atom_sub_range {o} (s : @atom_sub o) : list (get_patom_set o) :=
bare_atom_sub_range (projT1 s).
Definition is_fresh_atom {o} (s : @atom_sub o) (a : get_patom_set o) :=
!LIn a (atom_sub_range s).
Lemma implies_wf_bare_atom_sub_cons {o} :
forall v a (s : @bare_atom_sub o) (w : wf_bare_atom_sub s),
is_fresh_atom (existT _ s w) a
-> wf_bare_atom_sub ((v,a) :: s).
Proof.
introv f.
unfold is_fresh_atom in f; allsimpl.
unfold atom_sub_range in f; allsimpl.
apply wf_bare_atom_sub_cons; sp.
Qed.
Definition add_atom_sub {o}
(s : @atom_sub o)
(v : NVar)
(a : get_patom_set o) : is_fresh_atom s a -> atom_sub :=
match s with
| existT l w => fun p => existT _ ((v,a) :: l) (implies_wf_bare_atom_sub_cons v a l w p)
end.
*)
Definition atom_sub {o} := list (NVar # get_patom_set o).
Definition atom_sub_range {o} (s : @atom_sub o) : list (get_patom_set o) :=
map (fun x => snd x) s.
Definition atom_sub_dom {o} (s : @atom_sub o) : list NVar :=
map (fun x => fst x) s.
(* a better definition would say that ce_atom_sub does not contain atoms from
either the library or the term we're computing.
But then the definition will become messier.
*)
Record compenv {o} :=
{
ce_library : @library o;
ce_atom_sub : @atom_sub o
}.
Definition add_atom_sub {o}
(ce : @compenv o)
(v : NVar)
(a : get_patom_set o) : compenv :=
{|
ce_atom_sub := (v,a) :: ce_atom_sub ce;
ce_library := ce_library ce
|}.
(*
Definition ce_is_fresh_atom {o} (ce : @compenv o) (a : get_patom_set o) :=
is_fresh_atom (ce_atom_sub ce) a.
Definition ce_add_atom {o}
(ce : @compenv o)
(v : NVar)
(a : get_patom_set o)
(p : ce_is_fresh_atom ce a) : compenv :=
{|
ce_atom_sub := add_atom_sub (ce_atom_sub ce) v a p;
ce_library := ce_library ce
|}.
Fixpoint find_bare_atom {o} (s : @bare_atom_sub o) (var : NVar) : option (get_patom_set o) :=
match s with
| nil => None
| (v, t) :: xs => if beq_var v var then Some t else find_bare_atom xs var
end.
Definition find_atom {o} (s : @atom_sub o) (v : NVar) :=
find_bare_atom (projT1 s) v.
*)
Fixpoint find_atom {o} (s : @atom_sub o) (var : NVar) : option (get_patom_set o) :=
match s with
| nil => None
| (v, t) :: xs => if beq_var v var then Some t else find_atom xs var
end.
Definition compute_var {o} (v : NVar) (ce : @compenv o) (f : get_patom_set o -> @Comput_Result o) : Comput_Result :=
match find_atom (ce_atom_sub ce) v with
| None => cfailure compute_step_error_not_closed (vterm v)
| Some a => f a
end.
(* if we match on arg1c,arg2c instead, we get 22*22 cases when coq
compiles it to simple match statements. *)
(** %\noindent% Here is the function that does one step of computation for
[NArithOp] assuming both the principal arguments are canonical
%\noindent% [OpBindings (NCan NArithOp _) = [0,0]]
[[
t = oterm (NCan (NArithOp op)) ((bterm [] (oterm (Can arg1c) arg1bts))
::((bterm [] (oterm (Can arg2c) arg2bts)
::btsr)))
]]
*)
Definition compute_step_arith {p}
(op : ArithOp)
(arg1c arg2c: @CanonicalOp p)
(arg1bts arg2bts btsr : list (@BTerm p))
(t: @NTerm p) :=
match arg1bts,arg2bts,btsr with
| [],[],[] =>
match get_param_from_cop arg1c , get_param_from_cop arg2c with
| Some (PKi n1), Some (PKi n2) =>
csuccess (oterm (Can (Nint ((get_arith_op op) n1 n2))) [])
| _,_ => cfailure bad_args t
end
| _,_,_ => cfailure arithmetic_operation_not_well_formed t
end.
(** %\noindent% Finally, here is the notation that uses the above function if the second argument
is also canonical, and evaluates it for one step instead if it was non-canonical.
In this notation, [cstep] refers to [compute_step].
%\noindent% [t = oterm (NCan (NArithOp op)) ((bterm [] (oterm (Can arg1c) arg1bts))::btsr)]
*)
Definition ca_aux {o} btsr (t : @NTerm o) arg1bts arg1c op cstep arg1 ncr :=
match btsr with
| [] => cfailure too_few_args_to_arith_op t
| bterm (_ :: _) _ :: _ => cfailure cop_malformed_2nd_arg t
| bterm [] (vterm v) :: btsr3 => cfailure compute_step_error_not_closed t
| (bterm [] (oterm (Can arg2c) arg2bts)::btsr3) =>
compute_step_arith op arg1c arg2c arg1bts arg2bts btsr3 t
| bterm [] (oterm Exc _ as arg2nt) :: _ => csuccess arg2nt
| bterm [] (oterm _ _) :: btsr3 => (* ncan/abs *)
on_success cstep (fun f => oterm (NCan ncr) (bterm [] arg1::bterm [] f::btsr3))
| bterm [] (sterm _) :: btsr3 => cfailure cop_malformed_2nd_arg t
end.
Definition ca_wf {o} (arg1c : @CanonicalOp o) (arg1bts : list (@BTerm o)) :=
match arg1c, arg1bts with
| Nint _, [] => true
| _, _ => false
end.
Definition ca_wf_def {o} (arg1c : @CanonicalOp o) (arg1bts : list (@BTerm o)) :=
{i : Z & arg1c = Nint i # arg1bts = []}.
Lemma ca_wf_dec {o} :
forall (arg1c : @CanonicalOp o) (arg1bts : list (@BTerm o)),
decidable (ca_wf_def arg1c arg1bts).
Proof.
introv.
destruct arg1c; simpl; tcsp;
try (complete (right;unfold ca_wf_def;intro x; exrepnd; ginv)).
destruct arg1bts; tcsp;
try (complete (right;unfold ca_wf_def;intro x; exrepnd; ginv)).
left.
unfold ca_wf_def.
exists z; dands; auto.
Qed.
Definition ca {o} btsr (t : @NTerm o) arg1bts arg1c op cstep arg1 ncr :=
if ca_wf arg1c arg1bts
then ca_aux btsr t arg1bts arg1c op cstep arg1 ncr
else cfailure bad_args t.
(** %\noindent% Finally, we define the case for [NCompOp]
in a similar way as [NArithOp].
*)
(** %\noindent% [OpBindings (NCan NCompOp _) = [0,0,0,0]]
[[
t = oterm (NCan (NCompOp op)) ((bterm [] (oterm (Can arg1c) arg1bts))
::((bterm [] (oterm (Can arg2c) arg2bts)
::btsr)))
]]
*)
Definition compute_step_comp {p}
(op : ComparisonOp)
(arg1c arg2c: @CanonicalOp p)
(arg1bts arg2bts btsr : list (@BTerm p))
(t: NTerm) :=
match (arg1bts,arg2bts,btsr) with
| ([],[], [bterm [] arg3nt, bterm [] arg4nt]) =>
match op with
| CompOpLess =>
match get_param_from_cop arg1c, get_param_from_cop arg2c with
| Some (PKi n1), Some (PKi n2) => csuccess (if Z_lt_le_dec n1 n2 then arg3nt else arg4nt)
| _, _ => cfailure bad_args t
end
| CompOpEq =>
match get_param_from_cop arg1c, get_param_from_cop arg2c with
| Some pk1, Some pk2 => csuccess (if param_kind_deq pk1 pk2 then arg3nt else arg4nt)
| _, _ => cfailure bad_args t
end
end
| _ => cfailure bad_args t
end.
(**
%\noindent% [t = oterm (NCan (NCompOp op)) ((bterm [] (oterm (Can arg1c) arg1bts))::btsr)]
*)
Definition co_aux {o} btsr (t : @NTerm o) arg1bts arg1c op cstep arg1 ncr :=
match btsr with
| [] => cfailure too_few_args_to_comparison_op t
| bterm (_ :: _) _ :: _ => cfailure cop_malformed_2nd_arg t
| bterm [] (vterm v) :: btsr3 => cfailure compute_step_error_not_closed t
| bterm [] (oterm (Can arg2c) arg2bts) :: btsr3 =>
compute_step_comp op arg1c arg2c arg1bts arg2bts btsr3 t
| bterm [] (oterm Exc _ as arg2nt) :: _ => csuccess arg2nt
| bterm [] (oterm _ _) :: btsr3 => (* ncan/abs *)
on_success cstep (fun f => oterm (NCan ncr) (bterm [] arg1::bterm [] f::btsr3))
| bterm [] (sterm _) :: btsr3 => cfailure cop_malformed_2nd_arg t
end.
Definition co_wf {o} op (arg1c : @CanonicalOp o) (arg1bts : list (@BTerm o)) :=
match get_param_from_cop arg1c, arg1bts with
| Some pk, [] =>
match op, pk with
| CompOpEq, _ => true
| CompOpLess, PKi _ => true
| CompOpLess, _ => false
end
| _, _ => false
end.
Definition co_wf_def {o} op (arg1c : @CanonicalOp o) (arg1bts : list (@BTerm o)) :=
{pk : param_kind
& get_param_from_cop arg1c = Some pk
# arg1bts = []
# (op = CompOpEq
[+] {i : Z & op = CompOpLess # pk = PKi i})}.
Lemma co_wf_dec {o} :
forall op (arg1c : @CanonicalOp o) (arg1bts : list (@BTerm o)),
decidable (co_wf_def op arg1c arg1bts).
Proof.
introv.
destruct arg1c; simpl; tcsp;
try (complete (right;unfold co_wf_def;intro x; exrepnd; ginv; repndors; exrepnd; ginv));
destruct arg1bts; tcsp;
try (complete (right;unfold co_wf_def;intro x; exrepnd; ginv; repndors; exrepnd; ginv));
destruct op; tcsp;
try (complete (right;unfold co_wf_def;intro x; exrepnd; ginv; repndors; exrepnd; ginv));
try (complete (left; unfold co_wf_def; exists (@PKi o z); dands; tcsp));
try (complete (left; unfold co_wf_def; exists (@PKs o s); dands; tcsp));
try (complete (left; unfold co_wf_def; exists (@PKa o g); dands; tcsp)).
left; unfold co_wf_def.
exists (@PKi o z); dands; tcsp.
right.
exists z; dands; auto.
Qed.
Definition co {o} btsr (t : @NTerm o) arg1bts arg1c op cstep arg1 ncr :=
if co_wf op arg1c arg1bts
then co_aux btsr (t : @NTerm o) arg1bts arg1c op cstep arg1 ncr
else cfailure bad_args t.
(** ** [NSleep]
%\noindent% [NSleep] is a feature still under development.
[NSleep] calls on the sleep system function.
*)
Definition compute_step_sleep {p}
(arg1c : @CanonicalOp p)
(t : @NTerm p)
(arg1bts btsr : list (@BTerm p)) :=
match (arg1bts, btsr, get_param_from_cop arg1c) with
| ([],[],Some (PKi n)) =>
(* sleep for n milliseconds *)
csuccess mk_axiom
| _ => cfailure sleep_not_well_formed t
end.
(** ** [NTUni]
%\noindent% [NTUni] compute to regular universes.
*)
Definition compute_step_tuni {p}
(arg1c : @CanonicalOp p)
(t : @NTerm p)
(arg1bts btsr : list (@BTerm p)) :=
match (arg1bts, btsr, get_param_from_cop arg1c) with
| ([],[],Some (PKi n)) =>
if Z_le_gt_dec 0 n
then csuccess (mk_uni (Z.to_nat n))
else cfailure tuni_not_well_formed t
| _ => cfailure tuni_not_well_formed t
end.
(** ** [NMinus]
%\noindent% [NMinus] is the regular minus unary operator.
*)
Definition compute_step_minus {p}
(arg1c : @CanonicalOp p)
(t : @NTerm p)
(arg1bts btsr : list (@BTerm p)) :=
match (arg1bts, btsr, get_param_from_cop arg1c) with
| ([],[],Some (PKi n)) => csuccess (mk_integer (- n))
| _ => cfailure minus_not_well_formed t
end.
(*
CoInductive atom_stream {o} :=
| atom_stream_cons : get_patom_set o -> atom_stream -> atom_stream.
Record ComputationContext {o} :=
{
lib : @library o;
freshAtoms : list (get_patom_set o)
}.
*)
Definition compute_step_lib {o}
(lib : @library o)
(opabs : opabs)
(bs : list (@BTerm o)) :=
match unfold_abs lib opabs bs with
| Some u => csuccess u
| None => cfailure compute_step_error_abs (oterm (Abs opabs) bs)
end.
Definition utok_sub {o} := list (get_patom_set o # @NTerm o).
Fixpoint utok_sub_find {o} (sub : @utok_sub o) (a : get_patom_set o) : option NTerm :=
match sub with
| nil => None
| (x,t) :: xs =>
if get_patom_deq o x a
then Some t
else utok_sub_find xs a
end.
Definition subst_utok {o} (a : @get_patom_set o) (bs : list BTerm) (sub : utok_sub) : NTerm :=
match utok_sub_find sub a with
| None => oterm (Can (NUTok a)) bs
| Some t => t
end.
Fixpoint subst_utokens_aux {o} (t : @NTerm o) (sub : utok_sub) : NTerm :=
match t with
| vterm v => t
| sterm f => sterm f
| oterm op bs =>
match op with
| Can (NUTok a) => subst_utok a (map (fun b => subst_utokens_aux_b b sub) bs) sub
| _ => oterm op (map (fun b => subst_utokens_aux_b b sub) bs)
end
end
with subst_utokens_aux_b {o} (b : @BTerm o) (sub : utok_sub) : BTerm :=
match b with
| bterm vs t =>
bterm vs (subst_utokens_aux t sub)
end.
Fixpoint free_vars_utok_sub {o} (sub : @utok_sub o) :=
match sub with
| [] => []
| (_,t) :: s => free_vars t ++ free_vars_utok_sub s
end.
Definition subst_utokens {p} (t : @NTerm p) (sub : utok_sub) : NTerm :=
let sfr := free_vars_utok_sub sub in
if dec_disjointv (bound_vars t) sfr
then subst_utokens_aux t sub
else subst_utokens_aux (change_bvars_alpha sfr t) sub.
Definition get_utokens_library_entry {p} (entry : @library_entry p) : list (get_patom_set p) :=
match entry with
| lib_abs opabs vars rhs correct => get_utokens_so rhs
end.
Definition get_utokens_library {p} (lib : @library p) : list (get_patom_set p) :=
flat_map get_utokens_library_entry lib.
Definition get_utokens_ce {o} (ce : @compenv o) : list (get_patom_set o) :=
get_utokens_library (ce_library ce)
++ atom_sub_range (ce_atom_sub ce).
Definition valid_atom_sub {o} (sub : @atom_sub o) (ce : @compenv o) (t : @NTerm o) :=
disjoint (atom_sub_range sub)
(get_utokens_library (ce_library ce) ++ get_utokens t)
# atom_sub_dom sub = atom_sub_dom (ce_atom_sub ce).
Definition mk_ce {o} (lib : @library o) (sub : @atom_sub o) : compenv :=
{| ce_library := lib; ce_atom_sub := sub |}.
Definition ce_change_atom_sub {o} (ce : @compenv o) (sub : @atom_sub o) : compenv :=
mk_ce (ce_library ce) sub.
(* maps the atoms from [ce] to the atoms in [sub] *)
Definition mk_utok_sub {o} (sub : @atom_sub o) (ce : @compenv o) : @utok_sub o :=
combine (atom_sub_range (ce_atom_sub ce))
(map mk_utoken (atom_sub_range sub)).
(*
Lemma find_bare_atom_some_eq_doms {o} :
forall (s1 s2 : @bare_atom_sub o) v a,
find_bare_atom s1 v = Some a
-> bare_atom_sub_dom s1 = bare_atom_sub_dom s2
-> {a' : get_patom_set o & find_bare_atom s2 v = Some a'}.
Proof.
induction s1; destruct s2; introv fa e; allsimpl; ginv.
destruct a; destruct p; allsimpl.
boolvar; ginv; cpx.
- eexists; eauto.
- eapply IHs1 in fa; eauto.
Qed.
Lemma find_atom_some_eq_doms {o} :
forall (s1 s2 : @atom_sub o) v a,
find_atom s1 v = Some a
-> atom_sub_dom s1 = atom_sub_dom s2
-> {a' : get_patom_set o & find_atom s2 v = Some a'}.
Proof.
introv.
destruct s1 as [s1 w1].
destruct s2 as [s2 w2].
unfold find_atom; simpl.
unfold atom_sub_dom; simpl.
apply find_bare_atom_some_eq_doms.
Qed.
Lemma find_bare_atom_some {o} :
forall (s : @bare_atom_sub o) v a,
find_bare_atom s v = Some a
-> LIn (v,a) s.
Proof.
induction s; introv e; allsimpl; tcsp.
destruct a; boolvar; ginv; tcsp.
Qed.
Lemma find_atom_some {o} :
forall (s : @atom_sub o) v a,
find_atom s v = Some a
-> in_atom_sub v a s.
Proof.
introv fa.
destruct s.
unfold find_atom in fa; unfold in_atom_sub; allsimpl.
apply find_bare_atom_some in fa; auto.
Qed.
*)
Lemma find_atom_some {o} :
forall (s : @atom_sub o) v a,
find_atom s v = Some a
-> LIn (v,a) s.
Proof.
induction s; introv e; allsimpl; tcsp.
destruct a; boolvar; ginv; tcsp.
Qed.
(*
Lemma implies_bare_atom_sub_range {o} :
forall (s : @bare_atom_sub o) v a,
LIn (v,a) s -> LIn a (bare_atom_sub_range s).
Proof.
induction s; introv i; allsimpl; tcsp.
repndors; subst; tcsp.
destruct a; allsimpl; tcsp.
apply IHs in i; sp.
Qed.
Lemma implies_atom_sub_range {o} :
forall (s : @atom_sub o) v a,
in_atom_sub v a s -> LIn a (atom_sub_range s).
Proof.
introv i.
destruct s.
unfold in_atom_sub in i; unfold atom_sub_range; allsimpl.
apply implies_bare_atom_sub_range in i; auto.
Qed.
*)
Lemma implies_atom_sub_range {o} :
forall (s : @atom_sub o) v a,
LIn (v,a) s -> LIn a (atom_sub_range s).
Proof.
induction s; introv i; allsimpl; tcsp.
repndors; subst; tcsp.
destruct a; allsimpl; tcsp.
apply IHs in i; sp.
Qed.
(*
Lemma utok_sub_find_if_find_bare_atom {o} :
forall (s1 s2 : @bare_atom_sub o) v a1 a2,
find_bare_atom s1 v = Some a1
-> find_bare_atom s2 v = Some a2
-> wf_bare_atom_sub s1
-> wf_bare_atom_sub s2
-> bare_atom_sub_dom s1 = bare_atom_sub_dom s2
-> utok_sub_find (combine (bare_atom_sub_range s1) (map mk_utoken (bare_atom_sub_range s2))) a1
= Some (mk_utoken a2).
Proof.
induction s1; destruct s2; introv fa1 fa2 w1 w2 e; allsimpl; tcsp.
destruct a, p; allsimpl.
allrw @wf_bare_atom_sub_cons; repnd.
boolvar; allsimpl; cpx.
- provefalse.
apply find_bare_atom_some in fa1.
apply implies_bare_atom_sub_range in fa1; sp.
- eapply IHs1; eauto.
Qed.
Lemma utok_sub_find_if_find_atom {o} :
forall (s1 s2 : @atom_sub o) v a1 a2,
find_atom s1 v = Some a1
-> find_atom s2 v = Some a2
-> atom_sub_dom s1 = atom_sub_dom s2
-> utok_sub_find (combine (atom_sub_range s1) (map mk_utoken (atom_sub_range s2))) a1
= Some (mk_utoken a2).
Proof.
introv fa1 fa2 e.
destruct s1 as [s1 w1].
destruct s2 as [s2 w2].
allunfold @find_atom; allsimpl.
allunfold @atom_sub_dom; allsimpl.
allunfold @atom_sub_range; allsimpl.
eapply utok_sub_find_if_find_bare_atom; eauto.
Qed.
Lemma find_atom_if_valid {o} :
forall ce s (t : @NTerm o) v a,
find_atom (ce_atom_sub ce) v = Some a
-> valid_atom_sub s ce t
-> {a' : get_patom_set o
& find_atom s v = Some a'
# !LIn a' (get_utokens t ++ get_utokens_library (ce_library ce))
# (forall bs, subst_utok a bs (mk_utok_sub s ce) = mk_utoken a') }.
Proof.
introv fa val.
unfold valid_atom_sub in val.
destruct ce; allsimpl; repnd.
symmetry in val.
dup fa as f.
eapply @find_atom_some_eq_doms in fa;[|eauto].
exrepnd.
dup fa0 as f'.
apply find_atom_some in fa0.
apply implies_atom_sub_range in fa0.
apply val0 in fa0.
allrw in_app_iff; allrw not_over_or; repnd.
exists a'; dands; auto; tcsp.
- allrw in_app_iff; tcsp.
- introv.
unfold subst_utok, mk_utok_sub; simpl.
rw (utok_sub_find_if_find_atom ce_atom_sub0 s v a a'); auto.
Qed.
*)
(* similar to get_utokens but designed to handle things like:
[mk_fresh v (mk_apply (sterm (fun _ => mk_utoken a)) mk_zero)]
The issue is that if we don't look inside sequences, we could
pick the atom [a] to replace [v], and the application
[mk_apply (sterm (fun _ => mk_utoken a)) mk_zero]
would then reduce to [mk_utoken a], and we would then rebind the
variable by replacing [a] by [v] and forming [mk_fresh v v].
However, the two [a]'s are supposed to be different.
Therefore, because a new fresh atom is picked at each step, we could
also make sure that the one we pick is different from ones that
become ``visible`` after a computation step. We say that atoms in
sequences are not ``visible`` because they cannot be substituted and
[get_utokens] doesn't collect them.
*)
Fixpoint get_utokens_step_seq {o} (t : @NTerm o) : list (get_patom_set o) :=
match t with
| vterm _ => []
| sterm _ => []
| oterm op bs =>
(get_utokens_o op)
++ (flat_map get_utokens_step_seq_b bs)
++ (match op with
| NCan NApply =>
match bs with
| bterm [] (sterm f) :: bterm [] (oterm (Can (Nint z)) _) :: _ =>
if Z_le_gt_dec 0 z
then get_utokens_step_seq (f (Z.to_nat z))
else []
| _ => []
end
| NCan NEApply =>
match bs with
| bterm [] (sterm f) :: bterm [] (oterm (Can (Nint z)) _) :: _ =>
if Z_le_gt_dec 0 z
then get_utokens_step_seq (f (Z.to_nat z))
else []
| _ => []
end
| _ => []
end)
end
with get_utokens_step_seq_b {o} (bt : @BTerm o) : list (get_patom_set o) :=
match bt with
| bterm _ t => get_utokens_step_seq t
end.
Definition get_utokens_step_seq_oterm {o} (op : @Opid o) (bs : list (@BTerm o)) :=
match op with
| NCan NApply =>
match bs with
| bterm [] (sterm f) :: bterm [] (oterm (Can (Nint z)) _) :: _ =>
if Z_le_gt_dec 0 z
then get_utokens_step_seq (f (Z.to_nat z))
else []
| _ => []
end
| NCan NEApply =>
match bs with
| bterm [] (sterm f) :: bterm [] (oterm (Can (Nint z)) _) :: _ =>
if Z_le_gt_dec 0 z
then get_utokens_step_seq (f (Z.to_nat z))
else []
| _ => []
end
| _ => []
end.
Definition fold_get_utokens_step_seq_oterm {o} :
forall op (bs : list (@BTerm o)),
match op with
| NCan NApply =>
match bs with
| bterm [] (sterm f) :: bterm [] (oterm (Can (Nint z)) _) :: _ =>
if Z_le_gt_dec 0 z
then get_utokens_step_seq (f (Z.to_nat z))
else []
| _ => []
end
| NCan NEApply =>
match bs with
| bterm [] (sterm f) :: bterm [] (oterm (Can (Nint z)) _) :: _ =>
if Z_le_gt_dec 0 z
then get_utokens_step_seq (f (Z.to_nat z))
else []
| _ => []
end
| _ => []
end = get_utokens_step_seq_oterm op bs.
Proof. sp. Qed.
Lemma subset_get_utokens_get_utokens_step_seq {o} :
forall (t : @NTerm o),
subset (get_utokens t) (get_utokens_step_seq t).
Proof.
nterm_ind1s t as [v|f ind|op bs ind] Case; simpl; eauto 3 with slow.
Case "oterm".
apply app_subset; dands; eauto 3 with slow;[].
apply subset_app_l.
apply subset_app_r.
apply subset_flat_map2; introv i.
destruct x as [l t]; simpl.
eapply ind; eauto 3 with slow.
Qed.
Lemma osubset_get_utokens_step_seq_get_cutokens {o} :
forall (t : @NTerm o),
subseto (get_utokens_step_seq t) (get_cutokens t).
Proof.
nterm_ind1s t as [v|f ind|op bs ind] Case;
simpl; eauto 3 with slow.
Case "oterm".
allrw @subseto_app_l.
dands.
- eapply subseto_oeqset;[|apply oeqset_sym;apply oeqset_oappl_OLL].
apply implies_subseto_app_r; left; apply subseto_refl.
- eapply subseto_oeqset;[|apply oeqset_sym;apply oeqset_oappl_OLL].
apply implies_subseto_app_r; right.
apply subseto_flat_map2; introv i.
destruct x as [l t]; simpl.
eapply ind; eauto 3 with slow.
- dopid op as [can|ncan|exc|abs] SCase; simpl; eauto 3 with slow;[].
SCase "NCan".
dopid_noncan ncan SSCase; simpl; eauto 3 with slow;[|].
+ SSCase "NApply".
destruct bs as [|b1 bs]; simpl; eauto 3 with slow;[].
destruct b1 as [l1 t1].
destruct l1; simpl; eauto 3 with slow;[].
destruct t1 as [v1|f1|op1 bs1]; simpl; eauto 3 with slow;[].
destruct bs as [|b2 bs]; simpl; eauto 3 with slow;[].
destruct b2 as [l2 t2].
destruct l2; simpl; eauto 3 with slow;[].
destruct t2 as [v2|f2|op2 bs2]; simpl; eauto 3 with slow;[].
dopid op2 as [can2|ncan2|exc2|abs2] SSSCase; simpl; eauto 3 with slow;[].
SSSCase "Can".
destruct can2; simpl; eauto 3 with slow; [].
boolvar; simpl; eauto 3 with slow;[].
eapply subseto_oeqset;[|apply oeqset_sym;apply oeqset_oappl_OLL].
apply implies_subseto_cons_ols_r; left.
apply Wf_Z.Z_of_nat_complete_inf in l; exrepnd; subst.
rw Znat.Nat2Z.id.
exists n.
eapply ind;simpl;[left;reflexivity|].
simpl.
eapply ord_le_trans;[|apply ord_le_OS].
eapply implies_ord_le_limit_right; apply ord_le_refl.
+ SSCase "NEApply".
destruct bs as [|b1 bs]; simpl; eauto 3 with slow;[].
destruct b1 as [l1 t1].
destruct l1; simpl; eauto 3 with slow;[].
destruct t1 as [v1|f1|op1 bs1]; simpl; eauto 3 with slow;[].
destruct bs as [|b2 bs]; simpl; eauto 3 with slow;[].
destruct b2 as [l2 t2].
destruct l2; simpl; eauto 3 with slow;[].
destruct t2 as [v2|f2|op2 bs2]; simpl; eauto 3 with slow;[].
dopid op2 as [can2|ncan2|exc2|abs2] SSSCase; simpl; eauto 3 with slow;[].
SSSCase "Can".
destruct can2; simpl; eauto 3 with slow; [].
boolvar; simpl; eauto 3 with slow;[].
eapply subseto_oeqset;[|apply oeqset_sym;apply oeqset_oappl_OLL].
apply implies_subseto_cons_ols_r; left.
apply Wf_Z.Z_of_nat_complete_inf in l; exrepnd; subst.
rw Znat.Nat2Z.id.
exists n.
eapply ind;simpl;[left;reflexivity|].
simpl.
eapply ord_le_trans;[|apply ord_le_OS].
eapply implies_ord_le_limit_right; apply ord_le_refl.
Qed.
Definition get_fresh_atom {o} (t : @NTerm o) : get_patom_set o :=
projT1 (fresh_atom o (get_utokens t)).
Lemma get_fresh_atom_prop {o} :
forall (t : @NTerm o),
!LIn (get_fresh_atom t) (get_utokens t).
Proof.
introv i.
unfold get_fresh_atom in i.
destruct (fresh_atom o (get_utokens t)); allsimpl; sp.
Qed.
Lemma get_fresh_atom_prop2 {o} :
forall (t : @NTerm o),
!LIn (get_fresh_atom t) (get_utokens t).
Proof.
introv i.
(* apply subset_get_utokens_get_utokens_step_seq in i.*)
apply get_fresh_atom_prop in i; auto.
Qed.
Lemma eq_fresh_atom {o} :
forall (t1 t2 : @NTerm o),
get_utokens t1 = get_utokens t2
-> get_fresh_atom t1 = get_fresh_atom t2.
Proof.
introv e.
unfold get_fresh_atom.
rw e; auto.
Qed.
(*
Lemma implies_ce_is_fresh_atom {o} :
forall (ce : @compenv o) (t : @NTerm o) a,
!LIn a (get_utoks_norep ce t)
-> ce_is_fresh_atom ce a.
Proof.
introv ni.
unfold ce_is_fresh_atom, is_fresh_atom.
unfold get_utoks_norep in ni.
unfold get_utokens_ce in ni.
allrw in_remove_repeats.
allrw in_app_iff; allrw not_over_or; repnd; auto.
Qed.
Definition ce_add_fresh_atom {o}
(ce : @compenv o)
(v : NVar)
(a : get_patom_set o)
(t : @NTerm o)
(p : !LIn a (get_utoks_norep ce t)) : compenv :=
ce_add_atom ce v a (implies_ce_is_fresh_atom ce t a p).
*)
Definition maybe_new_var {o} (v : NVar) (vs : list NVar) (t : @NTerm o) :=
if memvar v vs then newvar t else v.
(* We could do better by not generating a [mk_fresh] term when [v] is in [vs]
but that messes up [implies_alpha_eq_pushdown_fresh] *)
Definition mk_fresh_bterm {o} (v : NVar) (b : @BTerm o) :=
match b with
| bterm vs t => bterm vs (mk_fresh (maybe_new_var v vs t) t)
end.
Definition mk_fresh_bterms {o} (v : NVar) (bs : list (@BTerm o)) :=
map (mk_fresh_bterm v) bs.
Definition pushdown_fresh {o} (v : NVar) (t : @NTerm o) :=
match t with
| vterm x => mk_fresh v t
| sterm f => sterm f
| oterm op bs => oterm op (mk_fresh_bterms v bs)
end.
Definition compute_step_fresh {o}
(lib : @library o)
(ncan : NonCanonicalOp)
(t : @NTerm o)
(v : NVar)
(vs : list NVar)
(u : NTerm)
(bs : list (@BTerm o))
(comp : Comput_Result)
(a : get_patom_set o) :=
match ncan, vs, bs with
| NFresh,[],[] =>
match u with
| vterm x =>
if deq_nvar v x
then csuccess t
else cfailure compute_step_error_not_closed t
| sterm f => csuccess (pushdown_fresh v u)
| oterm (Can _) _ => csuccess (pushdown_fresh v u)
| oterm Exc _ => csuccess (pushdown_fresh v u)
| oterm (Abs _) _ => on_success comp (fun r => mk_fresh v (subst_utokens r [(a,mk_var v)]))
| oterm (NCan _) _ => on_success comp (fun r => mk_fresh v (subst_utokens r [(a,mk_var v)]))
end
| _,_,_ => cfailure "check 1st arg" t
end.
(* begin hide *)
Definition not_int_cop {p} (c: @CanonicalOp p) :=
match c with
| Nint _ => false
| _ => true
end.
Lemma compute_comp_test_testcase1 {p} :
compute_step_comp CompOpLess (Nint (Z.of_nat 1)) (Nint (Z.of_nat 2))
[] [] [bterm [] (vterm nvarx) , bterm [] (vterm nvary)] (vterm nvarx)=
csuccess (@vterm p nvarx).
Proof. reflexivity. Qed.
Lemma compute_comp_test_testcase2 {p} :
compute_step_comp CompOpLess (Nint (Z.of_nat 3)) (Nint (Z.of_nat 2))
[] [] [bterm [] (vterm nvarx) , bterm [] (vterm nvary)] (vterm nvarx)=
csuccess (@vterm p nvary).
Proof. reflexivity. Qed.
Definition compute_step_canonical_form_test {p}
(test : CanonicalTest)
(cop : @CanonicalOp p)
(b c : @NTerm p) : NTerm :=
if canonical_form_test_for test cop
then b
else c.
Definition compute_step_parallel {o}
(arg1c : @CanonicalOp o)
(t : @NTerm o)
(arg1bts : list (@BTerm o))
(btsr : list (@BTerm o)) : @Comput_Result o :=
csuccess mk_axiom.
(* This is a stub for what should really come here.
I'll make the parallel return its principal argument if its canonical
otherwise it will make step of computation on its principal argument
and then rotate its subterms.
This means, I'll have to change the way computation on non-canonical
terms and abstractions work :(
*)
(*
*** Local Variables:
*** coq-load-path: ("." "../util/" "../terms/")
*** End:
*)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKINV_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__CLKINV_FUNCTIONAL_PP_V
/**
* clkinv: Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__clkinv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKINV_FUNCTIONAL_PP_V |
//////////////////////////////////////////////////////////////////////////////
//name : server
//input : input_eth_rx:16
//input : input_socket:16
//output : output_socket:16
//output : output_eth_tx:16
//source_file : server.c
///======
///
///Created by C2CHIP
//////////////////////////////////////////////////////////////////////////////
// Register Allocation
// ===================
// Register Name Size
// 0 put_eth return address 2
// 1 variable i 2
// 2 put_socket return address 2
// 3 variable i 2
// 4 get_eth return address 2
// 5 variable get_eth return value 2
// 6 rdy_eth return address 2
// 7 variable rdy_eth return value 2
// 8 get_socket return address 2
// 9 variable get_socket return value 2
// 10 array 2
// 11 variable checksum 4
// 12 reset_checksum return address 2
// 13 add_checksum return address 2
// 14 variable data 2
// 15 check_checksum return address 2
// 16 variable check_checksum return value 2
// 17 calc_ack return address 2
// 18 variable calc_ack return value 2
// 19 array 2
// 20 array 2
// 21 variable length 2
// 22 variable new_ack_0 2
// 23 variable new_ack_1 2
// 24 variable return_value 2
// 25 put_ethernet_packet return address 2
// 26 array 2
// 27 variable number_of_bytes 2
// 28 variable destination_mac_address_hi 2
// 29 variable destination_mac_address_med 2
// 30 variable destination_mac_address_lo 2
// 31 variable protocol 2
// 32 variable byte 2
// 33 variable index 2
// 34 get_ethernet_packet return address 2
// 35 variable get_ethernet_packet return value 2
// 36 array 2
// 37 variable number_of_bytes 2
// 38 variable index 2
// 39 variable byte 2
// 40 array 2
// 41 array 2
// 42 array 2
// 43 array 2
// 44 array 2
// 45 variable arp_pounsigneder 2
// 46 get_arp_cache return address 2
// 47 variable get_arp_cache return value 2
// 48 variable ip_hi 2
// 49 variable ip_lo 2
// 50 variable number_of_bytes 2
// 51 variable byte 2
// 52 array 2
// 53 variable i 2
// 54 put_ip_packet return address 2
// 55 array 2
// 56 variable total_length 2
// 57 variable protocol 2
// 58 variable ip_hi 2
// 59 variable ip_lo 2
// 60 variable number_of_bytes 2
// 61 variable i 2
// 62 variable arp_cache 2
// 63 get_ip_packet return address 2
// 64 variable get_ip_packet return value 2
// 65 array 2
// 66 variable total_length 2
// 67 variable header_length 2
// 68 variable payload_start 2
// 69 variable payload_length 2
// 70 variable i 2
// 71 variable from 2
// 72 variable to 2
// 73 variable payload_end 2
// 74 variable number_of_bytes 2
// 75 variable remote_ip_hi 2
// 76 variable remote_ip_lo 2
// 77 variable tx_source 2
// 78 variable tx_dest 2
// 79 array 2
// 80 array 2
// 81 array 2
// 82 variable tx_window 2
// 83 variable tx_fin_flag 2
// 84 variable tx_syn_flag 2
// 85 variable tx_rst_flag 2
// 86 variable tx_psh_flag 2
// 87 variable tx_ack_flag 2
// 88 variable tx_urg_flag 2
// 89 variable rx_source 2
// 90 variable rx_dest 2
// 91 array 2
// 92 array 2
// 93 variable rx_fin_flag 2
// 94 variable rx_syn_flag 2
// 95 variable rx_rst_flag 2
// 96 variable rx_ack_flag 2
// 97 put_tcp_packet return address 2
// 98 array 2
// 99 variable tx_length 2
// 100 variable payload_start 2
// 101 variable packet_length 2
// 102 variable index 2
// 103 variable i 2
// 104 variable rx_length 2
// 105 variable rx_start 2
// 106 get_tcp_packet return address 2
// 107 variable get_tcp_packet return value 2
// 108 array 2
// 109 variable number_of_bytes 2
// 110 variable header_length 2
// 111 variable payload_start 2
// 112 variable total_length 2
// 113 variable payload_length 2
// 114 variable tcp_header_length 2
// 115 application_put_data return address 2
// 116 array 2
// 117 variable start 2
// 118 variable length 2
// 119 variable i 2
// 120 variable index 2
// 121 application_get_data return address 2
// 122 variable application_get_data return value 2
// 123 array 2
// 124 variable start 2
// 125 variable i 2
// 126 variable index 2
// 127 variable length 2
// 128 init_tx return address 2
// 129 variable i 2
// 130 server return address 2
// 131 array 2
// 132 array 2
// 133 variable tx_start 2
// 134 variable tx_length 2
// 135 variable timeout 2
// 136 variable resend_wait 2
// 137 variable bytes 2
// 138 variable last_state 2
// 139 variable new_rx_data 2
// 140 variable state 2
// 141 temporary_register 2
// 142 temporary_register 2
// 143 temporary_register 2
// 144 temporary_register 4
// 145 temporary_register 4
// 146 temporary_register 4
// 147 temporary_register 2
// 148 temporary_register 2
// 149 temporary_register 1024
// 150 temporary_register 2
// 151 temporary_register 2
// 152 temporary_register 2048
module server(input_eth_rx,input_socket,input_eth_rx_stb,input_socket_stb,output_socket_ack,output_eth_tx_ack,clk,rst,output_socket,output_eth_tx,output_socket_stb,output_eth_tx_stb,input_eth_rx_ack,input_socket_ack);
integer file_count;
real fp_value;
input [15:0] input_eth_rx;
input [15:0] input_socket;
input input_eth_rx_stb;
input input_socket_stb;
input output_socket_ack;
input output_eth_tx_ack;
input clk;
input rst;
output [15:0] output_socket;
output [15:0] output_eth_tx;
output output_socket_stb;
output output_eth_tx_stb;
output input_eth_rx_ack;
output input_socket_ack;
reg [15:0] timer;
reg timer_enable;
reg stage_0_enable;
reg stage_1_enable;
reg stage_2_enable;
reg [11:0] program_counter;
reg [11:0] program_counter_0;
reg [53:0] instruction_0;
reg [5:0] opcode_0;
reg [7:0] dest_0;
reg [7:0] src_0;
reg [7:0] srcb_0;
reg [31:0] literal_0;
reg [11:0] program_counter_1;
reg [5:0] opcode_1;
reg [7:0] dest_1;
reg [31:0] register_1;
reg [31:0] registerb_1;
reg [31:0] literal_1;
reg [7:0] dest_2;
reg [31:0] result_2;
reg write_enable_2;
reg [15:0] address_2;
reg [15:0] data_out_2;
reg [15:0] data_in_2;
reg memory_enable_2;
reg [15:0] address_4;
reg [31:0] data_out_4;
reg [31:0] data_in_4;
reg memory_enable_4;
reg [15:0] s_output_socket_stb;
reg [15:0] s_output_eth_tx_stb;
reg [15:0] s_output_socket;
reg [15:0] s_output_eth_tx;
reg [15:0] s_input_eth_rx_ack;
reg [15:0] s_input_socket_ack;
reg [15:0] memory_2 [2685:0];
reg [53:0] instructions [3381:0];
reg [31:0] registers [152:0];
//////////////////////////////////////////////////////////////////////////////
// INSTRUCTION INITIALIZATION
//
// Initialise the contents of the instruction memory
//
// Intruction Set
// ==============
// 0 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'literal'}
// 1 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'jmp_and_link'}
// 2 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'stop'}
// 3 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'move'}
// 4 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'nop'}
// 5 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'output': 'eth_tx', 'op': 'write'}
// 6 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'jmp_to_reg'}
// 7 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'output': 'socket', 'op': 'write'}
// 8 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'input': 'eth_rx', 'op': 'read'}
// 9 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'input': 'eth_rx', 'op': 'ready'}
// 10 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'input': 'socket', 'op': 'read'}
// 11 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '+'}
// 12 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '&'}
// 13 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'jmp_if_false'}
// 14 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '+'}
// 15 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'goto'}
// 16 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': '~'}
// 17 {'right': False, 'element_size': 2, 'float': False, 'unsigned': False, 'literal': False, 'op': 'memory_read_request'}
// 18 {'right': False, 'element_size': 2, 'float': False, 'unsigned': False, 'literal': False, 'op': 'memory_read_wait'}
// 19 {'right': False, 'element_size': 2, 'float': False, 'unsigned': False, 'literal': False, 'op': 'memory_read'}
// 20 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '<'}
// 21 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '!='}
// 22 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'jmp_if_true'}
// 23 {'right': False, 'element_size': 2, 'float': False, 'unsigned': False, 'literal': False, 'op': 'memory_write'}
// 24 {'right': False, 'float': False, 'unsigned': True, 'literal': False, 'file': '/net/sendai/data3/Coding/ba/Chips-Demo/source/server.h', 'line': 107, 'op': 'report'}
// 25 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '=='}
// 26 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '!='}
// 27 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': '+'}
// 28 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '<'}
// 29 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '=='}
// 30 {'float': False, 'literal': True, 'right': False, 'unsigned': True, 'op': '|'}
// 31 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '<='}
// 32 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '>>'}
// 33 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '<<'}
// 34 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '-'}
// 35 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '-'}
// 36 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '<='}
// 37 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '|'}
// 38 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'input': 'socket', 'op': 'ready'}
// 39 {'float': False, 'literal': True, 'right': True, 'unsigned': False, 'op': '=='}
// 40 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'wait_clocks'}
// Intructions
// ===========
initial
begin
instructions[0] = {6'd0, 8'd10, 8'd0, 32'd0};//{'dest': 10, 'literal': 0, 'op': 'literal'}
instructions[1] = {6'd0, 8'd11, 8'd0, 32'd0};//{'dest': 11, 'literal': 0, 'size': 4, 'signed': 4, 'op': 'literal'}
instructions[2] = {6'd0, 8'd40, 8'd0, 32'd520};//{'dest': 40, 'literal': 520, 'op': 'literal'}
instructions[3] = {6'd0, 8'd41, 8'd0, 32'd536};//{'dest': 41, 'literal': 536, 'op': 'literal'}
instructions[4] = {6'd0, 8'd42, 8'd0, 32'd552};//{'dest': 42, 'literal': 552, 'op': 'literal'}
instructions[5] = {6'd0, 8'd43, 8'd0, 32'd568};//{'dest': 43, 'literal': 568, 'op': 'literal'}
instructions[6] = {6'd0, 8'd44, 8'd0, 32'd584};//{'dest': 44, 'literal': 584, 'op': 'literal'}
instructions[7] = {6'd0, 8'd45, 8'd0, 32'd0};//{'dest': 45, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[8] = {6'd0, 8'd75, 8'd0, 32'd0};//{'dest': 75, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[9] = {6'd0, 8'd76, 8'd0, 32'd0};//{'dest': 76, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[10] = {6'd0, 8'd77, 8'd0, 32'd0};//{'dest': 77, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[11] = {6'd0, 8'd78, 8'd0, 32'd0};//{'dest': 78, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[12] = {6'd0, 8'd79, 8'd0, 32'd620};//{'dest': 79, 'literal': 620, 'op': 'literal'}
instructions[13] = {6'd0, 8'd80, 8'd0, 32'd622};//{'dest': 80, 'literal': 622, 'op': 'literal'}
instructions[14] = {6'd0, 8'd81, 8'd0, 32'd624};//{'dest': 81, 'literal': 624, 'op': 'literal'}
instructions[15] = {6'd0, 8'd82, 8'd0, 32'd1460};//{'dest': 82, 'literal': 1460, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[16] = {6'd0, 8'd83, 8'd0, 32'd0};//{'dest': 83, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[17] = {6'd0, 8'd84, 8'd0, 32'd0};//{'dest': 84, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[18] = {6'd0, 8'd85, 8'd0, 32'd0};//{'dest': 85, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[19] = {6'd0, 8'd86, 8'd0, 32'd0};//{'dest': 86, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[20] = {6'd0, 8'd87, 8'd0, 32'd0};//{'dest': 87, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[21] = {6'd0, 8'd88, 8'd0, 32'd0};//{'dest': 88, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[22] = {6'd0, 8'd89, 8'd0, 32'd0};//{'dest': 89, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[23] = {6'd0, 8'd90, 8'd0, 32'd0};//{'dest': 90, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[24] = {6'd0, 8'd91, 8'd0, 32'd626};//{'dest': 91, 'literal': 626, 'op': 'literal'}
instructions[25] = {6'd0, 8'd92, 8'd0, 32'd628};//{'dest': 92, 'literal': 628, 'op': 'literal'}
instructions[26] = {6'd0, 8'd93, 8'd0, 32'd0};//{'dest': 93, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[27] = {6'd0, 8'd94, 8'd0, 32'd0};//{'dest': 94, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[28] = {6'd0, 8'd95, 8'd0, 32'd0};//{'dest': 95, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[29] = {6'd0, 8'd96, 8'd0, 32'd0};//{'dest': 96, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[30] = {6'd0, 8'd104, 8'd0, 32'd0};//{'dest': 104, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[31] = {6'd0, 8'd105, 8'd0, 32'd0};//{'dest': 105, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[32] = {6'd1, 8'd130, 8'd0, 32'd2653};//{'dest': 130, 'label': 2653, 'op': 'jmp_and_link'}
instructions[33] = {6'd2, 8'd0, 8'd0, 32'd0};//{'op': 'stop'}
instructions[34] = {6'd3, 8'd141, 8'd1, 32'd0};//{'dest': 141, 'src': 1, 'op': 'move'}
instructions[35] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[36] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[37] = {6'd5, 8'd0, 8'd141, 32'd0};//{'src': 141, 'output': 'eth_tx', 'op': 'write'}
instructions[38] = {6'd6, 8'd0, 8'd0, 32'd0};//{'src': 0, 'op': 'jmp_to_reg'}
instructions[39] = {6'd3, 8'd141, 8'd3, 32'd0};//{'dest': 141, 'src': 3, 'op': 'move'}
instructions[40] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[41] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[42] = {6'd7, 8'd0, 8'd141, 32'd0};//{'src': 141, 'output': 'socket', 'op': 'write'}
instructions[43] = {6'd6, 8'd0, 8'd2, 32'd0};//{'src': 2, 'op': 'jmp_to_reg'}
instructions[44] = {6'd8, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'input': 'eth_rx', 'op': 'read'}
instructions[45] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[46] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[47] = {6'd3, 8'd5, 8'd141, 32'd0};//{'dest': 5, 'src': 141, 'op': 'move'}
instructions[48] = {6'd6, 8'd0, 8'd4, 32'd0};//{'src': 4, 'op': 'jmp_to_reg'}
instructions[49] = {6'd9, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'input': 'eth_rx', 'op': 'ready'}
instructions[50] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[51] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[52] = {6'd3, 8'd7, 8'd141, 32'd0};//{'dest': 7, 'src': 141, 'op': 'move'}
instructions[53] = {6'd6, 8'd0, 8'd6, 32'd0};//{'src': 6, 'op': 'jmp_to_reg'}
instructions[54] = {6'd10, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'input': 'socket', 'op': 'read'}
instructions[55] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[56] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[57] = {6'd3, 8'd9, 8'd141, 32'd0};//{'dest': 9, 'src': 141, 'op': 'move'}
instructions[58] = {6'd6, 8'd0, 8'd8, 32'd0};//{'src': 8, 'op': 'jmp_to_reg'}
instructions[59] = {6'd0, 8'd144, 8'd0, 32'd0};//{'dest': 144, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[60] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[61] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[62] = {6'd3, 8'd11, 8'd144, 32'd0};//{'dest': 11, 'src': 144, 'op': 'move'}
instructions[63] = {6'd6, 8'd0, 8'd12, 32'd0};//{'src': 12, 'op': 'jmp_to_reg'}
instructions[64] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[65] = {6'd3, 8'd145, 8'd11, 32'd0};//{'dest': 145, 'src': 11, 'op': 'move'}
instructions[66] = {6'd3, 8'd146, 8'd14, 32'd0};//{'dest': 146, 'src': 14, 'op': 'move'}
instructions[67] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[68] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[69] = {6'd11, 8'd144, 8'd145, 32'd146};//{'srcb': 146, 'src': 145, 'dest': 144, 'signed': False, 'op': '+', 'type': 'int', 'size': 4}
instructions[70] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[71] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[72] = {6'd3, 8'd11, 8'd144, 32'd0};//{'dest': 11, 'src': 144, 'op': 'move'}
instructions[73] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[74] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[75] = {6'd3, 8'd145, 8'd11, 32'd0};//{'dest': 145, 'src': 11, 'op': 'move'}
instructions[76] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[77] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[78] = {6'd12, 8'd144, 8'd145, 32'd65536};//{'src': 145, 'right': 65536, 'dest': 144, 'signed': False, 'op': '&', 'type': 'int', 'size': 4}
instructions[79] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[80] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[81] = {6'd13, 8'd0, 8'd144, 32'd99};//{'src': 144, 'label': 99, 'op': 'jmp_if_false'}
instructions[82] = {6'd3, 8'd145, 8'd11, 32'd0};//{'dest': 145, 'src': 11, 'op': 'move'}
instructions[83] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[84] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[85] = {6'd12, 8'd144, 8'd145, 32'd65535};//{'src': 145, 'right': 65535, 'dest': 144, 'signed': False, 'op': '&', 'type': 'int', 'size': 4}
instructions[86] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[87] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[88] = {6'd3, 8'd11, 8'd144, 32'd0};//{'dest': 11, 'src': 144, 'op': 'move'}
instructions[89] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[90] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[91] = {6'd3, 8'd145, 8'd11, 32'd0};//{'dest': 145, 'src': 11, 'op': 'move'}
instructions[92] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[93] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[94] = {6'd14, 8'd144, 8'd145, 32'd1};//{'src': 145, 'right': 1, 'dest': 144, 'signed': False, 'op': '+', 'type': 'int', 'size': 4}
instructions[95] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[96] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[97] = {6'd3, 8'd11, 8'd144, 32'd0};//{'dest': 11, 'src': 144, 'op': 'move'}
instructions[98] = {6'd15, 8'd0, 8'd0, 32'd99};//{'label': 99, 'op': 'goto'}
instructions[99] = {6'd6, 8'd0, 8'd13, 32'd0};//{'src': 13, 'op': 'jmp_to_reg'}
instructions[100] = {6'd3, 8'd144, 8'd11, 32'd0};//{'dest': 144, 'src': 11, 'op': 'move'}
instructions[101] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[102] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[103] = {6'd16, 8'd141, 8'd144, 32'd0};//{'dest': 141, 'src': 144, 'op': '~'}
instructions[104] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[105] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[106] = {6'd3, 8'd16, 8'd141, 32'd0};//{'dest': 16, 'src': 141, 'op': 'move'}
instructions[107] = {6'd6, 8'd0, 8'd15, 32'd0};//{'src': 15, 'op': 'jmp_to_reg'}
instructions[108] = {6'd0, 8'd22, 8'd0, 32'd0};//{'dest': 22, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[109] = {6'd0, 8'd23, 8'd0, 32'd0};//{'dest': 23, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[110] = {6'd0, 8'd24, 8'd0, 32'd0};//{'dest': 24, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[111] = {6'd0, 8'd143, 8'd0, 32'd0};//{'dest': 143, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[112] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[113] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[114] = {6'd11, 8'd147, 8'd143, 32'd20};//{'dest': 147, 'src': 143, 'srcb': 20, 'signed': False, 'op': '+'}
instructions[115] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[116] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[117] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152843188920, 'op': 'memory_read_request'}
instructions[118] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[119] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152843188920, 'op': 'memory_read_wait'}
instructions[120] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152843188920, 'element_size': 2, 'op': 'memory_read'}
instructions[121] = {6'd3, 8'd143, 8'd21, 32'd0};//{'dest': 143, 'src': 21, 'op': 'move'}
instructions[122] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[123] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[124] = {6'd11, 8'd141, 8'd142, 32'd143};//{'srcb': 143, 'src': 142, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[125] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[126] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[127] = {6'd3, 8'd22, 8'd141, 32'd0};//{'dest': 22, 'src': 141, 'op': 'move'}
instructions[128] = {6'd0, 8'd142, 8'd0, 32'd1};//{'dest': 142, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[129] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[130] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[131] = {6'd11, 8'd143, 8'd142, 32'd20};//{'dest': 143, 'src': 142, 'srcb': 20, 'signed': False, 'op': '+'}
instructions[132] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[133] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[134] = {6'd17, 8'd0, 8'd143, 32'd0};//{'element_size': 2, 'src': 143, 'sequence': 140152843189424, 'op': 'memory_read_request'}
instructions[135] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[136] = {6'd18, 8'd0, 8'd143, 32'd0};//{'element_size': 2, 'src': 143, 'sequence': 140152843189424, 'op': 'memory_read_wait'}
instructions[137] = {6'd19, 8'd141, 8'd143, 32'd0};//{'dest': 141, 'src': 143, 'sequence': 140152843189424, 'element_size': 2, 'op': 'memory_read'}
instructions[138] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[139] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[140] = {6'd3, 8'd23, 8'd141, 32'd0};//{'dest': 23, 'src': 141, 'op': 'move'}
instructions[141] = {6'd3, 8'd142, 8'd22, 32'd0};//{'dest': 142, 'src': 22, 'op': 'move'}
instructions[142] = {6'd3, 8'd143, 8'd21, 32'd0};//{'dest': 143, 'src': 21, 'op': 'move'}
instructions[143] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[144] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[145] = {6'd20, 8'd141, 8'd142, 32'd143};//{'srcb': 143, 'src': 142, 'dest': 141, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[146] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[147] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[148] = {6'd13, 8'd0, 8'd141, 32'd157};//{'src': 141, 'label': 157, 'op': 'jmp_if_false'}
instructions[149] = {6'd3, 8'd142, 8'd23, 32'd0};//{'dest': 142, 'src': 23, 'op': 'move'}
instructions[150] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[151] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[152] = {6'd14, 8'd141, 8'd142, 32'd1};//{'src': 142, 'right': 1, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[153] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[154] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[155] = {6'd3, 8'd23, 8'd141, 32'd0};//{'dest': 23, 'src': 141, 'op': 'move'}
instructions[156] = {6'd15, 8'd0, 8'd0, 32'd157};//{'label': 157, 'op': 'goto'}
instructions[157] = {6'd3, 8'd142, 8'd22, 32'd0};//{'dest': 142, 'src': 22, 'op': 'move'}
instructions[158] = {6'd0, 8'd147, 8'd0, 32'd0};//{'dest': 147, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[159] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[160] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[161] = {6'd11, 8'd148, 8'd147, 32'd19};//{'dest': 148, 'src': 147, 'srcb': 19, 'signed': False, 'op': '+'}
instructions[162] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[163] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[164] = {6'd17, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152843219456, 'op': 'memory_read_request'}
instructions[165] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[166] = {6'd18, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152843219456, 'op': 'memory_read_wait'}
instructions[167] = {6'd19, 8'd143, 8'd148, 32'd0};//{'dest': 143, 'src': 148, 'sequence': 140152843219456, 'element_size': 2, 'op': 'memory_read'}
instructions[168] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[169] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[170] = {6'd21, 8'd141, 8'd142, 32'd143};//{'srcb': 143, 'src': 142, 'dest': 141, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[171] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[172] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[173] = {6'd22, 8'd0, 8'd141, 32'd188};//{'src': 141, 'label': 188, 'op': 'jmp_if_true'}
instructions[174] = {6'd3, 8'd142, 8'd23, 32'd0};//{'dest': 142, 'src': 23, 'op': 'move'}
instructions[175] = {6'd0, 8'd147, 8'd0, 32'd1};//{'dest': 147, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[176] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[177] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[178] = {6'd11, 8'd148, 8'd147, 32'd19};//{'dest': 148, 'src': 147, 'srcb': 19, 'signed': False, 'op': '+'}
instructions[179] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[180] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[181] = {6'd17, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152843219744, 'op': 'memory_read_request'}
instructions[182] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[183] = {6'd18, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152843219744, 'op': 'memory_read_wait'}
instructions[184] = {6'd19, 8'd143, 8'd148, 32'd0};//{'dest': 143, 'src': 148, 'sequence': 140152843219744, 'element_size': 2, 'op': 'memory_read'}
instructions[185] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[186] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[187] = {6'd21, 8'd141, 8'd142, 32'd143};//{'srcb': 143, 'src': 142, 'dest': 141, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[188] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[189] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[190] = {6'd13, 8'd0, 8'd141, 32'd212};//{'src': 141, 'label': 212, 'op': 'jmp_if_false'}
instructions[191] = {6'd3, 8'd141, 8'd22, 32'd0};//{'dest': 141, 'src': 22, 'op': 'move'}
instructions[192] = {6'd0, 8'd142, 8'd0, 32'd0};//{'dest': 142, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[193] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[194] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[195] = {6'd11, 8'd143, 8'd142, 32'd19};//{'dest': 143, 'src': 142, 'srcb': 19, 'signed': False, 'op': '+'}
instructions[196] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[197] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[198] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[199] = {6'd3, 8'd141, 8'd23, 32'd0};//{'dest': 141, 'src': 23, 'op': 'move'}
instructions[200] = {6'd0, 8'd142, 8'd0, 32'd1};//{'dest': 142, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[201] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[202] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[203] = {6'd11, 8'd143, 8'd142, 32'd19};//{'dest': 143, 'src': 142, 'srcb': 19, 'signed': False, 'op': '+'}
instructions[204] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[205] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[206] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[207] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[208] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[209] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[210] = {6'd3, 8'd24, 8'd141, 32'd0};//{'dest': 24, 'src': 141, 'op': 'move'}
instructions[211] = {6'd15, 8'd0, 8'd0, 32'd212};//{'label': 212, 'op': 'goto'}
instructions[212] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[213] = {6'd3, 8'd141, 8'd24, 32'd0};//{'dest': 141, 'src': 24, 'op': 'move'}
instructions[214] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[215] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[216] = {6'd3, 8'd18, 8'd141, 32'd0};//{'dest': 18, 'src': 141, 'op': 'move'}
instructions[217] = {6'd6, 8'd0, 8'd17, 32'd0};//{'src': 17, 'op': 'jmp_to_reg'}
instructions[218] = {6'd0, 8'd32, 8'd0, 32'd0};//{'dest': 32, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[219] = {6'd0, 8'd33, 8'd0, 32'd0};//{'dest': 33, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[220] = {6'd3, 8'd141, 8'd27, 32'd0};//{'dest': 141, 'src': 27, 'op': 'move'}
instructions[221] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[222] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[223] = {6'd24, 8'd0, 8'd141, 32'd0};//{'src': 141, 'signed': False, 'file': '/net/sendai/data3/Coding/ba/Chips-Demo/source/server.h', 'line': 107, 'type': 'int', 'op': 'report'}
instructions[224] = {6'd3, 8'd141, 8'd28, 32'd0};//{'dest': 141, 'src': 28, 'op': 'move'}
instructions[225] = {6'd0, 8'd142, 8'd0, 32'd0};//{'dest': 142, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[226] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[227] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[228] = {6'd11, 8'd143, 8'd142, 32'd26};//{'dest': 143, 'src': 142, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[229] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[230] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[231] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[232] = {6'd3, 8'd141, 8'd29, 32'd0};//{'dest': 141, 'src': 29, 'op': 'move'}
instructions[233] = {6'd0, 8'd142, 8'd0, 32'd1};//{'dest': 142, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[234] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[235] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[236] = {6'd11, 8'd143, 8'd142, 32'd26};//{'dest': 143, 'src': 142, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[237] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[238] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[239] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[240] = {6'd3, 8'd141, 8'd30, 32'd0};//{'dest': 141, 'src': 30, 'op': 'move'}
instructions[241] = {6'd0, 8'd142, 8'd0, 32'd2};//{'dest': 142, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[242] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[243] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[244] = {6'd11, 8'd143, 8'd142, 32'd26};//{'dest': 143, 'src': 142, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[245] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[246] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[247] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[248] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[249] = {6'd0, 8'd142, 8'd0, 32'd3};//{'dest': 142, 'literal': 3, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[250] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[251] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[252] = {6'd11, 8'd143, 8'd142, 32'd26};//{'dest': 143, 'src': 142, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[253] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[254] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[255] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[256] = {6'd0, 8'd141, 8'd0, 32'd515};//{'dest': 141, 'literal': 515, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[257] = {6'd0, 8'd142, 8'd0, 32'd4};//{'dest': 142, 'literal': 4, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[258] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[259] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[260] = {6'd11, 8'd143, 8'd142, 32'd26};//{'dest': 143, 'src': 142, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[261] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[262] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[263] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[264] = {6'd0, 8'd141, 8'd0, 32'd1029};//{'dest': 141, 'literal': 1029, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[265] = {6'd0, 8'd142, 8'd0, 32'd5};//{'dest': 142, 'literal': 5, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[266] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[267] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[268] = {6'd11, 8'd143, 8'd142, 32'd26};//{'dest': 143, 'src': 142, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[269] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[270] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[271] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[272] = {6'd3, 8'd141, 8'd31, 32'd0};//{'dest': 141, 'src': 31, 'op': 'move'}
instructions[273] = {6'd0, 8'd142, 8'd0, 32'd6};//{'dest': 142, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[274] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[275] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[276] = {6'd11, 8'd143, 8'd142, 32'd26};//{'dest': 143, 'src': 142, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[277] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[278] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[279] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[280] = {6'd3, 8'd142, 8'd27, 32'd0};//{'dest': 142, 'src': 27, 'op': 'move'}
instructions[281] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[282] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[283] = {6'd3, 8'd1, 8'd142, 32'd0};//{'dest': 1, 'src': 142, 'op': 'move'}
instructions[284] = {6'd1, 8'd0, 8'd0, 32'd34};//{'dest': 0, 'label': 34, 'op': 'jmp_and_link'}
instructions[285] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[286] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[287] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[288] = {6'd3, 8'd33, 8'd141, 32'd0};//{'dest': 33, 'src': 141, 'op': 'move'}
instructions[289] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[290] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[291] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[292] = {6'd3, 8'd32, 8'd141, 32'd0};//{'dest': 32, 'src': 141, 'op': 'move'}
instructions[293] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[294] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[295] = {6'd3, 8'd142, 8'd32, 32'd0};//{'dest': 142, 'src': 32, 'op': 'move'}
instructions[296] = {6'd3, 8'd143, 8'd27, 32'd0};//{'dest': 143, 'src': 27, 'op': 'move'}
instructions[297] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[298] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[299] = {6'd20, 8'd141, 8'd142, 32'd143};//{'srcb': 143, 'src': 142, 'dest': 141, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[300] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[301] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[302] = {6'd13, 8'd0, 8'd141, 32'd327};//{'src': 141, 'label': 327, 'op': 'jmp_if_false'}
instructions[303] = {6'd3, 8'd143, 8'd33, 32'd0};//{'dest': 143, 'src': 33, 'op': 'move'}
instructions[304] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[305] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[306] = {6'd11, 8'd147, 8'd143, 32'd26};//{'dest': 147, 'src': 143, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[307] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[308] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[309] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842731744, 'op': 'memory_read_request'}
instructions[310] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[311] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842731744, 'op': 'memory_read_wait'}
instructions[312] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152842731744, 'element_size': 2, 'op': 'memory_read'}
instructions[313] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[314] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[315] = {6'd3, 8'd1, 8'd142, 32'd0};//{'dest': 1, 'src': 142, 'op': 'move'}
instructions[316] = {6'd1, 8'd0, 8'd0, 32'd34};//{'dest': 0, 'label': 34, 'op': 'jmp_and_link'}
instructions[317] = {6'd3, 8'd141, 8'd33, 32'd0};//{'dest': 141, 'src': 33, 'op': 'move'}
instructions[318] = {6'd14, 8'd33, 8'd33, 32'd1};//{'src': 33, 'right': 1, 'dest': 33, 'signed': False, 'op': '+', 'size': 2}
instructions[319] = {6'd3, 8'd142, 8'd32, 32'd0};//{'dest': 142, 'src': 32, 'op': 'move'}
instructions[320] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[321] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[322] = {6'd14, 8'd141, 8'd142, 32'd2};//{'src': 142, 'right': 2, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[323] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[324] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[325] = {6'd3, 8'd32, 8'd141, 32'd0};//{'dest': 32, 'src': 141, 'op': 'move'}
instructions[326] = {6'd15, 8'd0, 8'd0, 32'd293};//{'label': 293, 'op': 'goto'}
instructions[327] = {6'd6, 8'd0, 8'd25, 32'd0};//{'src': 25, 'op': 'jmp_to_reg'}
instructions[328] = {6'd0, 8'd37, 8'd0, 32'd0};//{'dest': 37, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[329] = {6'd0, 8'd38, 8'd0, 32'd0};//{'dest': 38, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[330] = {6'd0, 8'd39, 8'd0, 32'd0};//{'dest': 39, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[331] = {6'd1, 8'd6, 8'd0, 32'd49};//{'dest': 6, 'label': 49, 'op': 'jmp_and_link'}
instructions[332] = {6'd3, 8'd142, 8'd7, 32'd0};//{'dest': 142, 'src': 7, 'op': 'move'}
instructions[333] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[334] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[335] = {6'd25, 8'd141, 8'd142, 32'd0};//{'src': 142, 'right': 0, 'dest': 141, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[336] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[337] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[338] = {6'd13, 8'd0, 8'd141, 32'd345};//{'src': 141, 'label': 345, 'op': 'jmp_if_false'}
instructions[339] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[340] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[341] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[342] = {6'd3, 8'd35, 8'd141, 32'd0};//{'dest': 35, 'src': 141, 'op': 'move'}
instructions[343] = {6'd6, 8'd0, 8'd34, 32'd0};//{'src': 34, 'op': 'jmp_to_reg'}
instructions[344] = {6'd15, 8'd0, 8'd0, 32'd345};//{'label': 345, 'op': 'goto'}
instructions[345] = {6'd1, 8'd4, 8'd0, 32'd44};//{'dest': 4, 'label': 44, 'op': 'jmp_and_link'}
instructions[346] = {6'd3, 8'd141, 8'd5, 32'd0};//{'dest': 141, 'src': 5, 'op': 'move'}
instructions[347] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[348] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[349] = {6'd3, 8'd37, 8'd141, 32'd0};//{'dest': 37, 'src': 141, 'op': 'move'}
instructions[350] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[351] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[352] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[353] = {6'd3, 8'd38, 8'd141, 32'd0};//{'dest': 38, 'src': 141, 'op': 'move'}
instructions[354] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[355] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[356] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[357] = {6'd3, 8'd39, 8'd141, 32'd0};//{'dest': 39, 'src': 141, 'op': 'move'}
instructions[358] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[359] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[360] = {6'd3, 8'd142, 8'd39, 32'd0};//{'dest': 142, 'src': 39, 'op': 'move'}
instructions[361] = {6'd3, 8'd143, 8'd37, 32'd0};//{'dest': 143, 'src': 37, 'op': 'move'}
instructions[362] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[363] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[364] = {6'd20, 8'd141, 8'd142, 32'd143};//{'srcb': 143, 'src': 142, 'dest': 141, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[365] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[366] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[367] = {6'd13, 8'd0, 8'd141, 32'd387};//{'src': 141, 'label': 387, 'op': 'jmp_if_false'}
instructions[368] = {6'd1, 8'd4, 8'd0, 32'd44};//{'dest': 4, 'label': 44, 'op': 'jmp_and_link'}
instructions[369] = {6'd3, 8'd141, 8'd5, 32'd0};//{'dest': 141, 'src': 5, 'op': 'move'}
instructions[370] = {6'd3, 8'd142, 8'd38, 32'd0};//{'dest': 142, 'src': 38, 'op': 'move'}
instructions[371] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[372] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[373] = {6'd11, 8'd143, 8'd142, 32'd36};//{'dest': 143, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[374] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[375] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[376] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[377] = {6'd3, 8'd141, 8'd38, 32'd0};//{'dest': 141, 'src': 38, 'op': 'move'}
instructions[378] = {6'd14, 8'd38, 8'd38, 32'd1};//{'src': 38, 'right': 1, 'dest': 38, 'signed': False, 'op': '+', 'size': 2}
instructions[379] = {6'd3, 8'd142, 8'd39, 32'd0};//{'dest': 142, 'src': 39, 'op': 'move'}
instructions[380] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[381] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[382] = {6'd14, 8'd141, 8'd142, 32'd2};//{'src': 142, 'right': 2, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[383] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[384] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[385] = {6'd3, 8'd39, 8'd141, 32'd0};//{'dest': 39, 'src': 141, 'op': 'move'}
instructions[386] = {6'd15, 8'd0, 8'd0, 32'd358};//{'label': 358, 'op': 'goto'}
instructions[387] = {6'd0, 8'd143, 8'd0, 32'd0};//{'dest': 143, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[388] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[389] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[390] = {6'd11, 8'd147, 8'd143, 32'd36};//{'dest': 147, 'src': 143, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[391] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[392] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[393] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842732752, 'op': 'memory_read_request'}
instructions[394] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[395] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842732752, 'op': 'memory_read_wait'}
instructions[396] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152842732752, 'element_size': 2, 'op': 'memory_read'}
instructions[397] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[398] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[399] = {6'd26, 8'd141, 8'd142, 32'd1};//{'src': 142, 'right': 1, 'dest': 141, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[400] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[401] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[402] = {6'd13, 8'd0, 8'd141, 32'd416};//{'src': 141, 'label': 416, 'op': 'jmp_if_false'}
instructions[403] = {6'd0, 8'd143, 8'd0, 32'd0};//{'dest': 143, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[404] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[405] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[406] = {6'd11, 8'd147, 8'd143, 32'd36};//{'dest': 147, 'src': 143, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[407] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[408] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[409] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842733040, 'op': 'memory_read_request'}
instructions[410] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[411] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842733040, 'op': 'memory_read_wait'}
instructions[412] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152842733040, 'element_size': 2, 'op': 'memory_read'}
instructions[413] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[414] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[415] = {6'd26, 8'd141, 8'd142, 32'd65535};//{'src': 142, 'right': 65535, 'dest': 141, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[416] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[417] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[418] = {6'd13, 8'd0, 8'd141, 32'd425};//{'src': 141, 'label': 425, 'op': 'jmp_if_false'}
instructions[419] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[420] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[421] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[422] = {6'd3, 8'd35, 8'd141, 32'd0};//{'dest': 35, 'src': 141, 'op': 'move'}
instructions[423] = {6'd6, 8'd0, 8'd34, 32'd0};//{'src': 34, 'op': 'jmp_to_reg'}
instructions[424] = {6'd15, 8'd0, 8'd0, 32'd425};//{'label': 425, 'op': 'goto'}
instructions[425] = {6'd0, 8'd143, 8'd0, 32'd1};//{'dest': 143, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[426] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[427] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[428] = {6'd11, 8'd147, 8'd143, 32'd36};//{'dest': 147, 'src': 143, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[429] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[430] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[431] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842733616, 'op': 'memory_read_request'}
instructions[432] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[433] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842733616, 'op': 'memory_read_wait'}
instructions[434] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152842733616, 'element_size': 2, 'op': 'memory_read'}
instructions[435] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[436] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[437] = {6'd26, 8'd141, 8'd142, 32'd515};//{'src': 142, 'right': 515, 'dest': 141, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[438] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[439] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[440] = {6'd13, 8'd0, 8'd141, 32'd454};//{'src': 141, 'label': 454, 'op': 'jmp_if_false'}
instructions[441] = {6'd0, 8'd143, 8'd0, 32'd1};//{'dest': 143, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[442] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[443] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[444] = {6'd11, 8'd147, 8'd143, 32'd36};//{'dest': 147, 'src': 143, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[445] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[446] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[447] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842733904, 'op': 'memory_read_request'}
instructions[448] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[449] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842733904, 'op': 'memory_read_wait'}
instructions[450] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152842733904, 'element_size': 2, 'op': 'memory_read'}
instructions[451] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[452] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[453] = {6'd26, 8'd141, 8'd142, 32'd65535};//{'src': 142, 'right': 65535, 'dest': 141, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[454] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[455] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[456] = {6'd13, 8'd0, 8'd141, 32'd463};//{'src': 141, 'label': 463, 'op': 'jmp_if_false'}
instructions[457] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[458] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[459] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[460] = {6'd3, 8'd35, 8'd141, 32'd0};//{'dest': 35, 'src': 141, 'op': 'move'}
instructions[461] = {6'd6, 8'd0, 8'd34, 32'd0};//{'src': 34, 'op': 'jmp_to_reg'}
instructions[462] = {6'd15, 8'd0, 8'd0, 32'd463};//{'label': 463, 'op': 'goto'}
instructions[463] = {6'd0, 8'd143, 8'd0, 32'd2};//{'dest': 143, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[464] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[465] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[466] = {6'd11, 8'd147, 8'd143, 32'd36};//{'dest': 147, 'src': 143, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[467] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[468] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[469] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842734480, 'op': 'memory_read_request'}
instructions[470] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[471] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842734480, 'op': 'memory_read_wait'}
instructions[472] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152842734480, 'element_size': 2, 'op': 'memory_read'}
instructions[473] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[474] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[475] = {6'd26, 8'd141, 8'd142, 32'd1029};//{'src': 142, 'right': 1029, 'dest': 141, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[476] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[477] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[478] = {6'd13, 8'd0, 8'd141, 32'd492};//{'src': 141, 'label': 492, 'op': 'jmp_if_false'}
instructions[479] = {6'd0, 8'd143, 8'd0, 32'd2};//{'dest': 143, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[480] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[481] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[482] = {6'd11, 8'd147, 8'd143, 32'd36};//{'dest': 147, 'src': 143, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[483] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[484] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[485] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842734768, 'op': 'memory_read_request'}
instructions[486] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[487] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842734768, 'op': 'memory_read_wait'}
instructions[488] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152842734768, 'element_size': 2, 'op': 'memory_read'}
instructions[489] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[490] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[491] = {6'd26, 8'd141, 8'd142, 32'd65535};//{'src': 142, 'right': 65535, 'dest': 141, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[492] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[493] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[494] = {6'd13, 8'd0, 8'd141, 32'd501};//{'src': 141, 'label': 501, 'op': 'jmp_if_false'}
instructions[495] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[496] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[497] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[498] = {6'd3, 8'd35, 8'd141, 32'd0};//{'dest': 35, 'src': 141, 'op': 'move'}
instructions[499] = {6'd6, 8'd0, 8'd34, 32'd0};//{'src': 34, 'op': 'jmp_to_reg'}
instructions[500] = {6'd15, 8'd0, 8'd0, 32'd501};//{'label': 501, 'op': 'goto'}
instructions[501] = {6'd0, 8'd143, 8'd0, 32'd6};//{'dest': 143, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[502] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[503] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[504] = {6'd11, 8'd147, 8'd143, 32'd36};//{'dest': 147, 'src': 143, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[505] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[506] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[507] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842735344, 'op': 'memory_read_request'}
instructions[508] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[509] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842735344, 'op': 'memory_read_wait'}
instructions[510] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152842735344, 'element_size': 2, 'op': 'memory_read'}
instructions[511] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[512] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[513] = {6'd25, 8'd141, 8'd142, 32'd2054};//{'src': 142, 'right': 2054, 'dest': 141, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[514] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[515] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[516] = {6'd13, 8'd0, 8'd141, 32'd749};//{'src': 141, 'label': 749, 'op': 'jmp_if_false'}
instructions[517] = {6'd0, 8'd143, 8'd0, 32'd10};//{'dest': 143, 'literal': 10, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[518] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[519] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[520] = {6'd11, 8'd147, 8'd143, 32'd36};//{'dest': 147, 'src': 143, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[521] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[522] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[523] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842748200, 'op': 'memory_read_request'}
instructions[524] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[525] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842748200, 'op': 'memory_read_wait'}
instructions[526] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152842748200, 'element_size': 2, 'op': 'memory_read'}
instructions[527] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[528] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[529] = {6'd25, 8'd141, 8'd142, 32'd1};//{'src': 142, 'right': 1, 'dest': 141, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[530] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[531] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[532] = {6'd13, 8'd0, 8'd141, 32'd743};//{'src': 141, 'label': 743, 'op': 'jmp_if_false'}
instructions[533] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[534] = {6'd0, 8'd142, 8'd0, 32'd7};//{'dest': 142, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[535] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[536] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[537] = {6'd27, 8'd143, 8'd142, 32'd10};//{'dest': 143, 'src': 142, 'srcb': 10, 'signed': True, 'op': '+'}
instructions[538] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[539] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[540] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[541] = {6'd0, 8'd141, 8'd0, 32'd2048};//{'dest': 141, 'literal': 2048, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[542] = {6'd0, 8'd142, 8'd0, 32'd8};//{'dest': 142, 'literal': 8, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[543] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[544] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[545] = {6'd27, 8'd143, 8'd142, 32'd10};//{'dest': 143, 'src': 142, 'srcb': 10, 'signed': True, 'op': '+'}
instructions[546] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[547] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[548] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[549] = {6'd0, 8'd141, 8'd0, 32'd1540};//{'dest': 141, 'literal': 1540, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[550] = {6'd0, 8'd142, 8'd0, 32'd9};//{'dest': 142, 'literal': 9, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[551] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[552] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[553] = {6'd27, 8'd143, 8'd142, 32'd10};//{'dest': 143, 'src': 142, 'srcb': 10, 'signed': True, 'op': '+'}
instructions[554] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[555] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[556] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[557] = {6'd0, 8'd141, 8'd0, 32'd2};//{'dest': 141, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[558] = {6'd0, 8'd142, 8'd0, 32'd10};//{'dest': 142, 'literal': 10, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[559] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[560] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[561] = {6'd27, 8'd143, 8'd142, 32'd10};//{'dest': 143, 'src': 142, 'srcb': 10, 'signed': True, 'op': '+'}
instructions[562] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[563] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[564] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[565] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[566] = {6'd0, 8'd142, 8'd0, 32'd11};//{'dest': 142, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[567] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[568] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[569] = {6'd11, 8'd143, 8'd142, 32'd10};//{'dest': 143, 'src': 142, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[570] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[571] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[572] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[573] = {6'd0, 8'd141, 8'd0, 32'd515};//{'dest': 141, 'literal': 515, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[574] = {6'd0, 8'd142, 8'd0, 32'd12};//{'dest': 142, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[575] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[576] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[577] = {6'd11, 8'd143, 8'd142, 32'd10};//{'dest': 143, 'src': 142, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[578] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[579] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[580] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[581] = {6'd0, 8'd141, 8'd0, 32'd1029};//{'dest': 141, 'literal': 1029, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[582] = {6'd0, 8'd142, 8'd0, 32'd13};//{'dest': 142, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[583] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[584] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[585] = {6'd11, 8'd143, 8'd142, 32'd10};//{'dest': 143, 'src': 142, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[586] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[587] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[588] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[589] = {6'd0, 8'd141, 8'd0, 32'd49320};//{'dest': 141, 'literal': 49320, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[590] = {6'd0, 8'd142, 8'd0, 32'd14};//{'dest': 142, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[591] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[592] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[593] = {6'd11, 8'd143, 8'd142, 32'd10};//{'dest': 143, 'src': 142, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[594] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[595] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[596] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[597] = {6'd0, 8'd141, 8'd0, 32'd257};//{'dest': 141, 'literal': 257, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[598] = {6'd0, 8'd142, 8'd0, 32'd15};//{'dest': 142, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[599] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[600] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[601] = {6'd11, 8'd143, 8'd142, 32'd10};//{'dest': 143, 'src': 142, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[602] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[603] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[604] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[605] = {6'd0, 8'd147, 8'd0, 32'd11};//{'dest': 147, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[606] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[607] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[608] = {6'd11, 8'd148, 8'd147, 32'd36};//{'dest': 148, 'src': 147, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[609] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[610] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[611] = {6'd17, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842784848, 'op': 'memory_read_request'}
instructions[612] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[613] = {6'd18, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842784848, 'op': 'memory_read_wait'}
instructions[614] = {6'd19, 8'd141, 8'd148, 32'd0};//{'dest': 141, 'src': 148, 'sequence': 140152842784848, 'element_size': 2, 'op': 'memory_read'}
instructions[615] = {6'd0, 8'd142, 8'd0, 32'd16};//{'dest': 142, 'literal': 16, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[616] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[617] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[618] = {6'd11, 8'd143, 8'd142, 32'd10};//{'dest': 143, 'src': 142, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[619] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[620] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[621] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[622] = {6'd0, 8'd147, 8'd0, 32'd12};//{'dest': 147, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[623] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[624] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[625] = {6'd11, 8'd148, 8'd147, 32'd36};//{'dest': 148, 'src': 147, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[626] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[627] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[628] = {6'd17, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842785280, 'op': 'memory_read_request'}
instructions[629] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[630] = {6'd18, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842785280, 'op': 'memory_read_wait'}
instructions[631] = {6'd19, 8'd141, 8'd148, 32'd0};//{'dest': 141, 'src': 148, 'sequence': 140152842785280, 'element_size': 2, 'op': 'memory_read'}
instructions[632] = {6'd0, 8'd142, 8'd0, 32'd17};//{'dest': 142, 'literal': 17, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[633] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[634] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[635] = {6'd11, 8'd143, 8'd142, 32'd10};//{'dest': 143, 'src': 142, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[636] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[637] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[638] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[639] = {6'd0, 8'd147, 8'd0, 32'd13};//{'dest': 147, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[640] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[641] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[642] = {6'd11, 8'd148, 8'd147, 32'd36};//{'dest': 148, 'src': 147, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[643] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[644] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[645] = {6'd17, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842785712, 'op': 'memory_read_request'}
instructions[646] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[647] = {6'd18, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842785712, 'op': 'memory_read_wait'}
instructions[648] = {6'd19, 8'd141, 8'd148, 32'd0};//{'dest': 141, 'src': 148, 'sequence': 140152842785712, 'element_size': 2, 'op': 'memory_read'}
instructions[649] = {6'd0, 8'd142, 8'd0, 32'd18};//{'dest': 142, 'literal': 18, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[650] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[651] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[652] = {6'd11, 8'd143, 8'd142, 32'd10};//{'dest': 143, 'src': 142, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[653] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[654] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[655] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[656] = {6'd0, 8'd147, 8'd0, 32'd14};//{'dest': 147, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[657] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[658] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[659] = {6'd11, 8'd148, 8'd147, 32'd36};//{'dest': 148, 'src': 147, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[660] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[661] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[662] = {6'd17, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842786144, 'op': 'memory_read_request'}
instructions[663] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[664] = {6'd18, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842786144, 'op': 'memory_read_wait'}
instructions[665] = {6'd19, 8'd141, 8'd148, 32'd0};//{'dest': 141, 'src': 148, 'sequence': 140152842786144, 'element_size': 2, 'op': 'memory_read'}
instructions[666] = {6'd0, 8'd142, 8'd0, 32'd19};//{'dest': 142, 'literal': 19, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[667] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[668] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[669] = {6'd11, 8'd143, 8'd142, 32'd10};//{'dest': 143, 'src': 142, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[670] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[671] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[672] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[673] = {6'd0, 8'd147, 8'd0, 32'd15};//{'dest': 147, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[674] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[675] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[676] = {6'd11, 8'd148, 8'd147, 32'd36};//{'dest': 148, 'src': 147, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[677] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[678] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[679] = {6'd17, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842786576, 'op': 'memory_read_request'}
instructions[680] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[681] = {6'd18, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842786576, 'op': 'memory_read_wait'}
instructions[682] = {6'd19, 8'd141, 8'd148, 32'd0};//{'dest': 141, 'src': 148, 'sequence': 140152842786576, 'element_size': 2, 'op': 'memory_read'}
instructions[683] = {6'd0, 8'd142, 8'd0, 32'd20};//{'dest': 142, 'literal': 20, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[684] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[685] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[686] = {6'd11, 8'd143, 8'd142, 32'd10};//{'dest': 143, 'src': 142, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[687] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[688] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[689] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[690] = {6'd3, 8'd149, 8'd10, 32'd0};//{'dest': 149, 'src': 10, 'op': 'move'}
instructions[691] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[692] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[693] = {6'd3, 8'd26, 8'd149, 32'd0};//{'dest': 26, 'src': 149, 'op': 'move'}
instructions[694] = {6'd0, 8'd142, 8'd0, 32'd64};//{'dest': 142, 'literal': 64, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[695] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[696] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[697] = {6'd3, 8'd27, 8'd142, 32'd0};//{'dest': 27, 'src': 142, 'op': 'move'}
instructions[698] = {6'd0, 8'd143, 8'd0, 32'd11};//{'dest': 143, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[699] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[700] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[701] = {6'd11, 8'd147, 8'd143, 32'd36};//{'dest': 147, 'src': 143, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[702] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[703] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[704] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842799656, 'op': 'memory_read_request'}
instructions[705] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[706] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842799656, 'op': 'memory_read_wait'}
instructions[707] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152842799656, 'element_size': 2, 'op': 'memory_read'}
instructions[708] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[709] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[710] = {6'd3, 8'd28, 8'd142, 32'd0};//{'dest': 28, 'src': 142, 'op': 'move'}
instructions[711] = {6'd0, 8'd143, 8'd0, 32'd12};//{'dest': 143, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[712] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[713] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[714] = {6'd11, 8'd147, 8'd143, 32'd36};//{'dest': 147, 'src': 143, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[715] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[716] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[717] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842799800, 'op': 'memory_read_request'}
instructions[718] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[719] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842799800, 'op': 'memory_read_wait'}
instructions[720] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152842799800, 'element_size': 2, 'op': 'memory_read'}
instructions[721] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[722] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[723] = {6'd3, 8'd29, 8'd142, 32'd0};//{'dest': 29, 'src': 142, 'op': 'move'}
instructions[724] = {6'd0, 8'd143, 8'd0, 32'd13};//{'dest': 143, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[725] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[726] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[727] = {6'd11, 8'd147, 8'd143, 32'd36};//{'dest': 147, 'src': 143, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[728] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[729] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[730] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842799944, 'op': 'memory_read_request'}
instructions[731] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[732] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842799944, 'op': 'memory_read_wait'}
instructions[733] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152842799944, 'element_size': 2, 'op': 'memory_read'}
instructions[734] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[735] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[736] = {6'd3, 8'd30, 8'd142, 32'd0};//{'dest': 30, 'src': 142, 'op': 'move'}
instructions[737] = {6'd0, 8'd142, 8'd0, 32'd2054};//{'dest': 142, 'literal': 2054, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[738] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[739] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[740] = {6'd3, 8'd31, 8'd142, 32'd0};//{'dest': 31, 'src': 142, 'op': 'move'}
instructions[741] = {6'd1, 8'd25, 8'd0, 32'd218};//{'dest': 25, 'label': 218, 'op': 'jmp_and_link'}
instructions[742] = {6'd15, 8'd0, 8'd0, 32'd743};//{'label': 743, 'op': 'goto'}
instructions[743] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[744] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[745] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[746] = {6'd3, 8'd35, 8'd141, 32'd0};//{'dest': 35, 'src': 141, 'op': 'move'}
instructions[747] = {6'd6, 8'd0, 8'd34, 32'd0};//{'src': 34, 'op': 'jmp_to_reg'}
instructions[748] = {6'd15, 8'd0, 8'd0, 32'd749};//{'label': 749, 'op': 'goto'}
instructions[749] = {6'd3, 8'd141, 8'd37, 32'd0};//{'dest': 141, 'src': 37, 'op': 'move'}
instructions[750] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[751] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[752] = {6'd3, 8'd35, 8'd141, 32'd0};//{'dest': 35, 'src': 141, 'op': 'move'}
instructions[753] = {6'd6, 8'd0, 8'd34, 32'd0};//{'src': 34, 'op': 'jmp_to_reg'}
instructions[754] = {6'd0, 8'd50, 8'd0, 32'd0};//{'dest': 50, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[755] = {6'd0, 8'd51, 8'd0, 32'd0};//{'dest': 51, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[756] = {6'd0, 8'd52, 8'd0, 32'd600};//{'dest': 52, 'literal': 600, 'op': 'literal'}
instructions[757] = {6'd0, 8'd53, 8'd0, 32'd0};//{'dest': 53, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[758] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[759] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[760] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[761] = {6'd3, 8'd53, 8'd141, 32'd0};//{'dest': 53, 'src': 141, 'op': 'move'}
instructions[762] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[763] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[764] = {6'd3, 8'd142, 8'd53, 32'd0};//{'dest': 142, 'src': 53, 'op': 'move'}
instructions[765] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[766] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[767] = {6'd28, 8'd141, 8'd142, 32'd16};//{'src': 142, 'right': 16, 'dest': 141, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[768] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[769] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[770] = {6'd13, 8'd0, 8'd141, 32'd814};//{'src': 141, 'label': 814, 'op': 'jmp_if_false'}
instructions[771] = {6'd3, 8'd143, 8'd53, 32'd0};//{'dest': 143, 'src': 53, 'op': 'move'}
instructions[772] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[773] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[774] = {6'd11, 8'd147, 8'd143, 32'd40};//{'dest': 147, 'src': 143, 'srcb': 40, 'signed': False, 'op': '+'}
instructions[775] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[776] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[777] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842800304, 'op': 'memory_read_request'}
instructions[778] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[779] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842800304, 'op': 'memory_read_wait'}
instructions[780] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152842800304, 'element_size': 2, 'op': 'memory_read'}
instructions[781] = {6'd3, 8'd143, 8'd48, 32'd0};//{'dest': 143, 'src': 48, 'op': 'move'}
instructions[782] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[783] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[784] = {6'd29, 8'd141, 8'd142, 32'd143};//{'srcb': 143, 'src': 142, 'dest': 141, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[785] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[786] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[787] = {6'd13, 8'd0, 8'd141, 32'd802};//{'src': 141, 'label': 802, 'op': 'jmp_if_false'}
instructions[788] = {6'd3, 8'd143, 8'd53, 32'd0};//{'dest': 143, 'src': 53, 'op': 'move'}
instructions[789] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[790] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[791] = {6'd11, 8'd147, 8'd143, 32'd41};//{'dest': 147, 'src': 143, 'srcb': 41, 'signed': False, 'op': '+'}
instructions[792] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[793] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[794] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842800592, 'op': 'memory_read_request'}
instructions[795] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[796] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842800592, 'op': 'memory_read_wait'}
instructions[797] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152842800592, 'element_size': 2, 'op': 'memory_read'}
instructions[798] = {6'd3, 8'd143, 8'd49, 32'd0};//{'dest': 143, 'src': 49, 'op': 'move'}
instructions[799] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[800] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[801] = {6'd29, 8'd141, 8'd142, 32'd143};//{'srcb': 143, 'src': 142, 'dest': 141, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[802] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[803] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[804] = {6'd13, 8'd0, 8'd141, 32'd811};//{'src': 141, 'label': 811, 'op': 'jmp_if_false'}
instructions[805] = {6'd3, 8'd141, 8'd53, 32'd0};//{'dest': 141, 'src': 53, 'op': 'move'}
instructions[806] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[807] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[808] = {6'd3, 8'd47, 8'd141, 32'd0};//{'dest': 47, 'src': 141, 'op': 'move'}
instructions[809] = {6'd6, 8'd0, 8'd46, 32'd0};//{'src': 46, 'op': 'jmp_to_reg'}
instructions[810] = {6'd15, 8'd0, 8'd0, 32'd811};//{'label': 811, 'op': 'goto'}
instructions[811] = {6'd3, 8'd141, 8'd53, 32'd0};//{'dest': 141, 'src': 53, 'op': 'move'}
instructions[812] = {6'd14, 8'd53, 8'd53, 32'd1};//{'src': 53, 'right': 1, 'dest': 53, 'signed': False, 'op': '+', 'size': 2}
instructions[813] = {6'd15, 8'd0, 8'd0, 32'd762};//{'label': 762, 'op': 'goto'}
instructions[814] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[815] = {6'd0, 8'd142, 8'd0, 32'd7};//{'dest': 142, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[816] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[817] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[818] = {6'd11, 8'd143, 8'd142, 32'd10};//{'dest': 143, 'src': 142, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[819] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[820] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[821] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[822] = {6'd0, 8'd141, 8'd0, 32'd2048};//{'dest': 141, 'literal': 2048, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[823] = {6'd0, 8'd142, 8'd0, 32'd8};//{'dest': 142, 'literal': 8, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[824] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[825] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[826] = {6'd11, 8'd143, 8'd142, 32'd10};//{'dest': 143, 'src': 142, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[827] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[828] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[829] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[830] = {6'd0, 8'd141, 8'd0, 32'd1540};//{'dest': 141, 'literal': 1540, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[831] = {6'd0, 8'd142, 8'd0, 32'd9};//{'dest': 142, 'literal': 9, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[832] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[833] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[834] = {6'd11, 8'd143, 8'd142, 32'd10};//{'dest': 143, 'src': 142, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[835] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[836] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[837] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[838] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[839] = {6'd0, 8'd142, 8'd0, 32'd10};//{'dest': 142, 'literal': 10, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[840] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[841] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[842] = {6'd11, 8'd143, 8'd142, 32'd10};//{'dest': 143, 'src': 142, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[843] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[844] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[845] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[846] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[847] = {6'd0, 8'd142, 8'd0, 32'd11};//{'dest': 142, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[848] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[849] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[850] = {6'd11, 8'd143, 8'd142, 32'd10};//{'dest': 143, 'src': 142, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[851] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[852] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[853] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[854] = {6'd0, 8'd141, 8'd0, 32'd515};//{'dest': 141, 'literal': 515, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[855] = {6'd0, 8'd142, 8'd0, 32'd12};//{'dest': 142, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[856] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[857] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[858] = {6'd11, 8'd143, 8'd142, 32'd10};//{'dest': 143, 'src': 142, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[859] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[860] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[861] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[862] = {6'd0, 8'd141, 8'd0, 32'd1029};//{'dest': 141, 'literal': 1029, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[863] = {6'd0, 8'd142, 8'd0, 32'd13};//{'dest': 142, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[864] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[865] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[866] = {6'd11, 8'd143, 8'd142, 32'd10};//{'dest': 143, 'src': 142, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[867] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[868] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[869] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[870] = {6'd0, 8'd141, 8'd0, 32'd49320};//{'dest': 141, 'literal': 49320, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[871] = {6'd0, 8'd142, 8'd0, 32'd14};//{'dest': 142, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[872] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[873] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[874] = {6'd11, 8'd143, 8'd142, 32'd10};//{'dest': 143, 'src': 142, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[875] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[876] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[877] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[878] = {6'd0, 8'd141, 8'd0, 32'd257};//{'dest': 141, 'literal': 257, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[879] = {6'd0, 8'd142, 8'd0, 32'd15};//{'dest': 142, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[880] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[881] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[882] = {6'd11, 8'd143, 8'd142, 32'd10};//{'dest': 143, 'src': 142, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[883] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[884] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[885] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[886] = {6'd3, 8'd141, 8'd48, 32'd0};//{'dest': 141, 'src': 48, 'op': 'move'}
instructions[887] = {6'd0, 8'd142, 8'd0, 32'd19};//{'dest': 142, 'literal': 19, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[888] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[889] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[890] = {6'd11, 8'd143, 8'd142, 32'd10};//{'dest': 143, 'src': 142, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[891] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[892] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[893] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[894] = {6'd3, 8'd141, 8'd49, 32'd0};//{'dest': 141, 'src': 49, 'op': 'move'}
instructions[895] = {6'd0, 8'd142, 8'd0, 32'd20};//{'dest': 142, 'literal': 20, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[896] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[897] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[898] = {6'd11, 8'd143, 8'd142, 32'd10};//{'dest': 143, 'src': 142, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[899] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[900] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[901] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[902] = {6'd3, 8'd149, 8'd10, 32'd0};//{'dest': 149, 'src': 10, 'op': 'move'}
instructions[903] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[904] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[905] = {6'd3, 8'd26, 8'd149, 32'd0};//{'dest': 26, 'src': 149, 'op': 'move'}
instructions[906] = {6'd0, 8'd142, 8'd0, 32'd64};//{'dest': 142, 'literal': 64, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[907] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[908] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[909] = {6'd3, 8'd27, 8'd142, 32'd0};//{'dest': 27, 'src': 142, 'op': 'move'}
instructions[910] = {6'd0, 8'd142, 8'd0, 32'd65535};//{'dest': 142, 'literal': 65535, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[911] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[912] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[913] = {6'd3, 8'd28, 8'd142, 32'd0};//{'dest': 28, 'src': 142, 'op': 'move'}
instructions[914] = {6'd0, 8'd142, 8'd0, 32'd65535};//{'dest': 142, 'literal': 65535, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[915] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[916] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[917] = {6'd3, 8'd29, 8'd142, 32'd0};//{'dest': 29, 'src': 142, 'op': 'move'}
instructions[918] = {6'd0, 8'd142, 8'd0, 32'd65535};//{'dest': 142, 'literal': 65535, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[919] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[920] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[921] = {6'd3, 8'd30, 8'd142, 32'd0};//{'dest': 30, 'src': 142, 'op': 'move'}
instructions[922] = {6'd0, 8'd142, 8'd0, 32'd2054};//{'dest': 142, 'literal': 2054, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[923] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[924] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[925] = {6'd3, 8'd31, 8'd142, 32'd0};//{'dest': 31, 'src': 142, 'op': 'move'}
instructions[926] = {6'd1, 8'd25, 8'd0, 32'd218};//{'dest': 25, 'label': 218, 'op': 'jmp_and_link'}
instructions[927] = {6'd1, 8'd4, 8'd0, 32'd44};//{'dest': 4, 'label': 44, 'op': 'jmp_and_link'}
instructions[928] = {6'd3, 8'd141, 8'd5, 32'd0};//{'dest': 141, 'src': 5, 'op': 'move'}
instructions[929] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[930] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[931] = {6'd3, 8'd50, 8'd141, 32'd0};//{'dest': 50, 'src': 141, 'op': 'move'}
instructions[932] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[933] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[934] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[935] = {6'd3, 8'd53, 8'd141, 32'd0};//{'dest': 53, 'src': 141, 'op': 'move'}
instructions[936] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[937] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[938] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[939] = {6'd3, 8'd51, 8'd141, 32'd0};//{'dest': 51, 'src': 141, 'op': 'move'}
instructions[940] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[941] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[942] = {6'd3, 8'd142, 8'd51, 32'd0};//{'dest': 142, 'src': 51, 'op': 'move'}
instructions[943] = {6'd3, 8'd143, 8'd50, 32'd0};//{'dest': 143, 'src': 50, 'op': 'move'}
instructions[944] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[945] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[946] = {6'd20, 8'd141, 8'd142, 32'd143};//{'srcb': 143, 'src': 142, 'dest': 141, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[947] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[948] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[949] = {6'd13, 8'd0, 8'd141, 32'd979};//{'src': 141, 'label': 979, 'op': 'jmp_if_false'}
instructions[950] = {6'd3, 8'd142, 8'd53, 32'd0};//{'dest': 142, 'src': 53, 'op': 'move'}
instructions[951] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[952] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[953] = {6'd28, 8'd141, 8'd142, 32'd16};//{'src': 142, 'right': 16, 'dest': 141, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[954] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[955] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[956] = {6'd13, 8'd0, 8'd141, 32'd967};//{'src': 141, 'label': 967, 'op': 'jmp_if_false'}
instructions[957] = {6'd1, 8'd4, 8'd0, 32'd44};//{'dest': 4, 'label': 44, 'op': 'jmp_and_link'}
instructions[958] = {6'd3, 8'd141, 8'd5, 32'd0};//{'dest': 141, 'src': 5, 'op': 'move'}
instructions[959] = {6'd3, 8'd142, 8'd53, 32'd0};//{'dest': 142, 'src': 53, 'op': 'move'}
instructions[960] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[961] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[962] = {6'd11, 8'd143, 8'd142, 32'd52};//{'dest': 143, 'src': 142, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[963] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[964] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[965] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[966] = {6'd15, 8'd0, 8'd0, 32'd969};//{'label': 969, 'op': 'goto'}
instructions[967] = {6'd1, 8'd4, 8'd0, 32'd44};//{'dest': 4, 'label': 44, 'op': 'jmp_and_link'}
instructions[968] = {6'd3, 8'd141, 8'd5, 32'd0};//{'dest': 141, 'src': 5, 'op': 'move'}
instructions[969] = {6'd3, 8'd141, 8'd53, 32'd0};//{'dest': 141, 'src': 53, 'op': 'move'}
instructions[970] = {6'd14, 8'd53, 8'd53, 32'd1};//{'src': 53, 'right': 1, 'dest': 53, 'signed': False, 'op': '+', 'size': 2}
instructions[971] = {6'd3, 8'd142, 8'd51, 32'd0};//{'dest': 142, 'src': 51, 'op': 'move'}
instructions[972] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[973] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[974] = {6'd14, 8'd141, 8'd142, 32'd2};//{'src': 142, 'right': 2, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[975] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[976] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[977] = {6'd3, 8'd51, 8'd141, 32'd0};//{'dest': 51, 'src': 141, 'op': 'move'}
instructions[978] = {6'd15, 8'd0, 8'd0, 32'd940};//{'label': 940, 'op': 'goto'}
instructions[979] = {6'd0, 8'd143, 8'd0, 32'd6};//{'dest': 143, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[980] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[981] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[982] = {6'd11, 8'd147, 8'd143, 32'd52};//{'dest': 147, 'src': 143, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[983] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[984] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[985] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842863104, 'op': 'memory_read_request'}
instructions[986] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[987] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842863104, 'op': 'memory_read_wait'}
instructions[988] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152842863104, 'element_size': 2, 'op': 'memory_read'}
instructions[989] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[990] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[991] = {6'd25, 8'd141, 8'd142, 32'd2054};//{'src': 142, 'right': 2054, 'dest': 141, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[992] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[993] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[994] = {6'd13, 8'd0, 8'd141, 32'd1008};//{'src': 141, 'label': 1008, 'op': 'jmp_if_false'}
instructions[995] = {6'd0, 8'd143, 8'd0, 32'd10};//{'dest': 143, 'literal': 10, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[996] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[997] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[998] = {6'd11, 8'd147, 8'd143, 32'd52};//{'dest': 147, 'src': 143, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[999] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1000] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1001] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842863392, 'op': 'memory_read_request'}
instructions[1002] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1003] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842863392, 'op': 'memory_read_wait'}
instructions[1004] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152842863392, 'element_size': 2, 'op': 'memory_read'}
instructions[1005] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1006] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1007] = {6'd25, 8'd141, 8'd142, 32'd2};//{'src': 142, 'right': 2, 'dest': 141, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1008] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1009] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1010] = {6'd13, 8'd0, 8'd141, 32'd1139};//{'src': 141, 'label': 1139, 'op': 'jmp_if_false'}
instructions[1011] = {6'd0, 8'd143, 8'd0, 32'd14};//{'dest': 143, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1012] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1013] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1014] = {6'd11, 8'd147, 8'd143, 32'd52};//{'dest': 147, 'src': 143, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[1015] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1016] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1017] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842863968, 'op': 'memory_read_request'}
instructions[1018] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1019] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842863968, 'op': 'memory_read_wait'}
instructions[1020] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152842863968, 'element_size': 2, 'op': 'memory_read'}
instructions[1021] = {6'd3, 8'd143, 8'd48, 32'd0};//{'dest': 143, 'src': 48, 'op': 'move'}
instructions[1022] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1023] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1024] = {6'd29, 8'd141, 8'd142, 32'd143};//{'srcb': 143, 'src': 142, 'dest': 141, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1025] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1026] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1027] = {6'd13, 8'd0, 8'd141, 32'd1042};//{'src': 141, 'label': 1042, 'op': 'jmp_if_false'}
instructions[1028] = {6'd0, 8'd143, 8'd0, 32'd15};//{'dest': 143, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1029] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1030] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1031] = {6'd11, 8'd147, 8'd143, 32'd52};//{'dest': 147, 'src': 143, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[1032] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1033] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1034] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842864256, 'op': 'memory_read_request'}
instructions[1035] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1036] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842864256, 'op': 'memory_read_wait'}
instructions[1037] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152842864256, 'element_size': 2, 'op': 'memory_read'}
instructions[1038] = {6'd3, 8'd143, 8'd49, 32'd0};//{'dest': 143, 'src': 49, 'op': 'move'}
instructions[1039] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1040] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1041] = {6'd29, 8'd141, 8'd142, 32'd143};//{'srcb': 143, 'src': 142, 'dest': 141, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1042] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1043] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1044] = {6'd13, 8'd0, 8'd141, 32'd1138};//{'src': 141, 'label': 1138, 'op': 'jmp_if_false'}
instructions[1045] = {6'd3, 8'd141, 8'd48, 32'd0};//{'dest': 141, 'src': 48, 'op': 'move'}
instructions[1046] = {6'd3, 8'd142, 8'd45, 32'd0};//{'dest': 142, 'src': 45, 'op': 'move'}
instructions[1047] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1048] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1049] = {6'd11, 8'd143, 8'd142, 32'd40};//{'dest': 143, 'src': 142, 'srcb': 40, 'signed': False, 'op': '+'}
instructions[1050] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1051] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1052] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[1053] = {6'd3, 8'd141, 8'd49, 32'd0};//{'dest': 141, 'src': 49, 'op': 'move'}
instructions[1054] = {6'd3, 8'd142, 8'd45, 32'd0};//{'dest': 142, 'src': 45, 'op': 'move'}
instructions[1055] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1056] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1057] = {6'd11, 8'd143, 8'd142, 32'd41};//{'dest': 143, 'src': 142, 'srcb': 41, 'signed': False, 'op': '+'}
instructions[1058] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1059] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1060] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[1061] = {6'd0, 8'd147, 8'd0, 32'd11};//{'dest': 147, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1062] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1063] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1064] = {6'd11, 8'd148, 8'd147, 32'd52};//{'dest': 148, 'src': 147, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[1065] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1066] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1067] = {6'd17, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842865624, 'op': 'memory_read_request'}
instructions[1068] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1069] = {6'd18, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842865624, 'op': 'memory_read_wait'}
instructions[1070] = {6'd19, 8'd141, 8'd148, 32'd0};//{'dest': 141, 'src': 148, 'sequence': 140152842865624, 'element_size': 2, 'op': 'memory_read'}
instructions[1071] = {6'd3, 8'd142, 8'd45, 32'd0};//{'dest': 142, 'src': 45, 'op': 'move'}
instructions[1072] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1073] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1074] = {6'd11, 8'd143, 8'd142, 32'd42};//{'dest': 143, 'src': 142, 'srcb': 42, 'signed': False, 'op': '+'}
instructions[1075] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1076] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1077] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[1078] = {6'd0, 8'd147, 8'd0, 32'd12};//{'dest': 147, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1079] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1080] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1081] = {6'd11, 8'd148, 8'd147, 32'd52};//{'dest': 148, 'src': 147, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[1082] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1083] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1084] = {6'd17, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842866056, 'op': 'memory_read_request'}
instructions[1085] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1086] = {6'd18, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842866056, 'op': 'memory_read_wait'}
instructions[1087] = {6'd19, 8'd141, 8'd148, 32'd0};//{'dest': 141, 'src': 148, 'sequence': 140152842866056, 'element_size': 2, 'op': 'memory_read'}
instructions[1088] = {6'd3, 8'd142, 8'd45, 32'd0};//{'dest': 142, 'src': 45, 'op': 'move'}
instructions[1089] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1090] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1091] = {6'd11, 8'd143, 8'd142, 32'd43};//{'dest': 143, 'src': 142, 'srcb': 43, 'signed': False, 'op': '+'}
instructions[1092] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1093] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1094] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[1095] = {6'd0, 8'd147, 8'd0, 32'd13};//{'dest': 147, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1096] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1097] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1098] = {6'd11, 8'd148, 8'd147, 32'd52};//{'dest': 148, 'src': 147, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[1099] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1100] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1101] = {6'd17, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842866488, 'op': 'memory_read_request'}
instructions[1102] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1103] = {6'd18, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842866488, 'op': 'memory_read_wait'}
instructions[1104] = {6'd19, 8'd141, 8'd148, 32'd0};//{'dest': 141, 'src': 148, 'sequence': 140152842866488, 'element_size': 2, 'op': 'memory_read'}
instructions[1105] = {6'd3, 8'd142, 8'd45, 32'd0};//{'dest': 142, 'src': 45, 'op': 'move'}
instructions[1106] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1107] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1108] = {6'd11, 8'd143, 8'd142, 32'd44};//{'dest': 143, 'src': 142, 'srcb': 44, 'signed': False, 'op': '+'}
instructions[1109] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1110] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1111] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[1112] = {6'd3, 8'd141, 8'd45, 32'd0};//{'dest': 141, 'src': 45, 'op': 'move'}
instructions[1113] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1114] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1115] = {6'd3, 8'd53, 8'd141, 32'd0};//{'dest': 53, 'src': 141, 'op': 'move'}
instructions[1116] = {6'd3, 8'd141, 8'd45, 32'd0};//{'dest': 141, 'src': 45, 'op': 'move'}
instructions[1117] = {6'd14, 8'd45, 8'd45, 32'd1};//{'src': 45, 'right': 1, 'dest': 45, 'signed': False, 'op': '+', 'size': 2}
instructions[1118] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1119] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1120] = {6'd3, 8'd142, 8'd45, 32'd0};//{'dest': 142, 'src': 45, 'op': 'move'}
instructions[1121] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1122] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1123] = {6'd25, 8'd141, 8'd142, 32'd16};//{'src': 142, 'right': 16, 'dest': 141, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1124] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1125] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1126] = {6'd13, 8'd0, 8'd141, 32'd1132};//{'src': 141, 'label': 1132, 'op': 'jmp_if_false'}
instructions[1127] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1128] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1129] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1130] = {6'd3, 8'd45, 8'd141, 32'd0};//{'dest': 45, 'src': 141, 'op': 'move'}
instructions[1131] = {6'd15, 8'd0, 8'd0, 32'd1132};//{'label': 1132, 'op': 'goto'}
instructions[1132] = {6'd3, 8'd141, 8'd53, 32'd0};//{'dest': 141, 'src': 53, 'op': 'move'}
instructions[1133] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1134] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1135] = {6'd3, 8'd47, 8'd141, 32'd0};//{'dest': 47, 'src': 141, 'op': 'move'}
instructions[1136] = {6'd6, 8'd0, 8'd46, 32'd0};//{'src': 46, 'op': 'jmp_to_reg'}
instructions[1137] = {6'd15, 8'd0, 8'd0, 32'd1138};//{'label': 1138, 'op': 'goto'}
instructions[1138] = {6'd15, 8'd0, 8'd0, 32'd1139};//{'label': 1139, 'op': 'goto'}
instructions[1139] = {6'd15, 8'd0, 8'd0, 32'd927};//{'label': 927, 'op': 'goto'}
instructions[1140] = {6'd0, 8'd60, 8'd0, 32'd0};//{'dest': 60, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1141] = {6'd0, 8'd61, 8'd0, 32'd0};//{'dest': 61, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1142] = {6'd0, 8'd62, 8'd0, 32'd0};//{'dest': 62, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1143] = {6'd3, 8'd142, 8'd58, 32'd0};//{'dest': 142, 'src': 58, 'op': 'move'}
instructions[1144] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1145] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1146] = {6'd3, 8'd48, 8'd142, 32'd0};//{'dest': 48, 'src': 142, 'op': 'move'}
instructions[1147] = {6'd3, 8'd142, 8'd59, 32'd0};//{'dest': 142, 'src': 59, 'op': 'move'}
instructions[1148] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1149] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1150] = {6'd3, 8'd49, 8'd142, 32'd0};//{'dest': 49, 'src': 142, 'op': 'move'}
instructions[1151] = {6'd1, 8'd46, 8'd0, 32'd754};//{'dest': 46, 'label': 754, 'op': 'jmp_and_link'}
instructions[1152] = {6'd3, 8'd141, 8'd47, 32'd0};//{'dest': 141, 'src': 47, 'op': 'move'}
instructions[1153] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1154] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1155] = {6'd3, 8'd62, 8'd141, 32'd0};//{'dest': 62, 'src': 141, 'op': 'move'}
instructions[1156] = {6'd0, 8'd141, 8'd0, 32'd17664};//{'dest': 141, 'literal': 17664, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1157] = {6'd0, 8'd142, 8'd0, 32'd7};//{'dest': 142, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1158] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1159] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1160] = {6'd27, 8'd143, 8'd142, 32'd55};//{'dest': 143, 'src': 142, 'srcb': 55, 'signed': True, 'op': '+'}
instructions[1161] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1162] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1163] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[1164] = {6'd3, 8'd141, 8'd56, 32'd0};//{'dest': 141, 'src': 56, 'op': 'move'}
instructions[1165] = {6'd0, 8'd142, 8'd0, 32'd8};//{'dest': 142, 'literal': 8, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1166] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1167] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1168] = {6'd11, 8'd143, 8'd142, 32'd55};//{'dest': 143, 'src': 142, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1169] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1170] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1171] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[1172] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1173] = {6'd0, 8'd142, 8'd0, 32'd9};//{'dest': 142, 'literal': 9, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1174] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1175] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1176] = {6'd27, 8'd143, 8'd142, 32'd55};//{'dest': 143, 'src': 142, 'srcb': 55, 'signed': True, 'op': '+'}
instructions[1177] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1178] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1179] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[1180] = {6'd0, 8'd141, 8'd0, 32'd16384};//{'dest': 141, 'literal': 16384, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1181] = {6'd0, 8'd142, 8'd0, 32'd10};//{'dest': 142, 'literal': 10, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1182] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1183] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1184] = {6'd27, 8'd143, 8'd142, 32'd55};//{'dest': 143, 'src': 142, 'srcb': 55, 'signed': True, 'op': '+'}
instructions[1185] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1186] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1187] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[1188] = {6'd3, 8'd147, 8'd57, 32'd0};//{'dest': 147, 'src': 57, 'op': 'move'}
instructions[1189] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1190] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1191] = {6'd30, 8'd141, 8'd147, 32'd65280};//{'src': 147, 'dest': 141, 'signed': False, 'op': '|', 'size': 2, 'type': 'int', 'left': 65280}
instructions[1192] = {6'd0, 8'd142, 8'd0, 32'd11};//{'dest': 142, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1193] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1194] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1195] = {6'd11, 8'd143, 8'd142, 32'd55};//{'dest': 143, 'src': 142, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1196] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1197] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1198] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[1199] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1200] = {6'd0, 8'd142, 8'd0, 32'd12};//{'dest': 142, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1201] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1202] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1203] = {6'd27, 8'd143, 8'd142, 32'd55};//{'dest': 143, 'src': 142, 'srcb': 55, 'signed': True, 'op': '+'}
instructions[1204] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1205] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1206] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[1207] = {6'd0, 8'd141, 8'd0, 32'd49320};//{'dest': 141, 'literal': 49320, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1208] = {6'd0, 8'd142, 8'd0, 32'd13};//{'dest': 142, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1209] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1210] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1211] = {6'd11, 8'd143, 8'd142, 32'd55};//{'dest': 143, 'src': 142, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1212] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1213] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1214] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[1215] = {6'd0, 8'd141, 8'd0, 32'd257};//{'dest': 141, 'literal': 257, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1216] = {6'd0, 8'd142, 8'd0, 32'd14};//{'dest': 142, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1217] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1218] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1219] = {6'd11, 8'd143, 8'd142, 32'd55};//{'dest': 143, 'src': 142, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1220] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1221] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1222] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[1223] = {6'd3, 8'd141, 8'd58, 32'd0};//{'dest': 141, 'src': 58, 'op': 'move'}
instructions[1224] = {6'd0, 8'd142, 8'd0, 32'd15};//{'dest': 142, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1225] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1226] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1227] = {6'd11, 8'd143, 8'd142, 32'd55};//{'dest': 143, 'src': 142, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1228] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1229] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1230] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[1231] = {6'd3, 8'd141, 8'd59, 32'd0};//{'dest': 141, 'src': 59, 'op': 'move'}
instructions[1232] = {6'd0, 8'd142, 8'd0, 32'd16};//{'dest': 142, 'literal': 16, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1233] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1234] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1235] = {6'd11, 8'd143, 8'd142, 32'd55};//{'dest': 143, 'src': 142, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1236] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1237] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1238] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[1239] = {6'd3, 8'd142, 8'd56, 32'd0};//{'dest': 142, 'src': 56, 'op': 'move'}
instructions[1240] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1241] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1242] = {6'd14, 8'd141, 8'd142, 32'd14};//{'src': 142, 'right': 14, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1243] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1244] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1245] = {6'd3, 8'd60, 8'd141, 32'd0};//{'dest': 60, 'src': 141, 'op': 'move'}
instructions[1246] = {6'd1, 8'd12, 8'd0, 32'd59};//{'dest': 12, 'label': 59, 'op': 'jmp_and_link'}
instructions[1247] = {6'd0, 8'd141, 8'd0, 32'd7};//{'dest': 141, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1248] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1249] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1250] = {6'd3, 8'd61, 8'd141, 32'd0};//{'dest': 61, 'src': 141, 'op': 'move'}
instructions[1251] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1252] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1253] = {6'd3, 8'd142, 8'd61, 32'd0};//{'dest': 142, 'src': 61, 'op': 'move'}
instructions[1254] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1255] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1256] = {6'd31, 8'd141, 8'd142, 32'd16};//{'src': 142, 'right': 16, 'dest': 141, 'signed': False, 'op': '<=', 'type': 'int', 'size': 2}
instructions[1257] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1258] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1259] = {6'd13, 8'd0, 8'd141, 32'd1277};//{'src': 141, 'label': 1277, 'op': 'jmp_if_false'}
instructions[1260] = {6'd3, 8'd143, 8'd61, 32'd0};//{'dest': 143, 'src': 61, 'op': 'move'}
instructions[1261] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1262] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1263] = {6'd11, 8'd147, 8'd143, 32'd55};//{'dest': 147, 'src': 143, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1264] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1265] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1266] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842924904, 'op': 'memory_read_request'}
instructions[1267] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1268] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842924904, 'op': 'memory_read_wait'}
instructions[1269] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152842924904, 'element_size': 2, 'op': 'memory_read'}
instructions[1270] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1271] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1272] = {6'd3, 8'd14, 8'd142, 32'd0};//{'dest': 14, 'src': 142, 'op': 'move'}
instructions[1273] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[1274] = {6'd3, 8'd141, 8'd61, 32'd0};//{'dest': 141, 'src': 61, 'op': 'move'}
instructions[1275] = {6'd14, 8'd61, 8'd61, 32'd1};//{'src': 61, 'right': 1, 'dest': 61, 'signed': False, 'op': '+', 'size': 2}
instructions[1276] = {6'd15, 8'd0, 8'd0, 32'd1251};//{'label': 1251, 'op': 'goto'}
instructions[1277] = {6'd1, 8'd15, 8'd0, 32'd100};//{'dest': 15, 'label': 100, 'op': 'jmp_and_link'}
instructions[1278] = {6'd3, 8'd141, 8'd16, 32'd0};//{'dest': 141, 'src': 16, 'op': 'move'}
instructions[1279] = {6'd0, 8'd142, 8'd0, 32'd12};//{'dest': 142, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1280] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1281] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1282] = {6'd11, 8'd143, 8'd142, 32'd55};//{'dest': 143, 'src': 142, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1283] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1284] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1285] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[1286] = {6'd3, 8'd142, 8'd60, 32'd0};//{'dest': 142, 'src': 60, 'op': 'move'}
instructions[1287] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1288] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1289] = {6'd28, 8'd141, 8'd142, 32'd64};//{'src': 142, 'right': 64, 'dest': 141, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[1290] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1291] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1292] = {6'd13, 8'd0, 8'd141, 32'd1298};//{'src': 141, 'label': 1298, 'op': 'jmp_if_false'}
instructions[1293] = {6'd0, 8'd141, 8'd0, 32'd64};//{'dest': 141, 'literal': 64, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1294] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1295] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1296] = {6'd3, 8'd60, 8'd141, 32'd0};//{'dest': 60, 'src': 141, 'op': 'move'}
instructions[1297] = {6'd15, 8'd0, 8'd0, 32'd1298};//{'label': 1298, 'op': 'goto'}
instructions[1298] = {6'd3, 8'd144, 8'd55, 32'd0};//{'dest': 144, 'src': 55, 'op': 'move'}
instructions[1299] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1300] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1301] = {6'd3, 8'd26, 8'd144, 32'd0};//{'dest': 26, 'src': 144, 'op': 'move'}
instructions[1302] = {6'd3, 8'd142, 8'd60, 32'd0};//{'dest': 142, 'src': 60, 'op': 'move'}
instructions[1303] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1304] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1305] = {6'd3, 8'd27, 8'd142, 32'd0};//{'dest': 27, 'src': 142, 'op': 'move'}
instructions[1306] = {6'd3, 8'd143, 8'd62, 32'd0};//{'dest': 143, 'src': 62, 'op': 'move'}
instructions[1307] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1308] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1309] = {6'd11, 8'd147, 8'd143, 32'd42};//{'dest': 147, 'src': 143, 'srcb': 42, 'signed': False, 'op': '+'}
instructions[1310] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1311] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1312] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842926560, 'op': 'memory_read_request'}
instructions[1313] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1314] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842926560, 'op': 'memory_read_wait'}
instructions[1315] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152842926560, 'element_size': 2, 'op': 'memory_read'}
instructions[1316] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1317] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1318] = {6'd3, 8'd28, 8'd142, 32'd0};//{'dest': 28, 'src': 142, 'op': 'move'}
instructions[1319] = {6'd3, 8'd143, 8'd62, 32'd0};//{'dest': 143, 'src': 62, 'op': 'move'}
instructions[1320] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1321] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1322] = {6'd11, 8'd147, 8'd143, 32'd43};//{'dest': 147, 'src': 143, 'srcb': 43, 'signed': False, 'op': '+'}
instructions[1323] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1324] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1325] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842926704, 'op': 'memory_read_request'}
instructions[1326] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1327] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842926704, 'op': 'memory_read_wait'}
instructions[1328] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152842926704, 'element_size': 2, 'op': 'memory_read'}
instructions[1329] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1330] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1331] = {6'd3, 8'd29, 8'd142, 32'd0};//{'dest': 29, 'src': 142, 'op': 'move'}
instructions[1332] = {6'd3, 8'd143, 8'd62, 32'd0};//{'dest': 143, 'src': 62, 'op': 'move'}
instructions[1333] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1334] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1335] = {6'd11, 8'd147, 8'd143, 32'd44};//{'dest': 147, 'src': 143, 'srcb': 44, 'signed': False, 'op': '+'}
instructions[1336] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1337] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1338] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842926848, 'op': 'memory_read_request'}
instructions[1339] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1340] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842926848, 'op': 'memory_read_wait'}
instructions[1341] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152842926848, 'element_size': 2, 'op': 'memory_read'}
instructions[1342] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1343] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1344] = {6'd3, 8'd30, 8'd142, 32'd0};//{'dest': 30, 'src': 142, 'op': 'move'}
instructions[1345] = {6'd0, 8'd142, 8'd0, 32'd2048};//{'dest': 142, 'literal': 2048, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1346] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1347] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1348] = {6'd3, 8'd31, 8'd142, 32'd0};//{'dest': 31, 'src': 142, 'op': 'move'}
instructions[1349] = {6'd1, 8'd25, 8'd0, 32'd218};//{'dest': 25, 'label': 218, 'op': 'jmp_and_link'}
instructions[1350] = {6'd6, 8'd0, 8'd54, 32'd0};//{'src': 54, 'op': 'jmp_to_reg'}
instructions[1351] = {6'd0, 8'd66, 8'd0, 32'd0};//{'dest': 66, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1352] = {6'd0, 8'd67, 8'd0, 32'd0};//{'dest': 67, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1353] = {6'd0, 8'd68, 8'd0, 32'd0};//{'dest': 68, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1354] = {6'd0, 8'd69, 8'd0, 32'd0};//{'dest': 69, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1355] = {6'd0, 8'd70, 8'd0, 32'd0};//{'dest': 70, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1356] = {6'd0, 8'd71, 8'd0, 32'd0};//{'dest': 71, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1357] = {6'd0, 8'd72, 8'd0, 32'd0};//{'dest': 72, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1358] = {6'd0, 8'd73, 8'd0, 32'd0};//{'dest': 73, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1359] = {6'd0, 8'd74, 8'd0, 32'd0};//{'dest': 74, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1360] = {6'd3, 8'd144, 8'd65, 32'd0};//{'dest': 144, 'src': 65, 'op': 'move'}
instructions[1361] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1362] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1363] = {6'd3, 8'd36, 8'd144, 32'd0};//{'dest': 36, 'src': 144, 'op': 'move'}
instructions[1364] = {6'd1, 8'd34, 8'd0, 32'd328};//{'dest': 34, 'label': 328, 'op': 'jmp_and_link'}
instructions[1365] = {6'd3, 8'd141, 8'd35, 32'd0};//{'dest': 141, 'src': 35, 'op': 'move'}
instructions[1366] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1367] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1368] = {6'd3, 8'd74, 8'd141, 32'd0};//{'dest': 74, 'src': 141, 'op': 'move'}
instructions[1369] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1370] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1371] = {6'd3, 8'd142, 8'd74, 32'd0};//{'dest': 142, 'src': 74, 'op': 'move'}
instructions[1372] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1373] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1374] = {6'd25, 8'd141, 8'd142, 32'd0};//{'src': 142, 'right': 0, 'dest': 141, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1375] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1376] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1377] = {6'd13, 8'd0, 8'd141, 32'd1384};//{'src': 141, 'label': 1384, 'op': 'jmp_if_false'}
instructions[1378] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1379] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1380] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1381] = {6'd3, 8'd64, 8'd141, 32'd0};//{'dest': 64, 'src': 141, 'op': 'move'}
instructions[1382] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1383] = {6'd15, 8'd0, 8'd0, 32'd1384};//{'label': 1384, 'op': 'goto'}
instructions[1384] = {6'd0, 8'd143, 8'd0, 32'd6};//{'dest': 143, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1385] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1386] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1387] = {6'd11, 8'd147, 8'd143, 32'd65};//{'dest': 147, 'src': 143, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1388] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1389] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1390] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842927568, 'op': 'memory_read_request'}
instructions[1391] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1392] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842927568, 'op': 'memory_read_wait'}
instructions[1393] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152842927568, 'element_size': 2, 'op': 'memory_read'}
instructions[1394] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1395] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1396] = {6'd26, 8'd141, 8'd142, 32'd2048};//{'src': 142, 'right': 2048, 'dest': 141, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[1397] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1398] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1399] = {6'd13, 8'd0, 8'd141, 32'd1406};//{'src': 141, 'label': 1406, 'op': 'jmp_if_false'}
instructions[1400] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1401] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1402] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1403] = {6'd3, 8'd64, 8'd141, 32'd0};//{'dest': 64, 'src': 141, 'op': 'move'}
instructions[1404] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1405] = {6'd15, 8'd0, 8'd0, 32'd1406};//{'label': 1406, 'op': 'goto'}
instructions[1406] = {6'd0, 8'd143, 8'd0, 32'd15};//{'dest': 143, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1407] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1408] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1409] = {6'd11, 8'd147, 8'd143, 32'd65};//{'dest': 147, 'src': 143, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1410] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1411] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1412] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842928072, 'op': 'memory_read_request'}
instructions[1413] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1414] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842928072, 'op': 'memory_read_wait'}
instructions[1415] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152842928072, 'element_size': 2, 'op': 'memory_read'}
instructions[1416] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1417] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1418] = {6'd26, 8'd141, 8'd142, 32'd49320};//{'src': 142, 'right': 49320, 'dest': 141, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[1419] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1420] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1421] = {6'd13, 8'd0, 8'd141, 32'd1428};//{'src': 141, 'label': 1428, 'op': 'jmp_if_false'}
instructions[1422] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1423] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1424] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1425] = {6'd3, 8'd64, 8'd141, 32'd0};//{'dest': 64, 'src': 141, 'op': 'move'}
instructions[1426] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1427] = {6'd15, 8'd0, 8'd0, 32'd1428};//{'label': 1428, 'op': 'goto'}
instructions[1428] = {6'd0, 8'd143, 8'd0, 32'd16};//{'dest': 143, 'literal': 16, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1429] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1430] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1431] = {6'd11, 8'd147, 8'd143, 32'd65};//{'dest': 147, 'src': 143, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1432] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1433] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1434] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842953216, 'op': 'memory_read_request'}
instructions[1435] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1436] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842953216, 'op': 'memory_read_wait'}
instructions[1437] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152842953216, 'element_size': 2, 'op': 'memory_read'}
instructions[1438] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1439] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1440] = {6'd26, 8'd141, 8'd142, 32'd257};//{'src': 142, 'right': 257, 'dest': 141, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[1441] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1442] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1443] = {6'd13, 8'd0, 8'd141, 32'd1450};//{'src': 141, 'label': 1450, 'op': 'jmp_if_false'}
instructions[1444] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1445] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1446] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1447] = {6'd3, 8'd64, 8'd141, 32'd0};//{'dest': 64, 'src': 141, 'op': 'move'}
instructions[1448] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1449] = {6'd15, 8'd0, 8'd0, 32'd1450};//{'label': 1450, 'op': 'goto'}
instructions[1450] = {6'd0, 8'd147, 8'd0, 32'd11};//{'dest': 147, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1451] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1452] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1453] = {6'd11, 8'd148, 8'd147, 32'd65};//{'dest': 148, 'src': 147, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1454] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1455] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1456] = {6'd17, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842957960, 'op': 'memory_read_request'}
instructions[1457] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1458] = {6'd18, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842957960, 'op': 'memory_read_wait'}
instructions[1459] = {6'd19, 8'd143, 8'd148, 32'd0};//{'dest': 143, 'src': 148, 'sequence': 140152842957960, 'element_size': 2, 'op': 'memory_read'}
instructions[1460] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1461] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1462] = {6'd12, 8'd142, 8'd143, 32'd255};//{'src': 143, 'right': 255, 'dest': 142, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[1463] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1464] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1465] = {6'd25, 8'd141, 8'd142, 32'd1};//{'src': 142, 'right': 1, 'dest': 141, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1466] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1467] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1468] = {6'd13, 8'd0, 8'd141, 32'd1675};//{'src': 141, 'label': 1675, 'op': 'jmp_if_false'}
instructions[1469] = {6'd0, 8'd148, 8'd0, 32'd7};//{'dest': 148, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1470] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1471] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1472] = {6'd11, 8'd150, 8'd148, 32'd65};//{'dest': 150, 'src': 148, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1473] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1474] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1475] = {6'd17, 8'd0, 8'd150, 32'd0};//{'element_size': 2, 'src': 150, 'sequence': 140152842180512, 'op': 'memory_read_request'}
instructions[1476] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1477] = {6'd18, 8'd0, 8'd150, 32'd0};//{'element_size': 2, 'src': 150, 'sequence': 140152842180512, 'op': 'memory_read_wait'}
instructions[1478] = {6'd19, 8'd147, 8'd150, 32'd0};//{'dest': 147, 'src': 150, 'sequence': 140152842180512, 'element_size': 2, 'op': 'memory_read'}
instructions[1479] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1480] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1481] = {6'd32, 8'd143, 8'd147, 32'd8};//{'src': 147, 'right': 8, 'dest': 143, 'signed': False, 'op': '>>', 'type': 'int', 'size': 2}
instructions[1482] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1483] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1484] = {6'd12, 8'd142, 8'd143, 32'd15};//{'src': 143, 'right': 15, 'dest': 142, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[1485] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1486] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1487] = {6'd33, 8'd141, 8'd142, 32'd1};//{'src': 142, 'right': 1, 'dest': 141, 'signed': False, 'op': '<<', 'type': 'int', 'size': 2}
instructions[1488] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1489] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1490] = {6'd3, 8'd67, 8'd141, 32'd0};//{'dest': 67, 'src': 141, 'op': 'move'}
instructions[1491] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1492] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1493] = {6'd3, 8'd142, 8'd67, 32'd0};//{'dest': 142, 'src': 67, 'op': 'move'}
instructions[1494] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1495] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1496] = {6'd14, 8'd141, 8'd142, 32'd7};//{'src': 142, 'right': 7, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1497] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1498] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1499] = {6'd3, 8'd68, 8'd141, 32'd0};//{'dest': 68, 'src': 141, 'op': 'move'}
instructions[1500] = {6'd0, 8'd142, 8'd0, 32'd8};//{'dest': 142, 'literal': 8, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1501] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1502] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1503] = {6'd11, 8'd143, 8'd142, 32'd65};//{'dest': 143, 'src': 142, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1504] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1505] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1506] = {6'd17, 8'd0, 8'd143, 32'd0};//{'element_size': 2, 'src': 143, 'sequence': 140152842894512, 'op': 'memory_read_request'}
instructions[1507] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1508] = {6'd18, 8'd0, 8'd143, 32'd0};//{'element_size': 2, 'src': 143, 'sequence': 140152842894512, 'op': 'memory_read_wait'}
instructions[1509] = {6'd19, 8'd141, 8'd143, 32'd0};//{'dest': 141, 'src': 143, 'sequence': 140152842894512, 'element_size': 2, 'op': 'memory_read'}
instructions[1510] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1511] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1512] = {6'd3, 8'd66, 8'd141, 32'd0};//{'dest': 66, 'src': 141, 'op': 'move'}
instructions[1513] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1514] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1515] = {6'd3, 8'd147, 8'd66, 32'd0};//{'dest': 147, 'src': 66, 'op': 'move'}
instructions[1516] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1517] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1518] = {6'd14, 8'd143, 8'd147, 32'd1};//{'src': 147, 'right': 1, 'dest': 143, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1519] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1520] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1521] = {6'd32, 8'd142, 8'd143, 32'd1};//{'src': 143, 'right': 1, 'dest': 142, 'signed': False, 'op': '>>', 'type': 'int', 'size': 2}
instructions[1522] = {6'd3, 8'd143, 8'd67, 32'd0};//{'dest': 143, 'src': 67, 'op': 'move'}
instructions[1523] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1524] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1525] = {6'd34, 8'd141, 8'd142, 32'd143};//{'srcb': 143, 'src': 142, 'dest': 141, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[1526] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1527] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1528] = {6'd3, 8'd69, 8'd141, 32'd0};//{'dest': 69, 'src': 141, 'op': 'move'}
instructions[1529] = {6'd3, 8'd143, 8'd68, 32'd0};//{'dest': 143, 'src': 68, 'op': 'move'}
instructions[1530] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1531] = {6'd3, 8'd147, 8'd69, 32'd0};//{'dest': 147, 'src': 69, 'op': 'move'}
instructions[1532] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1533] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1534] = {6'd11, 8'd142, 8'd143, 32'd147};//{'srcb': 147, 'src': 143, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1535] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1536] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1537] = {6'd35, 8'd141, 8'd142, 32'd1};//{'src': 142, 'right': 1, 'dest': 141, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[1538] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1539] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1540] = {6'd3, 8'd73, 8'd141, 32'd0};//{'dest': 73, 'src': 141, 'op': 'move'}
instructions[1541] = {6'd3, 8'd143, 8'd68, 32'd0};//{'dest': 143, 'src': 68, 'op': 'move'}
instructions[1542] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1543] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1544] = {6'd11, 8'd147, 8'd143, 32'd65};//{'dest': 147, 'src': 143, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1545] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1546] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1547] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842957312, 'op': 'memory_read_request'}
instructions[1548] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1549] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842957312, 'op': 'memory_read_wait'}
instructions[1550] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152842957312, 'element_size': 2, 'op': 'memory_read'}
instructions[1551] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1552] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1553] = {6'd25, 8'd141, 8'd142, 32'd2048};//{'src': 142, 'right': 2048, 'dest': 141, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1554] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1555] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1556] = {6'd13, 8'd0, 8'd141, 32'd1669};//{'src': 141, 'label': 1669, 'op': 'jmp_if_false'}
instructions[1557] = {6'd0, 8'd141, 8'd0, 32'd19};//{'dest': 141, 'literal': 19, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1558] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1559] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1560] = {6'd3, 8'd72, 8'd141, 32'd0};//{'dest': 72, 'src': 141, 'op': 'move'}
instructions[1561] = {6'd1, 8'd12, 8'd0, 32'd59};//{'dest': 12, 'label': 59, 'op': 'jmp_and_link'}
instructions[1562] = {6'd3, 8'd142, 8'd68, 32'd0};//{'dest': 142, 'src': 68, 'op': 'move'}
instructions[1563] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1564] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1565] = {6'd14, 8'd141, 8'd142, 32'd2};//{'src': 142, 'right': 2, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1566] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1567] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1568] = {6'd3, 8'd71, 8'd141, 32'd0};//{'dest': 71, 'src': 141, 'op': 'move'}
instructions[1569] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1570] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1571] = {6'd3, 8'd142, 8'd71, 32'd0};//{'dest': 142, 'src': 71, 'op': 'move'}
instructions[1572] = {6'd3, 8'd143, 8'd73, 32'd0};//{'dest': 143, 'src': 73, 'op': 'move'}
instructions[1573] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1574] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1575] = {6'd36, 8'd141, 8'd142, 32'd143};//{'srcb': 143, 'src': 142, 'dest': 141, 'signed': False, 'op': '<=', 'type': 'int', 'size': 2}
instructions[1576] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1577] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1578] = {6'd13, 8'd0, 8'd141, 32'd1612};//{'src': 141, 'label': 1612, 'op': 'jmp_if_false'}
instructions[1579] = {6'd3, 8'd142, 8'd71, 32'd0};//{'dest': 142, 'src': 71, 'op': 'move'}
instructions[1580] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1581] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1582] = {6'd11, 8'd143, 8'd142, 32'd65};//{'dest': 143, 'src': 142, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1583] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1584] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1585] = {6'd17, 8'd0, 8'd143, 32'd0};//{'element_size': 2, 'src': 143, 'sequence': 140152842925336, 'op': 'memory_read_request'}
instructions[1586] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1587] = {6'd18, 8'd0, 8'd143, 32'd0};//{'element_size': 2, 'src': 143, 'sequence': 140152842925336, 'op': 'memory_read_wait'}
instructions[1588] = {6'd19, 8'd141, 8'd143, 32'd0};//{'dest': 141, 'src': 143, 'sequence': 140152842925336, 'element_size': 2, 'op': 'memory_read'}
instructions[1589] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1590] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1591] = {6'd3, 8'd70, 8'd141, 32'd0};//{'dest': 70, 'src': 141, 'op': 'move'}
instructions[1592] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1593] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1594] = {6'd3, 8'd142, 8'd70, 32'd0};//{'dest': 142, 'src': 70, 'op': 'move'}
instructions[1595] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1596] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1597] = {6'd3, 8'd14, 8'd142, 32'd0};//{'dest': 14, 'src': 142, 'op': 'move'}
instructions[1598] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[1599] = {6'd3, 8'd141, 8'd70, 32'd0};//{'dest': 141, 'src': 70, 'op': 'move'}
instructions[1600] = {6'd3, 8'd142, 8'd72, 32'd0};//{'dest': 142, 'src': 72, 'op': 'move'}
instructions[1601] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1602] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1603] = {6'd11, 8'd143, 8'd142, 32'd10};//{'dest': 143, 'src': 142, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[1604] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1605] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1606] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[1607] = {6'd3, 8'd141, 8'd72, 32'd0};//{'dest': 141, 'src': 72, 'op': 'move'}
instructions[1608] = {6'd14, 8'd72, 8'd72, 32'd1};//{'src': 72, 'right': 1, 'dest': 72, 'signed': False, 'op': '+', 'size': 2}
instructions[1609] = {6'd3, 8'd141, 8'd71, 32'd0};//{'dest': 141, 'src': 71, 'op': 'move'}
instructions[1610] = {6'd14, 8'd71, 8'd71, 32'd1};//{'src': 71, 'right': 1, 'dest': 71, 'signed': False, 'op': '+', 'size': 2}
instructions[1611] = {6'd15, 8'd0, 8'd0, 32'd1569};//{'label': 1569, 'op': 'goto'}
instructions[1612] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1613] = {6'd0, 8'd142, 8'd0, 32'd17};//{'dest': 142, 'literal': 17, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1614] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1615] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1616] = {6'd27, 8'd143, 8'd142, 32'd10};//{'dest': 143, 'src': 142, 'srcb': 10, 'signed': True, 'op': '+'}
instructions[1617] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1618] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1619] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[1620] = {6'd1, 8'd15, 8'd0, 32'd100};//{'dest': 15, 'label': 100, 'op': 'jmp_and_link'}
instructions[1621] = {6'd3, 8'd141, 8'd16, 32'd0};//{'dest': 141, 'src': 16, 'op': 'move'}
instructions[1622] = {6'd0, 8'd142, 8'd0, 32'd18};//{'dest': 142, 'literal': 18, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1623] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1624] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1625] = {6'd11, 8'd143, 8'd142, 32'd10};//{'dest': 143, 'src': 142, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[1626] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1627] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1628] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[1629] = {6'd3, 8'd149, 8'd10, 32'd0};//{'dest': 149, 'src': 10, 'op': 'move'}
instructions[1630] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1631] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1632] = {6'd3, 8'd55, 8'd149, 32'd0};//{'dest': 55, 'src': 149, 'op': 'move'}
instructions[1633] = {6'd3, 8'd142, 8'd66, 32'd0};//{'dest': 142, 'src': 66, 'op': 'move'}
instructions[1634] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1635] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1636] = {6'd3, 8'd56, 8'd142, 32'd0};//{'dest': 56, 'src': 142, 'op': 'move'}
instructions[1637] = {6'd0, 8'd142, 8'd0, 32'd1};//{'dest': 142, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1638] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1639] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1640] = {6'd3, 8'd57, 8'd142, 32'd0};//{'dest': 57, 'src': 142, 'op': 'move'}
instructions[1641] = {6'd0, 8'd143, 8'd0, 32'd13};//{'dest': 143, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1642] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1643] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1644] = {6'd11, 8'd147, 8'd143, 32'd65};//{'dest': 147, 'src': 143, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1645] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1646] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1647] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842200128, 'op': 'memory_read_request'}
instructions[1648] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1649] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842200128, 'op': 'memory_read_wait'}
instructions[1650] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152842200128, 'element_size': 2, 'op': 'memory_read'}
instructions[1651] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1652] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1653] = {6'd3, 8'd58, 8'd142, 32'd0};//{'dest': 58, 'src': 142, 'op': 'move'}
instructions[1654] = {6'd0, 8'd143, 8'd0, 32'd14};//{'dest': 143, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1655] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1656] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1657] = {6'd11, 8'd147, 8'd143, 32'd65};//{'dest': 147, 'src': 143, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1658] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1659] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1660] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842200272, 'op': 'memory_read_request'}
instructions[1661] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1662] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842200272, 'op': 'memory_read_wait'}
instructions[1663] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152842200272, 'element_size': 2, 'op': 'memory_read'}
instructions[1664] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1665] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1666] = {6'd3, 8'd59, 8'd142, 32'd0};//{'dest': 59, 'src': 142, 'op': 'move'}
instructions[1667] = {6'd1, 8'd54, 8'd0, 32'd1140};//{'dest': 54, 'label': 1140, 'op': 'jmp_and_link'}
instructions[1668] = {6'd15, 8'd0, 8'd0, 32'd1669};//{'label': 1669, 'op': 'goto'}
instructions[1669] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1670] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1671] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1672] = {6'd3, 8'd64, 8'd141, 32'd0};//{'dest': 64, 'src': 141, 'op': 'move'}
instructions[1673] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1674] = {6'd15, 8'd0, 8'd0, 32'd1675};//{'label': 1675, 'op': 'goto'}
instructions[1675] = {6'd0, 8'd147, 8'd0, 32'd11};//{'dest': 147, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1676] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1677] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1678] = {6'd11, 8'd148, 8'd147, 32'd65};//{'dest': 148, 'src': 147, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1679] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1680] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1681] = {6'd17, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842200704, 'op': 'memory_read_request'}
instructions[1682] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1683] = {6'd18, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842200704, 'op': 'memory_read_wait'}
instructions[1684] = {6'd19, 8'd143, 8'd148, 32'd0};//{'dest': 143, 'src': 148, 'sequence': 140152842200704, 'element_size': 2, 'op': 'memory_read'}
instructions[1685] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1686] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1687] = {6'd12, 8'd142, 8'd143, 32'd255};//{'src': 143, 'right': 255, 'dest': 142, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[1688] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1689] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1690] = {6'd26, 8'd141, 8'd142, 32'd6};//{'src': 142, 'right': 6, 'dest': 141, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[1691] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1692] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1693] = {6'd13, 8'd0, 8'd141, 32'd1700};//{'src': 141, 'label': 1700, 'op': 'jmp_if_false'}
instructions[1694] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1695] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1696] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1697] = {6'd3, 8'd64, 8'd141, 32'd0};//{'dest': 64, 'src': 141, 'op': 'move'}
instructions[1698] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1699] = {6'd15, 8'd0, 8'd0, 32'd1700};//{'label': 1700, 'op': 'goto'}
instructions[1700] = {6'd3, 8'd141, 8'd74, 32'd0};//{'dest': 141, 'src': 74, 'op': 'move'}
instructions[1701] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1702] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1703] = {6'd3, 8'd64, 8'd141, 32'd0};//{'dest': 64, 'src': 141, 'op': 'move'}
instructions[1704] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1705] = {6'd0, 8'd100, 8'd0, 32'd17};//{'dest': 100, 'literal': 17, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1706] = {6'd0, 8'd101, 8'd0, 32'd0};//{'dest': 101, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1707] = {6'd0, 8'd102, 8'd0, 32'd0};//{'dest': 102, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1708] = {6'd0, 8'd103, 8'd0, 32'd0};//{'dest': 103, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1709] = {6'd3, 8'd141, 8'd77, 32'd0};//{'dest': 141, 'src': 77, 'op': 'move'}
instructions[1710] = {6'd3, 8'd147, 8'd100, 32'd0};//{'dest': 147, 'src': 100, 'op': 'move'}
instructions[1711] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1712] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1713] = {6'd14, 8'd142, 8'd147, 32'd0};//{'src': 147, 'right': 0, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1714] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1715] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1716] = {6'd11, 8'd143, 8'd142, 32'd98};//{'dest': 143, 'src': 142, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1717] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1718] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1719] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[1720] = {6'd3, 8'd141, 8'd78, 32'd0};//{'dest': 141, 'src': 78, 'op': 'move'}
instructions[1721] = {6'd3, 8'd147, 8'd100, 32'd0};//{'dest': 147, 'src': 100, 'op': 'move'}
instructions[1722] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1723] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1724] = {6'd14, 8'd142, 8'd147, 32'd1};//{'src': 147, 'right': 1, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1725] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1726] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1727] = {6'd11, 8'd143, 8'd142, 32'd98};//{'dest': 143, 'src': 142, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1728] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1729] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1730] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[1731] = {6'd0, 8'd147, 8'd0, 32'd1};//{'dest': 147, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1732] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1733] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1734] = {6'd11, 8'd148, 8'd147, 32'd79};//{'dest': 148, 'src': 147, 'srcb': 79, 'signed': False, 'op': '+'}
instructions[1735] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1736] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1737] = {6'd17, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152884526832, 'op': 'memory_read_request'}
instructions[1738] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1739] = {6'd18, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152884526832, 'op': 'memory_read_wait'}
instructions[1740] = {6'd19, 8'd141, 8'd148, 32'd0};//{'dest': 141, 'src': 148, 'sequence': 140152884526832, 'element_size': 2, 'op': 'memory_read'}
instructions[1741] = {6'd3, 8'd147, 8'd100, 32'd0};//{'dest': 147, 'src': 100, 'op': 'move'}
instructions[1742] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1743] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1744] = {6'd14, 8'd142, 8'd147, 32'd2};//{'src': 147, 'right': 2, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1745] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1746] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1747] = {6'd11, 8'd143, 8'd142, 32'd98};//{'dest': 143, 'src': 142, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1748] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1749] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1750] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[1751] = {6'd0, 8'd147, 8'd0, 32'd0};//{'dest': 147, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1752] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1753] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1754] = {6'd11, 8'd148, 8'd147, 32'd79};//{'dest': 148, 'src': 147, 'srcb': 79, 'signed': False, 'op': '+'}
instructions[1755] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1756] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1757] = {6'd17, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842223984, 'op': 'memory_read_request'}
instructions[1758] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1759] = {6'd18, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842223984, 'op': 'memory_read_wait'}
instructions[1760] = {6'd19, 8'd141, 8'd148, 32'd0};//{'dest': 141, 'src': 148, 'sequence': 140152842223984, 'element_size': 2, 'op': 'memory_read'}
instructions[1761] = {6'd3, 8'd147, 8'd100, 32'd0};//{'dest': 147, 'src': 100, 'op': 'move'}
instructions[1762] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1763] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1764] = {6'd14, 8'd142, 8'd147, 32'd3};//{'src': 147, 'right': 3, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1765] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1766] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1767] = {6'd11, 8'd143, 8'd142, 32'd98};//{'dest': 143, 'src': 142, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1768] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1769] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1770] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[1771] = {6'd0, 8'd147, 8'd0, 32'd1};//{'dest': 147, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1772] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1773] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1774] = {6'd11, 8'd148, 8'd147, 32'd81};//{'dest': 148, 'src': 147, 'srcb': 81, 'signed': False, 'op': '+'}
instructions[1775] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1776] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1777] = {6'd17, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842224560, 'op': 'memory_read_request'}
instructions[1778] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1779] = {6'd18, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842224560, 'op': 'memory_read_wait'}
instructions[1780] = {6'd19, 8'd141, 8'd148, 32'd0};//{'dest': 141, 'src': 148, 'sequence': 140152842224560, 'element_size': 2, 'op': 'memory_read'}
instructions[1781] = {6'd3, 8'd147, 8'd100, 32'd0};//{'dest': 147, 'src': 100, 'op': 'move'}
instructions[1782] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1783] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1784] = {6'd14, 8'd142, 8'd147, 32'd4};//{'src': 147, 'right': 4, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1785] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1786] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1787] = {6'd11, 8'd143, 8'd142, 32'd98};//{'dest': 143, 'src': 142, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1788] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1789] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1790] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[1791] = {6'd0, 8'd147, 8'd0, 32'd0};//{'dest': 147, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1792] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1793] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1794] = {6'd11, 8'd148, 8'd147, 32'd81};//{'dest': 148, 'src': 147, 'srcb': 81, 'signed': False, 'op': '+'}
instructions[1795] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1796] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1797] = {6'd17, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842225136, 'op': 'memory_read_request'}
instructions[1798] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1799] = {6'd18, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842225136, 'op': 'memory_read_wait'}
instructions[1800] = {6'd19, 8'd141, 8'd148, 32'd0};//{'dest': 141, 'src': 148, 'sequence': 140152842225136, 'element_size': 2, 'op': 'memory_read'}
instructions[1801] = {6'd3, 8'd147, 8'd100, 32'd0};//{'dest': 147, 'src': 100, 'op': 'move'}
instructions[1802] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1803] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1804] = {6'd14, 8'd142, 8'd147, 32'd5};//{'src': 147, 'right': 5, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1805] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1806] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1807] = {6'd11, 8'd143, 8'd142, 32'd98};//{'dest': 143, 'src': 142, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1808] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1809] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1810] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[1811] = {6'd0, 8'd141, 8'd0, 32'd20480};//{'dest': 141, 'literal': 20480, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1812] = {6'd3, 8'd147, 8'd100, 32'd0};//{'dest': 147, 'src': 100, 'op': 'move'}
instructions[1813] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1814] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1815] = {6'd14, 8'd142, 8'd147, 32'd6};//{'src': 147, 'right': 6, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1816] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1817] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1818] = {6'd27, 8'd143, 8'd142, 32'd98};//{'dest': 143, 'src': 142, 'srcb': 98, 'signed': True, 'op': '+'}
instructions[1819] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1820] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1821] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[1822] = {6'd3, 8'd141, 8'd82, 32'd0};//{'dest': 141, 'src': 82, 'op': 'move'}
instructions[1823] = {6'd3, 8'd147, 8'd100, 32'd0};//{'dest': 147, 'src': 100, 'op': 'move'}
instructions[1824] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1825] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1826] = {6'd14, 8'd142, 8'd147, 32'd7};//{'src': 147, 'right': 7, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1827] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1828] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1829] = {6'd11, 8'd143, 8'd142, 32'd98};//{'dest': 143, 'src': 142, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1830] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1831] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1832] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[1833] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1834] = {6'd3, 8'd147, 8'd100, 32'd0};//{'dest': 147, 'src': 100, 'op': 'move'}
instructions[1835] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1836] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1837] = {6'd14, 8'd142, 8'd147, 32'd8};//{'src': 147, 'right': 8, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1838] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1839] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1840] = {6'd27, 8'd143, 8'd142, 32'd98};//{'dest': 143, 'src': 142, 'srcb': 98, 'signed': True, 'op': '+'}
instructions[1841] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1842] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1843] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[1844] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1845] = {6'd3, 8'd147, 8'd100, 32'd0};//{'dest': 147, 'src': 100, 'op': 'move'}
instructions[1846] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1847] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1848] = {6'd14, 8'd142, 8'd147, 32'd9};//{'src': 147, 'right': 9, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1849] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1850] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1851] = {6'd27, 8'd143, 8'd142, 32'd98};//{'dest': 143, 'src': 142, 'srcb': 98, 'signed': True, 'op': '+'}
instructions[1852] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1853] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1854] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[1855] = {6'd3, 8'd141, 8'd83, 32'd0};//{'dest': 141, 'src': 83, 'op': 'move'}
instructions[1856] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1857] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1858] = {6'd13, 8'd0, 8'd141, 32'd1886};//{'src': 141, 'label': 1886, 'op': 'jmp_if_false'}
instructions[1859] = {6'd3, 8'd151, 8'd100, 32'd0};//{'dest': 151, 'src': 100, 'op': 'move'}
instructions[1860] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1861] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1862] = {6'd14, 8'd148, 8'd151, 32'd6};//{'src': 151, 'right': 6, 'dest': 148, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1863] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1864] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1865] = {6'd11, 8'd150, 8'd148, 32'd98};//{'dest': 150, 'src': 148, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1866] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1867] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1868] = {6'd17, 8'd0, 8'd150, 32'd0};//{'element_size': 2, 'src': 150, 'sequence': 140152884535664, 'op': 'memory_read_request'}
instructions[1869] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1870] = {6'd18, 8'd0, 8'd150, 32'd0};//{'element_size': 2, 'src': 150, 'sequence': 140152884535664, 'op': 'memory_read_wait'}
instructions[1871] = {6'd19, 8'd147, 8'd150, 32'd0};//{'dest': 147, 'src': 150, 'sequence': 140152884535664, 'element_size': 2, 'op': 'memory_read'}
instructions[1872] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1873] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1874] = {6'd37, 8'd141, 8'd147, 32'd1};//{'src': 147, 'right': 1, 'dest': 141, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1875] = {6'd3, 8'd147, 8'd100, 32'd0};//{'dest': 147, 'src': 100, 'op': 'move'}
instructions[1876] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1877] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1878] = {6'd14, 8'd142, 8'd147, 32'd6};//{'src': 147, 'right': 6, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1879] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1880] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1881] = {6'd11, 8'd143, 8'd142, 32'd98};//{'dest': 143, 'src': 142, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1882] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1883] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1884] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[1885] = {6'd15, 8'd0, 8'd0, 32'd1886};//{'label': 1886, 'op': 'goto'}
instructions[1886] = {6'd3, 8'd141, 8'd84, 32'd0};//{'dest': 141, 'src': 84, 'op': 'move'}
instructions[1887] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1888] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1889] = {6'd13, 8'd0, 8'd141, 32'd1917};//{'src': 141, 'label': 1917, 'op': 'jmp_if_false'}
instructions[1890] = {6'd3, 8'd151, 8'd100, 32'd0};//{'dest': 151, 'src': 100, 'op': 'move'}
instructions[1891] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1892] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1893] = {6'd14, 8'd148, 8'd151, 32'd6};//{'src': 151, 'right': 6, 'dest': 148, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1894] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1895] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1896] = {6'd11, 8'd150, 8'd148, 32'd98};//{'dest': 150, 'src': 148, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1897] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1898] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1899] = {6'd17, 8'd0, 8'd150, 32'd0};//{'element_size': 2, 'src': 150, 'sequence': 140152884536384, 'op': 'memory_read_request'}
instructions[1900] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1901] = {6'd18, 8'd0, 8'd150, 32'd0};//{'element_size': 2, 'src': 150, 'sequence': 140152884536384, 'op': 'memory_read_wait'}
instructions[1902] = {6'd19, 8'd147, 8'd150, 32'd0};//{'dest': 147, 'src': 150, 'sequence': 140152884536384, 'element_size': 2, 'op': 'memory_read'}
instructions[1903] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1904] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1905] = {6'd37, 8'd141, 8'd147, 32'd2};//{'src': 147, 'right': 2, 'dest': 141, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1906] = {6'd3, 8'd147, 8'd100, 32'd0};//{'dest': 147, 'src': 100, 'op': 'move'}
instructions[1907] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1908] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1909] = {6'd14, 8'd142, 8'd147, 32'd6};//{'src': 147, 'right': 6, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1910] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1911] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1912] = {6'd11, 8'd143, 8'd142, 32'd98};//{'dest': 143, 'src': 142, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1913] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1914] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1915] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[1916] = {6'd15, 8'd0, 8'd0, 32'd1917};//{'label': 1917, 'op': 'goto'}
instructions[1917] = {6'd3, 8'd141, 8'd85, 32'd0};//{'dest': 141, 'src': 85, 'op': 'move'}
instructions[1918] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1919] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1920] = {6'd13, 8'd0, 8'd141, 32'd1948};//{'src': 141, 'label': 1948, 'op': 'jmp_if_false'}
instructions[1921] = {6'd3, 8'd151, 8'd100, 32'd0};//{'dest': 151, 'src': 100, 'op': 'move'}
instructions[1922] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1923] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1924] = {6'd14, 8'd148, 8'd151, 32'd6};//{'src': 151, 'right': 6, 'dest': 148, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1925] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1926] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1927] = {6'd11, 8'd150, 8'd148, 32'd98};//{'dest': 150, 'src': 148, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1928] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1929] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1930] = {6'd17, 8'd0, 8'd150, 32'd0};//{'element_size': 2, 'src': 150, 'sequence': 140152884537104, 'op': 'memory_read_request'}
instructions[1931] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1932] = {6'd18, 8'd0, 8'd150, 32'd0};//{'element_size': 2, 'src': 150, 'sequence': 140152884537104, 'op': 'memory_read_wait'}
instructions[1933] = {6'd19, 8'd147, 8'd150, 32'd0};//{'dest': 147, 'src': 150, 'sequence': 140152884537104, 'element_size': 2, 'op': 'memory_read'}
instructions[1934] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1935] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1936] = {6'd37, 8'd141, 8'd147, 32'd4};//{'src': 147, 'right': 4, 'dest': 141, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1937] = {6'd3, 8'd147, 8'd100, 32'd0};//{'dest': 147, 'src': 100, 'op': 'move'}
instructions[1938] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1939] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1940] = {6'd14, 8'd142, 8'd147, 32'd6};//{'src': 147, 'right': 6, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1941] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1942] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1943] = {6'd11, 8'd143, 8'd142, 32'd98};//{'dest': 143, 'src': 142, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1944] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1945] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1946] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[1947] = {6'd15, 8'd0, 8'd0, 32'd1948};//{'label': 1948, 'op': 'goto'}
instructions[1948] = {6'd3, 8'd141, 8'd86, 32'd0};//{'dest': 141, 'src': 86, 'op': 'move'}
instructions[1949] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1950] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1951] = {6'd13, 8'd0, 8'd141, 32'd1979};//{'src': 141, 'label': 1979, 'op': 'jmp_if_false'}
instructions[1952] = {6'd3, 8'd151, 8'd100, 32'd0};//{'dest': 151, 'src': 100, 'op': 'move'}
instructions[1953] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1954] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1955] = {6'd14, 8'd148, 8'd151, 32'd6};//{'src': 151, 'right': 6, 'dest': 148, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1956] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1957] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1958] = {6'd11, 8'd150, 8'd148, 32'd98};//{'dest': 150, 'src': 148, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1959] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1960] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1961] = {6'd17, 8'd0, 8'd150, 32'd0};//{'element_size': 2, 'src': 150, 'sequence': 140152884537824, 'op': 'memory_read_request'}
instructions[1962] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1963] = {6'd18, 8'd0, 8'd150, 32'd0};//{'element_size': 2, 'src': 150, 'sequence': 140152884537824, 'op': 'memory_read_wait'}
instructions[1964] = {6'd19, 8'd147, 8'd150, 32'd0};//{'dest': 147, 'src': 150, 'sequence': 140152884537824, 'element_size': 2, 'op': 'memory_read'}
instructions[1965] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1966] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1967] = {6'd37, 8'd141, 8'd147, 32'd8};//{'src': 147, 'right': 8, 'dest': 141, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1968] = {6'd3, 8'd147, 8'd100, 32'd0};//{'dest': 147, 'src': 100, 'op': 'move'}
instructions[1969] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1970] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1971] = {6'd14, 8'd142, 8'd147, 32'd6};//{'src': 147, 'right': 6, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1972] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1973] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1974] = {6'd11, 8'd143, 8'd142, 32'd98};//{'dest': 143, 'src': 142, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1975] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1976] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1977] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[1978] = {6'd15, 8'd0, 8'd0, 32'd1979};//{'label': 1979, 'op': 'goto'}
instructions[1979] = {6'd3, 8'd141, 8'd87, 32'd0};//{'dest': 141, 'src': 87, 'op': 'move'}
instructions[1980] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1981] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1982] = {6'd13, 8'd0, 8'd141, 32'd2010};//{'src': 141, 'label': 2010, 'op': 'jmp_if_false'}
instructions[1983] = {6'd3, 8'd151, 8'd100, 32'd0};//{'dest': 151, 'src': 100, 'op': 'move'}
instructions[1984] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1985] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1986] = {6'd14, 8'd148, 8'd151, 32'd6};//{'src': 151, 'right': 6, 'dest': 148, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1987] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1988] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1989] = {6'd11, 8'd150, 8'd148, 32'd98};//{'dest': 150, 'src': 148, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1990] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1991] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1992] = {6'd17, 8'd0, 8'd150, 32'd0};//{'element_size': 2, 'src': 150, 'sequence': 140152884538544, 'op': 'memory_read_request'}
instructions[1993] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1994] = {6'd18, 8'd0, 8'd150, 32'd0};//{'element_size': 2, 'src': 150, 'sequence': 140152884538544, 'op': 'memory_read_wait'}
instructions[1995] = {6'd19, 8'd147, 8'd150, 32'd0};//{'dest': 147, 'src': 150, 'sequence': 140152884538544, 'element_size': 2, 'op': 'memory_read'}
instructions[1996] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1997] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1998] = {6'd37, 8'd141, 8'd147, 32'd16};//{'src': 147, 'right': 16, 'dest': 141, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1999] = {6'd3, 8'd147, 8'd100, 32'd0};//{'dest': 147, 'src': 100, 'op': 'move'}
instructions[2000] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2001] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2002] = {6'd14, 8'd142, 8'd147, 32'd6};//{'src': 147, 'right': 6, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2003] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2004] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2005] = {6'd11, 8'd143, 8'd142, 32'd98};//{'dest': 143, 'src': 142, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[2006] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2007] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2008] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[2009] = {6'd15, 8'd0, 8'd0, 32'd2010};//{'label': 2010, 'op': 'goto'}
instructions[2010] = {6'd3, 8'd141, 8'd88, 32'd0};//{'dest': 141, 'src': 88, 'op': 'move'}
instructions[2011] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2012] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2013] = {6'd13, 8'd0, 8'd141, 32'd2041};//{'src': 141, 'label': 2041, 'op': 'jmp_if_false'}
instructions[2014] = {6'd3, 8'd151, 8'd100, 32'd0};//{'dest': 151, 'src': 100, 'op': 'move'}
instructions[2015] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2016] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2017] = {6'd14, 8'd148, 8'd151, 32'd6};//{'src': 151, 'right': 6, 'dest': 148, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2018] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2019] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2020] = {6'd11, 8'd150, 8'd148, 32'd98};//{'dest': 150, 'src': 148, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[2021] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2022] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2023] = {6'd17, 8'd0, 8'd150, 32'd0};//{'element_size': 2, 'src': 150, 'sequence': 140152884539264, 'op': 'memory_read_request'}
instructions[2024] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2025] = {6'd18, 8'd0, 8'd150, 32'd0};//{'element_size': 2, 'src': 150, 'sequence': 140152884539264, 'op': 'memory_read_wait'}
instructions[2026] = {6'd19, 8'd147, 8'd150, 32'd0};//{'dest': 147, 'src': 150, 'sequence': 140152884539264, 'element_size': 2, 'op': 'memory_read'}
instructions[2027] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2028] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2029] = {6'd37, 8'd141, 8'd147, 32'd32};//{'src': 147, 'right': 32, 'dest': 141, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[2030] = {6'd3, 8'd147, 8'd100, 32'd0};//{'dest': 147, 'src': 100, 'op': 'move'}
instructions[2031] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2032] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2033] = {6'd14, 8'd142, 8'd147, 32'd6};//{'src': 147, 'right': 6, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2034] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2035] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2036] = {6'd11, 8'd143, 8'd142, 32'd98};//{'dest': 143, 'src': 142, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[2037] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2038] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2039] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[2040] = {6'd15, 8'd0, 8'd0, 32'd2041};//{'label': 2041, 'op': 'goto'}
instructions[2041] = {6'd1, 8'd12, 8'd0, 32'd59};//{'dest': 12, 'label': 59, 'op': 'jmp_and_link'}
instructions[2042] = {6'd0, 8'd142, 8'd0, 32'd49320};//{'dest': 142, 'literal': 49320, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2043] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2044] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2045] = {6'd3, 8'd14, 8'd142, 32'd0};//{'dest': 14, 'src': 142, 'op': 'move'}
instructions[2046] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[2047] = {6'd0, 8'd142, 8'd0, 32'd257};//{'dest': 142, 'literal': 257, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2048] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2049] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2050] = {6'd3, 8'd14, 8'd142, 32'd0};//{'dest': 14, 'src': 142, 'op': 'move'}
instructions[2051] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[2052] = {6'd3, 8'd142, 8'd75, 32'd0};//{'dest': 142, 'src': 75, 'op': 'move'}
instructions[2053] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2054] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2055] = {6'd3, 8'd14, 8'd142, 32'd0};//{'dest': 14, 'src': 142, 'op': 'move'}
instructions[2056] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[2057] = {6'd3, 8'd142, 8'd76, 32'd0};//{'dest': 142, 'src': 76, 'op': 'move'}
instructions[2058] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2059] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2060] = {6'd3, 8'd14, 8'd142, 32'd0};//{'dest': 14, 'src': 142, 'op': 'move'}
instructions[2061] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[2062] = {6'd0, 8'd142, 8'd0, 32'd6};//{'dest': 142, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2063] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2064] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2065] = {6'd3, 8'd14, 8'd142, 32'd0};//{'dest': 14, 'src': 142, 'op': 'move'}
instructions[2066] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[2067] = {6'd3, 8'd143, 8'd99, 32'd0};//{'dest': 143, 'src': 99, 'op': 'move'}
instructions[2068] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2069] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2070] = {6'd14, 8'd142, 8'd143, 32'd20};//{'src': 143, 'right': 20, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2071] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2072] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2073] = {6'd3, 8'd14, 8'd142, 32'd0};//{'dest': 14, 'src': 142, 'op': 'move'}
instructions[2074] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[2075] = {6'd3, 8'd147, 8'd99, 32'd0};//{'dest': 147, 'src': 99, 'op': 'move'}
instructions[2076] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2077] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2078] = {6'd14, 8'd143, 8'd147, 32'd20};//{'src': 147, 'right': 20, 'dest': 143, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2079] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2080] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2081] = {6'd14, 8'd142, 8'd143, 32'd1};//{'src': 143, 'right': 1, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2082] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2083] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2084] = {6'd32, 8'd141, 8'd142, 32'd1};//{'src': 142, 'right': 1, 'dest': 141, 'signed': False, 'op': '>>', 'type': 'int', 'size': 2}
instructions[2085] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2086] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2087] = {6'd3, 8'd101, 8'd141, 32'd0};//{'dest': 101, 'src': 141, 'op': 'move'}
instructions[2088] = {6'd3, 8'd141, 8'd100, 32'd0};//{'dest': 141, 'src': 100, 'op': 'move'}
instructions[2089] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2090] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2091] = {6'd3, 8'd102, 8'd141, 32'd0};//{'dest': 102, 'src': 141, 'op': 'move'}
instructions[2092] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2093] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2094] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2095] = {6'd3, 8'd103, 8'd141, 32'd0};//{'dest': 103, 'src': 141, 'op': 'move'}
instructions[2096] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2097] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2098] = {6'd3, 8'd142, 8'd103, 32'd0};//{'dest': 142, 'src': 103, 'op': 'move'}
instructions[2099] = {6'd3, 8'd143, 8'd101, 32'd0};//{'dest': 143, 'src': 101, 'op': 'move'}
instructions[2100] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2101] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2102] = {6'd20, 8'd141, 8'd142, 32'd143};//{'srcb': 143, 'src': 142, 'dest': 141, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[2103] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2104] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2105] = {6'd13, 8'd0, 8'd141, 32'd2125};//{'src': 141, 'label': 2125, 'op': 'jmp_if_false'}
instructions[2106] = {6'd3, 8'd143, 8'd102, 32'd0};//{'dest': 143, 'src': 102, 'op': 'move'}
instructions[2107] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2108] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2109] = {6'd11, 8'd147, 8'd143, 32'd98};//{'dest': 147, 'src': 143, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[2110] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2111] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2112] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842272992, 'op': 'memory_read_request'}
instructions[2113] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2114] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842272992, 'op': 'memory_read_wait'}
instructions[2115] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152842272992, 'element_size': 2, 'op': 'memory_read'}
instructions[2116] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2117] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2118] = {6'd3, 8'd14, 8'd142, 32'd0};//{'dest': 14, 'src': 142, 'op': 'move'}
instructions[2119] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[2120] = {6'd3, 8'd141, 8'd102, 32'd0};//{'dest': 141, 'src': 102, 'op': 'move'}
instructions[2121] = {6'd14, 8'd102, 8'd102, 32'd1};//{'src': 102, 'right': 1, 'dest': 102, 'signed': False, 'op': '+', 'size': 2}
instructions[2122] = {6'd3, 8'd141, 8'd103, 32'd0};//{'dest': 141, 'src': 103, 'op': 'move'}
instructions[2123] = {6'd14, 8'd103, 8'd103, 32'd1};//{'src': 103, 'right': 1, 'dest': 103, 'signed': False, 'op': '+', 'size': 2}
instructions[2124] = {6'd15, 8'd0, 8'd0, 32'd2096};//{'label': 2096, 'op': 'goto'}
instructions[2125] = {6'd1, 8'd15, 8'd0, 32'd100};//{'dest': 15, 'label': 100, 'op': 'jmp_and_link'}
instructions[2126] = {6'd3, 8'd141, 8'd16, 32'd0};//{'dest': 141, 'src': 16, 'op': 'move'}
instructions[2127] = {6'd3, 8'd147, 8'd100, 32'd0};//{'dest': 147, 'src': 100, 'op': 'move'}
instructions[2128] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2129] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2130] = {6'd14, 8'd142, 8'd147, 32'd8};//{'src': 147, 'right': 8, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2131] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2132] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2133] = {6'd11, 8'd143, 8'd142, 32'd98};//{'dest': 143, 'src': 142, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[2134] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2135] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2136] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[2137] = {6'd3, 8'd144, 8'd98, 32'd0};//{'dest': 144, 'src': 98, 'op': 'move'}
instructions[2138] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2139] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2140] = {6'd3, 8'd55, 8'd144, 32'd0};//{'dest': 55, 'src': 144, 'op': 'move'}
instructions[2141] = {6'd3, 8'd143, 8'd99, 32'd0};//{'dest': 143, 'src': 99, 'op': 'move'}
instructions[2142] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2143] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2144] = {6'd14, 8'd142, 8'd143, 32'd40};//{'src': 143, 'right': 40, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2145] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2146] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2147] = {6'd3, 8'd56, 8'd142, 32'd0};//{'dest': 56, 'src': 142, 'op': 'move'}
instructions[2148] = {6'd0, 8'd142, 8'd0, 32'd6};//{'dest': 142, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2149] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2150] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2151] = {6'd3, 8'd57, 8'd142, 32'd0};//{'dest': 57, 'src': 142, 'op': 'move'}
instructions[2152] = {6'd3, 8'd142, 8'd75, 32'd0};//{'dest': 142, 'src': 75, 'op': 'move'}
instructions[2153] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2154] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2155] = {6'd3, 8'd58, 8'd142, 32'd0};//{'dest': 58, 'src': 142, 'op': 'move'}
instructions[2156] = {6'd3, 8'd142, 8'd76, 32'd0};//{'dest': 142, 'src': 76, 'op': 'move'}
instructions[2157] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2158] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2159] = {6'd3, 8'd59, 8'd142, 32'd0};//{'dest': 59, 'src': 142, 'op': 'move'}
instructions[2160] = {6'd1, 8'd54, 8'd0, 32'd1140};//{'dest': 54, 'label': 1140, 'op': 'jmp_and_link'}
instructions[2161] = {6'd6, 8'd0, 8'd97, 32'd0};//{'src': 97, 'op': 'jmp_to_reg'}
instructions[2162] = {6'd0, 8'd109, 8'd0, 32'd0};//{'dest': 109, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2163] = {6'd0, 8'd110, 8'd0, 32'd0};//{'dest': 110, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2164] = {6'd0, 8'd111, 8'd0, 32'd0};//{'dest': 111, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2165] = {6'd0, 8'd112, 8'd0, 32'd0};//{'dest': 112, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2166] = {6'd0, 8'd113, 8'd0, 32'd0};//{'dest': 113, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2167] = {6'd0, 8'd114, 8'd0, 32'd0};//{'dest': 114, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2168] = {6'd3, 8'd144, 8'd108, 32'd0};//{'dest': 144, 'src': 108, 'op': 'move'}
instructions[2169] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2170] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2171] = {6'd3, 8'd65, 8'd144, 32'd0};//{'dest': 65, 'src': 144, 'op': 'move'}
instructions[2172] = {6'd1, 8'd63, 8'd0, 32'd1351};//{'dest': 63, 'label': 1351, 'op': 'jmp_and_link'}
instructions[2173] = {6'd3, 8'd141, 8'd64, 32'd0};//{'dest': 141, 'src': 64, 'op': 'move'}
instructions[2174] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2175] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2176] = {6'd3, 8'd109, 8'd141, 32'd0};//{'dest': 109, 'src': 141, 'op': 'move'}
instructions[2177] = {6'd0, 8'd148, 8'd0, 32'd7};//{'dest': 148, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2178] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2179] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2180] = {6'd11, 8'd150, 8'd148, 32'd108};//{'dest': 150, 'src': 148, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2181] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2182] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2183] = {6'd17, 8'd0, 8'd150, 32'd0};//{'element_size': 2, 'src': 150, 'sequence': 140152842295272, 'op': 'memory_read_request'}
instructions[2184] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2185] = {6'd18, 8'd0, 8'd150, 32'd0};//{'element_size': 2, 'src': 150, 'sequence': 140152842295272, 'op': 'memory_read_wait'}
instructions[2186] = {6'd19, 8'd147, 8'd150, 32'd0};//{'dest': 147, 'src': 150, 'sequence': 140152842295272, 'element_size': 2, 'op': 'memory_read'}
instructions[2187] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2188] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2189] = {6'd32, 8'd143, 8'd147, 32'd8};//{'src': 147, 'right': 8, 'dest': 143, 'signed': False, 'op': '>>', 'type': 'int', 'size': 2}
instructions[2190] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2191] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2192] = {6'd12, 8'd142, 8'd143, 32'd15};//{'src': 143, 'right': 15, 'dest': 142, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2193] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2194] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2195] = {6'd33, 8'd141, 8'd142, 32'd1};//{'src': 142, 'right': 1, 'dest': 141, 'signed': False, 'op': '<<', 'type': 'int', 'size': 2}
instructions[2196] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2197] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2198] = {6'd3, 8'd110, 8'd141, 32'd0};//{'dest': 110, 'src': 141, 'op': 'move'}
instructions[2199] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2200] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2201] = {6'd3, 8'd142, 8'd110, 32'd0};//{'dest': 142, 'src': 110, 'op': 'move'}
instructions[2202] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2203] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2204] = {6'd14, 8'd141, 8'd142, 32'd7};//{'src': 142, 'right': 7, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2205] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2206] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2207] = {6'd3, 8'd111, 8'd141, 32'd0};//{'dest': 111, 'src': 141, 'op': 'move'}
instructions[2208] = {6'd0, 8'd142, 8'd0, 32'd8};//{'dest': 142, 'literal': 8, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2209] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2210] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2211] = {6'd11, 8'd143, 8'd142, 32'd108};//{'dest': 143, 'src': 142, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2212] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2213] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2214] = {6'd17, 8'd0, 8'd143, 32'd0};//{'element_size': 2, 'src': 143, 'sequence': 140152884524456, 'op': 'memory_read_request'}
instructions[2215] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2216] = {6'd18, 8'd0, 8'd143, 32'd0};//{'element_size': 2, 'src': 143, 'sequence': 140152884524456, 'op': 'memory_read_wait'}
instructions[2217] = {6'd19, 8'd141, 8'd143, 32'd0};//{'dest': 141, 'src': 143, 'sequence': 140152884524456, 'element_size': 2, 'op': 'memory_read'}
instructions[2218] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2219] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2220] = {6'd3, 8'd112, 8'd141, 32'd0};//{'dest': 112, 'src': 141, 'op': 'move'}
instructions[2221] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2222] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2223] = {6'd3, 8'd142, 8'd112, 32'd0};//{'dest': 142, 'src': 112, 'op': 'move'}
instructions[2224] = {6'd3, 8'd147, 8'd110, 32'd0};//{'dest': 147, 'src': 110, 'op': 'move'}
instructions[2225] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2226] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2227] = {6'd33, 8'd143, 8'd147, 32'd1};//{'src': 147, 'right': 1, 'dest': 143, 'signed': False, 'op': '<<', 'type': 'int', 'size': 2}
instructions[2228] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2229] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2230] = {6'd34, 8'd141, 8'd142, 32'd143};//{'srcb': 143, 'src': 142, 'dest': 141, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[2231] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2232] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2233] = {6'd3, 8'd113, 8'd141, 32'd0};//{'dest': 113, 'src': 141, 'op': 'move'}
instructions[2234] = {6'd3, 8'd150, 8'd111, 32'd0};//{'dest': 150, 'src': 111, 'op': 'move'}
instructions[2235] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2236] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2237] = {6'd14, 8'd147, 8'd150, 32'd6};//{'src': 150, 'right': 6, 'dest': 147, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2238] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2239] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2240] = {6'd11, 8'd148, 8'd147, 32'd108};//{'dest': 148, 'src': 147, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2241] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2242] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2243] = {6'd17, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842310144, 'op': 'memory_read_request'}
instructions[2244] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2245] = {6'd18, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842310144, 'op': 'memory_read_wait'}
instructions[2246] = {6'd19, 8'd143, 8'd148, 32'd0};//{'dest': 143, 'src': 148, 'sequence': 140152842310144, 'element_size': 2, 'op': 'memory_read'}
instructions[2247] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2248] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2249] = {6'd12, 8'd142, 8'd143, 32'd61440};//{'src': 143, 'right': 61440, 'dest': 142, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2250] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2251] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2252] = {6'd32, 8'd141, 8'd142, 32'd10};//{'src': 142, 'right': 10, 'dest': 141, 'signed': False, 'op': '>>', 'type': 'int', 'size': 2}
instructions[2253] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2254] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2255] = {6'd3, 8'd114, 8'd141, 32'd0};//{'dest': 114, 'src': 141, 'op': 'move'}
instructions[2256] = {6'd3, 8'd142, 8'd113, 32'd0};//{'dest': 142, 'src': 113, 'op': 'move'}
instructions[2257] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2258] = {6'd3, 8'd143, 8'd114, 32'd0};//{'dest': 143, 'src': 114, 'op': 'move'}
instructions[2259] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2260] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2261] = {6'd34, 8'd141, 8'd142, 32'd143};//{'srcb': 143, 'src': 142, 'dest': 141, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[2262] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2263] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2264] = {6'd3, 8'd104, 8'd141, 32'd0};//{'dest': 104, 'src': 141, 'op': 'move'}
instructions[2265] = {6'd3, 8'd142, 8'd111, 32'd0};//{'dest': 142, 'src': 111, 'op': 'move'}
instructions[2266] = {6'd3, 8'd147, 8'd114, 32'd0};//{'dest': 147, 'src': 114, 'op': 'move'}
instructions[2267] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2268] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2269] = {6'd32, 8'd143, 8'd147, 32'd1};//{'src': 147, 'right': 1, 'dest': 143, 'signed': False, 'op': '>>', 'type': 'int', 'size': 2}
instructions[2270] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2271] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2272] = {6'd11, 8'd141, 8'd142, 32'd143};//{'srcb': 143, 'src': 142, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2273] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2274] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2275] = {6'd3, 8'd105, 8'd141, 32'd0};//{'dest': 105, 'src': 141, 'op': 'move'}
instructions[2276] = {6'd3, 8'd147, 8'd111, 32'd0};//{'dest': 147, 'src': 111, 'op': 'move'}
instructions[2277] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2278] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2279] = {6'd14, 8'd142, 8'd147, 32'd0};//{'src': 147, 'right': 0, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2280] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2281] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2282] = {6'd11, 8'd143, 8'd142, 32'd108};//{'dest': 143, 'src': 142, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2283] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2284] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2285] = {6'd17, 8'd0, 8'd143, 32'd0};//{'element_size': 2, 'src': 143, 'sequence': 140152842274288, 'op': 'memory_read_request'}
instructions[2286] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2287] = {6'd18, 8'd0, 8'd143, 32'd0};//{'element_size': 2, 'src': 143, 'sequence': 140152842274288, 'op': 'memory_read_wait'}
instructions[2288] = {6'd19, 8'd141, 8'd143, 32'd0};//{'dest': 141, 'src': 143, 'sequence': 140152842274288, 'element_size': 2, 'op': 'memory_read'}
instructions[2289] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2290] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2291] = {6'd3, 8'd89, 8'd141, 32'd0};//{'dest': 89, 'src': 141, 'op': 'move'}
instructions[2292] = {6'd3, 8'd147, 8'd111, 32'd0};//{'dest': 147, 'src': 111, 'op': 'move'}
instructions[2293] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2294] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2295] = {6'd14, 8'd142, 8'd147, 32'd1};//{'src': 147, 'right': 1, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2296] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2297] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2298] = {6'd11, 8'd143, 8'd142, 32'd108};//{'dest': 143, 'src': 142, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2299] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2300] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2301] = {6'd17, 8'd0, 8'd143, 32'd0};//{'element_size': 2, 'src': 143, 'sequence': 140152842275296, 'op': 'memory_read_request'}
instructions[2302] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2303] = {6'd18, 8'd0, 8'd143, 32'd0};//{'element_size': 2, 'src': 143, 'sequence': 140152842275296, 'op': 'memory_read_wait'}
instructions[2304] = {6'd19, 8'd141, 8'd143, 32'd0};//{'dest': 141, 'src': 143, 'sequence': 140152842275296, 'element_size': 2, 'op': 'memory_read'}
instructions[2305] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2306] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2307] = {6'd3, 8'd90, 8'd141, 32'd0};//{'dest': 90, 'src': 141, 'op': 'move'}
instructions[2308] = {6'd3, 8'd150, 8'd111, 32'd0};//{'dest': 150, 'src': 111, 'op': 'move'}
instructions[2309] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2310] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2311] = {6'd14, 8'd147, 8'd150, 32'd2};//{'src': 150, 'right': 2, 'dest': 147, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2312] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2313] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2314] = {6'd11, 8'd148, 8'd147, 32'd108};//{'dest': 148, 'src': 147, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2315] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2316] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2317] = {6'd17, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842274936, 'op': 'memory_read_request'}
instructions[2318] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2319] = {6'd18, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842274936, 'op': 'memory_read_wait'}
instructions[2320] = {6'd19, 8'd141, 8'd148, 32'd0};//{'dest': 141, 'src': 148, 'sequence': 140152842274936, 'element_size': 2, 'op': 'memory_read'}
instructions[2321] = {6'd0, 8'd142, 8'd0, 32'd1};//{'dest': 142, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2322] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2323] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2324] = {6'd11, 8'd143, 8'd142, 32'd91};//{'dest': 143, 'src': 142, 'srcb': 91, 'signed': False, 'op': '+'}
instructions[2325] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2326] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2327] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[2328] = {6'd3, 8'd150, 8'd111, 32'd0};//{'dest': 150, 'src': 111, 'op': 'move'}
instructions[2329] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2330] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2331] = {6'd14, 8'd147, 8'd150, 32'd3};//{'src': 150, 'right': 3, 'dest': 147, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2332] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2333] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2334] = {6'd11, 8'd148, 8'd147, 32'd108};//{'dest': 148, 'src': 147, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2335] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2336] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2337] = {6'd17, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842275512, 'op': 'memory_read_request'}
instructions[2338] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2339] = {6'd18, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842275512, 'op': 'memory_read_wait'}
instructions[2340] = {6'd19, 8'd141, 8'd148, 32'd0};//{'dest': 141, 'src': 148, 'sequence': 140152842275512, 'element_size': 2, 'op': 'memory_read'}
instructions[2341] = {6'd0, 8'd142, 8'd0, 32'd0};//{'dest': 142, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2342] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2343] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2344] = {6'd11, 8'd143, 8'd142, 32'd91};//{'dest': 143, 'src': 142, 'srcb': 91, 'signed': False, 'op': '+'}
instructions[2345] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2346] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2347] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[2348] = {6'd3, 8'd150, 8'd111, 32'd0};//{'dest': 150, 'src': 111, 'op': 'move'}
instructions[2349] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2350] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2351] = {6'd14, 8'd147, 8'd150, 32'd4};//{'src': 150, 'right': 4, 'dest': 147, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2352] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2353] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2354] = {6'd11, 8'd148, 8'd147, 32'd108};//{'dest': 148, 'src': 147, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2355] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2356] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2357] = {6'd17, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842276520, 'op': 'memory_read_request'}
instructions[2358] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2359] = {6'd18, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842276520, 'op': 'memory_read_wait'}
instructions[2360] = {6'd19, 8'd141, 8'd148, 32'd0};//{'dest': 141, 'src': 148, 'sequence': 140152842276520, 'element_size': 2, 'op': 'memory_read'}
instructions[2361] = {6'd0, 8'd142, 8'd0, 32'd1};//{'dest': 142, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2362] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2363] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2364] = {6'd11, 8'd143, 8'd142, 32'd92};//{'dest': 143, 'src': 142, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[2365] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2366] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2367] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[2368] = {6'd3, 8'd150, 8'd111, 32'd0};//{'dest': 150, 'src': 111, 'op': 'move'}
instructions[2369] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2370] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2371] = {6'd14, 8'd147, 8'd150, 32'd5};//{'src': 150, 'right': 5, 'dest': 147, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2372] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2373] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2374] = {6'd11, 8'd148, 8'd147, 32'd108};//{'dest': 148, 'src': 147, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2375] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2376] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2377] = {6'd17, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842276736, 'op': 'memory_read_request'}
instructions[2378] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2379] = {6'd18, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842276736, 'op': 'memory_read_wait'}
instructions[2380] = {6'd19, 8'd141, 8'd148, 32'd0};//{'dest': 141, 'src': 148, 'sequence': 140152842276736, 'element_size': 2, 'op': 'memory_read'}
instructions[2381] = {6'd0, 8'd142, 8'd0, 32'd0};//{'dest': 142, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2382] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2383] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2384] = {6'd11, 8'd143, 8'd142, 32'd92};//{'dest': 143, 'src': 142, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[2385] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2386] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2387] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[2388] = {6'd3, 8'd147, 8'd111, 32'd0};//{'dest': 147, 'src': 111, 'op': 'move'}
instructions[2389] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2390] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2391] = {6'd14, 8'd142, 8'd147, 32'd7};//{'src': 147, 'right': 7, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2392] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2393] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2394] = {6'd11, 8'd143, 8'd142, 32'd108};//{'dest': 143, 'src': 142, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2395] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2396] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2397] = {6'd17, 8'd0, 8'd143, 32'd0};//{'element_size': 2, 'src': 143, 'sequence': 140152842296784, 'op': 'memory_read_request'}
instructions[2398] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2399] = {6'd18, 8'd0, 8'd143, 32'd0};//{'element_size': 2, 'src': 143, 'sequence': 140152842296784, 'op': 'memory_read_wait'}
instructions[2400] = {6'd19, 8'd141, 8'd143, 32'd0};//{'dest': 141, 'src': 143, 'sequence': 140152842296784, 'element_size': 2, 'op': 'memory_read'}
instructions[2401] = {6'd3, 8'd148, 8'd111, 32'd0};//{'dest': 148, 'src': 111, 'op': 'move'}
instructions[2402] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2403] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2404] = {6'd14, 8'd143, 8'd148, 32'd6};//{'src': 148, 'right': 6, 'dest': 143, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2405] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2406] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2407] = {6'd11, 8'd147, 8'd143, 32'd108};//{'dest': 147, 'src': 143, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2408] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2409] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2410] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842296496, 'op': 'memory_read_request'}
instructions[2411] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2412] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842296496, 'op': 'memory_read_wait'}
instructions[2413] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152842296496, 'element_size': 2, 'op': 'memory_read'}
instructions[2414] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2415] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2416] = {6'd12, 8'd141, 8'd142, 32'd1};//{'src': 142, 'right': 1, 'dest': 141, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2417] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2418] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2419] = {6'd3, 8'd93, 8'd141, 32'd0};//{'dest': 93, 'src': 141, 'op': 'move'}
instructions[2420] = {6'd3, 8'd148, 8'd111, 32'd0};//{'dest': 148, 'src': 111, 'op': 'move'}
instructions[2421] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2422] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2423] = {6'd14, 8'd143, 8'd148, 32'd6};//{'src': 148, 'right': 6, 'dest': 143, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2424] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2425] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2426] = {6'd11, 8'd147, 8'd143, 32'd108};//{'dest': 147, 'src': 143, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2427] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2428] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2429] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842293328, 'op': 'memory_read_request'}
instructions[2430] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2431] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842293328, 'op': 'memory_read_wait'}
instructions[2432] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152842293328, 'element_size': 2, 'op': 'memory_read'}
instructions[2433] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2434] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2435] = {6'd12, 8'd141, 8'd142, 32'd2};//{'src': 142, 'right': 2, 'dest': 141, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2436] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2437] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2438] = {6'd3, 8'd94, 8'd141, 32'd0};//{'dest': 94, 'src': 141, 'op': 'move'}
instructions[2439] = {6'd3, 8'd148, 8'd111, 32'd0};//{'dest': 148, 'src': 111, 'op': 'move'}
instructions[2440] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2441] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2442] = {6'd14, 8'd143, 8'd148, 32'd6};//{'src': 148, 'right': 6, 'dest': 143, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2443] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2444] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2445] = {6'd11, 8'd147, 8'd143, 32'd108};//{'dest': 147, 'src': 143, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2446] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2447] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2448] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842293544, 'op': 'memory_read_request'}
instructions[2449] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2450] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842293544, 'op': 'memory_read_wait'}
instructions[2451] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152842293544, 'element_size': 2, 'op': 'memory_read'}
instructions[2452] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2453] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2454] = {6'd12, 8'd141, 8'd142, 32'd4};//{'src': 142, 'right': 4, 'dest': 141, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2455] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2456] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2457] = {6'd3, 8'd95, 8'd141, 32'd0};//{'dest': 95, 'src': 141, 'op': 'move'}
instructions[2458] = {6'd3, 8'd148, 8'd111, 32'd0};//{'dest': 148, 'src': 111, 'op': 'move'}
instructions[2459] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2460] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2461] = {6'd14, 8'd143, 8'd148, 32'd6};//{'src': 148, 'right': 6, 'dest': 143, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2462] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2463] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2464] = {6'd11, 8'd147, 8'd143, 32'd108};//{'dest': 147, 'src': 143, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2465] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2466] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2467] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842294984, 'op': 'memory_read_request'}
instructions[2468] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2469] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842294984, 'op': 'memory_read_wait'}
instructions[2470] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152842294984, 'element_size': 2, 'op': 'memory_read'}
instructions[2471] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2472] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2473] = {6'd12, 8'd141, 8'd142, 32'd8};//{'src': 142, 'right': 8, 'dest': 141, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2474] = {6'd3, 8'd148, 8'd111, 32'd0};//{'dest': 148, 'src': 111, 'op': 'move'}
instructions[2475] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2476] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2477] = {6'd14, 8'd143, 8'd148, 32'd6};//{'src': 148, 'right': 6, 'dest': 143, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2478] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2479] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2480] = {6'd11, 8'd147, 8'd143, 32'd108};//{'dest': 147, 'src': 143, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2481] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2482] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2483] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842295056, 'op': 'memory_read_request'}
instructions[2484] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2485] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842295056, 'op': 'memory_read_wait'}
instructions[2486] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152842295056, 'element_size': 2, 'op': 'memory_read'}
instructions[2487] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2488] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2489] = {6'd12, 8'd141, 8'd142, 32'd16};//{'src': 142, 'right': 16, 'dest': 141, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2490] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2491] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2492] = {6'd3, 8'd96, 8'd141, 32'd0};//{'dest': 96, 'src': 141, 'op': 'move'}
instructions[2493] = {6'd3, 8'd148, 8'd111, 32'd0};//{'dest': 148, 'src': 111, 'op': 'move'}
instructions[2494] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2495] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2496] = {6'd14, 8'd143, 8'd148, 32'd6};//{'src': 148, 'right': 6, 'dest': 143, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2497] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2498] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2499] = {6'd11, 8'd147, 8'd143, 32'd108};//{'dest': 147, 'src': 143, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2500] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2501] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2502] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842310648, 'op': 'memory_read_request'}
instructions[2503] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2504] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842310648, 'op': 'memory_read_wait'}
instructions[2505] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152842310648, 'element_size': 2, 'op': 'memory_read'}
instructions[2506] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2507] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2508] = {6'd12, 8'd141, 8'd142, 32'd32};//{'src': 142, 'right': 32, 'dest': 141, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2509] = {6'd3, 8'd141, 8'd109, 32'd0};//{'dest': 141, 'src': 109, 'op': 'move'}
instructions[2510] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2511] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2512] = {6'd3, 8'd107, 8'd141, 32'd0};//{'dest': 107, 'src': 141, 'op': 'move'}
instructions[2513] = {6'd6, 8'd0, 8'd106, 32'd0};//{'src': 106, 'op': 'jmp_to_reg'}
instructions[2514] = {6'd0, 8'd119, 8'd0, 32'd0};//{'dest': 119, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2515] = {6'd0, 8'd120, 8'd0, 32'd0};//{'dest': 120, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2516] = {6'd3, 8'd141, 8'd117, 32'd0};//{'dest': 141, 'src': 117, 'op': 'move'}
instructions[2517] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2518] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2519] = {6'd3, 8'd120, 8'd141, 32'd0};//{'dest': 120, 'src': 141, 'op': 'move'}
instructions[2520] = {6'd3, 8'd142, 8'd118, 32'd0};//{'dest': 142, 'src': 118, 'op': 'move'}
instructions[2521] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2522] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2523] = {6'd3, 8'd3, 8'd142, 32'd0};//{'dest': 3, 'src': 142, 'op': 'move'}
instructions[2524] = {6'd1, 8'd2, 8'd0, 32'd39};//{'dest': 2, 'label': 39, 'op': 'jmp_and_link'}
instructions[2525] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2526] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2527] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2528] = {6'd3, 8'd119, 8'd141, 32'd0};//{'dest': 119, 'src': 141, 'op': 'move'}
instructions[2529] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2530] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2531] = {6'd3, 8'd142, 8'd119, 32'd0};//{'dest': 142, 'src': 119, 'op': 'move'}
instructions[2532] = {6'd3, 8'd143, 8'd118, 32'd0};//{'dest': 143, 'src': 118, 'op': 'move'}
instructions[2533] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2534] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2535] = {6'd20, 8'd141, 8'd142, 32'd143};//{'srcb': 143, 'src': 142, 'dest': 141, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[2536] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2537] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2538] = {6'd13, 8'd0, 8'd141, 32'd2563};//{'src': 141, 'label': 2563, 'op': 'jmp_if_false'}
instructions[2539] = {6'd3, 8'd143, 8'd120, 32'd0};//{'dest': 143, 'src': 120, 'op': 'move'}
instructions[2540] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2541] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2542] = {6'd11, 8'd147, 8'd143, 32'd116};//{'dest': 147, 'src': 143, 'srcb': 116, 'signed': False, 'op': '+'}
instructions[2543] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2544] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2545] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842347080, 'op': 'memory_read_request'}
instructions[2546] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2547] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842347080, 'op': 'memory_read_wait'}
instructions[2548] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152842347080, 'element_size': 2, 'op': 'memory_read'}
instructions[2549] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2550] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2551] = {6'd3, 8'd3, 8'd142, 32'd0};//{'dest': 3, 'src': 142, 'op': 'move'}
instructions[2552] = {6'd1, 8'd2, 8'd0, 32'd39};//{'dest': 2, 'label': 39, 'op': 'jmp_and_link'}
instructions[2553] = {6'd3, 8'd141, 8'd120, 32'd0};//{'dest': 141, 'src': 120, 'op': 'move'}
instructions[2554] = {6'd14, 8'd120, 8'd120, 32'd1};//{'src': 120, 'right': 1, 'dest': 120, 'signed': False, 'op': '+', 'size': 2}
instructions[2555] = {6'd3, 8'd142, 8'd119, 32'd0};//{'dest': 142, 'src': 119, 'op': 'move'}
instructions[2556] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2557] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2558] = {6'd14, 8'd141, 8'd142, 32'd2};//{'src': 142, 'right': 2, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2559] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2560] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2561] = {6'd3, 8'd119, 8'd141, 32'd0};//{'dest': 119, 'src': 141, 'op': 'move'}
instructions[2562] = {6'd15, 8'd0, 8'd0, 32'd2529};//{'label': 2529, 'op': 'goto'}
instructions[2563] = {6'd6, 8'd0, 8'd115, 32'd0};//{'src': 115, 'op': 'jmp_to_reg'}
instructions[2564] = {6'd0, 8'd125, 8'd0, 32'd0};//{'dest': 125, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2565] = {6'd0, 8'd126, 8'd0, 32'd0};//{'dest': 126, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2566] = {6'd0, 8'd127, 8'd0, 32'd0};//{'dest': 127, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2567] = {6'd38, 8'd142, 8'd0, 32'd0};//{'dest': 142, 'input': 'socket', 'op': 'ready'}
instructions[2568] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2569] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2570] = {6'd39, 8'd141, 8'd142, 32'd0};//{'src': 142, 'right': 0, 'dest': 141, 'signed': True, 'op': '==', 'type': 'int', 'size': 2}
instructions[2571] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2572] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2573] = {6'd13, 8'd0, 8'd141, 32'd2580};//{'src': 141, 'label': 2580, 'op': 'jmp_if_false'}
instructions[2574] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2575] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2576] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2577] = {6'd3, 8'd122, 8'd141, 32'd0};//{'dest': 122, 'src': 141, 'op': 'move'}
instructions[2578] = {6'd6, 8'd0, 8'd121, 32'd0};//{'src': 121, 'op': 'jmp_to_reg'}
instructions[2579] = {6'd15, 8'd0, 8'd0, 32'd2580};//{'label': 2580, 'op': 'goto'}
instructions[2580] = {6'd3, 8'd141, 8'd124, 32'd0};//{'dest': 141, 'src': 124, 'op': 'move'}
instructions[2581] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2582] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2583] = {6'd3, 8'd126, 8'd141, 32'd0};//{'dest': 126, 'src': 141, 'op': 'move'}
instructions[2584] = {6'd1, 8'd8, 8'd0, 32'd54};//{'dest': 8, 'label': 54, 'op': 'jmp_and_link'}
instructions[2585] = {6'd3, 8'd141, 8'd9, 32'd0};//{'dest': 141, 'src': 9, 'op': 'move'}
instructions[2586] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2587] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2588] = {6'd3, 8'd127, 8'd141, 32'd0};//{'dest': 127, 'src': 141, 'op': 'move'}
instructions[2589] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2590] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2591] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2592] = {6'd3, 8'd125, 8'd141, 32'd0};//{'dest': 125, 'src': 141, 'op': 'move'}
instructions[2593] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2594] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2595] = {6'd3, 8'd142, 8'd125, 32'd0};//{'dest': 142, 'src': 125, 'op': 'move'}
instructions[2596] = {6'd3, 8'd143, 8'd127, 32'd0};//{'dest': 143, 'src': 127, 'op': 'move'}
instructions[2597] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2598] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2599] = {6'd20, 8'd141, 8'd142, 32'd143};//{'srcb': 143, 'src': 142, 'dest': 141, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[2600] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2601] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2602] = {6'd13, 8'd0, 8'd141, 32'd2622};//{'src': 141, 'label': 2622, 'op': 'jmp_if_false'}
instructions[2603] = {6'd1, 8'd8, 8'd0, 32'd54};//{'dest': 8, 'label': 54, 'op': 'jmp_and_link'}
instructions[2604] = {6'd3, 8'd141, 8'd9, 32'd0};//{'dest': 141, 'src': 9, 'op': 'move'}
instructions[2605] = {6'd3, 8'd142, 8'd126, 32'd0};//{'dest': 142, 'src': 126, 'op': 'move'}
instructions[2606] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2607] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2608] = {6'd11, 8'd143, 8'd142, 32'd123};//{'dest': 143, 'src': 142, 'srcb': 123, 'signed': False, 'op': '+'}
instructions[2609] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2610] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2611] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[2612] = {6'd3, 8'd141, 8'd126, 32'd0};//{'dest': 141, 'src': 126, 'op': 'move'}
instructions[2613] = {6'd14, 8'd126, 8'd126, 32'd1};//{'src': 126, 'right': 1, 'dest': 126, 'signed': False, 'op': '+', 'size': 2}
instructions[2614] = {6'd3, 8'd142, 8'd125, 32'd0};//{'dest': 142, 'src': 125, 'op': 'move'}
instructions[2615] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2616] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2617] = {6'd14, 8'd141, 8'd142, 32'd2};//{'src': 142, 'right': 2, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2618] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2619] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2620] = {6'd3, 8'd125, 8'd141, 32'd0};//{'dest': 125, 'src': 141, 'op': 'move'}
instructions[2621] = {6'd15, 8'd0, 8'd0, 32'd2593};//{'label': 2593, 'op': 'goto'}
instructions[2622] = {6'd3, 8'd141, 8'd127, 32'd0};//{'dest': 141, 'src': 127, 'op': 'move'}
instructions[2623] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2624] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2625] = {6'd3, 8'd122, 8'd141, 32'd0};//{'dest': 122, 'src': 141, 'op': 'move'}
instructions[2626] = {6'd6, 8'd0, 8'd121, 32'd0};//{'src': 121, 'op': 'jmp_to_reg'}
instructions[2627] = {6'd0, 8'd129, 8'd0, 32'd0};//{'dest': 129, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2628] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2629] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2630] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2631] = {6'd3, 8'd129, 8'd141, 32'd0};//{'dest': 129, 'src': 141, 'op': 'move'}
instructions[2632] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2633] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2634] = {6'd3, 8'd142, 8'd129, 32'd0};//{'dest': 142, 'src': 129, 'op': 'move'}
instructions[2635] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2636] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2637] = {6'd28, 8'd141, 8'd142, 32'd512};//{'src': 142, 'right': 512, 'dest': 141, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[2638] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2639] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2640] = {6'd13, 8'd0, 8'd141, 32'd2652};//{'src': 141, 'label': 2652, 'op': 'jmp_if_false'}
instructions[2641] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2642] = {6'd3, 8'd142, 8'd129, 32'd0};//{'dest': 142, 'src': 129, 'op': 'move'}
instructions[2643] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2644] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2645] = {6'd27, 8'd143, 8'd142, 32'd10};//{'dest': 143, 'src': 142, 'srcb': 10, 'signed': True, 'op': '+'}
instructions[2646] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2647] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2648] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[2649] = {6'd3, 8'd141, 8'd129, 32'd0};//{'dest': 141, 'src': 129, 'op': 'move'}
instructions[2650] = {6'd14, 8'd129, 8'd129, 32'd1};//{'src': 129, 'right': 1, 'dest': 129, 'signed': False, 'op': '+', 'size': 2}
instructions[2651] = {6'd15, 8'd0, 8'd0, 32'd2632};//{'label': 2632, 'op': 'goto'}
instructions[2652] = {6'd6, 8'd0, 8'd128, 32'd0};//{'src': 128, 'op': 'jmp_to_reg'}
instructions[2653] = {6'd0, 8'd131, 8'd0, 32'd638};//{'dest': 131, 'literal': 638, 'op': 'literal'}
instructions[2654] = {6'd0, 8'd132, 8'd0, 32'd1662};//{'dest': 132, 'literal': 1662, 'op': 'literal'}
instructions[2655] = {6'd0, 8'd133, 8'd0, 32'd27};//{'dest': 133, 'literal': 27, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2656] = {6'd0, 8'd134, 8'd0, 32'd0};//{'dest': 134, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2657] = {6'd0, 8'd135, 8'd0, 32'd0};//{'dest': 135, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2658] = {6'd0, 8'd136, 8'd0, 32'd0};//{'dest': 136, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2659] = {6'd0, 8'd137, 8'd0, 32'd0};//{'dest': 137, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2660] = {6'd0, 8'd138, 8'd0, 32'd0};//{'dest': 138, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2661] = {6'd0, 8'd139, 8'd0, 32'd0};//{'dest': 139, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2662] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2663] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2664] = {6'd0, 8'd142, 8'd0, 32'd0};//{'dest': 142, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2665] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2666] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2667] = {6'd27, 8'd143, 8'd142, 32'd79};//{'dest': 143, 'src': 142, 'srcb': 79, 'signed': True, 'op': '+'}
instructions[2668] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2669] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2670] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[2671] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2672] = {6'd0, 8'd142, 8'd0, 32'd1};//{'dest': 142, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2673] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2674] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2675] = {6'd27, 8'd143, 8'd142, 32'd79};//{'dest': 143, 'src': 142, 'srcb': 79, 'signed': True, 'op': '+'}
instructions[2676] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2677] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2678] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[2679] = {6'd1, 8'd128, 8'd0, 32'd2627};//{'dest': 128, 'label': 2627, 'op': 'jmp_and_link'}
instructions[2680] = {6'd3, 8'd141, 8'd135, 32'd0};//{'dest': 141, 'src': 135, 'op': 'move'}
instructions[2681] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2682] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2683] = {6'd13, 8'd0, 8'd141, 32'd2687};//{'src': 141, 'label': 2687, 'op': 'jmp_if_false'}
instructions[2684] = {6'd3, 8'd141, 8'd135, 32'd0};//{'dest': 141, 'src': 135, 'op': 'move'}
instructions[2685] = {6'd35, 8'd135, 8'd135, 32'd1};//{'src': 135, 'right': 1, 'dest': 135, 'signed': False, 'op': '-', 'size': 2}
instructions[2686] = {6'd15, 8'd0, 8'd0, 32'd2720};//{'label': 2720, 'op': 'goto'}
instructions[2687] = {6'd0, 8'd141, 8'd0, 32'd120};//{'dest': 141, 'literal': 120, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2688] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2689] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2690] = {6'd3, 8'd135, 8'd141, 32'd0};//{'dest': 135, 'src': 141, 'op': 'move'}
instructions[2691] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2692] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2693] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2694] = {6'd3, 8'd140, 8'd141, 32'd0};//{'dest': 140, 'src': 141, 'op': 'move'}
instructions[2695] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2696] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2697] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2698] = {6'd3, 8'd84, 8'd141, 32'd0};//{'dest': 84, 'src': 141, 'op': 'move'}
instructions[2699] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2700] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2701] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2702] = {6'd3, 8'd83, 8'd141, 32'd0};//{'dest': 83, 'src': 141, 'op': 'move'}
instructions[2703] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2704] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2705] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2706] = {6'd3, 8'd87, 8'd141, 32'd0};//{'dest': 87, 'src': 141, 'op': 'move'}
instructions[2707] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2708] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2709] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2710] = {6'd3, 8'd85, 8'd141, 32'd0};//{'dest': 85, 'src': 141, 'op': 'move'}
instructions[2711] = {6'd3, 8'd152, 8'd132, 32'd0};//{'dest': 152, 'src': 132, 'op': 'move'}
instructions[2712] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2713] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2714] = {6'd3, 8'd98, 8'd152, 32'd0};//{'dest': 98, 'src': 152, 'op': 'move'}
instructions[2715] = {6'd0, 8'd142, 8'd0, 32'd0};//{'dest': 142, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2716] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2717] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2718] = {6'd3, 8'd99, 8'd142, 32'd0};//{'dest': 99, 'src': 142, 'op': 'move'}
instructions[2719] = {6'd1, 8'd97, 8'd0, 32'd1705};//{'dest': 97, 'label': 1705, 'op': 'jmp_and_link'}
instructions[2720] = {6'd3, 8'd141, 8'd140, 32'd0};//{'dest': 141, 'src': 140, 'op': 'move'}
instructions[2721] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2722] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2723] = {6'd39, 8'd142, 8'd141, 32'd0};//{'src': 141, 'right': 0, 'dest': 142, 'signed': True, 'op': '==', 'size': 2}
instructions[2724] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2725] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2726] = {6'd22, 8'd0, 8'd142, 32'd2743};//{'src': 142, 'label': 2743, 'op': 'jmp_if_true'}
instructions[2727] = {6'd39, 8'd142, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 142, 'signed': True, 'op': '==', 'size': 2}
instructions[2728] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2729] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2730] = {6'd22, 8'd0, 8'd142, 32'd2760};//{'src': 142, 'label': 2760, 'op': 'jmp_if_true'}
instructions[2731] = {6'd39, 8'd142, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 142, 'signed': True, 'op': '==', 'size': 2}
instructions[2732] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2733] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2734] = {6'd22, 8'd0, 8'd142, 32'd2826};//{'src': 142, 'label': 2826, 'op': 'jmp_if_true'}
instructions[2735] = {6'd39, 8'd142, 8'd141, 32'd3};//{'src': 141, 'right': 3, 'dest': 142, 'signed': True, 'op': '==', 'size': 2}
instructions[2736] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2737] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2738] = {6'd22, 8'd0, 8'd142, 32'd2905};//{'src': 142, 'label': 2905, 'op': 'jmp_if_true'}
instructions[2739] = {6'd39, 8'd142, 8'd141, 32'd4};//{'src': 141, 'right': 4, 'dest': 142, 'signed': True, 'op': '==', 'size': 2}
instructions[2740] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2741] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2742] = {6'd22, 8'd0, 8'd142, 32'd2915};//{'src': 142, 'label': 2915, 'op': 'jmp_if_true'}
instructions[2743] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2744] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2745] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2746] = {6'd3, 8'd85, 8'd141, 32'd0};//{'dest': 85, 'src': 141, 'op': 'move'}
instructions[2747] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2748] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2749] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2750] = {6'd3, 8'd84, 8'd141, 32'd0};//{'dest': 84, 'src': 141, 'op': 'move'}
instructions[2751] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2752] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2753] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2754] = {6'd3, 8'd83, 8'd141, 32'd0};//{'dest': 83, 'src': 141, 'op': 'move'}
instructions[2755] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2756] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2757] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2758] = {6'd3, 8'd87, 8'd141, 32'd0};//{'dest': 87, 'src': 141, 'op': 'move'}
instructions[2759] = {6'd15, 8'd0, 8'd0, 32'd2947};//{'label': 2947, 'op': 'goto'}
instructions[2760] = {6'd0, 8'd142, 8'd0, 32'd13};//{'dest': 142, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2761] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2762] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2763] = {6'd11, 8'd143, 8'd142, 32'd131};//{'dest': 143, 'src': 142, 'srcb': 131, 'signed': False, 'op': '+'}
instructions[2764] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2765] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2766] = {6'd17, 8'd0, 8'd143, 32'd0};//{'element_size': 2, 'src': 143, 'sequence': 140152842403920, 'op': 'memory_read_request'}
instructions[2767] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2768] = {6'd18, 8'd0, 8'd143, 32'd0};//{'element_size': 2, 'src': 143, 'sequence': 140152842403920, 'op': 'memory_read_wait'}
instructions[2769] = {6'd19, 8'd141, 8'd143, 32'd0};//{'dest': 141, 'src': 143, 'sequence': 140152842403920, 'element_size': 2, 'op': 'memory_read'}
instructions[2770] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2771] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2772] = {6'd3, 8'd75, 8'd141, 32'd0};//{'dest': 75, 'src': 141, 'op': 'move'}
instructions[2773] = {6'd0, 8'd142, 8'd0, 32'd14};//{'dest': 142, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2774] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2775] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2776] = {6'd11, 8'd143, 8'd142, 32'd131};//{'dest': 143, 'src': 142, 'srcb': 131, 'signed': False, 'op': '+'}
instructions[2777] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2778] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2779] = {6'd17, 8'd0, 8'd143, 32'd0};//{'element_size': 2, 'src': 143, 'sequence': 140152842404280, 'op': 'memory_read_request'}
instructions[2780] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2781] = {6'd18, 8'd0, 8'd143, 32'd0};//{'element_size': 2, 'src': 143, 'sequence': 140152842404280, 'op': 'memory_read_wait'}
instructions[2782] = {6'd19, 8'd141, 8'd143, 32'd0};//{'dest': 141, 'src': 143, 'sequence': 140152842404280, 'element_size': 2, 'op': 'memory_read'}
instructions[2783] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2784] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2785] = {6'd3, 8'd76, 8'd141, 32'd0};//{'dest': 76, 'src': 141, 'op': 'move'}
instructions[2786] = {6'd3, 8'd141, 8'd89, 32'd0};//{'dest': 141, 'src': 89, 'op': 'move'}
instructions[2787] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2788] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2789] = {6'd3, 8'd78, 8'd141, 32'd0};//{'dest': 78, 'src': 141, 'op': 'move'}
instructions[2790] = {6'd0, 8'd141, 8'd0, 32'd80};//{'dest': 141, 'literal': 80, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2791] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2792] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2793] = {6'd3, 8'd77, 8'd141, 32'd0};//{'dest': 77, 'src': 141, 'op': 'move'}
instructions[2794] = {6'd3, 8'd144, 8'd81, 32'd0};//{'dest': 144, 'src': 81, 'op': 'move'}
instructions[2795] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2796] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2797] = {6'd3, 8'd19, 8'd144, 32'd0};//{'dest': 19, 'src': 144, 'op': 'move'}
instructions[2798] = {6'd3, 8'd144, 8'd91, 32'd0};//{'dest': 144, 'src': 91, 'op': 'move'}
instructions[2799] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2800] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2801] = {6'd3, 8'd20, 8'd144, 32'd0};//{'dest': 20, 'src': 144, 'op': 'move'}
instructions[2802] = {6'd0, 8'd142, 8'd0, 32'd1};//{'dest': 142, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2803] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2804] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2805] = {6'd3, 8'd21, 8'd142, 32'd0};//{'dest': 21, 'src': 142, 'op': 'move'}
instructions[2806] = {6'd1, 8'd17, 8'd0, 32'd108};//{'dest': 17, 'label': 108, 'op': 'jmp_and_link'}
instructions[2807] = {6'd3, 8'd141, 8'd18, 32'd0};//{'dest': 141, 'src': 18, 'op': 'move'}
instructions[2808] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2809] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2810] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2811] = {6'd3, 8'd84, 8'd141, 32'd0};//{'dest': 84, 'src': 141, 'op': 'move'}
instructions[2812] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2813] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2814] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2815] = {6'd3, 8'd87, 8'd141, 32'd0};//{'dest': 87, 'src': 141, 'op': 'move'}
instructions[2816] = {6'd3, 8'd152, 8'd132, 32'd0};//{'dest': 152, 'src': 132, 'op': 'move'}
instructions[2817] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2818] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2819] = {6'd3, 8'd98, 8'd152, 32'd0};//{'dest': 98, 'src': 152, 'op': 'move'}
instructions[2820] = {6'd0, 8'd142, 8'd0, 32'd0};//{'dest': 142, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2821] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2822] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2823] = {6'd3, 8'd99, 8'd142, 32'd0};//{'dest': 99, 'src': 142, 'op': 'move'}
instructions[2824] = {6'd1, 8'd97, 8'd0, 32'd1705};//{'dest': 97, 'label': 1705, 'op': 'jmp_and_link'}
instructions[2825] = {6'd15, 8'd0, 8'd0, 32'd2947};//{'label': 2947, 'op': 'goto'}
instructions[2826] = {6'd3, 8'd152, 8'd132, 32'd0};//{'dest': 152, 'src': 132, 'op': 'move'}
instructions[2827] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2828] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2829] = {6'd3, 8'd123, 8'd152, 32'd0};//{'dest': 123, 'src': 152, 'op': 'move'}
instructions[2830] = {6'd3, 8'd142, 8'd133, 32'd0};//{'dest': 142, 'src': 133, 'op': 'move'}
instructions[2831] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2832] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2833] = {6'd3, 8'd124, 8'd142, 32'd0};//{'dest': 124, 'src': 142, 'op': 'move'}
instructions[2834] = {6'd1, 8'd121, 8'd0, 32'd2564};//{'dest': 121, 'label': 2564, 'op': 'jmp_and_link'}
instructions[2835] = {6'd3, 8'd141, 8'd122, 32'd0};//{'dest': 141, 'src': 122, 'op': 'move'}
instructions[2836] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2837] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2838] = {6'd3, 8'd134, 8'd141, 32'd0};//{'dest': 134, 'src': 141, 'op': 'move'}
instructions[2839] = {6'd0, 8'd147, 8'd0, 32'd0};//{'dest': 147, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2840] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2841] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2842] = {6'd11, 8'd148, 8'd147, 32'd80};//{'dest': 148, 'src': 147, 'srcb': 80, 'signed': False, 'op': '+'}
instructions[2843] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2844] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2845] = {6'd17, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842407376, 'op': 'memory_read_request'}
instructions[2846] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2847] = {6'd18, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842407376, 'op': 'memory_read_wait'}
instructions[2848] = {6'd19, 8'd141, 8'd148, 32'd0};//{'dest': 141, 'src': 148, 'sequence': 140152842407376, 'element_size': 2, 'op': 'memory_read'}
instructions[2849] = {6'd0, 8'd142, 8'd0, 32'd0};//{'dest': 142, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2850] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2851] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2852] = {6'd11, 8'd143, 8'd142, 32'd79};//{'dest': 143, 'src': 142, 'srcb': 79, 'signed': False, 'op': '+'}
instructions[2853] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2854] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2855] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[2856] = {6'd0, 8'd147, 8'd0, 32'd1};//{'dest': 147, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2857] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2858] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2859] = {6'd11, 8'd148, 8'd147, 32'd80};//{'dest': 148, 'src': 147, 'srcb': 80, 'signed': False, 'op': '+'}
instructions[2860] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2861] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2862] = {6'd17, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842407808, 'op': 'memory_read_request'}
instructions[2863] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2864] = {6'd18, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842407808, 'op': 'memory_read_wait'}
instructions[2865] = {6'd19, 8'd141, 8'd148, 32'd0};//{'dest': 141, 'src': 148, 'sequence': 140152842407808, 'element_size': 2, 'op': 'memory_read'}
instructions[2866] = {6'd0, 8'd142, 8'd0, 32'd1};//{'dest': 142, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2867] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2868] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2869] = {6'd11, 8'd143, 8'd142, 32'd79};//{'dest': 143, 'src': 142, 'srcb': 79, 'signed': False, 'op': '+'}
instructions[2870] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2871] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2872] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[2873] = {6'd3, 8'd144, 8'd80, 32'd0};//{'dest': 144, 'src': 80, 'op': 'move'}
instructions[2874] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2875] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2876] = {6'd3, 8'd19, 8'd144, 32'd0};//{'dest': 19, 'src': 144, 'op': 'move'}
instructions[2877] = {6'd3, 8'd144, 8'd79, 32'd0};//{'dest': 144, 'src': 79, 'op': 'move'}
instructions[2878] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2879] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2880] = {6'd3, 8'd20, 8'd144, 32'd0};//{'dest': 20, 'src': 144, 'op': 'move'}
instructions[2881] = {6'd3, 8'd142, 8'd134, 32'd0};//{'dest': 142, 'src': 134, 'op': 'move'}
instructions[2882] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2883] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2884] = {6'd3, 8'd21, 8'd142, 32'd0};//{'dest': 21, 'src': 142, 'op': 'move'}
instructions[2885] = {6'd1, 8'd17, 8'd0, 32'd108};//{'dest': 17, 'label': 108, 'op': 'jmp_and_link'}
instructions[2886] = {6'd3, 8'd141, 8'd18, 32'd0};//{'dest': 141, 'src': 18, 'op': 'move'}
instructions[2887] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2888] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2889] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2890] = {6'd3, 8'd84, 8'd141, 32'd0};//{'dest': 84, 'src': 141, 'op': 'move'}
instructions[2891] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2892] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2893] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2894] = {6'd3, 8'd87, 8'd141, 32'd0};//{'dest': 87, 'src': 141, 'op': 'move'}
instructions[2895] = {6'd3, 8'd152, 8'd132, 32'd0};//{'dest': 152, 'src': 132, 'op': 'move'}
instructions[2896] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2897] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2898] = {6'd3, 8'd98, 8'd152, 32'd0};//{'dest': 98, 'src': 152, 'op': 'move'}
instructions[2899] = {6'd3, 8'd142, 8'd134, 32'd0};//{'dest': 142, 'src': 134, 'op': 'move'}
instructions[2900] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2901] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2902] = {6'd3, 8'd99, 8'd142, 32'd0};//{'dest': 99, 'src': 142, 'op': 'move'}
instructions[2903] = {6'd1, 8'd97, 8'd0, 32'd1705};//{'dest': 97, 'label': 1705, 'op': 'jmp_and_link'}
instructions[2904] = {6'd15, 8'd0, 8'd0, 32'd2947};//{'label': 2947, 'op': 'goto'}
instructions[2905] = {6'd3, 8'd152, 8'd132, 32'd0};//{'dest': 152, 'src': 132, 'op': 'move'}
instructions[2906] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2907] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2908] = {6'd3, 8'd98, 8'd152, 32'd0};//{'dest': 98, 'src': 152, 'op': 'move'}
instructions[2909] = {6'd3, 8'd142, 8'd134, 32'd0};//{'dest': 142, 'src': 134, 'op': 'move'}
instructions[2910] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2911] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2912] = {6'd3, 8'd99, 8'd142, 32'd0};//{'dest': 99, 'src': 142, 'op': 'move'}
instructions[2913] = {6'd1, 8'd97, 8'd0, 32'd1705};//{'dest': 97, 'label': 1705, 'op': 'jmp_and_link'}
instructions[2914] = {6'd15, 8'd0, 8'd0, 32'd2947};//{'label': 2947, 'op': 'goto'}
instructions[2915] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2916] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2917] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2918] = {6'd3, 8'd83, 8'd141, 32'd0};//{'dest': 83, 'src': 141, 'op': 'move'}
instructions[2919] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2920] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2921] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2922] = {6'd3, 8'd87, 8'd141, 32'd0};//{'dest': 87, 'src': 141, 'op': 'move'}
instructions[2923] = {6'd3, 8'd144, 8'd81, 32'd0};//{'dest': 144, 'src': 81, 'op': 'move'}
instructions[2924] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2925] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2926] = {6'd3, 8'd19, 8'd144, 32'd0};//{'dest': 19, 'src': 144, 'op': 'move'}
instructions[2927] = {6'd3, 8'd144, 8'd91, 32'd0};//{'dest': 144, 'src': 91, 'op': 'move'}
instructions[2928] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2929] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2930] = {6'd3, 8'd20, 8'd144, 32'd0};//{'dest': 20, 'src': 144, 'op': 'move'}
instructions[2931] = {6'd0, 8'd142, 8'd0, 32'd1};//{'dest': 142, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2932] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2933] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2934] = {6'd3, 8'd21, 8'd142, 32'd0};//{'dest': 21, 'src': 142, 'op': 'move'}
instructions[2935] = {6'd1, 8'd17, 8'd0, 32'd108};//{'dest': 17, 'label': 108, 'op': 'jmp_and_link'}
instructions[2936] = {6'd3, 8'd141, 8'd18, 32'd0};//{'dest': 141, 'src': 18, 'op': 'move'}
instructions[2937] = {6'd3, 8'd152, 8'd132, 32'd0};//{'dest': 152, 'src': 132, 'op': 'move'}
instructions[2938] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2939] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2940] = {6'd3, 8'd98, 8'd152, 32'd0};//{'dest': 98, 'src': 152, 'op': 'move'}
instructions[2941] = {6'd0, 8'd142, 8'd0, 32'd0};//{'dest': 142, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2942] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2943] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2944] = {6'd3, 8'd99, 8'd142, 32'd0};//{'dest': 99, 'src': 142, 'op': 'move'}
instructions[2945] = {6'd1, 8'd97, 8'd0, 32'd1705};//{'dest': 97, 'label': 1705, 'op': 'jmp_and_link'}
instructions[2946] = {6'd15, 8'd0, 8'd0, 32'd2947};//{'label': 2947, 'op': 'goto'}
instructions[2947] = {6'd0, 8'd141, 8'd0, 32'd10000};//{'dest': 141, 'literal': 10000, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2948] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2949] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2950] = {6'd3, 8'd136, 8'd141, 32'd0};//{'dest': 136, 'src': 141, 'op': 'move'}
instructions[2951] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2952] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2953] = {6'd3, 8'd141, 8'd136, 32'd0};//{'dest': 141, 'src': 136, 'op': 'move'}
instructions[2954] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2955] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2956] = {6'd13, 8'd0, 8'd141, 32'd3380};//{'src': 141, 'label': 3380, 'op': 'jmp_if_false'}
instructions[2957] = {6'd3, 8'd152, 8'd131, 32'd0};//{'dest': 152, 'src': 131, 'op': 'move'}
instructions[2958] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2959] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2960] = {6'd3, 8'd108, 8'd152, 32'd0};//{'dest': 108, 'src': 152, 'op': 'move'}
instructions[2961] = {6'd1, 8'd106, 8'd0, 32'd2162};//{'dest': 106, 'label': 2162, 'op': 'jmp_and_link'}
instructions[2962] = {6'd3, 8'd141, 8'd107, 32'd0};//{'dest': 141, 'src': 107, 'op': 'move'}
instructions[2963] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2964] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2965] = {6'd3, 8'd137, 8'd141, 32'd0};//{'dest': 137, 'src': 141, 'op': 'move'}
instructions[2966] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2967] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2968] = {6'd3, 8'd141, 8'd137, 32'd0};//{'dest': 141, 'src': 137, 'op': 'move'}
instructions[2969] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2970] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2971] = {6'd13, 8'd0, 8'd141, 32'd2976};//{'src': 141, 'label': 2976, 'op': 'jmp_if_false'}
instructions[2972] = {6'd3, 8'd142, 8'd90, 32'd0};//{'dest': 142, 'src': 90, 'op': 'move'}
instructions[2973] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2974] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2975] = {6'd25, 8'd141, 8'd142, 32'd80};//{'src': 142, 'right': 80, 'dest': 141, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[2976] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2977] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2978] = {6'd13, 8'd0, 8'd141, 32'd3373};//{'src': 141, 'label': 3373, 'op': 'jmp_if_false'}
instructions[2979] = {6'd3, 8'd142, 8'd140, 32'd0};//{'dest': 142, 'src': 140, 'op': 'move'}
instructions[2980] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2981] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2982] = {6'd26, 8'd141, 8'd142, 32'd0};//{'src': 142, 'right': 0, 'dest': 141, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[2983] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2984] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2985] = {6'd13, 8'd0, 8'd141, 32'd2991};//{'src': 141, 'label': 2991, 'op': 'jmp_if_false'}
instructions[2986] = {6'd3, 8'd142, 8'd89, 32'd0};//{'dest': 142, 'src': 89, 'op': 'move'}
instructions[2987] = {6'd3, 8'd143, 8'd78, 32'd0};//{'dest': 143, 'src': 78, 'op': 'move'}
instructions[2988] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2989] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2990] = {6'd21, 8'd141, 8'd142, 32'd143};//{'srcb': 143, 'src': 142, 'dest': 141, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[2991] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2992] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2993] = {6'd13, 8'd0, 8'd141, 32'd2996};//{'src': 141, 'label': 2996, 'op': 'jmp_if_false'}
instructions[2994] = {6'd15, 8'd0, 8'd0, 32'd3377};//{'label': 3377, 'op': 'goto'}
instructions[2995] = {6'd15, 8'd0, 8'd0, 32'd2996};//{'label': 2996, 'op': 'goto'}
instructions[2996] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2997] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2998] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2999] = {6'd3, 8'd139, 8'd141, 32'd0};//{'dest': 139, 'src': 141, 'op': 'move'}
instructions[3000] = {6'd3, 8'd141, 8'd140, 32'd0};//{'dest': 141, 'src': 140, 'op': 'move'}
instructions[3001] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3002] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3003] = {6'd3, 8'd138, 8'd141, 32'd0};//{'dest': 138, 'src': 141, 'op': 'move'}
instructions[3004] = {6'd3, 8'd141, 8'd140, 32'd0};//{'dest': 141, 'src': 140, 'op': 'move'}
instructions[3005] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3006] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3007] = {6'd39, 8'd142, 8'd141, 32'd0};//{'src': 141, 'right': 0, 'dest': 142, 'signed': True, 'op': '==', 'size': 2}
instructions[3008] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3009] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3010] = {6'd22, 8'd0, 8'd142, 32'd3027};//{'src': 142, 'label': 3027, 'op': 'jmp_if_true'}
instructions[3011] = {6'd39, 8'd142, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 142, 'signed': True, 'op': '==', 'size': 2}
instructions[3012] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3013] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3014] = {6'd22, 8'd0, 8'd142, 32'd3088};//{'src': 142, 'label': 3088, 'op': 'jmp_if_true'}
instructions[3015] = {6'd39, 8'd142, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 142, 'signed': True, 'op': '==', 'size': 2}
instructions[3016] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3017] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3018] = {6'd22, 8'd0, 8'd142, 32'd3166};//{'src': 142, 'label': 3166, 'op': 'jmp_if_true'}
instructions[3019] = {6'd39, 8'd142, 8'd141, 32'd3};//{'src': 141, 'right': 3, 'dest': 142, 'signed': True, 'op': '==', 'size': 2}
instructions[3020] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3021] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3022] = {6'd22, 8'd0, 8'd142, 32'd3202};//{'src': 142, 'label': 3202, 'op': 'jmp_if_true'}
instructions[3023] = {6'd39, 8'd142, 8'd141, 32'd4};//{'src': 141, 'right': 4, 'dest': 142, 'signed': True, 'op': '==', 'size': 2}
instructions[3024] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3025] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3026] = {6'd22, 8'd0, 8'd142, 32'd3290};//{'src': 142, 'label': 3290, 'op': 'jmp_if_true'}
instructions[3027] = {6'd3, 8'd141, 8'd94, 32'd0};//{'dest': 141, 'src': 94, 'op': 'move'}
instructions[3028] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3029] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3030] = {6'd13, 8'd0, 8'd141, 32'd3036};//{'src': 141, 'label': 3036, 'op': 'jmp_if_false'}
instructions[3031] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3032] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3033] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3034] = {6'd3, 8'd140, 8'd141, 32'd0};//{'dest': 140, 'src': 141, 'op': 'move'}
instructions[3035] = {6'd15, 8'd0, 8'd0, 32'd3087};//{'label': 3087, 'op': 'goto'}
instructions[3036] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3037] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3038] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3039] = {6'd3, 8'd85, 8'd141, 32'd0};//{'dest': 85, 'src': 141, 'op': 'move'}
instructions[3040] = {6'd0, 8'd142, 8'd0, 32'd13};//{'dest': 142, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3041] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3042] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3043] = {6'd11, 8'd143, 8'd142, 32'd131};//{'dest': 143, 'src': 142, 'srcb': 131, 'signed': False, 'op': '+'}
instructions[3044] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3045] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3046] = {6'd17, 8'd0, 8'd143, 32'd0};//{'element_size': 2, 'src': 143, 'sequence': 140152842432456, 'op': 'memory_read_request'}
instructions[3047] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3048] = {6'd18, 8'd0, 8'd143, 32'd0};//{'element_size': 2, 'src': 143, 'sequence': 140152842432456, 'op': 'memory_read_wait'}
instructions[3049] = {6'd19, 8'd141, 8'd143, 32'd0};//{'dest': 141, 'src': 143, 'sequence': 140152842432456, 'element_size': 2, 'op': 'memory_read'}
instructions[3050] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3051] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3052] = {6'd3, 8'd75, 8'd141, 32'd0};//{'dest': 75, 'src': 141, 'op': 'move'}
instructions[3053] = {6'd0, 8'd142, 8'd0, 32'd14};//{'dest': 142, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3054] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3055] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3056] = {6'd11, 8'd143, 8'd142, 32'd131};//{'dest': 143, 'src': 142, 'srcb': 131, 'signed': False, 'op': '+'}
instructions[3057] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3058] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3059] = {6'd17, 8'd0, 8'd143, 32'd0};//{'element_size': 2, 'src': 143, 'sequence': 140152841920880, 'op': 'memory_read_request'}
instructions[3060] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3061] = {6'd18, 8'd0, 8'd143, 32'd0};//{'element_size': 2, 'src': 143, 'sequence': 140152841920880, 'op': 'memory_read_wait'}
instructions[3062] = {6'd19, 8'd141, 8'd143, 32'd0};//{'dest': 141, 'src': 143, 'sequence': 140152841920880, 'element_size': 2, 'op': 'memory_read'}
instructions[3063] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3064] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3065] = {6'd3, 8'd76, 8'd141, 32'd0};//{'dest': 76, 'src': 141, 'op': 'move'}
instructions[3066] = {6'd3, 8'd141, 8'd89, 32'd0};//{'dest': 141, 'src': 89, 'op': 'move'}
instructions[3067] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3068] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3069] = {6'd3, 8'd78, 8'd141, 32'd0};//{'dest': 78, 'src': 141, 'op': 'move'}
instructions[3070] = {6'd0, 8'd141, 8'd0, 32'd80};//{'dest': 141, 'literal': 80, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3071] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3072] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3073] = {6'd3, 8'd77, 8'd141, 32'd0};//{'dest': 77, 'src': 141, 'op': 'move'}
instructions[3074] = {6'd3, 8'd152, 8'd132, 32'd0};//{'dest': 152, 'src': 132, 'op': 'move'}
instructions[3075] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3076] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3077] = {6'd3, 8'd98, 8'd152, 32'd0};//{'dest': 98, 'src': 152, 'op': 'move'}
instructions[3078] = {6'd0, 8'd142, 8'd0, 32'd0};//{'dest': 142, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3079] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3080] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3081] = {6'd3, 8'd99, 8'd142, 32'd0};//{'dest': 99, 'src': 142, 'op': 'move'}
instructions[3082] = {6'd1, 8'd97, 8'd0, 32'd1705};//{'dest': 97, 'label': 1705, 'op': 'jmp_and_link'}
instructions[3083] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3084] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3085] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3086] = {6'd3, 8'd85, 8'd141, 32'd0};//{'dest': 85, 'src': 141, 'op': 'move'}
instructions[3087] = {6'd15, 8'd0, 8'd0, 32'd3300};//{'label': 3300, 'op': 'goto'}
instructions[3088] = {6'd3, 8'd141, 8'd96, 32'd0};//{'dest': 141, 'src': 96, 'op': 'move'}
instructions[3089] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3090] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3091] = {6'd13, 8'd0, 8'd141, 32'd3165};//{'src': 141, 'label': 3165, 'op': 'jmp_if_false'}
instructions[3092] = {6'd0, 8'd147, 8'd0, 32'd1};//{'dest': 147, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3093] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3094] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3095] = {6'd11, 8'd148, 8'd147, 32'd92};//{'dest': 148, 'src': 147, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[3096] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3097] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3098] = {6'd17, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152841923040, 'op': 'memory_read_request'}
instructions[3099] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3100] = {6'd18, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152841923040, 'op': 'memory_read_wait'}
instructions[3101] = {6'd19, 8'd141, 8'd148, 32'd0};//{'dest': 141, 'src': 148, 'sequence': 140152841923040, 'element_size': 2, 'op': 'memory_read'}
instructions[3102] = {6'd0, 8'd142, 8'd0, 32'd1};//{'dest': 142, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3103] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3104] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3105] = {6'd11, 8'd143, 8'd142, 32'd79};//{'dest': 143, 'src': 142, 'srcb': 79, 'signed': False, 'op': '+'}
instructions[3106] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3107] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3108] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[3109] = {6'd0, 8'd147, 8'd0, 32'd0};//{'dest': 147, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3110] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3111] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3112] = {6'd11, 8'd148, 8'd147, 32'd92};//{'dest': 148, 'src': 147, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[3113] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3114] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3115] = {6'd17, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152841923472, 'op': 'memory_read_request'}
instructions[3116] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3117] = {6'd18, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152841923472, 'op': 'memory_read_wait'}
instructions[3118] = {6'd19, 8'd141, 8'd148, 32'd0};//{'dest': 141, 'src': 148, 'sequence': 140152841923472, 'element_size': 2, 'op': 'memory_read'}
instructions[3119] = {6'd0, 8'd142, 8'd0, 32'd0};//{'dest': 142, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3120] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3121] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3122] = {6'd11, 8'd143, 8'd142, 32'd79};//{'dest': 143, 'src': 142, 'srcb': 79, 'signed': False, 'op': '+'}
instructions[3123] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3124] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3125] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[3126] = {6'd0, 8'd147, 8'd0, 32'd1};//{'dest': 147, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3127] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3128] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3129] = {6'd11, 8'd148, 8'd147, 32'd92};//{'dest': 148, 'src': 147, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[3130] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3131] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3132] = {6'd17, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152841923904, 'op': 'memory_read_request'}
instructions[3133] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3134] = {6'd18, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152841923904, 'op': 'memory_read_wait'}
instructions[3135] = {6'd19, 8'd141, 8'd148, 32'd0};//{'dest': 141, 'src': 148, 'sequence': 140152841923904, 'element_size': 2, 'op': 'memory_read'}
instructions[3136] = {6'd0, 8'd142, 8'd0, 32'd1};//{'dest': 142, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3137] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3138] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3139] = {6'd11, 8'd143, 8'd142, 32'd80};//{'dest': 143, 'src': 142, 'srcb': 80, 'signed': False, 'op': '+'}
instructions[3140] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3141] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3142] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[3143] = {6'd0, 8'd147, 8'd0, 32'd0};//{'dest': 147, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3144] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3145] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3146] = {6'd11, 8'd148, 8'd147, 32'd92};//{'dest': 148, 'src': 147, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[3147] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3148] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3149] = {6'd17, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152841924336, 'op': 'memory_read_request'}
instructions[3150] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3151] = {6'd18, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152841924336, 'op': 'memory_read_wait'}
instructions[3152] = {6'd19, 8'd141, 8'd148, 32'd0};//{'dest': 141, 'src': 148, 'sequence': 140152841924336, 'element_size': 2, 'op': 'memory_read'}
instructions[3153] = {6'd0, 8'd142, 8'd0, 32'd0};//{'dest': 142, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3154] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3155] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3156] = {6'd11, 8'd143, 8'd142, 32'd80};//{'dest': 143, 'src': 142, 'srcb': 80, 'signed': False, 'op': '+'}
instructions[3157] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3158] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3159] = {6'd23, 8'd0, 8'd143, 32'd141};//{'srcb': 141, 'src': 143, 'element_size': 2, 'op': 'memory_write'}
instructions[3160] = {6'd0, 8'd141, 8'd0, 32'd2};//{'dest': 141, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3161] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3162] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3163] = {6'd3, 8'd140, 8'd141, 32'd0};//{'dest': 140, 'src': 141, 'op': 'move'}
instructions[3164] = {6'd15, 8'd0, 8'd0, 32'd3165};//{'label': 3165, 'op': 'goto'}
instructions[3165] = {6'd15, 8'd0, 8'd0, 32'd3300};//{'label': 3300, 'op': 'goto'}
instructions[3166] = {6'd3, 8'd144, 8'd81, 32'd0};//{'dest': 144, 'src': 81, 'op': 'move'}
instructions[3167] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3168] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3169] = {6'd3, 8'd19, 8'd144, 32'd0};//{'dest': 19, 'src': 144, 'op': 'move'}
instructions[3170] = {6'd3, 8'd144, 8'd91, 32'd0};//{'dest': 144, 'src': 91, 'op': 'move'}
instructions[3171] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3172] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3173] = {6'd3, 8'd20, 8'd144, 32'd0};//{'dest': 20, 'src': 144, 'op': 'move'}
instructions[3174] = {6'd3, 8'd142, 8'd104, 32'd0};//{'dest': 142, 'src': 104, 'op': 'move'}
instructions[3175] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3176] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3177] = {6'd3, 8'd21, 8'd142, 32'd0};//{'dest': 21, 'src': 142, 'op': 'move'}
instructions[3178] = {6'd1, 8'd17, 8'd0, 32'd108};//{'dest': 17, 'label': 108, 'op': 'jmp_and_link'}
instructions[3179] = {6'd3, 8'd141, 8'd18, 32'd0};//{'dest': 141, 'src': 18, 'op': 'move'}
instructions[3180] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3181] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3182] = {6'd3, 8'd139, 8'd141, 32'd0};//{'dest': 139, 'src': 141, 'op': 'move'}
instructions[3183] = {6'd3, 8'd141, 8'd93, 32'd0};//{'dest': 141, 'src': 93, 'op': 'move'}
instructions[3184] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3185] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3186] = {6'd13, 8'd0, 8'd141, 32'd3192};//{'src': 141, 'label': 3192, 'op': 'jmp_if_false'}
instructions[3187] = {6'd0, 8'd141, 8'd0, 32'd4};//{'dest': 141, 'literal': 4, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3188] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3189] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3190] = {6'd3, 8'd140, 8'd141, 32'd0};//{'dest': 140, 'src': 141, 'op': 'move'}
instructions[3191] = {6'd15, 8'd0, 8'd0, 32'd3201};//{'label': 3201, 'op': 'goto'}
instructions[3192] = {6'd3, 8'd141, 8'd134, 32'd0};//{'dest': 141, 'src': 134, 'op': 'move'}
instructions[3193] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3194] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3195] = {6'd13, 8'd0, 8'd141, 32'd3201};//{'src': 141, 'label': 3201, 'op': 'jmp_if_false'}
instructions[3196] = {6'd0, 8'd141, 8'd0, 32'd3};//{'dest': 141, 'literal': 3, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3197] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3198] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3199] = {6'd3, 8'd140, 8'd141, 32'd0};//{'dest': 140, 'src': 141, 'op': 'move'}
instructions[3200] = {6'd15, 8'd0, 8'd0, 32'd3201};//{'label': 3201, 'op': 'goto'}
instructions[3201] = {6'd15, 8'd0, 8'd0, 32'd3300};//{'label': 3300, 'op': 'goto'}
instructions[3202] = {6'd3, 8'd144, 8'd81, 32'd0};//{'dest': 144, 'src': 81, 'op': 'move'}
instructions[3203] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3204] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3205] = {6'd3, 8'd19, 8'd144, 32'd0};//{'dest': 19, 'src': 144, 'op': 'move'}
instructions[3206] = {6'd3, 8'd144, 8'd91, 32'd0};//{'dest': 144, 'src': 91, 'op': 'move'}
instructions[3207] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3208] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3209] = {6'd3, 8'd20, 8'd144, 32'd0};//{'dest': 20, 'src': 144, 'op': 'move'}
instructions[3210] = {6'd3, 8'd142, 8'd104, 32'd0};//{'dest': 142, 'src': 104, 'op': 'move'}
instructions[3211] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3212] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3213] = {6'd3, 8'd21, 8'd142, 32'd0};//{'dest': 21, 'src': 142, 'op': 'move'}
instructions[3214] = {6'd1, 8'd17, 8'd0, 32'd108};//{'dest': 17, 'label': 108, 'op': 'jmp_and_link'}
instructions[3215] = {6'd3, 8'd141, 8'd18, 32'd0};//{'dest': 141, 'src': 18, 'op': 'move'}
instructions[3216] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3217] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3218] = {6'd3, 8'd139, 8'd141, 32'd0};//{'dest': 139, 'src': 141, 'op': 'move'}
instructions[3219] = {6'd3, 8'd141, 8'd93, 32'd0};//{'dest': 141, 'src': 93, 'op': 'move'}
instructions[3220] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3221] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3222] = {6'd13, 8'd0, 8'd141, 32'd3228};//{'src': 141, 'label': 3228, 'op': 'jmp_if_false'}
instructions[3223] = {6'd0, 8'd141, 8'd0, 32'd4};//{'dest': 141, 'literal': 4, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3224] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3225] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3226] = {6'd3, 8'd140, 8'd141, 32'd0};//{'dest': 140, 'src': 141, 'op': 'move'}
instructions[3227] = {6'd15, 8'd0, 8'd0, 32'd3289};//{'label': 3289, 'op': 'goto'}
instructions[3228] = {6'd3, 8'd141, 8'd96, 32'd0};//{'dest': 141, 'src': 96, 'op': 'move'}
instructions[3229] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3230] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3231] = {6'd13, 8'd0, 8'd141, 32'd3255};//{'src': 141, 'label': 3255, 'op': 'jmp_if_false'}
instructions[3232] = {6'd0, 8'd143, 8'd0, 32'd1};//{'dest': 143, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3233] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3234] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3235] = {6'd11, 8'd147, 8'd143, 32'd80};//{'dest': 147, 'src': 143, 'srcb': 80, 'signed': False, 'op': '+'}
instructions[3236] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3237] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3238] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842538736, 'op': 'memory_read_request'}
instructions[3239] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3240] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842538736, 'op': 'memory_read_wait'}
instructions[3241] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152842538736, 'element_size': 2, 'op': 'memory_read'}
instructions[3242] = {6'd0, 8'd147, 8'd0, 32'd1};//{'dest': 147, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3243] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3244] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3245] = {6'd11, 8'd148, 8'd147, 32'd92};//{'dest': 148, 'src': 147, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[3246] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3247] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3248] = {6'd17, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842538880, 'op': 'memory_read_request'}
instructions[3249] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3250] = {6'd18, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842538880, 'op': 'memory_read_wait'}
instructions[3251] = {6'd19, 8'd143, 8'd148, 32'd0};//{'dest': 143, 'src': 148, 'sequence': 140152842538880, 'element_size': 2, 'op': 'memory_read'}
instructions[3252] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3253] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3254] = {6'd29, 8'd141, 8'd142, 32'd143};//{'srcb': 143, 'src': 142, 'dest': 141, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[3255] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3256] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3257] = {6'd13, 8'd0, 8'd141, 32'd3281};//{'src': 141, 'label': 3281, 'op': 'jmp_if_false'}
instructions[3258] = {6'd0, 8'd143, 8'd0, 32'd0};//{'dest': 143, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3259] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3260] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3261] = {6'd11, 8'd147, 8'd143, 32'd80};//{'dest': 147, 'src': 143, 'srcb': 80, 'signed': False, 'op': '+'}
instructions[3262] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3263] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3264] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842514656, 'op': 'memory_read_request'}
instructions[3265] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3266] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 140152842514656, 'op': 'memory_read_wait'}
instructions[3267] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 140152842514656, 'element_size': 2, 'op': 'memory_read'}
instructions[3268] = {6'd0, 8'd147, 8'd0, 32'd0};//{'dest': 147, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3269] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3270] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3271] = {6'd11, 8'd148, 8'd147, 32'd92};//{'dest': 148, 'src': 147, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[3272] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3273] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3274] = {6'd17, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842514800, 'op': 'memory_read_request'}
instructions[3275] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3276] = {6'd18, 8'd0, 8'd148, 32'd0};//{'element_size': 2, 'src': 148, 'sequence': 140152842514800, 'op': 'memory_read_wait'}
instructions[3277] = {6'd19, 8'd143, 8'd148, 32'd0};//{'dest': 143, 'src': 148, 'sequence': 140152842514800, 'element_size': 2, 'op': 'memory_read'}
instructions[3278] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3279] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3280] = {6'd29, 8'd141, 8'd142, 32'd143};//{'srcb': 143, 'src': 142, 'dest': 141, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[3281] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3282] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3283] = {6'd13, 8'd0, 8'd141, 32'd3289};//{'src': 141, 'label': 3289, 'op': 'jmp_if_false'}
instructions[3284] = {6'd0, 8'd141, 8'd0, 32'd2};//{'dest': 141, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3285] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3286] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3287] = {6'd3, 8'd140, 8'd141, 32'd0};//{'dest': 140, 'src': 141, 'op': 'move'}
instructions[3288] = {6'd15, 8'd0, 8'd0, 32'd3289};//{'label': 3289, 'op': 'goto'}
instructions[3289] = {6'd15, 8'd0, 8'd0, 32'd3300};//{'label': 3300, 'op': 'goto'}
instructions[3290] = {6'd3, 8'd141, 8'd96, 32'd0};//{'dest': 141, 'src': 96, 'op': 'move'}
instructions[3291] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3292] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3293] = {6'd13, 8'd0, 8'd141, 32'd3299};//{'src': 141, 'label': 3299, 'op': 'jmp_if_false'}
instructions[3294] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3295] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3296] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3297] = {6'd3, 8'd140, 8'd141, 32'd0};//{'dest': 140, 'src': 141, 'op': 'move'}
instructions[3298] = {6'd15, 8'd0, 8'd0, 32'd3299};//{'label': 3299, 'op': 'goto'}
instructions[3299] = {6'd15, 8'd0, 8'd0, 32'd3300};//{'label': 3300, 'op': 'goto'}
instructions[3300] = {6'd3, 8'd141, 8'd95, 32'd0};//{'dest': 141, 'src': 95, 'op': 'move'}
instructions[3301] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3302] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3303] = {6'd13, 8'd0, 8'd141, 32'd3309};//{'src': 141, 'label': 3309, 'op': 'jmp_if_false'}
instructions[3304] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3305] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3306] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3307] = {6'd3, 8'd140, 8'd141, 32'd0};//{'dest': 140, 'src': 141, 'op': 'move'}
instructions[3308] = {6'd15, 8'd0, 8'd0, 32'd3309};//{'label': 3309, 'op': 'goto'}
instructions[3309] = {6'd3, 8'd141, 8'd139, 32'd0};//{'dest': 141, 'src': 139, 'op': 'move'}
instructions[3310] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3311] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3312] = {6'd13, 8'd0, 8'd141, 32'd3345};//{'src': 141, 'label': 3345, 'op': 'jmp_if_false'}
instructions[3313] = {6'd3, 8'd152, 8'd131, 32'd0};//{'dest': 152, 'src': 131, 'op': 'move'}
instructions[3314] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3315] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3316] = {6'd3, 8'd116, 8'd152, 32'd0};//{'dest': 116, 'src': 152, 'op': 'move'}
instructions[3317] = {6'd3, 8'd142, 8'd105, 32'd0};//{'dest': 142, 'src': 105, 'op': 'move'}
instructions[3318] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3319] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3320] = {6'd3, 8'd117, 8'd142, 32'd0};//{'dest': 117, 'src': 142, 'op': 'move'}
instructions[3321] = {6'd3, 8'd142, 8'd104, 32'd0};//{'dest': 142, 'src': 104, 'op': 'move'}
instructions[3322] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3323] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3324] = {6'd3, 8'd118, 8'd142, 32'd0};//{'dest': 118, 'src': 142, 'op': 'move'}
instructions[3325] = {6'd1, 8'd115, 8'd0, 32'd2514};//{'dest': 115, 'label': 2514, 'op': 'jmp_and_link'}
instructions[3326] = {6'd3, 8'd142, 8'd140, 32'd0};//{'dest': 142, 'src': 140, 'op': 'move'}
instructions[3327] = {6'd3, 8'd143, 8'd138, 32'd0};//{'dest': 143, 'src': 138, 'op': 'move'}
instructions[3328] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3329] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3330] = {6'd29, 8'd141, 8'd142, 32'd143};//{'srcb': 143, 'src': 142, 'dest': 141, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[3331] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3332] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3333] = {6'd13, 8'd0, 8'd141, 32'd3344};//{'src': 141, 'label': 3344, 'op': 'jmp_if_false'}
instructions[3334] = {6'd3, 8'd152, 8'd132, 32'd0};//{'dest': 152, 'src': 132, 'op': 'move'}
instructions[3335] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3336] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3337] = {6'd3, 8'd98, 8'd152, 32'd0};//{'dest': 98, 'src': 152, 'op': 'move'}
instructions[3338] = {6'd3, 8'd142, 8'd134, 32'd0};//{'dest': 142, 'src': 134, 'op': 'move'}
instructions[3339] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3340] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3341] = {6'd3, 8'd99, 8'd142, 32'd0};//{'dest': 99, 'src': 142, 'op': 'move'}
instructions[3342] = {6'd1, 8'd97, 8'd0, 32'd1705};//{'dest': 97, 'label': 1705, 'op': 'jmp_and_link'}
instructions[3343] = {6'd15, 8'd0, 8'd0, 32'd3344};//{'label': 3344, 'op': 'goto'}
instructions[3344] = {6'd15, 8'd0, 8'd0, 32'd3345};//{'label': 3345, 'op': 'goto'}
instructions[3345] = {6'd3, 8'd142, 8'd140, 32'd0};//{'dest': 142, 'src': 140, 'op': 'move'}
instructions[3346] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3347] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3348] = {6'd25, 8'd141, 8'd142, 32'd2};//{'src': 142, 'right': 2, 'dest': 141, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[3349] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3350] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3351] = {6'd13, 8'd0, 8'd141, 32'd3353};//{'src': 141, 'label': 3353, 'op': 'jmp_if_false'}
instructions[3352] = {6'd38, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'input': 'socket', 'op': 'ready'}
instructions[3353] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3354] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3355] = {6'd13, 8'd0, 8'd141, 32'd3358};//{'src': 141, 'label': 3358, 'op': 'jmp_if_false'}
instructions[3356] = {6'd15, 8'd0, 8'd0, 32'd3380};//{'label': 3380, 'op': 'goto'}
instructions[3357] = {6'd15, 8'd0, 8'd0, 32'd3358};//{'label': 3358, 'op': 'goto'}
instructions[3358] = {6'd3, 8'd142, 8'd140, 32'd0};//{'dest': 142, 'src': 140, 'op': 'move'}
instructions[3359] = {6'd3, 8'd143, 8'd138, 32'd0};//{'dest': 143, 'src': 138, 'op': 'move'}
instructions[3360] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3361] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3362] = {6'd21, 8'd141, 8'd142, 32'd143};//{'srcb': 143, 'src': 142, 'dest': 141, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[3363] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3364] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3365] = {6'd13, 8'd0, 8'd141, 32'd3372};//{'src': 141, 'label': 3372, 'op': 'jmp_if_false'}
instructions[3366] = {6'd0, 8'd141, 8'd0, 32'd120};//{'dest': 141, 'literal': 120, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3367] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3368] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3369] = {6'd3, 8'd135, 8'd141, 32'd0};//{'dest': 135, 'src': 141, 'op': 'move'}
instructions[3370] = {6'd15, 8'd0, 8'd0, 32'd3380};//{'label': 3380, 'op': 'goto'}
instructions[3371] = {6'd15, 8'd0, 8'd0, 32'd3372};//{'label': 3372, 'op': 'goto'}
instructions[3372] = {6'd15, 8'd0, 8'd0, 32'd3377};//{'label': 3377, 'op': 'goto'}
instructions[3373] = {6'd0, 8'd141, 8'd0, 32'd10000};//{'dest': 141, 'literal': 10000, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3374] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3375] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3376] = {6'd40, 8'd0, 8'd141, 32'd0};//{'src': 141, 'op': 'wait_clocks'}
instructions[3377] = {6'd3, 8'd141, 8'd136, 32'd0};//{'dest': 141, 'src': 136, 'op': 'move'}
instructions[3378] = {6'd35, 8'd136, 8'd136, 32'd1};//{'src': 136, 'right': 1, 'dest': 136, 'signed': False, 'op': '-', 'size': 2}
instructions[3379] = {6'd15, 8'd0, 8'd0, 32'd2951};//{'label': 2951, 'op': 'goto'}
instructions[3380] = {6'd15, 8'd0, 8'd0, 32'd2680};//{'label': 2680, 'op': 'goto'}
instructions[3381] = {6'd6, 8'd0, 8'd130, 32'd0};//{'src': 130, 'op': 'jmp_to_reg'}
end
//////////////////////////////////////////////////////////////////////////////
// CPU IMPLEMENTAION OF C PROCESS
//
// This section of the file contains a CPU implementing the C process.
always @(posedge clk)
begin
//implement memory for 2 byte x n arrays
if (memory_enable_2 == 1'b1) begin
memory_2[address_2] <= data_in_2;
end
data_out_2 <= memory_2[address_2];
memory_enable_2 <= 1'b0;
write_enable_2 <= 0;
//stage 0 instruction fetch
if (stage_0_enable) begin
stage_1_enable <= 1;
instruction_0 <= instructions[program_counter];
opcode_0 = instruction_0[53:48];
dest_0 = instruction_0[47:40];
src_0 = instruction_0[39:32];
srcb_0 = instruction_0[7:0];
literal_0 = instruction_0[31:0];
if(write_enable_2) begin
registers[dest_2] <= result_2;
end
program_counter_0 <= program_counter;
program_counter <= program_counter + 1;
end
//stage 1 opcode fetch
if (stage_1_enable) begin
stage_2_enable <= 1;
register_1 <= registers[src_0];
registerb_1 <= registers[srcb_0];
dest_1 <= dest_0;
literal_1 <= literal_0;
opcode_1 <= opcode_0;
program_counter_1 <= program_counter_0;
end
//stage 2 opcode fetch
if (stage_2_enable) begin
dest_2 <= dest_1;
case(opcode_1)
16'd0:
begin
result_2 <= literal_1;
write_enable_2 <= 1;
end
16'd1:
begin
program_counter <= literal_1;
result_2 <= program_counter_1 + 1;
write_enable_2 <= 1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
16'd2:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
16'd3:
begin
result_2 <= register_1;
write_enable_2 <= 1;
end
16'd5:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_output_eth_tx_stb <= 1'b1;
s_output_eth_tx <= register_1;
end
16'd6:
begin
program_counter <= register_1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
16'd7:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_output_socket_stb <= 1'b1;
s_output_socket <= register_1;
end
16'd8:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_input_eth_rx_ack <= 1'b1;
end
16'd9:
begin
result_2 <= 0;
result_2[0] <= input_eth_rx_stb;
write_enable_2 <= 1;
end
16'd10:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_input_socket_ack <= 1'b1;
end
16'd11:
begin
result_2 <= $unsigned(register_1) + $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd12:
begin
result_2 <= $unsigned(register_1) & $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd13:
begin
if (register_1 == 0) begin
program_counter <= literal_1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
end
16'd14:
begin
result_2 <= $unsigned(register_1) + $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd15:
begin
program_counter <= literal_1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
16'd16:
begin
result_2 <= ~register_1;
write_enable_2 <= 1;
end
16'd17:
begin
address_2 <= register_1;
end
16'd19:
begin
result_2 <= data_out_2;
write_enable_2 <= 1;
end
16'd20:
begin
result_2 <= $unsigned(register_1) < $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd21:
begin
result_2 <= $unsigned(register_1) != $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd22:
begin
if (register_1 != 0) begin
program_counter <= literal_1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
end
16'd23:
begin
address_2 <= register_1;
data_in_2 <= registerb_1;
memory_enable_2 <= 1'b1;
end
16'd24:
begin
$display ("%d (report at line: 107 in file: /net/sendai/data3/Coding/ba/Chips-Demo/source/server.h)", $unsigned(register_1));
end
16'd25:
begin
result_2 <= $unsigned(register_1) == $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd26:
begin
result_2 <= $unsigned(register_1) != $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd27:
begin
result_2 <= $signed(register_1) + $signed(registerb_1);
write_enable_2 <= 1;
end
16'd28:
begin
result_2 <= $unsigned(register_1) < $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd29:
begin
result_2 <= $unsigned(register_1) == $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd30:
begin
result_2 <= $unsigned(literal_1) | $unsigned(register_1);
write_enable_2 <= 1;
end
16'd31:
begin
result_2 <= $unsigned(register_1) <= $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd32:
begin
result_2 <= $unsigned(register_1) >> $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd33:
begin
result_2 <= $unsigned(register_1) << $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd34:
begin
result_2 <= $unsigned(register_1) - $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd35:
begin
result_2 <= $unsigned(register_1) - $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd36:
begin
result_2 <= $unsigned(register_1) <= $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd37:
begin
result_2 <= $unsigned(register_1) | $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd38:
begin
result_2 <= 0;
result_2[0] <= input_socket_stb;
write_enable_2 <= 1;
end
16'd39:
begin
result_2 <= $signed(register_1) == $signed(literal_1);
write_enable_2 <= 1;
end
16'd40:
begin
timer <= register_1;
timer_enable <= 1;
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
endcase
end
if (s_output_eth_tx_stb == 1'b1 && output_eth_tx_ack == 1'b1) begin
s_output_eth_tx_stb <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (s_output_socket_stb == 1'b1 && output_socket_ack == 1'b1) begin
s_output_socket_stb <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (s_input_eth_rx_ack == 1'b1 && input_eth_rx_stb == 1'b1) begin
result_2 <= input_eth_rx;
write_enable_2 <= 1;
s_input_eth_rx_ack <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (s_input_socket_ack == 1'b1 && input_socket_stb == 1'b1) begin
result_2 <= input_socket;
write_enable_2 <= 1;
s_input_socket_ack <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (timer == 0) begin
if (timer_enable) begin
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
timer_enable <= 0;
end
end else begin
timer <= timer - 1;
end
if (rst == 1'b1) begin
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
timer <= 0;
timer_enable <= 0;
program_counter <= 0;
s_input_eth_rx_ack <= 0;
s_input_socket_ack <= 0;
s_output_socket_stb <= 0;
s_output_eth_tx_stb <= 0;
end
end
assign input_eth_rx_ack = s_input_eth_rx_ack;
assign input_socket_ack = s_input_socket_ack;
assign output_socket_stb = s_output_socket_stb;
assign output_socket = s_output_socket;
assign output_eth_tx_stb = s_output_eth_tx_stb;
assign output_eth_tx = s_output_eth_tx;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O211A_FUNCTIONAL_V
`define SKY130_FD_SC_HS__O211A_FUNCTIONAL_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o211a (
VPWR,
VGND,
X ,
A1 ,
A2 ,
B1 ,
C1
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
// Local signals
wire C1 or0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , or0_out, B1, C1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O211A_FUNCTIONAL_V |
// Check that the signedness of class properties are handled correctly when
// accessing the property in a class method.
module test;
bit failed = 1'b0;
`define check(x) \
if (!(x)) begin \
$display("FAILED: ", `"x`", `__LINE__); \
failed = 1'b1; \
end
int unsigned x = 10;
int y = 10;
int z;
class C;
shortint s = -1;
bit [15:0] u = -1;
task test;
// These all evaluate as signed
`check(s < 0)
`check($signed(u) < 0)
// These all evaluate as unsigned
`check(u > 0)
`check({s} > 0)
`check($unsigned(s) > 0)
`check(s > 16'h0)
// In arithmetic expressions if one operand is unsigned all operands are
// considered unsigned
z = u + x;
`check(z === 65545)
z = u + y;
`check(z === 65545)
z = s + x;
`check(z === 65545)
z = s + y;
`check(z === 9)
// For ternary operators if one operand is unsigned the result is unsigend
z = x ? u : x;
`check(z === 65535)
z = x ? u : y;
`check(z === 65535)
z = x ? s : x;
`check(z === 65535)
z = x ? s : y;
`check(z === -1)
if (!failed) begin
$display("PASSED");
end
endtask
endclass
C c;
initial begin
c = new;
c.test();
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR4_SYMBOL_V
`define SKY130_FD_SC_LS__OR4_SYMBOL_V
/**
* or4: 4-input OR.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__or4 (
//# {{data|Data Signals}}
input A,
input B,
input C,
input D,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR4_SYMBOL_V
|
/*************************************************************************************
date:2016/7/25
designer:ZhaiShaoMin
module name:tb_core_ras
module function:find out errors in the core_RAS
*************************************************************************************/
`timescale 1ns/1ps
`include"define.v"
module tb_core_pc();
//input
reg clk;
reg rst;
reg [31:0] btb_target;
reg [31:0] ras_target;
reg id_pc_src;
reg stall;
reg pc_go;
reg [31:0] good_target;
reg [1:0] btb_type;
reg btb_v;
//output
wire [31:0] pc_out;
wire v_pc_out;
wire [31:0] pc_plus4;
core_pc duv(//input
.clk(clk),
.rst(rst),
.btb_target(btb_target),
.ras_target(ras_target),
.pc_go(pc_go),//pipeline is not stall
.stall(stall),
// from id module
.good_target(good_target), // target from decode stage, correct target
.id_pc_src(id_pc_src), // if 1 ,meaning pc scoure is from decode ,0,otherwise
// from BTB module
.btb_v(btb_v),
.btb_type(btb_type),
//output
.pc_out(pc_out),
.v_pc_out(v_pc_out),
.pc_plus4(pc_plus4)
);
//initial inputs
initial begin
clk=1'b0;
rst=1'b1;
btb_target=32'hffffffff;
ras_target=32'h11111111;
pc_go=1'b0;
stall=1'b0;
good_target=32'h88888888;
id_pc_src=1'b0;
btb_v=1'b0;
btb_type=2'b11;
end
// para used in btb
parameter br_type=2'b00;
parameter j_type=2'b01;
parameter jal_type=2'b10;
parameter jr_type=2'b11;
always #5 clk=~clk;
integer log_file;
`define clk_step #10;
`define record_log 1
initial begin
log_file = $fopen("core_pc_tf.txt");
////////////////////////begin test//////////////////////////
`clk_step
rst=1'b0;
`clk_step
/////case 1: if rst is set to 1, then pc should be set to 32'h00040000;
rst=1'b1;
`clk_step
`ifdef record_log
$display( "(%t) we should get rst_pc. Got 0x%x. Expected 32'h00040000", $time, pc_out);
$fdisplay(log_file, "(%t) we should get rst_pc. Got 0x%x. Expected 32'h00040000", $time, pc_out);
`endif
/////// case 2.1: if rst==0&& pc_go stall pc_go&&!stall what it means
/////// 0 0 0 inst cache not hits, pipeline is busy.
rst=1'b0;
pc_go=1'b0;
stall=1'b0;
`clk_step
`ifdef record_log
$display( "(%t) pc_out should not be changed. Got 0x%x. Expected 32'h00040000", $time, pc_out);
$fdisplay(log_file, "(%t) pc_out should not be changed. Got 0x%x. Expected 32'h00040000", $time, pc_out);
`endif
/////// case 2.2: if rst==0&& pc_go stall pc_go&&!stall what it means
///////// 0 1 0 inst cache not hits, pipeline is stall.
rst=1'b0;
pc_go=1'b0;
stall=1'b1;
`clk_step
`ifdef record_log
$display( "(%t) pc_out should not be changed. Got 0x%x. Expected 32'h00040000", $time, pc_out);
$fdisplay(log_file, "(%t) pc_out should not be changed. Got 0x%x. Expected 32'h00040000", $time, pc_out);
`endif
/////// case 2.3: if rst==0&& pc_go stall pc_go&&!stall what it means
///////// 1 1 0 inst cache hits, pipeline is busy.
rst=1'b0;
pc_go=1'b1;
stall=1'b1;
`clk_step
`ifdef record_log
$display( "(%t) pc_out should not be changed. Got 0x%x. Expected 32'h00040000", $time, pc_out);
$fdisplay(log_file, "(%t) pc_out should not be changed. Got 0x%x. Expected 32'h00040000", $time, pc_out);
`endif
/////// case 2.4: if rst==0&& pc_go stall pc_go&&!stall what it means
/////// 1 0 1 inst cache hits, pipeline is busy.
//
// case 2-1-0: if id_pc_src==1,then pc is set to good_target;
rst=1'b0;
pc_go=1'b1;
stall=1'b0;
id_pc_src=1'b1;
good_target=32'h20168010;
`clk_step
`ifdef record_log
$display( "(%t) pc_out should be changed . Got 0x%x. Expected 32'h20168010", $time, pc_out);
$fdisplay(log_file, "(%t) pc_out should be changed. Got 0x%x. Expected 32'h20168010", $time, pc_out);
`endif
// case 2-1-1: if btb_v==0&&id_pc_src==0, then pc is set to pc_plus4;
rst=1'b0;
pc_go=1'b1;
stall=1'b0;
id_pc_src=1'b0;
good_target=32'h20168010;
btb_v=1'b0;
`clk_step
`ifdef record_log
$display( "(%t) pc_out should be changed . Got 0x%x. Expected 32'h20168014", $time, pc_out);
$fdisplay(log_file, "(%t) pc_out should be changed. Got 0x%x. Expected 32'h20168014", $time, pc_out);
`endif
// case 2-1-2: if btb_v==1&&id_pc_src==0&&btb_type==jr_type, then pc is set to RAS_target;
rst=1'b0;
pc_go=1'b1;
stall=1'b0;
id_pc_src=1'b0;
good_target=32'h20168010;
ras_target=32'h24241010;
btb_v=1'b1;
btb_type=`jr_type;
`clk_step
`ifdef record_log
$display( "(%t) pc_out should be changed . Got 0x%x. Expected 32'h24241010", $time, pc_out);
$fdisplay(log_file, "(%t) pc_out should be changed. Got 0x%x. Expected 32'h24241010", $time, pc_out);
`endif
// case 2-1-3: if btb_v==1&&id_pc_src==0&&(btb_type==br_type||
// btb_type==j_type||
// btb_type==jal_type),then pc is set to btb_target.
//////btb_type==j_type
rst=1'b0;
pc_go=1'b1;
stall=1'b0;
id_pc_src=1'b0;
good_target=32'h20168010;
ras_target=32'h24241010;
btb_target=32'h22228888;
btb_v=1'b1;
btb_type=`j_type;
`clk_step
`ifdef record_log
$display( "(%t) pc_out should be changed . Got 0x%x. Expected 32'h22228888", $time, pc_out);
$fdisplay(log_file, "(%t) pc_out should be changed. Got 0x%x. Expected 32'h22228888", $time, pc_out);
`endif
/////btb_type==jal_type
rst=1'b0;
pc_go=1'b1;
stall=1'b0;
id_pc_src=1'b0;
good_target=32'h20168010;
ras_target=32'h24241010;
btb_target=32'h22448888;
btb_v=1'b1;
btb_type=`jal_type;
`clk_step
`ifdef record_log
$display( "(%t) pc_out should be changed . Got 0x%x. Expected 32'h22448888", $time, pc_out);
$fdisplay(log_file, "(%t) pc_out should be changed. Got 0x%x. Expected 32'h22448888", $time, pc_out);
`endif
/////btb_type==br_type
rst=1'b0;
pc_go=1'b1;
stall=1'b0;
id_pc_src=1'b0;
good_target=32'h20168010;
ras_target=32'h24241010;
btb_target=32'h22446688;
btb_v=1'b1;
btb_type=`br_type;
`clk_step
`ifdef record_log
$display( "(%t) pc_out should be changed . Got 0x%x. Expected 32'h22446688", $time, pc_out);
$fdisplay(log_file, "(%t) pc_out should be changed. Got 0x%x. Expected 32'h22446688", $time, pc_out);
`endif
$stop;
end
endmodule |
module Sec5_SM(
input DigitalLDir,
input DigitalRDir,
input clk_i,
input reset_n,
output reg [3:0] outputs
// output reg Len,
// output reg Ldir,
// output reg Ren,
// output reg Rdir
);
reg [2:0] state;
reg [2:0] state_next;
parameter S0 = 3'b000; //Moving forward
parameter S1 = 3'b001; //Moving backward (right bumper)
parameter S2 = 3'b010; //Moving backward (right bumper)
parameter S3 = 3'b011; //Spinning left (right bumper)
parameter S4 = 3'b100; //Moving backward (left bumper)
parameter S5 = 3'b101; //Moving backward (left bumper)
parameter S6 = 3'b110; //Spinning right (left bumper)
//Async reset
always @ (posedge clk_i, negedge reset_n)
begin
if(!reset_n)
state <= S0;
else
state <= state_next;
end
//Next state logic
always @ (*)
begin
case(state)
S0:
begin
if( !DigitalLDir ) state_next <= S4;
else if( !DigitalRDir ) state_next <= S1;
else state_next <= S0;
end
S1: state_next = S2;
S2: state_next = S3;
S3: state_next = S0;
S4: state_next = S5;
S5: state_next = S6;
S6: state_next = S0;
default: state_next = S0;
endcase
end
//Output status logic
always @ (*)
begin
case (state)
S0:
begin
outputs = 4'b0101;
// Len <= 0; Ldir <= 1; Ren <= 0; Rdir <= 1;
end
S1:
begin
outputs = 4'b0000;
// Len <= 0; Ldir <= 0; Ren <= 0; Rdir <= 0;
end
S2:
begin
outputs = 4'b0000;
// Len <= 0; Ldir <= 1; Ren <= 0; Rdir <= 0;
end
S3:
begin
outputs = 4'b0100;
// Len <= 0; Ldir <= 1; Ren <= 0; Rdir <= 0;
end
S4:
begin
outputs = 4'b0000;
// Len <= 0; Ldir <= 0; Ren <= 0; Rdir <= 0;
end
S5:
begin
outputs = 4'b0000;
// Len <= 0; Ldir <= 0; Ren <= 0; Rdir <= 1;
end
S6:
begin
outputs = 4'b0001;
// Len <= 0; Ldir <= 0; Ren <= 0; Rdir <= 1;
end
default:
begin
outputs = 4'b0101;
end
endcase
end
endmodule
/*
module mux2(
input d0,
input d1,
input s,
output y);
assign y = (s) ? d1 : d0;
endmodule
module inv (input A,
output Z);
assign Z = ~A;
endmodule
*/ |
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